IP Core Library - Published and maintained by the Chair for VLSI Design, Diagnostics and Architecture, Faculty of Computer Science, Technische Universität Dresden, Germany
Clone or download
Paebbels Merge pull request #61 from FranzForstmayr/dev/ite_signed
Overloaded function `ite` for `signed` datatype.
Latest commit f56b6f1 Sep 24, 2018
Permalink
Type Name Latest commit message Commit time
Failed to load latest commit information.
.github Move CONTRIBUTING files according to GitHubs template rules. May 27, 2018
.gitlab Added Sphinx RTFD theme. May 17, 2018
.pyIPCMI Moved IP Core database files. May 27, 2018
docs Revert "Added build requirements.txt" Aug 9, 2018
lib Submodule update (due to merge into master branch). Jun 18, 2018
netlist Implemented configuration routines for Aldec and Lattice products. Up… Apr 28, 2016
py/.idea Added GitLab-CI configuration file. May 27, 2018
sim A lot of new stuff. May 6, 2018
src Overloaded ite for signed datatype Sep 24, 2018
tb A lot of new stuff. May 6, 2018
tcl Fixed copyright line. Nov 10, 2016
temp Added temp\precompiled directory. May 23, 2017
tools Removed debug switch from compile-osvvm.sh call. Jun 17, 2018
ucf Merge remote-tracking branch 'gitlab/release' into 'master'. Jun 18, 2018
xst Explicit instantiation of I/O buffers to support netlisting. Minor fi… Dec 21, 2016
.appveyor.yml Implemented new 'info' command in PoC. Dec 15, 2016
.editorconfig Added editorconfig description file. Jun 17, 2018
.gitattributes Updated Python infrastructure, documentation and pre-compile scripts.… Oct 28, 2016
.gitignore Updated .gitignore Aug 3, 2018
.gitlab-ci.yml Change Git submodule strategy. Jun 3, 2018
.gitmodules Updated UVVM URL from 'UVVM_All.git 'to 'UVVM.git'. Jun 3, 2018
.landscape.yml Changed Landscape.io settings back (part 1). Nov 17, 2016
.readthedocs.yml Disabled PDF rendering until SphinxContrib.TextStyle gets fixed. Nov 21, 2016
.travis.yml Updated GHDL to 0.35. Trying new settings for Travis-CI. May 6, 2018
AUTHORS.md Reworked vendor library pre-compile scripts. Added top-level generics… Jul 15, 2016
CHANGES.md First content example for RTFD. May 16, 2016
LICENSE.md Added a *.files file for each IP core. Updated Python infrastructure. Apr 18, 2016
README.md Fixed modelsim.ini file not found issue. Feb 3, 2017
README.tpl Fixed modelsim.ini file not found issue. Feb 3, 2017
poc.ps1 Step 1 in fixing Bash scripts for Linux. Jun 3, 2018
poc.sh Step 1 in fixing Bash scripts for Linux. Jun 3, 2018
requirements.txt Implemented dryrun feature. Added first dryrun tests to AppVeyor. Imp… Dec 15, 2016
vhdl_coding.md Added new constraint files for Digulent Arty and Digilent Arty S7 boa… May 27, 2018

README.md

The PoC-Library

Build Status by Travis-CI Build status by AppVeyor Documentation Status Python Infrastructure tested by Landscape.io Requirements Status
Join the chat at https://gitter.im/VLSI-EDA/PoC Subscribe for news at https://gitter.im/VLSI-EDA/News
Latest tag Latest release Apache License 2.0

This library is published and maintained by Chair for VLSI Design, Diagnostics and Architecture - Faculty of Computer Science, Technische Universität Dresden, Germany http://vlsi-eda.inf.tu-dresden.de

Technische Universität Dresden

Table of Content:

  1. Overview
  2. Quick Start Guide
    2.1. Requirements and Dependencies
    2.2. Download
    2.3. Configuring PoC on a Local System
    2.4. Integration
    2.5. Updating
  3. Common Notes
  4. Cite the PoC-Library

1 Overview

PoC - “Pile of Cores” provides implementations for often required hardware functions such as Arithmetic Units, Caches, Clock-Domain-Crossing Circuits, FIFOs, RAM wrappers, and I/O Controllers. The hardware modules are typically provided as VHDL or Verilog source code, so it can be easily re-used in a variety of hardware designs.

All hardware modules use a common set of VHDL packages to share new VHDL types, sub-programs and constants. Additionally, a set of simulation helper packages eases the writing of testbenches. Because PoC hosts a huge amount of IP cores, all cores are grouped into sub-namespaces to build a clear hierachy.

Various simulation and synthesis tool chains are supported to interoperate with PoC. To generalize all supported free and commercial vendor tool chains, PoC is shipped with a Python based infrastructure to offer a command line based frontend.

2 Quick Start Guide

This Quick Start Guide gives a fast and simple introduction into PoC. All topics can be found in the Using PoC section at ReadTheDocs.io with much more details and examples.

2.1 Requirements and Dependencies

The PoC-Library comes with some scripts to ease most of the common tasks, like running testbenches or generating IP cores. PoC uses Python 3 as a platform independent scripting environment. All Python scripts are wrapped in Bash or PowerShell scripts, to hide some platform specifics of Darwin, Linux or Windows. See Requirements for further details.

PoC requires:

  • A supported synthesis tool chain, if you want to synthezise IP cores.
  • A supported simulator tool chain, if you want to simulate IP cores.
  • The Python 3 programming language and runtime, if you want to use PoC's infrastructure.
  • A shell to execute shell scripts:
    • Bash on Linux and OS X
    • PowerShell on Windows

PoC optionally requires:

  • Git command line tools or
  • Git User Interface, if you want to check out the latest 'master' or 'release' branch.

PoC depends on third part libraries:

  • Cocotb
    A coroutine based cosimulation library for writing VHDL and Verilog testbenches in Python.
  • OS-VVM
    Open Source VHDL Verification Methodology.
  • UVVM
    Universal VHDL Verification Methodology.
  • VUnit
    An unit testing framework for VHDL.

All dependencies are available as GitHub repositories and are linked to PoC as Git submodules into the PoCRoot\lib directory. See Third Party Libraries for more details on these libraries.

2.2 Download

The PoC-Library can be downloaded as a zip-file (latest 'release' branch), cloned with git clone or embedded with git submodule add from GitHub. GitHub offers HTTPS and SSH as transfer protocols. See the Download page for further details. The installation directory is referred to as PoCRoot.

Protocol Git Clone Command
HTTPS git clone --recursive https://github.com/VLSI-EDA/PoC.git PoC
SSH git clone --recursive ssh://git@github.com:VLSI-EDA/PoC.git PoC

2.3 Configuring PoC on a Local System

To explore PoC's full potential, it's required to configure some paths and synthesis or simulation tool chains. The following commands start a guided configuration process. Please follow the instructions on screen. It's possible to relaunch the process at any time, for example to register new tools or to update tool versions. See Configuration for more details. Run the following command line instructions to configure PoC on your local system:

cd PoCRoot
.\poc.ps1 configure

Use the keyboard buttons: Y to accept, N to decline, P to skip/pass a step and Return to accept a default value displayed in brackets.

2.4 Integration

The PoC-Library is meant to be integrated into other HDL projects. Therefore it's recommended to create a library folder and add the PoC-Library as a Git submodule. After the repository linking is done, some short configuration steps are required to setup paths, tool chains and the target platform. The following command line instructions show a short example on how to integrate PoC.

a) Adding the Library as a Git submodule

The following command line instructions will create the folder lib\PoC\ and clone the PoC-Library as a Git submodule into that folder. ProjectRoot is the directory of the hosting Git. A detailed list of steps can be found at Integration.

cd ProjectRoot
mkdir lib | cd
git submodule add https://github.com:VLSI-EDA/PoC.git PoC
cd PoC
git remote rename origin github
cd ..\..
git add .gitmodules lib\PoC
git commit -m "Added new git submodule PoC in 'lib\PoC' (PoC-Library)."

b) Configuring PoC

The PoC-Library should be configured to explore its full potential. See Configuration for more details. The following command lines will start the configuration process:

cd ProjectRoot
.\lib\PoC\poc.ps1 configure

c) Creating PoC's my_config.vhdl and my_project.vhdl Files

The PoC-Library needs two VHDL files for its configuration. These files are used to determine the most suitable implementation depending on the provided target information. Copy the following two template files into your project's source folder. Rename these files to *.vhdl and configure the VHDL constants in the files:

cd ProjectRoot
cp lib\PoC\src\common\my_config.vhdl.template src\common\my_config.vhdl
cp lib\PoC\src\common\my_project.vhdl.template src\common\my_project.vhdl

my_config.vhdl defines two global constants, which need to be adjusted:

constant MY_BOARD            : string := "CHANGE THIS"; -- e.g. Custom, ML505, KC705, Atlys
constant MY_DEVICE           : string := "CHANGE THIS"; -- e.g. None, XC5VLX50T-1FF1136, EP2SGX90FF1508C3

my_project.vhdl also defines two global constants, which need to be adjusted:

constant MY_PROJECT_DIR      : string := "CHANGE THIS"; -- e.g. d:/vhdl/myproject/, /home/me/projects/myproject/"
constant MY_OPERATING_SYSTEM : string := "CHANGE THIS"; -- e.g. WINDOWS, LINUX

Further informations are provided at Creating my_config/my_project.vhdl.

d) Adding PoC's Common Packages to a Synthesis or Simulation Project

PoC is shipped with a set of common packages, which are used by most of its modules. These packages are stored in the PoCRoot\src\common directory. PoC also provides a VHDL context in common.vhdl , which can be used to reference all packages at once.

e) Adding PoC's Simulation Packages to a Simulation Project

Simulation projects additionally require PoC's simulation helper packages, which are located in the PoCRoot\src\sim directory. Because some VHDL version are incompatible among each other, PoC uses version suffixes like *.v93.vhdl or *.v08.vhdl in the file name to denote the supported VHDL version of a file.

f) Compiling Shipped IP Cores

Some IP Cores are shipped as pre-configured vendor IP Cores. If such IP cores shall be used in a HDL project, it's recommended to use PoC to create, compile and if needed patch these IP cores. See Synthesis for more details.

2.5 Updating

The PoC-Library can be updated by using git fetch and git merge.

cd PoCRoot
# update the local repository
git fetch --prune
# review the commit tree and messages, using the 'treea' alias
git treea
# if all changes are OK, do a fast-forward merge
git merge

See also:

3. Common Notes

The PoC-Library is structured into several sub-folders naming the purpose of the folder like src for sources files or tb for testbench files. The structure within these folders is always the same and based on PoC's sub-namespace tree.

Main directory overview:

  • lib - Embedded or linked external libraries.
  • netlist - Configuration files and output directory for pre-configured netlist synthesis results from vendor IP cores or from complex PoC controllers.
  • py - Supporting Python scripts.
  • sim - Pre-configured waveform views for selected testbenches.
  • src - PoC's source files grouped into sub-folders according to the sub-namespace tree.
  • tb - Testbench files.
  • tcl - Tcl files.
  • temp - Automatically created temporary directors for various tools used by PoC's Python scripts.
  • tools - Settings/highlighting files and helpers for supported tools.
  • ucf - Pre-configured constraint files (*.ucf, *.xdc, *.sdc) for supported FPGA boards.
  • xst - Configuration files to synthesize PoC modules with Xilinx XST into a netlist.

All VHDL source files should be compiled into the VHDL library PoC. If not indicated otherwise, all source files can be compiled using the VHDL-93 or VHDL-2008 language version. Incompatible files are named *.v93.vhdl and *.v08.vhdl to denote the highest supported language version.

4 Cite the PoC-Library

If you are using the PoC-Library, please let us know. We are grateful for your project's reference. The PoC-Library hosted at GitHub.com. Please use the following biblatex entry to cite us:

# BibLaTex example entry
@online{poc,
  title={{PoC - Pile of Cores}},
  author={{Chair of VLSI Design, Diagnostics and Architecture}},
  organization={{Technische Universität Dresden}},
  year={2016},
  url={https://github.com/VLSI-EDA/PoC},
  urldate={2016-10-28},
}