diff --git a/py/Simulator/ModelSimSimulator.py b/py/Simulator/ModelSimSimulator.py index 79ee75c4..45dd3c0e 100644 --- a/py/Simulator/ModelSimSimulator.py +++ b/py/Simulator/ModelSimSimulator.py @@ -101,7 +101,7 @@ def Run(self, testbench, board, vhdlVersion, vhdlGenerics=None): super().Run(testbench, board, vhdlVersion, vhdlGenerics) def _RunAnalysis(self, _): - # create a ModelSimVHDLCompiler instance + # create a VHDLCompiler instance vlib = self._toolChain.GetVHDLLibraryTool() for lib in self._pocProject.VHDLLibraries: vlib.Parameters[vlib.SwitchLibraryName] = lib.Name @@ -110,7 +110,7 @@ def _RunAnalysis(self, _): except DryRunException: pass - # create a ModelSimVHDLCompiler instance + # create a VHDLCompiler instance vcom = self._toolChain.GetVHDLCompiler() vcom.Parameters[vcom.FlagQuietMode] = True vcom.Parameters[vcom.FlagExplicit] = True @@ -174,7 +174,7 @@ def _RunSimulation(self, testbench): tclBatchFilePath = self.Host.Directories.Root / self.Host.PoCConfig[testbench.ConfigSectionName]['vSimBatchScript'] tclDefaultBatchFilePath = self.Host.Directories.Root / self.Host.PoCConfig[testbench.ConfigSectionName]['vSimDefaultBatchScript'] - # create a ModelSimSimulator instance + # create a VHDLSimulator instance vsim = self._toolChain.GetSimulator() vsim.Parameters[vsim.SwitchModelSimIniFile] = self._modelsimIniPath.as_posix() # vsim.Parameters[vsim.FlagOptimization] = True # FIXME: @@ -212,7 +212,7 @@ def _RunSimulationWithGUI(self, testbench): tclDefaultGUIFilePath = self.Host.Directories.Root / self.Host.PoCConfig[testbench.ConfigSectionName]['vSimDefaultGUIScript'] tclDefaultWaveFilePath = self.Host.Directories.Root / self.Host.PoCConfig[testbench.ConfigSectionName]['vSimDefaultWaveScript'] - # create a ModelSimSimulator instance + # create a VHDLSimulator instance vsim = self._toolChain.GetSimulator() vsim.Parameters[vsim.SwitchModelSimIniFile] = self._modelsimIniPath.as_posix() # vsim.Parameters[vsim.FlagOptimization] = True # FIXME: diff --git a/py/Simulator/QuestaSimulator.py b/py/Simulator/QuestaSimulator.py index 024e7b45..e1a30734 100644 --- a/py/Simulator/QuestaSimulator.py +++ b/py/Simulator/QuestaSimulator.py @@ -101,13 +101,13 @@ def Run(self, testbench, board, vhdlVersion, vhdlGenerics=None): super().Run(testbench, board, vhdlVersion, vhdlGenerics) def _RunAnalysis(self, _): - # create a ModelSimVHDLCompiler instance + # create a VHDLCompiler instance vlib = self._toolChain.GetVHDLLibraryTool() for lib in self._pocProject.VHDLLibraries: vlib.Parameters[vlib.SwitchLibraryName] = lib.Name vlib.CreateLibrary() - # create a ModelSimVHDLCompiler instance + # create a VHDLCompiler instance vcom = self._toolChain.GetVHDLCompiler() vcom.Parameters[vcom.FlagQuietMode] = True vcom.Parameters[vcom.FlagExplicit] = True @@ -171,7 +171,7 @@ def _RunSimulation(self, testbench): tclBatchFilePath = self.Host.Directories.Root / self.Host.PoCConfig[testbench.ConfigSectionName]['vSimBatchScript'] tclDefaultBatchFilePath = self.Host.Directories.Root / self.Host.PoCConfig[testbench.ConfigSectionName]['vSimDefaultBatchScript'] - # create a ModelSimSimulator instance + # create a VHDLSimulator instance vsim = self._toolChain.GetSimulator() vsim.Parameters[vsim.SwitchModelSimIniFile] = self._modelsimIniPath.as_posix() # vsim.Parameters[vsim.FlagOptimization] = True # FIXME: @@ -202,7 +202,7 @@ def _RunSimulationWithGUI(self, testbench): tclDefaultGUIFilePath = self.Host.Directories.Root / self.Host.PoCConfig[testbench.ConfigSectionName]['vSimDefaultGUIScript'] tclDefaultWaveFilePath = self.Host.Directories.Root / self.Host.PoCConfig[testbench.ConfigSectionName]['vSimDefaultWaveScript'] - # create a ModelSimSimulator instance + # create a VHDLSimulator instance vsim = self._toolChain.GetSimulator() vsim.Parameters[vsim.SwitchModelSimIniFile] = self._modelsimIniPath.as_posix() # vsim.Parameters[vsim.FlagOptimization] = True # FIXME: diff --git a/py/ToolChain/Aldec/ActiveHDL.py b/py/ToolChain/Aldec/ActiveHDL.py index e8c6c855..024399b5 100644 --- a/py/ToolChain/Aldec/ActiveHDL.py +++ b/py/ToolChain/Aldec/ActiveHDL.py @@ -49,13 +49,12 @@ 'ActiveHDLEditions', 'Configuration', 'ActiveHDL', + 'VHDLLibraryTool', 'VHDLCompiler', - 'StandaloneSimulator', - 'Simulator', - 'ActiveHDLVHDLLibraryTool', - 'VHDLCompilerFilter', - 'SimulatorFilter', - 'VHDLLibraryToolFilter' + 'VHDLStandaloneSimulator', + 'ActiveHDLVLibFilter', + 'ActiveHDLVComFilter', + 'ActiveHDLVSimFilter' ] __all__ = __api__ @@ -210,7 +209,7 @@ class ActiveHDL(ToolMixIn): """Factory for executable abstractions in Active-HDL.""" def GetVHDLLibraryTool(self): """Return an instance of Active-HDL's VHDL library management tool 'vlib'.""" - return ActiveHDLVHDLLibraryTool(self) + return VHDLLibraryTool(self) def GetVHDLCompiler(self): """Return an instance of Active-HDL's VHDL compiler 'vcom'.""" @@ -218,7 +217,76 @@ def GetVHDLCompiler(self): def GetSimulator(self): """Return an instance of Active-HDL's VHDL simulator 'vsim'.""" - return StandaloneSimulator(self) + return VHDLStandaloneSimulator(self) + + +class VHDLLibraryTool(OutputFilteredExecutable, ToolMixIn): + """Abstraction layer of Active-HDL's VHDL library management tool 'vlib'.""" + + def __init__(self, toolchain: ToolMixIn): + ToolMixIn.__init__( + self, toolchain._platform, toolchain._dryrun, toolchain._binaryDirectoryPath, toolchain._version, + toolchain._logger) + + if (self._platform == "Windows"): + executablePath = self._binaryDirectoryPath / "vlib.exe" + else: + raise PlatformNotSupportedException(self._platform) + super().__init__(self._platform, self._dryrun, executablePath, logger=self._logger) + + self.Parameters[self.Executable] = executablePath + + class Executable(metaclass=ExecutableArgument): + _value = None + + # class FlagVerbose(metaclass=FlagArgument): + # _name = "-v" + # _value = None + + class SwitchLibraryName(metaclass=StringArgument): + _value = None + + Parameters = CommandLineArgumentList( + Executable, + # FlagVerbose, + SwitchLibraryName + ) + + def CreateLibrary(self): + parameterList = self.Parameters.ToArgumentList() + self.LogVerbose("command: {0}".format(" ".join(parameterList))) + + try: + self.StartProcess(parameterList) + except Exception as ex: + raise ActiveHDLException("Failed to launch alib run.") from ex + + self._hasOutput = False + self._hasWarnings = False + self._hasErrors = False + try: + iterator = iter(VLibFilter(self.GetReader())) + line = next(iterator) + + self._hasOutput = True + self.LogNormal(" alib messages for '{0}'".format(self.Parameters[self.SwitchLibraryName])) + self.LogNormal(" " + ("-" * (78 - self.Logger.BaseIndent * 2))) + + while True: + self._hasWarnings |= (line.Severity is Severity.Warning) + self._hasErrors |= (line.Severity is Severity.Error) + + line.IndentBy(self.Logger.BaseIndent + 1) + self.Log(line) + line = next(iterator) + + except DryRunException: + pass + except StopIteration: + pass + finally: + if self._hasOutput: + self.LogNormal(" " + ("-" * (78 - self.Logger.BaseIndent * 2))) class VHDLCompiler(OutputFilteredExecutable, ToolMixIn): @@ -286,7 +354,7 @@ def Compile(self): self._hasWarnings = False self._hasErrors = False try: - iterator = iter(VHDLCompilerFilter(self.GetReader())) + iterator = iter(VComFilter(self.GetReader())) line = next(iterator) @@ -311,7 +379,7 @@ def Compile(self): self.LogNormal(" " + ("-" * (78 - self.Logger.BaseIndent*2))) -class StandaloneSimulator(OutputFilteredExecutable, ToolMixIn): +class VHDLStandaloneSimulator(OutputFilteredExecutable, ToolMixIn): """Abstraction layer of Active-HDL's VHDL standalone simulator 'vsimsa'.""" def __init__(self, toolchain : ToolMixIn): ToolMixIn.__init__( @@ -351,7 +419,7 @@ def Simulate(self): self._hasErrors = False simulationResult = CallByRefParam(SimulationResult.Error) try: - iterator = iter(PoCSimulationResultFilter(SimulatorFilter(self.GetReader()), simulationResult)) + iterator = iter(PoCSimulationResultFilter(VSimFilter(self.GetReader()), simulationResult)) line = next(iterator) self._hasOutput = True @@ -377,157 +445,17 @@ def Simulate(self): return simulationResult.value -class Simulator(Executable, ToolMixIn): - """Abstraction layer of Active-HDL's VHDL simulator 'vsim'.""" - def __init__(self, platform, dryrun, binaryDirectoryPath, version, logger=None): - ToolMixIn.__init__(self, platform, dryrun, binaryDirectoryPath, version, logger=logger) - if (self._platform == "Windows"): executablePath = binaryDirectoryPath / "vsimsa.exe" - # elif (self._platform == "Linux"): executablePath = binaryDirectoryPath / "vsimsa" - else: raise PlatformNotSupportedException(self._platform) - super().__init__(platform, dryrun, executablePath, logger=logger) - - self.Parameters[self.Executable] = executablePath - - class Executable(metaclass=ExecutableArgument): - _value = None - - # class FlagVerbose(metaclass=ShortFlagArgument): - # _name = "v" - # _value = None - # - # class FlagOptimization(metaclass=ShortFlagArgument): - # _name = "vopt" - # _value = None - # - # class FlagCommandLineMode(metaclass=ShortFlagArgument): - # _name = "c" - # _value = None - # - # class SwitchTimeResolution(metaclass=ShortTupleArgument): - # _name = "t" - # _value = None - - class SwitchBatchCommand(metaclass=ShortTupleArgument): - _name = "do" - - # class SwitchTopLevel(metaclass=ShortValuedFlagArgument): - # _name = "" - # _value = None - - Parameters = CommandLineArgumentList( - Executable, - # FlagVerbose, - # FlagOptimization, - # FlagCommandLineMode, - # SwitchTimeResolution, - SwitchBatchCommand - # SwitchTopLevel - ) - - # units = ("fs", "ps", "us", "ms", "sec", "min", "hr") - - def Simulate(self): - parameterList = self.Parameters.ToArgumentList() - - self.LogVerbose("command: {0}".format(" ".join(parameterList))) - self.LogDebug("tcl commands: {0}".format(self.Parameters[self.SwitchBatchCommand])) - - _indent = " " - print(_indent + "vsimsa messages for '{0}.{1}'".format("??????", "??????")) # self.VHDLLibrary, topLevel)) - print(_indent + "-" * 80) - try: - self.StartProcess(parameterList) - for line in self.GetReader(): - print(_indent + line) - except Exception as ex: - raise ex # SimulatorException() from ex - print(_indent + "-" * 80) - - -class ActiveHDLVHDLLibraryTool(OutputFilteredExecutable, ToolMixIn): - """Abstraction layer of Active-HDL's VHDL library management tool 'vlib'.""" - def __init__(self, toolchain : ToolMixIn): - ToolMixIn.__init__( - self, toolchain._platform, toolchain._dryrun, toolchain._binaryDirectoryPath, toolchain._version, - toolchain._logger) - - if (self._platform == "Windows"): executablePath = self._binaryDirectoryPath / "vlib.exe" - else: raise PlatformNotSupportedException(self._platform) - super().__init__(self._platform, self._dryrun, executablePath, logger=self._logger) - - self.Parameters[self.Executable] = executablePath - - class Executable(metaclass=ExecutableArgument): - _value = None - - # class FlagVerbose(metaclass=FlagArgument): - # _name = "-v" - # _value = None - - class SwitchLibraryName(metaclass=StringArgument): - _value = None - - Parameters = CommandLineArgumentList( - Executable, - # FlagVerbose, - SwitchLibraryName - ) - - def CreateLibrary(self): - parameterList = self.Parameters.ToArgumentList() - self.LogVerbose("command: {0}".format(" ".join(parameterList))) - - try: - self.StartProcess(parameterList) - except Exception as ex: - raise ActiveHDLException("Failed to launch alib run.") from ex - - self._hasOutput = False - self._hasWarnings = False - self._hasErrors = False - try: - iterator = iter(VHDLLibraryToolFilter(self.GetReader())) - line = next(iterator) - - self._hasOutput = True - self.LogNormal(" alib messages for '{0}'".format(self.Parameters[self.SwitchLibraryName])) - self.LogNormal(" " + ("-" * (78 - self.Logger.BaseIndent*2))) - - while True: - self._hasWarnings |= (line.Severity is Severity.Warning) - self._hasErrors |= (line.Severity is Severity.Error) - - line.IndentBy(self.Logger.BaseIndent + 1) - self.Log(line) - line = next(iterator) - - except DryRunException: - pass - except StopIteration: - pass - finally: - if self._hasOutput: - self.LogNormal(" " + ("-" * (78 - self.Logger.BaseIndent*2))) - +def VLibFilter(gen): + """A line based output stream filter for Active-HDL's VHDL library management + tool. + """ + for line in gen: + if line.startswith("ALIB: Library "): + yield LogEntry(line, Severity.Verbose) + else: + yield LogEntry(line, Severity.Normal) - # # assemble acom command as list of parameters - # parameterList = [ - # str(aComExecutablePath), - # '-O3', - # '-relax', - # '-l', 'acom.log', - # vhdlStandard, - # '-work', vhdlLibraryName, - # str(vhdlFilePath) - # ] - # parameterList = [ - # str(aSimExecutablePath)#, - # # '-vopt', - # # '-t', '1fs', - # ] - - -def VHDLCompilerFilter(gen): # mccabe:disable=MC0001 +def VComFilter(gen): # mccabe:disable=MC0001 """A line based output stream filter for Active-HDL's VHDL compiler.""" for line in gen: if line.startswith("Aldec, Inc. VHDL Compiler"): @@ -561,8 +489,7 @@ def VHDLCompilerFilter(gen): # mccabe:disable=MC0001 else: yield LogEntry(line, Severity.Normal) - -def SimulatorFilter(gen): +def VSimFilter(gen): """A line based output stream filter for Active-HDL's VHDL simulator.""" PoCOutputFound = False for line in gen: @@ -590,13 +517,3 @@ def SimulatorFilter(gen): yield LogEntry(line[8:], Severity.Normal) else: yield LogEntry(line, Severity.Normal) - -def VHDLLibraryToolFilter(gen): - """A line based output stream filter for Active-HDL's VHDL library management - tool. - """ - for line in gen: - if line.startswith("ALIB: Library "): - yield LogEntry(line, Severity.Verbose) - else: - yield LogEntry(line, Severity.Normal) diff --git a/py/ToolChain/Aldec/RivieraPRO.py b/py/ToolChain/Aldec/RivieraPRO.py index 7d19bc2f..e951d94c 100644 --- a/py/ToolChain/Aldec/RivieraPRO.py +++ b/py/ToolChain/Aldec/RivieraPRO.py @@ -44,13 +44,12 @@ 'RivieraPROException', 'Configuration', 'RivieraPRO', + 'VHDLLibraryTool', 'VHDLCompiler', - 'StandaloneSimulator', - 'Simulator', - 'RivieraPROVHDLLibraryTool', - 'VHDLCompilerFilter', - 'SimulatorFilter', - 'VHDLLibraryToolFilter' + 'VHDLSimulator', + 'RivieraPROVLibFilter', + 'RivieraPROVComFilter', + 'RivieraPROVSimFilter' ] __all__ = __api__ @@ -145,7 +144,7 @@ class RivieraPRO(ToolMixIn): """Factory for executable abstractions in Riviera-PRO.""" def GetVHDLLibraryTool(self): """Return an instance of Riviera-PRO's VHDL library management tool 'vlib'.""" - return RivieraPROVHDLLibraryTool(self) + return VHDLLibraryTool(self) def GetVHDLCompiler(self): """Return an instance of Riviera-PRO's VHDL compiler 'vcom'.""" @@ -156,15 +155,16 @@ def GetSimulator(self): return VHDLSimulator(self) -class RivieraPROVHDLLibraryTool(OutputFilteredExecutable, ToolMixIn): +class VHDLLibraryTool(OutputFilteredExecutable, ToolMixIn): """Abstraction layer of Riviera-PRO's VHDL library management tool 'vlib'.""" def __init__(self, toolchain : ToolMixIn): ToolMixIn.__init__( self, toolchain._platform, toolchain._dryrun, toolchain._binaryDirectoryPath, toolchain._version, toolchain._logger) - if (self._platform == "Windows"): executablePath = self._binaryDirectoryPath / "vlib.exe" - else: raise PlatformNotSupportedException(self._platform) + if (self._platform == "Windows"): executablePath = self._binaryDirectoryPath / "vlib.exe" + elif (self._platform == "Linux"): executablePath = self._binaryDirectoryPath / "vlib" + else: raise PlatformNotSupportedException(self._platform) super().__init__(self._platform, self._dryrun, executablePath, logger=self._logger) self.Parameters[self.Executable] = executablePath @@ -189,11 +189,11 @@ def CreateLibrary(self): except Exception as ex: raise RivieraPROException("Failed to launch alib run.") from ex - self._hasOutput = False + self._hasOutput = False self._hasWarnings = False - self._hasErrors = False + self._hasErrors = False try: - iterator = iter(RivieraPROVLibFilter(self.GetReader())) + iterator = iter(VLibFilter(self.GetReader())) line = next(iterator) self._hasOutput = True @@ -225,6 +225,7 @@ def __init__(self, toolchain : ToolMixIn): toolchain._logger) if (self._platform == "Windows"): executablePath = self._binaryDirectoryPath / "vcom.exe" + elif (self._platform == "Linux"): executablePath = self._binaryDirectoryPath / "vcom" else: raise PlatformNotSupportedException(self._platform) super().__init__(self._platform, self._dryrun, executablePath, logger=self._logger) @@ -234,7 +235,7 @@ class Executable(metaclass=ExecutableArgument): _value = None # class FlagNoRangeCheck(metaclass=LongFlagArgument): - # _name = "norangecheck" + # _name = "norangecheck" # _value = None class SwitchVHDLVersion(metaclass=ShortValuedFlagArgument): @@ -243,11 +244,11 @@ class SwitchVHDLVersion(metaclass=ShortValuedFlagArgument): _value = None class SwitchVHDLLibrary(metaclass=ShortTupleArgument): - _name = "work" - _value = None + _name = "work" + _value = None class ArgSourceFile(metaclass=PathArgument): - _value = None + _value = None Parameters = CommandLineArgumentList( Executable, @@ -270,11 +271,11 @@ def Compile(self): except Exception as ex: raise RivieraPROException("Failed to launch acom run.") from ex - self._hasOutput = False + self._hasOutput = False self._hasWarnings = False - self._hasErrors = False + self._hasErrors = False try: - iterator = iter(RivieraPROVComFilter(self.GetReader())) + iterator = iter(VComFilter(self.GetReader())) line = next(iterator) @@ -305,12 +306,9 @@ def __init__(self, toolchain: ToolMixIn): self, toolchain._platform, toolchain._dryrun, toolchain._binaryDirectoryPath, toolchain._version, toolchain._logger) - if (self._platform == "Windows"): - executablePath = self._binaryDirectoryPath / "vsim.exe" - elif (self._platform == "Linux"): - executablePath = self._binaryDirectoryPath / "vsim" - else: - raise PlatformNotSupportedException(self._platform) + if (self._platform == "Windows"): executablePath = self._binaryDirectoryPath / "vsim.exe" + elif (self._platform == "Linux"): executablePath = self._binaryDirectoryPath / "vsim" + else: raise PlatformNotSupportedException(self._platform) super().__init__(self._platform, self._dryrun, executablePath, logger=self._logger) self.Parameters[self.Executable] = executablePath @@ -362,7 +360,7 @@ def Simulate(self): self._hasErrors = False simulationResult = CallByRefParam(SimulationResult.Error) try: - iterator = iter(PoCSimulationResultFilter(RivieraPROVSimFilter(self.GetReader()), simulationResult)) + iterator = iter(PoCSimulationResultFilter(VSimFilter(self.GetReader()), simulationResult)) line = next(iterator) line.IndentBy(self.Logger.BaseIndent + 1) @@ -390,17 +388,17 @@ def Simulate(self): return simulationResult.value -def RivieraPROVLibFilter(gen): +def VLibFilter(gen): """A line based output stream filter for Riviera-PRO's VHDL library management tool.""" for line in gen: yield LogEntry(line, Severity.Normal) -def RivieraPROVComFilter(gen): # mccabe:disable=MC0001 +def VComFilter(gen): # mccabe:disable=MC0001 """A line based output stream filter for Riviera-PRO's VHDL compiler.""" for line in gen: yield LogEntry(line, Severity.Normal) -def RivieraPROVSimFilter(gen): +def VSimFilter(gen): """A line based output stream filter for Riviera-PRO's VHDL simulator.""" for line in gen: yield LogEntry(line, Severity.Normal) diff --git a/py/ToolChain/Mentor/ModelSim.py b/py/ToolChain/Mentor/ModelSim.py index 991de916..a2562fc2 100644 --- a/py/ToolChain/Mentor/ModelSim.py +++ b/py/ToolChain/Mentor/ModelSim.py @@ -54,9 +54,9 @@ 'ModelSimSE64Configuration', 'Selector', 'ModelSim', - 'ModelSimVHDLLibraryTool', - 'ModelSimVHDLCompiler', - 'ModelSimSimulator', + 'VHDLLibraryTool', + 'VHDLCompiler', + 'VHDLSimulator', 'ModelSimVLibFilter', 'ModelSimVComFilter', 'ModelSimVSimFilter' @@ -355,16 +355,16 @@ def Select(self): class ModelSim(ToolMixIn): def GetVHDLLibraryTool(self): - return ModelSimVHDLLibraryTool(self) + return VHDLLibraryTool(self) def GetVHDLCompiler(self): - return ModelSimVHDLCompiler(self) + return VHDLCompiler(self) def GetSimulator(self): - return ModelSimSimulator(self) + return VHDLSimulator(self) -class ModelSimVHDLLibraryTool(OutputFilteredExecutable, ToolMixIn): +class VHDLLibraryTool(OutputFilteredExecutable, ToolMixIn): def __init__(self, toolchain: ToolMixIn): ToolMixIn.__init__( self, toolchain._platform, toolchain._dryrun, toolchain._binaryDirectoryPath, toolchain._version, @@ -404,7 +404,7 @@ def CreateLibrary(self): self._hasWarnings = False self._hasErrors = False try: - iterator = iter(ModelSimVLibFilter(self.GetReader())) + iterator = iter(VLibFilter(self.GetReader())) line = next(iterator) line.IndentBy(self.Logger.BaseIndent + 1) @@ -430,7 +430,7 @@ def CreateLibrary(self): self.LogNormal("-" * (78 - self.Logger.BaseIndent * 2), indent=1) -class ModelSimVHDLCompiler(OutputFilteredExecutable, ToolMixIn): +class VHDLCompiler(OutputFilteredExecutable, ToolMixIn): def __init__(self, toolchain : ToolMixIn): ToolMixIn.__init__( self, toolchain._platform, toolchain._dryrun, toolchain._binaryDirectoryPath, toolchain._version, @@ -511,7 +511,7 @@ def Compile(self): self._hasWarnings = False self._hasErrors = False try: - iterator = iter(ModelSimVComFilter(self.GetReader())) + iterator = iter(VComFilter(self.GetReader())) line = next(iterator) line.IndentBy(self.Logger.BaseIndent + 1) @@ -541,7 +541,7 @@ def GetTclCommand(self): return "vcom " + " ".join(parameterList[1:]) -class ModelSimSimulator(OutputFilteredExecutable, ToolMixIn): +class VHDLSimulator(OutputFilteredExecutable, ToolMixIn): def __init__(self, toolchain : ToolMixIn): ToolMixIn.__init__( self, toolchain._platform, toolchain._dryrun, toolchain._binaryDirectoryPath, toolchain._version, @@ -660,7 +660,7 @@ def Simulate(self): self._hasErrors = False simulationResult = CallByRefParam(SimulationResult.Error) try: - iterator = iter(PoCSimulationResultFilter(ModelSimVSimFilter(self.GetReader()), simulationResult)) + iterator = iter(PoCSimulationResultFilter(VSimFilter(self.GetReader()), simulationResult)) line = next(iterator) line.IndentBy(self.Logger.BaseIndent + 1) @@ -691,7 +691,7 @@ def Simulate(self): return simulationResult.value -def ModelSimVLibFilter(gen): +def VLibFilter(gen): for line in gen: if line.startswith("** Warning: "): yield LogEntry(line, Severity.Warning) @@ -703,7 +703,7 @@ def ModelSimVLibFilter(gen): yield LogEntry(line, Severity.Normal) -def ModelSimVComFilter(gen): +def VComFilter(gen): for line in gen: if line.startswith("** Warning: "): yield LogEntry(line, Severity.Warning) @@ -715,7 +715,7 @@ def ModelSimVComFilter(gen): yield LogEntry(line, Severity.Normal) -def ModelSimVSimFilter(gen): +def VSimFilter(gen): PoCOutputFound = False for line in gen: if line.startswith("# Loading "):