VLSI Design & Automation Group
UC Santa Cruz VLSI Design and Automation research lab
- 125 followers
- Santa Cruz, CA
- http://vlsida.github.io
- mrg+vlsida@ucsc.edu
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VLSIDA/openram_testchip’s past year of commit activity - sky130_sram_macros Public
VLSIDA/sky130_sram_macros’s past year of commit activity - sky130_fd_bd_sram Public
VLSIDA/sky130_fd_bd_sram’s past year of commit activity - openram_testchip2 Public
VLSIDA/openram_testchip2’s past year of commit activity - OpenLane Public Forked from The-OpenROAD-Project/OpenLane
OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.
VLSIDA/OpenLane’s past year of commit activity - sky130_klayout_pdk Public Forked from mabrains/sky130_klayout_pdk
Skywater 130nm Klayout Device Generators PDK
VLSIDA/sky130_klayout_pdk’s past year of commit activity