From 80ecc327856f6e37544f676caa5c29dc7ddc08d9 Mon Sep 17 00:00:00 2001 From: Thomas Benz Date: Thu, 24 Sep 2020 11:52:28 +0200 Subject: [PATCH] WIP: proposed patch for word_size % write_size != 0 --- compiler/base/verilog.py | 9 +++++++-- compiler/characterizer/delay.py | 2 +- compiler/characterizer/functional.py | 3 ++- compiler/characterizer/simulation.py | 2 +- compiler/modules/bank.py | 2 +- compiler/modules/port_data.py | 3 ++- compiler/modules/write_driver_array.py | 3 ++- compiler/modules/write_mask_and_array.py | 3 ++- compiler/sram/sram_base.py | 4 ++-- 9 files changed, 20 insertions(+), 11 deletions(-) diff --git a/compiler/base/verilog.py b/compiler/base/verilog.py index 04344738f2ed1981487465cb20b7dfd007fae760..bebd3bc6347168e8be298b22cecc76d38b17d969 100644 --- a/compiler/base/verilog.py +++ b/compiler/base/verilog.py @@ -6,6 +6,7 @@ # All rights reserved. # import debug +import math class verilog: """ @@ -53,7 +54,7 @@ class verilog: self.vf.write("\n );\n\n") if self.write_size: - self.num_wmasks = int(self.word_size/self.write_size) + self.num_wmasks = int(math.ceil(self.word_size/self.write_size)) self.vf.write(" parameter NUM_WMASKS = {0} ;\n".format(self.num_wmasks)) self.vf.write(" parameter DATA_WIDTH = {0} ;\n".format(self.word_size)) self.vf.write(" parameter ADDR_WIDTH = {0} ;\n".format(self.addr_size)) @@ -189,9 +190,13 @@ class verilog: self.vf.write(" if (!csb{0}_reg)\n".format(port)) if self.write_size: + remainder_bits = self.word_size % self.write_size for mask in range(0,self.num_wmasks): lower = mask * self.write_size - upper = lower + self.write_size-1 + if (remainder_bits and mask == self.num_wmasks-1): + upper = lower + remainder_bits-1 + else: + upper = lower + self.write_size-1 self.vf.write(" if (wmask{0}_reg[{1}])\n".format(port,mask)) self.vf.write(" mem[addr{0}_reg][{1}:{2}] = din{0}_reg[{1}:{2}];\n".format(port,upper,lower)) self.vf.write(" end\n") diff --git a/compiler/characterizer/delay.py b/compiler/characterizer/delay.py index b7faaec32103b67c42f65cfac52ac050bfc2330c..f24148362fba753517ed17aa6d62c29ee251c165 100644 --- a/compiler/characterizer/delay.py +++ b/compiler/characterizer/delay.py @@ -47,7 +47,7 @@ class delay(simulation): self.targ_write_ports = [] self.period = 0 if self.write_size: - self.num_wmasks = int(self.word_size / self.write_size) + self.num_wmasks = int(math.ceil(self.word_size / self.write_size)) else: self.num_wmasks = 0 self.set_load_slew(0,0) diff --git a/compiler/characterizer/functional.py b/compiler/characterizer/functional.py index 2c391e384f9a74a992b68d2ecbeb13c4c9c6e093..4c2f8e9f3cf8507c2853f17ca8c59d7e39d53100 100644 --- a/compiler/characterizer/functional.py +++ b/compiler/characterizer/functional.py @@ -8,6 +8,7 @@ import collections import debug import random +import math from .stimuli import * from .charutils import * from globals import OPTS @@ -31,7 +32,7 @@ class functional(simulation): random.seed(12345) if self.write_size: - self.num_wmasks = int(self.word_size / self.write_size) + self.num_wmasks = int(math.ceil(self.word_size / self.write_size)) else: self.num_wmasks = 0 diff --git a/compiler/characterizer/simulation.py b/compiler/characterizer/simulation.py index 064eb2c5b42efb9ed9d90d7a26ee4b5abc60c496..9cbd42610e91fdb0460155d9b91178b175a4520c 100644 --- a/compiler/characterizer/simulation.py +++ b/compiler/characterizer/simulation.py @@ -38,7 +38,7 @@ class simulation(): self.write_ports = self.sram.write_ports self.words_per_row = self.sram.words_per_row if self.write_size: - self.num_wmasks = int(self.word_size/self.write_size) + self.num_wmasks = int(math.ceil(self.word_size/self.write_size)) else: self.num_wmasks = 0 diff --git a/compiler/modules/bank.py b/compiler/modules/bank.py index 158ac37be39341cb7a48618d9ede12ff1ff9cd91..6b351adca32c26e80bf7ce4b0f95760713ede02a 100644 --- a/compiler/modules/bank.py +++ b/compiler/modules/bank.py @@ -27,7 +27,7 @@ class bank(design.design): self.sram_config = sram_config sram_config.set_local_config(self) if self.write_size: - self.num_wmasks = int(self.word_size / self.write_size) + self.num_wmasks = int(ceil(self.word_size / self.write_size)) else: self.num_wmasks = 0 diff --git a/compiler/modules/port_data.py b/compiler/modules/port_data.py index bd6b39e275718d57ad3428a6015b8a6cba0e8419..148d5f7cad5a834dea856104210e5984c9e94beb 100644 --- a/compiler/modules/port_data.py +++ b/compiler/modules/port_data.py @@ -6,6 +6,7 @@ from tech import drc import debug import design +import math from sram_factory import factory from collections import namedtuple from vector import vector @@ -23,7 +24,7 @@ class port_data(design.design): sram_config.set_local_config(self) self.port = port if self.write_size is not None: - self.num_wmasks = int(self.word_size / self.write_size) + self.num_wmasks = int(math.ceil(self.word_size / self.write_size)) else: self.num_wmasks = 0 diff --git a/compiler/modules/write_driver_array.py b/compiler/modules/write_driver_array.py index a6eb1384246dfccb36cf6bec8ee19f3a87031935..66cfbfdcda1b6f75af57d2962763d27cdeb66d42 100644 --- a/compiler/modules/write_driver_array.py +++ b/compiler/modules/write_driver_array.py @@ -7,6 +7,7 @@ # import design import debug +import math from tech import drc from sram_factory import factory from vector import vector @@ -37,7 +38,7 @@ class write_driver_array(design.design): self.num_spare_cols = num_spare_cols if self.write_size: - self.num_wmasks = int(self.word_size / self.write_size) + self.num_wmasks = int(math.ceil(self.word_size / self.write_size)) self.create_netlist() if not OPTS.netlist_only: diff --git a/compiler/modules/write_mask_and_array.py b/compiler/modules/write_mask_and_array.py index d48aefefabd6e239a82a15cb293fc3f3158bf903..dbd83f81bf3941bf1722c686d296ccff2f5f2f8c 100644 --- a/compiler/modules/write_mask_and_array.py +++ b/compiler/modules/write_mask_and_array.py @@ -7,6 +7,7 @@ # import design import debug +import math from sram_factory import factory from vector import vector from globals import OPTS @@ -30,7 +31,7 @@ class write_mask_and_array(design.design): self.write_size = write_size self.column_offset = column_offset self.words_per_row = int(columns / word_size) - self.num_wmasks = int(word_size / write_size) + self.num_wmasks = int(math.ceil(word_size / write_size)) self.create_netlist() if not OPTS.netlist_only: diff --git a/compiler/sram/sram_base.py b/compiler/sram/sram_base.py index b16c28fa2f157ccd44113f34bc5e5820f552cf30..72b11978c4c13b9d47109b584f85a4b1b9f40b49 100644 --- a/compiler/sram/sram_base.py +++ b/compiler/sram/sram_base.py @@ -7,7 +7,7 @@ # import datetime import debug -from math import log +from math import log, ceil from importlib import reload from vector import vector from globals import OPTS, print_time @@ -33,7 +33,7 @@ class sram_base(design, verilog, lef): self.bank_insts = [] if self.write_size: - self.num_wmasks = int(self.word_size / self.write_size) + self.num_wmasks = int(ceil(self.word_size / self.write_size)) else: self.num_wmasks = 0 -- 2.16.5