training labs and examples
SystemVerilog Makefile Verilog Forth
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examples Singleton Object Pattern with SystemVerilog Jul 13, 2017
projects Up-Down Counter SV Testbench Environment Sep 18, 2016
README changed format Jul 17, 2014


This repository contains examples and sample short projects that can be used to learn basic concepts of functional verification using SystemVerilog

You can browse the code freely. If you want to clone a local copy - you need to first install git and then do following on a git bash shell 
(Refer for basic github tutorial)

1) git clone

There are two main sub directories in this repository
1) examples
     This directory contains several system verilog examples that you can refer through
2) project 
    This directory will eventually contain short projects that takes a smaller design and builds a complete verification testbench around the same.
    For now - the only one project is a simple 2x2 port ethernet switch (dut and env)
For more specific details on how to run simulations - see the README files in  examples/project sub-directories    

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