Skip to content
An easy-to-use Python library for generating VHDL, designed for use with FPGAs.
Branch: master
Clone or download
Fetching latest commit…
Cannot retrieve the latest commit at this time.
Permalink
Type Name Latest commit message Commit time
Failed to load latest commit information.
.idea
dist
docs
examples
pywire.egg-info
pywire
LICENSE.txt
MANIFEST.in
README.md
__init__.py
basic_and.py
bram_test.py
camera_example.py
iCloud
inverter_test.py
mkdocs.yml
setup.cfg
setup.py
test.py

README.md

PyWire is an easy-to-use Python library for generating VHDL, designed for use with FPGAs.

Features:

  • Simple and complex functions
  • BRAM
  • Import components
  • Generate timing files

Does not support:

  • More than one clock

To install:

pip install pywire

Example:

from pywire import *

x = Signal(1, io=“out”, port=“P7”)
y = Signal(1, io=in”, port=“P42”)

def inverter(x):
	return 1-x

x.drive(inverter, y)
print(vhdl(globals()))

See /examples for more functionality

You can’t perform that action at this time.