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An easy-to-use Python library for generating VHDL, designed for use with FPGAs.
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README.md

PyWire is an easy-to-use Python library for generating VHDL, designed for use with FPGAs.

Features:

  • Simple and complex functions
  • BRAM
  • Import components
  • Generate timing files

Does not support:

  • More than one clock

To install:

pip install pywire

Example:

from pywire import *

x = Signal(1, io=“out”, port=“P7”)
y = Signal(1, io=in”, port=“P42”)

def inverter(x):
	return 1-x

x.drive(inverter, y)
print(vhdl(globals()))

See /examples for more functionality

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