diff --git a/vistrails/core/wrapper/specs.py b/vistrails/core/wrapper/specs.py index 54a0136d3..97ba244d2 100644 --- a/vistrails/core/wrapper/specs.py +++ b/vistrails/core/wrapper/specs.py @@ -131,15 +131,28 @@ def to_xml(self, elt=None): for attr, props in self.attrs.iteritems(): value = getattr(self, attr) default_val, is_subelt, run_eval = parse_props(props) - if default_val != value: + if default_val != value and value is not None: + if run_eval: + value = repr(value) + else: + value = unicode(value) if is_subelt: subelt = ET.Element(attr) - subelt.text = unicode(getattr(self, attr)) + subelt.text = value elt.append(subelt) else: - elt.set(attr, unicode(value)) + elt.set(attr, value) return elt + def set_raw(self, attr, value): + """ parse the value before setting it + """ + props = self.attrs[attr] + run_eval = parse_props(props)[2] + if run_eval: + value = ast.literal_eval(value) + setattr(self, attr, value) + @classmethod def internal_from_xml(cls, elt): # Process attributes @@ -186,7 +199,7 @@ class PortSpec(SpecObject): # other attributes attrs = { "name": "", # port name - "port_type": None # type signature in vistrails + "port_type": 'basic:String' # type signature in vistrails } attrs.update(prop_attrs) @@ -273,6 +286,9 @@ def __init__(self, **kwargs): for spec in self.alternate_specs: spec.set_parent(self) + def has_alternate_versions(self): + return len(self.alternate_specs) > 0 + def set_parent(self, parent): self._parent = parent if not self.name: @@ -432,7 +448,7 @@ class FunctionInputPortSpec(InputPortSpec): attrs = {"arg": "", # function argument name "in_kwargs": (True, False, True), # Add as kwarg? "in_args": (False, False, True), # Add as arg? - "arg_pos": [None, False, False]} # argument position + "arg_pos": (-1, False, True)} # argument position attrs.update(InputPortSpec.attrs) def __init__(self, arg=None, **kwargs): @@ -445,8 +461,17 @@ def __init__(self, arg=None, **kwargs): class FunctionOutputPortSpec(OutputPortSpec): - pass + attrs = {"arg": "", # output name + } + attrs.update(InputPortSpec.attrs) + + def __init__(self, arg=None, **kwargs): + if arg is not None: + kwargs['arg'] = arg + if 'name' not in kwargs and 'arg' in kwargs: + kwargs['name'] = kwargs['arg'] + OutputPortSpec.__init__(self, **kwargs) class FunctionSpec(ModuleSpec): """ Specification for wrapping a python function diff --git a/vistrails/packages/vtk/identifiers.py b/vistrails/packages/vtk/identifiers.py index 0dd24179b..b40c648e5 100644 --- a/vistrails/packages/vtk/identifiers.py +++ b/vistrails/packages/vtk/identifiers.py @@ -39,4 +39,4 @@ identifier = 'org.vistrails.vistrails.vtk' old_identifiers = ['edu.utah.sci.vistrails.vtk'] name = 'VTK' -version = '1.0.1' +version = '1.0.2' diff --git a/vistrails/packages/vtk/init.py b/vistrails/packages/vtk/init.py index 8d8efefc7..87d2a1c29 100644 --- a/vistrails/packages/vtk/init.py +++ b/vistrails/packages/vtk/init.py @@ -698,6 +698,13 @@ def handle_module_upgrade_request(controller, module_id, pipeline): module_remap.add_module_remap( UpgradeModuleRemap('1.0.0', '1.0.1', '1.0.1', module_name=module_name)) + remap = module_remap.get_module_upgrade(module_name, '1.0.1') + # Only difference with 1.0.2 is that the spec serialization changed + if remap is None: + # Manually upgrade to 1.0.2 + module_remap.add_module_remap( + UpgradeModuleRemap('1.0.1', '1.0.2', '1.0.2', + module_name=module_name)) return UpgradeWorkflowHandler.remap_module(controller, module_id, pipeline, module_remap)