From bdc735a507de3549b04636314a0d2d499944d490 Mon Sep 17 00:00:00 2001 From: Akash Kollipara Date: Sun, 19 Feb 2023 02:31:41 +0530 Subject: [PATCH] Add platform support for Qemu SiFive-E - Add qemu sifive_e platform and bootloader support Note: Bootloader to be used with following command `qemu-system-riscv32 ... -device loader,file= ...` - Updates on platform files to reduce size for bootloader - Add USE_TIMER to enable/disable from platform config. - [driver] PLIC will only build if N_PLAT_IRQS are non 0 Issue: #233 --- README.md | 8 +- src/driver/interrupt/plic/build.mk | 2 + .../sifive/common_fe310/platform/plat_timer.c | 6 +- .../sifive/common_fe310/platform/platform.c | 7 ++ src/platform/sifive/fe310g002-bl/config.mk | 10 ++ src/platform/sifive/fe310g002/config.mk | 9 ++ src/platform/sifive/qemu-sifive-e-bl/build.mk | 28 +++++ .../sifive/qemu-sifive-e-bl/config.mk | 101 +++++++++++++++ .../qemu-sifive-e-bl/include/plat_defines.h | 20 +++ .../qemu-sifive-e-bl/include/plat_mem.h | 28 +++++ .../sifive/qemu-sifive-e-bl/platform.c | 17 +++ .../qemu-sifive-e-bl/resources/build.mk | 13 ++ .../sifive/qemu-sifive-e-bl/resources/dp.c | 90 ++++++++++++++ .../sifive/qemu-sifive-e-bl/resources/sp.c | 47 +++++++ src/platform/sifive/qemu-sifive-e/build.mk | 25 ++++ src/platform/sifive/qemu-sifive-e/config.mk | 100 +++++++++++++++ .../qemu-sifive-e/include/plat_defines.h | 20 +++ .../sifive/qemu-sifive-e/include/plat_mem.h | 28 +++++ .../sifive/qemu-sifive-e/resources/build.mk | 13 ++ .../sifive/qemu-sifive-e/resources/dp.c | 115 ++++++++++++++++++ .../sifive/qemu-sifive-e/resources/sp.c | 65 ++++++++++ 21 files changed, 746 insertions(+), 6 deletions(-) create mode 100644 src/platform/sifive/qemu-sifive-e-bl/build.mk create mode 100644 src/platform/sifive/qemu-sifive-e-bl/config.mk create mode 100644 src/platform/sifive/qemu-sifive-e-bl/include/plat_defines.h create mode 100644 src/platform/sifive/qemu-sifive-e-bl/include/plat_mem.h create mode 100644 src/platform/sifive/qemu-sifive-e-bl/platform.c create mode 100644 src/platform/sifive/qemu-sifive-e-bl/resources/build.mk create mode 100644 src/platform/sifive/qemu-sifive-e-bl/resources/dp.c create mode 100644 src/platform/sifive/qemu-sifive-e-bl/resources/sp.c create mode 100644 src/platform/sifive/qemu-sifive-e/build.mk create mode 100644 src/platform/sifive/qemu-sifive-e/config.mk create mode 100644 src/platform/sifive/qemu-sifive-e/include/plat_defines.h create mode 100644 src/platform/sifive/qemu-sifive-e/include/plat_mem.h create mode 100644 src/platform/sifive/qemu-sifive-e/resources/build.mk create mode 100644 src/platform/sifive/qemu-sifive-e/resources/dp.c create mode 100644 src/platform/sifive/qemu-sifive-e/resources/sp.c diff --git a/README.md b/README.md index 9b63560c..fbabdac7 100644 --- a/README.md +++ b/README.md @@ -25,10 +25,10 @@ Connect with us over VisorFolks discord server: < [**JOIN**](https://discord.gg/ ### Supported Platforms -| Atmel | SiFive | STMicro | TI | Raspberry Pi | -| ---------- | ----------- | ----------- | ----------- | -------------| -| ATMega328P | FE310-G002 | Coming soon | Coming soon | Coming soon | -| ATMega2560 | | | | | +| Atmel | SiFive | STMicro | TI | Raspberry Pi | +| ---------- | ------------- | ----------- | ----------- | -------------| +| ATMega328P | FE310-G002 | Coming soon | Coming soon | Coming soon | +| ATMega2560 | QEMU SiFive-E | | | | ### Programming Languages * asm/assembly diff --git a/src/driver/interrupt/plic/build.mk b/src/driver/interrupt/plic/build.mk index 0a52fcd2..4625b08f 100644 --- a/src/driver/interrupt/plic/build.mk +++ b/src/driver/interrupt/plic/build.mk @@ -11,8 +11,10 @@ PLIC_PATH := $(GET_PATH) ifeq ($(ARCH), riscv) +ifneq ($(N_PLAT_IRQS),0) DIR := $(PLIC_PATH) include mk/obj.mk endif +endif diff --git a/src/platform/sifive/common_fe310/platform/plat_timer.c b/src/platform/sifive/common_fe310/platform/plat_timer.c index 12e380e7..096a752a 100644 --- a/src/platform/sifive/common_fe310/platform/plat_timer.c +++ b/src/platform/sifive/common_fe310/platform/plat_timer.c @@ -147,7 +147,7 @@ static tvisor_timer_t *plat_timer_port; * plat_timer_setup - Timer driver setup function * To be exported to driver table. */ -static status_t plat_timer_setup(void) +status_t plat_timer_setup(void) { status_t ret = success; const irqs_t *irq; @@ -177,7 +177,7 @@ static status_t plat_timer_setup(void) * plat_timer_exit - Timer driver shutdown function * To be exported to driver table. */ -static status_t plat_timer_exit(void) +status_t plat_timer_exit(void) { const irqs_t *irq; arch_di_mtime(); @@ -189,4 +189,6 @@ static status_t plat_timer_exit(void) return timer_release_device(); } +#if USE_TIMER INCLUDE_DRIVER(plat_timer, plat_timer_setup, plat_timer_exit, 0, 1, 1); +#endif diff --git a/src/platform/sifive/common_fe310/platform/platform.c b/src/platform/sifive/common_fe310/platform/platform.c index 342a1955..e92673e3 100644 --- a/src/platform/sifive/common_fe310/platform/platform.c +++ b/src/platform/sifive/common_fe310/platform/platform.c @@ -75,12 +75,19 @@ void platform_setup() { status_t ret = success; +#if PRCI_CLK driver_setup("sysclk_prci"); ret |= sysclk_reset(); +#endif driver_setup("earlycon"); bootmsgs_enable(); +#ifdef BOOTLOADER + cyancore_insignia_lite(); +#else cyancore_insignia(); +#endif + #if PRINT_MEMORY_LAYOUT platform_memory_layout(); #endif diff --git a/src/platform/sifive/fe310g002-bl/config.mk b/src/platform/sifive/fe310g002-bl/config.mk index 70a9bbf6..b3c3b1a4 100644 --- a/src/platform/sifive/fe310g002-bl/config.mk +++ b/src/platform/sifive/fe310g002-bl/config.mk @@ -88,10 +88,20 @@ $(eval $(call add_define,ERRATA_CIP578)) #====================================================================== SYSCLK_ENABLE := 1 PRCI_CLK := 1 +$(eval $(call add_define,SYSCLK_ENABLE)) +$(eval $(call add_define,PRCI_CLK)) #====================================================================== #====================================================================== # Bootload Configuration #====================================================================== $(eval $(call add_define,BOOTLOADER)) + +#====================================================================== +# Bootloader +# \ Timer: Sched timer/wall clock +#====================================================================== +USE_TIMER ?= 0 +$(eval $(call add_define,USE_TIMER)) +#====================================================================== #====================================================================== diff --git a/src/platform/sifive/fe310g002/config.mk b/src/platform/sifive/fe310g002/config.mk index 6e6e7541..fb8cae0e 100644 --- a/src/platform/sifive/fe310g002/config.mk +++ b/src/platform/sifive/fe310g002/config.mk @@ -88,4 +88,13 @@ $(eval $(call add_define,ERRATA_CIP578)) #====================================================================== SYSCLK_ENABLE := 1 PRCI_CLK := 1 +$(eval $(call add_define,SYSCLK_ENABLE)) +$(eval $(call add_define,PRCI_CLK)) +#====================================================================== + +#====================================================================== +# Timer: Sched timer/wall clock +#====================================================================== +USE_TIMER ?= 1 +$(eval $(call add_define,USE_TIMER)) #====================================================================== diff --git a/src/platform/sifive/qemu-sifive-e-bl/build.mk b/src/platform/sifive/qemu-sifive-e-bl/build.mk new file mode 100644 index 00000000..64e69211 --- /dev/null +++ b/src/platform/sifive/qemu-sifive-e-bl/build.mk @@ -0,0 +1,28 @@ +# +# CYANCORE LICENSE +# Copyrights (C) 2019, Cyancore Team +# +# File Name : build.mk +# Description : This file accumulates the build scripts from +# all other directories that have HiFive 1 Rev B +# board support sources +# Primary Author : Akash Kollipara [akashkollipara@gmail.com] +# Organisation : Cyancore Core-Team +# + +FE310G002_DIR := $(GET_PATH) + +ARCH := riscv +BIT := 32 +ARCH_VARIANT := imac +ARCH_ABI := ilp32 +TARGET_FLAGS += -march=rv32imac -mabi=$(ARCH_ABI) +PLAT_INCLUDE += $(FE310G002_DIR)/include +OUTPUT_FORMAT := elf32-littleriscv + +include $(FE310G002_DIR)/config.mk +include $(FE310G002_DIR)/../common_fe310/build.mk +$(eval $(call check_and_include,USE_DEFAULT_RESOURCES,$(FE310G002_DIR)/resources/build.mk)) + +DIR := $(FE310G002_DIR) +include mk/obj.mk diff --git a/src/platform/sifive/qemu-sifive-e-bl/config.mk b/src/platform/sifive/qemu-sifive-e-bl/config.mk new file mode 100644 index 00000000..dbf8ecf1 --- /dev/null +++ b/src/platform/sifive/qemu-sifive-e-bl/config.mk @@ -0,0 +1,101 @@ +# +# CYANCORE LICENSE +# Copyrights (C) 2019, Cyancore Team +# +# File Name : config.mk +# Description : This file defines configuration for HiFive 1B +# Primary Author : Akash Kollipara [akashkollipara@gmail.com] +# Organisation : Cyancore Core-Team +# + +#====================================================================== +# Configuration file for Platforms +#====================================================================== + +#====================================================================== +# Platform Configuration +# Do not alter below FLAGS unless explicitly mentioned +#====================================================================== +N_CORES := 1 +$(eval $(call add_define,N_CORES)) + +CCSMP := 0 +$(eval $(call add_define,CCSMP)) + +$(eval $(call add_define,BIT)) + +BOOT_CORE_ID:= 0 +$(eval $(call add_define,BOOT_CORE_ID)) + +FLASH_START := 0x000001000 +FLASH_SIZE := 0x2000 # 8K +RAM_START := 0x80000000 +RAM_SIZE := 0x4000 # 16K +ITIM_START := 0x08000000 +ITIM_SIZE := 0x2000 # 8K +HEAP_SIZE ?= 512 +STACK_SIZE ?= 0xc00 +STACK_SIZE_PCPU ?= 0xc00 + +$(eval $(call add_define,HEAP_SIZE)) +$(eval $(call add_define,STACK_SIZE)) +$(eval $(call add_define,STACK_SIZE_PCPU)) + +# Call this FLAG from Project config file if needed +XCLK ?= 16000000 +ICLK ?= 72000000 +$(eval $(call add_define,XCLK)) +$(eval $(call add_define,ICLK)) + +N_EXCEP := 12 +$(eval $(call add_define,N_EXCEP)) + +N_IRQ := 12 +$(eval $(call add_define,N_IRQ)) + +N_PLAT_IRQS := 0 +$(eval $(call add_define,N_PLAT_IRQS)) + +MAX_INTERRUPTS_PER_DEVICE := 1 +$(eval $(call add_define,MAX_INTERRUPTS_PER_DEVICE)) + +USE_SPINLOCK ?= 1 +$(eval $(call add_define,USE_SPINLOCK)) + +#====================================================================== +# MEMBUF Configuration +#====================================================================== +MEMBUF_SIZE ?= 1024 +$(eval $(call add_define,MEMBUF_SIZE)) +#====================================================================== + +#====================================================================== +# GPIO Configuration +#====================================================================== +N_PORT := 1 +$(eval $(call add_define,N_PORT)) +#====================================================================== + +#====================================================================== +# Errata CIP-578 +#====================================================================== +ERRATA_CIP578 := 1 +$(eval $(call add_define,ERRATA_CIP578)) +#====================================================================== + +#====================================================================== +# PRCI Sysclk Configuration +#====================================================================== +SYSCLK_ENABLE := 1 +PRCI_CLK := 0 +$(eval $(call add_define,SYSCLK_ENABLE)) +$(eval $(call add_define,PRCI_CLK)) +#====================================================================== + +#====================================================================== +# Bootload Configuration +#====================================================================== +USE_TIMER ?= 0 +$(eval $(call add_define,USE_TIMER)) +$(eval $(call add_define,BOOTLOADER)) +#====================================================================== diff --git a/src/platform/sifive/qemu-sifive-e-bl/include/plat_defines.h b/src/platform/sifive/qemu-sifive-e-bl/include/plat_defines.h new file mode 100644 index 00000000..203a05ce --- /dev/null +++ b/src/platform/sifive/qemu-sifive-e-bl/include/plat_defines.h @@ -0,0 +1,20 @@ +/* + * CYANCORE LICENSE + * Copyrights (C) 2022, Cyancore Team + * + * File Name : plat_mem.h + * Description : This file contains defines corresponding to + * fe310-g002 board + * Primary Author : Akash Kollipara [akashkollipara@gmail.com] + * Organisation : Cyancore Core-Team + */ + +#pragma once + +#define __RISCV_FE310G002__ + +enum pinmux_functions +{ + serial = 0, + pwm = 1 +}; diff --git a/src/platform/sifive/qemu-sifive-e-bl/include/plat_mem.h b/src/platform/sifive/qemu-sifive-e-bl/include/plat_mem.h new file mode 100644 index 00000000..a2faae9d --- /dev/null +++ b/src/platform/sifive/qemu-sifive-e-bl/include/plat_mem.h @@ -0,0 +1,28 @@ +/* + * CYANCORE LICENSE + * Copyrights (C) 2022, Cyancore Team + * + * File Name : plat_mem.h + * Description : This file contains memory config of fe310-g002 + * Primary Author : Akash Kollipara [akashkollipara@gmail.com] + * Organisation : Cyancore Core-Team + */ + +#pragma once + +#define FLASH_SIZE 8K +#define RAM_SIZE 16K + +#define V_ITMEM_START 0x08000000 +#define V_IMEM_START 0x00001000 +#define V_DMEM_START 0x80000000 + +#define L_MEM_START 0x00001000 +#define L_MEM_LENGTH 0x00002000 + +#define ITMEM_LENGTH 0x00002000 +#define IMEM_LENGTH 0x00002000 +#define DMEM_LENGTH 0x00004000 + +#define ALIGN_BOUND 4 +#define HEAP_ALIGN ALIGN_BOUND diff --git a/src/platform/sifive/qemu-sifive-e-bl/platform.c b/src/platform/sifive/qemu-sifive-e-bl/platform.c new file mode 100644 index 00000000..30180b62 --- /dev/null +++ b/src/platform/sifive/qemu-sifive-e-bl/platform.c @@ -0,0 +1,17 @@ +/* + * CYANCORE LICENSE + * Copyrights (C) 2022, Cyancore Team + * + * File Name : platform.c + * Description : This file contains sources for platform apis + * Primary Author : Akash Kollipara [akashkollipara@gmail.com] + * Organisation : Cyancore Core-Team + */ + +#include + +void platform_jump_to_user_code(void) +{ + void (*jmp)(void) = (void *) 0x20000000; + jmp(); +} diff --git a/src/platform/sifive/qemu-sifive-e-bl/resources/build.mk b/src/platform/sifive/qemu-sifive-e-bl/resources/build.mk new file mode 100644 index 00000000..750c58c1 --- /dev/null +++ b/src/platform/sifive/qemu-sifive-e-bl/resources/build.mk @@ -0,0 +1,13 @@ +# +# CYANCORE LICENSE +# Copyrights (C) 2019, Cyancore Team +# +# File Name : build.mk +# Description : This file builds resources sources +# Primary Author : Akash Kollipara [akashkollipara@gmail.com] +# Organisation : Cyancore Core-Team +# + +DIR := $(GET_PATH) + +include mk/obj.mk diff --git a/src/platform/sifive/qemu-sifive-e-bl/resources/dp.c b/src/platform/sifive/qemu-sifive-e-bl/resources/dp.c new file mode 100644 index 00000000..5bcef4fd --- /dev/null +++ b/src/platform/sifive/qemu-sifive-e-bl/resources/dp.c @@ -0,0 +1,90 @@ +/* + * CYANCORE LICENSE + * Copyrights (C) 2019, Cyancore Team + * + * File Name : platform_dp.c + * Description : This file contains sources for platform + * device properties + * Primary Author : Akash Kollipara [akashkollipara@gmail.com] + * Organisation : Cyancore Core-Team + */ + +#include +#include +#include +#include + +#ifndef XCLK +#define XCLK 0 +WARN(< ! > XCLK is not defined!) +#endif + +cpu_t core0 = +{ + .name = "riscv-e310", + .id = 0x0000 +}; + +memory_t mem = +{ + .start = V_DMEM_START, + .size = DMEM_LENGTH +}; + +module_t clint0 = +{ + .id = clint, + .baddr = 0x02000000, + .stride = 0xc000, +}; + +module_t uart0 = +{ + .id = uart | 0, + .baddr = 0x10013000, + .stride = 0x20, + .clk = 115200, + .interrupt[0] = {int_plat, 3, int_rising_edge}, +}; + +gpio_module_t port0 = +{ + .id = gpio | PORTA, + .baddr = 0x10012000, + .stride = 0x4c, +}; + +module_t aon0 = +{ + .id = aon | 0, + .baddr = 0x10000000, + .stride = 0x1000, +}; + +module_t timer_core0 = +{ + .id = timer | 0, + .clk = 32768, + .interrupt[0] = {int_local, 7, int_level}, +}; + +gpio_module_t * const port_list[] = +{ + &port0, +}; + +module_t * const mod_list[] = +{ + &uart0, &clint0, &aon0, &timer_core0 +}; + +dp_t device_prop = +{ + .base_clock = XCLK, + .core[0] = &core0, + .memory = &mem, + + add_ports(port_list), + + add_modules(mod_list), +}; diff --git a/src/platform/sifive/qemu-sifive-e-bl/resources/sp.c b/src/platform/sifive/qemu-sifive-e-bl/resources/sp.c new file mode 100644 index 00000000..d2726681 --- /dev/null +++ b/src/platform/sifive/qemu-sifive-e-bl/resources/sp.c @@ -0,0 +1,47 @@ +/* + * CYANCORE LICENSE + * Copyrights (C) 2019, Cyancore Team + * + * File Name : platform_sp.c + * Description : This file contains sources for platform + * software properties + * Primary Author : Akash Kollipara [akashkollipara@gmail.com] + * Organisation : Cyancore Core-Team + */ + +#include +#include +#include + +static const uint8_t uart0pins[] = {16, 17}; +static pinmux_t uart0 = addpins(0, uart0pins, serial); +swdev_t consoleUart = +{ + .swdev_id = console_uart, + .hwdev_id = uart | 0, + .pmux = &uart0 +}; + +swdev_t schedTimer = +{ + .swdev_id = sched_timer, + .hwdev_id = timer | 0, +}; + +const sw_devid_t terra_devs[] = +{ + console_uart, sched_timer, +}; + +visor_t terravisor = add_visor_devs(terra_devs); + +swdev_t * const sw_devs[] = +{ + &consoleUart, &schedTimer, +}; + +sp_t software_prop = +{ + .terravisor = &terravisor, + add_swdev(sw_devs), +}; diff --git a/src/platform/sifive/qemu-sifive-e/build.mk b/src/platform/sifive/qemu-sifive-e/build.mk new file mode 100644 index 00000000..dece517e --- /dev/null +++ b/src/platform/sifive/qemu-sifive-e/build.mk @@ -0,0 +1,25 @@ +# +# CYANCORE LICENSE +# Copyrights (C) 2019, Cyancore Team +# +# File Name : build.mk +# Description : This file accumulates the build scripts from +# all other directories that have HiFive 1 Rev B +# board support sources +# Primary Author : Akash Kollipara [akashkollipara@gmail.com] +# Organisation : Cyancore Core-Team +# + +FE310G002_DIR := $(GET_PATH) + +ARCH := riscv +BIT := 32 +ARCH_VARIANT := imac +ARCH_ABI := ilp32 +TARGET_FLAGS += -march=rv32imac -mabi=$(ARCH_ABI) +PLAT_INCLUDE += $(FE310G002_DIR)/include +OUTPUT_FORMAT := elf32-littleriscv + +include $(FE310G002_DIR)/config.mk +include $(FE310G002_DIR)/../common_fe310/build.mk +$(eval $(call check_and_include,USE_DEFAULT_RESOURCES,$(FE310G002_DIR)/resources/build.mk)) diff --git a/src/platform/sifive/qemu-sifive-e/config.mk b/src/platform/sifive/qemu-sifive-e/config.mk new file mode 100644 index 00000000..4c8d753a --- /dev/null +++ b/src/platform/sifive/qemu-sifive-e/config.mk @@ -0,0 +1,100 @@ +# +# CYANCORE LICENSE +# Copyrights (C) 2019, Cyancore Team +# +# File Name : config.mk +# Description : This file defines configuration for HiFive 1B +# Primary Author : Akash Kollipara [akashkollipara@gmail.com] +# Organisation : Cyancore Core-Team +# + +#====================================================================== +# Configuration file for Platforms +#====================================================================== + +#====================================================================== +# Platform Configuration +# Do not alter below FLAGS unless explicitly mentioned +#====================================================================== +N_CORES := 1 +$(eval $(call add_define,N_CORES)) + +CCSMP := 0 +$(eval $(call add_define,CCSMP)) + +$(eval $(call add_define,BIT)) + +BOOT_CORE_ID:= 0 +$(eval $(call add_define,BOOT_CORE_ID)) + +FLASH_START := 0x20000000 +FLASH_SIZE := 0x20000000 # 4M +RAM_START := 0x80000000 +RAM_SIZE := 0x4000 # 16K +ITIM_START := 0x08000000 +ITIM_SIZE := 0x2000 # 8K +HEAP_SIZE ?= 4K +STACK_SIZE ?= 0xc00 +STACK_SIZE_PCPU ?= 0xc00 + +$(eval $(call add_define,HEAP_SIZE)) +$(eval $(call add_define,STACK_SIZE)) +$(eval $(call add_define,STACK_SIZE_PCPU)) + +# Call this FLAG from Project config file if needed +XCLK ?= 16000000 +ICLK ?= 72000000 +$(eval $(call add_define,XCLK)) +$(eval $(call add_define,ICLK)) + +N_EXCEP := 12 +$(eval $(call add_define,N_EXCEP)) + +N_IRQ := 12 +$(eval $(call add_define,N_IRQ)) + +N_PLAT_IRQS := 52 +$(eval $(call add_define,N_PLAT_IRQS)) + +MAX_INTERRUPTS_PER_DEVICE := 1 +$(eval $(call add_define,MAX_INTERRUPTS_PER_DEVICE)) + +USE_SPINLOCK ?= 1 +$(eval $(call add_define,USE_SPINLOCK)) + +#====================================================================== +# MEMBUF Configuration +#====================================================================== +MEMBUF_SIZE ?= 1024 +$(eval $(call add_define,MEMBUF_SIZE)) +#====================================================================== + +#====================================================================== +# GPIO Configuration +#====================================================================== +N_PORT := 1 +$(eval $(call add_define,N_PORT)) +#====================================================================== + +#====================================================================== +# Errata CIP-578 +#====================================================================== +ERRATA_CIP578 := 1 +$(eval $(call add_define,ERRATA_CIP578)) +#====================================================================== + +#====================================================================== +# PRCI Sysclk Configuration +#====================================================================== +SYSCLK_ENABLE := 1 +PRCI_CLK := 1 +$(eval $(call add_define,SYSCLK_ENABLE)) +$(eval $(call add_define,PRCI_CLK)) +#====================================================================== + +#====================================================================== +# Timer: Sched timer/wall clock +#====================================================================== +USE_TIMER ?= 1 +$(eval $(call add_define,USE_TIMER)) +#====================================================================== diff --git a/src/platform/sifive/qemu-sifive-e/include/plat_defines.h b/src/platform/sifive/qemu-sifive-e/include/plat_defines.h new file mode 100644 index 00000000..203a05ce --- /dev/null +++ b/src/platform/sifive/qemu-sifive-e/include/plat_defines.h @@ -0,0 +1,20 @@ +/* + * CYANCORE LICENSE + * Copyrights (C) 2022, Cyancore Team + * + * File Name : plat_mem.h + * Description : This file contains defines corresponding to + * fe310-g002 board + * Primary Author : Akash Kollipara [akashkollipara@gmail.com] + * Organisation : Cyancore Core-Team + */ + +#pragma once + +#define __RISCV_FE310G002__ + +enum pinmux_functions +{ + serial = 0, + pwm = 1 +}; diff --git a/src/platform/sifive/qemu-sifive-e/include/plat_mem.h b/src/platform/sifive/qemu-sifive-e/include/plat_mem.h new file mode 100644 index 00000000..a0acb0ce --- /dev/null +++ b/src/platform/sifive/qemu-sifive-e/include/plat_mem.h @@ -0,0 +1,28 @@ +/* + * CYANCORE LICENSE + * Copyrights (C) 2019, Cyancore Team + * + * File Name : plat_mem.h + * Description : This file contains memory config of fe310-g002 + * Primary Author : Akash Kollipara [akashkollipara@gmail.com] + * Organisation : Cyancore Core-Team + */ + +#pragma once + +#define FLASH_SIZE (4M-64K) +#define RAM_SIZE 16K + +#define V_ITMEM_START 0x08000000 +#define V_IMEM_START 0x20000000 +#define V_DMEM_START 0x80000000 + +#define L_MEM_START 0x20000000 +#define L_MEM_LENGTH 0x20000000 + +#define ITMEM_LENGTH 0x00002000 +#define IMEM_LENGTH 0x20000000 +#define DMEM_LENGTH 0x00004000 + +#define ALIGN_BOUND 4 +#define HEAP_ALIGN ALIGN_BOUND diff --git a/src/platform/sifive/qemu-sifive-e/resources/build.mk b/src/platform/sifive/qemu-sifive-e/resources/build.mk new file mode 100644 index 00000000..750c58c1 --- /dev/null +++ b/src/platform/sifive/qemu-sifive-e/resources/build.mk @@ -0,0 +1,13 @@ +# +# CYANCORE LICENSE +# Copyrights (C) 2019, Cyancore Team +# +# File Name : build.mk +# Description : This file builds resources sources +# Primary Author : Akash Kollipara [akashkollipara@gmail.com] +# Organisation : Cyancore Core-Team +# + +DIR := $(GET_PATH) + +include mk/obj.mk diff --git a/src/platform/sifive/qemu-sifive-e/resources/dp.c b/src/platform/sifive/qemu-sifive-e/resources/dp.c new file mode 100644 index 00000000..5cb7c709 --- /dev/null +++ b/src/platform/sifive/qemu-sifive-e/resources/dp.c @@ -0,0 +1,115 @@ +/* + * CYANCORE LICENSE + * Copyrights (C) 2019, Cyancore Team + * + * File Name : platform_dp.c + * Description : This file contains sources for platform + * device properties + * Primary Author : Akash Kollipara [akashkollipara@gmail.com] + * Organisation : Cyancore Core-Team + */ + +#include +#include +#include +#include + +#ifndef XCLK +#define XCLK 0 +WARN(< ! > XCLK is not defined!) +#endif + +cpu_t core0 = +{ + .name = "riscv-e310", + .id = 0x0000 +}; + +memory_t mem = +{ + .start = V_DMEM_START, + .size = DMEM_LENGTH +}; + +module_t plic0 = +{ + .id = plic, + .baddr = 0x0c000000, + .stride = 0x04000000, + .interrupt[0] = {int_local, 11, int_rising_edge}, +}; + +module_t clint0 = +{ + .id = clint, + .baddr = 0x02000000, + .stride = 0xc000, +}; + +module_t uart0 = +{ + .id = uart | 0, + .baddr = 0x10013000, + .stride = 0x20, + .clk = 115200, + .interrupt[0] = {int_plat, 3, int_rising_edge}, +}; + +module_t uart1 = +{ + .id = uart | 1, + .baddr = 0x10023000, + .stride = 0x20, + .clk = 115200, + .interrupt[0] = {int_plat, 4, int_rising_edge}, +}; + +module_t prci0 = +{ + .id = prci, + .baddr = 0x10008000, + .stride = 0x1000, +}; + +gpio_module_t port0 = +{ + .id = gpio | PORTA, + .baddr = 0x10012000, + .stride = 0x4c, +}; + +module_t aon0 = +{ + .id = aon | 0, + .baddr = 0x10000000, + .stride = 0x1000, +}; + +module_t timer_core0 = +{ + .id = timer | 0, + .clk = 32768, + .interrupt[0] = {int_local, 7, int_level}, +}; + +gpio_module_t * const port_list[] = +{ + &port0, +}; + +module_t * const mod_list[] = +{ + &plic0, &uart0, &prci0, &clint0, &aon0, &uart1, + &timer_core0, +}; + +dp_t device_prop = +{ + .base_clock = XCLK, + .core[0] = &core0, + .memory = &mem, + + add_ports(port_list), + + add_modules(mod_list), +}; diff --git a/src/platform/sifive/qemu-sifive-e/resources/sp.c b/src/platform/sifive/qemu-sifive-e/resources/sp.c new file mode 100644 index 00000000..4e668118 --- /dev/null +++ b/src/platform/sifive/qemu-sifive-e/resources/sp.c @@ -0,0 +1,65 @@ +/* + * CYANCORE LICENSE + * Copyrights (C) 2019, Cyancore Team + * + * File Name : platform_sp.c + * Description : This file contains sources for platform + * software properties + * Primary Author : Akash Kollipara [akashkollipara@gmail.com] + * Organisation : Cyancore Core-Team + */ + +#include +#include +#include + +static const uint8_t uart0pins[] = {16, 17}; +static pinmux_t uart0 = addpins(0, uart0pins, serial); +swdev_t consoleUart = +{ + .swdev_id = console_uart, + .hwdev_id = uart | 0, + .pmux = &uart0 +}; + +swdev_t schedTimer = +{ + .swdev_id = sched_timer, + .hwdev_id = timer | 0, +}; + +static const uint8_t led0pins[] = {19, 21}; +static pinmux_t obled0 = addpins(0, led0pins, 0); +swdev_t onBoardLED0 = +{ + .swdev_id = onboard_led | 0, + .pmux = &obled0 +}; + +static const uint8_t led1pins[] = {20}; +static pinmux_t obled1 = addpins(0, led1pins, 0); +swdev_t onBoardLED1 = +{ + .swdev_id = onboard_led | 1, + .pmux = &obled1 +}; + +const sw_devid_t terra_devs[] = +{ + console_uart, sched_timer, (onboard_led | 0), + (onboard_led | 1), +}; + +visor_t terravisor = add_visor_devs(terra_devs); + +swdev_t * const sw_devs[] = +{ + &consoleUart, &schedTimer, &onBoardLED0, + &onBoardLED1, +}; + +sp_t software_prop = +{ + .terravisor = &terravisor, + add_swdev(sw_devs), +};