From 3cfe6af88859196858a6a008dd5f0a6092be4787 Mon Sep 17 00:00:00 2001 From: Thomas Lively Date: Wed, 5 Sep 2018 15:59:06 -0700 Subject: [PATCH 1/5] Add v2i64 comparison operations --- proposals/simd/BinarySIMD.md | 140 +++++++++++++++++++---------------- proposals/simd/SIMD.md | 10 +++ 2 files changed, 85 insertions(+), 65 deletions(-) diff --git a/proposals/simd/BinarySIMD.md b/proposals/simd/BinarySIMD.md index bd7483c48..c10c04f83 100644 --- a/proposals/simd/BinarySIMD.md +++ b/proposals/simd/BinarySIMD.md @@ -102,68 +102,78 @@ The `v8x16.shuffle` instruction has 16 bytes after `simdop`. | `i8x16.eq` | 72 | - | | `i16x8.eq` | 73 | - | | `i32x4.eq` | 74 | - | -| `f32x4.eq` | 75 | - | -| `f64x2.eq` | 76 | - | -| `i8x16.ne` | 77 | - | -| `i16x8.ne` | 78 | - | -| `i32x4.ne` | 79 | - | -| `f32x4.ne` | 80 | - | -| `f64x2.ne` | 81 | - | -| `i8x16.lt_s` | 82 | - | -| `i8x16.lt_u` | 83 | - | -| `i16x8.lt_s` | 84 | - | -| `i16x8.lt_u` | 85 | - | -| `i32x4.lt_s` | 86 | - | -| `i32x4.lt_u` | 87 | - | -| `f32x4.lt` | 88 | - | -| `f64x2.lt` | 89 | - | -| `i8x16.le_s` | 90 | - | -| `i8x16.le_u` | 91 | - | -| `i16x8.le_s` | 92 | - | -| `i16x8.le_u` | 93 | - | -| `i32x4.le_s` | 94 | - | -| `i32x4.le_u` | 95 | - | -| `f32x4.le` | 96 | - | -| `f64x2.le` | 97 | - | -| `i8x16.gt_s` | 98 | - | -| `i8x16.gt_u` | 99 | - | -| `i16x8.gt_s` | 100 | - | -| `i16x8.gt_u` | 101 | - | -| `i32x4.gt_s` | 102 | - | -| `i32x4.gt_u` | 103 | - | -| `f32x4.gt` | 104 | - | -| `f64x2.gt` | 105 | - | -| `i8x16.ge_s` | 106 | - | -| `i8x16.ge_u` | 107 | - | -| `i16x8.ge_s` | 108 | - | -| `i16x8.ge_u` | 109 | - | -| `i32x4.ge_s` | 110 | - | -| `i32x4.ge_u` | 111 | - | -| `f32x4.ge` | 112 | - | -| `f64x2.ge` | 113 | - | -| `f32x4.neg` | 114 | - | -| `f64x2.neg` | 115 | - | -| `f32x4.abs` | 116 | - | -| `f64x2.abs` | 117 | - | -| `f32x4.min` | 118 | - | -| `f64x2.min` | 119 | - | -| `f32x4.max` | 120 | - | -| `f64x2.max` | 121 | - | -| `f32x4.add` | 122 | - | -| `f64x2.add` | 123 | - | -| `f32x4.sub` | 124 | - | -| `f64x2.sub` | 125 | - | -| `f32x4.div` | 126 | - | -| `f64x2.div` | 127 | - | -| `f32x4.mul` | 128 | - | -| `f64x2.mul` | 129 | - | -| `f32x4.sqrt` | 130 | - | -| `f64x2.sqrt` | 131 | - | -| `f32x4.convert_s/i32x4` | 132 | - | -| `f32x4.convert_u/i32x4` | 133 | - | -| `f64x2.convert_s/i64x2` | 134 | - | -| `f64x2.convert_u/i64x2` | 135 | - | -| `i32x4.trunc_s/f32x4:sat` | 136 | - | -| `i32x4.trunc_u/f32x4:sat` | 137 | - | -| `i64x2.trunc_s/f64x2:sat` | 138 | - | -| `i64x2.trunc_u/f64x2:sat` | 139 | - | +| `i64x2.eq` | 75 | - | +| `f32x4.eq` | 76 | - | +| `f64x2.eq` | 77 | - | +| `i8x16.ne` | 78 | - | +| `i16x8.ne` | 79 | - | +| `i32x4.ne` | 80 | - | +| `i64x2.ne` | 81 | - | +| `f32x4.ne` | 82 | - | +| `f64x2.ne` | 83 | - | +| `i8x16.lt_s` | 84 | - | +| `i8x16.lt_u` | 85 | - | +| `i16x8.lt_s` | 86 | - | +| `i16x8.lt_u` | 87 | - | +| `i32x4.lt_s` | 88 | - | +| `i32x4.lt_u` | 89 | - | +| `i64x2.lt_s` | 90 | - | +| `i64x2.lt_u | 91 | - | +| `f32x4.lt` | 92 | - | +| `f64x2.lt` | 93 | - | +| `i8x16.le_s` | 94 | - | +| `i8x16.le_u` | 95 | - | +| `i16x8.le_s` | 96 | - | +| `i16x8.le_u` | 97 | - | +| `i32x4.le_s` | 98 | - | +| `i32x4.le_u` | 99 | - | +| `i64x2.le_s` | 100 | - | +| `i64x2.le_u` | 101 | - | +| `f32x4.le` | 102 | - | +| `f64x2.le` | 103 | - | +| `i8x16.gt_s` | 104 | - | +| `i8x16.gt_u` | 105 | - | +| `i16x8.gt_s` | 106 | - | +| `i16x8.gt_u` | 107 | - | +| `i32x4.gt_s` | 108 | - | +| `i32x4.gt_u` | 109 | - | +| `i64x2.gt_s` | 110 | - | +| `i64x2.gt_u` | 111 | - | +| `f32x4.gt` | 112 | - | +| `f64x2.gt` | 113 | - | +| `i8x16.ge_s` | 114 | - | +| `i8x16.ge_u` | 115 | - | +| `i16x8.ge_s` | 116 | - | +| `i16x8.ge_u` | 117 | - | +| `i32x4.ge_s` | 118 | - | +| `i32x4.ge_u` | 119 | - | +| `i64x2.ge_s` | 120 | - | +| `i64x2.ge_u` | 121 | - | +| `f32x4.ge` | 122 | - | +| `f64x2.ge` | 123 | - | +| `f32x4.neg` | 124 | - | +| `f64x2.neg` | 125 | - | +| `f32x4.abs` | 126 | - | +| `f64x2.abs` | 127 | - | +| `f32x4.min` | 128 | - | +| `f64x2.min` | 129 | - | +| `f32x4.max` | 130 | - | +| `f64x2.max` | 131 | - | +| `f32x4.add` | 132 | - | +| `f64x2.add` | 133 | - | +| `f32x4.sub` | 134 | - | +| `f64x2.sub` | 135 | - | +| `f32x4.div` | 136 | - | +| `f64x2.div` | 137 | - | +| `f32x4.mul` | 138 | - | +| `f64x2.mul` | 139 | - | +| `f32x4.sqrt` | 140 | - | +| `f64x2.sqrt` | 141 | - | +| `f32x4.convert_s/i32x4` | 142 | - | +| `f32x4.convert_u/i32x4` | 143 | - | +| `f64x2.convert_s/i64x2` | 144 | - | +| `f64x2.convert_u/i64x2` | 145 | - | +| `i32x4.trunc_s/f32x4:sat` | 146 | - | +| `i32x4.trunc_u/f32x4:sat` | 147 | - | +| `i64x2.trunc_s/f64x2:sat` | 148 | - | +| `i64x2.trunc_u/f64x2:sat` | 149 | - | diff --git a/proposals/simd/SIMD.md b/proposals/simd/SIMD.md index afcdc9c09..40896a488 100644 --- a/proposals/simd/SIMD.md +++ b/proposals/simd/SIMD.md @@ -483,6 +483,7 @@ mask vector with the same number of lanes as the input interpretation. * `i8x16.eq(a: v128, b: v128) -> v128` * `i16x8.eq(a: v128, b: v128) -> v128` * `i32x4.eq(a: v128, b: v128) -> v128` +* `i64x2.eq(a: v128, b: v128) -> v128` * `f32x4.eq(a: v128, b: v128) -> v128` * `f64x2.eq(a: v128, b: v128) -> v128` @@ -501,6 +502,7 @@ def S.eq(a, b): * `i8x16.ne(a: v128, b: v128) -> v128` * `i16x8.ne(a: v128, b: v128) -> v128` * `i32x4.ne(a: v128, b: v128) -> v128` +* `i64x2.ne(a: v128, b: v128) -> v128` * `f32x4.ne(a: v128, b: v128) -> v128` * `f64x2.ne(a: v128, b: v128) -> v128` @@ -520,6 +522,8 @@ def S.ne(a, b): * `i16x8.lt_u(a: v128, b: v128) -> v128` * `i32x4.lt_s(a: v128, b: v128) -> v128` * `i32x4.lt_u(a: v128, b: v128) -> v128` +* `i64x2.lt_s(a: v128, b: v128) -> v128` +* `i64x2.lt_u(a: v128, b: v128) -> v128` * `f32x4.lt(a: v128, b: v128) -> v128` * `f64x2.lt(a: v128, b: v128) -> v128` @@ -530,6 +534,8 @@ def S.ne(a, b): * `i16x8.le_u(a: v128, b: v128) -> v128` * `i32x4.le_s(a: v128, b: v128) -> v128` * `i32x4.le_u(a: v128, b: v128) -> v128` +* `i64x2.le_s(a: v128, b: v128) -> v128` +* `i64x2.le_u(a: v128, b: v128) -> v128` * `f32x4.le(a: v128, b: v128) -> v128` * `f64x2.le(a: v128, b: v128) -> v128` @@ -540,6 +546,8 @@ def S.ne(a, b): * `i16x8.gt_u(a: v128, b: v128) -> v128` * `i32x4.gt_s(a: v128, b: v128) -> v128` * `i32x4.gt_u(a: v128, b: v128) -> v128` +* `i64x2.gt_s(a: v128, b: v128) -> v128` +* `i64x2.gt_u(a: v128, b: v128) -> v128` * `f32x4.gt(a: v128, b: v128) -> v128` * `f64x2.gt(a: v128, b: v128) -> v128` @@ -550,6 +558,8 @@ def S.ne(a, b): * `i16x8.ge_u(a: v128, b: v128) -> v128` * `i32x4.ge_s(a: v128, b: v128) -> v128` * `i32x4.ge_u(a: v128, b: v128) -> v128` +* `i64x2.ge_s(a: v128, b: v128) -> v128` +* `i64x2.ge_u(a: v128, b: v128) -> v128` * `f32x4.ge(a: v128, b: v128) -> v128` * `f64x2.ge(a: v128, b: v128) -> v128` From 87bdadd34beef5f1e2543dcc0fb0dfc69e4d616d Mon Sep 17 00:00:00 2001 From: Thomas Lively Date: Wed, 12 Sep 2018 16:54:12 -0700 Subject: [PATCH 2/5] Add opcode space holes instead of new instructions --- proposals/simd/BinarySIMD.md | 231 ++++++++++++++++++----------------- proposals/simd/SIMD.md | 10 -- 2 files changed, 116 insertions(+), 125 deletions(-) diff --git a/proposals/simd/BinarySIMD.md b/proposals/simd/BinarySIMD.md index c10c04f83..70532a284 100644 --- a/proposals/simd/BinarySIMD.md +++ b/proposals/simd/BinarySIMD.md @@ -62,118 +62,119 @@ The `v8x16.shuffle` instruction has 16 bytes after `simdop`. | `i8x16.mul` | 32 | - | | `i16x8.mul` | 33 | - | | `i32x4.mul` | 34 | - | -| `i8x16.neg` | 35 | - | -| `i16x8.neg` | 36 | - | -| `i32x4.neg` | 37 | - | -| `i64x2.neg` | 38 | - | -| `i8x16.add_saturate_s` | 39 | - | -| `i8x16.add_saturate_u` | 40 | - | -| `i16x8.add_saturate_s` | 41 | - | -| `i16x8.add_saturate_u` | 42 | - | -| `i8x16.sub_saturate_s` | 43 | - | -| `i8x16.sub_saturate_u` | 44 | - | -| `i16x8.sub_saturate_s` | 45 | - | -| `i16x8.sub_saturate_u` | 46 | - | -| `i8x16.shl` | 47 | - | -| `i16x8.shl` | 48 | - | -| `i32x4.shl` | 49 | - | -| `i64x2.shl` | 50 | - | -| `i8x16.shr_s` | 51 | - | -| `i8x16.shr_u` | 52 | - | -| `i16x8.shr_s` | 53 | - | -| `i16x8.shr_u` | 54 | - | -| `i32x4.shr_s` | 55 | - | -| `i32x4.shr_u` | 56 | - | -| `i64x2.shr_s` | 57 | - | -| `i64x2.shr_u` | 58 | - | -| `v128.and` | 59 | - | -| `v128.or` | 60 | - | -| `v128.xor` | 61 | - | -| `v128.not` | 62 | - | -| `v128.bitselect` | 63 | - | -| `i8x16.any_true` | 64 | - | -| `i16x8.any_true` | 65 | - | -| `i32x4.any_true` | 66 | - | -| `i64x2.any_true` | 67 | - | -| `i8x16.all_true` | 68 | - | -| `i16x8.all_true` | 69 | - | -| `i32x4.all_true` | 70 | - | -| `i64x2.all_true` | 71 | - | -| `i8x16.eq` | 72 | - | -| `i16x8.eq` | 73 | - | -| `i32x4.eq` | 74 | - | -| `i64x2.eq` | 75 | - | -| `f32x4.eq` | 76 | - | -| `f64x2.eq` | 77 | - | -| `i8x16.ne` | 78 | - | -| `i16x8.ne` | 79 | - | -| `i32x4.ne` | 80 | - | -| `i64x2.ne` | 81 | - | -| `f32x4.ne` | 82 | - | -| `f64x2.ne` | 83 | - | -| `i8x16.lt_s` | 84 | - | -| `i8x16.lt_u` | 85 | - | -| `i16x8.lt_s` | 86 | - | -| `i16x8.lt_u` | 87 | - | -| `i32x4.lt_s` | 88 | - | -| `i32x4.lt_u` | 89 | - | -| `i64x2.lt_s` | 90 | - | -| `i64x2.lt_u | 91 | - | -| `f32x4.lt` | 92 | - | -| `f64x2.lt` | 93 | - | -| `i8x16.le_s` | 94 | - | -| `i8x16.le_u` | 95 | - | -| `i16x8.le_s` | 96 | - | -| `i16x8.le_u` | 97 | - | -| `i32x4.le_s` | 98 | - | -| `i32x4.le_u` | 99 | - | -| `i64x2.le_s` | 100 | - | -| `i64x2.le_u` | 101 | - | -| `f32x4.le` | 102 | - | -| `f64x2.le` | 103 | - | -| `i8x16.gt_s` | 104 | - | -| `i8x16.gt_u` | 105 | - | -| `i16x8.gt_s` | 106 | - | -| `i16x8.gt_u` | 107 | - | -| `i32x4.gt_s` | 108 | - | -| `i32x4.gt_u` | 109 | - | -| `i64x2.gt_s` | 110 | - | -| `i64x2.gt_u` | 111 | - | -| `f32x4.gt` | 112 | - | -| `f64x2.gt` | 113 | - | -| `i8x16.ge_s` | 114 | - | -| `i8x16.ge_u` | 115 | - | -| `i16x8.ge_s` | 116 | - | -| `i16x8.ge_u` | 117 | - | -| `i32x4.ge_s` | 118 | - | -| `i32x4.ge_u` | 119 | - | -| `i64x2.ge_s` | 120 | - | -| `i64x2.ge_u` | 121 | - | -| `f32x4.ge` | 122 | - | -| `f64x2.ge` | 123 | - | -| `f32x4.neg` | 124 | - | -| `f64x2.neg` | 125 | - | -| `f32x4.abs` | 126 | - | -| `f64x2.abs` | 127 | - | -| `f32x4.min` | 128 | - | -| `f64x2.min` | 129 | - | -| `f32x4.max` | 130 | - | -| `f64x2.max` | 131 | - | -| `f32x4.add` | 132 | - | -| `f64x2.add` | 133 | - | -| `f32x4.sub` | 134 | - | -| `f64x2.sub` | 135 | - | -| `f32x4.div` | 136 | - | -| `f64x2.div` | 137 | - | -| `f32x4.mul` | 138 | - | -| `f64x2.mul` | 139 | - | -| `f32x4.sqrt` | 140 | - | -| `f64x2.sqrt` | 141 | - | -| `f32x4.convert_s/i32x4` | 142 | - | -| `f32x4.convert_u/i32x4` | 143 | - | -| `f64x2.convert_s/i64x2` | 144 | - | -| `f64x2.convert_u/i64x2` | 145 | - | -| `i32x4.trunc_s/f32x4:sat` | 146 | - | -| `i32x4.trunc_u/f32x4:sat` | 147 | - | -| `i64x2.trunc_s/f64x2:sat` | 148 | - | -| `i64x2.trunc_u/f64x2:sat` | 149 | - | +| `i64x2.mul` | 35 | - | +| `i8x16.neg` | 36 | - | +| `i16x8.neg` | 37 | - | +| `i32x4.neg` | 38 | - | +| `i64x2.neg` | 39 | - | +| `i8x16.add_saturate_s` | 40 | - | +| `i8x16.add_saturate_u` | 41 | - | +| `i16x8.add_saturate_s` | 42 | - | +| `i16x8.add_saturate_u` | 43 | - | +| `i8x16.sub_saturate_s` | 44 | - | +| `i8x16.sub_saturate_u` | 45 | - | +| `i16x8.sub_saturate_s` | 46 | - | +| `i16x8.sub_saturate_u` | 47 | - | +| `i8x16.shl` | 48 | - | +| `i16x8.shl` | 49 | - | +| `i32x4.shl` | 50 | - | +| `i64x2.shl` | 51 | - | +| `i8x16.shr_s` | 52 | - | +| `i8x16.shr_u` | 53 | - | +| `i16x8.shr_s` | 54 | - | +| `i16x8.shr_u` | 55 | - | +| `i32x4.shr_s` | 56 | - | +| `i32x4.shr_u` | 57 | - | +| `i64x2.shr_s` | 58 | - | +| `i64x2.shr_u` | 59 | - | +| `v128.and` | 60 | - | +| `v128.or` | 61 | - | +| `v128.xor` | 62 | - | +| `v128.not` | 63 | - | +| `v128.bitselect` | 64 | - | +| `i8x16.any_true` | 65 | - | +| `i16x8.any_true` | 66 | - | +| `i32x4.any_true` | 67 | - | +| `i64x2.any_true` | 68 | - | +| `i8x16.all_true` | 69 | - | +| `i16x8.all_true` | 70 | - | +| `i32x4.all_true` | 71 | - | +| `i64x2.all_true` | 72 | - | +| `i8x16.eq` | 73 | - | +| `i16x8.eq` | 74 | - | +| `i32x4.eq` | 75 | - | +| ~`i64x2.eq`~ | 76 | - | +| `f32x4.eq` | 77 | - | +| `f64x2.eq` | 78 | - | +| `i8x16.ne` | 79 | - | +| `i16x8.ne` | 80 | - | +| `i32x4.ne` | 81 | - | +| ~`i64x2.ne`~ | 82 | - | +| `f32x4.ne` | 83 | - | +| `f64x2.ne` | 84 | - | +| `i8x16.lt_s` | 85 | - | +| `i8x16.lt_u` | 86 | - | +| `i16x8.lt_s` | 87 | - | +| `i16x8.lt_u` | 88 | - | +| `i32x4.lt_s` | 89 | - | +| `i32x4.lt_u` | 90 | - | +| ~`i64x2.lt_s`~ | 91 | - | +| ~`i64x2.lt_u`~ | 92 | - | +| `f32x4.lt` | 93 | - | +| `f64x2.lt` | 94 | - | +| `i8x16.le_s` | 95 | - | +| `i8x16.le_u` | 96 | - | +| `i16x8.le_s` | 97 | - | +| `i16x8.le_u` | 98 | - | +| `i32x4.le_s` | 99 | - | +| `i32x4.le_u` | 100 | - | +| ~`i64x2.le_s`~ | 101 | - | +| ~`i64x2.le_u`~ | 102 | - | +| `f32x4.le` | 103 | - | +| `f64x2.le` | 104 | - | +| `i8x16.gt_s` | 105 | - | +| `i8x16.gt_u` | 106 | - | +| `i16x8.gt_s` | 107 | - | +| `i16x8.gt_u` | 108 | - | +| `i32x4.gt_s` | 109 | - | +| `i32x4.gt_u` | 110 | - | +| ~`i64x2.gt_s`~ | 111 | - | +| ~`i64x2.gt_u`~ | 112 | - | +| `f32x4.gt` | 113 | - | +| `f64x2.gt` | 114 | - | +| `i8x16.ge_s` | 115 | - | +| `i8x16.ge_u` | 116 | - | +| `i16x8.ge_s` | 117 | - | +| `i16x8.ge_u` | 118 | - | +| `i32x4.ge_s` | 119 | - | +| `i32x4.ge_u` | 120 | - | +| ~`i64x2.ge_s`~ | 121 | - | +| ~`i64x2.ge_u`~ | 122 | - | +| `f32x4.ge` | 123 | - | +| `f64x2.ge` | 124 | - | +| `f32x4.neg` | 125 | - | +| `f64x2.neg` | 126 | - | +| `f32x4.abs` | 127 | - | +| `f64x2.abs` | 128 | - | +| `f32x4.min` | 129 | - | +| `f64x2.min` | 130 | - | +| `f32x4.max` | 131 | - | +| `f64x2.max` | 132 | - | +| `f32x4.add` | 133 | - | +| `f64x2.add` | 134 | - | +| `f32x4.sub` | 135 | - | +| `f64x2.sub` | 136 | - | +| `f32x4.div` | 137 | - | +| `f64x2.div` | 138 | - | +| `f32x4.mul` | 139 | - | +| `f64x2.mul` | 140 | - | +| `f32x4.sqrt` | 141 | - | +| `f64x2.sqrt` | 142 | - | +| `f32x4.convert_s/i32x4` | 143 | - | +| `f32x4.convert_u/i32x4` | 144 | - | +| `f64x2.convert_s/i64x2` | 145 | - | +| `f64x2.convert_u/i64x2` | 146 | - | +| `i32x4.trunc_s/f32x4:sat` | 147 | - | +| `i32x4.trunc_u/f32x4:sat` | 148 | - | +| `i64x2.trunc_s/f64x2:sat` | 149 | - | +| `i64x2.trunc_u/f64x2:sat` | 150 | - | diff --git a/proposals/simd/SIMD.md b/proposals/simd/SIMD.md index 40896a488..afcdc9c09 100644 --- a/proposals/simd/SIMD.md +++ b/proposals/simd/SIMD.md @@ -483,7 +483,6 @@ mask vector with the same number of lanes as the input interpretation. * `i8x16.eq(a: v128, b: v128) -> v128` * `i16x8.eq(a: v128, b: v128) -> v128` * `i32x4.eq(a: v128, b: v128) -> v128` -* `i64x2.eq(a: v128, b: v128) -> v128` * `f32x4.eq(a: v128, b: v128) -> v128` * `f64x2.eq(a: v128, b: v128) -> v128` @@ -502,7 +501,6 @@ def S.eq(a, b): * `i8x16.ne(a: v128, b: v128) -> v128` * `i16x8.ne(a: v128, b: v128) -> v128` * `i32x4.ne(a: v128, b: v128) -> v128` -* `i64x2.ne(a: v128, b: v128) -> v128` * `f32x4.ne(a: v128, b: v128) -> v128` * `f64x2.ne(a: v128, b: v128) -> v128` @@ -522,8 +520,6 @@ def S.ne(a, b): * `i16x8.lt_u(a: v128, b: v128) -> v128` * `i32x4.lt_s(a: v128, b: v128) -> v128` * `i32x4.lt_u(a: v128, b: v128) -> v128` -* `i64x2.lt_s(a: v128, b: v128) -> v128` -* `i64x2.lt_u(a: v128, b: v128) -> v128` * `f32x4.lt(a: v128, b: v128) -> v128` * `f64x2.lt(a: v128, b: v128) -> v128` @@ -534,8 +530,6 @@ def S.ne(a, b): * `i16x8.le_u(a: v128, b: v128) -> v128` * `i32x4.le_s(a: v128, b: v128) -> v128` * `i32x4.le_u(a: v128, b: v128) -> v128` -* `i64x2.le_s(a: v128, b: v128) -> v128` -* `i64x2.le_u(a: v128, b: v128) -> v128` * `f32x4.le(a: v128, b: v128) -> v128` * `f64x2.le(a: v128, b: v128) -> v128` @@ -546,8 +540,6 @@ def S.ne(a, b): * `i16x8.gt_u(a: v128, b: v128) -> v128` * `i32x4.gt_s(a: v128, b: v128) -> v128` * `i32x4.gt_u(a: v128, b: v128) -> v128` -* `i64x2.gt_s(a: v128, b: v128) -> v128` -* `i64x2.gt_u(a: v128, b: v128) -> v128` * `f32x4.gt(a: v128, b: v128) -> v128` * `f64x2.gt(a: v128, b: v128) -> v128` @@ -558,8 +550,6 @@ def S.ne(a, b): * `i16x8.ge_u(a: v128, b: v128) -> v128` * `i32x4.ge_s(a: v128, b: v128) -> v128` * `i32x4.ge_u(a: v128, b: v128) -> v128` -* `i64x2.ge_s(a: v128, b: v128) -> v128` -* `i64x2.ge_u(a: v128, b: v128) -> v128` * `f32x4.ge(a: v128, b: v128) -> v128` * `f64x2.ge(a: v128, b: v128) -> v128` From 1cfa55ca3eecb74404a6e0d780b66b9f4ace38a5 Mon Sep 17 00:00:00 2001 From: Thomas Lively Date: Wed, 12 Sep 2018 16:57:05 -0700 Subject: [PATCH 3/5] Strikethrough i64x2.mul --- proposals/simd/BinarySIMD.md | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/proposals/simd/BinarySIMD.md b/proposals/simd/BinarySIMD.md index 70532a284..480b450ad 100644 --- a/proposals/simd/BinarySIMD.md +++ b/proposals/simd/BinarySIMD.md @@ -62,7 +62,7 @@ The `v8x16.shuffle` instruction has 16 bytes after `simdop`. | `i8x16.mul` | 32 | - | | `i16x8.mul` | 33 | - | | `i32x4.mul` | 34 | - | -| `i64x2.mul` | 35 | - | +| ~`i64x2.mul`~ | 35 | - | | `i8x16.neg` | 36 | - | | `i16x8.neg` | 37 | - | | `i32x4.neg` | 38 | - | From 9626b29b16ff2032a5a1d662847f541420473d63 Mon Sep 17 00:00:00 2001 From: Thomas Lively Date: Wed, 12 Sep 2018 17:00:33 -0700 Subject: [PATCH 4/5] Strikethrough opcode numbers, too --- proposals/simd/BinarySIMD.md | 22 +++++++++++----------- 1 file changed, 11 insertions(+), 11 deletions(-) diff --git a/proposals/simd/BinarySIMD.md b/proposals/simd/BinarySIMD.md index 480b450ad..488b75133 100644 --- a/proposals/simd/BinarySIMD.md +++ b/proposals/simd/BinarySIMD.md @@ -62,7 +62,7 @@ The `v8x16.shuffle` instruction has 16 bytes after `simdop`. | `i8x16.mul` | 32 | - | | `i16x8.mul` | 33 | - | | `i32x4.mul` | 34 | - | -| ~`i64x2.mul`~ | 35 | - | +| ~`i64x2.mul`~ | ~35~| - | | `i8x16.neg` | 36 | - | | `i16x8.neg` | 37 | - | | `i32x4.neg` | 38 | - | @@ -103,13 +103,13 @@ The `v8x16.shuffle` instruction has 16 bytes after `simdop`. | `i8x16.eq` | 73 | - | | `i16x8.eq` | 74 | - | | `i32x4.eq` | 75 | - | -| ~`i64x2.eq`~ | 76 | - | +| ~`i64x2.eq`~ | ~76~| - | | `f32x4.eq` | 77 | - | | `f64x2.eq` | 78 | - | | `i8x16.ne` | 79 | - | | `i16x8.ne` | 80 | - | | `i32x4.ne` | 81 | - | -| ~`i64x2.ne`~ | 82 | - | +| ~`i64x2.ne`~ | ~82~| - | | `f32x4.ne` | 83 | - | | `f64x2.ne` | 84 | - | | `i8x16.lt_s` | 85 | - | @@ -118,8 +118,8 @@ The `v8x16.shuffle` instruction has 16 bytes after `simdop`. | `i16x8.lt_u` | 88 | - | | `i32x4.lt_s` | 89 | - | | `i32x4.lt_u` | 90 | - | -| ~`i64x2.lt_s`~ | 91 | - | -| ~`i64x2.lt_u`~ | 92 | - | +| ~`i64x2.lt_s`~ | ~91~| - | +| ~`i64x2.lt_u`~ | ~92~| - | | `f32x4.lt` | 93 | - | | `f64x2.lt` | 94 | - | | `i8x16.le_s` | 95 | - | @@ -128,8 +128,8 @@ The `v8x16.shuffle` instruction has 16 bytes after `simdop`. | `i16x8.le_u` | 98 | - | | `i32x4.le_s` | 99 | - | | `i32x4.le_u` | 100 | - | -| ~`i64x2.le_s`~ | 101 | - | -| ~`i64x2.le_u`~ | 102 | - | +| ~`i64x2.le_s`~ | ~101~| - | +| ~`i64x2.le_u`~ | ~102~| - | | `f32x4.le` | 103 | - | | `f64x2.le` | 104 | - | | `i8x16.gt_s` | 105 | - | @@ -138,8 +138,8 @@ The `v8x16.shuffle` instruction has 16 bytes after `simdop`. | `i16x8.gt_u` | 108 | - | | `i32x4.gt_s` | 109 | - | | `i32x4.gt_u` | 110 | - | -| ~`i64x2.gt_s`~ | 111 | - | -| ~`i64x2.gt_u`~ | 112 | - | +| ~`i64x2.gt_s`~ | ~111~| - | +| ~`i64x2.gt_u`~ | ~112~| - | | `f32x4.gt` | 113 | - | | `f64x2.gt` | 114 | - | | `i8x16.ge_s` | 115 | - | @@ -148,8 +148,8 @@ The `v8x16.shuffle` instruction has 16 bytes after `simdop`. | `i16x8.ge_u` | 118 | - | | `i32x4.ge_s` | 119 | - | | `i32x4.ge_u` | 120 | - | -| ~`i64x2.ge_s`~ | 121 | - | -| ~`i64x2.ge_u`~ | 122 | - | +| ~`i64x2.ge_s`~ | ~121~| - | +| ~`i64x2.ge_u`~ | ~122~| - | | `f32x4.ge` | 123 | - | | `f64x2.ge` | 124 | - | | `f32x4.neg` | 125 | - | From c52f79013518b37a47c0102896a821c4bd38f27e Mon Sep 17 00:00:00 2001 From: Thomas Lively Date: Tue, 18 Sep 2018 17:21:17 -0700 Subject: [PATCH 5/5] Remove nonexistent instructions entirely --- proposals/simd/BinarySIMD.md | 11 ----------- 1 file changed, 11 deletions(-) diff --git a/proposals/simd/BinarySIMD.md b/proposals/simd/BinarySIMD.md index 488b75133..02cb1b75c 100644 --- a/proposals/simd/BinarySIMD.md +++ b/proposals/simd/BinarySIMD.md @@ -62,7 +62,6 @@ The `v8x16.shuffle` instruction has 16 bytes after `simdop`. | `i8x16.mul` | 32 | - | | `i16x8.mul` | 33 | - | | `i32x4.mul` | 34 | - | -| ~`i64x2.mul`~ | ~35~| - | | `i8x16.neg` | 36 | - | | `i16x8.neg` | 37 | - | | `i32x4.neg` | 38 | - | @@ -103,13 +102,11 @@ The `v8x16.shuffle` instruction has 16 bytes after `simdop`. | `i8x16.eq` | 73 | - | | `i16x8.eq` | 74 | - | | `i32x4.eq` | 75 | - | -| ~`i64x2.eq`~ | ~76~| - | | `f32x4.eq` | 77 | - | | `f64x2.eq` | 78 | - | | `i8x16.ne` | 79 | - | | `i16x8.ne` | 80 | - | | `i32x4.ne` | 81 | - | -| ~`i64x2.ne`~ | ~82~| - | | `f32x4.ne` | 83 | - | | `f64x2.ne` | 84 | - | | `i8x16.lt_s` | 85 | - | @@ -118,8 +115,6 @@ The `v8x16.shuffle` instruction has 16 bytes after `simdop`. | `i16x8.lt_u` | 88 | - | | `i32x4.lt_s` | 89 | - | | `i32x4.lt_u` | 90 | - | -| ~`i64x2.lt_s`~ | ~91~| - | -| ~`i64x2.lt_u`~ | ~92~| - | | `f32x4.lt` | 93 | - | | `f64x2.lt` | 94 | - | | `i8x16.le_s` | 95 | - | @@ -128,8 +123,6 @@ The `v8x16.shuffle` instruction has 16 bytes after `simdop`. | `i16x8.le_u` | 98 | - | | `i32x4.le_s` | 99 | - | | `i32x4.le_u` | 100 | - | -| ~`i64x2.le_s`~ | ~101~| - | -| ~`i64x2.le_u`~ | ~102~| - | | `f32x4.le` | 103 | - | | `f64x2.le` | 104 | - | | `i8x16.gt_s` | 105 | - | @@ -138,8 +131,6 @@ The `v8x16.shuffle` instruction has 16 bytes after `simdop`. | `i16x8.gt_u` | 108 | - | | `i32x4.gt_s` | 109 | - | | `i32x4.gt_u` | 110 | - | -| ~`i64x2.gt_s`~ | ~111~| - | -| ~`i64x2.gt_u`~ | ~112~| - | | `f32x4.gt` | 113 | - | | `f64x2.gt` | 114 | - | | `i8x16.ge_s` | 115 | - | @@ -148,8 +139,6 @@ The `v8x16.shuffle` instruction has 16 bytes after `simdop`. | `i16x8.ge_u` | 118 | - | | `i32x4.ge_s` | 119 | - | | `i32x4.ge_u` | 120 | - | -| ~`i64x2.ge_s`~ | ~121~| - | -| ~`i64x2.ge_u`~ | ~122~| - | | `f32x4.ge` | 123 | - | | `f64x2.ge` | 124 | - | | `f32x4.neg` | 125 | - |