diff --git a/document/core/appendix/gen-index-instructions.py b/document/core/appendix/gen-index-instructions.py index 03f65126a..5fcefc943 100755 --- a/document/core/appendix/gen-index-instructions.py +++ b/document/core/appendix/gen-index-instructions.py @@ -519,6 +519,8 @@ def Instruction(name, opcode, type=None, validation=None, execution=None, operat Instruction(r'\F32X4.\VDIV', r'\hex{FD}~~231', r'[\V128~\V128] \to [\V128]', r'valid-vbinop', r'exec-vbinop', r'op-fdiv'), Instruction(r'\F32X4.\VMIN', r'\hex{FD}~~232', r'[\V128~\V128] \to [\V128]', r'valid-vbinop', r'exec-vbinop', r'op-fmin'), Instruction(r'\F32X4.\VMAX', r'\hex{FD}~~233', r'[\V128~\V128] \to [\V128]', r'valid-vbinop', r'exec-vbinop', r'op-fmax'), + Instruction(r'\F32X4.\VPMIN', r'\hex{FD}~~234', r'[\V128~\V128] \to [\V128]', r'valid-vbinop', r'exec-vbinop', r'op-fpmin'), + Instruction(r'\F32X4.\VPMAX', r'\hex{FD}~~235', r'[\V128~\V128] \to [\V128]', r'valid-vbinop', r'exec-vbinop', r'op-fpmax'), Instruction(r'\F64X2.\VABS', r'\hex{FD}~~236', r'[\V128] \to [\V128]', r'valid-vunop', r'exec-vunop', r'op-fabs'), Instruction(r'\F64X2.\VNEG', r'\hex{FD}~~237', r'[\V128] \to [\V128]', r'valid-vunop', r'exec-vunop', r'op-fneg'), Instruction(r'\F64X2.\VSQRT', r'\hex{FD}~~239', r'[\V128] \to [\I32]', r'valid-vunop', r'exec-vunop', r'op-fsqrt'), @@ -527,6 +529,8 @@ def Instruction(name, opcode, type=None, validation=None, execution=None, operat Instruction(r'\F64X2.\VMUL', r'\hex{FD}~~242', r'[\V128~\V128] \to [\V128]', r'valid-vbinop', r'exec-vbinop', r'op-fmul'), Instruction(r'\F64X2.\VDIV', r'\hex{FD}~~243', r'[\V128~\V128] \to [\V128]', r'valid-vbinop', r'exec-vbinop', r'op-fdiv'), Instruction(r'\F64X2.\VMIN', r'\hex{FD}~~244', r'[\V128~\V128] \to [\V128]', r'valid-vbinop', r'exec-vbinop', r'op-fmin'), + Instruction(r'\F64X2.\VPMIN', r'\hex{FD}~~245', r'[\V128~\V128] \to [\V128]', r'valid-vbinop', r'exec-vbinop', r'op-fpmin'), + Instruction(r'\F64X2.\VPMAX', r'\hex{FD}~~246', r'[\V128~\V128] \to [\V128]', r'valid-vbinop', r'exec-vbinop', r'op-fpmax'), Instruction(r'\F64X2.\VMAX', r'\hex{FD}~~245', r'[\V128~\V128] \to [\V128]', r'valid-vbinop', r'exec-vbinop', r'op-fmax'), Instruction(r'\I32X4.\TRUNC\K{\_sat\_f32x4\_s}', r'\hex{FD}~~248', r'[\V128] \to [\V128]', r'valid-vunop', r'exec-vunop', r'op-trunc_sat_s'), Instruction(r'\I32X4.\TRUNC\K{\_sat\_f32x4\_u}', r'\hex{FD}~~249', r'[\V128] \to [\V128]', r'valid-vunop', r'exec-vunop', r'op-trunc_sat_u'), diff --git a/document/core/appendix/index-instructions.rst b/document/core/appendix/index-instructions.rst index a6c5e3b03..949bec12e 100644 --- a/document/core/appendix/index-instructions.rst +++ b/document/core/appendix/index-instructions.rst @@ -467,6 +467,8 @@ Instruction Binary Opcode Type :math:`\F32X4.\VDIV` :math:`\hex{FD}~~231` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` :math:`\F32X4.\VMIN` :math:`\hex{FD}~~232` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` :math:`\F32X4.\VMAX` :math:`\hex{FD}~~233` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\F32X4.\VPMIN` :math:`\hex{FD}~~234` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\F32X4.\VPMAX` :math:`\hex{FD}~~235` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` :math:`\F64X2.\VABS` :math:`\hex{FD}~~236` :math:`[\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` :math:`\F64X2.\VNEG` :math:`\hex{FD}~~237` :math:`[\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` :math:`\F64X2.\VSQRT` :math:`\hex{FD}~~239` :math:`[\V128] \to [\I32]` :ref:`validation ` :ref:`execution `, :ref:`operator ` @@ -475,6 +477,8 @@ Instruction Binary Opcode Type :math:`\F64X2.\VMUL` :math:`\hex{FD}~~242` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` :math:`\F64X2.\VDIV` :math:`\hex{FD}~~243` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` :math:`\F64X2.\VMIN` :math:`\hex{FD}~~244` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\F64X2.\VPMIN` :math:`\hex{FD}~~245` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` +:math:`\F64X2.\VPMAX` :math:`\hex{FD}~~246` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` :math:`\F64X2.\VMAX` :math:`\hex{FD}~~245` :math:`[\V128~\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` :math:`\I32X4.\TRUNC\K{\_sat\_f32x4\_s}` :math:`\hex{FD}~~248` :math:`[\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` :math:`\I32X4.\TRUNC\K{\_sat\_f32x4\_u}` :math:`\hex{FD}~~249` :math:`[\V128] \to [\V128]` :ref:`validation ` :ref:`execution `, :ref:`operator ` diff --git a/document/core/binary/instructions.rst b/document/core/binary/instructions.rst index 5370f1584..742434e5e 100644 --- a/document/core/binary/instructions.rst +++ b/document/core/binary/instructions.rst @@ -730,7 +730,9 @@ All other SIMD instructions are plain opcodes without any immediates. \hex{FD}~~230{:}\Bu32 &\Rightarrow& \F32X4.\VMUL \\ &&|& \hex{FD}~~231{:}\Bu32 &\Rightarrow& \F32X4.\VDIV \\ &&|& \hex{FD}~~232{:}\Bu32 &\Rightarrow& \F32X4.\VMIN \\ &&|& - \hex{FD}~~233{:}\Bu32 &\Rightarrow& \F32X4.\VMAX \\ + \hex{FD}~~233{:}\Bu32 &\Rightarrow& \F32X4.\VMAX \\ &&|& + \hex{FD}~~234{:}\Bu32 &\Rightarrow& \F32X4.\VPMIN \\ &&|& + \hex{FD}~~235{:}\Bu32 &\Rightarrow& \F32X4.\VPMAX \\ \end{array} .. math:: @@ -744,7 +746,9 @@ All other SIMD instructions are plain opcodes without any immediates. \hex{FD}~~242{:}\Bu32 &\Rightarrow& \F64X2.\VMUL \\ &&|& \hex{FD}~~243{:}\Bu32 &\Rightarrow& \F64X2.\VDIV \\ &&|& \hex{FD}~~244{:}\Bu32 &\Rightarrow& \F64X2.\VMIN \\ &&|& - \hex{FD}~~245{:}\Bu32 &\Rightarrow& \F64X2.\VMAX \\ + \hex{FD}~~245{:}\Bu32 &\Rightarrow& \F64X2.\VMAX \\ &&|& + \hex{FD}~~245{:}\Bu32 &\Rightarrow& \F64X2.\VPMIN \\ &&|& + \hex{FD}~~246{:}\Bu32 &\Rightarrow& \F64X2.\VPMAX \\ \end{array} .. math:: diff --git a/document/core/exec/numerics.rst b/document/core/exec/numerics.rst index 12d946509..b9c121b99 100644 --- a/document/core/exec/numerics.rst +++ b/document/core/exec/numerics.rst @@ -1675,6 +1675,38 @@ This non-deterministic result is expressed by the following auxiliary function p \end{array} +.. _op-fpmin: + +:math:`\fpmin_N(z_1, z_2)` +.......................... + +* If :math:`z_2` is less than :math:`z_1` then return :math:`z_2`. + +* Else return :math:`z_1`. + +.. math:: + \begin{array}{@{}lcll} + \fpmin_N(z_1, z_2) &=& z_2 & (\iff \flt_N(z_2, z_1) = 1) \\ + \fpmin_N(z_1, z_2) &=& z_1 & (\otherwise) + \end{array} + + +.. _op-fpmax: + +:math:`\fpmax_N(z_1, z_2)` +.......................... + +* If :math:`z_1` is less than :math:`z_2` then return :math:`z_2`. + +* Else return :math:`z_1`. + +.. math:: + \begin{array}{@{}lcll} + \fpmax_N(z_1, z_2) &=& z_2 & (\iff \flt_N(z_1, z_2) = 1) \\ + \fpmax_N(z_1, z_2) &=& z_1 & (\otherwise) + \end{array} + + .. _convert-ops: Conversions diff --git a/document/core/text/instructions.rst b/document/core/text/instructions.rst index 27098757d..2df52d3f8 100644 --- a/document/core/text/instructions.rst +++ b/document/core/text/instructions.rst @@ -763,7 +763,9 @@ SIMD const instructions have a mandatory :ref:`shape ` descri \text{f32x4.mul} &\Rightarrow& \F32X4.\VMUL\\ &&|& \text{f32x4.div} &\Rightarrow& \F32X4.\VDIV\\ &&|& \text{f32x4.min} &\Rightarrow& \F32X4.\VMIN\\ &&|& - \text{f32x4.max} &\Rightarrow& \F32X4.\VMAX\\ + \text{f32x4.max} &\Rightarrow& \F32X4.\VMAX\\ &&|& + \text{f32x4.pmin} &\Rightarrow& \F32X4.\VPMIN\\ &&|& + \text{f32x4.pmax} &\Rightarrow& \F32X4.\VPMAX\\ \end{array} .. math:: @@ -777,7 +779,9 @@ SIMD const instructions have a mandatory :ref:`shape ` descri \text{f64x2.mul} &\Rightarrow& \F64X2.\VMUL\\ &&|& \text{f64x2.div} &\Rightarrow& \F64X2.\VDIV\\ &&|& \text{f64x2.min} &\Rightarrow& \F64X2.\VMIN\\ &&|& - \text{f64x2.max} &\Rightarrow& \F64X2.\VMAX\\ + \text{f64x2.max} &\Rightarrow& \F64X2.\VMAX\\ &&|& + \text{f64x2.pmin} &\Rightarrow& \F64X2.\VPMIN\\ &&|& + \text{f64x2.pmax} &\Rightarrow& \F64X2.\VPMAX\\ \end{array} .. math:: diff --git a/document/core/util/macros.def b/document/core/util/macros.def index f72845275..2822712b6 100644 --- a/document/core/util/macros.def +++ b/document/core/util/macros.def @@ -420,6 +420,8 @@ .. |VDIV| mathdef:: \xref{syntax/instructions}{syntax-instr-simd}{\K{div}} .. |VMIN| mathdef:: \xref{syntax/instructions}{syntax-instr-simd}{\K{min}} .. |VMAX| mathdef:: \xref{syntax/instructions}{syntax-instr-simd}{\K{max}} +.. |VPMIN| mathdef:: \xref{syntax/instructions}{syntax-instr-simd}{\K{pmin}} +.. |VPMAX| mathdef:: \xref{syntax/instructions}{syntax-instr-simd}{\K{pmax}} .. |NARROW| mathdef:: \xref{syntax/instructions}{syntax-instr-simd}{\K{narrow}} .. |WIDEN| mathdef:: \xref{syntax/instructions}{syntax-instr-simd}{\K{widen}} .. |AVGR| mathdef:: \xref{syntax/instructions}{syntax-instr-simd}{\K{avgr}} @@ -1056,6 +1058,8 @@ .. |fgt| mathdef:: \xref{exec/numerics}{op-fgt}{\F{fgt}} .. |fle| mathdef:: \xref{exec/numerics}{op-fle}{\F{fle}} .. |fge| mathdef:: \xref{exec/numerics}{op-fge}{\F{fge}} +.. |fpmin| mathdef:: \xref{exec/numerics}{op-fpmin}{\F{fpmin}} +.. |fpmax| mathdef:: \xref{exec/numerics}{op-fpmax}{\F{fpmax}} .. |extend| mathdef:: \xref{exec/numerics}{op-extend_u}{\F{extend}} .. |extendu| mathdef:: \xref{exec/numerics}{op-extend_u}{\F{extend}^{\K{u}}}