From 0dc46046b0a327756091cddacb70a5a4d4c9a0df Mon Sep 17 00:00:00 2001 From: Deepti Gandluri Date: Tue, 6 Nov 2018 08:31:02 -0800 Subject: [PATCH 1/2] More minor opcode fixups Reserve opcode space for signed, and unsigned min/max, remove explicit `-` for reserved opcodes for consistency. --- proposals/simd/BinarySIMD.md | 151 ++++++++++++++--------------------- 1 file changed, 62 insertions(+), 89 deletions(-) diff --git a/proposals/simd/BinarySIMD.md b/proposals/simd/BinarySIMD.md index bb7a8e427..9cf5156b8 100644 --- a/proposals/simd/BinarySIMD.md +++ b/proposals/simd/BinarySIMD.md @@ -81,16 +81,6 @@ The `v8x16.shuffle` instruction has 16 bytes after `simdop`. | `i32x4.le_u` | `0x33`| - | | `i32x4.ge_s` | `0x34`| - | | `i32x4.ge_u` | `0x35`| - | -| - | `0x36`| - | -| - | `0x37`| - | -| - | `0x38`| - | -| - | `0x39`| - | -| - | `0x3a`| - | -| - | `0x3b`| - | -| - | `0x3c`| - | -| - | `0x3d`| - | -| - | `0x3e`| - | -| - | `0x3f`| - | | `f32x4.eq` | `0x40`| - | | `f32x4.ne` | `0x41`| - | | `f32x4.lt` | `0x42`| - | @@ -115,82 +105,65 @@ The `v8x16.shuffle` instruction has 16 bytes after `simdop`. | `i8x16.sub_saturate_s` | `0x55`| - | | `i8x16.sub_saturate_u` | `0x56`| - | | `i8x16.mul` | `0x57`| - | -| - | `0x58`| - | -| - | `0x59`| - | -| `i8x16.shl` | `0x5a`| - | -| `i8x16.shr_s` | `0x5b`| - | -| `i8x16.shr_u` | `0x5c`| - | -| `i8x16.neg` | `0x5d`| - | -| `i8x16.any_true` | `0x5e`| - | -| `i8x16.all_true` | `0x5f`| - | -| `i16x8.add` | `0x60`| - | -| `i16x8.add_saturate_s` | `0x61`| - | -| `i16x8.add_saturate_u` | `0x62`| - | -| `i16x8.sub` | `0x63`| - | -| `i16x8.sub_saturate_s` | `0x64`| - | -| `i16x8.sub_saturate_u` | `0x65`| - | -| `i16x8.mul` | `0x66`| - | -| - | `0x67`| - | -| - | `0x68`| - | -| `i16x8.shl` | `0x69`| - | -| `i16x8.shr_s` | `0x6a`| - | -| `i16x8.shr_u` | `0x6b`| - | -| `i16x8.neg` | `0x6c`| - | -| `i16x8.any_true` | `0x6d`| - | -| `i16x8.all_true` | `0x6e`| - | -| `i32x4.add` | `0x6f`| - | -| - | `0x70`| - | -| - | `0x71`| - | -| `i32x4.sub` | `0x72`| - | -| - | `0x73`| - | -| - | `0x74`| - | -| `i32x4.mul` | `0x75`| - | -| - | `0x76`| - | -| - | `0x77`| - | -| `i32x4.shl` | `0x78`| - | -| `i32x4.shr_s` | `0x79`| - | -| `i32x4.shr_u` | `0x7a`| - | -| `i32x4.neg` | `0x7b`| - | -| `i32x4.any_true` | `0x7c`| - | -| `i32x4.all_true` | `0x7d`| - | -| `i64x2.add` | `0x7e`| - | -| - | `0x7f`| - | -| - | `0x80`| - | -| `i64x2.sub` | `0x81`| - | -| - | `0x82`| - | -| - | `0x83`| - | -| - | `0x84`| - | -| - | `0x85`| - | -| - | `0x86`| - | -| `i64x2.shl` | `0x87`| - | -| `i64x2.shr_s` | `0x88`| - | -| `i64x2.shr_u` | `0x89`| - | -| `i64x2.neg` | `0x8a`| - | -| `i64x2.any_true` | `0x8b`| - | -| `i64x2.all_true` | `0x8c`| - | -| `f32x4.add` | `0x8d`| - | -| `f32x4.sub` | `0x8e`| - | -| `f32x4.mul` | `0x8f`| - | -| `f32x4.div` | `0x90`| - | -| `f32x4.min` | `0x91`| - | -| `f32x4.max` | `0x92`| - | -| `f32x4.neg` | `0x93`| - | -| `f32x4.abs` | `0x94`| - | -| `f32x4.sqrt` | `0x95`| - | -| `f64x2.add` | `0x96`| - | -| `f64x2.sub` | `0x97`| - | -| `f64x2.mul` | `0x98`| - | -| `f64x2.div` | `0x99`| - | -| `f64x2.min` | `0x9a`| - | -| `f64x2.max` | `0x9b`| - | -| `f64x2.neg` | `0x9c`| - | -| `f64x2.abs` | `0x9d`| - | -| `f64x2.sqrt` | `0x9e`| - | -| `i32x4.trunc_s/f32x4:sat` | `0x9f`| - | -| `i32x4.trunc_u/f32x4:sat` | `0xa0`| - | -| `i64x2.trunc_s/f64x2:sat` | `0xa1`| - | -| `i64x2.trunc_u/f64x2:sat` | `0xa2`| - | -| `f32x4.convert_s/i32x4` | `0xa3`| - | -| `f32x4.convert_u/i32x4` | `0xa4`| - | -| `f64x2.convert_s/i64x2` | `0xa5`| - | -| `f64x2.convert_u/i64x2` | `0xa6`| - | +| `i8x16.shl` | `0x5c`| - | +| `i8x16.shr_s` | `0x5d`| - | +| `i8x16.shr_u` | `0x5e`| - | +| `i8x16.neg` | `0x5f`| - | +| `i8x16.any_true` | `0x60`| - | +| `i8x16.all_true` | `0x61`| - | +| `i16x8.add` | `0x62`| - | +| `i16x8.add_saturate_s` | `0x63`| - | +| `i16x8.add_saturate_u` | `0x64`| - | +| `i16x8.sub` | `0x65`| - | +| `i16x8.sub_saturate_s` | `0x66`| - | +| `i16x8.sub_saturate_u` | `0x67`| - | +| `i16x8.mul` | `0x68`| - | +| `i16x8.shl` | `0x6d`| - | +| `i16x8.shr_s` | `0x6e`| - | +| `i16x8.shr_u` | `0x6f`| - | +| `i16x8.neg` | `0x70`| - | +| `i16x8.any_true` | `0x71`| - | +| `i16x8.all_true` | `0x72`| - | +| `i32x4.add` | `0x73`| - | +| `i32x4.sub` | `0x76`| - | +| `i32x4.mul` | `0x79`| - | +| `i32x4.shl` | `0x7e`| - | +| `i32x4.shr_s` | `0x7f`| - | +| `i32x4.shr_u` | `0x80`| - | +| `i32x4.neg` | `0x81`| - | +| `i32x4.any_true` | `0x82`| - | +| `i32x4.all_true` | `0x83`| - | +| `i64x2.add` | `0x84`| - | +| `i64x2.sub` | `0x87`| - | +| `i64x2.shl` | `0x8f`| - | +| `i64x2.shr_s` | `0x90`| - | +| `i64x2.shr_u` | `0x91`| - | +| `i64x2.neg` | `0x92`| - | +| `i64x2.any_true` | `0x93`| - | +| `i64x2.all_true` | `0x94`| - | +| `f32x4.add` | `0x95`| - | +| `f32x4.sub` | `0x96`| - | +| `f32x4.mul` | `0x97`| - | +| `f32x4.div` | `0x98`| - | +| `f32x4.min` | `0x99`| - | +| `f32x4.max` | `0x9a`| - | +| `f32x4.neg` | `0x9b`| - | +| `f32x4.abs` | `0x9c`| - | +| `f32x4.sqrt` | `0x9d`| - | +| `f64x2.add` | `0x9e`| - | +| `f64x2.sub` | `0x9f`| - | +| `f64x2.mul` | `0xa0`| - | +| `f64x2.div` | `0xa1`| - | +| `f64x2.min` | `0xa2`| - | +| `f64x2.max` | `0xa3`| - | +| `f64x2.neg` | `0xa4`| - | +| `f64x2.abs` | `0xa5`| - | +| `f64x2.sqrt` | `0xa6`| - | +| `i32x4.trunc_s/f32x4:sat` | `0xa7`| - | +| `i32x4.trunc_u/f32x4:sat` | `0xa8`| - | +| `i64x2.trunc_s/f64x2:sat` | `0xa9`| - | +| `i64x2.trunc_u/f64x2:sat` | `0xaa`| - | +| `f32x4.convert_s/i32x4` | `0xab`| - | +| `f32x4.convert_u/i32x4` | `0xac`| - | +| `f64x2.convert_s/i64x2` | `0xad`| - | +| `f64x2.convert_u/i64x2` | `0xae`| - | From 7b355cc1be062d2c78af606639d5a6f459c23b0b Mon Sep 17 00:00:00 2001 From: Deepti Gandluri Date: Tue, 6 Nov 2018 13:19:19 -0800 Subject: [PATCH 2/2] Update BinarySIMD.md Reserving a couple more opcodes for floating point RecipApprox, and RecipSqrtApprox. --- proposals/simd/BinarySIMD.md | 34 +++++++++++++++++----------------- 1 file changed, 17 insertions(+), 17 deletions(-) diff --git a/proposals/simd/BinarySIMD.md b/proposals/simd/BinarySIMD.md index 9cf5156b8..1c0610fd0 100644 --- a/proposals/simd/BinarySIMD.md +++ b/proposals/simd/BinarySIMD.md @@ -150,20 +150,20 @@ The `v8x16.shuffle` instruction has 16 bytes after `simdop`. | `f32x4.neg` | `0x9b`| - | | `f32x4.abs` | `0x9c`| - | | `f32x4.sqrt` | `0x9d`| - | -| `f64x2.add` | `0x9e`| - | -| `f64x2.sub` | `0x9f`| - | -| `f64x2.mul` | `0xa0`| - | -| `f64x2.div` | `0xa1`| - | -| `f64x2.min` | `0xa2`| - | -| `f64x2.max` | `0xa3`| - | -| `f64x2.neg` | `0xa4`| - | -| `f64x2.abs` | `0xa5`| - | -| `f64x2.sqrt` | `0xa6`| - | -| `i32x4.trunc_s/f32x4:sat` | `0xa7`| - | -| `i32x4.trunc_u/f32x4:sat` | `0xa8`| - | -| `i64x2.trunc_s/f64x2:sat` | `0xa9`| - | -| `i64x2.trunc_u/f64x2:sat` | `0xaa`| - | -| `f32x4.convert_s/i32x4` | `0xab`| - | -| `f32x4.convert_u/i32x4` | `0xac`| - | -| `f64x2.convert_s/i64x2` | `0xad`| - | -| `f64x2.convert_u/i64x2` | `0xae`| - | +| `f64x2.add` | `0xa0`| - | +| `f64x2.sub` | `0xa1`| - | +| `f64x2.mul` | `0xa2`| - | +| `f64x2.div` | `0xa3`| - | +| `f64x2.min` | `0xa4`| - | +| `f64x2.max` | `0xa5`| - | +| `f64x2.neg` | `0xa6`| - | +| `f64x2.abs` | `0xa7`| - | +| `f64x2.sqrt` | `0xa8`| - | +| `i32x4.trunc_s/f32x4:sat` | `0xab`| - | +| `i32x4.trunc_u/f32x4:sat` | `0xac`| - | +| `i64x2.trunc_s/f64x2:sat` | `0xad`| - | +| `i64x2.trunc_u/f64x2:sat` | `0xae`| - | +| `f32x4.convert_s/i32x4` | `0xaf`| - | +| `f32x4.convert_u/i32x4` | `0xb0`| - | +| `f64x2.convert_s/i64x2` | `0xb1`| - | +| `f64x2.convert_u/i64x2` | `0xb2`| - |