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[RISCV64] Support logical operations with immediates on BaseIndex add…
…resses in LLInt

https://bugs.webkit.org/show_bug.cgi?id=231734

Patch by Zan Dobersek <zdobersek@igalia.com> on 2021-10-14
Reviewed by Yusuke Suzuki.

RISCV64 offlineasm implementation gains support for performing logical
operations with immediate values on BaseIndex adresses, fixing the build
and bringing things back into operational state.

For this to function properly, BaseIndex loading is reworked so that no
additional scratch register is necessary for computing the target
address.

* offlineasm/riscv64.rb:

Canonical link: https://commits.webkit.org/242996@main
git-svn-id: https://svn.webkit.org/repository/webkit/trunk@284179 268f45cc-cd09-0410-ab3c-d52691b4dbfc
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commit-queue@webkit.org committed Oct 14, 2021
1 parent e577238 commit 2c412363fafadd9abffed7005161328c7bf9c3c7
Showing 2 changed files with 46 additions and 14 deletions.
@@ -1,3 +1,20 @@
2021-10-14 Zan Dobersek <zdobersek@igalia.com>

[RISCV64] Support logical operations with immediates on BaseIndex addresses in LLInt
https://bugs.webkit.org/show_bug.cgi?id=231734

Reviewed by Yusuke Suzuki.

RISCV64 offlineasm implementation gains support for performing logical
operations with immediate values on BaseIndex adresses, fixing the build
and bringing things back into operational state.

For this to function properly, BaseIndex loading is reworked so that no
additional scratch register is necessary for computing the target
address.

* offlineasm/riscv64.rb:

2021-10-14 Commit Queue <commit-queue@webkit.org>

Unreviewed, reverting r284151.
@@ -214,7 +214,7 @@ def riscv64EmitLoad(operands, type, mask)
$asm.puts "#{instruction} #{operands[1].riscv64Operand}, #{operands[0].riscv64Operand}"
end
when [BaseIndex, RegisterID]
operands[0].riscv64Load(RISCV64ScratchRegister.x31, RISCV64ScratchRegister.x30)
operands[0].riscv64Load(RISCV64ScratchRegister.x31)
$asm.puts "#{instruction} #{operands[1].riscv64Operand}, 0(x31)"
else
riscv64RaiseMismatchedOperands(operands)
@@ -241,7 +241,7 @@ def riscv64EmitStore(operands, type)
$asm.puts "#{instruction} #{operands[0].riscv64Operand}, #{operands[1].riscv64Operand}"
end
when [RegisterID, BaseIndex]
operands[1].riscv64Load(RISCV64ScratchRegister.x31, RISCV64ScratchRegister.x30)
operands[1].riscv64Load(RISCV64ScratchRegister.x31)
$asm.puts "#{instruction} #{operands[0].riscv64Operand}, 0(x31)"
when [Immediate, Address]
$asm.puts "li x30, #{operands[0].riscv64Operand}"
@@ -252,7 +252,7 @@ def riscv64EmitStore(operands, type)
$asm.puts "#{instruction} x30, #{operands[1].riscv64Operand}"
end
when [Immediate, BaseIndex]
operands[1].riscv64Load(RISCV64ScratchRegister.x31, RISCV64ScratchRegister.x30)
operands[1].riscv64Load(RISCV64ScratchRegister.x31)
$asm.puts "li x30, #{operands[0].riscv64Operand}"
$asm.puts "#{instruction} x30, 0(x31)"
else
@@ -400,7 +400,7 @@ def signExtendForSize(register, target, size)
end
$asm.puts "#{instruction} x30, x31, #{operands[2].asmLabel}"
when [RegisterID, BaseIndex, LocalLabelReference]
operands[1].riscv64Load(RISCV64ScratchRegister.x31, RISCV64ScratchRegister.x30)
operands[1].riscv64Load(RISCV64ScratchRegister.x31)
$asm.puts "#{riscv64LoadInstruction(size)} x31, 0(x31)"
signExtendForSize(operands[0], 'x30', size)
$asm.puts "#{instruction} x30, x31, #{operands[2].asmLabel}"
@@ -507,7 +507,7 @@ def signExtendForSize(target, size)
signExtendForSize('x31', size)
$asm.puts "#{bInstruction} x31, #{operands[2].asmLabel}"
when [BaseIndex, LocalLabelReference]
operands[0].riscv64Load(RISCV64ScratchRegister.x31, RISCV64ScratchRegister.x30)
operands[0].riscv64Load(RISCV64ScratchRegister.x31)
$asm.puts "#{loadInstruction} x31, 0(x31)"
$asm.puts "#{bInstruction} x31, #{operands[1].asmLabel}"
else
@@ -874,6 +874,17 @@ def opInstruction(operation)
else
$asm.puts "#{storeInstruction} x30, #{operands[1].riscv64Operand}"
end
when [Immediate, BaseIndex]
operands[1].riscv64Load(RISCV64ScratchRegister.x31)
$asm.puts "#{loadInstruction} x30, 0(x31)"
if operands[0].riscv64RequiresLoad
$asm.puts "li x31, #{operands[0].riscv64Operand}"
$asm.puts "#{instruction} x30, x30, x31"
operands[1].riscv64Load(RISCV64ScratchRegister.x31)
else
$asm.puts "#{instruction}i x30, x30, #{operands[0].riscv64Operand}"
end
$asm.puts "#{storeInstruction} x30, 0(x31)"
else
riscv64RaiseMismatchedOperands(operands)
end
@@ -967,7 +978,7 @@ def riscv64EmitFPLoad(operands, loadInstruction)
$asm.puts "#{loadInstruction} #{operands[1].riscv64Operand}, #{operands[0].riscv64Operand}"
end
when [BaseIndex, FPRegisterID]
operands[0].riscv64Load(RISCV64ScratchRegister.x31, RISCV64ScratchRegister.x30)
operands[0].riscv64Load(RISCV64ScratchRegister.x31)
$asm.puts "#{loadInstruction} #{operands[1].riscv64Operand}, 0(x31)"
else
riscv64RaiseMismatchedOperands(operands)
@@ -984,7 +995,7 @@ def riscv64EmitFPStore(operands, storeInstruction)
$asm.puts "#{storeInstruction} #{operands[0].riscv64Operand}, #{operands[1].riscv64Operand}"
end
when [FPRegisterID, BaseIndex]
operands[1].riscv64Load(RISCV64ScratchRegister.x31, RISCV64ScratchRegister.x30)
operands[1].riscv64Load(RISCV64ScratchRegister.x31)
$asm.puts "#{storeInstruction} #{operands[0].riscv64Operand}, 0(x31)"
else
riscv64RaiseMismatchedOperands(operands)
@@ -1434,14 +1445,18 @@ def riscv64Load(target)
end

class BaseIndex
def riscv64Load(target, scratch)
def riscv64Load(target)
case riscv64OperandTypes([base, index])
when [RegisterID, RegisterID]
$asm.puts "slli #{target.riscv64Operand}, #{index.riscv64Operand}, #{scaleShift}"
$asm.puts "add #{target.riscv64Operand}, #{base.riscv64Operand}, #{target.riscv64Operand}"
if offset.value != 0
$asm.puts "li #{scratch.riscv64Operand}, #{offset.value}"
$asm.puts "add #{target.riscv64Operand}, #{target.riscv64Operand}, #{scratch.riscv64Operand}"
$asm.puts "li #{target.riscv64Operand}, #{offset.value >> scaleShift}"
$asm.puts "add #{target.riscv64Operand}, #{target.riscv64Operand}, #{index.riscv64Operand}"
$asm.puts "slli #{target.riscv64Operand}, #{target.riscv64Operand}, #{scaleShift}"
$asm.puts "ori #{target.riscv64Operand}, #{target.riscv64Operand}, #{offset.value & ((1 << scaleShift) - 1)}"
$asm.puts "add #{target.riscv64Operand}, #{base.riscv64Operand}, #{target.riscv64Operand}"
else
$asm.puts "slli #{target.riscv64Operand}, #{index.riscv64Operand}, #{scaleShift}"
$asm.puts "add #{target.riscv64Operand}, #{base.riscv64Operand}, #{target.riscv64Operand}"
end
else
riscv64RaiseMismatchedOperands([base, index])
@@ -1730,7 +1745,7 @@ def lowerRISCV64
when [RegisterID, Immediate]
$asm.puts "jr #{operands[0].riscv64Operand}"
when [BaseIndex, Immediate, Immediate]
operands[0].riscv64Load(RISCV64ScratchRegister.x31, RISCV64ScratchRegister.x30)
operands[0].riscv64Load(RISCV64ScratchRegister.x31)
$asm.puts "ld x31, 0(x31)"
$asm.puts "jr x31"
when [Address, Immediate]
@@ -1859,7 +1874,7 @@ def lowerRISCV64
$asm.puts "addi #{operands[1].riscv64Operand}, #{operands[0].base.riscv64Operand}, #{operands[0].offset.value}"
end
when [BaseIndex, RegisterID]
operands[0].riscv64Load(RISCV64ScratchRegister.x31, RISCV64ScratchRegister.x30)
operands[0].riscv64Load(RISCV64ScratchRegister.x31)
$asm.puts "mv #{operands[1].riscv64Operand}, x31"
when [LabelReference, RegisterID]
$asm.puts "lla #{operands[1].riscv64Operand}, #{operands[0].asmLabel}"

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