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X86_64 support for compareDouble(DoubleCondition, FPRegisterID left, …
…FPRegisterID right, RegisterID dest)

https://bugs.webkit.org/show_bug.cgi?id=151009

Reviewed by Filip Pizlo.

Added compareDouble() macro assembler function and the supporting setnp_r() and setp_r() X86 assembler functions.
Hand tested.

* assembler/MacroAssemblerX86_64.h:
(JSC::MacroAssemblerX86_64::compare64):
(JSC::MacroAssemblerX86_64::compareDouble):
(JSC::MacroAssemblerX86_64::branch64):
* assembler/X86Assembler.h:
(JSC::X86Assembler::setnz_r):
(JSC::X86Assembler::setnp_r):
(JSC::X86Assembler::setp_r):
(JSC::X86Assembler::cdq):


Canonical link: https://commits.webkit.org/169303@main
git-svn-id: https://svn.webkit.org/repository/webkit/trunk@192267 268f45cc-cd09-0410-ab3c-d52691b4dbfc
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msaboff committed Nov 10, 2015
1 parent 6e48fb4 commit 82e8f5d55a64ff3fd64712ba6852b9517bd45859
Showing with 65 additions and 1 deletion.
  1. +20 −0 Source/JavaScriptCore/ChangeLog
  2. +35 −1 Source/JavaScriptCore/assembler/MacroAssemblerX86_64.h
  3. +10 −0 Source/JavaScriptCore/assembler/X86Assembler.h
@@ -1,3 +1,23 @@
2015-11-10 Michael Saboff <msaboff@apple.com>

X86_64 support for compareDouble(DoubleCondition, FPRegisterID left, FPRegisterID right, RegisterID dest)
https://bugs.webkit.org/show_bug.cgi?id=151009

Reviewed by Filip Pizlo.

Added compareDouble() macro assembler function and the supporting setnp_r() and setp_r() X86 assembler functions.
Hand tested.

* assembler/MacroAssemblerX86_64.h:
(JSC::MacroAssemblerX86_64::compare64):
(JSC::MacroAssemblerX86_64::compareDouble):
(JSC::MacroAssemblerX86_64::branch64):
* assembler/X86Assembler.h:
(JSC::X86Assembler::setnz_r):
(JSC::X86Assembler::setnp_r):
(JSC::X86Assembler::setp_r):
(JSC::X86Assembler::cdq):

2015-11-10 Saam barati <sbarati@apple.com>

Rename FTL's ExitArgumentList to something more indicative of what it is
@@ -577,7 +577,41 @@ class MacroAssemblerX86_64 : public MacroAssemblerX86Common {
m_assembler.setCC_r(x86Condition(cond), dest);
m_assembler.movzbl_rr(dest, dest);
}


void compareDouble(DoubleCondition cond, FPRegisterID left, FPRegisterID right, RegisterID dest)
{
if (cond & DoubleConditionBitInvert)
m_assembler.ucomisd_rr(left, right);
else
m_assembler.ucomisd_rr(right, left);

if (cond == DoubleEqual) {
if (left == right) {
m_assembler.setnp_r(dest);
return;
}

Jump isUnordered(m_assembler.jp());
m_assembler.sete_r(dest);
isUnordered.link(this);
return;
}

if (cond == DoubleNotEqualOrUnordered) {
if (left == right) {
m_assembler.setp_r(dest);
return;
}

m_assembler.setp_r(dest);
m_assembler.setne_r(dest);
return;
}

ASSERT(!(cond & DoubleConditionBitSpecial));
m_assembler.setCC_r(static_cast<X86Assembler::Condition>(cond & ~DoubleConditionBits), dest);
}

Jump branch64(RelationalCondition cond, RegisterID left, RegisterID right)
{
m_assembler.cmpq_rr(right, left);
@@ -1277,6 +1277,16 @@ class X86Assembler {
setne_r(dst);
}

void setnp_r(RegisterID dst)
{
m_formatter.twoByteOp8(setccOpcode(ConditionNP), (GroupOpcodeID)0, dst);
}

void setp_r(RegisterID dst)
{
m_formatter.twoByteOp8(setccOpcode(ConditionP), (GroupOpcodeID)0, dst);
}

// Various move ops:

void cdq()

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