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Make all register enums be backed by uint8_t.
https://bugs.webkit.org/show_bug.cgi?id=179074

Reviewed by Mark Lam.

* assembler/ARM64Assembler.h:
* assembler/ARMAssembler.h:
* assembler/ARMv7Assembler.h:
* assembler/MIPSAssembler.h:
* assembler/MacroAssembler.h:
* assembler/X86Assembler.h:


Canonical link: https://commits.webkit.org/195202@main
git-svn-id: https://svn.webkit.org/repository/webkit/trunk@224246 268f45cc-cd09-0410-ab3c-d52691b4dbfc
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kmiller68 committed Oct 31, 2017
1 parent 9d0cd94 commit 8d8f73f64cd3be0cd9718cb63b3d27406fef8db8
Showing 7 changed files with 40 additions and 26 deletions.
@@ -1,3 +1,17 @@
2017-10-31 Keith Miller <keith_miller@apple.com>

Make all register enums be backed by uint8_t.
https://bugs.webkit.org/show_bug.cgi?id=179074

Reviewed by Mark Lam.

* assembler/ARM64Assembler.h:
* assembler/ARMAssembler.h:
* assembler/ARMv7Assembler.h:
* assembler/MIPSAssembler.h:
* assembler/MacroAssembler.h:
* assembler/X86Assembler.h:

2017-10-31 Keith Miller <keith_miller@apple.com>

StructureStubInfo should have GPRReg members not int8_ts
@@ -205,16 +205,16 @@ enum RegisterID : uint8_t {
zr = 0x3f,
};

typedef enum {
enum SPRegisterID : uint8_t {
pc,
nzcv,
fpsr
} SPRegisterID;
};

// ARM64 always has 32 FPU registers 128-bits each. See http://llvm.org/devmtg/2012-11/Northover-AArch64.pdf
// and Section 5.1.2 in http://infocenter.arm.com/help/topic/com.arm.doc.ihi0055b/IHI0055B_aapcs64.pdf.
// However, we only use them for 64-bit doubles.
typedef enum {
enum FPRegisterID : uint8_t {
// Parameter/result registers.
q0,
q1,
@@ -250,7 +250,7 @@ typedef enum {
q29,
q30,
q31,
} FPRegisterID;
};

static constexpr bool isSp(RegisterID reg) { return reg == sp; }
static constexpr bool isZr(RegisterID reg) { return reg == zr; }
@@ -65,12 +65,12 @@ namespace JSC {
r15 = pc
};

typedef enum {
enum SPRegisterID : uint8_t {
apsr,
fpscr
} SPRegisterID;
};

typedef enum {
enum FPRegisterID : uint8_t {
d0,
d1,
d2,
@@ -108,7 +108,7 @@ namespace JSC {

// Pseudonyms for some of the registers.
SD0 = d7, /* Same as thumb assembler. */
} FPRegisterID;
};

} // namespace ARMRegisters

@@ -66,12 +66,12 @@ enum RegisterID : uint8_t {
pc = r15
};

typedef enum {
enum SPRegisterID : uint8_t {
apsr,
fpscr
} SPRegisterID;
};

typedef enum {
enum FPSingleRegisterID : uint8_t {
s0,
s1,
s2,
@@ -104,9 +104,9 @@ typedef enum {
s29,
s30,
s31,
} FPSingleRegisterID;
};

typedef enum {
enum FPDoubleRegisterID : uint8_t {
d0,
d1,
d2,
@@ -141,10 +141,10 @@ typedef enum {
d30,
d31,
#endif // CPU(ARM_NEON) || CPU(ARM_VFP_V3_D32)
} FPDoubleRegisterID;
};

#if CPU(ARM_NEON)
typedef enum {
enum FPQuadRegisterID : uint8_t {
q0,
q1,
q2,
@@ -161,7 +161,7 @@ typedef enum {
q13,
q14,
q15,
} FPQuadRegisterID;
};
#endif // CPU(ARM_NEON)

inline FPSingleRegisterID asSingle(FPDoubleRegisterID reg)
@@ -110,12 +110,12 @@ enum RegisterID : uint8_t {
};

// Currently, we don't have support for any special purpose registers.
typedef enum {
enum SPRegisterID : uint8_t {
firstInvalidSPR,
lastInvalidSPR = -1,
} SPRegisterID;
};

typedef enum {
enum FPRegisterID : uint8_t {
f0,
f1,
f2,
@@ -148,7 +148,7 @@ typedef enum {
f29,
f30,
f31
} FPRegisterID;
};

} // namespace MIPSRegisters

@@ -1921,8 +1921,8 @@ class MacroAssembler {

public:

enum RegisterID { NoRegister };
enum FPRegisterID { NoFPRegister };
enum RegisterID : uint8_t { NoRegister };
enum FPRegisterID : uint8_t { NoFPRegister };
};

} // namespace JSC
@@ -62,12 +62,12 @@ enum RegisterID : uint8_t {
#endif
};

typedef enum {
enum SPRegisterID : uint8_t {
eip,
eflags
} SPRegisterID;
};

typedef enum {
enum XMMRegisterID : uint8_t {
xmm0,
xmm1,
xmm2,
@@ -86,7 +86,7 @@ typedef enum {
xmm14,
xmm15
#endif
} XMMRegisterID;
};

} // namespace X86Register

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