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Unreviewed, rolling out r224243, r224246, and r224248.
https://bugs.webkit.org/show_bug.cgi?id=179083

The patch and fix broke the Windows build. (Requested by
mlewis13 on #webkit).

Reverted changesets:

"StructureStubInfo should have GPRReg members not int8_ts"
https://bugs.webkit.org/show_bug.cgi?id=179071
https://trac.webkit.org/changeset/224243

"Make all register enums be backed by uint8_t."
https://bugs.webkit.org/show_bug.cgi?id=179074
https://trac.webkit.org/changeset/224246

"Unreviewed, windows build fix."
https://trac.webkit.org/changeset/224248

Canonical link: https://commits.webkit.org/195210@main
git-svn-id: https://svn.webkit.org/repository/webkit/trunk@224258 268f45cc-cd09-0410-ab3c-d52691b4dbfc
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webkit-commit-queue committed Oct 31, 2017
1 parent 6809597 commit b23769da659ae899c61bfb548eb85e5bfa1c5602
Showing 13 changed files with 210 additions and 190 deletions.
@@ -1,3 +1,24 @@
2017-10-31 Commit Queue <commit-queue@webkit.org>

Unreviewed, rolling out r224243, r224246, and r224248.
https://bugs.webkit.org/show_bug.cgi?id=179083

The patch and fix broke the Windows build. (Requested by
mlewis13 on #webkit).

Reverted changesets:

"StructureStubInfo should have GPRReg members not int8_ts"
https://bugs.webkit.org/show_bug.cgi?id=179071
https://trac.webkit.org/changeset/224243

"Make all register enums be backed by uint8_t."
https://bugs.webkit.org/show_bug.cgi?id=179074
https://trac.webkit.org/changeset/224246

"Unreviewed, windows build fix."
https://trac.webkit.org/changeset/224248

2017-10-31 Tim Horton <timothy_horton@apple.com>

Fix up some content filtering feature flags
@@ -157,7 +157,7 @@ inline uint16_t getHalfword(uint64_t value, int which)

namespace ARM64Registers {

enum RegisterID : uint8_t {
typedef enum {
// Parameter/result registers.
x0,
x1,
@@ -203,18 +203,18 @@ enum RegisterID : uint8_t {
x29 = fp,
x30 = lr,
zr = 0x3f,
};
} RegisterID;

enum SPRegisterID : uint8_t {
typedef enum {
pc,
nzcv,
fpsr
};
} SPRegisterID;

// ARM64 always has 32 FPU registers 128-bits each. See http://llvm.org/devmtg/2012-11/Northover-AArch64.pdf
// and Section 5.1.2 in http://infocenter.arm.com/help/topic/com.arm.doc.ihi0055b/IHI0055B_aapcs64.pdf.
// However, we only use them for 64-bit doubles.
enum FPRegisterID : uint8_t {
typedef enum {
// Parameter/result registers.
q0,
q1,
@@ -250,7 +250,7 @@ enum FPRegisterID : uint8_t {
q29,
q30,
q31,
};
} FPRegisterID;

static constexpr bool isSp(RegisterID reg) { return reg == sp; }
static constexpr bool isZr(RegisterID reg) { return reg == zr; }
@@ -38,7 +38,7 @@ namespace JSC {

namespace ARMRegisters {

enum RegisterID : uint8_t {
typedef enum {
r0,
r1,
r2,
@@ -63,14 +63,14 @@ namespace JSC {
r13 = sp,
r14 = lr,
r15 = pc
};
} RegisterID;

enum SPRegisterID : uint8_t {
typedef enum {
apsr,
fpscr
};
} SPRegisterID;

enum FPRegisterID : uint8_t {
typedef enum {
d0,
d1,
d2,
@@ -108,7 +108,7 @@ namespace JSC {

// Pseudonyms for some of the registers.
SD0 = d7, /* Same as thumb assembler. */
};
} FPRegisterID;

} // namespace ARMRegisters

@@ -39,142 +39,142 @@ namespace JSC {

namespace ARMRegisters {

enum RegisterID : uint8_t {
r0,
r1,
r2,
r3,
r4,
r5,
r6,
r7,
r8,
r9,
r10,
r11,
r12,
r13,
r14,
r15,

fp = r7, // frame pointer
sb = r9, // static base
sl = r10, // stack limit
ip = r12,
sp = r13,
lr = r14,
pc = r15
};
typedef enum {
r0,
r1,
r2,
r3,
r4,
r5,
r6,
r7,
r8,
r9,
r10,
r11,
r12,
r13,
r14,
r15,

fp = r7, // frame pointer
sb = r9, // static base
sl = r10, // stack limit
ip = r12,
sp = r13,
lr = r14,
pc = r15
} RegisterID;

enum SPRegisterID : uint8_t {
apsr,
fpscr
};
typedef enum {
apsr,
fpscr
} SPRegisterID;

enum FPSingleRegisterID : uint8_t {
s0,
s1,
s2,
s3,
s4,
s5,
s6,
s7,
s8,
s9,
s10,
s11,
s12,
s13,
s14,
s15,
s16,
s17,
s18,
s19,
s20,
s21,
s22,
s23,
s24,
s25,
s26,
s27,
s28,
s29,
s30,
s31,
};
typedef enum {
s0,
s1,
s2,
s3,
s4,
s5,
s6,
s7,
s8,
s9,
s10,
s11,
s12,
s13,
s14,
s15,
s16,
s17,
s18,
s19,
s20,
s21,
s22,
s23,
s24,
s25,
s26,
s27,
s28,
s29,
s30,
s31,
} FPSingleRegisterID;

enum FPDoubleRegisterID : uint8_t {
d0,
d1,
d2,
d3,
d4,
d5,
d6,
d7,
d8,
d9,
d10,
d11,
d12,
d13,
d14,
d15,
typedef enum {
d0,
d1,
d2,
d3,
d4,
d5,
d6,
d7,
d8,
d9,
d10,
d11,
d12,
d13,
d14,
d15,
#if CPU(ARM_NEON) || CPU(ARM_VFP_V3_D32)
d16,
d17,
d18,
d19,
d20,
d21,
d22,
d23,
d24,
d25,
d26,
d27,
d28,
d29,
d30,
d31,
d16,
d17,
d18,
d19,
d20,
d21,
d22,
d23,
d24,
d25,
d26,
d27,
d28,
d29,
d30,
d31,
#endif // CPU(ARM_NEON) || CPU(ARM_VFP_V3_D32)
};
} FPDoubleRegisterID;

#if CPU(ARM_NEON)
enum FPQuadRegisterID : uint8_t {
q0,
q1,
q2,
q3,
q4,
q5,
q6,
q7,
q8,
q9,
q10,
q11,
q12,
q13,
q14,
q15,
};
typedef enum {
q0,
q1,
q2,
q3,
q4,
q5,
q6,
q7,
q8,
q9,
q10,
q11,
q12,
q13,
q14,
q15,
} FPQuadRegisterID;
#endif // CPU(ARM_NEON)

inline FPSingleRegisterID asSingle(FPDoubleRegisterID reg)
{
ASSERT(reg < d16);
return (FPSingleRegisterID)(reg << 1);
}

inline FPDoubleRegisterID asDouble(FPSingleRegisterID reg)
{
ASSERT(!(reg & 1));
return (FPDoubleRegisterID)(reg >> 1);
}
inline FPSingleRegisterID asSingle(FPDoubleRegisterID reg)
{
ASSERT(reg < d16);
return (FPSingleRegisterID)(reg << 1);
}

inline FPDoubleRegisterID asDouble(FPSingleRegisterID reg)
{
ASSERT(!(reg & 1));
return (FPDoubleRegisterID)(reg >> 1);
}

} // namespace ARMRegisters

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