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Add a new pattern to instruction selector to utilize SMADDL supported…
… by ARM64 https://bugs.webkit.org/show_bug.cgi?id=227188 Patch by Yijia Huang <yijia_huang@apple.com> on 2021-06-22 Reviewed by Saam Barati. Signed Multiply-Add Long(SMADDL), supported by ARM64, multiplies two 32-bit register values, adds a 64-bit register value, and writes the result to the 64-bit destination register. The instruction selector can utilize this to lowering certain patterns in B3 IR before further Air optimization. Given the operation: smaddl d, n, m, a The equivalent patterns would be: d = a + SExt32(n) * SExt32(m) d = SExt32(n) * SExt32(m) + a Given B3 IR: Int @0 = ArgumentReg(%x0) Int @1 = SExt32(Trunc(ArgumentReg(%x1))) Int @2 = SExt32(Trunc(ArgumentReg(%x2))) Int @3 = Mul(@1, @2) Int @4 = Add(@0, @3) Void@5 = Return(@4, Terminal) Before Adding SMADDL: // Old optimized AIR SignExtend32ToPtr %x1, %x1, @1 SignExtend32ToPtr %x2, %x2, @2 MultiplyAdd64 %x1, %x2, %x0, %x0, @4 Ret64 %x0, @5 After Adding SMADDL: // New optimized AIR MultiplyAddSignExtend32 %x1, %x2, %x0, %x0, @8 Ret64 %x0, @9 * assembler/MacroAssemblerARM64.h: (JSC::MacroAssemblerARM64::multiplyAddSignExtend32): * assembler/testmasm.cpp: (JSC::testMultiplyAddSignExtend32Left): (JSC::testMultiplyAddSignExtend32Right): * b3/B3LowerToAir.cpp: * b3/air/AirOpcode.opcodes: * b3/testb3.h: * b3/testb3_2.cpp: (testMulAddArg): (testMulAddArgsLeft): (testMulAddArgsRight): (testMulAddSignExtend32ArgsLeft): (testMulAddSignExtend32ArgsRight): (testMulAddArgsLeft32): (testMulAddArgsRight32): * b3/testb3_3.cpp: (addArgTests): Canonical link: https://commits.webkit.org/239048@main git-svn-id: https://svn.webkit.org/repository/webkit/trunk@279134 268f45cc-cd09-0410-ab3c-d52691b4dbfc
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