[WebAssembly SIMD] Emulate vector floating-point absolute value on Intel

https://bugs.webkit.org/show_bug.cgi?id=249038
rdar://103189245

Reviewed by Justin Michaud.

Adds an Air lower macro implementation for vectorized floating-point absolute
value on Intel.

* Source/JavaScriptCore/assembler/MacroAssemblerX86_64.h:
(JSC::MacroAssemblerX86_64::vectorAbs):
* Source/JavaScriptCore/b3/air/AirLowerMacros.cpp:
(JSC::B3::Air::lowerMacros):

Canonical link: https://commits.webkit.org/257806@main

Source/JavaScriptCore/assembler/MacroAssemblerX86_64.h

@@ -2808,6 +2808,10 @@ class MacroAssemblerX86_64 : public MacroAssemblerX86Common {
                 RELEASE_ASSERT_NOT_REACHED();
             }
             return;
+        case SIMDLane::f32x4:
+        case SIMDLane::f64x2:
+            RELEASE_ASSERT_NOT_REACHED_WITH_MESSAGE("f32 and f64 vector absolute value are not supported on x86, so this should have been expanded out prior to reaching the macro assembler.");
+            return;
         default:
             RELEASE_ASSERT_NOT_REACHED();
         }

Source/JavaScriptCore/b3/air/AirLowerMacros.cpp

@@ -255,6 +255,36 @@ void lowerMacros(Code& code)
                 inst = Inst();
             };
 
+            auto handleVectorAbs = [&] {
+                SIMDInfo simdInfo = inst.args[0].simdInfo();
+
+                if (!isX86() || !scalarTypeIsFloatingPoint(simdInfo.lane))
+                    return;
+
+                // Intel doesn't have a vector absolute-value instruction for floats, so we have to manually
+                // set the sign bit.
+
+                Tmp vec = inst.args[0].tmp();
+                Tmp dst = inst.args[1].tmp();
+                auto* origin = inst.origin;
+
+                Tmp fptmp = code.newTmp(FP);
+                Tmp gptmp = code.newTmp(GP);
+
+                if (simdInfo.lane == SIMDLane::f32x4) {
+                    insertionSet.insert(instIndex, Move, origin, Arg::imm(0x7fffffff), gptmp);
+                    insertionSet.insert(instIndex, Move32ToFloat, origin, gptmp, fptmp);
+                    insertionSet.insert(instIndex, VectorSplatFloat32, origin, fptmp, fptmp);
+                } else {
+                    insertionSet.insert(instIndex, Move, origin, Arg::bigImm(0x7fffffffffffffff), gptmp);
+                    insertionSet.insert(instIndex, Move64ToDouble, origin, gptmp, fptmp);
+                    insertionSet.insert(instIndex, VectorSplatFloat64, origin, fptmp, fptmp);
+                }
+                insertionSet.insert(instIndex, VectorAnd, origin, Arg::simdInfo(simdInfo), vec, fptmp, dst);
+
+                inst = Inst();
+            };
+
             auto handleVectorBitmask = [&] {
                 if (!isARM64())
                     return;
@@ -340,6 +370,9 @@ void lowerMacros(Code& code)
             case VectorAnyTrue:
                 handleVectorAnyTrue();
                 break;
+            case VectorAbs:
+                handleVectorAbs();
+                break;
             case VectorMul:
                 handleVectorMul();
                 break;