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[ARM64] Use link register instead of pinning a register for materiali…
…zing big load constants

https://bugs.webkit.org/show_bug.cgi?id=228710

Reviewed by Mark Lam.

Previously, we pin a register as a temp for materializing a large constant that cannot fit in
Load/Store imm form. This is not efficient since the register allocator has one less register
to allocate from. To solve this problem, we should switch to using the link register as the temp
on ARM64.

* b3/B3Common.cpp:
(JSC::B3::linkRegister):
(JSC::B3::pinnedExtendedOffsetAddrRegister): Deleted.
* b3/B3Common.h:
* b3/air/AirAllocateRegistersAndStackAndGenerateCode.cpp:
(JSC::B3::Air::callFrameAddr):
* b3/air/AirCode.cpp:
(JSC::B3::Air::Code::Code):
* b3/air/AirLowerStackArgs.cpp:
(JSC::B3::Air::lowerStackArgs):


Canonical link: https://commits.webkit.org/240227@main
git-svn-id: https://svn.webkit.org/repository/webkit/trunk@280609 268f45cc-cd09-0410-ab3c-d52691b4dbfc
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Yijia Huang committed Aug 3, 2021
1 parent 70f524b commit f685cb3722f858e027bc11cf0c3f1c29851d36b8
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Showing 6 changed files with 30 additions and 12 deletions.
@@ -1,3 +1,26 @@
2021-08-03 Yijia Huang <yijia_huang@apple.com>

[ARM64] Use link register instead of pinning a register for materializing big load constants
https://bugs.webkit.org/show_bug.cgi?id=228710

Reviewed by Mark Lam.

Previously, we pin a register as a temp for materializing a large constant that cannot fit in
Load/Store imm form. This is not efficient since the register allocator has one less register
to allocate from. To solve this problem, we should switch to using the link register as the temp
on ARM64.

* b3/B3Common.cpp:
(JSC::B3::linkRegister):
(JSC::B3::pinnedExtendedOffsetAddrRegister): Deleted.
* b3/B3Common.h:
* b3/air/AirAllocateRegistersAndStackAndGenerateCode.cpp:
(JSC::B3::Air::callFrameAddr):
* b3/air/AirCode.cpp:
(JSC::B3::Air::Code::Code):
* b3/air/AirLowerStackArgs.cpp:
(JSC::B3::Air::lowerStackArgs):

2021-08-02 Yijia Huang <yijia_huang@apple.com>

Add a new pattern to instruction selector to utilize UMULL supported by ARM64
@@ -67,10 +67,10 @@ bool shouldSaveIRBeforePhase()
return Options::verboseValidationFailure();
}

std::optional<GPRReg> pinnedExtendedOffsetAddrRegister()
std::optional<GPRReg> linkRegister()
{
#if CPU(ARM64)
return MacroAssembler::dataTempRegister;
return MacroAssembler::linkRegister;
#elif CPU(X86_64)
return std::nullopt;
#else
@@ -183,7 +183,7 @@ inline unsigned defaultOptLevel()
return Options::defaultB3OptLevel();
}

std::optional<GPRReg> pinnedExtendedOffsetAddrRegister();
std::optional<GPRReg> linkRegister();

} } // namespace JSC::B3

@@ -144,11 +144,11 @@ static ALWAYS_INLINE CCallHelpers::Address callFrameAddr(CCallHelpers& jit, intp
return CCallHelpers::Address(GPRInfo::callFrameRegister, offsetFromFP);
}

ASSERT(pinnedExtendedOffsetAddrRegister());
ASSERT(linkRegister());
auto addr = Arg::addr(Air::Tmp(GPRInfo::callFrameRegister), offsetFromFP);
if (addr.isValidForm(Width64))
return CCallHelpers::Address(GPRInfo::callFrameRegister, offsetFromFP);
GPRReg reg = *pinnedExtendedOffsetAddrRegister();
GPRReg reg = *linkRegister();
jit.move(CCallHelpers::TrustedImmPtr(offsetFromFP), reg);
jit.add64(GPRInfo::callFrameRegister, reg);
return CCallHelpers::Address(reg);
@@ -90,9 +90,6 @@ Code::Code(Procedure& proc)
setRegsInPriorityOrder(bank, result);
});

if (auto reg = pinnedExtendedOffsetAddrRegister())
pinRegister(*reg);

m_pinnedRegs.set(MacroAssembler::framePointerRegister);
}

@@ -78,8 +78,7 @@ void lowerStackArgs(Code& code)
if (Arg::isValidImmForm(offset))
inst = Inst(inst.kind.opcode == Lea32 ? Add32 : Add64, inst.origin, Arg::imm(offset), base, inst.args[1]);
else {
ASSERT(pinnedExtendedOffsetAddrRegister());
Air::Tmp tmp = Air::Tmp(*pinnedExtendedOffsetAddrRegister());
Air::Tmp tmp = Air::Tmp(*linkRegister());
Arg offsetArg = Arg::bigImm(offset);
insertionSet.insert(instIndex, Move, inst.origin, offsetArg, tmp);
inst = Inst(inst.kind.opcode == Lea32 ? Add32 : Add64, inst.origin, tmp, base, inst.args[1]);
@@ -128,8 +127,7 @@ void lowerStackArgs(Code& code)
if (result.isValidForm(width))
return result;
#if CPU(ARM64)
ASSERT(pinnedExtendedOffsetAddrRegister());
Air::Tmp tmp = Air::Tmp(*pinnedExtendedOffsetAddrRegister());
Air::Tmp tmp = Air::Tmp(*linkRegister());

Arg largeOffset = Arg::isValidImmForm(offsetFromSP) ? Arg::imm(offsetFromSP) : Arg::bigImm(offsetFromSP);
insertionSet.insert(instIndex, Move, inst.origin, largeOffset, tmp);

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