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// FPGA VGA Graphics Part 3: SRAM Module (single port)
// (C)2018 Will Green - Licensed under the MIT License
// Learn more at https://timetoexplore.net/blog/arty-fpga-vga-verilog-03
`default_nettype none
module sram #(parameter ADDR_WIDTH=8, DATA_WIDTH=8, DEPTH=256, MEMFILE="") (
input wire i_clk,
input wire [ADDR_WIDTH-1:0] i_addr,
input wire i_write,
input wire [DATA_WIDTH-1:0] i_data,
output reg [DATA_WIDTH-1:0] o_data
);
reg [DATA_WIDTH-1:0] memory_array [0:DEPTH-1];
initial begin
if (MEMFILE > 0)
begin
$display("Loading memory init file '" + MEMFILE + "' into array.");
$readmemh(MEMFILE, memory_array);
end
end
always @ (posedge i_clk)
begin
if(i_write) begin
memory_array[i_addr] <= i_data;
end
else begin
o_data <= memory_array[i_addr];
end
end
endmodule