diff --git a/vga01/arty.xdc b/vga01/arty.xdc
index b0a603e..93de95f 100644
--- a/vga01/arty.xdc
+++ b/vga01/arty.xdc
@@ -1,6 +1,6 @@
 ## FPGA VGA Graphics Part 1: Arty Board Constraints
 ## Adapted from Digilent master file:
-##   https://github.com/Digilent/digilent-xdc/blob/master/Arty-Master.xdc
+##  https://github.com/Digilent/digilent-xdc/blob/master/Arty-Master.xdc
 ## Learn more at https://timetoexplore.net/blog/arty-fpga-vga-verilog-01
 
 ## Clock
diff --git a/vga01/top.v b/vga01/top.v
index 4c96b99..f46fb63 100644
--- a/vga01/top.v
+++ b/vga01/top.v
@@ -5,7 +5,7 @@
 `default_nettype none
 
 module top(
-    input wire CLK,             // board clock: 100 MHz on Arty & Basys 3
+    input wire CLK,             // board clock: 100 MHz on Arty/Basys3/Nexys
     input wire RST_BTN,         // reset button
     output wire VGA_HS_O,       // horizontal sync output
     output wire VGA_VS_O,       // vertical sync output
@@ -14,7 +14,8 @@ module top(
     output wire [3:0] VGA_B     // 4-bit VGA blue output
     );
 
-    wire rst = ~RST_BTN;  // reset is active low on Arty
+    wire rst = ~RST_BTN;    // reset is active low on Arty & Nexys Video
+    // wire rst = RST_BTN;  // reset is active high on Basys3 (BTNC)
 
     wire [9:0] x;  // current pixel x position: 10-bit value: 0-1023
     wire [8:0] y;  // current pixel y position:  9-bit value: 0-511
diff --git a/vga01/top_static.v b/vga01/top_static.v
index 78dd530..656b8e8 100644
--- a/vga01/top_static.v
+++ b/vga01/top_static.v
@@ -3,7 +3,7 @@
 // Learn more at https://timetoexplore.net/blog/arty-fpga-vga-verilog-01
 
 module top(
-    input wire CLK,             // board clock: 100 MHz on Arty & Basys 3
+    input wire CLK,             // board clock: 100 MHz on Arty/Basys3/Nexys
     input wire RST_BTN,         // reset button
     output wire VGA_HS_O,       // horizontal sync output
     output wire VGA_VS_O,       // vertical sync output
@@ -12,7 +12,8 @@ module top(
     output wire [3:0] VGA_B     // 4-bit VGA blue output
     );
 
-    wire rst = ~RST_BTN;  // reset is active low on Arty
+    wire rst = ~RST_BTN;    // reset is active low on Arty & Nexys Video
+    // wire rst = RST_BTN;  // reset is active high on Basys3 (BTNC)
 
     // generate a 25 MHz pixel strobe
     reg [15:0] cnt;