Build Customized FPGA Implementations for Vivado
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com/xilinx/rapidwright Providing an example on how to decompose a LUT6 to two LUT5s and a 2:… Feb 21, 2019
doc First commit of code. Sep 30, 2018
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RapidWright is an open source project from Xilinx Research Labs that provides a new bridge to Vivado through reading and writing design checkpoint (DCP) files. Its mission is to enable power users greater flexibility in customizing solutions to their unique implementation challenges.

RapidWright also provides a new design methodology leveraging pre-implemented modules (modules that have been synthesized, placed and routed out-of-context). These pre-implemented modules can be cached, replicated and relocated using the RapidWright framework. We see pre-implmented modules as a way to build systematic shells and overlays and a core piece of strategy in achieving near-spec performance.

If you run into issues, feel free to file an issue on the Github issue tracker, or, for more broad questions/requests, post on our support forum. Documentation and Javadoc reference is also available.

For more information, please see

NOTE: RapidWright is not an official product from Xilinx and designs created or derived from it are not warranted. Please see LICENSE.TXT for full details.