From 5f2743eae37c2e1e336283ba5f7a3bcfb22f54a2 Mon Sep 17 00:00:00 2001 From: Gon Solo Date: Fri, 22 Mar 2024 12:24:44 +0100 Subject: [PATCH 01/22] Make compile for 6.8. --- XDMA/linux-kernel/xdma/cdev_ctrl.c | 2 +- XDMA/linux-kernel/xdma/cdev_sgdma.c | 4 ++-- XDMA/linux-kernel/xdma/xdma_cdev.c | 2 +- 3 files changed, 4 insertions(+), 4 deletions(-) diff --git a/XDMA/linux-kernel/xdma/cdev_ctrl.c b/XDMA/linux-kernel/xdma/cdev_ctrl.c index dbc41ef36..785c9357f 100644 --- a/XDMA/linux-kernel/xdma/cdev_ctrl.c +++ b/XDMA/linux-kernel/xdma/cdev_ctrl.c @@ -233,7 +233,7 @@ int bridge_mmap(struct file *file, struct vm_area_struct *vma) * prevent touching the pages (byte access) for swap-in, * and prevent the pages from being swapped out */ - vma->vm_flags |= VMEM_FLAGS; + vm_flags_set(vma, VMEM_FLAGS); /* make MMIO accessible to user space */ rv = io_remap_pfn_range(vma, vma->vm_start, phys >> PAGE_SHIFT, vsize, vma->vm_page_prot); diff --git a/XDMA/linux-kernel/xdma/cdev_sgdma.c b/XDMA/linux-kernel/xdma/cdev_sgdma.c index 4a9f63870..4678def9e 100644 --- a/XDMA/linux-kernel/xdma/cdev_sgdma.c +++ b/XDMA/linux-kernel/xdma/cdev_sgdma.c @@ -566,12 +566,12 @@ static ssize_t cdev_aio_read(struct kiocb *iocb, const struct iovec *io, #if LINUX_VERSION_CODE >= KERNEL_VERSION(3, 16, 0) static ssize_t cdev_write_iter(struct kiocb *iocb, struct iov_iter *io) { - return cdev_aio_write(iocb, io->iov, io->nr_segs, io->iov_offset); + return cdev_aio_write(iocb, iter_iov(io), io->nr_segs, io->iov_offset); } static ssize_t cdev_read_iter(struct kiocb *iocb, struct iov_iter *io) { - return cdev_aio_read(iocb, io->iov, io->nr_segs, io->iov_offset); + return cdev_aio_read(iocb, iter_iov(io), io->nr_segs, io->iov_offset); } #endif diff --git a/XDMA/linux-kernel/xdma/xdma_cdev.c b/XDMA/linux-kernel/xdma/xdma_cdev.c index 363ffb447..488a3a497 100644 --- a/XDMA/linux-kernel/xdma/xdma_cdev.c +++ b/XDMA/linux-kernel/xdma/xdma_cdev.c @@ -603,7 +603,7 @@ int xpdev_create_interfaces(struct xdma_pci_dev *xpdev) int xdma_cdev_init(void) { - g_xdma_class = class_create(THIS_MODULE, XDMA_NODE_NAME); + g_xdma_class = class_create(XDMA_NODE_NAME); if (IS_ERR(g_xdma_class)) { dbg_init(XDMA_NODE_NAME ": failed to create class"); return -EINVAL; From 2608353624796ad48f5b9fd2af447ae8110aa8dc Mon Sep 17 00:00:00 2001 From: Gon Solo Date: Fri, 22 Mar 2024 12:24:55 +0100 Subject: [PATCH 02/22] Change for Nitefury II according to Firesim. --- XDMA/linux-kernel/xdma/libxdma.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/XDMA/linux-kernel/xdma/libxdma.h b/XDMA/linux-kernel/xdma/libxdma.h index 933d86584..52758450e 100644 --- a/XDMA/linux-kernel/xdma/libxdma.h +++ b/XDMA/linux-kernel/xdma/libxdma.h @@ -93,7 +93,7 @@ #define XDMA_OFS_CONFIG (0x3000UL) /* maximum number of desc per transfer request */ -#define XDMA_ENGINE_XFER_MAX_DESC 0x800 +#define XDMA_ENGINE_XFER_MAX_DESC 16 // gonsolo for firesim 0x800 #define XDMA_ENGINE_CREDIT_XFER_MAX_DESC 0x3FF /* maximum size of a single DMA transfer descriptor */ From 4ef2e8b5eb7ce1cf51f7c2721b4b5f0e9b690d63 Mon Sep 17 00:00:00 2001 From: Gon Solo Date: Fri, 22 Mar 2024 12:25:17 +0100 Subject: [PATCH 03/22] Ignore. --- XDMA/linux-kernel/xdma/.gitignore | 7 +++++++ 1 file changed, 7 insertions(+) create mode 100644 XDMA/linux-kernel/xdma/.gitignore diff --git a/XDMA/linux-kernel/xdma/.gitignore b/XDMA/linux-kernel/xdma/.gitignore new file mode 100644 index 000000000..a3fbf7ac9 --- /dev/null +++ b/XDMA/linux-kernel/xdma/.gitignore @@ -0,0 +1,7 @@ +/*.o +/*.cmd +xdma.mod +/*.ko +modules.order +Module.symvers +xdma.mod.c From 5e5c6bc92cbc08dc7e03c67009d9618011c97c38 Mon Sep 17 00:00:00 2001 From: Gon Solo Date: Mon, 15 Apr 2024 11:05:12 +0200 Subject: [PATCH 04/22] Fix warning. --- XDMA/linux-kernel/xdma/xdma_thread.h | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/XDMA/linux-kernel/xdma/xdma_thread.h b/XDMA/linux-kernel/xdma/xdma_thread.h index c8f6dbb86..d6347962d 100644 --- a/XDMA/linux-kernel/xdma/xdma_thread.h +++ b/XDMA/linux-kernel/xdma/xdma_thread.h @@ -144,4 +144,8 @@ void xdma_thread_remove_work(struct xdma_engine *engine); *****************************************************************************/ void xdma_thread_add_work(struct xdma_engine *engine); +/* gonsolo */ +int xdma_kthread_start(struct xdma_kthread *thp, char *name, int id); +int xdma_kthread_stop(struct xdma_kthread *thp); + #endif /* #ifndef __XDMA_KTHREAD_H__ */ From 142c227f1308e8a08129f61d9905518771dcc941 Mon Sep 17 00:00:00 2001 From: Gon Solo Date: Mon, 15 Apr 2024 11:27:32 +0200 Subject: [PATCH 05/22] Fix uname. --- XDMA/linux-kernel/xdma/Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/XDMA/linux-kernel/xdma/Makefile b/XDMA/linux-kernel/xdma/Makefile index 41822048b..18e25f352 100644 --- a/XDMA/linux-kernel/xdma/Makefile +++ b/XDMA/linux-kernel/xdma/Makefile @@ -43,7 +43,7 @@ clean: @/bin/rm -f *.ko modules.order *.mod.c *.o *.o.ur-safe .*.o.cmd install: all - @rm -f /lib/modules/5.15.0-67-generic/extra/xdma.ko + @rm -f /lib/modules/$(shell uname -r)/extra/xdma.ko @echo "installing kernel modules to /lib/modules/$(shell uname -r)/xdma ..." @mkdir -p -m 755 /lib/modules/$(shell uname -r)/xdma @install -v -m 644 *.ko /lib/modules/$(shell uname -r)/xdma From b17e9d69a7f26ba6b499b63e72ef3bef1aa3d051 Mon Sep 17 00:00:00 2001 From: Gon Solo Date: Mon, 15 Apr 2024 21:57:59 +0200 Subject: [PATCH 06/22] Rename to distinguish from kernel xdma. --- XDMA/linux-kernel/xdma/Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/XDMA/linux-kernel/xdma/Makefile b/XDMA/linux-kernel/xdma/Makefile index 18e25f352..750f7d45e 100644 --- a/XDMA/linux-kernel/xdma/Makefile +++ b/XDMA/linux-kernel/xdma/Makefile @@ -18,7 +18,7 @@ $(warning XVC_FLAGS: $(XVC_FLAGS).) topdir := $(shell cd $(src)/.. && pwd) -TARGET_MODULE:=xdma +TARGET_MODULE:=xdma-gonsolo EXTRA_CFLAGS := -I$(topdir)/include $(XVC_FLAGS) ifeq ($(DEBUG),1) From 8e0040941e4c2a64ee12291f46f7aeacb5f62bfc Mon Sep 17 00:00:00 2001 From: Gon Solo Date: Tue, 16 Apr 2024 14:17:21 +0200 Subject: [PATCH 07/22] Instruction & ignore. --- XDMA/linux-kernel/xdma/.gitignore | 2 ++ XDMA/linux-kernel/xdma/GONSOLO | 6 ++++++ 2 files changed, 8 insertions(+) create mode 100644 XDMA/linux-kernel/xdma/GONSOLO diff --git a/XDMA/linux-kernel/xdma/.gitignore b/XDMA/linux-kernel/xdma/.gitignore index a3fbf7ac9..b99f3d226 100644 --- a/XDMA/linux-kernel/xdma/.gitignore +++ b/XDMA/linux-kernel/xdma/.gitignore @@ -5,3 +5,5 @@ xdma.mod modules.order Module.symvers xdma.mod.c +/xdma-gonsolo.mod +/xdma-gonsolo.mod.c diff --git a/XDMA/linux-kernel/xdma/GONSOLO b/XDMA/linux-kernel/xdma/GONSOLO new file mode 100644 index 000000000..c815a9f6c --- /dev/null +++ b/XDMA/linux-kernel/xdma/GONSOLO @@ -0,0 +1,6 @@ +make -j10 +sudo make -j10 install +Boot with pci=nomsi +sudo insmod /lib/modules/6.8.5-arch1-1/xdma/xdma-gonsolo.ko poll_mode=1 interrupt_mode=2 +lsmod|grep xdma_gonsolo +sudo rmmod xdma_gonsolo From a544e20779f27fe2058434ca1d626c114c23bb23 Mon Sep 17 00:00:00 2001 From: Gon Solo Date: Tue, 16 Apr 2024 14:21:46 +0200 Subject: [PATCH 08/22] Show devices. --- XDMA/linux-kernel/xdma/GONSOLO | 2 ++ 1 file changed, 2 insertions(+) diff --git a/XDMA/linux-kernel/xdma/GONSOLO b/XDMA/linux-kernel/xdma/GONSOLO index c815a9f6c..8652d8c2e 100644 --- a/XDMA/linux-kernel/xdma/GONSOLO +++ b/XDMA/linux-kernel/xdma/GONSOLO @@ -3,4 +3,6 @@ sudo make -j10 install Boot with pci=nomsi sudo insmod /lib/modules/6.8.5-arch1-1/xdma/xdma-gonsolo.ko poll_mode=1 interrupt_mode=2 lsmod|grep xdma_gonsolo +sudo dmesg sudo rmmod xdma_gonsolo +ls /dev/xdma* From 61f4b56bd17d71381646c6a5aa169e04e8bcc1d9 Mon Sep 17 00:00:00 2001 From: Gon Solo Date: Sat, 20 Apr 2024 09:58:13 +0200 Subject: [PATCH 09/22] Update. --- XDMA/linux-kernel/xdma/GONSOLO | 6 +++--- XDMA/linux-kernel/xdma/Makefile | 2 +- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/XDMA/linux-kernel/xdma/GONSOLO b/XDMA/linux-kernel/xdma/GONSOLO index 8652d8c2e..6be047b6c 100644 --- a/XDMA/linux-kernel/xdma/GONSOLO +++ b/XDMA/linux-kernel/xdma/GONSOLO @@ -1,7 +1,7 @@ -make -j10 -sudo make -j10 install +make -j10 DEBUG=1 +sudo make -j10 DEBUG=1 install Boot with pci=nomsi -sudo insmod /lib/modules/6.8.5-arch1-1/xdma/xdma-gonsolo.ko poll_mode=1 interrupt_mode=2 +sudo insmod /lib/modules/$(uname -r)/xdma/xdma-gonsolo.ko poll_mode=1 interrupt_mode=2 lsmod|grep xdma_gonsolo sudo dmesg sudo rmmod xdma_gonsolo diff --git a/XDMA/linux-kernel/xdma/Makefile b/XDMA/linux-kernel/xdma/Makefile index 750f7d45e..18e25f352 100644 --- a/XDMA/linux-kernel/xdma/Makefile +++ b/XDMA/linux-kernel/xdma/Makefile @@ -18,7 +18,7 @@ $(warning XVC_FLAGS: $(XVC_FLAGS).) topdir := $(shell cd $(src)/.. && pwd) -TARGET_MODULE:=xdma-gonsolo +TARGET_MODULE:=xdma EXTRA_CFLAGS := -I$(topdir)/include $(XVC_FLAGS) ifeq ($(DEBUG),1) From c008109f22dae117a748373c58b73e2c482ecceb Mon Sep 17 00:00:00 2001 From: Gon Solo Date: Sat, 20 Apr 2024 10:21:59 +0200 Subject: [PATCH 10/22] Fix "BUG: scheduling while atomic" https://github.com/Xilinx/dma_ip_drivers/issues/229 https://github.com/paulmnt/dma_ip_drivers/pull/1/files --- XDMA/linux-kernel/xdma/xdma_thread.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/XDMA/linux-kernel/xdma/xdma_thread.c b/XDMA/linux-kernel/xdma/xdma_thread.c index 662311fa0..6eaddf062 100644 --- a/XDMA/linux-kernel/xdma/xdma_thread.c +++ b/XDMA/linux-kernel/xdma/xdma_thread.c @@ -119,7 +119,9 @@ static int xthread_main(void *data) thp->name, thp->work_cnt); /* do work */ list_for_each_safe(work_item, next, &thp->work_list) { + unlock_thread(thp); thp->fproc(work_item); + lock_thread(thp); } } unlock_thread(thp); From 6caa6c18839018ddd67add457c9a20b8fae609b0 Mon Sep 17 00:00:00 2001 From: Gon Solo Date: Sat, 20 Apr 2024 10:26:48 +0200 Subject: [PATCH 11/22] Ignore. --- XDMA/linux-kernel/tools/.gitignore | 6 ++++++ XDMA/linux-kernel/xdma/.gitignore | 1 + 2 files changed, 7 insertions(+) create mode 100644 XDMA/linux-kernel/tools/.gitignore diff --git a/XDMA/linux-kernel/tools/.gitignore b/XDMA/linux-kernel/tools/.gitignore new file mode 100644 index 000000000..5fee6b7f1 --- /dev/null +++ b/XDMA/linux-kernel/tools/.gitignore @@ -0,0 +1,6 @@ +/dma_from_device +/dma_to_device +/performance +/reg_rw +/test_chrdev +*.o diff --git a/XDMA/linux-kernel/xdma/.gitignore b/XDMA/linux-kernel/xdma/.gitignore index b99f3d226..707b82c04 100644 --- a/XDMA/linux-kernel/xdma/.gitignore +++ b/XDMA/linux-kernel/xdma/.gitignore @@ -7,3 +7,4 @@ Module.symvers xdma.mod.c /xdma-gonsolo.mod /xdma-gonsolo.mod.c +/compile_commands.json From d77ed9d6ed5a3758cee589bbaa3f784a29eafd7e Mon Sep 17 00:00:00 2001 From: Gon Solo Date: Mon, 22 Apr 2024 09:22:46 +0200 Subject: [PATCH 12/22] Use mode 4. --- XDMA/linux-kernel/tests/scripts_mm/xdma_mm.sh | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/XDMA/linux-kernel/tests/scripts_mm/xdma_mm.sh b/XDMA/linux-kernel/tests/scripts_mm/xdma_mm.sh index a480dd777..61e89b8bf 100755 --- a/XDMA/linux-kernel/tests/scripts_mm/xdma_mm.sh +++ b/XDMA/linux-kernel/tests/scripts_mm/xdma_mm.sh @@ -6,7 +6,8 @@ # #################### outdir="/tmp" -driver_modes="0 4" ;# driver mode +# gonsolo driver_modes="0 4" ;# driver mode +driver_modes="4" address=0 offset=0 io_min=64 From a42eeb4f55a59ca4dc20832e3c278cdeb6b9f40b Mon Sep 17 00:00:00 2001 From: Gon Solo Date: Mon, 22 Apr 2024 09:23:11 +0200 Subject: [PATCH 13/22] Don't enable msi in poll mode. --- XDMA/linux-kernel/xdma/libxdma.c | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/XDMA/linux-kernel/xdma/libxdma.c b/XDMA/linux-kernel/xdma/libxdma.c index 3d9c86524..84af05f5e 100644 --- a/XDMA/linux-kernel/xdma/libxdma.c +++ b/XDMA/linux-kernel/xdma/libxdma.c @@ -4506,9 +4506,11 @@ void *xdma_device_open(const char *mname, struct pci_dev *pdev, int *user_max, if (rv) goto err_mask; - rv = enable_msi_msix(xdev, pdev); - if (rv < 0) - goto err_engines; + if (!poll_mode) { + rv = enable_msi_msix(xdev, pdev); + if (rv < 0) + goto err_engines; + } rv = irq_setup(xdev, pdev); if (rv < 0) From 27e0cb6eb41119ba6594f88ccbef758b4e741815 Mon Sep 17 00:00:00 2001 From: Gon Solo Date: Mon, 22 Apr 2024 20:53:47 +0200 Subject: [PATCH 14/22] Revert "Don't enable msi in poll mode." This reverts commit a42eeb4f55a59ca4dc20832e3c278cdeb6b9f40b. --- XDMA/linux-kernel/xdma/libxdma.c | 8 +++----- 1 file changed, 3 insertions(+), 5 deletions(-) diff --git a/XDMA/linux-kernel/xdma/libxdma.c b/XDMA/linux-kernel/xdma/libxdma.c index 84af05f5e..3d9c86524 100644 --- a/XDMA/linux-kernel/xdma/libxdma.c +++ b/XDMA/linux-kernel/xdma/libxdma.c @@ -4506,11 +4506,9 @@ void *xdma_device_open(const char *mname, struct pci_dev *pdev, int *user_max, if (rv) goto err_mask; - if (!poll_mode) { - rv = enable_msi_msix(xdev, pdev); - if (rv < 0) - goto err_engines; - } + rv = enable_msi_msix(xdev, pdev); + if (rv < 0) + goto err_engines; rv = irq_setup(xdev, pdev); if (rv < 0) From 22dd227a3d3dbc2b43e59707e18ce8f5069eb203 Mon Sep 17 00:00:00 2001 From: Gon Solo Date: Thu, 25 Apr 2024 18:48:38 +0200 Subject: [PATCH 15/22] Update to working xdma version. --- QDMA/DPDK/RELEASE | 195 - QDMA/DPDK/docs/README.txt | 557 -- QDMA/DPDK/drivers/net/qdma/meson.build | 79 - QDMA/DPDK/drivers/net/qdma/qdma.h | 500 - .../eqdma_cpm5_access/eqdma_cpm5_access.c | 6879 -------------- .../eqdma_cpm5_access/eqdma_cpm5_access.h | 360 - .../eqdma_cpm5_access/eqdma_cpm5_reg.h | 1300 --- .../eqdma_cpm5_access/eqdma_cpm5_reg_dump.c | 4025 --------- .../eqdma_soft_access/eqdma_soft_access.c | 6833 -------------- .../eqdma_soft_access/eqdma_soft_access.h | 361 - .../eqdma_soft_access/eqdma_soft_reg.h | 1540 ---- .../eqdma_soft_access/eqdma_soft_reg_dump.c | 5338 ----------- .../net/qdma/qdma_access/qdma_access_common.c | 1530 ---- .../net/qdma/qdma_access/qdma_access_common.h | 942 -- .../net/qdma/qdma_access/qdma_access_errors.h | 89 - .../net/qdma/qdma_access/qdma_access_export.h | 278 - .../qdma/qdma_access/qdma_access_version.h | 53 - .../qdma_cpm4_access/qdma_cpm4_access.c | 6071 ------------- .../qdma_cpm4_access/qdma_cpm4_access.h | 300 - .../qdma_cpm4_access/qdma_cpm4_reg.h | 2062 ----- .../qdma_cpm4_access/qdma_cpm4_reg_dump.c | 8029 ----------------- .../drivers/net/qdma/qdma_access/qdma_list.c | 78 - .../drivers/net/qdma/qdma_access/qdma_list.h | 142 - .../net/qdma/qdma_access/qdma_mbox_protocol.c | 2156 ----- .../net/qdma/qdma_access/qdma_mbox_protocol.h | 711 -- .../net/qdma/qdma_access/qdma_platform.h | 193 - .../net/qdma/qdma_access/qdma_reg_dump.h | 99 - .../net/qdma/qdma_access/qdma_resource_mgmt.c | 811 -- .../net/qdma/qdma_access/qdma_resource_mgmt.h | 230 - .../qdma_soft_access/qdma_soft_access.c | 6255 ------------- .../qdma_soft_access/qdma_soft_access.h | 310 - .../qdma_soft_access/qdma_soft_reg.h | 599 -- QDMA/DPDK/drivers/net/qdma/qdma_common.c | 657 -- QDMA/DPDK/drivers/net/qdma/qdma_devops.c | 1984 ---- QDMA/DPDK/drivers/net/qdma/qdma_devops.h | 515 -- QDMA/DPDK/drivers/net/qdma/qdma_dpdk_compat.c | 316 - QDMA/DPDK/drivers/net/qdma/qdma_dpdk_compat.h | 118 - QDMA/DPDK/drivers/net/qdma/qdma_ethdev.c | 976 -- QDMA/DPDK/drivers/net/qdma/qdma_log.h | 47 - QDMA/DPDK/drivers/net/qdma/qdma_mbox.c | 424 - QDMA/DPDK/drivers/net/qdma/qdma_mbox.h | 75 - QDMA/DPDK/drivers/net/qdma/qdma_platform.c | 264 - .../DPDK/drivers/net/qdma/qdma_platform_env.h | 61 - QDMA/DPDK/drivers/net/qdma/qdma_rxtx.c | 1464 --- QDMA/DPDK/drivers/net/qdma/qdma_rxtx.h | 51 - .../DPDK/drivers/net/qdma/qdma_rxtx_vec_sse.c | 851 -- QDMA/DPDK/drivers/net/qdma/qdma_user.c | 295 - QDMA/DPDK/drivers/net/qdma/qdma_user.h | 253 - QDMA/DPDK/drivers/net/qdma/qdma_vf_ethdev.c | 1265 --- QDMA/DPDK/drivers/net/qdma/qdma_xdebug.c | 1468 --- QDMA/DPDK/drivers/net/qdma/rte_pmd_qdma.c | 1821 ---- QDMA/DPDK/drivers/net/qdma/rte_pmd_qdma.h | 888 -- QDMA/DPDK/drivers/net/qdma/version.h | 52 - QDMA/DPDK/drivers/net/qdma/version.map | 166 - QDMA/DPDK/examples/qdma_testapp/Makefile | 97 - QDMA/DPDK/examples/qdma_testapp/commands.c | 1526 ---- QDMA/DPDK/examples/qdma_testapp/commands.h | 38 - .../examples/qdma_testapp/parse_obj_list.c | 197 - .../examples/qdma_testapp/parse_obj_list.h | 147 - QDMA/DPDK/examples/qdma_testapp/pcierw.c | 56 - QDMA/DPDK/examples/qdma_testapp/pcierw.h | 43 - QDMA/DPDK/examples/qdma_testapp/qdma_regs.h | 231 - QDMA/DPDK/examples/qdma_testapp/testapp.c | 1118 --- QDMA/DPDK/examples/qdma_testapp/testapp.h | 108 - ...MA-xdebug-to-proc-info-of-dpdk-22.11.patch | 362 - ....0-Patch-to-add-Jumbo-packet-support.patch | 320 - ....1-Patch-to-add-Jumbo-packet-support.patch | 466 - QDMA/DPDK/tools/README.txt | 45 - QDMA/linux-kernel/COPYING | 340 - QDMA/linux-kernel/LICENSE | 30 - QDMA/linux-kernel/Makefile | 184 - QDMA/linux-kernel/RELEASE | 208 - QDMA/linux-kernel/apps/Makefile | 122 - QDMA/linux-kernel/apps/dma-ctl/Makefile | 38 - QDMA/linux-kernel/apps/dma-ctl/cmd_parse.c | 1259 --- QDMA/linux-kernel/apps/dma-ctl/cmd_parse.h | 20 - QDMA/linux-kernel/apps/dma-ctl/main.c | 208 - QDMA/linux-kernel/apps/dma-ctl/version.h | 19 - .../apps/dma-from-device/Makefile | 27 - .../apps/dma-from-device/dma_from_device.c | 236 - .../apps/dma-from-device/version.h | 19 - QDMA/linux-kernel/apps/dma-latency/Makefile | 39 - QDMA/linux-kernel/apps/dma-latency/Readme.txt | 38 - QDMA/linux-kernel/apps/dma-latency/dmalat.c | 1133 --- .../dma-latency/sample_dma_latency_config.txt | 28 - QDMA/linux-kernel/apps/dma-latency/version.h | 19 - QDMA/linux-kernel/apps/dma-perf/Makefile | 39 - QDMA/linux-kernel/apps/dma-perf/dmaperf.c | 2275 ----- .../apps/dma-perf/dmaperf_config/st-bi.zip | Bin 112903 -> 0 bytes .../dmaperf_config/st-c2h-pfetch1.zip | Bin 111916 -> 0 bytes .../apps/dma-perf/dmaperf_config/st-h2c.zip | Bin 105919 -> 0 bytes QDMA/linux-kernel/apps/dma-perf/version.h | 19 - QDMA/linux-kernel/apps/dma-to-device/Makefile | 39 - .../apps/dma-to-device/dma_to_device.c | 265 - .../linux-kernel/apps/dma-to-device/version.h | 19 - QDMA/linux-kernel/apps/dma-utils/Makefile | 26 - .../apps/dma-utils/dma_xfer_utils.c | 214 - QDMA/linux-kernel/apps/dma-utils/dmactl.c | 884 -- .../apps/dma-utils/dmactl_internal.h | 23 - QDMA/linux-kernel/apps/dma-utils/dmactl_reg.c | 461 - QDMA/linux-kernel/apps/dma-utils/dmautils.c | 45 - QDMA/linux-kernel/apps/dma-utils/dmautils.h | 619 -- QDMA/linux-kernel/apps/dma-utils/dmaxfer.c | 1118 --- QDMA/linux-kernel/apps/dma-utils/dmaxfer.h | 46 - QDMA/linux-kernel/apps/dma-utils/version.h | 19 - QDMA/linux-kernel/apps/dma-xfer/Makefile | 39 - QDMA/linux-kernel/apps/dma-xfer/dmaxfer.c | 1266 --- .../apps/dma-xfer/sample_qdma_xfer_config.txt | 30 - QDMA/linux-kernel/apps/dma-xfer/version.h | 18 - QDMA/linux-kernel/apps/include/qdma_nl.h | 480 - .../apps/include/qdma_user_reg_dump.h | 54 - QDMA/linux-kernel/apps/include/xdev_regs.h | 238 - QDMA/linux-kernel/bsd_license.txt | 12 - QDMA/linux-kernel/docs/README | 323 - QDMA/linux-kernel/docs/dma-ctl.8.gz | Bin 2403 -> 0 bytes QDMA/linux-kernel/driver/Makefile | 272 - QDMA/linux-kernel/driver/include/qdma_nl.h | 488 - .../driver/include/qdma_user_reg_dump.h | 61 - QDMA/linux-kernel/driver/include/xdev_regs.h | 246 - QDMA/linux-kernel/driver/libqdma/Makefile | 66 - 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QDMA/windows/sys/libqdma/source/trace.h delete mode 100644 QDMA/windows/sys/libqdma/source/xpcie.cpp delete mode 100644 QDMA/windows/sys/libqdma/source/xpcie.hpp delete mode 100644 XDMA/linux-kernel/xdma/GONSOLO delete mode 100644 docs/source/includeme.rst delete mode 100644 index.html diff --git a/QDMA/DPDK/RELEASE b/QDMA/DPDK/RELEASE deleted file mode 100755 index 806779b5e..000000000 --- a/QDMA/DPDK/RELEASE +++ /dev/null @@ -1,195 +0,0 @@ -RELEASE: 2023.2.1 -================= - -This release is based on DPDK v20.11, v21.11 and v22.11 and -contains QDMA poll mode driver and QDMA test application. - -This release is validated for - - On VCU1525 for QDMA5.0 2022.1 example design - - On VCU1525 for QDMA4.0 2020.2 example design - - On VCU1525 for QDMA3.1 2019.2 example design - - On XCVP1202 for CPM5 2022.1 example design - - On XCVC1902 for CPM4 2022.1 example design - -This release includes patch files for dpdk-pktgen v20.12.0 and v22.04.1 that extends -dpdk-pktgen application to handle packets with packet sizes more than 1518 bytes -and it disables the packet size classification logic in dpdk-pktgen to remove -application overhead in performance measurement.This patch is used for -performance testing with dpdk-pktgen application. - -The driver is validated against dpdk-pktgen and testpmd applications for API compliance. - -SUPPORTED FEATURES: -=================== -2018.2 Features ---------------- -- Support for both the AXI4 Memory Mapped(MM) and AXI4 Streaming(ST) Interfaces -- 2048 Queue Sets - - 2048 H2C Descriptor Rings - - 2048 C2H Descriptor Rings - - 2048 C2H Completion Rings -- Supports Polling Mode -- Supports SR-IOV with 4 Physical Functions(PF) and 252 Virtual Functions(VF) -- Allows Only Privileged/Physical functions to program the contexts and registers -- Mailbox Support -- Supports Descriptor Prefetch -- ST H2C to C2H and C2H to H2C loopback support -- Zero-byte transfer support - -2018.3 Features ---------------- -- Descriptor (8, 16, 32, 64 bytes) bypass support -- Support for Completion queue descriptors of 64 bytes size -- Support flexible BAR mapping for QDMA configuration register space -- Support disabling overflow check in completion ring -- Indirect programming of FMAP registers -- Version for SW and HW - -2019.1 Features ---------------- -- Support DPDK v18.11 LTS -- Interrupt support for Mailbox events -- Support Completions in Memory mapped mode -- Interoperability between Linux driver (as PF/VF) and DPDK driver (as PF/VF) -- Error monitoring and error logging -- Driver restructuring to partition QDMA access code such that it can be used across different drivers -- Device configuration through additional driver APIs - -2019.2 Features ---------------- -- Support reset of a VF device (via rte_eth_dev_reset() API) -- Support PF device removal when its VF device is active -- Split user logic related data path handling code to qdma_user.c and qdma_user.h -- Bug Fixes - - Correct the PF and VF function ID used in the driver in accordance with HW - - Fix dma_from_device command in qdma_testapp application that requests more data from user logic than specified - - Fix memory offset calculation in dma_from_device and dma_to_device command in qdma_testapp application for MM mode - -2020.1 Updates --------------- -- Support DPDK v19.11 LTS -- Support QDMA4.0 context and register changes -- Common driver to support QDMA3.1 and QDMA4.0 designs -- Updated and validated the example design with marker changes for QDMA4.0 and without marker changes for QDMA3.1 -- Added support for more than 256 functions -- Support multiple bus numbers on single card -- CPU resource optimization in Tx and Rx data path - -2020.1 Patch Updates --------------------- -- Resolved HW errors observed with QDMA4.0 MM only design -- Verified QDMA DPDK software with IOVA=VA mode by enabling hugepage allocation matching support in DPDK - (i.e. by specifying the --match-allocations command-line switch to the EAL). - -2020.2 Updates --------------- -- Added support for detailed register dump -- Added support for post processing HW error messages -- Added support for Debug mode and Internal only mode -- Resolved the issue related to mbuf packet length -- Fixed VF FMAP programming of qmax issue by setting qmax to the actual user configured total queue number - -2020.2.1 Updates ----------------- -- Migrated qdma dpdk driver to use DPDK framework v20.11 - -2022.1 Updates --------------- -CPM5 - - FMAP context dump - - Debug register dump for ST and MM Errors - - Dual Instance support - -2022.1.1 Patch Updates ----------------------- -- Added VF 4K queues support for CPM5 design. This feature is applicable only when corresponding RTL support is added. - -2022.1.2 Patch Updates ----------------------- -- Added support for QDMA5.0 which has some performance optimization changes compared to QDMA4.0 - -2022.1.3 Patch Updates ----------------------- -- Added PF/VF 4K queues support for CPM5 design. This feature is applicable only when corresponding RTL support is added. - -2023.1.0 Updates ----------------- -- Added support for DPDK framework v21.11 and v22.11 and retained the backward compatibility for v20.11 -- Enabled 128 bit SIMD vectorization for Intel and AMD platforms by default for qdma Receive and Transmit APIs -- Added IO memory barriers for H2C/C2H producer index and completion ring consumer index updates - -2023.1.1 Updates ----------------- -- Optimized the driver code and HW register settings for performance improvements - -2023.1.2 Updates ----------------- -- Optimized dpdk PMD and HW register settings for CPM5 performance improvements - -2023.2.0 Updates ----------------- -- Added driver support for CPM4 design. -- Added support for Tx and Rx queue statistics to enhance debugging capabilities -- Added support for latency measurements in Tx and Rx data path to enhance debugging capabilities - -2023.2.1 Updates ----------------- -- Added support for latency measurements in Tx and Rx data path for VF - -KNOWN ISSUE: -============ -- CPM4: - - HW pdi limitation - - VF functionality with vfio-pci on host is not verified - - VF functionality on VM is not verified - - Forwarding performance numbers are not reaching 100Gbps and capping at 98.8Gbps - -- CPM5: - - Smaller packet forwarding performance optimizations are in progress and report will be updated in subsequent releases - -- All Designs - - Function Level Reset(FLR) of PF device when VFs are attached to this PF results in mailbox communication failure - - -DRIVER LIMITATIONS: -=================== -- CPM5 Only - - VF functionality is verified with 240 VF's as per CPM5 HW limitation - -- All Designs - - Big endian systems are not supported - - For optimal QDMA streaming performance, packet buffers of the descriptor ring should be aligned to at least 256 bytes. - - -/*- - * BSD LICENSE - * - * Copyright (c) 2017-2022 Xilinx, Inc. All rights reserved. - * Copyright (c) 2022-2023, Advanced Micro Devices, Inc. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * * Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ diff --git a/QDMA/DPDK/docs/README.txt b/QDMA/DPDK/docs/README.txt deleted file mode 100755 index a4ff05ee5..000000000 --- a/QDMA/DPDK/docs/README.txt +++ /dev/null @@ -1,557 +0,0 @@ -############################################################################### - - Xilinx QDMA Software README - -############################################################################### - -_____________________________________________________________________________ -Contents - -1. Setup: Download and modifications -2 Setup: Host system -3. Setup: Build Commands -4. Compile Test application -5. Running the DPDK software test application -_____________________________________________________________________________ - - -Note: This DPDK driver and applciation were tested on Ubuntu 18.04 machine. - - -1.) Setup: Download and modifications - -The reference driver code requires DPDK version 22.11. -Follow the steps below to download the proper version of DPDK and apply -driver code and test application supplied in the GitHub. - -Extract the DPDK driver software database from the Xilinx GitHub to the server where VCU1525 -is installed. Henceforth, this area is referred as . - -Create a directory for the DPDK download on the server where the VCU1525 -is installed and move to this directory. - - $ mkdir / - $ cd / - $ git clone http://dpdk.org/git/dpdk-stable - $ cd dpdk-stable - $ git checkout v22.11 - $ git clone git://dpdk.org/dpdk-kmods - $ cp -r /drivers/net/qdma ./drivers/net/ - $ cp -r /examples/qdma_testapp ./examples/ - - Additionally, make below changes to the DPDK 22.11 tree to build QDMA driver, - support 4K queues and populate Xilinx devices for binding. - - i. Add QDMA driver - a. To support 4K queues and 256 PCIe functions, update below configurations in ./config/rte_config.h - CONFIG_RTE_MAX_MEMZONE=40960 - CONFIG_RTE_MAX_ETHPORTS=256 - CONFIG_RTE_MAX_QUEUES_PER_PORT=4096 - - b. Add below lines to ./config/meson.build in DPDK 22.11 tree - # Set maximum Ethernet ports to 256 - dpdk_conf.set('RTE_MAX_ETHPORTS', 256) - - # Set maximum VFIO Groups to 256 - dpdk_conf.set('RTE_MAX_VFIO_GROUPS', 256) - - c. Add below lines to ./config/rte_config.h to enable driver debug logs - #define RTE_LIBRTE_QDMA_DEBUG_DRIVER 1 - - d. Add below line to ./drivers/net/meson.build, where PMDs are added to drivers list - 'qdma', - - e. To add Xilinx devices for device binding, add below lines to ./usertools/dpdk-devbind.py after cavium_pkx class, where PCI base class for devices are listed. - xilinx_qdma_pf = {'Class': '05', 'Vendor': '10ee', 'Device': '9011,9111,9211,9311,9014,9114,9214,9314,9018,9118,9218,9318,901f,911f,921f,931f,9021,9121,9221,9321,9024,9124,9224,9324,9028,9128,9228,9328,902f,912f,922f,932f,9031,9131,9231,9331,9034,9134,9234,9334,9038,9138,9238,9338,903f,913f,923f,933f,9041,9141,9241,9341,9044,9144,9244,9344,9048,9148,9248,9348,b011,b111,b211,b311,b014,b114,b214,b314,b018,b118,b218,b318,b01f,b11f,b21f,b31f,b021,b121,b221,b321,b024,b124,b224,b324,b028,b128,b228,b328,b02f,b12f,b22f,b32f,b031,b131,b231,b331,b034,b134,b234,b334,b038,b138,b238,b338,b03f,b13f,b23f,b33f,b041,b141,b241,b341,b044,b144,b244,b344,b048,b148,b248,b348', - 'SVendor': None, 'SDevice': None} - xilinx_qdma_vf = {'Class': '05', 'Vendor': '10ee', 'Device': 'a011,a111,a211,a311,a014,a114,a214,a314,a018,a118,a218,a318,a01f,a11f,a21f,a31f,a021,a121,a221,a321,a024,a124,a224,a324,a028,a128,a228,a328,a02f,a12f,a22f,a32f,a031,a131,a231,a331,a034,a134,a234,a334,a038,a138,a238,a338,a03f,a13f,a23f,a33f,a041,a141,a241,a341,a044,a144,a244,a344,a048,a148,a248,a348,c011,c111,c211,c311,c014,c114,c214,c314,c018,c118,c218,c318,c01f,c11f,c21f,c31f,c021,c121,c221,c321,c024,c124,c224,c324,c028,c128,c228,c328,c02f,c12f,c22f,c32f,c031,c131,c231,c331,c034,c134,c234,c334,c038,c138,c238,c338,c03f,c13f,c23f,c33f,c041,c141,c241,c341,c044,c144,c244,c344,c048,c148,c248,c348', - 'SVendor': None, 'SDevice': None} - - d. Update entries in network devices class in ./usertools/dpdk-devbind.py to add Xilinx devices - network_devices = [network_class, cavium_pkx, xilinx_qdma_pf, xilinx_qdma_vf], - -2.) Setup: Host system - -DPDK requires that hugepages are setup on the server. -The following modifications must be made to the /boot/grub/grub.cfg on the host system - - i. Add hugepages for DPDK - - Add following parameter to /etc/default/grub file - GRUB_CMDLINE_LINUX="default_hugepagesz=1GB hugepagesz=1G hugepages=20" - - This example adds 20 1GB hugepages, which are required to support 2048 queues, with descriptor ring of 1024 entries and each descriptor buffer length of 4KB. The number of hugepages required should be changed if the above configuration (queues, ring size, buffer size) changes. - - ii. Enable IOMMU for VM testing - - Update /etc/default/grub file as below. - GRUB_CMDLINE_LINUX="default_hugepagesz=1GB hugepagesz=1G hugepages=20 iommu=pt intel_iommu=on" - - iii. Execute the following command to modify the /boot/grub/grub.cfg with the configuration set in the above steps and permanently add them to the kernel command line. - update-grub - - iv. Reboot host system after making the above modifications. - -3.) Setup: Build Commands - - i. Compile DPDK & QDMA driver - a. Execute the following to compile and install the driver. - cd //dpdk-stable - meson build - cd build - ninja - ninja install - ldconfig - - - The following should appear when ninja completes - Linking target app/test/dpdk-test. - - - Verify that librte_net_qdma.a is installed in ./build/drivers directory. - - ii. Execute the following to compile the igb_uio kernel driver. - cd //dpdk-stable/dpdk-kmods/linux/igb_uio - make - - Important Note for VF 4K queue support for CPM5 design only - ----------------------------------------------------------- - - To enable VF 4K queue driver support for CPM5 design, QDMA DPDK driver need - to compile by enabling the EQDMA_CPM5_VF_GT_256Q_SUPPORTED macro - - cd //dpdk-stable - meson build -DEQDMA_CPM5_VF_GT_256Q_SUPPORTED=1 - cd build - ninja - ninja install - ldconfig - -4.) Compile Test application - - i. Change to root user and compile the application - sudo su - cd examples/qdma_testapp - make RTE_SDK=`pwd`/../.. RTE_TARGET=build - - - The following should appear when make completes - ln -sf qdma_testapp-shared build/qdma_testapp - - ii. Additionally, for memory mapped mode, BRAM size can be configured with make command. - Default BRAM size is set to 512KB in the driver makefile. - - -5.) Running the DPDK software test application - -The below steps describe the step by step procedure to run the DPDK QDMA test -application and to interact with the QDMA PCIe device. - - i. Navigate to examples/qdma_testapp directory. - cd //dpdk-stable/examples/qdma_testapp - - ii. Run the 'lspci' command on the console and verify that the PFs are detected as shown below. Here, '81' is the PCIe bus number on which Xilinx QDMA device is installed. - # lspci | grep Xilinx - 81:00.0 Memory controller: Xilinx Corporation Device 903f - 81:00.1 Memory controller: Xilinx Corporation Device 913f - 81:00.2 Memory controller: Xilinx Corporation Device 923f - 81:00.3 Memory controller: Xilinx Corporation Device 933f - - iii. Execute the following commands required for running the DPDK application - # mkdir /mnt/huge - # mount -t hugetlbfs nodev /mnt/huge - # modprobe uio - # insmod //dpdk-stable/dpdk-kmods/linux/igb_uio/igb_uio.ko - - iv. Bind PF ports to the igb_uio module as shown below - # ../../usertools/dpdk-devbind.py -b igb_uio 81:00.0 - # ../../usertools/dpdk-devbind.py -b igb_uio 81:00.1 - # ../../usertools/dpdk-devbind.py -b igb_uio 81:00.2 - # ../../usertools/dpdk-devbind.py -b igb_uio 81:00.3 - - v. The execution of steps iii and iv creates a max_vfs file entry in /sys/bus/pci/devices/0000::.. - - vi. Enable VFs for each PF by writing the number of VFs to enable to this file as shown below. - This example creates 1 VF for each PF. - # echo 1 > /sys/bus/pci/devices/0000\:81\:00.0/max_vfs - # echo 1 > /sys/bus/pci/devices/0000\:81\:00.1/max_vfs - # echo 1 > /sys/bus/pci/devices/0000\:81\:00.2/max_vfs - # echo 1 > /sys/bus/pci/devices/0000\:81\:00.3/max_vfs - - vii. Run the lspci command on the console and verify that the VFs are listed in the output as shown below - # lspci | grep Xilinx - 81:00.0 Memory controller: Xilinx Corporation Device 903f - 81:00.1 Memory controller: Xilinx Corporation Device 913f - 81:00.2 Memory controller: Xilinx Corporation Device 923f - 81:00.3 Memory controller: Xilinx Corporation Device 933f - 81:00.4 Memory controller: Xilinx Corporation Device a03f - 81:08.4 Memory controller: Xilinx Corporation Device a13f - 81:10.0 Memory controller: Xilinx Corporation Device a23f - 81:17.4 Memory controller: Xilinx Corporation Device a33f - - viii. Execute the following commands to bind the VF ports to igb_uio module - # ../../usertools/dpdk-devbind.py -b igb_uio 81:00.4 - # ../../usertools/dpdk-devbind.py -b igb_uio 81:08.4 - # ../../usertools/dpdk-devbind.py -b igb_uio 81:10.0 - # ../../usertools/dpdk-devbind.py -b igb_uio 81:17.4 - - ix. Run the qdma_testapp using the following command - #./build/qdma_testapp -c 0xf -n 4 - - '-c' represents processor mask - - '-n' represents number of memory channels - -CLI support in qdma_testapp -^^^^^^^^^^^^^^^^^^^^^^^^^^^ - -Sample log of the qdma_testapp execution is given below. -After running the qdma_testapp, command line prompt appears on the console as shown below. - -:: - - #./build/qdma_testapp -c 0xf -n 4 - QDMA testapp rte eal init... - EAL: Detected 8 lcore(s) - EAL: Probing VFIO support... - EAL: PCI device 0000:81:00.0 on NUMA socket -1 - EAL: probe driver: 10ee:903f net_qdma - EAL: PCI device 0000:81:00.1 on NUMA socket -1 - EAL: probe driver: 10ee:913f net_qdma - EAL: PCI device 0000:81:00.2 on NUMA socket -1 - EAL: probe driver: 10ee:923f net_qdma - EAL: PCI device 0000:81:00.3 on NUMA socket -1 - EAL: probe driver: 10ee:933f net_qdma - EAL: PCI device 0000:81:00.4 on NUMA socket -1 - EAL: probe driver: 10ee:a03f net_qdma - EAL: PCI device 0000:81:08.4 on NUMA socket -1 - EAL: probe driver: 10ee:a13f net_qdma - EAL: PCI device 0000:81:10.0 on NUMA socket -1 - EAL: probe driver: 10ee:a23f net_qdma - EAL: PCI device 0000:81:17.4 on NUMA socket -1 - EAL: probe driver: 10ee:a33f net_qdma - Ethernet Device Count: 8 - Logical Core Count: 4 - xilinx-app> - -Commands supported by the qdma_testapp CLI -++++++++++++++++++++++++++++++++++++++++++ - -1. port_init - - This command assigns queues to the port, sets up required resources for the queues, and prepares queues for data processing. - Format for this commad is: - - port_init - - port-id represents a logical numbering for PCIe functions in the order they are bind to igb_uio driver. - The first PCIe function that is bound has port id as 0. - - num-queues represents the total number of queues to be assigned to the port - - num-st-queues represents the total number of queues to be configured in streaming mode. - This implies that the (num-queues - num-st-queues) number of queues has to be configured in memory mapped mode. - - ring-depth represents the number of entries in C2H and H2C descriptor rings of each queue of the port - - pkt-buff-size represents the size of the data that a single C2H or H2C descriptor can support - - Example usage: - - port_init 1 32 16 1024 4096 - - This example initializes Port 1 with first 16 queues in streaming mode and remaining 16 queues in memory mapped mode. - Number of C2H and H2C descriptor ring depth is set to 1024 and data buffer of 4KB supported by each descriptor. - -2. port_close - - This command frees up all the allocated resources and removes the queues associated with the port. - Format for this commad is: - - port_close - - **port-id** represents a logical numbering for PCIe functions in the order they are bind to igb_uio driver. - The first PCIe function that is bound has port id as 0. - - Example usage: - - :: - - port_close 0 - - This example closes the port 0. Port 0 can again be re-initialized with `port_init` command after `port_close` command. - -3. port_reset - - This command resets the DPDK port. This command is supported for VF port only. - This command closes the port and re-initializes it with the values provided in this command. - Format for this commad is: - - port_reset - - port-id represents a logical numbering for PCIe functions in the order they are bind to igb_uio driver. - The first PCIe function that is bound has port id as 0. - - num-queues represents the total number of queues to be assigned to the port - - num-st-queues represents the total number of queues to be configured in streaming mode. - This implies that the (num-queues - num-st-queues) number of queues has to be configured in memory mapped mode. - - ring-depth represents the number of entries in C2H and H2C descriptor rings of each queue of the port - - pkt-buff-size represents the size of the data that a single C2H or H2C descriptor can support - - Example usage: - - port_reset 4 32 16 1024 4096 - - This example command resets the port 4 and re-initializes it with first 16 queues in streaming mode and - remaining 16 queues in memory mapped mode. Number of C2H and H2C descriptor ring depth is set to 1024 - and data buffer of 4KB supported by each descriptor. - -4. port_remove - - This command frees up all the resources allocated for the port and removes the port from application use. - User will need to restart the application to use the port again. - Format for this commad is: - - port_remove - - port-id represents a logical numbering for PCIe functions in the order they are bind to igb_uio driver. - The first PCIe function that is bound has port id as 0. - - Example usage: - - port_remove 4 - - This example removes the port 4. Restart the application to use port 4 again. - -5. dma_to_device - - This command is used to DMA the data from host to card. - Format for this commad is: - - dma_to_device - - port-id represents a logical numbering for PCIe functions in the order they are bind to igb_uio driver. - The first PCIe function that is bound has port id as 0. - - num-queues represents the total number of queues to use for transmitting the data - - input-filename represents the path to a valid binary data file, contents of which needs to be DMA'ed - - dst-addr represents the destination address (offset) in the card to where DMA should be done in memory mapped mode. - This field is ignored for streaming mode queues. - - size represents the amount of data in bytes that needs to be transmitted to the card from the given input file. - Data will be segmented across queues such that the total data transferred to the card is `size` amount - - iterations represents the number of loops to repeat the same DMA transfer - - Example usage: - - dma_to_device 0 2048 mm_datafile_1MB.bin 0 524288 0 - - This example segments the (524288) bytes from the mm_datafile_1MB.bin file equally to 2048 queues - and transmits the segmented data on each queue starting at destination BRAM offset 0 for 1st queue, - offset (1*524288)/2048 for 2nd queue, and so on. - -6. dma_from_device - - This command is used to DMA the data from card to host. - Format for this commad is: - - dma_from_device - - port-id represents a logical numbering for PCIe functions in the order they are bind to igb_uio driver. - The first PCIe function that is bound has port id as 0. - - num-queues represents the total number of queues to use to receive the data - - output-filename represents the path to output file to dump the received data - - src-addr represents the source address (offset) in the card from where DMA should be done in memory mapped mode. - This field is ignored for streaming mode queues. - - size represents the amount of data in bytes that needs to be received from the card. - Data will be segmented across queues such that the total data transferred from the card is `size` amount - - iterations represents the number of loops to repeat the same DMA transfer - - Example usage: - - dma_from_device 0 2048 port0_qcount2048_size524288.bin 0 524288 0 - - This example receives 524288 bytes from 2048 queues and writes to port0_qcount2048_size524288.bin file. - 1st queue receives (524288/2048) bytes of data from BRAM offset 0, - 2nd queue receives (524288/2048) bytes of data from BRAM offset (1*524288)/2048, and so on. - -7. reg_read - - This command is used to read the specified register. - Format for this commad is: - - reg_read
- - port-id represents a logical numbering for PCIe functions in the order they are bind to igb_uio driver. - The first PCIe function that is bound has port id as 0. - - bar-num represents the PCIe BAR where the register is located - - address represents offset of the register in the PCIe BAR `bar-num` - -8. reg_write - - This command is used to write a 32-bit value to the specified register. - Format for this commad is: - - reg_write
- - port-id represents a logical numbering for PCIe functions in the order they are bind to igb_uio driver. - The first PCIe function that is bound has port id as 0. - - bar-num represents the PCIe BAR where the register is located - - address represents offset of the register in the PCIe BAR `bar-num` - - value represents the value to be written at the register offset `address` - -9. reg_dump - - This command dumps important QDMA registers values of the given port on console. - Format for this commad is: - - reg_dump - - port-id represents a logical numbering for PCIe functions in the order they are bind to igb_uio driver. - The first PCIe function that is bound has port id as 0. - -10. reg_info_read - - This command reads the field info for the specified number of registers of the given port on console. - Format for this commad is: - - reg_info_read - - port-id represents a logical numbering for PCIe functions in the order they are bind to igb_uio driver. - The first PCIe function that is bound has port id as 0. - - reg-addr represents offset of the register in the PCIe BAR bar-num - - rum-regs represents number of registers to read - -11. queue_dump - - This command dumps the queue context of the specified queue number of the given port. - Format for this commad is: - - queue_dump - - port-id represents a logical numbering for PCIe functions in the order they are bind to igb_uio driver. - The first PCIe function that is bound has port id as 0. - - queue-id represents the queue number relative to the port, whose context information needs to be logged - -12. desc_dump - - This command dumps the descriptors of the C2H and H2C rings of the specified queue number of the given port. - Format for this commad is: - - desc_dump - - port-id represents a logical numbering for PCIe functions in the order they are bind to igb_uio driver. - The first PCIe function that is bound has port id as 0. - - queue-id represents the queue number relative to the port, whose C2H and H2C ring descriptors needs to be dumped - -13. load_cmds - - This command executes the list of CLI commands from the given file. - Format for this commad is: - - load_cmds - - file_name represents path to a valid file containing list of above described CLI commands to be executed in sequence. - -14. help - - This command dumps the help menu with supported commands and their format. - Format for this commad is: - - help - -15. ctrl+d - - The keyboard keys Ctrl and D when pressed together quits the application. - -Instructions on how to use proc-info test for driver debugging: -+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ - -1. Apply the below patch on top of the code changes mentioned in the dpdk driver documentation page and build the dpdk source code. - patch -p1 < 0001-Add-QDMA-xdebug-to-proc-info-of-dpdk-22.11.patch - -2. Run the testpmd application as primary application on one linux terminal - ./build/app/dpdk-testpmd -l 1-17 -n 4 -a 65:00.0,desc_prefetch=1,cmpt_desc_len=16 --log-level=3 -- --burst=256 -i --nb-cores=1 --rxq=1 --txq=1 --forward-mode=io --rxd=2048 --txd=2048 --mbcache=512 --mbuf-size=4096 - -3. Run the proc info as secondary application on another linux terminal as mentioned below with diferent port combinations. -One port: - ./build/app/dpdk-proc-info -a 81:00.0 --log-level=7 -- -p 1 -q 0 -g - ./build/app/dpdk-proc-info -a 81:00.0 --log-level=7 -- -p 1 -q 0 --qdevice - ./build/app/dpdk-proc-info -a 81:00.0 --log-level=7 -- -p 1 -q 0 --qinfo - ./build/app/dpdk-proc-info -a 81:00.0 --log-level=7 -- -p 1 -q 0 --qstats_clr - ./build/app/dpdk-proc-info -a 81:00.0 --log-level=7 -- -p 1 -q 0 --qstats - ./build/app/dpdk-proc-info -a 81:00.0 --log-level=7 -- -p 1 -q 0 --desc-dump tx - ./build/app/dpdk-proc-info -a 81:00.0 --log-level=7 -- -p 1 -q 0 --desc-dump rx - ./build/app/dpdk-proc-info -a 81:00.0 --log-level=7 -- -p 1 -q 0 --desc-dump cmpt - ./build/app/dpdk-proc-info -a 81:00.0 --log-level=7 -- -p 1 -q 0 --stats -Two ports: - ./build/app/dpdk-proc-info -a 81:00.0, -a 81:00.1, --log-level=7 -- -p 3 -q 0 -g - ./build/app/dpdk-proc-info -a 81:00.0, -a 81:00.1, --log-level=7 -- -p 3 -q 0 --qdevice - ./build/app/dpdk-proc-info -a 81:00.0, -a 81:00.1, --log-level=7 -- -p 3 -q 0 --qinfo - ./build/app/dpdk-proc-info -a 81:00.0, -a 81:00.1, --log-level=7 -- -p 3 -q 0 --qstats_clr - ./build/app/dpdk-proc-info -a 81:00.0, -a 81:00.1, --log-level=7 -- -p 3 -q 0 --qstats - ./build/app/dpdk-proc-info -a 81:00.0, -a 81:00.1, --log-level=7 -- -p 3 -q 0 --desc-dump tx - ./build/app/dpdk-proc-info -a 81:00.0, -a 81:00.1, --log-level=7 -- -p 3 -q 0 --desc-dump rx - ./build/app/dpdk-proc-info -a 81:00.0, -a 81:00.1, --log-level=7 -- -p 3 -q 0 --desc-dump cmpt - ./build/app/dpdk-proc-info -a 81:00.0, -a 81:00.1, --log-level=7 -- -p 3 -q 0 --stats -4. Available commands for proc info are mentioned below. - -m to display DPDK memory zones, segments and TAILQ information - -g to display DPDK QDMA PMD global CSR info - -p PORTMASK: hexadecimal bitmask of ports to retrieve stats for - --stats: to display port statistics, enabled by default - --qdevice: to display QDMA device structure - --qinfo: to display QDMA queue context and queue structures - --qstats: to display QDMA Tx and Rx queue stats - --qstats_clr: to clear QDMA Tx and Rx queue stats - --desc-dump {rx | tx | cmpt}: to dump QDMA queue descriptors - --xstats: to display extended port statistics, disabled by default - --metrics: to display derived metrics of the ports, disabled by - - - -/*- - * BSD LICENSE - * - * Copyright (c) 2017-2022 Xilinx, Inc. All rights reserved. - * Copyright (c) 2022-2023, Advanced Micro Devices, Inc. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * * Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - diff --git a/QDMA/DPDK/drivers/net/qdma/meson.build b/QDMA/DPDK/drivers/net/qdma/meson.build deleted file mode 100755 index 0a04d4d9b..000000000 --- a/QDMA/DPDK/drivers/net/qdma/meson.build +++ /dev/null @@ -1,79 +0,0 @@ -# BSD LICENSE -# -# Copyright (c) 2021-2022 Xilinx, Inc. All rights reserved. -# Copyright (c) 2022-2023, Advanced Micro Devices, Inc. All rights reserved. -# -# Redistribution and use in source and binary forms, with or without -# modification, are permitted provided that the following conditions -# are met: -# -# * Redistributions of source code must retain the above copyright -# notice, this list of conditions and the following disclaimer. -# * Redistributions in binary form must reproduce the above copyright -# notice, this list of conditions and the following disclaimer in -# the documentation and/or other materials provided with the -# distribution. -# * Neither the name of the copyright holder nor the names of its -# contributors may be used to endorse or promote products derived -# from this software without specific prior written permission. -# -# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -cflags += ['-DRTE_LIBRTE_QDMA_PMD'] -cflags += ['-DDMA_BRAM_SIZE=524288'] -cflags += ['-DTHROUGHPUT_MEASUREMENT'] - -# Use QDMA_DPDK_22_11 compiler flag for DPDK v22.11 -# Use QDMA_DPDK_21_11 compiler flag for DPDK v21.11 -# Use QDMA_DPDK_20_11 compiler flag for DPDK v20.11 -cflags += ['-DQDMA_DPDK_22_11'] - -includes += include_directories('.') -includes += include_directories('qdma_access') -includes += include_directories('qdma_access/qdma_soft_access') -includes += include_directories('qdma_access/eqdma_soft_access') -includes += include_directories('qdma_access/qdma_cpm4_access') -includes += include_directories('qdma_access/eqdma_cpm5_access') - -headers += files('rte_pmd_qdma.h') - -deps += ['mempool_ring'] - -sources = files( - 'qdma_ethdev.c', - 'qdma_vf_ethdev.c', - 'qdma_devops.c', - 'qdma_common.c', - 'qdma_rxtx.c', - 'qdma_xdebug.c', - 'qdma_user.c', - 'qdma_access/eqdma_soft_access/eqdma_soft_access.c', - 'qdma_access/eqdma_soft_access/eqdma_soft_reg_dump.c', - 'qdma_access/qdma_cpm4_access/qdma_cpm4_access.c', - 'qdma_access/qdma_cpm4_access/qdma_cpm4_reg_dump.c', - 'qdma_access/eqdma_cpm5_access/eqdma_cpm5_access.c', - 'qdma_access/eqdma_cpm5_access/eqdma_cpm5_reg_dump.c', - 'qdma_access/qdma_soft_access/qdma_soft_access.c', - 'qdma_access/qdma_list.c', - 'qdma_access/qdma_resource_mgmt.c', - 'qdma_access/qdma_mbox_protocol.c', - 'qdma_access/qdma_access_common.c', - 'qdma_mbox.c', - 'qdma_platform.c', - 'rte_pmd_qdma.c', - 'qdma_dpdk_compat.c' -) - -if arch_subdir == 'x86' - sources += files('qdma_rxtx_vec_sse.c') -endif \ No newline at end of file diff --git a/QDMA/DPDK/drivers/net/qdma/qdma.h b/QDMA/DPDK/drivers/net/qdma/qdma.h deleted file mode 100755 index b69906964..000000000 --- a/QDMA/DPDK/drivers/net/qdma/qdma.h +++ /dev/null @@ -1,500 +0,0 @@ -/*- - * BSD LICENSE - * - * Copyright (c) 2017-2022 Xilinx, Inc. All rights reserved. - * Copyright (c) 2022-2023, Advanced Micro Devices, Inc. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * * Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#ifndef __QDMA_H__ -#define __QDMA_H__ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include "qdma_user.h" -#include "qdma_resource_mgmt.h" -#include "qdma_mbox.h" -#include "rte_pmd_qdma.h" -#include "qdma_log.h" -#include "qdma_dpdk_compat.h" - -#define QDMA_NUM_BARS (6) -#define DEFAULT_PF_CONFIG_BAR (0) -#define DEFAULT_VF_CONFIG_BAR (0) -#define BAR_ID_INVALID (-1) - -#define QDMA_FUNC_ID_INVALID 0xFFFF - -#define DEFAULT_QUEUE_BASE (0) - -#define QDMA_MAX_BURST_SIZE (128) -#define QDMA_MIN_RXBUFF_SIZE (256) - -/* Descriptor Rings aligned to 4KB boundaries - only supported value */ -#define QDMA_ALIGN (4096) - -#define DEFAULT_TIMER_CNT_TRIG_MODE_TIMER (5) -#define DEFAULT_TIMER_CNT_TRIG_MODE_COUNT_TIMER (30) - -#define MIN_RX_PIDX_UPDATE_THRESHOLD (1) -#define MIN_TX_PIDX_UPDATE_THRESHOLD (1) -#define DEFAULT_MM_CMPT_CNT_THRESHOLD (2) -#define QDMA_TXQ_PIDX_UPDATE_INTERVAL (1000) //100 uSec - -/** Delays **/ -#define MAILBOX_PF_MSG_DELAY (20) -#define MAILBOX_VF_MSG_DELAY (10) -#define MAILBOX_PROG_POLL_COUNT (1250) - -#define WB_TIMEOUT (100000) -#define RESET_TIMEOUT (60000) -#define SHUTDOWN_TIMEOUT (60000) - -#define QDMA_MAX_BUFLEN (2048 * 10) - -#ifdef spin_lock_init -#undef spin_lock_init -#endif -#define spin_lock_init(sl) rte_spinlock_init(sl) - -/** Completion Context config */ -#define CMPT_DEFAULT_COLOR_BIT (1) -#define CMPT_CNTXT_DESC_SIZE_8B (0) -#define CMPT_CNTXT_DESC_SIZE_16B (1) -#define CMPT_CNTXT_DESC_SIZE_32B (2) -#define CMPT_CNTXT_DESC_SIZE_64B (3) - -/** SOFTWARE DESC CONTEXT */ -#define SW_DESC_CNTXT_8B_BYPASS_DMA (0) -#define SW_DESC_CNTXT_16B_BYPASS_DMA (1) -#define SW_DESC_CNTXT_32B_BYPASS_DMA (2) -#define SW_DESC_CNTXT_64B_BYPASS_DMA (3) - -#define SW_DESC_CNTXT_C2H_STREAM_DMA (0) -#define SW_DESC_CNTXT_H2C_STREAM_DMA (1) -#define SW_DESC_CNTXT_MEMORY_MAP_DMA (2) - -#define DEFAULT_QDMA_CMPT_DESC_LEN (RTE_PMD_QDMA_CMPT_DESC_LEN_8B) - -#define LATENCY_MAX_QUEUES 4 -#define LATENCY_CNT 20 - -#ifdef LATENCY_MEASUREMENT -extern const struct rte_memzone *txq_lat_buf_mz; -extern const struct rte_memzone *rxq_lat_buf_mz; -extern double (*h2c_pidx_to_hw_cidx_lat)[LATENCY_CNT]; -extern double (*c2h_pidx_to_cmpt_pidx_lat)[LATENCY_CNT]; -#endif - -enum dma_data_direction { - DMA_BIDIRECTIONAL = 0, - DMA_TO_DEVICE = 1, - DMA_FROM_DEVICE = 2, - DMA_NONE = 3, -}; - -enum reset_state_t { - RESET_STATE_IDLE, - RESET_STATE_RECV_PF_RESET_REQ, - RESET_STATE_RECV_PF_RESET_DONE, - RESET_STATE_INVALID -}; - -/** MM Write-back status structure **/ -struct __attribute__ ((packed)) wb_status -{ - volatile uint16_t pidx; /** in C2H WB **/ - volatile uint16_t cidx; /** Consumer-index **/ - uint32_t rsvd2; /** Reserved. **/ -}; - -struct qdma_pkt_stats { - uint64_t pkts; - uint64_t bytes; -}; - -struct qdma_pkt_lat { - double prev; - double curr; -}; - -struct qdma_txq_stats { - uint16_t pidx; - uint16_t wrb_cidx; - uint16_t txq_tail; - uint16_t in_use_desc; - uint16_t nb_pkts; - uint16_t lat_cnt; - uint32_t ring_wrap_cnt; - uint32_t txq_full_cnt; -#ifdef LATENCY_MEASUREMENT - uint32_t wrb_cidx_cnt_no_change; - uint32_t wrb_cidx_cnt_lt_8; - uint32_t wrb_cidx_cnt_8_to_32; - uint32_t wrb_cidx_cnt_32_to_64; - uint32_t wrb_cidx_cnt_gt_64; - struct qdma_pkt_lat pkt_lat; -#endif -}; - -struct qdma_rxq_stats { - uint16_t pidx; - uint16_t wrb_pidx; - uint16_t wrb_cidx; - uint16_t rxq_cmpt_tail; - uint16_t pending_desc; - uint16_t lat_cnt; - uint32_t ring_wrap_cnt; - uint32_t mbuf_avail_cnt; - uint32_t mbuf_in_use_cnt; -#ifdef LATENCY_MEASUREMENT - struct qdma_pkt_lat pkt_lat; -#endif -}; - -/* - * Structure associated with each CMPT queue. - */ -struct qdma_cmpt_queue { - struct qdma_ul_cmpt_ring *cmpt_ring; - struct wb_status *wb_status; - struct qdma_q_cmpt_cidx_reg_info cmpt_cidx_info; - struct rte_eth_dev *dev; - - uint16_t cmpt_desc_len; - uint16_t nb_cmpt_desc; - uint32_t queue_id; /**< CMPT queue index. */ - - uint8_t status:1; - uint8_t st_mode:1; /**< dma-mode: MM or ST */ - uint8_t dis_overflow_check:1; - uint8_t func_id; - uint16_t port_id; /**< Device port identifier. */ - int8_t ringszidx; - int8_t threshidx; - int8_t timeridx; - int8_t triggermode; - /* completion descriptor memzone */ - const struct rte_memzone *cmpt_mz; -}; - -/** - * Structure associated with each RX queue. - */ -struct qdma_rx_queue { - /* Move more accessed elementes into first cacheline */ - struct rte_mempool *mb_pool; /**< mbuf pool to populate RX ring. */ - void *rx_ring; /**< RX ring virtual address */ - union qdma_ul_st_cmpt_ring *cmpt_ring; - struct wb_status *wb_status; - struct rte_mbuf **sw_ring; /**< address of RX software ring. */ - enum rte_pmd_qdma_bypass_desc_len bypass_desc_sz:7; - - uint16_t rx_tail; - uint16_t cmpt_desc_len; - uint16_t rx_buff_size; - uint16_t nb_rx_desc; /**< number of RX descriptors. */ - uint16_t nb_rx_cmpt_desc; - uint32_t queue_id; /**< RX queue index. */ - uint64_t mbuf_initializer; /**< value to init mbufs */ - - struct qdma_q_pidx_reg_info q_pidx_info; - struct qdma_q_cmpt_cidx_reg_info cmpt_cidx_info; - struct qdma_pkt_stats stats; - struct qdma_rxq_stats qstats; - - struct rte_eth_dev *dev; - - uint16_t port_id; /**< Device port identifier. */ - uint8_t status:1; - uint8_t err:1; - uint8_t st_mode:1; /**< dma-mode: MM or ST */ - uint8_t dump_immediate_data:1; - uint8_t rx_deferred_start:1; - uint8_t en_prefetch:1; - uint8_t en_bypass:1; - uint8_t en_bypass_prefetch:1; - uint8_t dis_overflow_check:1; - - union qdma_ul_st_cmpt_ring cmpt_data[QDMA_MAX_BURST_SIZE]; - - uint8_t func_id; /**< RX queue index. */ - uint64_t ep_addr; - - int8_t ringszidx; - int8_t cmpt_ringszidx; - int8_t buffszidx; - int8_t threshidx; - int8_t timeridx; - int8_t triggermode; - - const struct rte_memzone *rx_mz; - /* C2H stream mode, completion descriptor result */ - const struct rte_memzone *rx_cmpt_mz; - -#ifdef QDMA_LATENCY_OPTIMIZED - /**< pend_pkt_moving_avg: average rate of packets received */ - unsigned int pend_pkt_moving_avg; - /**< pend_pkt_avg_thr_hi: higher average threshold */ - unsigned int pend_pkt_avg_thr_hi; - /**< pend_pkt_avg_thr_lo: lower average threshold */ - unsigned int pend_pkt_avg_thr_lo; - /**< sorted_c2h_cntr_idx: sorted c2h counter index */ - int8_t sorted_c2h_cntr_idx; - /**< c2h_cntr_monitor_cnt: c2h counter stagnant monitor count */ - unsigned char c2h_cntr_monitor_cnt; -#endif //QDMA_LATENCY_OPTIMIZED -}; - -/** - * Structure associated with each TX queue. - */ -struct qdma_tx_queue { - /* Move more accessed elementes into first cacheline */ - enum rte_pmd_qdma_bypass_desc_len bypass_desc_sz:7; - uint16_t tx_fl_tail; - void *tx_ring; /* TX ring virtual address*/ - struct qdma_q_pidx_reg_info q_pidx_info; - - struct wb_status *wb_status; - struct rte_mbuf **sw_ring;/* SW ring virtual address*/ - uint16_t tx_desc_pend; - uint16_t nb_tx_desc; /* No of TX descriptors.*/ - rte_spinlock_t pidx_update_lock; - uint64_t offloads; /* Tx offloads */ - - struct rte_eth_dev *dev; - - uint8_t st_mode:1;/* dma-mode: MM or ST */ - uint8_t tx_deferred_start:1; - uint8_t en_bypass:1; - uint8_t status:1; - uint16_t port_id; /* Device port identifier. */ - uint8_t func_id; /* RX queue index. */ - int8_t ringszidx; - - struct qdma_pkt_stats stats; - struct qdma_txq_stats qstats; - - uint64_t ep_addr; - uint32_t queue_id; /* TX queue index. */ - uint32_t num_queues; /* TX queue index. */ - const struct rte_memzone *tx_mz; -}; - -struct qdma_vf_info { - uint16_t func_id; -}; - -struct queue_info { - uint32_t queue_mode:1; - uint32_t rx_bypass_mode:2; - uint32_t tx_bypass_mode:1; - uint32_t cmpt_desc_sz:7; - uint8_t immediate_data_state:1; - uint8_t dis_cmpt_ovf_chk:1; - uint8_t en_prefetch:1; - enum rte_pmd_qdma_bypass_desc_len rx_bypass_desc_sz:7; - enum rte_pmd_qdma_bypass_desc_len tx_bypass_desc_sz:7; - uint8_t timer_count; - int8_t trigger_mode; -}; - -struct qdma_pci_dev { - void *bar_addr[QDMA_NUM_BARS]; /* memory mapped I/O addr for BARs */ - int config_bar_idx; - int user_bar_idx; - int bypass_bar_idx; - - /* Driver Attributes */ - uint32_t qsets_en; /* no. of queue pairs enabled */ - uint32_t queue_base; - uint16_t func_id; /* Function id */ - - /* DMA identifier used by the resource manager - * for the DMA instances used by this driver - */ - uint32_t dma_device_index; - - /* Device capabilities */ - struct qdma_dev_attributes dev_cap; - - uint8_t cmpt_desc_len; - uint8_t c2h_bypass_mode; - uint8_t h2c_bypass_mode; -#ifdef TANDEM_BOOT_SUPPORTED - uint8_t en_st_mode; -#endif - uint8_t trigger_mode; - uint8_t timer_count; - - uint8_t dev_configured:1; - uint8_t is_vf:1; - uint8_t is_master:1; - uint8_t en_desc_prefetch:1; - - /* Reset state */ - uint8_t reset_in_progress; - enum reset_state_t reset_state; - - /* Hardware version info*/ - uint32_t vivado_rel:4; - uint32_t rtl_version:4; - uint32_t device_type:4; - uint32_t ip_type:4; - - struct queue_info *q_info; - struct qdma_dev_mbox mbox; - uint8_t init_q_range; - - uint32_t g_ring_sz[QDMA_NUM_RING_SIZES]; - uint32_t g_c2h_cnt_th[QDMA_NUM_C2H_COUNTERS]; - uint32_t g_c2h_buf_sz[QDMA_NUM_C2H_BUFFER_SIZES]; - uint32_t g_c2h_timer_cnt[QDMA_NUM_C2H_TIMERS]; -#ifdef QDMA_LATENCY_OPTIMIZED - uint32_t sorted_idx_c2h_cnt_th[QDMA_NUM_C2H_COUNTERS]; -#endif //QDMA_LATENCY_OPTIMIZED - void **cmpt_queues; - /*Pointer to QDMA access layer function pointers*/ - struct qdma_hw_access *hw_access; - - struct qdma_vf_info *vfinfo; - uint8_t vf_online_count; - - int16_t tx_qid_statid_map[RTE_ETHDEV_QUEUE_STAT_CNTRS]; - int16_t rx_qid_statid_map[RTE_ETHDEV_QUEUE_STAT_CNTRS]; - - uint8_t rx_vec_allowed:1; - uint8_t tx_vec_allowed:1; -}; - -void qdma_dev_ops_init(struct rte_eth_dev *dev); -uint32_t qdma_read_reg(uint64_t reg_addr); -void qdma_write_reg(uint64_t reg_addr, uint32_t val); -void qdma_txq_pidx_update(void *arg); -int qdma_pf_csr_read(struct rte_eth_dev *dev); -int qdma_vf_csr_read(struct rte_eth_dev *dev); - -uint8_t qmda_get_desc_sz_idx(enum rte_pmd_qdma_bypass_desc_len); -int qdma_vf_dev_rx_queue_start(struct rte_eth_dev *dev, uint16_t qid); -int qdma_vf_dev_rx_queue_stop(struct rte_eth_dev *dev, uint16_t qid); -int qdma_vf_dev_tx_queue_start(struct rte_eth_dev *dev, uint16_t qid); -int qdma_vf_dev_tx_queue_stop(struct rte_eth_dev *dev, uint16_t qid); - -int qdma_init_rx_queue(struct qdma_rx_queue *rxq); -void qdma_reset_tx_queue(struct qdma_tx_queue *txq); -void qdma_reset_rx_queue(struct qdma_rx_queue *rxq); - -void qdma_clr_rx_queue_ctxts(struct rte_eth_dev *dev, uint32_t qid, - uint32_t mode); -void qdma_inv_rx_queue_ctxts(struct rte_eth_dev *dev, uint32_t qid, - uint32_t mode); -void qdma_clr_tx_queue_ctxts(struct rte_eth_dev *dev, uint32_t qid, - uint32_t mode); -void qdma_inv_tx_queue_ctxts(struct rte_eth_dev *dev, uint32_t qid, - uint32_t mode); -int qdma_identify_bars(struct rte_eth_dev *dev); -int qdma_get_hw_version(struct rte_eth_dev *dev); - -/* implemented in rxtx.c */ -uint16_t qdma_recv_pkts_st(struct qdma_rx_queue *rxq, struct rte_mbuf **rx_pkts, - uint16_t nb_pkts); -uint16_t qdma_recv_pkts_mm(struct qdma_rx_queue *rxq, struct rte_mbuf **rx_pkts, - uint16_t nb_pkts); -uint16_t qdma_xmit_pkts_st(struct qdma_tx_queue *txq, struct rte_mbuf **tx_pkts, - uint16_t nb_pkts); -uint16_t qdma_xmit_pkts_mm(struct qdma_tx_queue *txq, struct rte_mbuf **tx_pkts, - uint16_t nb_pkts); - -#ifdef TEST_64B_DESC_BYPASS -uint16_t qdma_xmit_64B_desc_bypass(struct qdma_tx_queue *txq, - struct rte_mbuf **tx_pkts, uint16_t nb_pkts); -#endif - -uint32_t qdma_pci_read_reg(struct rte_eth_dev *dev, uint32_t bar, uint32_t reg); -void qdma_pci_write_reg(struct rte_eth_dev *dev, uint32_t bar, - uint32_t reg, uint32_t val); - -int index_of_array(uint32_t *arr, uint32_t n, uint32_t element); - -int qdma_check_kvargs(struct rte_devargs *devargs, - struct qdma_pci_dev *qdma_dev); - -static inline const -struct rte_memzone *qdma_zone_reserve(struct rte_eth_dev *dev, - const char *ring_name, - uint32_t queue_id, - uint32_t ring_size, - int socket_id) -{ - char z_name[RTE_MEMZONE_NAMESIZE]; - snprintf(z_name, sizeof(z_name), "%s%s%d_%u", - dev->device->driver->name, ring_name, - dev->data->port_id, queue_id); - return rte_memzone_reserve_aligned(z_name, (uint64_t)ring_size, - socket_id, 0, QDMA_ALIGN); -} - -bool is_qdma_supported(struct rte_eth_dev *dev); -bool is_vf_device_supported(struct rte_eth_dev *dev); -bool is_pf_device_supported(struct rte_eth_dev *dev); - -void qdma_check_errors(void *arg); - -struct rte_mbuf *prepare_segmented_packet(struct qdma_rx_queue *rxq, - uint16_t pkt_length, uint16_t *tail); -int reclaim_tx_mbuf(struct qdma_tx_queue *txq, - uint16_t cidx, uint16_t free_cnt); -int qdma_ul_extract_st_cmpt_info(void *ul_cmpt_entry, void *cmpt_info); - -/* Transmit API for Streaming mode */ -uint16_t qdma_xmit_pkts_vec(void *tx_queue, - struct rte_mbuf **tx_pkts, uint16_t nb_pkts); -uint16_t qdma_xmit_pkts_st_vec(struct qdma_tx_queue *txq, - struct rte_mbuf **tx_pkts, uint16_t nb_pkts); - -/* Receive API for Streaming mode */ -uint16_t qdma_recv_pkts_vec(void *rx_queue, - struct rte_mbuf **rx_pkts, uint16_t nb_pkts); -uint16_t qdma_recv_pkts_st_vec(struct qdma_rx_queue *rxq, - struct rte_mbuf **rx_pkts, uint16_t nb_pkts); - -void __rte_cold qdma_set_tx_function(struct rte_eth_dev *dev); -void __rte_cold qdma_set_rx_function(struct rte_eth_dev *dev); - -int qdma_tx_qstats_clear(struct rte_eth_dev *dev, uint16_t queue); -int qdma_rx_qstats_clear(struct rte_eth_dev *dev, uint16_t queue); - -#endif /* ifndef __QDMA_H__ */ diff --git a/QDMA/DPDK/drivers/net/qdma/qdma_access/eqdma_cpm5_access/eqdma_cpm5_access.c b/QDMA/DPDK/drivers/net/qdma/qdma_access/eqdma_cpm5_access/eqdma_cpm5_access.c deleted file mode 100755 index 11f9cca14..000000000 --- a/QDMA/DPDK/drivers/net/qdma/qdma_access/eqdma_cpm5_access/eqdma_cpm5_access.c +++ /dev/null @@ -1,6879 +0,0 @@ -/* - * Copyright (c) 2019-2022, Xilinx, Inc. All rights reserved. - * Copyright (c) 2022, Advanced Micro Devices, Inc. All rights reserved. - * - * BSD LICENSE - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * * Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include "eqdma_cpm5_access.h" -#include "eqdma_cpm5_reg.h" -#include "qdma_reg_dump.h" - -#ifdef ENABLE_WPP_TRACING -#include "eqdma_cpm5_access.tmh" -#endif - -#define UNUSED(x) (void)(x) - -/** EQDMA Context array size */ -#define EQDMA_CPM5_FMAP_NUM_WORDS 2 -#define EQDMA_CPM5_SW_CONTEXT_NUM_WORDS 8 -#define EQDMA_CPM5_HW_CONTEXT_NUM_WORDS 2 -#define EQDMA_CPM5_PFETCH_CONTEXT_NUM_WORDS 2 -#define EQDMA_CPM5_CR_CONTEXT_NUM_WORDS 1 -#define EQDMA_CPM5_CMPT_CONTEXT_NUM_WORDS 6 -#define EQDMA_CPM5_IND_INTR_CONTEXT_NUM_WORDS 4 - -#define EQDMA_CPM5_VF_USER_BAR_ID 2 - -#define EQDMA_CPM5_REG_GROUP_1_START_ADDR 0x000 -#define EQDMA_CPM5_REG_GROUP_2_START_ADDR 0x804 -#define EQDMA_CPM5_REG_GROUP_3_START_ADDR 0xB00 -#define EQDMA_CPM5_REG_GROUP_4_START_ADDR 0x5014 - -#define EQDMA_CPM5_TOTAL_LEAF_ERROR_AGGREGATORS 11 -#define EQDMA_CPM5_GLBL_TRQ_ERR_ALL_MASK 0XB3 -#define EQDMA_CPM5_GLBL_DSC_ERR_ALL_MASK 0X1F9037E -#define EQDMA_CPM5_C2H_ERR_ALL_MASK 0X3F6DF -#define EQDMA_CPM5_C2H_FATAL_ERR_ALL_MASK 0X1FDF1B -#define EQDMA_CPM5_H2C_ERR_ALL_MASK 0X3F -#define EQDMA_CPM5_SBE_ERR_ALL_MASK 0XFFFFFFFF -#define EQDMA_CPM5_DBE_ERR_ALL_MASK 0XFFFFFFFF -#define EQDMA_CPM5_MM_C2H_ERR_ALL_MASK 0X70000003 -#define EQDMA_CPM5_MM_H2C0_ERR_ALL_MASK 0X3041013E - -/* H2C Throttle settings */ -#define EQDMA_CPM5_H2C_THROT_DATA_THRESH 0x5000 -#define EQDMA_CPM5_THROT_EN_DATA 1 -#define EQDMA_CPM5_THROT_EN_REQ 0 -#define EQDMA_CPM5_H2C_THROT_REQ_THRESH 0xC0 - - -/** Auxillary Bitmasks for fields spanning multiple words */ -#define EQDMA_CPM5_SW_CTXT_PASID_GET_H_MASK GENMASK(21, 12) -#define EQDMA_CPM5_SW_CTXT_PASID_GET_L_MASK GENMASK(11, 0) -#define EQDMA_CPM5_SW_CTXT_VIRTIO_DSC_BASE_GET_H_MASK GENMASK_ULL(63, 53) -#define EQDMA_CPM5_SW_CTXT_VIRTIO_DSC_BASE_GET_M_MASK GENMASK_ULL(52, 21) -#define EQDMA_CPM5_SW_CTXT_VIRTIO_DSC_BASE_GET_L_MASK GENMASK_ULL(20, 0) -#define EQDMA_CPM5_CMPL_CTXT_PASID_GET_H_MASK GENMASK(21, 9) -#define EQDMA_CPM5_CMPL_CTXT_PASID_GET_L_MASK GENMASK(8, 0) -#define EQDMA_CPM5_INTR_CTXT_PASID_GET_H_MASK GENMASK(21, 9) -#define EQDMA_CPM5_INTR_CTXT_PASID_GET_L_MASK GENMASK(8, 0) - -#define EQDMA_CPM5_OFFSET_GLBL2_PF_BARLITE_EXT 0x10C - -#define QDMA_OFFSET_GLBL2_PF_BARLITE_INT 0x104 -#define QDMA_GLBL2_PF3_BAR_MAP_MASK GENMASK(23, 18) -#define QDMA_GLBL2_PF2_BAR_MAP_MASK GENMASK(17, 12) -#define QDMA_GLBL2_PF1_BAR_MAP_MASK GENMASK(11, 6) -#define QDMA_GLBL2_PF0_BAR_MAP_MASK GENMASK(5, 0) - -#define EQDMA_CPM5_GLBL2_DBG_MODE_EN_MASK BIT(4) -#define EQDMA_CPM5_GLBL2_DESC_ENG_MODE_MASK GENMASK(3, 2) -#define EQDMA_CPM5_GLBL2_FLR_PRESENT_MASK BIT(1) -#define EQDMA_CPM5_GLBL2_MAILBOX_EN_MASK BIT(0) - -#define EQDMA_CPM5_DEFAULT_C2H_INTR_TIMER_TICK 50 -#define PREFETCH_QUEUE_COUNT_STEP 4 -#define EQDMA_CPM5_DEFAULT_CMPT_COAL_MAX_BUF_SZ 0x3F - -/* TODO: This is work around and this needs to be auto generated from ODS */ -/** EQDMA_CPM5_IND_REG_SEL_FMAP */ -#define EQDMA_CPM5_FMAP_CTXT_W1_QID_MAX_MASK GENMASK(12, 0) -#define EQDMA_CPM5_FMAP_CTXT_W0_QID_MASK GENMASK(11, 0) - -static void eqdma_cpm5_hw_st_h2c_err_process(void *dev_hndl); -static void eqdma_cpm5_hw_st_c2h_err_process(void *dev_hndl); -static void eqdma_cpm5_hw_desc_err_process(void *dev_hndl); -static void eqdma_cpm5_hw_trq_err_process(void *dev_hndl); -static void eqdma_cpm5_hw_ram_sbe_err_process(void *dev_hndl); -static void eqdma_cpm5_hw_ram_dbe_err_process(void *dev_hndl); -static void eqdma_cpm5_mm_h2c0_err_process(void *dev_hndl); -static void eqdma_cpm5_mm_c2h0_err_process(void *dev_hndl); - -static struct eqdma_cpm5_hw_err_info - eqdma_cpm5_err_info[EQDMA_CPM5_ERRS_ALL] = { - /* Descriptor errors */ - { - EQDMA_CPM5_DSC_ERR_POISON, - "Poison error", - EQDMA_CPM5_GLBL_DSC_ERR_MSK_ADDR, - EQDMA_CPM5_GLBL_DSC_ERR_STS_ADDR, - GLBL_DSC_ERR_STS_POISON_MASK, - GLBL_ERR_STAT_ERR_DSC_MASK, - &eqdma_cpm5_hw_desc_err_process - }, - { - EQDMA_CPM5_DSC_ERR_UR_CA, - "Unsupported request or completer aborted error", - EQDMA_CPM5_GLBL_DSC_ERR_MSK_ADDR, - EQDMA_CPM5_GLBL_DSC_ERR_STS_ADDR, - GLBL_DSC_ERR_STS_UR_CA_MASK, - GLBL_ERR_STAT_ERR_DSC_MASK, - &eqdma_cpm5_hw_desc_err_process - }, - { - EQDMA_CPM5_DSC_ERR_BCNT, - "Unexpected Byte count in completion error", - EQDMA_CPM5_GLBL_DSC_ERR_MSK_ADDR, - EQDMA_CPM5_GLBL_DSC_ERR_STS_ADDR, - GLBL_DSC_ERR_STS_BCNT_MASK, - GLBL_ERR_STAT_ERR_DSC_MASK, - &eqdma_cpm5_hw_desc_err_process - }, - { - EQDMA_CPM5_DSC_ERR_PARAM, - "Parameter mismatch error", - EQDMA_CPM5_GLBL_DSC_ERR_MSK_ADDR, - EQDMA_CPM5_GLBL_DSC_ERR_STS_ADDR, - GLBL_DSC_ERR_STS_PARAM_MASK, - GLBL_ERR_STAT_ERR_DSC_MASK, - &eqdma_cpm5_hw_desc_err_process - }, - { - EQDMA_CPM5_DSC_ERR_ADDR, - "Address mismatch error", - EQDMA_CPM5_GLBL_DSC_ERR_MSK_ADDR, - EQDMA_CPM5_GLBL_DSC_ERR_STS_ADDR, - GLBL_DSC_ERR_STS_ADDR_MASK, - GLBL_ERR_STAT_ERR_DSC_MASK, - &eqdma_cpm5_hw_desc_err_process - }, - { - EQDMA_CPM5_DSC_ERR_TAG, - "Unexpected tag error", - EQDMA_CPM5_GLBL_DSC_ERR_MSK_ADDR, - EQDMA_CPM5_GLBL_DSC_ERR_STS_ADDR, - GLBL_DSC_ERR_STS_TAG_MASK, - GLBL_ERR_STAT_ERR_DSC_MASK, - &eqdma_cpm5_hw_desc_err_process - }, - { - EQDMA_CPM5_DSC_ERR_FLR, - "FLR error", - EQDMA_CPM5_GLBL_DSC_ERR_MSK_ADDR, - EQDMA_CPM5_GLBL_DSC_ERR_STS_ADDR, - GLBL_DSC_ERR_STS_FLR_MASK, - GLBL_ERR_STAT_ERR_DSC_MASK, - &eqdma_cpm5_hw_desc_err_process - }, - { - EQDMA_CPM5_DSC_ERR_TIMEOUT, - "Timed out error", - EQDMA_CPM5_GLBL_DSC_ERR_MSK_ADDR, - EQDMA_CPM5_GLBL_DSC_ERR_STS_ADDR, - GLBL_DSC_ERR_STS_TIMEOUT_MASK, - GLBL_ERR_STAT_ERR_DSC_MASK, - &eqdma_cpm5_hw_desc_err_process - }, - { - EQDMA_CPM5_DSC_ERR_DAT_POISON, - "Poison data error", - EQDMA_CPM5_GLBL_DSC_ERR_MSK_ADDR, - EQDMA_CPM5_GLBL_DSC_ERR_STS_ADDR, - GLBL_DSC_ERR_STS_DAT_POISON_MASK, - GLBL_ERR_STAT_ERR_DSC_MASK, - &eqdma_cpm5_hw_desc_err_process - }, - { - EQDMA_CPM5_DSC_ERR_FLR_CANCEL, - "Descriptor fetch cancelled due to FLR error", - EQDMA_CPM5_GLBL_DSC_ERR_MSK_ADDR, - EQDMA_CPM5_GLBL_DSC_ERR_STS_ADDR, - GLBL_DSC_ERR_STS_FLR_CANCEL_MASK, - GLBL_ERR_STAT_ERR_DSC_MASK, - &eqdma_cpm5_hw_desc_err_process - }, - { - EQDMA_CPM5_DSC_ERR_DMA, - "DMA engine error", - EQDMA_CPM5_GLBL_DSC_ERR_MSK_ADDR, - EQDMA_CPM5_GLBL_DSC_ERR_STS_ADDR, - GLBL_DSC_ERR_STS_DMA_MASK, - GLBL_ERR_STAT_ERR_DSC_MASK, - &eqdma_cpm5_hw_desc_err_process - }, - { - EQDMA_CPM5_DSC_ERR_DSC, - "Invalid PIDX update error", - EQDMA_CPM5_GLBL_DSC_ERR_MSK_ADDR, - EQDMA_CPM5_GLBL_DSC_ERR_STS_ADDR, - GLBL_DSC_ERR_STS_DSC_MASK, - GLBL_ERR_STAT_ERR_DSC_MASK, - &eqdma_cpm5_hw_desc_err_process - }, - { - EQDMA_CPM5_DSC_ERR_RQ_CANCEL, - "Descriptor fetch cancelled due to disable register status error", - EQDMA_CPM5_GLBL_DSC_ERR_MSK_ADDR, - EQDMA_CPM5_GLBL_DSC_ERR_STS_ADDR, - GLBL_DSC_ERR_STS_RQ_CANCEL_MASK, - GLBL_ERR_STAT_ERR_DSC_MASK, - &eqdma_cpm5_hw_desc_err_process - }, - { - EQDMA_CPM5_DSC_ERR_DBE, - "UNC_ERR_RAM_DBE error", - EQDMA_CPM5_GLBL_DSC_ERR_MSK_ADDR, - EQDMA_CPM5_GLBL_DSC_ERR_STS_ADDR, - GLBL_DSC_ERR_STS_DBE_MASK, - GLBL_ERR_STAT_ERR_DSC_MASK, - &eqdma_cpm5_hw_desc_err_process - }, - { - EQDMA_CPM5_DSC_ERR_SBE, - "UNC_ERR_RAM_SBE error", - EQDMA_CPM5_GLBL_DSC_ERR_MSK_ADDR, - EQDMA_CPM5_GLBL_DSC_ERR_STS_ADDR, - GLBL_DSC_ERR_STS_SBE_MASK, - GLBL_ERR_STAT_ERR_DSC_MASK, - &eqdma_cpm5_hw_desc_err_process - }, - { - EQDMA_CPM5_DSC_ERR_PORT_ID, - "Port ID Error", - EQDMA_CPM5_GLBL_DSC_ERR_MSK_ADDR, - EQDMA_CPM5_GLBL_DSC_ERR_STS_ADDR, - GLBL_DSC_ERR_STS_PORT_ID_MASK, - GLBL_ERR_STAT_ERR_DSC_MASK, - &eqdma_cpm5_hw_desc_err_process - }, - { - EQDMA_CPM5_DSC_ERR_ALL, - "All Descriptor errors", - EQDMA_CPM5_GLBL_DSC_ERR_MSK_ADDR, - EQDMA_CPM5_GLBL_DSC_ERR_STS_ADDR, - EQDMA_CPM5_GLBL_DSC_ERR_ALL_MASK, - GLBL_ERR_STAT_ERR_DSC_MASK, - &eqdma_cpm5_hw_desc_err_process - }, - - /* TRQ errors */ - { - EQDMA_CPM5_TRQ_ERR_CSR_UNMAPPED, - "Access targeted unmapped register space via CSR pathway error", - EQDMA_CPM5_GLBL_TRQ_ERR_MSK_ADDR, - EQDMA_CPM5_GLBL_TRQ_ERR_STS_ADDR, - GLBL_TRQ_ERR_STS_CSR_UNMAPPED_MASK, - GLBL_ERR_STAT_ERR_TRQ_MASK, - &eqdma_cpm5_hw_trq_err_process - }, - { - EQDMA_CPM5_TRQ_ERR_VF_ACCESS, - "VF attempted to access Global register space or Function map", - EQDMA_CPM5_GLBL_TRQ_ERR_MSK_ADDR, - EQDMA_CPM5_GLBL_TRQ_ERR_STS_ADDR, - GLBL_TRQ_ERR_STS_VF_ACCESS_ERR_MASK, - GLBL_ERR_STAT_ERR_TRQ_MASK, - &eqdma_cpm5_hw_trq_err_process - }, - { - EQDMA_CPM5_TRQ_ERR_TCP_CSR_TIMEOUT, - "Timeout on request to dma internal csr register", - EQDMA_CPM5_GLBL_TRQ_ERR_MSK_ADDR, - EQDMA_CPM5_GLBL_TRQ_ERR_STS_ADDR, - GLBL_TRQ_ERR_STS_TCP_CSR_TIMEOUT_MASK, - GLBL_ERR_STAT_ERR_TRQ_MASK, - &eqdma_cpm5_hw_trq_err_process - }, - { - EQDMA_CPM5_TRQ_ERR_QSPC_UNMAPPED, - "Access targeted unmapped register via queue space pathway", - EQDMA_CPM5_GLBL_TRQ_ERR_MSK_ADDR, - EQDMA_CPM5_GLBL_TRQ_ERR_STS_ADDR, - GLBL_TRQ_ERR_STS_QSPC_UNMAPPED_MASK, - GLBL_ERR_STAT_ERR_TRQ_MASK, - &eqdma_cpm5_hw_trq_err_process - }, - { - EQDMA_CPM5_TRQ_ERR_QID_RANGE, - "Qid range error", - EQDMA_CPM5_GLBL_TRQ_ERR_MSK_ADDR, - EQDMA_CPM5_GLBL_TRQ_ERR_STS_ADDR, - GLBL_TRQ_ERR_STS_QID_RANGE_MASK, - GLBL_ERR_STAT_ERR_TRQ_MASK, - &eqdma_cpm5_hw_trq_err_process - }, - { - EQDMA_CPM5_TRQ_ERR_TCP_QSPC_TIMEOUT, - "Timeout on request to dma internal queue space register", - EQDMA_CPM5_GLBL_TRQ_ERR_MSK_ADDR, - EQDMA_CPM5_GLBL_TRQ_ERR_STS_ADDR, - GLBL_TRQ_ERR_STS_TCP_QSPC_TIMEOUT_MASK, - GLBL_ERR_STAT_ERR_TRQ_MASK, - &eqdma_cpm5_hw_trq_err_process - }, - { - EQDMA_CPM5_TRQ_ERR_ALL, - "All TRQ errors", - EQDMA_CPM5_GLBL_TRQ_ERR_MSK_ADDR, - EQDMA_CPM5_GLBL_TRQ_ERR_STS_ADDR, - EQDMA_CPM5_GLBL_TRQ_ERR_ALL_MASK, - GLBL_ERR_STAT_ERR_TRQ_MASK, - &eqdma_cpm5_hw_trq_err_process - }, - - /* C2H Errors*/ - { - EQDMA_CPM5_ST_C2H_ERR_MTY_MISMATCH, - "MTY mismatch error", - EQDMA_CPM5_C2H_ERR_MASK_ADDR, - EQDMA_CPM5_C2H_ERR_STAT_ADDR, - C2H_ERR_STAT_MTY_MISMATCH_MASK, - GLBL_ERR_STAT_ERR_C2H_ST_MASK, - &eqdma_cpm5_hw_st_c2h_err_process - }, - { - EQDMA_CPM5_ST_C2H_ERR_LEN_MISMATCH, - "Packet length mismatch error", - EQDMA_CPM5_C2H_ERR_MASK_ADDR, - EQDMA_CPM5_C2H_ERR_STAT_ADDR, - C2H_ERR_STAT_LEN_MISMATCH_MASK, - GLBL_ERR_STAT_ERR_C2H_ST_MASK, - &eqdma_cpm5_hw_st_c2h_err_process - }, - { - EQDMA_CPM5_ST_C2H_ERR_SH_CMPT_DSC, - "A Shared CMPT queue has encountered a descriptor error", - EQDMA_CPM5_C2H_ERR_MASK_ADDR, - EQDMA_CPM5_C2H_ERR_STAT_ADDR, - C2H_ERR_STAT_SH_CMPT_DSC_ERR_MASK, - GLBL_ERR_STAT_ERR_C2H_ST_MASK, - &eqdma_cpm5_hw_st_c2h_err_process - }, - { - EQDMA_CPM5_ST_C2H_ERR_QID_MISMATCH, - "Qid mismatch error", - EQDMA_CPM5_C2H_ERR_MASK_ADDR, - EQDMA_CPM5_C2H_ERR_STAT_ADDR, - C2H_ERR_STAT_QID_MISMATCH_MASK, - GLBL_ERR_STAT_ERR_C2H_ST_MASK, - &eqdma_cpm5_hw_st_c2h_err_process - }, - { - EQDMA_CPM5_ST_C2H_ERR_DESC_RSP_ERR, - "Descriptor error bit set", - EQDMA_CPM5_C2H_ERR_MASK_ADDR, - EQDMA_CPM5_C2H_ERR_STAT_ADDR, - C2H_ERR_STAT_DESC_RSP_ERR_MASK, - GLBL_ERR_STAT_ERR_C2H_ST_MASK, - &eqdma_cpm5_hw_st_c2h_err_process - }, - { - EQDMA_CPM5_ST_C2H_ERR_ENG_WPL_DATA_PAR_ERR, - "Data parity error", - EQDMA_CPM5_C2H_ERR_MASK_ADDR, - EQDMA_CPM5_C2H_ERR_STAT_ADDR, - C2H_ERR_STAT_ENG_WPL_DATA_PAR_ERR_MASK, - GLBL_ERR_STAT_ERR_C2H_ST_MASK, - &eqdma_cpm5_hw_st_c2h_err_process - }, - { - EQDMA_CPM5_ST_C2H_ERR_MSI_INT_FAIL, - "MSI got a fail response error", - EQDMA_CPM5_C2H_ERR_MASK_ADDR, - EQDMA_CPM5_C2H_ERR_STAT_ADDR, - C2H_ERR_STAT_MSI_INT_FAIL_MASK, - GLBL_ERR_STAT_ERR_C2H_ST_MASK, - &eqdma_cpm5_hw_st_c2h_err_process - }, - { - EQDMA_CPM5_ST_C2H_ERR_ERR_DESC_CNT, - "Descriptor count error", - EQDMA_CPM5_C2H_ERR_MASK_ADDR, - EQDMA_CPM5_C2H_ERR_STAT_ADDR, - C2H_ERR_STAT_ERR_DESC_CNT_MASK, - GLBL_ERR_STAT_ERR_C2H_ST_MASK, - &eqdma_cpm5_hw_st_c2h_err_process - }, - { - EQDMA_CPM5_ST_C2H_ERR_PORTID_CTXT_MISMATCH, - "Port id in packet and pfetch ctxt mismatch error", - EQDMA_CPM5_C2H_ERR_MASK_ADDR, - EQDMA_CPM5_C2H_ERR_STAT_ADDR, - C2H_ERR_STAT_PORT_ID_CTXT_MISMATCH_MASK, - GLBL_ERR_STAT_ERR_C2H_ST_MASK, - &eqdma_cpm5_hw_st_c2h_err_process - }, - { - EQDMA_CPM5_ST_C2H_ERR_CMPT_INV_Q_ERR, - "Writeback on invalid queue error", - EQDMA_CPM5_C2H_ERR_MASK_ADDR, - EQDMA_CPM5_C2H_ERR_STAT_ADDR, - C2H_ERR_STAT_WRB_INV_Q_ERR_MASK, - GLBL_ERR_STAT_ERR_C2H_ST_MASK, - &eqdma_cpm5_hw_st_c2h_err_process - }, - { - EQDMA_CPM5_ST_C2H_ERR_CMPT_QFULL_ERR, - "Completion queue gets full error", - EQDMA_CPM5_C2H_ERR_MASK_ADDR, - EQDMA_CPM5_C2H_ERR_STAT_ADDR, - C2H_ERR_STAT_WRB_QFULL_ERR_MASK, - GLBL_ERR_STAT_ERR_C2H_ST_MASK, - &eqdma_cpm5_hw_st_c2h_err_process - }, - { - EQDMA_CPM5_ST_C2H_ERR_CMPT_CIDX_ERR, - "Bad CIDX update by the software error", - EQDMA_CPM5_C2H_ERR_MASK_ADDR, - EQDMA_CPM5_C2H_ERR_STAT_ADDR, - C2H_ERR_STAT_WRB_CIDX_ERR_MASK, - GLBL_ERR_STAT_ERR_C2H_ST_MASK, - &eqdma_cpm5_hw_st_c2h_err_process - }, - { - EQDMA_CPM5_ST_C2H_ERR_CMPT_PRTY_ERR, - "C2H completion Parity error", - EQDMA_CPM5_C2H_ERR_MASK_ADDR, - EQDMA_CPM5_C2H_ERR_STAT_ADDR, - C2H_ERR_STAT_WRB_PRTY_ERR_MASK, - GLBL_ERR_STAT_ERR_C2H_ST_MASK, - &eqdma_cpm5_hw_st_c2h_err_process - }, - { - EQDMA_CPM5_ST_C2H_ERR_AVL_RING_DSC, - "Available ring fetch returns descriptor with error", - EQDMA_CPM5_C2H_ERR_MASK_ADDR, - EQDMA_CPM5_C2H_ERR_STAT_ADDR, - C2H_ERR_STAT_AVL_RING_DSC_ERR_MASK, - GLBL_ERR_STAT_ERR_C2H_ST_MASK, - &eqdma_cpm5_hw_st_c2h_err_process - }, - { - EQDMA_CPM5_ST_C2H_ERR_HDR_ECC_UNC, - "multi-bit ecc error on c2h packet header", - EQDMA_CPM5_C2H_ERR_MASK_ADDR, - EQDMA_CPM5_C2H_ERR_STAT_ADDR, - C2H_ERR_STAT_HDR_ECC_UNC_ERR_MASK, - GLBL_ERR_STAT_ERR_C2H_ST_MASK, - &eqdma_cpm5_hw_st_c2h_err_process - }, - { - EQDMA_CPM5_ST_C2H_ERR_HDR_ECC_COR, - "single-bit ecc error on c2h packet header", - EQDMA_CPM5_C2H_ERR_MASK_ADDR, - EQDMA_CPM5_C2H_ERR_STAT_ADDR, - C2H_ERR_STAT_HDR_ECC_COR_ERR_MASK, - GLBL_ERR_STAT_ERR_C2H_ST_MASK, - &eqdma_cpm5_hw_st_c2h_err_process - }, - { - EQDMA_CPM5_ST_C2H_ERR_WRB_PORT_ID_ERR, - "Port ID error", - EQDMA_CPM5_C2H_ERR_MASK_ADDR, - EQDMA_CPM5_C2H_ERR_STAT_ADDR, - C2H_ERR_STAT_WRB_PORT_ID_ERR_MASK, - GLBL_ERR_STAT_ERR_C2H_ST_MASK, - &eqdma_cpm5_hw_st_c2h_err_process - }, - { - EQDMA_CPM5_ST_C2H_ERR_ALL, - "All C2h errors", - EQDMA_CPM5_C2H_ERR_MASK_ADDR, - EQDMA_CPM5_C2H_ERR_STAT_ADDR, - EQDMA_CPM5_C2H_ERR_ALL_MASK, - GLBL_ERR_STAT_ERR_C2H_ST_MASK, - &eqdma_cpm5_hw_st_c2h_err_process - }, - - /* C2H fatal errors */ - { - EQDMA_CPM5_ST_FATAL_ERR_MTY_MISMATCH, - "Fatal MTY mismatch error", - EQDMA_CPM5_C2H_FATAL_ERR_MASK_ADDR, - EQDMA_CPM5_C2H_FATAL_ERR_STAT_ADDR, - C2H_FATAL_ERR_STAT_MTY_MISMATCH_MASK, - GLBL_ERR_STAT_ERR_C2H_ST_MASK, - &eqdma_cpm5_hw_st_c2h_err_process - }, - { - EQDMA_CPM5_ST_FATAL_ERR_LEN_MISMATCH, - "Fatal Len mismatch error", - EQDMA_CPM5_C2H_FATAL_ERR_MASK_ADDR, - EQDMA_CPM5_C2H_FATAL_ERR_STAT_ADDR, - C2H_FATAL_ERR_STAT_LEN_MISMATCH_MASK, - GLBL_ERR_STAT_ERR_C2H_ST_MASK, - &eqdma_cpm5_hw_st_c2h_err_process - }, - { - EQDMA_CPM5_ST_FATAL_ERR_QID_MISMATCH, - "Fatal Qid mismatch error", - EQDMA_CPM5_C2H_FATAL_ERR_MASK_ADDR, - EQDMA_CPM5_C2H_FATAL_ERR_STAT_ADDR, - C2H_FATAL_ERR_STAT_QID_MISMATCH_MASK, - GLBL_ERR_STAT_ERR_C2H_ST_MASK, - &eqdma_cpm5_hw_st_c2h_err_process - }, - { - EQDMA_CPM5_ST_FATAL_ERR_TIMER_FIFO_RAM_RDBE, - "RAM double bit fatal error", - EQDMA_CPM5_C2H_FATAL_ERR_MASK_ADDR, - EQDMA_CPM5_C2H_FATAL_ERR_STAT_ADDR, - C2H_FATAL_ERR_STAT_TIMER_FIFO_RAM_RDBE_MASK, - GLBL_ERR_STAT_ERR_C2H_ST_MASK, - &eqdma_cpm5_hw_st_c2h_err_process - }, - { - EQDMA_CPM5_ST_FATAL_ERR_PFCH_II_RAM_RDBE, - "RAM double bit fatal error", - EQDMA_CPM5_C2H_FATAL_ERR_MASK_ADDR, - EQDMA_CPM5_C2H_FATAL_ERR_STAT_ADDR, - C2H_FATAL_ERR_STAT_PFCH_LL_RAM_RDBE_MASK, - GLBL_ERR_STAT_ERR_C2H_ST_MASK, - &eqdma_cpm5_hw_st_c2h_err_process - }, - { - EQDMA_CPM5_ST_FATAL_ERR_CMPT_CTXT_RAM_RDBE, - "RAM double bit fatal error", - EQDMA_CPM5_C2H_FATAL_ERR_MASK_ADDR, - EQDMA_CPM5_C2H_FATAL_ERR_STAT_ADDR, - C2H_FATAL_ERR_STAT_WRB_CTXT_RAM_RDBE_MASK, - GLBL_ERR_STAT_ERR_C2H_ST_MASK, - &eqdma_cpm5_hw_st_c2h_err_process - }, - { - EQDMA_CPM5_ST_FATAL_ERR_PFCH_CTXT_RAM_RDBE, - "RAM double bit fatal error", - EQDMA_CPM5_C2H_FATAL_ERR_MASK_ADDR, - EQDMA_CPM5_C2H_FATAL_ERR_STAT_ADDR, - C2H_FATAL_ERR_STAT_PFCH_CTXT_RAM_RDBE_MASK, - GLBL_ERR_STAT_ERR_C2H_ST_MASK, - &eqdma_cpm5_hw_st_c2h_err_process - }, - { - EQDMA_CPM5_ST_FATAL_ERR_DESC_REQ_FIFO_RAM_RDBE, - "RAM double bit fatal error", - EQDMA_CPM5_C2H_FATAL_ERR_MASK_ADDR, - EQDMA_CPM5_C2H_FATAL_ERR_STAT_ADDR, - C2H_FATAL_ERR_STAT_DESC_REQ_FIFO_RAM_RDBE_MASK, - GLBL_ERR_STAT_ERR_C2H_ST_MASK, - &eqdma_cpm5_hw_st_c2h_err_process - }, - { - EQDMA_CPM5_ST_FATAL_ERR_INT_CTXT_RAM_RDBE, - "RAM double bit fatal error", - EQDMA_CPM5_C2H_FATAL_ERR_MASK_ADDR, - EQDMA_CPM5_C2H_FATAL_ERR_STAT_ADDR, - C2H_FATAL_ERR_STAT_INT_CTXT_RAM_RDBE_MASK, - GLBL_ERR_STAT_ERR_C2H_ST_MASK, - &eqdma_cpm5_hw_st_c2h_err_process - }, - { - EQDMA_CPM5_ST_FATAL_ERR_CMPT_COAL_DATA_RAM_RDBE, - "RAM double bit fatal error", - EQDMA_CPM5_C2H_FATAL_ERR_MASK_ADDR, - EQDMA_CPM5_C2H_FATAL_ERR_STAT_ADDR, - C2H_FATAL_ERR_STAT_WRB_COAL_DATA_RAM_RDBE_MASK, - GLBL_ERR_STAT_ERR_C2H_ST_MASK, - &eqdma_cpm5_hw_st_c2h_err_process - }, - { - EQDMA_CPM5_ST_FATAL_ERR_CMPT_FIFO_RAM_RDBE, - "RAM double bit fatal error", - EQDMA_CPM5_C2H_FATAL_ERR_MASK_ADDR, - EQDMA_CPM5_C2H_FATAL_ERR_STAT_ADDR, - C2H_FATAL_ERR_STAT_CMPT_FIFO_RAM_RDBE_MASK, - GLBL_ERR_STAT_ERR_C2H_ST_MASK, - &eqdma_cpm5_hw_st_c2h_err_process - }, - { - EQDMA_CPM5_ST_FATAL_ERR_QID_FIFO_RAM_RDBE, - "RAM double bit fatal error", - EQDMA_CPM5_C2H_FATAL_ERR_MASK_ADDR, - EQDMA_CPM5_C2H_FATAL_ERR_STAT_ADDR, - C2H_FATAL_ERR_STAT_QID_FIFO_RAM_RDBE_MASK, - GLBL_ERR_STAT_ERR_C2H_ST_MASK, - &eqdma_cpm5_hw_st_c2h_err_process - }, - { - EQDMA_CPM5_ST_FATAL_ERR_PAYLOAD_FIFO_RAM_RDBE, - "RAM double bit fatal error", - EQDMA_CPM5_C2H_FATAL_ERR_MASK_ADDR, - EQDMA_CPM5_C2H_FATAL_ERR_STAT_ADDR, - C2H_FATAL_ERR_STAT_PLD_FIFO_RAM_RDBE_MASK, - GLBL_ERR_STAT_ERR_C2H_ST_MASK, - &eqdma_cpm5_hw_st_c2h_err_process - }, - { - EQDMA_CPM5_ST_FATAL_ERR_WPL_DATA_PAR, - "RAM double bit fatal error", - EQDMA_CPM5_C2H_FATAL_ERR_MASK_ADDR, - EQDMA_CPM5_C2H_FATAL_ERR_STAT_ADDR, - C2H_FATAL_ERR_STAT_WPL_DATA_PAR_ERR_MASK, - GLBL_ERR_STAT_ERR_C2H_ST_MASK, - &eqdma_cpm5_hw_st_c2h_err_process - }, - { - EQDMA_CPM5_ST_FATAL_ERR_AVL_RING_FIFO_RAM_RDBE, - "RAM double bit fatal error", - EQDMA_CPM5_C2H_FATAL_ERR_MASK_ADDR, - EQDMA_CPM5_C2H_FATAL_ERR_STAT_ADDR, - C2H_FATAL_ERR_STAT_AVL_RING_FIFO_RAM_RDBE_MASK, - GLBL_ERR_STAT_ERR_C2H_ST_MASK, - &eqdma_cpm5_hw_st_c2h_err_process - }, - { - EQDMA_CPM5_ST_FATAL_ERR_HDR_ECC_UNC, - "RAM double bit fatal error", - EQDMA_CPM5_C2H_FATAL_ERR_MASK_ADDR, - EQDMA_CPM5_C2H_FATAL_ERR_STAT_ADDR, - C2H_FATAL_ERR_STAT_HDR_ECC_UNC_ERR_MASK, - GLBL_ERR_STAT_ERR_C2H_ST_MASK, - &eqdma_cpm5_hw_st_c2h_err_process - }, - { - EQDMA_CPM5_ST_FATAL_ERR_ALL, - "All fatal errors", - EQDMA_CPM5_C2H_FATAL_ERR_MASK_ADDR, - EQDMA_CPM5_C2H_FATAL_ERR_STAT_ADDR, - EQDMA_CPM5_C2H_FATAL_ERR_ALL_MASK, - GLBL_ERR_STAT_ERR_C2H_ST_MASK, - &eqdma_cpm5_hw_st_c2h_err_process - }, - - /* H2C St errors */ - { - EQDMA_CPM5_ST_H2C_ERR_ZERO_LEN_DESC, - "Zero length descriptor error", - EQDMA_CPM5_H2C_ERR_MASK_ADDR, - EQDMA_CPM5_H2C_ERR_STAT_ADDR, - H2C_ERR_STAT_ZERO_LEN_DS_MASK, - GLBL_ERR_STAT_ERR_H2C_ST_MASK, - &eqdma_cpm5_hw_st_h2c_err_process - }, - { - EQDMA_CPM5_ST_H2C_ERR_SDI_MRKR_REQ_MOP, - "A non-EOP descriptor received", - EQDMA_CPM5_H2C_ERR_MASK_ADDR, - EQDMA_CPM5_H2C_ERR_STAT_ADDR, - H2C_ERR_STAT_SDI_MRKR_REQ_MOP_ERR_MASK, - GLBL_ERR_STAT_ERR_H2C_ST_MASK, - &eqdma_cpm5_hw_st_h2c_err_process - }, - { - EQDMA_CPM5_ST_H2C_ERR_NO_DMA_DSC, - "No DMA descriptor received error", - EQDMA_CPM5_H2C_ERR_MASK_ADDR, - EQDMA_CPM5_H2C_ERR_STAT_ADDR, - H2C_ERR_STAT_NO_DMA_DS_MASK, - GLBL_ERR_STAT_ERR_H2C_ST_MASK, - &eqdma_cpm5_hw_st_h2c_err_process - }, - { - EQDMA_CPM5_ST_H2C_ERR_SBE, - "Single bit error detected on H2C-ST data error", - EQDMA_CPM5_H2C_ERR_MASK_ADDR, - EQDMA_CPM5_H2C_ERR_STAT_ADDR, - H2C_ERR_STAT_SBE_MASK, - GLBL_ERR_STAT_ERR_H2C_ST_MASK, - &eqdma_cpm5_hw_st_h2c_err_process - }, - { - EQDMA_CPM5_ST_H2C_ERR_DBE, - "Double bit error detected on H2C-ST data error", - EQDMA_CPM5_H2C_ERR_MASK_ADDR, - EQDMA_CPM5_H2C_ERR_STAT_ADDR, - H2C_ERR_STAT_DBE_MASK, - GLBL_ERR_STAT_ERR_H2C_ST_MASK, - &eqdma_cpm5_hw_st_h2c_err_process - }, - { - EQDMA_CPM5_ST_H2C_ERR_PAR, - "Internal data parity error", - EQDMA_CPM5_H2C_ERR_MASK_ADDR, - EQDMA_CPM5_H2C_ERR_STAT_ADDR, - H2C_ERR_STAT_PAR_ERR_MASK, - GLBL_ERR_STAT_ERR_H2C_ST_MASK, - &eqdma_cpm5_hw_st_h2c_err_process - }, - { - EQDMA_CPM5_ST_H2C_ERR_ALL, - "All H2C errors", - EQDMA_CPM5_H2C_ERR_MASK_ADDR, - EQDMA_CPM5_H2C_ERR_STAT_ADDR, - EQDMA_CPM5_H2C_ERR_ALL_MASK, - GLBL_ERR_STAT_ERR_H2C_ST_MASK, - &eqdma_cpm5_hw_st_h2c_err_process - }, - - /* SBE errors */ - { - EQDMA_CPM5_SBE_1_ERR_RC_RRQ_EVEN_RAM, - "RC RRQ Even RAM single bit ECC error.", - EQDMA_CPM5_RAM_SBE_MSK_1_A_ADDR, - EQDMA_CPM5_RAM_SBE_STS_1_A_ADDR, - RAM_SBE_STS_1_A_RC_RRQ_EVEN_RAM_MASK, - GLBL_ERR_STAT_ERR_RAM_SBE_MASK, - &eqdma_cpm5_hw_ram_sbe_err_process - }, - { - EQDMA_CPM5_SBE_1_ERR_TAG_ODD_RAM, - "Tag Odd Ram single bit ECC error.", - EQDMA_CPM5_RAM_SBE_MSK_1_A_ADDR, - EQDMA_CPM5_RAM_SBE_STS_1_A_ADDR, - RAM_SBE_STS_1_A_TAG_ODD_RAM_MASK, - GLBL_ERR_STAT_ERR_RAM_SBE_MASK, - &eqdma_cpm5_hw_ram_sbe_err_process - }, - { - EQDMA_CPM5_SBE_1_ERR_TAG_EVEN_RAM, - "Tag Even Ram single bit ECC error.", - EQDMA_CPM5_RAM_SBE_MSK_1_A_ADDR, - EQDMA_CPM5_RAM_SBE_STS_1_A_ADDR, - RAM_SBE_STS_1_A_TAG_EVEN_RAM_MASK, - GLBL_ERR_STAT_ERR_RAM_SBE_MASK, - &eqdma_cpm5_hw_ram_sbe_err_process - }, - { - EQDMA_CPM5_SBE_1_ERR_PFCH_CTXT_CAM_RAM_0, - "Pfch Ctxt CAM RAM 0 single bit ECC error.", - EQDMA_CPM5_RAM_SBE_MSK_1_A_ADDR, - EQDMA_CPM5_RAM_SBE_STS_1_A_ADDR, - RAM_SBE_STS_1_A_PFCH_CTXT_CAM_RAM_0_MASK, - GLBL_ERR_STAT_ERR_RAM_SBE_MASK, - &eqdma_cpm5_hw_ram_sbe_err_process - }, - { - EQDMA_CPM5_SBE_1_ERR_PFCH_CTXT_CAM_RAM_1, - "Pfch Ctxt CAM RAM 1 single bit ECC error.", - EQDMA_CPM5_RAM_SBE_MSK_1_A_ADDR, - EQDMA_CPM5_RAM_SBE_STS_1_A_ADDR, - RAM_SBE_STS_1_A_PFCH_CTXT_CAM_RAM_1_MASK, - GLBL_ERR_STAT_ERR_RAM_SBE_MASK, - &eqdma_cpm5_hw_ram_sbe_err_process - }, - { - EQDMA_CPM5_SBE_1_ERR_ALL, - "All SBE Errors.", - EQDMA_CPM5_RAM_SBE_MSK_1_A_ADDR, - EQDMA_CPM5_RAM_SBE_STS_1_A_ADDR, - EQDMA_CPM5_SBE_ERR_ALL_MASK, - GLBL_ERR_STAT_ERR_RAM_SBE_MASK, - &eqdma_cpm5_hw_ram_sbe_err_process - }, - { - EQDMA_CPM5_SBE_ERR_MI_H2C0_DAT, - "H2C MM data buffer single bit ECC error", - EQDMA_CPM5_RAM_SBE_MSK_A_ADDR, - EQDMA_CPM5_RAM_SBE_STS_A_ADDR, - RAM_SBE_STS_A_MI_H2C0_DAT_MASK, - GLBL_ERR_STAT_ERR_RAM_SBE_MASK, - &eqdma_cpm5_hw_ram_sbe_err_process - }, - { - EQDMA_CPM5_SBE_ERR_MI_H2C1_DAT, - "H2C MM data buffer single bit ECC error", - EQDMA_CPM5_RAM_SBE_MSK_A_ADDR, - EQDMA_CPM5_RAM_SBE_STS_A_ADDR, - RAM_SBE_STS_A_MI_H2C1_DAT_MASK, - GLBL_ERR_STAT_ERR_RAM_SBE_MASK, - &eqdma_cpm5_hw_ram_sbe_err_process - }, - { - EQDMA_CPM5_SBE_ERR_MI_H2C2_DAT, - "H2C MM data buffer single bit ECC error", - EQDMA_CPM5_RAM_SBE_MSK_A_ADDR, - EQDMA_CPM5_RAM_SBE_STS_A_ADDR, - RAM_SBE_STS_A_MI_H2C2_DAT_MASK, - GLBL_ERR_STAT_ERR_RAM_SBE_MASK, - &eqdma_cpm5_hw_ram_sbe_err_process - }, - { - EQDMA_CPM5_SBE_ERR_MI_H2C3_DAT, - "H2C MM data buffer single bit ECC error", - EQDMA_CPM5_RAM_SBE_MSK_A_ADDR, - EQDMA_CPM5_RAM_SBE_STS_A_ADDR, - RAM_SBE_STS_A_MI_H2C3_DAT_MASK, - GLBL_ERR_STAT_ERR_RAM_SBE_MASK, - &eqdma_cpm5_hw_ram_sbe_err_process - }, - { - EQDMA_CPM5_SBE_ERR_MI_C2H0_DAT, - "C2H MM data buffer single bit ECC error", - EQDMA_CPM5_RAM_SBE_MSK_A_ADDR, - EQDMA_CPM5_RAM_SBE_STS_A_ADDR, - RAM_SBE_STS_A_MI_C2H0_DAT_MASK, - GLBL_ERR_STAT_ERR_RAM_SBE_MASK, - &eqdma_cpm5_hw_ram_sbe_err_process - }, - { - EQDMA_CPM5_SBE_ERR_MI_C2H1_DAT, - "C2H MM data buffer single bit ECC error", - EQDMA_CPM5_RAM_SBE_MSK_A_ADDR, - EQDMA_CPM5_RAM_SBE_STS_A_ADDR, - RAM_SBE_STS_A_MI_C2H1_DAT_MASK, - GLBL_ERR_STAT_ERR_RAM_SBE_MASK, - &eqdma_cpm5_hw_ram_sbe_err_process - }, -{ - EQDMA_CPM5_SBE_ERR_MI_C2H2_DAT, - "C2H MM data buffer single bit ECC error", - EQDMA_CPM5_RAM_SBE_MSK_A_ADDR, - EQDMA_CPM5_RAM_SBE_STS_A_ADDR, - RAM_SBE_STS_A_MI_C2H2_DAT_MASK, - GLBL_ERR_STAT_ERR_RAM_SBE_MASK, - &eqdma_cpm5_hw_ram_sbe_err_process - }, - { - EQDMA_CPM5_SBE_ERR_MI_C2H3_DAT, - "C2H MM data buffer single bit ECC error", - EQDMA_CPM5_RAM_SBE_MSK_A_ADDR, - EQDMA_CPM5_RAM_SBE_STS_A_ADDR, - RAM_SBE_STS_A_MI_C2H3_DAT_MASK, - GLBL_ERR_STAT_ERR_RAM_SBE_MASK, - &eqdma_cpm5_hw_ram_sbe_err_process - }, - { - EQDMA_CPM5_SBE_ERR_H2C_RD_BRG_DAT, - "Bridge master read single bit ECC error", - EQDMA_CPM5_RAM_SBE_MSK_A_ADDR, - EQDMA_CPM5_RAM_SBE_STS_A_ADDR, - RAM_SBE_STS_A_H2C_RD_BRG_DAT_MASK, - GLBL_ERR_STAT_ERR_RAM_SBE_MASK, - &eqdma_cpm5_hw_ram_sbe_err_process - }, - { - EQDMA_CPM5_SBE_ERR_H2C_WR_BRG_DAT, - "Bridge master write single bit ECC error", - EQDMA_CPM5_RAM_SBE_MSK_A_ADDR, - EQDMA_CPM5_RAM_SBE_STS_A_ADDR, - RAM_SBE_STS_A_H2C_WR_BRG_DAT_MASK, - GLBL_ERR_STAT_ERR_RAM_SBE_MASK, - &eqdma_cpm5_hw_ram_sbe_err_process - }, - { - EQDMA_CPM5_SBE_ERR_C2H_RD_BRG_DAT, - "Bridge slave read data buffer single bit ECC error", - EQDMA_CPM5_RAM_SBE_MSK_A_ADDR, - EQDMA_CPM5_RAM_SBE_STS_A_ADDR, - RAM_SBE_STS_A_C2H_RD_BRG_DAT_MASK, - GLBL_ERR_STAT_ERR_RAM_SBE_MASK, - &eqdma_cpm5_hw_ram_sbe_err_process - }, - { - EQDMA_CPM5_SBE_ERR_C2H_WR_BRG_DAT, - "Bridge slave write data buffer single bit ECC error", - EQDMA_CPM5_RAM_SBE_MSK_A_ADDR, - EQDMA_CPM5_RAM_SBE_STS_A_ADDR, - RAM_SBE_STS_A_C2H_WR_BRG_DAT_MASK, - GLBL_ERR_STAT_ERR_RAM_SBE_MASK, - &eqdma_cpm5_hw_ram_sbe_err_process - }, - { - EQDMA_CPM5_SBE_ERR_FUNC_MAP, - "Function map RAM single bit ECC error", - EQDMA_CPM5_RAM_SBE_MSK_A_ADDR, - EQDMA_CPM5_RAM_SBE_STS_A_ADDR, - RAM_SBE_STS_A_FUNC_MAP_MASK, - GLBL_ERR_STAT_ERR_RAM_SBE_MASK, - &eqdma_cpm5_hw_ram_sbe_err_process - }, - { - EQDMA_CPM5_SBE_ERR_DSC_HW_CTXT, - "Descriptor engine hardware context RAM single bit ECC error", - EQDMA_CPM5_RAM_SBE_MSK_A_ADDR, - EQDMA_CPM5_RAM_SBE_STS_A_ADDR, - RAM_SBE_STS_A_DSC_HW_CTXT_MASK, - GLBL_ERR_STAT_ERR_RAM_SBE_MASK, - &eqdma_cpm5_hw_ram_sbe_err_process - }, - { - EQDMA_CPM5_SBE_ERR_DSC_CRD_RCV, - "Descriptor engine receive credit context RAM single bit ECC error", - EQDMA_CPM5_RAM_SBE_MSK_A_ADDR, - EQDMA_CPM5_RAM_SBE_STS_A_ADDR, - RAM_SBE_STS_A_DSC_CRD_RCV_MASK, - GLBL_ERR_STAT_ERR_RAM_SBE_MASK, - &eqdma_cpm5_hw_ram_sbe_err_process - }, - { - EQDMA_CPM5_SBE_ERR_DSC_SW_CTXT, - "Descriptor engine software context RAM single bit ECC error", - EQDMA_CPM5_RAM_SBE_MSK_A_ADDR, - EQDMA_CPM5_RAM_SBE_STS_A_ADDR, - RAM_SBE_STS_A_DSC_SW_CTXT_MASK, - GLBL_ERR_STAT_ERR_RAM_SBE_MASK, - &eqdma_cpm5_hw_ram_sbe_err_process - }, - { - EQDMA_CPM5_SBE_ERR_DSC_CPLI, - "Descriptor engine fetch completion information RAM single bit ECC error", - EQDMA_CPM5_RAM_SBE_MSK_A_ADDR, - EQDMA_CPM5_RAM_SBE_STS_A_ADDR, - RAM_SBE_STS_A_DSC_CPLI_MASK, - GLBL_ERR_STAT_ERR_RAM_SBE_MASK, - &eqdma_cpm5_hw_ram_sbe_err_process - }, - { - EQDMA_CPM5_SBE_ERR_DSC_CPLD, - "Descriptor engine fetch completion data RAM single bit ECC error", - EQDMA_CPM5_RAM_SBE_MSK_A_ADDR, - EQDMA_CPM5_RAM_SBE_STS_A_ADDR, - RAM_SBE_STS_A_DSC_CPLD_MASK, - GLBL_ERR_STAT_ERR_RAM_SBE_MASK, - &eqdma_cpm5_hw_ram_sbe_err_process - }, - { - EQDMA_CPM5_SBE_ERR_MI_TL_SLV_FIFO_RAM, - "TL Slavle FIFO RAM single bit ECC error", - EQDMA_CPM5_RAM_SBE_MSK_A_ADDR, - EQDMA_CPM5_RAM_SBE_STS_A_ADDR, - RAM_SBE_STS_A_MI_TL_SLV_FIFO_RAM_MASK, - GLBL_ERR_STAT_ERR_RAM_SBE_MASK, - &eqdma_cpm5_hw_ram_sbe_err_process - }, - { - EQDMA_CPM5_SBE_ERR_TIMER_FIFO_RAM, - "Timer fifo RAM single bit ECC error", - EQDMA_CPM5_RAM_SBE_MSK_A_ADDR, - EQDMA_CPM5_RAM_SBE_STS_A_ADDR, - RAM_SBE_STS_A_TIMER_FIFO_RAM_MASK, - GLBL_ERR_STAT_ERR_RAM_SBE_MASK, - &eqdma_cpm5_hw_ram_sbe_err_process - }, - { - EQDMA_CPM5_SBE_ERR_QID_FIFO_RAM, - "C2H ST QID FIFO RAM single bit ECC error", - EQDMA_CPM5_RAM_SBE_MSK_A_ADDR, - EQDMA_CPM5_RAM_SBE_STS_A_ADDR, - RAM_SBE_STS_A_QID_FIFO_RAM_MASK, - GLBL_ERR_STAT_ERR_RAM_SBE_MASK, - &eqdma_cpm5_hw_ram_sbe_err_process - }, - { - EQDMA_CPM5_SBE_ERR_WRB_COAL_DATA_RAM, - "Writeback Coalescing RAM single bit ECC error", - EQDMA_CPM5_RAM_SBE_MSK_A_ADDR, - EQDMA_CPM5_RAM_SBE_STS_A_ADDR, - RAM_SBE_STS_A_WRB_COAL_DATA_RAM_MASK, - GLBL_ERR_STAT_ERR_RAM_SBE_MASK, - &eqdma_cpm5_hw_ram_sbe_err_process - }, - { - EQDMA_CPM5_SBE_ERR_INT_CTXT_RAM, - "Interrupt context RAM single bit ECC error", - EQDMA_CPM5_RAM_SBE_MSK_A_ADDR, - EQDMA_CPM5_RAM_SBE_STS_A_ADDR, - RAM_SBE_STS_A_INT_CTXT_RAM_MASK, - GLBL_ERR_STAT_ERR_RAM_SBE_MASK, - &eqdma_cpm5_hw_ram_sbe_err_process - }, - { - EQDMA_CPM5_SBE_ERR_DESC_REQ_FIFO_RAM, - "C2H ST descriptor request RAM single bit ECC error", - EQDMA_CPM5_RAM_SBE_MSK_A_ADDR, - EQDMA_CPM5_RAM_SBE_STS_A_ADDR, - RAM_SBE_STS_A_DESC_REQ_FIFO_RAM_MASK, - GLBL_ERR_STAT_ERR_RAM_SBE_MASK, - &eqdma_cpm5_hw_ram_sbe_err_process - }, - { - EQDMA_CPM5_SBE_ERR_PFCH_CTXT_RAM, - "C2H ST prefetch RAM single bit ECC error", - EQDMA_CPM5_RAM_SBE_MSK_A_ADDR, - EQDMA_CPM5_RAM_SBE_STS_A_ADDR, - RAM_SBE_STS_A_PFCH_CTXT_RAM_MASK, - GLBL_ERR_STAT_ERR_RAM_SBE_MASK, - &eqdma_cpm5_hw_ram_sbe_err_process - }, - { - EQDMA_CPM5_SBE_ERR_WRB_CTXT_RAM, - "C2H ST completion context RAM single bit ECC error", - EQDMA_CPM5_RAM_SBE_MSK_A_ADDR, - EQDMA_CPM5_RAM_SBE_STS_A_ADDR, - RAM_SBE_STS_A_WRB_CTXT_RAM_MASK, - GLBL_ERR_STAT_ERR_RAM_SBE_MASK, - &eqdma_cpm5_hw_ram_sbe_err_process - }, - { - EQDMA_CPM5_SBE_ERR_PFCH_LL_RAM, - "C2H ST prefetch list RAM single bit ECC error", - EQDMA_CPM5_RAM_SBE_MSK_A_ADDR, - EQDMA_CPM5_RAM_SBE_STS_A_ADDR, - RAM_SBE_STS_A_PFCH_LL_RAM_MASK, - GLBL_ERR_STAT_ERR_RAM_SBE_MASK, - &eqdma_cpm5_hw_ram_sbe_err_process - }, - { - EQDMA_CPM5_SBE_ERR_PEND_FIFO_RAM, - "Pend FIFO RAM single bit ECC error", - EQDMA_CPM5_RAM_SBE_MSK_A_ADDR, - EQDMA_CPM5_RAM_SBE_STS_A_ADDR, - RAM_SBE_STS_A_PEND_FIFO_RAM_MASK, - GLBL_ERR_STAT_ERR_RAM_SBE_MASK, - &eqdma_cpm5_hw_ram_sbe_err_process - }, - { - EQDMA_CPM5_SBE_ERR_RC_RRQ_ODD_RAM, - "RC RRQ Odd RAM single bit ECC error.", - EQDMA_CPM5_RAM_SBE_MSK_A_ADDR, - EQDMA_CPM5_RAM_SBE_STS_A_ADDR, - RAM_SBE_STS_A_RC_RRQ_ODD_RAM_MASK, - GLBL_ERR_STAT_ERR_RAM_SBE_MASK, - &eqdma_cpm5_hw_ram_sbe_err_process - }, - { - EQDMA_CPM5_SBE_ERR_ALL, - "All SBE errors", - EQDMA_CPM5_RAM_SBE_MSK_A_ADDR, - EQDMA_CPM5_RAM_SBE_STS_A_ADDR, - EQDMA_CPM5_SBE_ERR_ALL_MASK, - GLBL_ERR_STAT_ERR_RAM_SBE_MASK, - &eqdma_cpm5_hw_ram_sbe_err_process - }, - - - /* DBE errors */ - { - EQDMA_CPM5_DBE_1_ERR_RC_RRQ_EVEN_RAM, - "RC RRQ Odd RAM double bit ECC error.", - EQDMA_CPM5_RAM_DBE_MSK_1_A_ADDR, - EQDMA_CPM5_RAM_DBE_STS_1_A_ADDR, - RAM_DBE_STS_1_A_RC_RRQ_EVEN_RAM_MASK, - GLBL_ERR_STAT_ERR_RAM_DBE_MASK, - &eqdma_cpm5_hw_ram_dbe_err_process - }, - { - EQDMA_CPM5_DBE_1_ERR_TAG_ODD_RAM, - "Tag Odd Ram double bit ECC error.", - EQDMA_CPM5_RAM_DBE_MSK_1_A_ADDR, - EQDMA_CPM5_RAM_DBE_STS_1_A_ADDR, - RAM_DBE_STS_1_A_TAG_ODD_RAM_MASK, - GLBL_ERR_STAT_ERR_RAM_DBE_MASK, - &eqdma_cpm5_hw_ram_dbe_err_process - }, - { - EQDMA_CPM5_DBE_1_ERR_TAG_EVEN_RAM, - "Tag Even Ram double bit ECC error.", - EQDMA_CPM5_RAM_DBE_MSK_1_A_ADDR, - EQDMA_CPM5_RAM_DBE_STS_1_A_ADDR, - RAM_DBE_STS_1_A_TAG_EVEN_RAM_MASK, - GLBL_ERR_STAT_ERR_RAM_DBE_MASK, - &eqdma_cpm5_hw_ram_dbe_err_process - }, - { - EQDMA_CPM5_DBE_1_ERR_PFCH_CTXT_CAM_RAM_0, - "Pfch Ctxt CAM RAM 0 double bit ECC error.", - EQDMA_CPM5_RAM_DBE_MSK_1_A_ADDR, - EQDMA_CPM5_RAM_DBE_STS_1_A_ADDR, - RAM_DBE_STS_1_A_PFCH_CTXT_CAM_RAM_0_MASK, - GLBL_ERR_STAT_ERR_RAM_DBE_MASK, - &eqdma_cpm5_hw_ram_dbe_err_process - }, - { - EQDMA_CPM5_DBE_1_ERR_PFCH_CTXT_CAM_RAM_1, - "Pfch Ctxt CAM RAM double bit ECC error.", - EQDMA_CPM5_RAM_DBE_MSK_1_A_ADDR, - EQDMA_CPM5_RAM_DBE_STS_1_A_ADDR, - RAM_DBE_STS_1_A_PFCH_CTXT_CAM_RAM_0_MASK, - GLBL_ERR_STAT_ERR_RAM_DBE_MASK, - &eqdma_cpm5_hw_ram_dbe_err_process - }, - { - EQDMA_CPM5_DBE_1_ERR_ALL, - "All DBE errors", - EQDMA_CPM5_RAM_DBE_MSK_1_A_ADDR, - EQDMA_CPM5_RAM_DBE_STS_1_A_ADDR, - EQDMA_CPM5_DBE_ERR_ALL_MASK, - GLBL_ERR_STAT_ERR_RAM_DBE_MASK, - &eqdma_cpm5_hw_ram_dbe_err_process - }, - { - EQDMA_CPM5_DBE_ERR_MI_H2C0_DAT, - "H2C MM data buffer double bit ECC error", - EQDMA_CPM5_RAM_DBE_MSK_A_ADDR, - EQDMA_CPM5_RAM_DBE_STS_A_ADDR, - RAM_DBE_STS_A_MI_H2C0_DAT_MASK, - GLBL_ERR_STAT_ERR_RAM_DBE_MASK, - &eqdma_cpm5_hw_ram_dbe_err_process - }, - { - EQDMA_CPM5_DBE_ERR_MI_H2C1_DAT, - "H2C MM data buffer double bit ECC error", - EQDMA_CPM5_RAM_DBE_MSK_A_ADDR, - EQDMA_CPM5_RAM_DBE_STS_A_ADDR, - RAM_DBE_STS_A_MI_H2C1_DAT_MASK, - GLBL_ERR_STAT_ERR_RAM_DBE_MASK, - &eqdma_cpm5_hw_ram_dbe_err_process - }, - { - EQDMA_CPM5_DBE_ERR_MI_H2C2_DAT, - "H2C MM data buffer double bit ECC error", - EQDMA_CPM5_RAM_DBE_MSK_A_ADDR, - EQDMA_CPM5_RAM_DBE_STS_A_ADDR, - RAM_DBE_STS_A_MI_H2C2_DAT_MASK, - GLBL_ERR_STAT_ERR_RAM_DBE_MASK, - &eqdma_cpm5_hw_ram_dbe_err_process - }, - { - EQDMA_CPM5_DBE_ERR_MI_H2C3_DAT, - "H2C MM data buffer double bit ECC error", - EQDMA_CPM5_RAM_DBE_MSK_A_ADDR, - EQDMA_CPM5_RAM_DBE_STS_A_ADDR, - RAM_DBE_STS_A_MI_H2C3_DAT_MASK, - GLBL_ERR_STAT_ERR_RAM_DBE_MASK, - &eqdma_cpm5_hw_ram_dbe_err_process - }, - { - EQDMA_CPM5_DBE_ERR_MI_C2H0_DAT, - "C2H MM data buffer double bit ECC error", - EQDMA_CPM5_RAM_DBE_MSK_A_ADDR, - EQDMA_CPM5_RAM_DBE_STS_A_ADDR, - RAM_DBE_STS_A_MI_C2H0_DAT_MASK, - GLBL_ERR_STAT_ERR_RAM_DBE_MASK, - &eqdma_cpm5_hw_ram_dbe_err_process - }, - { - EQDMA_CPM5_DBE_ERR_MI_C2H1_DAT, - "C2H MM data buffer double bit ECC error", - EQDMA_CPM5_RAM_DBE_MSK_A_ADDR, - EQDMA_CPM5_RAM_DBE_STS_A_ADDR, - RAM_DBE_STS_A_MI_C2H1_DAT_MASK, - GLBL_ERR_STAT_ERR_RAM_DBE_MASK, - &eqdma_cpm5_hw_ram_dbe_err_process - }, - { - EQDMA_CPM5_DBE_ERR_MI_C2H2_DAT, - "C2H MM data buffer double bit ECC error", - EQDMA_CPM5_RAM_DBE_MSK_A_ADDR, - EQDMA_CPM5_RAM_DBE_STS_A_ADDR, - RAM_DBE_STS_A_MI_C2H2_DAT_MASK, - GLBL_ERR_STAT_ERR_RAM_DBE_MASK, - &eqdma_cpm5_hw_ram_dbe_err_process - }, - { - EQDMA_CPM5_DBE_ERR_MI_C2H3_DAT, - "C2H MM data buffer double bit ECC error", - EQDMA_CPM5_RAM_DBE_MSK_A_ADDR, - EQDMA_CPM5_RAM_DBE_STS_A_ADDR, - RAM_DBE_STS_A_MI_C2H3_DAT_MASK, - GLBL_ERR_STAT_ERR_RAM_DBE_MASK, - &eqdma_cpm5_hw_ram_dbe_err_process - }, - { - EQDMA_CPM5_DBE_ERR_H2C_RD_BRG_DAT, - "Bridge master read double bit ECC error", - EQDMA_CPM5_RAM_DBE_MSK_A_ADDR, - EQDMA_CPM5_RAM_DBE_STS_A_ADDR, - RAM_DBE_STS_A_H2C_RD_BRG_DAT_MASK, - GLBL_ERR_STAT_ERR_RAM_DBE_MASK, - &eqdma_cpm5_hw_ram_dbe_err_process - }, - { - EQDMA_CPM5_DBE_ERR_H2C_WR_BRG_DAT, - "Bridge master write double bit ECC error", - EQDMA_CPM5_RAM_DBE_MSK_A_ADDR, - EQDMA_CPM5_RAM_DBE_STS_A_ADDR, - RAM_DBE_STS_A_H2C_WR_BRG_DAT_MASK, - GLBL_ERR_STAT_ERR_RAM_DBE_MASK, - &eqdma_cpm5_hw_ram_dbe_err_process - }, - { - EQDMA_CPM5_DBE_ERR_C2H_RD_BRG_DAT, - "Bridge slave read data buffer double bit ECC error", - EQDMA_CPM5_RAM_DBE_MSK_A_ADDR, - EQDMA_CPM5_RAM_DBE_STS_A_ADDR, - RAM_DBE_STS_A_C2H_RD_BRG_DAT_MASK, - GLBL_ERR_STAT_ERR_RAM_DBE_MASK, - &eqdma_cpm5_hw_ram_dbe_err_process - }, - { - EQDMA_CPM5_DBE_ERR_C2H_WR_BRG_DAT, - "Bridge slave write data buffer double bit ECC error", - EQDMA_CPM5_RAM_DBE_MSK_A_ADDR, - EQDMA_CPM5_RAM_DBE_STS_A_ADDR, - RAM_DBE_STS_A_C2H_WR_BRG_DAT_MASK, - GLBL_ERR_STAT_ERR_RAM_DBE_MASK, - &eqdma_cpm5_hw_ram_dbe_err_process - }, - { - EQDMA_CPM5_DBE_ERR_FUNC_MAP, - "Function map RAM double bit ECC error", - EQDMA_CPM5_RAM_DBE_MSK_A_ADDR, - EQDMA_CPM5_RAM_DBE_STS_A_ADDR, - RAM_DBE_STS_A_FUNC_MAP_MASK, - GLBL_ERR_STAT_ERR_RAM_DBE_MASK, - &eqdma_cpm5_hw_ram_dbe_err_process - }, - { - EQDMA_CPM5_DBE_ERR_DSC_HW_CTXT, - "Descriptor engine hardware context RAM double bit ECC error", - EQDMA_CPM5_RAM_DBE_MSK_A_ADDR, - EQDMA_CPM5_RAM_DBE_STS_A_ADDR, - RAM_DBE_STS_A_DSC_HW_CTXT_MASK, - GLBL_ERR_STAT_ERR_RAM_DBE_MASK, - &eqdma_cpm5_hw_ram_dbe_err_process - }, - { - EQDMA_CPM5_DBE_ERR_DSC_CRD_RCV, - "Descriptor engine receive credit context RAM double bit ECC error", - EQDMA_CPM5_RAM_DBE_MSK_A_ADDR, - EQDMA_CPM5_RAM_DBE_STS_A_ADDR, - RAM_DBE_STS_A_DSC_CRD_RCV_MASK, - GLBL_ERR_STAT_ERR_RAM_DBE_MASK, - &eqdma_cpm5_hw_ram_dbe_err_process - }, - { - EQDMA_CPM5_DBE_ERR_DSC_SW_CTXT, - "Descriptor engine software context RAM double bit ECC error", - EQDMA_CPM5_RAM_DBE_MSK_A_ADDR, - EQDMA_CPM5_RAM_DBE_STS_A_ADDR, - RAM_DBE_STS_A_DSC_SW_CTXT_MASK, - GLBL_ERR_STAT_ERR_RAM_DBE_MASK, - &eqdma_cpm5_hw_ram_dbe_err_process - }, - { - EQDMA_CPM5_DBE_ERR_DSC_CPLI, - "Descriptor engine fetch completion information RAM double bit ECC error", - EQDMA_CPM5_RAM_DBE_MSK_A_ADDR, - EQDMA_CPM5_RAM_DBE_STS_A_ADDR, - RAM_DBE_STS_A_DSC_CPLI_MASK, - GLBL_ERR_STAT_ERR_RAM_DBE_MASK, - &eqdma_cpm5_hw_ram_dbe_err_process - }, - { - EQDMA_CPM5_DBE_ERR_DSC_CPLD, - "Descriptor engine fetch completion data RAM double bit ECC error", - EQDMA_CPM5_RAM_DBE_MSK_A_ADDR, - EQDMA_CPM5_RAM_DBE_STS_A_ADDR, - RAM_DBE_STS_A_DSC_CPLD_MASK, - GLBL_ERR_STAT_ERR_RAM_DBE_MASK, - &eqdma_cpm5_hw_ram_dbe_err_process - }, - { - EQDMA_CPM5_DBE_ERR_MI_TL_SLV_FIFO_RAM, - "TL Slave FIFO RAM double bit ECC error", - EQDMA_CPM5_RAM_DBE_MSK_A_ADDR, - EQDMA_CPM5_RAM_DBE_STS_A_ADDR, - RAM_DBE_STS_A_MI_TL_SLV_FIFO_RAM_MASK, - GLBL_ERR_STAT_ERR_RAM_DBE_MASK, - &eqdma_cpm5_hw_ram_dbe_err_process - }, - { - EQDMA_CPM5_DBE_ERR_TIMER_FIFO_RAM, - "Timer fifo RAM double bit ECC error", - EQDMA_CPM5_RAM_DBE_MSK_A_ADDR, - EQDMA_CPM5_RAM_DBE_STS_A_ADDR, - RAM_DBE_STS_A_TIMER_FIFO_RAM_MASK, - GLBL_ERR_STAT_ERR_RAM_DBE_MASK, - &eqdma_cpm5_hw_ram_dbe_err_process - }, - { - EQDMA_CPM5_DBE_ERR_QID_FIFO_RAM, - "C2H ST QID FIFO RAM double bit ECC error", - EQDMA_CPM5_RAM_DBE_MSK_A_ADDR, - EQDMA_CPM5_RAM_DBE_STS_A_ADDR, - RAM_DBE_STS_A_QID_FIFO_RAM_MASK, - GLBL_ERR_STAT_ERR_RAM_DBE_MASK, - &eqdma_cpm5_hw_ram_dbe_err_process - }, - { - EQDMA_CPM5_DBE_ERR_WRB_COAL_DATA_RAM, - "Writeback Coalescing RAM double bit ECC error", - EQDMA_CPM5_RAM_DBE_MSK_A_ADDR, - EQDMA_CPM5_RAM_DBE_STS_A_ADDR, - RAM_DBE_STS_A_WRB_COAL_DATA_RAM_MASK, - GLBL_ERR_STAT_ERR_RAM_DBE_MASK, - &eqdma_cpm5_hw_ram_dbe_err_process - }, - { - EQDMA_CPM5_DBE_ERR_INT_CTXT_RAM, - "Interrupt context RAM double bit ECC error", - EQDMA_CPM5_RAM_DBE_MSK_A_ADDR, - EQDMA_CPM5_RAM_DBE_STS_A_ADDR, - RAM_DBE_STS_A_INT_CTXT_RAM_MASK, - GLBL_ERR_STAT_ERR_RAM_DBE_MASK, - &eqdma_cpm5_hw_ram_dbe_err_process - }, - { - EQDMA_CPM5_DBE_ERR_DESC_REQ_FIFO_RAM, - "C2H ST descriptor request RAM double bit ECC error", - EQDMA_CPM5_RAM_DBE_MSK_A_ADDR, - EQDMA_CPM5_RAM_DBE_STS_A_ADDR, - RAM_DBE_STS_A_DESC_REQ_FIFO_RAM_MASK, - GLBL_ERR_STAT_ERR_RAM_DBE_MASK, - &eqdma_cpm5_hw_ram_dbe_err_process - }, - { - EQDMA_CPM5_DBE_ERR_PFCH_CTXT_RAM, - "C2H ST prefetch RAM double bit ECC error", - EQDMA_CPM5_RAM_DBE_MSK_A_ADDR, - EQDMA_CPM5_RAM_DBE_STS_A_ADDR, - RAM_DBE_STS_A_PFCH_CTXT_RAM_MASK, - GLBL_ERR_STAT_ERR_RAM_DBE_MASK, - &eqdma_cpm5_hw_ram_dbe_err_process - }, - { - EQDMA_CPM5_DBE_ERR_WRB_CTXT_RAM, - "C2H ST completion context RAM double bit ECC error", - EQDMA_CPM5_RAM_DBE_MSK_A_ADDR, - EQDMA_CPM5_RAM_DBE_STS_A_ADDR, - RAM_DBE_STS_A_WRB_CTXT_RAM_MASK, - GLBL_ERR_STAT_ERR_RAM_DBE_MASK, - &eqdma_cpm5_hw_ram_dbe_err_process - }, - { - EQDMA_CPM5_DBE_ERR_PFCH_LL_RAM, - "C2H ST prefetch list RAM double bit ECC error", - EQDMA_CPM5_RAM_DBE_MSK_A_ADDR, - EQDMA_CPM5_RAM_DBE_STS_A_ADDR, - RAM_DBE_STS_A_PFCH_LL_RAM_MASK, - GLBL_ERR_STAT_ERR_RAM_DBE_MASK, - &eqdma_cpm5_hw_ram_dbe_err_process - }, - { - EQDMA_CPM5_DBE_ERR_PEND_FIFO_RAM, - "Pend FIFO RAM double bit ECC error", - EQDMA_CPM5_RAM_DBE_MSK_A_ADDR, - EQDMA_CPM5_RAM_DBE_STS_A_ADDR, - RAM_DBE_STS_A_PEND_FIFO_RAM_MASK, - GLBL_ERR_STAT_ERR_RAM_DBE_MASK, - &eqdma_cpm5_hw_ram_dbe_err_process - }, - { - EQDMA_CPM5_DBE_ERR_RC_RRQ_ODD_RAM, - "RC RRQ Odd RAM double bit ECC error.", - EQDMA_CPM5_RAM_DBE_MSK_A_ADDR, - EQDMA_CPM5_RAM_DBE_STS_A_ADDR, - RAM_DBE_STS_A_RC_RRQ_ODD_RAM_MASK, - GLBL_ERR_STAT_ERR_RAM_DBE_MASK, - &eqdma_cpm5_hw_ram_dbe_err_process - }, - { - EQDMA_CPM5_DBE_ERR_ALL, - "All DBE errors", - EQDMA_CPM5_RAM_DBE_MSK_A_ADDR, - EQDMA_CPM5_RAM_DBE_STS_A_ADDR, - EQDMA_CPM5_DBE_ERR_ALL_MASK, - GLBL_ERR_STAT_ERR_RAM_DBE_MASK, - &eqdma_cpm5_hw_ram_dbe_err_process - }, - - /* MM C2H Engine 0 errors */ - { - EQDMA_CPM5_MM_C2H_WR_SLR_ERR, - "MM C2H0 WR SLV Error", - EQDMA_CPM5_C2H_MM_ERR_CODE_ENABLE_MASK_ADDR, - EQDMA_CPM5_C2H_MM_STATUS_ADDR, - C2H_MM_ERR_CODE_ENABLE_WR_SLV_ERR_MASK, - GLBL_ERR_STAT_ERR_C2H_MM_0_MASK, - &eqdma_cpm5_mm_c2h0_err_process - }, - { - EQDMA_CPM5_MM_C2H_RD_SLR_ERR, - "MM C2H0 RD SLV Error", - EQDMA_CPM5_C2H_MM_ERR_CODE_ENABLE_MASK_ADDR, - EQDMA_CPM5_C2H_MM_STATUS_ADDR, - C2H_MM_ERR_CODE_ENABLE_RD_SLV_ERR_MASK, - GLBL_ERR_STAT_ERR_C2H_MM_0_MASK, - &eqdma_cpm5_mm_c2h0_err_process - }, - { - EQDMA_CPM5_MM_C2H_WR_FLR_ERR, - "MM C2H0 WR FLR Error", - EQDMA_CPM5_C2H_MM_ERR_CODE_ENABLE_MASK_ADDR, - EQDMA_CPM5_C2H_MM_STATUS_ADDR, - C2H_MM_ERR_CODE_ENABLE_WR_FLR_MASK, - GLBL_ERR_STAT_ERR_C2H_MM_0_MASK, - &eqdma_cpm5_mm_c2h0_err_process - }, - { - EQDMA_CPM5_MM_C2H_UR_ERR, - "MM C2H0 Unsupported Request Error", - EQDMA_CPM5_C2H_MM_ERR_CODE_ENABLE_MASK_ADDR, - EQDMA_CPM5_C2H_MM_STATUS_ADDR, - C2H_MM_ERR_CODE_ENABLE_WR_UR_MASK, - GLBL_ERR_STAT_ERR_C2H_MM_0_MASK, - &eqdma_cpm5_mm_c2h0_err_process - }, - { - EQDMA_CPM5_MM_C2H_WR_UC_RAM_ERR, - "MM C2H0 Write Uncorrectable RAM Error", - EQDMA_CPM5_C2H_MM_ERR_CODE_ENABLE_MASK_ADDR, - EQDMA_CPM5_C2H_MM_STATUS_ADDR, - C2H_MM_ERR_CODE_ENABLE_WR_UC_RAM_MASK, - GLBL_ERR_STAT_ERR_C2H_MM_0_MASK, - &eqdma_cpm5_mm_c2h0_err_process - }, - { - EQDMA_CPM5_MM_C2H_ERR_ALL, - "All MM C2H Errors", - EQDMA_CPM5_C2H_MM_ERR_CODE_ENABLE_MASK_ADDR, - EQDMA_CPM5_C2H_MM_STATUS_ADDR, - EQDMA_CPM5_MM_C2H_ERR_ALL_MASK, - GLBL_ERR_STAT_ERR_C2H_MM_0_MASK, - &eqdma_cpm5_hw_desc_err_process - }, - /* MM H2C Engine 0 Errors */ - { - EQDMA_CPM5_MM_H2C0_RD_HDR_POISON_ERR, - "MM H2C0 Read cmpt header pison Error", - EQDMA_CPM5_H2C_MM_ERR_CODE_ENABLE_MASK_ADDR, - EQDMA_CPM5_H2C_MM_STATUS_ADDR, - H2C_MM_ERR_CODE_ENABLE_RD_HRD_POISON_ERR_MASK, - GLBL_ERR_STAT_ERR_H2C_MM_0_MASK, - &eqdma_cpm5_mm_h2c0_err_process - }, - { - EQDMA_CPM5_MM_H2C0_RD_UR_CA_ERR, - "MM H2C0 Read cmpt unsupported request Error", - EQDMA_CPM5_H2C_MM_ERR_CODE_ENABLE_MASK_ADDR, - EQDMA_CPM5_H2C_MM_STATUS_ADDR, - H2C_MM_ERR_CODE_ENABLE_RD_UR_CA_MASK, - GLBL_ERR_STAT_ERR_H2C_MM_0_MASK, - &eqdma_cpm5_mm_h2c0_err_process - }, - { - EQDMA_CPM5_MM_H2C0_RD_HDR_BYTE_ERR, - "MM H2C0 Read cmpt hdr byte cnt Error", - EQDMA_CPM5_H2C_MM_ERR_CODE_ENABLE_MASK_ADDR, - EQDMA_CPM5_H2C_MM_STATUS_ADDR, - H2C_MM_ERR_CODE_ENABLE_RD_HDR_BYTE_ERR_MASK, - GLBL_ERR_STAT_ERR_H2C_MM_0_MASK, - &eqdma_cpm5_mm_h2c0_err_process - }, - { - EQDMA_CPM5_MM_H2C0_RD_HDR_PARAM_ERR, - "MM H2C0 Read cmpt hdr param mismatch Error", - EQDMA_CPM5_H2C_MM_ERR_CODE_ENABLE_MASK_ADDR, - EQDMA_CPM5_H2C_MM_STATUS_ADDR, - H2C_MM_ERR_CODE_ENABLE_RD_HDR_PARA_MASK, - GLBL_ERR_STAT_ERR_H2C_MM_0_MASK, - &eqdma_cpm5_mm_h2c0_err_process - }, - { - EQDMA_CPM5_MM_H2C0_RD_HDR_ADR_ERR, - "MM H2C0 Read cmpt hdr address mismatch Error", - EQDMA_CPM5_H2C_MM_ERR_CODE_ENABLE_MASK_ADDR, - EQDMA_CPM5_H2C_MM_STATUS_ADDR, - H2C_MM_ERR_CODE_ENABLE_RD_HDR_ADR_ERR_MASK, - GLBL_ERR_STAT_ERR_H2C_MM_0_MASK, - &eqdma_cpm5_mm_h2c0_err_process - }, - { - EQDMA_CPM5_MM_H2C0_RD_FLR_ERR, - "MM H2C0 Read flr Error", - EQDMA_CPM5_H2C_MM_ERR_CODE_ENABLE_MASK_ADDR, - EQDMA_CPM5_H2C_MM_STATUS_ADDR, - H2C_MM_ERR_CODE_ENABLE_RD_FLR_ERR_MASK, - GLBL_ERR_STAT_ERR_H2C_MM_0_MASK, - &eqdma_cpm5_mm_h2c0_err_process - }, - { - EQDMA_CPM5_MM_H2C0_RD_DAT_POISON_ERR, - "MM H2C0 Read data poison Error", - EQDMA_CPM5_H2C_MM_ERR_CODE_ENABLE_MASK_ADDR, - EQDMA_CPM5_H2C_MM_STATUS_ADDR, - H2C_MM_ERR_CODE_ENABLE_RD_DAT_POISON_ERR_MASK, - GLBL_ERR_STAT_ERR_H2C_MM_0_MASK, - &eqdma_cpm5_mm_h2c0_err_process - }, - { - EQDMA_CPM5_MM_H2C0_RD_RQ_DIS_ERR, - "MM H2C0 Read request disable Error", - EQDMA_CPM5_H2C_MM_ERR_CODE_ENABLE_MASK_ADDR, - EQDMA_CPM5_H2C_MM_STATUS_ADDR, - H2C_MM_ERR_CODE_ENABLE_RD_RQ_DIS_ERR_MASK, - GLBL_ERR_STAT_ERR_H2C_MM_0_MASK, - &eqdma_cpm5_mm_h2c0_err_process - }, - { - EQDMA_CPM5_MM_H2C0_WR_DEC_ERR, - "MM H2C0 Write desc Error", - EQDMA_CPM5_H2C_MM_ERR_CODE_ENABLE_MASK_ADDR, - EQDMA_CPM5_H2C_MM_STATUS_ADDR, - H2C_MM_ERR_CODE_ENABLE_WR_DEC_ERR_MASK, - GLBL_ERR_STAT_ERR_H2C_MM_0_MASK, - &eqdma_cpm5_mm_h2c0_err_process - }, - { - EQDMA_CPM5_MM_H2C0_WR_SLV_ERR, - "MM H2C0 Write slv Error", - EQDMA_CPM5_H2C_MM_ERR_CODE_ENABLE_MASK_ADDR, - EQDMA_CPM5_H2C_MM_STATUS_ADDR, - H2C_MM_ERR_CODE_ENABLE_WR_SLV_ERR_MASK, - GLBL_ERR_STAT_ERR_H2C_MM_0_MASK, - &eqdma_cpm5_mm_h2c0_err_process - }, - { - EQDMA_CPM5_MM_H2C0_ERR_ALL, - "All MM H2C Errors", - EQDMA_CPM5_H2C_MM_ERR_CODE_ENABLE_MASK_ADDR, - EQDMA_CPM5_H2C_MM_STATUS_ADDR, - EQDMA_CPM5_MM_H2C0_ERR_ALL_MASK, - GLBL_ERR_STAT_ERR_H2C_MM_0_MASK, - &eqdma_cpm5_hw_desc_err_process - }, -}; - - -static int32_t -all_eqdma_cpm5_hw_errs[EQDMA_CPM5_TOTAL_LEAF_ERROR_AGGREGATORS] = { - - EQDMA_CPM5_DSC_ERR_ALL, - EQDMA_CPM5_TRQ_ERR_ALL, - EQDMA_CPM5_ST_C2H_ERR_ALL, - EQDMA_CPM5_ST_FATAL_ERR_ALL, - EQDMA_CPM5_ST_H2C_ERR_ALL, - EQDMA_CPM5_SBE_1_ERR_ALL, - EQDMA_CPM5_SBE_ERR_ALL, - EQDMA_CPM5_DBE_1_ERR_ALL, - EQDMA_CPM5_DBE_ERR_ALL, - EQDMA_CPM5_MM_C2H_ERR_ALL, - EQDMA_CPM5_MM_H2C0_ERR_ALL -}; - -static struct qctx_entry eqdma_cpm5_sw_ctxt_entries[] = { - {"PIDX", 0}, - {"IRQ Arm", 0}, - {"Function Id", 0}, - {"Queue Enable", 0}, - {"Fetch Credit Enable", 0}, - {"Write back/Intr Check", 0}, - {"Write back/Intr Interval", 0}, - {"Address Translation", 0}, - {"Fetch Max", 0}, - {"Ring Size", 0}, - {"Descriptor Size", 0}, - {"Bypass Enable", 0}, - {"MM Channel", 0}, - {"Writeback Enable", 0}, - {"Interrupt Enable", 0}, - {"Port Id", 0}, - {"Interrupt No Last", 0}, - {"Error", 0}, - {"Writeback Error Sent", 0}, - {"IRQ Request", 0}, - {"Marker Disable", 0}, - {"Is Memory Mapped", 0}, - {"Descriptor Ring Base Addr (Low)", 0}, - {"Descriptor Ring Base Addr (High)", 0}, - {"Interrupt Vector/Ring Index", 0}, - {"Interrupt Aggregation", 0}, - {"Disable Interrupt with VF", 0}, - {"Pack descriptor output interface", 0}, - {"Irq Bypass", 0}, -}; - -static struct qctx_entry eqdma_cpm5_hw_ctxt_entries[] = { - {"CIDX", 0}, - {"Credits Consumed", 0}, - {"Descriptors Pending", 0}, - {"Queue Invalid No Desc Pending", 0}, - {"Eviction Pending", 0}, - {"Fetch Pending", 0}, -}; - -static struct qctx_entry eqdma_cpm5_credit_ctxt_entries[] = { - {"Credit", 0}, -}; - -static struct qctx_entry eqdma_cpm5_cmpt_ctxt_entries[] = { - {"Enable Status Desc Update", 0}, - {"Enable Interrupt", 0}, - {"Trigger Mode", 0}, - {"Function Id", 0}, - {"Counter Index", 0}, - {"Timer Index", 0}, - {"Interrupt State", 0}, - {"Color", 0}, - {"Ring Size", 0}, - {"Base Addr High (L)[37:6]", 0}, - {"Base Addr High(H)[63:38]", 0}, - {"Descriptor Size", 0}, - {"PIDX", 0}, - {"CIDX", 0}, - {"Valid", 0}, - {"Error", 0}, - {"Trigger Pending", 0}, - {"Timer Running", 0}, - {"Full Update", 0}, - {"Over Flow Check Disable", 0}, - {"Address Translation", 0}, - {"Interrupt Vector/Ring Index", 0}, - {"Interrupt Aggregation", 0}, - {"Disable Insterrupt with VF", 0}, - {"c2h Direction", 0}, - {"Base Addr Low[5:2]", 0}, - {"Shared Completion Queue", 0}, -}; - -static struct qctx_entry eqdma_cpm5_c2h_pftch_ctxt_entries[] = { - {"Bypass", 0}, - {"Buffer Size Index", 0}, - {"Port Id", 0}, - {"Variable Descriptor", 0}, - {"Number of descriptors prefetched", 0}, - {"Error", 0}, - {"Prefetch Enable", 0}, - {"In Prefetch", 0}, - {"Software Credit", 0}, - {"Valid", 0}, -}; - -static struct qctx_entry eqdma_cpm5_ind_intr_ctxt_entries[] = { - {"valid", 0}, - {"vec", 0}, - {"int_st", 0}, - {"color", 0}, - {"baddr_4k (Low)", 0}, - {"baddr_4k (High)", 0}, - {"page_size", 0}, - {"pidx", 0}, - {"at", 0}, - {"Function Id", 0}, -}; - -static struct qctx_entry eqdma_cpm5_fmap_ctxt_entries[] = { - {"Queue Base", 0}, - {"Queue Max", 0}, -}; - -static int eqdma_cpm5_indirect_reg_invalidate(void *dev_hndl, - enum ind_ctxt_cmd_sel sel, uint16_t hw_qid); -static int eqdma_cpm5_indirect_reg_clear(void *dev_hndl, - enum ind_ctxt_cmd_sel sel, uint16_t hw_qid); -static int eqdma_cpm5_indirect_reg_read(void *dev_hndl, - enum ind_ctxt_cmd_sel sel, - uint16_t hw_qid, uint32_t cnt, uint32_t *data); -static int eqdma_cpm5_indirect_reg_write(void *dev_hndl, - enum ind_ctxt_cmd_sel sel, - uint16_t hw_qid, uint32_t *data, uint16_t cnt); - -uint32_t eqdma_cpm5_get_config_num_regs(void) -{ - return eqdma_cpm5_config_num_regs_get(); -} - -struct xreg_info *eqdma_cpm5_get_config_regs(void) -{ - return eqdma_cpm5_config_regs_get(); -} - -uint32_t eqdma_cpm5_reg_dump_buf_len(void) -{ - uint32_t length = (eqdma_cpm5_config_num_regs_get() + 1) - * REG_DUMP_SIZE_PER_LINE; - return length; -} - -int eqdma_cpm5_context_buf_len(uint8_t st, - enum qdma_dev_q_type q_type, uint32_t *buflen) -{ - int len = 0; - - if (q_type == QDMA_DEV_Q_TYPE_CMPT) { - len += (((sizeof(eqdma_cpm5_cmpt_ctxt_entries) / - sizeof(eqdma_cpm5_cmpt_ctxt_entries[0])) + 1) * - REG_DUMP_SIZE_PER_LINE); - } else { - len += (((sizeof(eqdma_cpm5_sw_ctxt_entries) / - sizeof(eqdma_cpm5_sw_ctxt_entries[0])) + 1) - * REG_DUMP_SIZE_PER_LINE); - - len += (((sizeof(eqdma_cpm5_hw_ctxt_entries) / - sizeof(eqdma_cpm5_hw_ctxt_entries[0])) + 1) * - REG_DUMP_SIZE_PER_LINE); - - len += (((sizeof(eqdma_cpm5_credit_ctxt_entries) / - sizeof(eqdma_cpm5_credit_ctxt_entries[0])) + 1) * - REG_DUMP_SIZE_PER_LINE); - - len += (((sizeof(eqdma_cpm5_fmap_ctxt_entries) / - sizeof(eqdma_cpm5_fmap_ctxt_entries[0])) + 1) * - REG_DUMP_SIZE_PER_LINE); - - if (st && (q_type == QDMA_DEV_Q_TYPE_C2H)) { - len += (((sizeof(eqdma_cpm5_cmpt_ctxt_entries) / - sizeof(eqdma_cpm5_cmpt_ctxt_entries[0])) + - 1) * - REG_DUMP_SIZE_PER_LINE); - - len += (((sizeof(eqdma_cpm5_c2h_pftch_ctxt_entries) - / - sizeof(eqdma_cpm5_c2h_pftch_ctxt_entries[0] - )) + 1) * REG_DUMP_SIZE_PER_LINE); - } - } - - *buflen = len; - return 0; -} - -static uint32_t eqdma_cpm5_intr_context_buf_len(void) -{ - uint32_t len = 0; - - len += (((sizeof(eqdma_cpm5_ind_intr_ctxt_entries) / - sizeof(eqdma_cpm5_ind_intr_ctxt_entries[0])) + 1) * - REG_DUMP_SIZE_PER_LINE); - return len; -} - -/* - * eqdma_cpm5_set_perf_opt() - Helper function to set the - * cpm5 perf optimizations. - * - */ -static void eqdma_cpm5_set_perf_opt(void *dev_hndl) -{ - uint32_t reg_val = 0; - uint32_t pftch_cache_depth = 0; - uint32_t pftch_qcnt = 0; - uint32_t pftch_evnt_qcnt_th = 0; - uint32_t crdt_coal_fifo_th = 0; - uint32_t crdt_coal_crdt_th = 0; - - /* C2H interrupt timer tick */ - qdma_reg_write(dev_hndl, EQDMA_CPM5_C2H_INT_TIMER_TICK_ADDR, - EQDMA_CPM5_DEFAULT_C2H_INTR_TIMER_TICK); - -/* - * #define EQDMA_CPM5_C2H_PFCH_CACHE_DEPTH_ADDR 0xBE0 - * #define C2H_PFCH_CACHE_DEPTH_MAX_STBUF_MASK GENMASK(23, 16) - * #define C2H_PFCH_CACHE_DEPTH_MASK GENMASK(7, 0) - */ - reg_val = qdma_reg_read(dev_hndl, EQDMA_CPM5_C2H_PFCH_CACHE_DEPTH_ADDR); - pftch_cache_depth = FIELD_GET(C2H_PFCH_CACHE_DEPTH_MASK, reg_val); - -/* - * #define EQDMA_CPM5_GLBL_DSC_CFG_ADDR 0x250 - * #define GLBL_DSC_CFG_RSVD_1_MASK GENMASK(31, 10) - * #define GLBL_DSC_CFG_UNC_OVR_COR_MASK BIT(9) - * #define GLBL_DSC_CFG_CTXT_FER_DIS_MASK BIT(8) - * #define GLBL_DSC_CFG_RSVD_2_MASK GENMASK(7, 6) - * #define GLBL_DSC_CFG_MAXFETCH_MASK GENMASK(5, 3) - * #define GLBL_DSC_CFG_WB_ACC_INT_MASK GENMASK(2, 0) - */ -#define GLBL_DSC_CFG_RSVD_1_DFLT 0 -#define GLBL_DSC_CFG_UNC_OVR_COR_DFLT 0 -#define GLBL_DSC_CFG_CTXT_FER_DIS_DFLT 0 -#define GLBL_DSC_CFG_RSVD_2_DFLT 0 -/* =IF(Internal mode, 2,5) */ -#define GLBL_DSC_CFG_MAXFETCH 2 -#define GLBL_DSC_CFG_WB_ACC_INT 5 - reg_val = - FIELD_SET(GLBL_DSC_CFG_RSVD_1_MASK, GLBL_DSC_CFG_RSVD_1_DFLT) | - FIELD_SET(GLBL_DSC_CFG_UNC_OVR_COR_MASK, - GLBL_DSC_CFG_UNC_OVR_COR_DFLT) | - FIELD_SET(GLBL_DSC_CFG_CTXT_FER_DIS_MASK, - GLBL_DSC_CFG_CTXT_FER_DIS_DFLT) | - FIELD_SET(GLBL_DSC_CFG_RSVD_2_MASK, GLBL_DSC_CFG_RSVD_2_DFLT) | - FIELD_SET(GLBL_DSC_CFG_MAXFETCH_MASK, - GLBL_DSC_CFG_MAXFETCH) | - FIELD_SET(GLBL_DSC_CFG_WB_ACC_INT_MASK, - GLBL_DSC_CFG_WB_ACC_INT); - qdma_reg_write(dev_hndl, EQDMA_CPM5_GLBL_DSC_CFG_ADDR, reg_val); - reg_val = qdma_reg_read(dev_hndl, EQDMA_CPM5_GLBL_DSC_CFG_ADDR); - qdma_log_info("%s: reg = 0x%08X val = 0x%08X\n", - __func__, EQDMA_CPM5_GLBL_DSC_CFG_ADDR, reg_val); - -/* - * #define EQDMA_CPM5_CFG_BLK_MISC_CTL_ADDR 0x4C - * #define CFG_BLK_MISC_CTL_RSVD_1_MASK GENMASK(31, 24) - * #define CFG_BLK_MISC_CTL_10B_TAG_EN_MASK BIT(23) - * #define CFG_BLK_MISC_CTL_RSVD_2_MASK BIT(22) - * #define CFG_BLK_MISC_CTL_AXI_WBK_MASK BIT(21) - * #define CFG_BLK_MISC_CTL_AXI_DSC_MASK BIT(20) - * #define CFG_BLK_MISC_CTL_NUM_TAG_MASK GENMASK(19, 8) - * #define CFG_BLK_MISC_CTL_RSVD_3_MASK GENMASK(7, 5) - * #define CFG_BLK_MISC_CTL_RQ_METERING_MULTIPLIER_MASK GENMASK(4, 0) - */ -#define CFG_BLK_MISC_CTL_RSVD_1_DFLT 0 -#define CFG_BLK_MISC_CTL_RSVD_2_DFLT 0 -#define CFG_BLK_MISC_CTL_AXI_WBK_DFLT 0 -#define CFG_BLK_MISC_CTL_AXI_DSC_DFLT 0 -/* IF(10bit tag enabled, 512,256) */ -#ifdef EQDMA_CPM5_10BIT_TAG_ENABLE -#define CFG_BLK_MISC_CTL_10B_TAG_DFLT 1 -#define CFG_BLK_MISC_CTL_NUM_TAG_DFLT 512 -#else -#define CFG_BLK_MISC_CTL_10B_TAG_DFLT 0 -#define CFG_BLK_MISC_CTL_NUM_TAG_DFLT 256 -#endif -#define CFG_BLK_MISC_CTL_RSVD_3_DFLT 0 -#define EQDMA_CFG_BLK_MISC_CTL_RQ_METERING_MUL 31 - reg_val = - FIELD_SET(CFG_BLK_MISC_CTL_RSVD_1_MASK, - CFG_BLK_MISC_CTL_RSVD_1_DFLT) | - FIELD_SET(CFG_BLK_MISC_CTL_10B_TAG_EN_MASK, - CFG_BLK_MISC_CTL_10B_TAG_DFLT) | - FIELD_SET(CFG_BLK_MISC_CTL_RSVD_2_MASK, - CFG_BLK_MISC_CTL_RSVD_2_DFLT) | - FIELD_SET(CFG_BLK_MISC_CTL_AXI_WBK_MASK, - CFG_BLK_MISC_CTL_AXI_WBK_DFLT) | - FIELD_SET(CFG_BLK_MISC_CTL_AXI_DSC_MASK, - CFG_BLK_MISC_CTL_AXI_DSC_DFLT) | - FIELD_SET(CFG_BLK_MISC_CTL_NUM_TAG_MASK, - CFG_BLK_MISC_CTL_NUM_TAG_DFLT) | - FIELD_SET(CFG_BLK_MISC_CTL_RSVD_3_MASK, - CFG_BLK_MISC_CTL_RSVD_3_DFLT) | - FIELD_SET(CFG_BLK_MISC_CTL_RQ_METERING_MULTIPLIER_MASK, - EQDMA_CFG_BLK_MISC_CTL_RQ_METERING_MUL); - qdma_reg_write(dev_hndl, EQDMA_CPM5_CFG_BLK_MISC_CTL_ADDR, reg_val); - reg_val = qdma_reg_read(dev_hndl, EQDMA_CPM5_CFG_BLK_MISC_CTL_ADDR); - qdma_log_info("%s: reg = 0x%08X val = 0x%08X\n", - __func__, EQDMA_CPM5_CFG_BLK_MISC_CTL_ADDR, reg_val); - -/* - * #define EQDMA_CPM5_C2H_PFCH_CFG_ADDR 0xB08 - * #define C2H_PFCH_CFG_EVTFL_TH_MASK GENMASK(31, 16) - * #define C2H_PFCH_CFG_FL_TH_MASK GENMASK(15, 0) - */ -#define EQDMA_PFTCH_CFG_EVT_PFTH_FL_TH 256 -#define C2H_PFCH_CFG_FL_TH_DFLT 256 - reg_val = - FIELD_SET(C2H_PFCH_CFG_EVTFL_TH_MASK, - EQDMA_PFTCH_CFG_EVT_PFTH_FL_TH) | - FIELD_SET(C2H_PFCH_CFG_FL_TH_MASK, - C2H_PFCH_CFG_FL_TH_DFLT); - - qdma_reg_write(dev_hndl, EQDMA_CPM5_C2H_PFCH_CFG_ADDR, reg_val); - reg_val = qdma_reg_read(dev_hndl, EQDMA_CPM5_C2H_PFCH_CFG_ADDR); - qdma_log_info("%s: reg = 0x%08X val = 0x%08X\n", - __func__, EQDMA_CPM5_C2H_PFCH_CFG_ADDR, reg_val); - -/* - * #define EQDMA_CPM5_C2H_PFCH_CFG_1_ADDR 0xA80 - * #define C2H_PFCH_CFG_1_EVT_QCNT_TH_MASK GENMASK(31, 16) - * #define C2H_PFCH_CFG_1_QCNT_MASK GENMASK(15, 0) - */ - pftch_qcnt = pftch_cache_depth - PREFETCH_QUEUE_COUNT_STEP; - pftch_evnt_qcnt_th = pftch_qcnt - PREFETCH_QUEUE_COUNT_STEP; - reg_val = - FIELD_SET(C2H_PFCH_CFG_1_EVT_QCNT_TH_MASK, pftch_evnt_qcnt_th) | - FIELD_SET(C2H_PFCH_CFG_1_QCNT_MASK, pftch_qcnt); - qdma_reg_write(dev_hndl, EQDMA_CPM5_C2H_PFCH_CFG_1_ADDR, reg_val); - reg_val = qdma_reg_read(dev_hndl, EQDMA_CPM5_C2H_PFCH_CFG_1_ADDR); - qdma_log_info("%s: reg = 0x%08X val = 0x%08X\n", - __func__, EQDMA_CPM5_C2H_PFCH_CFG_1_ADDR, reg_val); - -/* - * #define EQDMA_CPM5_C2H_PFCH_CFG_2_ADDR 0xA84 - * #define C2H_PFCH_CFG_2_FENCE_MASK BIT(31) - * #define C2H_PFCH_CFG_2_RSVD_MASK GENMASK(30, 29) - * #define C2H_PFCH_CFG_2_VAR_DESC_NO_DROP_MASK BIT(28) - * #define C2H_PFCH_CFG_2_LL_SZ_TH_MASK GENMASK(27, 12) - * #define C2H_PFCH_CFG_2_VAR_DESC_NUM_MASK GENMASK(11, 6) - * #define C2H_PFCH_CFG_2_NUM_MASK GENMASK(5, 0) - */ -#define C2H_PFCH_CFG_2_FENCE_EN 1 -#define C2H_PFCH_CFG_2_RSVD_DFLT 0 -#define C2H_PFCH_CFG_2_VAR_DESC_NO_DROP_DFLT 0 -#define C2H_PFCH_CFG_2_LL_SZ_TH_DFLT 1024 -#define C2H_PFCH_CFG_2_VAR_DESC_NUM 15 -#define C2H_PFCH_CFG_2_NUM_PFCH_DFLT 16 - reg_val = - FIELD_SET(C2H_PFCH_CFG_2_FENCE_MASK, - C2H_PFCH_CFG_2_FENCE_EN) | - FIELD_SET(C2H_PFCH_CFG_2_RSVD_MASK, - C2H_PFCH_CFG_2_RSVD_DFLT) | - FIELD_SET(C2H_PFCH_CFG_2_VAR_DESC_NO_DROP_MASK, - C2H_PFCH_CFG_2_VAR_DESC_NO_DROP_DFLT) | - FIELD_SET(C2H_PFCH_CFG_2_LL_SZ_TH_MASK, - C2H_PFCH_CFG_2_LL_SZ_TH_DFLT) | - FIELD_SET(C2H_PFCH_CFG_2_VAR_DESC_NUM_MASK, - C2H_PFCH_CFG_2_VAR_DESC_NUM) | - FIELD_SET(C2H_PFCH_CFG_2_NUM_MASK, - C2H_PFCH_CFG_2_NUM_PFCH_DFLT); - qdma_reg_write(dev_hndl, EQDMA_CPM5_C2H_PFCH_CFG_2_ADDR, reg_val); - reg_val = qdma_reg_read(dev_hndl, EQDMA_CPM5_C2H_PFCH_CFG_2_ADDR); - qdma_log_info("%s: reg = 0x%08X val = 0x%08X\n", - __func__, EQDMA_CPM5_C2H_PFCH_CFG_2_ADDR, reg_val); - -/* Registers Not Applicable for CPM5 - * #define EQDMA_PFCH_CFG_3_ADDR 0x147C - * #define EQDMA_PFCH_CFG_4_ADDR 0x1484 - */ - -/* - * #define EQDMA_CPM5_C2H_CRDT_COAL_CFG_1_ADDR 0x1400 - * #define C2H_CRDT_COAL_CFG_1_RSVD_1_MASK GENMASK(31, 18) - * #define C2H_CRDT_COAL_CFG_1_PLD_FIFO_TH_MASK GENMASK(17, 10) - * #define C2H_CRDT_COAL_CFG_1_TIMER_TH_MASK GENMASK(9, 0)4 - */ -#define C2H_CRDT_COAL_CFG_1_RSVD_1_DFLT 0 -#define C2H_CRDT_COAL_CFG_1_PLD_FIFO_TH_DFLT 16 -#define C2H_CRDT_COAL_CFG_1_TIMER_TH 16 - reg_val = - FIELD_SET(C2H_CRDT_COAL_CFG_1_RSVD_1_MASK, - C2H_CRDT_COAL_CFG_1_RSVD_1_DFLT) | - FIELD_SET(C2H_CRDT_COAL_CFG_1_PLD_FIFO_TH_MASK, - C2H_CRDT_COAL_CFG_1_PLD_FIFO_TH_DFLT) | - FIELD_SET(C2H_CRDT_COAL_CFG_1_TIMER_TH_MASK, - C2H_CRDT_COAL_CFG_1_TIMER_TH); - qdma_reg_write(dev_hndl, EQDMA_CPM5_C2H_CRDT_COAL_CFG_1_ADDR, reg_val); - reg_val = qdma_reg_read(dev_hndl, EQDMA_CPM5_C2H_CRDT_COAL_CFG_1_ADDR); - qdma_log_info("%s: reg = 0x%08X val = 0x%08X\n", - __func__, EQDMA_CPM5_C2H_CRDT_COAL_CFG_1_ADDR, reg_val); - -/* - * #define EQDMA_CPM5_C2H_CRDT_COAL_CFG_2_ADDR 0x1404 - * #define C2H_CRDT_COAL_CFG_2_RSVD_1_MASK GENMASK(31, 24) - * #define C2H_CRDT_COAL_CFG_2_FIFO_TH_MASK GENMASK(23, 16) - * #define C2H_CRDT_COAL_CFG_2_RESERVED1_MASK GENMASK(15, 11) - * #define C2H_CRDT_COAL_CFG_2_NT_TH_MASK GENMASK(10, 0) - */ -#define C2H_CRDT_COAL_CFG_2_RSVD_1_DFLT 0 -#define C2H_CRDT_COAL_CFG_2_RESERVED1_DFLT 0 -#define C2H_CRDT_COAL_CFG_2_CRDT_CNT_TH_DFLT 156 - crdt_coal_fifo_th = pftch_cache_depth - 8; - crdt_coal_crdt_th = C2H_CRDT_COAL_CFG_2_CRDT_CNT_TH_DFLT; - reg_val = - FIELD_SET(C2H_CRDT_COAL_CFG_2_RSVD_1_MASK, - C2H_CRDT_COAL_CFG_2_RSVD_1_DFLT) | - FIELD_SET(C2H_CRDT_COAL_CFG_2_FIFO_TH_MASK, - crdt_coal_fifo_th) | - FIELD_SET(C2H_CRDT_COAL_CFG_2_RESERVED1_MASK, - C2H_CRDT_COAL_CFG_2_RESERVED1_DFLT) | - FIELD_SET(C2H_CRDT_COAL_CFG_2_NT_TH_MASK, - crdt_coal_crdt_th); - qdma_reg_write(dev_hndl, EQDMA_CPM5_C2H_CRDT_COAL_CFG_2_ADDR, reg_val); - reg_val = qdma_reg_read(dev_hndl, EQDMA_CPM5_C2H_CRDT_COAL_CFG_2_ADDR); - qdma_log_info("%s: reg = 0x%08X val = 0x%08X\n", - __func__, EQDMA_CPM5_C2H_CRDT_COAL_CFG_2_ADDR, reg_val); - -/* - * #define EQDMA_CPM5_H2C_REQ_THROT_PCIE_ADDR 0xE24 - * #define H2C_REQ_THROT_PCIE_EN_REQ_MASK BIT(31) - * #define H2C_REQ_THROT_PCIE_MASK GENMASK(30, 19) - * #define H2C_REQ_THROT_PCIE_EN_DATA_MASK BIT(18) - * #define H2C_REQ_THROT_PCIE_DATA_THRESH_MASK GENMASK(17, 0) - */ -#define H2C_REQ_THROT_PCIE_EN_REQ 1 -/* IF(10bit tag enabled, 512-64, 192) */ -#ifdef EQDMA_CPM5_10BIT_TAG_ENABLE -#define H2C_REQ_THROT_PCIE_REQ_TH 448 -#else -#define H2C_REQ_THROT_PCIE_REQ_TH 192 -#endif -#define H2C_REQ_THROT_PCIE_EN_DATA 1 -#define H2C_REQ_THROT_PCIE_DATA_TH 57344 - reg_val = - FIELD_SET(H2C_REQ_THROT_PCIE_EN_REQ_MASK, - H2C_REQ_THROT_PCIE_EN_REQ) | - FIELD_SET(H2C_REQ_THROT_PCIE_MASK, - H2C_REQ_THROT_PCIE_REQ_TH) | - FIELD_SET(H2C_REQ_THROT_PCIE_EN_DATA_MASK, - H2C_REQ_THROT_PCIE_EN_DATA) | - FIELD_SET(H2C_REQ_THROT_PCIE_DATA_THRESH_MASK, - H2C_REQ_THROT_PCIE_DATA_TH); - qdma_reg_write(dev_hndl, EQDMA_CPM5_H2C_REQ_THROT_PCIE_ADDR, reg_val); - reg_val = qdma_reg_read(dev_hndl, EQDMA_CPM5_H2C_REQ_THROT_PCIE_ADDR); - qdma_log_info("%s: reg = 0x%08X val = 0x%08X\n", - __func__, EQDMA_CPM5_H2C_REQ_THROT_PCIE_ADDR, reg_val); - -/* - * #define EQDMA_CPM5_H2C_REQ_THROT_AXIMM_ADDR 0xE2C - * #define H2C_REQ_THROT_AXIMM_EN_REQ_MASK BIT(31) - * #define H2C_REQ_THROT_AXIMM_MASK GENMASK(30, 19) - * #define H2C_REQ_THROT_AXIMM_EN_DATA_MASK BIT(18) - * #define H2C_REQ_THROT_AXIMM_DATA_THRESH_MASK GENMASK(17, 0) - */ -#define H2C_REQ_THROT_AXIMM_EN_REQ 0 -/* IF(10bit tag en=1, 512-64, 192) */ -#ifdef EQDMA_CPM5_10BIT_TAG_ENABLE -#define H2C_REQ_THROT_AXIMM_REQ_TH 448 -#else -#define H2C_REQ_THROT_AXIMM_REQ_TH 192 -#endif -#define H2C_REQ_THROT_AXIMM_EN_DATA 0 -#define H2C_REQ_THROT_AXIMM_DATA_TH 65536 - reg_val = - FIELD_SET(H2C_REQ_THROT_AXIMM_EN_REQ_MASK, - H2C_REQ_THROT_AXIMM_EN_REQ) | - FIELD_SET(H2C_REQ_THROT_AXIMM_MASK, - H2C_REQ_THROT_AXIMM_REQ_TH) | - FIELD_SET(H2C_REQ_THROT_AXIMM_EN_DATA_MASK, - H2C_REQ_THROT_AXIMM_EN_DATA) | - FIELD_SET(H2C_REQ_THROT_AXIMM_DATA_THRESH_MASK, - H2C_REQ_THROT_AXIMM_DATA_TH); - qdma_reg_write(dev_hndl, EQDMA_CPM5_H2C_REQ_THROT_AXIMM_ADDR, reg_val); - reg_val = qdma_reg_read(dev_hndl, EQDMA_CPM5_H2C_REQ_THROT_AXIMM_ADDR); - qdma_log_info("%s: reg = 0x%08X val = 0x%08X\n", - __func__, EQDMA_CPM5_H2C_REQ_THROT_AXIMM_ADDR, reg_val); - -#define EQDMA_CPM5_H2C_MM_DATA_THROTTLE_ADDR 0x12EC -#define H2C_MM_DATA_THROTTLE_RSVD_1_MASK GENMASK(31, 17) -#define H2C_MM_DATA_THROTTLE_DAT_EN_MASK BIT(16) -#define H2C_MM_DATA_THROTTLE_DAT_MASK GENMASK(15, 0) -#define H2C_MM_DATA_THROTTLE_RSVD_1_DFLT 0 -#define H2C_MM_DATA_TH_EN 1 -#define H2C_MM_DATA_TH 57344 - reg_val = - FIELD_SET(H2C_MM_DATA_THROTTLE_RSVD_1_MASK, - H2C_MM_DATA_THROTTLE_RSVD_1_DFLT) | - FIELD_SET(H2C_MM_DATA_THROTTLE_DAT_EN_MASK, H2C_MM_DATA_TH_EN) | - FIELD_SET(H2C_MM_DATA_THROTTLE_DAT_MASK, H2C_MM_DATA_TH); - qdma_reg_write(dev_hndl, EQDMA_CPM5_H2C_MM_DATA_THROTTLE_ADDR, reg_val); - reg_val = qdma_reg_read(dev_hndl, EQDMA_CPM5_H2C_MM_DATA_THROTTLE_ADDR); - qdma_log_info("%s: reg = 0x%08X val = 0x%08X\n", - __func__, EQDMA_CPM5_H2C_MM_DATA_THROTTLE_ADDR, reg_val); -} - -/* - * eqdma_cpm5_indirect_reg_invalidate() - helper function to invalidate - * indirect context registers. - * - * return -QDMA_ERR_HWACC_BUSY_TIMEOUT if register - * value didn't match, QDMA_SUCCESS other wise - */ -static int eqdma_cpm5_indirect_reg_invalidate(void *dev_hndl, - enum ind_ctxt_cmd_sel sel, uint16_t hw_qid) -{ - union qdma_ind_ctxt_cmd cmd; - - qdma_reg_access_lock(dev_hndl); - - /* set command register */ - cmd.word = 0; - cmd.bits.qid = hw_qid; - cmd.bits.op = QDMA_CTXT_CMD_INV; - cmd.bits.sel = sel; - qdma_reg_write(dev_hndl, EQDMA_CPM5_IND_CTXT_CMD_ADDR, cmd.word); - - /* check if the operation went through well */ - if (hw_monitor_reg(dev_hndl, EQDMA_CPM5_IND_CTXT_CMD_ADDR, - IND_CTXT_CMD_BUSY_MASK, 0, - QDMA_REG_POLL_DFLT_INTERVAL_US, - QDMA_REG_POLL_DFLT_TIMEOUT_US)) { - qdma_reg_access_release(dev_hndl); - qdma_log_error("%s: hw_monitor_reg failed with err:%d\n", - __func__, - -QDMA_ERR_HWACC_BUSY_TIMEOUT); - return -QDMA_ERR_HWACC_BUSY_TIMEOUT; - } - - qdma_reg_access_release(dev_hndl); - - return QDMA_SUCCESS; -} - -/* - * eqdma_cpm5_indirect_reg_clear() - helper function to clear indirect - * context registers. - * - * return -QDMA_ERR_HWACC_BUSY_TIMEOUT if register - * value didn't match, QDMA_SUCCESS other wise - */ -static int eqdma_cpm5_indirect_reg_clear(void *dev_hndl, - enum ind_ctxt_cmd_sel sel, uint16_t hw_qid) -{ - union qdma_ind_ctxt_cmd cmd; - - qdma_reg_access_lock(dev_hndl); - - /* set command register */ - cmd.word = 0; - cmd.bits.qid = hw_qid; - cmd.bits.op = QDMA_CTXT_CMD_CLR; - cmd.bits.sel = sel; - qdma_reg_write(dev_hndl, EQDMA_CPM5_IND_CTXT_CMD_ADDR, cmd.word); - - /* check if the operation went through well */ - if (hw_monitor_reg(dev_hndl, EQDMA_CPM5_IND_CTXT_CMD_ADDR, - IND_CTXT_CMD_BUSY_MASK, 0, - QDMA_REG_POLL_DFLT_INTERVAL_US, - QDMA_REG_POLL_DFLT_TIMEOUT_US)) { - qdma_reg_access_release(dev_hndl); - qdma_log_error("%s: hw_monitor_reg failed with err:%d\n", - __func__, - -QDMA_ERR_HWACC_BUSY_TIMEOUT); - return -QDMA_ERR_HWACC_BUSY_TIMEOUT; - } - - qdma_reg_access_release(dev_hndl); - - return QDMA_SUCCESS; -} - -/* - * eqdma_cpm5_indirect_reg_read() - helper function to read indirect - * context registers. - * - * return -QDMA_ERR_HWACC_BUSY_TIMEOUT if register - * value didn't match, QDMA_SUCCESS other wise - */ -static int eqdma_cpm5_indirect_reg_read(void *dev_hndl, - enum ind_ctxt_cmd_sel sel, - uint16_t hw_qid, uint32_t cnt, uint32_t *data) -{ - uint32_t index = 0, reg_addr = EQDMA_CPM5_IND_CTXT_DATA_ADDR; - union qdma_ind_ctxt_cmd cmd; - - qdma_reg_access_lock(dev_hndl); - - /* set command register */ - cmd.word = 0; - cmd.bits.qid = hw_qid; - cmd.bits.op = QDMA_CTXT_CMD_RD; - cmd.bits.sel = sel; - - qdma_reg_write(dev_hndl, EQDMA_CPM5_IND_CTXT_CMD_ADDR, cmd.word); - - /* check if the operation went through well */ - if (hw_monitor_reg(dev_hndl, EQDMA_CPM5_IND_CTXT_CMD_ADDR, - IND_CTXT_CMD_BUSY_MASK, 0, - QDMA_REG_POLL_DFLT_INTERVAL_US, - QDMA_REG_POLL_DFLT_TIMEOUT_US)) { - qdma_reg_access_release(dev_hndl); - qdma_log_error("%s: hw_monitor_reg failed with err:%d\n", - __func__, - -QDMA_ERR_HWACC_BUSY_TIMEOUT); - return -QDMA_ERR_HWACC_BUSY_TIMEOUT; - } - - for (index = 0; index < cnt; index++, reg_addr += sizeof(uint32_t)) - data[index] = qdma_reg_read(dev_hndl, reg_addr); - - qdma_reg_access_release(dev_hndl); - - return QDMA_SUCCESS; -} - -/* - * eqdma_cpm5_indirect_reg_write() - helper function to write indirect - * context registers. - * - * return -QDMA_ERR_HWACC_BUSY_TIMEOUT if register - * value didn't match, QDMA_SUCCESS other wise - */ -static int eqdma_cpm5_indirect_reg_write(void *dev_hndl, - enum ind_ctxt_cmd_sel sel, - uint16_t hw_qid, uint32_t *data, uint16_t cnt) -{ - uint32_t index, reg_addr; - struct qdma_indirect_ctxt_regs regs; - uint32_t *wr_data = (uint32_t *)®s; - - qdma_reg_access_lock(dev_hndl); - - /* write the context data */ - for (index = 0; index < QDMA_IND_CTXT_DATA_NUM_REGS; index++) { - if (index < cnt) - regs.qdma_ind_ctxt_data[index] = data[index]; - else - regs.qdma_ind_ctxt_data[index] = 0; - regs.qdma_ind_ctxt_mask[index] = 0xFFFFFFFF; - } - - regs.cmd.word = 0; - regs.cmd.bits.qid = hw_qid; - regs.cmd.bits.op = QDMA_CTXT_CMD_WR; - regs.cmd.bits.sel = sel; - reg_addr = EQDMA_CPM5_IND_CTXT_DATA_ADDR; - - for (index = 0; index < ((2 * QDMA_IND_CTXT_DATA_NUM_REGS) + 1); - index++, reg_addr += sizeof(uint32_t)) - qdma_reg_write(dev_hndl, reg_addr, wr_data[index]); - - /* check if the operation went through well */ - if (hw_monitor_reg(dev_hndl, EQDMA_CPM5_IND_CTXT_CMD_ADDR, - IND_CTXT_CMD_BUSY_MASK, 0, - QDMA_REG_POLL_DFLT_INTERVAL_US, - QDMA_REG_POLL_DFLT_TIMEOUT_US)) { - qdma_reg_access_release(dev_hndl); - qdma_log_error("%s: hw_monitor_reg failed with err:%d\n", - __func__, - -QDMA_ERR_HWACC_BUSY_TIMEOUT); - return -QDMA_ERR_HWACC_BUSY_TIMEOUT; - } - - qdma_reg_access_release(dev_hndl); - - return QDMA_SUCCESS; -} - -/* - * eqdma_cpm5_fill_sw_ctxt() - Helper function to fill sw context into - * structure - * - */ -static void eqdma_cpm5_fill_sw_ctxt(struct qdma_descq_sw_ctxt *sw_ctxt) -{ - int i = 0; - - eqdma_cpm5_sw_ctxt_entries[i++].value = sw_ctxt->pidx; - eqdma_cpm5_sw_ctxt_entries[i++].value = sw_ctxt->irq_arm; - eqdma_cpm5_sw_ctxt_entries[i++].value = sw_ctxt->fnc_id; - eqdma_cpm5_sw_ctxt_entries[i++].value = sw_ctxt->qen; - eqdma_cpm5_sw_ctxt_entries[i++].value = sw_ctxt->frcd_en; - eqdma_cpm5_sw_ctxt_entries[i++].value = sw_ctxt->wbi_chk; - eqdma_cpm5_sw_ctxt_entries[i++].value = sw_ctxt->wbi_intvl_en; - eqdma_cpm5_sw_ctxt_entries[i++].value = sw_ctxt->at; - eqdma_cpm5_sw_ctxt_entries[i++].value = sw_ctxt->fetch_max; - eqdma_cpm5_sw_ctxt_entries[i++].value = sw_ctxt->rngsz_idx; - eqdma_cpm5_sw_ctxt_entries[i++].value = sw_ctxt->desc_sz; - eqdma_cpm5_sw_ctxt_entries[i++].value = sw_ctxt->bypass; - eqdma_cpm5_sw_ctxt_entries[i++].value = sw_ctxt->mm_chn; - eqdma_cpm5_sw_ctxt_entries[i++].value = sw_ctxt->wbk_en; - eqdma_cpm5_sw_ctxt_entries[i++].value = sw_ctxt->irq_en; - eqdma_cpm5_sw_ctxt_entries[i++].value = sw_ctxt->port_id; - eqdma_cpm5_sw_ctxt_entries[i++].value = sw_ctxt->irq_no_last; - eqdma_cpm5_sw_ctxt_entries[i++].value = sw_ctxt->err; - eqdma_cpm5_sw_ctxt_entries[i++].value = sw_ctxt->err_wb_sent; - eqdma_cpm5_sw_ctxt_entries[i++].value = sw_ctxt->irq_req; - eqdma_cpm5_sw_ctxt_entries[i++].value = sw_ctxt->mrkr_dis; - eqdma_cpm5_sw_ctxt_entries[i++].value = sw_ctxt->is_mm; - eqdma_cpm5_sw_ctxt_entries[i++].value = - sw_ctxt->ring_bs_addr & 0xFFFFFFFF; - eqdma_cpm5_sw_ctxt_entries[i++].value = - (sw_ctxt->ring_bs_addr >> 32) & 0xFFFFFFFF; - eqdma_cpm5_sw_ctxt_entries[i++].value = sw_ctxt->vec; - eqdma_cpm5_sw_ctxt_entries[i++].value = sw_ctxt->intr_aggr; - eqdma_cpm5_sw_ctxt_entries[i++].value = sw_ctxt->dis_intr_on_vf; - eqdma_cpm5_sw_ctxt_entries[i++].value = sw_ctxt->pack_byp_out; - eqdma_cpm5_sw_ctxt_entries[i++].value = sw_ctxt->irq_byp; - -} - -/* - * eqdma_cpm5_fill_cmpt_ctxt() - Helper function to fill completion context - * into structure - * - */ -static void eqdma_cpm5_fill_cmpt_ctxt(struct qdma_descq_cmpt_ctxt - *cmpt_ctxt) -{ - int i = 0; - - eqdma_cpm5_cmpt_ctxt_entries[i++].value = cmpt_ctxt->en_stat_desc; - eqdma_cpm5_cmpt_ctxt_entries[i++].value = cmpt_ctxt->en_int; - eqdma_cpm5_cmpt_ctxt_entries[i++].value = cmpt_ctxt->trig_mode; - eqdma_cpm5_cmpt_ctxt_entries[i++].value = cmpt_ctxt->fnc_id; - eqdma_cpm5_cmpt_ctxt_entries[i++].value = cmpt_ctxt->counter_idx; - eqdma_cpm5_cmpt_ctxt_entries[i++].value = cmpt_ctxt->timer_idx; - eqdma_cpm5_cmpt_ctxt_entries[i++].value = cmpt_ctxt->in_st; - eqdma_cpm5_cmpt_ctxt_entries[i++].value = cmpt_ctxt->color; - eqdma_cpm5_cmpt_ctxt_entries[i++].value = cmpt_ctxt->ringsz_idx; - eqdma_cpm5_cmpt_ctxt_entries[i++].value = (uint32_t)FIELD_GET( - EQDMA_CPM5_COMPL_CTXT_BADDR_HIGH_L_MASK, - cmpt_ctxt->bs_addr); - eqdma_cpm5_cmpt_ctxt_entries[i++].value = (uint32_t)FIELD_GET( - EQDMA_CPM5_COMPL_CTXT_BADDR_HIGH_H_MASK, - cmpt_ctxt->bs_addr); - eqdma_cpm5_cmpt_ctxt_entries[i++].value = cmpt_ctxt->desc_sz; - eqdma_cpm5_cmpt_ctxt_entries[i++].value = cmpt_ctxt->pidx; - eqdma_cpm5_cmpt_ctxt_entries[i++].value = cmpt_ctxt->cidx; - eqdma_cpm5_cmpt_ctxt_entries[i++].value = cmpt_ctxt->valid; - eqdma_cpm5_cmpt_ctxt_entries[i++].value = cmpt_ctxt->err; - eqdma_cpm5_cmpt_ctxt_entries[i++].value = cmpt_ctxt->user_trig_pend; - eqdma_cpm5_cmpt_ctxt_entries[i++].value = cmpt_ctxt->timer_running; - eqdma_cpm5_cmpt_ctxt_entries[i++].value = cmpt_ctxt->full_upd; - eqdma_cpm5_cmpt_ctxt_entries[i++].value = cmpt_ctxt->ovf_chk_dis; - eqdma_cpm5_cmpt_ctxt_entries[i++].value = cmpt_ctxt->at; - eqdma_cpm5_cmpt_ctxt_entries[i++].value = cmpt_ctxt->vec; - eqdma_cpm5_cmpt_ctxt_entries[i++].value = cmpt_ctxt->int_aggr; - eqdma_cpm5_cmpt_ctxt_entries[i++].value = cmpt_ctxt->dis_intr_on_vf; - eqdma_cpm5_cmpt_ctxt_entries[i++].value = cmpt_ctxt->dir_c2h; - eqdma_cpm5_cmpt_ctxt_entries[i++].value = (uint32_t)FIELD_GET( - EQDMA_CPM5_COMPL_CTXT_BADDR_LOW_MASK, - cmpt_ctxt->bs_addr); - eqdma_cpm5_cmpt_ctxt_entries[i++].value = cmpt_ctxt->sh_cmpt; -} - -/* - * eqdma_cpm5_fill_hw_ctxt() - Helper function to fill HW context into - * structure - * - */ -static void eqdma_cpm5_fill_hw_ctxt(struct qdma_descq_hw_ctxt *hw_ctxt) -{ - int i = 0; - - eqdma_cpm5_hw_ctxt_entries[i++].value = hw_ctxt->cidx; - eqdma_cpm5_hw_ctxt_entries[i++].value = hw_ctxt->crd_use; - eqdma_cpm5_hw_ctxt_entries[i++].value = hw_ctxt->dsc_pend; - eqdma_cpm5_hw_ctxt_entries[i++].value = hw_ctxt->idl_stp_b; - eqdma_cpm5_hw_ctxt_entries[i++].value = hw_ctxt->evt_pnd; - eqdma_cpm5_hw_ctxt_entries[i++].value = hw_ctxt->fetch_pnd; -} - -/* - * eqdma_cpm5_fill_credit_ctxt() - Helper function to fill Credit context - * into structure - * - */ -static void eqdma_cpm5_fill_credit_ctxt(struct qdma_descq_credit_ctxt - *cr_ctxt) -{ - eqdma_cpm5_credit_ctxt_entries[0].value = cr_ctxt->credit; -} - -/* - * eqdma_cpm5_fill_pfetch_ctxt() - Helper function to fill Prefetch context - * into structure - * - */ -static void eqdma_cpm5_fill_pfetch_ctxt(struct qdma_descq_prefetch_ctxt - *pfetch_ctxt) -{ - int i = 0; - - eqdma_cpm5_c2h_pftch_ctxt_entries[i++].value = pfetch_ctxt->bypass; - eqdma_cpm5_c2h_pftch_ctxt_entries[i++].value = - pfetch_ctxt->bufsz_idx; - eqdma_cpm5_c2h_pftch_ctxt_entries[i++].value = pfetch_ctxt->port_id; - eqdma_cpm5_c2h_pftch_ctxt_entries[i++].value = - pfetch_ctxt->var_desc; - eqdma_cpm5_c2h_pftch_ctxt_entries[i++].value = - pfetch_ctxt->num_pftch; - eqdma_cpm5_c2h_pftch_ctxt_entries[i++].value = pfetch_ctxt->err; - eqdma_cpm5_c2h_pftch_ctxt_entries[i++].value = pfetch_ctxt->pfch_en; - eqdma_cpm5_c2h_pftch_ctxt_entries[i++].value = pfetch_ctxt->pfch; - eqdma_cpm5_c2h_pftch_ctxt_entries[i++].value = pfetch_ctxt->sw_crdt; - eqdma_cpm5_c2h_pftch_ctxt_entries[i++].value = pfetch_ctxt->valid; -} - -/* - * eqdma_cpm5_fill_fmap_ctxt() - Helper function to fill fmap context - * into structure - * - */ -static void eqdma_cpm5_fill_fmap_ctxt(struct qdma_fmap_cfg *fmap_ctxt) -{ - eqdma_cpm5_fmap_ctxt_entries[0].value = fmap_ctxt->qbase; - eqdma_cpm5_fmap_ctxt_entries[1].value = fmap_ctxt->qmax; -} - -/* - * eqdma_cpm5_fill_intr_ctxt() - Helper function to fill interrupt context - * into structure - * - */ -static void eqdma_cpm5_fill_intr_ctxt(struct qdma_indirect_intr_ctxt - *intr_ctxt) -{ - int i = 0; - - eqdma_cpm5_ind_intr_ctxt_entries[i++].value = intr_ctxt->valid; - eqdma_cpm5_ind_intr_ctxt_entries[i++].value = intr_ctxt->vec; - eqdma_cpm5_ind_intr_ctxt_entries[i++].value = intr_ctxt->int_st; - eqdma_cpm5_ind_intr_ctxt_entries[i++].value = intr_ctxt->color; - eqdma_cpm5_ind_intr_ctxt_entries[i++].value = - intr_ctxt->baddr_4k & 0xFFFFFFFF; - eqdma_cpm5_ind_intr_ctxt_entries[i++].value = - (intr_ctxt->baddr_4k >> 32) & 0xFFFFFFFF; - eqdma_cpm5_ind_intr_ctxt_entries[i++].value = intr_ctxt->page_size; - eqdma_cpm5_ind_intr_ctxt_entries[i++].value = intr_ctxt->pidx; - eqdma_cpm5_ind_intr_ctxt_entries[i++].value = intr_ctxt->at; - eqdma_cpm5_ind_intr_ctxt_entries[i++].value = intr_ctxt->func_id; -} - -/*****************************************************************************/ -/** - * eqdma_cpm5_set_default_global_csr() - function to set the global CSR - * register to default values. The value can be modified later by using the - * set/get csr functions - * - * @dev_hndl: device handle - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -int eqdma_cpm5_set_default_global_csr(void *dev_hndl) -{ - /* Default values */ - uint32_t reg_val = 0; - uint32_t rng_sz[QDMA_NUM_RING_SIZES] = {2049, 65, 129, 193, 257, 385, - 513, 769, 1025, 1537, 3073, 4097, 6145, 8193, 12289, 16385}; - uint32_t tmr_cnt[QDMA_NUM_C2H_TIMERS] = {1, 2, 4, 5, 8, 10, 15, 20, 25, - 30, 50, 75, 100, 125, 150, 200}; - uint32_t cnt_th[QDMA_NUM_C2H_COUNTERS] = {2, 4, 8, 16, 24, 32, 48, 64, - 80, 96, 112, 128, 144, 160, 176, 192}; - uint32_t buf_sz[QDMA_NUM_C2H_BUFFER_SIZES] = {4096, 256, 512, 1024, - 2048, 3968, 4096, 4096, 4096, 4096, 4096, 4096, 4096, 8192, - 9018, 16384}; - struct qdma_dev_attributes dev_cap; - - if (!dev_hndl) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", __func__, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - eqdma_cpm5_get_device_attributes(dev_hndl, &dev_cap); - - /* Configuring CSR registers */ - /* Global ring sizes */ - qdma_write_csr_values(dev_hndl, EQDMA_CPM5_GLBL_RNG_SZ_1_ADDR, 0, - QDMA_NUM_RING_SIZES, rng_sz); - - if (dev_cap.st_en || dev_cap.mm_cmpt_en) { - /* Counter thresholds */ - qdma_write_csr_values(dev_hndl, EQDMA_CPM5_C2H_CNT_TH_ADDR, - 0, QDMA_NUM_C2H_COUNTERS, cnt_th); - - /* Timer Counters */ - qdma_write_csr_values(dev_hndl, - EQDMA_CPM5_C2H_TIMER_CNT_ADDR, 0, - QDMA_NUM_C2H_TIMERS, tmr_cnt); - - - /* Writeback Interval */ - reg_val = - FIELD_SET(GLBL_DSC_CFG_MAXFETCH_MASK, - DEFAULT_MAX_DSC_FETCH) | - FIELD_SET(GLBL_DSC_CFG_WB_ACC_INT_MASK, - DEFAULT_WRB_INT); - qdma_reg_write(dev_hndl, EQDMA_CPM5_GLBL_DSC_CFG_ADDR, - reg_val); - } - - if (dev_cap.st_en) { - /* Buffer Sizes */ - qdma_write_csr_values(dev_hndl, EQDMA_CPM5_C2H_BUF_SZ_ADDR, - 0, QDMA_NUM_C2H_BUFFER_SIZES, buf_sz); - - /* C2h Completion Coalesce Configuration */ - reg_val = - FIELD_SET(C2H_WRB_COAL_CFG_TICK_CNT_MASK, - DEFAULT_CMPT_COAL_TIMER_CNT) | - FIELD_SET(C2H_WRB_COAL_CFG_TICK_VAL_MASK, - DEFAULT_CMPT_COAL_TIMER_TICK) | - FIELD_SET(C2H_WRB_COAL_CFG_MAX_BUF_SZ_MASK, - EQDMA_CPM5_DEFAULT_CMPT_COAL_MAX_BUF_SZ); - qdma_reg_write(dev_hndl, EQDMA_CPM5_C2H_WRB_COAL_CFG_ADDR, - reg_val); - } - - eqdma_cpm5_set_perf_opt(dev_hndl); - return QDMA_SUCCESS; -} - -/* - * dump_eqdma_cpm5_context() - Helper function to dump queue context into - * string - * - * return len - length of the string copied into buffer - */ -static int dump_eqdma_cpm5_context(struct qdma_descq_context *queue_context, - uint8_t st, enum qdma_dev_q_type q_type, - char *buf, int buf_sz) -{ - int i = 0; - int n; - int len = 0; - int rv; - char banner[DEBGFS_LINE_SZ] = ""; - - if (queue_context == NULL) { - qdma_log_error("%s: queue_context is NULL, err:%d\n", - __func__, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - if (q_type == QDMA_DEV_Q_TYPE_CMPT) { - eqdma_cpm5_fill_cmpt_ctxt(&queue_context->cmpt_ctxt); - } else if (q_type == QDMA_DEV_Q_TYPE_H2C) { - eqdma_cpm5_fill_sw_ctxt(&queue_context->sw_ctxt); - eqdma_cpm5_fill_hw_ctxt(&queue_context->hw_ctxt); - eqdma_cpm5_fill_credit_ctxt(&queue_context->cr_ctxt); - } else if (q_type == QDMA_DEV_Q_TYPE_C2H) { - eqdma_cpm5_fill_sw_ctxt(&queue_context->sw_ctxt); - eqdma_cpm5_fill_hw_ctxt(&queue_context->hw_ctxt); - eqdma_cpm5_fill_credit_ctxt(&queue_context->cr_ctxt); - if (st) { - eqdma_cpm5_fill_pfetch_ctxt( - &queue_context->pfetch_ctxt); - eqdma_cpm5_fill_cmpt_ctxt( - &queue_context->cmpt_ctxt); - } - } - - eqdma_cpm5_fill_fmap_ctxt(&queue_context->fmap); - - if (q_type != QDMA_DEV_Q_TYPE_CMPT) { - for (i = 0; i < DEBGFS_LINE_SZ - 5; i++) { - rv = QDMA_SNPRINTF_S(banner + i, - (DEBGFS_LINE_SZ - i), - sizeof("-"), "-"); - if ((rv < 0) || (rv > (int)sizeof("-"))) { - qdma_log_error( - "%d:%s QDMA_SNPRINTF_S() failed, err:%d\n", - __LINE__, __func__, rv); - goto INSUF_BUF_EXIT; - } - } - - /* SW context dump */ - n = sizeof(eqdma_cpm5_sw_ctxt_entries) / - sizeof((eqdma_cpm5_sw_ctxt_entries)[0]); - for (i = 0; i < n; i++) { - if ((len >= buf_sz) || - ((len + DEBGFS_LINE_SZ) >= buf_sz)) - goto INSUF_BUF_EXIT; - - if (i == 0) { - if ((len + (3 * DEBGFS_LINE_SZ)) >= buf_sz) - goto INSUF_BUF_EXIT; - rv = QDMA_SNPRINTF_S(buf + len, (buf_sz - len), - DEBGFS_LINE_SZ, "\n%s", banner); - if ((rv < 0) || (rv > DEBGFS_LINE_SZ)) { - qdma_log_error( - "%d:%s QDMA_SNPRINTF_S() failed, err:%d\n", - __LINE__, __func__, - rv); - goto INSUF_BUF_EXIT; - } - len += rv; - - rv = QDMA_SNPRINTF_S(buf + len, (buf_sz - len), - DEBGFS_LINE_SZ, "\n%40s", "SW Context"); - if ((rv < 0) || (rv > DEBGFS_LINE_SZ)) { - qdma_log_error( - "%d:%s QDMA_SNPRINTF_S() failed, err:%d\n", - __LINE__, __func__, - rv); - goto INSUF_BUF_EXIT; - } - len += rv; - - rv = QDMA_SNPRINTF_S(buf + len, (buf_sz - len), - DEBGFS_LINE_SZ, "\n%s\n", banner); - if ((rv < 0) || (rv > DEBGFS_LINE_SZ)) { - qdma_log_error( - "%d:%s QDMA_SNPRINTF_S() failed, err:%d\n", - __LINE__, __func__, - rv); - goto INSUF_BUF_EXIT; - } - len += rv; - } - - rv = QDMA_SNPRINTF_S(buf + len, (buf_sz - len), - DEBGFS_LINE_SZ, - "%-47s %#-10x %u\n", - eqdma_cpm5_sw_ctxt_entries[i].name, - eqdma_cpm5_sw_ctxt_entries[i].value, - eqdma_cpm5_sw_ctxt_entries[i].value); - if ((rv < 0) || (rv > DEBGFS_LINE_SZ)) { - qdma_log_error( - "%d:%s QDMA_SNPRINTF_S() failed, err:%d\n", - __LINE__, __func__, - rv); - goto INSUF_BUF_EXIT; - } - len += rv; - } - - /* HW context dump */ - n = sizeof(eqdma_cpm5_hw_ctxt_entries) / - sizeof((eqdma_cpm5_hw_ctxt_entries)[0]); - for (i = 0; i < n; i++) { - if ((len >= buf_sz) || - ((len + DEBGFS_LINE_SZ) >= buf_sz)) - goto INSUF_BUF_EXIT; - - if (i == 0) { - if ((len + (3 * DEBGFS_LINE_SZ)) >= buf_sz) - goto INSUF_BUF_EXIT; - - rv = QDMA_SNPRINTF_S(buf + len, (buf_sz - len), - DEBGFS_LINE_SZ, "\n%s", banner); - if ((rv < 0) || (rv > DEBGFS_LINE_SZ)) { - qdma_log_error( - "%d:%s QDMA_SNPRINTF_S() failed, err:%d\n", - __LINE__, __func__, - rv); - goto INSUF_BUF_EXIT; - } - len += rv; - - rv = QDMA_SNPRINTF_S(buf + len, (buf_sz - len), - DEBGFS_LINE_SZ, "\n%40s", "HW Context"); - if ((rv < 0) || (rv > DEBGFS_LINE_SZ)) { - qdma_log_error( - "%d:%s QDMA_SNPRINTF_S() failed, err:%d\n", - __LINE__, __func__, - rv); - goto INSUF_BUF_EXIT; - } - len += rv; - - rv = QDMA_SNPRINTF_S(buf + len, (buf_sz - len), - DEBGFS_LINE_SZ, "\n%s\n", banner); - if ((rv < 0) || (rv > DEBGFS_LINE_SZ)) { - qdma_log_error( - "%d:%s QDMA_SNPRINTF_S() failed, err:%d\n", - __LINE__, __func__, - rv); - goto INSUF_BUF_EXIT; - } - len += rv; - } - - rv = QDMA_SNPRINTF_S(buf + len, (buf_sz - len), - DEBGFS_LINE_SZ, - "%-47s %#-10x %u\n", - eqdma_cpm5_hw_ctxt_entries[i].name, - eqdma_cpm5_hw_ctxt_entries[i].value, - eqdma_cpm5_hw_ctxt_entries[i].value); - if ((rv < 0) || (rv > DEBGFS_LINE_SZ)) { - qdma_log_error( - "%d:%s QDMA_SNPRINTF_S() failed, err:%d\n", - __LINE__, __func__, - rv); - goto INSUF_BUF_EXIT; - } - len += rv; - } - - /* Credit context dump */ - n = sizeof(eqdma_cpm5_credit_ctxt_entries) / - sizeof((eqdma_cpm5_credit_ctxt_entries)[0]); - for (i = 0; i < n; i++) { - if ((len >= buf_sz) || - ((len + DEBGFS_LINE_SZ) >= buf_sz)) - goto INSUF_BUF_EXIT; - - if (i == 0) { - if ((len + (3 * DEBGFS_LINE_SZ)) >= buf_sz) - goto INSUF_BUF_EXIT; - - rv = QDMA_SNPRINTF_S(buf + len, (buf_sz - len), - DEBGFS_LINE_SZ, "\n%s", banner); - if ((rv < 0) || (rv > DEBGFS_LINE_SZ)) { - qdma_log_error( - "%d:%s QDMA_SNPRINTF_S() failed, err:%d\n", - __LINE__, __func__, - rv); - goto INSUF_BUF_EXIT; - } - len += rv; - - rv = QDMA_SNPRINTF_S(buf + len, (buf_sz - len), - DEBGFS_LINE_SZ, "\n%40s", - "Credit Context"); - if ((rv < 0) || (rv > DEBGFS_LINE_SZ)) { - qdma_log_error( - "%d:%s QDMA_SNPRINTF_S() failed, err:%d\n", - __LINE__, __func__, - rv); - goto INSUF_BUF_EXIT; - } - len += rv; - - rv = QDMA_SNPRINTF_S(buf + len, (buf_sz - len), - DEBGFS_LINE_SZ, "\n%s\n", banner); - if ((rv < 0) || (rv > DEBGFS_LINE_SZ)) { - qdma_log_error( - "%d:%s QDMA_SNPRINTF_S() failed, err:%d\n", - __LINE__, __func__, - rv); - goto INSUF_BUF_EXIT; - } - len += rv; - } - - rv = QDMA_SNPRINTF_S(buf + len, (buf_sz - len), - DEBGFS_LINE_SZ, - "%-47s %#-10x %u\n", - eqdma_cpm5_credit_ctxt_entries[i].name, - eqdma_cpm5_credit_ctxt_entries[i].value, - eqdma_cpm5_credit_ctxt_entries[i].value); - if ((rv < 0) || (rv > DEBGFS_LINE_SZ)) { - qdma_log_error( - "%d:%s QDMA_SNPRINTF_S() failed, err:%d\n", - __LINE__, __func__, - rv); - goto INSUF_BUF_EXIT; - } - len += rv; - } - } - - if ((q_type == QDMA_DEV_Q_TYPE_CMPT) || - (st && q_type == QDMA_DEV_Q_TYPE_C2H)) { - /* Completion context dump */ - n = sizeof(eqdma_cpm5_cmpt_ctxt_entries) / - sizeof((eqdma_cpm5_cmpt_ctxt_entries)[0]); - for (i = 0; i < n; i++) { - if ((len >= buf_sz) || - ((len + DEBGFS_LINE_SZ) >= buf_sz)) - goto INSUF_BUF_EXIT; - - if (i == 0) { - if ((len + (3 * DEBGFS_LINE_SZ)) >= buf_sz) - goto INSUF_BUF_EXIT; - - rv = QDMA_SNPRINTF_S(buf + len, (buf_sz - len), - DEBGFS_LINE_SZ, "\n%s", banner); - if ((rv < 0) || (rv > DEBGFS_LINE_SZ)) { - qdma_log_error( - "%d:%s QDMA_SNPRINTF_S() failed, err:%d\n", - __LINE__, __func__, - rv); - goto INSUF_BUF_EXIT; - } - len += rv; - - rv = QDMA_SNPRINTF_S(buf + len, (buf_sz - len), - DEBGFS_LINE_SZ, "\n%40s", - "Completion Context"); - if ((rv < 0) || (rv > DEBGFS_LINE_SZ)) { - qdma_log_error( - "%d:%s QDMA_SNPRINTF_S() failed, err:%d\n", - __LINE__, __func__, - rv); - goto INSUF_BUF_EXIT; - } - len += rv; - - rv = QDMA_SNPRINTF_S(buf + len, (buf_sz - len), - DEBGFS_LINE_SZ, "\n%s\n", banner); - if ((rv < 0) || (rv > DEBGFS_LINE_SZ)) { - qdma_log_error( - "%d:%s QDMA_SNPRINTF_S() failed, err:%d\n", - __LINE__, __func__, - rv); - goto INSUF_BUF_EXIT; - } - len += rv; - } - - rv = QDMA_SNPRINTF_S(buf + len, (buf_sz - len), - DEBGFS_LINE_SZ, - "%-47s %#-10x %u\n", - eqdma_cpm5_cmpt_ctxt_entries[i].name, - eqdma_cpm5_cmpt_ctxt_entries[i].value, - eqdma_cpm5_cmpt_ctxt_entries[i].value); - if ((rv < 0) || (rv > DEBGFS_LINE_SZ)) { - qdma_log_error( - "%d:%s QDMA_SNPRINTF_S() failed, err:%d\n", - __LINE__, __func__, - rv); - goto INSUF_BUF_EXIT; - } - len += rv; - } - } - - if (st && q_type == QDMA_DEV_Q_TYPE_C2H) { - /* Prefetch context dump */ - n = sizeof(eqdma_cpm5_c2h_pftch_ctxt_entries) / - sizeof(eqdma_cpm5_c2h_pftch_ctxt_entries[0]); - for (i = 0; i < n; i++) { - if ((len >= buf_sz) || - ((len + DEBGFS_LINE_SZ) >= buf_sz)) - goto INSUF_BUF_EXIT; - - if (i == 0) { - if ((len + (3 * DEBGFS_LINE_SZ)) >= buf_sz) - goto INSUF_BUF_EXIT; - - rv = QDMA_SNPRINTF_S(buf + len, (buf_sz - len), - DEBGFS_LINE_SZ, "\n%s", banner); - if ((rv < 0) || (rv > DEBGFS_LINE_SZ)) { - qdma_log_error( - "%d:%s QDMA_SNPRINTF_S() failed, err:%d\n", - __LINE__, __func__, - rv); - goto INSUF_BUF_EXIT; - } - len += rv; - - rv = QDMA_SNPRINTF_S(buf + len, (buf_sz - len), - DEBGFS_LINE_SZ, "\n%40s", - "Prefetch Context"); - if ((rv < 0) || (rv > DEBGFS_LINE_SZ)) { - qdma_log_error( - "%d:%s QDMA_SNPRINTF_S() failed, err:%d\n", - __LINE__, __func__, - rv); - goto INSUF_BUF_EXIT; - } - len += rv; - - rv = QDMA_SNPRINTF_S(buf + len, (buf_sz - len), - DEBGFS_LINE_SZ, "\n%s\n", banner); - if ((rv < 0) || (rv > DEBGFS_LINE_SZ)) { - qdma_log_error( - "%d:%s QDMA_SNPRINTF_S() failed, err:%d\n", - __LINE__, __func__, - rv); - goto INSUF_BUF_EXIT; - } - len += rv; - } - - rv = QDMA_SNPRINTF_S(buf + len, (buf_sz - len), - DEBGFS_LINE_SZ, - "%-47s %#-10x %u\n", - eqdma_cpm5_c2h_pftch_ctxt_entries[i].name, - eqdma_cpm5_c2h_pftch_ctxt_entries[i].value, - eqdma_cpm5_c2h_pftch_ctxt_entries[i].value); - if ((rv < 0) || (rv > DEBGFS_LINE_SZ)) { - qdma_log_error( - "%d:%s QDMA_SNPRINTF_S() failed, err:%d\n", - __LINE__, __func__, - rv); - goto INSUF_BUF_EXIT; - } - len += rv; - } - } - - /* Fmap context dump */ - n = sizeof(eqdma_cpm5_fmap_ctxt_entries) / - sizeof(eqdma_cpm5_fmap_ctxt_entries[0]); - for (i = 0; i < n; i++) { - if ((len >= buf_sz) || - ((len + DEBGFS_LINE_SZ) >= buf_sz)) - goto INSUF_BUF_EXIT; - - if (i == 0) { - if ((len + (3 * DEBGFS_LINE_SZ)) >= buf_sz) - goto INSUF_BUF_EXIT; - - rv = QDMA_SNPRINTF_S(buf + len, (buf_sz - len), - DEBGFS_LINE_SZ, "\n%s", banner); - if ((rv < 0) || (rv > DEBGFS_LINE_SZ)) { - qdma_log_error( - "%d:%s QDMA_SNPRINTF_S() failed, err:%d\n", - __LINE__, __func__, - rv); - goto INSUF_BUF_EXIT; - } - len += rv; - - rv = QDMA_SNPRINTF_S(buf + len, (buf_sz - len), - DEBGFS_LINE_SZ, "\n%40s", - "Fmap Context"); - if ((rv < 0) || (rv > DEBGFS_LINE_SZ)) { - qdma_log_error( - "%d:%s QDMA_SNPRINTF_S() failed, err:%d\n", - __LINE__, __func__, - rv); - goto INSUF_BUF_EXIT; - } - len += rv; - - rv = QDMA_SNPRINTF_S(buf + len, (buf_sz - len), - DEBGFS_LINE_SZ, "\n%s\n", banner); - if ((rv < 0) || (rv > DEBGFS_LINE_SZ)) { - qdma_log_error( - "%d:%s QDMA_SNPRINTF_S() failed, err:%d\n", - __LINE__, __func__, - rv); - goto INSUF_BUF_EXIT; - } - len += rv; - } - - rv = QDMA_SNPRINTF_S(buf + len, - (buf_sz - len), DEBGFS_LINE_SZ, - "%-47s %#-10x %u\n", - eqdma_cpm5_fmap_ctxt_entries[i].name, - eqdma_cpm5_fmap_ctxt_entries[i].value, - eqdma_cpm5_fmap_ctxt_entries[i].value); - if ((rv < 0) || (rv > DEBGFS_LINE_SZ)) { - qdma_log_error( - "%d:%s QDMA_SNPRINTF_S() failed, err:%d\n", - __LINE__, __func__, - rv); - goto INSUF_BUF_EXIT; - } - len += rv; - } - - return len; - -INSUF_BUF_EXIT: - if (buf_sz > DEBGFS_LINE_SZ) { - rv = QDMA_SNPRINTF_S((buf + buf_sz - DEBGFS_LINE_SZ), - buf_sz, DEBGFS_LINE_SZ, - "\n\nInsufficient buffer size, partial context dump\n"); - if ((rv < 0) || (rv > DEBGFS_LINE_SZ)) { - qdma_log_error( - "%d:%s QDMA_SNPRINTF_S() failed, err:%d\n", - __LINE__, __func__, - rv); - } - } - - qdma_log_error("%s: Insufficient buffer size, err:%d\n", - __func__, -QDMA_ERR_NO_MEM); - - return -QDMA_ERR_NO_MEM; -} - -/* - * dump_eqdma_cpm5_intr_context() - Helper function to dump interrupt - * context into string - * - * return len - length of the string copied into buffer - */ -static int dump_eqdma_cpm5_intr_context(struct qdma_indirect_intr_ctxt - *intr_ctx, - int ring_index, - char *buf, int buf_sz) -{ - int i = 0; - int n; - int len = 0; - int rv; - char banner[DEBGFS_LINE_SZ] = ""; - - eqdma_cpm5_fill_intr_ctxt(intr_ctx); - - for (i = 0; i < DEBGFS_LINE_SZ - 5; i++) { - rv = QDMA_SNPRINTF_S(banner + i, - (DEBGFS_LINE_SZ - i), - sizeof("-"), "-"); - if ((rv < 0) || (rv > (int)sizeof("-"))) { - qdma_log_error( - "%d:%s QDMA_SNPRINTF_S() failed, err:%d\n", - __LINE__, __func__, - rv); - goto INSUF_BUF_EXIT; - } - } - - /* Interrupt context dump */ - n = sizeof(eqdma_cpm5_ind_intr_ctxt_entries) / - sizeof((eqdma_cpm5_ind_intr_ctxt_entries)[0]); - for (i = 0; i < n; i++) { - if ((len >= buf_sz) || ((len + DEBGFS_LINE_SZ) >= buf_sz)) - goto INSUF_BUF_EXIT; - - if (i == 0) { - if ((len + (3 * DEBGFS_LINE_SZ)) >= buf_sz) - goto INSUF_BUF_EXIT; - - rv = QDMA_SNPRINTF_S(buf + len, (buf_sz - len), - DEBGFS_LINE_SZ, "\n%s", banner); - if ((rv < 0) || (rv > DEBGFS_LINE_SZ)) { - qdma_log_error( - "%d:%s QDMA_SNPRINTF_S() failed, err:%d\n", - __LINE__, __func__, - rv); - goto INSUF_BUF_EXIT; - } - len += rv; - - rv = QDMA_SNPRINTF_S(buf + len, (buf_sz - len), - DEBGFS_LINE_SZ, "\n%50s %d", - "Interrupt Context for ring#", ring_index); - if ((rv < 0) || (rv > DEBGFS_LINE_SZ)) { - qdma_log_error( - "%d:%s QDMA_SNPRINTF_S() failed, err:%d\n", - __LINE__, __func__, - rv); - goto INSUF_BUF_EXIT; - } - len += rv; - - rv = QDMA_SNPRINTF_S(buf + len, (buf_sz - len), - DEBGFS_LINE_SZ, "\n%s\n", banner); - if ((rv < 0) || (rv > DEBGFS_LINE_SZ)) { - qdma_log_error( - "%d:%s QDMA_SNPRINTF_S() failed, err:%d\n", - __LINE__, __func__, - rv); - goto INSUF_BUF_EXIT; - } - len += rv; - } - - rv = QDMA_SNPRINTF_S(buf + len, (buf_sz - len), DEBGFS_LINE_SZ, - "%-47s %#-10x %u\n", - eqdma_cpm5_ind_intr_ctxt_entries[i].name, - eqdma_cpm5_ind_intr_ctxt_entries[i].value, - eqdma_cpm5_ind_intr_ctxt_entries[i].value); - if ((rv < 0) || (rv > DEBGFS_LINE_SZ)) { - qdma_log_error( - "%d:%s QDMA_SNPRINTF_S() failed, err:%d\n", - __LINE__, __func__, - rv); - goto INSUF_BUF_EXIT; - } - len += rv; - } - - return len; - -INSUF_BUF_EXIT: - if (buf_sz > DEBGFS_LINE_SZ) { - rv = QDMA_SNPRINTF_S((buf + buf_sz - DEBGFS_LINE_SZ), - buf_sz, DEBGFS_LINE_SZ, - "\n\nInsufficient buffer size, partial context dump\n"); - if ((rv < 0) || (rv > DEBGFS_LINE_SZ)) { - qdma_log_error( - "%d:%s QDMA_SNPRINTF_S() failed, err:%d\n", - __LINE__, __func__, - rv); - } - } - - qdma_log_error("%s: Insufficient buffer size, err:%d\n", - __func__, -QDMA_ERR_NO_MEM); - - return -QDMA_ERR_NO_MEM; -} - -/*****************************************************************************/ -/** - * eqdma_cpm5_get_version() - Function to get the eqdma version - * - * @dev_hndl: device handle - * @is_vf: Whether PF or VF - * @version_info: pointer to hold the version info - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -int eqdma_cpm5_get_version(void *dev_hndl, uint8_t is_vf, - struct qdma_hw_version_info *version_info) -{ - uint32_t reg_val = 0; - uint32_t reg_addr = (is_vf) ? EQDMA_CPM5_OFFSET_VF_VERSION : - EQDMA_CPM5_GLBL2_MISC_CAP_ADDR; - - if (!dev_hndl) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - reg_val = qdma_reg_read(dev_hndl, reg_addr); - - qdma_fetch_version_details(dev_hndl, is_vf, reg_val, version_info); - - return QDMA_SUCCESS; -} - -/*****************************************************************************/ -/** - * eqdma_cpm5_sw_context_write() - create sw context and program it - * - * @dev_hndl: device handle - * @c2h: is c2h queue - * @hw_qid: hardware qid of the queue - * @ctxt: pointer to the SW context data strucutre - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -static int eqdma_cpm5_sw_context_write(void *dev_hndl, uint8_t c2h, - uint16_t hw_qid, - const struct qdma_descq_sw_ctxt *ctxt) -{ - uint32_t sw_ctxt[EQDMA_CPM5_SW_CONTEXT_NUM_WORDS] = {0}; - uint16_t num_words_count = 0; - uint32_t pasid_l, pasid_h; - uint32_t virtio_desc_base_l, virtio_desc_base_m, virtio_desc_base_h; - enum ind_ctxt_cmd_sel sel = c2h ? - QDMA_CTXT_SEL_SW_C2H : QDMA_CTXT_SEL_SW_H2C; - - /* Input args check */ - if (!dev_hndl || !ctxt) { - qdma_log_error("%s: dev_handle=%p sw_ctxt=%p NULL, err:%d\n", - __func__, dev_hndl, ctxt, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - pasid_l = - FIELD_GET(EQDMA_CPM5_SW_CTXT_PASID_GET_L_MASK, ctxt->pasid); - pasid_h = - FIELD_GET(EQDMA_CPM5_SW_CTXT_PASID_GET_H_MASK, ctxt->pasid); - - virtio_desc_base_l = (uint32_t)FIELD_GET( - EQDMA_CPM5_SW_CTXT_VIRTIO_DSC_BASE_GET_L_MASK, - ctxt->virtio_dsc_base); - virtio_desc_base_m = (uint32_t)FIELD_GET( - EQDMA_CPM5_SW_CTXT_VIRTIO_DSC_BASE_GET_M_MASK, - ctxt->virtio_dsc_base); - virtio_desc_base_h = (uint32_t)FIELD_GET( - EQDMA_CPM5_SW_CTXT_VIRTIO_DSC_BASE_GET_H_MASK, - ctxt->virtio_dsc_base); - - sw_ctxt[num_words_count++] = - FIELD_SET(SW_IND_CTXT_DATA_W0_PIDX_MASK, ctxt->pidx) | - FIELD_SET(SW_IND_CTXT_DATA_W0_IRQ_ARM_MASK, ctxt->irq_arm) | - FIELD_SET(SW_IND_CTXT_DATA_W0_FNC_MASK, ctxt->fnc_id); - - qdma_log_debug("%s: pidx=%x, irq_arm=%x, fnc_id=%x\n", - __func__, ctxt->pidx, ctxt->irq_arm, ctxt->fnc_id); - - sw_ctxt[num_words_count++] = - FIELD_SET(SW_IND_CTXT_DATA_W1_QEN_MASK, ctxt->qen) | - FIELD_SET(SW_IND_CTXT_DATA_W1_FCRD_EN_MASK, ctxt->frcd_en) | - FIELD_SET(SW_IND_CTXT_DATA_W1_WBI_CHK_MASK, ctxt->wbi_chk) | - FIELD_SET(SW_IND_CTXT_DATA_W1_WBI_INTVL_EN_MASK, - ctxt->wbi_intvl_en) | - FIELD_SET(SW_IND_CTXT_DATA_W1_AT_MASK, ctxt->at) | - FIELD_SET(SW_IND_CTXT_DATA_W1_FETCH_MAX_MASK, ctxt->fetch_max) | - FIELD_SET(SW_IND_CTXT_DATA_W1_RNG_SZ_MASK, ctxt->rngsz_idx) | - FIELD_SET(SW_IND_CTXT_DATA_W1_DSC_SZ_MASK, ctxt->desc_sz) | - FIELD_SET(SW_IND_CTXT_DATA_W1_BYPASS_MASK, ctxt->bypass) | - FIELD_SET(SW_IND_CTXT_DATA_W1_MM_CHN_MASK, ctxt->mm_chn) | - FIELD_SET(SW_IND_CTXT_DATA_W1_WBK_EN_MASK, ctxt->wbk_en) | - FIELD_SET(SW_IND_CTXT_DATA_W1_IRQ_EN_MASK, ctxt->irq_en) | - FIELD_SET(SW_IND_CTXT_DATA_W1_PORT_ID_MASK, ctxt->port_id) | - FIELD_SET(SW_IND_CTXT_DATA_W1_IRQ_NO_LAST_MASK, - ctxt->irq_no_last) | - FIELD_SET(SW_IND_CTXT_DATA_W1_ERR_MASK, ctxt->err) | - FIELD_SET(SW_IND_CTXT_DATA_W1_ERR_WB_SENT_MASK, - ctxt->err_wb_sent) | - FIELD_SET(SW_IND_CTXT_DATA_W1_IRQ_REQ_MASK, ctxt->irq_req) | - FIELD_SET(SW_IND_CTXT_DATA_W1_MRKR_DIS_MASK, ctxt->mrkr_dis) | - FIELD_SET(SW_IND_CTXT_DATA_W1_IS_MM_MASK, ctxt->is_mm); - - qdma_log_debug("%s: qen=%x, frcd_en=%x, wbi_chk=%x, wbi_intvl_en=%x\n", - __func__, ctxt->qen, ctxt->frcd_en, ctxt->wbi_chk, - ctxt->wbi_intvl_en); - - qdma_log_debug("%s: at=%x, fetch_max=%x, rngsz_idx=%x, desc_sz=%x\n", - __func__, ctxt->at, ctxt->fetch_max, ctxt->rngsz_idx, - ctxt->desc_sz); - - qdma_log_debug("%s: bypass=%x, mm_chn=%x, wbk_en=%x, irq_en=%x\n", - __func__, ctxt->bypass, ctxt->mm_chn, ctxt->wbk_en, - ctxt->irq_en); - - qdma_log_debug("%s: port_id=%x, irq_no_last=%x,err=%x", - __func__, ctxt->port_id, ctxt->irq_no_last, ctxt->err); - qdma_log_debug(", err_wb_sent=%x\n", ctxt->err_wb_sent); - - qdma_log_debug("%s: irq_req=%x, mrkr_dis=%x, is_mm=%x\n", - __func__, ctxt->irq_req, ctxt->mrkr_dis, ctxt->is_mm); - - sw_ctxt[num_words_count++] = ctxt->ring_bs_addr & 0xffffffff; - sw_ctxt[num_words_count++] = (ctxt->ring_bs_addr >> 32) & 0xffffffff; - - sw_ctxt[num_words_count++] = - FIELD_SET(SW_IND_CTXT_DATA_W4_VEC_MASK, ctxt->vec) | - FIELD_SET(SW_IND_CTXT_DATA_W4_INT_AGGR_MASK, ctxt->intr_aggr) | - FIELD_SET(SW_IND_CTXT_DATA_W4_DIS_INTR_ON_VF_MASK, - ctxt->dis_intr_on_vf) | - FIELD_SET(SW_IND_CTXT_DATA_W4_VIRTIO_EN_MASK, - ctxt->virtio_en) | - FIELD_SET(SW_IND_CTXT_DATA_W4_PACK_BYP_OUT_MASK, - ctxt->pack_byp_out) | - FIELD_SET(SW_IND_CTXT_DATA_W4_IRQ_BYP_MASK, ctxt->irq_byp) | - FIELD_SET(SW_IND_CTXT_DATA_W4_HOST_ID_MASK, ctxt->host_id) | - FIELD_SET(SW_IND_CTXT_DATA_W4_PASID_L_MASK, pasid_l); - - sw_ctxt[num_words_count++] = - FIELD_SET(SW_IND_CTXT_DATA_W5_PASID_H_MASK, pasid_h) | - FIELD_SET(SW_IND_CTXT_DATA_W5_PASID_EN_MASK, ctxt->pasid_en) | - FIELD_SET(SW_IND_CTXT_DATA_W5_VIRTIO_DSC_BASE_L_MASK, - virtio_desc_base_l); - - sw_ctxt[num_words_count++] = - FIELD_SET(SW_IND_CTXT_DATA_W6_VIRTIO_DSC_BASE_M_MASK, - virtio_desc_base_m); - - sw_ctxt[num_words_count++] = - FIELD_SET(SW_IND_CTXT_DATA_W7_VIRTIO_DSC_BASE_H_MASK, - virtio_desc_base_h); - - - qdma_log_debug("%s: vec=%x, intr_aggr=%x\n", - __func__, ctxt->vec, ctxt->intr_aggr); - - return eqdma_cpm5_indirect_reg_write(dev_hndl, sel, hw_qid, - sw_ctxt, num_words_count); -} - -/*****************************************************************************/ -/** - * eqdma_cpm5_sw_context_read() - read sw context - * - * @dev_hndl: device handle - * @c2h: is c2h queue - * @hw_qid: hardware qid of the queue - * @ctxt: pointer to the output context data - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -static int eqdma_cpm5_sw_context_read(void *dev_hndl, uint8_t c2h, - uint16_t hw_qid, - struct qdma_descq_sw_ctxt *ctxt) -{ - int rv = QDMA_SUCCESS; - uint32_t sw_ctxt[EQDMA_CPM5_SW_CONTEXT_NUM_WORDS] = {0}; - uint32_t pasid_l, pasid_h; - uint32_t virtio_desc_base_l, virtio_desc_base_m, virtio_desc_base_h; - enum ind_ctxt_cmd_sel sel = c2h ? - QDMA_CTXT_SEL_SW_C2H : QDMA_CTXT_SEL_SW_H2C; - - if (!dev_hndl || !ctxt) { - qdma_log_error("%s: dev_handle=%p sw_ctxt=%p NULL, err:%d\n", - __func__, dev_hndl, ctxt, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - rv = eqdma_cpm5_indirect_reg_read(dev_hndl, sel, hw_qid, - EQDMA_CPM5_SW_CONTEXT_NUM_WORDS, sw_ctxt); - if (rv < 0) - return rv; - - ctxt->pidx = FIELD_GET(SW_IND_CTXT_DATA_W0_PIDX_MASK, sw_ctxt[0]); - ctxt->irq_arm = - (uint8_t)(FIELD_GET(SW_IND_CTXT_DATA_W0_IRQ_ARM_MASK, - sw_ctxt[0])); - ctxt->fnc_id = FIELD_GET(SW_IND_CTXT_DATA_W0_FNC_MASK, sw_ctxt[0]); - - qdma_log_debug("%s: pidx=%x, irq_arm=%x, fnc_id=%x", - __func__, ctxt->pidx, ctxt->irq_arm, ctxt->fnc_id); - - ctxt->qen = FIELD_GET(SW_IND_CTXT_DATA_W1_QEN_MASK, sw_ctxt[1]); - ctxt->frcd_en = FIELD_GET(SW_IND_CTXT_DATA_W1_FCRD_EN_MASK, sw_ctxt[1]); - ctxt->wbi_chk = FIELD_GET(SW_IND_CTXT_DATA_W1_WBI_CHK_MASK, sw_ctxt[1]); - ctxt->wbi_intvl_en = - FIELD_GET(SW_IND_CTXT_DATA_W1_WBI_INTVL_EN_MASK, sw_ctxt[1]); - ctxt->at = FIELD_GET(SW_IND_CTXT_DATA_W1_AT_MASK, sw_ctxt[1]); - ctxt->fetch_max = - (uint8_t)FIELD_GET(SW_IND_CTXT_DATA_W1_FETCH_MAX_MASK, - sw_ctxt[1]); - ctxt->rngsz_idx = - (uint8_t)(FIELD_GET(SW_IND_CTXT_DATA_W1_RNG_SZ_MASK, - sw_ctxt[1])); - ctxt->desc_sz = - (uint8_t)(FIELD_GET(SW_IND_CTXT_DATA_W1_DSC_SZ_MASK, - sw_ctxt[1])); - ctxt->bypass = - (uint8_t)(FIELD_GET(SW_IND_CTXT_DATA_W1_BYPASS_MASK, - sw_ctxt[1])); - ctxt->mm_chn = - (uint8_t)(FIELD_GET(SW_IND_CTXT_DATA_W1_MM_CHN_MASK, - sw_ctxt[1])); - ctxt->wbk_en = - (uint8_t)(FIELD_GET(SW_IND_CTXT_DATA_W1_WBK_EN_MASK, - sw_ctxt[1])); - ctxt->irq_en = - (uint8_t)(FIELD_GET(SW_IND_CTXT_DATA_W1_IRQ_EN_MASK, - sw_ctxt[1])); - ctxt->port_id = - (uint8_t)(FIELD_GET(SW_IND_CTXT_DATA_W1_PORT_ID_MASK, - sw_ctxt[1])); - ctxt->irq_no_last = - (uint8_t)(FIELD_GET(SW_IND_CTXT_DATA_W1_IRQ_NO_LAST_MASK, - sw_ctxt[1])); - ctxt->err = - (uint8_t)(FIELD_GET(SW_IND_CTXT_DATA_W1_ERR_MASK, sw_ctxt[1])); - ctxt->err_wb_sent = - (uint8_t)(FIELD_GET(SW_IND_CTXT_DATA_W1_ERR_WB_SENT_MASK, - sw_ctxt[1])); - ctxt->irq_req = - (uint8_t)(FIELD_GET(SW_IND_CTXT_DATA_W1_IRQ_REQ_MASK, - sw_ctxt[1])); - ctxt->mrkr_dis = - (uint8_t)(FIELD_GET(SW_IND_CTXT_DATA_W1_MRKR_DIS_MASK, - sw_ctxt[1])); - ctxt->is_mm = - (uint8_t)(FIELD_GET(SW_IND_CTXT_DATA_W1_IS_MM_MASK, - sw_ctxt[1])); - - qdma_log_debug("%s: qen=%x, frcd_en=%x, wbi_chk=%x, wbi_intvl_en=%x\n", - __func__, ctxt->qen, ctxt->frcd_en, ctxt->wbi_chk, - ctxt->wbi_intvl_en); - qdma_log_debug("%s: at=%x, fetch_max=%x, rngsz_idx=%x, desc_sz=%x\n", - __func__, ctxt->at, ctxt->fetch_max, ctxt->rngsz_idx, - ctxt->desc_sz); - qdma_log_debug("%s: bypass=%x, mm_chn=%x, wbk_en=%x, irq_en=%x\n", - __func__, ctxt->bypass, ctxt->mm_chn, ctxt->wbk_en, - ctxt->irq_en); - qdma_log_debug("%s: port_id=%x, irq_no_last=%x,", - __func__, ctxt->port_id, ctxt->irq_no_last); - qdma_log_debug(" err=%x, err_wb_sent=%x\n", - ctxt->err, ctxt->err_wb_sent); - qdma_log_debug("%s: irq_req=%x, mrkr_dis=%x, is_mm=%x\n", - __func__, ctxt->irq_req, ctxt->mrkr_dis, ctxt->is_mm); - - ctxt->ring_bs_addr = ((uint64_t)sw_ctxt[3] << 32) | (sw_ctxt[2]); - - ctxt->vec = FIELD_GET(SW_IND_CTXT_DATA_W4_VEC_MASK, sw_ctxt[4]); - ctxt->intr_aggr = (uint8_t)(FIELD_GET(SW_IND_CTXT_DATA_W4_INT_AGGR_MASK, - sw_ctxt[4])); - ctxt->dis_intr_on_vf = - (uint8_t)(FIELD_GET(SW_IND_CTXT_DATA_W4_DIS_INTR_ON_VF_MASK, - sw_ctxt[4])); - ctxt->virtio_en = - (uint8_t)(FIELD_GET(SW_IND_CTXT_DATA_W4_VIRTIO_EN_MASK, - sw_ctxt[4])); - ctxt->pack_byp_out = - (uint8_t)(FIELD_GET(SW_IND_CTXT_DATA_W4_PACK_BYP_OUT_MASK, - sw_ctxt[4])); - ctxt->irq_byp = - (uint8_t)(FIELD_GET(SW_IND_CTXT_DATA_W4_IRQ_BYP_MASK, - sw_ctxt[4])); - ctxt->host_id = - (uint8_t)(FIELD_GET(SW_IND_CTXT_DATA_W4_HOST_ID_MASK, - sw_ctxt[4])); - pasid_l = FIELD_GET(SW_IND_CTXT_DATA_W4_PASID_L_MASK, sw_ctxt[4]); - - pasid_h = FIELD_GET(SW_IND_CTXT_DATA_W5_PASID_H_MASK, sw_ctxt[5]); - ctxt->pasid_en = (uint8_t)FIELD_GET(SW_IND_CTXT_DATA_W5_PASID_EN_MASK, - sw_ctxt[5]); - virtio_desc_base_l = - FIELD_GET(SW_IND_CTXT_DATA_W5_VIRTIO_DSC_BASE_L_MASK, - sw_ctxt[5]); - virtio_desc_base_m = - FIELD_GET(SW_IND_CTXT_DATA_W6_VIRTIO_DSC_BASE_M_MASK, - sw_ctxt[6]); - - virtio_desc_base_h = - FIELD_GET(SW_IND_CTXT_DATA_W7_VIRTIO_DSC_BASE_H_MASK, - sw_ctxt[6]); - - ctxt->pasid = - FIELD_SET(EQDMA_CPM5_SW_CTXT_PASID_GET_L_MASK, pasid_l) | - FIELD_SET(EQDMA_CPM5_SW_CTXT_PASID_GET_H_MASK, pasid_h); - - ctxt->virtio_dsc_base = - FIELD_SET(EQDMA_CPM5_SW_CTXT_VIRTIO_DSC_BASE_GET_L_MASK, - (uint64_t)virtio_desc_base_l) | - FIELD_SET(EQDMA_CPM5_SW_CTXT_VIRTIO_DSC_BASE_GET_M_MASK, - (uint64_t)virtio_desc_base_m) | - FIELD_SET(EQDMA_CPM5_SW_CTXT_VIRTIO_DSC_BASE_GET_H_MASK, - (uint64_t)virtio_desc_base_h); - - qdma_log_debug("%s: vec=%x, intr_aggr=%x\n", - __func__, ctxt->vec, ctxt->intr_aggr); - - return QDMA_SUCCESS; -} - -/*****************************************************************************/ -/** - * eqdma_cpm5_sw_context_clear() - clear sw context - * - * @dev_hndl: device handle - * @c2h: is c2h queue - * @hw_qid: hardware qid of the queue - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -static int eqdma_cpm5_sw_context_clear(void *dev_hndl, uint8_t c2h, - uint16_t hw_qid) -{ - enum ind_ctxt_cmd_sel sel = c2h ? - QDMA_CTXT_SEL_SW_C2H : QDMA_CTXT_SEL_SW_H2C; - - if (!dev_hndl) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", __func__, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - return eqdma_cpm5_indirect_reg_clear(dev_hndl, sel, hw_qid); -} - -/*****************************************************************************/ -/** - * eqdma_cpm5_sw_context_invalidate() - invalidate sw context - * - * @dev_hndl: device handle - * @c2h: is c2h queue - * @hw_qid: hardware qid of the queue - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -static int eqdma_cpm5_sw_context_invalidate(void *dev_hndl, uint8_t c2h, - uint16_t hw_qid) -{ - enum ind_ctxt_cmd_sel sel = c2h ? - QDMA_CTXT_SEL_SW_C2H : QDMA_CTXT_SEL_SW_H2C; - - if (!dev_hndl) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", __func__, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - return eqdma_cpm5_indirect_reg_invalidate(dev_hndl, sel, hw_qid); -} - -/*****************************************************************************/ -/** - * eqdma_cpm5_sw_ctx_conf() - configure SW context - * - * @dev_hndl: device handle - * @c2h: is c2h queue - * @hw_qid: hardware qid of the queue - * @ctxt: pointer to the context data - * @access_type HW access type (qdma_hw_access_type enum) value - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -int eqdma_cpm5_sw_ctx_conf(void *dev_hndl, uint8_t c2h, uint16_t hw_qid, - struct qdma_descq_sw_ctxt *ctxt, - enum qdma_hw_access_type access_type) -{ - int rv = QDMA_SUCCESS; - - switch (access_type) { - case QDMA_HW_ACCESS_READ: - rv = eqdma_cpm5_sw_context_read(dev_hndl, c2h, hw_qid, - ctxt); - break; - case QDMA_HW_ACCESS_WRITE: - rv = eqdma_cpm5_sw_context_write(dev_hndl, c2h, hw_qid, - ctxt); - break; - case QDMA_HW_ACCESS_CLEAR: - rv = eqdma_cpm5_sw_context_clear(dev_hndl, c2h, hw_qid); - break; - case QDMA_HW_ACCESS_INVALIDATE: - rv = eqdma_cpm5_sw_context_invalidate(dev_hndl, c2h, - hw_qid); - break; - default: - qdma_log_error("%s: access_type(%d) invalid, err:%d\n", - __func__, - access_type, - -QDMA_ERR_INV_PARAM); - rv = -QDMA_ERR_INV_PARAM; - break; - } - - return rv; -} - -/*****************************************************************************/ -/** - * eqdma_cpm5_pfetch_context_write() - create prefetch context and program - * it - * - * @dev_hndl: device handle - * @hw_qid: hardware qid of the queue - * @ctxt: pointer to the prefetch context data strucutre - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -static int eqdma_cpm5_pfetch_context_write(void *dev_hndl, uint16_t hw_qid, - const struct qdma_descq_prefetch_ctxt *ctxt) -{ - uint32_t pfetch_ctxt[EQDMA_CPM5_PFETCH_CONTEXT_NUM_WORDS] = {0}; - enum ind_ctxt_cmd_sel sel = QDMA_CTXT_SEL_PFTCH; - uint32_t sw_crdt_l, sw_crdt_h; - uint16_t num_words_count = 0; - - if (!dev_hndl || !ctxt) { - qdma_log_error("%s: dev_handle or pfetch ctxt NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - sw_crdt_l = - FIELD_GET(QDMA_PFTCH_CTXT_SW_CRDT_GET_L_MASK, ctxt->sw_crdt); - sw_crdt_h = - FIELD_GET(QDMA_PFTCH_CTXT_SW_CRDT_GET_H_MASK, ctxt->sw_crdt); - - qdma_log_debug("%s: sw_crdt_l=%u, sw_crdt_h=%u, hw_qid=%hu\n", - __func__, sw_crdt_l, sw_crdt_h, hw_qid); - - pfetch_ctxt[num_words_count++] = - FIELD_SET(PREFETCH_CTXT_DATA_W0_BYPASS_MASK, ctxt->bypass) | - FIELD_SET(PREFETCH_CTXT_DATA_W0_BUF_SZ_IDX_MASK, - ctxt->bufsz_idx) | - FIELD_SET(PREFETCH_CTXT_DATA_W0_PORT_ID_MASK, ctxt->port_id) | - FIELD_SET(PREFETCH_CTXT_DATA_W0_NUM_PFCH_MASK, - ctxt->num_pftch) | - FIELD_SET(PREFETCH_CTXT_DATA_W0_VAR_DESC_MASK, - ctxt->var_desc) | - FIELD_SET(PREFETCH_CTXT_DATA_W0_ERR_MASK, ctxt->err) | - FIELD_SET(PREFETCH_CTXT_DATA_W0_PFCH_EN_MASK, ctxt->pfch_en) | - FIELD_SET(PREFETCH_CTXT_DATA_W0_PFCH_MASK, ctxt->pfch) | - FIELD_SET(PREFETCH_CTXT_DATA_W0_SW_CRDT_L_MASK, sw_crdt_l); - - qdma_log_debug("%s: bypass=%x, bufsz_idx=%x, port_id=%x\n", - __func__, ctxt->bypass, ctxt->bufsz_idx, ctxt->port_id); - qdma_log_debug("%s: err=%x, pfch_en=%x, pfch=%x, ctxt->valid=%x\n", - __func__, ctxt->err, ctxt->pfch_en, ctxt->pfch, - ctxt->valid); - - pfetch_ctxt[num_words_count++] = - FIELD_SET(PREFETCH_CTXT_DATA_W1_SW_CRDT_H_MASK, sw_crdt_h) | - FIELD_SET(PREFETCH_CTXT_DATA_W1_VALID_MASK, ctxt->valid); - - return eqdma_cpm5_indirect_reg_write(dev_hndl, sel, hw_qid, - pfetch_ctxt, num_words_count); -} - -/*****************************************************************************/ -/** - * eqdma_cpm5_pfetch_context_read() - read prefetch context - * - * @dev_hndl: device handle - * @hw_qid: hardware qid of the queue - * @ctxt: pointer to the output context data - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -static int eqdma_cpm5_pfetch_context_read(void *dev_hndl, uint16_t hw_qid, - struct qdma_descq_prefetch_ctxt *ctxt) -{ - int rv = QDMA_SUCCESS; - uint32_t pfetch_ctxt[EQDMA_CPM5_PFETCH_CONTEXT_NUM_WORDS] = {0}; - enum ind_ctxt_cmd_sel sel = QDMA_CTXT_SEL_PFTCH; - uint32_t sw_crdt_l, sw_crdt_h; - - if (!dev_hndl || !ctxt) { - qdma_log_error("%s: dev_handle or pfetch ctxt NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - rv = eqdma_cpm5_indirect_reg_read(dev_hndl, sel, hw_qid, - EQDMA_CPM5_PFETCH_CONTEXT_NUM_WORDS, pfetch_ctxt); - if (rv < 0) - return rv; - - ctxt->bypass = - FIELD_GET(PREFETCH_CTXT_DATA_W0_BYPASS_MASK, pfetch_ctxt[0]); - ctxt->bufsz_idx = - FIELD_GET(PREFETCH_CTXT_DATA_W0_BUF_SZ_IDX_MASK, - pfetch_ctxt[0]); - ctxt->num_pftch = (uint16_t) FIELD_GET( - PREFETCH_CTXT_DATA_W0_NUM_PFCH_MASK, pfetch_ctxt[0]); - ctxt->port_id = - FIELD_GET(PREFETCH_CTXT_DATA_W0_PORT_ID_MASK, pfetch_ctxt[0]); - ctxt->var_desc = (uint8_t) - FIELD_GET(PREFETCH_CTXT_DATA_W0_VAR_DESC_MASK, - pfetch_ctxt[0]); - ctxt->err = - (uint8_t)(FIELD_GET(PREFETCH_CTXT_DATA_W0_ERR_MASK, - pfetch_ctxt[0])); - ctxt->pfch_en = - (uint8_t)(FIELD_GET(PREFETCH_CTXT_DATA_W0_PFCH_EN_MASK, - pfetch_ctxt[0])); - ctxt->pfch = - (uint8_t)(FIELD_GET(PREFETCH_CTXT_DATA_W0_PFCH_MASK, - pfetch_ctxt[0])); - sw_crdt_l = - FIELD_GET(PREFETCH_CTXT_DATA_W0_SW_CRDT_L_MASK, pfetch_ctxt[0]); - - sw_crdt_h = - FIELD_GET(PREFETCH_CTXT_DATA_W1_SW_CRDT_H_MASK, pfetch_ctxt[1]); - ctxt->valid = - (uint8_t)(FIELD_GET(PREFETCH_CTXT_DATA_W1_VALID_MASK, - pfetch_ctxt[1])); - - ctxt->sw_crdt = - FIELD_SET(QDMA_PFTCH_CTXT_SW_CRDT_GET_L_MASK, sw_crdt_l) | - FIELD_SET(QDMA_PFTCH_CTXT_SW_CRDT_GET_H_MASK, sw_crdt_h); - - qdma_log_debug("%s: sw_crdt_l=%u, sw_crdt_h=%u, hw_qid=%hu\n", - __func__, sw_crdt_l, sw_crdt_h, hw_qid); - qdma_log_debug("%s: bypass=%x, bufsz_idx=%x, port_id=%x\n", - __func__, ctxt->bypass, ctxt->bufsz_idx, ctxt->port_id); - qdma_log_debug("%s: err=%x, pfch_en=%x, pfch=%x, ctxt->valid=%x\n", - __func__, ctxt->err, ctxt->pfch_en, ctxt->pfch, - ctxt->valid); - - return QDMA_SUCCESS; -} - -/*****************************************************************************/ -/** - * eqdma_cpm5_pfetch_context_clear() - clear prefetch context - * - * @dev_hndl: device handle - * @hw_qid: hardware qid of the queue - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -static int eqdma_cpm5_pfetch_context_clear(void *dev_hndl, uint16_t hw_qid) -{ - enum ind_ctxt_cmd_sel sel = QDMA_CTXT_SEL_PFTCH; - - if (!dev_hndl) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", __func__, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - return eqdma_cpm5_indirect_reg_clear(dev_hndl, sel, hw_qid); -} - -/*****************************************************************************/ -/** - * eqdma_cpm5_pfetch_context_invalidate() - invalidate prefetch context - * - * @dev_hndl: device handle - * @hw_qid: hardware qid of the queue - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -static int eqdma_cpm5_pfetch_context_invalidate(void *dev_hndl, - uint16_t hw_qid) -{ - enum ind_ctxt_cmd_sel sel = QDMA_CTXT_SEL_PFTCH; - - if (!dev_hndl) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", __func__, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - return eqdma_cpm5_indirect_reg_invalidate(dev_hndl, sel, hw_qid); -} - -/*****************************************************************************/ -/** - * eqdma_cpm5_pfetch_ctx_conf() - configure prefetch context - * - * @dev_hndl: device handle - * @hw_qid: hardware qid of the queue - * @ctxt: pointer to context data - * @access_type HW access type (qdma_hw_access_type enum) value - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -int eqdma_cpm5_pfetch_ctx_conf(void *dev_hndl, uint16_t hw_qid, - struct qdma_descq_prefetch_ctxt *ctxt, - enum qdma_hw_access_type access_type) -{ - int rv = QDMA_SUCCESS; - - switch (access_type) { - case QDMA_HW_ACCESS_READ: - rv = eqdma_cpm5_pfetch_context_read(dev_hndl, hw_qid, - ctxt); - break; - case QDMA_HW_ACCESS_WRITE: - rv = eqdma_cpm5_pfetch_context_write(dev_hndl, hw_qid, - ctxt); - break; - case QDMA_HW_ACCESS_CLEAR: - rv = eqdma_cpm5_pfetch_context_clear(dev_hndl, hw_qid); - break; - case QDMA_HW_ACCESS_INVALIDATE: - rv = eqdma_cpm5_pfetch_context_invalidate(dev_hndl, - hw_qid); - break; - default: - qdma_log_error("%s: access_type(%d) invalid, err:%d\n", - __func__, - access_type, - -QDMA_ERR_INV_PARAM); - rv = -QDMA_ERR_INV_PARAM; - break; - } - - return rv; -} - -/*****************************************************************************/ -/** - * eqdma_cpm5_cmpt_context_write() - create completion context and program - * it - * - * @dev_hndl: device handle - * @hw_qid: hardware qid of the queue - * @ctxt: pointer to the cmpt context data strucutre - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -static int eqdma_cpm5_cmpt_context_write(void *dev_hndl, uint16_t hw_qid, - const struct qdma_descq_cmpt_ctxt *ctxt) -{ - uint32_t cmpt_ctxt[EQDMA_CPM5_CMPT_CONTEXT_NUM_WORDS] = {0}; - uint16_t num_words_count = 0; - uint32_t baddr4_high_l, baddr4_high_h, - baddr4_low, pidx_l, pidx_h, pasid_l, pasid_h; - enum ind_ctxt_cmd_sel sel = QDMA_CTXT_SEL_CMPT; - - /* Input args check */ - if (!dev_hndl || !ctxt) { - qdma_log_error("%s: dev_handle or cmpt ctxt NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - if (ctxt->trig_mode > QDMA_CMPT_UPDATE_TRIG_MODE_TMR_CNTR) { - qdma_log_error("%s: trig_mode(%d) > (%d) is invalid, err:%d\n", - __func__, - ctxt->trig_mode, - QDMA_CMPT_UPDATE_TRIG_MODE_TMR_CNTR, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - baddr4_high_l = - (uint32_t)FIELD_GET(EQDMA_CPM5_COMPL_CTXT_BADDR_HIGH_L_MASK, - ctxt->bs_addr); - baddr4_high_h = - (uint32_t)FIELD_GET(EQDMA_CPM5_COMPL_CTXT_BADDR_HIGH_H_MASK, - ctxt->bs_addr); - baddr4_low = - (uint32_t)FIELD_GET(EQDMA_CPM5_COMPL_CTXT_BADDR_LOW_MASK, - ctxt->bs_addr); - - pidx_l = FIELD_GET(QDMA_COMPL_CTXT_PIDX_GET_L_MASK, ctxt->pidx); - pidx_h = FIELD_GET(QDMA_COMPL_CTXT_PIDX_GET_H_MASK, ctxt->pidx); - - pasid_l = - FIELD_GET(EQDMA_CPM5_CMPL_CTXT_PASID_GET_L_MASK, - ctxt->pasid); - pasid_h = - FIELD_GET(EQDMA_CPM5_CMPL_CTXT_PASID_GET_H_MASK, - ctxt->pasid); - - cmpt_ctxt[num_words_count++] = - FIELD_SET(CMPL_CTXT_DATA_W0_EN_STAT_DESC_MASK, - ctxt->en_stat_desc) | - FIELD_SET(CMPL_CTXT_DATA_W0_EN_INT_MASK, ctxt->en_int) | - FIELD_SET(CMPL_CTXT_DATA_W0_TRIG_MODE_MASK, ctxt->trig_mode) | - FIELD_SET(CMPL_CTXT_DATA_W0_FNC_ID_MASK, ctxt->fnc_id) | - FIELD_SET(CMPL_CTXT_DATA_W0_CNTER_IX_MASK, - ctxt->counter_idx) | - FIELD_SET(CMPL_CTXT_DATA_W0_TIMER_IX_MASK, ctxt->timer_idx) | - FIELD_SET(CMPL_CTXT_DATA_W0_INT_ST_MASK, ctxt->in_st) | - FIELD_SET(CMPL_CTXT_DATA_W0_COLOR_MASK, ctxt->color) | - FIELD_SET(CMPL_CTXT_DATA_W0_QSIZE_IX_MASK, ctxt->ringsz_idx); - - cmpt_ctxt[num_words_count++] = - FIELD_SET(CMPL_CTXT_DATA_W1_BADDR4_HIGH_L_MASK, baddr4_high_l); - - cmpt_ctxt[num_words_count++] = - FIELD_SET(CMPL_CTXT_DATA_W2_BADDR4_HIGH_H_MASK, baddr4_high_h) | - FIELD_SET(CMPL_CTXT_DATA_W2_DESC_SIZE_MASK, ctxt->desc_sz) | - FIELD_SET(CMPL_CTXT_DATA_W2_PIDX_L_MASK, pidx_l); - - cmpt_ctxt[num_words_count++] = - FIELD_SET(CMPL_CTXT_DATA_W3_PIDX_H_MASK, pidx_h) | - FIELD_SET(CMPL_CTXT_DATA_W3_CIDX_MASK, ctxt->cidx) | - FIELD_SET(CMPL_CTXT_DATA_W3_VALID_MASK, ctxt->valid) | - FIELD_SET(CMPL_CTXT_DATA_W3_ERR_MASK, ctxt->err) | - FIELD_SET(CMPL_CTXT_DATA_W3_USER_TRIG_PEND_MASK, - ctxt->user_trig_pend); - - cmpt_ctxt[num_words_count++] = - FIELD_SET(CMPL_CTXT_DATA_W4_TIMER_RUNNING_MASK, - ctxt->timer_running) | - FIELD_SET(CMPL_CTXT_DATA_W4_FULL_UPD_MASK, ctxt->full_upd) | - FIELD_SET(CMPL_CTXT_DATA_W4_OVF_CHK_DIS_MASK, - ctxt->ovf_chk_dis) | - FIELD_SET(CMPL_CTXT_DATA_W4_AT_MASK, ctxt->at) | - FIELD_SET(CMPL_CTXT_DATA_W4_VEC_MASK, ctxt->vec) | - FIELD_SET(CMPL_CTXT_DATA_W4_INT_AGGR_MASK, ctxt->int_aggr) | - FIELD_SET(CMPL_CTXT_DATA_W4_DIS_INTR_ON_VF_MASK, - ctxt->dis_intr_on_vf) | - FIELD_SET(CMPL_CTXT_DATA_W4_VIO_MASK, ctxt->vio) | - FIELD_SET(CMPL_CTXT_DATA_W4_DIR_C2H_MASK, ctxt->dir_c2h) | - FIELD_SET(CMPL_CTXT_DATA_W4_HOST_ID_MASK, ctxt->host_id) | - FIELD_SET(CMPL_CTXT_DATA_W4_PASID_L_MASK, pasid_l); - - cmpt_ctxt[num_words_count++] = - FIELD_SET(CMPL_CTXT_DATA_W5_PASID_H_MASK, pasid_h) | - FIELD_SET(CMPL_CTXT_DATA_W5_PASID_EN_MASK, - ctxt->pasid_en) | - FIELD_SET(CMPL_CTXT_DATA_W5_BADDR4_LOW_MASK, - baddr4_low) | - FIELD_SET(CMPL_CTXT_DATA_W5_VIO_EOP_MASK, ctxt->vio_eop) | - FIELD_SET(CMPL_CTXT_DATA_W5_SH_CMPT_MASK, ctxt->sh_cmpt); - - return eqdma_cpm5_indirect_reg_write(dev_hndl, sel, hw_qid, - cmpt_ctxt, num_words_count); -} - -/*****************************************************************************/ -/** - * eqdma_cpm5_cmpt_context_read() - read completion context - * - * @dev_hndl: device handle - * @hw_qid: hardware qid of the queue - * @ctxt: pointer to the context data - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -static int eqdma_cpm5_cmpt_context_read(void *dev_hndl, uint16_t hw_qid, - struct qdma_descq_cmpt_ctxt *ctxt) -{ - int rv = QDMA_SUCCESS; - uint32_t cmpt_ctxt[EQDMA_CPM5_CMPT_CONTEXT_NUM_WORDS] = {0}; - enum ind_ctxt_cmd_sel sel = QDMA_CTXT_SEL_CMPT; - uint32_t baddr4_high_l, baddr4_high_h, baddr4_low, - pidx_l, pidx_h, pasid_l, pasid_h; - - if (!dev_hndl || !ctxt) { - qdma_log_error("%s: dev_handle or cmpt ctxt NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - rv = eqdma_cpm5_indirect_reg_read(dev_hndl, sel, hw_qid, - EQDMA_CPM5_CMPT_CONTEXT_NUM_WORDS, cmpt_ctxt); - if (rv < 0) - return rv; - - ctxt->en_stat_desc = - FIELD_GET(CMPL_CTXT_DATA_W0_EN_STAT_DESC_MASK, cmpt_ctxt[0]); - ctxt->en_int = FIELD_GET(CMPL_CTXT_DATA_W0_EN_INT_MASK, cmpt_ctxt[0]); - ctxt->trig_mode = - FIELD_GET(CMPL_CTXT_DATA_W0_TRIG_MODE_MASK, cmpt_ctxt[0]); - ctxt->fnc_id = FIELD_GET(CMPL_CTXT_DATA_W0_FNC_ID_MASK, cmpt_ctxt[0]); - ctxt->counter_idx = - (uint8_t)(FIELD_GET(CMPL_CTXT_DATA_W0_CNTER_IX_MASK, - cmpt_ctxt[0])); - ctxt->timer_idx = - (uint8_t)(FIELD_GET(CMPL_CTXT_DATA_W0_TIMER_IX_MASK, - cmpt_ctxt[0])); - ctxt->in_st = - (uint8_t)(FIELD_GET(CMPL_CTXT_DATA_W0_INT_ST_MASK, - cmpt_ctxt[0])); - ctxt->color = - (uint8_t)(FIELD_GET(CMPL_CTXT_DATA_W0_COLOR_MASK, - cmpt_ctxt[0])); - ctxt->ringsz_idx = - (uint8_t)(FIELD_GET(CMPL_CTXT_DATA_W0_QSIZE_IX_MASK, - cmpt_ctxt[0])); - - baddr4_high_l = FIELD_GET(CMPL_CTXT_DATA_W1_BADDR4_HIGH_L_MASK, - cmpt_ctxt[1]); - - baddr4_high_h = FIELD_GET(CMPL_CTXT_DATA_W2_BADDR4_HIGH_H_MASK, - cmpt_ctxt[2]); - ctxt->desc_sz = - (uint8_t)(FIELD_GET(CMPL_CTXT_DATA_W2_DESC_SIZE_MASK, - cmpt_ctxt[2])); - pidx_l = FIELD_GET(CMPL_CTXT_DATA_W2_PIDX_L_MASK, cmpt_ctxt[2]); - - pidx_h = FIELD_GET(CMPL_CTXT_DATA_W3_PIDX_H_MASK, cmpt_ctxt[3]); - ctxt->cidx = - (uint16_t)(FIELD_GET(CMPL_CTXT_DATA_W3_CIDX_MASK, - cmpt_ctxt[3])); - ctxt->valid = - (uint8_t)(FIELD_GET(CMPL_CTXT_DATA_W3_VALID_MASK, - cmpt_ctxt[3])); - ctxt->err = - (uint8_t)(FIELD_GET(CMPL_CTXT_DATA_W3_ERR_MASK, - cmpt_ctxt[3])); - ctxt->user_trig_pend = (uint8_t) - (FIELD_GET(CMPL_CTXT_DATA_W3_USER_TRIG_PEND_MASK, - cmpt_ctxt[3])); - - ctxt->timer_running = - FIELD_GET(CMPL_CTXT_DATA_W4_TIMER_RUNNING_MASK, cmpt_ctxt[4]); - ctxt->full_upd = - FIELD_GET(CMPL_CTXT_DATA_W4_FULL_UPD_MASK, cmpt_ctxt[4]); - ctxt->ovf_chk_dis = - FIELD_GET(CMPL_CTXT_DATA_W4_OVF_CHK_DIS_MASK, cmpt_ctxt[4]); - ctxt->at = FIELD_GET(CMPL_CTXT_DATA_W4_AT_MASK, cmpt_ctxt[4]); - ctxt->vec = FIELD_GET(CMPL_CTXT_DATA_W4_VEC_MASK, cmpt_ctxt[4]); - ctxt->int_aggr = (uint8_t) - (FIELD_GET(CMPL_CTXT_DATA_W4_INT_AGGR_MASK, cmpt_ctxt[4])); - ctxt->dis_intr_on_vf = (uint8_t) - FIELD_GET(CMPL_CTXT_DATA_W4_DIS_INTR_ON_VF_MASK, - cmpt_ctxt[4]); - ctxt->vio = (uint8_t)FIELD_GET(CMPL_CTXT_DATA_W4_VIO_MASK, - cmpt_ctxt[4]); - ctxt->dir_c2h = (uint8_t)FIELD_GET(CMPL_CTXT_DATA_W4_DIR_C2H_MASK, - cmpt_ctxt[4]); - ctxt->host_id = (uint8_t)FIELD_GET(CMPL_CTXT_DATA_W4_HOST_ID_MASK, - cmpt_ctxt[4]); - pasid_l = FIELD_GET(CMPL_CTXT_DATA_W4_PASID_L_MASK, cmpt_ctxt[4]); - - pasid_h = (uint32_t)FIELD_GET(CMPL_CTXT_DATA_W5_PASID_H_MASK, - cmpt_ctxt[5]); - ctxt->pasid_en = (uint8_t)FIELD_GET(CMPL_CTXT_DATA_W5_PASID_EN_MASK, - cmpt_ctxt[5]); - baddr4_low = (uint8_t)FIELD_GET( - CMPL_CTXT_DATA_W5_BADDR4_LOW_MASK, cmpt_ctxt[5]); - ctxt->vio_eop = (uint8_t)FIELD_GET(CMPL_CTXT_DATA_W5_VIO_EOP_MASK, - cmpt_ctxt[5]); - ctxt->sh_cmpt = (uint8_t)FIELD_GET(CMPL_CTXT_DATA_W5_SH_CMPT_MASK, - cmpt_ctxt[5]); - - ctxt->bs_addr = - FIELD_SET(EQDMA_CPM5_COMPL_CTXT_BADDR_HIGH_L_MASK, - (uint64_t)baddr4_high_l) | - FIELD_SET(EQDMA_CPM5_COMPL_CTXT_BADDR_HIGH_H_MASK, - (uint64_t)baddr4_high_h) | - FIELD_SET(EQDMA_CPM5_COMPL_CTXT_BADDR_LOW_MASK, - (uint64_t)baddr4_low); - - ctxt->pasid = - FIELD_SET(EQDMA_CPM5_CMPL_CTXT_PASID_GET_L_MASK, pasid_l) | - FIELD_SET(EQDMA_CPM5_CMPL_CTXT_PASID_GET_H_MASK, - (uint64_t)pasid_h); - - ctxt->pidx = - FIELD_SET(QDMA_COMPL_CTXT_PIDX_GET_L_MASK, pidx_l) | - FIELD_SET(QDMA_COMPL_CTXT_PIDX_GET_H_MASK, pidx_h); - - return QDMA_SUCCESS; -} - -/*****************************************************************************/ -/** - * eqdma_cpm5_cmpt_context_clear() - clear completion context - * - * @dev_hndl: device handle - * @hw_qid: hardware qid of the queue - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -static int eqdma_cpm5_cmpt_context_clear(void *dev_hndl, uint16_t hw_qid) -{ - enum ind_ctxt_cmd_sel sel = QDMA_CTXT_SEL_CMPT; - - if (!dev_hndl) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", __func__, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - return eqdma_cpm5_indirect_reg_clear(dev_hndl, sel, hw_qid); -} - -/*****************************************************************************/ -/** - * eqdma_cpm5_cmpt_context_invalidate() - invalidate completion context - * - * @dev_hndl: device handle - * @hw_qid: hardware qid of the queue - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -static int eqdma_cpm5_cmpt_context_invalidate(void *dev_hndl, - uint16_t hw_qid) -{ - enum ind_ctxt_cmd_sel sel = QDMA_CTXT_SEL_CMPT; - - if (!dev_hndl) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", __func__, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - return eqdma_cpm5_indirect_reg_invalidate(dev_hndl, sel, hw_qid); -} - -/*****************************************************************************/ -/** - * eqdma_cpm5_cmpt_ctx_conf() - configure completion context - * - * @dev_hndl: device handle - * @hw_qid: hardware qid of the queue - * @ctxt: pointer to context data - * @access_type HW access type (qdma_hw_access_type enum) value - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -int eqdma_cpm5_cmpt_ctx_conf(void *dev_hndl, uint16_t hw_qid, - struct qdma_descq_cmpt_ctxt *ctxt, - enum qdma_hw_access_type access_type) -{ - int rv = QDMA_SUCCESS; - - switch (access_type) { - case QDMA_HW_ACCESS_READ: - rv = eqdma_cpm5_cmpt_context_read(dev_hndl, hw_qid, ctxt); - break; - case QDMA_HW_ACCESS_WRITE: - rv = eqdma_cpm5_cmpt_context_write(dev_hndl, hw_qid, ctxt); - break; - case QDMA_HW_ACCESS_CLEAR: - rv = eqdma_cpm5_cmpt_context_clear(dev_hndl, hw_qid); - break; - case QDMA_HW_ACCESS_INVALIDATE: - rv = eqdma_cpm5_cmpt_context_invalidate(dev_hndl, hw_qid); - break; - default: - qdma_log_error("%s: access_type(%d) invalid, err:%d\n", - __func__, - access_type, - -QDMA_ERR_INV_PARAM); - rv = -QDMA_ERR_INV_PARAM; - break; - } - - return rv; -} - -/*****************************************************************************/ -/** - * eqdma_cpm5_hw_context_read() - read hardware context - * - * @dev_hndl: device handle - * @c2h: is c2h queue - * @hw_qid: hardware qid of the queue - * @ctxt: pointer to the output context data - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -static int eqdma_cpm5_hw_context_read(void *dev_hndl, uint8_t c2h, - uint16_t hw_qid, struct qdma_descq_hw_ctxt *ctxt) -{ - int rv = QDMA_SUCCESS; - uint32_t hw_ctxt[EQDMA_CPM5_HW_CONTEXT_NUM_WORDS] = {0}; - enum ind_ctxt_cmd_sel sel = c2h ? QDMA_CTXT_SEL_HW_C2H : - QDMA_CTXT_SEL_HW_H2C; - - if (!dev_hndl || !ctxt) { - qdma_log_error("%s: dev_handle or hw_ctxt NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - rv = eqdma_cpm5_indirect_reg_read(dev_hndl, sel, hw_qid, - EQDMA_CPM5_HW_CONTEXT_NUM_WORDS, hw_ctxt); - if (rv < 0) - return rv; - - ctxt->cidx = FIELD_GET(HW_IND_CTXT_DATA_W0_CIDX_MASK, hw_ctxt[0]); - ctxt->crd_use = - (uint16_t)(FIELD_GET(HW_IND_CTXT_DATA_W0_CRD_USE_MASK, - hw_ctxt[0])); - - ctxt->dsc_pend = - (uint8_t)(FIELD_GET(HW_IND_CTXT_DATA_W1_DSC_PND_MASK, - hw_ctxt[1])); - ctxt->idl_stp_b = - (uint8_t)(FIELD_GET(HW_IND_CTXT_DATA_W1_IDL_STP_B_MASK, - hw_ctxt[1])); - ctxt->evt_pnd = - (uint8_t)(FIELD_GET(HW_IND_CTXT_DATA_W1_EVT_PND_MASK, - hw_ctxt[1])); - ctxt->fetch_pnd = (uint8_t) - (FIELD_GET(HW_IND_CTXT_DATA_W1_DSC_PND_MASK, hw_ctxt[1])); - - qdma_log_debug("%s: cidx=%hu, crd_use=%hu, dsc_pend=%x\n", - __func__, ctxt->cidx, ctxt->crd_use, ctxt->dsc_pend); - qdma_log_debug("%s: idl_stp_b=%x, evt_pnd=%x, fetch_pnd=%x\n", - __func__, ctxt->idl_stp_b, ctxt->evt_pnd, - ctxt->fetch_pnd); - - return QDMA_SUCCESS; -} - -/*****************************************************************************/ -/** - * eqdma_cpm5_hw_context_clear() - clear hardware context - * - * @dev_hndl: device handle - * @c2h: is c2h queue - * @hw_qid: hardware qid of the queue - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -static int eqdma_cpm5_hw_context_clear(void *dev_hndl, uint8_t c2h, - uint16_t hw_qid) -{ - enum ind_ctxt_cmd_sel sel = c2h ? QDMA_CTXT_SEL_HW_C2H : - QDMA_CTXT_SEL_HW_H2C; - - if (!dev_hndl) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", __func__, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - return eqdma_cpm5_indirect_reg_clear(dev_hndl, sel, hw_qid); -} - -/*****************************************************************************/ -/** - * eqdma_cpm5_hw_context_invalidate() - invalidate hardware context - * - * @dev_hndl: device handle - * @c2h: is c2h queue - * @hw_qid: hardware qid of the queue - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -static int eqdma_cpm5_hw_context_invalidate(void *dev_hndl, uint8_t c2h, - uint16_t hw_qid) -{ - enum ind_ctxt_cmd_sel sel = c2h ? QDMA_CTXT_SEL_HW_C2H : - QDMA_CTXT_SEL_HW_H2C; - - if (!dev_hndl) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", __func__, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - return eqdma_cpm5_indirect_reg_invalidate(dev_hndl, sel, hw_qid); -} - -/*****************************************************************************/ -/** - * eqdma_cpm5_hw_ctx_conf() - configure HW context - * - * @dev_hndl: device handle - * @c2h: is c2h queue - * @hw_qid: hardware qid of the queue - * @ctxt: pointer to context data - * @access_type HW access type (qdma_hw_access_type enum) value - * QDMA_HW_ACCESS_WRITE Not supported - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -int eqdma_cpm5_hw_ctx_conf(void *dev_hndl, uint8_t c2h, uint16_t hw_qid, - struct qdma_descq_hw_ctxt *ctxt, - enum qdma_hw_access_type access_type) -{ - int rv = QDMA_SUCCESS; - - /** ctxt requires only H2C-0 or C2H-1 - * return error for any other values - */ - if (c2h > 1) { - qdma_log_error("%s: c2h(%d) invalid, err:%d\n", - __func__, - c2h, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - switch (access_type) { - case QDMA_HW_ACCESS_READ: - rv = eqdma_cpm5_hw_context_read(dev_hndl, c2h, hw_qid, - ctxt); - break; - case QDMA_HW_ACCESS_CLEAR: - rv = eqdma_cpm5_hw_context_clear(dev_hndl, c2h, hw_qid); - break; - case QDMA_HW_ACCESS_INVALIDATE: - rv = eqdma_cpm5_hw_context_invalidate(dev_hndl, c2h, - hw_qid); - break; - case QDMA_HW_ACCESS_WRITE: - default: - qdma_log_error("%s: access_type=%d is invalid, err:%d\n", - __func__, access_type, - -QDMA_ERR_INV_PARAM); - rv = -QDMA_ERR_INV_PARAM; - break; - } - - return rv; -} - -/*****************************************************************************/ -/** - * eqdma_cpm5_credit_context_read() - read credit context - * - * @dev_hndl: device handle - * @c2h: is c2h queue - * @hw_qid: hardware qid of the queue - * @ctxt: pointer to the context data - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -static int eqdma_cpm5_credit_context_read(void *dev_hndl, uint8_t c2h, - uint16_t hw_qid, - struct qdma_descq_credit_ctxt *ctxt) -{ - int rv = QDMA_SUCCESS; - uint32_t cr_ctxt[EQDMA_CPM5_CR_CONTEXT_NUM_WORDS] = {0}; - enum ind_ctxt_cmd_sel sel = c2h ? QDMA_CTXT_SEL_CR_C2H : - QDMA_CTXT_SEL_CR_H2C; - - if (!dev_hndl || !ctxt) { - qdma_log_error("%s: dev_hndl=%p credit_ctxt=%p, err:%d\n", - __func__, dev_hndl, ctxt, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - rv = eqdma_cpm5_indirect_reg_read(dev_hndl, sel, hw_qid, - EQDMA_CPM5_CR_CONTEXT_NUM_WORDS, cr_ctxt); - if (rv < 0) - return rv; - - ctxt->credit = FIELD_GET(CRED_CTXT_DATA_W0_CREDT_MASK, cr_ctxt[0]); - - qdma_log_debug("%s: credit=%u\n", __func__, ctxt->credit); - - return QDMA_SUCCESS; -} - -/*****************************************************************************/ -/** - * eqdma_cpm5_credit_context_clear() - clear credit context - * - * @dev_hndl: device handle - * @c2h: is c2h queue - * @hw_qid: hardware qid of the queue - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -static int eqdma_cpm5_credit_context_clear(void *dev_hndl, uint8_t c2h, - uint16_t hw_qid) -{ - enum ind_ctxt_cmd_sel sel = c2h ? QDMA_CTXT_SEL_CR_C2H : - QDMA_CTXT_SEL_CR_H2C; - - if (!dev_hndl) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", __func__, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - return eqdma_cpm5_indirect_reg_clear(dev_hndl, sel, hw_qid); -} - -/*****************************************************************************/ -/** - * eqdma_cpm5_credit_context_invalidate() - invalidate credit context - * - * @dev_hndl: device handle - * @c2h: is c2h queue - * @hw_qid: hardware qid of the queue - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -static int eqdma_cpm5_credit_context_invalidate(void *dev_hndl, uint8_t c2h, - uint16_t hw_qid) -{ - enum ind_ctxt_cmd_sel sel = c2h ? QDMA_CTXT_SEL_CR_C2H : - QDMA_CTXT_SEL_CR_H2C; - - if (!dev_hndl) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", __func__, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - return eqdma_cpm5_indirect_reg_invalidate(dev_hndl, sel, hw_qid); -} - -/*****************************************************************************/ -/** - * eqdma_cpm5_credit_ctx_conf() - configure credit context - * - * @dev_hndl: device handle - * @c2h: is c2h queue - * @hw_qid: hardware qid of the queue - * @ctxt: pointer to the context data - * @access_type HW access type (qdma_hw_access_type enum) value - * QDMA_HW_ACCESS_WRITE Not supported - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -int eqdma_cpm5_credit_ctx_conf(void *dev_hndl, uint8_t c2h, - uint16_t hw_qid, struct qdma_descq_credit_ctxt *ctxt, - enum qdma_hw_access_type access_type) -{ - int rv = QDMA_SUCCESS; - - /** ctxt requires only H2C-0 or C2H-1 - * return error for any other values - */ - if (c2h > 1) { - qdma_log_error("%s: c2h(%d) invalid, err:%d\n", - __func__, - c2h, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - switch (access_type) { - case QDMA_HW_ACCESS_READ: - rv = eqdma_cpm5_credit_context_read(dev_hndl, c2h, hw_qid, - ctxt); - break; - case QDMA_HW_ACCESS_CLEAR: - rv = eqdma_cpm5_credit_context_clear(dev_hndl, c2h, - hw_qid); - break; - case QDMA_HW_ACCESS_INVALIDATE: - rv = eqdma_cpm5_credit_context_invalidate(dev_hndl, c2h, - hw_qid); - break; - case QDMA_HW_ACCESS_WRITE: - default: - qdma_log_error("%s: Invalid access type=%d, err:%d\n", - __func__, access_type, - -QDMA_ERR_INV_PARAM); - rv = -QDMA_ERR_INV_PARAM; - break; - } - - return rv; -} - -/*****************************************************************************/ -/** - * eqdma_cpm5_fmap_context_write() - create fmap context and program it - * - * @dev_hndl: device handle - * @func_id: function id of the device - * @config: pointer to the fmap data strucutre - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -static int eqdma_cpm5_fmap_context_write(void *dev_hndl, uint16_t func_id, - const struct qdma_fmap_cfg *config) -{ - uint32_t fmap[EQDMA_CPM5_FMAP_NUM_WORDS] = {0}; - uint16_t num_words_count = 0; - enum ind_ctxt_cmd_sel sel = QDMA_CTXT_SEL_FMAP; - - if (!dev_hndl || !config) { - qdma_log_error("%s: dev_handle=%p fmap=%p NULL, err:%d\n", - __func__, dev_hndl, config, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - qdma_log_debug("%s: func_id=%hu, qbase=%hu, qmax=%hu\n", __func__, - func_id, config->qbase, config->qmax); - fmap[num_words_count++] = - FIELD_SET(EQDMA_CPM5_FMAP_CTXT_W0_QID_MASK, config->qbase); - fmap[num_words_count++] = - FIELD_SET(EQDMA_CPM5_FMAP_CTXT_W1_QID_MAX_MASK, - config->qmax); - - return eqdma_cpm5_indirect_reg_write(dev_hndl, sel, func_id, - fmap, num_words_count); -} - -/*****************************************************************************/ -/** - * eqdma_cpm5_fmap_context_read() - read fmap context - * - * @dev_hndl: device handle - * @func_id: function id of the device - * @config: pointer to the output fmap data - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -static int eqdma_cpm5_fmap_context_read(void *dev_hndl, uint16_t func_id, - struct qdma_fmap_cfg *config) -{ - int rv = QDMA_SUCCESS; - uint32_t fmap[EQDMA_CPM5_FMAP_NUM_WORDS] = {0}; - enum ind_ctxt_cmd_sel sel = QDMA_CTXT_SEL_FMAP; - - if (!dev_hndl || !config) { - qdma_log_error("%s: dev_handle=%p fmap=%p NULL, err:%d\n", - __func__, dev_hndl, config, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - rv = eqdma_cpm5_indirect_reg_read(dev_hndl, sel, func_id, - EQDMA_CPM5_FMAP_NUM_WORDS, fmap); - if (rv < 0) - return rv; - - config->qbase = FIELD_GET(EQDMA_CPM5_FMAP_CTXT_W0_QID_MASK, - fmap[0]); - config->qmax = FIELD_GET(EQDMA_CPM5_FMAP_CTXT_W1_QID_MAX_MASK, - fmap[1]); - - qdma_log_debug("%s: func_id=%hu, qbase=%hu, qmax=%hu\n", __func__, - func_id, config->qbase, config->qmax); - - return QDMA_SUCCESS; -} - -/*****************************************************************************/ -/** - * eqdma_cpm5_fmap_context_clear() - clear fmap context - * - * @dev_hndl: device handle - * @func_id: function id of the device - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -static int eqdma_cpm5_fmap_context_clear(void *dev_hndl, uint16_t func_id) -{ - enum ind_ctxt_cmd_sel sel = QDMA_CTXT_SEL_FMAP; - - if (!dev_hndl) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", __func__, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - qdma_log_debug("%s: func_id=%hu\n", __func__, func_id); - return eqdma_cpm5_indirect_reg_clear(dev_hndl, sel, func_id); -} - -/*****************************************************************************/ -/** - * eqdma_cpm5_fmap_conf() - configure fmap context - * - * @dev_hndl: device handle - * @func_id: function id of the device - * @config: pointer to the fmap data - * @access_type HW access type (qdma_hw_access_type enum) value - * QDMA_HW_ACCESS_INVALIDATE Not supported - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -int eqdma_cpm5_fmap_conf(void *dev_hndl, uint16_t func_id, - struct qdma_fmap_cfg *config, - enum qdma_hw_access_type access_type) -{ - int rv = QDMA_SUCCESS; - - switch (access_type) { - case QDMA_HW_ACCESS_READ: - rv = eqdma_cpm5_fmap_context_read(dev_hndl, - func_id, config); - break; - case QDMA_HW_ACCESS_WRITE: - rv = eqdma_cpm5_fmap_context_write(dev_hndl, - func_id, config); - break; - case QDMA_HW_ACCESS_CLEAR: - rv = eqdma_cpm5_fmap_context_clear(dev_hndl, func_id); - break; - case QDMA_HW_ACCESS_INVALIDATE: - default: - qdma_log_error("%s: access_type(%d) invalid, err:%d\n", - __func__, - access_type, - -QDMA_ERR_INV_PARAM); - rv = -QDMA_ERR_INV_PARAM; - break; - } - - return rv; -} - -/*****************************************************************************/ -/** - * eqdma_cpm5_indirect_intr_context_write() - create indirect interrupt - * context and program it - * - * @dev_hndl: device handle - * @ring_index: indirect interrupt ring index - * @ctxt: pointer to the interrupt context data strucutre - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -static int eqdma_cpm5_indirect_intr_context_write(void *dev_hndl, - uint16_t ring_index, const struct qdma_indirect_intr_ctxt - *ctxt) -{ - uint32_t intr_ctxt[EQDMA_CPM5_IND_INTR_CONTEXT_NUM_WORDS] = {0}; - enum ind_ctxt_cmd_sel sel = QDMA_CTXT_SEL_INT_COAL; - uint32_t baddr_l, baddr_m, baddr_h, pasid_l, pasid_h; - uint16_t num_words_count = 0; - - if (!dev_hndl || !ctxt) { - qdma_log_error("%s: dev_hndl=%p intr_ctxt=%p, err:%d\n", - __func__, dev_hndl, ctxt, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - baddr_l = (uint32_t)FIELD_GET(QDMA_INTR_CTXT_BADDR_GET_L_MASK, - ctxt->baddr_4k); - baddr_m = (uint32_t)FIELD_GET(QDMA_INTR_CTXT_BADDR_GET_M_MASK, - ctxt->baddr_4k); - baddr_h = (uint32_t)FIELD_GET(QDMA_INTR_CTXT_BADDR_GET_H_MASK, - ctxt->baddr_4k); - - pasid_l = - FIELD_GET(EQDMA_CPM5_INTR_CTXT_PASID_GET_L_MASK, - ctxt->pasid); - pasid_h = - FIELD_GET(EQDMA_CPM5_INTR_CTXT_PASID_GET_H_MASK, - ctxt->pasid); - - intr_ctxt[num_words_count++] = - FIELD_SET(INTR_CTXT_DATA_W0_VALID_MASK, ctxt->valid) | - FIELD_SET(INTR_CTXT_DATA_W0_VEC_MASK, ctxt->vec) | - FIELD_SET(INTR_CTXT_DATA_W0_INT_ST_MASK, ctxt->int_st) | - FIELD_SET(INTR_CTXT_DATA_W0_COLOR_MASK, ctxt->color) | - FIELD_SET(INTR_CTXT_DATA_W0_BADDR_4K_L_MASK, baddr_l); - - intr_ctxt[num_words_count++] = - FIELD_SET(INTR_CTXT_DATA_W1_BADDR_4K_M_MASK, baddr_m); - - intr_ctxt[num_words_count++] = - FIELD_SET(INTR_CTXT_DATA_W2_BADDR_4K_H_MASK, baddr_h) | - FIELD_SET(INTR_CTXT_DATA_W2_PAGE_SIZE_MASK, ctxt->page_size) | - FIELD_SET(INTR_CTXT_DATA_W2_PIDX_MASK, ctxt->pidx) | - FIELD_SET(INTR_CTXT_DATA_W2_AT_MASK, ctxt->at) | - FIELD_SET(INTR_CTXT_DATA_W2_HOST_ID_MASK, ctxt->host_id) | - FIELD_SET(INTR_CTXT_DATA_W2_PASID_L_MASK, pasid_l); - - intr_ctxt[num_words_count++] = - FIELD_SET(INTR_CTXT_DATA_W3_PASID_H_MASK, pasid_h) | - FIELD_SET(INTR_CTXT_DATA_W3_PASID_EN_MASK, ctxt->pasid_en) | - FIELD_SET(INTR_CTXT_DATA_W3_FUNC_MASK, ctxt->func_id); - - return eqdma_cpm5_indirect_reg_write(dev_hndl, sel, ring_index, - intr_ctxt, num_words_count); -} - -/*****************************************************************************/ -/** - * eqdma_cpm5_indirect_intr_context_read() - read indirect interrupt - * context - * - * @dev_hndl: device handle - * @ring_index: indirect interrupt ring index - * @ctxt: pointer to the output context data - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -static int eqdma_cpm5_indirect_intr_context_read(void *dev_hndl, - uint16_t ring_index, struct qdma_indirect_intr_ctxt *ctxt) -{ - int rv = QDMA_SUCCESS; - uint32_t intr_ctxt[EQDMA_CPM5_IND_INTR_CONTEXT_NUM_WORDS] = {0}; - enum ind_ctxt_cmd_sel sel = QDMA_CTXT_SEL_INT_COAL; - uint64_t baddr_l, baddr_m, baddr_h, pasid_l, pasid_h; - - if (!dev_hndl || !ctxt) { - qdma_log_error("%s: dev_hndl=%p intr_ctxt=%p, err:%d\n", - __func__, dev_hndl, ctxt, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - rv = eqdma_cpm5_indirect_reg_read(dev_hndl, sel, ring_index, - EQDMA_CPM5_IND_INTR_CONTEXT_NUM_WORDS, intr_ctxt); - if (rv < 0) - return rv; - - ctxt->valid = FIELD_GET(INTR_CTXT_DATA_W0_VALID_MASK, intr_ctxt[0]); - ctxt->vec = FIELD_GET(INTR_CTXT_DATA_W0_VEC_MASK, intr_ctxt[0]); - ctxt->int_st = - (uint8_t)(FIELD_GET(INTR_CTXT_DATA_W0_INT_ST_MASK, - intr_ctxt[0])); - ctxt->color = - (uint8_t)(FIELD_GET(INTR_CTXT_DATA_W0_COLOR_MASK, - intr_ctxt[0])); - baddr_l = FIELD_GET(INTR_CTXT_DATA_W0_BADDR_4K_L_MASK, intr_ctxt[0]); - - baddr_m = FIELD_GET(INTR_CTXT_DATA_W1_BADDR_4K_M_MASK, intr_ctxt[1]); - - baddr_h = FIELD_GET(INTR_CTXT_DATA_W2_BADDR_4K_H_MASK, intr_ctxt[2]); - ctxt->page_size = - FIELD_GET(INTR_CTXT_DATA_W2_PAGE_SIZE_MASK, intr_ctxt[2]); - ctxt->pidx = - (uint16_t)(FIELD_GET(INTR_CTXT_DATA_W2_PIDX_MASK, - intr_ctxt[2])); - ctxt->at = - (uint8_t)(FIELD_GET(INTR_CTXT_DATA_W2_AT_MASK, intr_ctxt[2])); - ctxt->host_id = (uint8_t)(FIELD_GET(INTR_CTXT_DATA_W2_HOST_ID_MASK, - intr_ctxt[2])); - pasid_l = (uint8_t)(FIELD_GET(INTR_CTXT_DATA_W2_PASID_L_MASK, - intr_ctxt[2])); - - pasid_h = FIELD_GET(INTR_CTXT_DATA_W3_PASID_H_MASK, intr_ctxt[3]); - ctxt->pasid_en = (uint8_t)FIELD_GET(INTR_CTXT_DATA_W3_PASID_EN_MASK, - intr_ctxt[3]); - - ctxt->func_id = (uint16_t)FIELD_GET(INTR_CTXT_DATA_W3_FUNC_MASK, - intr_ctxt[3]); - - ctxt->baddr_4k = - FIELD_SET(QDMA_INTR_CTXT_BADDR_GET_L_MASK, baddr_l) | - FIELD_SET(QDMA_INTR_CTXT_BADDR_GET_M_MASK, baddr_m) | - FIELD_SET(QDMA_INTR_CTXT_BADDR_GET_H_MASK, baddr_h); - - ctxt->pasid = - FIELD_SET(EQDMA_CPM5_INTR_CTXT_PASID_GET_L_MASK, pasid_l) | - FIELD_SET(EQDMA_CPM5_INTR_CTXT_PASID_GET_H_MASK, pasid_h); - - return QDMA_SUCCESS; -} - -/*****************************************************************************/ -/** - * eqdma_cpm5_indirect_intr_context_clear() - clear indirect interrupt - * context - * - * @dev_hndl: device handle - * @ring_index: indirect interrupt ring index - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -static int eqdma_cpm5_indirect_intr_context_clear(void *dev_hndl, - uint16_t ring_index) -{ - enum ind_ctxt_cmd_sel sel = QDMA_CTXT_SEL_INT_COAL; - - if (!dev_hndl) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", __func__, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - return eqdma_cpm5_indirect_reg_clear(dev_hndl, sel, ring_index); -} - -/*****************************************************************************/ -/** - * eqdma_cpm5_indirect_intr_context_invalidate() - invalidate indirect - * interrupt context - * - * @dev_hndl: device handle - * @ring_index: indirect interrupt ring index - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -static int eqdma_cpm5_indirect_intr_context_invalidate(void *dev_hndl, - uint16_t ring_index) -{ - enum ind_ctxt_cmd_sel sel = QDMA_CTXT_SEL_INT_COAL; - - if (!dev_hndl) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", __func__, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - return eqdma_cpm5_indirect_reg_invalidate(dev_hndl, sel, - ring_index); -} - -/*****************************************************************************/ -/** - * eqdma_cpm5_indirect_intr_ctx_conf() - configure indirect interrupt - * context - * - * @dev_hndl: device handle - * @ring_index: indirect interrupt ring index - * @ctxt: pointer to context data - * @access_type HW access type (qdma_hw_access_type enum) value - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -int eqdma_cpm5_indirect_intr_ctx_conf(void *dev_hndl, uint16_t ring_index, - struct qdma_indirect_intr_ctxt *ctxt, - enum qdma_hw_access_type access_type) -{ - int rv = QDMA_SUCCESS; - - switch (access_type) { - case QDMA_HW_ACCESS_READ: - rv = eqdma_cpm5_indirect_intr_context_read(dev_hndl, - ring_index, ctxt); - break; - case QDMA_HW_ACCESS_WRITE: - rv = eqdma_cpm5_indirect_intr_context_write(dev_hndl, - ring_index, ctxt); - break; - case QDMA_HW_ACCESS_CLEAR: - rv = eqdma_cpm5_indirect_intr_context_clear(dev_hndl, - ring_index); - break; - case QDMA_HW_ACCESS_INVALIDATE: - rv = eqdma_cpm5_indirect_intr_context_invalidate(dev_hndl, - ring_index); - break; - default: - qdma_log_error("%s: access_type=%d is invalid, err:%d\n", - __func__, access_type, - -QDMA_ERR_INV_PARAM); - rv = -QDMA_ERR_INV_PARAM; - break; - } - - return rv; -} - -/*****************************************************************************/ -/** - * eqdma_cpm5_dump_config_regs() - Function to get qdma config register - * dump in a buffer - * - * @dev_hndl: device handle - * @is_vf: Whether PF or VF - * @buf : pointer to buffer to be filled - * @buflen : Length of the buffer - * - * Return: Length up-till the buffer is filled -success and < 0 - failure - *****************************************************************************/ -int eqdma_cpm5_dump_config_regs(void *dev_hndl, uint8_t is_vf, - char *buf, uint32_t buflen) -{ - uint32_t i = 0, j = 0; - struct xreg_info *reg_info; - uint32_t num_regs = eqdma_cpm5_config_num_regs_get(); - uint32_t len = 0, val = 0; - int rv = QDMA_SUCCESS; - char name[DEBGFS_GEN_NAME_SZ] = ""; - struct qdma_dev_attributes dev_cap; - - if (!dev_hndl) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - if (buflen < eqdma_cpm5_reg_dump_buf_len()) { - qdma_log_error("%s: Buffer too small, err:%d\n", - __func__, -QDMA_ERR_NO_MEM); - return -QDMA_ERR_NO_MEM; - } - - if (is_vf) { - qdma_log_error("%s: Wrong API used for VF, err:%d\n", - __func__, - -QDMA_ERR_HWACC_FEATURE_NOT_SUPPORTED); - return -QDMA_ERR_HWACC_FEATURE_NOT_SUPPORTED; - } - - eqdma_cpm5_get_device_attributes(dev_hndl, &dev_cap); - - reg_info = eqdma_cpm5_config_regs_get(); - - for (i = 0; i < num_regs; i++) { - if ((GET_CAPABILITY_MASK(dev_cap.mm_en, dev_cap.st_en, - dev_cap.mm_cmpt_en, dev_cap.mailbox_en) - & reg_info[i].mode) == 0) - continue; - - /* If Debug Mode not enabled and the current register - * is debug register, skip reading it. - */ - if (dev_cap.debug_mode == 0 && - reg_info[i].is_debug_reg == 1) - continue; - - for (j = 0; j < reg_info[i].repeat; j++) { - rv = QDMA_SNPRINTF_S(name, DEBGFS_GEN_NAME_SZ, - DEBGFS_GEN_NAME_SZ, - "%s", reg_info[i].name); - if ((rv < 0) || (rv > DEBGFS_GEN_NAME_SZ)) { - qdma_log_error( - "%d:%s QDMA_SNPRINTF_S() failed, err:%d\n", - __LINE__, __func__, - rv); - return -QDMA_ERR_NO_MEM; - } - val = qdma_reg_read(dev_hndl, - (reg_info[i].addr + (j * 4))); - rv = dump_reg(buf + len, buflen - len, - (reg_info[i].addr + (j * 4)), - name, val); - if (rv < 0) { - qdma_log_error( - "%s Buff too small, err:%d\n", - __func__, - -QDMA_ERR_NO_MEM); - return -QDMA_ERR_NO_MEM; - } - len += rv; - } - } - - return len; -} - -/*****************************************************************************/ -/** - * qdma_dump_cpm_queue_context() - Function to get qdma queue context dump - * in a buffer - * - * @dev_hndl: device handle - * @st: Queue Mode(ST or MM) - * @q_type: Queue type(H2C/C2H/CMPT) - * @context: Queue Context - * @buf : pointer to buffer to be filled - * @buflen : Length of the buffer - * - * Return: Length up-till the buffer is filled -success and < 0 - failure - *****************************************************************************/ -int eqdma_cpm5_dump_queue_context(void *dev_hndl, - uint8_t st, - enum qdma_dev_q_type q_type, - struct qdma_descq_context *ctxt_data, - char *buf, uint32_t buflen) -{ - int rv = 0; - uint32_t req_buflen = 0; - - if (!dev_hndl) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - - return -QDMA_ERR_INV_PARAM; - } - - if (!ctxt_data) { - qdma_log_error("%s: ctxt_data is NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - - return -QDMA_ERR_INV_PARAM; - } - - if (!buf) { - qdma_log_error("%s: buf is NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - - return -QDMA_ERR_INV_PARAM; - } - - if (q_type >= QDMA_DEV_Q_TYPE_MAX) { - qdma_log_error("%s: invalid q_type, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - - return -QDMA_ERR_INV_PARAM; - } - - rv = eqdma_cpm5_context_buf_len(st, q_type, &req_buflen); - if (rv != QDMA_SUCCESS) - return rv; - - if (buflen < req_buflen) { - qdma_log_error("%s: Too small buffer(%d), reqd(%d), err:%d\n", - __func__, buflen, req_buflen, -QDMA_ERR_NO_MEM); - return -QDMA_ERR_NO_MEM; - } - - rv = dump_eqdma_cpm5_context(ctxt_data, st, q_type, - buf, buflen); - - return rv; -} - -/*****************************************************************************/ -/** - * eqdma_cpm5_dump_intr_context() - Function to get qdma interrupt context - * dump in a buffer - * - * @dev_hndl: device handle - * @intr_ctx: Interrupt Context - * @ring_index: Ring index - * @buf : pointer to buffer to be filled - * @buflen : Length of the buffer - * - * Return: Length up-till the buffer is filled -success and < 0 - failure - *****************************************************************************/ -int eqdma_cpm5_dump_intr_context(void *dev_hndl, - struct qdma_indirect_intr_ctxt *intr_ctx, - int ring_index, - char *buf, uint32_t buflen) -{ - int rv = 0; - uint32_t req_buflen = 0; - - if (!dev_hndl) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - - return -QDMA_ERR_INV_PARAM; - } - if (!intr_ctx) { - qdma_log_error("%s: intr_ctx is NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - if (!buf) { - qdma_log_error("%s: buf is NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - req_buflen = eqdma_cpm5_intr_context_buf_len(); - if (buflen < req_buflen) { - qdma_log_error("%s: Too small buffer(%d), reqd(%d), err:%d\n", - __func__, buflen, req_buflen, -QDMA_ERR_NO_MEM); - return -QDMA_ERR_NO_MEM; - } - - rv = dump_eqdma_cpm5_intr_context(intr_ctx, ring_index, buf, - buflen); - - return rv; -} - -/*****************************************************************************/ -/** - * eqdma_cpm5_read_dump_queue_context() - Function to read and dump the - * queue context in a buffer - * - * @dev_hndl: device handle - * @func_id: function id - * @hw_qid: queue id - * @st: Queue Mode(ST or MM) - * @q_type: Queue type(H2C/C2H/CMPT) - * @buf : pointer to buffer to be filled - * @buflen : Length of the buffer - * - * Return: Length up-till the buffer is filled -success and < 0 - failure - *****************************************************************************/ -int eqdma_cpm5_read_dump_queue_context(void *dev_hndl, - uint16_t func_id, - uint16_t qid_hw, - uint8_t st, - enum qdma_dev_q_type q_type, - char *buf, uint32_t buflen) -{ - int rv = QDMA_SUCCESS; - uint32_t req_buflen = 0; - struct qdma_descq_context context; - - if (!dev_hndl) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - - return -QDMA_ERR_INV_PARAM; - } - - if (!buf) { - qdma_log_error("%s: buf is NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - - return -QDMA_ERR_INV_PARAM; - } - - if (q_type >= QDMA_DEV_Q_TYPE_MAX) { - qdma_log_error("%s: Not supported for q_type, err = %d\n", - __func__, -QDMA_ERR_INV_PARAM); - - return -QDMA_ERR_INV_PARAM; - } - - rv = eqdma_cpm5_context_buf_len(st, q_type, &req_buflen); - if (rv != QDMA_SUCCESS) - return rv; - - if (buflen < req_buflen) { - qdma_log_error("%s: Too small buffer(%d), reqd(%d), err:%d\n", - __func__, buflen, req_buflen, -QDMA_ERR_NO_MEM); - return -QDMA_ERR_NO_MEM; - } - - qdma_memset(&context, 0, sizeof(struct qdma_descq_context)); - - if (q_type != QDMA_DEV_Q_TYPE_CMPT) { - rv = eqdma_cpm5_sw_ctx_conf(dev_hndl, (uint8_t)q_type, - qid_hw, &(context.sw_ctxt), - QDMA_HW_ACCESS_READ); - if (rv < 0) { - qdma_log_error( - "%s: Failed to read sw context, err = %d", - __func__, rv); - return rv; - } - - rv = eqdma_cpm5_hw_ctx_conf(dev_hndl, (uint8_t)q_type, - qid_hw, &(context.hw_ctxt), - QDMA_HW_ACCESS_READ); - if (rv < 0) { - qdma_log_error( - "%s: Failed to read hw context, err = %d", - __func__, rv); - return rv; - } - - rv = eqdma_cpm5_credit_ctx_conf(dev_hndl, (uint8_t)q_type, - qid_hw, &(context.cr_ctxt), - QDMA_HW_ACCESS_READ); - if (rv < 0) { - qdma_log_error( - "%s: Failed to read credit context, err = %d", - __func__, rv); - return rv; - } - - if (st && (q_type == QDMA_DEV_Q_TYPE_C2H)) { - rv = eqdma_cpm5_pfetch_ctx_conf(dev_hndl, - qid_hw, - &(context.pfetch_ctxt), - QDMA_HW_ACCESS_READ); - if (rv < 0) { - qdma_log_error( - "%s: Failed to read pftech context, err = %d", - __func__, rv); - return rv; - } - } - } - - if ((st && (q_type == QDMA_DEV_Q_TYPE_C2H)) || - (!st && (q_type == QDMA_DEV_Q_TYPE_CMPT))) { - rv = eqdma_cpm5_cmpt_ctx_conf(dev_hndl, qid_hw, - &(context.cmpt_ctxt), - QDMA_HW_ACCESS_READ); - if (rv < 0) { - qdma_log_error( - "%s: Failed to read cmpt context, err = %d", - __func__, rv); - return rv; - } - } - - rv = eqdma_cpm5_fmap_conf(dev_hndl, func_id, - &(context.fmap), QDMA_HW_ACCESS_READ); - if (rv < 0) { - qdma_log_error( - "%s: Failed to read fmap context, err = %d", - __func__, rv); - return rv; - } - - rv = dump_eqdma_cpm5_context(&context, st, q_type, - buf, buflen); - - return rv; -} - -/*****************************************************************************/ -/** - * eqdma_cpm5_get_user_bar() - Function to get the AXI Master - * Lite(user bar) number - * - * @dev_hndl: device handle - * @is_vf: Whether PF or VF - * @func_id: function id of the PF - * @user_bar: pointer to hold the AXI Master Lite bar number - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -int eqdma_cpm5_get_user_bar(void *dev_hndl, uint8_t is_vf, - uint16_t func_id, uint8_t *user_bar) -{ - /* TODO: In future, user bar is identified using RR */ - if (!dev_hndl) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - - return -QDMA_ERR_INV_PARAM; - } - UNUSED(func_id); - UNUSED(is_vf); - - *user_bar = 2; - - return QDMA_SUCCESS; -} - -/*****************************************************************************/ -/** - * eqdma_cpm5_hw_ram_sbe_err_process() - Function to dump SBE error - * debug information - * - * @dev_hndl: device handle - * @buf: Bufffer for the debug info to be dumped in - * @buflen: Length of the buffer - * - * Return: void - *****************************************************************************/ -static void eqdma_cpm5_hw_ram_sbe_err_process(void *dev_hndl) -{ - eqdma_cpm5_dump_reg_info(dev_hndl, - EQDMA_CPM5_RAM_SBE_STS_A_ADDR, 1, NULL, 0); - eqdma_cpm5_dump_reg_info(dev_hndl, - EQDMA_CPM5_RAM_SBE_STS_1_A_ADDR, 1, NULL, 0); -} - -/*****************************************************************************/ -/** - * eqdma_cpm5_hw_ram_dbe_err_process() - Function to dump DBE error - * debug information - * - * @dev_hndl: device handle - * @buf: Bufffer for the debug info to be dumped in - * @buflen: Length of the buffer - * - * Return: void - *****************************************************************************/ -static void eqdma_cpm5_hw_ram_dbe_err_process(void *dev_hndl) -{ - eqdma_cpm5_dump_reg_info(dev_hndl, - EQDMA_CPM5_RAM_DBE_STS_A_ADDR, 1, NULL, 0); - eqdma_cpm5_dump_reg_info(dev_hndl, - EQDMA_CPM5_RAM_DBE_STS_1_A_ADDR, 1, NULL, 0); -} - -/*****************************************************************************/ -/** - * eqdma_cpm5_hw_desc_err_process() - Function to dump Descriptor - * Error information - * - * @dev_hndl: device handle - * @buf: Bufffer for the debug info to be dumped in - * @buflen: Length of the buffer - * - * Return: void - *****************************************************************************/ -static void eqdma_cpm5_hw_desc_err_process(void *dev_hndl) -{ - int i = 0; - uint32_t desc_err_reg_list[] = { - EQDMA_CPM5_GLBL_DSC_ERR_STS_ADDR, - EQDMA_CPM5_GLBL_DSC_ERR_LOG0_ADDR, - EQDMA_CPM5_GLBL_DSC_ERR_LOG1_ADDR, - EQDMA_CPM5_GLBL_DSC_DBG_DAT0_ADDR, - EQDMA_CPM5_GLBL_DSC_DBG_DAT1_ADDR, - EQDMA_CPM5_GLBL_DSC_ERR_LOG2_ADDR - }; - int desc_err_num_regs = sizeof(desc_err_reg_list)/sizeof(uint32_t); - - for (i = 0; i < desc_err_num_regs; i++) { - eqdma_cpm5_dump_reg_info(dev_hndl, desc_err_reg_list[i], - 1, NULL, 0); - } -} - -/*****************************************************************************/ -/** - * eqdma_cpm5_hw_trq_err_process() - Function to dump Target Access - * Error information - * - * @dev_hndl: device handle - * @buf: Bufffer for the debug info to be dumped in - * @buflen: Length of the buffer - * - * Return: void - *****************************************************************************/ -static void eqdma_cpm5_hw_trq_err_process(void *dev_hndl) -{ - int i = 0; - uint32_t trq_err_reg_list[] = { - EQDMA_CPM5_GLBL_TRQ_ERR_STS_ADDR, - EQDMA_CPM5_GLBL_TRQ_ERR_LOG_ADDR - }; - int trq_err_reg_num_regs = sizeof(trq_err_reg_list)/sizeof(uint32_t); - - for (i = 0; i < trq_err_reg_num_regs; i++) { - eqdma_cpm5_dump_reg_info(dev_hndl, trq_err_reg_list[i], - 1, NULL, 0); - } -} - -/*****************************************************************************/ -/** - * eqdma_cpm5_hw_err_dump_ctxt_info() - Dump the imp ctxt fields on HW error - * - * @dev_hndl: device handle - * @first_err_qid: First Error QID - * @en_st: ST Mode or MM Mode enabled - * @c2h: C2H or H2C Mode - * - * Return: void - *****************************************************************************/ -static void eqdma_cpm5_hw_err_dump_ctxt_info(void *dev_hndl, - uint32_t first_err_qid_reg, - uint8_t en_st, uint8_t c2h) -{ - uint16_t first_err_qid = 0; - struct qdma_descq_sw_ctxt sw_ctxt; - struct qdma_descq_hw_ctxt hw_ctxt; - struct qdma_descq_cmpt_ctxt cmpt_ctxt; - - first_err_qid = qdma_reg_read(dev_hndl, first_err_qid_reg); - - eqdma_cpm5_sw_context_read(dev_hndl, c2h, first_err_qid, &sw_ctxt); - eqdma_cpm5_hw_context_read(dev_hndl, c2h, first_err_qid, &hw_ctxt); - eqdma_cpm5_fill_sw_ctxt(&sw_ctxt); - eqdma_cpm5_fill_hw_ctxt(&hw_ctxt); - - if (sw_ctxt.pidx != hw_ctxt.cidx) { - qdma_log_info("\n%40s\n", "SW Context:"); - /** SW Context: PIDX ***/ - qdma_log_info("%-47s %#-10x %u\n", - eqdma_cpm5_sw_ctxt_entries[0].name, - eqdma_cpm5_sw_ctxt_entries[0].value, - eqdma_cpm5_sw_ctxt_entries[0].value); - qdma_log_info("\n%40s\n", "HW Context:"); - /*** HW Context: CIDX ***/ - qdma_log_info("%-47s %#-10x %u\n", - eqdma_cpm5_hw_ctxt_entries[0].name, - eqdma_cpm5_hw_ctxt_entries[0].value, - eqdma_cpm5_hw_ctxt_entries[0].value); - } - - if (sw_ctxt.err != 0) { - /*** SW Context: ERR ***/ - qdma_log_info("%-47s %#-10x %u\n", - eqdma_cpm5_sw_ctxt_entries[17].name, - eqdma_cpm5_sw_ctxt_entries[17].value, - eqdma_cpm5_sw_ctxt_entries[17].value); - } - - /*** SW Context: ERR WB SENT***/ - qdma_log_info("%-47s %#-10x %u\n", - eqdma_cpm5_sw_ctxt_entries[18].name, - eqdma_cpm5_sw_ctxt_entries[18].value, - eqdma_cpm5_sw_ctxt_entries[18].value); - - /*** SW Context: IRQ REQ***/ - qdma_log_info("%-47s %#-10x %u\n", - eqdma_cpm5_sw_ctxt_entries[19].name, - eqdma_cpm5_sw_ctxt_entries[19].value, - eqdma_cpm5_sw_ctxt_entries[19].value); - - if (en_st && c2h) { - eqdma_cpm5_cmpt_context_read(dev_hndl, - first_err_qid, &cmpt_ctxt); - eqdma_cpm5_fill_cmpt_ctxt(&cmpt_ctxt); - - qdma_log_info("\n%40s\n", "CMPT Context:"); - - /*** CMPT Context: int_st ***/ - qdma_log_info("%-47s %#-10x %u\n", - eqdma_cpm5_cmpt_ctxt_entries[6].name, - eqdma_cpm5_cmpt_ctxt_entries[6].value, - eqdma_cpm5_cmpt_ctxt_entries[6].value); - - /** CMPT Context: PIDX ***/ - qdma_log_info("%-47s %#-10x %u\n", - eqdma_cpm5_cmpt_ctxt_entries[12].name, - eqdma_cpm5_cmpt_ctxt_entries[12].value, - eqdma_cpm5_cmpt_ctxt_entries[12].value); - /*** CMPT Context: CIDX ***/ - qdma_log_info("%-47s %#-10x %u\n", - eqdma_cpm5_cmpt_ctxt_entries[13].name, - eqdma_cpm5_cmpt_ctxt_entries[13].value, - eqdma_cpm5_cmpt_ctxt_entries[13].value); - - if (cmpt_ctxt.err != 0) { - /*** CMPT Context: ERR ***/ - qdma_log_info("%-47s %#-10x %u\n", - eqdma_cpm5_cmpt_ctxt_entries[15].name, - eqdma_cpm5_cmpt_ctxt_entries[15].value, - eqdma_cpm5_cmpt_ctxt_entries[15].value); - } - } -} - -/*****************************************************************************/ -/** - * eqdma_cpm5_hw_st_h2c_err_process() - Function to dump MM H2C Error - * information - * - * @dev_hndl: device handle - * @buf: Bufffer for the debug info to be dumped in - * @buflen: Length of the buffer - * - * Return: void - *****************************************************************************/ -static void eqdma_cpm5_hw_st_h2c_err_process(void *dev_hndl) -{ - int i = 0; - uint32_t st_h2c_err_reg_list[] = { - EQDMA_CPM5_H2C_ERR_STAT_ADDR, - EQDMA_CPM5_H2C_FIRST_ERR_QID_ADDR, - EQDMA_CPM5_H2C_DBG_REG0_ADDR, - EQDMA_CPM5_H2C_DBG_REG1_ADDR, - EQDMA_CPM5_H2C_DBG_REG2_ADDR, - EQDMA_CPM5_H2C_DBG_REG3_ADDR, - EQDMA_CPM5_H2C_DBG_REG4_ADDR - }; - int st_h2c_err_num_regs = sizeof(st_h2c_err_reg_list)/sizeof(uint32_t); - - for (i = 0; i < st_h2c_err_num_regs; i++) { - eqdma_cpm5_dump_reg_info(dev_hndl, st_h2c_err_reg_list[i], - 1, NULL, 0); - } - - eqdma_cpm5_hw_err_dump_ctxt_info(dev_hndl, - EQDMA_CPM5_H2C_FIRST_ERR_QID_ADDR, 1, 1); -} - - -/*****************************************************************************/ -/** - * eqdma_cpm5_hw_st_c2h_err_process() - Function to dump MM H2C - * Error information - * - * @dev_hndl: device handle - * @buf: Bufffer for the debug info to be dumped in - * @buflen: Length of the buffer - * - * Return: void - *****************************************************************************/ -static void eqdma_cpm5_hw_st_c2h_err_process(void *dev_hndl) -{ - int i = 0; - uint32_t st_c2h_err_reg_list[] = { - EQDMA_CPM5_C2H_ERR_STAT_ADDR, - EQDMA_CPM5_C2H_FATAL_ERR_STAT_ADDR, - EQDMA_CPM5_C2H_FIRST_ERR_QID_ADDR, - EQDMA_CPM5_C2H_STAT_S_AXIS_C2H_ACCEPTED_ADDR, - EQDMA_CPM5_C2H_STAT_S_AXIS_WRB_ACCEPTED_ADDR, - EQDMA_CPM5_C2H_STAT_DESC_RSP_PKT_ACCEPTED_ADDR, - EQDMA_CPM5_C2H_STAT_AXIS_PKG_CMP_ADDR, - EQDMA_CPM5_C2H_STAT_DBG_DMA_ENG_0_ADDR, - EQDMA_CPM5_C2H_STAT_DBG_DMA_ENG_1_ADDR, - EQDMA_CPM5_C2H_STAT_DBG_DMA_ENG_2_ADDR, - EQDMA_CPM5_C2H_STAT_DBG_DMA_ENG_3_ADDR, - EQDMA_CPM5_C2H_STAT_DESC_RSP_DROP_ACCEPTED_ADDR, - EQDMA_CPM5_C2H_STAT_DESC_RSP_ERR_ACCEPTED_ADDR - }; - int st_c2h_err_num_regs = sizeof(st_c2h_err_reg_list)/sizeof(uint32_t); - - for (i = 0; i < st_c2h_err_num_regs; i++) { - eqdma_cpm5_dump_reg_info(dev_hndl, st_c2h_err_reg_list[i], - 1, NULL, 0); - } - - eqdma_cpm5_hw_err_dump_ctxt_info(dev_hndl, - EQDMA_CPM5_C2H_FIRST_ERR_QID_ADDR, 1, 1); -} - -/*****************************************************************************/ -/** - * eqdma_cpm5_mm_c2h0_err_process() - Function to dump MM C2H - * Error information - * - * @dev_hndl: device handle - * - * Return: void - *****************************************************************************/ -static void eqdma_cpm5_mm_c2h0_err_process(void *dev_hndl) -{ - int i = 0; - uint32_t mm_c2h_err_reg_list[] = { - EQDMA_CPM5_C2H_MM_STATUS_ADDR, - EQDMA_CPM5_C2H_MM_CMPL_DESC_CNT_ADDR, - EQDMA_CPM5_C2H_MM_ERR_CODE_ADDR, - EQDMA_CPM5_C2H_MM_ERR_INFO_ADDR, - EQDMA_CPM5_C2H_MM_DBG_ADDR - }; - int mm_c2h_err_num_regs = sizeof(mm_c2h_err_reg_list)/sizeof(uint32_t); - - for (i = 0; i < mm_c2h_err_num_regs; i++) { - eqdma_cpm5_dump_reg_info(dev_hndl, mm_c2h_err_reg_list[i], - 1, NULL, 0); - } - - eqdma_cpm5_hw_err_dump_ctxt_info(dev_hndl, - EQDMA_CPM5_C2H_MM_ERR_INFO_ADDR, 0, 1); -} - -/*****************************************************************************/ -/** - * eqdma_cpm5_mm_h2c0_err_process() - Function to dump MM H2C - * Error information - * - * @dev_hndl: device handle - * - * Return: void - *****************************************************************************/ -static void eqdma_cpm5_mm_h2c0_err_process(void *dev_hndl) -{ - int i = 0; - uint32_t mm_h2c_err_reg_list[] = { - EQDMA_CPM5_H2C_MM_STATUS_ADDR, - EQDMA_CPM5_H2C_MM_CMPL_DESC_CNT_ADDR, - EQDMA_CPM5_H2C_MM_ERR_CODE_ADDR, - EQDMA_CPM5_H2C_MM_ERR_INFO_ADDR, - EQDMA_CPM5_H2C_MM_DBG_ADDR - }; - int mm_h2c_err_num_regs = sizeof(mm_h2c_err_reg_list)/sizeof(uint32_t); - - for (i = 0; i < mm_h2c_err_num_regs; i++) { - eqdma_cpm5_dump_reg_info(dev_hndl, mm_h2c_err_reg_list[i], - 1, NULL, 0); - } - - eqdma_cpm5_hw_err_dump_ctxt_info(dev_hndl, - EQDMA_CPM5_H2C_MM_ERR_INFO_ADDR, 0, 1); -} - -/*****************************************************************************/ -/** - * eqdma_cpm5_hw_get_error_name() - Function to get the error in string - * format - * - * @err_idx: error index - * - * Return: string - success and NULL on failure - *****************************************************************************/ -const char *eqdma_cpm5_hw_get_error_name(uint32_t err_idx) -{ - if (err_idx >= EQDMA_CPM5_ERRS_ALL) { - qdma_log_error("%s: err_idx=%d is invalid, returning NULL\n", - __func__, - (enum eqdma_cpm5_error_idx)err_idx); - return NULL; - } - - return eqdma_cpm5_err_info[(enum - eqdma_cpm5_error_idx)err_idx].err_name; -} - -/*****************************************************************************/ -/** - * eqdma_cpm5_hw_error_process() - Function to find the error that got - * triggered and call the handler qdma_hw_error_handler of that - * particular error. - * - * @dev_hndl: device handle - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -int eqdma_cpm5_hw_error_process(void *dev_hndl) -{ - uint32_t glbl_err_stat = 0, err_stat = 0; - uint32_t bit = 0, i = 0; - int32_t idx = 0; - struct qdma_dev_attributes dev_cap; - uint32_t hw_err_position[ - EQDMA_CPM5_TOTAL_LEAF_ERROR_AGGREGATORS] = { - EQDMA_CPM5_DSC_ERR_POISON, - EQDMA_CPM5_TRQ_ERR_CSR_UNMAPPED, - EQDMA_CPM5_ST_C2H_ERR_MTY_MISMATCH, - EQDMA_CPM5_ST_FATAL_ERR_MTY_MISMATCH, - EQDMA_CPM5_ST_H2C_ERR_ZERO_LEN_DESC, - EQDMA_CPM5_SBE_1_ERR_RC_RRQ_EVEN_RAM, - EQDMA_CPM5_SBE_ERR_MI_H2C0_DAT, - EQDMA_CPM5_DBE_1_ERR_RC_RRQ_EVEN_RAM, - EQDMA_CPM5_DBE_ERR_MI_H2C0_DAT, - EQDMA_CPM5_MM_C2H_WR_SLR_ERR, - EQDMA_CPM5_MM_H2C0_RD_HDR_POISON_ERR - }; - - if (!dev_hndl) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - - eqdma_cpm5_get_device_attributes(dev_hndl, &dev_cap); - - glbl_err_stat = qdma_reg_read(dev_hndl, - EQDMA_CPM5_GLBL_ERR_STAT_ADDR); - - if (!glbl_err_stat) - return QDMA_HW_ERR_NOT_DETECTED; - - - qdma_log_info("%s: Global Err Reg(0x%x) = 0x%x\n", - __func__, EQDMA_CPM5_GLBL_ERR_STAT_ADDR, - glbl_err_stat); - - for (i = 0; i < EQDMA_CPM5_TOTAL_LEAF_ERROR_AGGREGATORS; i++) { - bit = hw_err_position[i]; - - if ((!dev_cap.st_en) && - (bit == EQDMA_CPM5_ST_C2H_ERR_MTY_MISMATCH || - bit == EQDMA_CPM5_ST_FATAL_ERR_MTY_MISMATCH || - bit == EQDMA_CPM5_ST_H2C_ERR_ZERO_LEN_DESC)) - continue; - - err_stat = qdma_reg_read(dev_hndl, - eqdma_cpm5_err_info[bit].stat_reg_addr); - if (err_stat) { - qdma_log_info("addr = 0x%08x val = 0x%08x", - eqdma_cpm5_err_info[bit].stat_reg_addr, - err_stat); - - eqdma_cpm5_err_info[ - bit].eqdma_cpm5_hw_err_process(dev_hndl); - for (idx = bit; idx < all_eqdma_cpm5_hw_errs[i]; - idx++) { - /* call the platform specific handler */ - if (err_stat & - eqdma_cpm5_err_info[idx].leaf_err_mask) - qdma_log_error("%s detected %s\n", - __func__, - eqdma_cpm5_hw_get_error_name(idx)); - } - qdma_reg_write(dev_hndl, - eqdma_cpm5_err_info[bit].stat_reg_addr, - err_stat); - } - - } - - /* Write 1 to the global status register to clear the bits */ - qdma_reg_write(dev_hndl, EQDMA_CPM5_GLBL_ERR_STAT_ADDR, - glbl_err_stat); - - return QDMA_SUCCESS; -} - -/*****************************************************************************/ -/** - * qdma_hw_error_enable() - Function to enable all or a specific error - * - * @dev_hndl: device handle - * @err_idx: error index - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -int eqdma_cpm5_hw_error_enable(void *dev_hndl, uint32_t err_idx) -{ - uint32_t idx = 0, i = 0; - uint32_t reg_val = 0; - struct qdma_dev_attributes dev_cap; - - if (!dev_hndl) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - if (err_idx > EQDMA_CPM5_ERRS_ALL) { - qdma_log_error("%s: err_idx=%d is invalid, err:%d\n", - __func__, - (enum eqdma_cpm5_error_idx)err_idx, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - eqdma_cpm5_get_device_attributes(dev_hndl, &dev_cap); - - if (err_idx == EQDMA_CPM5_ERRS_ALL) { - for (i = 0; i < EQDMA_CPM5_TOTAL_LEAF_ERROR_AGGREGATORS; - i++) { - - idx = all_eqdma_cpm5_hw_errs[i]; - - /* Don't access streaming registers in - * MM only bitstreams - */ - if (!dev_cap.st_en) { - if (idx == EQDMA_CPM5_ST_C2H_ERR_ALL || - idx == EQDMA_CPM5_ST_FATAL_ERR_ALL - || idx == EQDMA_CPM5_ST_H2C_ERR_ALL) - continue; - } - - reg_val = eqdma_cpm5_err_info[idx].leaf_err_mask; - qdma_reg_write(dev_hndl, - eqdma_cpm5_err_info[idx].mask_reg_addr, - reg_val); - - reg_val = qdma_reg_read(dev_hndl, - EQDMA_CPM5_GLBL_ERR_MASK_ADDR); - reg_val |= FIELD_SET( - eqdma_cpm5_err_info[idx].global_err_mask, - 1); - qdma_reg_write(dev_hndl, - EQDMA_CPM5_GLBL_ERR_MASK_ADDR, - reg_val); - } - - } else { - /* Don't access streaming registers in MM only bitstreams - * QDMA_C2H_ERR_MTY_MISMATCH to QDMA_H2C_ERR_ALL are all - * ST errors - */ - if (!dev_cap.st_en) { - if (err_idx >= EQDMA_CPM5_ST_C2H_ERR_MTY_MISMATCH - && err_idx <= - EQDMA_CPM5_ST_H2C_ERR_ALL) - return QDMA_SUCCESS; - } - - reg_val = qdma_reg_read(dev_hndl, - eqdma_cpm5_err_info[err_idx].mask_reg_addr); - reg_val |= - FIELD_SET( - eqdma_cpm5_err_info[err_idx].leaf_err_mask, - 1); - qdma_reg_write(dev_hndl, - eqdma_cpm5_err_info[err_idx].mask_reg_addr, - reg_val); - - reg_val = qdma_reg_read(dev_hndl, - EQDMA_CPM5_GLBL_ERR_MASK_ADDR); - reg_val |= - FIELD_SET - (eqdma_cpm5_err_info[err_idx].global_err_mask, 1); - qdma_reg_write(dev_hndl, EQDMA_CPM5_GLBL_ERR_MASK_ADDR, - reg_val); - } - - return QDMA_SUCCESS; -} - -/*****************************************************************************/ -/** - * eqdma_cpm5_get_device_attributes() - Function to get the qdma device - * attributes - * - * @dev_hndl: device handle - * @dev_info: pointer to hold the device info - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -int eqdma_cpm5_get_device_attributes(void *dev_hndl, - struct qdma_dev_attributes *dev_info) -{ - uint32_t reg_val = 0; - - if (!dev_hndl) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - if (!dev_info) { - qdma_log_error("%s: dev_info is NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - /* number of PFs */ - reg_val = qdma_reg_read(dev_hndl, QDMA_OFFSET_GLBL2_PF_BARLITE_INT); - dev_info->num_pfs = FIELD_GET(QDMA_GLBL2_PF0_BAR_MAP_MASK, reg_val); - - /* Number of Qs */ - reg_val = qdma_reg_read(dev_hndl, - EQDMA_CPM5_GLBL2_CHANNEL_CAP_ADDR); - dev_info->num_qs = - FIELD_GET(GLBL2_CHANNEL_CAP_MULTIQ_MAX_MASK, reg_val); - - /* There are 12 bits assigned in EQDMA_CPM5_GLBL2_CHANNEL_CAP_ADDR - * to represent the num_qs. For CPM5, max queues can be 4096 which needs - * 13 bits(0x1000). Adding a hack in driver to represent 4096 queues - * when HW sets the num_qs to 0xFFF - */ - if (dev_info->num_qs == 0xFFF) - dev_info->num_qs++; - - /* FLR present */ - reg_val = qdma_reg_read(dev_hndl, EQDMA_CPM5_GLBL2_MISC_CAP_ADDR); - dev_info->mailbox_en = FIELD_GET(EQDMA_CPM5_GLBL2_MAILBOX_EN_MASK, - reg_val); - dev_info->flr_present = FIELD_GET(EQDMA_CPM5_GLBL2_FLR_PRESENT_MASK, - reg_val); - dev_info->mm_cmpt_en = 0; - dev_info->debug_mode = FIELD_GET(EQDMA_CPM5_GLBL2_DBG_MODE_EN_MASK, - reg_val); - dev_info->desc_eng_mode = - FIELD_GET(EQDMA_CPM5_GLBL2_DESC_ENG_MODE_MASK, - reg_val); - - /* ST/MM enabled? */ - reg_val = qdma_reg_read(dev_hndl, - EQDMA_CPM5_GLBL2_CHANNEL_MDMA_ADDR); - dev_info->st_en = (FIELD_GET(GLBL2_CHANNEL_MDMA_C2H_ST_MASK, reg_val) - && FIELD_GET(GLBL2_CHANNEL_MDMA_H2C_ST_MASK, reg_val)) ? 1 : 0; - dev_info->mm_en = (FIELD_GET(GLBL2_CHANNEL_MDMA_C2H_ENG_MASK, reg_val) - && FIELD_GET(GLBL2_CHANNEL_MDMA_H2C_ENG_MASK, reg_val)) ? 1 : 0; - - /* num of mm channels */ - /* TODO : Register not yet defined for this. - * Hard coding it to 2 for CPM5 - */ - dev_info->mm_channel_max = 2; - - dev_info->qid2vec_ctx = 0; - dev_info->cmpt_ovf_chk_dis = 1; - dev_info->mailbox_intr = 1; - dev_info->sw_desc_64b = 1; - dev_info->cmpt_desc_64b = 1; - dev_info->dynamic_bar = 1; - dev_info->legacy_intr = 1; - dev_info->cmpt_trig_count_timer = 1; - - return QDMA_SUCCESS; -} - -/*****************************************************************************/ -/** - * eqdma_cpm5_init_ctxt_memory() - function to initialize the context - * memory - * - * @dev_hndl: device handle - * - * Return: returns the platform specific error code - *****************************************************************************/ -int eqdma_cpm5_init_ctxt_memory(void *dev_hndl) -{ -#ifdef ENABLE_INIT_CTXT_MEMORY - uint32_t data[QDMA_REG_IND_CTXT_REG_COUNT]; - uint16_t i = 0; - struct qdma_dev_attributes dev_info; - - if (!dev_hndl) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - qdma_memset(data, 0, sizeof(uint32_t) * QDMA_REG_IND_CTXT_REG_COUNT); - eqdma_cpm5_get_device_attributes(dev_hndl, &dev_info); - - for (; i < dev_info.num_qs; i++) { - int sel = QDMA_CTXT_SEL_SW_C2H; - int rv; - -#ifdef TANDEM_BOOT_SUPPORTED - for (; sel <= QDMA_CTXT_SEL_CR_H2C; sel++) { - rv = eqdma_cpm5_indirect_reg_clear(dev_hndl, - (enum ind_ctxt_cmd_sel)sel, i); - if (rv < 0) - return rv; - } -#else - for (; sel <= QDMA_CTXT_SEL_PFTCH; sel++) { - /** TODO: Check for Tandem boot **/ - /** if the st mode(h2c/c2h) not enabled - * in the design, then skip the PFTCH - * and CMPT context setup - */ - if ((dev_info.st_en == 0) && - ((sel == QDMA_CTXT_SEL_PFTCH) || - (sel == QDMA_CTXT_SEL_CMPT))) { - qdma_log_debug("%s: ST context is skipped:", - __func__); - qdma_log_debug("sel = %d\n", sel); - continue; - } - - rv = eqdma_cpm5_indirect_reg_clear(dev_hndl, - (enum ind_ctxt_cmd_sel)sel, i); - if (rv < 0) - return rv; - } -#endif - } - - /* fmap */ - for (i = 0; i < dev_info.num_pfs; i++) - eqdma_cpm5_indirect_reg_clear(dev_hndl, - QDMA_CTXT_SEL_FMAP, i); - -#else - if (!dev_hndl) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } -#endif - return QDMA_SUCCESS; - -} - -#ifdef TANDEM_BOOT_SUPPORTED -/*****************************************************************************/ -/** - * eqdma_cpm5_init_st_ctxt() - Initialize the ST context - * - * @dev_hndl: device handle - * - * Return: returns the platform specific error code - *****************************************************************************/ -int eqdma_cpm5_init_st_ctxt(void *dev_hndl) -{ - uint32_t data[QDMA_REG_IND_CTXT_REG_COUNT]; - uint16_t i = 0; - struct qdma_dev_attributes dev_info; - - if (!dev_hndl) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - qdma_memset(data, 0, sizeof(uint32_t) * QDMA_REG_IND_CTXT_REG_COUNT); - eqdma_cpm5_get_device_attributes(dev_hndl, &dev_info); - - for (; i < dev_info.num_qs; i++) { - int sel = QDMA_CTXT_SEL_CMPT; - int rv; - - for (; sel <= QDMA_CTXT_SEL_PFTCH; sel++) { - /** if the st mode(h2c/c2h) not enabled - * in the design, then skip the PFTCH - * and CMPT context setup - */ - if ((dev_info.st_en == 0) && - ((sel == QDMA_CTXT_SEL_PFTCH) || - (sel == QDMA_CTXT_SEL_CMPT))) { - qdma_log_debug("%s: ST context is skipped:", - __func__); - qdma_log_debug("sel = %d\n", sel); - continue; - } - - rv = eqdma_cpm5_indirect_reg_clear(dev_hndl, - (enum ind_ctxt_cmd_sel)sel, i); - if (rv < 0) - return rv; - } - } - - return QDMA_SUCCESS; - -} -#endif - -static int get_reg_entry(uint32_t reg_addr, int *reg_entry) -{ - uint32_t i = 0; - struct xreg_info *reg_info; - uint32_t num_regs = eqdma_cpm5_config_num_regs_get(); - - reg_info = eqdma_cpm5_config_regs_get(); - - for (i = 0; (i < num_regs - 1); i++) { - if (reg_info[i].addr == reg_addr) { - *reg_entry = i; - break; - } - } - - if (i >= num_regs - 1) { - qdma_log_error("%s: 0x%08x is missing register list, err:%d\n", - __func__, - reg_addr, - -QDMA_ERR_INV_PARAM); - *reg_entry = -1; - return -QDMA_ERR_INV_PARAM; - } - - return 0; -} - -/*****************************************************************************/ -/** - * eqdma_cpm5_dump_config_reg_list() - Dump the registers - * - * @dev_hndl: device handle - * @total_regs : Max registers to read - * @reg_list : array of reg addr and reg values - * @buf : pointer to buffer to be filled - * @buflen : Length of the buffer - * - * Return: returns the platform specific error code - *****************************************************************************/ -int eqdma_cpm5_dump_config_reg_list(void *dev_hndl, uint32_t total_regs, - struct qdma_reg_data *reg_list, char *buf, uint32_t buflen) -{ - uint32_t j = 0, len = 0; - uint32_t reg_count = 0; - int reg_data_entry; - int rv = 0; - char name[DEBGFS_GEN_NAME_SZ] = ""; - struct xreg_info *reg_info = eqdma_cpm5_config_regs_get(); - struct qdma_dev_attributes dev_cap; - - if (!dev_hndl) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - if (!buf) { - qdma_log_error("%s: buf is NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - eqdma_cpm5_get_device_attributes(dev_hndl, &dev_cap); - - for (reg_count = 0; - (reg_count < total_regs);) { - - /* If Debug Mode not enabled and the current register - * is debug register, skip reading it. - */ - if (dev_cap.debug_mode == 0 && - reg_info[reg_count].is_debug_reg == 1) - continue; - - rv = get_reg_entry(reg_list[reg_count].reg_addr, - ®_data_entry); - if (rv < 0) { - qdma_log_error("%s: register missing in list, err:%d\n", - __func__, - -QDMA_ERR_INV_PARAM); - return rv; - } - - for (j = 0; j < reg_info[reg_data_entry].repeat; j++) { - rv = QDMA_SNPRINTF_S(name, DEBGFS_GEN_NAME_SZ, - DEBGFS_GEN_NAME_SZ, - "%s_%d", - reg_info[reg_data_entry].name, j); - if ((rv < 0) || (rv > DEBGFS_GEN_NAME_SZ)) { - qdma_log_error( - "%d:%s snprintf failed, err:%d\n", - __LINE__, __func__, - rv); - return -QDMA_ERR_NO_MEM; - } - rv = dump_reg(buf + len, buflen - len, - (reg_info[reg_data_entry].addr + (j * 4)), - name, - reg_list[reg_count + j].reg_val); - if (rv < 0) { - qdma_log_error( - "%s Buff too small, err:%d\n", - __func__, - -QDMA_ERR_NO_MEM); - return -QDMA_ERR_NO_MEM; - } - len += rv; - } - reg_count += j; - } - - return len; - -} - - -/*****************************************************************************/ -/** - * qdma_read_reg_list() - read the register values - * - * @dev_hndl: device handle - * @is_vf: Whether PF or VF - * @total_regs : Max registers to read - * @reg_list : array of reg addr and reg values - * - * Return: returns the platform specific error code - *****************************************************************************/ -int eqdma_cpm5_read_reg_list(void *dev_hndl, uint8_t is_vf, - uint16_t reg_rd_group, - uint16_t *total_regs, - struct qdma_reg_data *reg_list) -{ - uint16_t reg_count = 0, i = 0, j = 0; - struct xreg_info *reg_info; - uint32_t num_regs = eqdma_cpm5_config_num_regs_get(); - struct xreg_info *eqdma_cpm5_config_regs = - eqdma_cpm5_config_regs_get(); - struct qdma_dev_attributes dev_cap; - uint32_t reg_start_addr = 0; - int reg_index = 0; - int rv = 0; - - if (!is_vf) { - qdma_log_error("%s: not supported for PF, err:%d\n", - __func__, - -QDMA_ERR_HWACC_FEATURE_NOT_SUPPORTED); - return -QDMA_ERR_HWACC_FEATURE_NOT_SUPPORTED; - } - - if (!dev_hndl) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - if (!reg_list) { - qdma_log_error("%s: reg_list is NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - eqdma_cpm5_get_device_attributes(dev_hndl, &dev_cap); - - switch (reg_rd_group) { - case QDMA_REG_READ_GROUP_1: - reg_start_addr = EQDMA_CPM5_REG_GROUP_1_START_ADDR; - break; - case QDMA_REG_READ_GROUP_2: - reg_start_addr = EQDMA_CPM5_REG_GROUP_2_START_ADDR; - break; - case QDMA_REG_READ_GROUP_3: - reg_start_addr = EQDMA_CPM5_REG_GROUP_3_START_ADDR; - break; - case QDMA_REG_READ_GROUP_4: - reg_start_addr = EQDMA_CPM5_REG_GROUP_4_START_ADDR; - break; - default: - qdma_log_error("%s: Invalid slot received\n", - __func__); - return -QDMA_ERR_INV_PARAM; - } - - rv = get_reg_entry(reg_start_addr, ®_index); - if (rv < 0) { - qdma_log_error("%s: register missing in list, err:%d\n", - __func__, - -QDMA_ERR_INV_PARAM); - return rv; - } - reg_info = &eqdma_cpm5_config_regs[reg_index]; - - for (i = 0, reg_count = 0; - ((i < num_regs - 1 - reg_index) && - (reg_count < QDMA_MAX_REGISTER_DUMP)); i++) { - - if (((GET_CAPABILITY_MASK(dev_cap.mm_en, dev_cap.st_en, - dev_cap.mm_cmpt_en, dev_cap.mailbox_en) - & reg_info[i].mode) == 0) || - (reg_info[i].read_type == QDMA_REG_READ_PF_ONLY)) - continue; - - /* If Debug Mode not enabled and the current register - * is debug register, skip reading it. - */ - if (dev_cap.debug_mode == 0 && - reg_info[i].is_debug_reg == 1) - continue; - - for (j = 0; j < reg_info[i].repeat && - (reg_count < QDMA_MAX_REGISTER_DUMP); - j++) { - reg_list[reg_count].reg_addr = - (reg_info[i].addr + (j * 4)); - reg_list[reg_count].reg_val = - qdma_reg_read(dev_hndl, - reg_list[reg_count].reg_addr); - reg_count++; - } - } - - *total_regs = reg_count; - return rv; -} - -/*****************************************************************************/ -/** - * eqdma_cpm5_write_global_ring_sizes() - function to set the global ring - * size array - * - * @dev_hndl: device handle - * @index: Index from where the values needs to written - * @count: number of entries to be written - * @glbl_rng_sz: pointer to the array having the values to write - * - * (index + count) shall not be more than 16 - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -static int eqdma_cpm5_write_global_ring_sizes(void *dev_hndl, uint8_t index, - uint8_t count, const uint32_t *glbl_rng_sz) -{ - if (!dev_hndl || !glbl_rng_sz || !count) { - qdma_log_error("%s: dev_hndl=%p glbl_rng_sz=%p, err:%d\n", - __func__, dev_hndl, glbl_rng_sz, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - if ((index + count) > QDMA_NUM_RING_SIZES) { - qdma_log_error("%s: index=%u count=%u > %d, err:%d\n", - __func__, index, count, - QDMA_NUM_RING_SIZES, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - qdma_write_csr_values(dev_hndl, EQDMA_CPM5_GLBL_RNG_SZ_1_ADDR, - index, count, - glbl_rng_sz); - - return QDMA_SUCCESS; -} - -/*****************************************************************************/ -/** - * eqdma_cpm5_read_global_ring_sizes() - function to get the global rng_sz - * array - * - * @dev_hndl: device handle - * @index: Index from where the values needs to read - * @count: number of entries to be read - * @glbl_rng_sz: pointer to array to hold the values read - * - * (index + count) shall not be more than 16 - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -static int eqdma_cpm5_read_global_ring_sizes(void *dev_hndl, uint8_t index, - uint8_t count, uint32_t *glbl_rng_sz) -{ - if (!dev_hndl || !glbl_rng_sz || !count) { - qdma_log_error("%s: dev_hndl=%p glbl_rng_sz=%p, err:%d\n", - __func__, dev_hndl, glbl_rng_sz, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - if ((index + count) > QDMA_NUM_RING_SIZES) { - qdma_log_error("%s: index=%u count=%u > %d, err:%d\n", - __func__, index, count, - QDMA_NUM_C2H_BUFFER_SIZES, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - qdma_read_csr_values(dev_hndl, EQDMA_CPM5_GLBL_RNG_SZ_1_ADDR, - index, count, - glbl_rng_sz); - - return QDMA_SUCCESS; -} - -/*****************************************************************************/ -/** - * eqdma_cpm5_write_global_timer_count() - function to set the timer values - * - * @dev_hndl: device handle - * @glbl_tmr_cnt: pointer to the array having the values to write - * @index: Index from where the values needs to written - * @count: number of entries to be written - * - * (index + count) shall not be more than 16 - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -static int eqdma_cpm5_write_global_timer_count(void *dev_hndl, uint8_t - index, uint8_t count, const uint32_t *glbl_tmr_cnt) -{ - struct qdma_dev_attributes dev_cap; - - if (!dev_hndl || !glbl_tmr_cnt || !count) { - qdma_log_error("%s: dev_hndl=%p glbl_tmr_cnt=%p, err:%d\n", - __func__, dev_hndl, glbl_tmr_cnt, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - if ((index + count) > QDMA_NUM_C2H_TIMERS) { - qdma_log_error("%s: index=%u count=%u > %d, err:%d\n", - __func__, index, count, - QDMA_NUM_C2H_TIMERS, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - eqdma_cpm5_get_device_attributes(dev_hndl, &dev_cap); - - if (dev_cap.st_en || dev_cap.mm_cmpt_en) - qdma_write_csr_values(dev_hndl, - EQDMA_CPM5_C2H_TIMER_CNT_ADDR, - index, count, glbl_tmr_cnt); - else { - qdma_log_error("%s: ST or MM cmpt not supported, err:%d\n", - __func__, - -QDMA_ERR_HWACC_FEATURE_NOT_SUPPORTED); - return -QDMA_ERR_HWACC_FEATURE_NOT_SUPPORTED; - } - - return QDMA_SUCCESS; -} - -/*****************************************************************************/ -/** - * eqdma_cpm5_read_global_timer_count() - function to get the timer values - * - * @dev_hndl: device handle - * @index: Index from where the values needs to read - * @count: number of entries to be read - * @glbl_tmr_cnt: pointer to array to hold the values read - * - * (index + count) shall not be more than 16 - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -static int eqdma_cpm5_read_global_timer_count(void *dev_hndl, - uint8_t index, uint8_t count, uint32_t *glbl_tmr_cnt) -{ - struct qdma_dev_attributes dev_cap; - - if (!dev_hndl || !glbl_tmr_cnt || !count) { - qdma_log_error("%s: dev_hndl=%p glbl_tmr_cnt=%p, err:%d\n", - __func__, dev_hndl, glbl_tmr_cnt, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - if ((index + count) > QDMA_NUM_C2H_TIMERS) { - qdma_log_error("%s: index=%u count=%u > %d, err:%d\n", - __func__, index, count, - QDMA_NUM_C2H_TIMERS, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - eqdma_cpm5_get_device_attributes(dev_hndl, &dev_cap); - - if (dev_cap.st_en || dev_cap.mm_cmpt_en) - qdma_read_csr_values(dev_hndl, - EQDMA_CPM5_C2H_TIMER_CNT_ADDR, index, - count, glbl_tmr_cnt); - else { - qdma_log_error("%s: ST or MM cmpt not supported, err:%d\n", - __func__, - -QDMA_ERR_HWACC_FEATURE_NOT_SUPPORTED); - return -QDMA_ERR_HWACC_FEATURE_NOT_SUPPORTED; - } - - return QDMA_SUCCESS; -} - -/*****************************************************************************/ -/** - * eqdma_cpm5_write_global_counter_threshold() - function to set the - * counter threshold values - * - * @dev_hndl: device handle - * @index: Index from where the values needs to written - * @count: number of entries to be written - * @glbl_cnt_th: pointer to the array having the values to write - * - * (index + count) shall not be more than 16 - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -static int eqdma_cpm5_write_global_counter_threshold(void *dev_hndl, - uint8_t index, uint8_t count, const uint32_t *glbl_cnt_th) -{ - struct qdma_dev_attributes dev_cap; - - if (!dev_hndl || !glbl_cnt_th || !count) { - qdma_log_error("%s: dev_hndl=%p glbl_cnt_th=%p, err:%d\n", - __func__, dev_hndl, glbl_cnt_th, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - if ((index + count) > QDMA_NUM_C2H_COUNTERS) { - qdma_log_error("%s: index=%u count=%u > %d, err:%d\n", - __func__, index, count, - QDMA_NUM_C2H_BUFFER_SIZES, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - eqdma_cpm5_get_device_attributes(dev_hndl, &dev_cap); - - if (dev_cap.st_en || dev_cap.mm_cmpt_en) - qdma_write_csr_values(dev_hndl, EQDMA_CPM5_C2H_CNT_TH_ADDR, - index, - count, glbl_cnt_th); - else { - qdma_log_error("%s: ST or MM cmpt not supported, err:%d\n", - __func__, - -QDMA_ERR_HWACC_FEATURE_NOT_SUPPORTED); - return -QDMA_ERR_HWACC_FEATURE_NOT_SUPPORTED; - } - - return QDMA_SUCCESS; -} - -/*****************************************************************************/ -/** - * eqdma_cpm5_read_global_counter_threshold() - function to get the counter - * threshold - * values - * - * @dev_hndl: device handle - * @index: Index from where the values needs to read - * @count: number of entries to be read - * @glbl_cnt_th: pointer to array to hold the values read - * - * (index + count) shall not be more than 16 - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -static int eqdma_cpm5_read_global_counter_threshold(void *dev_hndl, uint8_t - index, - uint8_t count, uint32_t *glbl_cnt_th) -{ - struct qdma_dev_attributes dev_cap; - - if (!dev_hndl || !glbl_cnt_th || !count) { - qdma_log_error("%s: dev_hndl=%p glbl_cnt_th=%p, err:%d\n", - __func__, dev_hndl, glbl_cnt_th, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - if ((index + count) > QDMA_NUM_C2H_COUNTERS) { - qdma_log_error("%s: index=%u count=%u > %d, err:%d\n", - __func__, index, count, - QDMA_NUM_C2H_COUNTERS, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - eqdma_cpm5_get_device_attributes(dev_hndl, &dev_cap); - - if (dev_cap.st_en || dev_cap.mm_cmpt_en) - qdma_read_csr_values(dev_hndl, EQDMA_CPM5_C2H_CNT_TH_ADDR, - index, count, glbl_cnt_th); - else { - qdma_log_error("%s: ST or MM cmpt not supported, err:%d\n", - __func__, -QDMA_ERR_HWACC_FEATURE_NOT_SUPPORTED); - return -QDMA_ERR_HWACC_FEATURE_NOT_SUPPORTED; - } - - return QDMA_SUCCESS; -} - -/*****************************************************************************/ -/** - * eqdma_cpm5_write_global_buffer_sizes() - function to set the buffer - * sizes - * - * @dev_hndl: device handle - * @index: Index from where the values needs to written - * @count: number of entries to be written - * @glbl_buf_sz: pointer to the array having the values to write - * - * (index + count) shall not be more than 16 - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -static int eqdma_cpm5_write_global_buffer_sizes(void *dev_hndl, uint8_t - index, - uint8_t count, const uint32_t *glbl_buf_sz) -{ - struct qdma_dev_attributes dev_cap; - - if (!dev_hndl || !glbl_buf_sz || !count) { - qdma_log_error("%s: dev_hndl=%p glbl_buf_sz=%p, err:%d\n", - __func__, dev_hndl, glbl_buf_sz, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - if ((index + count) > QDMA_NUM_C2H_BUFFER_SIZES) { - qdma_log_error("%s: index=%u count=%u > %d, err:%d\n", - __func__, index, count, - QDMA_NUM_C2H_BUFFER_SIZES, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - eqdma_cpm5_get_device_attributes(dev_hndl, &dev_cap); - - if (dev_cap.st_en) - qdma_write_csr_values(dev_hndl, EQDMA_CPM5_C2H_BUF_SZ_ADDR, - index, - count, glbl_buf_sz); - else { - qdma_log_error("%s: ST not supported, err:%d\n", - __func__, - -QDMA_ERR_HWACC_FEATURE_NOT_SUPPORTED); - return -QDMA_ERR_HWACC_FEATURE_NOT_SUPPORTED; - } - - return QDMA_SUCCESS; -} - -/*****************************************************************************/ -/** - * eqdma_cpm5_read_global_buffer_sizes() - function to get the buffer sizes - * - * @dev_hndl: device handle - * @index: Index from where the values needs to read - * @count: number of entries to be read - * @glbl_buf_sz: pointer to array to hold the values read - * - * (index + count) shall not be more than 16 - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -static int eqdma_cpm5_read_global_buffer_sizes(void *dev_hndl, uint8_t - index, uint8_t count, uint32_t *glbl_buf_sz) -{ - struct qdma_dev_attributes dev_cap; - - if (!dev_hndl || !glbl_buf_sz || !count) { - qdma_log_error("%s: dev_hndl=%p glbl_buf_sz=%p, err:%d\n", - __func__, dev_hndl, glbl_buf_sz, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - if ((index + count) > QDMA_NUM_C2H_BUFFER_SIZES) { - qdma_log_error("%s: index=%u count=%u > %d, err:%d\n", - __func__, index, count, - QDMA_NUM_C2H_BUFFER_SIZES, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - eqdma_cpm5_get_device_attributes(dev_hndl, &dev_cap); - - if (dev_cap.st_en) - qdma_read_csr_values(dev_hndl, EQDMA_CPM5_C2H_BUF_SZ_ADDR, - index, - count, glbl_buf_sz); - else { - qdma_log_error("%s: ST is not supported, err:%d\n", - __func__, - -QDMA_ERR_HWACC_FEATURE_NOT_SUPPORTED); - return -QDMA_ERR_HWACC_FEATURE_NOT_SUPPORTED; - } - - return QDMA_SUCCESS; -} - -/*****************************************************************************/ -/** - * eqdma_cpm5_global_csr_conf() - function to configure global csr - * - * @dev_hndl: device handle - * @index: Index from where the values needs to read - * @count: number of entries to be read - * @csr_val: uint32_t pointer to csr value - * @csr_type: Type of the CSR (qdma_global_csr_type enum) to configure - * @access_type HW access type (qdma_hw_access_type enum) value - * QDMA_HW_ACCESS_CLEAR - Not supported - * QDMA_HW_ACCESS_INVALIDATE - Not supported - * - * (index + count) shall not be more than 16 - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -int eqdma_cpm5_global_csr_conf(void *dev_hndl, uint8_t index, - uint8_t count, - uint32_t *csr_val, - enum qdma_global_csr_type csr_type, - enum qdma_hw_access_type access_type) -{ - int rv = QDMA_SUCCESS; - - switch (csr_type) { - case QDMA_CSR_RING_SZ: - switch (access_type) { - case QDMA_HW_ACCESS_READ: - rv = eqdma_cpm5_read_global_ring_sizes( - dev_hndl, - index, - count, - csr_val); - break; - case QDMA_HW_ACCESS_WRITE: - rv = eqdma_cpm5_write_global_ring_sizes( - dev_hndl, - index, - count, - csr_val); - break; - default: - qdma_log_error("%s: access_type(%d) invalid, err:%d\n", - __func__, - access_type, - -QDMA_ERR_INV_PARAM); - rv = -QDMA_ERR_INV_PARAM; - break; - } - break; - case QDMA_CSR_TIMER_CNT: - switch (access_type) { - case QDMA_HW_ACCESS_READ: - rv = eqdma_cpm5_read_global_timer_count( - dev_hndl, - index, - count, - csr_val); - break; - case QDMA_HW_ACCESS_WRITE: - rv = eqdma_cpm5_write_global_timer_count( - dev_hndl, - index, - count, - csr_val); - break; - default: - qdma_log_error("%s: access_type(%d) invalid, err:%d\n", - __func__, - access_type, - -QDMA_ERR_INV_PARAM); - rv = -QDMA_ERR_INV_PARAM; - break; - } - break; - case QDMA_CSR_CNT_TH: - switch (access_type) { - case QDMA_HW_ACCESS_READ: - rv = - eqdma_cpm5_read_global_counter_threshold( - dev_hndl, - index, - count, - csr_val); - break; - case QDMA_HW_ACCESS_WRITE: - rv = - eqdma_cpm5_write_global_counter_threshold( - dev_hndl, - index, - count, - csr_val); - break; - default: - qdma_log_error("%s: access_type(%d) invalid, err:%d\n", - __func__, - access_type, - -QDMA_ERR_INV_PARAM); - rv = -QDMA_ERR_INV_PARAM; - break; - } - break; - case QDMA_CSR_BUF_SZ: - switch (access_type) { - case QDMA_HW_ACCESS_READ: - rv = - eqdma_cpm5_read_global_buffer_sizes(dev_hndl, - index, - count, - csr_val); - break; - case QDMA_HW_ACCESS_WRITE: - rv = - eqdma_cpm5_write_global_buffer_sizes(dev_hndl, - index, - count, - csr_val); - break; - default: - qdma_log_error("%s: access_type(%d) invalid, err:%d\n", - __func__, - access_type, - -QDMA_ERR_INV_PARAM); - rv = -QDMA_ERR_INV_PARAM; - break; - } - break; - default: - qdma_log_error("%s: csr_type(%d) invalid, err:%d\n", - __func__, - csr_type, - -QDMA_ERR_INV_PARAM); - rv = -QDMA_ERR_INV_PARAM; - break; - } - - return rv; -} - -/*****************************************************************************/ -/** - * eqdma_cpm5_global_writeback_interval_write() - function to set - * the writeback interval - * - * @dev_hndl device handle - * @wb_int: Writeback Interval - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -static int eqdma_cpm5_global_writeback_interval_write(void *dev_hndl, - enum qdma_wrb_interval wb_int) -{ - uint32_t reg_val; - struct qdma_dev_attributes dev_cap; - - if (!dev_hndl) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", __func__, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - if (wb_int >= QDMA_NUM_WRB_INTERVALS) { - qdma_log_error("%s: wb_int=%d is invalid, err:%d\n", - __func__, wb_int, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - eqdma_cpm5_get_device_attributes(dev_hndl, &dev_cap); - - if (dev_cap.st_en || dev_cap.mm_cmpt_en) { - reg_val = qdma_reg_read(dev_hndl, - EQDMA_CPM5_GLBL_DSC_CFG_ADDR); - reg_val |= FIELD_SET(GLBL_DSC_CFG_WB_ACC_INT_MASK, wb_int); - qdma_reg_write(dev_hndl, EQDMA_CPM5_GLBL_DSC_CFG_ADDR, - reg_val); - } else { - qdma_log_error("%s: ST or MM cmpt not supported, err:%d\n", - __func__, -QDMA_ERR_HWACC_FEATURE_NOT_SUPPORTED); - return -QDMA_ERR_HWACC_FEATURE_NOT_SUPPORTED; - } - - return QDMA_SUCCESS; -} - -/*****************************************************************************/ -/** - * eqdma_cpm5_global_writeback_interval_read() - function to get the - * writeback - * interval - * - * @dev_hndl: device handle - * @wb_int: pointer to the data to hold Writeback Interval - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -static int eqdma_cpm5_global_writeback_interval_read(void *dev_hndl, - enum qdma_wrb_interval *wb_int) -{ - uint32_t reg_val; - struct qdma_dev_attributes dev_cap; - - if (!dev_hndl) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", __func__, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - if (!wb_int) { - qdma_log_error("%s: wb_int is NULL, err:%d\n", __func__, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - eqdma_cpm5_get_device_attributes(dev_hndl, &dev_cap); - - if (dev_cap.st_en || dev_cap.mm_cmpt_en) { - reg_val = qdma_reg_read(dev_hndl, - EQDMA_CPM5_GLBL_DSC_CFG_ADDR); - *wb_int = (enum qdma_wrb_interval)FIELD_GET( - GLBL_DSC_CFG_WB_ACC_INT_MASK, reg_val); - } else { - qdma_log_error("%s: ST or MM cmpt not supported, err:%d\n", - __func__, -QDMA_ERR_HWACC_FEATURE_NOT_SUPPORTED); - return -QDMA_ERR_HWACC_FEATURE_NOT_SUPPORTED; - } - - return QDMA_SUCCESS; -} - -/*****************************************************************************/ -/** - * eqdma_cpm5_global_writeback_interval_conf() - function to configure - * the writeback interval - * - * @dev_hndl: device handle - * @wb_int: pointer to the data to hold Writeback Interval - * @access_type HW access type (qdma_hw_access_type enum) value - * QDMA_HW_ACCESS_CLEAR - Not supported - * QDMA_HW_ACCESS_INVALIDATE - Not supported - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -int eqdma_cpm5_global_writeback_interval_conf(void *dev_hndl, - enum qdma_wrb_interval *wb_int, - enum qdma_hw_access_type access_type) -{ - int rv = QDMA_SUCCESS; - - switch (access_type) { - case QDMA_HW_ACCESS_READ: - rv = eqdma_cpm5_global_writeback_interval_read(dev_hndl, - wb_int); - break; - case QDMA_HW_ACCESS_WRITE: - rv = eqdma_cpm5_global_writeback_interval_write(dev_hndl, - *wb_int); - break; - case QDMA_HW_ACCESS_CLEAR: - case QDMA_HW_ACCESS_INVALIDATE: - default: - qdma_log_error("%s: access_type(%d) invalid, err:%d\n", - __func__, - access_type, - -QDMA_ERR_INV_PARAM); - rv = -QDMA_ERR_INV_PARAM; - break; - } - - return rv; -} - - -/*****************************************************************************/ -/** - * eqdma_cpm5_mm_channel_conf() - Function to enable/disable the MM channel - * - * @dev_hndl: device handle - * @channel: MM channel number - * @is_c2h: Queue direction. Set 1 for C2H and 0 for H2C - * @enable: Enable or disable MM channel - * - * Presently, we have only 1 MM channel - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -int eqdma_cpm5_mm_channel_conf(void *dev_hndl, uint8_t channel, - uint8_t is_c2h, uint8_t enable) -{ - uint32_t reg_addr = (is_c2h) ? EQDMA_CPM5_C2H_MM_CTL_ADDR : - EQDMA_CPM5_H2C_MM_CTL_ADDR; - struct qdma_dev_attributes dev_cap; - - if (!dev_hndl) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - eqdma_cpm5_get_device_attributes(dev_hndl, &dev_cap); - - if (dev_cap.mm_en) - qdma_reg_write(dev_hndl, - reg_addr + (channel * QDMA_MM_CONTROL_STEP), - enable); - - - return QDMA_SUCCESS; -} - -int eqdma_cpm5_dump_reg_info(void *dev_hndl, uint32_t reg_addr, - uint32_t num_regs, char *buf, uint32_t buflen) -{ - uint32_t total_num_regs = eqdma_cpm5_config_num_regs_get(); - struct xreg_info *config_regs = eqdma_cpm5_config_regs_get(); - struct qdma_dev_attributes dev_cap; - const char *bitfield_name; - uint32_t i = 0, num_regs_idx = 0, k = 0, j = 0, - bitfield = 0, lsb = 0, msb = 31; - int rv = 0; - uint32_t reg_val; - uint32_t data_len = 0; - - if (!dev_hndl) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - eqdma_cpm5_get_device_attributes(dev_hndl, &dev_cap); - - for (i = 0; i < total_num_regs; i++) { - if (reg_addr == config_regs[i].addr) { - j = i; - break; - } - } - - if (i == total_num_regs) { - qdma_log_error("%s: Register not found err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - if (buf) - QDMA_SNPRINTF_S(buf, buflen, - DEBGFS_LINE_SZ, - "Register not found 0x%x\n", reg_addr); - - return -QDMA_ERR_INV_PARAM; - } - - num_regs_idx = (j + num_regs < total_num_regs) ? - (j + num_regs) : total_num_regs; - - for (; j < num_regs_idx ; j++) { - reg_val = qdma_reg_read(dev_hndl, - config_regs[j].addr); - - if (buf) { - rv = QDMA_SNPRINTF_S(buf, buflen, - DEBGFS_LINE_SZ, - "\n%-40s 0x%-7x %-#10x %-10d\n", - config_regs[j].name, - config_regs[j].addr, - reg_val, reg_val); - if ((rv < 0) || (rv > DEBGFS_LINE_SZ)) { - qdma_log_error( - "%s: Insufficient buffer, err:%d\n", - __func__, -QDMA_ERR_NO_MEM); - return -QDMA_ERR_NO_MEM; - } - buf += rv; - data_len += rv; - buflen -= rv; - } else - qdma_log_info("%-40s 0x%-7x %-#10x %-10d\n", - config_regs[j].name, - config_regs[j].addr, - reg_val, reg_val); - - - for (k = 0; - k < config_regs[j].num_bitfields; k++) { - /* If Debug Mode not enabled and the current register - * is debug register, skip reading it. - */ - if (dev_cap.debug_mode == 0 && - config_regs[j].is_debug_reg == 1) - continue; - - bitfield = - config_regs[j].bitfields[k].field_mask; - bitfield_name = - config_regs[i].bitfields[k].field_name; - lsb = 0; - msb = 31; - - while (!(BIT(lsb) & bitfield)) - lsb++; - - while (!(BIT(msb) & bitfield)) - msb--; - - if (msb != lsb) { - if (buf) { - rv = QDMA_SNPRINTF_S(buf, buflen, - DEBGFS_LINE_SZ, - "%-40s [%2u,%2u] %#-10x\n", - bitfield_name, - msb, lsb, - (reg_val & bitfield) >> - lsb); - if ((rv < 0) || (rv > DEBGFS_LINE_SZ)) { - qdma_log_error( - "%s: Insufficient buffer, err:%d\n", - __func__, - -QDMA_ERR_NO_MEM); - return -QDMA_ERR_NO_MEM; - } - buf += rv; - data_len += rv; - buflen -= rv; - } else - qdma_log_info( - "%-40s [%2u,%2u] %#-10x\n", - bitfield_name, - msb, lsb, - (reg_val & bitfield) >> lsb); - - - } else { - if (buf) { - rv = QDMA_SNPRINTF_S(buf, buflen, - DEBGFS_LINE_SZ, - "%-40s [%5u] %#-10x\n", - bitfield_name, - lsb, - (reg_val & bitfield) >> - lsb); - if ((rv < 0) || (rv > DEBGFS_LINE_SZ)) { - qdma_log_error( - "%s: Insufficient buffer, err:%d\n", - __func__, - -QDMA_ERR_NO_MEM); - return -QDMA_ERR_NO_MEM; - } - buf += rv; - data_len += rv; - buflen -= rv; - } else - qdma_log_info( - "%-40s [%5u] %#-10x\n", - bitfield_name, - lsb, - (reg_val & bitfield) >> lsb); - - } - } - } - - return data_len; -} - diff --git a/QDMA/DPDK/drivers/net/qdma/qdma_access/eqdma_cpm5_access/eqdma_cpm5_access.h b/QDMA/DPDK/drivers/net/qdma/qdma_access/eqdma_cpm5_access/eqdma_cpm5_access.h deleted file mode 100755 index 8c14e0403..000000000 --- a/QDMA/DPDK/drivers/net/qdma/qdma_access/eqdma_cpm5_access/eqdma_cpm5_access.h +++ /dev/null @@ -1,360 +0,0 @@ -/* - * Copyright (c) 2019-2022, Xilinx, Inc. All rights reserved. - * Copyright (c) 2022, Advanced Micro Devices, Inc. All rights reserved. - * - * BSD LICENSE - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * * Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#ifndef __EQDMA_CPM5_SOFT_ACCESS_H_ -#define __EQDMA_CPM5_SOFT_ACCESS_H_ - -#ifdef __cplusplus -extern "C" { -#endif - -#include "qdma_platform.h" - -/** - * enum eqdma_cpm5_error_idx - qdma errors - */ -enum eqdma_cpm5_error_idx { - /* Descriptor errors */ - EQDMA_CPM5_DSC_ERR_POISON, - EQDMA_CPM5_DSC_ERR_UR_CA, - EQDMA_CPM5_DSC_ERR_BCNT, - EQDMA_CPM5_DSC_ERR_PARAM, - EQDMA_CPM5_DSC_ERR_ADDR, - EQDMA_CPM5_DSC_ERR_TAG, - EQDMA_CPM5_DSC_ERR_FLR, - EQDMA_CPM5_DSC_ERR_TIMEOUT, - EQDMA_CPM5_DSC_ERR_DAT_POISON, - EQDMA_CPM5_DSC_ERR_FLR_CANCEL, - EQDMA_CPM5_DSC_ERR_DMA, - EQDMA_CPM5_DSC_ERR_DSC, - EQDMA_CPM5_DSC_ERR_RQ_CANCEL, - EQDMA_CPM5_DSC_ERR_DBE, - EQDMA_CPM5_DSC_ERR_SBE, - EQDMA_CPM5_DSC_ERR_PORT_ID, - EQDMA_CPM5_DSC_ERR_ALL, - - /* TRQ Errors */ - EQDMA_CPM5_TRQ_ERR_CSR_UNMAPPED, - EQDMA_CPM5_TRQ_ERR_VF_ACCESS, - EQDMA_CPM5_TRQ_ERR_TCP_CSR_TIMEOUT, - EQDMA_CPM5_TRQ_ERR_QSPC_UNMAPPED, - EQDMA_CPM5_TRQ_ERR_QID_RANGE, - EQDMA_CPM5_TRQ_ERR_TCP_QSPC_TIMEOUT, - EQDMA_CPM5_TRQ_ERR_ALL, - - /* ST C2H Errors */ - EQDMA_CPM5_ST_C2H_ERR_MTY_MISMATCH, - EQDMA_CPM5_ST_C2H_ERR_LEN_MISMATCH, - EQDMA_CPM5_ST_C2H_ERR_SH_CMPT_DSC, - EQDMA_CPM5_ST_C2H_ERR_QID_MISMATCH, - EQDMA_CPM5_ST_C2H_ERR_DESC_RSP_ERR, - EQDMA_CPM5_ST_C2H_ERR_ENG_WPL_DATA_PAR_ERR, - EQDMA_CPM5_ST_C2H_ERR_MSI_INT_FAIL, - EQDMA_CPM5_ST_C2H_ERR_ERR_DESC_CNT, - EQDMA_CPM5_ST_C2H_ERR_PORTID_CTXT_MISMATCH, - EQDMA_CPM5_ST_C2H_ERR_CMPT_INV_Q_ERR, - EQDMA_CPM5_ST_C2H_ERR_CMPT_QFULL_ERR, - EQDMA_CPM5_ST_C2H_ERR_CMPT_CIDX_ERR, - EQDMA_CPM5_ST_C2H_ERR_CMPT_PRTY_ERR, - EQDMA_CPM5_ST_C2H_ERR_AVL_RING_DSC, - EQDMA_CPM5_ST_C2H_ERR_HDR_ECC_UNC, - EQDMA_CPM5_ST_C2H_ERR_HDR_ECC_COR, - EQDMA_CPM5_ST_C2H_ERR_WRB_PORT_ID_ERR, - EQDMA_CPM5_ST_C2H_ERR_ALL, - - /* Fatal Errors */ - EQDMA_CPM5_ST_FATAL_ERR_MTY_MISMATCH, - EQDMA_CPM5_ST_FATAL_ERR_LEN_MISMATCH, - EQDMA_CPM5_ST_FATAL_ERR_QID_MISMATCH, - EQDMA_CPM5_ST_FATAL_ERR_TIMER_FIFO_RAM_RDBE, - EQDMA_CPM5_ST_FATAL_ERR_PFCH_II_RAM_RDBE, - EQDMA_CPM5_ST_FATAL_ERR_CMPT_CTXT_RAM_RDBE, - EQDMA_CPM5_ST_FATAL_ERR_PFCH_CTXT_RAM_RDBE, - EQDMA_CPM5_ST_FATAL_ERR_DESC_REQ_FIFO_RAM_RDBE, - EQDMA_CPM5_ST_FATAL_ERR_INT_CTXT_RAM_RDBE, - EQDMA_CPM5_ST_FATAL_ERR_CMPT_COAL_DATA_RAM_RDBE, - EQDMA_CPM5_ST_FATAL_ERR_CMPT_FIFO_RAM_RDBE, - EQDMA_CPM5_ST_FATAL_ERR_QID_FIFO_RAM_RDBE, - EQDMA_CPM5_ST_FATAL_ERR_PAYLOAD_FIFO_RAM_RDBE, - EQDMA_CPM5_ST_FATAL_ERR_WPL_DATA_PAR, - EQDMA_CPM5_ST_FATAL_ERR_AVL_RING_FIFO_RAM_RDBE, - EQDMA_CPM5_ST_FATAL_ERR_HDR_ECC_UNC, - EQDMA_CPM5_ST_FATAL_ERR_ALL, - - /* H2C Errors */ - EQDMA_CPM5_ST_H2C_ERR_ZERO_LEN_DESC, - EQDMA_CPM5_ST_H2C_ERR_SDI_MRKR_REQ_MOP, - EQDMA_CPM5_ST_H2C_ERR_NO_DMA_DSC, - EQDMA_CPM5_ST_H2C_ERR_SBE, - EQDMA_CPM5_ST_H2C_ERR_DBE, - EQDMA_CPM5_ST_H2C_ERR_PAR, - EQDMA_CPM5_ST_H2C_ERR_ALL, - - /* Single bit errors */ - EQDMA_CPM5_SBE_1_ERR_RC_RRQ_EVEN_RAM, - EQDMA_CPM5_SBE_1_ERR_TAG_ODD_RAM, - EQDMA_CPM5_SBE_1_ERR_TAG_EVEN_RAM, - EQDMA_CPM5_SBE_1_ERR_PFCH_CTXT_CAM_RAM_0, - EQDMA_CPM5_SBE_1_ERR_PFCH_CTXT_CAM_RAM_1, - EQDMA_CPM5_SBE_1_ERR_ALL, - - /* Single bit errors */ - EQDMA_CPM5_SBE_ERR_MI_H2C0_DAT, - EQDMA_CPM5_SBE_ERR_MI_H2C1_DAT, - EQDMA_CPM5_SBE_ERR_MI_H2C2_DAT, - EQDMA_CPM5_SBE_ERR_MI_H2C3_DAT, - EQDMA_CPM5_SBE_ERR_MI_C2H0_DAT, - EQDMA_CPM5_SBE_ERR_MI_C2H1_DAT, - EQDMA_CPM5_SBE_ERR_MI_C2H2_DAT, - EQDMA_CPM5_SBE_ERR_MI_C2H3_DAT, - EQDMA_CPM5_SBE_ERR_H2C_RD_BRG_DAT, - EQDMA_CPM5_SBE_ERR_H2C_WR_BRG_DAT, - EQDMA_CPM5_SBE_ERR_C2H_RD_BRG_DAT, - EQDMA_CPM5_SBE_ERR_C2H_WR_BRG_DAT, - EQDMA_CPM5_SBE_ERR_FUNC_MAP, - EQDMA_CPM5_SBE_ERR_DSC_HW_CTXT, - EQDMA_CPM5_SBE_ERR_DSC_CRD_RCV, - EQDMA_CPM5_SBE_ERR_DSC_SW_CTXT, - EQDMA_CPM5_SBE_ERR_DSC_CPLI, - EQDMA_CPM5_SBE_ERR_DSC_CPLD, - EQDMA_CPM5_SBE_ERR_MI_TL_SLV_FIFO_RAM, - EQDMA_CPM5_SBE_ERR_TIMER_FIFO_RAM, - EQDMA_CPM5_SBE_ERR_QID_FIFO_RAM, - EQDMA_CPM5_SBE_ERR_WRB_COAL_DATA_RAM, - EQDMA_CPM5_SBE_ERR_INT_CTXT_RAM, - EQDMA_CPM5_SBE_ERR_DESC_REQ_FIFO_RAM, - EQDMA_CPM5_SBE_ERR_PFCH_CTXT_RAM, - EQDMA_CPM5_SBE_ERR_WRB_CTXT_RAM, - EQDMA_CPM5_SBE_ERR_PFCH_LL_RAM, - EQDMA_CPM5_SBE_ERR_PEND_FIFO_RAM, - EQDMA_CPM5_SBE_ERR_RC_RRQ_ODD_RAM, - EQDMA_CPM5_SBE_ERR_ALL, - - /* Double bit Errors */ - EQDMA_CPM5_DBE_1_ERR_RC_RRQ_EVEN_RAM, - EQDMA_CPM5_DBE_1_ERR_TAG_ODD_RAM, - EQDMA_CPM5_DBE_1_ERR_TAG_EVEN_RAM, - EQDMA_CPM5_DBE_1_ERR_PFCH_CTXT_CAM_RAM_0, - EQDMA_CPM5_DBE_1_ERR_PFCH_CTXT_CAM_RAM_1, - EQDMA_CPM5_DBE_1_ERR_ALL, - - /* Double bit Errors */ - EQDMA_CPM5_DBE_ERR_MI_H2C0_DAT, - EQDMA_CPM5_DBE_ERR_MI_H2C1_DAT, - EQDMA_CPM5_DBE_ERR_MI_H2C2_DAT, - EQDMA_CPM5_DBE_ERR_MI_H2C3_DAT, - EQDMA_CPM5_DBE_ERR_MI_C2H0_DAT, - EQDMA_CPM5_DBE_ERR_MI_C2H1_DAT, - EQDMA_CPM5_DBE_ERR_MI_C2H2_DAT, - EQDMA_CPM5_DBE_ERR_MI_C2H3_DAT, - EQDMA_CPM5_DBE_ERR_H2C_RD_BRG_DAT, - EQDMA_CPM5_DBE_ERR_H2C_WR_BRG_DAT, - EQDMA_CPM5_DBE_ERR_C2H_RD_BRG_DAT, - EQDMA_CPM5_DBE_ERR_C2H_WR_BRG_DAT, - EQDMA_CPM5_DBE_ERR_FUNC_MAP, - EQDMA_CPM5_DBE_ERR_DSC_HW_CTXT, - EQDMA_CPM5_DBE_ERR_DSC_CRD_RCV, - EQDMA_CPM5_DBE_ERR_DSC_SW_CTXT, - EQDMA_CPM5_DBE_ERR_DSC_CPLI, - EQDMA_CPM5_DBE_ERR_DSC_CPLD, - EQDMA_CPM5_DBE_ERR_MI_TL_SLV_FIFO_RAM, - EQDMA_CPM5_DBE_ERR_TIMER_FIFO_RAM, - EQDMA_CPM5_DBE_ERR_QID_FIFO_RAM, - EQDMA_CPM5_DBE_ERR_WRB_COAL_DATA_RAM, - EQDMA_CPM5_DBE_ERR_INT_CTXT_RAM, - EQDMA_CPM5_DBE_ERR_DESC_REQ_FIFO_RAM, - EQDMA_CPM5_DBE_ERR_PFCH_CTXT_RAM, - EQDMA_CPM5_DBE_ERR_WRB_CTXT_RAM, - EQDMA_CPM5_DBE_ERR_PFCH_LL_RAM, - EQDMA_CPM5_DBE_ERR_PEND_FIFO_RAM, - EQDMA_CPM5_DBE_ERR_RC_RRQ_ODD_RAM, - EQDMA_CPM5_DBE_ERR_ALL, - - /* MM C2H Errors */ - EQDMA_CPM5_MM_C2H_WR_SLR_ERR, - EQDMA_CPM5_MM_C2H_RD_SLR_ERR, - EQDMA_CPM5_MM_C2H_WR_FLR_ERR, - EQDMA_CPM5_MM_C2H_UR_ERR, - EQDMA_CPM5_MM_C2H_WR_UC_RAM_ERR, - EQDMA_CPM5_MM_C2H_ERR_ALL, - - /* MM H2C Engine0 Errors */ - EQDMA_CPM5_MM_H2C0_RD_HDR_POISON_ERR, - EQDMA_CPM5_MM_H2C0_RD_UR_CA_ERR, - EQDMA_CPM5_MM_H2C0_RD_HDR_BYTE_ERR, - EQDMA_CPM5_MM_H2C0_RD_HDR_PARAM_ERR, - EQDMA_CPM5_MM_H2C0_RD_HDR_ADR_ERR, - EQDMA_CPM5_MM_H2C0_RD_FLR_ERR, - EQDMA_CPM5_MM_H2C0_RD_DAT_POISON_ERR, - EQDMA_CPM5_MM_H2C0_RD_RQ_DIS_ERR, - EQDMA_CPM5_MM_H2C0_WR_DEC_ERR, - EQDMA_CPM5_MM_H2C0_WR_SLV_ERR, - EQDMA_CPM5_MM_H2C0_ERR_ALL, - - EQDMA_CPM5_ERRS_ALL -}; - -struct eqdma_cpm5_hw_err_info { - enum eqdma_cpm5_error_idx idx; - const char *err_name; - uint32_t mask_reg_addr; - uint32_t stat_reg_addr; - uint32_t leaf_err_mask; - uint32_t global_err_mask; - void (*eqdma_cpm5_hw_err_process)(void *dev_hndl); -}; - -#ifdef EQDMA_CPM5_VF_GT_256Q_SUPPORTED -#define EQDMA_CPM5_OFFSET_VF_VERSION 0x21014 -#define EQDMA_CPM5_OFFSET_MBOX_BASE_VF 0x21000 -#else -#define EQDMA_CPM5_OFFSET_VF_VERSION 0x5014 -#define EQDMA_CPM5_OFFSET_MBOX_BASE_VF 0x5000 -#endif - -#define EQDMA_CPM5_OFFSET_MBOX_BASE_PF 0x42400 -#define EQDMA_CPM5_OFFSET_VF_USER_BAR 0x5018 - -#define EQDMA_CPM5_COMPL_CTXT_BADDR_HIGH_H_MASK GENMASK_ULL(63, 38) -#define EQDMA_CPM5_COMPL_CTXT_BADDR_HIGH_L_MASK GENMASK_ULL(37, 6) -#define EQDMA_CPM5_COMPL_CTXT_BADDR_LOW_MASK GENMASK_ULL(5, 2) - -int eqdma_cpm5_init_ctxt_memory(void *dev_hndl); - -#ifdef TANDEM_BOOT_SUPPORTED -int eqdma_cpm5_init_st_ctxt(void *dev_hndl); -#endif - -int eqdma_cpm5_get_version(void *dev_hndl, uint8_t is_vf, - struct qdma_hw_version_info *version_info); - -int eqdma_cpm5_sw_ctx_conf(void *dev_hndl, uint8_t c2h, uint16_t hw_qid, - struct qdma_descq_sw_ctxt *ctxt, - enum qdma_hw_access_type access_type); - -int eqdma_cpm5_hw_ctx_conf(void *dev_hndl, uint8_t c2h, uint16_t hw_qid, - struct qdma_descq_hw_ctxt *ctxt, - enum qdma_hw_access_type access_type); - -int eqdma_cpm5_credit_ctx_conf(void *dev_hndl, uint8_t c2h, - uint16_t hw_qid, struct qdma_descq_credit_ctxt *ctxt, - enum qdma_hw_access_type access_type); - -int eqdma_cpm5_pfetch_ctx_conf(void *dev_hndl, uint16_t hw_qid, - struct qdma_descq_prefetch_ctxt *ctxt, - enum qdma_hw_access_type access_type); - -int eqdma_cpm5_cmpt_ctx_conf(void *dev_hndl, uint16_t hw_qid, - struct qdma_descq_cmpt_ctxt *ctxt, - enum qdma_hw_access_type access_type); - -int eqdma_cpm5_fmap_conf(void *dev_hndl, uint16_t func_id, - struct qdma_fmap_cfg *config, - enum qdma_hw_access_type access_type); - -int eqdma_cpm5_indirect_intr_ctx_conf(void *dev_hndl, uint16_t ring_index, - struct qdma_indirect_intr_ctxt *ctxt, - enum qdma_hw_access_type access_type); - -int eqdma_cpm5_dump_config_regs(void *dev_hndl, uint8_t is_vf, - char *buf, uint32_t buflen); - -int eqdma_cpm5_dump_intr_context(void *dev_hndl, - struct qdma_indirect_intr_ctxt *intr_ctx, - int ring_index, - char *buf, uint32_t buflen); - -int eqdma_cpm5_dump_queue_context(void *dev_hndl, - uint8_t st, - enum qdma_dev_q_type q_type, - struct qdma_descq_context *ctxt_data, - char *buf, uint32_t buflen); - -uint32_t eqdma_cpm5_reg_dump_buf_len(void); - -int eqdma_cpm5_context_buf_len(uint8_t st, - enum qdma_dev_q_type q_type, uint32_t *buflen); - -int eqdma_cpm5_hw_error_process(void *dev_hndl); -const char *eqdma_cpm5_hw_get_error_name(uint32_t err_idx); -int eqdma_cpm5_hw_error_enable(void *dev_hndl, uint32_t err_idx); - -int eqdma_cpm5_read_dump_queue_context(void *dev_hndl, - uint16_t func_id, - uint16_t qid_hw, - uint8_t st, - enum qdma_dev_q_type q_type, - char *buf, uint32_t buflen); - -int eqdma_cpm5_get_device_attributes(void *dev_hndl, - struct qdma_dev_attributes *dev_info); - -int eqdma_cpm5_get_user_bar(void *dev_hndl, uint8_t is_vf, - uint16_t func_id, uint8_t *user_bar); - -int eqdma_cpm5_dump_config_reg_list(void *dev_hndl, - uint32_t total_regs, - struct qdma_reg_data *reg_list, - char *buf, uint32_t buflen); - -int eqdma_cpm5_read_reg_list(void *dev_hndl, uint8_t is_vf, - uint16_t reg_rd_group, - uint16_t *total_regs, - struct qdma_reg_data *reg_list); - -int eqdma_cpm5_set_default_global_csr(void *dev_hndl); - -int eqdma_cpm5_global_csr_conf(void *dev_hndl, uint8_t index, uint8_t count, - uint32_t *csr_val, - enum qdma_global_csr_type csr_type, - enum qdma_hw_access_type access_type); - -int eqdma_cpm5_global_writeback_interval_conf(void *dev_hndl, - enum qdma_wrb_interval *wb_int, - enum qdma_hw_access_type access_type); - -int eqdma_cpm5_mm_channel_conf(void *dev_hndl, uint8_t channel, - uint8_t is_c2h, uint8_t enable); - -int eqdma_cpm5_dump_reg_info(void *dev_hndl, uint32_t reg_addr, - uint32_t num_regs, char *buf, uint32_t buflen); - -uint32_t eqdma_cpm5_get_config_num_regs(void); - -struct xreg_info *eqdma_cpm5_get_config_regs(void); - -#ifdef __cplusplus -} -#endif - -#endif /* __EQDMA_CPM5_SOFT_ACCESS_H_ */ diff --git a/QDMA/DPDK/drivers/net/qdma/qdma_access/eqdma_cpm5_access/eqdma_cpm5_reg.h b/QDMA/DPDK/drivers/net/qdma/qdma_access/eqdma_cpm5_access/eqdma_cpm5_reg.h deleted file mode 100755 index 1099ede25..000000000 --- a/QDMA/DPDK/drivers/net/qdma/qdma_access/eqdma_cpm5_access/eqdma_cpm5_reg.h +++ /dev/null @@ -1,1300 +0,0 @@ -/* - * Copyright (c) 2019-2022 Xilinx, Inc. All rights reserved. - * Copyright (c) 2022, Advanced Micro Devices, Inc. All rights reserved. - * - * BSD LICENSE - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * * Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#ifndef __EQDMA_CPM5_REG_H -#define __EQDMA_CPM5_REG_H - - -#ifdef __cplusplus -extern "C" { -#endif - -#include "qdma_platform.h" - -#ifdef CHAR_BIT -#undef CHAR_BIT -#endif -#define CHAR_BIT 8 - -#ifdef BIT -#undef BIT -#endif -#define BIT(n) (1u << (n)) - -#ifdef BITS_PER_BYTE -#undef BITS_PER_BYTE -#endif -#define BITS_PER_BYTE CHAR_BIT - -#ifdef BITS_PER_LONG -#undef BITS_PER_LONG -#endif -#define BITS_PER_LONG (sizeof(uint32_t) * BITS_PER_BYTE) - -#ifdef BITS_PER_LONG_LONG -#undef BITS_PER_LONG_LONG -#endif -#define BITS_PER_LONG_LONG (sizeof(uint64_t) * BITS_PER_BYTE) - -#ifdef GENMASK -#undef GENMASK -#endif -#define GENMASK(h, l) \ - ((0xFFFFFFFF << (l)) & (0xFFFFFFFF >> (BITS_PER_LONG - 1 - (h)))) - -#ifdef GENMASK_ULL -#undef GENMASK_ULL -#endif -#define GENMASK_ULL(h, l) \ - ((0xFFFFFFFFFFFFFFFF << (l)) & \ - (0xFFFFFFFFFFFFFFFF >> (BITS_PER_LONG_LONG - 1 - (h)))) - -#define DEBGFS_LINE_SZ (81) - -#ifdef ARRAY_SIZE -#undef ARRAY_SIZE -#endif -#define ARRAY_SIZE(arr) (sizeof(arr) / \ - sizeof(arr[0])) - - -uint32_t eqdma_cpm5_config_num_regs_get(void); -struct xreg_info *eqdma_cpm5_config_regs_get(void); -#define EQDMA_CPM5_CFG_BLK_IDENTIFIER_ADDR 0x00 -#define CFG_BLK_IDENTIFIER_MASK GENMASK(31, 20) -#define CFG_BLK_IDENTIFIER_1_MASK GENMASK(19, 16) -#define CFG_BLK_IDENTIFIER_RSVD_1_MASK GENMASK(15, 8) -#define CFG_BLK_IDENTIFIER_VERSION_MASK GENMASK(7, 0) -#define EQDMA_CPM5_CFG_BLK_PCIE_MAX_PLD_SIZE_ADDR 0x08 -#define CFG_BLK_PCIE_MAX_PLD_SIZE_RSVD_1_MASK GENMASK(31, 7) -#define CFG_BLK_PCIE_MAX_PLD_SIZE_PROG_MASK GENMASK(6, 4) -#define CFG_BLK_PCIE_MAX_PLD_SIZE_RSVD_2_MASK BIT(3) -#define CFG_BLK_PCIE_MAX_PLD_SIZE_ISSUED_MASK GENMASK(2, 0) -#define EQDMA_CPM5_CFG_BLK_PCIE_MAX_READ_REQ_SIZE_ADDR 0x0C -#define CFG_BLK_PCIE_MAX_READ_REQ_SIZE_RSVD_1_MASK GENMASK(31, 7) -#define CFG_BLK_PCIE_MAX_READ_REQ_SIZE_PROG_MASK GENMASK(6, 4) -#define CFG_BLK_PCIE_MAX_READ_REQ_SIZE_RSVD_2_MASK BIT(3) -#define CFG_BLK_PCIE_MAX_READ_REQ_SIZE_ISSUED_MASK GENMASK(2, 0) -#define EQDMA_CPM5_CFG_BLK_SYSTEM_ID_ADDR 0x10 -#define CFG_BLK_SYSTEM_ID_RSVD_1_MASK GENMASK(31, 17) -#define CFG_BLK_SYSTEM_ID_INST_TYPE_MASK BIT(16) -#define CFG_BLK_SYSTEM_ID_MASK GENMASK(15, 0) -#define EQDMA_CPM5_CFG_BLK_MSIX_ENABLE_ADDR 0x014 -#define CFG_BLK_MSIX_ENABLE_MASK GENMASK(31, 0) -#define EQDMA_CPM5_CFG_PCIE_DATA_WIDTH_ADDR 0x18 -#define CFG_PCIE_DATA_WIDTH_RSVD_1_MASK GENMASK(31, 3) -#define CFG_PCIE_DATA_WIDTH_DATAPATH_MASK GENMASK(2, 0) -#define EQDMA_CPM5_CFG_PCIE_CTL_ADDR 0x1C -#define CFG_PCIE_CTL_RSVD_1_MASK GENMASK(31, 18) -#define CFG_PCIE_CTL_MGMT_AXIL_CTRL_MASK GENMASK(17, 16) -#define CFG_PCIE_CTL_RSVD_2_MASK GENMASK(15, 2) -#define CFG_PCIE_CTL_RRQ_DISABLE_MASK BIT(1) -#define CFG_PCIE_CTL_RELAXED_ORDERING_MASK BIT(0) -#define EQDMA_CPM5_CFG_BLK_MSI_ENABLE_ADDR 0x20 -#define CFG_BLK_MSI_ENABLE_MASK GENMASK(31, 0) -#define EQDMA_CPM5_CFG_AXI_USER_MAX_PLD_SIZE_ADDR 0x40 -#define CFG_AXI_USER_MAX_PLD_SIZE_RSVD_1_MASK GENMASK(31, 7) -#define CFG_AXI_USER_MAX_PLD_SIZE_ISSUED_MASK GENMASK(6, 4) -#define CFG_AXI_USER_MAX_PLD_SIZE_RSVD_2_MASK BIT(3) -#define CFG_AXI_USER_MAX_PLD_SIZE_PROG_MASK GENMASK(2, 0) -#define EQDMA_CPM5_CFG_AXI_USER_MAX_READ_REQ_SIZE_ADDR 0x44 -#define CFG_AXI_USER_MAX_READ_REQ_SIZE_RSVD_1_MASK GENMASK(31, 7) -#define CFG_AXI_USER_MAX_READ_REQ_SIZE_USISSUED_MASK GENMASK(6, 4) -#define CFG_AXI_USER_MAX_READ_REQ_SIZE_RSVD_2_MASK BIT(3) -#define CFG_AXI_USER_MAX_READ_REQ_SIZE_USPROG_MASK GENMASK(2, 0) -#define EQDMA_CPM5_CFG_BLK_MISC_CTL_ADDR 0x4C -#define CFG_BLK_MISC_CTL_RSVD_1_MASK GENMASK(31, 24) -#define CFG_BLK_MISC_CTL_10B_TAG_EN_MASK BIT(23) -#define CFG_BLK_MISC_CTL_RSVD_2_MASK BIT(22) -#define CFG_BLK_MISC_CTL_AXI_WBK_MASK BIT(21) -#define CFG_BLK_MISC_CTL_AXI_DSC_MASK BIT(20) -#define CFG_BLK_MISC_CTL_NUM_TAG_MASK GENMASK(19, 8) -#define CFG_BLK_MISC_CTL_RSVD_3_MASK GENMASK(7, 5) -#define CFG_BLK_MISC_CTL_RQ_METERING_MULTIPLIER_MASK GENMASK(4, 0) -#define EQDMA_CPM5_CFG_PL_CRED_CTL_ADDR 0x68 -#define CFG_PL_CRED_CTL_RSVD_1_MASK GENMASK(31, 5) -#define CFG_PL_CRED_CTL_SLAVE_CRD_RLS_MASK BIT(4) -#define CFG_PL_CRED_CTL_RSVD_2_MASK GENMASK(3, 1) -#define CFG_PL_CRED_CTL_MASTER_CRD_RST_MASK BIT(0) -#define EQDMA_CPM5_CFG_BLK_SCRATCH_ADDR 0x80 -#define CFG_BLK_SCRATCH_MASK GENMASK(31, 0) -#define EQDMA_CPM5_CFG_GIC_ADDR 0xA0 -#define CFG_GIC_RSVD_1_MASK GENMASK(31, 1) -#define CFG_GIC_GIC_IRQ_MASK BIT(0) -#define EQDMA_CPM5_RAM_SBE_MSK_1_A_ADDR 0xE0 -#define RAM_SBE_MSK_1_A_MASK GENMASK(31, 0) -#define EQDMA_CPM5_RAM_SBE_STS_1_A_ADDR 0xE4 -#define RAM_SBE_STS_1_A_RSVD_MASK GENMASK(31, 5) -#define RAM_SBE_STS_1_A_PFCH_CTXT_CAM_RAM_1_MASK BIT(4) -#define RAM_SBE_STS_1_A_PFCH_CTXT_CAM_RAM_0_MASK BIT(3) -#define RAM_SBE_STS_1_A_TAG_EVEN_RAM_MASK BIT(2) -#define RAM_SBE_STS_1_A_TAG_ODD_RAM_MASK BIT(1) -#define RAM_SBE_STS_1_A_RC_RRQ_EVEN_RAM_MASK BIT(0) -#define EQDMA_CPM5_RAM_DBE_MSK_1_A_ADDR 0xE8 -#define RAM_DBE_MSK_1_A_MASK GENMASK(31, 0) -#define EQDMA_CPM5_RAM_DBE_STS_1_A_ADDR 0xEC -#define RAM_DBE_STS_1_A_RSVD_MASK GENMASK(31, 5) -#define RAM_DBE_STS_1_A_PFCH_CTXT_CAM_RAM_1_MASK BIT(4) -#define RAM_DBE_STS_1_A_PFCH_CTXT_CAM_RAM_0_MASK BIT(3) -#define RAM_DBE_STS_1_A_TAG_EVEN_RAM_MASK BIT(2) -#define RAM_DBE_STS_1_A_TAG_ODD_RAM_MASK BIT(1) -#define RAM_DBE_STS_1_A_RC_RRQ_EVEN_RAM_MASK BIT(0) -#define EQDMA_CPM5_RAM_SBE_MSK_A_ADDR 0xF0 -#define RAM_SBE_MSK_A_MASK GENMASK(31, 0) -#define EQDMA_CPM5_RAM_SBE_STS_A_ADDR 0xF4 -#define RAM_SBE_STS_A_RC_RRQ_ODD_RAM_MASK BIT(31) -#define RAM_SBE_STS_A_PEND_FIFO_RAM_MASK BIT(30) -#define RAM_SBE_STS_A_PFCH_LL_RAM_MASK BIT(29) -#define RAM_SBE_STS_A_WRB_CTXT_RAM_MASK BIT(28) -#define RAM_SBE_STS_A_PFCH_CTXT_RAM_MASK BIT(27) -#define RAM_SBE_STS_A_DESC_REQ_FIFO_RAM_MASK BIT(26) -#define RAM_SBE_STS_A_INT_CTXT_RAM_MASK BIT(25) -#define RAM_SBE_STS_A_WRB_COAL_DATA_RAM_MASK BIT(24) -#define RAM_SBE_STS_A_QID_FIFO_RAM_MASK BIT(23) -#define RAM_SBE_STS_A_TIMER_FIFO_RAM_MASK GENMASK(22, 19) -#define RAM_SBE_STS_A_MI_TL_SLV_FIFO_RAM_MASK BIT(18) -#define RAM_SBE_STS_A_DSC_CPLD_MASK BIT(17) -#define RAM_SBE_STS_A_DSC_CPLI_MASK BIT(16) -#define RAM_SBE_STS_A_DSC_SW_CTXT_MASK BIT(15) -#define RAM_SBE_STS_A_DSC_CRD_RCV_MASK BIT(14) -#define RAM_SBE_STS_A_DSC_HW_CTXT_MASK BIT(13) -#define RAM_SBE_STS_A_FUNC_MAP_MASK BIT(12) -#define RAM_SBE_STS_A_C2H_WR_BRG_DAT_MASK BIT(11) -#define RAM_SBE_STS_A_C2H_RD_BRG_DAT_MASK BIT(10) -#define RAM_SBE_STS_A_H2C_WR_BRG_DAT_MASK BIT(9) -#define RAM_SBE_STS_A_H2C_RD_BRG_DAT_MASK BIT(8) -#define RAM_SBE_STS_A_MI_C2H3_DAT_MASK BIT(7) -#define RAM_SBE_STS_A_MI_C2H2_DAT_MASK BIT(6) -#define RAM_SBE_STS_A_MI_C2H1_DAT_MASK BIT(5) -#define RAM_SBE_STS_A_MI_C2H0_DAT_MASK BIT(4) -#define RAM_SBE_STS_A_MI_H2C3_DAT_MASK BIT(3) -#define RAM_SBE_STS_A_MI_H2C2_DAT_MASK BIT(2) -#define RAM_SBE_STS_A_MI_H2C1_DAT_MASK BIT(1) -#define RAM_SBE_STS_A_MI_H2C0_DAT_MASK BIT(0) -#define EQDMA_CPM5_RAM_DBE_MSK_A_ADDR 0xF8 -#define RAM_DBE_MSK_A_MASK GENMASK(31, 0) -#define EQDMA_CPM5_RAM_DBE_STS_A_ADDR 0xFC -#define RAM_DBE_STS_A_RC_RRQ_ODD_RAM_MASK BIT(31) -#define RAM_DBE_STS_A_PEND_FIFO_RAM_MASK BIT(30) -#define RAM_DBE_STS_A_PFCH_LL_RAM_MASK BIT(29) -#define RAM_DBE_STS_A_WRB_CTXT_RAM_MASK BIT(28) -#define RAM_DBE_STS_A_PFCH_CTXT_RAM_MASK BIT(27) -#define RAM_DBE_STS_A_DESC_REQ_FIFO_RAM_MASK BIT(26) -#define RAM_DBE_STS_A_INT_CTXT_RAM_MASK BIT(25) -#define RAM_DBE_STS_A_WRB_COAL_DATA_RAM_MASK BIT(24) -#define RAM_DBE_STS_A_QID_FIFO_RAM_MASK BIT(23) -#define RAM_DBE_STS_A_TIMER_FIFO_RAM_MASK GENMASK(22, 19) -#define RAM_DBE_STS_A_MI_TL_SLV_FIFO_RAM_MASK BIT(18) -#define RAM_DBE_STS_A_DSC_CPLD_MASK BIT(17) -#define RAM_DBE_STS_A_DSC_CPLI_MASK BIT(16) -#define RAM_DBE_STS_A_DSC_SW_CTXT_MASK BIT(15) -#define RAM_DBE_STS_A_DSC_CRD_RCV_MASK BIT(14) -#define RAM_DBE_STS_A_DSC_HW_CTXT_MASK BIT(13) -#define RAM_DBE_STS_A_FUNC_MAP_MASK BIT(12) -#define RAM_DBE_STS_A_C2H_WR_BRG_DAT_MASK BIT(11) -#define RAM_DBE_STS_A_C2H_RD_BRG_DAT_MASK BIT(10) -#define RAM_DBE_STS_A_H2C_WR_BRG_DAT_MASK BIT(9) -#define RAM_DBE_STS_A_H2C_RD_BRG_DAT_MASK BIT(8) -#define RAM_DBE_STS_A_MI_C2H3_DAT_MASK BIT(7) -#define RAM_DBE_STS_A_MI_C2H2_DAT_MASK BIT(6) -#define RAM_DBE_STS_A_MI_C2H1_DAT_MASK BIT(5) -#define RAM_DBE_STS_A_MI_C2H0_DAT_MASK BIT(4) -#define RAM_DBE_STS_A_MI_H2C3_DAT_MASK BIT(3) -#define RAM_DBE_STS_A_MI_H2C2_DAT_MASK BIT(2) -#define RAM_DBE_STS_A_MI_H2C1_DAT_MASK BIT(1) -#define RAM_DBE_STS_A_MI_H2C0_DAT_MASK BIT(0) -#define EQDMA_CPM5_GLBL2_IDENTIFIER_ADDR 0x100 -#define GLBL2_IDENTIFIER_MASK GENMASK(31, 8) -#define GLBL2_IDENTIFIER_VERSION_MASK GENMASK(7, 0) -#define EQDMA_CPM5_GLBL2_CHANNEL_INST_ADDR 0x114 -#define GLBL2_CHANNEL_INST_RSVD_1_MASK GENMASK(31, 18) -#define GLBL2_CHANNEL_INST_C2H_ST_MASK BIT(17) -#define GLBL2_CHANNEL_INST_H2C_ST_MASK BIT(16) -#define GLBL2_CHANNEL_INST_RSVD_2_MASK GENMASK(15, 12) -#define GLBL2_CHANNEL_INST_C2H_ENG_MASK GENMASK(11, 8) -#define GLBL2_CHANNEL_INST_RSVD_3_MASK GENMASK(7, 4) -#define GLBL2_CHANNEL_INST_H2C_ENG_MASK GENMASK(3, 0) -#define EQDMA_CPM5_GLBL2_CHANNEL_MDMA_ADDR 0x118 -#define GLBL2_CHANNEL_MDMA_RSVD_1_MASK GENMASK(31, 18) -#define GLBL2_CHANNEL_MDMA_C2H_ST_MASK BIT(17) -#define GLBL2_CHANNEL_MDMA_H2C_ST_MASK BIT(16) -#define GLBL2_CHANNEL_MDMA_RSVD_2_MASK GENMASK(15, 12) -#define GLBL2_CHANNEL_MDMA_C2H_ENG_MASK GENMASK(11, 8) -#define GLBL2_CHANNEL_MDMA_RSVD_3_MASK GENMASK(7, 4) -#define GLBL2_CHANNEL_MDMA_H2C_ENG_MASK GENMASK(3, 0) -#define EQDMA_CPM5_GLBL2_CHANNEL_STRM_ADDR 0x11C -#define GLBL2_CHANNEL_STRM_RSVD_1_MASK GENMASK(31, 18) -#define GLBL2_CHANNEL_STRM_C2H_ST_MASK BIT(17) -#define GLBL2_CHANNEL_STRM_H2C_ST_MASK BIT(16) -#define GLBL2_CHANNEL_STRM_RSVD_2_MASK GENMASK(15, 12) -#define GLBL2_CHANNEL_STRM_C2H_ENG_MASK GENMASK(11, 8) -#define GLBL2_CHANNEL_STRM_RSVD_3_MASK GENMASK(7, 4) -#define GLBL2_CHANNEL_STRM_H2C_ENG_MASK GENMASK(3, 0) -#define EQDMA_CPM5_GLBL2_CHANNEL_CAP_ADDR 0x120 -#define GLBL2_CHANNEL_CAP_RSVD_1_MASK GENMASK(31, 12) -#define GLBL2_CHANNEL_CAP_MULTIQ_MAX_MASK GENMASK(11, 0) -#define EQDMA_CPM5_GLBL2_CHANNEL_PASID_CAP_ADDR 0x128 -#define GLBL2_CHANNEL_PASID_CAP_RSVD_1_MASK GENMASK(31, 2) -#define GLBL2_CHANNEL_PASID_CAP_BRIDGEEN_MASK BIT(1) -#define GLBL2_CHANNEL_PASID_CAP_DMAEN_MASK BIT(0) -#define EQDMA_CPM5_GLBL2_SYSTEM_ID_ADDR 0x130 -#define GLBL2_SYSTEM_ID_RSVD_1_MASK GENMASK(31, 16) -#define GLBL2_SYSTEM_ID_MASK GENMASK(15, 0) -#define EQDMA_CPM5_GLBL2_MISC_CAP_ADDR 0x134 -#define GLBL2_MISC_CAP_MASK GENMASK(31, 0) -#define EQDMA_CPM5_GLBL2_DBG_PCIE_RQ0_ADDR 0x1B8 -#define GLBL2_PCIE_RQ0_NPH_AVL_MASK GENMASK(31, 20) -#define GLBL2_PCIE_RQ0_RCB_AVL_MASK GENMASK(19, 9) -#define GLBL2_PCIE_RQ0_SLV_RD_CREDS_MASK GENMASK(8, 2) -#define GLBL2_PCIE_RQ0_TAG_EP_MASK GENMASK(1, 0) -#define EQDMA_CPM5_GLBL2_DBG_PCIE_RQ1_ADDR 0x1BC -#define GLBL2_PCIE_RQ1_RSVD_1_MASK GENMASK(31, 21) -#define GLBL2_PCIE_RQ1_TAG_FL_MASK GENMASK(20, 19) -#define GLBL2_PCIE_RQ1_WTLP_HEADER_FIFO_FL_MASK BIT(18) -#define GLBL2_PCIE_RQ1_WTLP_HEADER_FIFO_EP_MASK BIT(17) -#define GLBL2_PCIE_RQ1_RQ_FIFO_EP_MASK BIT(16) -#define GLBL2_PCIE_RQ1_RQ_FIFO_FL_MASK BIT(15) -#define GLBL2_PCIE_RQ1_TLPSM_MASK GENMASK(14, 12) -#define GLBL2_PCIE_RQ1_TLPSM512_MASK GENMASK(11, 9) -#define GLBL2_PCIE_RQ1_RREQ_RCB_OK_MASK BIT(8) -#define GLBL2_PCIE_RQ1_RREQ0_SLV_MASK BIT(7) -#define GLBL2_PCIE_RQ1_RREQ0_VLD_MASK BIT(6) -#define GLBL2_PCIE_RQ1_RREQ0_RDY_MASK BIT(5) -#define GLBL2_PCIE_RQ1_RREQ1_SLV_MASK BIT(4) -#define GLBL2_PCIE_RQ1_RREQ1_VLD_MASK BIT(3) -#define GLBL2_PCIE_RQ1_RREQ1_RDY_MASK BIT(2) -#define GLBL2_PCIE_RQ1_WTLP_REQ_MASK BIT(1) -#define GLBL2_PCIE_RQ1_WTLP_STRADDLE_MASK BIT(0) -#define EQDMA_CPM5_GLBL2_DBG_AXIMM_WR0_ADDR 0x1C0 -#define GLBL2_AXIMM_WR0_RSVD_1_MASK GENMASK(31, 27) -#define GLBL2_AXIMM_WR0_WR_REQ_MASK BIT(26) -#define GLBL2_AXIMM_WR0_WR_CHN_MASK GENMASK(25, 23) -#define GLBL2_AXIMM_WR0_WTLP_DATA_FIFO_EP_MASK BIT(22) -#define GLBL2_AXIMM_WR0_WPL_FIFO_EP_MASK BIT(21) -#define GLBL2_AXIMM_WR0_BRSP_CLAIM_CHN_MASK GENMASK(20, 18) -#define GLBL2_AXIMM_WR0_WRREQ_CNT_MASK GENMASK(17, 12) -#define GLBL2_AXIMM_WR0_BID_MASK GENMASK(11, 9) -#define GLBL2_AXIMM_WR0_BVALID_MASK BIT(8) -#define GLBL2_AXIMM_WR0_BREADY_MASK BIT(7) -#define GLBL2_AXIMM_WR0_WVALID_MASK BIT(6) -#define GLBL2_AXIMM_WR0_WREADY_MASK BIT(5) -#define GLBL2_AXIMM_WR0_AWID_MASK GENMASK(4, 2) -#define GLBL2_AXIMM_WR0_AWVALID_MASK BIT(1) -#define GLBL2_AXIMM_WR0_AWREADY_MASK BIT(0) -#define EQDMA_CPM5_GLBL2_DBG_AXIMM_WR1_ADDR 0x1C4 -#define GLBL2_AXIMM_WR1_RSVD_1_MASK GENMASK(31, 30) -#define GLBL2_AXIMM_WR1_BRSP_CNT4_MASK GENMASK(29, 24) -#define GLBL2_AXIMM_WR1_BRSP_CNT3_MASK GENMASK(23, 18) -#define GLBL2_AXIMM_WR1_BRSP_CNT2_MASK GENMASK(17, 12) -#define GLBL2_AXIMM_WR1_BRSP_CNT1_MASK GENMASK(11, 6) -#define GLBL2_AXIMM_WR1_BRSP_CNT0_MASK GENMASK(5, 0) -#define EQDMA_CPM5_GLBL2_DBG_AXIMM_RD0_ADDR 0x1C8 -#define GLBL2_AXIMM_RD0_RSVD_1_MASK GENMASK(31, 23) -#define GLBL2_AXIMM_RD0_PND_CNT_MASK GENMASK(22, 17) -#define GLBL2_AXIMM_RD0_RD_REQ_MASK BIT(16) -#define GLBL2_AXIMM_RD0_RD_CHNL_MASK GENMASK(15, 13) -#define GLBL2_AXIMM_RD0_RRSP_CLAIM_CHNL_MASK GENMASK(12, 10) -#define GLBL2_AXIMM_RD0_RID_MASK GENMASK(9, 7) -#define GLBL2_AXIMM_RD0_RVALID_MASK BIT(6) -#define GLBL2_AXIMM_RD0_RREADY_MASK BIT(5) -#define GLBL2_AXIMM_RD0_ARID_MASK GENMASK(4, 2) -#define GLBL2_AXIMM_RD0_ARVALID_MASK BIT(1) -#define GLBL2_AXIMM_RD0_ARREADY_MASK BIT(0) -#define EQDMA_CPM5_GLBL2_DBG_AXIMM_RD1_ADDR 0x1CC -#define GLBL2_AXIMM_RD1_RSVD_1_MASK GENMASK(31, 30) -#define GLBL2_AXIMM_RD1_RRSP_CNT4_MASK GENMASK(29, 24) -#define GLBL2_AXIMM_RD1_RRSP_CNT3_MASK GENMASK(23, 18) -#define GLBL2_AXIMM_RD1_RRSP_CNT2_MASK GENMASK(17, 12) -#define GLBL2_AXIMM_RD1_RRSP_CNT1_MASK GENMASK(11, 6) -#define GLBL2_AXIMM_RD1_RRSP_CNT0_MASK GENMASK(5, 0) -#define EQDMA_CPM5_GLBL2_DBG_FAB0_ADDR 0x1D0 -#define GLBL2_FAB0_H2C_INB_CONV_IN_VLD_MASK BIT(31) -#define GLBL2_FAB0_H2C_INB_CONV_IN_RDY_MASK BIT(30) -#define GLBL2_FAB0_H2C_SEG_IN_VLD_MASK BIT(29) -#define GLBL2_FAB0_H2C_SEG_IN_RDY_MASK BIT(28) -#define GLBL2_FAB0_H2C_SEG_OUT_VLD_MASK GENMASK(27, 24) -#define GLBL2_FAB0_H2C_SEG_OUT_RDY_MASK BIT(23) -#define GLBL2_FAB0_H2C_MST_CRDT_STAT_MASK GENMASK(22, 16) -#define GLBL2_FAB0_C2H_SLV_AFIFO_FULL_MASK BIT(15) -#define GLBL2_FAB0_C2H_SLV_AFIFO_EMPTY_MASK BIT(14) -#define GLBL2_FAB0_C2H_DESEG_SEG_VLD_MASK GENMASK(13, 10) -#define GLBL2_FAB0_C2H_DESEG_SEG_RDY_MASK BIT(9) -#define GLBL2_FAB0_C2H_DESEG_OUT_VLD_MASK BIT(8) -#define GLBL2_FAB0_C2H_DESEG_OUT_RDY_MASK BIT(7) -#define GLBL2_FAB0_C2H_INB_DECONV_OUT_VLD_MASK BIT(6) -#define GLBL2_FAB0_C2H_INB_DECONV_OUT_RDY_MASK BIT(5) -#define GLBL2_FAB0_C2H_DSC_CRDT_AFIFO_FULL_MASK BIT(4) -#define GLBL2_FAB0_C2H_DSC_CRDT_AFIFO_EMPTY_MASK BIT(3) -#define GLBL2_FAB0_IRQ_IN_AFIFO_FULL_MASK BIT(2) -#define GLBL2_FAB0_IRQ_IN_AFIFO_EMPTY_MASK BIT(1) -#define GLBL2_FAB0_IMM_CRD_AFIFO_EMPTY_MASK BIT(0) -#define EQDMA_CPM5_GLBL2_DBG_FAB1_ADDR 0x1D4 -#define GLBL2_FAB1_BYP_OUT_CRDT_STAT_MASK GENMASK(31, 25) -#define GLBL2_FAB1_TM_DSC_STS_CRDT_STAT_MASK GENMASK(24, 18) -#define GLBL2_FAB1_C2H_CMN_AFIFO_FULL_MASK BIT(17) -#define GLBL2_FAB1_C2H_CMN_AFIFO_EMPTY_MASK BIT(16) -#define GLBL2_FAB1_RSVD_1_MASK GENMASK(15, 13) -#define GLBL2_FAB1_C2H_BYP_IN_AFIFO_FULL_MASK BIT(12) -#define GLBL2_FAB1_RSVD_2_MASK GENMASK(11, 9) -#define GLBL2_FAB1_C2H_BYP_IN_AFIFO_EMPTY_MASK BIT(8) -#define GLBL2_FAB1_RSVD_3_MASK GENMASK(7, 5) -#define GLBL2_FAB1_H2C_BYP_IN_AFIFO_FULL_MASK BIT(4) -#define GLBL2_FAB1_RSVD_4_MASK GENMASK(3, 1) -#define GLBL2_FAB1_H2C_BYP_IN_AFIFO_EMPTY_MASK BIT(0) -#define EQDMA_CPM5_GLBL2_DBG_MATCH_SEL_ADDR 0x1F4 -#define GLBL2_MATCH_SEL_RSV_MASK GENMASK(31, 18) -#define GLBL2_MATCH_SEL_CSR_SEL_MASK GENMASK(17, 13) -#define GLBL2_MATCH_SEL_CSR_EN_MASK BIT(12) -#define GLBL2_MATCH_SEL_ROTATE1_MASK GENMASK(11, 10) -#define GLBL2_MATCH_SEL_ROTATE0_MASK GENMASK(9, 8) -#define GLBL2_MATCH_SEL_SEL_MASK GENMASK(7, 0) -#define EQDMA_CPM5_GLBL2_DBG_MATCH_MSK_ADDR 0x1F8 -#define GLBL2_MATCH_MSK_MASK GENMASK(31, 0) -#define EQDMA_CPM5_GLBL2_DBG_MATCH_PAT_ADDR 0x1FC -#define GLBL2_MATCH_PAT_PATTERN_MASK GENMASK(31, 0) -#define EQDMA_CPM5_GLBL_RNG_SZ_1_ADDR 0x204 -#define GLBL_RNG_SZ_1_RSVD_1_MASK GENMASK(31, 16) -#define GLBL_RNG_SZ_1_RING_SIZE_MASK GENMASK(15, 0) -#define EQDMA_CPM5_GLBL_RNG_SZ_2_ADDR 0x208 -#define GLBL_RNG_SZ_2_RSVD_1_MASK GENMASK(31, 16) -#define GLBL_RNG_SZ_2_RING_SIZE_MASK GENMASK(15, 0) -#define EQDMA_CPM5_GLBL_RNG_SZ_3_ADDR 0x20C -#define GLBL_RNG_SZ_3_RSVD_1_MASK GENMASK(31, 16) -#define GLBL_RNG_SZ_3_RING_SIZE_MASK GENMASK(15, 0) -#define EQDMA_CPM5_GLBL_RNG_SZ_4_ADDR 0x210 -#define GLBL_RNG_SZ_4_RSVD_1_MASK GENMASK(31, 16) -#define GLBL_RNG_SZ_4_RING_SIZE_MASK GENMASK(15, 0) -#define EQDMA_CPM5_GLBL_RNG_SZ_5_ADDR 0x214 -#define GLBL_RNG_SZ_5_RSVD_1_MASK GENMASK(31, 16) -#define GLBL_RNG_SZ_5_RING_SIZE_MASK GENMASK(15, 0) -#define EQDMA_CPM5_GLBL_RNG_SZ_6_ADDR 0x218 -#define GLBL_RNG_SZ_6_RSVD_1_MASK GENMASK(31, 16) -#define GLBL_RNG_SZ_6_RING_SIZE_MASK GENMASK(15, 0) -#define EQDMA_CPM5_GLBL_RNG_SZ_7_ADDR 0x21C -#define GLBL_RNG_SZ_7_RSVD_1_MASK GENMASK(31, 16) -#define GLBL_RNG_SZ_7_RING_SIZE_MASK GENMASK(15, 0) -#define EQDMA_CPM5_GLBL_RNG_SZ_8_ADDR 0x220 -#define GLBL_RNG_SZ_8_RSVD_1_MASK GENMASK(31, 16) -#define GLBL_RNG_SZ_8_RING_SIZE_MASK GENMASK(15, 0) -#define EQDMA_CPM5_GLBL_RNG_SZ_9_ADDR 0x224 -#define GLBL_RNG_SZ_9_RSVD_1_MASK GENMASK(31, 16) -#define GLBL_RNG_SZ_9_RING_SIZE_MASK GENMASK(15, 0) -#define EQDMA_CPM5_GLBL_RNG_SZ_A_ADDR 0x228 -#define GLBL_RNG_SZ_A_RSVD_1_MASK GENMASK(31, 16) -#define GLBL_RNG_SZ_A_RING_SIZE_MASK GENMASK(15, 0) -#define EQDMA_CPM5_GLBL_RNG_SZ_B_ADDR 0x22C -#define GLBL_RNG_SZ_B_RSVD_1_MASK GENMASK(31, 16) -#define GLBL_RNG_SZ_B_RING_SIZE_MASK GENMASK(15, 0) -#define EQDMA_CPM5_GLBL_RNG_SZ_C_ADDR 0x230 -#define GLBL_RNG_SZ_C_RSVD_1_MASK GENMASK(31, 16) -#define GLBL_RNG_SZ_C_RING_SIZE_MASK GENMASK(15, 0) -#define EQDMA_CPM5_GLBL_RNG_SZ_D_ADDR 0x234 -#define GLBL_RNG_SZ_D_RSVD_1_MASK GENMASK(31, 16) -#define GLBL_RNG_SZ_D_RING_SIZE_MASK GENMASK(15, 0) -#define EQDMA_CPM5_GLBL_RNG_SZ_E_ADDR 0x238 -#define GLBL_RNG_SZ_E_RSVD_1_MASK GENMASK(31, 16) -#define GLBL_RNG_SZ_E_RING_SIZE_MASK GENMASK(15, 0) -#define EQDMA_CPM5_GLBL_RNG_SZ_F_ADDR 0x23C -#define GLBL_RNG_SZ_F_RSVD_1_MASK GENMASK(31, 16) -#define GLBL_RNG_SZ_F_RING_SIZE_MASK GENMASK(15, 0) -#define EQDMA_CPM5_GLBL_RNG_SZ_10_ADDR 0x240 -#define GLBL_RNG_SZ_10_RSVD_1_MASK GENMASK(31, 16) -#define GLBL_RNG_SZ_10_RING_SIZE_MASK GENMASK(15, 0) -#define EQDMA_CPM5_GLBL_ERR_STAT_ADDR 0x248 -#define GLBL_ERR_STAT_RSVD_1_MASK GENMASK(31, 18) -#define GLBL_ERR_STAT_ERR_FAB_MASK BIT(17) -#define GLBL_ERR_STAT_ERR_H2C_ST_MASK BIT(16) -#define GLBL_ERR_STAT_ERR_BDG_MASK BIT(15) -#define GLBL_ERR_STAT_IND_CTXT_CMD_ERR_MASK GENMASK(14, 9) -#define GLBL_ERR_STAT_ERR_C2H_ST_MASK BIT(8) -#define GLBL_ERR_STAT_ERR_C2H_MM_1_MASK BIT(7) -#define GLBL_ERR_STAT_ERR_C2H_MM_0_MASK BIT(6) -#define GLBL_ERR_STAT_ERR_H2C_MM_1_MASK BIT(5) -#define GLBL_ERR_STAT_ERR_H2C_MM_0_MASK BIT(4) -#define GLBL_ERR_STAT_ERR_TRQ_MASK BIT(3) -#define GLBL_ERR_STAT_ERR_DSC_MASK BIT(2) -#define GLBL_ERR_STAT_ERR_RAM_DBE_MASK BIT(1) -#define GLBL_ERR_STAT_ERR_RAM_SBE_MASK BIT(0) -#define EQDMA_CPM5_GLBL_ERR_MASK_ADDR 0x24C -#define GLBL_ERR_MASK GENMASK(31, 0) -#define EQDMA_CPM5_GLBL_DSC_CFG_ADDR 0x250 -#define GLBL_DSC_CFG_RSVD_1_MASK GENMASK(31, 10) -#define GLBL_DSC_CFG_UNC_OVR_COR_MASK BIT(9) -#define GLBL_DSC_CFG_CTXT_FER_DIS_MASK BIT(8) -#define GLBL_DSC_CFG_RSVD_2_MASK GENMASK(7, 6) -#define GLBL_DSC_CFG_MAXFETCH_MASK GENMASK(5, 3) -#define GLBL_DSC_CFG_WB_ACC_INT_MASK GENMASK(2, 0) -#define EQDMA_CPM5_GLBL_DSC_ERR_STS_ADDR 0x254 -#define GLBL_DSC_ERR_STS_RSVD_1_MASK GENMASK(31, 26) -#define GLBL_DSC_ERR_STS_PORT_ID_MASK BIT(25) -#define GLBL_DSC_ERR_STS_SBE_MASK BIT(24) -#define GLBL_DSC_ERR_STS_DBE_MASK BIT(23) -#define GLBL_DSC_ERR_STS_RQ_CANCEL_MASK BIT(22) -#define GLBL_DSC_ERR_STS_DSC_MASK BIT(21) -#define GLBL_DSC_ERR_STS_DMA_MASK BIT(20) -#define GLBL_DSC_ERR_STS_FLR_CANCEL_MASK BIT(19) -#define GLBL_DSC_ERR_STS_RSVD_2_MASK GENMASK(18, 17) -#define GLBL_DSC_ERR_STS_DAT_POISON_MASK BIT(16) -#define GLBL_DSC_ERR_STS_TIMEOUT_MASK BIT(9) -#define GLBL_DSC_ERR_STS_FLR_MASK BIT(8) -#define GLBL_DSC_ERR_STS_TAG_MASK BIT(6) -#define GLBL_DSC_ERR_STS_ADDR_MASK BIT(5) -#define GLBL_DSC_ERR_STS_PARAM_MASK BIT(4) -#define GLBL_DSC_ERR_STS_BCNT_MASK BIT(3) -#define GLBL_DSC_ERR_STS_UR_CA_MASK BIT(2) -#define GLBL_DSC_ERR_STS_POISON_MASK BIT(1) -#define EQDMA_CPM5_GLBL_DSC_ERR_MSK_ADDR 0x258 -#define GLBL_DSC_ERR_MSK_MASK GENMASK(31, 0) -#define EQDMA_CPM5_GLBL_DSC_ERR_LOG0_ADDR 0x25C -#define GLBL_DSC_ERR_LOG0_VALID_MASK BIT(31) -#define GLBL_DSC_ERR_LOG0_SEL_MASK BIT(30) -#define GLBL_DSC_ERR_LOG0_RSVD_1_MASK GENMASK(29, 13) -#define GLBL_DSC_ERR_LOG0_QID_MASK GENMASK(12, 0) -#define EQDMA_CPM5_GLBL_DSC_ERR_LOG1_ADDR 0x260 -#define GLBL_DSC_ERR_LOG1_RSVD_1_MASK GENMASK(31, 28) -#define GLBL_DSC_ERR_LOG1_CIDX_MASK GENMASK(27, 12) -#define GLBL_DSC_ERR_LOG1_RSVD_2_MASK GENMASK(11, 9) -#define GLBL_DSC_ERR_LOG1_SUB_TYPE_MASK GENMASK(8, 5) -#define GLBL_DSC_ERR_LOG1_ERR_TYPE_MASK GENMASK(4, 0) -#define EQDMA_CPM5_GLBL_TRQ_ERR_STS_ADDR 0x264 -#define GLBL_TRQ_ERR_STS_RSVD_1_MASK GENMASK(31, 8) -#define GLBL_TRQ_ERR_STS_TCP_QSPC_TIMEOUT_MASK BIT(7) -#define GLBL_TRQ_ERR_STS_RSVD_2_MASK BIT(6) -#define GLBL_TRQ_ERR_STS_QID_RANGE_MASK BIT(5) -#define GLBL_TRQ_ERR_STS_QSPC_UNMAPPED_MASK BIT(4) -#define GLBL_TRQ_ERR_STS_TCP_CSR_TIMEOUT_MASK BIT(3) -#define GLBL_TRQ_ERR_STS_RSVD_3_MASK BIT(2) -#define GLBL_TRQ_ERR_STS_VF_ACCESS_ERR_MASK BIT(1) -#define GLBL_TRQ_ERR_STS_CSR_UNMAPPED_MASK BIT(0) -#define EQDMA_CPM5_GLBL_TRQ_ERR_MSK_ADDR 0x268 -#define GLBL_TRQ_ERR_MSK_MASK GENMASK(31, 0) -#define EQDMA_CPM5_GLBL_TRQ_ERR_LOG_ADDR 0x26C -#define GLBL_TRQ_ERR_LOG_SRC_MASK BIT(31) -#define GLBL_TRQ_ERR_LOG_TARGET_MASK GENMASK(30, 27) -#define GLBL_TRQ_ERR_LOG_FUNC_MASK GENMASK(26, 17) -#define GLBL_TRQ_ERR_LOG_ADDRESS_MASK GENMASK(16, 0) -#define EQDMA_CPM5_GLBL_DSC_DBG_DAT0_ADDR 0x270 -#define GLBL_DSC_DAT0_RSVD_1_MASK GENMASK(31, 30) -#define GLBL_DSC_DAT0_CTXT_ARB_DIR_MASK BIT(29) -#define GLBL_DSC_DAT0_CTXT_ARB_QID_MASK GENMASK(28, 17) -#define GLBL_DSC_DAT0_CTXT_ARB_REQ_MASK GENMASK(16, 12) -#define GLBL_DSC_DAT0_IRQ_FIFO_FL_MASK BIT(11) -#define GLBL_DSC_DAT0_TMSTALL_MASK BIT(10) -#define GLBL_DSC_DAT0_RRQ_STALL_MASK GENMASK(9, 8) -#define GLBL_DSC_DAT0_RCP_FIFO_SPC_STALL_MASK GENMASK(7, 6) -#define GLBL_DSC_DAT0_RRQ_FIFO_SPC_STALL_MASK GENMASK(5, 4) -#define GLBL_DSC_DAT0_FAB_MRKR_RSP_STALL_MASK GENMASK(3, 2) -#define GLBL_DSC_DAT0_DSC_OUT_STALL_MASK GENMASK(1, 0) -#define EQDMA_CPM5_GLBL_DSC_DBG_DAT1_ADDR 0x274 -#define GLBL_DSC_DAT1_RSVD_1_MASK GENMASK(31, 28) -#define GLBL_DSC_DAT1_EVT_SPC_C2H_MASK GENMASK(27, 22) -#define GLBL_DSC_DAT1_EVT_SP_H2C_MASK GENMASK(21, 16) -#define GLBL_DSC_DAT1_DSC_SPC_C2H_MASK GENMASK(15, 8) -#define GLBL_DSC_DAT1_DSC_SPC_H2C_MASK GENMASK(7, 0) -#define EQDMA_CPM5_GLBL_DSC_DBG_CTL_ADDR 0x278 -#define GLBL_DSC_CTL_RSVD_1_MASK GENMASK(31, 3) -#define GLBL_DSC_CTL_SELECT_MASK GENMASK(2, 0) -#define EQDMA_CPM5_GLBL_DSC_ERR_LOG2_ADDR 0x27c -#define GLBL_DSC_ERR_LOG2_OLD_PIDX_MASK GENMASK(31, 16) -#define GLBL_DSC_ERR_LOG2_NEW_PIDX_MASK GENMASK(15, 0) -#define EQDMA_CPM5_GLBL_GLBL_INTERRUPT_CFG_ADDR 0x2c4 -#define GLBL_GLBL_INTERRUPT_CFG_RSVD_1_MASK GENMASK(31, 2) -#define GLBL_GLBL_INTERRUPT_CFG_LGCY_INTR_PENDING_MASK BIT(1) -#define GLBL_GLBL_INTERRUPT_CFG_EN_LGCY_INTR_MASK BIT(0) -#define EQDMA_CPM5_GLBL_VCH_HOST_PROFILE_ADDR 0x2c8 -#define GLBL_VCH_HOST_PROFILE_RSVD_1_MASK GENMASK(31, 28) -#define GLBL_VCH_HOST_PROFILE_2C_MM_MASK GENMASK(27, 24) -#define GLBL_VCH_HOST_PROFILE_2C_ST_MASK GENMASK(23, 20) -#define GLBL_VCH_HOST_PROFILE_VCH_DSC_MASK GENMASK(19, 16) -#define GLBL_VCH_HOST_PROFILE_VCH_INT_MSG_MASK GENMASK(15, 12) -#define GLBL_VCH_HOST_PROFILE_VCH_INT_AGGR_MASK GENMASK(11, 8) -#define GLBL_VCH_HOST_PROFILE_VCH_CMPT_MASK GENMASK(7, 4) -#define GLBL_VCH_HOST_PROFILE_VCH_C2H_PLD_MASK GENMASK(3, 0) -#define EQDMA_CPM5_GLBL_BRIDGE_HOST_PROFILE_ADDR 0x308 -#define GLBL_BRIDGE_HOST_PROFILE_RSVD_1_MASK GENMASK(31, 4) -#define GLBL_BRIDGE_HOST_PROFILE_BDGID_MASK GENMASK(3, 0) -#define EQDMA_CPM5_AXIMM_IRQ_DEST_ADDR_ADDR 0x30c -#define AXIMM_IRQ_DEST_ADDR_ADDR_MASK GENMASK(31, 0) -#define EQDMA_CPM5_FAB_ERR_LOG_ADDR 0x314 -#define FAB_ERR_LOG_RSVD_1_MASK GENMASK(31, 7) -#define FAB_ERR_LOG_SRC_MASK GENMASK(6, 0) -#define EQDMA_CPM5_IND_CTXT_DATA_ADDR 0x804 -#define IND_CTXT_DATA_DATA_MASK GENMASK(31, 0) -#define EQDMA_CPM5_IND_CTXT_MASK_ADDR 0x824 -#define IND_CTXT_MASK GENMASK(31, 0) -#define EQDMA_CPM5_IND_CTXT_CMD_ADDR 0x844 -#define IND_CTXT_CMD_RSVD_1_MASK GENMASK(31, 20) -#define IND_CTXT_CMD_QID_MASK GENMASK(19, 7) -#define IND_CTXT_CMD_OP_MASK GENMASK(6, 5) -#define IND_CTXT_CMD_SEL_MASK GENMASK(4, 1) -#define IND_CTXT_CMD_BUSY_MASK BIT(0) -#define EQDMA_CPM5_C2H_TIMER_CNT_ADDR 0xA00 -#define C2H_TIMER_CNT_RSVD_1_MASK GENMASK(31, 16) -#define C2H_TIMER_CNT_MASK GENMASK(15, 0) -#define EQDMA_CPM5_C2H_CNT_TH_ADDR 0xA40 -#define C2H_CNT_TH_RSVD_1_MASK GENMASK(31, 16) -#define C2H_CNT_TH_THESHOLD_CNT_MASK GENMASK(15, 0) -#define EQDMA_CPM5_C2H_STAT_S_AXIS_C2H_ACCEPTED_ADDR 0xA88 -#define C2H_STAT_S_AXIS_C2H_ACCEPTED_RSVD_1_MASK GENMASK(31, 18) -#define C2H_STAT_S_AXIS_C2H_ACCEPTED_MASK GENMASK(17, 0) -#define EQDMA_CPM5_C2H_STAT_S_AXIS_WRB_ACCEPTED_ADDR 0xA8C -#define C2H_STAT_S_AXIS_WRB_ACCEPTED_RSVD_1_MASK GENMASK(31, 18) -#define C2H_STAT_S_AXIS_WRB_ACCEPTED_MASK GENMASK(17, 0) -#define EQDMA_CPM5_C2H_STAT_DESC_RSP_PKT_ACCEPTED_ADDR 0xA90 -#define C2H_STAT_DESC_RSP_PKT_ACCEPTED_RSVD_1_MASK GENMASK(31, 18) -#define C2H_STAT_DESC_RSP_PKT_ACCEPTED_D_MASK GENMASK(17, 0) -#define EQDMA_CPM5_C2H_STAT_AXIS_PKG_CMP_ADDR 0xA94 -#define C2H_STAT_AXIS_PKG_CMP_RSVD_1_MASK GENMASK(31, 18) -#define C2H_STAT_AXIS_PKG_CMP_MASK GENMASK(17, 0) -#define EQDMA_CPM5_C2H_STAT_DESC_RSP_ACCEPTED_ADDR 0xA98 -#define C2H_STAT_DESC_RSP_ACCEPTED_RSVD_1_MASK GENMASK(31, 18) -#define C2H_STAT_DESC_RSP_ACCEPTED_D_MASK GENMASK(17, 0) -#define EQDMA_CPM5_C2H_STAT_DESC_RSP_CMP_ADDR 0xA9C -#define C2H_STAT_DESC_RSP_CMP_RSVD_1_MASK GENMASK(31, 18) -#define C2H_STAT_DESC_RSP_CMP_D_MASK GENMASK(17, 0) -#define EQDMA_CPM5_C2H_STAT_WRQ_OUT_ADDR 0xAA0 -#define C2H_STAT_WRQ_OUT_RSVD_1_MASK GENMASK(31, 18) -#define C2H_STAT_WRQ_OUT_MASK GENMASK(17, 0) -#define EQDMA_CPM5_C2H_STAT_WPL_REN_ACCEPTED_ADDR 0xAA4 -#define C2H_STAT_WPL_REN_ACCEPTED_RSVD_1_MASK GENMASK(31, 18) -#define C2H_STAT_WPL_REN_ACCEPTED_MASK GENMASK(17, 0) -#define EQDMA_CPM5_C2H_STAT_TOTAL_WRQ_LEN_ADDR 0xAA8 -#define C2H_STAT_TOTAL_WRQ_LEN_RSVD_1_MASK GENMASK(31, 18) -#define C2H_STAT_TOTAL_WRQ_LEN_MASK GENMASK(17, 0) -#define EQDMA_CPM5_C2H_STAT_TOTAL_WPL_LEN_ADDR 0xAAC -#define C2H_STAT_TOTAL_WPL_LEN_RSVD_1_MASK GENMASK(31, 18) -#define C2H_STAT_TOTAL_WPL_LEN_MASK GENMASK(17, 0) -#define EQDMA_CPM5_C2H_BUF_SZ_ADDR 0xAB0 -#define C2H_BUF_SZ_IZE_MASK GENMASK(31, 0) -#define EQDMA_CPM5_C2H_ERR_STAT_ADDR 0xAF0 -#define C2H_ERR_STAT_RSVD_1_MASK GENMASK(31, 21) -#define C2H_ERR_STAT_WRB_PORT_ID_ERR_MASK BIT(20) -#define C2H_ERR_STAT_HDR_PAR_ERR_MASK BIT(19) -#define C2H_ERR_STAT_HDR_ECC_COR_ERR_MASK BIT(18) -#define C2H_ERR_STAT_HDR_ECC_UNC_ERR_MASK BIT(17) -#define C2H_ERR_STAT_AVL_RING_DSC_ERR_MASK BIT(16) -#define C2H_ERR_STAT_WRB_PRTY_ERR_MASK BIT(15) -#define C2H_ERR_STAT_WRB_CIDX_ERR_MASK BIT(14) -#define C2H_ERR_STAT_WRB_QFULL_ERR_MASK BIT(13) -#define C2H_ERR_STAT_WRB_INV_Q_ERR_MASK BIT(12) -#define C2H_ERR_STAT_RSVD_2_MASK BIT(11) -#define C2H_ERR_STAT_PORT_ID_CTXT_MISMATCH_MASK BIT(10) -#define C2H_ERR_STAT_ERR_DESC_CNT_MASK BIT(9) -#define C2H_ERR_STAT_RSVD_3_MASK BIT(8) -#define C2H_ERR_STAT_MSI_INT_FAIL_MASK BIT(7) -#define C2H_ERR_STAT_ENG_WPL_DATA_PAR_ERR_MASK BIT(6) -#define C2H_ERR_STAT_RSVD_4_MASK BIT(5) -#define C2H_ERR_STAT_DESC_RSP_ERR_MASK BIT(4) -#define C2H_ERR_STAT_QID_MISMATCH_MASK BIT(3) -#define C2H_ERR_STAT_SH_CMPT_DSC_ERR_MASK BIT(2) -#define C2H_ERR_STAT_LEN_MISMATCH_MASK BIT(1) -#define C2H_ERR_STAT_MTY_MISMATCH_MASK BIT(0) -#define EQDMA_CPM5_C2H_ERR_MASK_ADDR 0xAF4 -#define C2H_ERR_EN_MASK GENMASK(31, 0) -#define EQDMA_CPM5_C2H_FATAL_ERR_STAT_ADDR 0xAF8 -#define C2H_FATAL_ERR_STAT_RSVD_1_MASK GENMASK(31, 21) -#define C2H_FATAL_ERR_STAT_HDR_ECC_UNC_ERR_MASK BIT(20) -#define C2H_FATAL_ERR_STAT_AVL_RING_FIFO_RAM_RDBE_MASK BIT(19) -#define C2H_FATAL_ERR_STAT_WPL_DATA_PAR_ERR_MASK BIT(18) -#define C2H_FATAL_ERR_STAT_PLD_FIFO_RAM_RDBE_MASK BIT(17) -#define C2H_FATAL_ERR_STAT_QID_FIFO_RAM_RDBE_MASK BIT(16) -#define C2H_FATAL_ERR_STAT_CMPT_FIFO_RAM_RDBE_MASK BIT(15) -#define C2H_FATAL_ERR_STAT_WRB_COAL_DATA_RAM_RDBE_MASK BIT(14) -#define C2H_FATAL_ERR_STAT_RESERVED2_MASK BIT(13) -#define C2H_FATAL_ERR_STAT_INT_CTXT_RAM_RDBE_MASK BIT(12) -#define C2H_FATAL_ERR_STAT_DESC_REQ_FIFO_RAM_RDBE_MASK BIT(11) -#define C2H_FATAL_ERR_STAT_PFCH_CTXT_RAM_RDBE_MASK BIT(10) -#define C2H_FATAL_ERR_STAT_WRB_CTXT_RAM_RDBE_MASK BIT(9) -#define C2H_FATAL_ERR_STAT_PFCH_LL_RAM_RDBE_MASK BIT(8) -#define C2H_FATAL_ERR_STAT_TIMER_FIFO_RAM_RDBE_MASK GENMASK(7, 4) -#define C2H_FATAL_ERR_STAT_QID_MISMATCH_MASK BIT(3) -#define C2H_FATAL_ERR_STAT_RESERVED1_MASK BIT(2) -#define C2H_FATAL_ERR_STAT_LEN_MISMATCH_MASK BIT(1) -#define C2H_FATAL_ERR_STAT_MTY_MISMATCH_MASK BIT(0) -#define EQDMA_CPM5_C2H_FATAL_ERR_MASK_ADDR 0xAFC -#define C2H_FATAL_ERR_C2HEN_MASK GENMASK(31, 0) -#define EQDMA_CPM5_C2H_FATAL_ERR_ENABLE_ADDR 0xB00 -#define C2H_FATAL_ERR_ENABLE_RSVD_1_MASK GENMASK(31, 2) -#define C2H_FATAL_ERR_ENABLE_WPL_PAR_INV_MASK BIT(1) -#define C2H_FATAL_ERR_ENABLE_WRQ_DIS_MASK BIT(0) -#define EQDMA_CPM5_GLBL_ERR_INT_ADDR 0xB04 -#define GLBL_ERR_INT_RSVD_1_MASK GENMASK(31, 30) -#define GLBL_ERR_INT_HOST_ID_MASK GENMASK(29, 26) -#define GLBL_ERR_INT_DIS_INTR_ON_VF_MASK BIT(25) -#define GLBL_ERR_INT_ARM_MASK BIT(24) -#define GLBL_ERR_INT_EN_COAL_MASK BIT(23) -#define GLBL_ERR_INT_VEC_MASK GENMASK(22, 12) -#define GLBL_ERR_INT_FUNC_MASK GENMASK(11, 0) -#define EQDMA_CPM5_C2H_PFCH_CFG_ADDR 0xB08 -#define C2H_PFCH_CFG_EVTFL_TH_MASK GENMASK(31, 16) -#define C2H_PFCH_CFG_FL_TH_MASK GENMASK(15, 0) -#define EQDMA_CPM5_C2H_PFCH_CFG_1_ADDR 0xA80 -#define C2H_PFCH_CFG_1_EVT_QCNT_TH_MASK GENMASK(31, 16) -#define C2H_PFCH_CFG_1_QCNT_MASK GENMASK(15, 0) -#define EQDMA_CPM5_C2H_PFCH_CFG_2_ADDR 0xA84 -#define C2H_PFCH_CFG_2_FENCE_MASK BIT(31) -#define C2H_PFCH_CFG_2_RSVD_MASK GENMASK(30, 29) -#define C2H_PFCH_CFG_2_VAR_DESC_NO_DROP_MASK BIT(28) -#define C2H_PFCH_CFG_2_LL_SZ_TH_MASK GENMASK(27, 12) -#define C2H_PFCH_CFG_2_VAR_DESC_NUM_MASK GENMASK(11, 6) -#define C2H_PFCH_CFG_2_NUM_MASK GENMASK(5, 0) -#define EQDMA_CPM5_C2H_INT_TIMER_TICK_ADDR 0xB0C -#define C2H_INT_TIMER_TICK_MASK GENMASK(31, 0) -#define EQDMA_CPM5_C2H_STAT_DESC_RSP_DROP_ACCEPTED_ADDR 0xB10 -#define C2H_STAT_DESC_RSP_DROP_ACCEPTED_RSVD_1_MASK GENMASK(31, 18) -#define C2H_STAT_DESC_RSP_DROP_ACCEPTED_D_MASK GENMASK(17, 0) -#define EQDMA_CPM5_C2H_STAT_DESC_RSP_ERR_ACCEPTED_ADDR 0xB14 -#define C2H_STAT_DESC_RSP_ERR_ACCEPTED_RSVD_1_MASK GENMASK(31, 18) -#define C2H_STAT_DESC_RSP_ERR_ACCEPTED_D_MASK GENMASK(17, 0) -#define EQDMA_CPM5_C2H_STAT_DESC_REQ_ADDR 0xB18 -#define C2H_STAT_DESC_REQ_RSVD_1_MASK GENMASK(31, 18) -#define C2H_STAT_DESC_REQ_MASK GENMASK(17, 0) -#define EQDMA_CPM5_C2H_STAT_DBG_DMA_ENG_0_ADDR 0xB1C -#define C2H_STAT_DMA_ENG_0_S_AXIS_C2H_TVALID_MASK BIT(31) -#define C2H_STAT_DMA_ENG_0_S_AXIS_C2H_TREADY_MASK BIT(30) -#define C2H_STAT_DMA_ENG_0_S_AXIS_WRB_TVALID_MASK GENMASK(29, 27) -#define C2H_STAT_DMA_ENG_0_S_AXIS_WRB_TREADY_MASK GENMASK(26, 24) -#define C2H_STAT_DMA_ENG_0_PLD_FIFO_IN_RDY_MASK BIT(23) -#define C2H_STAT_DMA_ENG_0_QID_FIFO_IN_RDY_MASK BIT(22) -#define C2H_STAT_DMA_ENG_0_ARB_FIFO_OUT_VLD_MASK BIT(21) -#define C2H_STAT_DMA_ENG_0_ARB_FIFO_OUT_QID_MASK GENMASK(20, 9) -#define C2H_STAT_DMA_ENG_0_WRB_FIFO_IN_RDY_MASK BIT(8) -#define C2H_STAT_DMA_ENG_0_WRB_FIFO_OUT_CNT_MASK GENMASK(7, 5) -#define C2H_STAT_DMA_ENG_0_WRB_SM_CS_MASK BIT(4) -#define C2H_STAT_DMA_ENG_0_MAIN_SM_CS_MASK GENMASK(3, 0) -#define EQDMA_CPM5_C2H_STAT_DBG_DMA_ENG_1_ADDR 0xB20 -#define C2H_STAT_DMA_ENG_1_RSVD_1_MASK GENMASK(31, 29) -#define C2H_STAT_DMA_ENG_1_QID_FIFO_OUT_CNT_MASK GENMASK(28, 18) -#define C2H_STAT_DMA_ENG_1_PLD_FIFO_OUT_CNT_MASK GENMASK(17, 7) -#define C2H_STAT_DMA_ENG_1_PLD_ST_FIFO_CNT_MASK GENMASK(6, 0) -#define EQDMA_CPM5_C2H_STAT_DBG_DMA_ENG_2_ADDR 0xB24 -#define C2H_STAT_DMA_ENG_2_RSVD_1_MASK GENMASK(31, 29) -#define C2H_STAT_DMA_ENG_2_QID_FIFO_OUT_CNT_MASK GENMASK(28, 18) -#define C2H_STAT_DMA_ENG_2_PLD_FIFO_OUT_CNT_MASK GENMASK(17, 7) -#define C2H_STAT_DMA_ENG_2_PLD_ST_FIFO_CNT_MASK GENMASK(6, 0) -#define EQDMA_CPM5_C2H_STAT_DBG_DMA_ENG_3_ADDR 0xB28 -#define C2H_STAT_DMA_ENG_3_RSVD_1_MASK GENMASK(31, 24) -#define C2H_STAT_DMA_ENG_3_WRQ_FIFO_OUT_CNT_MASK GENMASK(23, 19) -#define C2H_STAT_DMA_ENG_3_QID_FIFO_OUT_VLD_MASK BIT(18) -#define C2H_STAT_DMA_ENG_3_PLD_FIFO_OUT_VLD_MASK BIT(17) -#define C2H_STAT_DMA_ENG_3_PLD_ST_FIFO_OUT_VLD_MASK BIT(16) -#define C2H_STAT_DMA_ENG_3_PLD_ST_FIFO_OUT_DATA_EOP_MASK BIT(15) -#define C2H_STAT_DMA_ENG_3_PLD_ST_FIFO_OUT_DATA_AVL_IDX_ENABLE_MASK BIT(14) -#define C2H_STAT_DMA_ENG_3_PLD_ST_FIFO_OUT_DATA_DROP_MASK BIT(13) -#define C2H_STAT_DMA_ENG_3_PLD_ST_FIFO_OUT_DATA_ERR_MASK BIT(12) -#define C2H_STAT_DMA_ENG_3_DESC_CNT_FIFO_IN_RDY_MASK BIT(11) -#define C2H_STAT_DMA_ENG_3_DESC_RSP_FIFO_IN_RDY_MASK BIT(10) -#define C2H_STAT_DMA_ENG_3_PLD_PKT_ID_LARGER_0_MASK BIT(9) -#define C2H_STAT_DMA_ENG_3_WRQ_VLD_MASK BIT(8) -#define C2H_STAT_DMA_ENG_3_WRQ_RDY_MASK BIT(7) -#define C2H_STAT_DMA_ENG_3_WRQ_FIFO_OUT_RDY_MASK BIT(6) -#define C2H_STAT_DMA_ENG_3_WRQ_PACKET_OUT_DATA_DROP_MASK BIT(5) -#define C2H_STAT_DMA_ENG_3_WRQ_PACKET_OUT_DATA_ERR_MASK BIT(4) -#define C2H_STAT_DMA_ENG_3_WRQ_PACKET_OUT_DATA_MARKER_MASK BIT(3) -#define C2H_STAT_DMA_ENG_3_WRQ_PACKET_PRE_EOR_MASK BIT(2) -#define C2H_STAT_DMA_ENG_3_WCP_FIFO_IN_RDY_MASK BIT(1) -#define C2H_STAT_DMA_ENG_3_PLD_ST_FIFO_IN_RDY_MASK BIT(0) -#define EQDMA_CPM5_C2H_DBG_PFCH_ERR_CTXT_ADDR 0xB2C -#define C2H_PFCH_ERR_CTXT_RSVD_1_MASK GENMASK(31, 14) -#define C2H_PFCH_ERR_CTXT_ERR_STAT_MASK BIT(13) -#define C2H_PFCH_ERR_CTXT_CMD_WR_MASK BIT(12) -#define C2H_PFCH_ERR_CTXT_QID_MASK GENMASK(11, 1) -#define C2H_PFCH_ERR_CTXT_DONE_MASK BIT(0) -#define EQDMA_CPM5_C2H_FIRST_ERR_QID_ADDR 0xB30 -#define C2H_FIRST_ERR_QID_RSVD_1_MASK GENMASK(31, 21) -#define C2H_FIRST_ERR_QID_ERR_TYPE_MASK GENMASK(20, 16) -#define C2H_FIRST_ERR_QID_RSVD_MASK GENMASK(15, 13) -#define C2H_FIRST_ERR_QID_QID_MASK GENMASK(12, 0) -#define EQDMA_CPM5_STAT_NUM_WRB_IN_ADDR 0xB34 -#define STAT_NUM_WRB_IN_RSVD_1_MASK GENMASK(31, 16) -#define STAT_NUM_WRB_IN_WRB_CNT_MASK GENMASK(15, 0) -#define EQDMA_CPM5_STAT_NUM_WRB_OUT_ADDR 0xB38 -#define STAT_NUM_WRB_OUT_RSVD_1_MASK GENMASK(31, 16) -#define STAT_NUM_WRB_OUT_WRB_CNT_MASK GENMASK(15, 0) -#define EQDMA_CPM5_STAT_NUM_WRB_DRP_ADDR 0xB3C -#define STAT_NUM_WRB_DRP_RSVD_1_MASK GENMASK(31, 16) -#define STAT_NUM_WRB_DRP_WRB_CNT_MASK GENMASK(15, 0) -#define EQDMA_CPM5_STAT_NUM_STAT_DESC_OUT_ADDR 0xB40 -#define STAT_NUM_STAT_DESC_OUT_RSVD_1_MASK GENMASK(31, 16) -#define STAT_NUM_STAT_DESC_OUT_CNT_MASK GENMASK(15, 0) -#define EQDMA_CPM5_STAT_NUM_DSC_CRDT_SENT_ADDR 0xB44 -#define STAT_NUM_DSC_CRDT_SENT_RSVD_1_MASK GENMASK(31, 16) -#define STAT_NUM_DSC_CRDT_SENT_CNT_MASK GENMASK(15, 0) -#define EQDMA_CPM5_STAT_NUM_FCH_DSC_RCVD_ADDR 0xB48 -#define STAT_NUM_FCH_DSC_RCVD_RSVD_1_MASK GENMASK(31, 16) -#define STAT_NUM_FCH_DSC_RCVD_DSC_CNT_MASK GENMASK(15, 0) -#define EQDMA_CPM5_STAT_NUM_BYP_DSC_RCVD_ADDR 0xB4C -#define STAT_NUM_BYP_DSC_RCVD_RSVD_1_MASK GENMASK(31, 11) -#define STAT_NUM_BYP_DSC_RCVD_DSC_CNT_MASK GENMASK(10, 0) -#define EQDMA_CPM5_C2H_WRB_COAL_CFG_ADDR 0xB50 -#define C2H_WRB_COAL_CFG_MAX_BUF_SZ_MASK GENMASK(31, 26) -#define C2H_WRB_COAL_CFG_TICK_VAL_MASK GENMASK(25, 14) -#define C2H_WRB_COAL_CFG_TICK_CNT_MASK GENMASK(13, 2) -#define C2H_WRB_COAL_CFG_SET_GLB_FLUSH_MASK BIT(1) -#define C2H_WRB_COAL_CFG_DONE_GLB_FLUSH_MASK BIT(0) -#define EQDMA_CPM5_C2H_INTR_H2C_REQ_ADDR 0xB54 -#define C2H_INTR_H2C_REQ_RSVD_1_MASK GENMASK(31, 18) -#define C2H_INTR_H2C_REQ_CNT_MASK GENMASK(17, 0) -#define EQDMA_CPM5_C2H_INTR_C2H_MM_REQ_ADDR 0xB58 -#define C2H_INTR_C2H_MM_REQ_RSVD_1_MASK GENMASK(31, 18) -#define C2H_INTR_C2H_MM_REQ_CNT_MASK GENMASK(17, 0) -#define EQDMA_CPM5_C2H_INTR_ERR_INT_REQ_ADDR 0xB5C -#define C2H_INTR_ERR_INT_REQ_RSVD_1_MASK GENMASK(31, 18) -#define C2H_INTR_ERR_INT_REQ_CNT_MASK GENMASK(17, 0) -#define EQDMA_CPM5_C2H_INTR_C2H_ST_REQ_ADDR 0xB60 -#define C2H_INTR_C2H_ST_REQ_RSVD_1_MASK GENMASK(31, 18) -#define C2H_INTR_C2H_ST_REQ_CNT_MASK GENMASK(17, 0) -#define EQDMA_CPM5_C2H_INTR_H2C_ERR_C2H_MM_MSIX_ACK_ADDR 0xB64 -#define C2H_INTR_H2C_ERR_C2H_MM_MSIX_ACK_RSVD_1_MASK GENMASK(31, 18) -#define C2H_INTR_H2C_ERR_C2H_MM_MSIX_ACK_CNT_MASK GENMASK(17, 0) -#define EQDMA_CPM5_C2H_INTR_H2C_ERR_C2H_MM_MSIX_FAIL_ADDR 0xB68 -#define C2H_INTR_H2C_ERR_C2H_MM_MSIX_FAIL_RSVD_1_MASK GENMASK(31, 18) -#define C2H_INTR_H2C_ERR_C2H_MM_MSIX_FAIL_CNT_MASK GENMASK(17, 0) -#define EQDMA_CPM5_C2H_INTR_H2C_ERR_C2H_MM_MSIX_NO_MSIX_ADDR 0xB6C -#define C2H_INTR_H2C_ERR_C2H_MM_MSIX_NO_MSIX_RSVD_1_MASK GENMASK(31, 18) -#define C2H_INTR_H2C_ERR_C2H_MM_MSIX_NO_MSIX_CNT_MASK GENMASK(17, 0) -#define EQDMA_CPM5_C2H_INTR_H2C_ERR_C2H_MM_CTXT_INVAL_ADDR 0xB70 -#define C2H_INTR_H2C_ERR_C2H_MM_CTXT_INVAL_RSVD_1_MASK GENMASK(31, 18) -#define C2H_INTR_H2C_ERR_C2H_MM_CTXT_INVAL_CNT_MASK GENMASK(17, 0) -#define EQDMA_CPM5_C2H_INTR_C2H_ST_MSIX_ACK_ADDR 0xB74 -#define C2H_INTR_C2H_ST_MSIX_ACK_RSVD_1_MASK GENMASK(31, 18) -#define C2H_INTR_C2H_ST_MSIX_ACK_CNT_MASK GENMASK(17, 0) -#define EQDMA_CPM5_C2H_INTR_C2H_ST_MSIX_FAIL_ADDR 0xB78 -#define C2H_INTR_C2H_ST_MSIX_FAIL_RSVD_1_MASK GENMASK(31, 18) -#define C2H_INTR_C2H_ST_MSIX_FAIL_CNT_MASK GENMASK(17, 0) -#define EQDMA_CPM5_C2H_INTR_C2H_ST_NO_MSIX_ADDR 0xB7C -#define C2H_INTR_C2H_ST_NO_MSIX_RSVD_1_MASK GENMASK(31, 18) -#define C2H_INTR_C2H_ST_NO_MSIX_CNT_MASK GENMASK(17, 0) -#define EQDMA_CPM5_C2H_INTR_C2H_ST_CTXT_INVAL_ADDR 0xB80 -#define C2H_INTR_C2H_ST_CTXT_INVAL_RSVD_1_MASK GENMASK(31, 18) -#define C2H_INTR_C2H_ST_CTXT_INVAL_CNT_MASK GENMASK(17, 0) -#define EQDMA_CPM5_C2H_STAT_WR_CMP_ADDR 0xB84 -#define C2H_STAT_WR_CMP_RSVD_1_MASK GENMASK(31, 18) -#define C2H_STAT_WR_CMP_CNT_MASK GENMASK(17, 0) -#define EQDMA_CPM5_C2H_STAT_DBG_DMA_ENG_4_ADDR 0xB88 -#define C2H_STAT_DMA_ENG_4_RSVD_1_MASK GENMASK(31, 24) -#define C2H_STAT_DMA_ENG_4_WRQ_FIFO_OUT_CNT_MASK GENMASK(23, 19) -#define C2H_STAT_DMA_ENG_4_QID_FIFO_OUT_VLD_MASK BIT(18) -#define C2H_STAT_DMA_ENG_4_PLD_FIFO_OUT_VLD_MASK BIT(17) -#define C2H_STAT_DMA_ENG_4_PLD_ST_FIFO_OUT_VLD_MASK BIT(16) -#define C2H_STAT_DMA_ENG_4_PLD_ST_FIFO_OUT_DATA_EOP_MASK BIT(15) -#define C2H_STAT_DMA_ENG_4_PLD_ST_FIFO_OUT_DATA_AVL_IDX_ENABLE_MASK BIT(14) -#define C2H_STAT_DMA_ENG_4_PLD_ST_FIFO_OUT_DATA_DROP_MASK BIT(13) -#define C2H_STAT_DMA_ENG_4_PLD_ST_FIFO_OUT_DATA_ERR_MASK BIT(12) -#define C2H_STAT_DMA_ENG_4_DESC_CNT_FIFO_IN_RDY_MASK BIT(11) -#define C2H_STAT_DMA_ENG_4_DESC_RSP_FIFO_IN_RDY_MASK BIT(10) -#define C2H_STAT_DMA_ENG_4_PLD_PKT_ID_LARGER_0_MASK BIT(9) -#define C2H_STAT_DMA_ENG_4_WRQ_VLD_MASK BIT(8) -#define C2H_STAT_DMA_ENG_4_WRQ_RDY_MASK BIT(7) -#define C2H_STAT_DMA_ENG_4_WRQ_FIFO_OUT_RDY_MASK BIT(6) -#define C2H_STAT_DMA_ENG_4_WRQ_PACKET_OUT_DATA_DROP_MASK BIT(5) -#define C2H_STAT_DMA_ENG_4_WRQ_PACKET_OUT_DATA_ERR_MASK BIT(4) -#define C2H_STAT_DMA_ENG_4_WRQ_PACKET_OUT_DATA_MARKER_MASK BIT(3) -#define C2H_STAT_DMA_ENG_4_WRQ_PACKET_PRE_EOR_MASK BIT(2) -#define C2H_STAT_DMA_ENG_4_WCP_FIFO_IN_RDY_MASK BIT(1) -#define C2H_STAT_DMA_ENG_4_PLD_ST_FIFO_IN_RDY_MASK BIT(0) -#define EQDMA_CPM5_C2H_STAT_DBG_DMA_ENG_5_ADDR 0xB8C -#define C2H_STAT_DMA_ENG_5_RSVD_1_MASK GENMASK(31, 30) -#define C2H_STAT_DMA_ENG_5_WRB_SM_VIRT_CH_MASK BIT(29) -#define C2H_STAT_DMA_ENG_5_WRB_FIFO_IN_REQ_MASK GENMASK(28, 24) -#define C2H_STAT_DMA_ENG_5_ARB_FIFO_OUT_CNT_MASK GENMASK(23, 22) -#define C2H_STAT_DMA_ENG_5_ARB_FIFO_OUT_DATA_LEN_MASK GENMASK(21, 6) -#define C2H_STAT_DMA_ENG_5_ARB_FIFO_OUT_DATA_VIRT_CH_MASK BIT(5) -#define C2H_STAT_DMA_ENG_5_ARB_FIFO_OUT_DATA_VAR_DESC_MASK BIT(4) -#define C2H_STAT_DMA_ENG_5_ARB_FIFO_OUT_DATA_DROP_REQ_MASK BIT(3) -#define C2H_STAT_DMA_ENG_5_ARB_FIFO_OUT_DATA_NUM_BUF_OV_MASK BIT(2) -#define C2H_STAT_DMA_ENG_5_ARB_FIFO_OUT_DATA_MARKER_MASK BIT(1) -#define C2H_STAT_DMA_ENG_5_ARB_FIFO_OUT_DATA_HAS_CMPT_MASK BIT(0) -#define EQDMA_CPM5_C2H_DBG_PFCH_QID_ADDR 0xB90 -#define C2H_PFCH_QID_RSVD_1_MASK GENMASK(31, 16) -#define C2H_PFCH_QID_ERR_CTXT_MASK BIT(15) -#define C2H_PFCH_QID_TARGET_MASK GENMASK(14, 12) -#define C2H_PFCH_QID_QID_OR_TAG_MASK GENMASK(11, 0) -#define EQDMA_CPM5_C2H_DBG_PFCH_ADDR 0xB94 -#define C2H_PFCH_DATA_MASK GENMASK(31, 0) -#define EQDMA_CPM5_C2H_INT_DBG_ADDR 0xB98 -#define C2H_INT_RSVD_1_MASK GENMASK(31, 8) -#define C2H_INT_INT_COAL_SM_MASK GENMASK(7, 4) -#define C2H_INT_INT_SM_MASK GENMASK(3, 0) -#define EQDMA_CPM5_C2H_STAT_IMM_ACCEPTED_ADDR 0xB9C -#define C2H_STAT_IMM_ACCEPTED_RSVD_1_MASK GENMASK(31, 18) -#define C2H_STAT_IMM_ACCEPTED_CNT_MASK GENMASK(17, 0) -#define EQDMA_CPM5_C2H_STAT_MARKER_ACCEPTED_ADDR 0xBA0 -#define C2H_STAT_MARKER_ACCEPTED_RSVD_1_MASK GENMASK(31, 18) -#define C2H_STAT_MARKER_ACCEPTED_CNT_MASK GENMASK(17, 0) -#define EQDMA_CPM5_C2H_STAT_DISABLE_CMP_ACCEPTED_ADDR 0xBA4 -#define C2H_STAT_DISABLE_CMP_ACCEPTED_RSVD_1_MASK GENMASK(31, 18) -#define C2H_STAT_DISABLE_CMP_ACCEPTED_CNT_MASK GENMASK(17, 0) -#define EQDMA_CPM5_C2H_PLD_FIFO_CRDT_CNT_ADDR 0xBA8 -#define C2H_PLD_FIFO_CRDT_CNT_RSVD_1_MASK GENMASK(31, 18) -#define C2H_PLD_FIFO_CRDT_CNT_CNT_MASK GENMASK(17, 0) -#define EQDMA_CPM5_C2H_INTR_DYN_REQ_ADDR 0xBAC -#define C2H_INTR_DYN_REQ_RSVD_1_MASK GENMASK(31, 18) -#define C2H_INTR_DYN_REQ_CNT_MASK GENMASK(17, 0) -#define EQDMA_CPM5_C2H_INTR_DYN_MISC_ADDR 0xBB0 -#define C2H_INTR_DYN_MISC_RSVD_1_MASK GENMASK(31, 18) -#define C2H_INTR_DYN_MISC_CNT_MASK GENMASK(17, 0) -#define EQDMA_CPM5_C2H_DROP_LEN_MISMATCH_ADDR 0xBB4 -#define C2H_DROP_LEN_MISMATCH_RSVD_1_MASK GENMASK(31, 18) -#define C2H_DROP_LEN_MISMATCH_CNT_MASK GENMASK(17, 0) -#define EQDMA_CPM5_C2H_DROP_DESC_RSP_LEN_ADDR 0xBB8 -#define C2H_DROP_DESC_RSP_LEN_RSVD_1_MASK GENMASK(31, 18) -#define C2H_DROP_DESC_RSP_LEN_CNT_MASK GENMASK(17, 0) -#define EQDMA_CPM5_C2H_DROP_QID_FIFO_LEN_ADDR 0xBBC -#define C2H_DROP_QID_FIFO_LEN_RSVD_1_MASK GENMASK(31, 18) -#define C2H_DROP_QID_FIFO_LEN_CNT_MASK GENMASK(17, 0) -#define EQDMA_CPM5_C2H_DROP_PLD_CNT_ADDR 0xBC0 -#define C2H_DROP_PLD_CNT_RSVD_1_MASK GENMASK(31, 18) -#define C2H_DROP_PLD_CNT_CNT_MASK GENMASK(17, 0) -#define EQDMA_CPM5_C2H_CMPT_FORMAT_0_ADDR 0xBC4 -#define C2H_CMPT_FORMAT_0_DESC_ERR_LOC_MASK GENMASK(31, 16) -#define C2H_CMPT_FORMAT_0_COLOR_LOC_MASK GENMASK(15, 0) -#define EQDMA_CPM5_C2H_CMPT_FORMAT_1_ADDR 0xBC8 -#define C2H_CMPT_FORMAT_1_DESC_ERR_LOC_MASK GENMASK(31, 16) -#define C2H_CMPT_FORMAT_1_COLOR_LOC_MASK GENMASK(15, 0) -#define EQDMA_CPM5_C2H_CMPT_FORMAT_2_ADDR 0xBCC -#define C2H_CMPT_FORMAT_2_DESC_ERR_LOC_MASK GENMASK(31, 16) -#define C2H_CMPT_FORMAT_2_COLOR_LOC_MASK GENMASK(15, 0) -#define EQDMA_CPM5_C2H_CMPT_FORMAT_3_ADDR 0xBD0 -#define C2H_CMPT_FORMAT_3_DESC_ERR_LOC_MASK GENMASK(31, 16) -#define C2H_CMPT_FORMAT_3_COLOR_LOC_MASK GENMASK(15, 0) -#define EQDMA_CPM5_C2H_CMPT_FORMAT_4_ADDR 0xBD4 -#define C2H_CMPT_FORMAT_4_DESC_ERR_LOC_MASK GENMASK(31, 16) -#define C2H_CMPT_FORMAT_4_COLOR_LOC_MASK GENMASK(15, 0) -#define EQDMA_CPM5_C2H_CMPT_FORMAT_5_ADDR 0xBD8 -#define C2H_CMPT_FORMAT_5_DESC_ERR_LOC_MASK GENMASK(31, 16) -#define C2H_CMPT_FORMAT_5_COLOR_LOC_MASK GENMASK(15, 0) -#define EQDMA_CPM5_C2H_CMPT_FORMAT_6_ADDR 0xBDC -#define C2H_CMPT_FORMAT_6_DESC_ERR_LOC_MASK GENMASK(31, 16) -#define C2H_CMPT_FORMAT_6_COLOR_LOC_MASK GENMASK(15, 0) -#define EQDMA_CPM5_C2H_PFCH_CACHE_DEPTH_ADDR 0xBE0 -#define C2H_PFCH_CACHE_DEPTH_MAX_STBUF_MASK GENMASK(23, 16) -#define C2H_PFCH_CACHE_DEPTH_MASK GENMASK(7, 0) -#define EQDMA_CPM5_C2H_WRB_COAL_BUF_DEPTH_ADDR 0xBE4 -#define C2H_WRB_COAL_BUF_DEPTH_RSVD_1_MASK GENMASK(31, 8) -#define C2H_WRB_COAL_BUF_DEPTH_BUFFER_MASK GENMASK(7, 0) -#define EQDMA_CPM5_C2H_PFCH_CRDT_ADDR 0xBE8 -#define C2H_PFCH_CRDT_RSVD_1_MASK GENMASK(31, 1) -#define C2H_PFCH_CRDT_RSVD_2_MASK BIT(0) -#define EQDMA_CPM5_C2H_STAT_HAS_CMPT_ACCEPTED_ADDR 0xBEC -#define C2H_STAT_HAS_CMPT_ACCEPTED_RSVD_1_MASK GENMASK(31, 18) -#define C2H_STAT_HAS_CMPT_ACCEPTED_CNT_MASK GENMASK(17, 0) -#define EQDMA_CPM5_C2H_STAT_HAS_PLD_ACCEPTED_ADDR 0xBF0 -#define C2H_STAT_HAS_PLD_ACCEPTED_RSVD_1_MASK GENMASK(31, 18) -#define C2H_STAT_HAS_PLD_ACCEPTED_CNT_MASK GENMASK(17, 0) -#define EQDMA_CPM5_C2H_PLD_PKT_ID_ADDR 0xBF4 -#define C2H_PLD_PKT_ID_CMPT_WAIT_MASK GENMASK(31, 16) -#define C2H_PLD_PKT_ID_DATA_MASK GENMASK(15, 0) -#define EQDMA_CPM5_C2H_PLD_PKT_ID_1_ADDR 0xBF8 -#define C2H_PLD_PKT_ID_1_CMPT_WAIT_MASK GENMASK(31, 16) -#define C2H_PLD_PKT_ID_1_DATA_MASK GENMASK(15, 0) -#define EQDMA_CPM5_C2H_DROP_PLD_CNT_1_ADDR 0xBFC -#define C2H_DROP_PLD_CNT_1_RSVD_1_MASK GENMASK(31, 18) -#define C2H_DROP_PLD_CNT_1_CNT_MASK GENMASK(17, 0) -#define EQDMA_CPM5_H2C_ERR_STAT_ADDR 0xE00 -#define H2C_ERR_STAT_RSVD_1_MASK GENMASK(31, 6) -#define H2C_ERR_STAT_PAR_ERR_MASK BIT(5) -#define H2C_ERR_STAT_SBE_MASK BIT(4) -#define H2C_ERR_STAT_DBE_MASK BIT(3) -#define H2C_ERR_STAT_NO_DMA_DS_MASK BIT(2) -#define H2C_ERR_STAT_SDI_MRKR_REQ_MOP_ERR_MASK BIT(1) -#define H2C_ERR_STAT_ZERO_LEN_DS_MASK BIT(0) -#define EQDMA_CPM5_H2C_ERR_MASK_ADDR 0xE04 -#define H2C_ERR_EN_MASK GENMASK(31, 0) -#define EQDMA_CPM5_H2C_FIRST_ERR_QID_ADDR 0xE08 -#define H2C_FIRST_ERR_QID_RSVD_1_MASK GENMASK(31, 20) -#define H2C_FIRST_ERR_QID_ERR_TYPE_MASK GENMASK(19, 16) -#define H2C_FIRST_ERR_QID_RSVD_2_MASK GENMASK(15, 13) -#define H2C_FIRST_ERR_QID_QID_MASK GENMASK(12, 0) -#define EQDMA_CPM5_H2C_DBG_REG0_ADDR 0xE0C -#define H2C_REG0_NUM_DSC_RCVD_MASK GENMASK(31, 16) -#define H2C_REG0_NUM_WRB_SENT_MASK GENMASK(15, 0) -#define EQDMA_CPM5_H2C_DBG_REG1_ADDR 0xE10 -#define H2C_REG1_NUM_REQ_SENT_MASK GENMASK(31, 16) -#define H2C_REG1_NUM_CMP_SENT_MASK GENMASK(15, 0) -#define EQDMA_CPM5_H2C_DBG_REG2_ADDR 0xE14 -#define H2C_REG2_RSVD_1_MASK GENMASK(31, 16) -#define H2C_REG2_NUM_ERR_DSC_RCVD_MASK GENMASK(15, 0) -#define EQDMA_CPM5_H2C_DBG_REG3_ADDR 0xE18 -#define H2C_REG3_RSVD_1_MASK BIT(31) -#define H2C_REG3_DSCO_FIFO_EMPTY_MASK BIT(30) -#define H2C_REG3_DSCO_FIFO_FULL_MASK BIT(29) -#define H2C_REG3_CUR_RC_STATE_MASK GENMASK(28, 26) -#define H2C_REG3_RDREQ_LINES_MASK GENMASK(25, 16) -#define H2C_REG3_RDATA_LINES_AVAIL_MASK GENMASK(15, 6) -#define H2C_REG3_PEND_FIFO_EMPTY_MASK BIT(5) -#define H2C_REG3_PEND_FIFO_FULL_MASK BIT(4) -#define H2C_REG3_CUR_RQ_STATE_MASK GENMASK(3, 2) -#define H2C_REG3_DSCI_FIFO_FULL_MASK BIT(1) -#define H2C_REG3_DSCI_FIFO_EMPTY_MASK BIT(0) -#define EQDMA_CPM5_H2C_DBG_REG4_ADDR 0xE1C -#define H2C_REG4_RDREQ_ADDR_MASK GENMASK(31, 0) -#define EQDMA_CPM5_H2C_FATAL_ERR_EN_ADDR 0xE20 -#define H2C_FATAL_ERR_EN_RSVD_1_MASK GENMASK(31, 1) -#define H2C_FATAL_ERR_EN_H2C_MASK BIT(0) -#define EQDMA_CPM5_H2C_REQ_THROT_PCIE_ADDR 0xE24 -#define H2C_REQ_THROT_PCIE_EN_REQ_MASK BIT(31) -#define H2C_REQ_THROT_PCIE_MASK GENMASK(30, 19) -#define H2C_REQ_THROT_PCIE_EN_DATA_MASK BIT(18) -#define H2C_REQ_THROT_PCIE_DATA_THRESH_MASK GENMASK(17, 0) -#define EQDMA_CPM5_H2C_ALN_DBG_REG0_ADDR 0xE28 -#define H2C_ALN_REG0_NUM_PKT_SENT_MASK GENMASK(15, 0) -#define EQDMA_CPM5_H2C_REQ_THROT_AXIMM_ADDR 0xE2C -#define H2C_REQ_THROT_AXIMM_EN_REQ_MASK BIT(31) -#define H2C_REQ_THROT_AXIMM_MASK GENMASK(30, 19) -#define H2C_REQ_THROT_AXIMM_EN_DATA_MASK BIT(18) -#define H2C_REQ_THROT_AXIMM_DATA_THRESH_MASK GENMASK(17, 0) -#define EQDMA_CPM5_C2H_MM_CTL_ADDR 0x1004 -#define C2H_MM_CTL_RESERVED1_MASK GENMASK(31, 9) -#define C2H_MM_CTL_ERRC_EN_MASK BIT(8) -#define C2H_MM_CTL_RESERVED0_MASK GENMASK(7, 1) -#define C2H_MM_CTL_RUN_MASK BIT(0) -#define EQDMA_CPM5_C2H_MM_STATUS_ADDR 0x1040 -#define C2H_MM_STATUS_RSVD_1_MASK GENMASK(31, 1) -#define C2H_MM_STATUS_RUN_MASK BIT(0) -#define EQDMA_CPM5_C2H_MM_CMPL_DESC_CNT_ADDR 0x1048 -#define C2H_MM_CMPL_DESC_CNT_C2H_CO_MASK GENMASK(31, 0) -#define EQDMA_CPM5_C2H_MM_ERR_CODE_ENABLE_MASK_ADDR 0x1054 -#define C2H_MM_ERR_CODE_ENABLE_RESERVED1_MASK BIT(31) -#define C2H_MM_ERR_CODE_ENABLE_WR_UC_RAM_MASK BIT(30) -#define C2H_MM_ERR_CODE_ENABLE_WR_UR_MASK BIT(29) -#define C2H_MM_ERR_CODE_ENABLE_WR_FLR_MASK BIT(28) -#define C2H_MM_ERR_CODE_ENABLE_RESERVED0_MASK GENMASK(27, 2) -#define C2H_MM_ERR_CODE_ENABLE_RD_SLV_ERR_MASK BIT(1) -#define C2H_MM_ERR_CODE_ENABLE_WR_SLV_ERR_MASK BIT(0) -#define EQDMA_CPM5_C2H_MM_ERR_CODE_ADDR 0x1058 -#define C2H_MM_ERR_CODE_RESERVED1_MASK GENMASK(31, 28) -#define C2H_MM_ERR_CODE_CIDX_MASK GENMASK(27, 12) -#define C2H_MM_ERR_CODE_RESERVED0_MASK GENMASK(11, 10) -#define C2H_MM_ERR_CODE_SUB_TYPE_MASK GENMASK(9, 5) -#define C2H_MM_ERR_CODE_MASK GENMASK(4, 0) -#define EQDMA_CPM5_C2H_MM_ERR_INFO_ADDR 0x105C -#define C2H_MM_ERR_INFO_VALID_MASK BIT(31) -#define C2H_MM_ERR_INFO_SEL_MASK BIT(30) -#define C2H_MM_ERR_INFO_RSVD_1_MASK GENMASK(29, 24) -#define C2H_MM_ERR_INFO_QID_MASK GENMASK(23, 0) -#define EQDMA_CPM5_C2H_MM_PERF_MON_CTL_ADDR 0x10C0 -#define C2H_MM_PERF_MON_CTL_RSVD_1_MASK GENMASK(31, 4) -#define C2H_MM_PERF_MON_CTL_IMM_START_MASK BIT(3) -#define C2H_MM_PERF_MON_CTL_RUN_START_MASK BIT(2) -#define C2H_MM_PERF_MON_CTL_IMM_CLEAR_MASK BIT(1) -#define C2H_MM_PERF_MON_CTL_RUN_CLEAR_MASK BIT(0) -#define EQDMA_CPM5_C2H_MM_PERF_MON_CYCLE_CNT0_ADDR 0x10C4 -#define C2H_MM_PERF_MON_CYCLE_CNT0_CYC_CNT_MASK GENMASK(31, 0) -#define EQDMA_CPM5_C2H_MM_PERF_MON_CYCLE_CNT1_ADDR 0x10C8 -#define C2H_MM_PERF_MON_CYCLE_CNT1_RSVD_1_MASK GENMASK(31, 10) -#define C2H_MM_PERF_MON_CYCLE_CNT1_CYC_CNT_MASK GENMASK(9, 0) -#define EQDMA_CPM5_C2H_MM_PERF_MON_DATA_CNT0_ADDR 0x10CC -#define C2H_MM_PERF_MON_DATA_CNT0_DCNT_MASK GENMASK(31, 0) -#define EQDMA_CPM5_C2H_MM_PERF_MON_DATA_CNT1_ADDR 0x10D0 -#define C2H_MM_PERF_MON_DATA_CNT1_RSVD_1_MASK GENMASK(31, 10) -#define C2H_MM_PERF_MON_DATA_CNT1_DCNT_MASK GENMASK(9, 0) -#define EQDMA_CPM5_C2H_MM_DBG_ADDR 0x10E8 -#define C2H_MM_RSVD_1_MASK GENMASK(31, 24) -#define C2H_MM_RRQ_ENTRIES_MASK GENMASK(23, 17) -#define C2H_MM_DAT_FIFO_SPC_MASK GENMASK(16, 7) -#define C2H_MM_RD_STALL_MASK BIT(6) -#define C2H_MM_RRQ_FIFO_FI_MASK BIT(5) -#define C2H_MM_WR_STALL_MASK BIT(4) -#define C2H_MM_WRQ_FIFO_FI_MASK BIT(3) -#define C2H_MM_WBK_STALL_MASK BIT(2) -#define C2H_MM_DSC_FIFO_EP_MASK BIT(1) -#define C2H_MM_DSC_FIFO_FL_MASK BIT(0) -#define EQDMA_CPM5_H2C_MM_CTL_ADDR 0x1204 -#define H2C_MM_CTL_RESERVED1_MASK GENMASK(31, 9) -#define H2C_MM_CTL_ERRC_EN_MASK BIT(8) -#define H2C_MM_CTL_RESERVED0_MASK GENMASK(7, 1) -#define H2C_MM_CTL_RUN_MASK BIT(0) -#define EQDMA_CPM5_H2C_MM_STATUS_ADDR 0x1240 -#define H2C_MM_STATUS_RSVD_1_MASK GENMASK(31, 1) -#define H2C_MM_STATUS_RUN_MASK BIT(0) -#define EQDMA_CPM5_H2C_MM_CMPL_DESC_CNT_ADDR 0x1248 -#define H2C_MM_CMPL_DESC_CNT_H2C_CO_MASK GENMASK(31, 0) -#define EQDMA_CPM5_H2C_MM_ERR_CODE_ENABLE_MASK_ADDR 0x1254 -#define H2C_MM_ERR_CODE_ENABLE_RESERVED5_MASK GENMASK(31, 30) -#define H2C_MM_ERR_CODE_ENABLE_WR_SLV_ERR_MASK BIT(29) -#define H2C_MM_ERR_CODE_ENABLE_WR_DEC_ERR_MASK BIT(28) -#define H2C_MM_ERR_CODE_ENABLE_RESERVED4_MASK GENMASK(27, 23) -#define H2C_MM_ERR_CODE_ENABLE_RD_RQ_DIS_ERR_MASK BIT(22) -#define H2C_MM_ERR_CODE_ENABLE_RESERVED3_MASK GENMASK(21, 17) -#define H2C_MM_ERR_CODE_ENABLE_RD_DAT_POISON_ERR_MASK BIT(16) -#define H2C_MM_ERR_CODE_ENABLE_RESERVED2_MASK GENMASK(15, 9) -#define H2C_MM_ERR_CODE_ENABLE_RD_FLR_ERR_MASK BIT(8) -#define H2C_MM_ERR_CODE_ENABLE_RESERVED1_MASK GENMASK(7, 6) -#define H2C_MM_ERR_CODE_ENABLE_RD_HDR_ADR_ERR_MASK BIT(5) -#define H2C_MM_ERR_CODE_ENABLE_RD_HDR_PARA_MASK BIT(4) -#define H2C_MM_ERR_CODE_ENABLE_RD_HDR_BYTE_ERR_MASK BIT(3) -#define H2C_MM_ERR_CODE_ENABLE_RD_UR_CA_MASK BIT(2) -#define H2C_MM_ERR_CODE_ENABLE_RD_HRD_POISON_ERR_MASK BIT(1) -#define H2C_MM_ERR_CODE_ENABLE_RESERVED0_MASK BIT(0) -#define EQDMA_CPM5_H2C_MM_ERR_CODE_ADDR 0x1258 -#define H2C_MM_ERR_CODE_RSVD_1_MASK GENMASK(31, 28) -#define H2C_MM_ERR_CODE_CIDX_MASK GENMASK(27, 12) -#define H2C_MM_ERR_CODE_RESERVED0_MASK GENMASK(11, 10) -#define H2C_MM_ERR_CODE_SUB_TYPE_MASK GENMASK(9, 5) -#define H2C_MM_ERR_CODE_MASK GENMASK(4, 0) -#define EQDMA_CPM5_H2C_MM_ERR_INFO_ADDR 0x125C -#define H2C_MM_ERR_INFO_VALID_MASK BIT(31) -#define H2C_MM_ERR_INFO_SEL_MASK BIT(30) -#define H2C_MM_ERR_INFO_RSVD_1_MASK GENMASK(29, 24) -#define H2C_MM_ERR_INFO_QID_MASK GENMASK(23, 0) -#define EQDMA_CPM5_H2C_MM_PERF_MON_CTL_ADDR 0x12C0 -#define H2C_MM_PERF_MON_CTL_RSVD_1_MASK GENMASK(31, 4) -#define H2C_MM_PERF_MON_CTL_IMM_START_MASK BIT(3) -#define H2C_MM_PERF_MON_CTL_RUN_START_MASK BIT(2) -#define H2C_MM_PERF_MON_CTL_IMM_CLEAR_MASK BIT(1) -#define H2C_MM_PERF_MON_CTL_RUN_CLEAR_MASK BIT(0) -#define EQDMA_CPM5_H2C_MM_PERF_MON_CYCLE_CNT0_ADDR 0x12C4 -#define H2C_MM_PERF_MON_CYCLE_CNT0_CYC_CNT_MASK GENMASK(31, 0) -#define EQDMA_CPM5_H2C_MM_PERF_MON_CYCLE_CNT1_ADDR 0x12C8 -#define H2C_MM_PERF_MON_CYCLE_CNT1_RSVD_1_MASK GENMASK(31, 10) -#define H2C_MM_PERF_MON_CYCLE_CNT1_CYC_CNT_MASK GENMASK(9, 0) -#define EQDMA_CPM5_H2C_MM_PERF_MON_DATA_CNT0_ADDR 0x12CC -#define H2C_MM_PERF_MON_DATA_CNT0_DCNT_MASK GENMASK(31, 0) -#define EQDMA_CPM5_H2C_MM_PERF_MON_DATA_CNT1_ADDR 0x12D0 -#define H2C_MM_PERF_MON_DATA_CNT1_RSVD_1_MASK GENMASK(31, 10) -#define H2C_MM_PERF_MON_DATA_CNT1_DCNT_MASK GENMASK(9, 0) -#define EQDMA_CPM5_H2C_MM_DBG_ADDR 0x12E8 -#define H2C_MM_RSVD_1_MASK GENMASK(31, 24) -#define H2C_MM_RRQ_ENTRIES_MASK GENMASK(23, 17) -#define H2C_MM_DAT_FIFO_SPC_MASK GENMASK(16, 7) -#define H2C_MM_RD_STALL_MASK BIT(6) -#define H2C_MM_RRQ_FIFO_FI_MASK BIT(5) -#define H2C_MM_WR_STALL_MASK BIT(4) -#define H2C_MM_WRQ_FIFO_FI_MASK BIT(3) -#define H2C_MM_WBK_STALL_MASK BIT(2) -#define H2C_MM_DSC_FIFO_EP_MASK BIT(1) -#define H2C_MM_DSC_FIFO_FL_MASK BIT(0) -#define EQDMA_CPM5_C2H_CRDT_COAL_CFG_1_ADDR 0x1400 -#define C2H_CRDT_COAL_CFG_1_RSVD_1_MASK GENMASK(31, 18) -#define C2H_CRDT_COAL_CFG_1_PLD_FIFO_TH_MASK GENMASK(17, 10) -#define C2H_CRDT_COAL_CFG_1_TIMER_TH_MASK GENMASK(9, 0) -#define EQDMA_CPM5_C2H_CRDT_COAL_CFG_2_ADDR 0x1404 -#define C2H_CRDT_COAL_CFG_2_RSVD_1_MASK GENMASK(31, 24) -#define C2H_CRDT_COAL_CFG_2_FIFO_TH_MASK GENMASK(23, 16) -#define C2H_CRDT_COAL_CFG_2_RESERVED1_MASK GENMASK(15, 11) -#define C2H_CRDT_COAL_CFG_2_NT_TH_MASK GENMASK(10, 0) -#define EQDMA_CPM5_C2H_PFCH_BYP_QID_ADDR 0x1408 -#define C2H_PFCH_BYP_QID_RSVD_1_MASK GENMASK(31, 12) -#define C2H_PFCH_BYP_QID_MASK GENMASK(11, 0) -#define EQDMA_CPM5_C2H_PFCH_BYP_TAG_ADDR 0x140C -#define C2H_PFCH_BYP_TAG_RSVD_1_MASK GENMASK(31, 20) -#define C2H_PFCH_BYP_TAG_BYP_QID_MASK GENMASK(19, 8) -#define C2H_PFCH_BYP_TAG_RSVD_2_MASK BIT(7) -#define C2H_PFCH_BYP_TAG_MASK GENMASK(6, 0) -#define EQDMA_CPM5_C2H_WATER_MARK_ADDR 0x1500 -#define C2H_WATER_MARK_HIGH_WM_MASK GENMASK(31, 16) -#define C2H_WATER_MARK_LOW_WM_MASK GENMASK(15, 0) -#define EQDMA_CPM5_C2H_NOTIFY_EMPTY_ADDR 0x1800 -#define C2H_NOTIFY_EMPTY_RSVD_1_MASK GENMASK(31, 16) -#define C2H_NOTIFY_EMPTY_NOE_MASK GENMASK(15, 0) -#define EQDMA_CPM5_C2H_STAT_S_AXIS_C2H_ACCEPTED_1_ADDR 0x1804 -#define C2H_STAT_S_AXIS_C2H_ACCEPTED_1_MASK GENMASK(31, 0) -#define EQDMA_CPM5_C2H_STAT_S_AXIS_WRB_ACCEPTED_1_ADDR 0x1808 -#define C2H_STAT_S_AXIS_WRB_ACCEPTED_1_MASK GENMASK(31, 0) -#define EQDMA_CPM5_C2H_STAT_DESC_RSP_PKT_ACCEPTED_1_ADDR 0x180C -#define C2H_STAT_DESC_RSP_PKT_ACCEPTED_1_D_MASK GENMASK(31, 0) -#define EQDMA_CPM5_C2H_STAT_AXIS_PKG_CMP_1_ADDR 0x1810 -#define C2H_STAT_AXIS_PKG_CMP_1_MASK GENMASK(31, 0) -#define EQDMA_CPM5_C2H_STAT_S_AXIS_WRB_ACCEPTED_2_ADDR 0x1814 -#define C2H_STAT_S_AXIS_WRB_ACCEPTED_2_MASK GENMASK(31, 0) -#define EQDMA_CPM5_C2H_ST_PLD_FIFO_DEPTH_ADDR 0x1818 -#define C2H_ST_PLD_FIFO_DEPTH_MASK GENMASK(31, 0) -#define SW_IND_CTXT_DATA_W7_VIRTIO_DSC_BASE_H_MASK GENMASK(10, 0) -#define SW_IND_CTXT_DATA_W6_VIRTIO_DSC_BASE_M_MASK GENMASK(31, 0) -#define SW_IND_CTXT_DATA_W5_VIRTIO_DSC_BASE_L_MASK GENMASK(31, 11) -#define SW_IND_CTXT_DATA_W5_PASID_EN_MASK BIT(10) -#define SW_IND_CTXT_DATA_W5_PASID_H_MASK GENMASK(9, 0) -#define SW_IND_CTXT_DATA_W4_PASID_L_MASK GENMASK(31, 20) -#define SW_IND_CTXT_DATA_W4_HOST_ID_MASK GENMASK(19, 16) -#define SW_IND_CTXT_DATA_W4_IRQ_BYP_MASK BIT(15) -#define SW_IND_CTXT_DATA_W4_PACK_BYP_OUT_MASK BIT(14) -#define SW_IND_CTXT_DATA_W4_VIRTIO_EN_MASK BIT(13) -#define SW_IND_CTXT_DATA_W4_DIS_INTR_ON_VF_MASK BIT(12) -#define SW_IND_CTXT_DATA_W4_INT_AGGR_MASK BIT(11) -#define SW_IND_CTXT_DATA_W4_VEC_MASK GENMASK(10, 0) -#define SW_IND_CTXT_DATA_W3_DSC_BASE_H_MASK GENMASK(31, 0) -#define SW_IND_CTXT_DATA_W2_DSC_BASE_L_MASK GENMASK(31, 0) -#define SW_IND_CTXT_DATA_W1_IS_MM_MASK BIT(31) -#define SW_IND_CTXT_DATA_W1_MRKR_DIS_MASK BIT(30) -#define SW_IND_CTXT_DATA_W1_IRQ_REQ_MASK BIT(29) -#define SW_IND_CTXT_DATA_W1_ERR_WB_SENT_MASK BIT(28) -#define SW_IND_CTXT_DATA_W1_ERR_MASK GENMASK(27, 26) -#define SW_IND_CTXT_DATA_W1_IRQ_NO_LAST_MASK BIT(25) -#define SW_IND_CTXT_DATA_W1_PORT_ID_MASK GENMASK(24, 22) -#define SW_IND_CTXT_DATA_W1_IRQ_EN_MASK BIT(21) -#define SW_IND_CTXT_DATA_W1_WBK_EN_MASK BIT(20) -#define SW_IND_CTXT_DATA_W1_MM_CHN_MASK BIT(19) -#define SW_IND_CTXT_DATA_W1_BYPASS_MASK BIT(18) -#define SW_IND_CTXT_DATA_W1_DSC_SZ_MASK GENMASK(17, 16) -#define SW_IND_CTXT_DATA_W1_RNG_SZ_MASK GENMASK(15, 12) -#define SW_IND_CTXT_DATA_W1_RSVD_1_MASK GENMASK(11, 9) -#define SW_IND_CTXT_DATA_W1_FETCH_MAX_MASK GENMASK(8, 5) -#define SW_IND_CTXT_DATA_W1_AT_MASK BIT(4) -#define SW_IND_CTXT_DATA_W1_WBI_INTVL_EN_MASK BIT(3) -#define SW_IND_CTXT_DATA_W1_WBI_CHK_MASK BIT(2) -#define SW_IND_CTXT_DATA_W1_FCRD_EN_MASK BIT(1) -#define SW_IND_CTXT_DATA_W1_QEN_MASK BIT(0) -#define SW_IND_CTXT_DATA_W0_RSV_MASK GENMASK(31, 29) -#define SW_IND_CTXT_DATA_W0_FNC_MASK GENMASK(28, 17) -#define SW_IND_CTXT_DATA_W0_IRQ_ARM_MASK BIT(16) -#define SW_IND_CTXT_DATA_W0_PIDX_MASK GENMASK(15, 0) -#define HW_IND_CTXT_DATA_W1_RSVD_1_MASK BIT(15) -#define HW_IND_CTXT_DATA_W1_FETCH_PND_MASK GENMASK(14, 11) -#define HW_IND_CTXT_DATA_W1_EVT_PND_MASK BIT(10) -#define HW_IND_CTXT_DATA_W1_IDL_STP_B_MASK BIT(9) -#define HW_IND_CTXT_DATA_W1_DSC_PND_MASK BIT(8) -#define HW_IND_CTXT_DATA_W1_RSVD_2_MASK GENMASK(7, 0) -#define HW_IND_CTXT_DATA_W0_CRD_USE_MASK GENMASK(31, 16) -#define HW_IND_CTXT_DATA_W0_CIDX_MASK GENMASK(15, 0) -#define CRED_CTXT_DATA_W0_RSVD_1_MASK GENMASK(31, 16) -#define CRED_CTXT_DATA_W0_CREDT_MASK GENMASK(15, 0) -#define PREFETCH_CTXT_DATA_W1_VALID_MASK BIT(13) -#define PREFETCH_CTXT_DATA_W1_SW_CRDT_H_MASK GENMASK(12, 0) -#define PREFETCH_CTXT_DATA_W0_SW_CRDT_L_MASK GENMASK(31, 29) -#define PREFETCH_CTXT_DATA_W0_PFCH_MASK BIT(28) -#define PREFETCH_CTXT_DATA_W0_PFCH_EN_MASK BIT(27) -#define PREFETCH_CTXT_DATA_W0_ERR_MASK BIT(26) -#define PREFETCH_CTXT_DATA_W0_RSVD_MASK GENMASK(25, 22) -#define PREFETCH_CTXT_DATA_W0_PFCH_NEED_MASK GENMASK(21, 16) -#define PREFETCH_CTXT_DATA_W0_NUM_PFCH_MASK GENMASK(15, 10) -#define PREFETCH_CTXT_DATA_W0_VIRTIO_MASK BIT(9) -#define PREFETCH_CTXT_DATA_W0_VAR_DESC_MASK BIT(8) -#define PREFETCH_CTXT_DATA_W0_PORT_ID_MASK GENMASK(7, 5) -#define PREFETCH_CTXT_DATA_W0_BUF_SZ_IDX_MASK GENMASK(4, 1) -#define PREFETCH_CTXT_DATA_W0_BYPASS_MASK BIT(0) -#define CMPL_CTXT_DATA_W6_RSVD_1_H_MASK GENMASK(7, 0) -#define CMPL_CTXT_DATA_W5_RSVD_1_L_MASK GENMASK(31, 23) -#define CMPL_CTXT_DATA_W5_PORT_ID_MASK GENMASK(22, 20) -#define CMPL_CTXT_DATA_W5_SH_CMPT_MASK BIT(19) -#define CMPL_CTXT_DATA_W5_VIO_EOP_MASK BIT(18) -#define CMPL_CTXT_DATA_W5_BADDR4_LOW_MASK GENMASK(17, 14) -#define CMPL_CTXT_DATA_W5_PASID_EN_MASK BIT(13) -#define CMPL_CTXT_DATA_W5_PASID_H_MASK GENMASK(12, 0) -#define CMPL_CTXT_DATA_W4_PASID_L_MASK GENMASK(31, 23) -#define CMPL_CTXT_DATA_W4_HOST_ID_MASK GENMASK(22, 19) -#define CMPL_CTXT_DATA_W4_DIR_C2H_MASK BIT(18) -#define CMPL_CTXT_DATA_W4_VIO_MASK BIT(17) -#define CMPL_CTXT_DATA_W4_DIS_INTR_ON_VF_MASK BIT(16) -#define CMPL_CTXT_DATA_W4_INT_AGGR_MASK BIT(15) -#define CMPL_CTXT_DATA_W4_VEC_MASK GENMASK(14, 4) -#define CMPL_CTXT_DATA_W4_AT_MASK BIT(3) -#define CMPL_CTXT_DATA_W4_OVF_CHK_DIS_MASK BIT(2) -#define CMPL_CTXT_DATA_W4_FULL_UPD_MASK BIT(1) -#define CMPL_CTXT_DATA_W4_TIMER_RUNNING_MASK BIT(0) -#define CMPL_CTXT_DATA_W3_USER_TRIG_PEND_MASK BIT(31) -#define CMPL_CTXT_DATA_W3_ERR_MASK GENMASK(30, 29) -#define CMPL_CTXT_DATA_W3_VALID_MASK BIT(28) -#define CMPL_CTXT_DATA_W3_CIDX_MASK GENMASK(27, 12) -#define CMPL_CTXT_DATA_W3_PIDX_H_MASK GENMASK(11, 0) -#define CMPL_CTXT_DATA_W2_PIDX_L_MASK GENMASK(31, 28) -#define CMPL_CTXT_DATA_W2_DESC_SIZE_MASK GENMASK(27, 26) -#define CMPL_CTXT_DATA_W2_BADDR4_HIGH_H_MASK GENMASK(25, 0) -#define CMPL_CTXT_DATA_W1_BADDR4_HIGH_L_MASK GENMASK(31, 0) -#define CMPL_CTXT_DATA_W0_QSIZE_IX_MASK GENMASK(31, 28) -#define CMPL_CTXT_DATA_W0_COLOR_MASK BIT(27) -#define CMPL_CTXT_DATA_W0_INT_ST_MASK GENMASK(26, 25) -#define CMPL_CTXT_DATA_W0_TIMER_IX_MASK GENMASK(24, 21) -#define CMPL_CTXT_DATA_W0_CNTER_IX_MASK GENMASK(20, 17) -#define CMPL_CTXT_DATA_W0_FNC_ID_MASK GENMASK(16, 5) -#define CMPL_CTXT_DATA_W0_TRIG_MODE_MASK GENMASK(4, 2) -#define CMPL_CTXT_DATA_W0_EN_INT_MASK BIT(1) -#define CMPL_CTXT_DATA_W0_EN_STAT_DESC_MASK BIT(0) -#define INTR_CTXT_DATA_W3_FUNC_MASK GENMASK(29, 18) -#define INTR_CTXT_DATA_W3_RSVD_MASK GENMASK(17, 14) -#define INTR_CTXT_DATA_W3_PASID_EN_MASK BIT(13) -#define INTR_CTXT_DATA_W3_PASID_H_MASK GENMASK(12, 0) -#define INTR_CTXT_DATA_W2_PASID_L_MASK GENMASK(31, 23) -#define INTR_CTXT_DATA_W2_HOST_ID_MASK GENMASK(22, 19) -#define INTR_CTXT_DATA_W2_AT_MASK BIT(18) -#define INTR_CTXT_DATA_W2_PIDX_MASK GENMASK(17, 6) -#define INTR_CTXT_DATA_W2_PAGE_SIZE_MASK GENMASK(5, 3) -#define INTR_CTXT_DATA_W2_BADDR_4K_H_MASK GENMASK(2, 0) -#define INTR_CTXT_DATA_W1_BADDR_4K_M_MASK GENMASK(31, 0) -#define INTR_CTXT_DATA_W0_BADDR_4K_L_MASK GENMASK(31, 15) -#define INTR_CTXT_DATA_W0_COLOR_MASK BIT(14) -#define INTR_CTXT_DATA_W0_INT_ST_MASK BIT(13) -#define INTR_CTXT_DATA_W0_RSVD1_MASK BIT(12) -#define INTR_CTXT_DATA_W0_VEC_MASK GENMASK(11, 1) -#define INTR_CTXT_DATA_W0_VALID_MASK BIT(0) -#define HOSTID_TABLE_W6_SMID_MASK GENMASK(9, 0) -#define HOSTID_TABLE_W5_H2C_MM_AWPROT_MASK GENMASK(27, 26) -#define HOSTID_TABLE_W5_H2C_MM_AWCACHE_MASK GENMASK(25, 22) -#define HOSTID_TABLE_W5_H2C_MM_AWSTEERING_MASK GENMASK(20, 18) -#define HOSTID_TABLE_W5_DSC_AWPROT_MASK GENMASK(17, 16) -#define HOSTID_TABLE_W5_DSC_AWCACHE_MASK GENMASK(15, 12) -#define HOSTID_TABLE_W5_DSC_AWSTEERING_MASK GENMASK(11, 8) -#define HOSTID_TABLE_W5_INT_MSG_AWPROT_MASK GENMASK(7, 6) -#define HOSTID_TABLE_W5_INT_MSG_AWCACHE_MASK GENMASK(5, 2) -#define HOSTID_TABLE_W5_INT_MSG_AWSTEERING_H_MASK GENMASK(0, 0) -#define HOSTID_TABLE_W4_INT_MSG_AWSTEERING_L_MASK GENMASK(31, 30) -#define HOSTID_TABLE_W4_INT_AGGR_AWPROT_MASK GENMASK(29, 28) -#define HOSTID_TABLE_W4_INT_AGGR_AWCACHE_MASK GENMASK(27, 24) -#define HOSTID_TABLE_W4_INT_AGGR_AWSTEERING_MASK GENMASK(22, 20) -#define HOSTID_TABLE_W4_CMPT_AWPROT_MASK GENMASK(19, 18) -#define HOSTID_TABLE_W4_CMPT_AWCACHE_MASK GENMASK(17, 14) -#define HOSTID_TABLE_W4_CMPT_AWSTEERING_MASK GENMASK(12, 10) -#define HOSTID_TABLE_W4_C2H_PLD_AWPROT_MASK GENMASK(9, 8) -#define HOSTID_TABLE_W4_C2H_PLD_AWCACHE_MASK GENMASK(7, 4) -#define HOSTID_TABLE_W4_C2H_PLD_AWSTEERING_MASK GENMASK(2, 0) -#define HOSTID_TABLE_W3_C2H_MM_ARPROT_MASK GENMASK(7, 6) -#define HOSTID_TABLE_W3_C2H_MM_ARCACHE_MASK GENMASK(5, 2) -#define HOSTID_TABLE_W3_C2H_MM_ARSTEERING_H_MASK GENMASK(0, 0) -#define HOSTID_TABLE_W2_C2H_MM_ARSTEERING_L_MASK GENMASK(31, 30) -#define HOSTID_TABLE_W2_H2C_MM_ARPROT_MASK GENMASK(29, 28) -#define HOSTID_TABLE_W2_H2C_MM_ARCACHE_MASK GENMASK(27, 24) -#define HOSTID_TABLE_W2_H2C_MM_ARSTEERING_MASK GENMASK(22, 20) -#define HOSTID_TABLE_W2_H2C_ST_ARPROT_MASK GENMASK(19, 18) -#define HOSTID_TABLE_W2_H2C_ST_ARCACHE_MASK GENMASK(17, 14) -#define HOSTID_TABLE_W2_H2C_ST_ARSTEERING_MASK GENMASK(12, 10) -#define HOSTID_TABLE_W2_DSC_ARPOT_MASK GENMASK(9, 8) -#define HOSTID_TABLE_W2_DSC_ARCACHE_MASK GENMASK(7, 4) -#define HOSTID_TABLE_W2_DSC_ARSTEERING_MASK GENMASK(2, 0) -#define HOSTID_TABLE_W0_VCH_H2C_MM_MASK GENMASK(27, 24) -#define HOSTID_TABLE_W0_VCH_H2C_ST_MASK GENMASK(23, 20) -#define HOSTID_TABLE_W0_VCH_DSC_MASK GENMASK(19, 16) -#define HOSTID_TABLE_W0_VCH_INT_MSG_MASK GENMASK(15, 12) -#define HOSTID_TABLE_W0_VCH_INT_AGGR_MASK GENMASK(11, 8) -#define HOSTID_TABLE_W0_VCH_CMPT_MASK GENMASK(7, 4) -#define HOSTID_TABLE_W0_VCH_H2C_PLD_MASK GENMASK(3, 0) -#define CTXT_SELC_FNC_STS_W0_MSIX_MASK GENMASK(3, 3) -#define CTXT_SELC_FNC_STS_W0_MSIX_ENABLE_MASK GENMASK(2, 2) -#define CTXT_SELC_FNC_STS_W0_MEM_SPACE_ENABLE_MASK GENMASK(1, 1) -#define CTXT_SELC_FNC_STS_W0_BUS_MASTER_ENABLE_MASK GENMASK(0, 0) - -#ifdef __cplusplus -} -#endif - -#endif - diff --git a/QDMA/DPDK/drivers/net/qdma/qdma_access/eqdma_cpm5_access/eqdma_cpm5_reg_dump.c b/QDMA/DPDK/drivers/net/qdma/qdma_access/eqdma_cpm5_access/eqdma_cpm5_reg_dump.c deleted file mode 100755 index af9a175c3..000000000 --- a/QDMA/DPDK/drivers/net/qdma/qdma_access/eqdma_cpm5_access/eqdma_cpm5_reg_dump.c +++ /dev/null @@ -1,4025 +0,0 @@ -/* - * Copyright (c) 2019-2022 Xilinx, Inc. All rights reserved. - * Copyright (c) 2022, Advanced Micro Devices, Inc. All rights reserved. - * - * BSD LICENSE - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * * Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include "eqdma_cpm5_reg.h" -#include "qdma_reg_dump.h" - -#ifdef ENABLE_WPP_TRACING -#include "eqdma_cpm5_reg_dump.tmh" -#endif - - -static struct regfield_info - cfg_blk_identifier_field_info[] = { - {"CFG_BLK_IDENTIFIER", - CFG_BLK_IDENTIFIER_MASK}, - {"CFG_BLK_IDENTIFIER_1", - CFG_BLK_IDENTIFIER_1_MASK}, - {"CFG_BLK_IDENTIFIER_RSVD_1", - CFG_BLK_IDENTIFIER_RSVD_1_MASK}, - {"CFG_BLK_IDENTIFIER_VERSION", - CFG_BLK_IDENTIFIER_VERSION_MASK}, -}; - - -static struct regfield_info - cfg_blk_pcie_max_pld_size_field_info[] = { - {"CFG_BLK_PCIE_MAX_PLD_SIZE_RSVD_1", - CFG_BLK_PCIE_MAX_PLD_SIZE_RSVD_1_MASK}, - {"CFG_BLK_PCIE_MAX_PLD_SIZE_PROG", - CFG_BLK_PCIE_MAX_PLD_SIZE_PROG_MASK}, - {"CFG_BLK_PCIE_MAX_PLD_SIZE_RSVD_2", - CFG_BLK_PCIE_MAX_PLD_SIZE_RSVD_2_MASK}, - {"CFG_BLK_PCIE_MAX_PLD_SIZE_ISSUED", - CFG_BLK_PCIE_MAX_PLD_SIZE_ISSUED_MASK}, -}; - - -static struct regfield_info - cfg_blk_pcie_max_read_req_size_field_info[] = { - {"CFG_BLK_PCIE_MAX_READ_REQ_SIZE_RSVD_1", - CFG_BLK_PCIE_MAX_READ_REQ_SIZE_RSVD_1_MASK}, - {"CFG_BLK_PCIE_MAX_READ_REQ_SIZE_PROG", - CFG_BLK_PCIE_MAX_READ_REQ_SIZE_PROG_MASK}, - {"CFG_BLK_PCIE_MAX_READ_REQ_SIZE_RSVD_2", - CFG_BLK_PCIE_MAX_READ_REQ_SIZE_RSVD_2_MASK}, - {"CFG_BLK_PCIE_MAX_READ_REQ_SIZE_ISSUED", - CFG_BLK_PCIE_MAX_READ_REQ_SIZE_ISSUED_MASK}, -}; - - -static struct regfield_info - cfg_blk_system_id_field_info[] = { - {"CFG_BLK_SYSTEM_ID_RSVD_1", - CFG_BLK_SYSTEM_ID_RSVD_1_MASK}, - {"CFG_BLK_SYSTEM_ID_INST_TYPE", - CFG_BLK_SYSTEM_ID_INST_TYPE_MASK}, - {"CFG_BLK_SYSTEM_ID", - CFG_BLK_SYSTEM_ID_MASK}, -}; - - -static struct regfield_info - cfg_blk_msix_enable_field_info[] = { - {"CFG_BLK_MSIX_ENABLE", - CFG_BLK_MSIX_ENABLE_MASK}, -}; - - -static struct regfield_info - cfg_pcie_data_width_field_info[] = { - {"CFG_PCIE_DATA_WIDTH_RSVD_1", - CFG_PCIE_DATA_WIDTH_RSVD_1_MASK}, - {"CFG_PCIE_DATA_WIDTH_DATAPATH", - CFG_PCIE_DATA_WIDTH_DATAPATH_MASK}, -}; - - -static struct regfield_info - cfg_pcie_ctl_field_info[] = { - {"CFG_PCIE_CTL_RSVD_1", - CFG_PCIE_CTL_RSVD_1_MASK}, - {"CFG_PCIE_CTL_MGMT_AXIL_CTRL", - CFG_PCIE_CTL_MGMT_AXIL_CTRL_MASK}, - {"CFG_PCIE_CTL_RSVD_2", - CFG_PCIE_CTL_RSVD_2_MASK}, - {"CFG_PCIE_CTL_RRQ_DISABLE", - CFG_PCIE_CTL_RRQ_DISABLE_MASK}, - {"CFG_PCIE_CTL_RELAXED_ORDERING", - CFG_PCIE_CTL_RELAXED_ORDERING_MASK}, -}; - - -static struct regfield_info - cfg_blk_msi_enable_field_info[] = { - {"CFG_BLK_MSI_ENABLE", - CFG_BLK_MSI_ENABLE_MASK}, -}; - - -static struct regfield_info - cfg_axi_user_max_pld_size_field_info[] = { - {"CFG_AXI_USER_MAX_PLD_SIZE_RSVD_1", - CFG_AXI_USER_MAX_PLD_SIZE_RSVD_1_MASK}, - {"CFG_AXI_USER_MAX_PLD_SIZE_ISSUED", - CFG_AXI_USER_MAX_PLD_SIZE_ISSUED_MASK}, - {"CFG_AXI_USER_MAX_PLD_SIZE_RSVD_2", - CFG_AXI_USER_MAX_PLD_SIZE_RSVD_2_MASK}, - {"CFG_AXI_USER_MAX_PLD_SIZE_PROG", - CFG_AXI_USER_MAX_PLD_SIZE_PROG_MASK}, -}; - - -static struct regfield_info - cfg_axi_user_max_read_req_size_field_info[] = { - {"CFG_AXI_USER_MAX_READ_REQ_SIZE_RSVD_1", - CFG_AXI_USER_MAX_READ_REQ_SIZE_RSVD_1_MASK}, - {"CFG_AXI_USER_MAX_READ_REQ_SIZE_USISSUED", - CFG_AXI_USER_MAX_READ_REQ_SIZE_USISSUED_MASK}, - {"CFG_AXI_USER_MAX_READ_REQ_SIZE_RSVD_2", - CFG_AXI_USER_MAX_READ_REQ_SIZE_RSVD_2_MASK}, - {"CFG_AXI_USER_MAX_READ_REQ_SIZE_USPROG", - CFG_AXI_USER_MAX_READ_REQ_SIZE_USPROG_MASK}, -}; - - -static struct regfield_info - cfg_blk_misc_ctl_field_info[] = { - {"CFG_BLK_MISC_CTL_RSVD_1", - CFG_BLK_MISC_CTL_RSVD_1_MASK}, - {"CFG_BLK_MISC_CTL_10B_TAG_EN", - CFG_BLK_MISC_CTL_10B_TAG_EN_MASK}, - {"CFG_BLK_MISC_CTL_RSVD_2", - CFG_BLK_MISC_CTL_RSVD_2_MASK}, - {"CFG_BLK_MISC_CTL_AXI_WBK", - CFG_BLK_MISC_CTL_AXI_WBK_MASK}, - {"CFG_BLK_MISC_CTL_AXI_DSC", - CFG_BLK_MISC_CTL_AXI_DSC_MASK}, - {"CFG_BLK_MISC_CTL_NUM_TAG", - CFG_BLK_MISC_CTL_NUM_TAG_MASK}, - {"CFG_BLK_MISC_CTL_RSVD_3", - CFG_BLK_MISC_CTL_RSVD_3_MASK}, - {"CFG_BLK_MISC_CTL_RQ_METERING_MULTIPLIER", - CFG_BLK_MISC_CTL_RQ_METERING_MULTIPLIER_MASK}, -}; - - -static struct regfield_info - cfg_pl_cred_ctl_field_info[] = { - {"CFG_PL_CRED_CTL_RSVD_1", - CFG_PL_CRED_CTL_RSVD_1_MASK}, - {"CFG_PL_CRED_CTL_SLAVE_CRD_RLS", - CFG_PL_CRED_CTL_SLAVE_CRD_RLS_MASK}, - {"CFG_PL_CRED_CTL_RSVD_2", - CFG_PL_CRED_CTL_RSVD_2_MASK}, - {"CFG_PL_CRED_CTL_MASTER_CRD_RST", - CFG_PL_CRED_CTL_MASTER_CRD_RST_MASK}, -}; - - -static struct regfield_info - cfg_blk_scratch_field_info[] = { - {"CFG_BLK_SCRATCH", - CFG_BLK_SCRATCH_MASK}, -}; - - -static struct regfield_info - cfg_gic_field_info[] = { - {"CFG_GIC_RSVD_1", - CFG_GIC_RSVD_1_MASK}, - {"CFG_GIC_GIC_IRQ", - CFG_GIC_GIC_IRQ_MASK}, -}; - - -static struct regfield_info - ram_sbe_msk_1_a_field_info[] = { - {"RAM_SBE_MSK_1_A", - RAM_SBE_MSK_1_A_MASK}, -}; - - -static struct regfield_info - ram_sbe_sts_1_a_field_info[] = { - {"RAM_SBE_STS_1_A_RSVD", - RAM_SBE_STS_1_A_RSVD_MASK}, - {"RAM_SBE_STS_1_A_PFCH_CTXT_CAM_RAM_1", - RAM_SBE_STS_1_A_PFCH_CTXT_CAM_RAM_1_MASK}, - {"RAM_SBE_STS_1_A_PFCH_CTXT_CAM_RAM_0", - RAM_SBE_STS_1_A_PFCH_CTXT_CAM_RAM_0_MASK}, - {"RAM_SBE_STS_1_A_TAG_EVEN_RAM", - RAM_SBE_STS_1_A_TAG_EVEN_RAM_MASK}, - {"RAM_SBE_STS_1_A_TAG_ODD_RAM", - RAM_SBE_STS_1_A_TAG_ODD_RAM_MASK}, - {"RAM_SBE_STS_1_A_RC_RRQ_EVEN_RAM", - RAM_SBE_STS_1_A_RC_RRQ_EVEN_RAM_MASK}, -}; - - -static struct regfield_info - ram_dbe_msk_1_a_field_info[] = { - {"RAM_DBE_MSK_1_A", - RAM_DBE_MSK_1_A_MASK}, -}; - - -static struct regfield_info - ram_dbe_sts_1_a_field_info[] = { - {"RAM_DBE_STS_1_A_RSVD", - RAM_DBE_STS_1_A_RSVD_MASK}, - {"RAM_DBE_STS_1_A_PFCH_CTXT_CAM_RAM_1", - RAM_DBE_STS_1_A_PFCH_CTXT_CAM_RAM_1_MASK}, - {"RAM_DBE_STS_1_A_PFCH_CTXT_CAM_RAM_0", - RAM_DBE_STS_1_A_PFCH_CTXT_CAM_RAM_0_MASK}, - {"RAM_DBE_STS_1_A_TAG_EVEN_RAM", - RAM_DBE_STS_1_A_TAG_EVEN_RAM_MASK}, - {"RAM_DBE_STS_1_A_TAG_ODD_RAM", - RAM_DBE_STS_1_A_TAG_ODD_RAM_MASK}, - {"RAM_DBE_STS_1_A_RC_RRQ_EVEN_RAM", - RAM_DBE_STS_1_A_RC_RRQ_EVEN_RAM_MASK}, -}; - - -static struct regfield_info - ram_sbe_msk_a_field_info[] = { - {"RAM_SBE_MSK_A", - RAM_SBE_MSK_A_MASK}, -}; - - -static struct regfield_info - ram_sbe_sts_a_field_info[] = { - {"RAM_SBE_STS_A_RC_RRQ_ODD_RAM", - RAM_SBE_STS_A_RC_RRQ_ODD_RAM_MASK}, - {"RAM_SBE_STS_A_PEND_FIFO_RAM", - RAM_SBE_STS_A_PEND_FIFO_RAM_MASK}, - {"RAM_SBE_STS_A_PFCH_LL_RAM", - RAM_SBE_STS_A_PFCH_LL_RAM_MASK}, - {"RAM_SBE_STS_A_WRB_CTXT_RAM", - RAM_SBE_STS_A_WRB_CTXT_RAM_MASK}, - {"RAM_SBE_STS_A_PFCH_CTXT_RAM", - RAM_SBE_STS_A_PFCH_CTXT_RAM_MASK}, - {"RAM_SBE_STS_A_DESC_REQ_FIFO_RAM", - RAM_SBE_STS_A_DESC_REQ_FIFO_RAM_MASK}, - {"RAM_SBE_STS_A_INT_CTXT_RAM", - RAM_SBE_STS_A_INT_CTXT_RAM_MASK}, - {"RAM_SBE_STS_A_WRB_COAL_DATA_RAM", - RAM_SBE_STS_A_WRB_COAL_DATA_RAM_MASK}, - {"RAM_SBE_STS_A_QID_FIFO_RAM", - RAM_SBE_STS_A_QID_FIFO_RAM_MASK}, - {"RAM_SBE_STS_A_TIMER_FIFO_RAM", - RAM_SBE_STS_A_TIMER_FIFO_RAM_MASK}, - {"RAM_SBE_STS_A_MI_TL_SLV_FIFO_RAM", - RAM_SBE_STS_A_MI_TL_SLV_FIFO_RAM_MASK}, - {"RAM_SBE_STS_A_DSC_CPLD", - RAM_SBE_STS_A_DSC_CPLD_MASK}, - {"RAM_SBE_STS_A_DSC_CPLI", - RAM_SBE_STS_A_DSC_CPLI_MASK}, - {"RAM_SBE_STS_A_DSC_SW_CTXT", - RAM_SBE_STS_A_DSC_SW_CTXT_MASK}, - {"RAM_SBE_STS_A_DSC_CRD_RCV", - RAM_SBE_STS_A_DSC_CRD_RCV_MASK}, - {"RAM_SBE_STS_A_DSC_HW_CTXT", - RAM_SBE_STS_A_DSC_HW_CTXT_MASK}, - {"RAM_SBE_STS_A_FUNC_MAP", - RAM_SBE_STS_A_FUNC_MAP_MASK}, - {"RAM_SBE_STS_A_C2H_WR_BRG_DAT", - RAM_SBE_STS_A_C2H_WR_BRG_DAT_MASK}, - {"RAM_SBE_STS_A_C2H_RD_BRG_DAT", - RAM_SBE_STS_A_C2H_RD_BRG_DAT_MASK}, - {"RAM_SBE_STS_A_H2C_WR_BRG_DAT", - RAM_SBE_STS_A_H2C_WR_BRG_DAT_MASK}, - {"RAM_SBE_STS_A_H2C_RD_BRG_DAT", - RAM_SBE_STS_A_H2C_RD_BRG_DAT_MASK}, - {"RAM_SBE_STS_A_MI_C2H3_DAT", - RAM_SBE_STS_A_MI_C2H3_DAT_MASK}, - {"RAM_SBE_STS_A_MI_C2H2_DAT", - RAM_SBE_STS_A_MI_C2H2_DAT_MASK}, - {"RAM_SBE_STS_A_MI_C2H1_DAT", - RAM_SBE_STS_A_MI_C2H1_DAT_MASK}, - {"RAM_SBE_STS_A_MI_C2H0_DAT", - RAM_SBE_STS_A_MI_C2H0_DAT_MASK}, - {"RAM_SBE_STS_A_MI_H2C3_DAT", - RAM_SBE_STS_A_MI_H2C3_DAT_MASK}, - {"RAM_SBE_STS_A_MI_H2C2_DAT", - RAM_SBE_STS_A_MI_H2C2_DAT_MASK}, - {"RAM_SBE_STS_A_MI_H2C1_DAT", - RAM_SBE_STS_A_MI_H2C1_DAT_MASK}, - {"RAM_SBE_STS_A_MI_H2C0_DAT", - RAM_SBE_STS_A_MI_H2C0_DAT_MASK}, -}; - - -static struct regfield_info - ram_dbe_msk_a_field_info[] = { - {"RAM_DBE_MSK_A", - RAM_DBE_MSK_A_MASK}, -}; - - -static struct regfield_info - ram_dbe_sts_a_field_info[] = { - {"RAM_DBE_STS_A_RC_RRQ_ODD_RAM", - RAM_DBE_STS_A_RC_RRQ_ODD_RAM_MASK}, - {"RAM_DBE_STS_A_PEND_FIFO_RAM", - RAM_DBE_STS_A_PEND_FIFO_RAM_MASK}, - {"RAM_DBE_STS_A_PFCH_LL_RAM", - RAM_DBE_STS_A_PFCH_LL_RAM_MASK}, - {"RAM_DBE_STS_A_WRB_CTXT_RAM", - RAM_DBE_STS_A_WRB_CTXT_RAM_MASK}, - {"RAM_DBE_STS_A_PFCH_CTXT_RAM", - RAM_DBE_STS_A_PFCH_CTXT_RAM_MASK}, - {"RAM_DBE_STS_A_DESC_REQ_FIFO_RAM", - RAM_DBE_STS_A_DESC_REQ_FIFO_RAM_MASK}, - {"RAM_DBE_STS_A_INT_CTXT_RAM", - RAM_DBE_STS_A_INT_CTXT_RAM_MASK}, - {"RAM_DBE_STS_A_WRB_COAL_DATA_RAM", - RAM_DBE_STS_A_WRB_COAL_DATA_RAM_MASK}, - {"RAM_DBE_STS_A_QID_FIFO_RAM", - RAM_DBE_STS_A_QID_FIFO_RAM_MASK}, - {"RAM_DBE_STS_A_TIMER_FIFO_RAM", - RAM_DBE_STS_A_TIMER_FIFO_RAM_MASK}, - {"RAM_DBE_STS_A_MI_TL_SLV_FIFO_RAM", - RAM_DBE_STS_A_MI_TL_SLV_FIFO_RAM_MASK}, - {"RAM_DBE_STS_A_DSC_CPLD", - RAM_DBE_STS_A_DSC_CPLD_MASK}, - {"RAM_DBE_STS_A_DSC_CPLI", - RAM_DBE_STS_A_DSC_CPLI_MASK}, - {"RAM_DBE_STS_A_DSC_SW_CTXT", - RAM_DBE_STS_A_DSC_SW_CTXT_MASK}, - {"RAM_DBE_STS_A_DSC_CRD_RCV", - RAM_DBE_STS_A_DSC_CRD_RCV_MASK}, - {"RAM_DBE_STS_A_DSC_HW_CTXT", - RAM_DBE_STS_A_DSC_HW_CTXT_MASK}, - {"RAM_DBE_STS_A_FUNC_MAP", - RAM_DBE_STS_A_FUNC_MAP_MASK}, - {"RAM_DBE_STS_A_C2H_WR_BRG_DAT", - RAM_DBE_STS_A_C2H_WR_BRG_DAT_MASK}, - {"RAM_DBE_STS_A_C2H_RD_BRG_DAT", - RAM_DBE_STS_A_C2H_RD_BRG_DAT_MASK}, - {"RAM_DBE_STS_A_H2C_WR_BRG_DAT", - RAM_DBE_STS_A_H2C_WR_BRG_DAT_MASK}, - {"RAM_DBE_STS_A_H2C_RD_BRG_DAT", - RAM_DBE_STS_A_H2C_RD_BRG_DAT_MASK}, - {"RAM_DBE_STS_A_MI_C2H3_DAT", - RAM_DBE_STS_A_MI_C2H3_DAT_MASK}, - {"RAM_DBE_STS_A_MI_C2H2_DAT", - RAM_DBE_STS_A_MI_C2H2_DAT_MASK}, - {"RAM_DBE_STS_A_MI_C2H1_DAT", - RAM_DBE_STS_A_MI_C2H1_DAT_MASK}, - {"RAM_DBE_STS_A_MI_C2H0_DAT", - RAM_DBE_STS_A_MI_C2H0_DAT_MASK}, - {"RAM_DBE_STS_A_MI_H2C3_DAT", - RAM_DBE_STS_A_MI_H2C3_DAT_MASK}, - {"RAM_DBE_STS_A_MI_H2C2_DAT", - RAM_DBE_STS_A_MI_H2C2_DAT_MASK}, - {"RAM_DBE_STS_A_MI_H2C1_DAT", - RAM_DBE_STS_A_MI_H2C1_DAT_MASK}, - {"RAM_DBE_STS_A_MI_H2C0_DAT", - RAM_DBE_STS_A_MI_H2C0_DAT_MASK}, -}; - - -static struct regfield_info - glbl2_identifier_field_info[] = { - {"GLBL2_IDENTIFIER", - GLBL2_IDENTIFIER_MASK}, - {"GLBL2_IDENTIFIER_VERSION", - GLBL2_IDENTIFIER_VERSION_MASK}, -}; - - -static struct regfield_info - glbl2_channel_inst_field_info[] = { - {"GLBL2_CHANNEL_INST_RSVD_1", - GLBL2_CHANNEL_INST_RSVD_1_MASK}, - {"GLBL2_CHANNEL_INST_C2H_ST", - GLBL2_CHANNEL_INST_C2H_ST_MASK}, - {"GLBL2_CHANNEL_INST_H2C_ST", - GLBL2_CHANNEL_INST_H2C_ST_MASK}, - {"GLBL2_CHANNEL_INST_RSVD_2", - GLBL2_CHANNEL_INST_RSVD_2_MASK}, - {"GLBL2_CHANNEL_INST_C2H_ENG", - GLBL2_CHANNEL_INST_C2H_ENG_MASK}, - {"GLBL2_CHANNEL_INST_RSVD_3", - GLBL2_CHANNEL_INST_RSVD_3_MASK}, - {"GLBL2_CHANNEL_INST_H2C_ENG", - GLBL2_CHANNEL_INST_H2C_ENG_MASK}, -}; - - -static struct regfield_info - glbl2_channel_mdma_field_info[] = { - {"GLBL2_CHANNEL_MDMA_RSVD_1", - GLBL2_CHANNEL_MDMA_RSVD_1_MASK}, - {"GLBL2_CHANNEL_MDMA_C2H_ST", - GLBL2_CHANNEL_MDMA_C2H_ST_MASK}, - {"GLBL2_CHANNEL_MDMA_H2C_ST", - GLBL2_CHANNEL_MDMA_H2C_ST_MASK}, - {"GLBL2_CHANNEL_MDMA_RSVD_2", - GLBL2_CHANNEL_MDMA_RSVD_2_MASK}, - {"GLBL2_CHANNEL_MDMA_C2H_ENG", - GLBL2_CHANNEL_MDMA_C2H_ENG_MASK}, - {"GLBL2_CHANNEL_MDMA_RSVD_3", - GLBL2_CHANNEL_MDMA_RSVD_3_MASK}, - {"GLBL2_CHANNEL_MDMA_H2C_ENG", - GLBL2_CHANNEL_MDMA_H2C_ENG_MASK}, -}; - - -static struct regfield_info - glbl2_channel_strm_field_info[] = { - {"GLBL2_CHANNEL_STRM_RSVD_1", - GLBL2_CHANNEL_STRM_RSVD_1_MASK}, - {"GLBL2_CHANNEL_STRM_C2H_ST", - GLBL2_CHANNEL_STRM_C2H_ST_MASK}, - {"GLBL2_CHANNEL_STRM_H2C_ST", - GLBL2_CHANNEL_STRM_H2C_ST_MASK}, - {"GLBL2_CHANNEL_STRM_RSVD_2", - GLBL2_CHANNEL_STRM_RSVD_2_MASK}, - {"GLBL2_CHANNEL_STRM_C2H_ENG", - GLBL2_CHANNEL_STRM_C2H_ENG_MASK}, - {"GLBL2_CHANNEL_STRM_RSVD_3", - GLBL2_CHANNEL_STRM_RSVD_3_MASK}, - {"GLBL2_CHANNEL_STRM_H2C_ENG", - GLBL2_CHANNEL_STRM_H2C_ENG_MASK}, -}; - - -static struct regfield_info - glbl2_channel_cap_field_info[] = { - {"GLBL2_CHANNEL_CAP_RSVD_1", - GLBL2_CHANNEL_CAP_RSVD_1_MASK}, - {"GLBL2_CHANNEL_CAP_MULTIQ_MAX", - GLBL2_CHANNEL_CAP_MULTIQ_MAX_MASK}, -}; - - -static struct regfield_info - glbl2_channel_pasid_cap_field_info[] = { - {"GLBL2_CHANNEL_PASID_CAP_RSVD_1", - GLBL2_CHANNEL_PASID_CAP_RSVD_1_MASK}, - {"GLBL2_CHANNEL_PASID_CAP_BRIDGEEN", - GLBL2_CHANNEL_PASID_CAP_BRIDGEEN_MASK}, - {"GLBL2_CHANNEL_PASID_CAP_DMAEN", - GLBL2_CHANNEL_PASID_CAP_DMAEN_MASK}, -}; - - -static struct regfield_info - glbl2_system_id_field_info[] = { - {"GLBL2_SYSTEM_ID_RSVD_1", - GLBL2_SYSTEM_ID_RSVD_1_MASK}, - {"GLBL2_SYSTEM_ID", - GLBL2_SYSTEM_ID_MASK}, -}; - - -static struct regfield_info - glbl2_misc_cap_field_info[] = { - {"GLBL2_MISC_CAP", - GLBL2_MISC_CAP_MASK}, -}; - - -static struct regfield_info - glbl2_dbg_pcie_rq0_field_info[] = { - {"GLBL2_PCIE_RQ0_NPH_AVL", - GLBL2_PCIE_RQ0_NPH_AVL_MASK}, - {"GLBL2_PCIE_RQ0_RCB_AVL", - GLBL2_PCIE_RQ0_RCB_AVL_MASK}, - {"GLBL2_PCIE_RQ0_SLV_RD_CREDS", - GLBL2_PCIE_RQ0_SLV_RD_CREDS_MASK}, - {"GLBL2_PCIE_RQ0_TAG_EP", - GLBL2_PCIE_RQ0_TAG_EP_MASK}, -}; - - -static struct regfield_info - glbl2_dbg_pcie_rq1_field_info[] = { - {"GLBL2_PCIE_RQ1_RSVD_1", - GLBL2_PCIE_RQ1_RSVD_1_MASK}, - {"GLBL2_PCIE_RQ1_TAG_FL", - GLBL2_PCIE_RQ1_TAG_FL_MASK}, - {"GLBL2_PCIE_RQ1_WTLP_HEADER_FIFO_FL", - GLBL2_PCIE_RQ1_WTLP_HEADER_FIFO_FL_MASK}, - {"GLBL2_PCIE_RQ1_WTLP_HEADER_FIFO_EP", - GLBL2_PCIE_RQ1_WTLP_HEADER_FIFO_EP_MASK}, - {"GLBL2_PCIE_RQ1_RQ_FIFO_EP", - GLBL2_PCIE_RQ1_RQ_FIFO_EP_MASK}, - {"GLBL2_PCIE_RQ1_RQ_FIFO_FL", - GLBL2_PCIE_RQ1_RQ_FIFO_FL_MASK}, - {"GLBL2_PCIE_RQ1_TLPSM", - GLBL2_PCIE_RQ1_TLPSM_MASK}, - {"GLBL2_PCIE_RQ1_TLPSM512", - GLBL2_PCIE_RQ1_TLPSM512_MASK}, - {"GLBL2_PCIE_RQ1_RREQ_RCB_OK", - GLBL2_PCIE_RQ1_RREQ_RCB_OK_MASK}, - {"GLBL2_PCIE_RQ1_RREQ0_SLV", - GLBL2_PCIE_RQ1_RREQ0_SLV_MASK}, - {"GLBL2_PCIE_RQ1_RREQ0_VLD", - GLBL2_PCIE_RQ1_RREQ0_VLD_MASK}, - {"GLBL2_PCIE_RQ1_RREQ0_RDY", - GLBL2_PCIE_RQ1_RREQ0_RDY_MASK}, - {"GLBL2_PCIE_RQ1_RREQ1_SLV", - GLBL2_PCIE_RQ1_RREQ1_SLV_MASK}, - {"GLBL2_PCIE_RQ1_RREQ1_VLD", - GLBL2_PCIE_RQ1_RREQ1_VLD_MASK}, - {"GLBL2_PCIE_RQ1_RREQ1_RDY", - GLBL2_PCIE_RQ1_RREQ1_RDY_MASK}, - {"GLBL2_PCIE_RQ1_WTLP_REQ", - GLBL2_PCIE_RQ1_WTLP_REQ_MASK}, - {"GLBL2_PCIE_RQ1_WTLP_STRADDLE", - GLBL2_PCIE_RQ1_WTLP_STRADDLE_MASK}, -}; - - -static struct regfield_info - glbl2_dbg_aximm_wr0_field_info[] = { - {"GLBL2_AXIMM_WR0_RSVD_1", - GLBL2_AXIMM_WR0_RSVD_1_MASK}, - {"GLBL2_AXIMM_WR0_WR_REQ", - GLBL2_AXIMM_WR0_WR_REQ_MASK}, - {"GLBL2_AXIMM_WR0_WR_CHN", - GLBL2_AXIMM_WR0_WR_CHN_MASK}, - {"GLBL2_AXIMM_WR0_WTLP_DATA_FIFO_EP", - GLBL2_AXIMM_WR0_WTLP_DATA_FIFO_EP_MASK}, - {"GLBL2_AXIMM_WR0_WPL_FIFO_EP", - GLBL2_AXIMM_WR0_WPL_FIFO_EP_MASK}, - {"GLBL2_AXIMM_WR0_BRSP_CLAIM_CHN", - GLBL2_AXIMM_WR0_BRSP_CLAIM_CHN_MASK}, - {"GLBL2_AXIMM_WR0_WRREQ_CNT", - GLBL2_AXIMM_WR0_WRREQ_CNT_MASK}, - {"GLBL2_AXIMM_WR0_BID", - GLBL2_AXIMM_WR0_BID_MASK}, - {"GLBL2_AXIMM_WR0_BVALID", - GLBL2_AXIMM_WR0_BVALID_MASK}, - {"GLBL2_AXIMM_WR0_BREADY", - GLBL2_AXIMM_WR0_BREADY_MASK}, - {"GLBL2_AXIMM_WR0_WVALID", - GLBL2_AXIMM_WR0_WVALID_MASK}, - {"GLBL2_AXIMM_WR0_WREADY", - GLBL2_AXIMM_WR0_WREADY_MASK}, - {"GLBL2_AXIMM_WR0_AWID", - GLBL2_AXIMM_WR0_AWID_MASK}, - {"GLBL2_AXIMM_WR0_AWVALID", - GLBL2_AXIMM_WR0_AWVALID_MASK}, - {"GLBL2_AXIMM_WR0_AWREADY", - GLBL2_AXIMM_WR0_AWREADY_MASK}, -}; - - -static struct regfield_info - glbl2_dbg_aximm_wr1_field_info[] = { - {"GLBL2_AXIMM_WR1_RSVD_1", - GLBL2_AXIMM_WR1_RSVD_1_MASK}, - {"GLBL2_AXIMM_WR1_BRSP_CNT4", - GLBL2_AXIMM_WR1_BRSP_CNT4_MASK}, - {"GLBL2_AXIMM_WR1_BRSP_CNT3", - GLBL2_AXIMM_WR1_BRSP_CNT3_MASK}, - {"GLBL2_AXIMM_WR1_BRSP_CNT2", - GLBL2_AXIMM_WR1_BRSP_CNT2_MASK}, - {"GLBL2_AXIMM_WR1_BRSP_CNT1", - GLBL2_AXIMM_WR1_BRSP_CNT1_MASK}, - {"GLBL2_AXIMM_WR1_BRSP_CNT0", - GLBL2_AXIMM_WR1_BRSP_CNT0_MASK}, -}; - - -static struct regfield_info - glbl2_dbg_aximm_rd0_field_info[] = { - {"GLBL2_AXIMM_RD0_RSVD_1", - GLBL2_AXIMM_RD0_RSVD_1_MASK}, - {"GLBL2_AXIMM_RD0_PND_CNT", - GLBL2_AXIMM_RD0_PND_CNT_MASK}, - {"GLBL2_AXIMM_RD0_RD_REQ", - GLBL2_AXIMM_RD0_RD_REQ_MASK}, - {"GLBL2_AXIMM_RD0_RD_CHNL", - GLBL2_AXIMM_RD0_RD_CHNL_MASK}, - {"GLBL2_AXIMM_RD0_RRSP_CLAIM_CHNL", - GLBL2_AXIMM_RD0_RRSP_CLAIM_CHNL_MASK}, - {"GLBL2_AXIMM_RD0_RID", - GLBL2_AXIMM_RD0_RID_MASK}, - {"GLBL2_AXIMM_RD0_RVALID", - GLBL2_AXIMM_RD0_RVALID_MASK}, - {"GLBL2_AXIMM_RD0_RREADY", - GLBL2_AXIMM_RD0_RREADY_MASK}, - {"GLBL2_AXIMM_RD0_ARID", - GLBL2_AXIMM_RD0_ARID_MASK}, - {"GLBL2_AXIMM_RD0_ARVALID", - GLBL2_AXIMM_RD0_ARVALID_MASK}, - {"GLBL2_AXIMM_RD0_ARREADY", - GLBL2_AXIMM_RD0_ARREADY_MASK}, -}; - - -static struct regfield_info - glbl2_dbg_aximm_rd1_field_info[] = { - {"GLBL2_AXIMM_RD1_RSVD_1", - GLBL2_AXIMM_RD1_RSVD_1_MASK}, - {"GLBL2_AXIMM_RD1_RRSP_CNT4", - GLBL2_AXIMM_RD1_RRSP_CNT4_MASK}, - {"GLBL2_AXIMM_RD1_RRSP_CNT3", - GLBL2_AXIMM_RD1_RRSP_CNT3_MASK}, - {"GLBL2_AXIMM_RD1_RRSP_CNT2", - GLBL2_AXIMM_RD1_RRSP_CNT2_MASK}, - {"GLBL2_AXIMM_RD1_RRSP_CNT1", - GLBL2_AXIMM_RD1_RRSP_CNT1_MASK}, - {"GLBL2_AXIMM_RD1_RRSP_CNT0", - GLBL2_AXIMM_RD1_RRSP_CNT0_MASK}, -}; - - -static struct regfield_info - glbl2_dbg_fab0_field_info[] = { - {"GLBL2_FAB0_H2C_INB_CONV_IN_VLD", - GLBL2_FAB0_H2C_INB_CONV_IN_VLD_MASK}, - {"GLBL2_FAB0_H2C_INB_CONV_IN_RDY", - GLBL2_FAB0_H2C_INB_CONV_IN_RDY_MASK}, - {"GLBL2_FAB0_H2C_SEG_IN_VLD", - GLBL2_FAB0_H2C_SEG_IN_VLD_MASK}, - {"GLBL2_FAB0_H2C_SEG_IN_RDY", - GLBL2_FAB0_H2C_SEG_IN_RDY_MASK}, - {"GLBL2_FAB0_H2C_SEG_OUT_VLD", - GLBL2_FAB0_H2C_SEG_OUT_VLD_MASK}, - {"GLBL2_FAB0_H2C_SEG_OUT_RDY", - GLBL2_FAB0_H2C_SEG_OUT_RDY_MASK}, - {"GLBL2_FAB0_H2C_MST_CRDT_STAT", - GLBL2_FAB0_H2C_MST_CRDT_STAT_MASK}, - {"GLBL2_FAB0_C2H_SLV_AFIFO_FULL", - GLBL2_FAB0_C2H_SLV_AFIFO_FULL_MASK}, - {"GLBL2_FAB0_C2H_SLV_AFIFO_EMPTY", - GLBL2_FAB0_C2H_SLV_AFIFO_EMPTY_MASK}, - {"GLBL2_FAB0_C2H_DESEG_SEG_VLD", - GLBL2_FAB0_C2H_DESEG_SEG_VLD_MASK}, - {"GLBL2_FAB0_C2H_DESEG_SEG_RDY", - GLBL2_FAB0_C2H_DESEG_SEG_RDY_MASK}, - {"GLBL2_FAB0_C2H_DESEG_OUT_VLD", - GLBL2_FAB0_C2H_DESEG_OUT_VLD_MASK}, - {"GLBL2_FAB0_C2H_DESEG_OUT_RDY", - GLBL2_FAB0_C2H_DESEG_OUT_RDY_MASK}, - {"GLBL2_FAB0_C2H_INB_DECONV_OUT_VLD", - GLBL2_FAB0_C2H_INB_DECONV_OUT_VLD_MASK}, - {"GLBL2_FAB0_C2H_INB_DECONV_OUT_RDY", - GLBL2_FAB0_C2H_INB_DECONV_OUT_RDY_MASK}, - {"GLBL2_FAB0_C2H_DSC_CRDT_AFIFO_FULL", - GLBL2_FAB0_C2H_DSC_CRDT_AFIFO_FULL_MASK}, - {"GLBL2_FAB0_C2H_DSC_CRDT_AFIFO_EMPTY", - GLBL2_FAB0_C2H_DSC_CRDT_AFIFO_EMPTY_MASK}, - {"GLBL2_FAB0_IRQ_IN_AFIFO_FULL", - GLBL2_FAB0_IRQ_IN_AFIFO_FULL_MASK}, - {"GLBL2_FAB0_IRQ_IN_AFIFO_EMPTY", - GLBL2_FAB0_IRQ_IN_AFIFO_EMPTY_MASK}, - {"GLBL2_FAB0_IMM_CRD_AFIFO_EMPTY", - GLBL2_FAB0_IMM_CRD_AFIFO_EMPTY_MASK}, -}; - - -static struct regfield_info - glbl2_dbg_fab1_field_info[] = { - {"GLBL2_FAB1_BYP_OUT_CRDT_STAT", - GLBL2_FAB1_BYP_OUT_CRDT_STAT_MASK}, - {"GLBL2_FAB1_TM_DSC_STS_CRDT_STAT", - GLBL2_FAB1_TM_DSC_STS_CRDT_STAT_MASK}, - {"GLBL2_FAB1_C2H_CMN_AFIFO_FULL", - GLBL2_FAB1_C2H_CMN_AFIFO_FULL_MASK}, - {"GLBL2_FAB1_C2H_CMN_AFIFO_EMPTY", - GLBL2_FAB1_C2H_CMN_AFIFO_EMPTY_MASK}, - {"GLBL2_FAB1_RSVD_1", - GLBL2_FAB1_RSVD_1_MASK}, - {"GLBL2_FAB1_C2H_BYP_IN_AFIFO_FULL", - GLBL2_FAB1_C2H_BYP_IN_AFIFO_FULL_MASK}, - {"GLBL2_FAB1_RSVD_2", - GLBL2_FAB1_RSVD_2_MASK}, - {"GLBL2_FAB1_C2H_BYP_IN_AFIFO_EMPTY", - GLBL2_FAB1_C2H_BYP_IN_AFIFO_EMPTY_MASK}, - {"GLBL2_FAB1_RSVD_3", - GLBL2_FAB1_RSVD_3_MASK}, - {"GLBL2_FAB1_H2C_BYP_IN_AFIFO_FULL", - GLBL2_FAB1_H2C_BYP_IN_AFIFO_FULL_MASK}, - {"GLBL2_FAB1_RSVD_4", - GLBL2_FAB1_RSVD_4_MASK}, - {"GLBL2_FAB1_H2C_BYP_IN_AFIFO_EMPTY", - GLBL2_FAB1_H2C_BYP_IN_AFIFO_EMPTY_MASK}, -}; - - -static struct regfield_info - glbl2_dbg_match_sel_field_info[] = { - {"GLBL2_MATCH_SEL_RSV", - GLBL2_MATCH_SEL_RSV_MASK}, - {"GLBL2_MATCH_SEL_CSR_SEL", - GLBL2_MATCH_SEL_CSR_SEL_MASK}, - {"GLBL2_MATCH_SEL_CSR_EN", - GLBL2_MATCH_SEL_CSR_EN_MASK}, - {"GLBL2_MATCH_SEL_ROTATE1", - GLBL2_MATCH_SEL_ROTATE1_MASK}, - {"GLBL2_MATCH_SEL_ROTATE0", - GLBL2_MATCH_SEL_ROTATE0_MASK}, - {"GLBL2_MATCH_SEL_SEL", - GLBL2_MATCH_SEL_SEL_MASK}, -}; - - -static struct regfield_info - glbl2_dbg_match_msk_field_info[] = { - {"GLBL2_MATCH_MSK", - GLBL2_MATCH_MSK_MASK}, -}; - - -static struct regfield_info - glbl2_dbg_match_pat_field_info[] = { - {"GLBL2_MATCH_PAT_PATTERN", - GLBL2_MATCH_PAT_PATTERN_MASK}, -}; - - -static struct regfield_info - glbl_rng_sz_1_field_info[] = { - {"GLBL_RNG_SZ_1_RSVD_1", - GLBL_RNG_SZ_1_RSVD_1_MASK}, - {"GLBL_RNG_SZ_1_RING_SIZE", - GLBL_RNG_SZ_1_RING_SIZE_MASK}, -}; - - -static struct regfield_info - glbl_rng_sz_2_field_info[] = { - {"GLBL_RNG_SZ_2_RSVD_1", - GLBL_RNG_SZ_2_RSVD_1_MASK}, - {"GLBL_RNG_SZ_2_RING_SIZE", - GLBL_RNG_SZ_2_RING_SIZE_MASK}, -}; - - -static struct regfield_info - glbl_rng_sz_3_field_info[] = { - {"GLBL_RNG_SZ_3_RSVD_1", - GLBL_RNG_SZ_3_RSVD_1_MASK}, - {"GLBL_RNG_SZ_3_RING_SIZE", - GLBL_RNG_SZ_3_RING_SIZE_MASK}, -}; - - -static struct regfield_info - glbl_rng_sz_4_field_info[] = { - {"GLBL_RNG_SZ_4_RSVD_1", - GLBL_RNG_SZ_4_RSVD_1_MASK}, - {"GLBL_RNG_SZ_4_RING_SIZE", - GLBL_RNG_SZ_4_RING_SIZE_MASK}, -}; - - -static struct regfield_info - glbl_rng_sz_5_field_info[] = { - {"GLBL_RNG_SZ_5_RSVD_1", - GLBL_RNG_SZ_5_RSVD_1_MASK}, - {"GLBL_RNG_SZ_5_RING_SIZE", - GLBL_RNG_SZ_5_RING_SIZE_MASK}, -}; - - -static struct regfield_info - glbl_rng_sz_6_field_info[] = { - {"GLBL_RNG_SZ_6_RSVD_1", - GLBL_RNG_SZ_6_RSVD_1_MASK}, - {"GLBL_RNG_SZ_6_RING_SIZE", - GLBL_RNG_SZ_6_RING_SIZE_MASK}, -}; - - -static struct regfield_info - glbl_rng_sz_7_field_info[] = { - {"GLBL_RNG_SZ_7_RSVD_1", - GLBL_RNG_SZ_7_RSVD_1_MASK}, - {"GLBL_RNG_SZ_7_RING_SIZE", - GLBL_RNG_SZ_7_RING_SIZE_MASK}, -}; - - -static struct regfield_info - glbl_rng_sz_8_field_info[] = { - {"GLBL_RNG_SZ_8_RSVD_1", - GLBL_RNG_SZ_8_RSVD_1_MASK}, - {"GLBL_RNG_SZ_8_RING_SIZE", - GLBL_RNG_SZ_8_RING_SIZE_MASK}, -}; - - -static struct regfield_info - glbl_rng_sz_9_field_info[] = { - {"GLBL_RNG_SZ_9_RSVD_1", - GLBL_RNG_SZ_9_RSVD_1_MASK}, - {"GLBL_RNG_SZ_9_RING_SIZE", - GLBL_RNG_SZ_9_RING_SIZE_MASK}, -}; - - -static struct regfield_info - glbl_rng_sz_a_field_info[] = { - {"GLBL_RNG_SZ_A_RSVD_1", - GLBL_RNG_SZ_A_RSVD_1_MASK}, - {"GLBL_RNG_SZ_A_RING_SIZE", - GLBL_RNG_SZ_A_RING_SIZE_MASK}, -}; - - -static struct regfield_info - glbl_rng_sz_b_field_info[] = { - {"GLBL_RNG_SZ_B_RSVD_1", - GLBL_RNG_SZ_B_RSVD_1_MASK}, - {"GLBL_RNG_SZ_B_RING_SIZE", - GLBL_RNG_SZ_B_RING_SIZE_MASK}, -}; - - -static struct regfield_info - glbl_rng_sz_c_field_info[] = { - {"GLBL_RNG_SZ_C_RSVD_1", - GLBL_RNG_SZ_C_RSVD_1_MASK}, - {"GLBL_RNG_SZ_C_RING_SIZE", - GLBL_RNG_SZ_C_RING_SIZE_MASK}, -}; - - -static struct regfield_info - glbl_rng_sz_d_field_info[] = { - {"GLBL_RNG_SZ_D_RSVD_1", - GLBL_RNG_SZ_D_RSVD_1_MASK}, - {"GLBL_RNG_SZ_D_RING_SIZE", - GLBL_RNG_SZ_D_RING_SIZE_MASK}, -}; - - -static struct regfield_info - glbl_rng_sz_e_field_info[] = { - {"GLBL_RNG_SZ_E_RSVD_1", - GLBL_RNG_SZ_E_RSVD_1_MASK}, - {"GLBL_RNG_SZ_E_RING_SIZE", - GLBL_RNG_SZ_E_RING_SIZE_MASK}, -}; - - -static struct regfield_info - glbl_rng_sz_f_field_info[] = { - {"GLBL_RNG_SZ_F_RSVD_1", - GLBL_RNG_SZ_F_RSVD_1_MASK}, - {"GLBL_RNG_SZ_F_RING_SIZE", - GLBL_RNG_SZ_F_RING_SIZE_MASK}, -}; - - -static struct regfield_info - glbl_rng_sz_10_field_info[] = { - {"GLBL_RNG_SZ_10_RSVD_1", - GLBL_RNG_SZ_10_RSVD_1_MASK}, - {"GLBL_RNG_SZ_10_RING_SIZE", - GLBL_RNG_SZ_10_RING_SIZE_MASK}, -}; - - -static struct regfield_info - glbl_err_stat_field_info[] = { - {"GLBL_ERR_STAT_RSVD_1", - GLBL_ERR_STAT_RSVD_1_MASK}, - {"GLBL_ERR_STAT_ERR_FAB", - GLBL_ERR_STAT_ERR_FAB_MASK}, - {"GLBL_ERR_STAT_ERR_H2C_ST", - GLBL_ERR_STAT_ERR_H2C_ST_MASK}, - {"GLBL_ERR_STAT_ERR_BDG", - GLBL_ERR_STAT_ERR_BDG_MASK}, - {"GLBL_ERR_STAT_IND_CTXT_CMD_ERR", - GLBL_ERR_STAT_IND_CTXT_CMD_ERR_MASK}, - {"GLBL_ERR_STAT_ERR_C2H_ST", - GLBL_ERR_STAT_ERR_C2H_ST_MASK}, - {"GLBL_ERR_STAT_ERR_C2H_MM_1", - GLBL_ERR_STAT_ERR_C2H_MM_1_MASK}, - {"GLBL_ERR_STAT_ERR_C2H_MM_0", - GLBL_ERR_STAT_ERR_C2H_MM_0_MASK}, - {"GLBL_ERR_STAT_ERR_H2C_MM_1", - GLBL_ERR_STAT_ERR_H2C_MM_1_MASK}, - {"GLBL_ERR_STAT_ERR_H2C_MM_0", - GLBL_ERR_STAT_ERR_H2C_MM_0_MASK}, - {"GLBL_ERR_STAT_ERR_TRQ", - GLBL_ERR_STAT_ERR_TRQ_MASK}, - {"GLBL_ERR_STAT_ERR_DSC", - GLBL_ERR_STAT_ERR_DSC_MASK}, - {"GLBL_ERR_STAT_ERR_RAM_DBE", - GLBL_ERR_STAT_ERR_RAM_DBE_MASK}, - {"GLBL_ERR_STAT_ERR_RAM_SBE", - GLBL_ERR_STAT_ERR_RAM_SBE_MASK}, -}; - - -static struct regfield_info - glbl_err_mask_field_info[] = { - {"GLBL_ERR", - GLBL_ERR_MASK}, -}; - - -static struct regfield_info - glbl_dsc_cfg_field_info[] = { - {"GLBL_DSC_CFG_RSVD_1", - GLBL_DSC_CFG_RSVD_1_MASK}, - {"GLBL_DSC_CFG_UNC_OVR_COR", - GLBL_DSC_CFG_UNC_OVR_COR_MASK}, - {"GLBL_DSC_CFG_CTXT_FER_DIS", - GLBL_DSC_CFG_CTXT_FER_DIS_MASK}, - {"GLBL_DSC_CFG_RSVD_2", - GLBL_DSC_CFG_RSVD_2_MASK}, - {"GLBL_DSC_CFG_MAXFETCH", - GLBL_DSC_CFG_MAXFETCH_MASK}, - {"GLBL_DSC_CFG_WB_ACC_INT", - GLBL_DSC_CFG_WB_ACC_INT_MASK}, -}; - - -static struct regfield_info - glbl_dsc_err_sts_field_info[] = { - {"GLBL_DSC_ERR_STS_RSVD_1", - GLBL_DSC_ERR_STS_RSVD_1_MASK}, - {"GLBL_DSC_ERR_STS_PORT_ID", - GLBL_DSC_ERR_STS_PORT_ID_MASK}, - {"GLBL_DSC_ERR_STS_SBE", - GLBL_DSC_ERR_STS_SBE_MASK}, - {"GLBL_DSC_ERR_STS_DBE", - GLBL_DSC_ERR_STS_DBE_MASK}, - {"GLBL_DSC_ERR_STS_RQ_CANCEL", - GLBL_DSC_ERR_STS_RQ_CANCEL_MASK}, - {"GLBL_DSC_ERR_STS_DSC", - GLBL_DSC_ERR_STS_DSC_MASK}, - {"GLBL_DSC_ERR_STS_DMA", - GLBL_DSC_ERR_STS_DMA_MASK}, - {"GLBL_DSC_ERR_STS_FLR_CANCEL", - GLBL_DSC_ERR_STS_FLR_CANCEL_MASK}, - {"GLBL_DSC_ERR_STS_RSVD_2", - GLBL_DSC_ERR_STS_RSVD_2_MASK}, - {"GLBL_DSC_ERR_STS_DAT_POISON", - GLBL_DSC_ERR_STS_DAT_POISON_MASK}, - {"GLBL_DSC_ERR_STS_TIMEOUT", - GLBL_DSC_ERR_STS_TIMEOUT_MASK}, - {"GLBL_DSC_ERR_STS_FLR", - GLBL_DSC_ERR_STS_FLR_MASK}, - {"GLBL_DSC_ERR_STS_TAG", - GLBL_DSC_ERR_STS_TAG_MASK}, - {"GLBL_DSC_ERR_STS_ADDR", - GLBL_DSC_ERR_STS_ADDR_MASK}, - {"GLBL_DSC_ERR_STS_PARAM", - GLBL_DSC_ERR_STS_PARAM_MASK}, - {"GLBL_DSC_ERR_STS_BCNT", - GLBL_DSC_ERR_STS_BCNT_MASK}, - {"GLBL_DSC_ERR_STS_UR_CA", - GLBL_DSC_ERR_STS_UR_CA_MASK}, - {"GLBL_DSC_ERR_STS_POISON", - GLBL_DSC_ERR_STS_POISON_MASK}, -}; - - -static struct regfield_info - glbl_dsc_err_msk_field_info[] = { - {"GLBL_DSC_ERR_MSK", - GLBL_DSC_ERR_MSK_MASK}, -}; - - -static struct regfield_info - glbl_dsc_err_log0_field_info[] = { - {"GLBL_DSC_ERR_LOG0_VALID", - GLBL_DSC_ERR_LOG0_VALID_MASK}, - {"GLBL_DSC_ERR_LOG0_SEL", - GLBL_DSC_ERR_LOG0_SEL_MASK}, - {"GLBL_DSC_ERR_LOG0_RSVD_1", - GLBL_DSC_ERR_LOG0_RSVD_1_MASK}, - {"GLBL_DSC_ERR_LOG0_QID", - GLBL_DSC_ERR_LOG0_QID_MASK}, -}; - - -static struct regfield_info - glbl_dsc_err_log1_field_info[] = { - {"GLBL_DSC_ERR_LOG1_RSVD_1", - GLBL_DSC_ERR_LOG1_RSVD_1_MASK}, - {"GLBL_DSC_ERR_LOG1_CIDX", - GLBL_DSC_ERR_LOG1_CIDX_MASK}, - {"GLBL_DSC_ERR_LOG1_RSVD_2", - GLBL_DSC_ERR_LOG1_RSVD_2_MASK}, - {"GLBL_DSC_ERR_LOG1_SUB_TYPE", - GLBL_DSC_ERR_LOG1_SUB_TYPE_MASK}, - {"GLBL_DSC_ERR_LOG1_ERR_TYPE", - GLBL_DSC_ERR_LOG1_ERR_TYPE_MASK}, -}; - - -static struct regfield_info - glbl_trq_err_sts_field_info[] = { - {"GLBL_TRQ_ERR_STS_RSVD_1", - GLBL_TRQ_ERR_STS_RSVD_1_MASK}, - {"GLBL_TRQ_ERR_STS_TCP_QSPC_TIMEOUT", - GLBL_TRQ_ERR_STS_TCP_QSPC_TIMEOUT_MASK}, - {"GLBL_TRQ_ERR_STS_RSVD_2", - GLBL_TRQ_ERR_STS_RSVD_2_MASK}, - {"GLBL_TRQ_ERR_STS_QID_RANGE", - GLBL_TRQ_ERR_STS_QID_RANGE_MASK}, - {"GLBL_TRQ_ERR_STS_QSPC_UNMAPPED", - GLBL_TRQ_ERR_STS_QSPC_UNMAPPED_MASK}, - {"GLBL_TRQ_ERR_STS_TCP_CSR_TIMEOUT", - GLBL_TRQ_ERR_STS_TCP_CSR_TIMEOUT_MASK}, - {"GLBL_TRQ_ERR_STS_RSVD_3", - GLBL_TRQ_ERR_STS_RSVD_3_MASK}, - {"GLBL_TRQ_ERR_STS_VF_ACCESS_ERR", - GLBL_TRQ_ERR_STS_VF_ACCESS_ERR_MASK}, - {"GLBL_TRQ_ERR_STS_CSR_UNMAPPED", - GLBL_TRQ_ERR_STS_CSR_UNMAPPED_MASK}, -}; - - -static struct regfield_info - glbl_trq_err_msk_field_info[] = { - {"GLBL_TRQ_ERR_MSK", - GLBL_TRQ_ERR_MSK_MASK}, -}; - - -static struct regfield_info - glbl_trq_err_log_field_info[] = { - {"GLBL_TRQ_ERR_LOG_SRC", - GLBL_TRQ_ERR_LOG_SRC_MASK}, - {"GLBL_TRQ_ERR_LOG_TARGET", - GLBL_TRQ_ERR_LOG_TARGET_MASK}, - {"GLBL_TRQ_ERR_LOG_FUNC", - GLBL_TRQ_ERR_LOG_FUNC_MASK}, - {"GLBL_TRQ_ERR_LOG_ADDRESS", - GLBL_TRQ_ERR_LOG_ADDRESS_MASK}, -}; - - -static struct regfield_info - glbl_dsc_dbg_dat0_field_info[] = { - {"GLBL_DSC_DAT0_RSVD_1", - GLBL_DSC_DAT0_RSVD_1_MASK}, - {"GLBL_DSC_DAT0_CTXT_ARB_DIR", - GLBL_DSC_DAT0_CTXT_ARB_DIR_MASK}, - {"GLBL_DSC_DAT0_CTXT_ARB_QID", - GLBL_DSC_DAT0_CTXT_ARB_QID_MASK}, - {"GLBL_DSC_DAT0_CTXT_ARB_REQ", - GLBL_DSC_DAT0_CTXT_ARB_REQ_MASK}, - {"GLBL_DSC_DAT0_IRQ_FIFO_FL", - GLBL_DSC_DAT0_IRQ_FIFO_FL_MASK}, - {"GLBL_DSC_DAT0_TMSTALL", - GLBL_DSC_DAT0_TMSTALL_MASK}, - {"GLBL_DSC_DAT0_RRQ_STALL", - GLBL_DSC_DAT0_RRQ_STALL_MASK}, - {"GLBL_DSC_DAT0_RCP_FIFO_SPC_STALL", - GLBL_DSC_DAT0_RCP_FIFO_SPC_STALL_MASK}, - {"GLBL_DSC_DAT0_RRQ_FIFO_SPC_STALL", - GLBL_DSC_DAT0_RRQ_FIFO_SPC_STALL_MASK}, - {"GLBL_DSC_DAT0_FAB_MRKR_RSP_STALL", - GLBL_DSC_DAT0_FAB_MRKR_RSP_STALL_MASK}, - {"GLBL_DSC_DAT0_DSC_OUT_STALL", - GLBL_DSC_DAT0_DSC_OUT_STALL_MASK}, -}; - - -static struct regfield_info - glbl_dsc_dbg_dat1_field_info[] = { - {"GLBL_DSC_DAT1_RSVD_1", - GLBL_DSC_DAT1_RSVD_1_MASK}, - {"GLBL_DSC_DAT1_EVT_SPC_C2H", - GLBL_DSC_DAT1_EVT_SPC_C2H_MASK}, - {"GLBL_DSC_DAT1_EVT_SP_H2C", - GLBL_DSC_DAT1_EVT_SP_H2C_MASK}, - {"GLBL_DSC_DAT1_DSC_SPC_C2H", - GLBL_DSC_DAT1_DSC_SPC_C2H_MASK}, - {"GLBL_DSC_DAT1_DSC_SPC_H2C", - GLBL_DSC_DAT1_DSC_SPC_H2C_MASK}, -}; - - -static struct regfield_info - glbl_dsc_dbg_ctl_field_info[] = { - {"GLBL_DSC_CTL_RSVD_1", - GLBL_DSC_CTL_RSVD_1_MASK}, - {"GLBL_DSC_CTL_SELECT", - GLBL_DSC_CTL_SELECT_MASK}, -}; - - -static struct regfield_info - glbl_dsc_err_log2_field_info[] = { - {"GLBL_DSC_ERR_LOG2_OLD_PIDX", - GLBL_DSC_ERR_LOG2_OLD_PIDX_MASK}, - {"GLBL_DSC_ERR_LOG2_NEW_PIDX", - GLBL_DSC_ERR_LOG2_NEW_PIDX_MASK}, -}; - - -static struct regfield_info - glbl_glbl_interrupt_cfg_field_info[] = { - {"GLBL_GLBL_INTERRUPT_CFG_RSVD_1", - GLBL_GLBL_INTERRUPT_CFG_RSVD_1_MASK}, - {"GLBL_GLBL_INTERRUPT_CFG_LGCY_INTR_PENDING", - GLBL_GLBL_INTERRUPT_CFG_LGCY_INTR_PENDING_MASK}, - {"GLBL_GLBL_INTERRUPT_CFG_EN_LGCY_INTR", - GLBL_GLBL_INTERRUPT_CFG_EN_LGCY_INTR_MASK}, -}; - - -static struct regfield_info - glbl_vch_host_profile_field_info[] = { - {"GLBL_VCH_HOST_PROFILE_RSVD_1", - GLBL_VCH_HOST_PROFILE_RSVD_1_MASK}, - {"GLBL_VCH_HOST_PROFILE_2C_MM", - GLBL_VCH_HOST_PROFILE_2C_MM_MASK}, - {"GLBL_VCH_HOST_PROFILE_2C_ST", - GLBL_VCH_HOST_PROFILE_2C_ST_MASK}, - {"GLBL_VCH_HOST_PROFILE_VCH_DSC", - GLBL_VCH_HOST_PROFILE_VCH_DSC_MASK}, - {"GLBL_VCH_HOST_PROFILE_VCH_INT_MSG", - GLBL_VCH_HOST_PROFILE_VCH_INT_MSG_MASK}, - {"GLBL_VCH_HOST_PROFILE_VCH_INT_AGGR", - GLBL_VCH_HOST_PROFILE_VCH_INT_AGGR_MASK}, - {"GLBL_VCH_HOST_PROFILE_VCH_CMPT", - GLBL_VCH_HOST_PROFILE_VCH_CMPT_MASK}, - {"GLBL_VCH_HOST_PROFILE_VCH_C2H_PLD", - GLBL_VCH_HOST_PROFILE_VCH_C2H_PLD_MASK}, -}; - - -static struct regfield_info - glbl_bridge_host_profile_field_info[] = { - {"GLBL_BRIDGE_HOST_PROFILE_RSVD_1", - GLBL_BRIDGE_HOST_PROFILE_RSVD_1_MASK}, - {"GLBL_BRIDGE_HOST_PROFILE_BDGID", - GLBL_BRIDGE_HOST_PROFILE_BDGID_MASK}, -}; - - -static struct regfield_info - aximm_irq_dest_addr_field_info[] = { - {"AXIMM_IRQ_DEST_ADDR_ADDR", - AXIMM_IRQ_DEST_ADDR_ADDR_MASK}, -}; - - -static struct regfield_info - fab_err_log_field_info[] = { - {"FAB_ERR_LOG_RSVD_1", - FAB_ERR_LOG_RSVD_1_MASK}, - {"FAB_ERR_LOG_SRC", - FAB_ERR_LOG_SRC_MASK}, -}; - - -static struct regfield_info - ind_ctxt_data_field_info[] = { - {"IND_CTXT_DATA_DATA", - IND_CTXT_DATA_DATA_MASK}, -}; - - -static struct regfield_info - ind_ctxt_mask_field_info[] = { - {"IND_CTXT", - IND_CTXT_MASK}, -}; - - -static struct regfield_info - ind_ctxt_cmd_field_info[] = { - {"IND_CTXT_CMD_RSVD_1", - IND_CTXT_CMD_RSVD_1_MASK}, - {"IND_CTXT_CMD_QID", - IND_CTXT_CMD_QID_MASK}, - {"IND_CTXT_CMD_OP", - IND_CTXT_CMD_OP_MASK}, - {"IND_CTXT_CMD_SEL", - IND_CTXT_CMD_SEL_MASK}, - {"IND_CTXT_CMD_BUSY", - IND_CTXT_CMD_BUSY_MASK}, -}; - - -static struct regfield_info - c2h_timer_cnt_field_info[] = { - {"C2H_TIMER_CNT_RSVD_1", - C2H_TIMER_CNT_RSVD_1_MASK}, - {"C2H_TIMER_CNT", - C2H_TIMER_CNT_MASK}, -}; - - -static struct regfield_info - c2h_cnt_th_field_info[] = { - {"C2H_CNT_TH_RSVD_1", - C2H_CNT_TH_RSVD_1_MASK}, - {"C2H_CNT_TH_THESHOLD_CNT", - C2H_CNT_TH_THESHOLD_CNT_MASK}, -}; - - -static struct regfield_info - c2h_stat_s_axis_c2h_accepted_field_info[] = { - {"C2H_STAT_S_AXIS_C2H_ACCEPTED_RSVD_1", - C2H_STAT_S_AXIS_C2H_ACCEPTED_RSVD_1_MASK}, - {"C2H_STAT_S_AXIS_C2H_ACCEPTED", - C2H_STAT_S_AXIS_C2H_ACCEPTED_MASK}, -}; - - -static struct regfield_info - c2h_stat_s_axis_wrb_accepted_field_info[] = { - {"C2H_STAT_S_AXIS_WRB_ACCEPTED_RSVD_1", - C2H_STAT_S_AXIS_WRB_ACCEPTED_RSVD_1_MASK}, - {"C2H_STAT_S_AXIS_WRB_ACCEPTED", - C2H_STAT_S_AXIS_WRB_ACCEPTED_MASK}, -}; - - -static struct regfield_info - c2h_stat_desc_rsp_pkt_accepted_field_info[] = { - {"C2H_STAT_DESC_RSP_PKT_ACCEPTED_RSVD_1", - C2H_STAT_DESC_RSP_PKT_ACCEPTED_RSVD_1_MASK}, - {"C2H_STAT_DESC_RSP_PKT_ACCEPTED_D", - C2H_STAT_DESC_RSP_PKT_ACCEPTED_D_MASK}, -}; - - -static struct regfield_info - c2h_stat_axis_pkg_cmp_field_info[] = { - {"C2H_STAT_AXIS_PKG_CMP_RSVD_1", - C2H_STAT_AXIS_PKG_CMP_RSVD_1_MASK}, - {"C2H_STAT_AXIS_PKG_CMP", - C2H_STAT_AXIS_PKG_CMP_MASK}, -}; - - -static struct regfield_info - c2h_stat_desc_rsp_accepted_field_info[] = { - {"C2H_STAT_DESC_RSP_ACCEPTED_RSVD_1", - C2H_STAT_DESC_RSP_ACCEPTED_RSVD_1_MASK}, - {"C2H_STAT_DESC_RSP_ACCEPTED_D", - C2H_STAT_DESC_RSP_ACCEPTED_D_MASK}, -}; - - -static struct regfield_info - c2h_stat_desc_rsp_cmp_field_info[] = { - {"C2H_STAT_DESC_RSP_CMP_RSVD_1", - C2H_STAT_DESC_RSP_CMP_RSVD_1_MASK}, - {"C2H_STAT_DESC_RSP_CMP_D", - C2H_STAT_DESC_RSP_CMP_D_MASK}, -}; - - -static struct regfield_info - c2h_stat_wrq_out_field_info[] = { - {"C2H_STAT_WRQ_OUT_RSVD_1", - C2H_STAT_WRQ_OUT_RSVD_1_MASK}, - {"C2H_STAT_WRQ_OUT", - C2H_STAT_WRQ_OUT_MASK}, -}; - - -static struct regfield_info - c2h_stat_wpl_ren_accepted_field_info[] = { - {"C2H_STAT_WPL_REN_ACCEPTED_RSVD_1", - C2H_STAT_WPL_REN_ACCEPTED_RSVD_1_MASK}, - {"C2H_STAT_WPL_REN_ACCEPTED", - C2H_STAT_WPL_REN_ACCEPTED_MASK}, -}; - - -static struct regfield_info - c2h_stat_total_wrq_len_field_info[] = { - {"C2H_STAT_TOTAL_WRQ_LEN_RSVD_1", - C2H_STAT_TOTAL_WRQ_LEN_RSVD_1_MASK}, - {"C2H_STAT_TOTAL_WRQ_LEN", - C2H_STAT_TOTAL_WRQ_LEN_MASK}, -}; - - -static struct regfield_info - c2h_stat_total_wpl_len_field_info[] = { - {"C2H_STAT_TOTAL_WPL_LEN_RSVD_1", - C2H_STAT_TOTAL_WPL_LEN_RSVD_1_MASK}, - {"C2H_STAT_TOTAL_WPL_LEN", - C2H_STAT_TOTAL_WPL_LEN_MASK}, -}; - - -static struct regfield_info - c2h_buf_sz_field_info[] = { - {"C2H_BUF_SZ_IZE", - C2H_BUF_SZ_IZE_MASK}, -}; - - -static struct regfield_info - c2h_err_stat_field_info[] = { - {"C2H_ERR_STAT_RSVD_1", - C2H_ERR_STAT_RSVD_1_MASK}, - {"C2H_ERR_STAT_WRB_PORT_ID_ERR", - C2H_ERR_STAT_WRB_PORT_ID_ERR_MASK}, - {"C2H_ERR_STAT_HDR_PAR_ERR", - C2H_ERR_STAT_HDR_PAR_ERR_MASK}, - {"C2H_ERR_STAT_HDR_ECC_COR_ERR", - C2H_ERR_STAT_HDR_ECC_COR_ERR_MASK}, - {"C2H_ERR_STAT_HDR_ECC_UNC_ERR", - C2H_ERR_STAT_HDR_ECC_UNC_ERR_MASK}, - {"C2H_ERR_STAT_AVL_RING_DSC_ERR", - C2H_ERR_STAT_AVL_RING_DSC_ERR_MASK}, - {"C2H_ERR_STAT_WRB_PRTY_ERR", - C2H_ERR_STAT_WRB_PRTY_ERR_MASK}, - {"C2H_ERR_STAT_WRB_CIDX_ERR", - C2H_ERR_STAT_WRB_CIDX_ERR_MASK}, - {"C2H_ERR_STAT_WRB_QFULL_ERR", - C2H_ERR_STAT_WRB_QFULL_ERR_MASK}, - {"C2H_ERR_STAT_WRB_INV_Q_ERR", - C2H_ERR_STAT_WRB_INV_Q_ERR_MASK}, - {"C2H_ERR_STAT_RSVD_2", - C2H_ERR_STAT_RSVD_2_MASK}, - {"C2H_ERR_STAT_PORT_ID_CTXT_MISMATCH", - C2H_ERR_STAT_PORT_ID_CTXT_MISMATCH_MASK}, - {"C2H_ERR_STAT_ERR_DESC_CNT", - C2H_ERR_STAT_ERR_DESC_CNT_MASK}, - {"C2H_ERR_STAT_RSVD_3", - C2H_ERR_STAT_RSVD_3_MASK}, - {"C2H_ERR_STAT_MSI_INT_FAIL", - C2H_ERR_STAT_MSI_INT_FAIL_MASK}, - {"C2H_ERR_STAT_ENG_WPL_DATA_PAR_ERR", - C2H_ERR_STAT_ENG_WPL_DATA_PAR_ERR_MASK}, - {"C2H_ERR_STAT_RSVD_4", - C2H_ERR_STAT_RSVD_4_MASK}, - {"C2H_ERR_STAT_DESC_RSP_ERR", - C2H_ERR_STAT_DESC_RSP_ERR_MASK}, - {"C2H_ERR_STAT_QID_MISMATCH", - C2H_ERR_STAT_QID_MISMATCH_MASK}, - {"C2H_ERR_STAT_SH_CMPT_DSC_ERR", - C2H_ERR_STAT_SH_CMPT_DSC_ERR_MASK}, - {"C2H_ERR_STAT_LEN_MISMATCH", - C2H_ERR_STAT_LEN_MISMATCH_MASK}, - {"C2H_ERR_STAT_MTY_MISMATCH", - C2H_ERR_STAT_MTY_MISMATCH_MASK}, -}; - - -static struct regfield_info - c2h_err_mask_field_info[] = { - {"C2H_ERR_EN", - C2H_ERR_EN_MASK}, -}; - - -static struct regfield_info - c2h_fatal_err_stat_field_info[] = { - {"C2H_FATAL_ERR_STAT_RSVD_1", - C2H_FATAL_ERR_STAT_RSVD_1_MASK}, - {"C2H_FATAL_ERR_STAT_HDR_ECC_UNC_ERR", - C2H_FATAL_ERR_STAT_HDR_ECC_UNC_ERR_MASK}, - {"C2H_FATAL_ERR_STAT_AVL_RING_FIFO_RAM_RDBE", - C2H_FATAL_ERR_STAT_AVL_RING_FIFO_RAM_RDBE_MASK}, - {"C2H_FATAL_ERR_STAT_WPL_DATA_PAR_ERR", - C2H_FATAL_ERR_STAT_WPL_DATA_PAR_ERR_MASK}, - {"C2H_FATAL_ERR_STAT_PLD_FIFO_RAM_RDBE", - C2H_FATAL_ERR_STAT_PLD_FIFO_RAM_RDBE_MASK}, - {"C2H_FATAL_ERR_STAT_QID_FIFO_RAM_RDBE", - C2H_FATAL_ERR_STAT_QID_FIFO_RAM_RDBE_MASK}, - {"C2H_FATAL_ERR_STAT_CMPT_FIFO_RAM_RDBE", - C2H_FATAL_ERR_STAT_CMPT_FIFO_RAM_RDBE_MASK}, - {"C2H_FATAL_ERR_STAT_WRB_COAL_DATA_RAM_RDBE", - C2H_FATAL_ERR_STAT_WRB_COAL_DATA_RAM_RDBE_MASK}, - {"C2H_FATAL_ERR_STAT_RESERVED2", - C2H_FATAL_ERR_STAT_RESERVED2_MASK}, - {"C2H_FATAL_ERR_STAT_INT_CTXT_RAM_RDBE", - C2H_FATAL_ERR_STAT_INT_CTXT_RAM_RDBE_MASK}, - {"C2H_FATAL_ERR_STAT_DESC_REQ_FIFO_RAM_RDBE", - C2H_FATAL_ERR_STAT_DESC_REQ_FIFO_RAM_RDBE_MASK}, - {"C2H_FATAL_ERR_STAT_PFCH_CTXT_RAM_RDBE", - C2H_FATAL_ERR_STAT_PFCH_CTXT_RAM_RDBE_MASK}, - {"C2H_FATAL_ERR_STAT_WRB_CTXT_RAM_RDBE", - C2H_FATAL_ERR_STAT_WRB_CTXT_RAM_RDBE_MASK}, - {"C2H_FATAL_ERR_STAT_PFCH_LL_RAM_RDBE", - C2H_FATAL_ERR_STAT_PFCH_LL_RAM_RDBE_MASK}, - {"C2H_FATAL_ERR_STAT_TIMER_FIFO_RAM_RDBE", - C2H_FATAL_ERR_STAT_TIMER_FIFO_RAM_RDBE_MASK}, - {"C2H_FATAL_ERR_STAT_QID_MISMATCH", - C2H_FATAL_ERR_STAT_QID_MISMATCH_MASK}, - {"C2H_FATAL_ERR_STAT_RESERVED1", - C2H_FATAL_ERR_STAT_RESERVED1_MASK}, - {"C2H_FATAL_ERR_STAT_LEN_MISMATCH", - C2H_FATAL_ERR_STAT_LEN_MISMATCH_MASK}, - {"C2H_FATAL_ERR_STAT_MTY_MISMATCH", - C2H_FATAL_ERR_STAT_MTY_MISMATCH_MASK}, -}; - - -static struct regfield_info - c2h_fatal_err_mask_field_info[] = { - {"C2H_FATAL_ERR_C2HEN", - C2H_FATAL_ERR_C2HEN_MASK}, -}; - - -static struct regfield_info - c2h_fatal_err_enable_field_info[] = { - {"C2H_FATAL_ERR_ENABLE_RSVD_1", - C2H_FATAL_ERR_ENABLE_RSVD_1_MASK}, - {"C2H_FATAL_ERR_ENABLE_WPL_PAR_INV", - C2H_FATAL_ERR_ENABLE_WPL_PAR_INV_MASK}, - {"C2H_FATAL_ERR_ENABLE_WRQ_DIS", - C2H_FATAL_ERR_ENABLE_WRQ_DIS_MASK}, -}; - - -static struct regfield_info - glbl_err_int_field_info[] = { - {"GLBL_ERR_INT_RSVD_1", - GLBL_ERR_INT_RSVD_1_MASK}, - {"GLBL_ERR_INT_HOST_ID", - GLBL_ERR_INT_HOST_ID_MASK}, - {"GLBL_ERR_INT_DIS_INTR_ON_VF", - GLBL_ERR_INT_DIS_INTR_ON_VF_MASK}, - {"GLBL_ERR_INT_ARM", - GLBL_ERR_INT_ARM_MASK}, - {"GLBL_ERR_INT_EN_COAL", - GLBL_ERR_INT_EN_COAL_MASK}, - {"GLBL_ERR_INT_VEC", - GLBL_ERR_INT_VEC_MASK}, - {"GLBL_ERR_INT_FUNC", - GLBL_ERR_INT_FUNC_MASK}, -}; - - -static struct regfield_info - c2h_pfch_cfg_field_info[] = { - {"C2H_PFCH_CFG_EVTFL_TH", - C2H_PFCH_CFG_EVTFL_TH_MASK}, - {"C2H_PFCH_CFG_FL_TH", - C2H_PFCH_CFG_FL_TH_MASK}, -}; - - -static struct regfield_info - c2h_pfch_cfg_1_field_info[] = { - {"C2H_PFCH_CFG_1_EVT_QCNT_TH", - C2H_PFCH_CFG_1_EVT_QCNT_TH_MASK}, - {"C2H_PFCH_CFG_1_QCNT", - C2H_PFCH_CFG_1_QCNT_MASK}, -}; - - -static struct regfield_info - c2h_pfch_cfg_2_field_info[] = { - {"C2H_PFCH_CFG_2_FENCE", - C2H_PFCH_CFG_2_FENCE_MASK}, - {"C2H_PFCH_CFG_2_RSVD", - C2H_PFCH_CFG_2_RSVD_MASK}, - {"C2H_PFCH_CFG_2_VAR_DESC_NO_DROP", - C2H_PFCH_CFG_2_VAR_DESC_NO_DROP_MASK}, - {"C2H_PFCH_CFG_2_LL_SZ_TH", - C2H_PFCH_CFG_2_LL_SZ_TH_MASK}, - {"C2H_PFCH_CFG_2_VAR_DESC_NUM", - C2H_PFCH_CFG_2_VAR_DESC_NUM_MASK}, - {"C2H_PFCH_CFG_2_NUM", - C2H_PFCH_CFG_2_NUM_MASK}, -}; - - -static struct regfield_info - c2h_int_timer_tick_field_info[] = { - {"C2H_INT_TIMER_TICK", - C2H_INT_TIMER_TICK_MASK}, -}; - - -static struct regfield_info - c2h_stat_desc_rsp_drop_accepted_field_info[] = { - {"C2H_STAT_DESC_RSP_DROP_ACCEPTED_RSVD_1", - C2H_STAT_DESC_RSP_DROP_ACCEPTED_RSVD_1_MASK}, - {"C2H_STAT_DESC_RSP_DROP_ACCEPTED_D", - C2H_STAT_DESC_RSP_DROP_ACCEPTED_D_MASK}, -}; - - -static struct regfield_info - c2h_stat_desc_rsp_err_accepted_field_info[] = { - {"C2H_STAT_DESC_RSP_ERR_ACCEPTED_RSVD_1", - C2H_STAT_DESC_RSP_ERR_ACCEPTED_RSVD_1_MASK}, - {"C2H_STAT_DESC_RSP_ERR_ACCEPTED_D", - C2H_STAT_DESC_RSP_ERR_ACCEPTED_D_MASK}, -}; - - -static struct regfield_info - c2h_stat_desc_req_field_info[] = { - {"C2H_STAT_DESC_REQ_RSVD_1", - C2H_STAT_DESC_REQ_RSVD_1_MASK}, - {"C2H_STAT_DESC_REQ", - C2H_STAT_DESC_REQ_MASK}, -}; - - -static struct regfield_info - c2h_stat_dbg_dma_eng_0_field_info[] = { - {"C2H_STAT_DMA_ENG_0_S_AXIS_C2H_TVALID", - C2H_STAT_DMA_ENG_0_S_AXIS_C2H_TVALID_MASK}, - {"C2H_STAT_DMA_ENG_0_S_AXIS_C2H_TREADY", - C2H_STAT_DMA_ENG_0_S_AXIS_C2H_TREADY_MASK}, - {"C2H_STAT_DMA_ENG_0_S_AXIS_WRB_TVALID", - C2H_STAT_DMA_ENG_0_S_AXIS_WRB_TVALID_MASK}, - {"C2H_STAT_DMA_ENG_0_S_AXIS_WRB_TREADY", - C2H_STAT_DMA_ENG_0_S_AXIS_WRB_TREADY_MASK}, - {"C2H_STAT_DMA_ENG_0_PLD_FIFO_IN_RDY", - C2H_STAT_DMA_ENG_0_PLD_FIFO_IN_RDY_MASK}, - {"C2H_STAT_DMA_ENG_0_QID_FIFO_IN_RDY", - C2H_STAT_DMA_ENG_0_QID_FIFO_IN_RDY_MASK}, - {"C2H_STAT_DMA_ENG_0_ARB_FIFO_OUT_VLD", - C2H_STAT_DMA_ENG_0_ARB_FIFO_OUT_VLD_MASK}, - {"C2H_STAT_DMA_ENG_0_ARB_FIFO_OUT_QID", - C2H_STAT_DMA_ENG_0_ARB_FIFO_OUT_QID_MASK}, - {"C2H_STAT_DMA_ENG_0_WRB_FIFO_IN_RDY", - C2H_STAT_DMA_ENG_0_WRB_FIFO_IN_RDY_MASK}, - {"C2H_STAT_DMA_ENG_0_WRB_FIFO_OUT_CNT", - C2H_STAT_DMA_ENG_0_WRB_FIFO_OUT_CNT_MASK}, - {"C2H_STAT_DMA_ENG_0_WRB_SM_CS", - C2H_STAT_DMA_ENG_0_WRB_SM_CS_MASK}, - {"C2H_STAT_DMA_ENG_0_MAIN_SM_CS", - C2H_STAT_DMA_ENG_0_MAIN_SM_CS_MASK}, -}; - - -static struct regfield_info - c2h_stat_dbg_dma_eng_1_field_info[] = { - {"C2H_STAT_DMA_ENG_1_RSVD_1", - C2H_STAT_DMA_ENG_1_RSVD_1_MASK}, - {"C2H_STAT_DMA_ENG_1_QID_FIFO_OUT_CNT", - C2H_STAT_DMA_ENG_1_QID_FIFO_OUT_CNT_MASK}, - {"C2H_STAT_DMA_ENG_1_PLD_FIFO_OUT_CNT", - C2H_STAT_DMA_ENG_1_PLD_FIFO_OUT_CNT_MASK}, - {"C2H_STAT_DMA_ENG_1_PLD_ST_FIFO_CNT", - C2H_STAT_DMA_ENG_1_PLD_ST_FIFO_CNT_MASK}, -}; - - -static struct regfield_info - c2h_stat_dbg_dma_eng_2_field_info[] = { - {"C2H_STAT_DMA_ENG_2_RSVD_1", - C2H_STAT_DMA_ENG_2_RSVD_1_MASK}, - {"C2H_STAT_DMA_ENG_2_QID_FIFO_OUT_CNT", - C2H_STAT_DMA_ENG_2_QID_FIFO_OUT_CNT_MASK}, - {"C2H_STAT_DMA_ENG_2_PLD_FIFO_OUT_CNT", - C2H_STAT_DMA_ENG_2_PLD_FIFO_OUT_CNT_MASK}, - {"C2H_STAT_DMA_ENG_2_PLD_ST_FIFO_CNT", - C2H_STAT_DMA_ENG_2_PLD_ST_FIFO_CNT_MASK}, -}; - - -static struct regfield_info - c2h_stat_dbg_dma_eng_3_field_info[] = { - {"C2H_STAT_DMA_ENG_3_RSVD_1", - C2H_STAT_DMA_ENG_3_RSVD_1_MASK}, - {"C2H_STAT_DMA_ENG_3_WRQ_FIFO_OUT_CNT", - C2H_STAT_DMA_ENG_3_WRQ_FIFO_OUT_CNT_MASK}, - {"C2H_STAT_DMA_ENG_3_QID_FIFO_OUT_VLD", - C2H_STAT_DMA_ENG_3_QID_FIFO_OUT_VLD_MASK}, - {"C2H_STAT_DMA_ENG_3_PLD_FIFO_OUT_VLD", - C2H_STAT_DMA_ENG_3_PLD_FIFO_OUT_VLD_MASK}, - {"C2H_STAT_DMA_ENG_3_PLD_ST_FIFO_OUT_VLD", - C2H_STAT_DMA_ENG_3_PLD_ST_FIFO_OUT_VLD_MASK}, - {"C2H_STAT_DMA_ENG_3_PLD_ST_FIFO_OUT_DATA_EOP", - C2H_STAT_DMA_ENG_3_PLD_ST_FIFO_OUT_DATA_EOP_MASK}, - {"C2H_STAT_DMA_ENG_3_PLD_ST_FIFO_OUT_DATA_AVL_IDX_ENABLE", - C2H_STAT_DMA_ENG_3_PLD_ST_FIFO_OUT_DATA_AVL_IDX_ENABLE_MASK}, - {"C2H_STAT_DMA_ENG_3_PLD_ST_FIFO_OUT_DATA_DROP", - C2H_STAT_DMA_ENG_3_PLD_ST_FIFO_OUT_DATA_DROP_MASK}, - {"C2H_STAT_DMA_ENG_3_PLD_ST_FIFO_OUT_DATA_ERR", - C2H_STAT_DMA_ENG_3_PLD_ST_FIFO_OUT_DATA_ERR_MASK}, - {"C2H_STAT_DMA_ENG_3_DESC_CNT_FIFO_IN_RDY", - C2H_STAT_DMA_ENG_3_DESC_CNT_FIFO_IN_RDY_MASK}, - {"C2H_STAT_DMA_ENG_3_DESC_RSP_FIFO_IN_RDY", - C2H_STAT_DMA_ENG_3_DESC_RSP_FIFO_IN_RDY_MASK}, - {"C2H_STAT_DMA_ENG_3_PLD_PKT_ID_LARGER_0", - C2H_STAT_DMA_ENG_3_PLD_PKT_ID_LARGER_0_MASK}, - {"C2H_STAT_DMA_ENG_3_WRQ_VLD", - C2H_STAT_DMA_ENG_3_WRQ_VLD_MASK}, - {"C2H_STAT_DMA_ENG_3_WRQ_RDY", - C2H_STAT_DMA_ENG_3_WRQ_RDY_MASK}, - {"C2H_STAT_DMA_ENG_3_WRQ_FIFO_OUT_RDY", - C2H_STAT_DMA_ENG_3_WRQ_FIFO_OUT_RDY_MASK}, - {"C2H_STAT_DMA_ENG_3_WRQ_PACKET_OUT_DATA_DROP", - C2H_STAT_DMA_ENG_3_WRQ_PACKET_OUT_DATA_DROP_MASK}, - {"C2H_STAT_DMA_ENG_3_WRQ_PACKET_OUT_DATA_ERR", - C2H_STAT_DMA_ENG_3_WRQ_PACKET_OUT_DATA_ERR_MASK}, - {"C2H_STAT_DMA_ENG_3_WRQ_PACKET_OUT_DATA_MARKER", - C2H_STAT_DMA_ENG_3_WRQ_PACKET_OUT_DATA_MARKER_MASK}, - {"C2H_STAT_DMA_ENG_3_WRQ_PACKET_PRE_EOR", - C2H_STAT_DMA_ENG_3_WRQ_PACKET_PRE_EOR_MASK}, - {"C2H_STAT_DMA_ENG_3_WCP_FIFO_IN_RDY", - C2H_STAT_DMA_ENG_3_WCP_FIFO_IN_RDY_MASK}, - {"C2H_STAT_DMA_ENG_3_PLD_ST_FIFO_IN_RDY", - C2H_STAT_DMA_ENG_3_PLD_ST_FIFO_IN_RDY_MASK}, -}; - - -static struct regfield_info - c2h_dbg_pfch_err_ctxt_field_info[] = { - {"C2H_PFCH_ERR_CTXT_RSVD_1", - C2H_PFCH_ERR_CTXT_RSVD_1_MASK}, - {"C2H_PFCH_ERR_CTXT_ERR_STAT", - C2H_PFCH_ERR_CTXT_ERR_STAT_MASK}, - {"C2H_PFCH_ERR_CTXT_CMD_WR", - C2H_PFCH_ERR_CTXT_CMD_WR_MASK}, - {"C2H_PFCH_ERR_CTXT_QID", - C2H_PFCH_ERR_CTXT_QID_MASK}, - {"C2H_PFCH_ERR_CTXT_DONE", - C2H_PFCH_ERR_CTXT_DONE_MASK}, -}; - - -static struct regfield_info - c2h_first_err_qid_field_info[] = { - {"C2H_FIRST_ERR_QID_RSVD_1", - C2H_FIRST_ERR_QID_RSVD_1_MASK}, - {"C2H_FIRST_ERR_QID_ERR_TYPE", - C2H_FIRST_ERR_QID_ERR_TYPE_MASK}, - {"C2H_FIRST_ERR_QID_RSVD", - C2H_FIRST_ERR_QID_RSVD_MASK}, - {"C2H_FIRST_ERR_QID_QID", - C2H_FIRST_ERR_QID_QID_MASK}, -}; - - -static struct regfield_info - stat_num_wrb_in_field_info[] = { - {"STAT_NUM_WRB_IN_RSVD_1", - STAT_NUM_WRB_IN_RSVD_1_MASK}, - {"STAT_NUM_WRB_IN_WRB_CNT", - STAT_NUM_WRB_IN_WRB_CNT_MASK}, -}; - - -static struct regfield_info - stat_num_wrb_out_field_info[] = { - {"STAT_NUM_WRB_OUT_RSVD_1", - STAT_NUM_WRB_OUT_RSVD_1_MASK}, - {"STAT_NUM_WRB_OUT_WRB_CNT", - STAT_NUM_WRB_OUT_WRB_CNT_MASK}, -}; - - -static struct regfield_info - stat_num_wrb_drp_field_info[] = { - {"STAT_NUM_WRB_DRP_RSVD_1", - STAT_NUM_WRB_DRP_RSVD_1_MASK}, - {"STAT_NUM_WRB_DRP_WRB_CNT", - STAT_NUM_WRB_DRP_WRB_CNT_MASK}, -}; - - -static struct regfield_info - stat_num_stat_desc_out_field_info[] = { - {"STAT_NUM_STAT_DESC_OUT_RSVD_1", - STAT_NUM_STAT_DESC_OUT_RSVD_1_MASK}, - {"STAT_NUM_STAT_DESC_OUT_CNT", - STAT_NUM_STAT_DESC_OUT_CNT_MASK}, -}; - - -static struct regfield_info - stat_num_dsc_crdt_sent_field_info[] = { - {"STAT_NUM_DSC_CRDT_SENT_RSVD_1", - STAT_NUM_DSC_CRDT_SENT_RSVD_1_MASK}, - {"STAT_NUM_DSC_CRDT_SENT_CNT", - STAT_NUM_DSC_CRDT_SENT_CNT_MASK}, -}; - - -static struct regfield_info - stat_num_fch_dsc_rcvd_field_info[] = { - {"STAT_NUM_FCH_DSC_RCVD_RSVD_1", - STAT_NUM_FCH_DSC_RCVD_RSVD_1_MASK}, - {"STAT_NUM_FCH_DSC_RCVD_DSC_CNT", - STAT_NUM_FCH_DSC_RCVD_DSC_CNT_MASK}, -}; - - -static struct regfield_info - stat_num_byp_dsc_rcvd_field_info[] = { - {"STAT_NUM_BYP_DSC_RCVD_RSVD_1", - STAT_NUM_BYP_DSC_RCVD_RSVD_1_MASK}, - {"STAT_NUM_BYP_DSC_RCVD_DSC_CNT", - STAT_NUM_BYP_DSC_RCVD_DSC_CNT_MASK}, -}; - - -static struct regfield_info - c2h_wrb_coal_cfg_field_info[] = { - {"C2H_WRB_COAL_CFG_MAX_BUF_SZ", - C2H_WRB_COAL_CFG_MAX_BUF_SZ_MASK}, - {"C2H_WRB_COAL_CFG_TICK_VAL", - C2H_WRB_COAL_CFG_TICK_VAL_MASK}, - {"C2H_WRB_COAL_CFG_TICK_CNT", - C2H_WRB_COAL_CFG_TICK_CNT_MASK}, - {"C2H_WRB_COAL_CFG_SET_GLB_FLUSH", - C2H_WRB_COAL_CFG_SET_GLB_FLUSH_MASK}, - {"C2H_WRB_COAL_CFG_DONE_GLB_FLUSH", - C2H_WRB_COAL_CFG_DONE_GLB_FLUSH_MASK}, -}; - - -static struct regfield_info - c2h_intr_h2c_req_field_info[] = { - {"C2H_INTR_H2C_REQ_RSVD_1", - C2H_INTR_H2C_REQ_RSVD_1_MASK}, - {"C2H_INTR_H2C_REQ_CNT", - C2H_INTR_H2C_REQ_CNT_MASK}, -}; - - -static struct regfield_info - c2h_intr_c2h_mm_req_field_info[] = { - {"C2H_INTR_C2H_MM_REQ_RSVD_1", - C2H_INTR_C2H_MM_REQ_RSVD_1_MASK}, - {"C2H_INTR_C2H_MM_REQ_CNT", - C2H_INTR_C2H_MM_REQ_CNT_MASK}, -}; - - -static struct regfield_info - c2h_intr_err_int_req_field_info[] = { - {"C2H_INTR_ERR_INT_REQ_RSVD_1", - C2H_INTR_ERR_INT_REQ_RSVD_1_MASK}, - {"C2H_INTR_ERR_INT_REQ_CNT", - C2H_INTR_ERR_INT_REQ_CNT_MASK}, -}; - - -static struct regfield_info - c2h_intr_c2h_st_req_field_info[] = { - {"C2H_INTR_C2H_ST_REQ_RSVD_1", - C2H_INTR_C2H_ST_REQ_RSVD_1_MASK}, - {"C2H_INTR_C2H_ST_REQ_CNT", - C2H_INTR_C2H_ST_REQ_CNT_MASK}, -}; - - -static struct regfield_info - c2h_intr_h2c_err_c2h_mm_msix_ack_field_info[] = { - {"C2H_INTR_H2C_ERR_C2H_MM_MSIX_ACK_RSVD_1", - C2H_INTR_H2C_ERR_C2H_MM_MSIX_ACK_RSVD_1_MASK}, - {"C2H_INTR_H2C_ERR_C2H_MM_MSIX_ACK_CNT", - C2H_INTR_H2C_ERR_C2H_MM_MSIX_ACK_CNT_MASK}, -}; - - -static struct regfield_info - c2h_intr_h2c_err_c2h_mm_msix_fail_field_info[] = { - {"C2H_INTR_H2C_ERR_C2H_MM_MSIX_FAIL_RSVD_1", - C2H_INTR_H2C_ERR_C2H_MM_MSIX_FAIL_RSVD_1_MASK}, - {"C2H_INTR_H2C_ERR_C2H_MM_MSIX_FAIL_CNT", - C2H_INTR_H2C_ERR_C2H_MM_MSIX_FAIL_CNT_MASK}, -}; - - -static struct regfield_info - c2h_intr_h2c_err_c2h_mm_msix_no_msix_field_info[] = { - {"C2H_INTR_H2C_ERR_C2H_MM_MSIX_NO_MSIX_RSVD_1", - C2H_INTR_H2C_ERR_C2H_MM_MSIX_NO_MSIX_RSVD_1_MASK}, - {"C2H_INTR_H2C_ERR_C2H_MM_MSIX_NO_MSIX_CNT", - C2H_INTR_H2C_ERR_C2H_MM_MSIX_NO_MSIX_CNT_MASK}, -}; - - -static struct regfield_info - c2h_intr_h2c_err_c2h_mm_ctxt_inval_field_info[] = { - {"C2H_INTR_H2C_ERR_C2H_MM_CTXT_INVAL_RSVD_1", - C2H_INTR_H2C_ERR_C2H_MM_CTXT_INVAL_RSVD_1_MASK}, - {"C2H_INTR_H2C_ERR_C2H_MM_CTXT_INVAL_CNT", - C2H_INTR_H2C_ERR_C2H_MM_CTXT_INVAL_CNT_MASK}, -}; - - -static struct regfield_info - c2h_intr_c2h_st_msix_ack_field_info[] = { - {"C2H_INTR_C2H_ST_MSIX_ACK_RSVD_1", - C2H_INTR_C2H_ST_MSIX_ACK_RSVD_1_MASK}, - {"C2H_INTR_C2H_ST_MSIX_ACK_CNT", - C2H_INTR_C2H_ST_MSIX_ACK_CNT_MASK}, -}; - - -static struct regfield_info - c2h_intr_c2h_st_msix_fail_field_info[] = { - {"C2H_INTR_C2H_ST_MSIX_FAIL_RSVD_1", - C2H_INTR_C2H_ST_MSIX_FAIL_RSVD_1_MASK}, - {"C2H_INTR_C2H_ST_MSIX_FAIL_CNT", - C2H_INTR_C2H_ST_MSIX_FAIL_CNT_MASK}, -}; - - -static struct regfield_info - c2h_intr_c2h_st_no_msix_field_info[] = { - {"C2H_INTR_C2H_ST_NO_MSIX_RSVD_1", - C2H_INTR_C2H_ST_NO_MSIX_RSVD_1_MASK}, - {"C2H_INTR_C2H_ST_NO_MSIX_CNT", - C2H_INTR_C2H_ST_NO_MSIX_CNT_MASK}, -}; - - -static struct regfield_info - c2h_intr_c2h_st_ctxt_inval_field_info[] = { - {"C2H_INTR_C2H_ST_CTXT_INVAL_RSVD_1", - C2H_INTR_C2H_ST_CTXT_INVAL_RSVD_1_MASK}, - {"C2H_INTR_C2H_ST_CTXT_INVAL_CNT", - C2H_INTR_C2H_ST_CTXT_INVAL_CNT_MASK}, -}; - - -static struct regfield_info - c2h_stat_wr_cmp_field_info[] = { - {"C2H_STAT_WR_CMP_RSVD_1", - C2H_STAT_WR_CMP_RSVD_1_MASK}, - {"C2H_STAT_WR_CMP_CNT", - C2H_STAT_WR_CMP_CNT_MASK}, -}; - - -static struct regfield_info - c2h_stat_dbg_dma_eng_4_field_info[] = { - {"C2H_STAT_DMA_ENG_4_RSVD_1", - C2H_STAT_DMA_ENG_4_RSVD_1_MASK}, - {"C2H_STAT_DMA_ENG_4_WRQ_FIFO_OUT_CNT", - C2H_STAT_DMA_ENG_4_WRQ_FIFO_OUT_CNT_MASK}, - {"C2H_STAT_DMA_ENG_4_QID_FIFO_OUT_VLD", - C2H_STAT_DMA_ENG_4_QID_FIFO_OUT_VLD_MASK}, - {"C2H_STAT_DMA_ENG_4_PLD_FIFO_OUT_VLD", - C2H_STAT_DMA_ENG_4_PLD_FIFO_OUT_VLD_MASK}, - {"C2H_STAT_DMA_ENG_4_PLD_ST_FIFO_OUT_VLD", - C2H_STAT_DMA_ENG_4_PLD_ST_FIFO_OUT_VLD_MASK}, - {"C2H_STAT_DMA_ENG_4_PLD_ST_FIFO_OUT_DATA_EOP", - C2H_STAT_DMA_ENG_4_PLD_ST_FIFO_OUT_DATA_EOP_MASK}, - {"C2H_STAT_DMA_ENG_4_PLD_ST_FIFO_OUT_DATA_AVL_IDX_ENABLE", - C2H_STAT_DMA_ENG_4_PLD_ST_FIFO_OUT_DATA_AVL_IDX_ENABLE_MASK}, - {"C2H_STAT_DMA_ENG_4_PLD_ST_FIFO_OUT_DATA_DROP", - C2H_STAT_DMA_ENG_4_PLD_ST_FIFO_OUT_DATA_DROP_MASK}, - {"C2H_STAT_DMA_ENG_4_PLD_ST_FIFO_OUT_DATA_ERR", - C2H_STAT_DMA_ENG_4_PLD_ST_FIFO_OUT_DATA_ERR_MASK}, - {"C2H_STAT_DMA_ENG_4_DESC_CNT_FIFO_IN_RDY", - C2H_STAT_DMA_ENG_4_DESC_CNT_FIFO_IN_RDY_MASK}, - {"C2H_STAT_DMA_ENG_4_DESC_RSP_FIFO_IN_RDY", - C2H_STAT_DMA_ENG_4_DESC_RSP_FIFO_IN_RDY_MASK}, - {"C2H_STAT_DMA_ENG_4_PLD_PKT_ID_LARGER_0", - C2H_STAT_DMA_ENG_4_PLD_PKT_ID_LARGER_0_MASK}, - {"C2H_STAT_DMA_ENG_4_WRQ_VLD", - C2H_STAT_DMA_ENG_4_WRQ_VLD_MASK}, - {"C2H_STAT_DMA_ENG_4_WRQ_RDY", - C2H_STAT_DMA_ENG_4_WRQ_RDY_MASK}, - {"C2H_STAT_DMA_ENG_4_WRQ_FIFO_OUT_RDY", - C2H_STAT_DMA_ENG_4_WRQ_FIFO_OUT_RDY_MASK}, - {"C2H_STAT_DMA_ENG_4_WRQ_PACKET_OUT_DATA_DROP", - C2H_STAT_DMA_ENG_4_WRQ_PACKET_OUT_DATA_DROP_MASK}, - {"C2H_STAT_DMA_ENG_4_WRQ_PACKET_OUT_DATA_ERR", - C2H_STAT_DMA_ENG_4_WRQ_PACKET_OUT_DATA_ERR_MASK}, - {"C2H_STAT_DMA_ENG_4_WRQ_PACKET_OUT_DATA_MARKER", - C2H_STAT_DMA_ENG_4_WRQ_PACKET_OUT_DATA_MARKER_MASK}, - {"C2H_STAT_DMA_ENG_4_WRQ_PACKET_PRE_EOR", - C2H_STAT_DMA_ENG_4_WRQ_PACKET_PRE_EOR_MASK}, - {"C2H_STAT_DMA_ENG_4_WCP_FIFO_IN_RDY", - C2H_STAT_DMA_ENG_4_WCP_FIFO_IN_RDY_MASK}, - {"C2H_STAT_DMA_ENG_4_PLD_ST_FIFO_IN_RDY", - C2H_STAT_DMA_ENG_4_PLD_ST_FIFO_IN_RDY_MASK}, -}; - - -static struct regfield_info - c2h_stat_dbg_dma_eng_5_field_info[] = { - {"C2H_STAT_DMA_ENG_5_RSVD_1", - C2H_STAT_DMA_ENG_5_RSVD_1_MASK}, - {"C2H_STAT_DMA_ENG_5_WRB_SM_VIRT_CH", - C2H_STAT_DMA_ENG_5_WRB_SM_VIRT_CH_MASK}, - {"C2H_STAT_DMA_ENG_5_WRB_FIFO_IN_REQ", - C2H_STAT_DMA_ENG_5_WRB_FIFO_IN_REQ_MASK}, - {"C2H_STAT_DMA_ENG_5_ARB_FIFO_OUT_CNT", - C2H_STAT_DMA_ENG_5_ARB_FIFO_OUT_CNT_MASK}, - {"C2H_STAT_DMA_ENG_5_ARB_FIFO_OUT_DATA_LEN", - C2H_STAT_DMA_ENG_5_ARB_FIFO_OUT_DATA_LEN_MASK}, - {"C2H_STAT_DMA_ENG_5_ARB_FIFO_OUT_DATA_VIRT_CH", - C2H_STAT_DMA_ENG_5_ARB_FIFO_OUT_DATA_VIRT_CH_MASK}, - {"C2H_STAT_DMA_ENG_5_ARB_FIFO_OUT_DATA_VAR_DESC", - C2H_STAT_DMA_ENG_5_ARB_FIFO_OUT_DATA_VAR_DESC_MASK}, - {"C2H_STAT_DMA_ENG_5_ARB_FIFO_OUT_DATA_DROP_REQ", - C2H_STAT_DMA_ENG_5_ARB_FIFO_OUT_DATA_DROP_REQ_MASK}, - {"C2H_STAT_DMA_ENG_5_ARB_FIFO_OUT_DATA_NUM_BUF_OV", - C2H_STAT_DMA_ENG_5_ARB_FIFO_OUT_DATA_NUM_BUF_OV_MASK}, - {"C2H_STAT_DMA_ENG_5_ARB_FIFO_OUT_DATA_MARKER", - C2H_STAT_DMA_ENG_5_ARB_FIFO_OUT_DATA_MARKER_MASK}, - {"C2H_STAT_DMA_ENG_5_ARB_FIFO_OUT_DATA_HAS_CMPT", - C2H_STAT_DMA_ENG_5_ARB_FIFO_OUT_DATA_HAS_CMPT_MASK}, -}; - - -static struct regfield_info - c2h_dbg_pfch_qid_field_info[] = { - {"C2H_PFCH_QID_RSVD_1", - C2H_PFCH_QID_RSVD_1_MASK}, - {"C2H_PFCH_QID_ERR_CTXT", - C2H_PFCH_QID_ERR_CTXT_MASK}, - {"C2H_PFCH_QID_TARGET", - C2H_PFCH_QID_TARGET_MASK}, - {"C2H_PFCH_QID_QID_OR_TAG", - C2H_PFCH_QID_QID_OR_TAG_MASK}, -}; - - -static struct regfield_info - c2h_dbg_pfch_field_info[] = { - {"C2H_PFCH_DATA", - C2H_PFCH_DATA_MASK}, -}; - - -static struct regfield_info - c2h_int_dbg_field_info[] = { - {"C2H_INT_RSVD_1", - C2H_INT_RSVD_1_MASK}, - {"C2H_INT_INT_COAL_SM", - C2H_INT_INT_COAL_SM_MASK}, - {"C2H_INT_INT_SM", - C2H_INT_INT_SM_MASK}, -}; - - -static struct regfield_info - c2h_stat_imm_accepted_field_info[] = { - {"C2H_STAT_IMM_ACCEPTED_RSVD_1", - C2H_STAT_IMM_ACCEPTED_RSVD_1_MASK}, - {"C2H_STAT_IMM_ACCEPTED_CNT", - C2H_STAT_IMM_ACCEPTED_CNT_MASK}, -}; - - -static struct regfield_info - c2h_stat_marker_accepted_field_info[] = { - {"C2H_STAT_MARKER_ACCEPTED_RSVD_1", - C2H_STAT_MARKER_ACCEPTED_RSVD_1_MASK}, - {"C2H_STAT_MARKER_ACCEPTED_CNT", - C2H_STAT_MARKER_ACCEPTED_CNT_MASK}, -}; - - -static struct regfield_info - c2h_stat_disable_cmp_accepted_field_info[] = { - {"C2H_STAT_DISABLE_CMP_ACCEPTED_RSVD_1", - C2H_STAT_DISABLE_CMP_ACCEPTED_RSVD_1_MASK}, - {"C2H_STAT_DISABLE_CMP_ACCEPTED_CNT", - C2H_STAT_DISABLE_CMP_ACCEPTED_CNT_MASK}, -}; - - -static struct regfield_info - c2h_pld_fifo_crdt_cnt_field_info[] = { - {"C2H_PLD_FIFO_CRDT_CNT_RSVD_1", - C2H_PLD_FIFO_CRDT_CNT_RSVD_1_MASK}, - {"C2H_PLD_FIFO_CRDT_CNT_CNT", - C2H_PLD_FIFO_CRDT_CNT_CNT_MASK}, -}; - - -static struct regfield_info - c2h_intr_dyn_req_field_info[] = { - {"C2H_INTR_DYN_REQ_RSVD_1", - C2H_INTR_DYN_REQ_RSVD_1_MASK}, - {"C2H_INTR_DYN_REQ_CNT", - C2H_INTR_DYN_REQ_CNT_MASK}, -}; - - -static struct regfield_info - c2h_intr_dyn_misc_field_info[] = { - {"C2H_INTR_DYN_MISC_RSVD_1", - C2H_INTR_DYN_MISC_RSVD_1_MASK}, - {"C2H_INTR_DYN_MISC_CNT", - C2H_INTR_DYN_MISC_CNT_MASK}, -}; - - -static struct regfield_info - c2h_drop_len_mismatch_field_info[] = { - {"C2H_DROP_LEN_MISMATCH_RSVD_1", - C2H_DROP_LEN_MISMATCH_RSVD_1_MASK}, - {"C2H_DROP_LEN_MISMATCH_CNT", - C2H_DROP_LEN_MISMATCH_CNT_MASK}, -}; - - -static struct regfield_info - c2h_drop_desc_rsp_len_field_info[] = { - {"C2H_DROP_DESC_RSP_LEN_RSVD_1", - C2H_DROP_DESC_RSP_LEN_RSVD_1_MASK}, - {"C2H_DROP_DESC_RSP_LEN_CNT", - C2H_DROP_DESC_RSP_LEN_CNT_MASK}, -}; - - -static struct regfield_info - c2h_drop_qid_fifo_len_field_info[] = { - {"C2H_DROP_QID_FIFO_LEN_RSVD_1", - C2H_DROP_QID_FIFO_LEN_RSVD_1_MASK}, - {"C2H_DROP_QID_FIFO_LEN_CNT", - C2H_DROP_QID_FIFO_LEN_CNT_MASK}, -}; - - -static struct regfield_info - c2h_drop_pld_cnt_field_info[] = { - {"C2H_DROP_PLD_CNT_RSVD_1", - C2H_DROP_PLD_CNT_RSVD_1_MASK}, - {"C2H_DROP_PLD_CNT_CNT", - C2H_DROP_PLD_CNT_CNT_MASK}, -}; - - -static struct regfield_info - c2h_cmpt_format_0_field_info[] = { - {"C2H_CMPT_FORMAT_0_DESC_ERR_LOC", - C2H_CMPT_FORMAT_0_DESC_ERR_LOC_MASK}, - {"C2H_CMPT_FORMAT_0_COLOR_LOC", - C2H_CMPT_FORMAT_0_COLOR_LOC_MASK}, -}; - - -static struct regfield_info - c2h_cmpt_format_1_field_info[] = { - {"C2H_CMPT_FORMAT_1_DESC_ERR_LOC", - C2H_CMPT_FORMAT_1_DESC_ERR_LOC_MASK}, - {"C2H_CMPT_FORMAT_1_COLOR_LOC", - C2H_CMPT_FORMAT_1_COLOR_LOC_MASK}, -}; - - -static struct regfield_info - c2h_cmpt_format_2_field_info[] = { - {"C2H_CMPT_FORMAT_2_DESC_ERR_LOC", - C2H_CMPT_FORMAT_2_DESC_ERR_LOC_MASK}, - {"C2H_CMPT_FORMAT_2_COLOR_LOC", - C2H_CMPT_FORMAT_2_COLOR_LOC_MASK}, -}; - - -static struct regfield_info - c2h_cmpt_format_3_field_info[] = { - {"C2H_CMPT_FORMAT_3_DESC_ERR_LOC", - C2H_CMPT_FORMAT_3_DESC_ERR_LOC_MASK}, - {"C2H_CMPT_FORMAT_3_COLOR_LOC", - C2H_CMPT_FORMAT_3_COLOR_LOC_MASK}, -}; - - -static struct regfield_info - c2h_cmpt_format_4_field_info[] = { - {"C2H_CMPT_FORMAT_4_DESC_ERR_LOC", - C2H_CMPT_FORMAT_4_DESC_ERR_LOC_MASK}, - {"C2H_CMPT_FORMAT_4_COLOR_LOC", - C2H_CMPT_FORMAT_4_COLOR_LOC_MASK}, -}; - - -static struct regfield_info - c2h_cmpt_format_5_field_info[] = { - {"C2H_CMPT_FORMAT_5_DESC_ERR_LOC", - C2H_CMPT_FORMAT_5_DESC_ERR_LOC_MASK}, - {"C2H_CMPT_FORMAT_5_COLOR_LOC", - C2H_CMPT_FORMAT_5_COLOR_LOC_MASK}, -}; - - -static struct regfield_info - c2h_cmpt_format_6_field_info[] = { - {"C2H_CMPT_FORMAT_6_DESC_ERR_LOC", - C2H_CMPT_FORMAT_6_DESC_ERR_LOC_MASK}, - {"C2H_CMPT_FORMAT_6_COLOR_LOC", - C2H_CMPT_FORMAT_6_COLOR_LOC_MASK}, -}; - - -static struct regfield_info - c2h_pfch_cache_depth_field_info[] = { - {"C2H_PFCH_CACHE_DEPTH_MAX_STBUF", - C2H_PFCH_CACHE_DEPTH_MAX_STBUF_MASK}, - {"C2H_PFCH_CACHE_DEPTH", - C2H_PFCH_CACHE_DEPTH_MASK}, -}; - - -static struct regfield_info - c2h_wrb_coal_buf_depth_field_info[] = { - {"C2H_WRB_COAL_BUF_DEPTH_RSVD_1", - C2H_WRB_COAL_BUF_DEPTH_RSVD_1_MASK}, - {"C2H_WRB_COAL_BUF_DEPTH_BUFFER", - C2H_WRB_COAL_BUF_DEPTH_BUFFER_MASK}, -}; - - -static struct regfield_info - c2h_pfch_crdt_field_info[] = { - {"C2H_PFCH_CRDT_RSVD_1", - C2H_PFCH_CRDT_RSVD_1_MASK}, - {"C2H_PFCH_CRDT_RSVD_2", - C2H_PFCH_CRDT_RSVD_2_MASK}, -}; - - -static struct regfield_info - c2h_stat_has_cmpt_accepted_field_info[] = { - {"C2H_STAT_HAS_CMPT_ACCEPTED_RSVD_1", - C2H_STAT_HAS_CMPT_ACCEPTED_RSVD_1_MASK}, - {"C2H_STAT_HAS_CMPT_ACCEPTED_CNT", - C2H_STAT_HAS_CMPT_ACCEPTED_CNT_MASK}, -}; - - -static struct regfield_info - c2h_stat_has_pld_accepted_field_info[] = { - {"C2H_STAT_HAS_PLD_ACCEPTED_RSVD_1", - C2H_STAT_HAS_PLD_ACCEPTED_RSVD_1_MASK}, - {"C2H_STAT_HAS_PLD_ACCEPTED_CNT", - C2H_STAT_HAS_PLD_ACCEPTED_CNT_MASK}, -}; - - -static struct regfield_info - c2h_pld_pkt_id_field_info[] = { - {"C2H_PLD_PKT_ID_CMPT_WAIT", - C2H_PLD_PKT_ID_CMPT_WAIT_MASK}, - {"C2H_PLD_PKT_ID_DATA", - C2H_PLD_PKT_ID_DATA_MASK}, -}; - - -static struct regfield_info - c2h_pld_pkt_id_1_field_info[] = { - {"C2H_PLD_PKT_ID_1_CMPT_WAIT", - C2H_PLD_PKT_ID_1_CMPT_WAIT_MASK}, - {"C2H_PLD_PKT_ID_1_DATA", - C2H_PLD_PKT_ID_1_DATA_MASK}, -}; - - -static struct regfield_info - c2h_drop_pld_cnt_1_field_info[] = { - {"C2H_DROP_PLD_CNT_1_RSVD_1", - C2H_DROP_PLD_CNT_1_RSVD_1_MASK}, - {"C2H_DROP_PLD_CNT_1_CNT", - C2H_DROP_PLD_CNT_1_CNT_MASK}, -}; - - -static struct regfield_info - h2c_err_stat_field_info[] = { - {"H2C_ERR_STAT_RSVD_1", - H2C_ERR_STAT_RSVD_1_MASK}, - {"H2C_ERR_STAT_PAR_ERR", - H2C_ERR_STAT_PAR_ERR_MASK}, - {"H2C_ERR_STAT_SBE", - H2C_ERR_STAT_SBE_MASK}, - {"H2C_ERR_STAT_DBE", - H2C_ERR_STAT_DBE_MASK}, - {"H2C_ERR_STAT_NO_DMA_DS", - H2C_ERR_STAT_NO_DMA_DS_MASK}, - {"H2C_ERR_STAT_SDI_MRKR_REQ_MOP_ERR", - H2C_ERR_STAT_SDI_MRKR_REQ_MOP_ERR_MASK}, - {"H2C_ERR_STAT_ZERO_LEN_DS", - H2C_ERR_STAT_ZERO_LEN_DS_MASK}, -}; - - -static struct regfield_info - h2c_err_mask_field_info[] = { - {"H2C_ERR_EN", - H2C_ERR_EN_MASK}, -}; - - -static struct regfield_info - h2c_first_err_qid_field_info[] = { - {"H2C_FIRST_ERR_QID_RSVD_1", - H2C_FIRST_ERR_QID_RSVD_1_MASK}, - {"H2C_FIRST_ERR_QID_ERR_TYPE", - H2C_FIRST_ERR_QID_ERR_TYPE_MASK}, - {"H2C_FIRST_ERR_QID_RSVD_2", - H2C_FIRST_ERR_QID_RSVD_2_MASK}, - {"H2C_FIRST_ERR_QID_QID", - H2C_FIRST_ERR_QID_QID_MASK}, -}; - - -static struct regfield_info - h2c_dbg_reg0_field_info[] = { - {"H2C_REG0_NUM_DSC_RCVD", - H2C_REG0_NUM_DSC_RCVD_MASK}, - {"H2C_REG0_NUM_WRB_SENT", - H2C_REG0_NUM_WRB_SENT_MASK}, -}; - - -static struct regfield_info - h2c_dbg_reg1_field_info[] = { - {"H2C_REG1_NUM_REQ_SENT", - H2C_REG1_NUM_REQ_SENT_MASK}, - {"H2C_REG1_NUM_CMP_SENT", - H2C_REG1_NUM_CMP_SENT_MASK}, -}; - - -static struct regfield_info - h2c_dbg_reg2_field_info[] = { - {"H2C_REG2_RSVD_1", - H2C_REG2_RSVD_1_MASK}, - {"H2C_REG2_NUM_ERR_DSC_RCVD", - H2C_REG2_NUM_ERR_DSC_RCVD_MASK}, -}; - - -static struct regfield_info - h2c_dbg_reg3_field_info[] = { - {"H2C_REG3_RSVD_1", - H2C_REG3_RSVD_1_MASK}, - {"H2C_REG3_DSCO_FIFO_EMPTY", - H2C_REG3_DSCO_FIFO_EMPTY_MASK}, - {"H2C_REG3_DSCO_FIFO_FULL", - H2C_REG3_DSCO_FIFO_FULL_MASK}, - {"H2C_REG3_CUR_RC_STATE", - H2C_REG3_CUR_RC_STATE_MASK}, - {"H2C_REG3_RDREQ_LINES", - H2C_REG3_RDREQ_LINES_MASK}, - {"H2C_REG3_RDATA_LINES_AVAIL", - H2C_REG3_RDATA_LINES_AVAIL_MASK}, - {"H2C_REG3_PEND_FIFO_EMPTY", - H2C_REG3_PEND_FIFO_EMPTY_MASK}, - {"H2C_REG3_PEND_FIFO_FULL", - H2C_REG3_PEND_FIFO_FULL_MASK}, - {"H2C_REG3_CUR_RQ_STATE", - H2C_REG3_CUR_RQ_STATE_MASK}, - {"H2C_REG3_DSCI_FIFO_FULL", - H2C_REG3_DSCI_FIFO_FULL_MASK}, - {"H2C_REG3_DSCI_FIFO_EMPTY", - H2C_REG3_DSCI_FIFO_EMPTY_MASK}, -}; - - -static struct regfield_info - h2c_dbg_reg4_field_info[] = { - {"H2C_REG4_RDREQ_ADDR", - H2C_REG4_RDREQ_ADDR_MASK}, -}; - - -static struct regfield_info - h2c_fatal_err_en_field_info[] = { - {"H2C_FATAL_ERR_EN_RSVD_1", - H2C_FATAL_ERR_EN_RSVD_1_MASK}, - {"H2C_FATAL_ERR_EN_H2C", - H2C_FATAL_ERR_EN_H2C_MASK}, -}; - - -static struct regfield_info - h2c_req_throt_pcie_field_info[] = { - {"H2C_REQ_THROT_PCIE_EN_REQ", - H2C_REQ_THROT_PCIE_EN_REQ_MASK}, - {"H2C_REQ_THROT_PCIE", - H2C_REQ_THROT_PCIE_MASK}, - {"H2C_REQ_THROT_PCIE_EN_DATA", - H2C_REQ_THROT_PCIE_EN_DATA_MASK}, - {"H2C_REQ_THROT_PCIE_DATA_THRESH", - H2C_REQ_THROT_PCIE_DATA_THRESH_MASK}, -}; - - -static struct regfield_info - h2c_aln_dbg_reg0_field_info[] = { - {"H2C_ALN_REG0_NUM_PKT_SENT", - H2C_ALN_REG0_NUM_PKT_SENT_MASK}, -}; - - -static struct regfield_info - h2c_req_throt_aximm_field_info[] = { - {"H2C_REQ_THROT_AXIMM_EN_REQ", - H2C_REQ_THROT_AXIMM_EN_REQ_MASK}, - {"H2C_REQ_THROT_AXIMM", - H2C_REQ_THROT_AXIMM_MASK}, - {"H2C_REQ_THROT_AXIMM_EN_DATA", - H2C_REQ_THROT_AXIMM_EN_DATA_MASK}, - {"H2C_REQ_THROT_AXIMM_DATA_THRESH", - H2C_REQ_THROT_AXIMM_DATA_THRESH_MASK}, -}; - - -static struct regfield_info - c2h_mm_ctl_field_info[] = { - {"C2H_MM_CTL_RESERVED1", - C2H_MM_CTL_RESERVED1_MASK}, - {"C2H_MM_CTL_ERRC_EN", - C2H_MM_CTL_ERRC_EN_MASK}, - {"C2H_MM_CTL_RESERVED0", - C2H_MM_CTL_RESERVED0_MASK}, - {"C2H_MM_CTL_RUN", - C2H_MM_CTL_RUN_MASK}, -}; - - -static struct regfield_info - c2h_mm_status_field_info[] = { - {"C2H_MM_STATUS_RSVD_1", - C2H_MM_STATUS_RSVD_1_MASK}, - {"C2H_MM_STATUS_RUN", - C2H_MM_STATUS_RUN_MASK}, -}; - - -static struct regfield_info - c2h_mm_cmpl_desc_cnt_field_info[] = { - {"C2H_MM_CMPL_DESC_CNT_C2H_CO", - C2H_MM_CMPL_DESC_CNT_C2H_CO_MASK}, -}; - - -static struct regfield_info - c2h_mm_err_code_enable_mask_field_info[] = { - {"C2H_MM_ERR_CODE_ENABLE_RESERVED1", - C2H_MM_ERR_CODE_ENABLE_RESERVED1_MASK}, - {"C2H_MM_ERR_CODE_ENABLE_WR_UC_RAM", - C2H_MM_ERR_CODE_ENABLE_WR_UC_RAM_MASK}, - {"C2H_MM_ERR_CODE_ENABLE_WR_UR", - C2H_MM_ERR_CODE_ENABLE_WR_UR_MASK}, - {"C2H_MM_ERR_CODE_ENABLE_WR_FLR", - C2H_MM_ERR_CODE_ENABLE_WR_FLR_MASK}, - {"C2H_MM_ERR_CODE_ENABLE_RESERVED0", - C2H_MM_ERR_CODE_ENABLE_RESERVED0_MASK}, - {"C2H_MM_ERR_CODE_ENABLE_RD_SLV_ERR", - C2H_MM_ERR_CODE_ENABLE_RD_SLV_ERR_MASK}, - {"C2H_MM_ERR_CODE_ENABLE_WR_SLV_ERR", - C2H_MM_ERR_CODE_ENABLE_WR_SLV_ERR_MASK}, -}; - - -static struct regfield_info - c2h_mm_err_code_field_info[] = { - {"C2H_MM_ERR_CODE_RESERVED1", - C2H_MM_ERR_CODE_RESERVED1_MASK}, - {"C2H_MM_ERR_CODE_CIDX", - C2H_MM_ERR_CODE_CIDX_MASK}, - {"C2H_MM_ERR_CODE_RESERVED0", - C2H_MM_ERR_CODE_RESERVED0_MASK}, - {"C2H_MM_ERR_CODE_SUB_TYPE", - C2H_MM_ERR_CODE_SUB_TYPE_MASK}, - {"C2H_MM_ERR_CODE", - C2H_MM_ERR_CODE_MASK}, -}; - - -static struct regfield_info - c2h_mm_err_info_field_info[] = { - {"C2H_MM_ERR_INFO_VALID", - C2H_MM_ERR_INFO_VALID_MASK}, - {"C2H_MM_ERR_INFO_SEL", - C2H_MM_ERR_INFO_SEL_MASK}, - {"C2H_MM_ERR_INFO_RSVD_1", - C2H_MM_ERR_INFO_RSVD_1_MASK}, - {"C2H_MM_ERR_INFO_QID", - C2H_MM_ERR_INFO_QID_MASK}, -}; - - -static struct regfield_info - c2h_mm_perf_mon_ctl_field_info[] = { - {"C2H_MM_PERF_MON_CTL_RSVD_1", - C2H_MM_PERF_MON_CTL_RSVD_1_MASK}, - {"C2H_MM_PERF_MON_CTL_IMM_START", - C2H_MM_PERF_MON_CTL_IMM_START_MASK}, - {"C2H_MM_PERF_MON_CTL_RUN_START", - C2H_MM_PERF_MON_CTL_RUN_START_MASK}, - {"C2H_MM_PERF_MON_CTL_IMM_CLEAR", - C2H_MM_PERF_MON_CTL_IMM_CLEAR_MASK}, - {"C2H_MM_PERF_MON_CTL_RUN_CLEAR", - C2H_MM_PERF_MON_CTL_RUN_CLEAR_MASK}, -}; - - -static struct regfield_info - c2h_mm_perf_mon_cycle_cnt0_field_info[] = { - {"C2H_MM_PERF_MON_CYCLE_CNT0_CYC_CNT", - C2H_MM_PERF_MON_CYCLE_CNT0_CYC_CNT_MASK}, -}; - - -static struct regfield_info - c2h_mm_perf_mon_cycle_cnt1_field_info[] = { - {"C2H_MM_PERF_MON_CYCLE_CNT1_RSVD_1", - C2H_MM_PERF_MON_CYCLE_CNT1_RSVD_1_MASK}, - {"C2H_MM_PERF_MON_CYCLE_CNT1_CYC_CNT", - C2H_MM_PERF_MON_CYCLE_CNT1_CYC_CNT_MASK}, -}; - - -static struct regfield_info - c2h_mm_perf_mon_data_cnt0_field_info[] = { - {"C2H_MM_PERF_MON_DATA_CNT0_DCNT", - C2H_MM_PERF_MON_DATA_CNT0_DCNT_MASK}, -}; - - -static struct regfield_info - c2h_mm_perf_mon_data_cnt1_field_info[] = { - {"C2H_MM_PERF_MON_DATA_CNT1_RSVD_1", - C2H_MM_PERF_MON_DATA_CNT1_RSVD_1_MASK}, - {"C2H_MM_PERF_MON_DATA_CNT1_DCNT", - C2H_MM_PERF_MON_DATA_CNT1_DCNT_MASK}, -}; - - -static struct regfield_info - c2h_mm_dbg_field_info[] = { - {"C2H_MM_RSVD_1", - C2H_MM_RSVD_1_MASK}, - {"C2H_MM_RRQ_ENTRIES", - C2H_MM_RRQ_ENTRIES_MASK}, - {"C2H_MM_DAT_FIFO_SPC", - C2H_MM_DAT_FIFO_SPC_MASK}, - {"C2H_MM_RD_STALL", - C2H_MM_RD_STALL_MASK}, - {"C2H_MM_RRQ_FIFO_FI", - C2H_MM_RRQ_FIFO_FI_MASK}, - {"C2H_MM_WR_STALL", - C2H_MM_WR_STALL_MASK}, - {"C2H_MM_WRQ_FIFO_FI", - C2H_MM_WRQ_FIFO_FI_MASK}, - {"C2H_MM_WBK_STALL", - C2H_MM_WBK_STALL_MASK}, - {"C2H_MM_DSC_FIFO_EP", - C2H_MM_DSC_FIFO_EP_MASK}, - {"C2H_MM_DSC_FIFO_FL", - C2H_MM_DSC_FIFO_FL_MASK}, -}; - - -static struct regfield_info - h2c_mm_ctl_field_info[] = { - {"H2C_MM_CTL_RESERVED1", - H2C_MM_CTL_RESERVED1_MASK}, - {"H2C_MM_CTL_ERRC_EN", - H2C_MM_CTL_ERRC_EN_MASK}, - {"H2C_MM_CTL_RESERVED0", - H2C_MM_CTL_RESERVED0_MASK}, - {"H2C_MM_CTL_RUN", - H2C_MM_CTL_RUN_MASK}, -}; - - -static struct regfield_info - h2c_mm_status_field_info[] = { - {"H2C_MM_STATUS_RSVD_1", - H2C_MM_STATUS_RSVD_1_MASK}, - {"H2C_MM_STATUS_RUN", - H2C_MM_STATUS_RUN_MASK}, -}; - - -static struct regfield_info - h2c_mm_cmpl_desc_cnt_field_info[] = { - {"H2C_MM_CMPL_DESC_CNT_H2C_CO", - H2C_MM_CMPL_DESC_CNT_H2C_CO_MASK}, -}; - - -static struct regfield_info - h2c_mm_err_code_enable_mask_field_info[] = { - {"H2C_MM_ERR_CODE_ENABLE_RESERVED5", - H2C_MM_ERR_CODE_ENABLE_RESERVED5_MASK}, - {"H2C_MM_ERR_CODE_ENABLE_WR_SLV_ERR", - H2C_MM_ERR_CODE_ENABLE_WR_SLV_ERR_MASK}, - {"H2C_MM_ERR_CODE_ENABLE_WR_DEC_ERR", - H2C_MM_ERR_CODE_ENABLE_WR_DEC_ERR_MASK}, - {"H2C_MM_ERR_CODE_ENABLE_RESERVED4", - H2C_MM_ERR_CODE_ENABLE_RESERVED4_MASK}, - {"H2C_MM_ERR_CODE_ENABLE_RD_RQ_DIS_ERR", - H2C_MM_ERR_CODE_ENABLE_RD_RQ_DIS_ERR_MASK}, - {"H2C_MM_ERR_CODE_ENABLE_RESERVED3", - H2C_MM_ERR_CODE_ENABLE_RESERVED3_MASK}, - {"H2C_MM_ERR_CODE_ENABLE_RD_DAT_POISON_ERR", - H2C_MM_ERR_CODE_ENABLE_RD_DAT_POISON_ERR_MASK}, - {"H2C_MM_ERR_CODE_ENABLE_RESERVED2", - H2C_MM_ERR_CODE_ENABLE_RESERVED2_MASK}, - {"H2C_MM_ERR_CODE_ENABLE_RD_FLR_ERR", - H2C_MM_ERR_CODE_ENABLE_RD_FLR_ERR_MASK}, - {"H2C_MM_ERR_CODE_ENABLE_RESERVED1", - H2C_MM_ERR_CODE_ENABLE_RESERVED1_MASK}, - {"H2C_MM_ERR_CODE_ENABLE_RD_HDR_ADR_ERR", - H2C_MM_ERR_CODE_ENABLE_RD_HDR_ADR_ERR_MASK}, - {"H2C_MM_ERR_CODE_ENABLE_RD_HDR_PARA", - H2C_MM_ERR_CODE_ENABLE_RD_HDR_PARA_MASK}, - {"H2C_MM_ERR_CODE_ENABLE_RD_HDR_BYTE_ERR", - H2C_MM_ERR_CODE_ENABLE_RD_HDR_BYTE_ERR_MASK}, - {"H2C_MM_ERR_CODE_ENABLE_RD_UR_CA", - H2C_MM_ERR_CODE_ENABLE_RD_UR_CA_MASK}, - {"H2C_MM_ERR_CODE_ENABLE_RD_HRD_POISON_ERR", - H2C_MM_ERR_CODE_ENABLE_RD_HRD_POISON_ERR_MASK}, - {"H2C_MM_ERR_CODE_ENABLE_RESERVED0", - H2C_MM_ERR_CODE_ENABLE_RESERVED0_MASK}, -}; - - -static struct regfield_info - h2c_mm_err_code_field_info[] = { - {"H2C_MM_ERR_CODE_RSVD_1", - H2C_MM_ERR_CODE_RSVD_1_MASK}, - {"H2C_MM_ERR_CODE_CIDX", - H2C_MM_ERR_CODE_CIDX_MASK}, - {"H2C_MM_ERR_CODE_RESERVED0", - H2C_MM_ERR_CODE_RESERVED0_MASK}, - {"H2C_MM_ERR_CODE_SUB_TYPE", - H2C_MM_ERR_CODE_SUB_TYPE_MASK}, - {"H2C_MM_ERR_CODE", - H2C_MM_ERR_CODE_MASK}, -}; - - -static struct regfield_info - h2c_mm_err_info_field_info[] = { - {"H2C_MM_ERR_INFO_VALID", - H2C_MM_ERR_INFO_VALID_MASK}, - {"H2C_MM_ERR_INFO_SEL", - H2C_MM_ERR_INFO_SEL_MASK}, - {"H2C_MM_ERR_INFO_RSVD_1", - H2C_MM_ERR_INFO_RSVD_1_MASK}, - {"H2C_MM_ERR_INFO_QID", - H2C_MM_ERR_INFO_QID_MASK}, -}; - - -static struct regfield_info - h2c_mm_perf_mon_ctl_field_info[] = { - {"H2C_MM_PERF_MON_CTL_RSVD_1", - H2C_MM_PERF_MON_CTL_RSVD_1_MASK}, - {"H2C_MM_PERF_MON_CTL_IMM_START", - H2C_MM_PERF_MON_CTL_IMM_START_MASK}, - {"H2C_MM_PERF_MON_CTL_RUN_START", - H2C_MM_PERF_MON_CTL_RUN_START_MASK}, - {"H2C_MM_PERF_MON_CTL_IMM_CLEAR", - H2C_MM_PERF_MON_CTL_IMM_CLEAR_MASK}, - {"H2C_MM_PERF_MON_CTL_RUN_CLEAR", - H2C_MM_PERF_MON_CTL_RUN_CLEAR_MASK}, -}; - - -static struct regfield_info - h2c_mm_perf_mon_cycle_cnt0_field_info[] = { - {"H2C_MM_PERF_MON_CYCLE_CNT0_CYC_CNT", - H2C_MM_PERF_MON_CYCLE_CNT0_CYC_CNT_MASK}, -}; - - -static struct regfield_info - h2c_mm_perf_mon_cycle_cnt1_field_info[] = { - {"H2C_MM_PERF_MON_CYCLE_CNT1_RSVD_1", - H2C_MM_PERF_MON_CYCLE_CNT1_RSVD_1_MASK}, - {"H2C_MM_PERF_MON_CYCLE_CNT1_CYC_CNT", - H2C_MM_PERF_MON_CYCLE_CNT1_CYC_CNT_MASK}, -}; - - -static struct regfield_info - h2c_mm_perf_mon_data_cnt0_field_info[] = { - {"H2C_MM_PERF_MON_DATA_CNT0_DCNT", - H2C_MM_PERF_MON_DATA_CNT0_DCNT_MASK}, -}; - - -static struct regfield_info - h2c_mm_perf_mon_data_cnt1_field_info[] = { - {"H2C_MM_PERF_MON_DATA_CNT1_RSVD_1", - H2C_MM_PERF_MON_DATA_CNT1_RSVD_1_MASK}, - {"H2C_MM_PERF_MON_DATA_CNT1_DCNT", - H2C_MM_PERF_MON_DATA_CNT1_DCNT_MASK}, -}; - - -static struct regfield_info - h2c_mm_dbg_field_info[] = { - {"H2C_MM_RSVD_1", - H2C_MM_RSVD_1_MASK}, - {"H2C_MM_RRQ_ENTRIES", - H2C_MM_RRQ_ENTRIES_MASK}, - {"H2C_MM_DAT_FIFO_SPC", - H2C_MM_DAT_FIFO_SPC_MASK}, - {"H2C_MM_RD_STALL", - H2C_MM_RD_STALL_MASK}, - {"H2C_MM_RRQ_FIFO_FI", - H2C_MM_RRQ_FIFO_FI_MASK}, - {"H2C_MM_WR_STALL", - H2C_MM_WR_STALL_MASK}, - {"H2C_MM_WRQ_FIFO_FI", - H2C_MM_WRQ_FIFO_FI_MASK}, - {"H2C_MM_WBK_STALL", - H2C_MM_WBK_STALL_MASK}, - {"H2C_MM_DSC_FIFO_EP", - H2C_MM_DSC_FIFO_EP_MASK}, - {"H2C_MM_DSC_FIFO_FL", - H2C_MM_DSC_FIFO_FL_MASK}, -}; - - -static struct regfield_info - c2h_crdt_coal_cfg_1_field_info[] = { - {"C2H_CRDT_COAL_CFG_1_RSVD_1", - C2H_CRDT_COAL_CFG_1_RSVD_1_MASK}, - {"C2H_CRDT_COAL_CFG_1_PLD_FIFO_TH", - C2H_CRDT_COAL_CFG_1_PLD_FIFO_TH_MASK}, - {"C2H_CRDT_COAL_CFG_1_TIMER_TH", - C2H_CRDT_COAL_CFG_1_TIMER_TH_MASK}, -}; - - -static struct regfield_info - c2h_crdt_coal_cfg_2_field_info[] = { - {"C2H_CRDT_COAL_CFG_2_RSVD_1", - C2H_CRDT_COAL_CFG_2_RSVD_1_MASK}, - {"C2H_CRDT_COAL_CFG_2_FIFO_TH", - C2H_CRDT_COAL_CFG_2_FIFO_TH_MASK}, - {"C2H_CRDT_COAL_CFG_2_RESERVED1", - C2H_CRDT_COAL_CFG_2_RESERVED1_MASK}, - {"C2H_CRDT_COAL_CFG_2_NT_TH", - C2H_CRDT_COAL_CFG_2_NT_TH_MASK}, -}; - - -static struct regfield_info - c2h_pfch_byp_qid_field_info[] = { - {"C2H_PFCH_BYP_QID_RSVD_1", - C2H_PFCH_BYP_QID_RSVD_1_MASK}, - {"C2H_PFCH_BYP_QID", - C2H_PFCH_BYP_QID_MASK}, -}; - - -static struct regfield_info - c2h_pfch_byp_tag_field_info[] = { - {"C2H_PFCH_BYP_TAG_RSVD_1", - C2H_PFCH_BYP_TAG_RSVD_1_MASK}, - {"C2H_PFCH_BYP_TAG_BYP_QID", - C2H_PFCH_BYP_TAG_BYP_QID_MASK}, - {"C2H_PFCH_BYP_TAG_RSVD_2", - C2H_PFCH_BYP_TAG_RSVD_2_MASK}, - {"C2H_PFCH_BYP_TAG", - C2H_PFCH_BYP_TAG_MASK}, -}; - - -static struct regfield_info - c2h_water_mark_field_info[] = { - {"C2H_WATER_MARK_HIGH_WM", - C2H_WATER_MARK_HIGH_WM_MASK}, - {"C2H_WATER_MARK_LOW_WM", - C2H_WATER_MARK_LOW_WM_MASK}, -}; - - -static struct regfield_info - c2h_notify_empty_field_info[] = { - {"C2H_NOTIFY_EMPTY_RSVD_1", - C2H_NOTIFY_EMPTY_RSVD_1_MASK}, - {"C2H_NOTIFY_EMPTY_NOE", - C2H_NOTIFY_EMPTY_NOE_MASK}, -}; - - -static struct regfield_info - c2h_stat_s_axis_c2h_accepted_1_field_info[] = { - {"C2H_STAT_S_AXIS_C2H_ACCEPTED_1", - C2H_STAT_S_AXIS_C2H_ACCEPTED_1_MASK}, -}; - - -static struct regfield_info - c2h_stat_s_axis_wrb_accepted_1_field_info[] = { - {"C2H_STAT_S_AXIS_WRB_ACCEPTED_1", - C2H_STAT_S_AXIS_WRB_ACCEPTED_1_MASK}, -}; - - -static struct regfield_info - c2h_stat_desc_rsp_pkt_accepted_1_field_info[] = { - {"C2H_STAT_DESC_RSP_PKT_ACCEPTED_1_D", - C2H_STAT_DESC_RSP_PKT_ACCEPTED_1_D_MASK}, -}; - - -static struct regfield_info - c2h_stat_axis_pkg_cmp_1_field_info[] = { - {"C2H_STAT_AXIS_PKG_CMP_1", - C2H_STAT_AXIS_PKG_CMP_1_MASK}, -}; - - -static struct regfield_info - c2h_stat_s_axis_wrb_accepted_2_field_info[] = { - {"C2H_STAT_S_AXIS_WRB_ACCEPTED_2", - C2H_STAT_S_AXIS_WRB_ACCEPTED_2_MASK}, -}; - - -static struct regfield_info - c2h_st_pld_fifo_depth_field_info[] = { - {"C2H_ST_PLD_FIFO_DEPTH", - C2H_ST_PLD_FIFO_DEPTH_MASK}, -}; - -static struct xreg_info eqdma_cpm5_config_regs[] = { -{"CFG_BLK_IDENTIFIER", 0x00, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(cfg_blk_identifier_field_info), - cfg_blk_identifier_field_info -}, -{"CFG_BLK_PCIE_MAX_PLD_SIZE", 0x08, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(cfg_blk_pcie_max_pld_size_field_info), - cfg_blk_pcie_max_pld_size_field_info -}, -{"CFG_BLK_PCIE_MAX_READ_REQ_SIZE", 0x0c, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(cfg_blk_pcie_max_read_req_size_field_info), - cfg_blk_pcie_max_read_req_size_field_info -}, -{"CFG_BLK_SYSTEM_ID", 0x10, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(cfg_blk_system_id_field_info), - cfg_blk_system_id_field_info -}, -{"CFG_BLK_MSIX_ENABLE", 0x014, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(cfg_blk_msix_enable_field_info), - cfg_blk_msix_enable_field_info -}, -{"CFG_PCIE_DATA_WIDTH", 0x18, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(cfg_pcie_data_width_field_info), - cfg_pcie_data_width_field_info -}, -{"CFG_PCIE_CTL", 0x1c, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(cfg_pcie_ctl_field_info), - cfg_pcie_ctl_field_info -}, -{"CFG_BLK_MSI_ENABLE", 0x20, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(cfg_blk_msi_enable_field_info), - cfg_blk_msi_enable_field_info -}, -{"CFG_AXI_USER_MAX_PLD_SIZE", 0x40, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(cfg_axi_user_max_pld_size_field_info), - cfg_axi_user_max_pld_size_field_info -}, -{"CFG_AXI_USER_MAX_READ_REQ_SIZE", 0x44, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(cfg_axi_user_max_read_req_size_field_info), - cfg_axi_user_max_read_req_size_field_info -}, -{"CFG_BLK_MISC_CTL", 0x4c, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(cfg_blk_misc_ctl_field_info), - cfg_blk_misc_ctl_field_info -}, -{"CFG_PL_CRED_CTL", 0x68, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(cfg_pl_cred_ctl_field_info), - cfg_pl_cred_ctl_field_info -}, -{"CFG_BLK_SCRATCH", 0x80, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(cfg_blk_scratch_field_info), - cfg_blk_scratch_field_info -}, -{"CFG_GIC", 0xa0, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(cfg_gic_field_info), - cfg_gic_field_info -}, -{"RAM_SBE_MSK_1_A", 0xe0, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(ram_sbe_msk_1_a_field_info), - ram_sbe_msk_1_a_field_info -}, -{"RAM_SBE_STS_1_A", 0xe4, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(ram_sbe_sts_1_a_field_info), - ram_sbe_sts_1_a_field_info -}, -{"RAM_DBE_MSK_1_A", 0xe8, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(ram_dbe_msk_1_a_field_info), - ram_dbe_msk_1_a_field_info -}, -{"RAM_DBE_STS_1_A", 0xec, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(ram_dbe_sts_1_a_field_info), - ram_dbe_sts_1_a_field_info -}, -{"RAM_SBE_MSK_A", 0xf0, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(ram_sbe_msk_a_field_info), - ram_sbe_msk_a_field_info -}, -{"RAM_SBE_STS_A", 0xf4, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(ram_sbe_sts_a_field_info), - ram_sbe_sts_a_field_info -}, -{"RAM_DBE_MSK_A", 0xf8, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(ram_dbe_msk_a_field_info), - ram_dbe_msk_a_field_info -}, -{"RAM_DBE_STS_A", 0xfc, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(ram_dbe_sts_a_field_info), - ram_dbe_sts_a_field_info -}, -{"GLBL2_IDENTIFIER", 0x100, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(glbl2_identifier_field_info), - glbl2_identifier_field_info -}, -{"GLBL2_CHANNEL_INST", 0x114, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(glbl2_channel_inst_field_info), - glbl2_channel_inst_field_info -}, -{"GLBL2_CHANNEL_MDMA", 0x118, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(glbl2_channel_mdma_field_info), - glbl2_channel_mdma_field_info -}, -{"GLBL2_CHANNEL_STRM", 0x11c, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(glbl2_channel_strm_field_info), - glbl2_channel_strm_field_info -}, -{"GLBL2_CHANNEL_CAP", 0x120, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(glbl2_channel_cap_field_info), - glbl2_channel_cap_field_info -}, -{"GLBL2_CHANNEL_PASID_CAP", 0x128, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(glbl2_channel_pasid_cap_field_info), - glbl2_channel_pasid_cap_field_info -}, -{"GLBL2_SYSTEM_ID", 0x130, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(glbl2_system_id_field_info), - glbl2_system_id_field_info -}, -{"GLBL2_MISC_CAP", 0x134, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(glbl2_misc_cap_field_info), - glbl2_misc_cap_field_info -}, -{"GLBL2_DBG_PCIE_RQ0", 0x1b8, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(glbl2_dbg_pcie_rq0_field_info), - glbl2_dbg_pcie_rq0_field_info -}, -{"GLBL2_DBG_PCIE_RQ1", 0x1bc, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(glbl2_dbg_pcie_rq1_field_info), - glbl2_dbg_pcie_rq1_field_info -}, -{"GLBL2_DBG_AXIMM_WR0", 0x1c0, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(glbl2_dbg_aximm_wr0_field_info), - glbl2_dbg_aximm_wr0_field_info -}, -{"GLBL2_DBG_AXIMM_WR1", 0x1c4, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(glbl2_dbg_aximm_wr1_field_info), - glbl2_dbg_aximm_wr1_field_info -}, -{"GLBL2_DBG_AXIMM_RD0", 0x1c8, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(glbl2_dbg_aximm_rd0_field_info), - glbl2_dbg_aximm_rd0_field_info -}, -{"GLBL2_DBG_AXIMM_RD1", 0x1cc, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(glbl2_dbg_aximm_rd1_field_info), - glbl2_dbg_aximm_rd1_field_info -}, -{"GLBL2_DBG_FAB0", 0x1d0, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(glbl2_dbg_fab0_field_info), - glbl2_dbg_fab0_field_info -}, -{"GLBL2_DBG_FAB1", 0x1d4, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(glbl2_dbg_fab1_field_info), - glbl2_dbg_fab1_field_info -}, -{"GLBL2_DBG_MATCH_SEL", 0x1f4, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(glbl2_dbg_match_sel_field_info), - glbl2_dbg_match_sel_field_info -}, -{"GLBL2_DBG_MATCH_MSK", 0x1f8, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(glbl2_dbg_match_msk_field_info), - glbl2_dbg_match_msk_field_info -}, -{"GLBL2_DBG_MATCH_PAT", 0x1fc, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(glbl2_dbg_match_pat_field_info), - glbl2_dbg_match_pat_field_info -}, -{"GLBL_RNG_SZ_1", 0x204, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(glbl_rng_sz_1_field_info), - glbl_rng_sz_1_field_info -}, -{"GLBL_RNG_SZ_2", 0x208, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(glbl_rng_sz_2_field_info), - glbl_rng_sz_2_field_info -}, -{"GLBL_RNG_SZ_3", 0x20c, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(glbl_rng_sz_3_field_info), - glbl_rng_sz_3_field_info -}, -{"GLBL_RNG_SZ_4", 0x210, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(glbl_rng_sz_4_field_info), - glbl_rng_sz_4_field_info -}, -{"GLBL_RNG_SZ_5", 0x214, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(glbl_rng_sz_5_field_info), - glbl_rng_sz_5_field_info -}, -{"GLBL_RNG_SZ_6", 0x218, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(glbl_rng_sz_6_field_info), - glbl_rng_sz_6_field_info -}, -{"GLBL_RNG_SZ_7", 0x21c, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(glbl_rng_sz_7_field_info), - glbl_rng_sz_7_field_info -}, -{"GLBL_RNG_SZ_8", 0x220, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(glbl_rng_sz_8_field_info), - glbl_rng_sz_8_field_info -}, -{"GLBL_RNG_SZ_9", 0x224, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(glbl_rng_sz_9_field_info), - glbl_rng_sz_9_field_info -}, -{"GLBL_RNG_SZ_A", 0x228, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(glbl_rng_sz_a_field_info), - glbl_rng_sz_a_field_info -}, -{"GLBL_RNG_SZ_B", 0x22c, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(glbl_rng_sz_b_field_info), - glbl_rng_sz_b_field_info -}, -{"GLBL_RNG_SZ_C", 0x230, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(glbl_rng_sz_c_field_info), - glbl_rng_sz_c_field_info -}, -{"GLBL_RNG_SZ_D", 0x234, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(glbl_rng_sz_d_field_info), - glbl_rng_sz_d_field_info -}, -{"GLBL_RNG_SZ_E", 0x238, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(glbl_rng_sz_e_field_info), - glbl_rng_sz_e_field_info -}, -{"GLBL_RNG_SZ_F", 0x23c, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(glbl_rng_sz_f_field_info), - glbl_rng_sz_f_field_info -}, -{"GLBL_RNG_SZ_10", 0x240, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(glbl_rng_sz_10_field_info), - glbl_rng_sz_10_field_info -}, -{"GLBL_ERR_STAT", 0x248, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(glbl_err_stat_field_info), - glbl_err_stat_field_info -}, -{"GLBL_ERR_MASK", 0x24c, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(glbl_err_mask_field_info), - glbl_err_mask_field_info -}, -{"GLBL_DSC_CFG", 0x250, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(glbl_dsc_cfg_field_info), - glbl_dsc_cfg_field_info -}, -{"GLBL_DSC_ERR_STS", 0x254, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(glbl_dsc_err_sts_field_info), - glbl_dsc_err_sts_field_info -}, -{"GLBL_DSC_ERR_MSK", 0x258, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(glbl_dsc_err_msk_field_info), - glbl_dsc_err_msk_field_info -}, -{"GLBL_DSC_ERR_LOG0", 0x25c, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(glbl_dsc_err_log0_field_info), - glbl_dsc_err_log0_field_info -}, -{"GLBL_DSC_ERR_LOG1", 0x260, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(glbl_dsc_err_log1_field_info), - glbl_dsc_err_log1_field_info -}, -{"GLBL_TRQ_ERR_STS", 0x264, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(glbl_trq_err_sts_field_info), - glbl_trq_err_sts_field_info -}, -{"GLBL_TRQ_ERR_MSK", 0x268, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(glbl_trq_err_msk_field_info), - glbl_trq_err_msk_field_info -}, -{"GLBL_TRQ_ERR_LOG", 0x26c, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(glbl_trq_err_log_field_info), - glbl_trq_err_log_field_info -}, -{"GLBL_DSC_DBG_DAT0", 0x270, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(glbl_dsc_dbg_dat0_field_info), - glbl_dsc_dbg_dat0_field_info -}, -{"GLBL_DSC_DBG_DAT1", 0x274, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(glbl_dsc_dbg_dat1_field_info), - glbl_dsc_dbg_dat1_field_info -}, -{"GLBL_DSC_DBG_CTL", 0x278, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(glbl_dsc_dbg_ctl_field_info), - glbl_dsc_dbg_ctl_field_info -}, -{"GLBL_DSC_ERR_LOG2", 0x27c, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(glbl_dsc_err_log2_field_info), - glbl_dsc_err_log2_field_info -}, -{"GLBL_GLBL_INTERRUPT_CFG", 0x2c4, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(glbl_glbl_interrupt_cfg_field_info), - glbl_glbl_interrupt_cfg_field_info -}, -{"GLBL_VCH_HOST_PROFILE", 0x2c8, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(glbl_vch_host_profile_field_info), - glbl_vch_host_profile_field_info -}, -{"GLBL_BRIDGE_HOST_PROFILE", 0x308, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(glbl_bridge_host_profile_field_info), - glbl_bridge_host_profile_field_info -}, -{"AXIMM_IRQ_DEST_ADDR", 0x30c, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(aximm_irq_dest_addr_field_info), - aximm_irq_dest_addr_field_info -}, -{"FAB_ERR_LOG", 0x314, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(fab_err_log_field_info), - fab_err_log_field_info -}, -{"IND_CTXT_DATA", 0x804, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(ind_ctxt_data_field_info), - ind_ctxt_data_field_info -}, -{"IND_CTXT_MASK", 0x824, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(ind_ctxt_mask_field_info), - ind_ctxt_mask_field_info -}, -{"IND_CTXT_CMD", 0x844, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(ind_ctxt_cmd_field_info), - ind_ctxt_cmd_field_info -}, -{"C2H_TIMER_CNT", 0xa00, - 1, 0, 0, 0, - 0, QDMA_COMPLETION_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_timer_cnt_field_info), - c2h_timer_cnt_field_info -}, -{"C2H_CNT_TH", 0xa40, - 1, 0, 0, 0, - 0, QDMA_COMPLETION_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_cnt_th_field_info), - c2h_cnt_th_field_info -}, -{"C2H_STAT_S_AXIS_C2H_ACCEPTED", 0xa88, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(c2h_stat_s_axis_c2h_accepted_field_info), - c2h_stat_s_axis_c2h_accepted_field_info -}, -{"C2H_STAT_S_AXIS_WRB_ACCEPTED", 0xa8c, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(c2h_stat_s_axis_wrb_accepted_field_info), - c2h_stat_s_axis_wrb_accepted_field_info -}, -{"C2H_STAT_DESC_RSP_PKT_ACCEPTED", 0xa90, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(c2h_stat_desc_rsp_pkt_accepted_field_info), - c2h_stat_desc_rsp_pkt_accepted_field_info -}, -{"C2H_STAT_AXIS_PKG_CMP", 0xa94, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(c2h_stat_axis_pkg_cmp_field_info), - c2h_stat_axis_pkg_cmp_field_info -}, -{"C2H_STAT_DESC_RSP_ACCEPTED", 0xa98, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_stat_desc_rsp_accepted_field_info), - c2h_stat_desc_rsp_accepted_field_info -}, -{"C2H_STAT_DESC_RSP_CMP", 0xa9c, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_stat_desc_rsp_cmp_field_info), - c2h_stat_desc_rsp_cmp_field_info -}, -{"C2H_STAT_WRQ_OUT", 0xaa0, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_stat_wrq_out_field_info), - c2h_stat_wrq_out_field_info -}, -{"C2H_STAT_WPL_REN_ACCEPTED", 0xaa4, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_stat_wpl_ren_accepted_field_info), - c2h_stat_wpl_ren_accepted_field_info -}, -{"C2H_STAT_TOTAL_WRQ_LEN", 0xaa8, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_stat_total_wrq_len_field_info), - c2h_stat_total_wrq_len_field_info -}, -{"C2H_STAT_TOTAL_WPL_LEN", 0xaac, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_stat_total_wpl_len_field_info), - c2h_stat_total_wpl_len_field_info -}, -{"C2H_BUF_SZ", 0xab0, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_buf_sz_field_info), - c2h_buf_sz_field_info -}, -{"C2H_ERR_STAT", 0xaf0, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(c2h_err_stat_field_info), - c2h_err_stat_field_info -}, -{"C2H_ERR_MASK", 0xaf4, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(c2h_err_mask_field_info), - c2h_err_mask_field_info -}, -{"C2H_FATAL_ERR_STAT", 0xaf8, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(c2h_fatal_err_stat_field_info), - c2h_fatal_err_stat_field_info -}, -{"C2H_FATAL_ERR_MASK", 0xafc, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(c2h_fatal_err_mask_field_info), - c2h_fatal_err_mask_field_info -}, -{"C2H_FATAL_ERR_ENABLE", 0xb00, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(c2h_fatal_err_enable_field_info), - c2h_fatal_err_enable_field_info -}, -{"GLBL_ERR_INT", 0xb04, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(glbl_err_int_field_info), - glbl_err_int_field_info -}, -{"C2H_PFCH_CFG", 0xb08, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_pfch_cfg_field_info), - c2h_pfch_cfg_field_info -}, -{"C2H_PFCH_CFG_1", 0xa80, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(c2h_pfch_cfg_1_field_info), - c2h_pfch_cfg_1_field_info -}, -{"C2H_PFCH_CFG_2", 0xa84, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(c2h_pfch_cfg_2_field_info), - c2h_pfch_cfg_2_field_info -}, -{"C2H_INT_TIMER_TICK", 0xb0c, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_int_timer_tick_field_info), - c2h_int_timer_tick_field_info -}, -{"C2H_STAT_DESC_RSP_DROP_ACCEPTED", 0xb10, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(c2h_stat_desc_rsp_drop_accepted_field_info), - c2h_stat_desc_rsp_drop_accepted_field_info -}, -{"C2H_STAT_DESC_RSP_ERR_ACCEPTED", 0xb14, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(c2h_stat_desc_rsp_err_accepted_field_info), - c2h_stat_desc_rsp_err_accepted_field_info -}, -{"C2H_STAT_DESC_REQ", 0xb18, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_stat_desc_req_field_info), - c2h_stat_desc_req_field_info -}, -{"C2H_STAT_DBG_DMA_ENG_0", 0xb1c, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_stat_dbg_dma_eng_0_field_info), - c2h_stat_dbg_dma_eng_0_field_info -}, -{"C2H_STAT_DBG_DMA_ENG_1", 0xb20, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_stat_dbg_dma_eng_1_field_info), - c2h_stat_dbg_dma_eng_1_field_info -}, -{"C2H_STAT_DBG_DMA_ENG_2", 0xb24, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_stat_dbg_dma_eng_2_field_info), - c2h_stat_dbg_dma_eng_2_field_info -}, -{"C2H_STAT_DBG_DMA_ENG_3", 0xb28, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_stat_dbg_dma_eng_3_field_info), - c2h_stat_dbg_dma_eng_3_field_info -}, -{"C2H_DBG_PFCH_ERR_CTXT", 0xb2c, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_dbg_pfch_err_ctxt_field_info), - c2h_dbg_pfch_err_ctxt_field_info -}, -{"C2H_FIRST_ERR_QID", 0xb30, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(c2h_first_err_qid_field_info), - c2h_first_err_qid_field_info -}, -{"STAT_NUM_WRB_IN", 0xb34, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(stat_num_wrb_in_field_info), - stat_num_wrb_in_field_info -}, -{"STAT_NUM_WRB_OUT", 0xb38, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(stat_num_wrb_out_field_info), - stat_num_wrb_out_field_info -}, -{"STAT_NUM_WRB_DRP", 0xb3c, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(stat_num_wrb_drp_field_info), - stat_num_wrb_drp_field_info -}, -{"STAT_NUM_STAT_DESC_OUT", 0xb40, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(stat_num_stat_desc_out_field_info), - stat_num_stat_desc_out_field_info -}, -{"STAT_NUM_DSC_CRDT_SENT", 0xb44, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(stat_num_dsc_crdt_sent_field_info), - stat_num_dsc_crdt_sent_field_info -}, -{"STAT_NUM_FCH_DSC_RCVD", 0xb48, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(stat_num_fch_dsc_rcvd_field_info), - stat_num_fch_dsc_rcvd_field_info -}, -{"STAT_NUM_BYP_DSC_RCVD", 0xb4c, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(stat_num_byp_dsc_rcvd_field_info), - stat_num_byp_dsc_rcvd_field_info -}, -{"C2H_WRB_COAL_CFG", 0xb50, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_wrb_coal_cfg_field_info), - c2h_wrb_coal_cfg_field_info -}, -{"C2H_INTR_H2C_REQ", 0xb54, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(c2h_intr_h2c_req_field_info), - c2h_intr_h2c_req_field_info -}, -{"C2H_INTR_C2H_MM_REQ", 0xb58, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(c2h_intr_c2h_mm_req_field_info), - c2h_intr_c2h_mm_req_field_info -}, -{"C2H_INTR_ERR_INT_REQ", 0xb5c, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(c2h_intr_err_int_req_field_info), - c2h_intr_err_int_req_field_info -}, -{"C2H_INTR_C2H_ST_REQ", 0xb60, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(c2h_intr_c2h_st_req_field_info), - c2h_intr_c2h_st_req_field_info -}, -{"C2H_INTR_H2C_ERR_C2H_MM_MSIX_ACK", 0xb64, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_intr_h2c_err_c2h_mm_msix_ack_field_info), - c2h_intr_h2c_err_c2h_mm_msix_ack_field_info -}, -{"C2H_INTR_H2C_ERR_C2H_MM_MSIX_FAIL", 0xb68, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_intr_h2c_err_c2h_mm_msix_fail_field_info), - c2h_intr_h2c_err_c2h_mm_msix_fail_field_info -}, -{"C2H_INTR_H2C_ERR_C2H_MM_MSIX_NO_MSIX", 0xb6c, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_intr_h2c_err_c2h_mm_msix_no_msix_field_info), - c2h_intr_h2c_err_c2h_mm_msix_no_msix_field_info -}, -{"C2H_INTR_H2C_ERR_C2H_MM_CTXT_INVAL", 0xb70, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_intr_h2c_err_c2h_mm_ctxt_inval_field_info), - c2h_intr_h2c_err_c2h_mm_ctxt_inval_field_info -}, -{"C2H_INTR_C2H_ST_MSIX_ACK", 0xb74, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(c2h_intr_c2h_st_msix_ack_field_info), - c2h_intr_c2h_st_msix_ack_field_info -}, -{"C2H_INTR_C2H_ST_MSIX_FAIL", 0xb78, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(c2h_intr_c2h_st_msix_fail_field_info), - c2h_intr_c2h_st_msix_fail_field_info -}, -{"C2H_INTR_C2H_ST_NO_MSIX", 0xb7c, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_intr_c2h_st_no_msix_field_info), - c2h_intr_c2h_st_no_msix_field_info -}, -{"C2H_INTR_C2H_ST_CTXT_INVAL", 0xb80, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_intr_c2h_st_ctxt_inval_field_info), - c2h_intr_c2h_st_ctxt_inval_field_info -}, -{"C2H_STAT_WR_CMP", 0xb84, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_stat_wr_cmp_field_info), - c2h_stat_wr_cmp_field_info -}, -{"C2H_STAT_DBG_DMA_ENG_4", 0xb88, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_stat_dbg_dma_eng_4_field_info), - c2h_stat_dbg_dma_eng_4_field_info -}, -{"C2H_STAT_DBG_DMA_ENG_5", 0xb8c, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_stat_dbg_dma_eng_5_field_info), - c2h_stat_dbg_dma_eng_5_field_info -}, -{"C2H_DBG_PFCH_QID", 0xb90, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_dbg_pfch_qid_field_info), - c2h_dbg_pfch_qid_field_info -}, -{"C2H_DBG_PFCH", 0xb94, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_dbg_pfch_field_info), - c2h_dbg_pfch_field_info -}, -{"C2H_INT_DBG", 0xb98, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_int_dbg_field_info), - c2h_int_dbg_field_info -}, -{"C2H_STAT_IMM_ACCEPTED", 0xb9c, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_stat_imm_accepted_field_info), - c2h_stat_imm_accepted_field_info -}, -{"C2H_STAT_MARKER_ACCEPTED", 0xba0, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_stat_marker_accepted_field_info), - c2h_stat_marker_accepted_field_info -}, -{"C2H_STAT_DISABLE_CMP_ACCEPTED", 0xba4, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_stat_disable_cmp_accepted_field_info), - c2h_stat_disable_cmp_accepted_field_info -}, -{"C2H_PLD_FIFO_CRDT_CNT", 0xba8, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_pld_fifo_crdt_cnt_field_info), - c2h_pld_fifo_crdt_cnt_field_info -}, -{"C2H_INTR_DYN_REQ", 0xbac, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_intr_dyn_req_field_info), - c2h_intr_dyn_req_field_info -}, -{"C2H_INTR_DYN_MISC", 0xbb0, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_intr_dyn_misc_field_info), - c2h_intr_dyn_misc_field_info -}, -{"C2H_DROP_LEN_MISMATCH", 0xbb4, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_drop_len_mismatch_field_info), - c2h_drop_len_mismatch_field_info -}, -{"C2H_DROP_DESC_RSP_LEN", 0xbb8, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_drop_desc_rsp_len_field_info), - c2h_drop_desc_rsp_len_field_info -}, -{"C2H_DROP_QID_FIFO_LEN", 0xbbc, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_drop_qid_fifo_len_field_info), - c2h_drop_qid_fifo_len_field_info -}, -{"C2H_DROP_PLD_CNT", 0xbc0, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_drop_pld_cnt_field_info), - c2h_drop_pld_cnt_field_info -}, -{"C2H_CMPT_FORMAT_0", 0xbc4, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_cmpt_format_0_field_info), - c2h_cmpt_format_0_field_info -}, -{"C2H_CMPT_FORMAT_1", 0xbc8, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_cmpt_format_1_field_info), - c2h_cmpt_format_1_field_info -}, -{"C2H_CMPT_FORMAT_2", 0xbcc, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_cmpt_format_2_field_info), - c2h_cmpt_format_2_field_info -}, -{"C2H_CMPT_FORMAT_3", 0xbd0, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_cmpt_format_3_field_info), - c2h_cmpt_format_3_field_info -}, -{"C2H_CMPT_FORMAT_4", 0xbd4, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_cmpt_format_4_field_info), - c2h_cmpt_format_4_field_info -}, -{"C2H_CMPT_FORMAT_5", 0xbd8, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_cmpt_format_5_field_info), - c2h_cmpt_format_5_field_info -}, -{"C2H_CMPT_FORMAT_6", 0xbdc, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_cmpt_format_6_field_info), - c2h_cmpt_format_6_field_info -}, -{"C2H_PFCH_CACHE_DEPTH", 0xbe0, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_pfch_cache_depth_field_info), - c2h_pfch_cache_depth_field_info -}, -{"C2H_WRB_COAL_BUF_DEPTH", 0xbe4, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_wrb_coal_buf_depth_field_info), - c2h_wrb_coal_buf_depth_field_info -}, -{"C2H_PFCH_CRDT", 0xbe8, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_pfch_crdt_field_info), - c2h_pfch_crdt_field_info -}, -{"C2H_STAT_HAS_CMPT_ACCEPTED", 0xbec, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_stat_has_cmpt_accepted_field_info), - c2h_stat_has_cmpt_accepted_field_info -}, -{"C2H_STAT_HAS_PLD_ACCEPTED", 0xbf0, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_stat_has_pld_accepted_field_info), - c2h_stat_has_pld_accepted_field_info -}, -{"C2H_PLD_PKT_ID", 0xbf4, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_pld_pkt_id_field_info), - c2h_pld_pkt_id_field_info -}, -{"C2H_PLD_PKT_ID_1", 0xbf8, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_pld_pkt_id_1_field_info), - c2h_pld_pkt_id_1_field_info -}, -{"C2H_DROP_PLD_CNT_1", 0xbfc, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_drop_pld_cnt_1_field_info), - c2h_drop_pld_cnt_1_field_info -}, -{"H2C_ERR_STAT", 0xe00, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(h2c_err_stat_field_info), - h2c_err_stat_field_info -}, -{"H2C_ERR_MASK", 0xe04, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(h2c_err_mask_field_info), - h2c_err_mask_field_info -}, -{"H2C_FIRST_ERR_QID", 0xe08, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(h2c_first_err_qid_field_info), - h2c_first_err_qid_field_info -}, -{"H2C_DBG_REG0", 0xe0c, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(h2c_dbg_reg0_field_info), - h2c_dbg_reg0_field_info -}, -{"H2C_DBG_REG1", 0xe10, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(h2c_dbg_reg1_field_info), - h2c_dbg_reg1_field_info -}, -{"H2C_DBG_REG2", 0xe14, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(h2c_dbg_reg2_field_info), - h2c_dbg_reg2_field_info -}, -{"H2C_DBG_REG3", 0xe18, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(h2c_dbg_reg3_field_info), - h2c_dbg_reg3_field_info -}, -{"H2C_DBG_REG4", 0xe1c, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(h2c_dbg_reg4_field_info), - h2c_dbg_reg4_field_info -}, -{"H2C_FATAL_ERR_EN", 0xe20, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(h2c_fatal_err_en_field_info), - h2c_fatal_err_en_field_info -}, -{"H2C_REQ_THROT_PCIE", 0xe24, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(h2c_req_throt_pcie_field_info), - h2c_req_throt_pcie_field_info -}, -{"H2C_ALN_DBG_REG0", 0xe28, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(h2c_aln_dbg_reg0_field_info), - h2c_aln_dbg_reg0_field_info -}, -{"H2C_REQ_THROT_AXIMM", 0xe2c, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(h2c_req_throt_aximm_field_info), - h2c_req_throt_aximm_field_info -}, -{"C2H_MM_CTL", 0x1004, - 1, 0, 0, 0, - 0, QDMA_MM_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_mm_ctl_field_info), - c2h_mm_ctl_field_info -}, -{"C2H_MM_STATUS", 0x1040, - 1, 0, 0, 0, - 0, QDMA_MM_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_mm_status_field_info), - c2h_mm_status_field_info -}, -{"C2H_MM_CMPL_DESC_CNT", 0x1048, - 1, 0, 0, 0, - 0, QDMA_MM_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_mm_cmpl_desc_cnt_field_info), - c2h_mm_cmpl_desc_cnt_field_info -}, -{"C2H_MM_ERR_CODE_ENABLE_MASK", 0x1054, - 1, 0, 0, 0, - 0, QDMA_MM_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_mm_err_code_enable_mask_field_info), - c2h_mm_err_code_enable_mask_field_info -}, -{"C2H_MM_ERR_CODE", 0x1058, - 1, 0, 0, 0, - 0, QDMA_MM_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_mm_err_code_field_info), - c2h_mm_err_code_field_info -}, -{"C2H_MM_ERR_INFO", 0x105c, - 1, 0, 0, 0, - 0, QDMA_MM_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_mm_err_info_field_info), - c2h_mm_err_info_field_info -}, -{"C2H_MM_PERF_MON_CTL", 0x10c0, - 1, 0, 0, 0, - 0, QDMA_MM_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_mm_perf_mon_ctl_field_info), - c2h_mm_perf_mon_ctl_field_info -}, -{"C2H_MM_PERF_MON_CYCLE_CNT0", 0x10c4, - 1, 0, 0, 0, - 0, QDMA_MM_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_mm_perf_mon_cycle_cnt0_field_info), - c2h_mm_perf_mon_cycle_cnt0_field_info -}, -{"C2H_MM_PERF_MON_CYCLE_CNT1", 0x10c8, - 1, 0, 0, 0, - 0, QDMA_MM_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_mm_perf_mon_cycle_cnt1_field_info), - c2h_mm_perf_mon_cycle_cnt1_field_info -}, -{"C2H_MM_PERF_MON_DATA_CNT0", 0x10cc, - 1, 0, 0, 0, - 0, QDMA_MM_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_mm_perf_mon_data_cnt0_field_info), - c2h_mm_perf_mon_data_cnt0_field_info -}, -{"C2H_MM_PERF_MON_DATA_CNT1", 0x10d0, - 1, 0, 0, 0, - 0, QDMA_MM_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_mm_perf_mon_data_cnt1_field_info), - c2h_mm_perf_mon_data_cnt1_field_info -}, -{"C2H_MM_DBG", 0x10e8, - 1, 0, 0, 0, - 0, QDMA_MM_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_mm_dbg_field_info), - c2h_mm_dbg_field_info -}, -{"H2C_MM_CTL", 0x1204, - 1, 0, 0, 0, - 0, QDMA_MM_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(h2c_mm_ctl_field_info), - h2c_mm_ctl_field_info -}, -{"H2C_MM_STATUS", 0x1240, - 1, 0, 0, 0, - 0, QDMA_MM_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(h2c_mm_status_field_info), - h2c_mm_status_field_info -}, -{"H2C_MM_CMPL_DESC_CNT", 0x1248, - 1, 0, 0, 0, - 0, QDMA_MM_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(h2c_mm_cmpl_desc_cnt_field_info), - h2c_mm_cmpl_desc_cnt_field_info -}, -{"H2C_MM_ERR_CODE_ENABLE_MASK", 0x1254, - 1, 0, 0, 0, - 0, QDMA_MM_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(h2c_mm_err_code_enable_mask_field_info), - h2c_mm_err_code_enable_mask_field_info -}, -{"H2C_MM_ERR_CODE", 0x1258, - 1, 0, 0, 0, - 0, QDMA_MM_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(h2c_mm_err_code_field_info), - h2c_mm_err_code_field_info -}, -{"H2C_MM_ERR_INFO", 0x125c, - 1, 0, 0, 0, - 0, QDMA_MM_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(h2c_mm_err_info_field_info), - h2c_mm_err_info_field_info -}, -{"H2C_MM_PERF_MON_CTL", 0x12c0, - 1, 0, 0, 0, - 0, QDMA_MM_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(h2c_mm_perf_mon_ctl_field_info), - h2c_mm_perf_mon_ctl_field_info -}, -{"H2C_MM_PERF_MON_CYCLE_CNT0", 0x12c4, - 1, 0, 0, 0, - 0, QDMA_MM_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(h2c_mm_perf_mon_cycle_cnt0_field_info), - h2c_mm_perf_mon_cycle_cnt0_field_info -}, -{"H2C_MM_PERF_MON_CYCLE_CNT1", 0x12c8, - 1, 0, 0, 0, - 0, QDMA_MM_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(h2c_mm_perf_mon_cycle_cnt1_field_info), - h2c_mm_perf_mon_cycle_cnt1_field_info -}, -{"H2C_MM_PERF_MON_DATA_CNT0", 0x12cc, - 1, 0, 0, 0, - 0, QDMA_MM_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(h2c_mm_perf_mon_data_cnt0_field_info), - h2c_mm_perf_mon_data_cnt0_field_info -}, -{"H2C_MM_PERF_MON_DATA_CNT1", 0x12d0, - 1, 0, 0, 0, - 0, QDMA_MM_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(h2c_mm_perf_mon_data_cnt1_field_info), - h2c_mm_perf_mon_data_cnt1_field_info -}, -{"H2C_MM_DBG", 0x12e8, - 1, 0, 0, 0, - 0, QDMA_MM_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(h2c_mm_dbg_field_info), - h2c_mm_dbg_field_info -}, -{"C2H_CRDT_COAL_CFG_1", 0x1400, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_crdt_coal_cfg_1_field_info), - c2h_crdt_coal_cfg_1_field_info -}, -{"C2H_CRDT_COAL_CFG_2", 0x1404, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_crdt_coal_cfg_2_field_info), - c2h_crdt_coal_cfg_2_field_info -}, -{"C2H_PFCH_BYP_QID", 0x1408, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_pfch_byp_qid_field_info), - c2h_pfch_byp_qid_field_info -}, -{"C2H_PFCH_BYP_TAG", 0x140c, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_pfch_byp_tag_field_info), - c2h_pfch_byp_tag_field_info -}, -{"C2H_WATER_MARK", 0x1500, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_water_mark_field_info), - c2h_water_mark_field_info -}, -{"C2H_NOTIFY_EMPTY", 0x1800, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_notify_empty_field_info), - c2h_notify_empty_field_info -}, -{"C2H_STAT_S_AXIS_C2H_ACCEPTED_1", 0x1804, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_stat_s_axis_c2h_accepted_1_field_info), - c2h_stat_s_axis_c2h_accepted_1_field_info -}, -{"C2H_STAT_S_AXIS_WRB_ACCEPTED_1", 0x1808, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_stat_s_axis_wrb_accepted_1_field_info), - c2h_stat_s_axis_wrb_accepted_1_field_info -}, -{"C2H_STAT_DESC_RSP_PKT_ACCEPTED_1", 0x180c, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_stat_desc_rsp_pkt_accepted_1_field_info), - c2h_stat_desc_rsp_pkt_accepted_1_field_info -}, -{"C2H_STAT_AXIS_PKG_CMP_1", 0x1810, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_stat_axis_pkg_cmp_1_field_info), - c2h_stat_axis_pkg_cmp_1_field_info -}, -{"C2H_STAT_S_AXIS_WRB_ACCEPTED_2", 0x1814, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_stat_s_axis_wrb_accepted_2_field_info), - c2h_stat_s_axis_wrb_accepted_2_field_info -}, -{"C2H_ST_PLD_FIFO_DEPTH", 0x1818, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_st_pld_fifo_depth_field_info), - c2h_st_pld_fifo_depth_field_info -}, - -}; - -uint32_t eqdma_cpm5_config_num_regs_get(void) -{ - return (sizeof(eqdma_cpm5_config_regs)/ - sizeof(eqdma_cpm5_config_regs[0])); -} - -struct xreg_info *eqdma_cpm5_config_regs_get(void) -{ - return eqdma_cpm5_config_regs; -} - diff --git a/QDMA/DPDK/drivers/net/qdma/qdma_access/eqdma_soft_access/eqdma_soft_access.c b/QDMA/DPDK/drivers/net/qdma/qdma_access/eqdma_soft_access/eqdma_soft_access.c deleted file mode 100755 index 03324799e..000000000 --- a/QDMA/DPDK/drivers/net/qdma/qdma_access/eqdma_soft_access/eqdma_soft_access.c +++ /dev/null @@ -1,6833 +0,0 @@ -/* - * Copyright (c) 2019-2022, Xilinx, Inc. All rights reserved. - * Copyright (c) 2022, Advanced Micro Devices, Inc. All rights reserved. - * - * BSD LICENSE - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * * Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include "eqdma_soft_access.h" -#include "eqdma_soft_reg.h" -#include "qdma_reg_dump.h" - -#ifdef ENABLE_WPP_TRACING -#include "eqdma_soft_access.tmh" -#endif - -/** EQDMA Context array size */ -#define EQDMA_FMAP_NUM_WORDS 2 -#define EQDMA_SW_CONTEXT_NUM_WORDS 8 -#define EQDMA_HW_CONTEXT_NUM_WORDS 2 -#define EQDMA_PFETCH_CONTEXT_NUM_WORDS 2 -#define EQDMA_CR_CONTEXT_NUM_WORDS 1 -#define EQDMA_CMPT_CONTEXT_NUM_WORDS 6 -#define EQDMA_IND_INTR_CONTEXT_NUM_WORDS 4 - -#define EQDMA_VF_USER_BAR_ID 2 - -#define EQDMA_REG_GROUP_1_START_ADDR 0x000 -#define EQDMA_REG_GROUP_2_START_ADDR 0x804 -#define EQDMA_REG_GROUP_3_START_ADDR 0xB00 -#define EQDMA_REG_GROUP_4_START_ADDR 0x5014 - -#define EQDMA_TOTAL_LEAF_ERROR_AGGREGATORS 11 -#define EQDMA_GLBL_TRQ_ERR_ALL_MASK 0XB3 -#define EQDMA_GLBL_DSC_ERR_ALL_MASK 0X1F9037E -#define EQDMA_C2H_ERR_ALL_MASK 0X3F6DF -#define EQDMA_C2H_FATAL_ERR_ALL_MASK 0X1FDF1B -#define EQDMA_H2C_ERR_ALL_MASK 0X3F -#define EQDMA_SBE_ERR_ALL_MASK 0XFFFFFFFF -#define EQDMA_DBE_ERR_ALL_MASK 0XFFFFFFFF -#define EQDMA_MM_C2H_ERR_ALL_MASK 0X70000003 -#define EQDMA_MM_H2C0_ERR_ALL_MASK 0X3041013E - - - - -/* H2C Throttle settings for QDMA 4.0 */ -#define EQDMA_H2C_THROT_DATA_THRESH 0x5000 -#define EQDMA_THROT_EN_DATA 1 -#define EQDMA_THROT_EN_REQ 0 -#define EQDMA_H2C_THROT_REQ_THRESH 0xC0 - -/* H2C Throttle settings for QDMA 5.0 */ -#define EQDMA5_H2C_THROT_DATA_THRESH 0x5000 -#define EQDMA5_THROT_EN_DATA 1 -#define EQDMA5_THROT_EN_REQ 1 -#define EQDMA5_H2C_THROT_REQ_THRESH 0xC0 - -/* CSR Default values for QDMA 5.0 */ -#define EQDMA5_DEFAULT_C2H_UODSC_LIMIT 5 -#define EQDMA5_DEFAULT_H2C_UODSC_LIMIT 8 -#define EQDMA5_DEFAULT_MAX_DSC_FETCH 5 -#define EQDMA5_DEFAULT_WRB_INT QDMA_WRB_INTERVAL_128 - -/* C2H prefetch Throttle configuration. */ -#define EQDMA5_DEFAULT_C2H_EVT_QCNT_TH 0x38 -#define EQDMA5_DEFAULT_C2H_PFCH_QCNT 0x3c - -/** Auxillary Bitmasks for fields spanning multiple words */ -#define EQDMA_SW_CTXT_PASID_GET_H_MASK GENMASK(21, 12) -#define EQDMA_SW_CTXT_PASID_GET_L_MASK GENMASK(11, 0) -#define EQDMA_SW_CTXT_VIRTIO_DSC_BASE_GET_H_MASK GENMASK_ULL(63, 53) -#define EQDMA_SW_CTXT_VIRTIO_DSC_BASE_GET_M_MASK GENMASK_ULL(52, 21) -#define EQDMA_SW_CTXT_VIRTIO_DSC_BASE_GET_L_MASK GENMASK_ULL(20, 0) -#define EQDMA_CMPL_CTXT_PASID_GET_H_MASK GENMASK(21, 9) -#define EQDMA_CMPL_CTXT_PASID_GET_L_MASK GENMASK(8, 0) -#define EQDMA_INTR_CTXT_PASID_GET_H_MASK GENMASK(21, 9) -#define EQDMA_INTR_CTXT_PASID_GET_L_MASK GENMASK(8, 0) - - -#define EQDMA_OFFSET_GLBL2_PF_BARLITE_EXT 0x10C - -#define QDMA_OFFSET_GLBL2_PF_BARLITE_INT 0x104 -#define QDMA_GLBL2_PF3_BAR_MAP_MASK GENMASK(23, 18) -#define QDMA_GLBL2_PF2_BAR_MAP_MASK GENMASK(17, 12) -#define QDMA_GLBL2_PF1_BAR_MAP_MASK GENMASK(11, 6) -#define QDMA_GLBL2_PF0_BAR_MAP_MASK GENMASK(5, 0) - -#define EQDMA_GLBL2_DBG_MODE_EN_MASK BIT(4) -#define EQDMA_GLBL2_DESC_ENG_MODE_MASK GENMASK(3, 2) -#define EQDMA_GLBL2_FLR_PRESENT_MASK BIT(1) -#define EQDMA_GLBL2_MAILBOX_EN_MASK BIT(0) - -/** EQDMA_IND_REG_SEL_FMAP */ -#define EQDMA_FMAP_CTXT_W1_QID_MAX_MASK GENMASK(11, 0) -#define EQDMA_FMAP_CTXT_W0_QID_MASK GENMASK(10, 0) - -#define EQDMA_GLBL2_IP_VERSION_MASK GENMASK(23, 20) -#define EQDMA_GLBL2_VF_IP_VERSION_MASK GENMASK(7, 4) - -static void eqdma_hw_st_h2c_err_process(void *dev_hndl); -static void eqdma_hw_st_c2h_err_process(void *dev_hndl); -static void eqdma_hw_desc_err_process(void *dev_hndl); -static void eqdma_hw_trq_err_process(void *dev_hndl); -static void eqdma_hw_ram_sbe_err_process(void *dev_hndl); -static void eqdma_hw_ram_dbe_err_process(void *dev_hndl); -static void eqdma_mm_h2c0_err_process(void *dev_hndl); -static void eqdma_mm_c2h0_err_process(void *dev_hndl); - -static struct eqdma_hw_err_info eqdma_err_info[EQDMA_ERRS_ALL] = { - /* Descriptor errors */ - { - EQDMA_DSC_ERR_POISON, - "Poison error", - EQDMA_GLBL_DSC_ERR_MSK_ADDR, - EQDMA_GLBL_DSC_ERR_STS_ADDR, - GLBL_DSC_ERR_STS_POISON_MASK, - GLBL_ERR_STAT_ERR_DSC_MASK, - &eqdma_hw_desc_err_process - }, - { - EQDMA_DSC_ERR_UR_CA, - "Unsupported request or completer aborted error", - EQDMA_GLBL_DSC_ERR_MSK_ADDR, - EQDMA_GLBL_DSC_ERR_STS_ADDR, - GLBL_DSC_ERR_STS_UR_CA_MASK, - GLBL_ERR_STAT_ERR_DSC_MASK, - &eqdma_hw_desc_err_process - }, - { - EQDMA_DSC_ERR_BCNT, - "Unexpected Byte count in completion error", - EQDMA_GLBL_DSC_ERR_MSK_ADDR, - EQDMA_GLBL_DSC_ERR_STS_ADDR, - GLBL_DSC_ERR_STS_BCNT_MASK, - GLBL_ERR_STAT_ERR_DSC_MASK, - &eqdma_hw_desc_err_process - }, - { - EQDMA_DSC_ERR_PARAM, - "Parameter mismatch error", - EQDMA_GLBL_DSC_ERR_MSK_ADDR, - EQDMA_GLBL_DSC_ERR_STS_ADDR, - GLBL_DSC_ERR_STS_PARAM_MASK, - GLBL_ERR_STAT_ERR_DSC_MASK, - &eqdma_hw_desc_err_process - }, - { - EQDMA_DSC_ERR_ADDR, - "Address mismatch error", - EQDMA_GLBL_DSC_ERR_MSK_ADDR, - EQDMA_GLBL_DSC_ERR_STS_ADDR, - GLBL_DSC_ERR_STS_ADDR_MASK, - GLBL_ERR_STAT_ERR_DSC_MASK, - &eqdma_hw_desc_err_process - }, - { - EQDMA_DSC_ERR_TAG, - "Unexpected tag error", - EQDMA_GLBL_DSC_ERR_MSK_ADDR, - EQDMA_GLBL_DSC_ERR_STS_ADDR, - GLBL_DSC_ERR_STS_TAG_MASK, - GLBL_ERR_STAT_ERR_DSC_MASK, - &eqdma_hw_desc_err_process - }, - { - EQDMA_DSC_ERR_FLR, - "FLR error", - EQDMA_GLBL_DSC_ERR_MSK_ADDR, - EQDMA_GLBL_DSC_ERR_STS_ADDR, - GLBL_DSC_ERR_STS_FLR_MASK, - GLBL_ERR_STAT_ERR_DSC_MASK, - &eqdma_hw_desc_err_process - }, - { - EQDMA_DSC_ERR_TIMEOUT, - "Timed out error", - EQDMA_GLBL_DSC_ERR_MSK_ADDR, - EQDMA_GLBL_DSC_ERR_STS_ADDR, - GLBL_DSC_ERR_STS_TIMEOUT_MASK, - GLBL_ERR_STAT_ERR_DSC_MASK, - &eqdma_hw_desc_err_process - }, - { - EQDMA_DSC_ERR_DAT_POISON, - "Poison data error", - EQDMA_GLBL_DSC_ERR_MSK_ADDR, - EQDMA_GLBL_DSC_ERR_STS_ADDR, - GLBL_DSC_ERR_STS_DAT_POISON_MASK, - GLBL_ERR_STAT_ERR_DSC_MASK, - &eqdma_hw_desc_err_process - }, - { - EQDMA_DSC_ERR_FLR_CANCEL, - "Descriptor fetch cancelled due to FLR error", - EQDMA_GLBL_DSC_ERR_MSK_ADDR, - EQDMA_GLBL_DSC_ERR_STS_ADDR, - GLBL_DSC_ERR_STS_FLR_CANCEL_MASK, - GLBL_ERR_STAT_ERR_DSC_MASK, - &eqdma_hw_desc_err_process - }, - { - EQDMA_DSC_ERR_DMA, - "DMA engine error", - EQDMA_GLBL_DSC_ERR_MSK_ADDR, - EQDMA_GLBL_DSC_ERR_STS_ADDR, - GLBL_DSC_ERR_STS_DMA_MASK, - GLBL_ERR_STAT_ERR_DSC_MASK, - &eqdma_hw_desc_err_process - }, - { - EQDMA_DSC_ERR_DSC, - "Invalid PIDX update error", - EQDMA_GLBL_DSC_ERR_MSK_ADDR, - EQDMA_GLBL_DSC_ERR_STS_ADDR, - GLBL_DSC_ERR_STS_DSC_MASK, - GLBL_ERR_STAT_ERR_DSC_MASK, - &eqdma_hw_desc_err_process - }, - { - EQDMA_DSC_ERR_RQ_CANCEL, - "Descriptor fetch cancelled due to disable register status error", - EQDMA_GLBL_DSC_ERR_MSK_ADDR, - EQDMA_GLBL_DSC_ERR_STS_ADDR, - GLBL_DSC_ERR_STS_RQ_CANCEL_MASK, - GLBL_ERR_STAT_ERR_DSC_MASK, - &eqdma_hw_desc_err_process - }, - { - EQDMA_DSC_ERR_DBE, - "UNC_ERR_RAM_DBE error", - EQDMA_GLBL_DSC_ERR_MSK_ADDR, - EQDMA_GLBL_DSC_ERR_STS_ADDR, - GLBL_DSC_ERR_STS_DBE_MASK, - GLBL_ERR_STAT_ERR_DSC_MASK, - &eqdma_hw_desc_err_process - }, - { - EQDMA_DSC_ERR_SBE, - "UNC_ERR_RAM_SBE error", - EQDMA_GLBL_DSC_ERR_MSK_ADDR, - EQDMA_GLBL_DSC_ERR_STS_ADDR, - GLBL_DSC_ERR_STS_SBE_MASK, - GLBL_ERR_STAT_ERR_DSC_MASK, - &eqdma_hw_desc_err_process - }, - { - EQDMA_DSC_ERR_PORT_ID, - "Port ID Error", - EQDMA_GLBL_DSC_ERR_MSK_ADDR, - EQDMA_GLBL_DSC_ERR_STS_ADDR, - GLBL_DSC_ERR_STS_PORT_ID_MASK, - GLBL_ERR_STAT_ERR_DSC_MASK, - &eqdma_hw_desc_err_process - }, - { - EQDMA_DSC_ERR_ALL, - "All Descriptor errors", - EQDMA_GLBL_DSC_ERR_MSK_ADDR, - EQDMA_GLBL_DSC_ERR_STS_ADDR, - EQDMA_GLBL_DSC_ERR_ALL_MASK, - GLBL_ERR_STAT_ERR_DSC_MASK, - &eqdma_hw_desc_err_process - }, - - /* TRQ errors */ - { - EQDMA_TRQ_ERR_CSR_UNMAPPED, - "Access targeted unmapped register space via CSR pathway error", - EQDMA_GLBL_TRQ_ERR_MSK_ADDR, - EQDMA_GLBL_TRQ_ERR_STS_ADDR, - GLBL_TRQ_ERR_STS_CSR_UNMAPPED_MASK, - GLBL_ERR_STAT_ERR_TRQ_MASK, - &eqdma_hw_trq_err_process - }, - { - EQDMA_TRQ_ERR_VF_ACCESS, - "VF attempted to access Global register space or Function map", - EQDMA_GLBL_TRQ_ERR_MSK_ADDR, - EQDMA_GLBL_TRQ_ERR_STS_ADDR, - GLBL_TRQ_ERR_STS_VF_ACCESS_ERR_MASK, - GLBL_ERR_STAT_ERR_TRQ_MASK, - &eqdma_hw_trq_err_process - }, - { - EQDMA_TRQ_ERR_TCP_CSR_TIMEOUT, - "Timeout on request to dma internal csr register", - EQDMA_GLBL_TRQ_ERR_MSK_ADDR, - EQDMA_GLBL_TRQ_ERR_STS_ADDR, - GLBL_TRQ_ERR_STS_TCP_CSR_TIMEOUT_MASK, - GLBL_ERR_STAT_ERR_TRQ_MASK, - &eqdma_hw_trq_err_process - }, - { - EQDMA_TRQ_ERR_QSPC_UNMAPPED, - "Access targeted unmapped register via queue space pathway", - EQDMA_GLBL_TRQ_ERR_MSK_ADDR, - EQDMA_GLBL_TRQ_ERR_STS_ADDR, - GLBL_TRQ_ERR_STS_QSPC_UNMAPPED_MASK, - GLBL_ERR_STAT_ERR_TRQ_MASK, - &eqdma_hw_trq_err_process - }, - { - EQDMA_TRQ_ERR_QID_RANGE, - "Qid range error", - EQDMA_GLBL_TRQ_ERR_MSK_ADDR, - EQDMA_GLBL_TRQ_ERR_STS_ADDR, - GLBL_TRQ_ERR_STS_QID_RANGE_MASK, - GLBL_ERR_STAT_ERR_TRQ_MASK, - &eqdma_hw_trq_err_process - }, - { - EQDMA_TRQ_ERR_TCP_QSPC_TIMEOUT, - "Timeout on request to dma internal queue space register", - EQDMA_GLBL_TRQ_ERR_MSK_ADDR, - EQDMA_GLBL_TRQ_ERR_STS_ADDR, - GLBL_TRQ_ERR_STS_TCP_QSPC_TIMEOUT_MASK, - GLBL_ERR_STAT_ERR_TRQ_MASK, - &eqdma_hw_trq_err_process - }, - { - EQDMA_TRQ_ERR_ALL, - "All TRQ errors", - EQDMA_GLBL_TRQ_ERR_MSK_ADDR, - EQDMA_GLBL_TRQ_ERR_STS_ADDR, - EQDMA_GLBL_TRQ_ERR_ALL_MASK, - GLBL_ERR_STAT_ERR_TRQ_MASK, - &eqdma_hw_trq_err_process - }, - - /* C2H Errors*/ - { - EQDMA_ST_C2H_ERR_MTY_MISMATCH, - "MTY mismatch error", - EQDMA_C2H_ERR_MASK_ADDR, - EQDMA_C2H_ERR_STAT_ADDR, - C2H_ERR_STAT_MTY_MISMATCH_MASK, - GLBL_ERR_STAT_ERR_C2H_ST_MASK, - &eqdma_hw_st_c2h_err_process - }, - { - EQDMA_ST_C2H_ERR_LEN_MISMATCH, - "Packet length mismatch error", - EQDMA_C2H_ERR_MASK_ADDR, - EQDMA_C2H_ERR_STAT_ADDR, - C2H_ERR_STAT_LEN_MISMATCH_MASK, - GLBL_ERR_STAT_ERR_C2H_ST_MASK, - &eqdma_hw_st_c2h_err_process - }, - { - EQDMA_ST_C2H_ERR_SH_CMPT_DSC, - "A Shared CMPT queue has encountered a descriptor error", - EQDMA_C2H_ERR_MASK_ADDR, - EQDMA_C2H_ERR_STAT_ADDR, - C2H_ERR_STAT_SH_CMPT_DSC_ERR_MASK, - GLBL_ERR_STAT_ERR_C2H_ST_MASK, - &eqdma_hw_st_c2h_err_process - }, - { - EQDMA_ST_C2H_ERR_QID_MISMATCH, - "Qid mismatch error", - EQDMA_C2H_ERR_MASK_ADDR, - EQDMA_C2H_ERR_STAT_ADDR, - C2H_ERR_STAT_QID_MISMATCH_MASK, - GLBL_ERR_STAT_ERR_C2H_ST_MASK, - &eqdma_hw_st_c2h_err_process - }, - { - EQDMA_ST_C2H_ERR_DESC_RSP_ERR, - "Descriptor error bit set", - EQDMA_C2H_ERR_MASK_ADDR, - EQDMA_C2H_ERR_STAT_ADDR, - C2H_ERR_STAT_DESC_RSP_ERR_MASK, - GLBL_ERR_STAT_ERR_C2H_ST_MASK, - &eqdma_hw_st_c2h_err_process - }, - { - EQDMA_ST_C2H_ERR_ENG_WPL_DATA_PAR_ERR, - "Data parity error", - EQDMA_C2H_ERR_MASK_ADDR, - EQDMA_C2H_ERR_STAT_ADDR, - C2H_ERR_STAT_ENG_WPL_DATA_PAR_ERR_MASK, - GLBL_ERR_STAT_ERR_C2H_ST_MASK, - &eqdma_hw_st_c2h_err_process - }, - { - EQDMA_ST_C2H_ERR_MSI_INT_FAIL, - "MSI got a fail response error", - EQDMA_C2H_ERR_MASK_ADDR, - EQDMA_C2H_ERR_STAT_ADDR, - C2H_ERR_STAT_MSI_INT_FAIL_MASK, - GLBL_ERR_STAT_ERR_C2H_ST_MASK, - &eqdma_hw_st_c2h_err_process - }, - { - EQDMA_ST_C2H_ERR_ERR_DESC_CNT, - "Descriptor count error", - EQDMA_C2H_ERR_MASK_ADDR, - EQDMA_C2H_ERR_STAT_ADDR, - C2H_ERR_STAT_ERR_DESC_CNT_MASK, - GLBL_ERR_STAT_ERR_C2H_ST_MASK, - &eqdma_hw_st_c2h_err_process - }, - { - EQDMA_ST_C2H_ERR_PORTID_CTXT_MISMATCH, - "Port id in packet and pfetch ctxt mismatch error", - EQDMA_C2H_ERR_MASK_ADDR, - EQDMA_C2H_ERR_STAT_ADDR, - C2H_ERR_STAT_PORT_ID_CTXT_MISMATCH_MASK, - GLBL_ERR_STAT_ERR_C2H_ST_MASK, - &eqdma_hw_st_c2h_err_process - }, - { - EQDMA_ST_C2H_ERR_CMPT_INV_Q_ERR, - "Writeback on invalid queue error", - EQDMA_C2H_ERR_MASK_ADDR, - EQDMA_C2H_ERR_STAT_ADDR, - C2H_ERR_STAT_WRB_INV_Q_ERR_MASK, - GLBL_ERR_STAT_ERR_C2H_ST_MASK, - &eqdma_hw_st_c2h_err_process - }, - { - EQDMA_ST_C2H_ERR_CMPT_QFULL_ERR, - "Completion queue gets full error", - EQDMA_C2H_ERR_MASK_ADDR, - EQDMA_C2H_ERR_STAT_ADDR, - C2H_ERR_STAT_WRB_QFULL_ERR_MASK, - GLBL_ERR_STAT_ERR_C2H_ST_MASK, - &eqdma_hw_st_c2h_err_process - }, - { - EQDMA_ST_C2H_ERR_CMPT_CIDX_ERR, - "Bad CIDX update by the software error", - EQDMA_C2H_ERR_MASK_ADDR, - EQDMA_C2H_ERR_STAT_ADDR, - C2H_ERR_STAT_WRB_CIDX_ERR_MASK, - GLBL_ERR_STAT_ERR_C2H_ST_MASK, - &eqdma_hw_st_c2h_err_process - }, - { - EQDMA_ST_C2H_ERR_CMPT_PRTY_ERR, - "C2H completion Parity error", - EQDMA_C2H_ERR_MASK_ADDR, - EQDMA_C2H_ERR_STAT_ADDR, - C2H_ERR_STAT_WRB_PRTY_ERR_MASK, - GLBL_ERR_STAT_ERR_C2H_ST_MASK, - &eqdma_hw_st_c2h_err_process - }, - { - EQDMA_ST_C2H_ERR_AVL_RING_DSC, - "Available ring fetch returns descriptor with error", - EQDMA_C2H_ERR_MASK_ADDR, - EQDMA_C2H_ERR_STAT_ADDR, - C2H_ERR_STAT_AVL_RING_DSC_ERR_MASK, - GLBL_ERR_STAT_ERR_C2H_ST_MASK, - &eqdma_hw_st_c2h_err_process - }, - { - EQDMA_ST_C2H_ERR_HDR_ECC_UNC, - "multi-bit ecc error on c2h packet header", - EQDMA_C2H_ERR_MASK_ADDR, - EQDMA_C2H_ERR_STAT_ADDR, - C2H_ERR_STAT_HDR_ECC_UNC_ERR_MASK, - GLBL_ERR_STAT_ERR_C2H_ST_MASK, - &eqdma_hw_st_c2h_err_process - }, - { - EQDMA_ST_C2H_ERR_HDR_ECC_COR, - "single-bit ecc error on c2h packet header", - EQDMA_C2H_ERR_MASK_ADDR, - EQDMA_C2H_ERR_STAT_ADDR, - C2H_ERR_STAT_HDR_ECC_COR_ERR_MASK, - GLBL_ERR_STAT_ERR_C2H_ST_MASK, - &eqdma_hw_st_c2h_err_process - }, - { - EQDMA_ST_C2H_ERR_WRB_PORT_ID_ERR, - "Port ID error", - EQDMA_C2H_ERR_MASK_ADDR, - EQDMA_C2H_ERR_STAT_ADDR, - C2H_ERR_STAT_WRB_PORT_ID_ERR_MASK, - GLBL_ERR_STAT_ERR_C2H_ST_MASK, - &eqdma_hw_st_c2h_err_process - }, - { - EQDMA_ST_C2H_ERR_ALL, - "All C2h errors", - EQDMA_C2H_ERR_MASK_ADDR, - EQDMA_C2H_ERR_STAT_ADDR, - EQDMA_C2H_ERR_ALL_MASK, - GLBL_ERR_STAT_ERR_C2H_ST_MASK, - &eqdma_hw_st_c2h_err_process - }, - - /* C2H fatal errors */ - { - EQDMA_ST_FATAL_ERR_MTY_MISMATCH, - "Fatal MTY mismatch error", - EQDMA_C2H_FATAL_ERR_MASK_ADDR, - EQDMA_C2H_FATAL_ERR_STAT_ADDR, - C2H_FATAL_ERR_STAT_MTY_MISMATCH_MASK, - GLBL_ERR_STAT_ERR_C2H_ST_MASK, - &eqdma_hw_st_c2h_err_process - }, - { - EQDMA_ST_FATAL_ERR_LEN_MISMATCH, - "Fatal Len mismatch error", - EQDMA_C2H_FATAL_ERR_MASK_ADDR, - EQDMA_C2H_FATAL_ERR_STAT_ADDR, - C2H_FATAL_ERR_STAT_LEN_MISMATCH_MASK, - GLBL_ERR_STAT_ERR_C2H_ST_MASK, - &eqdma_hw_st_c2h_err_process - }, - { - EQDMA_ST_FATAL_ERR_QID_MISMATCH, - "Fatal Qid mismatch error", - EQDMA_C2H_FATAL_ERR_MASK_ADDR, - EQDMA_C2H_FATAL_ERR_STAT_ADDR, - C2H_FATAL_ERR_STAT_QID_MISMATCH_MASK, - GLBL_ERR_STAT_ERR_C2H_ST_MASK, - &eqdma_hw_st_c2h_err_process - }, - { - EQDMA_ST_FATAL_ERR_TIMER_FIFO_RAM_RDBE, - "RAM double bit fatal error", - EQDMA_C2H_FATAL_ERR_MASK_ADDR, - EQDMA_C2H_FATAL_ERR_STAT_ADDR, - C2H_FATAL_ERR_STAT_TIMER_FIFO_RAM_RDBE_MASK, - GLBL_ERR_STAT_ERR_C2H_ST_MASK, - &eqdma_hw_st_c2h_err_process - }, - { - EQDMA_ST_FATAL_ERR_PFCH_II_RAM_RDBE, - "RAM double bit fatal error", - EQDMA_C2H_FATAL_ERR_MASK_ADDR, - EQDMA_C2H_FATAL_ERR_STAT_ADDR, - C2H_FATAL_ERR_STAT_PFCH_LL_RAM_RDBE_MASK, - GLBL_ERR_STAT_ERR_C2H_ST_MASK, - &eqdma_hw_st_c2h_err_process - }, - { - EQDMA_ST_FATAL_ERR_CMPT_CTXT_RAM_RDBE, - "RAM double bit fatal error", - EQDMA_C2H_FATAL_ERR_MASK_ADDR, - EQDMA_C2H_FATAL_ERR_STAT_ADDR, - C2H_FATAL_ERR_STAT_WRB_CTXT_RAM_RDBE_MASK, - GLBL_ERR_STAT_ERR_C2H_ST_MASK, - &eqdma_hw_st_c2h_err_process - }, - { - EQDMA_ST_FATAL_ERR_PFCH_CTXT_RAM_RDBE, - "RAM double bit fatal error", - EQDMA_C2H_FATAL_ERR_MASK_ADDR, - EQDMA_C2H_FATAL_ERR_STAT_ADDR, - C2H_FATAL_ERR_STAT_PFCH_CTXT_RAM_RDBE_MASK, - GLBL_ERR_STAT_ERR_C2H_ST_MASK, - &eqdma_hw_st_c2h_err_process - }, - { - EQDMA_ST_FATAL_ERR_DESC_REQ_FIFO_RAM_RDBE, - "RAM double bit fatal error", - EQDMA_C2H_FATAL_ERR_MASK_ADDR, - EQDMA_C2H_FATAL_ERR_STAT_ADDR, - C2H_FATAL_ERR_STAT_DESC_REQ_FIFO_RAM_RDBE_MASK, - GLBL_ERR_STAT_ERR_C2H_ST_MASK, - &eqdma_hw_st_c2h_err_process - }, - { - EQDMA_ST_FATAL_ERR_INT_CTXT_RAM_RDBE, - "RAM double bit fatal error", - EQDMA_C2H_FATAL_ERR_MASK_ADDR, - EQDMA_C2H_FATAL_ERR_STAT_ADDR, - C2H_FATAL_ERR_STAT_INT_CTXT_RAM_RDBE_MASK, - GLBL_ERR_STAT_ERR_C2H_ST_MASK, - &eqdma_hw_st_c2h_err_process - }, - { - EQDMA_ST_FATAL_ERR_CMPT_COAL_DATA_RAM_RDBE, - "RAM double bit fatal error", - EQDMA_C2H_FATAL_ERR_MASK_ADDR, - EQDMA_C2H_FATAL_ERR_STAT_ADDR, - C2H_FATAL_ERR_STAT_WRB_COAL_DATA_RAM_RDBE_MASK, - GLBL_ERR_STAT_ERR_C2H_ST_MASK, - &eqdma_hw_st_c2h_err_process - }, - { - EQDMA_ST_FATAL_ERR_CMPT_FIFO_RAM_RDBE, - "RAM double bit fatal error", - EQDMA_C2H_FATAL_ERR_MASK_ADDR, - EQDMA_C2H_FATAL_ERR_STAT_ADDR, - C2H_FATAL_ERR_STAT_CMPT_FIFO_RAM_RDBE_MASK, - GLBL_ERR_STAT_ERR_C2H_ST_MASK, - &eqdma_hw_st_c2h_err_process - }, - { - EQDMA_ST_FATAL_ERR_QID_FIFO_RAM_RDBE, - "RAM double bit fatal error", - EQDMA_C2H_FATAL_ERR_MASK_ADDR, - EQDMA_C2H_FATAL_ERR_STAT_ADDR, - C2H_FATAL_ERR_STAT_QID_FIFO_RAM_RDBE_MASK, - GLBL_ERR_STAT_ERR_C2H_ST_MASK, - &eqdma_hw_st_c2h_err_process - }, - { - EQDMA_ST_FATAL_ERR_PAYLOAD_FIFO_RAM_RDBE, - "RAM double bit fatal error", - EQDMA_C2H_FATAL_ERR_MASK_ADDR, - EQDMA_C2H_FATAL_ERR_STAT_ADDR, - C2H_FATAL_ERR_STAT_PLD_FIFO_RAM_RDBE_MASK, - GLBL_ERR_STAT_ERR_C2H_ST_MASK, - &eqdma_hw_st_c2h_err_process - }, - { - EQDMA_ST_FATAL_ERR_WPL_DATA_PAR, - "RAM double bit fatal error", - EQDMA_C2H_FATAL_ERR_MASK_ADDR, - EQDMA_C2H_FATAL_ERR_STAT_ADDR, - C2H_FATAL_ERR_STAT_WPL_DATA_PAR_ERR_MASK, - GLBL_ERR_STAT_ERR_C2H_ST_MASK, - &eqdma_hw_st_c2h_err_process - }, - { - EQDMA_ST_FATAL_ERR_AVL_RING_FIFO_RAM_RDBE, - "RAM double bit fatal error", - EQDMA_C2H_FATAL_ERR_MASK_ADDR, - EQDMA_C2H_FATAL_ERR_STAT_ADDR, - C2H_FATAL_ERR_STAT_AVL_RING_FIFO_RAM_RDBE_MASK, - GLBL_ERR_STAT_ERR_C2H_ST_MASK, - &eqdma_hw_st_c2h_err_process - }, - { - EQDMA_ST_FATAL_ERR_HDR_ECC_UNC, - "RAM double bit fatal error", - EQDMA_C2H_FATAL_ERR_MASK_ADDR, - EQDMA_C2H_FATAL_ERR_STAT_ADDR, - C2H_FATAL_ERR_STAT_HDR_ECC_UNC_ERR_MASK, - GLBL_ERR_STAT_ERR_C2H_ST_MASK, - &eqdma_hw_st_c2h_err_process - }, - { - EQDMA_ST_FATAL_ERR_ALL, - "All fatal errors", - EQDMA_C2H_FATAL_ERR_MASK_ADDR, - EQDMA_C2H_FATAL_ERR_STAT_ADDR, - EQDMA_C2H_FATAL_ERR_ALL_MASK, - GLBL_ERR_STAT_ERR_C2H_ST_MASK, - &eqdma_hw_st_c2h_err_process - }, - - /* H2C St errors */ - { - EQDMA_ST_H2C_ERR_ZERO_LEN_DESC, - "Zero length descriptor error", - EQDMA_H2C_ERR_MASK_ADDR, - EQDMA_H2C_ERR_STAT_ADDR, - H2C_ERR_STAT_ZERO_LEN_DS_MASK, - GLBL_ERR_STAT_ERR_H2C_ST_MASK, - &eqdma_hw_st_h2c_err_process - }, - { - EQDMA_ST_H2C_ERR_SDI_MRKR_REQ_MOP, - "A non-EOP descriptor received", - EQDMA_H2C_ERR_MASK_ADDR, - EQDMA_H2C_ERR_STAT_ADDR, - H2C_ERR_STAT_SDI_MRKR_REQ_MOP_ERR_MASK, - GLBL_ERR_STAT_ERR_H2C_ST_MASK, - &eqdma_hw_st_h2c_err_process - }, - { - EQDMA_ST_H2C_ERR_NO_DMA_DSC, - "No DMA descriptor received error", - EQDMA_H2C_ERR_MASK_ADDR, - EQDMA_H2C_ERR_STAT_ADDR, - H2C_ERR_STAT_NO_DMA_DS_MASK, - GLBL_ERR_STAT_ERR_H2C_ST_MASK, - &eqdma_hw_st_h2c_err_process - }, - { - EQDMA_ST_H2C_ERR_SBE, - "Single bit error detected on H2C-ST data error", - EQDMA_H2C_ERR_MASK_ADDR, - EQDMA_H2C_ERR_STAT_ADDR, - H2C_ERR_STAT_SBE_MASK, - GLBL_ERR_STAT_ERR_H2C_ST_MASK, - &eqdma_hw_st_h2c_err_process - }, - { - EQDMA_ST_H2C_ERR_DBE, - "Double bit error detected on H2C-ST data error", - EQDMA_H2C_ERR_MASK_ADDR, - EQDMA_H2C_ERR_STAT_ADDR, - H2C_ERR_STAT_DBE_MASK, - GLBL_ERR_STAT_ERR_H2C_ST_MASK, - &eqdma_hw_st_h2c_err_process - }, - { - EQDMA_ST_H2C_ERR_PAR, - "Internal data parity error", - EQDMA_H2C_ERR_MASK_ADDR, - EQDMA_H2C_ERR_STAT_ADDR, - H2C_ERR_STAT_PAR_ERR_MASK, - GLBL_ERR_STAT_ERR_H2C_ST_MASK, - &eqdma_hw_st_h2c_err_process - }, - { - EQDMA_ST_H2C_ERR_ALL, - "All H2C errors", - EQDMA_H2C_ERR_MASK_ADDR, - EQDMA_H2C_ERR_STAT_ADDR, - EQDMA_H2C_ERR_ALL_MASK, - GLBL_ERR_STAT_ERR_H2C_ST_MASK, - &eqdma_hw_st_h2c_err_process - }, - - /* SBE errors */ - { - EQDMA_SBE_1_ERR_RC_RRQ_EVEN_RAM, - "RC RRQ Even RAM single bit ECC error.", - EQDMA_RAM_SBE_MSK_1_A_ADDR, - EQDMA_RAM_SBE_STS_1_A_ADDR, - RAM_SBE_STS_1_A_RC_RRQ_EVEN_RAM_MASK, - GLBL_ERR_STAT_ERR_RAM_SBE_MASK, - &eqdma_hw_ram_sbe_err_process - }, - { - EQDMA_SBE_1_ERR_TAG_ODD_RAM, - "Tag Odd Ram single bit ECC error.", - EQDMA_RAM_SBE_MSK_1_A_ADDR, - EQDMA_RAM_SBE_STS_1_A_ADDR, - RAM_SBE_STS_1_A_TAG_ODD_RAM_MASK, - GLBL_ERR_STAT_ERR_RAM_SBE_MASK, - &eqdma_hw_ram_sbe_err_process - }, - { - EQDMA_SBE_1_ERR_TAG_EVEN_RAM, - "Tag Even Ram single bit ECC error.", - EQDMA_RAM_SBE_MSK_1_A_ADDR, - EQDMA_RAM_SBE_STS_1_A_ADDR, - RAM_SBE_STS_1_A_TAG_EVEN_RAM_MASK, - GLBL_ERR_STAT_ERR_RAM_SBE_MASK, - &eqdma_hw_ram_sbe_err_process - }, - { - EQDMA_SBE_1_ERR_PFCH_CTXT_CAM_RAM_0, - "Pfch Ctxt CAM RAM 0 single bit ECC error.", - EQDMA_RAM_SBE_MSK_1_A_ADDR, - EQDMA_RAM_SBE_STS_1_A_ADDR, - RAM_SBE_STS_1_A_PFCH_CTXT_CAM_RAM_0_MASK, - GLBL_ERR_STAT_ERR_RAM_SBE_MASK, - &eqdma_hw_ram_sbe_err_process - }, - { - EQDMA_SBE_1_ERR_PFCH_CTXT_CAM_RAM_1, - "Pfch Ctxt CAM RAM 1 single bit ECC error.", - EQDMA_RAM_SBE_MSK_1_A_ADDR, - EQDMA_RAM_SBE_STS_1_A_ADDR, - RAM_SBE_STS_1_A_PFCH_CTXT_CAM_RAM_1_MASK, - GLBL_ERR_STAT_ERR_RAM_SBE_MASK, - &eqdma_hw_ram_sbe_err_process - }, - { - EQDMA_SBE_1_ERR_ALL, - "All SBE Errors.", - EQDMA_RAM_SBE_MSK_1_A_ADDR, - EQDMA_RAM_SBE_STS_1_A_ADDR, - EQDMA_SBE_ERR_ALL_MASK, - GLBL_ERR_STAT_ERR_RAM_SBE_MASK, - &eqdma_hw_ram_sbe_err_process - }, - { - EQDMA_SBE_ERR_MI_H2C0_DAT, - "H2C MM data buffer single bit ECC error", - EQDMA_RAM_SBE_MSK_A_ADDR, - EQDMA_RAM_SBE_STS_A_ADDR, - RAM_SBE_STS_A_MI_H2C0_DAT_MASK, - GLBL_ERR_STAT_ERR_RAM_SBE_MASK, - &eqdma_hw_ram_sbe_err_process - }, - { - EQDMA_SBE_ERR_MI_H2C1_DAT, - "H2C MM data buffer single bit ECC error", - EQDMA_RAM_SBE_MSK_A_ADDR, - EQDMA_RAM_SBE_STS_A_ADDR, - RAM_SBE_STS_A_MI_H2C1_DAT_MASK, - GLBL_ERR_STAT_ERR_RAM_SBE_MASK, - &eqdma_hw_ram_sbe_err_process - }, - { - EQDMA_SBE_ERR_MI_H2C2_DAT, - "H2C MM data buffer single bit ECC error", - EQDMA_RAM_SBE_MSK_A_ADDR, - EQDMA_RAM_SBE_STS_A_ADDR, - RAM_SBE_STS_A_MI_H2C2_DAT_MASK, - GLBL_ERR_STAT_ERR_RAM_SBE_MASK, - &eqdma_hw_ram_sbe_err_process - }, - { - EQDMA_SBE_ERR_MI_H2C3_DAT, - "H2C MM data buffer single bit ECC error", - EQDMA_RAM_SBE_MSK_A_ADDR, - EQDMA_RAM_SBE_STS_A_ADDR, - RAM_SBE_STS_A_MI_H2C3_DAT_MASK, - GLBL_ERR_STAT_ERR_RAM_SBE_MASK, - &eqdma_hw_ram_sbe_err_process - }, - { - EQDMA_SBE_ERR_MI_C2H0_DAT, - "C2H MM data buffer single bit ECC error", - EQDMA_RAM_SBE_MSK_A_ADDR, - EQDMA_RAM_SBE_STS_A_ADDR, - RAM_SBE_STS_A_MI_C2H0_DAT_MASK, - GLBL_ERR_STAT_ERR_RAM_SBE_MASK, - &eqdma_hw_ram_sbe_err_process - }, - { - EQDMA_SBE_ERR_MI_C2H1_DAT, - "C2H MM data buffer single bit ECC error", - EQDMA_RAM_SBE_MSK_A_ADDR, - EQDMA_RAM_SBE_STS_A_ADDR, - RAM_SBE_STS_A_MI_C2H1_DAT_MASK, - GLBL_ERR_STAT_ERR_RAM_SBE_MASK, - &eqdma_hw_ram_sbe_err_process - }, -{ - EQDMA_SBE_ERR_MI_C2H2_DAT, - "C2H MM data buffer single bit ECC error", - EQDMA_RAM_SBE_MSK_A_ADDR, - EQDMA_RAM_SBE_STS_A_ADDR, - RAM_SBE_STS_A_MI_C2H2_DAT_MASK, - GLBL_ERR_STAT_ERR_RAM_SBE_MASK, - &eqdma_hw_ram_sbe_err_process - }, - { - EQDMA_SBE_ERR_MI_C2H3_DAT, - "C2H MM data buffer single bit ECC error", - EQDMA_RAM_SBE_MSK_A_ADDR, - EQDMA_RAM_SBE_STS_A_ADDR, - RAM_SBE_STS_A_MI_C2H3_DAT_MASK, - GLBL_ERR_STAT_ERR_RAM_SBE_MASK, - &eqdma_hw_ram_sbe_err_process - }, - { - EQDMA_SBE_ERR_H2C_RD_BRG_DAT, - "Bridge master read single bit ECC error", - EQDMA_RAM_SBE_MSK_A_ADDR, - EQDMA_RAM_SBE_STS_A_ADDR, - RAM_SBE_STS_A_H2C_RD_BRG_DAT_MASK, - GLBL_ERR_STAT_ERR_RAM_SBE_MASK, - &eqdma_hw_ram_sbe_err_process - }, - { - EQDMA_SBE_ERR_H2C_WR_BRG_DAT, - "Bridge master write single bit ECC error", - EQDMA_RAM_SBE_MSK_A_ADDR, - EQDMA_RAM_SBE_STS_A_ADDR, - RAM_SBE_STS_A_H2C_WR_BRG_DAT_MASK, - GLBL_ERR_STAT_ERR_RAM_SBE_MASK, - &eqdma_hw_ram_sbe_err_process - }, - { - EQDMA_SBE_ERR_C2H_RD_BRG_DAT, - "Bridge slave read data buffer single bit ECC error", - EQDMA_RAM_SBE_MSK_A_ADDR, - EQDMA_RAM_SBE_STS_A_ADDR, - RAM_SBE_STS_A_C2H_RD_BRG_DAT_MASK, - GLBL_ERR_STAT_ERR_RAM_SBE_MASK, - &eqdma_hw_ram_sbe_err_process - }, - { - EQDMA_SBE_ERR_C2H_WR_BRG_DAT, - "Bridge slave write data buffer single bit ECC error", - EQDMA_RAM_SBE_MSK_A_ADDR, - EQDMA_RAM_SBE_STS_A_ADDR, - RAM_SBE_STS_A_C2H_WR_BRG_DAT_MASK, - GLBL_ERR_STAT_ERR_RAM_SBE_MASK, - &eqdma_hw_ram_sbe_err_process - }, - { - EQDMA_SBE_ERR_FUNC_MAP, - "Function map RAM single bit ECC error", - EQDMA_RAM_SBE_MSK_A_ADDR, - EQDMA_RAM_SBE_STS_A_ADDR, - RAM_SBE_STS_A_FUNC_MAP_MASK, - GLBL_ERR_STAT_ERR_RAM_SBE_MASK, - &eqdma_hw_ram_sbe_err_process - }, - { - EQDMA_SBE_ERR_DSC_HW_CTXT, - "Descriptor engine hardware context RAM single bit ECC error", - EQDMA_RAM_SBE_MSK_A_ADDR, - EQDMA_RAM_SBE_STS_A_ADDR, - RAM_SBE_STS_A_DSC_HW_CTXT_MASK, - GLBL_ERR_STAT_ERR_RAM_SBE_MASK, - &eqdma_hw_ram_sbe_err_process - }, - { - EQDMA_SBE_ERR_DSC_CRD_RCV, - "Descriptor engine receive credit context RAM single bit ECC error", - EQDMA_RAM_SBE_MSK_A_ADDR, - EQDMA_RAM_SBE_STS_A_ADDR, - RAM_SBE_STS_A_DSC_CRD_RCV_MASK, - GLBL_ERR_STAT_ERR_RAM_SBE_MASK, - &eqdma_hw_ram_sbe_err_process - }, - { - EQDMA_SBE_ERR_DSC_SW_CTXT, - "Descriptor engine software context RAM single bit ECC error", - EQDMA_RAM_SBE_MSK_A_ADDR, - EQDMA_RAM_SBE_STS_A_ADDR, - RAM_SBE_STS_A_DSC_SW_CTXT_MASK, - GLBL_ERR_STAT_ERR_RAM_SBE_MASK, - &eqdma_hw_ram_sbe_err_process - }, - { - EQDMA_SBE_ERR_DSC_CPLI, - "Descriptor engine fetch completion information RAM single bit ECC error", - EQDMA_RAM_SBE_MSK_A_ADDR, - EQDMA_RAM_SBE_STS_A_ADDR, - RAM_SBE_STS_A_DSC_CPLI_MASK, - GLBL_ERR_STAT_ERR_RAM_SBE_MASK, - &eqdma_hw_ram_sbe_err_process - }, - { - EQDMA_SBE_ERR_DSC_CPLD, - "Descriptor engine fetch completion data RAM single bit ECC error", - EQDMA_RAM_SBE_MSK_A_ADDR, - EQDMA_RAM_SBE_STS_A_ADDR, - RAM_SBE_STS_A_DSC_CPLD_MASK, - GLBL_ERR_STAT_ERR_RAM_SBE_MASK, - &eqdma_hw_ram_sbe_err_process - }, - { - EQDMA_SBE_ERR_MI_TL_SLV_FIFO_RAM, - "TL Slavle FIFO RAM single bit ECC error", - EQDMA_RAM_SBE_MSK_A_ADDR, - EQDMA_RAM_SBE_STS_A_ADDR, - RAM_SBE_STS_A_MI_TL_SLV_FIFO_RAM_MASK, - GLBL_ERR_STAT_ERR_RAM_SBE_MASK, - &eqdma_hw_ram_sbe_err_process - }, - { - EQDMA_SBE_ERR_TIMER_FIFO_RAM, - "Timer fifo RAM single bit ECC error", - EQDMA_RAM_SBE_MSK_A_ADDR, - EQDMA_RAM_SBE_STS_A_ADDR, - RAM_SBE_STS_A_TIMER_FIFO_RAM_MASK, - GLBL_ERR_STAT_ERR_RAM_SBE_MASK, - &eqdma_hw_ram_sbe_err_process - }, - { - EQDMA_SBE_ERR_QID_FIFO_RAM, - "C2H ST QID FIFO RAM single bit ECC error", - EQDMA_RAM_SBE_MSK_A_ADDR, - EQDMA_RAM_SBE_STS_A_ADDR, - RAM_SBE_STS_A_QID_FIFO_RAM_MASK, - GLBL_ERR_STAT_ERR_RAM_SBE_MASK, - &eqdma_hw_ram_sbe_err_process - }, - { - EQDMA_SBE_ERR_WRB_COAL_DATA_RAM, - "Writeback Coalescing RAM single bit ECC error", - EQDMA_RAM_SBE_MSK_A_ADDR, - EQDMA_RAM_SBE_STS_A_ADDR, - RAM_SBE_STS_A_WRB_COAL_DATA_RAM_MASK, - GLBL_ERR_STAT_ERR_RAM_SBE_MASK, - &eqdma_hw_ram_sbe_err_process - }, - { - EQDMA_SBE_ERR_INT_CTXT_RAM, - "Interrupt context RAM single bit ECC error", - EQDMA_RAM_SBE_MSK_A_ADDR, - EQDMA_RAM_SBE_STS_A_ADDR, - RAM_SBE_STS_A_INT_CTXT_RAM_MASK, - GLBL_ERR_STAT_ERR_RAM_SBE_MASK, - &eqdma_hw_ram_sbe_err_process - }, - { - EQDMA_SBE_ERR_DESC_REQ_FIFO_RAM, - "C2H ST descriptor request RAM single bit ECC error", - EQDMA_RAM_SBE_MSK_A_ADDR, - EQDMA_RAM_SBE_STS_A_ADDR, - RAM_SBE_STS_A_DESC_REQ_FIFO_RAM_MASK, - GLBL_ERR_STAT_ERR_RAM_SBE_MASK, - &eqdma_hw_ram_sbe_err_process - }, - { - EQDMA_SBE_ERR_PFCH_CTXT_RAM, - "C2H ST prefetch RAM single bit ECC error", - EQDMA_RAM_SBE_MSK_A_ADDR, - EQDMA_RAM_SBE_STS_A_ADDR, - RAM_SBE_STS_A_PFCH_CTXT_RAM_MASK, - GLBL_ERR_STAT_ERR_RAM_SBE_MASK, - &eqdma_hw_ram_sbe_err_process - }, - { - EQDMA_SBE_ERR_WRB_CTXT_RAM, - "C2H ST completion context RAM single bit ECC error", - EQDMA_RAM_SBE_MSK_A_ADDR, - EQDMA_RAM_SBE_STS_A_ADDR, - RAM_SBE_STS_A_WRB_CTXT_RAM_MASK, - GLBL_ERR_STAT_ERR_RAM_SBE_MASK, - &eqdma_hw_ram_sbe_err_process - }, - { - EQDMA_SBE_ERR_PFCH_LL_RAM, - "C2H ST prefetch list RAM single bit ECC error", - EQDMA_RAM_SBE_MSK_A_ADDR, - EQDMA_RAM_SBE_STS_A_ADDR, - RAM_SBE_STS_A_PFCH_LL_RAM_MASK, - GLBL_ERR_STAT_ERR_RAM_SBE_MASK, - &eqdma_hw_ram_sbe_err_process - }, - { - EQDMA_SBE_ERR_PEND_FIFO_RAM, - "Pend FIFO RAM single bit ECC error", - EQDMA_RAM_SBE_MSK_A_ADDR, - EQDMA_RAM_SBE_STS_A_ADDR, - RAM_SBE_STS_A_PEND_FIFO_RAM_MASK, - GLBL_ERR_STAT_ERR_RAM_SBE_MASK, - &eqdma_hw_ram_sbe_err_process - }, - { - EQDMA_SBE_ERR_RC_RRQ_ODD_RAM, - "RC RRQ Odd RAM single bit ECC error.", - EQDMA_RAM_SBE_MSK_A_ADDR, - EQDMA_RAM_SBE_STS_A_ADDR, - RAM_SBE_STS_A_RC_RRQ_ODD_RAM_MASK, - GLBL_ERR_STAT_ERR_RAM_SBE_MASK, - &eqdma_hw_ram_sbe_err_process - }, - { - EQDMA_SBE_ERR_ALL, - "All SBE errors", - EQDMA_RAM_SBE_MSK_A_ADDR, - EQDMA_RAM_SBE_STS_A_ADDR, - EQDMA_SBE_ERR_ALL_MASK, - GLBL_ERR_STAT_ERR_RAM_SBE_MASK, - &eqdma_hw_ram_sbe_err_process - }, - - - /* DBE errors */ - { - EQDMA_DBE_1_ERR_RC_RRQ_EVEN_RAM, - "RC RRQ Odd RAM double bit ECC error.", - EQDMA_RAM_DBE_MSK_1_A_ADDR, - EQDMA_RAM_DBE_STS_1_A_ADDR, - RAM_DBE_STS_1_A_RC_RRQ_EVEN_RAM_MASK, - GLBL_ERR_STAT_ERR_RAM_DBE_MASK, - &eqdma_hw_ram_dbe_err_process - }, - { - EQDMA_DBE_1_ERR_TAG_ODD_RAM, - "Tag Odd Ram double bit ECC error.", - EQDMA_RAM_DBE_MSK_1_A_ADDR, - EQDMA_RAM_DBE_STS_1_A_ADDR, - RAM_DBE_STS_1_A_TAG_ODD_RAM_MASK, - GLBL_ERR_STAT_ERR_RAM_DBE_MASK, - &eqdma_hw_ram_dbe_err_process - }, - { - EQDMA_DBE_1_ERR_TAG_EVEN_RAM, - "Tag Even Ram double bit ECC error.", - EQDMA_RAM_DBE_MSK_1_A_ADDR, - EQDMA_RAM_DBE_STS_1_A_ADDR, - RAM_DBE_STS_1_A_TAG_EVEN_RAM_MASK, - GLBL_ERR_STAT_ERR_RAM_DBE_MASK, - &eqdma_hw_ram_dbe_err_process - }, - { - EQDMA_DBE_1_ERR_PFCH_CTXT_CAM_RAM_0, - "Pfch Ctxt CAM RAM 0 double bit ECC error.", - EQDMA_RAM_DBE_MSK_1_A_ADDR, - EQDMA_RAM_DBE_STS_1_A_ADDR, - RAM_DBE_STS_1_A_PFCH_CTXT_CAM_RAM_0_MASK, - GLBL_ERR_STAT_ERR_RAM_DBE_MASK, - &eqdma_hw_ram_dbe_err_process - }, - { - EQDMA_DBE_1_ERR_PFCH_CTXT_CAM_RAM_1, - "Pfch Ctxt CAM RAM double bit ECC error.", - EQDMA_RAM_DBE_MSK_1_A_ADDR, - EQDMA_RAM_DBE_STS_1_A_ADDR, - RAM_DBE_STS_1_A_PFCH_CTXT_CAM_RAM_0_MASK, - GLBL_ERR_STAT_ERR_RAM_DBE_MASK, - &eqdma_hw_ram_dbe_err_process - }, - { - EQDMA_DBE_1_ERR_ALL, - "All DBE errors", - EQDMA_RAM_DBE_MSK_1_A_ADDR, - EQDMA_RAM_DBE_STS_1_A_ADDR, - EQDMA_DBE_ERR_ALL_MASK, - GLBL_ERR_STAT_ERR_RAM_DBE_MASK, - &eqdma_hw_ram_dbe_err_process - }, - { - EQDMA_DBE_ERR_MI_H2C0_DAT, - "H2C MM data buffer double bit ECC error", - EQDMA_RAM_DBE_MSK_A_ADDR, - EQDMA_RAM_DBE_STS_A_ADDR, - RAM_DBE_STS_A_MI_H2C0_DAT_MASK, - GLBL_ERR_STAT_ERR_RAM_DBE_MASK, - &eqdma_hw_ram_dbe_err_process - }, - { - EQDMA_DBE_ERR_MI_H2C1_DAT, - "H2C MM data buffer double bit ECC error", - EQDMA_RAM_DBE_MSK_A_ADDR, - EQDMA_RAM_DBE_STS_A_ADDR, - RAM_DBE_STS_A_MI_H2C1_DAT_MASK, - GLBL_ERR_STAT_ERR_RAM_DBE_MASK, - &eqdma_hw_ram_dbe_err_process - }, - { - EQDMA_DBE_ERR_MI_H2C2_DAT, - "H2C MM data buffer double bit ECC error", - EQDMA_RAM_DBE_MSK_A_ADDR, - EQDMA_RAM_DBE_STS_A_ADDR, - RAM_DBE_STS_A_MI_H2C2_DAT_MASK, - GLBL_ERR_STAT_ERR_RAM_DBE_MASK, - &eqdma_hw_ram_dbe_err_process - }, - { - EQDMA_DBE_ERR_MI_H2C3_DAT, - "H2C MM data buffer double bit ECC error", - EQDMA_RAM_DBE_MSK_A_ADDR, - EQDMA_RAM_DBE_STS_A_ADDR, - RAM_DBE_STS_A_MI_H2C3_DAT_MASK, - GLBL_ERR_STAT_ERR_RAM_DBE_MASK, - &eqdma_hw_ram_dbe_err_process - }, - { - EQDMA_DBE_ERR_MI_C2H0_DAT, - "C2H MM data buffer double bit ECC error", - EQDMA_RAM_DBE_MSK_A_ADDR, - EQDMA_RAM_DBE_STS_A_ADDR, - RAM_DBE_STS_A_MI_C2H0_DAT_MASK, - GLBL_ERR_STAT_ERR_RAM_DBE_MASK, - &eqdma_hw_ram_dbe_err_process - }, - { - EQDMA_DBE_ERR_MI_C2H1_DAT, - "C2H MM data buffer double bit ECC error", - EQDMA_RAM_DBE_MSK_A_ADDR, - EQDMA_RAM_DBE_STS_A_ADDR, - RAM_DBE_STS_A_MI_C2H1_DAT_MASK, - GLBL_ERR_STAT_ERR_RAM_DBE_MASK, - &eqdma_hw_ram_dbe_err_process - }, - { - EQDMA_DBE_ERR_MI_C2H2_DAT, - "C2H MM data buffer double bit ECC error", - EQDMA_RAM_DBE_MSK_A_ADDR, - EQDMA_RAM_DBE_STS_A_ADDR, - RAM_DBE_STS_A_MI_C2H2_DAT_MASK, - GLBL_ERR_STAT_ERR_RAM_DBE_MASK, - &eqdma_hw_ram_dbe_err_process - }, - { - EQDMA_DBE_ERR_MI_C2H3_DAT, - "C2H MM data buffer double bit ECC error", - EQDMA_RAM_DBE_MSK_A_ADDR, - EQDMA_RAM_DBE_STS_A_ADDR, - RAM_DBE_STS_A_MI_C2H3_DAT_MASK, - GLBL_ERR_STAT_ERR_RAM_DBE_MASK, - &eqdma_hw_ram_dbe_err_process - }, - { - EQDMA_DBE_ERR_H2C_RD_BRG_DAT, - "Bridge master read double bit ECC error", - EQDMA_RAM_DBE_MSK_A_ADDR, - EQDMA_RAM_DBE_STS_A_ADDR, - RAM_DBE_STS_A_H2C_RD_BRG_DAT_MASK, - GLBL_ERR_STAT_ERR_RAM_DBE_MASK, - &eqdma_hw_ram_dbe_err_process - }, - { - EQDMA_DBE_ERR_H2C_WR_BRG_DAT, - "Bridge master write double bit ECC error", - EQDMA_RAM_DBE_MSK_A_ADDR, - EQDMA_RAM_DBE_STS_A_ADDR, - RAM_DBE_STS_A_H2C_WR_BRG_DAT_MASK, - GLBL_ERR_STAT_ERR_RAM_DBE_MASK, - &eqdma_hw_ram_dbe_err_process - }, - { - EQDMA_DBE_ERR_C2H_RD_BRG_DAT, - "Bridge slave read data buffer double bit ECC error", - EQDMA_RAM_DBE_MSK_A_ADDR, - EQDMA_RAM_DBE_STS_A_ADDR, - RAM_DBE_STS_A_C2H_RD_BRG_DAT_MASK, - GLBL_ERR_STAT_ERR_RAM_DBE_MASK, - &eqdma_hw_ram_dbe_err_process - }, - { - EQDMA_DBE_ERR_C2H_WR_BRG_DAT, - "Bridge slave write data buffer double bit ECC error", - EQDMA_RAM_DBE_MSK_A_ADDR, - EQDMA_RAM_DBE_STS_A_ADDR, - RAM_DBE_STS_A_C2H_WR_BRG_DAT_MASK, - GLBL_ERR_STAT_ERR_RAM_DBE_MASK, - &eqdma_hw_ram_dbe_err_process - }, - { - EQDMA_DBE_ERR_FUNC_MAP, - "Function map RAM double bit ECC error", - EQDMA_RAM_DBE_MSK_A_ADDR, - EQDMA_RAM_DBE_STS_A_ADDR, - RAM_DBE_STS_A_FUNC_MAP_MASK, - GLBL_ERR_STAT_ERR_RAM_DBE_MASK, - &eqdma_hw_ram_dbe_err_process - }, - { - EQDMA_DBE_ERR_DSC_HW_CTXT, - "Descriptor engine hardware context RAM double bit ECC error", - EQDMA_RAM_DBE_MSK_A_ADDR, - EQDMA_RAM_DBE_STS_A_ADDR, - RAM_DBE_STS_A_DSC_HW_CTXT_MASK, - GLBL_ERR_STAT_ERR_RAM_DBE_MASK, - &eqdma_hw_ram_dbe_err_process - }, - { - EQDMA_DBE_ERR_DSC_CRD_RCV, - "Descriptor engine receive credit context RAM double bit ECC error", - EQDMA_RAM_DBE_MSK_A_ADDR, - EQDMA_RAM_DBE_STS_A_ADDR, - RAM_DBE_STS_A_DSC_CRD_RCV_MASK, - GLBL_ERR_STAT_ERR_RAM_DBE_MASK, - &eqdma_hw_ram_dbe_err_process - }, - { - EQDMA_DBE_ERR_DSC_SW_CTXT, - "Descriptor engine software context RAM double bit ECC error", - EQDMA_RAM_DBE_MSK_A_ADDR, - EQDMA_RAM_DBE_STS_A_ADDR, - RAM_DBE_STS_A_DSC_SW_CTXT_MASK, - GLBL_ERR_STAT_ERR_RAM_DBE_MASK, - &eqdma_hw_ram_dbe_err_process - }, - { - EQDMA_DBE_ERR_DSC_CPLI, - "Descriptor engine fetch completion information RAM double bit ECC error", - EQDMA_RAM_DBE_MSK_A_ADDR, - EQDMA_RAM_DBE_STS_A_ADDR, - RAM_DBE_STS_A_DSC_CPLI_MASK, - GLBL_ERR_STAT_ERR_RAM_DBE_MASK, - &eqdma_hw_ram_dbe_err_process - }, - { - EQDMA_DBE_ERR_DSC_CPLD, - "Descriptor engine fetch completion data RAM double bit ECC error", - EQDMA_RAM_DBE_MSK_A_ADDR, - EQDMA_RAM_DBE_STS_A_ADDR, - RAM_DBE_STS_A_DSC_CPLD_MASK, - GLBL_ERR_STAT_ERR_RAM_DBE_MASK, - &eqdma_hw_ram_dbe_err_process - }, - { - EQDMA_DBE_ERR_MI_TL_SLV_FIFO_RAM, - "TL Slave FIFO RAM double bit ECC error", - EQDMA_RAM_DBE_MSK_A_ADDR, - EQDMA_RAM_DBE_STS_A_ADDR, - RAM_DBE_STS_A_MI_TL_SLV_FIFO_RAM_MASK, - GLBL_ERR_STAT_ERR_RAM_DBE_MASK, - &eqdma_hw_ram_dbe_err_process - }, - { - EQDMA_DBE_ERR_TIMER_FIFO_RAM, - "Timer fifo RAM double bit ECC error", - EQDMA_RAM_DBE_MSK_A_ADDR, - EQDMA_RAM_DBE_STS_A_ADDR, - RAM_DBE_STS_A_TIMER_FIFO_RAM_MASK, - GLBL_ERR_STAT_ERR_RAM_DBE_MASK, - &eqdma_hw_ram_dbe_err_process - }, - { - EQDMA_DBE_ERR_QID_FIFO_RAM, - "C2H ST QID FIFO RAM double bit ECC error", - EQDMA_RAM_DBE_MSK_A_ADDR, - EQDMA_RAM_DBE_STS_A_ADDR, - RAM_DBE_STS_A_QID_FIFO_RAM_MASK, - GLBL_ERR_STAT_ERR_RAM_DBE_MASK, - &eqdma_hw_ram_dbe_err_process - }, - { - EQDMA_DBE_ERR_WRB_COAL_DATA_RAM, - "Writeback Coalescing RAM double bit ECC error", - EQDMA_RAM_DBE_MSK_A_ADDR, - EQDMA_RAM_DBE_STS_A_ADDR, - RAM_DBE_STS_A_WRB_COAL_DATA_RAM_MASK, - GLBL_ERR_STAT_ERR_RAM_DBE_MASK, - &eqdma_hw_ram_dbe_err_process - }, - { - EQDMA_DBE_ERR_INT_CTXT_RAM, - "Interrupt context RAM double bit ECC error", - EQDMA_RAM_DBE_MSK_A_ADDR, - EQDMA_RAM_DBE_STS_A_ADDR, - RAM_DBE_STS_A_INT_CTXT_RAM_MASK, - GLBL_ERR_STAT_ERR_RAM_DBE_MASK, - &eqdma_hw_ram_dbe_err_process - }, - { - EQDMA_DBE_ERR_DESC_REQ_FIFO_RAM, - "C2H ST descriptor request RAM double bit ECC error", - EQDMA_RAM_DBE_MSK_A_ADDR, - EQDMA_RAM_DBE_STS_A_ADDR, - RAM_DBE_STS_A_DESC_REQ_FIFO_RAM_MASK, - GLBL_ERR_STAT_ERR_RAM_DBE_MASK, - &eqdma_hw_ram_dbe_err_process - }, - { - EQDMA_DBE_ERR_PFCH_CTXT_RAM, - "C2H ST prefetch RAM double bit ECC error", - EQDMA_RAM_DBE_MSK_A_ADDR, - EQDMA_RAM_DBE_STS_A_ADDR, - RAM_DBE_STS_A_PFCH_CTXT_RAM_MASK, - GLBL_ERR_STAT_ERR_RAM_DBE_MASK, - &eqdma_hw_ram_dbe_err_process - }, - { - EQDMA_DBE_ERR_WRB_CTXT_RAM, - "C2H ST completion context RAM double bit ECC error", - EQDMA_RAM_DBE_MSK_A_ADDR, - EQDMA_RAM_DBE_STS_A_ADDR, - RAM_DBE_STS_A_WRB_CTXT_RAM_MASK, - GLBL_ERR_STAT_ERR_RAM_DBE_MASK, - &eqdma_hw_ram_dbe_err_process - }, - { - EQDMA_DBE_ERR_PFCH_LL_RAM, - "C2H ST prefetch list RAM double bit ECC error", - EQDMA_RAM_DBE_MSK_A_ADDR, - EQDMA_RAM_DBE_STS_A_ADDR, - RAM_DBE_STS_A_PFCH_LL_RAM_MASK, - GLBL_ERR_STAT_ERR_RAM_DBE_MASK, - &eqdma_hw_ram_dbe_err_process - }, - { - EQDMA_DBE_ERR_PEND_FIFO_RAM, - "Pend FIFO RAM double bit ECC error", - EQDMA_RAM_DBE_MSK_A_ADDR, - EQDMA_RAM_DBE_STS_A_ADDR, - RAM_DBE_STS_A_PEND_FIFO_RAM_MASK, - GLBL_ERR_STAT_ERR_RAM_DBE_MASK, - &eqdma_hw_ram_dbe_err_process - }, - { - EQDMA_DBE_ERR_RC_RRQ_ODD_RAM, - "RC RRQ Odd RAM double bit ECC error.", - EQDMA_RAM_DBE_MSK_A_ADDR, - EQDMA_RAM_DBE_STS_A_ADDR, - RAM_DBE_STS_A_RC_RRQ_ODD_RAM_MASK, - GLBL_ERR_STAT_ERR_RAM_DBE_MASK, - &eqdma_hw_ram_dbe_err_process - }, - { - EQDMA_DBE_ERR_ALL, - "All DBE errors", - EQDMA_RAM_DBE_MSK_A_ADDR, - EQDMA_RAM_DBE_STS_A_ADDR, - EQDMA_DBE_ERR_ALL_MASK, - GLBL_ERR_STAT_ERR_RAM_DBE_MASK, - &eqdma_hw_ram_dbe_err_process - }, - /* MM C2H Engine 0 errors */ - { - EQDMA_MM_C2H_WR_SLR_ERR, - "MM C2H0 WR SLV Error", - EQDMA_C2H_MM_ERR_CODE_ENABLE_MASK_ADDR, - EQDMA_C2H_MM_STATUS_ADDR, - C2H_MM_ERR_CODE_ENABLE_WR_SLV_ERR_MASK, - GLBL_ERR_STAT_ERR_C2H_MM_0_MASK, - &eqdma_mm_c2h0_err_process - }, - { - EQDMA_MM_C2H_RD_SLR_ERR, - "MM C2H0 RD SLV Error", - EQDMA_C2H_MM_ERR_CODE_ENABLE_MASK_ADDR, - EQDMA_C2H_MM_STATUS_ADDR, - C2H_MM_ERR_CODE_ENABLE_RD_SLV_ERR_MASK, - GLBL_ERR_STAT_ERR_C2H_MM_0_MASK, - &eqdma_mm_c2h0_err_process - }, - { - EQDMA_MM_C2H_WR_FLR_ERR, - "MM C2H0 WR FLR Error", - EQDMA_C2H_MM_ERR_CODE_ENABLE_MASK_ADDR, - EQDMA_C2H_MM_STATUS_ADDR, - C2H_MM_ERR_CODE_ENABLE_WR_FLR_MASK, - GLBL_ERR_STAT_ERR_C2H_MM_0_MASK, - &eqdma_mm_c2h0_err_process - }, - { - EQDMA_MM_C2H_UR_ERR, - "MM C2H0 Unsupported Request Error", - EQDMA_C2H_MM_ERR_CODE_ENABLE_MASK_ADDR, - EQDMA_C2H_MM_STATUS_ADDR, - C2H_MM_ERR_CODE_ENABLE_WR_UR_MASK, - GLBL_ERR_STAT_ERR_C2H_MM_0_MASK, - &eqdma_mm_c2h0_err_process - }, - { - EQDMA_MM_C2H_WR_UC_RAM_ERR, - "MM C2H0 Write Uncorrectable RAM Error", - EQDMA_C2H_MM_ERR_CODE_ENABLE_MASK_ADDR, - EQDMA_C2H_MM_STATUS_ADDR, - C2H_MM_ERR_CODE_ENABLE_WR_UC_RAM_MASK, - GLBL_ERR_STAT_ERR_C2H_MM_0_MASK, - &eqdma_mm_c2h0_err_process - }, - { - EQDMA_MM_C2H_ERR_ALL, - "All MM C2H Errors", - EQDMA_C2H_MM_ERR_CODE_ENABLE_MASK_ADDR, - EQDMA_C2H_MM_STATUS_ADDR, - EQDMA_MM_C2H_ERR_ALL_MASK, - GLBL_ERR_STAT_ERR_C2H_MM_0_MASK, - &eqdma_mm_c2h0_err_process - }, - /* MM H2C Engine 0 Errors */ - { - EQDMA_MM_H2C0_RD_HDR_POISON_ERR, - "MM H2C0 Read cmpt header pison Error", - EQDMA_H2C_MM_ERR_CODE_ENABLE_MASK_ADDR, - EQDMA_H2C_MM_STATUS_ADDR, - H2C_MM_ERR_CODE_ENABLE_RD_HRD_POISON_ERR_MASK, - GLBL_ERR_STAT_ERR_H2C_MM_0_MASK, - &eqdma_mm_h2c0_err_process - }, - { - EQDMA_MM_H2C0_RD_UR_CA_ERR, - "MM H2C0 Read cmpt unsupported request Error", - EQDMA_H2C_MM_ERR_CODE_ENABLE_MASK_ADDR, - EQDMA_H2C_MM_STATUS_ADDR, - H2C_MM_ERR_CODE_ENABLE_RD_UR_CA_MASK, - GLBL_ERR_STAT_ERR_H2C_MM_0_MASK, - &eqdma_mm_h2c0_err_process - }, - { - EQDMA_MM_H2C0_RD_HDR_BYTE_ERR, - "MM H2C0 Read cmpt hdr byte cnt Error", - EQDMA_H2C_MM_ERR_CODE_ENABLE_MASK_ADDR, - EQDMA_H2C_MM_STATUS_ADDR, - H2C_MM_ERR_CODE_ENABLE_RD_HDR_BYTE_ERR_MASK, - GLBL_ERR_STAT_ERR_H2C_MM_0_MASK, - &eqdma_mm_h2c0_err_process - }, - { - EQDMA_MM_H2C0_RD_HDR_PARAM_ERR, - "MM H2C0 Read cmpt hdr param mismatch Error", - EQDMA_H2C_MM_ERR_CODE_ENABLE_MASK_ADDR, - EQDMA_H2C_MM_STATUS_ADDR, - H2C_MM_ERR_CODE_ENABLE_RD_HDR_PARA_MASK, - GLBL_ERR_STAT_ERR_H2C_MM_0_MASK, - &eqdma_mm_h2c0_err_process - }, - { - EQDMA_MM_H2C0_RD_HDR_ADR_ERR, - "MM H2C0 Read cmpt hdr address mismatch Error", - EQDMA_H2C_MM_ERR_CODE_ENABLE_MASK_ADDR, - EQDMA_H2C_MM_STATUS_ADDR, - H2C_MM_ERR_CODE_ENABLE_RD_HDR_ADR_ERR_MASK, - GLBL_ERR_STAT_ERR_H2C_MM_0_MASK, - &eqdma_mm_h2c0_err_process - }, - { - EQDMA_MM_H2C0_RD_FLR_ERR, - "MM H2C0 Read flr Error", - EQDMA_H2C_MM_ERR_CODE_ENABLE_MASK_ADDR, - EQDMA_H2C_MM_STATUS_ADDR, - H2C_MM_ERR_CODE_ENABLE_RD_FLR_ERR_MASK, - GLBL_ERR_STAT_ERR_H2C_MM_0_MASK, - &eqdma_mm_h2c0_err_process - }, - { - EQDMA_MM_H2C0_RD_DAT_POISON_ERR, - "MM H2C0 Read data poison Error", - EQDMA_H2C_MM_ERR_CODE_ENABLE_MASK_ADDR, - EQDMA_H2C_MM_STATUS_ADDR, - H2C_MM_ERR_CODE_ENABLE_RD_DAT_POISON_ERR_MASK, - GLBL_ERR_STAT_ERR_H2C_MM_0_MASK, - &eqdma_mm_h2c0_err_process - }, - { - EQDMA_MM_H2C0_RD_RQ_DIS_ERR, - "MM H2C0 Read request disable Error", - EQDMA_H2C_MM_ERR_CODE_ENABLE_MASK_ADDR, - EQDMA_H2C_MM_STATUS_ADDR, - H2C_MM_ERR_CODE_ENABLE_RD_RQ_DIS_ERR_MASK, - GLBL_ERR_STAT_ERR_H2C_MM_0_MASK, - &eqdma_mm_h2c0_err_process - }, - { - EQDMA_MM_H2C0_WR_DEC_ERR, - "MM H2C0 Write desc Error", - EQDMA_H2C_MM_ERR_CODE_ENABLE_MASK_ADDR, - EQDMA_H2C_MM_STATUS_ADDR, - H2C_MM_ERR_CODE_ENABLE_WR_DEC_ERR_MASK, - GLBL_ERR_STAT_ERR_H2C_MM_0_MASK, - &eqdma_mm_h2c0_err_process - }, - { - EQDMA_MM_H2C0_WR_SLV_ERR, - "MM H2C0 Write slv Error", - EQDMA_H2C_MM_ERR_CODE_ENABLE_MASK_ADDR, - EQDMA_H2C_MM_STATUS_ADDR, - H2C_MM_ERR_CODE_ENABLE_WR_SLV_ERR_MASK, - GLBL_ERR_STAT_ERR_H2C_MM_0_MASK, - &eqdma_mm_h2c0_err_process - }, - { - EQDMA_MM_H2C0_ERR_ALL, - "All MM H2C Errors", - EQDMA_H2C_MM_ERR_CODE_ENABLE_MASK_ADDR, - EQDMA_H2C_MM_STATUS_ADDR, - EQDMA_MM_H2C0_ERR_ALL_MASK, - GLBL_ERR_STAT_ERR_H2C_MM_0_MASK, - &eqdma_mm_h2c0_err_process - }, - -}; - -static int32_t all_eqdma_hw_errs[EQDMA_TOTAL_LEAF_ERROR_AGGREGATORS] = { - - EQDMA_DSC_ERR_ALL, - EQDMA_TRQ_ERR_ALL, - EQDMA_ST_C2H_ERR_ALL, - EQDMA_ST_FATAL_ERR_ALL, - EQDMA_ST_H2C_ERR_ALL, - EQDMA_SBE_1_ERR_ALL, - EQDMA_SBE_ERR_ALL, - EQDMA_DBE_1_ERR_ALL, - EQDMA_DBE_ERR_ALL, - EQDMA_MM_C2H_ERR_ALL, - EQDMA_MM_H2C0_ERR_ALL -}; - -static struct qctx_entry eqdma_sw_ctxt_entries[] = { - {"PIDX", 0}, - {"IRQ Arm", 0}, - {"Function Id", 0}, - {"Queue Enable", 0}, - {"Fetch Credit Enable", 0}, - {"Write back/Intr Check", 0}, - {"Write back/Intr Interval", 0}, - {"Address Translation", 0}, - {"Fetch Max", 0}, - {"Ring Size", 0}, - {"Descriptor Size", 0}, - {"Bypass Enable", 0}, - {"MM Channel", 0}, - {"Writeback Enable", 0}, - {"Interrupt Enable", 0}, - {"Port Id", 0}, - {"Interrupt No Last", 0}, - {"Error", 0}, - {"Writeback Error Sent", 0}, - {"IRQ Request", 0}, - {"Marker Disable", 0}, - {"Is Memory Mapped", 0}, - {"Descriptor Ring Base Addr (Low)", 0}, - {"Descriptor Ring Base Addr (High)", 0}, - {"Interrupt Vector/Ring Index", 0}, - {"Interrupt Aggregation", 0}, - {"Disable Interrupt with VF", 0}, - {"Pack descriptor output interface", 0}, - {"Irq Bypass", 0}, -}; - -static struct qctx_entry eqdma_hw_ctxt_entries[] = { - {"CIDX", 0}, - {"Credits Consumed", 0}, - {"Descriptors Pending", 0}, - {"Queue Invalid No Desc Pending", 0}, - {"Eviction Pending", 0}, - {"Fetch Pending", 0}, -}; - -static struct qctx_entry eqdma_credit_ctxt_entries[] = { - {"Credit", 0}, -}; - -static struct qctx_entry eqdma_fmap_ctxt_entries[] = { - {"Queue Base", 0}, - {"Queue Max", 0}, -}; - -static struct qctx_entry eqdma_cmpt_ctxt_entries[] = { - {"Enable Status Desc Update", 0}, - {"Enable Interrupt", 0}, - {"Trigger Mode", 0}, - {"Function Id", 0}, - {"Counter Index", 0}, - {"Timer Index", 0}, - {"Interrupt State", 0}, - {"Color", 0}, - {"Ring Size", 0}, - {"Base Addr High (L)[37:6]", 0}, - {"Base Addr High(H)[63:38]", 0}, - {"Descriptor Size", 0}, - {"PIDX", 0}, - {"CIDX", 0}, - {"Valid", 0}, - {"Error", 0}, - {"Trigger Pending", 0}, - {"Timer Running", 0}, - {"Full Update", 0}, - {"Over Flow Check Disable", 0}, - {"Address Translation", 0}, - {"Interrupt Vector/Ring Index", 0}, - {"Interrupt Aggregation", 0}, - {"Disable Insterrupt with VF", 0}, - {"c2h Direction", 0}, - {"Base Addr Low[5:2]", 0}, - {"Shared Completion Queue", 0}, -}; - -static struct qctx_entry eqdma_c2h_pftch_ctxt_entries[] = { - {"Bypass", 0}, - {"Buffer Size Index", 0}, - {"Port Id", 0}, - {"Variable Descriptor", 0}, - {"Number of descriptors prefetched", 0}, - {"Error", 0}, - {"Prefetch Enable", 0}, - {"In Prefetch", 0}, - {"Software Credit", 0}, - {"Valid", 0}, -}; - -static struct qctx_entry eqdma_ind_intr_ctxt_entries[] = { - {"valid", 0}, - {"vec", 0}, - {"int_st", 0}, - {"color", 0}, - {"baddr_4k (Low)", 0}, - {"baddr_4k (High)", 0}, - {"page_size", 0}, - {"pidx", 0}, - {"at", 0}, - {"Function Id", 0}, -}; - -static int eqdma_indirect_reg_invalidate(void *dev_hndl, - enum ind_ctxt_cmd_sel sel, uint16_t hw_qid); -static int eqdma_indirect_reg_clear(void *dev_hndl, - enum ind_ctxt_cmd_sel sel, uint16_t hw_qid); -static int eqdma_indirect_reg_read(void *dev_hndl, enum ind_ctxt_cmd_sel sel, - uint16_t hw_qid, uint32_t cnt, uint32_t *data); -static int eqdma_indirect_reg_write(void *dev_hndl, enum ind_ctxt_cmd_sel sel, - uint16_t hw_qid, uint32_t *data, uint16_t cnt); - -uint32_t eqdma_get_config_num_regs(void) -{ - return eqdma_config_num_regs_get(); -} - -struct xreg_info *eqdma_get_config_regs(void) -{ - return eqdma_config_regs_get(); -} - -uint32_t eqdma_reg_dump_buf_len(void) -{ - uint32_t length = (eqdma_config_num_regs_get() + 1) - * REG_DUMP_SIZE_PER_LINE; - return length; -} - -int eqdma_context_buf_len(uint8_t st, - enum qdma_dev_q_type q_type, uint32_t *buflen) -{ - int len = 0; - - if (q_type == QDMA_DEV_Q_TYPE_CMPT) { - len += (((sizeof(eqdma_cmpt_ctxt_entries) / - sizeof(eqdma_cmpt_ctxt_entries[0])) + 1) * - REG_DUMP_SIZE_PER_LINE); - } else { - len += (((sizeof(eqdma_sw_ctxt_entries) / - sizeof(eqdma_sw_ctxt_entries[0])) + 1) * - REG_DUMP_SIZE_PER_LINE); - - len += (((sizeof(eqdma_hw_ctxt_entries) / - sizeof(eqdma_hw_ctxt_entries[0])) + 1) * - REG_DUMP_SIZE_PER_LINE); - - len += (((sizeof(eqdma_credit_ctxt_entries) / - sizeof(eqdma_credit_ctxt_entries[0])) + 1) * - REG_DUMP_SIZE_PER_LINE); - - len += (((sizeof(eqdma_fmap_ctxt_entries) / - sizeof(eqdma_fmap_ctxt_entries[0])) + 1) * - REG_DUMP_SIZE_PER_LINE); - - if (st && (q_type == QDMA_DEV_Q_TYPE_C2H)) { - len += (((sizeof(eqdma_cmpt_ctxt_entries) / - sizeof(eqdma_cmpt_ctxt_entries[0])) + 1) * - REG_DUMP_SIZE_PER_LINE); - - len += (((sizeof(eqdma_c2h_pftch_ctxt_entries) / - sizeof(eqdma_c2h_pftch_ctxt_entries[0])) + 1) * - REG_DUMP_SIZE_PER_LINE); - } - } - - *buflen = len; - return 0; -} - - -static uint32_t eqdma_intr_context_buf_len(void) -{ - uint32_t len = 0; - - len += (((sizeof(eqdma_ind_intr_ctxt_entries) / - sizeof(eqdma_ind_intr_ctxt_entries[0])) + 1) * - REG_DUMP_SIZE_PER_LINE); - return len; -} - - -static void eqdma_set_perf_opt(void *dev_hndl) -{ - uint32_t reg_val = 0, data_th = 0, pfch_cache_dpth = 0; - /**** - * TODO: All the below settings are for QDMA5.0 - * Need to add the QDMA4.0 settings - */ -#define EQDMA_PFTCH_CACHE_DEPTH 64 -#define GLBL_DSC_CFG_RSVD_1_DFLT 0 -#define EQDMA_GLBL_DSC_CFG_C2H_UODSC_LIMIT 5 -#define EQDMA_GLBL_DSC_CFG_H2C_UODSC_LIMIT 8 -#define GLBL_DSC_CFG_UNC_OVR_COR_DFLT 0 -#define GLBL_DSC_CFG_CTXT_FER_DIS_DFLT 0 -#define GLBL_DSC_CFG_RSVD_2_DFLT 0 -#define EQDMA_GLBL_DSC_CFG_MAXFETCH 2 -#define EQDMA_GLBL_DSC_CFG_WB_ACC_INT 5 - - reg_val = - FIELD_SET(GLBL_DSC_CFG_RSVD_1_MASK, GLBL_DSC_CFG_RSVD_1_DFLT) | - FIELD_SET(GLBL_DSC_CFG_C2H_UODSC_LIMIT_MASK, - EQDMA_GLBL_DSC_CFG_C2H_UODSC_LIMIT) | - FIELD_SET(GLBL_DSC_CFG_H2C_UODSC_LIMIT_MASK, - EQDMA_GLBL_DSC_CFG_H2C_UODSC_LIMIT) | - FIELD_SET(GLBL_DSC_CFG_UNC_OVR_COR_MASK, - GLBL_DSC_CFG_UNC_OVR_COR_DFLT) | - FIELD_SET(GLBL_DSC_CFG_CTXT_FER_DIS_MASK, - GLBL_DSC_CFG_CTXT_FER_DIS_DFLT) | - FIELD_SET(GLBL_DSC_CFG_RSVD_2_MASK, GLBL_DSC_CFG_RSVD_2_DFLT) | - FIELD_SET(GLBL_DSC_CFG_MAXFETCH_MASK, - EQDMA_GLBL_DSC_CFG_MAXFETCH) | - FIELD_SET(GLBL_DSC_CFG_WB_ACC_INT_MASK, - EQDMA_GLBL_DSC_CFG_WB_ACC_INT); - qdma_reg_write(dev_hndl, EQDMA_GLBL_DSC_CFG_ADDR, reg_val); - reg_val = qdma_reg_read(dev_hndl, EQDMA_GLBL_DSC_CFG_ADDR); - qdma_log_info("%s: reg = 0x%08X val = 0x%08X\n", - __func__, EQDMA_GLBL_DSC_CFG_ADDR, reg_val); - -#define CFG_BLK_MISC_CTL_RSVD_1_DFLT 0 -#define CFG_BLK_MISC_CTL_10B_TAG_DFLT 0 -#define CFG_BLK_MISC_CTL_RSVD_2_DFLT 0 -#define CFG_BLK_MISC_CTL_AXI_WBK_DFLT 0 -#define CFG_BLK_MISC_CTL_AXI_DSC_DFLT 0 -#define CFG_BLK_MISC_CTL_NUM_TAG_DFLT 256 -#define CFG_BLK_MISC_CTL_RSVD_3_DFLT 0 -#define EQDMA_CFG_BLK_MISC_CTL_RQ_METERING_MUL 9 - - - reg_val = - FIELD_SET(CFG_BLK_MISC_CTL_RSVD_1_MASK, - CFG_BLK_MISC_CTL_RSVD_1_DFLT) | - FIELD_SET(CFG_BLK_MISC_CTL_10B_TAG_EN_MASK, - CFG_BLK_MISC_CTL_10B_TAG_DFLT) | - FIELD_SET(CFG_BLK_MISC_CTL_RSVD_2_MASK, - CFG_BLK_MISC_CTL_RSVD_2_DFLT) | - FIELD_SET(CFG_BLK_MISC_CTL_AXI_WBK_MASK, - CFG_BLK_MISC_CTL_AXI_WBK_DFLT) | - FIELD_SET(CFG_BLK_MISC_CTL_AXI_DSC_MASK, - CFG_BLK_MISC_CTL_AXI_DSC_DFLT) | - FIELD_SET(CFG_BLK_MISC_CTL_NUM_TAG_MASK, - CFG_BLK_MISC_CTL_NUM_TAG_DFLT) | - FIELD_SET(CFG_BLK_MISC_CTL_RSVD_3_MASK, - CFG_BLK_MISC_CTL_RSVD_3_DFLT) | - FIELD_SET(CFG_BLK_MISC_CTL_RQ_METERING_MULTIPLIER_MASK, - EQDMA_CFG_BLK_MISC_CTL_RQ_METERING_MUL); - qdma_reg_write(dev_hndl, EQDMA_CFG_BLK_MISC_CTL_ADDR, reg_val); - reg_val = qdma_reg_read(dev_hndl, EQDMA_CFG_BLK_MISC_CTL_ADDR); - qdma_log_info("%s: reg = 0x%08X val = 0x%08X\n", - __func__, EQDMA_CFG_BLK_MISC_CTL_ADDR, reg_val); - -#define EQDMA_PFTCH_CFG_EVT_PFTH_FL_TH 256 -#define C2H_PFCH_CFG_FL_TH_DFLT 256 - - reg_val = - FIELD_SET(C2H_PFCH_CFG_EVTFL_TH_MASK, - EQDMA_PFTCH_CFG_EVT_PFTH_FL_TH) | - FIELD_SET(C2H_PFCH_CFG_FL_TH_MASK, C2H_PFCH_CFG_FL_TH_DFLT); - - qdma_reg_write(dev_hndl, EQDMA_C2H_PFCH_CFG_ADDR, reg_val); - reg_val = qdma_reg_read(dev_hndl, EQDMA_C2H_PFCH_CFG_ADDR); - qdma_log_info("%s: reg = 0x%08X val = 0x%08X\n", - __func__, EQDMA_C2H_PFCH_CFG_ADDR, reg_val); - -#define EQDMA_C2H_PFCH_CFG_1_QCNT_MASK (EQDMA_PFTCH_CACHE_DEPTH - 4) -#define EQDMA_C2H_PFCH_CFG_1_EVNT_QCNT_TH EQDMA_C2H_PFCH_CFG_1_QCNT_MASK - pfch_cache_dpth = qdma_reg_read(dev_hndl, - EQDMA_C2H_PFCH_CACHE_DEPTH_ADDR); - - reg_val = - FIELD_SET(C2H_PFCH_CFG_1_EVT_QCNT_TH_MASK, - (pfch_cache_dpth - 4)) | - FIELD_SET(C2H_PFCH_CFG_1_QCNT_MASK, (pfch_cache_dpth - 4)); - qdma_reg_write(dev_hndl, EQDMA_C2H_PFCH_CFG_1_ADDR, reg_val); - reg_val = qdma_reg_read(dev_hndl, EQDMA_C2H_PFCH_CFG_1_ADDR); - qdma_log_info("%s: reg = 0x%08X val = 0x%08X\n", - __func__, EQDMA_C2H_PFCH_CFG_1_ADDR, reg_val); - -#define EQDMA_C2H_PFCH_CFG_2_FENCE_EN 1 -#define C2H_PFCH_CFG_2_RSVD_DFLT 0 -#define C2H_PFCH_CFG_2_VAR_DESC_NO_DROP_DFLT 0 -#define C2H_PFCH_CFG_2_LL_SZ_TH_DFLT 1024 -#define C2H_PFCH_CFG_2_VAR_DESC_NUM 15 -#define C2H_PFCH_CFG_2_NUM_DFLT 8 - - reg_val = - FIELD_SET(C2H_PFCH_CFG_2_FENCE_MASK, - EQDMA_C2H_PFCH_CFG_2_FENCE_EN) | - FIELD_SET(C2H_PFCH_CFG_2_RSVD_MASK, C2H_PFCH_CFG_2_RSVD_DFLT) | - FIELD_SET(C2H_PFCH_CFG_2_VAR_DESC_NO_DROP_MASK, - C2H_PFCH_CFG_2_VAR_DESC_NO_DROP_DFLT) | - FIELD_SET(C2H_PFCH_CFG_2_LL_SZ_TH_MASK, - C2H_PFCH_CFG_2_LL_SZ_TH_DFLT) | - FIELD_SET(C2H_PFCH_CFG_2_VAR_DESC_NUM_MASK, - C2H_PFCH_CFG_2_VAR_DESC_NUM) | - FIELD_SET(C2H_PFCH_CFG_2_NUM_MASK, C2H_PFCH_CFG_2_NUM_DFLT); - qdma_reg_write(dev_hndl, EQDMA_C2H_PFCH_CFG_2_ADDR, reg_val); - reg_val = qdma_reg_read(dev_hndl, EQDMA_C2H_PFCH_CFG_2_ADDR); - qdma_log_info("%s: reg = 0x%08X val = 0x%08X\n", - __func__, EQDMA_C2H_PFCH_CFG_2_ADDR, reg_val); -#define PFCH_CFG_3_RSVD_DFLT 0 -#define PFCH_CFG_3_VAR_DESC_FL_FREE_CNT_TH_DFLT 256 -#define PFCH_CFG_3_VAR_DESC_LG_PKT_CAM_CN_TH_DFLT 0 - - - reg_val = - FIELD_SET(PFCH_CFG_3_RSVD_MASK, PFCH_CFG_3_RSVD_DFLT) | - FIELD_SET(PFCH_CFG_3_VAR_DESC_FL_FREE_CNT_TH_MASK, - PFCH_CFG_3_VAR_DESC_FL_FREE_CNT_TH_DFLT) | - FIELD_SET(PFCH_CFG_3_VAR_DESC_LG_PKT_CAM_CN_TH_MASK, - PFCH_CFG_3_VAR_DESC_LG_PKT_CAM_CN_TH_DFLT); - qdma_reg_write(dev_hndl, EQDMA_PFCH_CFG_3_ADDR, reg_val); - reg_val = qdma_reg_read(dev_hndl, EQDMA_PFCH_CFG_3_ADDR); - qdma_log_info("%s: reg = 0x%08X val = 0x%08X\n", - __func__, EQDMA_C2H_PFCH_CFG_2_ADDR, reg_val); -#define EQDMA_PFCH_CFG_4_GLB_EVT_TIMER_TICK 64 -#define PFCH_CFG_4_DISABLE_GLB_EVT_TIMER_DFLT 0 -#define EQDMA_PFCH_CFG_4_EVT_TIMER_TICK 400 -#define PFCH_CFG_4_DISABLE_EVT_TIMER_DFLT 0 - - - reg_val = - FIELD_SET(PFCH_CFG_4_GLB_EVT_TIMER_TICK_MASK, - EQDMA_PFCH_CFG_4_GLB_EVT_TIMER_TICK) | - FIELD_SET(PFCH_CFG_4_DISABLE_GLB_EVT_TIMER_MASK, - PFCH_CFG_4_DISABLE_GLB_EVT_TIMER_DFLT) | - FIELD_SET(PFCH_CFG_4_EVT_TIMER_TICK_MASK, - EQDMA_PFCH_CFG_4_EVT_TIMER_TICK) | - FIELD_SET(PFCH_CFG_4_DISABLE_EVT_TIMER_MASK, - PFCH_CFG_4_DISABLE_EVT_TIMER_DFLT); - qdma_reg_write(dev_hndl, EQDMA_PFCH_CFG_4_ADDR, reg_val); - reg_val = qdma_reg_read(dev_hndl, EQDMA_PFCH_CFG_4_ADDR); - qdma_log_info("%s: reg = 0x%08X val = 0x%08X\n", - __func__, EQDMA_PFCH_CFG_4_ADDR, reg_val); -/**************** SET_2 *******************/ -#define C2H_CRDT_COAL_CFG_1_RSVD_1_DFLT 0 -#define C2H_CRDT_COAL_CFG_1_PLD_FIFO_TH_DFLT 16 -#define EQDMA_C2H_CRDT_COAL_CFG_1_TIMER_TH 16 //64 - - - reg_val = - FIELD_SET(C2H_CRDT_COAL_CFG_1_RSVD_1_MASK, - C2H_CRDT_COAL_CFG_1_RSVD_1_DFLT) | - FIELD_SET(C2H_CRDT_COAL_CFG_1_PLD_FIFO_TH_MASK, - C2H_CRDT_COAL_CFG_1_PLD_FIFO_TH_DFLT) | - FIELD_SET(C2H_CRDT_COAL_CFG_1_TIMER_TH_MASK, - EQDMA_C2H_CRDT_COAL_CFG_1_TIMER_TH); - qdma_reg_write(dev_hndl, EQDMA_C2H_CRDT_COAL_CFG_1_ADDR, reg_val); - reg_val = qdma_reg_read(dev_hndl, EQDMA_C2H_CRDT_COAL_CFG_1_ADDR); - qdma_log_info("%s: reg = 0x%08X val = 0x%08X\n", - __func__, EQDMA_C2H_CRDT_COAL_CFG_1_ADDR, reg_val); -#define C2H_CRDT_COAL_CFG_2_RSVD_1_DFLT 0 -#define EQDMA_C2H_CRDT_COAL_CFG_2_FIFO_TH (EQDMA_PFTCH_CACHE_DEPTH - 8) -#define C2H_CRDT_COAL_CFG_2_RESERVED1_DFLT 0 -#define EQDMA_C2H_CRDT_COAL_CFG_2_CRDT_TH 96 - - reg_val = - FIELD_SET(C2H_CRDT_COAL_CFG_2_RSVD_1_MASK, - C2H_CRDT_COAL_CFG_2_RSVD_1_DFLT) | - FIELD_SET(C2H_CRDT_COAL_CFG_2_FIFO_TH_MASK, - (pfch_cache_dpth - 8)) | - FIELD_SET(C2H_CRDT_COAL_CFG_2_RESERVED1_MASK, - C2H_CRDT_COAL_CFG_2_RESERVED1_DFLT) | - FIELD_SET(C2H_CRDT_COAL_CFG_2_NT_TH_MASK, - EQDMA_C2H_CRDT_COAL_CFG_2_CRDT_TH); - qdma_reg_write(dev_hndl, EQDMA_C2H_CRDT_COAL_CFG_2_ADDR, reg_val); - reg_val = qdma_reg_read(dev_hndl, EQDMA_C2H_CRDT_COAL_CFG_2_ADDR); - qdma_log_info("%s: reg = 0x%08X val = 0x%08X\n", - __func__, EQDMA_C2H_CRDT_COAL_CFG_2_ADDR, reg_val); - -/**************** SET_3 *******************/ -#define EQDMA_GLBL2_RRQ_PCIE_THROT_REQ_EN 0 -#define GLBL2_RRQ_PCIE_THROT_REQ_DFLT 192 -#define GLBL2_RRQ_PCIE_THROT_DAT_EN_DFLT 1 -#define GLBL2_RRQ_PCIE_THROT_DAT_DFLT 20480 - - - reg_val = - FIELD_SET(GLBL2_RRQ_PCIE_THROT_REQ_EN_MASK, - EQDMA_GLBL2_RRQ_PCIE_THROT_REQ_EN) | - FIELD_SET(GLBL2_RRQ_PCIE_THROT_REQ_MASK, - GLBL2_RRQ_PCIE_THROT_REQ_DFLT) | - FIELD_SET(GLBL2_RRQ_PCIE_THROT_DAT_EN_MASK, - GLBL2_RRQ_PCIE_THROT_DAT_EN_DFLT) | - FIELD_SET(GLBL2_RRQ_PCIE_THROT_DAT_MASK, - GLBL2_RRQ_PCIE_THROT_DAT_DFLT); - qdma_reg_write(dev_hndl, EQDMA_GLBL2_RRQ_PCIE_THROT_ADDR, reg_val); - reg_val = qdma_reg_read(dev_hndl, EQDMA_GLBL2_RRQ_PCIE_THROT_ADDR); - qdma_log_info("%s: reg = 0x%08X val = 0x%08X\n", - __func__, EQDMA_GLBL2_RRQ_PCIE_THROT_ADDR, reg_val); -#define GLBL2_RRQ_AXIMM_THROT_REQ_EN_DFLT 0 -#define GLBL2_RRQ_AXIMM_THROT_REQ_DFLT 0 -#define GLBL2_RRQ_AXIMM_THROT_DAT_EN_DFLT 0 -#define GLBL2_RRQ_AXIMM_THROT_DAT_DFLT 0 - - reg_val = - FIELD_SET(GLBL2_RRQ_AXIMM_THROT_REQ_EN_MASK, - GLBL2_RRQ_AXIMM_THROT_REQ_EN_DFLT) | - FIELD_SET(GLBL2_RRQ_AXIMM_THROT_REQ_MASK, - GLBL2_RRQ_AXIMM_THROT_REQ_DFLT) | - FIELD_SET(GLBL2_RRQ_AXIMM_THROT_DAT_EN_MASK, - GLBL2_RRQ_AXIMM_THROT_DAT_EN_DFLT) | - FIELD_SET(GLBL2_RRQ_AXIMM_THROT_DAT_MASK, - GLBL2_RRQ_AXIMM_THROT_DAT_DFLT); - qdma_reg_write(dev_hndl, EQDMA_GLBL2_RRQ_AXIMM_THROT_ADDR, reg_val); - reg_val = qdma_reg_read(dev_hndl, EQDMA_GLBL2_RRQ_AXIMM_THROT_ADDR); - qdma_log_info("%s: reg = 0x%08X val = 0x%08X\n", - __func__, EQDMA_GLBL2_RRQ_AXIMM_THROT_ADDR, reg_val); -#define GLBL2_RRQ_BRG_THROT_REQ_EN_DFLT 1 -#define GLBL2_RRQ_BRG_THROT_REQ_DFLT GLBL2_RRQ_PCIE_THROT_REQ_DFLT -#define GLBL2_RRQ_BRG_THROT_DAT_EN_DFLT 1 - - - reg_val = qdma_reg_read(dev_hndl, EQDMA_GLBL2_RRQ_PCIE_THROT_ADDR); - qdma_log_info("%s: BF reg = 0x%08X val = 0x%08X\n", - __func__, EQDMA_GLBL2_RRQ_PCIE_THROT_ADDR, reg_val); - data_th = FIELD_GET(GLBL2_RRQ_PCIE_THROT_DAT_MASK, reg_val); - - reg_val = - FIELD_SET(GLBL2_RRQ_BRG_THROT_REQ_EN_MASK, - GLBL2_RRQ_BRG_THROT_REQ_EN_DFLT) | - FIELD_SET(GLBL2_RRQ_BRG_THROT_REQ_MASK, - GLBL2_RRQ_BRG_THROT_REQ_DFLT) | - FIELD_SET(GLBL2_RRQ_BRG_THROT_DAT_EN_MASK, - GLBL2_RRQ_BRG_THROT_DAT_EN_DFLT) | - FIELD_SET(GLBL2_RRQ_BRG_THROT_DAT_MASK, data_th); - qdma_reg_write(dev_hndl, EQDMA_GLBL2_RRQ_BRG_THROT_ADDR, reg_val); - reg_val = qdma_reg_read(dev_hndl, EQDMA_GLBL2_RRQ_BRG_THROT_ADDR); - qdma_log_info("%s: reg = 0x%08X val = 0x%08X\n", - __func__, EQDMA_GLBL2_RRQ_BRG_THROT_ADDR, reg_val); - -/******************* SET_4 *************************/ -#define EQDMA_H2C_REQ_THROT_PCIE_EN_REQ 1 -#define EQDMA_H2C_REQ_THROT_PCIE_REQ_TH GLBL2_RRQ_PCIE_THROT_REQ_DFLT -#define EQDMA_H2C_REQ_THROT_PCIE_EN_DATA 1 -#define EQDMA_H2C_REQ_THROT_PCIE_DATA_TH 24576 - - reg_val = - FIELD_SET(H2C_REQ_THROT_PCIE_EN_REQ_MASK, - EQDMA_H2C_REQ_THROT_PCIE_EN_REQ) | - FIELD_SET(H2C_REQ_THROT_PCIE_MASK, - EQDMA_H2C_REQ_THROT_PCIE_REQ_TH) | - FIELD_SET(H2C_REQ_THROT_PCIE_EN_DATA_MASK, - EQDMA_H2C_REQ_THROT_PCIE_EN_DATA) | - FIELD_SET(H2C_REQ_THROT_PCIE_DATA_THRESH_MASK, - EQDMA_H2C_REQ_THROT_PCIE_DATA_TH); - qdma_reg_write(dev_hndl, EQDMA_H2C_REQ_THROT_PCIE_ADDR, reg_val); - reg_val = qdma_reg_read(dev_hndl, EQDMA_H2C_REQ_THROT_PCIE_ADDR); - qdma_log_info("%s: reg = 0x%08X val = 0x%08X\n", - __func__, EQDMA_H2C_REQ_THROT_PCIE_ADDR, reg_val); -#define EQDMA_H2C_REQ_THROT_AXIMM_EN_REQ 1 -#define EQDMA_H2C_REQ_THROT_AXIMM_REQ_TH 64 -#define EQDMA_H2C_REQ_THROT_AXIMM_EN_DATA 1 -#define EQDMA_H2C_REQ_THROT_AXIMM_DATA_TH 16384 - - reg_val = - FIELD_SET(H2C_REQ_THROT_AXIMM_EN_REQ_MASK, - EQDMA_H2C_REQ_THROT_AXIMM_EN_REQ) | - FIELD_SET(H2C_REQ_THROT_AXIMM_MASK, - EQDMA_H2C_REQ_THROT_AXIMM_REQ_TH) | - FIELD_SET(H2C_REQ_THROT_AXIMM_EN_DATA_MASK, - EQDMA_H2C_REQ_THROT_AXIMM_EN_DATA) | - FIELD_SET(H2C_REQ_THROT_AXIMM_DATA_THRESH_MASK, - EQDMA_H2C_REQ_THROT_AXIMM_DATA_TH); - qdma_reg_write(dev_hndl, EQDMA_H2C_REQ_THROT_AXIMM_ADDR, reg_val); - reg_val = qdma_reg_read(dev_hndl, EQDMA_H2C_REQ_THROT_AXIMM_ADDR); - qdma_log_info("%s: reg = 0x%08X val = 0x%08X\n", - __func__, EQDMA_H2C_REQ_THROT_AXIMM_ADDR, reg_val); - -#define H2C_MM_DATA_THROTTLE_RSVD_1_DFLT 0 -#define EQDMA_H2C_MM_DATA_TH_EN GLBL2_RRQ_PCIE_THROT_DAT_EN_DFLT -#define EQDMA_H2C_MM_DATA_TH GLBL2_RRQ_PCIE_THROT_DAT_DFLT - - reg_val = - FIELD_SET(H2C_MM_DATA_THROTTLE_RSVD_1_MASK, - H2C_MM_DATA_THROTTLE_RSVD_1_DFLT) | - FIELD_SET(H2C_MM_DATA_THROTTLE_DAT_EN_MASK, - EQDMA_H2C_MM_DATA_TH_EN) | - FIELD_SET(H2C_MM_DATA_THROTTLE_DAT_MASK, EQDMA_H2C_MM_DATA_TH); - qdma_reg_write(dev_hndl, EQDMA_H2C_MM_DATA_THROTTLE_ADDR, reg_val); - reg_val = qdma_reg_read(dev_hndl, EQDMA_H2C_MM_DATA_THROTTLE_ADDR); - qdma_log_info("%s: reg = 0x%08X val = 0x%08X\n", - __func__, EQDMA_H2C_MM_DATA_THROTTLE_ADDR, reg_val); - -} - - -/* - * eqdma_indirect_reg_invalidate() - helper function to invalidate indirect - * context registers. - * - * return -QDMA_ERR_HWACC_BUSY_TIMEOUT if register - * value didn't match, QDMA_SUCCESS other wise - */ -static int eqdma_indirect_reg_invalidate(void *dev_hndl, - enum ind_ctxt_cmd_sel sel, uint16_t hw_qid) -{ - union qdma_ind_ctxt_cmd cmd; - - qdma_reg_access_lock(dev_hndl); - - /* set command register */ - cmd.word = 0; - cmd.bits.qid = hw_qid; - cmd.bits.op = QDMA_CTXT_CMD_INV; - cmd.bits.sel = sel; - qdma_reg_write(dev_hndl, EQDMA_IND_CTXT_CMD_ADDR, cmd.word); - - /* check if the operation went through well */ - if (hw_monitor_reg(dev_hndl, EQDMA_IND_CTXT_CMD_ADDR, - IND_CTXT_CMD_BUSY_MASK, 0, - QDMA_REG_POLL_DFLT_INTERVAL_US, - QDMA_REG_POLL_DFLT_TIMEOUT_US)) { - qdma_reg_access_release(dev_hndl); - qdma_log_error("%s: hw_monitor_reg failed with err:%d\n", - __func__, - -QDMA_ERR_HWACC_BUSY_TIMEOUT); - return -QDMA_ERR_HWACC_BUSY_TIMEOUT; - } - - qdma_reg_access_release(dev_hndl); - - return QDMA_SUCCESS; -} - -/* - * eqdma_indirect_reg_clear() - helper function to clear indirect - * context registers. - * - * return -QDMA_ERR_HWACC_BUSY_TIMEOUT if register - * value didn't match, QDMA_SUCCESS other wise - */ -static int eqdma_indirect_reg_clear(void *dev_hndl, - enum ind_ctxt_cmd_sel sel, uint16_t hw_qid) -{ - union qdma_ind_ctxt_cmd cmd; - - qdma_reg_access_lock(dev_hndl); - - /* set command register */ - cmd.word = 0; - cmd.bits.qid = hw_qid; - cmd.bits.op = QDMA_CTXT_CMD_CLR; - cmd.bits.sel = sel; - qdma_reg_write(dev_hndl, EQDMA_IND_CTXT_CMD_ADDR, cmd.word); - - /* check if the operation went through well */ - if (hw_monitor_reg(dev_hndl, EQDMA_IND_CTXT_CMD_ADDR, - IND_CTXT_CMD_BUSY_MASK, 0, - QDMA_REG_POLL_DFLT_INTERVAL_US, - QDMA_REG_POLL_DFLT_TIMEOUT_US)) { - qdma_reg_access_release(dev_hndl); - qdma_log_error("%s: hw_monitor_reg failed with err:%d\n", - __func__, - -QDMA_ERR_HWACC_BUSY_TIMEOUT); - return -QDMA_ERR_HWACC_BUSY_TIMEOUT; - } - - qdma_reg_access_release(dev_hndl); - - return QDMA_SUCCESS; -} - -/* - * eqdma_indirect_reg_read() - helper function to read indirect - * context registers. - * - * return -QDMA_ERR_HWACC_BUSY_TIMEOUT if register - * value didn't match, QDMA_SUCCESS other wise - */ -static int eqdma_indirect_reg_read(void *dev_hndl, enum ind_ctxt_cmd_sel sel, - uint16_t hw_qid, uint32_t cnt, uint32_t *data) -{ - uint32_t index = 0, reg_addr = EQDMA_IND_CTXT_DATA_ADDR; - union qdma_ind_ctxt_cmd cmd; - - qdma_reg_access_lock(dev_hndl); - - /* set command register */ - cmd.word = 0; - cmd.bits.qid = hw_qid; - cmd.bits.op = QDMA_CTXT_CMD_RD; - cmd.bits.sel = sel; - - qdma_reg_write(dev_hndl, EQDMA_IND_CTXT_CMD_ADDR, cmd.word); - - /* check if the operation went through well */ - if (hw_monitor_reg(dev_hndl, EQDMA_IND_CTXT_CMD_ADDR, - IND_CTXT_CMD_BUSY_MASK, 0, - QDMA_REG_POLL_DFLT_INTERVAL_US, - QDMA_REG_POLL_DFLT_TIMEOUT_US)) { - qdma_reg_access_release(dev_hndl); - qdma_log_error("%s: hw_monitor_reg failed with err:%d\n", - __func__, - -QDMA_ERR_HWACC_BUSY_TIMEOUT); - return -QDMA_ERR_HWACC_BUSY_TIMEOUT; - } - - for (index = 0; index < cnt; index++, reg_addr += sizeof(uint32_t)) - data[index] = qdma_reg_read(dev_hndl, reg_addr); - - qdma_reg_access_release(dev_hndl); - - return QDMA_SUCCESS; -} - -/* - * eqdma_indirect_reg_write() - helper function to write indirect - * context registers. - * - * return -QDMA_ERR_HWACC_BUSY_TIMEOUT if register - * value didn't match, QDMA_SUCCESS other wise - */ -static int eqdma_indirect_reg_write(void *dev_hndl, enum ind_ctxt_cmd_sel sel, - uint16_t hw_qid, uint32_t *data, uint16_t cnt) -{ - uint32_t index, reg_addr; - struct qdma_indirect_ctxt_regs regs; - uint32_t *wr_data = (uint32_t *)®s; - - qdma_reg_access_lock(dev_hndl); - - /* write the context data */ - for (index = 0; index < QDMA_IND_CTXT_DATA_NUM_REGS; index++) { - if (index < cnt) - regs.qdma_ind_ctxt_data[index] = data[index]; - else - regs.qdma_ind_ctxt_data[index] = 0; - regs.qdma_ind_ctxt_mask[index] = 0xFFFFFFFF; - } - - regs.cmd.word = 0; - regs.cmd.bits.qid = hw_qid; - regs.cmd.bits.op = QDMA_CTXT_CMD_WR; - regs.cmd.bits.sel = sel; - reg_addr = EQDMA_IND_CTXT_DATA_ADDR; - - for (index = 0; index < ((2 * QDMA_IND_CTXT_DATA_NUM_REGS) + 1); - index++, reg_addr += sizeof(uint32_t)) - qdma_reg_write(dev_hndl, reg_addr, wr_data[index]); - - /* check if the operation went through well */ - if (hw_monitor_reg(dev_hndl, EQDMA_IND_CTXT_CMD_ADDR, - IND_CTXT_CMD_BUSY_MASK, 0, - QDMA_REG_POLL_DFLT_INTERVAL_US, - QDMA_REG_POLL_DFLT_TIMEOUT_US)) { - qdma_reg_access_release(dev_hndl); - qdma_log_error("%s: hw_monitor_reg failed with err:%d\n", - __func__, - -QDMA_ERR_HWACC_BUSY_TIMEOUT); - return -QDMA_ERR_HWACC_BUSY_TIMEOUT; - } - - qdma_reg_access_release(dev_hndl); - - return QDMA_SUCCESS; -} - -int eqdma_get_ip_version(void *dev_hndl, uint8_t is_vf, - uint32_t *ip_version) -{ - uint32_t ver_reg_val = 0; - uint32_t reg_addr = (is_vf) ? EQDMA_OFFSET_VF_VERSION : - EQDMA_GLBL2_MISC_CAP_ADDR; - - if (!dev_hndl) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - ver_reg_val = qdma_reg_read(dev_hndl, reg_addr); - - if (!is_vf) { - *ip_version = - FIELD_GET(EQDMA_GLBL2_IP_VERSION_MASK, - ver_reg_val); - } else { - *ip_version = - FIELD_GET(EQDMA_GLBL2_VF_IP_VERSION_MASK, - ver_reg_val); - } - - return QDMA_SUCCESS; -} - -/* - * eqdma_fill_sw_ctxt() - Helper function to fill sw context into structure - * - */ -static void eqdma_fill_sw_ctxt(struct qdma_descq_sw_ctxt *sw_ctxt) -{ - int i = 0; - - eqdma_sw_ctxt_entries[i++].value = sw_ctxt->pidx; - eqdma_sw_ctxt_entries[i++].value = sw_ctxt->irq_arm; - eqdma_sw_ctxt_entries[i++].value = sw_ctxt->fnc_id; - eqdma_sw_ctxt_entries[i++].value = sw_ctxt->qen; - eqdma_sw_ctxt_entries[i++].value = sw_ctxt->frcd_en; - eqdma_sw_ctxt_entries[i++].value = sw_ctxt->wbi_chk; - eqdma_sw_ctxt_entries[i++].value = sw_ctxt->wbi_intvl_en; - eqdma_sw_ctxt_entries[i++].value = sw_ctxt->at; - eqdma_sw_ctxt_entries[i++].value = sw_ctxt->fetch_max; - eqdma_sw_ctxt_entries[i++].value = sw_ctxt->rngsz_idx; - eqdma_sw_ctxt_entries[i++].value = sw_ctxt->desc_sz; - eqdma_sw_ctxt_entries[i++].value = sw_ctxt->bypass; - eqdma_sw_ctxt_entries[i++].value = sw_ctxt->mm_chn; - eqdma_sw_ctxt_entries[i++].value = sw_ctxt->wbk_en; - eqdma_sw_ctxt_entries[i++].value = sw_ctxt->irq_en; - eqdma_sw_ctxt_entries[i++].value = sw_ctxt->port_id; - eqdma_sw_ctxt_entries[i++].value = sw_ctxt->irq_no_last; - eqdma_sw_ctxt_entries[i++].value = sw_ctxt->err; - eqdma_sw_ctxt_entries[i++].value = sw_ctxt->err_wb_sent; - eqdma_sw_ctxt_entries[i++].value = sw_ctxt->irq_req; - eqdma_sw_ctxt_entries[i++].value = sw_ctxt->mrkr_dis; - eqdma_sw_ctxt_entries[i++].value = sw_ctxt->is_mm; - eqdma_sw_ctxt_entries[i++].value = sw_ctxt->ring_bs_addr & 0xFFFFFFFF; - eqdma_sw_ctxt_entries[i++].value = - (sw_ctxt->ring_bs_addr >> 32) & 0xFFFFFFFF; - eqdma_sw_ctxt_entries[i++].value = sw_ctxt->vec; - eqdma_sw_ctxt_entries[i++].value = sw_ctxt->intr_aggr; - eqdma_sw_ctxt_entries[i++].value = sw_ctxt->dis_intr_on_vf; - eqdma_sw_ctxt_entries[i++].value = sw_ctxt->pack_byp_out; - eqdma_sw_ctxt_entries[i++].value = sw_ctxt->irq_byp; - -} - -/* - * eqdma_fill_cmpt_ctxt() - Helper function to fill completion context - * into structure - * - */ -static void eqdma_fill_cmpt_ctxt(struct qdma_descq_cmpt_ctxt *cmpt_ctxt) -{ - int i = 0; - - eqdma_cmpt_ctxt_entries[i++].value = cmpt_ctxt->en_stat_desc; - eqdma_cmpt_ctxt_entries[i++].value = cmpt_ctxt->en_int; - eqdma_cmpt_ctxt_entries[i++].value = cmpt_ctxt->trig_mode; - eqdma_cmpt_ctxt_entries[i++].value = cmpt_ctxt->fnc_id; - eqdma_cmpt_ctxt_entries[i++].value = cmpt_ctxt->counter_idx; - eqdma_cmpt_ctxt_entries[i++].value = cmpt_ctxt->timer_idx; - eqdma_cmpt_ctxt_entries[i++].value = cmpt_ctxt->in_st; - eqdma_cmpt_ctxt_entries[i++].value = cmpt_ctxt->color; - eqdma_cmpt_ctxt_entries[i++].value = cmpt_ctxt->ringsz_idx; - eqdma_cmpt_ctxt_entries[i++].value = (uint32_t)FIELD_GET( - EQDMA_COMPL_CTXT_BADDR_HIGH_L_MASK, - cmpt_ctxt->bs_addr); - eqdma_cmpt_ctxt_entries[i++].value = (uint32_t)FIELD_GET( - EQDMA_COMPL_CTXT_BADDR_HIGH_H_MASK, - cmpt_ctxt->bs_addr); - eqdma_cmpt_ctxt_entries[i++].value = cmpt_ctxt->desc_sz; - eqdma_cmpt_ctxt_entries[i++].value = cmpt_ctxt->pidx; - eqdma_cmpt_ctxt_entries[i++].value = cmpt_ctxt->cidx; - eqdma_cmpt_ctxt_entries[i++].value = cmpt_ctxt->valid; - eqdma_cmpt_ctxt_entries[i++].value = cmpt_ctxt->err; - eqdma_cmpt_ctxt_entries[i++].value = cmpt_ctxt->user_trig_pend; - eqdma_cmpt_ctxt_entries[i++].value = cmpt_ctxt->timer_running; - eqdma_cmpt_ctxt_entries[i++].value = cmpt_ctxt->full_upd; - eqdma_cmpt_ctxt_entries[i++].value = cmpt_ctxt->ovf_chk_dis; - eqdma_cmpt_ctxt_entries[i++].value = cmpt_ctxt->at; - eqdma_cmpt_ctxt_entries[i++].value = cmpt_ctxt->vec; - eqdma_cmpt_ctxt_entries[i++].value = cmpt_ctxt->int_aggr; - eqdma_cmpt_ctxt_entries[i++].value = cmpt_ctxt->dis_intr_on_vf; - eqdma_cmpt_ctxt_entries[i++].value = cmpt_ctxt->dir_c2h; - eqdma_cmpt_ctxt_entries[i++].value = (uint32_t)FIELD_GET( - EQDMA_COMPL_CTXT_BADDR_LOW_MASK, - cmpt_ctxt->bs_addr); - eqdma_cmpt_ctxt_entries[i++].value = cmpt_ctxt->sh_cmpt; -} - -/* - * eqdma_fill_hw_ctxt() - Helper function to fill HW context into structure - * - */ -static void eqdma_fill_hw_ctxt(struct qdma_descq_hw_ctxt *hw_ctxt) -{ - int i = 0; - - eqdma_hw_ctxt_entries[i++].value = hw_ctxt->cidx; - eqdma_hw_ctxt_entries[i++].value = hw_ctxt->crd_use; - eqdma_hw_ctxt_entries[i++].value = hw_ctxt->dsc_pend; - eqdma_hw_ctxt_entries[i++].value = hw_ctxt->idl_stp_b; - eqdma_hw_ctxt_entries[i++].value = hw_ctxt->evt_pnd; - eqdma_hw_ctxt_entries[i++].value = hw_ctxt->fetch_pnd; -} - -/* - * eqdma_fill_credit_ctxt() - Helper function to fill Credit context - * into structure - * - */ -static void eqdma_fill_credit_ctxt(struct qdma_descq_credit_ctxt *cr_ctxt) -{ - eqdma_credit_ctxt_entries[0].value = cr_ctxt->credit; -} - -/* - * eqdma_fill_pfetch_ctxt() - Helper function to fill Prefetch context - * into structure - * - */ -static void eqdma_fill_pfetch_ctxt(struct qdma_descq_prefetch_ctxt - *pfetch_ctxt) -{ - int i = 0; - - eqdma_c2h_pftch_ctxt_entries[i++].value = pfetch_ctxt->bypass; - eqdma_c2h_pftch_ctxt_entries[i++].value = pfetch_ctxt->bufsz_idx; - eqdma_c2h_pftch_ctxt_entries[i++].value = pfetch_ctxt->port_id; - eqdma_c2h_pftch_ctxt_entries[i++].value = pfetch_ctxt->var_desc; - eqdma_c2h_pftch_ctxt_entries[i++].value = pfetch_ctxt->num_pftch; - eqdma_c2h_pftch_ctxt_entries[i++].value = pfetch_ctxt->err; - eqdma_c2h_pftch_ctxt_entries[i++].value = pfetch_ctxt->pfch_en; - eqdma_c2h_pftch_ctxt_entries[i++].value = pfetch_ctxt->pfch; - eqdma_c2h_pftch_ctxt_entries[i++].value = pfetch_ctxt->sw_crdt; - eqdma_c2h_pftch_ctxt_entries[i++].value = pfetch_ctxt->valid; -} - -/* - * eqdma_fill_fmap_ctxt() - Helper function to fill fmap context - * into structure - * - */ -static void eqdma_fill_fmap_ctxt(struct qdma_fmap_cfg *fmap_ctxt) -{ - eqdma_fmap_ctxt_entries[0].value = fmap_ctxt->qbase; - eqdma_fmap_ctxt_entries[1].value = fmap_ctxt->qmax; -} - -/* - * eqdma_fill_intr_ctxt() - Helper function to fill interrupt context - * into structure - * - */ -static void eqdma_fill_intr_ctxt(struct qdma_indirect_intr_ctxt *intr_ctxt) -{ - int i = 0; - - eqdma_ind_intr_ctxt_entries[i++].value = intr_ctxt->valid; - eqdma_ind_intr_ctxt_entries[i++].value = intr_ctxt->vec; - eqdma_ind_intr_ctxt_entries[i++].value = intr_ctxt->int_st; - eqdma_ind_intr_ctxt_entries[i++].value = intr_ctxt->color; - eqdma_ind_intr_ctxt_entries[i++].value = - intr_ctxt->baddr_4k & 0xFFFFFFFF; - eqdma_ind_intr_ctxt_entries[i++].value = - (intr_ctxt->baddr_4k >> 32) & 0xFFFFFFFF; - eqdma_ind_intr_ctxt_entries[i++].value = intr_ctxt->page_size; - eqdma_ind_intr_ctxt_entries[i++].value = intr_ctxt->pidx; - eqdma_ind_intr_ctxt_entries[i++].value = intr_ctxt->at; - eqdma_ind_intr_ctxt_entries[i++].value = intr_ctxt->func_id; -} - -/*****************************************************************************/ -/** - * eqdma_set_default_global_csr() - function to set the global CSR register to - * default values. The value can be modified later by using the set/get csr - * functions - * - * @dev_hndl: device handle - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -int eqdma_set_default_global_csr(void *dev_hndl) -{ - int rv = QDMA_SUCCESS; - - /* Default values */ - uint32_t cfg_val = 0, reg_val = 0; - uint32_t rng_sz[QDMA_NUM_RING_SIZES] = {2049, 65, 129, 193, 257, 385, - 513, 769, 1025, 1537, 3073, 4097, 6145, 8193, 12289, 16385}; - uint32_t tmr_cnt[QDMA_NUM_C2H_TIMERS] = {1, 2, 4, 5, 8, 10, 15, 20, 25, - 30, 50, 75, 100, 125, 150, 200}; - uint32_t cnt_th[QDMA_NUM_C2H_COUNTERS] = {2, 4, 8, 16, 24, 32, 48, 64, - 80, 96, 112, 128, 144, 160, 176, 192}; - uint32_t buf_sz[QDMA_NUM_C2H_BUFFER_SIZES] = {4096, 256, 512, 1024, - 2048, 3968, 4096, 4096, 4096, 4096, 4096, 4096, 4096, 8192, - 9018, 16384}; - struct qdma_dev_attributes dev_cap; - uint32_t eqdma_ip_version; - - if (!dev_hndl) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", __func__, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - eqdma_get_device_attributes(dev_hndl, &dev_cap); - - rv = eqdma_get_ip_version(dev_hndl, 0, &eqdma_ip_version); - if (rv != QDMA_SUCCESS) - return rv; - - /* Configuring CSR registers */ - /* Global ring sizes */ - qdma_write_csr_values(dev_hndl, EQDMA_GLBL_RNG_SZ_1_ADDR, 0, - QDMA_NUM_RING_SIZES, rng_sz); - - if (dev_cap.st_en || dev_cap.mm_cmpt_en) { - /* Counter thresholds */ - qdma_write_csr_values(dev_hndl, EQDMA_C2H_CNT_TH_ADDR, 0, - QDMA_NUM_C2H_COUNTERS, cnt_th); - - /* Timer Counters */ - qdma_write_csr_values(dev_hndl, EQDMA_C2H_TIMER_CNT_ADDR, 0, - QDMA_NUM_C2H_TIMERS, tmr_cnt); - - /* Writeback Interval */ - if (eqdma_ip_version == EQDMA_IP_VERSION_4) { - reg_val = - FIELD_SET(GLBL_DSC_CFG_MAXFETCH_MASK, - DEFAULT_MAX_DSC_FETCH) | - FIELD_SET(GLBL_DSC_CFG_WB_ACC_INT_MASK, - DEFAULT_WRB_INT); - - qdma_reg_write(dev_hndl, EQDMA_GLBL_DSC_CFG_ADDR, - reg_val); - } - } - - if (dev_cap.st_en) { - /* Buffer Sizes */ - qdma_write_csr_values(dev_hndl, EQDMA_C2H_BUF_SZ_ADDR, 0, - QDMA_NUM_C2H_BUFFER_SIZES, buf_sz); - - /* Prefetch Configuration */ - if (eqdma_ip_version == EQDMA_IP_VERSION_4) { - reg_val = qdma_reg_read(dev_hndl, - EQDMA_C2H_PFCH_CACHE_DEPTH_ADDR); - cfg_val = FIELD_GET(C2H_PFCH_CACHE_DEPTH_MASK, reg_val); - reg_val = FIELD_SET(C2H_PFCH_CFG_1_QCNT_MASK, - (cfg_val >> 2)) | - FIELD_SET(C2H_PFCH_CFG_1_EVT_QCNT_TH_MASK, - ((cfg_val >> 2) - 4)); - - qdma_reg_write(dev_hndl, EQDMA_C2H_PFCH_CFG_1_ADDR, - reg_val); - - reg_val = qdma_reg_read(dev_hndl, - EQDMA_C2H_PFCH_CFG_2_ADDR); - reg_val |= FIELD_SET(C2H_PFCH_CFG_2_FENCE_MASK, 1); - qdma_reg_write(dev_hndl, EQDMA_C2H_PFCH_CFG_2_ADDR, - reg_val); - } - - /* C2H interrupt timer tick */ - qdma_reg_write(dev_hndl, EQDMA_C2H_INT_TIMER_TICK_ADDR, - DEFAULT_C2H_INTR_TIMER_TICK); - - /* C2h Completion Coalesce Configuration */ - cfg_val = qdma_reg_read(dev_hndl, - EQDMA_C2H_WRB_COAL_BUF_DEPTH_ADDR); - reg_val = - FIELD_SET(C2H_WRB_COAL_CFG_TICK_CNT_MASK, - DEFAULT_CMPT_COAL_TIMER_CNT) | - FIELD_SET(C2H_WRB_COAL_CFG_TICK_VAL_MASK, - DEFAULT_CMPT_COAL_TIMER_TICK) | - FIELD_SET(C2H_WRB_COAL_CFG_MAX_BUF_SZ_MASK, cfg_val); - qdma_reg_write(dev_hndl, EQDMA_C2H_WRB_COAL_CFG_ADDR, reg_val); - - /* H2C throttle Configuration*/ - if (eqdma_ip_version == EQDMA_IP_VERSION_4) { - reg_val = - FIELD_SET(H2C_REQ_THROT_PCIE_DATA_THRESH_MASK, - EQDMA_H2C_THROT_DATA_THRESH) | - FIELD_SET(H2C_REQ_THROT_PCIE_EN_DATA_MASK, - EQDMA_THROT_EN_DATA) | - FIELD_SET(H2C_REQ_THROT_PCIE_MASK, - EQDMA_H2C_THROT_REQ_THRESH) | - FIELD_SET(H2C_REQ_THROT_PCIE_EN_REQ_MASK, - EQDMA_THROT_EN_REQ); - - qdma_reg_write(dev_hndl, EQDMA_H2C_REQ_THROT_PCIE_ADDR, - reg_val); - } - } - - if (eqdma_ip_version == EQDMA_IP_VERSION_5) - eqdma_set_perf_opt(dev_hndl); - return QDMA_SUCCESS; -} - -/* - * dump_eqdma_context() - Helper function to dump queue context into string - * - * return len - length of the string copied into buffer - */ -static int dump_eqdma_context(struct qdma_descq_context *queue_context, - uint8_t st, enum qdma_dev_q_type q_type, - char *buf, int buf_sz) -{ - int i = 0; - int n; - int len = 0; - int rv; - char banner[DEBGFS_LINE_SZ] = ""; - - if (queue_context == NULL) { - qdma_log_error("%s: queue_context is NULL, err:%d\n", - __func__, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - if (q_type == QDMA_DEV_Q_TYPE_CMPT) { - eqdma_fill_cmpt_ctxt(&queue_context->cmpt_ctxt); - } else if (q_type == QDMA_DEV_Q_TYPE_H2C) { - eqdma_fill_sw_ctxt(&queue_context->sw_ctxt); - eqdma_fill_hw_ctxt(&queue_context->hw_ctxt); - eqdma_fill_credit_ctxt(&queue_context->cr_ctxt); - } else if (q_type == QDMA_DEV_Q_TYPE_C2H) { - eqdma_fill_sw_ctxt(&queue_context->sw_ctxt); - eqdma_fill_hw_ctxt(&queue_context->hw_ctxt); - eqdma_fill_credit_ctxt(&queue_context->cr_ctxt); - if (st) { - eqdma_fill_pfetch_ctxt(&queue_context->pfetch_ctxt); - eqdma_fill_cmpt_ctxt(&queue_context->cmpt_ctxt); - } - } - - eqdma_fill_fmap_ctxt(&queue_context->fmap); - - if (q_type != QDMA_DEV_Q_TYPE_CMPT) { - for (i = 0; i < DEBGFS_LINE_SZ - 5; i++) { - rv = QDMA_SNPRINTF_S(banner + i, - (DEBGFS_LINE_SZ - i), - sizeof("-"), "-"); - if ((rv < 0) || (rv > (int)sizeof("-"))) { - qdma_log_error( - "%d:%s QDMA_SNPRINTF_S() failed, err:%d\n", - __LINE__, __func__, - rv); - goto INSUF_BUF_EXIT; - } - } - - /* SW context dump */ - n = sizeof(eqdma_sw_ctxt_entries) / - sizeof((eqdma_sw_ctxt_entries)[0]); - for (i = 0; i < n; i++) { - if ((len >= buf_sz) || - ((len + DEBGFS_LINE_SZ) >= buf_sz)) - goto INSUF_BUF_EXIT; - - if (i == 0) { - if ((len + (3 * DEBGFS_LINE_SZ)) >= buf_sz) - goto INSUF_BUF_EXIT; - rv = QDMA_SNPRINTF_S(buf + len, (buf_sz - len), - DEBGFS_LINE_SZ, "\n%s", banner); - if ((rv < 0) || (rv > DEBGFS_LINE_SZ)) { - qdma_log_error( - "%d:%s QDMA_SNPRINTF_S() failed, err:%d\n", - __LINE__, __func__, - rv); - goto INSUF_BUF_EXIT; - } - len += rv; - - rv = QDMA_SNPRINTF_S(buf + len, (buf_sz - len), - DEBGFS_LINE_SZ, "\n%40s", "SW Context"); - if ((rv < 0) || (rv > DEBGFS_LINE_SZ)) { - qdma_log_error( - "%d:%s QDMA_SNPRINTF_S() failed, err:%d\n", - __LINE__, __func__, - rv); - goto INSUF_BUF_EXIT; - } - len += rv; - - rv = QDMA_SNPRINTF_S(buf + len, (buf_sz - len), - DEBGFS_LINE_SZ, "\n%s\n", banner); - if ((rv < 0) || (rv > DEBGFS_LINE_SZ)) { - qdma_log_error( - "%d:%s QDMA_SNPRINTF_S() failed, err:%d\n", - __LINE__, __func__, - rv); - goto INSUF_BUF_EXIT; - } - len += rv; - } - - rv = QDMA_SNPRINTF_S(buf + len, (buf_sz - len), - DEBGFS_LINE_SZ, - "%-47s %#-10x %u\n", - eqdma_sw_ctxt_entries[i].name, - eqdma_sw_ctxt_entries[i].value, - eqdma_sw_ctxt_entries[i].value); - if ((rv < 0) || (rv > DEBGFS_LINE_SZ)) { - qdma_log_error( - "%d:%s QDMA_SNPRINTF_S() failed, err:%d\n", - __LINE__, __func__, - rv); - goto INSUF_BUF_EXIT; - } - len += rv; - } - - /* HW context dump */ - n = sizeof(eqdma_hw_ctxt_entries) / - sizeof((eqdma_hw_ctxt_entries)[0]); - for (i = 0; i < n; i++) { - if ((len >= buf_sz) || - ((len + DEBGFS_LINE_SZ) >= buf_sz)) - goto INSUF_BUF_EXIT; - - if (i == 0) { - if ((len + (3 * DEBGFS_LINE_SZ)) >= buf_sz) - goto INSUF_BUF_EXIT; - - rv = QDMA_SNPRINTF_S(buf + len, (buf_sz - len), - DEBGFS_LINE_SZ, "\n%s", banner); - if ((rv < 0) || (rv > DEBGFS_LINE_SZ)) { - qdma_log_error( - "%d:%s QDMA_SNPRINTF_S() failed, err:%d\n", - __LINE__, __func__, - rv); - goto INSUF_BUF_EXIT; - } - len += rv; - - rv = QDMA_SNPRINTF_S(buf + len, (buf_sz - len), - DEBGFS_LINE_SZ, "\n%40s", "HW Context"); - if ((rv < 0) || (rv > DEBGFS_LINE_SZ)) { - qdma_log_error( - "%d:%s QDMA_SNPRINTF_S() failed, err:%d\n", - __LINE__, __func__, - rv); - goto INSUF_BUF_EXIT; - } - len += rv; - - rv = QDMA_SNPRINTF_S(buf + len, (buf_sz - len), - DEBGFS_LINE_SZ, "\n%s\n", banner); - if ((rv < 0) || (rv > DEBGFS_LINE_SZ)) { - qdma_log_error( - "%d:%s QDMA_SNPRINTF_S() failed, err:%d\n", - __LINE__, __func__, - rv); - goto INSUF_BUF_EXIT; - } - len += rv; - } - - rv = QDMA_SNPRINTF_S(buf + len, (buf_sz - len), - DEBGFS_LINE_SZ, - "%-47s %#-10x %u\n", - eqdma_hw_ctxt_entries[i].name, - eqdma_hw_ctxt_entries[i].value, - eqdma_hw_ctxt_entries[i].value); - if ((rv < 0) || (rv > DEBGFS_LINE_SZ)) { - qdma_log_error( - "%d:%s QDMA_SNPRINTF_S() failed, err:%d\n", - __LINE__, __func__, - rv); - goto INSUF_BUF_EXIT; - } - len += rv; - } - - /* Credit context dump */ - n = sizeof(eqdma_credit_ctxt_entries) / - sizeof((eqdma_credit_ctxt_entries)[0]); - for (i = 0; i < n; i++) { - if ((len >= buf_sz) || - ((len + DEBGFS_LINE_SZ) >= buf_sz)) - goto INSUF_BUF_EXIT; - - if (i == 0) { - if ((len + (3 * DEBGFS_LINE_SZ)) >= buf_sz) - goto INSUF_BUF_EXIT; - - rv = QDMA_SNPRINTF_S(buf + len, (buf_sz - len), - DEBGFS_LINE_SZ, "\n%s", banner); - if ((rv < 0) || (rv > DEBGFS_LINE_SZ)) { - qdma_log_error( - "%d:%s QDMA_SNPRINTF_S() failed, err:%d\n", - __LINE__, __func__, - rv); - goto INSUF_BUF_EXIT; - } - len += rv; - - rv = QDMA_SNPRINTF_S(buf + len, (buf_sz - len), - DEBGFS_LINE_SZ, "\n%40s", - "Credit Context"); - if ((rv < 0) || (rv > DEBGFS_LINE_SZ)) { - qdma_log_error( - "%d:%s QDMA_SNPRINTF_S() failed, err:%d\n", - __LINE__, __func__, - rv); - goto INSUF_BUF_EXIT; - } - len += rv; - - rv = QDMA_SNPRINTF_S(buf + len, (buf_sz - len), - DEBGFS_LINE_SZ, "\n%s\n", banner); - if ((rv < 0) || (rv > DEBGFS_LINE_SZ)) { - qdma_log_error( - "%d:%s QDMA_SNPRINTF_S() failed, err:%d\n", - __LINE__, __func__, - rv); - goto INSUF_BUF_EXIT; - } - len += rv; - } - - rv = QDMA_SNPRINTF_S(buf + len, (buf_sz - len), - DEBGFS_LINE_SZ, - "%-47s %#-10x %u\n", - eqdma_credit_ctxt_entries[i].name, - eqdma_credit_ctxt_entries[i].value, - eqdma_credit_ctxt_entries[i].value); - if ((rv < 0) || (rv > DEBGFS_LINE_SZ)) { - qdma_log_error( - "%d:%s QDMA_SNPRINTF_S() failed, err:%d\n", - __LINE__, __func__, - rv); - goto INSUF_BUF_EXIT; - } - len += rv; - } - } - - if ((q_type == QDMA_DEV_Q_TYPE_CMPT) || - (st && q_type == QDMA_DEV_Q_TYPE_C2H)) { - /* Completion context dump */ - n = sizeof(eqdma_cmpt_ctxt_entries) / - sizeof((eqdma_cmpt_ctxt_entries)[0]); - for (i = 0; i < n; i++) { - if ((len >= buf_sz) || - ((len + DEBGFS_LINE_SZ) >= buf_sz)) - goto INSUF_BUF_EXIT; - - if (i == 0) { - if ((len + (3 * DEBGFS_LINE_SZ)) >= buf_sz) - goto INSUF_BUF_EXIT; - - rv = QDMA_SNPRINTF_S(buf + len, (buf_sz - len), - DEBGFS_LINE_SZ, "\n%s", banner); - if ((rv < 0) || (rv > DEBGFS_LINE_SZ)) { - qdma_log_error( - "%d:%s QDMA_SNPRINTF_S() failed, err:%d\n", - __LINE__, __func__, - rv); - goto INSUF_BUF_EXIT; - } - len += rv; - - rv = QDMA_SNPRINTF_S(buf + len, (buf_sz - len), - DEBGFS_LINE_SZ, "\n%40s", - "Completion Context"); - if ((rv < 0) || (rv > DEBGFS_LINE_SZ)) { - qdma_log_error( - "%d:%s QDMA_SNPRINTF_S() failed, err:%d\n", - __LINE__, __func__, - rv); - goto INSUF_BUF_EXIT; - } - len += rv; - - rv = QDMA_SNPRINTF_S(buf + len, (buf_sz - len), - DEBGFS_LINE_SZ, "\n%s\n", banner); - if ((rv < 0) || (rv > DEBGFS_LINE_SZ)) { - qdma_log_error( - "%d:%s QDMA_SNPRINTF_S() failed, err:%d\n", - __LINE__, __func__, - rv); - goto INSUF_BUF_EXIT; - } - len += rv; - } - - rv = QDMA_SNPRINTF_S(buf + len, (buf_sz - len), - DEBGFS_LINE_SZ, - "%-47s %#-10x %u\n", - eqdma_cmpt_ctxt_entries[i].name, - eqdma_cmpt_ctxt_entries[i].value, - eqdma_cmpt_ctxt_entries[i].value); - if ((rv < 0) || (rv > DEBGFS_LINE_SZ)) { - qdma_log_error( - "%d:%s QDMA_SNPRINTF_S() failed, err:%d\n", - __LINE__, __func__, - rv); - goto INSUF_BUF_EXIT; - } - len += rv; - } - } - - if (st && q_type == QDMA_DEV_Q_TYPE_C2H) { - /* Prefetch context dump */ - n = sizeof(eqdma_c2h_pftch_ctxt_entries) / - sizeof(eqdma_c2h_pftch_ctxt_entries[0]); - for (i = 0; i < n; i++) { - if ((len >= buf_sz) || - ((len + DEBGFS_LINE_SZ) >= buf_sz)) - goto INSUF_BUF_EXIT; - - if (i == 0) { - if ((len + (3 * DEBGFS_LINE_SZ)) >= buf_sz) - goto INSUF_BUF_EXIT; - - rv = QDMA_SNPRINTF_S(buf + len, (buf_sz - len), - DEBGFS_LINE_SZ, "\n%s", banner); - if ((rv < 0) || (rv > DEBGFS_LINE_SZ)) { - qdma_log_error( - "%d:%s QDMA_SNPRINTF_S() failed, err:%d\n", - __LINE__, __func__, - rv); - goto INSUF_BUF_EXIT; - } - len += rv; - - rv = QDMA_SNPRINTF_S(buf + len, (buf_sz - len), - DEBGFS_LINE_SZ, "\n%40s", - "Prefetch Context"); - if ((rv < 0) || (rv > DEBGFS_LINE_SZ)) { - qdma_log_error( - "%d:%s QDMA_SNPRINTF_S() failed, err:%d\n", - __LINE__, __func__, - rv); - goto INSUF_BUF_EXIT; - } - len += rv; - - rv = QDMA_SNPRINTF_S(buf + len, (buf_sz - len), - DEBGFS_LINE_SZ, "\n%s\n", banner); - if ((rv < 0) || (rv > DEBGFS_LINE_SZ)) { - qdma_log_error( - "%d:%s QDMA_SNPRINTF_S() failed, err:%d\n", - __LINE__, __func__, - rv); - goto INSUF_BUF_EXIT; - } - len += rv; - } - - rv = QDMA_SNPRINTF_S(buf + len, (buf_sz - len), - DEBGFS_LINE_SZ, - "%-47s %#-10x %u\n", - eqdma_c2h_pftch_ctxt_entries[i].name, - eqdma_c2h_pftch_ctxt_entries[i].value, - eqdma_c2h_pftch_ctxt_entries[i].value); - if ((rv < 0) || (rv > DEBGFS_LINE_SZ)) { - qdma_log_error( - "%d:%s QDMA_SNPRINTF_S() failed, err:%d\n", - __LINE__, __func__, - rv); - goto INSUF_BUF_EXIT; - } - len += rv; - } - } - - /* FMAP context dump */ - n = sizeof(eqdma_fmap_ctxt_entries) / - sizeof((eqdma_fmap_ctxt_entries)[0]); - for (i = 0; i < n; i++) { - if ((len >= buf_sz) || - ((len + DEBGFS_LINE_SZ) >= buf_sz)) - goto INSUF_BUF_EXIT; - - if (i == 0) { - if ((len + (3 * DEBGFS_LINE_SZ)) >= buf_sz) - goto INSUF_BUF_EXIT; - - rv = QDMA_SNPRINTF_S(buf + len, (buf_sz - len), - DEBGFS_LINE_SZ, "\n%s", banner); - if ((rv < 0) || (rv > DEBGFS_LINE_SZ)) { - qdma_log_error( - "%d:%s QDMA_SNPRINTF_S() failed, err:%d\n", - __LINE__, __func__, - rv); - goto INSUF_BUF_EXIT; - } - len += rv; - - rv = QDMA_SNPRINTF_S(buf + len, (buf_sz - len), - DEBGFS_LINE_SZ, "\n%40s", - "FMAP Context"); - if ((rv < 0) || (rv > DEBGFS_LINE_SZ)) { - qdma_log_error( - "%d:%s QDMA_SNPRINTF_S() failed, err:%d\n", - __LINE__, __func__, - rv); - goto INSUF_BUF_EXIT; - } - len += rv; - - rv = QDMA_SNPRINTF_S(buf + len, (buf_sz - len), - DEBGFS_LINE_SZ, "\n%s\n", banner); - if ((rv < 0) || (rv > DEBGFS_LINE_SZ)) { - qdma_log_error( - "%d:%s QDMA_SNPRINTF_S() failed, err:%d\n", - __LINE__, __func__, - rv); - goto INSUF_BUF_EXIT; - } - len += rv; - } - - rv = QDMA_SNPRINTF_S(buf + len, (buf_sz - len), - DEBGFS_LINE_SZ, - "%-47s %#-10x %u\n", - eqdma_fmap_ctxt_entries[i].name, - eqdma_fmap_ctxt_entries[i].value, - eqdma_fmap_ctxt_entries[i].value); - if ((rv < 0) || (rv > DEBGFS_LINE_SZ)) { - qdma_log_error( - "%d:%s QDMA_SNPRINTF_S() failed, err:%d\n", - __LINE__, __func__, - rv); - goto INSUF_BUF_EXIT; - } - len += rv; - } - - return len; - -INSUF_BUF_EXIT: - if (buf_sz > DEBGFS_LINE_SZ) { - rv = QDMA_SNPRINTF_S((buf + buf_sz - DEBGFS_LINE_SZ), - buf_sz, DEBGFS_LINE_SZ, - "\n\nInsufficient buffer size, partial context dump\n"); - if ((rv < 0) || (rv > DEBGFS_LINE_SZ)) { - qdma_log_error( - "%d:%s QDMA_SNPRINTF_S() failed, err:%d\n", - __LINE__, __func__, - rv); - } - } - - qdma_log_error("%s: Insufficient buffer size, err:%d\n", - __func__, -QDMA_ERR_NO_MEM); - - return -QDMA_ERR_NO_MEM; -} - -/* - * dump_eqdma_intr_context() - Helper function to dump interrupt context into - * string - * - * return len - length of the string copied into buffer - */ -static int dump_eqdma_intr_context(struct qdma_indirect_intr_ctxt *intr_ctx, - int ring_index, - char *buf, int buf_sz) -{ - int i = 0; - int n; - int len = 0; - int rv; - char banner[DEBGFS_LINE_SZ]; - - eqdma_fill_intr_ctxt(intr_ctx); - - for (i = 0; i < DEBGFS_LINE_SZ - 5; i++) { - rv = QDMA_SNPRINTF_S(banner + i, - (DEBGFS_LINE_SZ - i), - sizeof("-"), "-"); - if ((rv < 0) || (rv > (int)sizeof("-"))) { - qdma_log_error( - "%d:%s QDMA_SNPRINTF_S() failed, err:%d\n", - __LINE__, __func__, - rv); - goto INSUF_BUF_EXIT; - } - } - - /* Interrupt context dump */ - n = sizeof(eqdma_ind_intr_ctxt_entries) / - sizeof((eqdma_ind_intr_ctxt_entries)[0]); - for (i = 0; i < n; i++) { - if ((len >= buf_sz) || ((len + DEBGFS_LINE_SZ) >= buf_sz)) - goto INSUF_BUF_EXIT; - - if (i == 0) { - if ((len + (3 * DEBGFS_LINE_SZ)) >= buf_sz) - goto INSUF_BUF_EXIT; - - rv = QDMA_SNPRINTF_S(buf + len, (buf_sz - len), - DEBGFS_LINE_SZ, "\n%s", banner); - if ((rv < 0) || (rv > DEBGFS_LINE_SZ)) { - qdma_log_error( - "%d:%s QDMA_SNPRINTF_S() failed, err:%d\n", - __LINE__, __func__, - rv); - goto INSUF_BUF_EXIT; - } - len += rv; - - rv = QDMA_SNPRINTF_S(buf + len, (buf_sz - len), - DEBGFS_LINE_SZ, "\n%50s %d", - "Interrupt Context for ring#", ring_index); - if ((rv < 0) || (rv > DEBGFS_LINE_SZ)) { - qdma_log_error( - "%d:%s QDMA_SNPRINTF_S() failed, err:%d\n", - __LINE__, __func__, - rv); - goto INSUF_BUF_EXIT; - } - len += rv; - - rv = QDMA_SNPRINTF_S(buf + len, (buf_sz - len), - DEBGFS_LINE_SZ, "\n%s\n", banner); - if ((rv < 0) || (rv > DEBGFS_LINE_SZ)) { - qdma_log_error( - "%d:%s QDMA_SNPRINTF_S() failed, err:%d\n", - __LINE__, __func__, - rv); - goto INSUF_BUF_EXIT; - } - len += rv; - } - - rv = QDMA_SNPRINTF_S(buf + len, (buf_sz - len), DEBGFS_LINE_SZ, - "%-47s %#-10x %u\n", - eqdma_ind_intr_ctxt_entries[i].name, - eqdma_ind_intr_ctxt_entries[i].value, - eqdma_ind_intr_ctxt_entries[i].value); - if ((rv < 0) || (rv > DEBGFS_LINE_SZ)) { - qdma_log_error( - "%d:%s QDMA_SNPRINTF_S() failed, err:%d\n", - __LINE__, __func__, - rv); - goto INSUF_BUF_EXIT; - } - len += rv; - } - - return len; - -INSUF_BUF_EXIT: - if (buf_sz > DEBGFS_LINE_SZ) { - rv = QDMA_SNPRINTF_S((buf + buf_sz - DEBGFS_LINE_SZ), - buf_sz, DEBGFS_LINE_SZ, - "\n\nInsufficient buffer size, partial context dump\n"); - if ((rv < 0) || (rv > DEBGFS_LINE_SZ)) { - qdma_log_error( - "%d:%s QDMA_SNPRINTF_S() failed, err:%d\n", - __LINE__, __func__, - rv); - } - } - - qdma_log_error("%s: Insufficient buffer size, err:%d\n", - __func__, -QDMA_ERR_NO_MEM); - - return -QDMA_ERR_NO_MEM; -} - -/*****************************************************************************/ -/** - * eqdma_get_version() - Function to get the eqdma version - * - * @dev_hndl: device handle - * @is_vf: Whether PF or VF - * @version_info: pointer to hold the version info - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -int eqdma_get_version(void *dev_hndl, uint8_t is_vf, - struct qdma_hw_version_info *version_info) -{ - uint32_t reg_val = 0; - uint32_t reg_addr = (is_vf) ? EQDMA_OFFSET_VF_VERSION : - EQDMA_GLBL2_MISC_CAP_ADDR; - - if (!dev_hndl) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - reg_val = qdma_reg_read(dev_hndl, reg_addr); - - qdma_fetch_version_details(dev_hndl, is_vf, reg_val, version_info); - - return QDMA_SUCCESS; -} - -/*****************************************************************************/ -/** - * eqdma_sw_context_write() - create sw context and program it - * - * @dev_hndl: device handle - * @c2h: is c2h queue - * @hw_qid: hardware qid of the queue - * @ctxt: pointer to the SW context data strucutre - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -static int eqdma_sw_context_write(void *dev_hndl, uint8_t c2h, - uint16_t hw_qid, - const struct qdma_descq_sw_ctxt *ctxt) -{ - uint32_t sw_ctxt[EQDMA_SW_CONTEXT_NUM_WORDS] = {0}; - uint16_t num_words_count = 0; - uint32_t pasid_l, pasid_h; - uint32_t virtio_desc_base_l, virtio_desc_base_m, virtio_desc_base_h; - enum ind_ctxt_cmd_sel sel = c2h ? - QDMA_CTXT_SEL_SW_C2H : QDMA_CTXT_SEL_SW_H2C; - - /* Input args check */ - if (!dev_hndl || !ctxt) { - qdma_log_error("%s: dev_handle=%p sw_ctxt=%p NULL, err:%d\n", - __func__, dev_hndl, ctxt, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - pasid_l = - FIELD_GET(EQDMA_SW_CTXT_PASID_GET_L_MASK, ctxt->pasid); - pasid_h = - FIELD_GET(EQDMA_SW_CTXT_PASID_GET_H_MASK, ctxt->pasid); - - virtio_desc_base_l = (uint32_t)FIELD_GET( - EQDMA_SW_CTXT_VIRTIO_DSC_BASE_GET_L_MASK, - ctxt->virtio_dsc_base); - virtio_desc_base_m = (uint32_t)FIELD_GET( - EQDMA_SW_CTXT_VIRTIO_DSC_BASE_GET_M_MASK, - ctxt->virtio_dsc_base); - virtio_desc_base_h = (uint32_t)FIELD_GET( - EQDMA_SW_CTXT_VIRTIO_DSC_BASE_GET_H_MASK, - ctxt->virtio_dsc_base); - - sw_ctxt[num_words_count++] = - FIELD_SET(SW_IND_CTXT_DATA_W0_PIDX_MASK, ctxt->pidx) | - FIELD_SET(SW_IND_CTXT_DATA_W0_IRQ_ARM_MASK, ctxt->irq_arm) | - FIELD_SET(SW_IND_CTXT_DATA_W0_FNC_MASK, ctxt->fnc_id); - - qdma_log_debug("%s: pidx=%x, irq_arm=%x, fnc_id=%x\n", - __func__, ctxt->pidx, ctxt->irq_arm, ctxt->fnc_id); - - sw_ctxt[num_words_count++] = - FIELD_SET(SW_IND_CTXT_DATA_W1_QEN_MASK, ctxt->qen) | - FIELD_SET(SW_IND_CTXT_DATA_W1_FCRD_EN_MASK, ctxt->frcd_en) | - FIELD_SET(SW_IND_CTXT_DATA_W1_WBI_CHK_MASK, ctxt->wbi_chk) | - FIELD_SET(SW_IND_CTXT_DATA_W1_WBI_INTVL_EN_MASK, - ctxt->wbi_intvl_en) | - FIELD_SET(SW_IND_CTXT_DATA_W1_AT_MASK, ctxt->at) | - FIELD_SET(SW_IND_CTXT_DATA_W1_FETCH_MAX_MASK, ctxt->fetch_max) | - FIELD_SET(SW_IND_CTXT_DATA_W1_RNG_SZ_MASK, ctxt->rngsz_idx) | - FIELD_SET(SW_IND_CTXT_DATA_W1_DSC_SZ_MASK, ctxt->desc_sz) | - FIELD_SET(SW_IND_CTXT_DATA_W1_BYPASS_MASK, ctxt->bypass) | - FIELD_SET(SW_IND_CTXT_DATA_W1_MM_CHN_MASK, ctxt->mm_chn) | - FIELD_SET(SW_IND_CTXT_DATA_W1_WBK_EN_MASK, ctxt->wbk_en) | - FIELD_SET(SW_IND_CTXT_DATA_W1_IRQ_EN_MASK, ctxt->irq_en) | - FIELD_SET(SW_IND_CTXT_DATA_W1_PORT_ID_MASK, ctxt->port_id) | - FIELD_SET(SW_IND_CTXT_DATA_W1_IRQ_NO_LAST_MASK, - ctxt->irq_no_last) | - FIELD_SET(SW_IND_CTXT_DATA_W1_ERR_MASK, ctxt->err) | - FIELD_SET(SW_IND_CTXT_DATA_W1_ERR_WB_SENT_MASK, - ctxt->err_wb_sent) | - FIELD_SET(SW_IND_CTXT_DATA_W1_IRQ_REQ_MASK, ctxt->irq_req) | - FIELD_SET(SW_IND_CTXT_DATA_W1_MRKR_DIS_MASK, ctxt->mrkr_dis) | - FIELD_SET(SW_IND_CTXT_DATA_W1_IS_MM_MASK, ctxt->is_mm); - - qdma_log_debug("%s: qen=%x, frcd_en=%x, wbi_chk=%x, wbi_intvl_en=%x\n", - __func__, ctxt->qen, ctxt->frcd_en, ctxt->wbi_chk, - ctxt->wbi_intvl_en); - - qdma_log_debug("%s: at=%x, fetch_max=%x, rngsz_idx=%x, desc_sz=%x\n", - __func__, ctxt->at, ctxt->fetch_max, ctxt->rngsz_idx, - ctxt->desc_sz); - - qdma_log_debug("%s: bypass=%x, mm_chn=%x, wbk_en=%x, irq_en=%x\n", - __func__, ctxt->bypass, ctxt->mm_chn, ctxt->wbk_en, - ctxt->irq_en); - - qdma_log_debug("%s: port_id=%x, irq_no_last=%x,err=%x", - __func__, ctxt->port_id, ctxt->irq_no_last, ctxt->err); - qdma_log_debug(", err_wb_sent=%x\n", ctxt->err_wb_sent); - - qdma_log_debug("%s: irq_req=%x, mrkr_dis=%x, is_mm=%x\n", - __func__, ctxt->irq_req, ctxt->mrkr_dis, ctxt->is_mm); - - sw_ctxt[num_words_count++] = ctxt->ring_bs_addr & 0xffffffff; - sw_ctxt[num_words_count++] = (ctxt->ring_bs_addr >> 32) & 0xffffffff; - - sw_ctxt[num_words_count++] = - FIELD_SET(SW_IND_CTXT_DATA_W4_VEC_MASK, ctxt->vec) | - FIELD_SET(SW_IND_CTXT_DATA_W4_INT_AGGR_MASK, ctxt->intr_aggr) | - FIELD_SET(SW_IND_CTXT_DATA_W4_DIS_INTR_ON_VF_MASK, - ctxt->dis_intr_on_vf) | - FIELD_SET(SW_IND_CTXT_DATA_W4_VIRTIO_EN_MASK, - ctxt->virtio_en) | - FIELD_SET(SW_IND_CTXT_DATA_W4_PACK_BYP_OUT_MASK, - ctxt->pack_byp_out) | - FIELD_SET(SW_IND_CTXT_DATA_W4_IRQ_BYP_MASK, ctxt->irq_byp) | - FIELD_SET(SW_IND_CTXT_DATA_W4_HOST_ID_MASK, ctxt->host_id) | - FIELD_SET(SW_IND_CTXT_DATA_W4_PASID_L_MASK, pasid_l); - - sw_ctxt[num_words_count++] = - FIELD_SET(SW_IND_CTXT_DATA_W5_PASID_H_MASK, pasid_h) | - FIELD_SET(SW_IND_CTXT_DATA_W5_PASID_EN_MASK, ctxt->pasid_en) | - FIELD_SET(SW_IND_CTXT_DATA_W5_VIRTIO_DSC_BASE_L_MASK, - virtio_desc_base_l); - - sw_ctxt[num_words_count++] = - FIELD_SET(SW_IND_CTXT_DATA_W6_VIRTIO_DSC_BASE_M_MASK, - virtio_desc_base_m); - - sw_ctxt[num_words_count++] = - FIELD_SET(SW_IND_CTXT_DATA_W7_VIRTIO_DSC_BASE_H_MASK, - virtio_desc_base_h); - - - qdma_log_debug("%s: vec=%x, intr_aggr=%x\n", - __func__, ctxt->vec, ctxt->intr_aggr); - - return eqdma_indirect_reg_write(dev_hndl, sel, hw_qid, - sw_ctxt, num_words_count); -} - -/*****************************************************************************/ -/** - * eqdma_sw_context_read() - read sw context - * - * @dev_hndl: device handle - * @c2h: is c2h queue - * @hw_qid: hardware qid of the queue - * @ctxt: pointer to the output context data - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -static int eqdma_sw_context_read(void *dev_hndl, uint8_t c2h, - uint16_t hw_qid, - struct qdma_descq_sw_ctxt *ctxt) -{ - int rv = QDMA_SUCCESS; - uint32_t sw_ctxt[EQDMA_SW_CONTEXT_NUM_WORDS] = {0}; - uint32_t pasid_l, pasid_h; - uint32_t virtio_desc_base_l, virtio_desc_base_m, virtio_desc_base_h; - enum ind_ctxt_cmd_sel sel = c2h ? - QDMA_CTXT_SEL_SW_C2H : QDMA_CTXT_SEL_SW_H2C; - - if (!dev_hndl || !ctxt) { - qdma_log_error("%s: dev_handle=%p sw_ctxt=%p NULL, err:%d\n", - __func__, dev_hndl, ctxt, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - rv = eqdma_indirect_reg_read(dev_hndl, sel, hw_qid, - EQDMA_SW_CONTEXT_NUM_WORDS, sw_ctxt); - if (rv < 0) - return rv; - - ctxt->pidx = FIELD_GET(SW_IND_CTXT_DATA_W0_PIDX_MASK, sw_ctxt[0]); - ctxt->irq_arm = - (uint8_t)(FIELD_GET(SW_IND_CTXT_DATA_W0_IRQ_ARM_MASK, - sw_ctxt[0])); - ctxt->fnc_id = - (uint8_t)(FIELD_GET(SW_IND_CTXT_DATA_W0_FNC_MASK, - sw_ctxt[0])); - - qdma_log_debug("%s: pidx=%x, irq_arm=%x, fnc_id=%x", - __func__, ctxt->pidx, ctxt->irq_arm, ctxt->fnc_id); - - ctxt->qen = FIELD_GET(SW_IND_CTXT_DATA_W1_QEN_MASK, sw_ctxt[1]); - ctxt->frcd_en = FIELD_GET(SW_IND_CTXT_DATA_W1_FCRD_EN_MASK, sw_ctxt[1]); - ctxt->wbi_chk = FIELD_GET(SW_IND_CTXT_DATA_W1_WBI_CHK_MASK, sw_ctxt[1]); - ctxt->wbi_intvl_en = - FIELD_GET(SW_IND_CTXT_DATA_W1_WBI_INTVL_EN_MASK, sw_ctxt[1]); - ctxt->at = FIELD_GET(SW_IND_CTXT_DATA_W1_AT_MASK, sw_ctxt[1]); - ctxt->fetch_max = - (uint8_t)FIELD_GET(SW_IND_CTXT_DATA_W1_FETCH_MAX_MASK, - sw_ctxt[1]); - ctxt->rngsz_idx = - (uint8_t)(FIELD_GET(SW_IND_CTXT_DATA_W1_RNG_SZ_MASK, - sw_ctxt[1])); - ctxt->desc_sz = - (uint8_t)(FIELD_GET(SW_IND_CTXT_DATA_W1_DSC_SZ_MASK, - sw_ctxt[1])); - ctxt->bypass = - (uint8_t)(FIELD_GET(SW_IND_CTXT_DATA_W1_BYPASS_MASK, - sw_ctxt[1])); - ctxt->mm_chn = - (uint8_t)(FIELD_GET(SW_IND_CTXT_DATA_W1_MM_CHN_MASK, - sw_ctxt[1])); - ctxt->wbk_en = - (uint8_t)(FIELD_GET(SW_IND_CTXT_DATA_W1_WBK_EN_MASK, - sw_ctxt[1])); - ctxt->irq_en = - (uint8_t)(FIELD_GET(SW_IND_CTXT_DATA_W1_IRQ_EN_MASK, - sw_ctxt[1])); - ctxt->port_id = - (uint8_t)(FIELD_GET(SW_IND_CTXT_DATA_W1_PORT_ID_MASK, - sw_ctxt[1])); - ctxt->irq_no_last = - (uint8_t)(FIELD_GET(SW_IND_CTXT_DATA_W1_IRQ_NO_LAST_MASK, - sw_ctxt[1])); - ctxt->err = - (uint8_t)(FIELD_GET(SW_IND_CTXT_DATA_W1_ERR_MASK, sw_ctxt[1])); - ctxt->err_wb_sent = - (uint8_t)(FIELD_GET(SW_IND_CTXT_DATA_W1_ERR_WB_SENT_MASK, - sw_ctxt[1])); - ctxt->irq_req = - (uint8_t)(FIELD_GET(SW_IND_CTXT_DATA_W1_IRQ_REQ_MASK, - sw_ctxt[1])); - ctxt->mrkr_dis = - (uint8_t)(FIELD_GET(SW_IND_CTXT_DATA_W1_MRKR_DIS_MASK, - sw_ctxt[1])); - ctxt->is_mm = - (uint8_t)(FIELD_GET(SW_IND_CTXT_DATA_W1_IS_MM_MASK, - sw_ctxt[1])); - - qdma_log_debug("%s: qen=%x, frcd_en=%x, wbi_chk=%x, wbi_intvl_en=%x\n", - __func__, ctxt->qen, ctxt->frcd_en, ctxt->wbi_chk, - ctxt->wbi_intvl_en); - qdma_log_debug("%s: at=%x, fetch_max=%x, rngsz_idx=%x, desc_sz=%x\n", - __func__, ctxt->at, ctxt->fetch_max, ctxt->rngsz_idx, - ctxt->desc_sz); - qdma_log_debug("%s: bypass=%x, mm_chn=%x, wbk_en=%x, irq_en=%x\n", - __func__, ctxt->bypass, ctxt->mm_chn, ctxt->wbk_en, - ctxt->irq_en); - qdma_log_debug("%s: port_id=%x, irq_no_last=%x,", - __func__, ctxt->port_id, ctxt->irq_no_last); - qdma_log_debug(" err=%x, err_wb_sent=%x\n", - ctxt->err, ctxt->err_wb_sent); - qdma_log_debug("%s: irq_req=%x, mrkr_dis=%x, is_mm=%x\n", - __func__, ctxt->irq_req, ctxt->mrkr_dis, ctxt->is_mm); - - ctxt->ring_bs_addr = ((uint64_t)sw_ctxt[3] << 32) | (sw_ctxt[2]); - - ctxt->vec = FIELD_GET(SW_IND_CTXT_DATA_W4_VEC_MASK, sw_ctxt[4]); - ctxt->intr_aggr = (uint8_t)(FIELD_GET(SW_IND_CTXT_DATA_W4_INT_AGGR_MASK, - sw_ctxt[4])); - ctxt->dis_intr_on_vf = - (uint8_t)(FIELD_GET(SW_IND_CTXT_DATA_W4_DIS_INTR_ON_VF_MASK, - sw_ctxt[4])); - ctxt->virtio_en = - (uint8_t)(FIELD_GET(SW_IND_CTXT_DATA_W4_VIRTIO_EN_MASK, - sw_ctxt[4])); - ctxt->pack_byp_out = - (uint8_t)(FIELD_GET(SW_IND_CTXT_DATA_W4_PACK_BYP_OUT_MASK, - sw_ctxt[4])); - ctxt->irq_byp = - (uint8_t)(FIELD_GET(SW_IND_CTXT_DATA_W4_IRQ_BYP_MASK, - sw_ctxt[4])); - ctxt->host_id = - (uint8_t)(FIELD_GET(SW_IND_CTXT_DATA_W4_HOST_ID_MASK, - sw_ctxt[4])); - pasid_l = FIELD_GET(SW_IND_CTXT_DATA_W4_PASID_L_MASK, sw_ctxt[4]); - - pasid_h = FIELD_GET(SW_IND_CTXT_DATA_W5_PASID_H_MASK, sw_ctxt[5]); - ctxt->pasid_en = (uint8_t)FIELD_GET(SW_IND_CTXT_DATA_W5_PASID_EN_MASK, - sw_ctxt[5]); - virtio_desc_base_l = - FIELD_GET(SW_IND_CTXT_DATA_W5_VIRTIO_DSC_BASE_L_MASK, - sw_ctxt[5]); - virtio_desc_base_m = - FIELD_GET(SW_IND_CTXT_DATA_W6_VIRTIO_DSC_BASE_M_MASK, - sw_ctxt[6]); - - virtio_desc_base_h = - FIELD_GET(SW_IND_CTXT_DATA_W7_VIRTIO_DSC_BASE_H_MASK, - sw_ctxt[6]); - - ctxt->pasid = - FIELD_SET(EQDMA_SW_CTXT_PASID_GET_L_MASK, pasid_l) | - FIELD_SET(EQDMA_SW_CTXT_PASID_GET_H_MASK, pasid_h); - - ctxt->virtio_dsc_base = - FIELD_SET(EQDMA_SW_CTXT_VIRTIO_DSC_BASE_GET_L_MASK, - (uint64_t)virtio_desc_base_l) | - FIELD_SET(EQDMA_SW_CTXT_VIRTIO_DSC_BASE_GET_M_MASK, - (uint64_t)virtio_desc_base_m) | - FIELD_SET(EQDMA_SW_CTXT_VIRTIO_DSC_BASE_GET_H_MASK, - (uint64_t)virtio_desc_base_h); - - qdma_log_debug("%s: vec=%x, intr_aggr=%x\n", - __func__, ctxt->vec, ctxt->intr_aggr); - - return QDMA_SUCCESS; -} - -/*****************************************************************************/ -/** - * eqdma_sw_context_clear() - clear sw context - * - * @dev_hndl: device handle - * @c2h: is c2h queue - * @hw_qid: hardware qid of the queue - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -static int eqdma_sw_context_clear(void *dev_hndl, uint8_t c2h, - uint16_t hw_qid) -{ - enum ind_ctxt_cmd_sel sel = c2h ? - QDMA_CTXT_SEL_SW_C2H : QDMA_CTXT_SEL_SW_H2C; - - if (!dev_hndl) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", __func__, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - return eqdma_indirect_reg_clear(dev_hndl, sel, hw_qid); -} - -/*****************************************************************************/ -/** - * eqdma_sw_context_invalidate() - invalidate sw context - * - * @dev_hndl: device handle - * @c2h: is c2h queue - * @hw_qid: hardware qid of the queue - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -static int eqdma_sw_context_invalidate(void *dev_hndl, uint8_t c2h, - uint16_t hw_qid) -{ - enum ind_ctxt_cmd_sel sel = c2h ? - QDMA_CTXT_SEL_SW_C2H : QDMA_CTXT_SEL_SW_H2C; - - if (!dev_hndl) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", __func__, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - return eqdma_indirect_reg_invalidate(dev_hndl, sel, hw_qid); -} - -/*****************************************************************************/ -/** - * eqdma_sw_ctx_conf() - configure SW context - * - * @dev_hndl: device handle - * @c2h: is c2h queue - * @hw_qid: hardware qid of the queue - * @ctxt: pointer to the context data - * @access_type HW access type (qdma_hw_access_type enum) value - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -int eqdma_sw_ctx_conf(void *dev_hndl, uint8_t c2h, uint16_t hw_qid, - struct qdma_descq_sw_ctxt *ctxt, - enum qdma_hw_access_type access_type) -{ - int rv = QDMA_SUCCESS; - - switch (access_type) { - case QDMA_HW_ACCESS_READ: - rv = eqdma_sw_context_read(dev_hndl, c2h, hw_qid, ctxt); - break; - case QDMA_HW_ACCESS_WRITE: - rv = eqdma_sw_context_write(dev_hndl, c2h, hw_qid, ctxt); - break; - case QDMA_HW_ACCESS_CLEAR: - rv = eqdma_sw_context_clear(dev_hndl, c2h, hw_qid); - break; - case QDMA_HW_ACCESS_INVALIDATE: - rv = eqdma_sw_context_invalidate(dev_hndl, c2h, hw_qid); - break; - default: - qdma_log_error("%s: access_type(%d) invalid, err:%d\n", - __func__, - access_type, - -QDMA_ERR_INV_PARAM); - rv = -QDMA_ERR_INV_PARAM; - break; - } - - return rv; -} - -/*****************************************************************************/ -/** - * eqdma_pfetch_context_write() - create prefetch context and program it - * - * @dev_hndl: device handle - * @hw_qid: hardware qid of the queue - * @ctxt: pointer to the prefetch context data strucutre - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -static int eqdma_pfetch_context_write(void *dev_hndl, uint16_t hw_qid, - const struct qdma_descq_prefetch_ctxt *ctxt) -{ - uint32_t pfetch_ctxt[EQDMA_PFETCH_CONTEXT_NUM_WORDS] = {0}; - enum ind_ctxt_cmd_sel sel = QDMA_CTXT_SEL_PFTCH; - uint32_t sw_crdt_l, sw_crdt_h; - uint16_t num_words_count = 0; - - if (!dev_hndl || !ctxt) { - qdma_log_error("%s: dev_handle or pfetch ctxt NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - sw_crdt_l = - FIELD_GET(QDMA_PFTCH_CTXT_SW_CRDT_GET_L_MASK, ctxt->sw_crdt); - sw_crdt_h = - FIELD_GET(QDMA_PFTCH_CTXT_SW_CRDT_GET_H_MASK, ctxt->sw_crdt); - - qdma_log_debug("%s: sw_crdt_l=%u, sw_crdt_h=%u, hw_qid=%hu\n", - __func__, sw_crdt_l, sw_crdt_h, hw_qid); - - pfetch_ctxt[num_words_count++] = - FIELD_SET(PREFETCH_CTXT_DATA_W0_BYPASS_MASK, ctxt->bypass) | - FIELD_SET(PREFETCH_CTXT_DATA_W0_BUF_SZ_IDX_MASK, - ctxt->bufsz_idx) | - FIELD_SET(PREFETCH_CTXT_DATA_W0_PORT_ID_MASK, ctxt->port_id) | - FIELD_SET(PREFETCH_CTXT_DATA_W0_NUM_PFCH_MASK, - ctxt->num_pftch) | - FIELD_SET(PREFETCH_CTXT_DATA_W0_VAR_DESC_MASK, - ctxt->var_desc) | - FIELD_SET(PREFETCH_CTXT_DATA_W0_ERR_MASK, ctxt->err) | - FIELD_SET(PREFETCH_CTXT_DATA_W0_PFCH_EN_MASK, ctxt->pfch_en) | - FIELD_SET(PREFETCH_CTXT_DATA_W0_PFCH_MASK, ctxt->pfch) | - FIELD_SET(PREFETCH_CTXT_DATA_W0_SW_CRDT_L_MASK, sw_crdt_l); - - qdma_log_debug("%s: bypass=%x, bufsz_idx=%x, port_id=%x\n", - __func__, ctxt->bypass, ctxt->bufsz_idx, ctxt->port_id); - qdma_log_debug("%s: err=%x, pfch_en=%x, pfch=%x, ctxt->valid=%x\n", - __func__, ctxt->err, ctxt->pfch_en, ctxt->pfch, - ctxt->valid); - - pfetch_ctxt[num_words_count++] = - FIELD_SET(PREFETCH_CTXT_DATA_W1_SW_CRDT_H_MASK, sw_crdt_h) | - FIELD_SET(PREFETCH_CTXT_DATA_W1_VALID_MASK, ctxt->valid); - - return eqdma_indirect_reg_write(dev_hndl, sel, hw_qid, - pfetch_ctxt, num_words_count); -} - -/*****************************************************************************/ -/** - * eqdma_pfetch_context_read() - read prefetch context - * - * @dev_hndl: device handle - * @hw_qid: hardware qid of the queue - * @ctxt: pointer to the output context data - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -static int eqdma_pfetch_context_read(void *dev_hndl, uint16_t hw_qid, - struct qdma_descq_prefetch_ctxt *ctxt) -{ - int rv = QDMA_SUCCESS; - uint32_t pfetch_ctxt[EQDMA_PFETCH_CONTEXT_NUM_WORDS] = {0}; - enum ind_ctxt_cmd_sel sel = QDMA_CTXT_SEL_PFTCH; - uint32_t sw_crdt_l, sw_crdt_h; - - if (!dev_hndl || !ctxt) { - qdma_log_error("%s: dev_handle or pfetch ctxt NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - rv = eqdma_indirect_reg_read(dev_hndl, sel, hw_qid, - EQDMA_PFETCH_CONTEXT_NUM_WORDS, pfetch_ctxt); - if (rv < 0) - return rv; - - ctxt->bypass = - FIELD_GET(PREFETCH_CTXT_DATA_W0_BYPASS_MASK, pfetch_ctxt[0]); - ctxt->bufsz_idx = - FIELD_GET(PREFETCH_CTXT_DATA_W0_BUF_SZ_IDX_MASK, - pfetch_ctxt[0]); - ctxt->num_pftch = (uint16_t) FIELD_GET( - PREFETCH_CTXT_DATA_W0_NUM_PFCH_MASK, pfetch_ctxt[0]); - ctxt->port_id = - FIELD_GET(PREFETCH_CTXT_DATA_W0_PORT_ID_MASK, pfetch_ctxt[0]); - ctxt->var_desc = (uint8_t) - FIELD_GET(PREFETCH_CTXT_DATA_W0_VAR_DESC_MASK, - pfetch_ctxt[0]); - ctxt->err = - (uint8_t)(FIELD_GET(PREFETCH_CTXT_DATA_W0_ERR_MASK, - pfetch_ctxt[0])); - ctxt->pfch_en = - (uint8_t)(FIELD_GET(PREFETCH_CTXT_DATA_W0_PFCH_EN_MASK, - pfetch_ctxt[0])); - ctxt->pfch = - (uint8_t)(FIELD_GET(PREFETCH_CTXT_DATA_W0_PFCH_MASK, - pfetch_ctxt[0])); - sw_crdt_l = - FIELD_GET(PREFETCH_CTXT_DATA_W0_SW_CRDT_L_MASK, pfetch_ctxt[0]); - - sw_crdt_h = - FIELD_GET(PREFETCH_CTXT_DATA_W1_SW_CRDT_H_MASK, pfetch_ctxt[1]); - ctxt->valid = - (uint8_t)(FIELD_GET(PREFETCH_CTXT_DATA_W1_VALID_MASK, - pfetch_ctxt[1])); - - ctxt->sw_crdt = - FIELD_SET(QDMA_PFTCH_CTXT_SW_CRDT_GET_L_MASK, sw_crdt_l) | - FIELD_SET(QDMA_PFTCH_CTXT_SW_CRDT_GET_H_MASK, sw_crdt_h); - - qdma_log_debug("%s: sw_crdt_l=%u, sw_crdt_h=%u, hw_qid=%hu\n", - __func__, sw_crdt_l, sw_crdt_h, hw_qid); - qdma_log_debug("%s: bypass=%x, bufsz_idx=%x, port_id=%x\n", - __func__, ctxt->bypass, ctxt->bufsz_idx, ctxt->port_id); - qdma_log_debug("%s: err=%x, pfch_en=%x, pfch=%x, ctxt->valid=%x\n", - __func__, ctxt->err, ctxt->pfch_en, ctxt->pfch, - ctxt->valid); - - return QDMA_SUCCESS; -} - -/*****************************************************************************/ -/** - * eqdma_pfetch_context_clear() - clear prefetch context - * - * @dev_hndl: device handle - * @hw_qid: hardware qid of the queue - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -static int eqdma_pfetch_context_clear(void *dev_hndl, uint16_t hw_qid) -{ - enum ind_ctxt_cmd_sel sel = QDMA_CTXT_SEL_PFTCH; - - if (!dev_hndl) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", __func__, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - return eqdma_indirect_reg_clear(dev_hndl, sel, hw_qid); -} - -/*****************************************************************************/ -/** - * eqdma_pfetch_context_invalidate() - invalidate prefetch context - * - * @dev_hndl: device handle - * @hw_qid: hardware qid of the queue - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -static int eqdma_pfetch_context_invalidate(void *dev_hndl, uint16_t hw_qid) -{ - enum ind_ctxt_cmd_sel sel = QDMA_CTXT_SEL_PFTCH; - - if (!dev_hndl) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", __func__, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - return eqdma_indirect_reg_invalidate(dev_hndl, sel, hw_qid); -} - -/*****************************************************************************/ -/** - * eqdma_pfetch_ctx_conf() - configure prefetch context - * - * @dev_hndl: device handle - * @hw_qid: hardware qid of the queue - * @ctxt: pointer to context data - * @access_type HW access type (qdma_hw_access_type enum) value - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -int eqdma_pfetch_ctx_conf(void *dev_hndl, uint16_t hw_qid, - struct qdma_descq_prefetch_ctxt *ctxt, - enum qdma_hw_access_type access_type) -{ - int rv = QDMA_SUCCESS; - - switch (access_type) { - case QDMA_HW_ACCESS_READ: - rv = eqdma_pfetch_context_read(dev_hndl, hw_qid, ctxt); - break; - case QDMA_HW_ACCESS_WRITE: - rv = eqdma_pfetch_context_write(dev_hndl, hw_qid, ctxt); - break; - case QDMA_HW_ACCESS_CLEAR: - rv = eqdma_pfetch_context_clear(dev_hndl, hw_qid); - break; - case QDMA_HW_ACCESS_INVALIDATE: - rv = eqdma_pfetch_context_invalidate(dev_hndl, hw_qid); - break; - default: - qdma_log_error("%s: access_type(%d) invalid, err:%d\n", - __func__, - access_type, - -QDMA_ERR_INV_PARAM); - rv = -QDMA_ERR_INV_PARAM; - break; - } - - return rv; -} - -/*****************************************************************************/ -/** - * eqdma_cmpt_context_write() - create completion context and program it - * - * @dev_hndl: device handle - * @hw_qid: hardware qid of the queue - * @ctxt: pointer to the cmpt context data strucutre - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -static int eqdma_cmpt_context_write(void *dev_hndl, uint16_t hw_qid, - const struct qdma_descq_cmpt_ctxt *ctxt) -{ - uint32_t cmpt_ctxt[EQDMA_CMPT_CONTEXT_NUM_WORDS] = {0}; - uint16_t num_words_count = 0; - uint32_t baddr4_high_l, baddr4_high_h, - baddr4_low, pidx_l, pidx_h, pasid_l, pasid_h; - enum ind_ctxt_cmd_sel sel = QDMA_CTXT_SEL_CMPT; - - /* Input args check */ - if (!dev_hndl || !ctxt) { - qdma_log_error("%s: dev_handle or cmpt ctxt NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - if (ctxt->trig_mode > QDMA_CMPT_UPDATE_TRIG_MODE_TMR_CNTR) { - qdma_log_error("%s: trig_mode(%d) > (%d) is invalid, err:%d\n", - __func__, - ctxt->trig_mode, - QDMA_CMPT_UPDATE_TRIG_MODE_TMR_CNTR, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - baddr4_high_l = (uint32_t)FIELD_GET(EQDMA_COMPL_CTXT_BADDR_HIGH_L_MASK, - ctxt->bs_addr); - baddr4_high_h = (uint32_t)FIELD_GET(EQDMA_COMPL_CTXT_BADDR_HIGH_H_MASK, - ctxt->bs_addr); - baddr4_low = (uint32_t)FIELD_GET(EQDMA_COMPL_CTXT_BADDR_LOW_MASK, - ctxt->bs_addr); - - pidx_l = FIELD_GET(QDMA_COMPL_CTXT_PIDX_GET_L_MASK, ctxt->pidx); - pidx_h = FIELD_GET(QDMA_COMPL_CTXT_PIDX_GET_H_MASK, ctxt->pidx); - - pasid_l = - FIELD_GET(EQDMA_CMPL_CTXT_PASID_GET_L_MASK, ctxt->pasid); - pasid_h = - FIELD_GET(EQDMA_CMPL_CTXT_PASID_GET_H_MASK, ctxt->pasid); - - cmpt_ctxt[num_words_count++] = - FIELD_SET(CMPL_CTXT_DATA_W0_EN_STAT_DESC_MASK, - ctxt->en_stat_desc) | - FIELD_SET(CMPL_CTXT_DATA_W0_EN_INT_MASK, ctxt->en_int) | - FIELD_SET(CMPL_CTXT_DATA_W0_TRIG_MODE_MASK, ctxt->trig_mode) | - FIELD_SET(CMPL_CTXT_DATA_W0_FNC_ID_MASK, ctxt->fnc_id) | - FIELD_SET(CMPL_CTXT_DATA_W0_CNTER_IX_MASK, - ctxt->counter_idx) | - FIELD_SET(CMPL_CTXT_DATA_W0_TIMER_IX_MASK, ctxt->timer_idx) | - FIELD_SET(CMPL_CTXT_DATA_W0_INT_ST_MASK, ctxt->in_st) | - FIELD_SET(CMPL_CTXT_DATA_W0_COLOR_MASK, ctxt->color) | - FIELD_SET(CMPL_CTXT_DATA_W0_QSIZE_IX_MASK, ctxt->ringsz_idx); - - cmpt_ctxt[num_words_count++] = - FIELD_SET(CMPL_CTXT_DATA_W1_BADDR4_HIGH_L_MASK, baddr4_high_l); - - cmpt_ctxt[num_words_count++] = - FIELD_SET(CMPL_CTXT_DATA_W2_BADDR4_HIGH_H_MASK, baddr4_high_h) | - FIELD_SET(CMPL_CTXT_DATA_W2_DESC_SIZE_MASK, ctxt->desc_sz) | - FIELD_SET(CMPL_CTXT_DATA_W2_PIDX_L_MASK, pidx_l); - - cmpt_ctxt[num_words_count++] = - FIELD_SET(CMPL_CTXT_DATA_W3_PIDX_H_MASK, pidx_h) | - FIELD_SET(CMPL_CTXT_DATA_W3_CIDX_MASK, ctxt->cidx) | - FIELD_SET(CMPL_CTXT_DATA_W3_VALID_MASK, ctxt->valid) | - FIELD_SET(CMPL_CTXT_DATA_W3_ERR_MASK, ctxt->err) | - FIELD_SET(CMPL_CTXT_DATA_W3_USER_TRIG_PEND_MASK, - ctxt->user_trig_pend); - - cmpt_ctxt[num_words_count++] = - FIELD_SET(CMPL_CTXT_DATA_W4_TIMER_RUNNING_MASK, - ctxt->timer_running) | - FIELD_SET(CMPL_CTXT_DATA_W4_FULL_UPD_MASK, ctxt->full_upd) | - FIELD_SET(CMPL_CTXT_DATA_W4_OVF_CHK_DIS_MASK, - ctxt->ovf_chk_dis) | - FIELD_SET(CMPL_CTXT_DATA_W4_AT_MASK, ctxt->at) | - FIELD_SET(CMPL_CTXT_DATA_W4_VEC_MASK, ctxt->vec) | - FIELD_SET(CMPL_CTXT_DATA_W4_INT_AGGR_MASK, ctxt->int_aggr) | - FIELD_SET(CMPL_CTXT_DATA_W4_DIS_INTR_ON_VF_MASK, - ctxt->dis_intr_on_vf) | - FIELD_SET(CMPL_CTXT_DATA_W4_VIO_MASK, ctxt->vio) | - FIELD_SET(CMPL_CTXT_DATA_W4_DIR_C2H_MASK, ctxt->dir_c2h) | - FIELD_SET(CMPL_CTXT_DATA_W4_HOST_ID_MASK, ctxt->host_id) | - FIELD_SET(CMPL_CTXT_DATA_W4_PASID_L_MASK, pasid_l); - - cmpt_ctxt[num_words_count++] = - FIELD_SET(CMPL_CTXT_DATA_W5_PASID_H_MASK, pasid_h) | - FIELD_SET(CMPL_CTXT_DATA_W5_PASID_EN_MASK, - ctxt->pasid_en) | - FIELD_SET(CMPL_CTXT_DATA_W5_BADDR4_LOW_MASK, - baddr4_low) | - FIELD_SET(CMPL_CTXT_DATA_W5_VIO_EOP_MASK, ctxt->vio_eop) | - FIELD_SET(CMPL_CTXT_DATA_W5_SH_CMPT_MASK, ctxt->sh_cmpt); - - return eqdma_indirect_reg_write(dev_hndl, sel, hw_qid, - cmpt_ctxt, num_words_count); -} - -/*****************************************************************************/ -/** - * eqdma_cmpt_context_read() - read completion context - * - * @dev_hndl: device handle - * @hw_qid: hardware qid of the queue - * @ctxt: pointer to the context data - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -static int eqdma_cmpt_context_read(void *dev_hndl, uint16_t hw_qid, - struct qdma_descq_cmpt_ctxt *ctxt) -{ - int rv = QDMA_SUCCESS; - uint32_t cmpt_ctxt[EQDMA_CMPT_CONTEXT_NUM_WORDS] = {0}; - enum ind_ctxt_cmd_sel sel = QDMA_CTXT_SEL_CMPT; - uint32_t baddr4_high_l, baddr4_high_h, baddr4_low, - pidx_l, pidx_h, pasid_l, pasid_h; - - if (!dev_hndl || !ctxt) { - qdma_log_error("%s: dev_handle or cmpt ctxt NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - rv = eqdma_indirect_reg_read(dev_hndl, sel, hw_qid, - EQDMA_CMPT_CONTEXT_NUM_WORDS, cmpt_ctxt); - if (rv < 0) - return rv; - - ctxt->en_stat_desc = - FIELD_GET(CMPL_CTXT_DATA_W0_EN_STAT_DESC_MASK, cmpt_ctxt[0]); - ctxt->en_int = FIELD_GET(CMPL_CTXT_DATA_W0_EN_INT_MASK, cmpt_ctxt[0]); - ctxt->trig_mode = - FIELD_GET(CMPL_CTXT_DATA_W0_TRIG_MODE_MASK, cmpt_ctxt[0]); - ctxt->fnc_id = - (uint8_t)(FIELD_GET(CMPL_CTXT_DATA_W0_FNC_ID_MASK, - cmpt_ctxt[0])); - ctxt->counter_idx = - (uint8_t)(FIELD_GET(CMPL_CTXT_DATA_W0_CNTER_IX_MASK, - cmpt_ctxt[0])); - ctxt->timer_idx = - (uint8_t)(FIELD_GET(CMPL_CTXT_DATA_W0_TIMER_IX_MASK, - cmpt_ctxt[0])); - ctxt->in_st = - (uint8_t)(FIELD_GET(CMPL_CTXT_DATA_W0_INT_ST_MASK, - cmpt_ctxt[0])); - ctxt->color = - (uint8_t)(FIELD_GET(CMPL_CTXT_DATA_W0_COLOR_MASK, - cmpt_ctxt[0])); - ctxt->ringsz_idx = - (uint8_t)(FIELD_GET(CMPL_CTXT_DATA_W0_QSIZE_IX_MASK, - cmpt_ctxt[0])); - - baddr4_high_l = FIELD_GET(CMPL_CTXT_DATA_W1_BADDR4_HIGH_L_MASK, - cmpt_ctxt[1]); - - baddr4_high_h = FIELD_GET(CMPL_CTXT_DATA_W2_BADDR4_HIGH_H_MASK, - cmpt_ctxt[2]); - ctxt->desc_sz = - (uint8_t)(FIELD_GET(CMPL_CTXT_DATA_W2_DESC_SIZE_MASK, - cmpt_ctxt[2])); - pidx_l = FIELD_GET(CMPL_CTXT_DATA_W2_PIDX_L_MASK, cmpt_ctxt[2]); - - pidx_h = FIELD_GET(CMPL_CTXT_DATA_W3_PIDX_H_MASK, cmpt_ctxt[3]); - ctxt->cidx = - (uint16_t)(FIELD_GET(CMPL_CTXT_DATA_W3_CIDX_MASK, - cmpt_ctxt[3])); - ctxt->valid = - (uint8_t)(FIELD_GET(CMPL_CTXT_DATA_W3_VALID_MASK, - cmpt_ctxt[3])); - ctxt->err = - (uint8_t)(FIELD_GET(CMPL_CTXT_DATA_W3_ERR_MASK, - cmpt_ctxt[3])); - ctxt->user_trig_pend = (uint8_t) - (FIELD_GET(CMPL_CTXT_DATA_W3_USER_TRIG_PEND_MASK, - cmpt_ctxt[3])); - - ctxt->timer_running = - FIELD_GET(CMPL_CTXT_DATA_W4_TIMER_RUNNING_MASK, cmpt_ctxt[4]); - ctxt->full_upd = - FIELD_GET(CMPL_CTXT_DATA_W4_FULL_UPD_MASK, cmpt_ctxt[4]); - ctxt->ovf_chk_dis = - FIELD_GET(CMPL_CTXT_DATA_W4_OVF_CHK_DIS_MASK, cmpt_ctxt[4]); - ctxt->at = FIELD_GET(CMPL_CTXT_DATA_W4_AT_MASK, cmpt_ctxt[4]); - ctxt->vec = FIELD_GET(CMPL_CTXT_DATA_W4_VEC_MASK, cmpt_ctxt[4]); - ctxt->int_aggr = (uint8_t) - (FIELD_GET(CMPL_CTXT_DATA_W4_INT_AGGR_MASK, cmpt_ctxt[4])); - ctxt->dis_intr_on_vf = (uint8_t) - FIELD_GET(CMPL_CTXT_DATA_W4_DIS_INTR_ON_VF_MASK, - cmpt_ctxt[4]); - ctxt->vio = (uint8_t)FIELD_GET(CMPL_CTXT_DATA_W4_VIO_MASK, - cmpt_ctxt[4]); - ctxt->dir_c2h = (uint8_t)FIELD_GET(CMPL_CTXT_DATA_W4_DIR_C2H_MASK, - cmpt_ctxt[4]); - ctxt->host_id = (uint8_t)FIELD_GET(CMPL_CTXT_DATA_W4_HOST_ID_MASK, - cmpt_ctxt[4]); - pasid_l = FIELD_GET(CMPL_CTXT_DATA_W4_PASID_L_MASK, cmpt_ctxt[4]); - - pasid_h = (uint32_t)FIELD_GET(CMPL_CTXT_DATA_W5_PASID_H_MASK, - cmpt_ctxt[5]); - ctxt->pasid_en = (uint8_t)FIELD_GET(CMPL_CTXT_DATA_W5_PASID_EN_MASK, - cmpt_ctxt[5]); - baddr4_low = (uint8_t)FIELD_GET( - CMPL_CTXT_DATA_W5_BADDR4_LOW_MASK, cmpt_ctxt[5]); - ctxt->vio_eop = (uint8_t)FIELD_GET(CMPL_CTXT_DATA_W5_VIO_EOP_MASK, - cmpt_ctxt[5]); - ctxt->sh_cmpt = (uint8_t)FIELD_GET(CMPL_CTXT_DATA_W5_SH_CMPT_MASK, - cmpt_ctxt[5]); - - ctxt->bs_addr = - FIELD_SET(EQDMA_COMPL_CTXT_BADDR_HIGH_L_MASK, - (uint64_t)baddr4_high_l) | - FIELD_SET(EQDMA_COMPL_CTXT_BADDR_HIGH_H_MASK, - (uint64_t)baddr4_high_h) | - FIELD_SET(EQDMA_COMPL_CTXT_BADDR_LOW_MASK, - (uint64_t)baddr4_low); - - ctxt->pasid = - FIELD_SET(EQDMA_CMPL_CTXT_PASID_GET_L_MASK, pasid_l) | - FIELD_SET(EQDMA_CMPL_CTXT_PASID_GET_H_MASK, - (uint64_t)pasid_h); - - ctxt->pidx = - FIELD_SET(QDMA_COMPL_CTXT_PIDX_GET_L_MASK, pidx_l) | - FIELD_SET(QDMA_COMPL_CTXT_PIDX_GET_H_MASK, pidx_h); - - return QDMA_SUCCESS; -} - -/*****************************************************************************/ -/** - * eqdma_cmpt_context_clear() - clear completion context - * - * @dev_hndl: device handle - * @hw_qid: hardware qid of the queue - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -static int eqdma_cmpt_context_clear(void *dev_hndl, uint16_t hw_qid) -{ - enum ind_ctxt_cmd_sel sel = QDMA_CTXT_SEL_CMPT; - - if (!dev_hndl) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", __func__, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - return eqdma_indirect_reg_clear(dev_hndl, sel, hw_qid); -} - -/*****************************************************************************/ -/** - * eqdma_cmpt_context_invalidate() - invalidate completion context - * - * @dev_hndl: device handle - * @hw_qid: hardware qid of the queue - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -static int eqdma_cmpt_context_invalidate(void *dev_hndl, uint16_t hw_qid) -{ - enum ind_ctxt_cmd_sel sel = QDMA_CTXT_SEL_CMPT; - - if (!dev_hndl) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", __func__, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - return eqdma_indirect_reg_invalidate(dev_hndl, sel, hw_qid); -} - -/*****************************************************************************/ -/** - * eqdma_cmpt_ctx_conf() - configure completion context - * - * @dev_hndl: device handle - * @hw_qid: hardware qid of the queue - * @ctxt: pointer to context data - * @access_type HW access type (qdma_hw_access_type enum) value - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -int eqdma_cmpt_ctx_conf(void *dev_hndl, uint16_t hw_qid, - struct qdma_descq_cmpt_ctxt *ctxt, - enum qdma_hw_access_type access_type) -{ - int rv = QDMA_SUCCESS; - - switch (access_type) { - case QDMA_HW_ACCESS_READ: - rv = eqdma_cmpt_context_read(dev_hndl, hw_qid, ctxt); - break; - case QDMA_HW_ACCESS_WRITE: - rv = eqdma_cmpt_context_write(dev_hndl, hw_qid, ctxt); - break; - case QDMA_HW_ACCESS_CLEAR: - rv = eqdma_cmpt_context_clear(dev_hndl, hw_qid); - break; - case QDMA_HW_ACCESS_INVALIDATE: - rv = eqdma_cmpt_context_invalidate(dev_hndl, hw_qid); - break; - default: - qdma_log_error("%s: access_type(%d) invalid, err:%d\n", - __func__, - access_type, - -QDMA_ERR_INV_PARAM); - rv = -QDMA_ERR_INV_PARAM; - break; - } - - return rv; -} - -/*****************************************************************************/ -/** - * eqdma_hw_context_read() - read hardware context - * - * @dev_hndl: device handle - * @c2h: is c2h queue - * @hw_qid: hardware qid of the queue - * @ctxt: pointer to the output context data - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -static int eqdma_hw_context_read(void *dev_hndl, uint8_t c2h, - uint16_t hw_qid, struct qdma_descq_hw_ctxt *ctxt) -{ - int rv = QDMA_SUCCESS; - uint32_t hw_ctxt[EQDMA_HW_CONTEXT_NUM_WORDS] = {0}; - enum ind_ctxt_cmd_sel sel = c2h ? QDMA_CTXT_SEL_HW_C2H : - QDMA_CTXT_SEL_HW_H2C; - - if (!dev_hndl || !ctxt) { - qdma_log_error("%s: dev_handle or hw_ctxt NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - rv = eqdma_indirect_reg_read(dev_hndl, sel, hw_qid, - EQDMA_HW_CONTEXT_NUM_WORDS, hw_ctxt); - if (rv < 0) - return rv; - - ctxt->cidx = FIELD_GET(HW_IND_CTXT_DATA_W0_CIDX_MASK, hw_ctxt[0]); - ctxt->crd_use = - (uint16_t)(FIELD_GET(HW_IND_CTXT_DATA_W0_CRD_USE_MASK, - hw_ctxt[0])); - - ctxt->dsc_pend = - (uint8_t)(FIELD_GET(HW_IND_CTXT_DATA_W1_DSC_PND_MASK, - hw_ctxt[1])); - ctxt->idl_stp_b = - (uint8_t)(FIELD_GET(HW_IND_CTXT_DATA_W1_IDL_STP_B_MASK, - hw_ctxt[1])); - ctxt->evt_pnd = - (uint8_t)(FIELD_GET(HW_IND_CTXT_DATA_W1_EVT_PND_MASK, - hw_ctxt[1])); - ctxt->fetch_pnd = (uint8_t) - (FIELD_GET(HW_IND_CTXT_DATA_W1_DSC_PND_MASK, hw_ctxt[1])); - - qdma_log_debug("%s: cidx=%hu, crd_use=%hu, dsc_pend=%x\n", - __func__, ctxt->cidx, ctxt->crd_use, ctxt->dsc_pend); - qdma_log_debug("%s: idl_stp_b=%x, evt_pnd=%x, fetch_pnd=%x\n", - __func__, ctxt->idl_stp_b, ctxt->evt_pnd, - ctxt->fetch_pnd); - - return QDMA_SUCCESS; -} - -/*****************************************************************************/ -/** - * eqdma_hw_context_clear() - clear hardware context - * - * @dev_hndl: device handle - * @c2h: is c2h queue - * @hw_qid: hardware qid of the queue - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -static int eqdma_hw_context_clear(void *dev_hndl, uint8_t c2h, - uint16_t hw_qid) -{ - enum ind_ctxt_cmd_sel sel = c2h ? QDMA_CTXT_SEL_HW_C2H : - QDMA_CTXT_SEL_HW_H2C; - - if (!dev_hndl) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", __func__, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - return eqdma_indirect_reg_clear(dev_hndl, sel, hw_qid); -} - -/*****************************************************************************/ -/** - * eqdma_hw_context_invalidate() - invalidate hardware context - * - * @dev_hndl: device handle - * @c2h: is c2h queue - * @hw_qid: hardware qid of the queue - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -static int eqdma_hw_context_invalidate(void *dev_hndl, uint8_t c2h, - uint16_t hw_qid) -{ - enum ind_ctxt_cmd_sel sel = c2h ? QDMA_CTXT_SEL_HW_C2H : - QDMA_CTXT_SEL_HW_H2C; - - if (!dev_hndl) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", __func__, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - return eqdma_indirect_reg_invalidate(dev_hndl, sel, hw_qid); -} - -/*****************************************************************************/ -/** - * eqdma_hw_ctx_conf() - configure HW context - * - * @dev_hndl: device handle - * @c2h: is c2h queue - * @hw_qid: hardware qid of the queue - * @ctxt: pointer to context data - * @access_type HW access type (qdma_hw_access_type enum) value - * QDMA_HW_ACCESS_WRITE Not supported - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -int eqdma_hw_ctx_conf(void *dev_hndl, uint8_t c2h, uint16_t hw_qid, - struct qdma_descq_hw_ctxt *ctxt, - enum qdma_hw_access_type access_type) -{ - int rv = QDMA_SUCCESS; - - /** ctxt requires only H2C-0 or C2H-1 - * return error for any other values - */ - if (c2h > 1) { - qdma_log_error("%s: c2h(%d) invalid, err:%d\n", - __func__, - c2h, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - switch (access_type) { - case QDMA_HW_ACCESS_READ: - rv = eqdma_hw_context_read(dev_hndl, c2h, hw_qid, ctxt); - break; - case QDMA_HW_ACCESS_CLEAR: - rv = eqdma_hw_context_clear(dev_hndl, c2h, hw_qid); - break; - case QDMA_HW_ACCESS_INVALIDATE: - rv = eqdma_hw_context_invalidate(dev_hndl, c2h, hw_qid); - break; - case QDMA_HW_ACCESS_WRITE: - default: - qdma_log_error("%s: access_type=%d is invalid, err:%d\n", - __func__, access_type, - -QDMA_ERR_INV_PARAM); - rv = -QDMA_ERR_INV_PARAM; - break; - } - - return rv; -} - -/*****************************************************************************/ -/** - * eqdma_credit_context_read() - read credit context - * - * @dev_hndl: device handle - * @c2h: is c2h queue - * @hw_qid: hardware qid of the queue - * @ctxt: pointer to the context data - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -static int eqdma_credit_context_read(void *dev_hndl, uint8_t c2h, - uint16_t hw_qid, - struct qdma_descq_credit_ctxt *ctxt) -{ - int rv = QDMA_SUCCESS; - uint32_t cr_ctxt[EQDMA_CR_CONTEXT_NUM_WORDS] = {0}; - enum ind_ctxt_cmd_sel sel = c2h ? QDMA_CTXT_SEL_CR_C2H : - QDMA_CTXT_SEL_CR_H2C; - - if (!dev_hndl || !ctxt) { - qdma_log_error("%s: dev_hndl=%p credit_ctxt=%p, err:%d\n", - __func__, dev_hndl, ctxt, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - rv = eqdma_indirect_reg_read(dev_hndl, sel, hw_qid, - EQDMA_CR_CONTEXT_NUM_WORDS, cr_ctxt); - if (rv < 0) - return rv; - - ctxt->credit = FIELD_GET(CRED_CTXT_DATA_W0_CREDT_MASK, cr_ctxt[0]); - - qdma_log_debug("%s: credit=%u\n", __func__, ctxt->credit); - - return QDMA_SUCCESS; -} - -/*****************************************************************************/ -/** - * eqdma_credit_context_clear() - clear credit context - * - * @dev_hndl: device handle - * @c2h: is c2h queue - * @hw_qid: hardware qid of the queue - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -static int eqdma_credit_context_clear(void *dev_hndl, uint8_t c2h, - uint16_t hw_qid) -{ - enum ind_ctxt_cmd_sel sel = c2h ? QDMA_CTXT_SEL_CR_C2H : - QDMA_CTXT_SEL_CR_H2C; - - if (!dev_hndl) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", __func__, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - return eqdma_indirect_reg_clear(dev_hndl, sel, hw_qid); -} - -/*****************************************************************************/ -/** - * eqdma_credit_context_invalidate() - invalidate credit context - * - * @dev_hndl: device handle - * @c2h: is c2h queue - * @hw_qid: hardware qid of the queue - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -static int eqdma_credit_context_invalidate(void *dev_hndl, uint8_t c2h, - uint16_t hw_qid) -{ - enum ind_ctxt_cmd_sel sel = c2h ? QDMA_CTXT_SEL_CR_C2H : - QDMA_CTXT_SEL_CR_H2C; - - if (!dev_hndl) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", __func__, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - return eqdma_indirect_reg_invalidate(dev_hndl, sel, hw_qid); -} - -/*****************************************************************************/ -/** - * eqdma_credit_ctx_conf() - configure credit context - * - * @dev_hndl: device handle - * @c2h: is c2h queue - * @hw_qid: hardware qid of the queue - * @ctxt: pointer to the context data - * @access_type HW access type (qdma_hw_access_type enum) value - * QDMA_HW_ACCESS_WRITE Not supported - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -int eqdma_credit_ctx_conf(void *dev_hndl, uint8_t c2h, - uint16_t hw_qid, struct qdma_descq_credit_ctxt *ctxt, - enum qdma_hw_access_type access_type) -{ - int rv = QDMA_SUCCESS; - - /** ctxt requires only H2C-0 or C2H-1 - * return error for any other values - */ - if (c2h > 1) { - qdma_log_error("%s: c2h(%d) invalid, err:%d\n", - __func__, - c2h, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - switch (access_type) { - case QDMA_HW_ACCESS_READ: - rv = eqdma_credit_context_read(dev_hndl, c2h, hw_qid, ctxt); - break; - case QDMA_HW_ACCESS_CLEAR: - rv = eqdma_credit_context_clear(dev_hndl, c2h, hw_qid); - break; - case QDMA_HW_ACCESS_INVALIDATE: - rv = eqdma_credit_context_invalidate(dev_hndl, c2h, hw_qid); - break; - case QDMA_HW_ACCESS_WRITE: - default: - qdma_log_error("%s: Invalid access type=%d, err:%d\n", - __func__, access_type, - -QDMA_ERR_INV_PARAM); - rv = -QDMA_ERR_INV_PARAM; - break; - } - - return rv; -} - -/*****************************************************************************/ -/** - * eqdma_fmap_context_write() - create fmap context and program it - * - * @dev_hndl: device handle - * @func_id: function id of the device - * @config: pointer to the fmap data strucutre - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -static int eqdma_fmap_context_write(void *dev_hndl, uint16_t func_id, - const struct qdma_fmap_cfg *config) -{ - uint32_t fmap[EQDMA_FMAP_NUM_WORDS] = {0}; - uint16_t num_words_count = 0; - enum ind_ctxt_cmd_sel sel = QDMA_CTXT_SEL_FMAP; - - if (!dev_hndl || !config) { - qdma_log_error("%s: dev_handle=%p fmap=%p NULL, err:%d\n", - __func__, dev_hndl, config, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - qdma_log_debug("%s: func_id=%hu, qbase=%hu, qmax=%hu\n", __func__, - func_id, config->qbase, config->qmax); - fmap[num_words_count++] = - FIELD_SET(EQDMA_FMAP_CTXT_W0_QID_MASK, config->qbase); - fmap[num_words_count++] = - FIELD_SET(EQDMA_FMAP_CTXT_W1_QID_MAX_MASK, config->qmax); - - return eqdma_indirect_reg_write(dev_hndl, sel, func_id, - fmap, num_words_count); -} - -/*****************************************************************************/ -/** - * eqdma_fmap_context_read() - read fmap context - * - * @dev_hndl: device handle - * @func_id: function id of the device - * @config: pointer to the output fmap data - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -static int eqdma_fmap_context_read(void *dev_hndl, uint16_t func_id, - struct qdma_fmap_cfg *config) -{ - int rv = QDMA_SUCCESS; - uint32_t fmap[EQDMA_FMAP_NUM_WORDS] = {0}; - enum ind_ctxt_cmd_sel sel = QDMA_CTXT_SEL_FMAP; - - if (!dev_hndl || !config) { - qdma_log_error("%s: dev_handle=%p fmap=%p NULL, err:%d\n", - __func__, dev_hndl, config, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - rv = eqdma_indirect_reg_read(dev_hndl, sel, func_id, - EQDMA_FMAP_NUM_WORDS, fmap); - if (rv < 0) - return rv; - - config->qbase = FIELD_GET(EQDMA_FMAP_CTXT_W0_QID_MASK, fmap[0]); - config->qmax = FIELD_GET(EQDMA_FMAP_CTXT_W1_QID_MAX_MASK, fmap[1]); - - qdma_log_debug("%s: func_id=%hu, qbase=%hu, qmax=%hu\n", __func__, - func_id, config->qbase, config->qmax); - - return QDMA_SUCCESS; -} - -/*****************************************************************************/ -/** - * eqdma_fmap_context_clear() - clear fmap context - * - * @dev_hndl: device handle - * @func_id: function id of the device - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -static int eqdma_fmap_context_clear(void *dev_hndl, uint16_t func_id) -{ - enum ind_ctxt_cmd_sel sel = QDMA_CTXT_SEL_FMAP; - - if (!dev_hndl) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", __func__, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - qdma_log_debug("%s: func_id=%hu\n", __func__, func_id); - return eqdma_indirect_reg_clear(dev_hndl, sel, func_id); -} - -/*****************************************************************************/ -/** - * eqdma_fmap_conf() - configure fmap context - * - * @dev_hndl: device handle - * @func_id: function id of the device - * @config: pointer to the fmap data - * @access_type HW access type (qdma_hw_access_type enum) value - * QDMA_HW_ACCESS_INVALIDATE Not supported - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -int eqdma_fmap_conf(void *dev_hndl, uint16_t func_id, - struct qdma_fmap_cfg *config, - enum qdma_hw_access_type access_type) -{ - int rv = QDMA_SUCCESS; - - switch (access_type) { - case QDMA_HW_ACCESS_READ: - rv = eqdma_fmap_context_read(dev_hndl, func_id, config); - break; - case QDMA_HW_ACCESS_WRITE: - rv = eqdma_fmap_context_write(dev_hndl, func_id, config); - break; - case QDMA_HW_ACCESS_CLEAR: - rv = eqdma_fmap_context_clear(dev_hndl, func_id); - break; - case QDMA_HW_ACCESS_INVALIDATE: - default: - qdma_log_error("%s: access_type(%d) invalid, err:%d\n", - __func__, - access_type, - -QDMA_ERR_INV_PARAM); - rv = -QDMA_ERR_INV_PARAM; - break; - } - - return rv; -} - -/*****************************************************************************/ -/** - * eqdma_indirect_intr_context_write() - create indirect interrupt context - * and program it - * - * @dev_hndl: device handle - * @ring_index: indirect interrupt ring index - * @ctxt: pointer to the interrupt context data strucutre - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -static int eqdma_indirect_intr_context_write(void *dev_hndl, - uint16_t ring_index, const struct qdma_indirect_intr_ctxt *ctxt) -{ - uint32_t intr_ctxt[EQDMA_IND_INTR_CONTEXT_NUM_WORDS] = {0}; - enum ind_ctxt_cmd_sel sel = QDMA_CTXT_SEL_INT_COAL; - uint32_t baddr_l, baddr_m, baddr_h, pasid_l, pasid_h; - uint16_t num_words_count = 0; - - if (!dev_hndl || !ctxt) { - qdma_log_error("%s: dev_hndl=%p intr_ctxt=%p, err:%d\n", - __func__, dev_hndl, ctxt, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - baddr_l = (uint32_t)FIELD_GET(QDMA_INTR_CTXT_BADDR_GET_L_MASK, - ctxt->baddr_4k); - baddr_m = (uint32_t)FIELD_GET(QDMA_INTR_CTXT_BADDR_GET_M_MASK, - ctxt->baddr_4k); - baddr_h = (uint32_t)FIELD_GET(QDMA_INTR_CTXT_BADDR_GET_H_MASK, - ctxt->baddr_4k); - - pasid_l = - FIELD_GET(EQDMA_INTR_CTXT_PASID_GET_L_MASK, ctxt->pasid); - pasid_h = - FIELD_GET(EQDMA_INTR_CTXT_PASID_GET_H_MASK, ctxt->pasid); - - intr_ctxt[num_words_count++] = - FIELD_SET(INTR_CTXT_DATA_W0_VALID_MASK, ctxt->valid) | - FIELD_SET(INTR_CTXT_DATA_W0_VEC_MASK, ctxt->vec) | - FIELD_SET(INTR_CTXT_DATA_W0_INT_ST_MASK, ctxt->int_st) | - FIELD_SET(INTR_CTXT_DATA_W0_COLOR_MASK, ctxt->color) | - FIELD_SET(INTR_CTXT_DATA_W0_BADDR_4K_L_MASK, baddr_l); - - intr_ctxt[num_words_count++] = - FIELD_SET(INTR_CTXT_DATA_W1_BADDR_4K_M_MASK, baddr_m); - - intr_ctxt[num_words_count++] = - FIELD_SET(INTR_CTXT_DATA_W2_BADDR_4K_H_MASK, baddr_h) | - FIELD_SET(INTR_CTXT_DATA_W2_PAGE_SIZE_MASK, ctxt->page_size) | - FIELD_SET(INTR_CTXT_DATA_W2_PIDX_MASK, ctxt->pidx) | - FIELD_SET(INTR_CTXT_DATA_W2_AT_MASK, ctxt->at) | - FIELD_SET(INTR_CTXT_DATA_W2_HOST_ID_MASK, ctxt->host_id) | - FIELD_SET(INTR_CTXT_DATA_W2_PASID_L_MASK, pasid_l); - - intr_ctxt[num_words_count++] = - FIELD_SET(INTR_CTXT_DATA_W3_PASID_H_MASK, pasid_h) | - FIELD_SET(INTR_CTXT_DATA_W3_PASID_EN_MASK, ctxt->pasid_en) | - FIELD_SET(INTR_CTXT_DATA_W3_FUNC_MASK, ctxt->func_id); - - return eqdma_indirect_reg_write(dev_hndl, sel, ring_index, - intr_ctxt, num_words_count); -} - -/*****************************************************************************/ -/** - * eqdma_indirect_intr_context_read() - read indirect interrupt context - * - * @dev_hndl: device handle - * @ring_index: indirect interrupt ring index - * @ctxt: pointer to the output context data - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -static int eqdma_indirect_intr_context_read(void *dev_hndl, - uint16_t ring_index, struct qdma_indirect_intr_ctxt *ctxt) -{ - int rv = QDMA_SUCCESS; - uint32_t intr_ctxt[EQDMA_IND_INTR_CONTEXT_NUM_WORDS] = {0}; - enum ind_ctxt_cmd_sel sel = QDMA_CTXT_SEL_INT_COAL; - uint64_t baddr_l, baddr_m, baddr_h, pasid_l, pasid_h; - - if (!dev_hndl || !ctxt) { - qdma_log_error("%s: dev_hndl=%p intr_ctxt=%p, err:%d\n", - __func__, dev_hndl, ctxt, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - rv = eqdma_indirect_reg_read(dev_hndl, sel, ring_index, - EQDMA_IND_INTR_CONTEXT_NUM_WORDS, intr_ctxt); - if (rv < 0) - return rv; - - ctxt->valid = FIELD_GET(INTR_CTXT_DATA_W0_VALID_MASK, intr_ctxt[0]); - ctxt->vec = FIELD_GET(INTR_CTXT_DATA_W0_VEC_MASK, intr_ctxt[0]); - ctxt->int_st = - (uint8_t)(FIELD_GET(INTR_CTXT_DATA_W0_INT_ST_MASK, - intr_ctxt[0])); - ctxt->color = - (uint8_t)(FIELD_GET(INTR_CTXT_DATA_W0_COLOR_MASK, - intr_ctxt[0])); - baddr_l = FIELD_GET(INTR_CTXT_DATA_W0_BADDR_4K_L_MASK, intr_ctxt[0]); - - baddr_m = FIELD_GET(INTR_CTXT_DATA_W1_BADDR_4K_M_MASK, intr_ctxt[1]); - - baddr_h = FIELD_GET(INTR_CTXT_DATA_W2_BADDR_4K_H_MASK, intr_ctxt[2]); - ctxt->page_size = - FIELD_GET(INTR_CTXT_DATA_W2_PAGE_SIZE_MASK, intr_ctxt[2]); - ctxt->pidx = - (uint16_t)(FIELD_GET(INTR_CTXT_DATA_W2_PIDX_MASK, - intr_ctxt[2])); - ctxt->at = - (uint8_t)(FIELD_GET(INTR_CTXT_DATA_W2_AT_MASK, intr_ctxt[2])); - ctxt->host_id = (uint8_t)(FIELD_GET(INTR_CTXT_DATA_W2_HOST_ID_MASK, - intr_ctxt[2])); - pasid_l = (uint8_t)(FIELD_GET(INTR_CTXT_DATA_W2_PASID_L_MASK, - intr_ctxt[2])); - - pasid_h = FIELD_GET(INTR_CTXT_DATA_W3_PASID_H_MASK, intr_ctxt[3]); - ctxt->pasid_en = (uint8_t)FIELD_GET(INTR_CTXT_DATA_W3_PASID_EN_MASK, - intr_ctxt[3]); - - ctxt->func_id = (uint16_t)FIELD_GET(INTR_CTXT_DATA_W3_FUNC_MASK, - intr_ctxt[3]); - - ctxt->baddr_4k = - FIELD_SET(QDMA_INTR_CTXT_BADDR_GET_L_MASK, baddr_l) | - FIELD_SET(QDMA_INTR_CTXT_BADDR_GET_M_MASK, baddr_m) | - FIELD_SET(QDMA_INTR_CTXT_BADDR_GET_H_MASK, baddr_h); - - ctxt->pasid = - FIELD_SET(EQDMA_INTR_CTXT_PASID_GET_L_MASK, pasid_l) | - FIELD_SET(EQDMA_INTR_CTXT_PASID_GET_H_MASK, pasid_h); - - return QDMA_SUCCESS; -} - -/*****************************************************************************/ -/** - * eqdma_indirect_intr_context_clear() - clear indirect interrupt context - * - * @dev_hndl: device handle - * @ring_index: indirect interrupt ring index - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -static int eqdma_indirect_intr_context_clear(void *dev_hndl, - uint16_t ring_index) -{ - enum ind_ctxt_cmd_sel sel = QDMA_CTXT_SEL_INT_COAL; - - if (!dev_hndl) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", __func__, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - return eqdma_indirect_reg_clear(dev_hndl, sel, ring_index); -} - -/*****************************************************************************/ -/** - * eqdma_indirect_intr_context_invalidate() - invalidate indirect interrupt - * context - * - * @dev_hndl: device handle - * @ring_index: indirect interrupt ring index - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -static int eqdma_indirect_intr_context_invalidate(void *dev_hndl, - uint16_t ring_index) -{ - enum ind_ctxt_cmd_sel sel = QDMA_CTXT_SEL_INT_COAL; - - if (!dev_hndl) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", __func__, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - return eqdma_indirect_reg_invalidate(dev_hndl, sel, ring_index); -} - -/*****************************************************************************/ -/** - * eqdma_indirect_intr_ctx_conf() - configure indirect interrupt context - * - * @dev_hndl: device handle - * @ring_index: indirect interrupt ring index - * @ctxt: pointer to context data - * @access_type HW access type (qdma_hw_access_type enum) value - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -int eqdma_indirect_intr_ctx_conf(void *dev_hndl, uint16_t ring_index, - struct qdma_indirect_intr_ctxt *ctxt, - enum qdma_hw_access_type access_type) -{ - int rv = QDMA_SUCCESS; - - switch (access_type) { - case QDMA_HW_ACCESS_READ: - rv = eqdma_indirect_intr_context_read(dev_hndl, ring_index, - ctxt); - break; - case QDMA_HW_ACCESS_WRITE: - rv = eqdma_indirect_intr_context_write(dev_hndl, ring_index, - ctxt); - break; - case QDMA_HW_ACCESS_CLEAR: - rv = eqdma_indirect_intr_context_clear(dev_hndl, - ring_index); - break; - case QDMA_HW_ACCESS_INVALIDATE: - rv = eqdma_indirect_intr_context_invalidate(dev_hndl, - ring_index); - break; - default: - qdma_log_error("%s: access_type=%d is invalid, err:%d\n", - __func__, access_type, - -QDMA_ERR_INV_PARAM); - rv = -QDMA_ERR_INV_PARAM; - break; - } - - return rv; -} - -/*****************************************************************************/ -/** - * eqdma_dump_config_regs() - Function to get qdma config register dump in a - * buffer - * - * @dev_hndl: device handle - * @is_vf: Whether PF or VF - * @buf : pointer to buffer to be filled - * @buflen : Length of the buffer - * - * Return: Length up-till the buffer is filled -success and < 0 - failure - *****************************************************************************/ -int eqdma_dump_config_regs(void *dev_hndl, uint8_t is_vf, - char *buf, uint32_t buflen) -{ - uint32_t i = 0, j = 0; - struct xreg_info *reg_info; - uint32_t num_regs = eqdma_config_num_regs_get(); - uint32_t len = 0, val = 0; - int rv = QDMA_SUCCESS; - char name[DEBGFS_GEN_NAME_SZ] = ""; - struct qdma_dev_attributes dev_cap; - - if (!dev_hndl) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - if (buflen < eqdma_reg_dump_buf_len()) { - qdma_log_error("%s: Buffer too small, err:%d\n", - __func__, -QDMA_ERR_NO_MEM); - return -QDMA_ERR_NO_MEM; - } - - if (is_vf) { - qdma_log_error("%s: Wrong API used for VF, err:%d\n", - __func__, - -QDMA_ERR_HWACC_FEATURE_NOT_SUPPORTED); - return -QDMA_ERR_HWACC_FEATURE_NOT_SUPPORTED; - } - - eqdma_get_device_attributes(dev_hndl, &dev_cap); - - reg_info = eqdma_config_regs_get(); - - for (i = 0; i < num_regs; i++) { - if ((GET_CAPABILITY_MASK(dev_cap.mm_en, dev_cap.st_en, - dev_cap.mm_cmpt_en, dev_cap.mailbox_en) - & reg_info[i].mode) == 0) - continue; - - /* If Debug Mode not enabled and the current register - * is debug register, skip reading it. - */ - if (dev_cap.debug_mode == 0 && - reg_info[i].is_debug_reg == 1) - continue; - - for (j = 0; j < reg_info[i].repeat; j++) { - rv = QDMA_SNPRINTF_S(name, DEBGFS_GEN_NAME_SZ, - DEBGFS_GEN_NAME_SZ, - "%s", reg_info[i].name); - if ((rv < 0) || (rv > DEBGFS_GEN_NAME_SZ)) { - qdma_log_error( - "%d:%s QDMA_SNPRINTF_S() failed, err:%d\n", - __LINE__, __func__, - rv); - return -QDMA_ERR_NO_MEM; - } - val = qdma_reg_read(dev_hndl, - (reg_info[i].addr + (j * 4))); - rv = dump_reg(buf + len, buflen - len, - (reg_info[i].addr + (j * 4)), - name, val); - if (rv < 0) { - qdma_log_error( - "%s Buff too small, err:%d\n", - __func__, - -QDMA_ERR_NO_MEM); - return -QDMA_ERR_NO_MEM; - } - len += rv; - } - } - - return len; -} - -/*****************************************************************************/ -/** - * qdma_dump_cpm_queue_context() - Function to get qdma queue context dump - * in a buffer - * - * @dev_hndl: device handle - * @st: Queue Mode(ST or MM) - * @q_type: Queue type(H2C/C2H/CMPT) - * @context: Queue Context - * @buf : pointer to buffer to be filled - * @buflen : Length of the buffer - * - * Return: Length up-till the buffer is filled -success and < 0 - failure - *****************************************************************************/ -int eqdma_dump_queue_context(void *dev_hndl, - uint8_t st, - enum qdma_dev_q_type q_type, - struct qdma_descq_context *ctxt_data, - char *buf, uint32_t buflen) -{ - int rv = 0; - uint32_t req_buflen = 0; - - if (!dev_hndl) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - - return -QDMA_ERR_INV_PARAM; - } - - if (!ctxt_data) { - qdma_log_error("%s: ctxt_data is NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - - return -QDMA_ERR_INV_PARAM; - } - - if (!buf) { - qdma_log_error("%s: buf is NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - - return -QDMA_ERR_INV_PARAM; - } - - if (q_type >= QDMA_DEV_Q_TYPE_MAX) { - qdma_log_error("%s: invalid q_type, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - - return -QDMA_ERR_INV_PARAM; - } - - rv = eqdma_context_buf_len(st, q_type, &req_buflen); - if (rv != QDMA_SUCCESS) - return rv; - - if (buflen < req_buflen) { - qdma_log_error("%s: Too small buffer(%d), reqd(%d), err:%d\n", - __func__, buflen, req_buflen, -QDMA_ERR_NO_MEM); - return -QDMA_ERR_NO_MEM; - } - - rv = dump_eqdma_context(ctxt_data, st, q_type, - buf, buflen); - - return rv; -} - -/*****************************************************************************/ -/** - * eqdma_dump_intr_context() - Function to get qdma interrupt context dump - * in a buffer - * - * @dev_hndl: device handle - * @intr_ctx: Interrupt Context - * @ring_index: Ring index - * @buf : pointer to buffer to be filled - * @buflen : Length of the buffer - * - * Return: Length up-till the buffer is filled -success and < 0 - failure - *****************************************************************************/ -int eqdma_dump_intr_context(void *dev_hndl, - struct qdma_indirect_intr_ctxt *intr_ctx, - int ring_index, - char *buf, uint32_t buflen) -{ - int rv = 0; - uint32_t req_buflen = 0; - - if (!dev_hndl) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - - return -QDMA_ERR_INV_PARAM; - } - if (!intr_ctx) { - qdma_log_error("%s: intr_ctx is NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - if (!buf) { - qdma_log_error("%s: buf is NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - req_buflen = eqdma_intr_context_buf_len(); - if (buflen < req_buflen) { - qdma_log_error("%s: Too small buffer(%d), reqd(%d), err:%d\n", - __func__, buflen, req_buflen, -QDMA_ERR_NO_MEM); - return -QDMA_ERR_NO_MEM; - } - - rv = dump_eqdma_intr_context(intr_ctx, ring_index, buf, buflen); - - return rv; -} - -/*****************************************************************************/ -/** - * eqdma_read_dump_queue_context() - Function to read and dump the queue - * context in a buffer - * - * @dev_hndl: device handle - * @func_id: function id - * @hw_qid: queue id - * @st: Queue Mode(ST or MM) - * @q_type: Queue type(H2C/C2H/CMPT) - * @buf : pointer to buffer to be filled - * @buflen : Length of the buffer - * - * Return: Length up-till the buffer is filled -success and < 0 - failure - *****************************************************************************/ -int eqdma_read_dump_queue_context(void *dev_hndl, - uint16_t func_id, - uint16_t qid_hw, - uint8_t st, - enum qdma_dev_q_type q_type, - char *buf, uint32_t buflen) -{ - int rv = QDMA_SUCCESS; - uint32_t req_buflen = 0; - struct qdma_descq_context context; - - if (!dev_hndl) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - - return -QDMA_ERR_INV_PARAM; - } - - if (!buf) { - qdma_log_error("%s: buf is NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - - return -QDMA_ERR_INV_PARAM; - } - - if (q_type >= QDMA_DEV_Q_TYPE_MAX) { - qdma_log_error("%s: Not supported for q_type, err = %d\n", - __func__, -QDMA_ERR_INV_PARAM); - - return -QDMA_ERR_INV_PARAM; - } - - rv = eqdma_context_buf_len(st, q_type, &req_buflen); - if (rv != QDMA_SUCCESS) - return rv; - - if (buflen < req_buflen) { - qdma_log_error("%s: Too small buffer(%d), reqd(%d), err:%d\n", - __func__, buflen, req_buflen, -QDMA_ERR_NO_MEM); - return -QDMA_ERR_NO_MEM; - } - - qdma_memset(&context, 0, sizeof(struct qdma_descq_context)); - - if (q_type != QDMA_DEV_Q_TYPE_CMPT) { - rv = eqdma_sw_ctx_conf(dev_hndl, (uint8_t)q_type, qid_hw, - &(context.sw_ctxt), QDMA_HW_ACCESS_READ); - if (rv < 0) { - qdma_log_error( - "%s: Failed to read sw context, err = %d", - __func__, rv); - return rv; - } - - rv = eqdma_hw_ctx_conf(dev_hndl, (uint8_t)q_type, qid_hw, - &(context.hw_ctxt), QDMA_HW_ACCESS_READ); - if (rv < 0) { - qdma_log_error( - "%s: Failed to read hw context, err = %d", - __func__, rv); - return rv; - } - - rv = eqdma_credit_ctx_conf(dev_hndl, (uint8_t)q_type, - qid_hw, &(context.cr_ctxt), - QDMA_HW_ACCESS_READ); - if (rv < 0) { - qdma_log_error( - "%s: Failed to read credit context, err = %d", - __func__, rv); - return rv; - } - - if (st && (q_type == QDMA_DEV_Q_TYPE_C2H)) { - rv = eqdma_pfetch_ctx_conf(dev_hndl, - qid_hw, - &(context.pfetch_ctxt), - QDMA_HW_ACCESS_READ); - if (rv < 0) { - qdma_log_error( - "%s: Failed to read pftech context, err = %d", - __func__, rv); - return rv; - } - } - } - - if ((st && (q_type == QDMA_DEV_Q_TYPE_C2H)) || - (!st && (q_type == QDMA_DEV_Q_TYPE_CMPT))) { - rv = eqdma_cmpt_ctx_conf(dev_hndl, qid_hw, - &(context.cmpt_ctxt), - QDMA_HW_ACCESS_READ); - if (rv < 0) { - qdma_log_error( - "%s: Failed to read cmpt context, err = %d", - __func__, rv); - return rv; - } - } - - rv = eqdma_fmap_conf(dev_hndl, func_id, - &(context.fmap), QDMA_HW_ACCESS_READ); - if (rv < 0) { - qdma_log_error( - "%s: Failed to read fmap context, err = %d", - __func__, rv); - return rv; - } - - rv = dump_eqdma_context(&context, st, q_type, - buf, buflen); - - return rv; -} - -/*****************************************************************************/ -/** - * eqdma_get_user_bar() - Function to get the AXI Master Lite(user bar) number - * - * @dev_hndl: device handle - * @is_vf: Whether PF or VF - * @func_id: function id of the PF - * @user_bar: pointer to hold the AXI Master Lite bar number - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -int eqdma_get_user_bar(void *dev_hndl, uint8_t is_vf, - uint16_t func_id, uint8_t *user_bar) -{ - uint8_t bar_found = 0; - uint8_t bar_idx = 0; - uint32_t user_bar_id = 0; - uint32_t reg_addr = (is_vf) ? EQDMA_OFFSET_VF_USER_BAR : - EQDMA_OFFSET_GLBL2_PF_BARLITE_EXT; - - if (!dev_hndl) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - if (!user_bar) { - qdma_log_error("%s: AXI Master Lite bar is NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - user_bar_id = qdma_reg_read(dev_hndl, reg_addr); - user_bar_id = (user_bar_id >> (6 * func_id)) & 0x3F; - - for (bar_idx = 0; bar_idx < QDMA_BAR_NUM; bar_idx++) { - if (user_bar_id & (1 << bar_idx)) { - *user_bar = bar_idx; - bar_found = 1; - break; - } - } - if (bar_found == 0) { - *user_bar = 0; - qdma_log_error("%s: Bar not found, err:%d\n", - __func__, - -QDMA_ERR_HWACC_BAR_NOT_FOUND); - return -QDMA_ERR_HWACC_BAR_NOT_FOUND; - } - - return QDMA_SUCCESS; -} - -/*****************************************************************************/ -/** - * eqdma_hw_ram_sbe_err_process() - Function to dump SBE error debug information - * - * @dev_hndl: device handle - * @buf: Bufffer for the debug info to be dumped in - * @buflen: Length of the buffer - * - * Return: void - *****************************************************************************/ -static void eqdma_hw_ram_sbe_err_process(void *dev_hndl) -{ - eqdma_dump_reg_info(dev_hndl, EQDMA_RAM_SBE_STS_A_ADDR, - 1, NULL, 0); - eqdma_dump_reg_info(dev_hndl, EQDMA_RAM_SBE_STS_1_A_ADDR, - 1, NULL, 0); -} - -/*****************************************************************************/ -/** - * eqdma_hw_ram_dbe_err_process() - Function to dump DBE error debug information - * - * @dev_hndl: device handle - * @buf: Bufffer for the debug info to be dumped in - * @buflen: Length of the buffer - * - * Return: void - *****************************************************************************/ -static void eqdma_hw_ram_dbe_err_process(void *dev_hndl) -{ - eqdma_dump_reg_info(dev_hndl, EQDMA_RAM_DBE_STS_A_ADDR, - 1, NULL, 0); - eqdma_dump_reg_info(dev_hndl, EQDMA_RAM_DBE_STS_1_A_ADDR, - 1, NULL, 0); -} - -/*****************************************************************************/ -/** - * eqdma_hw_desc_err_process() - Function to dump Descriptor Error information - * - * @dev_hndl: device handle - * @buf: Bufffer for the debug info to be dumped in - * @buflen: Length of the buffer - * - * Return: void - *****************************************************************************/ -static void eqdma_hw_desc_err_process(void *dev_hndl) -{ - int i = 0; - uint32_t desc_err_reg_list[] = { - EQDMA_GLBL_DSC_ERR_STS_ADDR, - EQDMA_GLBL_DSC_ERR_LOG0_ADDR, - EQDMA_GLBL_DSC_ERR_LOG1_ADDR, - EQDMA_GLBL_DSC_DBG_DAT0_ADDR, - EQDMA_GLBL_DSC_DBG_DAT1_ADDR, - EQDMA_GLBL_DSC_ERR_LOG2_ADDR - }; - int desc_err_num_regs = sizeof(desc_err_reg_list)/sizeof(uint32_t); - - for (i = 0; i < desc_err_num_regs; i++) { - eqdma_dump_reg_info(dev_hndl, desc_err_reg_list[i], - 1, NULL, 0); - } -} - -/*****************************************************************************/ -/** - * eqdma_hw_trq_err_process() - Function to dump Target Access Error information - * - * @dev_hndl: device handle - * @buf: Bufffer for the debug info to be dumped in - * @buflen: Length of the buffer - * - * Return: void - *****************************************************************************/ -static void eqdma_hw_trq_err_process(void *dev_hndl) -{ - int i = 0; - uint32_t trq_err_reg_list[] = { - EQDMA_GLBL_TRQ_ERR_STS_ADDR, - EQDMA_GLBL_TRQ_ERR_LOG_ADDR - }; - int trq_err_reg_num_regs = sizeof(trq_err_reg_list)/sizeof(uint32_t); - - for (i = 0; i < trq_err_reg_num_regs; i++) { - eqdma_dump_reg_info(dev_hndl, trq_err_reg_list[i], - 1, NULL, 0); - } -} - -/*****************************************************************************/ -/** - * eqdma_hw_err_dump_ctxt_info() - Dump the imp ctxt fields on HW error - * - * @dev_hndl: device handle - * @first_err_qid: First Error QID - * @en_st: ST Mode or MM Mode enabled - * @c2h: C2H or H2C Mode - * - * Return: void - *****************************************************************************/ -static void eqdma_hw_err_dump_ctxt_info(void *dev_hndl, - uint32_t first_err_qid_reg, - uint8_t en_st, uint8_t c2h) -{ - uint16_t first_err_qid = 0; - struct qdma_descq_sw_ctxt sw_ctxt; - struct qdma_descq_hw_ctxt hw_ctxt; - struct qdma_descq_cmpt_ctxt cmpt_ctxt; - - first_err_qid = qdma_reg_read(dev_hndl, first_err_qid_reg); - - eqdma_sw_context_read(dev_hndl, c2h, first_err_qid, &sw_ctxt); - eqdma_hw_context_read(dev_hndl, c2h, first_err_qid, &hw_ctxt); - eqdma_fill_sw_ctxt(&sw_ctxt); - eqdma_fill_hw_ctxt(&hw_ctxt); - - if (sw_ctxt.pidx != hw_ctxt.cidx) { - qdma_log_info("\n%40s\n", "SW Context:"); - /** SW Context: PIDX ***/ - qdma_log_info("%-47s %#-10x %u\n", - eqdma_sw_ctxt_entries[0].name, - eqdma_sw_ctxt_entries[0].value, - eqdma_sw_ctxt_entries[0].value); - qdma_log_info("\n%40s\n", "HW Context:"); - /*** HW Context: CIDX ***/ - qdma_log_info("%-47s %#-10x %u\n", - eqdma_hw_ctxt_entries[0].name, - eqdma_hw_ctxt_entries[0].value, - eqdma_hw_ctxt_entries[0].value); - } - - if (sw_ctxt.err != 0) { - /*** SW Context: ERR ***/ - qdma_log_info("%-47s %#-10x %u\n", - eqdma_sw_ctxt_entries[17].name, - eqdma_sw_ctxt_entries[17].value, - eqdma_sw_ctxt_entries[17].value); - } - - /*** SW Context: ERR WB SENT***/ - qdma_log_info("%-47s %#-10x %u\n", - eqdma_sw_ctxt_entries[18].name, - eqdma_sw_ctxt_entries[18].value, - eqdma_sw_ctxt_entries[18].value); - - /*** SW Context: IRQ REQ***/ - qdma_log_info("%-47s %#-10x %u\n", - eqdma_sw_ctxt_entries[19].name, - eqdma_sw_ctxt_entries[19].value, - eqdma_sw_ctxt_entries[19].value); - - if (en_st && c2h) { - eqdma_cmpt_context_read(dev_hndl, first_err_qid, &cmpt_ctxt); - eqdma_fill_cmpt_ctxt(&cmpt_ctxt); - - qdma_log_info("\n%40s\n", "CMPT Context:"); - - /*** CMPT Context: int_st ***/ - qdma_log_info("%-47s %#-10x %u\n", - eqdma_cmpt_ctxt_entries[6].name, - eqdma_cmpt_ctxt_entries[6].value, - eqdma_cmpt_ctxt_entries[6].value); - - /** CMPT Context: PIDX ***/ - qdma_log_info("%-47s %#-10x %u\n", - eqdma_cmpt_ctxt_entries[12].name, - eqdma_cmpt_ctxt_entries[12].value, - eqdma_cmpt_ctxt_entries[12].value); - /*** CMPT Context: CIDX ***/ - qdma_log_info("%-47s %#-10x %u\n", - eqdma_cmpt_ctxt_entries[13].name, - eqdma_cmpt_ctxt_entries[13].value, - eqdma_cmpt_ctxt_entries[13].value); - - if (cmpt_ctxt.err != 0) { - /*** CMPT Context: ERR ***/ - qdma_log_info("%-47s %#-10x %u\n", - eqdma_cmpt_ctxt_entries[15].name, - eqdma_cmpt_ctxt_entries[15].value, - eqdma_cmpt_ctxt_entries[15].value); - } - } -} -/*****************************************************************************/ -/** - * eqdma_hw_st_h2c_err_process() - Function to dump MM H2C Error information - * - * @dev_hndl: device handle - * @buf: Bufffer for the debug info to be dumped in - * @buflen: Length of the buffer - * - * Return: void - *****************************************************************************/ -static void eqdma_hw_st_h2c_err_process(void *dev_hndl) -{ - int i = 0; - uint32_t st_h2c_err_reg_list[] = { - EQDMA_H2C_ERR_STAT_ADDR, - EQDMA_H2C_FIRST_ERR_QID_ADDR, - EQDMA_H2C_DBG_REG0_ADDR, - EQDMA_H2C_DBG_REG1_ADDR, - EQDMA_H2C_DBG_REG2_ADDR, - EQDMA_H2C_DBG_REG3_ADDR, - EQDMA_H2C_DBG_REG4_ADDR - }; - int st_h2c_err_num_regs = sizeof(st_h2c_err_reg_list)/sizeof(uint32_t); - - for (i = 0; i < st_h2c_err_num_regs; i++) { - eqdma_dump_reg_info(dev_hndl, st_h2c_err_reg_list[i], - 1, NULL, 0); - } - - eqdma_hw_err_dump_ctxt_info(dev_hndl, - EQDMA_H2C_FIRST_ERR_QID_ADDR, 1, 0); - -} - - -/*****************************************************************************/ -/** - * eqdma_hw_st_c2h_err_process() - Function to dump MM H2C Error information - * - * @dev_hndl: device handle - * @buf: Bufffer for the debug info to be dumped in - * @buflen: Length of the buffer - * - * Return: void - *****************************************************************************/ -static void eqdma_hw_st_c2h_err_process(void *dev_hndl) -{ - int i = 0; - - uint32_t st_c2h_err_reg_list[] = { - EQDMA_C2H_ERR_STAT_ADDR, - EQDMA_C2H_FATAL_ERR_STAT_ADDR, - EQDMA_C2H_FIRST_ERR_QID_ADDR, - EQDMA_C2H_STAT_S_AXIS_C2H_ACCEPTED_ADDR, - EQDMA_C2H_STAT_S_AXIS_WRB_ACCEPTED_ADDR, - EQDMA_C2H_STAT_DESC_RSP_PKT_ACCEPTED_ADDR, - EQDMA_C2H_STAT_AXIS_PKG_CMP_ADDR, - EQDMA_C2H_STAT_DBG_DMA_ENG_0_ADDR, - EQDMA_C2H_STAT_DBG_DMA_ENG_1_ADDR, - EQDMA_C2H_STAT_DBG_DMA_ENG_2_ADDR, - EQDMA_C2H_STAT_DBG_DMA_ENG_3_ADDR, - EQDMA_C2H_STAT_DESC_RSP_DROP_ACCEPTED_ADDR, - EQDMA_C2H_STAT_DESC_RSP_ERR_ACCEPTED_ADDR - }; - int st_c2h_err_num_regs = sizeof(st_c2h_err_reg_list)/sizeof(uint32_t); - - for (i = 0; i < st_c2h_err_num_regs; i++) { - eqdma_dump_reg_info(dev_hndl, st_c2h_err_reg_list[i], - 1, NULL, 0); - } - - eqdma_hw_err_dump_ctxt_info(dev_hndl, - EQDMA_C2H_FIRST_ERR_QID_ADDR, 1, 1); - -} - -/*****************************************************************************/ -/** - * eqdma_mm_c2h0_err_process() - Function to dump MM C2H - * Error information - * - * @dev_hndl: device handle - * - * Return: void - *****************************************************************************/ -static void eqdma_mm_c2h0_err_process(void *dev_hndl) -{ - int i = 0; - uint32_t mm_c2h_err_reg_list[] = { - EQDMA_C2H_MM_STATUS_ADDR, - EQDMA_C2H_MM_CMPL_DESC_CNT_ADDR, - EQDMA_C2H_MM_ERR_CODE_ADDR, - EQDMA_C2H_MM_ERR_INFO_ADDR, - EQDMA_C2H_MM_DBG_ADDR - }; - int mm_c2h_err_num_regs = sizeof(mm_c2h_err_reg_list)/sizeof(uint32_t); - - for (i = 0; i < mm_c2h_err_num_regs; i++) { - eqdma_dump_reg_info(dev_hndl, mm_c2h_err_reg_list[i], - 1, NULL, 0); - } - - eqdma_hw_err_dump_ctxt_info(dev_hndl, - EQDMA_C2H_MM_ERR_INFO_ADDR, 0, 1); -} - -/*****************************************************************************/ -/** - * eqdma_mm_h2c0_err_process() - Function to dump MM H2C - * Error information - * - * @dev_hndl: device handle - * - * Return: void - *****************************************************************************/ -static void eqdma_mm_h2c0_err_process(void *dev_hndl) -{ - int i = 0; - uint32_t mm_h2c_err_reg_list[] = { - EQDMA_H2C_MM_STATUS_ADDR, - EQDMA_H2C_MM_CMPL_DESC_CNT_ADDR, - EQDMA_H2C_MM_ERR_CODE_ADDR, - EQDMA_H2C_MM_ERR_INFO_ADDR, - EQDMA_H2C_MM_DBG_ADDR - }; - int mm_h2c_err_num_regs = sizeof(mm_h2c_err_reg_list)/sizeof(uint32_t); - - for (i = 0; i < mm_h2c_err_num_regs; i++) { - eqdma_dump_reg_info(dev_hndl, mm_h2c_err_reg_list[i], - 1, NULL, 0); - } - - eqdma_hw_err_dump_ctxt_info(dev_hndl, - EQDMA_H2C_MM_ERR_INFO_ADDR, 0, 1); -} - -/*****************************************************************************/ -/** - * eqdma_hw_get_error_name() - Function to get the error in string format - * - * @err_idx: error index - * - * Return: string - success and NULL on failure - *****************************************************************************/ -const char *eqdma_hw_get_error_name(uint32_t err_idx) -{ - if (err_idx >= EQDMA_ERRS_ALL) { - qdma_log_error("%s: err_idx=%d is invalid, returning NULL\n", - __func__, (enum eqdma_error_idx)err_idx); - return NULL; - } - - return eqdma_err_info[(enum eqdma_error_idx)err_idx].err_name; -} - -/*****************************************************************************/ -/** - * eqdma_hw_error_process() - Function to find the error that got - * triggered and call the handler qdma_hw_error_handler of that - * particular error. - * - * @dev_hndl: device handle - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -int eqdma_hw_error_process(void *dev_hndl) -{ - uint32_t glbl_err_stat = 0, err_stat = 0; - uint32_t bit = 0, i = 0; - int32_t idx = 0; - struct qdma_dev_attributes dev_cap; - uint32_t hw_err_position[EQDMA_TOTAL_LEAF_ERROR_AGGREGATORS] = { - EQDMA_DSC_ERR_POISON, - EQDMA_TRQ_ERR_CSR_UNMAPPED, - EQDMA_ST_C2H_ERR_MTY_MISMATCH, - EQDMA_ST_FATAL_ERR_MTY_MISMATCH, - EQDMA_ST_H2C_ERR_ZERO_LEN_DESC, - EQDMA_SBE_1_ERR_RC_RRQ_EVEN_RAM, - EQDMA_SBE_ERR_MI_H2C0_DAT, - EQDMA_DBE_1_ERR_RC_RRQ_EVEN_RAM, - EQDMA_DBE_ERR_MI_H2C0_DAT, - EQDMA_MM_C2H_WR_SLR_ERR, - EQDMA_MM_H2C0_RD_HDR_POISON_ERR - }; - - if (!dev_hndl) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - - eqdma_get_device_attributes(dev_hndl, &dev_cap); - - glbl_err_stat = qdma_reg_read(dev_hndl, EQDMA_GLBL_ERR_STAT_ADDR); - - if (!glbl_err_stat) - return QDMA_HW_ERR_NOT_DETECTED; - - - qdma_log_info("%s: Global Err Reg(0x%x) = 0x%x\n", - __func__, EQDMA_GLBL_ERR_STAT_ADDR, - glbl_err_stat); - - for (i = 0; i < EQDMA_TOTAL_LEAF_ERROR_AGGREGATORS; i++) { - bit = hw_err_position[i]; - - if ((!dev_cap.st_en) && (bit == EQDMA_ST_C2H_ERR_MTY_MISMATCH || - bit == EQDMA_ST_FATAL_ERR_MTY_MISMATCH || - bit == EQDMA_ST_H2C_ERR_ZERO_LEN_DESC)) - continue; - - err_stat = qdma_reg_read(dev_hndl, - eqdma_err_info[bit].stat_reg_addr); - if (err_stat) { - qdma_log_info("addr = 0x%08x val = 0x%08x", - eqdma_err_info[bit].stat_reg_addr, - err_stat); - - eqdma_err_info[bit].eqdma_hw_err_process( - dev_hndl); - for (idx = bit; idx < all_eqdma_hw_errs[i]; idx++) { - /* call the platform specific handler */ - if (err_stat & - eqdma_err_info[idx].leaf_err_mask) - qdma_log_error("%s detected %s\n", - __func__, - eqdma_hw_get_error_name(idx)); - } - qdma_reg_write(dev_hndl, - eqdma_err_info[bit].stat_reg_addr, - err_stat); - } - - } - - /* Write 1 to the global status register to clear the bits */ - qdma_reg_write(dev_hndl, EQDMA_GLBL_ERR_STAT_ADDR, glbl_err_stat); - - return QDMA_SUCCESS; -} - -/*****************************************************************************/ -/** - * qdma_hw_error_enable() - Function to enable all or a specific error - * - * @dev_hndl: device handle - * @err_idx: error index - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -int eqdma_hw_error_enable(void *dev_hndl, uint32_t err_idx) -{ - uint32_t idx = 0, i = 0; - uint32_t reg_val = 0; - struct qdma_dev_attributes dev_cap; - - if (!dev_hndl) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - if (err_idx > EQDMA_ERRS_ALL) { - qdma_log_error("%s: err_idx=%d is invalid, err:%d\n", - __func__, (enum eqdma_error_idx)err_idx, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - eqdma_get_device_attributes(dev_hndl, &dev_cap); - - if (err_idx == EQDMA_ERRS_ALL) { - for (i = 0; i < EQDMA_TOTAL_LEAF_ERROR_AGGREGATORS; i++) { - - idx = all_eqdma_hw_errs[i]; - - /* Don't access streaming registers in - * MM only bitstreams - */ - if (!dev_cap.st_en) { - if (idx == EQDMA_ST_C2H_ERR_ALL || - idx == EQDMA_ST_FATAL_ERR_ALL || - idx == EQDMA_ST_H2C_ERR_ALL) - continue; - } - - reg_val = eqdma_err_info[idx].leaf_err_mask; - qdma_reg_write(dev_hndl, - eqdma_err_info[idx].mask_reg_addr, reg_val); - - reg_val = qdma_reg_read(dev_hndl, - EQDMA_GLBL_ERR_MASK_ADDR); - reg_val |= FIELD_SET( - eqdma_err_info[idx].global_err_mask, 1); - qdma_reg_write(dev_hndl, EQDMA_GLBL_ERR_MASK_ADDR, - reg_val); - } - - } else { - /* Don't access streaming registers in MM only bitstreams - * QDMA_C2H_ERR_MTY_MISMATCH to QDMA_H2C_ERR_ALL are all - * ST errors - */ - if (!dev_cap.st_en) { - if (err_idx >= EQDMA_ST_C2H_ERR_MTY_MISMATCH && - err_idx <= EQDMA_ST_H2C_ERR_ALL) - return QDMA_SUCCESS; - } - - reg_val = qdma_reg_read(dev_hndl, - eqdma_err_info[err_idx].mask_reg_addr); - reg_val |= FIELD_SET(eqdma_err_info[err_idx].leaf_err_mask, 1); - qdma_reg_write(dev_hndl, - eqdma_err_info[err_idx].mask_reg_addr, reg_val); - - reg_val = qdma_reg_read(dev_hndl, EQDMA_GLBL_ERR_MASK_ADDR); - reg_val |= - FIELD_SET(eqdma_err_info[err_idx].global_err_mask, 1); - qdma_reg_write(dev_hndl, EQDMA_GLBL_ERR_MASK_ADDR, reg_val); - } - - return QDMA_SUCCESS; -} - -/*****************************************************************************/ -/** - * eqdma_get_device_attributes() - Function to get the qdma device - * attributes - * - * @dev_hndl: device handle - * @dev_info: pointer to hold the device info - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -int eqdma_get_device_attributes(void *dev_hndl, - struct qdma_dev_attributes *dev_info) -{ - uint8_t count = 0; - uint32_t reg_val = 0; - - if (!dev_hndl) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - if (!dev_info) { - qdma_log_error("%s: dev_info is NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - /* number of PFs */ - reg_val = qdma_reg_read(dev_hndl, QDMA_OFFSET_GLBL2_PF_BARLITE_INT); - if (FIELD_GET(QDMA_GLBL2_PF0_BAR_MAP_MASK, reg_val)) - count++; - if (FIELD_GET(QDMA_GLBL2_PF1_BAR_MAP_MASK, reg_val)) - count++; - if (FIELD_GET(QDMA_GLBL2_PF2_BAR_MAP_MASK, reg_val)) - count++; - if (FIELD_GET(QDMA_GLBL2_PF3_BAR_MAP_MASK, reg_val)) - count++; - dev_info->num_pfs = count; - - /* Number of Qs */ - reg_val = qdma_reg_read(dev_hndl, EQDMA_GLBL2_CHANNEL_CAP_ADDR); - dev_info->num_qs = - FIELD_GET(GLBL2_CHANNEL_CAP_MULTIQ_MAX_MASK, reg_val); - - /* FLR present */ - reg_val = qdma_reg_read(dev_hndl, EQDMA_GLBL2_MISC_CAP_ADDR); - dev_info->mailbox_en = FIELD_GET(EQDMA_GLBL2_MAILBOX_EN_MASK, - reg_val); - dev_info->flr_present = FIELD_GET(EQDMA_GLBL2_FLR_PRESENT_MASK, - reg_val); - dev_info->mm_cmpt_en = 0; - dev_info->debug_mode = FIELD_GET(EQDMA_GLBL2_DBG_MODE_EN_MASK, - reg_val); - dev_info->desc_eng_mode = FIELD_GET(EQDMA_GLBL2_DESC_ENG_MODE_MASK, - reg_val); - - /* ST/MM enabled? */ - reg_val = qdma_reg_read(dev_hndl, EQDMA_GLBL2_CHANNEL_MDMA_ADDR); - dev_info->st_en = (FIELD_GET(GLBL2_CHANNEL_MDMA_C2H_ST_MASK, reg_val) - && FIELD_GET(GLBL2_CHANNEL_MDMA_H2C_ST_MASK, reg_val)) ? 1 : 0; - dev_info->mm_en = (FIELD_GET(GLBL2_CHANNEL_MDMA_C2H_ENG_MASK, reg_val) - && FIELD_GET(GLBL2_CHANNEL_MDMA_H2C_ENG_MASK, reg_val)) ? 1 : 0; - - /* num of mm channels */ - /* TODO : Register not yet defined for this. Hard coding it to 1.*/ - dev_info->mm_channel_max = 1; - - dev_info->qid2vec_ctx = 0; - dev_info->cmpt_ovf_chk_dis = 1; - dev_info->mailbox_intr = 1; - dev_info->sw_desc_64b = 1; - dev_info->cmpt_desc_64b = 1; - dev_info->dynamic_bar = 1; - dev_info->legacy_intr = 1; - dev_info->cmpt_trig_count_timer = 1; - - return QDMA_SUCCESS; -} - -/*****************************************************************************/ -/** - * eqdma_init_ctxt_memory() - function to initialize the context memory - * - * @dev_hndl: device handle - * - * Return: returns the platform specific error code - *****************************************************************************/ -int eqdma_init_ctxt_memory(void *dev_hndl) -{ -#ifdef ENABLE_INIT_CTXT_MEMORY - uint32_t data[QDMA_REG_IND_CTXT_REG_COUNT]; - uint16_t i = 0; - struct qdma_dev_attributes dev_info; - - if (!dev_hndl) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - qdma_memset(data, 0, sizeof(uint32_t) * QDMA_REG_IND_CTXT_REG_COUNT); - eqdma_get_device_attributes(dev_hndl, &dev_info); - - for (; i < dev_info.num_qs; i++) { - int sel = QDMA_CTXT_SEL_SW_C2H; - int rv; - - for (; sel <= QDMA_CTXT_SEL_PFTCH; sel++) { - /** if the st mode(h2c/c2h) not enabled - * in the design, then skip the PFTCH - * and CMPT context setup - */ - if ((dev_info.st_en == 0) && - ((sel == QDMA_CTXT_SEL_PFTCH) || - (sel == QDMA_CTXT_SEL_CMPT))) { - qdma_log_debug("%s: ST context is skipped:", - __func__); - qdma_log_debug("sel = %d\n", sel); - continue; - } - - rv = eqdma_indirect_reg_clear(dev_hndl, - (enum ind_ctxt_cmd_sel)sel, i); - if (rv < 0) - return rv; - } - } - - /* fmap */ - for (i = 0; i < dev_info.num_pfs; i++) - eqdma_indirect_reg_clear(dev_hndl, - QDMA_CTXT_SEL_FMAP, i); - -#else - if (!dev_hndl) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } -#endif - return QDMA_SUCCESS; - -} - - -static int get_reg_entry(uint32_t reg_addr, int *reg_entry) -{ - uint32_t i = 0; - struct xreg_info *reg_info; - uint32_t num_regs = eqdma_config_num_regs_get(); - - reg_info = eqdma_config_regs_get(); - - for (i = 0; (i < num_regs - 1); i++) { - if (reg_info[i].addr == reg_addr) { - *reg_entry = i; - break; - } - } - - if (i >= num_regs - 1) { - qdma_log_error("%s: 0x%08x is missing register list, err:%d\n", - __func__, - reg_addr, - -QDMA_ERR_INV_PARAM); - *reg_entry = -1; - return -QDMA_ERR_INV_PARAM; - } - - return 0; -} - -/*****************************************************************************/ -/** - * eqdma_dump_config_reg_list() - Dump the registers - * - * @dev_hndl: device handle - * @total_regs : Max registers to read - * @reg_list : array of reg addr and reg values - * @buf : pointer to buffer to be filled - * @buflen : Length of the buffer - * - * Return: returns the platform specific error code - *****************************************************************************/ -int eqdma_dump_config_reg_list(void *dev_hndl, uint32_t total_regs, - struct qdma_reg_data *reg_list, char *buf, uint32_t buflen) -{ - uint32_t j = 0, len = 0; - uint32_t reg_count = 0; - int reg_data_entry; - int rv = 0; - char name[DEBGFS_GEN_NAME_SZ] = ""; - struct xreg_info *reg_info = eqdma_config_regs_get(); - struct qdma_dev_attributes dev_cap; - - if (!dev_hndl) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - if (!buf) { - qdma_log_error("%s: buf is NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - eqdma_get_device_attributes(dev_hndl, &dev_cap); - - for (reg_count = 0; - (reg_count < total_regs);) { - - /* If Debug Mode not enabled and the current register - * is debug register, skip reading it. - */ - if (dev_cap.debug_mode == 0 && - reg_info[reg_count].is_debug_reg == 1) - continue; - - rv = get_reg_entry(reg_list[reg_count].reg_addr, - ®_data_entry); - if (rv < 0) { - qdma_log_error("%s: register missing in list, err:%d\n", - __func__, - -QDMA_ERR_INV_PARAM); - return rv; - } - - for (j = 0; j < reg_info[reg_data_entry].repeat; j++) { - rv = QDMA_SNPRINTF_S(name, DEBGFS_GEN_NAME_SZ, - DEBGFS_GEN_NAME_SZ, - "%s_%d", - reg_info[reg_data_entry].name, j); - if ((rv < 0) || (rv > DEBGFS_GEN_NAME_SZ)) { - qdma_log_error( - "%d:%s snprintf failed, err:%d\n", - __LINE__, __func__, - rv); - return -QDMA_ERR_NO_MEM; - } - rv = dump_reg(buf + len, buflen - len, - (reg_info[reg_data_entry].addr + (j * 4)), - name, - reg_list[reg_count + j].reg_val); - if (rv < 0) { - qdma_log_error( - "%s Buff too small, err:%d\n", - __func__, - -QDMA_ERR_NO_MEM); - return -QDMA_ERR_NO_MEM; - } - len += rv; - } - reg_count += j; - } - - return len; - -} - - -/*****************************************************************************/ -/** - * qdma_read_reg_list() - read the register values - * - * @dev_hndl: device handle - * @is_vf: Whether PF or VF - * @total_regs : Max registers to read - * @reg_list : array of reg addr and reg values - * - * Return: returns the platform specific error code - *****************************************************************************/ -int eqdma_read_reg_list(void *dev_hndl, uint8_t is_vf, - uint16_t reg_rd_group, - uint16_t *total_regs, - struct qdma_reg_data *reg_list) -{ - uint16_t reg_count = 0, i = 0, j = 0; - struct xreg_info *reg_info; - uint32_t num_regs = eqdma_config_num_regs_get(); - struct xreg_info *eqdma_config_regs = eqdma_config_regs_get(); - struct qdma_dev_attributes dev_cap; - uint32_t reg_start_addr = 0; - int reg_index = 0; - int rv = 0; - - if (!is_vf) { - qdma_log_error("%s: not supported for PF, err:%d\n", - __func__, - -QDMA_ERR_HWACC_FEATURE_NOT_SUPPORTED); - return -QDMA_ERR_HWACC_FEATURE_NOT_SUPPORTED; - } - - if (!dev_hndl) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - if (!reg_list) { - qdma_log_error("%s: reg_list is NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - eqdma_get_device_attributes(dev_hndl, &dev_cap); - - switch (reg_rd_group) { - case QDMA_REG_READ_GROUP_1: - reg_start_addr = EQDMA_REG_GROUP_1_START_ADDR; - break; - case QDMA_REG_READ_GROUP_2: - reg_start_addr = EQDMA_REG_GROUP_2_START_ADDR; - break; - case QDMA_REG_READ_GROUP_3: - reg_start_addr = EQDMA_REG_GROUP_3_START_ADDR; - break; - case QDMA_REG_READ_GROUP_4: - reg_start_addr = EQDMA_REG_GROUP_4_START_ADDR; - break; - default: - qdma_log_error("%s: Invalid slot received\n", - __func__); - return -QDMA_ERR_INV_PARAM; - } - - rv = get_reg_entry(reg_start_addr, ®_index); - if (rv < 0) { - qdma_log_error("%s: register missing in list, err:%d\n", - __func__, - -QDMA_ERR_INV_PARAM); - return rv; - } - reg_info = &eqdma_config_regs[reg_index]; - - for (i = 0, reg_count = 0; - ((i < num_regs - 1 - reg_index) && - (reg_count < QDMA_MAX_REGISTER_DUMP)); i++) { - - if (((GET_CAPABILITY_MASK(dev_cap.mm_en, dev_cap.st_en, - dev_cap.mm_cmpt_en, dev_cap.mailbox_en) - & reg_info[i].mode) == 0) || - (reg_info[i].read_type == QDMA_REG_READ_PF_ONLY)) - continue; - - /* If Debug Mode not enabled and the current register - * is debug register, skip reading it. - */ - if (dev_cap.debug_mode == 0 && - reg_info[i].is_debug_reg == 1) - continue; - - for (j = 0; j < reg_info[i].repeat && - (reg_count < QDMA_MAX_REGISTER_DUMP); - j++) { - reg_list[reg_count].reg_addr = - (reg_info[i].addr + (j * 4)); - reg_list[reg_count].reg_val = - qdma_reg_read(dev_hndl, - reg_list[reg_count].reg_addr); - reg_count++; - } - } - - *total_regs = reg_count; - return rv; -} - -/*****************************************************************************/ -/** - * eqdma_write_global_ring_sizes() - function to set the global ring size array - * - * @dev_hndl: device handle - * @index: Index from where the values needs to written - * @count: number of entries to be written - * @glbl_rng_sz: pointer to the array having the values to write - * - * (index + count) shall not be more than 16 - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -static int eqdma_write_global_ring_sizes(void *dev_hndl, uint8_t index, - uint8_t count, const uint32_t *glbl_rng_sz) -{ - if (!dev_hndl || !glbl_rng_sz || !count) { - qdma_log_error("%s: dev_hndl=%p glbl_rng_sz=%p, err:%d\n", - __func__, dev_hndl, glbl_rng_sz, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - if ((index + count) > QDMA_NUM_RING_SIZES) { - qdma_log_error("%s: index=%u count=%u > %d, err:%d\n", - __func__, index, count, - QDMA_NUM_RING_SIZES, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - qdma_write_csr_values(dev_hndl, EQDMA_GLBL_RNG_SZ_1_ADDR, index, count, - glbl_rng_sz); - - return QDMA_SUCCESS; -} - -/*****************************************************************************/ -/** - * eqdma_read_global_ring_sizes() - function to get the global rng_sz array - * - * @dev_hndl: device handle - * @index: Index from where the values needs to read - * @count: number of entries to be read - * @glbl_rng_sz: pointer to array to hold the values read - * - * (index + count) shall not be more than 16 - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -static int eqdma_read_global_ring_sizes(void *dev_hndl, uint8_t index, - uint8_t count, uint32_t *glbl_rng_sz) -{ - if (!dev_hndl || !glbl_rng_sz || !count) { - qdma_log_error("%s: dev_hndl=%p glbl_rng_sz=%p, err:%d\n", - __func__, dev_hndl, glbl_rng_sz, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - if ((index + count) > QDMA_NUM_RING_SIZES) { - qdma_log_error("%s: index=%u count=%u > %d, err:%d\n", - __func__, index, count, - QDMA_NUM_C2H_BUFFER_SIZES, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - qdma_read_csr_values(dev_hndl, EQDMA_GLBL_RNG_SZ_1_ADDR, index, count, - glbl_rng_sz); - - return QDMA_SUCCESS; -} - -/*****************************************************************************/ -/** - * eqdma_write_global_timer_count() - function to set the timer values - * - * @dev_hndl: device handle - * @glbl_tmr_cnt: pointer to the array having the values to write - * @index: Index from where the values needs to written - * @count: number of entries to be written - * - * (index + count) shall not be more than 16 - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -static int eqdma_write_global_timer_count(void *dev_hndl, uint8_t index, - uint8_t count, const uint32_t *glbl_tmr_cnt) -{ - struct qdma_dev_attributes dev_cap; - - if (!dev_hndl || !glbl_tmr_cnt || !count) { - qdma_log_error("%s: dev_hndl=%p glbl_tmr_cnt=%p, err:%d\n", - __func__, dev_hndl, glbl_tmr_cnt, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - if ((index + count) > QDMA_NUM_C2H_TIMERS) { - qdma_log_error("%s: index=%u count=%u > %d, err:%d\n", - __func__, index, count, - QDMA_NUM_C2H_TIMERS, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - eqdma_get_device_attributes(dev_hndl, &dev_cap); - - if (dev_cap.st_en || dev_cap.mm_cmpt_en) - qdma_write_csr_values(dev_hndl, EQDMA_C2H_TIMER_CNT_ADDR, - index, count, glbl_tmr_cnt); - else { - qdma_log_error("%s: ST or MM cmpt not supported, err:%d\n", - __func__, - -QDMA_ERR_HWACC_FEATURE_NOT_SUPPORTED); - return -QDMA_ERR_HWACC_FEATURE_NOT_SUPPORTED; - } - - return QDMA_SUCCESS; -} - -/*****************************************************************************/ -/** - * eqdma_read_global_timer_count() - function to get the timer values - * - * @dev_hndl: device handle - * @index: Index from where the values needs to read - * @count: number of entries to be read - * @glbl_tmr_cnt: pointer to array to hold the values read - * - * (index + count) shall not be more than 16 - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -static int eqdma_read_global_timer_count(void *dev_hndl, uint8_t index, - uint8_t count, uint32_t *glbl_tmr_cnt) -{ - struct qdma_dev_attributes dev_cap; - - if (!dev_hndl || !glbl_tmr_cnt || !count) { - qdma_log_error("%s: dev_hndl=%p glbl_tmr_cnt=%p, err:%d\n", - __func__, dev_hndl, glbl_tmr_cnt, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - if ((index + count) > QDMA_NUM_C2H_TIMERS) { - qdma_log_error("%s: index=%u count=%u > %d, err:%d\n", - __func__, index, count, - QDMA_NUM_C2H_TIMERS, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - eqdma_get_device_attributes(dev_hndl, &dev_cap); - - if (dev_cap.st_en || dev_cap.mm_cmpt_en) - qdma_read_csr_values(dev_hndl, - EQDMA_C2H_TIMER_CNT_ADDR, index, - count, glbl_tmr_cnt); - else { - qdma_log_error("%s: ST or MM cmpt not supported, err:%d\n", - __func__, - -QDMA_ERR_HWACC_FEATURE_NOT_SUPPORTED); - return -QDMA_ERR_HWACC_FEATURE_NOT_SUPPORTED; - } - - return QDMA_SUCCESS; -} - -/*****************************************************************************/ -/** - * eqdma_write_global_counter_threshold() - function to set the counter - * threshold values - * - * @dev_hndl: device handle - * @index: Index from where the values needs to written - * @count: number of entries to be written - * @glbl_cnt_th: pointer to the array having the values to write - * - * (index + count) shall not be more than 16 - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -static int eqdma_write_global_counter_threshold(void *dev_hndl, uint8_t index, - uint8_t count, const uint32_t *glbl_cnt_th) -{ - struct qdma_dev_attributes dev_cap; - - if (!dev_hndl || !glbl_cnt_th || !count) { - qdma_log_error("%s: dev_hndl=%p glbl_cnt_th=%p, err:%d\n", - __func__, dev_hndl, glbl_cnt_th, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - if ((index + count) > QDMA_NUM_C2H_COUNTERS) { - qdma_log_error("%s: index=%u count=%u > %d, err:%d\n", - __func__, index, count, - QDMA_NUM_C2H_BUFFER_SIZES, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - eqdma_get_device_attributes(dev_hndl, &dev_cap); - - if (dev_cap.st_en || dev_cap.mm_cmpt_en) - qdma_write_csr_values(dev_hndl, EQDMA_C2H_CNT_TH_ADDR, index, - count, glbl_cnt_th); - else { - qdma_log_error("%s: ST or MM cmpt not supported, err:%d\n", - __func__, - -QDMA_ERR_HWACC_FEATURE_NOT_SUPPORTED); - return -QDMA_ERR_HWACC_FEATURE_NOT_SUPPORTED; - } - - return QDMA_SUCCESS; -} - -/*****************************************************************************/ -/** - * eqdma_read_global_counter_threshold() - function to get the counter threshold - * values - * - * @dev_hndl: device handle - * @index: Index from where the values needs to read - * @count: number of entries to be read - * @glbl_cnt_th: pointer to array to hold the values read - * - * (index + count) shall not be more than 16 - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -static int eqdma_read_global_counter_threshold(void *dev_hndl, uint8_t index, - uint8_t count, uint32_t *glbl_cnt_th) -{ - struct qdma_dev_attributes dev_cap; - - if (!dev_hndl || !glbl_cnt_th || !count) { - qdma_log_error("%s: dev_hndl=%p glbl_cnt_th=%p, err:%d\n", - __func__, dev_hndl, glbl_cnt_th, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - if ((index + count) > QDMA_NUM_C2H_COUNTERS) { - qdma_log_error("%s: index=%u count=%u > %d, err:%d\n", - __func__, index, count, - QDMA_NUM_C2H_COUNTERS, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - eqdma_get_device_attributes(dev_hndl, &dev_cap); - - if (dev_cap.st_en || dev_cap.mm_cmpt_en) - qdma_read_csr_values(dev_hndl, EQDMA_C2H_CNT_TH_ADDR, index, - count, glbl_cnt_th); - else { - qdma_log_error("%s: ST or MM cmpt not supported, err:%d\n", - __func__, -QDMA_ERR_HWACC_FEATURE_NOT_SUPPORTED); - return -QDMA_ERR_HWACC_FEATURE_NOT_SUPPORTED; - } - - return QDMA_SUCCESS; -} - -/*****************************************************************************/ -/** - * eqdma_write_global_buffer_sizes() - function to set the buffer sizes - * - * @dev_hndl: device handle - * @index: Index from where the values needs to written - * @count: number of entries to be written - * @glbl_buf_sz: pointer to the array having the values to write - * - * (index + count) shall not be more than 16 - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -static int eqdma_write_global_buffer_sizes(void *dev_hndl, uint8_t index, - uint8_t count, const uint32_t *glbl_buf_sz) -{ - struct qdma_dev_attributes dev_cap; - - if (!dev_hndl || !glbl_buf_sz || !count) { - qdma_log_error("%s: dev_hndl=%p glbl_buf_sz=%p, err:%d\n", - __func__, dev_hndl, glbl_buf_sz, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - if ((index + count) > QDMA_NUM_C2H_BUFFER_SIZES) { - qdma_log_error("%s: index=%u count=%u > %d, err:%d\n", - __func__, index, count, - QDMA_NUM_C2H_BUFFER_SIZES, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - eqdma_get_device_attributes(dev_hndl, &dev_cap); - - if (dev_cap.st_en) - qdma_write_csr_values(dev_hndl, EQDMA_C2H_BUF_SZ_ADDR, index, - count, glbl_buf_sz); - else { - qdma_log_error("%s: ST not supported, err:%d\n", - __func__, - -QDMA_ERR_HWACC_FEATURE_NOT_SUPPORTED); - return -QDMA_ERR_HWACC_FEATURE_NOT_SUPPORTED; - } - - return QDMA_SUCCESS; -} - -/*****************************************************************************/ -/** - * eqdma_read_global_buffer_sizes() - function to get the buffer sizes - * - * @dev_hndl: device handle - * @index: Index from where the values needs to read - * @count: number of entries to be read - * @glbl_buf_sz: pointer to array to hold the values read - * - * (index + count) shall not be more than 16 - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -static int eqdma_read_global_buffer_sizes(void *dev_hndl, uint8_t index, - uint8_t count, uint32_t *glbl_buf_sz) -{ - struct qdma_dev_attributes dev_cap; - - if (!dev_hndl || !glbl_buf_sz || !count) { - qdma_log_error("%s: dev_hndl=%p glbl_buf_sz=%p, err:%d\n", - __func__, dev_hndl, glbl_buf_sz, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - if ((index + count) > QDMA_NUM_C2H_BUFFER_SIZES) { - qdma_log_error("%s: index=%u count=%u > %d, err:%d\n", - __func__, index, count, - QDMA_NUM_C2H_BUFFER_SIZES, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - eqdma_get_device_attributes(dev_hndl, &dev_cap); - - if (dev_cap.st_en) - qdma_read_csr_values(dev_hndl, EQDMA_C2H_BUF_SZ_ADDR, index, - count, glbl_buf_sz); - else { - qdma_log_error("%s: ST is not supported, err:%d\n", - __func__, - -QDMA_ERR_HWACC_FEATURE_NOT_SUPPORTED); - return -QDMA_ERR_HWACC_FEATURE_NOT_SUPPORTED; - } - - return QDMA_SUCCESS; -} - -/*****************************************************************************/ -/** - * eqdma_global_csr_conf() - function to configure global csr - * - * @dev_hndl: device handle - * @index: Index from where the values needs to read - * @count: number of entries to be read - * @csr_val: uint32_t pointer to csr value - * @csr_type: Type of the CSR (qdma_global_csr_type enum) to configure - * @access_type HW access type (qdma_hw_access_type enum) value - * QDMA_HW_ACCESS_CLEAR - Not supported - * QDMA_HW_ACCESS_INVALIDATE - Not supported - * - * (index + count) shall not be more than 16 - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -int eqdma_global_csr_conf(void *dev_hndl, uint8_t index, uint8_t count, - uint32_t *csr_val, - enum qdma_global_csr_type csr_type, - enum qdma_hw_access_type access_type) -{ - int rv = QDMA_SUCCESS; - - switch (csr_type) { - case QDMA_CSR_RING_SZ: - switch (access_type) { - case QDMA_HW_ACCESS_READ: - rv = eqdma_read_global_ring_sizes( - dev_hndl, - index, - count, - csr_val); - break; - case QDMA_HW_ACCESS_WRITE: - rv = eqdma_write_global_ring_sizes( - dev_hndl, - index, - count, - csr_val); - break; - default: - qdma_log_error("%s: access_type(%d) invalid, err:%d\n", - __func__, - access_type, - -QDMA_ERR_INV_PARAM); - rv = -QDMA_ERR_INV_PARAM; - break; - } - break; - case QDMA_CSR_TIMER_CNT: - switch (access_type) { - case QDMA_HW_ACCESS_READ: - rv = eqdma_read_global_timer_count( - dev_hndl, - index, - count, - csr_val); - break; - case QDMA_HW_ACCESS_WRITE: - rv = eqdma_write_global_timer_count( - dev_hndl, - index, - count, - csr_val); - break; - default: - qdma_log_error("%s: access_type(%d) invalid, err:%d\n", - __func__, - access_type, - -QDMA_ERR_INV_PARAM); - rv = -QDMA_ERR_INV_PARAM; - break; - } - break; - case QDMA_CSR_CNT_TH: - switch (access_type) { - case QDMA_HW_ACCESS_READ: - rv = - eqdma_read_global_counter_threshold( - dev_hndl, - index, - count, - csr_val); - break; - case QDMA_HW_ACCESS_WRITE: - rv = - eqdma_write_global_counter_threshold( - dev_hndl, - index, - count, - csr_val); - break; - default: - qdma_log_error("%s: access_type(%d) invalid, err:%d\n", - __func__, - access_type, - -QDMA_ERR_INV_PARAM); - rv = -QDMA_ERR_INV_PARAM; - break; - } - break; - case QDMA_CSR_BUF_SZ: - switch (access_type) { - case QDMA_HW_ACCESS_READ: - rv = - eqdma_read_global_buffer_sizes(dev_hndl, - index, - count, - csr_val); - break; - case QDMA_HW_ACCESS_WRITE: - rv = - eqdma_write_global_buffer_sizes(dev_hndl, - index, - count, - csr_val); - break; - default: - qdma_log_error("%s: access_type(%d) invalid, err:%d\n", - __func__, - access_type, - -QDMA_ERR_INV_PARAM); - rv = -QDMA_ERR_INV_PARAM; - break; - } - break; - default: - qdma_log_error("%s: csr_type(%d) invalid, err:%d\n", - __func__, - csr_type, - -QDMA_ERR_INV_PARAM); - rv = -QDMA_ERR_INV_PARAM; - break; - } - - return rv; -} - -/*****************************************************************************/ -/** - * eqdma_global_writeback_interval_write() - function to set the writeback - * interval - * - * @dev_hndl device handle - * @wb_int: Writeback Interval - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -static int eqdma_global_writeback_interval_write(void *dev_hndl, - enum qdma_wrb_interval wb_int) -{ - uint32_t reg_val; - struct qdma_dev_attributes dev_cap; - - if (!dev_hndl) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", __func__, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - if (wb_int >= QDMA_NUM_WRB_INTERVALS) { - qdma_log_error("%s: wb_int=%d is invalid, err:%d\n", - __func__, wb_int, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - eqdma_get_device_attributes(dev_hndl, &dev_cap); - - if (dev_cap.st_en || dev_cap.mm_cmpt_en) { - reg_val = qdma_reg_read(dev_hndl, EQDMA_GLBL_DSC_CFG_ADDR); - reg_val |= FIELD_SET(GLBL_DSC_CFG_WB_ACC_INT_MASK, wb_int); - qdma_reg_write(dev_hndl, EQDMA_GLBL_DSC_CFG_ADDR, reg_val); - } else { - qdma_log_error("%s: ST or MM cmpt not supported, err:%d\n", - __func__, -QDMA_ERR_HWACC_FEATURE_NOT_SUPPORTED); - return -QDMA_ERR_HWACC_FEATURE_NOT_SUPPORTED; - } - - return QDMA_SUCCESS; -} - -/*****************************************************************************/ -/** - * eqdma_global_writeback_interval_read() - function to get the writeback - * interval - * - * @dev_hndl: device handle - * @wb_int: pointer to the data to hold Writeback Interval - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -static int eqdma_global_writeback_interval_read(void *dev_hndl, - enum qdma_wrb_interval *wb_int) -{ - uint32_t reg_val; - struct qdma_dev_attributes dev_cap; - - if (!dev_hndl) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", __func__, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - if (!wb_int) { - qdma_log_error("%s: wb_int is NULL, err:%d\n", __func__, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - eqdma_get_device_attributes(dev_hndl, &dev_cap); - - if (dev_cap.st_en || dev_cap.mm_cmpt_en) { - reg_val = qdma_reg_read(dev_hndl, EQDMA_GLBL_DSC_CFG_ADDR); - *wb_int = (enum qdma_wrb_interval)FIELD_GET( - GLBL_DSC_CFG_WB_ACC_INT_MASK, reg_val); - } else { - qdma_log_error("%s: ST or MM cmpt not supported, err:%d\n", - __func__, -QDMA_ERR_HWACC_FEATURE_NOT_SUPPORTED); - return -QDMA_ERR_HWACC_FEATURE_NOT_SUPPORTED; - } - - return QDMA_SUCCESS; -} - -/*****************************************************************************/ -/** - * eqdma_global_writeback_interval_conf() - function to configure - * the writeback interval - * - * @dev_hndl: device handle - * @wb_int: pointer to the data to hold Writeback Interval - * @access_type HW access type (qdma_hw_access_type enum) value - * QDMA_HW_ACCESS_CLEAR - Not supported - * QDMA_HW_ACCESS_INVALIDATE - Not supported - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -int eqdma_global_writeback_interval_conf(void *dev_hndl, - enum qdma_wrb_interval *wb_int, - enum qdma_hw_access_type access_type) -{ - int rv = QDMA_SUCCESS; - - switch (access_type) { - case QDMA_HW_ACCESS_READ: - rv = eqdma_global_writeback_interval_read(dev_hndl, wb_int); - break; - case QDMA_HW_ACCESS_WRITE: - rv = eqdma_global_writeback_interval_write(dev_hndl, *wb_int); - break; - case QDMA_HW_ACCESS_CLEAR: - case QDMA_HW_ACCESS_INVALIDATE: - default: - qdma_log_error("%s: access_type(%d) invalid, err:%d\n", - __func__, - access_type, - -QDMA_ERR_INV_PARAM); - rv = -QDMA_ERR_INV_PARAM; - break; - } - - return rv; -} - - -/*****************************************************************************/ -/** - * eqdma_mm_channel_conf() - Function to enable/disable the MM channel - * - * @dev_hndl: device handle - * @channel: MM channel number - * @is_c2h: Queue direction. Set 1 for C2H and 0 for H2C - * @enable: Enable or disable MM channel - * - * Presently, we have only 1 MM channel - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -int eqdma_mm_channel_conf(void *dev_hndl, uint8_t channel, uint8_t is_c2h, - uint8_t enable) -{ - uint32_t reg_addr = (is_c2h) ? EQDMA_C2H_MM_CTL_ADDR : - EQDMA_H2C_MM_CTL_ADDR; - struct qdma_dev_attributes dev_cap; - - if (!dev_hndl) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - eqdma_get_device_attributes(dev_hndl, &dev_cap); - - if (dev_cap.mm_en) - qdma_reg_write(dev_hndl, - reg_addr + (channel * QDMA_MM_CONTROL_STEP), - enable); - - - return QDMA_SUCCESS; -} - -int eqdma_dump_reg_info(void *dev_hndl, uint32_t reg_addr, - uint32_t num_regs, char *buf, uint32_t buflen) -{ - uint32_t total_num_regs = eqdma_config_num_regs_get(); - struct xreg_info *config_regs = eqdma_config_regs_get(); - struct qdma_dev_attributes dev_cap; - const char *bitfield_name; - uint32_t i = 0, num_regs_idx = 0, k = 0, j = 0, - bitfield = 0, lsb = 0, msb = 31; - int rv = 0; - uint32_t reg_val; - uint32_t data_len = 0; - - if (!dev_hndl) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - eqdma_get_device_attributes(dev_hndl, &dev_cap); - - for (i = 0; i < total_num_regs; i++) { - if (reg_addr == config_regs[i].addr) { - j = i; - break; - } - } - - if (i == total_num_regs) { - qdma_log_error("%s: Register not found err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - if (buf) - QDMA_SNPRINTF_S(buf, buflen, - DEBGFS_LINE_SZ, - "Register not found 0x%x\n", reg_addr); - - return -QDMA_ERR_INV_PARAM; - } - - num_regs_idx = (j + num_regs < total_num_regs) ? - (j + num_regs) : total_num_regs; - - for (; j < num_regs_idx ; j++) { - reg_val = qdma_reg_read(dev_hndl, - config_regs[j].addr); - - if (buf) { - rv = QDMA_SNPRINTF_S(buf, buflen, - DEBGFS_LINE_SZ, - "\n%-40s 0x%-7x %-#10x %-10d\n", - config_regs[j].name, - config_regs[j].addr, - reg_val, reg_val); - if ((rv < 0) || (rv > DEBGFS_LINE_SZ)) { - qdma_log_error( - "%s: Insufficient buffer, err:%d\n", - __func__, -QDMA_ERR_NO_MEM); - return -QDMA_ERR_NO_MEM; - } - buf += rv; - data_len += rv; - buflen -= rv; - } else - qdma_log_info("%-40s 0x%-7x %-#10x %-10d\n", - config_regs[j].name, - config_regs[j].addr, - reg_val, reg_val); - - - for (k = 0; - k < config_regs[j].num_bitfields; k++) { - /* If Debug Mode not enabled and the current register - * is debug register, skip reading it. - */ - if (dev_cap.debug_mode == 0 && - config_regs[j].is_debug_reg == 1) - continue; - - bitfield = - config_regs[j].bitfields[k].field_mask; - bitfield_name = - config_regs[i].bitfields[k].field_name; - lsb = 0; - msb = 31; - - while (!(BIT(lsb) & bitfield)) - lsb++; - - while (!(BIT(msb) & bitfield)) - msb--; - - if (msb != lsb) { - if (buf) { - rv = QDMA_SNPRINTF_S(buf, buflen, - DEBGFS_LINE_SZ, - "%-40s [%2u,%2u] %#-10x\n", - bitfield_name, - msb, lsb, - (reg_val & bitfield) >> - lsb); - if ((rv < 0) || (rv > DEBGFS_LINE_SZ)) { - qdma_log_error( - "%s: Insufficient buffer, err:%d\n", - __func__, - -QDMA_ERR_NO_MEM); - return -QDMA_ERR_NO_MEM; - } - buf += rv; - data_len += rv; - buflen -= rv; - } else - qdma_log_info( - "%-40s [%2u,%2u] %#-10x\n", - bitfield_name, - msb, lsb, - (reg_val & bitfield) >> lsb); - - - } else { - if (buf) { - rv = QDMA_SNPRINTF_S(buf, buflen, - DEBGFS_LINE_SZ, - "%-40s [%5u] %#-10x\n", - bitfield_name, - lsb, - (reg_val & bitfield) >> - lsb); - if ((rv < 0) || (rv > DEBGFS_LINE_SZ)) { - qdma_log_error( - "%s: Insufficient buffer, err:%d\n", - __func__, - -QDMA_ERR_NO_MEM); - return -QDMA_ERR_NO_MEM; - } - buf += rv; - data_len += rv; - buflen -= rv; - } else - qdma_log_info( - "%-40s [%5u] %#-10x\n", - bitfield_name, - lsb, - (reg_val & bitfield) >> lsb); - - } - } - } - - return data_len; -} diff --git a/QDMA/DPDK/drivers/net/qdma/qdma_access/eqdma_soft_access/eqdma_soft_access.h b/QDMA/DPDK/drivers/net/qdma/qdma_access/eqdma_soft_access/eqdma_soft_access.h deleted file mode 100755 index b2df4fe19..000000000 --- a/QDMA/DPDK/drivers/net/qdma/qdma_access/eqdma_soft_access/eqdma_soft_access.h +++ /dev/null @@ -1,361 +0,0 @@ -/* - * Copyright (c) 2019-2022, Xilinx, Inc. All rights reserved. - * Copyright (c) 2022, Advanced Micro Devices, Inc. All rights reserved. - * - * BSD LICENSE - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * * Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#ifndef __EQDMA_SOFT_ACCESS_H_ -#define __EQDMA_SOFT_ACCESS_H_ - -#ifdef __cplusplus -extern "C" { -#endif - -#include "qdma_platform.h" - -/** - * enum qdma_error_idx - qdma errors - */ -enum eqdma_error_idx { - /* Descriptor errors */ - EQDMA_DSC_ERR_POISON, - EQDMA_DSC_ERR_UR_CA, - EQDMA_DSC_ERR_BCNT, - EQDMA_DSC_ERR_PARAM, - EQDMA_DSC_ERR_ADDR, - EQDMA_DSC_ERR_TAG, - EQDMA_DSC_ERR_FLR, - EQDMA_DSC_ERR_TIMEOUT, - EQDMA_DSC_ERR_DAT_POISON, - EQDMA_DSC_ERR_FLR_CANCEL, - EQDMA_DSC_ERR_DMA, - EQDMA_DSC_ERR_DSC, - EQDMA_DSC_ERR_RQ_CANCEL, - EQDMA_DSC_ERR_DBE, - EQDMA_DSC_ERR_SBE, - EQDMA_DSC_ERR_PORT_ID, - EQDMA_DSC_ERR_ALL, - - /* TRQ Errors */ - EQDMA_TRQ_ERR_CSR_UNMAPPED, - EQDMA_TRQ_ERR_VF_ACCESS, - EQDMA_TRQ_ERR_TCP_CSR_TIMEOUT, - EQDMA_TRQ_ERR_QSPC_UNMAPPED, - EQDMA_TRQ_ERR_QID_RANGE, - EQDMA_TRQ_ERR_TCP_QSPC_TIMEOUT, - EQDMA_TRQ_ERR_ALL, - - /* C2H Errors */ - EQDMA_ST_C2H_ERR_MTY_MISMATCH, - EQDMA_ST_C2H_ERR_LEN_MISMATCH, - EQDMA_ST_C2H_ERR_SH_CMPT_DSC, - EQDMA_ST_C2H_ERR_QID_MISMATCH, - EQDMA_ST_C2H_ERR_DESC_RSP_ERR, - EQDMA_ST_C2H_ERR_ENG_WPL_DATA_PAR_ERR, - EQDMA_ST_C2H_ERR_MSI_INT_FAIL, - EQDMA_ST_C2H_ERR_ERR_DESC_CNT, - EQDMA_ST_C2H_ERR_PORTID_CTXT_MISMATCH, - EQDMA_ST_C2H_ERR_CMPT_INV_Q_ERR, - EQDMA_ST_C2H_ERR_CMPT_QFULL_ERR, - EQDMA_ST_C2H_ERR_CMPT_CIDX_ERR, - EQDMA_ST_C2H_ERR_CMPT_PRTY_ERR, - EQDMA_ST_C2H_ERR_AVL_RING_DSC, - EQDMA_ST_C2H_ERR_HDR_ECC_UNC, - EQDMA_ST_C2H_ERR_HDR_ECC_COR, - EQDMA_ST_C2H_ERR_WRB_PORT_ID_ERR, - EQDMA_ST_C2H_ERR_ALL, - - /* Fatal Errors */ - EQDMA_ST_FATAL_ERR_MTY_MISMATCH, - EQDMA_ST_FATAL_ERR_LEN_MISMATCH, - EQDMA_ST_FATAL_ERR_QID_MISMATCH, - EQDMA_ST_FATAL_ERR_TIMER_FIFO_RAM_RDBE, - EQDMA_ST_FATAL_ERR_PFCH_II_RAM_RDBE, - EQDMA_ST_FATAL_ERR_CMPT_CTXT_RAM_RDBE, - EQDMA_ST_FATAL_ERR_PFCH_CTXT_RAM_RDBE, - EQDMA_ST_FATAL_ERR_DESC_REQ_FIFO_RAM_RDBE, - EQDMA_ST_FATAL_ERR_INT_CTXT_RAM_RDBE, - EQDMA_ST_FATAL_ERR_CMPT_COAL_DATA_RAM_RDBE, - EQDMA_ST_FATAL_ERR_CMPT_FIFO_RAM_RDBE, - EQDMA_ST_FATAL_ERR_QID_FIFO_RAM_RDBE, - EQDMA_ST_FATAL_ERR_PAYLOAD_FIFO_RAM_RDBE, - EQDMA_ST_FATAL_ERR_WPL_DATA_PAR, - EQDMA_ST_FATAL_ERR_AVL_RING_FIFO_RAM_RDBE, - EQDMA_ST_FATAL_ERR_HDR_ECC_UNC, - EQDMA_ST_FATAL_ERR_ALL, - - /* H2C Errors */ - EQDMA_ST_H2C_ERR_ZERO_LEN_DESC, - EQDMA_ST_H2C_ERR_SDI_MRKR_REQ_MOP, - EQDMA_ST_H2C_ERR_NO_DMA_DSC, - EQDMA_ST_H2C_ERR_SBE, - EQDMA_ST_H2C_ERR_DBE, - EQDMA_ST_H2C_ERR_PAR, - EQDMA_ST_H2C_ERR_ALL, - - /* Single bit errors */ - EQDMA_SBE_1_ERR_RC_RRQ_EVEN_RAM, - EQDMA_SBE_1_ERR_TAG_ODD_RAM, - EQDMA_SBE_1_ERR_TAG_EVEN_RAM, - EQDMA_SBE_1_ERR_PFCH_CTXT_CAM_RAM_0, - EQDMA_SBE_1_ERR_PFCH_CTXT_CAM_RAM_1, - EQDMA_SBE_1_ERR_ALL, - - /* Single bit errors */ - EQDMA_SBE_ERR_MI_H2C0_DAT, - EQDMA_SBE_ERR_MI_H2C1_DAT, - EQDMA_SBE_ERR_MI_H2C2_DAT, - EQDMA_SBE_ERR_MI_H2C3_DAT, - EQDMA_SBE_ERR_MI_C2H0_DAT, - EQDMA_SBE_ERR_MI_C2H1_DAT, - EQDMA_SBE_ERR_MI_C2H2_DAT, - EQDMA_SBE_ERR_MI_C2H3_DAT, - EQDMA_SBE_ERR_H2C_RD_BRG_DAT, - EQDMA_SBE_ERR_H2C_WR_BRG_DAT, - EQDMA_SBE_ERR_C2H_RD_BRG_DAT, - EQDMA_SBE_ERR_C2H_WR_BRG_DAT, - EQDMA_SBE_ERR_FUNC_MAP, - EQDMA_SBE_ERR_DSC_HW_CTXT, - EQDMA_SBE_ERR_DSC_CRD_RCV, - EQDMA_SBE_ERR_DSC_SW_CTXT, - EQDMA_SBE_ERR_DSC_CPLI, - EQDMA_SBE_ERR_DSC_CPLD, - EQDMA_SBE_ERR_MI_TL_SLV_FIFO_RAM, - EQDMA_SBE_ERR_TIMER_FIFO_RAM, - EQDMA_SBE_ERR_QID_FIFO_RAM, - EQDMA_SBE_ERR_WRB_COAL_DATA_RAM, - EQDMA_SBE_ERR_INT_CTXT_RAM, - EQDMA_SBE_ERR_DESC_REQ_FIFO_RAM, - EQDMA_SBE_ERR_PFCH_CTXT_RAM, - EQDMA_SBE_ERR_WRB_CTXT_RAM, - EQDMA_SBE_ERR_PFCH_LL_RAM, - EQDMA_SBE_ERR_PEND_FIFO_RAM, - EQDMA_SBE_ERR_RC_RRQ_ODD_RAM, - EQDMA_SBE_ERR_ALL, - - /* Double bit Errors */ - EQDMA_DBE_1_ERR_RC_RRQ_EVEN_RAM, - EQDMA_DBE_1_ERR_TAG_ODD_RAM, - EQDMA_DBE_1_ERR_TAG_EVEN_RAM, - EQDMA_DBE_1_ERR_PFCH_CTXT_CAM_RAM_0, - EQDMA_DBE_1_ERR_PFCH_CTXT_CAM_RAM_1, - EQDMA_DBE_1_ERR_ALL, - - /* Double bit Errors */ - EQDMA_DBE_ERR_MI_H2C0_DAT, - EQDMA_DBE_ERR_MI_H2C1_DAT, - EQDMA_DBE_ERR_MI_H2C2_DAT, - EQDMA_DBE_ERR_MI_H2C3_DAT, - EQDMA_DBE_ERR_MI_C2H0_DAT, - EQDMA_DBE_ERR_MI_C2H1_DAT, - EQDMA_DBE_ERR_MI_C2H2_DAT, - EQDMA_DBE_ERR_MI_C2H3_DAT, - EQDMA_DBE_ERR_H2C_RD_BRG_DAT, - EQDMA_DBE_ERR_H2C_WR_BRG_DAT, - EQDMA_DBE_ERR_C2H_RD_BRG_DAT, - EQDMA_DBE_ERR_C2H_WR_BRG_DAT, - EQDMA_DBE_ERR_FUNC_MAP, - EQDMA_DBE_ERR_DSC_HW_CTXT, - EQDMA_DBE_ERR_DSC_CRD_RCV, - EQDMA_DBE_ERR_DSC_SW_CTXT, - EQDMA_DBE_ERR_DSC_CPLI, - EQDMA_DBE_ERR_DSC_CPLD, - EQDMA_DBE_ERR_MI_TL_SLV_FIFO_RAM, - EQDMA_DBE_ERR_TIMER_FIFO_RAM, - EQDMA_DBE_ERR_QID_FIFO_RAM, - EQDMA_DBE_ERR_WRB_COAL_DATA_RAM, - EQDMA_DBE_ERR_INT_CTXT_RAM, - EQDMA_DBE_ERR_DESC_REQ_FIFO_RAM, - EQDMA_DBE_ERR_PFCH_CTXT_RAM, - EQDMA_DBE_ERR_WRB_CTXT_RAM, - EQDMA_DBE_ERR_PFCH_LL_RAM, - EQDMA_DBE_ERR_PEND_FIFO_RAM, - EQDMA_DBE_ERR_RC_RRQ_ODD_RAM, - EQDMA_DBE_ERR_ALL, - - /* MM C2H Errors */ - EQDMA_MM_C2H_WR_SLR_ERR, - EQDMA_MM_C2H_RD_SLR_ERR, - EQDMA_MM_C2H_WR_FLR_ERR, - EQDMA_MM_C2H_UR_ERR, - EQDMA_MM_C2H_WR_UC_RAM_ERR, - EQDMA_MM_C2H_ERR_ALL, - - /* MM H2C Engine0 Errors */ - EQDMA_MM_H2C0_RD_HDR_POISON_ERR, - EQDMA_MM_H2C0_RD_UR_CA_ERR, - EQDMA_MM_H2C0_RD_HDR_BYTE_ERR, - EQDMA_MM_H2C0_RD_HDR_PARAM_ERR, - EQDMA_MM_H2C0_RD_HDR_ADR_ERR, - EQDMA_MM_H2C0_RD_FLR_ERR, - EQDMA_MM_H2C0_RD_DAT_POISON_ERR, - EQDMA_MM_H2C0_RD_RQ_DIS_ERR, - EQDMA_MM_H2C0_WR_DEC_ERR, - EQDMA_MM_H2C0_WR_SLV_ERR, - EQDMA_MM_H2C0_ERR_ALL, - - EQDMA_ERRS_ALL -}; - -struct eqdma_hw_err_info { - enum eqdma_error_idx idx; - const char *err_name; - uint32_t mask_reg_addr; - uint32_t stat_reg_addr; - uint32_t leaf_err_mask; - uint32_t global_err_mask; - void (*eqdma_hw_err_process)(void *dev_hndl); -}; - -/* In QDMA_GLBL2_MISC_CAP(0x134) register, - * Bits [23:20] gives QDMA IP version. - * 0: QDMA3.1, 1: QDMA4.0, 2: QDMA5.0 - */ -#define EQDMA_IP_VERSION_4 1 -#define EQDMA_IP_VERSION_5 2 - -#define EQDMA_OFFSET_VF_VERSION 0x5014 -#define EQDMA_OFFSET_VF_USER_BAR 0x5018 - -#define EQDMA_OFFSET_MBOX_BASE_PF 0x22400 -#define EQDMA_OFFSET_MBOX_BASE_VF 0x5000 - -#define EQDMA_COMPL_CTXT_BADDR_HIGH_H_MASK GENMASK_ULL(63, 38) -#define EQDMA_COMPL_CTXT_BADDR_HIGH_L_MASK GENMASK_ULL(37, 6) -#define EQDMA_COMPL_CTXT_BADDR_LOW_MASK GENMASK_ULL(5, 2) - -int eqdma_init_ctxt_memory(void *dev_hndl); - -int eqdma_get_version(void *dev_hndl, uint8_t is_vf, - struct qdma_hw_version_info *version_info); - -int eqdma_get_ip_version(void *dev_hndl, uint8_t is_vf, - uint32_t *ip_version); - -int eqdma_sw_ctx_conf(void *dev_hndl, uint8_t c2h, uint16_t hw_qid, - struct qdma_descq_sw_ctxt *ctxt, - enum qdma_hw_access_type access_type); - -int eqdma_hw_ctx_conf(void *dev_hndl, uint8_t c2h, uint16_t hw_qid, - struct qdma_descq_hw_ctxt *ctxt, - enum qdma_hw_access_type access_type); - -int eqdma_credit_ctx_conf(void *dev_hndl, uint8_t c2h, - uint16_t hw_qid, struct qdma_descq_credit_ctxt *ctxt, - enum qdma_hw_access_type access_type); - -int eqdma_pfetch_ctx_conf(void *dev_hndl, uint16_t hw_qid, - struct qdma_descq_prefetch_ctxt *ctxt, - enum qdma_hw_access_type access_type); - -int eqdma_cmpt_ctx_conf(void *dev_hndl, uint16_t hw_qid, - struct qdma_descq_cmpt_ctxt *ctxt, - enum qdma_hw_access_type access_type); - -int eqdma_fmap_conf(void *dev_hndl, uint16_t func_id, - struct qdma_fmap_cfg *config, - enum qdma_hw_access_type access_type); - -int eqdma_indirect_intr_ctx_conf(void *dev_hndl, uint16_t ring_index, - struct qdma_indirect_intr_ctxt *ctxt, - enum qdma_hw_access_type access_type); - -int eqdma_dump_config_regs(void *dev_hndl, uint8_t is_vf, - char *buf, uint32_t buflen); - -int eqdma_dump_intr_context(void *dev_hndl, - struct qdma_indirect_intr_ctxt *intr_ctx, - int ring_index, - char *buf, uint32_t buflen); - -int eqdma_dump_queue_context(void *dev_hndl, - uint8_t st, - enum qdma_dev_q_type q_type, - struct qdma_descq_context *ctxt_data, - char *buf, uint32_t buflen); - -uint32_t eqdma_reg_dump_buf_len(void); - -int eqdma_context_buf_len(uint8_t st, - enum qdma_dev_q_type q_type, uint32_t *buflen); - -int eqdma_hw_error_process(void *dev_hndl); -const char *eqdma_hw_get_error_name(uint32_t err_idx); -int eqdma_hw_error_enable(void *dev_hndl, uint32_t err_idx); - -int eqdma_read_dump_queue_context(void *dev_hndl, - uint16_t func_id, - uint16_t qid_hw, - uint8_t st, - enum qdma_dev_q_type q_type, - char *buf, uint32_t buflen); - -int eqdma_get_device_attributes(void *dev_hndl, - struct qdma_dev_attributes *dev_info); - -int eqdma_get_user_bar(void *dev_hndl, uint8_t is_vf, - uint16_t func_id, uint8_t *user_bar); - -int eqdma_dump_config_reg_list(void *dev_hndl, - uint32_t total_regs, - struct qdma_reg_data *reg_list, - char *buf, uint32_t buflen); - -int eqdma_read_reg_list(void *dev_hndl, uint8_t is_vf, - uint16_t reg_rd_group, - uint16_t *total_regs, - struct qdma_reg_data *reg_list); - -int eqdma_set_default_global_csr(void *dev_hndl); - -int eqdma_global_csr_conf(void *dev_hndl, uint8_t index, uint8_t count, - uint32_t *csr_val, - enum qdma_global_csr_type csr_type, - enum qdma_hw_access_type access_type); - -int eqdma_global_writeback_interval_conf(void *dev_hndl, - enum qdma_wrb_interval *wb_int, - enum qdma_hw_access_type access_type); - -int eqdma_mm_channel_conf(void *dev_hndl, uint8_t channel, uint8_t is_c2h, - uint8_t enable); - -int eqdma_dump_reg_info(void *dev_hndl, uint32_t reg_addr, - uint32_t num_regs, char *buf, uint32_t buflen); - -uint32_t eqdma_get_config_num_regs(void); - -struct xreg_info *eqdma_get_config_regs(void); - -#ifdef __cplusplus -} -#endif - -#endif /* __EQDMA_SOFT_ACCESS_H_ */ diff --git a/QDMA/DPDK/drivers/net/qdma/qdma_access/eqdma_soft_access/eqdma_soft_reg.h b/QDMA/DPDK/drivers/net/qdma/qdma_access/eqdma_soft_access/eqdma_soft_reg.h deleted file mode 100755 index 4f326ea02..000000000 --- a/QDMA/DPDK/drivers/net/qdma/qdma_access/eqdma_soft_access/eqdma_soft_reg.h +++ /dev/null @@ -1,1540 +0,0 @@ -/* - * Copyright (c) 2019-2022 Xilinx, Inc. All rights reserved. - * Copyright (c) 2022, Advanced Micro Devices, Inc. All rights reserved. - * - * BSD LICENSE - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * * Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#ifndef __EQDMA_SOFT_REG_H -#define __EQDMA_SOFT_REG_H - - -#ifdef __cplusplus -extern "C" { -#endif - -#include "qdma_platform.h" - -#ifdef CHAR_BIT -#undef CHAR_BIT -#endif -#define CHAR_BIT 8 - -#ifdef BIT -#undef BIT -#endif -#define BIT(n) (1u << (n)) - -#ifdef BITS_PER_BYTE -#undef BITS_PER_BYTE -#endif -#define BITS_PER_BYTE CHAR_BIT - -#ifdef BITS_PER_LONG -#undef BITS_PER_LONG -#endif -#define BITS_PER_LONG (sizeof(uint32_t) * BITS_PER_BYTE) - -#ifdef BITS_PER_LONG_LONG -#undef BITS_PER_LONG_LONG -#endif -#define BITS_PER_LONG_LONG (sizeof(uint64_t) * BITS_PER_BYTE) - -#ifdef GENMASK -#undef GENMASK -#endif -#define GENMASK(h, l) \ - ((0xFFFFFFFF << (l)) & (0xFFFFFFFF >> (BITS_PER_LONG - 1 - (h)))) - -#ifdef GENMASK_ULL -#undef GENMASK_ULL -#endif -#define GENMASK_ULL(h, l) \ - ((0xFFFFFFFFFFFFFFFF << (l)) & \ - (0xFFFFFFFFFFFFFFFF >> (BITS_PER_LONG_LONG - 1 - (h)))) - -#define DEBGFS_LINE_SZ (81) - -#ifdef ARRAY_SIZE -#undef ARRAY_SIZE -#endif -#define ARRAY_SIZE(arr) (sizeof(arr) / \ - sizeof(arr[0])) - - -uint32_t eqdma_config_num_regs_get(void); -struct xreg_info *eqdma_config_regs_get(void); -#define EQDMA_CFG_BLK_IDENTIFIER_ADDR 0x00 -#define CFG_BLK_IDENTIFIER_MASK GENMASK(31, 20) -#define CFG_BLK_IDENTIFIER_1_MASK GENMASK(19, 16) -#define CFG_BLK_IDENTIFIER_RSVD_1_MASK GENMASK(15, 8) -#define CFG_BLK_IDENTIFIER_VERSION_MASK GENMASK(7, 0) -#define EQDMA_CFG_BLK_PCIE_MAX_PLD_SIZE_ADDR 0x08 -#define CFG_BLK_PCIE_MAX_PLD_SIZE_RSVD_1_MASK GENMASK(31, 7) -#define CFG_BLK_PCIE_MAX_PLD_SIZE_PROG_MASK GENMASK(6, 4) -#define CFG_BLK_PCIE_MAX_PLD_SIZE_RSVD_2_MASK BIT(3) -#define CFG_BLK_PCIE_MAX_PLD_SIZE_ISSUED_MASK GENMASK(2, 0) -#define EQDMA_CFG_BLK_PCIE_MAX_READ_REQ_SIZE_ADDR 0x0C -#define CFG_BLK_PCIE_MAX_READ_REQ_SIZE_RSVD_1_MASK GENMASK(31, 7) -#define CFG_BLK_PCIE_MAX_READ_REQ_SIZE_PROG_MASK GENMASK(6, 4) -#define CFG_BLK_PCIE_MAX_READ_REQ_SIZE_RSVD_2_MASK BIT(3) -#define CFG_BLK_PCIE_MAX_READ_REQ_SIZE_ISSUED_MASK GENMASK(2, 0) -#define EQDMA_CFG_BLK_SYSTEM_ID_ADDR 0x10 -#define CFG_BLK_SYSTEM_ID_RSVD_1_MASK GENMASK(31, 17) -#define CFG_BLK_SYSTEM_ID_INST_TYPE_MASK BIT(16) -#define CFG_BLK_SYSTEM_ID_MASK GENMASK(15, 0) -#define EQDMA_CFG_BLK_MSIX_ENABLE_ADDR 0x014 -#define CFG_BLK_MSIX_ENABLE_MASK GENMASK(31, 0) -#define EQDMA_CFG_PCIE_DATA_WIDTH_ADDR 0x18 -#define CFG_PCIE_DATA_WIDTH_RSVD_1_MASK GENMASK(31, 3) -#define CFG_PCIE_DATA_WIDTH_DATAPATH_MASK GENMASK(2, 0) -#define EQDMA_CFG_PCIE_CTL_ADDR 0x1C -#define CFG_PCIE_CTL_RSVD_1_MASK GENMASK(31, 18) -#define CFG_PCIE_CTL_MGMT_AXIL_CTRL_MASK GENMASK(17, 16) -#define CFG_PCIE_CTL_RSVD_2_MASK GENMASK(15, 2) -#define CFG_PCIE_CTL_RRQ_DISABLE_MASK BIT(1) -#define CFG_PCIE_CTL_RELAXED_ORDERING_MASK BIT(0) -#define EQDMA_CFG_BLK_MSI_ENABLE_ADDR 0x20 -#define CFG_BLK_MSI_ENABLE_MASK GENMASK(31, 0) -#define EQDMA_CFG_AXI_USER_MAX_PLD_SIZE_ADDR 0x40 -#define CFG_AXI_USER_MAX_PLD_SIZE_RSVD_1_MASK GENMASK(31, 7) -#define CFG_AXI_USER_MAX_PLD_SIZE_ISSUED_MASK GENMASK(6, 4) -#define CFG_AXI_USER_MAX_PLD_SIZE_RSVD_2_MASK BIT(3) -#define CFG_AXI_USER_MAX_PLD_SIZE_PROG_MASK GENMASK(2, 0) -#define EQDMA_CFG_AXI_USER_MAX_READ_REQ_SIZE_ADDR 0x44 -#define CFG_AXI_USER_MAX_READ_REQ_SIZE_RSVD_1_MASK GENMASK(31, 7) -#define CFG_AXI_USER_MAX_READ_REQ_SIZE_USISSUED_MASK GENMASK(6, 4) -#define CFG_AXI_USER_MAX_READ_REQ_SIZE_RSVD_2_MASK BIT(3) -#define CFG_AXI_USER_MAX_READ_REQ_SIZE_USPROG_MASK GENMASK(2, 0) -#define EQDMA_CFG_BLK_MISC_CTL_ADDR 0x4C -#define CFG_BLK_MISC_CTL_RSVD_1_MASK GENMASK(31, 24) -#define CFG_BLK_MISC_CTL_10B_TAG_EN_MASK BIT(23) -#define CFG_BLK_MISC_CTL_RSVD_2_MASK BIT(22) -#define CFG_BLK_MISC_CTL_AXI_WBK_MASK BIT(21) -#define CFG_BLK_MISC_CTL_AXI_DSC_MASK BIT(20) -#define CFG_BLK_MISC_CTL_NUM_TAG_MASK GENMASK(19, 8) -#define CFG_BLK_MISC_CTL_RSVD_3_MASK GENMASK(7, 5) -#define CFG_BLK_MISC_CTL_RQ_METERING_MULTIPLIER_MASK GENMASK(4, 0) -#define EQDMA_CFG_PL_CRED_CTL_ADDR 0x68 -#define CFG_PL_CRED_CTL_RSVD_1_MASK GENMASK(31, 5) -#define CFG_PL_CRED_CTL_SLAVE_CRD_RLS_MASK BIT(4) -#define CFG_PL_CRED_CTL_RSVD_2_MASK GENMASK(3, 1) -#define CFG_PL_CRED_CTL_MASTER_CRD_RST_MASK BIT(0) -#define EQDMA_CFG_BLK_SCRATCH_ADDR 0x80 -#define CFG_BLK_SCRATCH_MASK GENMASK(31, 0) -#define EQDMA_CFG_GIC_ADDR 0xA0 -#define CFG_GIC_RSVD_1_MASK GENMASK(31, 1) -#define CFG_GIC_GIC_IRQ_MASK BIT(0) -#define EQDMA_RAM_SBE_MSK_1_A_ADDR 0xE0 -#define RAM_SBE_MSK_1_A_MASK GENMASK(31, 0) -#define EQDMA_RAM_SBE_STS_1_A_ADDR 0xE4 -#define RAM_SBE_STS_1_A_RSVD_MASK GENMASK(31, 5) -#define RAM_SBE_STS_1_A_PFCH_CTXT_CAM_RAM_1_MASK BIT(4) -#define RAM_SBE_STS_1_A_PFCH_CTXT_CAM_RAM_0_MASK BIT(3) -#define RAM_SBE_STS_1_A_TAG_EVEN_RAM_MASK BIT(2) -#define RAM_SBE_STS_1_A_TAG_ODD_RAM_MASK BIT(1) -#define RAM_SBE_STS_1_A_RC_RRQ_EVEN_RAM_MASK BIT(0) -#define EQDMA_RAM_DBE_MSK_1_A_ADDR 0xE8 -#define RAM_DBE_MSK_1_A_MASK GENMASK(31, 0) -#define EQDMA_RAM_DBE_STS_1_A_ADDR 0xEC -#define RAM_DBE_STS_1_A_RSVD_MASK GENMASK(31, 5) -#define RAM_DBE_STS_1_A_PFCH_CTXT_CAM_RAM_1_MASK BIT(4) -#define RAM_DBE_STS_1_A_PFCH_CTXT_CAM_RAM_0_MASK BIT(3) -#define RAM_DBE_STS_1_A_TAG_EVEN_RAM_MASK BIT(2) -#define RAM_DBE_STS_1_A_TAG_ODD_RAM_MASK BIT(1) -#define RAM_DBE_STS_1_A_RC_RRQ_EVEN_RAM_MASK BIT(0) -#define EQDMA_RAM_SBE_MSK_A_ADDR 0xF0 -#define RAM_SBE_MSK_A_MASK GENMASK(31, 0) -#define EQDMA_RAM_SBE_STS_A_ADDR 0xF4 -#define RAM_SBE_STS_A_RC_RRQ_ODD_RAM_MASK BIT(31) -#define RAM_SBE_STS_A_PEND_FIFO_RAM_MASK BIT(30) -#define RAM_SBE_STS_A_PFCH_LL_RAM_MASK BIT(29) -#define RAM_SBE_STS_A_WRB_CTXT_RAM_MASK BIT(28) -#define RAM_SBE_STS_A_PFCH_CTXT_RAM_MASK BIT(27) -#define RAM_SBE_STS_A_DESC_REQ_FIFO_RAM_MASK BIT(26) -#define RAM_SBE_STS_A_INT_CTXT_RAM_MASK BIT(25) -#define RAM_SBE_STS_A_WRB_COAL_DATA_RAM_MASK BIT(24) -#define RAM_SBE_STS_A_QID_FIFO_RAM_MASK BIT(23) -#define RAM_SBE_STS_A_TIMER_FIFO_RAM_MASK GENMASK(22, 19) -#define RAM_SBE_STS_A_MI_TL_SLV_FIFO_RAM_MASK BIT(18) -#define RAM_SBE_STS_A_DSC_CPLD_MASK BIT(17) -#define RAM_SBE_STS_A_DSC_CPLI_MASK BIT(16) -#define RAM_SBE_STS_A_DSC_SW_CTXT_MASK BIT(15) -#define RAM_SBE_STS_A_DSC_CRD_RCV_MASK BIT(14) -#define RAM_SBE_STS_A_DSC_HW_CTXT_MASK BIT(13) -#define RAM_SBE_STS_A_FUNC_MAP_MASK BIT(12) -#define RAM_SBE_STS_A_C2H_WR_BRG_DAT_MASK BIT(11) -#define RAM_SBE_STS_A_C2H_RD_BRG_DAT_MASK BIT(10) -#define RAM_SBE_STS_A_H2C_WR_BRG_DAT_MASK BIT(9) -#define RAM_SBE_STS_A_H2C_RD_BRG_DAT_MASK BIT(8) -#define RAM_SBE_STS_A_MI_C2H3_DAT_MASK BIT(7) -#define RAM_SBE_STS_A_MI_C2H2_DAT_MASK BIT(6) -#define RAM_SBE_STS_A_MI_C2H1_DAT_MASK BIT(5) -#define RAM_SBE_STS_A_MI_C2H0_DAT_MASK BIT(4) -#define RAM_SBE_STS_A_MI_H2C3_DAT_MASK BIT(3) -#define RAM_SBE_STS_A_MI_H2C2_DAT_MASK BIT(2) -#define RAM_SBE_STS_A_MI_H2C1_DAT_MASK BIT(1) -#define RAM_SBE_STS_A_MI_H2C0_DAT_MASK BIT(0) -#define EQDMA_RAM_DBE_MSK_A_ADDR 0xF8 -#define RAM_DBE_MSK_A_MASK GENMASK(31, 0) -#define EQDMA_RAM_DBE_STS_A_ADDR 0xFC -#define RAM_DBE_STS_A_RC_RRQ_ODD_RAM_MASK BIT(31) -#define RAM_DBE_STS_A_PEND_FIFO_RAM_MASK BIT(30) -#define RAM_DBE_STS_A_PFCH_LL_RAM_MASK BIT(29) -#define RAM_DBE_STS_A_WRB_CTXT_RAM_MASK BIT(28) -#define RAM_DBE_STS_A_PFCH_CTXT_RAM_MASK BIT(27) -#define RAM_DBE_STS_A_DESC_REQ_FIFO_RAM_MASK BIT(26) -#define RAM_DBE_STS_A_INT_CTXT_RAM_MASK BIT(25) -#define RAM_DBE_STS_A_WRB_COAL_DATA_RAM_MASK BIT(24) -#define RAM_DBE_STS_A_QID_FIFO_RAM_MASK BIT(23) -#define RAM_DBE_STS_A_TIMER_FIFO_RAM_MASK GENMASK(22, 19) -#define RAM_DBE_STS_A_MI_TL_SLV_FIFO_RAM_MASK BIT(18) -#define RAM_DBE_STS_A_DSC_CPLD_MASK BIT(17) -#define RAM_DBE_STS_A_DSC_CPLI_MASK BIT(16) -#define RAM_DBE_STS_A_DSC_SW_CTXT_MASK BIT(15) -#define RAM_DBE_STS_A_DSC_CRD_RCV_MASK BIT(14) -#define RAM_DBE_STS_A_DSC_HW_CTXT_MASK BIT(13) -#define RAM_DBE_STS_A_FUNC_MAP_MASK BIT(12) -#define RAM_DBE_STS_A_C2H_WR_BRG_DAT_MASK BIT(11) -#define RAM_DBE_STS_A_C2H_RD_BRG_DAT_MASK BIT(10) -#define RAM_DBE_STS_A_H2C_WR_BRG_DAT_MASK BIT(9) -#define RAM_DBE_STS_A_H2C_RD_BRG_DAT_MASK BIT(8) -#define RAM_DBE_STS_A_MI_C2H3_DAT_MASK BIT(7) -#define RAM_DBE_STS_A_MI_C2H2_DAT_MASK BIT(6) -#define RAM_DBE_STS_A_MI_C2H1_DAT_MASK BIT(5) -#define RAM_DBE_STS_A_MI_C2H0_DAT_MASK BIT(4) -#define RAM_DBE_STS_A_MI_H2C3_DAT_MASK BIT(3) -#define RAM_DBE_STS_A_MI_H2C2_DAT_MASK BIT(2) -#define RAM_DBE_STS_A_MI_H2C1_DAT_MASK BIT(1) -#define RAM_DBE_STS_A_MI_H2C0_DAT_MASK BIT(0) -#define EQDMA_GLBL2_IDENTIFIER_ADDR 0x100 -#define GLBL2_IDENTIFIER_MASK GENMASK(31, 8) -#define GLBL2_IDENTIFIER_VERSION_MASK GENMASK(7, 0) -#define EQDMA_GLBL2_CHANNEL_INST_ADDR 0x114 -#define GLBL2_CHANNEL_INST_RSVD_1_MASK GENMASK(31, 18) -#define GLBL2_CHANNEL_INST_C2H_ST_MASK BIT(17) -#define GLBL2_CHANNEL_INST_H2C_ST_MASK BIT(16) -#define GLBL2_CHANNEL_INST_RSVD_2_MASK GENMASK(15, 12) -#define GLBL2_CHANNEL_INST_C2H_ENG_MASK GENMASK(11, 8) -#define GLBL2_CHANNEL_INST_RSVD_3_MASK GENMASK(7, 4) -#define GLBL2_CHANNEL_INST_H2C_ENG_MASK GENMASK(3, 0) -#define EQDMA_GLBL2_CHANNEL_MDMA_ADDR 0x118 -#define GLBL2_CHANNEL_MDMA_RSVD_1_MASK GENMASK(31, 18) -#define GLBL2_CHANNEL_MDMA_C2H_ST_MASK BIT(17) -#define GLBL2_CHANNEL_MDMA_H2C_ST_MASK BIT(16) -#define GLBL2_CHANNEL_MDMA_RSVD_2_MASK GENMASK(15, 12) -#define GLBL2_CHANNEL_MDMA_C2H_ENG_MASK GENMASK(11, 8) -#define GLBL2_CHANNEL_MDMA_RSVD_3_MASK GENMASK(7, 4) -#define GLBL2_CHANNEL_MDMA_H2C_ENG_MASK GENMASK(3, 0) -#define EQDMA_GLBL2_CHANNEL_STRM_ADDR 0x11C -#define GLBL2_CHANNEL_STRM_RSVD_1_MASK GENMASK(31, 18) -#define GLBL2_CHANNEL_STRM_C2H_ST_MASK BIT(17) -#define GLBL2_CHANNEL_STRM_H2C_ST_MASK BIT(16) -#define GLBL2_CHANNEL_STRM_RSVD_2_MASK GENMASK(15, 12) -#define GLBL2_CHANNEL_STRM_C2H_ENG_MASK GENMASK(11, 8) -#define GLBL2_CHANNEL_STRM_RSVD_3_MASK GENMASK(7, 4) -#define GLBL2_CHANNEL_STRM_H2C_ENG_MASK GENMASK(3, 0) -#define EQDMA_GLBL2_CHANNEL_CAP_ADDR 0x120 -#define GLBL2_CHANNEL_CAP_RSVD_1_MASK GENMASK(31, 12) -#define GLBL2_CHANNEL_CAP_MULTIQ_MAX_MASK GENMASK(11, 0) -#define EQDMA_GLBL2_CHANNEL_PASID_CAP_ADDR 0x128 -#define GLBL2_CHANNEL_PASID_CAP_RSVD_1_MASK GENMASK(31, 2) -#define GLBL2_CHANNEL_PASID_CAP_BRIDGEEN_MASK BIT(1) -#define GLBL2_CHANNEL_PASID_CAP_DMAEN_MASK BIT(0) -#define EQDMA_GLBL2_SYSTEM_ID_ADDR 0x130 -#define GLBL2_SYSTEM_ID_RSVD_1_MASK GENMASK(31, 16) -#define GLBL2_SYSTEM_ID_MASK GENMASK(15, 0) -#define EQDMA_GLBL2_MISC_CAP_ADDR 0x134 -#define GLBL2_MISC_CAP_MASK GENMASK(31, 0) -#define EQDMA_GLBL2_RRQ_BRG_THROT_ADDR 0x158 -#define GLBL2_RRQ_BRG_THROT_REQ_EN_MASK BIT(31) -#define GLBL2_RRQ_BRG_THROT_REQ_MASK GENMASK(30, 19) -#define GLBL2_RRQ_BRG_THROT_DAT_EN_MASK BIT(18) -#define GLBL2_RRQ_BRG_THROT_DAT_MASK GENMASK(17, 0) -#define EQDMA_GLBL2_RRQ_PCIE_THROT_ADDR 0x15C -#define GLBL2_RRQ_PCIE_THROT_REQ_EN_MASK BIT(31) -#define GLBL2_RRQ_PCIE_THROT_REQ_MASK GENMASK(30, 19) -#define GLBL2_RRQ_PCIE_THROT_DAT_EN_MASK BIT(18) -#define GLBL2_RRQ_PCIE_THROT_DAT_MASK GENMASK(17, 0) -#define EQDMA_GLBL2_RRQ_AXIMM_THROT_ADDR 0x160 -#define GLBL2_RRQ_AXIMM_THROT_REQ_EN_MASK BIT(31) -#define GLBL2_RRQ_AXIMM_THROT_REQ_MASK GENMASK(30, 19) -#define GLBL2_RRQ_AXIMM_THROT_DAT_EN_MASK BIT(18) -#define GLBL2_RRQ_AXIMM_THROT_DAT_MASK GENMASK(17, 0) -#define EQDMA_GLBL2_RRQ_PCIE_LAT0_ADDR 0x164 -#define GLBL2_RRQ_PCIE_LAT0_MAX_MASK GENMASK(31, 16) -#define GLBL2_RRQ_PCIE_LAT0_MIN_MASK GENMASK(15, 0) -#define EQDMA_GLBL2_RRQ_PCIE_LAT1_ADDR 0x168 -#define GLBL2_RRQ_PCIE_LAT1_RSVD_MASK GENMASK(31, 17) -#define GLBL2_RRQ_PCIE_LAT1_OVFL_MASK BIT(16) -#define GLBL2_RRQ_PCIE_LAT1_AVG_MASK GENMASK(15, 0) -#define EQDMA_GLBL2_RRQ_AXIMM_LAT0_ADDR 0x16C -#define GLBL2_RRQ_AXIMM_LAT0_MAX_MASK GENMASK(31, 16) -#define GLBL2_RRQ_AXIMM_LAT0_MIN_MASK GENMASK(15, 0) -#define EQDMA_GLBL2_RRQ_AXIMM_LAT1_ADDR 0x170 -#define GLBL2_RRQ_AXIMM_LAT1_RSVD_MASK GENMASK(31, 17) -#define GLBL2_RRQ_AXIMM_LAT1_OVFL_MASK BIT(16) -#define GLBL2_RRQ_AXIMM_LAT1_AVG_MASK GENMASK(15, 0) -#define EQDMA_GLBL2_DBG_PCIE_RQ0_ADDR 0x1B8 -#define GLBL2_PCIE_RQ0_NPH_AVL_MASK GENMASK(31, 20) -#define GLBL2_PCIE_RQ0_RCB_AVL_MASK GENMASK(19, 9) -#define GLBL2_PCIE_RQ0_SLV_RD_CREDS_MASK GENMASK(8, 2) -#define GLBL2_PCIE_RQ0_TAG_EP_MASK GENMASK(1, 0) -#define EQDMA_GLBL2_DBG_PCIE_RQ1_ADDR 0x1BC -#define GLBL2_PCIE_RQ1_RSVD_1_MASK GENMASK(31, 21) -#define GLBL2_PCIE_RQ1_TAG_FL_MASK GENMASK(20, 19) -#define GLBL2_PCIE_RQ1_WTLP_HEADER_FIFO_FL_MASK BIT(18) -#define GLBL2_PCIE_RQ1_WTLP_HEADER_FIFO_EP_MASK BIT(17) -#define GLBL2_PCIE_RQ1_RQ_FIFO_EP_MASK BIT(16) -#define GLBL2_PCIE_RQ1_RQ_FIFO_FL_MASK BIT(15) -#define GLBL2_PCIE_RQ1_TLPSM_MASK GENMASK(14, 12) -#define GLBL2_PCIE_RQ1_TLPSM512_MASK GENMASK(11, 9) -#define GLBL2_PCIE_RQ1_RREQ_RCB_OK_MASK BIT(8) -#define GLBL2_PCIE_RQ1_RREQ0_SLV_MASK BIT(7) -#define GLBL2_PCIE_RQ1_RREQ0_VLD_MASK BIT(6) -#define GLBL2_PCIE_RQ1_RREQ0_RDY_MASK BIT(5) -#define GLBL2_PCIE_RQ1_RREQ1_SLV_MASK BIT(4) -#define GLBL2_PCIE_RQ1_RREQ1_VLD_MASK BIT(3) -#define GLBL2_PCIE_RQ1_RREQ1_RDY_MASK BIT(2) -#define GLBL2_PCIE_RQ1_WTLP_REQ_MASK BIT(1) -#define GLBL2_PCIE_RQ1_WTLP_STRADDLE_MASK BIT(0) -#define EQDMA_GLBL2_DBG_AXIMM_WR0_ADDR 0x1C0 -#define GLBL2_AXIMM_WR0_RSVD_1_MASK GENMASK(31, 27) -#define GLBL2_AXIMM_WR0_WR_REQ_MASK BIT(26) -#define GLBL2_AXIMM_WR0_WR_CHN_MASK GENMASK(25, 23) -#define GLBL2_AXIMM_WR0_WTLP_DATA_FIFO_EP_MASK BIT(22) -#define GLBL2_AXIMM_WR0_WPL_FIFO_EP_MASK BIT(21) -#define GLBL2_AXIMM_WR0_BRSP_CLAIM_CHN_MASK GENMASK(20, 18) -#define GLBL2_AXIMM_WR0_WRREQ_CNT_MASK GENMASK(17, 12) -#define GLBL2_AXIMM_WR0_BID_MASK GENMASK(11, 9) -#define GLBL2_AXIMM_WR0_BVALID_MASK BIT(8) -#define GLBL2_AXIMM_WR0_BREADY_MASK BIT(7) -#define GLBL2_AXIMM_WR0_WVALID_MASK BIT(6) -#define GLBL2_AXIMM_WR0_WREADY_MASK BIT(5) -#define GLBL2_AXIMM_WR0_AWID_MASK GENMASK(4, 2) -#define GLBL2_AXIMM_WR0_AWVALID_MASK BIT(1) -#define GLBL2_AXIMM_WR0_AWREADY_MASK BIT(0) -#define EQDMA_GLBL2_DBG_AXIMM_WR1_ADDR 0x1C4 -#define GLBL2_AXIMM_WR1_RSVD_1_MASK GENMASK(31, 30) -#define GLBL2_AXIMM_WR1_BRSP_CNT4_MASK GENMASK(29, 24) -#define GLBL2_AXIMM_WR1_BRSP_CNT3_MASK GENMASK(23, 18) -#define GLBL2_AXIMM_WR1_BRSP_CNT2_MASK GENMASK(17, 12) -#define GLBL2_AXIMM_WR1_BRSP_CNT1_MASK GENMASK(11, 6) -#define GLBL2_AXIMM_WR1_BRSP_CNT0_MASK GENMASK(5, 0) -#define EQDMA_GLBL2_DBG_AXIMM_RD0_ADDR 0x1C8 -#define GLBL2_AXIMM_RD0_RSVD_1_MASK GENMASK(31, 23) -#define GLBL2_AXIMM_RD0_PND_CNT_MASK GENMASK(22, 17) -#define GLBL2_AXIMM_RD0_RD_REQ_MASK BIT(16) -#define GLBL2_AXIMM_RD0_RD_CHNL_MASK GENMASK(15, 13) -#define GLBL2_AXIMM_RD0_RRSP_CLAIM_CHNL_MASK GENMASK(12, 10) -#define GLBL2_AXIMM_RD0_RID_MASK GENMASK(9, 7) -#define GLBL2_AXIMM_RD0_RVALID_MASK BIT(6) -#define GLBL2_AXIMM_RD0_RREADY_MASK BIT(5) -#define GLBL2_AXIMM_RD0_ARID_MASK GENMASK(4, 2) -#define GLBL2_AXIMM_RD0_ARVALID_MASK BIT(1) -#define GLBL2_AXIMM_RD0_ARREADY_MASK BIT(0) -#define EQDMA_GLBL2_DBG_AXIMM_RD1_ADDR 0x1CC -#define GLBL2_AXIMM_RD1_RSVD_1_MASK GENMASK(31, 30) -#define GLBL2_AXIMM_RD1_RRSP_CNT4_MASK GENMASK(29, 24) -#define GLBL2_AXIMM_RD1_RRSP_CNT3_MASK GENMASK(23, 18) -#define GLBL2_AXIMM_RD1_RRSP_CNT2_MASK GENMASK(17, 12) -#define GLBL2_AXIMM_RD1_RRSP_CNT1_MASK GENMASK(11, 6) -#define GLBL2_AXIMM_RD1_RRSP_CNT0_MASK GENMASK(5, 0) -#define EQDMA_GLBL2_DBG_FAB0_ADDR 0x1D0 -#define GLBL2_FAB0_H2C_INB_CONV_IN_VLD_MASK BIT(31) -#define GLBL2_FAB0_H2C_INB_CONV_IN_RDY_MASK BIT(30) -#define GLBL2_FAB0_H2C_SEG_IN_VLD_MASK BIT(29) -#define GLBL2_FAB0_H2C_SEG_IN_RDY_MASK BIT(28) -#define GLBL2_FAB0_H2C_SEG_OUT_VLD_MASK GENMASK(27, 24) -#define GLBL2_FAB0_H2C_SEG_OUT_RDY_MASK BIT(23) -#define GLBL2_FAB0_H2C_MST_CRDT_STAT_MASK GENMASK(22, 16) -#define GLBL2_FAB0_C2H_SLV_AFIFO_FULL_MASK BIT(15) -#define GLBL2_FAB0_C2H_SLV_AFIFO_EMPTY_MASK BIT(14) -#define GLBL2_FAB0_C2H_DESEG_SEG_VLD_MASK GENMASK(13, 10) -#define GLBL2_FAB0_C2H_DESEG_SEG_RDY_MASK BIT(9) -#define GLBL2_FAB0_C2H_DESEG_OUT_VLD_MASK BIT(8) -#define GLBL2_FAB0_C2H_DESEG_OUT_RDY_MASK BIT(7) -#define GLBL2_FAB0_C2H_INB_DECONV_OUT_VLD_MASK BIT(6) -#define GLBL2_FAB0_C2H_INB_DECONV_OUT_RDY_MASK BIT(5) -#define GLBL2_FAB0_C2H_DSC_CRDT_AFIFO_FULL_MASK BIT(4) -#define GLBL2_FAB0_C2H_DSC_CRDT_AFIFO_EMPTY_MASK BIT(3) -#define GLBL2_FAB0_IRQ_IN_AFIFO_FULL_MASK BIT(2) -#define GLBL2_FAB0_IRQ_IN_AFIFO_EMPTY_MASK BIT(1) -#define GLBL2_FAB0_IMM_CRD_AFIFO_EMPTY_MASK BIT(0) -#define EQDMA_GLBL2_DBG_FAB1_ADDR 0x1D4 -#define GLBL2_FAB1_BYP_OUT_CRDT_STAT_MASK GENMASK(31, 25) -#define GLBL2_FAB1_TM_DSC_STS_CRDT_STAT_MASK GENMASK(24, 18) -#define GLBL2_FAB1_C2H_CMN_AFIFO_FULL_MASK BIT(17) -#define GLBL2_FAB1_C2H_CMN_AFIFO_EMPTY_MASK BIT(16) -#define GLBL2_FAB1_RSVD_1_MASK GENMASK(15, 13) -#define GLBL2_FAB1_C2H_BYP_IN_AFIFO_FULL_MASK BIT(12) -#define GLBL2_FAB1_RSVD_2_MASK GENMASK(11, 9) -#define GLBL2_FAB1_C2H_BYP_IN_AFIFO_EMPTY_MASK BIT(8) -#define GLBL2_FAB1_RSVD_3_MASK GENMASK(7, 5) -#define GLBL2_FAB1_H2C_BYP_IN_AFIFO_FULL_MASK BIT(4) -#define GLBL2_FAB1_RSVD_4_MASK GENMASK(3, 1) -#define GLBL2_FAB1_H2C_BYP_IN_AFIFO_EMPTY_MASK BIT(0) -#define EQDMA_GLBL2_DBG_MATCH_SEL_ADDR 0x1F4 -#define GLBL2_MATCH_SEL_RSV_MASK GENMASK(31, 18) -#define GLBL2_MATCH_SEL_CSR_SEL_MASK GENMASK(17, 13) -#define GLBL2_MATCH_SEL_CSR_EN_MASK BIT(12) -#define GLBL2_MATCH_SEL_ROTATE1_MASK GENMASK(11, 10) -#define GLBL2_MATCH_SEL_ROTATE0_MASK GENMASK(9, 8) -#define GLBL2_MATCH_SEL_SEL_MASK GENMASK(7, 0) -#define EQDMA_GLBL2_DBG_MATCH_MSK_ADDR 0x1F8 -#define GLBL2_MATCH_MSK_MASK GENMASK(31, 0) -#define EQDMA_GLBL2_DBG_MATCH_PAT_ADDR 0x1FC -#define GLBL2_MATCH_PAT_PATTERN_MASK GENMASK(31, 0) -#define EQDMA_GLBL_RNG_SZ_1_ADDR 0x204 -#define GLBL_RNG_SZ_1_RSVD_1_MASK GENMASK(31, 16) -#define GLBL_RNG_SZ_1_RING_SIZE_MASK GENMASK(15, 0) -#define EQDMA_GLBL_RNG_SZ_2_ADDR 0x208 -#define GLBL_RNG_SZ_2_RSVD_1_MASK GENMASK(31, 16) -#define GLBL_RNG_SZ_2_RING_SIZE_MASK GENMASK(15, 0) -#define EQDMA_GLBL_RNG_SZ_3_ADDR 0x20C -#define GLBL_RNG_SZ_3_RSVD_1_MASK GENMASK(31, 16) -#define GLBL_RNG_SZ_3_RING_SIZE_MASK GENMASK(15, 0) -#define EQDMA_GLBL_RNG_SZ_4_ADDR 0x210 -#define GLBL_RNG_SZ_4_RSVD_1_MASK GENMASK(31, 16) -#define GLBL_RNG_SZ_4_RING_SIZE_MASK GENMASK(15, 0) -#define EQDMA_GLBL_RNG_SZ_5_ADDR 0x214 -#define GLBL_RNG_SZ_5_RSVD_1_MASK GENMASK(31, 16) -#define GLBL_RNG_SZ_5_RING_SIZE_MASK GENMASK(15, 0) -#define EQDMA_GLBL_RNG_SZ_6_ADDR 0x218 -#define GLBL_RNG_SZ_6_RSVD_1_MASK GENMASK(31, 16) -#define GLBL_RNG_SZ_6_RING_SIZE_MASK GENMASK(15, 0) -#define EQDMA_GLBL_RNG_SZ_7_ADDR 0x21C -#define GLBL_RNG_SZ_7_RSVD_1_MASK GENMASK(31, 16) -#define GLBL_RNG_SZ_7_RING_SIZE_MASK GENMASK(15, 0) -#define EQDMA_GLBL_RNG_SZ_8_ADDR 0x220 -#define GLBL_RNG_SZ_8_RSVD_1_MASK GENMASK(31, 16) -#define GLBL_RNG_SZ_8_RING_SIZE_MASK GENMASK(15, 0) -#define EQDMA_GLBL_RNG_SZ_9_ADDR 0x224 -#define GLBL_RNG_SZ_9_RSVD_1_MASK GENMASK(31, 16) -#define GLBL_RNG_SZ_9_RING_SIZE_MASK GENMASK(15, 0) -#define EQDMA_GLBL_RNG_SZ_A_ADDR 0x228 -#define GLBL_RNG_SZ_A_RSVD_1_MASK GENMASK(31, 16) -#define GLBL_RNG_SZ_A_RING_SIZE_MASK GENMASK(15, 0) -#define EQDMA_GLBL_RNG_SZ_B_ADDR 0x22C -#define GLBL_RNG_SZ_B_RSVD_1_MASK GENMASK(31, 16) -#define GLBL_RNG_SZ_B_RING_SIZE_MASK GENMASK(15, 0) -#define EQDMA_GLBL_RNG_SZ_C_ADDR 0x230 -#define GLBL_RNG_SZ_C_RSVD_1_MASK GENMASK(31, 16) -#define GLBL_RNG_SZ_C_RING_SIZE_MASK GENMASK(15, 0) -#define EQDMA_GLBL_RNG_SZ_D_ADDR 0x234 -#define GLBL_RNG_SZ_D_RSVD_1_MASK GENMASK(31, 16) -#define GLBL_RNG_SZ_D_RING_SIZE_MASK GENMASK(15, 0) -#define EQDMA_GLBL_RNG_SZ_E_ADDR 0x238 -#define GLBL_RNG_SZ_E_RSVD_1_MASK GENMASK(31, 16) -#define GLBL_RNG_SZ_E_RING_SIZE_MASK GENMASK(15, 0) -#define EQDMA_GLBL_RNG_SZ_F_ADDR 0x23C -#define GLBL_RNG_SZ_F_RSVD_1_MASK GENMASK(31, 16) -#define GLBL_RNG_SZ_F_RING_SIZE_MASK GENMASK(15, 0) -#define EQDMA_GLBL_RNG_SZ_10_ADDR 0x240 -#define GLBL_RNG_SZ_10_RSVD_1_MASK GENMASK(31, 16) -#define GLBL_RNG_SZ_10_RING_SIZE_MASK GENMASK(15, 0) -#define EQDMA_GLBL_ERR_STAT_ADDR 0x248 -#define GLBL_ERR_STAT_RSVD_1_MASK GENMASK(31, 18) -#define GLBL_ERR_STAT_ERR_FAB_MASK BIT(17) -#define GLBL_ERR_STAT_ERR_H2C_ST_MASK BIT(16) -#define GLBL_ERR_STAT_ERR_BDG_MASK BIT(15) -#define GLBL_ERR_STAT_IND_CTXT_CMD_ERR_MASK GENMASK(14, 9) -#define GLBL_ERR_STAT_ERR_C2H_ST_MASK BIT(8) -#define GLBL_ERR_STAT_ERR_C2H_MM_1_MASK BIT(7) -#define GLBL_ERR_STAT_ERR_C2H_MM_0_MASK BIT(6) -#define GLBL_ERR_STAT_ERR_H2C_MM_1_MASK BIT(5) -#define GLBL_ERR_STAT_ERR_H2C_MM_0_MASK BIT(4) -#define GLBL_ERR_STAT_ERR_TRQ_MASK BIT(3) -#define GLBL_ERR_STAT_ERR_DSC_MASK BIT(2) -#define GLBL_ERR_STAT_ERR_RAM_DBE_MASK BIT(1) -#define GLBL_ERR_STAT_ERR_RAM_SBE_MASK BIT(0) -#define EQDMA_GLBL_ERR_MASK_ADDR 0x24C -#define GLBL_ERR_MASK GENMASK(31, 0) -#define EQDMA_GLBL_DSC_CFG_ADDR 0x250 -#define GLBL_DSC_CFG_RSVD_1_MASK GENMASK(31, 30) -#define GLBL_DSC_CFG_C2H_UODSC_LIMIT_MASK GENMASK(29, 20) -#define GLBL_DSC_CFG_H2C_UODSC_LIMIT_MASK GENMASK(19, 10) -#define GLBL_DSC_CFG_UNC_OVR_COR_MASK BIT(9) -#define GLBL_DSC_CFG_CTXT_FER_DIS_MASK BIT(8) -#define GLBL_DSC_CFG_RSVD_2_MASK GENMASK(7, 6) -#define GLBL_DSC_CFG_MAXFETCH_MASK GENMASK(5, 3) -#define GLBL_DSC_CFG_WB_ACC_INT_MASK GENMASK(2, 0) -#define EQDMA_GLBL_DSC_ERR_STS_ADDR 0x254 -#define GLBL_DSC_ERR_STS_RSVD_1_MASK GENMASK(31, 26) -#define GLBL_DSC_ERR_STS_PORT_ID_MASK BIT(25) -#define GLBL_DSC_ERR_STS_SBE_MASK BIT(24) -#define GLBL_DSC_ERR_STS_DBE_MASK BIT(23) -#define GLBL_DSC_ERR_STS_RQ_CANCEL_MASK BIT(22) -#define GLBL_DSC_ERR_STS_DSC_MASK BIT(21) -#define GLBL_DSC_ERR_STS_DMA_MASK BIT(20) -#define GLBL_DSC_ERR_STS_FLR_CANCEL_MASK BIT(19) -#define GLBL_DSC_ERR_STS_RSVD_2_MASK GENMASK(18, 17) -#define GLBL_DSC_ERR_STS_DAT_POISON_MASK BIT(16) -#define GLBL_DSC_ERR_STS_TIMEOUT_MASK BIT(9) -#define GLBL_DSC_ERR_STS_FLR_MASK BIT(8) -#define GLBL_DSC_ERR_STS_TAG_MASK BIT(6) -#define GLBL_DSC_ERR_STS_ADDR_MASK BIT(5) -#define GLBL_DSC_ERR_STS_PARAM_MASK BIT(4) -#define GLBL_DSC_ERR_STS_BCNT_MASK BIT(3) -#define GLBL_DSC_ERR_STS_UR_CA_MASK BIT(2) -#define GLBL_DSC_ERR_STS_POISON_MASK BIT(1) -#define EQDMA_GLBL_DSC_ERR_MSK_ADDR 0x258 -#define GLBL_DSC_ERR_MSK_MASK GENMASK(31, 0) -#define EQDMA_GLBL_DSC_ERR_LOG0_ADDR 0x25C -#define GLBL_DSC_ERR_LOG0_VALID_MASK BIT(31) -#define GLBL_DSC_ERR_LOG0_SEL_MASK BIT(30) -#define GLBL_DSC_ERR_LOG0_RSVD_1_MASK GENMASK(29, 13) -#define GLBL_DSC_ERR_LOG0_QID_MASK GENMASK(12, 0) -#define EQDMA_GLBL_DSC_ERR_LOG1_ADDR 0x260 -#define GLBL_DSC_ERR_LOG1_RSVD_1_MASK GENMASK(31, 28) -#define GLBL_DSC_ERR_LOG1_CIDX_MASK GENMASK(27, 12) -#define GLBL_DSC_ERR_LOG1_RSVD_2_MASK GENMASK(11, 9) -#define GLBL_DSC_ERR_LOG1_SUB_TYPE_MASK GENMASK(8, 5) -#define GLBL_DSC_ERR_LOG1_ERR_TYPE_MASK GENMASK(4, 0) -#define EQDMA_GLBL_TRQ_ERR_STS_ADDR 0x264 -#define GLBL_TRQ_ERR_STS_RSVD_1_MASK GENMASK(31, 8) -#define GLBL_TRQ_ERR_STS_TCP_QSPC_TIMEOUT_MASK BIT(7) -#define GLBL_TRQ_ERR_STS_RSVD_2_MASK BIT(6) -#define GLBL_TRQ_ERR_STS_QID_RANGE_MASK BIT(5) -#define GLBL_TRQ_ERR_STS_QSPC_UNMAPPED_MASK BIT(4) -#define GLBL_TRQ_ERR_STS_TCP_CSR_TIMEOUT_MASK BIT(3) -#define GLBL_TRQ_ERR_STS_RSVD_3_MASK BIT(2) -#define GLBL_TRQ_ERR_STS_VF_ACCESS_ERR_MASK BIT(1) -#define GLBL_TRQ_ERR_STS_CSR_UNMAPPED_MASK BIT(0) -#define EQDMA_GLBL_TRQ_ERR_MSK_ADDR 0x268 -#define GLBL_TRQ_ERR_MSK_MASK GENMASK(31, 0) -#define EQDMA_GLBL_TRQ_ERR_LOG_ADDR 0x26C -#define GLBL_TRQ_ERR_LOG_SRC_MASK BIT(31) -#define GLBL_TRQ_ERR_LOG_TARGET_MASK GENMASK(30, 27) -#define GLBL_TRQ_ERR_LOG_FUNC_MASK GENMASK(26, 17) -#define GLBL_TRQ_ERR_LOG_ADDRESS_MASK GENMASK(16, 0) -#define EQDMA_GLBL_DSC_DBG_DAT0_ADDR 0x270 -#define GLBL_DSC_DAT0_RSVD_1_MASK GENMASK(31, 30) -#define GLBL_DSC_DAT0_CTXT_ARB_DIR_MASK BIT(29) -#define GLBL_DSC_DAT0_CTXT_ARB_QID_MASK GENMASK(28, 17) -#define GLBL_DSC_DAT0_CTXT_ARB_REQ_MASK GENMASK(16, 12) -#define GLBL_DSC_DAT0_IRQ_FIFO_FL_MASK BIT(11) -#define GLBL_DSC_DAT0_TMSTALL_MASK BIT(10) -#define GLBL_DSC_DAT0_RRQ_STALL_MASK GENMASK(9, 8) -#define GLBL_DSC_DAT0_RCP_FIFO_SPC_STALL_MASK GENMASK(7, 6) -#define GLBL_DSC_DAT0_RRQ_FIFO_SPC_STALL_MASK GENMASK(5, 4) -#define GLBL_DSC_DAT0_FAB_MRKR_RSP_STALL_MASK GENMASK(3, 2) -#define GLBL_DSC_DAT0_DSC_OUT_STALL_MASK GENMASK(1, 0) -#define EQDMA_GLBL_DSC_DBG_DAT1_ADDR 0x274 -#define GLBL_DSC_DAT1_RSVD_1_MASK GENMASK(31, 28) -#define GLBL_DSC_DAT1_EVT_SPC_C2H_MASK GENMASK(27, 22) -#define GLBL_DSC_DAT1_EVT_SP_H2C_MASK GENMASK(21, 16) -#define GLBL_DSC_DAT1_DSC_SPC_C2H_MASK GENMASK(15, 8) -#define GLBL_DSC_DAT1_DSC_SPC_H2C_MASK GENMASK(7, 0) -#define EQDMA_GLBL_DSC_DBG_CTL_ADDR 0x278 -#define GLBL_DSC_CTL_RSVD_1_MASK GENMASK(31, 16) -#define GLBL_DSC_CTL_LAT_QID_MASK GENMASK(15, 4) -#define GLBL_DSC_CTL_DSC_ENG_LAT_CLR_MASK BIT(3) -#define GLBL_DSC_CTL_SELECT_MASK GENMASK(2, 0) -#define EQDMA_GLBL_DSC_ERR_LOG2_ADDR 0x27c -#define GLBL_DSC_ERR_LOG2_OLD_PIDX_MASK GENMASK(31, 16) -#define GLBL_DSC_ERR_LOG2_NEW_PIDX_MASK GENMASK(15, 0) -#define EQDMA_GLBL_GLBL_INTERRUPT_CFG_ADDR 0x2c4 -#define GLBL_GLBL_INTERRUPT_CFG_RSVD_1_MASK GENMASK(31, 2) -#define GLBL_GLBL_INTERRUPT_CFG_LGCY_INTR_PENDING_MASK BIT(1) -#define GLBL_GLBL_INTERRUPT_CFG_EN_LGCY_INTR_MASK BIT(0) -#define EQDMA_GLBL_VCH_HOST_PROFILE_ADDR 0x2c8 -#define GLBL_VCH_HOST_PROFILE_RSVD_1_MASK GENMASK(31, 28) -#define GLBL_VCH_HOST_PROFILE_2C_MM_MASK GENMASK(27, 24) -#define GLBL_VCH_HOST_PROFILE_2C_ST_MASK GENMASK(23, 20) -#define GLBL_VCH_HOST_PROFILE_VCH_DSC_MASK GENMASK(19, 16) -#define GLBL_VCH_HOST_PROFILE_VCH_INT_MSG_MASK GENMASK(15, 12) -#define GLBL_VCH_HOST_PROFILE_VCH_INT_AGGR_MASK GENMASK(11, 8) -#define GLBL_VCH_HOST_PROFILE_VCH_CMPT_MASK GENMASK(7, 4) -#define GLBL_VCH_HOST_PROFILE_VCH_C2H_PLD_MASK GENMASK(3, 0) -#define EQDMA_GLBL_BRIDGE_HOST_PROFILE_ADDR 0x308 -#define GLBL_BRIDGE_HOST_PROFILE_RSVD_1_MASK GENMASK(31, 4) -#define GLBL_BRIDGE_HOST_PROFILE_BDGID_MASK GENMASK(3, 0) -#define EQDMA_AXIMM_IRQ_DEST_ADDR_ADDR 0x30c -#define AXIMM_IRQ_DEST_ADDR_ADDR_MASK GENMASK(31, 0) -#define EQDMA_FAB_ERR_LOG_ADDR 0x314 -#define FAB_ERR_LOG_RSVD_1_MASK GENMASK(31, 7) -#define FAB_ERR_LOG_SRC_MASK GENMASK(6, 0) -#define EQDMA_GLBL_REQ_ERR_STS_ADDR 0x318 -#define GLBL_REQ_ERR_STS_RSVD_1_MASK GENMASK(31, 11) -#define GLBL_REQ_ERR_STS_RC_DISCONTINUE_MASK BIT(10) -#define GLBL_REQ_ERR_STS_RC_PRTY_MASK BIT(9) -#define GLBL_REQ_ERR_STS_RC_FLR_MASK BIT(8) -#define GLBL_REQ_ERR_STS_RC_TIMEOUT_MASK BIT(7) -#define GLBL_REQ_ERR_STS_RC_INV_BCNT_MASK BIT(6) -#define GLBL_REQ_ERR_STS_RC_INV_TAG_MASK BIT(5) -#define GLBL_REQ_ERR_STS_RC_START_ADDR_MISMCH_MASK BIT(4) -#define GLBL_REQ_ERR_STS_RC_RID_TC_ATTR_MISMCH_MASK BIT(3) -#define GLBL_REQ_ERR_STS_RC_NO_DATA_MASK BIT(2) -#define GLBL_REQ_ERR_STS_RC_UR_CA_CRS_MASK BIT(1) -#define GLBL_REQ_ERR_STS_RC_POISONED_MASK BIT(0) -#define EQDMA_GLBL_REQ_ERR_MSK_ADDR 0x31C -#define GLBL_REQ_ERR_MSK_MASK GENMASK(31, 0) -#define EQDMA_GLBL_DSC_DBG_LAT0_A_ADDR 0x320 -#define GLBL_DSC_LAT0_A_LAT_MAX_MASK GENMASK(31, 16) -#define GLBL_DSC_LAT0_A_LAT_MIN_MASK GENMASK(15, 0) -#define EQDMA_GLBL_DSC_DBG_LAT1_A_ADDR 0x324 -#define GLBL_DSC_LAT1_A_RSVD_MASK GENMASK(31, 17) -#define GLBL_DSC_LAT1_A_LAT_OVF_MASK BIT(16) -#define GLBL_DSC_LAT1_A_LAT_AVG_MASK GENMASK(15, 0) -#define EQDMA_GLBL_DSC_CRD_CTR0_A_ADDR 0x328 -#define GLBL_DSC_CRD_CTR0_A_CRD_RCV_CNT_MASK GENMASK(31, 0) -#define EQDMA_GLBL_DSC_CRD_CTR1_A_ADDR 0x32C -#define GLBL_DSC_CRD_CTR1_A_CRD_RCV_CNT_MASK GENMASK(31, 0) -#define EQDMA_GLBL_DSC_CRD_CTR2_A_ADDR 0x330 -#define GLBL_DSC_CRD_CTR2_A_CRD_RCV_NRDY_CNT_MASK GENMASK(31, 0) -#define EQDMA_GLBL_DSC_CRD_CTR3_A_ADDR 0x334 -#define GLBL_DSC_CRD_CTR3_A_CRD_RCV_NRDY_CNT_MASK GENMASK(31, 0) -#define EQDMA_GLBL_DSC_IMM_CRD_CTR0_A_ADDR 0x338 -#define GLBL_DSC_IMM_CRD_CTR0_A_RCV_CNT_MASK GENMASK(31, 0) -#define EQDMA_GLBL_DSC_IMM_CRD_CTR1_A_ADDR 0x33C -#define GLBL_DSC_IMM_CRD_CTR1_A_RCV_CNT_MASK GENMASK(31, 0) -#define EQDMA_GLBL_DSC_IMM_CRD_CTR2_A_ADDR 0x340 -#define GLBL_DSC_IMM_CRD_CTR2_A_RCV_NRDY_CNT_MASK GENMASK(31, 0) -#define EQDMA_GLBL_DSC_IMM_CRD_CTR3_A_ADDR 0x344 -#define GLBL_DSC_IMM_CRD_CTR3_A_RCV_NRDY_CNT_MASK GENMASK(31, 0) -#define EQDMA_GLBL_DSC_H2C_OUT_CTR0_A_ADDR 0x348 -#define GLBL_DSC_H2C_OUT_CTR0_A_H2CVLD_CNT_MASK GENMASK(31, 0) -#define EQDMA_GLBL_DSC_H2C_OUT_CTR1_A_ADDR 0x34C -#define GLBL_DSC_H2C_OUT_CTR1_A_H2CVLD_CNT_MASK GENMASK(31, 0) -#define EQDMA_GLBL_DSC_H2C_OUT_CTR2_A_ADDR 0x350 -#define GLBL_DSC_H2C_OUT_CTR2_A_H2CVLD_NRDY_CNT_MASK GENMASK(31, 0) -#define EQDMA_GLBL_DSC_H2C_OUT_CTR3_A_ADDR 0x354 -#define GLBL_DSC_H2C_OUT_CTR3_A_H2CVLD_NRDY_CNT_MASK GENMASK(31, 0) -#define EQDMA_GLBL_DSC_C2H_OUT_CTR0_A_ADDR 0x358 -#define GLBL_DSC_C2H_OUT_CTR0_A_C2HVLD_CNT_MASK GENMASK(31, 0) -#define EQDMA_GLBL_DSC_C2H_OUT_CTR1_A_ADDR 0x35C -#define GLBL_DSC_C2H_OUT_CTR1_A_C2HVLD_CNT_MASK GENMASK(31, 0) -#define EQDMA_GLBL_DSC_C2H_OUT_CTR2_A_ADDR 0x360 -#define GLBL_DSC_C2H_OUT_CTR2_A_C2HVLD_NRDY_CNT_MASK GENMASK(31, 0) -#define EQDMA_GLBL_DSC_C2H_OUT_CTR3_A_ADDR 0x364 -#define GLBL_DSC_C2H_OUT_CTR3_A_C2HVLD_NRDY_CNT_MASK GENMASK(31, 0) -#define EQDMA_T_ADDR 0x368 -#define T_USER_CTR_MAX_MASK GENMASK(31, 0) -#define EQDMA_GLBL_PERF_CNTR_CTL_A1_ADDR 0x36C -#define GLBL_PERF_CNTR_CTL_A1_RSVD_MASK GENMASK(31, 18) -#define GLBL_PERF_CNTR_CTL_A1_USER_CTR_CLEAR_MASK BIT(17) -#define GLBL_PERF_CNTR_CTL_A1_USER_CTR_READ_MASK BIT(16) -#define GLBL_PERF_CNTR_CTL_A1_USER_CTR_MAX_MASK GENMASK(15, 0) -#define EQDMA_GLBL_FREE_CNT_A0_ADDR 0x370 -#define GLBL_FREE_CNT_A0_S_MASK GENMASK(31, 0) -#define EQDMA_GLBL_FREE_CNT_A1_ADDR 0x374 -#define GLBL_FREE_CNT_A1_RSVD_MASK GENMASK(31, 16) -#define GLBL_FREE_CNT_A1_S_MASK GENMASK(15, 0) -#define EQDMA_GLBL_AXIS_H2C_CNT_A0_ADDR 0x378 -#define GLBL_AXIS_H2C_CNT_A0_MPKT_CNTS_MASK GENMASK(31, 0) -#define EQDMA_GLBL_AXIS_H2C_CNT_A1_ADDR 0x37C -#define GLBL_AXIS_H2C_CNT_A1_MIDLE_CNTS_MASK GENMASK(15, 0) -#define GLBL_AXIS_H2C_CNT_A1_MPKT_CNTS_MASK GENMASK(15, 0) -#define EQDMA_GLBL_AXIS_H2C_CNT_A2_ADDR 0x380 -#define GLBL_AXIS_H2C_CNT_A2_MIDLE_CNTS_MASK GENMASK(31, 0) -#define EQDMA_GLBL_AXIS_H2C_CNT_A3_ADDR 0x384 -#define GLBL_AXIS_H2C_CNT_A3_MACTV_CNTS_MASK GENMASK(31, 0) -#define EQDMA_GLBL_AXIS_H2C_CNT_A4_ADDR 0x388 -#define GLBL_AXIS_H2C_CNT_A4_MBUSY_CNTS_MASK GENMASK(15, 0) -#define GLBL_AXIS_H2C_CNT_A4_MACTV_CNTS_MASK GENMASK(15, 0) -#define EQDMA_GLBL_AXIS_H2C_CNT_A5_ADDR 0x38C -#define GLBL_AXIS_H2C_CNT_A5_MBUSY_CNTS_MASK GENMASK(31, 0) -#define EQDMA_GLBL_AXIS_C2H_CNT_A0_ADDR 0x390 -#define GLBL_AXIS_C2H_CNT_A0_SPKT_CNTS_MASK GENMASK(31, 0) -#define EQDMA_GLBL_AXIS_C2H_CNT_A1_ADDR 0x394 -#define GLBL_AXIS_C2H_CNT_A1_SIDLE_CNTS_MASK GENMASK(15, 0) -#define GLBL_AXIS_C2H_CNT_A1_SPKT_CNTS_MASK GENMASK(15, 0) -#define EQDMA_GLBL_AXIS_C2H_CNT_A2_ADDR 0x398 -#define GLBL_AXIS_C2H_CNT_A2_SIDLE_CNTS_MASK GENMASK(31, 0) -#define EQDMA_GLBL_AXIS_C2H_CNT_A3_ADDR 0x39C -#define GLBL_AXIS_C2H_CNT_A3_SACTV_CNTS_MASK GENMASK(31, 0) -#define EQDMA_GLBL_AXIS_C2H_CNT_A4_ADDR 0x3A0 -#define GLBL_AXIS_C2H_CNT_A4_SBUSY_CNTS_MASK GENMASK(15, 0) -#define GLBL_AXIS_C2H_CNT_A4_SACTV_CNTS_MASK GENMASK(15, 0) -#define EQDMA_GLBL_AXIS_C2H_CNT_A5_ADDR 0x3A4 -#define GLBL_AXIS_C2H_CNT_A5_SBUSY_CNTS_MASK GENMASK(31, 0) -#define EQDMA_GLBL_M_AXI_WR_CNT_A0_ADDR 0x3A8 -#define GLBL_M_AXI_WR_CNT_A0_PKT_CNTS_MASK GENMASK(31, 0) -#define EQDMA_GLBL_M_AXI_WR_CNT_A1_ADDR 0x3AC -#define GLBL_M_AXI_WR_CNT_A1_IDLE_CNTS_MASK GENMASK(15, 0) -#define GLBL_M_AXI_WR_CNT_A1_PKT_CNTS_MASK GENMASK(15, 0) -#define EQDMA_GLBL_M_AXI_WR_CNT_A2_ADDR 0x3B0 -#define GLBL_M_AXI_WR_CNT_A2_IDLE_CNTS_MASK GENMASK(31, 0) -#define EQDMA_GLBL_M_AXI_WR_CNT_A3_ADDR 0x3B4 -#define GLBL_M_AXI_WR_CNT_A3_ACTV_CNTS_MASK GENMASK(31, 0) -#define EQDMA_GLBL_M_AXI_WR_CNT_A4_ADDR 0x3B8 -#define GLBL_M_AXI_WR_CNT_A4_BUSY_CNTS_MASK GENMASK(15, 0) -#define GLBL_M_AXI_WR_CNT_A4_ACTV_CNTS_MASK GENMASK(15, 0) -#define EQDMA_GLBL_M_AXI_WR_CNT_A5_ADDR 0x3BC -#define GLBL_M_AXI_WR_CNT_A5_BUSY_CNTS_MASK GENMASK(31, 0) -#define EQDMA_GLBL_M_AXI_RD_CNT_A0_ADDR 0x3C0 -#define GLBL_M_AXI_RD_CNT_A0_PKT_CNTS_MASK GENMASK(31, 0) -#define EQDMA_GLBL_M_AXI_RD_CNT_A1_ADDR 0x3C4 -#define GLBL_M_AXI_RD_CNT_A1_IDLE_CNTS_MASK GENMASK(15, 0) -#define GLBL_M_AXI_RD_CNT_A1_PKT_CNTS_MASK GENMASK(15, 0) -#define EQDMA_GLBL_M_AXI_RD_CNT_A2_ADDR 0x3C8 -#define GLBL_M_AXI_RD_CNT_A2_IDLE_CNTS_MASK GENMASK(31, 0) -#define EQDMA_GLBL_M_AXI_RD_CNT_A3_ADDR 0x3CC -#define GLBL_M_AXI_RD_CNT_A3_ACTV_CNTS_MASK GENMASK(31, 0) -#define EQDMA_GLBL_M_AXI_RD_CNT_A4_ADDR 0x3D0 -#define GLBL_M_AXI_RD_CNT_A4_BUSY_CNTS_MASK GENMASK(15, 0) -#define GLBL_M_AXI_RD_CNT_A4_ACTV_CNTS_MASK GENMASK(15, 0) -#define EQDMA_GLBL_M_AXI_RD_CNT_A5_ADDR 0x3D4 -#define GLBL_M_AXI_RD_CNT_A5_BUSY_CNTS_MASK GENMASK(31, 0) -#define EQDMA_GLBL_M_AXIB_WR_CNT_A0_ADDR 0x3D8 -#define GLBL_M_AXIB_WR_CNT_A0_PKT_CNTS_MASK GENMASK(31, 0) -#define EQDMA_GLBL_M_AXIB_WR_CNT_A1_ADDR 0x3DC -#define GLBL_M_AXIB_WR_CNT_A1_IDLE_CNTS_MASK GENMASK(15, 0) -#define GLBL_M_AXIB_WR_CNT_A1_PKT_CNTS_MASK GENMASK(15, 0) -#define EQDMA_GLBL_M_AXIB_WR_CNT_A2_ADDR 0x3E0 -#define GLBL_M_AXIB_WR_CNT_A2_IDLE_CNTS_MASK GENMASK(31, 0) -#define EQDMA_GLBL_M_AXIB_WR_CNT_A3_ADDR 0x3E4 -#define GLBL_M_AXIB_WR_CNT_A3_ACTV_CNTS_MASK GENMASK(31, 0) -#define EQDMA_GLBL_M_AXIB_WR_CNT_A4_ADDR 0x3E8 -#define GLBL_M_AXIB_WR_CNT_A4_BUSY_CNTS_MASK GENMASK(15, 0) -#define GLBL_M_AXIB_WR_CNT_A4_ACTV_CNTS_MASK GENMASK(15, 0) -#define EQDMA_GLBL_M_AXIB_WR_CNT_A5_ADDR 0x3EC -#define GLBL_M_AXIB_WR_CNT_A5_BUSY_CNTS_MASK GENMASK(31, 0) -#define EQDMA_GLBL_M_AXIB_RD_CNT_A0_ADDR 0x3F0 -#define GLBL_M_AXIB_RD_CNT_A0_PKT_CNTS_MASK GENMASK(31, 0) -#define EQDMA_GLBL_M_AXIB_RD_CNT_A1_ADDR 0x3F4 -#define GLBL_M_AXIB_RD_CNT_A1_IDLE_CNTS_MASK GENMASK(15, 0) -#define GLBL_M_AXIB_RD_CNT_A1_PKT_CNTS_MASK GENMASK(15, 0) -#define EQDMA_GLBL_M_AXIB_RD_CNT_A2_ADDR 0x3F8 -#define GLBL_M_AXIB_RD_CNT_A2_IDLE_CNTS_MASK GENMASK(31, 0) -#define EQDMA_GLBL_M_AXIB_RD_CNT_A3_ADDR 0x3FC -#define GLBL_M_AXIB_RD_CNT_A3_ACTV_CNTS_MASK GENMASK(31, 0) -#define EQDMA_GLBL_M_AXIB_RD_CNT_A4_ADDR 0x400 -#define GLBL_M_AXIB_RD_CNT_A4_BUSY_CNTS_MASK GENMASK(15, 0) -#define GLBL_M_AXIB_RD_CNT_A4_ACTV_CNTS_MASK GENMASK(15, 0) -#define EQDMA_GLBL_M_AXIB_RD_CNT_A5_ADDR 0x404 -#define GLBL_M_AXIB_RD_CNT_A5_BUSY_CNTS_MASK GENMASK(31, 0) -#define EQDMA_GLBL_S_AXI_WR_CNT_A0_ADDR 0x408 -#define GLBL_S_AXI_WR_CNT_A0_PKT_CNTS_MASK GENMASK(31, 0) -#define EQDMA_GLBL_S_AXI_WR_CNT_A1_ADDR 0x40C -#define GLBL_S_AXI_WR_CNT_A1_IDLE_CNTS_MASK GENMASK(15, 0) -#define GLBL_S_AXI_WR_CNT_A1_PKT_CNTS_MASK GENMASK(15, 0) -#define EQDMA_GLBL_S_AXI_WR_CNT_A2_ADDR 0x410 -#define GLBL_S_AXI_WR_CNT_A2_IDLE_CNTS_MASK GENMASK(31, 0) -#define EQDMA_GLBL_S_AXI_WR_CNT_A3_ADDR 0x414 -#define GLBL_S_AXI_WR_CNT_A3_ACTV_CNTS_MASK GENMASK(31, 0) -#define EQDMA_GLBL_S_AXI_WR_CNT_A4_ADDR 0x418 -#define GLBL_S_AXI_WR_CNT_A4_BUSY_CNTS_MASK GENMASK(15, 0) -#define GLBL_S_AXI_WR_CNT_A4_ACTV_CNTS_MASK GENMASK(15, 0) -#define EQDMA_GLBL_S_AXI_WR_CNT_A5_ADDR 0x41C -#define GLBL_S_AXI_WR_CNT_A5_BUSY_CNTS_MASK GENMASK(31, 0) -#define EQDMA_GLBL_S_AXI_RD_CNT_A0_ADDR 0x420 -#define GLBL_S_AXI_RD_CNT_A0_PKT_CNTS_MASK GENMASK(31, 0) -#define EQDMA_GLBL_S_AXI_RD_CNT_A1_ADDR 0x424 -#define GLBL_S_AXI_RD_CNT_A1_IDLE_CNTS_MASK GENMASK(15, 0) -#define GLBL_S_AXI_RD_CNT_A1_PKT_CNTS_MASK GENMASK(15, 0) -#define EQDMA_GLBL_S_AXI_RD_CNT_A2_ADDR 0x428 -#define GLBL_S_AXI_RD_CNT_A2_IDLE_CNTS_MASK GENMASK(31, 0) -#define EQDMA_GLBL_S_AXI_RD_CNT_A3_ADDR 0x42C -#define GLBL_S_AXI_RD_CNT_A3_ACTV_CNTS_MASK GENMASK(31, 0) -#define EQDMA_GLBL_S_AXI_RD_CNT_A4_ADDR 0x430 -#define GLBL_S_AXI_RD_CNT_A4_BUSY_CNTS_MASK GENMASK(15, 0) -#define GLBL_S_AXI_RD_CNT_A4_ACTV_CNTS_MASK GENMASK(15, 0) -#define EQDMA_GLBL_S_AXI_RD_CNT_A5_ADDR 0x434 -#define GLBL_S_AXI_RD_CNT_A5_BUSY_CNTS_MASK GENMASK(31, 0) -#define EQDMA_GLBL_S_AXIS_CMP_CNT_A0_ADDR 0x438 -#define GLBL_S_AXIS_CMP_CNT_A0_PKT_CNTS_MASK GENMASK(31, 0) -#define EQDMA_GLBL_S_AXIS_CMP_CNT_A1_ADDR 0x43C -#define GLBL_S_AXIS_CMP_CNT_A1_IDLE_CNTS_MASK GENMASK(15, 0) -#define GLBL_S_AXIS_CMP_CNT_A1_PKT_CNTS_MASK GENMASK(15, 0) -#define EQDMA_GLBL_S_AXIS_CMP_CNT_A2_ADDR 0x440 -#define GLBL_S_AXIS_CMP_CNT_A2_IDLE_CNTS_MASK GENMASK(31, 0) -#define EQDMA_GLBL_S_AXIS_CMP_CNT_A3_ADDR 0x444 -#define GLBL_S_AXIS_CMP_CNT_A3_ACTV_CNTS_MASK GENMASK(31, 0) -#define EQDMA_GLBL_S_AXIS_CMP_CNT_A4_ADDR 0x448 -#define GLBL_S_AXIS_CMP_CNT_A4_BUSY_CNTS_MASK GENMASK(15, 0) -#define GLBL_S_AXIS_CMP_CNT_A4_ACTV_CNTS_MASK GENMASK(15, 0) -#define EQDMA_GLBL_S_AXIS_CMP_CNT_A5_ADDR 0x44C -#define GLBL_S_AXIS_CMP_CNT_A5_BUSY_CNTS_MASK GENMASK(31, 0) -#define EQDMA_IND_CTXT_DATA_ADDR 0x804 -#define IND_CTXT_DATA_DATA_MASK GENMASK(31, 0) -#define EQDMA_IND_CTXT_MASK_ADDR 0x824 -#define IND_CTXT_MASK GENMASK(31, 0) -#define EQDMA_IND_CTXT_CMD_ADDR 0x844 -#define IND_CTXT_CMD_RSVD_1_MASK GENMASK(31, 20) -#define IND_CTXT_CMD_QID_MASK GENMASK(19, 7) -#define IND_CTXT_CMD_OP_MASK GENMASK(6, 5) -#define IND_CTXT_CMD_SEL_MASK GENMASK(4, 1) -#define IND_CTXT_CMD_BUSY_MASK BIT(0) -#define EQDMA_C2H_TIMER_CNT_ADDR 0xA00 -#define C2H_TIMER_CNT_RSVD_1_MASK GENMASK(31, 16) -#define C2H_TIMER_CNT_MASK GENMASK(15, 0) -#define EQDMA_C2H_CNT_TH_ADDR 0xA40 -#define C2H_CNT_TH_RSVD_1_MASK GENMASK(31, 16) -#define C2H_CNT_TH_THESHOLD_CNT_MASK GENMASK(15, 0) -#define EQDMA_C2H_PFCH_CFG_1_ADDR 0xA80 -#define C2H_PFCH_CFG_1_EVT_QCNT_TH_MASK GENMASK(31, 16) -#define C2H_PFCH_CFG_1_QCNT_MASK GENMASK(15, 0) -#define EQDMA_C2H_PFCH_CFG_2_ADDR 0xA84 -#define C2H_PFCH_CFG_2_FENCE_MASK BIT(31) -#define C2H_PFCH_CFG_2_RSVD_MASK GENMASK(30, 29) -#define C2H_PFCH_CFG_2_VAR_DESC_NO_DROP_MASK BIT(28) -#define C2H_PFCH_CFG_2_LL_SZ_TH_MASK GENMASK(27, 12) -#define C2H_PFCH_CFG_2_VAR_DESC_NUM_MASK GENMASK(11, 6) -#define C2H_PFCH_CFG_2_NUM_MASK GENMASK(5, 0) -#define EQDMA_C2H_STAT_S_AXIS_C2H_ACCEPTED_ADDR 0xA88 -#define C2H_STAT_S_AXIS_C2H_ACCEPTED_MASK GENMASK(31, 0) -#define EQDMA_C2H_STAT_S_AXIS_WRB_ACCEPTED_ADDR 0xA8C -#define C2H_STAT_S_AXIS_WRB_ACCEPTED_MASK GENMASK(31, 0) -#define EQDMA_C2H_STAT_DESC_RSP_PKT_ACCEPTED_ADDR 0xA90 -#define C2H_STAT_DESC_RSP_PKT_ACCEPTED_D_MASK GENMASK(31, 0) -#define EQDMA_C2H_STAT_AXIS_PKG_CMP_ADDR 0xA94 -#define C2H_STAT_AXIS_PKG_CMP_MASK GENMASK(31, 0) -#define EQDMA_C2H_STAT_DESC_RSP_ACCEPTED_ADDR 0xA98 -#define C2H_STAT_DESC_RSP_ACCEPTED_D_MASK GENMASK(31, 0) -#define EQDMA_C2H_STAT_DESC_RSP_CMP_ADDR 0xA9C -#define C2H_STAT_DESC_RSP_CMP_D_MASK GENMASK(31, 0) -#define EQDMA_C2H_STAT_WRQ_OUT_ADDR 0xAA0 -#define C2H_STAT_WRQ_OUT_MASK GENMASK(31, 0) -#define EQDMA_C2H_STAT_WPL_REN_ACCEPTED_ADDR 0xAA4 -#define C2H_STAT_WPL_REN_ACCEPTED_MASK GENMASK(31, 0) -#define EQDMA_C2H_STAT_TOTAL_WRQ_LEN_ADDR 0xAA8 -#define C2H_STAT_TOTAL_WRQ_LEN_MASK GENMASK(31, 0) -#define EQDMA_C2H_STAT_TOTAL_WPL_LEN_ADDR 0xAAC -#define C2H_STAT_TOTAL_WPL_LEN_MASK GENMASK(31, 0) -#define EQDMA_C2H_BUF_SZ_ADDR 0xAB0 -#define C2H_BUF_SZ_IZE_MASK GENMASK(31, 0) -#define EQDMA_C2H_ERR_STAT_ADDR 0xAF0 -#define C2H_ERR_STAT_RSVD_1_MASK GENMASK(31, 21) -#define C2H_ERR_STAT_WRB_PORT_ID_ERR_MASK BIT(20) -#define C2H_ERR_STAT_HDR_PAR_ERR_MASK BIT(19) -#define C2H_ERR_STAT_HDR_ECC_COR_ERR_MASK BIT(18) -#define C2H_ERR_STAT_HDR_ECC_UNC_ERR_MASK BIT(17) -#define C2H_ERR_STAT_AVL_RING_DSC_ERR_MASK BIT(16) -#define C2H_ERR_STAT_WRB_PRTY_ERR_MASK BIT(15) -#define C2H_ERR_STAT_WRB_CIDX_ERR_MASK BIT(14) -#define C2H_ERR_STAT_WRB_QFULL_ERR_MASK BIT(13) -#define C2H_ERR_STAT_WRB_INV_Q_ERR_MASK BIT(12) -#define C2H_ERR_STAT_RSVD_2_MASK BIT(11) -#define C2H_ERR_STAT_PORT_ID_CTXT_MISMATCH_MASK BIT(10) -#define C2H_ERR_STAT_ERR_DESC_CNT_MASK BIT(9) -#define C2H_ERR_STAT_RSVD_3_MASK BIT(8) -#define C2H_ERR_STAT_MSI_INT_FAIL_MASK BIT(7) -#define C2H_ERR_STAT_ENG_WPL_DATA_PAR_ERR_MASK BIT(6) -#define C2H_ERR_STAT_RSVD_4_MASK BIT(5) -#define C2H_ERR_STAT_DESC_RSP_ERR_MASK BIT(4) -#define C2H_ERR_STAT_QID_MISMATCH_MASK BIT(3) -#define C2H_ERR_STAT_SH_CMPT_DSC_ERR_MASK BIT(2) -#define C2H_ERR_STAT_LEN_MISMATCH_MASK BIT(1) -#define C2H_ERR_STAT_MTY_MISMATCH_MASK BIT(0) -#define EQDMA_C2H_ERR_MASK_ADDR 0xAF4 -#define C2H_ERR_EN_MASK GENMASK(31, 0) -#define EQDMA_C2H_FATAL_ERR_STAT_ADDR 0xAF8 -#define C2H_FATAL_ERR_STAT_RSVD_1_MASK GENMASK(31, 21) -#define C2H_FATAL_ERR_STAT_HDR_ECC_UNC_ERR_MASK BIT(20) -#define C2H_FATAL_ERR_STAT_AVL_RING_FIFO_RAM_RDBE_MASK BIT(19) -#define C2H_FATAL_ERR_STAT_WPL_DATA_PAR_ERR_MASK BIT(18) -#define C2H_FATAL_ERR_STAT_PLD_FIFO_RAM_RDBE_MASK BIT(17) -#define C2H_FATAL_ERR_STAT_QID_FIFO_RAM_RDBE_MASK BIT(16) -#define C2H_FATAL_ERR_STAT_CMPT_FIFO_RAM_RDBE_MASK BIT(15) -#define C2H_FATAL_ERR_STAT_WRB_COAL_DATA_RAM_RDBE_MASK BIT(14) -#define C2H_FATAL_ERR_STAT_RESERVED2_MASK BIT(13) -#define C2H_FATAL_ERR_STAT_INT_CTXT_RAM_RDBE_MASK BIT(12) -#define C2H_FATAL_ERR_STAT_DESC_REQ_FIFO_RAM_RDBE_MASK BIT(11) -#define C2H_FATAL_ERR_STAT_PFCH_CTXT_RAM_RDBE_MASK BIT(10) -#define C2H_FATAL_ERR_STAT_WRB_CTXT_RAM_RDBE_MASK BIT(9) -#define C2H_FATAL_ERR_STAT_PFCH_LL_RAM_RDBE_MASK BIT(8) -#define C2H_FATAL_ERR_STAT_TIMER_FIFO_RAM_RDBE_MASK GENMASK(7, 4) -#define C2H_FATAL_ERR_STAT_QID_MISMATCH_MASK BIT(3) -#define C2H_FATAL_ERR_STAT_RESERVED1_MASK BIT(2) -#define C2H_FATAL_ERR_STAT_LEN_MISMATCH_MASK BIT(1) -#define C2H_FATAL_ERR_STAT_MTY_MISMATCH_MASK BIT(0) -#define EQDMA_C2H_FATAL_ERR_MASK_ADDR 0xAFC -#define C2H_FATAL_ERR_C2HEN_MASK GENMASK(31, 0) -#define EQDMA_C2H_FATAL_ERR_ENABLE_ADDR 0xB00 -#define C2H_FATAL_ERR_ENABLE_RSVD_1_MASK GENMASK(31, 2) -#define C2H_FATAL_ERR_ENABLE_WPL_PAR_INV_MASK BIT(1) -#define C2H_FATAL_ERR_ENABLE_WRQ_DIS_MASK BIT(0) -#define EQDMA_GLBL_ERR_INT_ADDR 0xB04 -#define GLBL_ERR_INT_RSVD_1_MASK GENMASK(31, 30) -#define GLBL_ERR_INT_HOST_ID_MASK GENMASK(29, 26) -#define GLBL_ERR_INT_DIS_INTR_ON_VF_MASK BIT(25) -#define GLBL_ERR_INT_ARM_MASK BIT(24) -#define GLBL_ERR_INT_EN_COAL_MASK BIT(23) -#define GLBL_ERR_INT_VEC_MASK GENMASK(22, 12) -#define GLBL_ERR_INT_FUNC_MASK GENMASK(11, 0) -#define EQDMA_C2H_PFCH_CFG_ADDR 0xB08 -#define C2H_PFCH_CFG_EVTFL_TH_MASK GENMASK(31, 16) -#define C2H_PFCH_CFG_FL_TH_MASK GENMASK(15, 0) -#define EQDMA_C2H_INT_TIMER_TICK_ADDR 0xB0C -#define C2H_INT_TIMER_TICK_MASK GENMASK(31, 0) -#define EQDMA_C2H_STAT_DESC_RSP_DROP_ACCEPTED_ADDR 0xB10 -#define C2H_STAT_DESC_RSP_DROP_ACCEPTED_D_MASK GENMASK(31, 0) -#define EQDMA_C2H_STAT_DESC_RSP_ERR_ACCEPTED_ADDR 0xB14 -#define C2H_STAT_DESC_RSP_ERR_ACCEPTED_D_MASK GENMASK(31, 0) -#define EQDMA_C2H_STAT_DESC_REQ_ADDR 0xB18 -#define C2H_STAT_DESC_REQ_MASK GENMASK(31, 0) -#define EQDMA_C2H_STAT_DBG_DMA_ENG_0_ADDR 0xB1C -#define C2H_STAT_DMA_ENG_0_S_AXIS_C2H_TVALID_MASK BIT(31) -#define C2H_STAT_DMA_ENG_0_S_AXIS_C2H_TREADY_MASK BIT(30) -#define C2H_STAT_DMA_ENG_0_S_AXIS_WRB_TVALID_MASK GENMASK(29, 27) -#define C2H_STAT_DMA_ENG_0_S_AXIS_WRB_TREADY_MASK GENMASK(26, 24) -#define C2H_STAT_DMA_ENG_0_PLD_FIFO_IN_RDY_MASK BIT(23) -#define C2H_STAT_DMA_ENG_0_QID_FIFO_IN_RDY_MASK BIT(22) -#define C2H_STAT_DMA_ENG_0_ARB_FIFO_OUT_VLD_MASK BIT(21) -#define C2H_STAT_DMA_ENG_0_ARB_FIFO_OUT_QID_MASK GENMASK(20, 9) -#define C2H_STAT_DMA_ENG_0_WRB_FIFO_IN_RDY_MASK BIT(8) -#define C2H_STAT_DMA_ENG_0_WRB_FIFO_OUT_CNT_MASK GENMASK(7, 5) -#define C2H_STAT_DMA_ENG_0_WRB_SM_CS_MASK BIT(4) -#define C2H_STAT_DMA_ENG_0_MAIN_SM_CS_MASK GENMASK(3, 0) -#define EQDMA_C2H_STAT_DBG_DMA_ENG_1_ADDR 0xB20 -#define C2H_STAT_DMA_ENG_1_WRB_USER_0_CMPT_TYPE_MASK GENMASK(31, 30) -#define C2H_STAT_DMA_ENG_1_DESC_RSP_FIFO_OUT_VLD_MASK GENMASK(29, 29) -#define C2H_STAT_DMA_ENG_1_QID_FIFO_OUT_CNT_MASK GENMASK(28, 18) -#define C2H_STAT_DMA_ENG_1_PLD_FIFO_OUT_CNT_MASK GENMASK(17, 7) -#define C2H_STAT_DMA_ENG_1_PLD_ST_FIFO_CNT_MASK GENMASK(6, 0) -#define EQDMA_C2H_STAT_DBG_DMA_ENG_2_ADDR 0xB24 -#define C2H_STAT_DMA_ENG_2_WRB_USER_1_CMPT_TYPE_MASK GENMASK(31, 30) -#define C2H_STAT_DMA_ENG_2_DESC_RSP_FIFO_OUT_VLD_1_MASK GENMASK(29, 29) -#define C2H_STAT_DMA_ENG_2_QID_FIFO_OUT_CNT_1_MASK GENMASK(28, 18) -#define C2H_STAT_DMA_ENG_2_PLD_FIFO_OUT_CNT_1_MASK GENMASK(17, 7) -#define C2H_STAT_DMA_ENG_2_PLD_ST_FIFO_CNT_1_MASK GENMASK(6, 0) -#define EQDMA_C2H_STAT_DBG_DMA_ENG_3_ADDR 0xB28 -#define C2H_STAT_DMA_ENG_3_QID_FIFO_OUT_DAT_HAS_CMPT_MASK BIT(31) -#define C2H_STAT_DMA_ENG_3_QID_FIFO_OUT_DAT_MARKER_MASK BIT(30) -#define C2H_STAT_DMA_ENG_3_QID_FIFO_OUT_DAT_DROP_REQ_MASK BIT(29) -#define C2H_STAT_DMA_ENG_3_QID_FIFO_OUT_DAT_QID_MASK GENMASK(28, 17) -#define C2H_STAT_DMA_ENG_3_WR_HDR_FIFO_OUT_CNT_MASK GENMASK(16, 12) -#define C2H_STAT_DMA_ENG_3_QID_FIFO_OUT_VLD_MASK BIT(11) -#define C2H_STAT_DMA_ENG_3_PLD_FIFO_OUT_VLD_MASK BIT(10) -#define C2H_STAT_DMA_ENG_3_PLD_ST_FIFO_OUT_VLD_MASK BIT(9) -#define C2H_STAT_DMA_ENG_3_PLD_ST_FIFO_OUT_DATA_EOP_MASK BIT(8) -#define C2H_STAT_DMA_ENG_3_PLD_ST_FIFO_OUT_DATA_AVL_IDX_ENABLE_MASK BIT(7) -#define C2H_STAT_DMA_ENG_3_PLD_ST_FIFO_OUT_DATA_DROP_MASK BIT(6) -#define C2H_STAT_DMA_ENG_3_PLD_ST_FIFO_OUT_DATA_ERR_MASK BIT(5) -#define C2H_STAT_DMA_ENG_3_DESC_CNT_FIFO_IN_RDY_MASK BIT(4) -#define C2H_STAT_DMA_ENG_3_DESC_RSP_FIFO_IN_RDY_MASK BIT(3) -#define C2H_STAT_DMA_ENG_3_PLD_PKT_ID_LARGER_MASK BIT(2) -#define C2H_STAT_DMA_ENG_3_WCP_FIFO_IN_RDY_MASK BIT(1) -#define C2H_STAT_DMA_ENG_3_PLD_ST_FIFO_IN_RDY_MASK BIT(0) -#define EQDMA_C2H_DBG_PFCH_ERR_CTXT_ADDR 0xB2C -#define C2H_PFCH_ERR_CTXT_RSVD_1_MASK GENMASK(31, 14) -#define C2H_PFCH_ERR_CTXT_ERR_STAT_MASK BIT(13) -#define C2H_PFCH_ERR_CTXT_CMD_WR_MASK BIT(12) -#define C2H_PFCH_ERR_CTXT_QID_MASK GENMASK(11, 1) -#define C2H_PFCH_ERR_CTXT_DONE_MASK BIT(0) -#define EQDMA_C2H_FIRST_ERR_QID_ADDR 0xB30 -#define C2H_FIRST_ERR_QID_RSVD_1_MASK GENMASK(31, 21) -#define C2H_FIRST_ERR_QID_ERR_TYPE_MASK GENMASK(20, 16) -#define C2H_FIRST_ERR_QID_RSVD_MASK GENMASK(15, 13) -#define C2H_FIRST_ERR_QID_QID_MASK GENMASK(12, 0) -#define EQDMA_STAT_NUM_WRB_IN_ADDR 0xB34 -#define STAT_NUM_WRB_IN_RSVD_1_MASK GENMASK(31, 16) -#define STAT_NUM_WRB_IN_WRB_CNT_MASK GENMASK(15, 0) -#define EQDMA_STAT_NUM_WRB_OUT_ADDR 0xB38 -#define STAT_NUM_WRB_OUT_RSVD_1_MASK GENMASK(31, 16) -#define STAT_NUM_WRB_OUT_WRB_CNT_MASK GENMASK(15, 0) -#define EQDMA_STAT_NUM_WRB_DRP_ADDR 0xB3C -#define STAT_NUM_WRB_DRP_RSVD_1_MASK GENMASK(31, 16) -#define STAT_NUM_WRB_DRP_WRB_CNT_MASK GENMASK(15, 0) -#define EQDMA_STAT_NUM_STAT_DESC_OUT_ADDR 0xB40 -#define STAT_NUM_STAT_DESC_OUT_RSVD_1_MASK GENMASK(31, 16) -#define STAT_NUM_STAT_DESC_OUT_CNT_MASK GENMASK(15, 0) -#define EQDMA_STAT_NUM_DSC_CRDT_SENT_ADDR 0xB44 -#define STAT_NUM_DSC_CRDT_SENT_RSVD_1_MASK GENMASK(31, 16) -#define STAT_NUM_DSC_CRDT_SENT_CNT_MASK GENMASK(15, 0) -#define EQDMA_STAT_NUM_FCH_DSC_RCVD_ADDR 0xB48 -#define STAT_NUM_FCH_DSC_RCVD_RSVD_1_MASK GENMASK(31, 16) -#define STAT_NUM_FCH_DSC_RCVD_DSC_CNT_MASK GENMASK(15, 0) -#define EQDMA_STAT_NUM_BYP_DSC_RCVD_ADDR 0xB4C -#define STAT_NUM_BYP_DSC_RCVD_RSVD_1_MASK GENMASK(31, 11) -#define STAT_NUM_BYP_DSC_RCVD_DSC_CNT_MASK GENMASK(10, 0) -#define EQDMA_C2H_WRB_COAL_CFG_ADDR 0xB50 -#define C2H_WRB_COAL_CFG_MAX_BUF_SZ_MASK GENMASK(31, 26) -#define C2H_WRB_COAL_CFG_TICK_VAL_MASK GENMASK(25, 14) -#define C2H_WRB_COAL_CFG_TICK_CNT_MASK GENMASK(13, 2) -#define C2H_WRB_COAL_CFG_SET_GLB_FLUSH_MASK BIT(1) -#define C2H_WRB_COAL_CFG_DONE_GLB_FLUSH_MASK BIT(0) -#define EQDMA_C2H_INTR_H2C_REQ_ADDR 0xB54 -#define C2H_INTR_H2C_REQ_RSVD_1_MASK GENMASK(31, 18) -#define C2H_INTR_H2C_REQ_CNT_MASK GENMASK(17, 0) -#define EQDMA_C2H_INTR_C2H_MM_REQ_ADDR 0xB58 -#define C2H_INTR_C2H_MM_REQ_RSVD_1_MASK GENMASK(31, 18) -#define C2H_INTR_C2H_MM_REQ_CNT_MASK GENMASK(17, 0) -#define EQDMA_C2H_INTR_ERR_INT_REQ_ADDR 0xB5C -#define C2H_INTR_ERR_INT_REQ_RSVD_1_MASK GENMASK(31, 18) -#define C2H_INTR_ERR_INT_REQ_CNT_MASK GENMASK(17, 0) -#define EQDMA_C2H_INTR_C2H_ST_REQ_ADDR 0xB60 -#define C2H_INTR_C2H_ST_REQ_RSVD_1_MASK GENMASK(31, 18) -#define C2H_INTR_C2H_ST_REQ_CNT_MASK GENMASK(17, 0) -#define EQDMA_C2H_INTR_H2C_ERR_C2H_MM_MSIX_ACK_ADDR 0xB64 -#define C2H_INTR_H2C_ERR_C2H_MM_MSIX_ACK_RSVD_1_MASK GENMASK(31, 18) -#define C2H_INTR_H2C_ERR_C2H_MM_MSIX_ACK_CNT_MASK GENMASK(17, 0) -#define EQDMA_C2H_INTR_H2C_ERR_C2H_MM_MSIX_FAIL_ADDR 0xB68 -#define C2H_INTR_H2C_ERR_C2H_MM_MSIX_FAIL_RSVD_1_MASK GENMASK(31, 18) -#define C2H_INTR_H2C_ERR_C2H_MM_MSIX_FAIL_CNT_MASK GENMASK(17, 0) -#define EQDMA_C2H_INTR_H2C_ERR_C2H_MM_MSIX_NO_MSIX_ADDR 0xB6C -#define C2H_INTR_H2C_ERR_C2H_MM_MSIX_NO_MSIX_RSVD_1_MASK GENMASK(31, 18) -#define C2H_INTR_H2C_ERR_C2H_MM_MSIX_NO_MSIX_CNT_MASK GENMASK(17, 0) -#define EQDMA_C2H_INTR_H2C_ERR_C2H_MM_CTXT_INVAL_ADDR 0xB70 -#define C2H_INTR_H2C_ERR_C2H_MM_CTXT_INVAL_RSVD_1_MASK GENMASK(31, 18) -#define C2H_INTR_H2C_ERR_C2H_MM_CTXT_INVAL_CNT_MASK GENMASK(17, 0) -#define EQDMA_C2H_INTR_C2H_ST_MSIX_ACK_ADDR 0xB74 -#define C2H_INTR_C2H_ST_MSIX_ACK_RSVD_1_MASK GENMASK(31, 18) -#define C2H_INTR_C2H_ST_MSIX_ACK_CNT_MASK GENMASK(17, 0) -#define EQDMA_C2H_INTR_C2H_ST_MSIX_FAIL_ADDR 0xB78 -#define C2H_INTR_C2H_ST_MSIX_FAIL_RSVD_1_MASK GENMASK(31, 18) -#define C2H_INTR_C2H_ST_MSIX_FAIL_CNT_MASK GENMASK(17, 0) -#define EQDMA_C2H_INTR_C2H_ST_NO_MSIX_ADDR 0xB7C -#define C2H_INTR_C2H_ST_NO_MSIX_RSVD_1_MASK GENMASK(31, 18) -#define C2H_INTR_C2H_ST_NO_MSIX_CNT_MASK GENMASK(17, 0) -#define EQDMA_C2H_INTR_C2H_ST_CTXT_INVAL_ADDR 0xB80 -#define C2H_INTR_C2H_ST_CTXT_INVAL_RSVD_1_MASK GENMASK(31, 18) -#define C2H_INTR_C2H_ST_CTXT_INVAL_CNT_MASK GENMASK(17, 0) -#define EQDMA_C2H_STAT_WR_CMP_ADDR 0xB84 -#define C2H_STAT_WR_CMP_RSVD_1_MASK GENMASK(31, 18) -#define C2H_STAT_WR_CMP_CNT_MASK GENMASK(17, 0) -#define EQDMA_C2H_STAT_DBG_DMA_ENG_4_ADDR 0xB88 -#define C2H_STAT_DMA_ENG_4_QID_FIFO_OUT_DAT_HAS_CMPT_1_MASK BIT(31) -#define C2H_STAT_DMA_ENG_4_QID_FIFO_OUT_DAT_MARKER_1_MASK BIT(30) -#define C2H_STAT_DMA_ENG_4_QID_FIFO_OUT_DAT_DROP_REQ_1_MASK BIT(29) -#define C2H_STAT_DMA_ENG_4_QID_FIFO_OUT_DAT_QID_1_MASK GENMASK(28, 17) -#define C2H_STAT_DMA_ENG_4_WR_HDR_FIFO_OUT_CNT_1_MASK GENMASK(16, 12) -#define C2H_STAT_DMA_ENG_4_QID_FIFO_OUT_VLD_1_MASK BIT(11) -#define C2H_STAT_DMA_ENG_4_PLD_FIFO_OUT_VLD_1_MASK BIT(10) -#define C2H_STAT_DMA_ENG_4_PLD_ST_FIFO_OUT_VLD_1_MASK BIT(9) -#define C2H_STAT_DMA_ENG_4_PLD_ST_FIFO_OUT_DATA_EOP_1_MASK BIT(8) -#define C2H_STAT_DMA_ENG_4_PLD_ST_FIFO_OUT_DATA_AVL_IDX_ENABLE_1_MASK BIT(7) -#define C2H_STAT_DMA_ENG_4_PLD_ST_FIFO_OUT_DATA_DROP_1_MASK BIT(6) -#define C2H_STAT_DMA_ENG_4_PLD_ST_FIFO_OUT_DATA_ERR_1_MASK BIT(5) -#define C2H_STAT_DMA_ENG_4_DESC_CNT_FIFO_IN_RDY_1_MASK BIT(4) -#define C2H_STAT_DMA_ENG_4_DESC_RSP_FIFO_IN_RDY_1_MASK BIT(3) -#define C2H_STAT_DMA_ENG_4_PLD_PKT_ID_LARGER_1_MASK BIT(2) -#define C2H_STAT_DMA_ENG_4_WCP_FIFO_IN_RDY_1_MASK BIT(1) -#define C2H_STAT_DMA_ENG_4_PLD_ST_FIFO_IN_RDY_1_MASK BIT(0) -#define EQDMA_C2H_STAT_DBG_DMA_ENG_5_ADDR 0xB8C -#define C2H_STAT_DMA_ENG_5_ARB_FIFO_IN_RDY_MASK BIT(31) -#define C2H_STAT_DMA_ENG_5_WRB_SM_VIRT_CH_MASK BIT(30) -#define C2H_STAT_DMA_ENG_5_WRB_FIFO_IN_REQ_MASK GENMASK(29, 24) -#define C2H_STAT_DMA_ENG_5_ARB_FIFO_OUT_CNT_MASK GENMASK(23, 22) -#define C2H_STAT_DMA_ENG_5_ARB_FIFO_OUT_DATA_LEN_MASK GENMASK(21, 6) -#define C2H_STAT_DMA_ENG_5_ARB_FIFO_OUT_DATA_VIRT_CH_MASK BIT(5) -#define C2H_STAT_DMA_ENG_5_ARB_FIFO_OUT_DATA_VAR_DESC_MASK BIT(4) -#define C2H_STAT_DMA_ENG_5_ARB_FIFO_OUT_DATA_DROP_REQ_MASK BIT(3) -#define C2H_STAT_DMA_ENG_5_ARB_FIFO_OUT_DATA_NUM_BUF_OV_MASK BIT(2) -#define C2H_STAT_DMA_ENG_5_ARB_FIFO_OUT_DATA_MARKER_MASK BIT(1) -#define C2H_STAT_DMA_ENG_5_ARB_FIFO_OUT_DATA_HAS_CMPT_MASK BIT(0) -#define EQDMA_C2H_DBG_PFCH_QID_ADDR 0xB90 -#define C2H_PFCH_QID_RSVD_1_MASK GENMASK(31, 16) -#define C2H_PFCH_QID_ERR_CTXT_MASK BIT(15) -#define C2H_PFCH_QID_TARGET_MASK GENMASK(14, 12) -#define C2H_PFCH_QID_QID_OR_TAG_MASK GENMASK(11, 0) -#define EQDMA_C2H_DBG_PFCH_ADDR 0xB94 -#define C2H_PFCH_DATA_MASK GENMASK(31, 0) -#define EQDMA_C2H_INT_DBG_ADDR 0xB98 -#define C2H_INT_RSVD_1_MASK GENMASK(31, 8) -#define C2H_INT_INT_COAL_SM_MASK GENMASK(7, 4) -#define C2H_INT_INT_SM_MASK GENMASK(3, 0) -#define EQDMA_C2H_STAT_IMM_ACCEPTED_ADDR 0xB9C -#define C2H_STAT_IMM_ACCEPTED_RSVD_1_MASK GENMASK(31, 18) -#define C2H_STAT_IMM_ACCEPTED_CNT_MASK GENMASK(17, 0) -#define EQDMA_C2H_STAT_MARKER_ACCEPTED_ADDR 0xBA0 -#define C2H_STAT_MARKER_ACCEPTED_RSVD_1_MASK GENMASK(31, 18) -#define C2H_STAT_MARKER_ACCEPTED_CNT_MASK GENMASK(17, 0) -#define EQDMA_C2H_STAT_DISABLE_CMP_ACCEPTED_ADDR 0xBA4 -#define C2H_STAT_DISABLE_CMP_ACCEPTED_RSVD_1_MASK GENMASK(31, 18) -#define C2H_STAT_DISABLE_CMP_ACCEPTED_CNT_MASK GENMASK(17, 0) -#define EQDMA_C2H_PLD_FIFO_CRDT_CNT_ADDR 0xBA8 -#define C2H_PLD_FIFO_CRDT_CNT_RSVD_1_MASK GENMASK(31, 18) -#define C2H_PLD_FIFO_CRDT_CNT_CNT_MASK GENMASK(17, 0) -#define EQDMA_C2H_INTR_DYN_REQ_ADDR 0xBAC -#define C2H_INTR_DYN_REQ_RSVD_1_MASK GENMASK(31, 18) -#define C2H_INTR_DYN_REQ_CNT_MASK GENMASK(17, 0) -#define EQDMA_C2H_INTR_DYN_MISC_ADDR 0xBB0 -#define C2H_INTR_DYN_MISC_RSVD_1_MASK GENMASK(31, 18) -#define C2H_INTR_DYN_MISC_CNT_MASK GENMASK(17, 0) -#define EQDMA_C2H_DROP_LEN_MISMATCH_ADDR 0xBB4 -#define C2H_DROP_LEN_MISMATCH_RSVD_1_MASK GENMASK(31, 18) -#define C2H_DROP_LEN_MISMATCH_CNT_MASK GENMASK(17, 0) -#define EQDMA_C2H_DROP_DESC_RSP_LEN_ADDR 0xBB8 -#define C2H_DROP_DESC_RSP_LEN_RSVD_1_MASK GENMASK(31, 18) -#define C2H_DROP_DESC_RSP_LEN_CNT_MASK GENMASK(17, 0) -#define EQDMA_C2H_DROP_QID_FIFO_LEN_ADDR 0xBBC -#define C2H_DROP_QID_FIFO_LEN_RSVD_1_MASK GENMASK(31, 18) -#define C2H_DROP_QID_FIFO_LEN_CNT_MASK GENMASK(17, 0) -#define EQDMA_C2H_DROP_PLD_CNT_ADDR 0xBC0 -#define C2H_DROP_PLD_CNT_RSVD_1_MASK GENMASK(31, 18) -#define C2H_DROP_PLD_CNT_CNT_MASK GENMASK(17, 0) -#define EQDMA_C2H_CMPT_FORMAT_0_ADDR 0xBC4 -#define C2H_CMPT_FORMAT_0_DESC_ERR_LOC_MASK GENMASK(31, 16) -#define C2H_CMPT_FORMAT_0_COLOR_LOC_MASK GENMASK(15, 0) -#define EQDMA_C2H_CMPT_FORMAT_1_ADDR 0xBC8 -#define C2H_CMPT_FORMAT_1_DESC_ERR_LOC_MASK GENMASK(31, 16) -#define C2H_CMPT_FORMAT_1_COLOR_LOC_MASK GENMASK(15, 0) -#define EQDMA_C2H_CMPT_FORMAT_2_ADDR 0xBCC -#define C2H_CMPT_FORMAT_2_DESC_ERR_LOC_MASK GENMASK(31, 16) -#define C2H_CMPT_FORMAT_2_COLOR_LOC_MASK GENMASK(15, 0) -#define EQDMA_C2H_CMPT_FORMAT_3_ADDR 0xBD0 -#define C2H_CMPT_FORMAT_3_DESC_ERR_LOC_MASK GENMASK(31, 16) -#define C2H_CMPT_FORMAT_3_COLOR_LOC_MASK GENMASK(15, 0) -#define EQDMA_C2H_CMPT_FORMAT_4_ADDR 0xBD4 -#define C2H_CMPT_FORMAT_4_DESC_ERR_LOC_MASK GENMASK(31, 16) -#define C2H_CMPT_FORMAT_4_COLOR_LOC_MASK GENMASK(15, 0) -#define EQDMA_C2H_CMPT_FORMAT_5_ADDR 0xBD8 -#define C2H_CMPT_FORMAT_5_DESC_ERR_LOC_MASK GENMASK(31, 16) -#define C2H_CMPT_FORMAT_5_COLOR_LOC_MASK GENMASK(15, 0) -#define EQDMA_C2H_CMPT_FORMAT_6_ADDR 0xBDC -#define C2H_CMPT_FORMAT_6_DESC_ERR_LOC_MASK GENMASK(31, 16) -#define C2H_CMPT_FORMAT_6_COLOR_LOC_MASK GENMASK(15, 0) -#define EQDMA_C2H_PFCH_CACHE_DEPTH_ADDR 0xBE0 -#define C2H_PFCH_CACHE_DEPTH_MAX_STBUF_MASK GENMASK(23, 16) -#define C2H_PFCH_CACHE_DEPTH_MASK GENMASK(7, 0) -#define EQDMA_C2H_WRB_COAL_BUF_DEPTH_ADDR 0xBE4 -#define C2H_WRB_COAL_BUF_DEPTH_RSVD_1_MASK GENMASK(31, 8) -#define C2H_WRB_COAL_BUF_DEPTH_BUFFER_MASK GENMASK(7, 0) -#define EQDMA_C2H_PFCH_CRDT_ADDR 0xBE8 -#define C2H_PFCH_CRDT_RSVD_1_MASK GENMASK(31, 1) -#define C2H_PFCH_CRDT_RSVD_2_MASK BIT(0) -#define EQDMA_C2H_STAT_HAS_CMPT_ACCEPTED_ADDR 0xBEC -#define C2H_STAT_HAS_CMPT_ACCEPTED_RSVD_1_MASK GENMASK(31, 18) -#define C2H_STAT_HAS_CMPT_ACCEPTED_CNT_MASK GENMASK(17, 0) -#define EQDMA_C2H_STAT_HAS_PLD_ACCEPTED_ADDR 0xBF0 -#define C2H_STAT_HAS_PLD_ACCEPTED_RSVD_1_MASK GENMASK(31, 18) -#define C2H_STAT_HAS_PLD_ACCEPTED_CNT_MASK GENMASK(17, 0) -#define EQDMA_C2H_PLD_PKT_ID_ADDR 0xBF4 -#define C2H_PLD_PKT_ID_CMPT_WAIT_MASK GENMASK(31, 16) -#define C2H_PLD_PKT_ID_DATA_MASK GENMASK(15, 0) -#define EQDMA_C2H_PLD_PKT_ID_1_ADDR 0xBF8 -#define C2H_PLD_PKT_ID_1_CMPT_WAIT_MASK GENMASK(31, 16) -#define C2H_PLD_PKT_ID_1_DATA_MASK GENMASK(15, 0) -#define EQDMA_C2H_DROP_PLD_CNT_1_ADDR 0xBFC -#define C2H_DROP_PLD_CNT_1_RSVD_1_MASK GENMASK(31, 18) -#define C2H_DROP_PLD_CNT_1_CNT_MASK GENMASK(17, 0) -#define EQDMA_H2C_ERR_STAT_ADDR 0xE00 -#define H2C_ERR_STAT_RSVD_1_MASK GENMASK(31, 6) -#define H2C_ERR_STAT_PAR_ERR_MASK BIT(5) -#define H2C_ERR_STAT_SBE_MASK BIT(4) -#define H2C_ERR_STAT_DBE_MASK BIT(3) -#define H2C_ERR_STAT_NO_DMA_DS_MASK BIT(2) -#define H2C_ERR_STAT_SDI_MRKR_REQ_MOP_ERR_MASK BIT(1) -#define H2C_ERR_STAT_ZERO_LEN_DS_MASK BIT(0) -#define EQDMA_H2C_ERR_MASK_ADDR 0xE04 -#define H2C_ERR_EN_MASK GENMASK(31, 0) -#define EQDMA_H2C_FIRST_ERR_QID_ADDR 0xE08 -#define H2C_FIRST_ERR_QID_RSVD_1_MASK GENMASK(31, 20) -#define H2C_FIRST_ERR_QID_ERR_TYPE_MASK GENMASK(19, 16) -#define H2C_FIRST_ERR_QID_RSVD_2_MASK GENMASK(15, 13) -#define H2C_FIRST_ERR_QID_QID_MASK GENMASK(12, 0) -#define EQDMA_H2C_DBG_REG0_ADDR 0xE0C -#define H2C_REG0_NUM_DSC_RCVD_MASK GENMASK(31, 16) -#define H2C_REG0_NUM_WRB_SENT_MASK GENMASK(15, 0) -#define EQDMA_H2C_DBG_REG1_ADDR 0xE10 -#define H2C_REG1_NUM_REQ_SENT_MASK GENMASK(31, 16) -#define H2C_REG1_NUM_CMP_SENT_MASK GENMASK(15, 0) -#define EQDMA_H2C_DBG_REG2_ADDR 0xE14 -#define H2C_REG2_RSVD_1_MASK GENMASK(31, 16) -#define H2C_REG2_NUM_ERR_DSC_RCVD_MASK GENMASK(15, 0) -#define EQDMA_H2C_DBG_REG3_ADDR 0xE18 -#define H2C_REG3_RSVD_1_MASK BIT(31) -#define H2C_REG3_DSCO_FIFO_EMPTY_MASK BIT(30) -#define H2C_REG3_DSCO_FIFO_FULL_MASK BIT(29) -#define H2C_REG3_CUR_RC_STATE_MASK GENMASK(28, 26) -#define H2C_REG3_RDREQ_LINES_MASK GENMASK(25, 16) -#define H2C_REG3_RDATA_LINES_AVAIL_MASK GENMASK(15, 6) -#define H2C_REG3_PEND_FIFO_EMPTY_MASK BIT(5) -#define H2C_REG3_PEND_FIFO_FULL_MASK BIT(4) -#define H2C_REG3_CUR_RQ_STATE_MASK GENMASK(3, 2) -#define H2C_REG3_DSCI_FIFO_FULL_MASK BIT(1) -#define H2C_REG3_DSCI_FIFO_EMPTY_MASK BIT(0) -#define EQDMA_H2C_DBG_REG4_ADDR 0xE1C -#define H2C_REG4_RDREQ_ADDR_MASK GENMASK(31, 0) -#define EQDMA_H2C_FATAL_ERR_EN_ADDR 0xE20 -#define H2C_FATAL_ERR_EN_RSVD_1_MASK GENMASK(31, 1) -#define H2C_FATAL_ERR_EN_H2C_MASK BIT(0) -#define EQDMA_H2C_REQ_THROT_PCIE_ADDR 0xE24 -#define H2C_REQ_THROT_PCIE_EN_REQ_MASK BIT(31) -#define H2C_REQ_THROT_PCIE_MASK GENMASK(30, 19) -#define H2C_REQ_THROT_PCIE_EN_DATA_MASK BIT(18) -#define H2C_REQ_THROT_PCIE_DATA_THRESH_MASK GENMASK(17, 0) -#define EQDMA_H2C_ALN_DBG_REG0_ADDR 0xE28 -#define H2C_ALN_REG0_NUM_PKT_SENT_MASK GENMASK(15, 0) -#define EQDMA_H2C_REQ_THROT_AXIMM_ADDR 0xE2C -#define H2C_REQ_THROT_AXIMM_EN_REQ_MASK BIT(31) -#define H2C_REQ_THROT_AXIMM_MASK GENMASK(30, 19) -#define H2C_REQ_THROT_AXIMM_EN_DATA_MASK BIT(18) -#define H2C_REQ_THROT_AXIMM_DATA_THRESH_MASK GENMASK(17, 0) -#define EQDMA_C2H_MM_CTL_ADDR 0x1004 -#define C2H_MM_CTL_RESERVED1_MASK GENMASK(31, 9) -#define C2H_MM_CTL_ERRC_EN_MASK BIT(8) -#define C2H_MM_CTL_RESERVED0_MASK GENMASK(7, 1) -#define C2H_MM_CTL_RUN_MASK BIT(0) -#define EQDMA_C2H_MM_STATUS_ADDR 0x1040 -#define C2H_MM_STATUS_RSVD_1_MASK GENMASK(31, 1) -#define C2H_MM_STATUS_RUN_MASK BIT(0) -#define EQDMA_C2H_MM_CMPL_DESC_CNT_ADDR 0x1048 -#define C2H_MM_CMPL_DESC_CNT_C2H_CO_MASK GENMASK(31, 0) -#define EQDMA_C2H_MM_ERR_CODE_ENABLE_MASK_ADDR 0x1054 -#define C2H_MM_ERR_CODE_ENABLE_RESERVED1_MASK BIT(31) -#define C2H_MM_ERR_CODE_ENABLE_WR_UC_RAM_MASK BIT(30) -#define C2H_MM_ERR_CODE_ENABLE_WR_UR_MASK BIT(29) -#define C2H_MM_ERR_CODE_ENABLE_WR_FLR_MASK BIT(28) -#define C2H_MM_ERR_CODE_ENABLE_RESERVED0_MASK GENMASK(27, 2) -#define C2H_MM_ERR_CODE_ENABLE_RD_SLV_ERR_MASK BIT(1) -#define C2H_MM_ERR_CODE_ENABLE_WR_SLV_ERR_MASK BIT(0) -#define EQDMA_C2H_MM_ERR_CODE_ADDR 0x1058 -#define C2H_MM_ERR_CODE_RESERVED1_MASK GENMASK(31, 28) -#define C2H_MM_ERR_CODE_CIDX_MASK GENMASK(27, 12) -#define C2H_MM_ERR_CODE_RESERVED0_MASK GENMASK(11, 10) -#define C2H_MM_ERR_CODE_SUB_TYPE_MASK GENMASK(9, 5) -#define C2H_MM_ERR_CODE_MASK GENMASK(4, 0) -#define EQDMA_C2H_MM_ERR_INFO_ADDR 0x105C -#define C2H_MM_ERR_INFO_VALID_MASK BIT(31) -#define C2H_MM_ERR_INFO_SEL_MASK BIT(30) -#define C2H_MM_ERR_INFO_RSVD_1_MASK GENMASK(29, 24) -#define C2H_MM_ERR_INFO_QID_MASK GENMASK(23, 0) -#define EQDMA_C2H_MM_PERF_MON_CTL_ADDR 0x10C0 -#define C2H_MM_PERF_MON_CTL_RSVD_1_MASK GENMASK(31, 4) -#define C2H_MM_PERF_MON_CTL_IMM_START_MASK BIT(3) -#define C2H_MM_PERF_MON_CTL_RUN_START_MASK BIT(2) -#define C2H_MM_PERF_MON_CTL_IMM_CLEAR_MASK BIT(1) -#define C2H_MM_PERF_MON_CTL_RUN_CLEAR_MASK BIT(0) -#define EQDMA_C2H_MM_PERF_MON_CYCLE_CNT0_ADDR 0x10C4 -#define C2H_MM_PERF_MON_CYCLE_CNT0_CYC_CNT_MASK GENMASK(31, 0) -#define EQDMA_C2H_MM_PERF_MON_CYCLE_CNT1_ADDR 0x10C8 -#define C2H_MM_PERF_MON_CYCLE_CNT1_RSVD_1_MASK GENMASK(31, 10) -#define C2H_MM_PERF_MON_CYCLE_CNT1_CYC_CNT_MASK GENMASK(9, 0) -#define EQDMA_C2H_MM_PERF_MON_DATA_CNT0_ADDR 0x10CC -#define C2H_MM_PERF_MON_DATA_CNT0_DCNT_MASK GENMASK(31, 0) -#define EQDMA_C2H_MM_PERF_MON_DATA_CNT1_ADDR 0x10D0 -#define C2H_MM_PERF_MON_DATA_CNT1_RSVD_1_MASK GENMASK(31, 10) -#define C2H_MM_PERF_MON_DATA_CNT1_DCNT_MASK GENMASK(9, 0) -#define EQDMA_C2H_MM_DBG_ADDR 0x10E8 -#define C2H_MM_RSVD_1_MASK GENMASK(31, 24) -#define C2H_MM_RRQ_ENTRIES_MASK GENMASK(23, 17) -#define C2H_MM_DAT_FIFO_SPC_MASK GENMASK(16, 7) -#define C2H_MM_RD_STALL_MASK BIT(6) -#define C2H_MM_RRQ_FIFO_FI_MASK BIT(5) -#define C2H_MM_WR_STALL_MASK BIT(4) -#define C2H_MM_WRQ_FIFO_FI_MASK BIT(3) -#define C2H_MM_WBK_STALL_MASK BIT(2) -#define C2H_MM_DSC_FIFO_EP_MASK BIT(1) -#define C2H_MM_DSC_FIFO_FL_MASK BIT(0) -#define EQDMA_H2C_MM_CTL_ADDR 0x1204 -#define H2C_MM_CTL_RESERVED1_MASK GENMASK(31, 9) -#define H2C_MM_CTL_ERRC_EN_MASK BIT(8) -#define H2C_MM_CTL_RESERVED0_MASK GENMASK(7, 1) -#define H2C_MM_CTL_RUN_MASK BIT(0) -#define EQDMA_H2C_MM_STATUS_ADDR 0x1240 -#define H2C_MM_STATUS_RSVD_1_MASK GENMASK(31, 1) -#define H2C_MM_STATUS_RUN_MASK BIT(0) -#define EQDMA_H2C_MM_CMPL_DESC_CNT_ADDR 0x1248 -#define H2C_MM_CMPL_DESC_CNT_H2C_CO_MASK GENMASK(31, 0) -#define EQDMA_H2C_MM_ERR_CODE_ENABLE_MASK_ADDR 0x1254 -#define H2C_MM_ERR_CODE_ENABLE_RESERVED5_MASK GENMASK(31, 30) -#define H2C_MM_ERR_CODE_ENABLE_WR_SLV_ERR_MASK BIT(29) -#define H2C_MM_ERR_CODE_ENABLE_WR_DEC_ERR_MASK BIT(28) -#define H2C_MM_ERR_CODE_ENABLE_RESERVED4_MASK GENMASK(27, 23) -#define H2C_MM_ERR_CODE_ENABLE_RD_RQ_DIS_ERR_MASK BIT(22) -#define H2C_MM_ERR_CODE_ENABLE_RESERVED3_MASK GENMASK(21, 17) -#define H2C_MM_ERR_CODE_ENABLE_RD_DAT_POISON_ERR_MASK BIT(16) -#define H2C_MM_ERR_CODE_ENABLE_RESERVED2_MASK GENMASK(15, 9) -#define H2C_MM_ERR_CODE_ENABLE_RD_FLR_ERR_MASK BIT(8) -#define H2C_MM_ERR_CODE_ENABLE_RESERVED1_MASK GENMASK(7, 6) -#define H2C_MM_ERR_CODE_ENABLE_RD_HDR_ADR_ERR_MASK BIT(5) -#define H2C_MM_ERR_CODE_ENABLE_RD_HDR_PARA_MASK BIT(4) -#define H2C_MM_ERR_CODE_ENABLE_RD_HDR_BYTE_ERR_MASK BIT(3) -#define H2C_MM_ERR_CODE_ENABLE_RD_UR_CA_MASK BIT(2) -#define H2C_MM_ERR_CODE_ENABLE_RD_HRD_POISON_ERR_MASK BIT(1) -#define H2C_MM_ERR_CODE_ENABLE_RESERVED0_MASK BIT(0) -#define EQDMA_H2C_MM_ERR_CODE_ADDR 0x1258 -#define H2C_MM_ERR_CODE_RSVD_1_MASK GENMASK(31, 28) -#define H2C_MM_ERR_CODE_CIDX_MASK GENMASK(27, 12) -#define H2C_MM_ERR_CODE_RESERVED0_MASK GENMASK(11, 10) -#define H2C_MM_ERR_CODE_SUB_TYPE_MASK GENMASK(9, 5) -#define H2C_MM_ERR_CODE_MASK GENMASK(4, 0) -#define EQDMA_H2C_MM_ERR_INFO_ADDR 0x125C -#define H2C_MM_ERR_INFO_VALID_MASK BIT(31) -#define H2C_MM_ERR_INFO_SEL_MASK BIT(30) -#define H2C_MM_ERR_INFO_RSVD_1_MASK GENMASK(29, 24) -#define H2C_MM_ERR_INFO_QID_MASK GENMASK(23, 0) -#define EQDMA_H2C_MM_PERF_MON_CTL_ADDR 0x12C0 -#define H2C_MM_PERF_MON_CTL_RSVD_1_MASK GENMASK(31, 4) -#define H2C_MM_PERF_MON_CTL_IMM_START_MASK BIT(3) -#define H2C_MM_PERF_MON_CTL_RUN_START_MASK BIT(2) -#define H2C_MM_PERF_MON_CTL_IMM_CLEAR_MASK BIT(1) -#define H2C_MM_PERF_MON_CTL_RUN_CLEAR_MASK BIT(0) -#define EQDMA_H2C_MM_PERF_MON_CYCLE_CNT0_ADDR 0x12C4 -#define H2C_MM_PERF_MON_CYCLE_CNT0_CYC_CNT_MASK GENMASK(31, 0) -#define EQDMA_H2C_MM_PERF_MON_CYCLE_CNT1_ADDR 0x12C8 -#define H2C_MM_PERF_MON_CYCLE_CNT1_RSVD_1_MASK GENMASK(31, 10) -#define H2C_MM_PERF_MON_CYCLE_CNT1_CYC_CNT_MASK GENMASK(9, 0) -#define EQDMA_H2C_MM_PERF_MON_DATA_CNT0_ADDR 0x12CC -#define H2C_MM_PERF_MON_DATA_CNT0_DCNT_MASK GENMASK(31, 0) -#define EQDMA_H2C_MM_PERF_MON_DATA_CNT1_ADDR 0x12D0 -#define H2C_MM_PERF_MON_DATA_CNT1_RSVD_1_MASK GENMASK(31, 10) -#define H2C_MM_PERF_MON_DATA_CNT1_DCNT_MASK GENMASK(9, 0) -#define EQDMA_H2C_MM_DBG_ADDR 0x12E8 -#define H2C_MM_RSVD_1_MASK GENMASK(31, 24) -#define H2C_MM_RRQ_ENTRIES_MASK GENMASK(23, 17) -#define H2C_MM_DAT_FIFO_SPC_MASK GENMASK(16, 7) -#define H2C_MM_RD_STALL_MASK BIT(6) -#define H2C_MM_RRQ_FIFO_FI_MASK BIT(5) -#define H2C_MM_WR_STALL_MASK BIT(4) -#define H2C_MM_WRQ_FIFO_FI_MASK BIT(3) -#define H2C_MM_WBK_STALL_MASK BIT(2) -#define H2C_MM_DSC_FIFO_EP_MASK BIT(1) -#define H2C_MM_DSC_FIFO_FL_MASK BIT(0) -#define EQDMA_H2C_MM_DATA_THROTTLE_ADDR 0x12EC -#define H2C_MM_DATA_THROTTLE_RSVD_1_MASK GENMASK(31, 17) -#define H2C_MM_DATA_THROTTLE_DAT_EN_MASK BIT(16) -#define H2C_MM_DATA_THROTTLE_DAT_MASK GENMASK(15, 0) -#define EQDMA_C2H_CRDT_COAL_CFG_1_ADDR 0x1400 -#define C2H_CRDT_COAL_CFG_1_RSVD_1_MASK GENMASK(31, 18) -#define C2H_CRDT_COAL_CFG_1_PLD_FIFO_TH_MASK GENMASK(17, 10) -#define C2H_CRDT_COAL_CFG_1_TIMER_TH_MASK GENMASK(9, 0) -#define EQDMA_C2H_CRDT_COAL_CFG_2_ADDR 0x1404 -#define C2H_CRDT_COAL_CFG_2_RSVD_1_MASK GENMASK(31, 24) -#define C2H_CRDT_COAL_CFG_2_FIFO_TH_MASK GENMASK(23, 16) -#define C2H_CRDT_COAL_CFG_2_RESERVED1_MASK GENMASK(15, 11) -#define C2H_CRDT_COAL_CFG_2_NT_TH_MASK GENMASK(10, 0) -#define EQDMA_C2H_PFCH_BYP_QID_ADDR 0x1408 -#define C2H_PFCH_BYP_QID_RSVD_1_MASK GENMASK(31, 12) -#define C2H_PFCH_BYP_QID_MASK GENMASK(11, 0) -#define EQDMA_C2H_PFCH_BYP_TAG_ADDR 0x140C -#define C2H_PFCH_BYP_TAG_RSVD_1_MASK GENMASK(31, 20) -#define C2H_PFCH_BYP_TAG_BYP_QID_MASK GENMASK(19, 8) -#define C2H_PFCH_BYP_TAG_RSVD_2_MASK BIT(7) -#define C2H_PFCH_BYP_TAG_MASK GENMASK(6, 0) -#define EQDMA_C2H_WATER_MARK_ADDR 0x1410 -#define C2H_WATER_MARK_HIGH_WM_MASK GENMASK(31, 16) -#define C2H_WATER_MARK_LOW_WM_MASK GENMASK(15, 0) -#define EQDMA_C2H_NOTIFY_EMPTY_ADDR 0x1450 -#define C2H_NOTIFY_EMPTY_RSVD_1_MASK GENMASK(31, 16) -#define C2H_NOTIFY_EMPTY_NOE_MASK GENMASK(15, 0) -#define EQDMA_C2H_STAT_S_AXIS_C2H_ACCEPTED_1_ADDR 0x1454 -#define C2H_STAT_S_AXIS_C2H_ACCEPTED_1_MASK GENMASK(31, 0) -#define EQDMA_C2H_STAT_S_AXIS_WRB_ACCEPTED_1_ADDR 0x1458 -#define C2H_STAT_S_AXIS_WRB_ACCEPTED_1_MASK GENMASK(31, 0) -#define EQDMA_C2H_STAT_DESC_RSP_PKT_ACCEPTED_1_ADDR 0x145C -#define C2H_STAT_DESC_RSP_PKT_ACCEPTED_1_D_MASK GENMASK(31, 0) -#define EQDMA_C2H_STAT_AXIS_PKG_CMP_1_ADDR 0x1460 -#define C2H_STAT_AXIS_PKG_CMP_1_MASK GENMASK(31, 0) -#define EQDMA_C2H_STAT_S_AXIS_WRB_ACCEPTED_2_ADDR 0x1464 -#define C2H_STAT_S_AXIS_WRB_ACCEPTED_2_MASK GENMASK(31, 0) -#define EQDMA_C2H_ST_PLD_FIFO_DEPTH_ADDR 0x1468 -#define C2H_ST_PLD_FIFO_DEPTH_MASK GENMASK(31, 0) -#define EQDMA_C2H_STAT_DBG_DMA_ENG_6_ADDR 0x146C -#define C2H_STAT_DMA_ENG_6_RSVD_MASK GENMASK(31, 29) -#define C2H_STAT_DMA_ENG_6_PLD_ST_FIFO_OUT_DATA_QID_MASK GENMASK(28, 17) -#define C2H_STAT_DMA_ENG_6_PLD_STS_FIFO_OUT_DATA_PLD_ST_PKT_ID_MASK \ - GENMASK(16, 1) -#define C2H_STAT_DMA_ENG_6_PLD_PKT_ID_LARGER_PLD_ST_MASK BIT(0) -#define EQDMA_C2H_STAT_DBG_DMA_ENG_7_ADDR 0x1470 -#define C2H_STAT_DMA_ENG_7_RSVD_MASK GENMASK(31, 29) -#define C2H_STAT_DMA_ENG_7_PLD_ST_FIFO_OUT_DATA_QID_1_MASK GENMASK(28, 17) -#define C2H_STAT_DMA_ENG_7_PLD_STS_FIFO_OUT_DATA_PLD_ST_PKT_ID_1_MASK \ - GENMASK(16, 1) -#define C2H_STAT_DMA_ENG_7_PLD_PKT_ID_LARGER_PLD_ST_1_MASK BIT(0) -#define EQDMA_C2H_STAT_PCIE_CMP_1_ADDR 0x1474 -#define C2H_STAT_PCIE_CMP_1_DEPTH_MASK GENMASK(31, 0) -#define EQDMA_C2H_PLD_FIFO_ALMOST_FULL_ADDR 0x1478 -#define C2H_PLD_FIFO_ALMOST_FULL_ENABLE_MASK BIT(31) -#define C2H_PLD_FIFO_ALMOST_FULL_TH_MASK GENMASK(30, 0) -#define EQDMA_PFCH_CFG_3_ADDR 0x147C -#define PFCH_CFG_3_RSVD_MASK GENMASK(31, 16) -#define PFCH_CFG_3_VAR_DESC_FL_FREE_CNT_TH_MASK GENMASK(15, 7) -#define PFCH_CFG_3_VAR_DESC_LG_PKT_CAM_CN_TH_MASK GENMASK(6, 0) -#define EQDMA_CMPT_CFG_0_ADDR 0x1480 -#define CMPT_CFG_0_RSVD_MASK GENMASK(31, 2) -#define CMPT_CFG_0_VIO_SPRS_INT_AFTER_RTY_MASK BIT(1) -#define CMPT_CFG_0_VIO_EVNT_SUP_EN_MASK BIT(0) -#define EQDMA_PFCH_CFG_4_ADDR 0x1484 -#define PFCH_CFG_4_GLB_EVT_TIMER_TICK_MASK GENMASK(31, 17) -#define PFCH_CFG_4_DISABLE_GLB_EVT_TIMER_MASK BIT(16) -#define PFCH_CFG_4_EVT_TIMER_TICK_MASK GENMASK(15, 1) -#define PFCH_CFG_4_DISABLE_EVT_TIMER_MASK BIT(0) -#define SW_IND_CTXT_DATA_W7_VIRTIO_DSC_BASE_H_MASK GENMASK(10, 0) -#define SW_IND_CTXT_DATA_W6_VIRTIO_DSC_BASE_M_MASK GENMASK(31, 0) -#define SW_IND_CTXT_DATA_W5_VIRTIO_DSC_BASE_L_MASK GENMASK(31, 11) -#define SW_IND_CTXT_DATA_W5_PASID_EN_MASK BIT(10) -#define SW_IND_CTXT_DATA_W5_PASID_H_MASK GENMASK(9, 0) -#define SW_IND_CTXT_DATA_W4_PASID_L_MASK GENMASK(31, 20) -#define SW_IND_CTXT_DATA_W4_HOST_ID_MASK GENMASK(19, 16) -#define SW_IND_CTXT_DATA_W4_IRQ_BYP_MASK BIT(15) -#define SW_IND_CTXT_DATA_W4_PACK_BYP_OUT_MASK BIT(14) -#define SW_IND_CTXT_DATA_W4_VIRTIO_EN_MASK BIT(13) -#define SW_IND_CTXT_DATA_W4_DIS_INTR_ON_VF_MASK BIT(12) -#define SW_IND_CTXT_DATA_W4_INT_AGGR_MASK BIT(11) -#define SW_IND_CTXT_DATA_W4_VEC_MASK GENMASK(10, 0) -#define SW_IND_CTXT_DATA_W3_DSC_BASE_H_MASK GENMASK(31, 0) -#define SW_IND_CTXT_DATA_W2_DSC_BASE_L_MASK GENMASK(31, 0) -#define SW_IND_CTXT_DATA_W1_IS_MM_MASK BIT(31) -#define SW_IND_CTXT_DATA_W1_MRKR_DIS_MASK BIT(30) -#define SW_IND_CTXT_DATA_W1_IRQ_REQ_MASK BIT(29) -#define SW_IND_CTXT_DATA_W1_ERR_WB_SENT_MASK BIT(28) -#define SW_IND_CTXT_DATA_W1_ERR_MASK GENMASK(27, 26) -#define SW_IND_CTXT_DATA_W1_IRQ_NO_LAST_MASK BIT(25) -#define SW_IND_CTXT_DATA_W1_PORT_ID_MASK GENMASK(24, 22) -#define SW_IND_CTXT_DATA_W1_IRQ_EN_MASK BIT(21) -#define SW_IND_CTXT_DATA_W1_WBK_EN_MASK BIT(20) -#define SW_IND_CTXT_DATA_W1_MM_CHN_MASK BIT(19) -#define SW_IND_CTXT_DATA_W1_BYPASS_MASK BIT(18) -#define SW_IND_CTXT_DATA_W1_DSC_SZ_MASK GENMASK(17, 16) -#define SW_IND_CTXT_DATA_W1_RNG_SZ_MASK GENMASK(15, 12) -#define SW_IND_CTXT_DATA_W1_RSVD_1_MASK GENMASK(11, 9) -#define SW_IND_CTXT_DATA_W1_FETCH_MAX_MASK GENMASK(8, 5) -#define SW_IND_CTXT_DATA_W1_AT_MASK BIT(4) -#define SW_IND_CTXT_DATA_W1_WBI_INTVL_EN_MASK BIT(3) -#define SW_IND_CTXT_DATA_W1_WBI_CHK_MASK BIT(2) -#define SW_IND_CTXT_DATA_W1_FCRD_EN_MASK BIT(1) -#define SW_IND_CTXT_DATA_W1_QEN_MASK BIT(0) -#define SW_IND_CTXT_DATA_W0_RSV_MASK GENMASK(31, 29) -#define SW_IND_CTXT_DATA_W0_FNC_MASK GENMASK(28, 17) -#define SW_IND_CTXT_DATA_W0_IRQ_ARM_MASK BIT(16) -#define SW_IND_CTXT_DATA_W0_PIDX_MASK GENMASK(15, 0) -#define HW_IND_CTXT_DATA_W1_RSVD_1_MASK BIT(15) -#define HW_IND_CTXT_DATA_W1_FETCH_PND_MASK GENMASK(14, 11) -#define HW_IND_CTXT_DATA_W1_EVT_PND_MASK BIT(10) -#define HW_IND_CTXT_DATA_W1_IDL_STP_B_MASK BIT(9) -#define HW_IND_CTXT_DATA_W1_DSC_PND_MASK BIT(8) -#define HW_IND_CTXT_DATA_W1_RSVD_2_MASK GENMASK(7, 0) -#define HW_IND_CTXT_DATA_W0_CRD_USE_MASK GENMASK(31, 16) -#define HW_IND_CTXT_DATA_W0_CIDX_MASK GENMASK(15, 0) -#define CRED_CTXT_DATA_W0_RSVD_1_MASK GENMASK(31, 16) -#define CRED_CTXT_DATA_W0_CREDT_MASK GENMASK(15, 0) -#define PREFETCH_CTXT_DATA_W1_VALID_MASK BIT(13) -#define PREFETCH_CTXT_DATA_W1_SW_CRDT_H_MASK GENMASK(12, 0) -#define PREFETCH_CTXT_DATA_W0_SW_CRDT_L_MASK GENMASK(31, 29) -#define PREFETCH_CTXT_DATA_W0_PFCH_MASK BIT(28) -#define PREFETCH_CTXT_DATA_W0_PFCH_EN_MASK BIT(27) -#define PREFETCH_CTXT_DATA_W0_ERR_MASK BIT(26) -#define PREFETCH_CTXT_DATA_W0_RSVD_MASK GENMASK(25, 22) -#define PREFETCH_CTXT_DATA_W0_PFCH_NEED_MASK GENMASK(21, 16) -#define PREFETCH_CTXT_DATA_W0_NUM_PFCH_MASK GENMASK(15, 10) -#define PREFETCH_CTXT_DATA_W0_VIRTIO_MASK BIT(9) -#define PREFETCH_CTXT_DATA_W0_VAR_DESC_MASK BIT(8) -#define PREFETCH_CTXT_DATA_W0_PORT_ID_MASK GENMASK(7, 5) -#define PREFETCH_CTXT_DATA_W0_BUF_SZ_IDX_MASK GENMASK(4, 1) -#define PREFETCH_CTXT_DATA_W0_BYPASS_MASK BIT(0) -#define CMPL_CTXT_DATA_W6_RSVD_1_H_MASK GENMASK(7, 0) -#define CMPL_CTXT_DATA_W5_RSVD_1_L_MASK GENMASK(31, 23) -#define CMPL_CTXT_DATA_W5_PORT_ID_MASK GENMASK(22, 20) -#define CMPL_CTXT_DATA_W5_SH_CMPT_MASK BIT(19) -#define CMPL_CTXT_DATA_W5_VIO_EOP_MASK BIT(18) -#define CMPL_CTXT_DATA_W5_BADDR4_LOW_MASK GENMASK(17, 14) -#define CMPL_CTXT_DATA_W5_PASID_EN_MASK BIT(13) -#define CMPL_CTXT_DATA_W5_PASID_H_MASK GENMASK(12, 0) -#define CMPL_CTXT_DATA_W4_PASID_L_MASK GENMASK(31, 23) -#define CMPL_CTXT_DATA_W4_HOST_ID_MASK GENMASK(22, 19) -#define CMPL_CTXT_DATA_W4_DIR_C2H_MASK BIT(18) -#define CMPL_CTXT_DATA_W4_VIO_MASK BIT(17) -#define CMPL_CTXT_DATA_W4_DIS_INTR_ON_VF_MASK BIT(16) -#define CMPL_CTXT_DATA_W4_INT_AGGR_MASK BIT(15) -#define CMPL_CTXT_DATA_W4_VEC_MASK GENMASK(14, 4) -#define CMPL_CTXT_DATA_W4_AT_MASK BIT(3) -#define CMPL_CTXT_DATA_W4_OVF_CHK_DIS_MASK BIT(2) -#define CMPL_CTXT_DATA_W4_FULL_UPD_MASK BIT(1) -#define CMPL_CTXT_DATA_W4_TIMER_RUNNING_MASK BIT(0) -#define CMPL_CTXT_DATA_W3_USER_TRIG_PEND_MASK BIT(31) -#define CMPL_CTXT_DATA_W3_ERR_MASK GENMASK(30, 29) -#define CMPL_CTXT_DATA_W3_VALID_MASK BIT(28) -#define CMPL_CTXT_DATA_W3_CIDX_MASK GENMASK(27, 12) -#define CMPL_CTXT_DATA_W3_PIDX_H_MASK GENMASK(11, 0) -#define CMPL_CTXT_DATA_W2_PIDX_L_MASK GENMASK(31, 28) -#define CMPL_CTXT_DATA_W2_DESC_SIZE_MASK GENMASK(27, 26) -#define CMPL_CTXT_DATA_W2_BADDR4_HIGH_H_MASK GENMASK(25, 0) -#define CMPL_CTXT_DATA_W1_BADDR4_HIGH_L_MASK GENMASK(31, 0) -#define CMPL_CTXT_DATA_W0_QSIZE_IX_MASK GENMASK(31, 28) -#define CMPL_CTXT_DATA_W0_COLOR_MASK BIT(27) -#define CMPL_CTXT_DATA_W0_INT_ST_MASK GENMASK(26, 25) -#define CMPL_CTXT_DATA_W0_TIMER_IX_MASK GENMASK(24, 21) -#define CMPL_CTXT_DATA_W0_CNTER_IX_MASK GENMASK(20, 17) -#define CMPL_CTXT_DATA_W0_FNC_ID_MASK GENMASK(16, 5) -#define CMPL_CTXT_DATA_W0_TRIG_MODE_MASK GENMASK(4, 2) -#define CMPL_CTXT_DATA_W0_EN_INT_MASK BIT(1) -#define CMPL_CTXT_DATA_W0_EN_STAT_DESC_MASK BIT(0) -#define INTR_CTXT_DATA_W3_FUNC_MASK GENMASK(29, 18) -#define INTR_CTXT_DATA_W3_RSVD_MASK GENMASK(17, 14) -#define INTR_CTXT_DATA_W3_PASID_EN_MASK BIT(13) -#define INTR_CTXT_DATA_W3_PASID_H_MASK GENMASK(12, 0) -#define INTR_CTXT_DATA_W2_PASID_L_MASK GENMASK(31, 23) -#define INTR_CTXT_DATA_W2_HOST_ID_MASK GENMASK(22, 19) -#define INTR_CTXT_DATA_W2_AT_MASK BIT(18) -#define INTR_CTXT_DATA_W2_PIDX_MASK GENMASK(17, 6) -#define INTR_CTXT_DATA_W2_PAGE_SIZE_MASK GENMASK(5, 3) -#define INTR_CTXT_DATA_W2_BADDR_4K_H_MASK GENMASK(2, 0) -#define INTR_CTXT_DATA_W1_BADDR_4K_M_MASK GENMASK(31, 0) -#define INTR_CTXT_DATA_W0_BADDR_4K_L_MASK GENMASK(31, 15) -#define INTR_CTXT_DATA_W0_COLOR_MASK BIT(14) -#define INTR_CTXT_DATA_W0_INT_ST_MASK BIT(13) -#define INTR_CTXT_DATA_W0_RSVD1_MASK BIT(12) -#define INTR_CTXT_DATA_W0_VEC_MASK GENMASK(11, 1) -#define INTR_CTXT_DATA_W0_VALID_MASK BIT(0) -#define HOSTID_TABLE_W6_SMID_MASK GENMASK(9, 0) -#define HOSTID_TABLE_W5_H2C_MM_AWPROT_MASK GENMASK(27, 26) -#define HOSTID_TABLE_W5_H2C_MM_AWCACHE_MASK GENMASK(25, 22) -#define HOSTID_TABLE_W5_H2C_MM_AWSTEERING_MASK GENMASK(20, 18) -#define HOSTID_TABLE_W5_DSC_AWPROT_MASK GENMASK(17, 16) -#define HOSTID_TABLE_W5_DSC_AWCACHE_MASK GENMASK(15, 12) -#define HOSTID_TABLE_W5_DSC_AWSTEERING_MASK GENMASK(11, 8) -#define HOSTID_TABLE_W5_INT_MSG_AWPROT_MASK GENMASK(7, 6) -#define HOSTID_TABLE_W5_INT_MSG_AWCACHE_MASK GENMASK(5, 2) -#define HOSTID_TABLE_W5_INT_MSG_AWSTEERING_H_MASK GENMASK(0, 0) -#define HOSTID_TABLE_W4_INT_MSG_AWSTEERING_L_MASK GENMASK(31, 30) -#define HOSTID_TABLE_W4_INT_AGGR_AWPROT_MASK GENMASK(29, 28) -#define HOSTID_TABLE_W4_INT_AGGR_AWCACHE_MASK GENMASK(27, 24) -#define HOSTID_TABLE_W4_INT_AGGR_AWSTEERING_MASK GENMASK(22, 20) -#define HOSTID_TABLE_W4_CMPT_AWPROT_MASK GENMASK(19, 18) -#define HOSTID_TABLE_W4_CMPT_AWCACHE_MASK GENMASK(17, 14) -#define HOSTID_TABLE_W4_CMPT_AWSTEERING_MASK GENMASK(12, 10) -#define HOSTID_TABLE_W4_C2H_PLD_AWPROT_MASK GENMASK(9, 8) -#define HOSTID_TABLE_W4_C2H_PLD_AWCACHE_MASK GENMASK(7, 4) -#define HOSTID_TABLE_W4_C2H_PLD_AWSTEERING_MASK GENMASK(2, 0) -#define HOSTID_TABLE_W3_C2H_MM_ARPROT_MASK GENMASK(7, 6) -#define HOSTID_TABLE_W3_C2H_MM_ARCACHE_MASK GENMASK(5, 2) -#define HOSTID_TABLE_W3_C2H_MM_ARSTEERING_H_MASK GENMASK(0, 0) -#define HOSTID_TABLE_W2_C2H_MM_ARSTEERING_L_MASK GENMASK(31, 30) -#define HOSTID_TABLE_W2_H2C_MM_ARPROT_MASK GENMASK(29, 28) -#define HOSTID_TABLE_W2_H2C_MM_ARCACHE_MASK GENMASK(27, 24) -#define HOSTID_TABLE_W2_H2C_MM_ARSTEERING_MASK GENMASK(22, 20) -#define HOSTID_TABLE_W2_H2C_ST_ARPROT_MASK GENMASK(19, 18) -#define HOSTID_TABLE_W2_H2C_ST_ARCACHE_MASK GENMASK(17, 14) -#define HOSTID_TABLE_W2_H2C_ST_ARSTEERING_MASK GENMASK(12, 10) -#define HOSTID_TABLE_W2_DSC_ARPOT_MASK GENMASK(9, 8) -#define HOSTID_TABLE_W2_DSC_ARCACHE_MASK GENMASK(7, 4) -#define HOSTID_TABLE_W2_DSC_ARSTEERING_MASK GENMASK(2, 0) -#define HOSTID_TABLE_W0_VCH_H2C_MM_MASK GENMASK(27, 24) -#define HOSTID_TABLE_W0_VCH_H2C_ST_MASK GENMASK(23, 20) -#define HOSTID_TABLE_W0_VCH_DSC_MASK GENMASK(19, 16) -#define HOSTID_TABLE_W0_VCH_INT_MSG_MASK GENMASK(15, 12) -#define HOSTID_TABLE_W0_VCH_INT_AGGR_MASK GENMASK(11, 8) -#define HOSTID_TABLE_W0_VCH_CMPT_MASK GENMASK(7, 4) -#define HOSTID_TABLE_W0_VCH_H2C_PLD_MASK GENMASK(3, 0) -#define CTXT_SELC_FNC_STS_W0_MSIX_MASK GENMASK(3, 3) -#define CTXT_SELC_FNC_STS_W0_MSIX_ENABLE_MASK GENMASK(2, 2) -#define CTXT_SELC_FNC_STS_W0_MEM_SPACE_ENABLE_MASK GENMASK(1, 1) -#define CTXT_SELC_FNC_STS_W0_BUS_MASTER_ENABLE_MASK GENMASK(0, 0) - -#ifdef __cplusplus -} -#endif - -#endif - diff --git a/QDMA/DPDK/drivers/net/qdma/qdma_access/eqdma_soft_access/eqdma_soft_reg_dump.c b/QDMA/DPDK/drivers/net/qdma/qdma_access/eqdma_soft_access/eqdma_soft_reg_dump.c deleted file mode 100755 index 41950f9ce..000000000 --- a/QDMA/DPDK/drivers/net/qdma/qdma_access/eqdma_soft_access/eqdma_soft_reg_dump.c +++ /dev/null @@ -1,5338 +0,0 @@ -/* - * Copyright (c) 2019-2022 Xilinx, Inc. All rights reserved. - * Copyright (c) 2022, Advanced Micro Devices, Inc. All rights reserved. - * - * BSD LICENSE - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * * Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include "eqdma_soft_reg.h" -#include "qdma_reg_dump.h" - -#ifdef ENABLE_WPP_TRACING -#include "eqdma_soft_reg_dump.tmh" -#endif - - -static struct regfield_info - cfg_blk_identifier_field_info[] = { - {"CFG_BLK_IDENTIFIER", - CFG_BLK_IDENTIFIER_MASK}, - {"CFG_BLK_IDENTIFIER_1", - CFG_BLK_IDENTIFIER_1_MASK}, - {"CFG_BLK_IDENTIFIER_RSVD_1", - CFG_BLK_IDENTIFIER_RSVD_1_MASK}, - {"CFG_BLK_IDENTIFIER_VERSION", - CFG_BLK_IDENTIFIER_VERSION_MASK}, -}; - - -static struct regfield_info - cfg_blk_pcie_max_pld_size_field_info[] = { - {"CFG_BLK_PCIE_MAX_PLD_SIZE_RSVD_1", - CFG_BLK_PCIE_MAX_PLD_SIZE_RSVD_1_MASK}, - {"CFG_BLK_PCIE_MAX_PLD_SIZE_PROG", - CFG_BLK_PCIE_MAX_PLD_SIZE_PROG_MASK}, - {"CFG_BLK_PCIE_MAX_PLD_SIZE_RSVD_2", - CFG_BLK_PCIE_MAX_PLD_SIZE_RSVD_2_MASK}, - {"CFG_BLK_PCIE_MAX_PLD_SIZE_ISSUED", - CFG_BLK_PCIE_MAX_PLD_SIZE_ISSUED_MASK}, -}; - - -static struct regfield_info - cfg_blk_pcie_max_read_req_size_field_info[] = { - {"CFG_BLK_PCIE_MAX_READ_REQ_SIZE_RSVD_1", - CFG_BLK_PCIE_MAX_READ_REQ_SIZE_RSVD_1_MASK}, - {"CFG_BLK_PCIE_MAX_READ_REQ_SIZE_PROG", - CFG_BLK_PCIE_MAX_READ_REQ_SIZE_PROG_MASK}, - {"CFG_BLK_PCIE_MAX_READ_REQ_SIZE_RSVD_2", - CFG_BLK_PCIE_MAX_READ_REQ_SIZE_RSVD_2_MASK}, - {"CFG_BLK_PCIE_MAX_READ_REQ_SIZE_ISSUED", - CFG_BLK_PCIE_MAX_READ_REQ_SIZE_ISSUED_MASK}, -}; - - -static struct regfield_info - cfg_blk_system_id_field_info[] = { - {"CFG_BLK_SYSTEM_ID_RSVD_1", - CFG_BLK_SYSTEM_ID_RSVD_1_MASK}, - {"CFG_BLK_SYSTEM_ID_INST_TYPE", - CFG_BLK_SYSTEM_ID_INST_TYPE_MASK}, - {"CFG_BLK_SYSTEM_ID", - CFG_BLK_SYSTEM_ID_MASK}, -}; - - -static struct regfield_info - cfg_blk_msix_enable_field_info[] = { - {"CFG_BLK_MSIX_ENABLE", - CFG_BLK_MSIX_ENABLE_MASK}, -}; - - -static struct regfield_info - cfg_pcie_data_width_field_info[] = { - {"CFG_PCIE_DATA_WIDTH_RSVD_1", - CFG_PCIE_DATA_WIDTH_RSVD_1_MASK}, - {"CFG_PCIE_DATA_WIDTH_DATAPATH", - CFG_PCIE_DATA_WIDTH_DATAPATH_MASK}, -}; - - -static struct regfield_info - cfg_pcie_ctl_field_info[] = { - {"CFG_PCIE_CTL_RSVD_1", - CFG_PCIE_CTL_RSVD_1_MASK}, - {"CFG_PCIE_CTL_MGMT_AXIL_CTRL", - CFG_PCIE_CTL_MGMT_AXIL_CTRL_MASK}, - {"CFG_PCIE_CTL_RSVD_2", - CFG_PCIE_CTL_RSVD_2_MASK}, - {"CFG_PCIE_CTL_RRQ_DISABLE", - CFG_PCIE_CTL_RRQ_DISABLE_MASK}, - {"CFG_PCIE_CTL_RELAXED_ORDERING", - CFG_PCIE_CTL_RELAXED_ORDERING_MASK}, -}; - - -static struct regfield_info - cfg_blk_msi_enable_field_info[] = { - {"CFG_BLK_MSI_ENABLE", - CFG_BLK_MSI_ENABLE_MASK}, -}; - - -static struct regfield_info - cfg_axi_user_max_pld_size_field_info[] = { - {"CFG_AXI_USER_MAX_PLD_SIZE_RSVD_1", - CFG_AXI_USER_MAX_PLD_SIZE_RSVD_1_MASK}, - {"CFG_AXI_USER_MAX_PLD_SIZE_ISSUED", - CFG_AXI_USER_MAX_PLD_SIZE_ISSUED_MASK}, - {"CFG_AXI_USER_MAX_PLD_SIZE_RSVD_2", - CFG_AXI_USER_MAX_PLD_SIZE_RSVD_2_MASK}, - {"CFG_AXI_USER_MAX_PLD_SIZE_PROG", - CFG_AXI_USER_MAX_PLD_SIZE_PROG_MASK}, -}; - - -static struct regfield_info - cfg_axi_user_max_read_req_size_field_info[] = { - {"CFG_AXI_USER_MAX_READ_REQ_SIZE_RSVD_1", - CFG_AXI_USER_MAX_READ_REQ_SIZE_RSVD_1_MASK}, - {"CFG_AXI_USER_MAX_READ_REQ_SIZE_USISSUED", - CFG_AXI_USER_MAX_READ_REQ_SIZE_USISSUED_MASK}, - {"CFG_AXI_USER_MAX_READ_REQ_SIZE_RSVD_2", - CFG_AXI_USER_MAX_READ_REQ_SIZE_RSVD_2_MASK}, - {"CFG_AXI_USER_MAX_READ_REQ_SIZE_USPROG", - CFG_AXI_USER_MAX_READ_REQ_SIZE_USPROG_MASK}, -}; - - -static struct regfield_info - cfg_blk_misc_ctl_field_info[] = { - {"CFG_BLK_MISC_CTL_RSVD_1", - CFG_BLK_MISC_CTL_RSVD_1_MASK}, - {"CFG_BLK_MISC_CTL_10B_TAG_EN", - CFG_BLK_MISC_CTL_10B_TAG_EN_MASK}, - {"CFG_BLK_MISC_CTL_RSVD_2", - CFG_BLK_MISC_CTL_RSVD_2_MASK}, - {"CFG_BLK_MISC_CTL_AXI_WBK", - CFG_BLK_MISC_CTL_AXI_WBK_MASK}, - {"CFG_BLK_MISC_CTL_AXI_DSC", - CFG_BLK_MISC_CTL_AXI_DSC_MASK}, - {"CFG_BLK_MISC_CTL_NUM_TAG", - CFG_BLK_MISC_CTL_NUM_TAG_MASK}, - {"CFG_BLK_MISC_CTL_RSVD_3", - CFG_BLK_MISC_CTL_RSVD_3_MASK}, - {"CFG_BLK_MISC_CTL_RQ_METERING_MULTIPLIER", - CFG_BLK_MISC_CTL_RQ_METERING_MULTIPLIER_MASK}, -}; - - -static struct regfield_info - cfg_pl_cred_ctl_field_info[] = { - {"CFG_PL_CRED_CTL_RSVD_1", - CFG_PL_CRED_CTL_RSVD_1_MASK}, - {"CFG_PL_CRED_CTL_SLAVE_CRD_RLS", - CFG_PL_CRED_CTL_SLAVE_CRD_RLS_MASK}, - {"CFG_PL_CRED_CTL_RSVD_2", - CFG_PL_CRED_CTL_RSVD_2_MASK}, - {"CFG_PL_CRED_CTL_MASTER_CRD_RST", - CFG_PL_CRED_CTL_MASTER_CRD_RST_MASK}, -}; - - -static struct regfield_info - cfg_blk_scratch_field_info[] = { - {"CFG_BLK_SCRATCH", - CFG_BLK_SCRATCH_MASK}, -}; - - -static struct regfield_info - cfg_gic_field_info[] = { - {"CFG_GIC_RSVD_1", - CFG_GIC_RSVD_1_MASK}, - {"CFG_GIC_GIC_IRQ", - CFG_GIC_GIC_IRQ_MASK}, -}; - - -static struct regfield_info - ram_sbe_msk_1_a_field_info[] = { - {"RAM_SBE_MSK_1_A", - RAM_SBE_MSK_1_A_MASK}, -}; - - -static struct regfield_info - ram_sbe_sts_1_a_field_info[] = { - {"RAM_SBE_STS_1_A_RSVD", - RAM_SBE_STS_1_A_RSVD_MASK}, - {"RAM_SBE_STS_1_A_PFCH_CTXT_CAM_RAM_1", - RAM_SBE_STS_1_A_PFCH_CTXT_CAM_RAM_1_MASK}, - {"RAM_SBE_STS_1_A_PFCH_CTXT_CAM_RAM_0", - RAM_SBE_STS_1_A_PFCH_CTXT_CAM_RAM_0_MASK}, - {"RAM_SBE_STS_1_A_TAG_EVEN_RAM", - RAM_SBE_STS_1_A_TAG_EVEN_RAM_MASK}, - {"RAM_SBE_STS_1_A_TAG_ODD_RAM", - RAM_SBE_STS_1_A_TAG_ODD_RAM_MASK}, - {"RAM_SBE_STS_1_A_RC_RRQ_EVEN_RAM", - RAM_SBE_STS_1_A_RC_RRQ_EVEN_RAM_MASK}, -}; - - -static struct regfield_info - ram_dbe_msk_1_a_field_info[] = { - {"RAM_DBE_MSK_1_A", - RAM_DBE_MSK_1_A_MASK}, -}; - - -static struct regfield_info - ram_dbe_sts_1_a_field_info[] = { - {"RAM_DBE_STS_1_A_RSVD", - RAM_DBE_STS_1_A_RSVD_MASK}, - {"RAM_DBE_STS_1_A_PFCH_CTXT_CAM_RAM_1", - RAM_DBE_STS_1_A_PFCH_CTXT_CAM_RAM_1_MASK}, - {"RAM_DBE_STS_1_A_PFCH_CTXT_CAM_RAM_0", - RAM_DBE_STS_1_A_PFCH_CTXT_CAM_RAM_0_MASK}, - {"RAM_DBE_STS_1_A_TAG_EVEN_RAM", - RAM_DBE_STS_1_A_TAG_EVEN_RAM_MASK}, - {"RAM_DBE_STS_1_A_TAG_ODD_RAM", - RAM_DBE_STS_1_A_TAG_ODD_RAM_MASK}, - {"RAM_DBE_STS_1_A_RC_RRQ_EVEN_RAM", - RAM_DBE_STS_1_A_RC_RRQ_EVEN_RAM_MASK}, -}; - - -static struct regfield_info - ram_sbe_msk_a_field_info[] = { - {"RAM_SBE_MSK_A", - RAM_SBE_MSK_A_MASK}, -}; - - -static struct regfield_info - ram_sbe_sts_a_field_info[] = { - {"RAM_SBE_STS_A_RC_RRQ_ODD_RAM", - RAM_SBE_STS_A_RC_RRQ_ODD_RAM_MASK}, - {"RAM_SBE_STS_A_PEND_FIFO_RAM", - RAM_SBE_STS_A_PEND_FIFO_RAM_MASK}, - {"RAM_SBE_STS_A_PFCH_LL_RAM", - RAM_SBE_STS_A_PFCH_LL_RAM_MASK}, - {"RAM_SBE_STS_A_WRB_CTXT_RAM", - RAM_SBE_STS_A_WRB_CTXT_RAM_MASK}, - {"RAM_SBE_STS_A_PFCH_CTXT_RAM", - RAM_SBE_STS_A_PFCH_CTXT_RAM_MASK}, - {"RAM_SBE_STS_A_DESC_REQ_FIFO_RAM", - RAM_SBE_STS_A_DESC_REQ_FIFO_RAM_MASK}, - {"RAM_SBE_STS_A_INT_CTXT_RAM", - RAM_SBE_STS_A_INT_CTXT_RAM_MASK}, - {"RAM_SBE_STS_A_WRB_COAL_DATA_RAM", - RAM_SBE_STS_A_WRB_COAL_DATA_RAM_MASK}, - {"RAM_SBE_STS_A_QID_FIFO_RAM", - RAM_SBE_STS_A_QID_FIFO_RAM_MASK}, - {"RAM_SBE_STS_A_TIMER_FIFO_RAM", - RAM_SBE_STS_A_TIMER_FIFO_RAM_MASK}, - {"RAM_SBE_STS_A_MI_TL_SLV_FIFO_RAM", - RAM_SBE_STS_A_MI_TL_SLV_FIFO_RAM_MASK}, - {"RAM_SBE_STS_A_DSC_CPLD", - RAM_SBE_STS_A_DSC_CPLD_MASK}, - {"RAM_SBE_STS_A_DSC_CPLI", - RAM_SBE_STS_A_DSC_CPLI_MASK}, - {"RAM_SBE_STS_A_DSC_SW_CTXT", - RAM_SBE_STS_A_DSC_SW_CTXT_MASK}, - {"RAM_SBE_STS_A_DSC_CRD_RCV", - RAM_SBE_STS_A_DSC_CRD_RCV_MASK}, - {"RAM_SBE_STS_A_DSC_HW_CTXT", - RAM_SBE_STS_A_DSC_HW_CTXT_MASK}, - {"RAM_SBE_STS_A_FUNC_MAP", - RAM_SBE_STS_A_FUNC_MAP_MASK}, - {"RAM_SBE_STS_A_C2H_WR_BRG_DAT", - RAM_SBE_STS_A_C2H_WR_BRG_DAT_MASK}, - {"RAM_SBE_STS_A_C2H_RD_BRG_DAT", - RAM_SBE_STS_A_C2H_RD_BRG_DAT_MASK}, - {"RAM_SBE_STS_A_H2C_WR_BRG_DAT", - RAM_SBE_STS_A_H2C_WR_BRG_DAT_MASK}, - {"RAM_SBE_STS_A_H2C_RD_BRG_DAT", - RAM_SBE_STS_A_H2C_RD_BRG_DAT_MASK}, - {"RAM_SBE_STS_A_MI_C2H3_DAT", - RAM_SBE_STS_A_MI_C2H3_DAT_MASK}, - {"RAM_SBE_STS_A_MI_C2H2_DAT", - RAM_SBE_STS_A_MI_C2H2_DAT_MASK}, - {"RAM_SBE_STS_A_MI_C2H1_DAT", - RAM_SBE_STS_A_MI_C2H1_DAT_MASK}, - {"RAM_SBE_STS_A_MI_C2H0_DAT", - RAM_SBE_STS_A_MI_C2H0_DAT_MASK}, - {"RAM_SBE_STS_A_MI_H2C3_DAT", - RAM_SBE_STS_A_MI_H2C3_DAT_MASK}, - {"RAM_SBE_STS_A_MI_H2C2_DAT", - RAM_SBE_STS_A_MI_H2C2_DAT_MASK}, - {"RAM_SBE_STS_A_MI_H2C1_DAT", - RAM_SBE_STS_A_MI_H2C1_DAT_MASK}, - {"RAM_SBE_STS_A_MI_H2C0_DAT", - RAM_SBE_STS_A_MI_H2C0_DAT_MASK}, -}; - - -static struct regfield_info - ram_dbe_msk_a_field_info[] = { - {"RAM_DBE_MSK_A", - RAM_DBE_MSK_A_MASK}, -}; - - -static struct regfield_info - ram_dbe_sts_a_field_info[] = { - {"RAM_DBE_STS_A_RC_RRQ_ODD_RAM", - RAM_DBE_STS_A_RC_RRQ_ODD_RAM_MASK}, - {"RAM_DBE_STS_A_PEND_FIFO_RAM", - RAM_DBE_STS_A_PEND_FIFO_RAM_MASK}, - {"RAM_DBE_STS_A_PFCH_LL_RAM", - RAM_DBE_STS_A_PFCH_LL_RAM_MASK}, - {"RAM_DBE_STS_A_WRB_CTXT_RAM", - RAM_DBE_STS_A_WRB_CTXT_RAM_MASK}, - {"RAM_DBE_STS_A_PFCH_CTXT_RAM", - RAM_DBE_STS_A_PFCH_CTXT_RAM_MASK}, - {"RAM_DBE_STS_A_DESC_REQ_FIFO_RAM", - RAM_DBE_STS_A_DESC_REQ_FIFO_RAM_MASK}, - {"RAM_DBE_STS_A_INT_CTXT_RAM", - RAM_DBE_STS_A_INT_CTXT_RAM_MASK}, - {"RAM_DBE_STS_A_WRB_COAL_DATA_RAM", - RAM_DBE_STS_A_WRB_COAL_DATA_RAM_MASK}, - {"RAM_DBE_STS_A_QID_FIFO_RAM", - RAM_DBE_STS_A_QID_FIFO_RAM_MASK}, - {"RAM_DBE_STS_A_TIMER_FIFO_RAM", - RAM_DBE_STS_A_TIMER_FIFO_RAM_MASK}, - {"RAM_DBE_STS_A_MI_TL_SLV_FIFO_RAM", - RAM_DBE_STS_A_MI_TL_SLV_FIFO_RAM_MASK}, - {"RAM_DBE_STS_A_DSC_CPLD", - RAM_DBE_STS_A_DSC_CPLD_MASK}, - {"RAM_DBE_STS_A_DSC_CPLI", - RAM_DBE_STS_A_DSC_CPLI_MASK}, - {"RAM_DBE_STS_A_DSC_SW_CTXT", - RAM_DBE_STS_A_DSC_SW_CTXT_MASK}, - {"RAM_DBE_STS_A_DSC_CRD_RCV", - RAM_DBE_STS_A_DSC_CRD_RCV_MASK}, - {"RAM_DBE_STS_A_DSC_HW_CTXT", - RAM_DBE_STS_A_DSC_HW_CTXT_MASK}, - {"RAM_DBE_STS_A_FUNC_MAP", - RAM_DBE_STS_A_FUNC_MAP_MASK}, - {"RAM_DBE_STS_A_C2H_WR_BRG_DAT", - RAM_DBE_STS_A_C2H_WR_BRG_DAT_MASK}, - {"RAM_DBE_STS_A_C2H_RD_BRG_DAT", - RAM_DBE_STS_A_C2H_RD_BRG_DAT_MASK}, - {"RAM_DBE_STS_A_H2C_WR_BRG_DAT", - RAM_DBE_STS_A_H2C_WR_BRG_DAT_MASK}, - {"RAM_DBE_STS_A_H2C_RD_BRG_DAT", - RAM_DBE_STS_A_H2C_RD_BRG_DAT_MASK}, - {"RAM_DBE_STS_A_MI_C2H3_DAT", - RAM_DBE_STS_A_MI_C2H3_DAT_MASK}, - {"RAM_DBE_STS_A_MI_C2H2_DAT", - RAM_DBE_STS_A_MI_C2H2_DAT_MASK}, - {"RAM_DBE_STS_A_MI_C2H1_DAT", - RAM_DBE_STS_A_MI_C2H1_DAT_MASK}, - {"RAM_DBE_STS_A_MI_C2H0_DAT", - RAM_DBE_STS_A_MI_C2H0_DAT_MASK}, - {"RAM_DBE_STS_A_MI_H2C3_DAT", - RAM_DBE_STS_A_MI_H2C3_DAT_MASK}, - {"RAM_DBE_STS_A_MI_H2C2_DAT", - RAM_DBE_STS_A_MI_H2C2_DAT_MASK}, - {"RAM_DBE_STS_A_MI_H2C1_DAT", - RAM_DBE_STS_A_MI_H2C1_DAT_MASK}, - {"RAM_DBE_STS_A_MI_H2C0_DAT", - RAM_DBE_STS_A_MI_H2C0_DAT_MASK}, -}; - - -static struct regfield_info - glbl2_identifier_field_info[] = { - {"GLBL2_IDENTIFIER", - GLBL2_IDENTIFIER_MASK}, - {"GLBL2_IDENTIFIER_VERSION", - GLBL2_IDENTIFIER_VERSION_MASK}, -}; - - -static struct regfield_info - glbl2_channel_inst_field_info[] = { - {"GLBL2_CHANNEL_INST_RSVD_1", - GLBL2_CHANNEL_INST_RSVD_1_MASK}, - {"GLBL2_CHANNEL_INST_C2H_ST", - GLBL2_CHANNEL_INST_C2H_ST_MASK}, - {"GLBL2_CHANNEL_INST_H2C_ST", - GLBL2_CHANNEL_INST_H2C_ST_MASK}, - {"GLBL2_CHANNEL_INST_RSVD_2", - GLBL2_CHANNEL_INST_RSVD_2_MASK}, - {"GLBL2_CHANNEL_INST_C2H_ENG", - GLBL2_CHANNEL_INST_C2H_ENG_MASK}, - {"GLBL2_CHANNEL_INST_RSVD_3", - GLBL2_CHANNEL_INST_RSVD_3_MASK}, - {"GLBL2_CHANNEL_INST_H2C_ENG", - GLBL2_CHANNEL_INST_H2C_ENG_MASK}, -}; - - -static struct regfield_info - glbl2_channel_mdma_field_info[] = { - {"GLBL2_CHANNEL_MDMA_RSVD_1", - GLBL2_CHANNEL_MDMA_RSVD_1_MASK}, - {"GLBL2_CHANNEL_MDMA_C2H_ST", - GLBL2_CHANNEL_MDMA_C2H_ST_MASK}, - {"GLBL2_CHANNEL_MDMA_H2C_ST", - GLBL2_CHANNEL_MDMA_H2C_ST_MASK}, - {"GLBL2_CHANNEL_MDMA_RSVD_2", - GLBL2_CHANNEL_MDMA_RSVD_2_MASK}, - {"GLBL2_CHANNEL_MDMA_C2H_ENG", - GLBL2_CHANNEL_MDMA_C2H_ENG_MASK}, - {"GLBL2_CHANNEL_MDMA_RSVD_3", - GLBL2_CHANNEL_MDMA_RSVD_3_MASK}, - {"GLBL2_CHANNEL_MDMA_H2C_ENG", - GLBL2_CHANNEL_MDMA_H2C_ENG_MASK}, -}; - - -static struct regfield_info - glbl2_channel_strm_field_info[] = { - {"GLBL2_CHANNEL_STRM_RSVD_1", - GLBL2_CHANNEL_STRM_RSVD_1_MASK}, - {"GLBL2_CHANNEL_STRM_C2H_ST", - GLBL2_CHANNEL_STRM_C2H_ST_MASK}, - {"GLBL2_CHANNEL_STRM_H2C_ST", - GLBL2_CHANNEL_STRM_H2C_ST_MASK}, - {"GLBL2_CHANNEL_STRM_RSVD_2", - GLBL2_CHANNEL_STRM_RSVD_2_MASK}, - {"GLBL2_CHANNEL_STRM_C2H_ENG", - GLBL2_CHANNEL_STRM_C2H_ENG_MASK}, - {"GLBL2_CHANNEL_STRM_RSVD_3", - GLBL2_CHANNEL_STRM_RSVD_3_MASK}, - {"GLBL2_CHANNEL_STRM_H2C_ENG", - GLBL2_CHANNEL_STRM_H2C_ENG_MASK}, -}; - - -static struct regfield_info - glbl2_channel_cap_field_info[] = { - {"GLBL2_CHANNEL_CAP_RSVD_1", - GLBL2_CHANNEL_CAP_RSVD_1_MASK}, - {"GLBL2_CHANNEL_CAP_MULTIQ_MAX", - GLBL2_CHANNEL_CAP_MULTIQ_MAX_MASK}, -}; - - -static struct regfield_info - glbl2_channel_pasid_cap_field_info[] = { - {"GLBL2_CHANNEL_PASID_CAP_RSVD_1", - GLBL2_CHANNEL_PASID_CAP_RSVD_1_MASK}, - {"GLBL2_CHANNEL_PASID_CAP_BRIDGEEN", - GLBL2_CHANNEL_PASID_CAP_BRIDGEEN_MASK}, - {"GLBL2_CHANNEL_PASID_CAP_DMAEN", - GLBL2_CHANNEL_PASID_CAP_DMAEN_MASK}, -}; - - -static struct regfield_info - glbl2_system_id_field_info[] = { - {"GLBL2_SYSTEM_ID_RSVD_1", - GLBL2_SYSTEM_ID_RSVD_1_MASK}, - {"GLBL2_SYSTEM_ID", - GLBL2_SYSTEM_ID_MASK}, -}; - - -static struct regfield_info - glbl2_misc_cap_field_info[] = { - {"GLBL2_MISC_CAP", - GLBL2_MISC_CAP_MASK}, -}; - - -static struct regfield_info - glbl2_rrq_brg_throt_field_info[] = { - {"GLBL2_RRQ_BRG_THROT_REQ_EN", - GLBL2_RRQ_BRG_THROT_REQ_EN_MASK}, - {"GLBL2_RRQ_BRG_THROT_REQ", - GLBL2_RRQ_BRG_THROT_REQ_MASK}, - {"GLBL2_RRQ_BRG_THROT_DAT_EN", - GLBL2_RRQ_BRG_THROT_DAT_EN_MASK}, - {"GLBL2_RRQ_BRG_THROT_DAT", - GLBL2_RRQ_BRG_THROT_DAT_MASK}, -}; - - -static struct regfield_info - glbl2_rrq_pcie_throt_field_info[] = { - {"GLBL2_RRQ_PCIE_THROT_REQ_EN", - GLBL2_RRQ_PCIE_THROT_REQ_EN_MASK}, - {"GLBL2_RRQ_PCIE_THROT_REQ", - GLBL2_RRQ_PCIE_THROT_REQ_MASK}, - {"GLBL2_RRQ_PCIE_THROT_DAT_EN", - GLBL2_RRQ_PCIE_THROT_DAT_EN_MASK}, - {"GLBL2_RRQ_PCIE_THROT_DAT", - GLBL2_RRQ_PCIE_THROT_DAT_MASK}, -}; - - -static struct regfield_info - glbl2_rrq_aximm_throt_field_info[] = { - {"GLBL2_RRQ_AXIMM_THROT_REQ_EN", - GLBL2_RRQ_AXIMM_THROT_REQ_EN_MASK}, - {"GLBL2_RRQ_AXIMM_THROT_REQ", - GLBL2_RRQ_AXIMM_THROT_REQ_MASK}, - {"GLBL2_RRQ_AXIMM_THROT_DAT_EN", - GLBL2_RRQ_AXIMM_THROT_DAT_EN_MASK}, - {"GLBL2_RRQ_AXIMM_THROT_DAT", - GLBL2_RRQ_AXIMM_THROT_DAT_MASK}, -}; - - -static struct regfield_info - glbl2_rrq_pcie_lat0_field_info[] = { - {"GLBL2_RRQ_PCIE_LAT0_MAX", - GLBL2_RRQ_PCIE_LAT0_MAX_MASK}, - {"GLBL2_RRQ_PCIE_LAT0_MIN", - GLBL2_RRQ_PCIE_LAT0_MIN_MASK}, -}; - - -static struct regfield_info - glbl2_rrq_pcie_lat1_field_info[] = { - {"GLBL2_RRQ_PCIE_LAT1_RSVD", - GLBL2_RRQ_PCIE_LAT1_RSVD_MASK}, - {"GLBL2_RRQ_PCIE_LAT1_OVFL", - GLBL2_RRQ_PCIE_LAT1_OVFL_MASK}, - {"GLBL2_RRQ_PCIE_LAT1_AVG", - GLBL2_RRQ_PCIE_LAT1_AVG_MASK}, -}; - - -static struct regfield_info - glbl2_rrq_aximm_lat0_field_info[] = { - {"GLBL2_RRQ_AXIMM_LAT0_MAX", - GLBL2_RRQ_AXIMM_LAT0_MAX_MASK}, - {"GLBL2_RRQ_AXIMM_LAT0_MIN", - GLBL2_RRQ_AXIMM_LAT0_MIN_MASK}, -}; - - -static struct regfield_info - glbl2_rrq_aximm_lat1_field_info[] = { - {"GLBL2_RRQ_AXIMM_LAT1_RSVD", - GLBL2_RRQ_AXIMM_LAT1_RSVD_MASK}, - {"GLBL2_RRQ_AXIMM_LAT1_OVFL", - GLBL2_RRQ_AXIMM_LAT1_OVFL_MASK}, - {"GLBL2_RRQ_AXIMM_LAT1_AVG", - GLBL2_RRQ_AXIMM_LAT1_AVG_MASK}, -}; - - -static struct regfield_info - glbl2_dbg_pcie_rq0_field_info[] = { - {"GLBL2_PCIE_RQ0_NPH_AVL", - GLBL2_PCIE_RQ0_NPH_AVL_MASK}, - {"GLBL2_PCIE_RQ0_RCB_AVL", - GLBL2_PCIE_RQ0_RCB_AVL_MASK}, - {"GLBL2_PCIE_RQ0_SLV_RD_CREDS", - GLBL2_PCIE_RQ0_SLV_RD_CREDS_MASK}, - {"GLBL2_PCIE_RQ0_TAG_EP", - GLBL2_PCIE_RQ0_TAG_EP_MASK}, -}; - - -static struct regfield_info - glbl2_dbg_pcie_rq1_field_info[] = { - {"GLBL2_PCIE_RQ1_RSVD_1", - GLBL2_PCIE_RQ1_RSVD_1_MASK}, - {"GLBL2_PCIE_RQ1_TAG_FL", - GLBL2_PCIE_RQ1_TAG_FL_MASK}, - {"GLBL2_PCIE_RQ1_WTLP_HEADER_FIFO_FL", - GLBL2_PCIE_RQ1_WTLP_HEADER_FIFO_FL_MASK}, - {"GLBL2_PCIE_RQ1_WTLP_HEADER_FIFO_EP", - GLBL2_PCIE_RQ1_WTLP_HEADER_FIFO_EP_MASK}, - {"GLBL2_PCIE_RQ1_RQ_FIFO_EP", - GLBL2_PCIE_RQ1_RQ_FIFO_EP_MASK}, - {"GLBL2_PCIE_RQ1_RQ_FIFO_FL", - GLBL2_PCIE_RQ1_RQ_FIFO_FL_MASK}, - {"GLBL2_PCIE_RQ1_TLPSM", - GLBL2_PCIE_RQ1_TLPSM_MASK}, - {"GLBL2_PCIE_RQ1_TLPSM512", - GLBL2_PCIE_RQ1_TLPSM512_MASK}, - {"GLBL2_PCIE_RQ1_RREQ_RCB_OK", - GLBL2_PCIE_RQ1_RREQ_RCB_OK_MASK}, - {"GLBL2_PCIE_RQ1_RREQ0_SLV", - GLBL2_PCIE_RQ1_RREQ0_SLV_MASK}, - {"GLBL2_PCIE_RQ1_RREQ0_VLD", - GLBL2_PCIE_RQ1_RREQ0_VLD_MASK}, - {"GLBL2_PCIE_RQ1_RREQ0_RDY", - GLBL2_PCIE_RQ1_RREQ0_RDY_MASK}, - {"GLBL2_PCIE_RQ1_RREQ1_SLV", - GLBL2_PCIE_RQ1_RREQ1_SLV_MASK}, - {"GLBL2_PCIE_RQ1_RREQ1_VLD", - GLBL2_PCIE_RQ1_RREQ1_VLD_MASK}, - {"GLBL2_PCIE_RQ1_RREQ1_RDY", - GLBL2_PCIE_RQ1_RREQ1_RDY_MASK}, - {"GLBL2_PCIE_RQ1_WTLP_REQ", - GLBL2_PCIE_RQ1_WTLP_REQ_MASK}, - {"GLBL2_PCIE_RQ1_WTLP_STRADDLE", - GLBL2_PCIE_RQ1_WTLP_STRADDLE_MASK}, -}; - - -static struct regfield_info - glbl2_dbg_aximm_wr0_field_info[] = { - {"GLBL2_AXIMM_WR0_RSVD_1", - GLBL2_AXIMM_WR0_RSVD_1_MASK}, - {"GLBL2_AXIMM_WR0_WR_REQ", - GLBL2_AXIMM_WR0_WR_REQ_MASK}, - {"GLBL2_AXIMM_WR0_WR_CHN", - GLBL2_AXIMM_WR0_WR_CHN_MASK}, - {"GLBL2_AXIMM_WR0_WTLP_DATA_FIFO_EP", - GLBL2_AXIMM_WR0_WTLP_DATA_FIFO_EP_MASK}, - {"GLBL2_AXIMM_WR0_WPL_FIFO_EP", - GLBL2_AXIMM_WR0_WPL_FIFO_EP_MASK}, - {"GLBL2_AXIMM_WR0_BRSP_CLAIM_CHN", - GLBL2_AXIMM_WR0_BRSP_CLAIM_CHN_MASK}, - {"GLBL2_AXIMM_WR0_WRREQ_CNT", - GLBL2_AXIMM_WR0_WRREQ_CNT_MASK}, - {"GLBL2_AXIMM_WR0_BID", - GLBL2_AXIMM_WR0_BID_MASK}, - {"GLBL2_AXIMM_WR0_BVALID", - GLBL2_AXIMM_WR0_BVALID_MASK}, - {"GLBL2_AXIMM_WR0_BREADY", - GLBL2_AXIMM_WR0_BREADY_MASK}, - {"GLBL2_AXIMM_WR0_WVALID", - GLBL2_AXIMM_WR0_WVALID_MASK}, - {"GLBL2_AXIMM_WR0_WREADY", - GLBL2_AXIMM_WR0_WREADY_MASK}, - {"GLBL2_AXIMM_WR0_AWID", - GLBL2_AXIMM_WR0_AWID_MASK}, - {"GLBL2_AXIMM_WR0_AWVALID", - GLBL2_AXIMM_WR0_AWVALID_MASK}, - {"GLBL2_AXIMM_WR0_AWREADY", - GLBL2_AXIMM_WR0_AWREADY_MASK}, -}; - - -static struct regfield_info - glbl2_dbg_aximm_wr1_field_info[] = { - {"GLBL2_AXIMM_WR1_RSVD_1", - GLBL2_AXIMM_WR1_RSVD_1_MASK}, - {"GLBL2_AXIMM_WR1_BRSP_CNT4", - GLBL2_AXIMM_WR1_BRSP_CNT4_MASK}, - {"GLBL2_AXIMM_WR1_BRSP_CNT3", - GLBL2_AXIMM_WR1_BRSP_CNT3_MASK}, - {"GLBL2_AXIMM_WR1_BRSP_CNT2", - GLBL2_AXIMM_WR1_BRSP_CNT2_MASK}, - {"GLBL2_AXIMM_WR1_BRSP_CNT1", - GLBL2_AXIMM_WR1_BRSP_CNT1_MASK}, - {"GLBL2_AXIMM_WR1_BRSP_CNT0", - GLBL2_AXIMM_WR1_BRSP_CNT0_MASK}, -}; - - -static struct regfield_info - glbl2_dbg_aximm_rd0_field_info[] = { - {"GLBL2_AXIMM_RD0_RSVD_1", - GLBL2_AXIMM_RD0_RSVD_1_MASK}, - {"GLBL2_AXIMM_RD0_PND_CNT", - GLBL2_AXIMM_RD0_PND_CNT_MASK}, - {"GLBL2_AXIMM_RD0_RD_REQ", - GLBL2_AXIMM_RD0_RD_REQ_MASK}, - {"GLBL2_AXIMM_RD0_RD_CHNL", - GLBL2_AXIMM_RD0_RD_CHNL_MASK}, - {"GLBL2_AXIMM_RD0_RRSP_CLAIM_CHNL", - GLBL2_AXIMM_RD0_RRSP_CLAIM_CHNL_MASK}, - {"GLBL2_AXIMM_RD0_RID", - GLBL2_AXIMM_RD0_RID_MASK}, - {"GLBL2_AXIMM_RD0_RVALID", - GLBL2_AXIMM_RD0_RVALID_MASK}, - {"GLBL2_AXIMM_RD0_RREADY", - GLBL2_AXIMM_RD0_RREADY_MASK}, - {"GLBL2_AXIMM_RD0_ARID", - GLBL2_AXIMM_RD0_ARID_MASK}, - {"GLBL2_AXIMM_RD0_ARVALID", - GLBL2_AXIMM_RD0_ARVALID_MASK}, - {"GLBL2_AXIMM_RD0_ARREADY", - GLBL2_AXIMM_RD0_ARREADY_MASK}, -}; - - -static struct regfield_info - glbl2_dbg_aximm_rd1_field_info[] = { - {"GLBL2_AXIMM_RD1_RSVD_1", - GLBL2_AXIMM_RD1_RSVD_1_MASK}, - {"GLBL2_AXIMM_RD1_RRSP_CNT4", - GLBL2_AXIMM_RD1_RRSP_CNT4_MASK}, - {"GLBL2_AXIMM_RD1_RRSP_CNT3", - GLBL2_AXIMM_RD1_RRSP_CNT3_MASK}, - {"GLBL2_AXIMM_RD1_RRSP_CNT2", - GLBL2_AXIMM_RD1_RRSP_CNT2_MASK}, - {"GLBL2_AXIMM_RD1_RRSP_CNT1", - GLBL2_AXIMM_RD1_RRSP_CNT1_MASK}, - {"GLBL2_AXIMM_RD1_RRSP_CNT0", - GLBL2_AXIMM_RD1_RRSP_CNT0_MASK}, -}; - - -static struct regfield_info - glbl2_dbg_fab0_field_info[] = { - {"GLBL2_FAB0_H2C_INB_CONV_IN_VLD", - GLBL2_FAB0_H2C_INB_CONV_IN_VLD_MASK}, - {"GLBL2_FAB0_H2C_INB_CONV_IN_RDY", - GLBL2_FAB0_H2C_INB_CONV_IN_RDY_MASK}, - {"GLBL2_FAB0_H2C_SEG_IN_VLD", - GLBL2_FAB0_H2C_SEG_IN_VLD_MASK}, - {"GLBL2_FAB0_H2C_SEG_IN_RDY", - GLBL2_FAB0_H2C_SEG_IN_RDY_MASK}, - {"GLBL2_FAB0_H2C_SEG_OUT_VLD", - GLBL2_FAB0_H2C_SEG_OUT_VLD_MASK}, - {"GLBL2_FAB0_H2C_SEG_OUT_RDY", - GLBL2_FAB0_H2C_SEG_OUT_RDY_MASK}, - {"GLBL2_FAB0_H2C_MST_CRDT_STAT", - GLBL2_FAB0_H2C_MST_CRDT_STAT_MASK}, - {"GLBL2_FAB0_C2H_SLV_AFIFO_FULL", - GLBL2_FAB0_C2H_SLV_AFIFO_FULL_MASK}, - {"GLBL2_FAB0_C2H_SLV_AFIFO_EMPTY", - GLBL2_FAB0_C2H_SLV_AFIFO_EMPTY_MASK}, - {"GLBL2_FAB0_C2H_DESEG_SEG_VLD", - GLBL2_FAB0_C2H_DESEG_SEG_VLD_MASK}, - {"GLBL2_FAB0_C2H_DESEG_SEG_RDY", - GLBL2_FAB0_C2H_DESEG_SEG_RDY_MASK}, - {"GLBL2_FAB0_C2H_DESEG_OUT_VLD", - GLBL2_FAB0_C2H_DESEG_OUT_VLD_MASK}, - {"GLBL2_FAB0_C2H_DESEG_OUT_RDY", - GLBL2_FAB0_C2H_DESEG_OUT_RDY_MASK}, - {"GLBL2_FAB0_C2H_INB_DECONV_OUT_VLD", - GLBL2_FAB0_C2H_INB_DECONV_OUT_VLD_MASK}, - {"GLBL2_FAB0_C2H_INB_DECONV_OUT_RDY", - GLBL2_FAB0_C2H_INB_DECONV_OUT_RDY_MASK}, - {"GLBL2_FAB0_C2H_DSC_CRDT_AFIFO_FULL", - GLBL2_FAB0_C2H_DSC_CRDT_AFIFO_FULL_MASK}, - {"GLBL2_FAB0_C2H_DSC_CRDT_AFIFO_EMPTY", - GLBL2_FAB0_C2H_DSC_CRDT_AFIFO_EMPTY_MASK}, - {"GLBL2_FAB0_IRQ_IN_AFIFO_FULL", - GLBL2_FAB0_IRQ_IN_AFIFO_FULL_MASK}, - {"GLBL2_FAB0_IRQ_IN_AFIFO_EMPTY", - GLBL2_FAB0_IRQ_IN_AFIFO_EMPTY_MASK}, - {"GLBL2_FAB0_IMM_CRD_AFIFO_EMPTY", - GLBL2_FAB0_IMM_CRD_AFIFO_EMPTY_MASK}, -}; - - -static struct regfield_info - glbl2_dbg_fab1_field_info[] = { - {"GLBL2_FAB1_BYP_OUT_CRDT_STAT", - GLBL2_FAB1_BYP_OUT_CRDT_STAT_MASK}, - {"GLBL2_FAB1_TM_DSC_STS_CRDT_STAT", - GLBL2_FAB1_TM_DSC_STS_CRDT_STAT_MASK}, - {"GLBL2_FAB1_C2H_CMN_AFIFO_FULL", - GLBL2_FAB1_C2H_CMN_AFIFO_FULL_MASK}, - {"GLBL2_FAB1_C2H_CMN_AFIFO_EMPTY", - GLBL2_FAB1_C2H_CMN_AFIFO_EMPTY_MASK}, - {"GLBL2_FAB1_RSVD_1", - GLBL2_FAB1_RSVD_1_MASK}, - {"GLBL2_FAB1_C2H_BYP_IN_AFIFO_FULL", - GLBL2_FAB1_C2H_BYP_IN_AFIFO_FULL_MASK}, - {"GLBL2_FAB1_RSVD_2", - GLBL2_FAB1_RSVD_2_MASK}, - {"GLBL2_FAB1_C2H_BYP_IN_AFIFO_EMPTY", - GLBL2_FAB1_C2H_BYP_IN_AFIFO_EMPTY_MASK}, - {"GLBL2_FAB1_RSVD_3", - GLBL2_FAB1_RSVD_3_MASK}, - {"GLBL2_FAB1_H2C_BYP_IN_AFIFO_FULL", - GLBL2_FAB1_H2C_BYP_IN_AFIFO_FULL_MASK}, - {"GLBL2_FAB1_RSVD_4", - GLBL2_FAB1_RSVD_4_MASK}, - {"GLBL2_FAB1_H2C_BYP_IN_AFIFO_EMPTY", - GLBL2_FAB1_H2C_BYP_IN_AFIFO_EMPTY_MASK}, -}; - - -static struct regfield_info - glbl2_dbg_match_sel_field_info[] = { - {"GLBL2_MATCH_SEL_RSV", - GLBL2_MATCH_SEL_RSV_MASK}, - {"GLBL2_MATCH_SEL_CSR_SEL", - GLBL2_MATCH_SEL_CSR_SEL_MASK}, - {"GLBL2_MATCH_SEL_CSR_EN", - GLBL2_MATCH_SEL_CSR_EN_MASK}, - {"GLBL2_MATCH_SEL_ROTATE1", - GLBL2_MATCH_SEL_ROTATE1_MASK}, - {"GLBL2_MATCH_SEL_ROTATE0", - GLBL2_MATCH_SEL_ROTATE0_MASK}, - {"GLBL2_MATCH_SEL_SEL", - GLBL2_MATCH_SEL_SEL_MASK}, -}; - - -static struct regfield_info - glbl2_dbg_match_msk_field_info[] = { - {"GLBL2_MATCH_MSK", - GLBL2_MATCH_MSK_MASK}, -}; - - -static struct regfield_info - glbl2_dbg_match_pat_field_info[] = { - {"GLBL2_MATCH_PAT_PATTERN", - GLBL2_MATCH_PAT_PATTERN_MASK}, -}; - - -static struct regfield_info - glbl_rng_sz_1_field_info[] = { - {"GLBL_RNG_SZ_1_RSVD_1", - GLBL_RNG_SZ_1_RSVD_1_MASK}, - {"GLBL_RNG_SZ_1_RING_SIZE", - GLBL_RNG_SZ_1_RING_SIZE_MASK}, -}; - - -static struct regfield_info - glbl_rng_sz_2_field_info[] = { - {"GLBL_RNG_SZ_2_RSVD_1", - GLBL_RNG_SZ_2_RSVD_1_MASK}, - {"GLBL_RNG_SZ_2_RING_SIZE", - GLBL_RNG_SZ_2_RING_SIZE_MASK}, -}; - - -static struct regfield_info - glbl_rng_sz_3_field_info[] = { - {"GLBL_RNG_SZ_3_RSVD_1", - GLBL_RNG_SZ_3_RSVD_1_MASK}, - {"GLBL_RNG_SZ_3_RING_SIZE", - GLBL_RNG_SZ_3_RING_SIZE_MASK}, -}; - - -static struct regfield_info - glbl_rng_sz_4_field_info[] = { - {"GLBL_RNG_SZ_4_RSVD_1", - GLBL_RNG_SZ_4_RSVD_1_MASK}, - {"GLBL_RNG_SZ_4_RING_SIZE", - GLBL_RNG_SZ_4_RING_SIZE_MASK}, -}; - - -static struct regfield_info - glbl_rng_sz_5_field_info[] = { - {"GLBL_RNG_SZ_5_RSVD_1", - GLBL_RNG_SZ_5_RSVD_1_MASK}, - {"GLBL_RNG_SZ_5_RING_SIZE", - GLBL_RNG_SZ_5_RING_SIZE_MASK}, -}; - - -static struct regfield_info - glbl_rng_sz_6_field_info[] = { - {"GLBL_RNG_SZ_6_RSVD_1", - GLBL_RNG_SZ_6_RSVD_1_MASK}, - {"GLBL_RNG_SZ_6_RING_SIZE", - GLBL_RNG_SZ_6_RING_SIZE_MASK}, -}; - - -static struct regfield_info - glbl_rng_sz_7_field_info[] = { - {"GLBL_RNG_SZ_7_RSVD_1", - GLBL_RNG_SZ_7_RSVD_1_MASK}, - {"GLBL_RNG_SZ_7_RING_SIZE", - GLBL_RNG_SZ_7_RING_SIZE_MASK}, -}; - - -static struct regfield_info - glbl_rng_sz_8_field_info[] = { - {"GLBL_RNG_SZ_8_RSVD_1", - GLBL_RNG_SZ_8_RSVD_1_MASK}, - {"GLBL_RNG_SZ_8_RING_SIZE", - GLBL_RNG_SZ_8_RING_SIZE_MASK}, -}; - - -static struct regfield_info - glbl_rng_sz_9_field_info[] = { - {"GLBL_RNG_SZ_9_RSVD_1", - GLBL_RNG_SZ_9_RSVD_1_MASK}, - {"GLBL_RNG_SZ_9_RING_SIZE", - GLBL_RNG_SZ_9_RING_SIZE_MASK}, -}; - - -static struct regfield_info - glbl_rng_sz_a_field_info[] = { - {"GLBL_RNG_SZ_A_RSVD_1", - GLBL_RNG_SZ_A_RSVD_1_MASK}, - {"GLBL_RNG_SZ_A_RING_SIZE", - GLBL_RNG_SZ_A_RING_SIZE_MASK}, -}; - - -static struct regfield_info - glbl_rng_sz_b_field_info[] = { - {"GLBL_RNG_SZ_B_RSVD_1", - GLBL_RNG_SZ_B_RSVD_1_MASK}, - {"GLBL_RNG_SZ_B_RING_SIZE", - GLBL_RNG_SZ_B_RING_SIZE_MASK}, -}; - - -static struct regfield_info - glbl_rng_sz_c_field_info[] = { - {"GLBL_RNG_SZ_C_RSVD_1", - GLBL_RNG_SZ_C_RSVD_1_MASK}, - {"GLBL_RNG_SZ_C_RING_SIZE", - GLBL_RNG_SZ_C_RING_SIZE_MASK}, -}; - - -static struct regfield_info - glbl_rng_sz_d_field_info[] = { - {"GLBL_RNG_SZ_D_RSVD_1", - GLBL_RNG_SZ_D_RSVD_1_MASK}, - {"GLBL_RNG_SZ_D_RING_SIZE", - GLBL_RNG_SZ_D_RING_SIZE_MASK}, -}; - - -static struct regfield_info - glbl_rng_sz_e_field_info[] = { - {"GLBL_RNG_SZ_E_RSVD_1", - GLBL_RNG_SZ_E_RSVD_1_MASK}, - {"GLBL_RNG_SZ_E_RING_SIZE", - GLBL_RNG_SZ_E_RING_SIZE_MASK}, -}; - - -static struct regfield_info - glbl_rng_sz_f_field_info[] = { - {"GLBL_RNG_SZ_F_RSVD_1", - GLBL_RNG_SZ_F_RSVD_1_MASK}, - {"GLBL_RNG_SZ_F_RING_SIZE", - GLBL_RNG_SZ_F_RING_SIZE_MASK}, -}; - - -static struct regfield_info - glbl_rng_sz_10_field_info[] = { - {"GLBL_RNG_SZ_10_RSVD_1", - GLBL_RNG_SZ_10_RSVD_1_MASK}, - {"GLBL_RNG_SZ_10_RING_SIZE", - GLBL_RNG_SZ_10_RING_SIZE_MASK}, -}; - - -static struct regfield_info - glbl_err_stat_field_info[] = { - {"GLBL_ERR_STAT_RSVD_1", - GLBL_ERR_STAT_RSVD_1_MASK}, - {"GLBL_ERR_STAT_ERR_FAB", - GLBL_ERR_STAT_ERR_FAB_MASK}, - {"GLBL_ERR_STAT_ERR_H2C_ST", - GLBL_ERR_STAT_ERR_H2C_ST_MASK}, - {"GLBL_ERR_STAT_ERR_BDG", - GLBL_ERR_STAT_ERR_BDG_MASK}, - {"GLBL_ERR_STAT_IND_CTXT_CMD_ERR", - GLBL_ERR_STAT_IND_CTXT_CMD_ERR_MASK}, - {"GLBL_ERR_STAT_ERR_C2H_ST", - GLBL_ERR_STAT_ERR_C2H_ST_MASK}, - {"GLBL_ERR_STAT_ERR_C2H_MM_1", - GLBL_ERR_STAT_ERR_C2H_MM_1_MASK}, - {"GLBL_ERR_STAT_ERR_C2H_MM_0", - GLBL_ERR_STAT_ERR_C2H_MM_0_MASK}, - {"GLBL_ERR_STAT_ERR_H2C_MM_1", - GLBL_ERR_STAT_ERR_H2C_MM_1_MASK}, - {"GLBL_ERR_STAT_ERR_H2C_MM_0", - GLBL_ERR_STAT_ERR_H2C_MM_0_MASK}, - {"GLBL_ERR_STAT_ERR_TRQ", - GLBL_ERR_STAT_ERR_TRQ_MASK}, - {"GLBL_ERR_STAT_ERR_DSC", - GLBL_ERR_STAT_ERR_DSC_MASK}, - {"GLBL_ERR_STAT_ERR_RAM_DBE", - GLBL_ERR_STAT_ERR_RAM_DBE_MASK}, - {"GLBL_ERR_STAT_ERR_RAM_SBE", - GLBL_ERR_STAT_ERR_RAM_SBE_MASK}, -}; - - -static struct regfield_info - glbl_err_mask_field_info[] = { - {"GLBL_ERR", - GLBL_ERR_MASK}, -}; - - -static struct regfield_info - glbl_dsc_cfg_field_info[] = { - {"GLBL_DSC_CFG_RSVD_1", - GLBL_DSC_CFG_RSVD_1_MASK}, - {"GLBL_DSC_CFG_C2H_UODSC_LIMIT", - GLBL_DSC_CFG_C2H_UODSC_LIMIT_MASK}, - {"GLBL_DSC_CFG_H2C_UODSC_LIMIT", - GLBL_DSC_CFG_H2C_UODSC_LIMIT_MASK}, - {"GLBL_DSC_CFG_UNC_OVR_COR", - GLBL_DSC_CFG_UNC_OVR_COR_MASK}, - {"GLBL_DSC_CFG_CTXT_FER_DIS", - GLBL_DSC_CFG_CTXT_FER_DIS_MASK}, - {"GLBL_DSC_CFG_RSVD_2", - GLBL_DSC_CFG_RSVD_2_MASK}, - {"GLBL_DSC_CFG_MAXFETCH", - GLBL_DSC_CFG_MAXFETCH_MASK}, - {"GLBL_DSC_CFG_WB_ACC_INT", - GLBL_DSC_CFG_WB_ACC_INT_MASK}, -}; - - -static struct regfield_info - glbl_dsc_err_sts_field_info[] = { - {"GLBL_DSC_ERR_STS_RSVD_1", - GLBL_DSC_ERR_STS_RSVD_1_MASK}, - {"GLBL_DSC_ERR_STS_PORT_ID", - GLBL_DSC_ERR_STS_PORT_ID_MASK}, - {"GLBL_DSC_ERR_STS_SBE", - GLBL_DSC_ERR_STS_SBE_MASK}, - {"GLBL_DSC_ERR_STS_DBE", - GLBL_DSC_ERR_STS_DBE_MASK}, - {"GLBL_DSC_ERR_STS_RQ_CANCEL", - GLBL_DSC_ERR_STS_RQ_CANCEL_MASK}, - {"GLBL_DSC_ERR_STS_DSC", - GLBL_DSC_ERR_STS_DSC_MASK}, - {"GLBL_DSC_ERR_STS_DMA", - GLBL_DSC_ERR_STS_DMA_MASK}, - {"GLBL_DSC_ERR_STS_FLR_CANCEL", - GLBL_DSC_ERR_STS_FLR_CANCEL_MASK}, - {"GLBL_DSC_ERR_STS_RSVD_2", - GLBL_DSC_ERR_STS_RSVD_2_MASK}, - {"GLBL_DSC_ERR_STS_DAT_POISON", - GLBL_DSC_ERR_STS_DAT_POISON_MASK}, - {"GLBL_DSC_ERR_STS_TIMEOUT", - GLBL_DSC_ERR_STS_TIMEOUT_MASK}, - {"GLBL_DSC_ERR_STS_FLR", - GLBL_DSC_ERR_STS_FLR_MASK}, - {"GLBL_DSC_ERR_STS_TAG", - GLBL_DSC_ERR_STS_TAG_MASK}, - {"GLBL_DSC_ERR_STS_ADDR", - GLBL_DSC_ERR_STS_ADDR_MASK}, - {"GLBL_DSC_ERR_STS_PARAM", - GLBL_DSC_ERR_STS_PARAM_MASK}, - {"GLBL_DSC_ERR_STS_BCNT", - GLBL_DSC_ERR_STS_BCNT_MASK}, - {"GLBL_DSC_ERR_STS_UR_CA", - GLBL_DSC_ERR_STS_UR_CA_MASK}, - {"GLBL_DSC_ERR_STS_POISON", - GLBL_DSC_ERR_STS_POISON_MASK}, -}; - - -static struct regfield_info - glbl_dsc_err_msk_field_info[] = { - {"GLBL_DSC_ERR_MSK", - GLBL_DSC_ERR_MSK_MASK}, -}; - - -static struct regfield_info - glbl_dsc_err_log0_field_info[] = { - {"GLBL_DSC_ERR_LOG0_VALID", - GLBL_DSC_ERR_LOG0_VALID_MASK}, - {"GLBL_DSC_ERR_LOG0_SEL", - GLBL_DSC_ERR_LOG0_SEL_MASK}, - {"GLBL_DSC_ERR_LOG0_RSVD_1", - GLBL_DSC_ERR_LOG0_RSVD_1_MASK}, - {"GLBL_DSC_ERR_LOG0_QID", - GLBL_DSC_ERR_LOG0_QID_MASK}, -}; - - -static struct regfield_info - glbl_dsc_err_log1_field_info[] = { - {"GLBL_DSC_ERR_LOG1_RSVD_1", - GLBL_DSC_ERR_LOG1_RSVD_1_MASK}, - {"GLBL_DSC_ERR_LOG1_CIDX", - GLBL_DSC_ERR_LOG1_CIDX_MASK}, - {"GLBL_DSC_ERR_LOG1_RSVD_2", - GLBL_DSC_ERR_LOG1_RSVD_2_MASK}, - {"GLBL_DSC_ERR_LOG1_SUB_TYPE", - GLBL_DSC_ERR_LOG1_SUB_TYPE_MASK}, - {"GLBL_DSC_ERR_LOG1_ERR_TYPE", - GLBL_DSC_ERR_LOG1_ERR_TYPE_MASK}, -}; - - -static struct regfield_info - glbl_trq_err_sts_field_info[] = { - {"GLBL_TRQ_ERR_STS_RSVD_1", - GLBL_TRQ_ERR_STS_RSVD_1_MASK}, - {"GLBL_TRQ_ERR_STS_TCP_QSPC_TIMEOUT", - GLBL_TRQ_ERR_STS_TCP_QSPC_TIMEOUT_MASK}, - {"GLBL_TRQ_ERR_STS_RSVD_2", - GLBL_TRQ_ERR_STS_RSVD_2_MASK}, - {"GLBL_TRQ_ERR_STS_QID_RANGE", - GLBL_TRQ_ERR_STS_QID_RANGE_MASK}, - {"GLBL_TRQ_ERR_STS_QSPC_UNMAPPED", - GLBL_TRQ_ERR_STS_QSPC_UNMAPPED_MASK}, - {"GLBL_TRQ_ERR_STS_TCP_CSR_TIMEOUT", - GLBL_TRQ_ERR_STS_TCP_CSR_TIMEOUT_MASK}, - {"GLBL_TRQ_ERR_STS_RSVD_3", - GLBL_TRQ_ERR_STS_RSVD_3_MASK}, - {"GLBL_TRQ_ERR_STS_VF_ACCESS_ERR", - GLBL_TRQ_ERR_STS_VF_ACCESS_ERR_MASK}, - {"GLBL_TRQ_ERR_STS_CSR_UNMAPPED", - GLBL_TRQ_ERR_STS_CSR_UNMAPPED_MASK}, -}; - - -static struct regfield_info - glbl_trq_err_msk_field_info[] = { - {"GLBL_TRQ_ERR_MSK", - GLBL_TRQ_ERR_MSK_MASK}, -}; - - -static struct regfield_info - glbl_trq_err_log_field_info[] = { - {"GLBL_TRQ_ERR_LOG_SRC", - GLBL_TRQ_ERR_LOG_SRC_MASK}, - {"GLBL_TRQ_ERR_LOG_TARGET", - GLBL_TRQ_ERR_LOG_TARGET_MASK}, - {"GLBL_TRQ_ERR_LOG_FUNC", - GLBL_TRQ_ERR_LOG_FUNC_MASK}, - {"GLBL_TRQ_ERR_LOG_ADDRESS", - GLBL_TRQ_ERR_LOG_ADDRESS_MASK}, -}; - - -static struct regfield_info - glbl_dsc_dbg_dat0_field_info[] = { - {"GLBL_DSC_DAT0_RSVD_1", - GLBL_DSC_DAT0_RSVD_1_MASK}, - {"GLBL_DSC_DAT0_CTXT_ARB_DIR", - GLBL_DSC_DAT0_CTXT_ARB_DIR_MASK}, - {"GLBL_DSC_DAT0_CTXT_ARB_QID", - GLBL_DSC_DAT0_CTXT_ARB_QID_MASK}, - {"GLBL_DSC_DAT0_CTXT_ARB_REQ", - GLBL_DSC_DAT0_CTXT_ARB_REQ_MASK}, - {"GLBL_DSC_DAT0_IRQ_FIFO_FL", - GLBL_DSC_DAT0_IRQ_FIFO_FL_MASK}, - {"GLBL_DSC_DAT0_TMSTALL", - GLBL_DSC_DAT0_TMSTALL_MASK}, - {"GLBL_DSC_DAT0_RRQ_STALL", - GLBL_DSC_DAT0_RRQ_STALL_MASK}, - {"GLBL_DSC_DAT0_RCP_FIFO_SPC_STALL", - GLBL_DSC_DAT0_RCP_FIFO_SPC_STALL_MASK}, - {"GLBL_DSC_DAT0_RRQ_FIFO_SPC_STALL", - GLBL_DSC_DAT0_RRQ_FIFO_SPC_STALL_MASK}, - {"GLBL_DSC_DAT0_FAB_MRKR_RSP_STALL", - GLBL_DSC_DAT0_FAB_MRKR_RSP_STALL_MASK}, - {"GLBL_DSC_DAT0_DSC_OUT_STALL", - GLBL_DSC_DAT0_DSC_OUT_STALL_MASK}, -}; - - -static struct regfield_info - glbl_dsc_dbg_dat1_field_info[] = { - {"GLBL_DSC_DAT1_RSVD_1", - GLBL_DSC_DAT1_RSVD_1_MASK}, - {"GLBL_DSC_DAT1_EVT_SPC_C2H", - GLBL_DSC_DAT1_EVT_SPC_C2H_MASK}, - {"GLBL_DSC_DAT1_EVT_SP_H2C", - GLBL_DSC_DAT1_EVT_SP_H2C_MASK}, - {"GLBL_DSC_DAT1_DSC_SPC_C2H", - GLBL_DSC_DAT1_DSC_SPC_C2H_MASK}, - {"GLBL_DSC_DAT1_DSC_SPC_H2C", - GLBL_DSC_DAT1_DSC_SPC_H2C_MASK}, -}; - - -static struct regfield_info - glbl_dsc_dbg_ctl_field_info[] = { - {"GLBL_DSC_CTL_RSVD_1", - GLBL_DSC_CTL_RSVD_1_MASK}, - {"GLBL_DSC_CTL_LAT_QID", - GLBL_DSC_CTL_LAT_QID_MASK}, - {"GLBL_DSC_CTL_DSC_ENG_LAT_CLR", - GLBL_DSC_CTL_DSC_ENG_LAT_CLR_MASK}, - {"GLBL_DSC_CTL_SELECT", - GLBL_DSC_CTL_SELECT_MASK}, -}; - - -static struct regfield_info - glbl_dsc_err_log2_field_info[] = { - {"GLBL_DSC_ERR_LOG2_OLD_PIDX", - GLBL_DSC_ERR_LOG2_OLD_PIDX_MASK}, - {"GLBL_DSC_ERR_LOG2_NEW_PIDX", - GLBL_DSC_ERR_LOG2_NEW_PIDX_MASK}, -}; - - -static struct regfield_info - glbl_glbl_interrupt_cfg_field_info[] = { - {"GLBL_GLBL_INTERRUPT_CFG_RSVD_1", - GLBL_GLBL_INTERRUPT_CFG_RSVD_1_MASK}, - {"GLBL_GLBL_INTERRUPT_CFG_LGCY_INTR_PENDING", - GLBL_GLBL_INTERRUPT_CFG_LGCY_INTR_PENDING_MASK}, - {"GLBL_GLBL_INTERRUPT_CFG_EN_LGCY_INTR", - GLBL_GLBL_INTERRUPT_CFG_EN_LGCY_INTR_MASK}, -}; - - -static struct regfield_info - glbl_vch_host_profile_field_info[] = { - {"GLBL_VCH_HOST_PROFILE_RSVD_1", - GLBL_VCH_HOST_PROFILE_RSVD_1_MASK}, - {"GLBL_VCH_HOST_PROFILE_2C_MM", - GLBL_VCH_HOST_PROFILE_2C_MM_MASK}, - {"GLBL_VCH_HOST_PROFILE_2C_ST", - GLBL_VCH_HOST_PROFILE_2C_ST_MASK}, - {"GLBL_VCH_HOST_PROFILE_VCH_DSC", - GLBL_VCH_HOST_PROFILE_VCH_DSC_MASK}, - {"GLBL_VCH_HOST_PROFILE_VCH_INT_MSG", - GLBL_VCH_HOST_PROFILE_VCH_INT_MSG_MASK}, - {"GLBL_VCH_HOST_PROFILE_VCH_INT_AGGR", - GLBL_VCH_HOST_PROFILE_VCH_INT_AGGR_MASK}, - {"GLBL_VCH_HOST_PROFILE_VCH_CMPT", - GLBL_VCH_HOST_PROFILE_VCH_CMPT_MASK}, - {"GLBL_VCH_HOST_PROFILE_VCH_C2H_PLD", - GLBL_VCH_HOST_PROFILE_VCH_C2H_PLD_MASK}, -}; - - -static struct regfield_info - glbl_bridge_host_profile_field_info[] = { - {"GLBL_BRIDGE_HOST_PROFILE_RSVD_1", - GLBL_BRIDGE_HOST_PROFILE_RSVD_1_MASK}, - {"GLBL_BRIDGE_HOST_PROFILE_BDGID", - GLBL_BRIDGE_HOST_PROFILE_BDGID_MASK}, -}; - - -static struct regfield_info - aximm_irq_dest_addr_field_info[] = { - {"AXIMM_IRQ_DEST_ADDR_ADDR", - AXIMM_IRQ_DEST_ADDR_ADDR_MASK}, -}; - - -static struct regfield_info - fab_err_log_field_info[] = { - {"FAB_ERR_LOG_RSVD_1", - FAB_ERR_LOG_RSVD_1_MASK}, - {"FAB_ERR_LOG_SRC", - FAB_ERR_LOG_SRC_MASK}, -}; - - -static struct regfield_info - glbl_req_err_sts_field_info[] = { - {"GLBL_REQ_ERR_STS_RSVD_1", - GLBL_REQ_ERR_STS_RSVD_1_MASK}, - {"GLBL_REQ_ERR_STS_RC_DISCONTINUE", - GLBL_REQ_ERR_STS_RC_DISCONTINUE_MASK}, - {"GLBL_REQ_ERR_STS_RC_PRTY", - GLBL_REQ_ERR_STS_RC_PRTY_MASK}, - {"GLBL_REQ_ERR_STS_RC_FLR", - GLBL_REQ_ERR_STS_RC_FLR_MASK}, - {"GLBL_REQ_ERR_STS_RC_TIMEOUT", - GLBL_REQ_ERR_STS_RC_TIMEOUT_MASK}, - {"GLBL_REQ_ERR_STS_RC_INV_BCNT", - GLBL_REQ_ERR_STS_RC_INV_BCNT_MASK}, - {"GLBL_REQ_ERR_STS_RC_INV_TAG", - GLBL_REQ_ERR_STS_RC_INV_TAG_MASK}, - {"GLBL_REQ_ERR_STS_RC_START_ADDR_MISMCH", - GLBL_REQ_ERR_STS_RC_START_ADDR_MISMCH_MASK}, - {"GLBL_REQ_ERR_STS_RC_RID_TC_ATTR_MISMCH", - GLBL_REQ_ERR_STS_RC_RID_TC_ATTR_MISMCH_MASK}, - {"GLBL_REQ_ERR_STS_RC_NO_DATA", - GLBL_REQ_ERR_STS_RC_NO_DATA_MASK}, - {"GLBL_REQ_ERR_STS_RC_UR_CA_CRS", - GLBL_REQ_ERR_STS_RC_UR_CA_CRS_MASK}, - {"GLBL_REQ_ERR_STS_RC_POISONED", - GLBL_REQ_ERR_STS_RC_POISONED_MASK}, -}; - - -static struct regfield_info - glbl_req_err_msk_field_info[] = { - {"GLBL_REQ_ERR_MSK", - GLBL_REQ_ERR_MSK_MASK}, -}; - - -static struct regfield_info - glbl_dsc_dbg_lat0_a_field_info[] = { - {"GLBL_DSC_LAT0_A_LAT_MAX", - GLBL_DSC_LAT0_A_LAT_MAX_MASK}, - {"GLBL_DSC_LAT0_A_LAT_MIN", - GLBL_DSC_LAT0_A_LAT_MIN_MASK}, -}; - - -static struct regfield_info - glbl_dsc_dbg_lat1_a_field_info[] = { - {"GLBL_DSC_LAT1_A_RSVD", - GLBL_DSC_LAT1_A_RSVD_MASK}, - {"GLBL_DSC_LAT1_A_LAT_OVF", - GLBL_DSC_LAT1_A_LAT_OVF_MASK}, - {"GLBL_DSC_LAT1_A_LAT_AVG", - GLBL_DSC_LAT1_A_LAT_AVG_MASK}, -}; - - -static struct regfield_info - glbl_dsc_crd_ctr0_a_field_info[] = { - {"GLBL_DSC_CRD_CTR0_A_CRD_RCV_CNT", - GLBL_DSC_CRD_CTR0_A_CRD_RCV_CNT_MASK}, -}; - - -static struct regfield_info - glbl_dsc_crd_ctr1_a_field_info[] = { - {"GLBL_DSC_CRD_CTR1_A_CRD_RCV_CNT", - GLBL_DSC_CRD_CTR1_A_CRD_RCV_CNT_MASK}, -}; - - -static struct regfield_info - glbl_dsc_crd_ctr2_a_field_info[] = { - {"GLBL_DSC_CRD_CTR2_A_CRD_RCV_NRDY_CNT", - GLBL_DSC_CRD_CTR2_A_CRD_RCV_NRDY_CNT_MASK}, -}; - - -static struct regfield_info - glbl_dsc_crd_ctr3_a_field_info[] = { - {"GLBL_DSC_CRD_CTR3_A_CRD_RCV_NRDY_CNT", - GLBL_DSC_CRD_CTR3_A_CRD_RCV_NRDY_CNT_MASK}, -}; - - -static struct regfield_info - glbl_dsc_imm_crd_ctr0_a_field_info[] = { - {"GLBL_DSC_IMM_CRD_CTR0_A_RCV_CNT", - GLBL_DSC_IMM_CRD_CTR0_A_RCV_CNT_MASK}, -}; - - -static struct regfield_info - glbl_dsc_imm_crd_ctr1_a_field_info[] = { - {"GLBL_DSC_IMM_CRD_CTR1_A_RCV_CNT", - GLBL_DSC_IMM_CRD_CTR1_A_RCV_CNT_MASK}, -}; - - -static struct regfield_info - glbl_dsc_imm_crd_ctr2_a_field_info[] = { - {"GLBL_DSC_IMM_CRD_CTR2_A_RCV_NRDY_CNT", - GLBL_DSC_IMM_CRD_CTR2_A_RCV_NRDY_CNT_MASK}, -}; - - -static struct regfield_info - glbl_dsc_imm_crd_ctr3_a_field_info[] = { - {"GLBL_DSC_IMM_CRD_CTR3_A_RCV_NRDY_CNT", - GLBL_DSC_IMM_CRD_CTR3_A_RCV_NRDY_CNT_MASK}, -}; - - -static struct regfield_info - glbl_dsc_h2c_out_ctr0_a_field_info[] = { - {"GLBL_DSC_H2C_OUT_CTR0_A_H2CVLD_CNT", - GLBL_DSC_H2C_OUT_CTR0_A_H2CVLD_CNT_MASK}, -}; - - -static struct regfield_info - glbl_dsc_h2c_out_ctr1_a_field_info[] = { - {"GLBL_DSC_H2C_OUT_CTR1_A_H2CVLD_CNT", - GLBL_DSC_H2C_OUT_CTR1_A_H2CVLD_CNT_MASK}, -}; - - -static struct regfield_info - glbl_dsc_h2c_out_ctr2_a_field_info[] = { - {"GLBL_DSC_H2C_OUT_CTR2_A_H2CVLD_NRDY_CNT", - GLBL_DSC_H2C_OUT_CTR2_A_H2CVLD_NRDY_CNT_MASK}, -}; - - -static struct regfield_info - glbl_dsc_h2c_out_ctr3_a_field_info[] = { - {"GLBL_DSC_H2C_OUT_CTR3_A_H2CVLD_NRDY_CNT", - GLBL_DSC_H2C_OUT_CTR3_A_H2CVLD_NRDY_CNT_MASK}, -}; - - -static struct regfield_info - glbl_dsc_c2h_out_ctr0_a_field_info[] = { - {"GLBL_DSC_C2H_OUT_CTR0_A_C2HVLD_CNT", - GLBL_DSC_C2H_OUT_CTR0_A_C2HVLD_CNT_MASK}, -}; - - -static struct regfield_info - glbl_dsc_c2h_out_ctr1_a_field_info[] = { - {"GLBL_DSC_C2H_OUT_CTR1_A_C2HVLD_CNT", - GLBL_DSC_C2H_OUT_CTR1_A_C2HVLD_CNT_MASK}, -}; - - -static struct regfield_info - glbl_dsc_c2h_out_ctr2_a_field_info[] = { - {"GLBL_DSC_C2H_OUT_CTR2_A_C2HVLD_NRDY_CNT", - GLBL_DSC_C2H_OUT_CTR2_A_C2HVLD_NRDY_CNT_MASK}, -}; - - -static struct regfield_info - glbl_dsc_c2h_out_ctr3_a_field_info[] = { - {"GLBL_DSC_C2H_OUT_CTR3_A_C2HVLD_NRDY_CNT", - GLBL_DSC_C2H_OUT_CTR3_A_C2HVLD_NRDY_CNT_MASK}, -}; - - -static struct regfield_info - t_field_info[] = { - {"T_USER_CTR_MAX", - T_USER_CTR_MAX_MASK}, -}; - - -static struct regfield_info - glbl_perf_cntr_ctl_a1_field_info[] = { - {"GLBL_PERF_CNTR_CTL_A1_RSVD", - GLBL_PERF_CNTR_CTL_A1_RSVD_MASK}, - {"GLBL_PERF_CNTR_CTL_A1_USER_CTR_CLEAR", - GLBL_PERF_CNTR_CTL_A1_USER_CTR_CLEAR_MASK}, - {"GLBL_PERF_CNTR_CTL_A1_USER_CTR_READ", - GLBL_PERF_CNTR_CTL_A1_USER_CTR_READ_MASK}, - {"GLBL_PERF_CNTR_CTL_A1_USER_CTR_MAX", - GLBL_PERF_CNTR_CTL_A1_USER_CTR_MAX_MASK}, -}; - - -static struct regfield_info - glbl_free_cnt_a0_field_info[] = { - {"GLBL_FREE_CNT_A0_S", - GLBL_FREE_CNT_A0_S_MASK}, -}; - - -static struct regfield_info - glbl_free_cnt_a1_field_info[] = { - {"GLBL_FREE_CNT_A1_RSVD", - GLBL_FREE_CNT_A1_RSVD_MASK}, - {"GLBL_FREE_CNT_A1_S", - GLBL_FREE_CNT_A1_S_MASK}, -}; - - -static struct regfield_info - glbl_axis_h2c_cnt_a0_field_info[] = { - {"GLBL_AXIS_H2C_CNT_A0_MPKT_CNTS", - GLBL_AXIS_H2C_CNT_A0_MPKT_CNTS_MASK}, -}; - - -static struct regfield_info - glbl_axis_h2c_cnt_a1_field_info[] = { - {"GLBL_AXIS_H2C_CNT_A1_MIDLE_CNTS", - GLBL_AXIS_H2C_CNT_A1_MIDLE_CNTS_MASK}, - {"GLBL_AXIS_H2C_CNT_A1_MPKT_CNTS", - GLBL_AXIS_H2C_CNT_A1_MPKT_CNTS_MASK}, -}; - - -static struct regfield_info - glbl_axis_h2c_cnt_a2_field_info[] = { - {"GLBL_AXIS_H2C_CNT_A2_MIDLE_CNTS", - GLBL_AXIS_H2C_CNT_A2_MIDLE_CNTS_MASK}, -}; - - -static struct regfield_info - glbl_axis_h2c_cnt_a3_field_info[] = { - {"GLBL_AXIS_H2C_CNT_A3_MACTV_CNTS", - GLBL_AXIS_H2C_CNT_A3_MACTV_CNTS_MASK}, -}; - - -static struct regfield_info - glbl_axis_h2c_cnt_a4_field_info[] = { - {"GLBL_AXIS_H2C_CNT_A4_MBUSY_CNTS", - GLBL_AXIS_H2C_CNT_A4_MBUSY_CNTS_MASK}, - {"GLBL_AXIS_H2C_CNT_A4_MACTV_CNTS", - GLBL_AXIS_H2C_CNT_A4_MACTV_CNTS_MASK}, -}; - - -static struct regfield_info - glbl_axis_h2c_cnt_a5_field_info[] = { - {"GLBL_AXIS_H2C_CNT_A5_MBUSY_CNTS", - GLBL_AXIS_H2C_CNT_A5_MBUSY_CNTS_MASK}, -}; - - -static struct regfield_info - glbl_axis_c2h_cnt_a0_field_info[] = { - {"GLBL_AXIS_C2H_CNT_A0_SPKT_CNTS", - GLBL_AXIS_C2H_CNT_A0_SPKT_CNTS_MASK}, -}; - - -static struct regfield_info - glbl_axis_c2h_cnt_a1_field_info[] = { - {"GLBL_AXIS_C2H_CNT_A1_SIDLE_CNTS", - GLBL_AXIS_C2H_CNT_A1_SIDLE_CNTS_MASK}, - {"GLBL_AXIS_C2H_CNT_A1_SPKT_CNTS", - GLBL_AXIS_C2H_CNT_A1_SPKT_CNTS_MASK}, -}; - - -static struct regfield_info - glbl_axis_c2h_cnt_a2_field_info[] = { - {"GLBL_AXIS_C2H_CNT_A2_SIDLE_CNTS", - GLBL_AXIS_C2H_CNT_A2_SIDLE_CNTS_MASK}, -}; - - -static struct regfield_info - glbl_axis_c2h_cnt_a3_field_info[] = { - {"GLBL_AXIS_C2H_CNT_A3_SACTV_CNTS", - GLBL_AXIS_C2H_CNT_A3_SACTV_CNTS_MASK}, -}; - - -static struct regfield_info - glbl_axis_c2h_cnt_a4_field_info[] = { - {"GLBL_AXIS_C2H_CNT_A4_SBUSY_CNTS", - GLBL_AXIS_C2H_CNT_A4_SBUSY_CNTS_MASK}, - {"GLBL_AXIS_C2H_CNT_A4_SACTV_CNTS", - GLBL_AXIS_C2H_CNT_A4_SACTV_CNTS_MASK}, -}; - - -static struct regfield_info - glbl_axis_c2h_cnt_a5_field_info[] = { - {"GLBL_AXIS_C2H_CNT_A5_SBUSY_CNTS", - GLBL_AXIS_C2H_CNT_A5_SBUSY_CNTS_MASK}, -}; - - -static struct regfield_info - glbl_m_axi_wr_cnt_a0_field_info[] = { - {"GLBL_M_AXI_WR_CNT_A0_PKT_CNTS", - GLBL_M_AXI_WR_CNT_A0_PKT_CNTS_MASK}, -}; - - -static struct regfield_info - glbl_m_axi_wr_cnt_a1_field_info[] = { - {"GLBL_M_AXI_WR_CNT_A1_IDLE_CNTS", - GLBL_M_AXI_WR_CNT_A1_IDLE_CNTS_MASK}, - {"GLBL_M_AXI_WR_CNT_A1_PKT_CNTS", - GLBL_M_AXI_WR_CNT_A1_PKT_CNTS_MASK}, -}; - - -static struct regfield_info - glbl_m_axi_wr_cnt_a2_field_info[] = { - {"GLBL_M_AXI_WR_CNT_A2_IDLE_CNTS", - GLBL_M_AXI_WR_CNT_A2_IDLE_CNTS_MASK}, -}; - - -static struct regfield_info - glbl_m_axi_wr_cnt_a3_field_info[] = { - {"GLBL_M_AXI_WR_CNT_A3_ACTV_CNTS", - GLBL_M_AXI_WR_CNT_A3_ACTV_CNTS_MASK}, -}; - - -static struct regfield_info - glbl_m_axi_wr_cnt_a4_field_info[] = { - {"GLBL_M_AXI_WR_CNT_A4_BUSY_CNTS", - GLBL_M_AXI_WR_CNT_A4_BUSY_CNTS_MASK}, - {"GLBL_M_AXI_WR_CNT_A4_ACTV_CNTS", - GLBL_M_AXI_WR_CNT_A4_ACTV_CNTS_MASK}, -}; - - -static struct regfield_info - glbl_m_axi_wr_cnt_a5_field_info[] = { - {"GLBL_M_AXI_WR_CNT_A5_BUSY_CNTS", - GLBL_M_AXI_WR_CNT_A5_BUSY_CNTS_MASK}, -}; - - -static struct regfield_info - glbl_m_axi_rd_cnt_a0_field_info[] = { - {"GLBL_M_AXI_RD_CNT_A0_PKT_CNTS", - GLBL_M_AXI_RD_CNT_A0_PKT_CNTS_MASK}, -}; - - -static struct regfield_info - glbl_m_axi_rd_cnt_a1_field_info[] = { - {"GLBL_M_AXI_RD_CNT_A1_IDLE_CNTS", - GLBL_M_AXI_RD_CNT_A1_IDLE_CNTS_MASK}, - {"GLBL_M_AXI_RD_CNT_A1_PKT_CNTS", - GLBL_M_AXI_RD_CNT_A1_PKT_CNTS_MASK}, -}; - - -static struct regfield_info - glbl_m_axi_rd_cnt_a2_field_info[] = { - {"GLBL_M_AXI_RD_CNT_A2_IDLE_CNTS", - GLBL_M_AXI_RD_CNT_A2_IDLE_CNTS_MASK}, -}; - - -static struct regfield_info - glbl_m_axi_rd_cnt_a3_field_info[] = { - {"GLBL_M_AXI_RD_CNT_A3_ACTV_CNTS", - GLBL_M_AXI_RD_CNT_A3_ACTV_CNTS_MASK}, -}; - - -static struct regfield_info - glbl_m_axi_rd_cnt_a4_field_info[] = { - {"GLBL_M_AXI_RD_CNT_A4_BUSY_CNTS", - GLBL_M_AXI_RD_CNT_A4_BUSY_CNTS_MASK}, - {"GLBL_M_AXI_RD_CNT_A4_ACTV_CNTS", - GLBL_M_AXI_RD_CNT_A4_ACTV_CNTS_MASK}, -}; - - -static struct regfield_info - glbl_m_axi_rd_cnt_a5_field_info[] = { - {"GLBL_M_AXI_RD_CNT_A5_BUSY_CNTS", - GLBL_M_AXI_RD_CNT_A5_BUSY_CNTS_MASK}, -}; - - -static struct regfield_info - glbl_m_axib_wr_cnt_a0_field_info[] = { - {"GLBL_M_AXIB_WR_CNT_A0_PKT_CNTS", - GLBL_M_AXIB_WR_CNT_A0_PKT_CNTS_MASK}, -}; - - -static struct regfield_info - glbl_m_axib_wr_cnt_a1_field_info[] = { - {"GLBL_M_AXIB_WR_CNT_A1_IDLE_CNTS", - GLBL_M_AXIB_WR_CNT_A1_IDLE_CNTS_MASK}, - {"GLBL_M_AXIB_WR_CNT_A1_PKT_CNTS", - GLBL_M_AXIB_WR_CNT_A1_PKT_CNTS_MASK}, -}; - - -static struct regfield_info - glbl_m_axib_wr_cnt_a2_field_info[] = { - {"GLBL_M_AXIB_WR_CNT_A2_IDLE_CNTS", - GLBL_M_AXIB_WR_CNT_A2_IDLE_CNTS_MASK}, -}; - - -static struct regfield_info - glbl_m_axib_wr_cnt_a3_field_info[] = { - {"GLBL_M_AXIB_WR_CNT_A3_ACTV_CNTS", - GLBL_M_AXIB_WR_CNT_A3_ACTV_CNTS_MASK}, -}; - - -static struct regfield_info - glbl_m_axib_wr_cnt_a4_field_info[] = { - {"GLBL_M_AXIB_WR_CNT_A4_BUSY_CNTS", - GLBL_M_AXIB_WR_CNT_A4_BUSY_CNTS_MASK}, - {"GLBL_M_AXIB_WR_CNT_A4_ACTV_CNTS", - GLBL_M_AXIB_WR_CNT_A4_ACTV_CNTS_MASK}, -}; - - -static struct regfield_info - glbl_m_axib_wr_cnt_a5_field_info[] = { - {"GLBL_M_AXIB_WR_CNT_A5_BUSY_CNTS", - GLBL_M_AXIB_WR_CNT_A5_BUSY_CNTS_MASK}, -}; - - -static struct regfield_info - glbl_m_axib_rd_cnt_a0_field_info[] = { - {"GLBL_M_AXIB_RD_CNT_A0_PKT_CNTS", - GLBL_M_AXIB_RD_CNT_A0_PKT_CNTS_MASK}, -}; - - -static struct regfield_info - glbl_m_axib_rd_cnt_a1_field_info[] = { - {"GLBL_M_AXIB_RD_CNT_A1_IDLE_CNTS", - GLBL_M_AXIB_RD_CNT_A1_IDLE_CNTS_MASK}, - {"GLBL_M_AXIB_RD_CNT_A1_PKT_CNTS", - GLBL_M_AXIB_RD_CNT_A1_PKT_CNTS_MASK}, -}; - - -static struct regfield_info - glbl_m_axib_rd_cnt_a2_field_info[] = { - {"GLBL_M_AXIB_RD_CNT_A2_IDLE_CNTS", - GLBL_M_AXIB_RD_CNT_A2_IDLE_CNTS_MASK}, -}; - - -static struct regfield_info - glbl_m_axib_rd_cnt_a3_field_info[] = { - {"GLBL_M_AXIB_RD_CNT_A3_ACTV_CNTS", - GLBL_M_AXIB_RD_CNT_A3_ACTV_CNTS_MASK}, -}; - - -static struct regfield_info - glbl_m_axib_rd_cnt_a4_field_info[] = { - {"GLBL_M_AXIB_RD_CNT_A4_BUSY_CNTS", - GLBL_M_AXIB_RD_CNT_A4_BUSY_CNTS_MASK}, - {"GLBL_M_AXIB_RD_CNT_A4_ACTV_CNTS", - GLBL_M_AXIB_RD_CNT_A4_ACTV_CNTS_MASK}, -}; - - -static struct regfield_info - glbl_m_axib_rd_cnt_a5_field_info[] = { - {"GLBL_M_AXIB_RD_CNT_A5_BUSY_CNTS", - GLBL_M_AXIB_RD_CNT_A5_BUSY_CNTS_MASK}, -}; - - -static struct regfield_info - glbl_s_axi_wr_cnt_a0_field_info[] = { - {"GLBL_S_AXI_WR_CNT_A0_PKT_CNTS", - GLBL_S_AXI_WR_CNT_A0_PKT_CNTS_MASK}, -}; - - -static struct regfield_info - glbl_s_axi_wr_cnt_a1_field_info[] = { - {"GLBL_S_AXI_WR_CNT_A1_IDLE_CNTS", - GLBL_S_AXI_WR_CNT_A1_IDLE_CNTS_MASK}, - {"GLBL_S_AXI_WR_CNT_A1_PKT_CNTS", - GLBL_S_AXI_WR_CNT_A1_PKT_CNTS_MASK}, -}; - - -static struct regfield_info - glbl_s_axi_wr_cnt_a2_field_info[] = { - {"GLBL_S_AXI_WR_CNT_A2_IDLE_CNTS", - GLBL_S_AXI_WR_CNT_A2_IDLE_CNTS_MASK}, -}; - - -static struct regfield_info - glbl_s_axi_wr_cnt_a3_field_info[] = { - {"GLBL_S_AXI_WR_CNT_A3_ACTV_CNTS", - GLBL_S_AXI_WR_CNT_A3_ACTV_CNTS_MASK}, -}; - - -static struct regfield_info - glbl_s_axi_wr_cnt_a4_field_info[] = { - {"GLBL_S_AXI_WR_CNT_A4_BUSY_CNTS", - GLBL_S_AXI_WR_CNT_A4_BUSY_CNTS_MASK}, - {"GLBL_S_AXI_WR_CNT_A4_ACTV_CNTS", - GLBL_S_AXI_WR_CNT_A4_ACTV_CNTS_MASK}, -}; - - -static struct regfield_info - glbl_s_axi_wr_cnt_a5_field_info[] = { - {"GLBL_S_AXI_WR_CNT_A5_BUSY_CNTS", - GLBL_S_AXI_WR_CNT_A5_BUSY_CNTS_MASK}, -}; - - -static struct regfield_info - glbl_s_axi_rd_cnt_a0_field_info[] = { - {"GLBL_S_AXI_RD_CNT_A0_PKT_CNTS", - GLBL_S_AXI_RD_CNT_A0_PKT_CNTS_MASK}, -}; - - -static struct regfield_info - glbl_s_axi_rd_cnt_a1_field_info[] = { - {"GLBL_S_AXI_RD_CNT_A1_IDLE_CNTS", - GLBL_S_AXI_RD_CNT_A1_IDLE_CNTS_MASK}, - {"GLBL_S_AXI_RD_CNT_A1_PKT_CNTS", - GLBL_S_AXI_RD_CNT_A1_PKT_CNTS_MASK}, -}; - - -static struct regfield_info - glbl_s_axi_rd_cnt_a2_field_info[] = { - {"GLBL_S_AXI_RD_CNT_A2_IDLE_CNTS", - GLBL_S_AXI_RD_CNT_A2_IDLE_CNTS_MASK}, -}; - - -static struct regfield_info - glbl_s_axi_rd_cnt_a3_field_info[] = { - {"GLBL_S_AXI_RD_CNT_A3_ACTV_CNTS", - GLBL_S_AXI_RD_CNT_A3_ACTV_CNTS_MASK}, -}; - - -static struct regfield_info - glbl_s_axi_rd_cnt_a4_field_info[] = { - {"GLBL_S_AXI_RD_CNT_A4_BUSY_CNTS", - GLBL_S_AXI_RD_CNT_A4_BUSY_CNTS_MASK}, - {"GLBL_S_AXI_RD_CNT_A4_ACTV_CNTS", - GLBL_S_AXI_RD_CNT_A4_ACTV_CNTS_MASK}, -}; - - -static struct regfield_info - glbl_s_axi_rd_cnt_a5_field_info[] = { - {"GLBL_S_AXI_RD_CNT_A5_BUSY_CNTS", - GLBL_S_AXI_RD_CNT_A5_BUSY_CNTS_MASK}, -}; - - -static struct regfield_info - glbl_s_axis_cmp_cnt_a0_field_info[] = { - {"GLBL_S_AXIS_CMP_CNT_A0_PKT_CNTS", - GLBL_S_AXIS_CMP_CNT_A0_PKT_CNTS_MASK}, -}; - - -static struct regfield_info - glbl_s_axis_cmp_cnt_a1_field_info[] = { - {"GLBL_S_AXIS_CMP_CNT_A1_IDLE_CNTS", - GLBL_S_AXIS_CMP_CNT_A1_IDLE_CNTS_MASK}, - {"GLBL_S_AXIS_CMP_CNT_A1_PKT_CNTS", - GLBL_S_AXIS_CMP_CNT_A1_PKT_CNTS_MASK}, -}; - - -static struct regfield_info - glbl_s_axis_cmp_cnt_a2_field_info[] = { - {"GLBL_S_AXIS_CMP_CNT_A2_IDLE_CNTS", - GLBL_S_AXIS_CMP_CNT_A2_IDLE_CNTS_MASK}, -}; - - -static struct regfield_info - glbl_s_axis_cmp_cnt_a3_field_info[] = { - {"GLBL_S_AXIS_CMP_CNT_A3_ACTV_CNTS", - GLBL_S_AXIS_CMP_CNT_A3_ACTV_CNTS_MASK}, -}; - - -static struct regfield_info - glbl_s_axis_cmp_cnt_a4_field_info[] = { - {"GLBL_S_AXIS_CMP_CNT_A4_BUSY_CNTS", - GLBL_S_AXIS_CMP_CNT_A4_BUSY_CNTS_MASK}, - {"GLBL_S_AXIS_CMP_CNT_A4_ACTV_CNTS", - GLBL_S_AXIS_CMP_CNT_A4_ACTV_CNTS_MASK}, -}; - - -static struct regfield_info - glbl_s_axis_cmp_cnt_a5_field_info[] = { - {"GLBL_S_AXIS_CMP_CNT_A5_BUSY_CNTS", - GLBL_S_AXIS_CMP_CNT_A5_BUSY_CNTS_MASK}, -}; - - -static struct regfield_info - ind_ctxt_data_field_info[] = { - {"IND_CTXT_DATA_DATA", - IND_CTXT_DATA_DATA_MASK}, -}; - - -static struct regfield_info - ind_ctxt_mask_field_info[] = { - {"IND_CTXT", - IND_CTXT_MASK}, -}; - - -static struct regfield_info - ind_ctxt_cmd_field_info[] = { - {"IND_CTXT_CMD_RSVD_1", - IND_CTXT_CMD_RSVD_1_MASK}, - {"IND_CTXT_CMD_QID", - IND_CTXT_CMD_QID_MASK}, - {"IND_CTXT_CMD_OP", - IND_CTXT_CMD_OP_MASK}, - {"IND_CTXT_CMD_SEL", - IND_CTXT_CMD_SEL_MASK}, - {"IND_CTXT_CMD_BUSY", - IND_CTXT_CMD_BUSY_MASK}, -}; - - -static struct regfield_info - c2h_timer_cnt_field_info[] = { - {"C2H_TIMER_CNT_RSVD_1", - C2H_TIMER_CNT_RSVD_1_MASK}, - {"C2H_TIMER_CNT", - C2H_TIMER_CNT_MASK}, -}; - - -static struct regfield_info - c2h_cnt_th_field_info[] = { - {"C2H_CNT_TH_RSVD_1", - C2H_CNT_TH_RSVD_1_MASK}, - {"C2H_CNT_TH_THESHOLD_CNT", - C2H_CNT_TH_THESHOLD_CNT_MASK}, -}; - - -static struct regfield_info - c2h_pfch_cfg_1_field_info[] = { - {"C2H_PFCH_CFG_1_EVT_QCNT_TH", - C2H_PFCH_CFG_1_EVT_QCNT_TH_MASK}, - {"C2H_PFCH_CFG_1_QCNT", - C2H_PFCH_CFG_1_QCNT_MASK}, -}; - - -static struct regfield_info - c2h_pfch_cfg_2_field_info[] = { - {"C2H_PFCH_CFG_2_FENCE", - C2H_PFCH_CFG_2_FENCE_MASK}, - {"C2H_PFCH_CFG_2_RSVD", - C2H_PFCH_CFG_2_RSVD_MASK}, - {"C2H_PFCH_CFG_2_VAR_DESC_NO_DROP", - C2H_PFCH_CFG_2_VAR_DESC_NO_DROP_MASK}, - {"C2H_PFCH_CFG_2_LL_SZ_TH", - C2H_PFCH_CFG_2_LL_SZ_TH_MASK}, - {"C2H_PFCH_CFG_2_VAR_DESC_NUM", - C2H_PFCH_CFG_2_VAR_DESC_NUM_MASK}, - {"C2H_PFCH_CFG_2_NUM", - C2H_PFCH_CFG_2_NUM_MASK}, -}; - - -static struct regfield_info - c2h_stat_s_axis_c2h_accepted_field_info[] = { - {"C2H_STAT_S_AXIS_C2H_ACCEPTED", - C2H_STAT_S_AXIS_C2H_ACCEPTED_MASK}, -}; - - -static struct regfield_info - c2h_stat_s_axis_wrb_accepted_field_info[] = { - {"C2H_STAT_S_AXIS_WRB_ACCEPTED", - C2H_STAT_S_AXIS_WRB_ACCEPTED_MASK}, -}; - - -static struct regfield_info - c2h_stat_desc_rsp_pkt_accepted_field_info[] = { - {"C2H_STAT_DESC_RSP_PKT_ACCEPTED_D", - C2H_STAT_DESC_RSP_PKT_ACCEPTED_D_MASK}, -}; - - -static struct regfield_info - c2h_stat_axis_pkg_cmp_field_info[] = { - {"C2H_STAT_AXIS_PKG_CMP", - C2H_STAT_AXIS_PKG_CMP_MASK}, -}; - - -static struct regfield_info - c2h_stat_desc_rsp_accepted_field_info[] = { - {"C2H_STAT_DESC_RSP_ACCEPTED_D", - C2H_STAT_DESC_RSP_ACCEPTED_D_MASK}, -}; - - -static struct regfield_info - c2h_stat_desc_rsp_cmp_field_info[] = { - {"C2H_STAT_DESC_RSP_CMP_D", - C2H_STAT_DESC_RSP_CMP_D_MASK}, -}; - - -static struct regfield_info - c2h_stat_wrq_out_field_info[] = { - {"C2H_STAT_WRQ_OUT", - C2H_STAT_WRQ_OUT_MASK}, -}; - - -static struct regfield_info - c2h_stat_wpl_ren_accepted_field_info[] = { - {"C2H_STAT_WPL_REN_ACCEPTED", - C2H_STAT_WPL_REN_ACCEPTED_MASK}, -}; - - -static struct regfield_info - c2h_stat_total_wrq_len_field_info[] = { - {"C2H_STAT_TOTAL_WRQ_LEN", - C2H_STAT_TOTAL_WRQ_LEN_MASK}, -}; - - -static struct regfield_info - c2h_stat_total_wpl_len_field_info[] = { - {"C2H_STAT_TOTAL_WPL_LEN", - C2H_STAT_TOTAL_WPL_LEN_MASK}, -}; - - -static struct regfield_info - c2h_buf_sz_field_info[] = { - {"C2H_BUF_SZ_IZE", - C2H_BUF_SZ_IZE_MASK}, -}; - - -static struct regfield_info - c2h_err_stat_field_info[] = { - {"C2H_ERR_STAT_RSVD_1", - C2H_ERR_STAT_RSVD_1_MASK}, - {"C2H_ERR_STAT_WRB_PORT_ID_ERR", - C2H_ERR_STAT_WRB_PORT_ID_ERR_MASK}, - {"C2H_ERR_STAT_HDR_PAR_ERR", - C2H_ERR_STAT_HDR_PAR_ERR_MASK}, - {"C2H_ERR_STAT_HDR_ECC_COR_ERR", - C2H_ERR_STAT_HDR_ECC_COR_ERR_MASK}, - {"C2H_ERR_STAT_HDR_ECC_UNC_ERR", - C2H_ERR_STAT_HDR_ECC_UNC_ERR_MASK}, - {"C2H_ERR_STAT_AVL_RING_DSC_ERR", - C2H_ERR_STAT_AVL_RING_DSC_ERR_MASK}, - {"C2H_ERR_STAT_WRB_PRTY_ERR", - C2H_ERR_STAT_WRB_PRTY_ERR_MASK}, - {"C2H_ERR_STAT_WRB_CIDX_ERR", - C2H_ERR_STAT_WRB_CIDX_ERR_MASK}, - {"C2H_ERR_STAT_WRB_QFULL_ERR", - C2H_ERR_STAT_WRB_QFULL_ERR_MASK}, - {"C2H_ERR_STAT_WRB_INV_Q_ERR", - C2H_ERR_STAT_WRB_INV_Q_ERR_MASK}, - {"C2H_ERR_STAT_RSVD_2", - C2H_ERR_STAT_RSVD_2_MASK}, - {"C2H_ERR_STAT_PORT_ID_CTXT_MISMATCH", - C2H_ERR_STAT_PORT_ID_CTXT_MISMATCH_MASK}, - {"C2H_ERR_STAT_ERR_DESC_CNT", - C2H_ERR_STAT_ERR_DESC_CNT_MASK}, - {"C2H_ERR_STAT_RSVD_3", - C2H_ERR_STAT_RSVD_3_MASK}, - {"C2H_ERR_STAT_MSI_INT_FAIL", - C2H_ERR_STAT_MSI_INT_FAIL_MASK}, - {"C2H_ERR_STAT_ENG_WPL_DATA_PAR_ERR", - C2H_ERR_STAT_ENG_WPL_DATA_PAR_ERR_MASK}, - {"C2H_ERR_STAT_RSVD_4", - C2H_ERR_STAT_RSVD_4_MASK}, - {"C2H_ERR_STAT_DESC_RSP_ERR", - C2H_ERR_STAT_DESC_RSP_ERR_MASK}, - {"C2H_ERR_STAT_QID_MISMATCH", - C2H_ERR_STAT_QID_MISMATCH_MASK}, - {"C2H_ERR_STAT_SH_CMPT_DSC_ERR", - C2H_ERR_STAT_SH_CMPT_DSC_ERR_MASK}, - {"C2H_ERR_STAT_LEN_MISMATCH", - C2H_ERR_STAT_LEN_MISMATCH_MASK}, - {"C2H_ERR_STAT_MTY_MISMATCH", - C2H_ERR_STAT_MTY_MISMATCH_MASK}, -}; - - -static struct regfield_info - c2h_err_mask_field_info[] = { - {"C2H_ERR_EN", - C2H_ERR_EN_MASK}, -}; - - -static struct regfield_info - c2h_fatal_err_stat_field_info[] = { - {"C2H_FATAL_ERR_STAT_RSVD_1", - C2H_FATAL_ERR_STAT_RSVD_1_MASK}, - {"C2H_FATAL_ERR_STAT_HDR_ECC_UNC_ERR", - C2H_FATAL_ERR_STAT_HDR_ECC_UNC_ERR_MASK}, - {"C2H_FATAL_ERR_STAT_AVL_RING_FIFO_RAM_RDBE", - C2H_FATAL_ERR_STAT_AVL_RING_FIFO_RAM_RDBE_MASK}, - {"C2H_FATAL_ERR_STAT_WPL_DATA_PAR_ERR", - C2H_FATAL_ERR_STAT_WPL_DATA_PAR_ERR_MASK}, - {"C2H_FATAL_ERR_STAT_PLD_FIFO_RAM_RDBE", - C2H_FATAL_ERR_STAT_PLD_FIFO_RAM_RDBE_MASK}, - {"C2H_FATAL_ERR_STAT_QID_FIFO_RAM_RDBE", - C2H_FATAL_ERR_STAT_QID_FIFO_RAM_RDBE_MASK}, - {"C2H_FATAL_ERR_STAT_CMPT_FIFO_RAM_RDBE", - C2H_FATAL_ERR_STAT_CMPT_FIFO_RAM_RDBE_MASK}, - {"C2H_FATAL_ERR_STAT_WRB_COAL_DATA_RAM_RDBE", - C2H_FATAL_ERR_STAT_WRB_COAL_DATA_RAM_RDBE_MASK}, - {"C2H_FATAL_ERR_STAT_RESERVED2", - C2H_FATAL_ERR_STAT_RESERVED2_MASK}, - {"C2H_FATAL_ERR_STAT_INT_CTXT_RAM_RDBE", - C2H_FATAL_ERR_STAT_INT_CTXT_RAM_RDBE_MASK}, - {"C2H_FATAL_ERR_STAT_DESC_REQ_FIFO_RAM_RDBE", - C2H_FATAL_ERR_STAT_DESC_REQ_FIFO_RAM_RDBE_MASK}, - {"C2H_FATAL_ERR_STAT_PFCH_CTXT_RAM_RDBE", - C2H_FATAL_ERR_STAT_PFCH_CTXT_RAM_RDBE_MASK}, - {"C2H_FATAL_ERR_STAT_WRB_CTXT_RAM_RDBE", - C2H_FATAL_ERR_STAT_WRB_CTXT_RAM_RDBE_MASK}, - {"C2H_FATAL_ERR_STAT_PFCH_LL_RAM_RDBE", - C2H_FATAL_ERR_STAT_PFCH_LL_RAM_RDBE_MASK}, - {"C2H_FATAL_ERR_STAT_TIMER_FIFO_RAM_RDBE", - C2H_FATAL_ERR_STAT_TIMER_FIFO_RAM_RDBE_MASK}, - {"C2H_FATAL_ERR_STAT_QID_MISMATCH", - C2H_FATAL_ERR_STAT_QID_MISMATCH_MASK}, - {"C2H_FATAL_ERR_STAT_RESERVED1", - C2H_FATAL_ERR_STAT_RESERVED1_MASK}, - {"C2H_FATAL_ERR_STAT_LEN_MISMATCH", - C2H_FATAL_ERR_STAT_LEN_MISMATCH_MASK}, - {"C2H_FATAL_ERR_STAT_MTY_MISMATCH", - C2H_FATAL_ERR_STAT_MTY_MISMATCH_MASK}, -}; - - -static struct regfield_info - c2h_fatal_err_mask_field_info[] = { - {"C2H_FATAL_ERR_C2HEN", - C2H_FATAL_ERR_C2HEN_MASK}, -}; - - -static struct regfield_info - c2h_fatal_err_enable_field_info[] = { - {"C2H_FATAL_ERR_ENABLE_RSVD_1", - C2H_FATAL_ERR_ENABLE_RSVD_1_MASK}, - {"C2H_FATAL_ERR_ENABLE_WPL_PAR_INV", - C2H_FATAL_ERR_ENABLE_WPL_PAR_INV_MASK}, - {"C2H_FATAL_ERR_ENABLE_WRQ_DIS", - C2H_FATAL_ERR_ENABLE_WRQ_DIS_MASK}, -}; - - -static struct regfield_info - glbl_err_int_field_info[] = { - {"GLBL_ERR_INT_RSVD_1", - GLBL_ERR_INT_RSVD_1_MASK}, - {"GLBL_ERR_INT_HOST_ID", - GLBL_ERR_INT_HOST_ID_MASK}, - {"GLBL_ERR_INT_DIS_INTR_ON_VF", - GLBL_ERR_INT_DIS_INTR_ON_VF_MASK}, - {"GLBL_ERR_INT_ARM", - GLBL_ERR_INT_ARM_MASK}, - {"GLBL_ERR_INT_EN_COAL", - GLBL_ERR_INT_EN_COAL_MASK}, - {"GLBL_ERR_INT_VEC", - GLBL_ERR_INT_VEC_MASK}, - {"GLBL_ERR_INT_FUNC", - GLBL_ERR_INT_FUNC_MASK}, -}; - - -static struct regfield_info - c2h_pfch_cfg_field_info[] = { - {"C2H_PFCH_CFG_EVTFL_TH", - C2H_PFCH_CFG_EVTFL_TH_MASK}, - {"C2H_PFCH_CFG_FL_TH", - C2H_PFCH_CFG_FL_TH_MASK}, -}; - - -static struct regfield_info - c2h_int_timer_tick_field_info[] = { - {"C2H_INT_TIMER_TICK", - C2H_INT_TIMER_TICK_MASK}, -}; - - -static struct regfield_info - c2h_stat_desc_rsp_drop_accepted_field_info[] = { - {"C2H_STAT_DESC_RSP_DROP_ACCEPTED_D", - C2H_STAT_DESC_RSP_DROP_ACCEPTED_D_MASK}, -}; - - -static struct regfield_info - c2h_stat_desc_rsp_err_accepted_field_info[] = { - {"C2H_STAT_DESC_RSP_ERR_ACCEPTED_D", - C2H_STAT_DESC_RSP_ERR_ACCEPTED_D_MASK}, -}; - - -static struct regfield_info - c2h_stat_desc_req_field_info[] = { - {"C2H_STAT_DESC_REQ", - C2H_STAT_DESC_REQ_MASK}, -}; - - -static struct regfield_info - c2h_stat_dbg_dma_eng_0_field_info[] = { - {"C2H_STAT_DMA_ENG_0_S_AXIS_C2H_TVALID", - C2H_STAT_DMA_ENG_0_S_AXIS_C2H_TVALID_MASK}, - {"C2H_STAT_DMA_ENG_0_S_AXIS_C2H_TREADY", - C2H_STAT_DMA_ENG_0_S_AXIS_C2H_TREADY_MASK}, - {"C2H_STAT_DMA_ENG_0_S_AXIS_WRB_TVALID", - C2H_STAT_DMA_ENG_0_S_AXIS_WRB_TVALID_MASK}, - {"C2H_STAT_DMA_ENG_0_S_AXIS_WRB_TREADY", - C2H_STAT_DMA_ENG_0_S_AXIS_WRB_TREADY_MASK}, - {"C2H_STAT_DMA_ENG_0_PLD_FIFO_IN_RDY", - C2H_STAT_DMA_ENG_0_PLD_FIFO_IN_RDY_MASK}, - {"C2H_STAT_DMA_ENG_0_QID_FIFO_IN_RDY", - C2H_STAT_DMA_ENG_0_QID_FIFO_IN_RDY_MASK}, - {"C2H_STAT_DMA_ENG_0_ARB_FIFO_OUT_VLD", - C2H_STAT_DMA_ENG_0_ARB_FIFO_OUT_VLD_MASK}, - {"C2H_STAT_DMA_ENG_0_ARB_FIFO_OUT_QID", - C2H_STAT_DMA_ENG_0_ARB_FIFO_OUT_QID_MASK}, - {"C2H_STAT_DMA_ENG_0_WRB_FIFO_IN_RDY", - C2H_STAT_DMA_ENG_0_WRB_FIFO_IN_RDY_MASK}, - {"C2H_STAT_DMA_ENG_0_WRB_FIFO_OUT_CNT", - C2H_STAT_DMA_ENG_0_WRB_FIFO_OUT_CNT_MASK}, - {"C2H_STAT_DMA_ENG_0_WRB_SM_CS", - C2H_STAT_DMA_ENG_0_WRB_SM_CS_MASK}, - {"C2H_STAT_DMA_ENG_0_MAIN_SM_CS", - C2H_STAT_DMA_ENG_0_MAIN_SM_CS_MASK}, -}; - - -static struct regfield_info - c2h_stat_dbg_dma_eng_1_field_info[] = { - {"C2H_STAT_DMA_ENG_1_WRB_USER_0_CMPT_TYPE", - C2H_STAT_DMA_ENG_1_WRB_USER_0_CMPT_TYPE_MASK}, - {"C2H_STAT_DMA_ENG_1_DESC_RSP_FIFO_OUT_VLD", - C2H_STAT_DMA_ENG_1_DESC_RSP_FIFO_OUT_VLD_MASK}, - {"C2H_STAT_DMA_ENG_1_QID_FIFO_OUT_CNT", - C2H_STAT_DMA_ENG_1_QID_FIFO_OUT_CNT_MASK}, - {"C2H_STAT_DMA_ENG_1_PLD_FIFO_OUT_CNT", - C2H_STAT_DMA_ENG_1_PLD_FIFO_OUT_CNT_MASK}, - {"C2H_STAT_DMA_ENG_1_PLD_ST_FIFO_CNT", - C2H_STAT_DMA_ENG_1_PLD_ST_FIFO_CNT_MASK}, -}; - - -static struct regfield_info - c2h_stat_dbg_dma_eng_2_field_info[] = { - {"C2H_STAT_DMA_ENG_2_WRB_USER_1_CMPT_TYPE", - C2H_STAT_DMA_ENG_2_WRB_USER_1_CMPT_TYPE_MASK}, - {"C2H_STAT_DMA_ENG_2_DESC_RSP_FIFO_OUT_VLD_1", - C2H_STAT_DMA_ENG_2_DESC_RSP_FIFO_OUT_VLD_1_MASK}, - {"C2H_STAT_DMA_ENG_2_QID_FIFO_OUT_CNT_1", - C2H_STAT_DMA_ENG_2_QID_FIFO_OUT_CNT_1_MASK}, - {"C2H_STAT_DMA_ENG_2_PLD_FIFO_OUT_CNT_1", - C2H_STAT_DMA_ENG_2_PLD_FIFO_OUT_CNT_1_MASK}, - {"C2H_STAT_DMA_ENG_2_PLD_ST_FIFO_CNT_1", - C2H_STAT_DMA_ENG_2_PLD_ST_FIFO_CNT_1_MASK}, -}; - - -static struct regfield_info - c2h_stat_dbg_dma_eng_3_field_info[] = { - {"C2H_STAT_DMA_ENG_3_QID_FIFO_OUT_DAT_HAS_CMPT", - C2H_STAT_DMA_ENG_3_QID_FIFO_OUT_DAT_HAS_CMPT_MASK}, - {"C2H_STAT_DMA_ENG_3_QID_FIFO_OUT_DAT_MARKER", - C2H_STAT_DMA_ENG_3_QID_FIFO_OUT_DAT_MARKER_MASK}, - {"C2H_STAT_DMA_ENG_3_QID_FIFO_OUT_DAT_DROP_REQ", - C2H_STAT_DMA_ENG_3_QID_FIFO_OUT_DAT_DROP_REQ_MASK}, - {"C2H_STAT_DMA_ENG_3_QID_FIFO_OUT_DAT_QID", - C2H_STAT_DMA_ENG_3_QID_FIFO_OUT_DAT_QID_MASK}, - {"C2H_STAT_DMA_ENG_3_WR_HDR_FIFO_OUT_CNT", - C2H_STAT_DMA_ENG_3_WR_HDR_FIFO_OUT_CNT_MASK}, - {"C2H_STAT_DMA_ENG_3_QID_FIFO_OUT_VLD", - C2H_STAT_DMA_ENG_3_QID_FIFO_OUT_VLD_MASK}, - {"C2H_STAT_DMA_ENG_3_PLD_FIFO_OUT_VLD", - C2H_STAT_DMA_ENG_3_PLD_FIFO_OUT_VLD_MASK}, - {"C2H_STAT_DMA_ENG_3_PLD_ST_FIFO_OUT_VLD", - C2H_STAT_DMA_ENG_3_PLD_ST_FIFO_OUT_VLD_MASK}, - {"C2H_STAT_DMA_ENG_3_PLD_ST_FIFO_OUT_DATA_EOP", - C2H_STAT_DMA_ENG_3_PLD_ST_FIFO_OUT_DATA_EOP_MASK}, - {"C2H_STAT_DMA_ENG_3_PLD_ST_FIFO_OUT_DATA_AVL_IDX_ENABLE", - C2H_STAT_DMA_ENG_3_PLD_ST_FIFO_OUT_DATA_AVL_IDX_ENABLE_MASK}, - {"C2H_STAT_DMA_ENG_3_PLD_ST_FIFO_OUT_DATA_DROP", - C2H_STAT_DMA_ENG_3_PLD_ST_FIFO_OUT_DATA_DROP_MASK}, - {"C2H_STAT_DMA_ENG_3_PLD_ST_FIFO_OUT_DATA_ERR", - C2H_STAT_DMA_ENG_3_PLD_ST_FIFO_OUT_DATA_ERR_MASK}, - {"C2H_STAT_DMA_ENG_3_DESC_CNT_FIFO_IN_RDY", - C2H_STAT_DMA_ENG_3_DESC_CNT_FIFO_IN_RDY_MASK}, - {"C2H_STAT_DMA_ENG_3_DESC_RSP_FIFO_IN_RDY", - C2H_STAT_DMA_ENG_3_DESC_RSP_FIFO_IN_RDY_MASK}, - {"C2H_STAT_DMA_ENG_3_PLD_PKT_ID_LARGER", - C2H_STAT_DMA_ENG_3_PLD_PKT_ID_LARGER_MASK}, - {"C2H_STAT_DMA_ENG_3_WCP_FIFO_IN_RDY", - C2H_STAT_DMA_ENG_3_WCP_FIFO_IN_RDY_MASK}, - {"C2H_STAT_DMA_ENG_3_PLD_ST_FIFO_IN_RDY", - C2H_STAT_DMA_ENG_3_PLD_ST_FIFO_IN_RDY_MASK}, -}; - - -static struct regfield_info - c2h_dbg_pfch_err_ctxt_field_info[] = { - {"C2H_PFCH_ERR_CTXT_RSVD_1", - C2H_PFCH_ERR_CTXT_RSVD_1_MASK}, - {"C2H_PFCH_ERR_CTXT_ERR_STAT", - C2H_PFCH_ERR_CTXT_ERR_STAT_MASK}, - {"C2H_PFCH_ERR_CTXT_CMD_WR", - C2H_PFCH_ERR_CTXT_CMD_WR_MASK}, - {"C2H_PFCH_ERR_CTXT_QID", - C2H_PFCH_ERR_CTXT_QID_MASK}, - {"C2H_PFCH_ERR_CTXT_DONE", - C2H_PFCH_ERR_CTXT_DONE_MASK}, -}; - - -static struct regfield_info - c2h_first_err_qid_field_info[] = { - {"C2H_FIRST_ERR_QID_RSVD_1", - C2H_FIRST_ERR_QID_RSVD_1_MASK}, - {"C2H_FIRST_ERR_QID_ERR_TYPE", - C2H_FIRST_ERR_QID_ERR_TYPE_MASK}, - {"C2H_FIRST_ERR_QID_RSVD", - C2H_FIRST_ERR_QID_RSVD_MASK}, - {"C2H_FIRST_ERR_QID_QID", - C2H_FIRST_ERR_QID_QID_MASK}, -}; - - -static struct regfield_info - stat_num_wrb_in_field_info[] = { - {"STAT_NUM_WRB_IN_RSVD_1", - STAT_NUM_WRB_IN_RSVD_1_MASK}, - {"STAT_NUM_WRB_IN_WRB_CNT", - STAT_NUM_WRB_IN_WRB_CNT_MASK}, -}; - - -static struct regfield_info - stat_num_wrb_out_field_info[] = { - {"STAT_NUM_WRB_OUT_RSVD_1", - STAT_NUM_WRB_OUT_RSVD_1_MASK}, - {"STAT_NUM_WRB_OUT_WRB_CNT", - STAT_NUM_WRB_OUT_WRB_CNT_MASK}, -}; - - -static struct regfield_info - stat_num_wrb_drp_field_info[] = { - {"STAT_NUM_WRB_DRP_RSVD_1", - STAT_NUM_WRB_DRP_RSVD_1_MASK}, - {"STAT_NUM_WRB_DRP_WRB_CNT", - STAT_NUM_WRB_DRP_WRB_CNT_MASK}, -}; - - -static struct regfield_info - stat_num_stat_desc_out_field_info[] = { - {"STAT_NUM_STAT_DESC_OUT_RSVD_1", - STAT_NUM_STAT_DESC_OUT_RSVD_1_MASK}, - {"STAT_NUM_STAT_DESC_OUT_CNT", - STAT_NUM_STAT_DESC_OUT_CNT_MASK}, -}; - - -static struct regfield_info - stat_num_dsc_crdt_sent_field_info[] = { - {"STAT_NUM_DSC_CRDT_SENT_RSVD_1", - STAT_NUM_DSC_CRDT_SENT_RSVD_1_MASK}, - {"STAT_NUM_DSC_CRDT_SENT_CNT", - STAT_NUM_DSC_CRDT_SENT_CNT_MASK}, -}; - - -static struct regfield_info - stat_num_fch_dsc_rcvd_field_info[] = { - {"STAT_NUM_FCH_DSC_RCVD_RSVD_1", - STAT_NUM_FCH_DSC_RCVD_RSVD_1_MASK}, - {"STAT_NUM_FCH_DSC_RCVD_DSC_CNT", - STAT_NUM_FCH_DSC_RCVD_DSC_CNT_MASK}, -}; - - -static struct regfield_info - stat_num_byp_dsc_rcvd_field_info[] = { - {"STAT_NUM_BYP_DSC_RCVD_RSVD_1", - STAT_NUM_BYP_DSC_RCVD_RSVD_1_MASK}, - {"STAT_NUM_BYP_DSC_RCVD_DSC_CNT", - STAT_NUM_BYP_DSC_RCVD_DSC_CNT_MASK}, -}; - - -static struct regfield_info - c2h_wrb_coal_cfg_field_info[] = { - {"C2H_WRB_COAL_CFG_MAX_BUF_SZ", - C2H_WRB_COAL_CFG_MAX_BUF_SZ_MASK}, - {"C2H_WRB_COAL_CFG_TICK_VAL", - C2H_WRB_COAL_CFG_TICK_VAL_MASK}, - {"C2H_WRB_COAL_CFG_TICK_CNT", - C2H_WRB_COAL_CFG_TICK_CNT_MASK}, - {"C2H_WRB_COAL_CFG_SET_GLB_FLUSH", - C2H_WRB_COAL_CFG_SET_GLB_FLUSH_MASK}, - {"C2H_WRB_COAL_CFG_DONE_GLB_FLUSH", - C2H_WRB_COAL_CFG_DONE_GLB_FLUSH_MASK}, -}; - - -static struct regfield_info - c2h_intr_h2c_req_field_info[] = { - {"C2H_INTR_H2C_REQ_RSVD_1", - C2H_INTR_H2C_REQ_RSVD_1_MASK}, - {"C2H_INTR_H2C_REQ_CNT", - C2H_INTR_H2C_REQ_CNT_MASK}, -}; - - -static struct regfield_info - c2h_intr_c2h_mm_req_field_info[] = { - {"C2H_INTR_C2H_MM_REQ_RSVD_1", - C2H_INTR_C2H_MM_REQ_RSVD_1_MASK}, - {"C2H_INTR_C2H_MM_REQ_CNT", - C2H_INTR_C2H_MM_REQ_CNT_MASK}, -}; - - -static struct regfield_info - c2h_intr_err_int_req_field_info[] = { - {"C2H_INTR_ERR_INT_REQ_RSVD_1", - C2H_INTR_ERR_INT_REQ_RSVD_1_MASK}, - {"C2H_INTR_ERR_INT_REQ_CNT", - C2H_INTR_ERR_INT_REQ_CNT_MASK}, -}; - - -static struct regfield_info - c2h_intr_c2h_st_req_field_info[] = { - {"C2H_INTR_C2H_ST_REQ_RSVD_1", - C2H_INTR_C2H_ST_REQ_RSVD_1_MASK}, - {"C2H_INTR_C2H_ST_REQ_CNT", - C2H_INTR_C2H_ST_REQ_CNT_MASK}, -}; - - -static struct regfield_info - c2h_intr_h2c_err_c2h_mm_msix_ack_field_info[] = { - {"C2H_INTR_H2C_ERR_C2H_MM_MSIX_ACK_RSVD_1", - C2H_INTR_H2C_ERR_C2H_MM_MSIX_ACK_RSVD_1_MASK}, - {"C2H_INTR_H2C_ERR_C2H_MM_MSIX_ACK_CNT", - C2H_INTR_H2C_ERR_C2H_MM_MSIX_ACK_CNT_MASK}, -}; - - -static struct regfield_info - c2h_intr_h2c_err_c2h_mm_msix_fail_field_info[] = { - {"C2H_INTR_H2C_ERR_C2H_MM_MSIX_FAIL_RSVD_1", - C2H_INTR_H2C_ERR_C2H_MM_MSIX_FAIL_RSVD_1_MASK}, - {"C2H_INTR_H2C_ERR_C2H_MM_MSIX_FAIL_CNT", - C2H_INTR_H2C_ERR_C2H_MM_MSIX_FAIL_CNT_MASK}, -}; - - -static struct regfield_info - c2h_intr_h2c_err_c2h_mm_msix_no_msix_field_info[] = { - {"C2H_INTR_H2C_ERR_C2H_MM_MSIX_NO_MSIX_RSVD_1", - C2H_INTR_H2C_ERR_C2H_MM_MSIX_NO_MSIX_RSVD_1_MASK}, - {"C2H_INTR_H2C_ERR_C2H_MM_MSIX_NO_MSIX_CNT", - C2H_INTR_H2C_ERR_C2H_MM_MSIX_NO_MSIX_CNT_MASK}, -}; - - -static struct regfield_info - c2h_intr_h2c_err_c2h_mm_ctxt_inval_field_info[] = { - {"C2H_INTR_H2C_ERR_C2H_MM_CTXT_INVAL_RSVD_1", - C2H_INTR_H2C_ERR_C2H_MM_CTXT_INVAL_RSVD_1_MASK}, - {"C2H_INTR_H2C_ERR_C2H_MM_CTXT_INVAL_CNT", - C2H_INTR_H2C_ERR_C2H_MM_CTXT_INVAL_CNT_MASK}, -}; - - -static struct regfield_info - c2h_intr_c2h_st_msix_ack_field_info[] = { - {"C2H_INTR_C2H_ST_MSIX_ACK_RSVD_1", - C2H_INTR_C2H_ST_MSIX_ACK_RSVD_1_MASK}, - {"C2H_INTR_C2H_ST_MSIX_ACK_CNT", - C2H_INTR_C2H_ST_MSIX_ACK_CNT_MASK}, -}; - - -static struct regfield_info - c2h_intr_c2h_st_msix_fail_field_info[] = { - {"C2H_INTR_C2H_ST_MSIX_FAIL_RSVD_1", - C2H_INTR_C2H_ST_MSIX_FAIL_RSVD_1_MASK}, - {"C2H_INTR_C2H_ST_MSIX_FAIL_CNT", - C2H_INTR_C2H_ST_MSIX_FAIL_CNT_MASK}, -}; - - -static struct regfield_info - c2h_intr_c2h_st_no_msix_field_info[] = { - {"C2H_INTR_C2H_ST_NO_MSIX_RSVD_1", - C2H_INTR_C2H_ST_NO_MSIX_RSVD_1_MASK}, - {"C2H_INTR_C2H_ST_NO_MSIX_CNT", - C2H_INTR_C2H_ST_NO_MSIX_CNT_MASK}, -}; - - -static struct regfield_info - c2h_intr_c2h_st_ctxt_inval_field_info[] = { - {"C2H_INTR_C2H_ST_CTXT_INVAL_RSVD_1", - C2H_INTR_C2H_ST_CTXT_INVAL_RSVD_1_MASK}, - {"C2H_INTR_C2H_ST_CTXT_INVAL_CNT", - C2H_INTR_C2H_ST_CTXT_INVAL_CNT_MASK}, -}; - - -static struct regfield_info - c2h_stat_wr_cmp_field_info[] = { - {"C2H_STAT_WR_CMP_RSVD_1", - C2H_STAT_WR_CMP_RSVD_1_MASK}, - {"C2H_STAT_WR_CMP_CNT", - C2H_STAT_WR_CMP_CNT_MASK}, -}; - - -static struct regfield_info - c2h_stat_dbg_dma_eng_4_field_info[] = { - {"C2H_STAT_DMA_ENG_4_QID_FIFO_OUT_DAT_HAS_CMPT_1", - C2H_STAT_DMA_ENG_4_QID_FIFO_OUT_DAT_HAS_CMPT_1_MASK}, - {"C2H_STAT_DMA_ENG_4_QID_FIFO_OUT_DAT_MARKER_1", - C2H_STAT_DMA_ENG_4_QID_FIFO_OUT_DAT_MARKER_1_MASK}, - {"C2H_STAT_DMA_ENG_4_QID_FIFO_OUT_DAT_DROP_REQ_1", - C2H_STAT_DMA_ENG_4_QID_FIFO_OUT_DAT_DROP_REQ_1_MASK}, - {"C2H_STAT_DMA_ENG_4_QID_FIFO_OUT_DAT_QID_1", - C2H_STAT_DMA_ENG_4_QID_FIFO_OUT_DAT_QID_1_MASK}, - {"C2H_STAT_DMA_ENG_4_WR_HDR_FIFO_OUT_CNT_1", - C2H_STAT_DMA_ENG_4_WR_HDR_FIFO_OUT_CNT_1_MASK}, - {"C2H_STAT_DMA_ENG_4_QID_FIFO_OUT_VLD_1", - C2H_STAT_DMA_ENG_4_QID_FIFO_OUT_VLD_1_MASK}, - {"C2H_STAT_DMA_ENG_4_PLD_FIFO_OUT_VLD_1", - C2H_STAT_DMA_ENG_4_PLD_FIFO_OUT_VLD_1_MASK}, - {"C2H_STAT_DMA_ENG_4_PLD_ST_FIFO_OUT_VLD_1", - C2H_STAT_DMA_ENG_4_PLD_ST_FIFO_OUT_VLD_1_MASK}, - {"C2H_STAT_DMA_ENG_4_PLD_ST_FIFO_OUT_DATA_EOP_1", - C2H_STAT_DMA_ENG_4_PLD_ST_FIFO_OUT_DATA_EOP_1_MASK}, - {"C2H_STAT_DMA_ENG_4_PLD_ST_FIFO_OUT_DATA_AVL_IDX_ENABLE_1", - C2H_STAT_DMA_ENG_4_PLD_ST_FIFO_OUT_DATA_AVL_IDX_ENABLE_1_MASK}, - {"C2H_STAT_DMA_ENG_4_PLD_ST_FIFO_OUT_DATA_DROP_1", - C2H_STAT_DMA_ENG_4_PLD_ST_FIFO_OUT_DATA_DROP_1_MASK}, - {"C2H_STAT_DMA_ENG_4_PLD_ST_FIFO_OUT_DATA_ERR_1", - C2H_STAT_DMA_ENG_4_PLD_ST_FIFO_OUT_DATA_ERR_1_MASK}, - {"C2H_STAT_DMA_ENG_4_DESC_CNT_FIFO_IN_RDY_1", - C2H_STAT_DMA_ENG_4_DESC_CNT_FIFO_IN_RDY_1_MASK}, - {"C2H_STAT_DMA_ENG_4_DESC_RSP_FIFO_IN_RDY_1", - C2H_STAT_DMA_ENG_4_DESC_RSP_FIFO_IN_RDY_1_MASK}, - {"C2H_STAT_DMA_ENG_4_PLD_PKT_ID_LARGER_1", - C2H_STAT_DMA_ENG_4_PLD_PKT_ID_LARGER_1_MASK}, - {"C2H_STAT_DMA_ENG_4_WCP_FIFO_IN_RDY_1", - C2H_STAT_DMA_ENG_4_WCP_FIFO_IN_RDY_1_MASK}, - {"C2H_STAT_DMA_ENG_4_PLD_ST_FIFO_IN_RDY_1", - C2H_STAT_DMA_ENG_4_PLD_ST_FIFO_IN_RDY_1_MASK}, -}; - - -static struct regfield_info - c2h_stat_dbg_dma_eng_5_field_info[] = { - {"C2H_STAT_DMA_ENG_5_ARB_FIFO_IN_RDY", - C2H_STAT_DMA_ENG_5_ARB_FIFO_IN_RDY_MASK}, - {"C2H_STAT_DMA_ENG_5_WRB_SM_VIRT_CH", - C2H_STAT_DMA_ENG_5_WRB_SM_VIRT_CH_MASK}, - {"C2H_STAT_DMA_ENG_5_WRB_FIFO_IN_REQ", - C2H_STAT_DMA_ENG_5_WRB_FIFO_IN_REQ_MASK}, - {"C2H_STAT_DMA_ENG_5_ARB_FIFO_OUT_CNT", - C2H_STAT_DMA_ENG_5_ARB_FIFO_OUT_CNT_MASK}, - {"C2H_STAT_DMA_ENG_5_ARB_FIFO_OUT_DATA_LEN", - C2H_STAT_DMA_ENG_5_ARB_FIFO_OUT_DATA_LEN_MASK}, - {"C2H_STAT_DMA_ENG_5_ARB_FIFO_OUT_DATA_VIRT_CH", - C2H_STAT_DMA_ENG_5_ARB_FIFO_OUT_DATA_VIRT_CH_MASK}, - {"C2H_STAT_DMA_ENG_5_ARB_FIFO_OUT_DATA_VAR_DESC", - C2H_STAT_DMA_ENG_5_ARB_FIFO_OUT_DATA_VAR_DESC_MASK}, - {"C2H_STAT_DMA_ENG_5_ARB_FIFO_OUT_DATA_DROP_REQ", - C2H_STAT_DMA_ENG_5_ARB_FIFO_OUT_DATA_DROP_REQ_MASK}, - {"C2H_STAT_DMA_ENG_5_ARB_FIFO_OUT_DATA_NUM_BUF_OV", - C2H_STAT_DMA_ENG_5_ARB_FIFO_OUT_DATA_NUM_BUF_OV_MASK}, - {"C2H_STAT_DMA_ENG_5_ARB_FIFO_OUT_DATA_MARKER", - C2H_STAT_DMA_ENG_5_ARB_FIFO_OUT_DATA_MARKER_MASK}, - {"C2H_STAT_DMA_ENG_5_ARB_FIFO_OUT_DATA_HAS_CMPT", - C2H_STAT_DMA_ENG_5_ARB_FIFO_OUT_DATA_HAS_CMPT_MASK}, -}; - - -static struct regfield_info - c2h_dbg_pfch_qid_field_info[] = { - {"C2H_PFCH_QID_RSVD_1", - C2H_PFCH_QID_RSVD_1_MASK}, - {"C2H_PFCH_QID_ERR_CTXT", - C2H_PFCH_QID_ERR_CTXT_MASK}, - {"C2H_PFCH_QID_TARGET", - C2H_PFCH_QID_TARGET_MASK}, - {"C2H_PFCH_QID_QID_OR_TAG", - C2H_PFCH_QID_QID_OR_TAG_MASK}, -}; - - -static struct regfield_info - c2h_dbg_pfch_field_info[] = { - {"C2H_PFCH_DATA", - C2H_PFCH_DATA_MASK}, -}; - - -static struct regfield_info - c2h_int_dbg_field_info[] = { - {"C2H_INT_RSVD_1", - C2H_INT_RSVD_1_MASK}, - {"C2H_INT_INT_COAL_SM", - C2H_INT_INT_COAL_SM_MASK}, - {"C2H_INT_INT_SM", - C2H_INT_INT_SM_MASK}, -}; - - -static struct regfield_info - c2h_stat_imm_accepted_field_info[] = { - {"C2H_STAT_IMM_ACCEPTED_RSVD_1", - C2H_STAT_IMM_ACCEPTED_RSVD_1_MASK}, - {"C2H_STAT_IMM_ACCEPTED_CNT", - C2H_STAT_IMM_ACCEPTED_CNT_MASK}, -}; - - -static struct regfield_info - c2h_stat_marker_accepted_field_info[] = { - {"C2H_STAT_MARKER_ACCEPTED_RSVD_1", - C2H_STAT_MARKER_ACCEPTED_RSVD_1_MASK}, - {"C2H_STAT_MARKER_ACCEPTED_CNT", - C2H_STAT_MARKER_ACCEPTED_CNT_MASK}, -}; - - -static struct regfield_info - c2h_stat_disable_cmp_accepted_field_info[] = { - {"C2H_STAT_DISABLE_CMP_ACCEPTED_RSVD_1", - C2H_STAT_DISABLE_CMP_ACCEPTED_RSVD_1_MASK}, - {"C2H_STAT_DISABLE_CMP_ACCEPTED_CNT", - C2H_STAT_DISABLE_CMP_ACCEPTED_CNT_MASK}, -}; - - -static struct regfield_info - c2h_pld_fifo_crdt_cnt_field_info[] = { - {"C2H_PLD_FIFO_CRDT_CNT_RSVD_1", - C2H_PLD_FIFO_CRDT_CNT_RSVD_1_MASK}, - {"C2H_PLD_FIFO_CRDT_CNT_CNT", - C2H_PLD_FIFO_CRDT_CNT_CNT_MASK}, -}; - - -static struct regfield_info - c2h_intr_dyn_req_field_info[] = { - {"C2H_INTR_DYN_REQ_RSVD_1", - C2H_INTR_DYN_REQ_RSVD_1_MASK}, - {"C2H_INTR_DYN_REQ_CNT", - C2H_INTR_DYN_REQ_CNT_MASK}, -}; - - -static struct regfield_info - c2h_intr_dyn_misc_field_info[] = { - {"C2H_INTR_DYN_MISC_RSVD_1", - C2H_INTR_DYN_MISC_RSVD_1_MASK}, - {"C2H_INTR_DYN_MISC_CNT", - C2H_INTR_DYN_MISC_CNT_MASK}, -}; - - -static struct regfield_info - c2h_drop_len_mismatch_field_info[] = { - {"C2H_DROP_LEN_MISMATCH_RSVD_1", - C2H_DROP_LEN_MISMATCH_RSVD_1_MASK}, - {"C2H_DROP_LEN_MISMATCH_CNT", - C2H_DROP_LEN_MISMATCH_CNT_MASK}, -}; - - -static struct regfield_info - c2h_drop_desc_rsp_len_field_info[] = { - {"C2H_DROP_DESC_RSP_LEN_RSVD_1", - C2H_DROP_DESC_RSP_LEN_RSVD_1_MASK}, - {"C2H_DROP_DESC_RSP_LEN_CNT", - C2H_DROP_DESC_RSP_LEN_CNT_MASK}, -}; - - -static struct regfield_info - c2h_drop_qid_fifo_len_field_info[] = { - {"C2H_DROP_QID_FIFO_LEN_RSVD_1", - C2H_DROP_QID_FIFO_LEN_RSVD_1_MASK}, - {"C2H_DROP_QID_FIFO_LEN_CNT", - C2H_DROP_QID_FIFO_LEN_CNT_MASK}, -}; - - -static struct regfield_info - c2h_drop_pld_cnt_field_info[] = { - {"C2H_DROP_PLD_CNT_RSVD_1", - C2H_DROP_PLD_CNT_RSVD_1_MASK}, - {"C2H_DROP_PLD_CNT_CNT", - C2H_DROP_PLD_CNT_CNT_MASK}, -}; - - -static struct regfield_info - c2h_cmpt_format_0_field_info[] = { - {"C2H_CMPT_FORMAT_0_DESC_ERR_LOC", - C2H_CMPT_FORMAT_0_DESC_ERR_LOC_MASK}, - {"C2H_CMPT_FORMAT_0_COLOR_LOC", - C2H_CMPT_FORMAT_0_COLOR_LOC_MASK}, -}; - - -static struct regfield_info - c2h_cmpt_format_1_field_info[] = { - {"C2H_CMPT_FORMAT_1_DESC_ERR_LOC", - C2H_CMPT_FORMAT_1_DESC_ERR_LOC_MASK}, - {"C2H_CMPT_FORMAT_1_COLOR_LOC", - C2H_CMPT_FORMAT_1_COLOR_LOC_MASK}, -}; - - -static struct regfield_info - c2h_cmpt_format_2_field_info[] = { - {"C2H_CMPT_FORMAT_2_DESC_ERR_LOC", - C2H_CMPT_FORMAT_2_DESC_ERR_LOC_MASK}, - {"C2H_CMPT_FORMAT_2_COLOR_LOC", - C2H_CMPT_FORMAT_2_COLOR_LOC_MASK}, -}; - - -static struct regfield_info - c2h_cmpt_format_3_field_info[] = { - {"C2H_CMPT_FORMAT_3_DESC_ERR_LOC", - C2H_CMPT_FORMAT_3_DESC_ERR_LOC_MASK}, - {"C2H_CMPT_FORMAT_3_COLOR_LOC", - C2H_CMPT_FORMAT_3_COLOR_LOC_MASK}, -}; - - -static struct regfield_info - c2h_cmpt_format_4_field_info[] = { - {"C2H_CMPT_FORMAT_4_DESC_ERR_LOC", - C2H_CMPT_FORMAT_4_DESC_ERR_LOC_MASK}, - {"C2H_CMPT_FORMAT_4_COLOR_LOC", - C2H_CMPT_FORMAT_4_COLOR_LOC_MASK}, -}; - - -static struct regfield_info - c2h_cmpt_format_5_field_info[] = { - {"C2H_CMPT_FORMAT_5_DESC_ERR_LOC", - C2H_CMPT_FORMAT_5_DESC_ERR_LOC_MASK}, - {"C2H_CMPT_FORMAT_5_COLOR_LOC", - C2H_CMPT_FORMAT_5_COLOR_LOC_MASK}, -}; - - -static struct regfield_info - c2h_cmpt_format_6_field_info[] = { - {"C2H_CMPT_FORMAT_6_DESC_ERR_LOC", - C2H_CMPT_FORMAT_6_DESC_ERR_LOC_MASK}, - {"C2H_CMPT_FORMAT_6_COLOR_LOC", - C2H_CMPT_FORMAT_6_COLOR_LOC_MASK}, -}; - - -static struct regfield_info - c2h_pfch_cache_depth_field_info[] = { - {"C2H_PFCH_CACHE_DEPTH_MAX_STBUF", - C2H_PFCH_CACHE_DEPTH_MAX_STBUF_MASK}, - {"C2H_PFCH_CACHE_DEPTH", - C2H_PFCH_CACHE_DEPTH_MASK}, -}; - - -static struct regfield_info - c2h_wrb_coal_buf_depth_field_info[] = { - {"C2H_WRB_COAL_BUF_DEPTH_RSVD_1", - C2H_WRB_COAL_BUF_DEPTH_RSVD_1_MASK}, - {"C2H_WRB_COAL_BUF_DEPTH_BUFFER", - C2H_WRB_COAL_BUF_DEPTH_BUFFER_MASK}, -}; - - -static struct regfield_info - c2h_pfch_crdt_field_info[] = { - {"C2H_PFCH_CRDT_RSVD_1", - C2H_PFCH_CRDT_RSVD_1_MASK}, - {"C2H_PFCH_CRDT_RSVD_2", - C2H_PFCH_CRDT_RSVD_2_MASK}, -}; - - -static struct regfield_info - c2h_stat_has_cmpt_accepted_field_info[] = { - {"C2H_STAT_HAS_CMPT_ACCEPTED_RSVD_1", - C2H_STAT_HAS_CMPT_ACCEPTED_RSVD_1_MASK}, - {"C2H_STAT_HAS_CMPT_ACCEPTED_CNT", - C2H_STAT_HAS_CMPT_ACCEPTED_CNT_MASK}, -}; - - -static struct regfield_info - c2h_stat_has_pld_accepted_field_info[] = { - {"C2H_STAT_HAS_PLD_ACCEPTED_RSVD_1", - C2H_STAT_HAS_PLD_ACCEPTED_RSVD_1_MASK}, - {"C2H_STAT_HAS_PLD_ACCEPTED_CNT", - C2H_STAT_HAS_PLD_ACCEPTED_CNT_MASK}, -}; - - -static struct regfield_info - c2h_pld_pkt_id_field_info[] = { - {"C2H_PLD_PKT_ID_CMPT_WAIT", - C2H_PLD_PKT_ID_CMPT_WAIT_MASK}, - {"C2H_PLD_PKT_ID_DATA", - C2H_PLD_PKT_ID_DATA_MASK}, -}; - - -static struct regfield_info - c2h_pld_pkt_id_1_field_info[] = { - {"C2H_PLD_PKT_ID_1_CMPT_WAIT", - C2H_PLD_PKT_ID_1_CMPT_WAIT_MASK}, - {"C2H_PLD_PKT_ID_1_DATA", - C2H_PLD_PKT_ID_1_DATA_MASK}, -}; - - -static struct regfield_info - c2h_drop_pld_cnt_1_field_info[] = { - {"C2H_DROP_PLD_CNT_1_RSVD_1", - C2H_DROP_PLD_CNT_1_RSVD_1_MASK}, - {"C2H_DROP_PLD_CNT_1_CNT", - C2H_DROP_PLD_CNT_1_CNT_MASK}, -}; - - -static struct regfield_info - h2c_err_stat_field_info[] = { - {"H2C_ERR_STAT_RSVD_1", - H2C_ERR_STAT_RSVD_1_MASK}, - {"H2C_ERR_STAT_PAR_ERR", - H2C_ERR_STAT_PAR_ERR_MASK}, - {"H2C_ERR_STAT_SBE", - H2C_ERR_STAT_SBE_MASK}, - {"H2C_ERR_STAT_DBE", - H2C_ERR_STAT_DBE_MASK}, - {"H2C_ERR_STAT_NO_DMA_DS", - H2C_ERR_STAT_NO_DMA_DS_MASK}, - {"H2C_ERR_STAT_SDI_MRKR_REQ_MOP_ERR", - H2C_ERR_STAT_SDI_MRKR_REQ_MOP_ERR_MASK}, - {"H2C_ERR_STAT_ZERO_LEN_DS", - H2C_ERR_STAT_ZERO_LEN_DS_MASK}, -}; - - -static struct regfield_info - h2c_err_mask_field_info[] = { - {"H2C_ERR_EN", - H2C_ERR_EN_MASK}, -}; - - -static struct regfield_info - h2c_first_err_qid_field_info[] = { - {"H2C_FIRST_ERR_QID_RSVD_1", - H2C_FIRST_ERR_QID_RSVD_1_MASK}, - {"H2C_FIRST_ERR_QID_ERR_TYPE", - H2C_FIRST_ERR_QID_ERR_TYPE_MASK}, - {"H2C_FIRST_ERR_QID_RSVD_2", - H2C_FIRST_ERR_QID_RSVD_2_MASK}, - {"H2C_FIRST_ERR_QID_QID", - H2C_FIRST_ERR_QID_QID_MASK}, -}; - - -static struct regfield_info - h2c_dbg_reg0_field_info[] = { - {"H2C_REG0_NUM_DSC_RCVD", - H2C_REG0_NUM_DSC_RCVD_MASK}, - {"H2C_REG0_NUM_WRB_SENT", - H2C_REG0_NUM_WRB_SENT_MASK}, -}; - - -static struct regfield_info - h2c_dbg_reg1_field_info[] = { - {"H2C_REG1_NUM_REQ_SENT", - H2C_REG1_NUM_REQ_SENT_MASK}, - {"H2C_REG1_NUM_CMP_SENT", - H2C_REG1_NUM_CMP_SENT_MASK}, -}; - - -static struct regfield_info - h2c_dbg_reg2_field_info[] = { - {"H2C_REG2_RSVD_1", - H2C_REG2_RSVD_1_MASK}, - {"H2C_REG2_NUM_ERR_DSC_RCVD", - H2C_REG2_NUM_ERR_DSC_RCVD_MASK}, -}; - - -static struct regfield_info - h2c_dbg_reg3_field_info[] = { - {"H2C_REG3_RSVD_1", - H2C_REG3_RSVD_1_MASK}, - {"H2C_REG3_DSCO_FIFO_EMPTY", - H2C_REG3_DSCO_FIFO_EMPTY_MASK}, - {"H2C_REG3_DSCO_FIFO_FULL", - H2C_REG3_DSCO_FIFO_FULL_MASK}, - {"H2C_REG3_CUR_RC_STATE", - H2C_REG3_CUR_RC_STATE_MASK}, - {"H2C_REG3_RDREQ_LINES", - H2C_REG3_RDREQ_LINES_MASK}, - {"H2C_REG3_RDATA_LINES_AVAIL", - H2C_REG3_RDATA_LINES_AVAIL_MASK}, - {"H2C_REG3_PEND_FIFO_EMPTY", - H2C_REG3_PEND_FIFO_EMPTY_MASK}, - {"H2C_REG3_PEND_FIFO_FULL", - H2C_REG3_PEND_FIFO_FULL_MASK}, - {"H2C_REG3_CUR_RQ_STATE", - H2C_REG3_CUR_RQ_STATE_MASK}, - {"H2C_REG3_DSCI_FIFO_FULL", - H2C_REG3_DSCI_FIFO_FULL_MASK}, - {"H2C_REG3_DSCI_FIFO_EMPTY", - H2C_REG3_DSCI_FIFO_EMPTY_MASK}, -}; - - -static struct regfield_info - h2c_dbg_reg4_field_info[] = { - {"H2C_REG4_RDREQ_ADDR", - H2C_REG4_RDREQ_ADDR_MASK}, -}; - - -static struct regfield_info - h2c_fatal_err_en_field_info[] = { - {"H2C_FATAL_ERR_EN_RSVD_1", - H2C_FATAL_ERR_EN_RSVD_1_MASK}, - {"H2C_FATAL_ERR_EN_H2C", - H2C_FATAL_ERR_EN_H2C_MASK}, -}; - - -static struct regfield_info - h2c_req_throt_pcie_field_info[] = { - {"H2C_REQ_THROT_PCIE_EN_REQ", - H2C_REQ_THROT_PCIE_EN_REQ_MASK}, - {"H2C_REQ_THROT_PCIE", - H2C_REQ_THROT_PCIE_MASK}, - {"H2C_REQ_THROT_PCIE_EN_DATA", - H2C_REQ_THROT_PCIE_EN_DATA_MASK}, - {"H2C_REQ_THROT_PCIE_DATA_THRESH", - H2C_REQ_THROT_PCIE_DATA_THRESH_MASK}, -}; - - -static struct regfield_info - h2c_aln_dbg_reg0_field_info[] = { - {"H2C_ALN_REG0_NUM_PKT_SENT", - H2C_ALN_REG0_NUM_PKT_SENT_MASK}, -}; - - -static struct regfield_info - h2c_req_throt_aximm_field_info[] = { - {"H2C_REQ_THROT_AXIMM_EN_REQ", - H2C_REQ_THROT_AXIMM_EN_REQ_MASK}, - {"H2C_REQ_THROT_AXIMM", - H2C_REQ_THROT_AXIMM_MASK}, - {"H2C_REQ_THROT_AXIMM_EN_DATA", - H2C_REQ_THROT_AXIMM_EN_DATA_MASK}, - {"H2C_REQ_THROT_AXIMM_DATA_THRESH", - H2C_REQ_THROT_AXIMM_DATA_THRESH_MASK}, -}; - - -static struct regfield_info - c2h_mm_ctl_field_info[] = { - {"C2H_MM_CTL_RESERVED1", - C2H_MM_CTL_RESERVED1_MASK}, - {"C2H_MM_CTL_ERRC_EN", - C2H_MM_CTL_ERRC_EN_MASK}, - {"C2H_MM_CTL_RESERVED0", - C2H_MM_CTL_RESERVED0_MASK}, - {"C2H_MM_CTL_RUN", - C2H_MM_CTL_RUN_MASK}, -}; - - -static struct regfield_info - c2h_mm_status_field_info[] = { - {"C2H_MM_STATUS_RSVD_1", - C2H_MM_STATUS_RSVD_1_MASK}, - {"C2H_MM_STATUS_RUN", - C2H_MM_STATUS_RUN_MASK}, -}; - - -static struct regfield_info - c2h_mm_cmpl_desc_cnt_field_info[] = { - {"C2H_MM_CMPL_DESC_CNT_C2H_CO", - C2H_MM_CMPL_DESC_CNT_C2H_CO_MASK}, -}; - - -static struct regfield_info - c2h_mm_err_code_enable_mask_field_info[] = { - {"C2H_MM_ERR_CODE_ENABLE_RESERVED1", - C2H_MM_ERR_CODE_ENABLE_RESERVED1_MASK}, - {"C2H_MM_ERR_CODE_ENABLE_WR_UC_RAM", - C2H_MM_ERR_CODE_ENABLE_WR_UC_RAM_MASK}, - {"C2H_MM_ERR_CODE_ENABLE_WR_UR", - C2H_MM_ERR_CODE_ENABLE_WR_UR_MASK}, - {"C2H_MM_ERR_CODE_ENABLE_WR_FLR", - C2H_MM_ERR_CODE_ENABLE_WR_FLR_MASK}, - {"C2H_MM_ERR_CODE_ENABLE_RESERVED0", - C2H_MM_ERR_CODE_ENABLE_RESERVED0_MASK}, - {"C2H_MM_ERR_CODE_ENABLE_RD_SLV_ERR", - C2H_MM_ERR_CODE_ENABLE_RD_SLV_ERR_MASK}, - {"C2H_MM_ERR_CODE_ENABLE_WR_SLV_ERR", - C2H_MM_ERR_CODE_ENABLE_WR_SLV_ERR_MASK}, -}; - - -static struct regfield_info - c2h_mm_err_code_field_info[] = { - {"C2H_MM_ERR_CODE_RESERVED1", - C2H_MM_ERR_CODE_RESERVED1_MASK}, - {"C2H_MM_ERR_CODE_CIDX", - C2H_MM_ERR_CODE_CIDX_MASK}, - {"C2H_MM_ERR_CODE_RESERVED0", - C2H_MM_ERR_CODE_RESERVED0_MASK}, - {"C2H_MM_ERR_CODE_SUB_TYPE", - C2H_MM_ERR_CODE_SUB_TYPE_MASK}, - {"C2H_MM_ERR_CODE", - C2H_MM_ERR_CODE_MASK}, -}; - - -static struct regfield_info - c2h_mm_err_info_field_info[] = { - {"C2H_MM_ERR_INFO_VALID", - C2H_MM_ERR_INFO_VALID_MASK}, - {"C2H_MM_ERR_INFO_SEL", - C2H_MM_ERR_INFO_SEL_MASK}, - {"C2H_MM_ERR_INFO_RSVD_1", - C2H_MM_ERR_INFO_RSVD_1_MASK}, - {"C2H_MM_ERR_INFO_QID", - C2H_MM_ERR_INFO_QID_MASK}, -}; - - -static struct regfield_info - c2h_mm_perf_mon_ctl_field_info[] = { - {"C2H_MM_PERF_MON_CTL_RSVD_1", - C2H_MM_PERF_MON_CTL_RSVD_1_MASK}, - {"C2H_MM_PERF_MON_CTL_IMM_START", - C2H_MM_PERF_MON_CTL_IMM_START_MASK}, - {"C2H_MM_PERF_MON_CTL_RUN_START", - C2H_MM_PERF_MON_CTL_RUN_START_MASK}, - {"C2H_MM_PERF_MON_CTL_IMM_CLEAR", - C2H_MM_PERF_MON_CTL_IMM_CLEAR_MASK}, - {"C2H_MM_PERF_MON_CTL_RUN_CLEAR", - C2H_MM_PERF_MON_CTL_RUN_CLEAR_MASK}, -}; - - -static struct regfield_info - c2h_mm_perf_mon_cycle_cnt0_field_info[] = { - {"C2H_MM_PERF_MON_CYCLE_CNT0_CYC_CNT", - C2H_MM_PERF_MON_CYCLE_CNT0_CYC_CNT_MASK}, -}; - - -static struct regfield_info - c2h_mm_perf_mon_cycle_cnt1_field_info[] = { - {"C2H_MM_PERF_MON_CYCLE_CNT1_RSVD_1", - C2H_MM_PERF_MON_CYCLE_CNT1_RSVD_1_MASK}, - {"C2H_MM_PERF_MON_CYCLE_CNT1_CYC_CNT", - C2H_MM_PERF_MON_CYCLE_CNT1_CYC_CNT_MASK}, -}; - - -static struct regfield_info - c2h_mm_perf_mon_data_cnt0_field_info[] = { - {"C2H_MM_PERF_MON_DATA_CNT0_DCNT", - C2H_MM_PERF_MON_DATA_CNT0_DCNT_MASK}, -}; - - -static struct regfield_info - c2h_mm_perf_mon_data_cnt1_field_info[] = { - {"C2H_MM_PERF_MON_DATA_CNT1_RSVD_1", - C2H_MM_PERF_MON_DATA_CNT1_RSVD_1_MASK}, - {"C2H_MM_PERF_MON_DATA_CNT1_DCNT", - C2H_MM_PERF_MON_DATA_CNT1_DCNT_MASK}, -}; - - -static struct regfield_info - c2h_mm_dbg_field_info[] = { - {"C2H_MM_RSVD_1", - C2H_MM_RSVD_1_MASK}, - {"C2H_MM_RRQ_ENTRIES", - C2H_MM_RRQ_ENTRIES_MASK}, - {"C2H_MM_DAT_FIFO_SPC", - C2H_MM_DAT_FIFO_SPC_MASK}, - {"C2H_MM_RD_STALL", - C2H_MM_RD_STALL_MASK}, - {"C2H_MM_RRQ_FIFO_FI", - C2H_MM_RRQ_FIFO_FI_MASK}, - {"C2H_MM_WR_STALL", - C2H_MM_WR_STALL_MASK}, - {"C2H_MM_WRQ_FIFO_FI", - C2H_MM_WRQ_FIFO_FI_MASK}, - {"C2H_MM_WBK_STALL", - C2H_MM_WBK_STALL_MASK}, - {"C2H_MM_DSC_FIFO_EP", - C2H_MM_DSC_FIFO_EP_MASK}, - {"C2H_MM_DSC_FIFO_FL", - C2H_MM_DSC_FIFO_FL_MASK}, -}; - - -static struct regfield_info - h2c_mm_ctl_field_info[] = { - {"H2C_MM_CTL_RESERVED1", - H2C_MM_CTL_RESERVED1_MASK}, - {"H2C_MM_CTL_ERRC_EN", - H2C_MM_CTL_ERRC_EN_MASK}, - {"H2C_MM_CTL_RESERVED0", - H2C_MM_CTL_RESERVED0_MASK}, - {"H2C_MM_CTL_RUN", - H2C_MM_CTL_RUN_MASK}, -}; - - -static struct regfield_info - h2c_mm_status_field_info[] = { - {"H2C_MM_STATUS_RSVD_1", - H2C_MM_STATUS_RSVD_1_MASK}, - {"H2C_MM_STATUS_RUN", - H2C_MM_STATUS_RUN_MASK}, -}; - - -static struct regfield_info - h2c_mm_cmpl_desc_cnt_field_info[] = { - {"H2C_MM_CMPL_DESC_CNT_H2C_CO", - H2C_MM_CMPL_DESC_CNT_H2C_CO_MASK}, -}; - - -static struct regfield_info - h2c_mm_err_code_enable_mask_field_info[] = { - {"H2C_MM_ERR_CODE_ENABLE_RESERVED5", - H2C_MM_ERR_CODE_ENABLE_RESERVED5_MASK}, - {"H2C_MM_ERR_CODE_ENABLE_WR_SLV_ERR", - H2C_MM_ERR_CODE_ENABLE_WR_SLV_ERR_MASK}, - {"H2C_MM_ERR_CODE_ENABLE_WR_DEC_ERR", - H2C_MM_ERR_CODE_ENABLE_WR_DEC_ERR_MASK}, - {"H2C_MM_ERR_CODE_ENABLE_RESERVED4", - H2C_MM_ERR_CODE_ENABLE_RESERVED4_MASK}, - {"H2C_MM_ERR_CODE_ENABLE_RD_RQ_DIS_ERR", - H2C_MM_ERR_CODE_ENABLE_RD_RQ_DIS_ERR_MASK}, - {"H2C_MM_ERR_CODE_ENABLE_RESERVED3", - H2C_MM_ERR_CODE_ENABLE_RESERVED3_MASK}, - {"H2C_MM_ERR_CODE_ENABLE_RD_DAT_POISON_ERR", - H2C_MM_ERR_CODE_ENABLE_RD_DAT_POISON_ERR_MASK}, - {"H2C_MM_ERR_CODE_ENABLE_RESERVED2", - H2C_MM_ERR_CODE_ENABLE_RESERVED2_MASK}, - {"H2C_MM_ERR_CODE_ENABLE_RD_FLR_ERR", - H2C_MM_ERR_CODE_ENABLE_RD_FLR_ERR_MASK}, - {"H2C_MM_ERR_CODE_ENABLE_RESERVED1", - H2C_MM_ERR_CODE_ENABLE_RESERVED1_MASK}, - {"H2C_MM_ERR_CODE_ENABLE_RD_HDR_ADR_ERR", - H2C_MM_ERR_CODE_ENABLE_RD_HDR_ADR_ERR_MASK}, - {"H2C_MM_ERR_CODE_ENABLE_RD_HDR_PARA", - H2C_MM_ERR_CODE_ENABLE_RD_HDR_PARA_MASK}, - {"H2C_MM_ERR_CODE_ENABLE_RD_HDR_BYTE_ERR", - H2C_MM_ERR_CODE_ENABLE_RD_HDR_BYTE_ERR_MASK}, - {"H2C_MM_ERR_CODE_ENABLE_RD_UR_CA", - H2C_MM_ERR_CODE_ENABLE_RD_UR_CA_MASK}, - {"H2C_MM_ERR_CODE_ENABLE_RD_HRD_POISON_ERR", - H2C_MM_ERR_CODE_ENABLE_RD_HRD_POISON_ERR_MASK}, - {"H2C_MM_ERR_CODE_ENABLE_RESERVED0", - H2C_MM_ERR_CODE_ENABLE_RESERVED0_MASK}, -}; - - -static struct regfield_info - h2c_mm_err_code_field_info[] = { - {"H2C_MM_ERR_CODE_RSVD_1", - H2C_MM_ERR_CODE_RSVD_1_MASK}, - {"H2C_MM_ERR_CODE_CIDX", - H2C_MM_ERR_CODE_CIDX_MASK}, - {"H2C_MM_ERR_CODE_RESERVED0", - H2C_MM_ERR_CODE_RESERVED0_MASK}, - {"H2C_MM_ERR_CODE_SUB_TYPE", - H2C_MM_ERR_CODE_SUB_TYPE_MASK}, - {"H2C_MM_ERR_CODE", - H2C_MM_ERR_CODE_MASK}, -}; - - -static struct regfield_info - h2c_mm_err_info_field_info[] = { - {"H2C_MM_ERR_INFO_VALID", - H2C_MM_ERR_INFO_VALID_MASK}, - {"H2C_MM_ERR_INFO_SEL", - H2C_MM_ERR_INFO_SEL_MASK}, - {"H2C_MM_ERR_INFO_RSVD_1", - H2C_MM_ERR_INFO_RSVD_1_MASK}, - {"H2C_MM_ERR_INFO_QID", - H2C_MM_ERR_INFO_QID_MASK}, -}; - - -static struct regfield_info - h2c_mm_perf_mon_ctl_field_info[] = { - {"H2C_MM_PERF_MON_CTL_RSVD_1", - H2C_MM_PERF_MON_CTL_RSVD_1_MASK}, - {"H2C_MM_PERF_MON_CTL_IMM_START", - H2C_MM_PERF_MON_CTL_IMM_START_MASK}, - {"H2C_MM_PERF_MON_CTL_RUN_START", - H2C_MM_PERF_MON_CTL_RUN_START_MASK}, - {"H2C_MM_PERF_MON_CTL_IMM_CLEAR", - H2C_MM_PERF_MON_CTL_IMM_CLEAR_MASK}, - {"H2C_MM_PERF_MON_CTL_RUN_CLEAR", - H2C_MM_PERF_MON_CTL_RUN_CLEAR_MASK}, -}; - - -static struct regfield_info - h2c_mm_perf_mon_cycle_cnt0_field_info[] = { - {"H2C_MM_PERF_MON_CYCLE_CNT0_CYC_CNT", - H2C_MM_PERF_MON_CYCLE_CNT0_CYC_CNT_MASK}, -}; - - -static struct regfield_info - h2c_mm_perf_mon_cycle_cnt1_field_info[] = { - {"H2C_MM_PERF_MON_CYCLE_CNT1_RSVD_1", - H2C_MM_PERF_MON_CYCLE_CNT1_RSVD_1_MASK}, - {"H2C_MM_PERF_MON_CYCLE_CNT1_CYC_CNT", - H2C_MM_PERF_MON_CYCLE_CNT1_CYC_CNT_MASK}, -}; - - -static struct regfield_info - h2c_mm_perf_mon_data_cnt0_field_info[] = { - {"H2C_MM_PERF_MON_DATA_CNT0_DCNT", - H2C_MM_PERF_MON_DATA_CNT0_DCNT_MASK}, -}; - - -static struct regfield_info - h2c_mm_perf_mon_data_cnt1_field_info[] = { - {"H2C_MM_PERF_MON_DATA_CNT1_RSVD_1", - H2C_MM_PERF_MON_DATA_CNT1_RSVD_1_MASK}, - {"H2C_MM_PERF_MON_DATA_CNT1_DCNT", - H2C_MM_PERF_MON_DATA_CNT1_DCNT_MASK}, -}; - - -static struct regfield_info - h2c_mm_dbg_field_info[] = { - {"H2C_MM_RSVD_1", - H2C_MM_RSVD_1_MASK}, - {"H2C_MM_RRQ_ENTRIES", - H2C_MM_RRQ_ENTRIES_MASK}, - {"H2C_MM_DAT_FIFO_SPC", - H2C_MM_DAT_FIFO_SPC_MASK}, - {"H2C_MM_RD_STALL", - H2C_MM_RD_STALL_MASK}, - {"H2C_MM_RRQ_FIFO_FI", - H2C_MM_RRQ_FIFO_FI_MASK}, - {"H2C_MM_WR_STALL", - H2C_MM_WR_STALL_MASK}, - {"H2C_MM_WRQ_FIFO_FI", - H2C_MM_WRQ_FIFO_FI_MASK}, - {"H2C_MM_WBK_STALL", - H2C_MM_WBK_STALL_MASK}, - {"H2C_MM_DSC_FIFO_EP", - H2C_MM_DSC_FIFO_EP_MASK}, - {"H2C_MM_DSC_FIFO_FL", - H2C_MM_DSC_FIFO_FL_MASK}, -}; - - -static struct regfield_info - h2c_mm_data_throttle_field_info[] = { - {"H2C_MM_DATA_THROTTLE_RSVD_1", - H2C_MM_DATA_THROTTLE_RSVD_1_MASK}, - {"H2C_MM_DATA_THROTTLE_DAT_EN", - H2C_MM_DATA_THROTTLE_DAT_EN_MASK}, - {"H2C_MM_DATA_THROTTLE_DAT", - H2C_MM_DATA_THROTTLE_DAT_MASK}, -}; - - -static struct regfield_info - c2h_crdt_coal_cfg_1_field_info[] = { - {"C2H_CRDT_COAL_CFG_1_RSVD_1", - C2H_CRDT_COAL_CFG_1_RSVD_1_MASK}, - {"C2H_CRDT_COAL_CFG_1_PLD_FIFO_TH", - C2H_CRDT_COAL_CFG_1_PLD_FIFO_TH_MASK}, - {"C2H_CRDT_COAL_CFG_1_TIMER_TH", - C2H_CRDT_COAL_CFG_1_TIMER_TH_MASK}, -}; - - -static struct regfield_info - c2h_crdt_coal_cfg_2_field_info[] = { - {"C2H_CRDT_COAL_CFG_2_RSVD_1", - C2H_CRDT_COAL_CFG_2_RSVD_1_MASK}, - {"C2H_CRDT_COAL_CFG_2_FIFO_TH", - C2H_CRDT_COAL_CFG_2_FIFO_TH_MASK}, - {"C2H_CRDT_COAL_CFG_2_RESERVED1", - C2H_CRDT_COAL_CFG_2_RESERVED1_MASK}, - {"C2H_CRDT_COAL_CFG_2_NT_TH", - C2H_CRDT_COAL_CFG_2_NT_TH_MASK}, -}; - - -static struct regfield_info - c2h_pfch_byp_qid_field_info[] = { - {"C2H_PFCH_BYP_QID_RSVD_1", - C2H_PFCH_BYP_QID_RSVD_1_MASK}, - {"C2H_PFCH_BYP_QID", - C2H_PFCH_BYP_QID_MASK}, -}; - - -static struct regfield_info - c2h_pfch_byp_tag_field_info[] = { - {"C2H_PFCH_BYP_TAG_RSVD_1", - C2H_PFCH_BYP_TAG_RSVD_1_MASK}, - {"C2H_PFCH_BYP_TAG_BYP_QID", - C2H_PFCH_BYP_TAG_BYP_QID_MASK}, - {"C2H_PFCH_BYP_TAG_RSVD_2", - C2H_PFCH_BYP_TAG_RSVD_2_MASK}, - {"C2H_PFCH_BYP_TAG", - C2H_PFCH_BYP_TAG_MASK}, -}; - - -static struct regfield_info - c2h_water_mark_field_info[] = { - {"C2H_WATER_MARK_HIGH_WM", - C2H_WATER_MARK_HIGH_WM_MASK}, - {"C2H_WATER_MARK_LOW_WM", - C2H_WATER_MARK_LOW_WM_MASK}, -}; - - -static struct regfield_info - c2h_notify_empty_field_info[] = { - {"C2H_NOTIFY_EMPTY_RSVD_1", - C2H_NOTIFY_EMPTY_RSVD_1_MASK}, - {"C2H_NOTIFY_EMPTY_NOE", - C2H_NOTIFY_EMPTY_NOE_MASK}, -}; - - -static struct regfield_info - c2h_stat_s_axis_c2h_accepted_1_field_info[] = { - {"C2H_STAT_S_AXIS_C2H_ACCEPTED_1", - C2H_STAT_S_AXIS_C2H_ACCEPTED_1_MASK}, -}; - - -static struct regfield_info - c2h_stat_s_axis_wrb_accepted_1_field_info[] = { - {"C2H_STAT_S_AXIS_WRB_ACCEPTED_1", - C2H_STAT_S_AXIS_WRB_ACCEPTED_1_MASK}, -}; - - -static struct regfield_info - c2h_stat_desc_rsp_pkt_accepted_1_field_info[] = { - {"C2H_STAT_DESC_RSP_PKT_ACCEPTED_1_D", - C2H_STAT_DESC_RSP_PKT_ACCEPTED_1_D_MASK}, -}; - - -static struct regfield_info - c2h_stat_axis_pkg_cmp_1_field_info[] = { - {"C2H_STAT_AXIS_PKG_CMP_1", - C2H_STAT_AXIS_PKG_CMP_1_MASK}, -}; - - -static struct regfield_info - c2h_stat_s_axis_wrb_accepted_2_field_info[] = { - {"C2H_STAT_S_AXIS_WRB_ACCEPTED_2", - C2H_STAT_S_AXIS_WRB_ACCEPTED_2_MASK}, -}; - - -static struct regfield_info - c2h_st_pld_fifo_depth_field_info[] = { - {"C2H_ST_PLD_FIFO_DEPTH", - C2H_ST_PLD_FIFO_DEPTH_MASK}, -}; - - -static struct regfield_info - c2h_stat_dbg_dma_eng_6_field_info[] = { - {"C2H_STAT_DMA_ENG_6_RSVD", - C2H_STAT_DMA_ENG_6_RSVD_MASK}, - {"C2H_STAT_DMA_ENG_6_PLD_ST_FIFO_OUT_DATA_QID", - C2H_STAT_DMA_ENG_6_PLD_ST_FIFO_OUT_DATA_QID_MASK}, - {"C2H_STAT_DMA_ENG_6_PLD_STS_FIFO_OUT_DATA_PLD_ST_PKT_ID", - C2H_STAT_DMA_ENG_6_PLD_STS_FIFO_OUT_DATA_PLD_ST_PKT_ID_MASK}, - {"C2H_STAT_DMA_ENG_6_PLD_PKT_ID_LARGER_PLD_ST", - C2H_STAT_DMA_ENG_6_PLD_PKT_ID_LARGER_PLD_ST_MASK}, -}; - - -static struct regfield_info - c2h_stat_dbg_dma_eng_7_field_info[] = { - {"C2H_STAT_DMA_ENG_7_RSVD", - C2H_STAT_DMA_ENG_7_RSVD_MASK}, - {"C2H_STAT_DMA_ENG_7_PLD_ST_FIFO_OUT_DATA_QID_1", - C2H_STAT_DMA_ENG_7_PLD_ST_FIFO_OUT_DATA_QID_1_MASK}, - {"C2H_STAT_DMA_ENG_7_PLD_STS_FIFO_OUT_DATA_PLD_ST_PKT_ID_1", - C2H_STAT_DMA_ENG_7_PLD_STS_FIFO_OUT_DATA_PLD_ST_PKT_ID_1_MASK}, - {"C2H_STAT_DMA_ENG_7_PLD_PKT_ID_LARGER_PLD_ST_1", - C2H_STAT_DMA_ENG_7_PLD_PKT_ID_LARGER_PLD_ST_1_MASK}, -}; - - -static struct regfield_info - c2h_stat_pcie_cmp_1_field_info[] = { - {"C2H_STAT_PCIE_CMP_1_DEPTH", - C2H_STAT_PCIE_CMP_1_DEPTH_MASK}, -}; - - -static struct regfield_info - c2h_pld_fifo_almost_full_field_info[] = { - {"C2H_PLD_FIFO_ALMOST_FULL_ENABLE", - C2H_PLD_FIFO_ALMOST_FULL_ENABLE_MASK}, - {"C2H_PLD_FIFO_ALMOST_FULL_TH", - C2H_PLD_FIFO_ALMOST_FULL_TH_MASK}, -}; - - -static struct regfield_info - pfch_cfg_3_field_info[] = { - {"PFCH_CFG_3_RSVD", - PFCH_CFG_3_RSVD_MASK}, - {"PFCH_CFG_3_VAR_DESC_FL_FREE_CNT_TH", - PFCH_CFG_3_VAR_DESC_FL_FREE_CNT_TH_MASK}, - {"PFCH_CFG_3_VAR_DESC_LG_PKT_CAM_CN_TH", - PFCH_CFG_3_VAR_DESC_LG_PKT_CAM_CN_TH_MASK}, -}; - - -static struct regfield_info - cmpt_cfg_0_field_info[] = { - {"CMPT_CFG_0_RSVD", - CMPT_CFG_0_RSVD_MASK}, - {"CMPT_CFG_0_VIO_SPRS_INT_AFTER_RTY", - CMPT_CFG_0_VIO_SPRS_INT_AFTER_RTY_MASK}, - {"CMPT_CFG_0_VIO_EVNT_SUP_EN", - CMPT_CFG_0_VIO_EVNT_SUP_EN_MASK}, -}; - - -static struct regfield_info - pfch_cfg_4_field_info[] = { - {"PFCH_CFG_4_GLB_EVT_TIMER_TICK", - PFCH_CFG_4_GLB_EVT_TIMER_TICK_MASK}, - {"PFCH_CFG_4_DISABLE_GLB_EVT_TIMER", - PFCH_CFG_4_DISABLE_GLB_EVT_TIMER_MASK}, - {"PFCH_CFG_4_EVT_TIMER_TICK", - PFCH_CFG_4_EVT_TIMER_TICK_MASK}, - {"PFCH_CFG_4_DISABLE_EVT_TIMER", - PFCH_CFG_4_DISABLE_EVT_TIMER_MASK}, -}; - -static struct xreg_info eqdma_config_regs[] = { -{"CFG_BLK_IDENTIFIER", 0x00, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(cfg_blk_identifier_field_info), - cfg_blk_identifier_field_info -}, -{"CFG_BLK_PCIE_MAX_PLD_SIZE", 0x08, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(cfg_blk_pcie_max_pld_size_field_info), - cfg_blk_pcie_max_pld_size_field_info -}, -{"CFG_BLK_PCIE_MAX_READ_REQ_SIZE", 0x0c, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(cfg_blk_pcie_max_read_req_size_field_info), - cfg_blk_pcie_max_read_req_size_field_info -}, -{"CFG_BLK_SYSTEM_ID", 0x10, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(cfg_blk_system_id_field_info), - cfg_blk_system_id_field_info -}, -{"CFG_BLK_MSIX_ENABLE", 0x014, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(cfg_blk_msix_enable_field_info), - cfg_blk_msix_enable_field_info -}, -{"CFG_PCIE_DATA_WIDTH", 0x18, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(cfg_pcie_data_width_field_info), - cfg_pcie_data_width_field_info -}, -{"CFG_PCIE_CTL", 0x1c, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(cfg_pcie_ctl_field_info), - cfg_pcie_ctl_field_info -}, -{"CFG_BLK_MSI_ENABLE", 0x20, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(cfg_blk_msi_enable_field_info), - cfg_blk_msi_enable_field_info -}, -{"CFG_AXI_USER_MAX_PLD_SIZE", 0x40, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(cfg_axi_user_max_pld_size_field_info), - cfg_axi_user_max_pld_size_field_info -}, -{"CFG_AXI_USER_MAX_READ_REQ_SIZE", 0x44, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(cfg_axi_user_max_read_req_size_field_info), - cfg_axi_user_max_read_req_size_field_info -}, -{"CFG_BLK_MISC_CTL", 0x4c, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(cfg_blk_misc_ctl_field_info), - cfg_blk_misc_ctl_field_info -}, -{"CFG_PL_CRED_CTL", 0x68, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(cfg_pl_cred_ctl_field_info), - cfg_pl_cred_ctl_field_info -}, -{"CFG_BLK_SCRATCH", 0x80, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(cfg_blk_scratch_field_info), - cfg_blk_scratch_field_info -}, -{"CFG_GIC", 0xa0, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(cfg_gic_field_info), - cfg_gic_field_info -}, -{"RAM_SBE_MSK_1_A", 0xe0, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(ram_sbe_msk_1_a_field_info), - ram_sbe_msk_1_a_field_info -}, -{"RAM_SBE_STS_1_A", 0xe4, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(ram_sbe_sts_1_a_field_info), - ram_sbe_sts_1_a_field_info -}, -{"RAM_DBE_MSK_1_A", 0xe8, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(ram_dbe_msk_1_a_field_info), - ram_dbe_msk_1_a_field_info -}, -{"RAM_DBE_STS_1_A", 0xec, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(ram_dbe_sts_1_a_field_info), - ram_dbe_sts_1_a_field_info -}, -{"RAM_SBE_MSK_A", 0xf0, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(ram_sbe_msk_a_field_info), - ram_sbe_msk_a_field_info -}, -{"RAM_SBE_STS_A", 0xf4, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(ram_sbe_sts_a_field_info), - ram_sbe_sts_a_field_info -}, -{"RAM_DBE_MSK_A", 0xf8, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(ram_dbe_msk_a_field_info), - ram_dbe_msk_a_field_info -}, -{"RAM_DBE_STS_A", 0xfc, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(ram_dbe_sts_a_field_info), - ram_dbe_sts_a_field_info -}, -{"GLBL2_IDENTIFIER", 0x100, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(glbl2_identifier_field_info), - glbl2_identifier_field_info -}, -{"GLBL2_CHANNEL_INST", 0x114, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(glbl2_channel_inst_field_info), - glbl2_channel_inst_field_info -}, -{"GLBL2_CHANNEL_MDMA", 0x118, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(glbl2_channel_mdma_field_info), - glbl2_channel_mdma_field_info -}, -{"GLBL2_CHANNEL_STRM", 0x11c, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(glbl2_channel_strm_field_info), - glbl2_channel_strm_field_info -}, -{"GLBL2_CHANNEL_CAP", 0x120, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(glbl2_channel_cap_field_info), - glbl2_channel_cap_field_info -}, -{"GLBL2_CHANNEL_PASID_CAP", 0x128, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(glbl2_channel_pasid_cap_field_info), - glbl2_channel_pasid_cap_field_info -}, -{"GLBL2_SYSTEM_ID", 0x130, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(glbl2_system_id_field_info), - glbl2_system_id_field_info -}, -{"GLBL2_MISC_CAP", 0x134, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(glbl2_misc_cap_field_info), - glbl2_misc_cap_field_info -}, -{"GLBL2_RRQ_BRG_THROT", 0x158, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(glbl2_rrq_brg_throt_field_info), - glbl2_rrq_brg_throt_field_info -}, -{"GLBL2_RRQ_PCIE_THROT", 0x15c, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(glbl2_rrq_pcie_throt_field_info), - glbl2_rrq_pcie_throt_field_info -}, -{"GLBL2_RRQ_AXIMM_THROT", 0x160, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(glbl2_rrq_aximm_throt_field_info), - glbl2_rrq_aximm_throt_field_info -}, -{"GLBL2_RRQ_PCIE_LAT0", 0x164, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(glbl2_rrq_pcie_lat0_field_info), - glbl2_rrq_pcie_lat0_field_info -}, -{"GLBL2_RRQ_PCIE_LAT1", 0x168, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(glbl2_rrq_pcie_lat1_field_info), - glbl2_rrq_pcie_lat1_field_info -}, -{"GLBL2_RRQ_AXIMM_LAT0", 0x16c, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(glbl2_rrq_aximm_lat0_field_info), - glbl2_rrq_aximm_lat0_field_info -}, -{"GLBL2_RRQ_AXIMM_LAT1", 0x170, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(glbl2_rrq_aximm_lat1_field_info), - glbl2_rrq_aximm_lat1_field_info -}, -{"GLBL2_DBG_PCIE_RQ0", 0x1b8, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(glbl2_dbg_pcie_rq0_field_info), - glbl2_dbg_pcie_rq0_field_info -}, -{"GLBL2_DBG_PCIE_RQ1", 0x1bc, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(glbl2_dbg_pcie_rq1_field_info), - glbl2_dbg_pcie_rq1_field_info -}, -{"GLBL2_DBG_AXIMM_WR0", 0x1c0, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(glbl2_dbg_aximm_wr0_field_info), - glbl2_dbg_aximm_wr0_field_info -}, -{"GLBL2_DBG_AXIMM_WR1", 0x1c4, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(glbl2_dbg_aximm_wr1_field_info), - glbl2_dbg_aximm_wr1_field_info -}, -{"GLBL2_DBG_AXIMM_RD0", 0x1c8, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(glbl2_dbg_aximm_rd0_field_info), - glbl2_dbg_aximm_rd0_field_info -}, -{"GLBL2_DBG_AXIMM_RD1", 0x1cc, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(glbl2_dbg_aximm_rd1_field_info), - glbl2_dbg_aximm_rd1_field_info -}, -{"GLBL2_DBG_FAB0", 0x1d0, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(glbl2_dbg_fab0_field_info), - glbl2_dbg_fab0_field_info -}, -{"GLBL2_DBG_FAB1", 0x1d4, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(glbl2_dbg_fab1_field_info), - glbl2_dbg_fab1_field_info -}, -{"GLBL2_DBG_MATCH_SEL", 0x1f4, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(glbl2_dbg_match_sel_field_info), - glbl2_dbg_match_sel_field_info -}, -{"GLBL2_DBG_MATCH_MSK", 0x1f8, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(glbl2_dbg_match_msk_field_info), - glbl2_dbg_match_msk_field_info -}, -{"GLBL2_DBG_MATCH_PAT", 0x1fc, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(glbl2_dbg_match_pat_field_info), - glbl2_dbg_match_pat_field_info -}, -{"GLBL_RNG_SZ_1", 0x204, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(glbl_rng_sz_1_field_info), - glbl_rng_sz_1_field_info -}, -{"GLBL_RNG_SZ_2", 0x208, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(glbl_rng_sz_2_field_info), - glbl_rng_sz_2_field_info -}, -{"GLBL_RNG_SZ_3", 0x20c, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(glbl_rng_sz_3_field_info), - glbl_rng_sz_3_field_info -}, -{"GLBL_RNG_SZ_4", 0x210, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(glbl_rng_sz_4_field_info), - glbl_rng_sz_4_field_info -}, -{"GLBL_RNG_SZ_5", 0x214, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(glbl_rng_sz_5_field_info), - glbl_rng_sz_5_field_info -}, -{"GLBL_RNG_SZ_6", 0x218, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(glbl_rng_sz_6_field_info), - glbl_rng_sz_6_field_info -}, -{"GLBL_RNG_SZ_7", 0x21c, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(glbl_rng_sz_7_field_info), - glbl_rng_sz_7_field_info -}, -{"GLBL_RNG_SZ_8", 0x220, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(glbl_rng_sz_8_field_info), - glbl_rng_sz_8_field_info -}, -{"GLBL_RNG_SZ_9", 0x224, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(glbl_rng_sz_9_field_info), - glbl_rng_sz_9_field_info -}, -{"GLBL_RNG_SZ_A", 0x228, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(glbl_rng_sz_a_field_info), - glbl_rng_sz_a_field_info -}, -{"GLBL_RNG_SZ_B", 0x22c, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(glbl_rng_sz_b_field_info), - glbl_rng_sz_b_field_info -}, -{"GLBL_RNG_SZ_C", 0x230, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(glbl_rng_sz_c_field_info), - glbl_rng_sz_c_field_info -}, -{"GLBL_RNG_SZ_D", 0x234, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(glbl_rng_sz_d_field_info), - glbl_rng_sz_d_field_info -}, -{"GLBL_RNG_SZ_E", 0x238, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(glbl_rng_sz_e_field_info), - glbl_rng_sz_e_field_info -}, -{"GLBL_RNG_SZ_F", 0x23c, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(glbl_rng_sz_f_field_info), - glbl_rng_sz_f_field_info -}, -{"GLBL_RNG_SZ_10", 0x240, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(glbl_rng_sz_10_field_info), - glbl_rng_sz_10_field_info -}, -{"GLBL_ERR_STAT", 0x248, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(glbl_err_stat_field_info), - glbl_err_stat_field_info -}, -{"GLBL_ERR_MASK", 0x24c, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(glbl_err_mask_field_info), - glbl_err_mask_field_info -}, -{"GLBL_DSC_CFG", 0x250, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(glbl_dsc_cfg_field_info), - glbl_dsc_cfg_field_info -}, -{"GLBL_DSC_ERR_STS", 0x254, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(glbl_dsc_err_sts_field_info), - glbl_dsc_err_sts_field_info -}, -{"GLBL_DSC_ERR_MSK", 0x258, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(glbl_dsc_err_msk_field_info), - glbl_dsc_err_msk_field_info -}, -{"GLBL_DSC_ERR_LOG0", 0x25c, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(glbl_dsc_err_log0_field_info), - glbl_dsc_err_log0_field_info -}, -{"GLBL_DSC_ERR_LOG1", 0x260, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(glbl_dsc_err_log1_field_info), - glbl_dsc_err_log1_field_info -}, -{"GLBL_TRQ_ERR_STS", 0x264, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(glbl_trq_err_sts_field_info), - glbl_trq_err_sts_field_info -}, -{"GLBL_TRQ_ERR_MSK", 0x268, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(glbl_trq_err_msk_field_info), - glbl_trq_err_msk_field_info -}, -{"GLBL_TRQ_ERR_LOG", 0x26c, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(glbl_trq_err_log_field_info), - glbl_trq_err_log_field_info -}, -{"GLBL_DSC_DBG_DAT0", 0x270, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(glbl_dsc_dbg_dat0_field_info), - glbl_dsc_dbg_dat0_field_info -}, -{"GLBL_DSC_DBG_DAT1", 0x274, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(glbl_dsc_dbg_dat1_field_info), - glbl_dsc_dbg_dat1_field_info -}, -{"GLBL_DSC_DBG_CTL", 0x278, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(glbl_dsc_dbg_ctl_field_info), - glbl_dsc_dbg_ctl_field_info -}, -{"GLBL_DSC_ERR_LOG2", 0x27c, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(glbl_dsc_err_log2_field_info), - glbl_dsc_err_log2_field_info -}, -{"GLBL_GLBL_INTERRUPT_CFG", 0x2c4, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(glbl_glbl_interrupt_cfg_field_info), - glbl_glbl_interrupt_cfg_field_info -}, -{"GLBL_VCH_HOST_PROFILE", 0x2c8, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(glbl_vch_host_profile_field_info), - glbl_vch_host_profile_field_info -}, -{"GLBL_BRIDGE_HOST_PROFILE", 0x308, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(glbl_bridge_host_profile_field_info), - glbl_bridge_host_profile_field_info -}, -{"AXIMM_IRQ_DEST_ADDR", 0x30c, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(aximm_irq_dest_addr_field_info), - aximm_irq_dest_addr_field_info -}, -{"FAB_ERR_LOG", 0x314, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(fab_err_log_field_info), - fab_err_log_field_info -}, -{"GLBL_REQ_ERR_STS", 0x318, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(glbl_req_err_sts_field_info), - glbl_req_err_sts_field_info -}, -{"GLBL_REQ_ERR_MSK", 0x31c, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(glbl_req_err_msk_field_info), - glbl_req_err_msk_field_info -}, -{"GLBL_DSC_DBG_LAT0_A", 0x320, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(glbl_dsc_dbg_lat0_a_field_info), - glbl_dsc_dbg_lat0_a_field_info -}, -{"GLBL_DSC_DBG_LAT1_A", 0x324, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(glbl_dsc_dbg_lat1_a_field_info), - glbl_dsc_dbg_lat1_a_field_info -}, -{"GLBL_DSC_CRD_CTR0_A", 0x328, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(glbl_dsc_crd_ctr0_a_field_info), - glbl_dsc_crd_ctr0_a_field_info -}, -{"GLBL_DSC_CRD_CTR1_A", 0x32c, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(glbl_dsc_crd_ctr1_a_field_info), - glbl_dsc_crd_ctr1_a_field_info -}, -{"GLBL_DSC_CRD_CTR2_A", 0x330, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(glbl_dsc_crd_ctr2_a_field_info), - glbl_dsc_crd_ctr2_a_field_info -}, -{"GLBL_DSC_CRD_CTR3_A", 0x334, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(glbl_dsc_crd_ctr3_a_field_info), - glbl_dsc_crd_ctr3_a_field_info -}, -{"GLBL_DSC_IMM_CRD_CTR0_A", 0x338, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(glbl_dsc_imm_crd_ctr0_a_field_info), - glbl_dsc_imm_crd_ctr0_a_field_info -}, -{"GLBL_DSC_IMM_CRD_CTR1_A", 0x33c, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(glbl_dsc_imm_crd_ctr1_a_field_info), - glbl_dsc_imm_crd_ctr1_a_field_info -}, -{"GLBL_DSC_IMM_CRD_CTR2_A", 0x340, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(glbl_dsc_imm_crd_ctr2_a_field_info), - glbl_dsc_imm_crd_ctr2_a_field_info -}, -{"GLBL_DSC_IMM_CRD_CTR3_A", 0x344, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(glbl_dsc_imm_crd_ctr3_a_field_info), - glbl_dsc_imm_crd_ctr3_a_field_info -}, -{"GLBL_DSC_H2C_OUT_CTR0_A", 0x348, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(glbl_dsc_h2c_out_ctr0_a_field_info), - glbl_dsc_h2c_out_ctr0_a_field_info -}, -{"GLBL_DSC_H2C_OUT_CTR1_A", 0x34c, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(glbl_dsc_h2c_out_ctr1_a_field_info), - glbl_dsc_h2c_out_ctr1_a_field_info -}, -{"GLBL_DSC_H2C_OUT_CTR2_A", 0x350, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(glbl_dsc_h2c_out_ctr2_a_field_info), - glbl_dsc_h2c_out_ctr2_a_field_info -}, -{"GLBL_DSC_H2C_OUT_CTR3_A", 0x354, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(glbl_dsc_h2c_out_ctr3_a_field_info), - glbl_dsc_h2c_out_ctr3_a_field_info -}, -{"GLBL_DSC_C2H_OUT_CTR0_A", 0x358, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(glbl_dsc_c2h_out_ctr0_a_field_info), - glbl_dsc_c2h_out_ctr0_a_field_info -}, -{"GLBL_DSC_C2H_OUT_CTR1_A", 0x35c, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(glbl_dsc_c2h_out_ctr1_a_field_info), - glbl_dsc_c2h_out_ctr1_a_field_info -}, -{"GLBL_DSC_C2H_OUT_CTR2_A", 0x360, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(glbl_dsc_c2h_out_ctr2_a_field_info), - glbl_dsc_c2h_out_ctr2_a_field_info -}, -{"GLBL_DSC_C2H_OUT_CTR3_A", 0x364, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(glbl_dsc_c2h_out_ctr3_a_field_info), - glbl_dsc_c2h_out_ctr3_a_field_info -}, -{"T", 0x368, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(t_field_info), - t_field_info -}, -{"GLBL_PERF_CNTR_CTL_A1", 0x36c, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(glbl_perf_cntr_ctl_a1_field_info), - glbl_perf_cntr_ctl_a1_field_info -}, -{"GLBL_FREE_CNT_A0", 0x370, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(glbl_free_cnt_a0_field_info), - glbl_free_cnt_a0_field_info -}, -{"GLBL_FREE_CNT_A1", 0x374, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(glbl_free_cnt_a1_field_info), - glbl_free_cnt_a1_field_info -}, -{"GLBL_AXIS_H2C_CNT_A0", 0x378, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(glbl_axis_h2c_cnt_a0_field_info), - glbl_axis_h2c_cnt_a0_field_info -}, -{"GLBL_AXIS_H2C_CNT_A1", 0x37c, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(glbl_axis_h2c_cnt_a1_field_info), - glbl_axis_h2c_cnt_a1_field_info -}, -{"GLBL_AXIS_H2C_CNT_A2", 0x380, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(glbl_axis_h2c_cnt_a2_field_info), - glbl_axis_h2c_cnt_a2_field_info -}, -{"GLBL_AXIS_H2C_CNT_A3", 0x384, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(glbl_axis_h2c_cnt_a3_field_info), - glbl_axis_h2c_cnt_a3_field_info -}, -{"GLBL_AXIS_H2C_CNT_A4", 0x388, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(glbl_axis_h2c_cnt_a4_field_info), - glbl_axis_h2c_cnt_a4_field_info -}, -{"GLBL_AXIS_H2C_CNT_A5", 0x38c, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(glbl_axis_h2c_cnt_a5_field_info), - glbl_axis_h2c_cnt_a5_field_info -}, -{"GLBL_AXIS_C2H_CNT_A0", 0x390, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(glbl_axis_c2h_cnt_a0_field_info), - glbl_axis_c2h_cnt_a0_field_info -}, -{"GLBL_AXIS_C2H_CNT_A1", 0x394, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(glbl_axis_c2h_cnt_a1_field_info), - glbl_axis_c2h_cnt_a1_field_info -}, -{"GLBL_AXIS_C2H_CNT_A2", 0x398, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(glbl_axis_c2h_cnt_a2_field_info), - glbl_axis_c2h_cnt_a2_field_info -}, -{"GLBL_AXIS_C2H_CNT_A3", 0x39c, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(glbl_axis_c2h_cnt_a3_field_info), - glbl_axis_c2h_cnt_a3_field_info -}, -{"GLBL_AXIS_C2H_CNT_A4", 0x3a0, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(glbl_axis_c2h_cnt_a4_field_info), - glbl_axis_c2h_cnt_a4_field_info -}, -{"GLBL_AXIS_C2H_CNT_A5", 0x3a4, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(glbl_axis_c2h_cnt_a5_field_info), - glbl_axis_c2h_cnt_a5_field_info -}, -{"GLBL_M_AXI_WR_CNT_A0", 0x3a8, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(glbl_m_axi_wr_cnt_a0_field_info), - glbl_m_axi_wr_cnt_a0_field_info -}, -{"GLBL_M_AXI_WR_CNT_A1", 0x3ac, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(glbl_m_axi_wr_cnt_a1_field_info), - glbl_m_axi_wr_cnt_a1_field_info -}, -{"GLBL_M_AXI_WR_CNT_A2", 0x3b0, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(glbl_m_axi_wr_cnt_a2_field_info), - glbl_m_axi_wr_cnt_a2_field_info -}, -{"GLBL_M_AXI_WR_CNT_A3", 0x3b4, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(glbl_m_axi_wr_cnt_a3_field_info), - glbl_m_axi_wr_cnt_a3_field_info -}, -{"GLBL_M_AXI_WR_CNT_A4", 0x3b8, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(glbl_m_axi_wr_cnt_a4_field_info), - glbl_m_axi_wr_cnt_a4_field_info -}, -{"GLBL_M_AXI_WR_CNT_A5", 0x3bc, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(glbl_m_axi_wr_cnt_a5_field_info), - glbl_m_axi_wr_cnt_a5_field_info -}, -{"GLBL_M_AXI_RD_CNT_A0", 0x3c0, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(glbl_m_axi_rd_cnt_a0_field_info), - glbl_m_axi_rd_cnt_a0_field_info -}, -{"GLBL_M_AXI_RD_CNT_A1", 0x3c4, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(glbl_m_axi_rd_cnt_a1_field_info), - glbl_m_axi_rd_cnt_a1_field_info -}, -{"GLBL_M_AXI_RD_CNT_A2", 0x3c8, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(glbl_m_axi_rd_cnt_a2_field_info), - glbl_m_axi_rd_cnt_a2_field_info -}, -{"GLBL_M_AXI_RD_CNT_A3", 0x3cc, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(glbl_m_axi_rd_cnt_a3_field_info), - glbl_m_axi_rd_cnt_a3_field_info -}, -{"GLBL_M_AXI_RD_CNT_A4", 0x3d0, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(glbl_m_axi_rd_cnt_a4_field_info), - glbl_m_axi_rd_cnt_a4_field_info -}, -{"GLBL_M_AXI_RD_CNT_A5", 0x3d4, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(glbl_m_axi_rd_cnt_a5_field_info), - glbl_m_axi_rd_cnt_a5_field_info -}, -{"GLBL_M_AXIB_WR_CNT_A0", 0x3d8, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(glbl_m_axib_wr_cnt_a0_field_info), - glbl_m_axib_wr_cnt_a0_field_info -}, -{"GLBL_M_AXIB_WR_CNT_A1", 0x3dc, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(glbl_m_axib_wr_cnt_a1_field_info), - glbl_m_axib_wr_cnt_a1_field_info -}, -{"GLBL_M_AXIB_WR_CNT_A2", 0x3e0, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(glbl_m_axib_wr_cnt_a2_field_info), - glbl_m_axib_wr_cnt_a2_field_info -}, -{"GLBL_M_AXIB_WR_CNT_A3", 0x3e4, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(glbl_m_axib_wr_cnt_a3_field_info), - glbl_m_axib_wr_cnt_a3_field_info -}, -{"GLBL_M_AXIB_WR_CNT_A4", 0x3e8, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(glbl_m_axib_wr_cnt_a4_field_info), - glbl_m_axib_wr_cnt_a4_field_info -}, -{"GLBL_M_AXIB_WR_CNT_A5", 0x3ec, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(glbl_m_axib_wr_cnt_a5_field_info), - glbl_m_axib_wr_cnt_a5_field_info -}, -{"GLBL_M_AXIB_RD_CNT_A0", 0x3f0, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(glbl_m_axib_rd_cnt_a0_field_info), - glbl_m_axib_rd_cnt_a0_field_info -}, -{"GLBL_M_AXIB_RD_CNT_A1", 0x3f4, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(glbl_m_axib_rd_cnt_a1_field_info), - glbl_m_axib_rd_cnt_a1_field_info -}, -{"GLBL_M_AXIB_RD_CNT_A2", 0x3f8, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(glbl_m_axib_rd_cnt_a2_field_info), - glbl_m_axib_rd_cnt_a2_field_info -}, -{"GLBL_M_AXIB_RD_CNT_A3", 0x3fc, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(glbl_m_axib_rd_cnt_a3_field_info), - glbl_m_axib_rd_cnt_a3_field_info -}, -{"GLBL_M_AXIB_RD_CNT_A4", 0x400, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(glbl_m_axib_rd_cnt_a4_field_info), - glbl_m_axib_rd_cnt_a4_field_info -}, -{"GLBL_M_AXIB_RD_CNT_A5", 0x404, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(glbl_m_axib_rd_cnt_a5_field_info), - glbl_m_axib_rd_cnt_a5_field_info -}, -{"GLBL_S_AXI_WR_CNT_A0", 0x408, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(glbl_s_axi_wr_cnt_a0_field_info), - glbl_s_axi_wr_cnt_a0_field_info -}, -{"GLBL_S_AXI_WR_CNT_A1", 0x40c, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(glbl_s_axi_wr_cnt_a1_field_info), - glbl_s_axi_wr_cnt_a1_field_info -}, -{"GLBL_S_AXI_WR_CNT_A2", 0x410, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(glbl_s_axi_wr_cnt_a2_field_info), - glbl_s_axi_wr_cnt_a2_field_info -}, -{"GLBL_S_AXI_WR_CNT_A3", 0x414, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(glbl_s_axi_wr_cnt_a3_field_info), - glbl_s_axi_wr_cnt_a3_field_info -}, -{"GLBL_S_AXI_WR_CNT_A4", 0x418, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(glbl_s_axi_wr_cnt_a4_field_info), - glbl_s_axi_wr_cnt_a4_field_info -}, -{"GLBL_S_AXI_WR_CNT_A5", 0x41c, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(glbl_s_axi_wr_cnt_a5_field_info), - glbl_s_axi_wr_cnt_a5_field_info -}, -{"GLBL_S_AXI_RD_CNT_A0", 0x420, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(glbl_s_axi_rd_cnt_a0_field_info), - glbl_s_axi_rd_cnt_a0_field_info -}, -{"GLBL_S_AXI_RD_CNT_A1", 0x424, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(glbl_s_axi_rd_cnt_a1_field_info), - glbl_s_axi_rd_cnt_a1_field_info -}, -{"GLBL_S_AXI_RD_CNT_A2", 0x428, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(glbl_s_axi_rd_cnt_a2_field_info), - glbl_s_axi_rd_cnt_a2_field_info -}, -{"GLBL_S_AXI_RD_CNT_A3", 0x42c, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(glbl_s_axi_rd_cnt_a3_field_info), - glbl_s_axi_rd_cnt_a3_field_info -}, -{"GLBL_S_AXI_RD_CNT_A4", 0x430, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(glbl_s_axi_rd_cnt_a4_field_info), - glbl_s_axi_rd_cnt_a4_field_info -}, -{"GLBL_S_AXI_RD_CNT_A5", 0x434, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(glbl_s_axi_rd_cnt_a5_field_info), - glbl_s_axi_rd_cnt_a5_field_info -}, -{"GLBL_S_AXIS_CMP_CNT_A0", 0x438, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(glbl_s_axis_cmp_cnt_a0_field_info), - glbl_s_axis_cmp_cnt_a0_field_info -}, -{"GLBL_S_AXIS_CMP_CNT_A1", 0x43c, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(glbl_s_axis_cmp_cnt_a1_field_info), - glbl_s_axis_cmp_cnt_a1_field_info -}, -{"GLBL_S_AXIS_CMP_CNT_A2", 0x440, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(glbl_s_axis_cmp_cnt_a2_field_info), - glbl_s_axis_cmp_cnt_a2_field_info -}, -{"GLBL_S_AXIS_CMP_CNT_A3", 0x444, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(glbl_s_axis_cmp_cnt_a3_field_info), - glbl_s_axis_cmp_cnt_a3_field_info -}, -{"GLBL_S_AXIS_CMP_CNT_A4", 0x448, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(glbl_s_axis_cmp_cnt_a4_field_info), - glbl_s_axis_cmp_cnt_a4_field_info -}, -{"GLBL_S_AXIS_CMP_CNT_A5", 0x44c, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(glbl_s_axis_cmp_cnt_a5_field_info), - glbl_s_axis_cmp_cnt_a5_field_info -}, -{"IND_CTXT_DATA", 0x804, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(ind_ctxt_data_field_info), - ind_ctxt_data_field_info -}, -{"IND_CTXT_MASK", 0x824, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(ind_ctxt_mask_field_info), - ind_ctxt_mask_field_info -}, -{"IND_CTXT_CMD", 0x844, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(ind_ctxt_cmd_field_info), - ind_ctxt_cmd_field_info -}, -{"C2H_TIMER_CNT", 0xa00, - 1, 0, 0, 0, - 0, QDMA_COMPLETION_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_timer_cnt_field_info), - c2h_timer_cnt_field_info -}, -{"C2H_CNT_TH", 0xa40, - 1, 0, 0, 0, - 0, QDMA_COMPLETION_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_cnt_th_field_info), - c2h_cnt_th_field_info -}, -{"C2H_PFCH_CFG_1", 0xa80, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(c2h_pfch_cfg_1_field_info), - c2h_pfch_cfg_1_field_info -}, -{"C2H_PFCH_CFG_2", 0xa84, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(c2h_pfch_cfg_2_field_info), - c2h_pfch_cfg_2_field_info -}, -{"C2H_STAT_S_AXIS_C2H_ACCEPTED", 0xa88, - 1, 0, 0, 0, - 1, QDMA_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(c2h_stat_s_axis_c2h_accepted_field_info), - c2h_stat_s_axis_c2h_accepted_field_info -}, -{"C2H_STAT_S_AXIS_WRB_ACCEPTED", 0xa8c, - 1, 0, 0, 0, - 1, QDMA_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(c2h_stat_s_axis_wrb_accepted_field_info), - c2h_stat_s_axis_wrb_accepted_field_info -}, -{"C2H_STAT_DESC_RSP_PKT_ACCEPTED", 0xa90, - 1, 0, 0, 0, - 1, QDMA_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(c2h_stat_desc_rsp_pkt_accepted_field_info), - c2h_stat_desc_rsp_pkt_accepted_field_info -}, -{"C2H_STAT_AXIS_PKG_CMP", 0xa94, - 1, 0, 0, 0, - 1, QDMA_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(c2h_stat_axis_pkg_cmp_field_info), - c2h_stat_axis_pkg_cmp_field_info -}, -{"C2H_STAT_DESC_RSP_ACCEPTED", 0xa98, - 1, 0, 0, 0, - 1, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_stat_desc_rsp_accepted_field_info), - c2h_stat_desc_rsp_accepted_field_info -}, -{"C2H_STAT_DESC_RSP_CMP", 0xa9c, - 1, 0, 0, 0, - 1, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_stat_desc_rsp_cmp_field_info), - c2h_stat_desc_rsp_cmp_field_info -}, -{"C2H_STAT_WRQ_OUT", 0xaa0, - 1, 0, 0, 0, - 1, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_stat_wrq_out_field_info), - c2h_stat_wrq_out_field_info -}, -{"C2H_STAT_WPL_REN_ACCEPTED", 0xaa4, - 1, 0, 0, 0, - 1, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_stat_wpl_ren_accepted_field_info), - c2h_stat_wpl_ren_accepted_field_info -}, -{"C2H_STAT_TOTAL_WRQ_LEN", 0xaa8, - 1, 0, 0, 0, - 1, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_stat_total_wrq_len_field_info), - c2h_stat_total_wrq_len_field_info -}, -{"C2H_STAT_TOTAL_WPL_LEN", 0xaac, - 1, 0, 0, 0, - 1, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_stat_total_wpl_len_field_info), - c2h_stat_total_wpl_len_field_info -}, -{"C2H_BUF_SZ", 0xab0, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_buf_sz_field_info), - c2h_buf_sz_field_info -}, -{"C2H_ERR_STAT", 0xaf0, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(c2h_err_stat_field_info), - c2h_err_stat_field_info -}, -{"C2H_ERR_MASK", 0xaf4, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(c2h_err_mask_field_info), - c2h_err_mask_field_info -}, -{"C2H_FATAL_ERR_STAT", 0xaf8, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(c2h_fatal_err_stat_field_info), - c2h_fatal_err_stat_field_info -}, -{"C2H_FATAL_ERR_MASK", 0xafc, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(c2h_fatal_err_mask_field_info), - c2h_fatal_err_mask_field_info -}, -{"C2H_FATAL_ERR_ENABLE", 0xb00, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(c2h_fatal_err_enable_field_info), - c2h_fatal_err_enable_field_info -}, -{"GLBL_ERR_INT", 0xb04, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(glbl_err_int_field_info), - glbl_err_int_field_info -}, -{"C2H_PFCH_CFG", 0xb08, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_pfch_cfg_field_info), - c2h_pfch_cfg_field_info -}, -{"C2H_INT_TIMER_TICK", 0xb0c, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_int_timer_tick_field_info), - c2h_int_timer_tick_field_info -}, -{"C2H_STAT_DESC_RSP_DROP_ACCEPTED", 0xb10, - 1, 0, 0, 0, - 1, QDMA_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(c2h_stat_desc_rsp_drop_accepted_field_info), - c2h_stat_desc_rsp_drop_accepted_field_info -}, -{"C2H_STAT_DESC_RSP_ERR_ACCEPTED", 0xb14, - 1, 0, 0, 0, - 1, QDMA_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(c2h_stat_desc_rsp_err_accepted_field_info), - c2h_stat_desc_rsp_err_accepted_field_info -}, -{"C2H_STAT_DESC_REQ", 0xb18, - 1, 0, 0, 0, - 1, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_stat_desc_req_field_info), - c2h_stat_desc_req_field_info -}, -{"C2H_STAT_DBG_DMA_ENG_0", 0xb1c, - 1, 0, 0, 0, - 1, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_stat_dbg_dma_eng_0_field_info), - c2h_stat_dbg_dma_eng_0_field_info -}, -{"C2H_STAT_DBG_DMA_ENG_1", 0xb20, - 1, 0, 0, 0, - 1, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_stat_dbg_dma_eng_1_field_info), - c2h_stat_dbg_dma_eng_1_field_info -}, -{"C2H_STAT_DBG_DMA_ENG_2", 0xb24, - 1, 0, 0, 0, - 1, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_stat_dbg_dma_eng_2_field_info), - c2h_stat_dbg_dma_eng_2_field_info -}, -{"C2H_STAT_DBG_DMA_ENG_3", 0xb28, - 1, 0, 0, 0, - 1, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_stat_dbg_dma_eng_3_field_info), - c2h_stat_dbg_dma_eng_3_field_info -}, -{"C2H_DBG_PFCH_ERR_CTXT", 0xb2c, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_dbg_pfch_err_ctxt_field_info), - c2h_dbg_pfch_err_ctxt_field_info -}, -{"C2H_FIRST_ERR_QID", 0xb30, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(c2h_first_err_qid_field_info), - c2h_first_err_qid_field_info -}, -{"STAT_NUM_WRB_IN", 0xb34, - 1, 0, 0, 0, - 1, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(stat_num_wrb_in_field_info), - stat_num_wrb_in_field_info -}, -{"STAT_NUM_WRB_OUT", 0xb38, - 1, 0, 0, 0, - 1, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(stat_num_wrb_out_field_info), - stat_num_wrb_out_field_info -}, -{"STAT_NUM_WRB_DRP", 0xb3c, - 1, 0, 0, 0, - 1, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(stat_num_wrb_drp_field_info), - stat_num_wrb_drp_field_info -}, -{"STAT_NUM_STAT_DESC_OUT", 0xb40, - 1, 0, 0, 0, - 1, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(stat_num_stat_desc_out_field_info), - stat_num_stat_desc_out_field_info -}, -{"STAT_NUM_DSC_CRDT_SENT", 0xb44, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(stat_num_dsc_crdt_sent_field_info), - stat_num_dsc_crdt_sent_field_info -}, -{"STAT_NUM_FCH_DSC_RCVD", 0xb48, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(stat_num_fch_dsc_rcvd_field_info), - stat_num_fch_dsc_rcvd_field_info -}, -{"STAT_NUM_BYP_DSC_RCVD", 0xb4c, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(stat_num_byp_dsc_rcvd_field_info), - stat_num_byp_dsc_rcvd_field_info -}, -{"C2H_WRB_COAL_CFG", 0xb50, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_wrb_coal_cfg_field_info), - c2h_wrb_coal_cfg_field_info -}, -{"C2H_INTR_H2C_REQ", 0xb54, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(c2h_intr_h2c_req_field_info), - c2h_intr_h2c_req_field_info -}, -{"C2H_INTR_C2H_MM_REQ", 0xb58, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(c2h_intr_c2h_mm_req_field_info), - c2h_intr_c2h_mm_req_field_info -}, -{"C2H_INTR_ERR_INT_REQ", 0xb5c, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(c2h_intr_err_int_req_field_info), - c2h_intr_err_int_req_field_info -}, -{"C2H_INTR_C2H_ST_REQ", 0xb60, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(c2h_intr_c2h_st_req_field_info), - c2h_intr_c2h_st_req_field_info -}, -{"C2H_INTR_H2C_ERR_C2H_MM_MSIX_ACK", 0xb64, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_intr_h2c_err_c2h_mm_msix_ack_field_info), - c2h_intr_h2c_err_c2h_mm_msix_ack_field_info -}, -{"C2H_INTR_H2C_ERR_C2H_MM_MSIX_FAIL", 0xb68, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_intr_h2c_err_c2h_mm_msix_fail_field_info), - c2h_intr_h2c_err_c2h_mm_msix_fail_field_info -}, -{"C2H_INTR_H2C_ERR_C2H_MM_MSIX_NO_MSIX", 0xb6c, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_intr_h2c_err_c2h_mm_msix_no_msix_field_info), - c2h_intr_h2c_err_c2h_mm_msix_no_msix_field_info -}, -{"C2H_INTR_H2C_ERR_C2H_MM_CTXT_INVAL", 0xb70, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_intr_h2c_err_c2h_mm_ctxt_inval_field_info), - c2h_intr_h2c_err_c2h_mm_ctxt_inval_field_info -}, -{"C2H_INTR_C2H_ST_MSIX_ACK", 0xb74, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(c2h_intr_c2h_st_msix_ack_field_info), - c2h_intr_c2h_st_msix_ack_field_info -}, -{"C2H_INTR_C2H_ST_MSIX_FAIL", 0xb78, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(c2h_intr_c2h_st_msix_fail_field_info), - c2h_intr_c2h_st_msix_fail_field_info -}, -{"C2H_INTR_C2H_ST_NO_MSIX", 0xb7c, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_intr_c2h_st_no_msix_field_info), - c2h_intr_c2h_st_no_msix_field_info -}, -{"C2H_INTR_C2H_ST_CTXT_INVAL", 0xb80, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_intr_c2h_st_ctxt_inval_field_info), - c2h_intr_c2h_st_ctxt_inval_field_info -}, -{"C2H_STAT_WR_CMP", 0xb84, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_stat_wr_cmp_field_info), - c2h_stat_wr_cmp_field_info -}, -{"C2H_STAT_DBG_DMA_ENG_4", 0xb88, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_stat_dbg_dma_eng_4_field_info), - c2h_stat_dbg_dma_eng_4_field_info -}, -{"C2H_STAT_DBG_DMA_ENG_5", 0xb8c, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_stat_dbg_dma_eng_5_field_info), - c2h_stat_dbg_dma_eng_5_field_info -}, -{"C2H_DBG_PFCH_QID", 0xb90, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_dbg_pfch_qid_field_info), - c2h_dbg_pfch_qid_field_info -}, -{"C2H_DBG_PFCH", 0xb94, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_dbg_pfch_field_info), - c2h_dbg_pfch_field_info -}, -{"C2H_INT_DBG", 0xb98, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_int_dbg_field_info), - c2h_int_dbg_field_info -}, -{"C2H_STAT_IMM_ACCEPTED", 0xb9c, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_stat_imm_accepted_field_info), - c2h_stat_imm_accepted_field_info -}, -{"C2H_STAT_MARKER_ACCEPTED", 0xba0, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_stat_marker_accepted_field_info), - c2h_stat_marker_accepted_field_info -}, -{"C2H_STAT_DISABLE_CMP_ACCEPTED", 0xba4, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_stat_disable_cmp_accepted_field_info), - c2h_stat_disable_cmp_accepted_field_info -}, -{"C2H_PLD_FIFO_CRDT_CNT", 0xba8, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_pld_fifo_crdt_cnt_field_info), - c2h_pld_fifo_crdt_cnt_field_info -}, -{"C2H_INTR_DYN_REQ", 0xbac, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_intr_dyn_req_field_info), - c2h_intr_dyn_req_field_info -}, -{"C2H_INTR_DYN_MISC", 0xbb0, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_intr_dyn_misc_field_info), - c2h_intr_dyn_misc_field_info -}, -{"C2H_DROP_LEN_MISMATCH", 0xbb4, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_drop_len_mismatch_field_info), - c2h_drop_len_mismatch_field_info -}, -{"C2H_DROP_DESC_RSP_LEN", 0xbb8, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_drop_desc_rsp_len_field_info), - c2h_drop_desc_rsp_len_field_info -}, -{"C2H_DROP_QID_FIFO_LEN", 0xbbc, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_drop_qid_fifo_len_field_info), - c2h_drop_qid_fifo_len_field_info -}, -{"C2H_DROP_PLD_CNT", 0xbc0, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_drop_pld_cnt_field_info), - c2h_drop_pld_cnt_field_info -}, -{"C2H_CMPT_FORMAT_0", 0xbc4, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_cmpt_format_0_field_info), - c2h_cmpt_format_0_field_info -}, -{"C2H_CMPT_FORMAT_1", 0xbc8, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_cmpt_format_1_field_info), - c2h_cmpt_format_1_field_info -}, -{"C2H_CMPT_FORMAT_2", 0xbcc, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_cmpt_format_2_field_info), - c2h_cmpt_format_2_field_info -}, -{"C2H_CMPT_FORMAT_3", 0xbd0, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_cmpt_format_3_field_info), - c2h_cmpt_format_3_field_info -}, -{"C2H_CMPT_FORMAT_4", 0xbd4, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_cmpt_format_4_field_info), - c2h_cmpt_format_4_field_info -}, -{"C2H_CMPT_FORMAT_5", 0xbd8, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_cmpt_format_5_field_info), - c2h_cmpt_format_5_field_info -}, -{"C2H_CMPT_FORMAT_6", 0xbdc, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_cmpt_format_6_field_info), - c2h_cmpt_format_6_field_info -}, -{"C2H_PFCH_CACHE_DEPTH", 0xbe0, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_pfch_cache_depth_field_info), - c2h_pfch_cache_depth_field_info -}, -{"C2H_WRB_COAL_BUF_DEPTH", 0xbe4, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_wrb_coal_buf_depth_field_info), - c2h_wrb_coal_buf_depth_field_info -}, -{"C2H_PFCH_CRDT", 0xbe8, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_pfch_crdt_field_info), - c2h_pfch_crdt_field_info -}, -{"C2H_STAT_HAS_CMPT_ACCEPTED", 0xbec, - 1, 0, 0, 0, - 1, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_stat_has_cmpt_accepted_field_info), - c2h_stat_has_cmpt_accepted_field_info -}, -{"C2H_STAT_HAS_PLD_ACCEPTED", 0xbf0, - 1, 0, 0, 0, - 1, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_stat_has_pld_accepted_field_info), - c2h_stat_has_pld_accepted_field_info -}, -{"C2H_PLD_PKT_ID", 0xbf4, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_pld_pkt_id_field_info), - c2h_pld_pkt_id_field_info -}, -{"C2H_PLD_PKT_ID_1", 0xbf8, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_pld_pkt_id_1_field_info), - c2h_pld_pkt_id_1_field_info -}, -{"C2H_DROP_PLD_CNT_1", 0xbfc, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_drop_pld_cnt_1_field_info), - c2h_drop_pld_cnt_1_field_info -}, -{"H2C_ERR_STAT", 0xe00, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(h2c_err_stat_field_info), - h2c_err_stat_field_info -}, -{"H2C_ERR_MASK", 0xe04, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(h2c_err_mask_field_info), - h2c_err_mask_field_info -}, -{"H2C_FIRST_ERR_QID", 0xe08, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(h2c_first_err_qid_field_info), - h2c_first_err_qid_field_info -}, -{"H2C_DBG_REG0", 0xe0c, - 1, 0, 0, 0, - 1, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(h2c_dbg_reg0_field_info), - h2c_dbg_reg0_field_info -}, -{"H2C_DBG_REG1", 0xe10, - 1, 0, 0, 0, - 1, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(h2c_dbg_reg1_field_info), - h2c_dbg_reg1_field_info -}, -{"H2C_DBG_REG2", 0xe14, - 1, 0, 0, 0, - 1, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(h2c_dbg_reg2_field_info), - h2c_dbg_reg2_field_info -}, -{"H2C_DBG_REG3", 0xe18, - 1, 0, 0, 0, - 1, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(h2c_dbg_reg3_field_info), - h2c_dbg_reg3_field_info -}, -{"H2C_DBG_REG4", 0xe1c, - 1, 0, 0, 0, - 1, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(h2c_dbg_reg4_field_info), - h2c_dbg_reg4_field_info -}, -{"H2C_FATAL_ERR_EN", 0xe20, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(h2c_fatal_err_en_field_info), - h2c_fatal_err_en_field_info -}, -{"H2C_REQ_THROT_PCIE", 0xe24, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(h2c_req_throt_pcie_field_info), - h2c_req_throt_pcie_field_info -}, -{"H2C_ALN_DBG_REG0", 0xe28, - 1, 0, 0, 0, - 1, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(h2c_aln_dbg_reg0_field_info), - h2c_aln_dbg_reg0_field_info -}, -{"H2C_REQ_THROT_AXIMM", 0xe2c, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(h2c_req_throt_aximm_field_info), - h2c_req_throt_aximm_field_info -}, -{"C2H_MM_CTL", 0x1004, - 1, 0, 0, 0, - 0, QDMA_MM_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_mm_ctl_field_info), - c2h_mm_ctl_field_info -}, -{"C2H_MM_STATUS", 0x1040, - 1, 0, 0, 0, - 0, QDMA_MM_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_mm_status_field_info), - c2h_mm_status_field_info -}, -{"C2H_MM_CMPL_DESC_CNT", 0x1048, - 1, 0, 0, 0, - 0, QDMA_MM_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_mm_cmpl_desc_cnt_field_info), - c2h_mm_cmpl_desc_cnt_field_info -}, -{"C2H_MM_ERR_CODE_ENABLE_MASK", 0x1054, - 1, 0, 0, 0, - 0, QDMA_MM_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_mm_err_code_enable_mask_field_info), - c2h_mm_err_code_enable_mask_field_info -}, -{"C2H_MM_ERR_CODE", 0x1058, - 1, 0, 0, 0, - 0, QDMA_MM_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_mm_err_code_field_info), - c2h_mm_err_code_field_info -}, -{"C2H_MM_ERR_INFO", 0x105c, - 1, 0, 0, 0, - 0, QDMA_MM_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_mm_err_info_field_info), - c2h_mm_err_info_field_info -}, -{"C2H_MM_PERF_MON_CTL", 0x10c0, - 1, 0, 0, 0, - 0, QDMA_MM_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_mm_perf_mon_ctl_field_info), - c2h_mm_perf_mon_ctl_field_info -}, -{"C2H_MM_PERF_MON_CYCLE_CNT0", 0x10c4, - 1, 0, 0, 0, - 0, QDMA_MM_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_mm_perf_mon_cycle_cnt0_field_info), - c2h_mm_perf_mon_cycle_cnt0_field_info -}, -{"C2H_MM_PERF_MON_CYCLE_CNT1", 0x10c8, - 1, 0, 0, 0, - 0, QDMA_MM_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_mm_perf_mon_cycle_cnt1_field_info), - c2h_mm_perf_mon_cycle_cnt1_field_info -}, -{"C2H_MM_PERF_MON_DATA_CNT0", 0x10cc, - 1, 0, 0, 0, - 0, QDMA_MM_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_mm_perf_mon_data_cnt0_field_info), - c2h_mm_perf_mon_data_cnt0_field_info -}, -{"C2H_MM_PERF_MON_DATA_CNT1", 0x10d0, - 1, 0, 0, 0, - 0, QDMA_MM_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_mm_perf_mon_data_cnt1_field_info), - c2h_mm_perf_mon_data_cnt1_field_info -}, -{"C2H_MM_DBG", 0x10e8, - 1, 0, 0, 0, - 0, QDMA_MM_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_mm_dbg_field_info), - c2h_mm_dbg_field_info -}, -{"H2C_MM_CTL", 0x1204, - 1, 0, 0, 0, - 0, QDMA_MM_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(h2c_mm_ctl_field_info), - h2c_mm_ctl_field_info -}, -{"H2C_MM_STATUS", 0x1240, - 1, 0, 0, 0, - 0, QDMA_MM_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(h2c_mm_status_field_info), - h2c_mm_status_field_info -}, -{"H2C_MM_CMPL_DESC_CNT", 0x1248, - 1, 0, 0, 0, - 0, QDMA_MM_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(h2c_mm_cmpl_desc_cnt_field_info), - h2c_mm_cmpl_desc_cnt_field_info -}, -{"H2C_MM_ERR_CODE_ENABLE_MASK", 0x1254, - 1, 0, 0, 0, - 0, QDMA_MM_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(h2c_mm_err_code_enable_mask_field_info), - h2c_mm_err_code_enable_mask_field_info -}, -{"H2C_MM_ERR_CODE", 0x1258, - 1, 0, 0, 0, - 0, QDMA_MM_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(h2c_mm_err_code_field_info), - h2c_mm_err_code_field_info -}, -{"H2C_MM_ERR_INFO", 0x125c, - 1, 0, 0, 0, - 0, QDMA_MM_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(h2c_mm_err_info_field_info), - h2c_mm_err_info_field_info -}, -{"H2C_MM_PERF_MON_CTL", 0x12c0, - 1, 0, 0, 0, - 0, QDMA_MM_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(h2c_mm_perf_mon_ctl_field_info), - h2c_mm_perf_mon_ctl_field_info -}, -{"H2C_MM_PERF_MON_CYCLE_CNT0", 0x12c4, - 1, 0, 0, 0, - 0, QDMA_MM_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(h2c_mm_perf_mon_cycle_cnt0_field_info), - h2c_mm_perf_mon_cycle_cnt0_field_info -}, -{"H2C_MM_PERF_MON_CYCLE_CNT1", 0x12c8, - 1, 0, 0, 0, - 0, QDMA_MM_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(h2c_mm_perf_mon_cycle_cnt1_field_info), - h2c_mm_perf_mon_cycle_cnt1_field_info -}, -{"H2C_MM_PERF_MON_DATA_CNT0", 0x12cc, - 1, 0, 0, 0, - 0, QDMA_MM_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(h2c_mm_perf_mon_data_cnt0_field_info), - h2c_mm_perf_mon_data_cnt0_field_info -}, -{"H2C_MM_PERF_MON_DATA_CNT1", 0x12d0, - 1, 0, 0, 0, - 0, QDMA_MM_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(h2c_mm_perf_mon_data_cnt1_field_info), - h2c_mm_perf_mon_data_cnt1_field_info -}, -{"H2C_MM_DBG", 0x12e8, - 1, 0, 0, 0, - 0, QDMA_MM_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(h2c_mm_dbg_field_info), - h2c_mm_dbg_field_info -}, -{"H2C_MM_DATA_THROTTLE", 0x12ec, - 1, 0, 0, 0, - 0, QDMA_MM_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(h2c_mm_data_throttle_field_info), - h2c_mm_data_throttle_field_info -}, -{"C2H_CRDT_COAL_CFG_1", 0x1400, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_crdt_coal_cfg_1_field_info), - c2h_crdt_coal_cfg_1_field_info -}, -{"C2H_CRDT_COAL_CFG_2", 0x1404, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_crdt_coal_cfg_2_field_info), - c2h_crdt_coal_cfg_2_field_info -}, -{"C2H_PFCH_BYP_QID", 0x1408, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_pfch_byp_qid_field_info), - c2h_pfch_byp_qid_field_info -}, -{"C2H_PFCH_BYP_TAG", 0x140c, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_pfch_byp_tag_field_info), - c2h_pfch_byp_tag_field_info -}, -{"C2H_WATER_MARK", 0x1410, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_water_mark_field_info), - c2h_water_mark_field_info -}, -{"C2H_NOTIFY_EMPTY", 0x1450, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_notify_empty_field_info), - c2h_notify_empty_field_info -}, -{"C2H_STAT_S_AXIS_C2H_ACCEPTED_1", 0x1454, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_stat_s_axis_c2h_accepted_1_field_info), - c2h_stat_s_axis_c2h_accepted_1_field_info -}, -{"C2H_STAT_S_AXIS_WRB_ACCEPTED_1", 0x1458, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_stat_s_axis_wrb_accepted_1_field_info), - c2h_stat_s_axis_wrb_accepted_1_field_info -}, -{"C2H_STAT_DESC_RSP_PKT_ACCEPTED_1", 0x145c, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_stat_desc_rsp_pkt_accepted_1_field_info), - c2h_stat_desc_rsp_pkt_accepted_1_field_info -}, -{"C2H_STAT_AXIS_PKG_CMP_1", 0x1460, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_stat_axis_pkg_cmp_1_field_info), - c2h_stat_axis_pkg_cmp_1_field_info -}, -{"C2H_STAT_S_AXIS_WRB_ACCEPTED_2", 0x1464, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_stat_s_axis_wrb_accepted_2_field_info), - c2h_stat_s_axis_wrb_accepted_2_field_info -}, -{"C2H_ST_PLD_FIFO_DEPTH", 0x1468, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_st_pld_fifo_depth_field_info), - c2h_st_pld_fifo_depth_field_info -}, -{"C2H_STAT_DBG_DMA_ENG_6", 0x146c, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_stat_dbg_dma_eng_6_field_info), - c2h_stat_dbg_dma_eng_6_field_info -}, -{"C2H_STAT_DBG_DMA_ENG_7", 0x1470, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_stat_dbg_dma_eng_7_field_info), - c2h_stat_dbg_dma_eng_7_field_info -}, -{"C2H_STAT_PCIE_CMP_1", 0x1474, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_stat_pcie_cmp_1_field_info), - c2h_stat_pcie_cmp_1_field_info -}, -{"C2H_PLD_FIFO_ALMOST_FULL", 0x1478, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_pld_fifo_almost_full_field_info), - c2h_pld_fifo_almost_full_field_info -}, -{"PFCH_CFG_3", 0x147c, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(pfch_cfg_3_field_info), - pfch_cfg_3_field_info -}, -{"CMPT_CFG_0", 0x1480, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(cmpt_cfg_0_field_info), - cmpt_cfg_0_field_info -}, -{"PFCH_CFG_4", 0x1484, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(pfch_cfg_4_field_info), - pfch_cfg_4_field_info -}, - -}; - -uint32_t eqdma_config_num_regs_get(void) -{ - return (sizeof(eqdma_config_regs)/ - sizeof(eqdma_config_regs[0])); -} - -struct xreg_info *eqdma_config_regs_get(void) -{ - return eqdma_config_regs; -} - diff --git a/QDMA/DPDK/drivers/net/qdma/qdma_access/qdma_access_common.c b/QDMA/DPDK/drivers/net/qdma/qdma_access/qdma_access_common.c deleted file mode 100755 index 84a952618..000000000 --- a/QDMA/DPDK/drivers/net/qdma/qdma_access/qdma_access_common.c +++ /dev/null @@ -1,1530 +0,0 @@ -/* - * Copyright (c) 2019-2022, Xilinx, Inc. All rights reserved. - * Copyright (c) 2022, Advanced Micro Devices, Inc. All rights reserved. - * - * BSD LICENSE - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * * Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include "qdma_access_common.h" -#include "qdma_platform.h" -#include "qdma_soft_reg.h" -#include "qdma_soft_access.h" -#include "qdma_cpm4_access/qdma_cpm4_access.h" -#include "eqdma_soft_access.h" -#include "eqdma_cpm5_access/eqdma_cpm5_access.h" -#include "qdma_reg_dump.h" - -#ifdef ENABLE_WPP_TRACING -#include "qdma_access_common.tmh" -#endif - -/* qdma version info */ -#define RTL_BASE_VERSION 2 -#define RTL_PATCH_VERSION 3 - -/** - * enum qdma_ip - To hold ip type - */ -enum qdma_ip { - QDMA_OR_VERSAL_IP, - EQDMA_IP, - EQDMA_CPM5_IP -}; - - -/* - * hw_monitor_reg() - polling a register repeatly until - * (the register value & mask) == val or time is up - * - * return -QDMA_BUSY_IIMEOUT_ERR if register value didn't match, 0 other wise - */ -int hw_monitor_reg(void *dev_hndl, uint32_t reg, uint32_t mask, - uint32_t val, uint32_t interval_us, uint32_t timeout_us) -{ - int count; - uint32_t v; - - if (!interval_us) - interval_us = QDMA_REG_POLL_DFLT_INTERVAL_US; - if (!timeout_us) - timeout_us = QDMA_REG_POLL_DFLT_TIMEOUT_US; - - count = timeout_us / interval_us; - - do { - v = qdma_reg_read(dev_hndl, reg); - if ((v & mask) == val) - return QDMA_SUCCESS; - qdma_udelay(interval_us); - } while (--count); - - v = qdma_reg_read(dev_hndl, reg); - if ((v & mask) == val) - return QDMA_SUCCESS; - - qdma_log_error("%s: Reg read=%u Expected=%u, err:%d\n", - __func__, v, val, - -QDMA_ERR_HWACC_BUSY_TIMEOUT); - return -QDMA_ERR_HWACC_BUSY_TIMEOUT; -} - -/*****************************************************************************/ -/** - * qdma_get_rtl_version() - Function to get the rtl_version in - * string format - * - * @rtl_version: Vivado release ID - * - * Return: string - success and NULL on failure - *****************************************************************************/ -static const char *qdma_get_rtl_version(enum qdma_rtl_version rtl_version) -{ - switch (rtl_version) { - case QDMA_RTL_PATCH: - return "RTL Patch"; - case QDMA_RTL_BASE: - return "RTL Base"; - default: - qdma_log_error("%s: invalid rtl_version(%d), err:%d\n", - __func__, rtl_version, -QDMA_ERR_INV_PARAM); - return NULL; - } -} - -/*****************************************************************************/ -/** - * qdma_get_ip_type() - Function to get the ip type in string format - * - * @dev_hndl: device handle - * @is_vf: Whether PF or VF - * @ip_type: IP Type - * - * Return: string - success and NULL on failure - *****************************************************************************/ -static const char *qdma_get_ip_type(void *dev_hndl, uint8_t is_vf, - enum qdma_ip_type ip_type) -{ - uint32_t ip_version; - int rv = QDMA_SUCCESS; - - if (!dev_hndl) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - return NULL; - } - - switch (ip_type) { - case QDMA_VERSAL_HARD_IP: - return "Versal Hard IP"; - case QDMA_VERSAL_SOFT_IP: - return "Versal Soft IP"; - case QDMA_SOFT_IP: - return "QDMA Soft IP"; - case EQDMA_SOFT_IP: - rv = eqdma_get_ip_version(dev_hndl, is_vf, &ip_version); - if (rv != QDMA_SUCCESS) - return NULL; - - if (ip_version == EQDMA_IP_VERSION_4) - return "EQDMA4.0 Soft IP"; - else if (ip_version == EQDMA_IP_VERSION_5) - return "EQDMA5.0 Soft IP"; - - qdma_log_error("%s: invalid eqdma ip version(%d), err:%d\n", - __func__, ip_version, -QDMA_ERR_INV_PARAM); - return NULL; - default: - qdma_log_error("%s: invalid ip type(%d), err:%d\n", - __func__, ip_type, -QDMA_ERR_INV_PARAM); - return NULL; - } -} - -/*****************************************************************************/ -/** - * qdma_get_device_type() - Function to get the device type in - * string format - * - * @device_type: Device Type - * - * Return: string - success and NULL on failure - *****************************************************************************/ -static const char *qdma_get_device_type(enum qdma_device_type device_type) -{ - switch (device_type) { - case QDMA_DEVICE_SOFT: - return "Soft IP"; - case QDMA_DEVICE_VERSAL_CPM4: - return "Versal CPM4 Hard IP"; - case QDMA_DEVICE_VERSAL_CPM5: - return "Versal Hard CPM5"; - default: - qdma_log_error("%s: invalid device type(%d), err:%d\n", - __func__, device_type, -QDMA_ERR_INV_PARAM); - return NULL; - } -} - -/*****************************************************************************/ -/** - * qdma_get_vivado_release_id() - Function to get the vivado release id in - * string format - * - * @vivado_release_id: Vivado release ID - * - * Return: string - success and NULL on failure - *****************************************************************************/ -static const char *qdma_get_vivado_release_id( - enum qdma_vivado_release_id vivado_release_id) -{ - switch (vivado_release_id) { - case QDMA_VIVADO_2018_3: - return "vivado 2018.3"; - case QDMA_VIVADO_2019_1: - return "vivado 2019.1"; - case QDMA_VIVADO_2019_2: - return "vivado 2019.2"; - case QDMA_VIVADO_2020_1: - return "vivado 2020.1"; - case QDMA_VIVADO_2020_2: - return "vivado 2020.2"; - case QDMA_VIVADO_2021_1: - return "vivado 2021.1"; - case QDMA_VIVADO_2022_1: - return "vivado 2022.1"; - default: - qdma_log_error("%s: invalid vivado_release_id(%d), err:%d\n", - __func__, - vivado_release_id, - -QDMA_ERR_INV_PARAM); - return NULL; - } -} - - -void qdma_write_csr_values(void *dev_hndl, uint32_t reg_offst, - uint32_t idx, uint32_t cnt, const uint32_t *values) -{ - uint32_t index, reg_addr; - - for (index = idx; index < (idx + cnt); index++) { - reg_addr = reg_offst + (index * sizeof(uint32_t)); - qdma_reg_write(dev_hndl, reg_addr, values[index - idx]); - } -} - -void qdma_read_csr_values(void *dev_hndl, uint32_t reg_offst, - uint32_t idx, uint32_t cnt, uint32_t *values) -{ - uint32_t index, reg_addr; - - reg_addr = reg_offst + (idx * sizeof(uint32_t)); - for (index = 0; index < cnt; index++) { - values[index] = qdma_reg_read(dev_hndl, reg_addr + - (index * sizeof(uint32_t))); - } -} - -void qdma_fetch_version_details(void *dev_hndl, uint8_t is_vf, - uint32_t version_reg_val, struct qdma_hw_version_info *version_info) -{ - uint32_t rtl_version, vivado_release_id, ip_type, device_type; - const char *version_str; - - if (!dev_hndl) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - return; - } - - if (!is_vf) { - rtl_version = FIELD_GET(QDMA_GLBL2_RTL_VERSION_MASK, - version_reg_val); - vivado_release_id = - FIELD_GET(QDMA_GLBL2_VIVADO_RELEASE_MASK, - version_reg_val); - device_type = FIELD_GET(QDMA_GLBL2_DEVICE_ID_MASK, - version_reg_val); - ip_type = FIELD_GET(QDMA_GLBL2_VERSAL_IP_MASK, - version_reg_val); - } else { - rtl_version = - FIELD_GET(QDMA_GLBL2_VF_RTL_VERSION_MASK, - version_reg_val); - vivado_release_id = - FIELD_GET(QDMA_GLBL2_VF_VIVADO_RELEASE_MASK, - version_reg_val); - device_type = FIELD_GET(QDMA_GLBL2_VF_DEVICE_ID_MASK, - version_reg_val); - ip_type = - FIELD_GET(QDMA_GLBL2_VF_VERSAL_IP_MASK, - version_reg_val); - } - - switch (rtl_version) { - case 0: - version_info->rtl_version = QDMA_RTL_BASE; - break; - case 1: - version_info->rtl_version = QDMA_RTL_PATCH; - break; - default: - version_info->rtl_version = QDMA_RTL_NONE; - break; - } - - version_str = qdma_get_rtl_version(version_info->rtl_version); - if (version_str != NULL) - qdma_strncpy(version_info->qdma_rtl_version_str, - version_str, - QDMA_HW_VERSION_STRING_LEN); - - switch (device_type) { - case 0: - version_info->device_type = QDMA_DEVICE_SOFT; - break; - case 1: - version_info->device_type = QDMA_DEVICE_VERSAL_CPM4; - break; - case 2: - version_info->device_type = QDMA_DEVICE_VERSAL_CPM5; - break; - default: - version_info->device_type = QDMA_DEVICE_NONE; - break; - } - - version_str = qdma_get_device_type(version_info->device_type); - if (version_str != NULL) - qdma_strncpy(version_info->qdma_device_type_str, - version_str, - QDMA_HW_VERSION_STRING_LEN); - - - if (version_info->device_type == QDMA_DEVICE_SOFT) { - switch (ip_type) { - case 0: - version_info->ip_type = QDMA_SOFT_IP; - break; - case 1: - case 2: - /* For QDMA4.0 and QDMA5.0, HW design and - * register map is same except some - * performance optimizations - */ - version_info->ip_type = EQDMA_SOFT_IP; - break; - default: - version_info->ip_type = QDMA_NONE_IP; - } - } else { - switch (ip_type) { - case 0: - version_info->ip_type = QDMA_VERSAL_HARD_IP; - break; - case 1: - version_info->ip_type = QDMA_VERSAL_SOFT_IP; - break; - default: - version_info->ip_type = QDMA_NONE_IP; - } - } - - version_str = qdma_get_ip_type(dev_hndl, is_vf, version_info->ip_type); - if (version_str != NULL) - qdma_strncpy(version_info->qdma_ip_type_str, - version_str, - QDMA_HW_VERSION_STRING_LEN); - - if (version_info->ip_type == QDMA_SOFT_IP) { - switch (vivado_release_id) { - case 0: - version_info->vivado_release = QDMA_VIVADO_2018_3; - break; - case 1: - version_info->vivado_release = QDMA_VIVADO_2019_1; - break; - case 2: - version_info->vivado_release = QDMA_VIVADO_2019_2; - break; - default: - version_info->vivado_release = QDMA_VIVADO_NONE; - break; - } - } else if (version_info->ip_type == EQDMA_SOFT_IP) { - switch (vivado_release_id) { - case 0: - version_info->vivado_release = QDMA_VIVADO_2020_1; - break; - case 1: - version_info->vivado_release = QDMA_VIVADO_2020_2; - break; - case 2: - version_info->vivado_release = QDMA_VIVADO_2022_1; - break; - default: - version_info->vivado_release = QDMA_VIVADO_NONE; - break; - } - } else if (version_info->device_type == QDMA_DEVICE_VERSAL_CPM5) { - switch (vivado_release_id) { - case 0: - version_info->vivado_release = QDMA_VIVADO_2021_1; - break; - case 1: - version_info->vivado_release = QDMA_VIVADO_2022_1; - break; - default: - version_info->vivado_release = QDMA_VIVADO_NONE; - break; - } - } else { /* Versal case */ - switch (vivado_release_id) { - case 0: - version_info->vivado_release = QDMA_VIVADO_2019_2; - break; - default: - version_info->vivado_release = QDMA_VIVADO_NONE; - break; - } - } - - version_str = qdma_get_vivado_release_id( - version_info->vivado_release); - if (version_str != NULL) - qdma_strncpy(version_info->qdma_vivado_release_id_str, - version_str, - QDMA_HW_VERSION_STRING_LEN); -} - - -/* - * dump_reg() - Helper function to dump register value into string - * - * return len - length of the string copied into buffer - */ -int dump_reg(char *buf, int buf_sz, uint32_t raddr, - const char *rname, uint32_t rval) -{ - /* length of the line should be minimum 80 chars. - * If below print pattern is changed, check for - * new buffer size requirement - */ - if (buf_sz < DEBGFS_LINE_SZ) { - qdma_log_error("%s: buf_sz(%d) < expected(%d): err: %d\n", - __func__, - buf_sz, DEBGFS_LINE_SZ, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - return QDMA_SNPRINTF_S(buf, buf_sz, DEBGFS_LINE_SZ, - "[%#7x] %-47s %#-10x %u\n", - raddr, rname, rval, rval); - -} - -void qdma_memset(void *to, uint8_t val, uint32_t size) -{ - uint32_t i; - uint8_t *_to = (uint8_t *)to; - - for (i = 0; i < size; i++) - _to[i] = val; -} - -/*****************************************************************************/ -/** - * qdma_queue_cmpt_cidx_read() - function to read the CMPT CIDX register - * - * @dev_hndl: device handle - * @is_vf: Whether PF or VF - * @qid: Queue id relative to the PF/VF calling this API - * @reg_info: pointer to array to hold the values read - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -static int qdma_queue_cmpt_cidx_read(void *dev_hndl, uint8_t is_vf, - uint16_t qid, struct qdma_q_cmpt_cidx_reg_info *reg_info) -{ - uint32_t reg_val = 0; - uint32_t reg_addr = (is_vf) ? QDMA_OFFSET_VF_DMAP_SEL_CMPT_CIDX : - QDMA_OFFSET_DMAP_SEL_CMPT_CIDX; - - if (!dev_hndl) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - if (!reg_info) { - qdma_log_error("%s: reg_info is NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - - reg_addr += qid * QDMA_CMPT_CIDX_STEP; - - reg_val = qdma_reg_read(dev_hndl, reg_addr); - - reg_info->wrb_cidx = - FIELD_GET(QDMA_DMAP_SEL_CMPT_WRB_CIDX_MASK, reg_val); - reg_info->counter_idx = - (uint8_t)(FIELD_GET(QDMA_DMAP_SEL_CMPT_CNT_THRESH_MASK, - reg_val)); - reg_info->wrb_en = - (uint8_t)(FIELD_GET(QDMA_DMAP_SEL_CMPT_STS_DESC_EN_MASK, - reg_val)); - reg_info->irq_en = - (uint8_t)(FIELD_GET(QDMA_DMAP_SEL_CMPT_IRQ_EN_MASK, reg_val)); - reg_info->timer_idx = - (uint8_t)(FIELD_GET(QDMA_DMAP_SEL_CMPT_TMR_CNT_MASK, reg_val)); - reg_info->trig_mode = - (uint8_t)(FIELD_GET(QDMA_DMAP_SEL_CMPT_TRG_MODE_MASK, reg_val)); - - return QDMA_SUCCESS; -} - - -/*****************************************************************************/ -/** - * qdma_initiate_flr() - function to initiate Function Level Reset - * - * @dev_hndl: device handle - * @is_vf: Whether PF or VF - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -static int qdma_initiate_flr(void *dev_hndl, uint8_t is_vf) -{ - uint32_t reg_addr = (is_vf) ? QDMA_OFFSET_VF_REG_FLR_STATUS : - QDMA_OFFSET_PF_REG_FLR_STATUS; - - if (!dev_hndl) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - qdma_reg_write(dev_hndl, reg_addr, 1); - - return QDMA_SUCCESS; -} - -/*****************************************************************************/ -/** - * qdma_is_flr_done() - function to check whether the FLR is done or not - * - * @dev_hndl: device handle - * @is_vf: Whether PF or VF - * @done: if FLR process completed , done is 1 else 0. - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -static int qdma_is_flr_done(void *dev_hndl, uint8_t is_vf, uint8_t *done) -{ - int rv; - uint32_t reg_addr = (is_vf) ? QDMA_OFFSET_VF_REG_FLR_STATUS : - QDMA_OFFSET_PF_REG_FLR_STATUS; - - if (!dev_hndl) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - if (!done) { - qdma_log_error("%s: done is NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - /* wait for it to become zero */ - rv = hw_monitor_reg(dev_hndl, reg_addr, QDMA_FLR_STATUS_MASK, - 0, 5 * QDMA_REG_POLL_DFLT_INTERVAL_US, - QDMA_REG_POLL_DFLT_TIMEOUT_US); - if (rv < 0) - *done = 0; - else - *done = 1; - - return QDMA_SUCCESS; -} - -/*****************************************************************************/ -/** - * qdma_is_config_bar() - function for the config bar verification - * - * @dev_hndl: device handle - * @is_vf: Whether PF or VF - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -static int qdma_is_config_bar(void *dev_hndl, uint8_t is_vf, enum qdma_ip *ip) -{ - uint32_t reg_val = 0; - uint32_t reg_addr = (is_vf) ? QDMA_OFFSET_VF_VERSION : - QDMA_OFFSET_CONFIG_BLOCK_ID; - - if (!dev_hndl) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - reg_val = qdma_reg_read(dev_hndl, reg_addr); - - /** TODO: Version register for VFs is 0x5014 for EQDMA and - * 0x1014 for QDMA/Versal. First time reading 0x5014 for - * all the device and based on the upper 16 bits value - * (i.e. 0x1fd3), finding out whether its EQDMA or QDMA/Versal - * for EQDMA VFs. - * Need to modify this logic once the hardware team - * comes up with a common register for VFs - */ - if (is_vf) { - if (FIELD_GET(QDMA_GLBL2_VF_UNIQUE_ID_MASK, reg_val) - != QDMA_MAGIC_NUMBER) { - /* Its either QDMA or Versal */ - -#ifdef EQDMA_CPM5_VF_GT_256Q_SUPPORTED - *ip = EQDMA_CPM5_IP; - reg_addr = EQDMA_CPM5_OFFSET_VF_VERSION; -#else - *ip = EQDMA_IP; - reg_addr = EQDMA_OFFSET_VF_VERSION; -#endif - reg_val = qdma_reg_read(dev_hndl, reg_addr); - } else { - *ip = QDMA_OR_VERSAL_IP; - return QDMA_SUCCESS; - } - } - - if (FIELD_GET(QDMA_CONFIG_BLOCK_ID_MASK, reg_val) - != QDMA_MAGIC_NUMBER) { - qdma_log_error("%s: Invalid config bar, err:%d\n", - __func__, - -QDMA_ERR_HWACC_INV_CONFIG_BAR); - return -QDMA_ERR_HWACC_INV_CONFIG_BAR; - } - - return QDMA_SUCCESS; -} - -int qdma_acc_reg_dump_buf_len(void *dev_hndl, enum qdma_ip_type ip_type, - enum qdma_device_type device_type, int *buflen) -{ - uint32_t len = 0; - int rv = 0; - - *buflen = 0; - - if (!dev_hndl) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - - return -QDMA_ERR_INV_PARAM; - } - - switch (ip_type) { - case QDMA_SOFT_IP: - len = qdma_soft_reg_dump_buf_len(); - break; - case QDMA_VERSAL_HARD_IP: - if (device_type == QDMA_DEVICE_VERSAL_CPM4) - len = qdma_cpm4_reg_dump_buf_len(); - else if (device_type == QDMA_DEVICE_VERSAL_CPM5) - len = eqdma_cpm5_reg_dump_buf_len(); - else { - qdma_log_error("%s: Invalid device type, err = %d", - __func__, -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - break; - case EQDMA_SOFT_IP: - len = eqdma_reg_dump_buf_len(); - break; - default: - qdma_log_error("%s: Invalid version number, err = %d", - __func__, -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - *buflen = (int)len; - return rv; -} - -int qdma_acc_reg_info_len(void *dev_hndl, enum qdma_ip_type ip_type, - enum qdma_device_type device_type, int *buflen, int *num_regs) -{ - uint32_t len = 0; - int rv = 0; - - if (!dev_hndl) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - - return -QDMA_ERR_INV_PARAM; - } - - if (!buflen) { - qdma_log_error("%s: buflen is NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - - return -QDMA_ERR_INV_PARAM; - } - - if (!num_regs) { - qdma_log_error("%s: num_regs is NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - - return -QDMA_ERR_INV_PARAM; - } - - *buflen = 0; - - switch (ip_type) { - case QDMA_SOFT_IP: - len = 0; - *num_regs = 0; - break; - case QDMA_VERSAL_HARD_IP: - if (device_type == QDMA_DEVICE_VERSAL_CPM4) { - len = qdma_cpm4_reg_dump_buf_len(); - *num_regs = (int)((len / REG_DUMP_SIZE_PER_LINE) - 1); - } else if (device_type == QDMA_DEVICE_VERSAL_CPM5) { - len = eqdma_cpm5_reg_dump_buf_len(); - *num_regs = (int)((len / REG_DUMP_SIZE_PER_LINE) - 1); - } else { - qdma_log_error("%s: Invalid device type, err = %d", - __func__, -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - break; - case EQDMA_SOFT_IP: - len = eqdma_reg_dump_buf_len(); - *num_regs = (int)((len / REG_DUMP_SIZE_PER_LINE) - 1); - break; - default: - qdma_log_error("%s: Invalid version number, err = %d", - __func__, -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - *buflen = (int)len; - return rv; -} - -int qdma_acc_context_buf_len(void *dev_hndl, enum qdma_ip_type ip_type, - enum qdma_device_type device_type, uint8_t st, - enum qdma_dev_q_type q_type, uint32_t *buflen) -{ - int rv = 0; - - *buflen = 0; - if (!dev_hndl) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - - return -QDMA_ERR_INV_PARAM; - } - - switch (ip_type) { - case QDMA_SOFT_IP: - rv = qdma_soft_context_buf_len(st, q_type, buflen); - break; - case QDMA_VERSAL_HARD_IP: - if (device_type == QDMA_DEVICE_VERSAL_CPM4) - rv = qdma_cpm4_context_buf_len(st, q_type, buflen); - else if (device_type == QDMA_DEVICE_VERSAL_CPM5) - rv = eqdma_cpm5_context_buf_len(st, q_type, buflen); - else { - qdma_log_error("%s: Invalid device type, err = %d", - __func__, -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - break; - case EQDMA_SOFT_IP: - rv = eqdma_context_buf_len(st, q_type, buflen); - break; - default: - qdma_log_error("%s: Invalid version number, err = %d", - __func__, -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - return rv; -} - -int qdma_acc_get_num_config_regs(void *dev_hndl, enum qdma_ip_type ip_type, - enum qdma_device_type device_type, uint32_t *num_regs) -{ - int rv = 0; - - *num_regs = 0; - if (!dev_hndl) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - - return -QDMA_ERR_INV_PARAM; - } - - switch (ip_type) { - case QDMA_SOFT_IP: - rv = qdma_get_config_num_regs(); - break; - case QDMA_VERSAL_HARD_IP: - if (device_type == QDMA_DEVICE_VERSAL_CPM4) - rv = qdma_cpm4_get_config_num_regs(); - else if (device_type == QDMA_DEVICE_VERSAL_CPM5) - rv = eqdma_cpm5_get_config_num_regs(); - else { - qdma_log_error("%s: Invalid device type, err = %d", - __func__, -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - break; - case EQDMA_SOFT_IP: - rv = eqdma_get_config_num_regs(); - break; - default: - qdma_log_error("%s: Invalid version number, err = %d", - __func__, -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - *num_regs = rv; - - return 0; -} - -/*****************************************************************************/ -/** - * qdma_acc_get_config_regs() - Function to get qdma config registers. - * - * @dev_hndl: device handle - * @is_vf: Whether PF or VF - * @ip_type: QDMA IP Type - * @device_type:QDMA DEVICE Type - * @reg_data: pointer to register data to be filled - * - * Return: Length up-till the buffer is filled -success and < 0 - failure - *****************************************************************************/ -int qdma_acc_get_config_regs(void *dev_hndl, uint8_t is_vf, - enum qdma_ip_type ip_type, enum qdma_device_type device_type, - uint32_t *reg_data) -{ - struct xreg_info *reg_info; - uint32_t count = 0; - uint32_t num_regs; - int rv = 0; - - if (!dev_hndl) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - if (is_vf) { - qdma_log_error("%s: Get Config regs not valid for VF, err:%d\n", - __func__, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - if (reg_data == NULL) { - qdma_log_error("%s: reg_data is NULL, err:%d\n", - __func__, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - switch (ip_type) { - case QDMA_SOFT_IP: - num_regs = qdma_get_config_num_regs(); - reg_info = qdma_get_config_regs(); - break; - case QDMA_VERSAL_HARD_IP: - if (device_type == QDMA_DEVICE_VERSAL_CPM4) { - num_regs = qdma_cpm4_get_config_num_regs(); - reg_info = qdma_cpm4_get_config_regs(); - } else if (device_type == QDMA_DEVICE_VERSAL_CPM5) { - num_regs = eqdma_cpm5_get_config_num_regs(); - reg_info = eqdma_cpm5_get_config_regs(); - } else { - qdma_log_error("%s: Invalid device type, err = %d", - __func__, -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - break; - case EQDMA_SOFT_IP: - num_regs = eqdma_get_config_num_regs(); - reg_info = eqdma_get_config_regs(); - break; - default: - qdma_log_error("%s: Invalid version number, err = %d", - __func__, -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - for (count = 0; count < num_regs - 1; count++) { - reg_data[count] = qdma_reg_read(dev_hndl, - reg_info[count].addr); - } - - return rv; -} - - -/*****************************************************************************/ -/** - * qdma_acc_dump_config_regs() - Function to get qdma config register dump in a - * buffer - * - * @dev_hndl: device handle - * @is_vf: Whether PF or VF - * @ip_type: QDMA IP Type - * @device_type:QDMA DEVICE Type - * @buf : pointer to buffer to be filled - * @buflen : Length of the buffer - * - * Return: Length up-till the buffer is filled -success and < 0 - failure - *****************************************************************************/ -int qdma_acc_dump_config_regs(void *dev_hndl, uint8_t is_vf, - enum qdma_ip_type ip_type, enum qdma_device_type device_type, - char *buf, uint32_t buflen) -{ - int rv = 0; - - switch (ip_type) { - case QDMA_SOFT_IP: - rv = qdma_soft_dump_config_regs(dev_hndl, is_vf, - buf, buflen); - break; - case QDMA_VERSAL_HARD_IP: - if (device_type == QDMA_DEVICE_VERSAL_CPM4) - rv = qdma_cpm4_dump_config_regs(dev_hndl, is_vf, - buf, buflen); - else if (device_type == QDMA_DEVICE_VERSAL_CPM5) - rv = eqdma_cpm5_dump_config_regs(dev_hndl, is_vf, - buf, buflen); - else { - qdma_log_error("%s: Invalid device type, err = %d", - __func__, -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - break; - case EQDMA_SOFT_IP: - rv = eqdma_dump_config_regs(dev_hndl, is_vf, - buf, buflen); - break; - default: - qdma_log_error("%s: Invalid version number, err = %d", - __func__, -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - return rv; -} - -/*****************************************************************************/ -/** - * qdma_acc_dump_reg_info() - Function to dump fileds in - * a specified register. - * - * @dev_hndl: device handle - * @ip_type: QDMA IP Type - * @device_type:QDMA DEVICE Type - * @buf : pointer to buffer to be filled - * @buflen : Length of the buffer - * - * Return: Length up-till the buffer is filled -success and < 0 - failure - *****************************************************************************/ -int qdma_acc_dump_reg_info(void *dev_hndl, enum qdma_ip_type ip_type, - enum qdma_device_type device_type, uint32_t reg_addr, - uint32_t num_regs, char *buf, uint32_t buflen) -{ - int rv = 0; - - if (!dev_hndl) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - if (!buf || !buflen) { - qdma_log_error("%s: Invalid input buffer, err = %d", - __func__, -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - switch (ip_type) { - case QDMA_SOFT_IP: - QDMA_SNPRINTF_S(buf, buflen, DEBGFS_LINE_SZ, - "QDMA reg field info not supported for QDMA_SOFT_IP\n"); - break; - case QDMA_VERSAL_HARD_IP: - if (device_type == QDMA_DEVICE_VERSAL_CPM4) - rv = qdma_cpm4_dump_reg_info(dev_hndl, reg_addr, - num_regs, buf, buflen); - else if (device_type == QDMA_DEVICE_VERSAL_CPM5) - rv = eqdma_cpm5_dump_reg_info(dev_hndl, reg_addr, - num_regs, buf, buflen); - else { - qdma_log_error("%s: Invalid device type, err = %d", - __func__, -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - break; - case EQDMA_SOFT_IP: - rv = eqdma_dump_reg_info(dev_hndl, reg_addr, - num_regs, buf, buflen); - break; - default: - qdma_log_error("%s: Invalid version number, err = %d", - __func__, -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - return rv; -} - -/*****************************************************************************/ -/** - * qdma_acc_dump_queue_context() - Function to get qdma queue context dump in a - * buffer - * - * @dev_hndl: device handle - * @ip_type: QDMA IP Type - * @device_type:QDMA DEVICE Type - * @st: Queue Mode (ST or MM) - * @q_type: Queue Type - * @ctxt_data: Context Data - * @buf : pointer to buffer to be filled - * @buflen : Length of the buffer - * - * Return: Length up-till the buffer is filled -success and < 0 - failure - *****************************************************************************/ -int qdma_acc_dump_queue_context(void *dev_hndl, - enum qdma_ip_type ip_type, - enum qdma_device_type device_type, - uint8_t st, - enum qdma_dev_q_type q_type, - struct qdma_descq_context *ctxt_data, - char *buf, uint32_t buflen) -{ - int rv = 0; - - switch (ip_type) { - case QDMA_SOFT_IP: - rv = qdma_soft_dump_queue_context(dev_hndl, - st, q_type, ctxt_data, buf, buflen); - break; - case QDMA_VERSAL_HARD_IP: - if (device_type == QDMA_DEVICE_VERSAL_CPM4) - rv = qdma_cpm4_dump_queue_context(dev_hndl, - st, q_type, ctxt_data, buf, buflen); - else if (device_type == QDMA_DEVICE_VERSAL_CPM5) - rv = eqdma_cpm5_dump_queue_context(dev_hndl, - st, q_type, ctxt_data, buf, buflen); - else { - qdma_log_error("%s: Invalid device type, err = %d", - __func__, -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - break; - case EQDMA_SOFT_IP: - rv = eqdma_dump_queue_context(dev_hndl, - st, q_type, ctxt_data, buf, buflen); - break; - default: - qdma_log_error("%s: Invalid version number, err = %d", - __func__, -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - return rv; -} - -/*****************************************************************************/ -/** - * qdma_acc_read_dump_queue_context() - Function to read and dump the queue - * context in the user-provided buffer. This API is valid only for PF and - * should not be used for VFs. For VF's use qdma_dump_queue_context() API - * after reading the context through mailbox. - * - * @dev_hndl: device handle - * @ip_type: QDMA IP type - * @device_type:QDMA DEVICE Type - * @hw_qid: queue id - * @st: Queue Mode(ST or MM) - * @q_type: Queue type(H2C/C2H/CMPT)* - * @buf : pointer to buffer to be filled - * @buflen : Length of the buffer - * - * Return: Length up-till the buffer is filled -success and < 0 - failure - *****************************************************************************/ -int qdma_acc_read_dump_queue_context(void *dev_hndl, - enum qdma_ip_type ip_type, - enum qdma_device_type device_type, - uint16_t func_id, - uint16_t qid_hw, - uint8_t st, - enum qdma_dev_q_type q_type, - char *buf, uint32_t buflen) -{ - int rv = QDMA_SUCCESS; - - switch (ip_type) { - case QDMA_SOFT_IP: - rv = qdma_soft_read_dump_queue_context(dev_hndl, func_id, - qid_hw, st, q_type, buf, buflen); - break; - case QDMA_VERSAL_HARD_IP: - if (device_type == QDMA_DEVICE_VERSAL_CPM4) - rv = qdma_cpm4_read_dump_queue_context(dev_hndl, - func_id, qid_hw, st, q_type, buf, buflen); - else if (device_type == QDMA_DEVICE_VERSAL_CPM5) - rv = eqdma_cpm5_read_dump_queue_context(dev_hndl, - func_id, qid_hw, st, q_type, buf, buflen); - else { - qdma_log_error("%s: Invalid device type, err = %d", - __func__, -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - break; - case EQDMA_SOFT_IP: - rv = eqdma_read_dump_queue_context(dev_hndl, func_id, - qid_hw, st, q_type, buf, buflen); - break; - default: - qdma_log_error("%s: Invalid version number, err = %d", - __func__, -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - return rv; -} - -/*****************************************************************************/ -/** - * qdma_acc_dump_config_reg_list() - Dump the registers - * - * @dev_hndl: device handle - * @ip_type: QDMA ip type - * @num_regs : Max registers to read - * @reg_list : array of reg addr and reg values - * @buf : pointer to buffer to be filled - * @buflen : Length of the buffer - * - * Return: returns the platform specific error code - *****************************************************************************/ -int qdma_acc_dump_config_reg_list(void *dev_hndl, - enum qdma_ip_type ip_type, - enum qdma_device_type device_type, - uint32_t num_regs, - struct qdma_reg_data *reg_list, - char *buf, uint32_t buflen) -{ - int rv = 0; - - switch (ip_type) { - case QDMA_SOFT_IP: - rv = qdma_soft_dump_config_reg_list(dev_hndl, - num_regs, - reg_list, buf, buflen); - break; - case QDMA_VERSAL_HARD_IP: - if (device_type == QDMA_DEVICE_VERSAL_CPM4) - rv = qdma_cpm4_dump_config_reg_list(dev_hndl, - num_regs, - reg_list, buf, buflen); - else if (device_type == QDMA_DEVICE_VERSAL_CPM5) - rv = eqdma_cpm5_dump_config_reg_list(dev_hndl, - num_regs, - reg_list, buf, buflen); - else { - qdma_log_error("%s: Invalid device type, err = %d", - __func__, -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - break; - case EQDMA_SOFT_IP: - rv = eqdma_dump_config_reg_list(dev_hndl, - num_regs, - reg_list, buf, buflen); - break; - default: - qdma_log_error("%s: Invalid version number, err = %d", - __func__, -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - return rv; -} - - -/*****************************************************************************/ -/** - * qdma_get_function_number() - Function to get the function number - * - * @dev_hndl: device handle - * @func_id: pointer to hold the function id - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -static int qdma_get_function_number(void *dev_hndl, uint16_t *func_id) -{ - if (!dev_hndl || !func_id) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - *func_id = (uint8_t)qdma_reg_read(dev_hndl, - QDMA_OFFSET_GLBL2_CHANNEL_FUNC_RET); - - return QDMA_SUCCESS; -} - - -/*****************************************************************************/ -/** - * qdma_hw_error_intr_setup() - Function to set up the qdma error - * interrupt - * - * @dev_hndl: device handle - * @func_id: Function id - * @err_intr_index: Interrupt vector - * @rearm: rearm or not - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -static int qdma_hw_error_intr_setup(void *dev_hndl, uint16_t func_id, - uint8_t err_intr_index) -{ - uint32_t reg_val = 0; - - if (!dev_hndl) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - reg_val = - FIELD_SET(QDMA_GLBL_ERR_FUNC_MASK, func_id) | - FIELD_SET(QDMA_GLBL_ERR_VEC_MASK, err_intr_index); - - qdma_reg_write(dev_hndl, QDMA_OFFSET_GLBL_ERR_INT, reg_val); - - return QDMA_SUCCESS; -} - -/*****************************************************************************/ -/** - * qdma_hw_error_intr_rearm() - Function to re-arm the error interrupt - * - * @dev_hndl: device handle - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -static int qdma_hw_error_intr_rearm(void *dev_hndl) -{ - uint32_t reg_val = 0; - - if (!dev_hndl) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - reg_val = qdma_reg_read(dev_hndl, QDMA_OFFSET_GLBL_ERR_INT); - reg_val |= FIELD_SET(QDMA_GLBL_ERR_ARM_MASK, 1); - - qdma_reg_write(dev_hndl, QDMA_OFFSET_GLBL_ERR_INT, reg_val); - - return QDMA_SUCCESS; -} - -/*****************************************************************************/ -/** - * qdma_get_error_code() - function to get the qdma access mapped - * error code - * - * @acc_err_code: qdma access error code - * - * Return: returns the platform specific error code - *****************************************************************************/ -int qdma_get_error_code(int acc_err_code) -{ - return qdma_get_err_code(acc_err_code); -} - -int qdma_hw_access_init(void *dev_hndl, uint8_t is_vf, - struct qdma_hw_access *hw_access) -{ - int rv = QDMA_SUCCESS; - enum qdma_ip ip = EQDMA_IP; - - struct qdma_hw_version_info version_info; - - if (!dev_hndl) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - if (!hw_access) { - qdma_log_error("%s: hw_access is NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - rv = qdma_is_config_bar(dev_hndl, is_vf, &ip); - if (rv != QDMA_SUCCESS) { - qdma_log_error("%s: config bar passed is INVALID, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - return rv; - } - - qdma_memset(hw_access, 0, sizeof(struct qdma_hw_access)); - - if (ip == EQDMA_IP) - hw_access->qdma_get_version = &eqdma_get_version; - else if (ip == EQDMA_CPM5_IP) - hw_access->qdma_get_version = &eqdma_cpm5_get_version; - else - hw_access->qdma_get_version = &qdma_get_version; - - hw_access->qdma_init_ctxt_memory = &qdma_init_ctxt_memory; - hw_access->qdma_fmap_conf = &qdma_fmap_conf; - hw_access->qdma_sw_ctx_conf = &qdma_sw_ctx_conf; - hw_access->qdma_pfetch_ctx_conf = &qdma_pfetch_ctx_conf; - hw_access->qdma_cmpt_ctx_conf = &qdma_cmpt_ctx_conf; - hw_access->qdma_hw_ctx_conf = &qdma_hw_ctx_conf; - hw_access->qdma_credit_ctx_conf = &qdma_credit_ctx_conf; - hw_access->qdma_indirect_intr_ctx_conf = &qdma_indirect_intr_ctx_conf; - hw_access->qdma_set_default_global_csr = &qdma_set_default_global_csr; - hw_access->qdma_global_csr_conf = &qdma_global_csr_conf; - hw_access->qdma_global_writeback_interval_conf = - &qdma_global_writeback_interval_conf; - hw_access->qdma_queue_pidx_update = &qdma_queue_pidx_update; - hw_access->qdma_queue_cmpt_cidx_read = &qdma_queue_cmpt_cidx_read; - hw_access->qdma_queue_cmpt_cidx_update = &qdma_queue_cmpt_cidx_update; - hw_access->qdma_queue_intr_cidx_update = &qdma_queue_intr_cidx_update; - hw_access->qdma_mm_channel_conf = &qdma_mm_channel_conf; - hw_access->qdma_get_user_bar = &qdma_get_user_bar; - hw_access->qdma_get_function_number = &qdma_get_function_number; - hw_access->qdma_get_device_attributes = &qdma_get_device_attributes; - hw_access->qdma_hw_error_intr_setup = &qdma_hw_error_intr_setup; - hw_access->qdma_hw_error_intr_rearm = &qdma_hw_error_intr_rearm; - hw_access->qdma_hw_error_enable = &qdma_hw_error_enable; - hw_access->qdma_hw_get_error_name = &qdma_hw_get_error_name; - hw_access->qdma_hw_error_process = &qdma_hw_error_process; - hw_access->qdma_dump_config_regs = &qdma_soft_dump_config_regs; - hw_access->qdma_dump_queue_context = &qdma_soft_dump_queue_context; - hw_access->qdma_read_dump_queue_context = - &qdma_soft_read_dump_queue_context; - hw_access->qdma_dump_intr_context = &qdma_dump_intr_context; - hw_access->qdma_is_legacy_intr_pend = &qdma_is_legacy_intr_pend; - hw_access->qdma_clear_pend_legacy_intr = &qdma_clear_pend_legacy_intr; - hw_access->qdma_legacy_intr_conf = &qdma_legacy_intr_conf; - hw_access->qdma_initiate_flr = &qdma_initiate_flr; - hw_access->qdma_is_flr_done = &qdma_is_flr_done; - hw_access->qdma_get_error_code = &qdma_get_error_code; - hw_access->qdma_read_reg_list = &qdma_read_reg_list; - hw_access->qdma_dump_config_reg_list = - &qdma_soft_dump_config_reg_list; - hw_access->qdma_dump_reg_info = &qdma_dump_reg_info; - hw_access->mbox_base_pf = QDMA_OFFSET_MBOX_BASE_PF; - hw_access->mbox_base_vf = QDMA_OFFSET_MBOX_BASE_VF; - hw_access->qdma_max_errors = QDMA_ERRS_ALL; - - rv = hw_access->qdma_get_version(dev_hndl, is_vf, &version_info); - if (rv != QDMA_SUCCESS) - return rv; - - qdma_log_info("Device Type: %s\n", - qdma_get_device_type(version_info.device_type)); - - qdma_log_info("IP Type: %s\n", - qdma_get_ip_type(dev_hndl, is_vf, version_info.ip_type)); - - qdma_log_info("Vivado Release: %s\n", - qdma_get_vivado_release_id(version_info.vivado_release)); - - if (version_info.ip_type == QDMA_VERSAL_HARD_IP && - version_info.device_type == QDMA_DEVICE_VERSAL_CPM4) { - hw_access->qdma_init_ctxt_memory = - &qdma_cpm4_init_ctxt_memory; - hw_access->qdma_qid2vec_conf = &qdma_cpm4_qid2vec_conf; - hw_access->qdma_fmap_conf = &qdma_cpm4_fmap_conf; - hw_access->qdma_sw_ctx_conf = &qdma_cpm4_sw_ctx_conf; - hw_access->qdma_pfetch_ctx_conf = - &qdma_cpm4_pfetch_ctx_conf; - hw_access->qdma_cmpt_ctx_conf = &qdma_cpm4_cmpt_ctx_conf; - hw_access->qdma_hw_ctx_conf = &qdma_cpm4_hw_ctx_conf; - hw_access->qdma_credit_ctx_conf = - &qdma_cpm4_credit_ctx_conf; - hw_access->qdma_indirect_intr_ctx_conf = - &qdma_cpm4_indirect_intr_ctx_conf; - hw_access->qdma_set_default_global_csr = - &qdma_cpm4_set_default_global_csr; - hw_access->qdma_queue_pidx_update = - &qdma_cpm4_queue_pidx_update; - hw_access->qdma_queue_cmpt_cidx_update = - &qdma_cpm4_queue_cmpt_cidx_update; - hw_access->qdma_queue_intr_cidx_update = - &qdma_cpm4_queue_intr_cidx_update; - hw_access->qdma_get_user_bar = &qdma_cmp_get_user_bar; - hw_access->qdma_get_device_attributes = - &qdma_cpm4_get_device_attributes; - hw_access->qdma_dump_config_regs = - &qdma_cpm4_dump_config_regs; - hw_access->qdma_dump_intr_context = - &qdma_cpm4_dump_intr_context; - hw_access->qdma_hw_error_enable = - &qdma_cpm4_hw_error_enable; - hw_access->qdma_hw_error_process = - &qdma_cpm4_hw_error_process; - hw_access->qdma_hw_get_error_name = - &qdma_cpm4_hw_get_error_name; - hw_access->qdma_legacy_intr_conf = NULL; - hw_access->qdma_read_reg_list = &qdma_cpm4_read_reg_list; - hw_access->qdma_dump_config_reg_list = - &qdma_cpm4_dump_config_reg_list; - hw_access->qdma_dump_queue_context = - &qdma_cpm4_dump_queue_context; - hw_access->qdma_read_dump_queue_context = - &qdma_cpm4_read_dump_queue_context; - hw_access->qdma_dump_reg_info = &qdma_cpm4_dump_reg_info; - hw_access->qdma_max_errors = QDMA_CPM4_ERRS_ALL; - } - - if (version_info.ip_type == QDMA_VERSAL_HARD_IP && - version_info.device_type == QDMA_DEVICE_VERSAL_CPM5) { - hw_access->qdma_init_ctxt_memory = - &eqdma_cpm5_init_ctxt_memory; -#ifdef TANDEM_BOOT_SUPPORTED - hw_access->qdma_init_st_ctxt = - &eqdma_cpm5_init_st_ctxt; -#endif - hw_access->qdma_sw_ctx_conf = &eqdma_cpm5_sw_ctx_conf; - hw_access->qdma_fmap_conf = &eqdma_cpm5_fmap_conf; - hw_access->qdma_pfetch_ctx_conf = - &eqdma_cpm5_pfetch_ctx_conf; - hw_access->qdma_cmpt_ctx_conf = &eqdma_cpm5_cmpt_ctx_conf; - hw_access->qdma_indirect_intr_ctx_conf = - &eqdma_cpm5_indirect_intr_ctx_conf; - hw_access->qdma_dump_config_regs = - &eqdma_cpm5_dump_config_regs; - hw_access->qdma_dump_intr_context = - &eqdma_cpm5_dump_intr_context; - hw_access->qdma_hw_error_enable = - &eqdma_cpm5_hw_error_enable; - hw_access->qdma_hw_error_process = - &eqdma_cpm5_hw_error_process; - hw_access->qdma_hw_get_error_name = - &eqdma_cpm5_hw_get_error_name; - hw_access->qdma_hw_ctx_conf = &eqdma_cpm5_hw_ctx_conf; - hw_access->qdma_credit_ctx_conf = - &eqdma_cpm5_credit_ctx_conf; - hw_access->qdma_set_default_global_csr = - &eqdma_cpm5_set_default_global_csr; - hw_access->qdma_get_device_attributes = - &eqdma_cpm5_get_device_attributes; - hw_access->qdma_get_user_bar = &eqdma_cpm5_get_user_bar; - hw_access->qdma_read_reg_list = &eqdma_cpm5_read_reg_list; - hw_access->qdma_dump_config_reg_list = - &eqdma_cpm5_dump_config_reg_list; - hw_access->qdma_dump_queue_context = - &eqdma_cpm5_dump_queue_context; - hw_access->qdma_read_dump_queue_context = - &eqdma_cpm5_read_dump_queue_context; - hw_access->qdma_dump_reg_info = &eqdma_cpm5_dump_reg_info; - /* All CSR and Queue space register belongs to Window 0. - * Mailbox and MSIX register belongs to Window 1 - * Therefore, Mailbox offsets are different for EQDMA - * Mailbox offset for PF : 128K + original address - * Mailbox offset for VF : 16K + original address - */ - hw_access->mbox_base_pf = EQDMA_CPM5_OFFSET_MBOX_BASE_PF; - hw_access->mbox_base_vf = EQDMA_CPM5_OFFSET_MBOX_BASE_VF; - hw_access->qdma_max_errors = EQDMA_CPM5_ERRS_ALL; - -} - - if (version_info.ip_type == EQDMA_SOFT_IP) { - hw_access->qdma_init_ctxt_memory = &eqdma_init_ctxt_memory; - hw_access->qdma_sw_ctx_conf = &eqdma_sw_ctx_conf; - hw_access->qdma_fmap_conf = &eqdma_fmap_conf; - hw_access->qdma_pfetch_ctx_conf = &eqdma_pfetch_ctx_conf; - hw_access->qdma_cmpt_ctx_conf = &eqdma_cmpt_ctx_conf; - hw_access->qdma_indirect_intr_ctx_conf = - &eqdma_indirect_intr_ctx_conf; - hw_access->qdma_dump_config_regs = &eqdma_dump_config_regs; - hw_access->qdma_dump_intr_context = &eqdma_dump_intr_context; - hw_access->qdma_hw_error_enable = &eqdma_hw_error_enable; - hw_access->qdma_hw_error_process = &eqdma_hw_error_process; - hw_access->qdma_hw_get_error_name = &eqdma_hw_get_error_name; - hw_access->qdma_hw_ctx_conf = &eqdma_hw_ctx_conf; - hw_access->qdma_credit_ctx_conf = &eqdma_credit_ctx_conf; - hw_access->qdma_set_default_global_csr = - &eqdma_set_default_global_csr; - hw_access->qdma_get_device_attributes = - &eqdma_get_device_attributes; - hw_access->qdma_get_user_bar = &eqdma_get_user_bar; - hw_access->qdma_read_reg_list = &eqdma_read_reg_list; - hw_access->qdma_dump_config_reg_list = - &eqdma_dump_config_reg_list; - hw_access->qdma_dump_queue_context = - &eqdma_dump_queue_context; - hw_access->qdma_read_dump_queue_context = - &eqdma_read_dump_queue_context; - hw_access->qdma_dump_reg_info = &eqdma_dump_reg_info; - /* All CSR and Queue space register belongs to Window 0. - * Mailbox and MSIX register belongs to Window 1 - * Therefore, Mailbox offsets are different for EQDMA - * Mailbox offset for PF : 128K + original address - * Mailbox offset for VF : 16K + original address - */ - hw_access->mbox_base_pf = EQDMA_OFFSET_MBOX_BASE_PF; - hw_access->mbox_base_vf = EQDMA_OFFSET_MBOX_BASE_VF; - hw_access->qdma_max_errors = EQDMA_ERRS_ALL; - } - - return QDMA_SUCCESS; -} diff --git a/QDMA/DPDK/drivers/net/qdma/qdma_access/qdma_access_common.h b/QDMA/DPDK/drivers/net/qdma/qdma_access/qdma_access_common.h deleted file mode 100755 index 24a218976..000000000 --- a/QDMA/DPDK/drivers/net/qdma/qdma_access/qdma_access_common.h +++ /dev/null @@ -1,942 +0,0 @@ -/* - * Copyright (c) 2019-2022, Xilinx, Inc. All rights reserved. - * Copyright (c) 2022, Advanced Micro Devices, Inc. All rights reserved. - * - * BSD LICENSE - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * * Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#ifndef __QDMA_ACCESS_COMMON_H_ -#define __QDMA_ACCESS_COMMON_H_ - -#ifdef __cplusplus -extern "C" { -#endif - -#include "qdma_access_export.h" -#include "qdma_access_errors.h" - -/* QDMA HW version string array length */ -#define QDMA_HW_VERSION_STRING_LEN 32 - -#define ENABLE_INIT_CTXT_MEMORY 1 - -#ifdef GCC_COMPILER -static inline uint32_t get_trailing_zeros(uint64_t x) -{ - uint32_t rv = - __builtin_ffsll(x) - 1; - return rv; -} -#else -static inline uint32_t get_trailing_zeros(uint64_t value) -{ - uint32_t pos = 0; - - if ((value & 0xffffffff) == 0) { - pos += 32; - value >>= 32; - } - if ((value & 0xffff) == 0) { - pos += 16; - value >>= 16; - } - if ((value & 0xff) == 0) { - pos += 8; - value >>= 8; - } - if ((value & 0xf) == 0) { - pos += 4; - value >>= 4; - } - if ((value & 0x3) == 0) { - pos += 2; - value >>= 2; - } - if ((value & 0x1) == 0) - pos += 1; - - return pos; -} -#endif - -#define FIELD_SHIFT(mask) get_trailing_zeros(mask) -#define FIELD_SET(mask, val) ((val << FIELD_SHIFT(mask)) & mask) -#define FIELD_GET(mask, reg) ((reg & mask) >> FIELD_SHIFT(mask)) - - -/* CSR Default values */ -#define DEFAULT_MAX_DSC_FETCH 6 -#define DEFAULT_WRB_INT QDMA_WRB_INTERVAL_128 - -/* Default values for 0xB08 */ -#define DEFAULT_PFCH_NUM_ENTRIES_PER_Q 8 -#define DEFAULT_PFCH_MAX_Q_CNT 16 -#define DEFAULT_C2H_INTR_TIMER_TICK 25 -#define DEFAULT_CMPT_COAL_TIMER_TICK 25 -#define DEFAULT_CMPT_COAL_MAX_BUF_SZ 32 - -#ifdef THROUGHPUT_MEASUREMENT -/* Update WRB coalesce timer count for throughput measurement */ -#define DEFAULT_CMPT_COAL_TIMER_CNT 10 -#else -/* Update WRB coalesce timer count for low latency measurement */ -#define DEFAULT_CMPT_COAL_TIMER_CNT 5 -#endif - -#define QDMA_BAR_NUM 6 - -/** Maximum data vectors to be used for each function - * TODO: Please note that for 2018.2 only one vector would be used - * per pf and only one ring would be created for this vector - * It is also assumed that all functions have the same number of data vectors - * and currently different number of vectors per PF is not supported - */ -#define QDMA_NUM_DATA_VEC_FOR_INTR_CXT 1 - -enum ind_ctxt_cmd_op { - QDMA_CTXT_CMD_CLR, - QDMA_CTXT_CMD_WR, - QDMA_CTXT_CMD_RD, - QDMA_CTXT_CMD_INV -}; - -enum ind_ctxt_cmd_sel { - QDMA_CTXT_SEL_SW_C2H, - QDMA_CTXT_SEL_SW_H2C, - QDMA_CTXT_SEL_HW_C2H, - QDMA_CTXT_SEL_HW_H2C, - QDMA_CTXT_SEL_CR_C2H, - QDMA_CTXT_SEL_CR_H2C, - QDMA_CTXT_SEL_CMPT, - QDMA_CTXT_SEL_PFTCH, - QDMA_CTXT_SEL_INT_COAL, - QDMA_CTXT_SEL_PASID_RAM_LOW, - QDMA_CTXT_SEL_PASID_RAM_HIGH, - QDMA_CTXT_SEL_TIMER, - QDMA_CTXT_SEL_FMAP, -}; - -/* polling a register */ -#define QDMA_REG_POLL_DFLT_INTERVAL_US 10 /* 10us per poll */ -#define QDMA_REG_POLL_DFLT_TIMEOUT_US (500*1000) /* 500ms */ - -/** Constants */ -#define QDMA_NUM_RING_SIZES 16 -#define QDMA_NUM_C2H_TIMERS 16 -#define QDMA_NUM_C2H_BUFFER_SIZES 16 -#define QDMA_NUM_C2H_COUNTERS 16 -#define QDMA_MM_CONTROL_RUN 0x1 -#define QDMA_MM_CONTROL_STEP 0x100 -#define QDMA_MAGIC_NUMBER 0x1fd3 -#define QDMA_PIDX_STEP 0x10 -#define QDMA_CMPT_CIDX_STEP 0x10 -#define QDMA_INT_CIDX_STEP 0x10 - - -/** QDMA_IND_REG_SEL_PFTCH */ -#define QDMA_PFTCH_CTXT_SW_CRDT_GET_H_MASK GENMASK(15, 3) -#define QDMA_PFTCH_CTXT_SW_CRDT_GET_L_MASK GENMASK(2, 0) - -/** QDMA_IND_REG_SEL_CMPT */ -#define QDMA_COMPL_CTXT_BADDR_GET_H_MASK GENMASK_ULL(63, 38) -#define QDMA_COMPL_CTXT_BADDR_GET_L_MASK GENMASK_ULL(37, 12) -#define QDMA_COMPL_CTXT_PIDX_GET_H_MASK GENMASK(15, 4) -#define QDMA_COMPL_CTXT_PIDX_GET_L_MASK GENMASK(3, 0) - -#define QDMA_INTR_CTXT_BADDR_GET_H_MASK GENMASK_ULL(63, 61) -#define QDMA_INTR_CTXT_BADDR_GET_M_MASK GENMASK_ULL(60, 29) -#define QDMA_INTR_CTXT_BADDR_GET_L_MASK GENMASK_ULL(28, 12) - -#define QDMA_GLBL2_MM_CMPT_EN_MASK BIT(2) -#define QDMA_GLBL2_FLR_PRESENT_MASK BIT(1) -#define QDMA_GLBL2_MAILBOX_EN_MASK BIT(0) - -#define QDMA_REG_IND_CTXT_REG_COUNT 8 - -/* ------------------------ indirect register context fields -----------*/ -union qdma_ind_ctxt_cmd { - uint32_t word; - struct { - uint32_t busy:1; - uint32_t sel:4; - uint32_t op:2; - uint32_t qid:12; - uint32_t rsvd:14; - } bits; -}; - -#define QDMA_IND_CTXT_DATA_NUM_REGS 8 - -/** - * struct qdma_indirect_ctxt_regs - Inirect Context programming registers - */ -struct qdma_indirect_ctxt_regs { - uint32_t qdma_ind_ctxt_data[QDMA_IND_CTXT_DATA_NUM_REGS]; - uint32_t qdma_ind_ctxt_mask[QDMA_IND_CTXT_DATA_NUM_REGS]; - union qdma_ind_ctxt_cmd cmd; -}; - -/** - * struct qdma_fmap_cfg - fmap config data structure - */ -struct qdma_fmap_cfg { - - /** @qbase - queue base for the function */ - uint16_t qbase; - /** @qmax - maximum queues in the function */ - uint16_t qmax; -}; - -/** - * struct qdma_qid2vec - qid to vector mapping data structure - */ -struct qdma_qid2vec { - - /** @c2h_vector - For direct interrupt, it is the interrupt - * vector index of msix table; - * for indirect interrupt, it is the ring index - */ - uint8_t c2h_vector; - /** @c2h_en_coal - C2H Interrupt aggregation enable */ - uint8_t c2h_en_coal; - /** @h2c_vector - For direct interrupt, it is the interrupt - * vector index of msix table; - * for indirect interrupt, it is the ring index - */ - uint8_t h2c_vector; - /** @h2c_en_coal - H2C Interrupt aggregation enable */ - uint8_t h2c_en_coal; -}; - -/** - * struct qdma_descq_sw_ctxt - descq SW context config data structure - */ -struct qdma_descq_sw_ctxt { - - /** @ring_bs_addr - ring base address */ - uint64_t ring_bs_addr; - /** @vec - vector number */ - uint16_t vec; - /** @pidx - initial producer index */ - uint16_t pidx; - /** @irq_arm - Interrupt Arm */ - uint8_t irq_arm; - /** @fnc_id - Function ID */ - uint8_t fnc_id; - /** @qen - Indicates that the queue is enabled */ - uint8_t qen; - /** @frcd_en -Enable fetch credit */ - uint8_t frcd_en; - /** @wbi_chk -Writeback/Interrupt after pending check */ - uint8_t wbi_chk; - /** @wbi_intvl_en -Write back/Interrupt interval */ - uint8_t wbi_intvl_en; - /** @at - Address tanslation */ - uint8_t at; - /** @fetch_max - Maximum number of descriptor fetches outstanding */ - uint8_t fetch_max; - /** @rngsz_idx - Descriptor ring size index */ - uint8_t rngsz_idx; - /** @desc_sz -Descriptor fetch size */ - uint8_t desc_sz; - /** @bypass - bypass enable */ - uint8_t bypass; - /** @mm_chn - MM channel */ - uint8_t mm_chn; - /** @wbk_en -Writeback enable */ - uint8_t wbk_en; - /** @irq_en -Interrupt enable */ - uint8_t irq_en; - /** @port_id -Port_id */ - uint8_t port_id; - /** @irq_no_last - No interrupt was sent */ - uint8_t irq_no_last; - /** @err - Error status */ - uint8_t err; - /** @err_wb_sent -writeback/interrupt was sent for an error */ - uint8_t err_wb_sent; - /** @irq_req - Interrupt due to error waiting to be sent */ - uint8_t irq_req; - /** @mrkr_dis - Marker disable */ - uint8_t mrkr_dis; - /** @is_mm - MM mode */ - uint8_t is_mm; - /** @intr_aggr - interrupt aggregation enable */ - uint8_t intr_aggr; - /** @pasid_en - PASID Enable */ - uint8_t pasid_en; - /** @dis_intr_on_vf - Disbale interrupt with VF */ - uint8_t dis_intr_on_vf; - /** @virtio_en - Queue is in Virtio Mode */ - uint8_t virtio_en; - /** @pack_byp_out - descs on desc output interface can be packed */ - uint8_t pack_byp_out; - /** @irq_byp - IRQ Bypass mode */ - uint8_t irq_byp; - /** @host_id - Host ID */ - uint8_t host_id; - /** @pasid - PASID */ - uint32_t pasid; - /** @virtio_dsc_base - Virtio Desc Base Address */ - uint64_t virtio_dsc_base; -}; - -/** - * struct qdma_descq_hw_ctxt - descq hw context config data structure - */ -struct qdma_descq_hw_ctxt { - /** @cidx - consumer index */ - uint16_t cidx; - /** @crd_use - credits consumed */ - uint16_t crd_use; - /** @dsc_pend - descriptors pending */ - uint8_t dsc_pend; - /** @idl_stp_b -Queue invalid and no descriptors pending */ - uint8_t idl_stp_b; - /** @evt_pnd - Event pending */ - uint8_t evt_pnd; - /** @fetch_pnd -Descriptor fetch pending */ - uint8_t fetch_pnd; -}; - -/** - * struct qdma_descq_credit_ctxt - descq credit context config data structure - */ -struct qdma_descq_credit_ctxt { - - /** @credit -Fetch credits received. */ - uint32_t credit; -}; - -/** - * struct qdma_descq_prefetch_ctxt - descq pfetch context config data structure - */ -struct qdma_descq_prefetch_ctxt { - /** @sw_crdt -Software credit */ - uint16_t sw_crdt; - /** @bypass - bypass enable */ - uint8_t bypass; - /** @bufsz_idx - c2h buffer size index */ - uint8_t bufsz_idx; - /** @port_id - port ID */ - uint8_t port_id; - /** @var_desc - Variable Descriptor */ - uint8_t var_desc; - /** @num_pftch - Number of descs prefetched */ - uint16_t num_pftch; - /** @err -Error detected on this queue */ - uint8_t err; - /** @pfch_en - Enable prefetch */ - uint8_t pfch_en; - /** @pfch - Queue is in prefetch */ - uint8_t pfch; - /** @valid - context is valid */ - uint8_t valid; -}; - -/** - * struct qdma_descq_cmpt_ctxt - descq completion context config data structure - */ -struct qdma_descq_cmpt_ctxt { - /** @bs_addr - completion ring base address */ - uint64_t bs_addr; - /** @vec - Interrupt Vector */ - uint16_t vec; - /** @pidx_l - producer index low */ - uint16_t pidx; - /** @cidx - consumer index */ - uint16_t cidx; - /** @en_stat_desc - Enable Completion Status writes */ - uint8_t en_stat_desc; - /** @en_int - Enable Completion interrupts */ - uint8_t en_int; - /** @trig_mode - Interrupt and Completion Status Write Trigger Mode */ - uint8_t trig_mode; - /** @fnc_id - Function ID */ - uint8_t fnc_id; - /** @counter_idx - Index to counter register */ - uint8_t counter_idx; - /** @timer_idx - Index to timer register */ - uint8_t timer_idx; - /** @in_st - Interrupt State */ - uint8_t in_st; - /** @color - initial color bit to be used on Completion */ - uint8_t color; - /** @ringsz_idx - Completion ring size index to ring size registers */ - uint8_t ringsz_idx; - /** @desc_sz -descriptor size */ - uint8_t desc_sz; - /** @valid - context valid */ - uint8_t valid; - /** @err - error status */ - uint8_t err; - /** - * @user_trig_pend - user logic initiated interrupt is - * pending to be generate - */ - uint8_t user_trig_pend; - /** @timer_running - timer is running on this queue */ - uint8_t timer_running; - /** @full_upd - Full update */ - uint8_t full_upd; - /** @ovf_chk_dis - Completion Ring Overflow Check Disable */ - uint8_t ovf_chk_dis; - /** @at -Address Translation */ - uint8_t at; - /** @int_aggr -Interrupt Aggregation */ - uint8_t int_aggr; - /** @dis_intr_on_vf - Disbale interrupt with VF */ - uint8_t dis_intr_on_vf; - /** @vio - queue is in VirtIO mode */ - uint8_t vio; - /** @dir_c2h - DMA direction is C2H */ - uint8_t dir_c2h; - /** @host_id - Host ID */ - uint8_t host_id; - /** @pasid - PASID */ - uint32_t pasid; - /** @pasid_en - PASID Enable */ - uint8_t pasid_en; - /** @vio_eop - Virtio End-of-packet */ - uint8_t vio_eop; - /** @sh_cmpt - Shared Completion Queue */ - uint8_t sh_cmpt; -}; - -/** - * struct qdma_indirect_intr_ctxt - indirect interrupt context config data - * structure - */ -struct qdma_indirect_intr_ctxt { - /** @baddr_4k -Base address of Interrupt Aggregation Ring */ - uint64_t baddr_4k; - /** @vec - Interrupt vector index in msix table */ - uint16_t vec; - /** @pidx - Producer Index */ - uint16_t pidx; - /** @valid - context valid */ - uint8_t valid; - /** @int_st -Interrupt State */ - uint8_t int_st; - /** @color - Color bit */ - uint8_t color; - /** @page_size - Interrupt Aggregation Ring size */ - uint8_t page_size; - /** @at - Address translation */ - uint8_t at; - /** @host_id - Host ID */ - uint8_t host_id; - /** @pasid - PASID */ - uint32_t pasid; - /** @pasid_en - PASID Enable */ - uint8_t pasid_en; - /** @func_id - Function ID */ - uint16_t func_id; -}; - -struct qdma_hw_version_info { - /** @rtl_version - RTL Version */ - enum qdma_rtl_version rtl_version; - /** @vivado_release - Vivado Release id */ - enum qdma_vivado_release_id vivado_release; - /** @versal_ip_state - Versal IP state */ - enum qdma_ip_type ip_type; - /** @device_type - Device Type */ - enum qdma_device_type device_type; - /** @qdma_rtl_version_str - RTL Version string*/ - char qdma_rtl_version_str[QDMA_HW_VERSION_STRING_LEN]; - /** @qdma_vivado_release_id_str - Vivado Release id string*/ - char qdma_vivado_release_id_str[QDMA_HW_VERSION_STRING_LEN]; - /** @qdma_device_type_str - Qdma device type string*/ - char qdma_device_type_str[QDMA_HW_VERSION_STRING_LEN]; - /** @qdma_versal_ip_state_str - Versal IP state string*/ - char qdma_ip_type_str[QDMA_HW_VERSION_STRING_LEN]; -}; - -#define CTXT_ENTRY_NAME_SZ 64 -struct qctx_entry { - char name[CTXT_ENTRY_NAME_SZ]; - uint32_t value; -}; - -/** - * @struct - qdma_descq_context - * @brief queue context information - */ -struct qdma_descq_context { - struct qdma_qid2vec qid2vec; - struct qdma_fmap_cfg fmap; - struct qdma_descq_sw_ctxt sw_ctxt; - struct qdma_descq_hw_ctxt hw_ctxt; - struct qdma_descq_credit_ctxt cr_ctxt; - struct qdma_descq_prefetch_ctxt pfetch_ctxt; - struct qdma_descq_cmpt_ctxt cmpt_ctxt; -}; - -/** - * struct qdma_q_pidx_reg_info - Software PIDX register fields - */ -struct qdma_q_pidx_reg_info { - /** @pidx - Producer Index */ - uint16_t pidx; - /** @irq_en - Interrupt enable */ - uint8_t irq_en; -}; - -/** - * struct qdma_q_intr_cidx_reg_info - Interrupt Ring CIDX register fields - */ -struct qdma_intr_cidx_reg_info { - /** @sw_cidx - Software Consumer Index */ - uint16_t sw_cidx; - /** @rng_idx - Ring Index of the Interrupt Aggregation ring */ - uint8_t rng_idx; -}; - -/** - * struct qdma_q_cmpt_cidx_reg_info - CMPT CIDX register fields - */ -struct qdma_q_cmpt_cidx_reg_info { - /** @wrb_cidx - CMPT Consumer Index */ - uint16_t wrb_cidx; - /** @counter_idx - Counter Threshold Index */ - uint8_t counter_idx; - /** @timer_idx - Timer Count Index */ - uint8_t timer_idx; - /** @trig_mode - Trigger mode */ - uint8_t trig_mode; - /** @wrb_en - Enable status descriptor for CMPT */ - uint8_t wrb_en; - /** @irq_en - Enable Interrupt for CMPT */ - uint8_t irq_en; -}; - - -/** - * struct qdma_csr_info - Global CSR info data structure - */ -struct qdma_csr_info { - /** @ringsz: ring size values */ - uint16_t ringsz[QDMA_GLOBAL_CSR_ARRAY_SZ]; - /** @bufsz: buffer size values */ - uint16_t bufsz[QDMA_GLOBAL_CSR_ARRAY_SZ]; - /** @timer_cnt: timer threshold values */ - uint8_t timer_cnt[QDMA_GLOBAL_CSR_ARRAY_SZ]; - /** @cnt_thres: counter threshold values */ - uint8_t cnt_thres[QDMA_GLOBAL_CSR_ARRAY_SZ]; - /** @wb_intvl: writeback interval */ - uint8_t wb_intvl; -}; - -#define QDMA_MAX_REGISTER_DUMP 14 - -/** - * struct qdma_reg_data - Structure to - * hold address value and pair - */ -struct qdma_reg_data { - /** @reg_addr: register address */ - uint32_t reg_addr; - /** @reg_val: register value */ - uint32_t reg_val; -}; - -/** - * enum qdma_hw_access_type - To hold hw access type - */ -enum qdma_hw_access_type { - QDMA_HW_ACCESS_READ, - QDMA_HW_ACCESS_WRITE, - QDMA_HW_ACCESS_CLEAR, - QDMA_HW_ACCESS_INVALIDATE, - QDMA_HW_ACCESS_MAX -}; - -/** - * enum qdma_global_csr_type - To hold global csr type - */ -enum qdma_global_csr_type { - QDMA_CSR_RING_SZ, - QDMA_CSR_TIMER_CNT, - QDMA_CSR_CNT_TH, - QDMA_CSR_BUF_SZ, - QDMA_CSR_MAX -}; - -/** - * enum status_type - To hold enable/disable status type - */ -enum status_type { - DISABLE = 0, - ENABLE = 1, -}; - -/** - * enum qdma_reg_read_type - Indicates reg read type - */ -enum qdma_reg_read_type { - /** @QDMA_REG_READ_PF_ONLY: Read the register for PFs only */ - QDMA_REG_READ_PF_ONLY, - /** @QDMA_REG_READ_VF_ONLY: Read the register for VFs only */ - QDMA_REG_READ_VF_ONLY, - /** @QDMA_REG_READ_PF_VF: Read the register for both PF and VF */ - QDMA_REG_READ_PF_VF, - /** @QDMA_REG_READ_MAX: Reg read enum max */ - QDMA_REG_READ_MAX -}; - -/** - * enum qdma_reg_read_groups - Indicates reg read groups - */ -enum qdma_reg_read_groups { - /** @QDMA_REG_READ_GROUP_1: Read the register from 0x000 to 0x288 */ - QDMA_REG_READ_GROUP_1, - /** @QDMA_REG_READ_GROUP_2: Read the register from 0x400 to 0xAFC */ - QDMA_REG_READ_GROUP_2, - /** @QDMA_REG_READ_GROUP_3: Read the register from 0xB00 to 0xE28 */ - QDMA_REG_READ_GROUP_3, - /** @QDMA_REG_READ_GROUP_4: Read the register Mailbox Registers */ - QDMA_REG_READ_GROUP_4, - /** @QDMA_REG_READ_GROUP_MAX: Reg read max groups */ - QDMA_REG_READ_GROUP_MAX -}; - -void qdma_write_csr_values(void *dev_hndl, uint32_t reg_offst, - uint32_t idx, uint32_t cnt, const uint32_t *values); - -void qdma_read_csr_values(void *dev_hndl, uint32_t reg_offst, - uint32_t idx, uint32_t cnt, uint32_t *values); - -int dump_reg(char *buf, int buf_sz, uint32_t raddr, - const char *rname, uint32_t rval); - -int hw_monitor_reg(void *dev_hndl, uint32_t reg, uint32_t mask, - uint32_t val, uint32_t interval_us, - uint32_t timeout_us); - -void qdma_memset(void *to, uint8_t val, uint32_t size); - -int qdma_acc_reg_dump_buf_len(void *dev_hndl, enum qdma_ip_type ip_type, - enum qdma_device_type device_type, int *buflen); - -int qdma_acc_reg_info_len(void *dev_hndl, enum qdma_ip_type ip_type, - enum qdma_device_type device_type, int *buflen, int *num_regs); - -int qdma_acc_context_buf_len(void *dev_hndl, enum qdma_ip_type ip_type, - enum qdma_device_type device_type, uint8_t st, - enum qdma_dev_q_type q_type, uint32_t *buflen); - -int qdma_acc_get_num_config_regs(void *dev_hndl, enum qdma_ip_type ip_type, - enum qdma_device_type device_type, uint32_t *num_regs); - -/* - * struct qdma_hw_access - Structure to hold HW access function pointers - */ -struct qdma_hw_access { - int (*qdma_set_default_global_csr)(void *dev_hndl); - int (*qdma_global_csr_conf)(void *dev_hndl, uint8_t index, - uint8_t count, uint32_t *csr_val, - enum qdma_global_csr_type csr_type, - enum qdma_hw_access_type access_type); - int (*qdma_global_writeback_interval_conf)(void *dev_hndl, - enum qdma_wrb_interval *wb_int, - enum qdma_hw_access_type access_type); - int (*qdma_init_ctxt_memory)(void *dev_hndl); - int (*qdma_qid2vec_conf)(void *dev_hndl, uint8_t c2h, uint16_t hw_qid, - struct qdma_qid2vec *ctxt, - enum qdma_hw_access_type access_type); - int (*qdma_fmap_conf)(void *dev_hndl, uint16_t func_id, - struct qdma_fmap_cfg *config, - enum qdma_hw_access_type access_type); - int (*qdma_sw_ctx_conf)(void *dev_hndl, uint8_t c2h, uint16_t hw_qid, - struct qdma_descq_sw_ctxt *ctxt, - enum qdma_hw_access_type access_type); - int (*qdma_pfetch_ctx_conf)(void *dev_hndl, uint16_t hw_qid, - struct qdma_descq_prefetch_ctxt *ctxt, - enum qdma_hw_access_type access_type); - int (*qdma_cmpt_ctx_conf)(void *dev_hndl, uint16_t hw_qid, - struct qdma_descq_cmpt_ctxt *ctxt, - enum qdma_hw_access_type access_type); - int (*qdma_hw_ctx_conf)(void *dev_hndl, uint8_t c2h, uint16_t hw_qid, - struct qdma_descq_hw_ctxt *ctxt, - enum qdma_hw_access_type access_type); - int (*qdma_credit_ctx_conf)(void *dev_hndl, uint8_t c2h, - uint16_t hw_qid, - struct qdma_descq_credit_ctxt *ctxt, - enum qdma_hw_access_type access_type); - int (*qdma_indirect_intr_ctx_conf)(void *dev_hndl, uint16_t ring_index, - struct qdma_indirect_intr_ctxt *ctxt, - enum qdma_hw_access_type access_type); - int (*qdma_queue_pidx_update)(void *dev_hndl, uint8_t is_vf, - uint16_t qid, - uint8_t is_c2h, - const struct qdma_q_pidx_reg_info *reg_info); - int (*qdma_queue_cmpt_cidx_read)(void *dev_hndl, uint8_t is_vf, - uint16_t qid, - struct qdma_q_cmpt_cidx_reg_info *reg_info); - int (*qdma_queue_cmpt_cidx_update)(void *dev_hndl, uint8_t is_vf, - uint16_t qid, - const struct qdma_q_cmpt_cidx_reg_info *reg_info); - int (*qdma_queue_intr_cidx_update)(void *dev_hndl, uint8_t is_vf, - uint16_t qid, - const struct qdma_intr_cidx_reg_info *reg_info); - int (*qdma_mm_channel_conf)(void *dev_hndl, uint8_t channel, - uint8_t is_c2h, uint8_t enable); - int (*qdma_get_user_bar)(void *dev_hndl, uint8_t is_vf, - uint16_t func_id, uint8_t *user_bar); - int (*qdma_get_function_number)(void *dev_hndl, uint16_t *func_id); - int (*qdma_get_version)(void *dev_hndl, uint8_t is_vf, - struct qdma_hw_version_info *version_info); - int (*qdma_get_device_attributes)(void *dev_hndl, - struct qdma_dev_attributes *dev_info); - int (*qdma_hw_error_intr_setup)(void *dev_hndl, uint16_t func_id, - uint8_t err_intr_index); - int (*qdma_hw_error_intr_rearm)(void *dev_hndl); - int (*qdma_hw_error_enable)(void *dev_hndl, - uint32_t err_idx); - const char *(*qdma_hw_get_error_name)(uint32_t err_idx); - int (*qdma_hw_error_process)(void *dev_hndl); - int (*qdma_dump_config_regs)(void *dev_hndl, uint8_t is_vf, char *buf, - uint32_t buflen); - int (*qdma_dump_reg_info)(void *dev_hndl, uint32_t reg_addr, - uint32_t num_regs, - char *buf, - uint32_t buflen); - int (*qdma_dump_queue_context)(void *dev_hndl, - uint8_t st, - enum qdma_dev_q_type q_type, - struct qdma_descq_context *ctxt_data, - char *buf, uint32_t buflen); - int (*qdma_read_dump_queue_context)(void *dev_hndl, - uint16_t func_id, - uint16_t qid_hw, - uint8_t st, - enum qdma_dev_q_type q_type, - char *buf, uint32_t buflen); - int (*qdma_dump_intr_context)(void *dev_hndl, - struct qdma_indirect_intr_ctxt *intr_ctx, - int ring_index, - char *buf, uint32_t buflen); - int (*qdma_is_legacy_intr_pend)(void *dev_hndl); - int (*qdma_clear_pend_legacy_intr)(void *dev_hndl); - int (*qdma_legacy_intr_conf)(void *dev_hndl, enum status_type enable); - int (*qdma_initiate_flr)(void *dev_hndl, uint8_t is_vf); - int (*qdma_is_flr_done)(void *dev_hndl, uint8_t is_vf, uint8_t *done); - int (*qdma_get_error_code)(int acc_err_code); - int (*qdma_read_reg_list)(void *dev_hndl, uint8_t is_vf, - uint16_t reg_rd_group, - uint16_t *total_regs, - struct qdma_reg_data *reg_list); - int (*qdma_dump_config_reg_list)(void *dev_hndl, - uint32_t num_regs, - struct qdma_reg_data *reg_list, - char *buf, uint32_t buflen); -#ifdef TANDEM_BOOT_SUPPORTED - int (*qdma_init_st_ctxt)(void *dev_hndl); -#endif - uint32_t mbox_base_pf; - uint32_t mbox_base_vf; - uint32_t qdma_max_errors; -}; - -/*****************************************************************************/ -/** - * qdma_hw_access_init() - Function to get the QDMA hardware - * access function pointers - * This function should be called once per device from - * device_open()/probe(). Caller shall allocate memory for - * qdma_hw_access structure and store pointer to it in their - * per device structure. Config BAR validation will be done - * inside this function - * - * @dev_hndl: device handle - * @is_vf: Whether PF or VF - * @hw_access: qdma_hw_access structure pointer. - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -int qdma_hw_access_init(void *dev_hndl, uint8_t is_vf, - struct qdma_hw_access *hw_access); - -/*****************************************************************************/ -/** - * qdma_acc_get_config_regs() - Function to get qdma config registers - * - * @dev_hndl: device handle - * @is_vf: Whether PF or VF - * @ip_type: QDMA IP Type - * @device_type:QDMA DEVICE Type - * @reg_data: pointer to register data to be filled - * - * Return: Length up-till the buffer is filled -success and < 0 - failure - *****************************************************************************/ -int qdma_acc_get_config_regs(void *dev_hndl, uint8_t is_vf, - enum qdma_ip_type ip_type, - enum qdma_device_type device_type, - uint32_t *reg_data); - -/*****************************************************************************/ -/** - * qdma_acc_dump_config_regs() - Function to get qdma config register dump in a - * buffer - * - * @dev_hndl: device handle - * @is_vf: Whether PF or VF - * @ip_type: QDMA IP Type - * @device_type:QDMA DEVICE Type - * @buf : pointer to buffer to be filled - * @buflen : Length of the buffer - * - * Return: Length up-till the buffer is filled -success and < 0 - failure - *****************************************************************************/ -int qdma_acc_dump_config_regs(void *dev_hndl, uint8_t is_vf, - enum qdma_ip_type ip_type, - enum qdma_device_type device_type, - char *buf, uint32_t buflen); - -/*****************************************************************************/ -/** - * qdma_acc_dump_reg_info() - Function to get qdma reg info in a buffer - * - * @dev_hndl: device handle - * @ip_type: QDMA IP Type - * @device_type:QDMA DEVICE Type - * @reg_addr: Register Address - * @num_regs: Number of Registers - * @buf : pointer to buffer to be filled - * @buflen : Length of the buffer - * - * Return: Length up-till the buffer is filled -success and < 0 - failure - *****************************************************************************/ -int qdma_acc_dump_reg_info(void *dev_hndl, enum qdma_ip_type ip_type, - enum qdma_device_type device_type, uint32_t reg_addr, - uint32_t num_regs, char *buf, uint32_t buflen); - -/*****************************************************************************/ -/** - * qdma_acc_dump_queue_context() - Function to dump qdma queue context data in a - * buffer where context information is already available in 'ctxt_data' - * structure pointer buffer - * - * @dev_hndl: device handle - * @ip_type: QDMA IP Type - * @device_type:QDMA DEVICE Type - * @st: ST or MM - * @q_type: Queue Type - * @ctxt_data: Context Data - * @buf : pointer to buffer to be filled - * @buflen : Length of the buffer - * - * Return: Length up-till the buffer is filled -success and < 0 - failure - *****************************************************************************/ -int qdma_acc_dump_queue_context(void *dev_hndl, - enum qdma_ip_type ip_type, - enum qdma_device_type device_type, - uint8_t st, - enum qdma_dev_q_type q_type, - struct qdma_descq_context *ctxt_data, - char *buf, uint32_t buflen); - -/*****************************************************************************/ -/** - * qdma_acc_read_dump_queue_context() - Function to read and dump the queue - * context in a buffer - * - * @dev_hndl: device handle - * @ip_type: QDMA IP Type - * @device_type:QDMA DEVICE Type - * @qid_hw: queue id - * @st: ST or MM - * @q_type: Queue Type - * @buf : pointer to buffer to be filled - * @buflen : Length of the buffer - * - * Return: Length up-till the buffer is filled -success and < 0 - failure - *****************************************************************************/ -int qdma_acc_read_dump_queue_context(void *dev_hndl, - enum qdma_ip_type ip_type, - enum qdma_device_type device_type, - uint16_t func_id, - uint16_t qid_hw, - uint8_t st, - enum qdma_dev_q_type q_type, - char *buf, uint32_t buflen); - - -/*****************************************************************************/ -/** - * qdma_acc_dump_config_reg_list() - Dump the registers - * - * @dev_hndl: device handle - * @ip_type: QDMA IP Type - * @device_type: QDMA DEVICE Type - * @total_regs : Max registers to read - * @reg_list : array of reg addr and reg values - * @buf : pointer to buffer to be filled - * @buflen : Length of the buffer - * - * Return: returns the platform specific error code - *****************************************************************************/ -int qdma_acc_dump_config_reg_list(void *dev_hndl, - enum qdma_ip_type ip_type, - enum qdma_device_type device_type, - uint32_t num_regs, - struct qdma_reg_data *reg_list, - char *buf, uint32_t buflen); - -/*****************************************************************************/ -/** - * qdma_get_error_code() - function to get the qdma access mapped - * error code - * - * @acc_err_code: qdma access error code - * - * Return: returns the platform specific error code - *****************************************************************************/ -int qdma_get_error_code(int acc_err_code); - -/*****************************************************************************/ -/** - * qdma_fetch_version_details() - Function to fetch the version details from the - * version register value - * - * @is_vf : Whether PF or VF - * @version_reg_val : Value of the version register - * @version_info : Pointer to store the version details. - * - * Return: Nothing - *****************************************************************************/ -void qdma_fetch_version_details(void *dev_hndl, uint8_t is_vf, - uint32_t version_reg_val, struct qdma_hw_version_info *version_info); - -#ifdef __cplusplus -} -#endif - -#endif /* QDMA_ACCESS_COMMON_H_ */ diff --git a/QDMA/DPDK/drivers/net/qdma/qdma_access/qdma_access_errors.h b/QDMA/DPDK/drivers/net/qdma/qdma_access/qdma_access_errors.h deleted file mode 100755 index 8eb2c582a..000000000 --- a/QDMA/DPDK/drivers/net/qdma/qdma_access/qdma_access_errors.h +++ /dev/null @@ -1,89 +0,0 @@ -/* - * Copyright (c) 2019-2022, Xilinx, Inc. All rights reserved. - * Copyright (c) 2022, Advanced Micro Devices, Inc. All rights reserved. - * - * BSD LICENSE - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * * Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#ifndef __QDMA_ACCESS_ERRORS_H_ -#define __QDMA_ACCESS_ERRORS_H_ - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * DOC: QDMA common library error codes definitions - * - * Header file *qdma_access_errors.h* defines error codes for common library - */ - -struct err_code_map { - int acc_err_code; - int err_code; -}; - -#define QDMA_HW_ERR_NOT_DETECTED 1 - -enum qdma_access_error_codes { - QDMA_SUCCESS = 0, - QDMA_ERR_INV_PARAM, - QDMA_ERR_NO_MEM, - QDMA_ERR_HWACC_BUSY_TIMEOUT, - QDMA_ERR_HWACC_INV_CONFIG_BAR, - QDMA_ERR_HWACC_NO_PEND_LEGCY_INTR, - QDMA_ERR_HWACC_BAR_NOT_FOUND, - QDMA_ERR_HWACC_FEATURE_NOT_SUPPORTED, /* 7 */ - - QDMA_ERR_RM_RES_EXISTS, /* 8 */ - QDMA_ERR_RM_RES_NOT_EXISTS, - QDMA_ERR_RM_DEV_EXISTS, - QDMA_ERR_RM_DEV_NOT_EXISTS, - QDMA_ERR_RM_NO_QUEUES_LEFT, - QDMA_ERR_RM_QMAX_CONF_REJECTED, /* 13 */ - - QDMA_ERR_MBOX_FMAP_WR_FAILED, /* 14 */ - QDMA_ERR_MBOX_NUM_QUEUES, - QDMA_ERR_MBOX_INV_QID, - QDMA_ERR_MBOX_INV_RINGSZ, - QDMA_ERR_MBOX_INV_BUFSZ, - QDMA_ERR_MBOX_INV_CNTR_TH, - QDMA_ERR_MBOX_INV_TMR_TH, - QDMA_ERR_MBOX_INV_MSG, - QDMA_ERR_MBOX_SEND_BUSY, - QDMA_ERR_MBOX_NO_MSG_IN, - QDMA_ERR_MBOX_REG_READ_FAILED, - QDMA_ERR_MBOX_ALL_ZERO_MSG, /* 25 */ -}; - -#ifdef __cplusplus -} -#endif - -#endif /* __QDMA_ACCESS_ERRORS_H_ */ diff --git a/QDMA/DPDK/drivers/net/qdma/qdma_access/qdma_access_export.h b/QDMA/DPDK/drivers/net/qdma/qdma_access/qdma_access_export.h deleted file mode 100755 index dba818585..000000000 --- a/QDMA/DPDK/drivers/net/qdma/qdma_access/qdma_access_export.h +++ /dev/null @@ -1,278 +0,0 @@ -/* - * Copyright (c) 2019-2022, Xilinx, Inc. All rights reserved. - * Copyright (c) 2022, Advanced Micro Devices, Inc. All rights reserved. - * - * BSD LICENSE - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * * Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#ifndef __QDMA_ACCESS_EXPORT_H_ -#define __QDMA_ACCESS_EXPORT_H_ - -#ifdef __cplusplus -extern "C" { -#endif - -#include "qdma_platform_env.h" - -/** QDMA Global CSR array size */ -#define QDMA_GLOBAL_CSR_ARRAY_SZ 16 - -/** - * struct qdma_dev_attributes - QDMA device attributes - */ -struct qdma_dev_attributes { - /** @num_pfs - Num of PFs*/ - uint8_t num_pfs; - /** @num_qs - Num of Queues */ - uint16_t num_qs; - /** @flr_present - FLR resent or not? */ - uint8_t flr_present:1; - /** @st_en - ST mode supported or not? */ - uint8_t st_en:1; - /** @mm_en - MM mode supported or not? */ - uint8_t mm_en:1; - /** @mm_cmpt_en - MM with Completions supported or not? */ - uint8_t mm_cmpt_en:1; - /** @mailbox_en - Mailbox supported or not? */ - uint8_t mailbox_en:1; - /** @debug_mode - Debug mode is enabled/disabled for IP */ - uint8_t debug_mode:1; - /** @desc_eng_mode - Descriptor Engine mode: - * Internal only/Bypass only/Internal & Bypass - */ - uint8_t desc_eng_mode:2; - /** @mm_channel_max - Num of MM channels */ - uint8_t mm_channel_max; - - /** Below are the list of HW features which are populated by qdma_access - * based on RTL version - */ - /** @qid2vec_ctx - To indicate support of qid2vec context */ - uint8_t qid2vec_ctx:1; - /** @cmpt_ovf_chk_dis - To indicate support of overflow check - * disable in CMPT ring - */ - uint8_t cmpt_ovf_chk_dis:1; - /** @mailbox_intr - To indicate support of mailbox interrupt */ - uint8_t mailbox_intr:1; - /** @sw_desc_64b - To indicate support of 64 bytes C2H/H2C - * descriptor format - */ - uint8_t sw_desc_64b:1; - /** @cmpt_desc_64b - To indicate support of 64 bytes CMPT - * descriptor format - */ - uint8_t cmpt_desc_64b:1; - /** @dynamic_bar - To indicate support of dynamic bar detection */ - uint8_t dynamic_bar:1; - /** @legacy_intr - To indicate support of legacy interrupt */ - uint8_t legacy_intr:1; - /** @cmpt_trig_count_timer - To indicate support of counter + timer - * trigger mode - */ - uint8_t cmpt_trig_count_timer:1; -}; - -/** qdma_dev_attributes structure size */ -#define QDMA_DEV_ATTR_STRUCT_SIZE (sizeof(struct qdma_dev_attributes)) - -/** global_csr_conf structure size */ -#define QDMA_DEV_GLOBAL_CSR_STRUCT_SIZE (sizeof(struct global_csr_conf)) - -/** - * enum qdma_dev_type - To hold qdma device type - */ -enum qdma_dev_type { - QDMA_DEV_PF, - QDMA_DEV_VF -}; - -/** - * enum qdma_dev_q_type: Q type - */ -enum qdma_dev_q_type { - /** @QDMA_DEV_Q_TYPE_H2C: H2C Q */ - QDMA_DEV_Q_TYPE_H2C, - /** @QDMA_DEV_Q_TYPE_C2H: C2H Q */ - QDMA_DEV_Q_TYPE_C2H, - /** @QDMA_DEV_Q_TYPE_CMPT: CMPT Q */ - QDMA_DEV_Q_TYPE_CMPT, - /** @QDMA_DEV_Q_TYPE_MAX: Total Q types */ - QDMA_DEV_Q_TYPE_MAX -}; - -/** - * @enum qdma_desc_size - QDMA queue descriptor size - */ -enum qdma_desc_size { - /** @QDMA_DESC_SIZE_8B - 8 byte descriptor */ - QDMA_DESC_SIZE_8B, - /** @QDMA_DESC_SIZE_16B - 16 byte descriptor */ - QDMA_DESC_SIZE_16B, - /** @QDMA_DESC_SIZE_32B - 32 byte descriptor */ - QDMA_DESC_SIZE_32B, - /** @QDMA_DESC_SIZE_64B - 64 byte descriptor */ - QDMA_DESC_SIZE_64B -}; - -/** - * @enum qdma_cmpt_update_trig_mode - Interrupt and Completion status write - * trigger mode - */ -enum qdma_cmpt_update_trig_mode { - /** @QDMA_CMPT_UPDATE_TRIG_MODE_DIS - disabled */ - QDMA_CMPT_UPDATE_TRIG_MODE_DIS, - /** @QDMA_CMPT_UPDATE_TRIG_MODE_EVERY - every */ - QDMA_CMPT_UPDATE_TRIG_MODE_EVERY, - /** @QDMA_CMPT_UPDATE_TRIG_MODE_USR_CNT - user counter */ - QDMA_CMPT_UPDATE_TRIG_MODE_USR_CNT, - /** @QDMA_CMPT_UPDATE_TRIG_MODE_USR - user */ - QDMA_CMPT_UPDATE_TRIG_MODE_USR, - /** @QDMA_CMPT_UPDATE_TRIG_MODE_USR_TMR - user timer */ - QDMA_CMPT_UPDATE_TRIG_MODE_USR_TMR, - /** @QDMA_CMPT_UPDATE_TRIG_MODE_TMR_CNTR - timer + counter combo */ - QDMA_CMPT_UPDATE_TRIG_MODE_TMR_CNTR -}; - - -/** - * @enum qdma_indirect_intr_ring_size - Indirect interrupt ring size - */ -enum qdma_indirect_intr_ring_size { - /** @QDMA_INDIRECT_INTR_RING_SIZE_4KB - Accommodates 512 entries */ - QDMA_INDIRECT_INTR_RING_SIZE_4KB, - /** @QDMA_INDIRECT_INTR_RING_SIZE_8KB - Accommodates 1024 entries */ - QDMA_INDIRECT_INTR_RING_SIZE_8KB, - /** @QDMA_INDIRECT_INTR_RING_SIZE_12KB - Accommodates 1536 entries */ - QDMA_INDIRECT_INTR_RING_SIZE_12KB, - /** @QDMA_INDIRECT_INTR_RING_SIZE_16KB - Accommodates 2048 entries */ - QDMA_INDIRECT_INTR_RING_SIZE_16KB, - /** @QDMA_INDIRECT_INTR_RING_SIZE_20KB - Accommodates 2560 entries */ - QDMA_INDIRECT_INTR_RING_SIZE_20KB, - /** @QDMA_INDIRECT_INTR_RING_SIZE_24KB - Accommodates 3072 entries */ - QDMA_INDIRECT_INTR_RING_SIZE_24KB, - /** @QDMA_INDIRECT_INTR_RING_SIZE_28KB - Accommodates 3584 entries */ - QDMA_INDIRECT_INTR_RING_SIZE_28KB, - /** @QDMA_INDIRECT_INTR_RING_SIZE_32KB - Accommodates 4096 entries */ - QDMA_INDIRECT_INTR_RING_SIZE_32KB -}; - -/** - * @enum qdma_wrb_interval - writeback update interval - */ -enum qdma_wrb_interval { - /** @QDMA_WRB_INTERVAL_4 - writeback update interval of 4 */ - QDMA_WRB_INTERVAL_4, - /** @QDMA_WRB_INTERVAL_8 - writeback update interval of 8 */ - QDMA_WRB_INTERVAL_8, - /** @QDMA_WRB_INTERVAL_16 - writeback update interval of 16 */ - QDMA_WRB_INTERVAL_16, - /** @QDMA_WRB_INTERVAL_32 - writeback update interval of 32 */ - QDMA_WRB_INTERVAL_32, - /** @QDMA_WRB_INTERVAL_64 - writeback update interval of 64 */ - QDMA_WRB_INTERVAL_64, - /** @QDMA_WRB_INTERVAL_128 - writeback update interval of 128 */ - QDMA_WRB_INTERVAL_128, - /** @QDMA_WRB_INTERVAL_256 - writeback update interval of 256 */ - QDMA_WRB_INTERVAL_256, - /** @QDMA_WRB_INTERVAL_512 - writeback update interval of 512 */ - QDMA_WRB_INTERVAL_512, - /** @QDMA_NUM_WRB_INTERVALS - total number of writeback intervals */ - QDMA_NUM_WRB_INTERVALS -}; - -enum qdma_rtl_version { - /** @QDMA_RTL_BASE - RTL Base */ - QDMA_RTL_BASE, - /** @QDMA_RTL_PATCH - RTL Patch */ - QDMA_RTL_PATCH, - /** @QDMA_RTL_NONE - Not a valid RTL version */ - QDMA_RTL_NONE, -}; - -enum qdma_vivado_release_id { - /** @QDMA_VIVADO_2018_3 - Vivado version 2018.3 */ - QDMA_VIVADO_2018_3, - /** @QDMA_VIVADO_2019_1 - Vivado version 2019.1 */ - QDMA_VIVADO_2019_1, - /** @QDMA_VIVADO_2019_2 - Vivado version 2019.2 */ - QDMA_VIVADO_2019_2, - /** @QDMA_VIVADO_2020_1 - Vivado version 2020.1 */ - QDMA_VIVADO_2020_1, - /** @QDMA_VIVADO_2020_2 - Vivado version 2020.2 */ - QDMA_VIVADO_2020_2, - /** @QDMA_VIVADO_2021_1 - Vivado version 2021.1 */ - QDMA_VIVADO_2021_1, - /** @QDMA_VIVADO_2022_1 - Vivado version 2022.1 */ - QDMA_VIVADO_2022_1, - /** @QDMA_VIVADO_NONE - Not a valid Vivado version*/ - QDMA_VIVADO_NONE -}; - -enum qdma_ip_type { - /** @QDMA_VERSAL_HARD_IP - Hard IP */ - QDMA_VERSAL_HARD_IP, - /** @QDMA_VERSAL_SOFT_IP - Soft IP */ - QDMA_VERSAL_SOFT_IP, - /** @QDMA_SOFT_IP - Hard IP */ - QDMA_SOFT_IP, - /** @EQDMA_SOFT_IP - Soft IP */ - EQDMA_SOFT_IP, - /** @QDMA_VERSAL_NONE - Not versal device */ - QDMA_NONE_IP -}; - - -enum qdma_device_type { - /** @QDMA_DEVICE_SOFT - UltraScale+ IP's */ - QDMA_DEVICE_SOFT, - /** @QDMA_DEVICE_VERSAL_CPM4 -VERSAL IP */ - QDMA_DEVICE_VERSAL_CPM4, - /** @QDMA_DEVICE_VERSAL_CPM5 -VERSAL IP */ - QDMA_DEVICE_VERSAL_CPM5, - /** @QDMA_DEVICE_NONE - Not a valid device */ - QDMA_DEVICE_NONE -}; - -enum qdma_desc_eng_mode { - /** @QDMA_DESC_ENG_INTERNAL_BYPASS - Internal and Bypass mode */ - QDMA_DESC_ENG_INTERNAL_BYPASS, - /** @QDMA_DESC_ENG_BYPASS_ONLY - Only Bypass mode */ - QDMA_DESC_ENG_BYPASS_ONLY, - /** @QDMA_DESC_ENG_INTERNAL_ONLY - Only Internal mode */ - QDMA_DESC_ENG_INTERNAL_ONLY, - /** @QDMA_DESC_ENG_MODE_MAX - Max of desc engine modes */ - QDMA_DESC_ENG_MODE_MAX -}; - -#ifdef __cplusplus -} -#endif - -#endif /* __QDMA_ACCESS_EXPORT_H_ */ diff --git a/QDMA/DPDK/drivers/net/qdma/qdma_access/qdma_access_version.h b/QDMA/DPDK/drivers/net/qdma/qdma_access/qdma_access_version.h deleted file mode 100755 index 652a5550f..000000000 --- a/QDMA/DPDK/drivers/net/qdma/qdma_access/qdma_access_version.h +++ /dev/null @@ -1,53 +0,0 @@ -/* - * Copyright (c) 2019-2022, Xilinx, Inc. All rights reserved. - * Copyright (c) 2022-2023, Advanced Micro Devices, Inc. All rights reserved. - * - * BSD LICENSE - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * * Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#ifndef __QDMA_ACCESS_VERSION_H_ -#define __QDMA_ACCESS_VERSION_H_ - - -#define QDMA_VERSION_MAJOR 2023 -#define QDMA_VERSION_MINOR 2 -#define QDMA_VERSION_PATCH 1 - -#define QDMA_VERSION_STR \ - __stringify(QDMA_VERSION_MAJOR) "." \ - __stringify(QDMA_VERSION_MINOR) "." \ - __stringify(QDMA_VERSION_PATCH) - -#define QDMA_VERSION \ - ((QDMA_VERSION_MAJOR)*1000 + \ - (QDMA_VERSION_MINOR)*100 + \ - QDMA_VERSION_PATCH) - - -#endif /* __QDMA_ACCESS_VERSION_H_ */ diff --git a/QDMA/DPDK/drivers/net/qdma/qdma_access/qdma_cpm4_access/qdma_cpm4_access.c b/QDMA/DPDK/drivers/net/qdma/qdma_access/qdma_cpm4_access/qdma_cpm4_access.c deleted file mode 100755 index b70e924e9..000000000 --- a/QDMA/DPDK/drivers/net/qdma/qdma_access/qdma_cpm4_access/qdma_cpm4_access.c +++ /dev/null @@ -1,6071 +0,0 @@ -/* - * Copyright (c) 2019-2022, Xilinx, Inc. All rights reserved. - * Copyright (c) 2022, Advanced Micro Devices, Inc. All rights reserved. - * - * BSD LICENSE - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * * Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include "qdma_cpm4_access.h" -#include "qdma_cpm4_reg.h" -#include "qdma_reg_dump.h" - -#ifdef ENABLE_WPP_TRACING -#include "qdma_cpm4_access.tmh" -#endif - -/** QDMA CPM4 Hard Context array size */ -#define QDMA_CPM4_SW_CONTEXT_NUM_WORDS 4 -#define QDMA_CPM4_CMPT_CONTEXT_NUM_WORDS 4 -#define QDMA_CPM4_QID2VEC_CONTEXT_NUM_WORDS 1 -#define QDMA_CPM4_HW_CONTEXT_NUM_WORDS 2 -#define QDMA_CPM4_CR_CONTEXT_NUM_WORDS 1 -#define QDMA_CPM4_IND_INTR_CONTEXT_NUM_WORDS 3 -#define QDMA_CPM4_PFETCH_CONTEXT_NUM_WORDS 2 - -#define QDMA_CPM4_VF_USER_BAR_ID 2 - -#define QDMA_CPM4_REG_GROUP_1_START_ADDR 0x000 -#define QDMA_CPM4_REG_GROUP_2_START_ADDR 0x400 -#define QDMA_CPM4_REG_GROUP_3_START_ADDR 0xB00 -#define QDMA_CPM4_REG_GROUP_4_START_ADDR 0x1014 - -#define QDMA_CPM4_REG_TRQ_SEL_FMAP_STEP 4 - -#define QDMA_CPM4_IND_CTXT_DATA_NUM_REGS 4 - -#define QDMA_CPM4_TOTAL_LEAF_ERROR_AGGREGATORS 7 -#define QDMA_CPM4_GLBL_TRQ_ERR_ALL_MASK 0XB3 -#define QDMA_CPM4_GLBL_DSC_ERR_ALL_MASK 0X1F9037E -#define QDMA_CPM4_C2H_ERR_ALL_MASK 0X3F6DF -#define QDMA_CPM4_C2H_FATAL_ERR_ALL_MASK 0X1FDF1B -#define QDMA_CPM4_H2C_ERR_ALL_MASK 0X3F -#define QDMA_CPM4_SBE_ERR_ALL_MASK 0XFFFFFFFF -#define QDMA_CPM4_DBE_ERR_ALL_MASK 0XFFFFFFFF - -#define QDMA_CPM4_OFFSET_DMAP_SEL_INT_CIDX 0x6400 -#define QDMA_CPM4_OFFSET_DMAP_SEL_H2C_DSC_PIDX 0x6404 -#define QDMA_CPM4_OFFSET_DMAP_SEL_C2H_DSC_PIDX 0x6408 -#define QDMA_CPM4_OFFSET_DMAP_SEL_CMPT_CIDX 0x640C - -#define QDMA_CPM4_OFFSET_VF_DMAP_SEL_INT_CIDX 0x3000 -#define QDMA_CPM4_OFFSET_VF_DMAP_SEL_H2C_DSC_PIDX 0x3004 -#define QDMA_CPM4_OFFSET_VF_DMAP_SEL_C2H_DSC_PIDX 0x3008 -#define QDMA_CPM4_OFFSET_VF_DMAP_SEL_CMPT_CIDX 0x300C - -#define QDMA_CPM4_DMA_SEL_INT_SW_CIDX_MASK GENMASK(15, 0) -#define QDMA_CPM4_DMA_SEL_INT_RING_IDX_MASK GENMASK(23, 16) -#define QDMA_CPM4_DMA_SEL_DESC_PIDX_MASK GENMASK(15, 0) -#define QDMA_CPM4_DMA_SEL_IRQ_EN_MASK BIT(16) -#define QDMA_CPM4_DMAP_SEL_CMPT_IRQ_EN_MASK BIT(28) -#define QDMA_CPM4_DMAP_SEL_CMPT_STS_DESC_EN_MASK BIT(27) -#define QDMA_CPM4_DMAP_SEL_CMPT_TRG_MODE_MASK GENMASK(26, 24) -#define QDMA_CPM4_DMAP_SEL_CMPT_TMR_CNT_MASK GENMASK(23, 20) -#define QDMA_CPM4_DMAP_SEL_CMPT_CNT_THRESH_MASK GENMASK(19, 16) -#define QDMA_CPM4_DMAP_SEL_CMPT_WRB_CIDX_MASK GENMASK(15, 0) -#define QDMA_CPM4_INTR_CTXT_BADDR_GET_H_MASK GENMASK_ULL(63, 35) -#define QDMA_CPM4_INTR_CTXT_BADDR_GET_L_MASK GENMASK_ULL(34, 12) -#define QDMA_CPM4_COMPL_CTXT_BADDR_GET_H_MASK GENMASK_ULL(63, 42) -#define QDMA_CPM4_COMPL_CTXT_BADDR_GET_M_MASK GENMASK_ULL(41, 10) -#define QDMA_CPM4_COMPL_CTXT_BADDR_GET_L_MASK GENMASK_ULL(9, 6) -#define QDMA_CPM4_COMPL_CTXT_PIDX_GET_H_MASK GENMASK(15, 8) -#define QDMA_CPM4_COMPL_CTXT_PIDX_GET_L_MASK GENMASK(7, 0) -#define QDMA_CPM4_QID2VEC_H2C_VECTOR GENMASK(16, 9) -#define QDMA_CPM4_QID2VEC_H2C_COAL_EN BIT(17) - -#define QDMA_CPM4_DEFAULT_PFCH_STOP_THRESH 256 - -static void qdma_cpm4_hw_st_h2c_err_process(void *dev_hndl); -static void qdma_cpm4_hw_st_c2h_err_process(void *dev_hndl); -static void qdma_cpm4_hw_desc_err_process(void *dev_hndl); -static void qdma_cpm4_hw_trq_err_process(void *dev_hndl); -static void qdma_cpm4_hw_ram_sbe_err_process(void *dev_hndl); -static void qdma_cpm4_hw_ram_dbe_err_process(void *dev_hndl); - -static struct qdma_cpm4_hw_err_info - qdma_cpm4_err_info[QDMA_CPM4_ERRS_ALL] = { - /* Descriptor errors */ - { - QDMA_CPM4_DSC_ERR_POISON, - "Poison error", - QDMA_CPM4_GLBL_DSC_ERR_MSK_ADDR, - QDMA_CPM4_GLBL_DSC_ERR_STS_ADDR, - GLBL_DSC_ERR_STS_POISON_MASK, - GLBL_ERR_STAT_ERR_DSC_MASK, - &qdma_cpm4_hw_desc_err_process - }, - { - QDMA_CPM4_DSC_ERR_UR_CA, - "Unsupported request or completer aborted error", - QDMA_CPM4_GLBL_DSC_ERR_MSK_ADDR, - QDMA_CPM4_GLBL_DSC_ERR_STS_ADDR, - GLBL_DSC_ERR_STS_UR_CA_MASK, - GLBL_ERR_STAT_ERR_DSC_MASK, - &qdma_cpm4_hw_desc_err_process - }, - { - QDMA_CPM4_DSC_ERR_PARAM, - "Parameter mismatch error", - QDMA_CPM4_GLBL_DSC_ERR_MSK_ADDR, - QDMA_CPM4_GLBL_DSC_ERR_STS_ADDR, - GLBL_DSC_ERR_STS_PARAM_MASK, - GLBL_ERR_STAT_ERR_DSC_MASK, - &qdma_cpm4_hw_desc_err_process - }, - { - QDMA_CPM4_DSC_ERR_ADDR, - "Address mismatch error", - QDMA_CPM4_GLBL_DSC_ERR_MSK_ADDR, - QDMA_CPM4_GLBL_DSC_ERR_STS_ADDR, - GLBL_DSC_ERR_STS_ADDR_MASK, - GLBL_ERR_STAT_ERR_DSC_MASK, - &qdma_cpm4_hw_desc_err_process - }, - { - QDMA_CPM4_DSC_ERR_TAG, - "Unexpected tag error", - QDMA_CPM4_GLBL_DSC_ERR_MSK_ADDR, - QDMA_CPM4_GLBL_DSC_ERR_STS_ADDR, - GLBL_DSC_ERR_STS_TAG_MASK, - GLBL_ERR_STAT_ERR_DSC_MASK, - &qdma_cpm4_hw_desc_err_process - }, - { - QDMA_CPM4_DSC_ERR_FLR, - "FLR error", - QDMA_CPM4_GLBL_DSC_ERR_MSK_ADDR, - QDMA_CPM4_GLBL_DSC_ERR_STS_ADDR, - GLBL_DSC_ERR_STS_FLR_MASK, - GLBL_ERR_STAT_ERR_DSC_MASK, - &qdma_cpm4_hw_desc_err_process - }, - { - QDMA_CPM4_DSC_ERR_TIMEOUT, - "Timed out error", - QDMA_CPM4_GLBL_DSC_ERR_MSK_ADDR, - QDMA_CPM4_GLBL_DSC_ERR_STS_ADDR, - GLBL_DSC_ERR_STS_TIMEOUT_MASK, - GLBL_ERR_STAT_ERR_DSC_MASK, - &qdma_cpm4_hw_desc_err_process - }, - { - QDMA_CPM4_DSC_ERR_DAT_POISON, - "Poison data error", - QDMA_CPM4_GLBL_DSC_ERR_MSK_ADDR, - QDMA_CPM4_GLBL_DSC_ERR_STS_ADDR, - GLBL_DSC_ERR_STS_DAT_POISON_MASK, - GLBL_ERR_STAT_ERR_DSC_MASK, - &qdma_cpm4_hw_desc_err_process - }, - { - QDMA_CPM4_DSC_ERR_FLR_CANCEL, - "Descriptor fetch cancelled due to FLR error", - QDMA_CPM4_GLBL_DSC_ERR_MSK_ADDR, - QDMA_CPM4_GLBL_DSC_ERR_STS_ADDR, - GLBL_DSC_ERR_STS_FLR_CANCEL_MASK, - GLBL_ERR_STAT_ERR_DSC_MASK, - &qdma_cpm4_hw_desc_err_process - }, - { - QDMA_CPM4_DSC_ERR_DMA, - "DMA engine error", - QDMA_CPM4_GLBL_DSC_ERR_MSK_ADDR, - QDMA_CPM4_GLBL_DSC_ERR_STS_ADDR, - GLBL_DSC_ERR_STS_DMA_MASK, - GLBL_ERR_STAT_ERR_DSC_MASK, - &qdma_cpm4_hw_desc_err_process - }, - { - QDMA_CPM4_DSC_ERR_DSC, - "Invalid PIDX update error", - QDMA_CPM4_GLBL_DSC_ERR_MSK_ADDR, - QDMA_CPM4_GLBL_DSC_ERR_STS_ADDR, - GLBL_DSC_ERR_STS_DSC_MASK, - GLBL_ERR_STAT_ERR_DSC_MASK, - &qdma_cpm4_hw_desc_err_process - }, - { - QDMA_CPM4_DSC_ERR_RQ_CANCEL, - "Descriptor fetch cancelled due to disable register status error", - QDMA_CPM4_GLBL_DSC_ERR_MSK_ADDR, - QDMA_CPM4_GLBL_DSC_ERR_STS_ADDR, - GLBL_DSC_ERR_STS_RQ_CANCEL_MASK, - GLBL_ERR_STAT_ERR_DSC_MASK, - &qdma_cpm4_hw_desc_err_process - }, - { - QDMA_CPM4_DSC_ERR_DBE, - "UNC_ERR_RAM_DBE error", - QDMA_CPM4_GLBL_DSC_ERR_MSK_ADDR, - QDMA_CPM4_GLBL_DSC_ERR_STS_ADDR, - GLBL_DSC_ERR_STS_DBE_MASK, - GLBL_ERR_STAT_ERR_DSC_MASK, - &qdma_cpm4_hw_desc_err_process - }, - { - QDMA_CPM4_DSC_ERR_SBE, - "UNC_ERR_RAM_SBE error", - QDMA_CPM4_GLBL_DSC_ERR_MSK_ADDR, - QDMA_CPM4_GLBL_DSC_ERR_STS_ADDR, - GLBL_DSC_ERR_STS_SBE_MASK, - GLBL_ERR_STAT_ERR_DSC_MASK, - &qdma_cpm4_hw_desc_err_process - }, - { - QDMA_CPM4_DSC_ERR_ALL, - "All Descriptor errors", - QDMA_CPM4_GLBL_DSC_ERR_MSK_ADDR, - QDMA_CPM4_GLBL_DSC_ERR_STS_ADDR, - QDMA_CPM4_DBE_ERR_ALL_MASK, - GLBL_ERR_STAT_ERR_DSC_MASK, - &qdma_cpm4_hw_desc_err_process - }, - - /* TRQ errors */ - { - QDMA_CPM4_TRQ_ERR_UNMAPPED, - "Access targeted unmapped register space via CSR pathway error", - QDMA_CPM4_GLBL_TRQ_ERR_MSK_ADDR, - QDMA_CPM4_GLBL_TRQ_ERR_STS_ADDR, - GLBL_TRQ_ERR_STS_UNMAPPED_MASK, - GLBL_ERR_STAT_ERR_TRQ_MASK, - &qdma_cpm4_hw_trq_err_process - }, - { - QDMA_CPM4_TRQ_ERR_QID_RANGE, - "Qid range error", - QDMA_CPM4_GLBL_TRQ_ERR_MSK_ADDR, - QDMA_CPM4_GLBL_TRQ_ERR_STS_ADDR, - GLBL_TRQ_ERR_STS_QID_RANGE_MASK, - GLBL_ERR_STAT_ERR_TRQ_MASK, - &qdma_cpm4_hw_trq_err_process - }, - { - QDMA_CPM4_TRQ_ERR_VF_ACCESS_ERR, - "VF attempted to access Global register space or Function map", - QDMA_CPM4_GLBL_TRQ_ERR_MSK_ADDR, - QDMA_CPM4_GLBL_TRQ_ERR_STS_ADDR, - GLBL_TRQ_ERR_STS_VF_ACCESS_ERR_MASK, - GLBL_ERR_STAT_ERR_TRQ_MASK, - &qdma_cpm4_hw_trq_err_process - }, - { - QDMA_CPM4_TRQ_ERR_TCP_TIMEOUT, - "Timeout on request to dma internal csr register", - QDMA_CPM4_GLBL_TRQ_ERR_MSK_ADDR, - QDMA_CPM4_GLBL_TRQ_ERR_STS_ADDR, - GLBL_TRQ_ERR_STS_TCP_TIMEOUT_MASK, - GLBL_ERR_STAT_ERR_TRQ_MASK, - &qdma_cpm4_hw_trq_err_process - }, - { - QDMA_CPM4_TRQ_ERR_ALL, - "All TRQ errors", - QDMA_CPM4_GLBL_TRQ_ERR_MSK_ADDR, - QDMA_CPM4_GLBL_TRQ_ERR_STS_ADDR, - QDMA_CPM4_GLBL_TRQ_ERR_ALL_MASK, - GLBL_ERR_STAT_ERR_TRQ_MASK, - &qdma_cpm4_hw_trq_err_process - }, - - /* C2H Errors*/ - { - QDMA_CPM4_ST_C2H_ERR_MTY_MISMATCH, - "MTY mismatch error", - QDMA_CPM4_C2H_ERR_MASK_ADDR, - QDMA_CPM4_C2H_ERR_STAT_ADDR, - C2H_ERR_STAT_MTY_MISMATCH_MASK, - GLBL_ERR_STAT_ERR_C2H_ST_MASK, - &qdma_cpm4_hw_st_c2h_err_process - }, - { - QDMA_CPM4_ST_C2H_ERR_LEN_MISMATCH, - "Packet length mismatch error", - QDMA_CPM4_C2H_ERR_MASK_ADDR, - QDMA_CPM4_C2H_ERR_STAT_ADDR, - C2H_ERR_STAT_LEN_MISMATCH_MASK, - GLBL_ERR_STAT_ERR_C2H_ST_MASK, - &qdma_cpm4_hw_st_c2h_err_process - }, - { - QDMA_CPM4_ST_C2H_ERR_QID_MISMATCH, - "Qid mismatch error", - QDMA_CPM4_C2H_ERR_MASK_ADDR, - QDMA_CPM4_C2H_ERR_STAT_ADDR, - C2H_ERR_STAT_QID_MISMATCH_MASK, - GLBL_ERR_STAT_ERR_C2H_ST_MASK, - &qdma_cpm4_hw_st_c2h_err_process - }, - { - QDMA_CPM4_ST_C2H_ERR_DESC_RSP_ERR, - "Descriptor error bit set", - QDMA_CPM4_C2H_ERR_MASK_ADDR, - QDMA_CPM4_C2H_ERR_STAT_ADDR, - C2H_ERR_STAT_DESC_RSP_ERR_MASK, - GLBL_ERR_STAT_ERR_C2H_ST_MASK, - &qdma_cpm4_hw_st_c2h_err_process - }, - { - QDMA_CPM4_ST_C2H_ERR_ENG_WPL_DATA_PAR_ERR, - "Data parity error", - QDMA_CPM4_C2H_ERR_MASK_ADDR, - QDMA_CPM4_C2H_ERR_STAT_ADDR, - C2H_ERR_STAT_ENG_WPL_DATA_PAR_ERR_MASK, - GLBL_ERR_STAT_ERR_C2H_ST_MASK, - &qdma_cpm4_hw_st_c2h_err_process - }, - { - QDMA_CPM4_ST_C2H_ERR_MSI_INT_FAIL, - "MSI got a fail response error", - QDMA_CPM4_C2H_ERR_MASK_ADDR, - QDMA_CPM4_C2H_ERR_STAT_ADDR, - C2H_ERR_STAT_MSI_INT_FAIL_MASK, - GLBL_ERR_STAT_ERR_C2H_ST_MASK, - &qdma_cpm4_hw_st_c2h_err_process - }, - { - QDMA_CPM4_ST_C2H_ERR_ERR_DESC_CNT, - "Descriptor count error", - QDMA_CPM4_C2H_ERR_MASK_ADDR, - QDMA_CPM4_C2H_ERR_STAT_ADDR, - C2H_ERR_STAT_ERR_DESC_CNT_MASK, - GLBL_ERR_STAT_ERR_C2H_ST_MASK, - &qdma_cpm4_hw_st_c2h_err_process - }, - { - QDMA_CPM4_ST_C2H_ERR_PORTID_CTXT_MISMATCH, - "Port id in packet and pfetch ctxt mismatch error", - QDMA_CPM4_C2H_ERR_MASK_ADDR, - QDMA_CPM4_C2H_ERR_STAT_ADDR, - C2H_ERR_STAT_PORT_ID_CTXT_MISMATCH_MASK, - GLBL_ERR_STAT_ERR_C2H_ST_MASK, - &qdma_cpm4_hw_st_c2h_err_process - }, - { - QDMA_CPM4_ST_C2H_ERR_PORTID_BYP_IN_MISMATCH, - "Port id in packet and bypass in mismatch error", - QDMA_CPM4_C2H_ERR_MASK_ADDR, - QDMA_CPM4_C2H_ERR_STAT_ADDR, - C2H_ERR_STAT_PORT_ID_CTXT_MISMATCH_MASK, - GLBL_ERR_STAT_ERR_C2H_ST_MASK, - &qdma_cpm4_hw_st_c2h_err_process - }, - { - QDMA_CPM4_ST_C2H_ERR_WRB_INV_Q_ERR, - "Writeback on invalid queue error", - QDMA_CPM4_C2H_ERR_MASK_ADDR, - QDMA_CPM4_C2H_ERR_STAT_ADDR, - C2H_ERR_STAT_WRB_INV_Q_ERR_MASK, - GLBL_ERR_STAT_ERR_C2H_ST_MASK, - &qdma_cpm4_hw_st_c2h_err_process - }, - { - QDMA_CPM4_ST_C2H_ERR_WRB_QFULL_ERR, - "Completion queue gets full error", - QDMA_CPM4_C2H_ERR_MASK_ADDR, - QDMA_CPM4_C2H_ERR_STAT_ADDR, - C2H_ERR_STAT_WRB_QFULL_ERR_MASK, - GLBL_ERR_STAT_ERR_C2H_ST_MASK, - &qdma_cpm4_hw_st_c2h_err_process - }, - { - QDMA_CPM4_ST_C2H_ERR_WRB_CIDX_ERR, - "Bad CIDX update by the software error", - QDMA_CPM4_C2H_ERR_MASK_ADDR, - QDMA_CPM4_C2H_ERR_STAT_ADDR, - C2H_ERR_STAT_WRB_CIDX_ERR_MASK, - GLBL_ERR_STAT_ERR_C2H_ST_MASK, - &qdma_cpm4_hw_st_c2h_err_process - }, - { - QDMA_CPM4_ST_C2H_ERR_WRB_PRTY_ERR, - "C2H completion Parity error", - QDMA_CPM4_C2H_ERR_MASK_ADDR, - QDMA_CPM4_C2H_ERR_STAT_ADDR, - C2H_ERR_STAT_WRB_PRTY_ERR_MASK, - GLBL_ERR_STAT_ERR_C2H_ST_MASK, - &qdma_cpm4_hw_st_c2h_err_process - }, - { - QDMA_CPM4_ST_C2H_ERR_ALL, - "All C2h errors", - QDMA_CPM4_C2H_ERR_MASK_ADDR, - QDMA_CPM4_C2H_ERR_STAT_ADDR, - QDMA_CPM4_C2H_ERR_ALL_MASK, - GLBL_ERR_STAT_ERR_C2H_ST_MASK, - &qdma_cpm4_hw_st_c2h_err_process - }, - - /* C2H fatal errors */ - { - QDMA_CPM4_ST_FATAL_ERR_MTY_MISMATCH, - "Fatal MTY mismatch error", - QDMA_CPM4_C2H_FATAL_ERR_MASK_ADDR, - QDMA_CPM4_C2H_FATAL_ERR_STAT_ADDR, - C2H_FATAL_ERR_STAT_MTY_MISMATCH_MASK, - GLBL_ERR_STAT_ERR_C2H_ST_MASK, - &qdma_cpm4_hw_st_c2h_err_process - }, - { - QDMA_CPM4_ST_FATAL_ERR_LEN_MISMATCH, - "Fatal Len mismatch error", - QDMA_CPM4_C2H_FATAL_ERR_MASK_ADDR, - QDMA_CPM4_C2H_FATAL_ERR_STAT_ADDR, - C2H_FATAL_ERR_STAT_LEN_MISMATCH_MASK, - GLBL_ERR_STAT_ERR_C2H_ST_MASK, - &qdma_cpm4_hw_st_c2h_err_process - }, - { - QDMA_CPM4_ST_FATAL_ERR_QID_MISMATCH, - "Fatal Qid mismatch error", - QDMA_CPM4_C2H_FATAL_ERR_MASK_ADDR, - QDMA_CPM4_C2H_FATAL_ERR_STAT_ADDR, - C2H_FATAL_ERR_STAT_QID_MISMATCH_MASK, - GLBL_ERR_STAT_ERR_C2H_ST_MASK, - &qdma_cpm4_hw_st_c2h_err_process - }, - { - QDMA_CPM4_ST_FATAL_ERR_TIMER_FIFO_RAM_RDBE, - "RAM double bit fatal error", - QDMA_CPM4_C2H_FATAL_ERR_MASK_ADDR, - QDMA_CPM4_C2H_FATAL_ERR_STAT_ADDR, - C2H_FATAL_ERR_STAT_TIMER_FIFO_RAM_RDBE_MASK, - GLBL_ERR_STAT_ERR_C2H_ST_MASK, - &qdma_cpm4_hw_st_c2h_err_process - }, - { - QDMA_CPM4_ST_FATAL_ERR_PFCH_II_RAM_RDBE, - "RAM double bit fatal error", - QDMA_CPM4_C2H_FATAL_ERR_MASK_ADDR, - QDMA_CPM4_C2H_FATAL_ERR_STAT_ADDR, - C2H_FATAL_ERR_STAT_PFCH_LL_RAM_RDBE_MASK, - GLBL_ERR_STAT_ERR_C2H_ST_MASK, - &qdma_cpm4_hw_st_c2h_err_process - }, - { - QDMA_CPM4_ST_FATAL_ERR_WRB_CTXT_RAM_RDBE, - "RAM double bit fatal error", - QDMA_CPM4_C2H_FATAL_ERR_MASK_ADDR, - QDMA_CPM4_C2H_FATAL_ERR_STAT_ADDR, - C2H_FATAL_ERR_STAT_WRB_CTXT_RAM_RDBE_MASK, - GLBL_ERR_STAT_ERR_C2H_ST_MASK, - &qdma_cpm4_hw_st_c2h_err_process - }, - { - QDMA_CPM4_ST_FATAL_ERR_PFCH_CTXT_RAM_RDBE, - "RAM double bit fatal error", - QDMA_CPM4_C2H_FATAL_ERR_MASK_ADDR, - QDMA_CPM4_C2H_FATAL_ERR_STAT_ADDR, - C2H_FATAL_ERR_STAT_PFCH_CTXT_RAM_RDBE_MASK, - GLBL_ERR_STAT_ERR_C2H_ST_MASK, - &qdma_cpm4_hw_st_c2h_err_process - }, - { - QDMA_CPM4_ST_FATAL_ERR_DESC_REQ_FIFO_RAM_RDBE, - "RAM double bit fatal error", - QDMA_CPM4_C2H_FATAL_ERR_MASK_ADDR, - QDMA_CPM4_C2H_FATAL_ERR_STAT_ADDR, - C2H_FATAL_ERR_STAT_DESC_REQ_FIFO_RAM_RDBE_MASK, - GLBL_ERR_STAT_ERR_C2H_ST_MASK, - &qdma_cpm4_hw_st_c2h_err_process - }, - { - QDMA_CPM4_ST_FATAL_ERR_INT_CTXT_RAM_RDBE, - "RAM double bit fatal error", - QDMA_CPM4_C2H_FATAL_ERR_MASK_ADDR, - QDMA_CPM4_C2H_FATAL_ERR_STAT_ADDR, - C2H_FATAL_ERR_STAT_INT_CTXT_RAM_RDBE_MASK, - GLBL_ERR_STAT_ERR_C2H_ST_MASK, - &qdma_cpm4_hw_st_c2h_err_process - }, - { - QDMA_CPM4_ST_FATAL_ERR_INT_QID2VEC_RAM_RDBE, - "RAM double bit fatal error", - QDMA_CPM4_C2H_FATAL_ERR_MASK_ADDR, - QDMA_CPM4_C2H_FATAL_ERR_STAT_ADDR, - C2H_FATAL_ERR_STAT_INT_QID2VEC_RAM_RDBE_MASK, - GLBL_ERR_STAT_ERR_C2H_ST_MASK, - &qdma_cpm4_hw_st_c2h_err_process - }, - { - QDMA_CPM4_ST_FATAL_ERR_WRB_COAL_DATA_RAM_RDBE, - "RAM double bit fatal error", - QDMA_CPM4_C2H_FATAL_ERR_MASK_ADDR, - QDMA_CPM4_C2H_FATAL_ERR_STAT_ADDR, - C2H_FATAL_ERR_STAT_WRB_COAL_DATA_RAM_RDBE_MASK, - GLBL_ERR_STAT_ERR_C2H_ST_MASK, - &qdma_cpm4_hw_st_c2h_err_process - }, - { - QDMA_CPM4_ST_FATAL_ERR_TUSER_FIFO_RAM_RDBE, - "RAM double bit fatal error", - QDMA_CPM4_C2H_FATAL_ERR_MASK_ADDR, - QDMA_CPM4_C2H_FATAL_ERR_STAT_ADDR, - C2H_FATAL_ERR_STAT_TUSER_FIFO_RAM_RDBE_MASK, - GLBL_ERR_STAT_ERR_C2H_ST_MASK, - &qdma_cpm4_hw_st_c2h_err_process - }, - { - QDMA_CPM4_ST_FATAL_ERR_QID_FIFO_RAM_RDBE, - "RAM double bit fatal error", - QDMA_CPM4_C2H_FATAL_ERR_MASK_ADDR, - QDMA_CPM4_C2H_FATAL_ERR_STAT_ADDR, - C2H_FATAL_ERR_STAT_QID_FIFO_RAM_RDBE_MASK, - GLBL_ERR_STAT_ERR_C2H_ST_MASK, - &qdma_cpm4_hw_st_c2h_err_process - }, - { - QDMA_CPM4_ST_FATAL_ERR_PAYLOAD_FIFO_RAM_RDBE, - "RAM double bit fatal error", - QDMA_CPM4_C2H_FATAL_ERR_MASK_ADDR, - QDMA_CPM4_C2H_FATAL_ERR_STAT_ADDR, - C2H_FATAL_ERR_STAT_PLD_FIFO_RAM_RDBE_MASK, - GLBL_ERR_STAT_ERR_C2H_ST_MASK, - &qdma_cpm4_hw_st_c2h_err_process - }, - { - QDMA_CPM4_ST_FATAL_ERR_WPL_DATA_PAR_ERR, - "RAM double bit fatal error", - QDMA_CPM4_C2H_FATAL_ERR_MASK_ADDR, - QDMA_CPM4_C2H_FATAL_ERR_STAT_ADDR, - C2H_FATAL_ERR_STAT_WPL_DATA_PAR_ERR_MASK, - GLBL_ERR_STAT_ERR_C2H_ST_MASK, - &qdma_cpm4_hw_st_c2h_err_process - }, - { - QDMA_CPM4_ST_FATAL_ERR_ALL, - "All fatal errors", - QDMA_CPM4_C2H_FATAL_ERR_MASK_ADDR, - QDMA_CPM4_C2H_FATAL_ERR_STAT_ADDR, - QDMA_CPM4_C2H_FATAL_ERR_ALL_MASK, - GLBL_ERR_STAT_ERR_C2H_ST_MASK, - &qdma_cpm4_hw_st_c2h_err_process - }, - - /* H2C St errors */ - { - QDMA_CPM4_ST_H2C_ERR_ZERO_LEN_DESC_ERR, - "Zero length descriptor error", - QDMA_CPM4_H2C_ERR_MASK_ADDR, - QDMA_CPM4_H2C_ERR_STAT_ADDR, - H2C_ERR_STAT_ZERO_LEN_DS_MASK, - GLBL_ERR_STAT_ERR_H2C_ST_MASK, - &qdma_cpm4_hw_st_h2c_err_process - }, - { - QDMA_CPM4_ST_H2C_ERR_SDI_MRKR_REQ_MOP_ERR, - "A non-EOP descriptor received", - QDMA_CPM4_H2C_ERR_MASK_ADDR, - QDMA_CPM4_H2C_ERR_STAT_ADDR, - H2C_ERR_STAT_SDI_MRKR_REQ_MOP_ERR_MASK, - GLBL_ERR_STAT_ERR_H2C_ST_MASK, - &qdma_cpm4_hw_st_h2c_err_process - }, - { - QDMA_CPM4_ST_H2C_ERR_NO_DMA_DSC, - "No DMA descriptor received error", - QDMA_CPM4_H2C_ERR_MASK_ADDR, - QDMA_CPM4_H2C_ERR_STAT_ADDR, - H2C_ERR_STAT_NO_DMA_DS_MASK, - GLBL_ERR_STAT_ERR_H2C_ST_MASK, - &qdma_cpm4_hw_st_h2c_err_process - }, - { - QDMA_CPM4_ST_H2C_ERR_DBE, - "Double bit error detected on H2C-ST data error", - QDMA_CPM4_H2C_ERR_MASK_ADDR, - QDMA_CPM4_H2C_ERR_STAT_ADDR, - H2C_ERR_STAT_DBE_MASK, - GLBL_ERR_STAT_ERR_H2C_ST_MASK, - &qdma_cpm4_hw_st_h2c_err_process - }, - { - QDMA_CPM4_ST_H2C_ERR_SBE, - "Single bit error detected on H2C-ST data error", - QDMA_CPM4_H2C_ERR_MASK_ADDR, - QDMA_CPM4_H2C_ERR_STAT_ADDR, - H2C_ERR_STAT_SBE_MASK, - GLBL_ERR_STAT_ERR_H2C_ST_MASK, - &qdma_cpm4_hw_st_h2c_err_process - }, - { - QDMA_CPM4_ST_H2C_ERR_ALL, - "All H2C errors", - QDMA_CPM4_H2C_ERR_MASK_ADDR, - QDMA_CPM4_H2C_ERR_STAT_ADDR, - QDMA_CPM4_H2C_ERR_ALL_MASK, - GLBL_ERR_STAT_ERR_H2C_ST_MASK, - &qdma_cpm4_hw_st_h2c_err_process - }, - - /* SBE errors */ - { - QDMA_CPM4_SBE_ERR_MI_H2C0_DAT, - "H2C MM data buffer single bit ECC error", - QDMA_CPM4_RAM_SBE_MSK_A_ADDR, - QDMA_CPM4_RAM_SBE_STS_A_ADDR, - RAM_SBE_STS_A_MI_H2C0_DAT_MASK, - GLBL_ERR_STAT_ERR_RAM_SBE_MASK, - &qdma_cpm4_hw_ram_sbe_err_process - }, - { - QDMA_CPM4_SBE_ERR_MI_C2H0_DAT, - "C2H MM data buffer single bit ECC error", - QDMA_CPM4_RAM_SBE_MSK_A_ADDR, - QDMA_CPM4_RAM_SBE_STS_A_ADDR, - RAM_SBE_STS_A_MI_C2H0_DAT_MASK, - GLBL_ERR_STAT_ERR_RAM_SBE_MASK, - &qdma_cpm4_hw_ram_sbe_err_process - }, - { - QDMA_CPM4_SBE_ERR_H2C_RD_BRG_DAT, - "Bridge master read single bit ECC error", - QDMA_CPM4_RAM_SBE_MSK_A_ADDR, - QDMA_CPM4_RAM_SBE_STS_A_ADDR, - RAM_SBE_STS_A_H2C_RD_BRG_DAT_MASK, - GLBL_ERR_STAT_ERR_RAM_SBE_MASK, - &qdma_cpm4_hw_ram_sbe_err_process - }, - { - QDMA_CPM4_SBE_ERR_H2C_WR_BRG_DAT, - "Bridge master write single bit ECC error", - QDMA_CPM4_RAM_SBE_MSK_A_ADDR, - QDMA_CPM4_RAM_SBE_STS_A_ADDR, - RAM_SBE_STS_A_H2C_WR_BRG_DAT_MASK, - GLBL_ERR_STAT_ERR_RAM_SBE_MASK, - &qdma_cpm4_hw_ram_sbe_err_process - }, - { - QDMA_CPM4_SBE_ERR_C2H_RD_BRG_DAT, - "Bridge slave read data buffer single bit ECC error", - QDMA_CPM4_RAM_SBE_MSK_A_ADDR, - QDMA_CPM4_RAM_SBE_STS_A_ADDR, - RAM_SBE_STS_A_C2H_RD_BRG_DAT_MASK, - GLBL_ERR_STAT_ERR_RAM_SBE_MASK, - &qdma_cpm4_hw_ram_sbe_err_process - }, - { - QDMA_CPM4_SBE_ERR_C2H_WR_BRG_DAT, - "Bridge slave write data buffer single bit ECC error", - QDMA_CPM4_RAM_SBE_MSK_A_ADDR, - QDMA_CPM4_RAM_SBE_STS_A_ADDR, - RAM_SBE_STS_A_C2H_WR_BRG_DAT_MASK, - GLBL_ERR_STAT_ERR_RAM_SBE_MASK, - &qdma_cpm4_hw_ram_sbe_err_process - }, - { - QDMA_CPM4_SBE_ERR_FUNC_MAP, - "Function map RAM single bit ECC error", - QDMA_CPM4_RAM_SBE_MSK_A_ADDR, - QDMA_CPM4_RAM_SBE_STS_A_ADDR, - RAM_SBE_STS_A_FUNC_MAP_MASK, - GLBL_ERR_STAT_ERR_RAM_SBE_MASK, - &qdma_cpm4_hw_ram_sbe_err_process - }, - { - QDMA_CPM4_SBE_ERR_DSC_HW_CTXT, - "Descriptor engine hardware context RAM single bit ECC error", - QDMA_CPM4_RAM_SBE_MSK_A_ADDR, - QDMA_CPM4_RAM_SBE_STS_A_ADDR, - RAM_SBE_STS_A_DSC_HW_CTXT_MASK, - GLBL_ERR_STAT_ERR_RAM_SBE_MASK, - &qdma_cpm4_hw_ram_sbe_err_process - }, - { - QDMA_CPM4_SBE_ERR_DSC_CRD_RCV, - "Descriptor engine receive credit context RAM single bit ECC error", - QDMA_CPM4_RAM_SBE_MSK_A_ADDR, - QDMA_CPM4_RAM_SBE_STS_A_ADDR, - RAM_SBE_STS_A_DSC_CRD_RCV_MASK, - GLBL_ERR_STAT_ERR_RAM_SBE_MASK, - &qdma_cpm4_hw_ram_sbe_err_process - }, - { - QDMA_CPM4_SBE_ERR_DSC_SW_CTXT, - "Descriptor engine software context RAM single bit ECC error", - QDMA_CPM4_RAM_SBE_MSK_A_ADDR, - QDMA_CPM4_RAM_SBE_STS_A_ADDR, - RAM_SBE_STS_A_DSC_SW_CTXT_MASK, - GLBL_ERR_STAT_ERR_RAM_SBE_MASK, - &qdma_cpm4_hw_ram_sbe_err_process - }, - { - QDMA_CPM4_SBE_ERR_DSC_CPLI, - "Descriptor engine fetch completion information RAM single bit ECC error", - QDMA_CPM4_RAM_SBE_MSK_A_ADDR, - QDMA_CPM4_RAM_SBE_STS_A_ADDR, - RAM_SBE_STS_A_DSC_CPLI_MASK, - GLBL_ERR_STAT_ERR_RAM_SBE_MASK, - &qdma_cpm4_hw_ram_sbe_err_process - }, - { - QDMA_CPM4_SBE_ERR_DSC_CPLD, - "Descriptor engine fetch completion data RAM single bit ECC error", - QDMA_CPM4_RAM_SBE_MSK_A_ADDR, - QDMA_CPM4_RAM_SBE_STS_A_ADDR, - RAM_SBE_STS_A_DSC_CPLD_MASK, - GLBL_ERR_STAT_ERR_RAM_SBE_MASK, - &qdma_cpm4_hw_ram_sbe_err_process - }, - { - QDMA_CPM4_SBE_ERR_PASID_CTXT_RAM, - "Pasid ctxt FIFO RAM single bit ECC error", - QDMA_CPM4_RAM_SBE_MSK_A_ADDR, - QDMA_CPM4_RAM_SBE_STS_A_ADDR, - RAM_SBE_STS_A_PASID_CTXT_RAM_MASK, - GLBL_ERR_STAT_ERR_RAM_SBE_MASK, - &qdma_cpm4_hw_ram_sbe_err_process - }, - { - QDMA_CPM4_SBE_ERR_TIMER_FIFO_RAM, - "Timer fifo RAM single bit ECC error", - QDMA_CPM4_RAM_SBE_MSK_A_ADDR, - QDMA_CPM4_RAM_SBE_STS_A_ADDR, - RAM_SBE_STS_A_TIMER_FIFO_RAM_MASK, - GLBL_ERR_STAT_ERR_RAM_SBE_MASK, - &qdma_cpm4_hw_ram_sbe_err_process - }, - { - QDMA_CPM4_SBE_ERR_PAYLOAD_FIFO_RAM, - "C2H ST payload FIFO RAM single bit ECC error", - QDMA_CPM4_RAM_SBE_MSK_A_ADDR, - QDMA_CPM4_RAM_SBE_STS_A_ADDR, - RAM_SBE_STS_A_PLD_FIFO_RAM_MASK, - GLBL_ERR_STAT_ERR_RAM_SBE_MASK, - &qdma_cpm4_hw_ram_sbe_err_process - }, - { - QDMA_CPM4_SBE_ERR_QID_FIFO_RAM, - "C2H ST QID FIFO RAM single bit ECC error", - QDMA_CPM4_RAM_SBE_MSK_A_ADDR, - QDMA_CPM4_RAM_SBE_STS_A_ADDR, - RAM_SBE_STS_A_QID_FIFO_RAM_MASK, - GLBL_ERR_STAT_ERR_RAM_SBE_MASK, - &qdma_cpm4_hw_ram_sbe_err_process - }, - { - QDMA_CPM4_SBE_ERR_TUSER_FIFO_RAM, - "C2H ST TUSER FIFO RAM single bit ECC error", - QDMA_CPM4_RAM_SBE_MSK_A_ADDR, - QDMA_CPM4_RAM_SBE_STS_A_ADDR, - RAM_SBE_STS_A_TUSER_FIFO_RAM_MASK, - GLBL_ERR_STAT_ERR_RAM_SBE_MASK, - &qdma_cpm4_hw_ram_sbe_err_process - }, - { - QDMA_CPM4_SBE_ERR_WRB_COAL_DATA_RAM, - "Writeback Coalescing RAM single bit ECC error", - QDMA_CPM4_RAM_SBE_MSK_A_ADDR, - QDMA_CPM4_RAM_SBE_STS_A_ADDR, - RAM_SBE_STS_A_WRB_COAL_DATA_RAM_MASK, - GLBL_ERR_STAT_ERR_RAM_SBE_MASK, - &qdma_cpm4_hw_ram_sbe_err_process - }, - { - QDMA_CPM4_SBE_ERR_INT_QID2VEC_RAM, - "Interrupt QID2VEC RAM single bit ECC error", - QDMA_CPM4_RAM_SBE_MSK_A_ADDR, - QDMA_CPM4_RAM_SBE_STS_A_ADDR, - RAM_SBE_STS_A_INT_QID2VEC_RAM_MASK, - GLBL_ERR_STAT_ERR_RAM_SBE_MASK, - &qdma_cpm4_hw_ram_sbe_err_process - }, - { - QDMA_CPM4_SBE_ERR_INT_CTXT_RAM, - "Interrupt context RAM single bit ECC error", - QDMA_CPM4_RAM_SBE_MSK_A_ADDR, - QDMA_CPM4_RAM_SBE_STS_A_ADDR, - RAM_SBE_STS_A_INT_CTXT_RAM_MASK, - GLBL_ERR_STAT_ERR_RAM_SBE_MASK, - &qdma_cpm4_hw_ram_sbe_err_process - }, - { - QDMA_CPM4_SBE_ERR_DESC_REQ_FIFO_RAM, - "C2H ST descriptor request RAM single bit ECC error", - QDMA_CPM4_RAM_SBE_MSK_A_ADDR, - QDMA_CPM4_RAM_SBE_STS_A_ADDR, - RAM_SBE_STS_A_DESC_REQ_FIFO_RAM_MASK, - GLBL_ERR_STAT_ERR_RAM_SBE_MASK, - &qdma_cpm4_hw_ram_sbe_err_process - }, - { - QDMA_CPM4_SBE_ERR_PFCH_CTXT_RAM, - "C2H ST prefetch RAM single bit ECC error", - QDMA_CPM4_RAM_SBE_MSK_A_ADDR, - QDMA_CPM4_RAM_SBE_STS_A_ADDR, - RAM_SBE_STS_A_PFCH_CTXT_RAM_MASK, - GLBL_ERR_STAT_ERR_RAM_SBE_MASK, - &qdma_cpm4_hw_ram_sbe_err_process - }, - { - QDMA_CPM4_SBE_ERR_WRB_CTXT_RAM, - "C2H ST completion context RAM single bit ECC error", - QDMA_CPM4_RAM_SBE_MSK_A_ADDR, - QDMA_CPM4_RAM_SBE_STS_A_ADDR, - RAM_SBE_STS_A_WRB_CTXT_RAM_MASK, - GLBL_ERR_STAT_ERR_RAM_SBE_MASK, - &qdma_cpm4_hw_ram_sbe_err_process - }, - { - QDMA_CPM4_SBE_ERR_PFCH_LL_RAM, - "C2H ST prefetch list RAM single bit ECC error", - QDMA_CPM4_RAM_SBE_MSK_A_ADDR, - QDMA_CPM4_RAM_SBE_STS_A_ADDR, - RAM_SBE_STS_A_PFCH_LL_RAM_MASK, - GLBL_ERR_STAT_ERR_RAM_SBE_MASK, - &qdma_cpm4_hw_ram_sbe_err_process - }, - { - QDMA_CPM4_SBE_ERR_ALL, - "All SBE errors", - QDMA_CPM4_RAM_SBE_MSK_A_ADDR, - QDMA_CPM4_RAM_SBE_STS_A_ADDR, - QDMA_CPM4_SBE_ERR_ALL_MASK, - GLBL_ERR_STAT_ERR_RAM_SBE_MASK, - &qdma_cpm4_hw_ram_sbe_err_process - }, - - - /* DBE errors */ - { - QDMA_CPM4_DBE_ERR_MI_H2C0_DAT, - "H2C MM data buffer single bit ECC error", - QDMA_CPM4_RAM_DBE_MSK_A_ADDR, - QDMA_CPM4_RAM_DBE_STS_A_ADDR, - RAM_DBE_STS_A_MI_H2C0_DAT_MASK, - GLBL_ERR_STAT_ERR_RAM_DBE_MASK, - &qdma_cpm4_hw_ram_dbe_err_process - }, - { - QDMA_CPM4_DBE_ERR_MI_C2H0_DAT, - "C2H MM data buffer single bit ECC error", - QDMA_CPM4_RAM_DBE_MSK_A_ADDR, - QDMA_CPM4_RAM_DBE_STS_A_ADDR, - RAM_DBE_STS_A_MI_C2H0_DAT_MASK, - GLBL_ERR_STAT_ERR_RAM_DBE_MASK, - &qdma_cpm4_hw_ram_dbe_err_process - }, - { - QDMA_CPM4_DBE_ERR_H2C_RD_BRG_DAT, - "Bridge master read single bit ECC error", - QDMA_CPM4_RAM_DBE_MSK_A_ADDR, - QDMA_CPM4_RAM_DBE_STS_A_ADDR, - RAM_DBE_STS_A_H2C_RD_BRG_DAT_MASK, - GLBL_ERR_STAT_ERR_RAM_DBE_MASK, - &qdma_cpm4_hw_ram_dbe_err_process - }, - { - QDMA_CPM4_DBE_ERR_H2C_WR_BRG_DAT, - "Bridge master write single bit ECC error", - QDMA_CPM4_RAM_DBE_MSK_A_ADDR, - QDMA_CPM4_RAM_DBE_STS_A_ADDR, - RAM_DBE_STS_A_H2C_WR_BRG_DAT_MASK, - GLBL_ERR_STAT_ERR_RAM_DBE_MASK, - &qdma_cpm4_hw_ram_dbe_err_process - }, - { - QDMA_CPM4_DBE_ERR_C2H_RD_BRG_DAT, - "Bridge slave read data buffer single bit ECC error", - QDMA_CPM4_RAM_DBE_MSK_A_ADDR, - QDMA_CPM4_RAM_DBE_STS_A_ADDR, - RAM_DBE_STS_A_C2H_RD_BRG_DAT_MASK, - GLBL_ERR_STAT_ERR_RAM_DBE_MASK, - &qdma_cpm4_hw_ram_dbe_err_process - }, - { - QDMA_CPM4_DBE_ERR_C2H_WR_BRG_DAT, - "Bridge slave write data buffer single bit ECC error", - QDMA_CPM4_RAM_DBE_MSK_A_ADDR, - QDMA_CPM4_RAM_DBE_STS_A_ADDR, - RAM_DBE_STS_A_C2H_WR_BRG_DAT_MASK, - GLBL_ERR_STAT_ERR_RAM_DBE_MASK, - &qdma_cpm4_hw_ram_dbe_err_process - }, - { - QDMA_CPM4_DBE_ERR_FUNC_MAP, - "Function map RAM single bit ECC error", - QDMA_CPM4_RAM_DBE_MSK_A_ADDR, - QDMA_CPM4_RAM_DBE_STS_A_ADDR, - RAM_DBE_STS_A_FUNC_MAP_MASK, - GLBL_ERR_STAT_ERR_RAM_DBE_MASK, - &qdma_cpm4_hw_ram_dbe_err_process - }, - { - QDMA_CPM4_DBE_ERR_DSC_HW_CTXT, - "Descriptor engine hardware context RAM single bit ECC error", - QDMA_CPM4_RAM_DBE_MSK_A_ADDR, - QDMA_CPM4_RAM_DBE_STS_A_ADDR, - RAM_DBE_STS_A_DSC_HW_CTXT_MASK, - GLBL_ERR_STAT_ERR_RAM_DBE_MASK, - &qdma_cpm4_hw_ram_dbe_err_process - }, - { - QDMA_CPM4_DBE_ERR_DSC_CRD_RCV, - "Descriptor engine receive credit context RAM single bit ECC error", - QDMA_CPM4_RAM_DBE_MSK_A_ADDR, - QDMA_CPM4_RAM_DBE_STS_A_ADDR, - RAM_DBE_STS_A_DSC_CRD_RCV_MASK, - GLBL_ERR_STAT_ERR_RAM_DBE_MASK, - &qdma_cpm4_hw_ram_dbe_err_process - }, - { - QDMA_CPM4_DBE_ERR_DSC_SW_CTXT, - "Descriptor engine software context RAM single bit ECC error", - QDMA_CPM4_RAM_DBE_MSK_A_ADDR, - QDMA_CPM4_RAM_DBE_STS_A_ADDR, - RAM_DBE_STS_A_DSC_SW_CTXT_MASK, - GLBL_ERR_STAT_ERR_RAM_DBE_MASK, - &qdma_cpm4_hw_ram_dbe_err_process - }, - { - QDMA_CPM4_DBE_ERR_DSC_CPLI, - "Descriptor engine fetch completion information RAM single bit ECC error", - QDMA_CPM4_RAM_DBE_MSK_A_ADDR, - QDMA_CPM4_RAM_DBE_STS_A_ADDR, - RAM_DBE_STS_A_DSC_CPLI_MASK, - GLBL_ERR_STAT_ERR_RAM_DBE_MASK, - &qdma_cpm4_hw_ram_dbe_err_process - }, - { - QDMA_CPM4_DBE_ERR_DSC_CPLD, - "Descriptor engine fetch completion data RAM single bit ECC error", - QDMA_CPM4_RAM_DBE_MSK_A_ADDR, - QDMA_CPM4_RAM_DBE_STS_A_ADDR, - RAM_DBE_STS_A_DSC_CPLD_MASK, - GLBL_ERR_STAT_ERR_RAM_DBE_MASK, - &qdma_cpm4_hw_ram_dbe_err_process - }, - { - QDMA_CPM4_DBE_ERR_PASID_CTXT_RAM, - "PASID CTXT RAM single bit ECC error", - QDMA_CPM4_RAM_DBE_MSK_A_ADDR, - QDMA_CPM4_RAM_DBE_STS_A_ADDR, - RAM_DBE_STS_A_PASID_CTXT_RAM_MASK, - GLBL_ERR_STAT_ERR_RAM_DBE_MASK, - &qdma_cpm4_hw_ram_dbe_err_process - }, - { - QDMA_CPM4_DBE_ERR_TIMER_FIFO_RAM, - "Timer fifo RAM single bit ECC error", - QDMA_CPM4_RAM_DBE_MSK_A_ADDR, - QDMA_CPM4_RAM_DBE_STS_A_ADDR, - RAM_DBE_STS_A_TIMER_FIFO_RAM_MASK, - GLBL_ERR_STAT_ERR_RAM_DBE_MASK, - &qdma_cpm4_hw_ram_dbe_err_process - }, - { - QDMA_CPM4_DBE_ERR_PAYLOAD_FIFO_RAM, - "Payload fifo RAM single bit ECC error", - QDMA_CPM4_RAM_DBE_MSK_A_ADDR, - QDMA_CPM4_RAM_DBE_STS_A_ADDR, - RAM_DBE_STS_A_PLD_FIFO_RAM_MASK, - GLBL_ERR_STAT_ERR_RAM_DBE_MASK, - &qdma_cpm4_hw_ram_dbe_err_process - }, - { - QDMA_CPM4_DBE_ERR_QID_FIFO_RAM, - "C2H ST QID FIFO RAM single bit ECC error", - QDMA_CPM4_RAM_DBE_MSK_A_ADDR, - QDMA_CPM4_RAM_DBE_STS_A_ADDR, - RAM_DBE_STS_A_QID_FIFO_RAM_MASK, - GLBL_ERR_STAT_ERR_RAM_DBE_MASK, - &qdma_cpm4_hw_ram_dbe_err_process - }, - { - QDMA_CPM4_DBE_ERR_WRB_COAL_DATA_RAM, - "Writeback Coalescing RAM single bit ECC error", - QDMA_CPM4_RAM_DBE_MSK_A_ADDR, - QDMA_CPM4_RAM_DBE_STS_A_ADDR, - RAM_DBE_STS_A_WRB_COAL_DATA_RAM_MASK, - GLBL_ERR_STAT_ERR_RAM_DBE_MASK, - &qdma_cpm4_hw_ram_dbe_err_process - }, - { - QDMA_CPM4_DBE_ERR_INT_QID2VEC_RAM, - "QID2VEC RAM single bit ECC error", - QDMA_CPM4_RAM_DBE_MSK_A_ADDR, - QDMA_CPM4_RAM_DBE_STS_A_ADDR, - RAM_DBE_STS_A_INT_QID2VEC_RAM_MASK, - GLBL_ERR_STAT_ERR_RAM_DBE_MASK, - &qdma_cpm4_hw_ram_dbe_err_process - }, - { - QDMA_CPM4_DBE_ERR_INT_CTXT_RAM, - "Interrupt context RAM single bit ECC error", - QDMA_CPM4_RAM_DBE_MSK_A_ADDR, - QDMA_CPM4_RAM_DBE_STS_A_ADDR, - RAM_DBE_STS_A_INT_CTXT_RAM_MASK, - GLBL_ERR_STAT_ERR_RAM_DBE_MASK, - &qdma_cpm4_hw_ram_dbe_err_process - }, - { - QDMA_CPM4_DBE_ERR_DESC_REQ_FIFO_RAM, - "C2H ST descriptor request RAM single bit ECC error", - QDMA_CPM4_RAM_DBE_MSK_A_ADDR, - QDMA_CPM4_RAM_DBE_STS_A_ADDR, - RAM_DBE_STS_A_DESC_REQ_FIFO_RAM_MASK, - GLBL_ERR_STAT_ERR_RAM_DBE_MASK, - &qdma_cpm4_hw_ram_dbe_err_process - }, - { - QDMA_CPM4_DBE_ERR_PFCH_CTXT_RAM, - "C2H ST prefetch RAM single bit ECC error", - QDMA_CPM4_RAM_DBE_MSK_A_ADDR, - QDMA_CPM4_RAM_DBE_STS_A_ADDR, - RAM_DBE_STS_A_PFCH_CTXT_RAM_MASK, - GLBL_ERR_STAT_ERR_RAM_DBE_MASK, - &qdma_cpm4_hw_ram_dbe_err_process - }, - { - QDMA_CPM4_DBE_ERR_WRB_CTXT_RAM, - "C2H ST completion context RAM single bit ECC error", - QDMA_CPM4_RAM_DBE_MSK_A_ADDR, - QDMA_CPM4_RAM_DBE_STS_A_ADDR, - RAM_DBE_STS_A_WRB_CTXT_RAM_MASK, - GLBL_ERR_STAT_ERR_RAM_DBE_MASK, - &qdma_cpm4_hw_ram_dbe_err_process - }, - { - QDMA_CPM4_DBE_ERR_PFCH_LL_RAM, - "C2H ST prefetch list RAM single bit ECC error", - QDMA_CPM4_RAM_DBE_MSK_A_ADDR, - QDMA_CPM4_RAM_DBE_STS_A_ADDR, - RAM_DBE_STS_A_PFCH_LL_RAM_MASK, - GLBL_ERR_STAT_ERR_RAM_DBE_MASK, - &qdma_cpm4_hw_ram_dbe_err_process - }, - { - QDMA_CPM4_DBE_ERR_ALL, - "All DBE errors", - QDMA_CPM4_RAM_DBE_MSK_A_ADDR, - QDMA_CPM4_RAM_DBE_STS_A_ADDR, - QDMA_CPM4_DBE_ERR_ALL_MASK, - GLBL_ERR_STAT_ERR_RAM_DBE_MASK, - &qdma_cpm4_hw_ram_dbe_err_process - } -}; - -static int32_t all_qdma_cpm4_hw_errs[ - QDMA_CPM4_TOTAL_LEAF_ERROR_AGGREGATORS] = { - - QDMA_CPM4_DSC_ERR_ALL, - QDMA_CPM4_TRQ_ERR_ALL, - QDMA_CPM4_ST_C2H_ERR_ALL, - QDMA_CPM4_ST_FATAL_ERR_ALL, - QDMA_CPM4_ST_H2C_ERR_ALL, - QDMA_CPM4_SBE_ERR_ALL, - QDMA_CPM4_DBE_ERR_ALL -}; - - - -union qdma_cpm4_ind_ctxt_cmd { - uint32_t word; - struct { - uint32_t busy:1; - uint32_t sel:4; - uint32_t op:2; - uint32_t qid:11; - uint32_t rsvd:14; - } bits; -}; - -struct qdma_cpm4_indirect_ctxt_regs { - uint32_t qdma_ind_ctxt_data[QDMA_CPM4_IND_CTXT_DATA_NUM_REGS]; - uint32_t qdma_ind_ctxt_mask[QDMA_CPM4_IND_CTXT_DATA_NUM_REGS]; - union qdma_cpm4_ind_ctxt_cmd cmd; -}; - -static struct qctx_entry qdma_cpm4_sw_ctxt_entries[] = { - {"PIDX", 0}, - {"IRQ Arm", 0}, - {"Queue Enable", 0}, - {"Fetch Credit Enable", 0}, - {"Write back/Intr Check", 0}, - {"Write back/Intr Interval", 0}, - {"Function Id", 0}, - {"Ring Size", 0}, - {"Descriptor Size", 0}, - {"Bypass Enable", 0}, - {"MM Channel", 0}, - {"Writeback Enable", 0}, - {"Interrupt Enable", 0}, - {"Port Id", 0}, - {"Interrupt No Last", 0}, - {"Error", 0}, - {"Writeback Error Sent", 0}, - {"IRQ Request", 0}, - {"Marker Disable", 0}, - {"Is Memory Mapped", 0}, - {"Descriptor Ring Base Addr (Low)", 0}, - {"Descriptor Ring Base Addr (High)", 0}, -}; - -static struct qctx_entry qdma_cpm4_hw_ctxt_entries[] = { - {"CIDX", 0}, - {"Credits Consumed", 0}, - {"Descriptors Pending", 0}, - {"Queue Invalid No Desc Pending", 0}, - {"Eviction Pending", 0}, - {"Fetch Pending", 0}, -}; - -static struct qctx_entry qdma_cpm4_credit_ctxt_entries[] = { - {"Credit", 0}, -}; - -static struct qctx_entry qdma_cpm4_fmap_ctxt_entries[] = { - {"Queue Base", 0}, - {"Queue Max", 0}, -}; - -static struct qctx_entry qdma_cpm4_cmpt_ctxt_entries[] = { - {"Enable Status Desc Update", 0}, - {"Enable Interrupt", 0}, - {"Trigger Mode", 0}, - {"Function Id", 0}, - {"Counter Index", 0}, - {"Timer Index", 0}, - {"Interrupt State", 0}, - {"Color", 0}, - {"Ring Size", 0}, - {"Base Address (Low)", 0}, - {"Base Address (High)", 0}, - {"Descriptor Size", 0}, - {"PIDX", 0}, - {"CIDX", 0}, - {"Valid", 0}, - {"Error", 0}, - {"Trigger Pending", 0}, - {"Timer Running", 0}, - {"Full Update", 0}, -}; - -static struct qctx_entry qdma_cpm4_c2h_pftch_ctxt_entries[] = { - {"Bypass", 0}, - {"Buffer Size Index", 0}, - {"Port Id", 0}, - {"Error", 0}, - {"Prefetch Enable", 0}, - {"In Prefetch", 0}, - {"Software Credit", 0}, - {"Valid", 0}, -}; - -static struct qctx_entry qdma_cpm4_qid2vec_ctxt_entries[] = { - {"c2h_vector", 0}, - {"c2h_en_coal", 0}, - {"h2c_vector", 0}, - {"h2c_en_coal", 0}, -}; - -static struct qctx_entry qdma_cpm4_ind_intr_ctxt_entries[] = { - {"valid", 0}, - {"vec", 0}, - {"int_st", 0}, - {"color", 0}, - {"baddr_4k (Low)", 0}, - {"baddr_4k (High)", 0}, - {"page_size", 0}, - {"pidx", 0}, -}; - -static int qdma_cpm4_indirect_reg_invalidate(void *dev_hndl, - enum ind_ctxt_cmd_sel sel, uint16_t hw_qid); -static int qdma_cpm4_indirect_reg_clear(void *dev_hndl, - enum ind_ctxt_cmd_sel sel, uint16_t hw_qid); -static int qdma_cpm4_indirect_reg_read(void *dev_hndl, - enum ind_ctxt_cmd_sel sel, - uint16_t hw_qid, uint32_t cnt, uint32_t *data); -static int qdma_cpm4_indirect_reg_write(void *dev_hndl, - enum ind_ctxt_cmd_sel sel, - uint16_t hw_qid, uint32_t *data, uint16_t cnt); - -uint32_t qdma_cpm4_get_config_num_regs(void) -{ - return qdma_cpm4_config_num_regs_get(); -} - -struct xreg_info *qdma_cpm4_get_config_regs(void) -{ - return qdma_cpm4_config_regs_get(); -} - -uint32_t qdma_cpm4_reg_dump_buf_len(void) -{ - uint32_t length = (qdma_cpm4_config_num_regs_get() + 1) - * REG_DUMP_SIZE_PER_LINE; - return length; -} - -int qdma_cpm4_context_buf_len(uint8_t st, - enum qdma_dev_q_type q_type, uint32_t *req_buflen) -{ - uint32_t len = 0; - int rv = 0; - - if (q_type == QDMA_DEV_Q_TYPE_CMPT) { - len += (((sizeof(qdma_cpm4_cmpt_ctxt_entries) / - sizeof(qdma_cpm4_cmpt_ctxt_entries[0])) + 1) * - REG_DUMP_SIZE_PER_LINE); - } else { - len += (((sizeof(qdma_cpm4_sw_ctxt_entries) / - sizeof(qdma_cpm4_sw_ctxt_entries[0])) + 1) * - REG_DUMP_SIZE_PER_LINE); - - len += (((sizeof(qdma_cpm4_hw_ctxt_entries) / - sizeof(qdma_cpm4_hw_ctxt_entries[0])) + 1) * - REG_DUMP_SIZE_PER_LINE); - - len += (((sizeof(qdma_cpm4_credit_ctxt_entries) / - sizeof(qdma_cpm4_credit_ctxt_entries[0])) + 1) * - REG_DUMP_SIZE_PER_LINE); - - len += (((sizeof(qdma_cpm4_fmap_ctxt_entries) / - sizeof(qdma_cpm4_fmap_ctxt_entries[0])) + 1) * - REG_DUMP_SIZE_PER_LINE); - - if (st && (q_type == QDMA_DEV_Q_TYPE_C2H)) { - len += (((sizeof(qdma_cpm4_cmpt_ctxt_entries) / - sizeof(qdma_cpm4_cmpt_ctxt_entries[0])) + 1) * - REG_DUMP_SIZE_PER_LINE); - - len += (((sizeof(qdma_cpm4_c2h_pftch_ctxt_entries) / - sizeof(qdma_cpm4_c2h_pftch_ctxt_entries[0])) + 1) * - REG_DUMP_SIZE_PER_LINE); - } - } - - *req_buflen = len; - return rv; -} - -static uint32_t qdma_cpm4_intr_context_buf_len(void) -{ - uint32_t len = 0; - - len += (((sizeof(qdma_cpm4_ind_intr_ctxt_entries) / - sizeof(qdma_cpm4_ind_intr_ctxt_entries[0])) + 1) * - REG_DUMP_SIZE_PER_LINE); - return len; -} - -/* - * qdma_acc_fill_sw_ctxt() - Helper function to fill sw context into structure - * - */ -static void qdma_cpm4_fill_sw_ctxt(struct qdma_descq_sw_ctxt *sw_ctxt) -{ - qdma_cpm4_sw_ctxt_entries[0].value = sw_ctxt->pidx; - qdma_cpm4_sw_ctxt_entries[1].value = sw_ctxt->irq_arm; - qdma_cpm4_sw_ctxt_entries[2].value = sw_ctxt->qen; - qdma_cpm4_sw_ctxt_entries[3].value = sw_ctxt->frcd_en; - qdma_cpm4_sw_ctxt_entries[4].value = sw_ctxt->wbi_chk; - qdma_cpm4_sw_ctxt_entries[5].value = sw_ctxt->wbi_intvl_en; - qdma_cpm4_sw_ctxt_entries[6].value = sw_ctxt->fnc_id; - qdma_cpm4_sw_ctxt_entries[7].value = sw_ctxt->rngsz_idx; - qdma_cpm4_sw_ctxt_entries[8].value = sw_ctxt->desc_sz; - qdma_cpm4_sw_ctxt_entries[9].value = sw_ctxt->bypass; - qdma_cpm4_sw_ctxt_entries[10].value = sw_ctxt->mm_chn; - qdma_cpm4_sw_ctxt_entries[11].value = sw_ctxt->wbk_en; - qdma_cpm4_sw_ctxt_entries[12].value = sw_ctxt->irq_en; - qdma_cpm4_sw_ctxt_entries[13].value = sw_ctxt->port_id; - qdma_cpm4_sw_ctxt_entries[14].value = sw_ctxt->irq_no_last; - qdma_cpm4_sw_ctxt_entries[15].value = sw_ctxt->err; - qdma_cpm4_sw_ctxt_entries[16].value = sw_ctxt->err_wb_sent; - qdma_cpm4_sw_ctxt_entries[17].value = sw_ctxt->irq_req; - qdma_cpm4_sw_ctxt_entries[18].value = sw_ctxt->mrkr_dis; - qdma_cpm4_sw_ctxt_entries[19].value = sw_ctxt->is_mm; - qdma_cpm4_sw_ctxt_entries[20].value = - sw_ctxt->ring_bs_addr & 0xFFFFFFFF; - qdma_cpm4_sw_ctxt_entries[21].value = - (sw_ctxt->ring_bs_addr >> 32) & 0xFFFFFFFF; -} - -/* - * qdma_acc_fill_cmpt_ctxt() - Helper function to fill completion context - * into structure - * - */ -static void qdma_cpm4_fill_cmpt_ctxt(struct qdma_descq_cmpt_ctxt *cmpt_ctxt) -{ - qdma_cpm4_cmpt_ctxt_entries[0].value = cmpt_ctxt->en_stat_desc; - qdma_cpm4_cmpt_ctxt_entries[1].value = cmpt_ctxt->en_int; - qdma_cpm4_cmpt_ctxt_entries[2].value = cmpt_ctxt->trig_mode; - qdma_cpm4_cmpt_ctxt_entries[3].value = cmpt_ctxt->fnc_id; - qdma_cpm4_cmpt_ctxt_entries[4].value = cmpt_ctxt->counter_idx; - qdma_cpm4_cmpt_ctxt_entries[5].value = cmpt_ctxt->timer_idx; - qdma_cpm4_cmpt_ctxt_entries[6].value = cmpt_ctxt->in_st; - qdma_cpm4_cmpt_ctxt_entries[7].value = cmpt_ctxt->color; - qdma_cpm4_cmpt_ctxt_entries[8].value = cmpt_ctxt->ringsz_idx; - qdma_cpm4_cmpt_ctxt_entries[9].value = - cmpt_ctxt->bs_addr & 0xFFFFFFFF; - qdma_cpm4_cmpt_ctxt_entries[10].value = - (cmpt_ctxt->bs_addr >> 32) & 0xFFFFFFFF; - qdma_cpm4_cmpt_ctxt_entries[11].value = cmpt_ctxt->desc_sz; - qdma_cpm4_cmpt_ctxt_entries[12].value = cmpt_ctxt->pidx; - qdma_cpm4_cmpt_ctxt_entries[13].value = cmpt_ctxt->cidx; - qdma_cpm4_cmpt_ctxt_entries[14].value = cmpt_ctxt->valid; - qdma_cpm4_cmpt_ctxt_entries[15].value = cmpt_ctxt->err; - qdma_cpm4_cmpt_ctxt_entries[16].value = cmpt_ctxt->user_trig_pend; - qdma_cpm4_cmpt_ctxt_entries[17].value = cmpt_ctxt->timer_running; - qdma_cpm4_cmpt_ctxt_entries[18].value = cmpt_ctxt->full_upd; - -} - -/* - * qdma_acc_fill_hw_ctxt() - Helper function to fill HW context into structure - * - */ -static void qdma_cpm4_fill_hw_ctxt(struct qdma_descq_hw_ctxt *hw_ctxt) -{ - qdma_cpm4_hw_ctxt_entries[0].value = hw_ctxt->cidx; - qdma_cpm4_hw_ctxt_entries[1].value = hw_ctxt->crd_use; - qdma_cpm4_hw_ctxt_entries[2].value = hw_ctxt->dsc_pend; - qdma_cpm4_hw_ctxt_entries[3].value = hw_ctxt->idl_stp_b; - qdma_cpm4_hw_ctxt_entries[4].value = hw_ctxt->evt_pnd; - qdma_cpm4_hw_ctxt_entries[5].value = hw_ctxt->fetch_pnd; -} - -/* - * qdma_acc_fill_credit_ctxt() - Helper function to fill Credit context - * into structure - * - */ -static void qdma_cpm4_fill_credit_ctxt( - struct qdma_descq_credit_ctxt *cr_ctxt) -{ - qdma_cpm4_credit_ctxt_entries[0].value = cr_ctxt->credit; -} - -/* - * qdma_acc_fill_pfetch_ctxt() - Helper function to fill Prefetch context - * into structure - * - */ -static void qdma_cpm4_fill_pfetch_ctxt( - struct qdma_descq_prefetch_ctxt *pfetch_ctxt) -{ - qdma_cpm4_c2h_pftch_ctxt_entries[0].value = pfetch_ctxt->bypass; - qdma_cpm4_c2h_pftch_ctxt_entries[1].value = pfetch_ctxt->bufsz_idx; - qdma_cpm4_c2h_pftch_ctxt_entries[2].value = pfetch_ctxt->port_id; - qdma_cpm4_c2h_pftch_ctxt_entries[3].value = pfetch_ctxt->err; - qdma_cpm4_c2h_pftch_ctxt_entries[4].value = pfetch_ctxt->pfch_en; - qdma_cpm4_c2h_pftch_ctxt_entries[5].value = pfetch_ctxt->pfch; - qdma_cpm4_c2h_pftch_ctxt_entries[6].value = pfetch_ctxt->sw_crdt; - qdma_cpm4_c2h_pftch_ctxt_entries[7].value = pfetch_ctxt->valid; -} - -/* - * qdma_cpm4_fill_fmap_ctxt() - Helper function to fill fmap context - * into structure - * - */ -static void qdma_cpm4_fill_fmap_ctxt(struct qdma_fmap_cfg *fmap_ctxt) -{ - qdma_cpm4_fmap_ctxt_entries[0].value = fmap_ctxt->qbase; - qdma_cpm4_fmap_ctxt_entries[1].value = fmap_ctxt->qmax; -} - -static void qdma_cpm4_fill_qid2vec_ctxt(struct qdma_qid2vec *qid2vec_ctxt) -{ - qdma_cpm4_qid2vec_ctxt_entries[0].value = qid2vec_ctxt->c2h_vector; - qdma_cpm4_qid2vec_ctxt_entries[1].value = qid2vec_ctxt->c2h_en_coal; - qdma_cpm4_qid2vec_ctxt_entries[2].value = qid2vec_ctxt->h2c_vector; - qdma_cpm4_qid2vec_ctxt_entries[3].value = qid2vec_ctxt->h2c_en_coal; -} - -static void qdma_cpm4_fill_intr_ctxt( - struct qdma_indirect_intr_ctxt *intr_ctxt) -{ - qdma_cpm4_ind_intr_ctxt_entries[0].value = intr_ctxt->valid; - qdma_cpm4_ind_intr_ctxt_entries[1].value = intr_ctxt->vec; - qdma_cpm4_ind_intr_ctxt_entries[2].value = intr_ctxt->int_st; - qdma_cpm4_ind_intr_ctxt_entries[3].value = intr_ctxt->color; - qdma_cpm4_ind_intr_ctxt_entries[4].value = - intr_ctxt->baddr_4k & 0xFFFFFFFF; - qdma_cpm4_ind_intr_ctxt_entries[5].value = - (intr_ctxt->baddr_4k >> 32) & 0xFFFFFFFF; - qdma_cpm4_ind_intr_ctxt_entries[6].value = intr_ctxt->page_size; - qdma_cpm4_ind_intr_ctxt_entries[7].value = intr_ctxt->pidx; -} - -/* - * dump_cpm4_context() - Helper function to dump queue context into string - * - * return len - length of the string copied into buffer - */ -static int dump_cpm4_context(struct qdma_descq_context *queue_context, - uint8_t st, enum qdma_dev_q_type q_type, - char *buf, int buf_sz) -{ - int i = 0; - int n; - int len = 0; - int rv; - char banner[DEBGFS_LINE_SZ] = ""; - - if (queue_context == NULL) { - qdma_log_error("%s: queue_context is NULL, err:%d\n", - __func__, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - if (q_type >= QDMA_DEV_Q_TYPE_CMPT) { - qdma_log_error("%s: Invalid queue type(%d), err:%d\n", - __func__, - q_type, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - qdma_cpm4_fill_sw_ctxt(&queue_context->sw_ctxt); - qdma_cpm4_fill_hw_ctxt(&queue_context->hw_ctxt); - qdma_cpm4_fill_credit_ctxt(&queue_context->cr_ctxt); - qdma_cpm4_fill_qid2vec_ctxt(&queue_context->qid2vec); - if (st && (q_type == QDMA_DEV_Q_TYPE_C2H)) { - qdma_cpm4_fill_pfetch_ctxt(&queue_context->pfetch_ctxt); - qdma_cpm4_fill_cmpt_ctxt(&queue_context->cmpt_ctxt); - } - - qdma_cpm4_fill_fmap_ctxt(&queue_context->fmap); - - if (q_type != QDMA_DEV_Q_TYPE_CMPT) { - for (i = 0; i < DEBGFS_LINE_SZ - 5; i++) { - rv = QDMA_SNPRINTF_S(banner + i, - (DEBGFS_LINE_SZ - i), - sizeof("-"), "-"); - if ((rv < 0) || (rv > (int)sizeof("-"))) { - qdma_log_error( - "%d:%s QDMA_SNPRINTF_S() failed, err:%d\n", - __LINE__, __func__, - rv); - goto INSUF_BUF_EXIT; - } - } - - /* SW context dump */ - n = sizeof(qdma_cpm4_sw_ctxt_entries) / - sizeof((qdma_cpm4_sw_ctxt_entries)[0]); - for (i = 0; i < n; i++) { - if ((len >= buf_sz) || - ((len + DEBGFS_LINE_SZ) >= buf_sz)) - goto INSUF_BUF_EXIT; - - if (i == 0) { - if ((len + (3 * DEBGFS_LINE_SZ)) >= buf_sz) - goto INSUF_BUF_EXIT; - rv = QDMA_SNPRINTF_S(buf + len, (buf_sz - len), - DEBGFS_LINE_SZ, "\n%s", banner); - if ((rv < 0) || (rv > DEBGFS_LINE_SZ)) { - qdma_log_error( - "%d:%s QDMA_SNPRINTF_S() failed, err:%d\n", - __LINE__, __func__, - rv); - goto INSUF_BUF_EXIT; - } - len += rv; - - rv = QDMA_SNPRINTF_S(buf + len, (buf_sz - len), - DEBGFS_LINE_SZ, "\n%40s", "SW Context"); - if ((rv < 0) || (rv > DEBGFS_LINE_SZ)) { - qdma_log_error( - "%d:%s QDMA_SNPRINTF_S() failed, err:%d\n", - __LINE__, __func__, - rv); - goto INSUF_BUF_EXIT; - } - len += rv; - - rv = QDMA_SNPRINTF_S(buf + len, (buf_sz - len), - DEBGFS_LINE_SZ, "\n%s\n", banner); - if ((rv < 0) || (rv > DEBGFS_LINE_SZ)) { - qdma_log_error( - "%d:%s QDMA_SNPRINTF_S() failed, err:%d\n", - __LINE__, __func__, - rv); - goto INSUF_BUF_EXIT; - } - len += rv; - } - - rv = QDMA_SNPRINTF_S(buf + len, (buf_sz - len), - DEBGFS_LINE_SZ, - "%-47s %#-10x %u\n", - qdma_cpm4_sw_ctxt_entries[i].name, - qdma_cpm4_sw_ctxt_entries[i].value, - qdma_cpm4_sw_ctxt_entries[i].value); - if ((rv < 0) || (rv > DEBGFS_LINE_SZ)) { - qdma_log_error( - "%d:%s QDMA_SNPRINTF_S() failed, err:%d\n", - __LINE__, __func__, - rv); - goto INSUF_BUF_EXIT; - } - len += rv; - } - - /* HW context dump */ - n = sizeof(qdma_cpm4_hw_ctxt_entries) / - sizeof((qdma_cpm4_hw_ctxt_entries)[0]); - for (i = 0; i < n; i++) { - if ((len >= buf_sz) || - ((len + DEBGFS_LINE_SZ) >= buf_sz)) - goto INSUF_BUF_EXIT; - - if (i == 0) { - if ((len + (3 * DEBGFS_LINE_SZ)) >= buf_sz) - goto INSUF_BUF_EXIT; - - rv = QDMA_SNPRINTF_S(buf + len, (buf_sz - len), - DEBGFS_LINE_SZ, "\n%s", banner); - if ((rv < 0) || (rv > DEBGFS_LINE_SZ)) { - qdma_log_error( - "%d:%s QDMA_SNPRINTF_S() failed, err:%d\n", - __LINE__, __func__, - rv); - goto INSUF_BUF_EXIT; - } - len += rv; - - rv = QDMA_SNPRINTF_S(buf + len, (buf_sz - len), - DEBGFS_LINE_SZ, "\n%40s", "HW Context"); - if ((rv < 0) || (rv > DEBGFS_LINE_SZ)) { - qdma_log_error( - "%d:%s QDMA_SNPRINTF_S() failed, err:%d\n", - __LINE__, __func__, - rv); - goto INSUF_BUF_EXIT; - } - len += rv; - - rv = QDMA_SNPRINTF_S(buf + len, (buf_sz - len), - DEBGFS_LINE_SZ, "\n%s\n", banner); - if ((rv < 0) || (rv > DEBGFS_LINE_SZ)) { - qdma_log_error( - "%d:%s QDMA_SNPRINTF_S() failed, err:%d\n", - __LINE__, __func__, - rv); - goto INSUF_BUF_EXIT; - } - len += rv; - } - - rv = QDMA_SNPRINTF_S(buf + len, (buf_sz - len), - DEBGFS_LINE_SZ, - "%-47s %#-10x %u\n", - qdma_cpm4_hw_ctxt_entries[i].name, - qdma_cpm4_hw_ctxt_entries[i].value, - qdma_cpm4_hw_ctxt_entries[i].value); - if ((rv < 0) || (rv > DEBGFS_LINE_SZ)) { - qdma_log_error( - "%d:%s QDMA_SNPRINTF_S() failed, err:%d\n", - __LINE__, __func__, - rv); - goto INSUF_BUF_EXIT; - } - len += rv; - } - - /* Credit context dump */ - n = sizeof(qdma_cpm4_credit_ctxt_entries) / - sizeof((qdma_cpm4_credit_ctxt_entries)[0]); - for (i = 0; i < n; i++) { - if ((len >= buf_sz) || - ((len + DEBGFS_LINE_SZ) >= buf_sz)) - goto INSUF_BUF_EXIT; - - if (i == 0) { - if ((len + (3 * DEBGFS_LINE_SZ)) >= buf_sz) - goto INSUF_BUF_EXIT; - - rv = QDMA_SNPRINTF_S(buf + len, (buf_sz - len), - DEBGFS_LINE_SZ, "\n%s", banner); - if ((rv < 0) || (rv > DEBGFS_LINE_SZ)) { - qdma_log_error( - "%d:%s QDMA_SNPRINTF_S() failed, err:%d\n", - __LINE__, __func__, - rv); - goto INSUF_BUF_EXIT; - } - len += rv; - - rv = QDMA_SNPRINTF_S(buf + len, (buf_sz - len), - DEBGFS_LINE_SZ, "\n%40s", - "Credit Context"); - if ((rv < 0) || (rv > DEBGFS_LINE_SZ)) { - qdma_log_error( - "%d:%s QDMA_SNPRINTF_S() failed, err:%d\n", - __LINE__, __func__, - rv); - goto INSUF_BUF_EXIT; - } - len += rv; - - rv = QDMA_SNPRINTF_S(buf + len, (buf_sz - len), - DEBGFS_LINE_SZ, "\n%s\n", banner); - if ((rv < 0) || (rv > DEBGFS_LINE_SZ)) { - qdma_log_error( - "%d:%s QDMA_SNPRINTF_S() failed, err:%d\n", - __LINE__, __func__, - rv); - goto INSUF_BUF_EXIT; - } - len += rv; - } - - rv = QDMA_SNPRINTF_S(buf + len, (buf_sz - len), - DEBGFS_LINE_SZ, - "%-47s %#-10x %u\n", - qdma_cpm4_credit_ctxt_entries[i].name, - qdma_cpm4_credit_ctxt_entries[i].value, - qdma_cpm4_credit_ctxt_entries[i].value); - if ((rv < 0) || (rv > DEBGFS_LINE_SZ)) { - qdma_log_error( - "%d:%s QDMA_SNPRINTF_S() failed, err:%d\n", - __LINE__, __func__, - rv); - goto INSUF_BUF_EXIT; - } - len += rv; - } - } - - /* SW context dump */ - n = sizeof(qdma_cpm4_qid2vec_ctxt_entries) / - sizeof((qdma_cpm4_qid2vec_ctxt_entries)[0]); - for (i = 0; i < n; i++) { - if ((len >= buf_sz) || - ((len + DEBGFS_LINE_SZ) >= buf_sz)) - goto INSUF_BUF_EXIT; - - if (i == 0) { - if ((len + (3 * DEBGFS_LINE_SZ)) >= buf_sz) - goto INSUF_BUF_EXIT; - rv = QDMA_SNPRINTF_S(buf + len, (buf_sz - len), - DEBGFS_LINE_SZ, "\n%s", banner); - if ((rv < 0) || (rv > DEBGFS_LINE_SZ)) { - qdma_log_error( - "%d:%s QDMA_SNPRINTF_S() failed, err:%d\n", - __LINE__, __func__, - rv); - goto INSUF_BUF_EXIT; - } - len += rv; - - rv = QDMA_SNPRINTF_S(buf + len, (buf_sz - len), - DEBGFS_LINE_SZ, "\n%40s", - "QID2VEC Context"); - if ((rv < 0) || (rv > DEBGFS_LINE_SZ)) { - qdma_log_error( - "%d:%s QDMA_SNPRINTF_S() failed, err:%d\n", - __LINE__, __func__, - rv); - goto INSUF_BUF_EXIT; - } - len += rv; - - rv = QDMA_SNPRINTF_S(buf + len, (buf_sz - len), - DEBGFS_LINE_SZ, "\n%s\n", banner); - if ((rv < 0) || (rv > DEBGFS_LINE_SZ)) { - qdma_log_error( - "%d:%s QDMA_SNPRINTF_S() failed, err:%d\n", - __LINE__, __func__, - rv); - goto INSUF_BUF_EXIT; - } - len += rv; - } - - rv = QDMA_SNPRINTF_S(buf + len, (buf_sz - len), DEBGFS_LINE_SZ, - "%-47s %#-10x %u\n", - qdma_cpm4_qid2vec_ctxt_entries[i].name, - qdma_cpm4_qid2vec_ctxt_entries[i].value, - qdma_cpm4_qid2vec_ctxt_entries[i].value); - if ((rv < 0) || (rv > DEBGFS_LINE_SZ)) { - qdma_log_error( - "%d:%s QDMA_SNPRINTF_S() failed, err:%d\n", - __LINE__, __func__, - rv); - goto INSUF_BUF_EXIT; - } - len += rv; - } - - - if ((q_type == QDMA_DEV_Q_TYPE_CMPT) || - (st && q_type == QDMA_DEV_Q_TYPE_C2H)) { - /* Completion context dump */ - n = sizeof(qdma_cpm4_cmpt_ctxt_entries) / - sizeof((qdma_cpm4_cmpt_ctxt_entries)[0]); - for (i = 0; i < n; i++) { - if ((len >= buf_sz) || - ((len + DEBGFS_LINE_SZ) >= buf_sz)) - goto INSUF_BUF_EXIT; - - if (i == 0) { - if ((len + (3 * DEBGFS_LINE_SZ)) >= buf_sz) - goto INSUF_BUF_EXIT; - - rv = QDMA_SNPRINTF_S(buf + len, (buf_sz - len), - DEBGFS_LINE_SZ, "\n%s", banner); - if ((rv < 0) || (rv > DEBGFS_LINE_SZ)) { - qdma_log_error( - "%d:%s QDMA_SNPRINTF_S() failed, err:%d\n", - __LINE__, __func__, - rv); - goto INSUF_BUF_EXIT; - } - len += rv; - - rv = QDMA_SNPRINTF_S(buf + len, (buf_sz - len), - DEBGFS_LINE_SZ, "\n%40s", - "Completion Context"); - if ((rv < 0) || (rv > DEBGFS_LINE_SZ)) { - qdma_log_error( - "%d:%s QDMA_SNPRINTF_S() failed, err:%d\n", - __LINE__, __func__, - rv); - goto INSUF_BUF_EXIT; - } - len += rv; - - rv = QDMA_SNPRINTF_S(buf + len, (buf_sz - len), - DEBGFS_LINE_SZ, "\n%s\n", banner); - if ((rv < 0) || (rv > DEBGFS_LINE_SZ)) { - qdma_log_error( - "%d:%s QDMA_SNPRINTF_S() failed, err:%d\n", - __LINE__, __func__, - rv); - goto INSUF_BUF_EXIT; - } - len += rv; - } - - rv = QDMA_SNPRINTF_S(buf + len, (buf_sz - len), - DEBGFS_LINE_SZ, - "%-47s %#-10x %u\n", - qdma_cpm4_cmpt_ctxt_entries[i].name, - qdma_cpm4_cmpt_ctxt_entries[i].value, - qdma_cpm4_cmpt_ctxt_entries[i].value); - if ((rv < 0) || (rv > DEBGFS_LINE_SZ)) { - qdma_log_error( - "%d:%s QDMA_SNPRINTF_S() failed, err:%d\n", - __LINE__, __func__, - rv); - goto INSUF_BUF_EXIT; - } - len += rv; - } - } - - if (st && q_type == QDMA_DEV_Q_TYPE_C2H) { - /* Prefetch context dump */ - n = sizeof(qdma_cpm4_c2h_pftch_ctxt_entries) / - sizeof(qdma_cpm4_c2h_pftch_ctxt_entries[0]); - for (i = 0; i < n; i++) { - if ((len >= buf_sz) || - ((len + DEBGFS_LINE_SZ) >= buf_sz)) - goto INSUF_BUF_EXIT; - - if (i == 0) { - if ((len + (3 * DEBGFS_LINE_SZ)) >= buf_sz) - goto INSUF_BUF_EXIT; - - rv = QDMA_SNPRINTF_S(buf + len, (buf_sz - len), - DEBGFS_LINE_SZ, "\n%s", banner); - if ((rv < 0) || (rv > DEBGFS_LINE_SZ)) { - qdma_log_error( - "%d:%s QDMA_SNPRINTF_S() failed, err:%d\n", - __LINE__, __func__, - rv); - goto INSUF_BUF_EXIT; - } - len += rv; - - rv = QDMA_SNPRINTF_S(buf + len, (buf_sz - len), - DEBGFS_LINE_SZ, "\n%40s", - "Prefetch Context"); - if ((rv < 0) || (rv > DEBGFS_LINE_SZ)) { - qdma_log_error( - "%d:%s QDMA_SNPRINTF_S() failed, err:%d\n", - __LINE__, __func__, - rv); - goto INSUF_BUF_EXIT; - } - len += rv; - - rv = QDMA_SNPRINTF_S(buf + len, (buf_sz - len), - DEBGFS_LINE_SZ, "\n%s\n", banner); - if ((rv < 0) || (rv > DEBGFS_LINE_SZ)) { - qdma_log_error( - "%d:%s QDMA_SNPRINTF_S() failed, err:%d\n", - __LINE__, __func__, - rv); - goto INSUF_BUF_EXIT; - } - len += rv; - } - - rv = QDMA_SNPRINTF_S(buf + len, (buf_sz - len), - DEBGFS_LINE_SZ, - "%-47s %#-10x %u\n", - qdma_cpm4_c2h_pftch_ctxt_entries[i].name, - qdma_cpm4_c2h_pftch_ctxt_entries[i].value, - qdma_cpm4_c2h_pftch_ctxt_entries[i].value); - if ((rv < 0) || (rv > DEBGFS_LINE_SZ)) { - qdma_log_error( - "%d:%s QDMA_SNPRINTF_S() failed, err:%d\n", - __LINE__, __func__, - rv); - goto INSUF_BUF_EXIT; - } - len += rv; - } - } - - /* Fmap context dump */ - n = sizeof(qdma_cpm4_fmap_ctxt_entries) / - sizeof(qdma_cpm4_fmap_ctxt_entries[0]); - for (i = 0; i < n; i++) { - if ((len >= buf_sz) || - ((len + DEBGFS_LINE_SZ) >= buf_sz)) - goto INSUF_BUF_EXIT; - - if (i == 0) { - if ((len + (3 * DEBGFS_LINE_SZ)) >= buf_sz) - goto INSUF_BUF_EXIT; - - rv = QDMA_SNPRINTF_S(buf + len, (buf_sz - len), - DEBGFS_LINE_SZ, "\n%s", banner); - if ((rv < 0) || (rv > DEBGFS_LINE_SZ)) { - qdma_log_error( - "%d:%s QDMA_SNPRINTF_S() failed, err:%d\n", - __LINE__, __func__, - rv); - goto INSUF_BUF_EXIT; - } - len += rv; - - rv = QDMA_SNPRINTF_S(buf + len, (buf_sz - len), - DEBGFS_LINE_SZ, "\n%40s", - "Fmap Context"); - if ((rv < 0) || (rv > DEBGFS_LINE_SZ)) { - qdma_log_error( - "%d:%s QDMA_SNPRINTF_S() failed, err:%d\n", - __LINE__, __func__, - rv); - goto INSUF_BUF_EXIT; - } - len += rv; - - rv = QDMA_SNPRINTF_S(buf + len, (buf_sz - len), - DEBGFS_LINE_SZ, "\n%s\n", banner); - if ((rv < 0) || (rv > DEBGFS_LINE_SZ)) { - qdma_log_error( - "%d:%s QDMA_SNPRINTF_S() failed, err:%d\n", - __LINE__, __func__, - rv); - goto INSUF_BUF_EXIT; - } - len += rv; - } - - rv = QDMA_SNPRINTF_S(buf + len, - (buf_sz - len), DEBGFS_LINE_SZ, - "%-47s %#-10x %u\n", - qdma_cpm4_fmap_ctxt_entries[i].name, - qdma_cpm4_fmap_ctxt_entries[i].value, - qdma_cpm4_fmap_ctxt_entries[i].value); - if ((rv < 0) || (rv > DEBGFS_LINE_SZ)) { - qdma_log_error( - "%d:%s QDMA_SNPRINTF_S() failed, err:%d\n", - __LINE__, __func__, - rv); - goto INSUF_BUF_EXIT; - } - len += rv; - } - - return len; - -INSUF_BUF_EXIT: - if (buf_sz > DEBGFS_LINE_SZ) { - rv = QDMA_SNPRINTF_S((buf + buf_sz - DEBGFS_LINE_SZ), - buf_sz, DEBGFS_LINE_SZ, - "\n\nInsufficient buffer size, partial context dump\n"); - if ((rv < 0) || (rv > DEBGFS_LINE_SZ)) { - qdma_log_error( - "%d:%s QDMA_SNPRINTF_S() failed, err:%d\n", - __LINE__, __func__, - rv); - } - } - - qdma_log_error("%s: Insufficient buffer size, err:%d\n", - __func__, -QDMA_ERR_NO_MEM); - - return -QDMA_ERR_NO_MEM; -} - -static int dump_cpm4_intr_context(struct qdma_indirect_intr_ctxt *intr_ctx, - int ring_index, - char *buf, int buf_sz) -{ - int i = 0; - int n; - int len = 0; - int rv; - char banner[DEBGFS_LINE_SZ] = ""; - - qdma_cpm4_fill_intr_ctxt(intr_ctx); - - for (i = 0; i < DEBGFS_LINE_SZ - 5; i++) { - rv = QDMA_SNPRINTF_S(banner + i, - (DEBGFS_LINE_SZ - i), - sizeof("-"), "-"); - if ((rv < 0) || (rv > (int)sizeof("-"))) { - qdma_log_error( - "%d:%s QDMA_SNPRINTF_S() failed, err:%d\n", - __LINE__, __func__, - rv); - goto INSUF_BUF_EXIT; - } - } - - /* Interrupt context dump */ - n = sizeof(qdma_cpm4_ind_intr_ctxt_entries) / - sizeof((qdma_cpm4_ind_intr_ctxt_entries)[0]); - for (i = 0; i < n; i++) { - if ((len >= buf_sz) || ((len + DEBGFS_LINE_SZ) >= buf_sz)) - goto INSUF_BUF_EXIT; - - if (i == 0) { - if ((len + (3 * DEBGFS_LINE_SZ)) >= buf_sz) - goto INSUF_BUF_EXIT; - - rv = QDMA_SNPRINTF_S(buf + len, (buf_sz - len), - DEBGFS_LINE_SZ, "\n%s", banner); - if ((rv < 0) || (rv > DEBGFS_LINE_SZ)) { - qdma_log_error( - "%d:%s QDMA_SNPRINTF_S() failed, err:%d\n", - __LINE__, __func__, - rv); - goto INSUF_BUF_EXIT; - } - len += rv; - - rv = QDMA_SNPRINTF_S(buf + len, (buf_sz - len), - DEBGFS_LINE_SZ, "\n%50s %d", - "Interrupt Context for ring#", ring_index); - if ((rv < 0) || (rv > DEBGFS_LINE_SZ)) { - qdma_log_error( - "%d:%s QDMA_SNPRINTF_S() failed, err:%d\n", - __LINE__, __func__, - rv); - goto INSUF_BUF_EXIT; - } - len += rv; - - rv = QDMA_SNPRINTF_S(buf + len, (buf_sz - len), - DEBGFS_LINE_SZ, "\n%s\n", banner); - if ((rv < 0) || (rv > DEBGFS_LINE_SZ)) { - qdma_log_error( - "%d:%s QDMA_SNPRINTF_S() failed, err:%d\n", - __LINE__, __func__, - rv); - goto INSUF_BUF_EXIT; - } - len += rv; - } - - rv = QDMA_SNPRINTF_S(buf + len, (buf_sz - len), DEBGFS_LINE_SZ, - "%-47s %#-10x %u\n", - qdma_cpm4_ind_intr_ctxt_entries[i].name, - qdma_cpm4_ind_intr_ctxt_entries[i].value, - qdma_cpm4_ind_intr_ctxt_entries[i].value); - if ((rv < 0) || (rv > DEBGFS_LINE_SZ)) { - qdma_log_error( - "%d:%s QDMA_SNPRINTF_S() failed, err:%d\n", - __LINE__, __func__, - rv); - goto INSUF_BUF_EXIT; - } - len += rv; - } - - return len; - -INSUF_BUF_EXIT: - if (buf_sz > DEBGFS_LINE_SZ) { - rv = QDMA_SNPRINTF_S((buf + buf_sz - DEBGFS_LINE_SZ), - buf_sz, DEBGFS_LINE_SZ, - "\n\nInsufficient buffer size, partial intr context dump\n"); - if ((rv < 0) || (rv > DEBGFS_LINE_SZ)) { - qdma_log_error( - "%d:%s QDMA_SNPRINTF_S() failed, err:%d\n", - __LINE__, __func__, - rv); - } - } - - qdma_log_error("%s: Insufficient buffer size, err:%d\n", - __func__, -QDMA_ERR_NO_MEM); - - return -QDMA_ERR_NO_MEM; -} - -/* - * qdma_cpm4_indirect_reg_invalidate() - helper function to invalidate - * indirect context registers. - * - * return -QDMA_ERR_HWACC_BUSY_TIMEOUT if register - * value didn't match, QDMA_SUCCESS other wise - */ -static int qdma_cpm4_indirect_reg_invalidate(void *dev_hndl, - enum ind_ctxt_cmd_sel sel, uint16_t hw_qid) -{ - union qdma_cpm4_ind_ctxt_cmd cmd; - - qdma_reg_access_lock(dev_hndl); - - /* set command register */ - cmd.word = 0; - cmd.bits.qid = hw_qid; - cmd.bits.op = QDMA_CTXT_CMD_INV; - cmd.bits.sel = sel; - qdma_reg_write(dev_hndl, QDMA_CPM4_IND_CTXT_CMD_ADDR, cmd.word); - - /* check if the operation went through well */ - if (hw_monitor_reg(dev_hndl, QDMA_CPM4_IND_CTXT_CMD_ADDR, - IND_CTXT_CMD_BUSY_MASK, 0, - QDMA_REG_POLL_DFLT_INTERVAL_US, - QDMA_REG_POLL_DFLT_TIMEOUT_US)) { - qdma_reg_access_release(dev_hndl); - qdma_log_error("%s: hw_monitor_reg failed, err:%d\n", - __func__, - -QDMA_ERR_HWACC_BUSY_TIMEOUT); - return -QDMA_ERR_HWACC_BUSY_TIMEOUT; - } - - qdma_reg_access_release(dev_hndl); - - return QDMA_SUCCESS; -} - -/* - * qdma_cpm4_indirect_reg_clear() - helper function to clear indirect - * context registers. - * - * return -QDMA_ERR_HWACC_BUSY_TIMEOUT if register - * value didn't match, QDMA_SUCCESS other wise - */ -static int qdma_cpm4_indirect_reg_clear(void *dev_hndl, - enum ind_ctxt_cmd_sel sel, uint16_t hw_qid) -{ - union qdma_cpm4_ind_ctxt_cmd cmd; - - qdma_reg_access_lock(dev_hndl); - - /* set command register */ - cmd.word = 0; - cmd.bits.qid = hw_qid; - cmd.bits.op = QDMA_CTXT_CMD_CLR; - cmd.bits.sel = sel; - - qdma_reg_write(dev_hndl, QDMA_CPM4_IND_CTXT_CMD_ADDR, cmd.word); - - /* check if the operation went through well */ - if (hw_monitor_reg(dev_hndl, QDMA_CPM4_IND_CTXT_CMD_ADDR, - IND_CTXT_CMD_BUSY_MASK, 0, - QDMA_REG_POLL_DFLT_INTERVAL_US, - QDMA_REG_POLL_DFLT_TIMEOUT_US)) { - qdma_reg_access_release(dev_hndl); - qdma_log_error("%s: hw_monitor_reg failed, err:%d\n", - __func__, - -QDMA_ERR_HWACC_BUSY_TIMEOUT); - return -QDMA_ERR_HWACC_BUSY_TIMEOUT; - } - - qdma_reg_access_release(dev_hndl); - - return QDMA_SUCCESS; -} - -/* - * qdma_cpm4_indirect_reg_read() - helper function to read indirect - * context registers. - * - * return -QDMA_ERR_HWACC_BUSY_TIMEOUT if register - * value didn't match, QDMA_SUCCESS other wise - */ -static int qdma_cpm4_indirect_reg_read(void *dev_hndl, - enum ind_ctxt_cmd_sel sel, - uint16_t hw_qid, uint32_t cnt, uint32_t *data) -{ - uint32_t index = 0, reg_addr = QDMA_CPM4_IND_CTXT_DATA_3_ADDR; - union qdma_cpm4_ind_ctxt_cmd cmd; - - qdma_reg_access_lock(dev_hndl); - - /* set command register */ - cmd.word = 0; - cmd.bits.qid = hw_qid; - cmd.bits.op = QDMA_CTXT_CMD_RD; - cmd.bits.sel = sel; - qdma_reg_write(dev_hndl, QDMA_CPM4_IND_CTXT_CMD_ADDR, cmd.word); - - /* check if the operation went through well */ - if (hw_monitor_reg(dev_hndl, QDMA_CPM4_IND_CTXT_CMD_ADDR, - IND_CTXT_CMD_BUSY_MASK, 0, - QDMA_REG_POLL_DFLT_INTERVAL_US, - QDMA_REG_POLL_DFLT_TIMEOUT_US)) { - qdma_reg_access_release(dev_hndl); - qdma_log_error("%s: hw_monitor_reg failed, err:%d\n", - __func__, - -QDMA_ERR_HWACC_BUSY_TIMEOUT); - return -QDMA_ERR_HWACC_BUSY_TIMEOUT; - } - - for (index = 0; index < cnt; index++, reg_addr += sizeof(uint32_t)) - data[index] = qdma_reg_read(dev_hndl, reg_addr); - - qdma_reg_access_release(dev_hndl); - - return QDMA_SUCCESS; -} - -/* - * qdma_cpm4_indirect_reg_write() - helper function to write indirect - * context registers. - * - * return -QDMA_ERR_HWACC_BUSY_TIMEOUT if register - * value didn't match, QDMA_SUCCESS other wise - */ -static int qdma_cpm4_indirect_reg_write(void *dev_hndl, - enum ind_ctxt_cmd_sel sel, - uint16_t hw_qid, uint32_t *data, uint16_t cnt) -{ - uint32_t index, reg_addr; - struct qdma_cpm4_indirect_ctxt_regs regs; - uint32_t *wr_data = (uint32_t *)®s; - - qdma_reg_access_lock(dev_hndl); - - /* write the context data */ - for (index = 0; index < QDMA_CPM4_IND_CTXT_DATA_NUM_REGS; - index++) { - if (index < cnt) - regs.qdma_ind_ctxt_data[index] = data[index]; - else - regs.qdma_ind_ctxt_data[index] = 0; - regs.qdma_ind_ctxt_mask[index] = 0xFFFFFFFF; - } - - regs.cmd.word = 0; - regs.cmd.bits.qid = hw_qid; - regs.cmd.bits.op = QDMA_CTXT_CMD_WR; - regs.cmd.bits.sel = sel; - reg_addr = QDMA_CPM4_IND_CTXT_DATA_3_ADDR; - - for (index = 0; - index < ((2 * QDMA_CPM4_IND_CTXT_DATA_NUM_REGS) + 1); - index++, reg_addr += sizeof(uint32_t)) - qdma_reg_write(dev_hndl, reg_addr, wr_data[index]); - - /* check if the operation went through well */ - if (hw_monitor_reg(dev_hndl, QDMA_CPM4_IND_CTXT_CMD_ADDR, - IND_CTXT_CMD_BUSY_MASK, 0, - QDMA_REG_POLL_DFLT_INTERVAL_US, - QDMA_REG_POLL_DFLT_TIMEOUT_US)) { - qdma_reg_access_release(dev_hndl); - qdma_log_error("%s: hw_monitor_reg failed, err:%d\n", - __func__, - -QDMA_ERR_HWACC_BUSY_TIMEOUT); - return -QDMA_ERR_HWACC_BUSY_TIMEOUT; - } - - qdma_reg_access_release(dev_hndl); - - return QDMA_SUCCESS; -} - -/*****************************************************************************/ -/** - * qdma_cpm4_qid2vec_write() - create qid2vec context and program it - * - * @dev_hndl: device handle - * @c2h: is c2h queue - * @hw_qid: hardware qid of the queue - * @ctxt: pointer to the context data - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -static int qdma_cpm4_qid2vec_write(void *dev_hndl, uint8_t c2h, - uint16_t hw_qid, struct qdma_qid2vec *ctxt) -{ - uint32_t qid2vec = 0; - enum ind_ctxt_cmd_sel sel = QDMA_CTXT_SEL_FMAP; - int rv = 0; - - if (!dev_hndl || !ctxt) { - qdma_log_error("%s: dev_hndl=%p qid2vec=%p, err:%d\n", - __func__, dev_hndl, ctxt, -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - rv = qdma_cpm4_indirect_reg_read(dev_hndl, sel, hw_qid, - 1, &qid2vec); - if (rv < 0) - return rv; - if (c2h) { - qid2vec = qid2vec & (QDMA_CPM4_QID2VEC_H2C_VECTOR | - QDMA_CPM4_QID2VEC_H2C_COAL_EN); - qid2vec |= FIELD_SET(C2H_QID2VEC_MAP_C2H_VECTOR_MASK, - ctxt->c2h_vector) | - FIELD_SET(C2H_QID2VEC_MAP_C2H_EN_COAL_MASK, - ctxt->c2h_en_coal); - } else { - qid2vec = qid2vec & (C2H_QID2VEC_MAP_C2H_VECTOR_MASK | - C2H_QID2VEC_MAP_C2H_EN_COAL_MASK); - qid2vec |= - FIELD_SET(QDMA_CPM4_QID2VEC_H2C_VECTOR, - ctxt->h2c_vector) | - FIELD_SET(QDMA_CPM4_QID2VEC_H2C_COAL_EN, - ctxt->h2c_en_coal); - } - - return qdma_cpm4_indirect_reg_write(dev_hndl, sel, hw_qid, - &qid2vec, QDMA_CPM4_QID2VEC_CONTEXT_NUM_WORDS); - -} - -/*****************************************************************************/ -/** - * qdma_cpm4_qid2vec_read() - read qid2vec context - * - * @dev_hndl: device handle - * @c2h: is c2h queue - * @hw_qid: hardware qid of the queue - * @ctxt: pointer to the context data - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -static int qdma_cpm4_qid2vec_read(void *dev_hndl, uint8_t c2h, - uint16_t hw_qid, struct qdma_qid2vec *ctxt) -{ - int rv = 0; - uint32_t qid2vec[QDMA_CPM4_QID2VEC_CONTEXT_NUM_WORDS] = {0}; - enum ind_ctxt_cmd_sel sel = QDMA_CTXT_SEL_FMAP; - - if (!dev_hndl || !ctxt) { - qdma_log_error("%s: dev_hndl=%p qid2vec=%p, err:%d\n", - __func__, dev_hndl, ctxt, -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - rv = qdma_cpm4_indirect_reg_read(dev_hndl, sel, hw_qid, - QDMA_CPM4_QID2VEC_CONTEXT_NUM_WORDS, qid2vec); - if (rv < 0) - return rv; - - if (c2h) { - ctxt->c2h_vector = FIELD_GET(C2H_QID2VEC_MAP_C2H_VECTOR_MASK, - qid2vec[0]); - ctxt->c2h_en_coal = - (uint8_t)(FIELD_GET(C2H_QID2VEC_MAP_C2H_EN_COAL_MASK, - qid2vec[0])); - } else { - ctxt->h2c_vector = - (uint8_t)(FIELD_GET(QDMA_CPM4_QID2VEC_H2C_VECTOR, - qid2vec[0])); - ctxt->h2c_en_coal = - (uint8_t)(FIELD_GET(QDMA_CPM4_QID2VEC_H2C_COAL_EN, - qid2vec[0])); - } - - return QDMA_SUCCESS; -} - -/*****************************************************************************/ -/** - * qdma_cpm4_qid2vec_clear() - clear qid2vec context - * - * @dev_hndl: device handle - * @hw_qid: hardware qid of the queue - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -static int qdma_cpm4_qid2vec_clear(void *dev_hndl, uint16_t hw_qid) -{ - enum ind_ctxt_cmd_sel sel = QDMA_CTXT_SEL_FMAP; - - if (!dev_hndl) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - return qdma_cpm4_indirect_reg_clear(dev_hndl, sel, hw_qid); -} - -/*****************************************************************************/ -/** - * qdma_cpm4_qid2vec_invalidate() - invalidate qid2vec context - * - * @dev_hndl: device handle - * @hw_qid: hardware qid of the queue - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -static int qdma_cpm4_qid2vec_invalidate(void *dev_hndl, uint16_t hw_qid) -{ - enum ind_ctxt_cmd_sel sel = QDMA_CTXT_SEL_FMAP; - - if (!dev_hndl) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - return qdma_cpm4_indirect_reg_invalidate(dev_hndl, sel, hw_qid); -} - -/*****************************************************************************/ -/** - * qdma_cpm4_qid2vec_conf() - configure qid2vector context - * - * @dev_hndl: device handle - * @c2h: is c2h queue - * @hw_qid: hardware qid of the queue - * @ctxt: pointer to the context data - * @access_type HW access type (qdma_hw_access_type enum) value - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -int qdma_cpm4_qid2vec_conf(void *dev_hndl, uint8_t c2h, uint16_t hw_qid, - struct qdma_qid2vec *ctxt, - enum qdma_hw_access_type access_type) -{ - int ret_val = 0; - - switch (access_type) { - case QDMA_HW_ACCESS_READ: - ret_val = qdma_cpm4_qid2vec_read(dev_hndl, c2h, - hw_qid, ctxt); - break; - case QDMA_HW_ACCESS_WRITE: - ret_val = qdma_cpm4_qid2vec_write(dev_hndl, c2h, - hw_qid, ctxt); - break; - case QDMA_HW_ACCESS_CLEAR: - ret_val = qdma_cpm4_qid2vec_clear(dev_hndl, hw_qid); - break; - case QDMA_HW_ACCESS_INVALIDATE: - ret_val = qdma_cpm4_qid2vec_invalidate(dev_hndl, hw_qid); - break; - default: - qdma_log_error("%s: access_type=%d is invalid, err:%d\n", - __func__, access_type, - -QDMA_ERR_INV_PARAM); - ret_val = -QDMA_ERR_INV_PARAM; - break; - } - - return ret_val; -} - -/*****************************************************************************/ -/** - * qdma_cpm4_fmap_write() - create fmap context and program it - * - * @dev_hndl: device handle - * @func_id: function id of the device - * @config: pointer to the fmap data strucutre - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -static int qdma_cpm4_fmap_write(void *dev_hndl, uint16_t func_id, - const struct qdma_fmap_cfg *config) -{ - uint32_t fmap = 0; - - if (!dev_hndl || !config) { - qdma_log_error("%s: dev_handle or config is NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - fmap = FIELD_SET(TRQ_SEL_FMAP_0_QID_BASE_MASK, config->qbase) | - FIELD_SET(TRQ_SEL_FMAP_0_QID_MAX_MASK, - config->qmax); - - qdma_reg_write(dev_hndl, QDMA_CPM4_TRQ_SEL_FMAP_0_ADDR + - func_id * QDMA_CPM4_REG_TRQ_SEL_FMAP_STEP, - fmap); - return QDMA_SUCCESS; -} - -/*****************************************************************************/ -/** - * qdma_cpm4_fmap_read() - read fmap context - * - * @dev_hndl: device handle - * @func_id: function id of the device - * @config: pointer to the output fmap data - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -static int qdma_cpm4_fmap_read(void *dev_hndl, uint16_t func_id, - struct qdma_fmap_cfg *config) -{ - uint32_t fmap = 0; - - if (!dev_hndl || !config) { - qdma_log_error("%s: dev_handle=%p fmap=%p NULL, err:%d\n", - __func__, dev_hndl, config, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - fmap = qdma_reg_read(dev_hndl, QDMA_CPM4_TRQ_SEL_FMAP_0_ADDR + - func_id * QDMA_CPM4_REG_TRQ_SEL_FMAP_STEP); - - config->qbase = FIELD_GET(TRQ_SEL_FMAP_0_QID_BASE_MASK, fmap); - config->qmax = - (uint16_t)(FIELD_GET(TRQ_SEL_FMAP_0_QID_MAX_MASK, - fmap)); - - return QDMA_SUCCESS; -} - -/*****************************************************************************/ -/** - * qdma_cpm4_fmap_clear() - clear fmap context - * - * @dev_hndl: device handle - * @func_id: function id of the device - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -static int qdma_cpm4_fmap_clear(void *dev_hndl, uint16_t func_id) -{ - uint32_t fmap = 0; - - if (!dev_hndl) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - qdma_reg_write(dev_hndl, QDMA_CPM4_TRQ_SEL_FMAP_0_ADDR + - func_id * QDMA_CPM4_REG_TRQ_SEL_FMAP_STEP, - fmap); - - return QDMA_SUCCESS; -} - -/*****************************************************************************/ -/** - * qdma_cpm4_fmap_conf() - configure fmap context - * - * @dev_hndl: device handle - * @func_id: function id of the device - * @config: pointer to the fmap data - * @access_type HW access type (qdma_hw_access_type enum) value - * QDMA_HW_ACCESS_INVALIDATE unsupported - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -int qdma_cpm4_fmap_conf(void *dev_hndl, uint16_t func_id, - struct qdma_fmap_cfg *config, - enum qdma_hw_access_type access_type) -{ - int ret_val = 0; - - switch (access_type) { - case QDMA_HW_ACCESS_READ: - ret_val = qdma_cpm4_fmap_read(dev_hndl, func_id, config); - break; - case QDMA_HW_ACCESS_WRITE: - ret_val = qdma_cpm4_fmap_write(dev_hndl, func_id, config); - break; - case QDMA_HW_ACCESS_CLEAR: - ret_val = qdma_cpm4_fmap_clear(dev_hndl, func_id); - break; - case QDMA_HW_ACCESS_INVALIDATE: - default: - qdma_log_error("%s: access_type=%d is invalid, err:%d\n", - __func__, access_type, - -QDMA_ERR_INV_PARAM); - ret_val = -QDMA_ERR_INV_PARAM; - break; - } - - return ret_val; -} - -/*****************************************************************************/ -/** - * qdma_cpm4_sw_context_write() - create sw context and program it - * - * @dev_hndl: device handle - * @c2h: is c2h queue - * @hw_qid: hardware qid of the queue - * @ctxt: pointer to the SW context data strucutre - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -static int qdma_cpm4_sw_context_write(void *dev_hndl, uint8_t c2h, - uint16_t hw_qid, - const struct qdma_descq_sw_ctxt *ctxt) -{ - uint32_t sw_ctxt[QDMA_CPM4_SW_CONTEXT_NUM_WORDS] = {0}; - uint16_t num_words_count = 0; - enum ind_ctxt_cmd_sel sel = c2h ? - QDMA_CTXT_SEL_SW_C2H : QDMA_CTXT_SEL_SW_H2C; - - /* Input args check */ - if (!dev_hndl || !ctxt) { - qdma_log_error("%s: dev_hndl or ctxt is NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - if ((ctxt->desc_sz > QDMA_DESC_SIZE_64B) || - (ctxt->rngsz_idx >= QDMA_NUM_RING_SIZES)) { - qdma_log_error("%s: Invalid desc_sz(%d)/rngidx(%d), err:%d\n", - __func__, - ctxt->desc_sz, - ctxt->rngsz_idx, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - sw_ctxt[num_words_count++] = - FIELD_SET(SW_IND_CTXT_DATA_W0_PIDX_MASK, ctxt->pidx) | - FIELD_SET(SW_IND_CTXT_DATA_W0_IRQ_ARM_MASK, ctxt->irq_arm); - - sw_ctxt[num_words_count++] = - FIELD_SET(SW_IND_CTXT_DATA_W1_QEN_MASK, ctxt->qen) | - FIELD_SET(SW_IND_CTXT_DATA_W1_FCRD_EN_MASK, ctxt->frcd_en) | - FIELD_SET(SW_IND_CTXT_DATA_W1_WBI_CHK_MASK, ctxt->wbi_chk) | - FIELD_SET(SW_IND_CTXT_DATA_W1_WBI_INTVL_EN_MASK, - ctxt->wbi_intvl_en) | - FIELD_SET(SW_IND_CTXT_DATA_W1_FNC_ID_MASK, ctxt->fnc_id) | - FIELD_SET(SW_IND_CTXT_DATA_W1_RNG_SZ_MASK, ctxt->rngsz_idx) | - FIELD_SET(SW_IND_CTXT_DATA_W1_DSC_SZ_MASK, ctxt->desc_sz) | - FIELD_SET(SW_IND_CTXT_DATA_W1_BYPASS_MASK, ctxt->bypass) | - FIELD_SET(SW_IND_CTXT_DATA_W1_MM_CHN_MASK, ctxt->mm_chn) | - FIELD_SET(SW_IND_CTXT_DATA_W1_WBK_EN_MASK, ctxt->wbk_en) | - FIELD_SET(SW_IND_CTXT_DATA_W1_IRQ_EN_MASK, ctxt->irq_en) | - FIELD_SET(SW_IND_CTXT_DATA_W1_PORT_ID_MASK, ctxt->port_id) | - FIELD_SET(SW_IND_CTXT_DATA_W1_IRQ_NO_LAST_MASK, - ctxt->irq_no_last) | - FIELD_SET(SW_IND_CTXT_DATA_W1_ERR_MASK, ctxt->err) | - FIELD_SET(SW_IND_CTXT_DATA_W1_ERR_WB_SENT_MASK, - ctxt->err_wb_sent) | - FIELD_SET(SW_IND_CTXT_DATA_W1_IRQ_REQ_MASK, ctxt->irq_req) | - FIELD_SET(SW_IND_CTXT_DATA_W1_MRKR_DIS_MASK, ctxt->mrkr_dis) | - FIELD_SET(SW_IND_CTXT_DATA_W1_IS_MM_MASK, ctxt->is_mm); - - sw_ctxt[num_words_count++] = ctxt->ring_bs_addr & 0xffffffff; - sw_ctxt[num_words_count++] = (ctxt->ring_bs_addr >> 32) & 0xffffffff; - - return qdma_cpm4_indirect_reg_write(dev_hndl, sel, hw_qid, - sw_ctxt, num_words_count); -} - -/*****************************************************************************/ -/** - * qdma_cpm4_sw_context_read() - read sw context - * - * @dev_hndl: device handle - * @c2h: is c2h queue - * @hw_qid: hardware qid of the queue - * @ctxt: pointer to the output context data - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -static int qdma_cpm4_sw_context_read(void *dev_hndl, uint8_t c2h, - uint16_t hw_qid, - struct qdma_descq_sw_ctxt *ctxt) -{ - int rv = 0; - uint32_t sw_ctxt[QDMA_CPM4_SW_CONTEXT_NUM_WORDS] = {0}; - enum ind_ctxt_cmd_sel sel = c2h ? - QDMA_CTXT_SEL_SW_C2H : QDMA_CTXT_SEL_SW_H2C; - struct qdma_qid2vec qid2vec_ctxt = {0}; - - if (!dev_hndl || !ctxt) { - qdma_log_error("%s: dev_hndl=%p sw_ctxt=%p, err:%d\n", - __func__, dev_hndl, ctxt, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - rv = qdma_cpm4_indirect_reg_read(dev_hndl, sel, hw_qid, - QDMA_CPM4_SW_CONTEXT_NUM_WORDS, sw_ctxt); - if (rv < 0) - return rv; - - ctxt->pidx = FIELD_GET(SW_IND_CTXT_DATA_W0_PIDX_MASK, sw_ctxt[0]); - ctxt->irq_arm = - (uint8_t)(FIELD_GET(SW_IND_CTXT_DATA_W0_IRQ_ARM_MASK, - sw_ctxt[0])); - - ctxt->qen = FIELD_GET(SW_IND_CTXT_DATA_W1_QEN_MASK, sw_ctxt[1]); - ctxt->frcd_en = FIELD_GET(SW_IND_CTXT_DATA_W1_FCRD_EN_MASK, - sw_ctxt[1]); - ctxt->wbi_chk = FIELD_GET(SW_IND_CTXT_DATA_W1_WBI_CHK_MASK, - sw_ctxt[1]); - ctxt->wbi_intvl_en = - FIELD_GET(SW_IND_CTXT_DATA_W1_WBI_INTVL_EN_MASK, - sw_ctxt[1]); - ctxt->fnc_id = - (uint8_t)(FIELD_GET(SW_IND_CTXT_DATA_W1_FNC_ID_MASK, - sw_ctxt[1])); - ctxt->rngsz_idx = - (uint8_t)(FIELD_GET(SW_IND_CTXT_DATA_W1_RNG_SZ_MASK, - sw_ctxt[1])); - ctxt->desc_sz = - (uint8_t)(FIELD_GET(SW_IND_CTXT_DATA_W1_DSC_SZ_MASK, - sw_ctxt[1])); - ctxt->bypass = - (uint8_t)(FIELD_GET(SW_IND_CTXT_DATA_W1_BYPASS_MASK, - sw_ctxt[1])); - ctxt->mm_chn = - (uint8_t)(FIELD_GET(SW_IND_CTXT_DATA_W1_MM_CHN_MASK, - sw_ctxt[1])); - ctxt->wbk_en = - (uint8_t)(FIELD_GET(SW_IND_CTXT_DATA_W1_WBK_EN_MASK, - sw_ctxt[1])); - ctxt->irq_en = - (uint8_t)(FIELD_GET(SW_IND_CTXT_DATA_W1_IRQ_EN_MASK, - sw_ctxt[1])); - ctxt->port_id = - (uint8_t)(FIELD_GET(SW_IND_CTXT_DATA_W1_PORT_ID_MASK, - sw_ctxt[1])); - ctxt->irq_no_last = - (uint8_t)(FIELD_GET(SW_IND_CTXT_DATA_W1_IRQ_NO_LAST_MASK, - sw_ctxt[1])); - ctxt->err = - (uint8_t)(FIELD_GET(SW_IND_CTXT_DATA_W1_ERR_MASK, sw_ctxt[1])); - ctxt->err_wb_sent = - (uint8_t)(FIELD_GET(SW_IND_CTXT_DATA_W1_ERR_WB_SENT_MASK, - sw_ctxt[1])); - ctxt->irq_req = - (uint8_t)(FIELD_GET(SW_IND_CTXT_DATA_W1_IRQ_REQ_MASK, - sw_ctxt[1])); - ctxt->mrkr_dis = - (uint8_t)(FIELD_GET(SW_IND_CTXT_DATA_W1_MRKR_DIS_MASK, - sw_ctxt[1])); - ctxt->is_mm = - (uint8_t)(FIELD_GET(SW_IND_CTXT_DATA_W1_IS_MM_MASK, - sw_ctxt[1])); - - ctxt->ring_bs_addr = ((uint64_t)sw_ctxt[3] << 32) | (sw_ctxt[2]); - - /** Read the QID2VEC Context Data */ - rv = qdma_cpm4_qid2vec_read(dev_hndl, c2h, hw_qid, &qid2vec_ctxt); - if (rv < 0) - return rv; - - if (c2h) { - ctxt->vec = qid2vec_ctxt.c2h_vector; - ctxt->intr_aggr = qid2vec_ctxt.c2h_en_coal; - } else { - ctxt->vec = qid2vec_ctxt.h2c_vector; - ctxt->intr_aggr = qid2vec_ctxt.h2c_en_coal; - } - - - return QDMA_SUCCESS; -} - -/*****************************************************************************/ -/** - * qdma_cpm4_sw_context_clear() - clear sw context - * - * @dev_hndl: device handle - * @c2h: is c2h queue - * @hw_qid: hardware qid of the queue - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -static int qdma_cpm4_sw_context_clear(void *dev_hndl, uint8_t c2h, - uint16_t hw_qid) -{ - enum ind_ctxt_cmd_sel sel = c2h ? - QDMA_CTXT_SEL_SW_C2H : QDMA_CTXT_SEL_SW_H2C; - - if (!dev_hndl) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - return qdma_cpm4_indirect_reg_clear(dev_hndl, sel, hw_qid); -} - -/*****************************************************************************/ -/** - * qdma_cpm4_sw_context_invalidate() - invalidate sw context - * - * @dev_hndl: device handle - * @c2h: is c2h queue - * @hw_qid: hardware qid of the queue - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -static int qdma_cpm4_sw_context_invalidate(void *dev_hndl, uint8_t c2h, - uint16_t hw_qid) -{ - enum ind_ctxt_cmd_sel sel = c2h ? - QDMA_CTXT_SEL_SW_C2H : QDMA_CTXT_SEL_SW_H2C; - - if (!dev_hndl) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - return qdma_cpm4_indirect_reg_invalidate(dev_hndl, sel, hw_qid); -} - -/*****************************************************************************/ -/** - * qdma_cpm4_sw_ctx_conf() - configure SW context - * - * @dev_hndl: device handle - * @c2h: is c2h queue - * @hw_qid: hardware qid of the queue - * @ctxt: pointer to the context data - * @access_type HW access type (qdma_hw_access_type enum) value - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -int qdma_cpm4_sw_ctx_conf(void *dev_hndl, uint8_t c2h, uint16_t hw_qid, - struct qdma_descq_sw_ctxt *ctxt, - enum qdma_hw_access_type access_type) -{ - int ret_val = 0; - - switch (access_type) { - case QDMA_HW_ACCESS_READ: - ret_val = qdma_cpm4_sw_context_read(dev_hndl, c2h, hw_qid, - ctxt); - break; - case QDMA_HW_ACCESS_WRITE: - ret_val = qdma_cpm4_sw_context_write(dev_hndl, c2h, hw_qid, - ctxt); - break; - case QDMA_HW_ACCESS_CLEAR: - ret_val = qdma_cpm4_sw_context_clear(dev_hndl, c2h, hw_qid); - break; - case QDMA_HW_ACCESS_INVALIDATE: - ret_val = qdma_cpm4_sw_context_invalidate(dev_hndl, - c2h, hw_qid); - break; - default: - qdma_log_error("%s: access_type=%d is invalid, err:%d\n", - __func__, access_type, - -QDMA_ERR_INV_PARAM); - ret_val = -QDMA_ERR_INV_PARAM; - break; - } - return ret_val; -} - -/*****************************************************************************/ -/** - * qdma_cpm4_pfetch_context_write() - create prefetch context and program it - * - * @dev_hndl: device handle - * @hw_qid: hardware qid of the queue - * @ctxt: pointer to the prefetch context data strucutre - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -static int qdma_cpm4_pfetch_context_write(void *dev_hndl, uint16_t hw_qid, - const struct qdma_descq_prefetch_ctxt *ctxt) -{ - uint32_t pfetch_ctxt[QDMA_CPM4_PFETCH_CONTEXT_NUM_WORDS] = {0}; - enum ind_ctxt_cmd_sel sel = QDMA_CTXT_SEL_PFTCH; - uint32_t sw_crdt_l, sw_crdt_h; - uint16_t num_words_count = 0; - - if (!dev_hndl || !ctxt) { - qdma_log_error("%s: dev_hndl=%p pfetch_ctxt=%p, err:%d\n", - __func__, dev_hndl, ctxt, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - sw_crdt_l = - FIELD_GET(QDMA_PFTCH_CTXT_SW_CRDT_GET_L_MASK, ctxt->sw_crdt); - sw_crdt_h = - FIELD_GET(QDMA_PFTCH_CTXT_SW_CRDT_GET_H_MASK, ctxt->sw_crdt); - - pfetch_ctxt[num_words_count++] = - FIELD_SET(PREFETCH_CTXT_DATA_W0_BYPASS_MASK, ctxt->bypass) | - FIELD_SET(PREFETCH_CTXT_DATA_W0_BUF_SIZE_IDX_MASK, - ctxt->bufsz_idx) | - FIELD_SET(PREFETCH_CTXT_DATA_W0_PORT_ID_MASK, ctxt->port_id) | - FIELD_SET(PREFETCH_CTXT_DATA_W0_ERR_MASK, ctxt->err) | - FIELD_SET(PREFETCH_CTXT_DATA_W0_PFCH_EN_MASK, ctxt->pfch_en) | - FIELD_SET(PREFETCH_CTXT_DATA_W0_PFCH_MASK, ctxt->pfch) | - FIELD_SET(PREFETCH_CTXT_DATA_W0_SW_CRDT_L_MASK, sw_crdt_l); - - pfetch_ctxt[num_words_count++] = - FIELD_SET(PREFETCH_CTXT_DATA_W1_SW_CRDT_H_MASK, sw_crdt_h) | - FIELD_SET(PREFETCH_CTXT_DATA_W1_VALID_MASK, ctxt->valid); - - return qdma_cpm4_indirect_reg_write(dev_hndl, sel, hw_qid, - pfetch_ctxt, num_words_count); -} - -/*****************************************************************************/ -/** - * qdma_cpm4_pfetch_context_read() - read prefetch context - * - * @dev_hndl: device handle - * @hw_qid: hardware qid of the queue - * @ctxt: pointer to the output context data - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -static int qdma_cpm4_pfetch_context_read(void *dev_hndl, uint16_t hw_qid, - struct qdma_descq_prefetch_ctxt *ctxt) -{ - int rv = 0; - uint32_t pfetch_ctxt[QDMA_CPM4_PFETCH_CONTEXT_NUM_WORDS] = {0}; - enum ind_ctxt_cmd_sel sel = QDMA_CTXT_SEL_PFTCH; - uint32_t sw_crdt_l, sw_crdt_h; - - if (!dev_hndl || !ctxt) { - qdma_log_error("%s: dev_hndl=%p pfetch_ctxt=%p, err:%d\n", - __func__, dev_hndl, ctxt, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - rv = qdma_cpm4_indirect_reg_read(dev_hndl, sel, hw_qid, - QDMA_CPM4_PFETCH_CONTEXT_NUM_WORDS, pfetch_ctxt); - if (rv < 0) - return rv; - - ctxt->bypass = - (uint8_t)(FIELD_GET(PREFETCH_CTXT_DATA_W0_BYPASS_MASK, - pfetch_ctxt[0])); - ctxt->bufsz_idx = - (uint8_t)(FIELD_GET(PREFETCH_CTXT_DATA_W0_BUF_SIZE_IDX_MASK, - pfetch_ctxt[0])); - ctxt->port_id = - (uint8_t)(FIELD_GET(PREFETCH_CTXT_DATA_W0_PORT_ID_MASK, - pfetch_ctxt[0])); - ctxt->err = - (uint8_t)(FIELD_GET(PREFETCH_CTXT_DATA_W0_ERR_MASK, - pfetch_ctxt[0])); - ctxt->pfch_en = - (uint8_t)(FIELD_GET(PREFETCH_CTXT_DATA_W0_PFCH_EN_MASK, - pfetch_ctxt[0])); - ctxt->pfch = - (uint8_t)(FIELD_GET(PREFETCH_CTXT_DATA_W0_PFCH_MASK, - pfetch_ctxt[0])); - sw_crdt_l = - (uint32_t)FIELD_GET(PREFETCH_CTXT_DATA_W0_SW_CRDT_L_MASK, - pfetch_ctxt[0]); - - sw_crdt_h = - (uint32_t)FIELD_GET(PREFETCH_CTXT_DATA_W1_SW_CRDT_H_MASK, - pfetch_ctxt[1]); - ctxt->valid = - (uint8_t)(FIELD_GET(PREFETCH_CTXT_DATA_W1_VALID_MASK, - pfetch_ctxt[1])); - - ctxt->sw_crdt = - (uint16_t)(FIELD_SET(QDMA_PFTCH_CTXT_SW_CRDT_GET_L_MASK, - sw_crdt_l) | - FIELD_SET(QDMA_PFTCH_CTXT_SW_CRDT_GET_H_MASK, sw_crdt_h)); - - return QDMA_SUCCESS; -} - -/*****************************************************************************/ -/** - * qdma_cpm4_pfetch_context_clear() - clear prefetch context - * - * @dev_hndl: device handle - * @hw_qid: hardware qid of the queue - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -static int qdma_cpm4_pfetch_context_clear(void *dev_hndl, uint16_t hw_qid) -{ - enum ind_ctxt_cmd_sel sel = QDMA_CTXT_SEL_PFTCH; - - if (!dev_hndl) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - return qdma_cpm4_indirect_reg_clear(dev_hndl, sel, hw_qid); -} - -/*****************************************************************************/ -/** - * qdma_cpm4_pfetch_context_invalidate() - invalidate prefetch context - * - * @dev_hndl: device handle - * @hw_qid: hardware qid of the queue - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -static int qdma_cpm4_pfetch_context_invalidate(void *dev_hndl, - uint16_t hw_qid) -{ - enum ind_ctxt_cmd_sel sel = QDMA_CTXT_SEL_PFTCH; - - if (!dev_hndl) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - return qdma_cpm4_indirect_reg_invalidate(dev_hndl, sel, hw_qid); -} - -/*****************************************************************************/ -/** - * qdma_cpm4_pfetch_ctx_conf() - configure prefetch context - * - * @dev_hndl: device handle - * @hw_qid: hardware qid of the queue - * @ctxt: pointer to context data - * @access_type HW access type (qdma_hw_access_type enum) value - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -int qdma_cpm4_pfetch_ctx_conf(void *dev_hndl, uint16_t hw_qid, - struct qdma_descq_prefetch_ctxt *ctxt, - enum qdma_hw_access_type access_type) -{ - int ret_val = 0; - - switch (access_type) { - case QDMA_HW_ACCESS_READ: - ret_val = qdma_cpm4_pfetch_context_read(dev_hndl, - hw_qid, ctxt); - break; - case QDMA_HW_ACCESS_WRITE: - ret_val = qdma_cpm4_pfetch_context_write(dev_hndl, - hw_qid, ctxt); - break; - case QDMA_HW_ACCESS_CLEAR: - ret_val = qdma_cpm4_pfetch_context_clear(dev_hndl, hw_qid); - break; - case QDMA_HW_ACCESS_INVALIDATE: - ret_val = qdma_cpm4_pfetch_context_invalidate(dev_hndl, - hw_qid); - break; - default: - qdma_log_error("%s: access_type=%d is invalid, err:%d\n", - __func__, access_type, - -QDMA_ERR_INV_PARAM); - ret_val = -QDMA_ERR_INV_PARAM; - break; - } - - return ret_val; -} - -/*****************************************************************************/ -/** - * qdma_cpm4_cmpt_context_write() - create completion context and program it - * - * @dev_hndl: device handle - * @hw_qid: hardware qid of the queue - * @ctxt: pointer to the cmpt context data strucutre - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -static int qdma_cpm4_cmpt_context_write(void *dev_hndl, uint16_t hw_qid, - const struct qdma_descq_cmpt_ctxt *ctxt) -{ - uint32_t cmpt_ctxt[QDMA_CPM4_CMPT_CONTEXT_NUM_WORDS] = {0}; - uint16_t num_words_count = 0; - uint32_t baddr_l, baddr_h, baddr_m, pidx_l, pidx_h; - enum ind_ctxt_cmd_sel sel = QDMA_CTXT_SEL_CMPT; - - /* Input args check */ - if (!dev_hndl || !ctxt) { - qdma_log_error("%s: dev_hndl=%p cmpt_ctxt=%p, err:%d\n", - __func__, dev_hndl, ctxt, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - if ((ctxt->desc_sz > QDMA_DESC_SIZE_32B) || - (ctxt->ringsz_idx >= QDMA_NUM_RING_SIZES) || - (ctxt->counter_idx >= QDMA_NUM_C2H_COUNTERS) || - (ctxt->timer_idx >= QDMA_NUM_C2H_TIMERS) || - (ctxt->trig_mode > QDMA_CMPT_UPDATE_TRIG_MODE_TMR_CNTR)) { - qdma_log_error - ("%s Inv dsz(%d)/ridx(%d)/cntr(%d)/tmr(%d)/tm(%d), err:%d\n", - __func__, - ctxt->desc_sz, - ctxt->ringsz_idx, - ctxt->counter_idx, - ctxt->timer_idx, - ctxt->trig_mode, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - baddr_l = - (uint32_t)FIELD_GET(QDMA_CPM4_COMPL_CTXT_BADDR_GET_L_MASK, - ctxt->bs_addr); - baddr_m = - (uint32_t)FIELD_GET(QDMA_CPM4_COMPL_CTXT_BADDR_GET_M_MASK, - ctxt->bs_addr); - baddr_h = - (uint32_t)FIELD_GET(QDMA_CPM4_COMPL_CTXT_BADDR_GET_H_MASK, - ctxt->bs_addr); - - pidx_l = FIELD_GET(QDMA_CPM4_COMPL_CTXT_PIDX_GET_L_MASK, - ctxt->pidx); - pidx_h = FIELD_GET(QDMA_CPM4_COMPL_CTXT_PIDX_GET_H_MASK, - ctxt->pidx); - - cmpt_ctxt[num_words_count++] = - FIELD_SET(CMPL_CTXT_DATA_W0_EN_STAT_DESC_MASK, - ctxt->en_stat_desc) | - FIELD_SET(CMPL_CTXT_DATA_W0_EN_INT_MASK, ctxt->en_int) | - FIELD_SET(CMPL_CTXT_DATA_W0_TRIG_MODE_MASK, ctxt->trig_mode) | - FIELD_SET(CMPL_CTXT_DATA_W0_FNC_ID_MASK, ctxt->fnc_id) | - FIELD_SET(CMPL_CTXT_DATA_W0_CNTER_IDX_MASK, - ctxt->counter_idx) | - FIELD_SET(CMPL_CTXT_DATA_W0_TIMER_IDX_MASK, - ctxt->timer_idx) | - FIELD_SET(CMPL_CTXT_DATA_W0_INT_ST_MASK, - ctxt->in_st) | - FIELD_SET(CMPL_CTXT_DATA_W0_COLOR_MASK, - ctxt->color) | - FIELD_SET(CMPL_CTXT_DATA_W0_QSIZE_IDX_MASK, - ctxt->ringsz_idx) | - FIELD_SET(CMPL_CTXT_DATA_W0_BADDR_64_L_MASK, - baddr_l); - - cmpt_ctxt[num_words_count++] = - FIELD_SET(CMPL_CTXT_DATA_W1_BADDR_64_M_MASK, - baddr_m); - - cmpt_ctxt[num_words_count++] = - FIELD_SET(CMPL_CTXT_DATA_W2_BADDR_64_H_MASK, - baddr_h) | - FIELD_SET(CMPL_CTXT_DATA_W2_DESC_SIZE_MASK, - ctxt->desc_sz) | - FIELD_SET(CMPL_CTXT_DATA_W2_PIDX_L_MASK, - pidx_l); - - cmpt_ctxt[num_words_count++] = - FIELD_SET(CMPL_CTXT_DATA_W3_PIDX_H_MASK, - pidx_h) | - FIELD_SET(CMPL_CTXT_DATA_W3_CIDX_MASK, ctxt->cidx) | - FIELD_SET(CMPL_CTXT_DATA_W3_VALID_MASK, ctxt->valid) | - FIELD_SET(CMPL_CTXT_DATA_W3_ERR_MASK, ctxt->err) | - FIELD_SET(CMPL_CTXT_DATA_W3_USER_TRIG_PEND_MASK, - ctxt->user_trig_pend) | - FIELD_SET(CMPL_CTXT_DATA_W3_TIMER_RUNNING_MASK, - ctxt->timer_running) | - FIELD_SET(CMPL_CTXT_DATA_W3_FULL_UPD_MASK, - ctxt->full_upd); - - return qdma_cpm4_indirect_reg_write(dev_hndl, sel, hw_qid, - cmpt_ctxt, num_words_count); - -} - -/*****************************************************************************/ -/** - * qdma_cpm4_cmpt_context_read() - read completion context - * - * @dev_hndl: device handle - * @hw_qid: hardware qid of the queue - * @ctxt: pointer to the context data - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -static int qdma_cpm4_cmpt_context_read(void *dev_hndl, uint16_t hw_qid, - struct qdma_descq_cmpt_ctxt *ctxt) -{ - int rv = 0; - uint32_t cmpt_ctxt[QDMA_CPM4_CMPT_CONTEXT_NUM_WORDS] = {0}; - enum ind_ctxt_cmd_sel sel = QDMA_CTXT_SEL_CMPT; - uint32_t baddr_l, baddr_h, baddr_m, - pidx_l, pidx_h; - - if (!dev_hndl || !ctxt) { - qdma_log_error("%s: dev_hndl=%p cmpt_ctxt=%p, err:%d\n", - __func__, dev_hndl, ctxt, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - rv = qdma_cpm4_indirect_reg_read(dev_hndl, sel, hw_qid, - QDMA_CPM4_CMPT_CONTEXT_NUM_WORDS, cmpt_ctxt); - if (rv < 0) - return rv; - - ctxt->en_stat_desc = - FIELD_GET(CMPL_CTXT_DATA_W0_EN_STAT_DESC_MASK, cmpt_ctxt[0]); - ctxt->en_int = FIELD_GET(CMPL_CTXT_DATA_W0_EN_INT_MASK, - cmpt_ctxt[0]); - ctxt->trig_mode = - FIELD_GET(CMPL_CTXT_DATA_W0_TRIG_MODE_MASK, cmpt_ctxt[0]); - ctxt->fnc_id = - (uint8_t)(FIELD_GET(CMPL_CTXT_DATA_W0_FNC_ID_MASK, - cmpt_ctxt[0])); - ctxt->counter_idx = - (uint8_t)(FIELD_GET( - CMPL_CTXT_DATA_W0_CNTER_IDX_MASK, - cmpt_ctxt[0])); - ctxt->timer_idx = - (uint8_t)(FIELD_GET(CMPL_CTXT_DATA_W0_TIMER_IDX_MASK, - cmpt_ctxt[0])); - ctxt->in_st = - (uint8_t)(FIELD_GET(CMPL_CTXT_DATA_W0_INT_ST_MASK, - cmpt_ctxt[0])); - ctxt->color = - (uint8_t)(FIELD_GET(CMPL_CTXT_DATA_W0_COLOR_MASK, - cmpt_ctxt[0])); - ctxt->ringsz_idx = - (uint8_t)(FIELD_GET(CMPL_CTXT_DATA_W0_QSIZE_IDX_MASK, - cmpt_ctxt[0])); - - baddr_l = - FIELD_GET(CMPL_CTXT_DATA_W0_BADDR_64_L_MASK, - cmpt_ctxt[0]); - baddr_m = - FIELD_GET(CMPL_CTXT_DATA_W1_BADDR_64_M_MASK, - cmpt_ctxt[1]); - baddr_h = - FIELD_GET(CMPL_CTXT_DATA_W2_BADDR_64_H_MASK, - cmpt_ctxt[2]); - - ctxt->desc_sz = - (uint8_t)(FIELD_GET(CMPL_CTXT_DATA_W2_DESC_SIZE_MASK, - cmpt_ctxt[2])); - pidx_l = FIELD_GET(CMPL_CTXT_DATA_W2_PIDX_L_MASK, - cmpt_ctxt[2]); - - pidx_h = FIELD_GET(CMPL_CTXT_DATA_W3_PIDX_H_MASK, - cmpt_ctxt[3]); - ctxt->cidx = - (uint16_t)(FIELD_GET(CMPL_CTXT_DATA_W3_CIDX_MASK, - cmpt_ctxt[3])); - ctxt->valid = - (uint8_t)(FIELD_GET(CMPL_CTXT_DATA_W3_VALID_MASK, - cmpt_ctxt[3])); - ctxt->err = - (uint8_t)(FIELD_GET(CMPL_CTXT_DATA_W3_ERR_MASK, - cmpt_ctxt[3])); - ctxt->user_trig_pend = - (uint8_t)(FIELD_GET( - CMPL_CTXT_DATA_W3_USER_TRIG_PEND_MASK, cmpt_ctxt[3])); - - ctxt->timer_running = - (uint8_t)(FIELD_GET(CMPL_CTXT_DATA_W3_TIMER_RUNNING_MASK, - cmpt_ctxt[3])); - ctxt->full_upd = - (uint8_t)(FIELD_GET(CMPL_CTXT_DATA_W3_FULL_UPD_MASK, - cmpt_ctxt[3])); - - ctxt->bs_addr = - FIELD_SET(QDMA_CPM4_COMPL_CTXT_BADDR_GET_L_MASK, - (uint64_t)baddr_l) | - FIELD_SET(QDMA_CPM4_COMPL_CTXT_BADDR_GET_M_MASK, - (uint64_t)baddr_m) | - FIELD_SET(QDMA_CPM4_COMPL_CTXT_BADDR_GET_H_MASK, - (uint64_t)baddr_h); - - ctxt->pidx = - (uint16_t)(FIELD_SET(QDMA_CPM4_COMPL_CTXT_PIDX_GET_L_MASK, - pidx_l) | - FIELD_SET(QDMA_CPM4_COMPL_CTXT_PIDX_GET_H_MASK, - pidx_h)); - - return QDMA_SUCCESS; -} - -/*****************************************************************************/ -/** - * qdma_cpm4_cmpt_context_clear() - clear completion context - * - * @dev_hndl: device handle - * @hw_qid: hardware qid of the queue - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -static int qdma_cpm4_cmpt_context_clear(void *dev_hndl, uint16_t hw_qid) -{ - enum ind_ctxt_cmd_sel sel = QDMA_CTXT_SEL_CMPT; - - if (!dev_hndl) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - return qdma_cpm4_indirect_reg_clear(dev_hndl, sel, hw_qid); -} - -/*****************************************************************************/ -/** - * qdma_cpm4_cmpt_context_invalidate() - invalidate completion context - * - * @dev_hndl: device handle - * @hw_qid: hardware qid of the queue - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -static int qdma_cpm4_cmpt_context_invalidate(void *dev_hndl, - uint16_t hw_qid) -{ - enum ind_ctxt_cmd_sel sel = QDMA_CTXT_SEL_CMPT; - - if (!dev_hndl) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - return qdma_cpm4_indirect_reg_invalidate(dev_hndl, sel, hw_qid); -} - -/*****************************************************************************/ -/** - * qdma_cpm4_cmpt_ctx_conf() - configure completion context - * - * @dev_hndl: device handle - * @hw_qid: hardware qid of the queue - * @ctxt: pointer to context data - * @access_type HW access type (qdma_hw_access_type enum) value - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -int qdma_cpm4_cmpt_ctx_conf(void *dev_hndl, uint16_t hw_qid, - struct qdma_descq_cmpt_ctxt *ctxt, - enum qdma_hw_access_type access_type) -{ - int ret_val = 0; - - if (!dev_hndl) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - switch (access_type) { - case QDMA_HW_ACCESS_READ: - ret_val = qdma_cpm4_cmpt_context_read(dev_hndl, - hw_qid, ctxt); - break; - case QDMA_HW_ACCESS_WRITE: - ret_val = qdma_cpm4_cmpt_context_write(dev_hndl, - hw_qid, ctxt); - break; - case QDMA_HW_ACCESS_CLEAR: - ret_val = qdma_cpm4_cmpt_context_clear(dev_hndl, hw_qid); - break; - case QDMA_HW_ACCESS_INVALIDATE: - ret_val = qdma_cpm4_cmpt_context_invalidate(dev_hndl, - hw_qid); - break; - default: - qdma_log_error("%s: access_type=%d is invalid, err:%d\n", - __func__, access_type, - -QDMA_ERR_INV_PARAM); - ret_val = -QDMA_ERR_INV_PARAM; - break; - } - - return ret_val; -} - -/*****************************************************************************/ -/** - * qdma_cpm4_hw_context_read() - read hardware context - * - * @dev_hndl: device handle - * @c2h: is c2h queue - * @hw_qid: hardware qid of the queue - * @ctxt: pointer to the output context data - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -static int qdma_cpm4_hw_context_read(void *dev_hndl, uint8_t c2h, - uint16_t hw_qid, struct qdma_descq_hw_ctxt *ctxt) -{ - int rv = 0; - uint32_t hw_ctxt[QDMA_CPM4_HW_CONTEXT_NUM_WORDS] = {0}; - enum ind_ctxt_cmd_sel sel = c2h ? QDMA_CTXT_SEL_HW_C2H : - QDMA_CTXT_SEL_HW_H2C; - - if (!dev_hndl || !ctxt) { - qdma_log_error("%s: dev_hndl=%p hw_ctxt=%p, err:%d\n", - __func__, dev_hndl, ctxt, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - rv = qdma_cpm4_indirect_reg_read(dev_hndl, sel, hw_qid, - QDMA_CPM4_HW_CONTEXT_NUM_WORDS, hw_ctxt); - if (rv < 0) - return rv; - - ctxt->cidx = FIELD_GET(HW_IND_CTXT_DATA_W0_CIDX_MASK, hw_ctxt[0]); - ctxt->crd_use = - (uint16_t)(FIELD_GET(HW_IND_CTXT_DATA_W0_CRD_USE_MASK, - hw_ctxt[0])); - - ctxt->dsc_pend = - (uint8_t)(FIELD_GET(HW_IND_CTXT_DATA_W1_DSC_PND_MASK, - hw_ctxt[1])); - ctxt->idl_stp_b = - (uint8_t)(FIELD_GET(HW_IND_CTXT_DATA_W1_IDL_STP_B_MASK, - hw_ctxt[1])); - ctxt->fetch_pnd = - (uint8_t)(FIELD_GET(HW_IND_CTXT_DATA_W1_FETCH_PND_MASK, - hw_ctxt[1])); - - return QDMA_SUCCESS; -} - -/*****************************************************************************/ -/** - * qdma_cpm4_hw_context_clear() - clear hardware context - * - * @dev_hndl: device handle - * @c2h: is c2h queue - * @hw_qid: hardware qid of the queue - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -static int qdma_cpm4_hw_context_clear(void *dev_hndl, uint8_t c2h, - uint16_t hw_qid) -{ - enum ind_ctxt_cmd_sel sel = c2h ? QDMA_CTXT_SEL_HW_C2H : - QDMA_CTXT_SEL_HW_H2C; - - if (!dev_hndl) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - return qdma_cpm4_indirect_reg_clear(dev_hndl, sel, hw_qid); -} - -/*****************************************************************************/ -/** - * qdma_cpm4_hw_context_invalidate() - invalidate hardware context - * - * @dev_hndl: device handle - * @c2h: is c2h queue - * @hw_qid: hardware qid of the queue - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -static int qdma_cpm4_hw_context_invalidate(void *dev_hndl, uint8_t c2h, - uint16_t hw_qid) -{ - enum ind_ctxt_cmd_sel sel = c2h ? QDMA_CTXT_SEL_HW_C2H : - QDMA_CTXT_SEL_HW_H2C; - - if (!dev_hndl) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - return qdma_cpm4_indirect_reg_invalidate(dev_hndl, sel, hw_qid); -} - -/*****************************************************************************/ -/** - * qdma_cpm4_hw_ctx_conf() - configure HW context - * - * @dev_hndl: device handle - * @c2h: is c2h queue - * @hw_qid: hardware qid of the queue - * @ctxt: pointer to context data - * @access_type HW access type (qdma_hw_access_type enum) value - * QDMA_HW_ACCESS_WRITE unsupported - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -int qdma_cpm4_hw_ctx_conf(void *dev_hndl, uint8_t c2h, uint16_t hw_qid, - struct qdma_descq_hw_ctxt *ctxt, - enum qdma_hw_access_type access_type) -{ - int ret_val = 0; - - switch (access_type) { - case QDMA_HW_ACCESS_READ: - ret_val = qdma_cpm4_hw_context_read(dev_hndl, c2h, hw_qid, - ctxt); - break; - case QDMA_HW_ACCESS_CLEAR: - ret_val = qdma_cpm4_hw_context_clear(dev_hndl, c2h, hw_qid); - break; - case QDMA_HW_ACCESS_INVALIDATE: - ret_val = qdma_cpm4_hw_context_invalidate(dev_hndl, c2h, - hw_qid); - break; - case QDMA_HW_ACCESS_WRITE: - default: - qdma_log_error("%s: access_type=%d is invalid, err:%d\n", - __func__, access_type, - -QDMA_ERR_INV_PARAM); - ret_val = -QDMA_ERR_INV_PARAM; - break; - } - - - return ret_val; -} - -/*****************************************************************************/ -/** - * qdma_cpm4_indirect_intr_context_write() - create indirect - * interrupt context and program it - * - * @dev_hndl: device handle - * @ring_index: indirect interrupt ring index - * @ctxt: pointer to the interrupt context data strucutre - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -static int qdma_cpm4_indirect_intr_context_write(void *dev_hndl, - uint16_t ring_index, const struct qdma_indirect_intr_ctxt *ctxt) -{ - uint32_t intr_ctxt[QDMA_CPM4_IND_INTR_CONTEXT_NUM_WORDS] = {0}; - enum ind_ctxt_cmd_sel sel = QDMA_CTXT_SEL_INT_COAL; - uint16_t num_words_count = 0; - uint32_t baddr_l, baddr_h; - - if (!dev_hndl || !ctxt) { - qdma_log_error("%s: dev_hndl=%p intr_ctxt=%p, err:%d\n", - __func__, dev_hndl, ctxt, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - if (ctxt->page_size > QDMA_INDIRECT_INTR_RING_SIZE_32KB) { - qdma_log_error("%s: ctxt->page_size=%u is too big, err:%d\n", - __func__, ctxt->page_size, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - baddr_l = - (uint32_t)FIELD_GET(QDMA_CPM4_INTR_CTXT_BADDR_GET_L_MASK, - ctxt->baddr_4k); - baddr_h = - (uint32_t)FIELD_GET(QDMA_CPM4_INTR_CTXT_BADDR_GET_H_MASK, - ctxt->baddr_4k); - - intr_ctxt[num_words_count++] = - FIELD_SET(INTR_CTXT_DATA_W0_VALID_MASK, ctxt->valid) | - FIELD_SET(INTR_CTXT_DATA_W0_VEC_MASK, ctxt->vec) | - FIELD_SET(INTR_CTXT_DATA_W0_INT_ST_MASK, - ctxt->int_st) | - FIELD_SET(INTR_CTXT_DATA_W0_COLOR_MASK, ctxt->color) | - FIELD_SET(INTR_CTXT_DATA_W0_BADDR_4K_L_MASK, baddr_l); - - intr_ctxt[num_words_count++] = - FIELD_SET(INTR_CTXT_DATA_W1_BADDR_4K_H_MASK, baddr_h) | - FIELD_SET(INTR_CTXT_DATA_W1_PAGE_SIZE_MASK, - ctxt->page_size); - - intr_ctxt[num_words_count++] = - FIELD_SET(INTR_CTXT_DATA_W2_PIDX_MASK, ctxt->pidx); - - return qdma_cpm4_indirect_reg_write(dev_hndl, sel, ring_index, - intr_ctxt, num_words_count); -} - -/*****************************************************************************/ -/** - * qdma_indirect_intr_context_read() - read indirect interrupt context - * - * @dev_hndl: device handle - * @ring_index: indirect interrupt ring index - * @ctxt: pointer to the output context data - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -static int qdma_cpm4_indirect_intr_context_read(void *dev_hndl, - uint16_t ring_index, struct qdma_indirect_intr_ctxt *ctxt) -{ - int rv = 0; - uint32_t intr_ctxt[QDMA_CPM4_IND_INTR_CONTEXT_NUM_WORDS] = {0}; - enum ind_ctxt_cmd_sel sel = QDMA_CTXT_SEL_INT_COAL; - uint64_t baddr_l, baddr_h; - - if (!dev_hndl || !ctxt) { - qdma_log_error("%s: dev_hndl=%p intr_ctxt=%p, err:%d\n", - __func__, dev_hndl, ctxt, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - rv = qdma_cpm4_indirect_reg_read(dev_hndl, sel, ring_index, - QDMA_CPM4_IND_INTR_CONTEXT_NUM_WORDS, intr_ctxt); - if (rv < 0) - return rv; - - ctxt->valid = FIELD_GET(INTR_CTXT_DATA_W0_VALID_MASK, intr_ctxt[0]); - ctxt->vec = FIELD_GET(INTR_CTXT_DATA_W0_VEC_MASK, - intr_ctxt[0]); - ctxt->int_st = FIELD_GET(INTR_CTXT_DATA_W0_INT_ST_MASK, - intr_ctxt[0]); - ctxt->color = - (uint8_t)(FIELD_GET(INTR_CTXT_DATA_W0_COLOR_MASK, - intr_ctxt[0])); - baddr_l = FIELD_GET(INTR_CTXT_DATA_W0_BADDR_4K_L_MASK, - intr_ctxt[0]); - - baddr_h = FIELD_GET(INTR_CTXT_DATA_W1_BADDR_4K_H_MASK, - intr_ctxt[1]); - ctxt->page_size = - (uint8_t)(FIELD_GET(INTR_CTXT_DATA_W1_PAGE_SIZE_MASK, - intr_ctxt[1])); - ctxt->pidx = FIELD_GET(INTR_CTXT_DATA_W2_PIDX_MASK, - intr_ctxt[2]); - - ctxt->baddr_4k = - FIELD_SET(QDMA_CPM4_INTR_CTXT_BADDR_GET_L_MASK, baddr_l) | - FIELD_SET(QDMA_CPM4_INTR_CTXT_BADDR_GET_H_MASK, baddr_h); - - return QDMA_SUCCESS; -} - -/*****************************************************************************/ -/** - * qdma_cpm4_indirect_intr_context_clear() - clear indirect - * interrupt context - * - * @dev_hndl: device handle - * @ring_index: indirect interrupt ring index - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -static int qdma_cpm4_indirect_intr_context_clear(void *dev_hndl, - uint16_t ring_index) -{ - enum ind_ctxt_cmd_sel sel = QDMA_CTXT_SEL_INT_COAL; - - if (!dev_hndl) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - return qdma_cpm4_indirect_reg_clear(dev_hndl, sel, ring_index); -} - -/*****************************************************************************/ -/** - * qdma_cpm4_indirect_intr_context_invalidate() - invalidate - * indirect interrupt context - * - * @dev_hndl: device handle - * @ring_index: indirect interrupt ring index - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -static int qdma_cpm4_indirect_intr_context_invalidate(void *dev_hndl, - uint16_t ring_index) -{ - enum ind_ctxt_cmd_sel sel = QDMA_CTXT_SEL_INT_COAL; - - if (!dev_hndl) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - return qdma_cpm4_indirect_reg_invalidate(dev_hndl, sel, ring_index); -} - -/*****************************************************************************/ -/** - * qdma_cpm4_indirect_intr_ctx_conf() - configure indirect interrupt context - * - * @dev_hndl: device handle - * @ring_index: indirect interrupt ring index - * @ctxt: pointer to context data - * @access_type HW access type (qdma_hw_access_type enum) value - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -int qdma_cpm4_indirect_intr_ctx_conf(void *dev_hndl, uint16_t ring_index, - struct qdma_indirect_intr_ctxt *ctxt, - enum qdma_hw_access_type access_type) -{ - int ret_val = 0; - - switch (access_type) { - case QDMA_HW_ACCESS_READ: - ret_val = qdma_cpm4_indirect_intr_context_read(dev_hndl, - ring_index, - ctxt); - break; - case QDMA_HW_ACCESS_WRITE: - ret_val = qdma_cpm4_indirect_intr_context_write(dev_hndl, - ring_index, - ctxt); - break; - case QDMA_HW_ACCESS_CLEAR: - ret_val = qdma_cpm4_indirect_intr_context_clear(dev_hndl, - ring_index); - break; - case QDMA_HW_ACCESS_INVALIDATE: - ret_val = qdma_cpm4_indirect_intr_context_invalidate( - dev_hndl, ring_index); - break; - default: - qdma_log_error("%s: access_type=%d is invalid, err:%d\n", - __func__, access_type, - -QDMA_ERR_INV_PARAM); - ret_val = -QDMA_ERR_INV_PARAM; - break; - } - - return ret_val; -} - -/*****************************************************************************/ -/** - * qdma_cpm4_set_default_global_csr() - function to set the global - * CSR register to default values. The value can be modified later by using - * the set/get csr functions - * - * @dev_hndl: device handle - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -int qdma_cpm4_set_default_global_csr(void *dev_hndl) -{ - /* Default values */ - uint32_t reg_val = 0; - uint32_t rng_sz[QDMA_NUM_RING_SIZES] = {2049, 65, 129, 193, 257, - 385, 513, 769, 1025, 1537, 3073, 4097, 6145, - 8193, 12289, 16385}; - uint32_t tmr_cnt[QDMA_NUM_C2H_TIMERS] = {1, 2, 4, 5, 8, 10, 15, 20, 25, - 30, 50, 75, 100, 125, 150, 200}; - uint32_t cnt_th[QDMA_NUM_C2H_COUNTERS] = {2, 4, 8, 16, 24, - 32, 48, 64, 80, 96, 112, 128, 144, - 160, 176, 192}; - uint32_t buf_sz[QDMA_NUM_C2H_BUFFER_SIZES] = {4096, 256, 512, 1024, - 2048, 3968, 4096, 4096, 4096, 4096, 4096, 4096, - 4096, 8192, 9018, 16384}; - struct qdma_dev_attributes dev_cap; - - if (!dev_hndl) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - qdma_cpm4_get_device_attributes(dev_hndl, &dev_cap); - - /* Configuring CSR registers */ - /* Global ring sizes */ - qdma_write_csr_values(dev_hndl, QDMA_CPM4_GLBL_RNG_SZ_1_ADDR, 0, - QDMA_NUM_RING_SIZES, rng_sz); - - if (dev_cap.st_en || dev_cap.mm_cmpt_en) { - /* Counter thresholds */ - qdma_write_csr_values(dev_hndl, - QDMA_CPM4_C2H_CNT_TH_1_ADDR, 0, - QDMA_NUM_C2H_COUNTERS, cnt_th); - - /* Timer Counters */ - qdma_write_csr_values(dev_hndl, - QDMA_CPM4_C2H_TIMER_CNT_1_ADDR, 0, - QDMA_NUM_C2H_TIMERS, tmr_cnt); - - - /* Writeback Interval */ - reg_val = - FIELD_SET(GLBL_DSC_CFG_MAXFETCH_MASK, - DEFAULT_MAX_DSC_FETCH) | - FIELD_SET(GLBL_DSC_CFG_WB_ACC_INT_MASK, - DEFAULT_WRB_INT); - qdma_reg_write(dev_hndl, - QDMA_CPM4_GLBL_DSC_CFG_ADDR, reg_val); - } - - if (dev_cap.st_en) { - /* Buffer Sizes */ - qdma_write_csr_values(dev_hndl, - QDMA_CPM4_C2H_BUF_SZ_0_ADDR, 0, - QDMA_NUM_C2H_BUFFER_SIZES, buf_sz); - - /* Prefetch Configuration */ - reg_val = - FIELD_SET(C2H_PFCH_CFG_FL_TH_MASK, - QDMA_CPM4_DEFAULT_PFCH_STOP_THRESH) | - FIELD_SET(C2H_PFCH_CFG_NUM_MASK, - DEFAULT_PFCH_NUM_ENTRIES_PER_Q) | - FIELD_SET(C2H_PFCH_CFG_QCNT_MASK, - DEFAULT_PFCH_MAX_Q_CNT) | - FIELD_SET(C2H_PFCH_CFG_EVT_QCNT_TH_MASK, - DEFAULT_C2H_INTR_TIMER_TICK); - qdma_reg_write(dev_hndl, - QDMA_CPM4_C2H_PFCH_CFG_ADDR, reg_val); - - /* C2H interrupt timer tick */ - qdma_reg_write(dev_hndl, QDMA_CPM4_C2H_INT_TIMER_TICK_ADDR, - DEFAULT_C2H_INTR_TIMER_TICK); - - /* C2h Completion Coalesce Configuration */ - reg_val = - FIELD_SET(C2H_WRB_COAL_CFG_TICK_CNT_MASK, - DEFAULT_CMPT_COAL_TIMER_CNT) | - FIELD_SET(C2H_WRB_COAL_CFG_TICK_VAL_MASK, - DEFAULT_CMPT_COAL_TIMER_TICK) | - FIELD_SET(C2H_WRB_COAL_CFG_MAX_BUF_SZ_MASK, - DEFAULT_CMPT_COAL_MAX_BUF_SZ); - qdma_reg_write(dev_hndl, - QDMA_CPM4_C2H_WRB_COAL_CFG_ADDR, reg_val); - -#if 0 - /* H2C throttle Configuration*/ - reg_val = - FIELD_SET(QDMA_H2C_DATA_THRESH_MASK, - DEFAULT_H2C_THROT_DATA_THRESH) | - FIELD_SET(QDMA_H2C_REQ_THROT_EN_DATA_MASK, - DEFAULT_THROT_EN_DATA); - qdma_reg_write(dev_hndl, QDMA_OFFSET_H2C_REQ_THROT, reg_val); -#endif - } - - return QDMA_SUCCESS; -} - -/*****************************************************************************/ -/** - * qdma_cpm4_queue_pidx_update() - function to update the desc PIDX - * - * @dev_hndl: device handle - * @is_vf: Whether PF or VF - * @qid: Queue id relative to the PF/VF calling this API - * @is_c2h: Queue direction. Set 1 for C2H and 0 for H2C - * @reg_info: data needed for the PIDX register update - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -int qdma_cpm4_queue_pidx_update(void *dev_hndl, uint8_t is_vf, uint16_t qid, - uint8_t is_c2h, const struct qdma_q_pidx_reg_info *reg_info) -{ - uint32_t reg_addr = 0; - uint32_t reg_val = 0; - - if (!dev_hndl) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - if (!reg_info) { - qdma_log_error("%s: reg_info is NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - if (!is_vf) { - reg_addr = (is_c2h) ? - QDMA_CPM4_OFFSET_DMAP_SEL_C2H_DSC_PIDX : - QDMA_CPM4_OFFSET_DMAP_SEL_H2C_DSC_PIDX; - } else { - reg_addr = (is_c2h) ? - QDMA_CPM4_OFFSET_VF_DMAP_SEL_C2H_DSC_PIDX : - QDMA_CPM4_OFFSET_VF_DMAP_SEL_H2C_DSC_PIDX; - } - - reg_addr += (qid * QDMA_PIDX_STEP); - - reg_val = FIELD_SET(QDMA_CPM4_DMA_SEL_DESC_PIDX_MASK, - reg_info->pidx) | - FIELD_SET(QDMA_CPM4_DMA_SEL_IRQ_EN_MASK, - reg_info->irq_en); - - qdma_reg_write(dev_hndl, reg_addr, reg_val); - - return QDMA_SUCCESS; -} - -/*****************************************************************************/ -/** - * qdma_cpm4_queue_cmpt_cidx_update() - function to update the CMPT - * CIDX update - * - * @dev_hndl: device handle - * @is_vf: Whether PF or VF - * @qid: Queue id relative to the PF/VF calling this API - * @reg_info: data needed for the CIDX register update - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -int qdma_cpm4_queue_cmpt_cidx_update(void *dev_hndl, uint8_t is_vf, - uint16_t qid, const struct qdma_q_cmpt_cidx_reg_info *reg_info) -{ - uint32_t reg_addr = (is_vf) ? - QDMA_CPM4_OFFSET_VF_DMAP_SEL_CMPT_CIDX : - QDMA_CPM4_OFFSET_DMAP_SEL_CMPT_CIDX; - uint32_t reg_val = 0; - - if (!dev_hndl) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - if (!reg_info) { - qdma_log_error("%s: reg_info is NULL, err:%d\n", - __func__, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - reg_addr += (qid * QDMA_CMPT_CIDX_STEP); - - reg_val = - FIELD_SET(QDMA_CPM4_DMAP_SEL_CMPT_WRB_CIDX_MASK, - reg_info->wrb_cidx) | - FIELD_SET(QDMA_CPM4_DMAP_SEL_CMPT_CNT_THRESH_MASK, - reg_info->counter_idx) | - FIELD_SET(QDMA_CPM4_DMAP_SEL_CMPT_TMR_CNT_MASK, - reg_info->timer_idx) | - FIELD_SET(QDMA_CPM4_DMAP_SEL_CMPT_TRG_MODE_MASK, - reg_info->trig_mode) | - FIELD_SET(QDMA_CPM4_DMAP_SEL_CMPT_STS_DESC_EN_MASK, - reg_info->wrb_en) | - FIELD_SET(QDMA_CPM4_DMAP_SEL_CMPT_IRQ_EN_MASK, - reg_info->irq_en); - - qdma_reg_write(dev_hndl, reg_addr, reg_val); - - return QDMA_SUCCESS; -} - -/*****************************************************************************/ -/** - * qdma_cpm4_queue_intr_cidx_update() - function to update the - * CMPT CIDX update - * - * @dev_hndl: device handle - * @is_vf: Whether PF or VF - * @qid: Queue id relative to the PF/VF calling this API - * @reg_info: data needed for the CIDX register update - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -int qdma_cpm4_queue_intr_cidx_update(void *dev_hndl, uint8_t is_vf, - uint16_t qid, const struct qdma_intr_cidx_reg_info *reg_info) -{ - uint32_t reg_addr = (is_vf) ? - QDMA_CPM4_OFFSET_VF_DMAP_SEL_INT_CIDX : - QDMA_CPM4_OFFSET_DMAP_SEL_INT_CIDX; - uint32_t reg_val = 0; - - if (!dev_hndl) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - if (!reg_info) { - qdma_log_error("%s: reg_info is NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - reg_addr += qid * QDMA_INT_CIDX_STEP; - - reg_val = - FIELD_SET(QDMA_CPM4_DMA_SEL_INT_SW_CIDX_MASK, - reg_info->sw_cidx) | - FIELD_SET(QDMA_CPM4_DMA_SEL_INT_RING_IDX_MASK, - reg_info->rng_idx); - - qdma_reg_write(dev_hndl, reg_addr, reg_val); - - return QDMA_SUCCESS; -} - -/*****************************************************************************/ -/** - * qdma_cmp_get_user_bar() - Function to get the - * AXI Master Lite(user bar) number - * @dev_hndl: device handle - * @is_vf: Whether PF or VF - * @func_id: function id of the PF - * @user_bar: pointer to hold the AXI Master Lite(user bar) number - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -int qdma_cmp_get_user_bar(void *dev_hndl, uint8_t is_vf, - uint16_t func_id, uint8_t *user_bar) -{ - uint8_t bar_found = 0; - uint8_t bar_idx = 0; - uint32_t user_bar_id = 0; - uint32_t reg_addr = 0; - - if (!dev_hndl) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - if (!user_bar) { - qdma_log_error("%s: user_bar is NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - reg_addr = (is_vf) ? QDMA_CPM4_GLBL2_PF_VF_BARLITE_EXT_ADDR : - QDMA_CPM4_GLBL2_PF_BARLITE_EXT_ADDR; - - if (!is_vf) { - user_bar_id = qdma_reg_read(dev_hndl, reg_addr); - user_bar_id = (user_bar_id >> (6 * func_id)) & 0x3F; - } else { - *user_bar = QDMA_CPM4_VF_USER_BAR_ID; - return QDMA_SUCCESS; - } - - for (bar_idx = 0; bar_idx < QDMA_BAR_NUM; bar_idx++) { - if (user_bar_id & (1 << bar_idx)) { - *user_bar = bar_idx; - bar_found = 1; - break; - } - } - if (bar_found == 0) { - *user_bar = 0; - qdma_log_error("%s: Bar not found, err:%d\n", - __func__, - -QDMA_ERR_HWACC_BAR_NOT_FOUND); - return -QDMA_ERR_HWACC_BAR_NOT_FOUND; - } - - return QDMA_SUCCESS; -} - -/*****************************************************************************/ -/** - * qdma_cpm4_hw_ram_sbe_err_process() -Function to dump SBE err debug info - * - * @dev_hndl: device handle - * @buf: Bufffer for the debug info to be dumped in - * @buflen: Length of the buffer - * - * Return: void - *****************************************************************************/ -static void qdma_cpm4_hw_ram_sbe_err_process(void *dev_hndl) -{ - qdma_cpm4_dump_reg_info(dev_hndl, QDMA_CPM4_RAM_SBE_STS_A_ADDR, - 1, NULL, 0); -} - -/*****************************************************************************/ -/** - * qdma_cpm4_hw_ram_dbe_err_process() -Function to dump DBE err debug info - * - * @dev_hndl: device handle - * @buf: Bufffer for the debug info to be dumped in - * @buflen: Length of the buffer - * - * Return: void - *****************************************************************************/ -static void qdma_cpm4_hw_ram_dbe_err_process(void *dev_hndl) -{ - qdma_cpm4_dump_reg_info(dev_hndl, QDMA_CPM4_RAM_DBE_STS_A_ADDR, - 1, NULL, 0); -} - -/*****************************************************************************/ -/** - * qdma_cpm4_hw_desc_err_process() -Function to dump Descriptor Error info - * - * @dev_hndl: device handle - * @buf: Bufffer for the debug info to be dumped in - * @buflen: Length of the buffer - * - * Return: void - *****************************************************************************/ -static void qdma_cpm4_hw_desc_err_process(void *dev_hndl) -{ - int i = 0; - uint32_t desc_err_reg_list[] = { - QDMA_CPM4_GLBL_DSC_ERR_STS_ADDR, - QDMA_CPM4_GLBL_DSC_ERR_LOG0_ADDR, - QDMA_CPM4_GLBL_DSC_ERR_LOG1_ADDR, - QDMA_CPM4_GLBL_DSC_DBG_DAT0_ADDR, - QDMA_CPM4_GLBL_DSC_DBG_DAT1_ADDR - }; - int desc_err_num_regs = sizeof(desc_err_reg_list)/sizeof(uint32_t); - - for (i = 0; i < desc_err_num_regs; i++) { - qdma_cpm4_dump_reg_info(dev_hndl, - desc_err_reg_list[i], - 1, NULL, 0); - } -} - -/*****************************************************************************/ -/** - * qdma_cpm4_hw_trq_err_process() -Function to dump Target Access Err info - * - * @dev_hndl: device handle - * @buf: Bufffer for the debug info to be dumped in - * @buflen: Length of the buffer - * - * Return: void - *****************************************************************************/ -static void qdma_cpm4_hw_trq_err_process(void *dev_hndl) -{ - int i = 0; - uint32_t trq_err_reg_list[] = { - QDMA_CPM4_GLBL_TRQ_ERR_STS_ADDR, - QDMA_CPM4_GLBL_TRQ_ERR_LOG_ADDR - }; - int trq_err_reg_num_regs = sizeof(trq_err_reg_list)/sizeof(uint32_t); - - for (i = 0; i < trq_err_reg_num_regs; i++) { - qdma_cpm4_dump_reg_info(dev_hndl, trq_err_reg_list[i], - 1, NULL, 0); - } - - -} - -/*****************************************************************************/ -/** - * qdma_cpm4_hw_st_h2c_err_process() - Function to dump MM H2C Error info - * - * @dev_hndl: device handle - * @buf: Bufffer for the debug info to be dumped in - * @buflen: Length of the buffer - * - * Return: void - *****************************************************************************/ -static void qdma_cpm4_hw_st_h2c_err_process(void *dev_hndl) -{ - int i = 0; - uint32_t st_h2c_err_reg_list[] = { - QDMA_CPM4_H2C_ERR_STAT_ADDR, - QDMA_CPM4_H2C_FIRST_ERR_QID_ADDR, - QDMA_CPM4_H2C_DBG_REG0_ADDR, - QDMA_CPM4_H2C_DBG_REG1_ADDR, - QDMA_CPM4_H2C_DBG_REG2_ADDR, - QDMA_CPM4_H2C_DBG_REG3_ADDR, - QDMA_CPM4_H2C_DBG_REG4_ADDR - }; - int st_h2c_err_num_regs = sizeof(st_h2c_err_reg_list)/sizeof(uint32_t); - - for (i = 0; i < st_h2c_err_num_regs; i++) { - qdma_cpm4_dump_reg_info(dev_hndl, - st_h2c_err_reg_list[i], - 1, NULL, 0); - } -} - - -/*****************************************************************************/ -/** - * qdma_cpm4_hw_st_c2h_err_process() - Function to dump MM H2C Error info - * - * @dev_hndl: device handle - * @buf: Bufffer for the debug info to be dumped in - * @buflen: Length of the buffer - * - * Return: void - *****************************************************************************/ -static void qdma_cpm4_hw_st_c2h_err_process(void *dev_hndl) -{ - int i = 0; - uint32_t st_c2h_err_reg_list[] = { - QDMA_CPM4_C2H_ERR_STAT_ADDR, - QDMA_CPM4_C2H_FATAL_ERR_STAT_ADDR, - QDMA_CPM4_C2H_FIRST_ERR_QID_ADDR, - QDMA_CPM4_C2H_STAT_S_AXIS_C2H_ACCEPTED_ADDR, - QDMA_CPM4_C2H_STAT_S_AXIS_WRB_ACCEPTED_ADDR, - QDMA_CPM4_C2H_STAT_DESC_RSP_PKT_ACCEPTED_ADDR, - QDMA_CPM4_C2H_STAT_AXIS_PKG_CMP_ADDR, - QDMA_CPM4_C2H_STAT_DBG_DMA_ENG_0_ADDR, - QDMA_CPM4_C2H_STAT_DBG_DMA_ENG_1_ADDR, - QDMA_CPM4_C2H_STAT_DBG_DMA_ENG_2_ADDR, - QDMA_CPM4_C2H_STAT_DBG_DMA_ENG_3_ADDR, - QDMA_CPM4_C2H_STAT_DESC_RSP_DROP_ACCEPTED_ADDR, - QDMA_CPM4_C2H_STAT_DESC_RSP_ERR_ACCEPTED_ADDR - }; - int st_c2h_err_num_regs = sizeof(st_c2h_err_reg_list)/sizeof(uint32_t); - - for (i = 0; i < st_c2h_err_num_regs; i++) { - qdma_cpm4_dump_reg_info(dev_hndl, - st_c2h_err_reg_list[i], - 1, NULL, 0); - } -} - - - -/*****************************************************************************/ -/** - * qdma_cpm4_hw_get_error_name() - Function to get the error in str format - * - * @err_idx: error index - * - * Return: string - success and NULL on failure - *****************************************************************************/ -const char *qdma_cpm4_hw_get_error_name(uint32_t err_idx) -{ - if (err_idx >= QDMA_CPM4_ERRS_ALL) { - qdma_log_error("%s: err_idx=%d is invalid, returning NULL\n", - __func__, - (enum qdma_cpm4_error_idx)err_idx); - return NULL; - } - - return qdma_cpm4_err_info[ - (enum qdma_cpm4_error_idx)err_idx].err_name; -} - -/*****************************************************************************/ -/** - * qdma_cpm4_hw_error_process() - Function to find the error that got - * triggered and call the handler qdma_hw_error_handler of that - * particular error. - * - * @dev_hndl: device handle - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -int qdma_cpm4_hw_error_process(void *dev_hndl) -{ - uint32_t glbl_err_stat = 0, err_stat = 0; - uint32_t i = 0, j = 0; - int32_t idx = 0; - struct qdma_dev_attributes dev_cap; - uint32_t hw_err_position[QDMA_CPM4_TOTAL_LEAF_ERROR_AGGREGATORS] = { - QDMA_CPM4_DSC_ERR_POISON, - QDMA_CPM4_TRQ_ERR_UNMAPPED, - QDMA_CPM4_ST_C2H_ERR_MTY_MISMATCH, - QDMA_CPM4_ST_FATAL_ERR_MTY_MISMATCH, - QDMA_CPM4_ST_H2C_ERR_ZERO_LEN_DESC_ERR, - QDMA_CPM4_SBE_ERR_MI_H2C0_DAT, - QDMA_CPM4_DBE_ERR_MI_H2C0_DAT - }; - - if (!dev_hndl) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - - qdma_cpm4_get_device_attributes(dev_hndl, &dev_cap); - - glbl_err_stat = qdma_reg_read(dev_hndl, - QDMA_CPM4_GLBL_ERR_STAT_ADDR); - if (!glbl_err_stat) - return QDMA_HW_ERR_NOT_DETECTED; - - qdma_log_info("%s: Global Err Reg(0x%x) = 0x%x\n", - __func__, QDMA_CPM4_GLBL_ERR_STAT_ADDR, - glbl_err_stat); - - for (i = 0; i < QDMA_CPM4_TOTAL_LEAF_ERROR_AGGREGATORS; i++) { - j = hw_err_position[i]; - - if ((!dev_cap.st_en) && - (j == QDMA_CPM4_ST_C2H_ERR_MTY_MISMATCH || - j == QDMA_CPM4_ST_FATAL_ERR_MTY_MISMATCH || - j == QDMA_CPM4_ST_H2C_ERR_ZERO_LEN_DESC_ERR)) - continue; - - err_stat = qdma_reg_read(dev_hndl, - qdma_cpm4_err_info[j].stat_reg_addr); - if (err_stat) { - qdma_log_info("addr = 0x%08x val = 0x%08x", - qdma_cpm4_err_info[j].stat_reg_addr, - err_stat); - - qdma_cpm4_err_info[j].qdma_cpm4_hw_err_process( - dev_hndl); - for (idx = j; - idx < all_qdma_cpm4_hw_errs[i]; - idx++) { - /* call the platform specific handler */ - if (err_stat & - qdma_cpm4_err_info[idx].leaf_err_mask) - qdma_log_error("%s detected %s\n", - __func__, - qdma_cpm4_hw_get_error_name( - idx)); - } - qdma_reg_write(dev_hndl, - qdma_cpm4_err_info[j].stat_reg_addr, - err_stat); - } - - } - - /* Write 1 to the global status register to clear the bits */ - qdma_reg_write(dev_hndl, - QDMA_CPM4_GLBL_ERR_STAT_ADDR, glbl_err_stat); - - return QDMA_SUCCESS; -} - -/*****************************************************************************/ -/** - * qdma_hw_error_enable() - Function to enable all or a specific error - * - * @dev_hndl: device handle - * @err_idx: error index - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -int qdma_cpm4_hw_error_enable(void *dev_hndl, uint32_t err_idx) -{ - uint32_t idx = 0, i = 0; - uint32_t reg_val = 0; - struct qdma_dev_attributes dev_cap; - - if (!dev_hndl) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - if (err_idx > QDMA_CPM4_ERRS_ALL) { - qdma_log_error("%s: err_idx=%d is invalid, err:%d\n", - __func__, (enum qdma_cpm4_error_idx)err_idx, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - qdma_cpm4_get_device_attributes(dev_hndl, &dev_cap); - - if (err_idx == QDMA_CPM4_ERRS_ALL) { - for (i = 0; - i < QDMA_CPM4_TOTAL_LEAF_ERROR_AGGREGATORS; - i++) { - - idx = all_qdma_cpm4_hw_errs[i]; - - /* Don't access streaming registers in - * MM only bitstreams - */ - if (!dev_cap.st_en) { - if (idx == QDMA_CPM4_ST_C2H_ERR_ALL || - idx == QDMA_CPM4_ST_FATAL_ERR_ALL || - idx == QDMA_CPM4_ST_H2C_ERR_ALL) - continue; - } - - reg_val = qdma_cpm4_err_info[idx].leaf_err_mask; - qdma_reg_write(dev_hndl, - qdma_cpm4_err_info[idx].mask_reg_addr, - reg_val); - - reg_val = qdma_reg_read(dev_hndl, - QDMA_CPM4_GLBL_ERR_MASK_ADDR); - reg_val |= FIELD_SET( - qdma_cpm4_err_info[idx].global_err_mask, 1); - qdma_reg_write(dev_hndl, - QDMA_CPM4_GLBL_ERR_MASK_ADDR, - reg_val); - } - - } else { - /* Don't access streaming registers in MM only bitstreams - * QDMA_C2H_ERR_MTY_MISMATCH to QDMA_H2C_ERR_ALL are all - * ST errors - */ - if (!dev_cap.st_en) { - if (err_idx >= QDMA_CPM4_ST_C2H_ERR_MTY_MISMATCH && - err_idx <= QDMA_CPM4_ST_H2C_ERR_ALL) - return QDMA_SUCCESS; - } - - reg_val = qdma_reg_read(dev_hndl, - qdma_cpm4_err_info[err_idx].mask_reg_addr); - reg_val |= - FIELD_SET(qdma_cpm4_err_info[err_idx].leaf_err_mask, - 1); - qdma_reg_write(dev_hndl, - qdma_cpm4_err_info[err_idx].mask_reg_addr, - reg_val); - - reg_val = qdma_reg_read(dev_hndl, - QDMA_CPM4_GLBL_ERR_MASK_ADDR); - reg_val |= - FIELD_SET( - qdma_cpm4_err_info[err_idx].global_err_mask, - 1); - qdma_reg_write(dev_hndl, - QDMA_CPM4_GLBL_ERR_MASK_ADDR, reg_val); - } - - return QDMA_SUCCESS; -} - -/*****************************************************************************/ -/** - * qdma_cpm4_get_device_attributes() - Function to get the qdma - * device attributes - * - * @dev_hndl: device handle - * @dev_info: pointer to hold the device info - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -int qdma_cpm4_get_device_attributes(void *dev_hndl, - struct qdma_dev_attributes *dev_info) -{ - uint8_t count = 0; - uint32_t reg_val = 0; - - if (!dev_hndl) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - if (!dev_info) { - qdma_log_error("%s: dev_info is NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - /* number of PFs */ - reg_val = qdma_reg_read(dev_hndl, - QDMA_CPM4_GLBL2_PF_BARLITE_INT_ADDR); - if (FIELD_GET(GLBL2_PF_BARLITE_INT_PF0_BAR_MAP_MASK, reg_val)) - count++; - if (FIELD_GET(GLBL2_PF_BARLITE_INT_PF1_BAR_MAP_MASK, reg_val)) - count++; - if (FIELD_GET(GLBL2_PF_BARLITE_INT_PF2_BAR_MAP_MASK, reg_val)) - count++; - if (FIELD_GET(GLBL2_PF_BARLITE_INT_PF3_BAR_MAP_MASK, reg_val)) - count++; - dev_info->num_pfs = count; - - /* Number of Qs */ - reg_val = qdma_reg_read(dev_hndl, QDMA_CPM4_GLBL2_CHANNEL_CAP_ADDR); - dev_info->num_qs = (FIELD_GET(GLBL2_CHANNEL_CAP_MULTIQ_MAX_MASK, - reg_val)); - - /* FLR present */ - reg_val = qdma_reg_read(dev_hndl, QDMA_CPM4_GLBL2_MISC_CAP_ADDR); - dev_info->mailbox_en = FIELD_GET(QDMA_GLBL2_MAILBOX_EN_MASK, reg_val); - dev_info->flr_present = FIELD_GET(QDMA_GLBL2_FLR_PRESENT_MASK, reg_val); - dev_info->mm_cmpt_en = 0; - - /* ST/MM enabled? */ - reg_val = qdma_reg_read(dev_hndl, - QDMA_CPM4_GLBL2_CHANNEL_MDMA_ADDR); - dev_info->mm_en = (FIELD_GET(GLBL2_CHANNEL_MDMA_C2H_ENG_MASK, reg_val) - && FIELD_GET(GLBL2_CHANNEL_MDMA_H2C_ENG_MASK, reg_val)) ? 1 : 0; - dev_info->st_en = (FIELD_GET(GLBL2_CHANNEL_MDMA_C2H_ST_MASK, reg_val) - && FIELD_GET(GLBL2_CHANNEL_MDMA_H2C_ST_MASK, - reg_val)) ? 1 : 0; - - /* num of mm channels for Versal Hard is 2 */ - dev_info->mm_channel_max = 2; - - dev_info->debug_mode = 0; - dev_info->desc_eng_mode = 0; - dev_info->qid2vec_ctx = 1; - dev_info->cmpt_ovf_chk_dis = 0; - dev_info->mailbox_intr = 0; - dev_info->sw_desc_64b = 0; - dev_info->cmpt_desc_64b = 0; - dev_info->dynamic_bar = 0; - dev_info->legacy_intr = 0; - dev_info->cmpt_trig_count_timer = 0; - - return QDMA_SUCCESS; -} - - -/*****************************************************************************/ -/** - * qdma_cpm4_credit_context_read() - read credit context - * - * @dev_hndl: device handle - * @c2h : is c2h queue - * @hw_qid : hardware qid of the queue - * @ctxt : pointer to the context data - * - * Return : 0 - success and < 0 - failure - *****************************************************************************/ -static int qdma_cpm4_credit_context_read(void *dev_hndl, uint8_t c2h, - uint16_t hw_qid, - struct qdma_descq_credit_ctxt *ctxt) -{ - int rv = QDMA_SUCCESS; - uint32_t cr_ctxt[QDMA_CPM4_CR_CONTEXT_NUM_WORDS] = {0}; - enum ind_ctxt_cmd_sel sel = c2h ? QDMA_CTXT_SEL_CR_C2H : - QDMA_CTXT_SEL_CR_H2C; - - if (!dev_hndl || !ctxt) { - qdma_log_error("%s: dev_hndl=%p credit_ctxt=%p, err:%d\n", - __func__, dev_hndl, ctxt, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - rv = qdma_cpm4_indirect_reg_read(dev_hndl, sel, hw_qid, - QDMA_CPM4_CR_CONTEXT_NUM_WORDS, cr_ctxt); - if (rv < 0) - return rv; - - ctxt->credit = FIELD_GET(CRED_CTXT_DATA_W0_CREDT_MASK, - cr_ctxt[0]); - - qdma_log_debug("%s: credit=%u\n", __func__, ctxt->credit); - - return QDMA_SUCCESS; -} - -/*****************************************************************************/ -/** - * qdma_cpm4_credit_context_clear() - clear credit context - * - * @dev_hndl: device handle - * @c2h : is c2h queue - * @hw_qid : hardware qid of the queue - * - * Return : 0 - success and < 0 - failure - *****************************************************************************/ -static int qdma_cpm4_credit_context_clear(void *dev_hndl, uint8_t c2h, - uint16_t hw_qid) -{ - enum ind_ctxt_cmd_sel sel = c2h ? QDMA_CTXT_SEL_CR_C2H : - QDMA_CTXT_SEL_CR_H2C; - - if (!dev_hndl) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", __func__, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - return qdma_cpm4_indirect_reg_clear(dev_hndl, sel, hw_qid); -} - -/*****************************************************************************/ -/** - * qdma_cpm4_credit_context_invalidate() - invalidate credit context - * - * @dev_hndl: device handle - * @c2h : is c2h queue - * @hw_qid : hardware qid of the queue - * - * Return : 0 - success and < 0 - failure - *****************************************************************************/ -static int qdma_cpm4_credit_context_invalidate(void *dev_hndl, uint8_t c2h, - uint16_t hw_qid) -{ - enum ind_ctxt_cmd_sel sel = c2h ? QDMA_CTXT_SEL_CR_C2H : - QDMA_CTXT_SEL_CR_H2C; - - if (!dev_hndl) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", __func__, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - return qdma_cpm4_indirect_reg_invalidate(dev_hndl, sel, hw_qid); -} - -/*****************************************************************************/ -/** - * qdma_cpm4_credit_ctx_conf() - configure credit context - * - * @dev_hndl : device handle - * @c2h : is c2h queue - * @hw_qid : hardware qid of the queue - * @ctxt : pointer to the context data - * @access_type : HW access type (qdma_hw_access_type enum) value - * QDMA_HW_ACCESS_WRITE Not supported - * - * Return : 0 - success and < 0 - failure - *****************************************************************************/ -int qdma_cpm4_credit_ctx_conf(void *dev_hndl, uint8_t c2h, uint16_t hw_qid, - struct qdma_descq_credit_ctxt *ctxt, - enum qdma_hw_access_type access_type) -{ - int rv = QDMA_SUCCESS; - - switch (access_type) { - case QDMA_HW_ACCESS_READ: - rv = qdma_cpm4_credit_context_read(dev_hndl, c2h, - hw_qid, ctxt); - break; - case QDMA_HW_ACCESS_CLEAR: - rv = qdma_cpm4_credit_context_clear(dev_hndl, c2h, hw_qid); - break; - case QDMA_HW_ACCESS_INVALIDATE: - rv = qdma_cpm4_credit_context_invalidate(dev_hndl, c2h, - hw_qid); - break; - case QDMA_HW_ACCESS_WRITE: - default: - qdma_log_error("%s: Invalid access type=%d, err:%d\n", - __func__, access_type, - -QDMA_ERR_INV_PARAM); - rv = -QDMA_ERR_INV_PARAM; - break; - } - - return rv; -} - - -/*****************************************************************************/ -/** - * qdma_cpm4_dump_config_regs() - Function to get qdma config register - * dump in a buffer - * - * @dev_hndl: device handle - * @is_vf: Whether PF or VF - * @buf : pointer to buffer to be filled - * @buflen : Length of the buffer - * - * Return: Length up-till the buffer is filled -success and < 0 - failure - *****************************************************************************/ -int qdma_cpm4_dump_config_regs(void *dev_hndl, uint8_t is_vf, - char *buf, uint32_t buflen) -{ - uint32_t i = 0, j = 0; - struct xreg_info *reg_info; - uint32_t num_regs = qdma_cpm4_config_num_regs_get(); - uint32_t len = 0, val = 0; - int rv = QDMA_SUCCESS; - char name[DEBGFS_GEN_NAME_SZ] = ""; - struct qdma_dev_attributes dev_cap; - - if (!dev_hndl) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - if (buflen < qdma_cpm4_reg_dump_buf_len()) { - qdma_log_error("%s: Buffer too small, err:%d\n", __func__, - -QDMA_ERR_NO_MEM); - return -QDMA_ERR_NO_MEM; - } - - if (is_vf) { - qdma_log_error("%s: Wrong API used for VF, err:%d\n", - __func__, - -QDMA_ERR_HWACC_FEATURE_NOT_SUPPORTED); - return -QDMA_ERR_HWACC_FEATURE_NOT_SUPPORTED; - } - - qdma_cpm4_get_device_attributes(dev_hndl, &dev_cap); - - reg_info = qdma_cpm4_config_regs_get(); - - for (i = 0; i < num_regs; i++) { - if ((GET_CAPABILITY_MASK(dev_cap.mm_en, dev_cap.st_en, - dev_cap.mm_cmpt_en, dev_cap.mailbox_en) - & reg_info[i].mode) == 0) - continue; - - for (j = 0; j < reg_info[i].repeat; j++) { - rv = QDMA_SNPRINTF_S(name, DEBGFS_GEN_NAME_SZ, - DEBGFS_GEN_NAME_SZ, - "%s_%d", reg_info[i].name, j); - if ((rv < 0) || (rv > DEBGFS_GEN_NAME_SZ)) { - qdma_log_error( - "%d:%s QDMA_SNPRINTF_S() failed, err:%d\n", - __LINE__, __func__, - rv); - return -QDMA_ERR_NO_MEM; - } - - val = qdma_reg_read(dev_hndl, - (reg_info[i].addr + (j * 4))); - rv = dump_reg(buf + len, buflen - len, - (reg_info[i].addr + (j * 4)), - name, val); - if (rv < 0) { - qdma_log_error( - "%s Buff too small, err:%d\n", - __func__, - -QDMA_ERR_NO_MEM); - return -QDMA_ERR_NO_MEM; - } - len += rv; - } - } - - return len; -} - -/*****************************************************************************/ -/** - * qdma_dump_cpm4_queue_context() - Function to get qdma queue context dump - * in a buffer - * - * @dev_hndl: device handle - * @hw_qid: queue id - * @buf : pointer to buffer to be filled - * @buflen : Length of the buffer - * - * Return: Length up-till the buffer is filled -success and < 0 - failure - *****************************************************************************/ -int qdma_cpm4_dump_queue_context(void *dev_hndl, - uint8_t st, - enum qdma_dev_q_type q_type, - struct qdma_descq_context *ctxt_data, - char *buf, uint32_t buflen) -{ - int rv = 0; - uint32_t req_buflen = 0; - - if (!dev_hndl) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - - return -QDMA_ERR_INV_PARAM; - } - - if (!ctxt_data) { - qdma_log_error("%s: ctxt_data is NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - - return -QDMA_ERR_INV_PARAM; - } - - if (!buf) { - qdma_log_error("%s: buf is NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - - return -QDMA_ERR_INV_PARAM; - } - if (q_type >= QDMA_DEV_Q_TYPE_MAX) { - qdma_log_error("%s: invalid q_type, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - - return -QDMA_ERR_INV_PARAM; - } - - rv = qdma_cpm4_context_buf_len(st, q_type, &req_buflen); - if (rv != QDMA_SUCCESS) - return rv; - - if (buflen < req_buflen) { - qdma_log_error("%s: Too small buffer(%d), reqd(%d), err:%d\n", - __func__, buflen, req_buflen, -QDMA_ERR_NO_MEM); - return -QDMA_ERR_NO_MEM; - } - - rv = dump_cpm4_context(ctxt_data, st, q_type, - buf, buflen); - - return rv; -} - -/*****************************************************************************/ -/** - * qdma_dump_cpm4_intr_context() - Function to get qdma interrupt - * context dump in a buffer - * - * @dev_hndl: device handle - * @hw_qid: queue id - * @buf : pointer to buffer to be filled - * @buflen : Length of the buffer - * - * Return: Length up-till the buffer is filled -success and < 0 - failure - *****************************************************************************/ -int qdma_cpm4_dump_intr_context(void *dev_hndl, - struct qdma_indirect_intr_ctxt *intr_ctx, - int ring_index, - char *buf, uint32_t buflen) -{ - int rv = 0; - uint32_t req_buflen = 0; - - if (!dev_hndl) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - - return -QDMA_ERR_INV_PARAM; - } - - if (!intr_ctx) { - qdma_log_error("%s: intr_ctx is NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - - return -QDMA_ERR_INV_PARAM; - } - - if (!buf) { - qdma_log_error("%s: buf is NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - req_buflen = qdma_cpm4_intr_context_buf_len(); - if (buflen < req_buflen) { - qdma_log_error("%s: Too small buffer(%d), reqd(%d), err:%d\n", - __func__, buflen, req_buflen, -QDMA_ERR_NO_MEM); - return -QDMA_ERR_NO_MEM; - } - - rv = dump_cpm4_intr_context(intr_ctx, ring_index, buf, buflen); - - return rv; -} - -/*****************************************************************************/ -/** - * qdma_cpm4_read_dump_queue_context() - Function to read and dump the queue - * context in a buffer - * - * @dev_hndl: device handle - * @func_id: function id - * @hw_qid: queue id - * @st: Queue Mode(ST or MM) - * @q_type: Queue type(H2C/C2H/CMPT) - * @buf : pointer to buffer to be filled - * @buflen : Length of the buffer - * - * Return: Length up-till the buffer is filled -success and < 0 - failure - *****************************************************************************/ -int qdma_cpm4_read_dump_queue_context(void *dev_hndl, - uint16_t func_id, - uint16_t qid_hw, - uint8_t st, - enum qdma_dev_q_type q_type, - char *buf, uint32_t buflen) -{ - int rv = QDMA_SUCCESS; - uint32_t req_buflen = 0; - struct qdma_descq_context context; - - if (!dev_hndl) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - - return -QDMA_ERR_INV_PARAM; - } - - if (!buf) { - qdma_log_error("%s: buf is NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - - return -QDMA_ERR_INV_PARAM; - } - - if (q_type >= QDMA_DEV_Q_TYPE_CMPT) { - qdma_log_error("%s: Not supported for q_type, err = %d\n", - __func__, -QDMA_ERR_INV_PARAM); - - return -QDMA_ERR_INV_PARAM; - } - - rv = qdma_cpm4_context_buf_len(st, q_type, &req_buflen); - - if (rv != QDMA_SUCCESS) - return rv; - - if (buflen < req_buflen) { - qdma_log_error("%s: Too small buffer(%d), reqd(%d), err:%d\n", - __func__, buflen, req_buflen, -QDMA_ERR_NO_MEM); - return -QDMA_ERR_NO_MEM; - } - - qdma_memset(&context, 0, sizeof(struct qdma_descq_context)); - - if (q_type != QDMA_DEV_Q_TYPE_CMPT) { - rv = qdma_cpm4_sw_ctx_conf(dev_hndl, (uint8_t)q_type, - qid_hw, &(context.sw_ctxt), - QDMA_HW_ACCESS_READ); - if (rv < 0) { - qdma_log_error( - "%s: Failed to read sw context, err = %d", - __func__, rv); - return rv; - } - - rv = qdma_cpm4_hw_ctx_conf(dev_hndl, (uint8_t)q_type, - qid_hw, &(context.hw_ctxt), - QDMA_HW_ACCESS_READ); - if (rv < 0) { - qdma_log_error( - "%s: Failed to read hw context, err = %d", - __func__, rv); - return rv; - } - - rv = qdma_cpm4_qid2vec_conf(dev_hndl, (uint8_t)q_type, - qid_hw, &(context.qid2vec), - QDMA_HW_ACCESS_READ); - if (rv < 0) { - qdma_log_error( - "%s: Failed to read qid2vec context, err = %d", - __func__, rv); - return rv; - } - - rv = qdma_cpm4_credit_ctx_conf(dev_hndl, (uint8_t)q_type, - qid_hw, &(context.cr_ctxt), - QDMA_HW_ACCESS_READ); - if (rv < 0) { - qdma_log_error( - "%s: Failed to read credit context, err = %d", - __func__, rv); - return rv; - } - - if (st && (q_type == QDMA_DEV_Q_TYPE_C2H)) { - rv = qdma_cpm4_pfetch_ctx_conf(dev_hndl, - qid_hw, - &(context.pfetch_ctxt), - QDMA_HW_ACCESS_READ); - if (rv < 0) { - qdma_log_error( - "%s: Failed to read pftech context, err = %d", - __func__, rv); - return rv; - } - } - } - - if ((st && (q_type == QDMA_DEV_Q_TYPE_C2H)) || - (!st && (q_type == QDMA_DEV_Q_TYPE_CMPT))) { - rv = qdma_cpm4_cmpt_ctx_conf(dev_hndl, qid_hw, - &(context.cmpt_ctxt), - QDMA_HW_ACCESS_READ); - if (rv < 0) { - qdma_log_error( - "%s: Failed to read cmpt context, err = %d", - __func__, rv); - return rv; - } - } - - rv = qdma_cpm4_fmap_conf(dev_hndl, func_id, - &(context.fmap), QDMA_HW_ACCESS_READ); - if (rv < 0) { - qdma_log_error( - "%s: Failed to read fmap context, err = %d", - __func__, rv); - return rv; - } - - rv = dump_cpm4_context(&context, st, q_type, - buf, buflen); - - return rv; -} - -/*****************************************************************************/ -/** - * qdma_cpm4_init_ctxt_memory() - Initialize the context for all queues - * - * @dev_hndl : device handle - * - * Return : 0 - success and < 0 - failure - *****************************************************************************/ - -int qdma_cpm4_init_ctxt_memory(void *dev_hndl) -{ -#ifdef ENABLE_INIT_CTXT_MEMORY - uint32_t data[QDMA_REG_IND_CTXT_REG_COUNT]; - uint16_t i = 0; - struct qdma_dev_attributes dev_info; - - if (!dev_hndl) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - qdma_memset(data, 0, sizeof(uint32_t) * QDMA_REG_IND_CTXT_REG_COUNT); - qdma_cpm4_get_device_attributes(dev_hndl, &dev_info); - qdma_log_info("%s: clearing the context for all qs", - __func__); - for (; i < dev_info.num_qs; i++) { - int sel = QDMA_CTXT_SEL_SW_C2H; - int rv; - - -#ifdef TANDEM_BOOT_SUPPORTED - for (; sel <= QDMA_CTXT_SEL_CR_H2C; sel++) { - rv = qdma_cpm4_indirect_reg_clear(dev_hndl, - (enum ind_ctxt_cmd_sel)sel, i); - if (rv < 0) - return rv; - } -#else - for (; sel <= QDMA_CTXT_SEL_PFTCH; sel++) { - /** if the st mode(h2c/c2h) not enabled - * in the design, then skip the PFTCH - * and CMPT context setup - */ - if ((dev_info.st_en == 0) && - (sel == QDMA_CTXT_SEL_PFTCH || - sel == QDMA_CTXT_SEL_CMPT)) { - qdma_log_debug("%s: ST context is skipped:", - __func__); - qdma_log_debug(" sel = %d", sel); - continue; - } - - rv = qdma_cpm4_indirect_reg_clear(dev_hndl, - (enum ind_ctxt_cmd_sel)sel, i); - if (rv < 0) - return rv; - } -#endif - } - - /* fmap */ - for (i = 0; i < dev_info.num_pfs; i++) - qdma_cpm4_fmap_clear(dev_hndl, i); -#else - if (!dev_hndl) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } -#endif - return 0; -} - -#ifdef TANDEM_BOOT_SUPPORTED -/*****************************************************************************/ -/** - * qdma_cpm4_init_st_ctxt() - Initialize the ST context - * - * @dev_hndl: device handle - * - * Return: returns the platform specific error code - *****************************************************************************/ -int qdma_cpm4_init_st_ctxt(void *dev_hndl) -{ - uint32_t data[QDMA_REG_IND_CTXT_REG_COUNT]; - uint16_t i = 0; - struct qdma_dev_attributes dev_info; - - if (!dev_hndl) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - qdma_memset(data, 0, sizeof(uint32_t) * QDMA_REG_IND_CTXT_REG_COUNT); - qdma_cpm4_get_device_attributes(dev_hndl, &dev_info); - - for (; i < dev_info.num_qs; i++) { - int sel = QDMA_CTXT_SEL_CMPT; - int rv; - - for (; sel <= QDMA_CTXT_SEL_PFTCH; sel++) { - /** if the st mode(h2c/c2h) not enabled - * in the design, then skip the PFTCH - * and CMPT context setup - */ - if ((dev_info.st_en == 0) && - ((sel == QDMA_CTXT_SEL_PFTCH) || - (sel == QDMA_CTXT_SEL_CMPT))) { - qdma_log_debug("%s: ST context is skipped:", - __func__); - qdma_log_debug("sel = %d\n", sel); - continue; - } - - rv = qdma_cpm4_indirect_reg_clear(dev_hndl, - (enum ind_ctxt_cmd_sel)sel, i); - if (rv < 0) - return rv; - } - } - - return QDMA_SUCCESS; - -} -#endif - -static int get_reg_entry(uint32_t reg_addr, int *reg_entry) -{ - uint32_t i = 0; - struct xreg_info *reg_info; - uint32_t num_regs = qdma_cpm4_config_num_regs_get(); - - reg_info = qdma_cpm4_config_regs_get(); - - for (i = 0; (i < num_regs - 1); i++) { - if (reg_info[i].addr == reg_addr) { - *reg_entry = i; - break; - } - } - - if (i >= num_regs - 1) { - qdma_log_error("%s: 0x%08x is missing register list, err:%d\n", - __func__, - reg_addr, - -QDMA_ERR_INV_PARAM); - *reg_entry = -1; - return -QDMA_ERR_INV_PARAM; - } - - return 0; -} - -/*****************************************************************************/ -/** - * qdma_cpm4_dump_config_reg_list() - Dump the registers - * - * @dev_hndl: device handle - * @total_regs : Max registers to read - * @reg_list : array of reg addr and reg values - * @buf : pointer to buffer to be filled - * @buflen : Length of the buffer - * - * Return: returns the platform specific error code - *****************************************************************************/ -int qdma_cpm4_dump_config_reg_list(void *dev_hndl, uint32_t total_regs, - struct qdma_reg_data *reg_list, char *buf, uint32_t buflen) -{ - uint32_t j = 0, len = 0; - uint32_t reg_count = 0; - int reg_data_entry; - int rv = 0; - char name[DEBGFS_GEN_NAME_SZ] = ""; - struct xreg_info *reg_info = qdma_cpm4_config_regs_get(); - - if (!dev_hndl) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - if (!buf) { - qdma_log_error("%s: buf is NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - for (reg_count = 0; - (reg_count < total_regs);) { - - rv = get_reg_entry(reg_list[reg_count].reg_addr, - ®_data_entry); - if (rv < 0) { - qdma_log_error("%s: register missing in list, err:%d\n", - __func__, - -QDMA_ERR_INV_PARAM); - return rv; - } - - for (j = 0; j < reg_info[reg_data_entry].repeat; j++) { - rv = QDMA_SNPRINTF_S(name, DEBGFS_GEN_NAME_SZ, - DEBGFS_GEN_NAME_SZ, - "%s_%d", - reg_info[reg_data_entry].name, j); - if ((rv < 0) || (rv > DEBGFS_GEN_NAME_SZ)) { - qdma_log_error( - "%d:%s snprintf failed, err:%d\n", - __LINE__, __func__, - rv); - return -QDMA_ERR_NO_MEM; - } - rv = dump_reg(buf + len, buflen - len, - (reg_info[reg_data_entry].addr + (j * 4)), - name, - reg_list[reg_count + j].reg_val); - if (rv < 0) { - qdma_log_error( - "%s Buff too small, err:%d\n", - __func__, - -QDMA_ERR_NO_MEM); - return -QDMA_ERR_NO_MEM; - } - len += rv; - } - reg_count += j; - } - - return len; - -} - - -/*****************************************************************************/ -/** - * qdma_read_reg_list() - read the register values - * - * @dev_hndl: device handle - * @is_vf: Whether PF or VF - * @total_regs : Max registers to read - * @reg_list : array of reg addr and reg values - * - * Return: returns the platform specific error code - *****************************************************************************/ -int qdma_cpm4_read_reg_list(void *dev_hndl, uint8_t is_vf, - uint16_t reg_rd_slot, - uint16_t *total_regs, - struct qdma_reg_data *reg_list) -{ - uint16_t reg_count = 0, i = 0, j = 0; - uint32_t num_regs = qdma_cpm4_config_num_regs_get(); - struct xreg_info *reg_info = qdma_cpm4_config_regs_get(); - struct qdma_dev_attributes dev_cap; - uint32_t reg_start_addr = 0; - int reg_index = 0; - int rv = 0; - - if (!is_vf) { - qdma_log_error("%s: not supported for PF, err:%d\n", - __func__, - -QDMA_ERR_HWACC_FEATURE_NOT_SUPPORTED); - return -QDMA_ERR_HWACC_FEATURE_NOT_SUPPORTED; - } - - if (!dev_hndl) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - if (!reg_list) { - qdma_log_error("%s: reg_list is NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - qdma_cpm4_get_device_attributes(dev_hndl, &dev_cap); - - switch (reg_rd_slot) { - case QDMA_REG_READ_GROUP_1: - reg_start_addr = QDMA_CPM4_REG_GROUP_1_START_ADDR; - break; - case QDMA_REG_READ_GROUP_2: - reg_start_addr = QDMA_CPM4_REG_GROUP_2_START_ADDR; - break; - case QDMA_REG_READ_GROUP_3: - reg_start_addr = QDMA_CPM4_REG_GROUP_3_START_ADDR; - break; - case QDMA_REG_READ_GROUP_4: - reg_start_addr = QDMA_CPM4_REG_GROUP_4_START_ADDR; - break; - default: - qdma_log_error("%s: Invalid slot received\n", - __func__); - return -QDMA_ERR_INV_PARAM; - } - - rv = get_reg_entry(reg_start_addr, ®_index); - if (rv < 0) { - qdma_log_error("%s: register missing in list, err:%d\n", - __func__, - -QDMA_ERR_INV_PARAM); - return rv; - } - - for (i = 0, reg_count = 0; - ((i < num_regs - 1 - reg_index) && - (reg_count < QDMA_MAX_REGISTER_DUMP)); i++) { - - if (((GET_CAPABILITY_MASK(dev_cap.mm_en, dev_cap.st_en, - dev_cap.mm_cmpt_en, dev_cap.mailbox_en) - & reg_info[i].mode) == 0) || - (reg_info[i].read_type == QDMA_REG_READ_PF_ONLY)) - continue; - - for (j = 0; j < reg_info[i].repeat && - (reg_count < QDMA_MAX_REGISTER_DUMP); - j++) { - reg_list[reg_count].reg_addr = - (reg_info[i].addr + (j * 4)); - reg_list[reg_count].reg_val = - qdma_reg_read(dev_hndl, - reg_list[reg_count].reg_addr); - reg_count++; - } - } - - *total_regs = reg_count; - return rv; -} - -/*****************************************************************************/ -/** - * qdma_cpm4_write_global_ring_sizes() - set the global ring size array - * - * @dev_hndl: device handle - * @index: Index from where the values needs to written - * @count: number of entries to be written - * @glbl_rng_sz: pointer to the array having the values to write - * - * (index + count) shall not be more than 16 - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -static int qdma_cpm4_write_global_ring_sizes(void *dev_hndl, uint8_t index, - uint8_t count, const uint32_t *glbl_rng_sz) -{ - if (!dev_hndl || !glbl_rng_sz || !count) { - qdma_log_error("%s: dev_hndl=%p glbl_rng_sz=%p, err:%d\n", - __func__, dev_hndl, glbl_rng_sz, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - if ((index + count) > QDMA_NUM_RING_SIZES) { - qdma_log_error("%s: index=%u count=%u > %d, err:%d\n", - __func__, index, count, - QDMA_NUM_RING_SIZES, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - qdma_write_csr_values(dev_hndl, - QDMA_CPM4_GLBL_RNG_SZ_1_ADDR, index, count, - glbl_rng_sz); - - return QDMA_SUCCESS; -} - -/*****************************************************************************/ -/** - * qdma_cpm4_read_global_ring_sizes() - function to get the - * global rng_sz array - * - * @dev_hndl: device handle - * @index: Index from where the values needs to read - * @count: number of entries to be read - * @glbl_rng_sz: pointer to array to hold the values read - * - * (index + count) shall not be more than 16 - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -static int qdma_cpm4_read_global_ring_sizes(void *dev_hndl, uint8_t index, - uint8_t count, uint32_t *glbl_rng_sz) -{ - if (!dev_hndl || !glbl_rng_sz || !count) { - qdma_log_error("%s: dev_hndl=%p glbl_rng_sz=%p, err:%d\n", - __func__, dev_hndl, glbl_rng_sz, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - if ((index + count) > QDMA_NUM_RING_SIZES) { - qdma_log_error("%s: index=%u count=%u > %d, err:%d\n", - __func__, index, count, - QDMA_NUM_C2H_BUFFER_SIZES, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - qdma_read_csr_values(dev_hndl, - QDMA_CPM4_GLBL_RNG_SZ_1_ADDR, index, count, - glbl_rng_sz); - - return QDMA_SUCCESS; -} - -/*****************************************************************************/ -/** - * qdma_cpm4_write_global_timer_count() - function to set the timer values - * - * @dev_hndl: device handle - * @glbl_tmr_cnt: pointer to the array having the values to write - * @index: Index from where the values needs to written - * @count: number of entries to be written - * - * (index + count) shall not be more than 16 - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -static int qdma_cpm4_write_global_timer_count(void *dev_hndl, uint8_t index, - uint8_t count, const uint32_t *glbl_tmr_cnt) -{ - struct qdma_dev_attributes dev_cap; - - if (!dev_hndl || !glbl_tmr_cnt || !count) { - qdma_log_error("%s: dev_hndl=%p glbl_tmr_cnt=%p, err:%d\n", - __func__, dev_hndl, glbl_tmr_cnt, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - if ((index + count) > QDMA_NUM_C2H_TIMERS) { - qdma_log_error("%s: index=%u count=%u > %d, err:%d\n", - __func__, index, count, - QDMA_NUM_C2H_TIMERS, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - qdma_cpm4_get_device_attributes(dev_hndl, &dev_cap); - - if (dev_cap.st_en || dev_cap.mm_cmpt_en) - qdma_write_csr_values(dev_hndl, - QDMA_CPM4_C2H_TIMER_CNT_1_ADDR, - index, count, glbl_tmr_cnt); - else { - qdma_log_error("%s: ST or MM cmpt not supported, err:%d\n", - __func__, - -QDMA_ERR_HWACC_FEATURE_NOT_SUPPORTED); - return -QDMA_ERR_HWACC_FEATURE_NOT_SUPPORTED; - } - - return QDMA_SUCCESS; -} - -/*****************************************************************************/ -/** - * qdma_cpm4_read_global_timer_count() - function to get the timer values - * - * @dev_hndl: device handle - * @index: Index from where the values needs to read - * @count: number of entries to be read - * @glbl_tmr_cnt: pointer to array to hold the values read - * - * (index + count) shall not be more than 16 - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -static int qdma_cpm4_read_global_timer_count(void *dev_hndl, uint8_t index, - uint8_t count, uint32_t *glbl_tmr_cnt) -{ - struct qdma_dev_attributes dev_cap; - - if (!dev_hndl || !glbl_tmr_cnt || !count) { - qdma_log_error("%s: dev_hndl=%p glbl_tmr_cnt=%p, err:%d\n", - __func__, dev_hndl, glbl_tmr_cnt, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - if ((index + count) > QDMA_NUM_C2H_TIMERS) { - qdma_log_error("%s: index=%u count=%u > %d, err:%d\n", - __func__, index, count, - QDMA_NUM_C2H_TIMERS, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - qdma_cpm4_get_device_attributes(dev_hndl, &dev_cap); - - if (dev_cap.st_en || dev_cap.mm_cmpt_en) - qdma_read_csr_values(dev_hndl, - QDMA_CPM4_C2H_TIMER_CNT_1_ADDR, index, - count, glbl_tmr_cnt); - else { - qdma_log_error("%s: ST or MM cmpt not supported, err:%d\n", - __func__, - -QDMA_ERR_HWACC_FEATURE_NOT_SUPPORTED); - return -QDMA_ERR_HWACC_FEATURE_NOT_SUPPORTED; - } - - return QDMA_SUCCESS; -} - -/*****************************************************************************/ -/** - * qdma_cpm4_write_global_counter_threshold() - function to set the counter - * threshold values - * - * @dev_hndl: device handle - * @index: Index from where the values needs to written - * @count: number of entries to be written - * @glbl_cnt_th: pointer to the array having the values to write - * - * (index + count) shall not be more than 16 - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -static int qdma_cpm4_write_global_counter_threshold(void *dev_hndl, - uint8_t index, - uint8_t count, const uint32_t *glbl_cnt_th) -{ - struct qdma_dev_attributes dev_cap; - - if (!dev_hndl || !glbl_cnt_th || !count) { - qdma_log_error("%s: dev_hndl=%p glbl_cnt_th=%p, err:%d\n", - __func__, dev_hndl, glbl_cnt_th, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - if ((index + count) > QDMA_NUM_C2H_COUNTERS) { - qdma_log_error("%s: index=%u count=%u > %d, err:%d\n", - __func__, index, count, - QDMA_NUM_C2H_BUFFER_SIZES, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - qdma_cpm4_get_device_attributes(dev_hndl, &dev_cap); - - if (dev_cap.st_en || dev_cap.mm_cmpt_en) - qdma_write_csr_values(dev_hndl, - QDMA_CPM4_C2H_CNT_TH_1_ADDR, index, - count, glbl_cnt_th); - else { - qdma_log_error("%s: ST or MM cmpt not supported, err:%d\n", - __func__, - -QDMA_ERR_HWACC_FEATURE_NOT_SUPPORTED); - return -QDMA_ERR_HWACC_FEATURE_NOT_SUPPORTED; - } - - return QDMA_SUCCESS; -} - -/*****************************************************************************/ -/** - * qdma_cpm4_read_global_counter_threshold() - get the counter - * threshold values - * - * @dev_hndl: device handle - * @index: Index from where the values needs to read - * @count: number of entries to be read - * @glbl_cnt_th: pointer to array to hold the values read - * - * (index + count) shall not be more than 16 - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -static int qdma_cpm4_read_global_counter_threshold(void *dev_hndl, - uint8_t index, - uint8_t count, uint32_t *glbl_cnt_th) -{ - struct qdma_dev_attributes dev_cap; - - if (!dev_hndl || !glbl_cnt_th || !count) { - qdma_log_error("%s: dev_hndl=%p glbl_cnt_th=%p, err:%d\n", - __func__, dev_hndl, glbl_cnt_th, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - if ((index + count) > QDMA_NUM_C2H_COUNTERS) { - qdma_log_error("%s: index=%u count=%u > %d, err:%d\n", - __func__, index, count, - QDMA_NUM_C2H_COUNTERS, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - qdma_cpm4_get_device_attributes(dev_hndl, &dev_cap); - - if (dev_cap.st_en || dev_cap.mm_cmpt_en) - qdma_read_csr_values(dev_hndl, - QDMA_CPM4_C2H_CNT_TH_1_ADDR, index, - count, glbl_cnt_th); - else { - qdma_log_error("%s: ST or MM cmpt not supported, err:%d\n", - __func__, -QDMA_ERR_HWACC_FEATURE_NOT_SUPPORTED); - return -QDMA_ERR_HWACC_FEATURE_NOT_SUPPORTED; - } - - return QDMA_SUCCESS; -} - -/*****************************************************************************/ -/** - * qdma_cpm4_write_global_buffer_sizes() - function to set the buffer sizes - * - * @dev_hndl: device handle - * @index: Index from where the values needs to written - * @count: number of entries to be written - * @glbl_buf_sz: pointer to the array having the values to write - * - * (index + count) shall not be more than 16 - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -static int qdma_cpm4_write_global_buffer_sizes(void *dev_hndl, - uint8_t index, - uint8_t count, const uint32_t *glbl_buf_sz) -{ - struct qdma_dev_attributes dev_cap; - - if (!dev_hndl || !glbl_buf_sz || !count) { - qdma_log_error("%s: dev_hndl=%p glbl_buf_sz=%p, err:%d\n", - __func__, dev_hndl, glbl_buf_sz, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - if ((index + count) > QDMA_NUM_C2H_BUFFER_SIZES) { - qdma_log_error("%s: index=%u count=%u > %d, err:%d\n", - __func__, index, count, - QDMA_NUM_C2H_BUFFER_SIZES, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - qdma_cpm4_get_device_attributes(dev_hndl, &dev_cap); - - if (dev_cap.st_en) - qdma_write_csr_values(dev_hndl, - QDMA_CPM4_C2H_BUF_SZ_0_ADDR, index, - count, glbl_buf_sz); - else { - qdma_log_error("%s: ST not supported, err:%d\n", - __func__, - -QDMA_ERR_HWACC_FEATURE_NOT_SUPPORTED); - return -QDMA_ERR_HWACC_FEATURE_NOT_SUPPORTED; - } - - return QDMA_SUCCESS; -} - -/*****************************************************************************/ -/** - * qdma_cpm4_read_global_buffer_sizes() - function to get the buffer sizes - * - * @dev_hndl: device handle - * @index: Index from where the values needs to read - * @count: number of entries to be read - * @glbl_buf_sz: pointer to array to hold the values read - * - * (index + count) shall not be more than 16 - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -static int qdma_cpm4_read_global_buffer_sizes(void *dev_hndl, uint8_t index, - uint8_t count, uint32_t *glbl_buf_sz) -{ - struct qdma_dev_attributes dev_cap; - - if (!dev_hndl || !glbl_buf_sz || !count) { - qdma_log_error("%s: dev_hndl=%p glbl_buf_sz=%p, err:%d\n", - __func__, dev_hndl, glbl_buf_sz, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - if ((index + count) > QDMA_NUM_C2H_BUFFER_SIZES) { - qdma_log_error("%s: index=%u count=%u > %d, err:%d\n", - __func__, index, count, - QDMA_NUM_C2H_BUFFER_SIZES, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - qdma_cpm4_get_device_attributes(dev_hndl, &dev_cap); - - if (dev_cap.st_en) - qdma_read_csr_values(dev_hndl, - QDMA_CPM4_C2H_BUF_SZ_0_ADDR, index, - count, glbl_buf_sz); - else { - qdma_log_error("%s: ST is not supported, err:%d\n", - __func__, - -QDMA_ERR_HWACC_FEATURE_NOT_SUPPORTED); - return -QDMA_ERR_HWACC_FEATURE_NOT_SUPPORTED; - } - - return QDMA_SUCCESS; -} - -/*****************************************************************************/ -/** - * qdma_cpm4_global_csr_conf() - function to configure global csr - * - * @dev_hndl: device handle - * @index: Index from where the values needs to read - * @count: number of entries to be read - * @csr_val: uint32_t pointer to csr value - * @csr_type: Type of the CSR (qdma_global_csr_type enum) to configure - * @access_type HW access type (qdma_hw_access_type enum) value - * QDMA_HW_ACCESS_CLEAR - Not supported - * QDMA_HW_ACCESS_INVALIDATE - Not supported - * - * (index + count) shall not be more than 16 - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -int qdma_cpm4_global_csr_conf(void *dev_hndl, uint8_t index, uint8_t count, - uint32_t *csr_val, - enum qdma_global_csr_type csr_type, - enum qdma_hw_access_type access_type) -{ - int rv = QDMA_SUCCESS; - - switch (csr_type) { - case QDMA_CSR_RING_SZ: - switch (access_type) { - case QDMA_HW_ACCESS_READ: - rv = qdma_cpm4_read_global_ring_sizes( - dev_hndl, - index, - count, - csr_val); - break; - case QDMA_HW_ACCESS_WRITE: - rv = qdma_cpm4_write_global_ring_sizes( - dev_hndl, - index, - count, - csr_val); - break; - default: - qdma_log_error("%s: access_type(%d) invalid, err:%d\n", - __func__, - access_type, - -QDMA_ERR_INV_PARAM); - rv = -QDMA_ERR_INV_PARAM; - break; - } - break; - case QDMA_CSR_TIMER_CNT: - switch (access_type) { - case QDMA_HW_ACCESS_READ: - rv = qdma_cpm4_read_global_timer_count( - dev_hndl, - index, - count, - csr_val); - break; - case QDMA_HW_ACCESS_WRITE: - rv = qdma_cpm4_write_global_timer_count( - dev_hndl, - index, - count, - csr_val); - break; - default: - qdma_log_error("%s: access_type(%d) invalid, err:%d\n", - __func__, - access_type, - -QDMA_ERR_INV_PARAM); - rv = -QDMA_ERR_INV_PARAM; - break; - } - break; - case QDMA_CSR_CNT_TH: - switch (access_type) { - case QDMA_HW_ACCESS_READ: - rv = - qdma_cpm4_read_global_counter_threshold( - dev_hndl, - index, - count, - csr_val); - break; - case QDMA_HW_ACCESS_WRITE: - rv = - qdma_cpm4_write_global_counter_threshold( - dev_hndl, - index, - count, - csr_val); - break; - default: - qdma_log_error("%s: access_type(%d) invalid, err:%d\n", - __func__, - access_type, - -QDMA_ERR_INV_PARAM); - rv = -QDMA_ERR_INV_PARAM; - break; - } - break; - case QDMA_CSR_BUF_SZ: - switch (access_type) { - case QDMA_HW_ACCESS_READ: - rv = - qdma_cpm4_read_global_buffer_sizes(dev_hndl, - index, - count, - csr_val); - break; - case QDMA_HW_ACCESS_WRITE: - rv = - qdma_cpm4_write_global_buffer_sizes(dev_hndl, - index, - count, - csr_val); - break; - default: - qdma_log_error("%s: access_type(%d) invalid, err:%d\n", - __func__, - access_type, - -QDMA_ERR_INV_PARAM); - rv = -QDMA_ERR_INV_PARAM; - break; - } - break; - default: - qdma_log_error("%s: csr_type(%d) invalid, err:%d\n", - __func__, - csr_type, - -QDMA_ERR_INV_PARAM); - rv = -QDMA_ERR_INV_PARAM; - break; - } - - return rv; -} - -/*****************************************************************************/ -/** - * qdma_cpm4_global_writeback_interval_write() - function to set the - * writeback interval - * - * @dev_hndl device handle - * @wb_int: Writeback Interval - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -static int qdma_cpm4_global_writeback_interval_write(void *dev_hndl, - enum qdma_wrb_interval wb_int) -{ - uint32_t reg_val; - struct qdma_dev_attributes dev_cap; - - if (!dev_hndl) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", __func__, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - if (wb_int >= QDMA_NUM_WRB_INTERVALS) { - qdma_log_error("%s: wb_int=%d is invalid, err:%d\n", - __func__, wb_int, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - qdma_cpm4_get_device_attributes(dev_hndl, &dev_cap); - - if (dev_cap.st_en || dev_cap.mm_cmpt_en) { - reg_val = qdma_reg_read(dev_hndl, - QDMA_CPM4_GLBL_DSC_CFG_ADDR); - reg_val |= FIELD_SET(GLBL_DSC_CFG_WB_ACC_INT_MASK, wb_int); - - qdma_reg_write(dev_hndl, - QDMA_CPM4_GLBL_DSC_CFG_ADDR, reg_val); - } else { - qdma_log_error("%s: ST or MM cmpt not supported, err:%d\n", - __func__, -QDMA_ERR_HWACC_FEATURE_NOT_SUPPORTED); - return -QDMA_ERR_HWACC_FEATURE_NOT_SUPPORTED; - } - - return QDMA_SUCCESS; -} - -/*****************************************************************************/ -/** - * qdma_cpm4_global_writeback_interval_read() - function to get the - * writeback interval - * - * @dev_hndl: device handle - * @wb_int: pointer to the data to hold Writeback Interval - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -static int qdma_cpm4_global_writeback_interval_read(void *dev_hndl, - enum qdma_wrb_interval *wb_int) -{ - uint32_t reg_val; - struct qdma_dev_attributes dev_cap; - - if (!dev_hndl) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", __func__, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - if (!wb_int) { - qdma_log_error("%s: wb_int is NULL, err:%d\n", __func__, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - qdma_cpm4_get_device_attributes(dev_hndl, &dev_cap); - - if (dev_cap.st_en || dev_cap.mm_cmpt_en) { - reg_val = qdma_reg_read(dev_hndl, - QDMA_CPM4_GLBL_DSC_CFG_ADDR); - *wb_int = (enum qdma_wrb_interval)FIELD_GET( - GLBL_DSC_CFG_WB_ACC_INT_MASK, reg_val); - } else { - qdma_log_error("%s: ST or MM cmpt not supported, err:%d\n", - __func__, -QDMA_ERR_HWACC_FEATURE_NOT_SUPPORTED); - return -QDMA_ERR_HWACC_FEATURE_NOT_SUPPORTED; - } - - return QDMA_SUCCESS; -} - -/*****************************************************************************/ -/** - * qdma_cpm4_global_writeback_interval_conf() - function to configure - * the writeback interval - * - * @dev_hndl: device handle - * @wb_int: pointer to the data to hold Writeback Interval - * @access_type HW access type (qdma_hw_access_type enum) value - * QDMA_HW_ACCESS_CLEAR - Not supported - * QDMA_HW_ACCESS_INVALIDATE - Not supported - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -int qdma_cpm4_global_writeback_interval_conf(void *dev_hndl, - enum qdma_wrb_interval *wb_int, - enum qdma_hw_access_type access_type) -{ - int rv = QDMA_SUCCESS; - - switch (access_type) { - case QDMA_HW_ACCESS_READ: - rv = - qdma_cpm4_global_writeback_interval_read(dev_hndl, wb_int); - break; - case QDMA_HW_ACCESS_WRITE: - rv = - qdma_cpm4_global_writeback_interval_write(dev_hndl, - *wb_int); - break; - case QDMA_HW_ACCESS_CLEAR: - case QDMA_HW_ACCESS_INVALIDATE: - default: - qdma_log_error("%s: access_type(%d) invalid, err:%d\n", - __func__, - access_type, - -QDMA_ERR_INV_PARAM); - rv = -QDMA_ERR_INV_PARAM; - break; - } - - return rv; -} - - -/*****************************************************************************/ -/** - * qdma_cpm4_mm_channel_conf() - Function to enable/disable the MM channel - * - * @dev_hndl: device handle - * @channel: MM channel number - * @is_c2h: Queue direction. Set 1 for C2H and 0 for H2C - * @enable: Enable or disable MM channel - * - * Presently, we have only 1 MM channel - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -int qdma_cpm4_mm_channel_conf(void *dev_hndl, uint8_t channel, - uint8_t is_c2h, - uint8_t enable) -{ - uint32_t reg_addr = (is_c2h) ? QDMA_CPM4_C2H_CHANNEL_CTL_ADDR : - QDMA_CPM4_H2C_CHANNEL_CTL_ADDR; - struct qdma_dev_attributes dev_cap; - - if (!dev_hndl) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - qdma_cpm4_get_device_attributes(dev_hndl, &dev_cap); - - if (dev_cap.mm_en) { - qdma_reg_write(dev_hndl, - reg_addr + (channel * QDMA_MM_CONTROL_STEP), - enable); - } - - return QDMA_SUCCESS; -} - -int qdma_cpm4_dump_reg_info(void *dev_hndl, uint32_t reg_addr, - uint32_t num_regs, char *buf, uint32_t buflen) -{ - uint32_t total_num_regs = qdma_cpm4_config_num_regs_get(); - struct xreg_info *config_regs = qdma_cpm4_config_regs_get(); - const char *bitfield_name; - uint32_t i = 0, num_regs_idx = 0, k = 0, j = 0, - bitfield = 0, lsb = 0, msb = 31; - int rv = 0; - uint32_t reg_val; - uint32_t data_len = 0; - - if (!dev_hndl) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - for (i = 0; i < total_num_regs; i++) { - if (reg_addr == config_regs[i].addr) { - j = i; - break; - } - } - - if (i == total_num_regs) { - qdma_log_error("%s: Register not found err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - if (buf) - QDMA_SNPRINTF_S(buf, buflen, - DEBGFS_LINE_SZ, - "Register not found 0x%x\n", reg_addr); - return -QDMA_ERR_INV_PARAM; - } - - num_regs_idx = (j + num_regs < total_num_regs) ? - (j + num_regs) : total_num_regs; - - for (; j < num_regs_idx ; j++) { - reg_val = qdma_reg_read(dev_hndl, - config_regs[j].addr); - - if (buf) { - rv = QDMA_SNPRINTF_S(buf, buflen, - DEBGFS_LINE_SZ, - "\n%-40s 0x%-7x %-#10x %-10d\n", - config_regs[j].name, - config_regs[j].addr, - reg_val, reg_val); - if ((rv < 0) || (rv > DEBGFS_LINE_SZ)) { - qdma_log_error( - "%s: Insufficient buffer, err:%d\n", - __func__, -QDMA_ERR_NO_MEM); - return -QDMA_ERR_NO_MEM; - } - buf += rv; - data_len += rv; - buflen -= rv; - } else - qdma_log_info("%-40s 0x%-7x %-#10x %-10d\n", - config_regs[j].name, - config_regs[j].addr, - reg_val, reg_val); - - - for (k = 0; - k < config_regs[j].num_bitfields; k++) { - - bitfield = - config_regs[j].bitfields[k].field_mask; - bitfield_name = - config_regs[i].bitfields[k].field_name; - lsb = 0; - msb = 31; - - while (!(BIT(lsb) & bitfield)) - lsb++; - - while (!(BIT(msb) & bitfield)) - msb--; - - if (msb != lsb) { - if (buf) { - rv = QDMA_SNPRINTF_S(buf, buflen, - DEBGFS_LINE_SZ, - "%-40s [%2u,%2u] %#-10x\n", - bitfield_name, - msb, lsb, - (reg_val & bitfield) >> - lsb); - if ((rv < 0) || (rv > DEBGFS_LINE_SZ)) { - qdma_log_error( - "%s: Insufficient buffer, err:%d\n", - __func__, - -QDMA_ERR_NO_MEM); - return -QDMA_ERR_NO_MEM; - } - buf += rv; - data_len += rv; - buflen -= rv; - } else - qdma_log_info( - "%-40s [%2u,%2u] %#-10x\n", - bitfield_name, - msb, lsb, - (reg_val & bitfield) >> lsb); - - - } else { - if (buf) { - rv = QDMA_SNPRINTF_S(buf, buflen, - DEBGFS_LINE_SZ, - "%-40s [%5u] %#-10x\n", - bitfield_name, - lsb, - (reg_val & bitfield) >> - lsb); - if ((rv < 0) || (rv > DEBGFS_LINE_SZ)) { - qdma_log_error( - "%s: Insufficient buffer, err:%d\n", - __func__, - -QDMA_ERR_NO_MEM); - return -QDMA_ERR_NO_MEM; - } - buf += rv; - data_len += rv; - buflen -= rv; - } else - qdma_log_info( - "%-40s [%5u] %#-10x\n", - bitfield_name, - lsb, - (reg_val & bitfield) >> lsb); - - } - } - } - - return data_len; - -} diff --git a/QDMA/DPDK/drivers/net/qdma/qdma_access/qdma_cpm4_access/qdma_cpm4_access.h b/QDMA/DPDK/drivers/net/qdma/qdma_access/qdma_cpm4_access/qdma_cpm4_access.h deleted file mode 100755 index a28f63367..000000000 --- a/QDMA/DPDK/drivers/net/qdma/qdma_access/qdma_cpm4_access/qdma_cpm4_access.h +++ /dev/null @@ -1,300 +0,0 @@ -/* - * Copyright (c) 2019-2022, Xilinx, Inc. All rights reserved. - * Copyright (c) 2022, Advanced Micro Devices, Inc. All rights reserved. - * - * BSD LICENSE - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * * Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#ifndef __QDMA_CPM4_ACCESS_H_ -#define __QDMA_CPM4_ACCESS_H_ - -#ifdef __cplusplus -extern "C" { -#endif - -#include "qdma_platform.h" - -/** - * enum qdma_error_idx - qdma errors - */ -enum qdma_cpm4_error_idx { - /* Descriptor errors */ - QDMA_CPM4_DSC_ERR_POISON, - QDMA_CPM4_DSC_ERR_UR_CA, - QDMA_CPM4_DSC_ERR_PARAM, - QDMA_CPM4_DSC_ERR_ADDR, - QDMA_CPM4_DSC_ERR_TAG, - QDMA_CPM4_DSC_ERR_FLR, - QDMA_CPM4_DSC_ERR_TIMEOUT, - QDMA_CPM4_DSC_ERR_DAT_POISON, - QDMA_CPM4_DSC_ERR_FLR_CANCEL, - QDMA_CPM4_DSC_ERR_DMA, - QDMA_CPM4_DSC_ERR_DSC, - QDMA_CPM4_DSC_ERR_RQ_CANCEL, - QDMA_CPM4_DSC_ERR_DBE, - QDMA_CPM4_DSC_ERR_SBE, - QDMA_CPM4_DSC_ERR_ALL, - - /* TRQ Errors */ - QDMA_CPM4_TRQ_ERR_UNMAPPED, - QDMA_CPM4_TRQ_ERR_QID_RANGE, - QDMA_CPM4_TRQ_ERR_VF_ACCESS_ERR, - QDMA_CPM4_TRQ_ERR_TCP_TIMEOUT, - QDMA_CPM4_TRQ_ERR_ALL, - - /* C2H Errors */ - QDMA_CPM4_ST_C2H_ERR_MTY_MISMATCH, - QDMA_CPM4_ST_C2H_ERR_LEN_MISMATCH, - QDMA_CPM4_ST_C2H_ERR_QID_MISMATCH, - QDMA_CPM4_ST_C2H_ERR_DESC_RSP_ERR, - QDMA_CPM4_ST_C2H_ERR_ENG_WPL_DATA_PAR_ERR, - QDMA_CPM4_ST_C2H_ERR_MSI_INT_FAIL, - QDMA_CPM4_ST_C2H_ERR_ERR_DESC_CNT, - QDMA_CPM4_ST_C2H_ERR_PORTID_CTXT_MISMATCH, - QDMA_CPM4_ST_C2H_ERR_PORTID_BYP_IN_MISMATCH, - QDMA_CPM4_ST_C2H_ERR_WRB_INV_Q_ERR, - QDMA_CPM4_ST_C2H_ERR_WRB_QFULL_ERR, - QDMA_CPM4_ST_C2H_ERR_WRB_CIDX_ERR, - QDMA_CPM4_ST_C2H_ERR_WRB_PRTY_ERR, - QDMA_CPM4_ST_C2H_ERR_ALL, - - /* Fatal Errors */ - QDMA_CPM4_ST_FATAL_ERR_MTY_MISMATCH, - QDMA_CPM4_ST_FATAL_ERR_LEN_MISMATCH, - QDMA_CPM4_ST_FATAL_ERR_QID_MISMATCH, - QDMA_CPM4_ST_FATAL_ERR_TIMER_FIFO_RAM_RDBE, - QDMA_CPM4_ST_FATAL_ERR_PFCH_II_RAM_RDBE, - QDMA_CPM4_ST_FATAL_ERR_WRB_CTXT_RAM_RDBE, - QDMA_CPM4_ST_FATAL_ERR_PFCH_CTXT_RAM_RDBE, - QDMA_CPM4_ST_FATAL_ERR_DESC_REQ_FIFO_RAM_RDBE, - QDMA_CPM4_ST_FATAL_ERR_INT_CTXT_RAM_RDBE, - QDMA_CPM4_ST_FATAL_ERR_INT_QID2VEC_RAM_RDBE, - QDMA_CPM4_ST_FATAL_ERR_WRB_COAL_DATA_RAM_RDBE, - QDMA_CPM4_ST_FATAL_ERR_TUSER_FIFO_RAM_RDBE, - QDMA_CPM4_ST_FATAL_ERR_QID_FIFO_RAM_RDBE, - QDMA_CPM4_ST_FATAL_ERR_PAYLOAD_FIFO_RAM_RDBE, - QDMA_CPM4_ST_FATAL_ERR_WPL_DATA_PAR_ERR, - QDMA_CPM4_ST_FATAL_ERR_ALL, - - /* H2C Errors */ - QDMA_CPM4_ST_H2C_ERR_ZERO_LEN_DESC_ERR, - QDMA_CPM4_ST_H2C_ERR_SDI_MRKR_REQ_MOP_ERR, - QDMA_CPM4_ST_H2C_ERR_NO_DMA_DSC, - QDMA_CPM4_ST_H2C_ERR_DBE, - QDMA_CPM4_ST_H2C_ERR_SBE, - QDMA_CPM4_ST_H2C_ERR_ALL, - - /* Single bit errors */ - QDMA_CPM4_SBE_ERR_MI_H2C0_DAT, - QDMA_CPM4_SBE_ERR_MI_C2H0_DAT, - QDMA_CPM4_SBE_ERR_H2C_RD_BRG_DAT, - QDMA_CPM4_SBE_ERR_H2C_WR_BRG_DAT, - QDMA_CPM4_SBE_ERR_C2H_RD_BRG_DAT, - QDMA_CPM4_SBE_ERR_C2H_WR_BRG_DAT, - QDMA_CPM4_SBE_ERR_FUNC_MAP, - QDMA_CPM4_SBE_ERR_DSC_HW_CTXT, - QDMA_CPM4_SBE_ERR_DSC_CRD_RCV, - QDMA_CPM4_SBE_ERR_DSC_SW_CTXT, - QDMA_CPM4_SBE_ERR_DSC_CPLI, - QDMA_CPM4_SBE_ERR_DSC_CPLD, - QDMA_CPM4_SBE_ERR_PASID_CTXT_RAM, - QDMA_CPM4_SBE_ERR_TIMER_FIFO_RAM, - QDMA_CPM4_SBE_ERR_PAYLOAD_FIFO_RAM, - QDMA_CPM4_SBE_ERR_QID_FIFO_RAM, - QDMA_CPM4_SBE_ERR_TUSER_FIFO_RAM, - QDMA_CPM4_SBE_ERR_WRB_COAL_DATA_RAM, - QDMA_CPM4_SBE_ERR_INT_QID2VEC_RAM, - QDMA_CPM4_SBE_ERR_INT_CTXT_RAM, - QDMA_CPM4_SBE_ERR_DESC_REQ_FIFO_RAM, - QDMA_CPM4_SBE_ERR_PFCH_CTXT_RAM, - QDMA_CPM4_SBE_ERR_WRB_CTXT_RAM, - QDMA_CPM4_SBE_ERR_PFCH_LL_RAM, - QDMA_CPM4_SBE_ERR_ALL, - - /* Double bit Errors */ - QDMA_CPM4_DBE_ERR_MI_H2C0_DAT, - QDMA_CPM4_DBE_ERR_MI_C2H0_DAT, - QDMA_CPM4_DBE_ERR_H2C_RD_BRG_DAT, - QDMA_CPM4_DBE_ERR_H2C_WR_BRG_DAT, - QDMA_CPM4_DBE_ERR_C2H_RD_BRG_DAT, - QDMA_CPM4_DBE_ERR_C2H_WR_BRG_DAT, - QDMA_CPM4_DBE_ERR_FUNC_MAP, - QDMA_CPM4_DBE_ERR_DSC_HW_CTXT, - QDMA_CPM4_DBE_ERR_DSC_CRD_RCV, - QDMA_CPM4_DBE_ERR_DSC_SW_CTXT, - QDMA_CPM4_DBE_ERR_DSC_CPLI, - QDMA_CPM4_DBE_ERR_DSC_CPLD, - QDMA_CPM4_DBE_ERR_PASID_CTXT_RAM, - QDMA_CPM4_DBE_ERR_TIMER_FIFO_RAM, - QDMA_CPM4_DBE_ERR_PAYLOAD_FIFO_RAM, - QDMA_CPM4_DBE_ERR_QID_FIFO_RAM, - QDMA_CPM4_DBE_ERR_WRB_COAL_DATA_RAM, - QDMA_CPM4_DBE_ERR_INT_QID2VEC_RAM, - QDMA_CPM4_DBE_ERR_INT_CTXT_RAM, - QDMA_CPM4_DBE_ERR_DESC_REQ_FIFO_RAM, - QDMA_CPM4_DBE_ERR_PFCH_CTXT_RAM, - QDMA_CPM4_DBE_ERR_WRB_CTXT_RAM, - QDMA_CPM4_DBE_ERR_PFCH_LL_RAM, - QDMA_CPM4_DBE_ERR_ALL, - - QDMA_CPM4_ERRS_ALL -}; - -struct qdma_cpm4_hw_err_info { - enum qdma_cpm4_error_idx idx; - const char *err_name; - uint32_t mask_reg_addr; - uint32_t stat_reg_addr; - uint32_t leaf_err_mask; - uint32_t global_err_mask; - void (*qdma_cpm4_hw_err_process)(void *dev_hndl); -}; - - -int qdma_cpm4_init_ctxt_memory(void *dev_hndl); - -#ifdef TANDEM_BOOT_SUPPORTED -int qdma_cpm4_init_st_ctxt(void *dev_hndl); -#endif - -int qdma_cpm4_qid2vec_conf(void *dev_hndl, uint8_t c2h, uint16_t hw_qid, - struct qdma_qid2vec *ctxt, - enum qdma_hw_access_type access_type); - -int qdma_cpm4_fmap_conf(void *dev_hndl, uint16_t func_id, - struct qdma_fmap_cfg *config, - enum qdma_hw_access_type access_type); - -int qdma_cpm4_sw_ctx_conf(void *dev_hndl, uint8_t c2h, uint16_t hw_qid, - struct qdma_descq_sw_ctxt *ctxt, - enum qdma_hw_access_type access_type); - -int qdma_cpm4_pfetch_ctx_conf(void *dev_hndl, uint16_t hw_qid, - struct qdma_descq_prefetch_ctxt *ctxt, - enum qdma_hw_access_type access_type); - -int qdma_cpm4_cmpt_ctx_conf(void *dev_hndl, uint16_t hw_qid, - struct qdma_descq_cmpt_ctxt *ctxt, - enum qdma_hw_access_type access_type); - -int qdma_cpm4_hw_ctx_conf(void *dev_hndl, uint8_t c2h, uint16_t hw_qid, - struct qdma_descq_hw_ctxt *ctxt, - enum qdma_hw_access_type access_type); - -int qdma_cpm4_credit_ctx_conf(void *dev_hndl, uint8_t c2h, uint16_t hw_qid, - struct qdma_descq_credit_ctxt *ctxt, - enum qdma_hw_access_type access_type); - -int qdma_cpm4_indirect_intr_ctx_conf(void *dev_hndl, uint16_t ring_index, - struct qdma_indirect_intr_ctxt *ctxt, - enum qdma_hw_access_type access_type); - -int qdma_cpm4_set_default_global_csr(void *dev_hndl); - -int qdma_cpm4_queue_pidx_update(void *dev_hndl, uint8_t is_vf, uint16_t qid, - uint8_t is_c2h, const struct qdma_q_pidx_reg_info *reg_info); - -int qdma_cpm4_queue_cmpt_cidx_update(void *dev_hndl, uint8_t is_vf, - uint16_t qid, const struct qdma_q_cmpt_cidx_reg_info *reg_info); - -int qdma_cpm4_queue_intr_cidx_update(void *dev_hndl, uint8_t is_vf, - uint16_t qid, const struct qdma_intr_cidx_reg_info *reg_info); - -int qdma_cmp_get_user_bar(void *dev_hndl, uint8_t is_vf, - uint16_t func_id, uint8_t *user_bar); - -int qdma_cpm4_get_device_attributes(void *dev_hndl, - struct qdma_dev_attributes *dev_info); - -uint32_t qdma_cpm4_reg_dump_buf_len(void); - -int qdma_cpm4_context_buf_len(uint8_t st, - enum qdma_dev_q_type q_type, uint32_t *req_buflen); - -int qdma_cpm4_dump_config_regs(void *dev_hndl, uint8_t is_vf, - char *buf, uint32_t buflen); - -int qdma_cpm4_hw_error_process(void *dev_hndl); -const char *qdma_cpm4_hw_get_error_name(uint32_t err_idx); -int qdma_cpm4_hw_error_enable(void *dev_hndl, uint32_t err_idx); - -int qdma_cpm4_dump_queue_context(void *dev_hndl, - uint8_t st, - enum qdma_dev_q_type q_type, - struct qdma_descq_context *ctxt_data, - char *buf, uint32_t buflen); - -int qdma_cpm4_dump_intr_context(void *dev_hndl, - struct qdma_indirect_intr_ctxt *intr_ctx, - int ring_index, - char *buf, uint32_t buflen); - -int qdma_cpm4_read_dump_queue_context(void *dev_hndl, - uint16_t func_id, - uint16_t qid_hw, - uint8_t st, - enum qdma_dev_q_type q_type, - char *buf, uint32_t buflen); - -int qdma_cpm4_dump_config_reg_list(void *dev_hndl, - uint32_t total_regs, - struct qdma_reg_data *reg_list, - char *buf, uint32_t buflen); - -int qdma_cpm4_read_reg_list(void *dev_hndl, uint8_t is_vf, - uint16_t reg_rd_slot, - uint16_t *total_regs, - struct qdma_reg_data *reg_list); - -int qdma_cpm4_global_csr_conf(void *dev_hndl, uint8_t index, - uint8_t count, - uint32_t *csr_val, - enum qdma_global_csr_type csr_type, - enum qdma_hw_access_type access_type); - -int qdma_cpm4_global_writeback_interval_conf(void *dev_hndl, - enum qdma_wrb_interval *wb_int, - enum qdma_hw_access_type access_type); - -int qdma_cpm4_mm_channel_conf(void *dev_hndl, uint8_t channel, - uint8_t is_c2h, - uint8_t enable); - -int qdma_cpm4_dump_reg_info(void *dev_hndl, uint32_t reg_addr, - uint32_t num_regs, char *buf, uint32_t buflen); - -uint32_t qdma_cpm4_get_config_num_regs(void); - -struct xreg_info *qdma_cpm4_get_config_regs(void); - -#ifdef __cplusplus -} -#endif - -#endif /* __QDMA_CPM4_ACCESS_H_ */ diff --git a/QDMA/DPDK/drivers/net/qdma/qdma_access/qdma_cpm4_access/qdma_cpm4_reg.h b/QDMA/DPDK/drivers/net/qdma/qdma_access/qdma_cpm4_access/qdma_cpm4_reg.h deleted file mode 100755 index 00bba141c..000000000 --- a/QDMA/DPDK/drivers/net/qdma/qdma_access/qdma_cpm4_access/qdma_cpm4_reg.h +++ /dev/null @@ -1,2062 +0,0 @@ -/* - * Copyright (c) 2019-2022, Xilinx, Inc. All rights reserved. - * Copyright (c) 2022, Advanced Micro Devices, Inc. All rights reserved. - * - * BSD LICENSE - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * * Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#ifndef __QDMA_CPM4_REG_H -#define __QDMA_CPM4_REG_H - - -#ifdef __cplusplus -extern "C" { -#endif - -#include "qdma_platform.h" - -#ifdef CHAR_BIT -#undef CHAR_BIT -#endif -#define CHAR_BIT 8 - -#ifdef BIT -#undef BIT -#endif -#define BIT(n) (1u << (n)) - -#ifdef BITS_PER_BYTE -#undef BITS_PER_BYTE -#endif -#define BITS_PER_BYTE CHAR_BIT - -#ifdef BITS_PER_LONG -#undef BITS_PER_LONG -#endif -#define BITS_PER_LONG (sizeof(uint32_t) * BITS_PER_BYTE) - -#ifdef BITS_PER_LONG_LONG -#undef BITS_PER_LONG_LONG -#endif -#define BITS_PER_LONG_LONG (sizeof(uint64_t) * BITS_PER_BYTE) - -#ifdef GENMASK -#undef GENMASK -#endif -#define GENMASK(h, l) \ - ((0xFFFFFFFF << (l)) & (0xFFFFFFFF >> (BITS_PER_LONG - 1 - (h)))) - -#ifdef GENMASK_ULL -#undef GENMASK_ULL -#endif -#define GENMASK_ULL(h, l) \ - ((0xFFFFFFFFFFFFFFFF << (l)) & \ - (0xFFFFFFFFFFFFFFFF >> (BITS_PER_LONG_LONG - 1 - (h)))) - -#define DEBGFS_LINE_SZ (81) - -#ifdef ARRAY_SIZE -#undef ARRAY_SIZE -#endif -#define ARRAY_SIZE(arr) (sizeof(arr) / \ - sizeof(arr[0])) - - -uint32_t qdma_cpm4_config_num_regs_get(void); -struct xreg_info *qdma_cpm4_config_regs_get(void); -#define QDMA_CPM4_CFG_BLK_IDENTIFIER_ADDR 0x00 -#define CFG_BLK_IDENTIFIER_MASK GENMASK(31, 20) -#define CFG_BLK_IDENTIFIER_1_MASK GENMASK(19, 16) -#define CFG_BLK_IDENTIFIER_RSVD_1_MASK GENMASK(15, 8) -#define CFG_BLK_IDENTIFIER_VERSION_MASK GENMASK(7, 0) -#define QDMA_CPM4_CFG_BLK_BUSDEV_ADDR 0x04 -#define CFG_BLK_BUSDEV_BDF_MASK GENMASK(15, 0) -#define QDMA_CPM4_CFG_BLK_PCIE_MAX_PLD_SIZE_ADDR 0x08 -#define CFG_BLK_PCIE_MAX_PLD_SIZE_MASK GENMASK(2, 0) -#define QDMA_CPM4_CFG_BLK_PCIE_MAX_READ_REQ_SIZE_ADDR 0x0C -#define CFG_BLK_PCIE_MAX_READ_REQ_SIZE_MASK GENMASK(2, 0) -#define QDMA_CPM4_CFG_BLK_SYSTEM_ID_ADDR 0x10 -#define CFG_BLK_SYSTEM_ID_MASK GENMASK(15, 0) -#define QDMA_CPM4_CFG_BLK_MSI_ENABLE_ADDR 0x014 -#define CFG_BLK_MSI_ENABLE_3_MASK BIT(17) -#define CFG_BLK_MSI_ENABLE_MSIX3_MASK BIT(16) -#define CFG_BLK_MSI_ENABLE_2_MASK BIT(13) -#define CFG_BLK_MSI_ENABLE_MSIX2_MASK BIT(12) -#define CFG_BLK_MSI_ENABLE_1_MASK BIT(9) -#define CFG_BLK_MSI_ENABLE_MSIX1_MASK BIT(8) -#define CFG_BLK_MSI_ENABLE_0_MASK BIT(1) -#define CFG_BLK_MSI_ENABLE_MSIX0_MASK BIT(0) -#define QDMA_CPM4_CFG_PCIE_DATA_WIDTH_ADDR 0x18 -#define CFG_PCIE_DATA_WIDTH_DATAPATH_MASK GENMASK(2, 0) -#define QDMA_CPM4_CFG_PCIE_CTL_ADDR 0x1C -#define CFG_PCIE_CTL_RRQ_DISABLE_MASK BIT(1) -#define CFG_PCIE_CTL_RELAXED_ORDERING_MASK BIT(0) -#define QDMA_CPM4_CFG_AXI_USER_MAX_PLD_SIZE_ADDR 0x40 -#define CFG_AXI_USER_MAX_PLD_SIZE_ISSUED_MASK GENMASK(6, 4) -#define CFG_AXI_USER_MAX_PLD_SIZE_PROG_MASK GENMASK(2, 0) -#define QDMA_CPM4_CFG_AXI_USER_MAX_READ_REQ_SIZE_ADDR 0x44 -#define CFG_AXI_USER_MAX_READ_REQ_SIZE_USISSUED_MASK GENMASK(6, 4) -#define CFG_AXI_USER_MAX_READ_REQ_SIZE_USPROG_MASK GENMASK(2, 0) -#define QDMA_CPM4_CFG_BLK_MISC_CTL_ADDR 0x4C -#define CFG_BLK_MISC_CTL_NUM_TAG_MASK GENMASK(19, 8) -#define CFG_BLK_MISC_CTL_RQ_METERING_MULTIPLIER_MASK GENMASK(4, 0) -#define QDMA_CPM4_CFG_BLK_SCRATCH_0_ADDR 0x80 -#define CFG_BLK_SCRATCH_0_MASK GENMASK(31, 0) -#define QDMA_CPM4_CFG_BLK_SCRATCH_1_ADDR 0x84 -#define CFG_BLK_SCRATCH_1_MASK GENMASK(31, 0) -#define QDMA_CPM4_CFG_BLK_SCRATCH_2_ADDR 0x88 -#define CFG_BLK_SCRATCH_2_MASK GENMASK(31, 0) -#define QDMA_CPM4_CFG_BLK_SCRATCH_3_ADDR 0x8C -#define CFG_BLK_SCRATCH_3_MASK GENMASK(31, 0) -#define QDMA_CPM4_CFG_BLK_SCRATCH_4_ADDR 0x90 -#define CFG_BLK_SCRATCH_4_MASK GENMASK(31, 0) -#define QDMA_CPM4_CFG_BLK_SCRATCH_5_ADDR 0x94 -#define CFG_BLK_SCRATCH_5_MASK GENMASK(31, 0) -#define QDMA_CPM4_CFG_BLK_SCRATCH_6_ADDR 0x98 -#define CFG_BLK_SCRATCH_6_MASK GENMASK(31, 0) -#define QDMA_CPM4_CFG_BLK_SCRATCH_7_ADDR 0x9C -#define CFG_BLK_SCRATCH_7_MASK GENMASK(31, 0) -#define QDMA_CPM4_RAM_SBE_MSK_A_ADDR 0xF0 -#define RAM_SBE_MSK_A_MASK GENMASK(31, 0) -#define QDMA_CPM4_RAM_SBE_STS_A_ADDR 0xF4 -#define RAM_SBE_STS_A_RSVD_1_MASK BIT(31) -#define RAM_SBE_STS_A_PFCH_LL_RAM_MASK BIT(30) -#define RAM_SBE_STS_A_WRB_CTXT_RAM_MASK BIT(29) -#define RAM_SBE_STS_A_PFCH_CTXT_RAM_MASK BIT(28) -#define RAM_SBE_STS_A_DESC_REQ_FIFO_RAM_MASK BIT(27) -#define RAM_SBE_STS_A_INT_CTXT_RAM_MASK BIT(26) -#define RAM_SBE_STS_A_INT_QID2VEC_RAM_MASK BIT(25) -#define RAM_SBE_STS_A_WRB_COAL_DATA_RAM_MASK BIT(24) -#define RAM_SBE_STS_A_TUSER_FIFO_RAM_MASK BIT(23) -#define RAM_SBE_STS_A_QID_FIFO_RAM_MASK BIT(22) -#define RAM_SBE_STS_A_PLD_FIFO_RAM_MASK BIT(21) -#define RAM_SBE_STS_A_TIMER_FIFO_RAM_MASK BIT(20) -#define RAM_SBE_STS_A_PASID_CTXT_RAM_MASK BIT(19) -#define RAM_SBE_STS_A_DSC_CPLD_MASK BIT(18) -#define RAM_SBE_STS_A_DSC_CPLI_MASK BIT(17) -#define RAM_SBE_STS_A_DSC_SW_CTXT_MASK BIT(16) -#define RAM_SBE_STS_A_DSC_CRD_RCV_MASK BIT(15) -#define RAM_SBE_STS_A_DSC_HW_CTXT_MASK BIT(14) -#define RAM_SBE_STS_A_FUNC_MAP_MASK BIT(13) -#define RAM_SBE_STS_A_C2H_WR_BRG_DAT_MASK BIT(12) -#define RAM_SBE_STS_A_C2H_RD_BRG_DAT_MASK BIT(11) -#define RAM_SBE_STS_A_H2C_WR_BRG_DAT_MASK BIT(10) -#define RAM_SBE_STS_A_H2C_RD_BRG_DAT_MASK BIT(9) -#define RAM_SBE_STS_A_RSVD_2_MASK GENMASK(8, 5) -#define RAM_SBE_STS_A_MI_C2H0_DAT_MASK BIT(4) -#define RAM_SBE_STS_A_RSVD_3_MASK GENMASK(3, 1) -#define RAM_SBE_STS_A_MI_H2C0_DAT_MASK BIT(0) -#define QDMA_CPM4_RAM_DBE_MSK_A_ADDR 0xF8 -#define RAM_DBE_MSK_A_MASK GENMASK(31, 0) -#define QDMA_CPM4_RAM_DBE_STS_A_ADDR 0xFC -#define RAM_DBE_STS_A_RSVD_1_MASK BIT(31) -#define RAM_DBE_STS_A_PFCH_LL_RAM_MASK BIT(30) -#define RAM_DBE_STS_A_WRB_CTXT_RAM_MASK BIT(29) -#define RAM_DBE_STS_A_PFCH_CTXT_RAM_MASK BIT(28) -#define RAM_DBE_STS_A_DESC_REQ_FIFO_RAM_MASK BIT(27) -#define RAM_DBE_STS_A_INT_CTXT_RAM_MASK BIT(26) -#define RAM_DBE_STS_A_INT_QID2VEC_RAM_MASK BIT(25) -#define RAM_DBE_STS_A_WRB_COAL_DATA_RAM_MASK BIT(24) -#define RAM_DBE_STS_A_TUSER_FIFO_RAM_MASK BIT(23) -#define RAM_DBE_STS_A_QID_FIFO_RAM_MASK BIT(22) -#define RAM_DBE_STS_A_PLD_FIFO_RAM_MASK BIT(21) -#define RAM_DBE_STS_A_TIMER_FIFO_RAM_MASK BIT(20) -#define RAM_DBE_STS_A_PASID_CTXT_RAM_MASK BIT(19) -#define RAM_DBE_STS_A_DSC_CPLD_MASK BIT(18) -#define RAM_DBE_STS_A_DSC_CPLI_MASK BIT(17) -#define RAM_DBE_STS_A_DSC_SW_CTXT_MASK BIT(16) -#define RAM_DBE_STS_A_DSC_CRD_RCV_MASK BIT(15) -#define RAM_DBE_STS_A_DSC_HW_CTXT_MASK BIT(14) -#define RAM_DBE_STS_A_FUNC_MAP_MASK BIT(13) -#define RAM_DBE_STS_A_C2H_WR_BRG_DAT_MASK BIT(12) -#define RAM_DBE_STS_A_C2H_RD_BRG_DAT_MASK BIT(11) -#define RAM_DBE_STS_A_H2C_WR_BRG_DAT_MASK BIT(10) -#define RAM_DBE_STS_A_H2C_RD_BRG_DAT_MASK BIT(9) -#define RAM_DBE_STS_A_RSVD_2_MASK GENMASK(8, 5) -#define RAM_DBE_STS_A_MI_C2H0_DAT_MASK BIT(4) -#define RAM_DBE_STS_A_RSVD_3_MASK GENMASK(3, 1) -#define RAM_DBE_STS_A_MI_H2C0_DAT_MASK BIT(0) -#define QDMA_CPM4_GLBL2_IDENTIFIER_ADDR 0x100 -#define GLBL2_IDENTIFIER_MASK GENMASK(31, 8) -#define GLBL2_IDENTIFIER_VERSION_MASK GENMASK(7, 0) -#define QDMA_CPM4_GLBL2_PF_BARLITE_INT_ADDR 0x104 -#define GLBL2_PF_BARLITE_INT_PF3_BAR_MAP_MASK GENMASK(23, 18) -#define GLBL2_PF_BARLITE_INT_PF2_BAR_MAP_MASK GENMASK(17, 12) -#define GLBL2_PF_BARLITE_INT_PF1_BAR_MAP_MASK GENMASK(11, 6) -#define GLBL2_PF_BARLITE_INT_PF0_BAR_MAP_MASK GENMASK(5, 0) -#define QDMA_CPM4_GLBL2_PF_VF_BARLITE_INT_ADDR 0x108 -#define GLBL2_PF_VF_BARLITE_INT_PF3_MAP_MASK GENMASK(23, 18) -#define GLBL2_PF_VF_BARLITE_INT_PF2_MAP_MASK GENMASK(17, 12) -#define GLBL2_PF_VF_BARLITE_INT_PF1_MAP_MASK GENMASK(11, 6) -#define GLBL2_PF_VF_BARLITE_INT_PF0_MAP_MASK GENMASK(5, 0) -#define QDMA_CPM4_GLBL2_PF_BARLITE_EXT_ADDR 0x10C -#define GLBL2_PF_BARLITE_EXT_PF3_BAR_MAP_MASK GENMASK(23, 18) -#define GLBL2_PF_BARLITE_EXT_PF2_BAR_MAP_MASK GENMASK(17, 12) -#define GLBL2_PF_BARLITE_EXT_PF1_BAR_MAP_MASK GENMASK(11, 6) -#define GLBL2_PF_BARLITE_EXT_PF0_BAR_MAP_MASK GENMASK(5, 0) -#define QDMA_CPM4_GLBL2_PF_VF_BARLITE_EXT_ADDR 0x110 -#define GLBL2_PF_VF_BARLITE_EXT_PF3_MAP_MASK GENMASK(23, 18) -#define GLBL2_PF_VF_BARLITE_EXT_PF2_MAP_MASK GENMASK(17, 12) -#define GLBL2_PF_VF_BARLITE_EXT_PF1_MAP_MASK GENMASK(11, 6) -#define GLBL2_PF_VF_BARLITE_EXT_PF0_MAP_MASK GENMASK(5, 0) -#define QDMA_CPM4_GLBL2_CHANNEL_INST_ADDR 0x114 -#define GLBL2_CHANNEL_INST_RSVD_1_MASK GENMASK(31, 18) -#define GLBL2_CHANNEL_INST_C2H_ST_MASK BIT(17) -#define GLBL2_CHANNEL_INST_H2C_ST_MASK BIT(16) -#define GLBL2_CHANNEL_INST_RSVD_2_MASK GENMASK(15, 9) -#define GLBL2_CHANNEL_INST_C2H_ENG_MASK BIT(8) -#define GLBL2_CHANNEL_INST_RSVD_3_MASK GENMASK(7, 1) -#define GLBL2_CHANNEL_INST_H2C_ENG_MASK BIT(0) -#define QDMA_CPM4_GLBL2_CHANNEL_MDMA_ADDR 0x118 -#define GLBL2_CHANNEL_MDMA_RSVD_1_MASK GENMASK(31, 18) -#define GLBL2_CHANNEL_MDMA_C2H_ST_MASK BIT(17) -#define GLBL2_CHANNEL_MDMA_H2C_ST_MASK BIT(16) -#define GLBL2_CHANNEL_MDMA_RSVD_2_MASK GENMASK(15, 9) -#define GLBL2_CHANNEL_MDMA_C2H_ENG_MASK BIT(8) -#define GLBL2_CHANNEL_MDMA_RSVD_3_MASK GENMASK(7, 1) -#define GLBL2_CHANNEL_MDMA_H2C_ENG_MASK BIT(0) -#define QDMA_CPM4_GLBL2_CHANNEL_STRM_ADDR 0x11C -#define GLBL2_CHANNEL_STRM_RSVD_1_MASK GENMASK(31, 18) -#define GLBL2_CHANNEL_STRM_C2H_ST_MASK BIT(17) -#define GLBL2_CHANNEL_STRM_H2C_ST_MASK BIT(16) -#define GLBL2_CHANNEL_STRM_RSVD_2_MASK GENMASK(15, 9) -#define GLBL2_CHANNEL_STRM_C2H_ENG_MASK BIT(8) -#define GLBL2_CHANNEL_STRM_RSVD_3_MASK GENMASK(7, 1) -#define GLBL2_CHANNEL_STRM_H2C_ENG_MASK BIT(0) -#define QDMA_CPM4_GLBL2_CHANNEL_CAP_ADDR 0x120 -#define GLBL2_CHANNEL_CAP_RSVD_1_MASK GENMASK(31, 12) -#define GLBL2_CHANNEL_CAP_MULTIQ_MAX_MASK GENMASK(11, 0) -#define QDMA_CPM4_GLBL2_CHANNEL_PASID_CAP_ADDR 0x128 -#define GLBL2_CHANNEL_PASID_CAP_RSVD_1_MASK GENMASK(31, 16) -#define GLBL2_CHANNEL_PASID_CAP_BRIDGEOFFSET_MASK GENMASK(15, 4) -#define GLBL2_CHANNEL_PASID_CAP_RSVD_2_MASK GENMASK(3, 2) -#define GLBL2_CHANNEL_PASID_CAP_BRIDGEEN_MASK BIT(1) -#define GLBL2_CHANNEL_PASID_CAP_DMAEN_MASK BIT(0) -#define QDMA_CPM4_GLBL2_CHANNEL_FUNC_RET_ADDR 0x12C -#define GLBL2_CHANNEL_FUNC_RET_RSVD_1_MASK GENMASK(31, 8) -#define GLBL2_CHANNEL_FUNC_RET_FUNC_MASK GENMASK(7, 0) -#define QDMA_CPM4_GLBL2_SYSTEM_ID_ADDR 0x130 -#define GLBL2_SYSTEM_ID_RSVD_1_MASK GENMASK(31, 16) -#define GLBL2_SYSTEM_ID_MASK GENMASK(15, 0) -#define QDMA_CPM4_GLBL2_MISC_CAP_ADDR 0x134 -#define GLBL2_MISC_CAP_RSVD_1_MASK GENMASK(31, 0) -#define QDMA_CPM4_GLBL2_DBG_PCIE_RQ0_ADDR 0x1B8 -#define GLBL2_PCIE_RQ0_NPH_AVL_MASK GENMASK(31, 20) -#define GLBL2_PCIE_RQ0_RCB_AVL_MASK GENMASK(19, 10) -#define GLBL2_PCIE_RQ0_SLV_RD_CREDS_MASK GENMASK(9, 4) -#define GLBL2_PCIE_RQ0_TAG_EP_MASK GENMASK(3, 2) -#define GLBL2_PCIE_RQ0_TAG_FL_MASK GENMASK(1, 0) -#define QDMA_CPM4_GLBL2_DBG_PCIE_RQ1_ADDR 0x1BC -#define GLBL2_PCIE_RQ1_RSVD_1_MASK GENMASK(31, 17) -#define GLBL2_PCIE_RQ1_WTLP_REQ_MASK BIT(16) -#define GLBL2_PCIE_RQ1_WTLP_HEADER_FIFO_FL_MASK BIT(15) -#define GLBL2_PCIE_RQ1_WTLP_HEADER_FIFO_EP_MASK BIT(14) -#define GLBL2_PCIE_RQ1_RQ_FIFO_EP_MASK BIT(13) -#define GLBL2_PCIE_RQ1_RQ_FIFO_FL_MASK BIT(12) -#define GLBL2_PCIE_RQ1_TLPSM_MASK GENMASK(11, 9) -#define GLBL2_PCIE_RQ1_TLPSM512_MASK GENMASK(8, 6) -#define GLBL2_PCIE_RQ1_RREQ0_RCB_OK_MASK BIT(5) -#define GLBL2_PCIE_RQ1_RREQ0_SLV_MASK BIT(4) -#define GLBL2_PCIE_RQ1_RREQ0_VLD_MASK BIT(3) -#define GLBL2_PCIE_RQ1_RREQ1_RCB_OK_MASK BIT(2) -#define GLBL2_PCIE_RQ1_RREQ1_SLV_MASK BIT(1) -#define GLBL2_PCIE_RQ1_RREQ1_VLD_MASK BIT(0) -#define QDMA_CPM4_GLBL2_DBG_AXIMM_WR0_ADDR 0x1C0 -#define GLBL2_AXIMM_WR0_RSVD_1_MASK GENMASK(31, 27) -#define GLBL2_AXIMM_WR0_WR_REQ_MASK BIT(26) -#define GLBL2_AXIMM_WR0_WR_CHN_MASK GENMASK(25, 23) -#define GLBL2_AXIMM_WR0_WTLP_DATA_FIFO_EP_MASK BIT(22) -#define GLBL2_AXIMM_WR0_WPL_FIFO_EP_MASK BIT(21) -#define GLBL2_AXIMM_WR0_BRSP_CLAIM_CHN_MASK GENMASK(20, 18) -#define GLBL2_AXIMM_WR0_WRREQ_CNT_MASK GENMASK(17, 12) -#define GLBL2_AXIMM_WR0_BID_MASK GENMASK(11, 9) -#define GLBL2_AXIMM_WR0_BVALID_MASK BIT(8) -#define GLBL2_AXIMM_WR0_BREADY_MASK BIT(7) -#define GLBL2_AXIMM_WR0_WVALID_MASK BIT(6) -#define GLBL2_AXIMM_WR0_WREADY_MASK BIT(5) -#define GLBL2_AXIMM_WR0_AWID_MASK GENMASK(4, 2) -#define GLBL2_AXIMM_WR0_AWVALID_MASK BIT(1) -#define GLBL2_AXIMM_WR0_AWREADY_MASK BIT(0) -#define QDMA_CPM4_GLBL2_DBG_AXIMM_WR1_ADDR 0x1C4 -#define GLBL2_AXIMM_WR1_RSVD_1_MASK GENMASK(31, 30) -#define GLBL2_AXIMM_WR1_BRSP_CNT4_MASK GENMASK(29, 24) -#define GLBL2_AXIMM_WR1_BRSP_CNT3_MASK GENMASK(23, 18) -#define GLBL2_AXIMM_WR1_BRSP_CNT2_MASK GENMASK(17, 12) -#define GLBL2_AXIMM_WR1_BRSP_CNT1_MASK GENMASK(11, 6) -#define GLBL2_AXIMM_WR1_BRSP_CNT0_MASK GENMASK(5, 0) -#define QDMA_CPM4_GLBL2_DBG_AXIMM_RD0_ADDR 0x1C8 -#define GLBL2_AXIMM_RD0_RSVD_1_MASK GENMASK(31, 23) -#define GLBL2_AXIMM_RD0_PND_CNT_MASK GENMASK(22, 17) -#define GLBL2_AXIMM_RD0_RD_CHNL_MASK GENMASK(16, 14) -#define GLBL2_AXIMM_RD0_RD_REQ_MASK BIT(13) -#define GLBL2_AXIMM_RD0_RRSP_CLAIM_CHNL_MASK GENMASK(12, 10) -#define GLBL2_AXIMM_RD0_RID_MASK GENMASK(9, 7) -#define GLBL2_AXIMM_RD0_RVALID_MASK BIT(6) -#define GLBL2_AXIMM_RD0_RREADY_MASK BIT(5) -#define GLBL2_AXIMM_RD0_ARID_MASK GENMASK(4, 2) -#define GLBL2_AXIMM_RD0_ARVALID_MASK BIT(1) -#define GLBL2_AXIMM_RD0_ARREADY_MASK BIT(0) -#define QDMA_CPM4_GLBL2_DBG_AXIMM_RD1_ADDR 0x1CC -#define GLBL2_AXIMM_RD1_RSVD_1_MASK GENMASK(31, 30) -#define GLBL2_AXIMM_RD1_RRSP_CNT4_MASK GENMASK(29, 24) -#define GLBL2_AXIMM_RD1_RRSP_CNT3_MASK GENMASK(23, 18) -#define GLBL2_AXIMM_RD1_RRSP_CNT2_MASK GENMASK(17, 12) -#define GLBL2_AXIMM_RD1_RRSP_CNT1_MASK GENMASK(11, 6) -#define GLBL2_AXIMM_RD1_RRSP_CNT0_MASK GENMASK(5, 0) -#define QDMA_CPM4_GLBL_RNG_SZ_1_ADDR 0x204 -#define GLBL_RNG_SZ_1_RSVD_1_MASK GENMASK(31, 16) -#define GLBL_RNG_SZ_1_RING_SIZE_MASK GENMASK(15, 0) -#define QDMA_CPM4_GLBL_RNG_SZ_2_ADDR 0x208 -#define GLBL_RNG_SZ_2_RSVD_1_MASK GENMASK(31, 16) -#define GLBL_RNG_SZ_2_RING_SIZE_MASK GENMASK(15, 0) -#define QDMA_CPM4_GLBL_RNG_SZ_3_ADDR 0x20C -#define GLBL_RNG_SZ_3_RSVD_1_MASK GENMASK(31, 16) -#define GLBL_RNG_SZ_3_RING_SIZE_MASK GENMASK(15, 0) -#define QDMA_CPM4_GLBL_RNG_SZ_4_ADDR 0x210 -#define GLBL_RNG_SZ_4_RSVD_1_MASK GENMASK(31, 16) -#define GLBL_RNG_SZ_4_RING_SIZE_MASK GENMASK(15, 0) -#define QDMA_CPM4_GLBL_RNG_SZ_5_ADDR 0x214 -#define GLBL_RNG_SZ_5_RSVD_1_MASK GENMASK(31, 16) -#define GLBL_RNG_SZ_5_RING_SIZE_MASK GENMASK(15, 0) -#define QDMA_CPM4_GLBL_RNG_SZ_6_ADDR 0x218 -#define GLBL_RNG_SZ_6_RSVD_1_MASK GENMASK(31, 16) -#define GLBL_RNG_SZ_6_RING_SIZE_MASK GENMASK(15, 0) -#define QDMA_CPM4_GLBL_RNG_SZ_7_ADDR 0x21C -#define GLBL_RNG_SZ_7_RSVD_1_MASK GENMASK(31, 16) -#define GLBL_RNG_SZ_7_RING_SIZE_MASK GENMASK(15, 0) -#define QDMA_CPM4_GLBL_RNG_SZ_8_ADDR 0x220 -#define GLBL_RNG_SZ_8_RSVD_1_MASK GENMASK(31, 16) -#define GLBL_RNG_SZ_8_RING_SIZE_MASK GENMASK(15, 0) -#define QDMA_CPM4_GLBL_RNG_SZ_9_ADDR 0x224 -#define GLBL_RNG_SZ_9_RSVD_1_MASK GENMASK(31, 16) -#define GLBL_RNG_SZ_9_RING_SIZE_MASK GENMASK(15, 0) -#define QDMA_CPM4_GLBL_RNG_SZ_A_ADDR 0x228 -#define GLBL_RNG_SZ_A_RSVD_1_MASK GENMASK(31, 16) -#define GLBL_RNG_SZ_A_RING_SIZE_MASK GENMASK(15, 0) -#define QDMA_CPM4_GLBL_RNG_SZ_B_ADDR 0x22C -#define GLBL_RNG_SZ_B_RSVD_1_MASK GENMASK(31, 16) -#define GLBL_RNG_SZ_B_RING_SIZE_MASK GENMASK(15, 0) -#define QDMA_CPM4_GLBL_RNG_SZ_C_ADDR 0x230 -#define GLBL_RNG_SZ_C_RSVD_1_MASK GENMASK(31, 16) -#define GLBL_RNG_SZ_C_RING_SIZE_MASK GENMASK(15, 0) -#define QDMA_CPM4_GLBL_RNG_SZ_D_ADDR 0x234 -#define GLBL_RNG_SZ_D_RSVD_1_MASK GENMASK(31, 16) -#define GLBL_RNG_SZ_D_RING_SIZE_MASK GENMASK(15, 0) -#define QDMA_CPM4_GLBL_RNG_SZ_E_ADDR 0x238 -#define GLBL_RNG_SZ_E_RSVD_1_MASK GENMASK(31, 16) -#define GLBL_RNG_SZ_E_RING_SIZE_MASK GENMASK(15, 0) -#define QDMA_CPM4_GLBL_RNG_SZ_F_ADDR 0x23C -#define GLBL_RNG_SZ_F_RSVD_1_MASK GENMASK(31, 16) -#define GLBL_RNG_SZ_F_RING_SIZE_MASK GENMASK(15, 0) -#define QDMA_CPM4_GLBL_RNG_SZ_10_ADDR 0x240 -#define GLBL_RNG_SZ_10_RSVD_1_MASK GENMASK(31, 16) -#define GLBL_RNG_SZ_10_RING_SIZE_MASK GENMASK(15, 0) -#define QDMA_CPM4_GLBL_ERR_STAT_ADDR 0x248 -#define GLBL_ERR_STAT_RSVD_1_MASK GENMASK(31, 12) -#define GLBL_ERR_STAT_ERR_H2C_ST_MASK BIT(11) -#define GLBL_ERR_STAT_ERR_BDG_MASK BIT(10) -#define GLBL_ERR_STAT_IND_CTXT_CMD_ERR_MASK BIT(9) -#define GLBL_ERR_STAT_ERR_C2H_ST_MASK BIT(8) -#define GLBL_ERR_STAT_ERR_C2H_MM_1_MASK BIT(7) -#define GLBL_ERR_STAT_ERR_C2H_MM_0_MASK BIT(6) -#define GLBL_ERR_STAT_ERR_H2C_MM_1_MASK BIT(5) -#define GLBL_ERR_STAT_ERR_H2C_MM_0_MASK BIT(4) -#define GLBL_ERR_STAT_ERR_TRQ_MASK BIT(3) -#define GLBL_ERR_STAT_ERR_DSC_MASK BIT(2) -#define GLBL_ERR_STAT_ERR_RAM_DBE_MASK BIT(1) -#define GLBL_ERR_STAT_ERR_RAM_SBE_MASK BIT(0) -#define QDMA_CPM4_GLBL_ERR_MASK_ADDR 0x24C -#define GLBL_ERR_RSVD_1_MASK GENMASK(31, 9) -#define GLBL_ERR_MASK GENMASK(8, 0) -#define QDMA_CPM4_GLBL_DSC_CFG_ADDR 0x250 -#define GLBL_DSC_CFG_RSVD_1_MASK GENMASK(31, 10) -#define GLBL_DSC_CFG_UNC_OVR_COR_MASK BIT(9) -#define GLBL_DSC_CFG_CTXT_FER_DIS_MASK BIT(8) -#define GLBL_DSC_CFG_RSVD_2_MASK GENMASK(7, 6) -#define GLBL_DSC_CFG_MAXFETCH_MASK GENMASK(5, 3) -#define GLBL_DSC_CFG_WB_ACC_INT_MASK GENMASK(2, 0) -#define QDMA_CPM4_GLBL_DSC_ERR_STS_ADDR 0x254 -#define GLBL_DSC_ERR_STS_RSVD_1_MASK GENMASK(31, 25) -#define GLBL_DSC_ERR_STS_SBE_MASK BIT(24) -#define GLBL_DSC_ERR_STS_DBE_MASK BIT(23) -#define GLBL_DSC_ERR_STS_RQ_CANCEL_MASK BIT(22) -#define GLBL_DSC_ERR_STS_DSC_MASK BIT(21) -#define GLBL_DSC_ERR_STS_DMA_MASK BIT(20) -#define GLBL_DSC_ERR_STS_FLR_CANCEL_MASK BIT(19) -#define GLBL_DSC_ERR_STS_RSVD_2_MASK GENMASK(18, 17) -#define GLBL_DSC_ERR_STS_DAT_POISON_MASK BIT(16) -#define GLBL_DSC_ERR_STS_TIMEOUT_MASK BIT(9) -#define GLBL_DSC_ERR_STS_FLR_MASK BIT(5) -#define GLBL_DSC_ERR_STS_TAG_MASK BIT(4) -#define GLBL_DSC_ERR_STS_ADDR_MASK BIT(3) -#define GLBL_DSC_ERR_STS_PARAM_MASK BIT(2) -#define GLBL_DSC_ERR_STS_UR_CA_MASK BIT(1) -#define GLBL_DSC_ERR_STS_POISON_MASK BIT(0) -#define QDMA_CPM4_GLBL_DSC_ERR_MSK_ADDR 0x258 -#define GLBL_DSC_ERR_MSK_MASK GENMASK(8, 0) -#define QDMA_CPM4_GLBL_DSC_ERR_LOG0_ADDR 0x25C -#define GLBL_DSC_ERR_LOG0_VALID_MASK BIT(31) -#define GLBL_DSC_ERR_LOG0_RSVD_1_MASK GENMASK(30, 29) -#define GLBL_DSC_ERR_LOG0_QID_MASK GENMASK(28, 17) -#define GLBL_DSC_ERR_LOG0_SEL_MASK BIT(16) -#define GLBL_DSC_ERR_LOG0_CIDX_MASK GENMASK(15, 0) -#define QDMA_CPM4_GLBL_DSC_ERR_LOG1_ADDR 0x260 -#define GLBL_DSC_ERR_LOG1_RSVD_1_MASK GENMASK(31, 9) -#define GLBL_DSC_ERR_LOG1_SUB_TYPE_MASK GENMASK(8, 5) -#define GLBL_DSC_ERR_LOG1_ERR_TYPE_MASK GENMASK(4, 0) -#define QDMA_CPM4_GLBL_TRQ_ERR_STS_ADDR 0x264 -#define GLBL_TRQ_ERR_STS_RSVD_1_MASK GENMASK(31, 4) -#define GLBL_TRQ_ERR_STS_TCP_TIMEOUT_MASK BIT(3) -#define GLBL_TRQ_ERR_STS_VF_ACCESS_ERR_MASK BIT(2) -#define GLBL_TRQ_ERR_STS_QID_RANGE_MASK BIT(1) -#define GLBL_TRQ_ERR_STS_UNMAPPED_MASK BIT(0) -#define QDMA_CPM4_GLBL_TRQ_ERR_MSK_ADDR 0x268 -#define GLBL_TRQ_ERR_MSK_MASK GENMASK(31, 0) -#define QDMA_CPM4_GLBL_TRQ_ERR_LOG_ADDR 0x26C -#define GLBL_TRQ_ERR_LOG_RSVD_1_MASK GENMASK(31, 28) -#define GLBL_TRQ_ERR_LOG_TARGET_MASK GENMASK(27, 24) -#define GLBL_TRQ_ERR_LOG_FUNC_MASK GENMASK(23, 16) -#define GLBL_TRQ_ERR_LOG_ADDRESS_MASK GENMASK(15, 0) -#define QDMA_CPM4_GLBL_DSC_DBG_DAT0_ADDR 0x270 -#define GLBL_DSC_DAT0_RSVD_1_MASK GENMASK(31, 30) -#define GLBL_DSC_DAT0_CTXT_ARB_DIR_MASK BIT(29) -#define GLBL_DSC_DAT0_CTXT_ARB_QID_MASK GENMASK(28, 17) -#define GLBL_DSC_DAT0_CTXT_ARB_REQ_MASK GENMASK(16, 12) -#define GLBL_DSC_DAT0_IRQ_FIFO_FL_MASK BIT(11) -#define GLBL_DSC_DAT0_TMSTALL_MASK BIT(10) -#define GLBL_DSC_DAT0_RRQ_STALL_MASK GENMASK(9, 8) -#define GLBL_DSC_DAT0_RCP_FIFO_SPC_STALL_MASK GENMASK(7, 6) -#define GLBL_DSC_DAT0_RRQ_FIFO_SPC_STALL_MASK GENMASK(5, 4) -#define GLBL_DSC_DAT0_FAB_MRKR_RSP_STALL_MASK GENMASK(3, 2) -#define GLBL_DSC_DAT0_DSC_OUT_STALL_MASK GENMASK(1, 0) -#define QDMA_CPM4_GLBL_DSC_DBG_DAT1_ADDR 0x274 -#define GLBL_DSC_DAT1_RSVD_1_MASK GENMASK(31, 28) -#define GLBL_DSC_DAT1_EVT_SPC_C2H_MASK GENMASK(27, 22) -#define GLBL_DSC_DAT1_EVT_SP_H2C_MASK GENMASK(21, 16) -#define GLBL_DSC_DAT1_DSC_SPC_C2H_MASK GENMASK(15, 8) -#define GLBL_DSC_DAT1_DSC_SPC_H2C_MASK GENMASK(7, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_0_ADDR 0x400 -#define TRQ_SEL_FMAP_0_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_0_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_0_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_1_ADDR 0x404 -#define TRQ_SEL_FMAP_1_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_1_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_1_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_2_ADDR 0x408 -#define TRQ_SEL_FMAP_2_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_2_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_2_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_3_ADDR 0x40C -#define TRQ_SEL_FMAP_3_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_3_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_3_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_4_ADDR 0x410 -#define TRQ_SEL_FMAP_4_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_4_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_4_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_5_ADDR 0x414 -#define TRQ_SEL_FMAP_5_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_5_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_5_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_6_ADDR 0x418 -#define TRQ_SEL_FMAP_6_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_6_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_6_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_7_ADDR 0x41C -#define TRQ_SEL_FMAP_7_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_7_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_7_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_8_ADDR 0x420 -#define TRQ_SEL_FMAP_8_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_8_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_8_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_9_ADDR 0x424 -#define TRQ_SEL_FMAP_9_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_9_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_9_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_A_ADDR 0x428 -#define TRQ_SEL_FMAP_A_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_A_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_A_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_B_ADDR 0x42C -#define TRQ_SEL_FMAP_B_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_B_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_B_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_D_ADDR 0x430 -#define TRQ_SEL_FMAP_D_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_D_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_D_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_E_ADDR 0x434 -#define TRQ_SEL_FMAP_E_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_E_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_E_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_F_ADDR 0x438 -#define TRQ_SEL_FMAP_F_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_F_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_F_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_10_ADDR 0x43C -#define TRQ_SEL_FMAP_10_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_10_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_10_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_11_ADDR 0x440 -#define TRQ_SEL_FMAP_11_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_11_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_11_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_12_ADDR 0x444 -#define TRQ_SEL_FMAP_12_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_12_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_12_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_13_ADDR 0x448 -#define TRQ_SEL_FMAP_13_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_13_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_13_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_14_ADDR 0x44C -#define TRQ_SEL_FMAP_14_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_14_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_14_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_15_ADDR 0x450 -#define TRQ_SEL_FMAP_15_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_15_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_15_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_16_ADDR 0x454 -#define TRQ_SEL_FMAP_16_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_16_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_16_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_17_ADDR 0x458 -#define TRQ_SEL_FMAP_17_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_17_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_17_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_18_ADDR 0x45C -#define TRQ_SEL_FMAP_18_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_18_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_18_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_19_ADDR 0x460 -#define TRQ_SEL_FMAP_19_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_19_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_19_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_1A_ADDR 0x464 -#define TRQ_SEL_FMAP_1A_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_1A_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_1A_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_1B_ADDR 0x468 -#define TRQ_SEL_FMAP_1B_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_1B_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_1B_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_1C_ADDR 0x46C -#define TRQ_SEL_FMAP_1C_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_1C_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_1C_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_1D_ADDR 0x470 -#define TRQ_SEL_FMAP_1D_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_1D_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_1D_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_1E_ADDR 0x474 -#define TRQ_SEL_FMAP_1E_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_1E_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_1E_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_1F_ADDR 0x478 -#define TRQ_SEL_FMAP_1F_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_1F_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_1F_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_20_ADDR 0x47C -#define TRQ_SEL_FMAP_20_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_20_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_20_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_21_ADDR 0x480 -#define TRQ_SEL_FMAP_21_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_21_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_21_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_22_ADDR 0x484 -#define TRQ_SEL_FMAP_22_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_22_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_22_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_23_ADDR 0x488 -#define TRQ_SEL_FMAP_23_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_23_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_23_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_24_ADDR 0x48C -#define TRQ_SEL_FMAP_24_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_24_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_24_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_25_ADDR 0x490 -#define TRQ_SEL_FMAP_25_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_25_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_25_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_26_ADDR 0x494 -#define TRQ_SEL_FMAP_26_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_26_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_26_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_27_ADDR 0x498 -#define TRQ_SEL_FMAP_27_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_27_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_27_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_28_ADDR 0x49C -#define TRQ_SEL_FMAP_28_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_28_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_28_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_29_ADDR 0x4A0 -#define TRQ_SEL_FMAP_29_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_29_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_29_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_2A_ADDR 0x4A4 -#define TRQ_SEL_FMAP_2A_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_2A_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_2A_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_2B_ADDR 0x4A8 -#define TRQ_SEL_FMAP_2B_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_2B_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_2B_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_2C_ADDR 0x4AC -#define TRQ_SEL_FMAP_2C_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_2C_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_2C_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_2D_ADDR 0x4B0 -#define TRQ_SEL_FMAP_2D_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_2D_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_2D_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_2E_ADDR 0x4B4 -#define TRQ_SEL_FMAP_2E_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_2E_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_2E_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_2F_ADDR 0x4B8 -#define TRQ_SEL_FMAP_2F_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_2F_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_2F_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_30_ADDR 0x4BC -#define TRQ_SEL_FMAP_30_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_30_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_30_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_31_ADDR 0x4D0 -#define TRQ_SEL_FMAP_31_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_31_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_31_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_32_ADDR 0x4D4 -#define TRQ_SEL_FMAP_32_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_32_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_32_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_33_ADDR 0x4D8 -#define TRQ_SEL_FMAP_33_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_33_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_33_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_34_ADDR 0x4DC -#define TRQ_SEL_FMAP_34_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_34_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_34_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_35_ADDR 0x4E0 -#define TRQ_SEL_FMAP_35_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_35_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_35_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_36_ADDR 0x4E4 -#define TRQ_SEL_FMAP_36_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_36_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_36_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_37_ADDR 0x4E8 -#define TRQ_SEL_FMAP_37_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_37_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_37_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_38_ADDR 0x4EC -#define TRQ_SEL_FMAP_38_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_38_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_38_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_39_ADDR 0x4F0 -#define TRQ_SEL_FMAP_39_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_39_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_39_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_3A_ADDR 0x4F4 -#define TRQ_SEL_FMAP_3A_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_3A_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_3A_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_3B_ADDR 0x4F8 -#define TRQ_SEL_FMAP_3B_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_3B_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_3B_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_3C_ADDR 0x4FC -#define TRQ_SEL_FMAP_3C_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_3C_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_3C_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_3D_ADDR 0x500 -#define TRQ_SEL_FMAP_3D_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_3D_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_3D_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_3E_ADDR 0x504 -#define TRQ_SEL_FMAP_3E_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_3E_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_3E_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_3F_ADDR 0x508 -#define TRQ_SEL_FMAP_3F_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_3F_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_3F_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_40_ADDR 0x50C -#define TRQ_SEL_FMAP_40_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_40_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_40_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_41_ADDR 0x510 -#define TRQ_SEL_FMAP_41_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_41_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_41_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_42_ADDR 0x514 -#define TRQ_SEL_FMAP_42_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_42_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_42_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_43_ADDR 0x518 -#define TRQ_SEL_FMAP_43_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_43_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_43_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_44_ADDR 0x51C -#define TRQ_SEL_FMAP_44_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_44_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_44_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_45_ADDR 0x520 -#define TRQ_SEL_FMAP_45_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_45_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_45_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_46_ADDR 0x524 -#define TRQ_SEL_FMAP_46_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_46_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_46_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_47_ADDR 0x528 -#define TRQ_SEL_FMAP_47_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_47_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_47_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_48_ADDR 0x52C -#define TRQ_SEL_FMAP_48_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_48_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_48_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_49_ADDR 0x530 -#define TRQ_SEL_FMAP_49_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_49_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_49_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_4A_ADDR 0x534 -#define TRQ_SEL_FMAP_4A_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_4A_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_4A_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_4B_ADDR 0x538 -#define TRQ_SEL_FMAP_4B_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_4B_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_4B_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_4C_ADDR 0x53C -#define TRQ_SEL_FMAP_4C_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_4C_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_4C_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_4D_ADDR 0x540 -#define TRQ_SEL_FMAP_4D_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_4D_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_4D_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_4E_ADDR 0x544 -#define TRQ_SEL_FMAP_4E_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_4E_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_4E_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_4F_ADDR 0x548 -#define TRQ_SEL_FMAP_4F_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_4F_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_4F_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_50_ADDR 0x54C -#define TRQ_SEL_FMAP_50_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_50_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_50_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_51_ADDR 0x550 -#define TRQ_SEL_FMAP_51_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_51_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_51_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_52_ADDR 0x554 -#define TRQ_SEL_FMAP_52_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_52_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_52_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_53_ADDR 0x558 -#define TRQ_SEL_FMAP_53_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_53_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_53_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_54_ADDR 0x55C -#define TRQ_SEL_FMAP_54_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_54_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_54_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_55_ADDR 0x560 -#define TRQ_SEL_FMAP_55_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_55_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_55_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_56_ADDR 0x564 -#define TRQ_SEL_FMAP_56_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_56_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_56_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_57_ADDR 0x568 -#define TRQ_SEL_FMAP_57_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_57_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_57_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_58_ADDR 0x56C -#define TRQ_SEL_FMAP_58_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_58_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_58_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_59_ADDR 0x570 -#define TRQ_SEL_FMAP_59_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_59_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_59_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_5A_ADDR 0x574 -#define TRQ_SEL_FMAP_5A_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_5A_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_5A_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_5B_ADDR 0x578 -#define TRQ_SEL_FMAP_5B_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_5B_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_5B_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_5C_ADDR 0x57C -#define TRQ_SEL_FMAP_5C_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_5C_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_5C_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_5D_ADDR 0x580 -#define TRQ_SEL_FMAP_5D_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_5D_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_5D_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_5E_ADDR 0x584 -#define TRQ_SEL_FMAP_5E_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_5E_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_5E_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_5F_ADDR 0x588 -#define TRQ_SEL_FMAP_5F_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_5F_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_5F_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_60_ADDR 0x58C -#define TRQ_SEL_FMAP_60_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_60_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_60_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_61_ADDR 0x590 -#define TRQ_SEL_FMAP_61_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_61_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_61_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_62_ADDR 0x594 -#define TRQ_SEL_FMAP_62_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_62_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_62_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_63_ADDR 0x598 -#define TRQ_SEL_FMAP_63_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_63_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_63_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_64_ADDR 0x59C -#define TRQ_SEL_FMAP_64_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_64_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_64_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_65_ADDR 0x5A0 -#define TRQ_SEL_FMAP_65_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_65_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_65_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_66_ADDR 0x5A4 -#define TRQ_SEL_FMAP_66_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_66_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_66_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_67_ADDR 0x5A8 -#define TRQ_SEL_FMAP_67_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_67_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_67_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_68_ADDR 0x5AC -#define TRQ_SEL_FMAP_68_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_68_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_68_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_69_ADDR 0x5B0 -#define TRQ_SEL_FMAP_69_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_69_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_69_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_6A_ADDR 0x5B4 -#define TRQ_SEL_FMAP_6A_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_6A_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_6A_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_6B_ADDR 0x5B8 -#define TRQ_SEL_FMAP_6B_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_6B_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_6B_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_6C_ADDR 0x5BC -#define TRQ_SEL_FMAP_6C_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_6C_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_6C_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_6D_ADDR 0x5C0 -#define TRQ_SEL_FMAP_6D_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_6D_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_6D_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_6E_ADDR 0x5C4 -#define TRQ_SEL_FMAP_6E_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_6E_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_6E_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_6F_ADDR 0x5C8 -#define TRQ_SEL_FMAP_6F_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_6F_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_6F_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_70_ADDR 0x5CC -#define TRQ_SEL_FMAP_70_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_70_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_70_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_71_ADDR 0x5D0 -#define TRQ_SEL_FMAP_71_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_71_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_71_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_72_ADDR 0x5D4 -#define TRQ_SEL_FMAP_72_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_72_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_72_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_73_ADDR 0x5D8 -#define TRQ_SEL_FMAP_73_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_73_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_73_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_74_ADDR 0x5DC -#define TRQ_SEL_FMAP_74_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_74_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_74_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_75_ADDR 0x5E0 -#define TRQ_SEL_FMAP_75_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_75_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_75_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_76_ADDR 0x5E4 -#define TRQ_SEL_FMAP_76_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_76_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_76_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_77_ADDR 0x5E8 -#define TRQ_SEL_FMAP_77_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_77_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_77_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_78_ADDR 0x5EC -#define TRQ_SEL_FMAP_78_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_78_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_78_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_79_ADDR 0x5F0 -#define TRQ_SEL_FMAP_79_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_79_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_79_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_7A_ADDR 0x5F4 -#define TRQ_SEL_FMAP_7A_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_7A_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_7A_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_7B_ADDR 0x5F8 -#define TRQ_SEL_FMAP_7B_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_7B_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_7B_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_7C_ADDR 0x5FC -#define TRQ_SEL_FMAP_7C_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_7C_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_7C_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_7D_ADDR 0x600 -#define TRQ_SEL_FMAP_7D_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_7D_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_7D_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_7E_ADDR 0x604 -#define TRQ_SEL_FMAP_7E_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_7E_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_7E_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_7F_ADDR 0x608 -#define TRQ_SEL_FMAP_7F_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_7F_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_7F_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_80_ADDR 0x60C -#define TRQ_SEL_FMAP_80_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_80_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_80_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_81_ADDR 0x610 -#define TRQ_SEL_FMAP_81_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_81_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_81_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_82_ADDR 0x614 -#define TRQ_SEL_FMAP_82_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_82_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_82_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_83_ADDR 0x618 -#define TRQ_SEL_FMAP_83_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_83_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_83_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_84_ADDR 0x61C -#define TRQ_SEL_FMAP_84_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_84_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_84_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_85_ADDR 0x620 -#define TRQ_SEL_FMAP_85_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_85_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_85_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_86_ADDR 0x624 -#define TRQ_SEL_FMAP_86_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_86_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_86_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_87_ADDR 0x628 -#define TRQ_SEL_FMAP_87_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_87_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_87_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_88_ADDR 0x62C -#define TRQ_SEL_FMAP_88_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_88_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_88_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_89_ADDR 0x630 -#define TRQ_SEL_FMAP_89_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_89_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_89_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_8A_ADDR 0x634 -#define TRQ_SEL_FMAP_8A_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_8A_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_8A_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_8B_ADDR 0x638 -#define TRQ_SEL_FMAP_8B_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_8B_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_8B_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_8C_ADDR 0x63C -#define TRQ_SEL_FMAP_8C_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_8C_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_8C_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_8D_ADDR 0x640 -#define TRQ_SEL_FMAP_8D_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_8D_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_8D_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_8E_ADDR 0x644 -#define TRQ_SEL_FMAP_8E_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_8E_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_8E_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_8F_ADDR 0x648 -#define TRQ_SEL_FMAP_8F_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_8F_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_8F_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_90_ADDR 0x64C -#define TRQ_SEL_FMAP_90_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_90_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_90_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_91_ADDR 0x650 -#define TRQ_SEL_FMAP_91_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_91_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_91_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_92_ADDR 0x654 -#define TRQ_SEL_FMAP_92_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_92_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_92_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_93_ADDR 0x658 -#define TRQ_SEL_FMAP_93_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_93_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_93_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_94_ADDR 0x65C -#define TRQ_SEL_FMAP_94_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_94_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_94_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_95_ADDR 0x660 -#define TRQ_SEL_FMAP_95_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_95_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_95_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_96_ADDR 0x664 -#define TRQ_SEL_FMAP_96_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_96_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_96_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_97_ADDR 0x668 -#define TRQ_SEL_FMAP_97_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_97_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_97_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_98_ADDR 0x66C -#define TRQ_SEL_FMAP_98_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_98_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_98_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_99_ADDR 0x670 -#define TRQ_SEL_FMAP_99_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_99_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_99_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_9A_ADDR 0x674 -#define TRQ_SEL_FMAP_9A_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_9A_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_9A_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_9B_ADDR 0x678 -#define TRQ_SEL_FMAP_9B_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_9B_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_9B_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_9C_ADDR 0x67C -#define TRQ_SEL_FMAP_9C_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_9C_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_9C_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_9D_ADDR 0x680 -#define TRQ_SEL_FMAP_9D_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_9D_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_9D_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_9E_ADDR 0x684 -#define TRQ_SEL_FMAP_9E_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_9E_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_9E_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_9F_ADDR 0x688 -#define TRQ_SEL_FMAP_9F_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_9F_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_9F_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_A0_ADDR 0x68C -#define TRQ_SEL_FMAP_A0_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_A0_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_A0_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_A1_ADDR 0x690 -#define TRQ_SEL_FMAP_A1_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_A1_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_A1_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_A2_ADDR 0x694 -#define TRQ_SEL_FMAP_A2_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_A2_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_A2_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_A3_ADDR 0x698 -#define TRQ_SEL_FMAP_A3_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_A3_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_A3_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_A4_ADDR 0x69C -#define TRQ_SEL_FMAP_A4_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_A4_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_A4_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_A5_ADDR 0x6A0 -#define TRQ_SEL_FMAP_A5_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_A5_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_A5_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_A6_ADDR 0x6A4 -#define TRQ_SEL_FMAP_A6_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_A6_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_A6_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_A7_ADDR 0x6A8 -#define TRQ_SEL_FMAP_A7_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_A7_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_A7_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_A8_ADDR 0x6AC -#define TRQ_SEL_FMAP_A8_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_A8_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_A8_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_A9_ADDR 0x6B0 -#define TRQ_SEL_FMAP_A9_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_A9_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_A9_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_AA_ADDR 0x6B4 -#define TRQ_SEL_FMAP_AA_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_AA_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_AA_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_AB_ADDR 0x6B8 -#define TRQ_SEL_FMAP_AB_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_AB_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_AB_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_AC_ADDR 0x6BC -#define TRQ_SEL_FMAP_AC_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_AC_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_AC_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_AD_ADDR 0x6D0 -#define TRQ_SEL_FMAP_AD_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_AD_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_AD_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_AE_ADDR 0x6D4 -#define TRQ_SEL_FMAP_AE_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_AE_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_AE_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_AF_ADDR 0x6D8 -#define TRQ_SEL_FMAP_AF_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_AF_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_AF_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_B0_ADDR 0x6DC -#define TRQ_SEL_FMAP_B0_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_B0_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_B0_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_B1_ADDR 0x6E0 -#define TRQ_SEL_FMAP_B1_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_B1_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_B1_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_B2_ADDR 0x6E4 -#define TRQ_SEL_FMAP_B2_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_B2_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_B2_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_B3_ADDR 0x6E8 -#define TRQ_SEL_FMAP_B3_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_B3_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_B3_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_B4_ADDR 0x6EC -#define TRQ_SEL_FMAP_B4_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_B4_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_B4_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_B5_ADDR 0x6F0 -#define TRQ_SEL_FMAP_B5_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_B5_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_B5_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_B6_ADDR 0x6F4 -#define TRQ_SEL_FMAP_B6_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_B6_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_B6_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_B7_ADDR 0x6F8 -#define TRQ_SEL_FMAP_B7_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_B7_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_B7_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_B8_ADDR 0x6FC -#define TRQ_SEL_FMAP_B8_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_B8_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_B8_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_B9_ADDR 0x700 -#define TRQ_SEL_FMAP_B9_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_B9_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_B9_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_BA_ADDR 0x704 -#define TRQ_SEL_FMAP_BA_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_BA_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_BA_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_BB_ADDR 0x708 -#define TRQ_SEL_FMAP_BB_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_BB_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_BB_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_BC_ADDR 0x70C -#define TRQ_SEL_FMAP_BC_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_BC_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_BC_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_BD_ADDR 0x710 -#define TRQ_SEL_FMAP_BD_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_BD_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_BD_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_BE_ADDR 0x714 -#define TRQ_SEL_FMAP_BE_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_BE_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_BE_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_BF_ADDR 0x718 -#define TRQ_SEL_FMAP_BF_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_BF_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_BF_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_C0_ADDR 0x71C -#define TRQ_SEL_FMAP_C0_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_C0_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_C0_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_C1_ADDR 0x720 -#define TRQ_SEL_FMAP_C1_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_C1_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_C1_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_C2_ADDR 0x734 -#define TRQ_SEL_FMAP_C2_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_C2_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_C2_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_C3_ADDR 0x748 -#define TRQ_SEL_FMAP_C3_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_C3_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_C3_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_C4_ADDR 0x74C -#define TRQ_SEL_FMAP_C4_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_C4_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_C4_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_C5_ADDR 0x750 -#define TRQ_SEL_FMAP_C5_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_C5_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_C5_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_C6_ADDR 0x754 -#define TRQ_SEL_FMAP_C6_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_C6_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_C6_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_C7_ADDR 0x758 -#define TRQ_SEL_FMAP_C7_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_C7_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_C7_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_C8_ADDR 0x75C -#define TRQ_SEL_FMAP_C8_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_C8_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_C8_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_C9_ADDR 0x760 -#define TRQ_SEL_FMAP_C9_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_C9_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_C9_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_CA_ADDR 0x764 -#define TRQ_SEL_FMAP_CA_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_CA_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_CA_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_CB_ADDR 0x768 -#define TRQ_SEL_FMAP_CB_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_CB_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_CB_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_CC_ADDR 0x76C -#define TRQ_SEL_FMAP_CC_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_CC_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_CC_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_CD_ADDR 0x770 -#define TRQ_SEL_FMAP_CD_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_CD_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_CD_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_CE_ADDR 0x774 -#define TRQ_SEL_FMAP_CE_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_CE_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_CE_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_CF_ADDR 0x778 -#define TRQ_SEL_FMAP_CF_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_CF_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_CF_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_D0_ADDR 0x77C -#define TRQ_SEL_FMAP_D0_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_D0_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_D0_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_D1_ADDR 0x780 -#define TRQ_SEL_FMAP_D1_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_D1_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_D1_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_D2_ADDR 0x784 -#define TRQ_SEL_FMAP_D2_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_D2_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_D2_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_D3_ADDR 0x788 -#define TRQ_SEL_FMAP_D3_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_D3_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_D3_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_D4_ADDR 0x78C -#define TRQ_SEL_FMAP_D4_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_D4_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_D4_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_D5_ADDR 0x790 -#define TRQ_SEL_FMAP_D5_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_D5_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_D5_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_D6_ADDR 0x794 -#define TRQ_SEL_FMAP_D6_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_D6_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_D6_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_D7_ADDR 0x798 -#define TRQ_SEL_FMAP_D7_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_D7_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_D7_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_D8_ADDR 0x79C -#define TRQ_SEL_FMAP_D8_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_D8_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_D8_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_D9_ADDR 0x7A0 -#define TRQ_SEL_FMAP_D9_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_D9_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_D9_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_DA_ADDR 0x7A4 -#define TRQ_SEL_FMAP_DA_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_DA_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_DA_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_DB_ADDR 0x7A8 -#define TRQ_SEL_FMAP_DB_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_DB_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_DB_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_DC_ADDR 0x7AC -#define TRQ_SEL_FMAP_DC_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_DC_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_DC_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_DD_ADDR 0x7B0 -#define TRQ_SEL_FMAP_DD_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_DD_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_DD_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_DE_ADDR 0x7B4 -#define TRQ_SEL_FMAP_DE_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_DE_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_DE_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_DF_ADDR 0x7B8 -#define TRQ_SEL_FMAP_DF_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_DF_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_DF_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_E0_ADDR 0x7BC -#define TRQ_SEL_FMAP_E0_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_E0_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_E0_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_E1_ADDR 0x7C0 -#define TRQ_SEL_FMAP_E1_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_E1_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_E1_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_E2_ADDR 0x7C4 -#define TRQ_SEL_FMAP_E2_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_E2_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_E2_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_E3_ADDR 0x7C8 -#define TRQ_SEL_FMAP_E3_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_E3_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_E3_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_E4_ADDR 0x7CC -#define TRQ_SEL_FMAP_E4_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_E4_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_E4_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_E5_ADDR 0x7D0 -#define TRQ_SEL_FMAP_E5_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_E5_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_E5_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_E6_ADDR 0x7D4 -#define TRQ_SEL_FMAP_E6_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_E6_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_E6_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_E7_ADDR 0x7D8 -#define TRQ_SEL_FMAP_E7_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_E7_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_E7_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_E8_ADDR 0x7DC -#define TRQ_SEL_FMAP_E8_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_E8_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_E8_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_E9_ADDR 0x7E0 -#define TRQ_SEL_FMAP_E9_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_E9_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_E9_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_EA_ADDR 0x7E4 -#define TRQ_SEL_FMAP_EA_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_EA_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_EA_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_EB_ADDR 0x7E8 -#define TRQ_SEL_FMAP_EB_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_EB_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_EB_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_EC_ADDR 0x7EC -#define TRQ_SEL_FMAP_EC_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_EC_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_EC_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_ED_ADDR 0x7F0 -#define TRQ_SEL_FMAP_ED_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_ED_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_ED_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_EE_ADDR 0x7F4 -#define TRQ_SEL_FMAP_EE_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_EE_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_EE_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_EF_ADDR 0x7F8 -#define TRQ_SEL_FMAP_EF_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_EF_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_EF_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_F0_ADDR 0x7FC -#define TRQ_SEL_FMAP_F0_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_F0_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_F0_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_IND_CTXT_DATA_3_ADDR 0x804 -#define IND_CTXT_DATA_3_DATA_MASK GENMASK(31, 0) -#define QDMA_CPM4_IND_CTXT_DATA_2_ADDR 0x808 -#define IND_CTXT_DATA_2_DATA_MASK GENMASK(31, 0) -#define QDMA_CPM4_IND_CTXT_DATA_1_ADDR 0x80C -#define IND_CTXT_DATA_1_DATA_MASK GENMASK(31, 0) -#define QDMA_CPM4_IND_CTXT_DATA_0_ADDR 0x810 -#define IND_CTXT_DATA_0_DATA_MASK GENMASK(31, 0) -#define QDMA_CPM4_IND_CTXT3_ADDR 0x814 -#define IND_CTXT3_MASK GENMASK(31, 0) -#define QDMA_CPM4_IND_CTXT2_ADDR 0x818 -#define IND_CTXT2_MASK GENMASK(31, 0) -#define QDMA_CPM4_IND_CTXT1_ADDR 0x81C -#define IND_CTXT1_MASK GENMASK(31, 0) -#define QDMA_CPM4_IND_CTXT0_ADDR 0x820 -#define IND_CTXT0_MASK GENMASK(31, 0) -#define QDMA_CPM4_IND_CTXT_CMD_ADDR 0x824 -#define IND_CTXT_CMD_RSVD_1_MASK GENMASK(31, 18) -#define IND_CTXT_CMD_QID_MASK GENMASK(17, 7) -#define IND_CTXT_CMD_OP_MASK GENMASK(6, 5) -#define IND_CTXT_CMD_SET_MASK GENMASK(4, 1) -#define IND_CTXT_CMD_BUSY_MASK BIT(0) -#define QDMA_CPM4_C2H_TIMER_CNT_1_ADDR 0xA00 -#define C2H_TIMER_CNT_1_RSVD_1_MASK GENMASK(31, 8) -#define C2H_TIMER_CNT_1_MASK GENMASK(7, 0) -#define QDMA_CPM4_C2H_TIMER_CNT_2_ADDR 0xA04 -#define C2H_TIMER_CNT_2_RSVD_1_MASK GENMASK(31, 8) -#define C2H_TIMER_CNT_2_MASK GENMASK(7, 0) -#define QDMA_CPM4_C2H_TIMER_CNT_3_ADDR 0xA08 -#define C2H_TIMER_CNT_3_RSVD_1_MASK GENMASK(31, 8) -#define C2H_TIMER_CNT_3_MASK GENMASK(7, 0) -#define QDMA_CPM4_C2H_TIMER_CNT_4_ADDR 0xA0C -#define C2H_TIMER_CNT_4_RSVD_1_MASK GENMASK(31, 8) -#define C2H_TIMER_CNT_4_MASK GENMASK(7, 0) -#define QDMA_CPM4_C2H_TIMER_CNT_5_ADDR 0xA10 -#define C2H_TIMER_CNT_5_RSVD_1_MASK GENMASK(31, 8) -#define C2H_TIMER_CNT_5_MASK GENMASK(7, 0) -#define QDMA_CPM4_C2H_TIMER_CNT_6_ADDR 0xA14 -#define C2H_TIMER_CNT_6_RSVD_1_MASK GENMASK(31, 8) -#define C2H_TIMER_CNT_6_MASK GENMASK(7, 0) -#define QDMA_CPM4_C2H_TIMER_CNT_7_ADDR 0xA18 -#define C2H_TIMER_CNT_7_RSVD_1_MASK GENMASK(31, 8) -#define C2H_TIMER_CNT_7_MASK GENMASK(7, 0) -#define QDMA_CPM4_C2H_TIMER_CNT_8_ADDR 0xA1C -#define C2H_TIMER_CNT_8_RSVD_1_MASK GENMASK(31, 8) -#define C2H_TIMER_CNT_8_MASK GENMASK(7, 0) -#define QDMA_CPM4_C2H_TIMER_CNT_9_ADDR 0xA20 -#define C2H_TIMER_CNT_9_RSVD_1_MASK GENMASK(31, 8) -#define C2H_TIMER_CNT_9_MASK GENMASK(7, 0) -#define QDMA_CPM4_C2H_TIMER_CNT_A_ADDR 0xA24 -#define C2H_TIMER_CNT_A_RSVD_1_MASK GENMASK(31, 8) -#define C2H_TIMER_CNT_A_MASK GENMASK(7, 0) -#define QDMA_CPM4_C2H_TIMER_CNT_B_ADDR 0xA28 -#define C2H_TIMER_CNT_B_RSVD_1_MASK GENMASK(31, 8) -#define C2H_TIMER_CNT_B_MASK GENMASK(7, 0) -#define QDMA_CPM4_C2H_TIMER_CNT_C_ADDR 0xA2C -#define C2H_TIMER_CNT_C_RSVD_1_MASK GENMASK(31, 8) -#define C2H_TIMER_CNT_C_MASK GENMASK(7, 0) -#define QDMA_CPM4_C2H_TIMER_CNT_D_ADDR 0xA30 -#define C2H_TIMER_CNT_D_RSVD_1_MASK GENMASK(31, 8) -#define C2H_TIMER_CNT_D_MASK GENMASK(7, 0) -#define QDMA_CPM4_C2H_TIMER_CNT_E_ADDR 0xA34 -#define C2H_TIMER_CNT_E_RSVD_1_MASK GENMASK(31, 8) -#define C2H_TIMER_CNT_E_MASK GENMASK(7, 0) -#define QDMA_CPM4_C2H_TIMER_CNT_F_ADDR 0xA38 -#define C2H_TIMER_CNT_F_RSVD_1_MASK GENMASK(31, 8) -#define C2H_TIMER_CNT_F_MASK GENMASK(7, 0) -#define QDMA_CPM4_C2H_TIMER_CNT_10_ADDR 0xA3C -#define C2H_TIMER_CNT_10_RSVD_1_MASK GENMASK(31, 8) -#define C2H_TIMER_CNT_10_MASK GENMASK(7, 0) -#define QDMA_CPM4_C2H_CNT_TH_1_ADDR 0xA40 -#define C2H_CNT_TH_1_RSVD_1_MASK GENMASK(31, 8) -#define C2H_CNT_TH_1_THESHOLD_CNT_MASK GENMASK(7, 0) -#define QDMA_CPM4_C2H_CNT_TH_2_ADDR 0xA44 -#define C2H_CNT_TH_2_RSVD_1_MASK GENMASK(31, 8) -#define C2H_CNT_TH_2_THESHOLD_CNT_MASK GENMASK(7, 0) -#define QDMA_CPM4_C2H_CNT_TH_3_ADDR 0xA48 -#define C2H_CNT_TH_3_RSVD_1_MASK GENMASK(31, 8) -#define C2H_CNT_TH_3_THESHOLD_CNT_MASK GENMASK(7, 0) -#define QDMA_CPM4_C2H_CNT_TH_4_ADDR 0xA4C -#define C2H_CNT_TH_4_RSVD_1_MASK GENMASK(31, 8) -#define C2H_CNT_TH_4_THESHOLD_CNT_MASK GENMASK(7, 0) -#define QDMA_CPM4_C2H_CNT_TH_5_ADDR 0xA50 -#define C2H_CNT_TH_5_RSVD_1_MASK GENMASK(31, 8) -#define C2H_CNT_TH_5_THESHOLD_CNT_MASK GENMASK(7, 0) -#define QDMA_CPM4_C2H_CNT_TH_6_ADDR 0xA54 -#define C2H_CNT_TH_6_RSVD_1_MASK GENMASK(31, 8) -#define C2H_CNT_TH_6_THESHOLD_CNT_MASK GENMASK(7, 0) -#define QDMA_CPM4_C2H_CNT_TH_7_ADDR 0xA58 -#define C2H_CNT_TH_7_RSVD_1_MASK GENMASK(31, 8) -#define C2H_CNT_TH_7_THESHOLD_CNT_MASK GENMASK(7, 0) -#define QDMA_CPM4_C2H_CNT_TH_8_ADDR 0xA5C -#define C2H_CNT_TH_8_RSVD_1_MASK GENMASK(31, 8) -#define C2H_CNT_TH_8_THESHOLD_CNT_MASK GENMASK(7, 0) -#define QDMA_CPM4_C2H_CNT_TH_9_ADDR 0xA60 -#define C2H_CNT_TH_9_RSVD_1_MASK GENMASK(31, 8) -#define C2H_CNT_TH_9_THESHOLD_CNT_MASK GENMASK(7, 0) -#define QDMA_CPM4_C2H_CNT_TH_A_ADDR 0xA64 -#define C2H_CNT_TH_A_RSVD_1_MASK GENMASK(31, 8) -#define C2H_CNT_TH_A_THESHOLD_CNT_MASK GENMASK(7, 0) -#define QDMA_CPM4_C2H_CNT_TH_B_ADDR 0xA68 -#define C2H_CNT_TH_B_RSVD_1_MASK GENMASK(31, 8) -#define C2H_CNT_TH_B_THESHOLD_CNT_MASK GENMASK(7, 0) -#define QDMA_CPM4_C2H_CNT_TH_C_ADDR 0xA6C -#define C2H_CNT_TH_C_RSVD_1_MASK GENMASK(31, 8) -#define C2H_CNT_TH_C_THESHOLD_CNT_MASK GENMASK(7, 0) -#define QDMA_CPM4_C2H_CNT_TH_D_ADDR 0xA70 -#define C2H_CNT_TH_D_RSVD_1_MASK GENMASK(31, 8) -#define C2H_CNT_TH_D_THESHOLD_CNT_MASK GENMASK(7, 0) -#define QDMA_CPM4_C2H_CNT_TH_E_ADDR 0xA74 -#define C2H_CNT_TH_E_RSVD_1_MASK GENMASK(31, 8) -#define C2H_CNT_TH_E_THESHOLD_CNT_MASK GENMASK(7, 0) -#define QDMA_CPM4_C2H_CNT_TH_F_ADDR 0xA78 -#define C2H_CNT_TH_F_RSVD_1_MASK GENMASK(31, 8) -#define C2H_CNT_TH_F_THESHOLD_CNT_MASK GENMASK(7, 0) -#define QDMA_CPM4_C2H_CNT_TH_10_ADDR 0xA7C -#define C2H_CNT_TH_10_RSVD_1_MASK GENMASK(31, 8) -#define C2H_CNT_TH_10_THESHOLD_CNT_MASK GENMASK(7, 0) -#define QDMA_CPM4_C2H_QID2VEC_MAP_QID_ADDR 0xA80 -#define C2H_QID2VEC_MAP_QID_RSVD_1_MASK GENMASK(31, 11) -#define C2H_QID2VEC_MAP_QID_QID_MASK GENMASK(10, 0) -#define QDMA_CPM4_C2H_QID2VEC_MAP_ADDR 0xA84 -#define C2H_QID2VEC_MAP_RSVD_1_MASK GENMASK(31, 19) -#define C2H_QID2VEC_MAP_H2C_EN_COAL_MASK BIT(18) -#define C2H_QID2VEC_MAP_H2C_VECTOR_MASK GENMASK(17, 9) -#define C2H_QID2VEC_MAP_C2H_EN_COAL_MASK BIT(8) -#define C2H_QID2VEC_MAP_C2H_VECTOR_MASK GENMASK(7, 0) -#define QDMA_CPM4_C2H_STAT_S_AXIS_C2H_ACCEPTED_ADDR 0xA88 -#define C2H_STAT_S_AXIS_C2H_ACCEPTED_MASK GENMASK(31, 0) -#define QDMA_CPM4_C2H_STAT_S_AXIS_WRB_ACCEPTED_ADDR 0xA8C -#define C2H_STAT_S_AXIS_WRB_ACCEPTED_MASK GENMASK(31, 0) -#define QDMA_CPM4_C2H_STAT_DESC_RSP_PKT_ACCEPTED_ADDR 0xA90 -#define C2H_STAT_DESC_RSP_PKT_ACCEPTED_D_MASK GENMASK(31, 0) -#define QDMA_CPM4_C2H_STAT_AXIS_PKG_CMP_ADDR 0xA94 -#define C2H_STAT_AXIS_PKG_CMP_MASK GENMASK(31, 0) -#define QDMA_CPM4_C2H_STAT_DESC_RSP_ACCEPTED_ADDR 0xA98 -#define C2H_STAT_DESC_RSP_ACCEPTED_D_MASK GENMASK(31, 0) -#define QDMA_CPM4_C2H_STAT_DESC_RSP_CMP_ADDR 0xA9C -#define C2H_STAT_DESC_RSP_CMP_D_MASK GENMASK(31, 0) -#define QDMA_CPM4_C2H_STAT_WRQ_OUT_ADDR 0xAA0 -#define C2H_STAT_WRQ_OUT_MASK GENMASK(31, 0) -#define QDMA_CPM4_C2H_STAT_WPL_REN_ACCEPTED_ADDR 0xAA4 -#define C2H_STAT_WPL_REN_ACCEPTED_MASK GENMASK(31, 0) -#define QDMA_CPM4_C2H_STAT_TOTAL_WRQ_LEN_ADDR 0xAA8 -#define C2H_STAT_TOTAL_WRQ_LEN_MASK GENMASK(31, 0) -#define QDMA_CPM4_C2H_STAT_TOTAL_WPL_LEN_ADDR 0xAAC -#define C2H_STAT_TOTAL_WPL_LEN_MASK GENMASK(31, 0) -#define QDMA_CPM4_C2H_BUF_SZ_0_ADDR 0xAB0 -#define C2H_BUF_SZ_0_SIZE_MASK GENMASK(31, 0) -#define QDMA_CPM4_C2H_BUF_SZ_1_ADDR 0xAB4 -#define C2H_BUF_SZ_1_SIZE_MASK GENMASK(31, 0) -#define QDMA_CPM4_C2H_BUF_SZ_2_ADDR 0xAB8 -#define C2H_BUF_SZ_2_SIZE_MASK GENMASK(31, 0) -#define QDMA_CPM4_C2H_BUF_SZ_3_ADDR 0xABC -#define C2H_BUF_SZ_3_SIZE_MASK GENMASK(31, 0) -#define QDMA_CPM4_C2H_BUF_SZ_4_ADDR 0xAC0 -#define C2H_BUF_SZ_4_SIZE_MASK GENMASK(31, 0) -#define QDMA_CPM4_C2H_BUF_SZ_5_ADDR 0xAC4 -#define C2H_BUF_SZ_5_SIZE_MASK GENMASK(31, 0) -#define QDMA_CPM4_C2H_BUF_SZ_7_ADDR 0XAC8 -#define C2H_BUF_SZ_7_SIZE_MASK GENMASK(31, 0) -#define QDMA_CPM4_C2H_BUF_SZ_8_ADDR 0XACC -#define C2H_BUF_SZ_8_SIZE_MASK GENMASK(31, 0) -#define QDMA_CPM4_C2H_BUF_SZ_9_ADDR 0xAD0 -#define C2H_BUF_SZ_9_SIZE_MASK GENMASK(31, 0) -#define QDMA_CPM4_C2H_BUF_SZ_10_ADDR 0xAD4 -#define C2H_BUF_SZ_10_SIZE_MASK GENMASK(31, 0) -#define QDMA_CPM4_C2H_BUF_SZ_11_ADDR 0xAD8 -#define C2H_BUF_SZ_11_SIZE_MASK GENMASK(31, 0) -#define QDMA_CPM4_C2H_BUF_SZ_12_ADDR 0xAE0 -#define C2H_BUF_SZ_12_SIZE_MASK GENMASK(31, 0) -#define QDMA_CPM4_C2H_BUF_SZ_13_ADDR 0xAE4 -#define C2H_BUF_SZ_13_SIZE_MASK GENMASK(31, 0) -#define QDMA_CPM4_C2H_BUF_SZ_14_ADDR 0xAE8 -#define C2H_BUF_SZ_14_SIZE_MASK GENMASK(31, 0) -#define QDMA_CPM4_C2H_BUF_SZ_15_ADDR 0XAEC -#define C2H_BUF_SZ_15_SIZE_MASK GENMASK(31, 0) -#define QDMA_CPM4_C2H_ERR_STAT_ADDR 0xAF0 -#define C2H_ERR_STAT_RSVD_1_MASK GENMASK(31, 16) -#define C2H_ERR_STAT_WRB_PRTY_ERR_MASK BIT(15) -#define C2H_ERR_STAT_WRB_CIDX_ERR_MASK BIT(14) -#define C2H_ERR_STAT_WRB_QFULL_ERR_MASK BIT(13) -#define C2H_ERR_STAT_WRB_INV_Q_ERR_MASK BIT(12) -#define C2H_ERR_STAT_PORT_ID_BYP_IN_MISMATCH_MASK BIT(11) -#define C2H_ERR_STAT_PORT_ID_CTXT_MISMATCH_MASK BIT(10) -#define C2H_ERR_STAT_ERR_DESC_CNT_MASK BIT(9) -#define C2H_ERR_STAT_RSVD_2_MASK BIT(8) -#define C2H_ERR_STAT_MSI_INT_FAIL_MASK BIT(7) -#define C2H_ERR_STAT_ENG_WPL_DATA_PAR_ERR_MASK BIT(6) -#define C2H_ERR_STAT_RSVD_3_MASK BIT(5) -#define C2H_ERR_STAT_DESC_RSP_ERR_MASK BIT(4) -#define C2H_ERR_STAT_QID_MISMATCH_MASK BIT(3) -#define C2H_ERR_STAT_RSVD_4_MASK BIT(2) -#define C2H_ERR_STAT_LEN_MISMATCH_MASK BIT(1) -#define C2H_ERR_STAT_MTY_MISMATCH_MASK BIT(0) -#define QDMA_CPM4_C2H_ERR_MASK_ADDR 0xAF4 -#define C2H_ERR_EN_MASK GENMASK(31, 0) -#define QDMA_CPM4_C2H_FATAL_ERR_STAT_ADDR 0xAF8 -#define C2H_FATAL_ERR_STAT_RSVD_1_MASK GENMASK(31, 19) -#define C2H_FATAL_ERR_STAT_WPL_DATA_PAR_ERR_MASK BIT(18) -#define C2H_FATAL_ERR_STAT_PLD_FIFO_RAM_RDBE_MASK BIT(17) -#define C2H_FATAL_ERR_STAT_QID_FIFO_RAM_RDBE_MASK BIT(16) -#define C2H_FATAL_ERR_STAT_TUSER_FIFO_RAM_RDBE_MASK BIT(15) -#define C2H_FATAL_ERR_STAT_WRB_COAL_DATA_RAM_RDBE_MASK BIT(14) -#define C2H_FATAL_ERR_STAT_INT_QID2VEC_RAM_RDBE_MASK BIT(13) -#define C2H_FATAL_ERR_STAT_INT_CTXT_RAM_RDBE_MASK BIT(12) -#define C2H_FATAL_ERR_STAT_DESC_REQ_FIFO_RAM_RDBE_MASK BIT(11) -#define C2H_FATAL_ERR_STAT_PFCH_CTXT_RAM_RDBE_MASK BIT(10) -#define C2H_FATAL_ERR_STAT_WRB_CTXT_RAM_RDBE_MASK BIT(9) -#define C2H_FATAL_ERR_STAT_PFCH_LL_RAM_RDBE_MASK BIT(8) -#define C2H_FATAL_ERR_STAT_TIMER_FIFO_RAM_RDBE_MASK GENMASK(7, 4) -#define C2H_FATAL_ERR_STAT_QID_MISMATCH_MASK BIT(3) -#define C2H_FATAL_ERR_STAT_RSVD_2_MASK BIT(2) -#define C2H_FATAL_ERR_STAT_LEN_MISMATCH_MASK BIT(1) -#define C2H_FATAL_ERR_STAT_MTY_MISMATCH_MASK BIT(0) -#define QDMA_CPM4_C2H_FATAL_ERR_MASK_ADDR 0xAFC -#define C2H_FATAL_ERR_C2HEN_MASK GENMASK(31, 0) -#define QDMA_CPM4_C2H_FATAL_ERR_ENABLE_ADDR 0xB00 -#define C2H_FATAL_ERR_ENABLE_RSVD_1_MASK GENMASK(31, 2) -#define C2H_FATAL_ERR_ENABLE_WPL_PAR_INV_MASK BIT(1) -#define C2H_FATAL_ERR_ENABLE_WRQ_DIS_MASK BIT(0) -#define QDMA_CPM4_GLBL_ERR_INT_ADDR 0xB04 -#define GLBL_ERR_INT_RSVD_1_MASK GENMASK(31, 18) -#define GLBL_ERR_INT_ARM_MASK BIT(17) -#define GLBL_ERR_INT_EN_COAL_MASK BIT(16) -#define GLBL_ERR_INT_VEC_MASK GENMASK(15, 8) -#define GLBL_ERR_INT_FUNC_MASK GENMASK(7, 0) -#define QDMA_CPM4_C2H_PFCH_CFG_ADDR 0xB08 -#define C2H_PFCH_CFG_EVT_QCNT_TH_MASK GENMASK(31, 25) -#define C2H_PFCH_CFG_QCNT_MASK GENMASK(24, 16) -#define C2H_PFCH_CFG_NUM_MASK GENMASK(15, 8) -#define C2H_PFCH_CFG_FL_TH_MASK GENMASK(7, 0) -#define QDMA_CPM4_C2H_INT_TIMER_TICK_ADDR 0xB0C -#define C2H_INT_TIMER_TICK_MASK GENMASK(31, 0) -#define QDMA_CPM4_C2H_STAT_DESC_RSP_DROP_ACCEPTED_ADDR 0xB10 -#define C2H_STAT_DESC_RSP_DROP_ACCEPTED_D_MASK GENMASK(31, 0) -#define QDMA_CPM4_C2H_STAT_DESC_RSP_ERR_ACCEPTED_ADDR 0xB14 -#define C2H_STAT_DESC_RSP_ERR_ACCEPTED_D_MASK GENMASK(31, 0) -#define QDMA_CPM4_C2H_STAT_DESC_REQ_ADDR 0xB18 -#define C2H_STAT_DESC_REQ_MASK GENMASK(31, 0) -#define QDMA_CPM4_C2H_STAT_DBG_DMA_ENG_0_ADDR 0xB1C -#define C2H_STAT_DMA_ENG_0_RSVD_1_MASK BIT(31) -#define C2H_STAT_DMA_ENG_0_WRB_FIFO_OUT_CNT_MASK GENMASK(30, 28) -#define C2H_STAT_DMA_ENG_0_QID_FIFO_OUT_CNT_MASK GENMASK(27, 18) -#define C2H_STAT_DMA_ENG_0_PLD_FIFO_OUT_CNT_MASK GENMASK(17, 8) -#define C2H_STAT_DMA_ENG_0_WRQ_FIFO_OUT_CNT_MASK GENMASK(7, 5) -#define C2H_STAT_DMA_ENG_0_WRB_SM_CS_MASK BIT(4) -#define C2H_STAT_DMA_ENG_0_MAIN_SM_CS_MASK GENMASK(3, 0) -#define QDMA_CPM4_C2H_STAT_DBG_DMA_ENG_1_ADDR 0xB20 -#define C2H_STAT_DMA_ENG_1_RSVD_1_MASK BIT(31) -#define C2H_STAT_DMA_ENG_1_DESC_RSP_LAST_MASK BIT(30) -#define C2H_STAT_DMA_ENG_1_PLD_FIFO_IN_CNT_MASK GENMASK(29, 20) -#define C2H_STAT_DMA_ENG_1_PLD_FIFO_OUTPUT_CNT_MASK GENMASK(19, 10) -#define C2H_STAT_DMA_ENG_1_QID_FIFO_IN_CNT_MASK GENMASK(9, 0) -#define QDMA_CPM4_C2H_STAT_DBG_DMA_ENG_2_ADDR 0xB24 -#define C2H_STAT_DMA_ENG_2_RSVD_1_MASK GENMASK(31, 30) -#define C2H_STAT_DMA_ENG_2_WRB_FIFO_IN_CNT_MASK GENMASK(29, 20) -#define C2H_STAT_DMA_ENG_2_WRB_FIFO_OUTPUT_CNT_MASK GENMASK(19, 10) -#define C2H_STAT_DMA_ENG_2_QID_FIFO_OUTPUT_CNT_MASK GENMASK(9, 0) -#define QDMA_CPM4_C2H_STAT_DBG_DMA_ENG_3_ADDR 0xB28 -#define C2H_STAT_DMA_ENG_3_RSVD_1_MASK GENMASK(31, 30) -#define C2H_STAT_DMA_ENG_3_ADDR_4K_SPLIT_CNT_MASK GENMASK(29, 20) -#define C2H_STAT_DMA_ENG_3_WRQ_FIFO_IN_CNT_MASK GENMASK(19, 10) -#define C2H_STAT_DMA_ENG_3_WRQ_FIFO_OUTPUT_CNT_MASK GENMASK(9, 0) -#define QDMA_CPM4_C2H_DBG_PFCH_ERR_CTXT_ADDR 0xB2C -#define C2H_PFCH_ERR_CTXT_RSVD_1_MASK GENMASK(31, 14) -#define C2H_PFCH_ERR_CTXT_ERR_STAT_MASK BIT(13) -#define C2H_PFCH_ERR_CTXT_CMD_WR_MASK BIT(12) -#define C2H_PFCH_ERR_CTXT_QID_MASK GENMASK(11, 1) -#define C2H_PFCH_ERR_CTXT_DONE_MASK BIT(0) -#define QDMA_CPM4_C2H_FIRST_ERR_QID_ADDR 0xB30 -#define C2H_FIRST_ERR_QID_RSVD_1_MASK GENMASK(31, 21) -#define C2H_FIRST_ERR_QID_ERR_STAT_MASK GENMASK(20, 16) -#define C2H_FIRST_ERR_QID_CMD_WR_MASK GENMASK(15, 12) -#define C2H_FIRST_ERR_QID_QID_MASK GENMASK(11, 0) -#define QDMA_CPM4_STAT_NUM_WRB_IN_ADDR 0xB34 -#define STAT_NUM_WRB_IN_RSVD_1_MASK GENMASK(31, 16) -#define STAT_NUM_WRB_IN_WRB_CNT_MASK GENMASK(15, 0) -#define QDMA_CPM4_STAT_NUM_WRB_OUT_ADDR 0xB38 -#define STAT_NUM_WRB_OUT_RSVD_1_MASK GENMASK(31, 16) -#define STAT_NUM_WRB_OUT_WRB_CNT_MASK GENMASK(15, 0) -#define QDMA_CPM4_STAT_NUM_WRB_DRP_ADDR 0xB3C -#define STAT_NUM_WRB_DRP_RSVD_1_MASK GENMASK(31, 16) -#define STAT_NUM_WRB_DRP_WRB_CNT_MASK GENMASK(15, 0) -#define QDMA_CPM4_STAT_NUM_STAT_DESC_OUT_ADDR 0xB40 -#define STAT_NUM_STAT_DESC_OUT_RSVD_1_MASK GENMASK(31, 16) -#define STAT_NUM_STAT_DESC_OUT_CNT_MASK GENMASK(15, 0) -#define QDMA_CPM4_STAT_NUM_DSC_CRDT_SENT_ADDR 0xB44 -#define STAT_NUM_DSC_CRDT_SENT_RSVD_1_MASK GENMASK(31, 16) -#define STAT_NUM_DSC_CRDT_SENT_CNT_MASK GENMASK(15, 0) -#define QDMA_CPM4_STAT_NUM_FCH_DSC_RCVD_ADDR 0xB48 -#define STAT_NUM_FCH_DSC_RCVD_RSVD_1_MASK GENMASK(31, 16) -#define STAT_NUM_FCH_DSC_RCVD_DSC_CNT_MASK GENMASK(15, 0) -#define QDMA_CPM4_STAT_NUM_BYP_DSC_RCVD_ADDR 0xB4C -#define STAT_NUM_BYP_DSC_RCVD_RSVD_1_MASK GENMASK(31, 11) -#define STAT_NUM_BYP_DSC_RCVD_DSC_CNT_MASK GENMASK(10, 0) -#define QDMA_CPM4_C2H_WRB_COAL_CFG_ADDR 0xB50 -#define C2H_WRB_COAL_CFG_MAX_BUF_SZ_MASK GENMASK(31, 26) -#define C2H_WRB_COAL_CFG_TICK_VAL_MASK GENMASK(25, 14) -#define C2H_WRB_COAL_CFG_TICK_CNT_MASK GENMASK(13, 2) -#define C2H_WRB_COAL_CFG_SET_GLB_FLUSH_MASK BIT(1) -#define C2H_WRB_COAL_CFG_DONE_GLB_FLUSH_MASK BIT(0) -#define QDMA_CPM4_C2H_INTR_H2C_REQ_ADDR 0xB54 -#define C2H_INTR_H2C_REQ_RSVD_1_MASK GENMASK(31, 18) -#define C2H_INTR_H2C_REQ_CNT_MASK GENMASK(17, 0) -#define QDMA_CPM4_C2H_INTR_C2H_MM_REQ_ADDR 0xB58 -#define C2H_INTR_C2H_MM_REQ_RSVD_1_MASK GENMASK(31, 18) -#define C2H_INTR_C2H_MM_REQ_CNT_MASK GENMASK(17, 0) -#define QDMA_CPM4_C2H_INTR_ERR_INT_REQ_ADDR 0xB5C -#define C2H_INTR_ERR_INT_REQ_RSVD_1_MASK GENMASK(31, 18) -#define C2H_INTR_ERR_INT_REQ_CNT_MASK GENMASK(17, 0) -#define QDMA_CPM4_C2H_INTR_C2H_ST_REQ_ADDR 0xB60 -#define C2H_INTR_C2H_ST_REQ_RSVD_1_MASK GENMASK(31, 18) -#define C2H_INTR_C2H_ST_REQ_CNT_MASK GENMASK(17, 0) -#define QDMA_CPM4_C2H_INTR_H2C_ERR_C2H_MM_MSIX_ACK_ADDR 0xB64 -#define C2H_INTR_H2C_ERR_C2H_MM_MSIX_ACK_RSVD_1_MASK GENMASK(31, 18) -#define C2H_INTR_H2C_ERR_C2H_MM_MSIX_ACK_CNT_MASK GENMASK(17, 0) -#define QDMA_CPM4_C2H_INTR_H2C_ERR_C2H_MM_MSIX_FAIL_ADDR 0xB68 -#define C2H_INTR_H2C_ERR_C2H_MM_MSIX_FAIL_RSVD_1_MASK GENMASK(31, 18) -#define C2H_INTR_H2C_ERR_C2H_MM_MSIX_FAIL_CNT_MASK GENMASK(17, 0) -#define QDMA_CPM4_C2H_INTR_H2C_ERR_C2H_MM_MSIX_NO_MSIX_ADDR 0xB6C -#define C2H_INTR_H2C_ERR_C2H_MM_MSIX_NO_MSIX_RSVD_1_MASK GENMASK(31, 18) -#define C2H_INTR_H2C_ERR_C2H_MM_MSIX_NO_MSIX_CNT_MASK GENMASK(17, 0) -#define QDMA_CPM4_C2H_INTR_H2C_ERR_C2H_MM_CTXT_INVAL_ADDR 0xB70 -#define C2H_INTR_H2C_ERR_C2H_MM_CTXT_INVAL_RSVD_1_MASK GENMASK(31, 18) -#define C2H_INTR_H2C_ERR_C2H_MM_CTXT_INVAL_CNT_MASK GENMASK(17, 0) -#define QDMA_CPM4_C2H_INTR_C2H_ST_MSIX_ACK_ADDR 0xB74 -#define C2H_INTR_C2H_ST_MSIX_ACK_RSVD_1_MASK GENMASK(31, 18) -#define C2H_INTR_C2H_ST_MSIX_ACK_CNT_MASK GENMASK(17, 0) -#define QDMA_CPM4_C2H_INTR_C2H_ST_MSIX_FAIL_ADDR 0xB78 -#define C2H_INTR_C2H_ST_MSIX_FAIL_RSVD_1_MASK GENMASK(31, 18) -#define C2H_INTR_C2H_ST_MSIX_FAIL_CNT_MASK GENMASK(17, 0) -#define QDMA_CPM4_C2H_INTR_C2H_ST_NO_MSIX_ADDR 0xB7C -#define C2H_INTR_C2H_ST_NO_MSIX_RSVD_1_MASK GENMASK(31, 18) -#define C2H_INTR_C2H_ST_NO_MSIX_CNT_MASK GENMASK(17, 0) -#define QDMA_CPM4_C2H_INTR_C2H_ST_CTXT_INVAL_ADDR 0xB80 -#define C2H_INTR_C2H_ST_CTXT_INVAL_RSVD_1_MASK GENMASK(31, 18) -#define C2H_INTR_C2H_ST_CTXT_INVAL_CNT_MASK GENMASK(17, 0) -#define QDMA_CPM4_C2H_STAT_WR_CMP_ADDR 0xB84 -#define C2H_STAT_WR_CMP_RSVD_1_MASK GENMASK(31, 18) -#define C2H_STAT_WR_CMP_CNT_MASK GENMASK(17, 0) -#define QDMA_CPM4_C2H_STAT_DBG_DMA_ENG_4_ADDR 0xB88 -#define C2H_STAT_DMA_ENG_4_TUSER_FIFO_OUT_VLD_MASK BIT(31) -#define C2H_STAT_DMA_ENG_4_WRB_FIFO_IN_RDY_MASK BIT(30) -#define C2H_STAT_DMA_ENG_4_TUSER_FIFO_IN_CNT_MASK GENMASK(29, 20) -#define C2H_STAT_DMA_ENG_4_TUSER_FIFO_OUTPUT_CNT_MASK GENMASK(19, 10) -#define C2H_STAT_DMA_ENG_4_TUSER_FIFO_OUT_CNT_MASK GENMASK(9, 0) -#define QDMA_CPM4_C2H_STAT_DBG_DMA_ENG_5_ADDR 0xB8C -#define C2H_STAT_DMA_ENG_5_RSVD_1_MASK GENMASK(31, 25) -#define C2H_STAT_DMA_ENG_5_TUSER_COMB_OUT_VLD_MASK BIT(24) -#define C2H_STAT_DMA_ENG_5_TUSER_FIFO_IN_RDY_MASK BIT(23) -#define C2H_STAT_DMA_ENG_5_TUSER_COMB_IN_CNT_MASK GENMASK(22, 13) -#define C2H_STAT_DMA_ENG_5_TUSE_COMB_OUTPUT_CNT_MASK GENMASK(12, 3) -#define C2H_STAT_DMA_ENG_5_TUSER_COMB_CNT_MASK GENMASK(2, 0) -#define QDMA_CPM4_C2H_DBG_PFCH_QID_ADDR 0xB90 -#define C2H_PFCH_QID_RSVD_1_MASK GENMASK(31, 15) -#define C2H_PFCH_QID_ERR_CTXT_MASK BIT(14) -#define C2H_PFCH_QID_TARGET_MASK GENMASK(13, 11) -#define C2H_PFCH_QID_QID_OR_TAG_MASK GENMASK(10, 0) -#define QDMA_CPM4_C2H_DBG_PFCH_ADDR 0xB94 -#define C2H_PFCH_DATA_MASK GENMASK(31, 0) -#define QDMA_CPM4_C2H_INT_DBG_ADDR 0xB98 -#define C2H_INT_RSVD_1_MASK GENMASK(31, 8) -#define C2H_INT_INT_COAL_SM_MASK GENMASK(7, 4) -#define C2H_INT_INT_SM_MASK GENMASK(3, 0) -#define QDMA_CPM4_C2H_STAT_IMM_ACCEPTED_ADDR 0xB9C -#define C2H_STAT_IMM_ACCEPTED_RSVD_1_MASK GENMASK(31, 18) -#define C2H_STAT_IMM_ACCEPTED_CNT_MASK GENMASK(17, 0) -#define QDMA_CPM4_C2H_STAT_MARKER_ACCEPTED_ADDR 0xBA0 -#define C2H_STAT_MARKER_ACCEPTED_RSVD_1_MASK GENMASK(31, 18) -#define C2H_STAT_MARKER_ACCEPTED_CNT_MASK GENMASK(17, 0) -#define QDMA_CPM4_C2H_STAT_DISABLE_CMP_ACCEPTED_ADDR 0xBA4 -#define C2H_STAT_DISABLE_CMP_ACCEPTED_RSVD_1_MASK GENMASK(31, 18) -#define C2H_STAT_DISABLE_CMP_ACCEPTED_CNT_MASK GENMASK(17, 0) -#define QDMA_CPM4_C2H_PLD_FIFO_CRDT_CNT_ADDR 0xBA8 -#define C2H_PLD_FIFO_CRDT_CNT_RSVD_1_MASK GENMASK(31, 18) -#define C2H_PLD_FIFO_CRDT_CNT_CNT_MASK GENMASK(17, 0) -#define QDMA_CPM4_H2C_ERR_STAT_ADDR 0xE00 -#define H2C_ERR_STAT_RSVD_1_MASK GENMASK(31, 5) -#define H2C_ERR_STAT_SBE_MASK BIT(4) -#define H2C_ERR_STAT_DBE_MASK BIT(3) -#define H2C_ERR_STAT_NO_DMA_DS_MASK BIT(2) -#define H2C_ERR_STAT_SDI_MRKR_REQ_MOP_ERR_MASK BIT(1) -#define H2C_ERR_STAT_ZERO_LEN_DS_MASK BIT(0) -#define QDMA_CPM4_H2C_ERR_MASK_ADDR 0xE04 -#define H2C_ERR_EN_MASK GENMASK(31, 0) -#define QDMA_CPM4_H2C_FIRST_ERR_QID_ADDR 0xE08 -#define H2C_FIRST_ERR_QID_RSVD_1_MASK GENMASK(31, 20) -#define H2C_FIRST_ERR_QID_ERR_TYPE_MASK GENMASK(19, 16) -#define H2C_FIRST_ERR_QID_RSVD_2_MASK GENMASK(15, 12) -#define H2C_FIRST_ERR_QID_QID_MASK GENMASK(11, 0) -#define QDMA_CPM4_H2C_DBG_REG0_ADDR 0xE0C -#define H2C_REG0_NUM_DSC_RCVD_MASK GENMASK(31, 16) -#define H2C_REG0_NUM_WRB_SENT_MASK GENMASK(15, 0) -#define QDMA_CPM4_H2C_DBG_REG1_ADDR 0xE10 -#define H2C_REG1_NUM_REQ_SENT_MASK GENMASK(31, 16) -#define H2C_REG1_NUM_CMP_SENT_MASK GENMASK(15, 0) -#define QDMA_CPM4_H2C_DBG_REG2_ADDR 0xE14 -#define H2C_REG2_RSVD_1_MASK GENMASK(31, 16) -#define H2C_REG2_NUM_ERR_DSC_RCVD_MASK GENMASK(15, 0) -#define QDMA_CPM4_H2C_DBG_REG3_ADDR 0xE18 -#define H2C_REG3_MASK BIT(31) -#define H2C_REG3_DSCO_FIFO_EMPTY_MASK BIT(30) -#define H2C_REG3_DSCO_FIFO_FULL_MASK BIT(29) -#define H2C_REG3_CUR_RC_STATE_MASK GENMASK(28, 26) -#define H2C_REG3_RDREQ_LINES_MASK GENMASK(25, 16) -#define H2C_REG3_RDATA_LINES_AVAIL_MASK GENMASK(15, 6) -#define H2C_REG3_PEND_FIFO_EMPTY_MASK BIT(5) -#define H2C_REG3_PEND_FIFO_FULL_MASK BIT(4) -#define H2C_REG3_CUR_RQ_STATE_MASK GENMASK(3, 2) -#define H2C_REG3_DSCI_FIFO_FULL_MASK BIT(1) -#define H2C_REG3_DSCI_FIFO_EMPTY_MASK BIT(0) -#define QDMA_CPM4_H2C_DBG_REG4_ADDR 0xE1C -#define H2C_REG4_RDREQ_ADDR_MASK GENMASK(31, 0) -#define QDMA_CPM4_H2C_FATAL_ERR_EN_ADDR 0xE20 -#define H2C_FATAL_ERR_EN_RSVD_1_MASK GENMASK(31, 1) -#define H2C_FATAL_ERR_EN_H2C_MASK BIT(0) -#define QDMA_CPM4_C2H_CHANNEL_CTL_ADDR 0x1004 -#define C2H_CHANNEL_CTL_RSVD_1_MASK GENMASK(31, 1) -#define C2H_CHANNEL_CTL_RUN_MASK BIT(0) -#define QDMA_CPM4_C2H_CHANNEL_CTL_1_ADDR 0x1008 -#define C2H_CHANNEL_CTL_1_RUN_MASK GENMASK(31, 1) -#define C2H_CHANNEL_CTL_1_RUN_1_MASK BIT(0) -#define QDMA_CPM4_C2H_MM_STATUS_ADDR 0x1040 -#define C2H_MM_STATUS_RSVD_1_MASK GENMASK(31, 1) -#define C2H_MM_STATUS_RUN_MASK BIT(0) -#define QDMA_CPM4_C2H_CHANNEL_CMPL_DESC_CNT_ADDR 0x1048 -#define C2H_CHANNEL_CMPL_DESC_CNT_C2H_CO_MASK GENMASK(31, 0) -#define QDMA_CPM4_C2H_MM_ERR_CODE_ENABLE_MASK_ADDR 0x1054 -#define C2H_MM_ERR_CODE_ENABLE_RSVD_1_MASK BIT(31) -#define C2H_MM_ERR_CODE_ENABLE_WR_UC_RAM_MASK BIT(30) -#define C2H_MM_ERR_CODE_ENABLE_WR_UR_MASK BIT(29) -#define C2H_MM_ERR_CODE_ENABLE_WR_FLR_MASK BIT(28) -#define C2H_MM_ERR_CODE_ENABLE_RSVD_2_MASK GENMASK(27, 2) -#define C2H_MM_ERR_CODE_ENABLE_RD_SLV_ERR_MASK BIT(1) -#define C2H_MM_ERR_CODE_ENABLE_WR_SLV_ERR_MASK BIT(0) -#define QDMA_CPM4_C2H_MM_ERR_CODE_ADDR 0x1058 -#define C2H_MM_ERR_CODE_RSVD_1_MASK GENMASK(31, 18) -#define C2H_MM_ERR_CODE_VALID_MASK BIT(17) -#define C2H_MM_ERR_CODE_RDWR_MASK BIT(16) -#define C2H_MM_ERR_CODE_MASK GENMASK(4, 0) -#define QDMA_CPM4_C2H_MM_ERR_INFO_ADDR 0x105C -#define C2H_MM_ERR_INFO_RSVD_1_MASK GENMASK(31, 29) -#define C2H_MM_ERR_INFO_QID_MASK GENMASK(28, 17) -#define C2H_MM_ERR_INFO_DIR_MASK BIT(16) -#define C2H_MM_ERR_INFO_CIDX_MASK GENMASK(15, 0) -#define QDMA_CPM4_C2H_MM_PERF_MON_CTL_ADDR 0x10C0 -#define C2H_MM_PERF_MON_CTL_RSVD_1_MASK GENMASK(31, 4) -#define C2H_MM_PERF_MON_CTL_IMM_START_MASK BIT(3) -#define C2H_MM_PERF_MON_CTL_RUN_START_MASK BIT(2) -#define C2H_MM_PERF_MON_CTL_IMM_CLEAR_MASK BIT(1) -#define C2H_MM_PERF_MON_CTL_RUN_CLEAR_MASK BIT(0) -#define QDMA_CPM4_C2H_MM_PERF_MON_CYCLE_CNT0_ADDR 0x10C4 -#define C2H_MM_PERF_MON_CYCLE_CNT0_CYC_CNT_MASK GENMASK(31, 0) -#define QDMA_CPM4_C2H_MM_PERF_MON_CYCLE_CNT1_ADDR 0x10C8 -#define C2H_MM_PERF_MON_CYCLE_CNT1_RSVD_1_MASK GENMASK(31, 10) -#define C2H_MM_PERF_MON_CYCLE_CNT1_CYC_CNT_MASK GENMASK(9, 0) -#define QDMA_CPM4_C2H_MM_PERF_MON_DATA_CNT0_ADDR 0x10CC -#define C2H_MM_PERF_MON_DATA_CNT0_DCNT_MASK GENMASK(31, 0) -#define QDMA_CPM4_C2H_MM_PERF_MON_DATA_CNT1_ADDR 0x10D0 -#define C2H_MM_PERF_MON_DATA_CNT1_RSVD_1_MASK GENMASK(31, 10) -#define C2H_MM_PERF_MON_DATA_CNT1_DCNT_MASK GENMASK(9, 0) -#define QDMA_CPM4_C2H_MM_DBG_ADDR 0x10E8 -#define C2H_MM_RSVD_1_MASK GENMASK(31, 24) -#define C2H_MM_RRQ_ENTRIES_MASK GENMASK(23, 17) -#define C2H_MM_DAT_FIFO_SPC_MASK GENMASK(16, 7) -#define C2H_MM_RD_STALL_MASK BIT(6) -#define C2H_MM_RRQ_FIFO_FI_MASK BIT(5) -#define C2H_MM_WR_STALL_MASK BIT(4) -#define C2H_MM_WRQ_FIFO_FI_MASK BIT(3) -#define C2H_MM_WBK_STALL_MASK BIT(2) -#define C2H_MM_DSC_FIFO_EP_MASK BIT(1) -#define C2H_MM_DSC_FIFO_FL_MASK BIT(0) -#define QDMA_CPM4_H2C_CHANNEL_CTL_ADDR 0x1204 -#define H2C_CHANNEL_CTL_RSVD_1_MASK GENMASK(31, 1) -#define H2C_CHANNEL_CTL_RUN_MASK BIT(0) -#define QDMA_CPM4_H2C_CHANNEL_CTL_1_ADDR 0x1208 -#define H2C_CHANNEL_CTL_1_RUN_MASK BIT(0) -#define QDMA_CPM4_H2C_CHANNEL_CTL_2_ADDR 0x120C -#define H2C_CHANNEL_CTL_2_RUN_MASK BIT(0) -#define QDMA_CPM4_H2C_MM_STATUS_ADDR 0x1240 -#define H2C_MM_STATUS_RSVD_1_MASK GENMASK(31, 1) -#define H2C_MM_STATUS_RUN_MASK BIT(0) -#define QDMA_CPM4_H2C_CHANNEL_CMPL_DESC_CNT_ADDR 0x1248 -#define H2C_CHANNEL_CMPL_DESC_CNT_H2C_CO_MASK GENMASK(31, 0) -#define QDMA_CPM4_H2C_MM_ERR_CODE_ENABLE_MASK_ADDR 0x1254 -#define H2C_MM_ERR_CODE_ENABLE_RSVD_1_MASK GENMASK(31, 30) -#define H2C_MM_ERR_CODE_ENABLE_WR_SLV_ERR_MASK BIT(29) -#define H2C_MM_ERR_CODE_ENABLE_WR_DEC_ERR_MASK BIT(28) -#define H2C_MM_ERR_CODE_ENABLE_RSVD_2_MASK GENMASK(27, 23) -#define H2C_MM_ERR_CODE_ENABLE_RD_RQ_DIS_ERR_MASK BIT(22) -#define H2C_MM_ERR_CODE_ENABLE_RSVD_3_MASK GENMASK(21, 17) -#define H2C_MM_ERR_CODE_ENABLE_RD_DAT_POISON_ERR_MASK BIT(16) -#define H2C_MM_ERR_CODE_ENABLE_RSVD_4_MASK GENMASK(15, 9) -#define H2C_MM_ERR_CODE_ENABLE_RD_FLR_ERR_MASK BIT(8) -#define H2C_MM_ERR_CODE_ENABLE_RSVD_5_MASK GENMASK(7, 6) -#define H2C_MM_ERR_CODE_ENABLE_RD_HDR_ADR_ERR_MASK BIT(5) -#define H2C_MM_ERR_CODE_ENABLE_RD_HDR_PARA_MASK BIT(4) -#define H2C_MM_ERR_CODE_ENABLE_RD_HDR_BYTE_ERR_MASK BIT(3) -#define H2C_MM_ERR_CODE_ENABLE_RD_UR_CA_MASK BIT(2) -#define H2C_MM_ERR_CODE_ENABLE_RD_HRD_POISON_ERR_MASK BIT(1) -#define H2C_MM_ERR_CODE_ENABLE_RSVD_6_MASK BIT(0) -#define QDMA_CPM4_H2C_MM_ERR_CODE_ADDR 0x1258 -#define H2C_MM_ERR_CODE_RSVD_1_MASK GENMASK(31, 18) -#define H2C_MM_ERR_CODE_VALID_MASK BIT(17) -#define H2C_MM_ERR_CODE_RDWR_MASK BIT(16) -#define H2C_MM_ERR_CODE_MASK GENMASK(4, 0) -#define QDMA_CPM4_H2C_MM_ERR_INFO_ADDR 0x125C -#define H2C_MM_ERR_INFO_RSVD_1_MASK GENMASK(31, 29) -#define H2C_MM_ERR_INFO_QID_MASK GENMASK(28, 17) -#define H2C_MM_ERR_INFO_DIR_MASK BIT(16) -#define H2C_MM_ERR_INFO_CIDX_MASK GENMASK(15, 0) -#define QDMA_CPM4_H2C_MM_PERF_MON_CTL_ADDR 0x12C0 -#define H2C_MM_PERF_MON_CTL_RSVD_1_MASK GENMASK(31, 4) -#define H2C_MM_PERF_MON_CTL_IMM_START_MASK BIT(3) -#define H2C_MM_PERF_MON_CTL_RUN_START_MASK BIT(2) -#define H2C_MM_PERF_MON_CTL_IMM_CLEAR_MASK BIT(1) -#define H2C_MM_PERF_MON_CTL_RUN_CLEAR_MASK BIT(0) -#define QDMA_CPM4_H2C_MM_PERF_MON_CYCLE_CNT0_ADDR 0x12C4 -#define H2C_MM_PERF_MON_CYCLE_CNT0_CYC_CNT_MASK GENMASK(31, 0) -#define QDMA_CPM4_H2C_MM_PERF_MON_CYCLE_CNT1_ADDR 0x12C8 -#define H2C_MM_PERF_MON_CYCLE_CNT1_RSVD_1_MASK GENMASK(31, 10) -#define H2C_MM_PERF_MON_CYCLE_CNT1_CYC_CNT_MASK GENMASK(9, 0) -#define QDMA_CPM4_H2C_MM_PERF_MON_DATA_CNT0_ADDR 0x12CC -#define H2C_MM_PERF_MON_DATA_CNT0_DCNT_MASK GENMASK(31, 0) -#define QDMA_CPM4_H2C_MM_PERF_MON_DATA_CNT1_ADDR 0x12D0 -#define H2C_MM_PERF_MON_DATA_CNT1_RSVD_1_MASK GENMASK(31, 10) -#define H2C_MM_PERF_MON_DATA_CNT1_DCNT_MASK GENMASK(9, 0) -#define QDMA_CPM4_H2C_MM_DBG_ADDR 0x12E8 -#define H2C_MM_RSVD_1_MASK GENMASK(31, 24) -#define H2C_MM_RRQ_ENTRIES_MASK GENMASK(23, 17) -#define H2C_MM_DAT_FIFO_SPC_MASK GENMASK(16, 7) -#define H2C_MM_RD_STALL_MASK BIT(6) -#define H2C_MM_RRQ_FIFO_FI_MASK BIT(5) -#define H2C_MM_WR_STALL_MASK BIT(4) -#define H2C_MM_WRQ_FIFO_FI_MASK BIT(3) -#define H2C_MM_WBK_STALL_MASK BIT(2) -#define H2C_MM_DSC_FIFO_EP_MASK BIT(1) -#define H2C_MM_DSC_FIFO_FL_MASK BIT(0) -#define QDMA_CPM4_FUNC_STATUS_REG_ADDR 0x2400 -#define FUNC_STATUS_REG_RSVD_1_MASK GENMASK(31, 12) -#define FUNC_STATUS_REG_CUR_SRC_FN_MASK GENMASK(11, 4) -#define FUNC_STATUS_REG_ACK_MASK BIT(2) -#define FUNC_STATUS_REG_O_MSG_MASK BIT(1) -#define FUNC_STATUS_REG_I_MSG_MASK BIT(0) -#define QDMA_CPM4_FUNC_CMD_REG_ADDR 0x2404 -#define FUNC_CMD_REG_RSVD_1_MASK GENMASK(31, 3) -#define FUNC_CMD_REG_RSVD_2_MASK BIT(2) -#define FUNC_CMD_REG_MSG_RCV_MASK BIT(1) -#define FUNC_CMD_REG_MSG_SENT_MASK BIT(0) -#define QDMA_CPM4_FUNC_INTERRUPT_VECTOR_REG_ADDR 0x2408 -#define FUNC_INTERRUPT_VECTOR_REG_RSVD_1_MASK GENMASK(31, 5) -#define FUNC_INTERRUPT_VECTOR_REG_IN_MASK GENMASK(4, 0) -#define QDMA_CPM4_TARGET_FUNC_REG_ADDR 0x240C -#define TARGET_FUNC_REG_RSVD_1_MASK GENMASK(31, 8) -#define TARGET_FUNC_REG_N_ID_MASK GENMASK(7, 0) -#define QDMA_CPM4_FUNC_INTERRUPT_CTL_REG_ADDR 0x2410 -#define FUNC_INTERRUPT_CTL_REG_RSVD_1_MASK GENMASK(31, 1) -#define FUNC_INTERRUPT_CTL_REG_INT_EN_MASK BIT(0) -#define SW_IND_CTXT_DATA_W3_DSC_BASE_H_MASK GENMASK(31, 0) -#define SW_IND_CTXT_DATA_W2_DSC_BASE_L_MASK GENMASK(31, 0) -#define SW_IND_CTXT_DATA_W1_IS_MM_MASK BIT(31) -#define SW_IND_CTXT_DATA_W1_MRKR_DIS_MASK BIT(30) -#define SW_IND_CTXT_DATA_W1_IRQ_REQ_MASK BIT(29) -#define SW_IND_CTXT_DATA_W1_ERR_WB_SENT_MASK BIT(28) -#define SW_IND_CTXT_DATA_W1_ERR_MASK GENMASK(27, 26) -#define SW_IND_CTXT_DATA_W1_IRQ_NO_LAST_MASK BIT(25) -#define SW_IND_CTXT_DATA_W1_PORT_ID_MASK GENMASK(24, 22) -#define SW_IND_CTXT_DATA_W1_IRQ_EN_MASK BIT(21) -#define SW_IND_CTXT_DATA_W1_WBK_EN_MASK BIT(20) -#define SW_IND_CTXT_DATA_W1_MM_CHN_MASK BIT(19) -#define SW_IND_CTXT_DATA_W1_BYPASS_MASK BIT(18) -#define SW_IND_CTXT_DATA_W1_DSC_SZ_MASK GENMASK(17, 16) -#define SW_IND_CTXT_DATA_W1_RNG_SZ_MASK GENMASK(15, 12) -#define SW_IND_CTXT_DATA_W1_FNC_ID_MASK GENMASK(11, 4) -#define SW_IND_CTXT_DATA_W1_WBI_INTVL_EN_MASK BIT(3) -#define SW_IND_CTXT_DATA_W1_WBI_CHK_MASK BIT(2) -#define SW_IND_CTXT_DATA_W1_FCRD_EN_MASK BIT(1) -#define SW_IND_CTXT_DATA_W1_QEN_MASK BIT(0) -#define SW_IND_CTXT_DATA_W0_RSV_MASK GENMASK(31, 17) -#define SW_IND_CTXT_DATA_W0_IRQ_ARM_MASK BIT(16) -#define SW_IND_CTXT_DATA_W0_PIDX_MASK GENMASK(15, 0) -#define HW_IND_CTXT_DATA_W1_RSVD_MASK GENMASK(15, 11) -#define HW_IND_CTXT_DATA_W1_FETCH_PND_MASK BIT(10) -#define HW_IND_CTXT_DATA_W1_IDL_STP_B_MASK BIT(9) -#define HW_IND_CTXT_DATA_W1_DSC_PND_MASK BIT(8) -#define HW_IND_CTXT_DATA_W1_RSVD_1_MASK GENMASK(7, 0) -#define HW_IND_CTXT_DATA_W0_CRD_USE_MASK GENMASK(31, 16) -#define HW_IND_CTXT_DATA_W0_CIDX_MASK GENMASK(15, 0) -#define CRED_CTXT_DATA_W0_RSVD_1_MASK GENMASK(31, 16) -#define CRED_CTXT_DATA_W0_CREDT_MASK GENMASK(15, 0) -#define PREFETCH_CTXT_DATA_W1_VALID_MASK BIT(13) -#define PREFETCH_CTXT_DATA_W1_SW_CRDT_H_MASK GENMASK(12, 0) -#define PREFETCH_CTXT_DATA_W0_SW_CRDT_L_MASK GENMASK(31, 29) -#define PREFETCH_CTXT_DATA_W0_PFCH_MASK BIT(28) -#define PREFETCH_CTXT_DATA_W0_PFCH_EN_MASK BIT(27) -#define PREFETCH_CTXT_DATA_W0_ERR_MASK BIT(26) -#define PREFETCH_CTXT_DATA_W0_RSVD_MASK GENMASK(25, 8) -#define PREFETCH_CTXT_DATA_W0_PORT_ID_MASK GENMASK(7, 5) -#define PREFETCH_CTXT_DATA_W0_BUF_SIZE_IDX_MASK GENMASK(4, 1) -#define PREFETCH_CTXT_DATA_W0_BYPASS_MASK BIT(0) -#define CMPL_CTXT_DATA_W3_RSVD_MASK GENMASK(31, 30) -#define CMPL_CTXT_DATA_W3_FULL_UPD_MASK BIT(29) -#define CMPL_CTXT_DATA_W3_TIMER_RUNNING_MASK BIT(28) -#define CMPL_CTXT_DATA_W3_USER_TRIG_PEND_MASK BIT(27) -#define CMPL_CTXT_DATA_W3_ERR_MASK GENMASK(26, 25) -#define CMPL_CTXT_DATA_W3_VALID_MASK BIT(24) -#define CMPL_CTXT_DATA_W3_CIDX_MASK GENMASK(23, 8) -#define CMPL_CTXT_DATA_W3_PIDX_H_MASK GENMASK(7, 0) -#define CMPL_CTXT_DATA_W2_PIDX_L_MASK GENMASK(31, 24) -#define CMPL_CTXT_DATA_W2_DESC_SIZE_MASK GENMASK(23, 22) -#define CMPL_CTXT_DATA_W2_BADDR_64_H_MASK GENMASK(21, 0) -#define CMPL_CTXT_DATA_W1_BADDR_64_M_MASK GENMASK(31, 0) -#define CMPL_CTXT_DATA_W0_BADDR_64_L_MASK GENMASK(31, 28) -#define CMPL_CTXT_DATA_W0_QSIZE_IDX_MASK GENMASK(27, 24) -#define CMPL_CTXT_DATA_W0_COLOR_MASK BIT(23) -#define CMPL_CTXT_DATA_W0_INT_ST_MASK GENMASK(22, 21) -#define CMPL_CTXT_DATA_W0_TIMER_IDX_MASK GENMASK(20, 17) -#define CMPL_CTXT_DATA_W0_CNTER_IDX_MASK GENMASK(16, 13) -#define CMPL_CTXT_DATA_W0_FNC_ID_MASK GENMASK(12, 5) -#define CMPL_CTXT_DATA_W0_TRIG_MODE_MASK GENMASK(4, 2) -#define CMPL_CTXT_DATA_W0_EN_INT_MASK BIT(1) -#define CMPL_CTXT_DATA_W0_EN_STAT_DESC_MASK BIT(0) -#define INTR_CTXT_DATA_W2_PIDX_MASK GENMASK(11, 0) -#define INTR_CTXT_DATA_W1_PAGE_SIZE_MASK GENMASK(31, 29) -#define INTR_CTXT_DATA_W1_BADDR_4K_H_MASK GENMASK(28, 0) -#define INTR_CTXT_DATA_W0_BADDR_4K_L_MASK GENMASK(31, 9) -#define INTR_CTXT_DATA_W0_COLOR_MASK BIT(8) -#define INTR_CTXT_DATA_W0_INT_ST_MASK BIT(7) -#define INTR_CTXT_DATA_W0_RSVD_MASK BIT(6) -#define INTR_CTXT_DATA_W0_VEC_MASK GENMASK(5, 1) -#define INTR_CTXT_DATA_W0_VALID_MASK BIT(0) - -#ifdef __cplusplus -} -#endif - -#endif - diff --git a/QDMA/DPDK/drivers/net/qdma/qdma_access/qdma_cpm4_access/qdma_cpm4_reg_dump.c b/QDMA/DPDK/drivers/net/qdma/qdma_access/qdma_cpm4_access/qdma_cpm4_reg_dump.c deleted file mode 100755 index 2955d7a95..000000000 --- a/QDMA/DPDK/drivers/net/qdma/qdma_access/qdma_cpm4_access/qdma_cpm4_reg_dump.c +++ /dev/null @@ -1,8029 +0,0 @@ -/* - * Copyright (c) 2019-2022, Xilinx, Inc. All rights reserved. - * Copyright (c) 2022, Advanced Micro Devices, Inc. All rights reserved. - * - * BSD LICENSE - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * * Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include "qdma_cpm4_reg.h" -#include "qdma_reg_dump.h" - -#ifdef ENABLE_WPP_TRACING -#include "qdma_cpm4_reg_dump.tmh" -#endif - - -static struct regfield_info - cfg_blk_identifier_field_info[] = { - {"CFG_BLK_IDENTIFIER", - CFG_BLK_IDENTIFIER_MASK}, - {"CFG_BLK_IDENTIFIER_1", - CFG_BLK_IDENTIFIER_1_MASK}, - {"CFG_BLK_IDENTIFIER_RSVD_1", - CFG_BLK_IDENTIFIER_RSVD_1_MASK}, - {"CFG_BLK_IDENTIFIER_VERSION", - CFG_BLK_IDENTIFIER_VERSION_MASK}, -}; - - -static struct regfield_info - cfg_blk_busdev_field_info[] = { - {"CFG_BLK_BUSDEV_BDF", - CFG_BLK_BUSDEV_BDF_MASK}, -}; - - -static struct regfield_info - cfg_blk_pcie_max_pld_size_field_info[] = { - {"CFG_BLK_PCIE_MAX_PLD_SIZE", - CFG_BLK_PCIE_MAX_PLD_SIZE_MASK}, -}; - - -static struct regfield_info - cfg_blk_pcie_max_read_req_size_field_info[] = { - {"CFG_BLK_PCIE_MAX_READ_REQ_SIZE", - CFG_BLK_PCIE_MAX_READ_REQ_SIZE_MASK}, -}; - - -static struct regfield_info - cfg_blk_system_id_field_info[] = { - {"CFG_BLK_SYSTEM_ID", - CFG_BLK_SYSTEM_ID_MASK}, -}; - - -static struct regfield_info - cfg_blk_msi_enable_field_info[] = { - {"CFG_BLK_MSI_ENABLE_3", - CFG_BLK_MSI_ENABLE_3_MASK}, - {"CFG_BLK_MSI_ENABLE_MSIX3", - CFG_BLK_MSI_ENABLE_MSIX3_MASK}, - {"CFG_BLK_MSI_ENABLE_2", - CFG_BLK_MSI_ENABLE_2_MASK}, - {"CFG_BLK_MSI_ENABLE_MSIX2", - CFG_BLK_MSI_ENABLE_MSIX2_MASK}, - {"CFG_BLK_MSI_ENABLE_1", - CFG_BLK_MSI_ENABLE_1_MASK}, - {"CFG_BLK_MSI_ENABLE_MSIX1", - CFG_BLK_MSI_ENABLE_MSIX1_MASK}, - {"CFG_BLK_MSI_ENABLE_0", - CFG_BLK_MSI_ENABLE_0_MASK}, - {"CFG_BLK_MSI_ENABLE_MSIX0", - CFG_BLK_MSI_ENABLE_MSIX0_MASK}, -}; - - -static struct regfield_info - cfg_pcie_data_width_field_info[] = { - {"CFG_PCIE_DATA_WIDTH_DATAPATH", - CFG_PCIE_DATA_WIDTH_DATAPATH_MASK}, -}; - - -static struct regfield_info - cfg_pcie_ctl_field_info[] = { - {"CFG_PCIE_CTL_RRQ_DISABLE", - CFG_PCIE_CTL_RRQ_DISABLE_MASK}, - {"CFG_PCIE_CTL_RELAXED_ORDERING", - CFG_PCIE_CTL_RELAXED_ORDERING_MASK}, -}; - - -static struct regfield_info - cfg_axi_user_max_pld_size_field_info[] = { - {"CFG_AXI_USER_MAX_PLD_SIZE_ISSUED", - CFG_AXI_USER_MAX_PLD_SIZE_ISSUED_MASK}, - {"CFG_AXI_USER_MAX_PLD_SIZE_PROG", - CFG_AXI_USER_MAX_PLD_SIZE_PROG_MASK}, -}; - - -static struct regfield_info - cfg_axi_user_max_read_req_size_field_info[] = { - {"CFG_AXI_USER_MAX_READ_REQ_SIZE_USISSUED", - CFG_AXI_USER_MAX_READ_REQ_SIZE_USISSUED_MASK}, - {"CFG_AXI_USER_MAX_READ_REQ_SIZE_USPROG", - CFG_AXI_USER_MAX_READ_REQ_SIZE_USPROG_MASK}, -}; - - -static struct regfield_info - cfg_blk_misc_ctl_field_info[] = { - {"CFG_BLK_MISC_CTL_NUM_TAG", - CFG_BLK_MISC_CTL_NUM_TAG_MASK}, - {"CFG_BLK_MISC_CTL_RQ_METERING_MULTIPLIER", - CFG_BLK_MISC_CTL_RQ_METERING_MULTIPLIER_MASK}, -}; - - -static struct regfield_info - cfg_blk_scratch_0_field_info[] = { - {"CFG_BLK_SCRATCH_0", - CFG_BLK_SCRATCH_0_MASK}, -}; - - -static struct regfield_info - cfg_blk_scratch_1_field_info[] = { - {"CFG_BLK_SCRATCH_1", - CFG_BLK_SCRATCH_1_MASK}, -}; - - -static struct regfield_info - cfg_blk_scratch_2_field_info[] = { - {"CFG_BLK_SCRATCH_2", - CFG_BLK_SCRATCH_2_MASK}, -}; - - -static struct regfield_info - cfg_blk_scratch_3_field_info[] = { - {"CFG_BLK_SCRATCH_3", - CFG_BLK_SCRATCH_3_MASK}, -}; - - -static struct regfield_info - cfg_blk_scratch_4_field_info[] = { - {"CFG_BLK_SCRATCH_4", - CFG_BLK_SCRATCH_4_MASK}, -}; - - -static struct regfield_info - cfg_blk_scratch_5_field_info[] = { - {"CFG_BLK_SCRATCH_5", - CFG_BLK_SCRATCH_5_MASK}, -}; - - -static struct regfield_info - cfg_blk_scratch_6_field_info[] = { - {"CFG_BLK_SCRATCH_6", - CFG_BLK_SCRATCH_6_MASK}, -}; - - -static struct regfield_info - cfg_blk_scratch_7_field_info[] = { - {"CFG_BLK_SCRATCH_7", - CFG_BLK_SCRATCH_7_MASK}, -}; - - -static struct regfield_info - ram_sbe_msk_a_field_info[] = { - {"RAM_SBE_MSK_A", - RAM_SBE_MSK_A_MASK}, -}; - - -static struct regfield_info - ram_sbe_sts_a_field_info[] = { - {"RAM_SBE_STS_A_RSVD_1", - RAM_SBE_STS_A_RSVD_1_MASK}, - {"RAM_SBE_STS_A_PFCH_LL_RAM", - RAM_SBE_STS_A_PFCH_LL_RAM_MASK}, - {"RAM_SBE_STS_A_WRB_CTXT_RAM", - RAM_SBE_STS_A_WRB_CTXT_RAM_MASK}, - {"RAM_SBE_STS_A_PFCH_CTXT_RAM", - RAM_SBE_STS_A_PFCH_CTXT_RAM_MASK}, - {"RAM_SBE_STS_A_DESC_REQ_FIFO_RAM", - RAM_SBE_STS_A_DESC_REQ_FIFO_RAM_MASK}, - {"RAM_SBE_STS_A_INT_CTXT_RAM", - RAM_SBE_STS_A_INT_CTXT_RAM_MASK}, - {"RAM_SBE_STS_A_INT_QID2VEC_RAM", - RAM_SBE_STS_A_INT_QID2VEC_RAM_MASK}, - {"RAM_SBE_STS_A_WRB_COAL_DATA_RAM", - RAM_SBE_STS_A_WRB_COAL_DATA_RAM_MASK}, - {"RAM_SBE_STS_A_TUSER_FIFO_RAM", - RAM_SBE_STS_A_TUSER_FIFO_RAM_MASK}, - {"RAM_SBE_STS_A_QID_FIFO_RAM", - RAM_SBE_STS_A_QID_FIFO_RAM_MASK}, - {"RAM_SBE_STS_A_PLD_FIFO_RAM", - RAM_SBE_STS_A_PLD_FIFO_RAM_MASK}, - {"RAM_SBE_STS_A_TIMER_FIFO_RAM", - RAM_SBE_STS_A_TIMER_FIFO_RAM_MASK}, - {"RAM_SBE_STS_A_PASID_CTXT_RAM", - RAM_SBE_STS_A_PASID_CTXT_RAM_MASK}, - {"RAM_SBE_STS_A_DSC_CPLD", - RAM_SBE_STS_A_DSC_CPLD_MASK}, - {"RAM_SBE_STS_A_DSC_CPLI", - RAM_SBE_STS_A_DSC_CPLI_MASK}, - {"RAM_SBE_STS_A_DSC_SW_CTXT", - RAM_SBE_STS_A_DSC_SW_CTXT_MASK}, - {"RAM_SBE_STS_A_DSC_CRD_RCV", - RAM_SBE_STS_A_DSC_CRD_RCV_MASK}, - {"RAM_SBE_STS_A_DSC_HW_CTXT", - RAM_SBE_STS_A_DSC_HW_CTXT_MASK}, - {"RAM_SBE_STS_A_FUNC_MAP", - RAM_SBE_STS_A_FUNC_MAP_MASK}, - {"RAM_SBE_STS_A_C2H_WR_BRG_DAT", - RAM_SBE_STS_A_C2H_WR_BRG_DAT_MASK}, - {"RAM_SBE_STS_A_C2H_RD_BRG_DAT", - RAM_SBE_STS_A_C2H_RD_BRG_DAT_MASK}, - {"RAM_SBE_STS_A_H2C_WR_BRG_DAT", - RAM_SBE_STS_A_H2C_WR_BRG_DAT_MASK}, - {"RAM_SBE_STS_A_H2C_RD_BRG_DAT", - RAM_SBE_STS_A_H2C_RD_BRG_DAT_MASK}, - {"RAM_SBE_STS_A_RSVD_2", - RAM_SBE_STS_A_RSVD_2_MASK}, - {"RAM_SBE_STS_A_MI_C2H0_DAT", - RAM_SBE_STS_A_MI_C2H0_DAT_MASK}, - {"RAM_SBE_STS_A_RSVD_3", - RAM_SBE_STS_A_RSVD_3_MASK}, - {"RAM_SBE_STS_A_MI_H2C0_DAT", - RAM_SBE_STS_A_MI_H2C0_DAT_MASK}, -}; - - -static struct regfield_info - ram_dbe_msk_a_field_info[] = { - {"RAM_DBE_MSK_A", - RAM_DBE_MSK_A_MASK}, -}; - - -static struct regfield_info - ram_dbe_sts_a_field_info[] = { - {"RAM_DBE_STS_A_RSVD_1", - RAM_DBE_STS_A_RSVD_1_MASK}, - {"RAM_DBE_STS_A_PFCH_LL_RAM", - RAM_DBE_STS_A_PFCH_LL_RAM_MASK}, - {"RAM_DBE_STS_A_WRB_CTXT_RAM", - RAM_DBE_STS_A_WRB_CTXT_RAM_MASK}, - {"RAM_DBE_STS_A_PFCH_CTXT_RAM", - RAM_DBE_STS_A_PFCH_CTXT_RAM_MASK}, - {"RAM_DBE_STS_A_DESC_REQ_FIFO_RAM", - RAM_DBE_STS_A_DESC_REQ_FIFO_RAM_MASK}, - {"RAM_DBE_STS_A_INT_CTXT_RAM", - RAM_DBE_STS_A_INT_CTXT_RAM_MASK}, - {"RAM_DBE_STS_A_INT_QID2VEC_RAM", - RAM_DBE_STS_A_INT_QID2VEC_RAM_MASK}, - {"RAM_DBE_STS_A_WRB_COAL_DATA_RAM", - RAM_DBE_STS_A_WRB_COAL_DATA_RAM_MASK}, - {"RAM_DBE_STS_A_TUSER_FIFO_RAM", - RAM_DBE_STS_A_TUSER_FIFO_RAM_MASK}, - {"RAM_DBE_STS_A_QID_FIFO_RAM", - RAM_DBE_STS_A_QID_FIFO_RAM_MASK}, - {"RAM_DBE_STS_A_PLD_FIFO_RAM", - RAM_DBE_STS_A_PLD_FIFO_RAM_MASK}, - {"RAM_DBE_STS_A_TIMER_FIFO_RAM", - RAM_DBE_STS_A_TIMER_FIFO_RAM_MASK}, - {"RAM_DBE_STS_A_PASID_CTXT_RAM", - RAM_DBE_STS_A_PASID_CTXT_RAM_MASK}, - {"RAM_DBE_STS_A_DSC_CPLD", - RAM_DBE_STS_A_DSC_CPLD_MASK}, - {"RAM_DBE_STS_A_DSC_CPLI", - RAM_DBE_STS_A_DSC_CPLI_MASK}, - {"RAM_DBE_STS_A_DSC_SW_CTXT", - RAM_DBE_STS_A_DSC_SW_CTXT_MASK}, - {"RAM_DBE_STS_A_DSC_CRD_RCV", - RAM_DBE_STS_A_DSC_CRD_RCV_MASK}, - {"RAM_DBE_STS_A_DSC_HW_CTXT", - RAM_DBE_STS_A_DSC_HW_CTXT_MASK}, - {"RAM_DBE_STS_A_FUNC_MAP", - RAM_DBE_STS_A_FUNC_MAP_MASK}, - {"RAM_DBE_STS_A_C2H_WR_BRG_DAT", - RAM_DBE_STS_A_C2H_WR_BRG_DAT_MASK}, - {"RAM_DBE_STS_A_C2H_RD_BRG_DAT", - RAM_DBE_STS_A_C2H_RD_BRG_DAT_MASK}, - {"RAM_DBE_STS_A_H2C_WR_BRG_DAT", - RAM_DBE_STS_A_H2C_WR_BRG_DAT_MASK}, - {"RAM_DBE_STS_A_H2C_RD_BRG_DAT", - RAM_DBE_STS_A_H2C_RD_BRG_DAT_MASK}, - {"RAM_DBE_STS_A_RSVD_2", - RAM_DBE_STS_A_RSVD_2_MASK}, - {"RAM_DBE_STS_A_MI_C2H0_DAT", - RAM_DBE_STS_A_MI_C2H0_DAT_MASK}, - {"RAM_DBE_STS_A_RSVD_3", - RAM_DBE_STS_A_RSVD_3_MASK}, - {"RAM_DBE_STS_A_MI_H2C0_DAT", - RAM_DBE_STS_A_MI_H2C0_DAT_MASK}, -}; - - -static struct regfield_info - glbl2_identifier_field_info[] = { - {"GLBL2_IDENTIFIER", - GLBL2_IDENTIFIER_MASK}, - {"GLBL2_IDENTIFIER_VERSION", - GLBL2_IDENTIFIER_VERSION_MASK}, -}; - - -static struct regfield_info - glbl2_pf_barlite_int_field_info[] = { - {"GLBL2_PF_BARLITE_INT_PF3_BAR_MAP", - GLBL2_PF_BARLITE_INT_PF3_BAR_MAP_MASK}, - {"GLBL2_PF_BARLITE_INT_PF2_BAR_MAP", - GLBL2_PF_BARLITE_INT_PF2_BAR_MAP_MASK}, - {"GLBL2_PF_BARLITE_INT_PF1_BAR_MAP", - GLBL2_PF_BARLITE_INT_PF1_BAR_MAP_MASK}, - {"GLBL2_PF_BARLITE_INT_PF0_BAR_MAP", - GLBL2_PF_BARLITE_INT_PF0_BAR_MAP_MASK}, -}; - - -static struct regfield_info - glbl2_pf_vf_barlite_int_field_info[] = { - {"GLBL2_PF_VF_BARLITE_INT_PF3_MAP", - GLBL2_PF_VF_BARLITE_INT_PF3_MAP_MASK}, - {"GLBL2_PF_VF_BARLITE_INT_PF2_MAP", - GLBL2_PF_VF_BARLITE_INT_PF2_MAP_MASK}, - {"GLBL2_PF_VF_BARLITE_INT_PF1_MAP", - GLBL2_PF_VF_BARLITE_INT_PF1_MAP_MASK}, - {"GLBL2_PF_VF_BARLITE_INT_PF0_MAP", - GLBL2_PF_VF_BARLITE_INT_PF0_MAP_MASK}, -}; - - -static struct regfield_info - glbl2_pf_barlite_ext_field_info[] = { - {"GLBL2_PF_BARLITE_EXT_PF3_BAR_MAP", - GLBL2_PF_BARLITE_EXT_PF3_BAR_MAP_MASK}, - {"GLBL2_PF_BARLITE_EXT_PF2_BAR_MAP", - GLBL2_PF_BARLITE_EXT_PF2_BAR_MAP_MASK}, - {"GLBL2_PF_BARLITE_EXT_PF1_BAR_MAP", - GLBL2_PF_BARLITE_EXT_PF1_BAR_MAP_MASK}, - {"GLBL2_PF_BARLITE_EXT_PF0_BAR_MAP", - GLBL2_PF_BARLITE_EXT_PF0_BAR_MAP_MASK}, -}; - - -static struct regfield_info - glbl2_pf_vf_barlite_ext_field_info[] = { - {"GLBL2_PF_VF_BARLITE_EXT_PF3_MAP", - GLBL2_PF_VF_BARLITE_EXT_PF3_MAP_MASK}, - {"GLBL2_PF_VF_BARLITE_EXT_PF2_MAP", - GLBL2_PF_VF_BARLITE_EXT_PF2_MAP_MASK}, - {"GLBL2_PF_VF_BARLITE_EXT_PF1_MAP", - GLBL2_PF_VF_BARLITE_EXT_PF1_MAP_MASK}, - {"GLBL2_PF_VF_BARLITE_EXT_PF0_MAP", - GLBL2_PF_VF_BARLITE_EXT_PF0_MAP_MASK}, -}; - - -static struct regfield_info - glbl2_channel_inst_field_info[] = { - {"GLBL2_CHANNEL_INST_RSVD_1", - GLBL2_CHANNEL_INST_RSVD_1_MASK}, - {"GLBL2_CHANNEL_INST_C2H_ST", - GLBL2_CHANNEL_INST_C2H_ST_MASK}, - {"GLBL2_CHANNEL_INST_H2C_ST", - GLBL2_CHANNEL_INST_H2C_ST_MASK}, - {"GLBL2_CHANNEL_INST_RSVD_2", - GLBL2_CHANNEL_INST_RSVD_2_MASK}, - {"GLBL2_CHANNEL_INST_C2H_ENG", - GLBL2_CHANNEL_INST_C2H_ENG_MASK}, - {"GLBL2_CHANNEL_INST_RSVD_3", - GLBL2_CHANNEL_INST_RSVD_3_MASK}, - {"GLBL2_CHANNEL_INST_H2C_ENG", - GLBL2_CHANNEL_INST_H2C_ENG_MASK}, -}; - - -static struct regfield_info - glbl2_channel_mdma_field_info[] = { - {"GLBL2_CHANNEL_MDMA_RSVD_1", - GLBL2_CHANNEL_MDMA_RSVD_1_MASK}, - {"GLBL2_CHANNEL_MDMA_C2H_ST", - GLBL2_CHANNEL_MDMA_C2H_ST_MASK}, - {"GLBL2_CHANNEL_MDMA_H2C_ST", - GLBL2_CHANNEL_MDMA_H2C_ST_MASK}, - {"GLBL2_CHANNEL_MDMA_RSVD_2", - GLBL2_CHANNEL_MDMA_RSVD_2_MASK}, - {"GLBL2_CHANNEL_MDMA_C2H_ENG", - GLBL2_CHANNEL_MDMA_C2H_ENG_MASK}, - {"GLBL2_CHANNEL_MDMA_RSVD_3", - GLBL2_CHANNEL_MDMA_RSVD_3_MASK}, - {"GLBL2_CHANNEL_MDMA_H2C_ENG", - GLBL2_CHANNEL_MDMA_H2C_ENG_MASK}, -}; - - -static struct regfield_info - glbl2_channel_strm_field_info[] = { - {"GLBL2_CHANNEL_STRM_RSVD_1", - GLBL2_CHANNEL_STRM_RSVD_1_MASK}, - {"GLBL2_CHANNEL_STRM_C2H_ST", - GLBL2_CHANNEL_STRM_C2H_ST_MASK}, - {"GLBL2_CHANNEL_STRM_H2C_ST", - GLBL2_CHANNEL_STRM_H2C_ST_MASK}, - {"GLBL2_CHANNEL_STRM_RSVD_2", - GLBL2_CHANNEL_STRM_RSVD_2_MASK}, - {"GLBL2_CHANNEL_STRM_C2H_ENG", - GLBL2_CHANNEL_STRM_C2H_ENG_MASK}, - {"GLBL2_CHANNEL_STRM_RSVD_3", - GLBL2_CHANNEL_STRM_RSVD_3_MASK}, - {"GLBL2_CHANNEL_STRM_H2C_ENG", - GLBL2_CHANNEL_STRM_H2C_ENG_MASK}, -}; - - -static struct regfield_info - glbl2_channel_cap_field_info[] = { - {"GLBL2_CHANNEL_CAP_RSVD_1", - GLBL2_CHANNEL_CAP_RSVD_1_MASK}, - {"GLBL2_CHANNEL_CAP_MULTIQ_MAX", - GLBL2_CHANNEL_CAP_MULTIQ_MAX_MASK}, -}; - - -static struct regfield_info - glbl2_channel_pasid_cap_field_info[] = { - {"GLBL2_CHANNEL_PASID_CAP_RSVD_1", - GLBL2_CHANNEL_PASID_CAP_RSVD_1_MASK}, - {"GLBL2_CHANNEL_PASID_CAP_BRIDGEOFFSET", - GLBL2_CHANNEL_PASID_CAP_BRIDGEOFFSET_MASK}, - {"GLBL2_CHANNEL_PASID_CAP_RSVD_2", - GLBL2_CHANNEL_PASID_CAP_RSVD_2_MASK}, - {"GLBL2_CHANNEL_PASID_CAP_BRIDGEEN", - GLBL2_CHANNEL_PASID_CAP_BRIDGEEN_MASK}, - {"GLBL2_CHANNEL_PASID_CAP_DMAEN", - GLBL2_CHANNEL_PASID_CAP_DMAEN_MASK}, -}; - - -static struct regfield_info - glbl2_channel_func_ret_field_info[] = { - {"GLBL2_CHANNEL_FUNC_RET_RSVD_1", - GLBL2_CHANNEL_FUNC_RET_RSVD_1_MASK}, - {"GLBL2_CHANNEL_FUNC_RET_FUNC", - GLBL2_CHANNEL_FUNC_RET_FUNC_MASK}, -}; - - -static struct regfield_info - glbl2_system_id_field_info[] = { - {"GLBL2_SYSTEM_ID_RSVD_1", - GLBL2_SYSTEM_ID_RSVD_1_MASK}, - {"GLBL2_SYSTEM_ID", - GLBL2_SYSTEM_ID_MASK}, -}; - - -static struct regfield_info - glbl2_misc_cap_field_info[] = { - {"GLBL2_MISC_CAP_RSVD_1", - GLBL2_MISC_CAP_RSVD_1_MASK}, -}; - - -static struct regfield_info - glbl2_dbg_pcie_rq0_field_info[] = { - {"GLBL2_PCIE_RQ0_NPH_AVL", - GLBL2_PCIE_RQ0_NPH_AVL_MASK}, - {"GLBL2_PCIE_RQ0_RCB_AVL", - GLBL2_PCIE_RQ0_RCB_AVL_MASK}, - {"GLBL2_PCIE_RQ0_SLV_RD_CREDS", - GLBL2_PCIE_RQ0_SLV_RD_CREDS_MASK}, - {"GLBL2_PCIE_RQ0_TAG_EP", - GLBL2_PCIE_RQ0_TAG_EP_MASK}, - {"GLBL2_PCIE_RQ0_TAG_FL", - GLBL2_PCIE_RQ0_TAG_FL_MASK}, -}; - - -static struct regfield_info - glbl2_dbg_pcie_rq1_field_info[] = { - {"GLBL2_PCIE_RQ1_RSVD_1", - GLBL2_PCIE_RQ1_RSVD_1_MASK}, - {"GLBL2_PCIE_RQ1_WTLP_REQ", - GLBL2_PCIE_RQ1_WTLP_REQ_MASK}, - {"GLBL2_PCIE_RQ1_WTLP_HEADER_FIFO_FL", - GLBL2_PCIE_RQ1_WTLP_HEADER_FIFO_FL_MASK}, - {"GLBL2_PCIE_RQ1_WTLP_HEADER_FIFO_EP", - GLBL2_PCIE_RQ1_WTLP_HEADER_FIFO_EP_MASK}, - {"GLBL2_PCIE_RQ1_RQ_FIFO_EP", - GLBL2_PCIE_RQ1_RQ_FIFO_EP_MASK}, - {"GLBL2_PCIE_RQ1_RQ_FIFO_FL", - GLBL2_PCIE_RQ1_RQ_FIFO_FL_MASK}, - {"GLBL2_PCIE_RQ1_TLPSM", - GLBL2_PCIE_RQ1_TLPSM_MASK}, - {"GLBL2_PCIE_RQ1_TLPSM512", - GLBL2_PCIE_RQ1_TLPSM512_MASK}, - {"GLBL2_PCIE_RQ1_RREQ0_RCB_OK", - GLBL2_PCIE_RQ1_RREQ0_RCB_OK_MASK}, - {"GLBL2_PCIE_RQ1_RREQ0_SLV", - GLBL2_PCIE_RQ1_RREQ0_SLV_MASK}, - {"GLBL2_PCIE_RQ1_RREQ0_VLD", - GLBL2_PCIE_RQ1_RREQ0_VLD_MASK}, - {"GLBL2_PCIE_RQ1_RREQ1_RCB_OK", - GLBL2_PCIE_RQ1_RREQ1_RCB_OK_MASK}, - {"GLBL2_PCIE_RQ1_RREQ1_SLV", - GLBL2_PCIE_RQ1_RREQ1_SLV_MASK}, - {"GLBL2_PCIE_RQ1_RREQ1_VLD", - GLBL2_PCIE_RQ1_RREQ1_VLD_MASK}, -}; - - -static struct regfield_info - glbl2_dbg_aximm_wr0_field_info[] = { - {"GLBL2_AXIMM_WR0_RSVD_1", - GLBL2_AXIMM_WR0_RSVD_1_MASK}, - {"GLBL2_AXIMM_WR0_WR_REQ", - GLBL2_AXIMM_WR0_WR_REQ_MASK}, - {"GLBL2_AXIMM_WR0_WR_CHN", - GLBL2_AXIMM_WR0_WR_CHN_MASK}, - {"GLBL2_AXIMM_WR0_WTLP_DATA_FIFO_EP", - GLBL2_AXIMM_WR0_WTLP_DATA_FIFO_EP_MASK}, - {"GLBL2_AXIMM_WR0_WPL_FIFO_EP", - GLBL2_AXIMM_WR0_WPL_FIFO_EP_MASK}, - {"GLBL2_AXIMM_WR0_BRSP_CLAIM_CHN", - GLBL2_AXIMM_WR0_BRSP_CLAIM_CHN_MASK}, - {"GLBL2_AXIMM_WR0_WRREQ_CNT", - GLBL2_AXIMM_WR0_WRREQ_CNT_MASK}, - {"GLBL2_AXIMM_WR0_BID", - GLBL2_AXIMM_WR0_BID_MASK}, - {"GLBL2_AXIMM_WR0_BVALID", - GLBL2_AXIMM_WR0_BVALID_MASK}, - {"GLBL2_AXIMM_WR0_BREADY", - GLBL2_AXIMM_WR0_BREADY_MASK}, - {"GLBL2_AXIMM_WR0_WVALID", - GLBL2_AXIMM_WR0_WVALID_MASK}, - {"GLBL2_AXIMM_WR0_WREADY", - GLBL2_AXIMM_WR0_WREADY_MASK}, - {"GLBL2_AXIMM_WR0_AWID", - GLBL2_AXIMM_WR0_AWID_MASK}, - {"GLBL2_AXIMM_WR0_AWVALID", - GLBL2_AXIMM_WR0_AWVALID_MASK}, - {"GLBL2_AXIMM_WR0_AWREADY", - GLBL2_AXIMM_WR0_AWREADY_MASK}, -}; - - -static struct regfield_info - glbl2_dbg_aximm_wr1_field_info[] = { - {"GLBL2_AXIMM_WR1_RSVD_1", - GLBL2_AXIMM_WR1_RSVD_1_MASK}, - {"GLBL2_AXIMM_WR1_BRSP_CNT4", - GLBL2_AXIMM_WR1_BRSP_CNT4_MASK}, - {"GLBL2_AXIMM_WR1_BRSP_CNT3", - GLBL2_AXIMM_WR1_BRSP_CNT3_MASK}, - {"GLBL2_AXIMM_WR1_BRSP_CNT2", - GLBL2_AXIMM_WR1_BRSP_CNT2_MASK}, - {"GLBL2_AXIMM_WR1_BRSP_CNT1", - GLBL2_AXIMM_WR1_BRSP_CNT1_MASK}, - {"GLBL2_AXIMM_WR1_BRSP_CNT0", - GLBL2_AXIMM_WR1_BRSP_CNT0_MASK}, -}; - - -static struct regfield_info - glbl2_dbg_aximm_rd0_field_info[] = { - {"GLBL2_AXIMM_RD0_RSVD_1", - GLBL2_AXIMM_RD0_RSVD_1_MASK}, - {"GLBL2_AXIMM_RD0_PND_CNT", - GLBL2_AXIMM_RD0_PND_CNT_MASK}, - {"GLBL2_AXIMM_RD0_RD_CHNL", - GLBL2_AXIMM_RD0_RD_CHNL_MASK}, - {"GLBL2_AXIMM_RD0_RD_REQ", - GLBL2_AXIMM_RD0_RD_REQ_MASK}, - {"GLBL2_AXIMM_RD0_RRSP_CLAIM_CHNL", - GLBL2_AXIMM_RD0_RRSP_CLAIM_CHNL_MASK}, - {"GLBL2_AXIMM_RD0_RID", - GLBL2_AXIMM_RD0_RID_MASK}, - {"GLBL2_AXIMM_RD0_RVALID", - GLBL2_AXIMM_RD0_RVALID_MASK}, - {"GLBL2_AXIMM_RD0_RREADY", - GLBL2_AXIMM_RD0_RREADY_MASK}, - {"GLBL2_AXIMM_RD0_ARID", - GLBL2_AXIMM_RD0_ARID_MASK}, - {"GLBL2_AXIMM_RD0_ARVALID", - GLBL2_AXIMM_RD0_ARVALID_MASK}, - {"GLBL2_AXIMM_RD0_ARREADY", - GLBL2_AXIMM_RD0_ARREADY_MASK}, -}; - - -static struct regfield_info - glbl2_dbg_aximm_rd1_field_info[] = { - {"GLBL2_AXIMM_RD1_RSVD_1", - GLBL2_AXIMM_RD1_RSVD_1_MASK}, - {"GLBL2_AXIMM_RD1_RRSP_CNT4", - GLBL2_AXIMM_RD1_RRSP_CNT4_MASK}, - {"GLBL2_AXIMM_RD1_RRSP_CNT3", - GLBL2_AXIMM_RD1_RRSP_CNT3_MASK}, - {"GLBL2_AXIMM_RD1_RRSP_CNT2", - GLBL2_AXIMM_RD1_RRSP_CNT2_MASK}, - {"GLBL2_AXIMM_RD1_RRSP_CNT1", - GLBL2_AXIMM_RD1_RRSP_CNT1_MASK}, - {"GLBL2_AXIMM_RD1_RRSP_CNT0", - GLBL2_AXIMM_RD1_RRSP_CNT0_MASK}, -}; - - -static struct regfield_info - glbl_rng_sz_1_field_info[] = { - {"GLBL_RNG_SZ_1_RSVD_1", - GLBL_RNG_SZ_1_RSVD_1_MASK}, - {"GLBL_RNG_SZ_1_RING_SIZE", - GLBL_RNG_SZ_1_RING_SIZE_MASK}, -}; - - -static struct regfield_info - glbl_rng_sz_2_field_info[] = { - {"GLBL_RNG_SZ_2_RSVD_1", - GLBL_RNG_SZ_2_RSVD_1_MASK}, - {"GLBL_RNG_SZ_2_RING_SIZE", - GLBL_RNG_SZ_2_RING_SIZE_MASK}, -}; - - -static struct regfield_info - glbl_rng_sz_3_field_info[] = { - {"GLBL_RNG_SZ_3_RSVD_1", - GLBL_RNG_SZ_3_RSVD_1_MASK}, - {"GLBL_RNG_SZ_3_RING_SIZE", - GLBL_RNG_SZ_3_RING_SIZE_MASK}, -}; - - -static struct regfield_info - glbl_rng_sz_4_field_info[] = { - {"GLBL_RNG_SZ_4_RSVD_1", - GLBL_RNG_SZ_4_RSVD_1_MASK}, - {"GLBL_RNG_SZ_4_RING_SIZE", - GLBL_RNG_SZ_4_RING_SIZE_MASK}, -}; - - -static struct regfield_info - glbl_rng_sz_5_field_info[] = { - {"GLBL_RNG_SZ_5_RSVD_1", - GLBL_RNG_SZ_5_RSVD_1_MASK}, - {"GLBL_RNG_SZ_5_RING_SIZE", - GLBL_RNG_SZ_5_RING_SIZE_MASK}, -}; - - -static struct regfield_info - glbl_rng_sz_6_field_info[] = { - {"GLBL_RNG_SZ_6_RSVD_1", - GLBL_RNG_SZ_6_RSVD_1_MASK}, - {"GLBL_RNG_SZ_6_RING_SIZE", - GLBL_RNG_SZ_6_RING_SIZE_MASK}, -}; - - -static struct regfield_info - glbl_rng_sz_7_field_info[] = { - {"GLBL_RNG_SZ_7_RSVD_1", - GLBL_RNG_SZ_7_RSVD_1_MASK}, - {"GLBL_RNG_SZ_7_RING_SIZE", - GLBL_RNG_SZ_7_RING_SIZE_MASK}, -}; - - -static struct regfield_info - glbl_rng_sz_8_field_info[] = { - {"GLBL_RNG_SZ_8_RSVD_1", - GLBL_RNG_SZ_8_RSVD_1_MASK}, - {"GLBL_RNG_SZ_8_RING_SIZE", - GLBL_RNG_SZ_8_RING_SIZE_MASK}, -}; - - -static struct regfield_info - glbl_rng_sz_9_field_info[] = { - {"GLBL_RNG_SZ_9_RSVD_1", - GLBL_RNG_SZ_9_RSVD_1_MASK}, - {"GLBL_RNG_SZ_9_RING_SIZE", - GLBL_RNG_SZ_9_RING_SIZE_MASK}, -}; - - -static struct regfield_info - glbl_rng_sz_a_field_info[] = { - {"GLBL_RNG_SZ_A_RSVD_1", - GLBL_RNG_SZ_A_RSVD_1_MASK}, - {"GLBL_RNG_SZ_A_RING_SIZE", - GLBL_RNG_SZ_A_RING_SIZE_MASK}, -}; - - -static struct regfield_info - glbl_rng_sz_b_field_info[] = { - {"GLBL_RNG_SZ_B_RSVD_1", - GLBL_RNG_SZ_B_RSVD_1_MASK}, - {"GLBL_RNG_SZ_B_RING_SIZE", - GLBL_RNG_SZ_B_RING_SIZE_MASK}, -}; - - -static struct regfield_info - glbl_rng_sz_c_field_info[] = { - {"GLBL_RNG_SZ_C_RSVD_1", - GLBL_RNG_SZ_C_RSVD_1_MASK}, - {"GLBL_RNG_SZ_C_RING_SIZE", - GLBL_RNG_SZ_C_RING_SIZE_MASK}, -}; - - -static struct regfield_info - glbl_rng_sz_d_field_info[] = { - {"GLBL_RNG_SZ_D_RSVD_1", - GLBL_RNG_SZ_D_RSVD_1_MASK}, - {"GLBL_RNG_SZ_D_RING_SIZE", - GLBL_RNG_SZ_D_RING_SIZE_MASK}, -}; - - -static struct regfield_info - glbl_rng_sz_e_field_info[] = { - {"GLBL_RNG_SZ_E_RSVD_1", - GLBL_RNG_SZ_E_RSVD_1_MASK}, - {"GLBL_RNG_SZ_E_RING_SIZE", - GLBL_RNG_SZ_E_RING_SIZE_MASK}, -}; - - -static struct regfield_info - glbl_rng_sz_f_field_info[] = { - {"GLBL_RNG_SZ_F_RSVD_1", - GLBL_RNG_SZ_F_RSVD_1_MASK}, - {"GLBL_RNG_SZ_F_RING_SIZE", - GLBL_RNG_SZ_F_RING_SIZE_MASK}, -}; - - -static struct regfield_info - glbl_rng_sz_10_field_info[] = { - {"GLBL_RNG_SZ_10_RSVD_1", - GLBL_RNG_SZ_10_RSVD_1_MASK}, - {"GLBL_RNG_SZ_10_RING_SIZE", - GLBL_RNG_SZ_10_RING_SIZE_MASK}, -}; - - -static struct regfield_info - glbl_err_stat_field_info[] = { - {"GLBL_ERR_STAT_RSVD_1", - GLBL_ERR_STAT_RSVD_1_MASK}, - {"GLBL_ERR_STAT_ERR_H2C_ST", - GLBL_ERR_STAT_ERR_H2C_ST_MASK}, - {"GLBL_ERR_STAT_ERR_BDG", - GLBL_ERR_STAT_ERR_BDG_MASK}, - {"GLBL_ERR_STAT_IND_CTXT_CMD_ERR", - GLBL_ERR_STAT_IND_CTXT_CMD_ERR_MASK}, - {"GLBL_ERR_STAT_ERR_C2H_ST", - GLBL_ERR_STAT_ERR_C2H_ST_MASK}, - {"GLBL_ERR_STAT_ERR_C2H_MM_1", - GLBL_ERR_STAT_ERR_C2H_MM_1_MASK}, - {"GLBL_ERR_STAT_ERR_C2H_MM_0", - GLBL_ERR_STAT_ERR_C2H_MM_0_MASK}, - {"GLBL_ERR_STAT_ERR_H2C_MM_1", - GLBL_ERR_STAT_ERR_H2C_MM_1_MASK}, - {"GLBL_ERR_STAT_ERR_H2C_MM_0", - GLBL_ERR_STAT_ERR_H2C_MM_0_MASK}, - {"GLBL_ERR_STAT_ERR_TRQ", - GLBL_ERR_STAT_ERR_TRQ_MASK}, - {"GLBL_ERR_STAT_ERR_DSC", - GLBL_ERR_STAT_ERR_DSC_MASK}, - {"GLBL_ERR_STAT_ERR_RAM_DBE", - GLBL_ERR_STAT_ERR_RAM_DBE_MASK}, - {"GLBL_ERR_STAT_ERR_RAM_SBE", - GLBL_ERR_STAT_ERR_RAM_SBE_MASK}, -}; - - -static struct regfield_info - glbl_err_mask_field_info[] = { - {"GLBL_ERR_RSVD_1", - GLBL_ERR_RSVD_1_MASK}, - {"GLBL_ERR", - GLBL_ERR_MASK}, -}; - - -static struct regfield_info - glbl_dsc_cfg_field_info[] = { - {"GLBL_DSC_CFG_RSVD_1", - GLBL_DSC_CFG_RSVD_1_MASK}, - {"GLBL_DSC_CFG_UNC_OVR_COR", - GLBL_DSC_CFG_UNC_OVR_COR_MASK}, - {"GLBL_DSC_CFG_CTXT_FER_DIS", - GLBL_DSC_CFG_CTXT_FER_DIS_MASK}, - {"GLBL_DSC_CFG_RSVD_2", - GLBL_DSC_CFG_RSVD_2_MASK}, - {"GLBL_DSC_CFG_MAXFETCH", - GLBL_DSC_CFG_MAXFETCH_MASK}, - {"GLBL_DSC_CFG_WB_ACC_INT", - GLBL_DSC_CFG_WB_ACC_INT_MASK}, -}; - - -static struct regfield_info - glbl_dsc_err_sts_field_info[] = { - {"GLBL_DSC_ERR_STS_RSVD_1", - GLBL_DSC_ERR_STS_RSVD_1_MASK}, - {"GLBL_DSC_ERR_STS_SBE", - GLBL_DSC_ERR_STS_SBE_MASK}, - {"GLBL_DSC_ERR_STS_DBE", - GLBL_DSC_ERR_STS_DBE_MASK}, - {"GLBL_DSC_ERR_STS_RQ_CANCEL", - GLBL_DSC_ERR_STS_RQ_CANCEL_MASK}, - {"GLBL_DSC_ERR_STS_DSC", - GLBL_DSC_ERR_STS_DSC_MASK}, - {"GLBL_DSC_ERR_STS_DMA", - GLBL_DSC_ERR_STS_DMA_MASK}, - {"GLBL_DSC_ERR_STS_FLR_CANCEL", - GLBL_DSC_ERR_STS_FLR_CANCEL_MASK}, - {"GLBL_DSC_ERR_STS_RSVD_2", - GLBL_DSC_ERR_STS_RSVD_2_MASK}, - {"GLBL_DSC_ERR_STS_DAT_POISON", - GLBL_DSC_ERR_STS_DAT_POISON_MASK}, - {"GLBL_DSC_ERR_STS_TIMEOUT", - GLBL_DSC_ERR_STS_TIMEOUT_MASK}, - {"GLBL_DSC_ERR_STS_FLR", - GLBL_DSC_ERR_STS_FLR_MASK}, - {"GLBL_DSC_ERR_STS_TAG", - GLBL_DSC_ERR_STS_TAG_MASK}, - {"GLBL_DSC_ERR_STS_ADDR", - GLBL_DSC_ERR_STS_ADDR_MASK}, - {"GLBL_DSC_ERR_STS_PARAM", - GLBL_DSC_ERR_STS_PARAM_MASK}, - {"GLBL_DSC_ERR_STS_UR_CA", - GLBL_DSC_ERR_STS_UR_CA_MASK}, - {"GLBL_DSC_ERR_STS_POISON", - GLBL_DSC_ERR_STS_POISON_MASK}, -}; - - -static struct regfield_info - glbl_dsc_err_msk_field_info[] = { - {"GLBL_DSC_ERR_MSK", - GLBL_DSC_ERR_MSK_MASK}, -}; - - -static struct regfield_info - glbl_dsc_err_log0_field_info[] = { - {"GLBL_DSC_ERR_LOG0_VALID", - GLBL_DSC_ERR_LOG0_VALID_MASK}, - {"GLBL_DSC_ERR_LOG0_RSVD_1", - GLBL_DSC_ERR_LOG0_RSVD_1_MASK}, - {"GLBL_DSC_ERR_LOG0_QID", - GLBL_DSC_ERR_LOG0_QID_MASK}, - {"GLBL_DSC_ERR_LOG0_SEL", - GLBL_DSC_ERR_LOG0_SEL_MASK}, - {"GLBL_DSC_ERR_LOG0_CIDX", - GLBL_DSC_ERR_LOG0_CIDX_MASK}, -}; - - -static struct regfield_info - glbl_dsc_err_log1_field_info[] = { - {"GLBL_DSC_ERR_LOG1_RSVD_1", - GLBL_DSC_ERR_LOG1_RSVD_1_MASK}, - {"GLBL_DSC_ERR_LOG1_SUB_TYPE", - GLBL_DSC_ERR_LOG1_SUB_TYPE_MASK}, - {"GLBL_DSC_ERR_LOG1_ERR_TYPE", - GLBL_DSC_ERR_LOG1_ERR_TYPE_MASK}, -}; - - -static struct regfield_info - glbl_trq_err_sts_field_info[] = { - {"GLBL_TRQ_ERR_STS_RSVD_1", - GLBL_TRQ_ERR_STS_RSVD_1_MASK}, - {"GLBL_TRQ_ERR_STS_TCP_TIMEOUT", - GLBL_TRQ_ERR_STS_TCP_TIMEOUT_MASK}, - {"GLBL_TRQ_ERR_STS_VF_ACCESS_ERR", - GLBL_TRQ_ERR_STS_VF_ACCESS_ERR_MASK}, - {"GLBL_TRQ_ERR_STS_QID_RANGE", - GLBL_TRQ_ERR_STS_QID_RANGE_MASK}, - {"GLBL_TRQ_ERR_STS_UNMAPPED", - GLBL_TRQ_ERR_STS_UNMAPPED_MASK}, -}; - - -static struct regfield_info - glbl_trq_err_msk_field_info[] = { - {"GLBL_TRQ_ERR_MSK", - GLBL_TRQ_ERR_MSK_MASK}, -}; - - -static struct regfield_info - glbl_trq_err_log_field_info[] = { - {"GLBL_TRQ_ERR_LOG_RSVD_1", - GLBL_TRQ_ERR_LOG_RSVD_1_MASK}, - {"GLBL_TRQ_ERR_LOG_TARGET", - GLBL_TRQ_ERR_LOG_TARGET_MASK}, - {"GLBL_TRQ_ERR_LOG_FUNC", - GLBL_TRQ_ERR_LOG_FUNC_MASK}, - {"GLBL_TRQ_ERR_LOG_ADDRESS", - GLBL_TRQ_ERR_LOG_ADDRESS_MASK}, -}; - - -static struct regfield_info - glbl_dsc_dbg_dat0_field_info[] = { - {"GLBL_DSC_DAT0_RSVD_1", - GLBL_DSC_DAT0_RSVD_1_MASK}, - {"GLBL_DSC_DAT0_CTXT_ARB_DIR", - GLBL_DSC_DAT0_CTXT_ARB_DIR_MASK}, - {"GLBL_DSC_DAT0_CTXT_ARB_QID", - GLBL_DSC_DAT0_CTXT_ARB_QID_MASK}, - {"GLBL_DSC_DAT0_CTXT_ARB_REQ", - GLBL_DSC_DAT0_CTXT_ARB_REQ_MASK}, - {"GLBL_DSC_DAT0_IRQ_FIFO_FL", - GLBL_DSC_DAT0_IRQ_FIFO_FL_MASK}, - {"GLBL_DSC_DAT0_TMSTALL", - GLBL_DSC_DAT0_TMSTALL_MASK}, - {"GLBL_DSC_DAT0_RRQ_STALL", - GLBL_DSC_DAT0_RRQ_STALL_MASK}, - {"GLBL_DSC_DAT0_RCP_FIFO_SPC_STALL", - GLBL_DSC_DAT0_RCP_FIFO_SPC_STALL_MASK}, - {"GLBL_DSC_DAT0_RRQ_FIFO_SPC_STALL", - GLBL_DSC_DAT0_RRQ_FIFO_SPC_STALL_MASK}, - {"GLBL_DSC_DAT0_FAB_MRKR_RSP_STALL", - GLBL_DSC_DAT0_FAB_MRKR_RSP_STALL_MASK}, - {"GLBL_DSC_DAT0_DSC_OUT_STALL", - GLBL_DSC_DAT0_DSC_OUT_STALL_MASK}, -}; - - -static struct regfield_info - glbl_dsc_dbg_dat1_field_info[] = { - {"GLBL_DSC_DAT1_RSVD_1", - GLBL_DSC_DAT1_RSVD_1_MASK}, - {"GLBL_DSC_DAT1_EVT_SPC_C2H", - GLBL_DSC_DAT1_EVT_SPC_C2H_MASK}, - {"GLBL_DSC_DAT1_EVT_SP_H2C", - GLBL_DSC_DAT1_EVT_SP_H2C_MASK}, - {"GLBL_DSC_DAT1_DSC_SPC_C2H", - GLBL_DSC_DAT1_DSC_SPC_C2H_MASK}, - {"GLBL_DSC_DAT1_DSC_SPC_H2C", - GLBL_DSC_DAT1_DSC_SPC_H2C_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_0_field_info[] = { - {"TRQ_SEL_FMAP_0_RSVD_1", - TRQ_SEL_FMAP_0_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_0_QID_MAX", - TRQ_SEL_FMAP_0_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_0_QID_BASE", - TRQ_SEL_FMAP_0_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_1_field_info[] = { - {"TRQ_SEL_FMAP_1_RSVD_1", - TRQ_SEL_FMAP_1_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_1_QID_MAX", - TRQ_SEL_FMAP_1_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_1_QID_BASE", - TRQ_SEL_FMAP_1_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_2_field_info[] = { - {"TRQ_SEL_FMAP_2_RSVD_1", - TRQ_SEL_FMAP_2_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_2_QID_MAX", - TRQ_SEL_FMAP_2_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_2_QID_BASE", - TRQ_SEL_FMAP_2_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_3_field_info[] = { - {"TRQ_SEL_FMAP_3_RSVD_1", - TRQ_SEL_FMAP_3_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_3_QID_MAX", - TRQ_SEL_FMAP_3_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_3_QID_BASE", - TRQ_SEL_FMAP_3_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_4_field_info[] = { - {"TRQ_SEL_FMAP_4_RSVD_1", - TRQ_SEL_FMAP_4_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_4_QID_MAX", - TRQ_SEL_FMAP_4_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_4_QID_BASE", - TRQ_SEL_FMAP_4_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_5_field_info[] = { - {"TRQ_SEL_FMAP_5_RSVD_1", - TRQ_SEL_FMAP_5_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_5_QID_MAX", - TRQ_SEL_FMAP_5_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_5_QID_BASE", - TRQ_SEL_FMAP_5_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_6_field_info[] = { - {"TRQ_SEL_FMAP_6_RSVD_1", - TRQ_SEL_FMAP_6_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_6_QID_MAX", - TRQ_SEL_FMAP_6_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_6_QID_BASE", - TRQ_SEL_FMAP_6_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_7_field_info[] = { - {"TRQ_SEL_FMAP_7_RSVD_1", - TRQ_SEL_FMAP_7_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_7_QID_MAX", - TRQ_SEL_FMAP_7_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_7_QID_BASE", - TRQ_SEL_FMAP_7_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_8_field_info[] = { - {"TRQ_SEL_FMAP_8_RSVD_1", - TRQ_SEL_FMAP_8_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_8_QID_MAX", - TRQ_SEL_FMAP_8_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_8_QID_BASE", - TRQ_SEL_FMAP_8_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_9_field_info[] = { - {"TRQ_SEL_FMAP_9_RSVD_1", - TRQ_SEL_FMAP_9_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_9_QID_MAX", - TRQ_SEL_FMAP_9_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_9_QID_BASE", - TRQ_SEL_FMAP_9_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_a_field_info[] = { - {"TRQ_SEL_FMAP_A_RSVD_1", - TRQ_SEL_FMAP_A_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_A_QID_MAX", - TRQ_SEL_FMAP_A_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_A_QID_BASE", - TRQ_SEL_FMAP_A_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_b_field_info[] = { - {"TRQ_SEL_FMAP_B_RSVD_1", - TRQ_SEL_FMAP_B_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_B_QID_MAX", - TRQ_SEL_FMAP_B_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_B_QID_BASE", - TRQ_SEL_FMAP_B_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_d_field_info[] = { - {"TRQ_SEL_FMAP_D_RSVD_1", - TRQ_SEL_FMAP_D_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_D_QID_MAX", - TRQ_SEL_FMAP_D_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_D_QID_BASE", - TRQ_SEL_FMAP_D_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_e_field_info[] = { - {"TRQ_SEL_FMAP_E_RSVD_1", - TRQ_SEL_FMAP_E_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_E_QID_MAX", - TRQ_SEL_FMAP_E_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_E_QID_BASE", - TRQ_SEL_FMAP_E_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_f_field_info[] = { - {"TRQ_SEL_FMAP_F_RSVD_1", - TRQ_SEL_FMAP_F_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_F_QID_MAX", - TRQ_SEL_FMAP_F_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_F_QID_BASE", - TRQ_SEL_FMAP_F_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_10_field_info[] = { - {"TRQ_SEL_FMAP_10_RSVD_1", - TRQ_SEL_FMAP_10_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_10_QID_MAX", - TRQ_SEL_FMAP_10_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_10_QID_BASE", - TRQ_SEL_FMAP_10_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_11_field_info[] = { - {"TRQ_SEL_FMAP_11_RSVD_1", - TRQ_SEL_FMAP_11_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_11_QID_MAX", - TRQ_SEL_FMAP_11_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_11_QID_BASE", - TRQ_SEL_FMAP_11_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_12_field_info[] = { - {"TRQ_SEL_FMAP_12_RSVD_1", - TRQ_SEL_FMAP_12_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_12_QID_MAX", - TRQ_SEL_FMAP_12_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_12_QID_BASE", - TRQ_SEL_FMAP_12_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_13_field_info[] = { - {"TRQ_SEL_FMAP_13_RSVD_1", - TRQ_SEL_FMAP_13_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_13_QID_MAX", - TRQ_SEL_FMAP_13_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_13_QID_BASE", - TRQ_SEL_FMAP_13_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_14_field_info[] = { - {"TRQ_SEL_FMAP_14_RSVD_1", - TRQ_SEL_FMAP_14_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_14_QID_MAX", - TRQ_SEL_FMAP_14_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_14_QID_BASE", - TRQ_SEL_FMAP_14_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_15_field_info[] = { - {"TRQ_SEL_FMAP_15_RSVD_1", - TRQ_SEL_FMAP_15_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_15_QID_MAX", - TRQ_SEL_FMAP_15_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_15_QID_BASE", - TRQ_SEL_FMAP_15_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_16_field_info[] = { - {"TRQ_SEL_FMAP_16_RSVD_1", - TRQ_SEL_FMAP_16_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_16_QID_MAX", - TRQ_SEL_FMAP_16_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_16_QID_BASE", - TRQ_SEL_FMAP_16_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_17_field_info[] = { - {"TRQ_SEL_FMAP_17_RSVD_1", - TRQ_SEL_FMAP_17_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_17_QID_MAX", - TRQ_SEL_FMAP_17_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_17_QID_BASE", - TRQ_SEL_FMAP_17_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_18_field_info[] = { - {"TRQ_SEL_FMAP_18_RSVD_1", - TRQ_SEL_FMAP_18_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_18_QID_MAX", - TRQ_SEL_FMAP_18_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_18_QID_BASE", - TRQ_SEL_FMAP_18_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_19_field_info[] = { - {"TRQ_SEL_FMAP_19_RSVD_1", - TRQ_SEL_FMAP_19_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_19_QID_MAX", - TRQ_SEL_FMAP_19_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_19_QID_BASE", - TRQ_SEL_FMAP_19_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_1a_field_info[] = { - {"TRQ_SEL_FMAP_1A_RSVD_1", - TRQ_SEL_FMAP_1A_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_1A_QID_MAX", - TRQ_SEL_FMAP_1A_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_1A_QID_BASE", - TRQ_SEL_FMAP_1A_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_1b_field_info[] = { - {"TRQ_SEL_FMAP_1B_RSVD_1", - TRQ_SEL_FMAP_1B_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_1B_QID_MAX", - TRQ_SEL_FMAP_1B_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_1B_QID_BASE", - TRQ_SEL_FMAP_1B_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_1c_field_info[] = { - {"TRQ_SEL_FMAP_1C_RSVD_1", - TRQ_SEL_FMAP_1C_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_1C_QID_MAX", - TRQ_SEL_FMAP_1C_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_1C_QID_BASE", - TRQ_SEL_FMAP_1C_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_1d_field_info[] = { - {"TRQ_SEL_FMAP_1D_RSVD_1", - TRQ_SEL_FMAP_1D_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_1D_QID_MAX", - TRQ_SEL_FMAP_1D_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_1D_QID_BASE", - TRQ_SEL_FMAP_1D_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_1e_field_info[] = { - {"TRQ_SEL_FMAP_1E_RSVD_1", - TRQ_SEL_FMAP_1E_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_1E_QID_MAX", - TRQ_SEL_FMAP_1E_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_1E_QID_BASE", - TRQ_SEL_FMAP_1E_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_1f_field_info[] = { - {"TRQ_SEL_FMAP_1F_RSVD_1", - TRQ_SEL_FMAP_1F_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_1F_QID_MAX", - TRQ_SEL_FMAP_1F_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_1F_QID_BASE", - TRQ_SEL_FMAP_1F_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_20_field_info[] = { - {"TRQ_SEL_FMAP_20_RSVD_1", - TRQ_SEL_FMAP_20_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_20_QID_MAX", - TRQ_SEL_FMAP_20_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_20_QID_BASE", - TRQ_SEL_FMAP_20_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_21_field_info[] = { - {"TRQ_SEL_FMAP_21_RSVD_1", - TRQ_SEL_FMAP_21_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_21_QID_MAX", - TRQ_SEL_FMAP_21_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_21_QID_BASE", - TRQ_SEL_FMAP_21_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_22_field_info[] = { - {"TRQ_SEL_FMAP_22_RSVD_1", - TRQ_SEL_FMAP_22_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_22_QID_MAX", - TRQ_SEL_FMAP_22_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_22_QID_BASE", - TRQ_SEL_FMAP_22_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_23_field_info[] = { - {"TRQ_SEL_FMAP_23_RSVD_1", - TRQ_SEL_FMAP_23_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_23_QID_MAX", - TRQ_SEL_FMAP_23_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_23_QID_BASE", - TRQ_SEL_FMAP_23_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_24_field_info[] = { - {"TRQ_SEL_FMAP_24_RSVD_1", - TRQ_SEL_FMAP_24_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_24_QID_MAX", - TRQ_SEL_FMAP_24_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_24_QID_BASE", - TRQ_SEL_FMAP_24_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_25_field_info[] = { - {"TRQ_SEL_FMAP_25_RSVD_1", - TRQ_SEL_FMAP_25_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_25_QID_MAX", - TRQ_SEL_FMAP_25_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_25_QID_BASE", - TRQ_SEL_FMAP_25_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_26_field_info[] = { - {"TRQ_SEL_FMAP_26_RSVD_1", - TRQ_SEL_FMAP_26_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_26_QID_MAX", - TRQ_SEL_FMAP_26_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_26_QID_BASE", - TRQ_SEL_FMAP_26_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_27_field_info[] = { - {"TRQ_SEL_FMAP_27_RSVD_1", - TRQ_SEL_FMAP_27_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_27_QID_MAX", - TRQ_SEL_FMAP_27_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_27_QID_BASE", - TRQ_SEL_FMAP_27_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_28_field_info[] = { - {"TRQ_SEL_FMAP_28_RSVD_1", - TRQ_SEL_FMAP_28_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_28_QID_MAX", - TRQ_SEL_FMAP_28_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_28_QID_BASE", - TRQ_SEL_FMAP_28_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_29_field_info[] = { - {"TRQ_SEL_FMAP_29_RSVD_1", - TRQ_SEL_FMAP_29_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_29_QID_MAX", - TRQ_SEL_FMAP_29_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_29_QID_BASE", - TRQ_SEL_FMAP_29_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_2a_field_info[] = { - {"TRQ_SEL_FMAP_2A_RSVD_1", - TRQ_SEL_FMAP_2A_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_2A_QID_MAX", - TRQ_SEL_FMAP_2A_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_2A_QID_BASE", - TRQ_SEL_FMAP_2A_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_2b_field_info[] = { - {"TRQ_SEL_FMAP_2B_RSVD_1", - TRQ_SEL_FMAP_2B_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_2B_QID_MAX", - TRQ_SEL_FMAP_2B_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_2B_QID_BASE", - TRQ_SEL_FMAP_2B_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_2c_field_info[] = { - {"TRQ_SEL_FMAP_2C_RSVD_1", - TRQ_SEL_FMAP_2C_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_2C_QID_MAX", - TRQ_SEL_FMAP_2C_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_2C_QID_BASE", - TRQ_SEL_FMAP_2C_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_2d_field_info[] = { - {"TRQ_SEL_FMAP_2D_RSVD_1", - TRQ_SEL_FMAP_2D_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_2D_QID_MAX", - TRQ_SEL_FMAP_2D_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_2D_QID_BASE", - TRQ_SEL_FMAP_2D_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_2e_field_info[] = { - {"TRQ_SEL_FMAP_2E_RSVD_1", - TRQ_SEL_FMAP_2E_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_2E_QID_MAX", - TRQ_SEL_FMAP_2E_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_2E_QID_BASE", - TRQ_SEL_FMAP_2E_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_2f_field_info[] = { - {"TRQ_SEL_FMAP_2F_RSVD_1", - TRQ_SEL_FMAP_2F_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_2F_QID_MAX", - TRQ_SEL_FMAP_2F_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_2F_QID_BASE", - TRQ_SEL_FMAP_2F_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_30_field_info[] = { - {"TRQ_SEL_FMAP_30_RSVD_1", - TRQ_SEL_FMAP_30_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_30_QID_MAX", - TRQ_SEL_FMAP_30_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_30_QID_BASE", - TRQ_SEL_FMAP_30_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_31_field_info[] = { - {"TRQ_SEL_FMAP_31_RSVD_1", - TRQ_SEL_FMAP_31_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_31_QID_MAX", - TRQ_SEL_FMAP_31_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_31_QID_BASE", - TRQ_SEL_FMAP_31_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_32_field_info[] = { - {"TRQ_SEL_FMAP_32_RSVD_1", - TRQ_SEL_FMAP_32_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_32_QID_MAX", - TRQ_SEL_FMAP_32_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_32_QID_BASE", - TRQ_SEL_FMAP_32_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_33_field_info[] = { - {"TRQ_SEL_FMAP_33_RSVD_1", - TRQ_SEL_FMAP_33_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_33_QID_MAX", - TRQ_SEL_FMAP_33_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_33_QID_BASE", - TRQ_SEL_FMAP_33_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_34_field_info[] = { - {"TRQ_SEL_FMAP_34_RSVD_1", - TRQ_SEL_FMAP_34_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_34_QID_MAX", - TRQ_SEL_FMAP_34_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_34_QID_BASE", - TRQ_SEL_FMAP_34_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_35_field_info[] = { - {"TRQ_SEL_FMAP_35_RSVD_1", - TRQ_SEL_FMAP_35_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_35_QID_MAX", - TRQ_SEL_FMAP_35_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_35_QID_BASE", - TRQ_SEL_FMAP_35_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_36_field_info[] = { - {"TRQ_SEL_FMAP_36_RSVD_1", - TRQ_SEL_FMAP_36_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_36_QID_MAX", - TRQ_SEL_FMAP_36_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_36_QID_BASE", - TRQ_SEL_FMAP_36_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_37_field_info[] = { - {"TRQ_SEL_FMAP_37_RSVD_1", - TRQ_SEL_FMAP_37_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_37_QID_MAX", - TRQ_SEL_FMAP_37_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_37_QID_BASE", - TRQ_SEL_FMAP_37_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_38_field_info[] = { - {"TRQ_SEL_FMAP_38_RSVD_1", - TRQ_SEL_FMAP_38_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_38_QID_MAX", - TRQ_SEL_FMAP_38_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_38_QID_BASE", - TRQ_SEL_FMAP_38_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_39_field_info[] = { - {"TRQ_SEL_FMAP_39_RSVD_1", - TRQ_SEL_FMAP_39_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_39_QID_MAX", - TRQ_SEL_FMAP_39_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_39_QID_BASE", - TRQ_SEL_FMAP_39_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_3a_field_info[] = { - {"TRQ_SEL_FMAP_3A_RSVD_1", - TRQ_SEL_FMAP_3A_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_3A_QID_MAX", - TRQ_SEL_FMAP_3A_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_3A_QID_BASE", - TRQ_SEL_FMAP_3A_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_3b_field_info[] = { - {"TRQ_SEL_FMAP_3B_RSVD_1", - TRQ_SEL_FMAP_3B_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_3B_QID_MAX", - TRQ_SEL_FMAP_3B_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_3B_QID_BASE", - TRQ_SEL_FMAP_3B_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_3c_field_info[] = { - {"TRQ_SEL_FMAP_3C_RSVD_1", - TRQ_SEL_FMAP_3C_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_3C_QID_MAX", - TRQ_SEL_FMAP_3C_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_3C_QID_BASE", - TRQ_SEL_FMAP_3C_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_3d_field_info[] = { - {"TRQ_SEL_FMAP_3D_RSVD_1", - TRQ_SEL_FMAP_3D_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_3D_QID_MAX", - TRQ_SEL_FMAP_3D_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_3D_QID_BASE", - TRQ_SEL_FMAP_3D_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_3e_field_info[] = { - {"TRQ_SEL_FMAP_3E_RSVD_1", - TRQ_SEL_FMAP_3E_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_3E_QID_MAX", - TRQ_SEL_FMAP_3E_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_3E_QID_BASE", - TRQ_SEL_FMAP_3E_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_3f_field_info[] = { - {"TRQ_SEL_FMAP_3F_RSVD_1", - TRQ_SEL_FMAP_3F_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_3F_QID_MAX", - TRQ_SEL_FMAP_3F_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_3F_QID_BASE", - TRQ_SEL_FMAP_3F_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_40_field_info[] = { - {"TRQ_SEL_FMAP_40_RSVD_1", - TRQ_SEL_FMAP_40_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_40_QID_MAX", - TRQ_SEL_FMAP_40_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_40_QID_BASE", - TRQ_SEL_FMAP_40_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_41_field_info[] = { - {"TRQ_SEL_FMAP_41_RSVD_1", - TRQ_SEL_FMAP_41_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_41_QID_MAX", - TRQ_SEL_FMAP_41_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_41_QID_BASE", - TRQ_SEL_FMAP_41_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_42_field_info[] = { - {"TRQ_SEL_FMAP_42_RSVD_1", - TRQ_SEL_FMAP_42_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_42_QID_MAX", - TRQ_SEL_FMAP_42_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_42_QID_BASE", - TRQ_SEL_FMAP_42_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_43_field_info[] = { - {"TRQ_SEL_FMAP_43_RSVD_1", - TRQ_SEL_FMAP_43_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_43_QID_MAX", - TRQ_SEL_FMAP_43_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_43_QID_BASE", - TRQ_SEL_FMAP_43_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_44_field_info[] = { - {"TRQ_SEL_FMAP_44_RSVD_1", - TRQ_SEL_FMAP_44_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_44_QID_MAX", - TRQ_SEL_FMAP_44_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_44_QID_BASE", - TRQ_SEL_FMAP_44_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_45_field_info[] = { - {"TRQ_SEL_FMAP_45_RSVD_1", - TRQ_SEL_FMAP_45_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_45_QID_MAX", - TRQ_SEL_FMAP_45_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_45_QID_BASE", - TRQ_SEL_FMAP_45_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_46_field_info[] = { - {"TRQ_SEL_FMAP_46_RSVD_1", - TRQ_SEL_FMAP_46_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_46_QID_MAX", - TRQ_SEL_FMAP_46_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_46_QID_BASE", - TRQ_SEL_FMAP_46_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_47_field_info[] = { - {"TRQ_SEL_FMAP_47_RSVD_1", - TRQ_SEL_FMAP_47_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_47_QID_MAX", - TRQ_SEL_FMAP_47_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_47_QID_BASE", - TRQ_SEL_FMAP_47_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_48_field_info[] = { - {"TRQ_SEL_FMAP_48_RSVD_1", - TRQ_SEL_FMAP_48_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_48_QID_MAX", - TRQ_SEL_FMAP_48_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_48_QID_BASE", - TRQ_SEL_FMAP_48_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_49_field_info[] = { - {"TRQ_SEL_FMAP_49_RSVD_1", - TRQ_SEL_FMAP_49_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_49_QID_MAX", - TRQ_SEL_FMAP_49_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_49_QID_BASE", - TRQ_SEL_FMAP_49_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_4a_field_info[] = { - {"TRQ_SEL_FMAP_4A_RSVD_1", - TRQ_SEL_FMAP_4A_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_4A_QID_MAX", - TRQ_SEL_FMAP_4A_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_4A_QID_BASE", - TRQ_SEL_FMAP_4A_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_4b_field_info[] = { - {"TRQ_SEL_FMAP_4B_RSVD_1", - TRQ_SEL_FMAP_4B_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_4B_QID_MAX", - TRQ_SEL_FMAP_4B_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_4B_QID_BASE", - TRQ_SEL_FMAP_4B_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_4c_field_info[] = { - {"TRQ_SEL_FMAP_4C_RSVD_1", - TRQ_SEL_FMAP_4C_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_4C_QID_MAX", - TRQ_SEL_FMAP_4C_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_4C_QID_BASE", - TRQ_SEL_FMAP_4C_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_4d_field_info[] = { - {"TRQ_SEL_FMAP_4D_RSVD_1", - TRQ_SEL_FMAP_4D_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_4D_QID_MAX", - TRQ_SEL_FMAP_4D_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_4D_QID_BASE", - TRQ_SEL_FMAP_4D_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_4e_field_info[] = { - {"TRQ_SEL_FMAP_4E_RSVD_1", - TRQ_SEL_FMAP_4E_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_4E_QID_MAX", - TRQ_SEL_FMAP_4E_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_4E_QID_BASE", - TRQ_SEL_FMAP_4E_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_4f_field_info[] = { - {"TRQ_SEL_FMAP_4F_RSVD_1", - TRQ_SEL_FMAP_4F_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_4F_QID_MAX", - TRQ_SEL_FMAP_4F_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_4F_QID_BASE", - TRQ_SEL_FMAP_4F_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_50_field_info[] = { - {"TRQ_SEL_FMAP_50_RSVD_1", - TRQ_SEL_FMAP_50_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_50_QID_MAX", - TRQ_SEL_FMAP_50_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_50_QID_BASE", - TRQ_SEL_FMAP_50_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_51_field_info[] = { - {"TRQ_SEL_FMAP_51_RSVD_1", - TRQ_SEL_FMAP_51_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_51_QID_MAX", - TRQ_SEL_FMAP_51_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_51_QID_BASE", - TRQ_SEL_FMAP_51_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_52_field_info[] = { - {"TRQ_SEL_FMAP_52_RSVD_1", - TRQ_SEL_FMAP_52_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_52_QID_MAX", - TRQ_SEL_FMAP_52_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_52_QID_BASE", - TRQ_SEL_FMAP_52_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_53_field_info[] = { - {"TRQ_SEL_FMAP_53_RSVD_1", - TRQ_SEL_FMAP_53_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_53_QID_MAX", - TRQ_SEL_FMAP_53_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_53_QID_BASE", - TRQ_SEL_FMAP_53_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_54_field_info[] = { - {"TRQ_SEL_FMAP_54_RSVD_1", - TRQ_SEL_FMAP_54_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_54_QID_MAX", - TRQ_SEL_FMAP_54_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_54_QID_BASE", - TRQ_SEL_FMAP_54_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_55_field_info[] = { - {"TRQ_SEL_FMAP_55_RSVD_1", - TRQ_SEL_FMAP_55_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_55_QID_MAX", - TRQ_SEL_FMAP_55_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_55_QID_BASE", - TRQ_SEL_FMAP_55_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_56_field_info[] = { - {"TRQ_SEL_FMAP_56_RSVD_1", - TRQ_SEL_FMAP_56_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_56_QID_MAX", - TRQ_SEL_FMAP_56_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_56_QID_BASE", - TRQ_SEL_FMAP_56_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_57_field_info[] = { - {"TRQ_SEL_FMAP_57_RSVD_1", - TRQ_SEL_FMAP_57_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_57_QID_MAX", - TRQ_SEL_FMAP_57_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_57_QID_BASE", - TRQ_SEL_FMAP_57_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_58_field_info[] = { - {"TRQ_SEL_FMAP_58_RSVD_1", - TRQ_SEL_FMAP_58_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_58_QID_MAX", - TRQ_SEL_FMAP_58_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_58_QID_BASE", - TRQ_SEL_FMAP_58_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_59_field_info[] = { - {"TRQ_SEL_FMAP_59_RSVD_1", - TRQ_SEL_FMAP_59_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_59_QID_MAX", - TRQ_SEL_FMAP_59_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_59_QID_BASE", - TRQ_SEL_FMAP_59_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_5a_field_info[] = { - {"TRQ_SEL_FMAP_5A_RSVD_1", - TRQ_SEL_FMAP_5A_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_5A_QID_MAX", - TRQ_SEL_FMAP_5A_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_5A_QID_BASE", - TRQ_SEL_FMAP_5A_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_5b_field_info[] = { - {"TRQ_SEL_FMAP_5B_RSVD_1", - TRQ_SEL_FMAP_5B_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_5B_QID_MAX", - TRQ_SEL_FMAP_5B_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_5B_QID_BASE", - TRQ_SEL_FMAP_5B_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_5c_field_info[] = { - {"TRQ_SEL_FMAP_5C_RSVD_1", - TRQ_SEL_FMAP_5C_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_5C_QID_MAX", - TRQ_SEL_FMAP_5C_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_5C_QID_BASE", - TRQ_SEL_FMAP_5C_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_5d_field_info[] = { - {"TRQ_SEL_FMAP_5D_RSVD_1", - TRQ_SEL_FMAP_5D_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_5D_QID_MAX", - TRQ_SEL_FMAP_5D_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_5D_QID_BASE", - TRQ_SEL_FMAP_5D_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_5e_field_info[] = { - {"TRQ_SEL_FMAP_5E_RSVD_1", - TRQ_SEL_FMAP_5E_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_5E_QID_MAX", - TRQ_SEL_FMAP_5E_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_5E_QID_BASE", - TRQ_SEL_FMAP_5E_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_5f_field_info[] = { - {"TRQ_SEL_FMAP_5F_RSVD_1", - TRQ_SEL_FMAP_5F_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_5F_QID_MAX", - TRQ_SEL_FMAP_5F_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_5F_QID_BASE", - TRQ_SEL_FMAP_5F_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_60_field_info[] = { - {"TRQ_SEL_FMAP_60_RSVD_1", - TRQ_SEL_FMAP_60_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_60_QID_MAX", - TRQ_SEL_FMAP_60_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_60_QID_BASE", - TRQ_SEL_FMAP_60_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_61_field_info[] = { - {"TRQ_SEL_FMAP_61_RSVD_1", - TRQ_SEL_FMAP_61_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_61_QID_MAX", - TRQ_SEL_FMAP_61_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_61_QID_BASE", - TRQ_SEL_FMAP_61_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_62_field_info[] = { - {"TRQ_SEL_FMAP_62_RSVD_1", - TRQ_SEL_FMAP_62_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_62_QID_MAX", - TRQ_SEL_FMAP_62_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_62_QID_BASE", - TRQ_SEL_FMAP_62_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_63_field_info[] = { - {"TRQ_SEL_FMAP_63_RSVD_1", - TRQ_SEL_FMAP_63_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_63_QID_MAX", - TRQ_SEL_FMAP_63_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_63_QID_BASE", - TRQ_SEL_FMAP_63_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_64_field_info[] = { - {"TRQ_SEL_FMAP_64_RSVD_1", - TRQ_SEL_FMAP_64_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_64_QID_MAX", - TRQ_SEL_FMAP_64_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_64_QID_BASE", - TRQ_SEL_FMAP_64_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_65_field_info[] = { - {"TRQ_SEL_FMAP_65_RSVD_1", - TRQ_SEL_FMAP_65_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_65_QID_MAX", - TRQ_SEL_FMAP_65_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_65_QID_BASE", - TRQ_SEL_FMAP_65_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_66_field_info[] = { - {"TRQ_SEL_FMAP_66_RSVD_1", - TRQ_SEL_FMAP_66_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_66_QID_MAX", - TRQ_SEL_FMAP_66_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_66_QID_BASE", - TRQ_SEL_FMAP_66_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_67_field_info[] = { - {"TRQ_SEL_FMAP_67_RSVD_1", - TRQ_SEL_FMAP_67_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_67_QID_MAX", - TRQ_SEL_FMAP_67_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_67_QID_BASE", - TRQ_SEL_FMAP_67_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_68_field_info[] = { - {"TRQ_SEL_FMAP_68_RSVD_1", - TRQ_SEL_FMAP_68_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_68_QID_MAX", - TRQ_SEL_FMAP_68_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_68_QID_BASE", - TRQ_SEL_FMAP_68_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_69_field_info[] = { - {"TRQ_SEL_FMAP_69_RSVD_1", - TRQ_SEL_FMAP_69_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_69_QID_MAX", - TRQ_SEL_FMAP_69_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_69_QID_BASE", - TRQ_SEL_FMAP_69_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_6a_field_info[] = { - {"TRQ_SEL_FMAP_6A_RSVD_1", - TRQ_SEL_FMAP_6A_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_6A_QID_MAX", - TRQ_SEL_FMAP_6A_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_6A_QID_BASE", - TRQ_SEL_FMAP_6A_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_6b_field_info[] = { - {"TRQ_SEL_FMAP_6B_RSVD_1", - TRQ_SEL_FMAP_6B_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_6B_QID_MAX", - TRQ_SEL_FMAP_6B_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_6B_QID_BASE", - TRQ_SEL_FMAP_6B_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_6c_field_info[] = { - {"TRQ_SEL_FMAP_6C_RSVD_1", - TRQ_SEL_FMAP_6C_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_6C_QID_MAX", - TRQ_SEL_FMAP_6C_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_6C_QID_BASE", - TRQ_SEL_FMAP_6C_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_6d_field_info[] = { - {"TRQ_SEL_FMAP_6D_RSVD_1", - TRQ_SEL_FMAP_6D_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_6D_QID_MAX", - TRQ_SEL_FMAP_6D_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_6D_QID_BASE", - TRQ_SEL_FMAP_6D_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_6e_field_info[] = { - {"TRQ_SEL_FMAP_6E_RSVD_1", - TRQ_SEL_FMAP_6E_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_6E_QID_MAX", - TRQ_SEL_FMAP_6E_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_6E_QID_BASE", - TRQ_SEL_FMAP_6E_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_6f_field_info[] = { - {"TRQ_SEL_FMAP_6F_RSVD_1", - TRQ_SEL_FMAP_6F_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_6F_QID_MAX", - TRQ_SEL_FMAP_6F_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_6F_QID_BASE", - TRQ_SEL_FMAP_6F_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_70_field_info[] = { - {"TRQ_SEL_FMAP_70_RSVD_1", - TRQ_SEL_FMAP_70_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_70_QID_MAX", - TRQ_SEL_FMAP_70_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_70_QID_BASE", - TRQ_SEL_FMAP_70_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_71_field_info[] = { - {"TRQ_SEL_FMAP_71_RSVD_1", - TRQ_SEL_FMAP_71_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_71_QID_MAX", - TRQ_SEL_FMAP_71_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_71_QID_BASE", - TRQ_SEL_FMAP_71_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_72_field_info[] = { - {"TRQ_SEL_FMAP_72_RSVD_1", - TRQ_SEL_FMAP_72_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_72_QID_MAX", - TRQ_SEL_FMAP_72_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_72_QID_BASE", - TRQ_SEL_FMAP_72_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_73_field_info[] = { - {"TRQ_SEL_FMAP_73_RSVD_1", - TRQ_SEL_FMAP_73_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_73_QID_MAX", - TRQ_SEL_FMAP_73_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_73_QID_BASE", - TRQ_SEL_FMAP_73_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_74_field_info[] = { - {"TRQ_SEL_FMAP_74_RSVD_1", - TRQ_SEL_FMAP_74_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_74_QID_MAX", - TRQ_SEL_FMAP_74_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_74_QID_BASE", - TRQ_SEL_FMAP_74_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_75_field_info[] = { - {"TRQ_SEL_FMAP_75_RSVD_1", - TRQ_SEL_FMAP_75_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_75_QID_MAX", - TRQ_SEL_FMAP_75_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_75_QID_BASE", - TRQ_SEL_FMAP_75_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_76_field_info[] = { - {"TRQ_SEL_FMAP_76_RSVD_1", - TRQ_SEL_FMAP_76_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_76_QID_MAX", - TRQ_SEL_FMAP_76_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_76_QID_BASE", - TRQ_SEL_FMAP_76_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_77_field_info[] = { - {"TRQ_SEL_FMAP_77_RSVD_1", - TRQ_SEL_FMAP_77_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_77_QID_MAX", - TRQ_SEL_FMAP_77_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_77_QID_BASE", - TRQ_SEL_FMAP_77_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_78_field_info[] = { - {"TRQ_SEL_FMAP_78_RSVD_1", - TRQ_SEL_FMAP_78_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_78_QID_MAX", - TRQ_SEL_FMAP_78_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_78_QID_BASE", - TRQ_SEL_FMAP_78_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_79_field_info[] = { - {"TRQ_SEL_FMAP_79_RSVD_1", - TRQ_SEL_FMAP_79_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_79_QID_MAX", - TRQ_SEL_FMAP_79_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_79_QID_BASE", - TRQ_SEL_FMAP_79_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_7a_field_info[] = { - {"TRQ_SEL_FMAP_7A_RSVD_1", - TRQ_SEL_FMAP_7A_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_7A_QID_MAX", - TRQ_SEL_FMAP_7A_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_7A_QID_BASE", - TRQ_SEL_FMAP_7A_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_7b_field_info[] = { - {"TRQ_SEL_FMAP_7B_RSVD_1", - TRQ_SEL_FMAP_7B_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_7B_QID_MAX", - TRQ_SEL_FMAP_7B_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_7B_QID_BASE", - TRQ_SEL_FMAP_7B_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_7c_field_info[] = { - {"TRQ_SEL_FMAP_7C_RSVD_1", - TRQ_SEL_FMAP_7C_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_7C_QID_MAX", - TRQ_SEL_FMAP_7C_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_7C_QID_BASE", - TRQ_SEL_FMAP_7C_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_7d_field_info[] = { - {"TRQ_SEL_FMAP_7D_RSVD_1", - TRQ_SEL_FMAP_7D_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_7D_QID_MAX", - TRQ_SEL_FMAP_7D_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_7D_QID_BASE", - TRQ_SEL_FMAP_7D_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_7e_field_info[] = { - {"TRQ_SEL_FMAP_7E_RSVD_1", - TRQ_SEL_FMAP_7E_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_7E_QID_MAX", - TRQ_SEL_FMAP_7E_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_7E_QID_BASE", - TRQ_SEL_FMAP_7E_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_7f_field_info[] = { - {"TRQ_SEL_FMAP_7F_RSVD_1", - TRQ_SEL_FMAP_7F_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_7F_QID_MAX", - TRQ_SEL_FMAP_7F_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_7F_QID_BASE", - TRQ_SEL_FMAP_7F_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_80_field_info[] = { - {"TRQ_SEL_FMAP_80_RSVD_1", - TRQ_SEL_FMAP_80_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_80_QID_MAX", - TRQ_SEL_FMAP_80_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_80_QID_BASE", - TRQ_SEL_FMAP_80_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_81_field_info[] = { - {"TRQ_SEL_FMAP_81_RSVD_1", - TRQ_SEL_FMAP_81_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_81_QID_MAX", - TRQ_SEL_FMAP_81_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_81_QID_BASE", - TRQ_SEL_FMAP_81_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_82_field_info[] = { - {"TRQ_SEL_FMAP_82_RSVD_1", - TRQ_SEL_FMAP_82_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_82_QID_MAX", - TRQ_SEL_FMAP_82_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_82_QID_BASE", - TRQ_SEL_FMAP_82_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_83_field_info[] = { - {"TRQ_SEL_FMAP_83_RSVD_1", - TRQ_SEL_FMAP_83_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_83_QID_MAX", - TRQ_SEL_FMAP_83_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_83_QID_BASE", - TRQ_SEL_FMAP_83_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_84_field_info[] = { - {"TRQ_SEL_FMAP_84_RSVD_1", - TRQ_SEL_FMAP_84_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_84_QID_MAX", - TRQ_SEL_FMAP_84_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_84_QID_BASE", - TRQ_SEL_FMAP_84_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_85_field_info[] = { - {"TRQ_SEL_FMAP_85_RSVD_1", - TRQ_SEL_FMAP_85_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_85_QID_MAX", - TRQ_SEL_FMAP_85_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_85_QID_BASE", - TRQ_SEL_FMAP_85_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_86_field_info[] = { - {"TRQ_SEL_FMAP_86_RSVD_1", - TRQ_SEL_FMAP_86_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_86_QID_MAX", - TRQ_SEL_FMAP_86_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_86_QID_BASE", - TRQ_SEL_FMAP_86_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_87_field_info[] = { - {"TRQ_SEL_FMAP_87_RSVD_1", - TRQ_SEL_FMAP_87_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_87_QID_MAX", - TRQ_SEL_FMAP_87_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_87_QID_BASE", - TRQ_SEL_FMAP_87_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_88_field_info[] = { - {"TRQ_SEL_FMAP_88_RSVD_1", - TRQ_SEL_FMAP_88_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_88_QID_MAX", - TRQ_SEL_FMAP_88_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_88_QID_BASE", - TRQ_SEL_FMAP_88_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_89_field_info[] = { - {"TRQ_SEL_FMAP_89_RSVD_1", - TRQ_SEL_FMAP_89_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_89_QID_MAX", - TRQ_SEL_FMAP_89_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_89_QID_BASE", - TRQ_SEL_FMAP_89_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_8a_field_info[] = { - {"TRQ_SEL_FMAP_8A_RSVD_1", - TRQ_SEL_FMAP_8A_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_8A_QID_MAX", - TRQ_SEL_FMAP_8A_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_8A_QID_BASE", - TRQ_SEL_FMAP_8A_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_8b_field_info[] = { - {"TRQ_SEL_FMAP_8B_RSVD_1", - TRQ_SEL_FMAP_8B_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_8B_QID_MAX", - TRQ_SEL_FMAP_8B_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_8B_QID_BASE", - TRQ_SEL_FMAP_8B_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_8c_field_info[] = { - {"TRQ_SEL_FMAP_8C_RSVD_1", - TRQ_SEL_FMAP_8C_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_8C_QID_MAX", - TRQ_SEL_FMAP_8C_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_8C_QID_BASE", - TRQ_SEL_FMAP_8C_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_8d_field_info[] = { - {"TRQ_SEL_FMAP_8D_RSVD_1", - TRQ_SEL_FMAP_8D_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_8D_QID_MAX", - TRQ_SEL_FMAP_8D_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_8D_QID_BASE", - TRQ_SEL_FMAP_8D_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_8e_field_info[] = { - {"TRQ_SEL_FMAP_8E_RSVD_1", - TRQ_SEL_FMAP_8E_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_8E_QID_MAX", - TRQ_SEL_FMAP_8E_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_8E_QID_BASE", - TRQ_SEL_FMAP_8E_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_8f_field_info[] = { - {"TRQ_SEL_FMAP_8F_RSVD_1", - TRQ_SEL_FMAP_8F_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_8F_QID_MAX", - TRQ_SEL_FMAP_8F_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_8F_QID_BASE", - TRQ_SEL_FMAP_8F_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_90_field_info[] = { - {"TRQ_SEL_FMAP_90_RSVD_1", - TRQ_SEL_FMAP_90_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_90_QID_MAX", - TRQ_SEL_FMAP_90_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_90_QID_BASE", - TRQ_SEL_FMAP_90_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_91_field_info[] = { - {"TRQ_SEL_FMAP_91_RSVD_1", - TRQ_SEL_FMAP_91_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_91_QID_MAX", - TRQ_SEL_FMAP_91_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_91_QID_BASE", - TRQ_SEL_FMAP_91_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_92_field_info[] = { - {"TRQ_SEL_FMAP_92_RSVD_1", - TRQ_SEL_FMAP_92_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_92_QID_MAX", - TRQ_SEL_FMAP_92_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_92_QID_BASE", - TRQ_SEL_FMAP_92_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_93_field_info[] = { - {"TRQ_SEL_FMAP_93_RSVD_1", - TRQ_SEL_FMAP_93_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_93_QID_MAX", - TRQ_SEL_FMAP_93_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_93_QID_BASE", - TRQ_SEL_FMAP_93_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_94_field_info[] = { - {"TRQ_SEL_FMAP_94_RSVD_1", - TRQ_SEL_FMAP_94_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_94_QID_MAX", - TRQ_SEL_FMAP_94_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_94_QID_BASE", - TRQ_SEL_FMAP_94_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_95_field_info[] = { - {"TRQ_SEL_FMAP_95_RSVD_1", - TRQ_SEL_FMAP_95_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_95_QID_MAX", - TRQ_SEL_FMAP_95_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_95_QID_BASE", - TRQ_SEL_FMAP_95_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_96_field_info[] = { - {"TRQ_SEL_FMAP_96_RSVD_1", - TRQ_SEL_FMAP_96_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_96_QID_MAX", - TRQ_SEL_FMAP_96_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_96_QID_BASE", - TRQ_SEL_FMAP_96_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_97_field_info[] = { - {"TRQ_SEL_FMAP_97_RSVD_1", - TRQ_SEL_FMAP_97_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_97_QID_MAX", - TRQ_SEL_FMAP_97_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_97_QID_BASE", - TRQ_SEL_FMAP_97_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_98_field_info[] = { - {"TRQ_SEL_FMAP_98_RSVD_1", - TRQ_SEL_FMAP_98_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_98_QID_MAX", - TRQ_SEL_FMAP_98_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_98_QID_BASE", - TRQ_SEL_FMAP_98_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_99_field_info[] = { - {"TRQ_SEL_FMAP_99_RSVD_1", - TRQ_SEL_FMAP_99_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_99_QID_MAX", - TRQ_SEL_FMAP_99_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_99_QID_BASE", - TRQ_SEL_FMAP_99_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_9a_field_info[] = { - {"TRQ_SEL_FMAP_9A_RSVD_1", - TRQ_SEL_FMAP_9A_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_9A_QID_MAX", - TRQ_SEL_FMAP_9A_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_9A_QID_BASE", - TRQ_SEL_FMAP_9A_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_9b_field_info[] = { - {"TRQ_SEL_FMAP_9B_RSVD_1", - TRQ_SEL_FMAP_9B_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_9B_QID_MAX", - TRQ_SEL_FMAP_9B_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_9B_QID_BASE", - TRQ_SEL_FMAP_9B_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_9c_field_info[] = { - {"TRQ_SEL_FMAP_9C_RSVD_1", - TRQ_SEL_FMAP_9C_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_9C_QID_MAX", - TRQ_SEL_FMAP_9C_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_9C_QID_BASE", - TRQ_SEL_FMAP_9C_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_9d_field_info[] = { - {"TRQ_SEL_FMAP_9D_RSVD_1", - TRQ_SEL_FMAP_9D_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_9D_QID_MAX", - TRQ_SEL_FMAP_9D_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_9D_QID_BASE", - TRQ_SEL_FMAP_9D_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_9e_field_info[] = { - {"TRQ_SEL_FMAP_9E_RSVD_1", - TRQ_SEL_FMAP_9E_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_9E_QID_MAX", - TRQ_SEL_FMAP_9E_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_9E_QID_BASE", - TRQ_SEL_FMAP_9E_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_9f_field_info[] = { - {"TRQ_SEL_FMAP_9F_RSVD_1", - TRQ_SEL_FMAP_9F_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_9F_QID_MAX", - TRQ_SEL_FMAP_9F_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_9F_QID_BASE", - TRQ_SEL_FMAP_9F_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_a0_field_info[] = { - {"TRQ_SEL_FMAP_A0_RSVD_1", - TRQ_SEL_FMAP_A0_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_A0_QID_MAX", - TRQ_SEL_FMAP_A0_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_A0_QID_BASE", - TRQ_SEL_FMAP_A0_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_a1_field_info[] = { - {"TRQ_SEL_FMAP_A1_RSVD_1", - TRQ_SEL_FMAP_A1_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_A1_QID_MAX", - TRQ_SEL_FMAP_A1_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_A1_QID_BASE", - TRQ_SEL_FMAP_A1_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_a2_field_info[] = { - {"TRQ_SEL_FMAP_A2_RSVD_1", - TRQ_SEL_FMAP_A2_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_A2_QID_MAX", - TRQ_SEL_FMAP_A2_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_A2_QID_BASE", - TRQ_SEL_FMAP_A2_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_a3_field_info[] = { - {"TRQ_SEL_FMAP_A3_RSVD_1", - TRQ_SEL_FMAP_A3_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_A3_QID_MAX", - TRQ_SEL_FMAP_A3_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_A3_QID_BASE", - TRQ_SEL_FMAP_A3_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_a4_field_info[] = { - {"TRQ_SEL_FMAP_A4_RSVD_1", - TRQ_SEL_FMAP_A4_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_A4_QID_MAX", - TRQ_SEL_FMAP_A4_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_A4_QID_BASE", - TRQ_SEL_FMAP_A4_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_a5_field_info[] = { - {"TRQ_SEL_FMAP_A5_RSVD_1", - TRQ_SEL_FMAP_A5_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_A5_QID_MAX", - TRQ_SEL_FMAP_A5_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_A5_QID_BASE", - TRQ_SEL_FMAP_A5_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_a6_field_info[] = { - {"TRQ_SEL_FMAP_A6_RSVD_1", - TRQ_SEL_FMAP_A6_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_A6_QID_MAX", - TRQ_SEL_FMAP_A6_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_A6_QID_BASE", - TRQ_SEL_FMAP_A6_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_a7_field_info[] = { - {"TRQ_SEL_FMAP_A7_RSVD_1", - TRQ_SEL_FMAP_A7_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_A7_QID_MAX", - TRQ_SEL_FMAP_A7_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_A7_QID_BASE", - TRQ_SEL_FMAP_A7_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_a8_field_info[] = { - {"TRQ_SEL_FMAP_A8_RSVD_1", - TRQ_SEL_FMAP_A8_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_A8_QID_MAX", - TRQ_SEL_FMAP_A8_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_A8_QID_BASE", - TRQ_SEL_FMAP_A8_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_a9_field_info[] = { - {"TRQ_SEL_FMAP_A9_RSVD_1", - TRQ_SEL_FMAP_A9_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_A9_QID_MAX", - TRQ_SEL_FMAP_A9_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_A9_QID_BASE", - TRQ_SEL_FMAP_A9_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_aa_field_info[] = { - {"TRQ_SEL_FMAP_AA_RSVD_1", - TRQ_SEL_FMAP_AA_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_AA_QID_MAX", - TRQ_SEL_FMAP_AA_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_AA_QID_BASE", - TRQ_SEL_FMAP_AA_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_ab_field_info[] = { - {"TRQ_SEL_FMAP_AB_RSVD_1", - TRQ_SEL_FMAP_AB_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_AB_QID_MAX", - TRQ_SEL_FMAP_AB_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_AB_QID_BASE", - TRQ_SEL_FMAP_AB_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_ac_field_info[] = { - {"TRQ_SEL_FMAP_AC_RSVD_1", - TRQ_SEL_FMAP_AC_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_AC_QID_MAX", - TRQ_SEL_FMAP_AC_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_AC_QID_BASE", - TRQ_SEL_FMAP_AC_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_ad_field_info[] = { - {"TRQ_SEL_FMAP_AD_RSVD_1", - TRQ_SEL_FMAP_AD_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_AD_QID_MAX", - TRQ_SEL_FMAP_AD_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_AD_QID_BASE", - TRQ_SEL_FMAP_AD_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_ae_field_info[] = { - {"TRQ_SEL_FMAP_AE_RSVD_1", - TRQ_SEL_FMAP_AE_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_AE_QID_MAX", - TRQ_SEL_FMAP_AE_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_AE_QID_BASE", - TRQ_SEL_FMAP_AE_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_af_field_info[] = { - {"TRQ_SEL_FMAP_AF_RSVD_1", - TRQ_SEL_FMAP_AF_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_AF_QID_MAX", - TRQ_SEL_FMAP_AF_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_AF_QID_BASE", - TRQ_SEL_FMAP_AF_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_b0_field_info[] = { - {"TRQ_SEL_FMAP_B0_RSVD_1", - TRQ_SEL_FMAP_B0_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_B0_QID_MAX", - TRQ_SEL_FMAP_B0_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_B0_QID_BASE", - TRQ_SEL_FMAP_B0_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_b1_field_info[] = { - {"TRQ_SEL_FMAP_B1_RSVD_1", - TRQ_SEL_FMAP_B1_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_B1_QID_MAX", - TRQ_SEL_FMAP_B1_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_B1_QID_BASE", - TRQ_SEL_FMAP_B1_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_b2_field_info[] = { - {"TRQ_SEL_FMAP_B2_RSVD_1", - TRQ_SEL_FMAP_B2_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_B2_QID_MAX", - TRQ_SEL_FMAP_B2_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_B2_QID_BASE", - TRQ_SEL_FMAP_B2_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_b3_field_info[] = { - {"TRQ_SEL_FMAP_B3_RSVD_1", - TRQ_SEL_FMAP_B3_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_B3_QID_MAX", - TRQ_SEL_FMAP_B3_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_B3_QID_BASE", - TRQ_SEL_FMAP_B3_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_b4_field_info[] = { - {"TRQ_SEL_FMAP_B4_RSVD_1", - TRQ_SEL_FMAP_B4_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_B4_QID_MAX", - TRQ_SEL_FMAP_B4_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_B4_QID_BASE", - TRQ_SEL_FMAP_B4_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_b5_field_info[] = { - {"TRQ_SEL_FMAP_B5_RSVD_1", - TRQ_SEL_FMAP_B5_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_B5_QID_MAX", - TRQ_SEL_FMAP_B5_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_B5_QID_BASE", - TRQ_SEL_FMAP_B5_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_b6_field_info[] = { - {"TRQ_SEL_FMAP_B6_RSVD_1", - TRQ_SEL_FMAP_B6_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_B6_QID_MAX", - TRQ_SEL_FMAP_B6_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_B6_QID_BASE", - TRQ_SEL_FMAP_B6_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_b7_field_info[] = { - {"TRQ_SEL_FMAP_B7_RSVD_1", - TRQ_SEL_FMAP_B7_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_B7_QID_MAX", - TRQ_SEL_FMAP_B7_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_B7_QID_BASE", - TRQ_SEL_FMAP_B7_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_b8_field_info[] = { - {"TRQ_SEL_FMAP_B8_RSVD_1", - TRQ_SEL_FMAP_B8_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_B8_QID_MAX", - TRQ_SEL_FMAP_B8_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_B8_QID_BASE", - TRQ_SEL_FMAP_B8_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_b9_field_info[] = { - {"TRQ_SEL_FMAP_B9_RSVD_1", - TRQ_SEL_FMAP_B9_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_B9_QID_MAX", - TRQ_SEL_FMAP_B9_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_B9_QID_BASE", - TRQ_SEL_FMAP_B9_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_ba_field_info[] = { - {"TRQ_SEL_FMAP_BA_RSVD_1", - TRQ_SEL_FMAP_BA_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_BA_QID_MAX", - TRQ_SEL_FMAP_BA_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_BA_QID_BASE", - TRQ_SEL_FMAP_BA_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_bb_field_info[] = { - {"TRQ_SEL_FMAP_BB_RSVD_1", - TRQ_SEL_FMAP_BB_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_BB_QID_MAX", - TRQ_SEL_FMAP_BB_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_BB_QID_BASE", - TRQ_SEL_FMAP_BB_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_bc_field_info[] = { - {"TRQ_SEL_FMAP_BC_RSVD_1", - TRQ_SEL_FMAP_BC_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_BC_QID_MAX", - TRQ_SEL_FMAP_BC_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_BC_QID_BASE", - TRQ_SEL_FMAP_BC_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_bd_field_info[] = { - {"TRQ_SEL_FMAP_BD_RSVD_1", - TRQ_SEL_FMAP_BD_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_BD_QID_MAX", - TRQ_SEL_FMAP_BD_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_BD_QID_BASE", - TRQ_SEL_FMAP_BD_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_be_field_info[] = { - {"TRQ_SEL_FMAP_BE_RSVD_1", - TRQ_SEL_FMAP_BE_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_BE_QID_MAX", - TRQ_SEL_FMAP_BE_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_BE_QID_BASE", - TRQ_SEL_FMAP_BE_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_bf_field_info[] = { - {"TRQ_SEL_FMAP_BF_RSVD_1", - TRQ_SEL_FMAP_BF_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_BF_QID_MAX", - TRQ_SEL_FMAP_BF_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_BF_QID_BASE", - TRQ_SEL_FMAP_BF_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_c0_field_info[] = { - {"TRQ_SEL_FMAP_C0_RSVD_1", - TRQ_SEL_FMAP_C0_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_C0_QID_MAX", - TRQ_SEL_FMAP_C0_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_C0_QID_BASE", - TRQ_SEL_FMAP_C0_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_c1_field_info[] = { - {"TRQ_SEL_FMAP_C1_RSVD_1", - TRQ_SEL_FMAP_C1_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_C1_QID_MAX", - TRQ_SEL_FMAP_C1_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_C1_QID_BASE", - TRQ_SEL_FMAP_C1_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_c2_field_info[] = { - {"TRQ_SEL_FMAP_C2_RSVD_1", - TRQ_SEL_FMAP_C2_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_C2_QID_MAX", - TRQ_SEL_FMAP_C2_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_C2_QID_BASE", - TRQ_SEL_FMAP_C2_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_c3_field_info[] = { - {"TRQ_SEL_FMAP_C3_RSVD_1", - TRQ_SEL_FMAP_C3_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_C3_QID_MAX", - TRQ_SEL_FMAP_C3_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_C3_QID_BASE", - TRQ_SEL_FMAP_C3_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_c4_field_info[] = { - {"TRQ_SEL_FMAP_C4_RSVD_1", - TRQ_SEL_FMAP_C4_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_C4_QID_MAX", - TRQ_SEL_FMAP_C4_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_C4_QID_BASE", - TRQ_SEL_FMAP_C4_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_c5_field_info[] = { - {"TRQ_SEL_FMAP_C5_RSVD_1", - TRQ_SEL_FMAP_C5_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_C5_QID_MAX", - TRQ_SEL_FMAP_C5_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_C5_QID_BASE", - TRQ_SEL_FMAP_C5_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_c6_field_info[] = { - {"TRQ_SEL_FMAP_C6_RSVD_1", - TRQ_SEL_FMAP_C6_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_C6_QID_MAX", - TRQ_SEL_FMAP_C6_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_C6_QID_BASE", - TRQ_SEL_FMAP_C6_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_c7_field_info[] = { - {"TRQ_SEL_FMAP_C7_RSVD_1", - TRQ_SEL_FMAP_C7_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_C7_QID_MAX", - TRQ_SEL_FMAP_C7_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_C7_QID_BASE", - TRQ_SEL_FMAP_C7_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_c8_field_info[] = { - {"TRQ_SEL_FMAP_C8_RSVD_1", - TRQ_SEL_FMAP_C8_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_C8_QID_MAX", - TRQ_SEL_FMAP_C8_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_C8_QID_BASE", - TRQ_SEL_FMAP_C8_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_c9_field_info[] = { - {"TRQ_SEL_FMAP_C9_RSVD_1", - TRQ_SEL_FMAP_C9_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_C9_QID_MAX", - TRQ_SEL_FMAP_C9_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_C9_QID_BASE", - TRQ_SEL_FMAP_C9_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_ca_field_info[] = { - {"TRQ_SEL_FMAP_CA_RSVD_1", - TRQ_SEL_FMAP_CA_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_CA_QID_MAX", - TRQ_SEL_FMAP_CA_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_CA_QID_BASE", - TRQ_SEL_FMAP_CA_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_cb_field_info[] = { - {"TRQ_SEL_FMAP_CB_RSVD_1", - TRQ_SEL_FMAP_CB_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_CB_QID_MAX", - TRQ_SEL_FMAP_CB_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_CB_QID_BASE", - TRQ_SEL_FMAP_CB_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_cc_field_info[] = { - {"TRQ_SEL_FMAP_CC_RSVD_1", - TRQ_SEL_FMAP_CC_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_CC_QID_MAX", - TRQ_SEL_FMAP_CC_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_CC_QID_BASE", - TRQ_SEL_FMAP_CC_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_cd_field_info[] = { - {"TRQ_SEL_FMAP_CD_RSVD_1", - TRQ_SEL_FMAP_CD_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_CD_QID_MAX", - TRQ_SEL_FMAP_CD_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_CD_QID_BASE", - TRQ_SEL_FMAP_CD_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_ce_field_info[] = { - {"TRQ_SEL_FMAP_CE_RSVD_1", - TRQ_SEL_FMAP_CE_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_CE_QID_MAX", - TRQ_SEL_FMAP_CE_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_CE_QID_BASE", - TRQ_SEL_FMAP_CE_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_cf_field_info[] = { - {"TRQ_SEL_FMAP_CF_RSVD_1", - TRQ_SEL_FMAP_CF_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_CF_QID_MAX", - TRQ_SEL_FMAP_CF_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_CF_QID_BASE", - TRQ_SEL_FMAP_CF_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_d0_field_info[] = { - {"TRQ_SEL_FMAP_D0_RSVD_1", - TRQ_SEL_FMAP_D0_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_D0_QID_MAX", - TRQ_SEL_FMAP_D0_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_D0_QID_BASE", - TRQ_SEL_FMAP_D0_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_d1_field_info[] = { - {"TRQ_SEL_FMAP_D1_RSVD_1", - TRQ_SEL_FMAP_D1_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_D1_QID_MAX", - TRQ_SEL_FMAP_D1_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_D1_QID_BASE", - TRQ_SEL_FMAP_D1_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_d2_field_info[] = { - {"TRQ_SEL_FMAP_D2_RSVD_1", - TRQ_SEL_FMAP_D2_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_D2_QID_MAX", - TRQ_SEL_FMAP_D2_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_D2_QID_BASE", - TRQ_SEL_FMAP_D2_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_d3_field_info[] = { - {"TRQ_SEL_FMAP_D3_RSVD_1", - TRQ_SEL_FMAP_D3_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_D3_QID_MAX", - TRQ_SEL_FMAP_D3_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_D3_QID_BASE", - TRQ_SEL_FMAP_D3_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_d4_field_info[] = { - {"TRQ_SEL_FMAP_D4_RSVD_1", - TRQ_SEL_FMAP_D4_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_D4_QID_MAX", - TRQ_SEL_FMAP_D4_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_D4_QID_BASE", - TRQ_SEL_FMAP_D4_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_d5_field_info[] = { - {"TRQ_SEL_FMAP_D5_RSVD_1", - TRQ_SEL_FMAP_D5_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_D5_QID_MAX", - TRQ_SEL_FMAP_D5_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_D5_QID_BASE", - TRQ_SEL_FMAP_D5_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_d6_field_info[] = { - {"TRQ_SEL_FMAP_D6_RSVD_1", - TRQ_SEL_FMAP_D6_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_D6_QID_MAX", - TRQ_SEL_FMAP_D6_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_D6_QID_BASE", - TRQ_SEL_FMAP_D6_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_d7_field_info[] = { - {"TRQ_SEL_FMAP_D7_RSVD_1", - TRQ_SEL_FMAP_D7_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_D7_QID_MAX", - TRQ_SEL_FMAP_D7_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_D7_QID_BASE", - TRQ_SEL_FMAP_D7_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_d8_field_info[] = { - {"TRQ_SEL_FMAP_D8_RSVD_1", - TRQ_SEL_FMAP_D8_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_D8_QID_MAX", - TRQ_SEL_FMAP_D8_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_D8_QID_BASE", - TRQ_SEL_FMAP_D8_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_d9_field_info[] = { - {"TRQ_SEL_FMAP_D9_RSVD_1", - TRQ_SEL_FMAP_D9_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_D9_QID_MAX", - TRQ_SEL_FMAP_D9_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_D9_QID_BASE", - TRQ_SEL_FMAP_D9_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_da_field_info[] = { - {"TRQ_SEL_FMAP_DA_RSVD_1", - TRQ_SEL_FMAP_DA_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_DA_QID_MAX", - TRQ_SEL_FMAP_DA_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_DA_QID_BASE", - TRQ_SEL_FMAP_DA_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_db_field_info[] = { - {"TRQ_SEL_FMAP_DB_RSVD_1", - TRQ_SEL_FMAP_DB_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_DB_QID_MAX", - TRQ_SEL_FMAP_DB_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_DB_QID_BASE", - TRQ_SEL_FMAP_DB_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_dc_field_info[] = { - {"TRQ_SEL_FMAP_DC_RSVD_1", - TRQ_SEL_FMAP_DC_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_DC_QID_MAX", - TRQ_SEL_FMAP_DC_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_DC_QID_BASE", - TRQ_SEL_FMAP_DC_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_dd_field_info[] = { - {"TRQ_SEL_FMAP_DD_RSVD_1", - TRQ_SEL_FMAP_DD_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_DD_QID_MAX", - TRQ_SEL_FMAP_DD_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_DD_QID_BASE", - TRQ_SEL_FMAP_DD_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_de_field_info[] = { - {"TRQ_SEL_FMAP_DE_RSVD_1", - TRQ_SEL_FMAP_DE_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_DE_QID_MAX", - TRQ_SEL_FMAP_DE_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_DE_QID_BASE", - TRQ_SEL_FMAP_DE_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_df_field_info[] = { - {"TRQ_SEL_FMAP_DF_RSVD_1", - TRQ_SEL_FMAP_DF_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_DF_QID_MAX", - TRQ_SEL_FMAP_DF_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_DF_QID_BASE", - TRQ_SEL_FMAP_DF_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_e0_field_info[] = { - {"TRQ_SEL_FMAP_E0_RSVD_1", - TRQ_SEL_FMAP_E0_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_E0_QID_MAX", - TRQ_SEL_FMAP_E0_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_E0_QID_BASE", - TRQ_SEL_FMAP_E0_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_e1_field_info[] = { - {"TRQ_SEL_FMAP_E1_RSVD_1", - TRQ_SEL_FMAP_E1_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_E1_QID_MAX", - TRQ_SEL_FMAP_E1_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_E1_QID_BASE", - TRQ_SEL_FMAP_E1_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_e2_field_info[] = { - {"TRQ_SEL_FMAP_E2_RSVD_1", - TRQ_SEL_FMAP_E2_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_E2_QID_MAX", - TRQ_SEL_FMAP_E2_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_E2_QID_BASE", - TRQ_SEL_FMAP_E2_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_e3_field_info[] = { - {"TRQ_SEL_FMAP_E3_RSVD_1", - TRQ_SEL_FMAP_E3_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_E3_QID_MAX", - TRQ_SEL_FMAP_E3_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_E3_QID_BASE", - TRQ_SEL_FMAP_E3_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_e4_field_info[] = { - {"TRQ_SEL_FMAP_E4_RSVD_1", - TRQ_SEL_FMAP_E4_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_E4_QID_MAX", - TRQ_SEL_FMAP_E4_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_E4_QID_BASE", - TRQ_SEL_FMAP_E4_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_e5_field_info[] = { - {"TRQ_SEL_FMAP_E5_RSVD_1", - TRQ_SEL_FMAP_E5_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_E5_QID_MAX", - TRQ_SEL_FMAP_E5_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_E5_QID_BASE", - TRQ_SEL_FMAP_E5_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_e6_field_info[] = { - {"TRQ_SEL_FMAP_E6_RSVD_1", - TRQ_SEL_FMAP_E6_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_E6_QID_MAX", - TRQ_SEL_FMAP_E6_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_E6_QID_BASE", - TRQ_SEL_FMAP_E6_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_e7_field_info[] = { - {"TRQ_SEL_FMAP_E7_RSVD_1", - TRQ_SEL_FMAP_E7_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_E7_QID_MAX", - TRQ_SEL_FMAP_E7_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_E7_QID_BASE", - TRQ_SEL_FMAP_E7_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_e8_field_info[] = { - {"TRQ_SEL_FMAP_E8_RSVD_1", - TRQ_SEL_FMAP_E8_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_E8_QID_MAX", - TRQ_SEL_FMAP_E8_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_E8_QID_BASE", - TRQ_SEL_FMAP_E8_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_e9_field_info[] = { - {"TRQ_SEL_FMAP_E9_RSVD_1", - TRQ_SEL_FMAP_E9_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_E9_QID_MAX", - TRQ_SEL_FMAP_E9_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_E9_QID_BASE", - TRQ_SEL_FMAP_E9_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_ea_field_info[] = { - {"TRQ_SEL_FMAP_EA_RSVD_1", - TRQ_SEL_FMAP_EA_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_EA_QID_MAX", - TRQ_SEL_FMAP_EA_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_EA_QID_BASE", - TRQ_SEL_FMAP_EA_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_eb_field_info[] = { - {"TRQ_SEL_FMAP_EB_RSVD_1", - TRQ_SEL_FMAP_EB_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_EB_QID_MAX", - TRQ_SEL_FMAP_EB_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_EB_QID_BASE", - TRQ_SEL_FMAP_EB_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_ec_field_info[] = { - {"TRQ_SEL_FMAP_EC_RSVD_1", - TRQ_SEL_FMAP_EC_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_EC_QID_MAX", - TRQ_SEL_FMAP_EC_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_EC_QID_BASE", - TRQ_SEL_FMAP_EC_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_ed_field_info[] = { - {"TRQ_SEL_FMAP_ED_RSVD_1", - TRQ_SEL_FMAP_ED_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_ED_QID_MAX", - TRQ_SEL_FMAP_ED_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_ED_QID_BASE", - TRQ_SEL_FMAP_ED_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_ee_field_info[] = { - {"TRQ_SEL_FMAP_EE_RSVD_1", - TRQ_SEL_FMAP_EE_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_EE_QID_MAX", - TRQ_SEL_FMAP_EE_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_EE_QID_BASE", - TRQ_SEL_FMAP_EE_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_ef_field_info[] = { - {"TRQ_SEL_FMAP_EF_RSVD_1", - TRQ_SEL_FMAP_EF_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_EF_QID_MAX", - TRQ_SEL_FMAP_EF_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_EF_QID_BASE", - TRQ_SEL_FMAP_EF_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_f0_field_info[] = { - {"TRQ_SEL_FMAP_F0_RSVD_1", - TRQ_SEL_FMAP_F0_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_F0_QID_MAX", - TRQ_SEL_FMAP_F0_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_F0_QID_BASE", - TRQ_SEL_FMAP_F0_QID_BASE_MASK}, -}; - - -static struct regfield_info - ind_ctxt_data_3_field_info[] = { - {"IND_CTXT_DATA_3_DATA", - IND_CTXT_DATA_3_DATA_MASK}, -}; - - -static struct regfield_info - ind_ctxt_data_2_field_info[] = { - {"IND_CTXT_DATA_2_DATA", - IND_CTXT_DATA_2_DATA_MASK}, -}; - - -static struct regfield_info - ind_ctxt_data_1_field_info[] = { - {"IND_CTXT_DATA_1_DATA", - IND_CTXT_DATA_1_DATA_MASK}, -}; - - -static struct regfield_info - ind_ctxt_data_0_field_info[] = { - {"IND_CTXT_DATA_0_DATA", - IND_CTXT_DATA_0_DATA_MASK}, -}; - - -static struct regfield_info - ind_ctxt3_field_info[] = { - {"IND_CTXT3", - IND_CTXT3_MASK}, -}; - - -static struct regfield_info - ind_ctxt2_field_info[] = { - {"IND_CTXT2", - IND_CTXT2_MASK}, -}; - - -static struct regfield_info - ind_ctxt1_field_info[] = { - {"IND_CTXT1", - IND_CTXT1_MASK}, -}; - - -static struct regfield_info - ind_ctxt0_field_info[] = { - {"IND_CTXT0", - IND_CTXT0_MASK}, -}; - - -static struct regfield_info - ind_ctxt_cmd_field_info[] = { - {"IND_CTXT_CMD_RSVD_1", - IND_CTXT_CMD_RSVD_1_MASK}, - {"IND_CTXT_CMD_QID", - IND_CTXT_CMD_QID_MASK}, - {"IND_CTXT_CMD_OP", - IND_CTXT_CMD_OP_MASK}, - {"IND_CTXT_CMD_SET", - IND_CTXT_CMD_SET_MASK}, - {"IND_CTXT_CMD_BUSY", - IND_CTXT_CMD_BUSY_MASK}, -}; - - -static struct regfield_info - c2h_timer_cnt_1_field_info[] = { - {"C2H_TIMER_CNT_1_RSVD_1", - C2H_TIMER_CNT_1_RSVD_1_MASK}, - {"C2H_TIMER_CNT_1", - C2H_TIMER_CNT_1_MASK}, -}; - - -static struct regfield_info - c2h_timer_cnt_2_field_info[] = { - {"C2H_TIMER_CNT_2_RSVD_1", - C2H_TIMER_CNT_2_RSVD_1_MASK}, - {"C2H_TIMER_CNT_2", - C2H_TIMER_CNT_2_MASK}, -}; - - -static struct regfield_info - c2h_timer_cnt_3_field_info[] = { - {"C2H_TIMER_CNT_3_RSVD_1", - C2H_TIMER_CNT_3_RSVD_1_MASK}, - {"C2H_TIMER_CNT_3", - C2H_TIMER_CNT_3_MASK}, -}; - - -static struct regfield_info - c2h_timer_cnt_4_field_info[] = { - {"C2H_TIMER_CNT_4_RSVD_1", - C2H_TIMER_CNT_4_RSVD_1_MASK}, - {"C2H_TIMER_CNT_4", - C2H_TIMER_CNT_4_MASK}, -}; - - -static struct regfield_info - c2h_timer_cnt_5_field_info[] = { - {"C2H_TIMER_CNT_5_RSVD_1", - C2H_TIMER_CNT_5_RSVD_1_MASK}, - {"C2H_TIMER_CNT_5", - C2H_TIMER_CNT_5_MASK}, -}; - - -static struct regfield_info - c2h_timer_cnt_6_field_info[] = { - {"C2H_TIMER_CNT_6_RSVD_1", - C2H_TIMER_CNT_6_RSVD_1_MASK}, - {"C2H_TIMER_CNT_6", - C2H_TIMER_CNT_6_MASK}, -}; - - -static struct regfield_info - c2h_timer_cnt_7_field_info[] = { - {"C2H_TIMER_CNT_7_RSVD_1", - C2H_TIMER_CNT_7_RSVD_1_MASK}, - {"C2H_TIMER_CNT_7", - C2H_TIMER_CNT_7_MASK}, -}; - - -static struct regfield_info - c2h_timer_cnt_8_field_info[] = { - {"C2H_TIMER_CNT_8_RSVD_1", - C2H_TIMER_CNT_8_RSVD_1_MASK}, - {"C2H_TIMER_CNT_8", - C2H_TIMER_CNT_8_MASK}, -}; - - -static struct regfield_info - c2h_timer_cnt_9_field_info[] = { - {"C2H_TIMER_CNT_9_RSVD_1", - C2H_TIMER_CNT_9_RSVD_1_MASK}, - {"C2H_TIMER_CNT_9", - C2H_TIMER_CNT_9_MASK}, -}; - - -static struct regfield_info - c2h_timer_cnt_a_field_info[] = { - {"C2H_TIMER_CNT_A_RSVD_1", - C2H_TIMER_CNT_A_RSVD_1_MASK}, - {"C2H_TIMER_CNT_A", - C2H_TIMER_CNT_A_MASK}, -}; - - -static struct regfield_info - c2h_timer_cnt_b_field_info[] = { - {"C2H_TIMER_CNT_B_RSVD_1", - C2H_TIMER_CNT_B_RSVD_1_MASK}, - {"C2H_TIMER_CNT_B", - C2H_TIMER_CNT_B_MASK}, -}; - - -static struct regfield_info - c2h_timer_cnt_c_field_info[] = { - {"C2H_TIMER_CNT_C_RSVD_1", - C2H_TIMER_CNT_C_RSVD_1_MASK}, - {"C2H_TIMER_CNT_C", - C2H_TIMER_CNT_C_MASK}, -}; - - -static struct regfield_info - c2h_timer_cnt_d_field_info[] = { - {"C2H_TIMER_CNT_D_RSVD_1", - C2H_TIMER_CNT_D_RSVD_1_MASK}, - {"C2H_TIMER_CNT_D", - C2H_TIMER_CNT_D_MASK}, -}; - - -static struct regfield_info - c2h_timer_cnt_e_field_info[] = { - {"C2H_TIMER_CNT_E_RSVD_1", - C2H_TIMER_CNT_E_RSVD_1_MASK}, - {"C2H_TIMER_CNT_E", - C2H_TIMER_CNT_E_MASK}, -}; - - -static struct regfield_info - c2h_timer_cnt_f_field_info[] = { - {"C2H_TIMER_CNT_F_RSVD_1", - C2H_TIMER_CNT_F_RSVD_1_MASK}, - {"C2H_TIMER_CNT_F", - C2H_TIMER_CNT_F_MASK}, -}; - - -static struct regfield_info - c2h_timer_cnt_10_field_info[] = { - {"C2H_TIMER_CNT_10_RSVD_1", - C2H_TIMER_CNT_10_RSVD_1_MASK}, - {"C2H_TIMER_CNT_10", - C2H_TIMER_CNT_10_MASK}, -}; - - -static struct regfield_info - c2h_cnt_th_1_field_info[] = { - {"C2H_CNT_TH_1_RSVD_1", - C2H_CNT_TH_1_RSVD_1_MASK}, - {"C2H_CNT_TH_1_THESHOLD_CNT", - C2H_CNT_TH_1_THESHOLD_CNT_MASK}, -}; - - -static struct regfield_info - c2h_cnt_th_2_field_info[] = { - {"C2H_CNT_TH_2_RSVD_1", - C2H_CNT_TH_2_RSVD_1_MASK}, - {"C2H_CNT_TH_2_THESHOLD_CNT", - C2H_CNT_TH_2_THESHOLD_CNT_MASK}, -}; - - -static struct regfield_info - c2h_cnt_th_3_field_info[] = { - {"C2H_CNT_TH_3_RSVD_1", - C2H_CNT_TH_3_RSVD_1_MASK}, - {"C2H_CNT_TH_3_THESHOLD_CNT", - C2H_CNT_TH_3_THESHOLD_CNT_MASK}, -}; - - -static struct regfield_info - c2h_cnt_th_4_field_info[] = { - {"C2H_CNT_TH_4_RSVD_1", - C2H_CNT_TH_4_RSVD_1_MASK}, - {"C2H_CNT_TH_4_THESHOLD_CNT", - C2H_CNT_TH_4_THESHOLD_CNT_MASK}, -}; - - -static struct regfield_info - c2h_cnt_th_5_field_info[] = { - {"C2H_CNT_TH_5_RSVD_1", - C2H_CNT_TH_5_RSVD_1_MASK}, - {"C2H_CNT_TH_5_THESHOLD_CNT", - C2H_CNT_TH_5_THESHOLD_CNT_MASK}, -}; - - -static struct regfield_info - c2h_cnt_th_6_field_info[] = { - {"C2H_CNT_TH_6_RSVD_1", - C2H_CNT_TH_6_RSVD_1_MASK}, - {"C2H_CNT_TH_6_THESHOLD_CNT", - C2H_CNT_TH_6_THESHOLD_CNT_MASK}, -}; - - -static struct regfield_info - c2h_cnt_th_7_field_info[] = { - {"C2H_CNT_TH_7_RSVD_1", - C2H_CNT_TH_7_RSVD_1_MASK}, - {"C2H_CNT_TH_7_THESHOLD_CNT", - C2H_CNT_TH_7_THESHOLD_CNT_MASK}, -}; - - -static struct regfield_info - c2h_cnt_th_8_field_info[] = { - {"C2H_CNT_TH_8_RSVD_1", - C2H_CNT_TH_8_RSVD_1_MASK}, - {"C2H_CNT_TH_8_THESHOLD_CNT", - C2H_CNT_TH_8_THESHOLD_CNT_MASK}, -}; - - -static struct regfield_info - c2h_cnt_th_9_field_info[] = { - {"C2H_CNT_TH_9_RSVD_1", - C2H_CNT_TH_9_RSVD_1_MASK}, - {"C2H_CNT_TH_9_THESHOLD_CNT", - C2H_CNT_TH_9_THESHOLD_CNT_MASK}, -}; - - -static struct regfield_info - c2h_cnt_th_a_field_info[] = { - {"C2H_CNT_TH_A_RSVD_1", - C2H_CNT_TH_A_RSVD_1_MASK}, - {"C2H_CNT_TH_A_THESHOLD_CNT", - C2H_CNT_TH_A_THESHOLD_CNT_MASK}, -}; - - -static struct regfield_info - c2h_cnt_th_b_field_info[] = { - {"C2H_CNT_TH_B_RSVD_1", - C2H_CNT_TH_B_RSVD_1_MASK}, - {"C2H_CNT_TH_B_THESHOLD_CNT", - C2H_CNT_TH_B_THESHOLD_CNT_MASK}, -}; - - -static struct regfield_info - c2h_cnt_th_c_field_info[] = { - {"C2H_CNT_TH_C_RSVD_1", - C2H_CNT_TH_C_RSVD_1_MASK}, - {"C2H_CNT_TH_C_THESHOLD_CNT", - C2H_CNT_TH_C_THESHOLD_CNT_MASK}, -}; - - -static struct regfield_info - c2h_cnt_th_d_field_info[] = { - {"C2H_CNT_TH_D_RSVD_1", - C2H_CNT_TH_D_RSVD_1_MASK}, - {"C2H_CNT_TH_D_THESHOLD_CNT", - C2H_CNT_TH_D_THESHOLD_CNT_MASK}, -}; - - -static struct regfield_info - c2h_cnt_th_e_field_info[] = { - {"C2H_CNT_TH_E_RSVD_1", - C2H_CNT_TH_E_RSVD_1_MASK}, - {"C2H_CNT_TH_E_THESHOLD_CNT", - C2H_CNT_TH_E_THESHOLD_CNT_MASK}, -}; - - -static struct regfield_info - c2h_cnt_th_f_field_info[] = { - {"C2H_CNT_TH_F_RSVD_1", - C2H_CNT_TH_F_RSVD_1_MASK}, - {"C2H_CNT_TH_F_THESHOLD_CNT", - C2H_CNT_TH_F_THESHOLD_CNT_MASK}, -}; - - -static struct regfield_info - c2h_cnt_th_10_field_info[] = { - {"C2H_CNT_TH_10_RSVD_1", - C2H_CNT_TH_10_RSVD_1_MASK}, - {"C2H_CNT_TH_10_THESHOLD_CNT", - C2H_CNT_TH_10_THESHOLD_CNT_MASK}, -}; - - -static struct regfield_info - c2h_qid2vec_map_qid_field_info[] = { - {"C2H_QID2VEC_MAP_QID_RSVD_1", - C2H_QID2VEC_MAP_QID_RSVD_1_MASK}, - {"C2H_QID2VEC_MAP_QID_QID", - C2H_QID2VEC_MAP_QID_QID_MASK}, -}; - - -static struct regfield_info - c2h_qid2vec_map_field_info[] = { - {"C2H_QID2VEC_MAP_RSVD_1", - C2H_QID2VEC_MAP_RSVD_1_MASK}, - {"C2H_QID2VEC_MAP_H2C_EN_COAL", - C2H_QID2VEC_MAP_H2C_EN_COAL_MASK}, - {"C2H_QID2VEC_MAP_H2C_VECTOR", - C2H_QID2VEC_MAP_H2C_VECTOR_MASK}, - {"C2H_QID2VEC_MAP_C2H_EN_COAL", - C2H_QID2VEC_MAP_C2H_EN_COAL_MASK}, - {"C2H_QID2VEC_MAP_C2H_VECTOR", - C2H_QID2VEC_MAP_C2H_VECTOR_MASK}, -}; - - -static struct regfield_info - c2h_stat_s_axis_c2h_accepted_field_info[] = { - {"C2H_STAT_S_AXIS_C2H_ACCEPTED", - C2H_STAT_S_AXIS_C2H_ACCEPTED_MASK}, -}; - - -static struct regfield_info - c2h_stat_s_axis_wrb_accepted_field_info[] = { - {"C2H_STAT_S_AXIS_WRB_ACCEPTED", - C2H_STAT_S_AXIS_WRB_ACCEPTED_MASK}, -}; - - -static struct regfield_info - c2h_stat_desc_rsp_pkt_accepted_field_info[] = { - {"C2H_STAT_DESC_RSP_PKT_ACCEPTED_D", - C2H_STAT_DESC_RSP_PKT_ACCEPTED_D_MASK}, -}; - - -static struct regfield_info - c2h_stat_axis_pkg_cmp_field_info[] = { - {"C2H_STAT_AXIS_PKG_CMP", - C2H_STAT_AXIS_PKG_CMP_MASK}, -}; - - -static struct regfield_info - c2h_stat_desc_rsp_accepted_field_info[] = { - {"C2H_STAT_DESC_RSP_ACCEPTED_D", - C2H_STAT_DESC_RSP_ACCEPTED_D_MASK}, -}; - - -static struct regfield_info - c2h_stat_desc_rsp_cmp_field_info[] = { - {"C2H_STAT_DESC_RSP_CMP_D", - C2H_STAT_DESC_RSP_CMP_D_MASK}, -}; - - -static struct regfield_info - c2h_stat_wrq_out_field_info[] = { - {"C2H_STAT_WRQ_OUT", - C2H_STAT_WRQ_OUT_MASK}, -}; - - -static struct regfield_info - c2h_stat_wpl_ren_accepted_field_info[] = { - {"C2H_STAT_WPL_REN_ACCEPTED", - C2H_STAT_WPL_REN_ACCEPTED_MASK}, -}; - - -static struct regfield_info - c2h_stat_total_wrq_len_field_info[] = { - {"C2H_STAT_TOTAL_WRQ_LEN", - C2H_STAT_TOTAL_WRQ_LEN_MASK}, -}; - - -static struct regfield_info - c2h_stat_total_wpl_len_field_info[] = { - {"C2H_STAT_TOTAL_WPL_LEN", - C2H_STAT_TOTAL_WPL_LEN_MASK}, -}; - - -static struct regfield_info - c2h_buf_sz_0_field_info[] = { - {"C2H_BUF_SZ_0_SIZE", - C2H_BUF_SZ_0_SIZE_MASK}, -}; - - -static struct regfield_info - c2h_buf_sz_1_field_info[] = { - {"C2H_BUF_SZ_1_SIZE", - C2H_BUF_SZ_1_SIZE_MASK}, -}; - - -static struct regfield_info - c2h_buf_sz_2_field_info[] = { - {"C2H_BUF_SZ_2_SIZE", - C2H_BUF_SZ_2_SIZE_MASK}, -}; - - -static struct regfield_info - c2h_buf_sz_3_field_info[] = { - {"C2H_BUF_SZ_3_SIZE", - C2H_BUF_SZ_3_SIZE_MASK}, -}; - - -static struct regfield_info - c2h_buf_sz_4_field_info[] = { - {"C2H_BUF_SZ_4_SIZE", - C2H_BUF_SZ_4_SIZE_MASK}, -}; - - -static struct regfield_info - c2h_buf_sz_5_field_info[] = { - {"C2H_BUF_SZ_5_SIZE", - C2H_BUF_SZ_5_SIZE_MASK}, -}; - - -static struct regfield_info - c2h_buf_sz_7_field_info[] = { - {"C2H_BUF_SZ_7_SIZE", - C2H_BUF_SZ_7_SIZE_MASK}, -}; - - -static struct regfield_info - c2h_buf_sz_8_field_info[] = { - {"C2H_BUF_SZ_8_SIZE", - C2H_BUF_SZ_8_SIZE_MASK}, -}; - - -static struct regfield_info - c2h_buf_sz_9_field_info[] = { - {"C2H_BUF_SZ_9_SIZE", - C2H_BUF_SZ_9_SIZE_MASK}, -}; - - -static struct regfield_info - c2h_buf_sz_10_field_info[] = { - {"C2H_BUF_SZ_10_SIZE", - C2H_BUF_SZ_10_SIZE_MASK}, -}; - - -static struct regfield_info - c2h_buf_sz_11_field_info[] = { - {"C2H_BUF_SZ_11_SIZE", - C2H_BUF_SZ_11_SIZE_MASK}, -}; - - -static struct regfield_info - c2h_buf_sz_12_field_info[] = { - {"C2H_BUF_SZ_12_SIZE", - C2H_BUF_SZ_12_SIZE_MASK}, -}; - - -static struct regfield_info - c2h_buf_sz_13_field_info[] = { - {"C2H_BUF_SZ_13_SIZE", - C2H_BUF_SZ_13_SIZE_MASK}, -}; - - -static struct regfield_info - c2h_buf_sz_14_field_info[] = { - {"C2H_BUF_SZ_14_SIZE", - C2H_BUF_SZ_14_SIZE_MASK}, -}; - - -static struct regfield_info - c2h_buf_sz_15_field_info[] = { - {"C2H_BUF_SZ_15_SIZE", - C2H_BUF_SZ_15_SIZE_MASK}, -}; - - -static struct regfield_info - c2h_err_stat_field_info[] = { - {"C2H_ERR_STAT_RSVD_1", - C2H_ERR_STAT_RSVD_1_MASK}, - {"C2H_ERR_STAT_WRB_PRTY_ERR", - C2H_ERR_STAT_WRB_PRTY_ERR_MASK}, - {"C2H_ERR_STAT_WRB_CIDX_ERR", - C2H_ERR_STAT_WRB_CIDX_ERR_MASK}, - {"C2H_ERR_STAT_WRB_QFULL_ERR", - C2H_ERR_STAT_WRB_QFULL_ERR_MASK}, - {"C2H_ERR_STAT_WRB_INV_Q_ERR", - C2H_ERR_STAT_WRB_INV_Q_ERR_MASK}, - {"C2H_ERR_STAT_PORT_ID_BYP_IN_MISMATCH", - C2H_ERR_STAT_PORT_ID_BYP_IN_MISMATCH_MASK}, - {"C2H_ERR_STAT_PORT_ID_CTXT_MISMATCH", - C2H_ERR_STAT_PORT_ID_CTXT_MISMATCH_MASK}, - {"C2H_ERR_STAT_ERR_DESC_CNT", - C2H_ERR_STAT_ERR_DESC_CNT_MASK}, - {"C2H_ERR_STAT_RSVD_2", - C2H_ERR_STAT_RSVD_2_MASK}, - {"C2H_ERR_STAT_MSI_INT_FAIL", - C2H_ERR_STAT_MSI_INT_FAIL_MASK}, - {"C2H_ERR_STAT_ENG_WPL_DATA_PAR_ERR", - C2H_ERR_STAT_ENG_WPL_DATA_PAR_ERR_MASK}, - {"C2H_ERR_STAT_RSVD_3", - C2H_ERR_STAT_RSVD_3_MASK}, - {"C2H_ERR_STAT_DESC_RSP_ERR", - C2H_ERR_STAT_DESC_RSP_ERR_MASK}, - {"C2H_ERR_STAT_QID_MISMATCH", - C2H_ERR_STAT_QID_MISMATCH_MASK}, - {"C2H_ERR_STAT_RSVD_4", - C2H_ERR_STAT_RSVD_4_MASK}, - {"C2H_ERR_STAT_LEN_MISMATCH", - C2H_ERR_STAT_LEN_MISMATCH_MASK}, - {"C2H_ERR_STAT_MTY_MISMATCH", - C2H_ERR_STAT_MTY_MISMATCH_MASK}, -}; - - -static struct regfield_info - c2h_err_mask_field_info[] = { - {"C2H_ERR_EN", - C2H_ERR_EN_MASK}, -}; - - -static struct regfield_info - c2h_fatal_err_stat_field_info[] = { - {"C2H_FATAL_ERR_STAT_RSVD_1", - C2H_FATAL_ERR_STAT_RSVD_1_MASK}, - {"C2H_FATAL_ERR_STAT_WPL_DATA_PAR_ERR", - C2H_FATAL_ERR_STAT_WPL_DATA_PAR_ERR_MASK}, - {"C2H_FATAL_ERR_STAT_PLD_FIFO_RAM_RDBE", - C2H_FATAL_ERR_STAT_PLD_FIFO_RAM_RDBE_MASK}, - {"C2H_FATAL_ERR_STAT_QID_FIFO_RAM_RDBE", - C2H_FATAL_ERR_STAT_QID_FIFO_RAM_RDBE_MASK}, - {"C2H_FATAL_ERR_STAT_TUSER_FIFO_RAM_RDBE", - C2H_FATAL_ERR_STAT_TUSER_FIFO_RAM_RDBE_MASK}, - {"C2H_FATAL_ERR_STAT_WRB_COAL_DATA_RAM_RDBE", - C2H_FATAL_ERR_STAT_WRB_COAL_DATA_RAM_RDBE_MASK}, - {"C2H_FATAL_ERR_STAT_INT_QID2VEC_RAM_RDBE", - C2H_FATAL_ERR_STAT_INT_QID2VEC_RAM_RDBE_MASK}, - {"C2H_FATAL_ERR_STAT_INT_CTXT_RAM_RDBE", - C2H_FATAL_ERR_STAT_INT_CTXT_RAM_RDBE_MASK}, - {"C2H_FATAL_ERR_STAT_DESC_REQ_FIFO_RAM_RDBE", - C2H_FATAL_ERR_STAT_DESC_REQ_FIFO_RAM_RDBE_MASK}, - {"C2H_FATAL_ERR_STAT_PFCH_CTXT_RAM_RDBE", - C2H_FATAL_ERR_STAT_PFCH_CTXT_RAM_RDBE_MASK}, - {"C2H_FATAL_ERR_STAT_WRB_CTXT_RAM_RDBE", - C2H_FATAL_ERR_STAT_WRB_CTXT_RAM_RDBE_MASK}, - {"C2H_FATAL_ERR_STAT_PFCH_LL_RAM_RDBE", - C2H_FATAL_ERR_STAT_PFCH_LL_RAM_RDBE_MASK}, - {"C2H_FATAL_ERR_STAT_TIMER_FIFO_RAM_RDBE", - C2H_FATAL_ERR_STAT_TIMER_FIFO_RAM_RDBE_MASK}, - {"C2H_FATAL_ERR_STAT_QID_MISMATCH", - C2H_FATAL_ERR_STAT_QID_MISMATCH_MASK}, - {"C2H_FATAL_ERR_STAT_RSVD_2", - C2H_FATAL_ERR_STAT_RSVD_2_MASK}, - {"C2H_FATAL_ERR_STAT_LEN_MISMATCH", - C2H_FATAL_ERR_STAT_LEN_MISMATCH_MASK}, - {"C2H_FATAL_ERR_STAT_MTY_MISMATCH", - C2H_FATAL_ERR_STAT_MTY_MISMATCH_MASK}, -}; - - -static struct regfield_info - c2h_fatal_err_mask_field_info[] = { - {"C2H_FATAL_ERR_C2HEN", - C2H_FATAL_ERR_C2HEN_MASK}, -}; - - -static struct regfield_info - c2h_fatal_err_enable_field_info[] = { - {"C2H_FATAL_ERR_ENABLE_RSVD_1", - C2H_FATAL_ERR_ENABLE_RSVD_1_MASK}, - {"C2H_FATAL_ERR_ENABLE_WPL_PAR_INV", - C2H_FATAL_ERR_ENABLE_WPL_PAR_INV_MASK}, - {"C2H_FATAL_ERR_ENABLE_WRQ_DIS", - C2H_FATAL_ERR_ENABLE_WRQ_DIS_MASK}, -}; - - -static struct regfield_info - glbl_err_int_field_info[] = { - {"GLBL_ERR_INT_RSVD_1", - GLBL_ERR_INT_RSVD_1_MASK}, - {"GLBL_ERR_INT_ARM", - GLBL_ERR_INT_ARM_MASK}, - {"GLBL_ERR_INT_EN_COAL", - GLBL_ERR_INT_EN_COAL_MASK}, - {"GLBL_ERR_INT_VEC", - GLBL_ERR_INT_VEC_MASK}, - {"GLBL_ERR_INT_FUNC", - GLBL_ERR_INT_FUNC_MASK}, -}; - - -static struct regfield_info - c2h_pfch_cfg_field_info[] = { - {"C2H_PFCH_CFG_EVT_QCNT_TH", - C2H_PFCH_CFG_EVT_QCNT_TH_MASK}, - {"C2H_PFCH_CFG_QCNT", - C2H_PFCH_CFG_QCNT_MASK}, - {"C2H_PFCH_CFG_NUM", - C2H_PFCH_CFG_NUM_MASK}, - {"C2H_PFCH_CFG_FL_TH", - C2H_PFCH_CFG_FL_TH_MASK}, -}; - - -static struct regfield_info - c2h_int_timer_tick_field_info[] = { - {"C2H_INT_TIMER_TICK", - C2H_INT_TIMER_TICK_MASK}, -}; - - -static struct regfield_info - c2h_stat_desc_rsp_drop_accepted_field_info[] = { - {"C2H_STAT_DESC_RSP_DROP_ACCEPTED_D", - C2H_STAT_DESC_RSP_DROP_ACCEPTED_D_MASK}, -}; - - -static struct regfield_info - c2h_stat_desc_rsp_err_accepted_field_info[] = { - {"C2H_STAT_DESC_RSP_ERR_ACCEPTED_D", - C2H_STAT_DESC_RSP_ERR_ACCEPTED_D_MASK}, -}; - - -static struct regfield_info - c2h_stat_desc_req_field_info[] = { - {"C2H_STAT_DESC_REQ", - C2H_STAT_DESC_REQ_MASK}, -}; - - -static struct regfield_info - c2h_stat_dbg_dma_eng_0_field_info[] = { - {"C2H_STAT_DMA_ENG_0_RSVD_1", - C2H_STAT_DMA_ENG_0_RSVD_1_MASK}, - {"C2H_STAT_DMA_ENG_0_WRB_FIFO_OUT_CNT", - C2H_STAT_DMA_ENG_0_WRB_FIFO_OUT_CNT_MASK}, - {"C2H_STAT_DMA_ENG_0_QID_FIFO_OUT_CNT", - C2H_STAT_DMA_ENG_0_QID_FIFO_OUT_CNT_MASK}, - {"C2H_STAT_DMA_ENG_0_PLD_FIFO_OUT_CNT", - C2H_STAT_DMA_ENG_0_PLD_FIFO_OUT_CNT_MASK}, - {"C2H_STAT_DMA_ENG_0_WRQ_FIFO_OUT_CNT", - C2H_STAT_DMA_ENG_0_WRQ_FIFO_OUT_CNT_MASK}, - {"C2H_STAT_DMA_ENG_0_WRB_SM_CS", - C2H_STAT_DMA_ENG_0_WRB_SM_CS_MASK}, - {"C2H_STAT_DMA_ENG_0_MAIN_SM_CS", - C2H_STAT_DMA_ENG_0_MAIN_SM_CS_MASK}, -}; - - -static struct regfield_info - c2h_stat_dbg_dma_eng_1_field_info[] = { - {"C2H_STAT_DMA_ENG_1_RSVD_1", - C2H_STAT_DMA_ENG_1_RSVD_1_MASK}, - {"C2H_STAT_DMA_ENG_1_DESC_RSP_LAST", - C2H_STAT_DMA_ENG_1_DESC_RSP_LAST_MASK}, - {"C2H_STAT_DMA_ENG_1_PLD_FIFO_IN_CNT", - C2H_STAT_DMA_ENG_1_PLD_FIFO_IN_CNT_MASK}, - {"C2H_STAT_DMA_ENG_1_PLD_FIFO_OUTPUT_CNT", - C2H_STAT_DMA_ENG_1_PLD_FIFO_OUTPUT_CNT_MASK}, - {"C2H_STAT_DMA_ENG_1_QID_FIFO_IN_CNT", - C2H_STAT_DMA_ENG_1_QID_FIFO_IN_CNT_MASK}, -}; - - -static struct regfield_info - c2h_stat_dbg_dma_eng_2_field_info[] = { - {"C2H_STAT_DMA_ENG_2_RSVD_1", - C2H_STAT_DMA_ENG_2_RSVD_1_MASK}, - {"C2H_STAT_DMA_ENG_2_WRB_FIFO_IN_CNT", - C2H_STAT_DMA_ENG_2_WRB_FIFO_IN_CNT_MASK}, - {"C2H_STAT_DMA_ENG_2_WRB_FIFO_OUTPUT_CNT", - C2H_STAT_DMA_ENG_2_WRB_FIFO_OUTPUT_CNT_MASK}, - {"C2H_STAT_DMA_ENG_2_QID_FIFO_OUTPUT_CNT", - C2H_STAT_DMA_ENG_2_QID_FIFO_OUTPUT_CNT_MASK}, -}; - - -static struct regfield_info - c2h_stat_dbg_dma_eng_3_field_info[] = { - {"C2H_STAT_DMA_ENG_3_RSVD_1", - C2H_STAT_DMA_ENG_3_RSVD_1_MASK}, - {"C2H_STAT_DMA_ENG_3_ADDR_4K_SPLIT_CNT", - C2H_STAT_DMA_ENG_3_ADDR_4K_SPLIT_CNT_MASK}, - {"C2H_STAT_DMA_ENG_3_WRQ_FIFO_IN_CNT", - C2H_STAT_DMA_ENG_3_WRQ_FIFO_IN_CNT_MASK}, - {"C2H_STAT_DMA_ENG_3_WRQ_FIFO_OUTPUT_CNT", - C2H_STAT_DMA_ENG_3_WRQ_FIFO_OUTPUT_CNT_MASK}, -}; - - -static struct regfield_info - c2h_dbg_pfch_err_ctxt_field_info[] = { - {"C2H_PFCH_ERR_CTXT_RSVD_1", - C2H_PFCH_ERR_CTXT_RSVD_1_MASK}, - {"C2H_PFCH_ERR_CTXT_ERR_STAT", - C2H_PFCH_ERR_CTXT_ERR_STAT_MASK}, - {"C2H_PFCH_ERR_CTXT_CMD_WR", - C2H_PFCH_ERR_CTXT_CMD_WR_MASK}, - {"C2H_PFCH_ERR_CTXT_QID", - C2H_PFCH_ERR_CTXT_QID_MASK}, - {"C2H_PFCH_ERR_CTXT_DONE", - C2H_PFCH_ERR_CTXT_DONE_MASK}, -}; - - -static struct regfield_info - c2h_first_err_qid_field_info[] = { - {"C2H_FIRST_ERR_QID_RSVD_1", - C2H_FIRST_ERR_QID_RSVD_1_MASK}, - {"C2H_FIRST_ERR_QID_ERR_STAT", - C2H_FIRST_ERR_QID_ERR_STAT_MASK}, - {"C2H_FIRST_ERR_QID_CMD_WR", - C2H_FIRST_ERR_QID_CMD_WR_MASK}, - {"C2H_FIRST_ERR_QID_QID", - C2H_FIRST_ERR_QID_QID_MASK}, -}; - - -static struct regfield_info - stat_num_wrb_in_field_info[] = { - {"STAT_NUM_WRB_IN_RSVD_1", - STAT_NUM_WRB_IN_RSVD_1_MASK}, - {"STAT_NUM_WRB_IN_WRB_CNT", - STAT_NUM_WRB_IN_WRB_CNT_MASK}, -}; - - -static struct regfield_info - stat_num_wrb_out_field_info[] = { - {"STAT_NUM_WRB_OUT_RSVD_1", - STAT_NUM_WRB_OUT_RSVD_1_MASK}, - {"STAT_NUM_WRB_OUT_WRB_CNT", - STAT_NUM_WRB_OUT_WRB_CNT_MASK}, -}; - - -static struct regfield_info - stat_num_wrb_drp_field_info[] = { - {"STAT_NUM_WRB_DRP_RSVD_1", - STAT_NUM_WRB_DRP_RSVD_1_MASK}, - {"STAT_NUM_WRB_DRP_WRB_CNT", - STAT_NUM_WRB_DRP_WRB_CNT_MASK}, -}; - - -static struct regfield_info - stat_num_stat_desc_out_field_info[] = { - {"STAT_NUM_STAT_DESC_OUT_RSVD_1", - STAT_NUM_STAT_DESC_OUT_RSVD_1_MASK}, - {"STAT_NUM_STAT_DESC_OUT_CNT", - STAT_NUM_STAT_DESC_OUT_CNT_MASK}, -}; - - -static struct regfield_info - stat_num_dsc_crdt_sent_field_info[] = { - {"STAT_NUM_DSC_CRDT_SENT_RSVD_1", - STAT_NUM_DSC_CRDT_SENT_RSVD_1_MASK}, - {"STAT_NUM_DSC_CRDT_SENT_CNT", - STAT_NUM_DSC_CRDT_SENT_CNT_MASK}, -}; - - -static struct regfield_info - stat_num_fch_dsc_rcvd_field_info[] = { - {"STAT_NUM_FCH_DSC_RCVD_RSVD_1", - STAT_NUM_FCH_DSC_RCVD_RSVD_1_MASK}, - {"STAT_NUM_FCH_DSC_RCVD_DSC_CNT", - STAT_NUM_FCH_DSC_RCVD_DSC_CNT_MASK}, -}; - - -static struct regfield_info - stat_num_byp_dsc_rcvd_field_info[] = { - {"STAT_NUM_BYP_DSC_RCVD_RSVD_1", - STAT_NUM_BYP_DSC_RCVD_RSVD_1_MASK}, - {"STAT_NUM_BYP_DSC_RCVD_DSC_CNT", - STAT_NUM_BYP_DSC_RCVD_DSC_CNT_MASK}, -}; - - -static struct regfield_info - c2h_wrb_coal_cfg_field_info[] = { - {"C2H_WRB_COAL_CFG_MAX_BUF_SZ", - C2H_WRB_COAL_CFG_MAX_BUF_SZ_MASK}, - {"C2H_WRB_COAL_CFG_TICK_VAL", - C2H_WRB_COAL_CFG_TICK_VAL_MASK}, - {"C2H_WRB_COAL_CFG_TICK_CNT", - C2H_WRB_COAL_CFG_TICK_CNT_MASK}, - {"C2H_WRB_COAL_CFG_SET_GLB_FLUSH", - C2H_WRB_COAL_CFG_SET_GLB_FLUSH_MASK}, - {"C2H_WRB_COAL_CFG_DONE_GLB_FLUSH", - C2H_WRB_COAL_CFG_DONE_GLB_FLUSH_MASK}, -}; - - -static struct regfield_info - c2h_intr_h2c_req_field_info[] = { - {"C2H_INTR_H2C_REQ_RSVD_1", - C2H_INTR_H2C_REQ_RSVD_1_MASK}, - {"C2H_INTR_H2C_REQ_CNT", - C2H_INTR_H2C_REQ_CNT_MASK}, -}; - - -static struct regfield_info - c2h_intr_c2h_mm_req_field_info[] = { - {"C2H_INTR_C2H_MM_REQ_RSVD_1", - C2H_INTR_C2H_MM_REQ_RSVD_1_MASK}, - {"C2H_INTR_C2H_MM_REQ_CNT", - C2H_INTR_C2H_MM_REQ_CNT_MASK}, -}; - - -static struct regfield_info - c2h_intr_err_int_req_field_info[] = { - {"C2H_INTR_ERR_INT_REQ_RSVD_1", - C2H_INTR_ERR_INT_REQ_RSVD_1_MASK}, - {"C2H_INTR_ERR_INT_REQ_CNT", - C2H_INTR_ERR_INT_REQ_CNT_MASK}, -}; - - -static struct regfield_info - c2h_intr_c2h_st_req_field_info[] = { - {"C2H_INTR_C2H_ST_REQ_RSVD_1", - C2H_INTR_C2H_ST_REQ_RSVD_1_MASK}, - {"C2H_INTR_C2H_ST_REQ_CNT", - C2H_INTR_C2H_ST_REQ_CNT_MASK}, -}; - - -static struct regfield_info - c2h_intr_h2c_err_c2h_mm_msix_ack_field_info[] = { - {"C2H_INTR_H2C_ERR_C2H_MM_MSIX_ACK_RSVD_1", - C2H_INTR_H2C_ERR_C2H_MM_MSIX_ACK_RSVD_1_MASK}, - {"C2H_INTR_H2C_ERR_C2H_MM_MSIX_ACK_CNT", - C2H_INTR_H2C_ERR_C2H_MM_MSIX_ACK_CNT_MASK}, -}; - - -static struct regfield_info - c2h_intr_h2c_err_c2h_mm_msix_fail_field_info[] = { - {"C2H_INTR_H2C_ERR_C2H_MM_MSIX_FAIL_RSVD_1", - C2H_INTR_H2C_ERR_C2H_MM_MSIX_FAIL_RSVD_1_MASK}, - {"C2H_INTR_H2C_ERR_C2H_MM_MSIX_FAIL_CNT", - C2H_INTR_H2C_ERR_C2H_MM_MSIX_FAIL_CNT_MASK}, -}; - - -static struct regfield_info - c2h_intr_h2c_err_c2h_mm_msix_no_msix_field_info[] = { - {"C2H_INTR_H2C_ERR_C2H_MM_MSIX_NO_MSIX_RSVD_1", - C2H_INTR_H2C_ERR_C2H_MM_MSIX_NO_MSIX_RSVD_1_MASK}, - {"C2H_INTR_H2C_ERR_C2H_MM_MSIX_NO_MSIX_CNT", - C2H_INTR_H2C_ERR_C2H_MM_MSIX_NO_MSIX_CNT_MASK}, -}; - - -static struct regfield_info - c2h_intr_h2c_err_c2h_mm_ctxt_inval_field_info[] = { - {"C2H_INTR_H2C_ERR_C2H_MM_CTXT_INVAL_RSVD_1", - C2H_INTR_H2C_ERR_C2H_MM_CTXT_INVAL_RSVD_1_MASK}, - {"C2H_INTR_H2C_ERR_C2H_MM_CTXT_INVAL_CNT", - C2H_INTR_H2C_ERR_C2H_MM_CTXT_INVAL_CNT_MASK}, -}; - - -static struct regfield_info - c2h_intr_c2h_st_msix_ack_field_info[] = { - {"C2H_INTR_C2H_ST_MSIX_ACK_RSVD_1", - C2H_INTR_C2H_ST_MSIX_ACK_RSVD_1_MASK}, - {"C2H_INTR_C2H_ST_MSIX_ACK_CNT", - C2H_INTR_C2H_ST_MSIX_ACK_CNT_MASK}, -}; - - -static struct regfield_info - c2h_intr_c2h_st_msix_fail_field_info[] = { - {"C2H_INTR_C2H_ST_MSIX_FAIL_RSVD_1", - C2H_INTR_C2H_ST_MSIX_FAIL_RSVD_1_MASK}, - {"C2H_INTR_C2H_ST_MSIX_FAIL_CNT", - C2H_INTR_C2H_ST_MSIX_FAIL_CNT_MASK}, -}; - - -static struct regfield_info - c2h_intr_c2h_st_no_msix_field_info[] = { - {"C2H_INTR_C2H_ST_NO_MSIX_RSVD_1", - C2H_INTR_C2H_ST_NO_MSIX_RSVD_1_MASK}, - {"C2H_INTR_C2H_ST_NO_MSIX_CNT", - C2H_INTR_C2H_ST_NO_MSIX_CNT_MASK}, -}; - - -static struct regfield_info - c2h_intr_c2h_st_ctxt_inval_field_info[] = { - {"C2H_INTR_C2H_ST_CTXT_INVAL_RSVD_1", - C2H_INTR_C2H_ST_CTXT_INVAL_RSVD_1_MASK}, - {"C2H_INTR_C2H_ST_CTXT_INVAL_CNT", - C2H_INTR_C2H_ST_CTXT_INVAL_CNT_MASK}, -}; - - -static struct regfield_info - c2h_stat_wr_cmp_field_info[] = { - {"C2H_STAT_WR_CMP_RSVD_1", - C2H_STAT_WR_CMP_RSVD_1_MASK}, - {"C2H_STAT_WR_CMP_CNT", - C2H_STAT_WR_CMP_CNT_MASK}, -}; - - -static struct regfield_info - c2h_stat_dbg_dma_eng_4_field_info[] = { - {"C2H_STAT_DMA_ENG_4_TUSER_FIFO_OUT_VLD", - C2H_STAT_DMA_ENG_4_TUSER_FIFO_OUT_VLD_MASK}, - {"C2H_STAT_DMA_ENG_4_WRB_FIFO_IN_RDY", - C2H_STAT_DMA_ENG_4_WRB_FIFO_IN_RDY_MASK}, - {"C2H_STAT_DMA_ENG_4_TUSER_FIFO_IN_CNT", - C2H_STAT_DMA_ENG_4_TUSER_FIFO_IN_CNT_MASK}, - {"C2H_STAT_DMA_ENG_4_TUSER_FIFO_OUTPUT_CNT", - C2H_STAT_DMA_ENG_4_TUSER_FIFO_OUTPUT_CNT_MASK}, - {"C2H_STAT_DMA_ENG_4_TUSER_FIFO_OUT_CNT", - C2H_STAT_DMA_ENG_4_TUSER_FIFO_OUT_CNT_MASK}, -}; - - -static struct regfield_info - c2h_stat_dbg_dma_eng_5_field_info[] = { - {"C2H_STAT_DMA_ENG_5_RSVD_1", - C2H_STAT_DMA_ENG_5_RSVD_1_MASK}, - {"C2H_STAT_DMA_ENG_5_TUSER_COMB_OUT_VLD", - C2H_STAT_DMA_ENG_5_TUSER_COMB_OUT_VLD_MASK}, - {"C2H_STAT_DMA_ENG_5_TUSER_FIFO_IN_RDY", - C2H_STAT_DMA_ENG_5_TUSER_FIFO_IN_RDY_MASK}, - {"C2H_STAT_DMA_ENG_5_TUSER_COMB_IN_CNT", - C2H_STAT_DMA_ENG_5_TUSER_COMB_IN_CNT_MASK}, - {"C2H_STAT_DMA_ENG_5_TUSE_COMB_OUTPUT_CNT", - C2H_STAT_DMA_ENG_5_TUSE_COMB_OUTPUT_CNT_MASK}, - {"C2H_STAT_DMA_ENG_5_TUSER_COMB_CNT", - C2H_STAT_DMA_ENG_5_TUSER_COMB_CNT_MASK}, -}; - - -static struct regfield_info - c2h_dbg_pfch_qid_field_info[] = { - {"C2H_PFCH_QID_RSVD_1", - C2H_PFCH_QID_RSVD_1_MASK}, - {"C2H_PFCH_QID_ERR_CTXT", - C2H_PFCH_QID_ERR_CTXT_MASK}, - {"C2H_PFCH_QID_TARGET", - C2H_PFCH_QID_TARGET_MASK}, - {"C2H_PFCH_QID_QID_OR_TAG", - C2H_PFCH_QID_QID_OR_TAG_MASK}, -}; - - -static struct regfield_info - c2h_dbg_pfch_field_info[] = { - {"C2H_PFCH_DATA", - C2H_PFCH_DATA_MASK}, -}; - - -static struct regfield_info - c2h_int_dbg_field_info[] = { - {"C2H_INT_RSVD_1", - C2H_INT_RSVD_1_MASK}, - {"C2H_INT_INT_COAL_SM", - C2H_INT_INT_COAL_SM_MASK}, - {"C2H_INT_INT_SM", - C2H_INT_INT_SM_MASK}, -}; - - -static struct regfield_info - c2h_stat_imm_accepted_field_info[] = { - {"C2H_STAT_IMM_ACCEPTED_RSVD_1", - C2H_STAT_IMM_ACCEPTED_RSVD_1_MASK}, - {"C2H_STAT_IMM_ACCEPTED_CNT", - C2H_STAT_IMM_ACCEPTED_CNT_MASK}, -}; - - -static struct regfield_info - c2h_stat_marker_accepted_field_info[] = { - {"C2H_STAT_MARKER_ACCEPTED_RSVD_1", - C2H_STAT_MARKER_ACCEPTED_RSVD_1_MASK}, - {"C2H_STAT_MARKER_ACCEPTED_CNT", - C2H_STAT_MARKER_ACCEPTED_CNT_MASK}, -}; - - -static struct regfield_info - c2h_stat_disable_cmp_accepted_field_info[] = { - {"C2H_STAT_DISABLE_CMP_ACCEPTED_RSVD_1", - C2H_STAT_DISABLE_CMP_ACCEPTED_RSVD_1_MASK}, - {"C2H_STAT_DISABLE_CMP_ACCEPTED_CNT", - C2H_STAT_DISABLE_CMP_ACCEPTED_CNT_MASK}, -}; - - -static struct regfield_info - c2h_pld_fifo_crdt_cnt_field_info[] = { - {"C2H_PLD_FIFO_CRDT_CNT_RSVD_1", - C2H_PLD_FIFO_CRDT_CNT_RSVD_1_MASK}, - {"C2H_PLD_FIFO_CRDT_CNT_CNT", - C2H_PLD_FIFO_CRDT_CNT_CNT_MASK}, -}; - - -static struct regfield_info - h2c_err_stat_field_info[] = { - {"H2C_ERR_STAT_RSVD_1", - H2C_ERR_STAT_RSVD_1_MASK}, - {"H2C_ERR_STAT_SBE", - H2C_ERR_STAT_SBE_MASK}, - {"H2C_ERR_STAT_DBE", - H2C_ERR_STAT_DBE_MASK}, - {"H2C_ERR_STAT_NO_DMA_DS", - H2C_ERR_STAT_NO_DMA_DS_MASK}, - {"H2C_ERR_STAT_SDI_MRKR_REQ_MOP_ERR", - H2C_ERR_STAT_SDI_MRKR_REQ_MOP_ERR_MASK}, - {"H2C_ERR_STAT_ZERO_LEN_DS", - H2C_ERR_STAT_ZERO_LEN_DS_MASK}, -}; - - -static struct regfield_info - h2c_err_mask_field_info[] = { - {"H2C_ERR_EN", - H2C_ERR_EN_MASK}, -}; - - -static struct regfield_info - h2c_first_err_qid_field_info[] = { - {"H2C_FIRST_ERR_QID_RSVD_1", - H2C_FIRST_ERR_QID_RSVD_1_MASK}, - {"H2C_FIRST_ERR_QID_ERR_TYPE", - H2C_FIRST_ERR_QID_ERR_TYPE_MASK}, - {"H2C_FIRST_ERR_QID_RSVD_2", - H2C_FIRST_ERR_QID_RSVD_2_MASK}, - {"H2C_FIRST_ERR_QID_QID", - H2C_FIRST_ERR_QID_QID_MASK}, -}; - - -static struct regfield_info - h2c_dbg_reg0_field_info[] = { - {"H2C_REG0_NUM_DSC_RCVD", - H2C_REG0_NUM_DSC_RCVD_MASK}, - {"H2C_REG0_NUM_WRB_SENT", - H2C_REG0_NUM_WRB_SENT_MASK}, -}; - - -static struct regfield_info - h2c_dbg_reg1_field_info[] = { - {"H2C_REG1_NUM_REQ_SENT", - H2C_REG1_NUM_REQ_SENT_MASK}, - {"H2C_REG1_NUM_CMP_SENT", - H2C_REG1_NUM_CMP_SENT_MASK}, -}; - - -static struct regfield_info - h2c_dbg_reg2_field_info[] = { - {"H2C_REG2_RSVD_1", - H2C_REG2_RSVD_1_MASK}, - {"H2C_REG2_NUM_ERR_DSC_RCVD", - H2C_REG2_NUM_ERR_DSC_RCVD_MASK}, -}; - - -static struct regfield_info - h2c_dbg_reg3_field_info[] = { - {"H2C_REG3", - H2C_REG3_MASK}, - {"H2C_REG3_DSCO_FIFO_EMPTY", - H2C_REG3_DSCO_FIFO_EMPTY_MASK}, - {"H2C_REG3_DSCO_FIFO_FULL", - H2C_REG3_DSCO_FIFO_FULL_MASK}, - {"H2C_REG3_CUR_RC_STATE", - H2C_REG3_CUR_RC_STATE_MASK}, - {"H2C_REG3_RDREQ_LINES", - H2C_REG3_RDREQ_LINES_MASK}, - {"H2C_REG3_RDATA_LINES_AVAIL", - H2C_REG3_RDATA_LINES_AVAIL_MASK}, - {"H2C_REG3_PEND_FIFO_EMPTY", - H2C_REG3_PEND_FIFO_EMPTY_MASK}, - {"H2C_REG3_PEND_FIFO_FULL", - H2C_REG3_PEND_FIFO_FULL_MASK}, - {"H2C_REG3_CUR_RQ_STATE", - H2C_REG3_CUR_RQ_STATE_MASK}, - {"H2C_REG3_DSCI_FIFO_FULL", - H2C_REG3_DSCI_FIFO_FULL_MASK}, - {"H2C_REG3_DSCI_FIFO_EMPTY", - H2C_REG3_DSCI_FIFO_EMPTY_MASK}, -}; - - -static struct regfield_info - h2c_dbg_reg4_field_info[] = { - {"H2C_REG4_RDREQ_ADDR", - H2C_REG4_RDREQ_ADDR_MASK}, -}; - - -static struct regfield_info - h2c_fatal_err_en_field_info[] = { - {"H2C_FATAL_ERR_EN_RSVD_1", - H2C_FATAL_ERR_EN_RSVD_1_MASK}, - {"H2C_FATAL_ERR_EN_H2C", - H2C_FATAL_ERR_EN_H2C_MASK}, -}; - - -static struct regfield_info - c2h_channel_ctl_field_info[] = { - {"C2H_CHANNEL_CTL_RSVD_1", - C2H_CHANNEL_CTL_RSVD_1_MASK}, - {"C2H_CHANNEL_CTL_RUN", - C2H_CHANNEL_CTL_RUN_MASK}, -}; - - -static struct regfield_info - c2h_channel_ctl_1_field_info[] = { - {"C2H_CHANNEL_CTL_1_RUN", - C2H_CHANNEL_CTL_1_RUN_MASK}, - {"C2H_CHANNEL_CTL_1_RUN_1", - C2H_CHANNEL_CTL_1_RUN_1_MASK}, -}; - - -static struct regfield_info - c2h_mm_status_field_info[] = { - {"C2H_MM_STATUS_RSVD_1", - C2H_MM_STATUS_RSVD_1_MASK}, - {"C2H_MM_STATUS_RUN", - C2H_MM_STATUS_RUN_MASK}, -}; - - -static struct regfield_info - c2h_channel_cmpl_desc_cnt_field_info[] = { - {"C2H_CHANNEL_CMPL_DESC_CNT_C2H_CO", - C2H_CHANNEL_CMPL_DESC_CNT_C2H_CO_MASK}, -}; - - -static struct regfield_info - c2h_mm_err_code_enable_mask_field_info[] = { - {"C2H_MM_ERR_CODE_ENABLE_RSVD_1", - C2H_MM_ERR_CODE_ENABLE_RSVD_1_MASK}, - {"C2H_MM_ERR_CODE_ENABLE_WR_UC_RAM", - C2H_MM_ERR_CODE_ENABLE_WR_UC_RAM_MASK}, - {"C2H_MM_ERR_CODE_ENABLE_WR_UR", - C2H_MM_ERR_CODE_ENABLE_WR_UR_MASK}, - {"C2H_MM_ERR_CODE_ENABLE_WR_FLR", - C2H_MM_ERR_CODE_ENABLE_WR_FLR_MASK}, - {"C2H_MM_ERR_CODE_ENABLE_RSVD_2", - C2H_MM_ERR_CODE_ENABLE_RSVD_2_MASK}, - {"C2H_MM_ERR_CODE_ENABLE_RD_SLV_ERR", - C2H_MM_ERR_CODE_ENABLE_RD_SLV_ERR_MASK}, - {"C2H_MM_ERR_CODE_ENABLE_WR_SLV_ERR", - C2H_MM_ERR_CODE_ENABLE_WR_SLV_ERR_MASK}, -}; - - -static struct regfield_info - c2h_mm_err_code_field_info[] = { - {"C2H_MM_ERR_CODE_RSVD_1", - C2H_MM_ERR_CODE_RSVD_1_MASK}, - {"C2H_MM_ERR_CODE_VALID", - C2H_MM_ERR_CODE_VALID_MASK}, - {"C2H_MM_ERR_CODE_RDWR", - C2H_MM_ERR_CODE_RDWR_MASK}, - {"C2H_MM_ERR_CODE", - C2H_MM_ERR_CODE_MASK}, -}; - - -static struct regfield_info - c2h_mm_err_info_field_info[] = { - {"C2H_MM_ERR_INFO_RSVD_1", - C2H_MM_ERR_INFO_RSVD_1_MASK}, - {"C2H_MM_ERR_INFO_QID", - C2H_MM_ERR_INFO_QID_MASK}, - {"C2H_MM_ERR_INFO_DIR", - C2H_MM_ERR_INFO_DIR_MASK}, - {"C2H_MM_ERR_INFO_CIDX", - C2H_MM_ERR_INFO_CIDX_MASK}, -}; - - -static struct regfield_info - c2h_mm_perf_mon_ctl_field_info[] = { - {"C2H_MM_PERF_MON_CTL_RSVD_1", - C2H_MM_PERF_MON_CTL_RSVD_1_MASK}, - {"C2H_MM_PERF_MON_CTL_IMM_START", - C2H_MM_PERF_MON_CTL_IMM_START_MASK}, - {"C2H_MM_PERF_MON_CTL_RUN_START", - C2H_MM_PERF_MON_CTL_RUN_START_MASK}, - {"C2H_MM_PERF_MON_CTL_IMM_CLEAR", - C2H_MM_PERF_MON_CTL_IMM_CLEAR_MASK}, - {"C2H_MM_PERF_MON_CTL_RUN_CLEAR", - C2H_MM_PERF_MON_CTL_RUN_CLEAR_MASK}, -}; - - -static struct regfield_info - c2h_mm_perf_mon_cycle_cnt0_field_info[] = { - {"C2H_MM_PERF_MON_CYCLE_CNT0_CYC_CNT", - C2H_MM_PERF_MON_CYCLE_CNT0_CYC_CNT_MASK}, -}; - - -static struct regfield_info - c2h_mm_perf_mon_cycle_cnt1_field_info[] = { - {"C2H_MM_PERF_MON_CYCLE_CNT1_RSVD_1", - C2H_MM_PERF_MON_CYCLE_CNT1_RSVD_1_MASK}, - {"C2H_MM_PERF_MON_CYCLE_CNT1_CYC_CNT", - C2H_MM_PERF_MON_CYCLE_CNT1_CYC_CNT_MASK}, -}; - - -static struct regfield_info - c2h_mm_perf_mon_data_cnt0_field_info[] = { - {"C2H_MM_PERF_MON_DATA_CNT0_DCNT", - C2H_MM_PERF_MON_DATA_CNT0_DCNT_MASK}, -}; - - -static struct regfield_info - c2h_mm_perf_mon_data_cnt1_field_info[] = { - {"C2H_MM_PERF_MON_DATA_CNT1_RSVD_1", - C2H_MM_PERF_MON_DATA_CNT1_RSVD_1_MASK}, - {"C2H_MM_PERF_MON_DATA_CNT1_DCNT", - C2H_MM_PERF_MON_DATA_CNT1_DCNT_MASK}, -}; - - -static struct regfield_info - c2h_mm_dbg_field_info[] = { - {"C2H_MM_RSVD_1", - C2H_MM_RSVD_1_MASK}, - {"C2H_MM_RRQ_ENTRIES", - C2H_MM_RRQ_ENTRIES_MASK}, - {"C2H_MM_DAT_FIFO_SPC", - C2H_MM_DAT_FIFO_SPC_MASK}, - {"C2H_MM_RD_STALL", - C2H_MM_RD_STALL_MASK}, - {"C2H_MM_RRQ_FIFO_FI", - C2H_MM_RRQ_FIFO_FI_MASK}, - {"C2H_MM_WR_STALL", - C2H_MM_WR_STALL_MASK}, - {"C2H_MM_WRQ_FIFO_FI", - C2H_MM_WRQ_FIFO_FI_MASK}, - {"C2H_MM_WBK_STALL", - C2H_MM_WBK_STALL_MASK}, - {"C2H_MM_DSC_FIFO_EP", - C2H_MM_DSC_FIFO_EP_MASK}, - {"C2H_MM_DSC_FIFO_FL", - C2H_MM_DSC_FIFO_FL_MASK}, -}; - - -static struct regfield_info - h2c_channel_ctl_field_info[] = { - {"H2C_CHANNEL_CTL_RSVD_1", - H2C_CHANNEL_CTL_RSVD_1_MASK}, - {"H2C_CHANNEL_CTL_RUN", - H2C_CHANNEL_CTL_RUN_MASK}, -}; - - -static struct regfield_info - h2c_channel_ctl_1_field_info[] = { - {"H2C_CHANNEL_CTL_1_RUN", - H2C_CHANNEL_CTL_1_RUN_MASK}, -}; - - -static struct regfield_info - h2c_channel_ctl_2_field_info[] = { - {"H2C_CHANNEL_CTL_2_RUN", - H2C_CHANNEL_CTL_2_RUN_MASK}, -}; - - -static struct regfield_info - h2c_mm_status_field_info[] = { - {"H2C_MM_STATUS_RSVD_1", - H2C_MM_STATUS_RSVD_1_MASK}, - {"H2C_MM_STATUS_RUN", - H2C_MM_STATUS_RUN_MASK}, -}; - - -static struct regfield_info - h2c_channel_cmpl_desc_cnt_field_info[] = { - {"H2C_CHANNEL_CMPL_DESC_CNT_H2C_CO", - H2C_CHANNEL_CMPL_DESC_CNT_H2C_CO_MASK}, -}; - - -static struct regfield_info - h2c_mm_err_code_enable_mask_field_info[] = { - {"H2C_MM_ERR_CODE_ENABLE_RSVD_1", - H2C_MM_ERR_CODE_ENABLE_RSVD_1_MASK}, - {"H2C_MM_ERR_CODE_ENABLE_WR_SLV_ERR", - H2C_MM_ERR_CODE_ENABLE_WR_SLV_ERR_MASK}, - {"H2C_MM_ERR_CODE_ENABLE_WR_DEC_ERR", - H2C_MM_ERR_CODE_ENABLE_WR_DEC_ERR_MASK}, - {"H2C_MM_ERR_CODE_ENABLE_RSVD_2", - H2C_MM_ERR_CODE_ENABLE_RSVD_2_MASK}, - {"H2C_MM_ERR_CODE_ENABLE_RD_RQ_DIS_ERR", - H2C_MM_ERR_CODE_ENABLE_RD_RQ_DIS_ERR_MASK}, - {"H2C_MM_ERR_CODE_ENABLE_RSVD_3", - H2C_MM_ERR_CODE_ENABLE_RSVD_3_MASK}, - {"H2C_MM_ERR_CODE_ENABLE_RD_DAT_POISON_ERR", - H2C_MM_ERR_CODE_ENABLE_RD_DAT_POISON_ERR_MASK}, - {"H2C_MM_ERR_CODE_ENABLE_RSVD_4", - H2C_MM_ERR_CODE_ENABLE_RSVD_4_MASK}, - {"H2C_MM_ERR_CODE_ENABLE_RD_FLR_ERR", - H2C_MM_ERR_CODE_ENABLE_RD_FLR_ERR_MASK}, - {"H2C_MM_ERR_CODE_ENABLE_RSVD_5", - H2C_MM_ERR_CODE_ENABLE_RSVD_5_MASK}, - {"H2C_MM_ERR_CODE_ENABLE_RD_HDR_ADR_ERR", - H2C_MM_ERR_CODE_ENABLE_RD_HDR_ADR_ERR_MASK}, - {"H2C_MM_ERR_CODE_ENABLE_RD_HDR_PARA", - H2C_MM_ERR_CODE_ENABLE_RD_HDR_PARA_MASK}, - {"H2C_MM_ERR_CODE_ENABLE_RD_HDR_BYTE_ERR", - H2C_MM_ERR_CODE_ENABLE_RD_HDR_BYTE_ERR_MASK}, - {"H2C_MM_ERR_CODE_ENABLE_RD_UR_CA", - H2C_MM_ERR_CODE_ENABLE_RD_UR_CA_MASK}, - {"H2C_MM_ERR_CODE_ENABLE_RD_HRD_POISON_ERR", - H2C_MM_ERR_CODE_ENABLE_RD_HRD_POISON_ERR_MASK}, - {"H2C_MM_ERR_CODE_ENABLE_RSVD_6", - H2C_MM_ERR_CODE_ENABLE_RSVD_6_MASK}, -}; - - -static struct regfield_info - h2c_mm_err_code_field_info[] = { - {"H2C_MM_ERR_CODE_RSVD_1", - H2C_MM_ERR_CODE_RSVD_1_MASK}, - {"H2C_MM_ERR_CODE_VALID", - H2C_MM_ERR_CODE_VALID_MASK}, - {"H2C_MM_ERR_CODE_RDWR", - H2C_MM_ERR_CODE_RDWR_MASK}, - {"H2C_MM_ERR_CODE", - H2C_MM_ERR_CODE_MASK}, -}; - - -static struct regfield_info - h2c_mm_err_info_field_info[] = { - {"H2C_MM_ERR_INFO_RSVD_1", - H2C_MM_ERR_INFO_RSVD_1_MASK}, - {"H2C_MM_ERR_INFO_QID", - H2C_MM_ERR_INFO_QID_MASK}, - {"H2C_MM_ERR_INFO_DIR", - H2C_MM_ERR_INFO_DIR_MASK}, - {"H2C_MM_ERR_INFO_CIDX", - H2C_MM_ERR_INFO_CIDX_MASK}, -}; - - -static struct regfield_info - h2c_mm_perf_mon_ctl_field_info[] = { - {"H2C_MM_PERF_MON_CTL_RSVD_1", - H2C_MM_PERF_MON_CTL_RSVD_1_MASK}, - {"H2C_MM_PERF_MON_CTL_IMM_START", - H2C_MM_PERF_MON_CTL_IMM_START_MASK}, - {"H2C_MM_PERF_MON_CTL_RUN_START", - H2C_MM_PERF_MON_CTL_RUN_START_MASK}, - {"H2C_MM_PERF_MON_CTL_IMM_CLEAR", - H2C_MM_PERF_MON_CTL_IMM_CLEAR_MASK}, - {"H2C_MM_PERF_MON_CTL_RUN_CLEAR", - H2C_MM_PERF_MON_CTL_RUN_CLEAR_MASK}, -}; - - -static struct regfield_info - h2c_mm_perf_mon_cycle_cnt0_field_info[] = { - {"H2C_MM_PERF_MON_CYCLE_CNT0_CYC_CNT", - H2C_MM_PERF_MON_CYCLE_CNT0_CYC_CNT_MASK}, -}; - - -static struct regfield_info - h2c_mm_perf_mon_cycle_cnt1_field_info[] = { - {"H2C_MM_PERF_MON_CYCLE_CNT1_RSVD_1", - H2C_MM_PERF_MON_CYCLE_CNT1_RSVD_1_MASK}, - {"H2C_MM_PERF_MON_CYCLE_CNT1_CYC_CNT", - H2C_MM_PERF_MON_CYCLE_CNT1_CYC_CNT_MASK}, -}; - - -static struct regfield_info - h2c_mm_perf_mon_data_cnt0_field_info[] = { - {"H2C_MM_PERF_MON_DATA_CNT0_DCNT", - H2C_MM_PERF_MON_DATA_CNT0_DCNT_MASK}, -}; - - -static struct regfield_info - h2c_mm_perf_mon_data_cnt1_field_info[] = { - {"H2C_MM_PERF_MON_DATA_CNT1_RSVD_1", - H2C_MM_PERF_MON_DATA_CNT1_RSVD_1_MASK}, - {"H2C_MM_PERF_MON_DATA_CNT1_DCNT", - H2C_MM_PERF_MON_DATA_CNT1_DCNT_MASK}, -}; - - -static struct regfield_info - h2c_mm_dbg_field_info[] = { - {"H2C_MM_RSVD_1", - H2C_MM_RSVD_1_MASK}, - {"H2C_MM_RRQ_ENTRIES", - H2C_MM_RRQ_ENTRIES_MASK}, - {"H2C_MM_DAT_FIFO_SPC", - H2C_MM_DAT_FIFO_SPC_MASK}, - {"H2C_MM_RD_STALL", - H2C_MM_RD_STALL_MASK}, - {"H2C_MM_RRQ_FIFO_FI", - H2C_MM_RRQ_FIFO_FI_MASK}, - {"H2C_MM_WR_STALL", - H2C_MM_WR_STALL_MASK}, - {"H2C_MM_WRQ_FIFO_FI", - H2C_MM_WRQ_FIFO_FI_MASK}, - {"H2C_MM_WBK_STALL", - H2C_MM_WBK_STALL_MASK}, - {"H2C_MM_DSC_FIFO_EP", - H2C_MM_DSC_FIFO_EP_MASK}, - {"H2C_MM_DSC_FIFO_FL", - H2C_MM_DSC_FIFO_FL_MASK}, -}; - - -static struct regfield_info - func_status_reg_field_info[] = { - {"FUNC_STATUS_REG_RSVD_1", - FUNC_STATUS_REG_RSVD_1_MASK}, - {"FUNC_STATUS_REG_CUR_SRC_FN", - FUNC_STATUS_REG_CUR_SRC_FN_MASK}, - {"FUNC_STATUS_REG_ACK", - FUNC_STATUS_REG_ACK_MASK}, - {"FUNC_STATUS_REG_O_MSG", - FUNC_STATUS_REG_O_MSG_MASK}, - {"FUNC_STATUS_REG_I_MSG", - FUNC_STATUS_REG_I_MSG_MASK}, -}; - - -static struct regfield_info - func_cmd_reg_field_info[] = { - {"FUNC_CMD_REG_RSVD_1", - FUNC_CMD_REG_RSVD_1_MASK}, - {"FUNC_CMD_REG_RSVD_2", - FUNC_CMD_REG_RSVD_2_MASK}, - {"FUNC_CMD_REG_MSG_RCV", - FUNC_CMD_REG_MSG_RCV_MASK}, - {"FUNC_CMD_REG_MSG_SENT", - FUNC_CMD_REG_MSG_SENT_MASK}, -}; - - -static struct regfield_info - func_interrupt_vector_reg_field_info[] = { - {"FUNC_INTERRUPT_VECTOR_REG_RSVD_1", - FUNC_INTERRUPT_VECTOR_REG_RSVD_1_MASK}, - {"FUNC_INTERRUPT_VECTOR_REG_IN", - FUNC_INTERRUPT_VECTOR_REG_IN_MASK}, -}; - - -static struct regfield_info - target_func_reg_field_info[] = { - {"TARGET_FUNC_REG_RSVD_1", - TARGET_FUNC_REG_RSVD_1_MASK}, - {"TARGET_FUNC_REG_N_ID", - TARGET_FUNC_REG_N_ID_MASK}, -}; - - -static struct regfield_info - func_interrupt_ctl_reg_field_info[] = { - {"FUNC_INTERRUPT_CTL_REG_RSVD_1", - FUNC_INTERRUPT_CTL_REG_RSVD_1_MASK}, - {"FUNC_INTERRUPT_CTL_REG_INT_EN", - FUNC_INTERRUPT_CTL_REG_INT_EN_MASK}, -}; - -static struct xreg_info qdma_cpm4_config_regs[] = { -{"CFG_BLK_IDENTIFIER", 0x00, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(cfg_blk_identifier_field_info), - cfg_blk_identifier_field_info -}, -{"CFG_BLK_BUSDEV", 0x04, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(cfg_blk_busdev_field_info), - cfg_blk_busdev_field_info -}, -{"CFG_BLK_PCIE_MAX_PLD_SIZE", 0x08, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(cfg_blk_pcie_max_pld_size_field_info), - cfg_blk_pcie_max_pld_size_field_info -}, -{"CFG_BLK_PCIE_MAX_READ_REQ_SIZE", 0x0c, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(cfg_blk_pcie_max_read_req_size_field_info), - cfg_blk_pcie_max_read_req_size_field_info -}, -{"CFG_BLK_SYSTEM_ID", 0x10, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(cfg_blk_system_id_field_info), - cfg_blk_system_id_field_info -}, -{"CFG_BLK_MSI_ENABLE", 0x014, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(cfg_blk_msi_enable_field_info), - cfg_blk_msi_enable_field_info -}, -{"CFG_PCIE_DATA_WIDTH", 0x18, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(cfg_pcie_data_width_field_info), - cfg_pcie_data_width_field_info -}, -{"CFG_PCIE_CTL", 0x1c, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(cfg_pcie_ctl_field_info), - cfg_pcie_ctl_field_info -}, -{"CFG_AXI_USER_MAX_PLD_SIZE", 0x40, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(cfg_axi_user_max_pld_size_field_info), - cfg_axi_user_max_pld_size_field_info -}, -{"CFG_AXI_USER_MAX_READ_REQ_SIZE", 0x44, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(cfg_axi_user_max_read_req_size_field_info), - cfg_axi_user_max_read_req_size_field_info -}, -{"CFG_BLK_MISC_CTL", 0x4c, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(cfg_blk_misc_ctl_field_info), - cfg_blk_misc_ctl_field_info -}, -{"CFG_BLK_SCRATCH_0", 0x80, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(cfg_blk_scratch_0_field_info), - cfg_blk_scratch_0_field_info -}, -{"CFG_BLK_SCRATCH_1", 0x84, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(cfg_blk_scratch_1_field_info), - cfg_blk_scratch_1_field_info -}, -{"CFG_BLK_SCRATCH_2", 0x88, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(cfg_blk_scratch_2_field_info), - cfg_blk_scratch_2_field_info -}, -{"CFG_BLK_SCRATCH_3", 0x8c, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(cfg_blk_scratch_3_field_info), - cfg_blk_scratch_3_field_info -}, -{"CFG_BLK_SCRATCH_4", 0x90, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(cfg_blk_scratch_4_field_info), - cfg_blk_scratch_4_field_info -}, -{"CFG_BLK_SCRATCH_5", 0x94, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(cfg_blk_scratch_5_field_info), - cfg_blk_scratch_5_field_info -}, -{"CFG_BLK_SCRATCH_6", 0x98, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(cfg_blk_scratch_6_field_info), - cfg_blk_scratch_6_field_info -}, -{"CFG_BLK_SCRATCH_7", 0x9c, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(cfg_blk_scratch_7_field_info), - cfg_blk_scratch_7_field_info -}, -{"RAM_SBE_MSK_A", 0xf0, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(ram_sbe_msk_a_field_info), - ram_sbe_msk_a_field_info -}, -{"RAM_SBE_STS_A", 0xf4, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(ram_sbe_sts_a_field_info), - ram_sbe_sts_a_field_info -}, -{"RAM_DBE_MSK_A", 0xf8, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(ram_dbe_msk_a_field_info), - ram_dbe_msk_a_field_info -}, -{"RAM_DBE_STS_A", 0xfc, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(ram_dbe_sts_a_field_info), - ram_dbe_sts_a_field_info -}, -{"GLBL2_IDENTIFIER", 0x100, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(glbl2_identifier_field_info), - glbl2_identifier_field_info -}, -{"GLBL2_PF_BARLITE_INT", 0x104, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(glbl2_pf_barlite_int_field_info), - glbl2_pf_barlite_int_field_info -}, -{"GLBL2_PF_VF_BARLITE_INT", 0x108, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(glbl2_pf_vf_barlite_int_field_info), - glbl2_pf_vf_barlite_int_field_info -}, -{"GLBL2_PF_BARLITE_EXT", 0x10c, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(glbl2_pf_barlite_ext_field_info), - glbl2_pf_barlite_ext_field_info -}, -{"GLBL2_PF_VF_BARLITE_EXT", 0x110, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(glbl2_pf_vf_barlite_ext_field_info), - glbl2_pf_vf_barlite_ext_field_info -}, -{"GLBL2_CHANNEL_INST", 0x114, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(glbl2_channel_inst_field_info), - glbl2_channel_inst_field_info -}, -{"GLBL2_CHANNEL_MDMA", 0x118, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(glbl2_channel_mdma_field_info), - glbl2_channel_mdma_field_info -}, -{"GLBL2_CHANNEL_STRM", 0x11c, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(glbl2_channel_strm_field_info), - glbl2_channel_strm_field_info -}, -{"GLBL2_CHANNEL_CAP", 0x120, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(glbl2_channel_cap_field_info), - glbl2_channel_cap_field_info -}, -{"GLBL2_CHANNEL_PASID_CAP", 0x128, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(glbl2_channel_pasid_cap_field_info), - glbl2_channel_pasid_cap_field_info -}, -{"GLBL2_CHANNEL_FUNC_RET", 0x12c, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(glbl2_channel_func_ret_field_info), - glbl2_channel_func_ret_field_info -}, -{"GLBL2_SYSTEM_ID", 0x130, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(glbl2_system_id_field_info), - glbl2_system_id_field_info -}, -{"GLBL2_MISC_CAP", 0x134, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(glbl2_misc_cap_field_info), - glbl2_misc_cap_field_info -}, -{"GLBL2_DBG_PCIE_RQ0", 0x1b8, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(glbl2_dbg_pcie_rq0_field_info), - glbl2_dbg_pcie_rq0_field_info -}, -{"GLBL2_DBG_PCIE_RQ1", 0x1bc, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(glbl2_dbg_pcie_rq1_field_info), - glbl2_dbg_pcie_rq1_field_info -}, -{"GLBL2_DBG_AXIMM_WR0", 0x1c0, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(glbl2_dbg_aximm_wr0_field_info), - glbl2_dbg_aximm_wr0_field_info -}, -{"GLBL2_DBG_AXIMM_WR1", 0x1c4, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(glbl2_dbg_aximm_wr1_field_info), - glbl2_dbg_aximm_wr1_field_info -}, -{"GLBL2_DBG_AXIMM_RD0", 0x1c8, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(glbl2_dbg_aximm_rd0_field_info), - glbl2_dbg_aximm_rd0_field_info -}, -{"GLBL2_DBG_AXIMM_RD1", 0x1cc, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(glbl2_dbg_aximm_rd1_field_info), - glbl2_dbg_aximm_rd1_field_info -}, -{"GLBL_RNG_SZ_1", 0x204, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(glbl_rng_sz_1_field_info), - glbl_rng_sz_1_field_info -}, -{"GLBL_RNG_SZ_2", 0x208, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(glbl_rng_sz_2_field_info), - glbl_rng_sz_2_field_info -}, -{"GLBL_RNG_SZ_3", 0x20c, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(glbl_rng_sz_3_field_info), - glbl_rng_sz_3_field_info -}, -{"GLBL_RNG_SZ_4", 0x210, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(glbl_rng_sz_4_field_info), - glbl_rng_sz_4_field_info -}, -{"GLBL_RNG_SZ_5", 0x214, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(glbl_rng_sz_5_field_info), - glbl_rng_sz_5_field_info -}, -{"GLBL_RNG_SZ_6", 0x218, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(glbl_rng_sz_6_field_info), - glbl_rng_sz_6_field_info -}, -{"GLBL_RNG_SZ_7", 0x21c, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(glbl_rng_sz_7_field_info), - glbl_rng_sz_7_field_info -}, -{"GLBL_RNG_SZ_8", 0x220, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(glbl_rng_sz_8_field_info), - glbl_rng_sz_8_field_info -}, -{"GLBL_RNG_SZ_9", 0x224, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(glbl_rng_sz_9_field_info), - glbl_rng_sz_9_field_info -}, -{"GLBL_RNG_SZ_A", 0x228, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(glbl_rng_sz_a_field_info), - glbl_rng_sz_a_field_info -}, -{"GLBL_RNG_SZ_B", 0x22c, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(glbl_rng_sz_b_field_info), - glbl_rng_sz_b_field_info -}, -{"GLBL_RNG_SZ_C", 0x230, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(glbl_rng_sz_c_field_info), - glbl_rng_sz_c_field_info -}, -{"GLBL_RNG_SZ_D", 0x234, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(glbl_rng_sz_d_field_info), - glbl_rng_sz_d_field_info -}, -{"GLBL_RNG_SZ_E", 0x238, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(glbl_rng_sz_e_field_info), - glbl_rng_sz_e_field_info -}, -{"GLBL_RNG_SZ_F", 0x23c, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(glbl_rng_sz_f_field_info), - glbl_rng_sz_f_field_info -}, -{"GLBL_RNG_SZ_10", 0x240, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(glbl_rng_sz_10_field_info), - glbl_rng_sz_10_field_info -}, -{"GLBL_ERR_STAT", 0x248, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(glbl_err_stat_field_info), - glbl_err_stat_field_info -}, -{"GLBL_ERR_MASK", 0x24c, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(glbl_err_mask_field_info), - glbl_err_mask_field_info -}, -{"GLBL_DSC_CFG", 0x250, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(glbl_dsc_cfg_field_info), - glbl_dsc_cfg_field_info -}, -{"GLBL_DSC_ERR_STS", 0x254, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(glbl_dsc_err_sts_field_info), - glbl_dsc_err_sts_field_info -}, -{"GLBL_DSC_ERR_MSK", 0x258, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(glbl_dsc_err_msk_field_info), - glbl_dsc_err_msk_field_info -}, -{"GLBL_DSC_ERR_LOG0", 0x25c, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(glbl_dsc_err_log0_field_info), - glbl_dsc_err_log0_field_info -}, -{"GLBL_DSC_ERR_LOG1", 0x260, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(glbl_dsc_err_log1_field_info), - glbl_dsc_err_log1_field_info -}, -{"GLBL_TRQ_ERR_STS", 0x264, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(glbl_trq_err_sts_field_info), - glbl_trq_err_sts_field_info -}, -{"GLBL_TRQ_ERR_MSK", 0x268, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(glbl_trq_err_msk_field_info), - glbl_trq_err_msk_field_info -}, -{"GLBL_TRQ_ERR_LOG", 0x26c, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(glbl_trq_err_log_field_info), - glbl_trq_err_log_field_info -}, -{"GLBL_DSC_DBG_DAT0", 0x270, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(glbl_dsc_dbg_dat0_field_info), - glbl_dsc_dbg_dat0_field_info -}, -{"GLBL_DSC_DBG_DAT1", 0x274, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(glbl_dsc_dbg_dat1_field_info), - glbl_dsc_dbg_dat1_field_info -}, -{"TRQ_SEL_FMAP_0", 0x400, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_0_field_info), - trq_sel_fmap_0_field_info -}, -{"TRQ_SEL_FMAP_1", 0x404, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_1_field_info), - trq_sel_fmap_1_field_info -}, -{"TRQ_SEL_FMAP_2", 0x408, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_2_field_info), - trq_sel_fmap_2_field_info -}, -{"TRQ_SEL_FMAP_3", 0x40c, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_3_field_info), - trq_sel_fmap_3_field_info -}, -{"TRQ_SEL_FMAP_4", 0x410, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_4_field_info), - trq_sel_fmap_4_field_info -}, -{"TRQ_SEL_FMAP_5", 0x414, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_5_field_info), - trq_sel_fmap_5_field_info -}, -{"TRQ_SEL_FMAP_6", 0x418, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_6_field_info), - trq_sel_fmap_6_field_info -}, -{"TRQ_SEL_FMAP_7", 0x41c, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_7_field_info), - trq_sel_fmap_7_field_info -}, -{"TRQ_SEL_FMAP_8", 0x420, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_8_field_info), - trq_sel_fmap_8_field_info -}, -{"TRQ_SEL_FMAP_9", 0x424, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_9_field_info), - trq_sel_fmap_9_field_info -}, -{"TRQ_SEL_FMAP_A", 0x428, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_a_field_info), - trq_sel_fmap_a_field_info -}, -{"TRQ_SEL_FMAP_B", 0x42c, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_b_field_info), - trq_sel_fmap_b_field_info -}, -{"TRQ_SEL_FMAP_D", 0x430, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_d_field_info), - trq_sel_fmap_d_field_info -}, -{"TRQ_SEL_FMAP_E", 0x434, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_e_field_info), - trq_sel_fmap_e_field_info -}, -{"TRQ_SEL_FMAP_F", 0x438, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_f_field_info), - trq_sel_fmap_f_field_info -}, -{"TRQ_SEL_FMAP_10", 0x43c, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_10_field_info), - trq_sel_fmap_10_field_info -}, -{"TRQ_SEL_FMAP_11", 0x440, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_11_field_info), - trq_sel_fmap_11_field_info -}, -{"TRQ_SEL_FMAP_12", 0x444, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_12_field_info), - trq_sel_fmap_12_field_info -}, -{"TRQ_SEL_FMAP_13", 0x448, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_13_field_info), - trq_sel_fmap_13_field_info -}, -{"TRQ_SEL_FMAP_14", 0x44c, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_14_field_info), - trq_sel_fmap_14_field_info -}, -{"TRQ_SEL_FMAP_15", 0x450, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_15_field_info), - trq_sel_fmap_15_field_info -}, -{"TRQ_SEL_FMAP_16", 0x454, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_16_field_info), - trq_sel_fmap_16_field_info -}, -{"TRQ_SEL_FMAP_17", 0x458, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_17_field_info), - trq_sel_fmap_17_field_info -}, -{"TRQ_SEL_FMAP_18", 0x45c, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_18_field_info), - trq_sel_fmap_18_field_info -}, -{"TRQ_SEL_FMAP_19", 0x460, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_19_field_info), - trq_sel_fmap_19_field_info -}, -{"TRQ_SEL_FMAP_1A", 0x464, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_1a_field_info), - trq_sel_fmap_1a_field_info -}, -{"TRQ_SEL_FMAP_1B", 0x468, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_1b_field_info), - trq_sel_fmap_1b_field_info -}, -{"TRQ_SEL_FMAP_1C", 0x46c, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_1c_field_info), - trq_sel_fmap_1c_field_info -}, -{"TRQ_SEL_FMAP_1D", 0x470, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_1d_field_info), - trq_sel_fmap_1d_field_info -}, -{"TRQ_SEL_FMAP_1E", 0x474, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_1e_field_info), - trq_sel_fmap_1e_field_info -}, -{"TRQ_SEL_FMAP_1F", 0x478, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_1f_field_info), - trq_sel_fmap_1f_field_info -}, -{"TRQ_SEL_FMAP_20", 0x47c, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_20_field_info), - trq_sel_fmap_20_field_info -}, -{"TRQ_SEL_FMAP_21", 0x480, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_21_field_info), - trq_sel_fmap_21_field_info -}, -{"TRQ_SEL_FMAP_22", 0x484, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_22_field_info), - trq_sel_fmap_22_field_info -}, -{"TRQ_SEL_FMAP_23", 0x488, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_23_field_info), - trq_sel_fmap_23_field_info -}, -{"TRQ_SEL_FMAP_24", 0x48c, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_24_field_info), - trq_sel_fmap_24_field_info -}, -{"TRQ_SEL_FMAP_25", 0x490, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_25_field_info), - trq_sel_fmap_25_field_info -}, -{"TRQ_SEL_FMAP_26", 0x494, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_26_field_info), - trq_sel_fmap_26_field_info -}, -{"TRQ_SEL_FMAP_27", 0x498, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_27_field_info), - trq_sel_fmap_27_field_info -}, -{"TRQ_SEL_FMAP_28", 0x49c, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_28_field_info), - trq_sel_fmap_28_field_info -}, -{"TRQ_SEL_FMAP_29", 0x4a0, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_29_field_info), - trq_sel_fmap_29_field_info -}, -{"TRQ_SEL_FMAP_2A", 0x4a4, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_2a_field_info), - trq_sel_fmap_2a_field_info -}, -{"TRQ_SEL_FMAP_2B", 0x4a8, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_2b_field_info), - trq_sel_fmap_2b_field_info -}, -{"TRQ_SEL_FMAP_2C", 0x4ac, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_2c_field_info), - trq_sel_fmap_2c_field_info -}, -{"TRQ_SEL_FMAP_2D", 0x4b0, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_2d_field_info), - trq_sel_fmap_2d_field_info -}, -{"TRQ_SEL_FMAP_2E", 0x4b4, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_2e_field_info), - trq_sel_fmap_2e_field_info -}, -{"TRQ_SEL_FMAP_2F", 0x4b8, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_2f_field_info), - trq_sel_fmap_2f_field_info -}, -{"TRQ_SEL_FMAP_30", 0x4bc, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_30_field_info), - trq_sel_fmap_30_field_info -}, -{"TRQ_SEL_FMAP_31", 0x4d0, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_31_field_info), - trq_sel_fmap_31_field_info -}, -{"TRQ_SEL_FMAP_32", 0x4d4, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_32_field_info), - trq_sel_fmap_32_field_info -}, -{"TRQ_SEL_FMAP_33", 0x4d8, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_33_field_info), - trq_sel_fmap_33_field_info -}, -{"TRQ_SEL_FMAP_34", 0x4dc, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_34_field_info), - trq_sel_fmap_34_field_info -}, -{"TRQ_SEL_FMAP_35", 0x4e0, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_35_field_info), - trq_sel_fmap_35_field_info -}, -{"TRQ_SEL_FMAP_36", 0x4e4, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_36_field_info), - trq_sel_fmap_36_field_info -}, -{"TRQ_SEL_FMAP_37", 0x4e8, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_37_field_info), - trq_sel_fmap_37_field_info -}, -{"TRQ_SEL_FMAP_38", 0x4ec, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_38_field_info), - trq_sel_fmap_38_field_info -}, -{"TRQ_SEL_FMAP_39", 0x4f0, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_39_field_info), - trq_sel_fmap_39_field_info -}, -{"TRQ_SEL_FMAP_3A", 0x4f4, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_3a_field_info), - trq_sel_fmap_3a_field_info -}, -{"TRQ_SEL_FMAP_3B", 0x4f8, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_3b_field_info), - trq_sel_fmap_3b_field_info -}, -{"TRQ_SEL_FMAP_3C", 0x4fc, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_3c_field_info), - trq_sel_fmap_3c_field_info -}, -{"TRQ_SEL_FMAP_3D", 0x500, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_3d_field_info), - trq_sel_fmap_3d_field_info -}, -{"TRQ_SEL_FMAP_3E", 0x504, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_3e_field_info), - trq_sel_fmap_3e_field_info -}, -{"TRQ_SEL_FMAP_3F", 0x508, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_3f_field_info), - trq_sel_fmap_3f_field_info -}, -{"TRQ_SEL_FMAP_40", 0x50c, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_40_field_info), - trq_sel_fmap_40_field_info -}, -{"TRQ_SEL_FMAP_41", 0x510, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_41_field_info), - trq_sel_fmap_41_field_info -}, -{"TRQ_SEL_FMAP_42", 0x514, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_42_field_info), - trq_sel_fmap_42_field_info -}, -{"TRQ_SEL_FMAP_43", 0x518, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_43_field_info), - trq_sel_fmap_43_field_info -}, -{"TRQ_SEL_FMAP_44", 0x51c, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_44_field_info), - trq_sel_fmap_44_field_info -}, -{"TRQ_SEL_FMAP_45", 0x520, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_45_field_info), - trq_sel_fmap_45_field_info -}, -{"TRQ_SEL_FMAP_46", 0x524, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_46_field_info), - trq_sel_fmap_46_field_info -}, -{"TRQ_SEL_FMAP_47", 0x528, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_47_field_info), - trq_sel_fmap_47_field_info -}, -{"TRQ_SEL_FMAP_48", 0x52c, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_48_field_info), - trq_sel_fmap_48_field_info -}, -{"TRQ_SEL_FMAP_49", 0x530, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_49_field_info), - trq_sel_fmap_49_field_info -}, -{"TRQ_SEL_FMAP_4A", 0x534, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_4a_field_info), - trq_sel_fmap_4a_field_info -}, -{"TRQ_SEL_FMAP_4B", 0x538, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_4b_field_info), - trq_sel_fmap_4b_field_info -}, -{"TRQ_SEL_FMAP_4C", 0x53c, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_4c_field_info), - trq_sel_fmap_4c_field_info -}, -{"TRQ_SEL_FMAP_4D", 0x540, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_4d_field_info), - trq_sel_fmap_4d_field_info -}, -{"TRQ_SEL_FMAP_4E", 0x544, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_4e_field_info), - trq_sel_fmap_4e_field_info -}, -{"TRQ_SEL_FMAP_4F", 0x548, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_4f_field_info), - trq_sel_fmap_4f_field_info -}, -{"TRQ_SEL_FMAP_50", 0x54c, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_50_field_info), - trq_sel_fmap_50_field_info -}, -{"TRQ_SEL_FMAP_51", 0x550, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_51_field_info), - trq_sel_fmap_51_field_info -}, -{"TRQ_SEL_FMAP_52", 0x554, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_52_field_info), - trq_sel_fmap_52_field_info -}, -{"TRQ_SEL_FMAP_53", 0x558, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_53_field_info), - trq_sel_fmap_53_field_info -}, -{"TRQ_SEL_FMAP_54", 0x55c, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_54_field_info), - trq_sel_fmap_54_field_info -}, -{"TRQ_SEL_FMAP_55", 0x560, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_55_field_info), - trq_sel_fmap_55_field_info -}, -{"TRQ_SEL_FMAP_56", 0x564, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_56_field_info), - trq_sel_fmap_56_field_info -}, -{"TRQ_SEL_FMAP_57", 0x568, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_57_field_info), - trq_sel_fmap_57_field_info -}, -{"TRQ_SEL_FMAP_58", 0x56c, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_58_field_info), - trq_sel_fmap_58_field_info -}, -{"TRQ_SEL_FMAP_59", 0x570, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_59_field_info), - trq_sel_fmap_59_field_info -}, -{"TRQ_SEL_FMAP_5A", 0x574, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_5a_field_info), - trq_sel_fmap_5a_field_info -}, -{"TRQ_SEL_FMAP_5B", 0x578, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_5b_field_info), - trq_sel_fmap_5b_field_info -}, -{"TRQ_SEL_FMAP_5C", 0x57c, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_5c_field_info), - trq_sel_fmap_5c_field_info -}, -{"TRQ_SEL_FMAP_5D", 0x580, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_5d_field_info), - trq_sel_fmap_5d_field_info -}, -{"TRQ_SEL_FMAP_5E", 0x584, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_5e_field_info), - trq_sel_fmap_5e_field_info -}, -{"TRQ_SEL_FMAP_5F", 0x588, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_5f_field_info), - trq_sel_fmap_5f_field_info -}, -{"TRQ_SEL_FMAP_60", 0x58c, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_60_field_info), - trq_sel_fmap_60_field_info -}, -{"TRQ_SEL_FMAP_61", 0x590, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_61_field_info), - trq_sel_fmap_61_field_info -}, -{"TRQ_SEL_FMAP_62", 0x594, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_62_field_info), - trq_sel_fmap_62_field_info -}, -{"TRQ_SEL_FMAP_63", 0x598, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_63_field_info), - trq_sel_fmap_63_field_info -}, -{"TRQ_SEL_FMAP_64", 0x59c, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_64_field_info), - trq_sel_fmap_64_field_info -}, -{"TRQ_SEL_FMAP_65", 0x5a0, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_65_field_info), - trq_sel_fmap_65_field_info -}, -{"TRQ_SEL_FMAP_66", 0x5a4, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_66_field_info), - trq_sel_fmap_66_field_info -}, -{"TRQ_SEL_FMAP_67", 0x5a8, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_67_field_info), - trq_sel_fmap_67_field_info -}, -{"TRQ_SEL_FMAP_68", 0x5ac, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_68_field_info), - trq_sel_fmap_68_field_info -}, -{"TRQ_SEL_FMAP_69", 0x5b0, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_69_field_info), - trq_sel_fmap_69_field_info -}, -{"TRQ_SEL_FMAP_6A", 0x5b4, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_6a_field_info), - trq_sel_fmap_6a_field_info -}, -{"TRQ_SEL_FMAP_6B", 0x5b8, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_6b_field_info), - trq_sel_fmap_6b_field_info -}, -{"TRQ_SEL_FMAP_6C", 0x5bc, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_6c_field_info), - trq_sel_fmap_6c_field_info -}, -{"TRQ_SEL_FMAP_6D", 0x5c0, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_6d_field_info), - trq_sel_fmap_6d_field_info -}, -{"TRQ_SEL_FMAP_6E", 0x5c4, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_6e_field_info), - trq_sel_fmap_6e_field_info -}, -{"TRQ_SEL_FMAP_6F", 0x5c8, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_6f_field_info), - trq_sel_fmap_6f_field_info -}, -{"TRQ_SEL_FMAP_70", 0x5cc, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_70_field_info), - trq_sel_fmap_70_field_info -}, -{"TRQ_SEL_FMAP_71", 0x5d0, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_71_field_info), - trq_sel_fmap_71_field_info -}, -{"TRQ_SEL_FMAP_72", 0x5d4, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_72_field_info), - trq_sel_fmap_72_field_info -}, -{"TRQ_SEL_FMAP_73", 0x5d8, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_73_field_info), - trq_sel_fmap_73_field_info -}, -{"TRQ_SEL_FMAP_74", 0x5dc, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_74_field_info), - trq_sel_fmap_74_field_info -}, -{"TRQ_SEL_FMAP_75", 0x5e0, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_75_field_info), - trq_sel_fmap_75_field_info -}, -{"TRQ_SEL_FMAP_76", 0x5e4, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_76_field_info), - trq_sel_fmap_76_field_info -}, -{"TRQ_SEL_FMAP_77", 0x5e8, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_77_field_info), - trq_sel_fmap_77_field_info -}, -{"TRQ_SEL_FMAP_78", 0x5ec, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_78_field_info), - trq_sel_fmap_78_field_info -}, -{"TRQ_SEL_FMAP_79", 0x5f0, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_79_field_info), - trq_sel_fmap_79_field_info -}, -{"TRQ_SEL_FMAP_7A", 0x5f4, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_7a_field_info), - trq_sel_fmap_7a_field_info -}, -{"TRQ_SEL_FMAP_7B", 0x5f8, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_7b_field_info), - trq_sel_fmap_7b_field_info -}, -{"TRQ_SEL_FMAP_7C", 0x5fc, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_7c_field_info), - trq_sel_fmap_7c_field_info -}, -{"TRQ_SEL_FMAP_7D", 0x600, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_7d_field_info), - trq_sel_fmap_7d_field_info -}, -{"TRQ_SEL_FMAP_7E", 0x604, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_7e_field_info), - trq_sel_fmap_7e_field_info -}, -{"TRQ_SEL_FMAP_7F", 0x608, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_7f_field_info), - trq_sel_fmap_7f_field_info -}, -{"TRQ_SEL_FMAP_80", 0x60c, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_80_field_info), - trq_sel_fmap_80_field_info -}, -{"TRQ_SEL_FMAP_81", 0x610, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_81_field_info), - trq_sel_fmap_81_field_info -}, -{"TRQ_SEL_FMAP_82", 0x614, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_82_field_info), - trq_sel_fmap_82_field_info -}, -{"TRQ_SEL_FMAP_83", 0x618, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_83_field_info), - trq_sel_fmap_83_field_info -}, -{"TRQ_SEL_FMAP_84", 0x61c, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_84_field_info), - trq_sel_fmap_84_field_info -}, -{"TRQ_SEL_FMAP_85", 0x620, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_85_field_info), - trq_sel_fmap_85_field_info -}, -{"TRQ_SEL_FMAP_86", 0x624, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_86_field_info), - trq_sel_fmap_86_field_info -}, -{"TRQ_SEL_FMAP_87", 0x628, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_87_field_info), - trq_sel_fmap_87_field_info -}, -{"TRQ_SEL_FMAP_88", 0x62c, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_88_field_info), - trq_sel_fmap_88_field_info -}, -{"TRQ_SEL_FMAP_89", 0x630, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_89_field_info), - trq_sel_fmap_89_field_info -}, -{"TRQ_SEL_FMAP_8A", 0x634, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_8a_field_info), - trq_sel_fmap_8a_field_info -}, -{"TRQ_SEL_FMAP_8B", 0x638, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_8b_field_info), - trq_sel_fmap_8b_field_info -}, -{"TRQ_SEL_FMAP_8C", 0x63c, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_8c_field_info), - trq_sel_fmap_8c_field_info -}, -{"TRQ_SEL_FMAP_8D", 0x640, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_8d_field_info), - trq_sel_fmap_8d_field_info -}, -{"TRQ_SEL_FMAP_8E", 0x644, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_8e_field_info), - trq_sel_fmap_8e_field_info -}, -{"TRQ_SEL_FMAP_8F", 0x648, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_8f_field_info), - trq_sel_fmap_8f_field_info -}, -{"TRQ_SEL_FMAP_90", 0x64c, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_90_field_info), - trq_sel_fmap_90_field_info -}, -{"TRQ_SEL_FMAP_91", 0x650, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_91_field_info), - trq_sel_fmap_91_field_info -}, -{"TRQ_SEL_FMAP_92", 0x654, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_92_field_info), - trq_sel_fmap_92_field_info -}, -{"TRQ_SEL_FMAP_93", 0x658, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_93_field_info), - trq_sel_fmap_93_field_info -}, -{"TRQ_SEL_FMAP_94", 0x65c, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_94_field_info), - trq_sel_fmap_94_field_info -}, -{"TRQ_SEL_FMAP_95", 0x660, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_95_field_info), - trq_sel_fmap_95_field_info -}, -{"TRQ_SEL_FMAP_96", 0x664, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_96_field_info), - trq_sel_fmap_96_field_info -}, -{"TRQ_SEL_FMAP_97", 0x668, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_97_field_info), - trq_sel_fmap_97_field_info -}, -{"TRQ_SEL_FMAP_98", 0x66c, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_98_field_info), - trq_sel_fmap_98_field_info -}, -{"TRQ_SEL_FMAP_99", 0x670, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_99_field_info), - trq_sel_fmap_99_field_info -}, -{"TRQ_SEL_FMAP_9A", 0x674, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_9a_field_info), - trq_sel_fmap_9a_field_info -}, -{"TRQ_SEL_FMAP_9B", 0x678, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_9b_field_info), - trq_sel_fmap_9b_field_info -}, -{"TRQ_SEL_FMAP_9C", 0x67c, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_9c_field_info), - trq_sel_fmap_9c_field_info -}, -{"TRQ_SEL_FMAP_9D", 0x680, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_9d_field_info), - trq_sel_fmap_9d_field_info -}, -{"TRQ_SEL_FMAP_9E", 0x684, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_9e_field_info), - trq_sel_fmap_9e_field_info -}, -{"TRQ_SEL_FMAP_9F", 0x688, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_9f_field_info), - trq_sel_fmap_9f_field_info -}, -{"TRQ_SEL_FMAP_A0", 0x68c, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_a0_field_info), - trq_sel_fmap_a0_field_info -}, -{"TRQ_SEL_FMAP_A1", 0x690, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_a1_field_info), - trq_sel_fmap_a1_field_info -}, -{"TRQ_SEL_FMAP_A2", 0x694, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_a2_field_info), - trq_sel_fmap_a2_field_info -}, -{"TRQ_SEL_FMAP_A3", 0x698, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_a3_field_info), - trq_sel_fmap_a3_field_info -}, -{"TRQ_SEL_FMAP_A4", 0x69c, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_a4_field_info), - trq_sel_fmap_a4_field_info -}, -{"TRQ_SEL_FMAP_A5", 0x6a0, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_a5_field_info), - trq_sel_fmap_a5_field_info -}, -{"TRQ_SEL_FMAP_A6", 0x6a4, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_a6_field_info), - trq_sel_fmap_a6_field_info -}, -{"TRQ_SEL_FMAP_A7", 0x6a8, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_a7_field_info), - trq_sel_fmap_a7_field_info -}, -{"TRQ_SEL_FMAP_A8", 0x6ac, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_a8_field_info), - trq_sel_fmap_a8_field_info -}, -{"TRQ_SEL_FMAP_A9", 0x6b0, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_a9_field_info), - trq_sel_fmap_a9_field_info -}, -{"TRQ_SEL_FMAP_AA", 0x6b4, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_aa_field_info), - trq_sel_fmap_aa_field_info -}, -{"TRQ_SEL_FMAP_AB", 0x6b8, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_ab_field_info), - trq_sel_fmap_ab_field_info -}, -{"TRQ_SEL_FMAP_AC", 0x6bc, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_ac_field_info), - trq_sel_fmap_ac_field_info -}, -{"TRQ_SEL_FMAP_AD", 0x6d0, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_ad_field_info), - trq_sel_fmap_ad_field_info -}, -{"TRQ_SEL_FMAP_AE", 0x6d4, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_ae_field_info), - trq_sel_fmap_ae_field_info -}, -{"TRQ_SEL_FMAP_AF", 0x6d8, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_af_field_info), - trq_sel_fmap_af_field_info -}, -{"TRQ_SEL_FMAP_B0", 0x6dc, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_b0_field_info), - trq_sel_fmap_b0_field_info -}, -{"TRQ_SEL_FMAP_B1", 0x6e0, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_b1_field_info), - trq_sel_fmap_b1_field_info -}, -{"TRQ_SEL_FMAP_B2", 0x6e4, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_b2_field_info), - trq_sel_fmap_b2_field_info -}, -{"TRQ_SEL_FMAP_B3", 0x6e8, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_b3_field_info), - trq_sel_fmap_b3_field_info -}, -{"TRQ_SEL_FMAP_B4", 0x6ec, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_b4_field_info), - trq_sel_fmap_b4_field_info -}, -{"TRQ_SEL_FMAP_B5", 0x6f0, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_b5_field_info), - trq_sel_fmap_b5_field_info -}, -{"TRQ_SEL_FMAP_B6", 0x6f4, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_b6_field_info), - trq_sel_fmap_b6_field_info -}, -{"TRQ_SEL_FMAP_B7", 0x6f8, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_b7_field_info), - trq_sel_fmap_b7_field_info -}, -{"TRQ_SEL_FMAP_B8", 0x6fc, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_b8_field_info), - trq_sel_fmap_b8_field_info -}, -{"TRQ_SEL_FMAP_B9", 0x700, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_b9_field_info), - trq_sel_fmap_b9_field_info -}, -{"TRQ_SEL_FMAP_BA", 0x704, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_ba_field_info), - trq_sel_fmap_ba_field_info -}, -{"TRQ_SEL_FMAP_BB", 0x708, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_bb_field_info), - trq_sel_fmap_bb_field_info -}, -{"TRQ_SEL_FMAP_BC", 0x70c, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_bc_field_info), - trq_sel_fmap_bc_field_info -}, -{"TRQ_SEL_FMAP_BD", 0x710, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_bd_field_info), - trq_sel_fmap_bd_field_info -}, -{"TRQ_SEL_FMAP_BE", 0x714, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_be_field_info), - trq_sel_fmap_be_field_info -}, -{"TRQ_SEL_FMAP_BF", 0x718, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_bf_field_info), - trq_sel_fmap_bf_field_info -}, -{"TRQ_SEL_FMAP_C0", 0x71c, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_c0_field_info), - trq_sel_fmap_c0_field_info -}, -{"TRQ_SEL_FMAP_C1", 0x720, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_c1_field_info), - trq_sel_fmap_c1_field_info -}, -{"TRQ_SEL_FMAP_C2", 0x734, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_c2_field_info), - trq_sel_fmap_c2_field_info -}, -{"TRQ_SEL_FMAP_C3", 0x748, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_c3_field_info), - trq_sel_fmap_c3_field_info -}, -{"TRQ_SEL_FMAP_C4", 0x74c, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_c4_field_info), - trq_sel_fmap_c4_field_info -}, -{"TRQ_SEL_FMAP_C5", 0x750, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_c5_field_info), - trq_sel_fmap_c5_field_info -}, -{"TRQ_SEL_FMAP_C6", 0x754, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_c6_field_info), - trq_sel_fmap_c6_field_info -}, -{"TRQ_SEL_FMAP_C7", 0x758, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_c7_field_info), - trq_sel_fmap_c7_field_info -}, -{"TRQ_SEL_FMAP_C8", 0x75c, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_c8_field_info), - trq_sel_fmap_c8_field_info -}, -{"TRQ_SEL_FMAP_C9", 0x760, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_c9_field_info), - trq_sel_fmap_c9_field_info -}, -{"TRQ_SEL_FMAP_CA", 0x764, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_ca_field_info), - trq_sel_fmap_ca_field_info -}, -{"TRQ_SEL_FMAP_CB", 0x768, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_cb_field_info), - trq_sel_fmap_cb_field_info -}, -{"TRQ_SEL_FMAP_CC", 0x76c, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_cc_field_info), - trq_sel_fmap_cc_field_info -}, -{"TRQ_SEL_FMAP_CD", 0x770, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_cd_field_info), - trq_sel_fmap_cd_field_info -}, -{"TRQ_SEL_FMAP_CE", 0x774, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_ce_field_info), - trq_sel_fmap_ce_field_info -}, -{"TRQ_SEL_FMAP_CF", 0x778, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_cf_field_info), - trq_sel_fmap_cf_field_info -}, -{"TRQ_SEL_FMAP_D0", 0x77c, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_d0_field_info), - trq_sel_fmap_d0_field_info -}, -{"TRQ_SEL_FMAP_D1", 0x780, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_d1_field_info), - trq_sel_fmap_d1_field_info -}, -{"TRQ_SEL_FMAP_D2", 0x784, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_d2_field_info), - trq_sel_fmap_d2_field_info -}, -{"TRQ_SEL_FMAP_D3", 0x788, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_d3_field_info), - trq_sel_fmap_d3_field_info -}, -{"TRQ_SEL_FMAP_D4", 0x78c, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_d4_field_info), - trq_sel_fmap_d4_field_info -}, -{"TRQ_SEL_FMAP_D5", 0x790, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_d5_field_info), - trq_sel_fmap_d5_field_info -}, -{"TRQ_SEL_FMAP_D6", 0x794, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_d6_field_info), - trq_sel_fmap_d6_field_info -}, -{"TRQ_SEL_FMAP_D7", 0x798, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_d7_field_info), - trq_sel_fmap_d7_field_info -}, -{"TRQ_SEL_FMAP_D8", 0x79c, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_d8_field_info), - trq_sel_fmap_d8_field_info -}, -{"TRQ_SEL_FMAP_D9", 0x7a0, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_d9_field_info), - trq_sel_fmap_d9_field_info -}, -{"TRQ_SEL_FMAP_DA", 0x7a4, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_da_field_info), - trq_sel_fmap_da_field_info -}, -{"TRQ_SEL_FMAP_DB", 0x7a8, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_db_field_info), - trq_sel_fmap_db_field_info -}, -{"TRQ_SEL_FMAP_DC", 0x7ac, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_dc_field_info), - trq_sel_fmap_dc_field_info -}, -{"TRQ_SEL_FMAP_DD", 0x7b0, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_dd_field_info), - trq_sel_fmap_dd_field_info -}, -{"TRQ_SEL_FMAP_DE", 0x7b4, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_de_field_info), - trq_sel_fmap_de_field_info -}, -{"TRQ_SEL_FMAP_DF", 0x7b8, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_df_field_info), - trq_sel_fmap_df_field_info -}, -{"TRQ_SEL_FMAP_E0", 0x7bc, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_e0_field_info), - trq_sel_fmap_e0_field_info -}, -{"TRQ_SEL_FMAP_E1", 0x7c0, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_e1_field_info), - trq_sel_fmap_e1_field_info -}, -{"TRQ_SEL_FMAP_E2", 0x7c4, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_e2_field_info), - trq_sel_fmap_e2_field_info -}, -{"TRQ_SEL_FMAP_E3", 0x7c8, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_e3_field_info), - trq_sel_fmap_e3_field_info -}, -{"TRQ_SEL_FMAP_E4", 0x7cc, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_e4_field_info), - trq_sel_fmap_e4_field_info -}, -{"TRQ_SEL_FMAP_E5", 0x7d0, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_e5_field_info), - trq_sel_fmap_e5_field_info -}, -{"TRQ_SEL_FMAP_E6", 0x7d4, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_e6_field_info), - trq_sel_fmap_e6_field_info -}, -{"TRQ_SEL_FMAP_E7", 0x7d8, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_e7_field_info), - trq_sel_fmap_e7_field_info -}, -{"TRQ_SEL_FMAP_E8", 0x7dc, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_e8_field_info), - trq_sel_fmap_e8_field_info -}, -{"TRQ_SEL_FMAP_E9", 0x7e0, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_e9_field_info), - trq_sel_fmap_e9_field_info -}, -{"TRQ_SEL_FMAP_EA", 0x7e4, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_ea_field_info), - trq_sel_fmap_ea_field_info -}, -{"TRQ_SEL_FMAP_EB", 0x7e8, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_eb_field_info), - trq_sel_fmap_eb_field_info -}, -{"TRQ_SEL_FMAP_EC", 0x7ec, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_ec_field_info), - trq_sel_fmap_ec_field_info -}, -{"TRQ_SEL_FMAP_ED", 0x7f0, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_ed_field_info), - trq_sel_fmap_ed_field_info -}, -{"TRQ_SEL_FMAP_EE", 0x7f4, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_ee_field_info), - trq_sel_fmap_ee_field_info -}, -{"TRQ_SEL_FMAP_EF", 0x7f8, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_ef_field_info), - trq_sel_fmap_ef_field_info -}, -{"TRQ_SEL_FMAP_F0", 0x7fc, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_f0_field_info), - trq_sel_fmap_f0_field_info -}, -{"IND_CTXT_DATA_3", 0x804, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(ind_ctxt_data_3_field_info), - ind_ctxt_data_3_field_info -}, -{"IND_CTXT_DATA_2", 0x808, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(ind_ctxt_data_2_field_info), - ind_ctxt_data_2_field_info -}, -{"IND_CTXT_DATA_1", 0x80c, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(ind_ctxt_data_1_field_info), - ind_ctxt_data_1_field_info -}, -{"IND_CTXT_DATA_0", 0x810, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(ind_ctxt_data_0_field_info), - ind_ctxt_data_0_field_info -}, -{"IND_CTXT3", 0x814, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(ind_ctxt3_field_info), - ind_ctxt3_field_info -}, -{"IND_CTXT2", 0x818, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(ind_ctxt2_field_info), - ind_ctxt2_field_info -}, -{"IND_CTXT1", 0x81c, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(ind_ctxt1_field_info), - ind_ctxt1_field_info -}, -{"IND_CTXT0", 0x820, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(ind_ctxt0_field_info), - ind_ctxt0_field_info -}, -{"IND_CTXT_CMD", 0x824, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(ind_ctxt_cmd_field_info), - ind_ctxt_cmd_field_info -}, -{"C2H_TIMER_CNT_1", 0xa00, - 1, 0, 0, 0, - 0, QDMA_COMPLETION_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_timer_cnt_1_field_info), - c2h_timer_cnt_1_field_info -}, -{"C2H_TIMER_CNT_2", 0xa04, - 1, 0, 0, 0, - 0, QDMA_COMPLETION_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_timer_cnt_2_field_info), - c2h_timer_cnt_2_field_info -}, -{"C2H_TIMER_CNT_3", 0xa08, - 1, 0, 0, 0, - 0, QDMA_COMPLETION_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_timer_cnt_3_field_info), - c2h_timer_cnt_3_field_info -}, -{"C2H_TIMER_CNT_4", 0xa0c, - 1, 0, 0, 0, - 0, QDMA_COMPLETION_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_timer_cnt_4_field_info), - c2h_timer_cnt_4_field_info -}, -{"C2H_TIMER_CNT_5", 0xa10, - 1, 0, 0, 0, - 0, QDMA_COMPLETION_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_timer_cnt_5_field_info), - c2h_timer_cnt_5_field_info -}, -{"C2H_TIMER_CNT_6", 0xa14, - 1, 0, 0, 0, - 0, QDMA_COMPLETION_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_timer_cnt_6_field_info), - c2h_timer_cnt_6_field_info -}, -{"C2H_TIMER_CNT_7", 0xa18, - 1, 0, 0, 0, - 0, QDMA_COMPLETION_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_timer_cnt_7_field_info), - c2h_timer_cnt_7_field_info -}, -{"C2H_TIMER_CNT_8", 0xa1c, - 1, 0, 0, 0, - 0, QDMA_COMPLETION_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_timer_cnt_8_field_info), - c2h_timer_cnt_8_field_info -}, -{"C2H_TIMER_CNT_9", 0xa20, - 1, 0, 0, 0, - 0, QDMA_COMPLETION_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_timer_cnt_9_field_info), - c2h_timer_cnt_9_field_info -}, -{"C2H_TIMER_CNT_A", 0xa24, - 1, 0, 0, 0, - 0, QDMA_COMPLETION_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_timer_cnt_a_field_info), - c2h_timer_cnt_a_field_info -}, -{"C2H_TIMER_CNT_B", 0xa28, - 1, 0, 0, 0, - 0, QDMA_COMPLETION_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_timer_cnt_b_field_info), - c2h_timer_cnt_b_field_info -}, -{"C2H_TIMER_CNT_C", 0xa2c, - 1, 0, 0, 0, - 0, QDMA_COMPLETION_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_timer_cnt_c_field_info), - c2h_timer_cnt_c_field_info -}, -{"C2H_TIMER_CNT_D", 0xa30, - 1, 0, 0, 0, - 0, QDMA_COMPLETION_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_timer_cnt_d_field_info), - c2h_timer_cnt_d_field_info -}, -{"C2H_TIMER_CNT_E", 0xa34, - 1, 0, 0, 0, - 0, QDMA_COMPLETION_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_timer_cnt_e_field_info), - c2h_timer_cnt_e_field_info -}, -{"C2H_TIMER_CNT_F", 0xa38, - 1, 0, 0, 0, - 0, QDMA_COMPLETION_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_timer_cnt_f_field_info), - c2h_timer_cnt_f_field_info -}, -{"C2H_TIMER_CNT_10", 0xa3c, - 1, 0, 0, 0, - 0, QDMA_COMPLETION_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_timer_cnt_10_field_info), - c2h_timer_cnt_10_field_info -}, -{"C2H_CNT_TH_1", 0xa40, - 1, 0, 0, 0, - 0, QDMA_COMPLETION_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_cnt_th_1_field_info), - c2h_cnt_th_1_field_info -}, -{"C2H_CNT_TH_2", 0xa44, - 1, 0, 0, 0, - 0, QDMA_COMPLETION_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_cnt_th_2_field_info), - c2h_cnt_th_2_field_info -}, -{"C2H_CNT_TH_3", 0xa48, - 1, 0, 0, 0, - 0, QDMA_COMPLETION_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_cnt_th_3_field_info), - c2h_cnt_th_3_field_info -}, -{"C2H_CNT_TH_4", 0xa4c, - 1, 0, 0, 0, - 0, QDMA_COMPLETION_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_cnt_th_4_field_info), - c2h_cnt_th_4_field_info -}, -{"C2H_CNT_TH_5", 0xa50, - 1, 0, 0, 0, - 0, QDMA_COMPLETION_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_cnt_th_5_field_info), - c2h_cnt_th_5_field_info -}, -{"C2H_CNT_TH_6", 0xa54, - 1, 0, 0, 0, - 0, QDMA_COMPLETION_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_cnt_th_6_field_info), - c2h_cnt_th_6_field_info -}, -{"C2H_CNT_TH_7", 0xa58, - 1, 0, 0, 0, - 0, QDMA_COMPLETION_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_cnt_th_7_field_info), - c2h_cnt_th_7_field_info -}, -{"C2H_CNT_TH_8", 0xa5c, - 1, 0, 0, 0, - 0, QDMA_COMPLETION_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_cnt_th_8_field_info), - c2h_cnt_th_8_field_info -}, -{"C2H_CNT_TH_9", 0xa60, - 1, 0, 0, 0, - 0, QDMA_COMPLETION_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_cnt_th_9_field_info), - c2h_cnt_th_9_field_info -}, -{"C2H_CNT_TH_A", 0xa64, - 1, 0, 0, 0, - 0, QDMA_COMPLETION_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_cnt_th_a_field_info), - c2h_cnt_th_a_field_info -}, -{"C2H_CNT_TH_B", 0xa68, - 1, 0, 0, 0, - 0, QDMA_COMPLETION_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_cnt_th_b_field_info), - c2h_cnt_th_b_field_info -}, -{"C2H_CNT_TH_C", 0xa6c, - 1, 0, 0, 0, - 0, QDMA_COMPLETION_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_cnt_th_c_field_info), - c2h_cnt_th_c_field_info -}, -{"C2H_CNT_TH_D", 0xa70, - 1, 0, 0, 0, - 0, QDMA_COMPLETION_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_cnt_th_d_field_info), - c2h_cnt_th_d_field_info -}, -{"C2H_CNT_TH_E", 0xa74, - 1, 0, 0, 0, - 0, QDMA_COMPLETION_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_cnt_th_e_field_info), - c2h_cnt_th_e_field_info -}, -{"C2H_CNT_TH_F", 0xa78, - 1, 0, 0, 0, - 0, QDMA_COMPLETION_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_cnt_th_f_field_info), - c2h_cnt_th_f_field_info -}, -{"C2H_CNT_TH_10", 0xa7c, - 1, 0, 0, 0, - 0, QDMA_COMPLETION_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_cnt_th_10_field_info), - c2h_cnt_th_10_field_info -}, -{"C2H_QID2VEC_MAP_QID", 0xa80, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_qid2vec_map_qid_field_info), - c2h_qid2vec_map_qid_field_info -}, -{"C2H_QID2VEC_MAP", 0xa84, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_qid2vec_map_field_info), - c2h_qid2vec_map_field_info -}, -{"C2H_STAT_S_AXIS_C2H_ACCEPTED", 0xa88, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(c2h_stat_s_axis_c2h_accepted_field_info), - c2h_stat_s_axis_c2h_accepted_field_info -}, -{"C2H_STAT_S_AXIS_WRB_ACCEPTED", 0xa8c, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(c2h_stat_s_axis_wrb_accepted_field_info), - c2h_stat_s_axis_wrb_accepted_field_info -}, -{"C2H_STAT_DESC_RSP_PKT_ACCEPTED", 0xa90, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(c2h_stat_desc_rsp_pkt_accepted_field_info), - c2h_stat_desc_rsp_pkt_accepted_field_info -}, -{"C2H_STAT_AXIS_PKG_CMP", 0xa94, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(c2h_stat_axis_pkg_cmp_field_info), - c2h_stat_axis_pkg_cmp_field_info -}, -{"C2H_STAT_DESC_RSP_ACCEPTED", 0xa98, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_stat_desc_rsp_accepted_field_info), - c2h_stat_desc_rsp_accepted_field_info -}, -{"C2H_STAT_DESC_RSP_CMP", 0xa9c, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_stat_desc_rsp_cmp_field_info), - c2h_stat_desc_rsp_cmp_field_info -}, -{"C2H_STAT_WRQ_OUT", 0xaa0, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_stat_wrq_out_field_info), - c2h_stat_wrq_out_field_info -}, -{"C2H_STAT_WPL_REN_ACCEPTED", 0xaa4, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_stat_wpl_ren_accepted_field_info), - c2h_stat_wpl_ren_accepted_field_info -}, -{"C2H_STAT_TOTAL_WRQ_LEN", 0xaa8, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_stat_total_wrq_len_field_info), - c2h_stat_total_wrq_len_field_info -}, -{"C2H_STAT_TOTAL_WPL_LEN", 0xaac, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_stat_total_wpl_len_field_info), - c2h_stat_total_wpl_len_field_info -}, -{"C2H_BUF_SZ_0", 0xab0, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_buf_sz_0_field_info), - c2h_buf_sz_0_field_info -}, -{"C2H_BUF_SZ_1", 0xab4, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_buf_sz_1_field_info), - c2h_buf_sz_1_field_info -}, -{"C2H_BUF_SZ_2", 0xab8, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_buf_sz_2_field_info), - c2h_buf_sz_2_field_info -}, -{"C2H_BUF_SZ_3", 0xabc, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_buf_sz_3_field_info), - c2h_buf_sz_3_field_info -}, -{"C2H_BUF_SZ_4", 0xac0, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_buf_sz_4_field_info), - c2h_buf_sz_4_field_info -}, -{"C2H_BUF_SZ_5", 0xac4, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_buf_sz_5_field_info), - c2h_buf_sz_5_field_info -}, -{"C2H_BUF_SZ_7", 0xac8, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_buf_sz_7_field_info), - c2h_buf_sz_7_field_info -}, -{"C2H_BUF_SZ_8", 0xacc, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_buf_sz_8_field_info), - c2h_buf_sz_8_field_info -}, -{"C2H_BUF_SZ_9", 0xad0, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_buf_sz_9_field_info), - c2h_buf_sz_9_field_info -}, -{"C2H_BUF_SZ_10", 0xad4, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_buf_sz_10_field_info), - c2h_buf_sz_10_field_info -}, -{"C2H_BUF_SZ_11", 0xad8, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_buf_sz_11_field_info), - c2h_buf_sz_11_field_info -}, -{"C2H_BUF_SZ_12", 0xae0, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_buf_sz_12_field_info), - c2h_buf_sz_12_field_info -}, -{"C2H_BUF_SZ_13", 0xae4, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_buf_sz_13_field_info), - c2h_buf_sz_13_field_info -}, -{"C2H_BUF_SZ_14", 0xae8, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_buf_sz_14_field_info), - c2h_buf_sz_14_field_info -}, -{"C2H_BUF_SZ_15", 0xaec, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_buf_sz_15_field_info), - c2h_buf_sz_15_field_info -}, -{"C2H_ERR_STAT", 0xaf0, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(c2h_err_stat_field_info), - c2h_err_stat_field_info -}, -{"C2H_ERR_MASK", 0xaf4, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(c2h_err_mask_field_info), - c2h_err_mask_field_info -}, -{"C2H_FATAL_ERR_STAT", 0xaf8, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(c2h_fatal_err_stat_field_info), - c2h_fatal_err_stat_field_info -}, -{"C2H_FATAL_ERR_MASK", 0xafc, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(c2h_fatal_err_mask_field_info), - c2h_fatal_err_mask_field_info -}, -{"C2H_FATAL_ERR_ENABLE", 0xb00, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(c2h_fatal_err_enable_field_info), - c2h_fatal_err_enable_field_info -}, -{"GLBL_ERR_INT", 0xb04, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(glbl_err_int_field_info), - glbl_err_int_field_info -}, -{"C2H_PFCH_CFG", 0xb08, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_pfch_cfg_field_info), - c2h_pfch_cfg_field_info -}, -{"C2H_INT_TIMER_TICK", 0xb0c, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_int_timer_tick_field_info), - c2h_int_timer_tick_field_info -}, -{"C2H_STAT_DESC_RSP_DROP_ACCEPTED", 0xb10, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(c2h_stat_desc_rsp_drop_accepted_field_info), - c2h_stat_desc_rsp_drop_accepted_field_info -}, -{"C2H_STAT_DESC_RSP_ERR_ACCEPTED", 0xb14, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(c2h_stat_desc_rsp_err_accepted_field_info), - c2h_stat_desc_rsp_err_accepted_field_info -}, -{"C2H_STAT_DESC_REQ", 0xb18, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_stat_desc_req_field_info), - c2h_stat_desc_req_field_info -}, -{"C2H_STAT_DBG_DMA_ENG_0", 0xb1c, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_stat_dbg_dma_eng_0_field_info), - c2h_stat_dbg_dma_eng_0_field_info -}, -{"C2H_STAT_DBG_DMA_ENG_1", 0xb20, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_stat_dbg_dma_eng_1_field_info), - c2h_stat_dbg_dma_eng_1_field_info -}, -{"C2H_STAT_DBG_DMA_ENG_2", 0xb24, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_stat_dbg_dma_eng_2_field_info), - c2h_stat_dbg_dma_eng_2_field_info -}, -{"C2H_STAT_DBG_DMA_ENG_3", 0xb28, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_stat_dbg_dma_eng_3_field_info), - c2h_stat_dbg_dma_eng_3_field_info -}, -{"C2H_DBG_PFCH_ERR_CTXT", 0xb2c, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_dbg_pfch_err_ctxt_field_info), - c2h_dbg_pfch_err_ctxt_field_info -}, -{"C2H_FIRST_ERR_QID", 0xb30, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(c2h_first_err_qid_field_info), - c2h_first_err_qid_field_info -}, -{"STAT_NUM_WRB_IN", 0xb34, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(stat_num_wrb_in_field_info), - stat_num_wrb_in_field_info -}, -{"STAT_NUM_WRB_OUT", 0xb38, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(stat_num_wrb_out_field_info), - stat_num_wrb_out_field_info -}, -{"STAT_NUM_WRB_DRP", 0xb3c, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(stat_num_wrb_drp_field_info), - stat_num_wrb_drp_field_info -}, -{"STAT_NUM_STAT_DESC_OUT", 0xb40, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(stat_num_stat_desc_out_field_info), - stat_num_stat_desc_out_field_info -}, -{"STAT_NUM_DSC_CRDT_SENT", 0xb44, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(stat_num_dsc_crdt_sent_field_info), - stat_num_dsc_crdt_sent_field_info -}, -{"STAT_NUM_FCH_DSC_RCVD", 0xb48, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(stat_num_fch_dsc_rcvd_field_info), - stat_num_fch_dsc_rcvd_field_info -}, -{"STAT_NUM_BYP_DSC_RCVD", 0xb4c, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(stat_num_byp_dsc_rcvd_field_info), - stat_num_byp_dsc_rcvd_field_info -}, -{"C2H_WRB_COAL_CFG", 0xb50, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_wrb_coal_cfg_field_info), - c2h_wrb_coal_cfg_field_info -}, -{"C2H_INTR_H2C_REQ", 0xb54, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(c2h_intr_h2c_req_field_info), - c2h_intr_h2c_req_field_info -}, -{"C2H_INTR_C2H_MM_REQ", 0xb58, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(c2h_intr_c2h_mm_req_field_info), - c2h_intr_c2h_mm_req_field_info -}, -{"C2H_INTR_ERR_INT_REQ", 0xb5c, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(c2h_intr_err_int_req_field_info), - c2h_intr_err_int_req_field_info -}, -{"C2H_INTR_C2H_ST_REQ", 0xb60, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(c2h_intr_c2h_st_req_field_info), - c2h_intr_c2h_st_req_field_info -}, -{"C2H_INTR_H2C_ERR_C2H_MM_MSIX_ACK", 0xb64, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_intr_h2c_err_c2h_mm_msix_ack_field_info), - c2h_intr_h2c_err_c2h_mm_msix_ack_field_info -}, -{"C2H_INTR_H2C_ERR_C2H_MM_MSIX_FAIL", 0xb68, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_intr_h2c_err_c2h_mm_msix_fail_field_info), - c2h_intr_h2c_err_c2h_mm_msix_fail_field_info -}, -{"C2H_INTR_H2C_ERR_C2H_MM_MSIX_NO_MSIX", 0xb6c, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_intr_h2c_err_c2h_mm_msix_no_msix_field_info), - c2h_intr_h2c_err_c2h_mm_msix_no_msix_field_info -}, -{"C2H_INTR_H2C_ERR_C2H_MM_CTXT_INVAL", 0xb70, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_intr_h2c_err_c2h_mm_ctxt_inval_field_info), - c2h_intr_h2c_err_c2h_mm_ctxt_inval_field_info -}, -{"C2H_INTR_C2H_ST_MSIX_ACK", 0xb74, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(c2h_intr_c2h_st_msix_ack_field_info), - c2h_intr_c2h_st_msix_ack_field_info -}, -{"C2H_INTR_C2H_ST_MSIX_FAIL", 0xb78, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(c2h_intr_c2h_st_msix_fail_field_info), - c2h_intr_c2h_st_msix_fail_field_info -}, -{"C2H_INTR_C2H_ST_NO_MSIX", 0xb7c, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_intr_c2h_st_no_msix_field_info), - c2h_intr_c2h_st_no_msix_field_info -}, -{"C2H_INTR_C2H_ST_CTXT_INVAL", 0xb80, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_intr_c2h_st_ctxt_inval_field_info), - c2h_intr_c2h_st_ctxt_inval_field_info -}, -{"C2H_STAT_WR_CMP", 0xb84, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_stat_wr_cmp_field_info), - c2h_stat_wr_cmp_field_info -}, -{"C2H_STAT_DBG_DMA_ENG_4", 0xb88, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_stat_dbg_dma_eng_4_field_info), - c2h_stat_dbg_dma_eng_4_field_info -}, -{"C2H_STAT_DBG_DMA_ENG_5", 0xb8c, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_stat_dbg_dma_eng_5_field_info), - c2h_stat_dbg_dma_eng_5_field_info -}, -{"C2H_DBG_PFCH_QID", 0xb90, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_dbg_pfch_qid_field_info), - c2h_dbg_pfch_qid_field_info -}, -{"C2H_DBG_PFCH", 0xb94, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_dbg_pfch_field_info), - c2h_dbg_pfch_field_info -}, -{"C2H_INT_DBG", 0xb98, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_int_dbg_field_info), - c2h_int_dbg_field_info -}, -{"C2H_STAT_IMM_ACCEPTED", 0xb9c, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_stat_imm_accepted_field_info), - c2h_stat_imm_accepted_field_info -}, -{"C2H_STAT_MARKER_ACCEPTED", 0xba0, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_stat_marker_accepted_field_info), - c2h_stat_marker_accepted_field_info -}, -{"C2H_STAT_DISABLE_CMP_ACCEPTED", 0xba4, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_stat_disable_cmp_accepted_field_info), - c2h_stat_disable_cmp_accepted_field_info -}, -{"C2H_PLD_FIFO_CRDT_CNT", 0xba8, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_pld_fifo_crdt_cnt_field_info), - c2h_pld_fifo_crdt_cnt_field_info -}, -{"H2C_ERR_STAT", 0xe00, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(h2c_err_stat_field_info), - h2c_err_stat_field_info -}, -{"H2C_ERR_MASK", 0xe04, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(h2c_err_mask_field_info), - h2c_err_mask_field_info -}, -{"H2C_FIRST_ERR_QID", 0xe08, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(h2c_first_err_qid_field_info), - h2c_first_err_qid_field_info -}, -{"H2C_DBG_REG0", 0xe0c, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(h2c_dbg_reg0_field_info), - h2c_dbg_reg0_field_info -}, -{"H2C_DBG_REG1", 0xe10, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(h2c_dbg_reg1_field_info), - h2c_dbg_reg1_field_info -}, -{"H2C_DBG_REG2", 0xe14, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(h2c_dbg_reg2_field_info), - h2c_dbg_reg2_field_info -}, -{"H2C_DBG_REG3", 0xe18, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(h2c_dbg_reg3_field_info), - h2c_dbg_reg3_field_info -}, -{"H2C_DBG_REG4", 0xe1c, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(h2c_dbg_reg4_field_info), - h2c_dbg_reg4_field_info -}, -{"H2C_FATAL_ERR_EN", 0xe20, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(h2c_fatal_err_en_field_info), - h2c_fatal_err_en_field_info -}, -{"C2H_CHANNEL_CTL", 0x1004, - 1, 0, 0, 0, - 0, QDMA_MM_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_channel_ctl_field_info), - c2h_channel_ctl_field_info -}, -{"C2H_CHANNEL_CTL_1", 0x1008, - 1, 0, 0, 0, - 0, QDMA_MM_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_channel_ctl_1_field_info), - c2h_channel_ctl_1_field_info -}, -{"C2H_MM_STATUS", 0x1040, - 1, 0, 0, 0, - 0, QDMA_MM_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_mm_status_field_info), - c2h_mm_status_field_info -}, -{"C2H_CHANNEL_CMPL_DESC_CNT", 0x1048, - 1, 0, 0, 0, - 0, QDMA_MM_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_channel_cmpl_desc_cnt_field_info), - c2h_channel_cmpl_desc_cnt_field_info -}, -{"C2H_MM_ERR_CODE_ENABLE_MASK", 0x1054, - 1, 0, 0, 0, - 0, QDMA_MM_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_mm_err_code_enable_mask_field_info), - c2h_mm_err_code_enable_mask_field_info -}, -{"C2H_MM_ERR_CODE", 0x1058, - 1, 0, 0, 0, - 0, QDMA_MM_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_mm_err_code_field_info), - c2h_mm_err_code_field_info -}, -{"C2H_MM_ERR_INFO", 0x105c, - 1, 0, 0, 0, - 0, QDMA_MM_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_mm_err_info_field_info), - c2h_mm_err_info_field_info -}, -{"C2H_MM_PERF_MON_CTL", 0x10c0, - 1, 0, 0, 0, - 0, QDMA_MM_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_mm_perf_mon_ctl_field_info), - c2h_mm_perf_mon_ctl_field_info -}, -{"C2H_MM_PERF_MON_CYCLE_CNT0", 0x10c4, - 1, 0, 0, 0, - 0, QDMA_MM_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_mm_perf_mon_cycle_cnt0_field_info), - c2h_mm_perf_mon_cycle_cnt0_field_info -}, -{"C2H_MM_PERF_MON_CYCLE_CNT1", 0x10c8, - 1, 0, 0, 0, - 0, QDMA_MM_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_mm_perf_mon_cycle_cnt1_field_info), - c2h_mm_perf_mon_cycle_cnt1_field_info -}, -{"C2H_MM_PERF_MON_DATA_CNT0", 0x10cc, - 1, 0, 0, 0, - 0, QDMA_MM_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_mm_perf_mon_data_cnt0_field_info), - c2h_mm_perf_mon_data_cnt0_field_info -}, -{"C2H_MM_PERF_MON_DATA_CNT1", 0x10d0, - 1, 0, 0, 0, - 0, QDMA_MM_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_mm_perf_mon_data_cnt1_field_info), - c2h_mm_perf_mon_data_cnt1_field_info -}, -{"C2H_MM_DBG", 0x10e8, - 1, 0, 0, 0, - 0, QDMA_MM_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_mm_dbg_field_info), - c2h_mm_dbg_field_info -}, -{"H2C_CHANNEL_CTL", 0x1204, - 1, 0, 0, 0, - 0, QDMA_MM_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(h2c_channel_ctl_field_info), - h2c_channel_ctl_field_info -}, -{"H2C_CHANNEL_CTL_1", 0x1208, - 1, 0, 0, 0, - 0, QDMA_MM_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(h2c_channel_ctl_1_field_info), - h2c_channel_ctl_1_field_info -}, -{"H2C_CHANNEL_CTL_2", 0x120c, - 1, 0, 0, 0, - 0, QDMA_MM_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(h2c_channel_ctl_2_field_info), - h2c_channel_ctl_2_field_info -}, -{"H2C_MM_STATUS", 0x1240, - 1, 0, 0, 0, - 0, QDMA_MM_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(h2c_mm_status_field_info), - h2c_mm_status_field_info -}, -{"H2C_CHANNEL_CMPL_DESC_CNT", 0x1248, - 1, 0, 0, 0, - 0, QDMA_MM_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(h2c_channel_cmpl_desc_cnt_field_info), - h2c_channel_cmpl_desc_cnt_field_info -}, -{"H2C_MM_ERR_CODE_ENABLE_MASK", 0x1254, - 1, 0, 0, 0, - 0, QDMA_MM_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(h2c_mm_err_code_enable_mask_field_info), - h2c_mm_err_code_enable_mask_field_info -}, -{"H2C_MM_ERR_CODE", 0x1258, - 1, 0, 0, 0, - 0, QDMA_MM_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(h2c_mm_err_code_field_info), - h2c_mm_err_code_field_info -}, -{"H2C_MM_ERR_INFO", 0x125c, - 1, 0, 0, 0, - 0, QDMA_MM_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(h2c_mm_err_info_field_info), - h2c_mm_err_info_field_info -}, -{"H2C_MM_PERF_MON_CTL", 0x12c0, - 1, 0, 0, 0, - 0, QDMA_MM_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(h2c_mm_perf_mon_ctl_field_info), - h2c_mm_perf_mon_ctl_field_info -}, -{"H2C_MM_PERF_MON_CYCLE_CNT0", 0x12c4, - 1, 0, 0, 0, - 0, QDMA_MM_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(h2c_mm_perf_mon_cycle_cnt0_field_info), - h2c_mm_perf_mon_cycle_cnt0_field_info -}, -{"H2C_MM_PERF_MON_CYCLE_CNT1", 0x12c8, - 1, 0, 0, 0, - 0, QDMA_MM_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(h2c_mm_perf_mon_cycle_cnt1_field_info), - h2c_mm_perf_mon_cycle_cnt1_field_info -}, -{"H2C_MM_PERF_MON_DATA_CNT0", 0x12cc, - 1, 0, 0, 0, - 0, QDMA_MM_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(h2c_mm_perf_mon_data_cnt0_field_info), - h2c_mm_perf_mon_data_cnt0_field_info -}, -{"H2C_MM_PERF_MON_DATA_CNT1", 0x12d0, - 1, 0, 0, 0, - 0, QDMA_MM_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(h2c_mm_perf_mon_data_cnt1_field_info), - h2c_mm_perf_mon_data_cnt1_field_info -}, -{"H2C_MM_DBG", 0x12e8, - 1, 0, 0, 0, - 0, QDMA_MM_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(h2c_mm_dbg_field_info), - h2c_mm_dbg_field_info -}, -{"FUNC_STATUS_REG", 0x2400, - 1, 0, 0, 0, - 0, QDMA_MAILBOX, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(func_status_reg_field_info), - func_status_reg_field_info -}, -{"FUNC_CMD_REG", 0x2404, - 1, 0, 0, 0, - 0, QDMA_MAILBOX, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(func_cmd_reg_field_info), - func_cmd_reg_field_info -}, -{"FUNC_INTERRUPT_VECTOR_REG", 0x2408, - 1, 0, 0, 0, - 0, QDMA_MAILBOX, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(func_interrupt_vector_reg_field_info), - func_interrupt_vector_reg_field_info -}, -{"TARGET_FUNC_REG", 0x240c, - 1, 0, 0, 0, - 0, QDMA_MAILBOX, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(target_func_reg_field_info), - target_func_reg_field_info -}, -{"FUNC_INTERRUPT_CTL_REG", 0x2410, - 1, 0, 0, 0, - 0, QDMA_MAILBOX, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(func_interrupt_ctl_reg_field_info), - func_interrupt_ctl_reg_field_info -}, - -}; - -uint32_t qdma_cpm4_config_num_regs_get(void) -{ - return (sizeof(qdma_cpm4_config_regs)/ - sizeof(qdma_cpm4_config_regs[0])); -} - -struct xreg_info *qdma_cpm4_config_regs_get(void) -{ - return qdma_cpm4_config_regs; -} - diff --git a/QDMA/DPDK/drivers/net/qdma/qdma_access/qdma_list.c b/QDMA/DPDK/drivers/net/qdma/qdma_access/qdma_list.c deleted file mode 100755 index 6cea8aa33..000000000 --- a/QDMA/DPDK/drivers/net/qdma/qdma_access/qdma_list.c +++ /dev/null @@ -1,78 +0,0 @@ -/* - * Copyright (c) 2019-2022, Xilinx, Inc. All rights reserved. - * Copyright (c) 2022, Advanced Micro Devices, Inc. All rights reserved. - * - * BSD LICENSE - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * * Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include "qdma_list.h" - -void qdma_list_init_head(struct qdma_list_head *head) -{ - if (head) - head->prev = head->next = head; -} - -void qdma_list_add_tail(struct qdma_list_head *node, - struct qdma_list_head *head) -{ - head->prev->next = node; - node->next = head; - node->prev = head->prev; - head->prev = node; -} - -void qdma_list_insert_before(struct qdma_list_head *new_node, - struct qdma_list_head *node) -{ - node->prev->next = new_node; - new_node->prev = node->prev; - new_node->next = node; - node->prev = new_node; -} - -void qdma_list_insert_after(struct qdma_list_head *new_node, - struct qdma_list_head *node) -{ - new_node->prev = node; - new_node->next = node->next; - node->next->prev = new_node; - node->next = new_node; -} - - -void qdma_list_del(struct qdma_list_head *node) -{ - if (node) { - if (node->prev) - node->prev->next = node->next; - if (node->next) - node->next->prev = node->prev; - } -} diff --git a/QDMA/DPDK/drivers/net/qdma/qdma_access/qdma_list.h b/QDMA/DPDK/drivers/net/qdma/qdma_access/qdma_list.h deleted file mode 100755 index f4224a4eb..000000000 --- a/QDMA/DPDK/drivers/net/qdma/qdma_access/qdma_list.h +++ /dev/null @@ -1,142 +0,0 @@ -/* - * Copyright (c) 2019-2022, Xilinx, Inc. All rights reserved. - * Copyright (c) 2022, Advanced Micro Devices, Inc. All rights reserved. - * - * BSD LICENSE - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * * Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#ifndef __QDMA_LIST_H_ -#define __QDMA_LIST_H_ - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * DOC: QDMA common library provided list implementation definitions - * - * Header file *qdma_list.h* defines APIs for creating and managing list. - */ - -/** - * struct qdma_list_head - data type for creating a list node - */ -struct qdma_list_head { - struct qdma_list_head *prev; - struct qdma_list_head *next; - void *priv; -}; - -#define QDMA_LIST_HEAD_INIT(name) { &(name), &(name), NULL } - -#define QDMA_LIST_HEAD(name) \ - struct qdma_list_head name = QDMA_LIST_HEAD_INIT(name) - -#define QDMA_LIST_GET_DATA(node) (node->priv) -#define QDMA_LIST_SET_DATA(node, data) ((node)->priv = data) - - -#define qdma_list_for_each_safe(pos, n, head) \ - for (pos = (head)->next, n = pos->next; pos != (head); \ - pos = n, n = pos->next) - - -#define qdma_list_is_last_entry(entry, head) ((entry)->next == (head)) - -#define qdma_list_is_empty(head) ((head)->next == (head)) - -/*****************************************************************************/ -/** - * qdma_list_init_head(): Init the list head - * - * @head: head of the list - * - * Return: None - *****************************************************************************/ -void qdma_list_init_head(struct qdma_list_head *head); - -/*****************************************************************************/ -/** - * qdma_list_add_tail(): add the given @node at the end of the list with @head - * - * @node: new entry which has to be added at the end of the list with @head - * @head: head of the list - * - * This API needs to be called with holding the lock to the list - * - * Return: None - *****************************************************************************/ -void qdma_list_add_tail(struct qdma_list_head *node, - struct qdma_list_head *head); - -/*****************************************************************************/ -/** - * qdma_list_insert_before(): add the given @node at the before a @node - * - * @new_node: new entry which has to be added before @node - * @node: reference node in the list - * - * This API needs to be called with holding the lock to the list - * - * Return: None - *****************************************************************************/ -void qdma_list_insert_before(struct qdma_list_head *new_node, - struct qdma_list_head *node); - -/*****************************************************************************/ -/** - * qdma_list_insert_after(): add the given @node at the after a @node - * - * @new_node: new entry which has to be added after @node - * @node: reference node in the list - * - * This API needs to be called with holding the lock to the list - * - * Return: None - *****************************************************************************/ -void qdma_list_insert_after(struct qdma_list_head *new_node, - struct qdma_list_head *node); - -/*****************************************************************************/ -/** - * qdma_list_del(): delete an node from the list - * - * @node: node in a list - * - * This API needs to be called with holding the lock to the list - * - * Return: None - *****************************************************************************/ -void qdma_list_del(struct qdma_list_head *node); - -#ifdef __cplusplus -} -#endif - -#endif /* __QDMA_LIST_H_ */ diff --git a/QDMA/DPDK/drivers/net/qdma/qdma_access/qdma_mbox_protocol.c b/QDMA/DPDK/drivers/net/qdma/qdma_access/qdma_mbox_protocol.c deleted file mode 100755 index 3dbae0d85..000000000 --- a/QDMA/DPDK/drivers/net/qdma/qdma_access/qdma_mbox_protocol.c +++ /dev/null @@ -1,2156 +0,0 @@ -/* - * Copyright (c) 2019-2022, Xilinx, Inc. All rights reserved. - * Copyright (c) 2022, Advanced Micro Devices, Inc. All rights reserved. - * - * BSD LICENSE - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * * Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include "qdma_mbox_protocol.h" - -/** mailbox function status */ -#define MBOX_FN_STATUS 0x0 -/** shift value for mailbox function status in msg */ -#define S_MBOX_FN_STATUS_IN_MSG 0 -/** mask value for mailbox function status in msg*/ -#define M_MBOX_FN_STATUS_IN_MSG 0x1 -/** face value for mailbox function status in msg */ -#define F_MBOX_FN_STATUS_IN_MSG 0x1 - -/** shift value for out msg */ -#define S_MBOX_FN_STATUS_OUT_MSG 1 -/** mask value for out msg */ -#define M_MBOX_FN_STATUS_OUT_MSG 0x1 -/** face value for out msg */ -#define F_MBOX_FN_STATUS_OUT_MSG (1 << S_MBOX_FN_STATUS_OUT_MSG) -/** shift value for status ack */ -#define S_MBOX_FN_STATUS_ACK 2 /* PF only, ack status */ -/** mask value for status ack */ -#define M_MBOX_FN_STATUS_ACK 0x1 -/** face value for status ack */ -#define F_MBOX_FN_STATUS_ACK (1 << S_MBOX_FN_STATUS_ACK) -/** shift value for status src */ -#define S_MBOX_FN_STATUS_SRC 4 /* PF only, source func.*/ -/** mask value for status src */ -#define M_MBOX_FN_STATUS_SRC 0xFFF -/** face value for status src */ -#define G_MBOX_FN_STATUS_SRC(x) \ - (((x) >> S_MBOX_FN_STATUS_SRC) & M_MBOX_FN_STATUS_SRC) -/** face value for mailbox function status */ -#define MBOX_FN_STATUS_MASK \ - (F_MBOX_FN_STATUS_IN_MSG | \ - F_MBOX_FN_STATUS_OUT_MSG | \ - F_MBOX_FN_STATUS_ACK) - -/** mailbox function commands register */ -#define MBOX_FN_CMD 0x4 -/** shift value for send command */ -#define S_MBOX_FN_CMD_SND 0 -/** mask value for send command */ -#define M_MBOX_FN_CMD_SND 0x1 -/** face value for send command */ -#define F_MBOX_FN_CMD_SND (1 << S_MBOX_FN_CMD_SND) -/** shift value for receive command */ -#define S_MBOX_FN_CMD_RCV 1 -/** mask value for receive command */ -#define M_MBOX_FN_CMD_RCV 0x1 -/** face value for receive command */ -#define F_MBOX_FN_CMD_RCV (1 << S_MBOX_FN_CMD_RCV) -/** shift value for vf reset */ -#define S_MBOX_FN_CMD_VF_RESET 3 /* TBD PF only: reset VF */ -/** mask value for vf reset */ -#define M_MBOX_FN_CMD_VF_RESET 0x1 -/** mailbox isr vector register */ -#define MBOX_ISR_VEC 0x8 -/** shift value for isr vector */ -#define S_MBOX_ISR_VEC 0 -/** mask value for isr vector */ -#define M_MBOX_ISR_VEC 0x1F -/** face value for isr vector */ -#define V_MBOX_ISR_VEC(x) ((x) & M_MBOX_ISR_VEC) -/** mailbox FN target register */ -#define MBOX_FN_TARGET 0xC -/** shift value for FN target id */ -#define S_MBOX_FN_TARGET_ID 0 -/** mask value for FN target id */ -#define M_MBOX_FN_TARGET_ID 0xFFF -/** face value for FN target id */ -#define V_MBOX_FN_TARGET_ID(x) ((x) & M_MBOX_FN_TARGET_ID) -/** mailbox isr enable register */ -#define MBOX_ISR_EN 0x10 -/** shift value for isr enable */ -#define S_MBOX_ISR_EN 0 -/** mask value for isr enable */ -#define M_MBOX_ISR_EN 0x1 -/** face value for isr enable */ -#define F_MBOX_ISR_EN 0x1 -/** pf acknowledge base */ -#define MBOX_PF_ACK_BASE 0x20 -/** pf acknowledge step */ -#define MBOX_PF_ACK_STEP 4 -/** pf acknowledge count */ -#define MBOX_PF_ACK_COUNT 8 -/** mailbox incoming msg base */ -#define MBOX_IN_MSG_BASE 0x800 -/** mailbox outgoing msg base */ -#define MBOX_OUT_MSG_BASE 0xc00 -/** mailbox msg step */ -#define MBOX_MSG_STEP 4 -/** mailbox register max */ -#define MBOX_MSG_REG_MAX 32 - -/** - * enum mbox_msg_op - mailbox messages opcode - */ -#define MBOX_MSG_OP_RSP_OFFSET 0x80 -enum mbox_msg_op { - /** @MBOX_OP_BYE: vf offline, response not required*/ - MBOX_OP_VF_BYE, - /** @MBOX_OP_HELLO: vf online */ - MBOX_OP_HELLO, - /** @: FMAP programming request */ - MBOX_OP_FMAP, - /** @MBOX_OP_CSR: global CSR registers request */ - MBOX_OP_CSR, - /** @MBOX_OP_QREQ: request queues */ - MBOX_OP_QREQ, - /** @MBOX_OP_QADD: notify of queue addition */ - MBOX_OP_QNOTIFY_ADD, - /** @MBOX_OP_QNOTIFY_DEL: notify of queue deletion */ - MBOX_OP_QNOTIFY_DEL, - /** @MBOX_OP_QACTIVE_CNT: get active q count */ - MBOX_OP_GET_QACTIVE_CNT, - /** @MBOX_OP_QCTXT_WRT: queue context write */ - MBOX_OP_QCTXT_WRT, - /** @MBOX_OP_QCTXT_RD: queue context read */ - MBOX_OP_QCTXT_RD, - /** @MBOX_OP_QCTXT_CLR: queue context clear */ - MBOX_OP_QCTXT_CLR, - /** @MBOX_OP_QCTXT_INV: queue context invalidate */ - MBOX_OP_QCTXT_INV, - /** @MBOX_OP_INTR_CTXT_WRT: interrupt context write */ - MBOX_OP_INTR_CTXT_WRT, - /** @MBOX_OP_INTR_CTXT_RD: interrupt context read */ - MBOX_OP_INTR_CTXT_RD, - /** @MBOX_OP_INTR_CTXT_CLR: interrupt context clear */ - MBOX_OP_INTR_CTXT_CLR, - /** @MBOX_OP_INTR_CTXT_INV: interrupt context invalidate */ - MBOX_OP_INTR_CTXT_INV, - /** @MBOX_OP_RESET_PREPARE: PF to VF message for VF reset*/ - MBOX_OP_RESET_PREPARE, - /** @MBOX_OP_RESET_DONE: PF reset done */ - MBOX_OP_RESET_DONE, - /** @MBOX_OP_REG_LIST_READ: Read the register list */ - MBOX_OP_REG_LIST_READ, - /** @MBOX_OP_PF_BYE: pf offline, response required */ - MBOX_OP_PF_BYE, - /** @MBOX_OP_PF_RESET_VF_BYE: VF reset BYE, response required*/ - MBOX_OP_PF_RESET_VF_BYE, - - /** @MBOX_OP_HELLO_RESP: response to @MBOX_OP_HELLO */ - MBOX_OP_HELLO_RESP = 0x81, - /** @MBOX_OP_FMAP_RESP: response to @MBOX_OP_FMAP */ - MBOX_OP_FMAP_RESP, - /** @MBOX_OP_CSR_RESP: response to @MBOX_OP_CSR */ - MBOX_OP_CSR_RESP, - /** @MBOX_OP_QREQ_RESP: response to @MBOX_OP_QREQ */ - MBOX_OP_QREQ_RESP, - /** @MBOX_OP_QADD: notify of queue addition */ - MBOX_OP_QNOTIFY_ADD_RESP, - /** @MBOX_OP_QNOTIFY_DEL: notify of queue deletion */ - MBOX_OP_QNOTIFY_DEL_RESP, - /** @MBOX_OP_QACTIVE_CNT_RESP: get active q count */ - MBOX_OP_GET_QACTIVE_CNT_RESP, - /** @MBOX_OP_QCTXT_WRT_RESP: response to @MBOX_OP_QCTXT_WRT */ - MBOX_OP_QCTXT_WRT_RESP, - /** @MBOX_OP_QCTXT_RD_RESP: response to @MBOX_OP_QCTXT_RD */ - MBOX_OP_QCTXT_RD_RESP, - /** @MBOX_OP_QCTXT_CLR_RESP: response to @MBOX_OP_QCTXT_CLR */ - MBOX_OP_QCTXT_CLR_RESP, - /** @MBOX_OP_QCTXT_INV_RESP: response to @MBOX_OP_QCTXT_INV */ - MBOX_OP_QCTXT_INV_RESP, - /** @MBOX_OP_INTR_CTXT_WRT_RESP: response to @MBOX_OP_INTR_CTXT_WRT */ - MBOX_OP_INTR_CTXT_WRT_RESP, - /** @MBOX_OP_INTR_CTXT_RD_RESP: response to @MBOX_OP_INTR_CTXT_RD */ - MBOX_OP_INTR_CTXT_RD_RESP, - /** @MBOX_OP_INTR_CTXT_CLR_RESP: response to @MBOX_OP_INTR_CTXT_CLR */ - MBOX_OP_INTR_CTXT_CLR_RESP, - /** @MBOX_OP_INTR_CTXT_INV_RESP: response to @MBOX_OP_INTR_CTXT_INV */ - MBOX_OP_INTR_CTXT_INV_RESP, - /** @MBOX_OP_RESET_PREPARE_RESP: response to @MBOX_OP_RESET_PREPARE */ - MBOX_OP_RESET_PREPARE_RESP, - /** @MBOX_OP_RESET_DONE_RESP: response to @MBOX_OP_PF_VF_RESET */ - MBOX_OP_RESET_DONE_RESP, - /** @MBOX_OP_REG_LIST_READ_RESP: response to @MBOX_OP_REG_LIST_READ */ - MBOX_OP_REG_LIST_READ_RESP, - /** @MBOX_OP_PF_BYE_RESP: response to @MBOX_OP_PF_BYE */ - MBOX_OP_PF_BYE_RESP, - /** @MBOX_OP_PF_RESET_VF_BYE_RESP: - * response to @MBOX_OP_PF_RESET_VF_BYE - */ - MBOX_OP_PF_RESET_VF_BYE_RESP, - /** @MBOX_OP_MAX: total mbox opcodes*/ - MBOX_OP_MAX -}; - -/** - * struct mbox_msg_hdr - mailbox message header - */ -struct mbox_msg_hdr { - /** @op: opcode */ - uint8_t op; - /** @status: execution status */ - char status; - /** @src_func_id: src function */ - uint16_t src_func_id; - /** @dst_func_id: dst function */ - uint16_t dst_func_id; -}; - -/** - * struct mbox_msg_fmap - FMAP programming command - */ -struct mbox_msg_hello { - /** @hdr: mailbox message header */ - struct mbox_msg_hdr hdr; - /** @qbase: start queue number in the queue range */ - uint32_t qbase; - /** @qmax: max queue number in the queue range(0-2k) */ - uint32_t qmax; - /** @dev_cap: device capability */ - struct qdma_dev_attributes dev_cap; - /** @dma_device_index: dma_device_index */ - uint32_t dma_device_index; -}; - -/** - * struct mbox_msg_active_qcnt - get active queue count command - */ -struct mbox_msg_active_qcnt { - /** @hdr: mailbox message header */ - struct mbox_msg_hdr hdr; - /** @h2c_queues: number of h2c queues */ - uint32_t h2c_queues; - /** @c2h_queues: number of c2h queues */ - uint32_t c2h_queues; - /** @cmpt_queues: number of cmpt queues */ - uint32_t cmpt_queues; -}; - -/** - * struct mbox_msg_fmap - FMAP programming command - */ -struct mbox_msg_fmap { - /** @hdr: mailbox message header */ - struct mbox_msg_hdr hdr; - /** @qbase: start queue number in the queue range */ - int qbase; - /** @qmax: max queue number in the queue range(0-2k) */ - uint32_t qmax; -}; - -/** - * struct mbox_msg_csr - mailbox csr reading message - */ -struct mbox_msg_csr { - /** @hdr - mailbox message header */ - struct mbox_msg_hdr hdr; - /** @csr_info: csr info data strucutre */ - struct qdma_csr_info csr_info; -}; - -/** - * struct mbox_msg_q_nitfy - queue add/del notify message - */ -struct mbox_msg_q_nitfy { - /** @hdr - mailbox message header */ - struct mbox_msg_hdr hdr; - /** @qid_hw: queue ID */ - uint16_t qid_hw; - /** @q_type: type of q */ - enum qdma_dev_q_type q_type; -}; - -/** - * @struct - mbox_msg_qctxt - * @brief queue context mailbox message header - */ -struct mbox_msg_qctxt { - /** @hdr: mailbox message header*/ - struct mbox_msg_hdr hdr; - /** @qid_hw: queue ID */ - uint16_t qid_hw; - /** @st: streaming mode */ - uint8_t st:1; - /** @c2h: c2h direction */ - uint8_t c2h:1; - /** @cmpt_ctxt_type: completion context type */ - enum mbox_cmpt_ctxt_type cmpt_ctxt_type:2; - /** @rsvd: reserved */ - uint8_t rsvd:4; - /** union compiled_message - complete hw configuration */ - union { - /** @descq_conf: mailbox message for queue context write*/ - struct mbox_descq_conf descq_conf; - /** @descq_ctxt: mailbox message for queue context read*/ - struct qdma_descq_context descq_ctxt; - }; -}; - -/** - * @struct - mbox_intr_ctxt - * @brief queue context mailbox message header - */ -struct mbox_intr_ctxt { - /** @hdr: mailbox message header*/ - struct mbox_msg_hdr hdr; - /** interrupt context mailbox message */ - struct mbox_msg_intr_ctxt ctxt; -}; - -/** - * @struct - mbox_read_reg_list - * @brief read register mailbox message header - */ -struct mbox_read_reg_list { - /** @hdr: mailbox message header*/ - struct mbox_msg_hdr hdr; - /** @group_num: reg group to read */ - uint16_t group_num; - /** @num_regs: number of registers to read */ - uint16_t num_regs; - /** @reg_list: register list */ - struct qdma_reg_data reg_list[QDMA_MAX_REGISTER_DUMP]; -}; - -union qdma_mbox_txrx { - /** mailbox message header*/ - struct mbox_msg_hdr hdr; - /** hello mailbox message */ - struct mbox_msg_hello hello; - /** fmap mailbox message */ - struct mbox_msg_fmap fmap; - /** interrupt context mailbox message */ - struct mbox_intr_ctxt intr_ctxt; - /** queue context mailbox message*/ - struct mbox_msg_qctxt qctxt; - /** global csr mailbox message */ - struct mbox_msg_csr csr; - /** acive q count */ - struct mbox_msg_active_qcnt qcnt; - /** q add/del notify message */ - struct mbox_msg_q_nitfy q_notify; - /** reg list mailbox message */ - struct mbox_read_reg_list reg_read_list; - /** buffer to hold raw data between pf and vf */ - uint32_t raw[MBOX_MSG_REG_MAX]; -}; - - -static inline uint32_t get_mbox_offset(void *dev_hndl, uint8_t is_vf) -{ - uint32_t mbox_base; - struct qdma_hw_access *hw = NULL; - - qdma_get_hw_access(dev_hndl, &hw); - mbox_base = (is_vf) ? - hw->mbox_base_vf : hw->mbox_base_pf; - - return mbox_base; -} - -static inline void mbox_pf_hw_clear_func_ack(void *dev_hndl, uint16_t func_id) -{ - int idx = func_id / 32; /* bitmask, uint32_t reg */ - int bit = func_id % 32; - uint32_t mbox_base = get_mbox_offset(dev_hndl, 0); - - /* clear the function's ack status */ - qdma_reg_write(dev_hndl, - mbox_base + MBOX_PF_ACK_BASE + idx * MBOX_PF_ACK_STEP, - (1 << bit)); -} - -static void qdma_mbox_memcpy(void *to, void *from, uint8_t size) -{ - uint8_t i; - uint8_t *_to = (uint8_t *)to; - uint8_t *_from = (uint8_t *)from; - - for (i = 0; i < size; i++) - _to[i] = _from[i]; -} - -static void qdma_mbox_memset(void *to, uint8_t val, uint8_t size) -{ - uint8_t i; - uint8_t *_to = (uint8_t *)to; - - for (i = 0; i < size; i++) - _to[i] = val; -} - -static int get_ring_idx(void *dev_hndl, uint16_t ring_sz, uint16_t *rng_idx) -{ - uint32_t rng_sz[QDMA_GLOBAL_CSR_ARRAY_SZ] = { 0 }; - int i, rv; - struct qdma_hw_access *hw = NULL; - - qdma_get_hw_access(dev_hndl, &hw); - rv = hw->qdma_global_csr_conf(dev_hndl, 0, - QDMA_GLOBAL_CSR_ARRAY_SZ, rng_sz, - QDMA_CSR_RING_SZ, QDMA_HW_ACCESS_READ); - - if (rv) - return rv; - for (i = 0; i < QDMA_GLOBAL_CSR_ARRAY_SZ; i++) { - if (ring_sz == (rng_sz[i] - 1)) { - *rng_idx = i; - return QDMA_SUCCESS; - } - } - - qdma_log_error("%s: Ring size not found, err:%d\n", - __func__, -QDMA_ERR_MBOX_INV_RINGSZ); - return -QDMA_ERR_MBOX_INV_RINGSZ; -} - -static int get_buf_idx(void *dev_hndl, uint16_t buf_sz, uint16_t *buf_idx) -{ - uint32_t c2h_buf_sz[QDMA_GLOBAL_CSR_ARRAY_SZ] = { 0 }; - int i, rv; - struct qdma_hw_access *hw = NULL; - - qdma_get_hw_access(dev_hndl, &hw); - - rv = hw->qdma_global_csr_conf(dev_hndl, 0, - QDMA_GLOBAL_CSR_ARRAY_SZ, c2h_buf_sz, - QDMA_CSR_BUF_SZ, QDMA_HW_ACCESS_READ); - if (rv) - return rv; - for (i = 0; i < QDMA_GLOBAL_CSR_ARRAY_SZ; i++) { - if (c2h_buf_sz[i] == buf_sz) { - *buf_idx = i; - return QDMA_SUCCESS; - } - } - - qdma_log_error("%s: Buf index not found, err:%d\n", - __func__, -QDMA_ERR_MBOX_INV_BUFSZ); - return -QDMA_ERR_MBOX_INV_BUFSZ; -} - -static int get_cntr_idx(void *dev_hndl, uint8_t cntr_val, uint8_t *cntr_idx) -{ - uint32_t cntr_th[QDMA_GLOBAL_CSR_ARRAY_SZ] = { 0 }; - int i, rv; - struct qdma_hw_access *hw = NULL; - - qdma_get_hw_access(dev_hndl, &hw); - - rv = hw->qdma_global_csr_conf(dev_hndl, 0, - QDMA_GLOBAL_CSR_ARRAY_SZ, cntr_th, - QDMA_CSR_CNT_TH, QDMA_HW_ACCESS_READ); - - if (rv) - return rv; - for (i = 0; i < QDMA_GLOBAL_CSR_ARRAY_SZ; i++) { - if (cntr_th[i] == cntr_val) { - *cntr_idx = i; - return QDMA_SUCCESS; - } - } - - qdma_log_error("%s: Counter val not found, err:%d\n", - __func__, -QDMA_ERR_MBOX_INV_CNTR_TH); - return -QDMA_ERR_MBOX_INV_CNTR_TH; -} - -static int get_tmr_idx(void *dev_hndl, uint8_t tmr_val, uint8_t *tmr_idx) -{ - uint32_t tmr_th[QDMA_GLOBAL_CSR_ARRAY_SZ] = { 0 }; - int i, rv; - struct qdma_hw_access *hw = NULL; - - qdma_get_hw_access(dev_hndl, &hw); - - rv = hw->qdma_global_csr_conf(dev_hndl, 0, - QDMA_GLOBAL_CSR_ARRAY_SZ, tmr_th, - QDMA_CSR_TIMER_CNT, QDMA_HW_ACCESS_READ); - if (rv) - return rv; - for (i = 0; i < QDMA_GLOBAL_CSR_ARRAY_SZ; i++) { - if (tmr_th[i] == tmr_val) { - *tmr_idx = i; - return QDMA_SUCCESS; - } - } - - qdma_log_error("%s: Timer val not found, err:%d\n", - __func__, -QDMA_ERR_MBOX_INV_TMR_TH); - return -QDMA_ERR_MBOX_INV_TMR_TH; -} - -static int mbox_compose_sw_context(void *dev_hndl, - struct mbox_msg_qctxt *qctxt, - struct qdma_descq_sw_ctxt *sw_ctxt) -{ - uint16_t rng_idx = 0; - int rv = QDMA_SUCCESS; - - if (!qctxt || !sw_ctxt) { - qdma_log_error("%s: qctxt=%p sw_ctxt=%p, err:%d\n", - __func__, - qctxt, sw_ctxt, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - rv = get_ring_idx(dev_hndl, qctxt->descq_conf.ringsz, &rng_idx); - if (rv < 0) { - qdma_log_error("%s: failed to get ring index, err:%d\n", - __func__, rv); - return rv; - } - /* compose sw context */ - sw_ctxt->vec = qctxt->descq_conf.intr_id; - sw_ctxt->intr_aggr = qctxt->descq_conf.intr_aggr; - - sw_ctxt->ring_bs_addr = qctxt->descq_conf.ring_bs_addr; - sw_ctxt->wbi_chk = qctxt->descq_conf.wbi_chk; - sw_ctxt->wbi_intvl_en = qctxt->descq_conf.wbi_intvl_en; - sw_ctxt->rngsz_idx = rng_idx; - sw_ctxt->bypass = qctxt->descq_conf.en_bypass; - sw_ctxt->wbk_en = qctxt->descq_conf.wbk_en; - sw_ctxt->irq_en = qctxt->descq_conf.irq_en; - sw_ctxt->is_mm = ~qctxt->st; - sw_ctxt->mm_chn = 0; - sw_ctxt->qen = 1; - sw_ctxt->frcd_en = qctxt->descq_conf.forced_en; - - sw_ctxt->desc_sz = qctxt->descq_conf.desc_sz; - - /* pidx = 0; irq_ack = 0 */ - sw_ctxt->fnc_id = qctxt->descq_conf.func_id; - sw_ctxt->irq_arm = qctxt->descq_conf.irq_arm; - - if (qctxt->st && qctxt->c2h) { - sw_ctxt->irq_en = 0; - sw_ctxt->irq_arm = 0; - sw_ctxt->wbk_en = 0; - sw_ctxt->wbi_chk = 0; - } - - return QDMA_SUCCESS; -} - -static int mbox_compose_prefetch_context(void *dev_hndl, - struct mbox_msg_qctxt *qctxt, - struct qdma_descq_prefetch_ctxt *pfetch_ctxt) -{ - uint16_t buf_idx = 0; - int rv = QDMA_SUCCESS; - - if (!qctxt || !pfetch_ctxt) { - qdma_log_error("%s: qctxt=%p pfetch_ctxt=%p, err:%d\n", - __func__, - qctxt, - pfetch_ctxt, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - rv = get_buf_idx(dev_hndl, qctxt->descq_conf.bufsz, &buf_idx); - if (rv < 0) { - qdma_log_error("%s: failed to get buf index, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - return rv; - } - /* prefetch context */ - pfetch_ctxt->valid = 1; - pfetch_ctxt->bypass = qctxt->descq_conf.en_bypass_prefetch; - pfetch_ctxt->bufsz_idx = buf_idx; - pfetch_ctxt->pfch_en = qctxt->descq_conf.pfch_en; - - return QDMA_SUCCESS; -} - - -static int mbox_compose_cmpt_context(void *dev_hndl, - struct mbox_msg_qctxt *qctxt, - struct qdma_descq_cmpt_ctxt *cmpt_ctxt) -{ - uint16_t rng_idx = 0; - uint8_t cntr_idx = 0, tmr_idx = 0; - int rv = QDMA_SUCCESS; - - if (!qctxt || !cmpt_ctxt) { - qdma_log_error("%s: qctxt=%p cmpt_ctxt=%p, err:%d\n", - __func__, qctxt, cmpt_ctxt, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - rv = get_cntr_idx(dev_hndl, qctxt->descq_conf.cnt_thres, &cntr_idx); - if (rv < 0) - return rv; - rv = get_tmr_idx(dev_hndl, qctxt->descq_conf.timer_thres, &tmr_idx); - if (rv < 0) - return rv; - rv = get_ring_idx(dev_hndl, qctxt->descq_conf.cmpt_ringsz, &rng_idx); - if (rv < 0) - return rv; - /* writeback context */ - - cmpt_ctxt->bs_addr = qctxt->descq_conf.cmpt_ring_bs_addr; - cmpt_ctxt->en_stat_desc = qctxt->descq_conf.cmpl_stat_en; - cmpt_ctxt->en_int = qctxt->descq_conf.cmpt_int_en; - cmpt_ctxt->trig_mode = qctxt->descq_conf.triggermode; - cmpt_ctxt->fnc_id = qctxt->descq_conf.func_id; - cmpt_ctxt->timer_idx = tmr_idx; - cmpt_ctxt->counter_idx = cntr_idx; - cmpt_ctxt->color = 1; - cmpt_ctxt->ringsz_idx = rng_idx; - - cmpt_ctxt->desc_sz = qctxt->descq_conf.cmpt_desc_sz; - - cmpt_ctxt->valid = 1; - - cmpt_ctxt->ovf_chk_dis = qctxt->descq_conf.dis_overflow_check; - cmpt_ctxt->vec = qctxt->descq_conf.intr_id; - cmpt_ctxt->int_aggr = qctxt->descq_conf.intr_aggr; - - return QDMA_SUCCESS; -} - -static int mbox_clear_queue_contexts(void *dev_hndl, uint8_t dma_device_index, - uint16_t func_id, uint16_t qid_hw, uint8_t st, - uint8_t c2h, - enum mbox_cmpt_ctxt_type cmpt_ctxt_type) -{ - int rv; - int qbase; - uint32_t qmax; - enum qdma_dev_q_range q_range; - struct qdma_hw_access *hw = NULL; - - qdma_get_hw_access(dev_hndl, &hw); - - if (cmpt_ctxt_type == QDMA_MBOX_CMPT_CTXT_ONLY) { - rv = hw->qdma_cmpt_ctx_conf(dev_hndl, qid_hw, - NULL, QDMA_HW_ACCESS_CLEAR); - if (rv < 0) { - qdma_log_error("%s: clear cmpt ctxt, err:%d\n", - __func__, rv); - return rv; - } - } else { - rv = qdma_dev_qinfo_get(dma_device_index, - func_id, &qbase, &qmax); - if (rv < 0) { - qdma_log_error("%s: failed to get qinfo, err:%d\n", - __func__, rv); - return rv; - } - - q_range = qdma_dev_is_queue_in_range(dma_device_index, - func_id, qid_hw); - if (q_range != QDMA_DEV_Q_IN_RANGE) { - qdma_log_error("%s: q_range invalid, err:%d\n", - __func__, rv); - return rv; - } - - rv = hw->qdma_sw_ctx_conf(dev_hndl, c2h, qid_hw, - NULL, QDMA_HW_ACCESS_CLEAR); - if (rv < 0) { - qdma_log_error("%s: clear sw_ctxt, err:%d\n", - __func__, rv); - return rv; - } - - rv = hw->qdma_hw_ctx_conf(dev_hndl, c2h, qid_hw, NULL, - QDMA_HW_ACCESS_CLEAR); - if (rv < 0) { - qdma_log_error("%s: clear hw_ctxt, err:%d\n", - __func__, rv); - return rv; - } - - rv = hw->qdma_credit_ctx_conf(dev_hndl, c2h, qid_hw, NULL, - QDMA_HW_ACCESS_CLEAR); - if (rv < 0) { - qdma_log_error("%s: clear cr_ctxt, err:%d\n", - __func__, rv); - return rv; - } - - if (st && c2h) { - rv = hw->qdma_pfetch_ctx_conf(dev_hndl, qid_hw, - NULL, - QDMA_HW_ACCESS_CLEAR); - if (rv < 0) { - qdma_log_error("%s:clear pfetch ctxt, err:%d\n", - __func__, rv); - return rv; - } - } - - if ((cmpt_ctxt_type == QDMA_MBOX_CMPT_WITH_MM) || - (cmpt_ctxt_type == QDMA_MBOX_CMPT_WITH_ST)) { - rv = hw->qdma_cmpt_ctx_conf(dev_hndl, qid_hw, - NULL, - QDMA_HW_ACCESS_CLEAR); - if (rv < 0) { - qdma_log_error("%s: clear cmpt ctxt, err:%d\n", - __func__, rv); - return rv; - } - } - } - - return QDMA_SUCCESS; -} - -static int mbox_invalidate_queue_contexts(void *dev_hndl, - uint8_t dma_device_index, uint16_t func_id, - uint16_t qid_hw, uint8_t st, - uint8_t c2h, enum mbox_cmpt_ctxt_type cmpt_ctxt_type) -{ - int rv; - int qbase; - uint32_t qmax; - enum qdma_dev_q_range q_range; - struct qdma_hw_access *hw = NULL; - - qdma_get_hw_access(dev_hndl, &hw); - - if (cmpt_ctxt_type == QDMA_MBOX_CMPT_CTXT_ONLY) { - rv = hw->qdma_cmpt_ctx_conf(dev_hndl, qid_hw, NULL, - QDMA_HW_ACCESS_INVALIDATE); - if (rv < 0) { - qdma_log_error("%s: inv cmpt ctxt, err:%d\n", - __func__, rv); - return rv; - } - } else { - rv = qdma_dev_qinfo_get(dma_device_index, func_id, - &qbase, &qmax); - if (rv < 0) { - qdma_log_error("%s: failed to get qinfo, err:%d\n", - __func__, rv); - return rv; - } - - q_range = qdma_dev_is_queue_in_range(dma_device_index, - func_id, qid_hw); - if (q_range != QDMA_DEV_Q_IN_RANGE) { - qdma_log_error("%s: Invalid qrange, err:%d\n", - __func__, rv); - return rv; - } - - rv = hw->qdma_sw_ctx_conf(dev_hndl, c2h, qid_hw, - NULL, QDMA_HW_ACCESS_INVALIDATE); - if (rv < 0) { - qdma_log_error("%s: inv sw ctxt, err:%d\n", - __func__, rv); - return rv; - } - - rv = hw->qdma_hw_ctx_conf(dev_hndl, c2h, qid_hw, NULL, - QDMA_HW_ACCESS_INVALIDATE); - if (rv < 0) { - qdma_log_error("%s: clear hw_ctxt, err:%d\n", - __func__, rv); - return rv; - } - - rv = hw->qdma_credit_ctx_conf(dev_hndl, c2h, qid_hw, NULL, - QDMA_HW_ACCESS_INVALIDATE); - if (rv < 0) { - qdma_log_error("%s: clear cr_ctxt, err:%d\n", - __func__, rv); - return rv; - } - - if (st && c2h) { - rv = hw->qdma_pfetch_ctx_conf(dev_hndl, qid_hw, - NULL, - QDMA_HW_ACCESS_INVALIDATE); - if (rv < 0) { - qdma_log_error("%s: inv pfetch ctxt, err:%d\n", - __func__, rv); - return rv; - } - } - - if ((cmpt_ctxt_type == QDMA_MBOX_CMPT_WITH_MM) || - (cmpt_ctxt_type == QDMA_MBOX_CMPT_WITH_ST)) { - rv = hw->qdma_cmpt_ctx_conf(dev_hndl, qid_hw, - NULL, - QDMA_HW_ACCESS_INVALIDATE); - if (rv < 0) { - qdma_log_error("%s: inv cmpt ctxt, err:%d\n", - __func__, rv); - return rv; - } - } - } - - return QDMA_SUCCESS; -} - -static int mbox_write_queue_contexts(void *dev_hndl, uint8_t dma_device_index, - struct mbox_msg_qctxt *qctxt) -{ - int rv; - int qbase; - uint32_t qmax; - enum qdma_dev_q_range q_range; - struct qdma_descq_context descq_ctxt; - uint16_t qid_hw = qctxt->qid_hw; - struct qdma_hw_access *hw = NULL; - - qdma_get_hw_access(dev_hndl, &hw); - - rv = qdma_dev_qinfo_get(dma_device_index, qctxt->descq_conf.func_id, - &qbase, &qmax); - if (rv < 0) - return rv; - - q_range = qdma_dev_is_queue_in_range(dma_device_index, - qctxt->descq_conf.func_id, - qctxt->qid_hw); - if (q_range != QDMA_DEV_Q_IN_RANGE) { - qdma_log_error("%s: Invalid qrange, err:%d\n", - __func__, rv); - return rv; - } - - qdma_mbox_memset(&descq_ctxt, 0, sizeof(struct qdma_descq_context)); - - if (qctxt->cmpt_ctxt_type == QDMA_MBOX_CMPT_CTXT_ONLY) { - rv = mbox_compose_cmpt_context(dev_hndl, qctxt, - &descq_ctxt.cmpt_ctxt); - if (rv < 0) - return rv; - - rv = hw->qdma_cmpt_ctx_conf(dev_hndl, qid_hw, - NULL, QDMA_HW_ACCESS_CLEAR); - if (rv < 0) { - qdma_log_error("%s: clear cmpt ctxt, err:%d\n", - __func__, rv); - return rv; - } - - rv = hw->qdma_cmpt_ctx_conf(dev_hndl, qid_hw, - &descq_ctxt.cmpt_ctxt, QDMA_HW_ACCESS_WRITE); - if (rv < 0) { - qdma_log_error("%s: write cmpt ctxt, err:%d\n", - __func__, rv); - return rv; - } - - } else { - rv = mbox_compose_sw_context(dev_hndl, qctxt, - &descq_ctxt.sw_ctxt); - if (rv < 0) - return rv; - - if (qctxt->st && qctxt->c2h) { - rv = mbox_compose_prefetch_context(dev_hndl, qctxt, - &descq_ctxt.pfetch_ctxt); - if (rv < 0) - return rv; - } - - if ((qctxt->cmpt_ctxt_type == QDMA_MBOX_CMPT_WITH_MM) || - (qctxt->cmpt_ctxt_type == QDMA_MBOX_CMPT_WITH_ST)) { - rv = mbox_compose_cmpt_context(dev_hndl, qctxt, - &descq_ctxt.cmpt_ctxt); - if (rv < 0) - return rv; - } - - rv = mbox_clear_queue_contexts(dev_hndl, dma_device_index, - qctxt->descq_conf.func_id, - qctxt->qid_hw, - qctxt->st, - qctxt->c2h, - qctxt->cmpt_ctxt_type); - if (rv < 0) - return rv; - rv = hw->qdma_sw_ctx_conf(dev_hndl, qctxt->c2h, qid_hw, - &descq_ctxt.sw_ctxt, - QDMA_HW_ACCESS_WRITE); - if (rv < 0) { - qdma_log_error("%s: write sw ctxt, err:%d\n", - __func__, rv); - return rv; - } - - if (qctxt->st && qctxt->c2h) { - rv = hw->qdma_pfetch_ctx_conf(dev_hndl, qid_hw, - &descq_ctxt.pfetch_ctxt, - QDMA_HW_ACCESS_WRITE); - if (rv < 0) { - qdma_log_error("%s:write pfetch ctxt, err:%d\n", - __func__, rv); - return rv; - } - } - - if ((qctxt->cmpt_ctxt_type == QDMA_MBOX_CMPT_WITH_MM) || - (qctxt->cmpt_ctxt_type == QDMA_MBOX_CMPT_WITH_ST)) { - rv = hw->qdma_cmpt_ctx_conf(dev_hndl, qid_hw, - &descq_ctxt.cmpt_ctxt, - QDMA_HW_ACCESS_WRITE); - if (rv < 0) { - qdma_log_error("%s: write cmpt ctxt, err:%d\n", - __func__, rv); - return rv; - } - } - } - return QDMA_SUCCESS; -} - -static int mbox_read_queue_contexts(void *dev_hndl, uint16_t func_id, - uint16_t qid_hw, uint8_t st, uint8_t c2h, - enum mbox_cmpt_ctxt_type cmpt_ctxt_type, - struct qdma_descq_context *ctxt) -{ - int rv; - struct qdma_hw_access *hw = NULL; - - qdma_get_hw_access(dev_hndl, &hw); - - rv = hw->qdma_sw_ctx_conf(dev_hndl, c2h, qid_hw, &ctxt->sw_ctxt, - QDMA_HW_ACCESS_READ); - if (rv < 0) { - qdma_log_error("%s: read sw ctxt, err:%d\n", - __func__, rv); - return rv; - } - - rv = hw->qdma_hw_ctx_conf(dev_hndl, c2h, qid_hw, &ctxt->hw_ctxt, - QDMA_HW_ACCESS_READ); - if (rv < 0) { - qdma_log_error("%s: read hw ctxt, err:%d\n", - __func__, rv); - return rv; - } - - rv = hw->qdma_credit_ctx_conf(dev_hndl, c2h, qid_hw, &ctxt->cr_ctxt, - QDMA_HW_ACCESS_READ); - if (rv < 0) { - qdma_log_error("%s: read credit ctxt, err:%d\n", - __func__, rv); - return rv; - } - - rv = hw->qdma_fmap_conf(dev_hndl, func_id, &ctxt->fmap, - QDMA_HW_ACCESS_READ); - if (rv < 0) { - qdma_log_error("%s: read fmap ctxt, err:%d\n", - __func__, rv); - return rv; - } - - if (st && c2h) { - rv = hw->qdma_pfetch_ctx_conf(dev_hndl, - qid_hw, &ctxt->pfetch_ctxt, - QDMA_HW_ACCESS_READ); - if (rv < 0) { - qdma_log_error("%s: read pfetch ctxt, err:%d\n", - __func__, rv); - return rv; - } - } - - if ((cmpt_ctxt_type == QDMA_MBOX_CMPT_WITH_MM) || - (cmpt_ctxt_type == QDMA_MBOX_CMPT_WITH_ST)) { - rv = hw->qdma_cmpt_ctx_conf(dev_hndl, - qid_hw, &ctxt->cmpt_ctxt, - QDMA_HW_ACCESS_READ); - if (rv < 0) { - qdma_log_error("%s: read cmpt ctxt, err:%d\n", - __func__, rv); - return rv; - } - } - - return QDMA_SUCCESS; -} - -int qdma_mbox_pf_rcv_msg_handler(void *dev_hndl, uint8_t dma_device_index, - uint16_t func_id, uint32_t *rcv_msg, - uint32_t *resp_msg) -{ - union qdma_mbox_txrx *rcv = (union qdma_mbox_txrx *)rcv_msg; - union qdma_mbox_txrx *resp = (union qdma_mbox_txrx *)resp_msg; - struct mbox_msg_hdr *hdr = &rcv->hdr; - struct qdma_hw_access *hw = NULL; - int rv = QDMA_SUCCESS; - int ret = 0; - - if (!rcv) { - qdma_log_error("%s: rcv_msg=%p failure:%d\n", - __func__, rcv, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - qdma_get_hw_access(dev_hndl, &hw); - - switch (rcv->hdr.op) { - case MBOX_OP_VF_BYE: - { - struct qdma_fmap_cfg fmap; - - fmap.qbase = 0; - fmap.qmax = 0; - rv = hw->qdma_fmap_conf(dev_hndl, hdr->src_func_id, &fmap, - QDMA_HW_ACCESS_WRITE); - - qdma_dev_entry_destroy(dma_device_index, hdr->src_func_id); - - ret = QDMA_MBOX_VF_OFFLINE; - } - break; - case MBOX_OP_PF_RESET_VF_BYE: - { - struct qdma_fmap_cfg fmap; - - fmap.qbase = 0; - fmap.qmax = 0; - rv = hw->qdma_fmap_conf(dev_hndl, hdr->src_func_id, &fmap, - QDMA_HW_ACCESS_WRITE); - - qdma_dev_entry_destroy(dma_device_index, hdr->src_func_id); - - ret = QDMA_MBOX_VF_RESET_BYE; - } - break; - case MBOX_OP_HELLO: - { - struct mbox_msg_fmap *fmap = &rcv->fmap; - struct qdma_fmap_cfg fmap_cfg; - struct mbox_msg_hello *rsp_hello = &resp->hello; - - rv = qdma_dev_qinfo_get(dma_device_index, hdr->src_func_id, - &fmap->qbase, &fmap->qmax); - if (rv < 0) - rv = qdma_dev_entry_create(dma_device_index, - hdr->src_func_id); - - if (!rv) { - rsp_hello->qbase = fmap->qbase; - rsp_hello->qmax = fmap->qmax; - rsp_hello->dma_device_index = dma_device_index; - hw->qdma_get_device_attributes(dev_hndl, - &rsp_hello->dev_cap); - } - qdma_mbox_memset(&fmap_cfg, 0, - sizeof(struct qdma_fmap_cfg)); - hw->qdma_fmap_conf(dev_hndl, hdr->src_func_id, &fmap_cfg, - QDMA_HW_ACCESS_WRITE); - - ret = QDMA_MBOX_VF_ONLINE; - } - break; - case MBOX_OP_FMAP: - { - struct mbox_msg_fmap *fmap = &rcv->fmap; - struct qdma_fmap_cfg fmap_cfg; - - fmap_cfg.qbase = fmap->qbase; - fmap_cfg.qmax = fmap->qmax; - - rv = hw->qdma_fmap_conf(dev_hndl, hdr->src_func_id, - &fmap_cfg, QDMA_HW_ACCESS_WRITE); - if (rv < 0) { - qdma_log_error("%s: failed to write fmap, err:%d\n", - __func__, rv); - return rv; - } - } - break; - case MBOX_OP_CSR: - { - struct mbox_msg_csr *rsp_csr = &resp->csr; - struct qdma_dev_attributes dev_cap; - - uint32_t ringsz[QDMA_GLOBAL_CSR_ARRAY_SZ] = {0}; - uint32_t bufsz[QDMA_GLOBAL_CSR_ARRAY_SZ] = {0}; - uint32_t tmr_th[QDMA_GLOBAL_CSR_ARRAY_SZ] = {0}; - uint32_t cntr_th[QDMA_GLOBAL_CSR_ARRAY_SZ] = {0}; - int i; - - rv = hw->qdma_global_csr_conf(dev_hndl, 0, - QDMA_GLOBAL_CSR_ARRAY_SZ, ringsz, - QDMA_CSR_RING_SZ, QDMA_HW_ACCESS_READ); - if (rv < 0) - goto exit_func; - - hw->qdma_get_device_attributes(dev_hndl, &dev_cap); - - if (dev_cap.st_en) { - rv = hw->qdma_global_csr_conf(dev_hndl, 0, - QDMA_GLOBAL_CSR_ARRAY_SZ, bufsz, - QDMA_CSR_BUF_SZ, QDMA_HW_ACCESS_READ); - if (rv < 0 && - (rv != -QDMA_ERR_HWACC_FEATURE_NOT_SUPPORTED)) - goto exit_func; - } - - if (dev_cap.st_en || dev_cap.mm_cmpt_en) { - rv = hw->qdma_global_csr_conf(dev_hndl, 0, - QDMA_GLOBAL_CSR_ARRAY_SZ, tmr_th, - QDMA_CSR_TIMER_CNT, QDMA_HW_ACCESS_READ); - if (rv < 0 && - (rv != -QDMA_ERR_HWACC_FEATURE_NOT_SUPPORTED)) - goto exit_func; - - rv = hw->qdma_global_csr_conf(dev_hndl, 0, - QDMA_GLOBAL_CSR_ARRAY_SZ, cntr_th, - QDMA_CSR_CNT_TH, QDMA_HW_ACCESS_READ); - if (rv < 0 && - (rv != -QDMA_ERR_HWACC_FEATURE_NOT_SUPPORTED)) - goto exit_func; - } - - for (i = 0; i < QDMA_GLOBAL_CSR_ARRAY_SZ; i++) { - rsp_csr->csr_info.ringsz[i] = ringsz[i] & - 0xFFFF; - if (!rv) { - rsp_csr->csr_info.bufsz[i] = bufsz[i] & 0xFFFF; - rsp_csr->csr_info.timer_cnt[i] = tmr_th[i] & - 0xFF; - rsp_csr->csr_info.cnt_thres[i] = cntr_th[i] & - 0xFF; - } - } - - if (rv == -QDMA_ERR_HWACC_FEATURE_NOT_SUPPORTED) - rv = QDMA_SUCCESS; - } - break; - case MBOX_OP_QREQ: - { - struct mbox_msg_fmap *fmap = &rcv->fmap; - - rv = qdma_dev_update(dma_device_index, - hdr->src_func_id, - fmap->qmax, &fmap->qbase); - if (rv == 0) - rv = qdma_dev_qinfo_get(dma_device_index, - hdr->src_func_id, - &resp->fmap.qbase, - &resp->fmap.qmax); - if (rv < 0) - rv = -QDMA_ERR_MBOX_NUM_QUEUES; - else { - struct qdma_fmap_cfg fmap_cfg; - - qdma_mbox_memset(&fmap_cfg, 0, - sizeof(struct qdma_fmap_cfg)); - hw->qdma_fmap_conf(dev_hndl, hdr->src_func_id, - &fmap_cfg, QDMA_HW_ACCESS_WRITE); - } - } - break; - case MBOX_OP_QNOTIFY_ADD: - { - struct mbox_msg_q_nitfy *q_notify = &rcv->q_notify; - enum qdma_dev_q_range q_range; - - q_range = qdma_dev_is_queue_in_range( - dma_device_index, - q_notify->hdr.src_func_id, - q_notify->qid_hw); - if (q_range != QDMA_DEV_Q_IN_RANGE) - rv = -QDMA_ERR_MBOX_INV_QID; - else - rv = qdma_dev_increment_active_queue( - dma_device_index, - q_notify->hdr.src_func_id, - q_notify->q_type); - } - break; - case MBOX_OP_QNOTIFY_DEL: - { - struct mbox_msg_q_nitfy *q_notify = &rcv->q_notify; - enum qdma_dev_q_range q_range; - - q_range = qdma_dev_is_queue_in_range( - dma_device_index, - q_notify->hdr.src_func_id, - q_notify->qid_hw); - if (q_range != QDMA_DEV_Q_IN_RANGE) - rv = -QDMA_ERR_MBOX_INV_QID; - else - rv = qdma_dev_decrement_active_queue( - dma_device_index, - q_notify->hdr.src_func_id, - q_notify->q_type); - } - break; - case MBOX_OP_GET_QACTIVE_CNT: - { - rv = qdma_get_device_active_queue_count( - dma_device_index, - rcv->hdr.src_func_id, - QDMA_DEV_Q_TYPE_H2C); - - resp->qcnt.h2c_queues = rv; - - rv = qdma_get_device_active_queue_count( - dma_device_index, - rcv->hdr.src_func_id, - QDMA_DEV_Q_TYPE_C2H); - - resp->qcnt.c2h_queues = rv; - - rv = qdma_get_device_active_queue_count( - dma_device_index, - rcv->hdr.src_func_id, - QDMA_DEV_Q_TYPE_CMPT); - - resp->qcnt.cmpt_queues = rv; - } - break; - case MBOX_OP_INTR_CTXT_WRT: - { - struct mbox_msg_intr_ctxt *ictxt = &rcv->intr_ctxt.ctxt; - struct qdma_indirect_intr_ctxt *ctxt; - uint8_t i; - uint32_t ring_index; - - for (i = 0; i < ictxt->num_rings; i++) { - ring_index = ictxt->ring_index_list[i]; - - ctxt = &ictxt->ictxt[i]; - rv = hw->qdma_indirect_intr_ctx_conf(dev_hndl, - ring_index, - NULL, - QDMA_HW_ACCESS_CLEAR); - if (rv < 0) - resp->hdr.status = rv; - rv = hw->qdma_indirect_intr_ctx_conf(dev_hndl, - ring_index, ctxt, - QDMA_HW_ACCESS_WRITE); - if (rv < 0) - resp->hdr.status = rv; - } - } - break; - case MBOX_OP_INTR_CTXT_RD: - { - struct mbox_msg_intr_ctxt *rcv_ictxt = &rcv->intr_ctxt.ctxt; - struct mbox_msg_intr_ctxt *rsp_ictxt = &resp->intr_ctxt.ctxt; - uint8_t i; - uint32_t ring_index; - - for (i = 0; i < rcv_ictxt->num_rings; i++) { - ring_index = rcv_ictxt->ring_index_list[i]; - - rv = hw->qdma_indirect_intr_ctx_conf(dev_hndl, - ring_index, - &rsp_ictxt->ictxt[i], - QDMA_HW_ACCESS_READ); - if (rv < 0) - resp->hdr.status = rv; - - } - } - break; - case MBOX_OP_INTR_CTXT_CLR: - { - int i; - struct mbox_msg_intr_ctxt *ictxt = &rcv->intr_ctxt.ctxt; - - for (i = 0; i < ictxt->num_rings; i++) { - rv = hw->qdma_indirect_intr_ctx_conf( - dev_hndl, - ictxt->ring_index_list[i], - NULL, QDMA_HW_ACCESS_CLEAR); - if (rv < 0) - resp->hdr.status = rv; - } - } - break; - case MBOX_OP_INTR_CTXT_INV: - { - struct mbox_msg_intr_ctxt *ictxt = &rcv->intr_ctxt.ctxt; - int i; - - for (i = 0; i < ictxt->num_rings; i++) { - rv = hw->qdma_indirect_intr_ctx_conf( - dev_hndl, - ictxt->ring_index_list[i], - NULL, QDMA_HW_ACCESS_INVALIDATE); - if (rv < 0) - resp->hdr.status = rv; - } - } - break; - case MBOX_OP_QCTXT_INV: - { - struct mbox_msg_qctxt *qctxt = &rcv->qctxt; - - rv = mbox_invalidate_queue_contexts(dev_hndl, - dma_device_index, - hdr->src_func_id, - qctxt->qid_hw, - qctxt->st, - qctxt->c2h, - qctxt->cmpt_ctxt_type); - } - break; - case MBOX_OP_QCTXT_CLR: - { - struct mbox_msg_qctxt *qctxt = &rcv->qctxt; - - rv = mbox_clear_queue_contexts(dev_hndl, - dma_device_index, - hdr->src_func_id, - qctxt->qid_hw, - qctxt->st, - qctxt->c2h, - qctxt->cmpt_ctxt_type); - } - break; - case MBOX_OP_QCTXT_RD: - { - struct mbox_msg_qctxt *qctxt = &rcv->qctxt; - - rv = mbox_read_queue_contexts(dev_hndl, hdr->src_func_id, - qctxt->qid_hw, - qctxt->st, - qctxt->c2h, - qctxt->cmpt_ctxt_type, - &resp->qctxt.descq_ctxt); - } - break; - case MBOX_OP_QCTXT_WRT: - { - struct mbox_msg_qctxt *qctxt = &rcv->qctxt; - - qctxt->descq_conf.func_id = hdr->src_func_id; - rv = mbox_write_queue_contexts(dev_hndl, - dma_device_index, qctxt); - } - break; - case MBOX_OP_RESET_PREPARE_RESP: - return QDMA_MBOX_VF_RESET; - case MBOX_OP_RESET_DONE_RESP: - return QDMA_MBOX_PF_RESET_DONE; - case MBOX_OP_REG_LIST_READ: - { - struct mbox_read_reg_list *rcv_read_reg_list = - &rcv->reg_read_list; - struct mbox_read_reg_list *rsp_read_reg_list = - &resp->reg_read_list; - - rv = hw->qdma_read_reg_list((void *)dev_hndl, 1, - rcv_read_reg_list->group_num, - &rsp_read_reg_list->num_regs, - rsp_read_reg_list->reg_list); - - if (rv < 0 || rsp_read_reg_list->num_regs == 0) { - rv = -QDMA_ERR_MBOX_REG_READ_FAILED; - goto exit_func; - } - - } - break; - case MBOX_OP_PF_BYE_RESP: - return QDMA_MBOX_PF_BYE; - default: - qdma_log_error("%s: op=%d invalid, err:%d\n", - __func__, - rcv->hdr.op, - -QDMA_ERR_MBOX_INV_MSG); - return -QDMA_ERR_MBOX_INV_MSG; - break; - } - -exit_func: - resp->hdr.op = rcv->hdr.op + MBOX_MSG_OP_RSP_OFFSET; - resp->hdr.dst_func_id = rcv->hdr.src_func_id; - resp->hdr.src_func_id = func_id; - - resp->hdr.status = rv; - - return ret; -} - -int qmda_mbox_compose_vf_online(uint16_t func_id, - uint16_t qmax, int *qbase, uint32_t *raw_data) -{ - union qdma_mbox_txrx *msg = (union qdma_mbox_txrx *)raw_data; - - if (!raw_data) { - qdma_log_error("%s: raw_data=%p, err:%d\n", - __func__, raw_data, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - qdma_mbox_memset(raw_data, 0, sizeof(union qdma_mbox_txrx)); - msg->hdr.op = MBOX_OP_HELLO; - msg->hdr.src_func_id = func_id; - msg->fmap.qbase = (uint32_t)*qbase; - msg->fmap.qmax = qmax; - - return QDMA_SUCCESS; -} - -int qdma_mbox_compose_vf_offline(uint16_t func_id, - uint32_t *raw_data) -{ - union qdma_mbox_txrx *msg = (union qdma_mbox_txrx *)raw_data; - - if (!raw_data) { - qdma_log_error("%s: raw_data=%p, err:%d\n", - __func__, raw_data, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - qdma_mbox_memset(raw_data, 0, sizeof(union qdma_mbox_txrx)); - msg->hdr.op = MBOX_OP_VF_BYE; - msg->hdr.src_func_id = func_id; - - return QDMA_SUCCESS; -} - -int qdma_mbox_compose_vf_reset_offline(uint16_t func_id, - uint32_t *raw_data) -{ - union qdma_mbox_txrx *msg = (union qdma_mbox_txrx *)raw_data; - - if (!raw_data) { - qdma_log_error("%s: raw_data=%p, err:%d\n", - __func__, raw_data, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - qdma_mbox_memset(raw_data, 0, sizeof(union qdma_mbox_txrx)); - msg->hdr.op = MBOX_OP_PF_RESET_VF_BYE; - msg->hdr.src_func_id = func_id; - - return QDMA_SUCCESS; -} - - - -int qdma_mbox_compose_vf_qreq(uint16_t func_id, - uint16_t qmax, int qbase, uint32_t *raw_data) -{ - union qdma_mbox_txrx *msg = (union qdma_mbox_txrx *)raw_data; - - if (!raw_data) { - qdma_log_error("%s: raw_data=%p, err:%d\n", - __func__, raw_data, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - qdma_mbox_memset(raw_data, 0, sizeof(union qdma_mbox_txrx)); - msg->hdr.op = MBOX_OP_QREQ; - msg->hdr.src_func_id = func_id; - msg->fmap.qbase = qbase; - msg->fmap.qmax = qmax; - - return QDMA_SUCCESS; -} - -int qdma_mbox_compose_vf_notify_qadd(uint16_t func_id, - uint16_t qid_hw, - enum qdma_dev_q_type q_type, - uint32_t *raw_data) -{ - union qdma_mbox_txrx *msg = (union qdma_mbox_txrx *)raw_data; - - if (!raw_data) { - qdma_log_error("%s: raw_data=%p, err:%d\n", - __func__, raw_data, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - qdma_mbox_memset(raw_data, 0, sizeof(union qdma_mbox_txrx)); - msg->hdr.op = MBOX_OP_QNOTIFY_ADD; - msg->hdr.src_func_id = func_id; - msg->q_notify.qid_hw = qid_hw; - msg->q_notify.q_type = q_type; - - return QDMA_SUCCESS; -} - -int qdma_mbox_compose_vf_get_device_active_qcnt(uint16_t func_id, - uint32_t *raw_data) -{ - union qdma_mbox_txrx *msg = (union qdma_mbox_txrx *)raw_data; - - if (!raw_data) { - qdma_log_error("%s: raw_data=%p, err:%d\n", - __func__, raw_data, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - qdma_mbox_memset(raw_data, 0, sizeof(union qdma_mbox_txrx)); - msg->hdr.op = MBOX_OP_GET_QACTIVE_CNT; - msg->hdr.src_func_id = func_id; - - return QDMA_SUCCESS; -} - -int qdma_mbox_compose_vf_notify_qdel(uint16_t func_id, - uint16_t qid_hw, - enum qdma_dev_q_type q_type, - uint32_t *raw_data) -{ - union qdma_mbox_txrx *msg = (union qdma_mbox_txrx *)raw_data; - - if (!raw_data) { - qdma_log_error("%s: raw_data=%p, err:%d\n", - __func__, raw_data, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - qdma_mbox_memset(raw_data, 0, sizeof(union qdma_mbox_txrx)); - msg->hdr.op = MBOX_OP_QNOTIFY_DEL; - msg->hdr.src_func_id = func_id; - msg->q_notify.qid_hw = qid_hw; - msg->q_notify.q_type = q_type; - - return QDMA_SUCCESS; -} - -int qdma_mbox_compose_vf_fmap_prog(uint16_t func_id, - uint16_t qmax, int qbase, - uint32_t *raw_data) -{ - union qdma_mbox_txrx *msg = (union qdma_mbox_txrx *)raw_data; - - if (!raw_data) { - qdma_log_error("%s: raw_data=%p, err:%d\n", - __func__, raw_data, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - qdma_mbox_memset(raw_data, 0, sizeof(union qdma_mbox_txrx)); - msg->hdr.op = MBOX_OP_FMAP; - msg->hdr.src_func_id = func_id; - msg->fmap.qbase = (uint32_t)qbase; - msg->fmap.qmax = qmax; - - return QDMA_SUCCESS; -} - -int qdma_mbox_compose_vf_qctxt_write(uint16_t func_id, - uint16_t qid_hw, uint8_t st, uint8_t c2h, - enum mbox_cmpt_ctxt_type cmpt_ctxt_type, - struct mbox_descq_conf *descq_conf, - uint32_t *raw_data) -{ - union qdma_mbox_txrx *msg = (union qdma_mbox_txrx *)raw_data; - - if (!raw_data) { - qdma_log_error("%s: raw_data=%p, err:%d\n", - __func__, raw_data, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - qdma_mbox_memset(raw_data, 0, sizeof(union qdma_mbox_txrx)); - msg->hdr.op = MBOX_OP_QCTXT_WRT; - msg->hdr.src_func_id = func_id; - msg->qctxt.qid_hw = qid_hw; - msg->qctxt.c2h = c2h; - msg->qctxt.st = st; - msg->qctxt.cmpt_ctxt_type = cmpt_ctxt_type; - - qdma_mbox_memcpy(&msg->qctxt.descq_conf, descq_conf, - sizeof(struct mbox_descq_conf)); - - return QDMA_SUCCESS; -} - -int qdma_mbox_compose_vf_qctxt_read(uint16_t func_id, - uint16_t qid_hw, uint8_t st, uint8_t c2h, - enum mbox_cmpt_ctxt_type cmpt_ctxt_type, - uint32_t *raw_data) -{ - union qdma_mbox_txrx *msg = (union qdma_mbox_txrx *)raw_data; - - if (!raw_data) { - qdma_log_error("%s: raw_data=%p, err:%d\n", - __func__, raw_data, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - qdma_mbox_memset(raw_data, 0, sizeof(union qdma_mbox_txrx)); - msg->hdr.op = MBOX_OP_QCTXT_RD; - msg->hdr.src_func_id = func_id; - msg->qctxt.qid_hw = qid_hw; - msg->qctxt.c2h = c2h; - msg->qctxt.st = st; - msg->qctxt.cmpt_ctxt_type = cmpt_ctxt_type; - - return QDMA_SUCCESS; -} - -int qdma_mbox_compose_vf_qctxt_invalidate(uint16_t func_id, - uint16_t qid_hw, uint8_t st, uint8_t c2h, - enum mbox_cmpt_ctxt_type cmpt_ctxt_type, - uint32_t *raw_data) -{ - union qdma_mbox_txrx *msg = (union qdma_mbox_txrx *)raw_data; - - if (!raw_data) { - qdma_log_error("%s: raw_data=%p, err:%d\n", - __func__, raw_data, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - qdma_mbox_memset(raw_data, 0, sizeof(union qdma_mbox_txrx)); - msg->hdr.op = MBOX_OP_QCTXT_INV; - msg->hdr.src_func_id = func_id; - msg->qctxt.qid_hw = qid_hw; - msg->qctxt.c2h = c2h; - msg->qctxt.st = st; - msg->qctxt.cmpt_ctxt_type = cmpt_ctxt_type; - - return QDMA_SUCCESS; -} - -int qdma_mbox_compose_vf_qctxt_clear(uint16_t func_id, - uint16_t qid_hw, uint8_t st, uint8_t c2h, - enum mbox_cmpt_ctxt_type cmpt_ctxt_type, - uint32_t *raw_data) -{ - union qdma_mbox_txrx *msg = (union qdma_mbox_txrx *)raw_data; - - if (!raw_data) { - qdma_log_error("%s: raw_data=%p, err:%d\n", - __func__, raw_data, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - qdma_mbox_memset(raw_data, 0, sizeof(union qdma_mbox_txrx)); - msg->hdr.op = MBOX_OP_QCTXT_CLR; - msg->hdr.src_func_id = func_id; - msg->qctxt.qid_hw = qid_hw; - msg->qctxt.c2h = c2h; - msg->qctxt.st = st; - msg->qctxt.cmpt_ctxt_type = cmpt_ctxt_type; - - return QDMA_SUCCESS; -} - -int qdma_mbox_compose_csr_read(uint16_t func_id, - uint32_t *raw_data) -{ - union qdma_mbox_txrx *msg = (union qdma_mbox_txrx *)raw_data; - - if (!raw_data) { - qdma_log_error("%s: raw_data=%p, err:%d\n", - __func__, raw_data, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - qdma_mbox_memset(raw_data, 0, sizeof(union qdma_mbox_txrx)); - msg->hdr.op = MBOX_OP_CSR; - msg->hdr.src_func_id = func_id; - - return QDMA_SUCCESS; -} - -int qdma_mbox_compose_reg_read(uint16_t func_id, - uint16_t group_num, - uint32_t *raw_data) -{ - union qdma_mbox_txrx *msg = (union qdma_mbox_txrx *)raw_data; - - if (!raw_data) { - qdma_log_error("%s: raw_data=%p, err:%d\n", - __func__, raw_data, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - qdma_mbox_memset(raw_data, 0, sizeof(union qdma_mbox_txrx)); - msg->hdr.op = MBOX_OP_REG_LIST_READ; - msg->hdr.src_func_id = func_id; - msg->reg_read_list.group_num = group_num; - - return QDMA_SUCCESS; -} - -int qdma_mbox_compose_vf_intr_ctxt_write(uint16_t func_id, - struct mbox_msg_intr_ctxt *intr_ctxt, - uint32_t *raw_data) -{ - union qdma_mbox_txrx *msg = (union qdma_mbox_txrx *)raw_data; - - if (!raw_data) { - qdma_log_error("%s: raw_data=%p, err:%d\n", - __func__, raw_data, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - qdma_mbox_memset(raw_data, 0, sizeof(union qdma_mbox_txrx)); - msg->hdr.op = MBOX_OP_INTR_CTXT_WRT; - msg->hdr.src_func_id = func_id; - qdma_mbox_memcpy(&msg->intr_ctxt.ctxt, intr_ctxt, - sizeof(struct mbox_msg_intr_ctxt)); - - return QDMA_SUCCESS; -} - -int qdma_mbox_compose_vf_intr_ctxt_read(uint16_t func_id, - struct mbox_msg_intr_ctxt *intr_ctxt, - uint32_t *raw_data) -{ - union qdma_mbox_txrx *msg = (union qdma_mbox_txrx *)raw_data; - - if (!raw_data) { - qdma_log_error("%s: raw_data=%p, err:%d\n", - __func__, raw_data, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - qdma_mbox_memset(raw_data, 0, sizeof(union qdma_mbox_txrx)); - msg->hdr.op = MBOX_OP_INTR_CTXT_RD; - msg->hdr.src_func_id = func_id; - qdma_mbox_memcpy(&msg->intr_ctxt.ctxt, intr_ctxt, - sizeof(struct mbox_msg_intr_ctxt)); - - return QDMA_SUCCESS; -} - -int qdma_mbox_compose_vf_intr_ctxt_clear(uint16_t func_id, - struct mbox_msg_intr_ctxt *intr_ctxt, - uint32_t *raw_data) -{ - union qdma_mbox_txrx *msg = (union qdma_mbox_txrx *)raw_data; - - if (!raw_data) { - qdma_log_error("%s: raw_data=%p, err:%d\n", - __func__, raw_data, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - qdma_mbox_memset(raw_data, 0, sizeof(union qdma_mbox_txrx)); - msg->hdr.op = MBOX_OP_INTR_CTXT_CLR; - msg->hdr.src_func_id = func_id; - qdma_mbox_memcpy(&msg->intr_ctxt.ctxt, intr_ctxt, - sizeof(struct mbox_msg_intr_ctxt)); - - return QDMA_SUCCESS; -} - -int qdma_mbox_compose_vf_intr_ctxt_invalidate(uint16_t func_id, - struct mbox_msg_intr_ctxt *intr_ctxt, - uint32_t *raw_data) -{ - union qdma_mbox_txrx *msg = (union qdma_mbox_txrx *)raw_data; - - if (!raw_data) { - qdma_log_error("%s: raw_data=%p, err:%d\n", - __func__, raw_data, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - qdma_mbox_memset(raw_data, 0, sizeof(union qdma_mbox_txrx)); - msg->hdr.op = MBOX_OP_INTR_CTXT_INV; - msg->hdr.src_func_id = func_id; - qdma_mbox_memcpy(&msg->intr_ctxt.ctxt, intr_ctxt, - sizeof(struct mbox_msg_intr_ctxt)); - - return QDMA_SUCCESS; -} - -uint8_t qdma_mbox_is_msg_response(uint32_t *send_data, uint32_t *rcv_data) -{ - union qdma_mbox_txrx *tx_msg = (union qdma_mbox_txrx *)send_data; - union qdma_mbox_txrx *rx_msg = (union qdma_mbox_txrx *)rcv_data; - - return ((tx_msg->hdr.op + MBOX_MSG_OP_RSP_OFFSET) == rx_msg->hdr.op) ? - 1 : 0; -} - -int qdma_mbox_vf_response_status(uint32_t *rcv_data) -{ - union qdma_mbox_txrx *msg = (union qdma_mbox_txrx *)rcv_data; - - return msg->hdr.status; -} - -uint8_t qdma_mbox_vf_func_id_get(uint32_t *rcv_data, uint8_t is_vf) -{ - union qdma_mbox_txrx *msg = (union qdma_mbox_txrx *)rcv_data; - uint16_t func_id; - - if (is_vf) - func_id = msg->hdr.dst_func_id; - else - func_id = msg->hdr.src_func_id; - - return func_id; -} - -int qdma_mbox_vf_active_queues_get(uint32_t *rcv_data, - enum qdma_dev_q_type q_type) -{ - union qdma_mbox_txrx *msg = (union qdma_mbox_txrx *)rcv_data; - int queues = 0; - - if (q_type == QDMA_DEV_Q_TYPE_H2C) - queues = msg->qcnt.h2c_queues; - - if (q_type == QDMA_DEV_Q_TYPE_C2H) - queues = msg->qcnt.c2h_queues; - - if (q_type == QDMA_DEV_Q_TYPE_CMPT) - queues = msg->qcnt.cmpt_queues; - - return queues; -} - - -uint8_t qdma_mbox_vf_parent_func_id_get(uint32_t *rcv_data) -{ - union qdma_mbox_txrx *msg = (union qdma_mbox_txrx *)rcv_data; - - return msg->hdr.src_func_id; -} - -int qdma_mbox_vf_dev_info_get(uint32_t *rcv_data, - struct qdma_dev_attributes *dev_cap, uint32_t *dma_device_index) -{ - union qdma_mbox_txrx *msg = (union qdma_mbox_txrx *)rcv_data; - - *dev_cap = msg->hello.dev_cap; - *dma_device_index = msg->hello.dma_device_index; - - return msg->hdr.status; -} - -int qdma_mbox_vf_qinfo_get(uint32_t *rcv_data, int *qbase, uint16_t *qmax) -{ - union qdma_mbox_txrx *msg = (union qdma_mbox_txrx *)rcv_data; - - *qbase = msg->fmap.qbase; - *qmax = msg->fmap.qmax; - - return msg->hdr.status; -} - -int qdma_mbox_vf_csr_get(uint32_t *rcv_data, struct qdma_csr_info *csr) -{ - union qdma_mbox_txrx *msg = (union qdma_mbox_txrx *)rcv_data; - - qdma_mbox_memcpy(csr, &msg->csr.csr_info, sizeof(struct qdma_csr_info)); - - return msg->hdr.status; - -} - -int qdma_mbox_vf_reg_list_get(uint32_t *rcv_data, - uint16_t *num_regs, struct qdma_reg_data *reg_list) -{ - union qdma_mbox_txrx *msg = (union qdma_mbox_txrx *)rcv_data; - - *num_regs = msg->reg_read_list.num_regs; - qdma_mbox_memcpy(reg_list, &(msg->reg_read_list.reg_list), - (*num_regs * sizeof(struct qdma_reg_data))); - - return msg->hdr.status; - -} - -int qdma_mbox_vf_context_get(uint32_t *rcv_data, - struct qdma_descq_context *ctxt) -{ - union qdma_mbox_txrx *msg = (union qdma_mbox_txrx *)rcv_data; - - qdma_mbox_memcpy(ctxt, &msg->qctxt.descq_ctxt, - sizeof(struct qdma_descq_context)); - - return msg->hdr.status; -} - -int qdma_mbox_vf_intr_context_get(uint32_t *rcv_data, - struct mbox_msg_intr_ctxt *ictxt) -{ - union qdma_mbox_txrx *msg = (union qdma_mbox_txrx *)rcv_data; - - qdma_mbox_memcpy(ictxt, &msg->intr_ctxt.ctxt, - sizeof(struct mbox_msg_intr_ctxt)); - - return msg->hdr.status; -} - -void qdma_mbox_pf_hw_clear_ack(void *dev_hndl) -{ - uint32_t v; - uint32_t reg; - int i; - uint32_t mbox_base = get_mbox_offset(dev_hndl, 0); - - reg = mbox_base + MBOX_PF_ACK_BASE; - - v = qdma_reg_read(dev_hndl, mbox_base + MBOX_FN_STATUS); - if ((v & F_MBOX_FN_STATUS_ACK) == 0) - return; - - for (i = 0; i < MBOX_PF_ACK_COUNT; i++, reg += MBOX_PF_ACK_STEP) { - v = qdma_reg_read(dev_hndl, reg); - - if (!v) - continue; - - /* clear the ack status */ - qdma_reg_write(dev_hndl, reg, v); - } -} - -int qdma_mbox_send(void *dev_hndl, uint8_t is_vf, uint32_t *raw_data) -{ - int i; - uint32_t reg = MBOX_OUT_MSG_BASE; - uint32_t v; - union qdma_mbox_txrx *msg = (union qdma_mbox_txrx *)raw_data; - uint16_t dst_func_id = msg->hdr.dst_func_id; - uint32_t mbox_base = get_mbox_offset(dev_hndl, is_vf); - - v = qdma_reg_read(dev_hndl, mbox_base + MBOX_FN_STATUS); - if (v & F_MBOX_FN_STATUS_OUT_MSG) - return -QDMA_ERR_MBOX_SEND_BUSY; - - if (!is_vf) - qdma_reg_write(dev_hndl, mbox_base + MBOX_FN_TARGET, - V_MBOX_FN_TARGET_ID(dst_func_id)); - - for (i = 0; i < MBOX_MSG_REG_MAX; i++, reg += MBOX_MSG_STEP) - qdma_reg_write(dev_hndl, mbox_base + reg, raw_data[i]); - - /* clear the outgoing ack */ - if (!is_vf) - mbox_pf_hw_clear_func_ack(dev_hndl, dst_func_id); - - - qdma_log_debug("%s %s tx from_id=%d, to_id=%d, opcode=0x%x\n", __func__, - is_vf?"VF":"PF", msg->hdr.src_func_id, - msg->hdr.dst_func_id, msg->hdr.op); - qdma_reg_write(dev_hndl, mbox_base + MBOX_FN_CMD, F_MBOX_FN_CMD_SND); - - return QDMA_SUCCESS; -} - -int qdma_mbox_rcv(void *dev_hndl, uint8_t is_vf, uint32_t *raw_data) -{ - uint32_t reg = MBOX_IN_MSG_BASE; - uint32_t v = 0; - int all_zero_msg = 1; - int i; - uint32_t from_id = 0; - union qdma_mbox_txrx *msg = (union qdma_mbox_txrx *)raw_data; - uint32_t mbox_base = get_mbox_offset(dev_hndl, is_vf); - - v = qdma_reg_read(dev_hndl, mbox_base + MBOX_FN_STATUS); - - if (!(v & M_MBOX_FN_STATUS_IN_MSG)) - return -QDMA_ERR_MBOX_NO_MSG_IN; - - if (!is_vf) { - from_id = G_MBOX_FN_STATUS_SRC(v); - qdma_reg_write(dev_hndl, mbox_base + MBOX_FN_TARGET, from_id); - } - - for (i = 0; i < MBOX_MSG_REG_MAX; i++, reg += MBOX_MSG_STEP) { - raw_data[i] = qdma_reg_read(dev_hndl, mbox_base + reg); - /* if rcv'ed message is all zero, stop and disable the mbox, - * the h/w mbox is not working properly - */ - if (raw_data[i]) - all_zero_msg = 0; - } - - /* ack'ed the sender */ - qdma_reg_write(dev_hndl, mbox_base + MBOX_FN_CMD, F_MBOX_FN_CMD_RCV); - if (all_zero_msg) { - qdma_log_error("%s: Message recv'd is all zeros. failure:%d\n", - __func__, - -QDMA_ERR_MBOX_ALL_ZERO_MSG); - return -QDMA_ERR_MBOX_ALL_ZERO_MSG; - } - - - qdma_log_debug("%s %s fid=%d, opcode=0x%x\n", __func__, - is_vf?"VF":"PF", msg->hdr.dst_func_id, - msg->hdr.op); - if (!is_vf && (from_id != msg->hdr.src_func_id)) - msg->hdr.src_func_id = from_id; - - return QDMA_SUCCESS; -} - -void qdma_mbox_hw_init(void *dev_hndl, uint8_t is_vf) -{ - uint32_t v; - uint32_t mbox_base = get_mbox_offset(dev_hndl, is_vf); - - if (is_vf) { - v = qdma_reg_read(dev_hndl, mbox_base + MBOX_FN_STATUS); - if (v & M_MBOX_FN_STATUS_IN_MSG) - qdma_reg_write(dev_hndl, mbox_base + MBOX_FN_CMD, - F_MBOX_FN_CMD_RCV); - } else - qdma_mbox_pf_hw_clear_ack(dev_hndl); -} - -void qdma_mbox_enable_interrupts(void *dev_hndl, uint8_t is_vf) -{ - int vector = 0x0; - uint32_t mbox_base = get_mbox_offset(dev_hndl, is_vf); - - qdma_reg_write(dev_hndl, mbox_base + MBOX_ISR_VEC, vector); - qdma_reg_write(dev_hndl, mbox_base + MBOX_ISR_EN, 0x1); -} - -void qdma_mbox_disable_interrupts(void *dev_hndl, uint8_t is_vf) -{ - uint32_t mbox_base = get_mbox_offset(dev_hndl, is_vf); - - qdma_reg_write(dev_hndl, mbox_base + MBOX_ISR_EN, 0x0); -} - - -int qdma_mbox_compose_vf_reset_message(uint32_t *raw_data, uint8_t src_funcid, - uint8_t dest_funcid) -{ - union qdma_mbox_txrx *msg = (union qdma_mbox_txrx *)raw_data; - - if (!raw_data) - return -QDMA_ERR_INV_PARAM; - - qdma_mbox_memset(raw_data, 0, sizeof(union qdma_mbox_txrx)); - msg->hdr.op = MBOX_OP_RESET_PREPARE; - msg->hdr.src_func_id = src_funcid; - msg->hdr.dst_func_id = dest_funcid; - return 0; -} - -int qdma_mbox_compose_pf_reset_done_message(uint32_t *raw_data, - uint8_t src_funcid, uint8_t dest_funcid) -{ - union qdma_mbox_txrx *msg = (union qdma_mbox_txrx *)raw_data; - - if (!raw_data) - return -QDMA_ERR_INV_PARAM; - - qdma_mbox_memset(raw_data, 0, sizeof(union qdma_mbox_txrx)); - msg->hdr.op = MBOX_OP_RESET_DONE; - msg->hdr.src_func_id = src_funcid; - msg->hdr.dst_func_id = dest_funcid; - return 0; -} - -int qdma_mbox_compose_pf_offline(uint32_t *raw_data, uint8_t src_funcid, - uint8_t dest_funcid) -{ - union qdma_mbox_txrx *msg = (union qdma_mbox_txrx *)raw_data; - - if (!raw_data) - return -QDMA_ERR_INV_PARAM; - - qdma_mbox_memset(raw_data, 0, sizeof(union qdma_mbox_txrx)); - msg->hdr.op = MBOX_OP_PF_BYE; - msg->hdr.src_func_id = src_funcid; - msg->hdr.dst_func_id = dest_funcid; - return 0; -} - -int qdma_mbox_vf_rcv_msg_handler(uint32_t *rcv_msg, uint32_t *resp_msg) -{ - union qdma_mbox_txrx *rcv = (union qdma_mbox_txrx *)rcv_msg; - union qdma_mbox_txrx *resp = (union qdma_mbox_txrx *)resp_msg; - int rv = 0; - - switch (rcv->hdr.op) { - case MBOX_OP_RESET_PREPARE: - resp->hdr.op = rcv->hdr.op + MBOX_MSG_OP_RSP_OFFSET; - resp->hdr.dst_func_id = rcv->hdr.src_func_id; - resp->hdr.src_func_id = rcv->hdr.dst_func_id; - rv = QDMA_MBOX_VF_RESET; - break; - case MBOX_OP_RESET_DONE: - resp->hdr.op = rcv->hdr.op + MBOX_MSG_OP_RSP_OFFSET; - resp->hdr.dst_func_id = rcv->hdr.src_func_id; - resp->hdr.src_func_id = rcv->hdr.dst_func_id; - rv = QDMA_MBOX_PF_RESET_DONE; - break; - case MBOX_OP_PF_BYE: - resp->hdr.op = rcv->hdr.op + MBOX_MSG_OP_RSP_OFFSET; - resp->hdr.dst_func_id = rcv->hdr.src_func_id; - resp->hdr.src_func_id = rcv->hdr.dst_func_id; - rv = QDMA_MBOX_PF_BYE; - break; - default: - break; - } - return rv; -} - -uint8_t qdma_mbox_out_status(void *dev_hndl, uint8_t is_vf) -{ - uint32_t v; - uint32_t mbox_base = get_mbox_offset(dev_hndl, is_vf); - - v = qdma_reg_read(dev_hndl, mbox_base + MBOX_FN_STATUS); - if (v & F_MBOX_FN_STATUS_OUT_MSG) - return 1; - else - return 0; -} diff --git a/QDMA/DPDK/drivers/net/qdma/qdma_access/qdma_mbox_protocol.h b/QDMA/DPDK/drivers/net/qdma/qdma_access/qdma_mbox_protocol.h deleted file mode 100755 index 243ee7570..000000000 --- a/QDMA/DPDK/drivers/net/qdma/qdma_access/qdma_mbox_protocol.h +++ /dev/null @@ -1,711 +0,0 @@ -/* - * Copyright (c) 2019-2022, Xilinx, Inc. All rights reserved. - * Copyright (c) 2022, Advanced Micro Devices, Inc. All rights reserved. - * - * BSD LICENSE - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * * Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#ifndef __QDMA_MBOX_PROTOCOL_H_ -#define __QDMA_MBOX_PROTOCOL_H_ - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * DOC: QDMA message box handling interface definitions - * - * Header file *qdma_mbox_protocol.h* defines data structures and function - * signatures exported for QDMA Mbox message handling. - */ - -#include "qdma_platform.h" -#include "qdma_resource_mgmt.h" - - -#define QDMA_MBOX_VF_ONLINE (1) -#define QDMA_MBOX_VF_OFFLINE (-1) -#define QDMA_MBOX_VF_RESET (2) -#define QDMA_MBOX_PF_RESET_DONE (3) -#define QDMA_MBOX_PF_BYE (4) -#define QDMA_MBOX_VF_RESET_BYE (5) - -/** mailbox register max */ -#define MBOX_MSG_REG_MAX 32 - -#define mbox_invalidate_msg(m) { (m)->hdr.op = MBOX_OP_NOOP; } - -/** - * struct mbox_descq_conf - collective bit-fields of all contexts - */ -struct mbox_descq_conf { - - /** @ring_bs_addr: ring base address */ - uint64_t ring_bs_addr; - /** @cmpt_ring_bs_addr: completion ring base address */ - uint64_t cmpt_ring_bs_addr; - /** @forced_en: enable fetch credit */ - uint32_t forced_en:1; - /** @en_bypass: bypass enable */ - uint32_t en_bypass:1; - /** @irq_arm: arm irq */ - uint32_t irq_arm:1; - /** @wbi_intvl_en: writeback interval enable */ - uint32_t wbi_intvl_en:1; - /** @wbi_chk: writeback pending check */ - uint32_t wbi_chk:1; - /** @at: address translation */ - uint32_t at:1; - /** @wbk_en: writeback enable */ - uint32_t wbk_en:1; - /** @irq_en: irq enable */ - uint32_t irq_en:1; - /** @pfch_en: prefetch enable */ - uint32_t pfch_en:1; - /** @en_bypass_prefetch: prefetch bypass enable */ - uint32_t en_bypass_prefetch:1; - /** @dis_overflow_check: disable overflow check */ - uint32_t dis_overflow_check:1; - /** @cmpt_int_en: completion interrupt enable */ - uint32_t cmpt_int_en:1; - /** @cmpt_at: completion address translation */ - uint32_t cmpt_at:1; - /** @cmpt_color: completion ring initial color bit */ - uint32_t cmpt_color:1; - /** @cmpt_full_upd: completion full update */ - uint32_t cmpt_full_upd:1; - /** @cmpl_stat_en: completion status enable */ - uint32_t cmpl_stat_en:1; - /** @desc_sz: descriptor size */ - uint32_t desc_sz:2; - /** @cmpt_desc_sz: completion ring descriptor size */ - uint32_t cmpt_desc_sz:2; - /** @triggermode: trigger mode */ - uint32_t triggermode:3; - /** @rsvd: reserved */ - uint32_t rsvd:9; - /** @func_id: function ID */ - uint32_t func_id:16; - /** @cnt_thres: counter threshold */ - uint32_t cnt_thres:8; - /** @timer_thres: timer threshold */ - uint32_t timer_thres:8; - /** @intr_id: interrupt id */ - uint16_t intr_id:11; - /** @intr_aggr: interrupt aggregation */ - uint16_t intr_aggr:1; - /** @filler: filler bits */ - uint16_t filler:4; - /** @ringsz: ring size */ - uint16_t ringsz; - /** @bufsz: c2h buffer size */ - uint16_t bufsz; - /** @cmpt_ringsz: completion ring size */ - uint16_t cmpt_ringsz; -}; - -/** - * @enum - mbox_cmpt_ctxt_type - * @brief specifies whether cmpt is enabled with MM/ST - */ -enum mbox_cmpt_ctxt_type { - /** @QDMA_MBOX_CMPT_CTXT_ONLY: only cmpt context programming required */ - QDMA_MBOX_CMPT_CTXT_ONLY, - /** @QDMA_MBOX_CMPT_WITH_MM: completion context with MM */ - QDMA_MBOX_CMPT_WITH_MM, - /** @QDMA_MBOX_CMPT_WITH_ST: complete context with ST */ - QDMA_MBOX_CMPT_WITH_ST, - /** @QDMA_MBOX_CMPT_CTXT_NONE: No completion context */ - QDMA_MBOX_CMPT_CTXT_NONE -}; - -/** - * @struct - mbox_msg_intr_ctxt - * @brief interrupt context mailbox message - */ -struct mbox_msg_intr_ctxt { - /** @num_rings: number of intr context rings be assigned - * for virtual function - */ - uint8_t num_rings; /* 1 ~ 8 */ - /** @ring_index_list: ring index associated for each vector */ - uint32_t ring_index_list[QDMA_NUM_DATA_VEC_FOR_INTR_CXT]; - /** @w: interrupt context data for all rings*/ - struct qdma_indirect_intr_ctxt ictxt[QDMA_NUM_DATA_VEC_FOR_INTR_CXT]; -}; - -/*****************************************************************************/ -/** - * qdma_mbox_hw_init(): Initialize the mobx HW - * - * @dev_hndl: device handle - * @is_vf: is VF mbox - * - * Return: None - *****************************************************************************/ -void qdma_mbox_hw_init(void *dev_hndl, uint8_t is_vf); - -/*****************************************************************************/ -/** - * qdma_mbox_pf_rcv_msg_handler(): handles the raw message received in pf - * - * @dma_device_index: pci bus number - * @dev_hndl: device handle - * @func_id: own function id - * @rcv_msg: received raw message - * @resp_msg: raw response message - * - * Return: 0 : success and < 0: failure - *****************************************************************************/ -int qdma_mbox_pf_rcv_msg_handler(void *dev_hndl, uint8_t dma_device_index, - uint16_t func_id, uint32_t *rcv_msg, - uint32_t *resp_msg); - -/*****************************************************************************/ -/** - * qmda_mbox_compose_vf_online(): compose VF online message - * - * @func_id: destination function id - * @qmax: number of queues being requested - * @qbase: q base at which queues are allocated - * @raw_data: output raw message to be sent - * - * Return: 0 : success and < 0: failure - *****************************************************************************/ -int qmda_mbox_compose_vf_online(uint16_t func_id, - uint16_t qmax, int *qbase, uint32_t *raw_data); - -/*****************************************************************************/ -/** - * qdma_mbox_compose_vf_offline(): compose VF offline message - * - * @func_id: destination function id - * @raw_data: output raw message to be sent - * - * Return: 0 : success and < 0: failure - *****************************************************************************/ -int qdma_mbox_compose_vf_offline(uint16_t func_id, - uint32_t *raw_data); - -/*****************************************************************************/ -/** - * qdma_mbox_compose_vf_reset_message(): compose VF reset message - * - * @raw_data: output raw message to be sent - * @src_funcid: own function id - * @dest_funcid: destination function id - * - * Return: 0 : success and < 0: failure - *****************************************************************************/ -int qdma_mbox_compose_vf_reset_message(uint32_t *raw_data, uint8_t src_funcid, - uint8_t dest_funcid); - -/*****************************************************************************/ -/** - * qdma_mbox_compose_vf_reset_offline(): compose VF BYE for PF initiated RESET - * - * @func_id: own function id - * @raw_data: output raw message to be sent - * - * Return: 0 : success and < 0: failure - *****************************************************************************/ -int qdma_mbox_compose_vf_reset_offline(uint16_t func_id, - uint32_t *raw_data); -/*****************************************************************************/ -/** - * qdma_mbox_compose_pf_reset_done_message(): compose PF reset done message - * - * @raw_data: output raw message to be sent - * @src_funcid: own function id - * @dest_funcid: destination function id - * - * Return: 0 : success and < 0: failure - *****************************************************************************/ -int qdma_mbox_compose_pf_reset_done_message(uint32_t *raw_data, - uint8_t src_funcid, uint8_t dest_funcid); - -/*****************************************************************************/ -/** - * qdma_mbox_compose_pf_offline(): compose PF offline message - * - * @raw_data: output raw message to be sent - * @src_funcid: own function id - * @dest_funcid: destination function id - * - * Return: 0 : success and < 0: failure - *****************************************************************************/ -int qdma_mbox_compose_pf_offline(uint32_t *raw_data, uint8_t src_funcid, - uint8_t dest_funcid); - -/*****************************************************************************/ -/** - * qdma_mbox_compose_vf_qreq(): compose message to request queues - * - * @func_id: destination function id - * @qmax: number of queues being requested - * @qbase: q base at which queues are allocated - * @raw_data: output raw message to be sent - * - * Return: 0 : success and < 0: failure - *****************************************************************************/ -int qdma_mbox_compose_vf_qreq(uint16_t func_id, - uint16_t qmax, int qbase, uint32_t *raw_data); - -/*****************************************************************************/ -/** - * qdma_mbox_compose_vf_notify_qadd(): compose message to notify queue add - * - * @func_id: destination function id - * @qid_hw: number of queues being requested - * @q_type: direction of the of queue - * @raw_data: output raw message to be sent - * - * Return: 0 : success and < 0: failure - *****************************************************************************/ -int qdma_mbox_compose_vf_notify_qadd(uint16_t func_id, - uint16_t qid_hw, - enum qdma_dev_q_type q_type, - uint32_t *raw_data); - -/*****************************************************************************/ -/** - * qdma_mbox_compose_vf_notify_qdel(): compose message to notify queue delete - * - * @func_id: destination function id - * @qid_hw: number of queues being requested - * @q_type: direction of the of queue - * @raw_data: output raw message to be sent - * - * Return: 0 : success and < 0: failure - *****************************************************************************/ -int qdma_mbox_compose_vf_notify_qdel(uint16_t func_id, - uint16_t qid_hw, - enum qdma_dev_q_type q_type, - uint32_t *raw_data); - -/*****************************************************************************/ -/** - * qdma_mbox_compose_vf_notify_qdel(): compose message to get the active - * queue count - * - * @func_id: destination function id - * @raw_data: output raw message to be sent - * - * Return: 0 : success and < 0: failure - *****************************************************************************/ -int qdma_mbox_compose_vf_get_device_active_qcnt(uint16_t func_id, - uint32_t *raw_data); - -/*****************************************************************************/ -/** - * qdma_mbox_compose_vf_fmap_prog(): handles the raw message received - * - * @func_id: destination function id - * @qmax: number of queues being requested - * @qbase: q base at which queues are allocated - * @raw_data: output raw message to be sent - * - * Return: 0 : success and < 0: failure - *****************************************************************************/ -int qdma_mbox_compose_vf_fmap_prog(uint16_t func_id, - uint16_t qmax, int qbase, - uint32_t *raw_data); - -/*****************************************************************************/ -/** - * qdma_mbox_compose_vf_qctxt_write(): compose queue configuration data for - * compose and program - * - * @func_id: destination function id - * @qid_hw: HW queue for which the context has to be read - * @st: is st mode - * @c2h: is c2h direction - * @cmpt_ctxt_type: completion context type - * @descq_conf: pointer to queue config data structure - * @raw_data: output raw message to be sent - * - * Return: 0 : success and < 0: failure - *****************************************************************************/ -int qdma_mbox_compose_vf_qctxt_write(uint16_t func_id, - uint16_t qid_hw, uint8_t st, uint8_t c2h, - enum mbox_cmpt_ctxt_type cmpt_ctxt_type, - struct mbox_descq_conf *descq_conf, - uint32_t *raw_data); - -/*****************************************************************************/ -/** - * qdma_mbox_compose_vf_qctxt_read(): compose message to read context data of a - * queue - * - * @func_id: destination function id - * @qid_hw: HW queue for which the context has to be read - * @st: is st mode - * @c2h: is c2h direction - * @cmpt_ctxt_type: completion context type - * @raw_data: output raw message to be sent - * - * Return: 0 : success and < 0: failure - *****************************************************************************/ -int qdma_mbox_compose_vf_qctxt_read(uint16_t func_id, - uint16_t qid_hw, uint8_t st, uint8_t c2h, - enum mbox_cmpt_ctxt_type cmpt_ctxt_type, - uint32_t *raw_data); - -/*****************************************************************************/ -/** - * qdma_mbox_compose_vf_qctxt_invalidate(): compose queue context invalidate - * message - * - * @func_id: destination function id - * @qid_hw: HW queue for which the context has to be invalidated - * @st: is st mode - * @c2h: is c2h direction - * @cmpt_ctxt_type: completion context type - * @raw_data: output raw message to be sent - * - * Return: 0 : success and < 0: failure - *****************************************************************************/ -int qdma_mbox_compose_vf_qctxt_invalidate(uint16_t func_id, - uint16_t qid_hw, uint8_t st, uint8_t c2h, - enum mbox_cmpt_ctxt_type cmpt_ctxt_type, - uint32_t *raw_data); - -/*****************************************************************************/ -/** - * qdma_mbox_compose_vf_qctxt_clear(): compose queue context clear message - * - * @func_id: destination function id - * @qid_hw: HW queue for which the context has to be cleared - * @st: is st mode - * @c2h: is c2h direction - * @cmpt_ctxt_type: completion context type - * @raw_data: output raw message to be sent - * - * Return: 0 : success and < 0: failure - *****************************************************************************/ -int qdma_mbox_compose_vf_qctxt_clear(uint16_t func_id, - uint16_t qid_hw, uint8_t st, uint8_t c2h, - enum mbox_cmpt_ctxt_type cmpt_ctxt_type, - uint32_t *raw_data); - -/*****************************************************************************/ -/** - * qdma_mbox_compose_csr_read(): compose message to read csr info - * - * @func_id: destination function id - * @raw_data: output raw message to be sent - * - * Return: 0 : success and < 0: failure - *****************************************************************************/ -int qdma_mbox_compose_csr_read(uint16_t func_id, - uint32_t *raw_data); - -/*****************************************************************************/ -/** - * qdma_mbox_compose_reg_read(): compose message to read the register values - * - * @func_id: destination function id - * @group_num: group number for the registers to read - * @raw_data: output raw message to be sent - * - * Return: 0 : success and < 0: failure - *****************************************************************************/ -int qdma_mbox_compose_reg_read(uint16_t func_id, uint16_t group_num, - uint32_t *raw_data); - -/*****************************************************************************/ -/** - * qdma_mbox_compose_vf_intr_ctxt_write(): compose interrupt ring context - * programming message - * - * @func_id: destination function id - * @intr_ctxt: pointer to interrupt context data structure - * @raw_data: output raw message to be sent - * - * Return: 0 : success and < 0: failure - *****************************************************************************/ -int qdma_mbox_compose_vf_intr_ctxt_write(uint16_t func_id, - struct mbox_msg_intr_ctxt *intr_ctxt, - uint32_t *raw_data); - -/*****************************************************************************/ -/** - * qdma_mbox_compose_vf_intr_ctxt_read(): handles the raw message received - * - * @func_id: destination function id - * @intr_ctxt: pointer to interrupt context data structure - * @raw_data: output raw message to be sent - * - * Return: 0 : success and < 0: failure - *****************************************************************************/ -int qdma_mbox_compose_vf_intr_ctxt_read(uint16_t func_id, - struct mbox_msg_intr_ctxt *intr_ctxt, - uint32_t *raw_data); - -/*****************************************************************************/ -/** - * qdma_mbox_compose_vf_intr_ctxt_clear(): compose interrupt ring context - * clear message - * - * @func_id: destination function id - * @intr_ctxt: pointer to interrupt context data structure - * @raw_data: output raw message to be sent - * - * Return: 0 : success and < 0: failure - *****************************************************************************/ -int qdma_mbox_compose_vf_intr_ctxt_clear(uint16_t func_id, - struct mbox_msg_intr_ctxt *intr_ctxt, - uint32_t *raw_data); - -/*****************************************************************************/ -/** - * qdma_mbox_compose_vf_qctxt_invalidate(): compose interrupt ring context - * invalidate message - * - * @func_id: destination function id - * @intr_ctxt: pointer to interrupt context data structure - * @raw_data: output raw message to be sent - * - * Return: 0 : success and < 0: failure - *****************************************************************************/ -int qdma_mbox_compose_vf_intr_ctxt_invalidate(uint16_t func_id, - struct mbox_msg_intr_ctxt *intr_ctxt, - uint32_t *raw_data); - -/*****************************************************************************/ -/** - * qdma_mbox_is_msg_response(): check if the received msg opcode is response - * sent message opcode - * - * @send_data: mbox message sent - * @rcv_data: mbox message recieved - * - * Return: 1 : match and 0: does not match - *****************************************************************************/ -uint8_t qdma_mbox_is_msg_response(uint32_t *send_data, uint32_t *rcv_data); - -/*****************************************************************************/ -/** - * qdma_mbox_vf_response_status(): return the response received for the sent msg - * - * @rcv_data: mbox message recieved - * - * Return: response status received to the sent message - *****************************************************************************/ -int qdma_mbox_vf_response_status(uint32_t *rcv_data); - -/*****************************************************************************/ -/** - * qdma_mbox_vf_func_id_get(): return the vf function id - * - * @rcv_data: mbox message recieved - * @is_vf: is VF mbox - * - * Return: vf function id - *****************************************************************************/ -uint8_t qdma_mbox_vf_func_id_get(uint32_t *rcv_data, uint8_t is_vf); - -int qdma_mbox_vf_active_queues_get(uint32_t *rcv_data, - enum qdma_dev_q_type q_type); - -/*****************************************************************************/ -/** - * qdma_mbox_vf_parent_func_id_get(): return the vf parent function id - * - * @rcv_data: mbox message recieved - * - * Return: vf function id - *****************************************************************************/ -uint8_t qdma_mbox_vf_parent_func_id_get(uint32_t *rcv_data); - -/*****************************************************************************/ -/** - * qdma_mbox_vf_dev_info_get(): get dev info from received message - * - * @rcv_data: mbox message recieved - * @dev_cap: device capability information - * @dma_device_index: DMA Identifier to be read using the mbox. - * - * Return: response status with dev info received to the sent message - *****************************************************************************/ -int qdma_mbox_vf_dev_info_get(uint32_t *rcv_data, - struct qdma_dev_attributes *dev_cap, - uint32_t *dma_device_index); - -/*****************************************************************************/ -/** - * qdma_mbox_vf_qinfo_get(): get qinfo from received message - * - * @rcv_data: mbox message recieved - * @qmax: number of queues - * @qbase: q base at which queues are allocated - * - * Return: response status received to the sent message - *****************************************************************************/ -int qdma_mbox_vf_qinfo_get(uint32_t *rcv_data, int *qbase, uint16_t *qmax); - -/*****************************************************************************/ -/** - * qdma_mbox_vf_csr_get(): get csr info from received message - * - * @rcv_data: mbox message recieved - * @csr: pointer to the csr info - * - * Return: response status received to the sent message - *****************************************************************************/ -int qdma_mbox_vf_csr_get(uint32_t *rcv_data, struct qdma_csr_info *csr); - -/*****************************************************************************/ -/** - * qdma_mbox_vf_reg_list_get(): get reg info from received message - * - * @rcv_data: mbox message recieved - * @num_regs: number of register read - * @reg_list: pointer to the register info - * - * Return: response status received to the sent message - *****************************************************************************/ -int qdma_mbox_vf_reg_list_get(uint32_t *rcv_data, - uint16_t *num_regs, struct qdma_reg_data *reg_list); - -/*****************************************************************************/ -/** - * qdma_mbox_vf_context_get(): get queue context info from received message - * - * @rcv_data: mbox message recieved - * @ctxt: pointer to the queue context info - * - * Return: response status received to the sent message - *****************************************************************************/ -int qdma_mbox_vf_context_get(uint32_t *rcv_data, - struct qdma_descq_context *ctxt); - -/*****************************************************************************/ -/** - * qdma_mbox_vf_context_get(): get intr context info from received message - * - * @rcv_data: mbox message recieved - * @ctxt: pointer to the intr context info - * - * Return: response status received to the sent message - *****************************************************************************/ -int qdma_mbox_vf_intr_context_get(uint32_t *rcv_data, - struct mbox_msg_intr_ctxt *ictxt); - - -/*****************************************************************************/ -/** - * qdma_mbox_pf_hw_clear_ack() - clear the HW ack - * - * @dev_hndl: device handle - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -void qdma_mbox_pf_hw_clear_ack(void *dev_hndl); - -/*****************************************************************************/ -/** - * qdma_mbox_send() - function to send raw data via qdma mailbox - * - * @dev_hndl: device handle - * @is_vf: Whether PF or VF - * @raw_data: pointer to message being sent - * - * The function sends the raw_data to the outgoing mailbox memory and if PF, - * then assert the acknowledge status register bit. - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -int qdma_mbox_send(void *dev_hndl, uint8_t is_vf, uint32_t *raw_data); - -/*****************************************************************************/ -/** - * qdma_mbox_rcv() - function to receive raw data via qdma mailbox - * - * @dev_hndl: device handle - * @is_vf: Whether PF or VF - * @raw_data: pointer to the message being received - * - * The function receives the raw_data from the incoming mailbox memory and - * then acknowledge the sender by setting msg_rcv field in the command - * register. - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -int qdma_mbox_rcv(void *dev_hndl, uint8_t is_vf, uint32_t *raw_data); - -/*****************************************************************************/ -/** - * qdma_mbox_enable_interrupts() - Enable the QDMA mailbox interrupt - * - * @dev_hndl: pointer to xlnx_dma_dev - * @is_vf: Whether PF or VF - * - * @return none - *****************************************************************************/ -void qdma_mbox_enable_interrupts(void *dev_hndl, uint8_t is_vf); - -/*****************************************************************************/ -/** - * qdma_mbox_disable_interrupts() - Disable the QDMA mailbox interrupt - * - * @dev_hndl: pointer to xlnx_dma_dev - * @is_vf: Whether PF or VF - * - * @return none - *****************************************************************************/ -void qdma_mbox_disable_interrupts(void *dev_hndl, uint8_t is_vf); - -/*****************************************************************************/ -/** - * qdma_mbox_vf_rcv_msg_handler(): handles the raw message received in VF - * - * @rcv_msg: received raw message - * @resp_msg: raw response message - * - * Return: 0 : success and < 0: failure - *****************************************************************************/ -int qdma_mbox_vf_rcv_msg_handler(uint32_t *rcv_msg, uint32_t *resp_msg); - -/*****************************************************************************/ -/** - * qdma_mbox_out_status(): - * - * @dev_hndl: pointer to xlnx_dma_dev - * @is_vf: Whether PF or VF - * - * Return: 0 if MBOX outbox is empty, 1 if MBOX is not empty - *****************************************************************************/ -uint8_t qdma_mbox_out_status(void *dev_hndl, uint8_t is_vf); - -#ifdef __cplusplus -} -#endif - -#endif /* __QDMA_MBOX_PROTOCOL_H_ */ diff --git a/QDMA/DPDK/drivers/net/qdma/qdma_access/qdma_platform.h b/QDMA/DPDK/drivers/net/qdma/qdma_access/qdma_platform.h deleted file mode 100755 index f44bd59dd..000000000 --- a/QDMA/DPDK/drivers/net/qdma/qdma_access/qdma_platform.h +++ /dev/null @@ -1,193 +0,0 @@ -/* - * Copyright (c) 2019-2022, Xilinx, Inc. All rights reserved. - * Copyright (c) 2022, Advanced Micro Devices, Inc. All rights reserved. - * - * BSD LICENSE - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * * Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#ifndef __QDMA_PLATFORM_H_ -#define __QDMA_PLATFORM_H_ - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * DOC: QDMA platform specific interface definitions - * - * Header file *qdma_platform_env.h* defines function signatures that are - * required to be implemented by platform specific drivers. - */ - -#include "qdma_access_common.h" - -/*****************************************************************************/ -/** - * qdma_calloc(): allocate memory and initialize with 0 - * - * @num_blocks: number of blocks of contiguous memory of @size - * @size: size of each chunk of memory - * - * Return: pointer to the memory block created on success and NULL on failure - *****************************************************************************/ -void *qdma_calloc(uint32_t num_blocks, uint32_t size); - -/*****************************************************************************/ -/** - * qdma_memfree(): free the memory - * - * @memptr: pointer to the memory block - * - * Return: None - *****************************************************************************/ -void qdma_memfree(void *memptr); - -/*****************************************************************************/ -/** - * qdma_resource_lock_init() - Init lock to access resource management APIs - * - * @return None - *****************************************************************************/ -int qdma_resource_lock_init(void); - -/*****************************************************************************/ -/** - * qdma_resource_lock_take() - take lock to access resource management APIs - * - * @return None - *****************************************************************************/ -void qdma_resource_lock_take(void); - -/*****************************************************************************/ -/** - * qdma_resource_lock_give() - release lock after accessing resource management - * APIs - * - * @return None - *****************************************************************************/ -void qdma_resource_lock_give(void); - -/*****************************************************************************/ -/** - * qdma_reg_write() - Register write API. - * - * @dev_hndl: device handle - * @reg_offst: QDMA Config bar register offset to write - * @val: value to be written - * - * Return: Nothing - *****************************************************************************/ -void qdma_reg_write(void *dev_hndl, uint32_t reg_offst, uint32_t val); - -/*****************************************************************************/ -/** - * qdma_reg_read() - Register read API. - * - * @dev_hndl: device handle - * @reg_offst: QDMA Config bar register offset to be read - * - * Return: Value read - *****************************************************************************/ -uint32_t qdma_reg_read(void *dev_hndl, uint32_t reg_offst); - -/*****************************************************************************/ -/** - * qdma_reg_access_lock() - Lock function for Register access - * - * @dev_hndl: device handle - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -int qdma_reg_access_lock(void *dev_hndl); - -/*****************************************************************************/ -/** - * qdma_reg_access_release() - Release function for Register access - * - * @dev_hndl: device handle - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -int qdma_reg_access_release(void *dev_hndl); - -/*****************************************************************************/ -/** - * qdma_udelay() - delay function to be used in the common library - * - * @delay_usec: delay in microseconds - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -void qdma_udelay(uint32_t delay_usec); - -/*****************************************************************************/ -/** - * qdma_get_hw_access() - function to get the qdma_hw_access - * - * @dev_hndl: device handle - * @dev_cap: pointer to hold qdma_hw_access structure - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -void qdma_get_hw_access(void *dev_hndl, struct qdma_hw_access **hw); - -/*****************************************************************************/ -/** - * qdma_strncpy(): copy n size string from source to destination buffer - * - * @memptr: pointer to the memory block - * - * Return: None - *****************************************************************************/ -void qdma_strncpy(char *dest, const char *src, size_t n); - - -/*****************************************************************************/ -/** - * qdma_get_err_code() - function to get the qdma access mapped error code - * - * @acc_err_code: qdma access error code - * - * Return: returns the platform specific error code - *****************************************************************************/ -int qdma_get_err_code(int acc_err_code); - -/*****************************************************************************/ -/** - * qdma_io_wmb() - Write memory barrier for IO device - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -int qdma_io_wmb(void); - -#ifdef __cplusplus -} -#endif - -#endif /* __QDMA_PLATFORM_H_ */ diff --git a/QDMA/DPDK/drivers/net/qdma/qdma_access/qdma_reg_dump.h b/QDMA/DPDK/drivers/net/qdma/qdma_access/qdma_reg_dump.h deleted file mode 100755 index b1a63c024..000000000 --- a/QDMA/DPDK/drivers/net/qdma/qdma_access/qdma_reg_dump.h +++ /dev/null @@ -1,99 +0,0 @@ -/* - * Copyright (c) 2019-2022, Xilinx, Inc. All rights reserved. - * Copyright (c) 2022, Advanced Micro Devices, Inc. All rights reserved. - * - * BSD LICENSE - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * * Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#ifndef __QDMA_REG_DUMP_H__ -#define __QDMA_REG_DUMP_H__ - -#ifdef __cplusplus -extern "C" { -#endif - -#include "qdma_platform_env.h" -#include "qdma_access_common.h" - -#define DEBUGFS_DEV_INFO_SZ (300) - -#define QDMA_REG_NAME_LENGTH 64 -#define DEBUGFS_INTR_CNTX_SZ (2048 * 2) -#define DBGFS_ERR_BUFLEN (64) -#define DEBGFS_LINE_SZ (81) -#define DEBGFS_GEN_NAME_SZ (40) -#define REG_DUMP_SIZE_PER_LINE (256) - -#define MAX_QDMA_CFG_REGS (200) - -#define QDMA_MM_EN_SHIFT 0 -#define QDMA_CMPT_EN_SHIFT 1 -#define QDMA_ST_EN_SHIFT 2 -#define QDMA_MAILBOX_EN_SHIFT 3 - -#define QDMA_MM_MODE (1 << QDMA_MM_EN_SHIFT) -#define QDMA_COMPLETION_MODE (1 << QDMA_CMPT_EN_SHIFT) -#define QDMA_ST_MODE (1 << QDMA_ST_EN_SHIFT) -#define QDMA_MAILBOX (1 << QDMA_MAILBOX_EN_SHIFT) - - -#define QDMA_MM_ST_MODE \ - (QDMA_MM_MODE | QDMA_COMPLETION_MODE | QDMA_ST_MODE) - -#define GET_CAPABILITY_MASK(mm_en, st_en, mm_cmpt_en, mailbox_en) \ - ((mm_en << QDMA_MM_EN_SHIFT) | \ - ((mm_cmpt_en | st_en) << QDMA_CMPT_EN_SHIFT) | \ - (st_en << QDMA_ST_EN_SHIFT) | \ - (mailbox_en << QDMA_MAILBOX_EN_SHIFT)) - - -struct regfield_info { - const char *field_name; - uint32_t field_mask; -}; - -struct xreg_info { - const char *name; - uint32_t addr; - uint32_t repeat; - uint32_t step; - uint8_t shift; - uint8_t len; - uint8_t is_debug_reg; - uint8_t mode; - uint8_t read_type; - uint8_t num_bitfields; - struct regfield_info *bitfields; -}; - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/QDMA/DPDK/drivers/net/qdma/qdma_access/qdma_resource_mgmt.c b/QDMA/DPDK/drivers/net/qdma/qdma_access/qdma_resource_mgmt.c deleted file mode 100755 index d903859dc..000000000 --- a/QDMA/DPDK/drivers/net/qdma/qdma_access/qdma_resource_mgmt.c +++ /dev/null @@ -1,811 +0,0 @@ -/* - * Copyright (c) 2019-2022, Xilinx, Inc. All rights reserved. - * Copyright (c) 2022, Advanced Micro Devices, Inc. All rights reserved. - * - * BSD LICENSE - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * * Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include "qdma_resource_mgmt.h" -#include "qdma_platform.h" -#include "qdma_list.h" -#include "qdma_access_errors.h" - -#ifdef ENABLE_WPP_TRACING -#include "qdma_resource_mgmt.tmh" -#endif - -struct qdma_resource_entry { - int qbase; - uint32_t total_q; - struct qdma_list_head node; -}; - -/** per function entry */ -struct qdma_dev_entry { - uint16_t func_id; - uint32_t active_h2c_qcnt; - uint32_t active_c2h_qcnt; - uint32_t active_cmpt_qcnt; - struct qdma_resource_entry entry; -}; - -/** for hodling the qconf_entry structure */ -struct qdma_resource_master { - /** DMA device index this resource belongs to */ - uint32_t dma_device_index; - /** starting pci bus number this resource belongs to */ - uint32_t pci_bus_start; - /** ending pci bus number this resource belongs to */ - uint32_t pci_bus_end; - /** total queue this resource manager handles */ - uint32_t total_q; - /** queue base from which this resource manger handles */ - int qbase; - /** for attaching to master resource list */ - struct qdma_list_head node; - /** for holding device entries */ - struct qdma_list_head dev_list; - /** for holding free resource list */ - struct qdma_list_head free_list; - /** active queue count per resource*/ - uint32_t active_qcnt; -}; - -static QDMA_LIST_HEAD(master_resource_list); - -static struct qdma_resource_master *qdma_find_master_resource_entry( - uint32_t bus_start, uint32_t bus_end) -{ - struct qdma_list_head *entry, *tmp; - - qdma_resource_lock_take(); - qdma_list_for_each_safe(entry, tmp, &master_resource_list) { - struct qdma_resource_master *q_resource = - (struct qdma_resource_master *) - QDMA_LIST_GET_DATA(entry); - - if (q_resource->pci_bus_start == bus_start && - q_resource->pci_bus_end == bus_end) { - qdma_resource_lock_give(); - return q_resource; - } - } - qdma_resource_lock_give(); - - return NULL; -} - -static struct qdma_resource_master *qdma_get_master_resource_entry( - uint32_t dma_device_index) -{ - struct qdma_list_head *entry, *tmp; - - qdma_resource_lock_take(); - qdma_list_for_each_safe(entry, tmp, &master_resource_list) { - struct qdma_resource_master *q_resource = - (struct qdma_resource_master *) - QDMA_LIST_GET_DATA(entry); - - if (q_resource->dma_device_index == dma_device_index) { - qdma_resource_lock_give(); - return q_resource; - } - } - qdma_resource_lock_give(); - - return NULL; -} - -static struct qdma_dev_entry *qdma_get_dev_entry(uint32_t dma_device_index, - uint16_t func_id) -{ - struct qdma_list_head *entry, *tmp; - struct qdma_resource_master *q_resource = - qdma_get_master_resource_entry(dma_device_index); - - if (!q_resource) - return NULL; - - qdma_resource_lock_take(); - qdma_list_for_each_safe(entry, tmp, &q_resource->dev_list) { - struct qdma_dev_entry *dev_entry = (struct qdma_dev_entry *) - QDMA_LIST_GET_DATA(entry); - - if (dev_entry->func_id == func_id) { - qdma_resource_lock_give(); - return dev_entry; - } - } - qdma_resource_lock_give(); - - return NULL; -} - -static struct qdma_resource_entry *qdma_free_entry_create(int q_base, - uint32_t total_q) -{ - struct qdma_resource_entry *entry = (struct qdma_resource_entry *) - qdma_calloc(1, sizeof(struct qdma_resource_master)); - if (entry == NULL) - return NULL; - - entry->total_q = total_q; - entry->qbase = q_base; - - return entry; -} - -static void qdma_submit_to_free_list(struct qdma_dev_entry *dev_entry, - struct qdma_list_head *head) -{ - struct qdma_resource_entry *streach_node = NULL; - struct qdma_list_head *entry, *tmp; - /* create a new node to be added to empty free list */ - struct qdma_resource_entry *new_node = NULL; - - if (!dev_entry->entry.total_q) - return; - - if (qdma_list_is_empty(head)) { - new_node = qdma_free_entry_create(dev_entry->entry.qbase, - dev_entry->entry.total_q); - if (new_node == NULL) - return; - QDMA_LIST_SET_DATA(&new_node->node, new_node); - qdma_list_add_tail(&new_node->node, head); - /* reset device entry q resource params */ - dev_entry->entry.qbase = -1; - dev_entry->entry.total_q = 0; - } else { - qdma_list_for_each_safe(entry, tmp, head) { - struct qdma_resource_entry *node = - (struct qdma_resource_entry *) - QDMA_LIST_GET_DATA(entry); - - /* insert the free slot at appropriate place */ - if ((node->qbase > dev_entry->entry.qbase) || - qdma_list_is_last_entry(entry, head)) { - new_node = qdma_free_entry_create( - dev_entry->entry.qbase, - dev_entry->entry.total_q); - if (new_node == NULL) - return; - QDMA_LIST_SET_DATA(&new_node->node, new_node); - if (node->qbase > dev_entry->entry.qbase) - qdma_list_insert_before(&new_node->node, - &node->node); - else - qdma_list_add_tail(&new_node->node, - head); - /* reset device entry q resource params */ - dev_entry->entry.qbase = -1; - dev_entry->entry.total_q = 0; - break; - } - } - } - - /* de-fragment (merge contiguous resource chunks) if possible */ - qdma_list_for_each_safe(entry, tmp, head) { - struct qdma_resource_entry *node = - (struct qdma_resource_entry *)QDMA_LIST_GET_DATA(entry); - - if (!streach_node) - streach_node = node; - else { - if ((streach_node->qbase + streach_node->total_q) == - (uint32_t)node->qbase) { - streach_node->total_q += node->total_q; - qdma_list_del(&node->node); - qdma_memfree(node); - } else - streach_node = node; - } - } -} - -/** - * qdma_resource_entry() - return the best free list entry node that can - * accommodate the new request - */ -static struct qdma_resource_entry *qdma_get_resource_node(uint32_t qmax, - int qbase, - struct qdma_list_head *free_list_head) -{ - struct qdma_list_head *entry, *tmp; - struct qdma_resource_entry *best_fit_node = NULL; - - /* try to honor requested qbase */ - if (qbase >= 0) { - qdma_list_for_each_safe(entry, tmp, free_list_head) { - struct qdma_resource_entry *node = - (struct qdma_resource_entry *)QDMA_LIST_GET_DATA(entry); - - if ((qbase >= node->qbase) && - (node->qbase + node->total_q) >= - (qbase + qmax)) { - best_fit_node = node; - goto fragment_free_list; - } - } - } - best_fit_node = NULL; - - /* find a best node to accommodate q resource request */ - qdma_list_for_each_safe(entry, tmp, free_list_head) { - struct qdma_resource_entry *node = - (struct qdma_resource_entry *)QDMA_LIST_GET_DATA(entry); - - if (node->total_q >= qmax) { - if (!best_fit_node || (best_fit_node->total_q >= - node->total_q)) { - best_fit_node = node; - qbase = best_fit_node->qbase; - } - } - } - -fragment_free_list: - if (!best_fit_node) - return NULL; - - if ((qbase == best_fit_node->qbase) && - (qmax == best_fit_node->total_q)) - return best_fit_node; - - /* split free resource node accordingly */ - if ((qbase == best_fit_node->qbase) && - (qmax != best_fit_node->total_q)) { - /* - * create an extra node to hold the extra queues from this node - */ - struct qdma_resource_entry *new_entry = NULL; - int lqbase = best_fit_node->qbase + qmax; - uint32_t lqmax = best_fit_node->total_q - qmax; - - new_entry = qdma_free_entry_create(lqbase, lqmax); - if (new_entry == NULL) - return NULL; - QDMA_LIST_SET_DATA(&new_entry->node, new_entry); - qdma_list_insert_after(&new_entry->node, - &best_fit_node->node); - best_fit_node->total_q -= lqmax; - } else if ((qbase > best_fit_node->qbase) && - ((qbase + qmax) == (best_fit_node->qbase + - best_fit_node->total_q))) { - /* - * create an extra node to hold the extra queues from this node - */ - struct qdma_resource_entry *new_entry = NULL; - int lqbase = best_fit_node->qbase; - uint32_t lqmax = qbase - best_fit_node->qbase; - - new_entry = qdma_free_entry_create(lqbase, lqmax); - if (new_entry == NULL) - return NULL; - QDMA_LIST_SET_DATA(&new_entry->node, new_entry); - qdma_list_insert_before(&new_entry->node, - &best_fit_node->node); - best_fit_node->total_q = qmax; - best_fit_node->qbase = qbase; - } else { - /* - * create two extra node to hold the extra queues from this node - */ - struct qdma_resource_entry *new_entry = NULL; - int lqbase = best_fit_node->qbase; - uint32_t lqmax = qbase - best_fit_node->qbase; - - new_entry = qdma_free_entry_create(lqbase, lqmax); - if (new_entry == NULL) - return NULL; - QDMA_LIST_SET_DATA(&new_entry->node, new_entry); - qdma_list_insert_before(&new_entry->node, - &best_fit_node->node); - - best_fit_node->qbase = qbase; - best_fit_node->total_q -= lqmax; - - lqbase = best_fit_node->qbase + qmax; - lqmax = best_fit_node->total_q - qmax; - - new_entry = qdma_free_entry_create(lqbase, lqmax); - if (new_entry == NULL) - return NULL; - QDMA_LIST_SET_DATA(&new_entry->node, new_entry); - qdma_list_insert_after(&new_entry->node, - &best_fit_node->node); - best_fit_node->total_q = qmax; - } - - return best_fit_node; -} - -static int qdma_request_q_resource(struct qdma_dev_entry *dev_entry, - uint32_t new_qmax, int new_qbase, - struct qdma_list_head *free_list_head) -{ - uint32_t qmax = dev_entry->entry.total_q; - int qbase = dev_entry->entry.qbase; - struct qdma_resource_entry *free_entry_node = NULL; - int rv = QDMA_SUCCESS; - - /* submit already allocated queues back to free list before requesting - * new resource - */ - qdma_submit_to_free_list(dev_entry, free_list_head); - - if (!new_qmax) - return 0; - /* check if the request can be accomodated */ - free_entry_node = qdma_get_resource_node(new_qmax, new_qbase, - free_list_head); - if (free_entry_node == NULL) { - /* request cannot be accommodated. Restore the dev_entry */ - free_entry_node = qdma_get_resource_node(qmax, qbase, - free_list_head); - rv = -QDMA_ERR_RM_NO_QUEUES_LEFT; - qdma_log_error("%s: Not enough queues, err:%d\n", __func__, - -QDMA_ERR_RM_NO_QUEUES_LEFT); - if (free_entry_node == NULL) { - dev_entry->entry.qbase = -1; - dev_entry->entry.total_q = 0; - - return rv; - } - } - - dev_entry->entry.qbase = free_entry_node->qbase; - dev_entry->entry.total_q = free_entry_node->total_q; - - qdma_list_del(&free_entry_node->node); - qdma_memfree(free_entry_node); - - return rv; -} - -int qdma_master_resource_create(uint32_t bus_start, uint32_t bus_end, - int q_base, uint32_t total_q, uint32_t *dma_device_index) -{ - struct qdma_resource_master *q_resource; - struct qdma_resource_entry *free_entry; - static int index; - - q_resource = qdma_find_master_resource_entry(bus_start, bus_end); - if (q_resource) { - *dma_device_index = q_resource->dma_device_index; - qdma_log_debug("%s: Resource already created", __func__); - qdma_log_debug("for this device(%d)\n", - q_resource->dma_device_index); - return -QDMA_ERR_RM_RES_EXISTS; - } - - *dma_device_index = index; - - q_resource = (struct qdma_resource_master *)qdma_calloc(1, - sizeof(struct qdma_resource_master)); - if (!q_resource) { - qdma_log_error("%s: no memory for q_resource, err:%d\n", - __func__, - -QDMA_ERR_NO_MEM); - return -QDMA_ERR_NO_MEM; - } - - free_entry = (struct qdma_resource_entry *) - qdma_calloc(1, sizeof(struct qdma_resource_entry)); - if (!free_entry) { - qdma_memfree(q_resource); - qdma_log_error("%s: no memory for free_entry, err:%d\n", - __func__, - -QDMA_ERR_NO_MEM); - return -QDMA_ERR_NO_MEM; - } - - qdma_resource_lock_take(); - q_resource->dma_device_index = index; - q_resource->pci_bus_start = bus_start; - q_resource->pci_bus_end = bus_end; - q_resource->total_q = total_q; - q_resource->qbase = q_base; - qdma_list_init_head(&q_resource->dev_list); - qdma_list_init_head(&q_resource->free_list); - QDMA_LIST_SET_DATA(&q_resource->node, q_resource); - QDMA_LIST_SET_DATA(&q_resource->free_list, q_resource); - qdma_list_add_tail(&q_resource->node, &master_resource_list); - - - free_entry->total_q = total_q; - free_entry->qbase = q_base; - QDMA_LIST_SET_DATA(&free_entry->node, free_entry); - qdma_list_add_tail(&free_entry->node, &q_resource->free_list); - qdma_resource_lock_give(); - - qdma_log_debug("%s: New master resource created at %d", - __func__, index); - ++index; - - return QDMA_SUCCESS; -} - -void qdma_master_resource_destroy(uint32_t dma_device_index) -{ - struct qdma_resource_master *q_resource = - qdma_get_master_resource_entry(dma_device_index); - struct qdma_list_head *entry, *tmp; - - if (!q_resource) - return; - qdma_resource_lock_take(); - if (!qdma_list_is_empty(&q_resource->dev_list)) { - qdma_resource_lock_give(); - return; - } - qdma_list_for_each_safe(entry, tmp, &q_resource->free_list) { - struct qdma_resource_entry *free_entry = - (struct qdma_resource_entry *) - QDMA_LIST_GET_DATA(entry); - - qdma_list_del(&free_entry->node); - qdma_memfree(free_entry); - } - qdma_list_del(&q_resource->node); - qdma_memfree(q_resource); - qdma_resource_lock_give(); -} - - -int qdma_dev_entry_create(uint32_t dma_device_index, uint16_t func_id) -{ - struct qdma_resource_master *q_resource = - qdma_get_master_resource_entry(dma_device_index); - struct qdma_dev_entry *dev_entry; - - if (!q_resource) { - qdma_log_error("%s: Queue resource not found, err: %d\n", - __func__, - -QDMA_ERR_RM_RES_NOT_EXISTS); - return -QDMA_ERR_RM_RES_NOT_EXISTS; - } - - dev_entry = qdma_get_dev_entry(dma_device_index, func_id); - if (!dev_entry) { - qdma_resource_lock_take(); - dev_entry = (struct qdma_dev_entry *) - qdma_calloc(1, sizeof(struct qdma_dev_entry)); - if (dev_entry == NULL) { - qdma_resource_lock_give(); - qdma_log_error("%s: Insufficient memory, err:%d\n", - __func__, - -QDMA_ERR_NO_MEM); - return -QDMA_ERR_NO_MEM; - } - dev_entry->func_id = func_id; - dev_entry->entry.qbase = -1; - dev_entry->entry.total_q = 0; - QDMA_LIST_SET_DATA(&dev_entry->entry.node, dev_entry); - qdma_list_add_tail(&dev_entry->entry.node, - &q_resource->dev_list); - qdma_resource_lock_give(); - qdma_log_info("%s: Created the dev entry successfully\n", - __func__); - } else { - qdma_log_error("%s: Dev entry already created, err = %d\n", - __func__, - -QDMA_ERR_RM_DEV_EXISTS); - return -QDMA_ERR_RM_DEV_EXISTS; - } - - return QDMA_SUCCESS; -} - -void qdma_dev_entry_destroy(uint32_t dma_device_index, uint16_t func_id) -{ - struct qdma_resource_master *q_resource = - qdma_get_master_resource_entry(dma_device_index); - struct qdma_dev_entry *dev_entry; - - if (!q_resource) { - qdma_log_error("%s: Queue resource not found.\n", __func__); - return; - } - - dev_entry = qdma_get_dev_entry(dma_device_index, func_id); - if (!dev_entry) { - qdma_log_error("%s: Dev entry not found\n", __func__); - return; - } - qdma_resource_lock_take(); - qdma_submit_to_free_list(dev_entry, &q_resource->free_list); - - qdma_list_del(&dev_entry->entry.node); - qdma_memfree(dev_entry); - qdma_resource_lock_give(); -} - -int qdma_dev_update(uint32_t dma_device_index, uint16_t func_id, - uint32_t qmax, int *qbase) -{ - struct qdma_resource_master *q_resource = - qdma_get_master_resource_entry(dma_device_index); - struct qdma_dev_entry *dev_entry; - int rv; - - if (!q_resource) { - qdma_log_error("%s: Queue resource not found, err: %d\n", - __func__, -QDMA_ERR_RM_RES_NOT_EXISTS); - return -QDMA_ERR_RM_RES_NOT_EXISTS; - } - - dev_entry = qdma_get_dev_entry(dma_device_index, func_id); - - if (!dev_entry) { - qdma_log_error("%s: Dev Entry not found, err: %d\n", - __func__, - -QDMA_ERR_RM_DEV_NOT_EXISTS); - return -QDMA_ERR_RM_DEV_NOT_EXISTS; - } - - qdma_resource_lock_take(); - - /* if any active queue on device, no more new qmax - * configuration allowed - */ - if (dev_entry->active_h2c_qcnt || - dev_entry->active_c2h_qcnt || - dev_entry->active_cmpt_qcnt) { - qdma_resource_lock_give(); - qdma_log_error("%s: Qs active. Config blocked, err: %d\n", - __func__, -QDMA_ERR_RM_QMAX_CONF_REJECTED); - return -QDMA_ERR_RM_QMAX_CONF_REJECTED; - } - - rv = qdma_request_q_resource(dev_entry, qmax, *qbase, - &q_resource->free_list); - - *qbase = dev_entry->entry.qbase; - qdma_resource_lock_give(); - - - return rv; -} - -int qdma_dev_qinfo_get(uint32_t dma_device_index, uint16_t func_id, - int *qbase, uint32_t *qmax) -{ - struct qdma_resource_master *q_resource = - qdma_get_master_resource_entry(dma_device_index); - struct qdma_dev_entry *dev_entry; - - if (!q_resource) { - qdma_log_error("%s: Queue resource not found, err: %d\n", - __func__, -QDMA_ERR_RM_RES_NOT_EXISTS); - return -QDMA_ERR_RM_RES_NOT_EXISTS; - } - - dev_entry = qdma_get_dev_entry(dma_device_index, func_id); - - if (!dev_entry) { - qdma_log_debug("%s: Dev Entry not created yet\n", __func__); - return -QDMA_ERR_RM_DEV_NOT_EXISTS; - } - - qdma_resource_lock_take(); - *qbase = dev_entry->entry.qbase; - *qmax = dev_entry->entry.total_q; - qdma_resource_lock_give(); - - return QDMA_SUCCESS; -} - -enum qdma_dev_q_range qdma_dev_is_queue_in_range(uint32_t dma_device_index, - uint16_t func_id, - uint32_t qid_hw) -{ - struct qdma_resource_master *q_resource = - qdma_get_master_resource_entry(dma_device_index); - struct qdma_dev_entry *dev_entry; - uint32_t qmax; - - if (!q_resource) { - qdma_log_error("%s: Queue resource not found, err: %d\n", - __func__, -QDMA_ERR_RM_RES_NOT_EXISTS); - return QDMA_DEV_Q_OUT_OF_RANGE; - } - - dev_entry = qdma_get_dev_entry(dma_device_index, func_id); - - if (!dev_entry) { - qdma_log_error("%s: Dev entry not found, err: %d\n", - __func__, -QDMA_ERR_RM_DEV_NOT_EXISTS); - return QDMA_DEV_Q_OUT_OF_RANGE; - } - - qdma_resource_lock_take(); - qmax = dev_entry->entry.qbase + dev_entry->entry.total_q; - if (dev_entry->entry.total_q && (qid_hw < qmax) && - ((int)qid_hw >= dev_entry->entry.qbase)) { - qdma_resource_lock_give(); - return QDMA_DEV_Q_IN_RANGE; - } - qdma_resource_lock_give(); - - return QDMA_DEV_Q_OUT_OF_RANGE; -} - -int qdma_dev_increment_active_queue(uint32_t dma_device_index, uint16_t func_id, - enum qdma_dev_q_type q_type) -{ - struct qdma_resource_master *q_resource = - qdma_get_master_resource_entry(dma_device_index); - struct qdma_dev_entry *dev_entry; - int rv = QDMA_SUCCESS; - uint32_t *active_qcnt = NULL; - - if (!q_resource) { - qdma_log_error("%s: Queue resource not found, err: %d\n", - __func__, -QDMA_ERR_RM_RES_NOT_EXISTS); - return -QDMA_ERR_RM_RES_NOT_EXISTS; - } - - dev_entry = qdma_get_dev_entry(dma_device_index, func_id); - - if (!dev_entry) { - qdma_log_error("%s: Dev Entry not found, err: %d\n", - __func__, - -QDMA_ERR_RM_DEV_NOT_EXISTS); - return -QDMA_ERR_RM_DEV_NOT_EXISTS; - } - - qdma_resource_lock_take(); - switch (q_type) { - case QDMA_DEV_Q_TYPE_H2C: - active_qcnt = &dev_entry->active_h2c_qcnt; - break; - case QDMA_DEV_Q_TYPE_C2H: - active_qcnt = &dev_entry->active_c2h_qcnt; - break; - case QDMA_DEV_Q_TYPE_CMPT: - active_qcnt = &dev_entry->active_cmpt_qcnt; - break; - default: - rv = -QDMA_ERR_RM_DEV_NOT_EXISTS; - } - - if (active_qcnt && (dev_entry->entry.total_q < ((*active_qcnt) + 1))) { - qdma_resource_lock_give(); - return -QDMA_ERR_RM_NO_QUEUES_LEFT; - } - - if (active_qcnt) { - *active_qcnt = (*active_qcnt) + 1; - q_resource->active_qcnt++; - } - qdma_resource_lock_give(); - - return rv; -} - - -int qdma_dev_decrement_active_queue(uint32_t dma_device_index, uint16_t func_id, - enum qdma_dev_q_type q_type) -{ - struct qdma_resource_master *q_resource = - qdma_get_master_resource_entry(dma_device_index); - struct qdma_dev_entry *dev_entry; - int rv = QDMA_SUCCESS; - - if (!q_resource) { - qdma_log_error("%s: Queue resource not found, err: %d\n", - __func__, - -QDMA_ERR_RM_RES_NOT_EXISTS); - return -QDMA_ERR_RM_RES_NOT_EXISTS; - } - - dev_entry = qdma_get_dev_entry(dma_device_index, func_id); - - if (!dev_entry) { - qdma_log_error("%s: Dev entry not found, err: %d\n", - __func__, -QDMA_ERR_RM_DEV_NOT_EXISTS); - return -QDMA_ERR_RM_DEV_NOT_EXISTS; - } - - qdma_resource_lock_take(); - switch (q_type) { - case QDMA_DEV_Q_TYPE_H2C: - if (dev_entry->active_h2c_qcnt) - dev_entry->active_h2c_qcnt--; - break; - case QDMA_DEV_Q_TYPE_C2H: - if (dev_entry->active_c2h_qcnt) - dev_entry->active_c2h_qcnt--; - break; - case QDMA_DEV_Q_TYPE_CMPT: - if (dev_entry->active_cmpt_qcnt) - dev_entry->active_cmpt_qcnt--; - break; - default: - rv = -QDMA_ERR_RM_DEV_NOT_EXISTS; - } - q_resource->active_qcnt--; - qdma_resource_lock_give(); - - return rv; -} - -uint32_t qdma_get_active_queue_count(uint32_t dma_device_index) -{ - struct qdma_resource_master *q_resource = - qdma_get_master_resource_entry(dma_device_index); - uint32_t q_cnt; - - if (!q_resource) - return QDMA_SUCCESS; - - qdma_resource_lock_take(); - q_cnt = q_resource->active_qcnt; - qdma_resource_lock_give(); - - return q_cnt; -} - -int qdma_get_device_active_queue_count(uint32_t dma_device_index, - uint16_t func_id, - enum qdma_dev_q_type q_type) -{ - struct qdma_resource_master *q_resource = - qdma_get_master_resource_entry(dma_device_index); - struct qdma_dev_entry *dev_entry; - uint32_t dev_active_qcnt = 0; - - if (!q_resource) - return -QDMA_ERR_RM_RES_NOT_EXISTS; - - dev_entry = qdma_get_dev_entry(dma_device_index, func_id); - - if (!dev_entry) - return -QDMA_ERR_RM_DEV_NOT_EXISTS; - - qdma_resource_lock_take(); - switch (q_type) { - case QDMA_DEV_Q_TYPE_H2C: - dev_active_qcnt = dev_entry->active_h2c_qcnt; - break; - case QDMA_DEV_Q_TYPE_C2H: - dev_active_qcnt = dev_entry->active_c2h_qcnt; - break; - case QDMA_DEV_Q_TYPE_CMPT: - dev_active_qcnt = dev_entry->active_cmpt_qcnt; - break; - default: - dev_active_qcnt = 0; - } - qdma_resource_lock_give(); - - return dev_active_qcnt; -} diff --git a/QDMA/DPDK/drivers/net/qdma/qdma_access/qdma_resource_mgmt.h b/QDMA/DPDK/drivers/net/qdma/qdma_access/qdma_resource_mgmt.h deleted file mode 100755 index 3361f165f..000000000 --- a/QDMA/DPDK/drivers/net/qdma/qdma_access/qdma_resource_mgmt.h +++ /dev/null @@ -1,230 +0,0 @@ -/* - * Copyright (c) 2019-2022, Xilinx, Inc. All rights reserved. - * Copyright (c) 2022, Advanced Micro Devices, Inc. All rights reserved. - * - * BSD LICENSE - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * * Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#ifndef __QDMA_RESOURCE_MGMT_H_ -#define __QDMA_RESOURCE_MGMT_H_ - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * DOC: QDMA resource management interface definitions - * - * Header file *qdma_resource_mgmt.h* defines data structures and function - * signatures exported for QDMA queue management. - */ - -#include "qdma_platform_env.h" -#include "qdma_access_export.h" - -/** - * enum qdma_dev_q_range: Q ranage check - */ -enum qdma_dev_q_range { - /** @QDMA_DEV_Q_IN_RANGE: Q belongs to dev */ - QDMA_DEV_Q_IN_RANGE, - /** @QDMA_DEV_Q_OUT_OF_RANGE: Q does not belong to dev */ - QDMA_DEV_Q_OUT_OF_RANGE, - /** @QDMA_DEV_Q_RANGE_MAX: total Q validity states */ - QDMA_DEV_Q_RANGE_MAX -}; - -/*****************************************************************************/ -/** - * qdma_master_resource_create(): create the master q resource - * - * @bus_start: Bus number of the device i.e. pdev->bus->number - * @bus_end: Ending bus number i.e. the subordinate bus number of the - * parent bridge - * @q_base: base from which this master resource needs to be created - * @total_q: total queues in this master resource - * @dma_device_index: DMA device identifier assigned by resource manager to - * track the number of devices - * - * A master resource per driver per board is created to manage the queues - * allocated to this driver. - * - * Return: 0 : success and < 0: failure - *****************************************************************************/ -int qdma_master_resource_create(uint32_t bus_start, uint32_t bus_end, - int q_base, uint32_t total_q, uint32_t *dma_device_index); - -/*****************************************************************************/ -/** - * qdma_master_resource_destroy(): destroy the master q resource - * - * @dma_device_index: DMA device identifier this master resource belongs to - * - * Return: None - *****************************************************************************/ -void qdma_master_resource_destroy(uint32_t dma_device_index); - -/*****************************************************************************/ -/** - * qdma_dev_entry_create(): create a device entry for @func_id - * - * @dma_device_index: DMA device identifier that this device belongs to - * @func_id: device identification id - * - * A device entry is to be created on every function probe. - * - * Return: 0 : success and < 0: failure - *****************************************************************************/ -int qdma_dev_entry_create(uint32_t dma_device_index, uint16_t func_id); - -/*****************************************************************************/ -/** - * qdma_dev_entry_destroy(): destroy device entry for @func_id - * - * @dma_device_index: DMA device identifier that this device belongs to - * @func_id: device identification id - * - * Return: None - *****************************************************************************/ -void qdma_dev_entry_destroy(uint32_t dma_device_index, uint16_t func_id); - -/*****************************************************************************/ -/** - * qdma_dev_update(): update qmax for the device - * - * @dma_device_index: DMA device identifier that this device belongs to - * @func_id: device identification id - * @dev_type: device type - * @qmax: qmax for this device - * @qbase: output qbase for this device - * - * This API is to be called for update request of qmax of any function. - * - * Return: 0 : success and < 0: failure - *****************************************************************************/ -int qdma_dev_update(uint32_t dma_device_index, uint16_t func_id, - uint32_t qmax, int *qbase); - -/*****************************************************************************/ -/** - * qdma_dev_qinfo_get(): get device info - * - * @dma_device_index: DMA device identifier that this device belongs to - * @func_id: device identification id - * @dev_type: device type - * @qmax: output qmax for this device - * @qbase: output qbase for this device - * - * This API can be used get the qbase and qmax for any function - * - * Return: 0 : success and < 0: failure - *****************************************************************************/ -int qdma_dev_qinfo_get(uint32_t dma_device_index, uint16_t func_id, - int *qbase, uint32_t *qmax); - -/*****************************************************************************/ -/** - * qdma_dev_is_queue_in_range(): check if queue belongs to this device - * - * @dma_device_index: DMA device identifier that this device belongs to - * @func_id: device identification id - * @qid_hw: hardware queue id - * - * This API checks if the queue ID is in valid range for function specified - * - * Return: @QDMA_DEV_Q_IN_RANGE : valid and - * @QDMA_DEV_Q_OUT_OF_RANGE: invalid - *****************************************************************************/ -enum qdma_dev_q_range qdma_dev_is_queue_in_range(uint32_t dma_device_index, - uint16_t func_id, - uint32_t qid_hw); - -/*****************************************************************************/ -/** - * qdma_dev_increment_active_queue(): increment active queue count - * - * @dma_device_index: DMA device identifier that this device belongs to - * @func_id: device identification id - * @q_type: Queue type i.e. C2H or H2C or CMPT - * - * This API is used to increment the active queue count of this function - * - * Return: 0 : success and < 0: failure - *****************************************************************************/ -int qdma_dev_increment_active_queue(uint32_t dma_device_index, uint16_t func_id, - enum qdma_dev_q_type q_type); - -/*****************************************************************************/ -/** - * qdma_dev_decrement_active_queue(): increment active queue count - * - * @dma_device_index: DMA device identifier that this device belongs to - * @func_id: device identification id - * @q_type: Queue type i.e. C2H or H2C or CMPT - * - * This API is used to increment the active queue count of this function - * - * Return: 0 : success and < 0: failure - *****************************************************************************/ -int qdma_dev_decrement_active_queue(uint32_t dma_device_index, uint16_t func_id, - enum qdma_dev_q_type q_type); - -/*****************************************************************************/ -/** - * qdma_is_active_queue(): check if any queue is active - * - * @dma_device_index: DMA device identifier that this resource belongs to - * - * This API is used to check if any active queue is present. - * - * Return: active queue count - *****************************************************************************/ -uint32_t qdma_get_active_queue_count(uint32_t dma_device_index); - -/*****************************************************************************/ -/** - * qdma_get_device_active_queue_count(): get device active queue count - * - * @dma_device_index: DMA device identifier that this device belongs to - * @func_id: device identification id - * @q_type: Queue type i.e. C2H or H2C or CMPT - * - * This API is used to get the active queue count of this function - * - * Return: 0 : success and < 0: failure - *****************************************************************************/ -int qdma_get_device_active_queue_count(uint32_t dma_device_index, - uint16_t func_id, - enum qdma_dev_q_type q_type); - -#ifdef __cplusplus -} -#endif - -#endif /* __QDMA_RESOURCE_MGMT_H_ */ diff --git a/QDMA/DPDK/drivers/net/qdma/qdma_access/qdma_soft_access/qdma_soft_access.c b/QDMA/DPDK/drivers/net/qdma/qdma_access/qdma_soft_access/qdma_soft_access.c deleted file mode 100755 index 2c14a8587..000000000 --- a/QDMA/DPDK/drivers/net/qdma/qdma_access/qdma_soft_access/qdma_soft_access.c +++ /dev/null @@ -1,6255 +0,0 @@ -/* - * Copyright (c) 2019-2022, Xilinx, Inc. All rights reserved. - * Copyright (c) 2022, Advanced Micro Devices, Inc. All rights reserved. - * - * BSD LICENSE - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * * Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include "qdma_soft_access.h" -#include "qdma_soft_reg.h" -#include "qdma_reg_dump.h" - - -#ifdef ENABLE_WPP_TRACING -#include "qdma_soft_access.tmh" -#endif - -/** QDMA Context array size */ -#define QDMA_FMAP_NUM_WORDS 2 -#define QDMA_SW_CONTEXT_NUM_WORDS 5 -#define QDMA_PFETCH_CONTEXT_NUM_WORDS 2 -#define QDMA_CMPT_CONTEXT_NUM_WORDS 5 -#define QDMA_HW_CONTEXT_NUM_WORDS 2 -#define QDMA_CR_CONTEXT_NUM_WORDS 1 -#define QDMA_IND_INTR_CONTEXT_NUM_WORDS 3 -#define QDMA_REG_IND_CTXT_REG_COUNT 8 - - -#define QDMA_REG_GROUP_1_START_ADDR 0x000 -#define QDMA_REG_GROUP_2_START_ADDR 0x400 -#define QDMA_REG_GROUP_3_START_ADDR 0xB00 -#define QDMA_REG_GROUP_4_START_ADDR 0x1014 - -#define QDMA_DEFAULT_PFCH_STOP_THRESH 256 - -static void qdma_hw_st_h2c_err_process(void *dev_hndl); -static void qdma_hw_st_c2h_err_process(void *dev_hndl); -static void qdma_hw_desc_err_process(void *dev_hndl); -static void qdma_hw_trq_err_process(void *dev_hndl); -static void qdma_hw_ram_sbe_err_process(void *dev_hndl); -static void qdma_hw_ram_dbe_err_process(void *dev_hndl); - -static struct xreg_info qdma_config_regs[] = { - - /* QDMA_TRQ_SEL_GLBL1 (0x00000) */ - {"CFG_BLOCK_ID", - 0x00, 1, 0, 0, 0, 0, - QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, 0, NULL}, - {"CFG_BUSDEV", - 0x04, 1, 0, 0, 0, 0, - QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, 0, NULL}, - {"CFG_PCIE_MAX_PL_SZ", - 0x08, 1, 0, 0, 0, 0, - QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, 0, NULL}, - {"CFG_PCIE_MAX_RDRQ_SZ", - 0x0C, 1, 0, 0, 0, 0, - QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, 0, NULL}, - {"CFG_SYS_ID", - 0x10, 1, 0, 0, 0, 0, - QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, 0, NULL}, - {"CFG_MSI_EN", - 0x14, 1, 0, 0, 0, 0, - QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, 0, NULL}, - {"CFG_PCIE_DATA_WIDTH", - 0x18, 1, 0, 0, 0, 0, - QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, 0, NULL}, - {"CFG_PCIE_CTRL", - 0x1C, 1, 0, 0, 0, 0, - QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, 0, NULL}, - {"CFG_AXI_USR_MAX_PL_SZ", - 0x40, 1, 0, 0, 0, 0, - QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, 0, NULL}, - {"CFG_AXI_USR_MAX_RDRQ_SZ", - 0x44, 1, 0, 0, 0, 0, - QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, 0, NULL}, - {"CFG_MISC_CTRL", - 0x4C, 1, 0, 0, 0, 0, - QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, 0, NULL}, - {"CFG_SCRATCH_REG", - 0x80, 8, 0, 0, 0, 0, - QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, 0, NULL}, - {"QDMA_RAM_SBE_MSK_A", - 0xF0, 1, 0, 0, 0, 0, - QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, 0, NULL}, - {"QDMA_RAM_SBE_STS_A", - 0xF4, 1, 0, 0, 0, 0, - QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, 0, NULL}, - {"QDMA_RAM_DBE_MSK_A", - 0xF8, 1, 0, 0, 0, 0, - QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, 0, NULL}, - {"QDMA_RAM_DBE_STS_A", - 0xFC, 1, 0, 0, 0, 0, - QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, 0, NULL}, - - /* QDMA_TRQ_SEL_GLBL2 (0x00100) */ - {"GLBL2_ID", - 0x100, 1, 0, 0, 0, 0, - QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, 0, NULL}, - {"GLBL2_PF_BL_INT", - 0x104, 1, 0, 0, 0, 0, - QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, 0, NULL}, - {"GLBL2_PF_VF_BL_INT", - 0x108, 1, 0, 0, 0, 0, - QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, 0, NULL}, - {"GLBL2_PF_BL_EXT", - 0x10C, 1, 0, 0, 0, 0, - QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, 0, NULL}, - {"GLBL2_PF_VF_BL_EXT", - 0x110, 1, 0, 0, 0, 0, - QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, 0, NULL}, - {"GLBL2_CHNL_INST", - 0x114, 1, 0, 0, 0, 0, - QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, 0, NULL}, - {"GLBL2_CHNL_QDMA", - 0x118, 1, 0, 0, 0, 0, - QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, 0, NULL}, - {"GLBL2_CHNL_STRM", - 0x11C, 1, 0, 0, 0, 0, - QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, 0, NULL}, - {"GLBL2_QDMA_CAP", - 0x120, 1, 0, 0, 0, 0, - QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, 0, NULL}, - {"GLBL2_PASID_CAP", - 0x128, 1, 0, 0, 0, 0, - QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, 0, NULL}, - {"GLBL2_FUNC_RET", - 0x12C, 1, 0, 0, 0, 0, - QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, 0, NULL}, - {"GLBL2_SYS_ID", - 0x130, 1, 0, 0, 0, 0, - QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, 0, NULL}, - {"GLBL2_MISC_CAP", - 0x134, 1, 0, 0, 0, 0, - QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, 0, NULL}, - {"GLBL2_DBG_PCIE_RQ", - 0x1B8, 2, 0, 0, 0, 0, - QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, 0, NULL}, - {"GLBL2_DBG_AXIMM_WR", - 0x1C0, 2, 0, 0, 0, 0, - QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, 0, NULL}, - {"GLBL2_DBG_AXIMM_RD", - 0x1C8, 2, 0, 0, 0, 0, - QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, 0, NULL}, - - /* QDMA_TRQ_SEL_GLBL (0x00200) */ - {"GLBL_RNGSZ", - 0x204, 16, 1, 0, 0, 0, - QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, 0, NULL}, - {"GLBL_ERR_STAT", - 0x248, 1, 0, 0, 0, 0, - QDMA_MM_ST_MODE, QDMA_REG_READ_PF_VF, 0, NULL}, - {"GLBL_ERR_MASK", - 0x24C, 1, 0, 0, 0, 0, - QDMA_MM_ST_MODE, QDMA_REG_READ_PF_VF, 0, NULL}, - {"GLBL_DSC_CFG", - 0x250, 1, 0, 0, 0, 0, - QDMA_MM_ST_MODE, QDMA_REG_READ_PF_VF, 0, NULL}, - {"GLBL_DSC_ERR_STS", - 0x254, 1, 0, 0, 0, 0, - QDMA_MM_ST_MODE, QDMA_REG_READ_PF_VF, 0, NULL}, - {"GLBL_DSC_ERR_MSK", - 0x258, 1, 0, 0, 0, 0, - QDMA_MM_ST_MODE, QDMA_REG_READ_PF_VF, 0, NULL}, - {"GLBL_DSC_ERR_LOG", - 0x25C, 2, 0, 0, 0, 0, - QDMA_MM_ST_MODE, QDMA_REG_READ_PF_VF, 0, NULL}, - {"GLBL_TRQ_ERR_STS", - 0x264, 1, 0, 0, 0, 0, - QDMA_MM_ST_MODE, QDMA_REG_READ_PF_VF, 0, NULL}, - {"GLBL_TRQ_ERR_MSK", - 0x268, 1, 0, 0, 0, 0, - QDMA_MM_ST_MODE, QDMA_REG_READ_PF_VF, 0, NULL}, - {"GLBL_TRQ_ERR_LOG", - 0x26C, 1, 0, 0, 0, 0, - QDMA_MM_ST_MODE, QDMA_REG_READ_PF_VF, 0, NULL}, - {"GLBL_DSC_DBG_DAT", - 0x270, 2, 0, 0, 0, 0, - QDMA_MM_ST_MODE, QDMA_REG_READ_PF_VF, 0, NULL}, - {"GLBL_DSC_ERR_LOG2", - 0x27C, 1, 0, 0, 0, 0, - QDMA_MM_ST_MODE, QDMA_REG_READ_PF_VF, 0, NULL}, - {"GLBL_INTERRUPT_CFG", - 0x288, 1, 0, 0, 0, 0, - QDMA_MM_ST_MODE, QDMA_REG_READ_PF_VF, 0, NULL}, - - /* QDMA_TRQ_SEL_FMAP (0x00400 - 0x7FC) */ - /* TODO: max 256, display 4 for now */ - {"TRQ_SEL_FMAP", - 0x400, 4, 0, 0, 0, 0, - QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, 0, NULL}, - - /* QDMA_TRQ_SEL_IND (0x00800) */ - {"IND_CTXT_DATA", - 0x804, 8, 0, 0, 0, 0, - QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, 0, NULL}, - {"IND_CTXT_MASK", - 0x824, 8, 0, 0, 0, 0, - QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, 0, NULL}, - {"IND_CTXT_CMD", - 0x844, 1, 0, 0, 0, 0, - QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, 0, NULL}, - - /* QDMA_TRQ_SEL_C2H (0x00A00) */ - {"C2H_TIMER_CNT", - 0xA00, 16, 0, 0, 0, 0, - QDMA_COMPLETION_MODE, QDMA_REG_READ_PF_ONLY, 0, NULL}, - {"C2H_CNT_THRESH", - 0xA40, 16, 0, 0, 0, 0, - QDMA_COMPLETION_MODE, QDMA_REG_READ_PF_ONLY, 0, NULL}, - {"C2H_STAT_S_AXIS_C2H_ACCEPTED", - 0xA88, 1, 0, 0, 0, 0, - QDMA_ST_MODE, QDMA_REG_READ_PF_VF, 0, NULL}, - {"C2H_STAT_S_AXIS_CMPT_ACCEPTED", - 0xA8C, 1, 0, 0, 0, 0, - QDMA_ST_MODE, QDMA_REG_READ_PF_VF, 0, NULL}, - {"C2H_STAT_DESC_RSP_PKT_ACCEPTED", - 0xA90, 1, 0, 0, 0, 0, - QDMA_ST_MODE, QDMA_REG_READ_PF_VF, 0, NULL}, - {"C2H_STAT_AXIS_PKG_CMP", - 0xA94, 1, 0, 0, 0, 0, - QDMA_ST_MODE, QDMA_REG_READ_PF_VF, 0, NULL}, - {"C2H_STAT_DESC_RSP_ACCEPTED", - 0xA98, 1, 0, 0, 0, 0, - QDMA_ST_MODE, QDMA_REG_READ_PF_VF, 0, NULL}, - {"C2H_STAT_DESC_RSP_CMP", - 0xA9C, 1, 0, 0, 0, 0, - QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, 0, NULL}, - {"C2H_STAT_WRQ_OUT", - 0xAA0, 1, 0, 0, 0, 0, - QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, 0, NULL}, - {"C2H_STAT_WPL_REN_ACCEPTED", - 0xAA4, 1, 0, 0, 0, 0, - QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, 0, NULL}, - {"C2H_STAT_TOTAL_WRQ_LEN", - 0xAA8, 1, 0, 0, 0, 0, - QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, 0, NULL}, - {"C2H_STAT_TOTAL_WPL_LEN", - 0xAAC, 1, 0, 0, 0, 0, - QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, 0, NULL}, - {"C2H_BUF_SZ", - 0xAB0, 16, 0, 0, 0, 0, - QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, 0, NULL}, - {"C2H_ERR_STAT", - 0xAF0, 1, 0, 0, 0, 0, - QDMA_ST_MODE, QDMA_REG_READ_PF_VF, 0, NULL}, - {"C2H_ERR_MASK", - 0xAF4, 1, 0, 0, 0, 0, - QDMA_ST_MODE, QDMA_REG_READ_PF_VF, 0, NULL}, - {"C2H_FATAL_ERR_STAT", - 0xAF8, 1, 0, 0, 0, 0, - QDMA_ST_MODE, QDMA_REG_READ_PF_VF, 0, NULL}, - {"C2H_FATAL_ERR_MASK", - 0xAFC, 1, 0, 0, 0, 0, - QDMA_ST_MODE, QDMA_REG_READ_PF_VF, 0, NULL}, - {"C2H_FATAL_ERR_ENABLE", - 0xB00, 1, 0, 0, 0, 0, - QDMA_ST_MODE, QDMA_REG_READ_PF_VF, 0, NULL}, - {"GLBL_ERR_INT", - 0xB04, 1, 0, 0, 0, 0, - QDMA_ST_MODE, QDMA_REG_READ_PF_VF, 0, NULL}, - {"C2H_PFCH_CFG", - 0xB08, 1, 0, 0, 0, 0, - QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, 0, NULL}, - {"C2H_INT_TIMER_TICK", - 0xB0C, 1, 0, 0, 0, 0, - QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, 0, NULL}, - {"C2H_STAT_DESC_RSP_DROP_ACCEPTED", - 0xB10, 1, 0, 0, 0, 0, - QDMA_ST_MODE, QDMA_REG_READ_PF_VF, 0, NULL}, - {"C2H_STAT_DESC_RSP_ERR_ACCEPTED", - 0xB14, 1, 0, 0, 0, 0, - QDMA_ST_MODE, QDMA_REG_READ_PF_VF, 0, NULL}, - {"C2H_STAT_DESC_REQ", - 0xB18, 1, 0, 0, 0, 0, - QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, 0, NULL}, - {"C2H_STAT_DEBUG_DMA_ENG", - 0xB1C, 4, 0, 0, 0, 0, - QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, 0, NULL}, - {"C2H_DBG_PFCH_ERR_CTXT", - 0xB2C, 1, 0, 0, 0, 0, - QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, 0, NULL}, - {"C2H_FIRST_ERR_QID", - 0xB30, 1, 0, 0, 0, 0, - QDMA_ST_MODE, QDMA_REG_READ_PF_VF, 0, NULL}, - {"STAT_NUM_CMPT_IN", - 0xB34, 1, 0, 0, 0, 0, - QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, 0, NULL}, - {"STAT_NUM_CMPT_OUT", - 0xB38, 1, 0, 0, 0, 0, - QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, 0, NULL}, - {"STAT_NUM_CMPT_DRP", - 0xB3C, 1, 0, 0, 0, 0, - QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, 0, NULL}, - {"STAT_NUM_STAT_DESC_OUT", - 0xB40, 1, 0, 0, 0, 0, - QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, 0, NULL}, - {"STAT_NUM_DSC_CRDT_SENT", - 0xB44, 1, 0, 0, 0, 0, - QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, 0, NULL}, - {"STAT_NUM_FCH_DSC_RCVD", - 0xB48, 1, 0, 0, 0, 0, - QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, 0, NULL}, - {"STAT_NUM_BYP_DSC_RCVD", - 0xB4C, 1, 0, 0, 0, 0, - QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, 0, NULL}, - {"C2H_CMPT_COAL_CFG", - 0xB50, 1, 0, 0, 0, 0, - QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, 0, NULL}, - {"C2H_INTR_H2C_REQ", - 0xB54, 1, 0, 0, 0, 0, - QDMA_ST_MODE, QDMA_REG_READ_PF_VF, 0, NULL}, - {"C2H_INTR_C2H_MM_REQ", - 0xB58, 1, 0, 0, 0, 0, - QDMA_ST_MODE, QDMA_REG_READ_PF_VF, 0, NULL}, - {"C2H_INTR_ERR_INT_REQ", - 0xB5C, 1, 0, 0, 0, 0, - QDMA_ST_MODE, QDMA_REG_READ_PF_VF, 0, NULL}, - {"C2H_INTR_C2H_ST_REQ", - 0xB60, 1, 0, 0, 0, 0, - QDMA_ST_MODE, QDMA_REG_READ_PF_VF, 0, NULL}, - {"C2H_INTR_H2C_ERR_MM_MSIX_ACK", - 0xB64, 1, 0, 0, 0, 0, - QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, 0, NULL}, - {"C2H_INTR_H2C_ERR_MM_MSIX_FAIL", - 0xB68, 1, 0, 0, 0, 0, - QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, 0, NULL}, - {"C2H_INTR_H2C_ERR_MM_NO_MSIX", - 0xB6C, 1, 0, 0, 0, 0, - QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, 0, NULL}, - {"C2H_INTR_H2C_ERR_MM_CTXT_INVAL", - 0xB70, 1, 0, 0, 0, 0, - QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, 0, NULL}, - {"C2H_INTR_C2H_ST_MSIX_ACK", - 0xB74, 1, 0, 0, 0, 0, - QDMA_ST_MODE, QDMA_REG_READ_PF_VF, 0, NULL}, - {"C2H_INTR_C2H_ST_MSIX_FAIL", - 0xB78, 1, 0, 0, 0, 0, - QDMA_ST_MODE, QDMA_REG_READ_PF_VF, 0, NULL}, - {"C2H_INTR_C2H_ST_NO_MSIX", - 0xB7C, 1, 0, 0, 0, 0, - QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, 0, NULL}, - {"C2H_INTR_C2H_ST_CTXT_INVAL", - 0xB80, 1, 0, 0, 0, 0, - QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, 0, NULL}, - {"C2H_STAT_WR_CMP", - 0xB84, 1, 0, 0, 0, 0, - QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, 0, NULL}, - {"C2H_STAT_DEBUG_DMA_ENG_4", - 0xB88, 1, 0, 0, 0, 0, - QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, 0, NULL}, - {"C2H_STAT_DEBUG_DMA_ENG_5", - 0xB8C, 1, 0, 0, 0, 0, - QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, 0, NULL}, - {"C2H_DBG_PFCH_QID", - 0xB90, 1, 0, 0, 0, 0, - QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, 0, NULL}, - {"C2H_DBG_PFCH", - 0xB94, 1, 0, 0, 0, 0, - QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, 0, NULL}, - {"C2H_INT_DEBUG", - 0xB98, 1, 0, 0, 0, 0, - QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, 0, NULL}, - {"C2H_STAT_IMM_ACCEPTED", - 0xB9C, 1, 0, 0, 0, 0, - QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, 0, NULL}, - {"C2H_STAT_MARKER_ACCEPTED", - 0xBA0, 1, 0, 0, 0, 0, - QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, 0, NULL}, - {"C2H_STAT_DISABLE_CMP_ACCEPTED", - 0xBA4, 1, 0, 0, 0, 0, - QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, 0, NULL}, - {"C2H_C2H_PAYLOAD_FIFO_CRDT_CNT", - 0xBA8, 1, 0, 0, 0, 0, - QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, 0, NULL}, - {"C2H_INTR_DYN_REQ", - 0xBAC, 1, 0, 0, 0, 0, - QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, 0, NULL}, - {"C2H_INTR_DYN_MSIX", - 0xBB0, 1, 0, 0, 0, 0, - QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, 0, NULL}, - {"C2H_DROP_LEN_MISMATCH", - 0xBB4, 1, 0, 0, 0, 0, - QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, 0, NULL}, - {"C2H_DROP_DESC_RSP_LEN", - 0xBB8, 1, 0, 0, 0, 0, - QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, 0, NULL}, - {"C2H_DROP_QID_FIFO_LEN", - 0xBBC, 1, 0, 0, 0, 0, - QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, 0, NULL}, - {"C2H_DROP_PAYLOAD_CNT", - 0xBC0, 1, 0, 0, 0, 0, - QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, 0, NULL}, - {"QDMA_C2H_CMPT_FORMAT", - 0xBC4, 7, 0, 0, 0, 0, - QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, 0, NULL}, - {"C2H_PFCH_CACHE_DEPTH", - 0xBE0, 1, 0, 0, 0, 0, - QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, 0, NULL}, - {"C2H_CMPT_COAL_BUF_DEPTH", - 0xBE4, 1, 0, 0, 0, 0, - QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, 0, NULL}, - {"C2H_PFCH_CRDT", - 0xBE8, 1, 0, 0, 0, 0, - QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, 0, NULL}, - - /* QDMA_TRQ_SEL_H2C(0x00E00) Register Space*/ - {"H2C_ERR_STAT", - 0xE00, 1, 0, 0, 0, 0, - QDMA_ST_MODE, QDMA_REG_READ_PF_VF, 0, NULL}, - {"H2C_ERR_MASK", - 0xE04, 1, 0, 0, 0, 0, - QDMA_ST_MODE, QDMA_REG_READ_PF_VF, 0, NULL}, - {"H2C_FIRST_ERR_QID", - 0xE08, 1, 0, 0, 0, 0, - QDMA_ST_MODE, QDMA_REG_READ_PF_VF, 0, NULL}, - {"H2C_DBG_REG", - 0xE0C, 5, 0, 0, 0, 0, - QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, 0, NULL}, - {"H2C_FATAL_ERR_EN", - 0xE20, 1, 0, 0, 0, 0, - QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, 0, NULL}, - {"H2C_REQ_THROT", - 0xE24, 1, 0, 0, 0, 0, - QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, 0, NULL}, - {"H2C_ALN_DBG_REG0", - 0xE28, 1, 0, 0, 0, 0, - QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, 0, NULL}, - - /* QDMA_TRQ_SEL_C2H_MM (0x1000) */ - {"C2H_MM_CONTROL", - 0x1004, 3, 0, 0, 0, 0, - QDMA_MM_MODE, QDMA_REG_READ_PF_ONLY, 0, NULL}, - {"C2H_MM_STATUS", - 0x1040, 2, 0, 0, 0, 0, - QDMA_MM_MODE, QDMA_REG_READ_PF_ONLY, 0, NULL}, - {"C2H_MM_CMPL_DSC_CNT", - 0x1048, 1, 0, 0, 0, 0, - QDMA_MM_MODE, QDMA_REG_READ_PF_ONLY, 0, NULL}, - {"C2H_MM_ERR_CODE_EN_MASK", - 0x1054, 1, 0, 0, 0, 0, - QDMA_MM_MODE, QDMA_REG_READ_PF_ONLY, 0, NULL}, - {"C2H_MM_ERR_CODE", - 0x1058, 1, 0, 0, 0, 0, - QDMA_MM_MODE, QDMA_REG_READ_PF_ONLY, 0, NULL}, - {"C2H_MM_ERR_INFO", - 0x105C, 1, 0, 0, 0, 0, - QDMA_MM_MODE, QDMA_REG_READ_PF_ONLY, 0, NULL}, - {"C2H_MM_PERF_MON_CTRL", - 0x10C0, 1, 0, 0, 0, 0, - QDMA_MM_MODE, QDMA_REG_READ_PF_ONLY, 0, NULL}, - {"C2H_MM_PERF_MON_CY_CNT", - 0x10C4, 2, 0, 0, 0, 0, - QDMA_MM_MODE, QDMA_REG_READ_PF_ONLY, 0, NULL}, - {"C2H_MM_PERF_MON_DATA_CNT", - 0x10CC, 2, 0, 0, 0, 0, - QDMA_MM_MODE, QDMA_REG_READ_PF_ONLY, 0, NULL}, - {"C2H_MM_DBG_INFO", - 0x10E8, 2, 0, 0, 0, 0, - QDMA_MM_MODE, QDMA_REG_READ_PF_ONLY, 0, NULL}, - - /* QDMA_TRQ_SEL_H2C_MM (0x1200)*/ - {"H2C_MM_CONTROL", - 0x1204, 3, 0, 0, 0, 0, - QDMA_MM_MODE, QDMA_REG_READ_PF_ONLY, 0, NULL}, - {"H2C_MM_STATUS", - 0x1240, 1, 0, 0, 0, 0, - QDMA_MM_MODE, QDMA_REG_READ_PF_ONLY, 0, NULL}, - {"H2C_MM_CMPL_DSC_CNT", - 0x1248, 1, 0, 0, 0, 0, - QDMA_MM_MODE, QDMA_REG_READ_PF_ONLY, 0, NULL}, - {"H2C_MM_ERR_CODE_EN_MASK", - 0x1254, 1, 0, 0, 0, 0, - QDMA_MM_MODE, QDMA_REG_READ_PF_ONLY, 0, NULL}, - {"H2C_MM_ERR_CODE", - 0x1258, 1, 0, 0, 0, 0, - QDMA_MM_MODE, QDMA_REG_READ_PF_ONLY, 0, NULL}, - {"H2C_MM_ERR_INFO", - 0x125C, 1, 0, 0, 0, 0, - QDMA_MM_MODE, QDMA_REG_READ_PF_ONLY, 0, NULL}, - {"H2C_MM_PERF_MON_CTRL", - 0x12C0, 1, 0, 0, 0, 0, - QDMA_MM_MODE, QDMA_REG_READ_PF_ONLY, 0, NULL}, - {"H2C_MM_PERF_MON_CY_CNT", - 0x12C4, 2, 0, 0, 0, 0, - QDMA_MM_MODE, QDMA_REG_READ_PF_ONLY, 0, NULL}, - {"H2C_MM_PERF_MON_DATA_CNT", - 0x12CC, 2, 0, 0, 0, 0, - QDMA_MM_MODE, QDMA_REG_READ_PF_ONLY, 0, NULL}, - {"H2C_MM_DBG_INFO", - 0x12E8, 1, 0, 0, 0, 0, - QDMA_MM_MODE, QDMA_REG_READ_PF_ONLY, 0, NULL}, - {"H2C_MM_REQ_THROT", - 0x12EC, 1, 0, 0, 0, 0, - QDMA_MM_MODE, QDMA_REG_READ_PF_ONLY, 0, NULL}, - - /* QDMA_PF_MAILBOX (0x2400) */ - {"FUNC_STATUS", - 0x2400, 1, 0, 0, 0, 0, - QDMA_MAILBOX, QDMA_REG_READ_PF_ONLY, 0, NULL}, - {"FUNC_CMD", - 0x2404, 1, 0, 0, 0, 0, - QDMA_MAILBOX, QDMA_REG_READ_PF_ONLY, 0, NULL}, - {"FUNC_INTR_VEC", - 0x2408, 1, 0, 0, 0, 0, - QDMA_MAILBOX, QDMA_REG_READ_PF_ONLY, 0, NULL}, - {"TARGET_FUNC", - 0x240C, 1, 0, 0, 0, 0, - QDMA_MAILBOX, QDMA_REG_READ_PF_ONLY, 0, NULL}, - {"INTR_CTRL", - 0x2410, 1, 0, 0, 0, 0, - QDMA_MAILBOX, QDMA_REG_READ_PF_ONLY, 0, NULL}, - {"PF_ACK", - 0x2420, 8, 0, 0, 0, 0, - QDMA_MAILBOX, QDMA_REG_READ_PF_ONLY, 0, NULL}, - {"FLR_CTRL_STATUS", - 0x2500, 1, 0, 0, 0, 0, - QDMA_MAILBOX, QDMA_REG_READ_PF_ONLY, 0, NULL}, - {"MSG_IN", - 0x2800, 32, 0, 0, 0, 0, - QDMA_MAILBOX, QDMA_REG_READ_PF_ONLY, 0, NULL}, - {"MSG_OUT", - 0x2C00, 32, 0, 0, 0, 0, - QDMA_MAILBOX, QDMA_REG_READ_PF_ONLY, 0, NULL}, - - {"", 0, 0, 0, 0, 0, 0, 0, 0, 0, NULL } -}; - - -static struct qdma_hw_err_info qdma_err_info[QDMA_ERRS_ALL] = { - /* Descriptor errors */ - { - QDMA_DSC_ERR_POISON, - "Poison error", - QDMA_OFFSET_GLBL_DSC_ERR_MASK, - QDMA_OFFSET_GLBL_DSC_ERR_STAT, - QDMA_GLBL_DSC_ERR_POISON_MASK, - QDMA_GLBL_ERR_DSC_MASK, - &qdma_hw_desc_err_process - }, - { - QDMA_DSC_ERR_UR_CA, - "Unsupported request or completer aborted error", - QDMA_OFFSET_GLBL_DSC_ERR_MASK, - QDMA_OFFSET_GLBL_DSC_ERR_STAT, - QDMA_GLBL_DSC_ERR_UR_CA_MASK, - QDMA_GLBL_ERR_DSC_MASK, - &qdma_hw_desc_err_process - }, - { - QDMA_DSC_ERR_PARAM, - "Parameter mismatch error", - QDMA_OFFSET_GLBL_DSC_ERR_MASK, - QDMA_OFFSET_GLBL_DSC_ERR_STAT, - QDMA_GLBL_DSC_ERR_PARAM_MASK, - QDMA_GLBL_ERR_DSC_MASK, - &qdma_hw_desc_err_process - }, - { - QDMA_DSC_ERR_ADDR, - "Address mismatch error", - QDMA_OFFSET_GLBL_DSC_ERR_MASK, - QDMA_OFFSET_GLBL_DSC_ERR_STAT, - QDMA_GLBL_DSC_ERR_ADDR_MASK, - QDMA_GLBL_ERR_DSC_MASK, - &qdma_hw_desc_err_process - }, - { - QDMA_DSC_ERR_TAG, - "Unexpected tag error", - QDMA_OFFSET_GLBL_DSC_ERR_MASK, - QDMA_OFFSET_GLBL_DSC_ERR_STAT, - QDMA_GLBL_DSC_ERR_TAG_MASK, - QDMA_GLBL_ERR_DSC_MASK, - &qdma_hw_desc_err_process - }, - { - QDMA_DSC_ERR_FLR, - "FLR error", - QDMA_OFFSET_GLBL_DSC_ERR_MASK, - QDMA_OFFSET_GLBL_DSC_ERR_STAT, - QDMA_GLBL_DSC_ERR_FLR_MASK, - QDMA_GLBL_ERR_DSC_MASK, - &qdma_hw_desc_err_process - }, - { - QDMA_DSC_ERR_TIMEOUT, - "Timed out error", - QDMA_OFFSET_GLBL_DSC_ERR_MASK, - QDMA_OFFSET_GLBL_DSC_ERR_STAT, - QDMA_GLBL_DSC_ERR_TIMEOUT_MASK, - QDMA_GLBL_ERR_DSC_MASK, - &qdma_hw_desc_err_process - }, - { - QDMA_DSC_ERR_DAT_POISON, - "Poison data error", - QDMA_OFFSET_GLBL_DSC_ERR_MASK, - QDMA_OFFSET_GLBL_DSC_ERR_STAT, - QDMA_GLBL_DSC_ERR_DAT_POISON_MASK, - QDMA_GLBL_ERR_DSC_MASK, - &qdma_hw_desc_err_process - }, - { - QDMA_DSC_ERR_FLR_CANCEL, - "Descriptor fetch cancelled due to FLR error", - QDMA_OFFSET_GLBL_DSC_ERR_MASK, - QDMA_OFFSET_GLBL_DSC_ERR_STAT, - QDMA_GLBL_DSC_ERR_FLR_CANCEL_MASK, - QDMA_GLBL_ERR_DSC_MASK, - &qdma_hw_desc_err_process - }, - { - QDMA_DSC_ERR_DMA, - "DMA engine error", - QDMA_OFFSET_GLBL_DSC_ERR_MASK, - QDMA_OFFSET_GLBL_DSC_ERR_STAT, - QDMA_GLBL_DSC_ERR_DMA_MASK, - QDMA_GLBL_ERR_DSC_MASK, - &qdma_hw_desc_err_process - }, - { - QDMA_DSC_ERR_DSC, - "Invalid PIDX update error", - QDMA_OFFSET_GLBL_DSC_ERR_MASK, - QDMA_OFFSET_GLBL_DSC_ERR_STAT, - QDMA_GLBL_DSC_ERR_DSC_MASK, - QDMA_GLBL_ERR_DSC_MASK, - &qdma_hw_desc_err_process - }, - { - QDMA_DSC_ERR_RQ_CANCEL, - "Descriptor fetch cancelled due to disable register status error", - QDMA_OFFSET_GLBL_DSC_ERR_MASK, - QDMA_OFFSET_GLBL_DSC_ERR_STAT, - QDMA_GLBL_DSC_ERR_RQ_CANCEL_MASK, - QDMA_GLBL_ERR_DSC_MASK, - &qdma_hw_desc_err_process - }, - { - QDMA_DSC_ERR_DBE, - "UNC_ERR_RAM_DBE error", - QDMA_OFFSET_GLBL_DSC_ERR_MASK, - QDMA_OFFSET_GLBL_DSC_ERR_STAT, - QDMA_GLBL_DSC_ERR_DBE_MASK, - QDMA_GLBL_ERR_DSC_MASK, - &qdma_hw_desc_err_process - }, - { - QDMA_DSC_ERR_SBE, - "UNC_ERR_RAM_SBE error", - QDMA_OFFSET_GLBL_DSC_ERR_MASK, - QDMA_OFFSET_GLBL_DSC_ERR_STAT, - QDMA_GLBL_DSC_ERR_SBE_MASK, - QDMA_GLBL_ERR_DSC_MASK, - &qdma_hw_desc_err_process - }, - { - QDMA_DSC_ERR_ALL, - "All Descriptor errors", - QDMA_OFFSET_GLBL_DSC_ERR_MASK, - QDMA_OFFSET_GLBL_DSC_ERR_STAT, - QDMA_GLBL_DSC_ERR_ALL_MASK, - QDMA_GLBL_ERR_DSC_MASK, - &qdma_hw_desc_err_process - }, - - /* TRQ errors */ - { - QDMA_TRQ_ERR_UNMAPPED, - "Access targeted unmapped register space error", - QDMA_OFFSET_GLBL_TRQ_ERR_MASK, - QDMA_OFFSET_GLBL_TRQ_ERR_STAT, - QDMA_GLBL_TRQ_ERR_UNMAPPED_MASK, - QDMA_GLBL_ERR_TRQ_MASK, - &qdma_hw_trq_err_process - }, - { - QDMA_TRQ_ERR_QID_RANGE, - "Qid range error", - QDMA_OFFSET_GLBL_TRQ_ERR_MASK, - QDMA_OFFSET_GLBL_TRQ_ERR_STAT, - QDMA_GLBL_TRQ_ERR_QID_RANGE_MASK, - QDMA_GLBL_ERR_TRQ_MASK, - &qdma_hw_trq_err_process - }, - { - QDMA_TRQ_ERR_VF_ACCESS, - "Invalid VF access error", - QDMA_OFFSET_GLBL_TRQ_ERR_MASK, - QDMA_OFFSET_GLBL_TRQ_ERR_STAT, - QDMA_GLBL_TRQ_ERR_VF_ACCESS_MASK, - QDMA_GLBL_ERR_TRQ_MASK, - &qdma_hw_trq_err_process - }, - { - QDMA_TRQ_ERR_TCP_TIMEOUT, - "Timeout on request error", - QDMA_OFFSET_GLBL_TRQ_ERR_MASK, - QDMA_OFFSET_GLBL_TRQ_ERR_STAT, - QDMA_GLBL_TRQ_ERR_TCP_TIMEOUT_MASK, - QDMA_GLBL_ERR_TRQ_MASK, - &qdma_hw_trq_err_process - }, - { - QDMA_TRQ_ERR_ALL, - "All TRQ errors", - QDMA_OFFSET_GLBL_TRQ_ERR_MASK, - QDMA_OFFSET_GLBL_TRQ_ERR_STAT, - QDMA_GLBL_TRQ_ERR_ALL_MASK, - QDMA_GLBL_ERR_TRQ_MASK, - &qdma_hw_trq_err_process - }, - - /* C2H Errors*/ - { - QDMA_ST_C2H_ERR_MTY_MISMATCH, - "MTY mismatch error", - QDMA_OFFSET_C2H_ERR_MASK, - QDMA_OFFSET_C2H_ERR_STAT, - QDMA_C2H_ERR_MTY_MISMATCH_MASK, - QDMA_GLBL_ERR_ST_C2H_MASK, - &qdma_hw_st_c2h_err_process - }, - { - QDMA_ST_C2H_ERR_LEN_MISMATCH, - "Packet length mismatch error", - QDMA_OFFSET_C2H_ERR_MASK, - QDMA_OFFSET_C2H_ERR_STAT, - QDMA_C2H_ERR_LEN_MISMATCH_MASK, - QDMA_GLBL_ERR_ST_C2H_MASK, - &qdma_hw_st_c2h_err_process - }, - { - QDMA_ST_C2H_ERR_QID_MISMATCH, - "Qid mismatch error", - QDMA_OFFSET_C2H_ERR_MASK, - QDMA_OFFSET_C2H_ERR_STAT, - QDMA_C2H_ERR_QID_MISMATCH_MASK, - QDMA_GLBL_ERR_ST_C2H_MASK, - &qdma_hw_st_c2h_err_process - }, - { - QDMA_ST_C2H_ERR_DESC_RSP_ERR, - "Descriptor error bit set", - QDMA_OFFSET_C2H_ERR_MASK, - QDMA_OFFSET_C2H_ERR_STAT, - QDMA_C2H_ERR_DESC_RSP_ERR_MASK, - QDMA_GLBL_ERR_ST_C2H_MASK, - &qdma_hw_st_c2h_err_process - }, - { - QDMA_ST_C2H_ERR_ENG_WPL_DATA_PAR_ERR, - "Data parity error", - QDMA_OFFSET_C2H_ERR_MASK, - QDMA_OFFSET_C2H_ERR_STAT, - QDMA_C2H_ERR_ENG_WPL_DATA_PAR_ERR_MASK, - QDMA_GLBL_ERR_ST_C2H_MASK, - &qdma_hw_st_c2h_err_process - }, - { - QDMA_ST_C2H_ERR_MSI_INT_FAIL, - "MSI got a fail response error", - QDMA_OFFSET_C2H_ERR_MASK, - QDMA_OFFSET_C2H_ERR_STAT, - QDMA_C2H_ERR_MSI_INT_FAIL_MASK, - QDMA_GLBL_ERR_ST_C2H_MASK, - &qdma_hw_st_c2h_err_process - }, - { - QDMA_ST_C2H_ERR_ERR_DESC_CNT, - "Descriptor count error", - QDMA_OFFSET_C2H_ERR_MASK, - QDMA_OFFSET_C2H_ERR_STAT, - QDMA_C2H_ERR_ERR_DESC_CNT_MASK, - QDMA_GLBL_ERR_ST_C2H_MASK, - &qdma_hw_st_c2h_err_process - }, - { - QDMA_ST_C2H_ERR_PORTID_CTXT_MISMATCH, - "Port id in packet and pfetch ctxt mismatch error", - QDMA_OFFSET_C2H_ERR_MASK, - QDMA_OFFSET_C2H_ERR_STAT, - QDMA_C2H_ERR_PORTID_CTXT_MISMATCH_MASK, - QDMA_GLBL_ERR_ST_C2H_MASK, - &qdma_hw_st_c2h_err_process - }, - { - QDMA_ST_C2H_ERR_PORTID_BYP_IN_MISMATCH, - "Port id in packet and bypass interface mismatch error", - QDMA_OFFSET_C2H_ERR_MASK, - QDMA_OFFSET_C2H_ERR_STAT, - QDMA_C2H_ERR_PORTID_BYP_IN_MISMATCH_MASK, - QDMA_GLBL_ERR_ST_C2H_MASK, - &qdma_hw_st_c2h_err_process - }, - { - QDMA_ST_C2H_ERR_CMPT_INV_Q_ERR, - "Writeback on invalid queue error", - QDMA_OFFSET_C2H_ERR_MASK, - QDMA_OFFSET_C2H_ERR_STAT, - QDMA_C2H_ERR_CMPT_INV_Q_ERR_MASK, - QDMA_GLBL_ERR_ST_C2H_MASK, - &qdma_hw_st_c2h_err_process - }, - { - QDMA_ST_C2H_ERR_CMPT_QFULL_ERR, - "Completion queue gets full error", - QDMA_OFFSET_C2H_ERR_MASK, - QDMA_OFFSET_C2H_ERR_STAT, - QDMA_C2H_ERR_CMPT_QFULL_ERR_MASK, - QDMA_GLBL_ERR_ST_C2H_MASK, - &qdma_hw_st_c2h_err_process - }, - { - QDMA_ST_C2H_ERR_CMPT_CIDX_ERR, - "Bad CIDX update by the software error", - QDMA_OFFSET_C2H_ERR_MASK, - QDMA_OFFSET_C2H_ERR_STAT, - QDMA_C2H_ERR_CMPT_CIDX_ERR_MASK, - QDMA_GLBL_ERR_ST_C2H_MASK, - &qdma_hw_st_c2h_err_process - }, - { - QDMA_ST_C2H_ERR_CMPT_PRTY_ERR, - "C2H completion Parity error", - QDMA_OFFSET_C2H_ERR_MASK, - QDMA_OFFSET_C2H_ERR_STAT, - QDMA_C2H_ERR_CMPT_PRTY_ERR_MASK, - QDMA_GLBL_ERR_ST_C2H_MASK, - &qdma_hw_st_c2h_err_process - }, - { - QDMA_ST_C2H_ERR_ALL, - "All C2h errors", - QDMA_OFFSET_C2H_ERR_MASK, - QDMA_OFFSET_C2H_ERR_STAT, - QDMA_C2H_ERR_ALL_MASK, - QDMA_GLBL_ERR_ST_C2H_MASK, - &qdma_hw_st_c2h_err_process - }, - - /* C2H fatal errors */ - { - QDMA_ST_FATAL_ERR_MTY_MISMATCH, - "Fatal MTY mismatch error", - QDMA_OFFSET_C2H_FATAL_ERR_MASK, - QDMA_OFFSET_C2H_FATAL_ERR_STAT, - QDMA_C2H_FATAL_ERR_MTY_MISMATCH_MASK, - QDMA_GLBL_ERR_ST_C2H_MASK, - &qdma_hw_st_c2h_err_process - }, - { - QDMA_ST_FATAL_ERR_LEN_MISMATCH, - "Fatal Len mismatch error", - QDMA_OFFSET_C2H_FATAL_ERR_MASK, - QDMA_OFFSET_C2H_FATAL_ERR_STAT, - QDMA_C2H_FATAL_ERR_LEN_MISMATCH_MASK, - QDMA_GLBL_ERR_ST_C2H_MASK, - &qdma_hw_st_c2h_err_process - }, - { - QDMA_ST_FATAL_ERR_QID_MISMATCH, - "Fatal Qid mismatch error", - QDMA_OFFSET_C2H_FATAL_ERR_MASK, - QDMA_OFFSET_C2H_FATAL_ERR_STAT, - QDMA_C2H_FATAL_ERR_QID_MISMATCH_MASK, - QDMA_GLBL_ERR_ST_C2H_MASK, - &qdma_hw_st_c2h_err_process - }, - { - QDMA_ST_FATAL_ERR_TIMER_FIFO_RAM_RDBE, - "RAM double bit fatal error", - QDMA_OFFSET_C2H_FATAL_ERR_MASK, - QDMA_OFFSET_C2H_FATAL_ERR_STAT, - QDMA_C2H_FATAL_ERR_TIMER_FIFO_RAM_RDBE_MASK, - QDMA_GLBL_ERR_ST_C2H_MASK, - &qdma_hw_st_c2h_err_process - }, - { - QDMA_ST_FATAL_ERR_PFCH_II_RAM_RDBE, - "RAM double bit fatal error", - QDMA_OFFSET_C2H_FATAL_ERR_MASK, - QDMA_OFFSET_C2H_FATAL_ERR_STAT, - QDMA_C2H_FATAL_ERR_PFCH_II_RAM_RDBE_MASK, - QDMA_GLBL_ERR_ST_C2H_MASK, - &qdma_hw_st_c2h_err_process - }, - { - QDMA_ST_FATAL_ERR_CMPT_CTXT_RAM_RDBE, - "RAM double bit fatal error", - QDMA_OFFSET_C2H_FATAL_ERR_MASK, - QDMA_OFFSET_C2H_FATAL_ERR_STAT, - QDMA_C2H_FATAL_ERR_CMPT_CTXT_RAM_RDBE_MASK, - QDMA_GLBL_ERR_ST_C2H_MASK, - &qdma_hw_st_c2h_err_process - }, - { - QDMA_ST_FATAL_ERR_PFCH_CTXT_RAM_RDBE, - "RAM double bit fatal error", - QDMA_OFFSET_C2H_FATAL_ERR_MASK, - QDMA_OFFSET_C2H_FATAL_ERR_STAT, - QDMA_C2H_FATAL_ERR_PFCH_CTXT_RAM_RDBE_MASK, - QDMA_GLBL_ERR_ST_C2H_MASK, - &qdma_hw_st_c2h_err_process - }, - { - QDMA_ST_FATAL_ERR_DESC_REQ_FIFO_RAM_RDBE, - "RAM double bit fatal error", - QDMA_OFFSET_C2H_FATAL_ERR_MASK, - QDMA_OFFSET_C2H_FATAL_ERR_STAT, - QDMA_C2H_FATAL_ERR_DESC_REQ_FIFO_RAM_RDBE_MASK, - QDMA_GLBL_ERR_ST_C2H_MASK, - &qdma_hw_st_c2h_err_process - }, - { - QDMA_ST_FATAL_ERR_INT_CTXT_RAM_RDBE, - "RAM double bit fatal error", - QDMA_OFFSET_C2H_FATAL_ERR_MASK, - QDMA_OFFSET_C2H_FATAL_ERR_STAT, - QDMA_C2H_FATAL_ERR_INT_CTXT_RAM_RDBE_MASK, - QDMA_GLBL_ERR_ST_C2H_MASK, - &qdma_hw_st_c2h_err_process - }, - { - QDMA_ST_FATAL_ERR_CMPT_COAL_DATA_RAM_RDBE, - "RAM double bit fatal error", - QDMA_OFFSET_C2H_FATAL_ERR_MASK, - QDMA_OFFSET_C2H_FATAL_ERR_STAT, - QDMA_C2H_FATAL_ERR_CMPT_COAL_DATA_RAM_RDBE_MASK, - QDMA_GLBL_ERR_ST_C2H_MASK, - &qdma_hw_st_c2h_err_process - }, - { - QDMA_ST_FATAL_ERR_TUSER_FIFO_RAM_RDBE, - "RAM double bit fatal error", - QDMA_OFFSET_C2H_FATAL_ERR_MASK, - QDMA_OFFSET_C2H_FATAL_ERR_STAT, - QDMA_C2H_FATAL_ERR_TUSER_FIFO_RAM_RDBE_MASK, - QDMA_GLBL_ERR_ST_C2H_MASK, - &qdma_hw_st_c2h_err_process - }, - { - QDMA_ST_FATAL_ERR_QID_FIFO_RAM_RDBE, - "RAM double bit fatal error", - QDMA_OFFSET_C2H_FATAL_ERR_MASK, - QDMA_OFFSET_C2H_FATAL_ERR_STAT, - QDMA_C2H_FATAL_ERR_QID_FIFO_RAM_RDBE_MASK, - QDMA_GLBL_ERR_ST_C2H_MASK, - &qdma_hw_st_c2h_err_process - }, - { - QDMA_ST_FATAL_ERR_PAYLOAD_FIFO_RAM_RDBE, - "RAM double bit fatal error", - QDMA_OFFSET_C2H_FATAL_ERR_MASK, - QDMA_OFFSET_C2H_FATAL_ERR_STAT, - QDMA_C2H_FATAL_ERR_PAYLOAD_FIFO_RAM_RDBE_MASK, - QDMA_GLBL_ERR_ST_C2H_MASK, - &qdma_hw_st_c2h_err_process - }, - { - QDMA_ST_FATAL_ERR_WPL_DATA_PAR, - "RAM double bit fatal error", - QDMA_OFFSET_C2H_FATAL_ERR_MASK, - QDMA_OFFSET_C2H_FATAL_ERR_STAT, - QDMA_C2H_FATAL_ERR_WPL_DATA_PAR_MASK, - QDMA_GLBL_ERR_ST_C2H_MASK, - &qdma_hw_st_c2h_err_process - }, - { - QDMA_ST_FATAL_ERR_ALL, - "All fatal errors", - QDMA_OFFSET_C2H_FATAL_ERR_MASK, - QDMA_OFFSET_C2H_FATAL_ERR_STAT, - QDMA_C2H_FATAL_ERR_ALL_MASK, - QDMA_GLBL_ERR_ST_C2H_MASK, - &qdma_hw_st_c2h_err_process - }, - - /* H2C St errors */ - { - QDMA_ST_H2C_ERR_ZERO_LEN_DESC, - "Zero length descriptor error", - QDMA_OFFSET_H2C_ERR_MASK, - QDMA_OFFSET_H2C_ERR_STAT, - QDMA_H2C_ERR_ZERO_LEN_DESC_MASK, - QDMA_GLBL_ERR_ST_H2C_MASK, - &qdma_hw_st_h2c_err_process - }, - { - QDMA_ST_H2C_ERR_CSI_MOP, - "Non EOP descriptor received error", - QDMA_OFFSET_H2C_ERR_MASK, - QDMA_OFFSET_H2C_ERR_STAT, - QDMA_H2C_ERR_CSI_MOP_MASK, - QDMA_GLBL_ERR_ST_H2C_MASK, - &qdma_hw_st_h2c_err_process - }, - { - QDMA_ST_H2C_ERR_NO_DMA_DSC, - "No DMA descriptor received error", - QDMA_OFFSET_H2C_ERR_MASK, - QDMA_OFFSET_H2C_ERR_STAT, - QDMA_H2C_ERR_NO_DMA_DSC_MASK, - QDMA_GLBL_ERR_ST_H2C_MASK, - &qdma_hw_st_h2c_err_process - }, - { - QDMA_ST_H2C_ERR_SBE, - "Single bit error detected on H2C-ST data error", - QDMA_OFFSET_H2C_ERR_MASK, - QDMA_OFFSET_H2C_ERR_STAT, - QDMA_H2C_ERR_SBE_MASK, - QDMA_GLBL_ERR_ST_H2C_MASK, - &qdma_hw_st_h2c_err_process - }, - { - QDMA_ST_H2C_ERR_DBE, - "Double bit error detected on H2C-ST data error", - QDMA_OFFSET_H2C_ERR_MASK, - QDMA_OFFSET_H2C_ERR_STAT, - QDMA_H2C_ERR_DBE_MASK, - QDMA_GLBL_ERR_ST_H2C_MASK, - &qdma_hw_st_h2c_err_process - }, - { - QDMA_ST_H2C_ERR_ALL, - "All H2C errors", - QDMA_OFFSET_H2C_ERR_MASK, - QDMA_OFFSET_H2C_ERR_STAT, - QDMA_H2C_ERR_ALL_MASK, - QDMA_GLBL_ERR_ST_H2C_MASK, - &qdma_hw_st_h2c_err_process - }, - - /* SBE errors */ - { - QDMA_SBE_ERR_MI_H2C0_DAT, - "H2C MM data buffer single bit ECC error", - QDMA_OFFSET_RAM_SBE_MASK, - QDMA_OFFSET_RAM_SBE_STAT, - QDMA_SBE_ERR_MI_H2C0_DAT_MASK, - QDMA_GLBL_ERR_RAM_SBE_MASK, - &qdma_hw_ram_sbe_err_process - }, - { - QDMA_SBE_ERR_MI_C2H0_DAT, - "C2H MM data buffer single bit ECC error", - QDMA_OFFSET_RAM_SBE_MASK, - QDMA_OFFSET_RAM_SBE_STAT, - QDMA_SBE_ERR_MI_C2H0_DAT_MASK, - QDMA_GLBL_ERR_RAM_SBE_MASK, - &qdma_hw_ram_sbe_err_process - }, - { - QDMA_SBE_ERR_H2C_RD_BRG_DAT, - "Bridge master read single bit ECC error", - QDMA_OFFSET_RAM_SBE_MASK, - QDMA_OFFSET_RAM_SBE_STAT, - QDMA_SBE_ERR_H2C_RD_BRG_DAT_MASK, - QDMA_GLBL_ERR_RAM_SBE_MASK, - &qdma_hw_ram_sbe_err_process - }, - { - QDMA_SBE_ERR_H2C_WR_BRG_DAT, - "Bridge master write single bit ECC error", - QDMA_OFFSET_RAM_SBE_MASK, - QDMA_OFFSET_RAM_SBE_STAT, - QDMA_SBE_ERR_H2C_WR_BRG_DAT_MASK, - QDMA_GLBL_ERR_RAM_SBE_MASK, - &qdma_hw_ram_sbe_err_process - }, - { - QDMA_SBE_ERR_C2H_RD_BRG_DAT, - "Bridge slave read data buffer single bit ECC error", - QDMA_OFFSET_RAM_SBE_MASK, - QDMA_OFFSET_RAM_SBE_STAT, - QDMA_SBE_ERR_C2H_RD_BRG_DAT_MASK, - QDMA_GLBL_ERR_RAM_SBE_MASK, - &qdma_hw_ram_sbe_err_process - }, - { - QDMA_SBE_ERR_C2H_WR_BRG_DAT, - "Bridge slave write data buffer single bit ECC error", - QDMA_OFFSET_RAM_SBE_MASK, - QDMA_OFFSET_RAM_SBE_STAT, - QDMA_SBE_ERR_C2H_WR_BRG_DAT_MASK, - QDMA_GLBL_ERR_RAM_SBE_MASK, - &qdma_hw_ram_sbe_err_process - }, - { - QDMA_SBE_ERR_FUNC_MAP, - "Function map RAM single bit ECC error", - QDMA_OFFSET_RAM_SBE_MASK, - QDMA_OFFSET_RAM_SBE_STAT, - QDMA_SBE_ERR_FUNC_MAP_MASK, - QDMA_GLBL_ERR_RAM_SBE_MASK, - &qdma_hw_ram_sbe_err_process - }, - { - QDMA_SBE_ERR_DSC_HW_CTXT, - "Descriptor engine hardware context RAM single bit ECC error", - QDMA_OFFSET_RAM_SBE_MASK, - QDMA_OFFSET_RAM_SBE_STAT, - QDMA_SBE_ERR_DSC_HW_CTXT_MASK, - QDMA_GLBL_ERR_RAM_SBE_MASK, - &qdma_hw_ram_sbe_err_process - }, - { - QDMA_SBE_ERR_DSC_CRD_RCV, - "Descriptor engine receive credit context RAM single bit ECC error", - QDMA_OFFSET_RAM_SBE_MASK, - QDMA_OFFSET_RAM_SBE_STAT, - QDMA_SBE_ERR_DSC_CRD_RCV_MASK, - QDMA_GLBL_ERR_RAM_SBE_MASK, - &qdma_hw_ram_sbe_err_process - }, - { - QDMA_SBE_ERR_DSC_SW_CTXT, - "Descriptor engine software context RAM single bit ECC error", - QDMA_OFFSET_RAM_SBE_MASK, - QDMA_OFFSET_RAM_SBE_STAT, - QDMA_SBE_ERR_DSC_SW_CTXT_MASK, - QDMA_GLBL_ERR_RAM_SBE_MASK, - &qdma_hw_ram_sbe_err_process - }, - { - QDMA_SBE_ERR_DSC_CPLI, - "Descriptor engine fetch completion information RAM single bit ECC error", - QDMA_OFFSET_RAM_SBE_MASK, - QDMA_OFFSET_RAM_SBE_STAT, - QDMA_SBE_ERR_DSC_CPLI_MASK, - QDMA_GLBL_ERR_RAM_SBE_MASK, - &qdma_hw_ram_sbe_err_process - }, - { - QDMA_SBE_ERR_DSC_CPLD, - "Descriptor engine fetch completion data RAM single bit ECC error", - QDMA_OFFSET_RAM_SBE_MASK, - QDMA_OFFSET_RAM_SBE_STAT, - QDMA_SBE_ERR_DSC_CPLD_MASK, - QDMA_GLBL_ERR_RAM_SBE_MASK, - &qdma_hw_ram_sbe_err_process - }, - { - QDMA_SBE_ERR_PASID_CTXT_RAM, - "PASID configuration RAM single bit ECC error", - QDMA_OFFSET_RAM_SBE_MASK, - QDMA_OFFSET_RAM_SBE_STAT, - QDMA_SBE_ERR_PASID_CTXT_RAM_MASK, - QDMA_GLBL_ERR_RAM_SBE_MASK, - &qdma_hw_ram_sbe_err_process - }, - { - QDMA_SBE_ERR_TIMER_FIFO_RAM, - "Timer fifo RAM single bit ECC error", - QDMA_OFFSET_RAM_SBE_MASK, - QDMA_OFFSET_RAM_SBE_STAT, - QDMA_SBE_ERR_TIMER_FIFO_RAM_MASK, - QDMA_GLBL_ERR_RAM_SBE_MASK, - &qdma_hw_ram_sbe_err_process - }, - { - QDMA_SBE_ERR_PAYLOAD_FIFO_RAM, - "C2H ST payload RAM single bit ECC error", - QDMA_OFFSET_RAM_SBE_MASK, - QDMA_OFFSET_RAM_SBE_STAT, - QDMA_SBE_ERR_PAYLOAD_FIFO_RAM_MASK, - QDMA_GLBL_ERR_RAM_SBE_MASK, - &qdma_hw_ram_sbe_err_process - }, - { - QDMA_SBE_ERR_QID_FIFO_RAM, - "C2H ST QID FIFO RAM single bit ECC error", - QDMA_OFFSET_RAM_SBE_MASK, - QDMA_OFFSET_RAM_SBE_STAT, - QDMA_SBE_ERR_QID_FIFO_RAM_MASK, - QDMA_GLBL_ERR_RAM_SBE_MASK, - &qdma_hw_ram_sbe_err_process - }, - { - QDMA_SBE_ERR_TUSER_FIFO_RAM, - "C2H ST TUSER RAM single bit ECC error", - QDMA_OFFSET_RAM_SBE_MASK, - QDMA_OFFSET_RAM_SBE_STAT, - QDMA_SBE_ERR_TUSER_FIFO_RAM_MASK, - QDMA_GLBL_ERR_RAM_SBE_MASK, - &qdma_hw_ram_sbe_err_process - }, - { - QDMA_SBE_ERR_WRB_COAL_DATA_RAM, - "Completion Coalescing RAM single bit ECC error", - QDMA_OFFSET_RAM_SBE_MASK, - QDMA_OFFSET_RAM_SBE_STAT, - QDMA_SBE_ERR_WRB_COAL_DATA_RAM_MASK, - QDMA_GLBL_ERR_RAM_SBE_MASK, - &qdma_hw_ram_sbe_err_process - }, - { - QDMA_SBE_ERR_INT_QID2VEC_RAM, - "Interrupt QID2VEC RAM single bit ECC error", - QDMA_OFFSET_RAM_SBE_MASK, - QDMA_OFFSET_RAM_SBE_STAT, - QDMA_SBE_ERR_INT_QID2VEC_RAM_MASK, - QDMA_GLBL_ERR_RAM_SBE_MASK, - &qdma_hw_ram_sbe_err_process - }, - { - QDMA_SBE_ERR_INT_CTXT_RAM, - "Interrupt context RAM single bit ECC error", - QDMA_OFFSET_RAM_SBE_MASK, - QDMA_OFFSET_RAM_SBE_STAT, - QDMA_SBE_ERR_INT_CTXT_RAM_MASK, - QDMA_GLBL_ERR_RAM_SBE_MASK, - &qdma_hw_ram_sbe_err_process - }, - { - QDMA_SBE_ERR_DESC_REQ_FIFO_RAM, - "C2H ST descriptor request RAM single bit ECC error", - QDMA_OFFSET_RAM_SBE_MASK, - QDMA_OFFSET_RAM_SBE_STAT, - QDMA_SBE_ERR_DESC_REQ_FIFO_RAM_MASK, - QDMA_GLBL_ERR_RAM_SBE_MASK, - &qdma_hw_ram_sbe_err_process - }, - { - QDMA_SBE_ERR_PFCH_CTXT_RAM, - "C2H ST prefetch RAM single bit ECC error", - QDMA_OFFSET_RAM_SBE_MASK, - QDMA_OFFSET_RAM_SBE_STAT, - QDMA_SBE_ERR_PFCH_CTXT_RAM_MASK, - QDMA_GLBL_ERR_RAM_SBE_MASK, - &qdma_hw_ram_sbe_err_process - }, - { - QDMA_SBE_ERR_WRB_CTXT_RAM, - "C2H ST completion context RAM single bit ECC error", - QDMA_OFFSET_RAM_SBE_MASK, - QDMA_OFFSET_RAM_SBE_STAT, - QDMA_SBE_ERR_WRB_CTXT_RAM_MASK, - QDMA_GLBL_ERR_RAM_SBE_MASK, - &qdma_hw_ram_sbe_err_process - }, - { - QDMA_SBE_ERR_PFCH_LL_RAM, - "C2H ST prefetch list RAM single bit ECC error", - QDMA_OFFSET_RAM_SBE_MASK, - QDMA_OFFSET_RAM_SBE_STAT, - QDMA_SBE_ERR_PFCH_LL_RAM_MASK, - QDMA_GLBL_ERR_RAM_SBE_MASK, - &qdma_hw_ram_sbe_err_process - }, - { - QDMA_SBE_ERR_H2C_PEND_FIFO, - "H2C ST pending fifo RAM single bit ECC error", - QDMA_OFFSET_RAM_SBE_MASK, - QDMA_OFFSET_RAM_SBE_STAT, - QDMA_SBE_ERR_H2C_PEND_FIFO_MASK, - QDMA_GLBL_ERR_RAM_SBE_MASK, - &qdma_hw_ram_sbe_err_process - }, - { - QDMA_SBE_ERR_ALL, - "All SBE errors", - QDMA_OFFSET_RAM_SBE_MASK, - QDMA_OFFSET_RAM_SBE_STAT, - QDMA_SBE_ERR_ALL_MASK, - QDMA_GLBL_ERR_RAM_SBE_MASK, - &qdma_hw_ram_sbe_err_process - }, - - - /* DBE Errors */ - { - QDMA_DBE_ERR_MI_H2C0_DAT, - "H2C MM data buffer double bit ECC error", - QDMA_OFFSET_RAM_DBE_MASK, - QDMA_OFFSET_RAM_DBE_STAT, - QDMA_DBE_ERR_MI_H2C0_DAT_MASK, - QDMA_GLBL_ERR_RAM_DBE_MASK, - &qdma_hw_ram_dbe_err_process - }, - { - QDMA_DBE_ERR_MI_C2H0_DAT, - "C2H MM data buffer double bit ECC error", - QDMA_OFFSET_RAM_DBE_MASK, - QDMA_OFFSET_RAM_DBE_STAT, - QDMA_DBE_ERR_MI_C2H0_DAT_MASK, - QDMA_GLBL_ERR_RAM_DBE_MASK, - &qdma_hw_ram_dbe_err_process - }, - { - QDMA_DBE_ERR_H2C_RD_BRG_DAT, - "Bridge master read double bit ECC error", - QDMA_OFFSET_RAM_DBE_MASK, - QDMA_OFFSET_RAM_DBE_STAT, - QDMA_DBE_ERR_H2C_RD_BRG_DAT_MASK, - QDMA_GLBL_ERR_RAM_DBE_MASK, - &qdma_hw_ram_dbe_err_process - }, - { - QDMA_DBE_ERR_H2C_WR_BRG_DAT, - "Bridge master write double bit ECC error", - QDMA_OFFSET_RAM_DBE_MASK, - QDMA_OFFSET_RAM_DBE_STAT, - QDMA_DBE_ERR_H2C_WR_BRG_DAT_MASK, - QDMA_GLBL_ERR_RAM_DBE_MASK, - &qdma_hw_ram_dbe_err_process - }, - { - QDMA_DBE_ERR_C2H_RD_BRG_DAT, - "Bridge slave read data buffer double bit ECC error", - QDMA_OFFSET_RAM_DBE_MASK, - QDMA_OFFSET_RAM_DBE_STAT, - QDMA_DBE_ERR_C2H_RD_BRG_DAT_MASK, - QDMA_GLBL_ERR_RAM_DBE_MASK, - &qdma_hw_ram_dbe_err_process - }, - { - QDMA_DBE_ERR_C2H_WR_BRG_DAT, - "Bridge slave write data buffer double bit ECC error", - QDMA_OFFSET_RAM_DBE_MASK, - QDMA_OFFSET_RAM_DBE_STAT, - QDMA_DBE_ERR_C2H_WR_BRG_DAT_MASK, - QDMA_GLBL_ERR_RAM_DBE_MASK, - &qdma_hw_ram_dbe_err_process - }, - { - QDMA_DBE_ERR_FUNC_MAP, - "Function map RAM double bit ECC error", - QDMA_OFFSET_RAM_DBE_MASK, - QDMA_OFFSET_RAM_DBE_STAT, - QDMA_DBE_ERR_FUNC_MAP_MASK, - QDMA_GLBL_ERR_RAM_DBE_MASK, - &qdma_hw_ram_dbe_err_process - }, - { - QDMA_DBE_ERR_DSC_HW_CTXT, - "Descriptor engine hardware context RAM double bit ECC error", - QDMA_OFFSET_RAM_DBE_MASK, - QDMA_OFFSET_RAM_DBE_STAT, - QDMA_DBE_ERR_DSC_HW_CTXT_MASK, - QDMA_GLBL_ERR_RAM_DBE_MASK, - &qdma_hw_ram_dbe_err_process - }, - { - QDMA_DBE_ERR_DSC_CRD_RCV, - "Descriptor engine receive credit context RAM double bit ECC error", - QDMA_OFFSET_RAM_DBE_MASK, - QDMA_OFFSET_RAM_DBE_STAT, - QDMA_DBE_ERR_DSC_CRD_RCV_MASK, - QDMA_GLBL_ERR_RAM_DBE_MASK, - &qdma_hw_ram_dbe_err_process - }, - { - QDMA_DBE_ERR_DSC_SW_CTXT, - "Descriptor engine software context RAM double bit ECC error", - QDMA_OFFSET_RAM_DBE_MASK, - QDMA_OFFSET_RAM_DBE_STAT, - QDMA_DBE_ERR_DSC_SW_CTXT_MASK, - QDMA_GLBL_ERR_RAM_DBE_MASK, - &qdma_hw_ram_dbe_err_process - }, - { - QDMA_DBE_ERR_DSC_CPLI, - "Descriptor engine fetch completion information RAM double bit ECC error", - QDMA_OFFSET_RAM_DBE_MASK, - QDMA_OFFSET_RAM_DBE_STAT, - QDMA_DBE_ERR_DSC_CPLI_MASK, - QDMA_GLBL_ERR_RAM_DBE_MASK, - &qdma_hw_ram_dbe_err_process - }, - { - QDMA_DBE_ERR_DSC_CPLD, - "Descriptor engine fetch completion data RAM double bit ECC error", - QDMA_OFFSET_RAM_DBE_MASK, - QDMA_OFFSET_RAM_DBE_STAT, - QDMA_DBE_ERR_DSC_CPLD_MASK, - QDMA_GLBL_ERR_RAM_DBE_MASK, - &qdma_hw_ram_dbe_err_process - }, - { - QDMA_DBE_ERR_PASID_CTXT_RAM, - "PASID configuration RAM double bit ECC error", - QDMA_OFFSET_RAM_DBE_MASK, - QDMA_OFFSET_RAM_DBE_STAT, - QDMA_DBE_ERR_PASID_CTXT_RAM_MASK, - QDMA_GLBL_ERR_RAM_DBE_MASK, - &qdma_hw_ram_dbe_err_process - }, - { - QDMA_DBE_ERR_TIMER_FIFO_RAM, - "Timer fifo RAM double bit ECC error", - QDMA_OFFSET_RAM_DBE_MASK, - QDMA_OFFSET_RAM_DBE_STAT, - QDMA_DBE_ERR_TIMER_FIFO_RAM_MASK, - QDMA_GLBL_ERR_RAM_DBE_MASK, - &qdma_hw_ram_dbe_err_process - }, - { - QDMA_DBE_ERR_PAYLOAD_FIFO_RAM, - "C2H ST payload RAM double bit ECC error", - QDMA_OFFSET_RAM_DBE_MASK, - QDMA_OFFSET_RAM_DBE_STAT, - QDMA_DBE_ERR_PAYLOAD_FIFO_RAM_MASK, - QDMA_GLBL_ERR_RAM_DBE_MASK, - &qdma_hw_ram_dbe_err_process - }, - { - QDMA_DBE_ERR_QID_FIFO_RAM, - "C2H ST QID FIFO RAM double bit ECC error", - QDMA_OFFSET_RAM_DBE_MASK, - QDMA_OFFSET_RAM_DBE_STAT, - QDMA_DBE_ERR_QID_FIFO_RAM_MASK, - QDMA_GLBL_ERR_RAM_DBE_MASK, - &qdma_hw_ram_dbe_err_process - }, - { - QDMA_DBE_ERR_TUSER_FIFO_RAM, - "C2H ST TUSER RAM double bit ECC error", - QDMA_OFFSET_RAM_DBE_MASK, - QDMA_OFFSET_RAM_DBE_STAT, - QDMA_DBE_ERR_TUSER_FIFO_RAM_MASK, - QDMA_GLBL_ERR_RAM_DBE_MASK, - &qdma_hw_ram_dbe_err_process - }, - { - QDMA_DBE_ERR_WRB_COAL_DATA_RAM, - "Completion Coalescing RAM double bit ECC error", - QDMA_OFFSET_RAM_DBE_MASK, - QDMA_OFFSET_RAM_DBE_STAT, - QDMA_DBE_ERR_WRB_COAL_DATA_RAM_MASK, - QDMA_GLBL_ERR_RAM_DBE_MASK, - &qdma_hw_ram_dbe_err_process - }, - { - QDMA_DBE_ERR_INT_QID2VEC_RAM, - "Interrupt QID2VEC RAM double bit ECC error", - QDMA_OFFSET_RAM_DBE_MASK, - QDMA_OFFSET_RAM_DBE_STAT, - QDMA_DBE_ERR_INT_QID2VEC_RAM_MASK, - QDMA_GLBL_ERR_RAM_DBE_MASK, - &qdma_hw_ram_dbe_err_process - }, - { - QDMA_DBE_ERR_INT_CTXT_RAM, - "Interrupt context RAM double bit ECC error", - QDMA_OFFSET_RAM_DBE_MASK, - QDMA_OFFSET_RAM_DBE_STAT, - QDMA_DBE_ERR_INT_CTXT_RAM_MASK, - QDMA_GLBL_ERR_RAM_DBE_MASK, - &qdma_hw_ram_dbe_err_process - }, - { - QDMA_DBE_ERR_DESC_REQ_FIFO_RAM, - "C2H ST descriptor request RAM double bit ECC error", - QDMA_OFFSET_RAM_DBE_MASK, - QDMA_OFFSET_RAM_DBE_STAT, - QDMA_DBE_ERR_DESC_REQ_FIFO_RAM_MASK, - QDMA_GLBL_ERR_RAM_DBE_MASK, - &qdma_hw_ram_dbe_err_process - }, - { - QDMA_DBE_ERR_PFCH_CTXT_RAM, - "C2H ST prefetch RAM double bit ECC error", - QDMA_OFFSET_RAM_DBE_MASK, - QDMA_OFFSET_RAM_DBE_STAT, - QDMA_DBE_ERR_PFCH_CTXT_RAM_MASK, - QDMA_GLBL_ERR_RAM_DBE_MASK, - &qdma_hw_ram_dbe_err_process - }, - { - QDMA_DBE_ERR_WRB_CTXT_RAM, - "C2H ST completion context RAM double bit ECC error", - QDMA_OFFSET_RAM_DBE_MASK, - QDMA_OFFSET_RAM_DBE_STAT, - QDMA_DBE_ERR_WRB_CTXT_RAM_MASK, - QDMA_GLBL_ERR_RAM_DBE_MASK, - &qdma_hw_ram_dbe_err_process - }, - { - QDMA_DBE_ERR_PFCH_LL_RAM, - "C2H ST prefetch list RAM double bit ECC error", - QDMA_OFFSET_RAM_DBE_MASK, - QDMA_OFFSET_RAM_DBE_STAT, - QDMA_DBE_ERR_PFCH_LL_RAM_MASK, - QDMA_GLBL_ERR_RAM_DBE_MASK, - &qdma_hw_ram_dbe_err_process - }, - { - QDMA_DBE_ERR_H2C_PEND_FIFO, - "H2C pending fifo RAM double bit ECC error", - QDMA_OFFSET_RAM_DBE_MASK, - QDMA_OFFSET_RAM_DBE_STAT, - QDMA_DBE_ERR_H2C_PEND_FIFO_MASK, - QDMA_GLBL_ERR_RAM_DBE_MASK, - &qdma_hw_ram_dbe_err_process - }, - { - QDMA_DBE_ERR_ALL, - "All DBE errors", - QDMA_OFFSET_RAM_DBE_MASK, - QDMA_OFFSET_RAM_DBE_STAT, - QDMA_DBE_ERR_ALL_MASK, - QDMA_GLBL_ERR_RAM_DBE_MASK, - &qdma_hw_ram_dbe_err_process - } -}; - -static int32_t all_hw_errs[TOTAL_LEAF_ERROR_AGGREGATORS] = { - - QDMA_DSC_ERR_ALL, - QDMA_TRQ_ERR_ALL, - QDMA_ST_C2H_ERR_ALL, - QDMA_ST_FATAL_ERR_ALL, - QDMA_ST_H2C_ERR_ALL, - QDMA_SBE_ERR_ALL, - QDMA_DBE_ERR_ALL -}; - -static int qdma_indirect_reg_invalidate(void *dev_hndl, - enum ind_ctxt_cmd_sel sel, uint16_t hw_qid); -static int qdma_indirect_reg_clear(void *dev_hndl, - enum ind_ctxt_cmd_sel sel, uint16_t hw_qid); -static int qdma_indirect_reg_read(void *dev_hndl, enum ind_ctxt_cmd_sel sel, - uint16_t hw_qid, uint32_t cnt, uint32_t *data); -static int qdma_indirect_reg_write(void *dev_hndl, enum ind_ctxt_cmd_sel sel, - uint16_t hw_qid, uint32_t *data, uint16_t cnt); - - -static struct qctx_entry sw_ctxt_entries[] = { - {"PIDX", 0}, - {"IRQ Arm", 0}, - {"Function Id", 0}, - {"Queue Enable", 0}, - {"Fetch Credit Enable", 0}, - {"Write back/Intr Check", 0}, - {"Write back/Intr Interval", 0}, - {"Address Translation", 0}, - {"Fetch Max", 0}, - {"Ring Size", 0}, - {"Descriptor Size", 0}, - {"Bypass Enable", 0}, - {"MM Channel", 0}, - {"Writeback Enable", 0}, - {"Interrupt Enable", 0}, - {"Port Id", 0}, - {"Interrupt No Last", 0}, - {"Error", 0}, - {"Writeback Error Sent", 0}, - {"IRQ Request", 0}, - {"Marker Disable", 0}, - {"Is Memory Mapped", 0}, - {"Descriptor Ring Base Addr (Low)", 0}, - {"Descriptor Ring Base Addr (High)", 0}, - {"Interrupt Vector/Ring Index", 0}, - {"Interrupt Aggregation", 0}, -}; - -static struct qctx_entry hw_ctxt_entries[] = { - {"CIDX", 0}, - {"Credits Consumed", 0}, - {"Descriptors Pending", 0}, - {"Queue Invalid No Desc Pending", 0}, - {"Eviction Pending", 0}, - {"Fetch Pending", 0}, -}; - -static struct qctx_entry credit_ctxt_entries[] = { - {"Credit", 0}, -}; - -static struct qctx_entry cmpt_ctxt_entries[] = { - {"Enable Status Desc Update", 0}, - {"Enable Interrupt", 0}, - {"Trigger Mode", 0}, - {"Function Id", 0}, - {"Counter Index", 0}, - {"Timer Index", 0}, - {"Interrupt State", 0}, - {"Color", 0}, - {"Ring Size", 0}, - {"Base Address (Low)", 0}, - {"Base Address (High)", 0}, - {"Descriptor Size", 0}, - {"PIDX", 0}, - {"CIDX", 0}, - {"Valid", 0}, - {"Error", 0}, - {"Trigger Pending", 0}, - {"Timer Running", 0}, - {"Full Update", 0}, - {"Over Flow Check Disable", 0}, - {"Address Translation", 0}, - {"Interrupt Vector/Ring Index", 0}, - {"Interrupt Aggregation", 0}, -}; - -static struct qctx_entry c2h_pftch_ctxt_entries[] = { - {"Bypass", 0}, - {"Buffer Size Index", 0}, - {"Port Id", 0}, - {"Error", 0}, - {"Prefetch Enable", 0}, - {"In Prefetch", 0}, - {"Software Credit", 0}, - {"Valid", 0}, -}; - -static struct qctx_entry fmap_ctxt_entries[] = { - {"Queue Base", 0}, - {"Queue Max", 0}, -}; - -static struct qctx_entry ind_intr_ctxt_entries[] = { - {"valid", 0}, - {"vec", 0}, - {"int_st", 0}, - {"color", 0}, - {"baddr_4k (Low)", 0}, - {"baddr_4k (High)", 0}, - {"page_size", 0}, - {"pidx", 0}, - {"at", 0}, -}; - -uint32_t qdma_soft_reg_dump_buf_len(void) -{ - uint32_t length = ((sizeof(qdma_config_regs) / - sizeof(qdma_config_regs[0])) + 1) * - REG_DUMP_SIZE_PER_LINE; - return length; -} - -uint32_t qdma_get_config_num_regs(void) -{ - return (sizeof(qdma_config_regs)/ - sizeof(qdma_config_regs[0])); -} - -struct xreg_info *qdma_get_config_regs(void) -{ - return qdma_config_regs; -} - -int qdma_soft_context_buf_len(uint8_t st, - enum qdma_dev_q_type q_type, uint32_t *buflen) -{ - uint32_t len = 0; - int rv = 0; - - *buflen = 0; - - if (q_type == QDMA_DEV_Q_TYPE_CMPT) { - len += (((sizeof(cmpt_ctxt_entries) / - sizeof(cmpt_ctxt_entries[0])) + 1) * - REG_DUMP_SIZE_PER_LINE); - } else { - len += (((sizeof(sw_ctxt_entries) / - sizeof(sw_ctxt_entries[0])) + 1) * - REG_DUMP_SIZE_PER_LINE); - - len += (((sizeof(hw_ctxt_entries) / - sizeof(hw_ctxt_entries[0])) + 1) * - REG_DUMP_SIZE_PER_LINE); - - len += (((sizeof(credit_ctxt_entries) / - sizeof(credit_ctxt_entries[0])) + 1) * - REG_DUMP_SIZE_PER_LINE); - - len += (((sizeof(fmap_ctxt_entries) / - sizeof(fmap_ctxt_entries[0])) + 1) * - REG_DUMP_SIZE_PER_LINE); - - if (st && (q_type == QDMA_DEV_Q_TYPE_C2H)) { - len += (((sizeof(cmpt_ctxt_entries) / - sizeof(cmpt_ctxt_entries[0])) + 1) * - REG_DUMP_SIZE_PER_LINE); - - len += (((sizeof(c2h_pftch_ctxt_entries) / - sizeof(c2h_pftch_ctxt_entries[0])) - + 1) * REG_DUMP_SIZE_PER_LINE); - } - } - - *buflen = len; - return rv; -} - -/* - * qdma_acc_fill_sw_ctxt() - Helper function to fill sw context into structure - * - */ -static void qdma_fill_sw_ctxt(struct qdma_descq_sw_ctxt *sw_ctxt) -{ - sw_ctxt_entries[0].value = sw_ctxt->pidx; - sw_ctxt_entries[1].value = sw_ctxt->irq_arm; - sw_ctxt_entries[2].value = sw_ctxt->fnc_id; - sw_ctxt_entries[3].value = sw_ctxt->qen; - sw_ctxt_entries[4].value = sw_ctxt->frcd_en; - sw_ctxt_entries[5].value = sw_ctxt->wbi_chk; - sw_ctxt_entries[6].value = sw_ctxt->wbi_intvl_en; - sw_ctxt_entries[7].value = sw_ctxt->at; - sw_ctxt_entries[8].value = sw_ctxt->fetch_max; - sw_ctxt_entries[9].value = sw_ctxt->rngsz_idx; - sw_ctxt_entries[10].value = sw_ctxt->desc_sz; - sw_ctxt_entries[11].value = sw_ctxt->bypass; - sw_ctxt_entries[12].value = sw_ctxt->mm_chn; - sw_ctxt_entries[13].value = sw_ctxt->wbk_en; - sw_ctxt_entries[14].value = sw_ctxt->irq_en; - sw_ctxt_entries[15].value = sw_ctxt->port_id; - sw_ctxt_entries[16].value = sw_ctxt->irq_no_last; - sw_ctxt_entries[17].value = sw_ctxt->err; - sw_ctxt_entries[18].value = sw_ctxt->err_wb_sent; - sw_ctxt_entries[19].value = sw_ctxt->irq_req; - sw_ctxt_entries[20].value = sw_ctxt->mrkr_dis; - sw_ctxt_entries[21].value = sw_ctxt->is_mm; - sw_ctxt_entries[22].value = sw_ctxt->ring_bs_addr & 0xFFFFFFFF; - sw_ctxt_entries[23].value = - (sw_ctxt->ring_bs_addr >> 32) & 0xFFFFFFFF; - sw_ctxt_entries[24].value = sw_ctxt->vec; - sw_ctxt_entries[25].value = sw_ctxt->intr_aggr; -} - -/* - * qdma_acc_fill_cmpt_ctxt() - Helper function to fill completion context - * into structure - * - */ -static void qdma_fill_cmpt_ctxt(struct qdma_descq_cmpt_ctxt *cmpt_ctxt) -{ - cmpt_ctxt_entries[0].value = cmpt_ctxt->en_stat_desc; - cmpt_ctxt_entries[1].value = cmpt_ctxt->en_int; - cmpt_ctxt_entries[2].value = cmpt_ctxt->trig_mode; - cmpt_ctxt_entries[3].value = cmpt_ctxt->fnc_id; - cmpt_ctxt_entries[4].value = cmpt_ctxt->counter_idx; - cmpt_ctxt_entries[5].value = cmpt_ctxt->timer_idx; - cmpt_ctxt_entries[6].value = cmpt_ctxt->in_st; - cmpt_ctxt_entries[7].value = cmpt_ctxt->color; - cmpt_ctxt_entries[8].value = cmpt_ctxt->ringsz_idx; - cmpt_ctxt_entries[9].value = cmpt_ctxt->bs_addr & 0xFFFFFFFF; - cmpt_ctxt_entries[10].value = - (cmpt_ctxt->bs_addr >> 32) & 0xFFFFFFFF; - cmpt_ctxt_entries[11].value = cmpt_ctxt->desc_sz; - cmpt_ctxt_entries[12].value = cmpt_ctxt->pidx; - cmpt_ctxt_entries[13].value = cmpt_ctxt->cidx; - cmpt_ctxt_entries[14].value = cmpt_ctxt->valid; - cmpt_ctxt_entries[15].value = cmpt_ctxt->err; - cmpt_ctxt_entries[16].value = cmpt_ctxt->user_trig_pend; - cmpt_ctxt_entries[17].value = cmpt_ctxt->timer_running; - cmpt_ctxt_entries[18].value = cmpt_ctxt->full_upd; - cmpt_ctxt_entries[19].value = cmpt_ctxt->ovf_chk_dis; - cmpt_ctxt_entries[20].value = cmpt_ctxt->at; - cmpt_ctxt_entries[21].value = cmpt_ctxt->vec; - cmpt_ctxt_entries[22].value = cmpt_ctxt->int_aggr; -} - -/* - * qdma_acc_fill_hw_ctxt() - Helper function to fill HW context into structure - * - */ -static void qdma_fill_hw_ctxt(struct qdma_descq_hw_ctxt *hw_ctxt) -{ - hw_ctxt_entries[0].value = hw_ctxt->cidx; - hw_ctxt_entries[1].value = hw_ctxt->crd_use; - hw_ctxt_entries[2].value = hw_ctxt->dsc_pend; - hw_ctxt_entries[3].value = hw_ctxt->idl_stp_b; - hw_ctxt_entries[4].value = hw_ctxt->evt_pnd; - hw_ctxt_entries[5].value = hw_ctxt->fetch_pnd; -} - -/* - * qdma_acc_fill_credit_ctxt() - Helper function to fill Credit context - * into structure - * - */ -static void qdma_fill_credit_ctxt(struct qdma_descq_credit_ctxt *cr_ctxt) -{ - credit_ctxt_entries[0].value = cr_ctxt->credit; -} - -/* - * qdma_acc_fill_pfetch_ctxt() - Helper function to fill Prefetch context - * into structure - * - */ -static void qdma_fill_pfetch_ctxt(struct qdma_descq_prefetch_ctxt *pfetch_ctxt) -{ - c2h_pftch_ctxt_entries[0].value = pfetch_ctxt->bypass; - c2h_pftch_ctxt_entries[1].value = pfetch_ctxt->bufsz_idx; - c2h_pftch_ctxt_entries[2].value = pfetch_ctxt->port_id; - c2h_pftch_ctxt_entries[3].value = pfetch_ctxt->err; - c2h_pftch_ctxt_entries[4].value = pfetch_ctxt->pfch_en; - c2h_pftch_ctxt_entries[5].value = pfetch_ctxt->pfch; - c2h_pftch_ctxt_entries[6].value = pfetch_ctxt->sw_crdt; - c2h_pftch_ctxt_entries[7].value = pfetch_ctxt->valid; -} - -/* - * qdma_acc_fill_fmap_ctxt() - Helper function to fill fmap context - * into structure - * - */ -static void qdma_fill_fmap_ctxt(struct qdma_fmap_cfg *fmap_ctxt) -{ - fmap_ctxt_entries[0].value = fmap_ctxt->qbase; - fmap_ctxt_entries[1].value = fmap_ctxt->qmax; -} - -/* - * dump_soft_context() - Helper function to dump queue context into string - * - * return len - length of the string copied into buffer - */ -static int dump_soft_context(struct qdma_descq_context *queue_context, - uint8_t st, enum qdma_dev_q_type q_type, - char *buf, int buf_sz) -{ - int i = 0; - int n; - int len = 0; - int rv; - char banner[DEBGFS_LINE_SZ]; - - if (queue_context == NULL) { - qdma_log_error("%s: queue_context is NULL, err:%d\n", - __func__, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - if (q_type == QDMA_DEV_Q_TYPE_CMPT) { - qdma_fill_cmpt_ctxt(&queue_context->cmpt_ctxt); - } else if (q_type == QDMA_DEV_Q_TYPE_H2C) { - qdma_fill_sw_ctxt(&queue_context->sw_ctxt); - qdma_fill_hw_ctxt(&queue_context->hw_ctxt); - qdma_fill_credit_ctxt(&queue_context->cr_ctxt); - } else if (q_type == QDMA_DEV_Q_TYPE_C2H) { - qdma_fill_sw_ctxt(&queue_context->sw_ctxt); - qdma_fill_hw_ctxt(&queue_context->hw_ctxt); - qdma_fill_credit_ctxt(&queue_context->cr_ctxt); - if (st) { - qdma_fill_pfetch_ctxt(&queue_context->pfetch_ctxt); - qdma_fill_cmpt_ctxt(&queue_context->cmpt_ctxt); - } - } - - qdma_fill_fmap_ctxt(&queue_context->fmap); - - for (i = 0; i < DEBGFS_LINE_SZ - 5; i++) { - rv = QDMA_SNPRINTF_S(banner + i, - (DEBGFS_LINE_SZ - i), - sizeof("-"), "-"); - if ((rv < 0) || (rv > (int)sizeof("-"))) { - qdma_log_error( - "%d:%s QDMA_SNPRINTF_S() failed, err:%d\n", - __LINE__, __func__, - rv); - goto INSUF_BUF_EXIT; - } - } - - if (q_type != QDMA_DEV_Q_TYPE_CMPT) { - /* SW context dump */ - n = sizeof(sw_ctxt_entries) / sizeof((sw_ctxt_entries)[0]); - for (i = 0; i < n; i++) { - if ((len >= buf_sz) || - ((len + DEBGFS_LINE_SZ) >= buf_sz)) - goto INSUF_BUF_EXIT; - - if (i == 0) { - if ((len + (3 * DEBGFS_LINE_SZ)) >= buf_sz) - goto INSUF_BUF_EXIT; - rv = QDMA_SNPRINTF_S(buf + len, (buf_sz - len), - DEBGFS_LINE_SZ, "\n%s", banner); - if ((rv < 0) || (rv > DEBGFS_LINE_SZ)) { - qdma_log_error( - "%d:%s QDMA_SNPRINTF_S() failed, err:%d\n", - __LINE__, __func__, - rv); - goto INSUF_BUF_EXIT; - } - len += rv; - - rv = QDMA_SNPRINTF_S(buf + len, (buf_sz - len), - DEBGFS_LINE_SZ, "\n%40s", "SW Context"); - if ((rv < 0) || (rv > DEBGFS_LINE_SZ)) { - qdma_log_error( - "%d:%s QDMA_SNPRINTF_S() failed, err:%d\n", - __LINE__, __func__, - rv); - goto INSUF_BUF_EXIT; - } - len += rv; - - rv = QDMA_SNPRINTF_S(buf + len, (buf_sz - len), - DEBGFS_LINE_SZ, "\n%s\n", banner); - if ((rv < 0) || (rv > DEBGFS_LINE_SZ)) { - qdma_log_error( - "%d:%s QDMA_SNPRINTF_S() failed, err:%d\n", - __LINE__, __func__, - rv); - goto INSUF_BUF_EXIT; - } - len += rv; - } - - rv = QDMA_SNPRINTF_S(buf + len, - (buf_sz - len), DEBGFS_LINE_SZ, - "%-47s %#-10x %u\n", - sw_ctxt_entries[i].name, - sw_ctxt_entries[i].value, - sw_ctxt_entries[i].value); - if ((rv < 0) || (rv > DEBGFS_LINE_SZ)) { - qdma_log_error( - "%d:%s QDMA_SNPRINTF_S() failed, err:%d\n", - __LINE__, __func__, - rv); - goto INSUF_BUF_EXIT; - } - len += rv; - } - - /* HW context dump */ - n = sizeof(hw_ctxt_entries) / sizeof((hw_ctxt_entries)[0]); - for (i = 0; i < n; i++) { - if ((len >= buf_sz) || - ((len + DEBGFS_LINE_SZ) >= buf_sz)) - goto INSUF_BUF_EXIT; - - if (i == 0) { - if ((len + (3 * DEBGFS_LINE_SZ)) >= buf_sz) - goto INSUF_BUF_EXIT; - - rv = QDMA_SNPRINTF_S(buf + len, (buf_sz - len), - DEBGFS_LINE_SZ, "\n%s", banner); - if ((rv < 0) || (rv > DEBGFS_LINE_SZ)) { - qdma_log_error( - "%d:%s QDMA_SNPRINTF_S() failed, err:%d\n", - __LINE__, __func__, - rv); - goto INSUF_BUF_EXIT; - } - len += rv; - - rv = QDMA_SNPRINTF_S(buf + len, (buf_sz - len), - DEBGFS_LINE_SZ, "\n%40s", "HW Context"); - if ((rv < 0) || (rv > DEBGFS_LINE_SZ)) { - qdma_log_error( - "%d:%s QDMA_SNPRINTF_S() failed, err:%d\n", - __LINE__, __func__, - rv); - goto INSUF_BUF_EXIT; - } - len += rv; - - rv = QDMA_SNPRINTF_S(buf + len, (buf_sz - len), - DEBGFS_LINE_SZ, "\n%s\n", banner); - if ((rv < 0) || (rv > DEBGFS_LINE_SZ)) { - qdma_log_error( - "%d:%s QDMA_SNPRINTF_S() failed, err:%d\n", - __LINE__, __func__, - rv); - goto INSUF_BUF_EXIT; - } - len += rv; - } - - rv = QDMA_SNPRINTF_S(buf + len, - (buf_sz - len), DEBGFS_LINE_SZ, - "%-47s %#-10x %u\n", - hw_ctxt_entries[i].name, - hw_ctxt_entries[i].value, - hw_ctxt_entries[i].value); - if ((rv < 0) || (rv > DEBGFS_LINE_SZ)) { - qdma_log_error( - "%d:%s QDMA_SNPRINTF_S() failed, err:%d\n", - __LINE__, __func__, - rv); - goto INSUF_BUF_EXIT; - } - len += rv; - } - - /* Credit context dump */ - n = sizeof(credit_ctxt_entries) / - sizeof((credit_ctxt_entries)[0]); - for (i = 0; i < n; i++) { - if ((len >= buf_sz) || - ((len + DEBGFS_LINE_SZ) >= buf_sz)) - goto INSUF_BUF_EXIT; - - if (i == 0) { - if ((len + (3 * DEBGFS_LINE_SZ)) >= buf_sz) - goto INSUF_BUF_EXIT; - - rv = QDMA_SNPRINTF_S(buf + len, (buf_sz - len), - DEBGFS_LINE_SZ, "\n%s", banner); - if ((rv < 0) || (rv > DEBGFS_LINE_SZ)) { - qdma_log_error( - "%d:%s QDMA_SNPRINTF_S() failed, err:%d\n", - __LINE__, __func__, - rv); - goto INSUF_BUF_EXIT; - } - len += rv; - - rv = QDMA_SNPRINTF_S(buf + len, (buf_sz - len), - DEBGFS_LINE_SZ, "\n%40s", - "Credit Context"); - if ((rv < 0) || (rv > DEBGFS_LINE_SZ)) { - qdma_log_error( - "%d:%s QDMA_SNPRINTF_S() failed, err:%d\n", - __LINE__, __func__, - rv); - goto INSUF_BUF_EXIT; - } - len += rv; - - rv = QDMA_SNPRINTF_S(buf + len, (buf_sz - len), - DEBGFS_LINE_SZ, "\n%s\n", banner); - if ((rv < 0) || (rv > DEBGFS_LINE_SZ)) { - qdma_log_error( - "%d:%s QDMA_SNPRINTF_S() failed, err:%d\n", - __LINE__, __func__, - rv); - goto INSUF_BUF_EXIT; - } - len += rv; - } - - rv = QDMA_SNPRINTF_S(buf + len, - (buf_sz - len), DEBGFS_LINE_SZ, - "%-47s %#-10x %u\n", - credit_ctxt_entries[i].name, - credit_ctxt_entries[i].value, - credit_ctxt_entries[i].value); - if ((rv < 0) || (rv > DEBGFS_LINE_SZ)) { - qdma_log_error( - "%d:%s QDMA_SNPRINTF_S() failed, err:%d\n", - __LINE__, __func__, - rv); - goto INSUF_BUF_EXIT; - } - len += rv; - } - } - - if ((q_type == QDMA_DEV_Q_TYPE_CMPT) || - (st && q_type == QDMA_DEV_Q_TYPE_C2H)) { - /* Completion context dump */ - n = sizeof(cmpt_ctxt_entries) / sizeof((cmpt_ctxt_entries)[0]); - for (i = 0; i < n; i++) { - if ((len >= buf_sz) || - ((len + DEBGFS_LINE_SZ) >= buf_sz)) - goto INSUF_BUF_EXIT; - - if (i == 0) { - if ((len + (3 * DEBGFS_LINE_SZ)) >= buf_sz) - goto INSUF_BUF_EXIT; - - rv = QDMA_SNPRINTF_S(buf + len, (buf_sz - len), - DEBGFS_LINE_SZ, "\n%s", banner); - if ((rv < 0) || (rv > DEBGFS_LINE_SZ)) { - qdma_log_error( - "%d:%s QDMA_SNPRINTF_S() failed, err:%d\n", - __LINE__, __func__, - rv); - goto INSUF_BUF_EXIT; - } - len += rv; - - rv = QDMA_SNPRINTF_S(buf + len, (buf_sz - len), - DEBGFS_LINE_SZ, "\n%40s", - "Completion Context"); - if ((rv < 0) || (rv > DEBGFS_LINE_SZ)) { - qdma_log_error( - "%d:%s QDMA_SNPRINTF_S() failed, err:%d\n", - __LINE__, __func__, - rv); - goto INSUF_BUF_EXIT; - } - len += rv; - - rv = QDMA_SNPRINTF_S(buf + len, (buf_sz - len), - DEBGFS_LINE_SZ, "\n%s\n", banner); - if ((rv < 0) || (rv > DEBGFS_LINE_SZ)) { - qdma_log_error( - "%d:%s QDMA_SNPRINTF_S() failed, err:%d\n", - __LINE__, __func__, - rv); - goto INSUF_BUF_EXIT; - } - len += rv; - } - - rv = QDMA_SNPRINTF_S(buf + len, - (buf_sz - len), DEBGFS_LINE_SZ, - "%-47s %#-10x %u\n", - cmpt_ctxt_entries[i].name, - cmpt_ctxt_entries[i].value, - cmpt_ctxt_entries[i].value); - if ((rv < 0) || (rv > DEBGFS_LINE_SZ)) { - qdma_log_error( - "%d:%s QDMA_SNPRINTF_S() failed, err:%d\n", - __LINE__, __func__, - rv); - goto INSUF_BUF_EXIT; - } - len += rv; - } - } - - if (st && q_type == QDMA_DEV_Q_TYPE_C2H) { - /* Prefetch context dump */ - n = sizeof(c2h_pftch_ctxt_entries) / - sizeof(c2h_pftch_ctxt_entries[0]); - for (i = 0; i < n; i++) { - if ((len >= buf_sz) || - ((len + DEBGFS_LINE_SZ) >= buf_sz)) - goto INSUF_BUF_EXIT; - - if (i == 0) { - if ((len + (3 * DEBGFS_LINE_SZ)) >= buf_sz) - goto INSUF_BUF_EXIT; - - rv = QDMA_SNPRINTF_S(buf + len, (buf_sz - len), - DEBGFS_LINE_SZ, "\n%s", banner); - if ((rv < 0) || (rv > DEBGFS_LINE_SZ)) { - qdma_log_error( - "%d:%s QDMA_SNPRINTF_S() failed, err:%d\n", - __LINE__, __func__, - rv); - goto INSUF_BUF_EXIT; - } - len += rv; - - rv = QDMA_SNPRINTF_S(buf + len, (buf_sz - len), - DEBGFS_LINE_SZ, "\n%40s", - "Prefetch Context"); - if ((rv < 0) || (rv > DEBGFS_LINE_SZ)) { - qdma_log_error( - "%d:%s QDMA_SNPRINTF_S() failed, err:%d\n", - __LINE__, __func__, - rv); - goto INSUF_BUF_EXIT; - } - len += rv; - - rv = QDMA_SNPRINTF_S(buf + len, (buf_sz - len), - DEBGFS_LINE_SZ, "\n%s\n", banner); - if ((rv < 0) || (rv > DEBGFS_LINE_SZ)) { - qdma_log_error( - "%d:%s QDMA_SNPRINTF_S() failed, err:%d\n", - __LINE__, __func__, - rv); - goto INSUF_BUF_EXIT; - } - len += rv; - } - - rv = QDMA_SNPRINTF_S(buf + len, - (buf_sz - len), DEBGFS_LINE_SZ, - "%-47s %#-10x %u\n", - c2h_pftch_ctxt_entries[i].name, - c2h_pftch_ctxt_entries[i].value, - c2h_pftch_ctxt_entries[i].value); - if ((rv < 0) || (rv > DEBGFS_LINE_SZ)) { - qdma_log_error( - "%d:%s QDMA_SNPRINTF_S() failed, err:%d\n", - __LINE__, __func__, - rv); - goto INSUF_BUF_EXIT; - } - len += rv; - } - } - - /* Fmap context dump */ - n = sizeof(fmap_ctxt_entries) / - sizeof(fmap_ctxt_entries[0]); - for (i = 0; i < n; i++) { - if ((len >= buf_sz) || - ((len + DEBGFS_LINE_SZ) >= buf_sz)) - goto INSUF_BUF_EXIT; - - if (i == 0) { - if ((len + (3 * DEBGFS_LINE_SZ)) >= buf_sz) - goto INSUF_BUF_EXIT; - - rv = QDMA_SNPRINTF_S(buf + len, (buf_sz - len), - DEBGFS_LINE_SZ, "\n%s", banner); - if ((rv < 0) || (rv > DEBGFS_LINE_SZ)) { - qdma_log_error( - "%d:%s QDMA_SNPRINTF_S() failed, err:%d\n", - __LINE__, __func__, - rv); - goto INSUF_BUF_EXIT; - } - len += rv; - - rv = QDMA_SNPRINTF_S(buf + len, (buf_sz - len), - DEBGFS_LINE_SZ, "\n%40s", - "Fmap Context"); - if ((rv < 0) || (rv > DEBGFS_LINE_SZ)) { - qdma_log_error( - "%d:%s QDMA_SNPRINTF_S() failed, err:%d\n", - __LINE__, __func__, - rv); - goto INSUF_BUF_EXIT; - } - len += rv; - - rv = QDMA_SNPRINTF_S(buf + len, (buf_sz - len), - DEBGFS_LINE_SZ, "\n%s\n", banner); - if ((rv < 0) || (rv > DEBGFS_LINE_SZ)) { - qdma_log_error( - "%d:%s QDMA_SNPRINTF_S() failed, err:%d\n", - __LINE__, __func__, - rv); - goto INSUF_BUF_EXIT; - } - len += rv; - } - - rv = QDMA_SNPRINTF_S(buf + len, - (buf_sz - len), DEBGFS_LINE_SZ, - "%-47s %#-10x %u\n", - fmap_ctxt_entries[i].name, - fmap_ctxt_entries[i].value, - fmap_ctxt_entries[i].value); - if ((rv < 0) || (rv > DEBGFS_LINE_SZ)) { - qdma_log_error( - "%d:%s QDMA_SNPRINTF_S() failed, err:%d\n", - __LINE__, __func__, - rv); - goto INSUF_BUF_EXIT; - } - len += rv; - } - - return len; - -INSUF_BUF_EXIT: - if (buf_sz > DEBGFS_LINE_SZ) { - rv = QDMA_SNPRINTF_S((buf + buf_sz - DEBGFS_LINE_SZ), - buf_sz, DEBGFS_LINE_SZ, - "\n\nInsufficient buffer size, partial context dump\n"); - if ((rv < 0) || (rv > DEBGFS_LINE_SZ)) { - qdma_log_error( - "%d:%s QDMA_SNPRINTF_S() failed, err:%d\n", - __LINE__, __func__, - rv); - } - } - - qdma_log_error("%s: Insufficient buffer size, err:%d\n", - __func__, -QDMA_ERR_NO_MEM); - - return -QDMA_ERR_NO_MEM; -} - -/* - * qdma_indirect_reg_invalidate() - helper function to invalidate indirect - * context registers. - * - * return -QDMA_ERR_HWACC_BUSY_TIMEOUT if register - * value didn't match, QDMA_SUCCESS other wise - */ -static int qdma_indirect_reg_invalidate(void *dev_hndl, - enum ind_ctxt_cmd_sel sel, uint16_t hw_qid) -{ - union qdma_ind_ctxt_cmd cmd; - - qdma_reg_access_lock(dev_hndl); - - /* set command register */ - cmd.word = 0; - cmd.bits.qid = hw_qid; - cmd.bits.op = QDMA_CTXT_CMD_INV; - cmd.bits.sel = sel; - qdma_reg_write(dev_hndl, QDMA_OFFSET_IND_CTXT_CMD, cmd.word); - - /* check if the operation went through well */ - if (hw_monitor_reg(dev_hndl, QDMA_OFFSET_IND_CTXT_CMD, - QDMA_IND_CTXT_CMD_BUSY_MASK, 0, - QDMA_REG_POLL_DFLT_INTERVAL_US, - QDMA_REG_POLL_DFLT_TIMEOUT_US)) { - qdma_reg_access_release(dev_hndl); - qdma_log_error("%s: hw_monitor_reg failed with err:%d\n", - __func__, - -QDMA_ERR_HWACC_BUSY_TIMEOUT); - return -QDMA_ERR_HWACC_BUSY_TIMEOUT; - } - - qdma_reg_access_release(dev_hndl); - - return QDMA_SUCCESS; -} - -/* - * qdma_indirect_reg_clear() - helper function to clear indirect - * context registers. - * - * return -QDMA_ERR_HWACC_BUSY_TIMEOUT if register - * value didn't match, QDMA_SUCCESS other wise - */ -static int qdma_indirect_reg_clear(void *dev_hndl, - enum ind_ctxt_cmd_sel sel, uint16_t hw_qid) -{ - union qdma_ind_ctxt_cmd cmd; - - qdma_reg_access_lock(dev_hndl); - - /* set command register */ - cmd.word = 0; - cmd.bits.qid = hw_qid; - cmd.bits.op = QDMA_CTXT_CMD_CLR; - cmd.bits.sel = sel; - qdma_reg_write(dev_hndl, QDMA_OFFSET_IND_CTXT_CMD, cmd.word); - - /* check if the operation went through well */ - if (hw_monitor_reg(dev_hndl, QDMA_OFFSET_IND_CTXT_CMD, - QDMA_IND_CTXT_CMD_BUSY_MASK, 0, - QDMA_REG_POLL_DFLT_INTERVAL_US, - QDMA_REG_POLL_DFLT_TIMEOUT_US)) { - qdma_reg_access_release(dev_hndl); - qdma_log_error("%s: hw_monitor_reg failed with err:%d\n", - __func__, - -QDMA_ERR_HWACC_BUSY_TIMEOUT); - return -QDMA_ERR_HWACC_BUSY_TIMEOUT; - } - - qdma_reg_access_release(dev_hndl); - - return QDMA_SUCCESS; -} - -/* - * qdma_indirect_reg_read() - helper function to read indirect - * context registers. - * - * return -QDMA_ERR_HWACC_BUSY_TIMEOUT if register - * value didn't match, QDMA_SUCCESS other wise - */ -static int qdma_indirect_reg_read(void *dev_hndl, enum ind_ctxt_cmd_sel sel, - uint16_t hw_qid, uint32_t cnt, uint32_t *data) -{ - uint32_t index = 0, reg_addr = QDMA_OFFSET_IND_CTXT_DATA; - union qdma_ind_ctxt_cmd cmd; - - qdma_reg_access_lock(dev_hndl); - - /* set command register */ - cmd.word = 0; - cmd.bits.qid = hw_qid; - cmd.bits.op = QDMA_CTXT_CMD_RD; - cmd.bits.sel = sel; - qdma_reg_write(dev_hndl, QDMA_OFFSET_IND_CTXT_CMD, cmd.word); - - /* check if the operation went through well */ - if (hw_monitor_reg(dev_hndl, QDMA_OFFSET_IND_CTXT_CMD, - QDMA_IND_CTXT_CMD_BUSY_MASK, 0, - QDMA_REG_POLL_DFLT_INTERVAL_US, - QDMA_REG_POLL_DFLT_TIMEOUT_US)) { - qdma_reg_access_release(dev_hndl); - qdma_log_error("%s: hw_monitor_reg failed with err:%d\n", - __func__, - -QDMA_ERR_HWACC_BUSY_TIMEOUT); - return -QDMA_ERR_HWACC_BUSY_TIMEOUT; - } - - for (index = 0; index < cnt; index++, reg_addr += sizeof(uint32_t)) - data[index] = qdma_reg_read(dev_hndl, reg_addr); - - qdma_reg_access_release(dev_hndl); - - return QDMA_SUCCESS; -} - -/* - * qdma_indirect_reg_write() - helper function to write indirect - * context registers. - * - * return -QDMA_ERR_HWACC_BUSY_TIMEOUT if register - * value didn't match, QDMA_SUCCESS other wise - */ -static int qdma_indirect_reg_write(void *dev_hndl, enum ind_ctxt_cmd_sel sel, - uint16_t hw_qid, uint32_t *data, uint16_t cnt) -{ - uint32_t index, reg_addr; - struct qdma_indirect_ctxt_regs regs; - uint32_t *wr_data = (uint32_t *)®s; - - qdma_reg_access_lock(dev_hndl); - - /* write the context data */ - for (index = 0; index < QDMA_IND_CTXT_DATA_NUM_REGS; index++) { - if (index < cnt) - regs.qdma_ind_ctxt_data[index] = data[index]; - else - regs.qdma_ind_ctxt_data[index] = 0; - regs.qdma_ind_ctxt_mask[index] = 0xFFFFFFFF; - } - - regs.cmd.word = 0; - regs.cmd.bits.qid = hw_qid; - regs.cmd.bits.op = QDMA_CTXT_CMD_WR; - regs.cmd.bits.sel = sel; - reg_addr = QDMA_OFFSET_IND_CTXT_DATA; - - for (index = 0; index < ((2 * QDMA_IND_CTXT_DATA_NUM_REGS) + 1); - index++, reg_addr += sizeof(uint32_t)) - qdma_reg_write(dev_hndl, reg_addr, wr_data[index]); - - /* check if the operation went through well */ - if (hw_monitor_reg(dev_hndl, QDMA_OFFSET_IND_CTXT_CMD, - QDMA_IND_CTXT_CMD_BUSY_MASK, 0, - QDMA_REG_POLL_DFLT_INTERVAL_US, - QDMA_REG_POLL_DFLT_TIMEOUT_US)) { - qdma_reg_access_release(dev_hndl); - qdma_log_error("%s: hw_monitor_reg failed with err:%d\n", - __func__, - -QDMA_ERR_HWACC_BUSY_TIMEOUT); - return -QDMA_ERR_HWACC_BUSY_TIMEOUT; - } - - qdma_reg_access_release(dev_hndl); - - return QDMA_SUCCESS; -} - -/*****************************************************************************/ -/** - * qdma_get_version() - Function to get the qdma version - * - * @dev_hndl: device handle - * @is_vf: Whether PF or VF - * @version_info: pointer to hold the version info - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -int qdma_get_version(void *dev_hndl, uint8_t is_vf, - struct qdma_hw_version_info *version_info) -{ - uint32_t reg_val = 0; - uint32_t reg_addr = (is_vf) ? QDMA_OFFSET_VF_VERSION : - QDMA_OFFSET_GLBL2_MISC_CAP; - - if (!dev_hndl) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - reg_val = qdma_reg_read(dev_hndl, reg_addr); - - qdma_fetch_version_details(dev_hndl, is_vf, reg_val, version_info); - - return QDMA_SUCCESS; -} - -/*****************************************************************************/ -/** - * qdma_fmap_write() - create fmap context and program it - * - * @dev_hndl: device handle - * @func_id: function id of the device - * @config: pointer to the fmap data strucutre - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -static int qdma_fmap_write(void *dev_hndl, uint16_t func_id, - const struct qdma_fmap_cfg *config) -{ - uint32_t fmap[QDMA_FMAP_NUM_WORDS] = {0}; - uint16_t num_words_count = 0; - enum ind_ctxt_cmd_sel sel = QDMA_CTXT_SEL_FMAP; - - if (!dev_hndl || !config) { - qdma_log_error("%s: dev_handle=%p fmap=%p NULL, err:%d\n", - __func__, dev_hndl, config, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - qdma_log_debug("%s: func_id=%hu, qbase=%hu, qmax=%hu\n", __func__, - func_id, config->qbase, config->qmax); - fmap[num_words_count++] = - FIELD_SET(QDMA_FMAP_CTXT_W0_QID_MASK, config->qbase); - fmap[num_words_count++] = - FIELD_SET(QDMA_FMAP_CTXT_W1_QID_MAX_MASK, config->qmax); - - return qdma_indirect_reg_write(dev_hndl, sel, func_id, - fmap, num_words_count); -} - -/*****************************************************************************/ -/** - * qdma_fmap_read() - read fmap context - * - * @dev_hndl: device handle - * @func_id: function id of the device - * @config: pointer to the output fmap data - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -static int qdma_fmap_read(void *dev_hndl, uint16_t func_id, - struct qdma_fmap_cfg *config) -{ - int rv = QDMA_SUCCESS; - uint32_t fmap[QDMA_FMAP_NUM_WORDS] = {0}; - enum ind_ctxt_cmd_sel sel = QDMA_CTXT_SEL_FMAP; - - if (!dev_hndl || !config) { - qdma_log_error("%s: dev_handle=%p fmap=%p NULL, err:%d\n", - __func__, dev_hndl, config, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - rv = qdma_indirect_reg_read(dev_hndl, sel, func_id, - QDMA_FMAP_NUM_WORDS, fmap); - if (rv < 0) - return rv; - - config->qbase = FIELD_GET(QDMA_FMAP_CTXT_W0_QID_MASK, fmap[0]); - config->qmax = FIELD_GET(QDMA_FMAP_CTXT_W1_QID_MAX_MASK, fmap[1]); - - qdma_log_debug("%s: func_id=%hu, qbase=%hu, qmax=%hu\n", __func__, - func_id, config->qbase, config->qmax); - - return QDMA_SUCCESS; -} - -/*****************************************************************************/ -/** - * qdma_fmap_clear() - clear fmap context - * - * @dev_hndl: device handle - * @func_id: function id of the device - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -static int qdma_fmap_clear(void *dev_hndl, uint16_t func_id) -{ - enum ind_ctxt_cmd_sel sel = QDMA_CTXT_SEL_FMAP; - - if (!dev_hndl) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", __func__, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - qdma_log_debug("%s: func_id=%hu\n", __func__, func_id); - return qdma_indirect_reg_clear(dev_hndl, sel, func_id); -} - -/*****************************************************************************/ -/** - * qdma_fmap_conf() - configure fmap context - * - * @dev_hndl: device handle - * @func_id: function id of the device - * @config: pointer to the fmap data - * @access_type HW access type (qdma_hw_access_type enum) value - * QDMA_HW_ACCESS_INVALIDATE Not supported - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -int qdma_fmap_conf(void *dev_hndl, uint16_t func_id, - struct qdma_fmap_cfg *config, - enum qdma_hw_access_type access_type) -{ - int rv = QDMA_SUCCESS; - - switch (access_type) { - case QDMA_HW_ACCESS_READ: - rv = qdma_fmap_read(dev_hndl, func_id, config); - break; - case QDMA_HW_ACCESS_WRITE: - rv = qdma_fmap_write(dev_hndl, func_id, config); - break; - case QDMA_HW_ACCESS_CLEAR: - rv = qdma_fmap_clear(dev_hndl, func_id); - break; - case QDMA_HW_ACCESS_INVALIDATE: - default: - qdma_log_error("%s: access_type(%d) invalid, err:%d\n", - __func__, - access_type, - -QDMA_ERR_INV_PARAM); - rv = -QDMA_ERR_INV_PARAM; - break; - } - - return rv; -} - -/*****************************************************************************/ -/** - * qdma_sw_context_write() - create sw context and program it - * - * @dev_hndl: device handle - * @c2h: is c2h queue - * @hw_qid: hardware qid of the queue - * @ctxt: pointer to the SW context data strucutre - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -static int qdma_sw_context_write(void *dev_hndl, uint8_t c2h, - uint16_t hw_qid, - const struct qdma_descq_sw_ctxt *ctxt) -{ - uint32_t sw_ctxt[QDMA_SW_CONTEXT_NUM_WORDS] = {0}; - uint16_t num_words_count = 0; - enum ind_ctxt_cmd_sel sel = c2h ? - QDMA_CTXT_SEL_SW_C2H : QDMA_CTXT_SEL_SW_H2C; - - /* Input args check */ - if (!dev_hndl || !ctxt) { - qdma_log_error("%s: dev_handle=%p sw_ctxt=%p NULL, err:%d\n", - __func__, dev_hndl, ctxt, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - sw_ctxt[num_words_count++] = - FIELD_SET(QDMA_SW_CTXT_W0_PIDX, ctxt->pidx) | - FIELD_SET(QDMA_SW_CTXT_W0_IRQ_ARM_MASK, ctxt->irq_arm) | - FIELD_SET(QDMA_SW_CTXT_W0_FUNC_ID_MASK, ctxt->fnc_id); - - qdma_log_debug("%s: pidx=%x, irq_arm=%x, fnc_id=%x\n", - __func__, ctxt->pidx, ctxt->irq_arm, ctxt->fnc_id); - - sw_ctxt[num_words_count++] = - FIELD_SET(QDMA_SW_CTXT_W1_QEN_MASK, ctxt->qen) | - FIELD_SET(QDMA_SW_CTXT_W1_FCRD_EN_MASK, ctxt->frcd_en) | - FIELD_SET(QDMA_SW_CTXT_W1_WBI_CHK_MASK, ctxt->wbi_chk) | - FIELD_SET(QDMA_SW_CTXT_W1_WB_INT_EN_MASK, ctxt->wbi_intvl_en) | - FIELD_SET(QDMA_SW_CTXT_W1_AT_MASK, ctxt->at) | - FIELD_SET(QDMA_SW_CTXT_W1_FETCH_MAX_MASK, ctxt->fetch_max) | - FIELD_SET(QDMA_SW_CTXT_W1_RNG_SZ_MASK, ctxt->rngsz_idx) | - FIELD_SET(QDMA_SW_CTXT_W1_DSC_SZ_MASK, ctxt->desc_sz) | - FIELD_SET(QDMA_SW_CTXT_W1_BYP_MASK, ctxt->bypass) | - FIELD_SET(QDMA_SW_CTXT_W1_MM_CHN_MASK, ctxt->mm_chn) | - FIELD_SET(QDMA_SW_CTXT_W1_WBK_EN_MASK, ctxt->wbk_en) | - FIELD_SET(QDMA_SW_CTXT_W1_IRQ_EN_MASK, ctxt->irq_en) | - FIELD_SET(QDMA_SW_CTXT_W1_PORT_ID_MASK, ctxt->port_id) | - FIELD_SET(QDMA_SW_CTXT_W1_IRQ_NO_LAST_MASK, ctxt->irq_no_last) | - FIELD_SET(QDMA_SW_CTXT_W1_ERR_MASK, ctxt->err) | - FIELD_SET(QDMA_SW_CTXT_W1_ERR_WB_SENT_MASK, ctxt->err_wb_sent) | - FIELD_SET(QDMA_SW_CTXT_W1_IRQ_REQ_MASK, ctxt->irq_req) | - FIELD_SET(QDMA_SW_CTXT_W1_MRKR_DIS_MASK, ctxt->mrkr_dis) | - FIELD_SET(QDMA_SW_CTXT_W1_IS_MM_MASK, ctxt->is_mm); - - qdma_log_debug("%s: qen=%x, frcd_en=%x, wbi_chk=%x, wbi_intvl_en=%x\n", - __func__, ctxt->qen, ctxt->frcd_en, ctxt->wbi_chk, - ctxt->wbi_intvl_en); - - qdma_log_debug("%s: at=%x, fetch_max=%x, rngsz_idx=%x, desc_sz=%x\n", - __func__, ctxt->at, ctxt->fetch_max, ctxt->rngsz_idx, - ctxt->desc_sz); - - qdma_log_debug("%s: bypass=%x, mm_chn=%x, wbk_en=%x, irq_en=%x\n", - __func__, ctxt->bypass, ctxt->mm_chn, ctxt->wbk_en, - ctxt->irq_en); - - qdma_log_debug("%s: port_id=%x, irq_no_last=%x,err=%x", - __func__, ctxt->port_id, ctxt->irq_no_last, ctxt->err); - qdma_log_debug(", err_wb_sent=%x\n", ctxt->err_wb_sent); - - qdma_log_debug("%s: irq_req=%x, mrkr_dis=%x, is_mm=%x\n", - __func__, ctxt->irq_req, ctxt->mrkr_dis, ctxt->is_mm); - - sw_ctxt[num_words_count++] = ctxt->ring_bs_addr & 0xffffffff; - sw_ctxt[num_words_count++] = (ctxt->ring_bs_addr >> 32) & 0xffffffff; - - sw_ctxt[num_words_count++] = - FIELD_SET(QDMA_SW_CTXT_W4_VEC_MASK, ctxt->vec) | - FIELD_SET(QDMA_SW_CTXT_W4_INTR_AGGR_MASK, ctxt->intr_aggr); - - qdma_log_debug("%s: vec=%x, intr_aggr=%x\n", - __func__, ctxt->vec, ctxt->intr_aggr); - - return qdma_indirect_reg_write(dev_hndl, sel, hw_qid, - sw_ctxt, num_words_count); -} - -/*****************************************************************************/ -/** - * qdma_sw_context_read() - read sw context - * - * @dev_hndl: device handle - * @c2h: is c2h queue - * @hw_qid: hardware qid of the queue - * @ctxt: pointer to the output context data - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -static int qdma_sw_context_read(void *dev_hndl, uint8_t c2h, - uint16_t hw_qid, - struct qdma_descq_sw_ctxt *ctxt) -{ - int rv = QDMA_SUCCESS; - uint32_t sw_ctxt[QDMA_SW_CONTEXT_NUM_WORDS] = {0}; - enum ind_ctxt_cmd_sel sel = c2h ? - QDMA_CTXT_SEL_SW_C2H : QDMA_CTXT_SEL_SW_H2C; - - if (!dev_hndl || !ctxt) { - qdma_log_error("%s: dev_handle=%p sw_ctxt=%p NULL, err:%d\n", - __func__, dev_hndl, ctxt, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - rv = qdma_indirect_reg_read(dev_hndl, sel, hw_qid, - QDMA_SW_CONTEXT_NUM_WORDS, sw_ctxt); - if (rv < 0) - return rv; - - ctxt->pidx = FIELD_GET(QDMA_SW_CTXT_W0_PIDX, sw_ctxt[0]); - ctxt->irq_arm = - (uint8_t)(FIELD_GET(QDMA_SW_CTXT_W0_IRQ_ARM_MASK, sw_ctxt[0])); - ctxt->fnc_id = - (uint8_t)(FIELD_GET(QDMA_SW_CTXT_W0_FUNC_ID_MASK, sw_ctxt[0])); - - qdma_log_debug("%s: pidx=%x, irq_arm=%x, fnc_id=%x", - __func__, ctxt->pidx, ctxt->irq_arm, ctxt->fnc_id); - - ctxt->qen = FIELD_GET(QDMA_SW_CTXT_W1_QEN_MASK, sw_ctxt[1]); - ctxt->frcd_en = FIELD_GET(QDMA_SW_CTXT_W1_FCRD_EN_MASK, sw_ctxt[1]); - ctxt->wbi_chk = FIELD_GET(QDMA_SW_CTXT_W1_WBI_CHK_MASK, sw_ctxt[1]); - ctxt->wbi_intvl_en = - FIELD_GET(QDMA_SW_CTXT_W1_WB_INT_EN_MASK, sw_ctxt[1]); - ctxt->at = FIELD_GET(QDMA_SW_CTXT_W1_AT_MASK, sw_ctxt[1]); - ctxt->fetch_max = - FIELD_GET(QDMA_SW_CTXT_W1_FETCH_MAX_MASK, sw_ctxt[1]); - ctxt->rngsz_idx = - (uint8_t)(FIELD_GET(QDMA_SW_CTXT_W1_RNG_SZ_MASK, sw_ctxt[1])); - ctxt->desc_sz = - (uint8_t)(FIELD_GET(QDMA_SW_CTXT_W1_DSC_SZ_MASK, sw_ctxt[1])); - ctxt->bypass = - (uint8_t)(FIELD_GET(QDMA_SW_CTXT_W1_BYP_MASK, sw_ctxt[1])); - ctxt->mm_chn = - (uint8_t)(FIELD_GET(QDMA_SW_CTXT_W1_MM_CHN_MASK, sw_ctxt[1])); - ctxt->wbk_en = - (uint8_t)(FIELD_GET(QDMA_SW_CTXT_W1_WBK_EN_MASK, sw_ctxt[1])); - ctxt->irq_en = - (uint8_t)(FIELD_GET(QDMA_SW_CTXT_W1_IRQ_EN_MASK, sw_ctxt[1])); - ctxt->port_id = - (uint8_t)(FIELD_GET(QDMA_SW_CTXT_W1_PORT_ID_MASK, sw_ctxt[1])); - ctxt->irq_no_last = - (uint8_t)(FIELD_GET(QDMA_SW_CTXT_W1_IRQ_NO_LAST_MASK, - sw_ctxt[1])); - ctxt->err = - (uint8_t)(FIELD_GET(QDMA_SW_CTXT_W1_ERR_MASK, sw_ctxt[1])); - ctxt->err_wb_sent = - (uint8_t)(FIELD_GET(QDMA_SW_CTXT_W1_ERR_WB_SENT_MASK, - sw_ctxt[1])); - ctxt->irq_req = - (uint8_t)(FIELD_GET(QDMA_SW_CTXT_W1_IRQ_REQ_MASK, sw_ctxt[1])); - ctxt->mrkr_dis = - (uint8_t)(FIELD_GET(QDMA_SW_CTXT_W1_MRKR_DIS_MASK, sw_ctxt[1])); - ctxt->is_mm = - (uint8_t)(FIELD_GET(QDMA_SW_CTXT_W1_IS_MM_MASK, sw_ctxt[1])); - - qdma_log_debug("%s: qen=%x, frcd_en=%x, wbi_chk=%x, wbi_intvl_en=%x\n", - __func__, ctxt->qen, ctxt->frcd_en, ctxt->wbi_chk, - ctxt->wbi_intvl_en); - qdma_log_debug("%s: at=%x, fetch_max=%x, rngsz_idx=%x, desc_sz=%x\n", - __func__, ctxt->at, ctxt->fetch_max, ctxt->rngsz_idx, - ctxt->desc_sz); - qdma_log_debug("%s: bypass=%x, mm_chn=%x, wbk_en=%x, irq_en=%x\n", - __func__, ctxt->bypass, ctxt->mm_chn, ctxt->wbk_en, - ctxt->irq_en); - qdma_log_debug("%s: port_id=%x, irq_no_last=%x,", - __func__, ctxt->port_id, ctxt->irq_no_last); - qdma_log_debug(" err=%x, err_wb_sent=%x\n", - ctxt->err, ctxt->err_wb_sent); - qdma_log_debug("%s: irq_req=%x, mrkr_dis=%x, is_mm=%x\n", - __func__, ctxt->irq_req, ctxt->mrkr_dis, ctxt->is_mm); - - ctxt->ring_bs_addr = ((uint64_t)sw_ctxt[3] << 32) | (sw_ctxt[2]); - - ctxt->vec = FIELD_GET(QDMA_SW_CTXT_W4_VEC_MASK, sw_ctxt[4]); - ctxt->intr_aggr = - (uint8_t)(FIELD_GET(QDMA_SW_CTXT_W4_INTR_AGGR_MASK, - sw_ctxt[4])); - - qdma_log_debug("%s: vec=%x, intr_aggr=%x\n", - __func__, ctxt->vec, ctxt->intr_aggr); - - return QDMA_SUCCESS; -} - -/*****************************************************************************/ -/** - * qdma_sw_context_clear() - clear sw context - * - * @dev_hndl: device handle - * @c2h: is c2h queue - * @hw_qid: hardware qid of the queue - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -static int qdma_sw_context_clear(void *dev_hndl, uint8_t c2h, - uint16_t hw_qid) -{ - enum ind_ctxt_cmd_sel sel = c2h ? - QDMA_CTXT_SEL_SW_C2H : QDMA_CTXT_SEL_SW_H2C; - - if (!dev_hndl) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", __func__, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - return qdma_indirect_reg_clear(dev_hndl, sel, hw_qid); -} - -/*****************************************************************************/ -/** - * qdma_sw_context_invalidate() - invalidate sw context - * - * @dev_hndl: device handle - * @c2h: is c2h queue - * @hw_qid: hardware qid of the queue - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -static int qdma_sw_context_invalidate(void *dev_hndl, uint8_t c2h, - uint16_t hw_qid) -{ - enum ind_ctxt_cmd_sel sel = c2h ? - QDMA_CTXT_SEL_SW_C2H : QDMA_CTXT_SEL_SW_H2C; - - if (!dev_hndl) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", __func__, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - return qdma_indirect_reg_invalidate(dev_hndl, sel, hw_qid); -} - -/*****************************************************************************/ -/** - * qdma_sw_ctx_conf() - configure SW context - * - * @dev_hndl: device handle - * @c2h: is c2h queue - * @hw_qid: hardware qid of the queue - * @ctxt: pointer to the context data - * @access_type HW access type (qdma_hw_access_type enum) value - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -int qdma_sw_ctx_conf(void *dev_hndl, uint8_t c2h, uint16_t hw_qid, - struct qdma_descq_sw_ctxt *ctxt, - enum qdma_hw_access_type access_type) -{ - int rv = QDMA_SUCCESS; - - /** ctxt requires only H2C-0 or C2H-1 - * return error for any other values - */ - if (c2h > 1) { - qdma_log_error("%s: c2h(%d) invalid, err:%d\n", - __func__, - c2h, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - switch (access_type) { - case QDMA_HW_ACCESS_READ: - rv = qdma_sw_context_read(dev_hndl, c2h, hw_qid, ctxt); - break; - case QDMA_HW_ACCESS_WRITE: - rv = qdma_sw_context_write(dev_hndl, c2h, hw_qid, ctxt); - break; - case QDMA_HW_ACCESS_CLEAR: - rv = qdma_sw_context_clear(dev_hndl, c2h, hw_qid); - break; - case QDMA_HW_ACCESS_INVALIDATE: - rv = qdma_sw_context_invalidate(dev_hndl, c2h, hw_qid); - break; - default: - qdma_log_error("%s: access_type(%d) invalid, err:%d\n", - __func__, - access_type, - -QDMA_ERR_INV_PARAM); - rv = -QDMA_ERR_INV_PARAM; - break; - } - - return rv; -} - -/*****************************************************************************/ -/** - * qdma_pfetch_context_write() - create prefetch context and program it - * - * @dev_hndl: device handle - * @hw_qid: hardware qid of the queue - * @ctxt: pointer to the prefetch context data strucutre - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -static int qdma_pfetch_context_write(void *dev_hndl, uint16_t hw_qid, - const struct qdma_descq_prefetch_ctxt *ctxt) -{ - uint32_t pfetch_ctxt[QDMA_PFETCH_CONTEXT_NUM_WORDS] = {0}; - enum ind_ctxt_cmd_sel sel = QDMA_CTXT_SEL_PFTCH; - uint32_t sw_crdt_l, sw_crdt_h; - uint16_t num_words_count = 0; - - if (!dev_hndl || !ctxt) { - qdma_log_error("%s: dev_handle or pfetch ctxt NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - sw_crdt_l = - FIELD_GET(QDMA_PFTCH_CTXT_SW_CRDT_GET_L_MASK, ctxt->sw_crdt); - sw_crdt_h = - FIELD_GET(QDMA_PFTCH_CTXT_SW_CRDT_GET_H_MASK, ctxt->sw_crdt); - - qdma_log_debug("%s: sw_crdt_l=%u, sw_crdt_h=%u, hw_qid=%hu\n", - __func__, sw_crdt_l, sw_crdt_h, hw_qid); - - pfetch_ctxt[num_words_count++] = - FIELD_SET(QDMA_PFTCH_CTXT_W0_BYPASS_MASK, ctxt->bypass) | - FIELD_SET(QDMA_PFTCH_CTXT_W0_BUF_SIZE_IDX_MASK, - ctxt->bufsz_idx) | - FIELD_SET(QDMA_PFTCH_CTXT_W0_PORT_ID_MASK, ctxt->port_id) | - FIELD_SET(QDMA_PFTCH_CTXT_W0_ERR_MASK, ctxt->err) | - FIELD_SET(QDMA_PFTCH_CTXT_W0_PFETCH_EN_MASK, ctxt->pfch_en) | - FIELD_SET(QDMA_PFTCH_CTXT_W0_Q_IN_PFETCH_MASK, ctxt->pfch) | - FIELD_SET(QDMA_PFTCH_CTXT_W0_SW_CRDT_L_MASK, sw_crdt_l); - - qdma_log_debug("%s: bypass=%x, bufsz_idx=%x, port_id=%x\n", - __func__, ctxt->bypass, ctxt->bufsz_idx, ctxt->port_id); - qdma_log_debug("%s: err=%x, pfch_en=%x, pfch=%x, ctxt->valid=%x\n", - __func__, ctxt->err, ctxt->pfch_en, ctxt->pfch, - ctxt->valid); - - pfetch_ctxt[num_words_count++] = - FIELD_SET(QDMA_PFTCH_CTXT_W1_SW_CRDT_H_MASK, sw_crdt_h) | - FIELD_SET(QDMA_PFTCH_CTXT_W1_VALID_MASK, ctxt->valid); - - return qdma_indirect_reg_write(dev_hndl, sel, hw_qid, - pfetch_ctxt, num_words_count); -} - -/*****************************************************************************/ -/** - * qdma_pfetch_context_read() - read prefetch context - * - * @dev_hndl: device handle - * @hw_qid: hardware qid of the queue - * @ctxt: pointer to the output context data - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -static int qdma_pfetch_context_read(void *dev_hndl, uint16_t hw_qid, - struct qdma_descq_prefetch_ctxt *ctxt) -{ - int rv = QDMA_SUCCESS; - uint32_t pfetch_ctxt[QDMA_PFETCH_CONTEXT_NUM_WORDS] = {0}; - enum ind_ctxt_cmd_sel sel = QDMA_CTXT_SEL_PFTCH; - uint32_t sw_crdt_l, sw_crdt_h; - - if (!dev_hndl || !ctxt) { - qdma_log_error("%s: dev_handle or pfetch ctxt NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - rv = qdma_indirect_reg_read(dev_hndl, sel, hw_qid, - QDMA_PFETCH_CONTEXT_NUM_WORDS, pfetch_ctxt); - if (rv < 0) - return rv; - - ctxt->bypass = - FIELD_GET(QDMA_PFTCH_CTXT_W0_BYPASS_MASK, pfetch_ctxt[0]); - ctxt->bufsz_idx = - FIELD_GET(QDMA_PFTCH_CTXT_W0_BUF_SIZE_IDX_MASK, pfetch_ctxt[0]); - ctxt->port_id = - FIELD_GET(QDMA_PFTCH_CTXT_W0_PORT_ID_MASK, pfetch_ctxt[0]); - ctxt->err = - (uint8_t)(FIELD_GET(QDMA_PFTCH_CTXT_W0_ERR_MASK, - pfetch_ctxt[0])); - ctxt->pfch_en = - (uint8_t)(FIELD_GET(QDMA_PFTCH_CTXT_W0_PFETCH_EN_MASK, - pfetch_ctxt[0])); - ctxt->pfch = - (uint8_t)(FIELD_GET(QDMA_PFTCH_CTXT_W0_Q_IN_PFETCH_MASK, - pfetch_ctxt[0])); - sw_crdt_l = - FIELD_GET(QDMA_PFTCH_CTXT_W0_SW_CRDT_L_MASK, pfetch_ctxt[0]); - - sw_crdt_h = - FIELD_GET(QDMA_PFTCH_CTXT_W1_SW_CRDT_H_MASK, pfetch_ctxt[1]); - ctxt->valid = - (uint8_t)(FIELD_GET(QDMA_PFTCH_CTXT_W1_VALID_MASK, - pfetch_ctxt[1])); - - ctxt->sw_crdt = - FIELD_SET(QDMA_PFTCH_CTXT_SW_CRDT_GET_L_MASK, sw_crdt_l) | - FIELD_SET(QDMA_PFTCH_CTXT_SW_CRDT_GET_H_MASK, sw_crdt_h); - - qdma_log_debug("%s: sw_crdt_l=%u, sw_crdt_h=%u, hw_qid=%hu\n", - __func__, sw_crdt_l, sw_crdt_h, hw_qid); - qdma_log_debug("%s: bypass=%x, bufsz_idx=%x, port_id=%x\n", - __func__, ctxt->bypass, ctxt->bufsz_idx, ctxt->port_id); - qdma_log_debug("%s: err=%x, pfch_en=%x, pfch=%x, ctxt->valid=%x\n", - __func__, ctxt->err, ctxt->pfch_en, ctxt->pfch, - ctxt->valid); - - return QDMA_SUCCESS; -} - -/*****************************************************************************/ -/** - * qdma_pfetch_context_clear() - clear prefetch context - * - * @dev_hndl: device handle - * @hw_qid: hardware qid of the queue - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -static int qdma_pfetch_context_clear(void *dev_hndl, uint16_t hw_qid) -{ - enum ind_ctxt_cmd_sel sel = QDMA_CTXT_SEL_PFTCH; - - if (!dev_hndl) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", __func__, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - return qdma_indirect_reg_clear(dev_hndl, sel, hw_qid); -} - -/*****************************************************************************/ -/** - * qdma_pfetch_context_invalidate() - invalidate prefetch context - * - * @dev_hndl: device handle - * @hw_qid: hardware qid of the queue - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -static int qdma_pfetch_context_invalidate(void *dev_hndl, uint16_t hw_qid) -{ - enum ind_ctxt_cmd_sel sel = QDMA_CTXT_SEL_PFTCH; - - if (!dev_hndl) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", __func__, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - return qdma_indirect_reg_invalidate(dev_hndl, sel, hw_qid); -} - -/*****************************************************************************/ -/** - * qdma_pfetch_ctx_conf() - configure prefetch context - * - * @dev_hndl: device handle - * @hw_qid: hardware qid of the queue - * @ctxt: pointer to context data - * @access_type HW access type (qdma_hw_access_type enum) value - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -int qdma_pfetch_ctx_conf(void *dev_hndl, uint16_t hw_qid, - struct qdma_descq_prefetch_ctxt *ctxt, - enum qdma_hw_access_type access_type) -{ - int rv = QDMA_SUCCESS; - - switch (access_type) { - case QDMA_HW_ACCESS_READ: - rv = qdma_pfetch_context_read(dev_hndl, hw_qid, ctxt); - break; - case QDMA_HW_ACCESS_WRITE: - rv = qdma_pfetch_context_write(dev_hndl, hw_qid, ctxt); - break; - case QDMA_HW_ACCESS_CLEAR: - rv = qdma_pfetch_context_clear(dev_hndl, hw_qid); - break; - case QDMA_HW_ACCESS_INVALIDATE: - rv = qdma_pfetch_context_invalidate(dev_hndl, hw_qid); - break; - default: - qdma_log_error("%s: access_type(%d) invalid, err:%d\n", - __func__, - access_type, - -QDMA_ERR_INV_PARAM); - rv = -QDMA_ERR_INV_PARAM; - break; - } - - return rv; -} - -/*****************************************************************************/ -/** - * qdma_cmpt_context_write() - create completion context and program it - * - * @dev_hndl: device handle - * @hw_qid: hardware qid of the queue - * @ctxt: pointer to the cmpt context data strucutre - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -static int qdma_cmpt_context_write(void *dev_hndl, uint16_t hw_qid, - const struct qdma_descq_cmpt_ctxt *ctxt) -{ - uint32_t cmpt_ctxt[QDMA_CMPT_CONTEXT_NUM_WORDS] = {0}; - uint16_t num_words_count = 0; - uint32_t baddr_l, baddr_h, pidx_l, pidx_h; - enum ind_ctxt_cmd_sel sel = QDMA_CTXT_SEL_CMPT; - - /* Input args check */ - if (!dev_hndl || !ctxt) { - qdma_log_error("%s: dev_handle or cmpt ctxt NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - if (ctxt->trig_mode > QDMA_CMPT_UPDATE_TRIG_MODE_TMR_CNTR) { - qdma_log_error("%s: trig_mode(%d) > (%d) is invalid, err:%d\n", - __func__, - ctxt->trig_mode, - QDMA_CMPT_UPDATE_TRIG_MODE_TMR_CNTR, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - baddr_l = (uint32_t)FIELD_GET(QDMA_COMPL_CTXT_BADDR_GET_L_MASK, - ctxt->bs_addr); - baddr_h = (uint32_t)FIELD_GET(QDMA_COMPL_CTXT_BADDR_GET_H_MASK, - ctxt->bs_addr); - pidx_l = FIELD_GET(QDMA_COMPL_CTXT_PIDX_GET_L_MASK, ctxt->pidx); - pidx_h = FIELD_GET(QDMA_COMPL_CTXT_PIDX_GET_H_MASK, ctxt->pidx); - - cmpt_ctxt[num_words_count++] = - FIELD_SET(QDMA_COMPL_CTXT_W0_EN_STAT_DESC_MASK, - ctxt->en_stat_desc) | - FIELD_SET(QDMA_COMPL_CTXT_W0_EN_INT_MASK, ctxt->en_int) | - FIELD_SET(QDMA_COMPL_CTXT_W0_TRIG_MODE_MASK, ctxt->trig_mode) | - FIELD_SET(QDMA_COMPL_CTXT_W0_FNC_ID_MASK, ctxt->fnc_id) | - FIELD_SET(QDMA_COMPL_CTXT_W0_COUNTER_IDX_MASK, - ctxt->counter_idx) | - FIELD_SET(QDMA_COMPL_CTXT_W0_TIMER_IDX_MASK, ctxt->timer_idx) | - FIELD_SET(QDMA_COMPL_CTXT_W0_INT_ST_MASK, ctxt->in_st) | - FIELD_SET(QDMA_COMPL_CTXT_W0_COLOR_MASK, ctxt->color) | - FIELD_SET(QDMA_COMPL_CTXT_W0_RING_SZ_MASK, ctxt->ringsz_idx); - - cmpt_ctxt[num_words_count++] = - FIELD_SET(QDMA_COMPL_CTXT_W1_BADDR_64_L_MASK, baddr_l); - - cmpt_ctxt[num_words_count++] = - FIELD_SET(QDMA_COMPL_CTXT_W2_BADDR_64_H_MASK, baddr_h) | - FIELD_SET(QDMA_COMPL_CTXT_W2_DESC_SIZE_MASK, ctxt->desc_sz) | - FIELD_SET(QDMA_COMPL_CTXT_W2_PIDX_L_MASK, pidx_l); - - - cmpt_ctxt[num_words_count++] = - FIELD_SET(QDMA_COMPL_CTXT_W3_PIDX_H_MASK, pidx_h) | - FIELD_SET(QDMA_COMPL_CTXT_W3_CIDX_MASK, ctxt->cidx) | - FIELD_SET(QDMA_COMPL_CTXT_W3_VALID_MASK, ctxt->valid) | - FIELD_SET(QDMA_COMPL_CTXT_W3_ERR_MASK, ctxt->err) | - FIELD_SET(QDMA_COMPL_CTXT_W3_USR_TRG_PND_MASK, - ctxt->user_trig_pend); - - cmpt_ctxt[num_words_count++] = - FIELD_SET(QDMA_COMPL_CTXT_W4_TMR_RUN_MASK, - ctxt->timer_running) | - FIELD_SET(QDMA_COMPL_CTXT_W4_FULL_UPDT_MASK, ctxt->full_upd) | - FIELD_SET(QDMA_COMPL_CTXT_W4_OVF_CHK_DIS_MASK, - ctxt->ovf_chk_dis) | - FIELD_SET(QDMA_COMPL_CTXT_W4_AT_MASK, ctxt->at) | - FIELD_SET(QDMA_COMPL_CTXT_W4_INTR_VEC_MASK, ctxt->vec) | - FIELD_SET(QDMA_COMPL_CTXT_W4_INTR_AGGR_MASK, ctxt->int_aggr); - - return qdma_indirect_reg_write(dev_hndl, sel, hw_qid, - cmpt_ctxt, num_words_count); -} - -/*****************************************************************************/ -/** - * qdma_cmpt_context_read() - read completion context - * - * @dev_hndl: device handle - * @hw_qid: hardware qid of the queue - * @ctxt: pointer to the context data - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -static int qdma_cmpt_context_read(void *dev_hndl, uint16_t hw_qid, - struct qdma_descq_cmpt_ctxt *ctxt) -{ - int rv = QDMA_SUCCESS; - uint32_t cmpt_ctxt[QDMA_CMPT_CONTEXT_NUM_WORDS] = {0}; - enum ind_ctxt_cmd_sel sel = QDMA_CTXT_SEL_CMPT; - uint32_t baddr_l, baddr_h, pidx_l, pidx_h; - - if (!dev_hndl || !ctxt) { - qdma_log_error("%s: dev_handle or cmpt ctxt NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - rv = qdma_indirect_reg_read(dev_hndl, sel, hw_qid, - QDMA_CMPT_CONTEXT_NUM_WORDS, cmpt_ctxt); - if (rv < 0) - return rv; - - ctxt->en_stat_desc = - FIELD_GET(QDMA_COMPL_CTXT_W0_EN_STAT_DESC_MASK, cmpt_ctxt[0]); - ctxt->en_int = FIELD_GET(QDMA_COMPL_CTXT_W0_EN_INT_MASK, cmpt_ctxt[0]); - ctxt->trig_mode = - FIELD_GET(QDMA_COMPL_CTXT_W0_TRIG_MODE_MASK, cmpt_ctxt[0]); - ctxt->fnc_id = - (uint8_t)(FIELD_GET(QDMA_COMPL_CTXT_W0_FNC_ID_MASK, - cmpt_ctxt[0])); - ctxt->counter_idx = - (uint8_t)(FIELD_GET(QDMA_COMPL_CTXT_W0_COUNTER_IDX_MASK, - cmpt_ctxt[0])); - ctxt->timer_idx = - (uint8_t)(FIELD_GET(QDMA_COMPL_CTXT_W0_TIMER_IDX_MASK, - cmpt_ctxt[0])); - ctxt->in_st = - (uint8_t)(FIELD_GET(QDMA_COMPL_CTXT_W0_INT_ST_MASK, - cmpt_ctxt[0])); - ctxt->color = - (uint8_t)(FIELD_GET(QDMA_COMPL_CTXT_W0_COLOR_MASK, - cmpt_ctxt[0])); - ctxt->ringsz_idx = - (uint8_t)(FIELD_GET(QDMA_COMPL_CTXT_W0_RING_SZ_MASK, - cmpt_ctxt[0])); - - baddr_l = FIELD_GET(QDMA_COMPL_CTXT_W1_BADDR_64_L_MASK, cmpt_ctxt[1]); - - baddr_h = FIELD_GET(QDMA_COMPL_CTXT_W2_BADDR_64_H_MASK, cmpt_ctxt[2]); - ctxt->desc_sz = - (uint8_t)(FIELD_GET(QDMA_COMPL_CTXT_W2_DESC_SIZE_MASK, - cmpt_ctxt[2])); - pidx_l = FIELD_GET(QDMA_COMPL_CTXT_W2_PIDX_L_MASK, cmpt_ctxt[2]); - - pidx_h = FIELD_GET(QDMA_COMPL_CTXT_W3_PIDX_H_MASK, cmpt_ctxt[3]); - ctxt->cidx = - (uint16_t)(FIELD_GET(QDMA_COMPL_CTXT_W3_CIDX_MASK, - cmpt_ctxt[3])); - ctxt->valid = - (uint8_t)(FIELD_GET(QDMA_COMPL_CTXT_W3_VALID_MASK, - cmpt_ctxt[3])); - ctxt->err = - (uint8_t)(FIELD_GET(QDMA_COMPL_CTXT_W3_ERR_MASK, cmpt_ctxt[3])); - ctxt->user_trig_pend = (uint8_t) - (FIELD_GET(QDMA_COMPL_CTXT_W3_USR_TRG_PND_MASK, cmpt_ctxt[3])); - - ctxt->timer_running = - FIELD_GET(QDMA_COMPL_CTXT_W4_TMR_RUN_MASK, cmpt_ctxt[4]); - ctxt->full_upd = - FIELD_GET(QDMA_COMPL_CTXT_W4_FULL_UPDT_MASK, cmpt_ctxt[4]); - ctxt->ovf_chk_dis = - FIELD_GET(QDMA_COMPL_CTXT_W4_OVF_CHK_DIS_MASK, cmpt_ctxt[4]); - ctxt->at = FIELD_GET(QDMA_COMPL_CTXT_W4_AT_MASK, cmpt_ctxt[4]); - ctxt->vec = FIELD_GET(QDMA_COMPL_CTXT_W4_INTR_VEC_MASK, cmpt_ctxt[4]); - ctxt->int_aggr = (uint8_t) - (FIELD_GET(QDMA_COMPL_CTXT_W4_INTR_AGGR_MASK, cmpt_ctxt[4])); - - ctxt->bs_addr = - FIELD_SET(QDMA_COMPL_CTXT_BADDR_GET_L_MASK, (uint64_t)baddr_l) | - FIELD_SET(QDMA_COMPL_CTXT_BADDR_GET_H_MASK, (uint64_t)baddr_h); - - ctxt->pidx = - FIELD_SET(QDMA_COMPL_CTXT_PIDX_GET_L_MASK, pidx_l) | - FIELD_SET(QDMA_COMPL_CTXT_PIDX_GET_H_MASK, pidx_h); - - return QDMA_SUCCESS; -} - -/*****************************************************************************/ -/** - * qdma_cmpt_context_clear() - clear completion context - * - * @dev_hndl: device handle - * @hw_qid: hardware qid of the queue - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -static int qdma_cmpt_context_clear(void *dev_hndl, uint16_t hw_qid) -{ - enum ind_ctxt_cmd_sel sel = QDMA_CTXT_SEL_CMPT; - - if (!dev_hndl) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", __func__, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - return qdma_indirect_reg_clear(dev_hndl, sel, hw_qid); -} - -/*****************************************************************************/ -/** - * qdma_cmpt_context_invalidate() - invalidate completion context - * - * @dev_hndl: device handle - * @hw_qid: hardware qid of the queue - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -static int qdma_cmpt_context_invalidate(void *dev_hndl, uint16_t hw_qid) -{ - enum ind_ctxt_cmd_sel sel = QDMA_CTXT_SEL_CMPT; - - if (!dev_hndl) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", __func__, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - return qdma_indirect_reg_invalidate(dev_hndl, sel, hw_qid); -} - -/*****************************************************************************/ -/** - * qdma_cmpt_ctx_conf() - configure completion context - * - * @dev_hndl: device handle - * @hw_qid: hardware qid of the queue - * @ctxt: pointer to context data - * @access_type HW access type (qdma_hw_access_type enum) value - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -int qdma_cmpt_ctx_conf(void *dev_hndl, uint16_t hw_qid, - struct qdma_descq_cmpt_ctxt *ctxt, - enum qdma_hw_access_type access_type) -{ - int rv = QDMA_SUCCESS; - - switch (access_type) { - case QDMA_HW_ACCESS_READ: - rv = qdma_cmpt_context_read(dev_hndl, hw_qid, ctxt); - break; - case QDMA_HW_ACCESS_WRITE: - rv = qdma_cmpt_context_write(dev_hndl, hw_qid, ctxt); - break; - case QDMA_HW_ACCESS_CLEAR: - rv = qdma_cmpt_context_clear(dev_hndl, hw_qid); - break; - case QDMA_HW_ACCESS_INVALIDATE: - rv = qdma_cmpt_context_invalidate(dev_hndl, hw_qid); - break; - default: - qdma_log_error("%s: access_type(%d) invalid, err:%d\n", - __func__, - access_type, - -QDMA_ERR_INV_PARAM); - rv = -QDMA_ERR_INV_PARAM; - break; - } - - return rv; -} - -/*****************************************************************************/ -/** - * qdma_hw_context_read() - read hardware context - * - * @dev_hndl: device handle - * @c2h: is c2h queue - * @hw_qid: hardware qid of the queue - * @ctxt: pointer to the output context data - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -static int qdma_hw_context_read(void *dev_hndl, uint8_t c2h, - uint16_t hw_qid, struct qdma_descq_hw_ctxt *ctxt) -{ - int rv = QDMA_SUCCESS; - uint32_t hw_ctxt[QDMA_HW_CONTEXT_NUM_WORDS] = {0}; - enum ind_ctxt_cmd_sel sel = c2h ? QDMA_CTXT_SEL_HW_C2H : - QDMA_CTXT_SEL_HW_H2C; - - if (!dev_hndl || !ctxt) { - qdma_log_error("%s: dev_handle or hw_ctxt NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - rv = qdma_indirect_reg_read(dev_hndl, sel, hw_qid, - QDMA_HW_CONTEXT_NUM_WORDS, hw_ctxt); - if (rv < 0) - return rv; - - ctxt->cidx = FIELD_GET(QDMA_HW_CTXT_W0_CIDX_MASK, hw_ctxt[0]); - ctxt->crd_use = - (uint16_t)(FIELD_GET(QDMA_HW_CTXT_W0_CRD_USE_MASK, hw_ctxt[0])); - - ctxt->dsc_pend = - (uint8_t)(FIELD_GET(QDMA_HW_CTXT_W1_DSC_PND_MASK, hw_ctxt[1])); - ctxt->idl_stp_b = - (uint8_t)(FIELD_GET(QDMA_HW_CTXT_W1_IDL_STP_B_MASK, - hw_ctxt[1])); - ctxt->evt_pnd = - (uint8_t)(FIELD_GET(QDMA_HW_CTXT_W1_EVENT_PEND_MASK, - hw_ctxt[1])); - ctxt->fetch_pnd = (uint8_t) - (FIELD_GET(QDMA_HW_CTXT_W1_FETCH_PEND_MASK, hw_ctxt[1])); - - qdma_log_debug("%s: cidx=%hu, crd_use=%hu, dsc_pend=%x\n", - __func__, ctxt->cidx, ctxt->crd_use, ctxt->dsc_pend); - qdma_log_debug("%s: idl_stp_b=%x, evt_pnd=%x, fetch_pnd=%x\n", - __func__, ctxt->idl_stp_b, ctxt->evt_pnd, - ctxt->fetch_pnd); - - return QDMA_SUCCESS; -} - -/*****************************************************************************/ -/** - * qdma_hw_context_clear() - clear hardware context - * - * @dev_hndl: device handle - * @c2h: is c2h queue - * @hw_qid: hardware qid of the queue - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -static int qdma_hw_context_clear(void *dev_hndl, uint8_t c2h, - uint16_t hw_qid) -{ - enum ind_ctxt_cmd_sel sel = c2h ? QDMA_CTXT_SEL_HW_C2H : - QDMA_CTXT_SEL_HW_H2C; - - if (!dev_hndl) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", __func__, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - return qdma_indirect_reg_clear(dev_hndl, sel, hw_qid); -} - -/*****************************************************************************/ -/** - * qdma_hw_context_invalidate() - invalidate hardware context - * - * @dev_hndl: device handle - * @c2h: is c2h queue - * @hw_qid: hardware qid of the queue - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -static int qdma_hw_context_invalidate(void *dev_hndl, uint8_t c2h, - uint16_t hw_qid) -{ - enum ind_ctxt_cmd_sel sel = c2h ? QDMA_CTXT_SEL_HW_C2H : - QDMA_CTXT_SEL_HW_H2C; - - if (!dev_hndl) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", __func__, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - return qdma_indirect_reg_invalidate(dev_hndl, sel, hw_qid); -} - -/*****************************************************************************/ -/** - * qdma_hw_ctx_conf() - configure HW context - * - * @dev_hndl: device handle - * @c2h: is c2h queue - * @hw_qid: hardware qid of the queue - * @ctxt: pointer to context data - * @access_type HW access type (qdma_hw_access_type enum) value - * QDMA_HW_ACCESS_WRITE Not supported - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -int qdma_hw_ctx_conf(void *dev_hndl, uint8_t c2h, uint16_t hw_qid, - struct qdma_descq_hw_ctxt *ctxt, - enum qdma_hw_access_type access_type) -{ - int rv = QDMA_SUCCESS; - - /** ctxt requires only H2C-0 or C2H-1 - * return error for any other values - */ - if (c2h > 1) { - qdma_log_error("%s: c2h(%d) invalid, err:%d\n", - __func__, - c2h, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - switch (access_type) { - case QDMA_HW_ACCESS_READ: - rv = qdma_hw_context_read(dev_hndl, c2h, hw_qid, ctxt); - break; - case QDMA_HW_ACCESS_CLEAR: - rv = qdma_hw_context_clear(dev_hndl, c2h, hw_qid); - break; - case QDMA_HW_ACCESS_INVALIDATE: - rv = qdma_hw_context_invalidate(dev_hndl, c2h, hw_qid); - break; - case QDMA_HW_ACCESS_WRITE: - default: - qdma_log_error("%s: access_type=%d is invalid, err:%d\n", - __func__, access_type, - -QDMA_ERR_INV_PARAM); - rv = -QDMA_ERR_INV_PARAM; - break; - } - - return rv; -} - -/*****************************************************************************/ -/** - * qdma_credit_context_read() - read credit context - * - * @dev_hndl: device handle - * @c2h: is c2h queue - * @hw_qid: hardware qid of the queue - * @ctxt: pointer to the context data - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -static int qdma_credit_context_read(void *dev_hndl, uint8_t c2h, - uint16_t hw_qid, - struct qdma_descq_credit_ctxt *ctxt) -{ - int rv = QDMA_SUCCESS; - uint32_t cr_ctxt[QDMA_CR_CONTEXT_NUM_WORDS] = {0}; - enum ind_ctxt_cmd_sel sel = c2h ? QDMA_CTXT_SEL_CR_C2H : - QDMA_CTXT_SEL_CR_H2C; - - if (!dev_hndl || !ctxt) { - qdma_log_error("%s: dev_hndl=%p credit_ctxt=%p, err:%d\n", - __func__, dev_hndl, ctxt, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - rv = qdma_indirect_reg_read(dev_hndl, sel, hw_qid, - QDMA_CR_CONTEXT_NUM_WORDS, cr_ctxt); - if (rv < 0) - return rv; - - ctxt->credit = FIELD_GET(QDMA_CR_CTXT_W0_CREDT_MASK, cr_ctxt[0]); - - qdma_log_debug("%s: credit=%u\n", __func__, ctxt->credit); - - return QDMA_SUCCESS; -} - -/*****************************************************************************/ -/** - * qdma_credit_context_clear() - clear credit context - * - * @dev_hndl: device handle - * @c2h: is c2h queue - * @hw_qid: hardware qid of the queue - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -static int qdma_credit_context_clear(void *dev_hndl, uint8_t c2h, - uint16_t hw_qid) -{ - enum ind_ctxt_cmd_sel sel = c2h ? QDMA_CTXT_SEL_CR_C2H : - QDMA_CTXT_SEL_CR_H2C; - - if (!dev_hndl) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", __func__, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - return qdma_indirect_reg_clear(dev_hndl, sel, hw_qid); -} - -/*****************************************************************************/ -/** - * qdma_credit_context_invalidate() - invalidate credit context - * - * @dev_hndl: device handle - * @c2h: is c2h queue - * @hw_qid: hardware qid of the queue - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -static int qdma_credit_context_invalidate(void *dev_hndl, uint8_t c2h, - uint16_t hw_qid) -{ - enum ind_ctxt_cmd_sel sel = c2h ? QDMA_CTXT_SEL_CR_C2H : - QDMA_CTXT_SEL_CR_H2C; - - if (!dev_hndl) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", __func__, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - return qdma_indirect_reg_invalidate(dev_hndl, sel, hw_qid); -} - -/*****************************************************************************/ -/** - * qdma_credit_ctx_conf() - configure credit context - * - * @dev_hndl: device handle - * @c2h: is c2h queue - * @hw_qid: hardware qid of the queue - * @ctxt: pointer to the context data - * @access_type HW access type (qdma_hw_access_type enum) value - * QDMA_HW_ACCESS_WRITE Not supported - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -int qdma_credit_ctx_conf(void *dev_hndl, uint8_t c2h, uint16_t hw_qid, - struct qdma_descq_credit_ctxt *ctxt, - enum qdma_hw_access_type access_type) -{ - int rv = QDMA_SUCCESS; - - /** ctxt requires only H2C-0 or C2H-1 - * return error for any other values - */ - if (c2h > 1) { - qdma_log_error("%s: c2h(%d) invalid, err:%d\n", - __func__, - c2h, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - switch (access_type) { - case QDMA_HW_ACCESS_READ: - rv = qdma_credit_context_read(dev_hndl, c2h, hw_qid, ctxt); - break; - case QDMA_HW_ACCESS_CLEAR: - rv = qdma_credit_context_clear(dev_hndl, c2h, hw_qid); - break; - case QDMA_HW_ACCESS_INVALIDATE: - rv = qdma_credit_context_invalidate(dev_hndl, c2h, hw_qid); - break; - case QDMA_HW_ACCESS_WRITE: - default: - qdma_log_error("%s: Invalid access type=%d, err:%d\n", - __func__, access_type, - -QDMA_ERR_INV_PARAM); - rv = -QDMA_ERR_INV_PARAM; - break; - } - - return rv; -} - -/*****************************************************************************/ -/** - * qdma_indirect_intr_context_write() - create indirect interrupt context - * and program it - * - * @dev_hndl: device handle - * @ring_index: indirect interrupt ring index - * @ctxt: pointer to the interrupt context data strucutre - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -static int qdma_indirect_intr_context_write(void *dev_hndl, uint16_t ring_index, - const struct qdma_indirect_intr_ctxt *ctxt) -{ - uint32_t intr_ctxt[QDMA_IND_INTR_CONTEXT_NUM_WORDS] = {0}; - enum ind_ctxt_cmd_sel sel = QDMA_CTXT_SEL_INT_COAL; - uint32_t baddr_l, baddr_m, baddr_h; - uint16_t num_words_count = 0; - - if (!dev_hndl || !ctxt) { - qdma_log_error("%s: dev_hndl=%p intr_ctxt=%p, err:%d\n", - __func__, dev_hndl, ctxt, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - baddr_l = (uint32_t)FIELD_GET(QDMA_INTR_CTXT_BADDR_GET_L_MASK, - ctxt->baddr_4k); - baddr_m = (uint32_t)FIELD_GET(QDMA_INTR_CTXT_BADDR_GET_M_MASK, - ctxt->baddr_4k); - baddr_h = (uint32_t)FIELD_GET(QDMA_INTR_CTXT_BADDR_GET_H_MASK, - ctxt->baddr_4k); - - intr_ctxt[num_words_count++] = - FIELD_SET(QDMA_INTR_CTXT_W0_VALID_MASK, ctxt->valid) | - FIELD_SET(QDMA_INTR_CTXT_W0_VEC_ID_MASK, ctxt->vec) | - FIELD_SET(QDMA_INTR_CTXT_W0_INT_ST_MASK, ctxt->int_st) | - FIELD_SET(QDMA_INTR_CTXT_W0_COLOR_MASK, ctxt->color) | - FIELD_SET(QDMA_INTR_CTXT_W0_BADDR_64_MASK, baddr_l); - - intr_ctxt[num_words_count++] = - FIELD_SET(QDMA_INTR_CTXT_W1_BADDR_64_MASK, baddr_m); - - intr_ctxt[num_words_count++] = - FIELD_SET(QDMA_INTR_CTXT_W2_BADDR_64_MASK, baddr_h) | - FIELD_SET(QDMA_INTR_CTXT_W2_PAGE_SIZE_MASK, ctxt->page_size) | - FIELD_SET(QDMA_INTR_CTXT_W2_PIDX_MASK, ctxt->pidx) | - FIELD_SET(QDMA_INTR_CTXT_W2_AT_MASK, ctxt->at); - - return qdma_indirect_reg_write(dev_hndl, sel, ring_index, - intr_ctxt, num_words_count); -} - -/*****************************************************************************/ -/** - * qdma_indirect_intr_context_read() - read indirect interrupt context - * - * @dev_hndl: device handle - * @ring_index: indirect interrupt ring index - * @ctxt: pointer to the output context data - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -static int qdma_indirect_intr_context_read(void *dev_hndl, uint16_t ring_index, - struct qdma_indirect_intr_ctxt *ctxt) -{ - int rv = QDMA_SUCCESS; - uint32_t intr_ctxt[QDMA_IND_INTR_CONTEXT_NUM_WORDS] = {0}; - enum ind_ctxt_cmd_sel sel = QDMA_CTXT_SEL_INT_COAL; - uint64_t baddr_l, baddr_m, baddr_h; - - if (!dev_hndl || !ctxt) { - qdma_log_error("%s: dev_hndl=%p intr_ctxt=%p, err:%d\n", - __func__, dev_hndl, ctxt, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - rv = qdma_indirect_reg_read(dev_hndl, sel, ring_index, - QDMA_IND_INTR_CONTEXT_NUM_WORDS, intr_ctxt); - if (rv < 0) - return rv; - - ctxt->valid = FIELD_GET(QDMA_INTR_CTXT_W0_VALID_MASK, intr_ctxt[0]); - ctxt->vec = FIELD_GET(QDMA_INTR_CTXT_W0_VEC_ID_MASK, intr_ctxt[0]); - ctxt->int_st = - (uint8_t)(FIELD_GET(QDMA_INTR_CTXT_W0_INT_ST_MASK, - intr_ctxt[0])); - ctxt->color = - (uint8_t)(FIELD_GET(QDMA_INTR_CTXT_W0_COLOR_MASK, - intr_ctxt[0])); - - baddr_l = FIELD_GET(QDMA_INTR_CTXT_W0_BADDR_64_MASK, intr_ctxt[0]); - - baddr_m = FIELD_GET(QDMA_INTR_CTXT_W1_BADDR_64_MASK, intr_ctxt[1]); - - baddr_h = FIELD_GET(QDMA_INTR_CTXT_W2_BADDR_64_MASK, intr_ctxt[2]); - ctxt->page_size = - FIELD_GET(QDMA_INTR_CTXT_W2_PAGE_SIZE_MASK, intr_ctxt[2]); - ctxt->pidx = - (uint16_t)(FIELD_GET(QDMA_INTR_CTXT_W2_PIDX_MASK, - intr_ctxt[2])); - ctxt->at = - (uint8_t)(FIELD_GET(QDMA_INTR_CTXT_W2_AT_MASK, intr_ctxt[2])); - - ctxt->baddr_4k = - FIELD_SET(QDMA_INTR_CTXT_BADDR_GET_L_MASK, baddr_l) | - FIELD_SET(QDMA_INTR_CTXT_BADDR_GET_M_MASK, baddr_m) | - FIELD_SET(QDMA_INTR_CTXT_BADDR_GET_H_MASK, baddr_h); - - return QDMA_SUCCESS; -} - -/*****************************************************************************/ -/** - * qdma_indirect_intr_context_clear() - clear indirect interrupt context - * - * @dev_hndl: device handle - * @ring_index: indirect interrupt ring index - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -static int qdma_indirect_intr_context_clear(void *dev_hndl, uint16_t ring_index) -{ - enum ind_ctxt_cmd_sel sel = QDMA_CTXT_SEL_INT_COAL; - - if (!dev_hndl) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", __func__, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - return qdma_indirect_reg_clear(dev_hndl, sel, ring_index); -} - -/*****************************************************************************/ -/** - * qdma_indirect_intr_context_invalidate() - invalidate indirect interrupt - * context - * - * @dev_hndl: device handle - * @ring_index: indirect interrupt ring index - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -static int qdma_indirect_intr_context_invalidate(void *dev_hndl, - uint16_t ring_index) -{ - enum ind_ctxt_cmd_sel sel = QDMA_CTXT_SEL_INT_COAL; - - if (!dev_hndl) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", __func__, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - return qdma_indirect_reg_invalidate(dev_hndl, sel, ring_index); -} - -/*****************************************************************************/ -/** - * qdma_indirect_intr_ctx_conf() - configure indirect interrupt context - * - * @dev_hndl: device handle - * @ring_index: indirect interrupt ring index - * @ctxt: pointer to context data - * @access_type HW access type (qdma_hw_access_type enum) value - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -int qdma_indirect_intr_ctx_conf(void *dev_hndl, uint16_t ring_index, - struct qdma_indirect_intr_ctxt *ctxt, - enum qdma_hw_access_type access_type) -{ - int rv = QDMA_SUCCESS; - - switch (access_type) { - case QDMA_HW_ACCESS_READ: - rv = qdma_indirect_intr_context_read(dev_hndl, ring_index, - ctxt); - break; - case QDMA_HW_ACCESS_WRITE: - rv = qdma_indirect_intr_context_write(dev_hndl, ring_index, - ctxt); - break; - case QDMA_HW_ACCESS_CLEAR: - rv = qdma_indirect_intr_context_clear(dev_hndl, - ring_index); - break; - case QDMA_HW_ACCESS_INVALIDATE: - rv = qdma_indirect_intr_context_invalidate(dev_hndl, - ring_index); - break; - default: - qdma_log_error("%s: access_type=%d is invalid, err:%d\n", - __func__, access_type, - -QDMA_ERR_INV_PARAM); - rv = -QDMA_ERR_INV_PARAM; - break; - } - - return rv; -} - -/*****************************************************************************/ -/** - * qdma_set_default_global_csr() - function to set the global CSR register to - * default values. The value can be modified later by using the set/get csr - * functions - * - * @dev_hndl: device handle - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -int qdma_set_default_global_csr(void *dev_hndl) -{ - /* Default values */ - uint32_t cfg_val = 0, reg_val = 0; - uint32_t rng_sz[QDMA_NUM_RING_SIZES] = {2049, 65, 129, 193, 257, 385, - 513, 769, 1025, 1537, 3073, 4097, 6145, 8193, 12289, 16385}; - uint32_t tmr_cnt[QDMA_NUM_C2H_TIMERS] = {1, 2, 4, 5, 8, 10, 15, 20, 25, - 30, 50, 75, 100, 125, 150, 200}; - uint32_t cnt_th[QDMA_NUM_C2H_COUNTERS] = {2, 4, 8, 16, 24, 32, 48, 64, - 80, 96, 112, 128, 144, 160, 176, 192}; - uint32_t buf_sz[QDMA_NUM_C2H_BUFFER_SIZES] = {4096, 256, 512, 1024, - 2048, 3968, 4096, 4096, 4096, 4096, 4096, 4096, 4096, 8192, - 9018, 16384}; - struct qdma_dev_attributes dev_cap; - - if (!dev_hndl) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", __func__, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - qdma_get_device_attributes(dev_hndl, &dev_cap); - - /* Configuring CSR registers */ - /* Global ring sizes */ - qdma_write_csr_values(dev_hndl, QDMA_OFFSET_GLBL_RNG_SZ, 0, - QDMA_NUM_RING_SIZES, rng_sz); - - if (dev_cap.st_en || dev_cap.mm_cmpt_en) { - /* Counter thresholds */ - qdma_write_csr_values(dev_hndl, QDMA_OFFSET_C2H_CNT_TH, 0, - QDMA_NUM_C2H_COUNTERS, cnt_th); - - /* Timer Counters */ - qdma_write_csr_values(dev_hndl, QDMA_OFFSET_C2H_TIMER_CNT, 0, - QDMA_NUM_C2H_TIMERS, tmr_cnt); - - - /* Writeback Interval */ - reg_val = - FIELD_SET(QDMA_GLBL_DSC_CFG_MAX_DSC_FETCH_MASK, - DEFAULT_MAX_DSC_FETCH) | - FIELD_SET(QDMA_GLBL_DSC_CFG_WB_ACC_INT_MASK, - DEFAULT_WRB_INT); - qdma_reg_write(dev_hndl, QDMA_OFFSET_GLBL_DSC_CFG, reg_val); - } - - if (dev_cap.st_en) { - /* Buffer Sizes */ - qdma_write_csr_values(dev_hndl, QDMA_OFFSET_C2H_BUF_SZ, 0, - QDMA_NUM_C2H_BUFFER_SIZES, buf_sz); - - /* Prefetch Configuration */ - cfg_val = qdma_reg_read(dev_hndl, - QDMA_OFFSET_C2H_PFETCH_CACHE_DEPTH); - reg_val = - FIELD_SET(QDMA_C2H_PFCH_FL_TH_MASK, - QDMA_DEFAULT_PFCH_STOP_THRESH) | - FIELD_SET(QDMA_C2H_NUM_PFCH_MASK, - DEFAULT_PFCH_NUM_ENTRIES_PER_Q) | - FIELD_SET(QDMA_C2H_PFCH_QCNT_MASK, (cfg_val >> 1)) | - FIELD_SET(QDMA_C2H_EVT_QCNT_TH_MASK, - ((cfg_val >> 1) - 2)); - qdma_reg_write(dev_hndl, QDMA_OFFSET_C2H_PFETCH_CFG, reg_val); - - /* C2H interrupt timer tick */ - qdma_reg_write(dev_hndl, QDMA_OFFSET_C2H_INT_TIMER_TICK, - DEFAULT_C2H_INTR_TIMER_TICK); - - /* C2h Completion Coalesce Configuration */ - cfg_val = qdma_reg_read(dev_hndl, - QDMA_OFFSET_C2H_CMPT_COAL_BUF_DEPTH); - reg_val = - FIELD_SET(QDMA_C2H_TICK_CNT_MASK, - DEFAULT_CMPT_COAL_TIMER_CNT) | - FIELD_SET(QDMA_C2H_TICK_VAL_MASK, - DEFAULT_CMPT_COAL_TIMER_TICK) | - FIELD_SET(QDMA_C2H_MAX_BUF_SZ_MASK, cfg_val); - qdma_reg_write(dev_hndl, QDMA_OFFSET_C2H_WRB_COAL_CFG, reg_val); - - /* H2C throttle Configuration*/ - reg_val = - FIELD_SET(QDMA_H2C_DATA_THRESH_MASK, - QDMA_H2C_THROT_DATA_THRESH) | - FIELD_SET(QDMA_H2C_REQ_THROT_EN_DATA_MASK, - QDMA_THROT_EN_DATA) | - FIELD_SET(QDMA_H2C_REQ_THRESH_MASK, - QDMA_H2C_THROT_REQ_THRESH) | - FIELD_SET(QDMA_H2C_REQ_THROT_EN_REQ_MASK, - QDMA_THROT_EN_REQ); - qdma_reg_write(dev_hndl, QDMA_OFFSET_H2C_REQ_THROT, reg_val); - } - - return QDMA_SUCCESS; -} - -/*****************************************************************************/ -/** - * qdma_queue_pidx_update() - function to update the desc PIDX - * - * @dev_hndl: device handle - * @is_vf: Whether PF or VF - * @qid: Queue id relative to the PF/VF calling this API - * @is_c2h: Queue direction. Set 1 for C2H and 0 for H2C - * @reg_info: data needed for the PIDX register update - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -int qdma_queue_pidx_update(void *dev_hndl, uint8_t is_vf, uint16_t qid, - uint8_t is_c2h, const struct qdma_q_pidx_reg_info *reg_info) -{ - uint32_t reg_addr = 0; - uint32_t reg_val = 0; - - if (!dev_hndl || !reg_info) { - qdma_log_error("%s: dev_hndl:(%p), reg_info:(%p), err:%d\n", - __func__, dev_hndl, reg_info, -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - if (!is_vf) { - reg_addr = (is_c2h) ? QDMA_OFFSET_DMAP_SEL_C2H_DSC_PIDX : - QDMA_OFFSET_DMAP_SEL_H2C_DSC_PIDX; - } else { - reg_addr = (is_c2h) ? QDMA_OFFSET_VF_DMAP_SEL_C2H_DSC_PIDX : - QDMA_OFFSET_VF_DMAP_SEL_H2C_DSC_PIDX; - } - - reg_addr += (qid * QDMA_PIDX_STEP); - - reg_val = FIELD_SET(QDMA_DMA_SEL_DESC_PIDX_MASK, reg_info->pidx) | - FIELD_SET(QDMA_DMA_SEL_IRQ_EN_MASK, - reg_info->irq_en); - - /* Make sure writes to the H2C/C2H descriptors are synchronized - * before updating PIDX - */ - qdma_io_wmb(); - - qdma_reg_write(dev_hndl, reg_addr, reg_val); - - return QDMA_SUCCESS; -} - -/*****************************************************************************/ -/** - * qdma_queue_cmpt_cidx_update() - function to update the CMPT CIDX update - * - * @dev_hndl: device handle - * @is_vf: Whether PF or VF - * @qid: Queue id relative to the PF/VF calling this API - * @reg_info: data needed for the CIDX register update - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -int qdma_queue_cmpt_cidx_update(void *dev_hndl, uint8_t is_vf, - uint16_t qid, const struct qdma_q_cmpt_cidx_reg_info *reg_info) -{ - uint32_t reg_addr = (is_vf) ? QDMA_OFFSET_VF_DMAP_SEL_CMPT_CIDX : - QDMA_OFFSET_DMAP_SEL_CMPT_CIDX; - uint32_t reg_val = 0; - - if (!dev_hndl || !reg_info) { - qdma_log_error("%s: dev_handle (%p) reg_info (%p) , err:%d\n", - __func__, dev_hndl, reg_info, -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - reg_addr += (qid * QDMA_CMPT_CIDX_STEP); - - reg_val = - FIELD_SET(QDMA_DMAP_SEL_CMPT_WRB_CIDX_MASK, - reg_info->wrb_cidx) | - FIELD_SET(QDMA_DMAP_SEL_CMPT_CNT_THRESH_MASK, - reg_info->counter_idx) | - FIELD_SET(QDMA_DMAP_SEL_CMPT_TMR_CNT_MASK, - reg_info->timer_idx) | - FIELD_SET(QDMA_DMAP_SEL_CMPT_TRG_MODE_MASK, - reg_info->trig_mode) | - FIELD_SET(QDMA_DMAP_SEL_CMPT_STS_DESC_EN_MASK, - reg_info->wrb_en) | - FIELD_SET(QDMA_DMAP_SEL_CMPT_IRQ_EN_MASK, reg_info->irq_en); - - /* Make sure writes to the CMPT ring are synchronized - * before updating CIDX - */ - qdma_io_wmb(); - - qdma_reg_write(dev_hndl, reg_addr, reg_val); - - return QDMA_SUCCESS; -} - -/*****************************************************************************/ -/** - * qdma_queue_intr_cidx_update() - function to update the CMPT CIDX update - * - * @dev_hndl: device handle - * @is_vf: Whether PF or VF - * @qid: Queue id relative to the PF/VF calling this API - * @reg_info: data needed for the CIDX register update - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -int qdma_queue_intr_cidx_update(void *dev_hndl, uint8_t is_vf, - uint16_t qid, const struct qdma_intr_cidx_reg_info *reg_info) -{ - uint32_t reg_addr = (is_vf) ? QDMA_OFFSET_VF_DMAP_SEL_INT_CIDX : - QDMA_OFFSET_DMAP_SEL_INT_CIDX; - uint32_t reg_val = 0; - - if (!dev_hndl || !reg_info) { - qdma_log_error("%s: dev_handle (%p) reg_info (%p), err:%d\n", - __func__, dev_hndl, reg_info, -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - reg_addr += qid * QDMA_INT_CIDX_STEP; - - reg_val = - FIELD_SET(QDMA_DMA_SEL_INT_SW_CIDX_MASK, reg_info->sw_cidx) | - FIELD_SET(QDMA_DMA_SEL_INT_RING_IDX_MASK, reg_info->rng_idx); - - qdma_reg_write(dev_hndl, reg_addr, reg_val); - - return QDMA_SUCCESS; -} - -/*****************************************************************************/ -/** - * qdma_get_user_bar() - Function to get the - * AXI Master Lite(user bar) number - * - * @dev_hndl: device handle - * @is_vf: Whether PF or VF - * @func_id: function id of the PF - * @user_bar: pointer to hold the AXI Master Lite number - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -int qdma_get_user_bar(void *dev_hndl, uint8_t is_vf, - uint16_t func_id, uint8_t *user_bar) -{ - uint8_t bar_found = 0; - uint8_t bar_idx = 0; - uint32_t user_bar_id = 0; - uint32_t reg_addr = (is_vf) ? QDMA_OFFSET_VF_USER_BAR_ID : - QDMA_OFFSET_GLBL2_PF_BARLITE_EXT; - - if (!dev_hndl) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - if (!user_bar) { - qdma_log_error("%s: user_bar is NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - user_bar_id = qdma_reg_read(dev_hndl, reg_addr); - - if (!is_vf) - user_bar_id = (user_bar_id >> (6 * func_id)) & 0x3F; - else - user_bar_id = user_bar_id & 0x3F; - - for (bar_idx = 0; bar_idx < QDMA_BAR_NUM; bar_idx++) { - if (user_bar_id & (1 << bar_idx)) { - *user_bar = bar_idx; - bar_found = 1; - break; - } - } - if (bar_found == 0) { - *user_bar = 0; - qdma_log_error("%s: Bar not found, vf:%d, usrbar:%d, err:%d\n", - __func__, - is_vf, - *user_bar, - -QDMA_ERR_HWACC_BAR_NOT_FOUND); - return -QDMA_ERR_HWACC_BAR_NOT_FOUND; - } - - return QDMA_SUCCESS; -} - -/*****************************************************************************/ -/** - * qdma_get_device_attributes() - Function to get the qdma device attributes - * - * @dev_hndl: device handle - * @dev_info: pointer to hold the device info - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -int qdma_get_device_attributes(void *dev_hndl, - struct qdma_dev_attributes *dev_info) -{ - uint8_t count = 0; - uint32_t reg_val = 0; - - if (!dev_hndl) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - if (!dev_info) { - qdma_log_error("%s: dev_info is NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - /* number of PFs */ - reg_val = qdma_reg_read(dev_hndl, QDMA_OFFSET_GLBL2_PF_BARLITE_INT); - if (FIELD_GET(QDMA_GLBL2_PF0_BAR_MAP_MASK, reg_val)) - count++; - if (FIELD_GET(QDMA_GLBL2_PF1_BAR_MAP_MASK, reg_val)) - count++; - if (FIELD_GET(QDMA_GLBL2_PF2_BAR_MAP_MASK, reg_val)) - count++; - if (FIELD_GET(QDMA_GLBL2_PF3_BAR_MAP_MASK, reg_val)) - count++; - dev_info->num_pfs = count; - - /* Number of Qs */ - reg_val = qdma_reg_read(dev_hndl, QDMA_OFFSET_GLBL2_CHANNEL_QDMA_CAP); - dev_info->num_qs = FIELD_GET(QDMA_GLBL2_MULTQ_MAX_MASK, reg_val); - - /* FLR present */ - reg_val = qdma_reg_read(dev_hndl, QDMA_OFFSET_GLBL2_MISC_CAP); - dev_info->mailbox_en = FIELD_GET(QDMA_GLBL2_MAILBOX_EN_MASK, reg_val); - dev_info->flr_present = FIELD_GET(QDMA_GLBL2_FLR_PRESENT_MASK, reg_val); - dev_info->mm_cmpt_en = FIELD_GET(QDMA_GLBL2_MM_CMPT_EN_MASK, reg_val); - - /* ST/MM enabled? */ - reg_val = qdma_reg_read(dev_hndl, QDMA_OFFSET_GLBL2_CHANNEL_MDMA); - dev_info->mm_en = (FIELD_GET(QDMA_GLBL2_MM_C2H_MASK, reg_val) - && FIELD_GET(QDMA_GLBL2_MM_H2C_MASK, reg_val)) ? 1 : 0; - dev_info->st_en = (FIELD_GET(QDMA_GLBL2_ST_C2H_MASK, reg_val) - && FIELD_GET(QDMA_GLBL2_ST_H2C_MASK, reg_val)) ? 1 : 0; - - /* num of mm channels */ - /* TODO : Register not yet defined for this. Hard coding it to 1.*/ - dev_info->mm_channel_max = 1; - - dev_info->debug_mode = 0; - dev_info->desc_eng_mode = 0; - dev_info->qid2vec_ctx = 0; - dev_info->cmpt_ovf_chk_dis = 1; - dev_info->mailbox_intr = 1; - dev_info->sw_desc_64b = 1; - dev_info->cmpt_desc_64b = 1; - dev_info->dynamic_bar = 1; - dev_info->legacy_intr = 1; - dev_info->cmpt_trig_count_timer = 1; - - return QDMA_SUCCESS; -} - -/*****************************************************************************/ -/** - * qdma_hw_ram_sbe_err_process() - Function to dump SBE error debug information - * - * @dev_hndl: device handle - * @buf: Bufffer for the debug info to be dumped in - * @buflen: Length of the buffer - * - * Return: void - *****************************************************************************/ -static void qdma_hw_ram_sbe_err_process(void *dev_hndl) -{ - qdma_dump_reg_info(dev_hndl, QDMA_OFFSET_RAM_SBE_STAT, - 1, NULL, 0); -} - -/*****************************************************************************/ -/** - * qdma_hw_ram_dbe_err_process() - Function to dump DBE error debug information - * - * @dev_hndl: device handle - * @buf: Bufffer for the debug info to be dumped in - * @buflen: Length of the buffer - * - * Return: void - *****************************************************************************/ -static void qdma_hw_ram_dbe_err_process(void *dev_hndl) -{ - qdma_dump_reg_info(dev_hndl, QDMA_OFFSET_RAM_DBE_STAT, - 1, NULL, 0); -} - -/*****************************************************************************/ -/** - * qdma_hw_desc_err_process() - Function to dump Descriptor Error information - * - * @dev_hndl: device handle - * @buf: Bufffer for the debug info to be dumped in - * @buflen: Length of the buffer - * - * Return: void - *****************************************************************************/ -static void qdma_hw_desc_err_process(void *dev_hndl) -{ - int i = 0; - uint32_t desc_err_reg_list[] = { - QDMA_OFFSET_GLBL_DSC_ERR_STS, - QDMA_OFFSET_GLBL_DSC_ERR_LOG0, - QDMA_OFFSET_GLBL_DSC_ERR_LOG1, - QDMA_OFFSET_GLBL_DSC_DBG_DAT0, - QDMA_OFFSET_GLBL_DSC_DBG_DAT1, - QDMA_OFFSET_GLBL_DSC_ERR_LOG2 - }; - int desc_err_num_regs = sizeof(desc_err_reg_list)/sizeof(uint32_t); - - for (i = 0; i < desc_err_num_regs; i++) { - qdma_dump_reg_info(dev_hndl, desc_err_reg_list[i], - 1, NULL, 0); - } -} - -/*****************************************************************************/ -/** - * qdma_hw_trq_err_process() - Function to dump Target Access Error information - * - * @dev_hndl: device handle - * @buf: Bufffer for the debug info to be dumped in - * @buflen: Length of the buffer - * - * Return: void - *****************************************************************************/ -static void qdma_hw_trq_err_process(void *dev_hndl) -{ - int i = 0; - uint32_t trq_err_reg_list[] = { - QDMA_OFFSET_GLBL_TRQ_ERR_STS, - QDMA_OFFSET_GLBL_TRQ_ERR_LOG - }; - int trq_err_reg_num_regs = sizeof(trq_err_reg_list)/sizeof(uint32_t); - - for (i = 0; i < trq_err_reg_num_regs; i++) { - qdma_dump_reg_info(dev_hndl, trq_err_reg_list[i], - 1, NULL, 0); - } - - -} - -/*****************************************************************************/ -/** - * qdma_hw_st_h2c_err_process() - Function to dump MM H2C Error information - * - * @dev_hndl: device handle - * @buf: Bufffer for the debug info to be dumped in - * @buflen: Length of the buffer - * - * Return: void - *****************************************************************************/ -static void qdma_hw_st_h2c_err_process(void *dev_hndl) -{ - int i = 0; - uint32_t st_h2c_err_reg_list[] = { - QDMA_OFFSET_H2C_ERR_STAT, - QDMA_OFFSET_H2C_FIRST_ERR_QID, - QDMA_OFFSET_H2C_DBG_REG0, - QDMA_OFFSET_H2C_DBG_REG1, - QDMA_OFFSET_H2C_DBG_REG2, - QDMA_OFFSET_H2C_DBG_REG3, - QDMA_OFFSET_H2C_DBG_REG4 - }; - int st_h2c_err_num_regs = sizeof(st_h2c_err_reg_list)/sizeof(uint32_t); - - for (i = 0; i < st_h2c_err_num_regs; i++) { - qdma_dump_reg_info(dev_hndl, st_h2c_err_reg_list[i], - 1, NULL, 0); - } -} - - -/*****************************************************************************/ -/** - * qdma_hw_st_c2h_err_process() - Function to dump MM H2C Error information - * - * @dev_hndl: device handle - * @buf: Bufffer for the debug info to be dumped in - * @buflen: Length of the buffer - * - * Return: void - *****************************************************************************/ -static void qdma_hw_st_c2h_err_process(void *dev_hndl) -{ - int i = 0; - uint32_t st_c2h_err_reg_list[] = { - QDMA_OFFSET_C2H_ERR_STAT, - QDMA_OFFSET_C2H_FATAL_ERR_STAT, - QDMA_OFFSET_C2H_FIRST_ERR_QID, - QDMA_OFFSET_C2H_STAT_S_AXIS_C2H_ACCEPTED, - QDMA_OFFSET_C2H_STAT_S_AXIS_CMPT_ACCEPTED, - QDMA_OFFSET_C2H_STAT_DESC_RSP_PKT_ACCEPTED, - QDMA_OFFSET_C2H_STAT_AXIS_PKG_CMP, - QDMA_OFFSET_C2H_STAT_DEBUG_DMA_ENG_0, - QDMA_OFFSET_C2H_STAT_DEBUG_DMA_ENG_1, - QDMA_OFFSET_C2H_STAT_DEBUG_DMA_ENG_2, - QDMA_OFFSET_C2H_STAT_DEBUG_DMA_ENG_3, - QDMA_OFFSET_C2H_STAT_DESC_RSP_DROP_ACCEPTED, - QDMA_OFFSET_C2H_STAT_DESC_RSP_ERR_ACCEPTED - }; - int st_c2h_err_num_regs = sizeof(st_c2h_err_reg_list)/sizeof(uint32_t); - - for (i = 0; i < st_c2h_err_num_regs; i++) { - qdma_dump_reg_info(dev_hndl, st_c2h_err_reg_list[i], - 1, NULL, 0); - } -} - - -/*****************************************************************************/ -/** - * qdma_hw_get_error_name() - Function to get the error in string format - * - * @err_idx: error index - * - * Return: string - success and NULL on failure - *****************************************************************************/ -const char *qdma_hw_get_error_name(uint32_t err_idx) -{ - if (err_idx >= QDMA_ERRS_ALL) { - qdma_log_error("%s: err_idx=%d is invalid, returning NULL\n", - __func__, (enum qdma_error_idx)err_idx); - return NULL; - } - - return qdma_err_info[(enum qdma_error_idx)err_idx].err_name; -} - -/*****************************************************************************/ -/** - * qdma_hw_error_process() - Function to find the error that got - * triggered and call the handler qdma_hw_error_handler of that - * particular error. - * - * @dev_hndl: device handle - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -int qdma_hw_error_process(void *dev_hndl) -{ - uint32_t glbl_err_stat = 0, err_stat = 0; - uint32_t bit = 0, i = 0; - int32_t idx = 0; - struct qdma_dev_attributes dev_cap; - uint32_t hw_err_position[TOTAL_LEAF_ERROR_AGGREGATORS] = { - QDMA_DSC_ERR_POISON, - QDMA_TRQ_ERR_UNMAPPED, - QDMA_ST_C2H_ERR_MTY_MISMATCH, - QDMA_ST_FATAL_ERR_MTY_MISMATCH, - QDMA_ST_H2C_ERR_ZERO_LEN_DESC, - QDMA_SBE_ERR_MI_H2C0_DAT, - QDMA_DBE_ERR_MI_H2C0_DAT - }; - - if (!dev_hndl) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - qdma_get_device_attributes(dev_hndl, &dev_cap); - - glbl_err_stat = qdma_reg_read(dev_hndl, QDMA_OFFSET_GLBL_ERR_STAT); - if (!glbl_err_stat) - return QDMA_HW_ERR_NOT_DETECTED; - - qdma_log_info("addr = 0x%08x val = 0x%08x", - QDMA_OFFSET_GLBL_ERR_STAT, - glbl_err_stat); - for (i = 0; i < TOTAL_LEAF_ERROR_AGGREGATORS; i++) { - bit = hw_err_position[i]; - - if ((!dev_cap.st_en) && (bit == QDMA_ST_C2H_ERR_MTY_MISMATCH || - bit == QDMA_ST_FATAL_ERR_MTY_MISMATCH || - bit == QDMA_ST_H2C_ERR_ZERO_LEN_DESC)) - continue; - - err_stat = qdma_reg_read(dev_hndl, - qdma_err_info[bit].stat_reg_addr); - - if (err_stat) { - qdma_log_info("addr = 0x%08x val = 0x%08x", - qdma_err_info[bit].stat_reg_addr, - err_stat); - - qdma_err_info[bit].qdma_hw_err_process( - dev_hndl); - - for (idx = bit; idx < all_hw_errs[i]; idx++) { - /* call the platform specific handler */ - if (err_stat & qdma_err_info[idx].leaf_err_mask) - qdma_log_error("%s detected %s", - __func__, - qdma_hw_get_error_name(idx)); - } - - qdma_reg_write(dev_hndl, - qdma_err_info[bit].stat_reg_addr, - err_stat); - - } - - } - - /* Write 1 to the global status register to clear the bits */ - qdma_reg_write(dev_hndl, QDMA_OFFSET_GLBL_ERR_STAT, glbl_err_stat); - - return QDMA_SUCCESS; -} - - -/*****************************************************************************/ -/** - * qdma_hw_error_enable() - Function to enable all or a specific error - * - * @dev_hndl: device handle - * @err_idx: error index - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -int qdma_hw_error_enable(void *dev_hndl, uint32_t err_idx) -{ - uint32_t idx = 0, i = 0; - uint32_t reg_val = 0; - struct qdma_dev_attributes dev_cap; - - if (!dev_hndl) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - if (err_idx > QDMA_ERRS_ALL) { - qdma_log_error("%s: err_idx=%d is invalid, err:%d\n", - __func__, err_idx, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - qdma_get_device_attributes(dev_hndl, &dev_cap); - - if (err_idx == QDMA_ERRS_ALL) { - for (i = 0; i < TOTAL_LEAF_ERROR_AGGREGATORS; i++) { - - idx = all_hw_errs[i]; - - /* Don't access streaming registers in - * MM only bitstreams - */ - if (!dev_cap.st_en) { - if (idx == QDMA_ST_C2H_ERR_ALL || - idx == QDMA_ST_FATAL_ERR_ALL || - idx == QDMA_ST_H2C_ERR_ALL) - continue; - } - - reg_val = qdma_err_info[idx].leaf_err_mask; - qdma_reg_write(dev_hndl, - qdma_err_info[idx].mask_reg_addr, reg_val); - - reg_val = qdma_reg_read(dev_hndl, - QDMA_OFFSET_GLBL_ERR_MASK); - reg_val |= FIELD_SET( - qdma_err_info[idx].global_err_mask, 1); - qdma_reg_write(dev_hndl, QDMA_OFFSET_GLBL_ERR_MASK, - reg_val); - } - - } else { - /* Don't access streaming registers in MM only bitstreams - * QDMA_C2H_ERR_MTY_MISMATCH to QDMA_H2C_ERR_ALL are all - * ST errors - */ - if (!dev_cap.st_en) { - if (err_idx >= QDMA_ST_C2H_ERR_MTY_MISMATCH && - err_idx <= QDMA_ST_H2C_ERR_ALL) - return QDMA_SUCCESS; - } - - reg_val = qdma_reg_read(dev_hndl, - qdma_err_info[err_idx].mask_reg_addr); - reg_val |= FIELD_SET(qdma_err_info[err_idx].leaf_err_mask, 1); - qdma_reg_write(dev_hndl, - qdma_err_info[err_idx].mask_reg_addr, reg_val); - - reg_val = qdma_reg_read(dev_hndl, QDMA_OFFSET_GLBL_ERR_MASK); - reg_val |= FIELD_SET(qdma_err_info[err_idx].global_err_mask, 1); - qdma_reg_write(dev_hndl, QDMA_OFFSET_GLBL_ERR_MASK, reg_val); - } - - return QDMA_SUCCESS; -} - - -/*****************************************************************************/ -/** - * qdma_soft_dump_config_regs() - Function to get qdma config register dump in a - * buffer - * - * @dev_hndl: device handle - * @is_vf: Whether PF or VF - * @buf : pointer to buffer to be filled - * @buflen : Length of the buffer - * - * Return: Length up-till the buffer is filled -success and < 0 - failure - *****************************************************************************/ -int qdma_soft_dump_config_regs(void *dev_hndl, uint8_t is_vf, - char *buf, uint32_t buflen) -{ - uint32_t i = 0, j = 0; - struct xreg_info *reg_info; - uint32_t num_regs = - sizeof(qdma_config_regs) / sizeof((qdma_config_regs)[0]); - uint32_t len = 0, val = 0; - int rv = QDMA_SUCCESS; - char name[DEBGFS_GEN_NAME_SZ] = ""; - struct qdma_dev_attributes dev_cap; - - if (!dev_hndl) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - if (buflen < qdma_soft_reg_dump_buf_len()) { - qdma_log_error("%s: Buffer too small, err:%d\n", - __func__, -QDMA_ERR_NO_MEM); - return -QDMA_ERR_NO_MEM; - } - - if (is_vf) { - qdma_log_error("%s: Wrong API used for VF, err:%d\n", - __func__, - -QDMA_ERR_HWACC_FEATURE_NOT_SUPPORTED); - return -QDMA_ERR_HWACC_FEATURE_NOT_SUPPORTED; - } - - qdma_get_device_attributes(dev_hndl, &dev_cap); - - reg_info = qdma_config_regs; - for (i = 0; i < num_regs; i++) { - if ((GET_CAPABILITY_MASK(dev_cap.mm_en, dev_cap.st_en, - dev_cap.mm_cmpt_en, dev_cap.mailbox_en) - & reg_info[i].mode) == 0) - continue; - - for (j = 0; j < reg_info[i].repeat; j++) { - rv = QDMA_SNPRINTF_S(name, DEBGFS_GEN_NAME_SZ, - DEBGFS_GEN_NAME_SZ, - "%s_%d", reg_info[i].name, j); - if ((rv < 0) || (rv > DEBGFS_GEN_NAME_SZ)) { - qdma_log_error( - "%d:%s QDMA_SNPRINTF_S() failed, err:%d\n", - __LINE__, __func__, - rv); - return -QDMA_ERR_NO_MEM; - } - val = qdma_reg_read(dev_hndl, - (reg_info[i].addr + (j * 4))); - rv = dump_reg(buf + len, buflen - len, - (reg_info[i].addr + (j * 4)), - name, val); - if (rv < 0) { - qdma_log_error( - "%s Buff too small, err:%d\n", - __func__, - -QDMA_ERR_NO_MEM); - return -QDMA_ERR_NO_MEM; - } - len += rv; - } - } - - return len; -} - -/* - * qdma_fill_intr_ctxt() - Helper function to fill interrupt context - * into structure - * - */ -static void qdma_fill_intr_ctxt(struct qdma_indirect_intr_ctxt *intr_ctxt) -{ - ind_intr_ctxt_entries[0].value = intr_ctxt->valid; - ind_intr_ctxt_entries[1].value = intr_ctxt->vec; - ind_intr_ctxt_entries[2].value = intr_ctxt->int_st; - ind_intr_ctxt_entries[3].value = intr_ctxt->color; - ind_intr_ctxt_entries[4].value = - intr_ctxt->baddr_4k & 0xFFFFFFFF; - ind_intr_ctxt_entries[5].value = - (intr_ctxt->baddr_4k >> 32) & 0xFFFFFFFF; - ind_intr_ctxt_entries[6].value = intr_ctxt->page_size; - ind_intr_ctxt_entries[7].value = intr_ctxt->pidx; - ind_intr_ctxt_entries[8].value = intr_ctxt->at; -} - - -static uint32_t qdma_intr_context_buf_len(void) -{ - uint32_t len = 0; - - len += (((sizeof(ind_intr_ctxt_entries) / - sizeof(ind_intr_ctxt_entries[0])) + 1) * - REG_DUMP_SIZE_PER_LINE); - return len; -} - -/* - * dump_intr_context() - Helper function to dump interrupt context into string - * - * return len - length of the string copied into buffer - */ -static int dump_intr_context(struct qdma_indirect_intr_ctxt *intr_ctx, - int ring_index, - char *buf, int buf_sz) -{ - int i = 0; - int n; - int len = 0; - int rv; - char banner[DEBGFS_LINE_SZ]; - - qdma_fill_intr_ctxt(intr_ctx); - - for (i = 0; i < DEBGFS_LINE_SZ - 5; i++) { - rv = QDMA_SNPRINTF_S(banner + i, - (DEBGFS_LINE_SZ - i), - sizeof("-"), "-"); - if ((rv < 0) || (rv > (int)sizeof("-"))) { - qdma_log_error( - "%d:%s QDMA_SNPRINTF_S() failed, err:%d\n", - __LINE__, __func__, - rv); - goto INSUF_BUF_EXIT; - } - } - - /* Interrupt context dump */ - n = sizeof(ind_intr_ctxt_entries) / - sizeof((ind_intr_ctxt_entries)[0]); - for (i = 0; i < n; i++) { - if ((len >= buf_sz) || ((len + DEBGFS_LINE_SZ) >= buf_sz)) - goto INSUF_BUF_EXIT; - - if (i == 0) { - if ((len + (3 * DEBGFS_LINE_SZ)) >= buf_sz) - goto INSUF_BUF_EXIT; - - rv = QDMA_SNPRINTF_S(buf + len, (buf_sz - len), - DEBGFS_LINE_SZ, "\n%s", banner); - if ((rv < 0) || (rv > DEBGFS_LINE_SZ)) { - qdma_log_error( - "%d:%s QDMA_SNPRINTF_S() failed, err:%d\n", - __LINE__, __func__, - rv); - goto INSUF_BUF_EXIT; - } - len += rv; - - rv = QDMA_SNPRINTF_S(buf + len, (buf_sz - len), - DEBGFS_LINE_SZ, "\n%50s %d", - "Interrupt Context for ring#", ring_index); - if ((rv < 0) || (rv > DEBGFS_LINE_SZ)) { - qdma_log_error( - "%d:%s QDMA_SNPRINTF_S() failed, err:%d\n", - __LINE__, __func__, - rv); - goto INSUF_BUF_EXIT; - } - len += rv; - - rv = QDMA_SNPRINTF_S(buf + len, (buf_sz - len), - DEBGFS_LINE_SZ, "\n%s\n", banner); - if ((rv < 0) || (rv > DEBGFS_LINE_SZ)) { - qdma_log_error( - "%d:%s QDMA_SNPRINTF_S() failed, err:%d\n", - __LINE__, __func__, - rv); - goto INSUF_BUF_EXIT; - } - len += rv; - } - - rv = QDMA_SNPRINTF_S(buf + len, (buf_sz - len), DEBGFS_LINE_SZ, - "%-47s %#-10x %u\n", - ind_intr_ctxt_entries[i].name, - ind_intr_ctxt_entries[i].value, - ind_intr_ctxt_entries[i].value); - if ((rv < 0) || (rv > DEBGFS_LINE_SZ)) { - qdma_log_error( - "%d:%s QDMA_SNPRINTF_S() failed, err:%d\n", - __LINE__, __func__, - rv); - goto INSUF_BUF_EXIT; - } - len += rv; - } - - return len; - -INSUF_BUF_EXIT: - if (buf_sz > DEBGFS_LINE_SZ) { - rv = QDMA_SNPRINTF_S((buf + buf_sz - DEBGFS_LINE_SZ), - buf_sz, DEBGFS_LINE_SZ, - "\n\nInsufficient buffer size, partial context dump\n"); - if ((rv < 0) || (rv > DEBGFS_LINE_SZ)) { - qdma_log_error( - "%d:%s QDMA_SNPRINTF_S() failed, err:%d\n", - __LINE__, __func__, - rv); - } - } - - qdma_log_error("%s: Insufficient buffer size, err:%d\n", - __func__, -QDMA_ERR_NO_MEM); - - return -QDMA_ERR_NO_MEM; -} - - -/*****************************************************************************/ -/** - * qdma_dump_intr_context() - Function to get qdma interrupt context dump in a - * buffer - * - * @dev_hndl: device handle - * @hw_qid: queue id - * @buf : pointer to buffer to be filled - * @buflen : Length of the buffer - * - * Return: Length up-till the buffer is filled -success and < 0 - failure - *****************************************************************************/ -int qdma_dump_intr_context(void *dev_hndl, - struct qdma_indirect_intr_ctxt *intr_ctx, - int ring_index, - char *buf, uint32_t buflen) -{ - int rv = 0; - uint32_t req_buflen = 0; - - if (!dev_hndl) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - - return -QDMA_ERR_INV_PARAM; - } - - if (!buf) { - qdma_log_error("%s: buf is NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - - return -QDMA_ERR_INV_PARAM; - } - - if (!intr_ctx) { - qdma_log_error("%s: intr_ctx is NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - - return -QDMA_ERR_INV_PARAM; - } - - req_buflen = qdma_intr_context_buf_len(); - if (buflen < req_buflen) { - qdma_log_error("%s: Too small buffer(%d), reqd(%d), err:%d\n", - __func__, buflen, req_buflen, -QDMA_ERR_NO_MEM); - return -QDMA_ERR_NO_MEM; - } - - rv = dump_intr_context(intr_ctx, ring_index, buf, buflen); - - return rv; -} - -/*****************************************************************************/ -/** - * qdma_soft_dump_queue_context() - Function to get qdma queue context dump in a - * buffer - * - * @dev_hndl: device handle - * @st: Queue Mode (ST or MM) - * @q_type: Queue Type - * @ctxt_data: Context Data - * @buf : pointer to buffer to be filled - * @buflen : Length of the buffer - * - * Return: Length up-till the buffer is filled -success and < 0 - failure - *****************************************************************************/ -int qdma_soft_dump_queue_context(void *dev_hndl, - uint8_t st, - enum qdma_dev_q_type q_type, - struct qdma_descq_context *ctxt_data, - char *buf, uint32_t buflen) -{ - int rv = 0; - uint32_t req_buflen = 0; - - if (!dev_hndl) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - - return -QDMA_ERR_INV_PARAM; - } - - if (!ctxt_data) { - qdma_log_error("%s: ctxt_data is NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - - return -QDMA_ERR_INV_PARAM; - } - - if (!buf) { - qdma_log_error("%s: buf is NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - - return -QDMA_ERR_INV_PARAM; - } - if (q_type >= QDMA_DEV_Q_TYPE_MAX) { - qdma_log_error("%s: invalid q_type, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - - return -QDMA_ERR_INV_PARAM; - } - - rv = qdma_soft_context_buf_len(st, q_type, &req_buflen); - if (rv != QDMA_SUCCESS) - return rv; - - if (buflen < req_buflen) { - qdma_log_error( - "%s: Too small buffer(%d), reqd(%d), err:%d\n", - __func__, buflen, req_buflen, -QDMA_ERR_NO_MEM); - return -QDMA_ERR_NO_MEM; - } - - rv = dump_soft_context(ctxt_data, st, q_type, buf, buflen); - - return rv; -} - -/*****************************************************************************/ -/** - * qdma_read_dump_queue_context() - Function to read and dump the queue - * context in the user-provided buffer. This API is valid only for PF and - * should not be used for VFs. For VF's use qdma_dump_queue_context() API - * after reading the context through mailbox. - * - * @dev_hndl: device handle - * @is_vf: VF or PF - * @hw_qid: queue id - * @st: Queue Mode(ST or MM) - * @q_type: Queue type(H2C/C2H/CMPT)* - * @buf : pointer to buffer to be filled - * @buflen : Length of the buffer - * - * Return: Length up-till the buffer is filled -success and < 0 - failure - *****************************************************************************/ -int qdma_soft_read_dump_queue_context(void *dev_hndl, - uint16_t func_id, - uint16_t qid_hw, - uint8_t st, - enum qdma_dev_q_type q_type, - char *buf, uint32_t buflen) -{ - int rv = QDMA_SUCCESS; - uint32_t req_buflen = 0; - struct qdma_descq_context context; - - if (!dev_hndl) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - - return -QDMA_ERR_INV_PARAM; - } - - if (!buf) { - qdma_log_error("%s: buf is NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - - return -QDMA_ERR_INV_PARAM; - } - - if (q_type >= QDMA_DEV_Q_TYPE_MAX) { - qdma_log_error("%s: Not supported for q_type, err = %d\n", - __func__, -QDMA_ERR_INV_PARAM); - - return -QDMA_ERR_INV_PARAM; - } - - rv = qdma_soft_context_buf_len(st, q_type, &req_buflen); - - if (rv != QDMA_SUCCESS) - return rv; - - if (buflen < req_buflen) { - qdma_log_error( - "%s: Too small buffer(%d), reqd(%d), err:%d\n", - __func__, buflen, req_buflen, -QDMA_ERR_NO_MEM); - return -QDMA_ERR_NO_MEM; - } - - qdma_memset(&context, 0, sizeof(struct qdma_descq_context)); - - if (q_type != QDMA_DEV_Q_TYPE_CMPT) { - rv = qdma_sw_ctx_conf(dev_hndl, (uint8_t)q_type, qid_hw, - &(context.sw_ctxt), - QDMA_HW_ACCESS_READ); - if (rv < 0) { - qdma_log_error("%s:sw ctxt read fail, err = %d", - __func__, rv); - return rv; - } - - rv = qdma_hw_ctx_conf(dev_hndl, (uint8_t)q_type, qid_hw, - &(context.hw_ctxt), - QDMA_HW_ACCESS_READ); - if (rv < 0) { - qdma_log_error("%s:hw ctxt read fail, err = %d", - __func__, rv); - return rv; - } - - rv = qdma_credit_ctx_conf(dev_hndl, (uint8_t)q_type, - qid_hw, - &(context.cr_ctxt), - QDMA_HW_ACCESS_READ); - if (rv < 0) { - qdma_log_error("%s:cr ctxt read fail, err = %d", - __func__, rv); - return rv; - } - - if (st && (q_type == QDMA_DEV_Q_TYPE_C2H)) { - rv = qdma_pfetch_ctx_conf(dev_hndl, - qid_hw, &(context.pfetch_ctxt), - QDMA_HW_ACCESS_READ); - if (rv < 0) { - qdma_log_error( - "%s:pftch ctxt read fail, err = %d", - __func__, rv); - return rv; - } - } - } - - if ((st && (q_type == QDMA_DEV_Q_TYPE_C2H)) || - (!st && (q_type == QDMA_DEV_Q_TYPE_CMPT))) { - rv = qdma_cmpt_ctx_conf(dev_hndl, qid_hw, - &(context.cmpt_ctxt), - QDMA_HW_ACCESS_READ); - if (rv < 0) { - qdma_log_error( - "%s:cmpt ctxt read fail, err = %d", - __func__, rv); - return rv; - } - } - - rv = qdma_fmap_conf(dev_hndl, func_id, - &(context.fmap), - QDMA_HW_ACCESS_READ); - if (rv < 0) { - qdma_log_error( - "%s:fmap ctxt read fail, err = %d", - __func__, rv); - return rv; - } - - rv = dump_soft_context(&context, st, q_type, buf, buflen); - - return rv; -} -/*****************************************************************************/ -/** - * qdma_is_legacy_intr_pend() - function to get legacy_intr_pending status bit - * - * @dev_hndl: device handle - * - * Return: legacy interrupt pending status bit value - *****************************************************************************/ -int qdma_is_legacy_intr_pend(void *dev_hndl) -{ - uint32_t reg_val; - - if (!dev_hndl) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - reg_val = qdma_reg_read(dev_hndl, QDMA_OFFSET_GLBL_INTERRUPT_CFG); - if (FIELD_GET(QDMA_GLBL_INTR_LGCY_INTR_PEND_MASK, reg_val)) - return QDMA_SUCCESS; - - qdma_log_error("%s: no pending legacy intr, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_HWACC_NO_PEND_LEGCY_INTR; -} - -/*****************************************************************************/ -/** - * qdma_clear_pend_legacy_intr() - function to clear legacy_intr_pending bit - * - * @dev_hndl: device handle - * - * Return: void - *****************************************************************************/ -int qdma_clear_pend_legacy_intr(void *dev_hndl) -{ - uint32_t reg_val; - - if (!dev_hndl) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - reg_val = qdma_reg_read(dev_hndl, QDMA_OFFSET_GLBL_INTERRUPT_CFG); - reg_val |= FIELD_SET(QDMA_GLBL_INTR_LGCY_INTR_PEND_MASK, 1); - qdma_reg_write(dev_hndl, QDMA_OFFSET_GLBL_INTERRUPT_CFG, reg_val); - - return QDMA_SUCCESS; -} - -/*****************************************************************************/ -/** - * qdma_legacy_intr_conf() - function to disable/enable legacy interrupt - * - * @dev_hndl: device handle - * @enable: enable/disable flag. 1 - enable, 0 - disable - * - * Return: void - *****************************************************************************/ -int qdma_legacy_intr_conf(void *dev_hndl, enum status_type enable) -{ - uint32_t reg_val; - - if (!dev_hndl) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - reg_val = qdma_reg_read(dev_hndl, QDMA_OFFSET_GLBL_INTERRUPT_CFG); - reg_val |= FIELD_SET(QDMA_GLBL_INTR_CFG_EN_LGCY_INTR_MASK, enable); - qdma_reg_write(dev_hndl, QDMA_OFFSET_GLBL_INTERRUPT_CFG, reg_val); - - return QDMA_SUCCESS; -} - -/*****************************************************************************/ -/** - * qdma_init_ctxt_memory() - function to initialize the context memory - * - * @dev_hndl: device handle - * - * Return: returns the platform specific error code - *****************************************************************************/ -int qdma_init_ctxt_memory(void *dev_hndl) -{ -#ifdef ENABLE_INIT_CTXT_MEMORY - uint32_t data[QDMA_REG_IND_CTXT_REG_COUNT]; - uint16_t i = 0; - struct qdma_dev_attributes dev_info; - - if (!dev_hndl) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - qdma_memset(data, 0, sizeof(uint32_t) * QDMA_REG_IND_CTXT_REG_COUNT); - qdma_get_device_attributes(dev_hndl, &dev_info); - - for (; i < dev_info.num_qs; i++) { - int sel = QDMA_CTXT_SEL_SW_C2H; - int rv; - - for (; sel <= QDMA_CTXT_SEL_PFTCH; sel++) { - /** if the st mode(h2c/c2h) not enabled - * in the design, then skip the PFTCH - * and CMPT context setup - */ - if ((dev_info.st_en == 0) && - ((sel == QDMA_CTXT_SEL_PFTCH) || - (sel == QDMA_CTXT_SEL_CMPT))) { - qdma_log_debug("%s: ST context is skipped:", - __func__); - qdma_log_debug("sel = %d\n", sel); - continue; - } - - rv = qdma_indirect_reg_clear(dev_hndl, - (enum ind_ctxt_cmd_sel)sel, i); - if (rv < 0) - return rv; - } - } - - /* fmap */ - for (i = 0; i < dev_info.num_pfs; i++) - qdma_indirect_reg_clear(dev_hndl, - QDMA_CTXT_SEL_FMAP, i); - -#else - if (!dev_hndl) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } -#endif - return QDMA_SUCCESS; - -} - -static int get_reg_entry(uint32_t reg_addr, int *reg_entry) -{ - uint32_t i = 0; - struct xreg_info *reg_info; - uint32_t num_regs = - sizeof(qdma_config_regs)/ - sizeof((qdma_config_regs)[0]); - - reg_info = qdma_config_regs; - - for (i = 0; (i < num_regs - 1); i++) { - if (reg_info[i].addr == reg_addr) { - *reg_entry = i; - break; - } - } - - if (i >= num_regs - 1) { - qdma_log_error("%s: 0x%08x is missing register list, err:%d\n", - __func__, - reg_addr, - -QDMA_ERR_INV_PARAM); - *reg_entry = -1; - return -QDMA_ERR_INV_PARAM; - } - - return 0; -} - -/*****************************************************************************/ -/** - * qdma_soft_dump_config_reg_list() - Dump the registers - * - * @dev_hndl: device handle - * @total_regs : Max registers to read - * @reg_list : array of reg addr and reg values - * @buf : pointer to buffer to be filled - * @buflen : Length of the buffer - * - * Return: returns the platform specific error code - *****************************************************************************/ -int qdma_soft_dump_config_reg_list(void *dev_hndl, uint32_t total_regs, - struct qdma_reg_data *reg_list, char *buf, uint32_t buflen) -{ - uint32_t j = 0, len = 0; - uint32_t reg_count = 0; - int reg_data_entry; - int rv = 0; - char name[DEBGFS_GEN_NAME_SZ] = ""; - struct xreg_info *reg_info = qdma_config_regs; - - if (!dev_hndl) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - if (!buf) { - qdma_log_error("%s: buf is NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - for (reg_count = 0; - (reg_count < total_regs);) { - - rv = get_reg_entry(reg_list[reg_count].reg_addr, - ®_data_entry); - if (rv < 0) { - qdma_log_error("%s: register missing in list, err:%d\n", - __func__, - -QDMA_ERR_INV_PARAM); - return rv; - } - - for (j = 0; j < reg_info[reg_data_entry].repeat; j++) { - rv = QDMA_SNPRINTF_S(name, DEBGFS_GEN_NAME_SZ, - DEBGFS_GEN_NAME_SZ, - "%s_%d", - reg_info[reg_data_entry].name, j); - if ((rv < 0) || (rv > DEBGFS_GEN_NAME_SZ)) { - qdma_log_error( - "%d:%s snprintf failed, err:%d\n", - __LINE__, __func__, - rv); - return -QDMA_ERR_NO_MEM; - } - rv = dump_reg(buf + len, buflen - len, - (reg_info[reg_data_entry].addr + (j * 4)), - name, - reg_list[reg_count + j].reg_val); - if (rv < 0) { - qdma_log_error( - "%s Buff too small, err:%d\n", - __func__, - -QDMA_ERR_NO_MEM); - return -QDMA_ERR_NO_MEM; - } - len += rv; - } - reg_count += j; - } - - return len; -} - - -/*****************************************************************************/ -/** - * qdma_read_reg_list() - read the register values - * - * @dev_hndl: device handle - * @is_vf: Whether PF or VF - * @total_regs : Max registers to read - * @reg_list : array of reg addr and reg values - * - * Return: returns the platform specific error code - *****************************************************************************/ -int qdma_read_reg_list(void *dev_hndl, uint8_t is_vf, - uint16_t reg_rd_group, - uint16_t *total_regs, - struct qdma_reg_data *reg_list) -{ - uint16_t reg_count = 0, i = 0, j = 0; - struct xreg_info *reg_info; - uint32_t num_regs = - sizeof(qdma_config_regs)/ - sizeof((qdma_config_regs)[0]); - struct qdma_dev_attributes dev_cap; - uint32_t reg_start_addr = 0; - int reg_index = 0; - int rv = 0; - - if (!is_vf) { - qdma_log_error("%s: not supported for PF, err:%d\n", - __func__, - -QDMA_ERR_HWACC_FEATURE_NOT_SUPPORTED); - return -QDMA_ERR_HWACC_FEATURE_NOT_SUPPORTED; - } - - if (!dev_hndl) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - if (!reg_list) { - qdma_log_error("%s: reg_list is NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - qdma_get_device_attributes(dev_hndl, &dev_cap); - - switch (reg_rd_group) { - case QDMA_REG_READ_GROUP_1: - reg_start_addr = QDMA_REG_GROUP_1_START_ADDR; - break; - case QDMA_REG_READ_GROUP_2: - reg_start_addr = QDMA_REG_GROUP_2_START_ADDR; - break; - case QDMA_REG_READ_GROUP_3: - reg_start_addr = QDMA_REG_GROUP_3_START_ADDR; - break; - case QDMA_REG_READ_GROUP_4: - reg_start_addr = QDMA_REG_GROUP_4_START_ADDR; - break; - default: - qdma_log_error("%s: Invalid group received\n", - __func__); - return -QDMA_ERR_INV_PARAM; - } - - rv = get_reg_entry(reg_start_addr, ®_index); - if (rv < 0) { - qdma_log_error("%s: register missing in list, err:%d\n", - __func__, - -QDMA_ERR_INV_PARAM); - return rv; - } - reg_info = &qdma_config_regs[reg_index]; - - for (i = 0, reg_count = 0; - ((i < num_regs - 1 - reg_index) && - (reg_count < QDMA_MAX_REGISTER_DUMP)); i++) { - - if (((GET_CAPABILITY_MASK(dev_cap.mm_en, dev_cap.st_en, - dev_cap.mm_cmpt_en, dev_cap.mailbox_en) - & reg_info[i].mode) == 0) || - (reg_info[i].read_type == QDMA_REG_READ_PF_ONLY)) - continue; - - for (j = 0; j < reg_info[i].repeat && - (reg_count < QDMA_MAX_REGISTER_DUMP); - j++) { - reg_list[reg_count].reg_addr = - (reg_info[i].addr + (j * 4)); - reg_list[reg_count].reg_val = - qdma_reg_read(dev_hndl, - reg_list[reg_count].reg_addr); - reg_count++; - } - } - - *total_regs = reg_count; - return rv; -} - -/*****************************************************************************/ -/** - * qdma_write_global_ring_sizes() - function to set the global ring size array - * - * @dev_hndl: device handle - * @index: Index from where the values needs to written - * @count: number of entries to be written - * @glbl_rng_sz: pointer to the array having the values to write - * - * (index + count) shall not be more than 16 - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -static int qdma_write_global_ring_sizes(void *dev_hndl, uint8_t index, - uint8_t count, const uint32_t *glbl_rng_sz) -{ - if (!dev_hndl || !glbl_rng_sz || !count) { - qdma_log_error("%s: dev_hndl=%p glbl_rng_sz=%p, err:%d\n", - __func__, dev_hndl, glbl_rng_sz, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - if ((index + count) > QDMA_NUM_RING_SIZES) { - qdma_log_error("%s: index=%u count=%u > %d, err:%d\n", - __func__, index, count, - QDMA_NUM_RING_SIZES, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - qdma_write_csr_values(dev_hndl, QDMA_OFFSET_GLBL_RNG_SZ, index, count, - glbl_rng_sz); - - return QDMA_SUCCESS; -} - -/*****************************************************************************/ -/** - * qdma_read_global_ring_sizes() - function to get the global rng_sz array - * - * @dev_hndl: device handle - * @index: Index from where the values needs to read - * @count: number of entries to be read - * @glbl_rng_sz: pointer to array to hold the values read - * - * (index + count) shall not be more than 16 - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -static int qdma_read_global_ring_sizes(void *dev_hndl, uint8_t index, - uint8_t count, uint32_t *glbl_rng_sz) -{ - if (!dev_hndl || !glbl_rng_sz || !count) { - qdma_log_error("%s: dev_hndl=%p glbl_rng_sz=%p, err:%d\n", - __func__, dev_hndl, glbl_rng_sz, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - if ((index + count) > QDMA_NUM_RING_SIZES) { - qdma_log_error("%s: index=%u count=%u > %d, err:%d\n", - __func__, index, count, - QDMA_NUM_C2H_BUFFER_SIZES, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - qdma_read_csr_values(dev_hndl, QDMA_OFFSET_GLBL_RNG_SZ, index, count, - glbl_rng_sz); - - return QDMA_SUCCESS; -} - -/*****************************************************************************/ -/** - * qdma_write_global_timer_count() - function to set the timer values - * - * @dev_hndl: device handle - * @glbl_tmr_cnt: pointer to the array having the values to write - * @index: Index from where the values needs to written - * @count: number of entries to be written - * - * (index + count) shall not be more than 16 - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -static int qdma_write_global_timer_count(void *dev_hndl, uint8_t index, - uint8_t count, const uint32_t *glbl_tmr_cnt) -{ - struct qdma_dev_attributes dev_cap; - - - - if (!dev_hndl || !glbl_tmr_cnt || !count) { - qdma_log_error("%s: dev_hndl=%p glbl_tmr_cnt=%p, err:%d\n", - __func__, dev_hndl, glbl_tmr_cnt, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - if ((index + count) > QDMA_NUM_C2H_TIMERS) { - qdma_log_error("%s: index=%u count=%u > %d, err:%d\n", - __func__, index, count, - QDMA_NUM_C2H_TIMERS, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - qdma_get_device_attributes(dev_hndl, &dev_cap); - - if (dev_cap.st_en || dev_cap.mm_cmpt_en) - qdma_write_csr_values(dev_hndl, QDMA_OFFSET_C2H_TIMER_CNT, - index, count, glbl_tmr_cnt); - else { - qdma_log_error("%s: ST or MM cmpt not supported, err:%d\n", - __func__, - -QDMA_ERR_HWACC_FEATURE_NOT_SUPPORTED); - return -QDMA_ERR_HWACC_FEATURE_NOT_SUPPORTED; - } - - return QDMA_SUCCESS; -} - -/*****************************************************************************/ -/** - * qdma_read_global_timer_count() - function to get the timer values - * - * @dev_hndl: device handle - * @index: Index from where the values needs to read - * @count: number of entries to be read - * @glbl_tmr_cnt: pointer to array to hold the values read - * - * (index + count) shall not be more than 16 - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -static int qdma_read_global_timer_count(void *dev_hndl, uint8_t index, - uint8_t count, uint32_t *glbl_tmr_cnt) -{ - struct qdma_dev_attributes dev_cap; - - if (!dev_hndl || !glbl_tmr_cnt || !count) { - qdma_log_error("%s: dev_hndl=%p glbl_tmr_cnt=%p, err:%d\n", - __func__, dev_hndl, glbl_tmr_cnt, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - if ((index + count) > QDMA_NUM_C2H_TIMERS) { - qdma_log_error("%s: index=%u count=%u > %d, err:%d\n", - __func__, index, count, - QDMA_NUM_C2H_TIMERS, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - qdma_get_device_attributes(dev_hndl, &dev_cap); - - if (dev_cap.st_en || dev_cap.mm_cmpt_en) - qdma_read_csr_values(dev_hndl, - QDMA_OFFSET_C2H_TIMER_CNT, index, - count, glbl_tmr_cnt); - else { - qdma_log_error("%s: ST or MM cmpt not supported, err:%d\n", - __func__, - -QDMA_ERR_HWACC_FEATURE_NOT_SUPPORTED); - return -QDMA_ERR_HWACC_FEATURE_NOT_SUPPORTED; - } - - return QDMA_SUCCESS; -} - -/*****************************************************************************/ -/** - * qdma_write_global_counter_threshold() - function to set the counter - * threshold values - * - * @dev_hndl: device handle - * @index: Index from where the values needs to written - * @count: number of entries to be written - * @glbl_cnt_th: pointer to the array having the values to write - * - * (index + count) shall not be more than 16 - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -static int qdma_write_global_counter_threshold(void *dev_hndl, uint8_t index, - uint8_t count, const uint32_t *glbl_cnt_th) -{ - struct qdma_dev_attributes dev_cap; - - if (!dev_hndl || !glbl_cnt_th || !count) { - qdma_log_error("%s: dev_hndl=%p glbl_cnt_th=%p, err:%d\n", - __func__, dev_hndl, glbl_cnt_th, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - if ((index + count) > QDMA_NUM_C2H_COUNTERS) { - qdma_log_error("%s: index=%u count=%u > %d, err:%d\n", - __func__, index, count, - QDMA_NUM_C2H_BUFFER_SIZES, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - qdma_get_device_attributes(dev_hndl, &dev_cap); - - if (dev_cap.st_en || dev_cap.mm_cmpt_en) - qdma_write_csr_values(dev_hndl, QDMA_OFFSET_C2H_CNT_TH, index, - count, glbl_cnt_th); - else { - qdma_log_error("%s: ST or MM cmpt not supported, err:%d\n", - __func__, - -QDMA_ERR_HWACC_FEATURE_NOT_SUPPORTED); - return -QDMA_ERR_HWACC_FEATURE_NOT_SUPPORTED; - } - - return QDMA_SUCCESS; -} - -/*****************************************************************************/ -/** - * qdma_read_global_counter_threshold() - function to get the counter threshold - * values - * - * @dev_hndl: device handle - * @index: Index from where the values needs to read - * @count: number of entries to be read - * @glbl_cnt_th: pointer to array to hold the values read - * - * (index + count) shall not be more than 16 - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -static int qdma_read_global_counter_threshold(void *dev_hndl, uint8_t index, - uint8_t count, uint32_t *glbl_cnt_th) -{ - struct qdma_dev_attributes dev_cap; - - if (!dev_hndl || !glbl_cnt_th || !count) { - qdma_log_error("%s: dev_hndl=%p glbl_cnt_th=%p, err:%d\n", - __func__, dev_hndl, glbl_cnt_th, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - if ((index + count) > QDMA_NUM_C2H_COUNTERS) { - qdma_log_error("%s: index=%u count=%u > %d, err:%d\n", - __func__, index, count, - QDMA_NUM_C2H_COUNTERS, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - qdma_get_device_attributes(dev_hndl, &dev_cap); - - if (dev_cap.st_en || dev_cap.mm_cmpt_en) - qdma_read_csr_values(dev_hndl, QDMA_OFFSET_C2H_CNT_TH, index, - count, glbl_cnt_th); - else { - qdma_log_error("%s: ST or MM cmpt not supported, err:%d\n", - __func__, -QDMA_ERR_HWACC_FEATURE_NOT_SUPPORTED); - return -QDMA_ERR_HWACC_FEATURE_NOT_SUPPORTED; - } - - return QDMA_SUCCESS; -} - -/*****************************************************************************/ -/** - * qdma_write_global_buffer_sizes() - function to set the buffer sizes - * - * @dev_hndl: device handle - * @index: Index from where the values needs to written - * @count: number of entries to be written - * @glbl_buf_sz: pointer to the array having the values to write - * - * (index + count) shall not be more than 16 - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -static int qdma_write_global_buffer_sizes(void *dev_hndl, uint8_t index, - uint8_t count, const uint32_t *glbl_buf_sz) -{ - struct qdma_dev_attributes dev_cap; - - if (!dev_hndl || !glbl_buf_sz || !count) { - qdma_log_error("%s: dev_hndl=%p glbl_buf_sz=%p, err:%d\n", - __func__, dev_hndl, glbl_buf_sz, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - if ((index + count) > QDMA_NUM_C2H_BUFFER_SIZES) { - qdma_log_error("%s: index=%u count=%u > %d, err:%d\n", - __func__, index, count, - QDMA_NUM_C2H_BUFFER_SIZES, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - qdma_get_device_attributes(dev_hndl, &dev_cap); - - if (dev_cap.st_en) - qdma_write_csr_values(dev_hndl, QDMA_OFFSET_C2H_BUF_SZ, index, - count, glbl_buf_sz); - else { - qdma_log_error("%s: ST not supported, err:%d\n", - __func__, - -QDMA_ERR_HWACC_FEATURE_NOT_SUPPORTED); - return -QDMA_ERR_HWACC_FEATURE_NOT_SUPPORTED; - } - - return QDMA_SUCCESS; -} - -/*****************************************************************************/ -/** - * qdma_read_global_buffer_sizes() - function to get the buffer sizes - * - * @dev_hndl: device handle - * @index: Index from where the values needs to read - * @count: number of entries to be read - * @glbl_buf_sz: pointer to array to hold the values read - * - * (index + count) shall not be more than 16 - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -static int qdma_read_global_buffer_sizes(void *dev_hndl, uint8_t index, - uint8_t count, uint32_t *glbl_buf_sz) -{ - struct qdma_dev_attributes dev_cap; - - if (!dev_hndl || !glbl_buf_sz || !count) { - qdma_log_error("%s: dev_hndl=%p glbl_buf_sz=%p, err:%d\n", - __func__, dev_hndl, glbl_buf_sz, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - if ((index + count) > QDMA_NUM_C2H_BUFFER_SIZES) { - qdma_log_error("%s: index=%u count=%u > %d, err:%d\n", - __func__, index, count, - QDMA_NUM_C2H_BUFFER_SIZES, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - qdma_get_device_attributes(dev_hndl, &dev_cap); - - if (dev_cap.st_en) - qdma_read_csr_values(dev_hndl, QDMA_OFFSET_C2H_BUF_SZ, index, - count, glbl_buf_sz); - else { - qdma_log_error("%s: ST is not supported, err:%d\n", - __func__, - -QDMA_ERR_HWACC_FEATURE_NOT_SUPPORTED); - return -QDMA_ERR_HWACC_FEATURE_NOT_SUPPORTED; - } - - return QDMA_SUCCESS; -} - -/*****************************************************************************/ -/** - * qdma_global_csr_conf() - function to configure global csr - * - * @dev_hndl: device handle - * @index: Index from where the values needs to read - * @count: number of entries to be read - * @csr_val: uint32_t pointer to csr value - * @csr_type: Type of the CSR (qdma_global_csr_type enum) to configure - * @access_type HW access type (qdma_hw_access_type enum) value - * QDMA_HW_ACCESS_CLEAR - Not supported - * QDMA_HW_ACCESS_INVALIDATE - Not supported - * - * (index + count) shall not be more than 16 - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -int qdma_global_csr_conf(void *dev_hndl, uint8_t index, uint8_t count, - uint32_t *csr_val, - enum qdma_global_csr_type csr_type, - enum qdma_hw_access_type access_type) -{ - int rv = QDMA_SUCCESS; - - switch (csr_type) { - case QDMA_CSR_RING_SZ: - switch (access_type) { - case QDMA_HW_ACCESS_READ: - rv = qdma_read_global_ring_sizes( - dev_hndl, - index, - count, - csr_val); - break; - case QDMA_HW_ACCESS_WRITE: - rv = qdma_write_global_ring_sizes( - dev_hndl, - index, - count, - csr_val); - break; - default: - qdma_log_error("%s: access_type(%d) invalid, err:%d\n", - __func__, - access_type, - -QDMA_ERR_INV_PARAM); - rv = -QDMA_ERR_INV_PARAM; - break; - } - break; - case QDMA_CSR_TIMER_CNT: - switch (access_type) { - case QDMA_HW_ACCESS_READ: - rv = qdma_read_global_timer_count( - dev_hndl, - index, - count, - csr_val); - break; - case QDMA_HW_ACCESS_WRITE: - rv = qdma_write_global_timer_count( - dev_hndl, - index, - count, - csr_val); - break; - default: - qdma_log_error("%s: access_type(%d) invalid, err:%d\n", - __func__, - access_type, - -QDMA_ERR_INV_PARAM); - rv = -QDMA_ERR_INV_PARAM; - break; - } - break; - case QDMA_CSR_CNT_TH: - switch (access_type) { - case QDMA_HW_ACCESS_READ: - rv = - qdma_read_global_counter_threshold( - dev_hndl, - index, - count, - csr_val); - break; - case QDMA_HW_ACCESS_WRITE: - rv = - qdma_write_global_counter_threshold( - dev_hndl, - index, - count, - csr_val); - break; - default: - qdma_log_error("%s: access_type(%d) invalid, err:%d\n", - __func__, - access_type, - -QDMA_ERR_INV_PARAM); - rv = -QDMA_ERR_INV_PARAM; - break; - } - break; - case QDMA_CSR_BUF_SZ: - switch (access_type) { - case QDMA_HW_ACCESS_READ: - rv = - qdma_read_global_buffer_sizes(dev_hndl, - index, - count, - csr_val); - break; - case QDMA_HW_ACCESS_WRITE: - rv = - qdma_write_global_buffer_sizes(dev_hndl, - index, - count, - csr_val); - break; - default: - qdma_log_error("%s: access_type(%d) invalid, err:%d\n", - __func__, - access_type, - -QDMA_ERR_INV_PARAM); - rv = -QDMA_ERR_INV_PARAM; - break; - } - break; - default: - qdma_log_error("%s: csr_type(%d) invalid, err:%d\n", - __func__, - csr_type, - -QDMA_ERR_INV_PARAM); - rv = -QDMA_ERR_INV_PARAM; - break; - } - - return rv; -} - -/*****************************************************************************/ -/** - * qdma_global_writeback_interval_write() - function to set the writeback - * interval - * - * @dev_hndl device handle - * @wb_int: Writeback Interval - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -static int qdma_global_writeback_interval_write(void *dev_hndl, - enum qdma_wrb_interval wb_int) -{ - uint32_t reg_val; - struct qdma_dev_attributes dev_cap; - - if (!dev_hndl) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", __func__, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - if (wb_int >= QDMA_NUM_WRB_INTERVALS) { - qdma_log_error("%s: wb_int=%d is invalid, err:%d\n", - __func__, wb_int, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - qdma_get_device_attributes(dev_hndl, &dev_cap); - - if (dev_cap.st_en || dev_cap.mm_cmpt_en) { - reg_val = qdma_reg_read(dev_hndl, QDMA_OFFSET_GLBL_DSC_CFG); - reg_val |= FIELD_SET(QDMA_GLBL_DSC_CFG_WB_ACC_INT_MASK, wb_int); - - qdma_reg_write(dev_hndl, QDMA_OFFSET_GLBL_DSC_CFG, reg_val); - } else { - qdma_log_error("%s: ST or MM cmpt not supported, err:%d\n", - __func__, -QDMA_ERR_HWACC_FEATURE_NOT_SUPPORTED); - return -QDMA_ERR_HWACC_FEATURE_NOT_SUPPORTED; - } - - return QDMA_SUCCESS; -} - -/*****************************************************************************/ -/** - * qdma_global_writeback_interval_read() - function to get the writeback - * interval - * - * @dev_hndl: device handle - * @wb_int: pointer to the data to hold Writeback Interval - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -static int qdma_global_writeback_interval_read(void *dev_hndl, - enum qdma_wrb_interval *wb_int) -{ - uint32_t reg_val; - struct qdma_dev_attributes dev_cap; - - if (!dev_hndl) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", __func__, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - if (!wb_int) { - qdma_log_error("%s: wb_int is NULL, err:%d\n", __func__, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - qdma_get_device_attributes(dev_hndl, &dev_cap); - - if (dev_cap.st_en || dev_cap.mm_cmpt_en) { - reg_val = qdma_reg_read(dev_hndl, QDMA_OFFSET_GLBL_DSC_CFG); - *wb_int = (enum qdma_wrb_interval)FIELD_GET( - QDMA_GLBL_DSC_CFG_WB_ACC_INT_MASK, reg_val); - } else { - qdma_log_error("%s: ST or MM cmpt not supported, err:%d\n", - __func__, -QDMA_ERR_HWACC_FEATURE_NOT_SUPPORTED); - return -QDMA_ERR_HWACC_FEATURE_NOT_SUPPORTED; - } - - return QDMA_SUCCESS; -} - -/*****************************************************************************/ -/** - * qdma_global_writeback_interval_conf() - function to configure - * the writeback interval - * - * @dev_hndl: device handle - * @wb_int: pointer to the data to hold Writeback Interval - * @access_type HW access type (qdma_hw_access_type enum) value - * QDMA_HW_ACCESS_CLEAR - Not supported - * QDMA_HW_ACCESS_INVALIDATE - Not supported - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -int qdma_global_writeback_interval_conf(void *dev_hndl, - enum qdma_wrb_interval *wb_int, - enum qdma_hw_access_type access_type) -{ - int rv = QDMA_SUCCESS; - - switch (access_type) { - case QDMA_HW_ACCESS_READ: - rv = qdma_global_writeback_interval_read(dev_hndl, wb_int); - break; - case QDMA_HW_ACCESS_WRITE: - rv = qdma_global_writeback_interval_write(dev_hndl, *wb_int); - break; - case QDMA_HW_ACCESS_CLEAR: - case QDMA_HW_ACCESS_INVALIDATE: - default: - qdma_log_error("%s: access_type(%d) invalid, err:%d\n", - __func__, - access_type, - -QDMA_ERR_INV_PARAM); - rv = -QDMA_ERR_INV_PARAM; - break; - } - - return rv; -} - - -/*****************************************************************************/ -/** - * qdma_mm_channel_conf() - Function to enable/disable the MM channel - * - * @dev_hndl: device handle - * @channel: MM channel number - * @is_c2h: Queue direction. Set 1 for C2H and 0 for H2C - * @enable: Enable or disable MM channel - * - * Presently, we have only 1 MM channel - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -int qdma_mm_channel_conf(void *dev_hndl, uint8_t channel, uint8_t is_c2h, - uint8_t enable) -{ - uint32_t reg_addr = (is_c2h) ? QDMA_OFFSET_C2H_MM_CONTROL : - QDMA_OFFSET_H2C_MM_CONTROL; - struct qdma_dev_attributes dev_cap; - - if (!dev_hndl) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - qdma_get_device_attributes(dev_hndl, &dev_cap); - - if (dev_cap.mm_en) { - qdma_reg_write(dev_hndl, - reg_addr + (channel * QDMA_MM_CONTROL_STEP), - enable); - } - - return QDMA_SUCCESS; -} - - -int qdma_dump_reg_info(void *dev_hndl, uint32_t reg_addr, - uint32_t num_regs, char *buf, uint32_t buflen) -{ - uint32_t total_num_regs = qdma_get_config_num_regs(); - struct xreg_info *config_regs = qdma_get_config_regs(); - const char *bitfield_name; - uint32_t i = 0, num_regs_idx = 0, k = 0, j = 0, - bitfield = 0, lsb = 0, msb = 31; - int rv = 0; - uint32_t reg_val; - uint32_t data_len = 0; - - if (!dev_hndl) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - for (i = 0; i < total_num_regs; i++) { - if (reg_addr == config_regs[i].addr) { - j = i; - break; - } - } - - if (i == total_num_regs) { - qdma_log_error("%s: Register not found err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - if (buf) - QDMA_SNPRINTF_S(buf, buflen, - DEBGFS_LINE_SZ, - "Register not found 0x%x\n", reg_addr); - return -QDMA_ERR_INV_PARAM; - } - - num_regs_idx = (j + num_regs < total_num_regs) ? - (j + num_regs) : total_num_regs; - - for (; j < num_regs_idx ; j++) { - reg_val = qdma_reg_read(dev_hndl, - config_regs[j].addr); - - if (buf) { - rv = QDMA_SNPRINTF_S(buf, buflen, - DEBGFS_LINE_SZ, - "\n%-40s 0x%-7x %-#10x %-10d\n", - config_regs[j].name, - config_regs[j].addr, - reg_val, reg_val); - if ((rv < 0) || (rv > DEBGFS_LINE_SZ)) { - qdma_log_error( - "%s: Insufficient buffer, err:%d\n", - __func__, -QDMA_ERR_NO_MEM); - return -QDMA_ERR_NO_MEM; - } - buf += rv; - data_len += rv; - buflen -= rv; - } else - qdma_log_info("%-40s 0x%-7x %-#10x %-10d\n", - config_regs[j].name, - config_regs[j].addr, - reg_val, reg_val); - - - for (k = 0; - k < config_regs[j].num_bitfields; k++) { - - bitfield = - config_regs[j].bitfields[k].field_mask; - bitfield_name = - config_regs[i].bitfields[k].field_name; - lsb = 0; - msb = 31; - - while (!(BIT(lsb) & bitfield)) - lsb++; - - while (!(BIT(msb) & bitfield)) - msb--; - - if (msb != lsb) { - if (buf) { - rv = QDMA_SNPRINTF_S(buf, buflen, - DEBGFS_LINE_SZ, - "%-40s [%2u,%2u] %#-10x\n", - bitfield_name, - msb, lsb, - (reg_val & bitfield) >> - lsb); - if ((rv < 0) || (rv > DEBGFS_LINE_SZ)) { - qdma_log_error( - "%s: Insufficient buffer, err:%d\n", - __func__, - -QDMA_ERR_NO_MEM); - return -QDMA_ERR_NO_MEM; - } - buf += rv; - data_len += rv; - buflen -= rv; - } else - qdma_log_info( - "%-40s [%2u,%2u] %#-10x\n", - bitfield_name, - msb, lsb, - (reg_val & bitfield) >> lsb); - - - } else { - if (buf) { - rv = QDMA_SNPRINTF_S(buf, buflen, - DEBGFS_LINE_SZ, - "%-40s [%5u] %#-10x\n", - bitfield_name, - lsb, - (reg_val & bitfield) >> - lsb); - if ((rv < 0) || (rv > DEBGFS_LINE_SZ)) { - qdma_log_error( - "%s: Insufficient buffer, err:%d\n", - __func__, - -QDMA_ERR_NO_MEM); - return -QDMA_ERR_NO_MEM; - } - buf += rv; - data_len += rv; - buflen -= rv; - } else - qdma_log_info( - "%-40s [%5u] %#-10x\n", - bitfield_name, - lsb, - (reg_val & bitfield) >> lsb); - - } - } - } - - return data_len; - -} - diff --git a/QDMA/DPDK/drivers/net/qdma/qdma_access/qdma_soft_access/qdma_soft_access.h b/QDMA/DPDK/drivers/net/qdma/qdma_access/qdma_soft_access/qdma_soft_access.h deleted file mode 100755 index 6640987bd..000000000 --- a/QDMA/DPDK/drivers/net/qdma/qdma_access/qdma_soft_access/qdma_soft_access.h +++ /dev/null @@ -1,310 +0,0 @@ -/* - * Copyright (c) 2019-2022, Xilinx, Inc. All rights reserved. - * Copyright (c) 2022, Advanced Micro Devices, Inc. All rights reserved. - * - * BSD LICENSE - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * * Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#ifndef __QDMA_SOFT_ACCESS_H_ -#define __QDMA_SOFT_ACCESS_H_ - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * DOC: QDMA common library interface definitions - * - * Header file *qdma_access.h* defines data structures and function signatures - * exported by QDMA common library. - */ - -#include "qdma_platform.h" - -/** - * enum qdma_error_idx - qdma errors - */ -enum qdma_error_idx { - /* Descriptor errors */ - QDMA_DSC_ERR_POISON, - QDMA_DSC_ERR_UR_CA, - QDMA_DSC_ERR_PARAM, - QDMA_DSC_ERR_ADDR, - QDMA_DSC_ERR_TAG, - QDMA_DSC_ERR_FLR, - QDMA_DSC_ERR_TIMEOUT, - QDMA_DSC_ERR_DAT_POISON, - QDMA_DSC_ERR_FLR_CANCEL, - QDMA_DSC_ERR_DMA, - QDMA_DSC_ERR_DSC, - QDMA_DSC_ERR_RQ_CANCEL, - QDMA_DSC_ERR_DBE, - QDMA_DSC_ERR_SBE, - QDMA_DSC_ERR_ALL, - - /* TRQ Errors */ - QDMA_TRQ_ERR_UNMAPPED, - QDMA_TRQ_ERR_QID_RANGE, - QDMA_TRQ_ERR_VF_ACCESS, - QDMA_TRQ_ERR_TCP_TIMEOUT, - QDMA_TRQ_ERR_ALL, - - /* C2H Errors */ - QDMA_ST_C2H_ERR_MTY_MISMATCH, - QDMA_ST_C2H_ERR_LEN_MISMATCH, - QDMA_ST_C2H_ERR_QID_MISMATCH, - QDMA_ST_C2H_ERR_DESC_RSP_ERR, - QDMA_ST_C2H_ERR_ENG_WPL_DATA_PAR_ERR, - QDMA_ST_C2H_ERR_MSI_INT_FAIL, - QDMA_ST_C2H_ERR_ERR_DESC_CNT, - QDMA_ST_C2H_ERR_PORTID_CTXT_MISMATCH, - QDMA_ST_C2H_ERR_PORTID_BYP_IN_MISMATCH, - QDMA_ST_C2H_ERR_CMPT_INV_Q_ERR, - QDMA_ST_C2H_ERR_CMPT_QFULL_ERR, - QDMA_ST_C2H_ERR_CMPT_CIDX_ERR, - QDMA_ST_C2H_ERR_CMPT_PRTY_ERR, - QDMA_ST_C2H_ERR_ALL, - - /* Fatal Errors */ - QDMA_ST_FATAL_ERR_MTY_MISMATCH, - QDMA_ST_FATAL_ERR_LEN_MISMATCH, - QDMA_ST_FATAL_ERR_QID_MISMATCH, - QDMA_ST_FATAL_ERR_TIMER_FIFO_RAM_RDBE, - QDMA_ST_FATAL_ERR_PFCH_II_RAM_RDBE, - QDMA_ST_FATAL_ERR_CMPT_CTXT_RAM_RDBE, - QDMA_ST_FATAL_ERR_PFCH_CTXT_RAM_RDBE, - QDMA_ST_FATAL_ERR_DESC_REQ_FIFO_RAM_RDBE, - QDMA_ST_FATAL_ERR_INT_CTXT_RAM_RDBE, - QDMA_ST_FATAL_ERR_CMPT_COAL_DATA_RAM_RDBE, - QDMA_ST_FATAL_ERR_TUSER_FIFO_RAM_RDBE, - QDMA_ST_FATAL_ERR_QID_FIFO_RAM_RDBE, - QDMA_ST_FATAL_ERR_PAYLOAD_FIFO_RAM_RDBE, - QDMA_ST_FATAL_ERR_WPL_DATA_PAR, - QDMA_ST_FATAL_ERR_ALL, - - /* H2C Errors */ - QDMA_ST_H2C_ERR_ZERO_LEN_DESC, - QDMA_ST_H2C_ERR_CSI_MOP, - QDMA_ST_H2C_ERR_NO_DMA_DSC, - QDMA_ST_H2C_ERR_SBE, - QDMA_ST_H2C_ERR_DBE, - QDMA_ST_H2C_ERR_ALL, - - /* Single bit errors */ - QDMA_SBE_ERR_MI_H2C0_DAT, - QDMA_SBE_ERR_MI_C2H0_DAT, - QDMA_SBE_ERR_H2C_RD_BRG_DAT, - QDMA_SBE_ERR_H2C_WR_BRG_DAT, - QDMA_SBE_ERR_C2H_RD_BRG_DAT, - QDMA_SBE_ERR_C2H_WR_BRG_DAT, - QDMA_SBE_ERR_FUNC_MAP, - QDMA_SBE_ERR_DSC_HW_CTXT, - QDMA_SBE_ERR_DSC_CRD_RCV, - QDMA_SBE_ERR_DSC_SW_CTXT, - QDMA_SBE_ERR_DSC_CPLI, - QDMA_SBE_ERR_DSC_CPLD, - QDMA_SBE_ERR_PASID_CTXT_RAM, - QDMA_SBE_ERR_TIMER_FIFO_RAM, - QDMA_SBE_ERR_PAYLOAD_FIFO_RAM, - QDMA_SBE_ERR_QID_FIFO_RAM, - QDMA_SBE_ERR_TUSER_FIFO_RAM, - QDMA_SBE_ERR_WRB_COAL_DATA_RAM, - QDMA_SBE_ERR_INT_QID2VEC_RAM, - QDMA_SBE_ERR_INT_CTXT_RAM, - QDMA_SBE_ERR_DESC_REQ_FIFO_RAM, - QDMA_SBE_ERR_PFCH_CTXT_RAM, - QDMA_SBE_ERR_WRB_CTXT_RAM, - QDMA_SBE_ERR_PFCH_LL_RAM, - QDMA_SBE_ERR_H2C_PEND_FIFO, - QDMA_SBE_ERR_ALL, - - /* Double bit Errors */ - QDMA_DBE_ERR_MI_H2C0_DAT, - QDMA_DBE_ERR_MI_C2H0_DAT, - QDMA_DBE_ERR_H2C_RD_BRG_DAT, - QDMA_DBE_ERR_H2C_WR_BRG_DAT, - QDMA_DBE_ERR_C2H_RD_BRG_DAT, - QDMA_DBE_ERR_C2H_WR_BRG_DAT, - QDMA_DBE_ERR_FUNC_MAP, - QDMA_DBE_ERR_DSC_HW_CTXT, - QDMA_DBE_ERR_DSC_CRD_RCV, - QDMA_DBE_ERR_DSC_SW_CTXT, - QDMA_DBE_ERR_DSC_CPLI, - QDMA_DBE_ERR_DSC_CPLD, - QDMA_DBE_ERR_PASID_CTXT_RAM, - QDMA_DBE_ERR_TIMER_FIFO_RAM, - QDMA_DBE_ERR_PAYLOAD_FIFO_RAM, - QDMA_DBE_ERR_QID_FIFO_RAM, - QDMA_DBE_ERR_TUSER_FIFO_RAM, - QDMA_DBE_ERR_WRB_COAL_DATA_RAM, - QDMA_DBE_ERR_INT_QID2VEC_RAM, - QDMA_DBE_ERR_INT_CTXT_RAM, - QDMA_DBE_ERR_DESC_REQ_FIFO_RAM, - QDMA_DBE_ERR_PFCH_CTXT_RAM, - QDMA_DBE_ERR_WRB_CTXT_RAM, - QDMA_DBE_ERR_PFCH_LL_RAM, - QDMA_DBE_ERR_H2C_PEND_FIFO, - QDMA_DBE_ERR_ALL, - - QDMA_ERRS_ALL -}; - -struct qdma_hw_err_info { - enum qdma_error_idx idx; - const char *err_name; - uint32_t mask_reg_addr; - uint32_t stat_reg_addr; - uint32_t leaf_err_mask; - uint32_t global_err_mask; - void (*qdma_hw_err_process)(void *dev_hndl); -}; - - -int qdma_set_default_global_csr(void *dev_hndl); - -int qdma_get_version(void *dev_hndl, uint8_t is_vf, - struct qdma_hw_version_info *version_info); - -int qdma_pfetch_ctx_conf(void *dev_hndl, uint16_t hw_qid, - struct qdma_descq_prefetch_ctxt *ctxt, - enum qdma_hw_access_type access_type); - -int qdma_sw_ctx_conf(void *dev_hndl, uint8_t c2h, uint16_t hw_qid, - struct qdma_descq_sw_ctxt *ctxt, - enum qdma_hw_access_type access_type); - -int qdma_fmap_conf(void *dev_hndl, uint16_t func_id, - struct qdma_fmap_cfg *config, - enum qdma_hw_access_type access_type); - -int qdma_cmpt_ctx_conf(void *dev_hndl, uint16_t hw_qid, - struct qdma_descq_cmpt_ctxt *ctxt, - enum qdma_hw_access_type access_type); - -int qdma_hw_ctx_conf(void *dev_hndl, uint8_t c2h, uint16_t hw_qid, - struct qdma_descq_hw_ctxt *ctxt, - enum qdma_hw_access_type access_type); - -int qdma_credit_ctx_conf(void *dev_hndl, uint8_t c2h, uint16_t hw_qid, - struct qdma_descq_credit_ctxt *ctxt, - enum qdma_hw_access_type access_type); - -int qdma_indirect_intr_ctx_conf(void *dev_hndl, uint16_t ring_index, - struct qdma_indirect_intr_ctxt *ctxt, - enum qdma_hw_access_type access_type); - -int qdma_queue_pidx_update(void *dev_hndl, uint8_t is_vf, uint16_t qid, - uint8_t is_c2h, const struct qdma_q_pidx_reg_info *reg_info); - -int qdma_queue_cmpt_cidx_update(void *dev_hndl, uint8_t is_vf, - uint16_t qid, const struct qdma_q_cmpt_cidx_reg_info *reg_info); - -int qdma_queue_intr_cidx_update(void *dev_hndl, uint8_t is_vf, - uint16_t qid, const struct qdma_intr_cidx_reg_info *reg_info); - -int qdma_init_ctxt_memory(void *dev_hndl); - -int qdma_legacy_intr_conf(void *dev_hndl, enum status_type enable); - -int qdma_clear_pend_legacy_intr(void *dev_hndl); - -int qdma_is_legacy_intr_pend(void *dev_hndl); - -int qdma_dump_intr_context(void *dev_hndl, - struct qdma_indirect_intr_ctxt *intr_ctx, - int ring_index, - char *buf, uint32_t buflen); - -uint32_t qdma_soft_reg_dump_buf_len(void); - -uint32_t qdma_get_config_num_regs(void); - -struct xreg_info *qdma_get_config_regs(void); - -int qdma_soft_context_buf_len(uint8_t st, - enum qdma_dev_q_type q_type, uint32_t *buflen); - -int qdma_soft_dump_config_regs(void *dev_hndl, uint8_t is_vf, - char *buf, uint32_t buflen); - -int qdma_soft_dump_queue_context(void *dev_hndl, - uint8_t st, - enum qdma_dev_q_type q_type, - struct qdma_descq_context *ctxt_data, - char *buf, uint32_t buflen); - -int qdma_soft_read_dump_queue_context(void *dev_hndl, - uint16_t func_id, - uint16_t qid_hw, - uint8_t st, - enum qdma_dev_q_type q_type, - char *buf, uint32_t buflen); - -int qdma_hw_error_process(void *dev_hndl); - -const char *qdma_hw_get_error_name(uint32_t err_idx); - -int qdma_hw_error_enable(void *dev_hndl, uint32_t err_idx); - -int qdma_get_device_attributes(void *dev_hndl, - struct qdma_dev_attributes *dev_info); - -int qdma_get_user_bar(void *dev_hndl, uint8_t is_vf, - uint16_t func_id, uint8_t *user_bar); - -int qdma_soft_dump_config_reg_list(void *dev_hndl, - uint32_t total_regs, - struct qdma_reg_data *reg_list, - char *buf, uint32_t buflen); - -int qdma_read_reg_list(void *dev_hndl, uint8_t is_vf, - uint16_t reg_rd_group, - uint16_t *total_regs, - struct qdma_reg_data *reg_list); - -int qdma_global_csr_conf(void *dev_hndl, uint8_t index, uint8_t count, - uint32_t *csr_val, - enum qdma_global_csr_type csr_type, - enum qdma_hw_access_type access_type); - -int qdma_global_writeback_interval_conf(void *dev_hndl, - enum qdma_wrb_interval *wb_int, - enum qdma_hw_access_type access_type); - -int qdma_mm_channel_conf(void *dev_hndl, uint8_t channel, uint8_t is_c2h, - uint8_t enable); - -int qdma_dump_reg_info(void *dev_hndl, uint32_t reg_addr, - uint32_t num_regs, char *buf, uint32_t buflen); - -#ifdef __cplusplus -} -#endif - -#endif /* __QDMA_SOFT_ACCESS_H_ */ diff --git a/QDMA/DPDK/drivers/net/qdma/qdma_access/qdma_soft_access/qdma_soft_reg.h b/QDMA/DPDK/drivers/net/qdma/qdma_access/qdma_soft_access/qdma_soft_reg.h deleted file mode 100755 index 53671a6b9..000000000 --- a/QDMA/DPDK/drivers/net/qdma/qdma_access/qdma_soft_access/qdma_soft_reg.h +++ /dev/null @@ -1,599 +0,0 @@ -/* - * Copyright (c) 2019-2022, Xilinx, Inc. All rights reserved. - * Copyright (c) 2022, Advanced Micro Devices, Inc. All rights reserved. - * - * BSD LICENSE - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * * Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#ifndef __QDMA_SOFT_REG_H__ -#define __QDMA_SOFT_REG_H__ - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * User defined helper macros for masks and shifts. If the same macros are - * defined in linux kernel code , then undefined them and used the user - * defined macros - */ -#ifdef CHAR_BIT -#undef CHAR_BIT -#endif -#define CHAR_BIT 8 - -#ifdef BIT -#undef BIT -#endif -#define BIT(n) (1u << (n)) - -#ifdef BITS_PER_BYTE -#undef BITS_PER_BYTE -#endif -#define BITS_PER_BYTE CHAR_BIT - -#ifdef BITS_PER_LONG -#undef BITS_PER_LONG -#endif -#define BITS_PER_LONG (sizeof(uint32_t) * BITS_PER_BYTE) - -#ifdef BITS_PER_LONG_LONG -#undef BITS_PER_LONG_LONG -#endif -#define BITS_PER_LONG_LONG (sizeof(uint64_t) * BITS_PER_BYTE) - -#ifdef GENMASK -#undef GENMASK -#endif -#define GENMASK(h, l) \ - ((0xFFFFFFFF << (l)) & (0xFFFFFFFF >> (BITS_PER_LONG - 1 - (h)))) - -#ifdef GENMASK_ULL -#undef GENMASK_ULL -#endif -#define GENMASK_ULL(h, l) \ - ((0xFFFFFFFFFFFFFFFF << (l)) & \ - (0xFFFFFFFFFFFFFFFF >> (BITS_PER_LONG_LONG - 1 - (h)))) - - -#define DEBGFS_LINE_SZ (81) - - -#define QDMA_H2C_THROT_DATA_THRESH 0x4000 -#define QDMA_THROT_EN_DATA 1 -#define QDMA_THROT_EN_REQ 0 -#define QDMA_H2C_THROT_REQ_THRESH 0x60 - -/* - * Q Context programming (indirect) - */ - -#define QDMA_REG_IND_CTXT_REG_COUNT 8 -#define QDMA_REG_IND_CTXT_WCNT_1 1 -#define QDMA_REG_IND_CTXT_WCNT_2 2 -#define QDMA_REG_IND_CTXT_WCNT_3 3 -#define QDMA_REG_IND_CTXT_WCNT_4 4 -#define QDMA_REG_IND_CTXT_WCNT_5 5 -#define QDMA_REG_IND_CTXT_WCNT_6 6 -#define QDMA_REG_IND_CTXT_WCNT_7 7 -#define QDMA_REG_IND_CTXT_WCNT_8 8 - -/* ------------------------- QDMA_TRQ_SEL_IND (0x00800) ----------------*/ -#define QDMA_OFFSET_IND_CTXT_DATA 0x804 -#define QDMA_OFFSET_IND_CTXT_MASK 0x824 -#define QDMA_OFFSET_IND_CTXT_CMD 0x844 -#define QDMA_IND_CTXT_CMD_BUSY_MASK 0x1 - -/** QDMA_IND_REG_SEL_FMAP */ -#define QDMA_FMAP_CTXT_W1_QID_MAX_MASK GENMASK(11, 0) -#define QDMA_FMAP_CTXT_W0_QID_MASK GENMASK(10, 0) - -/** QDMA_IND_REG_SEL_SW_C2H */ -/** QDMA_IND_REG_SEL_SW_H2C */ -#define QDMA_SW_CTXT_W4_INTR_AGGR_MASK BIT(11) -#define QDMA_SW_CTXT_W4_VEC_MASK GENMASK(10, 0) -#define QDMA_SW_CTXT_W3_DSC_H_MASK GENMASK(31, 0) -#define QDMA_SW_CTXT_W2_DSC_L_MASK GENMASK(31, 0) -#define QDMA_SW_CTXT_W1_IS_MM_MASK BIT(31) -#define QDMA_SW_CTXT_W1_MRKR_DIS_MASK BIT(30) -#define QDMA_SW_CTXT_W1_IRQ_REQ_MASK BIT(29) -#define QDMA_SW_CTXT_W1_ERR_WB_SENT_MASK BIT(28) -#define QDMA_SW_CTXT_W1_ERR_MASK GENMASK(27, 26) -#define QDMA_SW_CTXT_W1_IRQ_NO_LAST_MASK BIT(25) -#define QDMA_SW_CTXT_W1_PORT_ID_MASK GENMASK(24, 22) -#define QDMA_SW_CTXT_W1_IRQ_EN_MASK BIT(21) -#define QDMA_SW_CTXT_W1_WBK_EN_MASK BIT(20) -#define QDMA_SW_CTXT_W1_MM_CHN_MASK BIT(19) -#define QDMA_SW_CTXT_W1_BYP_MASK BIT(18) -#define QDMA_SW_CTXT_W1_DSC_SZ_MASK GENMASK(17, 16) -#define QDMA_SW_CTXT_W1_RNG_SZ_MASK GENMASK(15, 12) -#define QDMA_SW_CTXT_W1_FETCH_MAX_MASK GENMASK(7, 5) -#define QDMA_SW_CTXT_W1_AT_MASK BIT(4) -#define QDMA_SW_CTXT_W1_WB_INT_EN_MASK BIT(3) -#define QDMA_SW_CTXT_W1_WBI_CHK_MASK BIT(2) -#define QDMA_SW_CTXT_W1_FCRD_EN_MASK BIT(1) -#define QDMA_SW_CTXT_W1_QEN_MASK BIT(0) -#define QDMA_SW_CTXT_W0_FUNC_ID_MASK GENMASK(24, 17) -#define QDMA_SW_CTXT_W0_IRQ_ARM_MASK BIT(16) -#define QDMA_SW_CTXT_W0_PIDX GENMASK(15, 0) - - - -#define QDMA_PFTCH_CTXT_W1_VALID_MASK BIT(13) -#define QDMA_PFTCH_CTXT_W1_SW_CRDT_H_MASK GENMASK(12, 0) -#define QDMA_PFTCH_CTXT_W0_SW_CRDT_L_MASK GENMASK(31, 29) -#define QDMA_PFTCH_CTXT_W0_Q_IN_PFETCH_MASK BIT(28) -#define QDMA_PFTCH_CTXT_W0_PFETCH_EN_MASK BIT(27) -#define QDMA_PFTCH_CTXT_W0_ERR_MASK BIT(26) -#define QDMA_PFTCH_CTXT_W0_PORT_ID_MASK GENMASK(7, 5) -#define QDMA_PFTCH_CTXT_W0_BUF_SIZE_IDX_MASK GENMASK(4, 1) -#define QDMA_PFTCH_CTXT_W0_BYPASS_MASK BIT(0) - - - - -#define QDMA_COMPL_CTXT_W4_INTR_AGGR_MASK BIT(15) -#define QDMA_COMPL_CTXT_W4_INTR_VEC_MASK GENMASK(14, 4) -#define QDMA_COMPL_CTXT_W4_AT_MASK BIT(3) -#define QDMA_COMPL_CTXT_W4_OVF_CHK_DIS_MASK BIT(2) -#define QDMA_COMPL_CTXT_W4_FULL_UPDT_MASK BIT(1) -#define QDMA_COMPL_CTXT_W4_TMR_RUN_MASK BIT(0) -#define QDMA_COMPL_CTXT_W3_USR_TRG_PND_MASK BIT(31) -#define QDMA_COMPL_CTXT_W3_ERR_MASK GENMASK(30, 29) -#define QDMA_COMPL_CTXT_W3_VALID_MASK BIT(28) -#define QDMA_COMPL_CTXT_W3_CIDX_MASK GENMASK(27, 12) -#define QDMA_COMPL_CTXT_W3_PIDX_H_MASK GENMASK(11, 0) -#define QDMA_COMPL_CTXT_W2_PIDX_L_MASK GENMASK(31, 28) -#define QDMA_COMPL_CTXT_W2_DESC_SIZE_MASK GENMASK(27, 26) -#define QDMA_COMPL_CTXT_W2_BADDR_64_H_MASK GENMASK(25, 0) -#define QDMA_COMPL_CTXT_W1_BADDR_64_L_MASK GENMASK(31, 6) -#define QDMA_COMPL_CTXT_W0_RING_SZ_MASK GENMASK(31, 28) -#define QDMA_COMPL_CTXT_W0_COLOR_MASK BIT(27) -#define QDMA_COMPL_CTXT_W0_INT_ST_MASK GENMASK(26, 25) -#define QDMA_COMPL_CTXT_W0_TIMER_IDX_MASK GENMASK(24, 21) -#define QDMA_COMPL_CTXT_W0_COUNTER_IDX_MASK GENMASK(20, 17) -#define QDMA_COMPL_CTXT_W0_FNC_ID_MASK GENMASK(12, 5) -#define QDMA_COMPL_CTXT_W0_TRIG_MODE_MASK GENMASK(4, 2) -#define QDMA_COMPL_CTXT_W0_EN_INT_MASK BIT(1) -#define QDMA_COMPL_CTXT_W0_EN_STAT_DESC_MASK BIT(0) - -/** QDMA_IND_REG_SEL_HW_C2H */ -/** QDMA_IND_REG_SEL_HW_H2C */ -#define QDMA_HW_CTXT_W1_FETCH_PEND_MASK GENMASK(14, 11) -#define QDMA_HW_CTXT_W1_EVENT_PEND_MASK BIT(10) -#define QDMA_HW_CTXT_W1_IDL_STP_B_MASK BIT(9) -#define QDMA_HW_CTXT_W1_DSC_PND_MASK BIT(8) -#define QDMA_HW_CTXT_W0_CRD_USE_MASK GENMASK(31, 16) -#define QDMA_HW_CTXT_W0_CIDX_MASK GENMASK(15, 0) - -/** QDMA_IND_REG_SEL_CR_C2H */ -/** QDMA_IND_REG_SEL_CR_H2C */ -#define QDMA_CR_CTXT_W0_CREDT_MASK GENMASK(15, 0) - -/** QDMA_IND_REG_SEL_INTR */ - - -#define QDMA_INTR_CTXT_W2_AT_MASK BIT(18) -#define QDMA_INTR_CTXT_W2_PIDX_MASK GENMASK(17, 6) -#define QDMA_INTR_CTXT_W2_PAGE_SIZE_MASK GENMASK(5, 3) -#define QDMA_INTR_CTXT_W2_BADDR_64_MASK GENMASK(2, 0) -#define QDMA_INTR_CTXT_W1_BADDR_64_MASK GENMASK(31, 0) -#define QDMA_INTR_CTXT_W0_BADDR_64_MASK GENMASK(31, 15) -#define QDMA_INTR_CTXT_W0_COLOR_MASK BIT(14) -#define QDMA_INTR_CTXT_W0_INT_ST_MASK BIT(13) -#define QDMA_INTR_CTXT_W0_VEC_ID_MASK GENMASK(11, 1) -#define QDMA_INTR_CTXT_W0_VALID_MASK BIT(0) - - - - - -/* ------------------------ QDMA_TRQ_SEL_GLBL (0x00200)-------------------*/ -#define QDMA_OFFSET_GLBL_RNG_SZ 0x204 -#define QDMA_OFFSET_GLBL_SCRATCH 0x244 -#define QDMA_OFFSET_GLBL_ERR_STAT 0x248 -#define QDMA_OFFSET_GLBL_ERR_MASK 0x24C -#define QDMA_OFFSET_GLBL_DSC_CFG 0x250 -#define QDMA_GLBL_DSC_CFG_WB_ACC_INT_MASK GENMASK(2, 0) -#define QDMA_GLBL_DSC_CFG_MAX_DSC_FETCH_MASK GENMASK(5, 3) -#define QDMA_OFFSET_GLBL_DSC_ERR_STS 0x254 -#define QDMA_OFFSET_GLBL_DSC_ERR_MSK 0x258 -#define QDMA_OFFSET_GLBL_DSC_ERR_LOG0 0x25C -#define QDMA_OFFSET_GLBL_DSC_ERR_LOG1 0x260 -#define QDMA_OFFSET_GLBL_TRQ_ERR_STS 0x264 -#define QDMA_OFFSET_GLBL_TRQ_ERR_MSK 0x268 -#define QDMA_OFFSET_GLBL_TRQ_ERR_LOG 0x26C -#define QDMA_OFFSET_GLBL_DSC_DBG_DAT0 0x270 -#define QDMA_OFFSET_GLBL_DSC_DBG_DAT1 0x274 -#define QDMA_OFFSET_GLBL_DSC_ERR_LOG2 0x27C -#define QDMA_OFFSET_GLBL_INTERRUPT_CFG 0x2C4 -#define QDMA_GLBL_INTR_CFG_EN_LGCY_INTR_MASK BIT(0) -#define QDMA_GLBL_INTR_LGCY_INTR_PEND_MASK BIT(1) - -/* ------------------------- QDMA_TRQ_SEL_C2H (0x00A00) ------------------*/ -#define QDMA_OFFSET_C2H_TIMER_CNT 0xA00 -#define QDMA_OFFSET_C2H_CNT_TH 0xA40 -#define QDMA_OFFSET_C2H_QID2VEC_MAP_QID 0xA80 -#define QDMA_OFFSET_C2H_QID2VEC_MAP 0xA84 -#define QDMA_OFFSET_C2H_STAT_S_AXIS_C2H_ACCEPTED 0xA88 -#define QDMA_OFFSET_C2H_STAT_S_AXIS_CMPT_ACCEPTED 0xA8C -#define QDMA_OFFSET_C2H_STAT_DESC_RSP_PKT_ACCEPTED 0xA90 -#define QDMA_OFFSET_C2H_STAT_AXIS_PKG_CMP 0xA94 -#define QDMA_OFFSET_C2H_STAT_DESC_RSP_ACCEPTED 0xA98 -#define QDMA_OFFSET_C2H_STAT_DESC_RSP_CMP 0xA9C -#define QDMA_OFFSET_C2H_STAT_WRQ_OUT 0xAA0 -#define QDMA_OFFSET_C2H_STAT_WPL_REN_ACCEPTED 0xAA4 -#define QDMA_OFFSET_C2H_STAT_TOTAL_WRQ_LEN 0xAA8 -#define QDMA_OFFSET_C2H_STAT_TOTAL_WPL_LEN 0xAAC -#define QDMA_OFFSET_C2H_BUF_SZ 0xAB0 -#define QDMA_OFFSET_C2H_ERR_STAT 0xAF0 -#define QDMA_OFFSET_C2H_ERR_MASK 0xAF4 -#define QDMA_OFFSET_C2H_FATAL_ERR_STAT 0xAF8 -#define QDMA_OFFSET_C2H_FATAL_ERR_MASK 0xAFC -#define QDMA_OFFSET_C2H_FATAL_ERR_ENABLE 0xB00 -#define QDMA_OFFSET_C2H_ERR_INT 0xB04 -#define QDMA_OFFSET_C2H_PFETCH_CFG 0xB08 -#define QDMA_C2H_EVT_QCNT_TH_MASK GENMASK(31, 25) -#define QDMA_C2H_PFCH_QCNT_MASK GENMASK(24, 18) -#define QDMA_C2H_NUM_PFCH_MASK GENMASK(17, 9) -#define QDMA_C2H_PFCH_FL_TH_MASK GENMASK(8, 0) -#define QDMA_OFFSET_C2H_INT_TIMER_TICK 0xB0C -#define QDMA_OFFSET_C2H_STAT_DESC_RSP_DROP_ACCEPTED 0xB10 -#define QDMA_OFFSET_C2H_STAT_DESC_RSP_ERR_ACCEPTED 0xB14 -#define QDMA_OFFSET_C2H_STAT_DESC_REQ 0xB18 -#define QDMA_OFFSET_C2H_STAT_DEBUG_DMA_ENG_0 0xB1C -#define QDMA_OFFSET_C2H_STAT_DEBUG_DMA_ENG_1 0xB20 -#define QDMA_OFFSET_C2H_STAT_DEBUG_DMA_ENG_2 0xB24 -#define QDMA_OFFSET_C2H_STAT_DEBUG_DMA_ENG_3 0xB28 -#define QDMA_OFFSET_C2H_DBG_PFCH_ERR_CTXT 0xB2C -#define QDMA_OFFSET_C2H_FIRST_ERR_QID 0xB30 -#define QDMA_OFFSET_C2H_STAT_NUM_CMPT_IN 0xB34 -#define QDMA_OFFSET_C2H_STAT_NUM_CMPT_OUT 0xB38 -#define QDMA_OFFSET_C2H_STAT_NUM_CMPT_DRP 0xB3C -#define QDMA_OFFSET_C2H_STAT_NUM_STAT_DESC_OUT 0xB40 -#define QDMA_OFFSET_C2H_STAT_NUM_DSC_CRDT_SENT 0xB44 -#define QDMA_OFFSET_C2H_STAT_NUM_FCH_DSC_RCVD 0xB48 -#define QDMA_OFFSET_C2H_STAT_NUM_BYP_DSC_RCVD 0xB4C -#define QDMA_OFFSET_C2H_WRB_COAL_CFG 0xB50 -#define QDMA_C2H_MAX_BUF_SZ_MASK GENMASK(31, 26) -#define QDMA_C2H_TICK_VAL_MASK GENMASK(25, 14) -#define QDMA_C2H_TICK_CNT_MASK GENMASK(13, 2) -#define QDMA_C2H_SET_GLB_FLUSH_MASK BIT(1) -#define QDMA_C2H_DONE_GLB_FLUSH_MASK BIT(0) -#define QDMA_OFFSET_C2H_INTR_H2C_REQ 0xB54 -#define QDMA_OFFSET_C2H_INTR_C2H_MM_REQ 0xB58 -#define QDMA_OFFSET_C2H_INTR_ERR_INT_REQ 0xB5C -#define QDMA_OFFSET_C2H_INTR_C2H_ST_REQ 0xB60 -#define QDMA_OFFSET_C2H_INTR_H2C_ERR_C2H_MM_MSIX_ACK 0xB64 -#define QDMA_OFFSET_C2H_INTR_H2C_ERR_C2H_MM_MSIX_FAIL 0xB68 -#define QDMA_OFFSET_C2H_INTR_H2C_ERR_C2H_MM_MSIX_NO_MSIX 0xB6C -#define QDMA_OFFSET_C2H_INTR_H2C_ERR_C2H_MM_CTXT_INVAL 0xB70 -#define QDMA_OFFSET_C2H_INTR_C2H_ST_MSIX_ACK 0xB74 -#define QDMA_OFFSET_C2H_INTR_C2H_ST_MSIX_FAIL 0xB78 -#define QDMA_OFFSET_C2H_INTR_C2H_ST_NO_MSIX 0xB7C -#define QDMA_OFFSET_C2H_INTR_C2H_ST_CTXT_INVAL 0xB80 -#define QDMA_OFFSET_C2H_STAT_WR_CMP 0xB84 -#define QDMA_OFFSET_C2H_STAT_DEBUG_DMA_ENG_4 0xB88 -#define QDMA_OFFSET_C2H_STAT_DEBUG_DMA_ENG_5 0xB8C -#define QDMA_OFFSET_C2H_DBG_PFCH_QID 0xB90 -#define QDMA_OFFSET_C2H_DBG_PFCH 0xB94 -#define QDMA_OFFSET_C2H_INT_DEBUG 0xB98 -#define QDMA_OFFSET_C2H_STAT_IMM_ACCEPTED 0xB9C -#define QDMA_OFFSET_C2H_STAT_MARKER_ACCEPTED 0xBA0 -#define QDMA_OFFSET_C2H_STAT_DISABLE_CMP_ACCEPTED 0xBA4 -#define QDMA_OFFSET_C2H_PAYLOAD_FIFO_CRDT_CNT 0xBA8 -#define QDMA_OFFSET_C2H_PFETCH_CACHE_DEPTH 0xBE0 -#define QDMA_OFFSET_C2H_CMPT_COAL_BUF_DEPTH 0xBE4 - -/* ------------------------- QDMA_TRQ_SEL_H2C (0x00E00) ------------------*/ -#define QDMA_OFFSET_H2C_ERR_STAT 0xE00 -#define QDMA_OFFSET_H2C_ERR_MASK 0xE04 -#define QDMA_OFFSET_H2C_FIRST_ERR_QID 0xE08 -#define QDMA_OFFSET_H2C_DBG_REG0 0xE0C -#define QDMA_OFFSET_H2C_DBG_REG1 0xE10 -#define QDMA_OFFSET_H2C_DBG_REG2 0xE14 -#define QDMA_OFFSET_H2C_DBG_REG3 0xE18 -#define QDMA_OFFSET_H2C_DBG_REG4 0xE1C -#define QDMA_OFFSET_H2C_FATAL_ERR_EN 0xE20 -#define QDMA_OFFSET_H2C_REQ_THROT 0xE24 -#define QDMA_H2C_REQ_THROT_EN_REQ_MASK BIT(31) -#define QDMA_H2C_REQ_THRESH_MASK GENMASK(25, 17) -#define QDMA_H2C_REQ_THROT_EN_DATA_MASK BIT(16) -#define QDMA_H2C_DATA_THRESH_MASK GENMASK(15, 0) - - -/* ------------------------- QDMA_TRQ_SEL_H2C_MM (0x1200) ----------------*/ -#define QDMA_OFFSET_H2C_MM_CONTROL 0x1204 -#define QDMA_OFFSET_H2C_MM_CONTROL_W1S 0x1208 -#define QDMA_OFFSET_H2C_MM_CONTROL_W1C 0x120C -#define QDMA_OFFSET_H2C_MM_STATUS 0x1240 -#define QDMA_OFFSET_H2C_MM_STATUS_RC 0x1244 -#define QDMA_OFFSET_H2C_MM_COMPLETED_DESC_COUNT 0x1248 -#define QDMA_OFFSET_H2C_MM_ERR_CODE_EN_MASK 0x1254 -#define QDMA_OFFSET_H2C_MM_ERR_CODE 0x1258 -#define QDMA_OFFSET_H2C_MM_ERR_INFO 0x125C -#define QDMA_OFFSET_H2C_MM_PERF_MON_CONTROL 0x12C0 -#define QDMA_OFFSET_H2C_MM_PERF_MON_CYCLE_COUNT_0 0x12C4 -#define QDMA_OFFSET_H2C_MM_PERF_MON_CYCLE_COUNT_1 0x12C8 -#define QDMA_OFFSET_H2C_MM_PERF_MON_DATA_COUNT_0 0x12CC -#define QDMA_OFFSET_H2C_MM_PERF_MON_DATA_COUNT_1 0x12D0 -#define QDMA_OFFSET_H2C_MM_DEBUG 0x12E8 - -/* ------------------------- QDMA_TRQ_SEL_C2H_MM (0x1000) ----------------*/ -#define QDMA_OFFSET_C2H_MM_CONTROL 0x1004 -#define QDMA_OFFSET_C2H_MM_CONTROL_W1S 0x1008 -#define QDMA_OFFSET_C2H_MM_CONTROL_W1C 0x100C -#define QDMA_OFFSET_C2H_MM_STATUS 0x1040 -#define QDMA_OFFSET_C2H_MM_STATUS_RC 0x1044 -#define QDMA_OFFSET_C2H_MM_COMPLETED_DESC_COUNT 0x1048 -#define QDMA_OFFSET_C2H_MM_ERR_CODE_EN_MASK 0x1054 -#define QDMA_OFFSET_C2H_MM_ERR_CODE 0x1058 -#define QDMA_OFFSET_C2H_MM_ERR_INFO 0x105C -#define QDMA_OFFSET_C2H_MM_PERF_MON_CONTROL 0x10C0 -#define QDMA_OFFSET_C2H_MM_PERF_MON_CYCLE_COUNT_0 0x10C4 -#define QDMA_OFFSET_C2H_MM_PERF_MON_CYCLE_COUNT_1 0x10C8 -#define QDMA_OFFSET_C2H_MM_PERF_MON_DATA_COUNT_0 0x10CC -#define QDMA_OFFSET_C2H_MM_PERF_MON_DATA_COUNT_1 0x10D0 -#define QDMA_OFFSET_C2H_MM_DEBUG 0x10E8 - -/* ------------------------- QDMA_TRQ_SEL_GLBL1 (0x0) -----------------*/ -#define QDMA_OFFSET_CONFIG_BLOCK_ID 0x0 -#define QDMA_CONFIG_BLOCK_ID_MASK GENMASK(31, 16) - - -/* ------------------------- QDMA_TRQ_SEL_GLBL2 (0x00100) ----------------*/ -#define QDMA_OFFSET_GLBL2_ID 0x100 -#define QDMA_OFFSET_GLBL2_PF_BARLITE_INT 0x104 -#define QDMA_GLBL2_PF3_BAR_MAP_MASK GENMASK(23, 18) -#define QDMA_GLBL2_PF2_BAR_MAP_MASK GENMASK(17, 12) -#define QDMA_GLBL2_PF1_BAR_MAP_MASK GENMASK(11, 6) -#define QDMA_GLBL2_PF0_BAR_MAP_MASK GENMASK(5, 0) -#define QDMA_OFFSET_GLBL2_PF_VF_BARLITE_INT 0x108 -#define QDMA_OFFSET_GLBL2_PF_BARLITE_EXT 0x10C -#define QDMA_OFFSET_GLBL2_PF_VF_BARLITE_EXT 0x110 -#define QDMA_OFFSET_GLBL2_CHANNEL_INST 0x114 -#define QDMA_OFFSET_GLBL2_CHANNEL_MDMA 0x118 -#define QDMA_GLBL2_ST_C2H_MASK BIT(17) -#define QDMA_GLBL2_ST_H2C_MASK BIT(16) -#define QDMA_GLBL2_MM_C2H_MASK BIT(8) -#define QDMA_GLBL2_MM_H2C_MASK BIT(0) -#define QDMA_OFFSET_GLBL2_CHANNEL_STRM 0x11C -#define QDMA_OFFSET_GLBL2_CHANNEL_QDMA_CAP 0x120 -#define QDMA_GLBL2_MULTQ_MAX_MASK GENMASK(11, 0) -#define QDMA_OFFSET_GLBL2_CHANNEL_PASID_CAP 0x128 -#define QDMA_OFFSET_GLBL2_CHANNEL_FUNC_RET 0x12C -#define QDMA_OFFSET_GLBL2_SYSTEM_ID 0x130 -#define QDMA_OFFSET_GLBL2_MISC_CAP 0x134 - -#define QDMA_GLBL2_DEVICE_ID_MASK GENMASK(31, 28) -#define QDMA_GLBL2_VIVADO_RELEASE_MASK GENMASK(27, 24) -#define QDMA_GLBL2_VERSAL_IP_MASK GENMASK(23, 20) -#define QDMA_GLBL2_RTL_VERSION_MASK GENMASK(19, 16) -#define QDMA_OFFSET_GLBL2_DBG_PCIE_RQ0 0x1B8 -#define QDMA_OFFSET_GLBL2_DBG_PCIE_RQ1 0x1BC -#define QDMA_OFFSET_GLBL2_DBG_AXIMM_WR0 0x1C0 -#define QDMA_OFFSET_GLBL2_DBG_AXIMM_WR1 0x1C4 -#define QDMA_OFFSET_GLBL2_DBG_AXIMM_RD0 0x1C8 -#define QDMA_OFFSET_GLBL2_DBG_AXIMM_RD1 0x1CC - -/* used for VF bars identification */ -#define QDMA_OFFSET_VF_USER_BAR_ID 0x1018 -#define QDMA_OFFSET_VF_CONFIG_BAR_ID 0x1014 - -/* FLR programming */ -#define QDMA_OFFSET_VF_REG_FLR_STATUS 0x1100 -#define QDMA_OFFSET_PF_REG_FLR_STATUS 0x2500 -#define QDMA_FLR_STATUS_MASK 0x1 - -/* VF qdma version */ -#define QDMA_OFFSET_VF_VERSION 0x1014 -#define QDMA_OFFSET_PF_VERSION 0x2414 -#define QDMA_GLBL2_VF_UNIQUE_ID_MASK GENMASK(31, 16) -#define QDMA_GLBL2_VF_DEVICE_ID_MASK GENMASK(15, 12) -#define QDMA_GLBL2_VF_VIVADO_RELEASE_MASK GENMASK(11, 8) -#define QDMA_GLBL2_VF_VERSAL_IP_MASK GENMASK(7, 4) -#define QDMA_GLBL2_VF_RTL_VERSION_MASK GENMASK(3, 0) - - -/* ------------------------- QDMA_TRQ_SEL_QUEUE_PF (0x18000) ----------------*/ - -#define QDMA_OFFSET_DMAP_SEL_INT_CIDX 0x18000 -#define QDMA_OFFSET_DMAP_SEL_H2C_DSC_PIDX 0x18004 -#define QDMA_OFFSET_DMAP_SEL_C2H_DSC_PIDX 0x18008 -#define QDMA_OFFSET_DMAP_SEL_CMPT_CIDX 0x1800C - -#define QDMA_OFFSET_VF_DMAP_SEL_INT_CIDX 0x3000 -#define QDMA_OFFSET_VF_DMAP_SEL_H2C_DSC_PIDX 0x3004 -#define QDMA_OFFSET_VF_DMAP_SEL_C2H_DSC_PIDX 0x3008 -#define QDMA_OFFSET_VF_DMAP_SEL_CMPT_CIDX 0x300C - -#define QDMA_DMA_SEL_INT_SW_CIDX_MASK GENMASK(15, 0) -#define QDMA_DMA_SEL_INT_RING_IDX_MASK GENMASK(23, 16) -#define QDMA_DMA_SEL_DESC_PIDX_MASK GENMASK(15, 0) -#define QDMA_DMA_SEL_IRQ_EN_MASK BIT(16) -#define QDMA_DMAP_SEL_CMPT_IRQ_EN_MASK BIT(28) -#define QDMA_DMAP_SEL_CMPT_STS_DESC_EN_MASK BIT(27) -#define QDMA_DMAP_SEL_CMPT_TRG_MODE_MASK GENMASK(26, 24) -#define QDMA_DMAP_SEL_CMPT_TMR_CNT_MASK GENMASK(23, 20) -#define QDMA_DMAP_SEL_CMPT_CNT_THRESH_MASK GENMASK(19, 16) -#define QDMA_DMAP_SEL_CMPT_WRB_CIDX_MASK GENMASK(15, 0) - -/* ------------------------- Hardware Errors ------------------------------ */ -#define TOTAL_LEAF_ERROR_AGGREGATORS 7 - -#define QDMA_OFFSET_GLBL_ERR_INT 0xB04 -#define QDMA_GLBL_ERR_FUNC_MASK GENMASK(7, 0) -#define QDMA_GLBL_ERR_VEC_MASK GENMASK(22, 12) -#define QDMA_GLBL_ERR_ARM_MASK BIT(24) - -#define QDMA_OFFSET_GLBL_ERR_STAT 0x248 -#define QDMA_OFFSET_GLBL_ERR_MASK 0x24C -#define QDMA_GLBL_ERR_RAM_SBE_MASK BIT(0) -#define QDMA_GLBL_ERR_RAM_DBE_MASK BIT(1) -#define QDMA_GLBL_ERR_DSC_MASK BIT(2) -#define QDMA_GLBL_ERR_TRQ_MASK BIT(3) -#define QDMA_GLBL_ERR_ST_C2H_MASK BIT(8) -#define QDMA_GLBL_ERR_ST_H2C_MASK BIT(11) - -#define QDMA_OFFSET_C2H_ERR_STAT 0xAF0 -#define QDMA_OFFSET_C2H_ERR_MASK 0xAF4 -#define QDMA_C2H_ERR_MTY_MISMATCH_MASK BIT(0) -#define QDMA_C2H_ERR_LEN_MISMATCH_MASK BIT(1) -#define QDMA_C2H_ERR_QID_MISMATCH_MASK BIT(3) -#define QDMA_C2H_ERR_DESC_RSP_ERR_MASK BIT(4) -#define QDMA_C2H_ERR_ENG_WPL_DATA_PAR_ERR_MASK BIT(6) -#define QDMA_C2H_ERR_MSI_INT_FAIL_MASK BIT(7) -#define QDMA_C2H_ERR_ERR_DESC_CNT_MASK BIT(9) -#define QDMA_C2H_ERR_PORTID_CTXT_MISMATCH_MASK BIT(10) -#define QDMA_C2H_ERR_PORTID_BYP_IN_MISMATCH_MASK BIT(11) -#define QDMA_C2H_ERR_CMPT_INV_Q_ERR_MASK BIT(12) -#define QDMA_C2H_ERR_CMPT_QFULL_ERR_MASK BIT(13) -#define QDMA_C2H_ERR_CMPT_CIDX_ERR_MASK BIT(14) -#define QDMA_C2H_ERR_CMPT_PRTY_ERR_MASK BIT(15) -#define QDMA_C2H_ERR_ALL_MASK 0xFEDB - -#define QDMA_OFFSET_C2H_FATAL_ERR_STAT 0xAF8 -#define QDMA_OFFSET_C2H_FATAL_ERR_MASK 0xAFC -#define QDMA_C2H_FATAL_ERR_MTY_MISMATCH_MASK BIT(0) -#define QDMA_C2H_FATAL_ERR_LEN_MISMATCH_MASK BIT(1) -#define QDMA_C2H_FATAL_ERR_QID_MISMATCH_MASK BIT(3) -#define QDMA_C2H_FATAL_ERR_TIMER_FIFO_RAM_RDBE_MASK BIT(4) -#define QDMA_C2H_FATAL_ERR_PFCH_II_RAM_RDBE_MASK BIT(8) -#define QDMA_C2H_FATAL_ERR_CMPT_CTXT_RAM_RDBE_MASK BIT(9) -#define QDMA_C2H_FATAL_ERR_PFCH_CTXT_RAM_RDBE_MASK BIT(10) -#define QDMA_C2H_FATAL_ERR_DESC_REQ_FIFO_RAM_RDBE_MASK BIT(11) -#define QDMA_C2H_FATAL_ERR_INT_CTXT_RAM_RDBE_MASK BIT(12) -#define QDMA_C2H_FATAL_ERR_CMPT_COAL_DATA_RAM_RDBE_MASK BIT(14) -#define QDMA_C2H_FATAL_ERR_TUSER_FIFO_RAM_RDBE_MASK BIT(15) -#define QDMA_C2H_FATAL_ERR_QID_FIFO_RAM_RDBE_MASK BIT(16) -#define QDMA_C2H_FATAL_ERR_PAYLOAD_FIFO_RAM_RDBE_MASK BIT(17) -#define QDMA_C2H_FATAL_ERR_WPL_DATA_PAR_MASK BIT(18) -#define QDMA_C2H_FATAL_ERR_ALL_MASK 0x7DF1B - -#define QDMA_OFFSET_H2C_ERR_STAT 0xE00 -#define QDMA_OFFSET_H2C_ERR_MASK 0xE04 -#define QDMA_H2C_ERR_ZERO_LEN_DESC_MASK BIT(0) -#define QDMA_H2C_ERR_CSI_MOP_MASK BIT(1) -#define QDMA_H2C_ERR_NO_DMA_DSC_MASK BIT(2) -#define QDMA_H2C_ERR_SBE_MASK BIT(3) -#define QDMA_H2C_ERR_DBE_MASK BIT(4) -#define QDMA_H2C_ERR_ALL_MASK 0x1F - -#define QDMA_OFFSET_GLBL_DSC_ERR_STAT 0x254 -#define QDMA_OFFSET_GLBL_DSC_ERR_MASK 0x258 -#define QDMA_GLBL_DSC_ERR_POISON_MASK BIT(0) -#define QDMA_GLBL_DSC_ERR_UR_CA_MASK BIT(1) -#define QDMA_GLBL_DSC_ERR_PARAM_MASK BIT(2) -#define QDMA_GLBL_DSC_ERR_ADDR_MASK BIT(3) -#define QDMA_GLBL_DSC_ERR_TAG_MASK BIT(4) -#define QDMA_GLBL_DSC_ERR_FLR_MASK BIT(5) -#define QDMA_GLBL_DSC_ERR_TIMEOUT_MASK BIT(9) -#define QDMA_GLBL_DSC_ERR_DAT_POISON_MASK BIT(16) -#define QDMA_GLBL_DSC_ERR_FLR_CANCEL_MASK BIT(19) -#define QDMA_GLBL_DSC_ERR_DMA_MASK BIT(20) -#define QDMA_GLBL_DSC_ERR_DSC_MASK BIT(21) -#define QDMA_GLBL_DSC_ERR_RQ_CANCEL_MASK BIT(22) -#define QDMA_GLBL_DSC_ERR_DBE_MASK BIT(23) -#define QDMA_GLBL_DSC_ERR_SBE_MASK BIT(24) -#define QDMA_GLBL_DSC_ERR_ALL_MASK 0x1F9023F - -#define QDMA_OFFSET_GLBL_TRQ_ERR_STAT 0x264 -#define QDMA_OFFSET_GLBL_TRQ_ERR_MASK 0x268 -#define QDMA_GLBL_TRQ_ERR_UNMAPPED_MASK BIT(0) -#define QDMA_GLBL_TRQ_ERR_QID_RANGE_MASK BIT(1) -#define QDMA_GLBL_TRQ_ERR_VF_ACCESS_MASK BIT(2) -#define QDMA_GLBL_TRQ_ERR_TCP_TIMEOUT_MASK BIT(3) -#define QDMA_GLBL_TRQ_ERR_ALL_MASK 0xF - -#define QDMA_OFFSET_RAM_SBE_STAT 0xF4 -#define QDMA_OFFSET_RAM_SBE_MASK 0xF0 -#define QDMA_SBE_ERR_MI_H2C0_DAT_MASK BIT(0) -#define QDMA_SBE_ERR_MI_C2H0_DAT_MASK BIT(4) -#define QDMA_SBE_ERR_H2C_RD_BRG_DAT_MASK BIT(9) -#define QDMA_SBE_ERR_H2C_WR_BRG_DAT_MASK BIT(10) -#define QDMA_SBE_ERR_C2H_RD_BRG_DAT_MASK BIT(11) -#define QDMA_SBE_ERR_C2H_WR_BRG_DAT_MASK BIT(12) -#define QDMA_SBE_ERR_FUNC_MAP_MASK BIT(13) -#define QDMA_SBE_ERR_DSC_HW_CTXT_MASK BIT(14) -#define QDMA_SBE_ERR_DSC_CRD_RCV_MASK BIT(15) -#define QDMA_SBE_ERR_DSC_SW_CTXT_MASK BIT(16) -#define QDMA_SBE_ERR_DSC_CPLI_MASK BIT(17) -#define QDMA_SBE_ERR_DSC_CPLD_MASK BIT(18) -#define QDMA_SBE_ERR_PASID_CTXT_RAM_MASK BIT(19) -#define QDMA_SBE_ERR_TIMER_FIFO_RAM_MASK BIT(20) -#define QDMA_SBE_ERR_PAYLOAD_FIFO_RAM_MASK BIT(21) -#define QDMA_SBE_ERR_QID_FIFO_RAM_MASK BIT(22) -#define QDMA_SBE_ERR_TUSER_FIFO_RAM_MASK BIT(23) -#define QDMA_SBE_ERR_WRB_COAL_DATA_RAM_MASK BIT(24) -#define QDMA_SBE_ERR_INT_QID2VEC_RAM_MASK BIT(25) -#define QDMA_SBE_ERR_INT_CTXT_RAM_MASK BIT(26) -#define QDMA_SBE_ERR_DESC_REQ_FIFO_RAM_MASK BIT(27) -#define QDMA_SBE_ERR_PFCH_CTXT_RAM_MASK BIT(28) -#define QDMA_SBE_ERR_WRB_CTXT_RAM_MASK BIT(29) -#define QDMA_SBE_ERR_PFCH_LL_RAM_MASK BIT(30) -#define QDMA_SBE_ERR_H2C_PEND_FIFO_MASK BIT(31) -#define QDMA_SBE_ERR_ALL_MASK 0xFFFFFF11 - -#define QDMA_OFFSET_RAM_DBE_STAT 0xFC -#define QDMA_OFFSET_RAM_DBE_MASK 0xF8 -#define QDMA_DBE_ERR_MI_H2C0_DAT_MASK BIT(0) -#define QDMA_DBE_ERR_MI_C2H0_DAT_MASK BIT(4) -#define QDMA_DBE_ERR_H2C_RD_BRG_DAT_MASK BIT(9) -#define QDMA_DBE_ERR_H2C_WR_BRG_DAT_MASK BIT(10) -#define QDMA_DBE_ERR_C2H_RD_BRG_DAT_MASK BIT(11) -#define QDMA_DBE_ERR_C2H_WR_BRG_DAT_MASK BIT(12) -#define QDMA_DBE_ERR_FUNC_MAP_MASK BIT(13) -#define QDMA_DBE_ERR_DSC_HW_CTXT_MASK BIT(14) -#define QDMA_DBE_ERR_DSC_CRD_RCV_MASK BIT(15) -#define QDMA_DBE_ERR_DSC_SW_CTXT_MASK BIT(16) -#define QDMA_DBE_ERR_DSC_CPLI_MASK BIT(17) -#define QDMA_DBE_ERR_DSC_CPLD_MASK BIT(18) -#define QDMA_DBE_ERR_PASID_CTXT_RAM_MASK BIT(19) -#define QDMA_DBE_ERR_TIMER_FIFO_RAM_MASK BIT(20) -#define QDMA_DBE_ERR_PAYLOAD_FIFO_RAM_MASK BIT(21) -#define QDMA_DBE_ERR_QID_FIFO_RAM_MASK BIT(22) -#define QDMA_DBE_ERR_TUSER_FIFO_RAM_MASK BIT(23) -#define QDMA_DBE_ERR_WRB_COAL_DATA_RAM_MASK BIT(24) -#define QDMA_DBE_ERR_INT_QID2VEC_RAM_MASK BIT(25) -#define QDMA_DBE_ERR_INT_CTXT_RAM_MASK BIT(26) -#define QDMA_DBE_ERR_DESC_REQ_FIFO_RAM_MASK BIT(27) -#define QDMA_DBE_ERR_PFCH_CTXT_RAM_MASK BIT(28) -#define QDMA_DBE_ERR_WRB_CTXT_RAM_MASK BIT(29) -#define QDMA_DBE_ERR_PFCH_LL_RAM_MASK BIT(30) -#define QDMA_DBE_ERR_H2C_PEND_FIFO_MASK BIT(31) -#define QDMA_DBE_ERR_ALL_MASK 0xFFFFFF11 - -#define QDMA_OFFSET_MBOX_BASE_VF 0x1000 -#define QDMA_OFFSET_MBOX_BASE_PF 0x2400 - -#ifdef __cplusplus -} -#endif - -#endif /* __QDMA_SOFT_REG_H__ */ diff --git a/QDMA/DPDK/drivers/net/qdma/qdma_common.c b/QDMA/DPDK/drivers/net/qdma/qdma_common.c deleted file mode 100755 index a25127edd..000000000 --- a/QDMA/DPDK/drivers/net/qdma/qdma_common.c +++ /dev/null @@ -1,657 +0,0 @@ -/*- - * BSD LICENSE - * - * Copyright (c) 2017-2022 Xilinx, Inc. All rights reserved. - * Copyright (c) 2022-2023, Advanced Micro Devices, Inc. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * * Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include -#include -#include -#include -#include -#include "qdma.h" -#include "qdma_access_common.h" -#include -#include - -/* Read register */ -uint32_t qdma_read_reg(uint64_t reg_addr) -{ - uint32_t val; - - val = *((volatile uint32_t *)(reg_addr)); - return val; -} - -/* Write register */ -void qdma_write_reg(uint64_t reg_addr, uint32_t val) -{ - *((volatile uint32_t *)(reg_addr)) = val; -} - -uint32_t qdma_pci_read_reg(struct rte_eth_dev *dev, uint32_t bar, uint32_t reg) -{ - struct qdma_pci_dev *qdma_dev = dev->data->dev_private; - uint64_t baseaddr; - uint32_t val; - - if (bar >= (QDMA_NUM_BARS - 1)) { - printf("Error: PCI BAR number:%u not supported\n" - "Please enter valid BAR number\n", bar); - return -1; - } - - baseaddr = (uint64_t)qdma_dev->bar_addr[bar]; - if (!baseaddr) { - printf("Error: PCI BAR number:%u not mapped\n", bar); - return -1; - } - -#ifdef TANDEM_BOOT_SUPPORTED - val = *((volatile uint64_t *)(baseaddr + reg)); -#else - val = *((volatile uint32_t *)(baseaddr + reg)); -#endif - - return val; -} - -void qdma_pci_write_reg(struct rte_eth_dev *dev, uint32_t bar, - uint32_t reg, uint32_t val) -{ - struct qdma_pci_dev *qdma_dev = dev->data->dev_private; - uint64_t baseaddr; - - if (bar >= (QDMA_NUM_BARS - 1)) { - printf("Error: PCI BAR index:%u not supported\n" - "Please enter valid BAR index\n", bar); - return; - } - - baseaddr = (uint64_t)qdma_dev->bar_addr[bar]; - if (!baseaddr) { - printf("Error: PCI BAR number:%u not mapped\n", bar); - return; - } - -#ifdef TANDEM_BOOT_SUPPORTED - *((volatile uint64_t *)(baseaddr + reg)) = val; -#else - *((volatile uint32_t *)(baseaddr + reg)) = val; -#endif -} - -void qdma_reset_rx_queue(struct qdma_rx_queue *rxq) -{ - uint32_t i; - uint32_t sz; - - rxq->rx_tail = 0; - rxq->q_pidx_info.pidx = 0; - - /* Zero out HW ring memory, For MM Descriptor */ - if (rxq->st_mode) { /** if ST-mode **/ - sz = rxq->cmpt_desc_len; - for (i = 0; i < (sz * rxq->nb_rx_cmpt_desc); i++) - ((volatile char *)rxq->cmpt_ring)[i] = 0; - - sz = sizeof(struct qdma_ul_st_c2h_desc); - for (i = 0; i < (sz * rxq->nb_rx_desc); i++) - ((volatile char *)rxq->rx_ring)[i] = 0; - - } else { - sz = sizeof(struct qdma_ul_mm_desc); - for (i = 0; i < (sz * rxq->nb_rx_desc); i++) - ((volatile char *)rxq->rx_ring)[i] = 0; - } - - /* Initialize SW ring entries */ - for (i = 0; i < rxq->nb_rx_desc; i++) - rxq->sw_ring[i] = NULL; -} - -void qdma_inv_rx_queue_ctxts(struct rte_eth_dev *dev, - uint32_t qid, uint32_t mode) -{ - struct qdma_pci_dev *qdma_dev = dev->data->dev_private; - struct qdma_descq_sw_ctxt q_sw_ctxt; - struct qdma_descq_prefetch_ctxt q_prefetch_ctxt; - struct qdma_descq_cmpt_ctxt q_cmpt_ctxt; - struct qdma_descq_hw_ctxt q_hw_ctxt; - struct qdma_descq_credit_ctxt q_credit_ctxt; - struct qdma_hw_access *hw_access = qdma_dev->hw_access; - - hw_access->qdma_sw_ctx_conf(dev, 1, qid, &q_sw_ctxt, - QDMA_HW_ACCESS_INVALIDATE); - hw_access->qdma_hw_ctx_conf(dev, 1, qid, &q_hw_ctxt, - QDMA_HW_ACCESS_INVALIDATE); - if (mode) { /** ST-mode **/ - hw_access->qdma_pfetch_ctx_conf(dev, qid, - &q_prefetch_ctxt, QDMA_HW_ACCESS_INVALIDATE); - hw_access->qdma_cmpt_ctx_conf(dev, qid, - &q_cmpt_ctxt, QDMA_HW_ACCESS_INVALIDATE); - hw_access->qdma_credit_ctx_conf(dev, 1, qid, - &q_credit_ctxt, QDMA_HW_ACCESS_INVALIDATE); - } -} - -/** - * Clears the Rx queue contexts. - * - * @param dev - * Pointer to Ethernet device structure. - * - * @return - * Nothing. - */ -void qdma_clr_rx_queue_ctxts(struct rte_eth_dev *dev, - uint32_t qid, uint32_t mode) -{ - struct qdma_pci_dev *qdma_dev = dev->data->dev_private; - struct qdma_descq_prefetch_ctxt q_prefetch_ctxt; - struct qdma_descq_cmpt_ctxt q_cmpt_ctxt; - struct qdma_descq_hw_ctxt q_hw_ctxt; - struct qdma_descq_credit_ctxt q_credit_ctxt; - struct qdma_descq_sw_ctxt q_sw_ctxt; - struct qdma_hw_access *hw_access = qdma_dev->hw_access; - - hw_access->qdma_sw_ctx_conf(dev, 1, qid, &q_sw_ctxt, - QDMA_HW_ACCESS_CLEAR); - hw_access->qdma_hw_ctx_conf(dev, 1, qid, &q_hw_ctxt, - QDMA_HW_ACCESS_CLEAR); - if (mode) { /** ST-mode **/ - hw_access->qdma_pfetch_ctx_conf(dev, qid, - &q_prefetch_ctxt, QDMA_HW_ACCESS_CLEAR); - hw_access->qdma_cmpt_ctx_conf(dev, qid, - &q_cmpt_ctxt, QDMA_HW_ACCESS_CLEAR); - hw_access->qdma_credit_ctx_conf(dev, 1, qid, - &q_credit_ctxt, QDMA_HW_ACCESS_CLEAR); - } -} - -int qdma_init_rx_queue(struct qdma_rx_queue *rxq) -{ - struct rte_mbuf *mb; - void *obj = NULL; - uint64_t phys_addr; - uint16_t i; - struct qdma_ul_st_c2h_desc *rx_ring_st = NULL; - - /* allocate new buffers for the Rx descriptor ring */ - if (rxq->st_mode) { /** ST-mode **/ - rx_ring_st = (struct qdma_ul_st_c2h_desc *)rxq->rx_ring; -#ifdef DUMP_MEMPOOL_USAGE_STATS - PMD_DRV_LOG(INFO, "%s(): %d: queue id %d, mbuf_avail_count =%d," - "mbuf_in_use_count = %d", - __func__, __LINE__, rxq->queue_id, - rte_mempool_avail_count(rxq->mb_pool), - rte_mempool_in_use_count(rxq->mb_pool)); -#endif //DUMP_MEMPOOL_USAGE_STATS - for (i = 0; i < (rxq->nb_rx_desc - 2); i++) { - if (rte_mempool_get(rxq->mb_pool, &obj) != 0) { - PMD_DRV_LOG(ERR, "qdma-start-rx-queue(): " - "rte_mempool_get: failed"); - goto fail; - } - - if (obj != NULL) - mb = obj; - else { - PMD_DRV_LOG(ERR, "%s(): %d: qid %d, rte_mempool_get failed", - __func__, __LINE__, rxq->queue_id); - goto fail; - } - - phys_addr = (uint64_t)mb->buf_iova + - RTE_PKTMBUF_HEADROOM; - - mb->data_off = RTE_PKTMBUF_HEADROOM; - rxq->sw_ring[i] = mb; - rx_ring_st[i].dst_addr = phys_addr; - } -#ifdef DUMP_MEMPOOL_USAGE_STATS - PMD_DRV_LOG(INFO, "%s(): %d: qid %d, mbuf_avail_count = %d," - "mbuf_in_use_count = %d", - __func__, __LINE__, rxq->queue_id, - rte_mempool_avail_count(rxq->mb_pool), - rte_mempool_in_use_count(rxq->mb_pool)); -#endif //DUMP_MEMPOOL_USAGE_STATS - } - - /* initialize tail */ - rxq->rx_tail = 0; - - return 0; -fail: - return -ENOMEM; -} - -/* - * Tx queue reset - */ -void qdma_reset_tx_queue(struct qdma_tx_queue *txq) -{ - uint32_t i; - uint32_t sz; - - txq->tx_fl_tail = 0; - if (txq->st_mode) { /** ST-mode **/ - sz = sizeof(struct qdma_ul_st_h2c_desc); - /* Zero out HW ring memory */ - for (i = 0; i < (sz * (txq->nb_tx_desc)); i++) - ((volatile char *)txq->tx_ring)[i] = 0; - } else { - sz = sizeof(struct qdma_ul_mm_desc); - /* Zero out HW ring memory */ - for (i = 0; i < (sz * (txq->nb_tx_desc)); i++) - ((volatile char *)txq->tx_ring)[i] = 0; - } - - /* Initialize SW ring entries */ - for (i = 0; i < txq->nb_tx_desc; i++) - txq->sw_ring[i] = NULL; -} - -void qdma_inv_tx_queue_ctxts(struct rte_eth_dev *dev, - uint32_t qid, uint32_t mode) -{ - struct qdma_pci_dev *qdma_dev = dev->data->dev_private; - struct qdma_descq_sw_ctxt q_sw_ctxt; - struct qdma_descq_hw_ctxt q_hw_ctxt; - struct qdma_descq_credit_ctxt q_credit_ctxt; - struct qdma_hw_access *hw_access = qdma_dev->hw_access; - - hw_access->qdma_sw_ctx_conf(dev, 0, qid, &q_sw_ctxt, - QDMA_HW_ACCESS_INVALIDATE); - hw_access->qdma_hw_ctx_conf(dev, 0, qid, &q_hw_ctxt, - QDMA_HW_ACCESS_INVALIDATE); - - if (mode) { /** ST-mode **/ - hw_access->qdma_credit_ctx_conf(dev, 0, qid, - &q_credit_ctxt, QDMA_HW_ACCESS_INVALIDATE); - } -} - -/** - * Clear Tx queue contexts - * - * @param dev - * Pointer to Ethernet device structure. - * - * @return - * Nothing. - */ -void qdma_clr_tx_queue_ctxts(struct rte_eth_dev *dev, - uint32_t qid, uint32_t mode) -{ - struct qdma_pci_dev *qdma_dev = dev->data->dev_private; - struct qdma_descq_sw_ctxt q_sw_ctxt; - struct qdma_descq_credit_ctxt q_credit_ctxt; - struct qdma_descq_hw_ctxt q_hw_ctxt; - struct qdma_hw_access *hw_access = qdma_dev->hw_access; - - hw_access->qdma_sw_ctx_conf(dev, 0, qid, &q_sw_ctxt, - QDMA_HW_ACCESS_CLEAR); - hw_access->qdma_hw_ctx_conf(dev, 0, qid, &q_hw_ctxt, - QDMA_HW_ACCESS_CLEAR); - if (mode) { /** ST-mode **/ - hw_access->qdma_credit_ctx_conf(dev, 0, qid, - &q_credit_ctxt, QDMA_HW_ACCESS_CLEAR); - } -} - -/* Utility function to find index of an element in an array */ -int index_of_array(uint32_t *arr, uint32_t n, uint32_t element) -{ - int index = 0; - - for (index = 0; (uint32_t)index < n; index++) { - if (*(arr + index) == element) - return index; - } - return -1; -} - -static int pfetch_check_handler(__rte_unused const char *key, - const char *value, void *opaque) -{ - struct qdma_pci_dev *qdma_dev = (struct qdma_pci_dev *)opaque; - char *end = NULL; - uint8_t desc_prefetch; - - PMD_DRV_LOG(INFO, "QDMA devargs desc_prefetch is: %s\n", value); - desc_prefetch = (uint8_t)strtoul(value, &end, 10); - if (desc_prefetch > 1) { - PMD_DRV_LOG(INFO, "QDMA devargs prefetch should be 1 or 0," - " setting to 1.\n"); - } - qdma_dev->en_desc_prefetch = desc_prefetch ? 1 : 0; - return 0; -} - -static int cmpt_desc_len_check_handler(__rte_unused const char *key, - const char *value, void *opaque) -{ - struct qdma_pci_dev *qdma_dev = (struct qdma_pci_dev *)opaque; - char *end = NULL; - - PMD_DRV_LOG(INFO, "QDMA devargs cmpt_desc_len is: %s\n", value); - qdma_dev->cmpt_desc_len = (uint8_t)strtoul(value, &end, 10); - if (qdma_dev->cmpt_desc_len != RTE_PMD_QDMA_CMPT_DESC_LEN_8B && - qdma_dev->cmpt_desc_len != RTE_PMD_QDMA_CMPT_DESC_LEN_16B && - qdma_dev->cmpt_desc_len != RTE_PMD_QDMA_CMPT_DESC_LEN_32B && - (qdma_dev->cmpt_desc_len != RTE_PMD_QDMA_CMPT_DESC_LEN_64B || - !qdma_dev->dev_cap.cmpt_desc_64b)) { - PMD_DRV_LOG(INFO, "QDMA devargs incorrect cmpt_desc_len = %d " - "specified\n", - qdma_dev->cmpt_desc_len); - return -1; - } - - return 0; -} - -static int trigger_mode_handler(__rte_unused const char *key, - const char *value, void *opaque) -{ - struct qdma_pci_dev *qdma_dev = (struct qdma_pci_dev *)opaque; - char *end = NULL; - - PMD_DRV_LOG(INFO, "QDMA devargs trigger mode: %s\n", value); - qdma_dev->trigger_mode = (uint8_t)strtoul(value, &end, 10); - - if (qdma_dev->trigger_mode >= RTE_PMD_QDMA_TRIG_MODE_MAX) { - qdma_dev->trigger_mode = RTE_PMD_QDMA_TRIG_MODE_MAX; - PMD_DRV_LOG(INFO, "QDMA devargs trigger mode invalid," - "reset to default: %d\n", - qdma_dev->trigger_mode); - } - return 0; -} - -static int config_bar_idx_handler(__rte_unused const char *key, - const char *value, void *opaque) -{ - struct qdma_pci_dev *qdma_dev = (struct qdma_pci_dev *)opaque; - char *end = NULL; - - PMD_DRV_LOG(INFO, "QDMA devargs trigger mode: %s\n", value); - qdma_dev->config_bar_idx = (int)strtoul(value, &end, 10); - - if (qdma_dev->config_bar_idx >= QDMA_NUM_BARS || - qdma_dev->config_bar_idx < 0) { - PMD_DRV_LOG(INFO, "QDMA devargs config bar idx invalid: %d\n", - qdma_dev->config_bar_idx); - return -1; - } - return 0; -} - -static int c2h_byp_mode_check_handler(__rte_unused const char *key, - const char *value, void *opaque) -{ - struct qdma_pci_dev *qdma_dev = (struct qdma_pci_dev *)opaque; - char *end = NULL; - - PMD_DRV_LOG(INFO, "QDMA devargs c2h_byp_mode is: %s\n", value); - qdma_dev->c2h_bypass_mode = (uint8_t)strtoul(value, &end, 10); - - if (qdma_dev->c2h_bypass_mode >= RTE_PMD_QDMA_RX_BYPASS_MAX) { - PMD_DRV_LOG(INFO, "QDMA devargs incorrect " - "c2h_byp_mode= %d specified\n", - qdma_dev->c2h_bypass_mode); - return -1; - } - - return 0; -} - -static int h2c_byp_mode_check_handler(__rte_unused const char *key, - const char *value, void *opaque) -{ - struct qdma_pci_dev *qdma_dev = (struct qdma_pci_dev *)opaque; - char *end = NULL; - - PMD_DRV_LOG(INFO, "QDMA devargs h2c_byp_mode is: %s\n", value); - qdma_dev->h2c_bypass_mode = (uint8_t)strtoul(value, &end, 10); - - if (qdma_dev->h2c_bypass_mode > 1) { - PMD_DRV_LOG(INFO, "QDMA devargs incorrect" - " h2c_byp_mode =%d specified\n", - qdma_dev->h2c_bypass_mode); - return -1; - } - - return 0; -} -#ifdef TANDEM_BOOT_SUPPORTED -static int en_st_mode_check_handler(__rte_unused const char *key, - const char *value, void *opaque) -{ - struct qdma_pci_dev *qdma_dev = (struct qdma_pci_dev *)opaque; - char *end = NULL; - - PMD_DRV_LOG(INFO, "QDMA devargs en_st is: %s\n", value); - qdma_dev->en_st_mode = (uint8_t)strtoul(value, &end, 10); - - if (qdma_dev->en_st_mode > 1) { - PMD_DRV_LOG(INFO, "QDMA devargs incorrect" - " en_st_mode =%d specified\n", - qdma_dev->en_st_mode); - return -1; - } - - return 0; -} -#endif -/* Process the all devargs */ -int qdma_check_kvargs(struct rte_devargs *devargs, - struct qdma_pci_dev *qdma_dev) -{ - struct rte_kvargs *kvlist; - const char *pfetch_key = "desc_prefetch"; - const char *cmpt_desc_len_key = "cmpt_desc_len"; - const char *trigger_mode_key = "trigger_mode"; - const char *config_bar_key = "config_bar"; - const char *c2h_byp_mode_key = "c2h_byp_mode"; - const char *h2c_byp_mode_key = "h2c_byp_mode"; -#ifdef TANDEM_BOOT_SUPPORTED - const char *en_st_key = "en_st"; -#endif - int ret = 0; - - if (!devargs) - return 0; - - kvlist = rte_kvargs_parse(devargs->args, NULL); - if (!kvlist) - return 0; - - /* process the desc_prefetch*/ - if (rte_kvargs_count(kvlist, pfetch_key)) { - ret = rte_kvargs_process(kvlist, pfetch_key, - pfetch_check_handler, qdma_dev); - if (ret) { - rte_kvargs_free(kvlist); - return ret; - } - } - - /* process the cmpt_desc_len*/ - if (rte_kvargs_count(kvlist, cmpt_desc_len_key)) { - ret = rte_kvargs_process(kvlist, cmpt_desc_len_key, - cmpt_desc_len_check_handler, qdma_dev); - if (ret) { - rte_kvargs_free(kvlist); - return ret; - } - } - - /* process the trigger_mode*/ - if (rte_kvargs_count(kvlist, trigger_mode_key)) { - ret = rte_kvargs_process(kvlist, trigger_mode_key, - trigger_mode_handler, qdma_dev); - if (ret) { - rte_kvargs_free(kvlist); - return ret; - } - } - - /* process the config bar*/ - if (rte_kvargs_count(kvlist, config_bar_key)) { - ret = rte_kvargs_process(kvlist, config_bar_key, - config_bar_idx_handler, qdma_dev); - if (ret) { - rte_kvargs_free(kvlist); - return ret; - } - } - - /* process c2h_byp_mode*/ - if (rte_kvargs_count(kvlist, c2h_byp_mode_key)) { - ret = rte_kvargs_process(kvlist, c2h_byp_mode_key, - c2h_byp_mode_check_handler, qdma_dev); - if (ret) { - rte_kvargs_free(kvlist); - return ret; - } - } - - /* process h2c_byp_mode*/ - if (rte_kvargs_count(kvlist, h2c_byp_mode_key)) { - ret = rte_kvargs_process(kvlist, h2c_byp_mode_key, - h2c_byp_mode_check_handler, qdma_dev); - if (ret) { - rte_kvargs_free(kvlist); - return ret; - } - } - -#ifdef TANDEM_BOOT_SUPPORTED - /* Enable ST */ - if (rte_kvargs_count(kvlist, en_st_key)) { - ret = rte_kvargs_process(kvlist, en_st_key, - en_st_mode_check_handler, qdma_dev); - if (ret) { - rte_kvargs_free(kvlist); - return ret; - } - } -#endif - - rte_kvargs_free(kvlist); - return ret; -} - -int qdma_identify_bars(struct rte_eth_dev *dev) -{ - int bar_len, i, ret; - uint8_t usr_bar; - struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); - struct qdma_pci_dev *dma_priv; - - dma_priv = (struct qdma_pci_dev *)dev->data->dev_private; - - /* Config bar */ - bar_len = pci_dev->mem_resource[dma_priv->config_bar_idx].len; - if (!bar_len) { - PMD_DRV_LOG(INFO, "QDMA config BAR index :%d is not enabled", - dma_priv->config_bar_idx); - return -1; - } - - /* Find AXI Master Lite(user bar) */ - ret = dma_priv->hw_access->qdma_get_user_bar(dev, - dma_priv->is_vf, dma_priv->func_id, &usr_bar); - if ((ret != QDMA_SUCCESS) || - (pci_dev->mem_resource[usr_bar].len == 0)) { - if (dma_priv->ip_type == QDMA_VERSAL_HARD_IP) { - if (pci_dev->mem_resource[1].len == 0) - dma_priv->user_bar_idx = 2; - else - dma_priv->user_bar_idx = 1; - } else { - dma_priv->user_bar_idx = -1; - PMD_DRV_LOG(INFO, "Cannot find AXI Master Lite BAR"); - } - } else - dma_priv->user_bar_idx = usr_bar; - - /* Find AXI Bridge Master bar(bypass bar) */ - for (i = 0; i < QDMA_NUM_BARS; i++) { - bar_len = pci_dev->mem_resource[i].len; - if (!bar_len) /* Bar not enabled ? */ - continue; - if (dma_priv->user_bar_idx != i && - dma_priv->config_bar_idx != i) { - dma_priv->bypass_bar_idx = i; - break; - } - } - - PMD_DRV_LOG(INFO, "QDMA config bar idx :%d\n", - dma_priv->config_bar_idx); - PMD_DRV_LOG(INFO, "QDMA AXI Master Lite bar idx :%d\n", - dma_priv->user_bar_idx); - PMD_DRV_LOG(INFO, "QDMA AXI Bridge Master bar idx :%d\n", - dma_priv->bypass_bar_idx); - - return 0; -} -int qdma_get_hw_version(struct rte_eth_dev *dev) -{ - int ret; - struct qdma_pci_dev *dma_priv; - struct qdma_hw_version_info version_info; - - dma_priv = (struct qdma_pci_dev *)dev->data->dev_private; - ret = dma_priv->hw_access->qdma_get_version(dev, - dma_priv->is_vf, &version_info); - if (ret < 0) - return dma_priv->hw_access->qdma_get_error_code(ret); - - dma_priv->rtl_version = version_info.rtl_version; - dma_priv->vivado_rel = version_info.vivado_release; - dma_priv->device_type = version_info.device_type; - dma_priv->ip_type = version_info.ip_type; - - PMD_DRV_LOG(INFO, "QDMA RTL VERSION : %s\n", - version_info.qdma_rtl_version_str); - PMD_DRV_LOG(INFO, "QDMA DEVICE TYPE : %s\n", - version_info.qdma_device_type_str); - PMD_DRV_LOG(INFO, "QDMA VIVADO RELEASE ID : %s\n", - version_info.qdma_vivado_release_id_str); - if (version_info.ip_type == QDMA_VERSAL_HARD_IP) { - PMD_DRV_LOG(INFO, "QDMA VERSAL IP TYPE : %s\n", - version_info.qdma_ip_type_str); - } - - return 0; -} diff --git a/QDMA/DPDK/drivers/net/qdma/qdma_devops.c b/QDMA/DPDK/drivers/net/qdma/qdma_devops.c deleted file mode 100755 index 45c9b4f19..000000000 --- a/QDMA/DPDK/drivers/net/qdma/qdma_devops.c +++ /dev/null @@ -1,1984 +0,0 @@ -/*- - * BSD LICENSE - * - * Copyright (c) 2017-2022 Xilinx, Inc. All rights reserved. - * Copyright (c) 2022-2023, Advanced Micro Devices, Inc. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * * Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include "qdma.h" -#include "qdma_access_common.h" -#include "qdma_mbox_protocol.h" -#include "qdma_mbox.h" -#include "qdma_reg_dump.h" -#include "qdma_platform.h" -#include "qdma_devops.h" - -#ifdef QDMA_LATENCY_OPTIMIZED -static void qdma_sort_c2h_cntr_th_values(struct qdma_pci_dev *qdma_dev) -{ - uint8_t i, idx = 0, j = 0; - uint8_t c2h_cntr_val = qdma_dev->g_c2h_cnt_th[0]; - uint8_t least_max = 0; - int ref_idx = -1; - -get_next_idx: - for (i = 0; i < QDMA_NUM_C2H_COUNTERS; i++) { - if ((ref_idx >= 0) && (ref_idx == i)) - continue; - if (qdma_dev->g_c2h_cnt_th[i] < least_max) - continue; - c2h_cntr_val = qdma_dev->g_c2h_cnt_th[i]; - idx = i; - break; - } - for (; i < QDMA_NUM_C2H_COUNTERS; i++) { - if ((ref_idx >= 0) && (ref_idx == i)) - continue; - if (qdma_dev->g_c2h_cnt_th[i] < least_max) - continue; - if (c2h_cntr_val >= qdma_dev->g_c2h_cnt_th[i]) { - c2h_cntr_val = qdma_dev->g_c2h_cnt_th[i]; - idx = i; - } - } - qdma_dev->sorted_idx_c2h_cnt_th[j] = idx; - ref_idx = idx; - j++; - idx = j; - least_max = c2h_cntr_val; - if (j < QDMA_NUM_C2H_COUNTERS) - goto get_next_idx; -} -#endif //QDMA_LATENCY_OPTIMIZED - -int qdma_vf_csr_read(struct rte_eth_dev *dev) -{ - struct qdma_pci_dev *qdma_dev = dev->data->dev_private; - struct qdma_mbox_msg *m = qdma_mbox_msg_alloc(); - int rv, i; - struct qdma_csr_info csr_info; - - if (!m) - return -ENOMEM; - - qdma_mbox_compose_csr_read(qdma_dev->func_id, m->raw_data); - rv = qdma_mbox_msg_send(dev, m, MBOX_OP_RSP_TIMEOUT); - if (rv < 0) - goto free_msg; - - rv = qdma_mbox_vf_csr_get(m->raw_data, &csr_info); - if (rv < 0) - goto free_msg; - for (i = 0; i < QDMA_NUM_RING_SIZES; i++) { - qdma_dev->g_ring_sz[i] = (uint32_t)csr_info.ringsz[i]; - qdma_dev->g_c2h_buf_sz[i] = (uint32_t)csr_info.bufsz[i]; - qdma_dev->g_c2h_timer_cnt[i] = (uint32_t)csr_info.timer_cnt[i]; - qdma_dev->g_c2h_cnt_th[i] = (uint32_t)csr_info.cnt_thres[i]; -#ifdef QDMA_LATENCY_OPTIMIZED - qdma_sort_c2h_cntr_th_values(qdma_dev); -#endif //QDMA_LATENCY_OPTIMIZED - } - - -free_msg: - qdma_mbox_msg_free(m); - return rv; -} - -int qdma_pf_csr_read(struct rte_eth_dev *dev) -{ - int ret = 0; - struct qdma_pci_dev *qdma_dev = dev->data->dev_private; - struct qdma_hw_access *hw_access = qdma_dev->hw_access; - - ret = hw_access->qdma_global_csr_conf(dev, 0, - QDMA_NUM_RING_SIZES, qdma_dev->g_ring_sz, - QDMA_CSR_RING_SZ, QDMA_HW_ACCESS_READ); - if (ret != QDMA_SUCCESS) - PMD_DRV_LOG(ERR, "qdma_global_csr_conf for ring size " - "returned %d", ret); - if (qdma_dev->dev_cap.st_en || qdma_dev->dev_cap.mm_cmpt_en) { - ret = hw_access->qdma_global_csr_conf(dev, 0, - QDMA_NUM_C2H_TIMERS, qdma_dev->g_c2h_timer_cnt, - QDMA_CSR_TIMER_CNT, QDMA_HW_ACCESS_READ); - if (ret != QDMA_SUCCESS) - PMD_DRV_LOG(ERR, "qdma_global_csr_conf for timer count " - "returned %d", ret); - - ret = hw_access->qdma_global_csr_conf(dev, 0, - QDMA_NUM_C2H_COUNTERS, qdma_dev->g_c2h_cnt_th, - QDMA_CSR_CNT_TH, QDMA_HW_ACCESS_READ); - if (ret != QDMA_SUCCESS) - PMD_DRV_LOG(ERR, "qdma_global_csr_conf for counter threshold " - "returned %d", ret); -#ifdef QDMA_LATENCY_OPTIMIZED - qdma_sort_c2h_cntr_th_values(qdma_dev); -#endif //QDMA_LATENCY_OPTIMIZED - } - - if (qdma_dev->dev_cap.st_en) { - ret = hw_access->qdma_global_csr_conf(dev, 0, - QDMA_NUM_C2H_BUFFER_SIZES, - qdma_dev->g_c2h_buf_sz, - QDMA_CSR_BUF_SZ, - QDMA_HW_ACCESS_READ); - if (ret != QDMA_SUCCESS) - PMD_DRV_LOG(ERR, "qdma_global_csr_conf for buffer sizes " - "returned %d", ret); - } - - if (ret < 0) - return qdma_dev->hw_access->qdma_get_error_code(ret); - - return ret; -} - -static int qdma_pf_fmap_prog(struct rte_eth_dev *dev) -{ - struct qdma_pci_dev *qdma_dev = dev->data->dev_private; - struct qdma_fmap_cfg fmap_cfg; - int ret = 0; - - memset(&fmap_cfg, 0, sizeof(struct qdma_fmap_cfg)); - - /** FMAP configuration **/ - fmap_cfg.qbase = qdma_dev->queue_base; - fmap_cfg.qmax = qdma_dev->qsets_en; - ret = qdma_dev->hw_access->qdma_fmap_conf(dev, - qdma_dev->func_id, &fmap_cfg, QDMA_HW_ACCESS_WRITE); - if (ret < 0) - return qdma_dev->hw_access->qdma_get_error_code(ret); - - return ret; -} - -int qdma_dev_notify_qadd(struct rte_eth_dev *dev, uint32_t qidx_hw, - enum qdma_dev_q_type q_type) -{ - struct qdma_pci_dev *qdma_dev = dev->data->dev_private; - struct qdma_mbox_msg *m; - int rv = 0; - - m = qdma_mbox_msg_alloc(); - if (!m) - return -ENOMEM; - - qdma_mbox_compose_vf_notify_qadd(qdma_dev->func_id, qidx_hw, - q_type, m->raw_data); - rv = qdma_mbox_msg_send(dev, m, MBOX_OP_RSP_TIMEOUT); - - qdma_mbox_msg_free(m); - return rv; -} - -int qdma_dev_notify_qdel(struct rte_eth_dev *dev, uint32_t qidx_hw, - enum qdma_dev_q_type q_type) -{ - struct qdma_pci_dev *qdma_dev = dev->data->dev_private; - struct qdma_mbox_msg *m; - int rv = 0; - - m = qdma_mbox_msg_alloc(); - if (!m) - return -ENOMEM; - - qdma_mbox_compose_vf_notify_qdel(qdma_dev->func_id, qidx_hw, - q_type, m->raw_data); - rv = qdma_mbox_msg_send(dev, m, MBOX_OP_RSP_TIMEOUT); - - qdma_mbox_msg_free(m); - return rv; -} - -uint8_t qmda_get_desc_sz_idx(enum rte_pmd_qdma_bypass_desc_len size) -{ - return ((size == RTE_PMD_QDMA_BYPASS_DESC_LEN_64B) ? 3 : - (size == RTE_PMD_QDMA_BYPASS_DESC_LEN_32B) ? 2 : - (size == RTE_PMD_QDMA_BYPASS_DESC_LEN_16B) ? 1 : - /* (size == RTE_PMD_QDMA_BYPASS_DESC_LEN_8B) */0); -} - -static inline int -qdma_rxq_default_mbuf_init(struct qdma_rx_queue *rxq) -{ - uintptr_t p; - struct rte_mbuf mb = { .buf_addr = 0 }; - - mb.nb_segs = 1; - mb.data_off = RTE_PKTMBUF_HEADROOM; - mb.port = rxq->port_id; - rte_mbuf_refcnt_set(&mb, 1); - - /* prevent compiler reordering */ - rte_compiler_barrier(); - p = (uintptr_t)&mb.rearm_data; - rxq->mbuf_initializer = *(uint64_t *)p; - return 0; -} - -/** - * DPDK callback to configure a RX queue. - * - * @param dev - * Pointer to Ethernet device structure. - * @param rx_queue_id - * RX queue index. - * @param nb_rx_desc - * Number of descriptors to configure in queue. - * @param socket_id - * NUMA socket on which memory must be allocated. - * @param[in] rx_conf - * Thresholds parameters. - * @param mp_pool - * Memory pool for buffer allocations. - * - * @return - * 0 on success, - * -ENOMEM when memory allocation fails - * -ENOTSUP when HW doesn't support the required configuration - * -EINVAL on other failure. - */ -int qdma_dev_rx_queue_setup(struct rte_eth_dev *dev, uint16_t rx_queue_id, - uint16_t nb_rx_desc, unsigned int socket_id, - const struct rte_eth_rxconf *rx_conf, - struct rte_mempool *mb_pool) -{ - struct qdma_pci_dev *qdma_dev = dev->data->dev_private; - struct qdma_rx_queue *rxq = NULL; - struct qdma_ul_mm_desc *rx_ring_mm; - uint32_t sz; - uint8_t *rx_ring_bypass; - int err = 0; - - PMD_DRV_LOG(INFO, "Configuring Rx queue id:%d\n", rx_queue_id); - - if (nb_rx_desc == 0) { - PMD_DRV_LOG(ERR, "Invalid descriptor ring size %d\n", - nb_rx_desc); - return -EINVAL; - } - - if (!qdma_dev->dev_configured) { - PMD_DRV_LOG(ERR, - "Device for Rx queue id %d is not configured yet\n", - rx_queue_id); - return -EINVAL; - } - - if (!qdma_dev->is_vf) { - err = qdma_dev_increment_active_queue( - qdma_dev->dma_device_index, - qdma_dev->func_id, - QDMA_DEV_Q_TYPE_C2H); - if (err != QDMA_SUCCESS) - return -EINVAL; - - if (qdma_dev->q_info[rx_queue_id].queue_mode == - RTE_PMD_QDMA_STREAMING_MODE) { - err = qdma_dev_increment_active_queue( - qdma_dev->dma_device_index, - qdma_dev->func_id, - QDMA_DEV_Q_TYPE_CMPT); - if (err != QDMA_SUCCESS) { - qdma_dev_decrement_active_queue( - qdma_dev->dma_device_index, - qdma_dev->func_id, - QDMA_DEV_Q_TYPE_C2H); - return -EINVAL; - } - } - } else { - err = qdma_dev_notify_qadd(dev, rx_queue_id + - qdma_dev->queue_base, - QDMA_DEV_Q_TYPE_C2H); - if (err < 0) - return -EINVAL; - - if (qdma_dev->q_info[rx_queue_id].queue_mode == - RTE_PMD_QDMA_STREAMING_MODE) { - err = qdma_dev_notify_qadd(dev, rx_queue_id + - qdma_dev->queue_base, - QDMA_DEV_Q_TYPE_CMPT); - if (err < 0) { - qdma_dev_notify_qdel(dev, rx_queue_id + - qdma_dev->queue_base, - QDMA_DEV_Q_TYPE_C2H); - return -EINVAL; - } - } - } - if (!qdma_dev->init_q_range) { - if (qdma_dev->is_vf) { - err = qdma_vf_csr_read(dev); - if (err < 0) - goto rx_setup_err; - } else { - err = qdma_pf_csr_read(dev); - if (err < 0) - goto rx_setup_err; - } - qdma_dev->init_q_range = 1; - } - - /* allocate rx queue data structure */ - rxq = rte_zmalloc_socket("QDMA_RxQ", sizeof(struct qdma_rx_queue), - RTE_CACHE_LINE_SIZE, socket_id); - if (!rxq) { - PMD_DRV_LOG(ERR, "Unable to allocate structure rxq of " - "size %d\n", - (int)(sizeof(struct qdma_rx_queue))); - err = -ENOMEM; - goto rx_setup_err; - } - - rxq->queue_id = rx_queue_id; - rxq->port_id = dev->data->port_id; - rxq->func_id = qdma_dev->func_id; - rxq->mb_pool = mb_pool; - rxq->dev = dev; - rxq->st_mode = qdma_dev->q_info[rx_queue_id].queue_mode; - - rxq->nb_rx_desc = (nb_rx_desc + 1); - /* <= 2018.2 IP - * double the cmpl ring size to avoid run out of cmpl entry while - * desc. ring still have free entries - */ - rxq->nb_rx_cmpt_desc = ((nb_rx_desc * 2) + 1); - rxq->en_prefetch = qdma_dev->q_info[rx_queue_id].en_prefetch; - rxq->cmpt_desc_len = qdma_dev->q_info[rx_queue_id].cmpt_desc_sz; - if ((rxq->cmpt_desc_len == RTE_PMD_QDMA_CMPT_DESC_LEN_64B) && - !qdma_dev->dev_cap.cmpt_desc_64b) { - PMD_DRV_LOG(ERR, "PF-%d(DEVFN) 64B completion entry size is " - "not supported in this design\n", qdma_dev->func_id); - return -ENOTSUP; - } - rxq->triggermode = qdma_dev->q_info[rx_queue_id].trigger_mode; - rxq->rx_deferred_start = rx_conf->rx_deferred_start; - rxq->dump_immediate_data = - qdma_dev->q_info[rx_queue_id].immediate_data_state; - rxq->dis_overflow_check = - qdma_dev->q_info[rx_queue_id].dis_cmpt_ovf_chk; - - if (qdma_dev->q_info[rx_queue_id].rx_bypass_mode == - RTE_PMD_QDMA_RX_BYPASS_CACHE || - qdma_dev->q_info[rx_queue_id].rx_bypass_mode == - RTE_PMD_QDMA_RX_BYPASS_SIMPLE) - rxq->en_bypass = 1; - if (qdma_dev->q_info[rx_queue_id].rx_bypass_mode == - RTE_PMD_QDMA_RX_BYPASS_SIMPLE) - rxq->en_bypass_prefetch = 1; - - if (qdma_dev->ip_type == EQDMA_SOFT_IP && - qdma_dev->vivado_rel >= QDMA_VIVADO_2020_2) { - if (qdma_dev->dev_cap.desc_eng_mode == - QDMA_DESC_ENG_BYPASS_ONLY) { - PMD_DRV_LOG(ERR, - "Bypass only mode design " - "is not supported\n"); - return -ENOTSUP; - } - - if (rxq->en_bypass && - (qdma_dev->dev_cap.desc_eng_mode == - QDMA_DESC_ENG_INTERNAL_ONLY)) { - PMD_DRV_LOG(ERR, - "Rx qid %d config in bypass " - "mode not supported on " - "internal only mode design\n", - rx_queue_id); - return -ENOTSUP; - } - } - - if (rxq->en_bypass) { - rxq->bypass_desc_sz = - qdma_dev->q_info[rx_queue_id].rx_bypass_desc_sz; - if ((rxq->bypass_desc_sz == RTE_PMD_QDMA_BYPASS_DESC_LEN_64B) - && !qdma_dev->dev_cap.sw_desc_64b) { - PMD_DRV_LOG(ERR, "PF-%d(DEVFN) C2H bypass descriptor " - "size of 64B is not supported in this design:\n", - qdma_dev->func_id); - return -ENOTSUP; - } - } - /* Calculate the ring index, completion queue ring size, - * buffer index and threshold index. - * If index is not found , by default use the index as 0 - */ - - /* Find C2H queue ring size index */ - rxq->ringszidx = index_of_array(qdma_dev->g_ring_sz, - QDMA_NUM_RING_SIZES, rxq->nb_rx_desc); - if (rxq->ringszidx < 0) { - PMD_DRV_LOG(ERR, "Expected Ring size %d not found\n", - rxq->nb_rx_desc); - err = -EINVAL; - goto rx_setup_err; - } - - /* Find completion ring size index */ - rxq->cmpt_ringszidx = index_of_array(qdma_dev->g_ring_sz, - QDMA_NUM_RING_SIZES, - rxq->nb_rx_cmpt_desc); - if (rxq->cmpt_ringszidx < 0) { - PMD_DRV_LOG(ERR, "Expected completion ring size %d not found\n", - rxq->nb_rx_cmpt_desc); - err = -EINVAL; - goto rx_setup_err; - } - - /* Find Threshold index */ - rxq->threshidx = index_of_array(qdma_dev->g_c2h_cnt_th, - QDMA_NUM_C2H_COUNTERS, - rx_conf->rx_thresh.wthresh); - if (rxq->threshidx < 0) { - PMD_DRV_LOG(WARNING, "Expected Threshold %d not found," - " using the value %d at index 7\n", - rx_conf->rx_thresh.wthresh, - qdma_dev->g_c2h_cnt_th[7]); - rxq->threshidx = 7; - } - -#ifdef QDMA_LATENCY_OPTIMIZED - uint8_t next_idx; - - /* Initialize sorted_c2h_cntr_idx */ - rxq->sorted_c2h_cntr_idx = index_of_array( - qdma_dev->sorted_idx_c2h_cnt_th, - QDMA_NUM_C2H_COUNTERS, - qdma_dev->g_c2h_cnt_th[rxq->threshidx]); - - if (rxq->sorted_c2h_cntr_idx < 0) { - PMD_DRV_LOG(ERR, - "Expected counter threshold %d not found\n", - qdma_dev->g_c2h_cnt_th[rxq->threshidx]); - err = -EINVAL; - goto rx_setup_err; - } - - /* Initialize pend_pkt_moving_avg */ - rxq->pend_pkt_moving_avg = qdma_dev->g_c2h_cnt_th[rxq->threshidx]; - - /* Initialize pend_pkt_avg_thr_hi */ - if (rxq->sorted_c2h_cntr_idx < (QDMA_NUM_C2H_COUNTERS - 1)) - next_idx = qdma_dev->sorted_idx_c2h_cnt_th[ - rxq->sorted_c2h_cntr_idx + 1]; - else - next_idx = qdma_dev->sorted_idx_c2h_cnt_th[ - rxq->sorted_c2h_cntr_idx]; - - rxq->pend_pkt_avg_thr_hi = qdma_dev->g_c2h_cnt_th[next_idx]; - - /* Initialize pend_pkt_avg_thr_lo */ - if (rxq->sorted_c2h_cntr_idx > 0) - next_idx = qdma_dev->sorted_idx_c2h_cnt_th[ - rxq->sorted_c2h_cntr_idx - 1]; - else - next_idx = qdma_dev->sorted_idx_c2h_cnt_th[ - rxq->sorted_c2h_cntr_idx]; - - rxq->pend_pkt_avg_thr_lo = qdma_dev->g_c2h_cnt_th[next_idx]; -#endif //QDMA_LATENCY_OPTIMIZED - - /* Find Timer index */ - rxq->timeridx = index_of_array(qdma_dev->g_c2h_timer_cnt, - QDMA_NUM_C2H_TIMERS, - qdma_dev->q_info[rx_queue_id].timer_count); - if (rxq->timeridx < 0) { - PMD_DRV_LOG(WARNING, "Expected timer %d not found, " - "using the value %d at index 1\n", - qdma_dev->q_info[rx_queue_id].timer_count, - qdma_dev->g_c2h_timer_cnt[1]); - rxq->timeridx = 1; - } - - rxq->rx_buff_size = (uint16_t) - (rte_pktmbuf_data_room_size(rxq->mb_pool) - - RTE_PKTMBUF_HEADROOM); - /* Allocate memory for Rx descriptor ring */ - if (rxq->st_mode) { - if (!qdma_dev->dev_cap.st_en) { - PMD_DRV_LOG(ERR, "Streaming mode not enabled " - "in the hardware\n"); - err = -EINVAL; - goto rx_setup_err; - } - /* Find Buffer size index */ - rxq->buffszidx = index_of_array(qdma_dev->g_c2h_buf_sz, - QDMA_NUM_C2H_BUFFER_SIZES, - rxq->rx_buff_size); - if (rxq->buffszidx < 0) { - PMD_DRV_LOG(ERR, "Expected buffer size %d not found\n", - rxq->rx_buff_size); - err = -EINVAL; - goto rx_setup_err; - } - - if (rxq->en_bypass && - (rxq->bypass_desc_sz != 0)) - sz = (rxq->nb_rx_desc) * (rxq->bypass_desc_sz); - else - sz = (rxq->nb_rx_desc) * - sizeof(struct qdma_ul_st_c2h_desc); - - rxq->rx_mz = qdma_zone_reserve(dev, "RxHwRn", rx_queue_id, - sz, socket_id); - if (!rxq->rx_mz) { - PMD_DRV_LOG(ERR, "Unable to allocate rxq->rx_mz " - "of size %d\n", sz); - err = -ENOMEM; - goto rx_setup_err; - } - rxq->rx_ring = rxq->rx_mz->addr; - memset(rxq->rx_ring, 0, sz); - - /* Allocate memory for Rx completion(CMPT) descriptor ring */ - sz = (rxq->nb_rx_cmpt_desc) * rxq->cmpt_desc_len; - rxq->rx_cmpt_mz = qdma_zone_reserve(dev, "RxHwCmptRn", - rx_queue_id, sz, socket_id); - if (!rxq->rx_cmpt_mz) { - PMD_DRV_LOG(ERR, "Unable to allocate rxq->rx_cmpt_mz " - "of size %d\n", sz); - err = -ENOMEM; - goto rx_setup_err; - } - rxq->cmpt_ring = - (union qdma_ul_st_cmpt_ring *)rxq->rx_cmpt_mz->addr; - - /* Write-back status structure */ - rxq->wb_status = (struct wb_status *)((uint64_t)rxq->cmpt_ring + - (((uint64_t)rxq->nb_rx_cmpt_desc - 1) * - rxq->cmpt_desc_len)); - memset(rxq->cmpt_ring, 0, sz); - } else { - if (!qdma_dev->dev_cap.mm_en) { - PMD_DRV_LOG(ERR, "Memory mapped mode not enabled " - "in the hardware\n"); - err = -EINVAL; - goto rx_setup_err; - } - - if (rxq->en_bypass && - (rxq->bypass_desc_sz != 0)) - sz = (rxq->nb_rx_desc) * (rxq->bypass_desc_sz); - else - sz = (rxq->nb_rx_desc) * sizeof(struct qdma_ul_mm_desc); - rxq->rx_mz = qdma_zone_reserve(dev, "RxHwRn", - rx_queue_id, sz, socket_id); - if (!rxq->rx_mz) { - PMD_DRV_LOG(ERR, "Unable to allocate rxq->rx_mz " - "of size %d\n", sz); - err = -ENOMEM; - goto rx_setup_err; - } - rxq->rx_ring = rxq->rx_mz->addr; - rx_ring_mm = (struct qdma_ul_mm_desc *)rxq->rx_mz->addr; - memset(rxq->rx_ring, 0, sz); - - rx_ring_bypass = (uint8_t *)rxq->rx_mz->addr; - if (rxq->en_bypass && - (rxq->bypass_desc_sz != 0)) - rxq->wb_status = (struct wb_status *)& - (rx_ring_bypass[(rxq->nb_rx_desc - 1) * - (rxq->bypass_desc_sz)]); - else - rxq->wb_status = (struct wb_status *)& - (rx_ring_mm[rxq->nb_rx_desc - 1]); - } - - /* allocate memory for RX software ring */ - sz = (rxq->nb_rx_desc) * sizeof(struct rte_mbuf *); - rxq->sw_ring = rte_zmalloc_socket("RxSwRn", sz, - RTE_CACHE_LINE_SIZE, socket_id); - if (!rxq->sw_ring) { - PMD_DRV_LOG(ERR, "Unable to allocate rxq->sw_ring of size %d\n", - sz); - err = -ENOMEM; - goto rx_setup_err; - } - - qdma_rxq_default_mbuf_init(rxq); - - dev->data->rx_queues[rx_queue_id] = rxq; - -#ifdef LATENCY_MEASUREMENT - err = qdma_rx_qstats_clear(dev, rx_queue_id); - if (err) { - PMD_DRV_LOG(ERR, - "Failed to clear QDMA Rx queue stats for qid: %d\n", - rx_queue_id); - return err; - } -#endif - - return 0; - -rx_setup_err: - if (!qdma_dev->is_vf) { - qdma_dev_decrement_active_queue(qdma_dev->dma_device_index, - qdma_dev->func_id, - QDMA_DEV_Q_TYPE_C2H); - - if (qdma_dev->q_info[rx_queue_id].queue_mode == - RTE_PMD_QDMA_STREAMING_MODE) - qdma_dev_decrement_active_queue( - qdma_dev->dma_device_index, - qdma_dev->func_id, - QDMA_DEV_Q_TYPE_CMPT); - } else { - qdma_dev_notify_qdel(dev, rx_queue_id + - qdma_dev->queue_base, QDMA_DEV_Q_TYPE_C2H); - - if (qdma_dev->q_info[rx_queue_id].queue_mode == - RTE_PMD_QDMA_STREAMING_MODE) - qdma_dev_notify_qdel(dev, rx_queue_id + - qdma_dev->queue_base, QDMA_DEV_Q_TYPE_CMPT); - } - - if (rxq) { - if (rxq->rx_mz) - rte_memzone_free(rxq->rx_mz); - if (rxq->sw_ring) - rte_free(rxq->sw_ring); - rte_free(rxq); - } - return err; -} - -/** - * DPDK callback to configure a TX queue. - * - * @param dev - * Pointer to Ethernet device structure. - * @param tx_queue_id - * TX queue index. - * @param nb_tx_desc - * Number of descriptors to configure in queue. - * @param socket_id - * NUMA socket on which memory must be allocated. - * @param[in] tx_conf - * Thresholds parameters. - * - * @return - * 0 on success - * -ENOMEM when memory allocation fails - * -EINVAL on other failure. - */ -int qdma_dev_tx_queue_setup(struct rte_eth_dev *dev, uint16_t tx_queue_id, - uint16_t nb_tx_desc, unsigned int socket_id, - const struct rte_eth_txconf *tx_conf) -{ - struct qdma_pci_dev *qdma_dev = dev->data->dev_private; - struct qdma_tx_queue *txq = NULL; - struct qdma_ul_mm_desc *tx_ring_mm; - struct qdma_ul_st_h2c_desc *tx_ring_st; - uint32_t sz; - uint8_t *tx_ring_bypass; - int err = 0; - - PMD_DRV_LOG(INFO, "Configuring Tx queue id:%d with %d desc\n", - tx_queue_id, nb_tx_desc); - - if (!qdma_dev->is_vf) { - err = qdma_dev_increment_active_queue( - qdma_dev->dma_device_index, - qdma_dev->func_id, - QDMA_DEV_Q_TYPE_H2C); - if (err != QDMA_SUCCESS) - return -EINVAL; - } else { - err = qdma_dev_notify_qadd(dev, tx_queue_id + - qdma_dev->queue_base, - QDMA_DEV_Q_TYPE_H2C); - if (err < 0) - return -EINVAL; - } - if (!qdma_dev->init_q_range) { - if (qdma_dev->is_vf) { - err = qdma_vf_csr_read(dev); - if (err < 0) { - PMD_DRV_LOG(ERR, "CSR read failed\n"); - goto tx_setup_err; - } - } else { - err = qdma_pf_csr_read(dev); - if (err < 0) { - PMD_DRV_LOG(ERR, "CSR read failed\n"); - goto tx_setup_err; - } - } - qdma_dev->init_q_range = 1; - } - /* allocate rx queue data structure */ - txq = rte_zmalloc_socket("QDMA_TxQ", sizeof(struct qdma_tx_queue), - RTE_CACHE_LINE_SIZE, socket_id); - if (txq == NULL) { - PMD_DRV_LOG(ERR, "Memory allocation failed for " - "Tx queue SW structure\n"); - err = -ENOMEM; - goto tx_setup_err; - } - - txq->st_mode = qdma_dev->q_info[tx_queue_id].queue_mode; - - txq->en_bypass = (qdma_dev->q_info[tx_queue_id].tx_bypass_mode) ? 1 : 0; - txq->bypass_desc_sz = qdma_dev->q_info[tx_queue_id].tx_bypass_desc_sz; - - txq->nb_tx_desc = (nb_tx_desc + 1); - txq->queue_id = tx_queue_id; - txq->dev = dev; - txq->port_id = dev->data->port_id; - txq->func_id = qdma_dev->func_id; - txq->num_queues = dev->data->nb_tx_queues; - txq->tx_deferred_start = tx_conf->tx_deferred_start; - - txq->ringszidx = index_of_array(qdma_dev->g_ring_sz, - QDMA_NUM_RING_SIZES, txq->nb_tx_desc); - if (txq->ringszidx < 0) { - PMD_DRV_LOG(ERR, "Expected Ring size %d not found\n", - txq->nb_tx_desc); - err = -EINVAL; - goto tx_setup_err; - } - - if (qdma_dev->ip_type == EQDMA_SOFT_IP && - qdma_dev->vivado_rel >= QDMA_VIVADO_2020_2) { - if (qdma_dev->dev_cap.desc_eng_mode == - QDMA_DESC_ENG_BYPASS_ONLY) { - PMD_DRV_LOG(ERR, - "Bypass only mode design " - "is not supported\n"); - return -ENOTSUP; - } - - if (txq->en_bypass && - (qdma_dev->dev_cap.desc_eng_mode == - QDMA_DESC_ENG_INTERNAL_ONLY)) { - PMD_DRV_LOG(ERR, - "Tx qid %d config in bypass " - "mode not supported on " - "internal only mode design\n", - tx_queue_id); - return -ENOTSUP; - } - } - - /* Allocate memory for TX descriptor ring */ - if (txq->st_mode) { - if (!qdma_dev->dev_cap.st_en) { - PMD_DRV_LOG(ERR, "Streaming mode not enabled " - "in the hardware\n"); - err = -EINVAL; - goto tx_setup_err; - } - - if (txq->en_bypass && - (txq->bypass_desc_sz != 0)) - sz = (txq->nb_tx_desc) * (txq->bypass_desc_sz); - else - sz = (txq->nb_tx_desc) * - sizeof(struct qdma_ul_st_h2c_desc); - txq->tx_mz = qdma_zone_reserve(dev, "TxHwRn", tx_queue_id, sz, - socket_id); - if (!txq->tx_mz) { - PMD_DRV_LOG(ERR, "Couldn't reserve memory for " - "ST H2C ring of size %d\n", sz); - err = -ENOMEM; - goto tx_setup_err; - } - - txq->tx_ring = txq->tx_mz->addr; - tx_ring_st = (struct qdma_ul_st_h2c_desc *)txq->tx_ring; - - tx_ring_bypass = (uint8_t *)txq->tx_ring; - /* Write-back status structure */ - if (txq->en_bypass && - (txq->bypass_desc_sz != 0)) - txq->wb_status = (struct wb_status *)& - tx_ring_bypass[(txq->nb_tx_desc - 1) * - (txq->bypass_desc_sz)]; - else - txq->wb_status = (struct wb_status *)& - tx_ring_st[txq->nb_tx_desc - 1]; - } else { - if (!qdma_dev->dev_cap.mm_en) { - PMD_DRV_LOG(ERR, "Memory mapped mode not " - "enabled in the hardware\n"); - err = -EINVAL; - goto tx_setup_err; - } - - if (txq->en_bypass && - (txq->bypass_desc_sz != 0)) - sz = (txq->nb_tx_desc) * (txq->bypass_desc_sz); - else - sz = (txq->nb_tx_desc) * sizeof(struct qdma_ul_mm_desc); - txq->tx_mz = qdma_zone_reserve(dev, "TxHwRn", tx_queue_id, - sz, socket_id); - if (!txq->tx_mz) { - PMD_DRV_LOG(ERR, "Couldn't reserve memory for " - "MM H2C ring of size %d\n", sz); - err = -ENOMEM; - goto tx_setup_err; - } - - txq->tx_ring = txq->tx_mz->addr; - tx_ring_mm = (struct qdma_ul_mm_desc *)txq->tx_ring; - - /* Write-back status structure */ - - tx_ring_bypass = (uint8_t *)txq->tx_ring; - if (txq->en_bypass && - (txq->bypass_desc_sz != 0)) - txq->wb_status = (struct wb_status *)& - tx_ring_bypass[(txq->nb_tx_desc - 1) * - (txq->bypass_desc_sz)]; - else - txq->wb_status = (struct wb_status *)& - tx_ring_mm[txq->nb_tx_desc - 1]; - } - - PMD_DRV_LOG(INFO, "Tx ring phys addr: 0x%lX, Tx Ring virt addr: 0x%lX", - (uint64_t)txq->tx_mz->iova, (uint64_t)txq->tx_ring); - - /* Allocate memory for TX software ring */ - sz = txq->nb_tx_desc * sizeof(struct rte_mbuf *); - txq->sw_ring = rte_zmalloc_socket("TxSwRn", sz, - RTE_CACHE_LINE_SIZE, socket_id); - if (txq->sw_ring == NULL) { - PMD_DRV_LOG(ERR, "Memory allocation failed for " - "Tx queue SW ring\n"); - err = -ENOMEM; - goto tx_setup_err; - } - - rte_spinlock_init(&txq->pidx_update_lock); - dev->data->tx_queues[tx_queue_id] = txq; - -#ifdef LATENCY_MEASUREMENT - err = qdma_tx_qstats_clear(dev, tx_queue_id); - if (err) { - PMD_DRV_LOG(ERR, - "Failed to clear QDMA Tx queue stats for qid: %d\n", - tx_queue_id); - return err; - } -#endif - - return 0; - -tx_setup_err: - PMD_DRV_LOG(ERR, " Tx queue setup failed"); - if (!qdma_dev->is_vf) - qdma_dev_decrement_active_queue(qdma_dev->dma_device_index, - qdma_dev->func_id, - QDMA_DEV_Q_TYPE_H2C); - else - qdma_dev_notify_qdel(dev, tx_queue_id + - qdma_dev->queue_base, QDMA_DEV_Q_TYPE_H2C); - if (txq) { - if (txq->tx_mz) - rte_memzone_free(txq->tx_mz); - if (txq->sw_ring) - rte_free(txq->sw_ring); - rte_free(txq); - } - return err; -} - -#if (MIN_TX_PIDX_UPDATE_THRESHOLD > 1) -void qdma_txq_pidx_update(void *arg) -{ - struct rte_eth_dev *dev = (struct rte_eth_dev *)arg; - struct qdma_pci_dev *qdma_dev = dev->data->dev_private; - struct qdma_tx_queue *txq; - uint32_t qid; - - for (qid = 0; qid < dev->data->nb_tx_queues; qid++) { - txq = (struct qdma_tx_queue *)dev->data->tx_queues[qid]; - if (txq->tx_desc_pend) { - rte_spinlock_lock(&txq->pidx_update_lock); - if (txq->tx_desc_pend) { - qdma_dev->hw_access->qdma_queue_pidx_update(dev, - qdma_dev->is_vf, - qid, 0, &txq->q_pidx_info); - - txq->tx_desc_pend = 0; - } - rte_spinlock_unlock(&txq->pidx_update_lock); - } - } - rte_eal_alarm_set(QDMA_TXQ_PIDX_UPDATE_INTERVAL, - qdma_txq_pidx_update, (void *)arg); -} -#endif - -/** - * DPDK callback to start the device. - * - * Start the device by configuring the Rx/Tx descriptor and device registers. - * - * @param dev - * Pointer to Ethernet device structure. - * - * @return - * 0 on success, negative errno value on failure. - */ -int qdma_dev_start(struct rte_eth_dev *dev) -{ - struct qdma_tx_queue *txq; - struct qdma_rx_queue *rxq; - uint32_t qid; - int err; - - PMD_DRV_LOG(INFO, "qdma-dev-start: Starting\n"); - - /* prepare descriptor rings for operation */ - for (qid = 0; qid < dev->data->nb_tx_queues; qid++) { - txq = (struct qdma_tx_queue *)dev->data->tx_queues[qid]; - - /*Deferred Queues should not start with dev_start*/ - if (!txq->tx_deferred_start) { - err = qdma_dev_tx_queue_start(dev, qid); - if (err != 0) - return err; - } - } - - for (qid = 0; qid < dev->data->nb_rx_queues; qid++) { - rxq = (struct qdma_rx_queue *)dev->data->rx_queues[qid]; - - /*Deferred Queues should not start with dev_start*/ - if (!rxq->rx_deferred_start) { - err = qdma_dev_rx_queue_start(dev, qid); - if (err != 0) - return err; - } - } - -#if (MIN_TX_PIDX_UPDATE_THRESHOLD > 1) - rte_eal_alarm_set(QDMA_TXQ_PIDX_UPDATE_INTERVAL, - qdma_txq_pidx_update, (void *)dev); -#endif - return 0; -} - -/** - * DPDK callback to retrieve the physical link information. - * - * @param dev - * Pointer to Ethernet device structure. - * @param wait_to_complete - * wait_to_complete field is ignored. - */ -int qdma_dev_link_update(struct rte_eth_dev *dev, - __rte_unused int wait_to_complete) -{ - dev->data->dev_link.link_status = ETH_LINK_UP; - dev->data->dev_link.link_duplex = ETH_LINK_FULL_DUPLEX; - - /* TODO: Configure link speed by reading hardware capabilities */ - dev->data->dev_link.link_speed = ETH_SPEED_NUM_200G; - - PMD_DRV_LOG(INFO, "Link update done\n"); - return 0; -} - -/** - * DPDK callback to get information about the device. - * - * @param dev - * Pointer to Ethernet device structure. - * @param[out] dev_info - * Device information structure output buffer. - */ -int qdma_dev_infos_get(struct rte_eth_dev *dev, - struct rte_eth_dev_info *dev_info) -{ - struct qdma_pci_dev *qdma_dev = dev->data->dev_private; - - dev_info->max_rx_queues = qdma_dev->dev_cap.num_qs; - dev_info->max_tx_queues = qdma_dev->dev_cap.num_qs; - - dev_info->min_rx_bufsize = QDMA_MIN_RXBUFF_SIZE; - dev_info->max_rx_pktlen = DMA_BRAM_SIZE; - dev_info->max_mac_addrs = 1; - - return 0; -} - -/** - * DPDK callback to stop the device. - * - * Stop the device by clearing all configured Rx/Tx queue - * descriptors and registers. - * - * @param dev - * Pointer to Ethernet device structure. - */ -int qdma_dev_stop(struct rte_eth_dev *dev) -{ -#ifdef RTE_LIBRTE_QDMA_DEBUG_DRIVER - struct qdma_pci_dev *qdma_dev = dev->data->dev_private; -#endif - uint32_t qid; - - /* reset driver's internal queue structures to default values */ - PMD_DRV_LOG(INFO, "PF-%d(DEVFN) Stop H2C & C2H queues", - qdma_dev->func_id); - for (qid = 0; qid < dev->data->nb_tx_queues; qid++) - qdma_dev_tx_queue_stop(dev, qid); - for (qid = 0; qid < dev->data->nb_rx_queues; qid++) - qdma_dev_rx_queue_stop(dev, qid); - -#if (MIN_TX_PIDX_UPDATE_THRESHOLD > 1) - /* Cancel pending PIDX updates */ - rte_eal_alarm_cancel(qdma_txq_pidx_update, (void *)dev); -#endif - - return 0; -} - -/** - * DPDK callback to close the device. - * - * Destroy all queues and objects, free memory. - * - * @param dev - * Pointer to Ethernet device structure. - */ -int qdma_dev_close(struct rte_eth_dev *dev) -{ - struct qdma_pci_dev *qdma_dev = dev->data->dev_private; - struct qdma_tx_queue *txq; - struct qdma_rx_queue *rxq; - struct qdma_cmpt_queue *cmptq; - uint32_t qid; - struct qdma_fmap_cfg fmap_cfg; - int ret = 0; - - PMD_DRV_LOG(INFO, "PF-%d(DEVFN) DEV Close\n", qdma_dev->func_id); - - if (dev->data->dev_started) - qdma_dev_stop(dev); - - memset(&fmap_cfg, 0, sizeof(struct qdma_fmap_cfg)); - qdma_dev->hw_access->qdma_fmap_conf(dev, - qdma_dev->func_id, &fmap_cfg, QDMA_HW_ACCESS_CLEAR); - - /* iterate over rx queues */ - for (qid = 0; qid < dev->data->nb_rx_queues; ++qid) { - rxq = dev->data->rx_queues[qid]; - if (rxq) { - PMD_DRV_LOG(INFO, "Remove C2H queue: %d", qid); - - if (rxq->sw_ring) - rte_free(rxq->sw_ring); - if (rxq->st_mode) { /** if ST-mode **/ - if (rxq->rx_cmpt_mz) - rte_memzone_free(rxq->rx_cmpt_mz); - } - - qdma_dev_decrement_active_queue( - qdma_dev->dma_device_index, - qdma_dev->func_id, - QDMA_DEV_Q_TYPE_C2H); - - if (rxq->st_mode) - qdma_dev_decrement_active_queue( - qdma_dev->dma_device_index, - qdma_dev->func_id, - QDMA_DEV_Q_TYPE_CMPT); - - if (rxq->rx_mz) - rte_memzone_free(rxq->rx_mz); - rte_free(rxq); - PMD_DRV_LOG(INFO, "C2H queue %d removed", qid); - } - } - - /* iterate over tx queues */ - for (qid = 0; qid < dev->data->nb_tx_queues; ++qid) { - txq = dev->data->tx_queues[qid]; - if (txq) { - PMD_DRV_LOG(INFO, "Remove H2C queue: %d", qid); - - if (txq->sw_ring) - rte_free(txq->sw_ring); - if (txq->tx_mz) - rte_memzone_free(txq->tx_mz); - rte_free(txq); - PMD_DRV_LOG(INFO, "H2C queue %d removed", qid); - - qdma_dev_decrement_active_queue( - qdma_dev->dma_device_index, - qdma_dev->func_id, - QDMA_DEV_Q_TYPE_H2C); - } - } - if (qdma_dev->dev_cap.mm_cmpt_en) { - /* iterate over cmpt queues */ - for (qid = 0; qid < qdma_dev->qsets_en; ++qid) { - cmptq = qdma_dev->cmpt_queues[qid]; - if (cmptq != NULL) { - PMD_DRV_LOG(INFO, "PF-%d(DEVFN) Remove CMPT queue: %d", - qdma_dev->func_id, qid); - if (cmptq->cmpt_mz) - rte_memzone_free(cmptq->cmpt_mz); - rte_free(cmptq); - PMD_DRV_LOG(INFO, "PF-%d(DEVFN) CMPT queue %d removed", - qdma_dev->func_id, qid); - qdma_dev_decrement_active_queue( - qdma_dev->dma_device_index, - qdma_dev->func_id, - QDMA_DEV_Q_TYPE_CMPT); - } - } - - if (qdma_dev->cmpt_queues != NULL) { - rte_free(qdma_dev->cmpt_queues); - qdma_dev->cmpt_queues = NULL; - } - } - qdma_dev->qsets_en = 0; - ret = qdma_dev_update(qdma_dev->dma_device_index, qdma_dev->func_id, - qdma_dev->qsets_en, (int *)&qdma_dev->queue_base); - if (ret != QDMA_SUCCESS) { - PMD_DRV_LOG(ERR, "PF-%d(DEVFN) qmax update failed: %d\n", - qdma_dev->func_id, ret); - return 0; - } - - qdma_dev->init_q_range = 0; - rte_free(qdma_dev->q_info); - qdma_dev->q_info = NULL; - qdma_dev->dev_configured = 0; - - /* cancel pending polls*/ - if (qdma_dev->is_master) - rte_eal_alarm_cancel(qdma_check_errors, (void *)dev); - - return 0; -} - -/** - * DPDK callback to reset the device. - * - * Uninitialze PF device after waiting for all its VFs to shutdown. - * Initialize back PF device and then send Reset done mailbox - * message to all its VFs to come online again. - * - * @param dev - * Pointer to Ethernet device structure. - * - * @return - * 0 on success, negative errno value on failure. - */ -int qdma_dev_reset(struct rte_eth_dev *dev) -{ - struct qdma_pci_dev *qdma_dev = dev->data->dev_private; - struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); - struct qdma_mbox_msg *m = NULL; - uint32_t vf_device_count = 0; - uint32_t i = 0; - int ret = 0; - - /* Get the number of active VFs for this PF device */ - vf_device_count = qdma_dev->vf_online_count; - qdma_dev->reset_in_progress = 1; - - /* Uninitialze PCI device */ - ret = qdma_eth_dev_uninit(dev); - if (ret != QDMA_SUCCESS) { - PMD_DRV_LOG(ERR, "PF-%d(DEVFN) uninitialization failed: %d\n", - qdma_dev->func_id, ret); - return -1; - } - - /* Initialize PCI device */ - ret = qdma_eth_dev_init(dev); - if (ret != QDMA_SUCCESS) { - PMD_DRV_LOG(ERR, "PF-%d(DEVFN) initialization failed: %d\n", - qdma_dev->func_id, ret); - return -1; - } - - /* Send "PF_RESET_DONE" mailbox message from PF to all its VFs, - * so that VFs can come online again - */ - for (i = 0; i < pci_dev->max_vfs; i++) { - if (qdma_dev->vfinfo[i].func_id == QDMA_FUNC_ID_INVALID) - continue; - - m = qdma_mbox_msg_alloc(); - if (!m) - return -ENOMEM; - - qdma_mbox_compose_pf_reset_done_message(m->raw_data, - qdma_dev->func_id, - qdma_dev->vfinfo[i].func_id); - ret = qdma_mbox_msg_send(dev, m, 0); - if (ret < 0) - PMD_DRV_LOG(ERR, "Sending reset failed from PF:%d to VF:%d\n", - qdma_dev->func_id, - qdma_dev->vfinfo[i].func_id); - - /* Mark VFs with invalid function id mapping, - * and this gets updated when VF comes online again - */ - qdma_dev->vfinfo[i].func_id = QDMA_FUNC_ID_INVALID; - } - - /* Start waiting for a maximum of 60 secs to get all its VFs - * to come online that were active before PF reset - */ - i = 0; - while (i < RESET_TIMEOUT) { - if (qdma_dev->vf_online_count == vf_device_count) { - PMD_DRV_LOG(INFO, - "%s: Reset completed for PF-%d(DEVFN)\n", - __func__, qdma_dev->func_id); - break; - } - rte_delay_ms(1); - i++; - } - - if (i >= RESET_TIMEOUT) { - PMD_DRV_LOG(ERR, "%s: Failed reset for PF-%d(DEVFN)\n", - __func__, qdma_dev->func_id); - } - - return ret; -} - -/** - * DPDK callback for Ethernet device configuration. - * - * @param dev - * Pointer to Ethernet device structure. - * - * @return - * 0 on success, negative errno value on failure. - */ -int qdma_dev_configure(struct rte_eth_dev *dev) -{ - struct qdma_pci_dev *qdma_dev = dev->data->dev_private; - uint16_t qid = 0; - int ret = 0, queue_base = -1; - uint8_t stat_id; - - PMD_DRV_LOG(INFO, "Configure the qdma engines\n"); - - qdma_dev->qsets_en = RTE_MAX(dev->data->nb_rx_queues, - dev->data->nb_tx_queues); - if (qdma_dev->qsets_en > qdma_dev->dev_cap.num_qs) { - PMD_DRV_LOG(ERR, "PF-%d(DEVFN) Error: Number of Queues to be" - " configured are greater than the queues" - " supported by the hardware\n", - qdma_dev->func_id); - qdma_dev->qsets_en = 0; - return -1; - } - - /* Request queue base from the resource manager */ - ret = qdma_dev_update(qdma_dev->dma_device_index, qdma_dev->func_id, - qdma_dev->qsets_en, &queue_base); - if (ret != QDMA_SUCCESS) { - PMD_DRV_LOG(ERR, "PF-%d(DEVFN) queue allocation failed: %d\n", - qdma_dev->func_id, ret); - return -1; - } - - ret = qdma_dev_qinfo_get(qdma_dev->dma_device_index, qdma_dev->func_id, - (int *)&qdma_dev->queue_base, - &qdma_dev->qsets_en); - if (ret != QDMA_SUCCESS) { - PMD_DRV_LOG(ERR, "%s: Error %d querying qbase\n", - __func__, ret); - return -1; - } - PMD_DRV_LOG(INFO, "Bus: 0x%x, PF-%d(DEVFN) queue_base: %d\n", - qdma_dev->dma_device_index, - qdma_dev->func_id, - qdma_dev->queue_base); - - qdma_dev->q_info = rte_zmalloc("qinfo", sizeof(struct queue_info) * - (qdma_dev->qsets_en), 0); - if (!qdma_dev->q_info) { - PMD_DRV_LOG(ERR, "PF-%d(DEVFN) Cannot allocate " - "memory for queue info\n", qdma_dev->func_id); - return (-ENOMEM); - } - - /* Reserve memory for cmptq ring pointers - * Max completion queues can be maximum of rx and tx queues. - */ - qdma_dev->cmpt_queues = rte_zmalloc("cmpt_queues", - sizeof(qdma_dev->cmpt_queues[0]) * - qdma_dev->qsets_en, - RTE_CACHE_LINE_SIZE); - if (qdma_dev->cmpt_queues == NULL) { - PMD_DRV_LOG(ERR, "PF-%d(DEVFN) cmpt ring pointers memory " - "allocation failed:\n", qdma_dev->func_id); - rte_free(qdma_dev->q_info); - qdma_dev->q_info = NULL; - return -(ENOMEM); - } - - for (qid = 0 ; qid < qdma_dev->qsets_en; qid++) { - /* Initialize queue_modes to all 1's ( i.e. Streaming) */ - qdma_dev->q_info[qid].queue_mode = RTE_PMD_QDMA_STREAMING_MODE; - - /* Disable the cmpt over flow check by default */ - qdma_dev->q_info[qid].dis_cmpt_ovf_chk = 0; - - qdma_dev->q_info[qid].trigger_mode = qdma_dev->trigger_mode; - qdma_dev->q_info[qid].timer_count = - qdma_dev->timer_count; - } - - for (qid = 0 ; qid < dev->data->nb_rx_queues; qid++) { - qdma_dev->q_info[qid].cmpt_desc_sz = qdma_dev->cmpt_desc_len; - qdma_dev->q_info[qid].rx_bypass_mode = - qdma_dev->c2h_bypass_mode; - qdma_dev->q_info[qid].en_prefetch = qdma_dev->en_desc_prefetch; - qdma_dev->q_info[qid].immediate_data_state = 0; - } - - for (qid = 0 ; qid < dev->data->nb_tx_queues; qid++) - qdma_dev->q_info[qid].tx_bypass_mode = - qdma_dev->h2c_bypass_mode; - for (stat_id = 0, qid = 0; - stat_id < RTE_ETHDEV_QUEUE_STAT_CNTRS; - stat_id++, qid++) { - /* Initialize map with qid same as stat_id */ - qdma_dev->tx_qid_statid_map[stat_id] = - (qid < dev->data->nb_tx_queues) ? qid : -1; - qdma_dev->rx_qid_statid_map[stat_id] = - (qid < dev->data->nb_rx_queues) ? qid : -1; - } - - ret = qdma_pf_fmap_prog(dev); - if (ret < 0) { - PMD_DRV_LOG(ERR, "FMAP programming failed\n"); - rte_free(qdma_dev->q_info); - qdma_dev->q_info = NULL; - rte_free(qdma_dev->cmpt_queues); - qdma_dev->cmpt_queues = NULL; - return ret; - } - - qdma_dev->dev_configured = 1; - - return 0; -} - -int qdma_dev_tx_queue_start(struct rte_eth_dev *dev, uint16_t qid) -{ - struct qdma_pci_dev *qdma_dev = dev->data->dev_private; - struct qdma_tx_queue *txq; - uint32_t queue_base = qdma_dev->queue_base; - int err, bypass_desc_sz_idx; - struct qdma_descq_sw_ctxt q_sw_ctxt; - struct qdma_hw_access *hw_access = qdma_dev->hw_access; - - txq = (struct qdma_tx_queue *)dev->data->tx_queues[qid]; - - memset(&q_sw_ctxt, 0, sizeof(struct qdma_descq_sw_ctxt)); - - bypass_desc_sz_idx = qmda_get_desc_sz_idx(txq->bypass_desc_sz); - - qdma_reset_tx_queue(txq); - qdma_clr_tx_queue_ctxts(dev, (qid + queue_base), txq->st_mode); - - if (txq->st_mode) { - q_sw_ctxt.desc_sz = SW_DESC_CNTXT_H2C_STREAM_DMA; - } else { - q_sw_ctxt.desc_sz = SW_DESC_CNTXT_MEMORY_MAP_DMA; - q_sw_ctxt.is_mm = 1; - } - q_sw_ctxt.wbi_chk = 1; - q_sw_ctxt.wbi_intvl_en = 1; - q_sw_ctxt.fnc_id = txq->func_id; - q_sw_ctxt.qen = 1; - q_sw_ctxt.rngsz_idx = txq->ringszidx; - q_sw_ctxt.bypass = txq->en_bypass; - q_sw_ctxt.wbk_en = 1; - q_sw_ctxt.ring_bs_addr = (uint64_t)txq->tx_mz->iova; - - if (txq->en_bypass && - (txq->bypass_desc_sz != 0)) - q_sw_ctxt.desc_sz = bypass_desc_sz_idx; - - /* Set SW Context */ - err = hw_access->qdma_sw_ctx_conf(dev, 0, - (qid + queue_base), &q_sw_ctxt, - QDMA_HW_ACCESS_WRITE); - if (err < 0) - return qdma_dev->hw_access->qdma_get_error_code(err); - - txq->q_pidx_info.pidx = 0; - hw_access->qdma_queue_pidx_update(dev, qdma_dev->is_vf, - qid, 0, &txq->q_pidx_info); - - dev->data->tx_queue_state[qid] = RTE_ETH_QUEUE_STATE_STARTED; - txq->status = RTE_ETH_QUEUE_STATE_STARTED; - return 0; -} - - -int qdma_dev_rx_queue_start(struct rte_eth_dev *dev, uint16_t qid) -{ - struct qdma_pci_dev *qdma_dev = dev->data->dev_private; - struct qdma_rx_queue *rxq; - uint32_t queue_base = qdma_dev->queue_base; - uint8_t cmpt_desc_fmt; - int err, bypass_desc_sz_idx; - struct qdma_descq_sw_ctxt q_sw_ctxt; - struct qdma_descq_cmpt_ctxt q_cmpt_ctxt; - struct qdma_descq_prefetch_ctxt q_prefetch_ctxt; - struct qdma_hw_access *hw_access = qdma_dev->hw_access; - - rxq = (struct qdma_rx_queue *)dev->data->rx_queues[qid]; - - memset(&q_sw_ctxt, 0, sizeof(struct qdma_descq_sw_ctxt)); - - qdma_reset_rx_queue(rxq); - qdma_clr_rx_queue_ctxts(dev, (qid + queue_base), rxq->st_mode); - - bypass_desc_sz_idx = qmda_get_desc_sz_idx(rxq->bypass_desc_sz); - - switch (rxq->cmpt_desc_len) { - case RTE_PMD_QDMA_CMPT_DESC_LEN_8B: - cmpt_desc_fmt = CMPT_CNTXT_DESC_SIZE_8B; - break; - case RTE_PMD_QDMA_CMPT_DESC_LEN_16B: - cmpt_desc_fmt = CMPT_CNTXT_DESC_SIZE_16B; - break; - case RTE_PMD_QDMA_CMPT_DESC_LEN_32B: - cmpt_desc_fmt = CMPT_CNTXT_DESC_SIZE_32B; - break; - case RTE_PMD_QDMA_CMPT_DESC_LEN_64B: - cmpt_desc_fmt = CMPT_CNTXT_DESC_SIZE_64B; - break; - default: - cmpt_desc_fmt = CMPT_CNTXT_DESC_SIZE_8B; - break; - } - - err = qdma_init_rx_queue(rxq); - if (err != 0) - return err; - - if (rxq->st_mode) { - memset(&q_cmpt_ctxt, 0, sizeof(struct qdma_descq_cmpt_ctxt)); - memset(&q_prefetch_ctxt, 0, - sizeof(struct qdma_descq_prefetch_ctxt)); - - q_prefetch_ctxt.bypass = (rxq->en_bypass_prefetch) ? 1 : 0; - q_prefetch_ctxt.bufsz_idx = rxq->buffszidx; - q_prefetch_ctxt.pfch_en = (rxq->en_prefetch) ? 1 : 0; - q_prefetch_ctxt.valid = 1; - -#ifdef QDMA_LATENCY_OPTIMIZED - q_cmpt_ctxt.full_upd = 1; -#endif //QDMA_LATENCY_OPTIMIZED - q_cmpt_ctxt.en_stat_desc = 1; - q_cmpt_ctxt.trig_mode = rxq->triggermode; - q_cmpt_ctxt.fnc_id = rxq->func_id; - q_cmpt_ctxt.counter_idx = rxq->threshidx; - q_cmpt_ctxt.timer_idx = rxq->timeridx; - q_cmpt_ctxt.color = CMPT_DEFAULT_COLOR_BIT; - q_cmpt_ctxt.ringsz_idx = rxq->cmpt_ringszidx; - q_cmpt_ctxt.bs_addr = (uint64_t)rxq->rx_cmpt_mz->iova; - q_cmpt_ctxt.desc_sz = cmpt_desc_fmt; - q_cmpt_ctxt.valid = 1; - if (qdma_dev->dev_cap.cmpt_ovf_chk_dis) - q_cmpt_ctxt.ovf_chk_dis = rxq->dis_overflow_check; - - - q_sw_ctxt.desc_sz = SW_DESC_CNTXT_C2H_STREAM_DMA; - q_sw_ctxt.frcd_en = 1; - } else { - q_sw_ctxt.desc_sz = SW_DESC_CNTXT_MEMORY_MAP_DMA; - q_sw_ctxt.is_mm = 1; - q_sw_ctxt.wbi_chk = 1; - q_sw_ctxt.wbi_intvl_en = 1; - } - - q_sw_ctxt.fnc_id = rxq->func_id; - q_sw_ctxt.qen = 1; - q_sw_ctxt.rngsz_idx = rxq->ringszidx; - q_sw_ctxt.bypass = rxq->en_bypass; - q_sw_ctxt.wbk_en = 1; - q_sw_ctxt.ring_bs_addr = (uint64_t)rxq->rx_mz->iova; - - if (rxq->en_bypass && - (rxq->bypass_desc_sz != 0)) - q_sw_ctxt.desc_sz = bypass_desc_sz_idx; - - /* Set SW Context */ - err = hw_access->qdma_sw_ctx_conf(dev, 1, (qid + queue_base), - &q_sw_ctxt, QDMA_HW_ACCESS_WRITE); - if (err < 0) - return qdma_dev->hw_access->qdma_get_error_code(err); - - if (rxq->st_mode) { - /* Set Prefetch Context */ - err = hw_access->qdma_pfetch_ctx_conf(dev, (qid + queue_base), - &q_prefetch_ctxt, QDMA_HW_ACCESS_WRITE); - if (err < 0) - return qdma_dev->hw_access->qdma_get_error_code(err); - - /* Set Completion Context */ - err = hw_access->qdma_cmpt_ctx_conf(dev, (qid + queue_base), - &q_cmpt_ctxt, QDMA_HW_ACCESS_WRITE); - if (err < 0) - return qdma_dev->hw_access->qdma_get_error_code(err); - - rte_wmb(); - /* enable status desc , loading the triggermode, - * thresidx and timeridx passed from the user - */ - - rxq->cmpt_cidx_info.counter_idx = rxq->threshidx; - rxq->cmpt_cidx_info.timer_idx = rxq->timeridx; - rxq->cmpt_cidx_info.trig_mode = rxq->triggermode; - rxq->cmpt_cidx_info.wrb_en = 1; - rxq->cmpt_cidx_info.wrb_cidx = 0; - hw_access->qdma_queue_cmpt_cidx_update(dev, qdma_dev->is_vf, - qid, &rxq->cmpt_cidx_info); - - rxq->q_pidx_info.pidx = (rxq->nb_rx_desc - 2); - hw_access->qdma_queue_pidx_update(dev, qdma_dev->is_vf, qid, - 1, &rxq->q_pidx_info); - } - - dev->data->rx_queue_state[qid] = RTE_ETH_QUEUE_STATE_STARTED; - rxq->status = RTE_ETH_QUEUE_STATE_STARTED; - return 0; -} - -int qdma_dev_rx_queue_stop(struct rte_eth_dev *dev, uint16_t qid) -{ - struct qdma_pci_dev *qdma_dev = dev->data->dev_private; - struct qdma_rx_queue *rxq; - uint32_t queue_base = qdma_dev->queue_base; - int i = 0; - int cnt = 0; - - rxq = (struct qdma_rx_queue *)dev->data->rx_queues[qid]; - - rxq->status = RTE_ETH_QUEUE_STATE_STOPPED; - - /* Wait for queue to recv all packets. */ - if (rxq->st_mode) { /** ST-mode **/ - /* For eqdma, c2h marker takes care to drain the pipeline */ - if (!(qdma_dev->ip_type == EQDMA_SOFT_IP)) { - while (rxq->wb_status->pidx != - rxq->cmpt_cidx_info.wrb_cidx) { - rte_delay_us_block(10); - if (cnt++ > 10000) - break; - } - } - } else { /* MM mode */ - while (rxq->wb_status->cidx != rxq->q_pidx_info.pidx) { - rte_delay_us_block(10); - if (cnt++ > 10000) - break; - } - } - - qdma_inv_rx_queue_ctxts(dev, (qid + queue_base), rxq->st_mode); - - if (rxq->st_mode) { /** ST-mode **/ -#ifdef DUMP_MEMPOOL_USAGE_STATS - PMD_DRV_LOG(INFO, "%s(): %d: queue id %d," - "mbuf_avail_count = %d, mbuf_in_use_count = %d", - __func__, __LINE__, rxq->queue_id, - rte_mempool_avail_count(rxq->mb_pool), - rte_mempool_in_use_count(rxq->mb_pool)); -#endif //DUMP_MEMPOOL_USAGE_STATS - for (i = 0; i < rxq->nb_rx_desc - 1; i++) { - rte_pktmbuf_free(rxq->sw_ring[i]); - rxq->sw_ring[i] = NULL; - } -#ifdef DUMP_MEMPOOL_USAGE_STATS - PMD_DRV_LOG(INFO, "%s(): %d: queue id %d," - "mbuf_avail_count = %d, mbuf_in_use_count = %d", - __func__, __LINE__, rxq->queue_id, - rte_mempool_avail_count(rxq->mb_pool), - rte_mempool_in_use_count(rxq->mb_pool)); -#endif //DUMP_MEMPOOL_USAGE_STATS - } - - qdma_reset_rx_queue(rxq); - - dev->data->rx_queue_state[qid] = RTE_ETH_QUEUE_STATE_STOPPED; - - return 0; -} - -int qdma_dev_tx_queue_stop(struct rte_eth_dev *dev, uint16_t qid) -{ - struct qdma_pci_dev *qdma_dev = dev->data->dev_private; - uint32_t queue_base = qdma_dev->queue_base; - struct qdma_tx_queue *txq; - int cnt = 0; - uint16_t count; - - txq = (struct qdma_tx_queue *)dev->data->tx_queues[qid]; - - txq->status = RTE_ETH_QUEUE_STATE_STOPPED; - /* Wait for TXQ to send out all packets. */ - while (txq->wb_status->cidx != txq->q_pidx_info.pidx) { - rte_delay_us_block(10); - if (cnt++ > 10000) - break; - } - - qdma_inv_tx_queue_ctxts(dev, (qid + queue_base), txq->st_mode); - - /* Relinquish pending mbufs */ - for (count = 0; count < txq->nb_tx_desc - 1; count++) { - rte_pktmbuf_free(txq->sw_ring[count]); - txq->sw_ring[count] = NULL; - } - qdma_reset_tx_queue(txq); - - dev->data->tx_queue_state[qid] = RTE_ETH_QUEUE_STATE_STOPPED; - - return 0; -} - -/** - * DPDK callback to retrieve device registers and - * register attributes (number of registers and register size) - * - * @param dev - * Pointer to Ethernet device structure. - * @param regs - * Pointer to rte_dev_reg_info structure to fill in. If regs->data is - * NULL the function fills in the width and length fields. If non-NULL - * the registers are put into the buffer pointed at by the data field. - * - * @return - * 0 on success, -ENOTSUP on failure. - */ -int -qdma_dev_get_regs(struct rte_eth_dev *dev, - struct rte_dev_reg_info *regs) -{ - struct qdma_pci_dev *qdma_dev = dev->data->dev_private; - uint32_t *data = regs->data; - uint32_t reg_length = 0; - int ret = 0; - - ret = qdma_acc_get_num_config_regs(dev, - (enum qdma_ip_type)qdma_dev->ip_type, - (enum qdma_device_type)qdma_dev->device_type, - ®_length); - if (ret < 0 || reg_length == 0) { - PMD_DRV_LOG(ERR, "%s: Failed to get number of config registers\n", - __func__); - return ret; - } - - if (data == NULL) { - regs->length = reg_length - 1; - regs->width = sizeof(uint32_t); - return 0; - } - - /* Support only full register dump */ - if ((regs->length == 0) || - (regs->length == (reg_length - 1))) { - regs->version = 1; - ret = qdma_acc_get_config_regs(dev, qdma_dev->is_vf, - (enum qdma_ip_type)qdma_dev->ip_type, - (enum qdma_device_type)qdma_dev->device_type, data); - if (ret < 0) { - PMD_DRV_LOG(ERR, "%s: Failed to get config registers\n", - __func__); - } - return ret; - } - - PMD_DRV_LOG(ERR, "%s: Unsupported length (0x%x) requested\n", - __func__, regs->length); - return -ENOTSUP; -} - -/** - * DPDK callback to set a queue statistics mapping for - * a tx/rx queue of an Ethernet device. - * - * @param dev - * Pointer to Ethernet device structure. - * @param queue_id - * Index of the queue for which a queue stats mapping is required. - * @param stat_idx - * The per-queue packet statistics functionality number that - * the queue_id is to be assigned. - * @param is_rx - * Whether queue is a Rx or a Tx queue. - * - * @return - * 0 on success, -EINVAL on failure. - */ -int qdma_dev_queue_stats_mapping(struct rte_eth_dev *dev, - uint16_t queue_id, - uint8_t stat_idx, - uint8_t is_rx) -{ - struct qdma_pci_dev *qdma_dev = dev->data->dev_private; - - if (is_rx && (queue_id >= dev->data->nb_rx_queues)) { - PMD_DRV_LOG(ERR, "%s: Invalid Rx qid %d\n", - __func__, queue_id); - return -EINVAL; - } - - if (!is_rx && (queue_id >= dev->data->nb_tx_queues)) { - PMD_DRV_LOG(ERR, "%s: Invalid Tx qid %d\n", - __func__, queue_id); - return -EINVAL; - } - - if (stat_idx >= RTE_ETHDEV_QUEUE_STAT_CNTRS) { - PMD_DRV_LOG(ERR, "%s: Invalid stats index %d\n", - __func__, stat_idx); - return -EINVAL; - } - - if (is_rx) - qdma_dev->rx_qid_statid_map[stat_idx] = queue_id; - else - qdma_dev->tx_qid_statid_map[stat_idx] = queue_id; - - return 0; -} - -/** - * DPDK callback for retrieving Port statistics. - * - * @param dev - * Pointer to Ethernet device structure. - * @param eth_stats - * Pointer to structure containing statistics. - * - * @return - * Returns 0 i.e. success - */ -int qdma_dev_stats_get(struct rte_eth_dev *dev, - struct rte_eth_stats *eth_stats) -{ - uint32_t i; - int qid; - struct qdma_rx_queue *rxq; - struct qdma_tx_queue *txq; - struct qdma_pci_dev *qdma_dev = dev->data->dev_private; - - memset(eth_stats, 0, sizeof(struct rte_eth_stats)); - for (i = 0; i < dev->data->nb_rx_queues; i++) { - rxq = (struct qdma_rx_queue *)dev->data->rx_queues[i]; - eth_stats->ipackets += rxq->stats.pkts; - eth_stats->ibytes += rxq->stats.bytes; - } - - for (i = 0; i < RTE_ETHDEV_QUEUE_STAT_CNTRS; i++) { - qid = qdma_dev->rx_qid_statid_map[i]; - if (qid >= 0) { - rxq = (struct qdma_rx_queue *)dev->data->rx_queues[qid]; - eth_stats->q_ipackets[i] = rxq->stats.pkts; - eth_stats->q_ibytes[i] = rxq->stats.bytes; - } - } - - for (i = 0; i < dev->data->nb_tx_queues; i++) { - txq = (struct qdma_tx_queue *)dev->data->tx_queues[i]; - eth_stats->opackets += txq->stats.pkts; - eth_stats->obytes += txq->stats.bytes; - } - - for (i = 0; i < RTE_ETHDEV_QUEUE_STAT_CNTRS; i++) { - qid = qdma_dev->tx_qid_statid_map[i]; - if (qid >= 0) { - txq = (struct qdma_tx_queue *)dev->data->tx_queues[qid]; - eth_stats->q_opackets[i] = txq->stats.pkts; - eth_stats->q_obytes[i] = txq->stats.bytes; - } - } - return 0; -} - -/** - * DPDK callback to reset Port statistics. - * - * @param dev - * Pointer to Ethernet device structure. - * - */ -int qdma_dev_stats_reset(struct rte_eth_dev *dev) -{ - uint32_t i; - - for (i = 0; i < dev->data->nb_rx_queues; i++) { - struct qdma_rx_queue *rxq = - (struct qdma_rx_queue *)dev->data->rx_queues[i]; - rxq->stats.pkts = 0; - rxq->stats.bytes = 0; - } - - for (i = 0; i < dev->data->nb_tx_queues; i++) { - struct qdma_tx_queue *txq = - (struct qdma_tx_queue *)dev->data->tx_queues[i]; - txq->stats.pkts = 0; - txq->stats.bytes = 0; - } - return 0; -} - -/** - * DPDK callback to get Rx Queue info of an Ethernet device. - * - * @param dev - * Pointer to Ethernet device structure. - * @param rx_queue_id - * The RX queue on the Ethernet device for which information will be - * retrieved - * @param qinfo - * A pointer to a structure of type rte_eth_rxq_info_info to be filled with - * the information of given Rx queue. - */ -void -qdma_dev_rxq_info_get(struct rte_eth_dev *dev, uint16_t rx_queue_id, - struct rte_eth_rxq_info *qinfo) -{ - struct qdma_pci_dev *dma_priv; - struct qdma_rx_queue *rxq = NULL; - - if (!qinfo) - return; - - dma_priv = (struct qdma_pci_dev *)dev->data->dev_private; - - rxq = dev->data->rx_queues[rx_queue_id]; - memset(qinfo, 0, sizeof(struct rte_eth_rxq_info)); - qinfo->mp = rxq->mb_pool; - qinfo->conf.rx_deferred_start = rxq->rx_deferred_start; - qinfo->conf.rx_drop_en = 1; - qinfo->conf.rx_thresh.wthresh = dma_priv->g_c2h_cnt_th[rxq->threshidx]; - qinfo->scattered_rx = 1; - qinfo->nb_desc = rxq->nb_rx_desc - 1; -} - -/** - * DPDK callback to get Tx Queue info of an Ethernet device. - * - * @param dev - * Pointer to Ethernet device structure. - * @param tx_queue_id - * The TX queue on the Ethernet device for which information will be - * retrieved - * @param qinfo - * A pointer to a structure of type rte_eth_txq_info_info to be filled with - * the information of given Tx queue. - */ -void -qdma_dev_txq_info_get(struct rte_eth_dev *dev, uint16_t tx_queue_id, - struct rte_eth_txq_info *qinfo) -{ - struct qdma_tx_queue *txq = NULL; - - if (!qinfo) - return; - - txq = dev->data->tx_queues[tx_queue_id]; - qinfo->conf.offloads = txq->offloads; - qinfo->conf.tx_deferred_start = txq->tx_deferred_start; - qinfo->conf.tx_rs_thresh = 0; - qinfo->nb_desc = txq->nb_tx_desc - 1; - -} - -static struct eth_dev_ops qdma_eth_dev_ops = { - .dev_configure = qdma_dev_configure, - .dev_infos_get = qdma_dev_infos_get, - .dev_start = qdma_dev_start, - .dev_stop = qdma_dev_stop, - .dev_close = qdma_dev_close, - .dev_reset = qdma_dev_reset, - .link_update = qdma_dev_link_update, - .rx_queue_setup = qdma_dev_rx_queue_setup, - .tx_queue_setup = qdma_dev_tx_queue_setup, - .rx_queue_release = qdma_dev_rx_queue_release, - .tx_queue_release = qdma_dev_tx_queue_release, - .rx_queue_start = qdma_dev_rx_queue_start, - .rx_queue_stop = qdma_dev_rx_queue_stop, - .tx_queue_start = qdma_dev_tx_queue_start, - .tx_queue_stop = qdma_dev_tx_queue_stop, - .tx_done_cleanup = qdma_dev_tx_done_cleanup, - .queue_stats_mapping_set = qdma_dev_queue_stats_mapping, - .get_reg = qdma_dev_get_regs, - .stats_get = qdma_dev_stats_get, - .stats_reset = qdma_dev_stats_reset, - .rxq_info_get = qdma_dev_rxq_info_get, - .txq_info_get = qdma_dev_txq_info_get, -}; - -void qdma_dev_ops_init(struct rte_eth_dev *dev) -{ - dev->dev_ops = &qdma_eth_dev_ops; - if (rte_eal_process_type() == RTE_PROC_PRIMARY) { - qdma_set_rx_function(dev); - qdma_set_tx_function(dev); - dev->rx_queue_count = &qdma_dev_rx_queue_count; - dev->rx_descriptor_status = &qdma_dev_rx_descriptor_status; - dev->tx_descriptor_status = &qdma_dev_tx_descriptor_status; - } -} - diff --git a/QDMA/DPDK/drivers/net/qdma/qdma_devops.h b/QDMA/DPDK/drivers/net/qdma/qdma_devops.h deleted file mode 100755 index 56c0d2866..000000000 --- a/QDMA/DPDK/drivers/net/qdma/qdma_devops.h +++ /dev/null @@ -1,515 +0,0 @@ -/*- - * BSD LICENSE - * - * Copyright (c) 2020-2022 Xilinx, Inc. All rights reserved. - * Copyright (c) 2022-2023, Advanced Micro Devices, Inc. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * * Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#ifndef __QDMA_DEVOPS_H__ -#define __QDMA_DEVOPS_H__ - -#ifdef __cplusplus -extern "C" { -#endif - -/** @defgroup dpdk_devops_func Functions - */ - -/** - * DPDK callback to register an Ethernet PCIe device. - * - * The Following actions are performed by this function: - * - Parse and validate device arguments - * - Identify PCIe BARs present in the device - * - Register device operations - * - Enable MM C2H and H2C channels - * - Register PCIe device with Queue Resource Manager - * - Program the QDMA IP global registers (by 1st PF that was probed) - * - Enable HW errors and launch QDMA HW error monitoring thread - * (by 1st PF that was probed) - * - If VF is enabled, then enable Mailbox interrupt and register - * Rx message handling function as interrupt handler - * - * @param dev Pointer to Ethernet device structure - * - * @return 0 on success, < 0 on failure - * @ingroup dpdk_devops_func - * - */ -int qdma_eth_dev_init(struct rte_eth_dev *dev); - -/** - * DPDK callback for Ethernet device configuration. - * - * This API requests the queue base from Queue Resource Manager and programs - * the queue base and queue count in function map (FMAP) - * - * @param dev Pointer to Ethernet device structure - * - * @return 0 on success, < 0 on failure - * @ingroup dpdk_devops_func - * - */ -int qdma_dev_configure(struct rte_eth_dev *dev); - -/** - * DPDK callback to get information about the device - * - * @param dev Pointer to Ethernet device structure - * @param dev_info: Pointer to Device information structure - * - * @ingroup dpdk_devops_func - */ -int qdma_dev_infos_get(struct rte_eth_dev *dev, - struct rte_eth_dev_info *dev_info); - -/** - * DPDK callback to retrieve the physical link information - * - * @param dev - * Pointer to Ethernet device structure - * @param wait_to_complete - * wait_to_complete field is ignored - * - * @ingroup dpdk_devops_func - */ -int qdma_dev_link_update(struct rte_eth_dev *dev, - __rte_unused int wait_to_complete); - -/** - * DPDK callback to configure a RX queue. - * - * This API validates queue parameters and allocates C2H ring and - * Streaming CMPT ring from the DPDK reserved hugepage memory zones - * - * @param dev Pointer to Ethernet device structure. - * @param rx_queue_id RX queue index relative to the PCIe function - * pointed by dev - * @param nb_rx_desc Number of C2H descriptors to configure for this queue - * @param socket_id NUMA socket on which memory must be allocated - * @param rx_conf Rx queue configuration parameters - * @param mb_pool Memory pool to use for buffer allocations on this queue - * - * @return 0 on success, < 0 on failure - * @ingroup dpdk_devops_func - * - */ -int qdma_dev_rx_queue_setup(struct rte_eth_dev *dev, uint16_t rx_queue_id, - uint16_t nb_rx_desc, unsigned int socket_id, - const struct rte_eth_rxconf *rx_conf, - struct rte_mempool *mb_pool); - -/** - * DPDK callback to configure a TX queue. - * - * This API validates queue parameters and allocates H2C ring from the - * DPDK reserved hugepage memory zone - * - * @param dev Pointer to Ethernet device structure - * @param tx_queue_id TX queue index - * @param nb_tx_desc Number of descriptors to configure in queue - * @param socket_id NUMA socket on which memory must be allocated - * @param tx_conf Tx queue configuration parameters - * - * @return 0 on success, < 0 on failure - * @ingroup dpdk_devops_func - * - */ -int qdma_dev_tx_queue_setup(struct rte_eth_dev *dev, uint16_t tx_queue_id, - uint16_t nb_tx_desc, unsigned int socket_id, - const struct rte_eth_txconf *tx_conf); - -/** - * DPDK callback to get Rx queue info of an Ethernet device - * - * @param dev - * Pointer to Ethernet device structure - * @param rx_queue_id - * The RX queue on the Ethernet device for which information will be - * retrieved - * @param qinfo - * A pointer to a structure of type rte_eth_rxq_info_info to be filled with - * the information of given Rx queue - * - * @ingroup dpdk_devops_func - */ -void -qdma_dev_rxq_info_get(struct rte_eth_dev *dev, uint16_t rx_queue_id, - struct rte_eth_rxq_info *qinfo); - -/** - * DPDK callback to get Tx queue info of an Ethernet device - * - * @param dev - * Pointer to Ethernet device structure - * @param tx_queue_id - * The TX queue on the Ethernet device for which information will be - * retrieved - * @param qinfo - * A pointer to a structure of type rte_eth_txq_info_info to be filled with - * the information of given Tx queue - * - * @ingroup dpdk_devops_func - */ -void -qdma_dev_txq_info_get(struct rte_eth_dev *dev, uint16_t tx_queue_id, - struct rte_eth_txq_info *qinfo); - -/** - * DPDK callback to start the device. - * - * This API starts the Ethernet device by initializing Rx, Tx descriptors - * and device registers. For the Port queues whose start is not deferred, - * it calls qdma_dev_tx_queue_start and qdma_dev_rx_queue_start to start - * the queues for packet processing. - * - * @param dev Pointer to Ethernet device structure - * - * @return 0 on success, < 0 on failure - * @ingroup dpdk_devops_func - * - */ -int qdma_dev_start(struct rte_eth_dev *dev); - -/** - * DPDK callback to start a C2H queue which has been deferred start. - * - * This API clears and then programs the Software, Prefetch and - * Completion context of the C2H queue - * - * @param dev Pointer to Ethernet device structure - * @param qid Rx queue index - * - * @return 0 on success, < 0 on failure - * @ingroup dpdk_devops_func - * - */ -int qdma_dev_rx_queue_start(struct rte_eth_dev *dev, uint16_t qid); - -/** - * DPDK callback to start a H2C queue which has been deferred start. - * - * This API clears and then programs the Software context of the H2C queue - * - * @param dev Pointer to Ethernet device structure - * @param qid Tx queue index - * - * @return 0 on success, < 0 on failure - * @ingroup dpdk_devops_func - * - */ -int qdma_dev_tx_queue_start(struct rte_eth_dev *dev, uint16_t qid); - -/** - * DPDK callback for receiving packets in burst. - * - * This API does following operations: - * - Process the Completion ring to determine and store packet information - * - Update CMPT CIDX - * - Process C2H ring to retrieve rte_mbuf pointers corresponding to - * received packets and store in rx_pkts array. - * - Populate C2H ring with new pointers for packet buffers - * - Update C2H ring PIDX - * - * @param rx_queue Generic pointer to Rx queue structure - * @param rx_pkts The address of an array of pointers to rte_mbuf structures - * that must be large enough to store nb_pkts pointers in it - * @param nb_pkts Maximum number of packets to retrieve - * - * @return Number of packets successfully received (<= nb_pkts) - * @ingroup dpdk_devops_func - * - */ -uint16_t qdma_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, - uint16_t nb_pkts); - -/** - * DPDK callback for transmitting packets in burst. - * - * This API does following operations: - * - Free rte_mbuf pointers to previous transmitted packets, - * back to the memory pool - * - Retrieve packet buffer pointer from tx_pkts and populate H2C ring - * with pointers to new packet buffers. - * - Update H2C ring PIDX - * - * @param tx_queue Generic pointer to Tx queue structure - * @param tx_pkts The address of an array of nb_pkts pointers to - * rte_mbuf structures which contain the output packets - * @param nb_pkts The maximum number of packets to transmit - * - * @return Number of packets successfully transmitted (<= nb_pkts) - * @ingroup dpdk_devops_func - * - */ -uint16_t qdma_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, - uint16_t nb_pkts); - -/** - * DPDK callback for retrieving Port statistics. - * - * This API updates Port statistics in rte_eth_stats structure parameters - * - * @param dev Pointer to Ethernet device structure - * @param eth_stats Pointer to structure containing statistics - * - * @return 0 on success, < 0 on failure - * @ingroup dpdk_devops_func - * - */ -int qdma_dev_stats_get(struct rte_eth_dev *dev, - struct rte_eth_stats *eth_stats); - -/** - * DPDK callback to reset Port statistics. - * - * @param dev - * Pointer to Ethernet device structure. - * - * @ingroup dpdk_devops_func - */ -int qdma_dev_stats_reset(struct rte_eth_dev *dev); - -/** - * DPDK callback to set a queue statistics mapping for - * a tx/rx queue of an Ethernet device. - * - * @param dev - * Pointer to Ethernet device structure - * @param queue_id - * Index of the queue for which a queue stats mapping is required - * @param stat_idx - * The per-queue packet statistics functionality number that - * the queue_id is to be assigned - * @param is_rx - * Whether queue is a Rx or a Tx queue - * - * @return - * 0 on success, -EINVAL on failure - * @ingroup dpdk_devops_func - */ -int qdma_dev_queue_stats_mapping(struct rte_eth_dev *dev, - uint16_t queue_id, - uint8_t stat_idx, - uint8_t is_rx); - - -/** - * DPDK callback to check the status of a Rx descriptor in the queue - * - * @param rx_queue - * Pointer to Rx queue specific data structure - * @param offset - * The offset of the descriptor starting from tail (0 is the next - * packet to be received by the driver) - * - * @return - * - (RTE_ETH_RX_DESC_AVAIL): Descriptor is available for the hardware to - * receive a packet. - * - (RTE_ETH_RX_DESC_DONE): Descriptor is done, it is filled by hw, but - * not yet processed by the driver (i.e. in the receive queue). - * - (RTE_ETH_RX_DESC_UNAVAIL): Descriptor is unavailable, either hold by - * the driver and not yet returned to hw, or reserved by the hw. - * - (-EINVAL) bad descriptor offset. - * @ingroup dpdk_devops_func - */ -int -qdma_dev_rx_descriptor_status(void *rx_queue, uint16_t offset); - -/** - * DPDK callback to check the status of a Tx descriptor in the queue - * - * @param tx_queue - * Pointer to Tx queue specific data structure - * @param offset - * The offset of the descriptor starting from tail (0 is the place where - * the next packet will be send) - * - * @return - * - (RTE_ETH_TX_DESC_FULL) Descriptor is being processed by the hw, i.e. - * in the transmit queue. - * - (RTE_ETH_TX_DESC_DONE) Hardware is done with this descriptor, it can - * be reused by the driver. - * - (RTE_ETH_TX_DESC_UNAVAIL): Descriptor is unavailable, reserved by the - * driver or the hardware. - * - (-EINVAL) bad descriptor offset. - * @ingroup dpdk_devops_func - */ -int -qdma_dev_tx_descriptor_status(void *tx_queue, uint16_t offset); - -/** - * DPDK callback to request the driver to free mbufs - * currently cached by the driver - * - * @param tx_queue - * Pointer to Tx queue specific data structure - * @param free_cnt - * Maximum number of packets to free. Use 0 to indicate all possible packets - * should be freed. Note that a packet may be using multiple mbufs. - * - * @return - * - Failure: < 0 - * - Success: >= 0 - * 0-n: Number of packets freed. More packets may still remain in ring that - * are in use. - * @ingroup dpdk_devops_func - */ -int -qdma_dev_tx_done_cleanup(void *tx_queue, uint32_t free_cnt); - -/** - * DPDK callback to retrieve device registers and - * register attributes (number of registers and register size) - * - * @param dev - * Pointer to Ethernet device structure - * @param regs - * Pointer to rte_dev_reg_info structure to fill in. If regs->data is - * NULL the function fills in the width and length fields. If non-NULL - * the registers are put into the buffer pointed at by the data field. - * - * @return - * 0 on success, -ENOTSUP on failure - * @ingroup dpdk_devops_func - */ -int -qdma_dev_get_regs(struct rte_eth_dev *dev, - struct rte_dev_reg_info *regs); - -/** - * DPDK callback to stop a C2H queue - * - * This API invalidates Hardware, Software, Prefetch and completion contexts - * of C2H queue. It also free the rte_mbuf pointers assigned to descriptors - * prepared for packet reception. - * - * @param dev Pointer to Ethernet device structure - * @param qid Rx queue index - * - * @return 0 on success, < 0 on failure - * @ingroup dpdk_devops_func - * - */ -int qdma_dev_rx_queue_stop(struct rte_eth_dev *dev, uint16_t qid); - -/** - * qdma_dev_tx_queue_stop() - DPDK callback to stop a queue in H2C direction - * - * This API invalidates Hardware, Software contexts of H2C queue. It also free - * the rte_mbuf pointers assigned to descriptors that are pending transmission. - * - * @param dev Pointer to Ethernet device structure - * @param qid TX queue index - * - * @return 0 on success, < 0 on failure - * @ingroup dpdk_devops_func - * - */ -int qdma_dev_tx_queue_stop(struct rte_eth_dev *dev, uint16_t qid); - - -/** - * DPDK callback to stop the device. - * - * This API stops the device by invalidating all the contexts of all the queues - * belonging to the port by calling qdma_dev_tx_queue_stop() and - * qdma_dev_rx_queue_stop() for all the queues of the port. - * - * @param dev Pointer to Ethernet device structure - * - * @ingroup dpdk_devops_func - * - */ -int qdma_dev_stop(struct rte_eth_dev *dev); - -/** - * DPDK callback to close the device. - * - * This API frees the descriptor rings and objects beonging to all the queues - * of the given port. It also clears the FMAP. - * - * @param dev Pointer to Ethernet device structure - * - * @ingroup dpdk_devops_func - */ -int qdma_dev_close(struct rte_eth_dev *dev); - -/** - * DPDK callback to close the VF device. - * - * This API frees the descriptor rings and objects beonging to all the queues - * of the given port. It also clears the FMAP. - * - * @param dev Pointer to Ethernet device structure - * - * @ingroup dpdk_devops_func - */ -int qdma_vf_dev_close(struct rte_eth_dev *dev); - -/** - * DPDK callback to reset the device. - * - * This callback is invoked when applcation calls rte_eth_dev_reset() API - * to reset a device. This callback uninitialzes PF device after waiting for - * all its VFs to shutdown. It initialize back PF device and then send - * Reset done mailbox message to all its VFs to come online again. - * - * @param dev - * Pointer to Ethernet device structure - * - * @return - * 0 on success, negative errno value on failure - * @ingroup dpdk_devops_func - */ -int qdma_dev_reset(struct rte_eth_dev *dev); - -/** - * DPDK callback to deregister a PCI device. - * - * The Following actions are performed by this function: - * - Flushes out pending actions from the Tx Mailbox List - * - Terminate Tx Mailbox thread - * - Disable Mailbox interrupt and unregister interrupt handler - * - Unregister PCIe device from Queue Resource Manager - * - Cancel QDMA HW error monitoring thread if created by this device - * - Disable MM C2H and H2C channels - * - * @param dev Pointer to Ethernet device structure - * - * @return 0 on success, < 0 on failure - * @ingroup dpdk_devops_func - * - */ -int qdma_eth_dev_uninit(struct rte_eth_dev *dev); - -#ifdef __cplusplus -} -#endif -#endif /* ifndef __QDMA_DEVOPS_H__ */ diff --git a/QDMA/DPDK/drivers/net/qdma/qdma_dpdk_compat.c b/QDMA/DPDK/drivers/net/qdma/qdma_dpdk_compat.c deleted file mode 100755 index 1b4e76717..000000000 --- a/QDMA/DPDK/drivers/net/qdma/qdma_dpdk_compat.c +++ /dev/null @@ -1,316 +0,0 @@ -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include "qdma.h" -#include "qdma_access_common.h" -#include "qdma_mbox_protocol.h" -#include "qdma_mbox.h" -#include "qdma_reg_dump.h" -#include "qdma_platform.h" -#include "qdma_devops.h" - - -#if defined(QDMA_DPDK_21_11) || defined(QDMA_DPDK_22_11) - -void qdma_dev_tx_queue_release(struct rte_eth_dev *dev, - uint16_t queue_id) -{ - struct qdma_tx_queue *txq = - (struct qdma_tx_queue *)dev->data->tx_queues[queue_id]; - struct qdma_pci_dev *qdma_dev; - - if (txq != NULL) { - PMD_DRV_LOG(INFO, "Remove H2C queue: %d", txq->queue_id); - qdma_dev = txq->dev->data->dev_private; - - if (!qdma_dev->is_vf) - qdma_dev_decrement_active_queue( - qdma_dev->dma_device_index, - qdma_dev->func_id, - QDMA_DEV_Q_TYPE_H2C); - else - qdma_dev_notify_qdel(txq->dev, txq->queue_id + - qdma_dev->queue_base, - QDMA_DEV_Q_TYPE_H2C); - if (txq->sw_ring) - rte_free(txq->sw_ring); - if (txq->tx_mz) - rte_memzone_free(txq->tx_mz); - rte_free(txq); - PMD_DRV_LOG(INFO, "H2C queue %d removed", txq->queue_id); - } -} - -void qdma_dev_rx_queue_release(struct rte_eth_dev *dev, - uint16_t queue_id) -{ - struct qdma_rx_queue *rxq = - (struct qdma_rx_queue *)dev->data->rx_queues[queue_id]; - struct qdma_pci_dev *qdma_dev = NULL; - - if (rxq != NULL) { - PMD_DRV_LOG(INFO, "Remove C2H queue: %d", rxq->queue_id); - qdma_dev = rxq->dev->data->dev_private; - - if (!qdma_dev->is_vf) { - qdma_dev_decrement_active_queue( - qdma_dev->dma_device_index, - qdma_dev->func_id, - QDMA_DEV_Q_TYPE_C2H); - - if (rxq->st_mode) - qdma_dev_decrement_active_queue( - qdma_dev->dma_device_index, - qdma_dev->func_id, - QDMA_DEV_Q_TYPE_CMPT); - } else { - qdma_dev_notify_qdel(rxq->dev, rxq->queue_id + - qdma_dev->queue_base, - QDMA_DEV_Q_TYPE_C2H); - - if (rxq->st_mode) - qdma_dev_notify_qdel(rxq->dev, rxq->queue_id + - qdma_dev->queue_base, - QDMA_DEV_Q_TYPE_CMPT); - } - - if (rxq->sw_ring) - rte_free(rxq->sw_ring); - if (rxq->st_mode) { /** if ST-mode **/ - if (rxq->rx_cmpt_mz) - rte_memzone_free(rxq->rx_cmpt_mz); - } - if (rxq->rx_mz) - rte_memzone_free(rxq->rx_mz); - rte_free(rxq); - PMD_DRV_LOG(INFO, "C2H queue %d removed", rxq->queue_id); - } -} - -/** - * DPDK callback to get the number of receive queue. - * - * @param dev - * Generic pointer to receive queue - * - * @return - * The number of receieve queue count. - */ -uint32_t -qdma_dev_rx_queue_count(void *rx_queue) -{ - struct qdma_rx_queue *rxq = rx_queue; - return rx_queue_count(rxq); -} - -#endif - -#ifdef QDMA_DPDK_20_11 -void qdma_dev_tx_queue_release(void *tqueue) -{ - struct qdma_tx_queue *txq = (struct qdma_tx_queue *)tqueue; - struct qdma_pci_dev *qdma_dev; - if (txq != NULL) { - PMD_DRV_LOG(INFO, "Remove H2C queue: %d", txq->queue_id); - qdma_dev = txq->dev->data->dev_private; - if (!qdma_dev->is_vf) - qdma_dev_decrement_active_queue( - qdma_dev->dma_device_index, - qdma_dev->func_id, - QDMA_DEV_Q_TYPE_H2C); - else - qdma_dev_notify_qdel(txq->dev, txq->queue_id + - qdma_dev->queue_base, - QDMA_DEV_Q_TYPE_H2C); - if (txq->sw_ring) - rte_free(txq->sw_ring); - if (txq->tx_mz) - rte_memzone_free(txq->tx_mz); - rte_free(txq); - PMD_DRV_LOG(INFO, "H2C queue %d removed", txq->queue_id); - } -} - -void qdma_dev_rx_queue_release(void *rqueue) -{ - struct qdma_rx_queue *rxq = (struct qdma_rx_queue *)rqueue; - struct qdma_pci_dev *qdma_dev = NULL; - if (rxq != NULL) { - PMD_DRV_LOG(INFO, "Remove C2H queue: %d", rxq->queue_id); - qdma_dev = rxq->dev->data->dev_private; - if (!qdma_dev->is_vf) { - qdma_dev_decrement_active_queue( - qdma_dev->dma_device_index, - qdma_dev->func_id, - QDMA_DEV_Q_TYPE_C2H); - if (rxq->st_mode) - qdma_dev_decrement_active_queue( - qdma_dev->dma_device_index, - qdma_dev->func_id, - QDMA_DEV_Q_TYPE_CMPT); - } else { - qdma_dev_notify_qdel(rxq->dev, rxq->queue_id + - qdma_dev->queue_base, - QDMA_DEV_Q_TYPE_C2H); - if (rxq->st_mode) - qdma_dev_notify_qdel(rxq->dev, rxq->queue_id + - qdma_dev->queue_base, - QDMA_DEV_Q_TYPE_CMPT); - } - if (rxq->sw_ring) - rte_free(rxq->sw_ring); - if (rxq->st_mode) { /** if ST-mode **/ - if (rxq->rx_cmpt_mz) - rte_memzone_free(rxq->rx_cmpt_mz); - } - if (rxq->rx_mz) - rte_memzone_free(rxq->rx_mz); - rte_free(rxq); - PMD_DRV_LOG(INFO, "C2H queue %d removed", rxq->queue_id); - } -} - -/** - * DPDK callback to get the number of used descriptors of a rx queue. - * - * @param dev - * Pointer to Ethernet device structure. - * @param rx_queue_id - * The RX queue on the Ethernet device for which information will be - * retrieved - * - * @return - * The number of used descriptors in the specific queue. - */ -uint32_t -qdma_dev_rx_queue_count(struct rte_eth_dev *dev, uint16_t rx_queue_id) -{ - return rx_queue_count(dev->data->rx_queues[rx_queue_id]); -} - -#endif - -void rte_pmd_qdma_compat_memzone_reserve_aligned(void) -{ - const struct rte_memzone *mz = 0; - - mz = rte_memzone_reserve_aligned("eth_devices", RTE_MAX_ETHPORTS * - sizeof(*rte_eth_devices), 0, 0, 4096); - - if (mz == NULL) - rte_exit(EXIT_FAILURE, "Failed to allocate aligned memzone\n"); - - memcpy(mz->addr, &rte_eth_devices[0], RTE_MAX_ETHPORTS * - sizeof(*rte_eth_devices)); -} - -void rte_pmd_qdma_get_bdf(uint32_t m_id, uint32_t *bus, - uint32_t *dev, uint32_t *fn) -{ - struct rte_pci_device *pci_dev; - pci_dev = RTE_ETH_DEV_TO_PCI(&rte_eth_devices[m_id]); - *bus = pci_dev->addr.bus; - *dev = pci_dev->addr.devid; - *fn = pci_dev->addr.function; -} - -int rte_pmd_qdma_dev_remove(int port_id) -{ - struct rte_device *dev; - dev = rte_eth_devices[port_id].device; - return rte_dev_remove(dev); -} - -struct rte_device *rte_pmd_qdma_get_device(int port_id) -{ - struct rte_device *dev; - dev = rte_eth_devices[port_id].device; - return dev; -} - -bool rte_pmd_qdma_validate_dev(int port_id) -{ - struct rte_device *device = rte_pmd_qdma_get_device(port_id); - - if (device && ((!strcmp(device->driver->name, "net_qdma")) || - (!strcmp(device->driver->name, "net_qdma_vf")))) - return true; - else - return false; -} - -uint16_t rte_pmd_qdma_get_dev_id(int port_id) -{ - struct rte_pci_device *pci_dev; - pci_dev = RTE_ETH_DEV_TO_PCI(&rte_eth_devices[port_id]); - return pci_dev->id.device_id; -} - -struct rte_pci_device *rte_pmd_qdma_eth_dev_to_pci(int port_id) -{ - return RTE_ETH_DEV_TO_PCI(&rte_eth_devices[port_id]); -} - -unsigned int rte_pmd_qdma_compat_pci_read_reg(int port_id, - unsigned int bar, unsigned int offset) -{ - return qdma_pci_read_reg(&rte_eth_devices[port_id], bar, offset); -} - -void rte_pmd_qdma_compat_pci_write_reg(int port_id, uint32_t bar, - uint32_t offset, uint32_t reg_val) -{ - qdma_pci_write_reg(&rte_eth_devices[port_id], bar, offset, reg_val); -} - -void rte_pmd_qdma_dev_started(int port_id, bool status) -{ - struct rte_eth_dev *dev; - dev = &rte_eth_devices[port_id]; - dev->data->dev_started = status; -} - -int rte_pmd_qdma_dev_fp_ops_config(int port_id) -{ -#if (defined(QDMA_DPDK_21_11) || defined(QDMA_DPDK_22_11)) - struct rte_eth_dev *dev; - struct rte_eth_fp_ops *fpo = rte_eth_fp_ops; - - if (port_id < 0 || port_id >= rte_eth_dev_count_avail()) { - PMD_DRV_LOG(ERR, - "%s:%d Wrong port id %d\n", - __func__, __LINE__, port_id); - return -ENOTSUP; - } - dev = &rte_eth_devices[port_id]; - - fpo[port_id].rx_pkt_burst = dev->rx_pkt_burst; - fpo[port_id].tx_pkt_burst = dev->tx_pkt_burst; - fpo[port_id].rx_queue_count = dev->rx_queue_count; - fpo[port_id].rx_descriptor_status = dev->rx_descriptor_status; - fpo[port_id].tx_descriptor_status = dev->tx_descriptor_status; - fpo[port_id].rxq.data = dev->data->rx_queues; - fpo[port_id].txq.data = dev->data->tx_queues; - - return 0; -#endif - -#ifdef QDMA_DPDK_20_11 - RTE_SET_USED(port_id); - return 0; -#endif -} - diff --git a/QDMA/DPDK/drivers/net/qdma/qdma_dpdk_compat.h b/QDMA/DPDK/drivers/net/qdma/qdma_dpdk_compat.h deleted file mode 100755 index dfe358648..000000000 --- a/QDMA/DPDK/drivers/net/qdma/qdma_dpdk_compat.h +++ /dev/null @@ -1,118 +0,0 @@ -#ifndef __QDMA_DPDK_COMPAT_H__ -#define __QDMA_DPDK_COMPAT_H__ - -#if (defined(QDMA_DPDK_21_11) || defined(QDMA_DPDK_22_11)) -#include -#include - -#define ETH_LINK_UP RTE_ETH_LINK_UP -#define ETH_LINK_FULL_DUPLEX RTE_ETH_LINK_FULL_DUPLEX -#define ETH_SPEED_NUM_200G RTE_ETH_SPEED_NUM_200G -#define pci_dev_intr_handle pci_dev->intr_handle -#define qdma_dev_rx_queue_count qdma_dev_rx_queue_count_v2122 -#define qdma_dev_rx_queue_release qdma_dev_rx_queue_release_v2122 -#define qdma_dev_tx_queue_release qdma_dev_tx_queue_release_v2122 - -#ifdef QDMA_DPDK_21_11 -#include -#else //QDMA_DPDK_22_11 -#include -#endif - -/** - * DPDK callback to get the number of rx_queue - * - * @param rx_queue - * Generic recieve queue pointer - * @return - * The number of receive queues - * @ingroup dpdk_devops_func - */ -uint32_t -qdma_dev_rx_queue_count(void *rx_queue); - -/** - * DPDK callback to release a Rx queue. - * - * @param dev - * Pointer to Ethernet device structure - * @param rx_queue_id - * The RX queue on the Ethernet device for which information will be - * retrieved - * - * @ingroup dpdk_devops_func - */ -void qdma_dev_rx_queue_release(struct rte_eth_dev *dev, uint16_t queue_id); - -/** - * DPDK callback to release a Tx queue. - * - * @param dev - * Pointer to Ethernet device structure - * @param queue_id - * The Tx queue on the Ethernet device for which information will be - * retrieved - * - * @ingroup dpdk_devops_func - */ - -void qdma_dev_tx_queue_release(struct rte_eth_dev *dev, uint16_t queue_id); -#endif - -#ifdef QDMA_DPDK_20_11 - -#include -#include -#define pci_dev_intr_handle (&pci_dev->intr_handle) -#define qdma_dev_rx_queue_count qdma_dev_rx_queue_count_v2011 -#define qdma_dev_rx_queue_release qdma_dev_rx_queue_release_v2011 -#define qdma_dev_tx_queue_release qdma_dev_tx_queue_release_v2011 - -/** - * DPDK callback to get the number of used descriptors of a rx queue - * - * @param dev - * Pointer to Ethernet device structure - * @param rx_queue_id - * The RX queue on the Ethernet device for which information will be - * retrieved - * - * @return - * The number of used descriptors in the specific queue - * @ingroup dpdk_devops_func - */ -uint32_t -qdma_dev_rx_queue_count(struct rte_eth_dev *dev, uint16_t rx_queue_id); - -/** - * DPDK callback to release a Tx queue. - * - * This API releases the descriptor rings and any additional memory allocated - * for given H2C queue - * - * @param tqueue: Generic Tx queue pointer - * - * @ingroup dpdk_devops_func - */ -void qdma_dev_tx_queue_release(void *tqueue); - -/** - * DPDK callback to release a Rx queue. - * - * This API releases the descriptor rings and any additional memory allocated - * for given C2H queue - * - * @param rqueue: Generic Rx queue pointer - * - * @ingroup dpdk_devops_func - */ -void qdma_dev_rx_queue_release(void *rqueue); - -#endif - - -#endif /* ifndef __QDMA_DPDK_COMPAT_H__ */ - - - - diff --git a/QDMA/DPDK/drivers/net/qdma/qdma_ethdev.c b/QDMA/DPDK/drivers/net/qdma/qdma_ethdev.c deleted file mode 100755 index 6bd6147f7..000000000 --- a/QDMA/DPDK/drivers/net/qdma/qdma_ethdev.c +++ /dev/null @@ -1,976 +0,0 @@ -/*- - * BSD LICENSE - * - * Copyright (c) 2017-2022 Xilinx, Inc. All rights reserved. - * Copyright (c) 2022-2023, Advanced Micro Devices, Inc. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * * Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include "qdma.h" -#include "version.h" -#include "qdma_access_common.h" -#include "qdma_access_export.h" -#include "qdma_mbox.h" -#include "qdma_devops.h" - -/* Poll for QDMA errors every 1 second */ -#define QDMA_ERROR_POLL_FRQ (1000000) - -#define PCI_CONFIG_BRIDGE_DEVICE (6) -#define PCI_CONFIG_CLASS_CODE_SHIFT (16) - -#define MAX_PCIE_CAPABILITY (48) - -#ifdef LATENCY_MEASUREMENT -const struct rte_memzone *txq_lat_buf_mz; -const struct rte_memzone *rxq_lat_buf_mz; -double (*h2c_pidx_to_hw_cidx_lat)[LATENCY_CNT] = NULL; -double (*c2h_pidx_to_cmpt_pidx_lat)[LATENCY_CNT] = NULL; -#endif - -static void qdma_device_attributes_get(struct rte_eth_dev *dev); - -/* Poll for any QDMA errors */ -void qdma_check_errors(void *arg) -{ - struct qdma_pci_dev *qdma_dev; - qdma_dev = ((struct rte_eth_dev *)arg)->data->dev_private; - qdma_dev->hw_access->qdma_hw_error_process(arg); - rte_eal_alarm_set(QDMA_ERROR_POLL_FRQ, qdma_check_errors, arg); -} - -/* - * The set of PCI devices this driver supports - */ -static struct rte_pci_id qdma_pci_id_tbl[] = { -#define RTE_PCI_DEV_ID_DECL(vend, dev) {RTE_PCI_DEVICE(vend, dev)}, -#ifndef PCI_VENDOR_ID_XILINX -#define PCI_VENDOR_ID_XILINX 0x10ee -#endif - - /** Gen 1 PF */ - /** PCIe lane width x1 */ - RTE_PCI_DEV_ID_DECL(PCI_VENDOR_ID_XILINX, 0x9011) /** PF 0 */ - RTE_PCI_DEV_ID_DECL(PCI_VENDOR_ID_XILINX, 0x9111) /** PF 1 */ - RTE_PCI_DEV_ID_DECL(PCI_VENDOR_ID_XILINX, 0x9211) /** PF 2 */ - RTE_PCI_DEV_ID_DECL(PCI_VENDOR_ID_XILINX, 0x9311) /** PF 3 */ - /** PCIe lane width x4 */ - RTE_PCI_DEV_ID_DECL(PCI_VENDOR_ID_XILINX, 0x9014) /** PF 0 */ - RTE_PCI_DEV_ID_DECL(PCI_VENDOR_ID_XILINX, 0x9114) /** PF 1 */ - RTE_PCI_DEV_ID_DECL(PCI_VENDOR_ID_XILINX, 0x9214) /** PF 2 */ - RTE_PCI_DEV_ID_DECL(PCI_VENDOR_ID_XILINX, 0x9314) /** PF 3 */ - /** PCIe lane width x8 */ - RTE_PCI_DEV_ID_DECL(PCI_VENDOR_ID_XILINX, 0x9018) /** PF 0 */ - RTE_PCI_DEV_ID_DECL(PCI_VENDOR_ID_XILINX, 0x9118) /** PF 1 */ - RTE_PCI_DEV_ID_DECL(PCI_VENDOR_ID_XILINX, 0x9218) /** PF 2 */ - RTE_PCI_DEV_ID_DECL(PCI_VENDOR_ID_XILINX, 0x9318) /** PF 3 */ - /** PCIe lane width x16 */ - RTE_PCI_DEV_ID_DECL(PCI_VENDOR_ID_XILINX, 0x901f) /** PF 0 */ - RTE_PCI_DEV_ID_DECL(PCI_VENDOR_ID_XILINX, 0x911f) /** PF 1 */ - RTE_PCI_DEV_ID_DECL(PCI_VENDOR_ID_XILINX, 0x921f) /** PF 2 */ - RTE_PCI_DEV_ID_DECL(PCI_VENDOR_ID_XILINX, 0x931f) /** PF 3 */ - - /** Gen 2 PF */ - /** PCIe lane width x1 */ - RTE_PCI_DEV_ID_DECL(PCI_VENDOR_ID_XILINX, 0x9021) /** PF 0 */ - RTE_PCI_DEV_ID_DECL(PCI_VENDOR_ID_XILINX, 0x9121) /** PF 1 */ - RTE_PCI_DEV_ID_DECL(PCI_VENDOR_ID_XILINX, 0x9221) /** PF 2 */ - RTE_PCI_DEV_ID_DECL(PCI_VENDOR_ID_XILINX, 0x9321) /** PF 3 */ - /** PCIe lane width x4 */ - RTE_PCI_DEV_ID_DECL(PCI_VENDOR_ID_XILINX, 0x9024) /** PF 0 */ - RTE_PCI_DEV_ID_DECL(PCI_VENDOR_ID_XILINX, 0x9124) /** PF 1 */ - RTE_PCI_DEV_ID_DECL(PCI_VENDOR_ID_XILINX, 0x9224) /** PF 2 */ - RTE_PCI_DEV_ID_DECL(PCI_VENDOR_ID_XILINX, 0x9324) /** PF 3 */ - /** PCIe lane width x8 */ - RTE_PCI_DEV_ID_DECL(PCI_VENDOR_ID_XILINX, 0x9028) /** PF 0 */ - RTE_PCI_DEV_ID_DECL(PCI_VENDOR_ID_XILINX, 0x9128) /** PF 1 */ - RTE_PCI_DEV_ID_DECL(PCI_VENDOR_ID_XILINX, 0x9228) /** PF 2 */ - RTE_PCI_DEV_ID_DECL(PCI_VENDOR_ID_XILINX, 0x9328) /** PF 3 */ - /** PCIe lane width x16 */ - RTE_PCI_DEV_ID_DECL(PCI_VENDOR_ID_XILINX, 0x902f) /** PF 0 */ - RTE_PCI_DEV_ID_DECL(PCI_VENDOR_ID_XILINX, 0x912f) /** PF 1 */ - RTE_PCI_DEV_ID_DECL(PCI_VENDOR_ID_XILINX, 0x922f) /** PF 2 */ - RTE_PCI_DEV_ID_DECL(PCI_VENDOR_ID_XILINX, 0x932f) /** PF 3 */ - - /** Gen 3 PF */ - /** PCIe lane width x1 */ - RTE_PCI_DEV_ID_DECL(PCI_VENDOR_ID_XILINX, 0x9031) /** PF 0 */ - RTE_PCI_DEV_ID_DECL(PCI_VENDOR_ID_XILINX, 0x9131) /** PF 1 */ - RTE_PCI_DEV_ID_DECL(PCI_VENDOR_ID_XILINX, 0x9231) /** PF 2 */ - RTE_PCI_DEV_ID_DECL(PCI_VENDOR_ID_XILINX, 0x9331) /** PF 3 */ - /** PCIe lane width x4 */ - RTE_PCI_DEV_ID_DECL(PCI_VENDOR_ID_XILINX, 0x9034) /** PF 0 */ - RTE_PCI_DEV_ID_DECL(PCI_VENDOR_ID_XILINX, 0x9134) /** PF 1 */ - RTE_PCI_DEV_ID_DECL(PCI_VENDOR_ID_XILINX, 0x9234) /** PF 2 */ - RTE_PCI_DEV_ID_DECL(PCI_VENDOR_ID_XILINX, 0x9334) /** PF 3 */ - /** PCIe lane width x8 */ - RTE_PCI_DEV_ID_DECL(PCI_VENDOR_ID_XILINX, 0x9038) /** PF 0 */ - RTE_PCI_DEV_ID_DECL(PCI_VENDOR_ID_XILINX, 0x9138) /** PF 1 */ - RTE_PCI_DEV_ID_DECL(PCI_VENDOR_ID_XILINX, 0x9238) /** PF 2 */ - RTE_PCI_DEV_ID_DECL(PCI_VENDOR_ID_XILINX, 0x9338) /** PF 3 */ - /** PCIe lane width x16 */ - RTE_PCI_DEV_ID_DECL(PCI_VENDOR_ID_XILINX, 0x903f) /** PF 0 */ - RTE_PCI_DEV_ID_DECL(PCI_VENDOR_ID_XILINX, 0x913f) /** PF 1 */ - RTE_PCI_DEV_ID_DECL(PCI_VENDOR_ID_XILINX, 0x923f) /** PF 2 */ - RTE_PCI_DEV_ID_DECL(PCI_VENDOR_ID_XILINX, 0x933f) /** PF 3 */ - - /** Gen 4 PF */ - /** PCIe lane width x1 */ - RTE_PCI_DEV_ID_DECL(PCI_VENDOR_ID_XILINX, 0x9041) /** PF 0 */ - RTE_PCI_DEV_ID_DECL(PCI_VENDOR_ID_XILINX, 0x9141) /** PF 1 */ - RTE_PCI_DEV_ID_DECL(PCI_VENDOR_ID_XILINX, 0x9241) /** PF 2 */ - RTE_PCI_DEV_ID_DECL(PCI_VENDOR_ID_XILINX, 0x9341) /** PF 3 */ - /** PCIe lane width x4 */ - RTE_PCI_DEV_ID_DECL(PCI_VENDOR_ID_XILINX, 0x9044) /** PF 0 */ - RTE_PCI_DEV_ID_DECL(PCI_VENDOR_ID_XILINX, 0x9144) /** PF 1 */ - RTE_PCI_DEV_ID_DECL(PCI_VENDOR_ID_XILINX, 0x9244) /** PF 2 */ - RTE_PCI_DEV_ID_DECL(PCI_VENDOR_ID_XILINX, 0x9344) /** PF 3 */ - /** PCIe lane width x8 */ - RTE_PCI_DEV_ID_DECL(PCI_VENDOR_ID_XILINX, 0x9048) /** PF 0 */ - RTE_PCI_DEV_ID_DECL(PCI_VENDOR_ID_XILINX, 0x9148) /** PF 1 */ - RTE_PCI_DEV_ID_DECL(PCI_VENDOR_ID_XILINX, 0x9248) /** PF 2 */ - RTE_PCI_DEV_ID_DECL(PCI_VENDOR_ID_XILINX, 0x9348) /** PF 3 */ - - /** Versal */ - /** Gen 1 PF */ - /** PCIe lane width x1 */ - RTE_PCI_DEV_ID_DECL(PCI_VENDOR_ID_XILINX, 0xb011) /** PF 0 */ - RTE_PCI_DEV_ID_DECL(PCI_VENDOR_ID_XILINX, 0xb111) /** PF 1 */ - RTE_PCI_DEV_ID_DECL(PCI_VENDOR_ID_XILINX, 0xb211) /** PF 2 */ - RTE_PCI_DEV_ID_DECL(PCI_VENDOR_ID_XILINX, 0xb311) /** PF 3 */ - /** PCIe lane width x4 */ - RTE_PCI_DEV_ID_DECL(PCI_VENDOR_ID_XILINX, 0xb014) /** PF 0 */ - RTE_PCI_DEV_ID_DECL(PCI_VENDOR_ID_XILINX, 0xb114) /** PF 1 */ - RTE_PCI_DEV_ID_DECL(PCI_VENDOR_ID_XILINX, 0xb214) /** PF 2 */ - RTE_PCI_DEV_ID_DECL(PCI_VENDOR_ID_XILINX, 0xb314) /** PF 3 */ - /** PCIe lane width x8 */ - RTE_PCI_DEV_ID_DECL(PCI_VENDOR_ID_XILINX, 0xb018) /** PF 0 */ - RTE_PCI_DEV_ID_DECL(PCI_VENDOR_ID_XILINX, 0xb118) /** PF 1 */ - RTE_PCI_DEV_ID_DECL(PCI_VENDOR_ID_XILINX, 0xb218) /** PF 2 */ - RTE_PCI_DEV_ID_DECL(PCI_VENDOR_ID_XILINX, 0xb318) /** PF 3 */ - /** PCIe lane width x16 */ - RTE_PCI_DEV_ID_DECL(PCI_VENDOR_ID_XILINX, 0xb01f) /** PF 0 */ - RTE_PCI_DEV_ID_DECL(PCI_VENDOR_ID_XILINX, 0xb11f) /** PF 1 */ - RTE_PCI_DEV_ID_DECL(PCI_VENDOR_ID_XILINX, 0xb21f) /** PF 2 */ - RTE_PCI_DEV_ID_DECL(PCI_VENDOR_ID_XILINX, 0xb31f) /** PF 3 */ - - /** Gen 2 PF */ - /** PCIe lane width x1 */ - RTE_PCI_DEV_ID_DECL(PCI_VENDOR_ID_XILINX, 0xb021) /** PF 0 */ - RTE_PCI_DEV_ID_DECL(PCI_VENDOR_ID_XILINX, 0xb121) /** PF 1 */ - RTE_PCI_DEV_ID_DECL(PCI_VENDOR_ID_XILINX, 0xb221) /** PF 2 */ - RTE_PCI_DEV_ID_DECL(PCI_VENDOR_ID_XILINX, 0xb321) /** PF 3 */ - /** PCIe lane width x4 */ - RTE_PCI_DEV_ID_DECL(PCI_VENDOR_ID_XILINX, 0xb024) /** PF 0 */ - RTE_PCI_DEV_ID_DECL(PCI_VENDOR_ID_XILINX, 0xb124) /** PF 1 */ - RTE_PCI_DEV_ID_DECL(PCI_VENDOR_ID_XILINX, 0xb224) /** PF 2 */ - RTE_PCI_DEV_ID_DECL(PCI_VENDOR_ID_XILINX, 0xb324) /** PF 3 */ - /** PCIe lane width x8 */ - RTE_PCI_DEV_ID_DECL(PCI_VENDOR_ID_XILINX, 0xb028) /** PF 0 */ - RTE_PCI_DEV_ID_DECL(PCI_VENDOR_ID_XILINX, 0xb128) /** PF 1 */ - RTE_PCI_DEV_ID_DECL(PCI_VENDOR_ID_XILINX, 0xb228) /** PF 2 */ - RTE_PCI_DEV_ID_DECL(PCI_VENDOR_ID_XILINX, 0xb328) /** PF 3 */ - /** PCIe lane width x16 */ - RTE_PCI_DEV_ID_DECL(PCI_VENDOR_ID_XILINX, 0xb02f) /** PF 0 */ - RTE_PCI_DEV_ID_DECL(PCI_VENDOR_ID_XILINX, 0xb12f) /** PF 1 */ - RTE_PCI_DEV_ID_DECL(PCI_VENDOR_ID_XILINX, 0xb22f) /** PF 2 */ - RTE_PCI_DEV_ID_DECL(PCI_VENDOR_ID_XILINX, 0xb32f) /** PF 3 */ - - /** Gen 3 PF */ - /** PCIe lane width x1 */ - RTE_PCI_DEV_ID_DECL(PCI_VENDOR_ID_XILINX, 0xb031) /** PF 0 */ - RTE_PCI_DEV_ID_DECL(PCI_VENDOR_ID_XILINX, 0xb131) /** PF 1 */ - RTE_PCI_DEV_ID_DECL(PCI_VENDOR_ID_XILINX, 0xb231) /** PF 2 */ - RTE_PCI_DEV_ID_DECL(PCI_VENDOR_ID_XILINX, 0xb331) /** PF 3 */ - /** PCIe lane width x4 */ - RTE_PCI_DEV_ID_DECL(PCI_VENDOR_ID_XILINX, 0xb034) /** PF 0 */ - RTE_PCI_DEV_ID_DECL(PCI_VENDOR_ID_XILINX, 0xb134) /** PF 1 */ - RTE_PCI_DEV_ID_DECL(PCI_VENDOR_ID_XILINX, 0xb234) /** PF 2 */ - RTE_PCI_DEV_ID_DECL(PCI_VENDOR_ID_XILINX, 0xb334) /** PF 3 */ - /** PCIe lane width x8 */ - RTE_PCI_DEV_ID_DECL(PCI_VENDOR_ID_XILINX, 0xb038) /** PF 0 */ - RTE_PCI_DEV_ID_DECL(PCI_VENDOR_ID_XILINX, 0xb138) /** PF 1 */ - RTE_PCI_DEV_ID_DECL(PCI_VENDOR_ID_XILINX, 0xb238) /** PF 2 */ - RTE_PCI_DEV_ID_DECL(PCI_VENDOR_ID_XILINX, 0xb338) /** PF 3 */ - /** PCIe lane width x16 */ - RTE_PCI_DEV_ID_DECL(PCI_VENDOR_ID_XILINX, 0xb03f) /** PF 0 */ - RTE_PCI_DEV_ID_DECL(PCI_VENDOR_ID_XILINX, 0xb13f) /** PF 1 */ - RTE_PCI_DEV_ID_DECL(PCI_VENDOR_ID_XILINX, 0xb23f) /** PF 2 */ - RTE_PCI_DEV_ID_DECL(PCI_VENDOR_ID_XILINX, 0xb33f) /** PF 3 */ - - /** Gen 4 PF */ - /** PCIe lane width x1 */ - RTE_PCI_DEV_ID_DECL(PCI_VENDOR_ID_XILINX, 0xb041) /** PF 0 */ - RTE_PCI_DEV_ID_DECL(PCI_VENDOR_ID_XILINX, 0xb141) /** PF 1 */ - RTE_PCI_DEV_ID_DECL(PCI_VENDOR_ID_XILINX, 0xb241) /** PF 2 */ - RTE_PCI_DEV_ID_DECL(PCI_VENDOR_ID_XILINX, 0xb341) /** PF 3 */ - /** PCIe lane width x4 */ - RTE_PCI_DEV_ID_DECL(PCI_VENDOR_ID_XILINX, 0xb044) /** PF 0 */ - RTE_PCI_DEV_ID_DECL(PCI_VENDOR_ID_XILINX, 0xb144) /** PF 1 */ - RTE_PCI_DEV_ID_DECL(PCI_VENDOR_ID_XILINX, 0xb244) /** PF 2 */ - RTE_PCI_DEV_ID_DECL(PCI_VENDOR_ID_XILINX, 0xb344) /** PF 3 */ - /** PCIe lane width x8 */ - RTE_PCI_DEV_ID_DECL(PCI_VENDOR_ID_XILINX, 0xb048) /** PF 0 */ - RTE_PCI_DEV_ID_DECL(PCI_VENDOR_ID_XILINX, 0xb148) /** PF 1 */ - RTE_PCI_DEV_ID_DECL(PCI_VENDOR_ID_XILINX, 0xb248) /** PF 2 */ - RTE_PCI_DEV_ID_DECL(PCI_VENDOR_ID_XILINX, 0xb348) /** PF 3 */ - - /** Gen 5 PF */ - /** PCIe lane width x8 */ - RTE_PCI_DEV_ID_DECL(PCI_VENDOR_ID_XILINX, 0xb058) /** PF 0 */ - RTE_PCI_DEV_ID_DECL(PCI_VENDOR_ID_XILINX, 0xb158) /** PF 1 */ - RTE_PCI_DEV_ID_DECL(PCI_VENDOR_ID_XILINX, 0xb258) /** PF 2 */ - RTE_PCI_DEV_ID_DECL(PCI_VENDOR_ID_XILINX, 0xb358) /** PF 3 */ - - { .vendor_id = 0, /* sentinel */ }, -}; - -static void qdma_device_attributes_get(struct rte_eth_dev *dev) -{ - struct qdma_pci_dev *qdma_dev; - - qdma_dev = (struct qdma_pci_dev *)dev->data->dev_private; - qdma_dev->hw_access->qdma_get_device_attributes(dev, - &qdma_dev->dev_cap); - - /* Check DPDK configured queues per port */ - if (qdma_dev->dev_cap.num_qs > RTE_MAX_QUEUES_PER_PORT) - qdma_dev->dev_cap.num_qs = RTE_MAX_QUEUES_PER_PORT; - - PMD_DRV_LOG(INFO, "qmax = %d, mm %d, st %d.\n", - qdma_dev->dev_cap.num_qs, qdma_dev->dev_cap.mm_en, - qdma_dev->dev_cap.st_en); -} - -static inline uint8_t pcie_find_cap(const struct rte_pci_device *pci_dev, - uint8_t cap) -{ - uint8_t pcie_cap_pos = 0; - uint8_t pcie_cap_id = 0; - int ttl = MAX_PCIE_CAPABILITY; - int ret; - - ret = rte_pci_read_config(pci_dev, &pcie_cap_pos, sizeof(uint8_t), - PCI_CAPABILITY_LIST); - if (ret < 0) { - PMD_DRV_LOG(ERR, "PCIe config space read failed..\n"); - return 0; - } - - while (ttl-- && pcie_cap_pos >= PCI_STD_HEADER_SIZEOF) { - pcie_cap_pos &= ~3; - - ret = rte_pci_read_config(pci_dev, - &pcie_cap_id, sizeof(uint8_t), - (pcie_cap_pos + PCI_CAP_LIST_ID)); - if (ret < 0) { - PMD_DRV_LOG(ERR, "PCIe config space read failed..\n"); - return 0; - } - - if (pcie_cap_id == 0xff) - break; - - if (pcie_cap_id == cap) - return pcie_cap_pos; - - ret = rte_pci_read_config(pci_dev, - &pcie_cap_pos, sizeof(uint8_t), - (pcie_cap_pos + PCI_CAP_LIST_NEXT)); - if (ret < 0) { - PMD_DRV_LOG(ERR, "PCIe config space read failed..\n"); - return 0; - } - } - - return 0; -} - -static void pcie_perf_enable(const struct rte_pci_device *pci_dev) -{ - uint16_t value; - uint8_t pcie_cap_pos = pcie_find_cap(pci_dev, PCI_CAP_ID_EXP); - - if (!pcie_cap_pos) - return; - - if (pcie_cap_pos > 0) { - if (rte_pci_read_config(pci_dev, &value, sizeof(uint16_t), - pcie_cap_pos + PCI_EXP_DEVCTL) < 0) { - PMD_DRV_LOG(ERR, "PCIe config space read failed..\n"); - return; - } - - value |= (PCI_EXP_DEVCTL_EXT_TAG | PCI_EXP_DEVCTL_RELAX_EN); - - if (rte_pci_write_config(pci_dev, &value, sizeof(uint16_t), - pcie_cap_pos + PCI_EXP_DEVCTL) < 0) { - PMD_DRV_LOG(ERR, "PCIe config space write failed..\n"); - return; - } - } -} - -/* parse a sysfs file containing one integer value */ -static int parse_sysfs_value(const char *filename, uint32_t *val) -{ - FILE *f; - char buf[BUFSIZ]; - char *end = NULL; - - f = fopen(filename, "r"); - if (f == NULL) { - PMD_DRV_LOG(ERR, "%s(): Failed to open sysfs file %s\n", - __func__, filename); - return -1; - } - - if (fgets(buf, sizeof(buf), f) == NULL) { - PMD_DRV_LOG(ERR, "%s(): Failed to read sysfs value %s\n", - __func__, filename); - fclose(f); - return -1; - } - *val = (uint32_t)strtoul(buf, &end, 0); - if ((buf[0] == '\0') || (end == NULL) || (*end != '\n')) { - PMD_DRV_LOG(ERR, "%s(): Failed to parse sysfs value %s\n", - __func__, filename); - fclose(f); - return -1; - } - fclose(f); - return 0; -} - -/* Split up a pci address into its constituent parts. */ -static int parse_pci_addr_format(const char *buf, - int bufsize, struct rte_pci_addr *addr) -{ - /* first split on ':' */ - union splitaddr { - struct { - char *domain; - char *bus; - char *devid; - char *function; - }; - /* last element-separator is "." not ":" */ - char *str[PCI_FMT_NVAL]; - } splitaddr; - - char *buf_copy = strndup(buf, bufsize); - if (buf_copy == NULL) { - PMD_DRV_LOG(ERR, "Failed to get pci address duplicate copy\n"); - return -1; - } - - if (rte_strsplit(buf_copy, bufsize, splitaddr.str, PCI_FMT_NVAL, ':') - != PCI_FMT_NVAL - 1) { - PMD_DRV_LOG(ERR, "Failed to split pci address string\n"); - goto error; - } - - /* final split is on '.' between devid and function */ - splitaddr.function = strchr(splitaddr.devid, '.'); - if (splitaddr.function == NULL) { - PMD_DRV_LOG(ERR, "Failed to split pci devid and function\n"); - goto error; - } - *splitaddr.function++ = '\0'; - - /* now convert to int values */ - addr->domain = strtoul(splitaddr.domain, NULL, 16); - addr->bus = strtoul(splitaddr.bus, NULL, 16); - addr->devid = strtoul(splitaddr.devid, NULL, 16); - addr->function = strtoul(splitaddr.function, NULL, 10); - - free(buf_copy); /* free the copy made with strdup */ - return 0; - -error: - free(buf_copy); - return -1; -} - -/* Get max pci bus number from the corresponding pci bridge device */ -static int get_max_pci_bus_num(uint8_t start_bus, uint8_t *end_bus) -{ - char dirname[PATH_MAX]; - char filename[PATH_MAX]; - char cfgname[PATH_MAX]; - struct rte_pci_addr addr; - struct dirent *dp; - uint32_t pci_class_code; - uint8_t sec_bus_num, sub_bus_num; - DIR *dir; - int ret, fd; - - /* Initialize end bus number to zero */ - *end_bus = 0; - - /* Open pci devices directory */ - dir = opendir(rte_pci_get_sysfs_path()); - if (dir == NULL) { - PMD_DRV_LOG(ERR, "%s(): opendir failed\n", - __func__); - return -1; - } - - while ((dp = readdir(dir)) != NULL) { - if (dp->d_name[0] == '.') - continue; - - /* Split pci address to get bus, devid and function numbers */ - if (parse_pci_addr_format(dp->d_name, - sizeof(dp->d_name), &addr) != 0) - continue; - - snprintf(dirname, sizeof(dirname), "%s/%s", - rte_pci_get_sysfs_path(), dp->d_name); - - /* get class code */ - snprintf(filename, sizeof(filename), "%s/class", dirname); - if (parse_sysfs_value(filename, &pci_class_code) < 0) { - PMD_DRV_LOG(ERR, "Failed to get pci class code\n"); - goto error; - } - - /* Get max pci number from pci bridge device */ - if ((((pci_class_code >> PCI_CONFIG_CLASS_CODE_SHIFT) & 0xFF) == - PCI_CONFIG_BRIDGE_DEVICE)) { - snprintf(cfgname, sizeof(cfgname), - "%s/config", dirname); - fd = open(cfgname, O_RDWR); - if (fd < 0) { - PMD_DRV_LOG(ERR, "Failed to open %s\n", - cfgname); - goto error; - } - - /* get secondary bus number */ - ret = pread(fd, &sec_bus_num, sizeof(uint8_t), - PCI_SECONDARY_BUS); - if (ret == -1) { - PMD_DRV_LOG(ERR, "Failed to read secondary bus number\n"); - close(fd); - goto error; - } - - /* get subordinate bus number */ - ret = pread(fd, &sub_bus_num, sizeof(uint8_t), - PCI_SUBORDINATE_BUS); - if (ret == -1) { - PMD_DRV_LOG(ERR, "Failed to read subordinate bus number\n"); - close(fd); - goto error; - } - - /* Get max bus number by checking if given bus number - * falls in between secondary and subordinate bus - * numbers of this pci bridge device. - */ - if ((start_bus >= sec_bus_num) && - (start_bus <= sub_bus_num)) { - *end_bus = sub_bus_num; - close(fd); - closedir(dir); - return 0; - } - - close(fd); - } - } - -error: - closedir(dir); - return -1; -} - -/** - * DPDK callback to register a PCI device. - * - * This function creates an Ethernet device for each port of a given - * PCI device. - * - * @param[in] dev - * Pointer to Ethernet device structure. - * - * @return - * 0 on success, negative errno value on failure. - */ -int qdma_eth_dev_init(struct rte_eth_dev *dev) -{ - struct qdma_pci_dev *dma_priv; - uint8_t *baseaddr; - int i, idx, ret, qbase; - struct rte_pci_device *pci_dev; - uint16_t num_vfs; - uint8_t max_pci_bus = 0; - - /* sanity checks */ - if (dev == NULL) - return -EINVAL; - if (dev->data == NULL) - return -EINVAL; - if (dev->data->dev_private == NULL) - return -EINVAL; - - pci_dev = RTE_ETH_DEV_TO_PCI(dev); - if (pci_dev == NULL) - return -EINVAL; - - /* for secondary processes, we don't initialise any further as primary - * has already done this work. - */ - if (rte_eal_process_type() != RTE_PROC_PRIMARY) { - qdma_dev_ops_init(dev); - return 0; - } - - /* allocate space for a single Ethernet MAC address */ - dev->data->mac_addrs = rte_zmalloc("qdma", RTE_ETHER_ADDR_LEN * 1, 0); - if (dev->data->mac_addrs == NULL) - return -ENOMEM; - - /* Copy some dummy Ethernet MAC address for QDMA device - * This will change in real NIC device... - */ - for (i = 0; i < RTE_ETHER_ADDR_LEN; ++i) - dev->data->mac_addrs[0].addr_bytes[i] = 0x15 + i; - - /* Init system & device */ - dma_priv = (struct qdma_pci_dev *)dev->data->dev_private; - dma_priv->is_vf = 0; - dma_priv->is_master = 0; - dma_priv->vf_online_count = 0; - dma_priv->timer_count = DEFAULT_TIMER_CNT_TRIG_MODE_TIMER; - - dma_priv->en_desc_prefetch = 0; //Keep prefetch default to 0 - dma_priv->cmpt_desc_len = DEFAULT_QDMA_CMPT_DESC_LEN; - dma_priv->c2h_bypass_mode = RTE_PMD_QDMA_RX_BYPASS_NONE; - dma_priv->h2c_bypass_mode = 0; - - dma_priv->config_bar_idx = DEFAULT_PF_CONFIG_BAR; - dma_priv->bypass_bar_idx = BAR_ID_INVALID; - dma_priv->user_bar_idx = BAR_ID_INVALID; - - /* Check and handle device devargs*/ - if (qdma_check_kvargs(dev->device->devargs, dma_priv)) { - PMD_DRV_LOG(INFO, "devargs failed\n"); - rte_free(dev->data->mac_addrs); - return -EINVAL; - } - - /* Store BAR address and length of Config BAR */ - baseaddr = (uint8_t *) - pci_dev->mem_resource[dma_priv->config_bar_idx].addr; - dma_priv->bar_addr[dma_priv->config_bar_idx] = baseaddr; - - /*Assigning QDMA access layer function pointers based on the HW design*/ - dma_priv->hw_access = rte_zmalloc("hwaccess", - sizeof(struct qdma_hw_access), 0); - if (dma_priv->hw_access == NULL) { - rte_free(dev->data->mac_addrs); - return -ENOMEM; - } - idx = qdma_hw_access_init(dev, dma_priv->is_vf, dma_priv->hw_access); - if (idx < 0) { - rte_free(dma_priv->hw_access); - rte_free(dev->data->mac_addrs); - return -EINVAL; - } - - idx = qdma_get_hw_version(dev); - if (idx < 0) { - rte_free(dma_priv->hw_access); - rte_free(dev->data->mac_addrs); - return -EINVAL; - } - - idx = qdma_identify_bars(dev); - if (idx < 0) { - rte_free(dma_priv->hw_access); - rte_free(dev->data->mac_addrs); - return -EINVAL; - } - - /* Store BAR address and length of AXI Master Lite BAR(user bar) */ - if (dma_priv->user_bar_idx >= 0) { - baseaddr = (uint8_t *) - pci_dev->mem_resource[dma_priv->user_bar_idx].addr; - dma_priv->bar_addr[dma_priv->user_bar_idx] = baseaddr; - } - - PMD_DRV_LOG(INFO, "QDMA device driver probe:"); - - qdma_dev_ops_init(dev); - - /* Getting the device attributes from the Hardware */ - qdma_device_attributes_get(dev); - - /* Setting default Mode to RTE_PMD_QDMA_TRIG_MODE_USER_TIMER */ - dma_priv->trigger_mode = RTE_PMD_QDMA_TRIG_MODE_USER_TIMER; - - /* Create master resource node for queue management on the given - * bus number. Node will be created only once per bus number. - */ - qbase = DEFAULT_QUEUE_BASE; - - ret = get_max_pci_bus_num(pci_dev->addr.bus, &max_pci_bus); - if ((ret != QDMA_SUCCESS) && !max_pci_bus) { - PMD_DRV_LOG(ERR, "Failed to get max pci bus number\n"); - rte_free(dma_priv->hw_access); - rte_free(dev->data->mac_addrs); - return -EINVAL; - } - PMD_DRV_LOG(INFO, "PCI max bus number : 0x%x", max_pci_bus); - - ret = qdma_master_resource_create(pci_dev->addr.bus, max_pci_bus, - qbase, dma_priv->dev_cap.num_qs, - &dma_priv->dma_device_index); - if (ret == -QDMA_ERR_NO_MEM) { - rte_free(dma_priv->hw_access); - rte_free(dev->data->mac_addrs); - return -ENOMEM; - } - - dma_priv->hw_access->qdma_get_function_number(dev, - &dma_priv->func_id); - PMD_DRV_LOG(INFO, "PF function ID: %d", dma_priv->func_id); - - /* CSR programming is done once per given board or bus number, - * done by the master PF - */ - if (ret == QDMA_SUCCESS) { - RTE_LOG(INFO, PMD, "QDMA PMD VERSION: %s\n", QDMA_PMD_VERSION); - dma_priv->hw_access->qdma_set_default_global_csr(dev); - for (i = 0; i < dma_priv->dev_cap.mm_channel_max; i++) { - if (dma_priv->dev_cap.mm_en) { - /* Enable MM C2H Channel */ - dma_priv->hw_access->qdma_mm_channel_conf(dev, - i, 1, 1); - /* Enable MM H2C Channel */ - dma_priv->hw_access->qdma_mm_channel_conf(dev, - i, 0, 1); - } else { - /* Disable MM C2H Channel */ - dma_priv->hw_access->qdma_mm_channel_conf(dev, - i, 1, 0); - /* Disable MM H2C Channel */ - dma_priv->hw_access->qdma_mm_channel_conf(dev, - i, 0, 0); - } - } - - ret = dma_priv->hw_access->qdma_init_ctxt_memory(dev); - if (ret < 0) { - PMD_DRV_LOG(ERR, - "%s: Failed to initialize ctxt memory, err = %d\n", - __func__, ret); - return -EINVAL; - } - -#ifdef TANDEM_BOOT_SUPPORTED - if (dma_priv->en_st_mode) { - ret = dma_priv->hw_access->qdma_init_st_ctxt(dev); - if (ret < 0) { - PMD_DRV_LOG(ERR, - "%s: Failed to initialize st ctxt memory, err = %d\n", - __func__, ret); - return -EINVAL; - } - } -#endif - dma_priv->hw_access->qdma_hw_error_enable(dev, - dma_priv->hw_access->qdma_max_errors); - if (ret < 0) { - PMD_DRV_LOG(ERR, - "%s: Failed to enable hw errors, err = %d\n", - __func__, ret); - return -EINVAL; - } - - rte_eal_alarm_set(QDMA_ERROR_POLL_FRQ, qdma_check_errors, - (void *)dev); - dma_priv->is_master = 1; - } - - /* - * Create an entry for the device in board list if not already - * created - */ - ret = qdma_dev_entry_create(dma_priv->dma_device_index, - dma_priv->func_id); - if ((ret != QDMA_SUCCESS) && - (ret != -QDMA_ERR_RM_DEV_EXISTS)) { - PMD_DRV_LOG(ERR, "PF-%d(DEVFN) qdma_dev_entry_create failed: %d\n", - dma_priv->func_id, ret); - rte_free(dma_priv->hw_access); - rte_free(dev->data->mac_addrs); - return -ENOMEM; - } - - pcie_perf_enable(pci_dev); - if (dma_priv->dev_cap.mailbox_en && pci_dev->max_vfs) - qdma_mbox_init(dev); - - if (!dma_priv->reset_in_progress) { - num_vfs = pci_dev->max_vfs; - if (num_vfs) { - dma_priv->vfinfo = rte_zmalloc("vfinfo", - sizeof(struct qdma_vf_info) * num_vfs, 0); - if (dma_priv->vfinfo == NULL) - rte_panic("Cannot allocate memory for private VF info\n"); - - /* Mark all VFs with invalid function id mapping*/ - for (i = 0; i < num_vfs; i++) - dma_priv->vfinfo[i].func_id = - QDMA_FUNC_ID_INVALID; - } - } - -#ifdef LATENCY_MEASUREMENT - /* Create txq and rxq latency measurement shared memory - * if not already created by the VF - */ - if (!h2c_pidx_to_hw_cidx_lat) { - /* Create a shared memory zone for the txq latency buffer */ - txq_lat_buf_mz = rte_memzone_reserve("TXQ_LAT_BUFFER_ZONE", - LATENCY_MAX_QUEUES * LATENCY_CNT * sizeof(double), - rte_socket_id(), 0); - if (txq_lat_buf_mz == NULL) { - PMD_DRV_LOG(ERR, - "Failed to allocate txq latency buffer memzone\n"); - return -1; - } - - /* Get the virtual address of the txq latency buffer */ - h2c_pidx_to_hw_cidx_lat = - (double(*)[LATENCY_CNT])txq_lat_buf_mz->addr; - } - - if (!c2h_pidx_to_cmpt_pidx_lat) { - /* Create a shared memory zone for the rxq latency buffer */ - rxq_lat_buf_mz = rte_memzone_reserve("RXQ_LAT_BUFFER_ZONE", - LATENCY_MAX_QUEUES * LATENCY_CNT * sizeof(double), - rte_socket_id(), 0); - if (rxq_lat_buf_mz == NULL) { - PMD_DRV_LOG(ERR, - "Failed to allocate rxq latency buffer memzone\n"); - return -1; - } - - /* Get the virtual address of the rxq latency buffer */ - c2h_pidx_to_cmpt_pidx_lat = - (double(*)[LATENCY_CNT])rxq_lat_buf_mz->addr; - } -#endif - - dma_priv->reset_in_progress = 0; - - return 0; -} - -/** - * DPDK callback to deregister PCI device. - * - * @param[in] dev - * Pointer to Ethernet device structure. - * - * @return - * 0 on success, negative errno value on failure. - */ -int qdma_eth_dev_uninit(struct rte_eth_dev *dev) -{ - struct qdma_pci_dev *qdma_dev = dev->data->dev_private; - struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); - struct qdma_mbox_msg *m = NULL; - int i, rv; - - /* only uninitialize in the primary process */ - if (rte_eal_process_type() != RTE_PROC_PRIMARY) - return -EPERM; - - if (qdma_dev->vf_online_count) { - for (i = 0; i < pci_dev->max_vfs; i++) { - if (qdma_dev->vfinfo[i].func_id == QDMA_FUNC_ID_INVALID) - continue; - - m = qdma_mbox_msg_alloc(); - if (!m) - return -ENOMEM; - - if (!qdma_dev->reset_in_progress) - qdma_mbox_compose_pf_offline(m->raw_data, - qdma_dev->func_id, - qdma_dev->vfinfo[i].func_id); - else - qdma_mbox_compose_vf_reset_message(m->raw_data, - qdma_dev->func_id, - qdma_dev->vfinfo[i].func_id); - rv = qdma_mbox_msg_send(dev, m, 0); - if (rv < 0) - PMD_DRV_LOG(ERR, "Send bye failed from PF:%d to VF:%d\n", - qdma_dev->func_id, - qdma_dev->vfinfo[i].func_id); - } - - PMD_DRV_LOG(INFO, - "%s: Wait till all VFs shutdown for PF-%d(DEVFN)\n", - __func__, qdma_dev->func_id); - - i = 0; - while (i < SHUTDOWN_TIMEOUT) { - if (!qdma_dev->vf_online_count) { - PMD_DRV_LOG(INFO, - "%s: VFs shutdown completed for PF-%d(DEVFN)\n", - __func__, qdma_dev->func_id); - break; - } - rte_delay_ms(1); - i++; - } - - if (i >= SHUTDOWN_TIMEOUT) { - PMD_DRV_LOG(ERR, "%s: Failed VFs shutdown for PF-%d(DEVFN)\n", - __func__, qdma_dev->func_id); - } - } - - if (qdma_dev->dev_configured) - qdma_dev_close(dev); - - if (qdma_dev->dev_cap.mailbox_en && pci_dev->max_vfs) - qdma_mbox_uninit(dev); - - /* cancel pending polls*/ - if (qdma_dev->is_master) - rte_eal_alarm_cancel(qdma_check_errors, (void *)dev); - - /* Remove the device node from the board list */ - qdma_dev_entry_destroy(qdma_dev->dma_device_index, - qdma_dev->func_id); - qdma_master_resource_destroy(qdma_dev->dma_device_index); - - dev->dev_ops = NULL; - dev->rx_pkt_burst = NULL; - dev->tx_pkt_burst = NULL; - dev->data->nb_rx_queues = 0; - dev->data->nb_tx_queues = 0; - - if (!qdma_dev->reset_in_progress && - qdma_dev->vfinfo != NULL) { - rte_free(qdma_dev->vfinfo); - qdma_dev->vfinfo = NULL; - } - - if (dev->data->mac_addrs != NULL) { - rte_free(dev->data->mac_addrs); - dev->data->mac_addrs = NULL; - } - - if (qdma_dev->q_info != NULL) { - rte_free(qdma_dev->q_info); - qdma_dev->q_info = NULL; - } - - if (qdma_dev->hw_access != NULL) { - rte_free(qdma_dev->hw_access); - qdma_dev->hw_access = NULL; - } - -#ifdef LATENCY_MEASUREMENT - rte_memzone_free(txq_lat_buf_mz); - rte_memzone_free(rxq_lat_buf_mz); -#endif - - return 0; -} - -static int eth_qdma_pci_probe(struct rte_pci_driver *pci_drv __rte_unused, - struct rte_pci_device *pci_dev) -{ - return rte_eth_dev_pci_generic_probe(pci_dev, - sizeof(struct qdma_pci_dev), - qdma_eth_dev_init); -} - -/* Detach a ethdev interface */ -static int eth_qdma_pci_remove(struct rte_pci_device *pci_dev) -{ - return rte_eth_dev_pci_generic_remove(pci_dev, qdma_eth_dev_uninit); -} - -static struct rte_pci_driver rte_qdma_pmd = { - .id_table = qdma_pci_id_tbl, - .drv_flags = RTE_PCI_DRV_NEED_MAPPING, - .probe = eth_qdma_pci_probe, - .remove = eth_qdma_pci_remove, -}; - -bool -is_pf_device_supported(struct rte_eth_dev *dev) -{ - if (strcmp(dev->device->driver->name, rte_qdma_pmd.driver.name)) - return false; - - return true; -} - -bool is_qdma_supported(struct rte_eth_dev *dev) -{ - bool is_pf, is_vf; - - is_pf = is_pf_device_supported(dev); - is_vf = is_vf_device_supported(dev); - - if (!is_pf && !is_vf) - return false; - - return true; -} - -RTE_PMD_REGISTER_PCI(net_qdma, rte_qdma_pmd); -RTE_PMD_REGISTER_PCI_TABLE(net_qdma, qdma_pci_id_tbl); diff --git a/QDMA/DPDK/drivers/net/qdma/qdma_log.h b/QDMA/DPDK/drivers/net/qdma/qdma_log.h deleted file mode 100755 index 6851db755..000000000 --- a/QDMA/DPDK/drivers/net/qdma/qdma_log.h +++ /dev/null @@ -1,47 +0,0 @@ -/*- - * BSD LICENSE - * - * Copyright (c) 2019-2022 Xilinx, Inc. All rights reserved. - * Copyright (c) 2022-2023, Advanced Micro Devices, Inc. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * * Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#ifndef __QDMA_LOG_H__ -#define __QDMA_LOG_H__ - -#include - -#ifdef RTE_LIBRTE_QDMA_DEBUG_DRIVER -#define PMD_DRV_LOG(level, fmt, args...) \ - RTE_LOG(level, PMD, "%s(): " fmt "\n", __func__, ## args) -#else -#define PMD_DRV_LOG(level, fmt, args...) do { } while (0) -#endif - - -#endif /* ifndef __QDMA_LOG_H__ */ diff --git a/QDMA/DPDK/drivers/net/qdma/qdma_mbox.c b/QDMA/DPDK/drivers/net/qdma/qdma_mbox.c deleted file mode 100755 index e1cd2a5ee..000000000 --- a/QDMA/DPDK/drivers/net/qdma/qdma_mbox.c +++ /dev/null @@ -1,424 +0,0 @@ -/*- - * BSD LICENSE - * - * Copyright (c) 2019-2022 Xilinx, Inc. All rights reserved. - * Copyright (c) 2022-2023, Advanced Micro Devices, Inc. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * * Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include "qdma.h" -#include "qdma_mbox.h" -#include -#include -#include - -/* - * Get index from VF info array of PF device for a given VF funcion id. - */ -static int qdma_get_internal_vf_index(struct rte_eth_dev *dev, uint8_t devfn) -{ - struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); - struct qdma_pci_dev *qdma_dev = dev->data->dev_private; - uint16_t i; - - for (i = 0; i < pci_dev->max_vfs; i++) { - if (qdma_dev->vfinfo[i].func_id == devfn) - return i; - } - - return QDMA_FUNC_ID_INVALID; -} - -static void qdma_mbox_process_msg_from_vf(void *arg) -{ - struct qdma_mbox_msg *mbox_msg_rsp = qdma_mbox_msg_alloc(); - struct rte_eth_dev *dev = (struct rte_eth_dev *)arg; - struct qdma_pci_dev *qdma_dev = dev->data->dev_private; - struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); - uint16_t vf_func_id; - uint16_t vf_index; - int i, rv; - - if (mbox_msg_rsp == NULL) - return; - - if (!qdma_dev) - return; - - rv = qdma_mbox_pf_rcv_msg_handler(dev, - qdma_dev->dma_device_index, - qdma_dev->func_id, - qdma_dev->mbox.rx_data, - mbox_msg_rsp->raw_data); - if (rv != QDMA_MBOX_VF_OFFLINE && - rv != QDMA_MBOX_VF_RESET && - rv != QDMA_MBOX_PF_RESET_DONE && - rv != QDMA_MBOX_PF_BYE) - qdma_mbox_msg_send(dev, mbox_msg_rsp, 0); - else - qdma_mbox_msg_free(mbox_msg_rsp); - - if (rv == QDMA_MBOX_VF_ONLINE) { - vf_func_id = qdma_mbox_vf_func_id_get(qdma_dev->mbox.rx_data, - qdma_dev->is_vf); - /* Mapping internal VF function id to a valid VF function id */ - for (i = 0; i < pci_dev->max_vfs; i++) { - if (qdma_dev->vfinfo[i].func_id == - QDMA_FUNC_ID_INVALID) { - qdma_dev->vfinfo[i].func_id = - vf_func_id; - break; - } - } - - if (i == pci_dev->max_vfs) { - PMD_DRV_LOG(INFO, "PF-%d failed to create function id mapping VF func_id%d", - qdma_dev->func_id, vf_func_id); - return; - } - - qdma_dev->vf_online_count++; - } else if (rv == QDMA_MBOX_VF_OFFLINE) { - if (!qdma_dev->reset_in_progress) { - vf_func_id = - qdma_mbox_vf_func_id_get(qdma_dev->mbox.rx_data, - qdma_dev->is_vf); - vf_index = qdma_get_internal_vf_index(dev, vf_func_id); - if (vf_index != QDMA_FUNC_ID_INVALID) - qdma_dev->vfinfo[vf_index].func_id = - QDMA_FUNC_ID_INVALID; - } - qdma_dev->vf_online_count--; - } -} - -static void *qdma_reset_task(void *arg) -{ - struct rte_eth_dev *dev = (struct rte_eth_dev *)arg; - struct qdma_pci_dev *qdma_dev = dev->data->dev_private; - - if (!qdma_dev) - return NULL; - - rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_RESET, - NULL); - - return NULL; -} - -static void *qdma_remove_task(void *arg) -{ - struct rte_eth_dev *dev = (struct rte_eth_dev *)arg; - struct qdma_pci_dev *qdma_dev = dev->data->dev_private; - - if (!qdma_dev) - return NULL; - - rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_RMV, - NULL); - - return NULL; -} - -static void qdma_mbox_process_msg_from_pf(void *arg) -{ - struct qdma_mbox_msg *mbox_msg_rsp = NULL; - struct rte_eth_dev *dev = (struct rte_eth_dev *)arg; - struct qdma_pci_dev *qdma_dev = dev->data->dev_private; - pthread_t thread; - pthread_attr_t tattr; - int rv; - - if (!qdma_dev) - return; - - mbox_msg_rsp = qdma_mbox_msg_alloc(); - if (!mbox_msg_rsp) - return; - - rv = qdma_mbox_vf_rcv_msg_handler(qdma_dev->mbox.rx_data, - mbox_msg_rsp->raw_data); - if (rv) - qdma_mbox_msg_send(dev, mbox_msg_rsp, 0); - else { - qdma_mbox_msg_free(mbox_msg_rsp); - return; - } - - if (rv == QDMA_MBOX_VF_RESET) { - qdma_dev->reset_state = RESET_STATE_RECV_PF_RESET_REQ; - - rv = pthread_attr_init(&tattr); - if (rv) - PMD_DRV_LOG(ERR, - "Failed pthread_attr_init for PF reset\n"); - - rv = pthread_attr_setdetachstate(&tattr, - PTHREAD_CREATE_DETACHED); - if (rv) - PMD_DRV_LOG(ERR, - "Failed pthread_attr_setdetachstate for PF reset\n"); - - if (pthread_create(&thread, NULL, - qdma_reset_task, (void *)dev)) { - PMD_DRV_LOG(ERR, "Could not create qdma reset" - " starter thread\n"); - } - } else if (rv == QDMA_MBOX_PF_RESET_DONE) { - qdma_dev->reset_state = RESET_STATE_RECV_PF_RESET_DONE; - } else if (rv == QDMA_MBOX_PF_BYE) { - rv = pthread_attr_init(&tattr); - if (rv) - PMD_DRV_LOG(ERR, - "Failed pthread_attr_init for PF shutdown\n"); - - rv = pthread_attr_setdetachstate(&tattr, - PTHREAD_CREATE_DETACHED); - if (rv) - PMD_DRV_LOG(ERR, - "Failed pthread_attr_setdetachstate for PF shutdown\n"); - - if (pthread_create(&thread, NULL, - qdma_remove_task, (void *)dev)) { - PMD_DRV_LOG(ERR, - "Could not create qdma remove" - " starter thread\n"); - } - } -} - -static void qdma_mbox_process_rsp_from_pf(void *arg) -{ - struct rte_eth_dev *dev = (struct rte_eth_dev *)arg; - struct qdma_pci_dev *qdma_dev = dev->data->dev_private; - struct qdma_list_head *entry = NULL; - struct qdma_list_head *tmp = NULL; - - if (!qdma_dev) - return; - - if ((qdma_dev->is_vf) && (qdma_dev->func_id == 0)) { - qdma_dev->func_id = - qdma_mbox_vf_func_id_get(qdma_dev->mbox.rx_data, - qdma_dev->is_vf); - PMD_DRV_LOG(INFO, "VF function ID: %d", qdma_dev->func_id); - } - - rte_spinlock_lock(&qdma_dev->mbox.list_lock); - qdma_list_for_each_safe(entry, tmp, - &qdma_dev->mbox.rx_pend_list) { - struct qdma_mbox_msg *msg = QDMA_LIST_GET_DATA(entry); - - if (qdma_mbox_is_msg_response(msg->raw_data, - qdma_dev->mbox.rx_data)) { - /* copy response message back to tx buffer */ - memcpy(msg->raw_data, qdma_dev->mbox.rx_data, - MBOX_MSG_REG_MAX * sizeof(uint32_t)); - msg->rsp_rcvd = 1; - qdma_list_del(entry); - break; - } - } - rte_spinlock_unlock(&qdma_dev->mbox.list_lock); -} - -static void qdma_mbox_rcv_task(void *arg) -{ - struct rte_eth_dev *dev = (struct rte_eth_dev *)arg; - struct qdma_pci_dev *qdma_dev = dev->data->dev_private; - int rv; - - if (!qdma_dev) - return; - - do { - memset(qdma_dev->mbox.rx_data, 0, - MBOX_MSG_REG_MAX * sizeof(uint32_t)); - rv = qdma_mbox_rcv(dev, qdma_dev->is_vf, - qdma_dev->mbox.rx_data); - if (rv < 0) - break; - if (qdma_dev->is_vf) { - qdma_mbox_process_msg_from_pf(arg); - qdma_mbox_process_rsp_from_pf(arg); - } else - qdma_mbox_process_msg_from_vf(arg); - - } while (1); - - if (!qdma_dev->dev_cap.mailbox_intr) - rte_eal_alarm_set(MBOX_POLL_FRQ, qdma_mbox_rcv_task, arg); -} - -static void qdma_mbox_send_task(void *arg) -{ - struct rte_eth_dev *dev = (struct rte_eth_dev *)arg; - struct qdma_pci_dev *qdma_dev = dev->data->dev_private; - struct qdma_list_head *entry = NULL; - struct qdma_list_head *tmp = NULL; - int rv; - - rte_spinlock_lock(&qdma_dev->mbox.list_lock); - qdma_list_for_each_safe(entry, tmp, &qdma_dev->mbox.tx_todo_list) { - struct qdma_mbox_msg *msg = QDMA_LIST_GET_DATA(entry); - - rv = qdma_mbox_send(dev, qdma_dev->is_vf, msg->raw_data); - if (rv < 0) { - msg->retry_cnt--; - if (!msg->retry_cnt) { - qdma_list_del(entry); - if (msg->rsp_wait == QDMA_MBOX_RSP_NO_WAIT) - qdma_mbox_msg_free(msg); - } - } else { - qdma_list_del(entry); - if (msg->rsp_wait == QDMA_MBOX_RSP_WAIT) - qdma_list_add_tail(entry, - &qdma_dev->mbox.rx_pend_list); - else - qdma_mbox_msg_free(msg); - } - } - if (!qdma_list_is_empty(&qdma_dev->mbox.tx_todo_list)) - rte_eal_alarm_set(MBOX_POLL_FRQ, qdma_mbox_send_task, arg); - rte_spinlock_unlock(&qdma_dev->mbox.list_lock); -} - -int qdma_mbox_msg_send(struct rte_eth_dev *dev, struct qdma_mbox_msg *msg, - unsigned int timeout_ms) -{ - struct qdma_pci_dev *qdma_dev = dev->data->dev_private; - - if (!msg) - return -EINVAL; - - msg->retry_cnt = timeout_ms ? ((timeout_ms / MBOX_POLL_FRQ) + 1) : - MBOX_SEND_RETRY_COUNT; - QDMA_LIST_SET_DATA(&msg->node, msg); - - rte_spinlock_lock(&qdma_dev->mbox.list_lock); - qdma_list_add_tail(&msg->node, &qdma_dev->mbox.tx_todo_list); - rte_spinlock_unlock(&qdma_dev->mbox.list_lock); - - msg->rsp_wait = (!timeout_ms) ? QDMA_MBOX_RSP_NO_WAIT : - QDMA_MBOX_RSP_WAIT; - rte_eal_alarm_set(MBOX_POLL_FRQ, qdma_mbox_send_task, dev); - - if (!timeout_ms) - return 0; - - /* if code reached here, caller should free the buffer */ - while (msg->retry_cnt && !msg->rsp_rcvd) - rte_delay_ms(1); - - if (!msg->rsp_rcvd) - return -EPIPE; - - return 0; -} - -void *qdma_mbox_msg_alloc(void) -{ - return rte_zmalloc(NULL, sizeof(struct qdma_mbox_msg), 0); -} - -void qdma_mbox_msg_free(void *buffer) -{ - rte_free(buffer); -} - -int qdma_mbox_init(struct rte_eth_dev *dev) -{ - struct qdma_pci_dev *qdma_dev = dev->data->dev_private; - struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); - uint32_t raw_data[MBOX_MSG_REG_MAX] = {0}; - struct rte_intr_handle *intr_handle = pci_dev_intr_handle; - - if (!qdma_dev->is_vf) { - int i; - - for (i = 0; i < pci_dev->max_vfs; i++) - qdma_mbox_rcv(dev, 0, raw_data); - } else - qdma_mbox_rcv(dev, 1, raw_data); - - qdma_mbox_hw_init(dev, qdma_dev->is_vf); - qdma_list_init_head(&qdma_dev->mbox.tx_todo_list); - qdma_list_init_head(&qdma_dev->mbox.rx_pend_list); - rte_spinlock_init(&qdma_dev->mbox.list_lock); - - if (qdma_dev->dev_cap.mailbox_intr) { - /* Register interrupt call back handler */ - rte_intr_callback_register(intr_handle, - qdma_mbox_rcv_task, dev); - - /* enable uio/vfio intr/eventfd mapping */ - rte_intr_enable(intr_handle); - - /* enable qdma mailbox interrupt */ - qdma_mbox_enable_interrupts((void *)dev, qdma_dev->is_vf); - } else { - rte_eal_alarm_set(MBOX_POLL_FRQ, qdma_mbox_rcv_task, - (void *)dev); - } - - return 0; -} - -void qdma_mbox_uninit(struct rte_eth_dev *dev) -{ - struct qdma_pci_dev *qdma_dev = dev->data->dev_private; - struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); - struct rte_intr_handle *intr_handle = pci_dev_intr_handle; - - do { - rte_spinlock_lock(&qdma_dev->mbox.list_lock); - if (!qdma_list_is_empty(&qdma_dev->mbox.tx_todo_list)) { - rte_spinlock_unlock(&qdma_dev->mbox.list_lock); - rte_delay_ms(100); - continue; - } - rte_spinlock_unlock(&qdma_dev->mbox.list_lock); - break; - } while (1); - - rte_eal_alarm_cancel(qdma_mbox_send_task, (void *)dev); - if (qdma_dev->dev_cap.mailbox_intr) { - /* Disable the mailbox interrupt */ - qdma_mbox_disable_interrupts((void *)dev, qdma_dev->is_vf); - - /* Disable uio intr before callback unregister */ - rte_intr_disable(intr_handle); - - rte_intr_callback_unregister(intr_handle, - qdma_mbox_rcv_task, dev); - } else { - rte_eal_alarm_cancel(qdma_mbox_rcv_task, (void *)dev); - } -} - diff --git a/QDMA/DPDK/drivers/net/qdma/qdma_mbox.h b/QDMA/DPDK/drivers/net/qdma/qdma_mbox.h deleted file mode 100755 index d861342ff..000000000 --- a/QDMA/DPDK/drivers/net/qdma/qdma_mbox.h +++ /dev/null @@ -1,75 +0,0 @@ -/*- - * BSD LICENSE - * - * Copyright (c) 2019-2022 Xilinx, Inc. All rights reserved. - * Copyright (c) 2022-2023, Advanced Micro Devices, Inc. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * * Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -#ifndef QDMA_DPDK_MBOX_H_ -#define QDMA_DPDK_MBOX_H_ - -#include "qdma_list.h" -#include "qdma_mbox_protocol.h" -#include - -#define MBOX_POLL_FRQ 1000 -#define MBOX_OP_RSP_TIMEOUT (10000 * MBOX_POLL_FRQ) /* 10 sec */ -#define MBOX_SEND_RETRY_COUNT (MBOX_OP_RSP_TIMEOUT/MBOX_POLL_FRQ) - -enum qdma_mbox_rsp_state { - QDMA_MBOX_RSP_NO_WAIT, - QDMA_MBOX_RSP_WAIT -}; - -struct qdma_dev_mbox { - struct qdma_list_head tx_todo_list; - struct qdma_list_head rx_pend_list; - rte_spinlock_t list_lock; - uint32_t rx_data[MBOX_MSG_REG_MAX]; -}; - -struct qdma_mbox_msg { - uint8_t rsp_rcvd; - uint32_t retry_cnt; - enum qdma_mbox_rsp_state rsp_wait; - uint32_t raw_data[MBOX_MSG_REG_MAX]; - struct qdma_list_head node; -}; - -int qdma_mbox_init(struct rte_eth_dev *dev); -void qdma_mbox_uninit(struct rte_eth_dev *dev); -void *qdma_mbox_msg_alloc(void); -void qdma_mbox_msg_free(void *buffer); -int qdma_mbox_msg_send(struct rte_eth_dev *dev, struct qdma_mbox_msg *msg, - unsigned int timeout_ms); -int qdma_dev_notify_qadd(struct rte_eth_dev *dev, uint32_t qidx_hw, - enum qdma_dev_q_type q_type); -int qdma_dev_notify_qdel(struct rte_eth_dev *dev, uint32_t qidx_hw, - enum qdma_dev_q_type q_type); - -#endif /* QDMA_DPDK_MBOX_H_ */ diff --git a/QDMA/DPDK/drivers/net/qdma/qdma_platform.c b/QDMA/DPDK/drivers/net/qdma/qdma_platform.c deleted file mode 100755 index 9abe8f65c..000000000 --- a/QDMA/DPDK/drivers/net/qdma/qdma_platform.c +++ /dev/null @@ -1,264 +0,0 @@ -/*- - * BSD LICENSE - * - * Copyright (c) 2019-2022 Xilinx, Inc. All rights reserved. - * Copyright (c) 2022-2023, Advanced Micro Devices, Inc. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * * Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include "qdma_access_common.h" -#include "qdma_platform.h" -#include "rte_pmd_qdma.h" -#include "qdma.h" -#include -#include - -static rte_spinlock_t resource_lock = RTE_SPINLOCK_INITIALIZER; -static rte_spinlock_t reg_access_lock = RTE_SPINLOCK_INITIALIZER; - -struct err_code_map error_code_map_list[] = { - {QDMA_SUCCESS, 0}, - {QDMA_ERR_INV_PARAM, EINVAL}, - {QDMA_ERR_NO_MEM, ENOMEM}, - {QDMA_ERR_HWACC_BUSY_TIMEOUT, EBUSY}, - {QDMA_ERR_HWACC_INV_CONFIG_BAR, EINVAL}, - {QDMA_ERR_HWACC_NO_PEND_LEGCY_INTR, EINVAL}, - {QDMA_ERR_HWACC_BAR_NOT_FOUND, EINVAL}, - {QDMA_ERR_HWACC_FEATURE_NOT_SUPPORTED, EINVAL}, - {QDMA_ERR_RM_RES_EXISTS, EPERM}, - {QDMA_ERR_RM_RES_NOT_EXISTS, EINVAL}, - {QDMA_ERR_RM_DEV_EXISTS, EPERM}, - {QDMA_ERR_RM_DEV_NOT_EXISTS, EINVAL}, - {QDMA_ERR_RM_NO_QUEUES_LEFT, EPERM}, - {QDMA_ERR_RM_QMAX_CONF_REJECTED, EPERM}, - {QDMA_ERR_MBOX_FMAP_WR_FAILED, EIO}, - {QDMA_ERR_MBOX_NUM_QUEUES, EINVAL}, - {QDMA_ERR_MBOX_INV_QID, EINVAL}, - {QDMA_ERR_MBOX_INV_RINGSZ, EINVAL}, - {QDMA_ERR_MBOX_INV_BUFSZ, EINVAL}, - {QDMA_ERR_MBOX_INV_CNTR_TH, EINVAL}, - {QDMA_ERR_MBOX_INV_TMR_TH, EINVAL}, - {QDMA_ERR_MBOX_INV_MSG, EINVAL}, - {QDMA_ERR_MBOX_SEND_BUSY, EBUSY}, - {QDMA_ERR_MBOX_NO_MSG_IN, EINVAL}, - {QDMA_ERR_MBOX_ALL_ZERO_MSG, EINVAL}, -}; - -/*****************************************************************************/ -/** - * qdma_calloc(): allocate memory and initialize with 0 - * - * @num_blocks: number of blocks of contiguous memory of @size - * @size: size of each chunk of memory - * - * Return: pointer to the memory block created on success and NULL on failure - *****************************************************************************/ -void *qdma_calloc(uint32_t num_blocks, uint32_t size) -{ - return rte_calloc(NULL, num_blocks, size, 0); -} - -/*****************************************************************************/ -/** - * qdma_memfree(): free the memory - * - * @memptr: pointer to the memory block - * - * Return: None - *****************************************************************************/ -void qdma_memfree(void *memptr) -{ - return rte_free(memptr); -} - -/*****************************************************************************/ -/** - * qdma_resource_lock_take() - take lock to access resource management APIs - * - * @return None - *****************************************************************************/ -void qdma_resource_lock_take(void) -{ - rte_spinlock_lock(&resource_lock); -} - -/*****************************************************************************/ -/** - * qdma_resource_lock_give() - release lock after accessing - * resource management APIs - * - * @return None - *****************************************************************************/ -void qdma_resource_lock_give(void) -{ - rte_spinlock_unlock(&resource_lock); -} - -/*****************************************************************************/ -/** - * qdma_reg_write() - Register write API. - * - * @dev_hndl: device handle - * @reg_offst: QDMA Config bar register offset to write - * @val: value to be written - * - * Return: None - *****************************************************************************/ -void qdma_reg_write(void *dev_hndl, uint32_t reg_offst, uint32_t val) -{ - struct qdma_pci_dev *qdma_dev; - uint64_t bar_addr; - - qdma_dev = ((struct rte_eth_dev *)dev_hndl)->data->dev_private; - bar_addr = (uint64_t)qdma_dev->bar_addr[qdma_dev->config_bar_idx]; - *((volatile uint32_t *)(bar_addr + reg_offst)) = val; -} - -/*****************************************************************************/ -/** - * qdma_reg_read() - Register read API. - * - * @dev_hndl: device handle - * @reg_offst: QDMA Config bar register offset to be read - * - * Return: Value read - *****************************************************************************/ -uint32_t qdma_reg_read(void *dev_hndl, uint32_t reg_offst) -{ - struct qdma_pci_dev *qdma_dev; - uint64_t bar_addr; - uint32_t val; - - qdma_dev = ((struct rte_eth_dev *)dev_hndl)->data->dev_private; - bar_addr = (uint64_t)qdma_dev->bar_addr[qdma_dev->config_bar_idx]; - val = *((volatile uint32_t *)(bar_addr + reg_offst)); - - return val; -} - -/*****************************************************************************/ -/** - * qdma_reg_access_lock() - Lock function for Register access - * - * @dev_hndl: device handle - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -int qdma_reg_access_lock(void *dev_hndl) -{ - (void) dev_hndl; - rte_spinlock_lock(®_access_lock); - return 0; -} - -/*****************************************************************************/ -/** - * qdma_reg_access_release() - Release function for Register access - * - * @dev_hndl: device handle - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -int qdma_reg_access_release(void *dev_hndl) -{ - (void) dev_hndl; - rte_spinlock_unlock(®_access_lock); - return 0; -} - -/*****************************************************************************/ -/** - * qdma_udelay() - delay function to be used in the common library - * - * @delay_usec: delay in microseconds - * - * Return: None - *****************************************************************************/ -void qdma_udelay(uint32_t delay_usec) -{ - rte_delay_us(delay_usec); -} - -/*****************************************************************************/ -/** - * qdma_get_hw_access() - function to get the qdma_hw_access - * - * @dev_hndl: device handle - * @dev_cap: pointer to hold qdma_hw_access structure - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -void qdma_get_hw_access(void *dev_hndl, struct qdma_hw_access **hw) -{ - struct qdma_pci_dev *qdma_dev; - qdma_dev = ((struct rte_eth_dev *)dev_hndl)->data->dev_private; - *hw = qdma_dev->hw_access; -} - -/*****************************************************************************/ -/** - * qdma_strncpy(): copy n size string from source to destination buffer - * - * @memptr: pointer to the memory block - * - * Return: None - *****************************************************************************/ -void qdma_strncpy(char *dest, const char *src, size_t n) -{ - strncpy(dest, src, n); -} - -/*****************************************************************************/ -/** - * qdma_get_err_code() - function to get the qdma access mapped error code - * - * @acc_err_code: qdma access error code which is a negative input value - * - * Return: returns the platform specific error code - *****************************************************************************/ -int qdma_get_err_code(int acc_err_code) -{ - /* Multiply acc_err_code with -1 to convert it to a postive number - * and use it as an array index for error codes. - */ - acc_err_code *= -1; - - return -(error_code_map_list[acc_err_code].err_code); -} - -/*****************************************************************************/ -/** - * qdma_io_wmb() - Write memory barrier for IO device - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -int qdma_io_wmb(void) -{ - rte_io_wmb(); - return 0; -} diff --git a/QDMA/DPDK/drivers/net/qdma/qdma_platform_env.h b/QDMA/DPDK/drivers/net/qdma/qdma_platform_env.h deleted file mode 100755 index 69d5e5919..000000000 --- a/QDMA/DPDK/drivers/net/qdma/qdma_platform_env.h +++ /dev/null @@ -1,61 +0,0 @@ -/*- - * BSD LICENSE - * - * Copyright (c) 2019-2022 Xilinx, Inc. All rights reserved. - * Copyright (c) 2022-2023, Advanced Micro Devices, Inc. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * * Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#ifndef QDMA_PLATFORM_ENV_H_ -#define QDMA_PLATFORM_ENV_H_ - -#include -#include -#include -#include - -#define QDMA_SNPRINTF_S(arg1, arg2, arg3, ...) \ - snprintf(arg1, arg3, ##__VA_ARGS__) - -#ifdef RTE_LIBRTE_QDMA_DEBUG_DRIVER -#define qdma_log_info(x_, ...) rte_log(RTE_LOG_INFO,\ - RTE_LOGTYPE_USER1, x_, ##__VA_ARGS__) -#define qdma_log_warning(x_, ...) rte_log(RTE_LOG_WARNING,\ - RTE_LOGTYPE_USER1, x_, ##__VA_ARGS__) -#define qdma_log_debug(x_, ...) rte_log(RTE_LOG_DEBUG,\ - RTE_LOGTYPE_USER1, x_, ##__VA_ARGS__) -#define qdma_log_error(x_, ...) rte_log(RTE_LOG_ERR,\ - RTE_LOGTYPE_USER1, x_, ##__VA_ARGS__) -#else -#define qdma_log_info(x_, ...) do { } while (0) -#define qdma_log_warning(x_, ...) do { } while (0) -#define qdma_log_debug(x_, ...) do { } while (0) -#define qdma_log_error(x_, ...) do { } while (0) -#endif - -#endif /* QDMA_PLATFORM_ENV_H_ */ diff --git a/QDMA/DPDK/drivers/net/qdma/qdma_rxtx.c b/QDMA/DPDK/drivers/net/qdma/qdma_rxtx.c deleted file mode 100755 index 186c1bb31..000000000 --- a/QDMA/DPDK/drivers/net/qdma/qdma_rxtx.c +++ /dev/null @@ -1,1464 +0,0 @@ -/*- - * BSD LICENSE - * - * Copyright (c) 2017-2022 Xilinx, Inc. All rights reserved. - * Copyright (c) 2022-2023, Advanced Micro Devices, Inc. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * * Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include -#include -#include "qdma.h" -#include "qdma_access_common.h" - -#include -#include -#include "qdma_rxtx.h" -#include "qdma_devops.h" - -#if defined RTE_ARCH_X86_64 -#include -#include -#define RTE_QDMA_DESCS_PER_LOOP (2) -#endif - -/** - * Poll the QDMA engine for transfer completion. - * - * @param txq - * Generic pointer to either Rx/Tx queue structure based on the DMA direction. - * @param expected_count - * expected transfer count. - * - * @return - * Number of packets transferred successfully by the engine. - */ -static int dma_wb_monitor(void *xq, uint8_t dir, uint16_t expected_count) -{ - struct wb_status *wb_status; - uint16_t mode, wb_tail; - uint32_t i = 0; - - if (dir == DMA_TO_DEVICE) { - struct qdma_tx_queue *txq = (struct qdma_tx_queue *)xq; - wb_status = txq->wb_status; - - while (i < WB_TIMEOUT) { - if (expected_count == wb_status->cidx) { - PMD_DRV_LOG(DEBUG, "Poll writeback count " - "matches to the expected count :%d", - expected_count); - return 0; - } - PMD_DRV_LOG(DEBUG, "poll wait on wb-count:%d and " - "expected-count:%d\n", - wb_status->cidx, expected_count); - rte_delay_us(2); - i++; - } - PMD_DRV_LOG(DEBUG, "DMA Engine write-back monitor " - "timeout error occurred\n"); - return -1; - } - /* dir == DMA_FROM_DEVICE */ - struct qdma_rx_queue *rxq = (struct qdma_rx_queue *)xq; - wb_status = rxq->wb_status; - mode = rxq->st_mode; - - /* Poll the writeback location until timeout Or, the expected - * count matches to the writeback count - */ - while (i < WB_TIMEOUT) { - if (mode) { - wb_tail = - (rxq->cmpt_cidx_info.wrb_cidx + expected_count) % - (rxq->nb_rx_cmpt_desc - 1); - if (wb_tail == wb_status->pidx) { - PMD_DRV_LOG(DEBUG, "ST: Poll cmpt count matches" - " to the expected count :%d", - expected_count); - return 0; - } - PMD_DRV_LOG(DEBUG, "ST: poll wait on wb-count:%d and" - " expected-count:%d\n", - wb_status->pidx, expected_count); - } else { - if (expected_count == wb_status->cidx) { - PMD_DRV_LOG(DEBUG, "MM: Poll writeback count " - "matches to the expected count" - " :%d", expected_count); - return 0; - } - PMD_DRV_LOG(DEBUG, "MM: poll wait on wb-count:%d " - "and expected-count:%d\n", - wb_status->cidx, expected_count); - } - rte_delay_us(2); - i++; - } - return -1; -} - -static int qdma_extract_st_cmpt_info(void *ul_cmpt_entry, void *cmpt_info) -{ - union qdma_ul_st_cmpt_ring *cmpt_data, *cmpt_desc; - - cmpt_desc = (union qdma_ul_st_cmpt_ring *)(ul_cmpt_entry); - cmpt_data = (union qdma_ul_st_cmpt_ring *)(cmpt_info); - - cmpt_data->data = cmpt_desc->data; - if (unlikely(!cmpt_desc->desc_used)) - cmpt_data->length = 0; - - return 0; -} - -int reclaim_tx_mbuf(struct qdma_tx_queue *txq, - uint16_t cidx, uint16_t free_cnt) -{ - int fl_desc = 0; - uint16_t fl_desc_cnt; - uint16_t count; - int id; - - id = txq->tx_fl_tail; - fl_desc = (int)cidx - id; - - if (unlikely(!fl_desc)) - return 0; - - if (fl_desc < 0) - fl_desc += (txq->nb_tx_desc - 1); - - if (free_cnt && (fl_desc > free_cnt)) - fl_desc = free_cnt; - - if ((id + fl_desc) < (txq->nb_tx_desc - 1)) { - fl_desc_cnt = ((uint16_t)fl_desc & 0xFFFF); - rte_pktmbuf_free_bulk(&txq->sw_ring[id], fl_desc_cnt); - for (count = 0; count < fl_desc_cnt; count++) - txq->sw_ring[id++] = NULL; - - txq->tx_fl_tail = id; - - return fl_desc; - } - - txq->qstats.ring_wrap_cnt++; - - /* Handle Tx queue ring wrap case */ - fl_desc -= (txq->nb_tx_desc - 1 - id); - rte_pktmbuf_free_bulk(&txq->sw_ring[id], (txq->nb_tx_desc - 1 - id)); - for (; id < (txq->nb_tx_desc - 1); id++) - txq->sw_ring[id] = NULL; - - id -= (txq->nb_tx_desc - 1); - fl_desc_cnt = ((uint16_t)fl_desc & 0xFFFF); - rte_pktmbuf_free_bulk(&txq->sw_ring[id], fl_desc_cnt); - for (count = 0; count < fl_desc_cnt; count++) - txq->sw_ring[id++] = NULL; - - txq->tx_fl_tail = id; - - return fl_desc; -} - -#ifdef TEST_64B_DESC_BYPASS -uint16_t qdma_xmit_64B_desc_bypass(struct qdma_tx_queue *txq, - struct rte_mbuf **tx_pkts, uint16_t nb_pkts) -{ - uint16_t count, id; - uint8_t *tx_ring_st_bypass = NULL; - int ofd = -1, ret = 0; - char fln[50]; - struct qdma_pci_dev *qdma_dev = txq->dev->data->dev_private; - - id = txq->q_pidx_info.pidx; - - for (count = 0; count < nb_pkts; count++) { - tx_ring_st_bypass = (uint8_t *)txq->tx_ring; - memset(&tx_ring_st_bypass[id * (txq->bypass_desc_sz)], - ((id % 255) + 1), txq->bypass_desc_sz); - - snprintf(fln, sizeof(fln), "q_%u_%s", txq->queue_id, - "h2c_desc_data.txt"); - ofd = open(fln, O_RDWR | O_CREAT | O_APPEND | O_SYNC, - 0666); - if (ofd < 0) { - PMD_DRV_LOG(INFO, " txq[%d] unable to create " - "outfile to dump descriptor" - " data", txq->queue_id); - return 0; - } - ret = write(ofd, &(tx_ring_st_bypass[id * - (txq->bypass_desc_sz)]), - txq->bypass_desc_sz); - if (ret < txq->bypass_desc_sz) - PMD_DRV_LOG(DEBUG, "Txq[%d] descriptor data " - "len: %d, written to inputfile" - " :%d bytes", txq->queue_id, - txq->bypass_desc_sz, ret); - close(ofd); - - rte_pktmbuf_free(tx_pkts[count]); - - id++; - if (unlikely(id >= (txq->nb_tx_desc - 1))) - id -= (txq->nb_tx_desc - 1); - } - - /* Make sure writes to the H2C descriptors are synchronized - * before updating PIDX - */ - rte_wmb(); - - txq->q_pidx_info.pidx = id; - qdma_dev->hw_access->qdma_queue_pidx_update(txq->dev, qdma_dev->is_vf, - txq->queue_id, 0, &txq->q_pidx_info); - - PMD_DRV_LOG(DEBUG, " xmit completed with count:%d\n", count); - - return count; -} -#endif - -uint16_t qdma_get_rx_queue_id(void *queue_hndl) -{ - struct qdma_rx_queue *rxq = (struct qdma_rx_queue *)queue_hndl; - - return rxq->queue_id; -} - -void qdma_get_device_info(void *queue_hndl, - enum qdma_device_type *device_type, - enum qdma_ip_type *ip_type) -{ - struct qdma_rx_queue *rxq = (struct qdma_rx_queue *)queue_hndl; - struct qdma_pci_dev *qdma_dev = rxq->dev->data->dev_private; - - *device_type = (enum qdma_device_type)qdma_dev->device_type; - *ip_type = (enum qdma_ip_type)qdma_dev->ip_type; -} - -uint64_t get_mm_c2h_ep_addr(void *queue_hndl) -{ - struct qdma_rx_queue *rxq = (struct qdma_rx_queue *)queue_hndl; - - return rxq->ep_addr; -} - -uint32_t get_mm_buff_size(void *queue_hndl) -{ - struct qdma_rx_queue *rxq = (struct qdma_rx_queue *)queue_hndl; - - return rxq->rx_buff_size; -} - -struct qdma_ul_st_h2c_desc *get_st_h2c_desc(void *queue_hndl) -{ - volatile uint16_t id; - struct qdma_ul_st_h2c_desc *tx_ring_st; - struct qdma_ul_st_h2c_desc *desc; - struct qdma_tx_queue *txq = (struct qdma_tx_queue *)queue_hndl; - - id = txq->q_pidx_info.pidx; - tx_ring_st = (struct qdma_ul_st_h2c_desc *)txq->tx_ring; - desc = (struct qdma_ul_st_h2c_desc *)&tx_ring_st[id]; - - id++; - if (unlikely(id >= (txq->nb_tx_desc - 1))) - id -= (txq->nb_tx_desc - 1); - - txq->q_pidx_info.pidx = id; - - return desc; -} - -struct qdma_ul_mm_desc *get_mm_h2c_desc(void *queue_hndl) -{ - struct qdma_ul_mm_desc *desc; - struct qdma_tx_queue *txq = (struct qdma_tx_queue *)queue_hndl; - struct qdma_ul_mm_desc *tx_ring = - (struct qdma_ul_mm_desc *)txq->tx_ring; - uint32_t id; - - id = txq->q_pidx_info.pidx; - desc = (struct qdma_ul_mm_desc *)&tx_ring[id]; - - id = (id + 1) % (txq->nb_tx_desc - 1); - txq->q_pidx_info.pidx = id; - - return desc; -} - -uint64_t get_mm_h2c_ep_addr(void *queue_hndl) -{ - struct qdma_tx_queue *txq = (struct qdma_tx_queue *)queue_hndl; - - return txq->ep_addr; -} - -#ifdef QDMA_LATENCY_OPTIMIZED -static void adjust_c2h_cntr_avgs(struct qdma_rx_queue *rxq) -{ - int i; - struct qdma_pci_dev *qdma_dev = rxq->dev->data->dev_private; - - if (rxq->sorted_c2h_cntr_idx < 0) - return; - - rxq->pend_pkt_moving_avg = - qdma_dev->g_c2h_cnt_th[rxq->cmpt_cidx_info.counter_idx]; - - if (rxq->sorted_c2h_cntr_idx == (QDMA_GLOBAL_CSR_ARRAY_SZ - 1)) - i = qdma_dev->sorted_idx_c2h_cnt_th[rxq->sorted_c2h_cntr_idx]; - else - i = qdma_dev->sorted_idx_c2h_cnt_th[ - rxq->sorted_c2h_cntr_idx + 1]; - - rxq->pend_pkt_avg_thr_hi = qdma_dev->g_c2h_cnt_th[i]; - - if (rxq->sorted_c2h_cntr_idx > 0) - i = qdma_dev->sorted_idx_c2h_cnt_th[ - rxq->sorted_c2h_cntr_idx - 1]; - else - i = qdma_dev->sorted_idx_c2h_cnt_th[rxq->sorted_c2h_cntr_idx]; - - rxq->pend_pkt_avg_thr_lo = qdma_dev->g_c2h_cnt_th[i]; - - PMD_DRV_LOG(DEBUG, "q%u: c2h_cntr_idx = %u %u %u", - rxq->queue_id, - rxq->cmpt_cidx_info.counter_idx, - rxq->pend_pkt_avg_thr_lo, - rxq->pend_pkt_avg_thr_hi); -} - -static void incr_c2h_cntr_th(struct qdma_rx_queue *rxq) -{ - struct qdma_pci_dev *qdma_dev = rxq->dev->data->dev_private; - unsigned char i, c2h_cntr_idx; - unsigned char c2h_cntr_val_new; - unsigned char c2h_cntr_val_curr; - - if (rxq->sorted_c2h_cntr_idx == - (QDMA_NUM_C2H_COUNTERS - 1)) - return; - - rxq->c2h_cntr_monitor_cnt = 0; - i = rxq->sorted_c2h_cntr_idx; - c2h_cntr_idx = qdma_dev->sorted_idx_c2h_cnt_th[i]; - c2h_cntr_val_curr = qdma_dev->g_c2h_cnt_th[c2h_cntr_idx]; - i++; - c2h_cntr_idx = qdma_dev->sorted_idx_c2h_cnt_th[i]; - c2h_cntr_val_new = qdma_dev->g_c2h_cnt_th[c2h_cntr_idx]; - - /* Choose the closest counter value */ - if ((c2h_cntr_val_new >= rxq->pend_pkt_moving_avg) && - (c2h_cntr_val_new - rxq->pend_pkt_moving_avg) >= - (rxq->pend_pkt_moving_avg - c2h_cntr_val_curr)) - return; - - /* Do not allow c2h counter value go beyond half of C2H ring sz*/ - if (c2h_cntr_val_new < (qdma_dev->g_ring_sz[rxq->ringszidx] >> 1)) { - rxq->cmpt_cidx_info.counter_idx = c2h_cntr_idx; - rxq->sorted_c2h_cntr_idx = i; - adjust_c2h_cntr_avgs(rxq); - } -} - -static void decr_c2h_cntr_th(struct qdma_rx_queue *rxq) -{ - struct qdma_pci_dev *qdma_dev = rxq->dev->data->dev_private; - unsigned char i, c2h_cntr_idx; - unsigned char c2h_cntr_val_new; - unsigned char c2h_cntr_val_curr; - - if (!rxq->sorted_c2h_cntr_idx) - return; - rxq->c2h_cntr_monitor_cnt = 0; - i = rxq->sorted_c2h_cntr_idx; - c2h_cntr_idx = qdma_dev->sorted_idx_c2h_cnt_th[i]; - c2h_cntr_val_curr = qdma_dev->g_c2h_cnt_th[c2h_cntr_idx]; - i--; - c2h_cntr_idx = qdma_dev->sorted_idx_c2h_cnt_th[i]; - - c2h_cntr_val_new = qdma_dev->g_c2h_cnt_th[c2h_cntr_idx]; - - /* Choose the closest counter value */ - if ((c2h_cntr_val_new <= rxq->pend_pkt_moving_avg) && - (rxq->pend_pkt_moving_avg - c2h_cntr_val_new) >= - (c2h_cntr_val_curr - rxq->pend_pkt_moving_avg)) - return; - - rxq->cmpt_cidx_info.counter_idx = c2h_cntr_idx; - - rxq->sorted_c2h_cntr_idx = i; - adjust_c2h_cntr_avgs(rxq); -} - -#define MAX_C2H_CNTR_STAGNANT_CNT 16 -static void adapt_update_counter(struct qdma_rx_queue *rxq, - uint16_t nb_pkts_avail) -{ - /* Add available pkt count and average */ - rxq->pend_pkt_moving_avg += nb_pkts_avail; - rxq->pend_pkt_moving_avg >>= 1; - - /* if avg > hi_th, increase the counter - * if avg < lo_th, decrease the counter - */ - if (rxq->pend_pkt_avg_thr_hi <= rxq->pend_pkt_moving_avg) - incr_c2h_cntr_th(rxq); - else if (rxq->pend_pkt_avg_thr_lo >= - rxq->pend_pkt_moving_avg) - decr_c2h_cntr_th(rxq); - else { - rxq->c2h_cntr_monitor_cnt++; - if (rxq->c2h_cntr_monitor_cnt == MAX_C2H_CNTR_STAGNANT_CNT) { - /* go down on counter value to see if we actually are - * increasing latency by setting - * higher counter threshold - */ - decr_c2h_cntr_th(rxq); - rxq->c2h_cntr_monitor_cnt = 0; - } else - return; - } -} -#endif //QDMA_LATENCY_OPTIMIZED - -/* Process completion ring */ -static int process_cmpt_ring(struct qdma_rx_queue *rxq, - uint16_t num_cmpt_entries) -{ - struct qdma_pci_dev *qdma_dev = rxq->dev->data->dev_private; - union qdma_ul_st_cmpt_ring *user_cmpt_entry; - uint32_t count = 0; - int ret = 0; - uint16_t rx_cmpt_tail = rxq->cmpt_cidx_info.wrb_cidx; - - if (likely(!rxq->dump_immediate_data)) { - if ((rx_cmpt_tail + num_cmpt_entries) < - (rxq->nb_rx_cmpt_desc - 1)) { - for (count = 0; count < num_cmpt_entries; count++) { - user_cmpt_entry = - (union qdma_ul_st_cmpt_ring *) - ((uint64_t)rxq->cmpt_ring + - ((uint64_t)rx_cmpt_tail * rxq->cmpt_desc_len)); - - ret = qdma_extract_st_cmpt_info( - user_cmpt_entry, - &rxq->cmpt_data[count]); - if (ret != 0) { - PMD_DRV_LOG(ERR, "Error detected on CMPT ring " - "at index %d, queue_id = %d\n", - rx_cmpt_tail, rxq->queue_id); - rxq->err = 1; - return -1; - } - rx_cmpt_tail++; - } - } else { - while (count < num_cmpt_entries) { - user_cmpt_entry = - (union qdma_ul_st_cmpt_ring *) - ((uint64_t)rxq->cmpt_ring + - ((uint64_t)rx_cmpt_tail * rxq->cmpt_desc_len)); - - ret = qdma_extract_st_cmpt_info( - user_cmpt_entry, - &rxq->cmpt_data[count]); - if (ret != 0) { - PMD_DRV_LOG(ERR, "Error detected on CMPT ring " - "at index %d, queue_id = %d\n", - rx_cmpt_tail, rxq->queue_id); - rxq->err = 1; - return -1; - } - - rx_cmpt_tail++; - if (unlikely(rx_cmpt_tail >= - (rxq->nb_rx_cmpt_desc - 1))) - rx_cmpt_tail -= - (rxq->nb_rx_cmpt_desc - 1); - count++; - } - } - } else { - while (count < num_cmpt_entries) { - user_cmpt_entry = - (union qdma_ul_st_cmpt_ring *) - ((uint64_t)rxq->cmpt_ring + - ((uint64_t)rx_cmpt_tail * rxq->cmpt_desc_len)); - - ret = qdma_ul_extract_st_cmpt_info( - user_cmpt_entry, - &rxq->cmpt_data[count]); - if (ret != 0) { - PMD_DRV_LOG(ERR, "Error detected on CMPT ring " - "at CMPT index %d, queue_id = %d\n", - rx_cmpt_tail, rxq->queue_id); - rxq->err = 1; - return -1; - } - - ret = qdma_ul_process_immediate_data_st((void *)rxq, - user_cmpt_entry, rxq->cmpt_desc_len); - if (ret < 0) { - PMD_DRV_LOG(ERR, "Error processing immediate data " - "at CMPT index = %d, queue_id = %d\n", - rx_cmpt_tail, rxq->queue_id); - return -1; - } - - rx_cmpt_tail++; - if (unlikely(rx_cmpt_tail >= - (rxq->nb_rx_cmpt_desc - 1))) - rx_cmpt_tail -= (rxq->nb_rx_cmpt_desc - 1); - count++; - } - } - - // Update the CPMT CIDX - rxq->cmpt_cidx_info.wrb_cidx = rx_cmpt_tail; - qdma_dev->hw_access->qdma_queue_cmpt_cidx_update(rxq->dev, - qdma_dev->is_vf, - rxq->queue_id, &rxq->cmpt_cidx_info); - - return 0; -} - -uint32_t rx_queue_count(void *rx_queue) -{ - struct qdma_rx_queue *rxq = rx_queue; - struct wb_status *wb_status; - uint16_t pkt_length; - uint16_t nb_pkts_avail = 0; - uint16_t rx_cmpt_tail = 0; - uint16_t cmpt_pidx; - uint32_t nb_desc_used = 0, count = 0; - union qdma_ul_st_cmpt_ring *user_cmpt_entry; - union qdma_ul_st_cmpt_ring cmpt_data; - - wb_status = rxq->wb_status; - rx_cmpt_tail = rxq->cmpt_cidx_info.wrb_cidx; - cmpt_pidx = wb_status->pidx; - - if (rx_cmpt_tail < cmpt_pidx) - nb_pkts_avail = cmpt_pidx - rx_cmpt_tail; - else if (rx_cmpt_tail > cmpt_pidx) - nb_pkts_avail = rxq->nb_rx_cmpt_desc - 1 - rx_cmpt_tail + - cmpt_pidx; - - if (nb_pkts_avail == 0) - return 0; - - while (count < nb_pkts_avail) { - user_cmpt_entry = - (union qdma_ul_st_cmpt_ring *)((uint64_t)rxq->cmpt_ring + - ((uint64_t)rx_cmpt_tail * rxq->cmpt_desc_len)); - - if (qdma_ul_extract_st_cmpt_info(user_cmpt_entry, - &cmpt_data)) { - break; - } - - pkt_length = qdma_ul_get_cmpt_pkt_len(&cmpt_data); - if (unlikely(!pkt_length)) { - count++; - continue; - } - - nb_desc_used += ((pkt_length/rxq->rx_buff_size) + 1); - rx_cmpt_tail++; - if (unlikely(rx_cmpt_tail >= (rxq->nb_rx_cmpt_desc - 1))) - rx_cmpt_tail -= (rxq->nb_rx_cmpt_desc - 1); - count++; - } - PMD_DRV_LOG(DEBUG, "%s: nb_desc_used = %d", - __func__, nb_desc_used); - return nb_desc_used; -} - -/** - * DPDK callback to check the status of a Rx descriptor in the queue. - * - * @param rx_queue - * Pointer to Rx queue specific data structure. - * @param offset - * The offset of the descriptor starting from tail (0 is the next - * packet to be received by the driver). - * - * @return - * - (RTE_ETH_RX_DESC_AVAIL): Descriptor is available for the hardware to - * receive a packet. - * - (RTE_ETH_RX_DESC_DONE): Descriptor is done, it is filled by hw, but - * not yet processed by the driver (i.e. in the receive queue). - * - (RTE_ETH_RX_DESC_UNAVAIL): Descriptor is unavailable, either hold by - * the driver and not yet returned to hw, or reserved by the hw. - * - (-EINVAL) bad descriptor offset. - */ -int -qdma_dev_rx_descriptor_status(void *rx_queue, uint16_t offset) -{ - struct qdma_rx_queue *rxq = rx_queue; - uint32_t desc_used_count; - uint16_t rx_tail, c2h_pidx, pending_desc; - - if (unlikely(offset >= (rxq->nb_rx_desc - 1))) - return -EINVAL; - - /* One descriptor is reserved so that pidx is not same as tail */ - if (offset == (rxq->nb_rx_desc - 2)) - return RTE_ETH_RX_DESC_UNAVAIL; - - desc_used_count = rx_queue_count(rxq); - if (offset < desc_used_count) - return RTE_ETH_RX_DESC_DONE; - - /* If Tail is not same as PIDX, descriptors are held by the driver */ - rx_tail = rxq->rx_tail; - c2h_pidx = rxq->q_pidx_info.pidx; - - pending_desc = rx_tail - c2h_pidx - 1; - if (rx_tail < (c2h_pidx + 1)) - pending_desc = rxq->nb_rx_desc - 2 + rx_tail - - c2h_pidx; - - if (offset < (desc_used_count + pending_desc)) - return RTE_ETH_RX_DESC_UNAVAIL; - - return RTE_ETH_RX_DESC_AVAIL; -} - -/* Update mbuf for a segmented packet */ -struct rte_mbuf *prepare_segmented_packet(struct qdma_rx_queue *rxq, - uint16_t pkt_length, uint16_t *tail) -{ - struct rte_mbuf *mb; - struct rte_mbuf *first_seg = NULL; - struct rte_mbuf *last_seg = NULL; - uint16_t id = *tail; - uint16_t length; - uint16_t rx_buff_size = rxq->rx_buff_size; - - do { - mb = rxq->sw_ring[id]; - rxq->sw_ring[id++] = NULL; - length = pkt_length; - - if (unlikely(id >= (rxq->nb_rx_desc - 1))) - id -= (rxq->nb_rx_desc - 1); - if (pkt_length > rx_buff_size) { - rte_pktmbuf_data_len(mb) = rx_buff_size; - pkt_length -= rx_buff_size; - } else { - rte_pktmbuf_data_len(mb) = pkt_length; - pkt_length = 0; - } - rte_mbuf_refcnt_set(mb, 1); - - if (first_seg == NULL) { - first_seg = mb; - first_seg->nb_segs = 1; - first_seg->pkt_len = length; - first_seg->packet_type = 0; - first_seg->ol_flags = 0; - first_seg->port = rxq->port_id; - first_seg->vlan_tci = 0; - first_seg->hash.rss = 0; - } else { - first_seg->nb_segs++; - if (last_seg != NULL) - last_seg->next = mb; - } - - last_seg = mb; - mb->next = NULL; - } while (pkt_length); - - *tail = id; - return first_seg; -} - -/* Prepare mbuf for one packet */ -static inline -struct rte_mbuf *prepare_single_packet(struct qdma_rx_queue *rxq, - uint16_t cmpt_idx) -{ - struct rte_mbuf *mb = NULL; - uint16_t id = rxq->rx_tail; - uint16_t pkt_length; - - pkt_length = qdma_ul_get_cmpt_pkt_len(&rxq->cmpt_data[cmpt_idx]); - - if (pkt_length) { - rxq->stats.pkts++; - rxq->stats.bytes += pkt_length; - - if (likely(pkt_length <= rxq->rx_buff_size)) { - mb = rxq->sw_ring[id]; - rxq->sw_ring[id++] = NULL; - - if (unlikely(id >= (rxq->nb_rx_desc - 1))) - id -= (rxq->nb_rx_desc - 1); - - rte_mbuf_refcnt_set(mb, 1); - mb->nb_segs = 1; - mb->port = rxq->port_id; - mb->ol_flags = 0; - mb->packet_type = 0; - mb->pkt_len = pkt_length; - mb->data_len = pkt_length; - } else { - mb = prepare_segmented_packet(rxq, pkt_length, &id); - } - - rxq->rx_tail = id; - } - return mb; -} - -/* Prepare mbufs with packet information */ -static uint16_t prepare_packets(struct qdma_rx_queue *rxq, - struct rte_mbuf **rx_pkts, uint16_t nb_pkts) -{ - uint16_t count_pkts = 0; - - struct rte_mbuf *mb; - uint16_t pkt_length; - uint16_t count = 0; - while (count < nb_pkts) { - pkt_length = qdma_ul_get_cmpt_pkt_len( - &rxq->cmpt_data[count]); - if (pkt_length) { - rxq->stats.pkts++; - rxq->stats.bytes += pkt_length; - mb = prepare_segmented_packet(rxq, - pkt_length, &rxq->rx_tail); - rx_pkts[count_pkts++] = mb; - } - count++; - } - - return count_pkts; -} - -/* Populate C2H ring with new buffers */ -static int rearm_c2h_ring(struct qdma_rx_queue *rxq, uint16_t num_desc) -{ - struct qdma_pci_dev *qdma_dev = rxq->dev->data->dev_private; - struct rte_mbuf *mb; - struct qdma_ul_st_c2h_desc *rx_ring_st = - (struct qdma_ul_st_c2h_desc *)rxq->rx_ring; - uint16_t mbuf_index = 0; - uint16_t id; - int rearm_descs; - - id = rxq->q_pidx_info.pidx; - - /* Split the C2H ring updation in two parts. - * First handle till end of ring and then - * handle from beginning of ring, if ring wraps - */ - if ((id + num_desc) < (rxq->nb_rx_desc - 1)) - rearm_descs = num_desc; - else { - rearm_descs = (rxq->nb_rx_desc - 1) - id; - rxq->qstats.ring_wrap_cnt++; - } - - /* allocate new buffer */ - if (rte_mempool_get_bulk(rxq->mb_pool, (void *)&rxq->sw_ring[id], - rearm_descs) != 0){ - PMD_DRV_LOG(ERR, "%s(): %d: No MBUFS, queue id = %d," - "mbuf_avail_count = %d," - " mbuf_in_use_count = %d, num_desc_req = %d\n", - __func__, __LINE__, rxq->queue_id, - rte_mempool_avail_count(rxq->mb_pool), - rte_mempool_in_use_count(rxq->mb_pool), rearm_descs); - return -1; - } - - for (mbuf_index = 0; mbuf_index < rearm_descs; - mbuf_index++, id++) { - mb = rxq->sw_ring[id]; - mb->data_off = RTE_PKTMBUF_HEADROOM; - - /* rearm descriptor */ - rx_ring_st[id].dst_addr = - (uint64_t)mb->buf_iova + - RTE_PKTMBUF_HEADROOM; - } - - if (unlikely(id >= (rxq->nb_rx_desc - 1))) - id -= (rxq->nb_rx_desc - 1); - - /* Handle from beginning of ring, if ring wrapped */ - rearm_descs = num_desc - rearm_descs; - if (unlikely(rearm_descs)) { - /* allocate new buffer */ - if (rte_mempool_get_bulk(rxq->mb_pool, - (void *)&rxq->sw_ring[id], rearm_descs) != 0) { - PMD_DRV_LOG(ERR, "%s(): %d: No MBUFS, queue id = %d," - "mbuf_avail_count = %d," - " mbuf_in_use_count = %d, num_desc_req = %d\n", - __func__, __LINE__, rxq->queue_id, - rte_mempool_avail_count(rxq->mb_pool), - rte_mempool_in_use_count(rxq->mb_pool), rearm_descs); - - rxq->q_pidx_info.pidx = id; - qdma_dev->hw_access->qdma_queue_pidx_update(rxq->dev, - qdma_dev->is_vf, - rxq->queue_id, 1, &rxq->q_pidx_info); - - return -1; - } - - for (mbuf_index = 0; - mbuf_index < ((uint16_t)rearm_descs & 0xFFFF); - mbuf_index++, id++) { - mb = rxq->sw_ring[id]; - mb->data_off = RTE_PKTMBUF_HEADROOM; - - /* rearm descriptor */ - rx_ring_st[id].dst_addr = - (uint64_t)mb->buf_iova + - RTE_PKTMBUF_HEADROOM; - } - } - - PMD_DRV_LOG(DEBUG, "%s(): %d: PIDX Update: queue id = %d, " - "num_desc = %d", - __func__, __LINE__, rxq->queue_id, - num_desc); - - /* Make sure writes to the C2H descriptors are - * synchronized before updating PIDX - */ - rte_wmb(); - - rxq->q_pidx_info.pidx = id; - qdma_dev->hw_access->qdma_queue_pidx_update(rxq->dev, - qdma_dev->is_vf, - rxq->queue_id, 1, &rxq->q_pidx_info); - - return 0; -} - -/* Receive API for Streaming mode */ -uint16_t qdma_recv_pkts_st(struct qdma_rx_queue *rxq, - struct rte_mbuf **rx_pkts, uint16_t nb_pkts) -{ - uint16_t count_pkts; - struct wb_status *wb_status; - uint16_t nb_pkts_avail = 0; - uint16_t rx_cmpt_tail = 0; - uint16_t cmpt_pidx, c2h_pidx; - uint16_t pending_desc; -#ifdef TEST_64B_DESC_BYPASS - int bypass_desc_sz_idx = qmda_get_desc_sz_idx(rxq->bypass_desc_sz); -#endif - - if (unlikely(rxq->err)) - return 0; - - PMD_DRV_LOG(DEBUG, "recv start on rx queue-id :%d, on " - "tail index:%d number of pkts %d", - rxq->queue_id, rxq->rx_tail, nb_pkts); - wb_status = rxq->wb_status; - rx_cmpt_tail = rxq->cmpt_cidx_info.wrb_cidx; - -#ifdef TEST_64B_DESC_BYPASS - if (unlikely(rxq->en_bypass && - bypass_desc_sz_idx == SW_DESC_CNTXT_64B_BYPASS_DMA)) { - PMD_DRV_LOG(DEBUG, "For RX ST-mode, example" - " design doesn't support 64byte descriptor\n"); - return 0; - } -#endif - cmpt_pidx = wb_status->pidx; - -#ifdef LATENCY_MEASUREMENT - if (cmpt_pidx != rxq->qstats.wrb_pidx) { - /* stop the timer */ - rxq->qstats.pkt_lat.curr = rte_get_timer_cycles(); - c2h_pidx_to_cmpt_pidx_lat[rxq->queue_id][rxq->qstats.lat_cnt] = - rxq->qstats.pkt_lat.curr - rxq->qstats.pkt_lat.prev; - rxq->qstats.lat_cnt = ((rxq->qstats.lat_cnt + 1) % LATENCY_CNT); - } -#endif - - if (rx_cmpt_tail < cmpt_pidx) - nb_pkts_avail = cmpt_pidx - rx_cmpt_tail; - else if (rx_cmpt_tail > cmpt_pidx) - nb_pkts_avail = rxq->nb_rx_cmpt_desc - 1 - rx_cmpt_tail + - cmpt_pidx; - - if (nb_pkts_avail == 0) { - PMD_DRV_LOG(DEBUG, "%s(): %d: nb_pkts_avail = 0\n", - __func__, __LINE__); - return 0; - } - - nb_pkts = RTE_MIN(nb_pkts, RTE_MIN(nb_pkts_avail, QDMA_MAX_BURST_SIZE)); - -#ifdef DUMP_MEMPOOL_USAGE_STATS - PMD_DRV_LOG(DEBUG, "%s(): %d: queue id = %d, mbuf_avail_count = %d, " - "mbuf_in_use_count = %d", - __func__, __LINE__, rxq->queue_id, - rte_mempool_avail_count(rxq->mb_pool), - rte_mempool_in_use_count(rxq->mb_pool)); -#endif //DUMP_MEMPOOL_USAGE_STATS - /* Make sure reads to CMPT ring are synchronized before - * accessing the ring - */ - rte_rmb(); -#ifdef QDMA_LATENCY_OPTIMIZED - adapt_update_counter(rxq, nb_pkts_avail); -#endif //QDMA_LATENCY_OPTIMIZED - - int ret = process_cmpt_ring(rxq, nb_pkts); - if (unlikely(ret)) - return 0; - - if (rxq->status != RTE_ETH_QUEUE_STATE_STARTED) { - PMD_DRV_LOG(DEBUG, "%s(): %d: rxq->status = %d\n", - __func__, __LINE__, rxq->status); - return 0; - } - - count_pkts = prepare_packets(rxq, rx_pkts, nb_pkts); - - c2h_pidx = rxq->q_pidx_info.pidx; - pending_desc = rxq->rx_tail - c2h_pidx - 1; - if (rxq->rx_tail < (c2h_pidx + 1)) - pending_desc = rxq->nb_rx_desc - 2 + rxq->rx_tail - - c2h_pidx; - - rxq->qstats.pidx = rxq->q_pidx_info.pidx; - rxq->qstats.wrb_pidx = rxq->wb_status->pidx; - rxq->qstats.wrb_cidx = rxq->wb_status->cidx; - rxq->qstats.rxq_cmpt_tail = rx_cmpt_tail; - rxq->qstats.pending_desc = pending_desc; - rxq->qstats.mbuf_avail_cnt = rte_mempool_avail_count(rxq->mb_pool); - rxq->qstats.mbuf_in_use_cnt = rte_mempool_in_use_count(rxq->mb_pool); - - /* Batch the PIDX updates, this minimizes overhead on - * descriptor engine - */ - if (pending_desc >= MIN_RX_PIDX_UPDATE_THRESHOLD) - rearm_c2h_ring(rxq, pending_desc); - -#ifdef DUMP_MEMPOOL_USAGE_STATS - PMD_DRV_LOG(DEBUG, "%s(): %d: queue id = %d, mbuf_avail_count = %d," - " mbuf_in_use_count = %d, count_pkts = %d", - __func__, __LINE__, rxq->queue_id, - rte_mempool_avail_count(rxq->mb_pool), - rte_mempool_in_use_count(rxq->mb_pool), count_pkts); -#endif //DUMP_MEMPOOL_USAGE_STATS - - PMD_DRV_LOG(DEBUG, " Recv complete with hw cidx :%d", - rxq->wb_status->cidx); - PMD_DRV_LOG(DEBUG, " Recv complete with hw pidx :%d\n", - rxq->wb_status->pidx); - - return count_pkts; -} - -/* Receive API for Memory mapped mode */ -uint16_t qdma_recv_pkts_mm(struct qdma_rx_queue *rxq, - struct rte_mbuf **rx_pkts, uint16_t nb_pkts) -{ - struct rte_mbuf *mb; - uint32_t count, id; - struct qdma_ul_mm_desc *desc; - uint32_t len; - int ret; - struct qdma_pci_dev *qdma_dev = rxq->dev->data->dev_private; -#ifdef TEST_64B_DESC_BYPASS - int bypass_desc_sz_idx = qmda_get_desc_sz_idx(rxq->bypass_desc_sz); -#endif - - if (rxq->status != RTE_ETH_QUEUE_STATE_STARTED) - return 0; - - id = rxq->q_pidx_info.pidx; /* Descriptor index */ - - PMD_DRV_LOG(DEBUG, "recv start on rx queue-id :%d, on tail index:%d\n", - rxq->queue_id, id); - -#ifdef TEST_64B_DESC_BYPASS - if (unlikely(rxq->en_bypass && - bypass_desc_sz_idx == SW_DESC_CNTXT_64B_BYPASS_DMA)) { - PMD_DRV_LOG(DEBUG, "For MM mode, example design doesn't " - "support 64byte descriptor\n"); - return 0; - } -#endif - /* Make 1 less available, otherwise if we allow all descriptors - * to be filled,when nb_pkts = nb_tx_desc - 1, pidx will be same - * as old pidx and HW will treat this as no new descriptors were added. - * Hence, DMA won't happen with new descriptors. - */ - if (nb_pkts > rxq->nb_rx_desc - 2) - nb_pkts = rxq->nb_rx_desc - 2; - - for (count = 0; count < nb_pkts; count++) { - /* allocate new buffer */ - if (rte_mempool_get(rxq->mb_pool, (void *)&mb) != 0) { - PMD_DRV_LOG(ERR, "%s(): %d: No MBUFS, queue id = %d," - "mbuf_avail_count = %d," - " mbuf_in_use_count = %d\n", - __func__, __LINE__, rxq->queue_id, - rte_mempool_avail_count(rxq->mb_pool), - rte_mempool_in_use_count(rxq->mb_pool)); - return 0; - } - - desc = (struct qdma_ul_mm_desc *)rxq->rx_ring; - desc += id; - qdma_ul_update_mm_c2h_desc(rxq, mb, desc); - - len = (int)rxq->rx_buff_size; - rte_pktmbuf_pkt_len(mb) = len; - - rte_mbuf_refcnt_set(mb, 1); - mb->packet_type = 0; - mb->ol_flags = 0; - mb->next = 0; - mb->nb_segs = 1; - mb->port = rxq->port_id; - mb->vlan_tci = 0; - mb->hash.rss = 0; - - rx_pkts[count] = mb; - - rxq->ep_addr = (rxq->ep_addr + len) % DMA_BRAM_SIZE; - id = (id + 1) % (rxq->nb_rx_desc - 1); - } - - /* Make sure writes to the C2H descriptors are synchronized - * before updating PIDX - */ - rte_wmb(); - - /* update pidx pointer for MM-mode*/ - if (count > 0) { - rxq->q_pidx_info.pidx = id; - qdma_dev->hw_access->qdma_queue_pidx_update(rxq->dev, - qdma_dev->is_vf, - rxq->queue_id, 1, &rxq->q_pidx_info); - } - - ret = dma_wb_monitor(rxq, DMA_FROM_DEVICE, id); - if (ret) {//Error - PMD_DRV_LOG(ERR, "DMA Engine write-back monitor " - "timeout error occurred, wb-count:%d " - "and expected-count:%d\n", - rxq->wb_status->cidx, id); - - return 0; - } - return count; -} -/** - * DPDK callback for receiving packets in burst. - * - * @param rx_queue - * Generic pointer to Rx queue structure. - * @param[out] rx_pkts - * Array to store received packets. - * @param nb_pkts - * Maximum number of packets in array. - * - * @return - * Number of packets successfully received (<= nb_pkts). - */ -uint16_t qdma_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, - uint16_t nb_pkts) -{ - struct qdma_rx_queue *rxq = rx_queue; - uint32_t count; - - if (rxq->st_mode) - count = qdma_recv_pkts_st(rxq, rx_pkts, nb_pkts); - else - count = qdma_recv_pkts_mm(rxq, rx_pkts, nb_pkts); - - return count; -} - -/** - * DPDK callback to request the driver to free mbufs - * currently cached by the driver. - * - * @param tx_queue - * Pointer to Tx queue specific data structure. - * @param free_cnt - * Maximum number of packets to free. Use 0 to indicate all possible packets - * should be freed. Note that a packet may be using multiple mbufs. - * - * @return - * Failure: < 0 - * Success: >= 0 - * 0-n: Number of packets freed. More packets may still remain in ring that - * are in use. - */ -int -qdma_dev_tx_done_cleanup(void *tx_queue, uint32_t free_cnt) -{ - struct qdma_tx_queue *txq = tx_queue; - - if ((uint16_t)free_cnt >= (txq->nb_tx_desc - 1)) - return -EINVAL; - - /* Free transmitted mbufs back to pool */ - return reclaim_tx_mbuf(txq, txq->wb_status->cidx, free_cnt); -} - -/** - * DPDK callback to check the status of a Tx descriptor in the queue. - * - * @param tx_queue - * Pointer to Tx queue specific data structure. - * @param offset - * The offset of the descriptor starting from tail (0 is the place where - * the next packet will be send). - * - * @return - * - (RTE_ETH_TX_DESC_FULL) Descriptor is being processed by the hw, i.e. - * in the transmit queue. - * - (RTE_ETH_TX_DESC_DONE) Hardware is done with this descriptor, it can - * be reused by the driver. - * - (RTE_ETH_TX_DESC_UNAVAIL): Descriptor is unavailable, reserved by the - * driver or the hardware. - * - (-EINVAL) bad descriptor offset. - */ -int -qdma_dev_tx_descriptor_status(void *tx_queue, uint16_t offset) -{ - struct qdma_tx_queue *txq = tx_queue; - uint16_t id; - int avail, in_use; - uint16_t cidx = 0; - - if (unlikely(offset >= (txq->nb_tx_desc - 1))) - return -EINVAL; - - /* One descriptor is reserved so that pidx is not same as old pidx */ - if (offset == (txq->nb_tx_desc - 2)) - return RTE_ETH_TX_DESC_UNAVAIL; - - id = txq->q_pidx_info.pidx; - cidx = txq->wb_status->cidx; - - in_use = (int)id - cidx; - if (in_use < 0) - in_use += (txq->nb_tx_desc - 1); - avail = txq->nb_tx_desc - 2 - in_use; - - if (offset < avail) - return RTE_ETH_TX_DESC_DONE; - - return RTE_ETH_TX_DESC_FULL; -} - -/* Transmit API for Streaming mode */ -uint16_t qdma_xmit_pkts_st(struct qdma_tx_queue *txq, - struct rte_mbuf **tx_pkts, uint16_t nb_pkts) -{ - struct rte_mbuf *mb = NULL; - uint64_t pkt_len = 0; - int avail, in_use, ret, nsegs; - uint16_t cidx = 0; - uint16_t count = 0, id; - struct qdma_pci_dev *qdma_dev = txq->dev->data->dev_private; - -#ifdef TEST_64B_DESC_BYPASS - int bypass_desc_sz_idx = qmda_get_desc_sz_idx(txq->bypass_desc_sz); - - if (unlikely(txq->en_bypass && - bypass_desc_sz_idx == SW_DESC_CNTXT_64B_BYPASS_DMA)) { - return qdma_xmit_64B_desc_bypass(txq, tx_pkts, nb_pkts); - } -#endif - - id = txq->q_pidx_info.pidx; - - /* Make sure reads to Tx ring are synchronized before - * accessing the status descriptor. - */ - rte_rmb(); - - cidx = txq->wb_status->cidx; - -#ifdef LATENCY_MEASUREMENT - if (cidx != txq->qstats.wrb_cidx) { - /* stop the timer */ - txq->qstats.pkt_lat.curr = rte_get_timer_cycles(); - h2c_pidx_to_hw_cidx_lat[txq->queue_id][txq->qstats.lat_cnt] = - txq->qstats.pkt_lat.curr - txq->qstats.pkt_lat.prev; - txq->qstats.lat_cnt = ((txq->qstats.lat_cnt + 1) % LATENCY_CNT); - } -#endif - - PMD_DRV_LOG(DEBUG, "Xmit start on tx queue-id:%d, tail index:%d\n", - txq->queue_id, id); - - /* Free transmitted mbufs back to pool */ - reclaim_tx_mbuf(txq, cidx, 0); - - in_use = (int)id - cidx; - if (in_use < 0) - in_use += (txq->nb_tx_desc - 1); - - /* Make 1 less available, otherwise if we allow all descriptors - * to be filled, when nb_pkts = nb_tx_desc - 1, pidx will be same - * as old pidx and HW will treat this as no new descriptors were added. - * Hence, DMA won't happen with new descriptors. - */ - avail = txq->nb_tx_desc - 2 - in_use; - - if (unlikely(!avail)) { - txq->qstats.txq_full_cnt++; - PMD_DRV_LOG(DEBUG, "Tx queue full, in_use = %d", in_use); - return 0; - } - - for (count = 0; count < nb_pkts; count++) { - mb = tx_pkts[count]; - nsegs = mb->nb_segs; - if (nsegs > avail) { - /* Number of segments in current mbuf are greater - * than number of descriptors available, - * hence update PIDX and return - */ - break; - } - avail -= nsegs; - id = txq->q_pidx_info.pidx; - txq->sw_ring[id] = mb; - pkt_len += rte_pktmbuf_pkt_len(mb); - - ret = qdma_ul_update_st_h2c_desc(txq, txq->offloads, mb); - if (unlikely(ret < 0)) - break; - } - - txq->stats.pkts += count; - txq->stats.bytes += pkt_len; - - txq->qstats.pidx = id; - txq->qstats.wrb_cidx = cidx; - txq->qstats.txq_tail = txq->tx_fl_tail; - txq->qstats.in_use_desc = in_use; - txq->qstats.nb_pkts = nb_pkts; - -#if (MIN_TX_PIDX_UPDATE_THRESHOLD > 1) - rte_spinlock_lock(&txq->pidx_update_lock); -#endif - txq->tx_desc_pend += count; - - /* Send PIDX update only if pending desc is more than threshold - * Saves frequent Hardware transactions - */ - if (txq->tx_desc_pend >= MIN_TX_PIDX_UPDATE_THRESHOLD) { - qdma_dev->hw_access->qdma_queue_pidx_update(txq->dev, - qdma_dev->is_vf, - txq->queue_id, 0, &txq->q_pidx_info); - - txq->tx_desc_pend = 0; -#ifdef LATENCY_MEASUREMENT - /* start the timer */ - txq->qstats.pkt_lat.prev = rte_get_timer_cycles(); -#endif - } -#if (MIN_TX_PIDX_UPDATE_THRESHOLD > 1) - rte_spinlock_unlock(&txq->pidx_update_lock); -#endif - PMD_DRV_LOG(DEBUG, " xmit completed with count:%d\n", count); - - return count; -} - -/* Transmit API for Memory mapped mode */ -uint16_t qdma_xmit_pkts_mm(struct qdma_tx_queue *txq, - struct rte_mbuf **tx_pkts, uint16_t nb_pkts) -{ - struct rte_mbuf *mb; - uint32_t count, id; - uint64_t len = 0; - int avail, in_use; - int ret; - struct qdma_pci_dev *qdma_dev = txq->dev->data->dev_private; - uint16_t cidx = 0; - -#ifdef TEST_64B_DESC_BYPASS - int bypass_desc_sz_idx = qmda_get_desc_sz_idx(txq->bypass_desc_sz); -#endif - - id = txq->q_pidx_info.pidx; - PMD_DRV_LOG(DEBUG, "Xmit start on tx queue-id:%d, tail index:%d\n", - txq->queue_id, id); - -#ifdef TEST_64B_DESC_BYPASS - if (unlikely(txq->en_bypass && - bypass_desc_sz_idx == SW_DESC_CNTXT_64B_BYPASS_DMA)) { - PMD_DRV_LOG(DEBUG, "For MM mode, example design doesn't " - "support 64B bypass testing\n"); - return 0; - } -#endif - cidx = txq->wb_status->cidx; - /* Free transmitted mbufs back to pool */ - reclaim_tx_mbuf(txq, cidx, 0); - in_use = (int)id - cidx; - if (in_use < 0) - in_use += (txq->nb_tx_desc - 1); - - /* Make 1 less available, otherwise if we allow all descriptors to be - * filled, when nb_pkts = nb_tx_desc - 1, pidx will be same as old pidx - * and HW will treat this as no new descriptors were added. - * Hence, DMA won't happen with new descriptors. - */ - avail = txq->nb_tx_desc - 2 - in_use; - if (!avail) { - PMD_DRV_LOG(ERR, "Tx queue full, in_use = %d", in_use); - return 0; - } - - if (nb_pkts > avail) - nb_pkts = avail; - - // Set the xmit descriptors and control bits - for (count = 0; count < nb_pkts; count++) { - - mb = tx_pkts[count]; - txq->sw_ring[id] = mb; - /*Update the descriptor control feilds*/ - qdma_ul_update_mm_h2c_desc(txq, mb); - - len = rte_pktmbuf_data_len(mb); - PMD_DRV_LOG(DEBUG, "xmit number of bytes:%ld, count:%d ", - len, count); - -#ifndef TANDEM_BOOT_SUPPORTED - txq->ep_addr = (txq->ep_addr + len) % DMA_BRAM_SIZE; -#endif - id = txq->q_pidx_info.pidx; - } - - /* Make sure writes to the H2C descriptors are synchronized before - * updating PIDX - */ - rte_wmb(); - - /* update pidx pointer */ - if (count > 0) { - PMD_DRV_LOG(INFO, "tx PIDX=%d", txq->q_pidx_info.pidx); - qdma_dev->hw_access->qdma_queue_pidx_update(txq->dev, - qdma_dev->is_vf, - txq->queue_id, 0, &txq->q_pidx_info); - } - - ret = dma_wb_monitor(txq, DMA_TO_DEVICE, id); - if (ret) { - PMD_DRV_LOG(ERR, "DMA Engine write-back monitor " - "timeout error occurred, wb-count:%d " - "and expected-count:%d\n", - txq->wb_status->cidx, id); - return 0; - } - - PMD_DRV_LOG(DEBUG, " xmit completed with count:%d", count); - return count; -} -/** - * DPDK callback for transmitting packets in burst. - * - * @param tx_queue - * Generic pointer to TX queue structure. - * @param[in] tx_pkts - * Packets to transmit. - * @param nb_pkts - * Number of packets in array. - * - * @return - * Number of packets successfully transmitted (<= nb_pkts). - */ -uint16_t qdma_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, - uint16_t nb_pkts) -{ - struct qdma_tx_queue *txq = tx_queue; - uint16_t count; - - if (txq->status != RTE_ETH_QUEUE_STATE_STARTED) - return 0; - - if (txq->st_mode) - count = qdma_xmit_pkts_st(txq, tx_pkts, nb_pkts); - else - count = qdma_xmit_pkts_mm(txq, tx_pkts, nb_pkts); - - return count; -} - -void __rte_cold -qdma_set_tx_function(struct rte_eth_dev *dev) -{ - struct qdma_pci_dev *qdma_dev = dev->data->dev_private; - - if (rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_128) { - PMD_DRV_LOG(DEBUG, "Using Vector Tx (port %d).", - dev->data->port_id); - qdma_dev->tx_vec_allowed = true; - dev->tx_pkt_burst = qdma_xmit_pkts_vec; - } else { - PMD_DRV_LOG(DEBUG, "Normal Rx will be used on port %d.", - dev->data->port_id); - dev->tx_pkt_burst = qdma_xmit_pkts; - } -} - -void __rte_cold -qdma_set_rx_function(struct rte_eth_dev *dev) -{ - struct qdma_pci_dev *qdma_dev = dev->data->dev_private; - - if (rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_128) { - PMD_DRV_LOG(DEBUG, "Using Vector Rx (port %d).", - dev->data->port_id); - qdma_dev->rx_vec_allowed = true; - dev->rx_pkt_burst = qdma_recv_pkts_vec; - } else { - PMD_DRV_LOG(DEBUG, "Normal Rx will be used on port %d.", - dev->data->port_id); - dev->rx_pkt_burst = qdma_recv_pkts; - } -} diff --git a/QDMA/DPDK/drivers/net/qdma/qdma_rxtx.h b/QDMA/DPDK/drivers/net/qdma/qdma_rxtx.h deleted file mode 100755 index 58ac9e566..000000000 --- a/QDMA/DPDK/drivers/net/qdma/qdma_rxtx.h +++ /dev/null @@ -1,51 +0,0 @@ -/*- - * BSD LICENSE - * - * Copyright (c) 2019-2022 Xilinx, Inc. All rights reserved. - * Copyright (c) 2022-2023, Advanced Micro Devices, Inc. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * * Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -#ifndef QDMA_DPDK_RXTX_H_ -#define QDMA_DPDK_RXTX_H_ - -#include "qdma_access_export.h" - -/*Supporting functions for user logic pluggability*/ -uint16_t qdma_get_rx_queue_id(void *queue_hndl); -void qdma_get_device_info(void *queue_hndl, - enum qdma_device_type *device_type, - enum qdma_ip_type *ip_type); -struct qdma_ul_st_h2c_desc *get_st_h2c_desc(void *queue_hndl); -struct qdma_ul_mm_desc *get_mm_h2c_desc(void *queue_hndl); -uint64_t get_mm_c2h_ep_addr(void *queue_hndl); -uint64_t get_mm_h2c_ep_addr(void *queue_hndl); -uint32_t get_mm_buff_size(void *queue_hndl); - -uint32_t rx_queue_count(void *rx_queue); - -#endif /* QDMA_DPDK_RXTX_H_ */ diff --git a/QDMA/DPDK/drivers/net/qdma/qdma_rxtx_vec_sse.c b/QDMA/DPDK/drivers/net/qdma/qdma_rxtx_vec_sse.c deleted file mode 100755 index 34809dd6e..000000000 --- a/QDMA/DPDK/drivers/net/qdma/qdma_rxtx_vec_sse.c +++ /dev/null @@ -1,851 +0,0 @@ -/*- - * BSD LICENSE - * - * Copyright (c) 2017-2022 Xilinx, Inc. All rights reserved. - * Copyright (c) 2022-2023, Advanced Micro Devices, Inc. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * * Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include -#include -#include "qdma.h" -#include "qdma_access_common.h" - -#include -#include -#include "qdma_rxtx.h" -#include "qdma_devops.h" - -#if defined RTE_ARCH_X86_64 -#include -#include -#define RTE_QDMA_DESCS_PER_LOOP (2) -#endif - -/* Vector implementation to get packet length from two completion entries */ -static void qdma_ul_get_cmpt_pkt_len_vec(void *ul_cmpt_entry, __m128i *data) -{ - union qdma_ul_st_cmpt_ring *cmpt_entry1, *cmpt_entry2; - __m128i pkt_len_shift = _mm_set_epi64x(0, 4); - - cmpt_entry1 = (union qdma_ul_st_cmpt_ring *)(ul_cmpt_entry); - cmpt_entry2 = cmpt_entry1 + 1; - - /* Read desc statuses backwards to avoid race condition */ - /* Load a pkt desc */ - data[1] = _mm_set_epi64x(0, cmpt_entry2->data); - /* Find packet length, currently driver needs - * only packet length from completion info - */ - data[1] = _mm_srl_epi32(data[1], pkt_len_shift); - - /* Load a pkt desc */ - data[0] = _mm_set_epi64x(0, cmpt_entry1->data); - /* Find packet length, currently driver needs - * only packet length from completion info - */ - data[0] = _mm_srl_epi32(data[0], pkt_len_shift); -} - -/* Vector implementation to update H2C descriptor */ -static int qdma_ul_update_st_h2c_desc_vec(void *qhndl, uint64_t q_offloads, - struct rte_mbuf *mb) -{ - (void)q_offloads; - int nsegs = mb->nb_segs; - uint16_t flags = S_H2C_DESC_F_SOP | S_H2C_DESC_F_EOP; - uint16_t id; - struct qdma_ul_st_h2c_desc *tx_ring_st; - struct qdma_tx_queue *txq = (struct qdma_tx_queue *)qhndl; - - tx_ring_st = (struct qdma_ul_st_h2c_desc *)txq->tx_ring; - id = txq->q_pidx_info.pidx; - - if (nsegs == 1) { - __m128i descriptor; - uint16_t datalen = mb->data_len; - - descriptor = _mm_set_epi64x(mb->buf_iova + mb->data_off, - (uint64_t)datalen << 16 | - (uint64_t)datalen << 32 | - (uint64_t)flags << 48); - _mm_store_si128((__m128i *)&tx_ring_st[id], descriptor); - - id++; - if (unlikely(id >= (txq->nb_tx_desc - 1))) - id -= (txq->nb_tx_desc - 1); - } else { - int pkt_segs = nsegs; - while (nsegs && mb) { - __m128i descriptor; - uint16_t datalen = mb->data_len; - - flags = 0; - if (nsegs == pkt_segs) - flags |= S_H2C_DESC_F_SOP; - if (nsegs == 1) - flags |= S_H2C_DESC_F_EOP; - - descriptor = _mm_set_epi64x(mb->buf_iova + mb->data_off, - (uint64_t)datalen << 16 | - (uint64_t)datalen << 32 | - (uint64_t)flags << 48); - _mm_store_si128((__m128i *)&tx_ring_st[id], descriptor); - - nsegs--; - mb = mb->next; - id++; - if (unlikely(id >= (txq->nb_tx_desc - 1))) - id -= (txq->nb_tx_desc - 1); - } - } - - txq->q_pidx_info.pidx = id; - - return 0; -} - -/* Process completion ring */ -static int process_cmpt_ring_vec(struct qdma_rx_queue *rxq, - uint16_t num_cmpt_entries) -{ - struct qdma_pci_dev *qdma_dev = rxq->dev->data->dev_private; - union qdma_ul_st_cmpt_ring *user_cmpt_entry; - uint32_t count = 0; - int ret = 0; - uint16_t rx_cmpt_tail = rxq->cmpt_cidx_info.wrb_cidx; - - if (likely(!rxq->dump_immediate_data)) { - if ((rx_cmpt_tail + num_cmpt_entries) < - (rxq->nb_rx_cmpt_desc - 1)) { - for (count = 0; count < num_cmpt_entries; count++) { - user_cmpt_entry = - (union qdma_ul_st_cmpt_ring *) - ((uint64_t)rxq->cmpt_ring + - ((uint64_t)rx_cmpt_tail * rxq->cmpt_desc_len)); - - ret = qdma_ul_extract_st_cmpt_info( - user_cmpt_entry, - &rxq->cmpt_data[count]); - if (ret != 0) { - PMD_DRV_LOG(ERR, "Error detected on CMPT ring " - "at index %d, queue_id = %d\n", - rx_cmpt_tail, rxq->queue_id); - rxq->err = 1; - return -1; - } - rx_cmpt_tail++; - } - } else { - while (count < num_cmpt_entries) { - user_cmpt_entry = - (union qdma_ul_st_cmpt_ring *) - ((uint64_t)rxq->cmpt_ring + - ((uint64_t)rx_cmpt_tail * rxq->cmpt_desc_len)); - - ret = qdma_ul_extract_st_cmpt_info( - user_cmpt_entry, - &rxq->cmpt_data[count]); - if (ret != 0) { - PMD_DRV_LOG(ERR, "Error detected on CMPT ring " - "at index %d, queue_id = %d\n", - rx_cmpt_tail, rxq->queue_id); - rxq->err = 1; - return -1; - } - - rx_cmpt_tail++; - if (unlikely(rx_cmpt_tail >= - (rxq->nb_rx_cmpt_desc - 1))) - rx_cmpt_tail -= - (rxq->nb_rx_cmpt_desc - 1); - count++; - } - } - } else { - while (count < num_cmpt_entries) { - user_cmpt_entry = - (union qdma_ul_st_cmpt_ring *) - ((uint64_t)rxq->cmpt_ring + - ((uint64_t)rx_cmpt_tail * rxq->cmpt_desc_len)); - - ret = qdma_ul_extract_st_cmpt_info( - user_cmpt_entry, - &rxq->cmpt_data[count]); - if (ret != 0) { - PMD_DRV_LOG(ERR, "Error detected on CMPT ring " - "at CMPT index %d, queue_id = %d\n", - rx_cmpt_tail, rxq->queue_id); - rxq->err = 1; - return -1; - } - - ret = qdma_ul_process_immediate_data_st((void *)rxq, - user_cmpt_entry, rxq->cmpt_desc_len); - if (ret < 0) { - PMD_DRV_LOG(ERR, "Error processing immediate data " - "at CMPT index = %d, queue_id = %d\n", - rx_cmpt_tail, rxq->queue_id); - return -1; - } - - rx_cmpt_tail++; - if (unlikely(rx_cmpt_tail >= - (rxq->nb_rx_cmpt_desc - 1))) - rx_cmpt_tail -= (rxq->nb_rx_cmpt_desc - 1); - count++; - } - } - - // Update the CPMT CIDX - rxq->cmpt_cidx_info.wrb_cidx = rx_cmpt_tail; - qdma_dev->hw_access->qdma_queue_cmpt_cidx_update(rxq->dev, - qdma_dev->is_vf, - rxq->queue_id, &rxq->cmpt_cidx_info); - - return 0; -} - -/* Prepare mbuf for one packet */ -static inline -struct rte_mbuf *prepare_single_packet(struct qdma_rx_queue *rxq, - uint16_t cmpt_idx) -{ - struct rte_mbuf *mb = NULL; - uint16_t id = rxq->rx_tail; - uint16_t pkt_length; - - pkt_length = qdma_ul_get_cmpt_pkt_len(&rxq->cmpt_data[cmpt_idx]); - - if (pkt_length) { - rxq->stats.pkts++; - rxq->stats.bytes += pkt_length; - - if (likely(pkt_length <= rxq->rx_buff_size)) { - mb = rxq->sw_ring[id]; - rxq->sw_ring[id++] = NULL; - - if (unlikely(id >= (rxq->nb_rx_desc - 1))) - id -= (rxq->nb_rx_desc - 1); - - rte_mbuf_refcnt_set(mb, 1); - mb->nb_segs = 1; - mb->port = rxq->port_id; - mb->ol_flags = 0; - mb->packet_type = 0; - mb->pkt_len = pkt_length; - mb->data_len = pkt_length; - } else { - mb = prepare_segmented_packet(rxq, pkt_length, &id); - } - - rxq->rx_tail = id; - } - return mb; -} - -/* Vector implementation to prepare mbufs for packets. - * Update this API if HW provides more information to be populated in mbuf. - */ -static uint16_t prepare_packets_vec(struct qdma_rx_queue *rxq, - struct rte_mbuf **rx_pkts, uint16_t nb_pkts) -{ - struct rte_mbuf *mb; - uint16_t count = 0, count_pkts = 0; - uint16_t n_pkts = nb_pkts & -2; - uint16_t id = rxq->rx_tail; - struct rte_mbuf **sw_ring = rxq->sw_ring; - uint16_t rx_buff_size = rxq->rx_buff_size; - /* mask to shuffle from desc. to mbuf */ - __m128i shuf_msk = _mm_set_epi8( - 0xFF, 0xFF, 0xFF, 0xFF, /* skip 32bits rss */ - 0xFF, 0xFF, /* skip low 16 bits vlan_macip */ - 1, 0, /* octet 0~1, 16 bits data_len */ - 0xFF, 0xFF, /* skip high 16 bits pkt_len, zero out */ - 1, 0, /* octet 0~1, low 16 bits pkt_len */ - 0xFF, 0xFF, /* skip 32 bit pkt_type */ - 0xFF, 0xFF - ); - __m128i mbuf_init, pktlen, zero_data; - - mbuf_init = _mm_set_epi64x(0, rxq->mbuf_initializer); - pktlen = _mm_setzero_si128(); - zero_data = _mm_setzero_si128(); - - /* compile-time check */ - RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, pkt_len) != - offsetof(struct rte_mbuf, rx_descriptor_fields1) + 4); - RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, data_len) != - offsetof(struct rte_mbuf, rx_descriptor_fields1) + 8); - RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, rearm_data) != - RTE_ALIGN(offsetof(struct rte_mbuf, rearm_data), 16)); - - for (count = 0; count < n_pkts; - count += RTE_QDMA_DESCS_PER_LOOP) { - __m128i pkt_len[RTE_QDMA_DESCS_PER_LOOP]; - __m128i pkt_mb1, pkt_mb2; - __m128i mbp1; - uint16_t pktlen1, pktlen2; - - qdma_ul_get_cmpt_pkt_len_vec( - &rxq->cmpt_data[count], pkt_len); - - pktlen1 = _mm_extract_epi16(pkt_len[0], 0); - pktlen2 = _mm_extract_epi16(pkt_len[1], 0); - - /* Check if packets are segmented across descriptors */ - if ((pktlen1 && (pktlen1 <= rx_buff_size)) && - (pktlen2 && (pktlen2 <= rx_buff_size)) && - ((id + RTE_QDMA_DESCS_PER_LOOP) < - (rxq->nb_rx_desc - 1))) { - /* Load 2 (64 bit) mbuf pointers */ - mbp1 = _mm_loadu_si128((__m128i *)&sw_ring[id]); - - /* Copy 2 64 bit mbuf point into rx_pkts */ - _mm_storeu_si128((__m128i *)&rx_pkts[count_pkts], mbp1); - _mm_storeu_si128((__m128i *)&sw_ring[id], zero_data); - - /* Pkt 1,2 convert format from desc to pktmbuf */ - /* We only have packet length to copy */ - pkt_mb2 = _mm_shuffle_epi8(pkt_len[1], shuf_msk); - pkt_mb1 = _mm_shuffle_epi8(pkt_len[0], shuf_msk); - - /* Write the rearm data and the olflags in one write */ - _mm_store_si128( - (__m128i *)&rx_pkts[count_pkts]->rearm_data, mbuf_init); - _mm_store_si128( - (__m128i *)&rx_pkts[count_pkts + 1]->rearm_data, - mbuf_init); - - /* Write packet length */ - _mm_storeu_si128( - (void *)&rx_pkts[count_pkts]->rx_descriptor_fields1, - pkt_mb1); - _mm_storeu_si128( - (void *)&rx_pkts[count_pkts + 1]->rx_descriptor_fields1, - pkt_mb2); - - /* Accumulate packet length counter */ - pktlen = _mm_add_epi64(pktlen, - _mm_set_epi16(0, 0, 0, 0, - 0, 0, 0, pktlen1)); - pktlen = _mm_add_epi64(pktlen, - _mm_set_epi16(0, 0, 0, 0, - 0, 0, 0, pktlen2)); - - count_pkts += RTE_QDMA_DESCS_PER_LOOP; - id += RTE_QDMA_DESCS_PER_LOOP; - } else { - /* Handle packets segmented - * across multiple descriptors - * or ring wrap - */ - if (pktlen1) { - mb = prepare_segmented_packet(rxq, - pktlen1, &id); - rx_pkts[count_pkts++] = mb; - pktlen = _mm_add_epi64(pktlen, - _mm_set_epi16(0, 0, 0, 0, - 0, 0, 0, pktlen1)); - } - - if (pktlen2) { - mb = prepare_segmented_packet(rxq, - pktlen2, &id); - rx_pkts[count_pkts++] = mb; - pktlen = _mm_add_epi64(pktlen, - _mm_set_epi16(0, 0, 0, 0, - 0, 0, 0, pktlen2)); - } - } - } - - rxq->stats.pkts += count_pkts; - rxq->stats.bytes += _mm_extract_epi64(pktlen, 0); - rxq->rx_tail = id; - - /* Handle single packet, if any pending */ - if (nb_pkts & 1) { - mb = prepare_single_packet(rxq, count); - if (mb) - rx_pkts[count_pkts++] = mb; - } - - return count_pkts; -} - -/* Populate C2H ring with new buffers */ -static int rearm_c2h_ring_vec(struct qdma_rx_queue *rxq, uint16_t num_desc) -{ - struct qdma_pci_dev *qdma_dev = rxq->dev->data->dev_private; - struct rte_mbuf *mb; - struct qdma_ul_st_c2h_desc *rx_ring_st = - (struct qdma_ul_st_c2h_desc *)rxq->rx_ring; - uint16_t mbuf_index = 0; - uint16_t id; - int rearm_descs; - - id = rxq->q_pidx_info.pidx; - - /* Split the C2H ring updation in two parts. - * First handle till end of ring and then - * handle from beginning of ring, if ring wraps - */ - if ((id + num_desc) < (rxq->nb_rx_desc - 1)) - rearm_descs = num_desc; - else { - rearm_descs = (rxq->nb_rx_desc - 1) - id; - rxq->qstats.ring_wrap_cnt++; - } - - /* allocate new buffer */ - if (rte_mempool_get_bulk(rxq->mb_pool, (void *)&rxq->sw_ring[id], - rearm_descs) != 0){ - PMD_DRV_LOG(ERR, "%s(): %d: No MBUFS, queue id = %d," - "mbuf_avail_count = %d," - " mbuf_in_use_count = %d, num_desc_req = %d\n", - __func__, __LINE__, rxq->queue_id, - rte_mempool_avail_count(rxq->mb_pool), - rte_mempool_in_use_count(rxq->mb_pool), rearm_descs); - return -1; - } - - int rearm_cnt = rearm_descs & -2; - __m128i head_room = _mm_set_epi64x(RTE_PKTMBUF_HEADROOM, - RTE_PKTMBUF_HEADROOM); - - for (mbuf_index = 0; mbuf_index < ((uint16_t)rearm_cnt & 0xFFFF); - mbuf_index += RTE_QDMA_DESCS_PER_LOOP, - id += RTE_QDMA_DESCS_PER_LOOP) { - __m128i vaddr0, vaddr1; - __m128i dma_addr; - - /* load buf_addr(lo 64bit) and buf_iova(hi 64bit) */ - RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, buf_iova) != - offsetof(struct rte_mbuf, buf_addr) + 8); - - /* Load two mbufs data addresses */ - vaddr0 = _mm_loadu_si128( - (__m128i *)&(rxq->sw_ring[id]->buf_addr)); - vaddr1 = _mm_loadu_si128( - (__m128i *)&(rxq->sw_ring[id+1]->buf_addr)); - - /* Extract physical addresses of two mbufs */ - dma_addr = _mm_unpackhi_epi64(vaddr0, vaddr1); - - /* Add headroom to dma_addr */ - dma_addr = _mm_add_epi64(dma_addr, head_room); - - /* Write C2H desc with physical dma_addr */ - _mm_storeu_si128((__m128i *)&rx_ring_st[id], dma_addr); - } - - if (rearm_descs & 1) { - mb = rxq->sw_ring[id]; - - /* rearm descriptor */ - rx_ring_st[id].dst_addr = - (uint64_t)mb->buf_iova + - RTE_PKTMBUF_HEADROOM; - id++; - } - - if (unlikely(id >= (rxq->nb_rx_desc - 1))) - id -= (rxq->nb_rx_desc - 1); - - /* Handle from beginning of ring, if ring wrapped */ - rearm_descs = num_desc - rearm_descs; - if (unlikely(rearm_descs)) { - /* allocate new buffer */ - if (rte_mempool_get_bulk(rxq->mb_pool, - (void *)&rxq->sw_ring[id], rearm_descs) != 0) { - PMD_DRV_LOG(ERR, "%s(): %d: No MBUFS, queue id = %d," - "mbuf_avail_count = %d," - " mbuf_in_use_count = %d, num_desc_req = %d\n", - __func__, __LINE__, rxq->queue_id, - rte_mempool_avail_count(rxq->mb_pool), - rte_mempool_in_use_count(rxq->mb_pool), rearm_descs); - - rxq->q_pidx_info.pidx = id; - qdma_dev->hw_access->qdma_queue_pidx_update(rxq->dev, - qdma_dev->is_vf, - rxq->queue_id, 1, &rxq->q_pidx_info); -#ifdef LATENCY_MEASUREMENT - /* start the timer */ - rxq->qstats.pkt_lat.prev = rte_get_timer_cycles(); -#endif - return -1; - } - - for (mbuf_index = 0; - mbuf_index < ((uint16_t)rearm_descs & 0xFFFF); - mbuf_index++, id++) { - mb = rxq->sw_ring[id]; - mb->data_off = RTE_PKTMBUF_HEADROOM; - - /* rearm descriptor */ - rx_ring_st[id].dst_addr = - (uint64_t)mb->buf_iova + - RTE_PKTMBUF_HEADROOM; - } - } - - PMD_DRV_LOG(DEBUG, "%s(): %d: PIDX Update: queue id = %d, " - "num_desc = %d", - __func__, __LINE__, rxq->queue_id, - num_desc); - - /* Make sure writes to the C2H descriptors are - * synchronized before updating PIDX - */ - rte_wmb(); - - rxq->q_pidx_info.pidx = id; - qdma_dev->hw_access->qdma_queue_pidx_update(rxq->dev, - qdma_dev->is_vf, - rxq->queue_id, 1, &rxq->q_pidx_info); - -#ifdef LATENCY_MEASUREMENT - /* start the timer */ - rxq->qstats.pkt_lat.prev = rte_get_timer_cycles(); -#endif - return 0; -} - -/* Receive API for Streaming mode */ -uint16_t qdma_recv_pkts_st_vec(struct qdma_rx_queue *rxq, - struct rte_mbuf **rx_pkts, uint16_t nb_pkts) -{ - uint16_t count_pkts; - struct wb_status *wb_status; - uint16_t nb_pkts_avail = 0; - uint16_t rx_cmpt_tail = 0; - uint16_t cmpt_pidx, c2h_pidx; - uint16_t pending_desc; -#ifdef TEST_64B_DESC_BYPASS - int bypass_desc_sz_idx = qmda_get_desc_sz_idx(rxq->bypass_desc_sz); -#endif - - if (unlikely(rxq->err)) - return 0; - - PMD_DRV_LOG(DEBUG, "recv start on rx queue-id :%d, on " - "tail index:%d number of pkts %d", - rxq->queue_id, rxq->rx_tail, nb_pkts); - wb_status = rxq->wb_status; - rx_cmpt_tail = rxq->cmpt_cidx_info.wrb_cidx; - -#ifdef TEST_64B_DESC_BYPASS - if (unlikely(rxq->en_bypass && - bypass_desc_sz_idx == SW_DESC_CNTXT_64B_BYPASS_DMA)) { - PMD_DRV_LOG(DEBUG, "For RX ST-mode, example" - " design doesn't support 64byte descriptor\n"); - return 0; - } -#endif - cmpt_pidx = wb_status->pidx; - -#ifdef LATENCY_MEASUREMENT - if (cmpt_pidx != rxq->qstats.wrb_pidx) { - /* stop the timer */ - rxq->qstats.pkt_lat.curr = rte_get_timer_cycles(); - c2h_pidx_to_cmpt_pidx_lat[rxq->queue_id][rxq->qstats.lat_cnt] = - rxq->qstats.pkt_lat.curr - rxq->qstats.pkt_lat.prev; - rxq->qstats.lat_cnt = ((rxq->qstats.lat_cnt + 1) % LATENCY_CNT); - } -#endif - - if (rx_cmpt_tail < cmpt_pidx) - nb_pkts_avail = cmpt_pidx - rx_cmpt_tail; - else if (rx_cmpt_tail > cmpt_pidx) - nb_pkts_avail = rxq->nb_rx_cmpt_desc - 1 - rx_cmpt_tail + - cmpt_pidx; - - if (nb_pkts_avail == 0) { - PMD_DRV_LOG(DEBUG, "%s(): %d: nb_pkts_avail = 0\n", - __func__, __LINE__); - return 0; - } - - nb_pkts = RTE_MIN(nb_pkts, RTE_MIN(nb_pkts_avail, QDMA_MAX_BURST_SIZE)); - -#ifdef DUMP_MEMPOOL_USAGE_STATS - PMD_DRV_LOG(DEBUG, "%s(): %d: queue id = %d, mbuf_avail_count = %d, " - "mbuf_in_use_count = %d", - __func__, __LINE__, rxq->queue_id, - rte_mempool_avail_count(rxq->mb_pool), - rte_mempool_in_use_count(rxq->mb_pool)); -#endif //DUMP_MEMPOOL_USAGE_STATS - /* Make sure reads to CMPT ring are synchronized before - * accessing the ring - */ - rte_rmb(); -#ifdef QDMA_LATENCY_OPTIMIZED - adapt_update_counter(rxq, nb_pkts_avail); -#endif //QDMA_LATENCY_OPTIMIZED - - int ret = process_cmpt_ring_vec(rxq, nb_pkts); - if (unlikely(ret)) - return 0; - - if (rxq->status != RTE_ETH_QUEUE_STATE_STARTED) { - PMD_DRV_LOG(DEBUG, "%s(): %d: rxq->status = %d\n", - __func__, __LINE__, rxq->status); - return 0; - } - - count_pkts = prepare_packets_vec(rxq, rx_pkts, nb_pkts); - - c2h_pidx = rxq->q_pidx_info.pidx; - pending_desc = rxq->rx_tail - c2h_pidx - 1; - if (rxq->rx_tail < (c2h_pidx + 1)) - pending_desc = rxq->nb_rx_desc - 2 + rxq->rx_tail - - c2h_pidx; - - rxq->qstats.pidx = rxq->q_pidx_info.pidx; - rxq->qstats.wrb_pidx = rxq->wb_status->pidx; - rxq->qstats.wrb_cidx = rxq->wb_status->cidx; - rxq->qstats.rxq_cmpt_tail = rx_cmpt_tail; - rxq->qstats.pending_desc = pending_desc; - rxq->qstats.mbuf_avail_cnt = rte_mempool_avail_count(rxq->mb_pool); - rxq->qstats.mbuf_in_use_cnt = rte_mempool_in_use_count(rxq->mb_pool); - - /* Batch the PIDX updates, this minimizes overhead on - * descriptor engine - */ - if (pending_desc >= MIN_RX_PIDX_UPDATE_THRESHOLD) - rearm_c2h_ring_vec(rxq, pending_desc); - -#ifdef DUMP_MEMPOOL_USAGE_STATS - PMD_DRV_LOG(DEBUG, "%s(): %d: queue id = %d, mbuf_avail_count = %d," - " mbuf_in_use_count = %d, count_pkts = %d", - __func__, __LINE__, rxq->queue_id, - rte_mempool_avail_count(rxq->mb_pool), - rte_mempool_in_use_count(rxq->mb_pool), count_pkts); -#endif //DUMP_MEMPOOL_USAGE_STATS - - PMD_DRV_LOG(DEBUG, " Recv complete with hw cidx :%d", - rxq->wb_status->cidx); - PMD_DRV_LOG(DEBUG, " Recv complete with hw pidx :%d\n", - rxq->wb_status->pidx); - - return count_pkts; -} - -/** - * DPDK callback for receiving packets in burst. - * - * @param rx_queue - * Generic pointer to Rx queue structure. - * @param[out] rx_pkts - * Array to store received packets. - * @param nb_pkts - * Maximum number of packets in array. - * - * @return - * Number of packets successfully received (<= nb_pkts). - */ -uint16_t qdma_recv_pkts_vec(void *rx_queue, struct rte_mbuf **rx_pkts, - uint16_t nb_pkts) -{ - struct qdma_rx_queue *rxq = rx_queue; - uint32_t count; - - if (rxq->st_mode) - count = qdma_recv_pkts_st_vec(rxq, rx_pkts, nb_pkts); - else - count = qdma_recv_pkts_mm(rxq, rx_pkts, nb_pkts); - - return count; -} - -/* Transmit API for Streaming mode */ -uint16_t qdma_xmit_pkts_st_vec(struct qdma_tx_queue *txq, - struct rte_mbuf **tx_pkts, uint16_t nb_pkts) -{ - struct rte_mbuf *mb; - uint64_t pkt_len = 0; - int avail, in_use, ret, nsegs; - uint16_t cidx = 0; - uint16_t count = 0, id; - struct qdma_pci_dev *qdma_dev = txq->dev->data->dev_private; - -#ifdef TEST_64B_DESC_BYPASS - int bypass_desc_sz_idx = qmda_get_desc_sz_idx(txq->bypass_desc_sz); - - if (unlikely(txq->en_bypass && - bypass_desc_sz_idx == SW_DESC_CNTXT_64B_BYPASS_DMA)) { - return qdma_xmit_64B_desc_bypass(txq, tx_pkts, nb_pkts); - } -#endif - - id = txq->q_pidx_info.pidx; - - /* Make sure reads to Tx ring are synchronized before - * accessing the status descriptor. - */ - rte_rmb(); - - cidx = txq->wb_status->cidx; - -#ifdef LATENCY_MEASUREMENT - uint32_t cidx_cnt = 0; - if (cidx != txq->qstats.wrb_cidx) { - if ((cidx - txq->qstats.wrb_cidx) > 0) { - cidx_cnt = cidx - txq->qstats.wrb_cidx; - - if (cidx_cnt <= 8) - txq->qstats.wrb_cidx_cnt_lt_8++; - else if (cidx_cnt > 8 && cidx_cnt <= 32) - txq->qstats.wrb_cidx_cnt_8_to_32++; - else if (cidx_cnt > 32 && cidx_cnt <= 64) - txq->qstats.wrb_cidx_cnt_32_to_64++; - else - txq->qstats.wrb_cidx_cnt_gt_64++; - } - - /* stop the timer */ - txq->qstats.pkt_lat.curr = rte_get_timer_cycles(); - h2c_pidx_to_hw_cidx_lat[txq->queue_id][txq->qstats.lat_cnt] = - txq->qstats.pkt_lat.curr - txq->qstats.pkt_lat.prev; - txq->qstats.lat_cnt = ((txq->qstats.lat_cnt + 1) % LATENCY_CNT); - } else { - txq->qstats.wrb_cidx_cnt_no_change++; - } -#endif - - PMD_DRV_LOG(DEBUG, "Xmit start on tx queue-id:%d, tail index:%d\n", - txq->queue_id, id); - - /* Free transmitted mbufs back to pool */ - reclaim_tx_mbuf(txq, cidx, 0); - - in_use = (int)id - cidx; - if (in_use < 0) - in_use += (txq->nb_tx_desc - 1); - - /* Make 1 less available, otherwise if we allow all descriptors - * to be filled, when nb_pkts = nb_tx_desc - 1, pidx will be same - * as old pidx and HW will treat this as no new descriptors were added. - * Hence, DMA won't happen with new descriptors. - */ - avail = txq->nb_tx_desc - 2 - in_use; - - if (unlikely(!avail)) { - txq->qstats.txq_full_cnt++; - PMD_DRV_LOG(DEBUG, "Tx queue full, in_use = %d", in_use); - return 0; - } - - for (count = 0; count < nb_pkts; count++) { - mb = tx_pkts[count]; - nsegs = mb->nb_segs; - if (nsegs > avail) { - /* Number of segments in current mbuf are greater - * than number of descriptors available, - * hence update PIDX and return - */ - break; - } - avail -= nsegs; - id = txq->q_pidx_info.pidx; - txq->sw_ring[id] = mb; - pkt_len += rte_pktmbuf_pkt_len(mb); - - ret = qdma_ul_update_st_h2c_desc_vec(txq, txq->offloads, mb); - - if (unlikely(ret < 0)) - break; - } - - txq->stats.pkts += count; - txq->stats.bytes += pkt_len; - - txq->qstats.pidx = id; - txq->qstats.wrb_cidx = cidx; - txq->qstats.txq_tail = txq->tx_fl_tail; - txq->qstats.in_use_desc = in_use; - txq->qstats.nb_pkts = nb_pkts; - -#if (MIN_TX_PIDX_UPDATE_THRESHOLD > 1) - rte_spinlock_lock(&txq->pidx_update_lock); -#endif - txq->tx_desc_pend += count; - - /* Send PIDX update only if pending desc is more than threshold - * Saves frequent Hardware transactions - */ - if (txq->tx_desc_pend >= MIN_TX_PIDX_UPDATE_THRESHOLD) { - qdma_dev->hw_access->qdma_queue_pidx_update(txq->dev, - qdma_dev->is_vf, - txq->queue_id, 0, &txq->q_pidx_info); - - txq->tx_desc_pend = 0; - -#ifdef LATENCY_MEASUREMENT - /* start the timer */ - txq->qstats.pkt_lat.prev = rte_get_timer_cycles(); -#endif - } -#if (MIN_TX_PIDX_UPDATE_THRESHOLD > 1) - rte_spinlock_unlock(&txq->pidx_update_lock); -#endif - PMD_DRV_LOG(DEBUG, " xmit completed with count:%d\n", count); - - return count; -} - -/** - * DPDK callback for transmitting packets in burst. - * - * @param tx_queue - * Generic pointer to TX queue structure. - * @param[in] tx_pkts - * Packets to transmit. - * @param nb_pkts - * Number of packets in array. - * - * @return - * Number of packets successfully transmitted (<= nb_pkts). - */ -uint16_t qdma_xmit_pkts_vec(void *tx_queue, struct rte_mbuf **tx_pkts, - uint16_t nb_pkts) -{ - struct qdma_tx_queue *txq = tx_queue; - uint16_t count; - - if (txq->status != RTE_ETH_QUEUE_STATE_STARTED) - return 0; - - if (txq->st_mode) - count = qdma_xmit_pkts_st_vec(txq, tx_pkts, nb_pkts); - else - count = qdma_xmit_pkts_mm(txq, tx_pkts, nb_pkts); - - return count; -} diff --git a/QDMA/DPDK/drivers/net/qdma/qdma_user.c b/QDMA/DPDK/drivers/net/qdma/qdma_user.c deleted file mode 100755 index a487de667..000000000 --- a/QDMA/DPDK/drivers/net/qdma/qdma_user.c +++ /dev/null @@ -1,295 +0,0 @@ -/*- - * BSD LICENSE - * - * Copyright (c) 2019-2022 Xilinx, Inc. All rights reserved. - * Copyright (c) 2022-2023, Advanced Micro Devices, Inc. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * * Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include -#include -#include -#include "qdma_user.h" -#include "qdma_access_common.h" -#include "qdma_log.h" - -#include -#include - -/** - * Extract the fields of given completion entry in the completion ring. - * - * @param ul_cmpt_entry - * Pointer to completion entry to be extracted. - * @param cmpt_info - * Pointer to variable to which completion entry details to be extracted. - * - * @return - * 0 on success and -1 on failure. - */ -int qdma_ul_extract_st_cmpt_info(void *ul_cmpt_entry, void *cmpt_info) -{ - union qdma_ul_st_cmpt_ring *cmpt_data, *cmpt_desc; - - cmpt_desc = (union qdma_ul_st_cmpt_ring *)(ul_cmpt_entry); - cmpt_data = (union qdma_ul_st_cmpt_ring *)(cmpt_info); - - if (unlikely(cmpt_desc->err || cmpt_desc->data_frmt)) - return -1; - - cmpt_data->data = cmpt_desc->data; - if (unlikely(!cmpt_desc->desc_used)) - cmpt_data->length = 0; - - return 0; -} - -/** - * Extract the packet length from the given completion entry. - * - * @param ul_cmpt_entry - * Pointer to completion entry to be extracted. - * - * @return - * Packet length - */ -uint16_t qdma_ul_get_cmpt_pkt_len(void *ul_cmpt_entry) -{ - return ((union qdma_ul_st_cmpt_ring *)ul_cmpt_entry)->length; -} - -/** - * Processes the immediate data for the given completion ring entry - * and stores in a file. - * - * @param qhndl - * Pointer to RX queue handle. - * @param cmpt_desc_len - * Completion descriptor length. - * @param cmpt_entry - * Pointer to completion entry to be processed. - * - * @return - * None. - */ -int qdma_ul_process_immediate_data_st(void *qhndl, void *cmpt_entry, - uint16_t cmpt_desc_len) -{ - int ofd; - char fln[50]; -#ifndef TEST_64B_DESC_BYPASS - uint16_t i = 0; - enum qdma_device_type dev_type; - enum qdma_ip_type ip_type; -#else - int ret = 0; -#endif - uint16_t queue_id = 0; - - queue_id = qdma_get_rx_queue_id(qhndl); - snprintf(fln, sizeof(fln), "q_%d_%s", queue_id, - "immmediate_data.txt"); - ofd = open(fln, O_RDWR | O_CREAT | O_APPEND | - O_SYNC, 0666); - if (ofd < 0) { - PMD_DRV_LOG(INFO, "recv on qhndl[%d] CMPT, " - "unable to create outfile " - " to dump immediate data", - queue_id); - return ofd; - } -#ifdef TEST_64B_DESC_BYPASS - ret = write(ofd, cmpt_entry, cmpt_desc_len); - if (ret < cmpt_desc_len) - PMD_DRV_LOG(DEBUG, "recv on rxq[%d] CMPT, " - "immediate data len: %d, " - "written to outfile :%d bytes", - queue_id, cmpt_desc_len, - ret); -#else - qdma_get_device_info(qhndl, &dev_type, &ip_type); - - if (ip_type == QDMA_VERSAL_HARD_IP && - dev_type == QDMA_DEVICE_VERSAL_CPM4) { - //Ignoring first 20 bits of length feild - dprintf(ofd, "%02x", - (*((uint8_t *)cmpt_entry + 2) & 0xF0)); - for (i = 3; i < (cmpt_desc_len) ; i++) - dprintf(ofd, "%02x", - *((uint8_t *)cmpt_entry + i)); - } else { - dprintf(ofd, "%02x", - (*((uint8_t *)cmpt_entry) & 0xF0)); - for (i = 1; i < (cmpt_desc_len) ; i++) - dprintf(ofd, "%02x", - *((uint8_t *)cmpt_entry + i)); - } -#endif - - close(ofd); - return 0; -} - -/** - * Updates the ST H2C descriptor. - * - * @param qhndl - * Pointer to TX queue handle. - * @param q_offloads - * Offloads supported for the queue. - * @param mb - * Pointer to memory buffer. - * - * @return - * None. - */ -int qdma_ul_update_st_h2c_desc(void *qhndl, uint64_t q_offloads, - struct rte_mbuf *mb) -{ - (void)q_offloads; - struct qdma_ul_st_h2c_desc *desc_info; - int nsegs = mb->nb_segs; - int pkt_segs = nsegs; - - if (nsegs == 1) { - desc_info = get_st_h2c_desc(qhndl); - desc_info->len = rte_pktmbuf_data_len(mb); - desc_info->pld_len = desc_info->len; - desc_info->src_addr = mb->buf_iova + mb->data_off; - desc_info->flags = (S_H2C_DESC_F_SOP | S_H2C_DESC_F_EOP); - desc_info->cdh_flags = 0; - return 0; - } - - while (nsegs && mb) { - desc_info = get_st_h2c_desc(qhndl); - - desc_info->len = rte_pktmbuf_data_len(mb); - desc_info->pld_len = desc_info->len; - desc_info->src_addr = mb->buf_iova + mb->data_off; - desc_info->flags = 0; - - desc_info->flags |= (nsegs == pkt_segs) ? S_H2C_DESC_F_SOP : 0; - desc_info->flags |= (nsegs == 1) ? S_H2C_DESC_F_EOP : 0; - - desc_info->cdh_flags = 0; - - nsegs--; - mb = mb->next; - } - - return 0; -} - -/** - * updates the MM c2h descriptor. - * - * @param qhndl - * Pointer to RX queue handle. - * @param mb - * Pointer to memory buffer. - * @param desc - * Pointer to descriptor entry. - * - * @return - * None. - */ -int qdma_ul_update_mm_c2h_desc(void *qhndl, struct rte_mbuf *mb, void *desc) -{ - struct qdma_ul_mm_desc *desc_info = (struct qdma_ul_mm_desc *)desc; - - desc_info->src_addr = get_mm_c2h_ep_addr(qhndl); - /* make it so the data pointer starts there too... */ - mb->data_off = RTE_PKTMBUF_HEADROOM; - /* low 32-bits of phys addr must be 4KB aligned... */ - desc_info->dst_addr = (uint64_t)mb->buf_iova + RTE_PKTMBUF_HEADROOM; - desc_info->dv = 1; - desc_info->eop = 1; - desc_info->sop = 1; - desc_info->len = (int)get_mm_buff_size(qhndl); - - return 0; -} - -/** - * updates the MM h2c descriptor. - * - * @param qhndl - * Pointer to TX queue handle. - * @param mb - * Pointer to memory buffer. - * - * @return - * None. - */ -int qdma_ul_update_mm_h2c_desc(void *qhndl, struct rte_mbuf *mb) -{ - struct qdma_ul_mm_desc *desc_info; - - desc_info = (struct qdma_ul_mm_desc *)get_mm_h2c_desc(qhndl); - desc_info->src_addr = mb->buf_iova + mb->data_off; - desc_info->dst_addr = get_mm_h2c_ep_addr(qhndl); - desc_info->dv = 1; - desc_info->eop = 1; - desc_info->sop = 1; - desc_info->len = rte_pktmbuf_data_len(mb); - - return 0; -} - -/** - * Processes the completion data from the given completion entry. - * - * @param cmpt_entry - * Pointer to completion entry to be processed. - * @param cmpt_desc_len - * Completion descriptor length. - * @param cmpt_buff - * Pointer to the data buffer to which the data will be extracted. - * - * @return - * None. - */ -int qdma_ul_process_immediate_data(void *cmpt_entry, uint16_t cmpt_desc_len, - char *cmpt_buff) -{ - uint16_t i = 0; - char *cmpt_buff_ptr; - struct qdma_ul_cmpt_ring *cmpt_desc = - (struct qdma_ul_cmpt_ring *)(cmpt_entry); - - if (unlikely(cmpt_desc->err || cmpt_desc->data_frmt)) - return -1; - - cmpt_buff_ptr = (char *)cmpt_buff; - *(cmpt_buff_ptr) = (*((uint8_t *)cmpt_desc) & 0xF0); - for (i = 1; i < (cmpt_desc_len); i++) - *(cmpt_buff_ptr + i) = (*((uint8_t *)cmpt_desc + i)); - - return 0; -} diff --git a/QDMA/DPDK/drivers/net/qdma/qdma_user.h b/QDMA/DPDK/drivers/net/qdma/qdma_user.h deleted file mode 100755 index 9c3de6f8c..000000000 --- a/QDMA/DPDK/drivers/net/qdma/qdma_user.h +++ /dev/null @@ -1,253 +0,0 @@ -/*- - * BSD LICENSE - * - * Copyright (c) 2018-2022 Xilinx, Inc. All rights reserved. - * Copyright (c) 2022-2023, Advanced Micro Devices, Inc. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * * Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#ifndef __QDMA_USER_H__ -#define __QDMA_USER_H__ -/** - * @file - * @brief This file contains example design/user logic controlled - * data structures and functions - * The driver is specific to an example design, if the example design - * changes user controlled parameters, this file needs to be modified - * appropriately. - * Structures for Completion entry, Descriptor bypass can be added here. - */ - -#include "qdma_rxtx.h" - /** - * C2H Completion entry structure - * This structure is specific for the example design. - * Processing of this ring happens in qdma_rxtx.c. - */ -union qdma_ul_st_cmpt_ring { - volatile uint64_t data; - struct { - /* For 2018.2 IP, this field determines the - * Standard or User format of completion entry - */ - volatile uint32_t data_frmt:1; - - /* This field inverts every time PIDX wraps - * the completion ring - */ - volatile uint32_t color:1; - - /* Indicates that C2H engine encountered - * a descriptor error - */ - volatile uint32_t err:1; - - /* Indicates that the completion packet - * consumes descriptor in C2H ring - */ - volatile uint32_t desc_used:1; - - /* Indicates length of the data packet */ - volatile uint32_t length:16; - - /* Reserved field */ - volatile uint32_t user_rsv:4; - - /* User logic defined data of - * length based on CMPT entry - * length - */ - volatile uint8_t user_def[]; - }; -}; - - - /** - * Completion entry structure - * This structure is specific for the example design. - * Currently this structure is used for the processing - * of the MM completion ring in rte_pmd_qdma.c. - */ -struct __attribute__ ((packed)) qdma_ul_cmpt_ring -{ - volatile uint32_t data_frmt:1; /* For 2018.2 IP, this field - * determines the Standard or User - * format of completion entry - */ - volatile uint32_t color:1; /* This field inverts every time - * PIDX wraps the completion ring - */ - volatile uint32_t err:1; /* Indicates that C2H engine - * encountered a descriptor - * error - */ - volatile uint32_t rsv:1; /* Reserved */ - volatile uint8_t user_def[]; /* User logic defined data of - * length based on CMPT entry - * length - */ -}; - -/** ST C2H Descriptor **/ -struct __attribute__ ((packed)) qdma_ul_st_c2h_desc -{ - uint64_t dst_addr; -}; - -#define S_H2C_DESC_F_SOP 1 -#define S_H2C_DESC_F_EOP 2 - -/* pld_len and flags members are part of custom descriptor format needed - * by example design for ST loopback and desc bypass - */ - -/** ST H2C Descriptor **/ -struct __attribute__ ((packed)) qdma_ul_st_h2c_desc -{ - volatile uint16_t cdh_flags; - volatile uint16_t pld_len; - volatile uint16_t len; - volatile uint16_t flags; - volatile uint64_t src_addr; -}; - -/** MM Descriptor **/ -struct __attribute__ ((packed)) qdma_ul_mm_desc -{ - volatile uint64_t src_addr; - volatile uint64_t len:28; - volatile uint64_t dv:1; - volatile uint64_t sop:1; - volatile uint64_t eop:1; - volatile uint64_t rsvd:33; - volatile uint64_t dst_addr; - volatile uint64_t rsvd2; -}; - -/** - * Extract the fields of given completion entry in the completion ring. - * - * @param ul_cmpt_entry - * Pointer to completion entry to be extracted. - * @param cmpt_info - * Pointer to structure to which completion entry details needs to be filled. - * - * @return - * 0 on success and -ve on error. - */ -int qdma_ul_extract_st_cmpt_info(void *ul_cmpt_entry, void *cmpt_info); - -/** - * Extract the packet length from the given completion entry. - * - * @param ul_cmpt_entry - * Pointer to completion entry to be extracted. - * - * @return - * Packet length - */ -uint16_t qdma_ul_get_cmpt_pkt_len(void *ul_cmpt_entry); - -/** - * Processes the immediate data for the given completion ring entry - * and stores the immediate data in a file. - * - * @param qhndl - * Pointer to RX queue handle. - * @param cmpt_entry - * Pointer to completion entry to be processed. - * @param cmpt_desc_len - * Completion descriptor length. - * - * @return - * None. - */ -int qdma_ul_process_immediate_data_st(void *qhndl, void *cmpt_entry, - uint16_t cmpt_desc_len); - -/** - * Updates the ST H2C descriptor - * - * @param qhndl - * Pointer to TX queue handle. - * @param q_offloads - * Offloads supported for the queue. - * @param mb - * Pointer to memory buffer. - * - * @return - * None. - */ -int qdma_ul_update_st_h2c_desc(void *qhndl, uint64_t q_offloads, - struct rte_mbuf *mb); - -/** - * Updates the MM c2h descriptor. - * - * @param qhndl - * Pointer to RX queue handle. - * @param mb - * Pointer to memory buffer. - * @param desc - * Pointer to descriptor entry. - * - * @return - * None. - */ -int qdma_ul_update_mm_c2h_desc(void *qhndl, struct rte_mbuf *mb, void *desc); - -/** - * updates the MM h2c descriptor. - * - * @param qhndl - * Pointer to TX queue handle. - * @param mb - * Pointer to memory buffer. - * - * @return - * None. - */ -int qdma_ul_update_mm_h2c_desc(void *qhndl, struct rte_mbuf *mb); - -/** - * Processes the completion data from the given completion entry. - * - * @param cmpt_entry - * Pointer to completion entry to be processed. - * @param cmpt_desc_len - * Completion descriptor length. - * @param cmpt_buff - * Pointer to the data buffer to which the data will be extracted. - * - * @return - * None. - */ -int qdma_ul_process_immediate_data(void *cmpt_entry, uint16_t cmpt_desc_len, - char *cmpt_buff); - -#endif /* ifndef __QDMA_USER_H__ */ diff --git a/QDMA/DPDK/drivers/net/qdma/qdma_vf_ethdev.c b/QDMA/DPDK/drivers/net/qdma/qdma_vf_ethdev.c deleted file mode 100755 index 219af04e1..000000000 --- a/QDMA/DPDK/drivers/net/qdma/qdma_vf_ethdev.c +++ /dev/null @@ -1,1265 +0,0 @@ -/*- - * BSD LICENSE - * - * Copyright (c) 2017-2022 Xilinx, Inc. All rights reserved. - * Copyright (c) 2022-2023, Advanced Micro Devices, Inc. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * * Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include "qdma.h" -#include "version.h" -#include "qdma_access_common.h" -#include "qdma_mbox_protocol.h" -#include "qdma_mbox.h" -#include "qdma_devops.h" - -static int eth_qdma_vf_dev_init(struct rte_eth_dev *dev); -static int eth_qdma_vf_dev_uninit(struct rte_eth_dev *dev); - -/* - * The set of PCI devices this driver supports - */ -static struct rte_pci_id qdma_vf_pci_id_tbl[] = { -#define RTE_PCI_DEV_ID_DECL(vend, dev) {RTE_PCI_DEVICE(vend, dev)}, -#ifndef PCI_VENDOR_ID_XILINX -#define PCI_VENDOR_ID_XILINX 0x10ee -#endif - - /** Gen 1 VF */ - /** PCIe lane width x1 */ - RTE_PCI_DEV_ID_DECL(PCI_VENDOR_ID_XILINX, 0xa011) /* VF on PF 0 */ - RTE_PCI_DEV_ID_DECL(PCI_VENDOR_ID_XILINX, 0xa111) /* VF on PF 1 */ - RTE_PCI_DEV_ID_DECL(PCI_VENDOR_ID_XILINX, 0xa211) /* VF on PF 2 */ - RTE_PCI_DEV_ID_DECL(PCI_VENDOR_ID_XILINX, 0xa311) /* VF on PF 3 */ - /** PCIe lane width x4 */ - RTE_PCI_DEV_ID_DECL(PCI_VENDOR_ID_XILINX, 0xa014) /* VF on PF 0 */ - RTE_PCI_DEV_ID_DECL(PCI_VENDOR_ID_XILINX, 0xa114) /* VF on PF 1 */ - RTE_PCI_DEV_ID_DECL(PCI_VENDOR_ID_XILINX, 0xa214) /* VF on PF 2 */ - RTE_PCI_DEV_ID_DECL(PCI_VENDOR_ID_XILINX, 0xa314) /* VF on PF 3 */ - /** PCIe lane width x8 */ - RTE_PCI_DEV_ID_DECL(PCI_VENDOR_ID_XILINX, 0xa018) /* VF on PF 0 */ - RTE_PCI_DEV_ID_DECL(PCI_VENDOR_ID_XILINX, 0xa118) /* VF on PF 1 */ - RTE_PCI_DEV_ID_DECL(PCI_VENDOR_ID_XILINX, 0xa218) /* VF on PF 2 */ - RTE_PCI_DEV_ID_DECL(PCI_VENDOR_ID_XILINX, 0xa318) /* VF on PF 3 */ - /** PCIe lane width x16 */ - RTE_PCI_DEV_ID_DECL(PCI_VENDOR_ID_XILINX, 0xa01f) /* VF on PF 0 */ - RTE_PCI_DEV_ID_DECL(PCI_VENDOR_ID_XILINX, 0xa11f) /* VF on PF 1 */ - RTE_PCI_DEV_ID_DECL(PCI_VENDOR_ID_XILINX, 0xa21f) /* VF on PF 2 */ - RTE_PCI_DEV_ID_DECL(PCI_VENDOR_ID_XILINX, 0xa31f) /* VF on PF 3 */ - - /** Gen 2 VF */ - /** PCIe lane width x1 */ - RTE_PCI_DEV_ID_DECL(PCI_VENDOR_ID_XILINX, 0xa021) /* VF on PF 0 */ - RTE_PCI_DEV_ID_DECL(PCI_VENDOR_ID_XILINX, 0xa121) /* VF on PF 1 */ - RTE_PCI_DEV_ID_DECL(PCI_VENDOR_ID_XILINX, 0xa221) /* VF on PF 2 */ - RTE_PCI_DEV_ID_DECL(PCI_VENDOR_ID_XILINX, 0xa321) /* VF on PF 3 */ - /** PCIe lane width x4 */ - RTE_PCI_DEV_ID_DECL(PCI_VENDOR_ID_XILINX, 0xa024) /* VF on PF 0 */ - RTE_PCI_DEV_ID_DECL(PCI_VENDOR_ID_XILINX, 0xa124) /* VF on PF 1 */ - RTE_PCI_DEV_ID_DECL(PCI_VENDOR_ID_XILINX, 0xa224) /* VF on PF 2 */ - RTE_PCI_DEV_ID_DECL(PCI_VENDOR_ID_XILINX, 0xa324) /* VF on PF 3 */ - /** PCIe lane width x8 */ - RTE_PCI_DEV_ID_DECL(PCI_VENDOR_ID_XILINX, 0xa028) /* VF on PF 0 */ - RTE_PCI_DEV_ID_DECL(PCI_VENDOR_ID_XILINX, 0xa128) /* VF on PF 1 */ - RTE_PCI_DEV_ID_DECL(PCI_VENDOR_ID_XILINX, 0xa228) /* VF on PF 2 */ - RTE_PCI_DEV_ID_DECL(PCI_VENDOR_ID_XILINX, 0xa328) /* VF on PF 3 */ - /** PCIe lane width x16 */ - RTE_PCI_DEV_ID_DECL(PCI_VENDOR_ID_XILINX, 0xa02f) /* VF on PF 0 */ - RTE_PCI_DEV_ID_DECL(PCI_VENDOR_ID_XILINX, 0xa12f) /* VF on PF 1 */ - RTE_PCI_DEV_ID_DECL(PCI_VENDOR_ID_XILINX, 0xa22f) /* VF on PF 2 */ - RTE_PCI_DEV_ID_DECL(PCI_VENDOR_ID_XILINX, 0xa32f) /* VF on PF 3 */ - - /** Gen 3 VF */ - /** PCIe lane width x1 */ - RTE_PCI_DEV_ID_DECL(PCI_VENDOR_ID_XILINX, 0xa031) /* VF on PF 0 */ - RTE_PCI_DEV_ID_DECL(PCI_VENDOR_ID_XILINX, 0xa131) /* VF on PF 1 */ - RTE_PCI_DEV_ID_DECL(PCI_VENDOR_ID_XILINX, 0xa231) /* VF on PF 2 */ - RTE_PCI_DEV_ID_DECL(PCI_VENDOR_ID_XILINX, 0xa331) /* VF on PF 3 */ - /** PCIe lane width x4 */ - RTE_PCI_DEV_ID_DECL(PCI_VENDOR_ID_XILINX, 0xa034) /* VF on PF 0 */ - RTE_PCI_DEV_ID_DECL(PCI_VENDOR_ID_XILINX, 0xa134) /* VF on PF 1 */ - RTE_PCI_DEV_ID_DECL(PCI_VENDOR_ID_XILINX, 0xa234) /* VF on PF 2 */ - RTE_PCI_DEV_ID_DECL(PCI_VENDOR_ID_XILINX, 0xa334) /* VF on PF 3 */ - /** PCIe lane width x8 */ - RTE_PCI_DEV_ID_DECL(PCI_VENDOR_ID_XILINX, 0xa038) /* VF on PF 0 */ - RTE_PCI_DEV_ID_DECL(PCI_VENDOR_ID_XILINX, 0xa138) /* VF on PF 1 */ - RTE_PCI_DEV_ID_DECL(PCI_VENDOR_ID_XILINX, 0xa238) /* VF on PF 2 */ - RTE_PCI_DEV_ID_DECL(PCI_VENDOR_ID_XILINX, 0xa338) /* VF on PF 3 */ - /** PCIe lane width x16 */ - RTE_PCI_DEV_ID_DECL(PCI_VENDOR_ID_XILINX, 0xa03f) /* VF on PF 0 */ - RTE_PCI_DEV_ID_DECL(PCI_VENDOR_ID_XILINX, 0xa13f) /* VF on PF 1 */ - RTE_PCI_DEV_ID_DECL(PCI_VENDOR_ID_XILINX, 0xa23f) /* VF on PF 2 */ - RTE_PCI_DEV_ID_DECL(PCI_VENDOR_ID_XILINX, 0xa33f) /* VF on PF 3 */ - - /** Gen 4 VF */ - /** PCIe lane width x1 */ - RTE_PCI_DEV_ID_DECL(PCI_VENDOR_ID_XILINX, 0xa041) /* VF on PF 0 */ - RTE_PCI_DEV_ID_DECL(PCI_VENDOR_ID_XILINX, 0xa141) /* VF on PF 1 */ - RTE_PCI_DEV_ID_DECL(PCI_VENDOR_ID_XILINX, 0xa241) /* VF on PF 2 */ - RTE_PCI_DEV_ID_DECL(PCI_VENDOR_ID_XILINX, 0xa341) /* VF on PF 3 */ - /** PCIe lane width x4 */ - RTE_PCI_DEV_ID_DECL(PCI_VENDOR_ID_XILINX, 0xa044) /* VF on PF 0 */ - RTE_PCI_DEV_ID_DECL(PCI_VENDOR_ID_XILINX, 0xa144) /* VF on PF 1 */ - RTE_PCI_DEV_ID_DECL(PCI_VENDOR_ID_XILINX, 0xa244) /* VF on PF 2 */ - RTE_PCI_DEV_ID_DECL(PCI_VENDOR_ID_XILINX, 0xa344) /* VF on PF 3 */ - /** PCIe lane width x8 */ - RTE_PCI_DEV_ID_DECL(PCI_VENDOR_ID_XILINX, 0xa048) /* VF on PF 0 */ - RTE_PCI_DEV_ID_DECL(PCI_VENDOR_ID_XILINX, 0xa148) /* VF on PF 1 */ - RTE_PCI_DEV_ID_DECL(PCI_VENDOR_ID_XILINX, 0xa248) /* VF on PF 2 */ - RTE_PCI_DEV_ID_DECL(PCI_VENDOR_ID_XILINX, 0xa348) /* VF on PF 3 */ - - /** Versal */ - /** Gen 1 VF */ - /** PCIe lane width x1 */ - RTE_PCI_DEV_ID_DECL(PCI_VENDOR_ID_XILINX, 0xc011) /* VF on PF 0 */ - RTE_PCI_DEV_ID_DECL(PCI_VENDOR_ID_XILINX, 0xc111) /* VF on PF 1 */ - RTE_PCI_DEV_ID_DECL(PCI_VENDOR_ID_XILINX, 0xc211) /* VF on PF 2 */ - RTE_PCI_DEV_ID_DECL(PCI_VENDOR_ID_XILINX, 0xc311) /* VF on PF 3 */ - /** PCIe lane width x4 */ - RTE_PCI_DEV_ID_DECL(PCI_VENDOR_ID_XILINX, 0xc014) /* VF on PF 0 */ - RTE_PCI_DEV_ID_DECL(PCI_VENDOR_ID_XILINX, 0xc114) /* VF on PF 1 */ - RTE_PCI_DEV_ID_DECL(PCI_VENDOR_ID_XILINX, 0xc214) /* VF on PF 2 */ - RTE_PCI_DEV_ID_DECL(PCI_VENDOR_ID_XILINX, 0xc314) /* VF on PF 3 */ - /** PCIe lane width x8 */ - RTE_PCI_DEV_ID_DECL(PCI_VENDOR_ID_XILINX, 0xc018) /* VF on PF 0 */ - RTE_PCI_DEV_ID_DECL(PCI_VENDOR_ID_XILINX, 0xc118) /* VF on PF 1 */ - RTE_PCI_DEV_ID_DECL(PCI_VENDOR_ID_XILINX, 0xc218) /* VF on PF 2 */ - RTE_PCI_DEV_ID_DECL(PCI_VENDOR_ID_XILINX, 0xc318) /* VF on PF 3 */ - /** PCIe lane width x16 */ - RTE_PCI_DEV_ID_DECL(PCI_VENDOR_ID_XILINX, 0xc01f) /* VF on PF 0 */ - RTE_PCI_DEV_ID_DECL(PCI_VENDOR_ID_XILINX, 0xc11f) /* VF on PF 1 */ - RTE_PCI_DEV_ID_DECL(PCI_VENDOR_ID_XILINX, 0xc21f) /* VF on PF 2 */ - RTE_PCI_DEV_ID_DECL(PCI_VENDOR_ID_XILINX, 0xc31f) /* VF on PF 3 */ - - /** Gen 2 VF */ - /** PCIe lane width x1 */ - RTE_PCI_DEV_ID_DECL(PCI_VENDOR_ID_XILINX, 0xc021) /* VF on PF 0 */ - RTE_PCI_DEV_ID_DECL(PCI_VENDOR_ID_XILINX, 0xc121) /* VF on PF 1 */ - RTE_PCI_DEV_ID_DECL(PCI_VENDOR_ID_XILINX, 0xc221) /* VF on PF 2 */ - RTE_PCI_DEV_ID_DECL(PCI_VENDOR_ID_XILINX, 0xc321) /* VF on PF 3 */ - /** PCIe lane width x4 */ - RTE_PCI_DEV_ID_DECL(PCI_VENDOR_ID_XILINX, 0xc024) /* VF on PF 0 */ - RTE_PCI_DEV_ID_DECL(PCI_VENDOR_ID_XILINX, 0xc124) /* VF on PF 1 */ - RTE_PCI_DEV_ID_DECL(PCI_VENDOR_ID_XILINX, 0xc224) /* VF on PF 2 */ - RTE_PCI_DEV_ID_DECL(PCI_VENDOR_ID_XILINX, 0xc324) /* VF on PF 3 */ - /** PCIe lane width x8 */ - RTE_PCI_DEV_ID_DECL(PCI_VENDOR_ID_XILINX, 0xc028) /* VF on PF 0 */ - RTE_PCI_DEV_ID_DECL(PCI_VENDOR_ID_XILINX, 0xc128) /* VF on PF 1 */ - RTE_PCI_DEV_ID_DECL(PCI_VENDOR_ID_XILINX, 0xc228) /* VF on PF 2 */ - RTE_PCI_DEV_ID_DECL(PCI_VENDOR_ID_XILINX, 0xc328) /* VF on PF 3 */ - /** PCIe lane width x16 */ - RTE_PCI_DEV_ID_DECL(PCI_VENDOR_ID_XILINX, 0xc02f) /* VF on PF 0 */ - RTE_PCI_DEV_ID_DECL(PCI_VENDOR_ID_XILINX, 0xc12f) /* VF on PF 1 */ - RTE_PCI_DEV_ID_DECL(PCI_VENDOR_ID_XILINX, 0xc22f) /* VF on PF 2 */ - RTE_PCI_DEV_ID_DECL(PCI_VENDOR_ID_XILINX, 0xc32f) /* VF on PF 3 */ - - /** Gen 3 VF */ - /** PCIe lane width x1 */ - RTE_PCI_DEV_ID_DECL(PCI_VENDOR_ID_XILINX, 0xc031) /* VF on PF 0 */ - RTE_PCI_DEV_ID_DECL(PCI_VENDOR_ID_XILINX, 0xc131) /* VF on PF 1 */ - RTE_PCI_DEV_ID_DECL(PCI_VENDOR_ID_XILINX, 0xc231) /* VF on PF 2 */ - RTE_PCI_DEV_ID_DECL(PCI_VENDOR_ID_XILINX, 0xc331) /* VF on PF 3 */ - /** PCIe lane width x4 */ - RTE_PCI_DEV_ID_DECL(PCI_VENDOR_ID_XILINX, 0xc034) /* VF on PF 0 */ - RTE_PCI_DEV_ID_DECL(PCI_VENDOR_ID_XILINX, 0xc134) /* VF on PF 1 */ - RTE_PCI_DEV_ID_DECL(PCI_VENDOR_ID_XILINX, 0xc234) /* VF on PF 2 */ - RTE_PCI_DEV_ID_DECL(PCI_VENDOR_ID_XILINX, 0xc334) /* VF on PF 3 */ - /** PCIe lane width x8 */ - RTE_PCI_DEV_ID_DECL(PCI_VENDOR_ID_XILINX, 0xc038) /* VF on PF 0 */ - RTE_PCI_DEV_ID_DECL(PCI_VENDOR_ID_XILINX, 0xc138) /* VF on PF 1 */ - RTE_PCI_DEV_ID_DECL(PCI_VENDOR_ID_XILINX, 0xc238) /* VF on PF 2 */ - RTE_PCI_DEV_ID_DECL(PCI_VENDOR_ID_XILINX, 0xc338) /* VF on PF 3 */ - /** PCIe lane width x16 */ - RTE_PCI_DEV_ID_DECL(PCI_VENDOR_ID_XILINX, 0xc03f) /* VF on PF 0 */ - RTE_PCI_DEV_ID_DECL(PCI_VENDOR_ID_XILINX, 0xc13f) /* VF on PF 1 */ - RTE_PCI_DEV_ID_DECL(PCI_VENDOR_ID_XILINX, 0xc23f) /* VF on PF 2 */ - RTE_PCI_DEV_ID_DECL(PCI_VENDOR_ID_XILINX, 0xc33f) /* VF on PF 3 */ - - /** Gen 4 VF */ - /** PCIe lane width x1 */ - RTE_PCI_DEV_ID_DECL(PCI_VENDOR_ID_XILINX, 0xc041) /* VF on PF 0 */ - RTE_PCI_DEV_ID_DECL(PCI_VENDOR_ID_XILINX, 0xc141) /* VF on PF 1 */ - RTE_PCI_DEV_ID_DECL(PCI_VENDOR_ID_XILINX, 0xc241) /* VF on PF 2 */ - RTE_PCI_DEV_ID_DECL(PCI_VENDOR_ID_XILINX, 0xc341) /* VF on PF 3 */ - /** PCIe lane width x4 */ - RTE_PCI_DEV_ID_DECL(PCI_VENDOR_ID_XILINX, 0xc044) /* VF on PF 0 */ - RTE_PCI_DEV_ID_DECL(PCI_VENDOR_ID_XILINX, 0xc144) /* VF on PF 1 */ - RTE_PCI_DEV_ID_DECL(PCI_VENDOR_ID_XILINX, 0xc244) /* VF on PF 2 */ - RTE_PCI_DEV_ID_DECL(PCI_VENDOR_ID_XILINX, 0xc344) /* VF on PF 3 */ - /** PCIe lane width x8 */ - RTE_PCI_DEV_ID_DECL(PCI_VENDOR_ID_XILINX, 0xc048) /* VF on PF 0 */ - RTE_PCI_DEV_ID_DECL(PCI_VENDOR_ID_XILINX, 0xc148) /* VF on PF 1 */ - RTE_PCI_DEV_ID_DECL(PCI_VENDOR_ID_XILINX, 0xc248) /* VF on PF 2 */ - RTE_PCI_DEV_ID_DECL(PCI_VENDOR_ID_XILINX, 0xc348) /* VF on PF 3 */ - - /** Gen 5 VF */ - /** PCIe lane width x8 */ - RTE_PCI_DEV_ID_DECL(PCI_VENDOR_ID_XILINX, 0xc058) /* VF on PF 0 */ - RTE_PCI_DEV_ID_DECL(PCI_VENDOR_ID_XILINX, 0xc158) /* VF on PF 1 */ - RTE_PCI_DEV_ID_DECL(PCI_VENDOR_ID_XILINX, 0xc258) /* VF on PF 2 */ - RTE_PCI_DEV_ID_DECL(PCI_VENDOR_ID_XILINX, 0xc358) /* VF on PF 3 */ - - { .vendor_id = 0, /* sentinel */ }, -}; - -static int qdma_ethdev_online(struct rte_eth_dev *dev) -{ - int rv = 0; - int qbase = -1; - struct qdma_pci_dev *qdma_dev = dev->data->dev_private; - struct qdma_mbox_msg *m = qdma_mbox_msg_alloc(); - - if (!m) - return -ENOMEM; - - qmda_mbox_compose_vf_online(qdma_dev->func_id, 0, &qbase, m->raw_data); - - rv = qdma_mbox_msg_send(dev, m, MBOX_OP_RSP_TIMEOUT); - if (rv < 0) - PMD_DRV_LOG(ERR, "%x, send hello failed %d.\n", - qdma_dev->func_id, rv); - - rv = qdma_mbox_vf_dev_info_get(m->raw_data, - &qdma_dev->dev_cap, - &qdma_dev->dma_device_index); - - if (rv < 0) - PMD_DRV_LOG(ERR, "%x, failed to get dev info %d.\n", - qdma_dev->func_id, rv); - else { - qdma_mbox_msg_free(m); - } - return rv; -} - -static int qdma_ethdev_offline(struct rte_eth_dev *dev) -{ - int rv; - struct qdma_pci_dev *qdma_dev = dev->data->dev_private; - struct qdma_mbox_msg *m = qdma_mbox_msg_alloc(); - - if (!m) - return -ENOMEM; - - qdma_mbox_compose_vf_offline(qdma_dev->func_id, m->raw_data); - - rv = qdma_mbox_msg_send(dev, m, 0); - if (rv < 0) - PMD_DRV_LOG(ERR, "%x, send bye failed %d.\n", - qdma_dev->func_id, rv); - - return rv; -} - -static int qdma_vf_set_qrange(struct rte_eth_dev *dev) -{ - struct qdma_pci_dev *qdma_dev = dev->data->dev_private; - struct qdma_mbox_msg *m; - int rv = 0; - - - m = qdma_mbox_msg_alloc(); - if (!m) - return -ENOMEM; - - qdma_mbox_compose_vf_fmap_prog(qdma_dev->func_id, - (uint16_t)qdma_dev->qsets_en, - (int)qdma_dev->queue_base, - m->raw_data); - rv = qdma_mbox_msg_send(dev, m, MBOX_OP_RSP_TIMEOUT); - if (rv < 0) { - if (rv != -ENODEV) - PMD_DRV_LOG(ERR, "%x set q range (fmap) failed %d.\n", - qdma_dev->func_id, rv); - goto err_out; - } - - rv = qdma_mbox_vf_response_status(m->raw_data); - -err_out: - qdma_mbox_msg_free(m); - return rv; -} - -static int qdma_set_qmax(struct rte_eth_dev *dev, int *qmax, int *qbase) -{ - struct qdma_mbox_msg *m; - int rv = 0; - struct qdma_pci_dev *qdma_dev = dev->data->dev_private; - - m = qdma_mbox_msg_alloc(); - if (!m) - return -ENOMEM; - - qdma_mbox_compose_vf_qreq(qdma_dev->func_id, (uint16_t)*qmax & 0xFFFF, - *qbase, m->raw_data); - rv = qdma_mbox_msg_send(dev, m, MBOX_OP_RSP_TIMEOUT); - if (rv < 0) { - PMD_DRV_LOG(ERR, "%x set q max failed %d.\n", - qdma_dev->func_id, rv); - goto err_out; - } - - rv = qdma_mbox_vf_qinfo_get(m->raw_data, qbase, (uint16_t *)qmax); -err_out: - qdma_mbox_msg_free(m); - return rv; -} - -static int qdma_rxq_context_setup(struct rte_eth_dev *dev, uint16_t qid) -{ - struct qdma_pci_dev *qdma_dev = dev->data->dev_private; - uint32_t qid_hw; - struct qdma_mbox_msg *m = qdma_mbox_msg_alloc(); - struct mbox_descq_conf descq_conf; - int rv, bypass_desc_sz_idx; - struct qdma_rx_queue *rxq; - uint8_t cmpt_desc_fmt; - enum mbox_cmpt_ctxt_type cmpt_ctxt_type = QDMA_MBOX_CMPT_CTXT_NONE; - - if (!m) - return -ENOMEM; - memset(&descq_conf, 0, sizeof(struct mbox_descq_conf)); - rxq = (struct qdma_rx_queue *)dev->data->rx_queues[qid]; - qid_hw = qdma_dev->queue_base + rxq->queue_id; - - switch (rxq->cmpt_desc_len) { - case RTE_PMD_QDMA_CMPT_DESC_LEN_8B: - cmpt_desc_fmt = CMPT_CNTXT_DESC_SIZE_8B; - break; - case RTE_PMD_QDMA_CMPT_DESC_LEN_16B: - cmpt_desc_fmt = CMPT_CNTXT_DESC_SIZE_16B; - break; - case RTE_PMD_QDMA_CMPT_DESC_LEN_32B: - cmpt_desc_fmt = CMPT_CNTXT_DESC_SIZE_32B; - break; - case RTE_PMD_QDMA_CMPT_DESC_LEN_64B: - if (!qdma_dev->dev_cap.cmpt_desc_64b) { - PMD_DRV_LOG(ERR, "PF-%d(DEVFN) 64B is not supported in this " - "mode:\n", qdma_dev->func_id); - return -1; - } - cmpt_desc_fmt = CMPT_CNTXT_DESC_SIZE_64B; - break; - default: - cmpt_desc_fmt = CMPT_CNTXT_DESC_SIZE_8B; - break; - } - descq_conf.ring_bs_addr = rxq->rx_mz->iova; - descq_conf.en_bypass = rxq->en_bypass; - descq_conf.irq_arm = 0; - descq_conf.at = 0; - descq_conf.wbk_en = 1; - descq_conf.irq_en = 0; - - bypass_desc_sz_idx = qmda_get_desc_sz_idx(rxq->bypass_desc_sz); - - if (!rxq->st_mode) {/* mm c2h */ - descq_conf.desc_sz = SW_DESC_CNTXT_MEMORY_MAP_DMA; - descq_conf.wbi_intvl_en = 1; - descq_conf.wbi_chk = 1; - } else {/* st c2h*/ - descq_conf.desc_sz = SW_DESC_CNTXT_C2H_STREAM_DMA; - descq_conf.forced_en = 1; - descq_conf.cmpt_ring_bs_addr = rxq->rx_cmpt_mz->iova; - descq_conf.cmpt_desc_sz = cmpt_desc_fmt; - descq_conf.triggermode = rxq->triggermode; - - descq_conf.cmpt_color = CMPT_DEFAULT_COLOR_BIT; - descq_conf.cmpt_full_upd = 0; - descq_conf.cnt_thres = - qdma_dev->g_c2h_cnt_th[rxq->threshidx]; - descq_conf.timer_thres = - qdma_dev->g_c2h_timer_cnt[rxq->timeridx]; - descq_conf.cmpt_ringsz = - qdma_dev->g_ring_sz[rxq->cmpt_ringszidx] - 1; - descq_conf.bufsz = qdma_dev->g_c2h_buf_sz[rxq->buffszidx]; - descq_conf.cmpt_int_en = 0; - descq_conf.cmpl_stat_en = rxq->st_mode; - descq_conf.pfch_en = rxq->en_prefetch; - descq_conf.en_bypass_prefetch = rxq->en_bypass_prefetch; - if (qdma_dev->dev_cap.cmpt_ovf_chk_dis) - descq_conf.dis_overflow_check = rxq->dis_overflow_check; - - cmpt_ctxt_type = QDMA_MBOX_CMPT_WITH_ST; - } - - if (rxq->en_bypass && - (rxq->bypass_desc_sz != 0)) - descq_conf.desc_sz = bypass_desc_sz_idx; - - descq_conf.func_id = rxq->func_id; - descq_conf.ringsz = qdma_dev->g_ring_sz[rxq->ringszidx] - 1; - - qdma_mbox_compose_vf_qctxt_write(rxq->func_id, qid_hw, rxq->st_mode, 1, - cmpt_ctxt_type, - &descq_conf, m->raw_data); - - rv = qdma_mbox_msg_send(dev, m, MBOX_OP_RSP_TIMEOUT); - if (rv < 0) { - PMD_DRV_LOG(ERR, "%x, qid_hw 0x%x, mbox failed %d.\n", - qdma_dev->func_id, qid_hw, rv); - goto err_out; - } - - rv = qdma_mbox_vf_response_status(m->raw_data); - -err_out: - qdma_mbox_msg_free(m); - return rv; -} - -static int qdma_txq_context_setup(struct rte_eth_dev *dev, uint16_t qid) -{ - struct qdma_pci_dev *qdma_dev = dev->data->dev_private; - struct qdma_mbox_msg *m = qdma_mbox_msg_alloc(); - struct mbox_descq_conf descq_conf; - int rv, bypass_desc_sz_idx; - struct qdma_tx_queue *txq; - uint32_t qid_hw; - - if (!m) - return -ENOMEM; - memset(&descq_conf, 0, sizeof(struct mbox_descq_conf)); - txq = (struct qdma_tx_queue *)dev->data->tx_queues[qid]; - qid_hw = qdma_dev->queue_base + txq->queue_id; - descq_conf.ring_bs_addr = txq->tx_mz->iova; - descq_conf.en_bypass = txq->en_bypass; - descq_conf.wbi_intvl_en = 1; - descq_conf.wbi_chk = 1; - descq_conf.wbk_en = 1; - - bypass_desc_sz_idx = qmda_get_desc_sz_idx(txq->bypass_desc_sz); - - if (!txq->st_mode) /* mm h2c */ - descq_conf.desc_sz = SW_DESC_CNTXT_MEMORY_MAP_DMA; - else /* st h2c */ - descq_conf.desc_sz = SW_DESC_CNTXT_H2C_STREAM_DMA; - descq_conf.func_id = txq->func_id; - descq_conf.ringsz = qdma_dev->g_ring_sz[txq->ringszidx] - 1; - - if (txq->en_bypass && - (txq->bypass_desc_sz != 0)) - descq_conf.desc_sz = bypass_desc_sz_idx; - - qdma_mbox_compose_vf_qctxt_write(txq->func_id, qid_hw, txq->st_mode, 0, - QDMA_MBOX_CMPT_CTXT_NONE, - &descq_conf, m->raw_data); - - rv = qdma_mbox_msg_send(dev, m, MBOX_OP_RSP_TIMEOUT); - if (rv < 0) { - PMD_DRV_LOG(ERR, "%x, qid_hw 0x%x, mbox failed %d.\n", - qdma_dev->func_id, qid_hw, rv); - goto err_out; - } - - rv = qdma_mbox_vf_response_status(m->raw_data); - -err_out: - qdma_mbox_msg_free(m); - return rv; -} - -static int qdma_queue_context_invalidate(struct rte_eth_dev *dev, uint32_t qid, - bool st, bool c2h) -{ - struct qdma_mbox_msg *m = qdma_mbox_msg_alloc(); - struct qdma_pci_dev *qdma_dev = dev->data->dev_private; - uint32_t qid_hw; - int rv; - enum mbox_cmpt_ctxt_type cmpt_ctxt_type = QDMA_MBOX_CMPT_CTXT_NONE; - - if (!m) - return -ENOMEM; - - if (st && c2h) - cmpt_ctxt_type = QDMA_MBOX_CMPT_WITH_ST; - qid_hw = qdma_dev->queue_base + qid; - qdma_mbox_compose_vf_qctxt_invalidate(qdma_dev->func_id, qid_hw, - st, c2h, cmpt_ctxt_type, - m->raw_data); - rv = qdma_mbox_msg_send(dev, m, MBOX_OP_RSP_TIMEOUT); - if (rv < 0) { - if (rv != -ENODEV) - PMD_DRV_LOG(INFO, "%x, qid_hw 0x%x mbox failed %d.\n", - qdma_dev->func_id, qid_hw, rv); - goto err_out; - } - - rv = qdma_mbox_vf_response_status(m->raw_data); - -err_out: - qdma_mbox_msg_free(m); - return rv; -} - -static int qdma_vf_dev_start(struct rte_eth_dev *dev) -{ - struct qdma_tx_queue *txq; - struct qdma_rx_queue *rxq; - uint32_t qid; - int err; - - PMD_DRV_LOG(INFO, "qdma_dev_start: Starting\n"); - /* prepare descriptor rings for operation */ - for (qid = 0; qid < dev->data->nb_tx_queues; qid++) { - txq = (struct qdma_tx_queue *)dev->data->tx_queues[qid]; - - /*Deferred Queues should not start with dev_start*/ - if (!txq->tx_deferred_start) { - err = qdma_vf_dev_tx_queue_start(dev, qid); - if (err != 0) - return err; - } - } - - for (qid = 0; qid < dev->data->nb_rx_queues; qid++) { - rxq = (struct qdma_rx_queue *)dev->data->rx_queues[qid]; - - /*Deferred Queues should not start with dev_start*/ - if (!rxq->rx_deferred_start) { - err = qdma_vf_dev_rx_queue_start(dev, qid); - if (err != 0) - return err; - } - } - return 0; -} - -static int qdma_vf_dev_link_update(struct rte_eth_dev *dev, - __rte_unused int wait_to_complete) -{ - dev->data->dev_link.link_status = ETH_LINK_UP; - dev->data->dev_link.link_duplex = ETH_LINK_FULL_DUPLEX; - - /* TODO: Configure link speed by reading hardware capabilities */ - dev->data->dev_link.link_speed = ETH_SPEED_NUM_200G; - - PMD_DRV_LOG(INFO, "Link update done\n"); - - return 0; -} - -static int qdma_vf_dev_infos_get(__rte_unused struct rte_eth_dev *dev, - struct rte_eth_dev_info *dev_info) -{ - struct qdma_pci_dev *qdma_dev = dev->data->dev_private; - - dev_info->max_rx_queues = qdma_dev->dev_cap.num_qs; - dev_info->max_tx_queues = qdma_dev->dev_cap.num_qs; - - dev_info->min_rx_bufsize = QDMA_MIN_RXBUFF_SIZE; - dev_info->max_rx_pktlen = DMA_BRAM_SIZE; - dev_info->max_mac_addrs = 1; - - return 0; -} - -static int qdma_vf_dev_stop(struct rte_eth_dev *dev) -{ -#ifdef RTE_LIBRTE_QDMA_DEBUG_DRIVER - struct qdma_pci_dev *qdma_dev = dev->data->dev_private; -#endif - uint32_t qid; - - /* reset driver's internal queue structures to default values */ - PMD_DRV_LOG(INFO, "VF-%d(DEVFN) Stop H2C & C2H queues", - qdma_dev->func_id); - for (qid = 0; qid < dev->data->nb_tx_queues; qid++) - qdma_vf_dev_tx_queue_stop(dev, qid); - for (qid = 0; qid < dev->data->nb_rx_queues; qid++) - qdma_vf_dev_rx_queue_stop(dev, qid); - - return 0; -} - -int qdma_vf_dev_close(struct rte_eth_dev *dev) -{ - struct qdma_pci_dev *qdma_dev = dev->data->dev_private; - struct qdma_tx_queue *txq; - struct qdma_rx_queue *rxq; - struct qdma_cmpt_queue *cmptq; - uint32_t qid; - - PMD_DRV_LOG(INFO, "Closing all queues\n"); - - if (dev->data->dev_started) - qdma_vf_dev_stop(dev); - - /* iterate over rx queues */ - for (qid = 0; qid < dev->data->nb_rx_queues; ++qid) { - rxq = dev->data->rx_queues[qid]; - if (rxq != NULL) { - PMD_DRV_LOG(INFO, "VF-%d(DEVFN) Remove C2H queue: %d", - qdma_dev->func_id, qid); - - qdma_dev_notify_qdel(rxq->dev, rxq->queue_id + - qdma_dev->queue_base, - QDMA_DEV_Q_TYPE_C2H); - - if (rxq->st_mode) - qdma_dev_notify_qdel(rxq->dev, rxq->queue_id + - qdma_dev->queue_base, - QDMA_DEV_Q_TYPE_CMPT); - - if (rxq->sw_ring) - rte_free(rxq->sw_ring); - - if (rxq->st_mode) { /** if ST-mode **/ - if (rxq->rx_cmpt_mz) - rte_memzone_free(rxq->rx_cmpt_mz); - } - - if (rxq->rx_mz) - rte_memzone_free(rxq->rx_mz); - rte_free(rxq); - PMD_DRV_LOG(INFO, "VF-%d(DEVFN) C2H queue %d removed", - qdma_dev->func_id, qid); - } - } - - /* iterate over tx queues */ - for (qid = 0; qid < dev->data->nb_tx_queues; ++qid) { - txq = dev->data->tx_queues[qid]; - if (txq != NULL) { - PMD_DRV_LOG(INFO, "VF-%d(DEVFN) Remove H2C queue: %d", - qdma_dev->func_id, qid); - - qdma_dev_notify_qdel(txq->dev, txq->queue_id + - qdma_dev->queue_base, - QDMA_DEV_Q_TYPE_H2C); - if (txq->sw_ring) - rte_free(txq->sw_ring); - if (txq->tx_mz) - rte_memzone_free(txq->tx_mz); - rte_free(txq); - PMD_DRV_LOG(INFO, "VF-%d(DEVFN) H2C queue %d removed", - qdma_dev->func_id, qid); - } - } - if (qdma_dev->dev_cap.mm_cmpt_en) { - /* iterate over cmpt queues */ - for (qid = 0; qid < qdma_dev->qsets_en; ++qid) { - cmptq = qdma_dev->cmpt_queues[qid]; - if (cmptq != NULL) { - PMD_DRV_LOG(INFO, "VF-%d(DEVFN) Remove CMPT queue: %d", - qdma_dev->func_id, qid); - qdma_dev_notify_qdel(cmptq->dev, - cmptq->queue_id + - qdma_dev->queue_base, - QDMA_DEV_Q_TYPE_CMPT); - if (cmptq->cmpt_mz) - rte_memzone_free(cmptq->cmpt_mz); - rte_free(cmptq); - PMD_DRV_LOG(INFO, "VF-%d(DEVFN) CMPT queue %d removed", - qdma_dev->func_id, qid); - } - } - - if (qdma_dev->cmpt_queues != NULL) { - rte_free(qdma_dev->cmpt_queues); - qdma_dev->cmpt_queues = NULL; - } - } - - qdma_dev->qsets_en = 0; - qdma_set_qmax(dev, (int *)&qdma_dev->qsets_en, - (int *)&qdma_dev->queue_base); - qdma_dev->init_q_range = 0; - rte_free(qdma_dev->q_info); - qdma_dev->q_info = NULL; - qdma_dev->dev_configured = 0; - - return 0; -} - -static int qdma_vf_dev_reset(struct rte_eth_dev *dev) -{ - struct qdma_pci_dev *qdma_dev = dev->data->dev_private; - uint32_t i = 0; - int ret; - - PMD_DRV_LOG(INFO, "%s: Reset VF-%d(DEVFN)", - __func__, qdma_dev->func_id); - - ret = eth_qdma_vf_dev_uninit(dev); - if (ret) - return ret; - - if (qdma_dev->reset_state == RESET_STATE_IDLE) { - ret = eth_qdma_vf_dev_init(dev); - } else { - - /* VFs do not stop mbox and start waiting for a - * "PF_RESET_DONE" mailbox message from PF - * for a maximum of 60 secs - */ - PMD_DRV_LOG(INFO, - "%s: Waiting for reset done message from PF", - __func__); - while (i < RESET_TIMEOUT) { - if (qdma_dev->reset_state == - RESET_STATE_RECV_PF_RESET_DONE) { - qdma_mbox_uninit(dev); - - ret = eth_qdma_vf_dev_init(dev); - return ret; - } - - rte_delay_ms(1); - i++; - } - } - - if (i >= RESET_TIMEOUT) { - PMD_DRV_LOG(ERR, "%s: Reset failed for VF-%d(DEVFN)\n", - __func__, qdma_dev->func_id); - return -ETIMEDOUT; - } - - return ret; -} - -static int qdma_vf_dev_configure(struct rte_eth_dev *dev) -{ - struct qdma_pci_dev *qdma_dev = dev->data->dev_private; - int32_t ret = 0, queue_base = -1; - uint32_t qid = 0; - - /** FMAP configuration **/ - qdma_dev->qsets_en = RTE_MAX(dev->data->nb_rx_queues, - dev->data->nb_tx_queues); - - if (qdma_dev->qsets_en > qdma_dev->dev_cap.num_qs) { - PMD_DRV_LOG(INFO, "VF-%d(DEVFN) Error: Number of Queues to be " - "configured are greater than the queues " - "supported by the hardware\n", - qdma_dev->func_id); - qdma_dev->qsets_en = 0; - return -1; - } - - /* Request queue base from the resource manager */ - ret = qdma_set_qmax(dev, (int *)&qdma_dev->qsets_en, - (int *)&queue_base); - if (ret != QDMA_SUCCESS) { - PMD_DRV_LOG(ERR, "VF-%d(DEVFN) queue allocation failed: %d\n", - qdma_dev->func_id, ret); - return -1; - } - qdma_dev->queue_base = queue_base; - - qdma_dev->q_info = rte_zmalloc("qinfo", sizeof(struct queue_info) * - qdma_dev->qsets_en, 0); - if (qdma_dev->q_info == NULL) { - PMD_DRV_LOG(INFO, "VF-%d fail to allocate queue info memory\n", - qdma_dev->func_id); - return (-ENOMEM); - } - - /* Reserve memory for cmptq ring pointers - * Max completion queues can be maximum of rx and tx queues. - */ - qdma_dev->cmpt_queues = rte_zmalloc("cmpt_queues", - sizeof(qdma_dev->cmpt_queues[0]) * - qdma_dev->qsets_en, - RTE_CACHE_LINE_SIZE); - if (qdma_dev->cmpt_queues == NULL) { - PMD_DRV_LOG(ERR, "VF-%d(DEVFN) cmpt ring pointers memory " - "allocation failed:\n", qdma_dev->func_id); - rte_free(qdma_dev->q_info); - qdma_dev->q_info = NULL; - return -(ENOMEM); - } - - /* Initialize queue_modes to all 1's ( i.e. Streaming) */ - for (qid = 0 ; qid < qdma_dev->qsets_en; qid++) - qdma_dev->q_info[qid].queue_mode = RTE_PMD_QDMA_STREAMING_MODE; - - for (qid = 0 ; qid < dev->data->nb_rx_queues; qid++) { - qdma_dev->q_info[qid].cmpt_desc_sz = qdma_dev->cmpt_desc_len; - qdma_dev->q_info[qid].rx_bypass_mode = - qdma_dev->c2h_bypass_mode; - qdma_dev->q_info[qid].trigger_mode = qdma_dev->trigger_mode; - qdma_dev->q_info[qid].timer_count = - qdma_dev->timer_count; - } - - for (qid = 0 ; qid < dev->data->nb_tx_queues; qid++) - qdma_dev->q_info[qid].tx_bypass_mode = - qdma_dev->h2c_bypass_mode; - - ret = qdma_vf_set_qrange(dev); - if (ret < 0) { - PMD_DRV_LOG(ERR, "FMAP programming failed\n"); - rte_free(qdma_dev->q_info); - qdma_dev->q_info = NULL; - rte_free(qdma_dev->cmpt_queues); - qdma_dev->cmpt_queues = NULL; - return ret; - } - - qdma_dev->dev_configured = 1; - - return ret; -} - -int qdma_vf_dev_tx_queue_start(struct rte_eth_dev *dev, uint16_t qid) -{ - struct qdma_pci_dev *qdma_dev = dev->data->dev_private; - struct qdma_tx_queue *txq; - - txq = (struct qdma_tx_queue *)dev->data->tx_queues[qid]; - qdma_reset_tx_queue(txq); - - if (qdma_txq_context_setup(dev, qid) < 0) - return -1; - - txq->q_pidx_info.pidx = 0; - qdma_dev->hw_access->qdma_queue_pidx_update(dev, qdma_dev->is_vf, - qid, 0, &txq->q_pidx_info); - - dev->data->tx_queue_state[qid] = RTE_ETH_QUEUE_STATE_STARTED; - txq->status = RTE_ETH_QUEUE_STATE_STARTED; - - return 0; -} - -int qdma_vf_dev_rx_queue_start(struct rte_eth_dev *dev, uint16_t qid) -{ - struct qdma_pci_dev *qdma_dev = dev->data->dev_private; - struct qdma_rx_queue *rxq; - int err; - - rxq = (struct qdma_rx_queue *)dev->data->rx_queues[qid]; - qdma_reset_rx_queue(rxq); - - err = qdma_init_rx_queue(rxq); - if (err != 0) - return err; - if (qdma_rxq_context_setup(dev, qid) < 0) { - PMD_DRV_LOG(ERR, "context_setup for qid - %u failed", qid); - - return -1; - } - - if (rxq->st_mode) { - rxq->cmpt_cidx_info.counter_idx = rxq->threshidx; - rxq->cmpt_cidx_info.timer_idx = rxq->timeridx; - rxq->cmpt_cidx_info.trig_mode = rxq->triggermode; - rxq->cmpt_cidx_info.wrb_en = 1; - qdma_dev->hw_access->qdma_queue_cmpt_cidx_update(dev, 1, - qid, &rxq->cmpt_cidx_info); - - rxq->q_pidx_info.pidx = (rxq->nb_rx_desc - 2); - qdma_dev->hw_access->qdma_queue_pidx_update(dev, 1, - qid, 1, &rxq->q_pidx_info); - } - - dev->data->rx_queue_state[qid] = RTE_ETH_QUEUE_STATE_STARTED; - rxq->status = RTE_ETH_QUEUE_STATE_STARTED; - return 0; -} - -int qdma_vf_dev_rx_queue_stop(struct rte_eth_dev *dev, uint16_t qid) -{ - struct qdma_rx_queue *rxq; - int i = 0, cnt = 0; - - rxq = (struct qdma_rx_queue *)dev->data->rx_queues[qid]; - - rxq->status = RTE_ETH_QUEUE_STATE_STOPPED; - - /* Wait for queue to recv all packets. */ - if (rxq->st_mode) { /** ST-mode **/ - while (rxq->wb_status->pidx != rxq->cmpt_cidx_info.wrb_cidx) { - usleep(10); - if (cnt++ > 10000) - break; - } - } else { /* MM mode */ - while (rxq->wb_status->cidx != rxq->q_pidx_info.pidx) { - usleep(10); - if (cnt++ > 10000) - break; - } - } - - qdma_queue_context_invalidate(dev, qid, rxq->st_mode, 1); - - if (rxq->st_mode) { /** ST-mode **/ -#ifdef DUMP_MEMPOOL_USAGE_STATS - PMD_DRV_LOG(INFO, "%s(): %d: queue id = %d, mbuf_avail_count = " - "%d, mbuf_in_use_count = %d", - __func__, __LINE__, rxq->queue_id, - rte_mempool_avail_count(rxq->mb_pool), - rte_mempool_in_use_count(rxq->mb_pool)); -#endif //DUMP_MEMPOOL_USAGE_STATS - - for (i = 0; i < rxq->nb_rx_desc - 1; i++) { - rte_pktmbuf_free(rxq->sw_ring[i]); - rxq->sw_ring[i] = NULL; - } -#ifdef DUMP_MEMPOOL_USAGE_STATS - PMD_DRV_LOG(INFO, "%s(): %d: queue id = %d, mbuf_avail_count = " - "%d, mbuf_in_use_count = %d", - __func__, __LINE__, rxq->queue_id, - rte_mempool_avail_count(rxq->mb_pool), - rte_mempool_in_use_count(rxq->mb_pool)); -#endif //DUMP_MEMPOOL_USAGE_STATS - } - - qdma_reset_rx_queue(rxq); - dev->data->rx_queue_state[qid] = RTE_ETH_QUEUE_STATE_STOPPED; - return 0; -} - - -int qdma_vf_dev_tx_queue_stop(struct rte_eth_dev *dev, uint16_t qid) -{ - struct qdma_tx_queue *txq; - int i = 0, cnt = 0; - - txq = (struct qdma_tx_queue *)dev->data->tx_queues[qid]; - - txq->status = RTE_ETH_QUEUE_STATE_STOPPED; - /* Wait for TXQ to send out all packets. */ - while (txq->wb_status->cidx != txq->q_pidx_info.pidx) { - usleep(10); - if (cnt++ > 10000) - break; - } - - qdma_queue_context_invalidate(dev, qid, txq->st_mode, 0); - - /* Free mbufs if any pending in the ring */ - for (i = 0; i < txq->nb_tx_desc; i++) { - rte_pktmbuf_free(txq->sw_ring[i]); - txq->sw_ring[i] = NULL; - } - qdma_reset_tx_queue(txq); - dev->data->tx_queue_state[qid] = RTE_ETH_QUEUE_STATE_STOPPED; - return 0; -} - -static struct eth_dev_ops qdma_vf_eth_dev_ops = { - .dev_configure = qdma_vf_dev_configure, - .dev_infos_get = qdma_vf_dev_infos_get, - .dev_start = qdma_vf_dev_start, - .dev_stop = qdma_vf_dev_stop, - .dev_close = qdma_vf_dev_close, - .dev_reset = qdma_vf_dev_reset, - .link_update = qdma_vf_dev_link_update, - .rx_queue_setup = qdma_dev_rx_queue_setup, - .tx_queue_setup = qdma_dev_tx_queue_setup, - .rx_queue_release = qdma_dev_rx_queue_release, - .tx_queue_release = qdma_dev_tx_queue_release, - .rx_queue_start = qdma_vf_dev_rx_queue_start, - .rx_queue_stop = qdma_vf_dev_rx_queue_stop, - .tx_queue_start = qdma_vf_dev_tx_queue_start, - .tx_queue_stop = qdma_vf_dev_tx_queue_stop, - .stats_get = qdma_dev_stats_get, -}; - -/** - * DPDK callback to register a PCI device. - * - * This function creates an Ethernet device for each port of a given - * PCI device. - * - * @param[in] dev - * Pointer to Ethernet device structure. - * - * @return - * 0 on success, negative errno value on failure. - */ -static int eth_qdma_vf_dev_init(struct rte_eth_dev *dev) -{ - struct qdma_pci_dev *dma_priv; - uint8_t *baseaddr; - int i, idx; - static bool once = true; - struct rte_pci_device *pci_dev; - - /* sanity checks */ - if (dev == NULL) - return -EINVAL; - if (dev->data == NULL) - return -EINVAL; - if (dev->data->dev_private == NULL) - return -EINVAL; - - pci_dev = RTE_ETH_DEV_TO_PCI(dev); - if (pci_dev == NULL) - return -EINVAL; - - /* for secondary processes, we don't initialise any further as primary - * has already done this work. - */ - if (rte_eal_process_type() != RTE_PROC_PRIMARY) { - dev->dev_ops = &qdma_vf_eth_dev_ops; - return 0; - } - - if (once) { - RTE_LOG(INFO, PMD, "QDMA PMD VERSION: %s\n", QDMA_PMD_VERSION); - once = false; - } - - /* allocate space for a single Ethernet MAC address */ - dev->data->mac_addrs = rte_zmalloc("qdma_vf", - RTE_ETHER_ADDR_LEN * 1, 0); - if (dev->data->mac_addrs == NULL) - return -ENOMEM; - - /* Copy some dummy Ethernet MAC address for XDMA device - * This will change in real NIC device... - */ - for (i = 0; i < RTE_ETHER_ADDR_LEN; ++i) - dev->data->mac_addrs[0].addr_bytes[i] = 0x15 + i; - - /* Init system & device */ - dma_priv = (struct qdma_pci_dev *)dev->data->dev_private; - dma_priv->func_id = 0; - dma_priv->is_vf = 1; - dma_priv->timer_count = DEFAULT_TIMER_CNT_TRIG_MODE_TIMER; - - dma_priv->en_desc_prefetch = 0; - dma_priv->cmpt_desc_len = DEFAULT_QDMA_CMPT_DESC_LEN; - dma_priv->c2h_bypass_mode = RTE_PMD_QDMA_RX_BYPASS_NONE; - dma_priv->h2c_bypass_mode = 0; - - dev->dev_ops = &qdma_vf_eth_dev_ops; - dev->rx_pkt_burst = &qdma_recv_pkts; - dev->tx_pkt_burst = &qdma_xmit_pkts; - - dma_priv->config_bar_idx = DEFAULT_VF_CONFIG_BAR; - dma_priv->bypass_bar_idx = BAR_ID_INVALID; - dma_priv->user_bar_idx = BAR_ID_INVALID; - - if (qdma_check_kvargs(dev->device->devargs, dma_priv)) { - PMD_DRV_LOG(INFO, "devargs failed\n"); - rte_free(dev->data->mac_addrs); - return -EINVAL; - } - - /* Store BAR address and length of Config BAR */ - baseaddr = (uint8_t *) - pci_dev->mem_resource[dma_priv->config_bar_idx].addr; - dma_priv->bar_addr[dma_priv->config_bar_idx] = baseaddr; - - /*Assigning QDMA access layer function pointers based on the HW design*/ - dma_priv->hw_access = rte_zmalloc("vf_hwaccess", - sizeof(struct qdma_hw_access), 0); - if (dma_priv->hw_access == NULL) { - rte_free(dev->data->mac_addrs); - return -ENOMEM; - } - idx = qdma_hw_access_init(dev, dma_priv->is_vf, dma_priv->hw_access); - if (idx < 0) { - rte_free(dma_priv->hw_access); - rte_free(dev->data->mac_addrs); - return -EINVAL; - } - - idx = qdma_get_hw_version(dev); - if (idx < 0) { - rte_free(dma_priv->hw_access); - rte_free(dev->data->mac_addrs); - return -EINVAL; - } - - idx = qdma_identify_bars(dev); - if (idx < 0) { - rte_free(dma_priv->hw_access); - rte_free(dev->data->mac_addrs); - return -EINVAL; - } - - /* Store BAR address and length of AXI Master Lite BAR(user bar)*/ - if (dma_priv->user_bar_idx >= 0) { - baseaddr = (uint8_t *) - pci_dev->mem_resource[dma_priv->user_bar_idx].addr; - dma_priv->bar_addr[dma_priv->user_bar_idx] = baseaddr; - } - - if (dma_priv->ip_type == QDMA_VERSAL_HARD_IP && - dma_priv->device_type == - QDMA_DEVICE_VERSAL_CPM4) - dma_priv->dev_cap.mailbox_intr = 0; - else - dma_priv->dev_cap.mailbox_intr = 1; - - qdma_mbox_init(dev); - idx = qdma_ethdev_online(dev); - if (idx < 0) { - rte_free(dma_priv->hw_access); - rte_free(dev->data->mac_addrs); - return -EINVAL; - } - - /* Setting default Mode to RTE_PMD_QDMA_TRIG_MODE_USER_TIMER */ - dma_priv->trigger_mode = RTE_PMD_QDMA_TRIG_MODE_USER_TIMER; - - dma_priv->reset_state = RESET_STATE_IDLE; - -#ifdef LATENCY_MEASUREMENT - /* Create txq and rxq latency measurement shared memory - * if not already created by the PF - */ - if (!h2c_pidx_to_hw_cidx_lat) { - /* Create a shared memory zone for the txq latency buffer */ - txq_lat_buf_mz = rte_memzone_reserve("TXQ_LAT_BUFFER_ZONE", - LATENCY_MAX_QUEUES * LATENCY_CNT * sizeof(double), - rte_socket_id(), 0); - if (txq_lat_buf_mz == NULL) { - PMD_DRV_LOG(ERR, - "Failed to allocate txq latency buffer memzone\n"); - return -1; - } - - /* Get the virtual address of the txq latency buffer */ - h2c_pidx_to_hw_cidx_lat = - (double(*)[LATENCY_CNT])txq_lat_buf_mz->addr; - } - - if (!c2h_pidx_to_cmpt_pidx_lat) { - /* Create a shared memory zone for the rxq latency buffer */ - rxq_lat_buf_mz = rte_memzone_reserve("RXQ_LAT_BUFFER_ZONE", - LATENCY_MAX_QUEUES * LATENCY_CNT * sizeof(double), - rte_socket_id(), 0); - if (rxq_lat_buf_mz == NULL) { - PMD_DRV_LOG(ERR, - "Failed to allocate rxq latency buffer memzone\n"); - return -1; - } - - /* Get the virtual address of the rxq latency buffer */ - c2h_pidx_to_cmpt_pidx_lat = - (double(*)[LATENCY_CNT])rxq_lat_buf_mz->addr; - } -#endif - - PMD_DRV_LOG(INFO, "VF-%d(DEVFN) QDMA device driver probe:", - dma_priv->func_id); - - return 0; -} - -/** - * DPDK callback to deregister PCI device. - * - * @param[in] dev - * Pointer to Ethernet device structure. - * - * @return - * 0 on success, negative errno value on failure. - */ -static int eth_qdma_vf_dev_uninit(struct rte_eth_dev *dev) -{ - struct qdma_pci_dev *qdma_dev = dev->data->dev_private; - - /* only uninitialize in the primary process */ - if (rte_eal_process_type() != RTE_PROC_PRIMARY) - return -EPERM; - - if (qdma_dev->dev_configured) - qdma_vf_dev_close(dev); - - qdma_ethdev_offline(dev); - - if (qdma_dev->reset_state != RESET_STATE_RECV_PF_RESET_REQ) - qdma_mbox_uninit(dev); - - dev->dev_ops = NULL; - dev->rx_pkt_burst = NULL; - dev->tx_pkt_burst = NULL; - dev->data->nb_rx_queues = 0; - dev->data->nb_tx_queues = 0; - - if (dev->data->mac_addrs != NULL) { - rte_free(dev->data->mac_addrs); - dev->data->mac_addrs = NULL; - } - - if (qdma_dev->q_info != NULL) { - rte_free(qdma_dev->q_info); - qdma_dev->q_info = NULL; - } - - return 0; -} - -static int eth_qdma_vf_pci_probe(struct rte_pci_driver *pci_drv __rte_unused, - struct rte_pci_device *pci_dev) -{ - return rte_eth_dev_pci_generic_probe(pci_dev, - sizeof(struct qdma_pci_dev), - eth_qdma_vf_dev_init); -} - -/* Detach a ethdev interface */ -static int eth_qdma_vf_pci_remove(struct rte_pci_device *pci_dev) -{ - return rte_eth_dev_pci_generic_remove(pci_dev, eth_qdma_vf_dev_uninit); -} - -static struct rte_pci_driver rte_qdma_vf_pmd = { - .id_table = qdma_vf_pci_id_tbl, - .drv_flags = RTE_PCI_DRV_NEED_MAPPING, - .probe = eth_qdma_vf_pci_probe, - .remove = eth_qdma_vf_pci_remove, -}; - -bool -is_vf_device_supported(struct rte_eth_dev *dev) -{ - if (strcmp(dev->device->driver->name, rte_qdma_vf_pmd.driver.name)) - return false; - - return true; -} - -RTE_PMD_REGISTER_PCI(net_qdma_vf, rte_qdma_vf_pmd); -RTE_PMD_REGISTER_PCI_TABLE(net_qdma_vf, qdma_vf_pci_id_tbl); diff --git a/QDMA/DPDK/drivers/net/qdma/qdma_xdebug.c b/QDMA/DPDK/drivers/net/qdma/qdma_xdebug.c deleted file mode 100755 index 4cade046e..000000000 --- a/QDMA/DPDK/drivers/net/qdma/qdma_xdebug.c +++ /dev/null @@ -1,1468 +0,0 @@ -/*- - * BSD LICENSE - * - * Copyright (c) 2017-2022 Xilinx, Inc. All rights reserved. - * Copyright (c) 2022-2023, Advanced Micro Devices, Inc. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * * Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include "qdma.h" -#include "rte_pmd_qdma.h" -#include "qdma_access_common.h" -#include "qdma_reg_dump.h" -#include "qdma_mbox_protocol.h" -#include "qdma_mbox.h" - -#define xdebug_info(args...) rte_log(RTE_LOG_INFO, RTE_LOGTYPE_USER1,\ - ## args) -#define xdebug_error(args...) rte_log(RTE_LOG_ERR, RTE_LOGTYPE_USER1,\ - ## args) - -struct xdebug_desc_param { - uint16_t queue; - int start; - int end; - enum rte_pmd_qdma_xdebug_desc_type type; -}; - -const char *qdma_desc_eng_mode_info[QDMA_DESC_ENG_MODE_MAX] = { - "Internal and Bypass mode", - "Bypass only mode", - "Internal only mode" -}; - -static void print_header(const char *str) -{ - xdebug_info("\n\n%s\n\n", str); -} - -static int qdma_h2c_struct_dump(uint8_t port_id, uint16_t queue) -{ - struct rte_eth_dev *dev; - struct qdma_tx_queue *tx_q; - - if (port_id >= rte_eth_dev_count_avail()) { - xdebug_error("Wrong port id %d\n", port_id); - return -EINVAL; - } - - dev = &rte_eth_devices[port_id]; - tx_q = (struct qdma_tx_queue *)dev->data->tx_queues[queue]; - - if (queue >= dev->data->nb_tx_queues) { - xdebug_info("TX queue_id=%d not configured\n", queue); - return -EINVAL; - } - - if (tx_q) { - print_header("***********TX Queue struct************"); - xdebug_info("\t\t wb_pidx :%x\n", - tx_q->wb_status->pidx); - xdebug_info("\t\t wb_cidx :%x\n", - tx_q->wb_status->cidx); - xdebug_info("\t\t h2c_pidx :%x\n", - tx_q->q_pidx_info.pidx); - xdebug_info("\t\t tx_fl_tail :%x\n", - tx_q->tx_fl_tail); - xdebug_info("\t\t tx_desc_pend :%x\n", - tx_q->tx_desc_pend); - xdebug_info("\t\t nb_tx_desc :%x\n", - tx_q->nb_tx_desc); - xdebug_info("\t\t st_mode :%x\n", - tx_q->st_mode); - xdebug_info("\t\t tx_deferred_start :%x\n", - tx_q->tx_deferred_start); - xdebug_info("\t\t en_bypass :%x\n", - tx_q->en_bypass); - xdebug_info("\t\t bypass_desc_sz :%x\n", - tx_q->bypass_desc_sz); - xdebug_info("\t\t func_id :%x\n", - tx_q->func_id); - xdebug_info("\t\t port_id :%x\n", - tx_q->port_id); - xdebug_info("\t\t ringszidx :%x\n", - tx_q->ringszidx); - xdebug_info("\t\t ep_addr :0x%" PRIx64 "\n", - tx_q->ep_addr); - } - - return 0; -} - -static int qdma_c2h_struct_dump(uint8_t port_id, uint16_t queue) -{ - struct rte_eth_dev *dev; - struct qdma_pci_dev *qdma_dev; - struct qdma_rx_queue *rx_q; - enum qdma_ip_type ip_type; - - if (port_id >= rte_eth_dev_count_avail()) { - xdebug_error("Wrong port id %d\n", port_id); - return -EINVAL; - } - - dev = &rte_eth_devices[port_id]; - qdma_dev = dev->data->dev_private; - ip_type = (enum qdma_ip_type)qdma_dev->ip_type; - rx_q = (struct qdma_rx_queue *)dev->data->rx_queues[queue]; - - if (queue >= dev->data->nb_rx_queues) { - xdebug_info("RX queue_id=%d not configured\n", queue); - return -EINVAL; - } - - if (rx_q) { - print_header(" ***********RX Queue struct********** "); - xdebug_info("\t\t wb_pidx :%x\n", - rx_q->wb_status->pidx); - xdebug_info("\t\t wb_cidx :%x\n", - rx_q->wb_status->cidx); - xdebug_info("\t\t rx_tail (ST) :%x\n", - rx_q->rx_tail); - xdebug_info("\t\t c2h_pidx :%x\n", - rx_q->q_pidx_info.pidx); - xdebug_info("\t\t rx_cmpt_cidx :%x\n", - rx_q->cmpt_cidx_info.wrb_cidx); - xdebug_info("\t\t cmpt_desc_len :%x\n", - rx_q->cmpt_desc_len); - xdebug_info("\t\t rx_buff_size :%x\n", - rx_q->rx_buff_size); - xdebug_info("\t\t nb_rx_desc :%x\n", - rx_q->nb_rx_desc); - xdebug_info("\t\t nb_rx_cmpt_desc :%x\n", - rx_q->nb_rx_cmpt_desc); - xdebug_info("\t\t ep_addr :0x%" PRIx64 "\n", - rx_q->ep_addr); - xdebug_info("\t\t st_mode :%x\n", - rx_q->st_mode); - xdebug_info("\t\t rx_deferred_start :%x\n", - rx_q->rx_deferred_start); - xdebug_info("\t\t en_prefetch :%x\n", - rx_q->en_prefetch); - xdebug_info("\t\t en_bypass :%x\n", - rx_q->en_bypass); - xdebug_info("\t\t dump_immediate_data :%x\n", - rx_q->dump_immediate_data); - xdebug_info("\t\t en_bypass_prefetch :%x\n", - rx_q->en_bypass_prefetch); - - if (!(ip_type == QDMA_VERSAL_HARD_IP)) - xdebug_info("\t\t dis_overflow_check :%x\n", - rx_q->dis_overflow_check); - - xdebug_info("\t\t bypass_desc_sz :%x\n", - rx_q->bypass_desc_sz); - xdebug_info("\t\t ringszidx :%x\n", - rx_q->ringszidx); - xdebug_info("\t\t cmpt_ringszidx :%x\n", - rx_q->cmpt_ringszidx); - xdebug_info("\t\t buffszidx :%x\n", - rx_q->buffszidx); - xdebug_info("\t\t threshidx :%x\n", - rx_q->threshidx); - xdebug_info("\t\t timeridx :%x\n", - rx_q->timeridx); - xdebug_info("\t\t triggermode :%x\n", - rx_q->triggermode); - } - - return 0; -} - -static int qdma_config_read_reg_list(struct rte_eth_dev *dev, - uint16_t group_num, - uint16_t *num_regs, struct qdma_reg_data *reg_list) -{ - struct qdma_pci_dev *qdma_dev = dev->data->dev_private; - struct qdma_mbox_msg *m = qdma_mbox_msg_alloc(); - int rv; - - if (!m) - return -ENOMEM; - - qdma_mbox_compose_reg_read(qdma_dev->func_id, group_num, m->raw_data); - - rv = qdma_mbox_msg_send(dev, m, MBOX_OP_RSP_TIMEOUT); - if (rv < 0) { - if (rv != -ENODEV) - xdebug_error("reg read mbox failed with error = %d\n", - rv); - goto err_out; - } - - rv = qdma_mbox_vf_reg_list_get(m->raw_data, num_regs, reg_list); - if (rv < 0) { - xdebug_error("qdma_mbox_vf_reg_list_get failed with error = %d\n", - rv); - goto err_out; - } - -err_out: - qdma_mbox_msg_free(m); - return rv; -} - -static int qdma_config_reg_dump(uint8_t port_id) -{ - struct rte_eth_dev *dev; - struct qdma_pci_dev *qdma_dev; - enum qdma_ip_type ip_type; - enum qdma_device_type device_type; - char *buf = NULL; - int buflen; - int ret; - struct qdma_reg_data *reg_list; - uint16_t num_regs = 0, group_num = 0; - int len = 0, rcv_len = 0, reg_len = 0; - - if (port_id >= rte_eth_dev_count_avail()) { - xdebug_error("Wrong port id %d\n", port_id); - return -EINVAL; - } - - dev = &rte_eth_devices[port_id]; - qdma_dev = dev->data->dev_private; - ip_type = (enum qdma_ip_type)qdma_dev->ip_type; - device_type = (enum qdma_device_type)qdma_dev->device_type; - - if (qdma_dev->is_vf) { - reg_len = (QDMA_MAX_REGISTER_DUMP * - sizeof(struct qdma_reg_data)); - reg_list = (struct qdma_reg_data *)rte_zmalloc("QDMA_DUMP_REG_VF", - reg_len, RTE_CACHE_LINE_SIZE); - if (!reg_list) { - xdebug_error("Unable to allocate memory for VF dump for reglist " - "size %d\n", reg_len); - return -ENOMEM; - } - - ret = qdma_acc_reg_dump_buf_len(dev, ip_type, - device_type, &buflen); - if (ret < 0) { - xdebug_error("Failed to get register dump buffer length\n"); - return ret; - } - /*allocate memory for register dump*/ - buf = (char *)rte_zmalloc("QDMA_DUMP_BUF_VF", buflen, - RTE_CACHE_LINE_SIZE); - if (!buf) { - xdebug_error("Unable to allocate memory for reg dump " - "size %d\n", buflen); - rte_free(reg_list); - return -ENOMEM; - } - xdebug_info("FPGA Config Registers for port_id: %d\n--------\n", - port_id); - xdebug_info(" Offset Name " - " Value(Hex) Value(Dec)\n"); - - for (group_num = 0; group_num < QDMA_REG_READ_GROUP_3; - group_num++) { - /** Reset the reg_list with 0's */ - memset(reg_list, 0, (QDMA_MAX_REGISTER_DUMP * - sizeof(struct qdma_reg_data))); - ret = qdma_config_read_reg_list(dev, - group_num, &num_regs, reg_list); - if (ret < 0) { - xdebug_error("Failed to read config registers " - "size %d, err = %d\n", buflen, ret); - rte_free(reg_list); - rte_free(buf); - return ret; - } - - rcv_len = qdma_acc_dump_config_reg_list(dev, - ip_type, device_type, num_regs, - reg_list, buf + len, buflen - len); - if (len < 0) { - xdebug_error("Failed to dump config regs " - "size %d, err = %d\n", buflen, ret); - rte_free(reg_list); - rte_free(buf); - return ret; - } - len += rcv_len; - } - if (ret < 0) { - xdebug_error("Insufficient space to dump Config Bar register values\n"); - rte_free(reg_list); - rte_free(buf); - return qdma_get_error_code(ret); - } - xdebug_info("%s\n", buf); - rte_free(reg_list); - rte_free(buf); - } else { - ret = qdma_acc_reg_dump_buf_len(dev, - ip_type, device_type, &buflen); - if (ret < 0) { - xdebug_error("Failed to get register dump buffer length\n"); - return ret; - } - - /*allocate memory for register dump*/ - buf = (char *)rte_zmalloc("QDMA_REG_DUMP", buflen, - RTE_CACHE_LINE_SIZE); - if (!buf) { - xdebug_error("Unable to allocate memory for reg dump " - "size %d\n", buflen); - return -ENOMEM; - } - xdebug_info("FPGA Config Registers for port_id: %d\n--------\n", - port_id); - xdebug_info(" Offset Name " - " Value(Hex) Value(Dec)\n"); - - ret = qdma_acc_dump_config_regs(dev, qdma_dev->is_vf, - ip_type, device_type, buf, buflen); - if (ret < 0) { - xdebug_error("Insufficient space to dump Config Bar register values\n"); - rte_free(buf); - return qdma_get_error_code(ret); - } - xdebug_info("%s\n", buf); - rte_free(buf); - } - - return 0; -} - -static int qdma_device_dump(uint8_t port_id) -{ - struct rte_eth_dev *dev; - struct qdma_pci_dev *qdma_dev; - - if (port_id >= rte_eth_dev_count_avail()) { - xdebug_error("Wrong port id %d\n", port_id); - return -EINVAL; - } - - dev = &rte_eth_devices[port_id]; - qdma_dev = dev->data->dev_private; - - xdebug_info("\n*** QDMA Device struct for port_id: %d ***\n\n", - port_id); - - xdebug_info("\t\t config BAR index :%x\n", - qdma_dev->config_bar_idx); - xdebug_info("\t\t AXI Master Lite BAR index :%x\n", - qdma_dev->user_bar_idx); - xdebug_info("\t\t AXI Bridge Master BAR index :%x\n", - qdma_dev->bypass_bar_idx); - xdebug_info("\t\t qsets enable :%x\n", - qdma_dev->qsets_en); - xdebug_info("\t\t queue base :%x\n", - qdma_dev->queue_base); - xdebug_info("\t\t pf :%x\n", - qdma_dev->func_id); - xdebug_info("\t\t cmpt desc length :%x\n", - qdma_dev->cmpt_desc_len); - xdebug_info("\t\t c2h bypass mode :%x\n", - qdma_dev->c2h_bypass_mode); - xdebug_info("\t\t h2c bypass mode :%x\n", - qdma_dev->h2c_bypass_mode); - xdebug_info("\t\t trigger mode :%x\n", - qdma_dev->trigger_mode); - xdebug_info("\t\t timer count :%x\n", - qdma_dev->timer_count); - xdebug_info("\t\t is vf :%x\n", - qdma_dev->is_vf); - xdebug_info("\t\t is master :%x\n", - qdma_dev->is_master); - xdebug_info("\t\t enable desc prefetch :%x\n", - qdma_dev->en_desc_prefetch); - xdebug_info("\t\t ip type :%x\n", - qdma_dev->ip_type); - xdebug_info("\t\t vivado release :%x\n", - qdma_dev->vivado_rel); - xdebug_info("\t\t rtl version :%x\n", - qdma_dev->rtl_version); - xdebug_info("\t\t is queue conigured :%x\n", - qdma_dev->init_q_range); - - xdebug_info("\n\t ***** Device Capabilities *****\n"); - xdebug_info("\t\t number of PFs :%x\n", - qdma_dev->dev_cap.num_pfs); - xdebug_info("\t\t number of Queues :%x\n", - qdma_dev->dev_cap.num_qs); - xdebug_info("\t\t FLR present :%x\n", - qdma_dev->dev_cap.flr_present); - xdebug_info("\t\t ST mode enable :%x\n", - qdma_dev->dev_cap.st_en); - xdebug_info("\t\t MM mode enable :%x\n", - qdma_dev->dev_cap.mm_en); - xdebug_info("\t\t MM with compt enable :%x\n", - qdma_dev->dev_cap.mm_cmpt_en); - xdebug_info("\t\t Mailbox enable :%x\n", - qdma_dev->dev_cap.mailbox_en); - xdebug_info("\t\t Num of MM channels :%x\n", - qdma_dev->dev_cap.mm_channel_max); - xdebug_info("\t\t Descriptor engine mode :%s\n", - qdma_desc_eng_mode_info[qdma_dev->dev_cap.desc_eng_mode]); - xdebug_info("\t\t Debug mode enable :%x\n", - qdma_dev->dev_cap.debug_mode); - - return 0; -} - -static int qdma_tx_qstats_dump(struct qdma_tx_queue *txq) -{ - if (txq == NULL) { - xdebug_info("Caught NULL pointer for queue_id: %d\n", - txq->queue_id); - return -1; - } - - xdebug_info("\n***** QDMA Tx Qstats on port_id: %d for qid: %d *****\n", - txq->port_id, txq->queue_id); - xdebug_info("\t\t txq_pidx :%u\n", - txq->qstats.pidx); - xdebug_info("\t\t txq_wrb_cidx :%u\n", - txq->qstats.wrb_cidx); - xdebug_info("\t\t txq_tail :%u\n", - txq->qstats.txq_tail); - xdebug_info("\t\t in_use_desc :%u\n", - txq->qstats.in_use_desc); - xdebug_info("\t\t nb_pkts :%u\n", - txq->qstats.nb_pkts); - xdebug_info("\t\t ring_wrap_cnt :%u\n", - txq->qstats.ring_wrap_cnt); - xdebug_info("\t\t txq_full_cnt :%u\n", - txq->qstats.txq_full_cnt); - -#ifdef LATENCY_MEASUREMENT - xdebug_info("\n\t***** wrb cidx counts *****\n"); - xdebug_info("\t\t wrb_cidx_cnt_no_change :%u\n", - txq->qstats.wrb_cidx_cnt_no_change); - xdebug_info("\t\t wrb_cidx_cnt_lt_8 :%u\n", - txq->qstats.wrb_cidx_cnt_lt_8); - xdebug_info("\t\t wrb_cidx_cnt_8_to_32 :%u\n", - txq->qstats.wrb_cidx_cnt_8_to_32); - xdebug_info("\t\t wrb_cidx_cnt_32_to_64 :%u\n", - txq->qstats.wrb_cidx_cnt_32_to_64); - xdebug_info("\t\t wrb_cidx_cnt_gt_64 :%u\n", - txq->qstats.wrb_cidx_cnt_gt_64); -#endif - - return 0; -} - -static int qdma_tx_qstats_latency_dump(struct rte_eth_dev *dev, uint16_t queue) -{ - struct qdma_tx_queue *txq; - int ret; -#ifdef LATENCY_MEASUREMENT - double pkt_lat_val_ms = 0; - double txq_avg_lat_ms = 0; - const struct rte_memzone *memzone; - double (*lat_data)[LATENCY_CNT] = NULL; - uint64_t hz; - int i; -#endif - - if (dev == NULL) { - xdebug_error("Caught NULL pointer for dev\n"); - return -EINVAL; - } - - if (queue >= dev->data->nb_tx_queues) { - xdebug_info("TX queue_id=%d not configured\n", queue); - return -EINVAL; - } - - txq = (struct qdma_tx_queue *)dev->data->tx_queues[queue]; - if (txq == NULL) { - xdebug_info("Caught NULL pointer for queue_id: %d\n", queue); - return -1; - } - - if (txq->status != RTE_ETH_QUEUE_STATE_STARTED) { - xdebug_info("Queue_id %d is not yet started\n", txq->queue_id); - return -1; - } - - ret = qdma_tx_qstats_dump(txq); - if (ret < 0) { - xdebug_info("Failed to dump Tx qstats for queue_id: %d\n", - queue); - return -1; - } - -#ifdef LATENCY_MEASUREMENT - /* Find the memzone created by the primary application */ - memzone = rte_memzone_lookup("TXQ_LAT_BUFFER_ZONE"); - if (memzone == NULL) { - /* Handle memzone lookup failure */ - return -1; - } - - /* Get the virtual address of the shared rxq latency buffer memory */ - lat_data = memzone->addr; - - xdebug_info("\n\t**** TxQ SW PIDX to HW CIDX Latency for qid: %d ****\n", - queue); - hz = rte_get_timer_hz(); - for (i = 0; i < LATENCY_CNT; i++) { - pkt_lat_val_ms = - ((double)lat_data[queue][i]*1000000/hz); - txq_avg_lat_ms += pkt_lat_val_ms; - xdebug_info("\t\t h2c_sw_pidx_to_hw_cidx_latency[%d][%d] : %f ms\n", - queue, i, pkt_lat_val_ms); - } - - xdebug_info( - "\n\t Avg h2c_sw_pidx_to_hw_cidx_latency for qid:%d is %f ms\n", - queue, (txq_avg_lat_ms/LATENCY_CNT)); -#endif - - return 0; -} - -static int qdma_rx_qstats_dump(struct qdma_rx_queue *rxq) -{ - if (rxq == NULL) { - xdebug_info("Caught NULL pointer for queue_id: %d\n", - rxq->queue_id); - return -1; - } - - xdebug_info("\n***** QDMA Rx Qstats on port_id: %d for qid: %d *****\n", - rxq->port_id, rxq->queue_id); - - xdebug_info("\t\t rxq_pidx :%u\n", - rxq->qstats.pidx); - xdebug_info("\t\t rxq_wrb_pidx :%u\n", - rxq->qstats.wrb_pidx); - xdebug_info("\t\t rxq_wrb_cidx :%u\n", - rxq->qstats.wrb_cidx); - xdebug_info("\t\t rxq_cmpt_tail :%u\n", - rxq->qstats.rxq_cmpt_tail); - xdebug_info("\t\t pending_desc :%u\n", - rxq->qstats.pending_desc); - xdebug_info("\t\t ring_wrap_cnt :%u\n", - rxq->qstats.ring_wrap_cnt); - xdebug_info("\t\t mbuf_avail_cnt :%u\n", - rxq->qstats.mbuf_avail_cnt); - xdebug_info("\t\t mbuf_in_use_cnt :%u\n", - rxq->qstats.mbuf_in_use_cnt); - - return 0; -} - -static int qdma_rx_qstats_latency_dump(struct rte_eth_dev *dev, uint16_t queue) -{ - struct qdma_rx_queue *rxq; - int ret; -#ifdef LATENCY_MEASUREMENT - double pkt_lat_val_ms = 0; - double rxq_avg_lat_ms = 0; - const struct rte_memzone *memzone; - double (*lat_data)[LATENCY_CNT] = NULL; - uint64_t hz; - int i; -#endif - - if (dev == NULL) { - xdebug_error("Caught NULL pointer for dev\n"); - return -EINVAL; - } - - if (queue >= dev->data->nb_rx_queues) { - xdebug_info("RX queue_id=%d not configured\n", queue); - return -EINVAL; - } - - rxq = (struct qdma_rx_queue *)dev->data->rx_queues[queue]; - if (rxq == NULL) { - xdebug_info("Caught NULL pointer for queue_id: %d\n", queue); - return -1; - } - - if (rxq->status != RTE_ETH_QUEUE_STATE_STARTED) { - xdebug_info("Queue_id %d is not yet started\n", rxq->queue_id); - return -1; - } - - ret = qdma_rx_qstats_dump(rxq); - if (ret < 0) { - xdebug_info("Failed to dump Rx qstats for queue_id: %d\n", - queue); - return -1; - } - -#ifdef LATENCY_MEASUREMENT - /* Find the memzone created by the primary application */ - memzone = rte_memzone_lookup("RXQ_LAT_BUFFER_ZONE"); - if (memzone == NULL) { - /* Handle memzone lookup failure */ - return -1; - } - - /* Get the virtual address of the shared txq latency buffer memory */ - lat_data = memzone->addr; - - xdebug_info("\n\t*** RxQ SW PIDX to CMPT PIDX Latency for qid: %d ***\n", - queue); - hz = rte_get_timer_hz(); - for (i = 0; i < LATENCY_CNT; i++) { - pkt_lat_val_ms = - ((double)lat_data[queue][i]*1000000/hz); - rxq_avg_lat_ms += pkt_lat_val_ms; - xdebug_info("\t\t c2h_sw_pidx_to_cmpt_pidx_latency[%d][%d] : %f ms\n", - queue, i, pkt_lat_val_ms); - } - - xdebug_info( - "\n\t Avg c2h_sw_pidx_to_cmpt_pidx_latency for qid:%d is %f ms\n", - queue, (rxq_avg_lat_ms/LATENCY_CNT)); -#endif - - return 0; -} - -static int qdma_descq_context_read_vf(struct rte_eth_dev *dev, - unsigned int qid_hw, bool st_mode, - enum qdma_dev_q_type q_type, - struct qdma_descq_context *context) -{ - struct qdma_pci_dev *qdma_dev = dev->data->dev_private; - struct qdma_mbox_msg *m = qdma_mbox_msg_alloc(); - enum mbox_cmpt_ctxt_type cmpt_ctxt_type = QDMA_MBOX_CMPT_CTXT_NONE; - int rv; - - if (!m) - return -ENOMEM; - - if (!st_mode) { - if (q_type == QDMA_DEV_Q_TYPE_CMPT) - cmpt_ctxt_type = QDMA_MBOX_CMPT_CTXT_ONLY; - else - cmpt_ctxt_type = QDMA_MBOX_CMPT_CTXT_NONE; - } else { - if (q_type == QDMA_DEV_Q_TYPE_C2H) - cmpt_ctxt_type = QDMA_MBOX_CMPT_WITH_ST; - } - - qdma_mbox_compose_vf_qctxt_read(qdma_dev->func_id, - qid_hw, st_mode, q_type, cmpt_ctxt_type, m->raw_data); - - rv = qdma_mbox_msg_send(dev, m, MBOX_OP_RSP_TIMEOUT); - if (rv < 0) { - xdebug_error("%x, qid_hw 0x%x, mbox failed for vf q context %d.\n", - qdma_dev->func_id, qid_hw, rv); - goto free_msg; - } - - rv = qdma_mbox_vf_context_get(m->raw_data, context); - if (rv < 0) { - xdebug_error("%x, failed to get vf queue context info %d.\n", - qdma_dev->func_id, rv); - goto free_msg; - } - -free_msg: - qdma_mbox_msg_free(m); - return rv; -} - -static int qdma_c2h_context_dump(uint8_t port_id, uint16_t queue) -{ - struct rte_eth_dev *dev; - struct qdma_pci_dev *qdma_dev; - struct qdma_descq_context queue_context; - enum qdma_dev_q_type q_type; - enum qdma_ip_type ip_type; - enum qdma_device_type device_type; - uint16_t qid; - uint8_t st_mode; - char *buf = NULL; - uint32_t buflen = 0; - int ret = 0; - - if (port_id >= rte_eth_dev_count_avail()) { - xdebug_error("Wrong port id %d\n", port_id); - return -EINVAL; - } - - dev = &rte_eth_devices[port_id]; - qdma_dev = dev->data->dev_private; - qid = qdma_dev->queue_base + queue; - ip_type = (enum qdma_ip_type)qdma_dev->ip_type; - device_type = (enum qdma_device_type)qdma_dev->device_type; - st_mode = qdma_dev->q_info[qid].queue_mode; - q_type = QDMA_DEV_Q_TYPE_C2H; - - if (queue >= dev->data->nb_rx_queues) { - xdebug_info("RX queue_id=%d not configured\n", queue); - return -EINVAL; - } - - xdebug_info( - "\n ***** C2H Queue Contexts on port_id: %d for q_id: %d *****\n", - port_id, qid); - - ret = qdma_acc_context_buf_len(dev, ip_type, device_type, st_mode, - q_type, &buflen); - if (ret < 0) { - xdebug_error("Failed to get context buffer length,\n"); - return ret; - } - - /*allocate memory for csr dump*/ - buf = (char *)rte_zmalloc("QDMA_C2H_CONTEXT_DUMP", - buflen, RTE_CACHE_LINE_SIZE); - if (!buf) { - xdebug_error("Unable to allocate memory for c2h context dump " - "size %d\n", buflen); - return -ENOMEM; - } - - if (qdma_dev->is_vf) { - ret = qdma_descq_context_read_vf(dev, qid, - st_mode, q_type, &queue_context); - if (ret < 0) { - xdebug_error("Failed to read c2h queue context\n"); - rte_free(buf); - return qdma_get_error_code(ret); - } - - ret = qdma_acc_dump_queue_context(dev, ip_type, device_type, - st_mode, q_type, &queue_context, buf, buflen); - if (ret < 0) { - xdebug_error("Failed to dump c2h queue context\n"); - rte_free(buf); - return qdma_get_error_code(ret); - } - } else { - ret = qdma_acc_read_dump_queue_context(dev, - ip_type, device_type, qdma_dev->func_id, qid, - st_mode, q_type, buf, buflen); - if (ret < 0) { - xdebug_error("Failed to read and dump c2h queue context\n"); - rte_free(buf); - return qdma_get_error_code(ret); - } - } - - xdebug_info("%s\n", buf); - rte_free(buf); - - return 0; -} - -static int qdma_h2c_context_dump(uint8_t port_id, uint16_t queue) -{ - struct rte_eth_dev *dev; - struct qdma_pci_dev *qdma_dev; - struct qdma_descq_context queue_context; - enum qdma_dev_q_type q_type; - enum qdma_ip_type ip_type; - enum qdma_device_type device_type; - uint32_t buflen = 0; - uint16_t qid; - uint8_t st_mode; - char *buf = NULL; - int ret = 0; - - if (port_id >= rte_eth_dev_count_avail()) { - xdebug_error("Wrong port id %d\n", port_id); - return -EINVAL; - } - - dev = &rte_eth_devices[port_id]; - qdma_dev = dev->data->dev_private; - qid = qdma_dev->queue_base + queue; - ip_type = (enum qdma_ip_type)qdma_dev->ip_type; - device_type = (enum qdma_device_type)qdma_dev->device_type; - st_mode = qdma_dev->q_info[qid].queue_mode; - q_type = QDMA_DEV_Q_TYPE_H2C; - - if (queue >= dev->data->nb_tx_queues) { - xdebug_info("TX queue_id=%d not configured\n", queue); - return -EINVAL; - } - - xdebug_info( - "\n ***** H2C Queue Contexts on port_id: %d for q_id: %d *****\n", - port_id, qid); - - ret = qdma_acc_context_buf_len(dev, ip_type, device_type, st_mode, - q_type, &buflen); - if (ret < 0) { - xdebug_error("Failed to get context buffer length,\n"); - return ret; - } - - /*allocate memory for csr dump*/ - buf = (char *)rte_zmalloc("QDMA_H2C_CONTEXT_DUMP", - buflen, RTE_CACHE_LINE_SIZE); - if (!buf) { - xdebug_error("Unable to allocate memory for h2c context dump " - "size %d\n", buflen); - return -ENOMEM; - } - - if (qdma_dev->is_vf) { - ret = qdma_descq_context_read_vf(dev, qid, - st_mode, q_type, &queue_context); - if (ret < 0) { - xdebug_error("Failed to read h2c queue context\n"); - rte_free(buf); - return qdma_get_error_code(ret); - } - - ret = qdma_acc_dump_queue_context(dev, ip_type, - device_type, st_mode, q_type, - &queue_context, buf, buflen); - if (ret < 0) { - xdebug_error("Failed to dump h2c queue context\n"); - rte_free(buf); - return qdma_get_error_code(ret); - } - } else { - ret = qdma_acc_read_dump_queue_context(dev, - ip_type, device_type, qdma_dev->func_id, qid, - st_mode, q_type, buf, buflen); - if (ret < 0) { - xdebug_error("Failed to read and dump h2c queue context\n"); - rte_free(buf); - return qdma_get_error_code(ret); - } - } - - xdebug_info("%s\n", buf); - rte_free(buf); - - return 0; -} - -static int qdma_cmpt_context_dump(uint8_t port_id, uint16_t queue) -{ - struct rte_eth_dev *dev; - struct qdma_pci_dev *qdma_dev; - struct qdma_descq_context queue_context; - enum qdma_dev_q_type q_type; - enum qdma_ip_type ip_type; - enum qdma_device_type device_type; - uint32_t buflen; - uint16_t qid; - uint8_t st_mode; - char *buf = NULL; - int ret = 0; - - if (port_id >= rte_eth_dev_count_avail()) { - xdebug_error("Wrong port id %d\n", port_id); - return -EINVAL; - } - - dev = &rte_eth_devices[port_id]; - qdma_dev = dev->data->dev_private; - qid = qdma_dev->queue_base + queue; - ip_type = (enum qdma_ip_type)qdma_dev->ip_type; - device_type = (enum qdma_device_type)qdma_dev->device_type; - st_mode = qdma_dev->q_info[qid].queue_mode; - q_type = QDMA_DEV_Q_TYPE_CMPT; - - if (queue >= dev->data->nb_rx_queues) { - xdebug_info("RX queue_id=%d not configured\n", queue); - return -EINVAL; - } - - xdebug_info( - "\n ***** CMPT Queue Contexts on port_id: %d for q_id: %d *****\n", - port_id, qid); - - ret = qdma_acc_context_buf_len(dev, ip_type, device_type, - st_mode, q_type, &buflen); - if (ret < 0) { - xdebug_error("Failed to get context buffer length\n"); - return ret; - } - - /*allocate memory for csr dump*/ - buf = (char *)rte_zmalloc("QDMA_CMPT_CONTEXT_DUMP", - buflen, RTE_CACHE_LINE_SIZE); - if (!buf) { - xdebug_error("Unable to allocate memory for cmpt context dump " - "size %d\n", buflen); - return -ENOMEM; - } - - if (qdma_dev->is_vf) { - ret = qdma_descq_context_read_vf(dev, qid, - st_mode, q_type, &queue_context); - if (ret < 0) { - xdebug_error("Failed to read cmpt queue context\n"); - rte_free(buf); - return qdma_get_error_code(ret); - } - - ret = qdma_acc_dump_queue_context(dev, ip_type, - device_type, st_mode, q_type, - &queue_context, buf, buflen); - if (ret < 0) { - xdebug_error("Failed to dump cmpt queue context\n"); - rte_free(buf); - return qdma_get_error_code(ret); - } - } else { - ret = qdma_acc_read_dump_queue_context(dev, - ip_type, device_type, qdma_dev->func_id, qid, st_mode, - q_type, buf, buflen); - if (ret < 0) { - xdebug_error("Failed to read and dump cmpt queue context\n"); - rte_free(buf); - return qdma_get_error_code(ret); - } - } - - xdebug_info("%s\n", buf); - rte_free(buf); - - return 0; -} - -static int qdma_queue_desc_dump(uint8_t port_id, - struct xdebug_desc_param *param) -{ - struct rte_eth_dev *dev; - struct qdma_rx_queue *rxq; - struct qdma_tx_queue *txq; - uint8_t *rx_ring_bypass = NULL; - uint8_t *tx_ring_bypass = NULL; - char str[50]; - int x; - - if (port_id >= rte_eth_dev_count_avail()) { - xdebug_error("Wrong port id %d\n", port_id); - return -EINVAL; - } - - dev = &rte_eth_devices[port_id]; - - switch (param->type) { - case RTE_PMD_QDMA_XDEBUG_DESC_C2H: - - if (param->queue >= dev->data->nb_rx_queues) { - xdebug_info("queue_id=%d not configured", - param->queue); - return -1; - } - - rxq = (struct qdma_rx_queue *) - dev->data->rx_queues[param->queue]; - - if (rxq == NULL) { - xdebug_info("Caught NULL pointer for queue_id: %d\n", - param->queue); - return -1; - } - - if (rxq->status != RTE_ETH_QUEUE_STATE_STARTED) { - xdebug_info("Queue_id %d is not yet started\n", - param->queue); - return -1; - } - - if (param->start < 0 || param->start > rxq->nb_rx_desc) - param->start = 0; - if (param->end <= param->start || - param->end > rxq->nb_rx_desc) - param->end = rxq->nb_rx_desc; - - if ((rxq->en_bypass) && (rxq->bypass_desc_sz != 0)) { - rx_ring_bypass = (uint8_t *)rxq->rx_ring; - - xdebug_info("\n===== C2H bypass descriptors=====\n"); - for (x = param->start; x < param->end; x++) { - uint8_t *rx_bypass = - &rx_ring_bypass[x]; - snprintf(str, sizeof(str), - "\nDescriptor ID %d\t", x); - rte_hexdump(stdout, str, - (const void *)rx_bypass, - rxq->bypass_desc_sz); - } - } else { - if (rxq->st_mode) { - struct qdma_ul_st_c2h_desc *rx_ring_st = - (struct qdma_ul_st_c2h_desc *)rxq->rx_ring; - - xdebug_info("\n===== C2H ring descriptors=====\n"); - for (x = param->start; x < param->end; x++) { - struct qdma_ul_st_c2h_desc *rx_st = - &rx_ring_st[x]; - snprintf(str, sizeof(str), - "\nDescriptor ID %d\t", x); - rte_hexdump(stdout, str, - (const void *)rx_st, - sizeof(struct qdma_ul_st_c2h_desc)); - } - } else { - struct qdma_ul_mm_desc *rx_ring_mm = - (struct qdma_ul_mm_desc *)rxq->rx_ring; - xdebug_info("\n====== C2H ring descriptors======\n"); - for (x = param->start; x < param->end; x++) { - snprintf(str, sizeof(str), - "\nDescriptor ID %d\t", x); - rte_hexdump(stdout, str, - (const void *)&rx_ring_mm[x], - sizeof(struct qdma_ul_mm_desc)); - } - } - } - break; - case RTE_PMD_QDMA_XDEBUG_DESC_CMPT: - - if (param->queue >= dev->data->nb_rx_queues) { - xdebug_info("queue_id=%d not configured", - param->queue); - return -1; - } - - rxq = (struct qdma_rx_queue *) - dev->data->rx_queues[param->queue]; - - if (rxq) { - if (rxq->status != RTE_ETH_QUEUE_STATE_STARTED) { - xdebug_info("Queue_id %d is not yet started\n", - param->queue); - return -1; - } - - if (param->start < 0 || - param->start > rxq->nb_rx_cmpt_desc) - param->start = 0; - if (param->end <= param->start || - param->end > rxq->nb_rx_cmpt_desc) - param->end = rxq->nb_rx_cmpt_desc; - - if (!rxq->st_mode) { - xdebug_info("Queue_id %d is not initialized " - "in Stream mode\n", param->queue); - return -1; - } - - xdebug_info("\n===== CMPT ring descriptors=====\n"); - for (x = param->start; x < param->end; x++) { - uint32_t *cmpt_ring = (uint32_t *) - ((uint64_t)(rxq->cmpt_ring) + - ((uint64_t)x * rxq->cmpt_desc_len)); - snprintf(str, sizeof(str), - "\nDescriptor ID %d\t", x); - rte_hexdump(stdout, str, - (const void *)cmpt_ring, - rxq->cmpt_desc_len); - } - } - break; - case RTE_PMD_QDMA_XDEBUG_DESC_H2C: - - if (param->queue >= dev->data->nb_tx_queues) { - xdebug_info("queue_id=%d not configured", - param->queue); - return -1; - } - - txq = (struct qdma_tx_queue *) - dev->data->tx_queues[param->queue]; - - if (txq == NULL) { - xdebug_info("Caught NULL pointer for queue_id: %d\n", - param->queue); - return -1; - } - - if (txq->status != RTE_ETH_QUEUE_STATE_STARTED) { - xdebug_info("Queue_id %d is not yet started\n", - param->queue); - return -1; - } - - if (param->start < 0 || param->start > txq->nb_tx_desc) - param->start = 0; - if (param->end <= param->start || - param->end > txq->nb_tx_desc) - param->end = txq->nb_tx_desc; - - if ((txq->en_bypass) && (txq->bypass_desc_sz != 0)) { - tx_ring_bypass = (uint8_t *)txq->tx_ring; - - xdebug_info("\n====== H2C bypass descriptors=====\n"); - for (x = param->start; x < param->end; x++) { - uint8_t *tx_bypass = - &tx_ring_bypass[x]; - snprintf(str, sizeof(str), - "\nDescriptor ID %d\t", x); - rte_hexdump(stdout, str, - (const void *)tx_bypass, - txq->bypass_desc_sz); - } - } else { - if (txq->st_mode) { - struct qdma_ul_st_h2c_desc *qdma_h2c_ring = - (struct qdma_ul_st_h2c_desc *)txq->tx_ring; - xdebug_info("\n====== H2C ring descriptors=====\n"); - for (x = param->start; x < param->end; x++) { - snprintf(str, sizeof(str), - "\nDescriptor ID %d\t", x); - rte_hexdump(stdout, str, - (const void *)&qdma_h2c_ring[x], - sizeof(struct qdma_ul_st_h2c_desc)); - } - } else { - struct qdma_ul_mm_desc *tx_ring_mm = - (struct qdma_ul_mm_desc *)txq->tx_ring; - xdebug_info("\n===== H2C ring descriptors=====\n"); - for (x = param->start; x < param->end; x++) { - snprintf(str, sizeof(str), - "\nDescriptor ID %d\t", x); - rte_hexdump(stdout, str, - (const void *)&tx_ring_mm[x], - sizeof(struct qdma_ul_mm_desc)); - } - } - } - break; - default: - xdebug_info("Invalid ring selected\n"); - break; - } - return 0; -} - -int rte_pmd_qdma_dbg_regdump(uint8_t port_id) -{ - int err; - - if (port_id >= rte_eth_dev_count_avail()) { - xdebug_error("Wrong port id %d\n", port_id); - return -EINVAL; - } - - err = qdma_config_reg_dump(port_id); - if (err) { - xdebug_error("Error dumping Global registers\n"); - return err; - } - return 0; -} - -int rte_pmd_qdma_dbg_reg_info_dump(uint8_t port_id, - uint32_t num_regs, uint32_t reg_addr) -{ - struct rte_eth_dev *dev; - struct qdma_pci_dev *qdma_dev; - enum qdma_ip_type ip_type; - enum qdma_device_type device_type; - char *buf = NULL; - int buflen = QDMA_MAX_BUFLEN; - int ret; - - if (port_id >= rte_eth_dev_count_avail()) { - xdebug_error("Wrong port id %d\n", port_id); - return -EINVAL; - } - - dev = &rte_eth_devices[port_id]; - qdma_dev = dev->data->dev_private; - ip_type = (enum qdma_ip_type)qdma_dev->ip_type; - device_type = (enum qdma_device_type)qdma_dev->device_type; - - /*allocate memory for register dump*/ - buf = (char *)rte_zmalloc("QDMA_DUMP_BUF_REG_INFO", buflen, - RTE_CACHE_LINE_SIZE); - if (!buf) { - xdebug_error("Unable to allocate memory for reg info dump " - "size %d\n", buflen); - return -ENOMEM; - } - - ret = qdma_acc_dump_reg_info(dev, ip_type, device_type, - reg_addr, num_regs, buf, buflen); - if (ret < 0) { - xdebug_error("Failed to dump reg field values\n"); - rte_free(buf); - return qdma_get_error_code(ret); - } - xdebug_info("%s\n", buf); - rte_free(buf); - - return 0; -} - -int rte_pmd_qdma_dbg_qdevice(uint8_t port_id) -{ - int err; - - if (port_id >= rte_eth_dev_count_avail()) { - xdebug_error("Wrong port id %d\n", port_id); - return -EINVAL; - } - - err = qdma_device_dump(port_id); - if (err) { - xdebug_error("Error dumping QDMA device\n"); - return err; - } - return 0; -} - -int rte_pmd_qdma_qstats(uint8_t port_id, uint16_t queue) -{ - struct rte_eth_dev *dev; - int ret; - - if (port_id >= rte_eth_dev_count_avail()) { - xdebug_error("Wrong port id %d\n", port_id); - return -EINVAL; - } - - dev = &rte_eth_devices[port_id]; - if (dev == NULL) { - xdebug_error("Caught NULL pointer for dev\n"); - return -EINVAL; - } - - ret = qdma_tx_qstats_latency_dump(dev, queue); - if (ret) { - xdebug_error("Error dumping QDMA Tx queue stats\n"); - return ret; - } - - ret = qdma_rx_qstats_latency_dump(dev, queue); - if (ret) { - xdebug_error("Error dumping QDMA Rx queue stats\n"); - return ret; - } - - return 0; -} - -int qdma_tx_qstats_clear(struct rte_eth_dev *dev, uint16_t queue) -{ - struct qdma_tx_queue *txq; - int ret; -#ifdef LATENCY_MEASUREMENT - int i; -#endif - - if (queue >= dev->data->nb_tx_queues) { - xdebug_info("TX queue_id=%d not configured\n", queue); - return -EINVAL; - } - - txq = (struct qdma_tx_queue *)dev->data->tx_queues[queue]; - if (txq == NULL) { - xdebug_info("Caught NULL pointer for queue_id: %d\n", queue); - return -EINVAL; - } - - memset(&txq->qstats, 0, sizeof(struct qdma_txq_stats)); - -#ifdef LATENCY_MEASUREMENT - for (i = 0; i < LATENCY_CNT; i++) - h2c_pidx_to_hw_cidx_lat[queue][i] = 0; -#endif - - xdebug_info("\nCleared Tx queue stats for qid: %d\n", - queue); - - ret = qdma_tx_qstats_dump(txq); - if (ret < 0) { - xdebug_info("Failed to dump Tx qstats for queue_id: %d\n", - queue); - return -1; - } - - return 0; -} - -int qdma_rx_qstats_clear(struct rte_eth_dev *dev, uint16_t queue) -{ - struct qdma_rx_queue *rxq; - int ret; -#ifdef LATENCY_MEASUREMENT - int i; -#endif - - if (queue >= dev->data->nb_rx_queues) { - xdebug_info("RX queue_id=%d not configured\n", queue); - return -EINVAL; - } - - rxq = (struct qdma_rx_queue *)dev->data->rx_queues[queue]; - if (rxq == NULL) { - xdebug_info("Caught NULL pointer for queue_id: %d\n", queue); - return -EINVAL; - } - - memset(&rxq->qstats, 0, sizeof(struct qdma_rxq_stats)); - -#ifdef LATENCY_MEASUREMENT - for (i = 0; i < LATENCY_CNT; i++) - c2h_pidx_to_cmpt_pidx_lat[queue][i] = 0; -#endif - - xdebug_info("\nCleared Rx queue stats for qid: %d\n", - queue); - - ret = qdma_rx_qstats_dump(rxq); - if (ret < 0) { - xdebug_info("Failed to dump Rx qstats for queue_id: %d\n", - queue); - return -1; - } - - return 0; -} - -int rte_pmd_qdma_qstats_clear(uint8_t port_id, uint16_t queue) -{ - struct rte_eth_dev *dev; - int ret; - - if (port_id >= rte_eth_dev_count_avail()) { - xdebug_error("Wrong port id %d\n", port_id); - return -EINVAL; - } - - dev = &rte_eth_devices[port_id]; - - ret = qdma_tx_qstats_clear(dev, queue); - if (ret) { - xdebug_error("Failed to clear QDMA Tx queue stats\n"); - return ret; - } - - ret = qdma_rx_qstats_clear(dev, queue); - if (ret) { - xdebug_error("Failed to clear QDMA Rx queue stats\n"); - return ret; - } - - return 0; -} - -int rte_pmd_qdma_dbg_qinfo(uint8_t port_id, uint16_t queue) -{ - struct rte_eth_dev *dev; - struct qdma_pci_dev *qdma_dev; - uint16_t qid; - uint8_t st_mode; - int err; - - if (port_id >= rte_eth_dev_count_avail()) { - xdebug_error("Wrong port id %d\n", port_id); - return -EINVAL; - } - - dev = &rte_eth_devices[port_id]; - qdma_dev = dev->data->dev_private; - qid = qdma_dev->queue_base + queue; - st_mode = qdma_dev->q_info[qid].queue_mode; - - err = qdma_h2c_context_dump(port_id, queue); - if (err) { - xdebug_error("Error dumping %d: %d\n", - queue, err); - return err; - } - - err = qdma_c2h_context_dump(port_id, queue); - if (err) { - xdebug_error("Error dumping %d: %d\n", - queue, err); - return err; - } - - if (!st_mode && qdma_dev->dev_cap.mm_cmpt_en) { - err = qdma_cmpt_context_dump(port_id, queue); - if (err) { - xdebug_error("Error dumping %d: %d\n", - queue, err); - return err; - } - } - - err = qdma_h2c_struct_dump(port_id, queue); - if (err) { - xdebug_error("Error dumping %d: %d\n", - queue, err); - return err; - } - - err = qdma_c2h_struct_dump(port_id, queue); - if (err) { - xdebug_error("Error dumping %d: %d\n", - queue, err); - return err; - } - - return 0; -} - -int rte_pmd_qdma_dbg_qdesc(uint8_t port_id, uint16_t queue, int start, - int end, enum rte_pmd_qdma_xdebug_desc_type type) -{ - struct xdebug_desc_param param; - int err; - - if (port_id >= rte_eth_dev_count_avail()) { - xdebug_error("Wrong port id %d\n", port_id); - return -EINVAL; - } - - param.queue = queue; - param.start = start; - param.end = end; - param.type = type; - - err = qdma_queue_desc_dump(port_id, ¶m); - if (err) { - xdebug_error("Error dumping %d: %d\n", - queue, err); - return err; - } - return 0; -} diff --git a/QDMA/DPDK/drivers/net/qdma/rte_pmd_qdma.c b/QDMA/DPDK/drivers/net/qdma/rte_pmd_qdma.c deleted file mode 100755 index d2b93ba1a..000000000 --- a/QDMA/DPDK/drivers/net/qdma/rte_pmd_qdma.c +++ /dev/null @@ -1,1821 +0,0 @@ -/*- - * BSD LICENSE - * - * Copyright (c) 2019-2022 Xilinx, Inc. All rights reserved. - * Copyright (c) 2022-2023, Advanced Micro Devices, Inc. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * * Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include "qdma.h" -#include "qdma_access_common.h" -#include "rte_pmd_qdma.h" -#include "qdma_devops.h" - - -static int validate_qdma_dev_info(int port_id, uint16_t qid) -{ - struct rte_eth_dev *dev; - struct qdma_pci_dev *qdma_dev; - - if (port_id < 0 || port_id >= rte_eth_dev_count_avail()) { - PMD_DRV_LOG(ERR, "Wrong port id %d\n", port_id); - return -ENOTSUP; - } - dev = &rte_eth_devices[port_id]; - qdma_dev = dev->data->dev_private; - if (!is_qdma_supported(dev)) { - PMD_DRV_LOG(ERR, "Device is not supported\n"); - return -ENOTSUP; - } - - if (qid >= qdma_dev->qsets_en) { - PMD_DRV_LOG(ERR, "Invalid Queue id passed, queue ID = %d\n", - qid); - return -EINVAL; - } - - if (!qdma_dev->dev_configured) { - PMD_DRV_LOG(ERR, - "Device for port id %d is not configured yet\n", - port_id); - return -EINVAL; - } - - return 0; -} - -static int8_t qdma_get_trigger_mode(enum rte_pmd_qdma_tigger_mode_t mode) -{ - int8_t ret; - switch (mode) { - case RTE_PMD_QDMA_TRIG_MODE_DISABLE: - ret = QDMA_CMPT_UPDATE_TRIG_MODE_DIS; - break; - case RTE_PMD_QDMA_TRIG_MODE_EVERY: - ret = QDMA_CMPT_UPDATE_TRIG_MODE_EVERY; - break; - case RTE_PMD_QDMA_TRIG_MODE_USER_COUNT: - ret = QDMA_CMPT_UPDATE_TRIG_MODE_USR_CNT; - break; - case RTE_PMD_QDMA_TRIG_MODE_USER: - ret = QDMA_CMPT_UPDATE_TRIG_MODE_USR; - break; - case RTE_PMD_QDMA_TRIG_MODE_USER_TIMER: - ret = QDMA_CMPT_UPDATE_TRIG_MODE_USR_TMR; - break; - case RTE_PMD_QDMA_TRIG_MODE_USER_TIMER_COUNT: - ret = QDMA_CMPT_UPDATE_TRIG_MODE_TMR_CNTR; - break; - default: - ret = QDMA_CMPT_UPDATE_TRIG_MODE_USR_TMR; - break; - } - return ret; -} - -/******************************************************************************/ -/** - * Function Name: rte_pmd_qdma_get_bar_details - * Description: Returns the BAR indices of the QDMA BARs - * - * @param port_id : Port ID - * @param config_bar_idx : Config BAR index - * @param user_bar_idx : AXI Master Lite BAR(user bar) index - * @param bypass_bar_idx : AXI Bridge Master BAR(bypass bar) index - * - * @return '0' on success and '< 0' on failure. - * - * @note None. - ******************************************************************************/ -int rte_pmd_qdma_get_bar_details(int port_id, int32_t *config_bar_idx, - int32_t *user_bar_idx, int32_t *bypass_bar_idx) -{ - struct rte_eth_dev *dev; - struct qdma_pci_dev *dma_priv; - - if (port_id < 0 || port_id >= rte_eth_dev_count_avail()) { - PMD_DRV_LOG(ERR, "Wrong port id %d\n", port_id); - return -ENOTSUP; - } - dev = &rte_eth_devices[port_id]; - dma_priv = dev->data->dev_private; - if (!is_qdma_supported(dev)) { - PMD_DRV_LOG(ERR, "Device is not supported\n"); - return -ENOTSUP; - } - - if (config_bar_idx != NULL) - *(config_bar_idx) = dma_priv->config_bar_idx; - - if (user_bar_idx != NULL) - *(user_bar_idx) = dma_priv->user_bar_idx; - - if (bypass_bar_idx != NULL) - *(bypass_bar_idx) = dma_priv->bypass_bar_idx; - - return 0; -} - -/******************************************************************************/ -/** - * Function Name: rte_pmd_qdma_get_queue_base - * Description: Returns queue base for given port - * - * @param port_id : Port ID. - * @param queue_base : queue base. - * - * @return '0' on success and '< 0' on failure. - * - * @note Application can call this API only after successful - * call to rte_eh_dev_configure() API. - ******************************************************************************/ -int rte_pmd_qdma_get_queue_base(int port_id, uint32_t *queue_base) -{ - struct rte_eth_dev *dev; - struct qdma_pci_dev *dma_priv; - - if (port_id < 0 || port_id >= rte_eth_dev_count_avail()) { - PMD_DRV_LOG(ERR, "Wrong port id %d\n", port_id); - return -ENOTSUP; - } - dev = &rte_eth_devices[port_id]; - dma_priv = dev->data->dev_private; - if (!is_qdma_supported(dev)) { - PMD_DRV_LOG(ERR, "Device is not supported\n"); - return -ENOTSUP; - } - - if (queue_base == NULL) { - PMD_DRV_LOG(ERR, "Caught NULL pointer for queue base\n"); - return -EINVAL; - } - - *(queue_base) = dma_priv->queue_base; - - return 0; -} - -/******************************************************************************/ -/** - * Function Name: rte_pmd_qdma_get_pci_func_type - * Description: Retrieves pci function type i.e. PF or VF - * - * @param port_id : Port ID. - * @param func_type : Indicates pci function type. - * - * @return '0' on success and '< 0' on failure. - * - * @note Returns the PCIe function type i.e. PF or VF of the given port. - ******************************************************************************/ -int rte_pmd_qdma_get_pci_func_type(int port_id, - enum rte_pmd_qdma_pci_func_type *func_type) -{ - struct rte_eth_dev *dev; - struct qdma_pci_dev *dma_priv; - - if (port_id < 0 || port_id >= rte_eth_dev_count_avail()) { - PMD_DRV_LOG(ERR, "Wrong port id %d\n", port_id); - return -ENOTSUP; - } - dev = &rte_eth_devices[port_id]; - dma_priv = dev->data->dev_private; - if (!is_qdma_supported(dev)) { - PMD_DRV_LOG(ERR, "Device is not supported\n"); - return -ENOTSUP; - } - - if (func_type == NULL) { - PMD_DRV_LOG(ERR, "Caught NULL pointer for function type\n"); - return -EINVAL; - } - - *((enum rte_pmd_qdma_pci_func_type *)func_type) = (dma_priv->is_vf) ? - RTE_PMD_QDMA_PCI_FUNC_VF : RTE_PMD_QDMA_PCI_FUNC_PF; - - return 0; -} - -/******************************************************************************/ -/** - * Function Name: rte_pmd_qdma_get_immediate_data_state - * Description: Returns immediate data state - * i.e. whether enabled or disabled, for the specified - * queue - * - * @param port_id : Port ID. - * @param qid : Queue ID. - * @param state : Pointer to the state specifying whether - * immediate data is enabled or not - * - * @return '0' on success and '< 0' on failure. - * - * @note Application can call this function after - * rte_eth_tx_queue_setup() or - * rte_eth_rx_queue_setup() is called. - * API is applicable for streaming queues only. - ******************************************************************************/ -int rte_pmd_qdma_get_immediate_data_state(int port_id, uint32_t qid, - int *state) -{ - struct rte_eth_dev *dev; - struct qdma_pci_dev *qdma_dev; - struct qdma_rx_queue *rxq; - int ret = 0; - - ret = validate_qdma_dev_info(port_id, qid); - if (ret != QDMA_SUCCESS) { - PMD_DRV_LOG(ERR, - "QDMA device validation failed for port id %d\n", - port_id); - return ret; - } - dev = &rte_eth_devices[port_id]; - qdma_dev = dev->data->dev_private; - if (qid >= dev->data->nb_rx_queues) { - PMD_DRV_LOG(ERR, "Invalid Q-id passed qid %d max en_qid %d\n", - qid, dev->data->nb_rx_queues); - return -EINVAL; - } - - if (state == NULL) { - PMD_DRV_LOG(ERR, "Invalid state for qid %d\n", qid); - return -EINVAL; - } - - if (qdma_dev->q_info[qid].queue_mode == - RTE_PMD_QDMA_STREAMING_MODE) { - rxq = (struct qdma_rx_queue *)dev->data->rx_queues[qid]; - if (rxq != NULL) { - *((int *)state) = rxq->dump_immediate_data; - } else { - PMD_DRV_LOG(ERR, "Qid %d is not setup\n", qid); - return -EINVAL; - } - - } else { - PMD_DRV_LOG(ERR, "Qid %d is not setup in Streaming mode\n", - qid); - return -EINVAL; - } - return ret; -} - -/******************************************************************************/ -/** - * Function Name: rte_pmd_qdma_set_queue_mode - * Description: Sets queue mode for the specified queue - * - * @param port_id : Port ID. - * @param qid : Queue ID. - * @param mode : Queue mode to be set - * - * @return '0' on success and '<0' on failure. - * - * @note Application can call this API after successful call to - * rte_eth_dev_configure() but before - * rte_eth_tx_queue_setup/rte_eth_rx_queue_setup() API. - * By default, all queues are setup in streaming mode. - ******************************************************************************/ -int rte_pmd_qdma_set_queue_mode(int port_id, uint32_t qid, - enum rte_pmd_qdma_queue_mode_t mode) -{ - struct rte_eth_dev *dev; - struct qdma_pci_dev *qdma_dev; - int ret = 0; - - ret = validate_qdma_dev_info(port_id, qid); - if (ret != QDMA_SUCCESS) { - PMD_DRV_LOG(ERR, - "QDMA device validation failed for port id %d\n", - port_id); - return ret; - } - dev = &rte_eth_devices[port_id]; - qdma_dev = dev->data->dev_private; - if (mode >= RTE_PMD_QDMA_QUEUE_MODE_MAX) { - PMD_DRV_LOG(ERR, "Invalid Queue mode passed,Mode = %d\n", mode); - return -EINVAL; - } - - qdma_dev->q_info[qid].queue_mode = mode; - - return ret; -} - -/******************************************************************************/ -/** - *Function Name: rte_pmd_qdma_set_immediate_data_state - *Description: Sets immediate data state - * i.e. enable or disable, for the specified queue. - * If enabled, the user defined data in the completion - * ring are dumped in to a queue specific file - * "q__immmediate_data.txt" in the local directory. - * - * @param port_id : Port ID. - * @param qid : Queue ID. - * @param value : Immediate data state to be set - * Set '0' to disable and '1' to enable - * - * @return '0' on success and '< 0' on failure. - * - * @note Application can call this API after successful - * call to rte_eth_dev_configure() API. Application can - * also call this API after successful call to - * rte_eth_rx_queue_setup() only if rx queue is not in - * start state. This API is applicable for - * streaming queues only. - ******************************************************************************/ -int rte_pmd_qdma_set_immediate_data_state(int port_id, uint32_t qid, - uint8_t state) -{ - struct rte_eth_dev *dev; - struct qdma_pci_dev *qdma_dev; - struct qdma_rx_queue *rxq; - int ret = 0; - - ret = validate_qdma_dev_info(port_id, qid); - if (ret != QDMA_SUCCESS) { - PMD_DRV_LOG(ERR, - "QDMA device validation failed for port id %d\n", - port_id); - return ret; - } - dev = &rte_eth_devices[port_id]; - qdma_dev = dev->data->dev_private; - if (qid >= dev->data->nb_rx_queues) { - PMD_DRV_LOG(ERR, "Invalid RX Queue id passed for %s," - "Queue ID = %d\n", __func__, qid); - return -EINVAL; - } - - if (state > 1) { - PMD_DRV_LOG(ERR, "Invalid value specified for immediate data " - "state %s, Queue ID = %d\n", __func__, qid); - return -EINVAL; - } - - if (qdma_dev->q_info[qid].queue_mode != - RTE_PMD_QDMA_STREAMING_MODE) { - PMD_DRV_LOG(ERR, "Qid %d is not setup in ST mode\n", qid); - return -EINVAL; - } - - rxq = (struct qdma_rx_queue *)dev->data->rx_queues[qid]; - if (rxq == NULL) { - /* Update the configuration in q_info structure - * if rx queue is not setup. - */ - qdma_dev->q_info[qid].immediate_data_state = state; - } else if (dev->data->rx_queue_state[qid] == - RTE_ETH_QUEUE_STATE_STOPPED) { - /* Update the config in both q_info and rxq structures, - * only if rx queue is setup but not yet started. - */ - qdma_dev->q_info[qid].immediate_data_state = state; - rxq->dump_immediate_data = state; - } else { - PMD_DRV_LOG(ERR, - "Cannot configure when Qid %d is in start state\n", - qid); - return -EINVAL; - } - - return ret; -} - -/******************************************************************************/ -/** - * Function Name: rte_pmd_qdma_set_cmpt_overflow_check - * Description: Enables or disables the overflow check - * (whether PIDX is overflowing the CIDX) performed by - * QDMA on the completion descriptor ring of specified - * queue. - * - * @param port_id : Port ID. - * @param qid : Queue ID. - * @param enable : '1' to enable and '0' to disable the overflow check - * - * @return '0' on success and '< 0' on failure. - * - * @note Application can call this API after successful call to - * rte_eth_dev_configure() API. Application can also call this - * API after successful call to rte_eth_rx_queue_setup()/ - * rte_pmd_qdma_dev_cmptq_setup() API only if - * rx/cmpt queue is not in start state. - ******************************************************************************/ -int rte_pmd_qdma_set_cmpt_overflow_check(int port_id, uint32_t qid, - uint8_t enable) -{ - struct rte_eth_dev *dev; - struct qdma_pci_dev *qdma_dev; - struct qdma_cmpt_queue *cmptq; - struct qdma_rx_queue *rxq; - int ret = 0; - - ret = validate_qdma_dev_info(port_id, qid); - if (ret != QDMA_SUCCESS) { - PMD_DRV_LOG(ERR, - "QDMA device validation failed for port id %d\n", - port_id); - return ret; - } - dev = &rte_eth_devices[port_id]; - qdma_dev = dev->data->dev_private; - if (enable > 1) - return -EINVAL; - - if (!qdma_dev->dev_cap.cmpt_ovf_chk_dis) { - PMD_DRV_LOG(ERR, "%s: Completion overflow check disable is " - "not supported in the current design\n", __func__); - return -EINVAL; - } - if (qdma_dev->q_info[qid].queue_mode == - RTE_PMD_QDMA_STREAMING_MODE) { - if (qid >= dev->data->nb_rx_queues) { - PMD_DRV_LOG(ERR, "Invalid Queue id passed for %s," - "Queue ID(ST-mode) = %d\n", __func__, - qid); - return -EINVAL; - } - - rxq = (struct qdma_rx_queue *)dev->data->rx_queues[qid]; - if (rxq == NULL) { - /* Update the configuration in q_info structure - * if rx queue is not setup. - */ - qdma_dev->q_info[qid].dis_cmpt_ovf_chk = - (enable == 1) ? 0 : 1; - } else if (dev->data->rx_queue_state[qid] == - RTE_ETH_QUEUE_STATE_STOPPED) { - /* Update the config in both q_info and rxq structures, - * only if rx queue is setup but not yet started. - */ - qdma_dev->q_info[qid].dis_cmpt_ovf_chk = - (enable == 1) ? 0 : 1; - rxq->dis_overflow_check = - qdma_dev->q_info[qid].dis_cmpt_ovf_chk; - } else { - PMD_DRV_LOG(ERR, - "Cannot configure when Qid %d is in start state\n", - qid); - return -EINVAL; - } - } else { - cmptq = (struct qdma_cmpt_queue *)qdma_dev->cmpt_queues[qid]; - if (cmptq == NULL) { - /* Update the configuration in q_info structure - * if cmpt queue is not setup. - */ - qdma_dev->q_info[qid].dis_cmpt_ovf_chk = - (enable == 1) ? 0 : 1; - } else if (cmptq->status == - RTE_ETH_QUEUE_STATE_STOPPED) { - /* Update the configuration in both q_info and cmptq - * structures if cmpt queue is already setup. - */ - qdma_dev->q_info[qid].dis_cmpt_ovf_chk = - (enable == 1) ? 0 : 1; - cmptq->dis_overflow_check = - qdma_dev->q_info[qid].dis_cmpt_ovf_chk; - } else { - PMD_DRV_LOG(ERR, - "Cannot configure when Qid %d is in start state\n", - qid); - return -EINVAL; - } - } - - return ret; -} - -/******************************************************************************/ -/** - * Function Name: rte_pmd_qdma_set_cmpt_descriptor_size - * Description: Configures the completion ring descriptor size - * - * @param port_id : Port ID. - * @param qid : Queue ID. - * @param size : Descriptor size to be configured - * - * @return '0' on success and '<0' on failure. - * - * @note Application can call this API after successful call to - * rte_eth_dev_configure() but before rte_eth_rx_queue_setup() API - * when queue is in streaming mode, and before - * rte_pmd_qdma_dev_cmptq_setup when queue is in memory mapped - * mode. - * By default, the completion desciptor size is set to 8 bytes. - ******************************************************************************/ -int rte_pmd_qdma_set_cmpt_descriptor_size(int port_id, uint32_t qid, - enum rte_pmd_qdma_cmpt_desc_len size) -{ - struct rte_eth_dev *dev; - struct qdma_pci_dev *qdma_dev; - int ret = 0; - - ret = validate_qdma_dev_info(port_id, qid); - if (ret != QDMA_SUCCESS) { - PMD_DRV_LOG(ERR, - "QDMA device validation failed for port id %d\n", - port_id); - return ret; - } - dev = &rte_eth_devices[port_id]; - qdma_dev = dev->data->dev_private; - if (qdma_dev->q_info[qid].queue_mode == - RTE_PMD_QDMA_STREAMING_MODE) { - if (qid >= dev->data->nb_rx_queues) { - PMD_DRV_LOG(ERR, "Invalid Queue id passed for %s," - "Queue ID(ST-mode) = %d\n", __func__, - qid); - return -EINVAL; - } - } - - if (size != RTE_PMD_QDMA_CMPT_DESC_LEN_8B && - size != RTE_PMD_QDMA_CMPT_DESC_LEN_16B && - size != RTE_PMD_QDMA_CMPT_DESC_LEN_32B && - (size != RTE_PMD_QDMA_CMPT_DESC_LEN_64B || - !qdma_dev->dev_cap.cmpt_desc_64b)) { - - PMD_DRV_LOG(ERR, "Invalid Size passed for %s, Size = %d\n", - __func__, size); - return -EINVAL; - } - - qdma_dev->q_info[qid].cmpt_desc_sz = size; - - return ret; -} - -/******************************************************************************/ -/** - * Function Name: rte_pmd_qdma_set_cmpt_trigger_mode - * Description: Configures the trigger mode for completion ring CIDX - * updates - * - * @param port_id : Port ID. - * @param qid : Queue ID. - * @param mode : Trigger mode to be configured - * - * @return '0' on success and '<0' on failure. - * - * @note Application can call this API after successful - * call to rte_eth_dev_configure() API. Application can - * also call this API after successful call to - * rte_eth_rx_queue_setup()/rte_pmd_qdma_dev_cmptq_setup() - * API only if rx/cmpt queue is not in start state. - * By default, trigger mode is set to Counter + Timer. - ******************************************************************************/ -int rte_pmd_qdma_set_cmpt_trigger_mode(int port_id, uint32_t qid, - enum rte_pmd_qdma_tigger_mode_t mode) -{ - struct rte_eth_dev *dev; - struct qdma_pci_dev *qdma_dev; - struct qdma_cmpt_queue *cmptq; - struct qdma_rx_queue *rxq; - int ret = 0; - - ret = validate_qdma_dev_info(port_id, qid); - if (ret != QDMA_SUCCESS) { - PMD_DRV_LOG(ERR, - "QDMA device validation failed for port id %d\n", - port_id); - return ret; - } - dev = &rte_eth_devices[port_id]; - qdma_dev = dev->data->dev_private; - if (mode >= RTE_PMD_QDMA_TRIG_MODE_MAX) { - PMD_DRV_LOG(ERR, "Invalid Trigger mode passed\n"); - return -EINVAL; - } - - if ((mode == RTE_PMD_QDMA_TRIG_MODE_USER_TIMER_COUNT) && - !qdma_dev->dev_cap.cmpt_trig_count_timer) { - PMD_DRV_LOG(ERR, "%s: Trigger mode %d is " - "not supported in the current design\n", - __func__, mode); - return -EINVAL; - } - - if (qdma_dev->q_info[qid].queue_mode == - RTE_PMD_QDMA_STREAMING_MODE) { - if (qid >= dev->data->nb_rx_queues) { - PMD_DRV_LOG(ERR, "Invalid Queue id passed for %s," - "Queue ID(ST-mode) = %d\n", __func__, - qid); - return -EINVAL; - } - - rxq = (struct qdma_rx_queue *)dev->data->rx_queues[qid]; - if (rxq == NULL) { - /* Update the configuration in q_info structure - * if rx queue is not setup. - */ - qdma_dev->q_info[qid].trigger_mode = - qdma_get_trigger_mode(mode); - } else if (dev->data->rx_queue_state[qid] == - RTE_ETH_QUEUE_STATE_STOPPED) { - /* Update the config in both q_info and rxq structures, - * only if rx queue is setup but not yet started. - */ - qdma_dev->q_info[qid].trigger_mode = - qdma_get_trigger_mode(mode); - rxq->triggermode = qdma_dev->q_info[qid].trigger_mode; - } else { - PMD_DRV_LOG(ERR, - "Cannot configure when Qid %d is in start state\n", - qid); - return -EINVAL; - } - } else if (qdma_dev->dev_cap.mm_cmpt_en) { - cmptq = (struct qdma_cmpt_queue *)qdma_dev->cmpt_queues[qid]; - if (cmptq == NULL) { - /* Update the configuration in q_info structure - * if cmpt queue is not setup. - */ - qdma_dev->q_info[qid].trigger_mode = - qdma_get_trigger_mode(mode); - } else if (cmptq->status == - RTE_ETH_QUEUE_STATE_STOPPED) { - /* Update the configuration in both q_info and cmptq - * structures if cmpt queue is already setup. - */ - qdma_dev->q_info[qid].trigger_mode = - qdma_get_trigger_mode(mode); - cmptq->triggermode = - qdma_dev->q_info[qid].trigger_mode; - } else { - PMD_DRV_LOG(ERR, - "Cannot configure when Qid %d is in start state\n", - qid); - return -EINVAL; - } - } else { - PMD_DRV_LOG(ERR, "Unable to set trigger mode for %s," - "Queue ID = %d, Queue Mode = %d\n", - __func__, - qid, qdma_dev->q_info[qid].queue_mode); - } - return ret; -} - -/******************************************************************************/ -/** - * Function Name: rte_pmd_qdma_set_cmpt_timer - * Description: Configures the timer interval in microseconds to trigger - * the completion ring CIDX updates - * - * @param port_id : Port ID. - * @param qid : Queue ID. - * @param value : Timer interval for completion trigger to be configured - * - * @return '0' on success and "<0" on failure. - * - * @note Application can call this API after successful - * call to rte_eth_dev_configure() API. Application can - * also call this API after successful call to - * rte_eth_rx_queue_setup()/rte_pmd_qdma_dev_cmptq_setup() API - * only if rx/cmpt queue is not in start state. - ******************************************************************************/ -int rte_pmd_qdma_set_cmpt_timer(int port_id, uint32_t qid, uint32_t value) -{ - struct rte_eth_dev *dev; - struct qdma_pci_dev *qdma_dev; - struct qdma_cmpt_queue *cmptq; - struct qdma_rx_queue *rxq; - int8_t timer_index; - int ret = 0; - - ret = validate_qdma_dev_info(port_id, qid); - if (ret != QDMA_SUCCESS) { - PMD_DRV_LOG(ERR, - "QDMA device validation failed for port id %d\n", - port_id); - return ret; - } - dev = &rte_eth_devices[port_id]; - qdma_dev = dev->data->dev_private; - timer_index = index_of_array(qdma_dev->g_c2h_timer_cnt, - QDMA_NUM_C2H_TIMERS, - value); - - if (timer_index < 0) { - PMD_DRV_LOG(ERR, "Expected timer %d not found\n", value); - return -ENOTSUP; - } - - if (qdma_dev->q_info[qid].queue_mode == - RTE_PMD_QDMA_STREAMING_MODE) { - if (qid >= dev->data->nb_rx_queues) { - PMD_DRV_LOG(ERR, "Invalid Queue id passed for %s," - "Queue ID(ST-mode) = %d\n", __func__, - qid); - return -EINVAL; - } - - rxq = (struct qdma_rx_queue *)dev->data->rx_queues[qid]; - if (rxq == NULL) { - /* Update the configuration in q_info structure - * if rx queue is not setup. - */ - qdma_dev->q_info[qid].timer_count = value; - } else if (dev->data->rx_queue_state[qid] == - RTE_ETH_QUEUE_STATE_STOPPED) { - /* Update the config in both q_info and rxq structures, - * only if rx queue is setup but not yet started. - */ - qdma_dev->q_info[qid].timer_count = value; - rxq->timeridx = timer_index; - } else { - PMD_DRV_LOG(ERR, - "Cannot configure when Qid %d is in start state\n", - qid); - return -EINVAL; - } - } else if (qdma_dev->dev_cap.mm_cmpt_en) { - cmptq = (struct qdma_cmpt_queue *)qdma_dev->cmpt_queues[qid]; - if (cmptq == NULL) { - /* Update the configuration in q_info structure - * if cmpt queue is not setup. - */ - qdma_dev->q_info[qid].timer_count = value; - } else if (cmptq->status == - RTE_ETH_QUEUE_STATE_STOPPED) { - /* Update the configuration in both q_info and cmptq - * structures if cmpt queue is already setup. - */ - qdma_dev->q_info[qid].timer_count = value; - cmptq->timeridx = timer_index; - } else { - PMD_DRV_LOG(ERR, - "Cannot configure when Qid %d is in start state\n", - qid); - return -EINVAL; - } - } else { - PMD_DRV_LOG(ERR, "Unable to set trigger mode for %s," - "Queue ID = %d, Queue Mode = %d\n", - __func__, - qid, qdma_dev->q_info[qid].queue_mode); - } - return ret; -} - -/******************************************************************************/ -/** - *Function Name: rte_pmd_qdma_set_c2h_descriptor_prefetch - *Description: Enables or disables prefetch of the descriptors by - * prefetch engine - * - * @param port_id : Port ID. - * @param qid : Queue ID. - * @param enable:'1' to enable and '0' to disable the descriptor prefetch - * - * @return '0' on success and '<0' on failure. - * - * @note Application can call this API after successful - * call to rte_eth_dev_configure() API. Application can - * also call this API after successful call to - * rte_eth_rx_queue_setup() API, only if rx queue - * is not in start state. - ******************************************************************************/ -int rte_pmd_qdma_set_c2h_descriptor_prefetch(int port_id, uint32_t qid, - uint8_t enable) -{ - struct rte_eth_dev *dev; - struct qdma_pci_dev *qdma_dev; - struct qdma_rx_queue *rxq; - int ret = 0; - - ret = validate_qdma_dev_info(port_id, qid); - if (ret != QDMA_SUCCESS) { - PMD_DRV_LOG(ERR, - "QDMA device validation failed for port id %d\n", - port_id); - return ret; - } - dev = &rte_eth_devices[port_id]; - qdma_dev = dev->data->dev_private; - if (qid >= dev->data->nb_rx_queues) { - PMD_DRV_LOG(ERR, "Invalid Queue id passed for %s, " - "Queue ID = %d\n", __func__, qid); - return -EINVAL; - } - - if (qdma_dev->q_info[qid].queue_mode == - RTE_PMD_QDMA_MEMORY_MAPPED_MODE) { - PMD_DRV_LOG(ERR, "%s() not supported for qid %d in MM mode", - __func__, qid); - return -ENOTSUP; - } - - rxq = (struct qdma_rx_queue *)dev->data->rx_queues[qid]; - - if (rxq == NULL) { - /* Update the configuration in q_info structure - * if rx queue is not setup. - */ - qdma_dev->q_info[qid].en_prefetch = (enable > 0) ? 1 : 0; - } else if (dev->data->rx_queue_state[qid] == - RTE_ETH_QUEUE_STATE_STOPPED) { - /* Update the config in both q_info and rxq structures, - * only if rx queue is setup but not yet started. - */ - qdma_dev->q_info[qid].en_prefetch = (enable > 0) ? 1 : 0; - rxq->en_prefetch = qdma_dev->q_info[qid].en_prefetch; - } else { - PMD_DRV_LOG(ERR, - "Cannot configure when Qid %d is in start state\n", - qid); - return -EINVAL; - } - - return ret; -} - -/*****************************************************************************/ -/** - * Function Name: rte_pmd_qdma_set_mm_endpoint_addr - * Description: Sets the PCIe endpoint memory offset at which to - * perform DMA operation for the specified queue operating - * in memory mapped mode. - * - * @param port_id : Port ID. - * @param qid : Queue ID. - * @param dir : direction i.e. TX or RX. - * @param addr : Destination address for TX , Source address for RX - * - * @return '0' on success and '<0' on failure. - * - * @note This API can be called before TX/RX burst API's - * (rte_eth_tx_burst() and rte_eth_rx_burst()) are called. - *****************************************************************************/ -int rte_pmd_qdma_set_mm_endpoint_addr(int port_id, uint32_t qid, - enum rte_pmd_qdma_dir_type dir, uint64_t addr) -{ - struct rte_eth_dev *dev; - struct qdma_pci_dev *qdma_dev; - struct qdma_rx_queue *rxq; - struct qdma_tx_queue *txq; - int ret = 0; - - ret = validate_qdma_dev_info(port_id, qid); - if (ret != QDMA_SUCCESS) { - PMD_DRV_LOG(ERR, - "QDMA device validation failed for port id %d\n", - port_id); - return ret; - } - dev = &rte_eth_devices[port_id]; - qdma_dev = dev->data->dev_private; - if (qdma_dev->q_info[qid].queue_mode != - RTE_PMD_QDMA_MEMORY_MAPPED_MODE) { - PMD_DRV_LOG(ERR, "Invalid Queue mode for %s, Queue ID = %d," - "mode = %d\n", __func__, qid, - qdma_dev->q_info[qid].queue_mode); - return -EINVAL; - } - - if (dir == RTE_PMD_QDMA_TX) { - txq = (struct qdma_tx_queue *)dev->data->tx_queues[qid]; - if (txq != NULL) - txq->ep_addr = addr; - else { - PMD_DRV_LOG(ERR, "Qid %d is not setup\n", qid); - return -EINVAL; - } - } else if (dir == RTE_PMD_QDMA_RX) { - rxq = (struct qdma_rx_queue *)dev->data->rx_queues[qid]; - if (rxq != NULL) - rxq->ep_addr = addr; - else { - PMD_DRV_LOG(ERR, "Qid %d is not setup\n", qid); - return -EINVAL; - } - } else { - PMD_DRV_LOG(ERR, "Invalid direction specified," - "Direction is %d\n", dir); - return -EINVAL; - } - return ret; -} - -/******************************************************************************/ -/** - * Function Name: rte_pmd_qdma_configure_tx_bypass - * Description: Sets the TX bypass mode and bypass descriptor size - * for the specified queue - * - * @param port_id : Port ID. - * @param qid : Queue ID. - * @param bypass_mode : Bypass mode to be set - * @param size : Bypass descriptor size to be set - * - * @return '0' on success and '<0' on failure. - * - * @note Application can call this API after successful call to - * rte_eth_dev_configure() but before tx_setup() API. - * By default, all queues are configured in internal mode - * i.e. bypass disabled. - * If size is specified zero, then the bypass descriptor size is - * set to the one used in internal mode. - ******************************************************************************/ -int rte_pmd_qdma_configure_tx_bypass(int port_id, uint32_t qid, - enum rte_pmd_qdma_tx_bypass_mode bypass_mode, - enum rte_pmd_qdma_bypass_desc_len size) -{ - struct rte_eth_dev *dev; - struct qdma_pci_dev *qdma_dev; - int ret = 0; - - ret = validate_qdma_dev_info(port_id, qid); - if (ret != QDMA_SUCCESS) { - PMD_DRV_LOG(ERR, - "QDMA device validation failed for port id %d\n", - port_id); - return ret; - } - dev = &rte_eth_devices[port_id]; - qdma_dev = dev->data->dev_private; - if (qid < dev->data->nb_tx_queues) { - if (bypass_mode >= RTE_PMD_QDMA_TX_BYPASS_MAX) { - PMD_DRV_LOG(ERR, "Invalid Tx Bypass mode : %d\n", - bypass_mode); - return -EINVAL; - } - if (qdma_dev->dev_cap.sw_desc_64b) { - /*64byte descriptor size supported - *in >2018.3 Example Design Only - */ - if ((size != 0) && (size != 64)) { - PMD_DRV_LOG(ERR, "%s: Descriptor size %d not supported." - "64B and internal " - "mode descriptor sizes (size = 0) " - "are only supported by the driver in > 2018.3 " - "example design\n", __func__, size); - return -EINVAL; - } - } else { - /*In 2018.2 design, internal mode descriptor - *sizes are only supported.Hence not allowing - *to configure bypass descriptor size. - *Size 0 indicates internal mode descriptor size. - */ - if (size != 0) { - PMD_DRV_LOG(ERR, "%s: Descriptor size %d not supported.Only " - "Internal mode descriptor sizes (size = 0)" - "are supported in the current design.\n", - __func__, size); - return -EINVAL; - } - } - qdma_dev->q_info[qid].tx_bypass_mode = bypass_mode; - - qdma_dev->q_info[qid].tx_bypass_desc_sz = size; - } else { - PMD_DRV_LOG(ERR, "Invalid queue ID specified, Queue ID = %d\n", - qid); - return -EINVAL; - } - - return ret; -} - -/******************************************************************************/ -/** - * Function Name: rte_pmd_qdma_configure_rx_bypass - * Description: Sets the RX bypass mode and bypass descriptor size for - * the specified queue - * - * @param port_id : Port ID. - * @param qid : Queue ID. - * @param bypass_mode : Bypass mode to be set - * @param size : Bypass descriptor size to be set - * - * @return '0' on success and '<0' on failure. - * - * @note Application can call this API after successful call to - * rte_eth_dev_configure() but before rte_eth_rx_queue_setup() API. - * By default, all queues are configured in internal mode - * i.e. bypass disabled. - * If size is specified zero, then the bypass descriptor size is - * set to the one used in internal mode. - ******************************************************************************/ -int rte_pmd_qdma_configure_rx_bypass(int port_id, uint32_t qid, - enum rte_pmd_qdma_rx_bypass_mode bypass_mode, - enum rte_pmd_qdma_bypass_desc_len size) -{ - struct rte_eth_dev *dev; - struct qdma_pci_dev *qdma_dev; - int ret = 0; - - ret = validate_qdma_dev_info(port_id, qid); - if (ret != QDMA_SUCCESS) { - PMD_DRV_LOG(ERR, - "QDMA device validation failed for port id %d\n", - port_id); - return ret; - } - dev = &rte_eth_devices[port_id]; - qdma_dev = dev->data->dev_private; - if (qid < dev->data->nb_rx_queues) { - if (bypass_mode >= RTE_PMD_QDMA_RX_BYPASS_MAX) { - PMD_DRV_LOG(ERR, "Invalid Rx Bypass mode : %d\n", - bypass_mode); - return -EINVAL; - } - - if (qdma_dev->dev_cap.sw_desc_64b) { - /*64byte descriptor size supported - *in >2018.3 Example Design Only - */ - if ((size != 0) && (size != 64)) { - PMD_DRV_LOG(ERR, "%s: Descriptor size %d not supported." - "64B and internal " - "mode descriptor sizes (size = 0) " - "are only supported by the driver in > 2018.3 " - "example design\n", __func__, size); - return -EINVAL; - } - } else { - /*In 2018.2 design, internal mode descriptor - *sizes are only supported.Hence not allowing - *to configure bypass descriptor size. - *Size 0 indicates internal mode descriptor size. - */ - if (size != 0) { - PMD_DRV_LOG(ERR, "%s: Descriptor size %d not supported.Only " - "Internal mode descriptor sizes (size = 0)" - "are supported in the current design.\n", - __func__, size); - return -EINVAL; - } - } - - qdma_dev->q_info[qid].rx_bypass_mode = bypass_mode; - - qdma_dev->q_info[qid].rx_bypass_desc_sz = size; - } else { - PMD_DRV_LOG(ERR, "Invalid queue ID specified, Queue ID = %d\n", - qid); - return -EINVAL; - } - - return ret; -} - -/******************************************************************************/ -/** - * Function Name: rte_pmd_qdma_get_device_capabilities - * Description: Retrive the device capabilities - * - * @param port_id : Port ID. - * @param dev_attr:Pointer to the device capabilities structure - * - * @return '0' on success and '< 0' on failure. - * - * @note None. - ******************************************************************************/ -int rte_pmd_qdma_get_device_capabilities(int port_id, - struct rte_pmd_qdma_dev_attributes *dev_attr) -{ - struct rte_eth_dev *dev; - struct qdma_pci_dev *qdma_dev; - - if (port_id < 0 || port_id >= rte_eth_dev_count_avail()) { - PMD_DRV_LOG(ERR, "Wrong port id %d\n", port_id); - return -ENOTSUP; - } - dev = &rte_eth_devices[port_id]; - qdma_dev = dev->data->dev_private; - if (!is_qdma_supported(dev)) { - PMD_DRV_LOG(ERR, "Device is not supported\n"); - return -ENOTSUP; - } - - if (dev_attr == NULL) { - PMD_DRV_LOG(ERR, "Caught NULL pointer for dev_attr\n"); - return -EINVAL; - } - - dev_attr->num_pfs = qdma_dev->dev_cap.num_pfs; - dev_attr->num_qs = qdma_dev->dev_cap.num_qs; - dev_attr->flr_present = qdma_dev->dev_cap.flr_present; - dev_attr->st_en = qdma_dev->dev_cap.st_en; - dev_attr->mm_en = qdma_dev->dev_cap.mm_en; - dev_attr->mm_cmpt_en = qdma_dev->dev_cap.mm_cmpt_en; - dev_attr->mailbox_en = qdma_dev->dev_cap.mailbox_en; - dev_attr->mm_channel_max = qdma_dev->dev_cap.mm_channel_max; - dev_attr->debug_mode = qdma_dev->dev_cap.debug_mode; - dev_attr->desc_eng_mode = qdma_dev->dev_cap.desc_eng_mode; - dev_attr->cmpt_ovf_chk_dis = qdma_dev->dev_cap.cmpt_ovf_chk_dis; - dev_attr->sw_desc_64b = qdma_dev->dev_cap.sw_desc_64b; - dev_attr->cmpt_desc_64b = qdma_dev->dev_cap.cmpt_desc_64b; - dev_attr->cmpt_trig_count_timer = - qdma_dev->dev_cap.cmpt_trig_count_timer; - - switch (qdma_dev->device_type) { - case QDMA_DEVICE_SOFT: - dev_attr->device_type = RTE_PMD_QDMA_DEVICE_SOFT; - break; - case QDMA_DEVICE_VERSAL_CPM4: - dev_attr->device_type = RTE_PMD_QDMA_DEVICE_VERSAL_CPM4; - break; - case QDMA_DEVICE_VERSAL_CPM5: - dev_attr->device_type = RTE_PMD_QDMA_DEVICE_VERSAL_CPM5; - break; - default: - PMD_DRV_LOG(ERR, "%s: Invalid device type " - "Id = %d\n", __func__, qdma_dev->device_type); - return -EINVAL; - } - - switch (qdma_dev->ip_type) { - case QDMA_VERSAL_HARD_IP: - dev_attr->ip_type = - RTE_PMD_QDMA_VERSAL_HARD_IP; - break; - case QDMA_VERSAL_SOFT_IP: - dev_attr->ip_type = - RTE_PMD_QDMA_VERSAL_SOFT_IP; - break; - case QDMA_SOFT_IP: - dev_attr->ip_type = - RTE_PMD_QDMA_SOFT_IP; - break; - case EQDMA_SOFT_IP: - dev_attr->ip_type = - RTE_PMD_EQDMA_SOFT_IP; - break; - default: - dev_attr->ip_type = RTE_PMD_QDMA_NONE_IP; - PMD_DRV_LOG(ERR, "%s: Invalid IP type " - "ip_type = %d\n", __func__, - qdma_dev->ip_type); - return -EINVAL; - } - - return 0; -} - -/******************************************************************************/ -/** - * Function Name: rte_pmd_qdma_dev_cmptq_setup - * Description: Allocate and set up a completion queue for - * memory mapped mode. - * - * @param port_id : Port ID. - * @param qid : Queue ID. - * @param nb_cmpt_desc: Completion queue ring size. - * @param socket_id : The socket_id argument is the socket identifier - * in case of NUMA. Its value can be SOCKET_ID_ANY - * if there is no NUMA constraint for the DMA memory - * allocated for the transmit descriptors of the ring. - * - * @return '0' on success and '< 0' on failure. - * - * @note Application can call this API after successful call to - * rte_eth_dev_configure() and rte_pmd_qdma_set_queue_mode() - * for queues in memory mapped mode. - ******************************************************************************/ - -int rte_pmd_qdma_dev_cmptq_setup(int port_id, uint32_t cmpt_queue_id, - uint16_t nb_cmpt_desc, - unsigned int socket_id) -{ - struct rte_eth_dev *dev; - uint32_t sz; - struct qdma_pci_dev *qdma_dev; - struct qdma_cmpt_queue *cmptq = NULL; - int err; - int ret = 0; - - ret = validate_qdma_dev_info(port_id, cmpt_queue_id); - if (ret != QDMA_SUCCESS) { - PMD_DRV_LOG(ERR, - "QDMA device validation failed for port id %d\n", - port_id); - return ret; - } - dev = &rte_eth_devices[port_id]; - qdma_dev = dev->data->dev_private; - if (nb_cmpt_desc == 0) { - PMD_DRV_LOG(ERR, "Invalid descriptor ring size %d\n", - nb_cmpt_desc); - return -EINVAL; - } - - if (!qdma_dev->dev_cap.mm_cmpt_en) { - PMD_DRV_LOG(ERR, "Completion Queue support for MM-mode " - "not enabled"); - return -EINVAL; - } - - if (!qdma_dev->is_vf) { - err = qdma_dev_increment_active_queue( - qdma_dev->dma_device_index, - qdma_dev->func_id, - QDMA_DEV_Q_TYPE_CMPT); - if (err != QDMA_SUCCESS) - return -EINVAL; - } else { - err = qdma_dev_notify_qadd(dev, cmpt_queue_id + - qdma_dev->queue_base, QDMA_DEV_Q_TYPE_CMPT); - - if (err < 0) { - PMD_DRV_LOG(ERR, "%s: Queue addition failed for CMPT Queue ID " - "%d\n", __func__, cmpt_queue_id); - return -EINVAL; - } - } - - if (!qdma_dev->init_q_range) { - if (qdma_dev->is_vf) { - err = qdma_vf_csr_read(dev); - if (err < 0) - goto cmptq_setup_err; - } else { - err = qdma_pf_csr_read(dev); - if (err < 0) - goto cmptq_setup_err; - } - qdma_dev->init_q_range = 1; - } - - /* Allocate cmpt queue data structure */ - cmptq = rte_zmalloc("QDMA_CmptQ", sizeof(struct qdma_cmpt_queue), - RTE_CACHE_LINE_SIZE); - - if (!cmptq) { - PMD_DRV_LOG(ERR, "Unable to allocate structure cmptq of " - "size %d\n", - (int)(sizeof(struct qdma_cmpt_queue))); - err = -ENOMEM; - goto cmptq_setup_err; - } - - cmptq->queue_id = cmpt_queue_id; - cmptq->port_id = dev->data->port_id; - cmptq->func_id = qdma_dev->func_id; - cmptq->dev = dev; - cmptq->st_mode = qdma_dev->q_info[cmpt_queue_id].queue_mode; - cmptq->triggermode = qdma_dev->q_info[cmpt_queue_id].trigger_mode; - cmptq->nb_cmpt_desc = nb_cmpt_desc + 1; - cmptq->cmpt_desc_len = qdma_dev->q_info[cmpt_queue_id].cmpt_desc_sz; - if ((cmptq->cmpt_desc_len == RTE_PMD_QDMA_CMPT_DESC_LEN_64B) && - !qdma_dev->dev_cap.cmpt_desc_64b) { - PMD_DRV_LOG(ERR, "%s: PF-%d(DEVFN) CMPT of 64B is not supported in the " - "current design\n", __func__, qdma_dev->func_id); - return -ENOTSUP; - } - /* Find completion ring size index */ - cmptq->ringszidx = index_of_array(qdma_dev->g_ring_sz, - QDMA_NUM_RING_SIZES, - cmptq->nb_cmpt_desc); - if (cmptq->ringszidx < 0) { - PMD_DRV_LOG(ERR, "Expected completion ring size %d not found\n", - cmptq->nb_cmpt_desc); - err = -EINVAL; - goto cmptq_setup_err; - } - - /* Find Threshold index */ - cmptq->threshidx = index_of_array(qdma_dev->g_c2h_cnt_th, - QDMA_NUM_C2H_COUNTERS, - DEFAULT_MM_CMPT_CNT_THRESHOLD); - if (cmptq->threshidx < 0) { - PMD_DRV_LOG(ERR, "Expected Threshold %d not found," - " using the value %d at index 0\n", - DEFAULT_MM_CMPT_CNT_THRESHOLD, - qdma_dev->g_c2h_cnt_th[0]); - cmptq->threshidx = 0; - } - - /* Find Timer index */ - cmptq->timeridx = index_of_array(qdma_dev->g_c2h_timer_cnt, - QDMA_NUM_C2H_TIMERS, - qdma_dev->q_info[cmpt_queue_id].timer_count); - if (cmptq->timeridx < 0) { - PMD_DRV_LOG(ERR, "Expected timer %d not found, " - "using the value %d at index 1\n", - qdma_dev->q_info[cmpt_queue_id].timer_count, - qdma_dev->g_c2h_timer_cnt[1]); - cmptq->timeridx = 1; - } - - cmptq->dis_overflow_check = - qdma_dev->q_info[cmpt_queue_id].dis_cmpt_ovf_chk; - - /* Allocate memory for completion(CMPT) descriptor ring */ - sz = (cmptq->nb_cmpt_desc) * cmptq->cmpt_desc_len; - cmptq->cmpt_mz = qdma_zone_reserve(dev, "RxHwCmptRn", - cmpt_queue_id, sz, socket_id); - if (!cmptq->cmpt_mz) { - PMD_DRV_LOG(ERR, "Unable to allocate cmptq->cmpt_mz " - "of size %d\n", sz); - err = -ENOMEM; - goto cmptq_setup_err; - } - cmptq->cmpt_ring = (struct qdma_ul_cmpt_ring *)cmptq->cmpt_mz->addr; - - /* Write-back status structure */ - cmptq->wb_status = (struct wb_status *)((uint64_t)cmptq->cmpt_ring + - (((uint64_t)cmptq->nb_cmpt_desc - 1) * - cmptq->cmpt_desc_len)); - memset(cmptq->cmpt_ring, 0, sz); - qdma_dev->cmpt_queues[cmpt_queue_id] = cmptq; - return ret; - -cmptq_setup_err: - if (!qdma_dev->is_vf) - qdma_dev_decrement_active_queue(qdma_dev->dma_device_index, - qdma_dev->func_id, QDMA_DEV_Q_TYPE_CMPT); - else - qdma_dev_notify_qdel(dev, cmpt_queue_id + - qdma_dev->queue_base, QDMA_DEV_Q_TYPE_CMPT); - - if (cmptq) { - if (cmptq->cmpt_mz) - rte_memzone_free(cmptq->cmpt_mz); - rte_free(cmptq); - } - return err; -} - -static int qdma_vf_cmptq_context_write(struct rte_eth_dev *dev, uint16_t qid) -{ - struct qdma_pci_dev *qdma_dev = dev->data->dev_private; - uint32_t qid_hw; - struct qdma_mbox_msg *m = qdma_mbox_msg_alloc(); - struct mbox_descq_conf descq_conf; - int rv; - struct qdma_cmpt_queue *cmptq; - uint8_t cmpt_desc_fmt; - - if (!m) - return -ENOMEM; - memset(&descq_conf, 0, sizeof(struct mbox_descq_conf)); - cmptq = (struct qdma_cmpt_queue *)qdma_dev->cmpt_queues[qid]; - qid_hw = qdma_dev->queue_base + cmptq->queue_id; - - switch (cmptq->cmpt_desc_len) { - case RTE_PMD_QDMA_CMPT_DESC_LEN_8B: - cmpt_desc_fmt = CMPT_CNTXT_DESC_SIZE_8B; - break; - case RTE_PMD_QDMA_CMPT_DESC_LEN_16B: - cmpt_desc_fmt = CMPT_CNTXT_DESC_SIZE_16B; - break; - case RTE_PMD_QDMA_CMPT_DESC_LEN_32B: - cmpt_desc_fmt = CMPT_CNTXT_DESC_SIZE_32B; - break; - case RTE_PMD_QDMA_CMPT_DESC_LEN_64B: - cmpt_desc_fmt = CMPT_CNTXT_DESC_SIZE_64B; - break; - default: - cmpt_desc_fmt = CMPT_CNTXT_DESC_SIZE_8B; - break; - } - - descq_conf.irq_arm = 0; - descq_conf.at = 0; - descq_conf.wbk_en = 1; - descq_conf.irq_en = 0; - descq_conf.desc_sz = SW_DESC_CNTXT_MEMORY_MAP_DMA; - descq_conf.forced_en = 1; - descq_conf.cmpt_ring_bs_addr = cmptq->cmpt_mz->iova; - descq_conf.cmpt_desc_sz = cmpt_desc_fmt; - descq_conf.triggermode = cmptq->triggermode; - - descq_conf.cmpt_color = CMPT_DEFAULT_COLOR_BIT; - descq_conf.cmpt_full_upd = 0; - descq_conf.cnt_thres = qdma_dev->g_c2h_cnt_th[cmptq->threshidx]; - descq_conf.timer_thres = qdma_dev->g_c2h_timer_cnt[cmptq->timeridx]; - descq_conf.cmpt_ringsz = qdma_dev->g_ring_sz[cmptq->ringszidx] - 1; - descq_conf.cmpt_int_en = 0; - descq_conf.cmpl_stat_en = 1; /* Enable stats for MM-CMPT */ - - if (qdma_dev->dev_cap.cmpt_ovf_chk_dis) - descq_conf.dis_overflow_check = cmptq->dis_overflow_check; - - descq_conf.func_id = cmptq->func_id; - - qdma_mbox_compose_vf_qctxt_write(cmptq->func_id, qid_hw, - cmptq->st_mode, 1, - QDMA_MBOX_CMPT_CTXT_ONLY, - &descq_conf, m->raw_data); - - rv = qdma_mbox_msg_send(dev, m, MBOX_OP_RSP_TIMEOUT); - if (rv < 0) { - PMD_DRV_LOG(ERR, "%x, qid_hw 0x%x, mbox failed %d.\n", - qdma_dev->func_id, qid_hw, rv); - goto err_out; - } - - rv = qdma_mbox_vf_response_status(m->raw_data); - - cmptq->cmpt_cidx_info.counter_idx = cmptq->threshidx; - cmptq->cmpt_cidx_info.timer_idx = cmptq->timeridx; - cmptq->cmpt_cidx_info.trig_mode = cmptq->triggermode; - cmptq->cmpt_cidx_info.wrb_en = 1; - cmptq->cmpt_cidx_info.wrb_cidx = 0; - qdma_dev->hw_access->qdma_queue_cmpt_cidx_update(dev, qdma_dev->is_vf, - qid, &cmptq->cmpt_cidx_info); - cmptq->status = RTE_ETH_QUEUE_STATE_STARTED; -err_out: - qdma_mbox_msg_free(m); - return rv; -} - -static int qdma_pf_cmptq_context_write(struct rte_eth_dev *dev, uint32_t qid) -{ - struct qdma_pci_dev *qdma_dev = dev->data->dev_private; - struct qdma_cmpt_queue *cmptq; - uint32_t queue_base = qdma_dev->queue_base; - uint8_t cmpt_desc_fmt; - int err = 0; - struct qdma_descq_cmpt_ctxt q_cmpt_ctxt; - - cmptq = (struct qdma_cmpt_queue *)qdma_dev->cmpt_queues[qid]; - memset(&q_cmpt_ctxt, 0, sizeof(struct qdma_descq_cmpt_ctxt)); - /* Clear Completion Context */ - qdma_dev->hw_access->qdma_cmpt_ctx_conf(dev, qid, - &q_cmpt_ctxt, QDMA_HW_ACCESS_CLEAR); - - switch (cmptq->cmpt_desc_len) { - case RTE_PMD_QDMA_CMPT_DESC_LEN_8B: - cmpt_desc_fmt = CMPT_CNTXT_DESC_SIZE_8B; - break; - case RTE_PMD_QDMA_CMPT_DESC_LEN_16B: - cmpt_desc_fmt = CMPT_CNTXT_DESC_SIZE_16B; - break; - case RTE_PMD_QDMA_CMPT_DESC_LEN_32B: - cmpt_desc_fmt = CMPT_CNTXT_DESC_SIZE_32B; - break; - case RTE_PMD_QDMA_CMPT_DESC_LEN_64B: - cmpt_desc_fmt = CMPT_CNTXT_DESC_SIZE_64B; - break; - default: - cmpt_desc_fmt = CMPT_CNTXT_DESC_SIZE_8B; - break; - } - - q_cmpt_ctxt.en_stat_desc = 1; - q_cmpt_ctxt.trig_mode = cmptq->triggermode; - q_cmpt_ctxt.fnc_id = cmptq->func_id; - q_cmpt_ctxt.counter_idx = cmptq->threshidx; - q_cmpt_ctxt.timer_idx = cmptq->timeridx; - q_cmpt_ctxt.color = CMPT_DEFAULT_COLOR_BIT; - q_cmpt_ctxt.ringsz_idx = cmptq->ringszidx; - q_cmpt_ctxt.bs_addr = (uint64_t)cmptq->cmpt_mz->iova; - q_cmpt_ctxt.desc_sz = cmpt_desc_fmt; - q_cmpt_ctxt.valid = 1; - - if (qdma_dev->dev_cap.cmpt_ovf_chk_dis) - q_cmpt_ctxt.ovf_chk_dis = cmptq->dis_overflow_check; - - /* Set Completion Context */ - err = qdma_dev->hw_access->qdma_cmpt_ctx_conf(dev, (qid + queue_base), - &q_cmpt_ctxt, QDMA_HW_ACCESS_WRITE); - if (err < 0) - return qdma_dev->hw_access->qdma_get_error_code(err); - - cmptq->cmpt_cidx_info.counter_idx = cmptq->threshidx; - cmptq->cmpt_cidx_info.timer_idx = cmptq->timeridx; - cmptq->cmpt_cidx_info.trig_mode = cmptq->triggermode; - cmptq->cmpt_cidx_info.wrb_en = 1; - cmptq->cmpt_cidx_info.wrb_cidx = 0; - qdma_dev->hw_access->qdma_queue_cmpt_cidx_update(dev, qdma_dev->is_vf, - qid, &cmptq->cmpt_cidx_info); - cmptq->status = RTE_ETH_QUEUE_STATE_STARTED; - - return 0; -} - -/******************************************************************************/ -/* - * Function Name: rte_pmd_qdma_dev_cmptq_start - * Description: Start the MM completion queue. - * - * @param port_id : Port ID. - * @param qid : Queue ID. - * - * @return '0' on success and '< 0' on failure. - * - * @note Application can call this API after successful call to - * rte_pmd_qdma_dev_cmptq_setup() API when queue is in - * memory mapped mode. - ******************************************************************************/ -int rte_pmd_qdma_dev_cmptq_start(int port_id, uint32_t qid) -{ - struct rte_eth_dev *dev; - struct qdma_pci_dev *qdma_dev; - int ret = 0; - - ret = validate_qdma_dev_info(port_id, qid); - if (ret != QDMA_SUCCESS) { - PMD_DRV_LOG(ERR, - "QDMA device validation failed for port id %d\n", - port_id); - return ret; - } - dev = &rte_eth_devices[port_id]; - qdma_dev = dev->data->dev_private; - if (qdma_dev->q_info[qid].queue_mode != - RTE_PMD_QDMA_MEMORY_MAPPED_MODE) { - PMD_DRV_LOG(ERR, "Qid %d is not configured in MM-mode\n", qid); - return -EINVAL; - } - - if (qid >= qdma_dev->qsets_en) { - PMD_DRV_LOG(ERR, "Invalid Queue id passed for %s," - "Queue ID(MM-mode) = %d\n", __func__, - qid); - return -EINVAL; - } - - if (qdma_dev->is_vf) - return qdma_vf_cmptq_context_write(dev, qid); - else - return qdma_pf_cmptq_context_write(dev, qid); -} - -static int qdma_pf_cmptq_context_invalidate(struct rte_eth_dev *dev, - uint32_t qid) -{ - struct qdma_pci_dev *qdma_dev = dev->data->dev_private; - struct qdma_cmpt_queue *cmptq; - uint32_t sz, i = 0; - struct qdma_descq_cmpt_ctxt q_cmpt_ctxt; - - cmptq = (struct qdma_cmpt_queue *)qdma_dev->cmpt_queues[qid]; - qdma_dev->hw_access->qdma_cmpt_ctx_conf(dev, - (qid + qdma_dev->queue_base), - &q_cmpt_ctxt, QDMA_HW_ACCESS_INVALIDATE); - - /* Zero the cmpt-ring entries*/ - sz = cmptq->cmpt_desc_len; - for (i = 0; i < (sz * cmptq->nb_cmpt_desc); i++) - ((volatile char *)cmptq->cmpt_ring)[i] = 0; - - cmptq->status = RTE_ETH_QUEUE_STATE_STOPPED; - - return 0; -} - -static int qdma_vf_cmptq_context_invalidate(struct rte_eth_dev *dev, - uint32_t qid) -{ - struct qdma_mbox_msg *m = qdma_mbox_msg_alloc(); - struct qdma_pci_dev *qdma_dev = dev->data->dev_private; - struct qdma_cmpt_queue *cmptq; - uint32_t qid_hw; - int rv; - - if (!m) - return -ENOMEM; - - qid_hw = qdma_dev->queue_base + qid; - qdma_mbox_compose_vf_qctxt_invalidate(qdma_dev->func_id, qid_hw, - 0, 0, QDMA_MBOX_CMPT_CTXT_ONLY, - m->raw_data); - rv = qdma_mbox_msg_send(dev, m, MBOX_OP_RSP_TIMEOUT); - if (rv < 0) { - if (rv != -ENODEV) - PMD_DRV_LOG(INFO, "%x, qid_hw 0x%x mbox failed %d.\n", - qdma_dev->func_id, qid_hw, rv); - goto err_out; - } - - rv = qdma_mbox_vf_response_status(m->raw_data); - - cmptq = (struct qdma_cmpt_queue *)qdma_dev->cmpt_queues[qid]; - cmptq->status = RTE_ETH_QUEUE_STATE_STOPPED; - -err_out: - qdma_mbox_msg_free(m); - return rv; -} - -/******************************************************************************/ -/* - * Function Name: rte_pmd_qdma_dev_cmptq_stop - * Description: Stop the MM completion queue. - * - * @param port_id : Port ID. - * @param qid : Queue ID. - * - * @return '0' on success and '< 0' on failure. - * - * @note Application can call this API after successful call to - * rte_pmd_qdma_dev_cmptq_start() API when queue is in - * memory mapped mode. - ******************************************************************************/ -int rte_pmd_qdma_dev_cmptq_stop(int port_id, uint32_t qid) -{ - struct rte_eth_dev *dev; - struct qdma_pci_dev *qdma_dev; - int ret = 0; - - ret = validate_qdma_dev_info(port_id, qid); - if (ret != QDMA_SUCCESS) { - PMD_DRV_LOG(ERR, - "QDMA device validation failed for port id %d\n", - port_id); - return ret; - } - dev = &rte_eth_devices[port_id]; - qdma_dev = dev->data->dev_private; - if (qdma_dev->q_info[qid].queue_mode != - RTE_PMD_QDMA_MEMORY_MAPPED_MODE) { - PMD_DRV_LOG(ERR, "Qid %d is not configured in MM-mode\n", qid); - return -EINVAL; - } - - if (qdma_dev->is_vf) - return qdma_vf_cmptq_context_invalidate(dev, qid); - else - return qdma_pf_cmptq_context_invalidate(dev, qid); -} - -/*****************************************************************************/ -/** - * Function Name: rte_pmd_qdma_mm_cmpt_process - * Description: Process the MM Completion queue entries. - * - * @param port_id : Port ID. - * @param qid : Queue ID. - * @param cmpt_buff : User buffer pointer to store the completion data. - * @param nb_entries: Number of compeltion entries to process. - * - * @return 'number of entries processed' on success and '< 0' on failure. - * - * @note Application can call this API after successful call to - * rte_pmd_qdma_dev_cmptq_start() API. - ******************************************************************************/ - -uint16_t rte_pmd_qdma_mm_cmpt_process(int port_id, uint32_t qid, - void *cmpt_buff, uint16_t nb_entries) -{ - struct rte_eth_dev *dev; - struct qdma_pci_dev *qdma_dev; - struct qdma_cmpt_queue *cmptq; - uint32_t count = 0; - struct qdma_ul_cmpt_ring *cmpt_entry; - struct wb_status *wb_status; - uint16_t nb_entries_avail = 0; - uint16_t cmpt_tail = 0; - uint16_t cmpt_pidx; - int ret = 0; - - ret = validate_qdma_dev_info(port_id, qid); - if (ret != QDMA_SUCCESS) { - PMD_DRV_LOG(ERR, - "QDMA device validation failed for port id %d\n", - port_id); - return ret; - } - dev = &rte_eth_devices[port_id]; - qdma_dev = dev->data->dev_private; - if (qdma_dev->q_info[qid].queue_mode != - RTE_PMD_QDMA_MEMORY_MAPPED_MODE) { - PMD_DRV_LOG(ERR, "Qid %d is not configured in MM-mode\n", qid); - return -EINVAL; - } - - cmptq = (struct qdma_cmpt_queue *)qdma_dev->cmpt_queues[qid]; - - if (cmpt_buff == NULL) { - PMD_DRV_LOG(ERR, "Invalid user buffer pointer from user"); - return 0; - } - - wb_status = cmptq->wb_status; - cmpt_tail = cmptq->cmpt_cidx_info.wrb_cidx; - cmpt_pidx = wb_status->pidx; - - if (cmpt_tail < cmpt_pidx) - nb_entries_avail = cmpt_pidx - cmpt_tail; - else if (cmpt_tail > cmpt_pidx) - nb_entries_avail = cmptq->nb_cmpt_desc - 1 - cmpt_tail + - cmpt_pidx; - - if (nb_entries_avail == 0) { - PMD_DRV_LOG(DEBUG, "%s(): %d: nb_entries_avail = 0\n", - __func__, __LINE__); - return 0; - } - - if (nb_entries > nb_entries_avail) - nb_entries = nb_entries_avail; - - while (count < nb_entries) { - cmpt_entry = - (struct qdma_ul_cmpt_ring *)((uint64_t)cmptq->cmpt_ring + - ((uint64_t)cmpt_tail * cmptq->cmpt_desc_len)); - - ret = qdma_ul_process_immediate_data(cmpt_entry, - cmptq->cmpt_desc_len, cmpt_buff); - if (ret < 0) { - PMD_DRV_LOG(ERR, "Error detected on CMPT ring at " - "index %d, queue_id = %d\n", - cmpt_tail, - cmptq->queue_id); - return 0; - } - cmpt_tail++; - if (unlikely(cmpt_tail >= (cmptq->nb_cmpt_desc - 1))) - cmpt_tail -= (cmptq->nb_cmpt_desc - 1); - count++; - } - - // Update the CPMT CIDX - cmptq->cmpt_cidx_info.wrb_cidx = cmpt_tail; - qdma_dev->hw_access->qdma_queue_cmpt_cidx_update(cmptq->dev, - qdma_dev->is_vf, - cmptq->queue_id, - &cmptq->cmpt_cidx_info); - return count; -} - -/*****************************************************************************/ -/** - * Function Name: rte_pmd_qdma_dev_close - * Description: DPDK PMD function to close the device. - * - * @param port_id Port ID - * - * @return '0' on success and '< 0' on failure - * - ******************************************************************************/ -int rte_pmd_qdma_dev_close(uint16_t port_id) -{ - struct rte_eth_dev *dev; - struct qdma_pci_dev *qdma_dev; - - if (port_id >= rte_eth_dev_count_avail()) { - PMD_DRV_LOG(ERR, "%s:%d Wrong port id %d\n", __func__, __LINE__, - port_id); - return -ENOTSUP; - } - dev = &rte_eth_devices[port_id]; - qdma_dev = dev->data->dev_private; - - dev->data->dev_started = 0; - - if (qdma_dev->is_vf) - qdma_vf_dev_close(dev); - else - qdma_dev_close(dev); - - dev->data->nb_rx_queues = 0; - rte_free(dev->data->rx_queues); - dev->data->rx_queues = NULL; - dev->data->nb_tx_queues = 0; - rte_free(dev->data->tx_queues); - dev->data->tx_queues = NULL; - - return 0; -} - diff --git a/QDMA/DPDK/drivers/net/qdma/rte_pmd_qdma.h b/QDMA/DPDK/drivers/net/qdma/rte_pmd_qdma.h deleted file mode 100755 index 8a6e95c93..000000000 --- a/QDMA/DPDK/drivers/net/qdma/rte_pmd_qdma.h +++ /dev/null @@ -1,888 +0,0 @@ -/*- - * BSD LICENSE - * - * Copyright (c) 2019-2022 Xilinx, Inc. All rights reserved. - * Copyright (c) 2022-2023, Advanced Micro Devices, Inc. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * * Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#ifndef __RTE_PMD_QDMA_EXPORT_H__ -#define __RTE_PMD_QDMA_EXPORT_H__ - -#include -#include -#include -#include -#include -#include -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/** @defgroup rte_pmd_qdma_enums Enumerations - */ -/** @defgroup rte_pmd_qdma_struct Data Structures - */ -/** @defgroup rte_pmd_qdma_func Functions - */ - -/** - * Bypass modes in C2H direction - * @ingroup rte_pmd_qdma_enums - */ -enum rte_pmd_qdma_rx_bypass_mode { - /** C2H bypass mode disabled */ - RTE_PMD_QDMA_RX_BYPASS_NONE = 0, - /** C2H cache bypass mode */ - RTE_PMD_QDMA_RX_BYPASS_CACHE = 1, - /** C2H simple bypass mode */ - RTE_PMD_QDMA_RX_BYPASS_SIMPLE = 2, - /** C2H bypass mode invalid */ - RTE_PMD_QDMA_RX_BYPASS_MAX -}; - -/** - * Bypass modes in H2C direction - * @ingroup rte_pmd_qdma_enums - */ -enum rte_pmd_qdma_tx_bypass_mode { - /** H2C bypass mode disabled */ - RTE_PMD_QDMA_TX_BYPASS_NONE = 0, - /** H2C bypass mode enabled */ - RTE_PMD_QDMA_TX_BYPASS_ENABLE = 1, - /** H2C bypass mode invalid */ - RTE_PMD_QDMA_TX_BYPASS_MAX -}; - -/** - * Enum to specify the direction i.e. TX or RX - * @ingroup rte_pmd_qdma_enums - */ -enum rte_pmd_qdma_dir_type { - /** H2C direction */ - RTE_PMD_QDMA_TX = 0, - /** C2H direction */ - RTE_PMD_QDMA_RX, - /** Invalid Direction */ - RTE_PMD_QDMA_DIR_TYPE_MAX -}; - -/** - * Enum to specify the PCIe function type i.e. PF or VF - * @ingroup rte_pmd_qdma_enums - */ -enum rte_pmd_qdma_pci_func_type { - /** Physical Function */ - RTE_PMD_QDMA_PCI_FUNC_PF, - /** Virtual Function */ - RTE_PMD_QDMA_PCI_FUNC_VF, - /** Invalid PCI Function */ - RTE_PMD_QDMA_PCI_FUNC_TYPE_MAX, -}; - -/** - * Enum to specify the queue mode - * @ingroup rte_pmd_qdma_enums - */ -enum rte_pmd_qdma_queue_mode_t { - /** Memory mapped queue mode */ - RTE_PMD_QDMA_MEMORY_MAPPED_MODE, - /** Streaming queue mode */ - RTE_PMD_QDMA_STREAMING_MODE, - /** Invalid queue mode */ - RTE_PMD_QDMA_QUEUE_MODE_MAX, -}; - -/** - * Enum to specify the completion trigger mode - * @ingroup rte_pmd_qdma_enums - */ -enum rte_pmd_qdma_tigger_mode_t { - /** Trigger mode disabled */ - RTE_PMD_QDMA_TRIG_MODE_DISABLE, - /** Trigger mode every */ - RTE_PMD_QDMA_TRIG_MODE_EVERY, - /** Trigger mode user count */ - RTE_PMD_QDMA_TRIG_MODE_USER_COUNT, - /** Trigger mode user */ - RTE_PMD_QDMA_TRIG_MODE_USER, - /** Trigger mode timer */ - RTE_PMD_QDMA_TRIG_MODE_USER_TIMER, - /** Trigger mode timer + count */ - RTE_PMD_QDMA_TRIG_MODE_USER_TIMER_COUNT, - /** Trigger mode invalid */ - RTE_PMD_QDMA_TRIG_MODE_MAX, -}; - -/** - * Enum to specify the completion descriptor length - * @ingroup rte_pmd_qdma_enums - */ -enum rte_pmd_qdma_cmpt_desc_len { - /** 8B Completion descriptor */ - RTE_PMD_QDMA_CMPT_DESC_LEN_8B = 8, - /** 16B Completion descriptor */ - RTE_PMD_QDMA_CMPT_DESC_LEN_16B = 16, - /** 32B Completion descriptor */ - RTE_PMD_QDMA_CMPT_DESC_LEN_32B = 32, - /** 64B Completion descriptor */ - RTE_PMD_QDMA_CMPT_DESC_LEN_64B = 64, - /** Invalid Completion descriptor */ - RTE_PMD_QDMA_CMPT_DESC_LEN_MAX, -}; - -/** - * Enum to specify the bypass descriptor length - * @ingroup rte_pmd_qdma_enums - */ -enum rte_pmd_qdma_bypass_desc_len { - /** 8B Bypass descriptor */ - RTE_PMD_QDMA_BYPASS_DESC_LEN_8B = 8, - /** 16B Bypass descriptor */ - RTE_PMD_QDMA_BYPASS_DESC_LEN_16B = 16, - /** 32B Bypass descriptor */ - RTE_PMD_QDMA_BYPASS_DESC_LEN_32B = 32, - /** 64B Bypass descriptor */ - RTE_PMD_QDMA_BYPASS_DESC_LEN_64B = 64, - /** Invalid Bypass descriptor */ - RTE_PMD_QDMA_BYPASS_DESC_LEN_MAX, -}; - -/** - * Enum to specify the debug request type - * @ingroup rte_pmd_qdma_enums - */ -enum rte_pmd_qdma_xdebug_type { - /** Debug Global registers */ - RTE_PMD_QDMA_XDEBUG_QDMA_GLOBAL_CSR, - /** Debug Device specific structure */ - RTE_PMD_QDMA_XDEBUG_QDMA_DEVICE_STRUCT, - /** Debug Queue information */ - RTE_PMD_QDMA_XDEBUG_QUEUE_INFO, - /** Debug descriptor */ - RTE_PMD_QDMA_XDEBUG_QUEUE_DESC_DUMP, - /** Invalid debug type */ - RTE_PMD_QDMA_XDEBUG_MAX, -}; - -/** - * Enum to specify the queue ring for debug - * @ingroup rte_pmd_qdma_enums - */ -enum rte_pmd_qdma_xdebug_desc_type { - /** Debug C2H ring descriptor */ - RTE_PMD_QDMA_XDEBUG_DESC_C2H, - /** Debug H2C ring descriptor */ - RTE_PMD_QDMA_XDEBUG_DESC_H2C, - /** Debug CMPT ring descriptor */ - RTE_PMD_QDMA_XDEBUG_DESC_CMPT, - /** Invalid debug type */ - RTE_PMD_QDMA_XDEBUG_DESC_MAX, -}; - -/** - * Enum to specify the QDMA device type - * @ingroup rte_pmd_qdma_enums - */ -enum rte_pmd_qdma_device_type { - /** QDMA Soft device e.g. UltraScale+ IP's */ - RTE_PMD_QDMA_DEVICE_SOFT, - /** QDMA Versal CPM4 device */ - RTE_PMD_QDMA_DEVICE_VERSAL_CPM4, - /** QDMA Versal CPM5 device */ - RTE_PMD_QDMA_DEVICE_VERSAL_CPM5, - /** Invalid QDMA device */ - RTE_PMD_QDMA_DEVICE_NONE -}; - -/** - * Enum to specify the QDMA IP type - * @ingroup rte_pmd_qdma_enums - */ -enum rte_pmd_qdma_ip_type { - /** Versal Hard IP */ - RTE_PMD_QDMA_VERSAL_HARD_IP, - /** Versal Soft IP */ - RTE_PMD_QDMA_VERSAL_SOFT_IP, - /** QDMA Soft IP */ - RTE_PMD_QDMA_SOFT_IP, - /** EQDMA Soft IP */ - RTE_PMD_EQDMA_SOFT_IP, - /** Invalid IP type */ - RTE_PMD_QDMA_NONE_IP -}; - - - - -/** - * Structure to hold the QDMA device attributes - * - * @ingroup rte_pmd_qdma_struct - */ -struct rte_pmd_qdma_dev_attributes { - /** Number of PFs*/ - uint8_t num_pfs; - /** Number of Queues */ - uint16_t num_qs; - /** Indicates whether FLR supported or not */ - uint8_t flr_present:1; - /** Indicates whether ST mode supported or not */ - uint8_t st_en:1; - /** Indicates whether MM mode supported or not */ - uint8_t mm_en:1; - /** Indicates whether MM with Completions supported or not */ - uint8_t mm_cmpt_en:1; - /** Indicates whether Mailbox supported or not */ - uint8_t mailbox_en:1; - /** Debug mode is enabled/disabled for IP */ - uint8_t debug_mode:1; - /** Descriptor Engine mode: - * Internal only/Bypass only/Internal & Bypass - */ - uint8_t desc_eng_mode:2; - /** Number of MM channels */ - uint8_t mm_channel_max; - - /** To indicate support of - * overflow check disable in CMPT ring - */ - uint8_t cmpt_ovf_chk_dis:1; - /** To indicate support of 64 bytes - * C2H/H2C descriptor format - */ - uint8_t sw_desc_64b:1; - /** To indicate support of 64 bytes - * CMPT descriptor format - */ - uint8_t cmpt_desc_64b:1; - /** To indicate support of - * counter + timer trigger mode - */ - uint8_t cmpt_trig_count_timer:1; - /** Device Type */ - enum rte_pmd_qdma_device_type device_type; - /** Versal IP Type */ - enum rte_pmd_qdma_ip_type ip_type; -}; - - -/******************************************************************************/ -/** - * Dumps the QDMA configuration registers for the given port - * - * @param port_id Port ID - * - * @return '0' on success and "< 0" on failure - * - * @note None - * @ingroup rte_pmd_qdma_func - ******************************************************************************/ -int rte_pmd_qdma_dbg_regdump(uint8_t port_id); - -/******************************************************************************/ -/** - * Dumps the QDMA register field information for a given register offset - * - * @param port_id Port ID - * @param reg_addr Register Address - * - * @return '0' on success and "< 0" on failure - * - * @note None - * @ingroup rte_pmd_qdma_func - ******************************************************************************/ -int rte_pmd_qdma_dbg_reg_info_dump(uint8_t port_id, - uint32_t num_regs, uint32_t reg_addr); - -/******************************************************************************/ -/** - * Dumps the device specific SW structure for the given port - * - * @param port_id Port ID - * - * @return '0' on success and "< 0" on failure - * - * @note None - * @ingroup rte_pmd_qdma_func - ******************************************************************************/ -int rte_pmd_qdma_dbg_qdevice(uint8_t port_id); - -/******************************************************************************/ -/** - * Dumps the qdma Tx and Rx queue stats for the given queue ID - * - * @param port_id Port ID - * @param queue Queue ID relative to the Port - * - * @return '0' on success and "< 0" on failure - * - * @note None - * @ingroup rte_pmd_qdma_func - ******************************************************************************/ -int rte_pmd_qdma_qstats(uint8_t port_id, uint16_t queue); - -/******************************************************************************/ -/** - * Clear the qdma Tx and Rx queue stats for the given queue ID - * - * @param port_id Port ID - * @param queue Queue ID relative to the Port - * - * @return '0' on success and "< 0" on failure - * - * @note None - * @ingroup rte_pmd_qdma_func - ******************************************************************************/ -int rte_pmd_qdma_qstats_clear(uint8_t port_id, uint16_t queue); - -/******************************************************************************/ -/** - * Dumps the queue contexts and queue specific SW - * structures for the given queue ID - * - * @param port_id Port ID - * @param queue Queue ID relative to the Port - * - * @return '0' on success and "< 0" on failure - * - * @note None - * @ingroup rte_pmd_qdma_func - ******************************************************************************/ -int rte_pmd_qdma_dbg_qinfo(uint8_t port_id, uint16_t queue); - -/******************************************************************************/ -/** - * Dumps the Queue descriptors - * - * @param port_id Port ID - * @param queue Queue ID relative to the Port - * @param start Start index of the descriptor to dump - * @param end End index of the descriptor to dump - * @param type Descriptor type - * - * @return '0' on success and "< 0" on failure - * - * @note None - * @ingroup rte_pmd_qdma_func - ******************************************************************************/ -int rte_pmd_qdma_dbg_qdesc(uint8_t port_id, uint16_t queue, int start, - int end, enum rte_pmd_qdma_xdebug_desc_type type); - -/******************************************************************************/ -/** - * Returns the BAR indices of the QDMA BARs - * - * @param port_id Port ID - * @param config_bar_idx Config BAR index - * @param user_bar_idx AXI Master Lite BAR(user bar) index - * @param bypass_bar_idx AXI Bridge Master BAR(bypass bar) index - * - * @return '0' on success and '< 0' on failure - * - * @note None - * @ingroup rte_pmd_qdma_func - ******************************************************************************/ -int rte_pmd_qdma_get_bar_details(int port_id, int32_t *config_bar_idx, - int32_t *user_bar_idx, int32_t *bypass_bar_idx); - -/******************************************************************************/ -/** - * Returns queue base for given port - * - * @param port_id Port ID - * @param queue_base Queue base - * - * @return '0' on success and '< 0' on failure - * - * @note Application can call this API only after successful - * call to rte_eh_dev_configure() API - * @ingroup rte_pmd_qdma_func - ******************************************************************************/ -int rte_pmd_qdma_get_queue_base(int port_id, uint32_t *queue_base); - -/******************************************************************************/ -/** - * Retrieves PCIe function type i.e. PF or VF - * - * @param port_id Port ID - * @param func_type Indicates PCIe function type - * - * @return '0' on success and '< 0' on failure - * - * @note Returns the PCIe function type i.e. PF or VF of the given port - * @ingroup rte_pmd_qdma_func - ******************************************************************************/ -int rte_pmd_qdma_get_pci_func_type(int port_id, - enum rte_pmd_qdma_pci_func_type *func_type); - -/******************************************************************************/ -/** - * Returns immediate data state i.e. whether enabled or disabled, - * for the specified queue - * - * @param port_id Port ID - * @param qid Queue ID - * @param state Pointer to the state specifying whether - * immediate data is enabled or not - * @return '0' on success and '< 0' on failure - * - * @note Application can call this function after - * rte_eth_rx_queue_setup() is called. - * API is applicable for streaming queues only. - * @ingroup rte_pmd_qdma_func - ******************************************************************************/ -int rte_pmd_qdma_get_immediate_data_state(int port_id, uint32_t qid, - int *state); - -/******************************************************************************/ -/** - * Sets queue interface mode for the specified queue - * - * @param port_id Port ID - * @param qid Queue ID - * @param mode Queue interface mode to be set - * - * @return '0' on success and '< 0' on failure - * - * @note Application can call this API after successful call to - * rte_eth_dev_configure() but before - * rte_eth_tx_queue_setup()/rte_eth_rx_queue_setup() API. - * By default, all queues are setup in streaming mode. - * @ingroup rte_pmd_qdma_func - ******************************************************************************/ -int rte_pmd_qdma_set_queue_mode(int port_id, uint32_t qid, - enum rte_pmd_qdma_queue_mode_t mode); - -/******************************************************************************/ -/** - * Sets immediate data state i.e. enable or disable, for the specified queue. - * If enabled, the user defined data in the completion - * ring are dumped in to a queue specific file - * "q__immmediate_data.txt" in the local directory. - * - *@param port_id Port ID - *@param qid Queue ID - *@param state Immediate data state to be set. - * Set '0' to disable and '1' to enable. - * - *@return '0' on success and '< 0' on failure - * - *@note Application can call this API after successful - * call to rte_eth_rx_queue_setup() API. - * This API is applicable for streaming queues only. - * @ingroup rte_pmd_qdma_func - ******************************************************************************/ -int rte_pmd_qdma_set_immediate_data_state(int port_id, uint32_t qid, - uint8_t state); - -/******************************************************************************/ -/** - * Enables or disables the overflow check (whether PIDX is overflowing - * the CIDX) performed by QDMA on the completion descriptor ring of specified - * queue. - * - * @param port_id Port ID - * @param qid Queue ID - * @param enable '1' to enable and '0' to disable the overflow check - * - * @return '0' on success and '< 0' on failure - * - * @note Application can call this API after successful call to - * rte_eth_rx_queue_setup() API, but before calling - * rte_eth_rx_queue_start() or rte_eth_dev_start() API. - * @ingroup rte_pmd_qdma_func - ******************************************************************************/ -int rte_pmd_qdma_set_cmpt_overflow_check(int port_id, uint32_t qid, - uint8_t enable); - -/******************************************************************************/ -/** - * Configures the completion ring descriptor size - * - * @param port_id Port ID - * @param qid Queue ID - * @param size Descriptor size to be configured - * - * @return '0' on success and '< 0' on failure - * - * @note Application can call this API after successful call to - * rte_eth_dev_configure() but before rte_eth_rx_queue_setup() API - * when queue is in streaming mode, and before - * rte_pmd_qdma_dev_cmptq_setup when queue is in - * memory mapped mode. - * By default, the completion desciptor size is set to 8 bytes. - * @ingroup rte_pmd_qdma_func - ******************************************************************************/ -int rte_pmd_qdma_set_cmpt_descriptor_size(int port_id, uint32_t qid, - enum rte_pmd_qdma_cmpt_desc_len size); - -/******************************************************************************/ -/** - * Configures the trigger mode for completion ring CIDX updates - * - * @param port_id Port ID - * @param qid Queue ID - * @param mode Trigger mode to be configured - * - * @return '0' on success and '< 0' on failure - * - * @note Application can call this API before calling - * rte_eth_rx_queue_start() or rte_eth_dev_start() API. - * By default, trigger mode is set to - * RTE_PMD_QDMA_TRIG_MODE_USER_TIMER_COUNT. - * @ingroup rte_pmd_qdma_func - ******************************************************************************/ -int rte_pmd_qdma_set_cmpt_trigger_mode(int port_id, uint32_t qid, - enum rte_pmd_qdma_tigger_mode_t mode); - -/******************************************************************************/ -/** - * Configures the timer interval in microseconds to trigger - * the completion ring CIDX updates - * - * @param port_id Port ID - * @param qid Queue ID - * @param value Timer interval for completion trigger to be configured - * - * @return '0' on success and '< 0' on failure - * - * @note Application can call this API before calling - * rte_eth_rx_queue_start() or rte_eth_dev_start() API. - * @ingroup rte_pmd_qdma_func - ******************************************************************************/ -int rte_pmd_qdma_set_cmpt_timer(int port_id, uint32_t qid, uint32_t value); - -/******************************************************************************/ -/** - * Enables or disables prefetch of the descriptors by prefetch engine - * - *@param port_id Port ID - *@param qid Queue ID - *@param enable '1' to enable and '0' to disable the descriptor prefetch - * - *@return '0' on success and '< 0' on failure - * - *@note Application can call this API after successful call to - * rte_eth_rx_queue_setup() API, but before calling - * rte_eth_rx_queue_start() or rte_eth_dev_start() API. - * @ingroup rte_pmd_qdma_func - ******************************************************************************/ -int rte_pmd_qdma_set_c2h_descriptor_prefetch(int port_id, uint32_t qid, - uint8_t enable); - -/*****************************************************************************/ -/** - * Sets the PCIe endpoint memory offset at which to - * perform DMA operation for the specified queue operating - * in memory mapped mode. - * - * @param port_id Port ID - * @param qid Queue ID - * @param dir Direction i.e. Tx or Rx - * @param addr Destination address for Tx, Source address for Rx - * - * @return '0' on success and '< 0' on failure - * - * @note This API can be called before Tx/Rx burst API's - * (rte_eth_tx_burst() and rte_eth_rx_burst()) are called. - * @ingroup rte_pmd_qdma_func - *****************************************************************************/ -int rte_pmd_qdma_set_mm_endpoint_addr(int port_id, uint32_t qid, - enum rte_pmd_qdma_dir_type dir, uint64_t addr); - -/******************************************************************************/ -/** - * Sets the Tx bypass mode and bypass descriptor size for the specified queue - * - * @param port_id Port ID - * @param qid Queue ID - * @param bypass_mode Bypass mode to be set - * @param size Bypass descriptor size to be set - * - * @return '0' on success and '< 0' on failure - * - * @note Application can call this API after successful call to - * rte_eth_dev_configure() but before tx_setup() API. - * By default, all queues are configured in internal mode - * i.e. bypass disabled. - * If size is specified zero, then the bypass descriptor size is - * set to the one used in internal mode. - * @ingroup rte_pmd_qdma_func - ******************************************************************************/ -int rte_pmd_qdma_configure_tx_bypass(int port_id, uint32_t qid, - enum rte_pmd_qdma_tx_bypass_mode bypass_mode, - enum rte_pmd_qdma_bypass_desc_len size); - -/******************************************************************************/ -/** - * Sets the Rx bypass mode and bypass descriptor size for the specified queue - * - * @param port_id Port ID - * @param qid Queue ID - * @param bypass_mode Bypass mode to be set - * @param size Bypass descriptor size to be set - * - * @return '0' on success and '< 0' on failure - * - * @note Application can call this API after successful call to - * rte_eth_dev_configure() but before rte_eth_rx_queue_setup() API. - * By default, all queues are configured in internal mode - * i.e. bypass disabled. - * If size is specified zero, then the bypass descriptor size is - * set to the one used in internal mode. - * @ingroup rte_pmd_qdma_func - ******************************************************************************/ -int rte_pmd_qdma_configure_rx_bypass(int port_id, uint32_t qid, - enum rte_pmd_qdma_rx_bypass_mode bypass_mode, - enum rte_pmd_qdma_bypass_desc_len size); - -/******************************************************************************/ -/** - * Retrive the device capabilities - * - * @param port_id Port ID - * @param dev_attr Pointer to the device capabilities structure - * - * @return '0' on success and '< 0' on failure - * - * @note None. - * @ingroup rte_pmd_qdma_func - ******************************************************************************/ -int rte_pmd_qdma_get_device_capabilities(int port_id, - struct rte_pmd_qdma_dev_attributes *dev_attr); - -/******************************************************************************/ -/** - * Allocate and set up a completion queue for memory mapped mode - * - * @param port_id Port ID - * @param qid Queue ID - * @param nb_cmpt_desc Completion queue ring size - * @param socket_id The socket_id argument is the socket identifier - * in case of NUMA. Its value can be SOCKET_ID_ANY - * if there is no NUMA constraint for the DMA memory - * allocated for the transmit descriptors of the ring. - * - * @return '0' on success and '< 0' on failure - * - * @note Application can call this API after successful call to - * rte_eth_dev_configure() and rte_pmd_qdma_set_queue_mode() - * for queues in memory mapped mode. - * @ingroup rte_pmd_qdma_func - ******************************************************************************/ -int rte_pmd_qdma_dev_cmptq_setup(int port_id, uint32_t cmpt_queue_id, - uint16_t nb_cmpt_desc, - unsigned int socket_id); - -/******************************************************************************/ -/** - * Start the MM completion queue - * - * @param port_id Port ID - * @param qid Queue ID - * - * @return '0' on success and '< 0' on failure - * - * @note Application can call this API after successful call to - * rte_pmd_qdma_dev_cmptq_setup() API when queue is in - * memory mapped mode. - * @ingroup rte_pmd_qdma_func - ******************************************************************************/ -int rte_pmd_qdma_dev_cmptq_start(int port_id, uint32_t qid); - -/******************************************************************************/ -/** - * Stop the MM completion queue - * - * @param port_id Port ID - * @param qid Queue ID - * - * @return '0' on success and '< 0' on failure - * - * @note Application can call this API after successful call to - * rte_pmd_qdma_dev_cmptq_start() API when queue is in - * memory mapped mode. - * @ingroup rte_pmd_qdma_func - ******************************************************************************/ -int rte_pmd_qdma_dev_cmptq_stop(int port_id, uint32_t qid); - -/*****************************************************************************/ -/** - * Process the MM Completion queue entries - * - * @param port_id Port ID - * @param qid Queue ID - * @param cmpt_buff User buffer pointer to store the completion data - * @param nb_entries Number of compeltion entries to process - * - * @return 'number of entries processed' on success and '< 0' on failure - * - * @note Application can call this API after successful call to - * rte_pmd_qdma_dev_cmptq_start() API - * @ingroup rte_pmd_qdma_func - ******************************************************************************/ -uint16_t rte_pmd_qdma_mm_cmpt_process(int port_id, uint32_t qid, - void *cmpt_buff, uint16_t nb_entries); - -/*****************************************************************************/ -/** - * DPDK PMD function to close the device. - * - * @param port_id Port ID - * - * @return '0' on success and '< 0' on failure - * - ******************************************************************************/ -int rte_pmd_qdma_dev_close(uint16_t port_id); - -/*****************************************************************************/ -/** - * DPDK PMD function to fill fast-path operations. - * - * @param port_id Port ID - * - * @return on success return 0 - * - ******************************************************************************/ -int rte_pmd_qdma_dev_fp_ops_config(int port_id); - -/*****************************************************************************/ -/** - * DPDK PMD compatibility function to read pci registers. - * - * @param port_id Port ID - * @param bar Bar - * @param offset Offset - * - * @return pci_read_reg value - * - ******************************************************************************/ -unsigned int rte_pmd_qdma_compat_pci_read_reg(int port_id, - unsigned int bar, unsigned int offset); - -/*****************************************************************************/ -/** - * DPDK PMD compatibility function to write pci registers. - * - * @param port_id Port ID - * @param bar Bar - * @param offset Offset - * @param reg_val Value which needs to write - * - ******************************************************************************/ -void rte_pmd_qdma_compat_pci_write_reg(int port_id, uint32_t bar, - uint32_t offset, uint32_t reg_val); - -/*****************************************************************************/ -/** - * DPDK PMD compatibility function to get bdf - * - * @param m_id Port ID - * @param bus Bus - * @param dev Device - * @param fn Function - * - ******************************************************************************/ -void rte_pmd_qdma_get_bdf(uint32_t m_id, uint32_t *bus, - uint32_t *dev, uint32_t *fn); - -/*****************************************************************************/ -/** - * DPDK PMD compatibility function to reserve memzone - * - ******************************************************************************/ -void rte_pmd_qdma_compat_memzone_reserve_aligned(void); - -/*****************************************************************************/ -/** - * DPDK PMD compatibility function to device remove - * - * @param port_id Port ID - * @return device id to remove - * - ******************************************************************************/ -int rte_pmd_qdma_dev_remove(int port_id); - -/*****************************************************************************/ -/** - * DPDK PMD compatibility function to get device id - * - * @param port_id Port ID - * @return device id to get - * - ******************************************************************************/ -uint16_t rte_pmd_qdma_get_dev_id(int port_id); - -/*****************************************************************************/ -/** - * DPDK PMD compatibility function to device started - * - * @param port_id Port ID - * @param status Enable/Disable - * - ******************************************************************************/ -void rte_pmd_qdma_dev_started(int port_id, bool status); - -/*****************************************************************************/ -/** - * DPDK PMD compatibility function for eth dev to pci - * - * @param port_id Port ID - * @return rte_pci_device* pci_device - * - ******************************************************************************/ - -struct rte_pci_device *rte_pmd_qdma_eth_dev_to_pci(int port_id); - -/*****************************************************************************/ -/** - * DPDK PMD compatibility function to get rte device - * - * @param port_id Port ID - * @return rte_device* rte_device - * - ******************************************************************************/ -struct rte_device *rte_pmd_qdma_get_device(int port_id); - -/*****************************************************************************/ -/** - * DPDK PMD compatibility function to validate rte device - * - * @param port_id Port ID - * @return bool true/false - * - ******************************************************************************/ -bool rte_pmd_qdma_validate_dev(int port_id); - -#ifdef __cplusplus -} -#endif -#endif /* ifndef __RTE_PMD_QDMA_EXPORT_H__ */ diff --git a/QDMA/DPDK/drivers/net/qdma/version.h b/QDMA/DPDK/drivers/net/qdma/version.h deleted file mode 100755 index 8e44e3a27..000000000 --- a/QDMA/DPDK/drivers/net/qdma/version.h +++ /dev/null @@ -1,52 +0,0 @@ -/*- - * BSD LICENSE - * - * Copyright (c) 2017-2022 Xilinx, Inc. All rights reserved. - * Copyright (c) 2022-2023, Advanced Micro Devices, Inc. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * * Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#ifndef __QDMA_VERSION_H__ -#define __QDMA_VERSION_H__ - -#define qdma_stringify1(x...) #x -#define qdma_stringify(x...) qdma_stringify1(x) - -#define QDMA_PMD_MAJOR 2023 -#define QDMA_PMD_MINOR 2 -#define QDMA_PMD_PATCHLEVEL 1 - -#define QDMA_PMD_VERSION \ - qdma_stringify(QDMA_PMD_MAJOR) "." \ - qdma_stringify(QDMA_PMD_MINOR) "." \ - qdma_stringify(QDMA_PMD_PATCHLEVEL) - -#define QDMA_PMD_VERSION_NUMBER \ - ((QDMA_PMD_MAJOR) * 1000 + (QDMA_PMD_MINOR) * 100 + QDMA_PMD_PATCHLEVEL) - -#endif /* ifndef __QDMA_VERSION_H__ */ diff --git a/QDMA/DPDK/drivers/net/qdma/version.map b/QDMA/DPDK/drivers/net/qdma/version.map deleted file mode 100755 index 29441454f..000000000 --- a/QDMA/DPDK/drivers/net/qdma/version.map +++ /dev/null @@ -1,166 +0,0 @@ -/*- - * BSD LICENSE - * - * Copyright (c) 2017-2022 Xilinx, Inc. All rights reserved. - * Copyright (c) 2022-2023, Advanced Micro Devices, Inc. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * * Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -DPDK_21 { - global: - - rte_pmd_qdma_set_immediate_data_state; - rte_pmd_qdma_get_bar_details; - rte_pmd_qdma_get_queue_base; - rte_pmd_qdma_set_queue_mode; - rte_pmd_qdma_get_device_capabilities; - qdma_pci_read_reg; - qdma_pci_write_reg; - rte_pmd_qdma_set_mm_endpoint_addr; - rte_pmd_qdma_dbg_qdesc; - rte_pmd_qdma_dbg_regdump; - rte_pmd_qdma_dbg_reg_info_dump; - rte_pmd_qdma_dbg_qinfo; - - rte_pmd_qdma_get_pci_func_type; - rte_pmd_qdma_configure_tx_bypass; - rte_pmd_qdma_configure_rx_bypass; - rte_pmd_qdma_set_cmpt_descriptor_size; - rte_pmd_qdma_set_c2h_descriptor_prefetch; - rte_pmd_qdma_set_cmpt_overflow_check; - rte_pmd_qdma_set_cmpt_trigger_mode; - rte_pmd_qdma_set_cmpt_timer; - rte_pmd_qdma_get_immediate_data_state; - rte_pmd_qdma_dev_cmptq_setup; - rte_pmd_qdma_dev_cmptq_start; - rte_pmd_qdma_mm_cmpt_process; - rte_pmd_qdma_dev_cmptq_stop; - rte_pmd_qdma_dbg_qdevice; - rte_pmd_qdma_qstats; - rte_pmd_qdma_qstats_clear; - rte_pmd_qdma_dev_close; - rte_pmd_qdma_dev_fp_ops_config; - - local: *; -}; - -DPDK_22 { - global: - - rte_pmd_qdma_set_immediate_data_state; - rte_pmd_qdma_get_bar_details; - rte_pmd_qdma_get_queue_base; - rte_pmd_qdma_set_queue_mode; - rte_pmd_qdma_get_device_capabilities; - qdma_pci_read_reg; - qdma_pci_write_reg; - rte_pmd_qdma_set_mm_endpoint_addr; - rte_pmd_qdma_dbg_qdesc; - rte_pmd_qdma_dbg_regdump; - rte_pmd_qdma_dbg_reg_info_dump; - rte_pmd_qdma_dbg_qinfo; - - rte_pmd_qdma_get_pci_func_type; - rte_pmd_qdma_configure_tx_bypass; - rte_pmd_qdma_configure_rx_bypass; - rte_pmd_qdma_set_cmpt_descriptor_size; - rte_pmd_qdma_set_c2h_descriptor_prefetch; - rte_pmd_qdma_set_cmpt_overflow_check; - rte_pmd_qdma_set_cmpt_trigger_mode; - rte_pmd_qdma_set_cmpt_timer; - rte_pmd_qdma_get_immediate_data_state; - rte_pmd_qdma_dev_cmptq_setup; - rte_pmd_qdma_dev_cmptq_start; - rte_pmd_qdma_mm_cmpt_process; - rte_pmd_qdma_dev_cmptq_stop; - rte_pmd_qdma_dbg_qdevice; - rte_pmd_qdma_qstats; - rte_pmd_qdma_qstats_clear; - rte_pmd_qdma_dev_close; - rte_pmd_qdma_dev_fp_ops_config; - rte_pmd_qdma_compat_pci_write_reg; - rte_pmd_qdma_compat_pci_read_reg; - rte_pmd_qdma_compat_memzone_reserve_aligned; - rte_pmd_qdma_get_bdf; - rte_pmd_qdma_dev_remove; - rte_pmd_qdma_get_dev_id; - rte_pmd_qdma_dev_started; - rte_pmd_qdma_eth_dev_to_pci; - rte_pmd_qdma_get_device; - rte_pmd_qdma_validate_dev; - - local: *; -}; - -DPDK_23 { - global: - - rte_pmd_qdma_set_immediate_data_state; - rte_pmd_qdma_get_bar_details; - rte_pmd_qdma_get_queue_base; - rte_pmd_qdma_set_queue_mode; - rte_pmd_qdma_get_device_capabilities; - qdma_pci_read_reg; - qdma_pci_write_reg; - rte_pmd_qdma_set_mm_endpoint_addr; - rte_pmd_qdma_dbg_qdesc; - rte_pmd_qdma_dbg_regdump; - rte_pmd_qdma_dbg_reg_info_dump; - rte_pmd_qdma_dbg_qinfo; - - rte_pmd_qdma_get_pci_func_type; - rte_pmd_qdma_configure_tx_bypass; - rte_pmd_qdma_configure_rx_bypass; - rte_pmd_qdma_set_cmpt_descriptor_size; - rte_pmd_qdma_set_c2h_descriptor_prefetch; - rte_pmd_qdma_set_cmpt_overflow_check; - rte_pmd_qdma_set_cmpt_trigger_mode; - rte_pmd_qdma_set_cmpt_timer; - rte_pmd_qdma_get_immediate_data_state; - rte_pmd_qdma_dev_cmptq_setup; - rte_pmd_qdma_dev_cmptq_start; - rte_pmd_qdma_mm_cmpt_process; - rte_pmd_qdma_dev_cmptq_stop; - rte_pmd_qdma_dbg_qdevice; - rte_pmd_qdma_qstats; - rte_pmd_qdma_qstats_clear; - rte_pmd_qdma_dev_close; - rte_pmd_qdma_dev_fp_ops_config; - rte_pmd_qdma_compat_pci_write_reg; - rte_pmd_qdma_compat_pci_read_reg; - rte_pmd_qdma_compat_memzone_reserve_aligned; - rte_pmd_qdma_get_bdf; - rte_pmd_qdma_dev_remove; - rte_pmd_qdma_get_dev_id; - rte_pmd_qdma_dev_started; - rte_pmd_qdma_eth_dev_to_pci; - rte_pmd_qdma_get_device; - rte_pmd_qdma_validate_dev; - - local: *; -}; diff --git a/QDMA/DPDK/examples/qdma_testapp/Makefile b/QDMA/DPDK/examples/qdma_testapp/Makefile deleted file mode 100755 index 177c5cf4e..000000000 --- a/QDMA/DPDK/examples/qdma_testapp/Makefile +++ /dev/null @@ -1,97 +0,0 @@ -# BSD LICENSE -# -# Copyright (c) 2017-2022 Xilinx, Inc. All rights reserved. -# Copyright (c) 2022-2023, Advanced Micro Devices, Inc. All rights reserved. -# -# Redistribution and use in source and binary forms, with or without -# modification, are permitted provided that the following conditions -# are met: -# -# * Redistributions of source code must retain the above copyright -# notice, this list of conditions and the following disclaimer. -# * Redistributions in binary form must reproduce the above copyright -# notice, this list of conditions and the following disclaimer in -# the documentation and/or other materials provided with the -# distribution. -# * Neither the name of the copyright holder nor the names of its -# contributors may be used to endorse or promote products derived -# from this software without specific prior written permission. -# -# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -ifeq ($(RTE_SDK),) -$(error "Please define RTE_SDK environment variable") -endif - -# Default target, can be overriden by command line or environment -RTE_TARGET ?= build - -#Default BRAM size is set to 512K -#if modified the BRAM_SIZE, the same need to be set to the driver Makefile -BRAM_SIZE ?= 524288 - -# binary name -APP = qdma_testapp - -# all source are stored in SRCS-y -SRCS-y := testapp.c pcierw.c commands.c - -ifeq ($(CONFIG_RTE_LIBRTE_QDMA_GCOV),y) - CFLAGS += -g -ftest-coverage -fprofile-arcs - LDFLAGS += -lgcov -endif - -# Build using pkg-config variables if possible -ifneq ($(shell pkg-config --exists libdpdk && echo 0),0) -$(error "no installation of DPDK found") -endif - -all: shared -.PHONY: shared static -shared: build/$(APP)-shared - ln -sf $(APP)-shared build/$(APP) -static: build/$(APP)-static - ln -sf $(APP)-static build/$(APP) - -PKGCONF ?= pkg-config - -CFLAGS += -DBRAM_SIZE=$(BRAM_SIZE) -CFLAGS += -DDPDK=1 - -# Add flag to allow experimental API as qdma_testapp uses rte_ethdev_set_ptype API -CFLAGS += -DALLOW_EXPERIMENTAL_API - -PC_FILE := $(shell $(PKGCONF) --path libdpdk 2>/dev/null) -CFLAGS += -O3 $(shell $(PKGCONF) --cflags libdpdk) -LDFLAGS_SHARED = $(shell $(PKGCONF) --libs libdpdk) -LDFLAGS_STATIC = $(shell $(PKGCONF) --static --libs libdpdk) -LDFLAGS += $(shell $(PKGCONF) --libs libdpdk) - -LDFLAGS += -lrte_net_qdma - -# for shared library builds, we need to explicitly link these PMDs -LDFLAGS_SHARED += -lrte_net_qdma - -build/$(APP)-shared: $(SRCS-y) Makefile $(PC_FILE) | build - $(CC) $(CFLAGS) $(SRCS-y) -o $@ $(LDFLAGS) $(LDFLAGS_SHARED) - -build/$(APP)-static: $(SRCS-y) Makefile $(PC_FILE) | build - $(CC) $(CFLAGS) $(SRCS-y) -o $@ $(LDFLAGS) $(LDFLAGS_STATIC) - -build: - @mkdir -p $@ - -.PHONY: clean -clean: - rm -f build/$(APP) build/$(APP)-static build/$(APP)-shared - test -d build && rmdir -p build || true diff --git a/QDMA/DPDK/examples/qdma_testapp/commands.c b/QDMA/DPDK/examples/qdma_testapp/commands.c deleted file mode 100755 index 20e8af7f5..000000000 --- a/QDMA/DPDK/examples/qdma_testapp/commands.c +++ /dev/null @@ -1,1526 +0,0 @@ -/*- - * BSD LICENSE - * - * Copyright (c) 2017-2022 Xilinx, Inc. All rights reserved. - * Copyright (c) 2022-2023, Advanced Micro Devices, Inc. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * * Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -/*- - * BSD LICENSE - * - * Copyright (c) 2010-2014 Intel Corporation. All rights reserved. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * * Neither the name of Intel Corporation nor the names of its - * contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -/* - * Copyright (c) 2009, Olivier MATZ - * All rights reserved. - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of the University of California, Berkeley nor the - * names of its contributors may be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND ANY - * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE REGENTS AND CONTRIBUTORS BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#ifndef __linux__ -#include -#endif - -#include -#include -#include -#include -#include -#include - -#include -#include -#include - -#include "parse_obj_list.h" -#include "pcierw.h" -#include "commands.h" -#include "qdma_regs.h" -#include "testapp.h" -#include "../../drivers/net/qdma/rte_pmd_qdma.h" - -#define ALIGN_TO_WORD_BYTES (4) -#define NUMERICAL_BASE_HEXADECIMAL (16) - -/* Command help */ -struct cmd_help_result { - cmdline_fixed_string_t help; -}; - -static void cmd_help_parsed(__attribute__((unused)) void *parsed_result, - struct cmdline *cl, - __attribute__((unused)) void *data) -{ - cmdline_printf(cl, - "Demo example of command line interface in RTE\n\n" - "This is a readline-like interface that can be " - "used to\n debug your RTE application.\n\n" - "Supported Commands:\n" - "\tport_init " - " " - " " - " :port-initailization\n" - "\tport_close " - ":port-close\n" - "\tport_reset " - " " - " " - " :port-reset\n" - "\tport_remove " - ":port-remove\n" - "\treg_read
" - ":Reads Specified Register\n" - "\treg_write
" - " " - ":Writes Specified Register\n" - "\tdma_to_device " - " " - " " - ":To Transmit\n" - "\tdma_from_device " - " " - " " - ":To Receive\n" - "\treg_dump " - ":To dump all the valid registers\n" - "\treg_info_read " - ":Reads the field info for the specified number of registers\n" - "\tqueue_dump " - ":To dump the queue-context of a queue-number\n" - "\tqstats " - ":To dump the queue-stats of a queue-number\n" - "\tqstats_clr " - ":To clear the queue-stats of a queue-number\n" - "\tdesc_dump " - ":To dump the descriptor-fields of a " - "queue-number\n" - "\tload_cmds " - ":To execute the list of commands from file\n" - "\thelp\n" - "\tCtrl-d " - ": To quit from this command-line type Ctrl+d\n" - "\n"); -} - -cmdline_parse_token_string_t cmd_help_help = - TOKEN_STRING_INITIALIZER(struct cmd_help_result, help, "help"); - -cmdline_parse_inst_t cmd_help = { - .f = cmd_help_parsed, /* function to call */ - .data = NULL, /* 2nd arg of func */ - .help_str = "show help", - .tokens = { /* token list, NULL terminated */ - (void *)&cmd_help_help, - NULL, - }, -}; - -struct cmd_obj_port_init_result { - cmdline_fixed_string_t action; - cmdline_fixed_string_t port_id; - cmdline_fixed_string_t num_queues; - cmdline_fixed_string_t st_queues; - cmdline_fixed_string_t nb_descs; - cmdline_fixed_string_t buff_size; -}; - -static void cmd_obj_port_init_parsed(void *parsed_result, - struct cmdline *cl, - __attribute__((unused)) void *data) -{ - struct cmd_obj_port_init_result *res = parsed_result; - - cmdline_printf(cl, "Port-init Port:%s, num-queues:%s, st-queues: %s\n", - res->port_id, res->num_queues, res->st_queues); - - int port_id = atoi(res->port_id); - if (pinfo[port_id].num_queues) { - cmdline_printf(cl, "Error: port-id:%d already initialized\n" - "To re-initialize please close the port\n", - port_id); - return; - } - - int num_queues = atoi(res->num_queues); - int st_queues = atoi(res->st_queues); - int nb_descs = atoi(res->nb_descs); - int buff_size = atoi(res->buff_size); - - if ((num_queues < 1) || (num_queues > MAX_NUM_QUEUES)) { - cmdline_printf(cl, "Error: please enter valid number of queues," - "entered: %d max allowed: %d\n", - num_queues, MAX_NUM_QUEUES); - return; - } - - if (port_id >= num_ports) { - cmdline_printf(cl, "Error: please enter valid port number: " - "%d\n", port_id); - return; - } - - int result = port_init(port_id, num_queues, - st_queues, nb_descs, buff_size); - - if (result < 0) - cmdline_printf(cl, "Error: Port initialization on " - "port-id:%d failed\n", port_id); - else - cmdline_printf(cl, "Port initialization done " - "successfully on port-id:%d\n", - port_id); -} - -cmdline_parse_token_string_t cmd_obj_action_port_init = - TOKEN_STRING_INITIALIZER(struct cmd_obj_port_init_result, action, - "port_init"); -cmdline_parse_token_string_t cmd_obj_port_init_port_id = - TOKEN_STRING_INITIALIZER(struct cmd_obj_port_init_result, port_id, - NULL); -cmdline_parse_token_string_t cmd_obj_port_init_num_queues = - TOKEN_STRING_INITIALIZER(struct cmd_obj_port_init_result, num_queues, - NULL); -cmdline_parse_token_string_t cmd_obj_port_init_st_queues = - TOKEN_STRING_INITIALIZER(struct cmd_obj_port_init_result, st_queues, - NULL); -cmdline_parse_token_string_t cmd_obj_port_init_nb_descs = - TOKEN_STRING_INITIALIZER(struct cmd_obj_port_init_result, nb_descs, - NULL); -cmdline_parse_token_string_t cmd_obj_port_init_buff_size = - TOKEN_STRING_INITIALIZER(struct cmd_obj_port_init_result, buff_size, - NULL); - -cmdline_parse_inst_t cmd_obj_port_init = { - .f = cmd_obj_port_init_parsed, /* function to call */ - .data = NULL, /* 2nd arg of func */ - .help_str = "port_init port-id num-queues st-queues " - "queue-ring-size buffer-size", - .tokens = { /* token list, NULL terminated */ - (void *)&cmd_obj_action_port_init, - (void *)&cmd_obj_port_init_port_id, - (void *)&cmd_obj_port_init_num_queues, - (void *)&cmd_obj_port_init_st_queues, - (void *)&cmd_obj_port_init_nb_descs, - (void *)&cmd_obj_port_init_buff_size, - NULL, - }, -}; - -/* Command port-close */ -struct cmd_obj_port_close_result { - cmdline_fixed_string_t action; - cmdline_fixed_string_t port_id; -}; - -static void cmd_obj_port_close_parsed(void *parsed_result, - struct cmdline *cl, - __attribute__((unused)) void *data) -{ - struct cmd_obj_port_close_result *res = parsed_result; - - cmdline_printf(cl, "Port-close on Port-id:%s\n", res->port_id); - - int port_id = atoi(res->port_id); - if (pinfo[port_id].num_queues == 0) { - cmdline_printf(cl, "Error: port-id:%d already closed\n", - port_id); - return; - } - - if (port_id >= num_ports) { - cmdline_printf(cl, "Error: please enter valid port " - "number: %d\n", port_id); - return; - } - - port_close(port_id); - pinfo[port_id].num_queues = 0; - cmdline_printf(cl, "Port-id:%d closed successfully\n", port_id); -} - -cmdline_parse_token_string_t cmd_obj_action_port_close = - TOKEN_STRING_INITIALIZER(struct cmd_obj_port_close_result, action, - "port_close"); -cmdline_parse_token_string_t cmd_obj_port_close_port_id = - TOKEN_STRING_INITIALIZER(struct cmd_obj_port_close_result, port_id, - NULL); - -cmdline_parse_inst_t cmd_obj_port_close = { - .f = cmd_obj_port_close_parsed, /* function to call */ - .data = NULL, /* 2nd arg of func */ - .help_str = "port_close port-id ", - .tokens = { /* token list, NULL terminated */ - (void *)&cmd_obj_action_port_close, - (void *)&cmd_obj_port_close_port_id, - NULL, - }, - -}; - -/* Command port-reset */ -struct cmd_obj_port_reset_result { - cmdline_fixed_string_t action; - cmdline_fixed_string_t port_id; - cmdline_fixed_string_t num_queues; - cmdline_fixed_string_t st_queues; - cmdline_fixed_string_t nb_descs; - cmdline_fixed_string_t buff_size; -}; - -static void cmd_obj_port_reset_parsed(void *parsed_result, - struct cmdline *cl, - __attribute__((unused)) void *data) -{ - struct cmd_obj_port_reset_result *res = parsed_result; - - cmdline_printf(cl, "Port-reset Port:%s, num-queues:%s, st-queues: %s\n", - res->port_id, res->num_queues, res->st_queues); - - int port_id = atoi(res->port_id); - int num_queues = atoi(res->num_queues); - int st_queues = atoi(res->st_queues); - int nb_descs = atoi(res->nb_descs); - int buff_size = atoi(res->buff_size); - - if ((num_queues < 1) || (num_queues > MAX_NUM_QUEUES)) { - cmdline_printf(cl, "Error: please enter valid number of queues," - "entered: %d max allowed: %d\n", - num_queues, MAX_NUM_QUEUES); - return; - } - - if (port_id >= num_ports) { - cmdline_printf(cl, "Error: please enter valid port number: " - "%d\n", port_id); - return; - } - - int result = port_reset(port_id, num_queues, - st_queues, nb_descs, buff_size); - - if (result < 0) - cmdline_printf(cl, "Error: Port reset on " - "port-id:%d failed\n", port_id); -} - -cmdline_parse_token_string_t cmd_obj_action_port_reset = - TOKEN_STRING_INITIALIZER(struct cmd_obj_port_reset_result, action, - "port_reset"); -cmdline_parse_token_string_t cmd_obj_port_reset_port_id = - TOKEN_STRING_INITIALIZER(struct cmd_obj_port_reset_result, port_id, - NULL); -cmdline_parse_token_string_t cmd_obj_port_reset_num_queues = - TOKEN_STRING_INITIALIZER(struct cmd_obj_port_reset_result, num_queues, - NULL); -cmdline_parse_token_string_t cmd_obj_port_reset_st_queues = - TOKEN_STRING_INITIALIZER(struct cmd_obj_port_reset_result, st_queues, - NULL); -cmdline_parse_token_string_t cmd_obj_port_reset_nb_descs = - TOKEN_STRING_INITIALIZER(struct cmd_obj_port_reset_result, nb_descs, - NULL); -cmdline_parse_token_string_t cmd_obj_port_reset_buff_size = - TOKEN_STRING_INITIALIZER(struct cmd_obj_port_reset_result, buff_size, - NULL); - -cmdline_parse_inst_t cmd_obj_port_reset = { - .f = cmd_obj_port_reset_parsed, /* function to call */ - .data = NULL, /* 2nd arg of func */ - .help_str = "port_reset port-id num-queues st-queues " - "queue-ring-size buffer-size", - .tokens = { /* token list, NULL terminated */ - (void *)&cmd_obj_action_port_reset, - (void *)&cmd_obj_port_reset_port_id, - (void *)&cmd_obj_port_reset_num_queues, - (void *)&cmd_obj_port_reset_st_queues, - (void *)&cmd_obj_port_reset_nb_descs, - (void *)&cmd_obj_port_reset_buff_size, - NULL, - }, -}; - -/* Command port-remove */ -struct cmd_obj_port_remove_result { - cmdline_fixed_string_t action; - cmdline_fixed_string_t port_id; -}; - -static void cmd_obj_port_remove_parsed(void *parsed_result, - struct cmdline *cl, - __attribute__((unused)) void *data) -{ - struct cmd_obj_port_remove_result *res = parsed_result; - - cmdline_printf(cl, "Port-remove on Port-id:%s\n", res->port_id); - - int port_id = atoi(res->port_id); - if (port_id >= num_ports) { - cmdline_printf(cl, "Error: please enter valid port " - "number: %d\n", port_id); - return; - } - - int result = port_remove(port_id); - pinfo[port_id].num_queues = 0; - - if (result < 0) - cmdline_printf(cl, "Error: Port remove on " - "port-id:%d failed\n", port_id); -} - -cmdline_parse_token_string_t cmd_obj_action_port_remove = - TOKEN_STRING_INITIALIZER(struct cmd_obj_port_remove_result, action, - "port_remove"); -cmdline_parse_token_string_t cmd_obj_port_remove_port_id = - TOKEN_STRING_INITIALIZER(struct cmd_obj_port_remove_result, port_id, - NULL); - -cmdline_parse_inst_t cmd_obj_port_remove = { - .f = cmd_obj_port_remove_parsed, /* function to call */ - .data = NULL, /* 2nd arg of func */ - .help_str = "port_remove port-id ", - .tokens = { /* token list, NULL terminated */ - (void *)&cmd_obj_action_port_remove, - (void *)&cmd_obj_port_remove_port_id, - NULL, - }, -}; - -/* Command Read addr */ -struct cmd_obj_reg_read_result { - cmdline_fixed_string_t action; - cmdline_fixed_string_t port_id; - cmdline_fixed_string_t bar_id; - cmdline_fixed_string_t addr; -}; - -static void cmd_obj_reg_read_parsed(void *parsed_result, - struct cmdline *cl, - __attribute__((unused)) void *data) -{ - struct cmd_obj_reg_read_result *res = parsed_result; - - cmdline_printf(cl, "Read Port:%s, BAR-index:%s, Address:%s\n\n", - res->port_id, res->bar_id, res->addr); - - int addr = strtol(res->addr, NULL, NUMERICAL_BASE_HEXADECIMAL); - - if (addr % ALIGN_TO_WORD_BYTES) { - cmdline_printf(cl, "ERROR: Read address must aligned to " - "a 4-byte boundary.\n\n"); - } else { - int port_id = atoi(res->port_id); - int bar_id = atoi(res->bar_id); - if (port_id >= num_ports) { - cmdline_printf(cl, "Error: port-id:%d not supported\n " - "Please enter valid port-id\n", - port_id); - return; - } - int result = PciRead(bar_id, addr, port_id); - - cmdline_printf(cl, "Read (%d:0x%08x) = 0x%08x\n", - port_id, addr, result); - } -} - -cmdline_parse_token_string_t cmd_obj_action_reg_read = - TOKEN_STRING_INITIALIZER(struct cmd_obj_reg_read_result, action, - "reg_read"); -cmdline_parse_token_string_t cmd_obj_reg_read_port_id = - TOKEN_STRING_INITIALIZER(struct cmd_obj_reg_read_result, port_id, NULL); -cmdline_parse_token_string_t cmd_obj_reg_read_bar_id = - TOKEN_STRING_INITIALIZER(struct cmd_obj_reg_read_result, bar_id, NULL); -cmdline_parse_token_string_t cmd_obj_reg_read_addr = - TOKEN_STRING_INITIALIZER(struct cmd_obj_reg_read_result, addr, NULL); - -cmdline_parse_inst_t cmd_obj_reg_read = { - .f = cmd_obj_reg_read_parsed, /* function to call */ - .data = NULL, /* 2nd arg of func */ - .help_str = "reg_read port-id bar-id address", - .tokens = { /* token list, NULL terminated */ - (void *)&cmd_obj_action_reg_read, - (void *)&cmd_obj_reg_read_port_id, - (void *)&cmd_obj_reg_read_bar_id, - (void *)&cmd_obj_reg_read_addr, - NULL, - }, - -}; - -/* Command Write addr */ -struct cmd_obj_reg_write_result { - cmdline_fixed_string_t action; - cmdline_fixed_string_t port_id; - cmdline_fixed_string_t bar_id; - cmdline_fixed_string_t address; - cmdline_fixed_string_t value; -}; - -static void cmd_obj_reg_write_parsed(void *parsed_result, - struct cmdline *cl, - __attribute__((unused)) void *data) -{ - struct cmd_obj_reg_write_result *res = parsed_result; - - cmdline_printf(cl, "Write Port:%s, Address:%s, Value:%s\n", - res->port_id, res->address, res->value); - - int bar_id = atoi(res->bar_id); - int port_id = atoi(res->port_id); - int addr = strtol(res->address, NULL, NUMERICAL_BASE_HEXADECIMAL); - if (port_id >= num_ports) { - cmdline_printf(cl, "Error: port-id:%d not supported\n " - "Please enter valid port-id\n", port_id); - return; - } - if (addr % ALIGN_TO_WORD_BYTES) { - cmdline_printf(cl, "ERROR: Write address must aligned to a " - "4-byte boundary.\n\n"); - } else{ - int value = strtol(res->value, NULL, NUMERICAL_BASE_HEXADECIMAL); - PciWrite(bar_id, addr, value, port_id); - int result = PciRead(bar_id, addr, port_id); - cmdline_printf(cl, "Read (%d:0x%08x) = 0x%08x\n", port_id, addr, - result); - } -} - -cmdline_parse_token_string_t cmd_obj_action_reg_write = - TOKEN_STRING_INITIALIZER(struct cmd_obj_reg_write_result, action, - "reg_write"); -cmdline_parse_token_string_t cmd_obj_reg_write_port_id = - TOKEN_STRING_INITIALIZER(struct cmd_obj_reg_write_result, port_id, - NULL); -cmdline_parse_token_string_t cmd_obj_reg_write_bar_id = - TOKEN_STRING_INITIALIZER(struct cmd_obj_reg_write_result, bar_id, NULL); -cmdline_parse_token_string_t cmd_obj_reg_write_address = - TOKEN_STRING_INITIALIZER(struct cmd_obj_reg_write_result, address, - NULL); -cmdline_parse_token_string_t cmd_obj_reg_write_value = - TOKEN_STRING_INITIALIZER(struct cmd_obj_reg_write_result, value, NULL); - -cmdline_parse_inst_t cmd_obj_reg_write = { - .f = cmd_obj_reg_write_parsed, /* function to call */ - .data = NULL, /* 2nd arg of func */ - .help_str = "reg_write port-id bar-id address value", - .tokens = { /* token list, NULL terminated */ - (void *)&cmd_obj_action_reg_write, - (void *)&cmd_obj_reg_write_port_id, - (void *)&cmd_obj_reg_write_bar_id, - (void *)&cmd_obj_reg_write_address, - (void *)&cmd_obj_reg_write_value, - NULL, - }, - -}; - -/* Command do-xmit */ -struct cmd_obj_dma_to_device_result { - cmdline_fixed_string_t action; - cmdline_fixed_string_t port_id; - cmdline_fixed_string_t queues; - cmdline_fixed_string_t filename; - cmdline_fixed_string_t dst_addr; - cmdline_fixed_string_t size; - cmdline_fixed_string_t loops; -}; - -static void cmd_obj_dma_to_device_parsed(void *parsed_result, - struct cmdline *cl, - __attribute__((unused)) void *data) -{ - struct cmd_obj_dma_to_device_result *res = parsed_result; - int i, ifd, tot_num_desc, offset, size, r_size = 0, total_size = 0; - int ld_size = 0, loop = 0, ret, j, zbyte = 0, user_bar_idx; - off_t ret_val; - int port_id = 0, num_queues = 0, input_size = 0, num_loops = 0; - uint64_t dst_addr = 0; - uint32_t regval = 0; - unsigned int q_data_size = 0; - char *p = NULL; - - cmdline_printf(cl, "xmit on Port:%s, filename:%s, num-queues:%s\n\n", - res->port_id, res->filename, res->queues); - - ifd = open(res->filename, O_RDWR); - if (ifd < 0) { - cmdline_printf(cl, "Error: Invalid filename: %s\n", - res->filename); - return; - } - - { - port_id = atoi(res->port_id); - if (port_id >= num_ports) { - cmdline_printf(cl, "Error: port-id:%d not supported\n " - "Please enter valid port-id\n", - port_id); - close(ifd); - return; - } - num_queues = atoi(res->queues); - if ((unsigned int)num_queues > pinfo[port_id].num_queues) { - cmdline_printf(cl, "Error: num-queues:%d are more than " - "the configured queues:%d,\n " - "Please enter valid number of queues\n", - num_queues, pinfo[port_id].num_queues); - close(ifd); - return; - } - if (num_queues == 0) { - cmdline_printf(cl, "Error: Please enter valid number " - "of queues\n"); - close(ifd); - return; - } - user_bar_idx = pinfo[port_id].user_bar_idx; - -#if !defined(TANDEM_BOOT_SUPPORTED) - regval = PciRead(user_bar_idx, C2H_CONTROL_REG, port_id); -#endif - - input_size = atoi(res->size); - num_loops = atoi(res->loops); - dst_addr = strtoull(res->dst_addr, &p, 0); - -#if !defined(PERF_BENCHMARK) && !defined(TANDEM_BOOT_SUPPORTED) - if (dst_addr + input_size > BRAM_SIZE) { - cmdline_printf(cl, "Error: (dst_addr %ld + input size " - "%d) shall be less than " - "BRAM_SIZE %d.\n", dst_addr, - input_size, BRAM_SIZE); - close(ifd); - return; - } -#endif - /* For zero-byte transfers, HW expects a - * buffer of length 4kb and with desc->len as 0. - */ - if (input_size == 0) { - if ((unsigned int)num_queues <= - pinfo[port_id].st_queues) { - zbyte = 1; - } else { - cmdline_printf(cl, "Error: Zero-length support " - "is for queues with ST-mode " - "only\n"); - close(ifd); - return; - } - } - - if (input_size % num_queues) { - size = input_size / num_queues; - r_size = input_size % num_queues; - } else - size = input_size / num_queues; - - do { - total_size = input_size; - dst_addr = strtoull(res->dst_addr, &p, 0); - q_data_size = 0; - /* transmit data on the number of Queues configured - * from the input file - */ - for (i = 0, j = 0; i < num_queues; i++, j++) { - dst_addr += q_data_size; - -#ifndef TANDEM_BOOT_SUPPORTED - dst_addr %= BRAM_SIZE; -#endif - - if ((unsigned int)i >= - pinfo[port_id].st_queues) { - ret = - rte_pmd_qdma_set_mm_endpoint_addr( - port_id, - i, - RTE_PMD_QDMA_TX, - dst_addr); - if (ret < 0) { - close(ifd); - return; - } - } - - if (total_size == 0) - q_data_size = pinfo[port_id].buff_size; - else if (total_size == (r_size + size)) { - q_data_size = total_size; - total_size = 0; - } else { - q_data_size = size; - total_size -= size; - } - - if (q_data_size >= pinfo[port_id].buff_size) { - if (q_data_size % - pinfo[port_id].buff_size) { - tot_num_desc = (q_data_size / - pinfo[port_id].buff_size) + 1; - ld_size = q_data_size % - pinfo[port_id].buff_size; - } else - tot_num_desc = (q_data_size / - pinfo[port_id].buff_size); - } else { - tot_num_desc = 1; - ld_size = q_data_size % - pinfo[port_id].buff_size; - } - - if (port_id) - offset = (input_size/num_queues) * j; - else - offset = (input_size/num_queues) * i; - - if ((unsigned int)i < (pinfo[port_id].st_queues) - && !(regval & ST_LOOPBACK_EN)) - ret_val = lseek(ifd, 0, SEEK_SET); - else - ret_val = lseek(ifd, offset, SEEK_SET); - - if (ret_val == (off_t)-1) { - cmdline_printf(cl, "DMA-to-Device: " - "lseek func failed\n"); - close(ifd); - return; - } - - cmdline_printf(cl, "DMA-to-Device: with " - "input-size:%d, ld_size:%d," - "tot_num_desc:%d\n", - input_size, ld_size, - tot_num_desc); - ret = do_xmit(port_id, ifd, i, ld_size, - tot_num_desc, zbyte); - if (ret < 0) { - close(ifd); - return; - } - } - ++loop; - } while (loop < num_loops); - close(ifd); - } - cmdline_printf(cl, "\n######## DMA transfer to device is completed " - "successfully #######\n"); -} - -cmdline_parse_token_string_t cmd_obj_action_dma_to_device = - TOKEN_STRING_INITIALIZER(struct cmd_obj_dma_to_device_result, action, - "dma_to_device"); -cmdline_parse_token_string_t cmd_obj_dma_to_device_port_id = - TOKEN_STRING_INITIALIZER(struct cmd_obj_dma_to_device_result, port_id, - NULL); -cmdline_parse_token_string_t cmd_obj_dma_to_device_queues = - TOKEN_STRING_INITIALIZER(struct cmd_obj_dma_to_device_result, queues, - NULL); -cmdline_parse_token_string_t cmd_obj_dma_to_device_filename = - TOKEN_STRING_INITIALIZER(struct cmd_obj_dma_to_device_result, filename, - NULL); -cmdline_parse_token_string_t cmd_obj_dma_to_device_dst_addr = - TOKEN_STRING_INITIALIZER(struct cmd_obj_dma_to_device_result, dst_addr, - NULL); -cmdline_parse_token_string_t cmd_obj_dma_to_device_size = - TOKEN_STRING_INITIALIZER(struct cmd_obj_dma_to_device_result, size, - NULL); -cmdline_parse_token_string_t cmd_obj_dma_to_device_loops = - TOKEN_STRING_INITIALIZER(struct cmd_obj_dma_to_device_result, loops, - NULL); - -cmdline_parse_inst_t cmd_obj_dma_to_device = { - .f = cmd_obj_dma_to_device_parsed, /* function to call */ - .data = NULL, /* 2nd arg of func */ - .help_str = "dma_to_device port-id num-queues filename dst_addr " - "size loops", - .tokens = { /* token list, NULL terminated */ - (void *)&cmd_obj_action_dma_to_device, - (void *)&cmd_obj_dma_to_device_port_id, - (void *)&cmd_obj_dma_to_device_queues, - (void *)&cmd_obj_dma_to_device_filename, - (void *)&cmd_obj_dma_to_device_dst_addr, - (void *)&cmd_obj_dma_to_device_size, - (void *)&cmd_obj_dma_to_device_loops, - NULL, - }, - -}; - -/* Command do-recv */ -struct cmd_obj_dma_from_device_result { - cmdline_fixed_string_t action; - cmdline_fixed_string_t port_id; - cmdline_fixed_string_t queues; - cmdline_fixed_string_t filename; - cmdline_fixed_string_t src_addr; - cmdline_fixed_string_t size; - cmdline_fixed_string_t loops; -}; - -static void cmd_obj_dma_from_device_parsed(void *parsed_result, - struct cmdline *cl, - __attribute__((unused)) void *data) -{ - struct cmd_obj_dma_from_device_result *res = parsed_result; - int i, ofd, offset, size, total_size, r_size = 0; - int mm_tdesc, mm_ld_size = 0; - int loop = 0, ret, j; - off_t ret_val; - int port_id = 0, num_queues = 0, input_size = 0, num_loops = 0; - uint64_t src_addr = 0; - unsigned int q_data_size = 0; - - cmdline_printf(cl, "recv on Port:%s, filename:%s\n", - res->port_id, res->filename); - - ofd = open(res->filename, O_RDWR | O_CREAT | O_TRUNC | O_SYNC, 0666); - if (ofd < 0) { - cmdline_printf(cl, "Error: Invalid filename: %s\n", - res->filename); - return; - } - - { - port_id = atoi(res->port_id); - if (port_id >= num_ports) { - cmdline_printf(cl, "Error: port-id:%d not supported\n " - "Please enter valid port-id\n", - port_id); - close(ofd); - return; - } - num_queues = atoi(res->queues); - if ((unsigned int)num_queues > pinfo[port_id].num_queues) { - cmdline_printf(cl, "Error: num-queues:%d are more than " - "the configured queues:%d,\n" - "Please enter valid number of queues\n", - num_queues, pinfo[port_id].num_queues); - close(ofd); - return; - } - if (num_queues == 0) { - cmdline_printf(cl, "Error: Please enter valid number " - "of queues\n"); - close(ofd); - return; - } - input_size = atoi(res->size); - num_loops = atoi(res->loops); - src_addr = atoi(res->src_addr); -#ifndef PERF_BENCHMARK - if (src_addr + input_size > BRAM_SIZE) { - cmdline_printf(cl, "Error: (src_addr %ld + input " - "size %d) shall be less than " - "BRAM_SIZE %d.\n", src_addr, - input_size, BRAM_SIZE); - close(ofd); - return; - } -#endif - /* Restrict C2H zerobyte support to ST-mode queues*/ - if (input_size == 0) { - if ((unsigned int)num_queues > - pinfo[port_id].st_queues) { - cmdline_printf(cl, "Error: Zero-length support " - "is for queues with ST-mode only\n"); - close(ofd); - return; - } - } - - if (input_size % num_queues) { - size = input_size / num_queues; - r_size = input_size % num_queues; - } else - size = input_size / num_queues; - - do { - total_size = input_size; - src_addr = atoi(res->src_addr); - q_data_size = 0; - /* Transmit data on the number of Queues configured - * from the input file - */ - for (i = 0, j = 0; i < num_queues; i++, j++) { - src_addr += q_data_size; - src_addr %= BRAM_SIZE; - - if ((unsigned int)i >= - pinfo[port_id].st_queues) { - ret = - rte_pmd_qdma_set_mm_endpoint_addr( - port_id, - i, - RTE_PMD_QDMA_RX, - src_addr); - if (ret < 0) { - close(ofd); - return; - } - } - - if (total_size == (r_size + size)) { - q_data_size = total_size; - total_size = 0; - } else { - q_data_size = size; - total_size -= size; - } - - if (q_data_size >= pinfo[port_id].buff_size) { - if (q_data_size % - pinfo[port_id].buff_size) { - mm_tdesc = (q_data_size / - pinfo[port_id].buff_size) + 1; - - mm_ld_size = q_data_size % - pinfo[port_id].buff_size; - } else - mm_tdesc = (q_data_size / - pinfo[port_id].buff_size); - } else { - mm_tdesc = 1; - mm_ld_size = q_data_size % - pinfo[port_id].buff_size; - } - - if (port_id) - offset = (input_size/num_queues) * j; - else - offset = (input_size/num_queues) * i; - - ret_val = lseek(ofd, offset, SEEK_SET); - if (ret_val == (off_t)-1) { - cmdline_printf(cl, "DMA-to-Device: " - "lseek func failed\n"); - close(ofd); - return; - } - - cmdline_printf(cl, "DMA-from-Device: with " - "input-size:%d, ld_size:%d, " - "tot_num_desc:%d\n", - input_size, mm_ld_size, - mm_tdesc); - - if ((unsigned int)i < - (pinfo[port_id].st_queues)) - ret = do_recv_st(port_id, ofd, i, - q_data_size); - else - ret = do_recv_mm(port_id, ofd, i, - mm_ld_size, - mm_tdesc); - if (ret < 0) { - close(ofd); - return; - } - - ret_val = lseek(ofd, offset, SEEK_END); - if (ret_val == (off_t)-1) { - cmdline_printf(cl, "DMA-to-Device: " - "lseek func failed\n"); - close(ofd); - return; - } - } - ++loop; - } while (loop < num_loops); - close(ofd); - } - cmdline_printf(cl, "\n####### DMA transfer from device is completed " - "successfully #######\n"); -} - -cmdline_parse_token_string_t cmd_obj_action_dma_from_device = - TOKEN_STRING_INITIALIZER(struct cmd_obj_dma_from_device_result, action, - "dma_from_device"); -cmdline_parse_token_string_t cmd_obj_dma_from_device_port_id = - TOKEN_STRING_INITIALIZER(struct cmd_obj_dma_from_device_result, port_id, - NULL); -cmdline_parse_token_string_t cmd_obj_dma_from_device_queues = - TOKEN_STRING_INITIALIZER(struct cmd_obj_dma_from_device_result, queues, - NULL); -cmdline_parse_token_string_t cmd_obj_dma_from_device_filename = - TOKEN_STRING_INITIALIZER(struct cmd_obj_dma_from_device_result, - filename, NULL); -cmdline_parse_token_string_t cmd_obj_dma_from_device_src_addr = - TOKEN_STRING_INITIALIZER(struct cmd_obj_dma_from_device_result, - src_addr, NULL); -cmdline_parse_token_string_t cmd_obj_dma_from_device_size = - TOKEN_STRING_INITIALIZER(struct cmd_obj_dma_from_device_result, size, - NULL); -cmdline_parse_token_string_t cmd_obj_dma_from_device_loops = - TOKEN_STRING_INITIALIZER(struct cmd_obj_dma_from_device_result, loops, - NULL); - -cmdline_parse_inst_t cmd_obj_dma_from_device = { - .f = cmd_obj_dma_from_device_parsed, /* function to call */ - .data = NULL, /* 2nd arg of func */ - .help_str = "dma_from_device port_id num-queues filename " - "src_addr size loops", - .tokens = { /* token list, NULL terminated */ - (void *)&cmd_obj_action_dma_from_device, - (void *)&cmd_obj_dma_from_device_port_id, - (void *)&cmd_obj_dma_from_device_queues, - (void *)&cmd_obj_dma_from_device_filename, - (void *)&cmd_obj_dma_from_device_src_addr, - (void *)&cmd_obj_dma_from_device_size, - (void *)&cmd_obj_dma_from_device_loops, - NULL, - }, - -}; - -struct cmd_obj_reg_dump_result { - cmdline_fixed_string_t action; - cmdline_fixed_string_t port_id; -}; - -static void cmd_obj_reg_dump_parsed(void *parsed_result, - struct cmdline *cl, - __attribute__((unused)) void *data) -{ - struct cmd_obj_reg_dump_result *res = parsed_result; - - - int bar_id; - int port_id = atoi(res->port_id); - - bar_id = pinfo[port_id].config_bar_idx; - if (bar_id < 0) { - cmdline_printf(cl, "Error: fetching QDMA config BAR-id " - "on port-id:%d not supported\n Please enter " - "valid port-id\n", port_id); - return; - } - cmdline_printf(cl, "Register dump on cofig BAR-id:%d with Port-id:%s\n", - bar_id, res->port_id); - if (port_id >= num_ports) { - cmdline_printf(cl, "Error: port-id:%d not supported\n " - "Please enter valid port-id\n", - port_id); - return; - } - rte_pmd_qdma_dbg_regdump(port_id); -} - -cmdline_parse_token_string_t cmd_obj_action_reg_dump = - TOKEN_STRING_INITIALIZER(struct cmd_obj_reg_dump_result, action, - "reg_dump"); -cmdline_parse_token_string_t cmd_obj_reg_dump_port_id = - TOKEN_STRING_INITIALIZER(struct cmd_obj_reg_dump_result, port_id, NULL); - -cmdline_parse_inst_t cmd_obj_reg_dump = { - .f = cmd_obj_reg_dump_parsed, /* function to call */ - .data = NULL, /* 2nd arg of func */ - .help_str = "reg_dump port-id", - .tokens = { /* token list, NULL terminated */ - (void *)&cmd_obj_action_reg_dump, - (void *)&cmd_obj_reg_dump_port_id, - NULL, - }, - -}; - - -/* Command Read Info addr */ -struct cmd_obj_reg_info_read_result { - cmdline_fixed_string_t action; - cmdline_fixed_string_t port_id; - cmdline_fixed_string_t reg_addr; - cmdline_fixed_string_t num_regs; -}; - -static void cmd_obj_reg_info_read_parsed(void *parsed_result, - struct cmdline *cl, - __attribute__((unused)) void *data) -{ - struct cmd_obj_reg_info_read_result *res = parsed_result; - - cmdline_printf(cl, "Read Reg info Port:%s, Address:%s, Num Regs: %s\n\n", - res->port_id, res->reg_addr, res->num_regs); - - int reg_addr = strtol(res->reg_addr, NULL, NUMERICAL_BASE_HEXADECIMAL); - - if (reg_addr % ALIGN_TO_WORD_BYTES) { - cmdline_printf(cl, "ERROR: Read address must aligned to " - "a 4-byte boundary.\n\n"); - } else { - int port_id = atoi(res->port_id); - int num_regs = atoi(res->num_regs); - if (port_id >= num_ports) { - cmdline_printf(cl, "Error: port-id:%d not supported\n " - "Please enter valid port-id\n", - port_id); - return; - } - rte_pmd_qdma_dbg_reg_info_dump(port_id, num_regs,reg_addr); - } -} - -cmdline_parse_token_string_t cmd_obj_action_reg_info_read = - TOKEN_STRING_INITIALIZER(struct cmd_obj_reg_info_read_result, action, - "reg_info_read"); -cmdline_parse_token_string_t cmd_obj_reg_info_read_port_id = - TOKEN_STRING_INITIALIZER(struct cmd_obj_reg_info_read_result, port_id, NULL); -cmdline_parse_token_string_t cmd_obj_reg_info_read_reg_addr = - TOKEN_STRING_INITIALIZER(struct cmd_obj_reg_info_read_result, reg_addr, NULL); -cmdline_parse_token_string_t cmd_obj_reg_info_read_num_regs = - TOKEN_STRING_INITIALIZER(struct cmd_obj_reg_info_read_result, num_regs, NULL); - -cmdline_parse_inst_t cmd_obj_reg_info_read = { - .f = cmd_obj_reg_info_read_parsed, /* function to call */ - .data = NULL, /* 2nd arg of func */ - .help_str = "reg_info_read port-id reg-addr", - .tokens = { /* token list, NULL terminated */ - (void *)&cmd_obj_action_reg_info_read, - (void *)&cmd_obj_reg_info_read_port_id, - (void *)&cmd_obj_reg_info_read_reg_addr, - (void *)&cmd_obj_reg_info_read_num_regs, - NULL, - }, - -}; - - -/*Command queue-context dump*/ - -struct cmd_obj_queue_dump_result { - cmdline_fixed_string_t action; - cmdline_fixed_string_t port_id; - cmdline_fixed_string_t queue_id; -}; - -static void cmd_obj_queue_dump_parsed(void *parsed_result, - struct cmdline *cl, - __attribute__((unused)) void *data) -{ - struct cmd_obj_queue_dump_result *res = parsed_result; - - cmdline_printf(cl, "queue-dump on Port:%s, queue-id:%s\n\n", - res->port_id, res->queue_id); - - { - int port_id = atoi(res->port_id); - int qid = atoi(res->queue_id); - int bar_id = 0x0; - - bar_id = pinfo[port_id].config_bar_idx; - if (bar_id < 0) { - cmdline_printf(cl, "Error: fetching QDMA config BAR-id " - "on port-id:%d not supported\n Please " - "enter valid port-id\n", port_id); - return; - } - if (port_id >= num_ports) { - cmdline_printf(cl, "Error: port-id:%d not supported\n " - "Please enter valid port-id\n", - port_id); - return; - } - if ((unsigned int)qid >= pinfo[port_id].num_queues) { - cmdline_printf(cl, "Error: queue-id:%d is greater than " - "the number of confgiured queues in " - "the port\n Please enter valid " - "queue-id\n", qid); - return; - } - rte_pmd_qdma_dbg_qinfo(port_id, qid); - } -} - -cmdline_parse_token_string_t cmd_obj_action_queue_dump = - TOKEN_STRING_INITIALIZER(struct cmd_obj_queue_dump_result, action, - "queue_dump"); -cmdline_parse_token_string_t cmd_obj_queue_dump_port_id = - TOKEN_STRING_INITIALIZER(struct cmd_obj_queue_dump_result, port_id, - NULL); -cmdline_parse_token_string_t cmd_obj_queue_dump_queue_id = - TOKEN_STRING_INITIALIZER(struct cmd_obj_queue_dump_result, queue_id, - NULL); - -cmdline_parse_inst_t cmd_obj_queue_dump = { - .f = cmd_obj_queue_dump_parsed, /* function to call */ - .data = NULL, /* 2nd arg of func */ - .help_str = "queue_dump port-id queue_id", - .tokens = { /* token list, NULL terminated */ - (void *)&cmd_obj_action_queue_dump, - (void *)&cmd_obj_queue_dump_port_id, - (void *)&cmd_obj_queue_dump_queue_id, - NULL, - }, - -}; - -/*Command queue-stats dump*/ - -struct cmd_obj_qstats_result { - cmdline_fixed_string_t action; - cmdline_fixed_string_t port_id; - cmdline_fixed_string_t queue_id; -}; - -static void cmd_obj_qstats_parsed(void *parsed_result, - struct cmdline *cl, - __attribute__((unused)) void *data) -{ - struct cmd_obj_qstats_result *res = parsed_result; - - cmdline_printf(cl, "queue-dump on Port:%s, queue-id:%s\n\n", - res->port_id, res->queue_id); - - { - int port_id = atoi(res->port_id); - int qid = atoi(res->queue_id); - int bar_id = 0x0; - - bar_id = pinfo[port_id].config_bar_idx; - if (bar_id < 0) { - cmdline_printf(cl, "Error: fetching QDMA config BAR-id " - "on port-id:%d not supported\n Please " - "enter valid port-id\n", port_id); - return; - } - if (port_id >= num_ports) { - cmdline_printf(cl, "Error: port-id:%d not supported\n " - "Please enter valid port-id\n", - port_id); - return; - } - if ((unsigned int)qid >= pinfo[port_id].num_queues) { - cmdline_printf(cl, "Error: queue-id:%d is greater than " - "the number of confgiured queues in " - "the port\n Please enter valid " - "queue-id\n", qid); - return; - } - rte_pmd_qdma_qstats(port_id, qid); - } -} - -cmdline_parse_token_string_t cmd_obj_action_qstats = - TOKEN_STRING_INITIALIZER(struct cmd_obj_qstats_result, action, - "qstats"); -cmdline_parse_token_string_t cmd_obj_qstats_port_id = - TOKEN_STRING_INITIALIZER(struct cmd_obj_qstats_result, port_id, - NULL); -cmdline_parse_token_string_t cmd_obj_qstats_queue_id = - TOKEN_STRING_INITIALIZER(struct cmd_obj_qstats_result, queue_id, - NULL); - -cmdline_parse_inst_t cmd_obj_qstats = { - .f = cmd_obj_qstats_parsed, /* function to call */ - .data = NULL, /* 2nd arg of func */ - .help_str = "qstats port-id queue_id", - .tokens = { /* token list, NULL terminated */ - (void *)&cmd_obj_action_qstats, - (void *)&cmd_obj_qstats_port_id, - (void *)&cmd_obj_qstats_queue_id, - NULL, - }, - -}; - -/*Command queue-stats-cleaar dump*/ - -struct cmd_obj_qstats_clr_result { - cmdline_fixed_string_t action; - cmdline_fixed_string_t port_id; - cmdline_fixed_string_t queue_id; -}; - -static void cmd_obj_qstats_clr_parsed(void *parsed_result, - struct cmdline *cl, - __attribute__((unused)) void *data) -{ - struct cmd_obj_qstats_clr_result *res = parsed_result; - - cmdline_printf(cl, "queue-dump on Port:%s, queue-id:%s\n\n", - res->port_id, res->queue_id); - - { - int port_id = atoi(res->port_id); - int qid = atoi(res->queue_id); - int bar_id = 0x0; - - bar_id = pinfo[port_id].config_bar_idx; - if (bar_id < 0) { - cmdline_printf(cl, "Error: fetching QDMA config BAR-id " - "on port-id:%d not supported\n Please " - "enter valid port-id\n", port_id); - return; - } - if (port_id >= num_ports) { - cmdline_printf(cl, "Error: port-id:%d not supported\n " - "Please enter valid port-id\n", - port_id); - return; - } - if ((unsigned int)qid >= pinfo[port_id].num_queues) { - cmdline_printf(cl, "Error: queue-id:%d is greater than " - "the number of confgiured queues in " - "the port\n Please enter valid " - "queue-id\n", qid); - return; - } - rte_pmd_qdma_qstats_clear(port_id, qid); - } -} - -cmdline_parse_token_string_t cmd_obj_action_qstats_clr = - TOKEN_STRING_INITIALIZER(struct cmd_obj_qstats_clr_result, action, - "qstats_clr"); -cmdline_parse_token_string_t cmd_obj_qstats_clr_port_id = - TOKEN_STRING_INITIALIZER(struct cmd_obj_qstats_clr_result, port_id, - NULL); -cmdline_parse_token_string_t cmd_obj_qstats_clr_queue_id = - TOKEN_STRING_INITIALIZER(struct cmd_obj_qstats_clr_result, queue_id, - NULL); - -cmdline_parse_inst_t cmd_obj_qstats_clr = { - .f = cmd_obj_qstats_clr_parsed, /* function to call */ - .data = NULL, /* 2nd arg of func */ - .help_str = "qstats_clr port-id queue_id", - .tokens = { /* token list, NULL terminated */ - (void *)&cmd_obj_action_qstats_clr, - (void *)&cmd_obj_qstats_clr_port_id, - (void *)&cmd_obj_qstats_clr_queue_id, - NULL, - }, - -}; - -/* Command descriptor dump */ - -struct cmd_obj_desc_dump_result { - cmdline_fixed_string_t action; - cmdline_fixed_string_t port_id; - cmdline_fixed_string_t queue_id; -}; - -static void cmd_obj_desc_dump_parsed(void *parsed_result, - struct cmdline *cl, - __attribute__((unused)) void *data) -{ - struct cmd_obj_desc_dump_result *res = parsed_result; - int start; - int end; - - cmdline_printf(cl, "Descriptor-dump on Port:%s, queue-id:%s\n\n", - res->port_id, res->queue_id); - { - int port_id = atoi(res->port_id); - int qid = atoi(res->queue_id); - if (port_id >= num_ports) { - cmdline_printf(cl, "Error: port-id:%d not supported\n" - "Please enter valid port-id\n", - port_id); - return; - } - if ((unsigned int)qid >= pinfo[port_id].num_queues) { - cmdline_printf(cl, "Error: queue-id:%d is greater than " - "the number of confgiured queues in " - "the port\n Please enter valid " - "queue-id\n", qid); - return; - } - - start = 0; - end = pinfo[port_id].nb_descs - 1; - rte_pmd_qdma_dbg_qdesc(port_id, qid, start, - end, RTE_PMD_QDMA_XDEBUG_DESC_C2H); - - rte_pmd_qdma_dbg_qdesc(port_id, qid, start, - end, RTE_PMD_QDMA_XDEBUG_DESC_H2C); - - if ((unsigned int)qid < pinfo[port_id].st_queues) { - rte_pmd_qdma_dbg_qdesc(port_id, qid, start, - end, RTE_PMD_QDMA_XDEBUG_DESC_CMPT); - } - } -} - -cmdline_parse_token_string_t cmd_obj_action_desc_dump = - TOKEN_STRING_INITIALIZER(struct cmd_obj_desc_dump_result, action, - "desc_dump"); -cmdline_parse_token_string_t cmd_obj_desc_dump_port_id = - TOKEN_STRING_INITIALIZER(struct cmd_obj_desc_dump_result, port_id, - NULL); -cmdline_parse_token_string_t cmd_obj_desc_dump_queue_id = - TOKEN_STRING_INITIALIZER(struct cmd_obj_desc_dump_result, queue_id, - NULL); - -cmdline_parse_inst_t cmd_obj_desc_dump = { - .f = cmd_obj_desc_dump_parsed, /* function to call */ - .data = NULL, /* 2nd arg of func */ - .help_str = "desc_dump port-id queue_id", - .tokens = { /* token list, NULL terminated */ - (void *)&cmd_obj_action_desc_dump, - (void *)&cmd_obj_desc_dump_port_id, - (void *)&cmd_obj_desc_dump_queue_id, - NULL, - }, - -}; - -/*Command load commands from file */ - -struct cmd_obj_load_cmds_result { - cmdline_fixed_string_t action; - cmdline_fixed_string_t filename; -}; - -static void cmd_obj_load_cmds_parsed(void *parsed_result, - struct cmdline *cl, - __attribute__((unused)) void *data) -{ - struct cmd_obj_load_cmds_result *res = parsed_result; - FILE *fp; - char buff[256]; - - cmdline_printf(cl, "load-cmds from file:%s\n\n", res->filename); - fp = fopen((const char *)res->filename, "r"); - if (fp == NULL) { - cmdline_printf(cl, "Error: Invalid filename: %s\n", - res->filename); - return; - } - - - struct rdline *rdl = cmdline_get_rdline(cl); - rdline_reset(rdl); - { - cmdline_in(cl, "\r", 1); - while (fgets(buff, sizeof(buff), fp)) - cmdline_in(cl, buff, strlen(buff)); - - cmdline_in(cl, "\r", 1); - } - fclose(fp); -} - -cmdline_parse_token_string_t cmd_obj_action_load_cmds = - TOKEN_STRING_INITIALIZER(struct cmd_obj_load_cmds_result, action, - "load_cmds"); -cmdline_parse_token_string_t cmd_obj_load_cmds_filename = - TOKEN_STRING_INITIALIZER(struct cmd_obj_load_cmds_result, filename, - NULL); - -cmdline_parse_inst_t cmd_obj_load_cmds = { - .f = cmd_obj_load_cmds_parsed, /* function to call */ - .data = NULL, /* 2nd arg of func */ - .help_str = "load_cmds file-name", - .tokens = { /* token list, NULL terminated */ - (void *)&cmd_obj_action_load_cmds, - (void *)&cmd_obj_load_cmds_filename, - NULL, - }, - -}; - -/* CONTEXT (list of instruction) */ - -cmdline_parse_ctx_t main_ctx[] = { - (cmdline_parse_inst_t *)&cmd_obj_port_init, - (cmdline_parse_inst_t *)&cmd_obj_port_close, - (cmdline_parse_inst_t *)&cmd_obj_port_reset, - (cmdline_parse_inst_t *)&cmd_obj_port_remove, - (cmdline_parse_inst_t *)&cmd_obj_reg_read, - (cmdline_parse_inst_t *)&cmd_obj_reg_write, - (cmdline_parse_inst_t *)&cmd_obj_dma_to_device, - (cmdline_parse_inst_t *)&cmd_obj_dma_from_device, - (cmdline_parse_inst_t *)&cmd_obj_reg_dump, - (cmdline_parse_inst_t *)&cmd_obj_reg_info_read, - (cmdline_parse_inst_t *)&cmd_obj_queue_dump, - (cmdline_parse_inst_t *)&cmd_obj_qstats, - (cmdline_parse_inst_t *)&cmd_obj_qstats_clr, - (cmdline_parse_inst_t *)&cmd_obj_desc_dump, - (cmdline_parse_inst_t *)&cmd_obj_load_cmds, - (cmdline_parse_inst_t *)&cmd_help, - NULL, -}; diff --git a/QDMA/DPDK/examples/qdma_testapp/commands.h b/QDMA/DPDK/examples/qdma_testapp/commands.h deleted file mode 100755 index e598e4b68..000000000 --- a/QDMA/DPDK/examples/qdma_testapp/commands.h +++ /dev/null @@ -1,38 +0,0 @@ -/*- - * BSD LICENSE - * - * Copyright (c) 2010-2023 Intel Corporation. All rights reserved. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * * Neither the name of Intel Corporation nor the names of its - * contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#ifndef _COMMANDS_H_ -#define _COMMANDS_H_ - -extern cmdline_parse_ctx_t main_ctx[]; -#endif /* _COMMANDS_H_ */ diff --git a/QDMA/DPDK/examples/qdma_testapp/parse_obj_list.c b/QDMA/DPDK/examples/qdma_testapp/parse_obj_list.c deleted file mode 100755 index f0f38ed1a..000000000 --- a/QDMA/DPDK/examples/qdma_testapp/parse_obj_list.c +++ /dev/null @@ -1,197 +0,0 @@ -/*- - * BSD LICENSE - * - * Copyright (c) 2017-2022 Xilinx, Inc. All rights reserved. - * Copyright (c) 2022-2023, Advanced Micro Devices, Inc. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * * Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -/*- - * BSD LICENSE - * - * Copyright (c) 2010-2014 Intel Corporation. All rights reserved. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * * Neither the name of Intel Corporation nor the names of its - * contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -/* - * Copyright (c) 2009, Olivier MATZ - * All rights reserved. - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of the University of California, Berkeley nor the - * names of its contributors may be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND ANY - * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE REGENTS AND CONTRIBUTORS BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include -#include -#include -#include -#include -#include -#include - -#include -#include - -#include - -#include "parse_obj_list.h" - -/* This file is an example of extension of libcmdline. It provides an - * example of objects stored in a list - */ - -struct cmdline_token_ops token_obj_list_ops = { - .parse = parse_obj_list, - .complete_get_nb = complete_get_nb_obj_list, - .complete_get_elt = complete_get_elt_obj_list, - .get_help = get_help_obj_list, -}; - -int -parse_obj_list(cmdline_parse_token_hdr_t *tk, const char *srcbuf, void *res, - unsigned int buf_len) -{ - struct token_obj_list *tk2 = (struct token_obj_list *)tk; - struct token_obj_list_data *tkd = &tk2->obj_list_data; - struct object *obj = NULL; - unsigned int token_len = 0; - - if (*srcbuf == 0) - return -1; - - while (!cmdline_isendoftoken(srcbuf[token_len])) - token_len++; - - SLIST_FOREACH(obj, tkd->list, next) { - if (token_len != strnlen(obj->name, OBJ_NAME_LEN_MAX)) - continue; - if (strncmp(srcbuf, obj->name, token_len)) - continue; - break; - } - if (!obj) /* not found */ - return -1; - - /* store the address of object in structure */ - if (res) - *(struct object **)res = obj; - - return token_len; -} - -int complete_get_nb_obj_list(cmdline_parse_token_hdr_t *tk) -{ - struct token_obj_list *tk2 = (struct token_obj_list *)tk; - struct token_obj_list_data *tkd = &tk2->obj_list_data; - struct object *obj = NULL; - int ret = 0; - - SLIST_FOREACH(obj, tkd->list, next) { - ret++; - } - return ret; -} - -int complete_get_elt_obj_list(cmdline_parse_token_hdr_t *tk, - int idx, char *dstbuf, unsigned int size) -{ - struct token_obj_list *tk2 = (struct token_obj_list *)tk; - struct token_obj_list_data *tkd = &tk2->obj_list_data; - struct object *obj = NULL; - int i = 0; - unsigned int len; - - SLIST_FOREACH(obj, tkd->list, next) { - if (i++ == idx) - break; - } - if (!obj) - return -1; - - len = strnlen(obj->name, OBJ_NAME_LEN_MAX); - if ((len + 1) > size) - return -1; - - if (dstbuf) - snprintf(dstbuf, size, "%s", obj->name); - - return 0; -} - - -int get_help_obj_list(__attribute__((unused)) cmdline_parse_token_hdr_t *tk, - char *dstbuf, unsigned int size) -{ - snprintf(dstbuf, size, "Obj-List"); - return 0; -} diff --git a/QDMA/DPDK/examples/qdma_testapp/parse_obj_list.h b/QDMA/DPDK/examples/qdma_testapp/parse_obj_list.h deleted file mode 100755 index e35e9ded8..000000000 --- a/QDMA/DPDK/examples/qdma_testapp/parse_obj_list.h +++ /dev/null @@ -1,147 +0,0 @@ -/*- - * BSD LICENSE - * - * Copyright (c) 2017-2022 Xilinx, Inc. All rights reserved. - * Copyright (c) 2022-2023, Advanced Micro Devices, Inc. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * * Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -/*- - * BSD LICENSE - * - * Copyright (c) 2010-2014 Intel Corporation. All rights reserved. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * * Neither the name of Intel Corporation nor the names of its - * contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -/* - * Copyright (c) 2009, Olivier MATZ - * All rights reserved. - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of the University of California, Berkeley nor the - * names of its contributors may be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND ANY - * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE REGENTS AND CONTRIBUTORS BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#ifndef _PARSE_OBJ_LIST_H_ -#define _PARSE_OBJ_LIST_H_ - -/* This file is an example of extension of libcmdline. It provides an - * example of objects stored in a list. - */ - -#include -#include - -#define OBJ_NAME_LEN_MAX 64 - -struct object { - SLIST_ENTRY(object) next; - char name[OBJ_NAME_LEN_MAX]; - cmdline_ipaddr_t ip; -}; - -/* define struct object_list */ -SLIST_HEAD(object_list, object); - -/* data is a pointer to a list */ -struct token_obj_list_data { - struct object_list *list; -}; - -struct token_obj_list { - struct cmdline_token_hdr hdr; - struct token_obj_list_data obj_list_data; -}; -typedef struct token_obj_list parse_token_obj_list_t; - -extern struct cmdline_token_ops token_obj_list_ops; - -int parse_obj_list(cmdline_parse_token_hdr_t *tk, const char *srcbuf, - void *res, unsigned int buf_len); -int complete_get_nb_obj_list(cmdline_parse_token_hdr_t *tk); -int complete_get_elt_obj_list(cmdline_parse_token_hdr_t *tk, int idx, - char *dstbuf, unsigned int size); -int get_help_obj_list(cmdline_parse_token_hdr_t *tk, char *dstbuf, - unsigned int size); - -#define TOKEN_OBJ_LIST_INITIALIZER(structure, field, obj_list_ptr) \ -{ \ - .hdr = { \ - .ops = &token_obj_list_ops, \ - .offset = offsetof(structure, field), \ - }, \ - .obj_list_data = { \ - .list = obj_list_ptr, \ - }, \ -} - -#endif /* _PARSE_OBJ_LIST_H_ */ diff --git a/QDMA/DPDK/examples/qdma_testapp/pcierw.c b/QDMA/DPDK/examples/qdma_testapp/pcierw.c deleted file mode 100755 index ed6830362..000000000 --- a/QDMA/DPDK/examples/qdma_testapp/pcierw.c +++ /dev/null @@ -1,56 +0,0 @@ -/*- - * BSD LICENSE - * - * Copyright (c) 2017-2022 Xilinx, Inc. All rights reserved. - * Copyright (c) 2022-2023, Advanced Micro Devices, Inc. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * * Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include -#include -#include -#include -#include -#include -#include -#include "../../drivers/net/qdma/rte_pmd_qdma.h" - - -#include "pcierw.h" - -unsigned int PciRead(unsigned int bar, unsigned int offset, int port_id) -{ - return rte_pmd_qdma_compat_pci_read_reg(port_id, bar, offset); -} - - -void PciWrite(unsigned int bar, unsigned int offset, unsigned int reg_val, - int port_id) -{ - rte_pmd_qdma_compat_pci_write_reg(port_id, bar, offset, reg_val); -} diff --git a/QDMA/DPDK/examples/qdma_testapp/pcierw.h b/QDMA/DPDK/examples/qdma_testapp/pcierw.h deleted file mode 100755 index e88f91cd7..000000000 --- a/QDMA/DPDK/examples/qdma_testapp/pcierw.h +++ /dev/null @@ -1,43 +0,0 @@ -/*- - * BSD LICENSE - * - * Copyright (c) 2017-2022 Xilinx, Inc. All rights reserved. - * Copyright (c) 2022-2023, Advanced Micro Devices, Inc. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * * Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#ifndef __PCIERW_H__ -#define __PCIERW_H__ - -unsigned int PciRead(unsigned int bar, unsigned int offset, int port_id); -void PciWrite(unsigned int bar, unsigned int offset, unsigned int reg_val, - int port_id); -void qdma_pci_write_reg(struct rte_eth_dev *dev, uint32_t bar, uint32_t reg, - uint32_t val); -uint32_t qdma_pci_read_reg(struct rte_eth_dev *dev, uint32_t bar, uint32_t reg); -#endif diff --git a/QDMA/DPDK/examples/qdma_testapp/qdma_regs.h b/QDMA/DPDK/examples/qdma_testapp/qdma_regs.h deleted file mode 100755 index aaf7022c5..000000000 --- a/QDMA/DPDK/examples/qdma_testapp/qdma_regs.h +++ /dev/null @@ -1,231 +0,0 @@ -/*- - * BSD LICENSE - * - * Copyright (c) 2017-2022 Xilinx, Inc. All rights reserved. - * Copyright (c) 2022-2023, Advanced Micro Devices, Inc. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * * Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -/** Target definations **/ -#define QDMA_TRQ_SEL_GLBL 0x00000200 -#define QDMA_TRQ_SEL_FMAP 0x00000400 -#define QDMA_TRQ_SEL_IND 0x00000800 -#define QDMA_TRQ_SEL_C2H 0x00000A00 -#define QDMA_TRQ_SEL_H2H 0x00000E00 -#define QDMA_TRQ_SEL_C2H_MM0 0x00001000 -#define QDMA_TRQ_SEL_H2C_MM0 0x00001200 -#define QDMA_TRQ_SEL_QUEUE_PF 0x00006400 - -#define QDMA_CONFIG_BLOCK_ID 0x1fd00000UL -/** Global registers **/ -#define QDMA_GLBL_RING_SZ 0x04 -#define QDMA_GLBL_SCRATCH 0x44 -#define QDMA_GLBL_WB_ACC 0x50 -#define QDMA_RING_SZ_MSK 0x0000ffff -#define QDMA_WB_ACC_MSK 0x00000007 - -/** Fmap registers **/ -#define QID_BASE_MSK (0x000007ff) -#define QID_MAX_MSK (0x003ff800) -#define QID_MAX_SHIFT_B (11) - -/** Queue Indirect programming commands **/ - -#define QDMA_IND_Q_PRG_OFF (0x4) - -#define QDMA_CNTXT_CMD_RD (2) - -#define QDMA_CNTXT_SEL_DESC_SW_C2H (0) -#define QDMA_CNTXT_SEL_DESC_SW_H2C (1) -#define QDMA_CNTXT_SEL_DESC_HW_C2H (2) -#define QDMA_CNTXT_SEL_DESC_HW_H2C (3) -#define QDMA_CNTXT_SEL_DESC_CMPT (6) -#define QDMA_CNTXT_SEL_PFTCH (7) - -#define QID_SHIFT_B (7) -#define OP_CODE_SHIFT_B (5) -#define CTXT_SEL_SHIFT_B (1) -#define BUSY_BIT_MSK (1) - -#define WB_EN_SHIFT_B (20) -#define MM_CHAN_SHIFT_B (19) -#define MM_DESC_SZ_SHIFT_B (17) -#define ST_H2C_DESC_SZ_SHIFT_B (16) -#define DESC_RING_SZ_SHIFT_B (12) -#define ST_H2C_DESC_SZ_SHIFT_B (16) -#define MM_DESC_SZ_WB_SHIFT_B (29) -#define C2H_WB_CTXT_V_SHIFT_B (24) - -/** C2H target registers **/ -#define QDMA_C2H_CNT_TH_BASE 0x40 -#define QDMA_C2H_BUF_SZ_BASE 0xB0 - -/** PF Queue index registers */ -#define QDMA_H2C_PIDX_Q_OFF (0x04) -#define QDMA_C2H_PIDX_Q_OFF (0x08) -#define QDMA_SEL_CMPT_CIDX_Q_OFF (0x0c) - - -/** QDMA Target registers **/ -#define QDMA_C2H_MM0_CONTROL 0x00000004 -#define QDMA_H2C_MM0_CONTROL 0x00000004 -#define QDMA_MM_CTRL_START (1 << 0) - -/** QDMA Descriptor definations **/ -#define QDMA_DESC_SOP 0x1 -#define QDMA_DESC_EOP 0x1 -#define QDMA_DESC_VALID 0x1 - - -/** Queue Indirect programming registers **/ -struct __attribute__ ((packed)) q_ind_prg -{ - uint32_t ctxt_data[8]; - uint32_t ctxt_mask[8]; - uint32_t ctxt_cmd; -}; - -union __attribute__ ((packed)) h2c_c2h_ctxt -{ - struct __attribute__ ((packed)) ctxt_data - { - uint32_t data[5]; - } c_data; - struct __attribute__ ((packed)) ctxt_fields - { - uint16_t pidx; - uint16_t irq_ack:1; - uint16_t fnc_id:8; - uint16_t rsv0:7; - uint16_t qen:1; - uint16_t fcrd_en:1; - uint16_t wbi_chk:1; - uint16_t wbi_acc_en:1; - uint16_t at:1; - uint16_t fetch_max:3; - uint16_t rsv1:4; - uint16_t rng_sz:4; - uint16_t dsc_sz:2; - uint16_t byp:1; - uint16_t mm_chn:1; - uint16_t wbk_en:1; - uint16_t irq_en:1; - uint16_t port_id:3; - uint16_t irq_no_last:1; - uint16_t err:2; - uint16_t err_wb_sent:1; - uint16_t irq_req:1; - uint16_t mrkr_dis:1; - uint16_t is_mm:1; - uint64_t dsc_base; - uint16_t int_vec:11; - uint16_t int_aggr:1; - } c_fields; -}; - -union __attribute__ ((packed)) c2h_cmpt_ctxt -{ - struct __attribute__ ((packed)) c2h_cmpt_data - { - uint32_t data[5]; - } c_data; - struct __attribute__ ((packed)) c2h_cmpt_fields - { - uint32_t en_stat_desc:1; - uint32_t en_int:1; - uint32_t trig_mode:3; - uint32_t fnc_id:12; - uint32_t count_idx:4; - uint32_t timer_idx:4; - uint32_t int_st:2; - uint32_t color:1; - uint32_t size:4; - uint32_t cmpt_dsc_base_l; - uint32_t cmpt_dsc_base_h:26; - uint32_t desc_sz:2; - uint32_t pidx:16; - uint32_t cidx:16; - uint32_t valid:1; - uint32_t err:2; - uint32_t usr_trig_pend:1; - uint32_t timer_run:1; - uint32_t full_upd:1; - uint32_t ovf_chk_dis:1; - uint32_t at:1; - } c_fields; -}; - -union __attribute__ ((packed)) h2c_c2h_hw_ctxt -{ - struct __attribute__ ((packed)) hw_ctxt_data - { - uint32_t data[2]; - } c_data; - struct __attribute__ ((packed)) hw_ctxt_fields - { - uint32_t cidx:16; - uint32_t crd_use:16; - uint32_t rsvd0:8; - uint32_t pnd:1; - uint32_t idl_stp_b:1; - uint32_t event_pend:1; - uint32_t fetch_pend:4; - uint32_t rsvd1:1; - } c_fields; -}; - -union __attribute__ ((packed)) prefetch_ctxt -{ - struct __attribute__ ((packed)) pref_ctxt_data - { - uint32_t data[2]; - } c_data; - - struct __attribute__ ((packed)) pref_ctxt_fields - { - uint8_t bypass:1; - uint8_t buf_sz_idx:4; - uint8_t port_id:3; - uint32_t rsvd:18; - uint8_t err:1; - uint8_t pfch_en:1; - uint8_t pfch:1; - uint16_t sw_crdt:16; - uint8_t valid:1; - } c_fields; -}; - -#define PIDX_MSK (0) -#define Q_STATUS_MSK (0) -#define Q_STATUS_EN_MSK (3) -#define Q_STATUS_RST_MSK (1) -#define WBI_CHK_MSK (6) -#define WBI_ACC_EN_MSK (7) -#define FUNC_ID_MSK (8) -#define RING_SZ_MSK (16) -#define DESC_SZ_MSK (16) diff --git a/QDMA/DPDK/examples/qdma_testapp/testapp.c b/QDMA/DPDK/examples/qdma_testapp/testapp.c deleted file mode 100755 index e8d7703eb..000000000 --- a/QDMA/DPDK/examples/qdma_testapp/testapp.c +++ /dev/null @@ -1,1118 +0,0 @@ -/*- - * BSD LICENSE - * - * Copyright (c) 2017-2022 Xilinx, Inc. All rights reserved. - * Copyright (c) 2022-2023, Advanced Micro Devices, Inc. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * * Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include -#include /**> memset */ -#include -#include -#include /**> rte_eal_init */ -#include /**> for rte_panic */ -#include /**> rte_eth_rx_burst */ -#include /**> rte_errno global var */ -#include /**> rte_memzone_dump */ -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include /** For SLEEP **/ -#include -#include -#include -#include - -#include "pcierw.h" -#include "commands.h" -#include "qdma_regs.h" -#include "testapp.h" -#include "../../drivers/net/qdma/rte_pmd_qdma.h" - -#define RTE_LIBRTE_QDMA_PMD 1 - -int num_ports; -char *filename; - -struct port_info pinfo[QDMA_MAX_PORTS]; - -int do_recv_mm(int port_id, int fd, int queueid, int ld_size, int tot_num_desc) -{ - struct rte_mbuf *pkts[NUM_RX_PKTS] = { NULL }; - int nb_rx = 0, i = 0, ret = 0, num_pkts; - int tdesc; -#ifdef PERF_BENCHMARK - uint64_t prev_tsc, cur_tsc, diff_tsc; -#endif - - if (tot_num_desc == 0) { - printf("Error: tot_num_desc : invalid value\n"); - return -1; - } - - rte_spinlock_lock(&pinfo[port_id].port_update_lock); - - if (rte_pmd_qdma_get_device(port_id) == NULL) { - printf("Port id %d already removed. " - "Relaunch application to use the port again\n", - port_id); - rte_spinlock_unlock(&pinfo[port_id].port_update_lock); - return -1; - } - - printf("recv start num-desc: %d, with data-len: %u, " - "last-desc-size:%d\n", - tot_num_desc, pinfo[port_id].buff_size, ld_size); - tdesc = tot_num_desc; - if (ld_size) - tdesc--; - - while (tdesc) { - if (tdesc > NUM_RX_PKTS) - num_pkts = NUM_RX_PKTS; - else - num_pkts = tdesc; -#ifdef PERF_BENCHMARK - prev_tsc = rte_rdtsc_precise(); -#endif - /* try to receive RX_BURST_SZ packets */ - nb_rx = rte_eth_rx_burst(port_id, queueid, pkts, num_pkts); - -#ifdef PERF_BENCHMARK - cur_tsc = rte_rdtsc_precise(); - diff_tsc = cur_tsc - prev_tsc; -#endif - - if (nb_rx == 0) { - printf("Error: dma_from_device failed to " - "receive packets\n"); - rte_spinlock_unlock(&pinfo[port_id].port_update_lock); - return -1; - } -#ifdef PERF_BENCHMARK - /* Calculate average operations processed per second */ - double pkts_per_second = ((double)nb_rx * rte_get_tsc_hz() / - diff_tsc); - - /* Calculate average throughput (Gbps) in bits per second */ - double throughput_gbps = ((pkts_per_second * - pinfo[port_id].buff_size) / 1000000000); - printf("Throughput GBps %lf\n", throughput_gbps); - printf("%16s%16s%16s%16s%16s%16s%16s\n\n", - "Buf Size", "Burst Size", - "pps", "Gbps", "freq", "Cycles", - "Cycles/Buf"); - - printf("%16u%16u%16.4lf%16.4lf%16 " - ""PRIu64"%16"PRIu64"%16"PRIu64"\n", - pinfo[port_id].buff_size, - nb_rx, - pkts_per_second, - throughput_gbps, - rte_get_tsc_hz(), - diff_tsc, - diff_tsc/nb_rx); -#endif - - for (i = 0; i < nb_rx; i++) { - struct rte_mbuf *mb = pkts[i]; - ret = write(fd, rte_pktmbuf_mtod(mb, void*), - pinfo[port_id].buff_size); - rte_pktmbuf_free(mb); -#ifndef PERF_BENCHMARK - printf("recv count: %d, with data-len: %d\n", i, ret); -#endif - } - tdesc = tdesc - nb_rx; - } - if (ld_size) { - struct rte_mbuf *mb; - nb_rx = rte_eth_rx_burst(port_id, queueid, pkts, 1); - if (nb_rx != 0) { - mb = pkts[0]; - ret = write(fd, rte_pktmbuf_mtod(mb, void*), ld_size); - rte_pktmbuf_free(mb); - } - } - fsync(fd); - - rte_spinlock_unlock(&pinfo[port_id].port_update_lock); - ret = 0; - - printf("DMA received number of packets: %d, on queue-id:%d\n", - nb_rx, queueid); - return ret; -} - -int do_recv_st(int port_id, int fd, int queueid, int input_size) -{ - struct rte_mbuf *pkts[NUM_RX_PKTS] = { NULL }; - int nb_rx = 0, ret = 0, tmp = 0, num_pkts, nb_pkts; - int reg_val, loopback_en; - int regval; - int user_bar_idx; - struct rte_mbuf *nxtmb; - int qbase = pinfo[port_id].queue_base, diag; - unsigned int max_completion_size, last_pkt_size = 0, total_rcv_pkts = 0; - unsigned int max_rx_retry, rcv_count = 0, num_pkts_recv = 0; - unsigned int i = 0, only_pkt = 0; - -#ifdef DUMP_MEMPOOL_USAGE_STATS - struct rte_mempool *mp; -#endif //DUMP_MEMPOOL_USAGE_STATS - - rte_spinlock_lock(&pinfo[port_id].port_update_lock); - - if (rte_pmd_qdma_get_device(port_id) == NULL) { - printf("Port id %d already removed. " - "Relaunch application to use the port again\n", - port_id); - rte_spinlock_unlock(&pinfo[port_id].port_update_lock); - return -1; - } - -#ifdef DUMP_MEMPOOL_USAGE_STATS - mp = rte_mempool_lookup(pinfo[port_id].mem_pool); - - /* get the mempool from which to acquire buffers */ - if (mp == NULL) { - printf("Could not find mempool with name %s\n", - pinfo[port_id].mem_pool); - rte_spinlock_unlock(&pinfo[port_id].port_update_lock); - return -1; - } -#endif //DUMP_MEMPOOL_USAGE_STATS - - user_bar_idx = pinfo[port_id].user_bar_idx; - PciWrite(user_bar_idx, C2H_ST_QID_REG, (queueid + qbase), port_id); - - reg_val = PciRead(user_bar_idx, C2H_CONTROL_REG, port_id); - reg_val &= C2H_CONTROL_REG_MASK; - loopback_en = reg_val & ST_LOOPBACK_EN; - - /* As per hardware design a single completion will point to atmost - * 7 descriptors. So If the size of the buffer in descriptor is 4KB , - * then a single completion which corresponds a packet can give you - * atmost 28KB data. - * - * As per this when testing sizes beyond 28KB, one needs to split it - * up in chunks of 28KB, example : to test 56KB data size, set 28KB - * as packet length in AXI Master Lite BAR(user bar) 0x04 register and no of packets as 2 - * in AXI Master Lite BAR(user bar) 0x20 register this would give you completions or - * packets, which needs to be combined as one in application. - */ - - if (!loopback_en) - max_completion_size = pinfo[port_id].buff_size * 7; - else { - /* For loopback case, each packet handles 4KB only, - * so limiting to buffer size. - */ - max_completion_size = pinfo[port_id].buff_size; - } - - /* Calculate number of packets to receive and programming AXI Master Lite bar(user bar) */ - if (input_size == 0) /* zerobyte support uses one descriptor */ - num_pkts = 1; - else if (input_size % max_completion_size != 0) { - num_pkts = input_size / max_completion_size; - last_pkt_size = input_size % max_completion_size; - } else - num_pkts = input_size / max_completion_size; - - if ((num_pkts == 0) && last_pkt_size) { - num_pkts = 1; - only_pkt = 1; - } - - if (!loopback_en) { - PciWrite(user_bar_idx, C2H_PACKET_COUNT_REG, num_pkts, port_id); - - if (num_pkts > 1) - PciWrite(user_bar_idx, C2H_ST_LEN_REG, - max_completion_size, port_id); - else if ((only_pkt == 1) && (last_pkt_size)) - PciWrite(user_bar_idx, C2H_ST_LEN_REG, - last_pkt_size, port_id); - else if (input_size == 0) - PciWrite(user_bar_idx, C2H_ST_LEN_REG, input_size, - port_id); - else if (num_pkts == 1) - PciWrite(user_bar_idx, C2H_ST_LEN_REG, - max_completion_size, port_id); - - /* Start the C2H Engine */ - reg_val |= ST_C2H_START_VAL; - PciWrite(user_bar_idx, C2H_CONTROL_REG, reg_val, - port_id); - regval = PciRead(user_bar_idx, C2H_PACKET_COUNT_REG, port_id); - printf("BAR-%d is the QDMA C2H number of packets:0x%x,\n", - user_bar_idx, regval); - } - - while (num_pkts) { - if (num_pkts > NUM_RX_PKTS) - nb_pkts = NUM_RX_PKTS; - else - nb_pkts = num_pkts; - - max_rx_retry = RX_TX_MAX_RETRY; - - if ((only_pkt == 1) && (last_pkt_size)) - last_pkt_size = 0; - - /* Immediate data Enabled*/ - if ((reg_val & ST_C2H_IMMEDIATE_DATA_EN)) { - /* payload received is zero for the immediate data case. - * Therefore, no need to call the rx_burst function - * again in this case and set the num_pkts to nb_rx - * which is always Zero. - */ - diag = rte_pmd_qdma_set_immediate_data_state(port_id, - queueid, 1); - if (diag < 0) { - printf("rte_pmd_qdma_set_immediate_data_state : " - "failed\n"); - rte_spinlock_unlock( - &pinfo[port_id].port_update_lock); - return -1; - } - - nb_rx = rte_eth_rx_burst(port_id, queueid, pkts, - nb_pkts); - num_pkts = num_pkts_recv = nb_rx; - - /* Reset the queue's DUMP_IMMEDIATE_DATA mode */ - diag = rte_pmd_qdma_set_immediate_data_state(port_id, - queueid, 0); - if (diag < 0) { - printf("rte_pmd_qdma_set_immediate_data_state : " - "failed\n"); - rte_spinlock_unlock( - &pinfo[port_id].port_update_lock); - return -1; - } - } else { - /* try to receive RX_BURST_SZ packets */ - - nb_rx = rte_eth_rx_burst(port_id, queueid, pkts, - nb_pkts); - - /* For zero byte packets, do not continue looping */ - if (input_size == 0) - break; - - tmp = nb_rx; - while ((nb_rx < nb_pkts) && max_rx_retry) { - rte_delay_us(1); - nb_pkts -= nb_rx; - nb_rx = rte_eth_rx_burst(port_id, queueid, - &pkts[tmp], - nb_pkts); - tmp += nb_rx; - max_rx_retry--; - } - num_pkts_recv = tmp; - if ((max_rx_retry == 0) && (num_pkts_recv == 0)) { - printf("ERROR: rte_eth_rx_burst failed for " - "port %d queue id %d, Expected pkts = %d " - "Received pkts = %u\n", - port_id, queueid, - nb_pkts, num_pkts_recv); - break; - } - } - -#ifdef DUMP_MEMPOOL_USAGE_STATS - printf("%s(): %d: queue id = %d, mbuf_avail_count = %d, " - "mbuf_in_use_count = %d\n", - __func__, __LINE__, queueid, - rte_mempool_avail_count(mp), - rte_mempool_in_use_count(mp)); -#endif //DUMP_MEMPOOL_USAGE_STATS - for (i = 0; i < num_pkts_recv; i++) { - struct rte_mbuf *mb = pkts[i]; - while (mb != NULL) { - ret += write(fd, rte_pktmbuf_mtod(mb, void*), - rte_pktmbuf_data_len(mb)); - nxtmb = mb->next; - mb = nxtmb; - } - - mb = pkts[i]; - rte_pktmbuf_free(mb); -#ifndef PERF_BENCHMARK - printf("recv count: %u, with data-len: %d\n", - i + rcv_count, ret); -#endif - ret = 0; - } - rcv_count += i; -#ifdef DUMP_MEMPOOL_USAGE_STATS - printf("%s(): %d: queue id = %d, mbuf_avail_count = %d, " - "mbuf_in_use_count = %d, num_pkts_recv = %u\n", - __func__, __LINE__, queueid, - rte_mempool_avail_count(mp), - rte_mempool_in_use_count(mp), num_pkts_recv); -#endif //DUMP_MEMPOOL_USAGE_STATS - num_pkts = num_pkts - num_pkts_recv; - total_rcv_pkts += num_pkts_recv; - if ((num_pkts == 0) && last_pkt_size) { - num_pkts = 1; - if (!loopback_en) { - /* Stop the C2H Engine */ - reg_val = PciRead(user_bar_idx, - C2H_CONTROL_REG, - port_id); - reg_val &= C2H_CONTROL_REG_MASK; - reg_val &= ~(ST_C2H_START_VAL); - PciWrite(user_bar_idx, C2H_CONTROL_REG, reg_val, - port_id); - - /* Update number of packets as 1 and - * packet size as last packet length - */ - PciWrite(user_bar_idx, C2H_PACKET_COUNT_REG, - num_pkts, port_id); - - PciWrite(user_bar_idx, C2H_ST_LEN_REG, - last_pkt_size, port_id); - - /* Start the C2H Engine */ - reg_val = PciRead(user_bar_idx, - C2H_CONTROL_REG, - port_id); - reg_val &= C2H_CONTROL_REG_MASK; - reg_val |= ST_C2H_START_VAL; - PciWrite(user_bar_idx, C2H_CONTROL_REG, reg_val, - port_id); - } - last_pkt_size = 0; - continue; - } - } - /* Stop the C2H Engine */ - if (!loopback_en) { - reg_val = PciRead(user_bar_idx, C2H_CONTROL_REG, port_id); - reg_val &= C2H_CONTROL_REG_MASK; - reg_val &= ~(ST_C2H_START_VAL); - PciWrite(user_bar_idx, C2H_CONTROL_REG, reg_val, - port_id); - } - printf("DMA received number of packets: %u, on queue-id:%d\n", - total_rcv_pkts, queueid); - fsync(fd); - rte_spinlock_unlock(&pinfo[port_id].port_update_lock); - return 0; -} - -int do_xmit(int port_id, int fd, int queueid, int ld_size, int tot_num_desc, - int zbyte) -{ - struct rte_mempool *mp; - struct rte_mbuf *mb[NUM_TX_PKTS] = { NULL }; - int ret = 0, nb_tx, i = 0, tdesc, num_pkts = 0, total_tx = 0, reg_val; - int tmp = 0, user_bar_idx; - int qbase = pinfo[port_id].queue_base; - uint32_t max_tx_retry; - -#ifdef PERF_BENCHMARK - uint64_t prev_tsc, cur_tsc, diff_tsc; -#endif - - rte_spinlock_lock(&pinfo[port_id].port_update_lock); - - if (rte_pmd_qdma_get_device(port_id) == NULL) { - printf("Port id %d already removed. " - "Relaunch application to use the port again\n", - port_id); - rte_spinlock_unlock(&pinfo[port_id].port_update_lock); - return -1; - } - - mp = rte_mempool_lookup(pinfo[port_id].mem_pool); - /* get the mempool from which to acquire buffers */ - if (mp == NULL) { - printf("Could not find mempool with name %s\n", - pinfo[port_id].mem_pool); - rte_spinlock_unlock(&pinfo[port_id].port_update_lock); - return -1; - } - - tdesc = tot_num_desc; - user_bar_idx = pinfo[port_id].user_bar_idx; - - if (ld_size) - tdesc--; - - while (tdesc) { - if (tdesc > NUM_TX_PKTS) - num_pkts = NUM_TX_PKTS; - else - num_pkts = tdesc; - - max_tx_retry = RX_TX_MAX_RETRY; -#ifdef DUMP_MEMPOOL_USAGE_STATS - printf("%s(): %d: queue id %d, mbuf_avail_count = %d, " - "mbuf_in_use_count = %d", - __func__, __LINE__, queueid, - rte_mempool_avail_count(mp), - rte_mempool_in_use_count(mp)); -#endif //DUMP_MEMPOOL_USAGE_STATS - for (i = 0; i < num_pkts; i++) { - mb[i] = rte_pktmbuf_alloc(mp); - if (mb[i] == NULL) { - printf(" #####Cannot " - "allocate mbuf packet\n"); - rte_spinlock_unlock( - &pinfo[port_id].port_update_lock); - return -1; - } - - if (!zbyte) - ret = read(fd, rte_pktmbuf_mtod(mb[i], void *), - pinfo[port_id].buff_size); - if (ret < 0) { - printf("Error: Could not the read " - "input-file\n"); - rte_spinlock_unlock( - &pinfo[port_id].port_update_lock); - return -1; - } - mb[i]->nb_segs = 1; - mb[i]->next = NULL; - rte_pktmbuf_data_len(mb[i]) = (uint16_t)ret; - rte_pktmbuf_pkt_len(mb[i]) = (uint16_t)ret; - } - -#ifdef DUMP_MEMPOOL_USAGE_STATS - printf("%s(): %d: queue id %d, mbuf_avail_count = %d, " - "mbuf_in_use_count = %d, num_pkts_tx = %d", - __func__, __LINE__, queueid, - rte_mempool_avail_count(mp), - rte_mempool_in_use_count(mp), num_pkts); -#endif //DUMP_MEMPOOL_USAGE_STATS - - total_tx = num_pkts; - -#ifndef TANDEM_BOOT_SUPPORTED - PciWrite(user_bar_idx, C2H_ST_QID_REG, (queueid + qbase), - port_id); -#endif - /* try to transmit TX_BURST_SZ packets */ - -#ifdef PERF_BENCHMARK - prev_tsc = rte_rdtsc_precise(); -#endif - nb_tx = rte_eth_tx_burst(port_id, queueid, mb, num_pkts); -#ifdef PERF_BENCHMARK - cur_tsc = rte_rdtsc_precise(); - diff_tsc = cur_tsc - prev_tsc; - /* Calculate average operations processed per second */ - double pkts_per_second = ((double)nb_tx * rte_get_tsc_hz() / - diff_tsc); - - /* Calculate average throughput (Gbps) in bits per second */ - double throughput_gbps = ((pkts_per_second * - pinfo[port_id].buff_size) / 1000000000); - printf("Throughput GBps %lf\n", throughput_gbps); - printf("%12s%12s%12s%12s%12s%12s%12s\n\n", - "Buf Size", "Burst Size", - "pps", "Gbps", "freq", "Cycles", - "Cycles/Buf"); - - printf("%12u%12u%12.4lf%12.4lf%12" - ""PRIu64"%12"PRIu64"%12"PRIu64"\n", - pinfo[port_id].buff_size, - nb_tx, - pkts_per_second, - throughput_gbps, - rte_get_tsc_hz(), - diff_tsc, - diff_tsc/nb_tx); -#endif - tmp = nb_tx; - while ((nb_tx < num_pkts) && max_tx_retry) { - printf("Couldn't transmit all the packets: Expected = %d " - "Transmitted = %d.\n" - "Calling rte_eth_tx_burst again\n", - num_pkts, nb_tx); - rte_delay_us(1); - num_pkts -= nb_tx; - nb_tx = rte_eth_tx_burst(port_id, queueid, &mb[tmp], - num_pkts); - tmp += nb_tx; - max_tx_retry--; - } - - if ((max_tx_retry == 0)) { - for (i = tmp; i < total_tx; i++) - rte_pktmbuf_free(mb[i]); - if (tmp == 0) { - printf("ERROR: rte_eth_tx_burst failed " - "for port %d queue %d\n", - port_id, queueid); - break; - } - } - - tdesc = tdesc - tmp; - printf("\nDMA transmitted number of packets: %d, " - "on Queue-id:%d\n", - tmp, queueid); - } - - if (ld_size) { - mb[0] = rte_pktmbuf_alloc(mp); - if (mb[0] == NULL) { - printf(" #####Cannot allocate mbuf " - "packet\n"); - rte_spinlock_unlock(&pinfo[port_id].port_update_lock); - return -1; - } - ret = read(fd, rte_pktmbuf_mtod(mb[0], void *), ld_size); - if (ret < 0) { - printf("Error: Could not read the input-file\n"); - rte_spinlock_unlock(&pinfo[port_id].port_update_lock); - return -1; - } - mb[0]->nb_segs = 1; - mb[0]->next = NULL; - rte_pktmbuf_data_len(mb[0]) = (uint16_t)ret; - rte_pktmbuf_pkt_len(mb[0]) = (uint16_t)ret; - - nb_tx = rte_eth_tx_burst(port_id, queueid, mb, 1); - if (nb_tx == 0) - rte_pktmbuf_free(mb[0]); - } - -#ifndef TANDEM_BOOT_SUPPORTED - reg_val = PciRead(user_bar_idx, C2H_CONTROL_REG, port_id); - reg_val &= C2H_CONTROL_REG_MASK; - if (!(reg_val & ST_LOOPBACK_EN)) { - reg_val = PciRead(user_bar_idx, H2C_STATUS_REG, port_id); - printf("BAR-%d is the QDMA H2C transfer match: 0x%x,\n", - user_bar_idx, reg_val); - - /** TO clear H2C DMA write **/ - PciWrite(user_bar_idx, H2C_CONTROL_REG, 0x1, port_id); - } -#endif - - rte_spinlock_unlock(&pinfo[port_id].port_update_lock); - return 0; -} - -static int dev_reset_callback(uint16_t port_id, - enum rte_eth_event_type type, - void *param __rte_unused, void *ret_param) -{ - int ret = 0; - - RTE_SET_USED(ret_param); - printf("%s is received\n", __func__); - - if (type != RTE_ETH_EVENT_INTR_RESET) { - printf("Error: Invalid event value. " - "Expected = %d, Received = %d\n", - RTE_ETH_EVENT_INTR_RESET, type); - return -ENOMSG; - } - - ret = port_reset(port_id, pinfo[port_id].num_queues, - pinfo[port_id].st_queues, - pinfo[port_id].nb_descs, - pinfo[port_id].buff_size); - if (ret < 0) - printf("Error: Failed to reset port: %d\n", port_id); - - return ret; -} - -static int dev_remove_callback(uint16_t port_id, - enum rte_eth_event_type type, - void *param __rte_unused, void *ret_param) -{ - int ret = 0; - - RTE_SET_USED(ret_param); - printf("%s is received\n", __func__); - - if (type != RTE_ETH_EVENT_INTR_RMV) { - printf("Error: Invalid event value. " - "Expected = %d, Received = %d\n", - RTE_ETH_EVENT_INTR_RMV, type); - return -ENOMSG; - } - - ret = port_remove(port_id); - if (ret < 0) - printf("Error: Failed to remove port: %d\n", port_id); - - return 0; -} - -void port_close(int port_id) -{ - struct rte_mempool *mp; - struct rte_pmd_qdma_dev_attributes dev_attr; - int user_bar_idx; - int reg_val; - int ret = 0; - - if (rte_pmd_qdma_get_device(port_id) == NULL) { - printf("Port id %d already removed. " - "Relaunch application to use the port again\n", - port_id); - return; - } - - user_bar_idx = pinfo[port_id].user_bar_idx; - ret = rte_pmd_qdma_get_device_capabilities(port_id, &dev_attr); - if (ret < 0) { - printf("rte_pmd_qdma_get_device_capabilities failed for port: %d\n", - port_id); - return; - } - - if ((dev_attr.device_type == RTE_PMD_QDMA_DEVICE_SOFT) - && (dev_attr.ip_type == RTE_PMD_EQDMA_SOFT_IP)) { - PciWrite(user_bar_idx, C2H_CONTROL_REG, - C2H_STREAM_MARKER_PKT_GEN_VAL, - port_id); - unsigned int retry = 50; - while (retry) { - usleep(500); - reg_val = PciRead(user_bar_idx, - C2H_STATUS_REG, port_id); - if (reg_val & MARKER_RESPONSE_COMPLETION_BIT) - break; - - printf("Failed to receive c2h marker completion, retry count = %u\n", - (50 - (retry-1))); - retry--; - } - } - - rte_eth_dev_stop(port_id); - - rte_pmd_qdma_dev_close(port_id); - - pinfo[port_id].num_queues = 0; - - mp = rte_mempool_lookup(pinfo[port_id].mem_pool); - - if (mp != NULL) - rte_mempool_free(mp); -} - -int port_reset(int port_id, int num_queues, int st_queues, - int nb_descs, int buff_size) -{ - int ret = 0; - - printf("%s is received\n", __func__); - - if (rte_pmd_qdma_get_device(port_id) == NULL) { - printf("Port id %d already removed. " - "Relaunch application to use the port again\n", - port_id); - return -1; - } - - rte_spinlock_lock(&pinfo[port_id].port_update_lock); - - port_close(port_id); - - ret = rte_eth_dev_reset(port_id); - if (ret < 0) { - printf("Error: Failed to reset device for port: %d\n", port_id); - rte_spinlock_unlock(&pinfo[port_id].port_update_lock); - return -1; - } - - ret = port_init(port_id, num_queues, st_queues, - nb_descs, buff_size); - if (ret < 0) - printf("Error: Failed to initialize port: %d\n", port_id); - - rte_spinlock_unlock(&pinfo[port_id].port_update_lock); - - if (!ret) - printf("Port reset done successfully on port-id: %d\n", - port_id); - - return ret; -} - -int port_remove(int port_id) -{ - int ret = 0; - - printf("%s is received\n", __func__); - - /* Detach the port, it will invoke device remove/uninit */ - printf("Removing a device with port id %d\n", port_id); - if (rte_pmd_qdma_get_device(port_id) == NULL) { - printf("Port id %d already removed\n", port_id); - return 0; - } - - rte_spinlock_lock(&pinfo[port_id].port_update_lock); - - port_close(port_id); - - ret = rte_pmd_qdma_dev_remove(port_id); - if (ret < 0) - printf("Failed to remove device on port_id: %d\n", port_id); - - rte_spinlock_unlock(&pinfo[port_id].port_update_lock); - - if (!ret) - printf("Port remove done successfully on port-id: %d\n", - port_id); - - return ret; -} - -static struct option const long_opts[] = { -{"filename", 1, 0, 0}, -{NULL, 0, 0, 0} -}; - -int parse_cmdline(int argc, char **argv) -{ - int cmd_opt; - int option_index; - char **argvopt; - - argvopt = argv; - while ((cmd_opt = getopt_long(argc, argvopt, "c:n:b:w", long_opts, - &option_index)) != EOF) { - switch (cmd_opt) { - case 'c': - /* eal option */ - break; - case 'n': - /* eal option */ - break; - case 'b': - /* eal option */ - break; - case 'w': - /* eal option */ - break; - case '?': - /* Long eal options */ - break; - case 0: - if (!strncmp(long_opts[option_index].name, - "filename", - sizeof("filename"))) { - - filename = optarg; - } - break; - default: - printf("please pass valid parameters as follows:\n"); - return -1; - } - } - return 0; -} - -int port_init(int port_id, int num_queues, int st_queues, - int nb_descs, int buff_size) -{ - struct rte_mempool *mbuf_pool; - struct rte_eth_conf port_conf; - struct rte_eth_txconf tx_conf; - struct rte_eth_rxconf rx_conf; - int diag, x; - uint32_t queue_base, nb_buff; - - printf("Setting up port :%d.\n", port_id); - - if (rte_pmd_qdma_get_device(port_id) == NULL) { - printf("Port id %d already removed. " - "Relaunch application to use the port again\n", - port_id); - return -1; - } - - snprintf(pinfo[port_id].mem_pool, RTE_MEMPOOL_NAMESIZE, - MBUF_POOL_NAME_PORT, port_id); - - /* Mbuf packet pool */ - nb_buff = ((nb_descs) * num_queues * 2); - - /* NUM_TX_PKTS should be added to every queue as that many descriptors - * can be pending with application after Rx processing but before - * consumed by application or sent to Tx - */ - nb_buff += ((NUM_TX_PKTS) * num_queues); - - /* - * rte_mempool_create_empty() has sanity check to refuse large cache - * size compared to the number of elements. - * CACHE_FLUSHTHRESH_MULTIPLIER (1.5) is defined in a C file, so using a - * constant number 2 instead. - */ - nb_buff = RTE_MAX(nb_buff, MP_CACHE_SZ * 2); - - mbuf_pool = rte_pktmbuf_pool_create(pinfo[port_id].mem_pool, nb_buff, - MP_CACHE_SZ, 0, buff_size + - RTE_PKTMBUF_HEADROOM, - rte_socket_id()); - - if (mbuf_pool == NULL) - rte_exit(EXIT_FAILURE, " Cannot create mbuf pkt-pool\n"); -#ifdef DUMP_MEMPOOL_USAGE_STATS - printf("%s(): %d: mpool = %p, mbuf_avail_count = %d," - " mbuf_in_use_count = %d," - "nb_buff = %u\n", __func__, __LINE__, mbuf_pool, - rte_mempool_avail_count(mbuf_pool), - rte_mempool_in_use_count(mbuf_pool), nb_buff); -#endif //DUMP_MEMPOOL_USAGE_STATS - - /* - * Make sure the port is configured. Zero everything and - * hope for sane defaults - */ - memset(&port_conf, 0x0, sizeof(struct rte_eth_conf)); - memset(&tx_conf, 0x0, sizeof(struct rte_eth_txconf)); - memset(&rx_conf, 0x0, sizeof(struct rte_eth_rxconf)); - diag = rte_pmd_qdma_get_bar_details(port_id, - &(pinfo[port_id].config_bar_idx), - &(pinfo[port_id].user_bar_idx), - &(pinfo[port_id].bypass_bar_idx)); - - if (diag < 0) - rte_exit(EXIT_FAILURE, "rte_pmd_qdma_get_bar_details failed\n"); - - printf("QDMA Config bar idx: %d\n", pinfo[port_id].config_bar_idx); - printf("QDMA AXI Master Lite bar idx: %d\n", pinfo[port_id].user_bar_idx); - printf("QDMA AXI Bridge Master bar idx: %d\n", pinfo[port_id].bypass_bar_idx); - - /* configure the device to use # queues */ - diag = rte_eth_dev_configure(port_id, num_queues, num_queues, - &port_conf); - if (diag < 0) - rte_exit(EXIT_FAILURE, "Cannot configure port %d (err=%d)\n", - port_id, diag); - - diag = rte_pmd_qdma_get_queue_base(port_id, &queue_base); - if (diag < 0) - rte_exit(EXIT_FAILURE, "rte_pmd_qdma_get_queue_base : Querying of " - "QUEUE_BASE failed\n"); - pinfo[port_id].queue_base = queue_base; - pinfo[port_id].num_queues = num_queues; - pinfo[port_id].st_queues = st_queues; - pinfo[port_id].buff_size = buff_size; - pinfo[port_id].nb_descs = nb_descs; - - for (x = 0; x < num_queues; x++) { - if (x < st_queues) { - diag = rte_pmd_qdma_set_queue_mode(port_id, x, - RTE_PMD_QDMA_STREAMING_MODE); - if (diag < 0) - rte_exit(EXIT_FAILURE, "rte_pmd_qdma_set_queue_mode : " - "Passing of QUEUE_MODE " - "failed\n"); - } else { - diag = rte_pmd_qdma_set_queue_mode(port_id, x, - RTE_PMD_QDMA_MEMORY_MAPPED_MODE); - if (diag < 0) - rte_exit(EXIT_FAILURE, "rte_pmd_qdma_set_queue_mode : " - "Passing of QUEUE_MODE " - "failed\n"); - } - - diag = rte_eth_tx_queue_setup(port_id, x, nb_descs, 0, - &tx_conf); - if (diag < 0) - rte_exit(EXIT_FAILURE, "Cannot setup port %d " - "TX Queue id:%d " - "(err=%d)\n", port_id, x, diag); - rx_conf.rx_thresh.wthresh = DEFAULT_RX_WRITEBACK_THRESH; - diag = rte_eth_rx_queue_setup(port_id, x, nb_descs, 0, - &rx_conf, mbuf_pool); - if (diag < 0) - rte_exit(EXIT_FAILURE, "Cannot setup port %d " - "RX Queue 0 (err=%d)\n", port_id, diag); - } - - diag = rte_eth_dev_start(port_id); - if (diag < 0) - rte_exit(EXIT_FAILURE, "Cannot start port %d (err=%d)\n", - port_id, diag); - - return 0; -} - -static inline void do_sanity_checks(void) -{ -#if (!defined(RTE_LIBRTE_QDMA_PMD)) - rte_exit(EXIT_FAILURE, "CONFIG_RTE_LIBRTE_QDMA_PMD must be set " - "to 'Y' in the .config file\n"); -#endif /* RTE_LIBRTE_XDMA_PMD */ - -} - -void load_file_cmds(struct cmdline *cl) -{ - FILE *fp; - char buff[256]; - - cmdline_printf(cl, "load commands from file:%s\n\n", filename); - fp = fopen((const char *)filename, "r"); - if (fp == NULL) { - cmdline_printf(cl, "Error: Invalid filename: %s\n", filename); - return; - } - - struct rdline *rdl = cmdline_get_rdline(cl); - rdline_reset(rdl); - { - cmdline_in(cl, "\r", 1); - while (fgets(buff, sizeof(buff), fp)) - cmdline_in(cl, buff, strlen(buff)); - - cmdline_in(cl, "\r", 1); - } - fclose(fp); -} - -/** XDMA DPDK testapp */ - -int main(int argc, char **argv) -{ - const struct rte_memzone *mz = 0; - struct cmdline *cl; - int port_id = 0; - int ret = 0; - int curr_avail_ports = 0; - - /* Make sure the port is configured. Zero everything and - * hope for same defaults - */ - - printf("QDMA testapp rte eal init...\n"); - - /* Make sure things are initialized ... */ - ret = rte_eal_init(argc, argv); - if (ret < 0) - rte_exit(EXIT_FAILURE, "Error with EAL initialization\n"); - rte_log_set_global_level(RTE_LOG_DEBUG); - - printf("Ethernet Device Count: %d\n", (int)rte_eth_dev_count_avail()); - printf("Logical Core Count: %d\n", rte_lcore_count()); - - num_ports = rte_eth_dev_count_avail(); - if (num_ports < 1) - rte_exit(EXIT_FAILURE, "No Ethernet devices found." - " Try updating the FPGA image.\n"); - - for (port_id = 0; port_id < num_ports; port_id++) - rte_spinlock_init(&pinfo[port_id].port_update_lock); - - ret = rte_eth_dev_callback_register(RTE_ETH_ALL, RTE_ETH_EVENT_INTR_RMV, - dev_remove_callback, NULL); - if (ret < 0) - rte_exit(EXIT_FAILURE, "Failed to register dev_remove_callback\n"); - - ret = rte_eth_dev_callback_register(RTE_ETH_ALL, - RTE_ETH_EVENT_INTR_RESET, - dev_reset_callback, NULL); - if (ret < 0) - rte_exit(EXIT_FAILURE, "Failed to register dev_reset_callback\n"); - -#if 1 - ret = parse_cmdline(argc, argv); - if (ret < 0) - rte_exit(EXIT_FAILURE, "Invalid argument\n"); -#endif - - /* Make sure things are defined ... */ - do_sanity_checks(); - - /* Allocate aligned mezone */ - rte_pmd_qdma_compat_memzone_reserve_aligned(); - - cl = cmdline_stdin_new(main_ctx, "xilinx-app> "); - if (cl == NULL) - rte_panic("Cannot create cmdline instance\n"); - - /* if input commands file exists, then load commands from the file */ - if (filename != NULL) { - load_file_cmds(cl); - rte_delay_ms(100); - } else - cmdline_interact(cl); - - rte_eth_dev_callback_unregister(RTE_ETH_ALL, RTE_ETH_EVENT_INTR_RMV, - dev_remove_callback, NULL); - - rte_eth_dev_callback_unregister(RTE_ETH_ALL, RTE_ETH_EVENT_INTR_RESET, - dev_reset_callback, NULL); - - curr_avail_ports = rte_eth_dev_count_avail(); - if (!curr_avail_ports) - printf("Ports already removed\n"); - else { - for (port_id = num_ports - 1; port_id >= 0; port_id--) { - - if (pinfo[port_id].num_queues) - port_close(port_id); - - printf("Removing a device with port id %d\n", port_id); - if (rte_pmd_qdma_get_device(port_id) == NULL) { - printf("Port id %d already removed\n", port_id); - continue; - } - /* Detach the port, it will invoke - * device remove/uninit - */ - if (rte_pmd_qdma_dev_remove(port_id)) - printf("Failed to detach port '%d'\n", port_id); - } - } - - cmdline_stdin_exit(cl); - - rte_delay_ms(5000); - return 0; -} diff --git a/QDMA/DPDK/examples/qdma_testapp/testapp.h b/QDMA/DPDK/examples/qdma_testapp/testapp.h deleted file mode 100755 index 5d58a0d02..000000000 --- a/QDMA/DPDK/examples/qdma_testapp/testapp.h +++ /dev/null @@ -1,108 +0,0 @@ -/*- - * BSD LICENSE - * - * Copyright (c) 2017-2022 Xilinx, Inc. All rights reserved. - * Copyright (c) 2022-2023, Advanced Micro Devices, Inc. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * * Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#define QDMA_MAX_PORTS 256 - -#define PORT_0 0 - -#define NUM_DESC_PER_RING 1024 -#ifdef PERF_BENCHMARK -#define NUM_RX_PKTS (NUM_DESC_PER_RING - 2) -#else -#define NUM_RX_PKTS 32 -#endif - -/* Tandem boot feature involves DMA transfer of - * second stage bootloader size greater than 2MB - * from Host to Slave Boot Interface(SBI) buffer. - * Increased the limit of pending tx packets that need - * to process by application to avoid transfer timeouts. - */ -#ifdef TANDEM_BOOT_SUPPORTED -#define NUM_TX_PKTS 128 -#else -#define NUM_TX_PKTS 32 -#endif - -#define MAX_NUM_QUEUES 4096 -#define DEFAULT_NUM_QUEUES 64 -#define RX_TX_MAX_RETRY 1500 -#define DEFAULT_RX_WRITEBACK_THRESH (64) - -#define MP_CACHE_SZ 512 -#define MBUF_POOL_NAME_PORT "mbuf_pool_%d" - -/* AXI Master Lite bar(user bar) registers */ -#define C2H_ST_QID_REG 0x0 -#define C2H_ST_LEN_REG 0x4 -#define C2H_CONTROL_REG 0x8 -#define ST_LOOPBACK_EN 0x1 -#define ST_C2H_START_VAL 0x2 -#define ST_C2H_IMMEDIATE_DATA_EN 0x4 -#define C2H_CONTROL_REG_MASK 0xF -#define H2C_CONTROL_REG 0xC -#define H2C_STATUS_REG 0x10 -#define C2H_PACKET_COUNT_REG 0x20 -#define C2H_STATUS_REG 0x18 -#define C2H_STREAM_MARKER_PKT_GEN_VAL 0x22 -#define MARKER_RESPONSE_COMPLETION_BIT 0x1 - -extern int num_ports; - -struct port_info { - int config_bar_idx; - int user_bar_idx; - int bypass_bar_idx; - unsigned int queue_base; - unsigned int num_queues; - unsigned int nb_descs; - unsigned int st_queues; - unsigned int buff_size; - rte_spinlock_t port_update_lock; - char mem_pool[RTE_MEMPOOL_NAMESIZE]; -}; - -extern struct port_info pinfo[QDMA_MAX_PORTS]; -int port_init(int port_id, int num_queues, int st_queues, - int nb_descs, int buff_size); -int do_recv_st(int port_id, int fd, int queueid, int input_size); -int do_recv_mm(int port_id, int fd, int queueid, - int ld_size, int tot_num_desc); -int do_xmit(int port_id, int fd, int queueid, - int ld_size, int tot_num_desc, int zbyte); -void load_file_cmds(struct cmdline *cl); -void port_close(int port_id); -int port_reset(int port_id, int num_queues, int st_queues, - int nb_descs, int buff_size); -int port_remove(int port_id); -int parse_cmdline(int argc, char **argv); diff --git a/QDMA/DPDK/tools/0001-Add-QDMA-xdebug-to-proc-info-of-dpdk-22.11.patch b/QDMA/DPDK/tools/0001-Add-QDMA-xdebug-to-proc-info-of-dpdk-22.11.patch deleted file mode 100755 index e3501a48a..000000000 --- a/QDMA/DPDK/tools/0001-Add-QDMA-xdebug-to-proc-info-of-dpdk-22.11.patch +++ /dev/null @@ -1,362 +0,0 @@ -From aa6931cc32ac9c7baea453717a34816f01803536 Mon Sep 17 00:00:00 2001 -From: Suryanarayana Raju Sangani -Date: Mon, 19 Jun 2023 12:44:20 +0530 -Subject: [PATCH] Add QDMA xdebug to proc-info of dpdk-22.11 - -Signed-off-by: Nikhil agarwal -Signed-off-by: Prasad Pardeshi -Signed-off-by: Sangani Suryanarayana Raju ---- - app/proc-info/main.c | 195 ++++++++++++++++++++++++++++++++++++-- - app/proc-info/meson.build | 2 +- - app/test-pmd/config.c | 2 + - 3 files changed, 189 insertions(+), 10 deletions(-) - mode change 100644 => 100755 app/proc-info/main.c - mode change 100644 => 100755 app/proc-info/meson.build - mode change 100644 => 100755 app/test-pmd/config.c - -diff --git a/app/proc-info/main.c b/app/proc-info/main.c -old mode 100644 -new mode 100755 -index 53e852a..eeb20e7 ---- a/app/proc-info/main.c -+++ b/app/proc-info/main.c -@@ -32,6 +32,7 @@ - #ifdef RTE_LIB_METRICS - #include - #endif -+#include - #include - #ifdef RTE_LIB_SECURITY - #include -@@ -55,9 +56,31 @@ - STATS_BDR_FMT, s, w, STATS_BDR_FMT) - - /* mask of enabled ports */ --static unsigned long enabled_port_mask; -+static uint64_t enabled_port_mask; -+/**< QID for queue context */ -+static uint32_t qid; -+/**< desc dump type */ -+static uint32_t desc_type; -+/**< QID for desc start value */ -+static uint32_t start; -+/**< QID for desc end value */ -+static uint32_t end; -+/**< Enable desc dump. */ -+static uint32_t enable_desc_dump; - /* Enable stats. */ - static uint32_t enable_stats; -+/**< Enable Device Structs */ -+static uint32_t qdma_device; -+/**< Enable QDMA Tx and Rx queue stats */ -+static uint32_t qdma_qstats; -+/**< Clear QDMA Tx and Rx queue stats */ -+static uint32_t qdma_qstats_clear; -+/**< Enable Queue context and Queue structs. */ -+static uint32_t queue_info; -+/**< Enable register field information. */ -+static uint32_t reg_info; -+/**< Register address */ -+static uint32_t reg_addr; - /* Enable xstats. */ - static uint32_t enable_xstats; - /* Enable collectd format */ -@@ -76,6 +99,8 @@ static uint32_t reset_stats; - static uint32_t reset_xstats; - /* Enable memory info. */ - static uint32_t mem_info; -+/**< Enable Global Errors . */ -+static uint32_t qdma_csr_info; - /* Enable displaying xstat name. */ - static uint32_t enable_xstats_name; - static char *xstats_name; -@@ -138,8 +163,15 @@ proc_info_usage(const char *prgname) - { - printf("%s [EAL options] -- -p PORTMASK\n" - " -m to display DPDK memory zones, segments and TAILQ information\n" -+ " -g to display DPDK QDMA PMD global CSR info\n" - " -p PORTMASK: hexadecimal bitmask of ports to retrieve stats for\n" - " --stats: to display port statistics, enabled by default\n" -+ " --qdevice: to display QDMA device structure\n" -+ " --qstats: to display QDMA Tx and Rx queue stats\n" -+ " --qstats_clr: to clear QDMA Tx and Rx queue stats\n" -+ " --qinfo: to display QDMA queue context and queue structures\n" -+ " --reg-info {reg_addr}: to display field info of a register at reg_addr offset\n" -+ " --desc-dump {rx | tx | cmpt}: to dump QDMA queue descriptors\n" - " --xstats: to display extended port statistics, disabled by " - "default\n" - #ifdef RTE_LIB_METRICS -@@ -179,7 +211,7 @@ proc_info_usage(const char *prgname) - /* - * Parse the portmask provided at run time. - */ --static int -+static int64_t - parse_portmask(const char *portmask) - { - char *end = NULL; -@@ -196,6 +228,71 @@ parse_portmask(const char *portmask) - return 0; - } - -+/* -+ * * Parse the QID provided at run time. -+ **/ -+static int -+parse_int(const char *id) -+{ -+ char *end = NULL; -+ unsigned long val; -+ -+ errno = 0; -+ -+ /* parse hexadecimal string */ -+ val = strtoul(id, &end, 10); -+ if ((id[0] == '\0') || (end == NULL) || (*end != '\0') || -+ (errno != 0)) { -+ printf("%s ERROR parsing the QID\n", __func__); -+ return -1; -+ } -+ -+ return val; -+} -+ -+/* -+ * Parse the register address provided at run time. -+ */ -+static int32_t -+parse_reg_addr(const char *addr) -+{ -+ char *end = NULL; -+ -+ errno = 0; -+ -+ /* parse hexadecimal string */ -+ reg_addr = strtoul(addr, &end, 16); -+ if ((addr[0] == '\0') || (end == NULL) || (*end != '\0') || -+ (errno != 0)) { -+ printf("%s ERROR parsing the register address\n", __func__); -+ return -1; -+ } -+ -+ if (reg_addr == 0) -+ return -1; -+ -+ return reg_addr; -+} -+ -+/* -+ * * Parse the desc dump type provided at run time. -+ **/ -+static int -+parse_desc_type(const char *type) -+{ -+ if (!strcmp(type, "rx")) { -+ desc_type = RTE_PMD_QDMA_XDEBUG_DESC_C2H; -+ } else if (!strcmp(type, "tx")) { -+ desc_type = RTE_PMD_QDMA_XDEBUG_DESC_H2C; -+ } else if (!strcmp(type, "cmpt")) { -+ desc_type = RTE_PMD_QDMA_XDEBUG_DESC_CMPT; -+ } else { -+ printf("%s ERROR parsing the desc type\n", __func__); -+ return -1; -+ } -+ return 0; -+} -+ - /* - * Parse ids value list into array - */ -@@ -273,11 +370,17 @@ proc_info_preparse_args(int argc, char **argv) - static int - proc_info_parse_args(int argc, char **argv) - { -- int opt; -+ int opt, ret; - int option_index; - char *prgname = argv[0]; - static struct option long_option[] = { - {"stats", 0, NULL, 0}, -+ {"qdevice", 0, NULL, 0}, -+ {"qstats", 0, NULL, 0}, -+ {"qstats_clr", 0, NULL, 0}, -+ {"qinfo", 0, NULL, 0}, -+ {"reg-info", required_argument, NULL, 1}, -+ {"desc-dump", required_argument, NULL, 1}, - {"stats-reset", 0, NULL, 0}, - {"xstats", 0, NULL, 0}, - #ifdef RTE_LIB_METRICS -@@ -309,7 +412,7 @@ proc_info_parse_args(int argc, char **argv) - proc_info_usage(prgname); - - /* Parse command line */ -- while ((opt = getopt_long(argc, argv, "p:m", -+ while ((opt = getopt_long(argc, argv, "p:mq:gs:e:", - long_option, &option_index)) != EOF) { - switch (opt) { - /* portmask */ -@@ -322,11 +425,54 @@ proc_info_parse_args(int argc, char **argv) - case 'm': - mem_info = 1; - break; -+ case 'g': -+ qdma_csr_info = 1; -+ break; -+ case 'q': -+ ret = parse_int(optarg); -+ if (ret < 0) { -+ printf("Invalid queue\n"); -+ return -1; -+ } -+ qid = ret; -+ break; -+ case 's': -+ ret = parse_int(optarg); -+ if (ret < 0) { -+ printf("Invalid start value\n"); -+ return -1; -+ } -+ start = ret; -+ break; -+ case 'e': -+ ret = parse_int(optarg); -+ if (ret < 0) { -+ printf("Invalid end value\n"); -+ return -1; -+ } -+ end = ret; -+ break; - case 0: - /* Print stats */ - if (!strncmp(long_option[option_index].name, "stats", - MAX_LONG_OPT_SZ)) - enable_stats = 1; -+ /* Print qdma device */ -+ if (!strncmp(long_option[option_index].name, "qdevice", -+ MAX_LONG_OPT_SZ)) -+ qdma_device = 1; -+ /* Print qdma Tx and Rx queue stats */ -+ if (!strncmp(long_option[option_index].name, "qstats", -+ MAX_LONG_OPT_SZ)) -+ qdma_qstats = 1; -+ /* Clear qdma Tx and Rx queue stats */ -+ if (!strncmp(long_option[option_index].name, "qstats_clr", -+ MAX_LONG_OPT_SZ)) -+ qdma_qstats_clear = 1; -+ /* Print queue context and queue Structures*/ -+ if (!strncmp(long_option[option_index].name, "qinfo", -+ MAX_LONG_OPT_SZ)) -+ queue_info = 1; - /* Print xstats */ - else if (!strncmp(long_option[option_index].name, "xstats", - MAX_LONG_OPT_SZ)) -@@ -425,6 +571,24 @@ proc_info_parse_args(int argc, char **argv) - return -1; - } - enable_shw_tx_desc_dump = 1; -+ } else if (!strncmp(long_option[option_index].name, -+ "desc-dump", -+ MAX_LONG_OPT_SZ)) { -+ if (parse_desc_type(optarg) < 0) { -+ printf("desc-dump parse error.\n"); -+ proc_info_usage(prgname); -+ return -1; -+ } -+ enable_desc_dump = 1; -+ } else if (!strncmp(long_option[option_index].name, -+ "reg-info", -+ MAX_LONG_OPT_SZ)) { -+ if (parse_reg_addr(optarg) < 0) { -+ printf("reg-info parse error.\n"); -+ proc_info_usage(prgname); -+ return -1; -+ } -+ reg_info = 1; - } - break; - default: -@@ -1791,7 +1955,6 @@ main(int argc, char **argv) - - if (mem_info) { - meminfo_display(); -- return 0; - } - - nb_ports = rte_eth_dev_count_avail(); -@@ -1807,7 +1970,7 @@ main(int argc, char **argv) - for (i = 0; i < RTE_MAX_ETHPORTS; i++) { - - /* Skip if port is not in mask */ -- if ((enabled_port_mask & (1ul << i)) == 0) -+ if ((enabled_port_mask & ((uint64_t)1 << i)) == 0) - continue; - - /* Skip if port is unused */ -@@ -1832,6 +1995,23 @@ main(int argc, char **argv) - metrics_display(i); - #endif - -+ else if (qdma_csr_info) -+ rte_pmd_qdma_dbg_regdump(i); -+ else if (qdma_device) -+ rte_pmd_qdma_dbg_qdevice(i); -+ else if (qdma_qstats) -+ rte_pmd_qdma_qstats(i, qid); -+ else if (qdma_qstats_clear) -+ rte_pmd_qdma_qstats_clear(i, qid); -+ else if (queue_info) -+ rte_pmd_qdma_dbg_qinfo(i, qid); -+ else if (reg_info) -+ rte_pmd_qdma_dbg_reg_info_dump(i, -+ 1, reg_addr); -+ else if (enable_desc_dump) -+ rte_pmd_qdma_dbg_qdesc(i, qid, -+ start, end, desc_type); -+ - if (enable_shw_rx_desc_dump) - nic_rx_descriptor_display(i, &rx_desc_param); - if (enable_shw_tx_desc_dump) -@@ -1870,9 +2050,6 @@ main(int argc, char **argv) - if (enable_shw_module_eeprom) - show_module_eeprom_info(); - -- RTE_ETH_FOREACH_DEV(i) -- rte_eth_dev_close(i); -- - ret = rte_eal_cleanup(); - if (ret) - printf("Error from rte_eal_cleanup(), %d\n", ret); -diff --git a/app/proc-info/meson.build b/app/proc-info/meson.build -old mode 100644 -new mode 100755 -index 1563ce6..340b9ab ---- a/app/proc-info/meson.build -+++ b/app/proc-info/meson.build -@@ -8,7 +8,7 @@ if is_windows - endif - - sources = files('main.c') --deps += ['ethdev', 'security'] -+deps += ['ethdev', 'metrics', 'security', 'net_qdma'] - if dpdk_conf.has('RTE_LIB_METRICS') - deps += 'metrics' - endif -diff --git a/app/test-pmd/config.c b/app/test-pmd/config.c -old mode 100644 -new mode 100755 -index acccb6b..6d51d62 ---- a/app/test-pmd/config.c -+++ b/app/test-pmd/config.c -@@ -58,6 +58,8 @@ - #include "testpmd.h" - #include "cmdline_mtr.h" - -+#include -+ - #define ETHDEV_FWVERS_LEN 32 - - #ifdef CLOCK_MONOTONIC_RAW /* Defined in glibc bits/time.h */ --- -2.25.1 - diff --git a/QDMA/DPDK/tools/0001-PKTGEN-20.12.0-Patch-to-add-Jumbo-packet-support.patch b/QDMA/DPDK/tools/0001-PKTGEN-20.12.0-Patch-to-add-Jumbo-packet-support.patch deleted file mode 100755 index e0a11d480..000000000 --- a/QDMA/DPDK/tools/0001-PKTGEN-20.12.0-Patch-to-add-Jumbo-packet-support.patch +++ /dev/null @@ -1,320 +0,0 @@ -From 8d8204c48660cfe67ce27c95ce029e2cfa302958 Mon Sep 17 00:00:00 2001 -From: Suryanarayana Raju Sangani -Date: Thu, 27 Feb 2020 05:13:38 -0700 -Subject: [PATCH] PKTGEN-20.12.0: Patch to add Jumbo packet support - -This patch include: -1. Jumbo frame support for Pktgen. -2. Increase default number of RX_DESC to 2K. -3. Disable RX classification. -4. Set user provided packet size as DMA packet size i.e. not to remove -CRC bytes - -Signed-off-by: Kumar Sanghvi -Signed-off-by: Nikhil Agarwal -Signed-off-by: Pankaj Darak -Signed-off-by: Thanneeru Srinivasulu -Signed-off-by: tarakr -Signed-off-by: Suryanarayana Raju Sangani ---- - app/pktgen-cmds.c | 15 +++++++++++---- - app/pktgen-constants.h | 3 ++- - app/pktgen-main.c | 24 +++++++++++++++++------- - app/pktgen-port-cfg.c | 12 ++++++++---- - app/pktgen-range.c | 3 ++- - app/pktgen.c | 19 +++++++++++++++++-- - app/pktgen.h | 4 +++- - 7 files changed, 60 insertions(+), 20 deletions(-) - -diff --git a/app/pktgen-cmds.c b/app/pktgen-cmds.c -index 4da9bab..065fbe8 100644 ---- a/app/pktgen-cmds.c -+++ b/app/pktgen-cmds.c -@@ -3125,18 +3125,22 @@ single_set_pkt_size(port_info_t *info, uint16_t size) - { - pkt_seq_t * pkt = &info->seq_pkt[SINGLE_PKT]; - -+ uint16_t pktsize = (pktgen.flags & MTU9K_SUPPORT_FLAG) ? -+ MAX_PKT_SIZE: (PG_ETHER_MAX_LEN - PG_ETHER_CRC_LEN); -+ - if (size < PG_ETHER_CRC_LEN) - size = PG_ETHER_CRC_LEN; - - if ( (size - PG_ETHER_CRC_LEN) < MIN_PKT_SIZE) - size = pktgen.eth_min_pkt; -- if ( (size - PG_ETHER_CRC_LEN) > MAX_PKT_SIZE) -- size = pktgen.eth_max_pkt; -+ if ( (size - PG_ETHER_CRC_LEN) > pktsize) -+ size = pktsize + PG_ETHER_CRC_LEN; - - if ((pkt->ethType == PG_ETHER_TYPE_IPv6) && (size < (MIN_v6_PKT_SIZE + PG_ETHER_CRC_LEN))) - size = MIN_v6_PKT_SIZE + PG_ETHER_CRC_LEN; - - pkt->pktSize = (size - PG_ETHER_CRC_LEN); -+ pkt->pktSize = size; - - pktgen_packet_ctor(info, SINGLE_PKT, -1); - pktgen_packet_rate(info); -@@ -3924,6 +3928,9 @@ range_set_cos_id(port_info_t *info, char *what, uint8_t id) - void - range_set_pkt_size(port_info_t *info, char *what, uint16_t size) - { -+ uint32_t pktsize = (pktgen.flags & MTU9K_SUPPORT_FLAG) ? -+ MAX_9K_SIZE : PG_ETHER_MAX_LEN; -+ - if (!strcmp(what, "inc") || !strcmp(what, "increment")) { - if (size > pktgen.eth_max_pkt) - size = pktgen.eth_max_pkt; -@@ -3931,8 +3938,8 @@ range_set_pkt_size(port_info_t *info, char *what, uint16_t size) - } else { - if (size < pktgen.eth_min_pkt) - size = MIN_PKT_SIZE; -- else if (size > pktgen.eth_max_pkt) -- size = MAX_PKT_SIZE; -+ else if (size > pktsize) -+ size = pktsize; - else - size -= PG_ETHER_CRC_LEN; - -diff --git a/app/pktgen-constants.h b/app/pktgen-constants.h -index ede4e65..8694e18 100644 ---- a/app/pktgen-constants.h -+++ b/app/pktgen-constants.h -@@ -17,7 +17,7 @@ extern "C" { - enum { - #ifndef RTE_LIBRTE_VMXNET3_PMD - DEFAULT_PKT_BURST = 64, /* Increasing this number consumes memory very fast */ -- DEFAULT_RX_DESC = (DEFAULT_PKT_BURST * 8 * 2), -+ DEFAULT_RX_DESC = (DEFAULT_PKT_BURST * 8 * 2 * 2), - DEFAULT_TX_DESC = DEFAULT_RX_DESC * 2, - #else - DEFAULT_PKT_BURST = 32, /* Increasing this number consumes memory very fast */ -@@ -31,6 +31,7 @@ enum { - - DEFAULT_PRIV_SIZE = 0, - -+ MBUF_9K_SIZE = 9018 + RTE_PKTMBUF_HEADROOM + DEFAULT_PRIV_SIZE, - NUM_Q = 16, /**< Number of cores per port. */ - }; - #define DEFAULT_MBUF_SIZE (PG_ETHER_MAX_JUMBO_FRAME_LEN + RTE_PKTMBUF_HEADROOM) /* See: http://dpdk.org/dev/patchwork/patch/4479/ */ -diff --git a/app/pktgen-main.c b/app/pktgen-main.c -index 96d1c0c..1ca2941 100644 ---- a/app/pktgen-main.c -+++ b/app/pktgen-main.c -@@ -188,7 +188,7 @@ pktgen_parse_args(int argc, char **argv) - pktgen.mbuf_buf_size = RTE_MBUF_DEFAULT_BUF_SIZE; - - pktgen.verbose = 0; -- while ((opt = getopt_long(argc, argvopt, "p:m:f:l:s:g:hPNGTvjtr", -+ while ((opt = getopt_long(argc, argvopt, "p:m:f:l:s:g:hPNGTvjtr9", - lgopts, &option_index)) != EOF) - switch (opt) { - case 't': -@@ -300,7 +300,12 @@ pktgen_parse_args(int argc, char **argv) - - case 'h': /* print out the help message */ - pktgen_usage(prgname); -- return -1; -+ return -1; -+ -+ case '9': /* MTU 9K support */ -+ pktgen_log_info("%s: case 9... \n", __func__); -+ pktgen.flags |= MTU9K_SUPPORT_FLAG; -+ break; - - case 0: /* crc-strip for all ports */ - printf(">>> Strip CRC in hardware is the default\n"); -@@ -407,8 +412,10 @@ RTE_FINI(pktgen_fini) - int - main(int argc, char **argv) - { -- uint32_t i; -+ uint32_t nb_ports; -+ int32_t i; - int32_t ret; -+ struct rte_device *dev; - - signal(SIGSEGV, sig_handler); - signal(SIGHUP, sig_handler); -@@ -563,10 +570,13 @@ main(int argc, char **argv) - /* Wait for all of the cores to stop running and exit. */ - rte_eal_mp_wait_lcore(); - -- RTE_ETH_FOREACH_DEV(i) { -- rte_eth_dev_stop(i); -- rte_delay_us_sleep(100 * 1000); -- rte_eth_dev_close(i); -+ nb_ports = rte_eth_dev_count_avail(); -+ for(i = nb_ports-1; i >= 0; i--) { -+ dev = rte_eth_devices[i].device; -+ if (rte_dev_remove(dev)) -+ printf("Failed to detach port '%d'\n", i); -+ else -+ printf("successfully removed port '%d'\n", i); - } - - cli_destroy(); -diff --git a/app/pktgen-port-cfg.c b/app/pktgen-port-cfg.c -index a982d0d..7a27602 100644 ---- a/app/pktgen-port-cfg.c -+++ b/app/pktgen-port-cfg.c -@@ -101,16 +101,19 @@ pktgen_mbuf_pool_create(const char *type, uint8_t pid, uint8_t queue_id, - struct rte_mempool *mp; - char name[RTE_MEMZONE_NAMESIZE]; - uint64_t sz; -+ uint16_t mbuf_sz = (pktgen.flags & MTU9K_SUPPORT_FLAG) ? -+ MBUF_9K_SIZE :DEFAULT_MBUF_SIZE; -+ - - snprintf(name, sizeof(name), "%-12s%u:%u", type, pid, queue_id); - -- sz = nb_mbufs * (DEFAULT_MBUF_SIZE + sizeof(struct rte_mbuf)); -+ sz = nb_mbufs * (mbuf_sz + sizeof(struct rte_mbuf)); - sz = RTE_ALIGN_CEIL(sz + sizeof(struct rte_mempool), 1024); - - if (pktgen.verbose) - pktgen_log_info( - " Create: %-*s - Memory used (MBUFs %5u x (size %u + Hdr %lu)) + %lu = %6lu KB, headroom %d", -- 16, name, nb_mbufs, DEFAULT_MBUF_SIZE, -+ 16, name, nb_mbufs, mbuf_sz, - sizeof(struct rte_mbuf), sizeof(struct rte_mempool), - sz / 1024, RTE_PKTMBUF_HEADROOM); - -@@ -119,7 +122,7 @@ pktgen_mbuf_pool_create(const char *type, uint8_t pid, uint8_t queue_id, - - /* create the mbuf pool */ - mp = rte_pktmbuf_pool_create(name, nb_mbufs, cache_size, -- DEFAULT_PRIV_SIZE, DEFAULT_MBUF_SIZE, socket_id); -+ DEFAULT_PRIV_SIZE, mbuf_sz, socket_id); - if (mp == NULL) - pktgen_log_panic( - "Cannot create mbuf pool (%s) port %d, queue %d, nb_mbufs %d, socket_id %d: %s", -@@ -227,7 +230,8 @@ pktgen_config_ports(void) - pktgen_log_info( - ">>>> Configuring %d ports, MBUF Size %d, MBUF Cache Size %d", - pktgen.nb_ports, -- DEFAULT_MBUF_SIZE, -+ (pktgen.flags & MTU9K_SUPPORT_FLAG) ? MBUF_9K_SIZE : -+ DEFAULT_MBUF_SIZE, - MBUF_CACHE_SIZE); - } - -diff --git a/app/pktgen-range.c b/app/pktgen-range.c -index f88258d..bbaaa6f 100644 ---- a/app/pktgen-range.c -+++ b/app/pktgen-range.c -@@ -595,7 +595,8 @@ pktgen_range_setup(port_info_t *info) - range->pkt_size = MIN_PKT_SIZE; - range->pkt_size_inc = 0; - range->pkt_size_min = MIN_PKT_SIZE; -- range->pkt_size_max = MAX_PKT_SIZE; -+ range->pkt_size_max = (pktgen.flags & MTU9K_SUPPORT_FLAG) ? -+ MAX_PKT_SIZE : (PG_ETHER_MAX_LEN - PG_ETHER_CRC_LEN); - - range->vxlan_gid = info->seq_pkt[SINGLE_PKT].group_id; - range->vxlan_gid_inc = 0; -diff --git a/app/pktgen.c b/app/pktgen.c -index 26cc80d..1042a47 100644 ---- a/app/pktgen.c -+++ b/app/pktgen.c -@@ -74,6 +74,7 @@ pktgen_wire_size(port_info_t *info) - } else - size = info->seq_pkt[SINGLE_PKT].pktSize + PKT_OVERHEAD_SIZE; - } -+ size -= (PKT_PREAMBLE_SIZE + INTER_FRAME_GAP + PG_ETHER_CRC_LEN); - return size; - } - -@@ -296,6 +297,7 @@ pktgen_send_burst(port_info_t *info, uint16_t qid) - struct qstats_s *qstats; - uint32_t ret, cnt, tap, rnd, tstamp, i; - int32_t seq_idx; -+ pkt_seq_t *pkt; - - if ((cnt = mtab->len) == 0) - return; -@@ -310,6 +312,10 @@ pktgen_send_burst(port_info_t *info, uint16_t qid) - else - seq_idx = SINGLE_PKT; - -+ pkt = &info->seq_pkt[seq_idx]; -+ for (i = 0; i < cnt; i++) -+ rte_pktmbuf_pkt_len(pkts[i]) = pkt->pktSize; -+ - tap = pktgen_tst_port_flags(info, PROCESS_TX_TAP_PKTS); - rnd = pktgen_tst_port_flags(info, SEND_RANDOM_PKTS); - tstamp = pktgen_tst_port_flags(info, (SEND_LATENCY_PKTS | SEND_RATE_PACKETS | SAMPLING_LATENCIES)); -@@ -912,6 +918,10 @@ pktgen_setup_cb(struct rte_mempool *mp, - pkt_seq_t *pkt; - uint16_t qid, idx; - -+ uint32_t pktsize = (pktgen.flags & MTU9K_SUPPORT_FLAG) ? -+ MAX_PKT_SIZE: -+ (PG_ETHER_MAX_LEN - PG_ETHER_CRC_LEN); -+ - info = data->info; - qid = data->qid; - -@@ -941,7 +951,7 @@ pktgen_setup_cb(struct rte_mempool *mp, - pktgen_packet_ctor(info, idx, -1); - - rte_memcpy((uint8_t *)m->buf_addr + m->data_off, -- (uint8_t *)&pkt->hdr, MAX_PKT_SIZE); -+ (uint8_t *)&pkt->hdr, pktsize); - - m->pkt_len = pkt->pktSize; - m->data_len = pkt->pktSize; -@@ -1150,7 +1160,7 @@ pktgen_main_receive(port_info_t *info, uint8_t lid, - { - uint8_t pid; - uint16_t qid, nb_rx; -- capture_t *capture; -+ __rte_unused capture_t *capture; - struct qstats_s *qstats; - int i; - -@@ -1169,6 +1179,10 @@ pktgen_main_receive(port_info_t *info, uint8_t lid, - for(i = 0; i < nb_rx; i++) - qstats->rxbytes += rte_pktmbuf_data_len(pkts_burst[i]); - -+ info->sizes._64 += nb_rx; -+ rte_pktmbuf_free_bulk(pkts_burst, nb_rx); -+ -+#if 0 - pktgen_recv_tstamp(info, pkts_burst, nb_rx); - - /* packets are not freed in the next call. */ -@@ -1185,6 +1199,7 @@ pktgen_main_receive(port_info_t *info, uint8_t lid, - } - - rte_pktmbuf_free_bulk(pkts_burst, nb_rx); -+#endif - } - - static void -diff --git a/app/pktgen.h b/app/pktgen.h -index 66fa12e..20fb943 100644 ---- a/app/pktgen.h -+++ b/app/pktgen.h -@@ -253,8 +253,9 @@ enum { - SOCKET0 = 0 /**< Socket ID value for allocation */ - }; - -+#define MAX_9K_SIZE 9018 - #define MIN_PKT_SIZE (pktgen.eth_min_pkt - PG_ETHER_CRC_LEN) --#define MAX_PKT_SIZE (pktgen.eth_max_pkt - PG_ETHER_CRC_LEN) -+#define MAX_PKT_SIZE (MAX_9K_SIZE - PG_ETHER_CRC_LEN) - - typedef struct rte_mbuf rte_mbuf_t; - -@@ -351,6 +352,7 @@ enum { /* Pktgen flags bits */ - BLINK_PORTS_FLAG = (1 << 10), /**< Blink the port leds */ - ENABLE_THEME_FLAG = (1 << 11), /**< Enable theme or color support */ - -+ MTU9K_SUPPORT_FLAG = (1 << 15), /**< MTU 9K support */ - CONFIG_PAGE_FLAG = (1 << 16), /**< Display the configure page */ - SEQUENCE_PAGE_FLAG = (1 << 17), /**< Display the Packet sequence page */ - RANGE_PAGE_FLAG = (1 << 18), /**< Display the range page */ --- -2.17.1 - diff --git a/QDMA/DPDK/tools/0001-PKTGEN-22.04.1-Patch-to-add-Jumbo-packet-support.patch b/QDMA/DPDK/tools/0001-PKTGEN-22.04.1-Patch-to-add-Jumbo-packet-support.patch deleted file mode 100755 index e50d80d83..000000000 --- a/QDMA/DPDK/tools/0001-PKTGEN-22.04.1-Patch-to-add-Jumbo-packet-support.patch +++ /dev/null @@ -1,466 +0,0 @@ -From fb3ffa15e6d1f6b1a576b393ff69317707351aae Mon Sep 17 00:00:00 2001 -From: Prasad Pardeshi -Date: Tue, 28 Feb 2023 17:37:06 +0530 -Subject: [PATCH] [PATCH] PKTGEN-22.04.1: Patch to add Jumbo packet support - -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -This patch include: -1. Jumbo frame support for Pktgen. -2. Increase default number of RX_DESC to 2K. -3. Disable RX classification. -4. Set user provided packet size as DMA packet size i.e. not to remove -CRC bytes Signed-off-by: Kumar Sanghvi -Signed-off-by: Nikhil Agarwal -Signed-off-by: Pankaj Darak -Signed-off-by: Thanneeru Srinivasulu -Signed-off-by: tarakr -Signed-off-by: Suryanarayana Raju Sangani ---- - app/lpktgenlib.c | 2 ++ - app/meson.build | 1 + - app/pktgen-cmds.c | 18 ++++++++++++++---- - app/pktgen-constants.h | 4 ++-- - app/pktgen-latency.c | 2 ++ - app/pktgen-main.c | 25 ++++++++++++++++++------- - app/pktgen-port-cfg.c | 15 ++++++++++----- - app/pktgen-port-cfg.h | 2 +- - app/pktgen-range.c | 3 ++- - app/pktgen-rate.c | 2 ++ - app/pktgen-stats.c | 2 ++ - app/pktgen.c | 19 +++++++++++++++++-- - app/pktgen.h | 5 +++-- - lib/cli/cli_map.c | 1 + - lib/common/pg_strings.c | 1 + - 15 files changed, 78 insertions(+), 24 deletions(-) - -diff --git a/app/lpktgenlib.c b/app/lpktgenlib.c -index bc24433..add5a16 100644 ---- a/app/lpktgenlib.c -+++ b/app/lpktgenlib.c -@@ -14,6 +14,8 @@ - #include - #include "lpktgenlib.h" - -+#include -+#include - #include - #include - -diff --git a/app/meson.build b/app/meson.build -index 66087a5..1027997 100644 ---- a/app/meson.build -+++ b/app/meson.build -@@ -35,6 +35,7 @@ deps += [cc.find_library('rte_net_i40e', required: false)] - deps += [cc.find_library('rte_net_ixgbe', required: false)] - deps += [cc.find_library('rte_net_ice', required: false)] - deps += [cc.find_library('rte_bus_vdev', required: false)] -+deps += [cc.find_library('rte_net_qdma', required: true)] - - deps += [dependency('threads')] - deps += [cc.find_library('numa', required: true)] -diff --git a/app/pktgen-cmds.c b/app/pktgen-cmds.c -index 9708b28..f92b890 100644 ---- a/app/pktgen-cmds.c -+++ b/app/pktgen-cmds.c -@@ -3054,18 +3054,25 @@ single_set_pkt_size(port_info_t *info, uint16_t size) - { - pkt_seq_t *pkt = &info->seq_pkt[SINGLE_PKT]; - -+ uint16_t pktsize = (pktgen.flags & MTU9K_SUPPORT_FLAG) ? -+ MAX_PKT_SIZE: (RTE_ETHER_MAX_LEN - RTE_ETHER_CRC_LEN); -+ -+ - if (size < RTE_ETHER_CRC_LEN) - size = RTE_ETHER_CRC_LEN; - -+ -+ - if ((size - RTE_ETHER_CRC_LEN) < MIN_PKT_SIZE) - size = pktgen.eth_min_pkt; -- if ((size - RTE_ETHER_CRC_LEN) > MAX_PKT_SIZE) -- size = pktgen.eth_max_pkt; -+ if ( (size - RTE_ETHER_CRC_LEN) > pktsize) -+ size = pktsize + RTE_ETHER_CRC_LEN; - - if ((pkt->ethType == RTE_ETHER_TYPE_IPV6) && (size < (MIN_v6_PKT_SIZE + RTE_ETHER_CRC_LEN))) - size = MIN_v6_PKT_SIZE + RTE_ETHER_CRC_LEN; - - pkt->pktSize = (size - RTE_ETHER_CRC_LEN); -+ pkt->pktSize = size; - - pktgen_packet_ctor(info, SINGLE_PKT, -1); - pktgen_packet_rate(info); -@@ -3094,6 +3101,7 @@ rate_set_pkt_size(port_info_t *info, uint16_t size) - - if ((size - RTE_ETHER_CRC_LEN) < MIN_PKT_SIZE) - size = pktgen.eth_min_pkt; -+ - if ((size - RTE_ETHER_CRC_LEN) > MAX_PKT_SIZE) - size = pktgen.eth_max_pkt; - -@@ -4209,6 +4217,8 @@ range_set_cos_id(port_info_t *info, char *what, uint8_t id) - void - range_set_pkt_size(port_info_t *info, char *what, uint16_t size) - { -+ uint32_t pktsize = (pktgen.flags & MTU9K_SUPPORT_FLAG) ? -+ MAX_9K_SIZE : RTE_ETHER_MAX_LEN; - if (!strcmp(what, "inc") || !strcmp(what, "increment")) { - if (size > pktgen.eth_max_pkt) - size = pktgen.eth_max_pkt; -@@ -4216,8 +4226,8 @@ range_set_pkt_size(port_info_t *info, char *what, uint16_t size) - } else { - if (size < pktgen.eth_min_pkt) - size = MIN_PKT_SIZE; -- else if (size > pktgen.eth_max_pkt) -- size = MAX_PKT_SIZE; -+ else if (size > pktsize) -+ size = pktsize; - else - size -= RTE_ETHER_CRC_LEN; - -diff --git a/app/pktgen-constants.h b/app/pktgen-constants.h -index 6c02f82..16d5f5c 100644 ---- a/app/pktgen-constants.h -+++ b/app/pktgen-constants.h -@@ -17,7 +17,7 @@ extern "C" { - enum { - #if !defined(RTE_LIBRTE_VMXNET3_PMD) && !defined(RTE_NET_VMXNET3) - DEFAULT_PKT_BURST = 64, /* Increasing this number consumes memory very fast */ -- DEFAULT_RX_DESC = (DEFAULT_PKT_BURST * 8 * 2), -+ DEFAULT_RX_DESC = (DEFAULT_PKT_BURST * 8 * 2 * 2), - DEFAULT_TX_DESC = DEFAULT_RX_DESC * 2, - #else - DEFAULT_PKT_BURST = 128, /* Increasing this number consumes memory very fast */ -@@ -30,7 +30,7 @@ enum { - MBUF_CACHE_SIZE = (MAX_MBUFS_PER_PORT / 8), - - DEFAULT_PRIV_SIZE = 0, -- -+ MBUF_9K_SIZE = 9018 + RTE_PKTMBUF_HEADROOM + DEFAULT_PRIV_SIZE, - NUM_Q = 16, /**< Number of cores per port. */ - }; - #define DEFAULT_MBUF_SIZE \ -diff --git a/app/pktgen-latency.c b/app/pktgen-latency.c -index bafaf1c..7787a6f 100644 ---- a/app/pktgen-latency.c -+++ b/app/pktgen-latency.c -@@ -8,6 +8,8 @@ - - #include - -+#include -+#include - #include "lua_config.h" - - #include "pktgen-cmds.h" -diff --git a/app/pktgen-main.c b/app/pktgen-main.c -index 7debdb3..11a118a 100644 ---- a/app/pktgen-main.c -+++ b/app/pktgen-main.c -@@ -29,6 +29,8 @@ - #include "pktgen-log.h" - #include "cli-functions.h" - -+#include -+ - /* Offset to the mbuf dynamic field holding pktgen data. */ - int pktgen_dynfield_offset = -1; - -@@ -206,7 +208,7 @@ pktgen_parse_args(int argc, char **argv) - pktgen.mbuf_buf_size = RTE_MBUF_DEFAULT_BUF_SIZE; - - pktgen.verbose = 0; -- while ((opt = getopt_long(argc, argvopt, "p:m:f:l:s:g:hPNGTvjtr", lgopts, &option_index)) != -+ while ((opt = getopt_long(argc, argvopt, "p:m:f:l:s:g:hPNGTvjtr9", lgopts, &option_index)) != - EOF) - switch (opt) { - case 't': -@@ -315,7 +317,12 @@ pktgen_parse_args(int argc, char **argv) - - case 'h': /* print out the help message */ - pktgen_usage(prgname); -- return -1; -+ return -1; -+ -+ case '9': /* MTU 9K support */ -+ pktgen_log_info("%s: case 9... \n", __func__); -+ pktgen.flags |= MTU9K_SUPPORT_FLAG; -+ break; - - case 0: /* crc-strip for all ports */ - printf(">>> Strip CRC in hardware is the default\n"); -@@ -421,7 +428,8 @@ RTE_FINI(pktgen_fini) - int - main(int argc, char **argv) - { -- uint32_t i; -+ uint32_t nb_ports; -+ int32_t i; - int32_t ret; - - setlocale(LC_ALL, ""); -@@ -574,10 +582,13 @@ main(int argc, char **argv) - /* Wait for all of the cores to stop running and exit. */ - rte_eal_mp_wait_lcore(); - -- RTE_ETH_FOREACH_DEV(i) -- { -- rte_eth_dev_stop(i); -- rte_delay_us_sleep(100 * 1000); -+ nb_ports = rte_eth_dev_count_avail(); -+ for(i = nb_ports-1; i >= 0; i--) { -+ if (rte_pmd_qdma_dev_remove(i)) -+ printf("Failed to detach port '%d'\n", i); -+ else -+ printf("successfully removed port '%d'\n", i); -+ - } - - cli_destroy(); -diff --git a/app/pktgen-port-cfg.c b/app/pktgen-port-cfg.c -index 7a61db3..3579d07 100644 ---- a/app/pktgen-port-cfg.c -+++ b/app/pktgen-port-cfg.c -@@ -10,6 +10,9 @@ - #include - #include - -+#include -+#include -+ - #include "pktgen-port-cfg.h" - - #include "pktgen.h" -@@ -41,7 +44,6 @@ static struct rte_eth_conf default_port_conf = { - { - .mq_mode = RTE_ETH_MQ_RX_RSS, - .max_lro_pkt_size = RTE_ETHER_MAX_LEN, -- .split_hdr_size = 0, - }, - - .rx_adv_conf = -@@ -93,23 +95,25 @@ pktgen_mbuf_pool_create(const char *type, uint8_t pid, uint8_t queue_id, uint32_ - struct rte_mempool *mp; - char name[RTE_MEMZONE_NAMESIZE]; - uint64_t sz; -+ uint16_t mbuf_sz = (pktgen.flags & MTU9K_SUPPORT_FLAG) ? -+ MBUF_9K_SIZE :DEFAULT_MBUF_SIZE; - - snprintf(name, sizeof(name), "%-12s%u:%u", type, pid, queue_id); - -- sz = nb_mbufs * (DEFAULT_MBUF_SIZE + sizeof(struct rte_mbuf)); -+ sz = nb_mbufs * (mbuf_sz + sizeof(struct rte_mbuf)); - sz = RTE_ALIGN_CEIL(sz + sizeof(struct rte_mempool), 1024); - - if (pktgen.verbose) - pktgen_log_info(" Create: %-*s - Memory used (MBUFs %5u x (size %u + Hdr %lu)) + %lu = " - "%6lu KB, headroom %d", -- 16, name, nb_mbufs, DEFAULT_MBUF_SIZE, sizeof(struct rte_mbuf), -+ 16, name, nb_mbufs, mbuf_sz, sizeof(struct rte_mbuf), - sizeof(struct rte_mempool), sz / 1024, RTE_PKTMBUF_HEADROOM); - - pktgen.mem_used += sz; - pktgen.total_mem_used += sz; - - /* create the mbuf pool */ -- mp = rte_pktmbuf_pool_create(name, nb_mbufs, cache_size, DEFAULT_PRIV_SIZE, DEFAULT_MBUF_SIZE, -+ mp = rte_pktmbuf_pool_create(name, nb_mbufs, cache_size, DEFAULT_PRIV_SIZE, mbuf_sz, - socket_id); - if (mp == NULL) - pktgen_log_panic( -@@ -194,7 +198,8 @@ pktgen_config_ports(void) - pg_port_matrix_dump(pktgen.l2p); - - pktgen_log_info(">>>> Configuring %d ports, MBUF Size %d, MBUF Cache Size %d", -- pktgen.nb_ports, DEFAULT_MBUF_SIZE, MBUF_CACHE_SIZE); -+ pktgen.nb_ports, (pktgen.flags & MTU9K_SUPPORT_FLAG) ? MBUF_9K_SIZE : -+ DEFAULT_MBUF_SIZE, MBUF_CACHE_SIZE); - } - - /* For each lcore setup each port that is handled by that lcore. */ -diff --git a/app/pktgen-port-cfg.h b/app/pktgen-port-cfg.h -index 820f131..6ee4f29 100644 ---- a/app/pktgen-port-cfg.h -+++ b/app/pktgen-port-cfg.h -@@ -421,7 +421,7 @@ rte_get_rx_capa_list(uint64_t rx_capa, char *buf, size_t len) - {RTE_ETH_RX_OFFLOAD_QINQ_STRIP, _(QINQ_STRIP)}, - {RTE_ETH_RX_OFFLOAD_OUTER_IPV4_CKSUM, _(OUTER_IPV4_CKSUM)}, - {RTE_ETH_RX_OFFLOAD_MACSEC_STRIP, _(MACSEC_STRIP)}, -- {RTE_ETH_RX_OFFLOAD_HEADER_SPLIT, _(HEADER_SPLIT)}, -+ {RTE_ETH_RX_OFFLOAD_BUFFER_SPLIT, _(HEADER_SPLIT)}, - {RTE_ETH_RX_OFFLOAD_VLAN_FILTER, _(VLAN_FILTER)}, - {RTE_ETH_RX_OFFLOAD_VLAN_EXTEND, _(VLAN_EXTEND)}, - {RTE_ETH_RX_OFFLOAD_SCATTER, _(SCATTER)}, -diff --git a/app/pktgen-range.c b/app/pktgen-range.c -index 7d0ece0..5d9bf04 100644 ---- a/app/pktgen-range.c -+++ b/app/pktgen-range.c -@@ -744,7 +744,8 @@ pktgen_range_setup(port_info_t *info) - range->pkt_size = MIN_PKT_SIZE; - range->pkt_size_inc = 0; - range->pkt_size_min = MIN_PKT_SIZE; -- range->pkt_size_max = MAX_PKT_SIZE; -+ range->pkt_size_max = (pktgen.flags & MTU9K_SUPPORT_FLAG) ? -+ MAX_PKT_SIZE : (RTE_ETHER_MAX_LEN - RTE_ETHER_CRC_LEN); - - range->vxlan_gid = info->seq_pkt[SINGLE_PKT].group_id; - range->vxlan_gid_inc = 0; -diff --git a/app/pktgen-rate.c b/app/pktgen-rate.c -index 4599f8e..4f5aecb 100644 ---- a/app/pktgen-rate.c -+++ b/app/pktgen-rate.c -@@ -8,6 +8,8 @@ - - #include - -+#include -+#include - #include "lua_config.h" - - #include "pktgen-cmds.h" -diff --git a/app/pktgen-stats.c b/app/pktgen-stats.c -index e7f27ef..7840b08 100644 ---- a/app/pktgen-stats.c -+++ b/app/pktgen-stats.c -@@ -8,6 +8,8 @@ - - #include - -+#include -+#include - #include - #include - -diff --git a/app/pktgen.c b/app/pktgen.c -index 448cc7f..14441f7 100644 ---- a/app/pktgen.c -+++ b/app/pktgen.c -@@ -75,6 +75,7 @@ pktgen_wire_size(port_info_t *info) - } else - size = info->seq_pkt[SINGLE_PKT].pktSize + PKT_OVERHEAD_SIZE; - } -+ size -= (PKT_PREAMBLE_SIZE + INTER_FRAME_GAP + RTE_ETHER_CRC_LEN); - return size; - } - -@@ -297,6 +298,7 @@ pktgen_send_burst(port_info_t *info, uint16_t qid) - struct qstats_s *qstats = &info->qstats[qid]; - uint32_t ret, cnt, tap, rnd, tstamp, i; - int32_t seq_idx; -+ pkt_seq_t *pkt; - - tap = pktgen_tst_port_flags(info, PROCESS_TX_TAP_PKTS); - -@@ -313,6 +315,10 @@ pktgen_send_burst(port_info_t *info, uint16_t qid) - else - seq_idx = SINGLE_PKT; - -+ pkt = &info->seq_pkt[seq_idx]; -+ for (i = 0; i < cnt; i++) -+ rte_pktmbuf_pkt_len(pkts[i]) = pkt->pktSize; -+ - rnd = pktgen_tst_port_flags(info, SEND_RANDOM_PKTS); - tstamp = - pktgen_tst_port_flags(info, (SEND_LATENCY_PKTS | SEND_RATE_PACKETS | SAMPLING_LATENCIES)); -@@ -930,6 +936,10 @@ pktgen_setup_cb(struct rte_mempool *mp, void *opaque, void *obj, unsigned obj_id - pkt_seq_t *pkt; - uint16_t qid, idx; - -+ uint32_t pktsize = (pktgen.flags & MTU9K_SUPPORT_FLAG) ? -+ MAX_PKT_SIZE: -+ (RTE_ETHER_MAX_LEN - RTE_ETHER_CRC_LEN); -+ - info = data->info; - qid = data->qid; - -@@ -958,7 +968,7 @@ pktgen_setup_cb(struct rte_mempool *mp, void *opaque, void *obj, unsigned obj_id - - pktgen_packet_ctor(info, idx, -1); - -- rte_memcpy((uint8_t *)m->buf_addr + m->data_off, (uint8_t *)&pkt->hdr, MAX_PKT_SIZE); -+ rte_memcpy((uint8_t *)m->buf_addr + m->data_off, (uint8_t *)&pkt->hdr, pktsize); - - m->pkt_len = pkt->pktSize; - m->data_len = pkt->pktSize; -@@ -1144,7 +1154,7 @@ pktgen_main_receive(port_info_t *info, uint8_t lid, struct rte_mbuf *pkts_burst[ - { - uint8_t pid; - uint16_t qid, nb_rx; -- capture_t *capture; -+ __rte_unused capture_t *capture; - struct qstats_s *qstats; - int i; - -@@ -1163,6 +1173,10 @@ pktgen_main_receive(port_info_t *info, uint8_t lid, struct rte_mbuf *pkts_burst[ - for (i = 0; i < nb_rx; i++) - qstats->rxbytes += rte_pktmbuf_data_len(pkts_burst[i]); - -+ info->qstats[qid].sizes._64 += nb_rx; -+ rte_pktmbuf_free_bulk(pkts_burst, nb_rx); -+ -+#if 0 - pktgen_recv_tstamp(info, pkts_burst, nb_rx); - - /* packets are not freed in the next call. */ -@@ -1178,6 +1192,7 @@ pktgen_main_receive(port_info_t *info, uint8_t lid, struct rte_mbuf *pkts_burst[ - } - - rte_pktmbuf_free_bulk(pkts_burst, nb_rx); -+#endif - } - - static void -diff --git a/app/pktgen.h b/app/pktgen.h -index 1be8389..4a70a3a 100644 ---- a/app/pktgen.h -+++ b/app/pktgen.h -@@ -239,8 +239,9 @@ enum { - SOCKET0 = 0 /**< Socket ID value for allocation */ - }; - -+#define MAX_9K_SIZE 9018 - #define MIN_PKT_SIZE (pktgen.eth_min_pkt - RTE_ETHER_CRC_LEN) --#define MAX_PKT_SIZE (pktgen.eth_max_pkt - RTE_ETHER_CRC_LEN) -+#define MAX_PKT_SIZE (MAX_9K_SIZE - RTE_ETHER_CRC_LEN) - - typedef struct rte_mbuf rte_mbuf_t; - -@@ -336,7 +337,7 @@ enum { /* Pktgen flags bits */ - FAKE_PORTS_FLAG = (1 << 9), /**< Fake ports enabled */ - BLINK_PORTS_FLAG = (1 << 10), /**< Blink the port leds */ - ENABLE_THEME_FLAG = (1 << 11), /**< Enable theme or color support */ -- -+ MTU9K_SUPPORT_FLAG = (1 << 15), /**< MTU 9K support */ - CONFIG_PAGE_FLAG = (1 << 16), /**< Display the configure page */ - SEQUENCE_PAGE_FLAG = (1 << 17), /**< Display the Packet sequence page */ - RANGE_PAGE_FLAG = (1 << 18), /**< Display the range page */ -diff --git a/lib/cli/cli_map.c b/lib/cli/cli_map.c -index 50e30e1..44b924c 100644 ---- a/lib/cli/cli_map.c -+++ b/lib/cli/cli_map.c -@@ -7,6 +7,7 @@ - #include <_atoip.h> - - #include "cli.h" -+#include "ctype.h" - - int - cli_map_list_search(const char *fmt, char *item, int index) -diff --git a/lib/common/pg_strings.c b/lib/common/pg_strings.c -index a81acf2..3320c43 100644 ---- a/lib/common/pg_strings.c -+++ b/lib/common/pg_strings.c -@@ -3,6 +3,7 @@ - */ - - #include "pg_strings.h" -+#include "ctype.h" - - #define SIZE_OF_PORTLIST (sizeof(portlist_t) * 8) - --- -2.27.0 - diff --git a/QDMA/DPDK/tools/README.txt b/QDMA/DPDK/tools/README.txt deleted file mode 100755 index 2cddef886..000000000 --- a/QDMA/DPDK/tools/README.txt +++ /dev/null @@ -1,45 +0,0 @@ -0001-PKTGEN-22.04.1-Patch-to-add-Jumbo-packet-support.patch -is the patch file over dpdk-pktgen v22.11.0 and -0001-PKTGEN-20.12.0-Patch-to-add-Jumbo-packet-support.patch -is the patch file over dpdk-pktgen v20.12.0 that extends -dpdk-pktgen application to handle packets with packet sizes -more than 1518 bytes and it disables the packet size -classification logic in dpdk-pktgen to remove application -overhead in performance measurement. - -This patch is used for performance testing with dpdk-pktgen application. - - -/*- - * BSD LICENSE - * - * Copyright (c) 2017-2022 Xilinx, Inc. All rights reserved. - * Copyright (c) 2022, Advanced Micro Devices, Inc. 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If this is what you want to do, use the GNU Library General -Public License instead of this License. diff --git a/QDMA/linux-kernel/LICENSE b/QDMA/linux-kernel/LICENSE deleted file mode 100755 index 94e1237bf..000000000 --- a/QDMA/linux-kernel/LICENSE +++ /dev/null @@ -1,30 +0,0 @@ -BSD License - -For Xilinx DMA IP software - -Copyright (c) 2016-2022 Xilinx, Inc. All rights reserved. - -Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - * Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - - * Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - - * Neither the name Xilinx nor the names of its contributors may be used to - endorse or promote products derived from this software without specific - prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR -ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. diff --git a/QDMA/linux-kernel/Makefile b/QDMA/linux-kernel/Makefile deleted file mode 100755 index 53b933d7f..000000000 --- a/QDMA/linux-kernel/Makefile +++ /dev/null @@ -1,184 +0,0 @@ -#/* -# * This file is part of the Xilinx DMA IP Core driver for Linux -# * -# * Copyright (c) 2017-2022, Xilinx, Inc. All rights reserved. -# * Copyright (c) 2022-2023, Advanced Micro Devices, Inc. All rights reserved. -# * -# * This source code is free software; you can redistribute it and/or modify it -# * under the terms and conditions of the GNU General Public License, -# * version 2, as published by the Free Software Foundation. -# * -# * This program is distributed in the hope that it will be useful, but WITHOUT -# * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -# * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for -# * more details. -# * -# * The full GNU General Public License is included in this distribution in -# * the file called "COPYING". -# */ - - -SHELL = /bin/bash - -# -# makefile parameters: -# - KDIR/KSRC/KOBJ=, optional -# - install_path=, override all install directories -# - kernel_install_path=, override install directory for kernel module -# - dev_install_path=, override install directory for development headers -# - apps_install_path=, override install directory for applications -# - docs_install_path=, override install directory for man pages -# -# - enable_cmpt_immediate_data=<0|1> enable immediate data in writeback desc. -# - disable_st_c2h_completion=<0|1> disable completion -# - CROSS_COMPILE=, gcc compiler prefix for architecture eg. aarch64-linux-gnu- - -# Define grep error output to NULL, since -s is not portable. -grep = grep 2>/dev/null - -# Define paths. -srcdir := $(shell pwd) -topdir := $(shell cd $(srcdir)/.. && pwd) -bin_dir := $(srcdir)/bin -apps_dir := $(srcdir)/apps - - -# ALL subdirectories -ALLSUBDIRS := driver -DRIVER_SRC_DIR := driver - -# Exports. -export grep -export srcdir -export topdir -export bin_dir -export verbose - -# evaluate install paths -ifeq ($(install_path),) - # defaults - kernel_install_path ?= $(PREFIX)/lib/modules/$(utsrelease)/updates/kernel/drivers/qdma - dev_install_path ?= /usr/local/include/qdma - apps_install_path ?= /usr/local/sbin - docs_install_path ?= /usr/share/man/man8 -else # bundled install - kernel_install_path ?= $(install_path)/modules - dev_install_path ?= $(install_path)/include/qdma - apps_install_path ?= $(install_path)/bin - docs_install_path ?= $(install_path)/doc -endif - -.PHONY: eval.mak - -.PHONY: default -default: apps driver post - -.PHONY: install -install: install-apps install-dev install-mods - -.PHONY: uninstall -uninstall: uninstall-apps uninstall-dev uninstall-mods - -.PHONY: apps -apps: - @echo "#######################"; - @echo "#### apps ####"; - @echo "#######################"; - $(MAKE) -C apps - -.PHONY: driver -driver: - @echo "#######################"; - @echo "#### Driver ####"; - @echo "#######################"; - $(MAKE) $(MODULE) -C driver modulesymfile=$(srcdir)/driver/src/Module.symvers - -.PHONY: post -post: - @if [ -n "$(post_msg)" ]; then \ - echo -e "\nWARNING:\n $(post_msg)";\ - fi; - -.PHONY: clean -clean: - @echo "#######################"; - @echo "#### apps ####"; - @echo "#######################"; - $(MAKE) -C apps clean; - @for dir in $(ALLSUBDIRS); do \ - echo "#######################";\ - printf "#### %-8s%5s####\n" $$dir;\ - echo "#######################";\ - drvdir=$(shell pwd)/$$dir $(MAKE) -C $$dir clean;\ - done; - @-/bin/rm -f *.symvers eval.mak 2>/dev/null; - @rm -rf $(bin_dir) - -.PHONY: install-mods -install-mods: - @echo "installing kernel modules to /lib/modules/$(shell uname -r)/qdma ..." - @mkdir -p -m 755 /lib/modules/$(shell uname -r)/qdma - @install -v -m 644 $(bin_dir)/*.ko /lib/modules/$(shell uname -r)/qdma - @depmod -a || true - - -.PHONY: install-apps -install-apps: - @echo "installing apps to $(apps_install_path) ..." - @mkdir -p -m 755 $(apps_install_path) - @install -v -m 755 bin/dma-ctl* $(apps_install_path) - @install -v -m 755 bin/dma-xfer* $(apps_install_path) - @install -v -m 755 bin/dma-from-device $(apps_install_path) - @install -v -m 755 bin/dma-to-device $(apps_install_path) - @install -v -m 755 bin/dma-perf $(apps_install_path) - @install -v -m 755 bin/dma-latency $(apps_install_path) - @echo "MAN PAGES:" - @mkdir -p -m 755 $(docs_install_path) - @install -v -m 644 docs/dma-ctl.8.gz $(docs_install_path) - -.PHONY: install-dev -install-dev: - @echo "installing development headers to $(dev_install_path) ..." - @mkdir -p -m 755 $(dev_install_path) - @install -v -m 755 driver/include/* $(dev_install_path) - -.PHONY: uninstall-mods -uninstall-mods: - @echo "Un-installing /lib/modules/$(shell uname -r)/qdma ..." - @/bin/rm -rf /lib/modules/$(shell uname -r)/qdma - @depmod -a - -.PHONY: uninstall-apps -uninstall-apps: - @echo "Un-installing apps under $(apps_install_path) ..." - @/bin/rm -f $(apps_install_path)/dma-ctl - @/bin/rm -f $(apps_install_path)/dma-xfer - @/bin/rm -f $(apps_install_path)/dma-from-device - @/bin/rm -f $(apps_install_path)/dma-to-device - @/bin/rm -f $(apps_install_path)/dma-perf - @/bin/rm -f $(apps_install_path)/dma-latency - -.PHONY: uninstall-dev -uninstall-dev: - @echo "Un-installing development headers under $(dev_install_path) ..." - @/bin/rm -r $(dev_install_path) - -.PHONY: help -help: - @echo "Build Targets:";\ - echo " install - Installs apps and development headers.";\ - echo " uninstall - Uninstalls apps and development headers.";\ - echo " install-mods - Installs drivers.";\ - echo " uninstall-mods - Uninstalls drivers.";\ - echo;\ - echo "Build Options:";\ - echo " KOBJ= - Kernel build (object) path.";\ - echo " KSRC= - Kernel source path.";\ - echo " - Note: When using KSRC or KOBJ, both";\ - echo " variables must be specified.";\ - echo " KDIR= - Kernel build and source path. Shortcut";\ - echo " for KOBJ=KSRC=.";\ - echo " kernel_install_path=";\ - echo " - kernel module install path.";\ - echo " apps_install_path=";\ - echo " - user cli tool install path."; diff --git a/QDMA/linux-kernel/RELEASE b/QDMA/linux-kernel/RELEASE deleted file mode 100755 index 39807d725..000000000 --- a/QDMA/linux-kernel/RELEASE +++ /dev/null @@ -1,208 +0,0 @@ -RELEASE: 2023.2.1 -================= - -This release is validated - - On VCU1525 for QDMA5.0 2022.1 example design - - On VCU1525 for QDMA4.0 2020.2 example design - - On VCU1525 for QDMA3.1 2019.2 example design - - On XCVP1202 for CPM5 2022.1 example design - - On XCVC1902 for CPM4 2022.1 example design - -SUPPORTED FEATURES: -=================== -2018.2 Features ---------------- -- Support for both the AXI4 Memory Mapped(MM) and AXI4 Streaming(ST) Interfaces -- 2048 Queue Sets - - 2048 H2C Descriptor Rings - - 2048 C2H Descriptor Rings - - 2048 C2H Completion Rings -- Supports Polling Mode -- Interrupts - - 2048 MSI-X Vectors - - Up to 8 MSI-X per Function - - Interrupt Aggregation - - User Interrupts - - Error Interrupts -- C2H Stream Completion queue entry coalescing -- Supports SR-IOV with up to 4 Physical Functions(PF) and 252 Virtual Functions(VF) -- Allows only Privileged/Physical functions to program the contexts and registers -- Function Level Reset(FLR) Support -- Mailbox Support -- Descriptor bypass(8, 16, 32 descriptor sizes) -- Descriptor Prefetching -- Asynchronous and Synchronous IO support -- ST H2C to C2H and C2H to H2C loopback support -- Driver configuration through sysfs -- Zero byte transfer support -- Dynamic queue configuration -- Dynamic driver configuration - -2018.3 Features ---------------- -- Auto mode support for PF & VF driver - - MM and ST H2C requests are services in poll mode - - ST C2H is services in Interrupt Aggregation mode -- Support 64B descriptor format in bypass mode -- Support for Completion queue descriptors of 64 bytes size -- Support flexible BAR mapping for QDMA configuration register space -- Indirect programming of FMAP registers -- Support disabling overflow check in completion ring -- Version for SW and HW -- ECC Support -- Flexible interrupt allocation between PF/VF -- Greater than 32 vectors per function -- Legacy Interrupt Support -- VF driver support in direct and indirect interrupt mode - -2019.1 Features ---------------- -- Interrupt support for Mailbox events -- Support Completions in Memory mapped mode -- Interoperability between Linux driver (as PF/VF) and DPDK driver (as PF/VF) -- Driver restructuring to partition QDMA access code such that it can be used across different drivers - -2019.2 Features ---------------- -- Support for PF device removal when its VF devices are active -- Support for Interrupt moderation and adaptive counter threshold -- Support for configurable number of User and Data interrupts -- Added user logic pluggable interfaces for processing the descriptors and completions -- Added new interfaces for updating the Consumer Index and Producer Index - -2020.1 Updates --------------- -- Modified the directory structure for driver source code. -- Application names are changed as "dma-ctl", "dma-perf", "dma-to-device", "dma-from-device" -- Support QDMA4.0 context and register changes -- Common driver to support QDMA3.1 and QDMA4.0 designs -- Support multiple bus numbers on single card -- Updated and validated the example design with marker changes for QDMA4.0 and without marker changes for QDMA3.1 -- Added support for more than 256 functions -- Modified the driver interface to pass the module parameters for more than 256 functions -- Support for Function Level Reset (FLR) of both PFs and VFs. - -2020.1 Patch Updates --------------------- -- Resolved HW errors observed with QDMA4.0 MM only design -- Addressed VF performance issues. - -2020.2 Updates --------------- -- Added support for detailed register dump -- Added support for post processing HW error messages -- Added support for Debug mode and Internal only mode -- Added support for Versal PDI programming through keyhole interface - -2020.2 Patch Updates --------------------- -- Added support for MM Channel Selection and Keyhole feature in dmaperf -- Fixed bug in in driver which caused crash during performance run - -2022.1 Updates --------------- -CPM5 - - Tandem Boot support - - FMAP context dump - - Debug register dump for ST and MM Errors - - Dual Instance support - -2022.1.1 Patch Updates ----------------------- -- Ported changes from pull request https://github.com/Xilinx/dma_ip_drivers/pull/167 to fix XRT build issues while integrating qdma linux driver in to XRT stack - -2022.1.2 Patch Updates ----------------------- -- Added VF 4K queues support for CPM5 design. This feature is applicable only when corresponding RTL support is added. - -2022.1.3 Patch Updates ----------------------- -- Ported changes from pull request https://github.com/Xilinx/dma_ip_drivers/pull/170 to fix coverity issues - -2022.1.4 Patch Updates ----------------------- -- Added support for more than 2K queues for PF/VF -- Added support for Fedora36 - -2022.1.5 Patch Updates ----------------------- -- Added PF/VF 4K queues support for CPM5 design. This feature is applicable only when corresponding RTL support is added. - -2023.1.0 Updates ----------------- -- Updated the queue list command for >2048 Q's. -- Added support to accomodate H2C & C2H Q's offset with fixed intervals for dma-perf application. - -2023.1.1 Updates ----------------- -- Optimized the driver code and HW register settings for performance improvements. - -2023.1.2 Updates ----------------- -- Added support for Fedora37 & CentOS9 distros. - -2023.1.3 Updates ----------------- -- dma-ctl application is updated to append q params during queue start. - -2023.2.0 Updates ----------------- -- Added driver support for CPM4 design. - -2023.2.1 Updates ----------------- -- Added driver support to enable 10 bit tag for CPM5 design. - -KNOWN ISSUES: -============= -- CPM4 Only - - Due to HW PDI limitaion, - - VF is supported in poll mode only. - - VF functionality on VM is not verfied. - -- Observed MMAP failure for applications when device is binded QDMA Linux driver on Fedora37. Fix will be availbale in upcoming release. - -- CPM5 Only - - Performace optimizations are not finalized, Performance report with optimizations will be available in next patch release. - -- All Designs - - In interrupt mode, Sometimes completions are not received when C2H PIDX updates are held for 64 descriptors - - On QDMA4.0 2020.1 design, HW error observed during the probe of the VFs - -DRIVER LIMITATIONS: -=================== -- CPM5 Only - - VF functionality is verified with 240 VF's as per CPM5 HW limitation - -- All Designs - - Driver compilation on Fedora 28 with gcc8.1 results in compilation warnings - - Big endian systems are not supported - - For optimal QDMA streaming performance, packet buffers of the descriptor ring should be aligned to at least 256 bytes. - - FLR is not supported in the Driver for CentOS because linux kernels provided in CentOS versions does not support the driver call back registration for FLR functionality - -- XRT Only - - QDMA: Bypass user BAR check for XRT application - - The existing driver code assmues the presence of the user BAR as indicated in the functional example design. If this user BAR is not detected during the driver probing process, - it results in a failure. However, this check is specific to example design and some customer designs might not contain user BAR. So bypassing the user BAR check to prevent - driver returning error and proceed further. - - - -/* - * This file is part of the Xilinx DMA IP Core driver for Linux - * - * Copyright (c) 2017-2022, Xilinx, Inc. All rights reserved. - * Copyright (c) 2022-2023, Advanced Micro Devices, Inc. All rights reserved. - * - * This source code is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * The full GNU General Public License is included in this distribution in - * the file called "COPYING". - */ diff --git a/QDMA/linux-kernel/apps/Makefile b/QDMA/linux-kernel/apps/Makefile deleted file mode 100755 index 9b7e9875e..000000000 --- a/QDMA/linux-kernel/apps/Makefile +++ /dev/null @@ -1,122 +0,0 @@ -# -#/* -# * This file is part of the QDMA userspace application -# * to enable the user to execute the QDMA functionality -# * -# * Copyright (c) 2018-2022, Xilinx, Inc. All rights reserved. -# * Copyright (c) 2022-2023, Advanced Micro Devices, Inc. All rights reserved. -# * -# * This source code is licensed under BSD-style license (found in the -# * LICENSE file in the root directory of this source tree) -# */ - -SHELL = /bin/bash - -CFLAGS += -g -#CFLAGS += -O2 -fno-inline -Wall -Wstrict-prototypes -CFLAGS += $(EXTRA_FLAGS) - -srcdir := $(shell pwd) -topdir := $(shell cd $(srcdir)/.. && pwd) -bin_dir := $(topdir)/bin -dma-ctl_dir = $(srcdir)/dma-ctl -dma-from-device_dir = $(srcdir)/dma-from-device -dma-to-device_dir = $(srcdir)/dma-to-device -dma-xfer_dir = $(srcdir)/dma-xfer -dma-perf_dir = $(srcdir)/dma-perf -dma-latency_dir = $(srcdir)/dma-latency - -export topdir -export bin_dir - -all: clean apps - -.PHONY: dma-from-device -dma-from-device: - @echo "#############################"; - @echo "#### dma-from-device ####"; - @echo "#############################"; - $(MAKE) -C dma-from-device - @cp -f $(dma-from-device_dir)/dma-from-device $(bin_dir) - -.PHONY: dma-to-device -dma-to-device: - @echo "###########################"; - @echo "#### dma-to-device ####"; - @echo "###########################"; - $(MAKE) -C dma-to-device - @cp -f $(dma-to-device_dir)/dma-to-device $(bin_dir) - -.PHONY: dma-xfer -dma-xfer: - @echo "###########################"; - @echo "#### dma-xfer #####"; - @echo "###########################"; - $(MAKE) -C dma-xfer - @cp -f $(dma-xfer_dir)/dma-xfer $(bin_dir) - -.PHONY: dma-ctl -dma-ctl: - @echo "#######################"; - @echo "#### dma-ctl ######"; - @echo "#######################"; - @mkdir -p -m 755 $(bin_dir) - $(MAKE) -C dma-ctl - @cp -f $(dma-ctl_dir)/dma-ctl $(bin_dir) - - -.PHONY: dma-perf -dma-perf: - @echo "########################"; - @echo "#### dma-perf #######"; - @echo "########################"; - $(MAKE) -C dma-perf - @cp -f $(dma-perf_dir)/dma-perf $(bin_dir) - -.PHONY: dma-latency -dma-latency: - @echo "########################"; - @echo "#### dma-latency #######"; - @echo "########################"; - $(MAKE) -C dma-latency - @cp -f $(dma-latency_dir)/dma-latency $(bin_dir) - -.PHONY: apps -apps: dma-ctl dma-from-device dma-to-device dma-xfer dma-perf dma-latency - - -.PHONY: clean -clean: - @echo "#############################"; - @echo "#### dma-from-device ####"; - @echo "#############################"; - $(MAKE) -C dma-from-device clean; - @echo "#############################"; - @echo "#### dma-to-device ####"; - @echo "#############################"; - $(MAKE) -C dma-to-device clean; - @echo "#############################"; - @echo "#### dma-xfer ####"; - @echo "#############################"; - $(MAKE) -C dma-xfer clean; - @echo "#############################"; - @echo "#### dma-ctl ####"; - @echo "#############################"; - $(MAKE) -C dma-ctl clean; - @echo "#############################"; - @echo "#### dma-perf ####"; - @echo "#############################"; - $(MAKE) -C dma-perf clean; - @echo "#############################"; - @echo "#### dma-latency ####"; - @echo "#############################"; - $(MAKE) -C dma-latency clean; - @rm -f $(bin_dir)/dma-ctl $(bin_dir)/dma-from-device $(bin_dir)/dma-to-device $(bin_dir)/dma-xfer $(bin_dir)/dma-perf $(bin_dir)/dma-latency - @for dir in $(ALLSUBDIRS); do \ - echo "#######################";\ - printf "#### %-8s%5s####\n" $$dir;\ - echo "#######################";\ - drvdir=$(shell pwd)/$$dir $(MAKE) -C $$dir clean;\ - done; - @-/bin/rm -f *.symvers eval.mak 2>/dev/null; - diff --git a/QDMA/linux-kernel/apps/dma-ctl/Makefile b/QDMA/linux-kernel/apps/dma-ctl/Makefile deleted file mode 100755 index ef55091f3..000000000 --- a/QDMA/linux-kernel/apps/dma-ctl/Makefile +++ /dev/null @@ -1,38 +0,0 @@ -# -#/* -# * This file is part of the QDMA userspace application -# * to enable the user to execute the QDMA functionality -# * -# * Copyright (c) 2018-2022, Xilinx, Inc. All rights reserved. -# * Copyright (c) 2022-2023, Advanced Micro Devices, Inc. All rights reserved. -# * -# * This source code is licensed under BSD-style license (found in the -# * LICENSE file in the root directory of this source tree) -# */ - -SHELL = /bin/bash - -CFLAGS += -g -#CFLAGS += -O2 -fno-inline -Wall -Wstrict-prototypes -CFLAGS += -I. -I../include -I../dma-utils -CFLAGS += $(EXTRA_FLAGS) - -DMA-CTL = dma-ctl -DMA-UTILS_OBJS := $(patsubst %.c,%.o,$(wildcard ../dma-utils/*.c)) -DMA-CTL_OBJS := $(patsubst %.c,%.o,$(wildcard *.c)) -DMA-CTL_OBJS += $(DMA-UTILS_OBJS) - -ifneq ($(CROSS_COMPILE_FLAG),) - CC=$(CROSS_COMPILE_FLAG)gcc -endif - -all: clean dma-ctl - -dma-ctl: $(DMA-CTL_OBJS) - $(CC) -pthread -lrt $^ -o $(DMA-CTL) -laio -D_FILE_OFFSET_BITS=64 -D_GNU_SOURCE -D_LARGE_FILE_SOURCE - -%.o: %.c - $(CC) $(CFLAGS) -c -std=c99 -o $@ $< -D_FILE_OFFSET_BITS=64 -D_GNU_SOURCE -D_LARGE_FILE_SOURCE -D_AIO_AIX_SOURCE - -clean: - @rm -f *.o */*.o ../dma-utils/*.o $(DMA-CTL) diff --git a/QDMA/linux-kernel/apps/dma-ctl/cmd_parse.c b/QDMA/linux-kernel/apps/dma-ctl/cmd_parse.c deleted file mode 100755 index 18ecd7b68..000000000 --- a/QDMA/linux-kernel/apps/dma-ctl/cmd_parse.c +++ /dev/null @@ -1,1259 +0,0 @@ -/* - * This file is part of the QDMA userspace application - * to enable the user to execute the QDMA functionality - * - * Copyright (c) 2018-2022, Xilinx, Inc. All rights reserved. - * Copyright (c) 2022-2023, Advanced Micro Devices, Inc. All rights reserved. - * - * This source code is licensed under BSD-style license (found in the - * LICENSE file in the root directory of this source tree) - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include "cmd_parse.h" -#include "qdma_nl.h" -#include "version.h" - -static int read_range(int argc, char *argv[], int i, unsigned int *v1, - unsigned int *v2); - -static const char *progname; -#define DESC_SIZE_64B 3 - -#define Q_ADD_ATTR_IGNORE_MASK ~((1 << QPARM_IDX) | \ - (1 << QPARM_MODE) | \ - (1 << QPARM_DIR)) -#define Q_START_ATTR_IGNORE_MASK ((1 << QPARM_MODE) | \ - (1 << QPARM_DESC) | \ - (1 << QPARM_CMPT)) -#define Q_STOP_ATTR_IGNORE_MASK ~((1 << QPARM_IDX) | \ - (1 << QPARM_DIR)) -#define Q_DEL_ATTR_IGNORE_MASK ~((1 << QPARM_IDX) | \ - (1 << QPARM_DIR)) -#define Q_DUMP_ATTR_IGNORE_MASK ~((1 << QPARM_IDX) | \ - (1 << QPARM_DIR) | \ - (1 << QPARM_DESC) | \ - (1 << QPARM_CMPT)) -#define Q_DUMP_PKT_ATTR_IGNORE_MASK ~((1 << QPARM_IDX) | \ - (1 << QPARM_DIR)) -#define Q_H2C_ATTR_IGNORE_MASK ((1 << QPARM_C2H_BUFSZ_IDX) | \ - (1 << QPARM_CMPT_TMR_IDX) | \ - (1 << QPARM_CMPT_CNTR_IDX) | \ - (1 << QPARM_CMPT_TRIG_MODE) | \ - (1 << QPARM_CMPTSZ)) -#define Q_CMPT_READ_ATTR_IGNORE_MASK ~((1 << QPARM_IDX) | \ - (1 << QPARM_DIR)) -#define Q_ADD_FLAG_IGNORE_MASK ~(XNL_F_QMODE_ST | \ - XNL_F_QMODE_MM | \ - XNL_F_QDIR_BOTH | XNL_F_Q_CMPL) -#define Q_START_FLAG_IGNORE_MASK (XNL_F_QMODE_ST | \ - XNL_F_QMODE_MM) -#define Q_STOP_FLAG_IGNORE_MASK ~(XNL_F_QMODE_ST | \ - XNL_F_QMODE_MM | \ - XNL_F_QDIR_BOTH | XNL_F_Q_CMPL) -#define Q_DEL_FLAG_IGNORE_MASK ~(XNL_F_QMODE_ST | \ - XNL_F_QMODE_MM | \ - XNL_F_QDIR_BOTH | XNL_F_Q_CMPL) -#define Q_DUMP_FLAG_IGNORE_MASK ~(XNL_F_QMODE_ST | \ - XNL_F_QMODE_MM | \ - XNL_F_QDIR_BOTH | XNL_F_Q_CMPL) -#define Q_DUMP_PKT_FLAG_IGNORE_MASK ~(XNL_F_QMODE_ST | \ - XNL_F_QMODE_MM | \ - XNL_F_QDIR_C2H) -#define Q_H2C_FLAG_IGNORE_MASK (XNL_F_C2H_CMPL_INTR_EN | \ - XNL_F_CMPL_UDD_EN) - -#define Q_CMPT_READ_FLAG_IGNORE_MASK ~(XNL_F_QMODE_ST | \ - XNL_F_QMODE_MM | \ - XNL_F_QDIR_BOTH | XNL_F_Q_CMPL) - -#ifdef ERR_DEBUG -char *qdma_err_str[qdma_errs] = { - "err_ram_sbe", - "err_ram_dbe", - "err_dsc", - "err_trq", - "err_h2c_mm_0", - "err_h2c_mm_1", - "err_c2h_mm_0", - "err_c2h_mm_1", - "err_c2h_st", - "ind_ctxt_cmd_err", - "err_bdg", - "err_h2c_st", - "poison", - "ur_ca", - "param", - "addr", - "tag", - "flr", - "timeout", - "dat_poison", - "flr_cancel", - "dma", - "dsc", - "rq_cancel", - "dbe", - "sbe", - "unmapped", - "qid_range", - "vf_access_err", - "tcp_timeout", - "mty_mismatch", - "len_mismatch", - "qid_mismatch", - "desc_rsp_err", - "eng_wpl_data_par_err", - "msi_int_fail", - "err_desc_cnt", - "portid_ctxt_mismatch", - "portid_byp_in_mismatch", - "cmpt_inv_q_err", - "cmpt_qfull_err", - "cmpt_cidx_err", - "cmpt_prty_err", - "fatal_mty_mismatch", - "fatal_len_mismatch", - "fatal_qid_mismatch", - "timer_fifo_ram_rdbe", - "fatal_eng_wpl_data_par_err", - "pfch_II_ram_rdbe", - "cmpt_ctxt_ram_rdbe", - "pfch_ctxt_ram_rdbe", - "desc_req_fifo_ram_rdbe", - "int_ctxt_ram_rdbe", - "cmpt_coal_data_ram_rdbe", - "tuser_fifo_ram_rdbe", - "qid_fifo_ram_rdbe", - "payload_fifo_ram_rdbe", - "wpl_data_par_err", - "zero_len_desc_err", - "csi_mop_err", - "no_dma_dsc_err", - "sb_mi_h2c0_dat", - "sb_mi_c2h0_dat", - "sb_h2c_rd_brg_dat", - "sb_h2c_wr_brg_dat", - "sb_c2h_rd_brg_dat", - "sb_c2h_wr_brg_dat", - "sb_func_map", - "sb_dsc_hw_ctxt", - "sb_dsc_crd_rcv", - "sb_dsc_sw_ctxt", - "sb_dsc_cpli", - "sb_dsc_cpld", - "sb_pasid_ctxt_ram", - "sb_timer_fifo_ram", - "sb_payload_fifo_ram", - "sb_qid_fifo_ram", - "sb_tuser_fifo_ram", - "sb_wrb_coal_data_ram", - "sb_int_qid2vec_ram", - "sb_int_ctxt_ram", - "sb_desc_req_fifo_ram", - "sb_pfch_ctxt_ram", - "sb_wrb_ctxt_ram", - "sb_pfch_ll_ram", - "sb_h2c_pend_fifo", - "db_mi_h2c0_dat", - "db_mi_c2h0_dat", - "db_h2c_rd_brg_dat", - "db_h2c_wr_brg_dat", - "db_c2h_rd_brg_dat", - "db_c2h_wr_brg_dat", - "db_func_map", - "db_dsc_hw_ctxt", - "db_dsc_crd_rcv", - "db_dsc_sw_ctxt", - "db_dsc_cpli", - "db_dsc_cpld", - "db_pasid_ctxt_ram", - "db_timer_fifo_ram", - "db_payload_fifo_ram", - "db_qid_fifo_ram", - "db_tuser_fifo_ram", - "db_wrb_coal_data_ram", - "db_int_qid2vec_ram", - "db_int_ctxt_ram", - "db_desc_req_fifo_ram", - "db_pfch_ctxt_ram", - "db_wrb_ctxt_ram", - "db_pfch_ll_ram", - "db_h2c_pend_fifo", -}; -#endif - -static void __attribute__((noreturn)) usage(FILE *fp) -{ - fprintf(fp, "Usage: %s [dev|qdma[vf]] [operation] \n", progname); - fprintf(fp, "\tdev [operation]: system wide FPGA operations\n"); - fprintf(fp, - "\t\tlist list all qdma functions\n"); - fprintf(fp, - "\tqdma[N] [operation]: per QDMA FPGA operations\n"); - fprintf(fp, - "\t\tcap.... lists the Hardware and Software version and capabilities\n" - "\t\tstat statistics of qdma[N] device\n" - "\t\tstat clear clear all statistics data of qdma[N} device\n" - "\t\tglobal_csr dump the Global CSR of qdma[N} device\n" - "\t\tq list - List queues from idx \n" - "\t\tq add idx [mode ] [dir ] - add a queue\n" - "\t\t *mode default to mm\n" - "\t\t *dir default to h2c\n" - "\t\tq add list [mode ] [dir ] - add multiple queues at once\n" - "\t\tq start idx [dir ] [idx_ringsz <0:15>] [idx_bufsz <0:15>] [idx_tmr <0:15>]\n" - " [idx_cntr <0:15>] [trigmode ] [cmptsz <0|1|2|3>] [sw_desc_sz <3>]\n" - " [mm_chn <0|1>] [desc_bypass_en] [pfetch_en] [pfetch_bypass_en] [dis_cmpl_status]\n" - " [dis_cmpl_status_acc] [dis_cmpl_status_pend_chk] [c2h_udd_en]\n" - " [cmpl_ovf_dis] [fetch_credit ] [dis_cmpl_status] [c2h_cmpl_intr_en] [aperture_sz ]- start a single queue\n" - "\t\tq start list [dir ] [idx_bufsz <0:15>] [idx_tmr <0:15>]\n" - " [idx_cntr <0:15>] [trigmode ] [cmptsz <0|1|2|3>] [sw_desc_sz <3>]\n" - " [mm_chn <0|1>] [desc_bypass_en] [pfetch_en] [pfetch_bypass_en] [dis_cmpl_status]\n" - " [dis_cmpl_status_acc] [dis_cmpl_status_pend_chk] [cmpl_ovf_dis]\n" - " [fetch_credit ] [dis_cmpl_status] [c2h_cmpl_intr_en] [aperture_sz ]- start multiple queues at once\n" - "\t\tq stop idx dir [] - stop a single queue\n" - "\t\tq stop list dir [] - stop list of queues at once\n" - "\t\tq del idx dir [] - delete a queue\n" - "\t\tq del list dir [] - delete list of queues at once\n" - "\t\tq dump idx dir [] dump queue param\n" - "\t\tq dump list dir [] - dump queue param\n" - "\t\tq dump idx dir [] desc - dump desc ring entry x ~ y\n" - "\t\tq dump list dir [] desc - dump desc ring entry x ~ y\n" - "\t\tq dump idx dir [] cmpt - dump cmpt ring entry x ~ y\n" - "\t\tq dump list dir [] cmpt - dump cmpt ring entry x ~ y\n" - "\t\tq cmpt_read idx - read the completion data\n" -#ifdef ERR_DEBUG - "\t\tq err help - help to induce errors \n" - "\t\tq err idx [>] dir <[h2c|c2h|bi]> - induce errors on q idx \n" -#endif - ); - fprintf(fp, - "\t\treg dump [dmap ] - register dump. Only dump dmap registers if dmap is specified.\n" - "\t\t specify dmap range to dump: Q=queue, N=num of queues\n" - "\t\treg read [bar ] - read a register\n" - "\t\treg write [bar ] - write a register\n" - "\t\treg info bar [num_regs ] - dump detailed fields information of a register\n"); - fprintf(fp, - "\t\tintring dump vector - interrupt ring dump for vector number \n" - "\t\t for intrrupt entries : --- \n"); -#ifdef TANDEM_BOOT_SUPPORTED - fprintf(fp, "\t\ten_st - enable streamig \n"); -#endif - exit(fp == stderr ? 1 : 0); -} - -static int arg_read_int(char *s, uint32_t *v) -{ - char *p; - - *v = strtoul(s, &p, 0); - if (*p) { - warnx("bad parameter \"%s\", integer expected", s); - return -EINVAL; - } - return 0; -} - -static int parse_ifname(char *name, struct xcmd_info *xcmd) -{ - int len = strlen(name); - int pos, i; - uint32_t v; - char *p; - - /* qdmaN of qdmavfN*/ - if (len > 11) { - warnx("interface name %s too long, expect qdma.\n", name); - return -EINVAL; - } - if (strncmp(name, "qdma", 4)) { - warnx("bad interface name %s, expect qdma.\n", name); - return -EINVAL; - } - if (name[4] == 'v' && name[5] == 'f') { - xcmd->vf = 1; - pos = 6; - } else { - xcmd->vf = 0; - pos = 4; - } - for (i = pos; i < len; i++) { - if (!isxdigit(name[i])) { - warnx("%s unexpected , %d.\n", name, i); - return -EINVAL; - } - } - - v = strtoul(name + pos, &p, 16); - if (*p) { - warnx("bad parameter \"%s\", integer expected", name + pos); - return -EINVAL; - } - - xcmd->if_bdf = v; - return 0; -} - -#define get_next_arg(argc, argv, i) \ - if (++(*i) >= argc) { \ - warnx("%s missing parameter after \"%s\".\n", __FUNCTION__, argv[--(*i)]); \ - return -EINVAL; \ - } - -#define __get_next_arg(argc, argv, i) \ - if (++i >= argc) { \ - warnx("%s missing parameter aft \"%s\".\n", __FUNCTION__, argv[--i]); \ - return -EINVAL; \ - } - -static int next_arg_read_int(int argc, char *argv[], int *i, unsigned int *v) -{ - get_next_arg(argc, argv, i); - return arg_read_int(argv[*i], v); -} - -static int validate_regcmd(enum xnl_op_t qcmd, struct xcmd_reg *regcmd) -{ - int invalid = 0; - - switch(qcmd) { - case XNL_CMD_REG_DUMP: - break; - case XNL_CMD_REG_RD: - case XNL_CMD_REG_INFO_READ: - case XNL_CMD_REG_WRT: - if ((regcmd->bar != 0) && (regcmd->bar != 2) && (regcmd->bar != 4)) { - printf("dmactl: bar %u number out of range\n", - regcmd->bar); - invalid = -EINVAL; - break; - } - break; - default: - invalid = -EINVAL; - break; - } - - return invalid; -} - -static int parse_reg_cmd(int argc, char *argv[], int i, struct xcmd_info *xcmd) -{ - struct xcmd_reg *regcmd = &xcmd->req.reg; - int rv; - int args_valid; - - /* - * reg dump - * reg read [bar ] - * reg write [bar ] - */ - - memset(regcmd, 0, sizeof(struct xcmd_reg)); - if (!strcmp(argv[i], "dump")) { - xcmd->op = XNL_CMD_REG_DUMP; - i++; - - if (i < argc) { - if (!strcmp(argv[i], "dmap")) { - get_next_arg(argc, argv, &i); - rv = read_range(argc, argv, i, ®cmd->range_start, - ®cmd->range_end); - if (rv < 0) - return rv; - i = rv; - } - } - - } else if (!strcmp(argv[i], "read")) { - xcmd->op = XNL_CMD_REG_RD; - - get_next_arg(argc, argv, &i); - if (!strcmp(argv[i], "bar")) { - rv = next_arg_read_int(argc, argv, &i, ®cmd->bar); - if (rv < 0) - return rv; - regcmd->sflags |= XCMD_REG_F_BAR_SET; - get_next_arg(argc, argv, &i); - } - rv = arg_read_int(argv[i], ®cmd->reg); - if (rv < 0) - return rv; - regcmd->sflags |= XCMD_REG_F_REG_SET; - - i++; - - } else if (!strcmp(argv[i], "write")) { - xcmd->op = XNL_CMD_REG_WRT; - - get_next_arg(argc, argv, &i); - if (!strcmp(argv[i], "bar")) { - rv = next_arg_read_int(argc, argv, &i, ®cmd->bar); - if (rv < 0) - return rv; - regcmd->sflags |= XCMD_REG_F_BAR_SET; - get_next_arg(argc, argv, &i); - } - rv = arg_read_int(argv[i], &xcmd->req.reg.reg); - if (rv < 0) - return rv; - regcmd->sflags |= XCMD_REG_F_REG_SET; - - rv = next_arg_read_int(argc, argv, &i, &xcmd->req.reg.val); - if (rv < 0) - return rv; - regcmd->sflags |= XCMD_REG_F_VAL_SET; - - i++; - } else if (!strcmp(argv[i], "info")) { - xcmd->op = XNL_CMD_REG_INFO_READ; - get_next_arg(argc, argv, &i); - if (!strcmp(argv[i], "bar")) { - rv = next_arg_read_int(argc, argv, &i, ®cmd->bar); - if (rv < 0) - return rv; - regcmd->sflags |= XCMD_REG_F_BAR_SET; - get_next_arg(argc, argv, &i); - } - rv = arg_read_int(argv[i], &xcmd->req.reg.reg); - if (rv < 0) - return rv; - regcmd->sflags |= XCMD_REG_F_REG_SET; - i++; - - if (i < argc) { - if (!strcmp(argv[i], "num_regs")) { - rv = next_arg_read_int(argc, argv, &i, ®cmd->range_end); - if (rv < 0) - return rv; - } - } else - regcmd->range_end = 1; - i++; - } - - args_valid = validate_regcmd(xcmd->op, regcmd); - - return (args_valid == 0) ? i : args_valid; -} - -static int read_range(int argc, char *argv[], int i, unsigned int *v1, - unsigned int *v2) -{ - int rv; - - /* range */ - rv = arg_read_int(argv[i], v1); - if (rv < 0) - return rv; - - get_next_arg(argc, argv, &i); - rv = arg_read_int(argv[i], v2); - if (rv < 0) - return rv; - - if (v2 < v1) { - warnx("invalid range %u ~ %u.\n", *v1, *v2); - return -EINVAL; - } - - return ++i; -} - -/** 1:1 mapping to entries in q_parm_type of nl_user.h */ -static char *qparm_type_str[QPARM_MAX] = { - "idx", - "mode", - "dir", - "desc", - "cmpt", - "cmptsz", - "sw_desc_sz", - "idx_ringsz", - "idx_bufsz", - "idx_tmr", - "idx_cntr", - "trigmode", -#ifdef ERR_DEBUG - "err_no" -#endif -}; - -/** 1:1 mapping for flags from qdma_nl.h #defines flags */ -static char *qflag_type_str[MAX_QFLAGS] = { - "mode", - "mode", - "dir", - "dir", - "pfetch_en", - "bypass", - "fetch_credit", - "fetch_credit", - "dis_cmpl_status_acc", - "dis_cmpl_status", - "dis_cmpl_status_pend_chk", - "dis_cmpl_status", - "c2h_cmpl_intr_en", - "c2h_udd_en", - "pftch_bypass_en", - "cmpl_ovf_dis", - "en_mm_cmpl" -}; - -#define IS_SIZE_IDX_VALID(x) (x < 16) - -static void print_ignored_params(uint32_t ignore_mask, uint8_t isflag, - char *ignored_dir) -{ - unsigned int maxcount = isflag ? MAX_QFLAGS : QPARM_MAX; - char **qparam = isflag ? qflag_type_str : qparm_type_str; - char *pdesc = isflag ? "flag" : "attr"; - unsigned int i; - - for (i = 0; ignore_mask && (i < maxcount); i++) { - if (ignore_mask & 0x01) { - if(ignored_dir == NULL) - warnx("Warn: Ignoring %s: %s", pdesc, qparam[i]); - else - warnx("Info: Ignoring %s \"%s\" for %s direction only", pdesc, qparam[i], - ignored_dir); - } - ignore_mask >>= 1; - } -} - - -static int validate_qcmd(enum xnl_op_t qcmd, struct xcmd_q_parm *qparm) -{ - int invalid = 0; - switch(qcmd) { - case XNL_CMD_Q_LIST: - if (qparm->sflags) - warnx("Warn: Ignoring all attributes and flags"); - break; - case XNL_CMD_Q_ADD: - print_ignored_params(qparm->sflags & - Q_ADD_ATTR_IGNORE_MASK, 0, NULL); - print_ignored_params(qparm->flags & - Q_ADD_FLAG_IGNORE_MASK, 1, NULL); - break; - case XNL_CMD_Q_START: - if (!IS_SIZE_IDX_VALID(qparm->c2h_bufsz_idx)) { - warnx("dmactl: C2H Buf index out of range"); - invalid = -EINVAL; - } - if (!IS_SIZE_IDX_VALID(qparm->qrngsz_idx)) { - warnx("dmactl: Queue ring size index out of range"); - invalid = -EINVAL; - } - if (!IS_SIZE_IDX_VALID(qparm->cmpt_cntr_idx)) { - warnx("dmactl: CMPT counter index out of range"); - invalid = -EINVAL; - } - if (!IS_SIZE_IDX_VALID(qparm->cmpt_tmr_idx)) { - warnx("dmactl: CMPT timer index out of range"); - invalid = -EINVAL; - } - if (qparm->cmpt_entry_size >= - XNL_ST_C2H_NUM_CMPT_DESC_SIZES) { - warnx("dmactl: CMPT entry size out of range"); - invalid = -EINVAL; - } - if (qparm->flags & XNL_F_PFETCH_BYPASS_EN) { - if (!(qparm->flags & XNL_F_DESC_BYPASS_EN)) { - printf("Error:desc bypass enable must be enabled for configuring pfetch bypass enable\n"); - invalid = -EINVAL; - break; - } - } - if (qparm->flags & XNL_F_CMPL_UDD_EN) { - if (!(qparm->sflags & (1 << QPARM_CMPTSZ))) { - printf("Error: cmptsz required for enabling c2h udd packet\n"); - invalid = -EINVAL; - break; - } - } - - print_ignored_params(qparm->sflags & - Q_START_ATTR_IGNORE_MASK, - 0, NULL); - - if ((qparm->sflags & (1 << QPARM_SW_DESC_SZ))) { - /* TODO: in 2018.3 RTL1 , only 64B sw_desc_size is supported */ - if (qparm->sw_desc_sz != DESC_SIZE_64B) { - warnx("dmactl: desc size out of range"); - invalid = -EINVAL; - } - } - break; - case XNL_CMD_Q_STOP: - print_ignored_params(qparm->sflags & - Q_STOP_ATTR_IGNORE_MASK, 0, NULL); - print_ignored_params(qparm->flags & - Q_STOP_FLAG_IGNORE_MASK, 1, NULL); - break; - case XNL_CMD_Q_DEL: - print_ignored_params(qparm->sflags & - Q_DEL_ATTR_IGNORE_MASK, 0, NULL); - print_ignored_params(qparm->flags & - Q_DEL_FLAG_IGNORE_MASK, 1, NULL); - break; - case XNL_CMD_Q_CMPT: - case XNL_CMD_Q_DUMP: - if ((qparm->sflags & ((1 << QPARM_DESC) | - (1 << QPARM_CMPT))) == ((1 << QPARM_DESC) | - (1 << QPARM_CMPT))) { - invalid = -EINVAL; - printf("Error: Both desc and cmpt attr cannot be taken for Q DUMP\n"); - break; - } - case XNL_CMD_Q_DESC: - print_ignored_params(qparm->sflags & - Q_DUMP_ATTR_IGNORE_MASK, 0, NULL); - print_ignored_params(qparm->flags & - Q_DUMP_FLAG_IGNORE_MASK, 1, NULL); - break; - case XNL_CMD_Q_RX_PKT: - if (qparm->flags & XNL_F_QDIR_H2C) { - printf("Rx dump packet is st c2h only command\n"); - invalid = -EINVAL; - break; - } - print_ignored_params(qparm->sflags & - Q_DUMP_PKT_ATTR_IGNORE_MASK, 0, NULL); - print_ignored_params(qparm->flags & - Q_DUMP_PKT_FLAG_IGNORE_MASK, 1, NULL); - break; - case XNL_CMD_Q_CMPT_READ: - print_ignored_params(qparm->sflags & - Q_CMPT_READ_ATTR_IGNORE_MASK, 0, NULL); - print_ignored_params(qparm->flags & - Q_CMPT_READ_FLAG_IGNORE_MASK, 1, NULL); - break; -#ifdef ERR_DEBUG - case XNL_CMD_Q_ERR_INDUCE: - break; -#endif - default: - invalid = -EINVAL; - break; - } - - return invalid; -} - -#ifdef ERR_DEBUG -static unsigned char get_err_num(char *err) -{ - uint32_t i; - - for (i = 0; i < qdma_errs; i++) - if (!strcmp(err, qdma_err_str[i])) - break; - - return i; -} -#endif - -static int read_qparm(int argc, char *argv[], int i, struct xcmd_q_parm *qparm, - unsigned int f_arg_required) -{ - int rv; - uint32_t v1; - unsigned int f_arg_set = 0;; - unsigned int mask; - - /* - * idx - * list - * ringsz - * bufsz - * mode - * dir - * cdev <0|1> - * bypass <0|1> - * desc - * cmpt - * cmptsz <0|1|2|3> - */ - - qparm->idx = XNL_QIDX_INVALID; - - while (i < argc) { -#ifdef ERR_DEBUG - if ((f_arg_required & (1 << QPARAM_ERR_NO)) && - (!strcmp(argv[i], "help"))) { - uint32_t j; - - fprintf(stdout, "q err idx [list of >] dir <[h2c|c2h|bi]>\n"); - fprintf(stdout, "Supported errors:\n"); - for (j = 0; j < qdma_errs; j++) - fprintf(stdout, "\t%s\n", qdma_err_str[j]); - - return argc; - } -#endif - if (!strcmp(argv[i], "idx")) { - rv = next_arg_read_int(argc, argv, &i, &v1); - if (rv < 0) - return rv; - - qparm->idx = v1; - f_arg_set |= 1 << QPARM_IDX; - qparm->num_q = 1; -#ifdef ERR_DEBUG - if (f_arg_required & (1 << QPARAM_ERR_NO)) { - unsigned char err_no; - - get_next_arg(argc, argv, &i); - - err_no = get_err_num(argv[i]); - if (err_no >= qdma_errs) { - fprintf(stderr, - "unknown err %s.\n", - argv[i]); - return -EINVAL; - } - - rv = next_arg_read_int(argc, argv, &i, &v1); - if (rv < 0) - return rv; - - qparm->err.en = v1 ? 1 : 0; - qparm->err.err_no = err_no; - printf("%s-%u: err_no/en: %u/%u\n", argv[i], qparm->idx, qparm->err.err_no, qparm->err.en); - i++; - f_arg_set |= 1 << QPARAM_ERR_NO; - } else - i++; -#else - i++; -#endif - - } else if (!strcmp(argv[i], "list")) { - rv = next_arg_read_int(argc, argv, &i, &v1); - if (rv < 0) - return rv; - - qparm->idx = v1; - f_arg_set |= 1 << QPARM_IDX; - rv = next_arg_read_int(argc, argv, &i, &v1); - if (rv < 0) - return rv; - - qparm->num_q = v1; - i++; - - } else if (!strcmp(argv[i], "mode")) { - get_next_arg(argc, argv, (&i)); - - if (!strcmp(argv[i], "mm")) { - qparm->flags |= XNL_F_QMODE_MM; - } else if (!strcmp(argv[i], "st")) { - qparm->flags |= XNL_F_QMODE_ST; - } else { - warnx("unknown q mode %s.\n", argv[i]); - return -EINVAL; - } - f_arg_set |= 1 << QPARM_MODE; - i++; - - } else if (!strcmp(argv[i], "dir")) { - get_next_arg(argc, argv, (&i)); - - if (!strcmp(argv[i], "h2c")) { - qparm->flags |= XNL_F_QDIR_H2C; - } else if (!strcmp(argv[i], "c2h")) { - qparm->flags |= XNL_F_QDIR_C2H; - } else if (!strcmp(argv[i], "bi")) { - qparm->flags |= XNL_F_QDIR_BOTH; - } else if (!strcmp(argv[i], "cmpt")) { - qparm->flags |= XNL_F_Q_CMPL; - } else { - warnx("unknown q dir %s.\n", argv[i]); - return -EINVAL; - } - f_arg_set |= 1 << QPARM_DIR; - i++; - } else if (!strcmp(argv[i], "idx_bufsz")) { - rv = next_arg_read_int(argc, argv, &i, &v1); - if (rv < 0) - return rv; - - qparm->c2h_bufsz_idx = v1; - - f_arg_set |= 1 << QPARM_C2H_BUFSZ_IDX; - i++; - - } else if (!strcmp(argv[i], "idx_ringsz")) { - rv = next_arg_read_int(argc, argv, &i, &v1); - if (rv < 0) - return rv; - - qparm->qrngsz_idx = v1; - f_arg_set |= 1 << QPARM_RNGSZ_IDX; - i++; - } else if (!strcmp(argv[i], "idx_tmr")) { - rv = next_arg_read_int(argc, argv, &i, &v1); - if (rv < 0) - return rv; - - qparm->cmpt_tmr_idx = v1; - f_arg_set |= 1 << QPARM_CMPT_TMR_IDX; - i++; - } else if (!strcmp(argv[i], "idx_cntr")) { - rv = next_arg_read_int(argc, argv, &i, &v1); - if (rv < 0) - return rv; - - qparm->cmpt_cntr_idx = v1; - f_arg_set |= 1 << QPARM_CMPT_CNTR_IDX; - i++; - } else if (!strcmp(argv[i], "mm_chn")) { - rv = next_arg_read_int(argc, argv, &i, &v1); - if (rv < 0) - return rv; - - qparm->mm_channel = v1; - f_arg_set |= 1 << QPARM_MM_CHANNEL; - i++; - } else if (!strcmp(argv[i], "cmpl_ovf_dis")) { - qparm->flags |= XNL_F_CMPT_OVF_CHK_DIS; - i++; - } else if (!strcmp(argv[i], "trigmode")) { - get_next_arg(argc, argv, (&i)); - - if (!strcmp(argv[i], "every")) { - v1 = 1; - } else if (!strcmp(argv[i], "usr_cnt")) { - v1 = 2; - } else if (!strcmp(argv[i], "usr")) { - v1 = 3; - } else if (!strcmp(argv[i], "usr_tmr")) { - v1=4; - } else if (!strcmp(argv[i], "cntr_tmr")) { - v1=5; - } else if (!strcmp(argv[i], "dis")) { - v1 = 0; - } else { - warnx("unknown q trigmode %s.\n", argv[i]); - return -EINVAL; - } - - qparm->cmpt_trig_mode = v1; - f_arg_set |= 1 << QPARM_CMPT_TRIG_MODE; - i++; - } else if (!strcmp(argv[i], "desc")) { - get_next_arg(argc, argv, &i); - rv = read_range(argc, argv, i, &qparm->range_start, - &qparm->range_end); - if (rv < 0) - return rv; - i = rv; - f_arg_set |= 1 << QPARM_DESC; - - } else if (!strcmp(argv[i], "cmpt")) { - get_next_arg(argc, argv, &i); - rv = read_range(argc, argv, i, &qparm->range_start, - &qparm->range_end); - if (rv < 0) - return rv; - i = rv; - f_arg_set |= 1 << QPARM_CMPT; - } else if (!strcmp(argv[i], "cmptsz")) { - get_next_arg(argc, argv, &i); - sscanf(argv[i], "%hhu", &qparm->cmpt_entry_size); - f_arg_set |= 1 << QPARM_CMPTSZ; - i++; - } else if (!strcmp(argv[i], "sw_desc_sz")) { - get_next_arg(argc, argv, &i); - sscanf(argv[i], "%hhu", &qparm->sw_desc_sz); - f_arg_set |= 1 << QPARM_SW_DESC_SZ; - i++; - } else if (!strcmp(argv[i], "pfetch_en")) { - qparm->flags |= XNL_F_PFETCH_EN; - i++; - } else if (!strcmp(argv[i], "ping_pong_en")) { - f_arg_set |= 1 << QPARM_PING_PONG_EN; - i++; - } else if (!strcmp(argv[i], "aperture_sz")) { - rv = next_arg_read_int(argc, argv, &i, &v1); - if (rv < 0) - return rv; - - if(((v1 != 0) && ((v1 &(v1 - 1))))) { - warnx("Error: Keyhole aperture should be a size of 2\n"); - return -EINVAL; - } - - f_arg_set |= 1 << QPARM_KEYHOLE_EN; - qparm->aperture_sz = v1; - i++; - } else if (!strcmp(argv[i], "pfetch_bypass_en")) { - qparm->flags |= XNL_F_PFETCH_BYPASS_EN; - i++; - } else if (!strcmp(argv[i], "desc_bypass_en")) { - qparm->flags |= XNL_F_DESC_BYPASS_EN; - i++; - } else if (!strcmp(argv[i], "c2h_cmpl_intr_en")) { - qparm->flags |= XNL_F_C2H_CMPL_INTR_EN; - i++; - } else if (!strcmp(argv[i], "dis_cmpl_status")) { - qparm->flags &= ~XNL_F_CMPL_STATUS_EN; - i++; - } else if (!strcmp(argv[i], "dis_cmpl_status_acc")) { - qparm->flags &= ~XNL_F_CMPL_STATUS_ACC_EN; - i++; - } else if (!strcmp(argv[i], "dis_cmpl_status_pend_chk")) { - qparm->flags &= ~XNL_F_CMPL_STATUS_PEND_CHK; - i++; - } else if (!strcmp(argv[i], "fetch_credit")) { - get_next_arg(argc, argv, (&i)); - if (!strcmp(argv[i], "h2c")) { - if (((qparm->flags & XNL_F_QDIR_H2C) == XNL_F_QDIR_H2C) - || ((qparm->flags & XNL_F_QDIR_BOTH) == XNL_F_QDIR_BOTH)) - v1 = Q_ENABLE_H2C_FETCH_CREDIT; - else { - warnx("Invalid Fetch credit option,%s", - "Q direction mismatch, not H2C dir\n"); - return -EINVAL; - } - } else if (!strcmp(argv[i], "c2h")) { - if (((qparm->flags & XNL_F_QDIR_C2H) == XNL_F_QDIR_C2H) - || ((qparm->flags & XNL_F_QDIR_BOTH) == XNL_F_QDIR_BOTH)) - v1 = Q_ENABLE_C2H_FETCH_CREDIT; - else { - warnx("Invalid Fetch credit option,%s", - "Q direction mismatch, not C2H dir\n"); - return -EINVAL; - } - } else if (!strcmp(argv[i], "bi")) { - if (((qparm->flags & XNL_F_QDIR_BOTH) == XNL_F_QDIR_BOTH)) - v1 = Q_ENABLE_H2C_C2H_FETCH_CREDIT; - else { - warnx("Invalid Fetch credit option, %s", - "Q direction mismatch, not BI dir\n"); - return -EINVAL; - } - } else if (!strcmp(argv[i], "none")){ - v1 = Q_DISABLE_FETCH_CREDIT; - } else { - warnx("unknown fetch_credit option %s.\n", argv[i]); - return -EINVAL; - } - qparm->fetch_credit = v1; - i++; - } else if (!strcmp(argv[i], "c2h_udd_en")) { - qparm->flags |= XNL_F_CMPL_UDD_EN; - i++; - } else { - warnx("unknown q parameter %s.\n", argv[i]); - return -EINVAL; - } - } - if ((f_arg_required & (1 << QPARM_RNGSZ_IDX)) && - !(f_arg_set & (1 << QPARM_RNGSZ_IDX))) { - warnx("Info: Default ring size set to 2048"); - qparm->qrngsz_idx = 9; - f_arg_set |= 1 << QPARM_RNGSZ_IDX; - } - /* check for any missing mandatory parameters */ - mask = f_arg_set & f_arg_required; - if (mask != f_arg_required) { - int i; - unsigned int bit_mask = 1; - - for (i = 0; i < QPARM_MAX; i++, bit_mask <<= 1) { - if (!(bit_mask & f_arg_required)) - continue; - warnx("missing q parameter %s.\n", qparm_type_str[i]); - return -EINVAL; - } - } - - - if (!(f_arg_set & 1 << QPARM_DIR) && !(qparm->flags & XNL_F_Q_CMPL)) { - /* default to H2C */ - warnx("Warn: Default dir set to \'h2c\'"); - f_arg_set |= 1 << QPARM_DIR; - qparm->flags |= XNL_F_QDIR_H2C; - } - - qparm->sflags = f_arg_set; - - return argc; -} - -static int parse_q_cmd(int argc, char *argv[], int i, struct xcmd_info *xcmd) -{ - struct xcmd_q_parm *qparm = &xcmd->req.qparm; - uint32_t v1; - unsigned int f_arg_set = 0; - int rv; - int args_valid; - - /* - * q list - * q add idx mode [dir ] [cdev <0|1>] [cmptsz <0|1|2|3>] - * q start idx dir - * q stop idx dir - * q del idx dir - * q dump idx dir - * q dump idx dir desc - * q dump idx dir cmpt - * q pkt idx - */ - - if (!strcmp(argv[i], "list")) { - xcmd->op = XNL_CMD_Q_LIST; - rv = next_arg_read_int(argc, argv, &i, &v1); - if (rv < 0) - return rv; - qparm->idx = v1; - f_arg_set |= 1 << QPARM_IDX; - rv = next_arg_read_int(argc, argv, &i, &v1); - if (rv < 0) - return rv; - qparm->num_q = v1; - return ++i; - } else if (!strcmp(argv[i], "add")) { - unsigned int mask; - - xcmd->op = XNL_CMD_Q_ADD; - get_next_arg(argc, argv, &i); - rv = read_qparm(argc, argv, i, qparm, (1 << QPARM_IDX)); - /* error checking of parameter values */ - if (qparm->sflags & (1 << QPARM_MODE)) { - mask = XNL_F_QMODE_MM | XNL_F_QMODE_ST; - if ((qparm->flags & mask) == mask) { - warnx("mode mm/st cannot be combined.\n"); - return -EINVAL; - } - } else { - /* default to MM */ - warnx("Warn: Default mode set to \'mm\'"); - qparm->sflags |= 1 << QPARM_MODE; - qparm->flags |= XNL_F_QMODE_MM; - } - - } else if (!strcmp(argv[i], "start")) { - xcmd->op = XNL_CMD_Q_START; - get_next_arg(argc, argv, &i); - qparm->fetch_credit = Q_ENABLE_C2H_FETCH_CREDIT; - qparm->flags |= (XNL_F_CMPL_STATUS_EN | XNL_F_CMPL_STATUS_ACC_EN | - XNL_F_CMPL_STATUS_PEND_CHK | XNL_F_CMPL_STATUS_DESC_EN | - XNL_F_FETCH_CREDIT); - rv = read_qparm(argc, argv, i, qparm, ((1 << QPARM_IDX) | - (1 << QPARM_RNGSZ_IDX))); - if ((qparm->flags & (XNL_F_QDIR_C2H | XNL_F_QMODE_ST)) == - (XNL_F_QDIR_C2H | XNL_F_QMODE_ST)) { - if (!(qparm->sflags & (1 << QPARM_CMPTSZ))) { - /* default to 8B */ - qparm->cmpt_entry_size = XNL_ST_C2H_CMPT_DESC_SIZE_8B; - qparm->sflags |= - (1 << QPARM_CMPTSZ); - } - } - } else if (!strcmp(argv[i], "stop")) { - xcmd->op = XNL_CMD_Q_STOP; - get_next_arg(argc, argv, &i); - rv = read_qparm(argc, argv, i, qparm, (1 << QPARM_IDX)); - } else if (!strcmp(argv[i], "del")) { - xcmd->op = XNL_CMD_Q_DEL; - get_next_arg(argc, argv, &i); - rv = read_qparm(argc, argv, i, qparm, (1 << QPARM_IDX)); - } else if (!strcmp(argv[i], "dump")) { - xcmd->op = XNL_CMD_Q_DUMP; - get_next_arg(argc, argv, &i); - rv = read_qparm(argc, argv, i, qparm, (1 << QPARM_IDX)); - } else if (!strcmp(argv[i], "pkt")) { - xcmd->op = XNL_CMD_Q_RX_PKT; - get_next_arg(argc, argv, &i); - rv = read_qparm(argc, argv, i, qparm, (1 << QPARM_IDX)); - } else if (!strcmp(argv[i], "cmpt_read")) { - xcmd->op = XNL_CMD_Q_CMPT_READ; - qparm->flags |= XNL_F_Q_CMPL; - get_next_arg(argc, argv, &i); - rv = read_qparm(argc, argv, i, qparm, (1 << QPARM_IDX)); -#ifdef ERR_DEBUG - } else if (!strcmp(argv[i], "err")) { - xcmd->op = XNL_CMD_Q_ERR_INDUCE; - get_next_arg(argc, argv, &i); - rv = read_qparm(argc, argv, i, qparm, ((1 << QPARM_IDX) | - (1 << QPARAM_ERR_NO))); -#endif - } else { - printf("Error: Unknown q command\n"); - return -EINVAL; - } - - if (rv < 0) - return rv; - i = rv; - - if (xcmd->op == XNL_CMD_Q_DUMP) { - unsigned int mask = (1 << QPARM_DESC) | (1 << QPARM_CMPT); - - if ((qparm->sflags & mask) == mask) { - warnx("dump cmpt/desc cannot be combined.\n"); - return -EINVAL; - } - if ((qparm->sflags & (1 << QPARM_DESC))) - xcmd->op = XNL_CMD_Q_DESC; - else if ((qparm->sflags & (1 << QPARM_CMPT))) - xcmd->op = XNL_CMD_Q_CMPT; - } - - args_valid = validate_qcmd(xcmd->op, qparm); - - qparm->sflags |= f_arg_set; - return (args_valid == 0) ? i : args_valid; -} - -static int parse_dev_cmd(int argc, char *argv[], int i, struct xcmd_info *xcmd) -{ - if (!strcmp(argv[i], "list")) { - xcmd->op = XNL_CMD_DEV_LIST; - i++; - } - - return i; -} - -static int parse_stat_cmd(int argc, char *argv[], int i, struct xcmd_info *xcmd) -{ - - xcmd->op = XNL_CMD_DEV_STAT; - if (i >= argc) - return i; - if (!strcmp(argv[i], "clear")) { - xcmd->op = XNL_CMD_DEV_STAT_CLEAR; - i++; - } - return i; -} - -static int parse_intr_cmd(int argc, char *argv[], int i, struct xcmd_info *xcmd) -{ - struct xcmd_intr *intrcmd = &xcmd->req.intr; - int rv; - - /* - * intr dump vector - */ - - memset(intrcmd, 0, sizeof(struct xcmd_intr)); - if (!strcmp(argv[i], "dump")) { - xcmd->op = XNL_CMD_INTR_RING_DUMP; - - get_next_arg(argc, argv, &i); - if (!strcmp(argv[i], "vector")) { - rv = next_arg_read_int(argc, argv, &i, &intrcmd->vector); - if (rv < 0) - return rv; - } - rv = next_arg_read_int(argc, argv, &i, &intrcmd->start_idx); - if (rv < 0) { - intrcmd->start_idx = 0; - intrcmd->end_idx = QDMA_MAX_INT_RING_ENTRIES - 1; - goto func_ret; - } - rv = next_arg_read_int(argc, argv, &i, &intrcmd->end_idx); - if (rv < 0) - intrcmd->end_idx = QDMA_MAX_INT_RING_ENTRIES - 1; - } -func_ret: - i++; - return i; -} - -int parse_cmd(int argc, char *argv[], struct xcmd_info *xcmd) -{ - char *ifname; - int i; - int rv; - - memset(xcmd, 0, sizeof(struct xcmd_info)); - - progname = argv[0]; - - if (argc == 1) - usage(stderr); - - if (argc == 2) { - if (!strcmp(argv[1], "?") || !strcmp(argv[1], "-h") || - !strcmp(argv[1], "help") || !strcmp(argv[1], "--help")) - usage(stdout); - - if (!strcmp(argv[1], "-v") || !strcmp(argv[1], "--version")) { - printf("%s version %s\n", PROGNAME, VERSION); - printf("%s\n", COPYRIGHT); - exit(0); - } - } - - if (!strcmp(argv[1], "dev")) { - rv = parse_dev_cmd(argc, argv, 2, xcmd); - goto done; - } - - /* which dma fpga */ - ifname = argv[1]; - rv = parse_ifname(ifname, xcmd); - if (rv < 0) - return rv; - - if (argc == 2) { - rv = 2; - xcmd->op = XNL_CMD_DEV_INFO; - goto done; - } - - i = 3; - if (!strcmp(argv[2], "reg")) { - rv = parse_reg_cmd(argc, argv, i, xcmd); - } else if (!strcmp(argv[2], "stat")) { - rv = parse_stat_cmd(argc, argv, i, xcmd); - } else if (!strcmp(argv[2], "q")) { - rv = parse_q_cmd(argc, argv, i, xcmd); - } else if (!strcmp(argv[2], "intring")){ - rv = parse_intr_cmd(argc, argv, i, xcmd); - } else if (!strcmp(argv[2], "cap")) { - rv = 3; - xcmd->op = XNL_CMD_DEV_CAP; - } else if (!strcmp(argv[2], "global_csr")) { - rv = 3; - xcmd->op = XNL_CMD_GLOBAL_CSR; - } else if (!strcmp(argv[2], "info")) { /* not exposed. only for debug */ - rv = 3; - xcmd->op = XNL_CMD_DEV_INFO; -#ifdef TANDEM_BOOT_SUPPORTED - } else if (!strcmp(argv[2], "en_st")) { - rv = 3; - xcmd->op = XNL_CMD_EN_ST; -#endif - } else { - warnx("bad parameter \"%s\".\n", argv[2]); - return -EINVAL; - } - -done: - if (rv < 0) - return rv; - i = rv; - - if (i < argc) { - warnx("unexpected parameter \"%s\".\n", argv[i]); - return -EINVAL; - } - return 0; -} diff --git a/QDMA/linux-kernel/apps/dma-ctl/cmd_parse.h b/QDMA/linux-kernel/apps/dma-ctl/cmd_parse.h deleted file mode 100755 index ecd9224dc..000000000 --- a/QDMA/linux-kernel/apps/dma-ctl/cmd_parse.h +++ /dev/null @@ -1,20 +0,0 @@ -/* - * This file is part of the QDMA userspace application - * to enable the user to execute the QDMA functionality - * - * Copyright (c) 2018-2022, Xilinx, Inc. All rights reserved. - * Copyright (c) 2022-2023, Advanced Micro Devices, Inc. All rights reserved. - * - * This source code is licensed under BSD-style license (found in the - * LICENSE file in the root directory of this source tree) - */ - -#ifndef USER_CLI_CMD_PARSE_H_ -#define USER_CLI_CMD_PARSE_H_ - -#include "qdma_nl.h" -#include "dmautils.h" - -int parse_cmd(int argc, char *argv[], struct xcmd_info *xcmd); - -#endif /* USER_CLI_CMD_PARSE_H_ */ diff --git a/QDMA/linux-kernel/apps/dma-ctl/main.c b/QDMA/linux-kernel/apps/dma-ctl/main.c deleted file mode 100755 index 2a80961e2..000000000 --- a/QDMA/linux-kernel/apps/dma-ctl/main.c +++ /dev/null @@ -1,208 +0,0 @@ -/* - * This file is part of the QDMA userspace application - * to enable the user to execute the QDMA functionality - * - * Copyright (c) 2018-2022, Xilinx, Inc. All rights reserved. - * Copyright (c) 2022-2023, Advanced Micro Devices, Inc. All rights reserved. - * - * This source code is licensed under BSD-style license (found in the - * LICENSE file in the root directory of this source tree) - */ - -#include -#include -#include -#include - -#include "cmd_parse.h" -#include "dmautils.h" - -static int (*xnl_proc_fn[XNL_CMD_MAX])(struct xcmd_info *xcmd) = { - qdma_dev_list_dump, /* XNL_CMD_DEV_LIST */ - qdma_dev_info, /* XNL_CMD_DEV_INFO */ - qdma_dev_stat, /* XNL_CMD_DEV_STAT */ - qdma_dev_stat_clear, /* XNL_CMD_DEV_STAT_CLEAR */ - qdma_reg_dump, /* XNL_CMD_REG_DUMP */ - qdma_reg_read, /* XNL_CMD_REG_RD */ - qdma_reg_write, /* XNL_CMD_REG_WRT */ - qdma_dev_q_list_dump, /* XNL_CMD_Q_LIST */ - qdma_q_add, /* XNL_CMD_Q_ADD */ - qdma_q_start, /* XNL_CMD_Q_START */ - qdma_q_stop, /* XNL_CMD_Q_STOP */ - qdma_q_del, /* XNL_CMD_Q_DEL */ - qdma_q_dump, /* XNL_CMD_Q_DUMP */ - qdma_q_desc_dump, /* XNL_CMD_Q_DESC */ - qdma_q_desc_dump, /* XNL_CMD_Q_CMPT */ - NULL, /* XNL_CMD_Q_RX_PKT */ - qdma_q_cmpt_read, /* XNL_CMD_Q_CMPT_READ */ -#ifdef ERR_DEBUG - NULL, /* XNL_CMD_Q_ERR_INDUCE */ -#endif - qdma_dev_intr_ring_dump, /* XNL_CMD_INTR_RING_DUMP */ - NULL, /* XNL_CMD_Q_UDD */ - qdma_dev_get_global_csr, /* XNL_CMD_GLOBAL_CSR */ - qdma_dev_cap, /* XNL_CMD_DEV_CAP */ - NULL, /* XNL_CMD_GET_Q_STATE */ - qdma_reg_info_read, /* XNL_CMD_REG_INFO_READ */ -#ifdef TANDEM_BOOT_SUPPORTED - qdma_en_st, /* XNL_CMD_EN_ST */ -#endif -}; - -static const char *desc_engine_mode[] = { - "Internal and Bypass mode", - "Bypass only mode", - "Inernal only mode" -}; - -static void dump_dev_cap(struct xcmd_info *xcmd) -{ - printf("%s\n\n", xcmd->resp.cap.version_str); - printf("=============Hardware Capabilities============\n\n"); - printf("Number of PFs supported : %u\n", xcmd->resp.cap.num_pfs); - printf("Total number of queues supported : %u\n", xcmd->resp.cap.num_qs); - printf("MM channels : %u\n", xcmd->resp.cap.mm_channel_max); - printf("FLR Present : %s\n", xcmd->resp.cap.flr_present ? "yes":"no"); - printf("ST enabled : %s\n", xcmd->resp.cap.st_en ? "yes":"no"); - printf("MM enabled : %s\n", xcmd->resp.cap.mm_en ? "yes":"no"); - printf("Mailbox enabled : %s\n", xcmd->resp.cap.mailbox_en ? "yes":"no"); - printf("MM completion enabled : %s\n", xcmd->resp.cap.mm_cmpt_en ? "yes":"no"); - printf("Debug Mode enabled : %s\n", xcmd->resp.cap.debug_mode ? "yes":"no"); - - if (xcmd->resp.cap.desc_eng_mode < sizeof(desc_engine_mode) / sizeof(desc_engine_mode[0])) { - printf("Desc Engine Mode : %s\n", - desc_engine_mode[xcmd->resp.cap.desc_eng_mode]); - }else { - printf("Desc Engine Mode : INVALID\n"); - } -} - -static void dump_dev_info(struct xcmd_info *xcmd) -{ - printf("=============Device Information============\n"); - printf("PCI : %02x:%02x.%01x\n", - xcmd->resp.dev_info.pci_bus, - xcmd->resp.dev_info.pci_dev, - xcmd->resp.dev_info.dev_func); - printf("HW q base : %u\n", xcmd->resp.dev_info.qbase); - printf("Max queues : %u\n", xcmd->resp.dev_info.qmax); - printf("Config bar : %u\n", xcmd->resp.dev_info.config_bar); - printf("AXI Master Lite bar : %u\n", xcmd->resp.dev_info.user_bar); -} - -static void dump_dev_stat(struct xcmd_info *xcmd) -{ - unsigned long long mmh2c_pkts; - unsigned long long mmc2h_pkts; - unsigned long long sth2c_pkts; - unsigned long long stc2h_pkts; - unsigned long long min_ping_pong_lat = 0; - unsigned long long max_ping_pong_lat = 0; - unsigned long long avg_ping_pong_lat = 0; - - mmh2c_pkts = xcmd->resp.dev_stat.mm_h2c_pkts; - mmc2h_pkts = xcmd->resp.dev_stat.mm_c2h_pkts; - sth2c_pkts = xcmd->resp.dev_stat.st_h2c_pkts; - stc2h_pkts = xcmd->resp.dev_stat.st_c2h_pkts; - min_ping_pong_lat = xcmd->resp.dev_stat.ping_pong_lat_min; - max_ping_pong_lat = xcmd->resp.dev_stat.ping_pong_lat_max; - avg_ping_pong_lat = xcmd->resp.dev_stat.ping_pong_lat_avg; - - printf("qdma%s%05x:statistics\n", xcmd->vf ? "vf" : "", xcmd->if_bdf); - printf("Total MM H2C packets processed = %llu\n", mmh2c_pkts); - printf("Total MM C2H packets processed = %llu\n", mmc2h_pkts); - printf("Total ST H2C packets processed = %llu\n", sth2c_pkts); - printf("Total ST C2H packets processed = %llu\n", stc2h_pkts); - printf("Min Ping Pong Latency = %llu\n", min_ping_pong_lat); - printf("Max Ping Pong Latency = %llu\n", max_ping_pong_lat); - printf("Avg Ping Pong Latency = %llu\n", avg_ping_pong_lat); -} - -static void dump_dev_global_csr(struct xcmd_info *xcmd) -{ - printf("Global Ring Sizes:"); - for ( int i=0; i < QDMA_GLOBAL_CSR_ARRAY_SZ; i++) - printf("%d ",xcmd->resp.csr.ring_sz[i]); - printf("\nC2H Timer Counters:"); - for ( int i=0; i < QDMA_GLOBAL_CSR_ARRAY_SZ; i++) - printf("%d ",xcmd->resp.csr.c2h_timer_cnt[i]); - printf("\nC2H Counter Thresholds:"); - for ( int i=0; i < QDMA_GLOBAL_CSR_ARRAY_SZ; i++) - printf("%d ",xcmd->resp.csr.c2h_cnt_th[i]); - printf("\nC2H Buf Sizes:"); - for ( int i=0; i < QDMA_GLOBAL_CSR_ARRAY_SZ; i++) - printf("%d ",xcmd->resp.csr.c2h_buf_sz[i]); - printf("\nWriteback Interval:%d\n",xcmd->resp.csr.wb_intvl); - -} - -static void xnl_dump_response(const char *resp) -{ - printf("%s", resp); -} - -void xnl_dump_cmd_resp(struct xcmd_info *xcmd) -{ - - switch(xcmd->op) { - case XNL_CMD_DEV_CAP: - dump_dev_cap(xcmd); - break; - case XNL_CMD_DEV_INFO: - dump_dev_info(xcmd); - break; - case XNL_CMD_DEV_STAT: - dump_dev_stat(xcmd); - break; - case XNL_CMD_REG_RD: - printf("qdma%s%05x, %02x:%02x.%02x, bar#%u, 0x%x = 0x%x.\n", - xcmd->vf ? "vf" :"", - xcmd->if_bdf, xcmd->resp.dev_info.pci_bus, - xcmd->resp.dev_info.pci_dev, - xcmd->resp.dev_info.dev_func, xcmd->req.reg.bar, - xcmd->req.reg.reg, xcmd->req.reg.val); - break; - case XNL_CMD_REG_WRT: - printf("qdma%s%05x, %02x:%02x.%02x, bar#%u, reg 0x%x, read back 0x%x.\n", - xcmd->vf ? "vf" :"", - xcmd->if_bdf, xcmd->resp.dev_info.pci_bus, - xcmd->resp.dev_info.pci_dev, - xcmd->resp.dev_info.dev_func, xcmd->req.reg.bar, - xcmd->req.reg.reg, xcmd->req.reg.val); - break; - case XNL_CMD_GLOBAL_CSR: - dump_dev_global_csr(xcmd); - break; - case XNL_CMD_REG_INFO_READ: - break; - default: - break; - } -} - -static int xnl_proc_cmd(struct xcmd_info *xcmd) -{ - xcmd->log_msg_dump = xnl_dump_response; - if (xnl_proc_fn[xcmd->op]) - return xnl_proc_fn[xcmd->op](xcmd); - - return -EOPNOTSUPP; -} - -int main(int argc, char *argv[]) -{ - struct xcmd_info xcmd; - int rv = 0; - - memset(&xcmd, 0, sizeof(xcmd)); - - rv = parse_cmd(argc, argv, &xcmd); - if (rv < 0) - return rv; - rv = xnl_proc_cmd(&xcmd); - if (rv < 0) - return rv; - xnl_dump_cmd_resp(&xcmd); - - return 0; -} diff --git a/QDMA/linux-kernel/apps/dma-ctl/version.h b/QDMA/linux-kernel/apps/dma-ctl/version.h deleted file mode 100755 index e01b78a8a..000000000 --- a/QDMA/linux-kernel/apps/dma-ctl/version.h +++ /dev/null @@ -1,19 +0,0 @@ -/* - * This file is part of the QDMA userspace application - * to enable the user to execute the QDMA functionality - * - * Copyright (c) 2018-2022, Xilinx, Inc. All rights reserved. - * Copyright (c) 2022-2023, Advanced Micro Devices, Inc. All rights reserved. - * - * This source code is licensed under BSD-style license (found in the - * LICENSE file in the root directory of this source tree) - */ - -#ifndef __DMA_CTL_VERSION_H -#define __DMA_CTL_VERSION_H - -#define PROGNAME "dma-ctl" -#define VERSION "2023.2.0" -#define COPYRIGHT "Copyright (c) 2022-2023 Advanced Micro Devices Inc." - -#endif diff --git a/QDMA/linux-kernel/apps/dma-from-device/Makefile b/QDMA/linux-kernel/apps/dma-from-device/Makefile deleted file mode 100755 index 95e66d294..000000000 --- a/QDMA/linux-kernel/apps/dma-from-device/Makefile +++ /dev/null @@ -1,27 +0,0 @@ -CC ?= gcc - -CFLAGS += -g -#CFLAGS += -O2 -fno-inline -Wall -Wstrict-prototypes -CFLAGS += -I. -I../include -I../dma-utils -CFLAGS += $(EXTRA_FLAGS) - -DMA-FROM-DEVICE = dma-from-device -DMA-UTILS_OBJS := $(patsubst %.c,%.o,$(wildcard ../dma-utils/*.c)) -DMA-FROM-DEVICE_OBJS := dma_from_device.o -DMA-FROM-DEVICE_OBJS += $(DMA-UTILS_OBJS) - -ifneq ($(CROSS_COMPILE_FLAG),) - CC=$(CROSS_COMPILE_FLAG)gcc -endif - -all: clean dma-from-device - -dma-from-device: $(DMA-FROM-DEVICE_OBJS) - $(CC) -lrt -o $@ $< -D_FILE_OFFSET_BITS=64 -D_GNU_SOURCE -D_LARGE_FILE_SOURCE - -%.o: %.c - $(CC) $(CFLAGS) -c -std=c99 -o $@ $< -D_FILE_OFFSET_BITS=64 -D_GNU_SOURCE -D_LARGE_FILE_SOURCE -D_AIO_AIX_SOURCE - -clean: - @rm -f *.o */*.o ../dma-utils/*.o - rm -rf *.o *.bin dma-from-device diff --git a/QDMA/linux-kernel/apps/dma-from-device/dma_from_device.c b/QDMA/linux-kernel/apps/dma-from-device/dma_from_device.c deleted file mode 100755 index fe3475759..000000000 --- a/QDMA/linux-kernel/apps/dma-from-device/dma_from_device.c +++ /dev/null @@ -1,236 +0,0 @@ -/* - * This file is part of the QDMA userspace application - * to enable the user to execute the QDMA functionality - * - * Copyright (c) 2018-2022, Xilinx, Inc. All rights reserved. - * Copyright (c) 2022-2023, Advanced Micro Devices, Inc. All rights reserved. - * - * This source code is licensed under BSD-style license (found in the - * LICENSE file in the root directory of this source tree) - */ - -#define _DEFAULT_SOURCE -#define _XOPEN_SOURCE 500 -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include - -#include "dma_xfer_utils.c" - -#define DEVICE_NAME_DEFAULT "/dev/qdma01000-MM-0" -#define SIZE_DEFAULT (32) -#define COUNT_DEFAULT (1) - - - - -static struct option const long_opts[] = { - {"device", required_argument, NULL, 'd'}, - {"address", required_argument, NULL, 'a'}, - {"size", required_argument, NULL, 's'}, - {"offset", required_argument, NULL, 'o'}, - {"count", required_argument, NULL, 'c'}, - {"file", required_argument, NULL, 'f'}, - {"help", no_argument, NULL, 'h'}, - {"verbose", no_argument, NULL, 'v'}, - {0, 0, 0, 0} -}; - -static int test_dma(char *devname, uint64_t addr, uint64_t size, - uint64_t offset, uint64_t count, char *ofname); -static int no_write = 0; - -static void usage(const char *name) -{ - int i = 0; - fprintf(stdout, "%s\n\n", name); - fprintf(stdout, "usage: %s [OPTIONS]\n\n", name); - fprintf(stdout, "Read via SGDMA, optionally save output to a file\n\n"); - - fprintf(stdout, " -%c (--%s) device (defaults to %s)\n", - long_opts[i].val, long_opts[i].name, DEVICE_NAME_DEFAULT); - i++; - fprintf(stdout, " -%c (--%s) the start address on the AXI bus\n", - long_opts[i].val, long_opts[i].name); - i++; - fprintf(stdout, - " -%c (--%s) size of a single transfer in bytes, default %d.\n", - long_opts[i].val, long_opts[i].name, SIZE_DEFAULT); - i++; - fprintf(stdout, " -%c (--%s) page offset of transfer\n", - long_opts[i].val, long_opts[i].name); - i++; - fprintf(stdout, " -%c (--%s) number of transfers, default is %d.\n", - long_opts[i].val, long_opts[i].name, COUNT_DEFAULT); - i++; - fprintf(stdout, - " -%c (--%s) file to write the data of the transfers\n", - long_opts[i].val, long_opts[i].name); - i++; - fprintf(stdout, " -%c (--%s) print usage help and exit\n", - long_opts[i].val, long_opts[i].name); - i++; - fprintf(stdout, " -%c (--%s) verbose output\n", - long_opts[i].val, long_opts[i].name); -} - -int main(int argc, char *argv[]) -{ - int cmd_opt; - char *device = DEVICE_NAME_DEFAULT; - uint64_t address = 0; - uint64_t size = SIZE_DEFAULT; - uint64_t offset = 0; - uint64_t count = COUNT_DEFAULT; - char *ofname = NULL; - - while ((cmd_opt = getopt_long(argc, argv, "vhxc:f:d:a:s:o:", long_opts, - NULL)) != -1) { - switch (cmd_opt) { - case 0: - /* long option */ - break; - case 'd': - /* device node name */ - device = strdup(optarg); - break; - case 'a': - /* RAM address on the AXI bus in bytes */ - address = getopt_integer(optarg); - break; - /* RAM size in bytes */ - case 's': - size = getopt_integer(optarg); - break; - case 'o': - offset = getopt_integer(optarg) & 4095; - break; - /* count */ - case 'c': - count = getopt_integer(optarg); - break; - /* count */ - case 'f': - ofname = strdup(optarg); - break; - /* print usage help and exit */ - case 'x': - no_write++; - break; - case 'v': - verbose = 1; - break; - case 'h': - default: - usage(argv[0]); - exit(0); - break; - } - } - if (verbose) - fprintf(stdout, - "dev %s, addr 0x%lx, size 0x%lx, offset 0x%lx, count %lu\n", - device, address, size, offset, count); - - return test_dma(device, address, size, offset, count, ofname); -} - -static int test_dma(char *devname, uint64_t addr, uint64_t size, - uint64_t offset, uint64_t count, char *ofname) -{ - ssize_t rc; - uint64_t i; - char *buffer = NULL; - char *allocated = NULL; - struct timespec ts_start, ts_end; - int out_fd = -1; - int fpga_fd = open(devname, O_RDWR | O_NONBLOCK); - double total_time = 0; - double result; - double avg_time = 0; - - if (fpga_fd < 0) { - fprintf(stderr, "unable to open device %s, %d.\n", - devname, fpga_fd); - perror("open device"); - return -EINVAL; - } - - /* create file to write data to */ - if (ofname) { - out_fd = open(ofname, O_RDWR | O_CREAT | O_TRUNC | O_SYNC, - 0666); - if (out_fd < 0) { - fprintf(stderr, "unable to open output file %s, %d.\n", - ofname, out_fd); - perror("open output file"); - rc = -EINVAL; - goto out; - } - } - - posix_memalign((void **)&allocated, 4096 /*alignment */ , size + 4096); - if (!allocated) { - fprintf(stderr, "OOM %lu.\n", size + 4096); - rc = -ENOMEM; - goto out; - } - - buffer = allocated + offset; - if (verbose) - fprintf(stdout, "host buffer 0x%lx, %p.\n", size + 4096, buffer); - - for (i = 0; i < count; i++) { - clock_gettime(CLOCK_MONOTONIC, &ts_start); - /* lseek & read data from AXI MM into buffer using SGDMA */ - rc = read_to_buffer(devname, fpga_fd, buffer, size, addr); - if (rc < 0) - goto out; - clock_gettime(CLOCK_MONOTONIC, &ts_end); - - /* subtract the start time from the end time */ - timespec_sub(&ts_end, &ts_start); - total_time += (ts_end.tv_sec + ((double)ts_end.tv_nsec/NSEC_DIV)); - /* a bit less accurate but side-effects are accounted for */ - if (verbose) - fprintf(stdout, - "#%lu: CLOCK_MONOTONIC %ld.%09ld sec. read %lu bytes\n", - i, ts_end.tv_sec, ts_end.tv_nsec, size); - - /* file argument given? */ - if ((out_fd >= 0) & (no_write == 0)) { - rc = write_from_buffer(ofname, out_fd, buffer, - size, i*size); - if (rc < 0) - goto out; - } - } - avg_time = (double)total_time/(double)count; - result = ((double)size)/avg_time; - if (verbose) - printf("** Avg time device %s, total time %f nsec, avg_time = %f, size = %lu, BW = %f bytes/sec\n", - devname, total_time, avg_time, size, result); - dump_throughput_result(size, result); - - rc = 0; - -out: - close(fpga_fd); - if (out_fd >= 0) - close(out_fd); - free(allocated); - - return rc; -} diff --git a/QDMA/linux-kernel/apps/dma-from-device/version.h b/QDMA/linux-kernel/apps/dma-from-device/version.h deleted file mode 100755 index 9eeb78480..000000000 --- a/QDMA/linux-kernel/apps/dma-from-device/version.h +++ /dev/null @@ -1,19 +0,0 @@ -/* - * This file is part of the QDMA userspace application - * to enable the user to execute the QDMA functionality - * - * Copyright (c) 2018-2022, Xilinx, Inc. All rights reserved. - * Copyright (c) 2022-2023, Advanced Micro Devices, Inc. All rights reserved. - * - * This source code is licensed under BSD-style license (found in the - * LICENSE file in the root directory of this source tree) - */ - -#ifndef __DMA_FROM_DEVICE_VERSION_H -#define __DMA_FROM_DEVICE_VERSION_H - -#define PROGNAME "dma-from-device" -#define VERSION "2023.2.0" -#define COPYRIGHT "Copyright (c) 2022-2023 Advanced Micro Devices Inc." - -#endif diff --git a/QDMA/linux-kernel/apps/dma-latency/Makefile b/QDMA/linux-kernel/apps/dma-latency/Makefile deleted file mode 100755 index 565497308..000000000 --- a/QDMA/linux-kernel/apps/dma-latency/Makefile +++ /dev/null @@ -1,39 +0,0 @@ -# -#/* -# * This file is part of the QDMA userspace application -# * to enable the user to execute the QDMA functionality -# * -# * Copyright (c) 2018-2022, Xilinx, Inc. All rights reserved. -# * Copyright (c) 2022-2023, Advanced Micro Devices, Inc. All rights reserved. -# * -# * This source code is licensed under BSD-style license (found in the -# * LICENSE file in the root directory of this source tree) -# */ - -CC ?= gcc - -CFLAGS += -g -#CFLAGS += -O2 -fno-inline -Wall -Wstrict-prototypes -CFLAGS += -I. -I../include -I../dma-utils -CFLAGS += $(EXTRA_FLAGS) - -DMA-LATENCY = dma-latency -DMA-UTILS_OBJS := $(patsubst %.c,%.o,$(wildcard ../dma-utils/*.c)) -DMA-LAT_OBJS := dmalat.o -DMA-LAT_OBJS += $(DMA-UTILS_OBJS) - -ifneq ($(CROSS_COMPILE_FLAG),) - CC=$(CROSS_COMPILE_FLAG)gcc -endif - -all: clean dma-latency - -dma-latency: $(DMA-LAT_OBJS) - $(CC) -pthread -lrt -o $@ $^ -laio -D_FILE_OFFSET_BITS=64 -D_GNU_SOURCE -D_LARGE_FILE_SOURCE - -%.o: %.c - $(CC) $(CFLAGS) -c -std=c99 -o $@ $< -D_FILE_OFFSET_BITS=64 -D_GNU_SOURCE -D_LARGE_FILE_SOURCE -D_AIO_AIX_SOURCE - -clean: - @rm -f *.o */*.o ../dma-utils/*.o - rm -rf *.o *.bin dma-latency diff --git a/QDMA/linux-kernel/apps/dma-latency/Readme.txt b/QDMA/linux-kernel/apps/dma-latency/Readme.txt deleted file mode 100755 index 9c07c2c88..000000000 --- a/QDMA/linux-kernel/apps/dma-latency/Readme.txt +++ /dev/null @@ -1,38 +0,0 @@ -/* - * This file is part of the Xilinx DMA IP Core driver for Linux - * - * Copyright (c) 2018-2022, Xilinx, Inc. All rights reserved. - * Copyright (c) 2022-2023, Advanced Micro Devices, Inc. All rights reserved. - * - * This source code is licensed under both the BSD-style license (found in the - * LICENSE file in the root directory of this source tree) and the GPLv2 (found - * in the COPYING file in the root directory of this source tree). - * You may select, at your option, one of the above-listed licenses. - */ - -What is the dma-lat tool? -The intent of the tool is to gather metrics related how much time do packets -take to loopback to the host when a packet is transmitted in the ST H2C direction -and the ST Traffic Generator loops back the same packet in the ST C2H direction. -The RDTSC timestamp is inserted into the packet that is transmitted in the H2C -direction at the time of PIDX update. The timestamp at the time when the -data interrupt is hit is taken and the difference in the timestamps is used to -measure the latency for the packet. The tool measures average, maximum and -minimum latency in CPU tick counts. To obtain the latency numbers in nanosecs, -the numbers reported by the tool need to be divided by the nominal CPU freq. - -How to use the tool? -The tool takes in a configuration file as input which contains data such as the -number of queues, packet sizes etc. Please refer to the Sample_dma_latency_config.txt -for more information on what are available the configuraion parameters. -The command syntax is - -dma-lat -c - -Important Note- -To be able to get correct results for the latency numbers it is necessary that the -number of CPUs be restricted to 1 and hyperthreading be turned OFF from BIOS. This is -to ensure that the CPU core that sends out the H2C packet which contains the timestamp -is the same CPU that receives that data interrupt for the loopback. If this is not done -then the packet might get transmitted from one CPU core with a different TSC timestamp, -and the interrupt might get hit on another CPU core which would cause an error in the -measurement. diff --git a/QDMA/linux-kernel/apps/dma-latency/dmalat.c b/QDMA/linux-kernel/apps/dma-latency/dmalat.c deleted file mode 100755 index 98c157ba3..000000000 --- a/QDMA/linux-kernel/apps/dma-latency/dmalat.c +++ /dev/null @@ -1,1133 +0,0 @@ -/* - * This file is part of the QDMA userspace application - * to enable the user to execute the QDMA functionality - * - * Copyright (c) 2018-2022, Xilinx, Inc. All rights reserved. - * Copyright (c) 2022-2023, Advanced Micro Devices, Inc. All rights reserved. - * - * This source code is licensed under BSD-style license (found in the - * LICENSE file in the root directory of this source tree) - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include "dmautils.h" -#include "qdma_nl.h" - -static struct option const long_opts[] = { - {"config", required_argument, NULL, 'c'}, - {0, 0, 0, 0} -}; - -static void prep_pci_dump(void); - -static void usage(const char *name) -{ - int i = 0; - fprintf(stdout, "%s\n\n", name); - fprintf(stdout, "usage: %s [OPTIONS]\n\n", name); - - fprintf(stdout, " -%c (--%s) config file that has configration for IO\n", - long_opts[i].val, long_opts[i].name); -} - -static unsigned int num_trailing_blanks(char *word) -{ - unsigned int i = 0; - unsigned int slen = strlen(word); - - if (!slen) return 0; - while (isspace(word[slen - i - 1])) { - i++; - } - - return i; -} - -static char * strip_blanks(char *word, long unsigned int *banlks) -{ - char *p = word; - unsigned int i = 0; - - while (isblank(p[0])) { - p++; - i++; - } - if (banlks) - *banlks = i; - - return p; -} - -static unsigned int copy_value(char *src, char *dst, unsigned int max_len) -{ - char *p = src; - unsigned int i = 0; - - while (max_len && !isspace(p[0])) { - dst[i] = p[0]; - p++; - i++; - max_len--; - } - - return i; -} - -static char * strip_comments(char *word) -{ - size_t numblanks; - char *p = strip_blanks(word, &numblanks); - - if (p[0] == '#') - return NULL; - else - p = strtok(word, "#"); - - return p; -} - -#define PCI_DUMP_CMD_LEN 100 -#define QDMA_GLBL_MAX_ENTRIES (16) - -enum q_mode { - Q_MODE_MM, - Q_MODE_ST, - Q_MODES -}; - -enum q_dir { - Q_DIR_H2C, - Q_DIR_C2H, - Q_DIR_BI, - Q_DIRS -}; - - -struct io_info { - int pid; - char q_name[20]; - char trig_mode[10]; - unsigned char q_ctrl; - unsigned int q_added; - unsigned int q_started; - int fd; - unsigned int pf; - unsigned int qid; - enum q_mode mode; - enum q_dir dir; - unsigned int idx_tmr; - unsigned int idx_cnt; - unsigned int idx_rngsz; - unsigned int pfetch_en; - unsigned int pkt_sz; - unsigned int cmptsz; - unsigned int thread_id; -}; - -#define container_of(ptr, type, member) ({ \ - const struct iocb *__mptr = (ptr); \ - (type *)( (char *)__mptr - offsetof(type,member) );}) - -static unsigned int io_exit = 0; -static unsigned int force_exit = 0; -static unsigned int num_q = 0; -static unsigned int pkt_sz = 0; -static unsigned int tsecs = 0; -struct io_info info[8]; -static char cfg_name[20]; -static unsigned int pci_bus = 0; -static unsigned int pci_dev = 0; -static unsigned int vf_perf = 0; -static char *dmactl_dev_prefix_str; -char *pf_dmactl_prefix_str = "qdma"; -char *vf_dmactl_prefix_str = "qdmavf"; -int base_pid; -enum q_mode mode = Q_MODE_ST; -enum q_dir dir = Q_DIR_BI; -unsigned int num_pf = 0; -unsigned int pf_start = 0; -unsigned int q_start = 0; -unsigned int idx_rngsz = 0; -unsigned int idx_tmr = 0; -unsigned int idx_cnt = 0; -unsigned int pfetch_en = 0; -unsigned int cmptsz = 0; -char trigmode[10]; -char pci_dump[PCI_DUMP_CMD_LEN]; -unsigned int dump_en = 0; -static struct timespec g_ts_start; -int *child_pid_lst = NULL; -unsigned int glbl_rng_sz[QDMA_GLBL_MAX_ENTRIES]; - -static int setup_thrd_env(struct io_info *_info, unsigned char is_new_fd); - -static int arg_read_int(char *s, uint32_t *v) -{ - char *p = NULL; - - - *v = strtoul(s, &p, 0); - if (*p && (*p != '\n') && !isblank(*p)) { - printf("Error:something not right%s %s %s",s, p, isblank(*p)? "true": "false"); - return -EINVAL; - } - return 0; -} - -static int arg_read_int_array(char *s, unsigned int *v, unsigned int max_arr_size) -{ - unsigned int slen = strlen(s); - unsigned int trail_blanks = num_trailing_blanks(s); - char *str = (char *)malloc(slen - trail_blanks + 1); - char *elem; - int cnt = 0; - - memset(str, '\0', slen + 1); - strncpy(str, s + 1, slen - trail_blanks - 2); - str[slen] = '\0'; - - elem = strtok(str, " ,");/* space or comma separated */ - while (elem != NULL) { - int ret; - - ret = arg_read_int(elem, &v[cnt]); - if (ret < 0) { - printf("ERROR: Invalid array element %sin %s\n", elem, s); - exit(0); - } - cnt++; - elem = strtok(NULL, " ,"); - if (cnt > (int)max_arr_size) { /* to avoid out of bounds */ - printf("ERROR: More than expected number of elements in %s - expected = %u\n", - str, max_arr_size); - exit(0); - } - } - free(str); - - return cnt; -} - -static int get_array_len(char *s) -{ - int i, len = 0; - - if (strlen(s) < 2) - return -EINVAL; - if ((s[0] != '(') && (s[strlen(s) - 1] != ')')) - return -EINVAL; - if ((s[0] == '(') && (s[1] == ')')) - return 0; - for (i = 0; i < (int)strlen(s); i++) { - if ((s[i] == ' ') || (s[i] == ',')) /* space or comma separated */ - len++; - if (s[i] == ')') - break; - } - - return (len + 1); - -} - -static void dump_thrd_info(struct io_info *_info) { - printf("q_name = %s\n", info->q_name); - printf("dir = %d\n", _info->dir); - printf("mode = %d\n", _info->mode); - printf("idx_cnt = %u\n", _info->idx_cnt); - printf("idx_rngsz = %u\n", _info->idx_rngsz); - printf("idx_tmr = %u\n", _info->idx_tmr); - printf("pf = %x\n", _info->pf); - printf("qid = %u\n", _info->qid); - printf("fd = %d\n", _info->fd); - printf("trig_mode = %s\n", _info->trig_mode); - printf("q_ctrl = %u\n", _info->q_ctrl); - printf("q_added = %u\n", _info->q_added); - printf("q_started = %u\n", _info->q_started); -} - -static void xnl_dump_response(const char *resp) -{ - printf("%s", resp); -} - -static int qdma_register_write(unsigned char is_vf, - unsigned int pf, int bar, unsigned long reg, - unsigned long value) -{ - struct xcmd_info xcmd; - struct xcmd_reg *regcmd; - int ret; - - memset(&xcmd, 0, sizeof(struct xcmd_info)); - - regcmd = &xcmd.req.reg; - xcmd.op = XNL_CMD_REG_WRT; - xcmd.vf = is_vf; - xcmd.if_bdf = pf; - xcmd.log_msg_dump = xnl_dump_response; - regcmd->bar = bar; - regcmd->reg = reg; - regcmd->val = value; - regcmd->sflags = XCMD_REG_F_BAR_SET | - XCMD_REG_F_REG_SET | - XCMD_REG_F_VAL_SET; - - ret = qdma_reg_write(&xcmd); - if (ret < 0) - printf("QDMA_REG_WRITE Failed, ret :%d\n", ret); - - return ret; -} - -static int qdma_register_read(unsigned char is_vf, - unsigned int pf, int bar, unsigned long reg, - unsigned int *reg_val) -{ - struct xcmd_info xcmd; - struct xcmd_reg *regcmd; - int ret; - - memset(&xcmd, 0, sizeof(struct xcmd_info)); - - regcmd = &xcmd.req.reg; - xcmd.op = XNL_CMD_REG_RD; - xcmd.vf = is_vf; - xcmd.if_bdf = pf; - xcmd.log_msg_dump = xnl_dump_response; - regcmd->bar = bar; - regcmd->reg = reg; - regcmd->sflags = XCMD_REG_F_BAR_SET | - XCMD_REG_F_REG_SET; - - ret = qdma_reg_read(&xcmd); - if (ret < 0) - printf("QDMA_REG_READ Failed, ret :%d\n", ret); - - *reg_val = regcmd->val; - - return ret; -} - -static int qdma_prepare_reg_dump(struct xcmd_info *xcmd, - unsigned char is_vf, struct io_info *info) -{ - struct xcmd_q_parm *qparm; - - if (!xcmd) { - printf("Error: Invalid Input Param\n"); - return -EINVAL; - } - - qparm = &xcmd->req.qparm; - - xcmd->op = XNL_CMD_REG_DUMP; - xcmd->vf = is_vf; - xcmd->if_bdf = info->pf; - xcmd->log_msg_dump = xnl_dump_response; - - return 0; -} - -static int qdma_registers_dump(unsigned char is_vf, struct io_info *info) -{ - struct xcmd_info xcmd; - int ret; - - memset(&xcmd, 0, sizeof(struct xcmd_info)); - ret = qdma_prepare_reg_dump(&xcmd, is_vf, info); - if (ret < 0) - return ret; - - ret = qdma_reg_dump(&xcmd); - if (ret < 0) - printf("Q_ failed, ret :%d\n", ret); - - return ret; -} - -static int qdma_prepare_q_add(struct xcmd_info *xcmd, - unsigned char is_vf, struct io_info *info) -{ - struct xcmd_q_parm *qparm; - - if (!xcmd) { - printf("Error: Invalid Input Param\n"); - return -EINVAL; - } - - qparm = &xcmd->req.qparm; - - xcmd->op = XNL_CMD_Q_ADD; - xcmd->vf = is_vf; - xcmd->if_bdf = info->pf; - xcmd->log_msg_dump = xnl_dump_response; - qparm->idx = info->qid; - qparm->num_q = 1; - - if (info->mode == Q_MODE_MM) - qparm->flags |= XNL_F_QMODE_MM; - else if (info->mode == Q_MODE_ST) - qparm->flags |= XNL_F_QMODE_ST; - else - return -EINVAL; - - if (info->dir == Q_DIR_H2C) - qparm->flags |= XNL_F_QDIR_H2C; - else if (info->dir == Q_DIR_C2H) - qparm->flags |= XNL_F_QDIR_C2H; - else - return -EINVAL; - - qparm->sflags = qparm->flags; - - return 0; -} - -static int qdma_add_queue(unsigned char is_vf, struct io_info *info) -{ - struct xcmd_info xcmd; - int ret; - - memset(&xcmd, 0, sizeof(struct xcmd_info)); - ret = qdma_prepare_q_add(&xcmd, is_vf, info); - if (ret < 0) - return ret; - - ret = qdma_q_add(&xcmd); - if (ret < 0) - printf("Q_ADD failed, ret :%d\n", ret); - - return ret; -} - -static int qdma_prepare_q_start(struct xcmd_info *xcmd, - unsigned char is_vf, struct io_info *info) -{ - struct xcmd_q_parm *qparm; - - - if (!xcmd) { - printf("Error: Invalid Input Param\n"); - return -EINVAL; - } - qparm = &xcmd->req.qparm; - - xcmd->op = XNL_CMD_Q_START; - xcmd->vf = is_vf; - xcmd->if_bdf = info->pf; - xcmd->log_msg_dump = xnl_dump_response; - qparm->idx = info->qid; - qparm->num_q = 1; - qparm->fetch_credit = Q_ENABLE_C2H_FETCH_CREDIT; - - if (info->mode == Q_MODE_MM) - qparm->flags |= XNL_F_QMODE_MM; - else if (info->mode == Q_MODE_ST) - qparm->flags |= XNL_F_QMODE_ST; - else - return -EINVAL; - - if (info->dir == Q_DIR_H2C) - qparm->flags |= XNL_F_QDIR_H2C; - else if (info->dir == Q_DIR_C2H) - qparm->flags |= XNL_F_QDIR_C2H; - else - return -EINVAL; - - qparm->qrngsz_idx = info->idx_rngsz; - - if ((info->dir == Q_DIR_C2H) && (info->mode == Q_MODE_ST)) { - if (cmptsz) - qparm->cmpt_entry_size = info->cmptsz; - else - qparm->cmpt_entry_size = XNL_ST_C2H_CMPT_DESC_SIZE_8B; - qparm->cmpt_tmr_idx = info->idx_tmr; - qparm->cmpt_cntr_idx = info->idx_cnt; - - if (!strcmp(info->trig_mode, "every")) - qparm->cmpt_trig_mode = 1; - else if (!strcmp(info->trig_mode, "usr_cnt")) - qparm->cmpt_trig_mode = 2; - else if (!strcmp(info->trig_mode, "usr")) - qparm->cmpt_trig_mode = 3; - else if (!strcmp(info->trig_mode, "usr_tmr")) - qparm->cmpt_trig_mode=4; - else if (!strcmp(info->trig_mode, "cntr_tmr")) - qparm->cmpt_trig_mode=5; - else if (!strcmp(info->trig_mode, "dis")) - qparm->cmpt_trig_mode = 0; - else { - printf("Error: unknown q trigmode %s.\n", info->trig_mode); - return -EINVAL; - } - - if (pfetch_en) - qparm->flags |= XNL_F_PFETCH_EN; - } - - qparm->flags |= (XNL_F_CMPL_STATUS_EN | XNL_F_CMPL_STATUS_ACC_EN | - XNL_F_CMPL_STATUS_PEND_CHK | XNL_F_CMPL_STATUS_DESC_EN | - XNL_F_FETCH_CREDIT); - - qparm->sflags |= (1 << QPARM_PING_PONG_EN); - - return 0; -} - -static int qdma_start_queue(unsigned char is_vf, struct io_info *info) -{ - struct xcmd_info xcmd; - int ret; - - memset(&xcmd, 0, sizeof(struct xcmd_info)); - ret = qdma_prepare_q_start(&xcmd, is_vf, info); - if (ret < 0) - return ret; - - ret = qdma_q_start(&xcmd); - if (ret < 0) - printf("Q_START failed, ret :%d\n", ret); - - return ret; -} - -static int qdma_prepare_q_stop(struct xcmd_info *xcmd, unsigned char is_vf, - struct io_info *info) -{ - struct xcmd_q_parm *qparm; - - if (!xcmd) - return -EINVAL; - - qparm = &xcmd->req.qparm; - - xcmd->op = XNL_CMD_Q_STOP; - xcmd->vf = is_vf; - xcmd->if_bdf = info->pf; - xcmd->log_msg_dump = xnl_dump_response; - qparm->idx = info->qid; - qparm->num_q = 1; - - if (info->mode == Q_MODE_MM) - qparm->flags |= XNL_F_QMODE_MM; - else if (info->mode == Q_MODE_ST) - qparm->flags |= XNL_F_QMODE_ST; - else - return -EINVAL; - - if (info->dir == Q_DIR_H2C) - qparm->flags |= XNL_F_QDIR_H2C; - else if (info->dir == Q_DIR_C2H) - qparm->flags |= XNL_F_QDIR_C2H; - else - return -EINVAL; - - return 0; -} - -static int qdma_stop_queue(unsigned char is_vf, struct io_info *info) -{ - struct xcmd_info xcmd; - int ret; - - memset(&xcmd, 0, sizeof(struct xcmd_info)); - ret = qdma_prepare_q_stop(&xcmd, is_vf, info); - if (ret < 0) - return ret; - - ret = qdma_q_stop(&xcmd); - if (ret < 0) - printf("Q_STOP failed, ret :%d\n", ret); - - return ret; -} - -static int qdma_prepare_q_del(struct xcmd_info *xcmd, unsigned char is_vf, - struct io_info *info) -{ - struct xcmd_q_parm *qparm; - - if (!xcmd) { - printf("Error: Invalid Input Param\n"); - return -EINVAL; - } - - qparm = &xcmd->req.qparm; - - xcmd->op = XNL_CMD_Q_DEL; - xcmd->vf = is_vf; - xcmd->if_bdf = info->pf; - xcmd->log_msg_dump = xnl_dump_response; - qparm->idx = info->qid; - qparm->num_q = 1; - - if (info->mode == Q_MODE_MM) - qparm->flags |= XNL_F_QMODE_MM; - else if (info->mode == Q_MODE_ST) - qparm->flags |= XNL_F_QMODE_ST; - else - return -EINVAL; - - if (info->dir == Q_DIR_H2C) - qparm->flags |= XNL_F_QDIR_H2C; - else if (info->dir == Q_DIR_C2H) - qparm->flags |= XNL_F_QDIR_C2H; - else - return -EINVAL; - - return 0; -} - -static int qdma_del_queue(unsigned char is_vf, struct io_info *info) -{ - struct xcmd_info xcmd; - int ret; - - memset(&xcmd, 0, sizeof(struct xcmd_info)); - ret = qdma_prepare_q_del(&xcmd, is_vf, info); - if (ret < 0) - return ret; - - ret = qdma_q_del(&xcmd); - if (ret < 0) - printf("Q_DEL failed, ret :%d\n", ret); - - return ret; -} - -static int qdma_prepare_q_dump(struct xcmd_info *xcmd, unsigned char is_vf, - struct io_info *info) -{ - struct xcmd_q_parm *qparm; - - if (!xcmd) { - printf("Error: Invalid Input Param\n"); - return -EINVAL; - } - - qparm = &xcmd->req.qparm; - - xcmd->op = XNL_CMD_Q_DUMP; - xcmd->vf = is_vf; - xcmd->if_bdf = info->pf; - xcmd->log_msg_dump = xnl_dump_response; - qparm->idx = info->qid; - qparm->num_q = 1; - - if (info->mode == Q_MODE_MM) - qparm->flags |= XNL_F_QMODE_MM; - else if (info->mode == Q_MODE_ST) - qparm->flags |= XNL_F_QMODE_ST; - else - return -EINVAL; - - if (info->dir == Q_DIR_H2C) - qparm->flags |= XNL_F_QDIR_H2C; - else if (info->dir == Q_DIR_C2H) - qparm->flags |= XNL_F_QDIR_C2H; - else - return -EINVAL; - - return 0; -} - -static int qdma_dump_queue(unsigned char is_vf, struct io_info *info) -{ - struct xcmd_info xcmd; - int ret; - - memset(&xcmd, 0, sizeof(struct xcmd_info)); - ret = qdma_prepare_q_dump(&xcmd, is_vf, info); - if (ret < 0) - return ret; - - return qdma_q_dump(&xcmd); -} - - -static void create_thread_info(void) -{ - unsigned int base = 0; - unsigned int q_ctrl = 1; - unsigned int i, k; - int last_fd = -1; - unsigned char is_new_fd = 1; - struct io_info *_info = info; - - prep_pci_dump(); - - if ((mode == Q_MODE_ST) && (dir != Q_DIR_H2C)) { - qdma_register_write(vf_perf, (pci_bus << 12) | (pci_dev << 4) | pf_start, 2, 0x50, cmptsz); - } - - for (k = 0; k < num_pf; k++) { - for (i = 0 ; i < num_q; i++) { - is_new_fd = 1; - snprintf(_info[base].q_name, 20, "%s%02x%02x%01x-%s-%u", - dmactl_dev_prefix_str, pci_bus, pci_dev, - pf_start+k, (mode == Q_MODE_MM) ? "MM" : "ST", q_start + i); - - _info[base].dir = Q_DIR_H2C; - _info[base].mode = mode; - _info[base].idx_rngsz = idx_rngsz; - _info[base].pf = (pci_bus << 12) | (pci_dev << 4) | (pf_start + k); - _info[base].qid = q_start + i; - _info[base].q_ctrl = q_ctrl; - _info[base].pkt_sz = pkt_sz; - last_fd = setup_thrd_env(&_info[base], is_new_fd); - _info[base].fd = last_fd; - is_new_fd = 0; - // Adding the Queue in the C2H direction also - _info[base].dir = Q_DIR_C2H; - _info[base].pfetch_en = pfetch_en; - _info[base].idx_cnt = idx_cnt; - _info[base].idx_tmr = idx_tmr; - _info[base].cmptsz = cmptsz; - strncpy(_info[base].trig_mode, trigmode, 10); - last_fd = setup_thrd_env(&_info[base], is_new_fd); - _info[base].thread_id = base; - base++; - } - - } - // Reset ST Traffic generator - qdma_register_write(vf_perf, (pci_bus << 12) | (pci_dev << 4) | pf_start, 2, 0x08, 0); - // Set the loopback bit for the ST traffic generator - qdma_register_write(vf_perf, (pci_bus << 12) | (pci_dev << 4) | pf_start, 2, 0x08, 1); - - usleep(1000); - -} - -static void parse_config_file(const char *cfg_fname) -{ - char *linebuf = NULL; - char *realbuf; - FILE *fp; - size_t linelen = 0; - size_t numread; - size_t numblanks; - unsigned int linenum = 0; - char *config, *value; - unsigned int dir_factor = 1; - char rng_sz[100] = {'\0'}; - char rng_sz_path[512] = {'\0'}; - int rng_sz_fd, ret = 0; - - fp = fopen(cfg_fname, "r"); - if (fp == NULL) - exit(EXIT_FAILURE); - - while ((numread = getline(&linebuf, &linelen, fp)) != -1) { - numread--; - linenum++; - linebuf = strip_comments(linebuf); - if (!linebuf) - continue; - realbuf = strip_blanks(linebuf, &numblanks); - linelen -= numblanks; - if (0 == linelen) - continue; - config = strtok(realbuf, "="); - value = strtok(NULL, "="); - if (!strncmp(config, "name", 3)) { - copy_value(value, cfg_name, 20); - } else if (!strncmp(config, "pf_range", 8)) { - char *pf_range_start = strtok(value, ":"); - char *pf_range_end = strtok(NULL, ":"); - unsigned int start; - unsigned int end; - if (arg_read_int(pf_range_start, &start)) { - printf("Error: Invalid pf range start:%s\n", pf_range_start); - goto prase_cleanup; - } - if (arg_read_int(pf_range_end, &end)) { - printf("Error: Invalid pf range end:%s\n", pf_range_end); - goto prase_cleanup; - } - - pf_start = start; - num_pf = end - start + 1; - } else if (!strncmp(config, "q_range", 7)) { - char *q_range_start = strtok(value, ":"); - char *q_range_end = strtok(NULL, ":"); - unsigned int start; - unsigned int end; - if (arg_read_int(q_range_start, &start)) { - printf("Error: Invalid q range start:%s\n", q_range_start); - goto prase_cleanup; - } - if (arg_read_int(q_range_end, &end)) { - printf("Error: Invalid q range end:%s\n", q_range_end); - goto prase_cleanup; - } - - q_start = start; - num_q = end - start + 1; - } else if (!strncmp(config, "rngidx", 6)) { - if (arg_read_int(value, &idx_rngsz)) { - printf("Error: Invalid idx_rngsz:%s\n", value); - goto prase_cleanup; - } - } else if (!strncmp(config, "tmr_idx", 7)) { - if (arg_read_int(value, &idx_tmr)) { - printf("Error: Invalid idx_tmr:%s\n", value); - goto prase_cleanup; - } - } - if (!strncmp(config, "cntr_idx", 8)) { - if (arg_read_int(value, &idx_cnt)) { - printf("Error: Invalid idx_cnt:%s\n", value); - goto prase_cleanup; - } - } else if (!strncmp(config, "pfetch_en", 9)) { - if (arg_read_int(value, &pfetch_en)) { - printf("Error: Invalid pfetch_en:%s\n", value); - goto prase_cleanup; - } - } else if (!strncmp(config, "cmptsz", 5)) { - if (arg_read_int(value, &cmptsz)) { - printf("Error: Invalid cmptsz:%s\n", value); - goto prase_cleanup; - } - } else if (!strncmp(config, "dump_en", 5)) { - if (arg_read_int(value, &dump_en)) { - printf("Error: Invalid dump_en:%s\n", value); - goto prase_cleanup; - } - } else if (!strncmp(config, "trig_mode", 9)) { - copy_value(value, trigmode, 10); - } else if (!strncmp(config, "runtime", 9)) { - if (arg_read_int(value, &tsecs)) { - printf("Error: Invalid tsecs:%s\n", value); - goto prase_cleanup; - } - } else if (!strncmp(config, "pkt_sz", 6)) { - if (arg_read_int(value, &pkt_sz)) { - printf("Error: Invalid pkt_sz:%s\n", value); - goto prase_cleanup; - } - } else if (!strncmp(config, "pci_bus", 7)) { - char *p; - - pci_bus = strtoul(value, &p, 16); - if (*p && (*p != '\n')) { - printf("Error: bad parameter \"%s\", integer expected", value); - goto prase_cleanup; - } - } else if (!strncmp(config, "pci_dev", 7)) { - char *p; - - pci_dev = strtoul(value, &p, 16); - if (*p && (*p != '\n')) { - printf("Error: bad parameter \"%s\", integer expected", value); - goto prase_cleanup; - } - } else if (!strncmp(config, "vf_perf", 7)) { - char *p; - - vf_perf = strtoul(value, &p, 16); - if (*p && (*p != '\n')) { - printf("Error: bad parameter \"%s\", integer expected", value); - goto prase_cleanup; - } - - } - } - fclose(fp); - if (vf_perf == 0) { - dmactl_dev_prefix_str = pf_dmactl_prefix_str; - } else { - dmactl_dev_prefix_str = vf_dmactl_prefix_str; - } - - if (!pci_bus && !pci_dev) { - printf("Error: PCI bus information not provided\n"); - exit(1); - } - - snprintf(rng_sz_path, 200,"dma-ctl %s%05x global_csr | grep Global| cut -d : -f 2 > glbl_rng_sz", - dmactl_dev_prefix_str, (pci_bus << 12) | (pci_dev << 4) | pf_start); - printf("%s\n", rng_sz_path); - system(rng_sz_path); - memset(rng_sz_path, 0, 200); - snprintf(rng_sz_path, 200, "glbl_rng_sz"); - - rng_sz_fd = open(rng_sz_path, O_RDONLY); - if (rng_sz_fd < 0) { - printf("Could not open %s\n", rng_sz_path); - exit(1); - } - ret = read(rng_sz_fd, &rng_sz[1], 99); - if (ret < 0) { - printf("Error: Could not read the file\n"); - exit(1); - } - close(rng_sz_fd); - /* below 2 line a work around to use arg_read_int_array */ - rng_sz[0] = ' '; - rng_sz[strlen(rng_sz)] = ' '; - ret = arg_read_int_array(rng_sz, glbl_rng_sz, QDMA_GLBL_MAX_ENTRIES); - if (ret <= 0) { - printf("Error: Invalid ring size array:%s\n", rng_sz); - exit(1); - } - - create_thread_info(); - - return; - -prase_cleanup: - fclose(fp); - exit(-1); -} - -/* Subtract timespec t2 from t1 - * - * Both t1 and t2 must already be normalized - * i.e. 0 <= nsec < 1000000000 - */ -static int timespec_check(struct timespec *t) -{ - if ((t->tv_nsec < 0) || (t->tv_nsec >= 1000000000)) - return -1; - return 0; - -} - -static void timespec_sub(struct timespec *t1, struct timespec *t2) -{ - if (timespec_check(t1) < 0) { - fprintf(stderr, "invalid time #1: %lld.%.9ld.\n", - (long long)t1->tv_sec, t1->tv_nsec); - return; - } - if (timespec_check(t2) < 0) { - fprintf(stderr, "invalid time #2: %lld.%.9ld.\n", - (long long)t2->tv_sec, t2->tv_nsec); - return; - } - t1->tv_sec -= t2->tv_sec; - t1->tv_nsec -= t2->tv_nsec; - if (t1->tv_nsec >= 1000000000) { - t1->tv_sec++; - t1->tv_nsec -= 1000000000; - } else if (t1->tv_nsec < 0) { - t1->tv_sec--; - t1->tv_nsec += 1000000000; - } -} - -static void io_proc_cleanup(struct io_info *_info) -{ - int s; - char reg_cmd[100] = {'\0'}; - - if (dump_en) { - s = qdma_dump_queue(vf_perf, _info); - if (s < 0) { - printf("Failed: queue_dump\nerrcode = %d\n", s); - } - } - - s = qdma_stop_queue(vf_perf, _info); - if (s < 0) { - printf("Failed: queue_stop\nerrcode = %d\n", s); - } - _info->q_started = 0; - - system(reg_cmd); - - s = qdma_del_queue(vf_perf, _info); - if (s < 0) { - printf("Failed: queue_del\nerrcode = %d\n", s); - } - _info->q_added = 0; -} - -static void *io_thread(void *argp) -{ - - struct io_info *_info = (struct io_info *)argp; - char *buffer = NULL; - - unsigned int io_sz = _info->pkt_sz; - - posix_memalign((void **)&buffer, 4096 /*alignment */ , io_sz + 4096); - if (!buffer) { - printf("OOM \n"); - return NULL; - } - - do { - - struct timespec ts_cur; - - if (tsecs) { - if (clock_gettime(CLOCK_MONOTONIC, &ts_cur) != 0) - break; - timespec_sub(&ts_cur, &g_ts_start); - if (ts_cur.tv_sec >= tsecs) - break; - } - - write(_info->fd, buffer ,io_sz); - read(_info->fd, buffer ,io_sz); - - - } while (tsecs && !force_exit); - - free(buffer); - - return NULL; -} - -static void prep_pci_dump(void) -{ - memset(pci_dump, '\0', PCI_DUMP_CMD_LEN); - snprintf(pci_dump, PCI_DUMP_CMD_LEN, "lspci -s %02x:%02x.%01x -vvv", pci_bus, pci_dev, pf_start); -} - -static int setup_thrd_env(struct io_info *_info, unsigned char is_new_fd) -{ - int s; - - /* add queue */ - s = qdma_add_queue(vf_perf, _info); - if (s < 0) { - exit(1); - } - _info->q_added++; - - /* start queue */ - /* start queue */ - s = qdma_start_queue(vf_perf, _info); - if (s < 0) - exit(1); - _info->q_started++; - - if (is_new_fd) { - char node[25] = {'\0'}; - - snprintf(node, 25, "/dev/%s", _info->q_name); - _info->fd = open(node, O_RDWR); - if (_info->fd < 0) { - printf("Error: Cannot find %s\n", node); - exit(1); - } - } - - return _info->fd; -} - -static void dump_result() -{ - char reg_cmd[100] = {'\0'}; - - snprintf(reg_cmd, 100, "dma-ctl %s%05x stat", - dmactl_dev_prefix_str, info[0].pf); - system(reg_cmd); - memset(reg_cmd, 0, 100); - snprintf(reg_cmd, 100, "dma-ctl %s%05x stat clear", - dmactl_dev_prefix_str, info[0].pf); - system(reg_cmd); - memset(reg_cmd, 0, 100); - -} - -static int is_valid_fd(int fd) -{ - return fcntl(fd, F_GETFL) != -1 || errno != EBADF; -} - -static void cleanup(void) { - - if (getpid() != base_pid) - return; - - for (int i=0;i 0 && is_valid_fd(info[i].fd)) - close(info[i].fd); - info[i].dir = Q_DIR_H2C; - io_proc_cleanup(&info[i]); - info[i].dir = Q_DIR_C2H; - io_proc_cleanup(&info[i]); - } - dump_result(); -} - -int main(int argc, char *argv[]) -{ - - int cmd_opt; - char *cfg_fname = NULL; - unsigned int i = 0; - cpu_set_t set; - while ((cmd_opt = getopt_long(argc, argv, "vhxc:c:", long_opts, - NULL)) != -1) { - switch (cmd_opt) { - case 0: - /* long option */ - break; - case 'c': - /* config file name */ - cfg_fname = strdup(optarg); - break; - default: - usage(argv[0]); - exit(0); - break; - } - } - if (cfg_fname == NULL) - return 1; - - parse_config_file(cfg_fname); - atexit(cleanup); - - printf("dmautils(%u) threads\n", num_q); - child_pid_lst = calloc(num_q, sizeof(int)); - base_pid = getpid(); - - CPU_ZERO(&set); - CPU_SET(0, &set); - if (sched_setaffinity(getpid(), sizeof(set), &set) == -1) - printf("setaffinity for thrd%u failed\n", info[i].thread_id); - - for (i = 0; i < num_q; i++) { - if (getpid() == base_pid) - child_pid_lst[i] = fork(); - else - break; - } - - clock_gettime(CLOCK_MONOTONIC, &g_ts_start); - if (getpid() == base_pid) { - for(i = 0; i < num_q; i++) { - waitpid(child_pid_lst[i], NULL, 0); - } - free(child_pid_lst); - child_pid_lst = NULL; - - qdma_register_write(vf_perf, (pci_bus << 12) | (pci_dev << 4) | pf_start, 2, 0x08, 0); - - } else { - info[i-1].pid = getpid(); - io_thread(&info[i-1]); - } - return 0; -} - diff --git a/QDMA/linux-kernel/apps/dma-latency/sample_dma_latency_config.txt b/QDMA/linux-kernel/apps/dma-latency/sample_dma_latency_config.txt deleted file mode 100755 index f71084506..000000000 --- a/QDMA/linux-kernel/apps/dma-latency/sample_dma_latency_config.txt +++ /dev/null @@ -1,28 +0,0 @@ -# -#/* -# * This file is part of the QDMA userspace application -# * to enable the user to execute the QDMA functionality -# * -# * Copyright (c) 2018-2022, Xilinx, Inc. All rights reserved. - * Copyright (c) 2022-2023, Advanced Micro Devices, Inc. All rights reserved. -# * -# * This source code is licensed under BSD-style license (found in the -# * LICENSE file in the root directory of this source tree) -# */ - -pf_range=0:0 -q_range=0:0 -flags= -cmpl_status_acc=5 -dump_en=0 -tmr_idx=9 -cntr_idx=0 -trig_mode=cntr_tmr -pfetch_en=1 -cmptsz=1 -rngidx=9 -runtime=1 -pkt_sz=64 -pci_bus=41 -pci_device=00 - diff --git a/QDMA/linux-kernel/apps/dma-latency/version.h b/QDMA/linux-kernel/apps/dma-latency/version.h deleted file mode 100755 index 650deb97f..000000000 --- a/QDMA/linux-kernel/apps/dma-latency/version.h +++ /dev/null @@ -1,19 +0,0 @@ -/* - * This file is part of the QDMA userspace application - * to enable the user to execute the QDMA functionality - * - * Copyright (c) 2018-2022, Xilinx, Inc. All rights reserved. - * Copyright (c) 2022-2023, Advanced Micro Devices, Inc. All rights reserved. - * - * This source code is licensed under BSD-style license (found in the - * LICENSE file in the root directory of this source tree) - */ - -#ifndef __DMA_LATENCY_VERSION_H -#define __DMA_LATENCY_VERSION_H - -#define PROGNAME "dma-latency" -#define VERSION "2023.2.0" -#define COPYRIGHT "Copyright (c) 2022-2023 Advanced Micro Devices Inc." - -#endif diff --git a/QDMA/linux-kernel/apps/dma-perf/Makefile b/QDMA/linux-kernel/apps/dma-perf/Makefile deleted file mode 100755 index 34ba4846d..000000000 --- a/QDMA/linux-kernel/apps/dma-perf/Makefile +++ /dev/null @@ -1,39 +0,0 @@ -# -#/* -# * This file is part of the QDMA userspace application -# * to enable the user to execute the QDMA functionality -# * -# * Copyright (c) 2018-2022, Xilinx, Inc. All rights reserved. -# * Copyright (c) 2022-2023, Advanced Micro Devices, Inc. All rights reserved. -# * -# * This source code is licensed under BSD-style license (found in the -# * LICENSE file in the root directory of this source tree) -# */ - -CC ?= gcc - -CFLAGS += -g -#CFLAGS += -O2 -fno-inline -Wall -Wstrict-prototypes -CFLAGS += -I. -I../include -I../dma-utils -CFLAGS += $(EXTRA_FLAGS) - -DMA-PERF = dma-perf -DMA-UTILS_OBJS := $(patsubst %.c,%.o,$(wildcard ../dma-utils/*.c)) -DMA-PERF_OBJS := dmaperf.o -DMA-PERF_OBJS += $(DMA-UTILS_OBJS) - -ifneq ($(CROSS_COMPILE_FLAG),) - CC=$(CROSS_COMPILE_FLAG)gcc -endif - -all: clean dma-perf - -dma-perf: $(DMA-PERF_OBJS) - $(CC) -pthread -lrt -o $@ $^ -laio -D_FILE_OFFSET_BITS=64 -D_GNU_SOURCE -D_LARGE_FILE_SOURCE - -%.o: %.c - $(CC) $(CFLAGS) -c -std=c99 -o $@ $< -D_FILE_OFFSET_BITS=64 -D_GNU_SOURCE -D_LARGE_FILE_SOURCE -D_AIO_AIX_SOURCE - -clean: - @rm -f *.o */*.o ../dma-utils/*.o - rm -rf *.o *.bin dma-perf diff --git a/QDMA/linux-kernel/apps/dma-perf/dmaperf.c b/QDMA/linux-kernel/apps/dma-perf/dmaperf.c deleted file mode 100755 index 1d9638e01..000000000 --- a/QDMA/linux-kernel/apps/dma-perf/dmaperf.c +++ /dev/null @@ -1,2275 +0,0 @@ -/* - * This file is part of the QDMA userspace application - * to enable the user to execute the QDMA functionality - * - * Copyright (c) 2018-2022, Xilinx, Inc. All rights reserved. - * Copyright (c) 2022-2023, Advanced Micro Devices, Inc. All rights reserved. - * - * This source code is licensed under BSD-style license (found in the - * LICENSE file in the root directory of this source tree) - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include "dmautils.h" -#include "qdma_nl.h" - -#define SEC2NSEC 1000000000 -#define SEC2USEC 1000000 -#define DEFAULT_PAGE_SIZE 4096 -#define PAGE_SHIFT 12 - -#define DATA_VALIDATION 0 - -static struct option const long_opts[] = { - {"config", required_argument, NULL, 'c'}, - {0, 0, 0, 0} -}; - -static void prep_pci_dump(void); - -static void usage(const char *name) -{ - int i = 0; - fprintf(stdout, "%s\n\n", name); - fprintf(stdout, "usage: %s [OPTIONS]\n\n", name); - - fprintf(stdout, " -%c (--%s) config file that has configration for IO\n", - long_opts[i].val, long_opts[i].name); -} - -static unsigned int num_trailing_blanks(char *word) -{ - unsigned int i = 0; - unsigned int slen = strlen(word); - - if (!slen) return 0; - while (isspace(word[slen - i - 1])) { - i++; - } - - return i; -} - -static char * strip_blanks(char *word, long unsigned int *banlks) -{ - char *p = word; - unsigned int i = 0; - - while (isblank(p[0])) { - p++; - i++; - } - if (banlks) - *banlks = i; - - return p; -} - -static unsigned int copy_value(char *src, char *dst, unsigned int max_len) -{ - char *p = src; - unsigned int i = 0; - - while (max_len && !isspace(p[0])) { - dst[i] = p[0]; - p++; - i++; - max_len--; - } - - return i; -} - -static char * strip_comments(char *word) -{ - size_t numblanks; - char *p = strip_blanks(word, &numblanks); - - if (p[0] == '#') - return NULL; - else - p = strtok(word, "#"); - - return p; -} - -#define MSEC2NSEC 1000000 -#define CMPL_STATUS_ACC_CMD_LEN 200 -#define PCI_DUMP_CMD_LEN 100 - -#define QDMA_UL_SEND_MARKER_PACKET (1 << 5) -#define QDMA_UL_IMM_DUMP_C2H_DATA (1 << 17) -#define QDMA_UL_STOP_C2H_TRANSFER (1 << 18) -#define QDMA_UL_DROP_ENABLE (1 << 19) -#define QDMA_UL_IMM_DUMP_CMPT_FIFO (1 << 20) -#define QDMA_UL_STOP_CMPT_TRANSFER (1 << 21) - -#define QDMA_GLBL_MAX_ENTRIES (16) -//#define DEBUG - -enum q_mode { - Q_MODE_MM, - Q_MODE_ST, - Q_MODES -}; - -enum q_dir { - Q_DIR_H2C, - Q_DIR_C2H, - Q_DIR_BI, - Q_DIRS -}; - - -enum mm_channel_ctrl { - MM_CHANNEL_0, /*All Qs are assigned to channel 0*/ - MM_CHANNEL_1, /*All Qs are assigned to channel 1*/ - MM_CHANNEL_INTERLEAVE /*Odd queues are assigned to ch 1 and even Qs are assigned to channel 0*/ -}; - -#define THREADS_SET_CPU_AFFINITY 0 - -struct io_info { - unsigned int num_req_submitted; - unsigned int num_req_completed; - unsigned int num_req_completed_in_time; - int exit_check_count; - struct list_head *head; - struct list_head *tail; - sem_t llock; - int pid; - pthread_t evt_id; - char q_name[20]; - char trig_mode[10]; - unsigned char q_ctrl; - unsigned int q_added; - unsigned int q_started; - unsigned int q_wait_for_stop; - int fd; - unsigned int pf; - unsigned int qid; - enum q_mode mode; - enum q_dir dir; - unsigned int idx_tmr; - unsigned int idx_cnt; - unsigned int idx_rngsz; - unsigned int pfetch_en; - unsigned int pkt_burst; - unsigned int pkt_sz; - unsigned int cmptsz; - unsigned int stm_mode; - unsigned int pipe_gl_max; - unsigned int pipe_flow_id; - unsigned int pipe_slr_id; - unsigned int pipe_tdest; - unsigned int mm_chnl; - int keyhole_en; - unsigned int aperture_sz; - unsigned long int offset; -#ifdef DEBUG - unsigned long long total_nodes; - unsigned long long freed_nodes; -#endif - unsigned int thread_id; -#if THREADS_SET_CPU_AFFINITY - int cpu; -#endif -}; - -struct list_head { - struct list_head *next; - unsigned int max_events; - unsigned int completed_events; - io_context_t ctxt; -}; - -#define container_of(ptr, type, member) ({ \ - const struct iocb *__mptr = (ptr); \ - (type *)( (char *)__mptr - offsetof(type,member) );}) - -static unsigned int *io_exit = 0; -int io_exit_id; -static unsigned int mm_chnl = 0; -static unsigned int force_exit = 0; -static unsigned int num_q = 0; -static unsigned int pkt_sz = 0; -static unsigned int num_pkts; -static int keyhole_en = 0; -static unsigned int aperture_sz = 0; -/* For MM Channel =0 or 1 , offset is used for both MM Channels */ -static unsigned long int offset_ch0 = 0; -/*In MM Channel interleaving offset_ch1 is the offset used for Channel 1*/ -static unsigned long int offset_ch1 = 0; -static int offset_q_en= 0; -static unsigned long int h2c_q_offset_intvl = 0; -static unsigned long int c2h_q_offset_intvl = 0; -static unsigned long int h2c_q_start_offset= 0; -static unsigned long int c2h_q_start_offset= 0; -static unsigned int tsecs = 0; -struct io_info *info = NULL; -static char cfg_name[20]; -static unsigned int pci_bus = 0; -static unsigned int pci_dev = 0; -static unsigned int vf_perf = 0; -static char *dmactl_dev_prefix_str; -char *pf_dmactl_prefix_str = "qdma"; -char *vf_dmactl_prefix_str = "qdmavf"; -unsigned int num_thrds = 0; -unsigned int num_thrds_per_q = 1; -int shmid; -int base_pid; -enum q_mode mode; -enum q_dir dir; -unsigned int num_pf = 0; -unsigned int pf_start = 0; -unsigned int q_start = 0; -unsigned int idx_rngsz = 0; -unsigned int idx_tmr = 0; -unsigned int idx_cnt = 0; -unsigned int pfetch_en = 0; -unsigned int cmptsz = 0; -unsigned int no_memcpy = 1; -unsigned int stm_mode = 0; -unsigned int *pipe_gl_max_lst = NULL; -unsigned int *pipe_flow_id_lst = NULL; -unsigned int *pipe_slr_id_lst = NULL; -unsigned int *pipe_tdest_lst = NULL; -char trigmode[10]; -char pci_dump[PCI_DUMP_CMD_LEN]; -unsigned int dump_en = 0; -unsigned int marker_en = 1; -static struct timespec g_ts_start; -static unsigned char *q_lst_stop = NULL; -int q_lst_stop_mid; -int *child_pid_lst = NULL; -unsigned int glbl_rng_sz[QDMA_GLBL_MAX_ENTRIES]; -#if THREADS_SET_CPU_AFFINITY -unsigned int num_processors = 1; -#endif -#if DATA_VALIDATION -unsigned short valid_data[2*1024]; -#endif - -static void clear_events(struct io_info *_info, struct list_head *node); -static int setup_thrd_env(struct io_info *_info, unsigned char is_new_fd); - -static int arg_read_int(char *s, uint32_t *v) -{ - char *p = NULL; - - - *v = strtoul(s, &p, 0); - if (*p && (*p != '\n') && !isblank(*p)) { - printf("Error:something not right%s %s %s",s, p, isblank(*p)? "true": "false"); - return -EINVAL; - } - return 0; -} - -static int arg_read_long_uint(char *s, uint64_t *v) -{ - char *p = NULL; - *v = strtoull(s, &p, 0); - if (*p && (*p != '\n') && !isblank(*p)) { - printf("Error:something not right%s %s %s",s, p, isblank(*p)? "true": "false"); - return -EINVAL; - } - return 0; -} - -static int update_q_off(struct io_info *info) -{ - if (info->dir == Q_DIR_H2C) { - info->offset += h2c_q_start_offset + (info->qid * h2c_q_offset_intvl); - } else { - info->offset += c2h_q_start_offset + (info->qid * c2h_q_offset_intvl); - } -} - -static int arg_read_int_array(char *s, unsigned int *v, unsigned int max_arr_size) -{ - unsigned int slen = strlen(s); - unsigned int trail_blanks = num_trailing_blanks(s); - char *str = (char *)malloc(slen - trail_blanks + 1); - char *elem; - int cnt = 0; - - memset(str, '\0', slen + 1); - strncpy(str, s + 1, slen - trail_blanks - 2); - str[slen] = '\0'; - - elem = strtok(str, " ,");/* space or comma separated */ - while (elem != NULL) { - int ret; - - ret = arg_read_int(elem, &v[cnt]); - if (ret < 0) { - printf("ERROR: Invalid array element %sin %s\n", elem, s); - exit(0); - } - cnt++; - elem = strtok(NULL, " ,"); - if (cnt > (int)max_arr_size) { /* to avoid out of bounds */ - printf("ERROR: More than expected number of elements in %s - expected = %u\n", - str, max_arr_size); - exit(0); - } - } - free(str); - - return cnt; -} - -static int get_array_len(char *s) -{ - int i, len = 0; - - if (strlen(s) < 2) - return -EINVAL; - if ((s[0] != '(') && (s[strlen(s) - 1] != ')')) - return -EINVAL; - if ((s[0] == '(') && (s[1] == ')')) - return 0; - for (i = 0; i < (int)strlen(s); i++) { - if ((s[i] == ' ') || (s[i] == ',')) /* space or comma separated */ - len++; - if (s[i] == ')') - break; - } - - return (len + 1); - -} - -static void dump_thrd_info(struct io_info *_info) { - - printf("q_name = %s\n", _info->q_name); - printf("dir = %d\n", _info->dir); - printf("mode = %d\n", _info->mode); - printf("idx_cnt = %u\n", _info->idx_cnt); - printf("idx_rngsz = %u\n", _info->idx_rngsz); - printf("idx_tmr = %u\n", _info->idx_tmr); - printf("pf = %x\n", _info->pf); - printf("qid = %u\n", _info->qid); - printf("fd = %d\n", _info->fd); - printf("trig_mode = %s\n", _info->trig_mode); - printf("q_ctrl = %u\n", _info->q_ctrl); - printf("q_added = %u\n", _info->q_added); - printf("q_started = %u\n", _info->q_started); - printf("offset = 0x%lx\n", _info->offset); - if (stm_mode) { - printf("pipe_gl_max = %u\n", _info->pipe_gl_max); - printf("pipe_flow_id = %u\n", _info->pipe_flow_id); - printf("pipe_slr_id = %u\n", _info->pipe_slr_id); - printf("pipe_tdest = %u\n", _info->pipe_tdest); - } -#if THREADS_SET_CPU_AFFINITY - printf("cpu = %u\n", _info->cpu); -#endif -} - -struct dma_meminfo { - void *memptr; - unsigned int num_blks; -}; - -#define USE_MEMPOOL - -struct mempool_handle { - void *mempool; - unsigned int mempool_blkidx; - unsigned int mempool_blksz; - unsigned int total_memblks; - struct dma_meminfo *mempool_info; -#ifdef DEBUG - unsigned int id; - unsigned int loop; -#endif -}; - -static struct mempool_handle ctxhandle; -static struct mempool_handle iocbhandle; -static struct mempool_handle datahandle; - -static void mempool_create(struct mempool_handle *mpool, unsigned int entry_size, unsigned int max_entries) -{ -#ifdef USE_MEMPOOL - if (posix_memalign((void **)&mpool->mempool, DEFAULT_PAGE_SIZE, - max_entries * (entry_size + sizeof(struct dma_meminfo)))) { - printf("OOM\n"); - exit(1); - } - mpool->mempool_info = (struct dma_meminfo *)(((char *)mpool->mempool) + (max_entries * entry_size)); -#endif - mpool->mempool_blksz = entry_size; - mpool->total_memblks = max_entries; - mpool->mempool_blkidx = 0; -} - -static void mempool_free(struct mempool_handle *mpool) -{ -#ifdef USE_MEMPOOL - free(mpool->mempool); - mpool->mempool = NULL; -#endif -} - -static void *dma_memalloc(struct mempool_handle *mpool, unsigned int num_blks) -{ - unsigned int _mempool_blkidx = mpool->mempool_blkidx; - unsigned int tmp_blkidx = _mempool_blkidx; - unsigned int max_blkcnt = tmp_blkidx + num_blks; - unsigned int i, avail = 0; - void *memptr = NULL; - char *mempool = mpool->mempool; - struct dma_meminfo *_mempool_info = mpool->mempool_info; - unsigned int _total_memblks = mpool->total_memblks; - -#ifdef USE_MEMPOOL - if (max_blkcnt > _total_memblks) { - tmp_blkidx = 0; - max_blkcnt = num_blks; - } - for (i = tmp_blkidx; (i < _total_memblks) && (i < max_blkcnt); i++) { - if (_mempool_info[i].memptr) { /* occupied blks ahead */ - i += _mempool_info[i].num_blks; - max_blkcnt = i + num_blks; - avail = 0; - tmp_blkidx = i; - } else - avail++; - if (max_blkcnt > _total_memblks) { /* reached the end of mempool. circle through*/ - if (num_blks > _mempool_blkidx) return NULL; /* Continuous num_blks not available */ - i = 0; - avail = 0; - max_blkcnt = num_blks; - tmp_blkidx = 0; - } - } - if (avail < num_blks) { /* no required available blocks */ - return NULL; - } - - memptr = &(mempool[tmp_blkidx * mpool->mempool_blksz]); - _mempool_info[tmp_blkidx].memptr = memptr; - _mempool_info[tmp_blkidx].num_blks = num_blks; - mpool->mempool_blkidx = tmp_blkidx + num_blks; -#else - memptr = calloc(num_blks, mpool->mempool_blksz); -#endif - - return memptr; -} - -static void dma_free(struct mempool_handle *mpool, void *memptr) -{ -#ifdef USE_MEMPOOL - struct dma_meminfo *_meminfo = mpool->mempool_info; - unsigned int idx; - - if (!memptr) return; - - idx = (memptr - mpool->mempool)/mpool->mempool_blksz; -#ifdef DEBUG - if (idx >= mpool->total_memblks) { - printf("Asserting: %u:Invalid memory index %u acquired\n", mpool->id, idx); - while(1); - } -#endif - - _meminfo[idx].num_blks = 0; - _meminfo[idx].memptr = NULL; -#else - free(memptr); -#endif -} - -static void xnl_dump_response(const char *resp) -{ - printf("%s", resp); -} - -static int qdma_register_write(unsigned char is_vf, - unsigned int pf, int bar, unsigned long reg, - unsigned long value) -{ - struct xcmd_info xcmd; - struct xcmd_reg *regcmd; - int ret; - - memset(&xcmd, 0, sizeof(struct xcmd_info)); - - regcmd = &xcmd.req.reg; - xcmd.op = XNL_CMD_REG_WRT; - xcmd.vf = is_vf; - xcmd.if_bdf = pf; - xcmd.log_msg_dump = xnl_dump_response; - regcmd->bar = bar; - regcmd->reg = reg; - regcmd->val = value; - regcmd->sflags = XCMD_REG_F_BAR_SET | - XCMD_REG_F_REG_SET | - XCMD_REG_F_VAL_SET; - - ret = qdma_reg_write(&xcmd); - if (ret < 0) - printf("QDMA_REG_WRITE Failed, ret :%d\n", ret); - - return ret; -} - -static int qdma_register_read(unsigned char is_vf, - unsigned int pf, int bar, unsigned long reg, - unsigned int *reg_val) -{ - struct xcmd_info xcmd; - struct xcmd_reg *regcmd; - int ret; - - memset(&xcmd, 0, sizeof(struct xcmd_info)); - - regcmd = &xcmd.req.reg; - xcmd.op = XNL_CMD_REG_RD; - xcmd.vf = is_vf; - xcmd.if_bdf = pf; - xcmd.log_msg_dump = xnl_dump_response; - regcmd->bar = bar; - regcmd->reg = reg; - regcmd->sflags = XCMD_REG_F_BAR_SET | - XCMD_REG_F_REG_SET; - - ret = qdma_reg_read(&xcmd); - if (ret < 0) - printf("QDMA_REG_READ Failed, ret :%d\n", ret); - - *reg_val = regcmd->val; - - return ret; -} - -static void create_thread_info(void) -{ - unsigned int base = 0; - unsigned int dir_factor = 1; - unsigned int q_ctrl = 1; - unsigned int i, j, k; - struct io_info *_info; - int last_fd = -1; - unsigned char is_new_fd = 1; -#if THREADS_SET_CPU_AFFINITY - int h2c_cpu = 0; - int max_h2c_cpu = (num_processors / 2); - int c2h_cpu = max_h2c_cpu; - int max_c2h_cpu = (num_processors / 2) + ((num_processors % 2) ? 1 : 0); -#endif - - if (dir == Q_DIR_BI) - dir_factor = 2; - if ((shmid = shmget(IPC_PRIVATE, num_thrds * sizeof(struct io_info), IPC_CREAT | 0666)) < 0) - { - perror("smget returned -1\n"); - error(-1, errno, " "); - exit(-1); - } - if ((q_lst_stop_mid = shmget(IPC_PRIVATE, dir_factor * num_q * num_pf, IPC_CREAT | 0666)) < 0) - { - perror("smget returned -1\n"); - error(-1, errno, " "); - exit(-1); - } - if ((q_lst_stop = (unsigned char *) shmat(q_lst_stop_mid, NULL, 0)) == (unsigned char *) -1) { - perror("Process shmat returned NULL\n"); - error(-1, errno, " "); - exit(1); - } - memset(q_lst_stop, 0 , num_q); - if (shmdt(q_lst_stop) == -1) { - perror("shmdt returned -1\n"); - error(-1, errno, " "); - } - if ((_info = (struct io_info *) shmat(shmid, NULL, 0)) == (struct io_info *) -1) { - perror("Process shmat returned NULL\n"); - error(-1, errno, " "); - } - - if ((io_exit_id = shmget(IPC_PRIVATE,sizeof(unsigned int), IPC_CREAT | 0666)) < 0) - { - perror("smget returned -1\n"); - error(-1, errno, " "); - exit(-1); - } - - if ((io_exit = (unsigned int *) shmat(io_exit_id, NULL, 0)) == (unsigned int *) -1) { - perror("Process shmat returned NULL\n"); - error(-1, errno, " "); - } - prep_pci_dump(); - if ((mode == Q_MODE_ST) && (dir != Q_DIR_H2C)) { - qdma_register_write(vf_perf, (pci_bus << 12) | (pci_dev << 4) | pf_start, 2, 0x50, cmptsz); - qdma_register_write(vf_perf, (pci_bus << 12) | (pci_dev << 4) | pf_start, 2, 0x90, pkt_sz); - usleep(1000); - } - - base = 0; - for (k = 0; k < num_pf; k++) { - for (i = 0 ; i < num_q; i++) { - q_ctrl = 1; -#if THREADS_SET_CPU_AFFINITY - if (h2c_cpu >= max_h2c_cpu) - h2c_cpu = 0; - if (c2h_cpu >= (max_h2c_cpu + max_h2c_cpu)) - c2h_cpu = max_h2c_cpu; -#endif - for (j = 0; j < num_thrds_per_q; j++) { - is_new_fd = 1; - if ((dir == Q_DIR_H2C) || (dir == Q_DIR_BI)) { - snprintf(_info[base].q_name, 20, "%s%02x%02x%01x-%s-%u", - dmactl_dev_prefix_str, pci_bus, pci_dev, - pf_start+k, (mode == Q_MODE_MM) ? "MM" : "ST", q_start + i); - _info[base].dir = Q_DIR_H2C; - _info[base].mode = mode; - _info[base].idx_rngsz = idx_rngsz; - _info[base].pf = (pci_bus << 12) | (pci_dev << 4) | (pf_start + k); - _info[base].qid = q_start + i; - _info[base].q_ctrl = q_ctrl; - _info[base].fd = last_fd; - _info[base].pkt_burst = num_pkts; - if(mm_chnl == MM_CHANNEL_INTERLEAVE) - _info[base].mm_chnl = _info[base].qid % 2; - else - _info[base].mm_chnl = mm_chnl; - _info[base].pkt_sz = pkt_sz; - if ((_info[base].mode == Q_MODE_ST) && - (stm_mode)) { - _info[base].stm_mode = stm_mode; - _info[base].pipe_gl_max = pipe_gl_max_lst[(k*num_q) + i]; - _info[base].pipe_flow_id = pipe_flow_id_lst[(k*num_q) + i]; - _info[base].pipe_slr_id = pipe_slr_id_lst[(k*num_q) + i]; - _info[base].pipe_tdest = pipe_tdest_lst[(k*num_q) + i]; - } - - if (_info[base].mode == Q_MODE_MM && - keyhole_en) { - _info[base].aperture_sz = aperture_sz; - } - if(mm_chnl == MM_CHANNEL_INTERLEAVE && _info[base].mm_chnl ) - _info[base].offset = offset_ch1; - else - _info[base].offset = offset_ch0; - if(offset_q_en) - update_q_off(&_info[base]); -#if THREADS_SET_CPU_AFFINITY - _info[base].cpu = h2c_cpu; -#endif - sem_init(&_info[base].llock, 0, 1); - if (q_ctrl != 0) { - last_fd = setup_thrd_env(&_info[base], is_new_fd); - } - _info[base].thread_id = base; -// dump_thrd_info(&_info[base]); - _info[base].exit_check_count = 0; - base++; - is_new_fd = 0; - } - if (dir != Q_DIR_H2C) - { - snprintf(_info[base].q_name, 20, "%s%02x%02x%01x-%s-%u", - dmactl_dev_prefix_str, pci_bus, pci_dev, pf_start+k, (mode == Q_MODE_MM) ? "MM" : "ST", q_start + i); - _info[base].exit_check_count = 0; - _info[base].dir = Q_DIR_C2H; - _info[base].mode = mode; - _info[base].idx_rngsz = idx_rngsz; - _info[base].pf = (pci_bus << 12) | (pci_dev << 4) | (pf_start + k); - _info[base].qid = q_start + i; - _info[base].q_ctrl = q_ctrl; - _info[base].pkt_burst = num_pkts; - if(mm_chnl == MM_CHANNEL_INTERLEAVE) - _info[base].mm_chnl = _info[base].qid % 2; - else - _info[base].mm_chnl = mm_chnl; - if(mm_chnl == MM_CHANNEL_INTERLEAVE && _info[base].mm_chnl ) - _info[base].offset = offset_ch1; - else - _info[base].offset = offset_ch0; - if(offset_q_en) - update_q_off(&_info[base]); - - _info[base].pkt_sz = pkt_sz; -#if THREADS_SET_CPU_AFFINITY - _info[base].cpu = c2h_cpu; -#endif - if (_info[base].mode == Q_MODE_ST) { - _info[base].pfetch_en = pfetch_en; - _info[base].idx_cnt = idx_cnt; - _info[base].idx_tmr = idx_tmr; - _info[base].cmptsz = cmptsz; - strncpy(_info[base].trig_mode, trigmode, 10); - if (stm_mode) { - _info[base].stm_mode = stm_mode; - _info[base].pipe_gl_max = pipe_gl_max_lst[(k*num_q) + i]; - _info[base].pipe_flow_id = pipe_flow_id_lst[(k*num_q) + i]; - _info[base].pipe_slr_id = pipe_slr_id_lst[(k*num_q) + i]; - _info[base].pipe_tdest = pipe_tdest_lst[(k*num_q) + i]; - } - } - sem_init(&_info[base].llock, 0, 1); - _info[base].fd = last_fd; - if (q_ctrl != 0) { - last_fd = setup_thrd_env(&_info[base], is_new_fd); - } - _info[base].thread_id = base; -// dump_thrd_info(&_info[base]); - base++; - } - q_ctrl = 0; - } -#if THREADS_SET_CPU_AFFINITY - h2c_cpu++; - c2h_cpu++; -#endif - } - } - if ((mode == Q_MODE_ST) && (dir != Q_DIR_H2C)) { - if (!stm_mode) { - qdma_register_write(vf_perf, (pci_bus << 12) | (pci_dev << 4) | pf_start, 2, 0x08, - QDMA_UL_IMM_DUMP_C2H_DATA | QDMA_UL_IMM_DUMP_CMPT_FIFO/* | QDMA_UL_DROP_ENABLE*/); - usleep(1000); - } - } - if (shmdt(_info) == -1) { - perror("shmdt returned -1\n"); - error(-1, errno, " "); - } -} - -static void parse_config_file(const char *cfg_fname) -{ - char *linebuf = NULL; - char *realbuf; - FILE *fp; - size_t linelen = 0; - size_t numread; - size_t numblanks; - unsigned int linenum = 0; - char *config, *value; - unsigned int dir_factor = 1; - char rng_sz[100] = {'\0'}; - char rng_sz_path[200] = {'\0'}; - int rng_sz_fd, ret = 0; - - fp = fopen(cfg_fname, "r"); - if (fp == NULL) - exit(EXIT_FAILURE); - - while ((numread = getline(&linebuf, &linelen, fp)) != -1) { - numread--; - linenum++; - linebuf = strip_comments(linebuf); - if (!linebuf) - continue; - realbuf = strip_blanks(linebuf, &numblanks); - linelen -= numblanks; - if (0 == linelen) - continue; - config = strtok(realbuf, "="); - value = strtok(NULL, "="); - if (!strncmp(config, "mode", 4)) { - if (!strncmp(value, "mm", 2)) - mode = Q_MODE_MM; - else if(!strncmp(value, "st", 2)) - mode = Q_MODE_ST; - else { - printf("Error: Unkown mode"); - goto prase_cleanup; - } - } else if (!strncmp(config, "dir", 3)) { - if (!strncmp(value, "h2c", 3)) - dir = Q_DIR_H2C; - else if(!strncmp(value, "c2h", 3)) - dir = Q_DIR_C2H; - else if(!strncmp(value, "bi", 2)) - dir = Q_DIR_BI; - else { - printf("Error: Unkown dir"); - goto prase_cleanup; - } - } else if (!strncmp(config, "name", 3)) { - copy_value(value, cfg_name, 20); - } else if (!strncmp(config, "pf_range", 8)) { - char *pf_range_start = strtok(value, ":"); - char *pf_range_end = strtok(NULL, ":"); - unsigned int start; - unsigned int end; - if (arg_read_int(pf_range_start, &start)) { - printf("Error: Invalid pf range start:%s\n", pf_range_start); - goto prase_cleanup; - } - if (arg_read_int(pf_range_end, &end)) { - printf("Error: Invalid pf range end:%s\n", pf_range_end); - goto prase_cleanup; - } - - pf_start = start; - num_pf = end - start + 1; - } else if (!strncmp(config, "q_range", 7)) { - char *q_range_start = strtok(value, ":"); - char *q_range_end = strtok(NULL, ":"); - unsigned int start; - unsigned int end; - if (arg_read_int(q_range_start, &start)) { - printf("Error: Invalid q range start:%s\n", q_range_start); - goto prase_cleanup; - } - if (arg_read_int(q_range_end, &end)) { - printf("Error: Invalid q range end:%s\n", q_range_end); - goto prase_cleanup; - } - - q_start = start; - num_q = end - start + 1; - } else if (!strncmp(config, "rngidx", 6)) { - if (arg_read_int(value, &idx_rngsz)) { - printf("Error: Invalid idx_rngsz:%s\n", value); - goto prase_cleanup; - } - } else if (!strncmp(config, "tmr_idx", 7)) { - if (arg_read_int(value, &idx_tmr)) { - printf("Error: Invalid idx_tmr:%s\n", value); - goto prase_cleanup; - } - } - if (!strncmp(config, "cntr_idx", 8)) { - if (arg_read_int(value, &idx_cnt)) { - printf("Error: Invalid idx_cnt:%s\n", value); - goto prase_cleanup; - } - } else if (!strncmp(config, "pfetch_en", 9)) { - if (arg_read_int(value, &pfetch_en)) { - printf("Error: Invalid pfetch_en:%s\n", value); - goto prase_cleanup; - } - } else if (!strncmp(config, "cmptsz", 5)) { - if (arg_read_int(value, &cmptsz)) { - printf("Error: Invalid cmptsz:%s\n", value); - goto prase_cleanup; - } - } else if (!strncmp(config, "dump_en", 5)) { - if (arg_read_int(value, &dump_en)) { - printf("Error: Invalid dump_en:%s\n", value); - goto prase_cleanup; - } - } else if (!strncmp(config, "trig_mode", 9)) { - copy_value(value, trigmode, 10); - } else if (!strncmp(config, "runtime", 9)) { - if (arg_read_int(value, &tsecs)) { - printf("Error: Invalid tsecs:%s\n", value); - goto prase_cleanup; - } - } else if (!strncmp(config, "num_threads", 11)) { - if (arg_read_int(value, &num_thrds_per_q)) { - printf("Error: Invalid num_threads:%s\n", value); - goto prase_cleanup; - } - } else if (!strncmp(config, "pkt_sz", 6)) { - if (arg_read_int(value, &pkt_sz)) { - printf("Error: Invalid pkt_sz:%s\n", value); - goto prase_cleanup; - } - } else if (!strncmp(config, "mm_chnl", 7)) { - if (arg_read_int(value, &mm_chnl)) { - printf("Error: Invalid mm_chnl:%s\n", value); - goto prase_cleanup; - } - } else if (!strncmp(config, "num_pkt", 7)) { - if (arg_read_int(value, &num_pkts)) { - printf("Error: Invalid num_pkt:%s\n", value); - goto prase_cleanup; - } - } else if (!strncmp(config, "aperture_sz", 11)) { - if (arg_read_int(value, &aperture_sz)) { - printf("Error: Invalid aperture size:%s\n", value); - goto prase_cleanup; - } - } else if (!strncmp(config, "offset_ch1", 10)) { - if (arg_read_long_uint(value, &offset_ch1)) { - printf("Error: Invalid aperture offset:%s\n", value); - goto prase_cleanup; - } - } else if (!strncmp(config, "offset_q_en", 11)) { - if (arg_read_int(value, &offset_q_en)) { - printf("Error: Invalid offset_q_en option:%s\n", value); - goto prase_cleanup; - } - } else if (!strncmp(config, "h2c_q_offset_intvl", 18)) { - if (arg_read_long_uint(value, &h2c_q_offset_intvl)) { - printf("Error: Invalid H2C q offset:%s\n", value); - goto prase_cleanup; - } - } else if (!strncmp(config, "c2h_q_offset_intvl", 18)) { - if (arg_read_long_uint(value, &c2h_q_offset_intvl)) { - printf("Error: Invalid C2H q offset:%s\n", value); - goto prase_cleanup; - } - } else if (!strncmp(config, "h2c_q_start_offset", 18)) { - if (arg_read_long_uint(value, &h2c_q_start_offset)) { - printf("Error: Invalid H2C q offset:%s\n", value); - goto prase_cleanup; - } - } else if (!strncmp(config, "c2h_q_start_offset", 18)) { - if (arg_read_long_uint(value, &c2h_q_start_offset)) { - printf("Error: Invalid H2C q offset:%s\n", value); - goto prase_cleanup; - } - } else if (!strncmp(config, "offset_ch0", 10)) { - if (arg_read_long_uint(value, &offset_ch0)) { - printf("Error: Invalid aperture offset:%s\n", value); - goto prase_cleanup; - } - } else if (!strncmp(config, "keyhole_en", 7)) { - if (arg_read_int(value, &keyhole_en)) { - printf("Error: Invalid keyhole option:%s\n", value); - goto prase_cleanup; - } - } - else if (!strncmp(config, "no_memcpy", 9)) { - if (arg_read_int(value, &no_memcpy)) { - printf("Error: Invalid no_memcpy:%s\n", value); - goto prase_cleanup; - } - } else if (!strncmp(config, "stm_mode", 8)) { - if (arg_read_int(value, &stm_mode)) { - printf("Error: Invalid stm_mode:%s\n", value); - goto prase_cleanup; - } - } else if (!strncmp(config, "pipe_gl_max_lst", 15)) { - int arr_len = get_array_len(value); - int i; - - if ((arr_len < 0) || (arr_len != (int)(num_q*num_pf))) { - printf("ERROR: Invalid number of entries in pipe_gl_max_lst - %s\n", value); - exit(1); - } - if (arr_len) { - pipe_gl_max_lst = (unsigned int *)calloc(arr_len, sizeof(unsigned int)); - int ret = arg_read_int_array(value, pipe_gl_max_lst, arr_len); - if (ret <= 0) { - printf("Error: Invalid pipe_gl_max_lst:%s\n", value); - exit(1); - } - } - } else if (!strncmp(config, "pipe_flow_id_lst", 16)) { - int arr_len = get_array_len(value); - int i; - - if ((arr_len < 0) || (arr_len != (int)(num_q*num_pf))) { - printf("ERROR: Invalid number of entries in pipe_flow_id_lst - %s\n", value); - exit(1); - } - if (arr_len) { - pipe_flow_id_lst = (unsigned int *)calloc(arr_len, sizeof(unsigned int)); - int ret = arg_read_int_array(value, pipe_flow_id_lst, arr_len); - if (ret <= 0) { - printf("Error: Invalid pipe_flow_id_lst:%s\n", value); - exit(1); - } - } - } else if (!strncmp(config, "pipe_slr_id_lst", 15)) { - int arr_len = get_array_len(value); - int i; - - if ((arr_len < 0) || (arr_len != (int)(num_q*num_pf))) { - printf("ERROR: Invalid number of entries in pipe_slr_id_lst - %s\n", value); - exit(1); - } - if (arr_len) { - pipe_slr_id_lst = (unsigned int *)calloc(arr_len, sizeof(unsigned int)); - int ret = arg_read_int_array(value, pipe_slr_id_lst, arr_len); - if (ret <= 0) { - printf("Error: Invalid pipe_slr_id_lst:%s\n", value); - exit(1); - } - } - } else if (!strncmp(config, "pipe_tdest_lst", 15)) { - int arr_len = get_array_len(value); - int i; - - if ((arr_len < 0) || (arr_len != (int)(num_q*num_pf))) { - printf("ERROR: Invalid number of entries in pipe_tdest_lst - %s\n", value); - exit(1); - } - if (arr_len) { - pipe_tdest_lst = (unsigned int *)calloc(arr_len, sizeof(unsigned int)); - int ret = arg_read_int_array(value, pipe_tdest_lst, arr_len); - if (ret <= 0) { - printf("Error: Invalid pipe_tdest_lst:%s\n", value); - exit(1); - } - } - } else if (!strncmp(config, "pci_bus", 7)) { - char *p; - - pci_bus = strtoul(value, &p, 16); - if (*p && (*p != '\n')) { - printf("Error: bad parameter \"%s\", integer expected", value); - goto prase_cleanup; - } - } else if (!strncmp(config, "pci_dev", 7)) { - char *p; - - pci_dev = strtoul(value, &p, 16); - if (*p && (*p != '\n')) { - printf("Error: bad parameter \"%s\", integer expected", value); - goto prase_cleanup; - } - - } else if (!strncmp(config, "marker_en", 9)) { - char *p; - - marker_en = strtoul(value, &p, 16); - if (*p && (*p != '\n')) { - printf("Error: bad parameter \"%s\", integer expected", value); - goto prase_cleanup; - } - } else if (!strncmp(config, "vf_perf", 7)) { - char *p; - - vf_perf = strtoul(value, &p, 16); - if (*p && (*p != '\n')) { - printf("Error: bad parameter \"%s\", integer expected", value); - goto prase_cleanup; - } - - } - } - - fclose(fp); - if (vf_perf == 0) { - dmactl_dev_prefix_str = pf_dmactl_prefix_str; - } else { - dmactl_dev_prefix_str = vf_dmactl_prefix_str; - } - if (stm_mode && (!pipe_gl_max_lst || !pipe_flow_id_lst || - !pipe_slr_id_lst || !pipe_tdest_lst)) { - printf("Error: STM Attributes missing\n"); - exit(1); - } - - if (!pci_bus && !pci_dev) { - printf("Error: PCI bus information not provided\n"); - exit(1); - } - - snprintf(rng_sz_path, 200,"dma-ctl %s%05x global_csr | grep \"Global Ring\"| cut -d \":\" -f 2 > glbl_rng_sz", - dmactl_dev_prefix_str, (pci_bus << 12) | (pci_dev << 4) | pf_start); - system(rng_sz_path); - snprintf(rng_sz_path, 200, "glbl_rng_sz"); - - rng_sz_fd = open(rng_sz_path, O_RDONLY); - if (rng_sz_fd < 0) { - printf("Could not open %s\n", rng_sz_path); - exit(1); - } - ret = read(rng_sz_fd, &rng_sz[1], 99); - if (ret < 0) { - printf("Error: Could not read the file\n"); - exit(1); - } - close(rng_sz_fd); - /* below 2 line a work around to use arg_read_int_array */ - rng_sz[0] = ' '; - rng_sz[strlen(rng_sz)] = ' '; - ret = arg_read_int_array(rng_sz, glbl_rng_sz, QDMA_GLBL_MAX_ENTRIES); - if (ret <= 0) { - printf("Error: Invalid ring size array:%s\n", rng_sz); - exit(1); - } - - if (dir == Q_DIR_BI) - dir_factor = 2; - num_thrds = num_pf * num_q * dir_factor * num_thrds_per_q; - create_thread_info(); - if (stm_mode) { - free(pipe_tdest_lst); - free(pipe_slr_id_lst); - free(pipe_flow_id_lst); - free(pipe_gl_max_lst); - } - return; - -prase_cleanup: - fclose(fp); -} - -#define MAX_AIO_EVENTS 65536 - -static void list_add_tail(struct io_info *_info, struct list_head *node) -{ - sem_wait(&_info->llock); - if (_info->head == NULL) { - _info->head = node; - _info->tail = node; - } else { - _info->tail->next = node; - _info->tail = node; - } -#ifdef DEBUG - _info->total_nodes++; -#endif - sem_post( &_info->llock); -} - -static void list_add_head(struct io_info *_info, struct list_head *node) -{ - sem_wait(&_info->llock); - node->next = _info->head; - if (_info->head == NULL) { - _info->tail = node; - } - _info->head = node; - sem_post( &_info->llock); -} - -static struct list_head *list_pop(struct io_info *_info) -{ - struct list_head *node = NULL; - - sem_wait(&_info->llock); - node = _info->head; - if (_info->head == _info->tail) - _info->tail = NULL; - - if (node) - _info->head = node->next; - - sem_post(&_info->llock); - - return node; -} - -static void list_free(struct io_info *_info) -{ - struct list_head *node = NULL; - - sem_wait(&_info->llock); -#ifdef DEBUG - printf("Need to free %llu nodes in thrd%u\n", _info->total_nodes - _info->freed_nodes, _info->thread_id); -#endif - node = _info->head; - - while (node != NULL) { - struct list_head *prev_node = NULL; - - clear_events(_info, node); - io_destroy(node->ctxt); - prev_node = node; - node = node->next; - dma_free(&ctxhandle, prev_node); -#ifdef DEBUG - _info->freed_nodes++; -#endif - } - sem_post(&_info->llock); -} - -/* Subtract timespec t2 from t1 - * - * Both t1 and t2 must already be normalized - * i.e. 0 <= nsec < 1000000000 - */ -static int timespec_check(struct timespec *t) -{ - if ((t->tv_nsec < 0) || (t->tv_nsec >= 1000000000)) - return -1; - return 0; - -} - -static void timespec_sub(struct timespec *t1, struct timespec *t2) -{ - if (timespec_check(t1) < 0) { - fprintf(stderr, "invalid time #1: %lld.%.9ld.\n", - (long long)t1->tv_sec, t1->tv_nsec); - return; - } - if (timespec_check(t2) < 0) { - fprintf(stderr, "invalid time #2: %lld.%.9ld.\n", - (long long)t2->tv_sec, t2->tv_nsec); - return; - } - t1->tv_sec -= t2->tv_sec; - t1->tv_nsec -= t2->tv_nsec; - if (t1->tv_nsec >= 1000000000) { - t1->tv_sec++; - t1->tv_nsec -= 1000000000; - } else if (t1->tv_nsec < 0) { - t1->tv_sec--; - t1->tv_nsec += 1000000000; - } -} - -static void clear_events(struct io_info *_info, struct list_head *node) { - struct io_event *events = NULL; - int num_events = 0; - unsigned int j, bufcnt; - struct timespec ts_cur = {1, 0}; - - if (node->max_events <= node->completed_events) - return; -#ifdef DEBUG - printf("Thrd%u: Need to clear %u/%u events in node %p\n", - _info->thread_id, node->max_events - node->completed_events, - node->max_events, node); -#endif - events = calloc(node->max_events - node->completed_events, sizeof(struct io_event)); - if (events == NULL) { - printf("OOM\n"); - return; - } - do { - num_events = io_getevents(node->ctxt, 1, - node->max_events - node->completed_events, events, - &ts_cur); - for (j = 0; (num_events > 0) && (j < num_events); j++) { - struct iocb *iocb = (struct iocb *)events[j].obj; - struct iovec *iov; - - node->completed_events++; - if (!iocb) { - printf("Error: Invalid IOCB from events\n"); - continue; - } - - iov = (struct iovec *)iocb->u.c.buf; - - for (bufcnt = 0; bufcnt < iocb->u.c.nbytes; bufcnt++) - dma_free(&datahandle, iov[bufcnt].iov_base); - dma_free(&iocbhandle, iocb); - } - } while ((num_events > 0) && (node->max_events > node->completed_events)); - - free(events); -} - -// this function returns 1 as long as long as traffic can run, -// returns 0 when it is safe to exit the thread -static int thread_exit_check(struct io_info *_info) { - if((0 == *io_exit) && (0 == force_exit) ){ - return 1; - } else { - if ((_info->num_req_submitted != _info->num_req_completed) && _info->exit_check_count < 10000) { - if(_info->exit_check_count == 0) { - _info->num_req_completed_in_time = _info->num_req_completed; - } - _info->exit_check_count++; - usleep(100); - return 1; - } else { - printf("Exit Check: tid =%u, req_sbmitted=%u req_completed=%u dir=%s, intime=%u loop_count=%d, \n", - _info->thread_id, _info->num_req_submitted, - _info->num_req_completed,_info->dir == Q_DIR_H2C ? "H2C": "C2H", - _info->num_req_completed_in_time, _info->exit_check_count); - if(_info->exit_check_count != 0 ) { - _info->num_req_completed = _info->num_req_completed_in_time; - } - return 0; - } - - } -} - - - -static void *event_mon(void *argp) -{ - struct io_info *_info = (struct io_info *)argp; - unsigned int j, bufcnt; - struct io_event *events = NULL; - int num_events = 0; - struct timespec ts_cur = {0, 0}; -#if DATA_VALIDATION - unsigned short *rcv_data; - unsigned int k; -#endif - - events = calloc(MAX_AIO_EVENTS, sizeof(struct io_event)); - if (events == NULL) { - printf("OOM\n"); - exit(1); - } - - while (thread_exit_check(_info)) { - struct list_head *node = list_pop(_info); - - if (!node) - continue; - - memset(events, 0, MAX_AIO_EVENTS * sizeof(struct io_event)); - do { - num_events = io_getevents(node->ctxt, 1, - node->max_events - node->completed_events, events, - &ts_cur); - for (j = 0; (num_events > 0) && (j < num_events); j++) { - struct iocb *iocb = (struct iocb *)events[j].obj; - struct iovec *iov = NULL; - - if (!iocb) { - printf("Error: Invalid IOCB from events\n"); - continue; - } - _info->num_req_completed += events[j].res; - - iov = (struct iovec *)(iocb->u.c.buf); - if (!iov) { - printf("invalid buffer\n"); - continue; - } -#if DATA_VALIDATION - rcv_data = iov[0].iov_base; - for (k = 0; k < (iov[0].iov_len/2) && events[j].res && !(events[j].res2); k += 8) { - printf("%04x: %04x %04x %04x %04x %04x %04x %04x %04x\n", k, - rcv_data[k], rcv_data[k+1], rcv_data[k+2], - rcv_data[k+3], rcv_data[k+4], rcv_data[k+5], - rcv_data[k+6], rcv_data[k+7]); - } -#endif - for (bufcnt = 0; (bufcnt < iocb->u.c.nbytes) && iov; bufcnt++) - dma_free(&datahandle, iov[bufcnt].iov_base); - dma_free(&iocbhandle, iocb); - } - if (num_events > 0) - node->completed_events += num_events; - if (node->completed_events >= node->max_events) { - io_destroy(node->ctxt); - dma_free(&ctxhandle, node); - break; - } - } while(thread_exit_check(_info)); - if (node->completed_events < node->max_events) - list_add_head(_info, node); - } - free(events); -#ifdef DEBUG - printf("Exiting evt_thrd: %u\n", _info->thread_id); -#endif - - return NULL; -} - -static int qdma_prepare_reg_dump(struct xcmd_info *xcmd, - unsigned char is_vf, struct io_info *info) -{ - struct xcmd_q_parm *qparm; - - if (!xcmd) { - printf("Error: Invalid Input Param\n"); - return -EINVAL; - } - - qparm = &xcmd->req.qparm; - - xcmd->op = XNL_CMD_REG_DUMP; - xcmd->vf = is_vf; - xcmd->if_bdf = info->pf; - xcmd->log_msg_dump = xnl_dump_response; - - return 0; -} - -static int qdma_registers_dump(unsigned char is_vf, struct io_info *info) -{ - struct xcmd_info xcmd; - int ret; - - memset(&xcmd, 0, sizeof(struct xcmd_info)); - ret = qdma_prepare_reg_dump(&xcmd, is_vf, info); - if (ret < 0) - return ret; - - ret = qdma_reg_dump(&xcmd); - if (ret < 0) - printf("Q_ failed, ret :%d\n", ret); - - return ret; -} - -static int qdma_prepare_q_add(struct xcmd_info *xcmd, - unsigned char is_vf, struct io_info *info) -{ - struct xcmd_q_parm *qparm; - - if (!xcmd) { - printf("Error: Invalid Input Param\n"); - return -EINVAL; - } - - qparm = &xcmd->req.qparm; - - xcmd->op = XNL_CMD_Q_ADD; - xcmd->vf = is_vf; - xcmd->if_bdf = info->pf; - xcmd->log_msg_dump = xnl_dump_response; - qparm->idx = info->qid; - qparm->num_q = 1; - - if (info->mode == Q_MODE_MM) - qparm->flags |= XNL_F_QMODE_MM; - else if (info->mode == Q_MODE_ST) - qparm->flags |= XNL_F_QMODE_ST; - else - return -EINVAL; - - if (info->dir == Q_DIR_H2C) - qparm->flags |= XNL_F_QDIR_H2C; - else if (info->dir == Q_DIR_C2H) - qparm->flags |= XNL_F_QDIR_C2H; - else - return -EINVAL; - - qparm->sflags = qparm->flags; - - return 0; -} - -static int qdma_add_queue(unsigned char is_vf, struct io_info *info) -{ - struct xcmd_info xcmd; - int ret; - - memset(&xcmd, 0, sizeof(struct xcmd_info)); - ret = qdma_prepare_q_add(&xcmd, is_vf, info); - if (ret < 0) - return ret; - - ret = qdma_q_add(&xcmd); - if (ret < 0) - printf("Q_ADD failed, ret :%d\n", ret); - - return ret; -} - -static int qdma_prepare_q_start(struct xcmd_info *xcmd, - unsigned char is_vf, struct io_info *info) -{ - struct xcmd_q_parm *qparm; - unsigned int f_arg_set = 0; - - - if (!xcmd) { - printf("Error: Invalid Input Param\n"); - return -EINVAL; - } - qparm = &xcmd->req.qparm; - - xcmd->op = XNL_CMD_Q_START; - xcmd->vf = is_vf; - xcmd->if_bdf = info->pf; - xcmd->log_msg_dump = xnl_dump_response; - qparm->idx = info->qid; - qparm->num_q = 1; - f_arg_set |= 1 << QPARM_IDX; - qparm->fetch_credit = Q_ENABLE_C2H_FETCH_CREDIT; - - if (info->mode == Q_MODE_MM) - qparm->flags |= XNL_F_QMODE_MM; - else if (info->mode == Q_MODE_ST) - qparm->flags |= XNL_F_QMODE_ST; - else - return -EINVAL; - f_arg_set |= 1 << QPARM_MODE; - if (info->dir == Q_DIR_H2C) - qparm->flags |= XNL_F_QDIR_H2C; - else if (info->dir == Q_DIR_C2H) - qparm->flags |= XNL_F_QDIR_C2H; - else - return -EINVAL; - - f_arg_set |= 1 << QPARM_DIR; - qparm->qrngsz_idx = info->idx_rngsz; - f_arg_set |= 1 << QPARM_RNGSZ_IDX; - if ((info->dir == Q_DIR_C2H) && (info->mode == Q_MODE_ST)) { - if (cmptsz) - qparm->cmpt_entry_size = info->cmptsz; - else - qparm->cmpt_entry_size = XNL_ST_C2H_CMPT_DESC_SIZE_8B; - f_arg_set |= 1 << QPARM_CMPTSZ; - qparm->cmpt_tmr_idx = info->idx_tmr; - f_arg_set |= 1 << QPARM_CMPT_TMR_IDX; - qparm->cmpt_cntr_idx = info->idx_cnt; - f_arg_set |= 1 << QPARM_CMPT_CNTR_IDX; - - if (!strcmp(info->trig_mode, "every")) - qparm->cmpt_trig_mode = 1; - else if (!strcmp(info->trig_mode, "usr_cnt")) - qparm->cmpt_trig_mode = 2; - else if (!strcmp(info->trig_mode, "usr")) - qparm->cmpt_trig_mode = 3; - else if (!strcmp(info->trig_mode, "usr_tmr")) - qparm->cmpt_trig_mode=4; - else if (!strcmp(info->trig_mode, "cntr_tmr")) - qparm->cmpt_trig_mode=5; - else if (!strcmp(info->trig_mode, "dis")) - qparm->cmpt_trig_mode = 0; - else { - printf("Error: unknown q trigmode %s.\n", info->trig_mode); - return -EINVAL; - } - f_arg_set |= 1 << QPARM_CMPT_TRIG_MODE; - if (pfetch_en) - qparm->flags |= XNL_F_PFETCH_EN; - } - - if (info->mode == Q_MODE_MM) { - qparm->mm_channel = info->mm_chnl; - f_arg_set |= 1 <dir == Q_DIR_H2C) && (info->mode == Q_MODE_MM)) { - if (keyhole_en) { - qparm->aperture_sz = info->aperture_sz; - f_arg_set |= 1 << QPARM_KEYHOLE_EN; - } - } - - qparm->flags |= (XNL_F_CMPL_STATUS_EN | XNL_F_CMPL_STATUS_ACC_EN | - XNL_F_CMPL_STATUS_PEND_CHK | XNL_F_CMPL_STATUS_DESC_EN | - XNL_F_FETCH_CREDIT); - - qparm->sflags = f_arg_set; - return 0; -} - -static int qdma_start_queue(unsigned char is_vf, struct io_info *info) -{ - struct xcmd_info xcmd; - int ret; - - memset(&xcmd, 0, sizeof(struct xcmd_info)); - ret = qdma_prepare_q_start(&xcmd, is_vf, info); - if (ret < 0) - return ret; - - ret = qdma_q_start(&xcmd); - if (ret < 0) - printf("Q_START failed, ret :%d\n", ret); - - return ret; -} - -static int qdma_prepare_q_stop(struct xcmd_info *xcmd, unsigned char is_vf, - struct io_info *info) -{ - struct xcmd_q_parm *qparm; - - if (!xcmd) - return -EINVAL; - - qparm = &xcmd->req.qparm; - - xcmd->op = XNL_CMD_Q_STOP; - xcmd->vf = is_vf; - xcmd->if_bdf = info->pf; - xcmd->log_msg_dump = xnl_dump_response; - qparm->idx = info->qid; - qparm->num_q = 1; - - if (info->mode == Q_MODE_MM) - qparm->flags |= XNL_F_QMODE_MM; - else if (info->mode == Q_MODE_ST) - qparm->flags |= XNL_F_QMODE_ST; - else - return -EINVAL; - - if (info->dir == Q_DIR_H2C) - qparm->flags |= XNL_F_QDIR_H2C; - else if (info->dir == Q_DIR_C2H) - qparm->flags |= XNL_F_QDIR_C2H; - else - return -EINVAL; - - return 0; -} - -static int qdma_stop_queue(unsigned char is_vf, struct io_info *info) -{ - struct xcmd_info xcmd; - int ret; - - memset(&xcmd, 0, sizeof(struct xcmd_info)); - ret = qdma_prepare_q_stop(&xcmd, is_vf, info); - if (ret < 0) - return ret; - - ret = qdma_q_stop(&xcmd); - if (ret < 0) - printf("Q_STOP failed, ret :%d\n", ret); - - return ret; -} - -static int qdma_prepare_q_del(struct xcmd_info *xcmd, unsigned char is_vf, - struct io_info *info) -{ - struct xcmd_q_parm *qparm; - - if (!xcmd) { - printf("Error: Invalid Input Param\n"); - return -EINVAL; - } - - qparm = &xcmd->req.qparm; - - xcmd->op = XNL_CMD_Q_DEL; - xcmd->vf = is_vf; - xcmd->if_bdf = info->pf; - xcmd->log_msg_dump = xnl_dump_response; - qparm->idx = info->qid; - qparm->num_q = 1; - - if (info->mode == Q_MODE_MM) - qparm->flags |= XNL_F_QMODE_MM; - else if (info->mode == Q_MODE_ST) - qparm->flags |= XNL_F_QMODE_ST; - else - return -EINVAL; - - if (info->dir == Q_DIR_H2C) - qparm->flags |= XNL_F_QDIR_H2C; - else if (info->dir == Q_DIR_C2H) - qparm->flags |= XNL_F_QDIR_C2H; - else - return -EINVAL; - - return 0; -} - -static int qdma_del_queue(unsigned char is_vf, struct io_info *info) -{ - struct xcmd_info xcmd; - int ret; - - memset(&xcmd, 0, sizeof(struct xcmd_info)); - ret = qdma_prepare_q_del(&xcmd, is_vf, info); - if (ret < 0) - return ret; - - ret = qdma_q_del(&xcmd); - if (ret < 0) - printf("Q_DEL failed, ret :%d\n", ret); - - return ret; -} - -static int qdma_prepare_q_dump(struct xcmd_info *xcmd, unsigned char is_vf, - struct io_info *info) -{ - struct xcmd_q_parm *qparm; - - if (!xcmd) { - printf("Error: Invalid Input Param\n"); - return -EINVAL; - } - - qparm = &xcmd->req.qparm; - - xcmd->op = XNL_CMD_Q_DUMP; - xcmd->vf = is_vf; - xcmd->if_bdf = info->pf; - xcmd->log_msg_dump = xnl_dump_response; - qparm->idx = info->qid; - qparm->num_q = 1; - - if (info->mode == Q_MODE_MM) - qparm->flags |= XNL_F_QMODE_MM; - else if (info->mode == Q_MODE_ST) - qparm->flags |= XNL_F_QMODE_ST; - else - return -EINVAL; - - if (info->dir == Q_DIR_H2C) - qparm->flags |= XNL_F_QDIR_H2C; - else if (info->dir == Q_DIR_C2H) - qparm->flags |= XNL_F_QDIR_C2H; - else - return -EINVAL; - - return 0; -} - -static int qdma_dump_queue(unsigned char is_vf, struct io_info *info) -{ - struct xcmd_info xcmd; - int ret; - - memset(&xcmd, 0, sizeof(struct xcmd_info)); - ret = qdma_prepare_q_dump(&xcmd, is_vf, info); - if (ret < 0) - return ret; - - return qdma_q_dump(&xcmd); -} - -static void io_proc_cleanup(struct io_info *_info) -{ - unsigned int i; - unsigned int q_offset; - unsigned int dir_factor = (dir == Q_DIR_BI) ? 1 : 2; - unsigned int q_lst_idx_base; - unsigned char is_q_stop = (_info->q_ctrl && _info->q_started); - int reg_value = 0; - - *io_exit = 1; - pthread_join(_info->evt_id, NULL); - - q_offset = (_info->dir == Q_DIR_H2C) ? 0 : num_q; - if (dir != Q_DIR_BI) - q_offset = 0; - q_lst_idx_base = ((((_info->pf & 0x0000F) - pf_start) * num_q * dir_factor) - + q_offset); - _info->q_wait_for_stop = 1; - - while (is_q_stop) { - unsigned int j = 0; - for (i = 0; i < num_thrds; i++) { - if ((info[i].pf != _info->pf) || (info[i].qid != _info->qid) - || (info[i].dir != _info->dir)) - continue; - if (info[i].q_wait_for_stop) - j++; - else - break; - } - if (j != num_thrds_per_q) - sched_yield(); - else - break; - } - - if ((mode == Q_MODE_ST) && (dir != Q_DIR_H2C)) { - do { - for (i = 0; i < num_thrds; i++) { - if (!info[i].q_wait_for_stop) - break; - } - if (i == num_thrds) - break; - } while (1); - - if (!stm_mode && _info->pid == base_pid) { - qdma_register_write(vf_perf, _info->pf, 2, 0x08, - QDMA_UL_STOP_C2H_TRANSFER | QDMA_UL_STOP_CMPT_TRANSFER | - QDMA_UL_IMM_DUMP_CMPT_FIFO | QDMA_UL_IMM_DUMP_C2H_DATA); - - if (marker_en) { - qdma_register_write(vf_perf, _info->pf, 2, 0x08, - QDMA_UL_IMM_DUMP_C2H_DATA | QDMA_UL_IMM_DUMP_CMPT_FIFO - | QDMA_UL_SEND_MARKER_PACKET); - - usleep(1000); - - unsigned retry = 50; - while (retry) { - qdma_register_read(vf_perf, _info->pf, 2, 0x18, ®_value); - - usleep(500); - if (reg_value == 0x1) - break; - else - printf("Didnt received the c2h marker completion, retry count = %u\n", - (50 - (retry - 1))); - - usleep(500); - retry--; - } - } - } - } - - if (is_q_stop) { - int s; - if (dump_en) { - s = qdma_dump_queue(vf_perf, _info); - if (s < 0) { - printf("Failed: queue_dump\nerrcode = %d\n", s); - } - } - - if (_info->q_started) { - s = qdma_stop_queue(vf_perf, _info); - if (s < 0) { - printf("Failed: queue_stop\nerrcode = %d\n", s); - } - } - _info->q_started = 0; - - q_lst_stop[q_lst_idx_base + _info->qid - q_start] = 1; - } - - while (!(q_lst_stop[q_lst_idx_base + _info->qid - q_start])) { - sched_yield(); - } - - if (shmdt(q_lst_stop) == -1) { - perror("shmdt returned -1\n"); - error(-1, errno, " "); - } - - list_free(_info); - - mempool_free(&iocbhandle); - mempool_free(&ctxhandle); - mempool_free(&datahandle); -} - -static void *io_thread(void *argp) -{ - struct io_info *_info = (struct io_info *)argp; - int ret; - int s; - unsigned int max_io = MAX_AIO_EVENTS; - unsigned int cnt = 0; - pthread_attr_t attr; - unsigned int io_sz = _info->pkt_sz; - unsigned int burst_cnt = _info->pkt_burst; - unsigned int num_desc; - unsigned int max_reqs; - struct iocb *io_list[1]; - - if ((_info->mode == Q_MODE_ST) && (_info->dir == Q_DIR_C2H)) { - io_sz = _info->pkt_burst * _info->pkt_sz; - burst_cnt = 1; - } - num_desc = (io_sz + DEFAULT_PAGE_SIZE - 1) >> PAGE_SHIFT; - max_reqs = glbl_rng_sz[idx_rngsz]; - mempool_create(&datahandle, num_desc*DEFAULT_PAGE_SIZE, max_reqs + (burst_cnt * num_desc)); - mempool_create(&ctxhandle, sizeof(struct list_head), max_reqs); - mempool_create(&iocbhandle, sizeof(struct iocb) + (burst_cnt * sizeof(struct iovec)), max_reqs + (burst_cnt * num_desc)); -#ifdef DEBUG - ctxhandle.id = 1; - datahandle.id = 0; - iocbhandle.id = 2; -#endif - s = pthread_attr_init(&attr); - if (s != 0) - printf("pthread_attr_init failed\n"); - if (pthread_create(&_info->evt_id, &attr, event_mon, _info)) - exit(1); - - do { - struct list_head *node = NULL; - struct timespec ts_cur; - - if (tsecs) { - if (clock_gettime(CLOCK_MONOTONIC, &ts_cur) != 0) - break; - timespec_sub(&ts_cur, &g_ts_start); - if (ts_cur.tv_sec >= tsecs) - break; - } - node = dma_memalloc(&ctxhandle, 1); - if (!node) { - continue; - } - ret = io_queue_init(max_io, &node->ctxt); - if (ret != 0) { - printf("Error: io_setup error %d on %u\n", ret, _info->thread_id); - dma_free(&ctxhandle, node); - sched_yield(); - continue; - } - cnt = 0; - node->max_events = max_io; - list_add_tail(_info, node); - do { - struct iovec *iov = NULL; - unsigned int iovcnt; - if (tsecs) { - ret = clock_gettime(CLOCK_MONOTONIC, &ts_cur); - timespec_sub(&ts_cur, &g_ts_start); - if (ts_cur.tv_sec >= tsecs) { - node->max_events = cnt; - break; - } - } - - if (((_info->num_req_submitted - _info->num_req_completed) * - num_desc) > max_reqs) { - sched_yield(); - continue; - } - - io_list[0] = dma_memalloc(&iocbhandle, 1); - if (io_list[0] == NULL) { - if (cnt) { - node->max_events = cnt; - break; - } - else { - sched_yield(); - continue; - } - } - iov = (struct iovec *)(io_list[0] + 1); - for (iovcnt = 0; iovcnt < burst_cnt; iovcnt++) { - iov[iovcnt].iov_base = dma_memalloc(&datahandle, 1); - if (iov[iovcnt].iov_base == NULL) - break; - iov[iovcnt].iov_len = io_sz; - } - if (iovcnt == 0) { - dma_free(&iocbhandle, io_list[0]); - continue; - } - if (_info->dir == Q_DIR_H2C) { - io_prep_pwritev(io_list[0], - _info->fd, - iov, - iovcnt, - _info->offset); - } else { - io_prep_preadv(io_list[0], - _info->fd, - iov, - iovcnt, - _info->offset); - } - - ret = io_submit(node->ctxt, 1, io_list); - if(ret != 1) { - printf("Error: io_submit error:%d on %s for %u\n", ret, _info->q_name, cnt); - for (; iovcnt > 0; iovcnt--) - dma_free(&datahandle, iov[iovcnt].iov_base); - dma_free(&iocbhandle, io_list[0]); - node->max_events = cnt; - break; - } else { - cnt++; - _info->num_req_submitted += iovcnt; - } - } while (tsecs && !force_exit && (cnt < max_io)); - } while (tsecs && !force_exit); - - io_proc_cleanup(_info); - - return NULL; -} - -static void prep_pci_dump(void) -{ - memset(pci_dump, '\0', PCI_DUMP_CMD_LEN); - snprintf(pci_dump, PCI_DUMP_CMD_LEN, "lspci -s %02x:%02x.%01x -vvv", pci_bus, pci_dev, pf_start); -} - -static int setup_thrd_env(struct io_info *_info, unsigned char is_new_fd) -{ - int s; - - /* add queue */ - s = qdma_add_queue(vf_perf, _info); - if (s < 0) { - exit(1); - } - _info->q_added++; - - /* start queue */ - s = qdma_start_queue(vf_perf, _info); - if (s < 0) - exit(1); - _info->q_started++; - - if (is_new_fd) { - char node[25] = {'\0'}; - - snprintf(node, 25, "/dev/%s", _info->q_name); - _info->fd = open(node, O_RDWR); - if (_info->fd < 0) { - printf("Error: Cannot find %s\n", node); - exit(1); - } - } - - s = ioctl(_info->fd, 0, &no_memcpy); - if (s != 0) { - printf("failed to set non memcpy\n"); - exit(1); - } - - return _info->fd; -} - -static void dump_result(unsigned long long total_io_sz) -{ - unsigned long long gig_div = ((unsigned long long)tsecs * 1000000000); - unsigned long long meg_div = ((unsigned long long)tsecs * 1000000); - unsigned long long kil_div = ((unsigned long long)tsecs * 1000); - unsigned long long byt_div = ((unsigned long long)tsecs); - - if ((total_io_sz/gig_div)) { - printf("BW = %f GB/sec\n", ((double)total_io_sz/gig_div)); - } else if ((total_io_sz/meg_div)) { - printf("BW = %f MB/sec\n", ((double)total_io_sz/meg_div)); - } else if ((total_io_sz/kil_div)) { - printf("BW = %f KB/sec\n", ((double)total_io_sz/kil_div)); - } else - printf("BW = %f Bytes/sec\n", ((double)total_io_sz/byt_div)); -} - -static int is_valid_fd(int fd) -{ - return fcntl(fd, F_GETFL) != -1 || errno != EBADF; -} - -static void cleanup(void) -{ - int i; - unsigned long long total_num_h2c_ios = 0; - unsigned long long total_num_c2h_ios = 0; - unsigned long long total_io_sz = 0; - int s; - - if ((*io_exit == 0)) { - printf("force exit: cleaning up\n"); - force_exit = 1; - if (getpid() != base_pid) { - if (shmdt(info) == -1){ - perror("shmdt returned -1\n"); - error(-1, errno, " "); - } - if ((shmdt(q_lst_stop) == -1)) { - perror("shmdt returned -1\n"); - error(-1, errno, " "); - } - } else - for (i = 1; i < num_thrds; i++) - wait(NULL); - }/* else - printf("normal exit: cleaning up\n");*/ - - if (getpid() != base_pid) return; - - if (child_pid_lst != NULL) - free(child_pid_lst); - if (shmctl(q_lst_stop_mid, IPC_RMID, NULL) == -1) { - perror("shmctl returned -1\n"); - error(-1, errno, " "); - } - if (info == NULL) return; - - if (dump_en) { - s = system(pci_dump); - if (s != 0) { - printf("Failed: %s\nerrcode = %d\n", pci_dump, s); - } - - if(!vf_perf) { - s = qdma_registers_dump(vf_perf, &info[0]); - if (s < 0) { - printf("qdma_registers_dump failed. Errcode = %d\n", s); - } - } - } - - for (i = 0; i < num_thrds; i++) { - if (info[i].q_ctrl && info[i].q_started) { - if (dump_en) { - s = qdma_dump_queue(vf_perf, &info[i]); - if (s < 0) { - printf("Failed: queue_dump\nerrcode = %d\n", s); - } - } - - s = qdma_stop_queue(vf_perf, &info[i]); - if (s < 0) { - printf("Failed: queue_stop\nerrcode = %d\n", s); - } - info[i].q_started = 0; - } - if ((info[i].q_ctrl != 0) && (info[i].fd > 0) && is_valid_fd(info[i].fd)) - close(info[i].fd); - if (info[i].q_ctrl && info[i].q_added) { - s = qdma_del_queue(vf_perf, &info[i]); - if (s < 0) { - printf("Failed: queue_del\nerrcode = %d\n", s); - } - info[i].q_added = 0; - } - } - - - if(marker_en) { - if (info[0].mode == Q_MODE_ST && info[0].dir == Q_DIR_C2H) { - qdma_register_write(vf_perf, info[0].pf, 2, 0x08, - QDMA_UL_IMM_DUMP_C2H_DATA | QDMA_UL_IMM_DUMP_CMPT_FIFO); - } - } - - /* accumulate the statistics */ - for (i = 0; i < num_thrds; i++) { - if (info[i].dir == Q_DIR_H2C) - total_num_h2c_ios += info[i].num_req_completed; - else { - if (info[i].mode == Q_MODE_ST) - info[i].num_req_completed *= info[i].pkt_burst; - total_num_c2h_ios += info[i].num_req_completed; - } - } - if (shmdt(info) == -1){ - perror("shmdt returned -1\n"); - error(-1, errno, " "); - } - if (shmctl(shmid, IPC_RMID, NULL) == -1) { - perror("shmctl returned -1\n"); - error(-1, errno, " "); - } - if (shmdt(io_exit) == -1){ - perror("shmdt returned -1\n"); - error(-1, errno, " "); - } - if (shmctl(io_exit_id, IPC_RMID, NULL) == -1) { - perror("shmctl returned -1\n"); - error(-1, errno, " "); - } - if (tsecs == 0) tsecs = 1; - if (0 != total_num_h2c_ios) { - total_io_sz = (total_num_h2c_ios*pkt_sz); - printf("WRITE: total pps = %llu", total_num_h2c_ios/tsecs); - printf(" "); - dump_result(total_io_sz); - } - if (0 != total_num_c2h_ios) { - total_io_sz = (total_num_c2h_ios*pkt_sz); - printf("READ: total pps = %llu", total_num_c2h_ios/tsecs); - printf(" "); - dump_result(total_io_sz); - } - if ((0 == total_num_h2c_ios) && (0 == total_num_c2h_ios)) - printf("No IOs happened\n"); -} - -int main(int argc, char *argv[]) -{ - int cmd_opt; - char *cfg_fname = NULL; - unsigned int i; - unsigned int aio_max_nr = 0xFFFFFFFF; - char aio_max_nr_cmd[100] = {'\0'}; -#if THREADS_SET_CPU_AFFINITY - cpu_set_t set; -#endif - - while ((cmd_opt = getopt_long(argc, argv, "vhxc:c:", long_opts, - NULL)) != -1) { - switch (cmd_opt) { - case 0: - /* long option */ - break; - case 'c': - /* config file name */ - cfg_fname = strdup(optarg); - break; - default: - usage(argv[0]); - exit(0); - break; - } - } - if (cfg_fname == NULL) - return 1; - -#if THREADS_SET_CPU_AFFINITY - num_processors = get_nprocs_conf(); - CPU_ZERO(&set); -#endif -#if DATA_VALIDATION - for (i = 0; i < 2*1024; i++) - valid_data[i] = i; -#endif - parse_config_file(cfg_fname); - atexit(cleanup); - - snprintf(aio_max_nr_cmd, 100, "echo %u > /proc/sys/fs/aio-max-nr", aio_max_nr); - system(aio_max_nr_cmd); - - printf("dmautils(%u) threads\n", num_thrds); - child_pid_lst = calloc(num_thrds, sizeof(int)); - base_pid = getpid(); - child_pid_lst[0] = base_pid; - for (i = 1; i < num_thrds; i++) { - if (getpid() == base_pid) - child_pid_lst[i] = fork(); - else - break; - } - if ((info = (struct io_info *) shmat(shmid, NULL, 0)) == (struct io_info *) -1) { - perror("Process shmat returned NULL\n"); - error(-1, errno, " "); - exit(1); - } - if ((q_lst_stop = (unsigned char *) shmat(q_lst_stop_mid, NULL, 0)) == (unsigned char *) -1) { - perror("Process shmat returned NULL\n"); - error(-1, errno, " "); - exit(1); - } - - clock_gettime(CLOCK_MONOTONIC, &g_ts_start); - if (getpid() == base_pid) { - io_thread(&info[0]); -#if THREADS_SET_CPU_AFFINITY - for (j = 0; j < num_processors; j++) { - if (j != info[0].cpu) - CPU_SET(j, &set); - } - if (sched_setaffinity(base_pid, sizeof(set), &set) == -1) - printf("setaffinity for thrd%u failed\n", info[i].thread_id); -#endif - for(i = 1; i < num_thrds; i++) { - waitpid(child_pid_lst[i], NULL, 0); - } - free(child_pid_lst); - child_pid_lst = NULL; - } else { - info[i].pid = getpid(); -#if THREADS_SET_CPU_AFFINITY - for (j = 0; j < num_processors; j++) { - if (j != info[i].cpu) - CPU_SET(j, &set); - } - if (sched_setaffinity(getpid(), sizeof(set), &set) == -1) - printf("setaffinity for thrd%u failed\n", info[i].thread_id); -#endif - io_thread(&info[i - 1]); - if ((shmdt(info) == -1)) { - perror("shmdt returned -1\n"); - error(-1, errno, " "); - } - } - - *io_exit = 1; - return 0; -} - diff --git a/QDMA/linux-kernel/apps/dma-perf/dmaperf_config/st-bi.zip b/QDMA/linux-kernel/apps/dma-perf/dmaperf_config/st-bi.zip deleted file mode 100644 index d22e34b60e59af5345d7ab816aed07a7f895cd40..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 112903 zcmdqK3s_Bg`#z2+N*neRCL%5e*uT5?fmakE_STvxQP|(*Oj=SM+cTcfiz5Am74fcU26PP44XOR~-ibivHODE9P&hPw&8g zQ|aBSmmZ&Ab@>{HZvS--T6&X+-v|1=P<|f<8Pwf9^=j7c<^(iH@j`h2yGxx%s z(89YGX|WFb%)WaM94NG=Ib_bwoLyo4f1j7UWyPe;LYWE~(-zki4YnOGrk(gq*7{we ztdBWUud3I+@iRKJWUs1<*qb=Z{o$gNc2?`it=DI6$F!gN{>Q_Ps25D#f~^y5Pg{+3 zky$)_wW@-muK1GYQ`Zj=HTZjWh_cW%<$dQaH;ZSs#61i=q;=|4eERzDv?tLb8IaohN zMs>aZ)a&NOHp|`?UQtUwC%mq5{0+@Dxi?2nbNt%p+L|XP-@5)i@4fZ%gxHQuPBfEqN<_chw|+q z?7CO}#tE50UphkOW@_(QXLmJ9+EA!Q+vH-SFn8Q$ zY{^!k9XG9sx|%)b8xgns^}5C3dSV-0jx7!vRd}}`h4Xde&bLfqc?Ef;3m(q>)xyJ% zEUwvoVUwp&`9h_~dRtG;dfHhjaaC10R8f2GftEefpUXU2>iW6nsqeEgQL)UoF4cD0 zOU0~e!vC@nP8mEhSLEKKZBp9i-htEdhDufy7=H{}5x>s&cJBP}8IA2?3l><}yDwq- z))s_Fk5hYgLwC~cfT-xFHL1e;E{YX?&T>+`G4|~6AHBKb_LtP@C%5UoQ%%iD6Zyn# z{T;k2>|dYe{QKj;bf^k_m6My|>TCWUx~5ZJ==RoidlUb-W81WMnfW5$h!LfSwlzqX zD_!(+?r+i(e#EPOw@?4JL5aC@Z8!7^pEdbMh4S{3(q$%Vqs&70EW9F4M^E9@s0LvlG42g@?ZyTohx(^|rY> zD`9rA=A|7^78@F`A9>~MmRCcEc^y1FB2Rdu`Iv<(Yh|NQEiDw|)Y7lt#It93ec7?9 z=;>!I{Ok7C%eHMG_H{Gjj$3qk!6@3rR6|FHPY+UxssgiN%Sb1qi#kD0Ch@x^RT68L z*}8jw+xzE-(wu}IP=7Io*s{Z!-O9p-X z!~KQyyv1WxPCfPxymj`7SXJ6KebJiV>Kt=YW1P>wt`?f5VO6@Wc)M?{n?^EocIwlo zb3|tPy;)kWKhECr;O8vU-_piLba|wGJ~=F>pKg;T3)+L^*N0sn$_iUm@m1&6FQ}L* z2;DYbV&Ev*nD~11v;m7;Rpr#!3af^eGTfTj`b)(mg1JA>yBQ2MecT)ltJdne1`ZK z8>jdjW`eQToOvo8Lfq-LDIwt;{dCjRz~hG6-ELc6XhIYR&M5z`{lw*>&i(S`^Cu3N zr8sal^dPlk7L(*!X=)r%5Xxj^nAny+AL0|Q;_j-cKe?ev zEbCtQ)#Lr{?_SV$o6$G}is_X}^UGMpG!GS1|M99FMhumPxZYOR?ypAAG`q;U%-Anw z$ra7|0irQx4?+}#AKV+W$x&M0J~U1(u+aRTwcSdrn6@lWnCE-4{r&2?fB=R2wW-3F z*NUY=zKyvtHg32*ci8ME?fXhU-6l@@|H0R7|23cKcn{*i?m;52$+LS93GTSf?w4Ur zJKZ$3b@WW#aourchfTMc~OT>OQ#I_K7ArG2=` zuuZlayLR&8h0Yfk$0v$gKG*y>K={ULsk;&)r^RX(z0BEhD5iK-c8N07QdOv>8Of>o(ZIDgGTZ?@y08nq6M$*wUO>+UcgHHCf=+t!{k*(Yht7tf5klONk|G|Ex>|)Bqim5yl(_%@in3|%&^coDN>ZTS_ zx1!ZKEw5)9w7ehjmiHe{%iE{Bme;Y*;Ni66rZJf{(DNS^{=)-(Wy_`=uYWV}nyyv% z{;N!+-&)0&`kM^Ye1xB^4O~)58BLpo7CNA3N^1|Ir-i2*&!X^up?7QeJV4+*h;aM) zL^LSSirQq>w~c4ih;N%y{StTfJg^uk^2O+a}T9!aRN3EctVFN;_9;9lSO2Oul3LmG3eSJEmL|Ylsud zOk6EZ{XI?6A(QYSjo$1Mlg&awEQmZ!@Sp z?ipeISjZu$?(mAaZ6e$i;bPw_jkGI*hK4quT;nt#7tiaH8j$)f4TveL0bvM1MW8ew zqRZaQvV9WxX67FquSfapm1HPRm~)^NpGupsskC#r)Q_X7;hPJ#o`1Ds671ZHme;8= z6pd^qEQx68%bY)E|lWQ_Pd|@ZOlJD<5AVY<4=iy|Mmd2&ez(+g<-LXz>mc`p;BDm)|sx zR&E%g;6Go*Rq9Q$>+;_{(sk@HM4`SU=jOycI(bEXeJ-?x%{m^#>*^xq>KP`*9j}H2 zK4-0tJehi@hDskZK0QCwsBOTB_d&W(4m#~Kcr)1LuIA#~8@<*=w-{{;_dk?#7ltdV z_4*_CC(BJ;@Zo~`@k_HUuV^+55RQT2N>^lM|C(n-IiZJQ;?BR$nF7PrI&8Sow>!RL zb}PO*db>1Fe{i|w`gZ{^T+P;0rmjG~kL^=KJ8F|yqdfn%EjITBJ8BpV(?W$|Qduwz z%vNR8*@^_iDEQw57)G>9vH=X^NQD#91GwOX5iB^tb8_6}{(iejFpTW3V7FTFM;ng6 z^Tt8HtmdhW@)+nR&E2=@O^EMHyV=#!#0Pl+qE>22X?B0d2YGh03xhn??82H-w_K5D zvm3k_HM;>_nqAq49lAX?yXV=>Zti@Sq}PQa2bRZQFS;_I{Y7o|#1*jIU9UIsla`40 z3zH_zq+=q6k}oyxA8YKx9klpaQuAr2nl|gR#xrP~xynVB+_WW=cH%e!lgCQ6a$)

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z@ZA5#l+y4w?wlC#Bi-s88o)|9F+l*1MK&k!Q3o1e$YU6Q(>3ZvJjvs_wNCX2S zaLQFeL-XwENf4)_i|)mobY%7En1S>p$kK%Y82Q*;i-H6N(uxmYeNJJZr**8r9#_=} z2H*t2Q|Bb^qPJq>CNKaa3o&`lOcVMQw35O4oKl4_gD`B_!u1)Qe50K$1^Mu9 z#xMZK7c-$i)TY3>6%4?sR_V0t!U6gfa5I4c7Pe5S~12D=}3f9LQQt4|( fs4LsR`tSCpHIXUxbeiZk(Txe#(J^YPatHhe^KbyK diff --git a/QDMA/linux-kernel/apps/dma-perf/version.h b/QDMA/linux-kernel/apps/dma-perf/version.h deleted file mode 100755 index 53a766a5e..000000000 --- a/QDMA/linux-kernel/apps/dma-perf/version.h +++ /dev/null @@ -1,19 +0,0 @@ -/* - * This file is part of the QDMA userspace application - * to enable the user to execute the QDMA functionality - * - * Copyright (c) 2018-2022, Xilinx, Inc. All rights reserved. - * Copyright (c) 2022-2023, Advanced Micro Devices, Inc. All rights reserved. - * - * This source code is licensed under BSD-style license (found in the - * LICENSE file in the root directory of this source tree) - */ - -#ifndef __DMA_PERF_VERSION_H -#define __DMA_PERF_VERSION_H - -#define PROGNAME "dma-perf" -#define VERSION "2023.2.0" -#define COPYRIGHT "Copyright (c) 2022-2023 Advanced Micro Devices Inc." - -#endif diff --git a/QDMA/linux-kernel/apps/dma-to-device/Makefile b/QDMA/linux-kernel/apps/dma-to-device/Makefile deleted file mode 100755 index bccb83465..000000000 --- a/QDMA/linux-kernel/apps/dma-to-device/Makefile +++ /dev/null @@ -1,39 +0,0 @@ -# -#/* -# * This file is part of the QDMA userspace application -# * to enable the user to execute the QDMA functionality -# * -# * Copyright (c) 2018-2022, Xilinx, Inc. All rights reserved. -# * Copyright (c) 2022-2023, Advanced Micro Devices, Inc. All rights reserved. -# * -# * This source code is licensed under BSD-style license (found in the -# * LICENSE file in the root directory of this source tree) -# */ - -CC ?= gcc - -CFLAGS += -g -#CFLAGS += -O2 -fno-inline -Wall -Wstrict-prototypes -CFLAGS += -I. -I../include -I../dma-utils -CFLAGS += $(EXTRA_FLAGS) - -DMA-TO-DEVICE = dma-to-device -DMA-UTILS_OBJS := $(patsubst %.c,%.o,$(wildcard ../dma-utils/*.c)) -DMA-TO-DEVICE_OBJS := dma_to_device.o -DMA-TO-DEVICE_OBJS += $(DMA-UTILS_OBJS) - -ifneq ($(CROSS_COMPILE_FLAG),) - CC=$(CROSS_COMPILE_FLAG)gcc -endif - -all: clean dma-to-device - -dma-to-device: $(DMA-TO-DEVICE_OBJS) - $(CC) -lrt -o $@ $< -D_FILE_OFFSET_BITS=64 -D_GNU_SOURCE -D_LARGE_FILE_SOURCE - -%.o: %.c - $(CC) $(CFLAGS) -c -std=c99 -o $@ $< -D_FILE_OFFSET_BITS=64 -D_GNU_SOURCE -D_LARGE_FILE_SOURCE -D_AIO_AIX_SOURCE - -clean: - @rm -f *.o */*.o ../dma-utils/*.o - rm -rf *.o *.bin dma-to-device diff --git a/QDMA/linux-kernel/apps/dma-to-device/dma_to_device.c b/QDMA/linux-kernel/apps/dma-to-device/dma_to_device.c deleted file mode 100755 index 49d53b0c4..000000000 --- a/QDMA/linux-kernel/apps/dma-to-device/dma_to_device.c +++ /dev/null @@ -1,265 +0,0 @@ -/* - * This file is part of the QDMA userspace application - * to enable the user to execute the QDMA functionality - * - * Copyright (c) 2018-2022, Xilinx, Inc. All rights reserved. - * Copyright (c) 2022-2023, Advanced Micro Devices, Inc. All rights reserved. - * - * This source code is licensed under BSD-style license (found in the - * LICENSE file in the root directory of this source tree) - */ - -#define _DEFAULT_SOURCE -#define _XOPEN_SOURCE 500 -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include - -#include "dma_xfer_utils.c" - -#define DEVICE_NAME_DEFAULT "/dev/qdma01000-MM-0" -#define SIZE_DEFAULT (32) -#define COUNT_DEFAULT (1) - -static struct option const long_opts[] = { - {"device", required_argument, NULL, 'd'}, - {"address", required_argument, NULL, 'a'}, - {"size", required_argument, NULL, 's'}, - {"offset", required_argument, NULL, 'o'}, - {"count", required_argument, NULL, 'c'}, - {"data infile", required_argument, NULL, 'f'}, - {"data outfile", required_argument, NULL, 'w'}, - {"help", no_argument, NULL, 'h'}, - {"verbose", no_argument, NULL, 'v'}, - {0, 0, 0, 0} -}; - -static int test_dma(char *devname, uint64_t addr, uint64_t size, - uint64_t offset, uint64_t count, char *infname, char *); - -static void usage(const char *name) -{ - int i = 0; - - fprintf(stdout, "%s\n\n", name); - fprintf(stdout, "usage: %s [OPTIONS]\n\n", name); - fprintf(stdout, - "Write via SGDMA, optionally read input from a file.\n\n"); - - fprintf(stdout, " -%c (--%s) device (defaults to %s)\n", - long_opts[i].val, long_opts[i].name, DEVICE_NAME_DEFAULT); - i++; - fprintf(stdout, " -%c (--%s) the start address on the AXI bus\n", - long_opts[i].val, long_opts[i].name); - i++; - fprintf(stdout, - " -%c (--%s) size of a single transfer in bytes, default %d,\n", - long_opts[i].val, long_opts[i].name, SIZE_DEFAULT); - i++; - fprintf(stdout, " -%c (--%s) page offset of transfer\n", - long_opts[i].val, long_opts[i].name); - i++; - fprintf(stdout, " -%c (--%s) number of transfers, default %d\n", - long_opts[i].val, long_opts[i].name, COUNT_DEFAULT); - i++; - fprintf(stdout, " -%c (--%s) filename to read the data from.\n", - long_opts[i].val, long_opts[i].name); - i++; - fprintf(stdout, - " -%c (--%s) filename to write the data of the transfers\n", - long_opts[i].val, long_opts[i].name); - i++; - fprintf(stdout, " -%c (--%s) print usage help and exit\n", - long_opts[i].val, long_opts[i].name); - i++; - fprintf(stdout, " -%c (--%s) verbose output\n", - long_opts[i].val, long_opts[i].name); -} - -int main(int argc, char *argv[]) -{ - int cmd_opt; - char *device = DEVICE_NAME_DEFAULT; - uint64_t address = 0; - uint64_t size = SIZE_DEFAULT; - uint64_t offset = 0; - uint64_t count = COUNT_DEFAULT; - char *infname = NULL; - char *ofname = NULL; - - while ((cmd_opt = - getopt_long(argc, argv, "vhc:f:d:a:s:o:w:", long_opts, - NULL)) != -1) { - switch (cmd_opt) { - case 0: - /* long option */ - break; - case 'd': - /* device node name */ - //fprintf(stdout, "'%s'\n", optarg); - device = strdup(optarg); - break; - case 'a': - /* RAM address on the AXI bus in bytes */ - address = getopt_integer(optarg); - break; - case 's': - /* size in bytes */ - size = getopt_integer(optarg); - break; - case 'o': - offset = getopt_integer(optarg) & 4095; - break; - /* count */ - case 'c': - count = getopt_integer(optarg); - break; - /* count */ - case 'f': - infname = strdup(optarg); - break; - case 'w': - ofname = strdup(optarg); - break; - /* print usage help and exit */ - case 'v': - verbose = 1; - break; - case 'h': - default: - usage(argv[0]); - exit(0); - break; - } - } - - if (verbose) - fprintf(stdout, - "dev %s, address 0x%lx, size 0x%lx, offset 0x%lx, count %lu\n", - device, address, size, offset, count); - - return test_dma(device, address, size, offset, count, infname, ofname); -} - -static int test_dma(char *devname, uint64_t addr, uint64_t size, - uint64_t offset, uint64_t count, char *infname, - char *ofname) -{ - uint64_t i; - ssize_t rc; - char *buffer = NULL; - char *allocated = NULL; - struct timespec ts_start, ts_end; - int infile_fd = -1; - int outfile_fd = -1; - int fpga_fd = open(devname, O_RDWR); - double total_time = 0; - double result; - double avg_time = 0; - - - if (fpga_fd < 0) { - fprintf(stderr, "unable to open device %s, %d.\n", - devname, fpga_fd); - perror("open device"); - return -EINVAL; - } - - if (infname) { - infile_fd = open(infname, O_RDONLY); - if (infile_fd < 0) { - fprintf(stderr, "unable to open input file %s, %d.\n", - infname, infile_fd); - perror("open input file"); - rc = -EINVAL; - goto out; - } - } - - if (ofname) { - outfile_fd = - open(ofname, O_RDWR | O_CREAT | O_TRUNC | O_SYNC, - 0666); - if (outfile_fd < 0) { - fprintf(stderr, "unable to open output file %s, %d.\n", - ofname, outfile_fd); - perror("open output file"); - rc = -EINVAL; - goto out; - } - } - - posix_memalign((void **)&allocated, 4096 /*alignment */ , size + 4096); - if (!allocated) { - fprintf(stderr, "OOM %lu.\n", size + 4096); - rc = -ENOMEM; - goto out; - } - buffer = allocated + offset; - if (verbose) - fprintf(stdout, "host buffer 0x%lx = %p\n", - size + 4096, buffer); - - if (infile_fd >= 0) { - rc = read_to_buffer(infname, infile_fd, buffer, size, 0); - if (rc < 0) - goto out; - } - - for (i = 0; i < count; i++) { - /* write buffer to AXI MM address using SGDMA */ - clock_gettime(CLOCK_MONOTONIC, &ts_start); - - rc = write_from_buffer(devname, fpga_fd, buffer, size, addr); - if (rc < 0) - goto out; - - rc = clock_gettime(CLOCK_MONOTONIC, &ts_end); - /* subtract the start time from the end time */ - timespec_sub(&ts_end, &ts_start); - total_time += (ts_end.tv_sec + ((double)ts_end.tv_nsec/NSEC_DIV)); - /* a bit less accurate but side-effects are accounted for */ - if (verbose) - fprintf(stdout, - "#%lu: CLOCK_MONOTONIC %ld.%09ld sec. write %lu bytes\n", - i, ts_end.tv_sec, ts_end.tv_nsec, size); - - if (outfile_fd >= 0) { - rc = write_from_buffer(ofname, outfile_fd, buffer, - size, i * size); - if (rc < 0) - goto out; - } - } - avg_time = (double)total_time/(double)count; - result = ((double)size)/avg_time; - if (verbose) - printf("** Avg time device %s, total time %f nsec, avg_time = %f, size = %lu, BW = %f bytes/sec\n", - devname, total_time, avg_time, size, result); - dump_throughput_result(size, result); - - rc = 0; - -out: - close(fpga_fd); - if (infile_fd >= 0) - close(infile_fd); - if (outfile_fd >= 0) - close(outfile_fd); - free(allocated); - - return rc; -} diff --git a/QDMA/linux-kernel/apps/dma-to-device/version.h b/QDMA/linux-kernel/apps/dma-to-device/version.h deleted file mode 100755 index b14cefc12..000000000 --- a/QDMA/linux-kernel/apps/dma-to-device/version.h +++ /dev/null @@ -1,19 +0,0 @@ -/* - * This file is part of the QDMA userspace application - * to enable the user to execute the QDMA functionality - * - * Copyright (c) 2018-2022, Xilinx, Inc. All rights reserved. - * Copyright (c) 2022-2023, Advanced Micro Devices, Inc. All rights reserved. - * - * This source code is licensed under BSD-style license (found in the - * LICENSE file in the root directory of this source tree) - */ - -#ifndef __DMA_TO_DEVICE_VERSION_H -#define __DMA_TO_DEVICE_VERSION_H - -#define PROGNAME "dma-to-device" -#define VERSION "2023.2.0" -#define COPYRIGHT "Copyright (c) 2022-2023 Advanced Micro Devices Inc." - -#endif diff --git a/QDMA/linux-kernel/apps/dma-utils/Makefile b/QDMA/linux-kernel/apps/dma-utils/Makefile deleted file mode 100755 index f6d9ecd1d..000000000 --- a/QDMA/linux-kernel/apps/dma-utils/Makefile +++ /dev/null @@ -1,26 +0,0 @@ -# -#/* -# * This file is part of the QDMA userspace application -# * to enable the user to execute the QDMA functionality -# * -# * Copyright (c) 2018-2022, Xilinx, Inc. All rights reserved. -# * Copyright (c) 2022-2023, Advanced Micro Devices, Inc. All rights reserved. -# * -# * This source code is licensed under BSD-style license (found in the -# * LICENSE file in the root directory of this source tree) -# */ - -CC ?= gcc - -CFLAGS += -g -#CFLAGS += -O2 -fno-inline -Wall -Wstrict-prototypes -CFLAGS += -I. -I../include -CFLAGS += $(EXTRA_FLAGS) - -all: dmautils.o dmactl.o dmactl_reg.o dmaxfer.o dma_xfer_utils.o - -%.o: %.c - $(CC) $(CFLAGS) -c -std=c99 -o $@ $< -D_FILE_OFFSET_BITS=64 -D_GNU_SOURCE -D_LARGE_FILE_SOURCE -D_AIO_AIX_SOURCE - -clean: - rm -rf *.o diff --git a/QDMA/linux-kernel/apps/dma-utils/dma_xfer_utils.c b/QDMA/linux-kernel/apps/dma-utils/dma_xfer_utils.c deleted file mode 100755 index d3fefd26d..000000000 --- a/QDMA/linux-kernel/apps/dma-utils/dma_xfer_utils.c +++ /dev/null @@ -1,214 +0,0 @@ -/* - * This file is part of the QDMA userspace application - * to enable the user to execute the QDMA functionality - * - * Copyright (c) 2018-2022, Xilinx, Inc. All rights reserved. - * Copyright (c) 2022-2023, Advanced Micro Devices, Inc. All rights reserved. - * - * This source code is licensed under BSD-style license (found in the - * LICENSE file in the root directory of this source tree) - */ - -#include -#include -#include -#include -#include -#include - -/* - * man 2 write: - * On Linux, write() (and similar system calls) will transfer at most - * 0x7ffff000 (2,147,479,552) bytes, returning the number of bytes - * actually transferred. (This is true on both 32-bit and 64-bit - * systems.) - */ - -#define RW_MAX_SIZE 0x7ffff000 -#define GB_DIV 1000000000 -#define MB_DIV 1000000 -#define KB_DIV 1000 -#define NSEC_DIV 1000000000 - -int verbose = 0; - -void dump_throughput_result(uint64_t size, float result) { - printf("size=%lu ", size); - if (((long long)(result)/GB_DIV)) { - printf("Average BW = %f GB/sec\n", ((double)result/GB_DIV)); - } else if (((long long)(result)/MB_DIV)) { - printf("Average BW = %f MB/sec\n", ((double)result/MB_DIV)); - } else if (((long long)(result)/KB_DIV)) { - printf("Average BW = %f KB/sec\n", ((double)result/KB_DIV)); - } else - printf("Average BW = %f Bytes/sec\n", ((double)result)); -} - -uint64_t getopt_integer(char *optarg) -{ - int rc; - uint64_t value; - - rc = sscanf(optarg, "0x%lx", &value); - if (rc <= 0) - sscanf(optarg, "%lu", &value); - //printf("sscanf() = %d, value = 0x%lx\n", rc, value); - - return value; -} - -ssize_t read_to_buffer(char *fname, int fd, char *buffer, uint64_t size, - uint64_t base) -{ - ssize_t rc; - uint64_t count = 0; - char *buf = buffer; - off_t offset = base; - - do { /* Support zero byte transfer */ - uint64_t bytes = size - count; - - if (bytes > RW_MAX_SIZE) - bytes = RW_MAX_SIZE; - - if (offset) { - rc = lseek(fd, offset, SEEK_SET); - if (rc < 0) { - fprintf(stderr, - "%s, seek off 0x%lx failed %zd.\n", - fname, offset, rc); - perror("seek file"); - return -EIO; - } - if (rc != offset) { - fprintf(stderr, - "%s, seek off 0x%lx != 0x%lx.\n", - fname, rc, offset); - return -EIO; - } - } - - /* read data from file into memory buffer */ - rc = read(fd, buf, bytes); - if (rc < 0) { - fprintf(stderr, - "%s, read off 0x%lx + 0x%lx failed %zd.\n", - fname, offset, bytes, rc); - perror("read file"); - return -EIO; - } - if (rc != bytes) { - fprintf(stderr, - "%s, R off 0x%lx, 0x%lx != 0x%lx.\n", - fname, count, rc, bytes); - return -EIO; - } - - count += bytes; - buf += bytes; - offset += bytes; - } while (count < size); - - if (count != size) { - fprintf(stderr, "%s, R failed 0x%lx != 0x%lx.\n", - fname, count, size); - return -EIO; - } - return count; -} - -ssize_t write_from_buffer(char *fname, int fd, char *buffer, uint64_t size, - uint64_t base) -{ - ssize_t rc; - uint64_t count = 0; - char *buf = buffer; - off_t offset = base; - - do { /* Support zero byte transfer */ - uint64_t bytes = size - count; - - if (bytes > RW_MAX_SIZE) - bytes = RW_MAX_SIZE; - - if (offset) { - rc = lseek(fd, offset, SEEK_SET); - if (rc < 0) { - fprintf(stderr, - "%s, seek off 0x%lx failed %zd.\n", - fname, offset, rc); - perror("seek file"); - return -EIO; - } - if (rc != offset) { - fprintf(stderr, - "%s, seek off 0x%lx != 0x%lx.\n", - fname, rc, offset); - return -EIO; - } - } - - /* write data to file from memory buffer */ - rc = write(fd, buf, bytes); - if (rc < 0) { - fprintf(stderr, "%s, W off 0x%lx, 0x%lx failed %zd.\n", - fname, offset, bytes, rc); - perror("write file"); - return -EIO; - } - if (rc != bytes) { - fprintf(stderr, "%s, W off 0x%lx, 0x%lx != 0x%lx.\n", - fname, offset, rc, bytes); - return -EIO; - } - - count += bytes; - buf += bytes; - offset += bytes; - } while (count < size); - - if (count != size) { - fprintf(stderr, "%s, R failed 0x%lx != 0x%lx.\n", - fname, count, size); - return -EIO; - } - return count; -} - - -/* Subtract timespec t2 from t1 - * - * Both t1 and t2 must already be normalized - * i.e. 0 <= nsec < 1000000000 - */ -static int timespec_check(struct timespec *t) -{ - if ((t->tv_nsec < 0) || (t->tv_nsec >= 1000000000)) - return -1; - return 0; - -} - -void timespec_sub(struct timespec *t1, struct timespec *t2) -{ - if (timespec_check(t1) < 0) { - fprintf(stderr, "invalid time #1: %lld.%.9ld.\n", - (long long)t1->tv_sec, t1->tv_nsec); - return; - } - if (timespec_check(t2) < 0) { - fprintf(stderr, "invalid time #2: %lld.%.9ld.\n", - (long long)t2->tv_sec, t2->tv_nsec); - return; - } - t1->tv_sec -= t2->tv_sec; - t1->tv_nsec -= t2->tv_nsec; - if (t1->tv_nsec >= 1000000000) { - t1->tv_sec++; - t1->tv_nsec -= 1000000000; - } else if (t1->tv_nsec < 0) { - t1->tv_sec--; - t1->tv_nsec += 1000000000; - } -} - diff --git a/QDMA/linux-kernel/apps/dma-utils/dmactl.c b/QDMA/linux-kernel/apps/dma-utils/dmactl.c deleted file mode 100755 index 988d482ee..000000000 --- a/QDMA/linux-kernel/apps/dma-utils/dmactl.c +++ /dev/null @@ -1,884 +0,0 @@ -/* - * This file is part of the QDMA userspace application - * to enable the user to execute the QDMA functionality - * - * Copyright (c) 2019-2022, Xilinx, Inc. All rights reserved. - * Copyright (c) 2022-2023, Advanced Micro Devices, Inc. All rights reserved. - * - * This source code is licensed under BSD-style license (found in the - * LICENSE file in the root directory of this source tree) - */ -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include "qdma_nl.h" -#include "dmaxfer.h" -#include "dmactl_internal.h" - -#define MAX_KMALLOC_SIZE (4*1024*1024) - -//#define DEBUG 1 -/* - * netlink message - */ -struct xnl_hdr { - struct nlmsghdr n; - struct genlmsghdr g; -}; - -struct xnl_cb { - int fd; - unsigned short family; - unsigned int snd_seq; - unsigned int rcv_seq; -}; - -struct xnl_gen_msg { - struct xnl_hdr hdr; - char data[0]; -}; - -void xnl_close(struct xnl_cb *cb) -{ - close(cb->fd); -} - -static int xnl_send(struct xnl_cb *cb, struct xnl_hdr *hdr, - void (*log_err)(const char *)) -{ - int rv; - struct sockaddr_nl addr = { - .nl_family = AF_NETLINK, - }; - - hdr->n.nlmsg_seq = cb->snd_seq; - cb->snd_seq++; - - rv = sendto(cb->fd, (char *)hdr, hdr->n.nlmsg_len, 0, - (struct sockaddr *)&addr, sizeof(addr)); - if (rv != hdr->n.nlmsg_len) { - if (log_err) - log_err("nl send err"); - return -1; - } - - return 0; -} - -static int xnl_recv(struct xnl_cb *cb, struct xnl_hdr *hdr, int dlen, - void (*log_err)(const char *)) -{ - int rv; - - memset(hdr, 0, sizeof(struct xnl_gen_msg) + dlen); - - rv = recv(cb->fd, hdr, dlen, 0); - if (rv < 0) { - if (log_err) - log_err("nl recv err"); - return -1; - } - /* as long as there is attribute, even if it is shorter than expected */ - if (!NLMSG_OK((&hdr->n), rv) && (rv <= sizeof(struct xnl_hdr))) { - char err_msg[100] = {'\0'}; - - snprintf(err_msg, 100, - "nl recv:, invalid message, cmd 0x%x, %d,%d.\n", - hdr->g.cmd, dlen, rv); - if (log_err) - log_err(err_msg); - return -1; - } - - if (hdr->n.nlmsg_type == NLMSG_ERROR) { - char err_msg[100] = {'\0'}; - - snprintf(err_msg, 100, "nl recv, msg error, cmd 0x%x\n", - hdr->g.cmd); - if (log_err) - log_err(err_msg); - return -1; - } - - return 0; -} - -static inline struct xnl_gen_msg *xnl_msg_alloc(unsigned int dlen, - void (*log_err)(const char *)) -{ - struct xnl_gen_msg *msg; - unsigned int extra_mem = (XNL_ATTR_MAX * (sizeof(struct nlattr) + - sizeof(uint32_t))); - - if (dlen) - extra_mem = dlen; - - msg = malloc(sizeof(struct xnl_gen_msg) + extra_mem); - if (!msg) { - char err_msg[100] = {'\0'}; - - snprintf(err_msg, 100, "%s: OOM, %u.\n", - __FUNCTION__, extra_mem); - if (log_err) - log_err(err_msg); - return NULL; - } - - memset(msg, 0, sizeof(struct xnl_gen_msg) + extra_mem); - return msg; -} - -static int xnl_connect(struct xnl_cb *cb, int vf, void (*log_err)(const char *)) -{ - int fd; - struct sockaddr_nl addr; - struct xnl_gen_msg *msg = xnl_msg_alloc(0, log_err); - struct xnl_hdr *hdr = &msg->hdr; - struct nlattr *attr; - int rv = -1; - - fd = socket(AF_NETLINK, SOCK_RAW, NETLINK_GENERIC); - if (fd < 0) { - if (log_err) - log_err("nl socket err"); - rv = fd; - goto out; - } - cb->fd = fd; - - memset(&addr, 0, sizeof(struct sockaddr_nl)); - addr.nl_family = AF_NETLINK; - rv = bind(fd, (struct sockaddr *)&addr, sizeof(struct sockaddr_nl)); - if (rv < 0) { - if (log_err) - log_err("nl bind err"); - goto out; - } - - hdr->n.nlmsg_type = GENL_ID_CTRL; - hdr->n.nlmsg_flags = NLM_F_REQUEST; - hdr->n.nlmsg_pid = getpid(); - hdr->n.nlmsg_len = NLMSG_LENGTH(GENL_HDRLEN); - - hdr->g.cmd = CTRL_CMD_GETFAMILY; - hdr->g.version = XNL_VERSION; - - attr = (struct nlattr *)(hdr + 1); - attr->nla_type = CTRL_ATTR_FAMILY_NAME; - cb->family = CTRL_ATTR_FAMILY_NAME; - - if (vf) { - attr->nla_len = strlen(XNL_NAME_VF) + 1 + NLA_HDRLEN; - memcpy((char *)(attr + 1), XNL_NAME_VF, sizeof(XNL_NAME_VF) - 1); - } else { - attr->nla_len = strlen(XNL_NAME_PF) + 1 + NLA_HDRLEN; - memcpy((char *)(attr + 1), XNL_NAME_PF, sizeof(XNL_NAME_PF) - 1); - } - hdr->n.nlmsg_len += NLMSG_ALIGN(attr->nla_len); - - rv = xnl_send(cb, hdr, log_err); - if (rv < 0) - goto out; - - rv = xnl_recv(cb, hdr, XNL_RESP_BUFLEN_MIN, NULL); - if (rv < 0) - goto out; - - attr = (struct nlattr *)((char *)attr + NLA_ALIGN(attr->nla_len)); - /* family ID */ - if (attr->nla_type == CTRL_ATTR_FAMILY_ID) - cb->family = *(__u16 *)(attr + 1); - - rv = 0; - -out: - free(msg); - return rv; -} - - -static void xnl_msg_set_hdr(struct xnl_hdr *hdr, int family, int op) -{ - hdr->n.nlmsg_len = NLMSG_LENGTH(GENL_HDRLEN); - hdr->n.nlmsg_type = family; - hdr->n.nlmsg_flags = NLM_F_REQUEST; - hdr->n.nlmsg_pid = getpid(); - - hdr->g.cmd = op; -} - -static int xnl_msg_add_int_attr(struct xnl_hdr *hdr, enum xnl_attr_t type, - unsigned int v) -{ - struct nlattr *attr = (struct nlattr *)((char *)hdr + hdr->n.nlmsg_len); - - attr->nla_type = (__u16)type; - attr->nla_len = sizeof(__u32) + NLA_HDRLEN; - *(__u32 *)(attr+ 1) = v; - - hdr->n.nlmsg_len += NLMSG_ALIGN(attr->nla_len); - return 0; -} - -static int xnl_msg_add_str_attr(struct xnl_hdr *hdr, enum xnl_attr_t type, - char *s) -{ - struct nlattr *attr = (struct nlattr *)((char *)hdr + hdr->n.nlmsg_len); - int len = strlen(s); - - attr->nla_type = (__u16)type; - attr->nla_len = len + 1 + NLA_HDRLEN; - - strcpy((char *)(attr + 1), s); - - hdr->n.nlmsg_len += NLMSG_ALIGN(attr->nla_len); - return 0; -} - -static int recv_attrs(struct xnl_hdr *hdr, struct xcmd_info *xcmd, - uint32_t *attrs) -{ - unsigned char *p = (unsigned char *)(hdr + 1); - int maxlen = hdr->n.nlmsg_len - NLMSG_LENGTH(GENL_HDRLEN); - - while (maxlen > 0) { - struct nlattr *na = (struct nlattr *)p; - int len = NLA_ALIGN(na->nla_len); - - if (na->nla_type >= XNL_ATTR_MAX) { - void (*log_err)(const char *) = xcmd->log_msg_dump; - char err_msg[100] = {'\0'}; - - snprintf(err_msg, 100, - "unknown attr type %d, len %d.\n", - na->nla_type, na->nla_len); - if (log_err) - log_err(err_msg); - return -EINVAL; - } - - if (na->nla_type == XNL_ATTR_GENMSG) { - if (xcmd->log_msg_dump) - xcmd->log_msg_dump((const char *)(na + 1)); - } else { - attrs[na->nla_type] = *(uint32_t *)(na + 1); - } - - p += len; - maxlen -= len; - } - - return 0; -} - -static int get_cmd_resp_buf_len(enum xnl_op_t op, struct xcmd_info *xcmd) -{ - int buf_len = XNL_RESP_BUFLEN_MAX; - unsigned int row_len = 50; - - switch (op) { - case XNL_CMD_Q_DESC: - row_len *= 2; - case XNL_CMD_Q_CMPT: - buf_len += ((xcmd->req.qparm.range_end - - xcmd->req.qparm.range_start)*row_len); - break; - case XNL_CMD_INTR_RING_DUMP: - buf_len += ((xcmd->req.intr.end_idx - - xcmd->req.intr.start_idx)*row_len); - break; - case XNL_CMD_DEV_LIST: - case XNL_CMD_DEV_INFO: - case XNL_CMD_DEV_CAP: - case XNL_CMD_Q_START: - case XNL_CMD_Q_STOP: - case XNL_CMD_Q_DEL: - case XNL_CMD_GLOBAL_CSR: - return buf_len; - case XNL_CMD_Q_ADD: - case XNL_CMD_Q_DUMP: - case XNL_CMD_Q_LIST: - case XNL_CMD_Q_CMPT_READ: - break; - case XNL_CMD_REG_DUMP: - case XNL_CMD_REG_INFO_READ: - buf_len = XNL_RESP_BUFLEN_MAX * 6; - break; - case XNL_CMD_DEV_STAT: - buf_len = XNL_RESP_BUFLEN_MAX; - break; - default: - buf_len = XNL_RESP_BUFLEN_MIN; - return buf_len; - } - if ((xcmd->req.qparm.flags & XNL_F_QDIR_BOTH) == XNL_F_QDIR_BOTH) - buf_len *= 2; - if(xcmd->req.qparm.num_q > 1) - buf_len *= xcmd->req.qparm.num_q; - if(buf_len > MAX_KMALLOC_SIZE) - buf_len = MAX_KMALLOC_SIZE; - return buf_len; -} - - -static int recv_nl_msg(struct xnl_hdr *hdr, struct xcmd_info *xcmd, - uint32_t *attrs) -{ - if (!attrs) - return 0; - recv_attrs(hdr, xcmd, attrs); - - if (attrs[XNL_ATTR_ERROR] != 0) - return (int)attrs[XNL_ATTR_ERROR]; - - return 0; -} - -static void xnl_msg_add_extra_config_attrs(struct xnl_hdr *hdr, - struct xcmd_info *xcmd) -{ - if (xcmd->req.qparm.sflags & (1 << QPARM_RNGSZ_IDX)) - xnl_msg_add_int_attr(hdr, XNL_ATTR_QRNGSZ_IDX, - xcmd->req.qparm.qrngsz_idx); - if (xcmd->req.qparm.sflags & (1 << QPARM_C2H_BUFSZ_IDX)) - xnl_msg_add_int_attr(hdr, XNL_ATTR_C2H_BUFSZ_IDX, - xcmd->req.qparm.c2h_bufsz_idx); - if (xcmd->req.qparm.sflags & (1 << QPARM_CMPTSZ)) - xnl_msg_add_int_attr(hdr, XNL_ATTR_CMPT_DESC_SIZE, - xcmd->req.qparm.cmpt_entry_size); - if (xcmd->req.qparm.sflags & (1 << QPARM_SW_DESC_SZ)) - xnl_msg_add_int_attr(hdr, XNL_ATTR_SW_DESC_SIZE, - xcmd->req.qparm.sw_desc_sz); - if (xcmd->req.qparm.sflags & (1 << QPARM_CMPT_TMR_IDX)) - xnl_msg_add_int_attr(hdr, XNL_ATTR_CMPT_TIMER_IDX, - xcmd->req.qparm.cmpt_tmr_idx); - if (xcmd->req.qparm.sflags & (1 << QPARM_CMPT_CNTR_IDX)) - xnl_msg_add_int_attr(hdr, XNL_ATTR_CMPT_CNTR_IDX, - xcmd->req.qparm.cmpt_cntr_idx); - if (xcmd->req.qparm.sflags & (1 << QPARM_MM_CHANNEL)) - xnl_msg_add_int_attr(hdr, XNL_ATTR_MM_CHANNEL, - xcmd->req.qparm.mm_channel); - if (xcmd->req.qparm.sflags & (1 << QPARM_CMPT_TRIG_MODE)) - xnl_msg_add_int_attr(hdr, XNL_ATTR_CMPT_TRIG_MODE, - xcmd->req.qparm.cmpt_trig_mode); - if (xcmd->req.qparm.sflags & (1 << QPARM_PING_PONG_EN)) { - xnl_msg_add_int_attr(hdr, XNL_ATTR_PING_PONG_EN, - xcmd->req.qparm.ping_pong_en); - } - if (xcmd->req.qparm.sflags & (1 << QPARM_KEYHOLE_EN)) { - xnl_msg_add_int_attr(hdr, XNL_ATTR_APERTURE_SZ, - xcmd->req.qparm.aperture_sz); - } -} - -static int xnl_parse_response(struct xnl_cb *cb, struct xnl_hdr *hdr, - struct xcmd_info *xcmd, unsigned int dlen, - uint32_t *attrs) -{ - struct nlattr *attr; - int rv; - - rv = xnl_recv(cb, hdr, dlen, xcmd->log_msg_dump); - if (rv < 0) - goto out; - - rv = recv_nl_msg(hdr, xcmd, attrs); -out: - return rv; -} - -static int xnl_send_cmd(struct xnl_cb *cb, struct xnl_hdr *hdr, - struct xcmd_info *xcmd, unsigned int dlen) -{ - struct nlattr *attr; - int rv; - - attr = (struct nlattr *)(hdr + 1); - - xnl_msg_add_int_attr(hdr, XNL_ATTR_DEV_IDX, xcmd->if_bdf); - - switch(xcmd->op) { - case XNL_CMD_DEV_LIST: - case XNL_CMD_DEV_INFO: - case XNL_CMD_DEV_STAT: - case XNL_CMD_DEV_STAT_CLEAR: - /* no parameter */ - break; - case XNL_CMD_Q_LIST: - xnl_msg_add_int_attr(hdr, XNL_ATTR_QIDX, xcmd->req.qparm.idx); - xnl_msg_add_int_attr(hdr, XNL_ATTR_NUM_Q, xcmd->req.qparm.num_q); - case XNL_CMD_Q_ADD: - xnl_msg_add_int_attr(hdr, XNL_ATTR_QIDX, xcmd->req.qparm.idx); - xnl_msg_add_int_attr(hdr, XNL_ATTR_NUM_Q, xcmd->req.qparm.num_q); - xnl_msg_add_int_attr(hdr, XNL_ATTR_QFLAG, xcmd->req.qparm.flags); - xnl_msg_add_int_attr(hdr, XNL_ATTR_RSP_BUF_LEN, dlen ); - break; - case XNL_CMD_Q_START: - xnl_msg_add_extra_config_attrs(hdr, xcmd); - case XNL_CMD_Q_STOP: - case XNL_CMD_Q_DEL: - case XNL_CMD_Q_DUMP: - xnl_msg_add_int_attr(hdr, XNL_ATTR_QIDX, xcmd->req.qparm.idx); - xnl_msg_add_int_attr(hdr, XNL_ATTR_NUM_Q, xcmd->req.qparm.num_q); - xnl_msg_add_int_attr(hdr, XNL_ATTR_QFLAG, xcmd->req.qparm.flags); - xnl_msg_add_int_attr(hdr, XNL_ATTR_RSP_BUF_LEN, dlen); - break; - case XNL_CMD_Q_DESC: - case XNL_CMD_Q_CMPT: - xnl_msg_add_int_attr(hdr, XNL_ATTR_QIDX, xcmd->req.qparm.idx); - xnl_msg_add_int_attr(hdr, XNL_ATTR_NUM_Q, xcmd->req.qparm.num_q); - xnl_msg_add_int_attr(hdr, XNL_ATTR_QFLAG, xcmd->req.qparm.flags); - xnl_msg_add_int_attr(hdr, XNL_ATTR_RANGE_START, - xcmd->req.qparm.range_start); - xnl_msg_add_int_attr(hdr, XNL_ATTR_RANGE_END, - xcmd->req.qparm.range_end); - xnl_msg_add_int_attr(hdr, XNL_ATTR_RSP_BUF_LEN, dlen); - break; - case XNL_CMD_Q_RX_PKT: - xnl_msg_add_int_attr(hdr, XNL_ATTR_QIDX, xcmd->req.qparm.idx); - xnl_msg_add_int_attr(hdr, XNL_ATTR_NUM_Q, xcmd->req.qparm.num_q); - /* hard coded to C2H */ - xnl_msg_add_int_attr(hdr, XNL_ATTR_QFLAG, XNL_F_QDIR_C2H); - break; - case XNL_CMD_Q_CMPT_READ: - xnl_msg_add_int_attr(hdr, XNL_ATTR_QIDX, xcmd->req.qparm.idx); - xnl_msg_add_int_attr(hdr, XNL_ATTR_QFLAG, xcmd->req.qparm.flags); - /*xnl_msg_add_int_attr(hdr, XNL_ATTR_NUM_ENTRIES, - xcmd->u.qparm.num_entries);*/ - break; - case XNL_CMD_INTR_RING_DUMP: - xnl_msg_add_int_attr(hdr, XNL_ATTR_INTR_VECTOR_IDX, - xcmd->req.intr.vector); - xnl_msg_add_int_attr(hdr, XNL_ATTR_INTR_VECTOR_START_IDX, - xcmd->req.intr.start_idx); - xnl_msg_add_int_attr(hdr, XNL_ATTR_INTR_VECTOR_END_IDX, - xcmd->req.intr.end_idx); - xnl_msg_add_int_attr(hdr, XNL_ATTR_RSP_BUF_LEN, dlen); - break; - case XNL_CMD_REG_RD: - xnl_msg_add_int_attr(hdr, XNL_ATTR_REG_BAR_NUM, - xcmd->req.reg.bar); - xnl_msg_add_int_attr(hdr, XNL_ATTR_REG_ADDR, - xcmd->req.reg.reg); - break; - case XNL_CMD_REG_WRT: - xnl_msg_add_int_attr(hdr, XNL_ATTR_REG_BAR_NUM, - xcmd->req.reg.bar); - xnl_msg_add_int_attr(hdr, XNL_ATTR_REG_ADDR, - xcmd->req.reg.reg); - xnl_msg_add_int_attr(hdr, XNL_ATTR_REG_VAL, - xcmd->req.reg.val); - break; - case XNL_CMD_REG_INFO_READ: - xnl_msg_add_int_attr(hdr, XNL_ATTR_REG_BAR_NUM, - xcmd->req.reg.bar); - xnl_msg_add_int_attr(hdr, XNL_ATTR_REG_ADDR, - xcmd->req.reg.reg); - xnl_msg_add_int_attr(hdr, XNL_ATTR_NUM_REGS, - xcmd->req.reg.range_end); - xnl_msg_add_int_attr(hdr, XNL_ATTR_RSP_BUF_LEN, - dlen); - break; - case XNL_CMD_REG_DUMP: - xnl_msg_add_int_attr(hdr, XNL_ATTR_RSP_BUF_LEN, - dlen); - break; - case XNL_CMD_GLOBAL_CSR: - xnl_msg_add_int_attr(hdr, XNL_ATTR_CSR_INDEX, - 0); - xnl_msg_add_int_attr(hdr, XNL_ATTR_CSR_COUNT, - QDMA_GLOBAL_CSR_ARRAY_SZ); - break; - default: - break; - } - - rv = xnl_send(cb, hdr, xcmd->log_msg_dump); - if (rv < 0) - goto out; - -out: - return rv; -} - -void xnl_parse_dev_info_attrs(uint32_t *attrs, struct xcmd_info *xcmd) -{ - unsigned int usr_bar; - struct xnl_dev_info *dev_info = &xcmd->resp.dev_info; - - dev_info->config_bar = attrs[XNL_ATTR_DEV_CFG_BAR]; - usr_bar = (int)attrs[XNL_ATTR_DEV_USR_BAR]; - dev_info->qmax = attrs[XNL_ATTR_DEV_QSET_MAX]; - dev_info->qbase = attrs[XNL_ATTR_DEV_QSET_QBASE]; - dev_info->pci_bus = attrs[XNL_ATTR_PCI_BUS]; - dev_info->pci_dev = attrs[XNL_ATTR_PCI_DEV]; - dev_info->dev_func = attrs[XNL_ATTR_PCI_FUNC]; - - if (usr_bar+1 == 0) - dev_info->user_bar = 2; - else - dev_info->user_bar = usr_bar; -} - -void xnl_parse_dev_stat_attrs(uint32_t *attrs, struct xcmd_info *xcmd) -{ - unsigned int pkts; - struct xnl_dev_stat *dev_stat = &xcmd->resp.dev_stat; - - pkts = attrs[XNL_ATTR_DEV_STAT_MMH2C_PKTS1]; - dev_stat->mm_h2c_pkts = pkts; - pkts = attrs[XNL_ATTR_DEV_STAT_MMH2C_PKTS2]; - dev_stat->mm_h2c_pkts |= (((unsigned long long)pkts) << 32); - - pkts = attrs[XNL_ATTR_DEV_STAT_MMC2H_PKTS1]; - dev_stat->mm_c2h_pkts = pkts; - pkts = attrs[XNL_ATTR_DEV_STAT_MMC2H_PKTS2]; - dev_stat->mm_c2h_pkts |= (((unsigned long long)pkts) << 32); - - pkts = attrs[XNL_ATTR_DEV_STAT_STH2C_PKTS1]; - dev_stat->st_h2c_pkts = pkts; - pkts = attrs[XNL_ATTR_DEV_STAT_STH2C_PKTS2]; - dev_stat->st_h2c_pkts |= (((unsigned long long)pkts) << 32); - - pkts = attrs[XNL_ATTR_DEV_STAT_STC2H_PKTS1]; - dev_stat->st_c2h_pkts = pkts; - pkts = attrs[XNL_ATTR_DEV_STAT_STC2H_PKTS2]; - dev_stat->st_c2h_pkts |= (((unsigned long long)pkts) << 32); - - pkts = attrs[XNL_ATTR_DEV_STAT_PING_PONG_LATMAX1]; - dev_stat->ping_pong_lat_max = pkts; - pkts = attrs[XNL_ATTR_DEV_STAT_PING_PONG_LATMAX2]; - dev_stat->ping_pong_lat_max |= (((unsigned long long)pkts) << 32); - - pkts = attrs[XNL_ATTR_DEV_STAT_PING_PONG_LATMIN1]; - dev_stat->ping_pong_lat_min = pkts; - pkts = attrs[XNL_ATTR_DEV_STAT_PING_PONG_LATMIN2]; - dev_stat->ping_pong_lat_min |= (((unsigned long long)pkts) << 32); - - pkts = attrs[XNL_ATTR_DEV_STAT_PING_PONG_LATAVG1]; - dev_stat->ping_pong_lat_avg = pkts; - pkts = attrs[XNL_ATTR_DEV_STAT_PING_PONG_LATAVG2]; - dev_stat->ping_pong_lat_avg |= (((unsigned long long)pkts) << 32); -} - -void xnl_parse_dev_cap_attrs(struct xnl_hdr *hdr, uint32_t *attrs, - struct xcmd_info *xcmd) -{ - unsigned char *p = (unsigned char *)(hdr + 1); - struct nlattr *na = (struct nlattr *)p; - - xcmd->resp.cap.mailbox_en = attrs[XNL_ATTR_DEV_MAILBOX_ENABLE]; - xcmd->resp.cap.mm_channel_max = attrs[XNL_ATTR_DEV_MM_CHANNEL_MAX]; - xcmd->resp.cap.num_pfs = attrs[XNL_ATTR_DEV_NUM_PFS]; - xcmd->resp.cap.num_qs = attrs[XNL_ATTR_DEV_NUMQS]; - xcmd->resp.cap.flr_present = attrs[XNL_ATTR_DEV_FLR_PRESENT]; - xcmd->resp.cap.mm_en = attrs[XNL_ATTR_DEV_MM_ENABLE]; - xcmd->resp.cap.debug_mode = attrs[XNL_ATTR_DEBUG_EN]; - xcmd->resp.cap.desc_eng_mode = attrs[XNL_ATTR_DESC_ENGINE_MODE]; - xcmd->resp.cap.mm_cmpt_en = - attrs[XNL_ATTR_DEV_MM_CMPT_ENABLE]; - xcmd->resp.cap.st_en = attrs[XNL_ATTR_DEV_ST_ENABLE]; - if (na->nla_type == XNL_ATTR_VERSION_INFO) { - strncpy(xcmd->resp.cap.version_str, (char *)(na + 1), QDMA_VERSION_INFO_STR_LENGTH); - } - if (na->nla_type == XNL_ATTR_DEVICE_TYPE) { - strncpy(xcmd->resp.cap.version_str, (char *)(na + 1), QDMA_VERSION_INFO_STR_LENGTH); - } - if (na->nla_type == XNL_ATTR_IP_TYPE) { - strncpy(xcmd->resp.cap.version_str, (char *)(na + 1), QDMA_VERSION_INFO_STR_LENGTH); - } -} - -void xnl_parse_reg_attrs(uint32_t *attrs, struct xcmd_info *xcmd) -{ - xcmd->req.reg.val = attrs[XNL_ATTR_REG_VAL]; -} - -static void xnl_parse_q_state_attrs(uint32_t *attrs, struct xcmd_info *xcmd) -{ - xcmd->resp.q_info.flags = attrs[XNL_ATTR_QFLAG]; - xcmd->resp.q_info.qidx = attrs[XNL_ATTR_QIDX]; - xcmd->resp.q_info.state = attrs[XNL_ATTR_Q_STATE]; -} - -static void xnl_parse_csr_attrs(struct xnl_hdr *hdr, uint32_t *attrs, struct xcmd_info *xcmd) -{ - unsigned char *p = (unsigned char *)(hdr + 1); - struct nlattr *na = (struct nlattr *)p; - - if (na->nla_type == XNL_ATTR_GLOBAL_CSR) { - memcpy(&xcmd->resp.csr,(void *) (na + 1), - sizeof(struct global_csr_conf)); - - } - -} - -static void xnl_parse_cmd_attrs(struct xnl_hdr *hdr, struct xcmd_info *xcmd, - uint32_t *attrs) -{ - switch(xcmd->op) { - case XNL_CMD_DEV_INFO: - xnl_parse_dev_info_attrs(attrs, xcmd); - break; - case XNL_CMD_DEV_STAT: - xnl_parse_dev_stat_attrs(attrs, xcmd); - break; - case XNL_CMD_DEV_CAP: - xnl_parse_dev_cap_attrs(hdr, attrs, xcmd); - break; - case XNL_CMD_REG_RD: - case XNL_CMD_REG_WRT: - xnl_parse_reg_attrs(attrs, xcmd); - break; - case XNL_CMD_GET_Q_STATE: - xnl_parse_q_state_attrs(attrs, xcmd); - break; - case XNL_CMD_GLOBAL_CSR: - xnl_parse_csr_attrs(hdr, attrs, xcmd); - break; - default: - break; - } -} - -int xnl_common_msg_send(struct xcmd_info *cmd, uint32_t *attrs) -{ - int rv; - struct xnl_gen_msg *msg = NULL; - struct xnl_hdr *hdr; - struct xnl_cb cb; - unsigned int dlen; - - rv = xnl_connect(&cb, cmd->vf, cmd->log_msg_dump); - if (rv < 0) - return rv; - dlen = get_cmd_resp_buf_len(cmd->op, cmd); - msg = xnl_msg_alloc(dlen, cmd->log_msg_dump); - if (!msg) - goto close; - hdr = &msg->hdr; - - xnl_msg_set_hdr(hdr, cb.family, cmd->op); - - rv = xnl_send_cmd(&cb, hdr, cmd, dlen); - if (rv < 0) - goto free_mem; - - rv = xnl_parse_response(&cb, hdr, cmd, dlen, attrs); - if (rv < 0) - goto free_mem; - xnl_parse_cmd_attrs(hdr, cmd, attrs); -free_mem: - free(msg); -close: - xnl_close(&cb); - - return rv; -} - -int qdma_dev_list_dump(struct xcmd_info *cmd) -{ - uint32_t attrs[XNL_ATTR_MAX] = {0}; - - xnl_common_msg_send(cmd, attrs); - cmd->vf = 1; - return xnl_common_msg_send(cmd, attrs); -} - -int qdma_dev_info(struct xcmd_info *cmd) -{ - uint32_t attrs[XNL_ATTR_MAX] = {0}; - int rv; - - rv = xnl_common_msg_send(cmd, attrs); - if (rv < 0) - return rv; -} - -int qdma_dev_cap(struct xcmd_info *cmd) -{ - uint32_t attrs[XNL_ATTR_MAX] = {0}; - int rv; - - rv = xnl_common_msg_send(cmd, attrs); - if (rv < 0) - return rv; -} - -int qdma_dev_stat(struct xcmd_info *cmd) -{ - uint32_t attrs[XNL_ATTR_MAX] = {0}; - int rv; - - rv = xnl_common_msg_send(cmd, attrs); - if (rv < 0) - return rv; -} - -int qdma_dev_stat_clear(struct xcmd_info *cmd) -{ - uint32_t attrs[XNL_ATTR_MAX] = {0}; - - return xnl_common_msg_send(cmd, attrs); -} - -int qdma_dev_intr_ring_dump(struct xcmd_info *cmd) -{ - uint32_t attrs[XNL_ATTR_MAX] = {0}; - - return xnl_common_msg_send(cmd, attrs); -} - -int qdma_dev_get_global_csr(struct xcmd_info *cmd) -{ - uint32_t attrs[XNL_ATTR_MAX] = {0}; - - return xnl_common_msg_send(cmd, attrs); -} - -int qdma_dev_q_list_dump(struct xcmd_info *cmd) -{ - uint32_t attrs[XNL_ATTR_MAX] = {0}; - - return xnl_common_msg_send(cmd, attrs); -} - -int qdma_q_add(struct xcmd_info *cmd) -{ - uint32_t attrs[XNL_ATTR_MAX] = {0}; - - return xnl_common_msg_send(cmd, attrs); -} - -int qdma_q_del(struct xcmd_info *cmd) -{ - uint32_t attrs[XNL_ATTR_MAX] = {0}; - - return xnl_common_msg_send(cmd, attrs); -} - -int qdma_q_start(struct xcmd_info *cmd) -{ - uint32_t attrs[XNL_ATTR_MAX] = {0}; - int rv = 0; - if ((cmd->req.qparm.flags & XNL_F_QDIR_BOTH) == - XNL_F_QDIR_BOTH) { - - if ((cmd->req.qparm.fetch_credit & - Q_ENABLE_C2H_FETCH_CREDIT) == Q_ENABLE_C2H_FETCH_CREDIT) - cmd->req.qparm.flags |= XNL_F_FETCH_CREDIT; - else - cmd->req.qparm.flags &= ~XNL_F_FETCH_CREDIT; - - cmd->req.qparm.flags = ((cmd->req.qparm.flags & - (~XNL_F_QDIR_BOTH)) | XNL_F_QDIR_C2H); - - rv = xnl_common_msg_send(cmd, attrs); - if (rv < 0) - return rv; - - if ((cmd->req.qparm.fetch_credit & - Q_ENABLE_H2C_FETCH_CREDIT) == Q_ENABLE_H2C_FETCH_CREDIT) - cmd->req.qparm.flags |= XNL_F_FETCH_CREDIT; - else - cmd->req.qparm.flags &= ~XNL_F_FETCH_CREDIT; - - cmd->req.qparm.flags = ((cmd->req.qparm.flags & - (~XNL_F_QDIR_BOTH)) | XNL_F_QDIR_H2C); - - return xnl_common_msg_send(cmd, attrs); - } else { - if ((cmd->req.qparm.flags & XNL_F_QDIR_H2C) == - XNL_F_QDIR_H2C) { - if ((cmd->req.qparm.fetch_credit & - Q_ENABLE_H2C_FETCH_CREDIT) == Q_ENABLE_H2C_FETCH_CREDIT) - cmd->req.qparm.flags |= XNL_F_FETCH_CREDIT; - else - cmd->req.qparm.flags &= ~XNL_F_FETCH_CREDIT; - } else if ((cmd->req.qparm.flags & XNL_F_QDIR_C2H) == - XNL_F_QDIR_C2H) { - if ((cmd->req.qparm.fetch_credit & - Q_ENABLE_C2H_FETCH_CREDIT) == Q_ENABLE_C2H_FETCH_CREDIT) - cmd->req.qparm.flags |= XNL_F_FETCH_CREDIT; - else - cmd->req.qparm.flags &= ~XNL_F_FETCH_CREDIT; - } - return xnl_common_msg_send(cmd, attrs); - } -} - -int qdma_q_stop(struct xcmd_info *cmd) -{ - uint32_t attrs[XNL_ATTR_MAX] = {0}; - - return xnl_common_msg_send(cmd, attrs); -} - -int qdma_q_dump(struct xcmd_info *cmd) -{ - uint32_t attrs[XNL_ATTR_MAX] = {0}; - - return xnl_common_msg_send(cmd, attrs); -} - -int qdma_q_get_state(struct xcmd_info *cmd) -{ - uint32_t attrs[XNL_ATTR_MAX] = {0}; - - return xnl_common_msg_send(cmd, attrs); -} - - -int qdma_q_desc_dump(struct xcmd_info *cmd) -{ - uint32_t attrs[XNL_ATTR_MAX] = {0}; - - return xnl_common_msg_send(cmd, attrs); -} - -int qdma_q_cmpt_read(struct xcmd_info *cmd) -{ - uint32_t attrs[XNL_ATTR_MAX] = {0}; - - return xnl_common_msg_send(cmd, attrs); -} - -int qdma_reg_read(struct xcmd_info *cmd) -{ - return proc_reg_cmd(cmd); -} - -int qdma_reg_write(struct xcmd_info *cmd) -{ - return proc_reg_cmd(cmd); -} - -int qdma_reg_info_read(struct xcmd_info *cmd) -{ - return proc_reg_cmd(cmd); -} - -int qdma_reg_dump(struct xcmd_info *cmd) -{ - return proc_reg_cmd(cmd); -} - -#ifdef TANDEM_BOOT_SUPPORTED -int qdma_en_st(struct xcmd_info *cmd) -{ - uint32_t attrs[XNL_ATTR_MAX] = {0}; - int rv; - - rv = xnl_common_msg_send(cmd, attrs); - if (rv < 0) - return rv; -} -#endif diff --git a/QDMA/linux-kernel/apps/dma-utils/dmactl_internal.h b/QDMA/linux-kernel/apps/dma-utils/dmactl_internal.h deleted file mode 100755 index 7283f7cc1..000000000 --- a/QDMA/linux-kernel/apps/dma-utils/dmactl_internal.h +++ /dev/null @@ -1,23 +0,0 @@ -/* - * This file is part of the QDMA userspace application - * to enable the user to execute the QDMA functionality - * - * Copyright (c) 2019 - 2022, Xilinx, Inc. - * All rights reserved. - * - * This source code is licensed under BSD-style license (found in the - * LICENSE file in the root directory of this source tree) - */ - -#ifndef _QDMACTL_INTERNAL_H_ -#define _QDMACTL_INTERNAL_H_ - -#include - -#include "dmautils.h" - -int proc_reg_cmd(struct xcmd_info *xcmd); -int is_valid_addr(unsigned char bar_no, unsigned int reg_addr); -int xnl_common_msg_send(struct xcmd_info *cmd, uint32_t *attrs); - -#endif /* _QDMACTL_INTERNAL_H_ */ diff --git a/QDMA/linux-kernel/apps/dma-utils/dmactl_reg.c b/QDMA/linux-kernel/apps/dma-utils/dmactl_reg.c deleted file mode 100755 index 549d67af2..000000000 --- a/QDMA/linux-kernel/apps/dma-utils/dmactl_reg.c +++ /dev/null @@ -1,461 +0,0 @@ -/* - * This file is part of the QDMA userspace application - * to enable the user to execute the QDMA functionality - * - * Copyright (c) 2019 - 2022, Xilinx, Inc. - * All rights reserved. - * - * This source code is licensed under BSD-style license (found in the - * LICENSE file in the root directory of this source tree) - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include "qdma_nl.h" -#include "dmactl_internal.h" - -#define QDMA_CFG_BAR_SIZE 0xB400 -#define QDMA_USR_BAR_SIZE 0x100 - -/* Macros for reading device capability */ -#define QDMA_GLBL2_MISC_CAP 0x134 -#define QDMA_GLBL2_MM_CMPT_EN_MASK 0x4 -#define QDMA_GLBL2_CHANNEL_MDMA 0x118 -#define QDMA_GLBL2_ST_C2H_MASK 0x10000 -#define QDMA_GLBL2_ST_H2C_MASK 0x20000 -#define QDMA_GLBL2_MM_C2H_MASK 0x100 -#define QDMA_GLBL2_MM_H2C_MASK 0x1 - -#define QDMA_MM_EN_SHIFT 0 -#define QDMA_CMPT_EN_SHIFT 1 -#define QDMA_ST_EN_SHIFT 2 -#define QDMA_MAILBOX_EN_SHIFT 3 - -#define QDMA_MM_MODE (1 << QDMA_MM_EN_SHIFT) -#define QDMA_COMPLETION_MODE (1 << QDMA_CMPT_EN_SHIFT) -#define QDMA_ST_MODE (1 << QDMA_ST_EN_SHIFT) -#define QDMA_MAILBOX (1 << QDMA_MAILBOX_EN_SHIFT) - - -#define QDMA_MM_ST_MODE \ - (QDMA_MM_MODE | QDMA_COMPLETION_MODE | QDMA_ST_MODE) - -#define GET_CAPABILITY_MASK(mm_en, st_en, mm_cmpt_en, mailbox_en) \ - ((mm_en << QDMA_MM_EN_SHIFT) | \ - ((mm_cmpt_en | st_en) << QDMA_CMPT_EN_SHIFT) | \ - (st_en << QDMA_ST_EN_SHIFT) | \ - (mailbox_en << QDMA_MAILBOX_EN_SHIFT)) - -struct xreg_info { - const char name[32]; - uint32_t addr; - uint32_t repeat; - uint32_t step; - uint8_t shift; - uint8_t len; - uint8_t mode; -}; - -static struct xreg_info qdma_user_regs[] = { - {"ST_C2H_QID", 0x0, 0, 0, 0, 0, QDMA_MM_ST_MODE}, - {"ST_C2H_PKTLEN", 0x4, 0, 0, 0, 0, QDMA_MM_ST_MODE}, - {"ST_C2H_CONTROL", 0x8, 0, 0, 0, 0, QDMA_MM_ST_MODE}, - /* ST_C2H_CONTROL: - * [1] : start C2H - * [2] : immediate data - * [3] : every packet statrs with 00 instead of continuous data - * stream until # of packets is complete - * [31]: gen_user_reset_n - */ - {"ST_H2C_CONTROL", 0xC, 0, 0, 0, 0, QDMA_MM_ST_MODE}, - /* ST_H2C_CONTROL: - * [0] : clear match for H2C transfer - */ - {"ST_H2C_STATUS", 0x10, 0, 0, 0, 0, QDMA_MM_ST_MODE}, - {"ST_H2C_XFER_CNT", 0x14, 0, 0, 0, 0, QDMA_MM_ST_MODE}, - {"ST_C2H_PKT_CNT", 0x20, 0, 0, 0, 0, QDMA_MM_ST_MODE}, - {"ST_C2H_CMPT_DATA", 0x30, 8, 0, 0, 0, QDMA_MM_ST_MODE}, - {"ST_C2H_CMPT_SIZE", 0x50, 0, 0, 0, 0, QDMA_MM_ST_MODE}, - {"ST_SCRATCH_REG", 0x60, 2, 0, 0, 0, QDMA_MM_ST_MODE}, - {"ST_C2H_PKT_DROP", 0x88, 0, 0, 0, 0, QDMA_MM_ST_MODE}, - {"ST_C2H_PKT_ACCEPT", 0x8C, 0, 0, 0, 0, QDMA_MM_ST_MODE}, - {"DSC_BYPASS_LOOP", 0x90, 0, 0, 0, 0, QDMA_MM_ST_MODE}, - {"USER_INTERRUPT", 0x94, 0, 0, 0, 0, QDMA_MM_ST_MODE}, - {"USER_INTERRUPT_MASK", 0x98, 0, 0, 0, 0, QDMA_MM_ST_MODE}, - {"USER_INTERRUPT_VEC", 0x9C, 0, 0, 0, 0, QDMA_MM_ST_MODE}, - {"DMA_CONTROL", 0xA0, 0, 0, 0, 0, QDMA_MM_ST_MODE}, - {"VDM_MSG_READ", 0xA4, 0, 0, 0, 0, QDMA_MM_ST_MODE}, - - {"", 0, 0, 0 } -}; - - -static struct xreg_info qdma_cpm_dmap_regs[] = { -/* QDMA_TRQ_SEL_QUEUE_PF (0x6400) */ - {"DMAP_SEL_INT_CIDX", 0x6400, 512, 0x10, 0, 0, QDMA_MM_ST_MODE}, - {"DMAP_SEL_H2C_DSC_PIDX", 0x6404, 512, 0x10, 0, 0, QDMA_MM_ST_MODE}, - {"DMAP_SEL_C2H_DSC_PIDX", 0x6408, 512, 0x10, 0, 0, QDMA_MM_ST_MODE}, - {"DMAP_SEL_CMPT_CIDX", 0x640C, 512, 0x10, 0, 0, QDMA_MM_ST_MODE}, - {"", 0, 0, 0 } -}; - -static struct xreg_info qdma_dmap_regs[] = { -/* QDMA_TRQ_SEL_QUEUE_PF (0x6400) */ - {"DMAP_SEL_INT_CIDX", 0x6400, 512, 0x10, 0, 0, QDMA_MM_ST_MODE}, - {"DMAP_SEL_H2C_DSC_PIDX", 0x6404, 512, 0x10, 0, 0, QDMA_MM_ST_MODE}, - {"DMAP_SEL_C2H_DSC_PIDX", 0x6408, 512, 0x10, 0, 0, QDMA_MM_ST_MODE}, - {"DMAP_SEL_CMPT_CIDX", 0x640C, 512, 0x10, 0, 0, QDMA_MM_ST_MODE}, - {"", 0, 0, 0 } -}; - -/* - * Register I/O through mmap of BAR0. - */ - -/* /sys/bus/pci/devices/0000::./resource */ -#define get_syspath_bar_mmap(s, bus,dev,func,bar) \ - snprintf(s, sizeof(s), \ - "/sys/bus/pci/devices/0000:%02x:%02x.%x/resource%u", \ - bus, dev, func, bar) - -static uint32_t *mmap_bar(char *fname, size_t len, int prot) -{ - int fd; - uint32_t *bar; - - fd = open(fname, (prot & PROT_WRITE) ? O_RDWR : O_RDONLY); - if (fd < 0) - return NULL; - - bar = mmap(NULL, len, prot, MAP_SHARED, fd, 0); - close(fd); - - return bar == MAP_FAILED ? NULL : bar; -} - -static int32_t reg_read_mmap(struct xnl_dev_info *dev_info, - unsigned char barno, - struct xcmd_info *xcmd) -{ - uint32_t *bar; - char fname[256]; - int rv = 0; - uint32_t attrs[XNL_ATTR_MAX] = {0}; - - get_syspath_bar_mmap(fname, dev_info->pci_bus, dev_info->pci_dev, - dev_info->dev_func, barno); - - bar = mmap_bar(fname, xcmd->req.reg.reg + 4, PROT_READ); - if (!bar) { - if (xcmd->op == XNL_CMD_REG_WRT) - xcmd->op = XNL_CMD_REG_RD; - - rv = xnl_common_msg_send(xcmd, attrs); - - return rv; - } - - xcmd->req.reg.val = le32toh(bar[xcmd->req.reg.reg / 4]); - munmap(bar, xcmd->req.reg.reg + 4); - - return rv; -} - -static int32_t reg_write_mmap(struct xnl_dev_info *dev_info, - unsigned char barno, - struct xcmd_info *xcmd) -{ - uint32_t *bar; - char fname[256]; - int rv = 0; - uint32_t attrs[XNL_ATTR_MAX] = {0}; - - get_syspath_bar_mmap(fname, dev_info->pci_bus, dev_info->pci_dev, - dev_info->dev_func, barno); - - bar = mmap_bar(fname, xcmd->req.reg.reg + 4, PROT_WRITE); - if (!bar) { - rv = xnl_common_msg_send(xcmd, attrs); - - return rv; - } - - bar[xcmd->req.reg.reg / 4] = htole32(xcmd->req.reg.val); - munmap(bar, xcmd->req.reg.reg + 4); - return 0; -} - -static void print_repeated_reg(uint32_t *bar, struct xreg_info *xreg, - unsigned start, unsigned limit, struct xnl_dev_info *dev_info, - struct xcmd_info *xcmd, void (*log_reg)(const char *)) -{ - int i; - int end = start + limit; - int step = xreg->step ? xreg->step : 4; - uint32_t val; - int32_t rv = 0; - char reg_dump[100]; - - for (i = start; i < end; i++) { - uint32_t addr = xreg->addr + (i * step); - char name[40]; - snprintf(name, 40, "%s_%d", - xreg->name, i); - - if (xcmd == NULL) { - val = le32toh(bar[addr / 4]); - } else { - xcmd->req.reg.reg = addr; - rv = reg_read_mmap(dev_info, xcmd->req.reg.bar, xcmd); - if (rv < 0) { - snprintf(reg_dump, 100, "\n"); - if (log_reg) - log_reg(reg_dump); - continue; - } - } - snprintf(reg_dump, 100, "[%#7x] %-47s %#-10x %u\n", - addr, name, val, val); - if (log_reg) - log_reg(reg_dump); - } -} - -static void read_config_regs(uint32_t *bar, struct xnl_dev_info *xdev, - struct xcmd_info *xcmd) -{ - uint32_t attrs[XNL_ATTR_MAX] = {0}; - - /* Get the capabilities of the Device */ - xcmd->op = XNL_CMD_REG_DUMP; - xnl_common_msg_send(xcmd, attrs); -} - -static void read_regs(uint32_t *bar, struct xreg_info *reg_list, - struct xnl_dev_info *xdev, struct xcmd_info *xcmd, - void (*log_reg)(const char *)) -{ - struct xreg_info *xreg = reg_list; - uint32_t val; - int32_t rv = 0; - char reg_dump[100] = {'\0'}; - - for (xreg = reg_list; strlen(xreg->name); xreg++) { - - if (!xreg->len) { - if (xreg->repeat) { - if (xcmd == NULL) - print_repeated_reg(bar, xreg, 0, - xreg->repeat, NULL, - NULL, log_reg); - else - print_repeated_reg(NULL, xreg, 0, - xreg->repeat, xdev, - xcmd, log_reg); - } else { - uint32_t addr = xreg->addr; - if (xcmd == NULL) { - val = le32toh(bar[addr / 4]); - } else { - xcmd->req.reg.reg = addr; - rv = reg_read_mmap(xdev, - xcmd->req.reg.bar, - xcmd); - if (rv < 0) - continue; - } - snprintf(reg_dump, 100, - "[%#7x] %-47s %#-10x %u\n", - addr, xreg->name, val, val); - if (log_reg) - log_reg(reg_dump); - } - } else { - uint32_t addr = xreg->addr; - uint32_t val = 0; - if (xcmd == NULL) { - val = le32toh(bar[addr / 4]); - } else { - xcmd->req.reg.reg = addr; - rv = reg_read_mmap(xdev, xcmd->req.reg.bar, - xcmd); - if (rv < 0) - continue; - } - - uint32_t v = (val >> xreg->shift) & - ((1 << xreg->len) - 1); - - snprintf(reg_dump, 100, - " %*u:%d %-47s %#-10x %u\n", - xreg->shift < 10 ? 3 : 2, - xreg->shift + xreg->len - 1, - xreg->shift, xreg->name, v, v); - if (log_reg) - log_reg(reg_dump); - } - memset(reg_dump, '\0', 100); - } -} - -static void reg_dump_mmap(struct xnl_dev_info *dev_info, unsigned char barno, - struct xreg_info *reg_list, unsigned int max, - struct xcmd_info *xcmd) -{ - uint32_t *bar; - char fname[256]; - - get_syspath_bar_mmap(fname, dev_info->pci_bus, dev_info->pci_dev, - dev_info->dev_func, barno); - - if ((barno == dev_info->config_bar) && (reg_list == NULL)) - read_config_regs(NULL, dev_info, xcmd); - else { - bar = mmap_bar(fname, max, PROT_READ); - if (!bar) { - xcmd->req.reg.bar = barno; - xcmd->op = XNL_CMD_REG_RD; - read_regs(NULL, reg_list, dev_info, xcmd, - xcmd->log_msg_dump); - } else { - read_regs(bar, reg_list, NULL, NULL, xcmd->log_msg_dump); - munmap(bar, max); - } - } - return; -} - - -static void reg_dump_range(struct xnl_dev_info *dev_info, unsigned char barno, - unsigned int max, struct xreg_info *reg_list, - unsigned int start, unsigned int limit, - struct xcmd_info *xcmd) -{ - struct xreg_info *xreg = reg_list; - uint32_t *bar; - char fname[256]; - - get_syspath_bar_mmap(fname, dev_info->pci_bus, dev_info->pci_dev, - dev_info->dev_func, barno); - - bar = mmap_bar(fname, max, PROT_READ); - if (!bar) { - xcmd->op = XNL_CMD_REG_RD; - xcmd->req.reg.bar = barno; - for (xreg = reg_list; strlen(xreg->name); xreg++) { - print_repeated_reg(NULL, xreg, start, limit, dev_info, - xcmd, xcmd->log_msg_dump); - } - return; - } - - for (xreg = reg_list; strlen(xreg->name); xreg++) { - print_repeated_reg(bar, xreg, start, limit, NULL, NULL, - xcmd->log_msg_dump); - } - - munmap(bar, max); -} - -static inline void print_seperator(struct xcmd_info *xcmd) -{ - char buffer[81]; - - memset(buffer, '#', 80); - buffer[80] = '\0'; - - if (xcmd && xcmd->log_msg_dump) - xcmd->log_msg_dump(buffer); -} - -int proc_reg_cmd(struct xcmd_info *xcmd) -{ - struct xcmd_reg *regcmd; - struct xcmd_info dev_xcmd; - int32_t rv = 0; - char reg_dump[100]; - unsigned int barno; - unsigned char version[QDMA_VERSION_INFO_STR_LENGTH]; - int32_t v; - unsigned char op; - uint32_t attrs[XNL_ATTR_MAX] = {0}; - - memcpy(&dev_xcmd, xcmd, sizeof(dev_xcmd)); - - dev_xcmd.op = XNL_CMD_DEV_CAP; - rv = qdma_dev_cap(&dev_xcmd); - if (rv < 0) - return rv; - - strcpy(version, dev_xcmd.resp.cap.version_str); - - op = xcmd->op; - xcmd->op = XNL_CMD_DEV_INFO; - rv = qdma_dev_info(xcmd); - if (rv < 0) - return rv; - xcmd->op = op; - regcmd = &xcmd->req.reg; - barno = (regcmd->sflags & XCMD_REG_F_BAR_SET) ? - regcmd->bar : xcmd->resp.dev_info.config_bar; - regcmd->bar = barno; - - switch (xcmd->op) { - case XNL_CMD_REG_RD: - rv = reg_read_mmap(&xcmd->resp.dev_info, barno, xcmd); - if (rv < 0) - return rv; - break; - case XNL_CMD_REG_WRT: - v = reg_write_mmap(&xcmd->resp.dev_info, barno, xcmd); - if (v < 0) - return rv; - rv = reg_read_mmap(&xcmd->resp.dev_info, barno, xcmd); - if (rv < 0) - return rv; - break; - case XNL_CMD_REG_DUMP: - print_seperator(xcmd); - - if (xcmd->vf) - snprintf(reg_dump, 100, "\n###\t\tqdmavf%05x, pci %02x:%02x.%02x, reg dump\n", - xcmd->if_bdf, xcmd->resp.dev_info.pci_bus, - xcmd->resp.dev_info.pci_dev, xcmd->resp.dev_info.dev_func); - else - snprintf(reg_dump, 100, "\n###\t\tqdma%05x, pci %02x:%02x.%02x, reg dump\n", - xcmd->if_bdf, xcmd->resp.dev_info.pci_bus, - xcmd->resp.dev_info.pci_dev, xcmd->resp.dev_info.dev_func); - if (xcmd->log_msg_dump) - xcmd->log_msg_dump(reg_dump); - - print_seperator(xcmd); - snprintf(reg_dump, 100, "\nAXI Master Lite Bar #%d\n", - xcmd->resp.dev_info.user_bar); - if (xcmd->log_msg_dump) - xcmd->log_msg_dump(reg_dump); - - reg_dump_mmap(&xcmd->resp.dev_info, xcmd->resp.dev_info.user_bar, - qdma_user_regs, QDMA_USR_BAR_SIZE, xcmd); - - snprintf(reg_dump, 100, "\nCONFIG BAR #%d\n", - xcmd->resp.dev_info.config_bar); - if (xcmd->log_msg_dump) - xcmd->log_msg_dump(reg_dump); - reg_dump_mmap(&xcmd->resp.dev_info, xcmd->resp.dev_info.config_bar, NULL, - QDMA_CFG_BAR_SIZE, xcmd); - break; - case XNL_CMD_REG_INFO_READ: - xnl_common_msg_send(xcmd, attrs); - break; - default: - break; - } - - return 0; -} diff --git a/QDMA/linux-kernel/apps/dma-utils/dmautils.c b/QDMA/linux-kernel/apps/dma-utils/dmautils.c deleted file mode 100755 index 358530bc8..000000000 --- a/QDMA/linux-kernel/apps/dma-utils/dmautils.c +++ /dev/null @@ -1,45 +0,0 @@ -/* - * This file is part of the QDMA userspace application - * to enable the user to execute the QDMA functionality - * - * Copyright (c) 2019 - 2022, Xilinx, Inc. - * All rights reserved. - * - * This source code is licensed under BSD-style license (found in the - * LICENSE file in the root directory of this source tree) - */ -#include "dmautils.h" - -#include -#include -#include -#include -#include -#include -#include -#include - -#include "qdma_nl.h" -#include "dmaxfer.h" -#include "version.h" - -#define QDMA_Q_NAME_LEN 100 - -enum qdma_reg_op { - QDMA_Q_REG_DUMP, - QDMA_Q_REG_RD, - QDMA_Q_REG_WR, -}; - - -int qdmautils_sync_xfer(char *filename, enum qdmautils_io_dir dir, void *buf, - unsigned int xfer_len) -{ - return dmaxfer_iosubmit(filename, dir, DMAXFER_IO_SYNC, buf, xfer_len); -} - -int qdmautils_async_xfer(char *filename, enum qdmautils_io_dir dir, void *buf, - unsigned int xfer_len) -{ - return dmaxfer_iosubmit(filename, dir, DMAXFER_IO_ASYNC, buf, xfer_len); -} diff --git a/QDMA/linux-kernel/apps/dma-utils/dmautils.h b/QDMA/linux-kernel/apps/dma-utils/dmautils.h deleted file mode 100755 index 2df9416ac..000000000 --- a/QDMA/linux-kernel/apps/dma-utils/dmautils.h +++ /dev/null @@ -1,619 +0,0 @@ -/* - * This file is part of the QDMA userspace application - * to enable the user to execute the QDMA functionality - * - * Copyright (c) 2019 - 2020, Xilinx, Inc. - * All rights reserved. - * - * This source code is licensed under BSD-style license (found in the - * LICENSE file in the root directory of this source tree) - */ -#ifndef QDMAUTILS_H -#define QDMAUTILS_H - - -/** @QDMA_GLOBAL_CSR_ARRAY_SZ: QDMA Global CSR array size */ -#define QDMA_GLOBAL_CSR_ARRAY_SZ 16 - -/** - * enum dmautils_io_dir - DMA direction to perform - */ -enum qdmautils_io_dir { - /** @DMAXFER_IO_READ: DMA card to host */ - DMAXFER_IO_READ, - /** @DMAXFER_IO_WRITE: DMA host to card */ - DMAXFER_IO_WRITE, -}; - - -enum qdma_q_fetch_credit { - /** @NONE: Disable Fetch Credit**/ - Q_DISABLE_FETCH_CREDIT = 0, - /** @Q_H2C: Enable fetch credit for H2C direction */ - Q_ENABLE_H2C_FETCH_CREDIT, - /** @Q_C2H: Enable fetch credit for C2H direction */ - Q_ENABLE_C2H_FETCH_CREDIT, - /** @Q_H2C_C2H: Enable fetch credit for H2C and C2H direction */ - Q_ENABLE_H2C_C2H_FETCH_CREDIT, -}; - - -/** - * enum qdma_q_state - QDMA q state - */ -enum qdma_q_state { - /** @Q_STATE_DISABLED: Queue is not taken */ - Q_STATE_DISABLED = 0, - /** @Q_STATE_ENABLED: Assigned/taken. Partial config is done */ - Q_STATE_ENABLED, - /** @Q_STATE_ONLINE: Resource/context is initialized for the queue and is available for - * data consumption - */ - Q_STATE_ONLINE, -}; - -/** @set_qparam - helper macro to set q param - * @xcmd: pointer to xcmd_info - * @var_ptr: pointer to the variable to be updated in xcmd->u.qparm - * @param_type: type of the q param that is being updated - * @val: calue to be updated in @var_ptr - */ -#define set_qparam(xcmd, var_ptr, param_type, val) \ - do {\ - *var_ptr = val; \ - xcmd->sflags |= (1 << param_type); \ - } while (0); - -/** - * enum qdma_q_parm_type - QDMA q param type to indicate what all params are - * provided - */ -enum qdma_q_parm_type { - /** @QPARM_IDX: q index param */ - QPARM_IDX, - /** @QPARM_MODE: q mode param */ - QPARM_MODE, - /** @QPARM_DIR: q direction param */ - QPARM_DIR, - /** @QPARM_DESC: q desc request param */ - QPARM_DESC, - /** @QPARM_CMPT: q cmpt desc request param */ - QPARM_CMPT, - /** @QPARM_CMPTSZ: q cmpt size param */ - QPARM_CMPTSZ, - /** @QPARM_SW_DESC_SZ: q sw desc size param */ - QPARM_SW_DESC_SZ, - /** @QPARM_RNGSZ_IDX: q ring size idx param */ - QPARM_RNGSZ_IDX, - /** @QPARM_C2H_BUFSZ_IDX: q c2h buf size idx param */ - QPARM_C2H_BUFSZ_IDX, - /** @QPARM_CMPT_TMR_IDX: q cmpt timer idx param */ - QPARM_CMPT_TMR_IDX, - /** @QPARM_CMPT_CNTR_IDX: q cmpt counter idx param */ - QPARM_CMPT_CNTR_IDX, - /** @QPARM_CMPT_TRIG_MODE: q cmpt trigger mode param */ - QPARM_CMPT_TRIG_MODE, - /** @QPARM_PING_PONG_EN: ping pong param */ - QPARM_PING_PONG_EN, - /** @KEYHOLE_PARAM: keyhole feature aperture */ - QPARM_KEYHOLE_EN, - /** @QPARM_MM_CHANNEL: q mm channel enable param */ - QPARM_MM_CHANNEL, - /** @QPARM_MAX: max q param */ - QPARM_MAX, -}; - -/** - * struct xcmd_q_parm - QDMA q param information - */ -struct xcmd_q_parm { - /** @sflags: flgas to indicate the presence of parms with - * @qdma_q_parm_type */ - unsigned int sflags; - /** @sflags: flgas to indicate the presence of features */ - unsigned int flags; - /** @idx: index of queue */ - unsigned int idx; - /** @num_q: num of queue */ - unsigned int num_q; - /** @range_start: start of range */ - unsigned int range_start; - /** @range_end: end of range */ - unsigned int range_end; - /** @sw_desc_sz: SW desc size */ - unsigned char sw_desc_sz; - /** @cmpt_entry_size: completion desc size */ - unsigned char cmpt_entry_size; - /** @qrngsz_idx: ring size idx */ - unsigned char qrngsz_idx; - /** @c2h_bufsz_idx: c2h buf size index */ - unsigned char c2h_bufsz_idx; - /** @cmpt_tmr_idx: cmpt timer index */ - unsigned char cmpt_tmr_idx; - /** @cmpt_cntr_idx: cmpt counter index */ - unsigned char cmpt_cntr_idx; - /** @cmpt_trig_mode: cmpt trigger mode */ - unsigned char cmpt_trig_mode; - /** @mm_channel: mm channel enable */ - unsigned char mm_channel; - /** @fetch_credit: fetch credit enable */ - unsigned char fetch_credit; - /** @is_qp: queue pair */ - unsigned char is_qp; - /** @ping_pong_en: ping pong en */ - unsigned char ping_pong_en; - /** @aperture_sz: aperture_size for keyhole transfers*/ - unsigned int aperture_sz; -}; - -/** - * struct xcmd_intr - QDMA dev interrupt ring dump - */ -struct xcmd_intr { - /** @vector: vector number */ - unsigned int vector; - /** @start_idx: start idx of interrupt ring descriptor */ - int start_idx; - /** @end_idx: end idx of interrupt ring descriptor */ - int end_idx; -}; - -/** @QDMA_VERSION_INFO_STR_LENGTH: QDMA version string length */ -#define QDMA_VERSION_INFO_STR_LENGTH 256 - -/** - * struct xcmd_dev_cap - QDMA device capabilites - */ -struct xcmd_dev_cap { - /** @version_str: qdma version string */ - char version_str[QDMA_VERSION_INFO_STR_LENGTH]; - /** @num_qs: HW qmax */ - unsigned int num_qs; - /** @num_pfs: HW number of pf */ - unsigned int num_pfs; - /** @flr_present: flr support */ - unsigned int flr_present; - /** @mm_en: MM mode support */ - unsigned int mm_en; - /** @mm_cmpt_en: MM CMPT mode support */ - unsigned int mm_cmpt_en; - /** @st_en: ST mode support */ - unsigned int st_en; - /** @mailbox_en: Mailbox support */ - unsigned int mailbox_en; - /** @mm_channel_max: Max MM channel */ - unsigned int mm_channel_max; - /** @debug_mode: Debug Mode*/ - unsigned int debug_mode; - /** @desc_eng_mode: Descriptor Engine Mode*/ - unsigned int desc_eng_mode; -}; - -/** - * struct xcmd_reg - register access command info - */ -struct xcmd_reg { - /** @sflags: flags to indicate parameter presence */ - unsigned int sflags; - /** @XCMD_REG_F_BAR_SET: bar param set */ -#define XCMD_REG_F_BAR_SET 0x1 - /** @XCMD_REG_F_REG_SET: reg param set */ -#define XCMD_REG_F_REG_SET 0x2 - /** @XCMD_REG_F_VAL_SET: val param set */ -#define XCMD_REG_F_VAL_SET 0x4 - /** @bar: bar number */ - unsigned int bar; - /** @reg: register offset */ - unsigned int reg; - /** @val: value */ - unsigned int val; - /** @range_start: range start */ - unsigned int range_start; - /** @range_end: range end */ - unsigned int range_end; -}; - -/** - * struct xnl_dev_info - device information - */ -struct xnl_dev_info { - /** @pci_bus: pci bus */ - unsigned char pci_bus; - /** @pci_dev: pci device */ - unsigned char pci_dev; - /** @dev_func: pci function */ - unsigned char dev_func; - /** @config_bar: config bar */ - unsigned char config_bar; - /** @user_bar: AXI Master Lite(user bar) */ - unsigned char user_bar; - /** @qmax: SW qmax */ - unsigned int qmax; - /** @qbase: HW q base */ - unsigned int qbase; -}; - -/** - * struct xnl_dev_stat - device statistics - */ -struct xnl_dev_stat { - /** @mm_h2c_pkts: MM H2C packets processed */ - unsigned long long mm_h2c_pkts; - /** @mm_c2h_pkts: MM C2H packets processed */ - unsigned long long mm_c2h_pkts; - /** @st_h2c_pkts: ST H2C packets processed */ - unsigned long long st_h2c_pkts; - /** @st_c2h_pkts: ST C2H packets processed */ - unsigned long long st_c2h_pkts; - /** max ping_pong latency */ - unsigned long long ping_pong_lat_max; - /** min ping_pong latency */ - unsigned long long ping_pong_lat_min; - /** avg ping_pong latency */ - unsigned long long ping_pong_lat_avg; -}; - -/** - * struct xnl_q_info - q state information - */ -struct xnl_q_info { - /** @flags: feature flags enabled */ - unsigned int flags; - /** @qidx: index of queue */ - unsigned int qidx; - /** @state: queue state */ - enum qdma_q_state state; -}; - -/** - * struct global_csr_conf - Global CSR information - */ -struct global_csr_conf { - /** @ring_sz: Descriptor ring size ie. queue depth */ - unsigned int ring_sz[QDMA_GLOBAL_CSR_ARRAY_SZ]; - /** @c2h_timer_cnt: C2H timer count list */ - unsigned int c2h_timer_cnt[QDMA_GLOBAL_CSR_ARRAY_SZ]; - /** @c2h_cnt_th: C2H counter threshold list*/ - unsigned int c2h_cnt_th[QDMA_GLOBAL_CSR_ARRAY_SZ]; - /** @c2h_buf_sz: C2H buffer size list */ - unsigned int c2h_buf_sz[QDMA_GLOBAL_CSR_ARRAY_SZ]; - /** @wb_intvl: Writeback interval */ - unsigned int wb_intvl; -}; - - -/** - * struct xcmd_info - command information - */ -struct xcmd_info { - /** @vf: is VF */ - unsigned char vf:1; - /** @op: operation */ - unsigned char op:7; - /** @req: union of other information for request */ - union { - /** @intr: interrupt ring info */ - struct xcmd_intr intr; - /** @reg: reg command info */ - struct xcmd_reg reg; - /** @qparm: q command info */ - struct xcmd_q_parm qparm; - } req; - /** @resp: union of information from response */ - union { - /** @cap: device capabilities response */ - struct xcmd_dev_cap cap; - /** @dev_stat: device stat response */ - struct xnl_dev_stat dev_stat; - /** @dev_info: device info response */ - struct xnl_dev_info dev_info; - /** @q_info: queue info response */ - struct xnl_q_info q_info; - /** @csr: CSR reponse */ - struct global_csr_conf csr; - } resp; - /** @if_bdf: interface BDF */ - unsigned int if_bdf; - /** @log_msg_dump: log messages dumping function */ - void (*log_msg_dump)(const char *resp_str); -}; - -/** @QDMAUTILS_VERSION_LEN: qdmautils version string length */ -#define QDMAUTILS_VERSION_LEN 10 -/** - * struct qdmautils_version - qdmautils version information - */ -struct qdmautils_version { - char version[QDMAUTILS_VERSION_LEN]; -}; - -/*****************************************************************************/ -/** - * qdmautils_get_version() - Get qdmautils version - * - * @ver: Pointer to the output data structure where version is to be - * updated - * - * Return: Nothing - * - *****************************************************************************/ -void qdmautils_get_version(struct qdmautils_version *ver); - -/*****************************************************************************/ -/** - * qdma_dev_list_dump() - dump device list - * - * @cmd: command information - * - * Return: >=0 for success and <0 for error - * - *****************************************************************************/ -int qdma_dev_list_dump(struct xcmd_info *cmd); - -/*****************************************************************************/ -/** - * qdma_dev_info() - get device information provided by cmd->u.dev_info - * - * @cmd: command information - * - * Return: >=0 for success and <0 for error - * - *****************************************************************************/ -int qdma_dev_info(struct xcmd_info *cmd); - -/*****************************************************************************/ -/** - * qdma_dev_cap() - get device capabilities provided by cmd->u.dev_cap - * - * @cmd: command information - * - * Return: >=0 for success and <0 for error - * - *****************************************************************************/ -int qdma_dev_cap(struct xcmd_info *cmd); - -/*****************************************************************************/ -/** - * qdma_dev_stat() - get device statistics provided by cmd->u.dev_stat - * - * @cmd: command information - * - * Return: >=0 for success and <0 for error - * - *****************************************************************************/ -int qdma_dev_stat(struct xcmd_info *cmd); - -/*****************************************************************************/ -/** - * qdma_dev_stat_clear() - clear device statistics - * - * @cmd: command information - * - * Return: >=0 for success and <0 for error - * - *****************************************************************************/ -int qdma_dev_stat_clear(struct xcmd_info *cmd); - -/*****************************************************************************/ -/** - * qdma_dev_intr_ring_dump() - dump device interrupt ring - * - * @cmd: command information - * - * Return: >=0 for success and <0 for error - * - *****************************************************************************/ -int qdma_dev_intr_ring_dump(struct xcmd_info *cmd); - -/*****************************************************************************/ -/** - * qdma_dev_get_global_csr() - get global CSR provided by cmd->u.csr - * - * @cmd: command information - * - * Return: >=0 for success and <0 for error - * - *****************************************************************************/ -int qdma_dev_get_global_csr(struct xcmd_info *cmd); - - -/*****************************************************************************/ -/** - * qdma_dev_q_list_dump() - dump device q list - * - * @cmd: command information - * - * Return: >=0 for success and <0 for error - * - *****************************************************************************/ -int qdma_dev_q_list_dump(struct xcmd_info *cmd); - -/*****************************************************************************/ -/** - * qdma_q_add() - add a queue - * - * @cmd: command information - * - * Return: >=0 for success and <0 for error - * - *****************************************************************************/ -int qdma_q_add(struct xcmd_info *cmd); - -/*****************************************************************************/ -/** - * qdma_q_del() - delete a queue - * - * @cmd: command information - * - * Return: >=0 for success and <0 for error - * - *****************************************************************************/ -int qdma_q_del(struct xcmd_info *cmd); - -/*****************************************************************************/ -/** - * qdma_q_start() - start a queue - * - * @cmd: command information - * - * Return: >=0 for success and <0 for error - * - *****************************************************************************/ -int qdma_q_start(struct xcmd_info *cmd); - -/*****************************************************************************/ -/** - * qdma_q_stop() - stop a queue - * - * @cmd: command information - * - * Return: >=0 for success and <0 for error - * - *****************************************************************************/ -int qdma_q_stop(struct xcmd_info *cmd); - -/*****************************************************************************/ -/** - * qdma_q_get_state() - get q state information provided by cmd->u.q_info - * - * @cmd: command information - * - * Return: >=0 for success and <0 for error - * - *****************************************************************************/ -int qdma_q_get_state(struct xcmd_info *cmd); - -/*****************************************************************************/ -/** - * qdma_q_dump() - dump q context - * - * @cmd: command information - * - * Return: >=0 for success and <0 for error - * - *****************************************************************************/ -int qdma_q_dump(struct xcmd_info *cmd); - -/*****************************************************************************/ -/** - * qdma_q_desc_dump() - dump q sw/cmpt descriptors - * - * @cmd: command information - * - * Return: >=0 for success and <0 for error - * - *****************************************************************************/ -int qdma_q_desc_dump(struct xcmd_info *cmd); - -/*****************************************************************************/ -/** - * qdma_q_cmpt_read() - dump last cmpt descriptor of the queue - * - * @cmd: command information - * - * Return: >=0 for success and <0 for error - * - *****************************************************************************/ -int qdma_q_cmpt_read(struct xcmd_info *cmd); - - -/*****************************************************************************/ -/** - * qdma_reg_read() - read register - * - * @cmd: command information - * - * Return: >=0 for success and <0 for error - * - *****************************************************************************/ -int qdma_reg_read(struct xcmd_info *cmd); - -/*****************************************************************************/ -/** - * qdma_reg_info_read() - read register fields information - * - * @cmd: command information - * - * Return: >=0 for success and <0 for error - * - *****************************************************************************/ -int qdma_reg_info_read(struct xcmd_info *cmd); - -/*****************************************************************************/ -/** - * qdma_reg_write() - write register - * - * @cmd: command information - * - * Return: >=0 for success and <0 for error - * - *****************************************************************************/ -int qdma_reg_write(struct xcmd_info *cmd); - -/*****************************************************************************/ -/** - * qdma_reg_dump() - dump registers - * - * @cmd: command information - * - * Return: >=0 for success and <0 for error - * - *****************************************************************************/ -int qdma_reg_dump(struct xcmd_info *cmd); - - -/*****************************************************************************/ -/** - * qdmautils_ioctl_nomemcpy() - set no memcpy from ioctl for the cdev - * - * @filename: filename on which ioctl needs to be done - * - * Return: >=0 for success and <0 for error - * - *****************************************************************************/ -int qdmautils_ioctl_nomemcpy(char *filename); - -/*****************************************************************************/ -/** - * qdmautils_sync_xfer() - sync transfer - * - * @filename: filename on which transfer needs to be done - * @dir: direction oif operation - * @buf: pointer to buffer - * @xfer_len: size of transfer - * - * Return: >=0 for success and <0 for error - * - *****************************************************************************/ -int qdmautils_sync_xfer(char *filename, enum qdmautils_io_dir dir, void *buf, - unsigned int xfer_len); - -/*****************************************************************************/ -/** - * qdmautils_async_xfer() - async trasnfer - * - * @filename: filename on which transfer needs to be done - * @dir: direction oif operation - * @buf: pointer to buffer - * @xfer_len: size of transfer - * - * Return: >=0 for success and <0 for error - * - *****************************************************************************/ -int qdmautils_async_xfer(char *filename, enum qdmautils_io_dir dir, void *buf, - unsigned int xfer_len); - -#ifdef TANDEM_BOOT_SUPPORTED -/*****************************************************************************/ -/** - * qdma_en_st() - Enable Streaming - * - * @cmd: command information - * - * Return: >=0 for success and <0 for error - * - *****************************************************************************/ -int qdma_en_st(struct xcmd_info *cmd); -#endif - -#endif /* QDMAUTILS_H */ diff --git a/QDMA/linux-kernel/apps/dma-utils/dmaxfer.c b/QDMA/linux-kernel/apps/dma-utils/dmaxfer.c deleted file mode 100755 index b0c9b8ea5..000000000 --- a/QDMA/linux-kernel/apps/dma-utils/dmaxfer.c +++ /dev/null @@ -1,1118 +0,0 @@ -/* - * This file is part of the QDMA userspace application - * to enable the user to execute the QDMA functionality - * - * Copyright (c) 2018-2022, Xilinx, Inc. All rights reserved. - * Copyright (c) 2022-2023, Advanced Micro Devices, Inc. All rights reserved. - * - * This source code is licensed under BSD-style license (found in the - * LICENSE file in the root directory of this source tree) - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include "dmaxfer.h" - -#define SEC2NSEC 1000000000 -#define SEC2USEC 1000000 - -#define DATA_VALIDATION 0 -#define MSEC2NSEC 1000000 - -struct dmaxfer_perf_handle { - int shmid; - unsigned int active_threads; - int *child_pid_lst; -}; - -struct dma_meminfo { - void *memptr; - unsigned int num_blks; -}; - -enum dmaio_direction { - DMAIO_READ, - DMAIO_WRITE, - DMAIO_RDWR, -}; - -#define USE_MEMPOOL - -struct mempool_handle { - void *mempool; - unsigned int mempool_blkidx; - unsigned int mempool_blksz; - unsigned int total_memblks; - struct dma_meminfo *mempool_info; -#ifdef DEBUG - unsigned int id; - unsigned int loop; -#endif -}; - -struct io_info { - unsigned int num_req_submitted; - unsigned int num_req_completed; - struct list_head *head; - struct list_head *tail; - sem_t llock; - int pid; - int fd; - pthread_t evt_id; - enum dmaio_direction dir; -#ifdef DEBUG - unsigned long long total_nodes; - unsigned long long freed_nodes; -#endif - unsigned int thread_id; - unsigned int max_reqs; - struct dmaxfer_io_info *dinfo; - bool io_exit; - bool force_exit; - struct timespec g_ts_start; - struct timespec ts_cur; - struct mempool_handle ctxhandle; - struct mempool_handle iocbhandle; - struct mempool_handle datahandle; -}; - -struct list_head { - struct list_head *next; - unsigned int max_events; - unsigned int completed_events; - io_context_t ctxt; -}; - -#if DATA_VALIDATION -unsigned short valid_data[2*1024]; -#endif - -static void clear_events(struct io_info *_info, struct list_head *node); -static void dump_thrd_info(struct io_info *_info) { - printf("dir = %d\n", _info->dir); -} - -static int mempool_create(struct mempool_handle *mpool, unsigned int entry_size, - unsigned int max_entries) -{ -#ifdef USE_MEMPOOL - if (posix_memalign((void **)&mpool->mempool, DMAPERF_PAGE_SIZE, - max_entries * (entry_size + sizeof(struct dma_meminfo)))) { - printf("OOM Mempool\n"); - return -ENOMEM; - } - mpool->mempool_info = (struct dma_meminfo *)(((char *)mpool->mempool) + (max_entries * entry_size)); -#endif - mpool->mempool_blksz = entry_size; - mpool->total_memblks = max_entries; - mpool->mempool_blkidx = 0; - - return 0; -} - -static void mempool_free(struct mempool_handle *mpool) -{ -#ifdef USE_MEMPOOL - free(mpool->mempool); - mpool->mempool = NULL; -#endif -} - -static void *dma_memalloc(struct mempool_handle *mpool, unsigned int num_blks) -{ - unsigned int _mempool_blkidx = mpool->mempool_blkidx; - unsigned int tmp_blkidx = _mempool_blkidx; - unsigned int max_blkcnt = tmp_blkidx + num_blks; - unsigned int i, avail = 0; - void *memptr = NULL; - char *mempool = mpool->mempool; - struct dma_meminfo *_mempool_info = mpool->mempool_info; - unsigned int _total_memblks = mpool->total_memblks; - -#ifdef USE_MEMPOOL - if (max_blkcnt > _total_memblks) { - tmp_blkidx = 0; - max_blkcnt = num_blks; - } - for (i = tmp_blkidx; (i < _total_memblks) && (i < max_blkcnt); i++) { - if (_mempool_info[i].memptr) { /* occupied blks ahead */ - i += _mempool_info[i].num_blks; - max_blkcnt = i + num_blks; - avail = 0; - tmp_blkidx = i; - } else - avail++; - if (max_blkcnt > _total_memblks) { /* reached the end of mempool. circle through*/ - if (num_blks > _mempool_blkidx) return NULL; /* Continuous num_blks not available */ - i = 0; - avail = 0; - max_blkcnt = num_blks; - tmp_blkidx = 0; - } - } - if (avail < num_blks) { /* no required available blocks */ - return NULL; - } - - memptr = &(mempool[tmp_blkidx * mpool->mempool_blksz]); - _mempool_info[tmp_blkidx].memptr = memptr; - _mempool_info[tmp_blkidx].num_blks = num_blks; - mpool->mempool_blkidx = tmp_blkidx + num_blks; -#else - memptr = calloc(num_blks, mpool->mempool_blksz); -#endif - - return memptr; -} - -static void dma_free(struct mempool_handle *mpool, void *memptr) -{ -#ifdef USE_MEMPOOL - struct dma_meminfo *_meminfo = mpool->mempool_info; - unsigned int idx; - - if (!memptr) return; - - idx = (memptr - mpool->mempool)/mpool->mempool_blksz; -#ifdef DEBUG - if (idx >= mpool->total_memblks) { - printf("Asserting: %u:Invalid memory index %u acquired\n", mpool->id, idx); - while(1); - } -#endif - - _meminfo[idx].num_blks = 0; - _meminfo[idx].memptr = NULL; -#else - free(memptr); -#endif -} - -static int dmasetio_info(struct io_info *info, struct dmaxfer_io_info *ptr, - unsigned int base, enum dmaio_direction dir) -{ - - int fd; - unsigned int flags; - - info[base].dir = dir; - info[base].dinfo = ptr; - info[base].thread_id = base; - info[base].max_reqs = ptr->max_req_outstanding; - sem_init(&info[base].llock, 0, 1); - - if (dir == DMAIO_READ) - flags = O_RDONLY | O_NONBLOCK; - else - flags = O_WRONLY | O_NONBLOCK; - - fd = open(ptr->file_name, flags); - if (fd < 0) - return fd; - info[base].fd = fd; - - return 0; -} - -static int create_thread_info(struct dmaxfer_io_info *list, - unsigned int num_entries, - unsigned int num_jobs) -{ - unsigned int base = 0; - unsigned int i, j; - struct io_info *_info; - int shmid; - - if ((shmid = shmget(IPC_PRIVATE, - num_jobs * sizeof(struct io_info), - IPC_CREAT | 0666)) < 0) - { - perror("smget returned -1\n"); - error(-1, errno, " "); - return -EINVAL; - } - - if ((_info = (struct io_info *) shmat(shmid, NULL, 0)) == (struct io_info *) -1) { - perror("Process shmat returned NULL\n"); - error(-1, errno, " "); - } - - for (i = 0; i < num_entries; i++) { - for (j = 0; j < list[i].num_jobs; j++) { - if ((list[i].write == DMAIO_RDWR) || - (list[i].write == DMAIO_READ)) { - dmasetio_info(_info, list + i, base, - DMAIO_READ); - base++; - } - if ((list[i].write == DMAIO_RDWR) || - (list[i].write == DMAIO_WRITE)) { - dmasetio_info(_info, list + i, base, - DMAIO_WRITE); - base++; - } - //dump_thrd_info(&_info[i]); - } - } - - if (shmdt(_info) == -1) { - perror("shmdt returned -1\n"); - error(-1, errno, " "); - } - return shmid; -} - -#define MAX_AIO_EVENTS 65536 - -static void list_add_tail(struct io_info *_info, struct list_head *node) -{ - sem_wait(&_info->llock); - if (_info->head == NULL) { - _info->head = node; - _info->tail = node; - } else { - _info->tail->next = node; - _info->tail = node; - } -#ifdef DEBUG - _info->total_nodes++; -#endif - sem_post( &_info->llock); -} - -static void list_add_head(struct io_info *_info, struct list_head *node) -{ - sem_wait(&_info->llock); - node->next = _info->head; - if (_info->head == NULL) { - _info->tail = node; - } - _info->head = node; - sem_post( &_info->llock); -} - -static struct list_head *list_pop(struct io_info *_info) -{ - struct list_head *node = NULL; - - sem_wait(&_info->llock); - node = _info->head; - if (_info->head == _info->tail) - _info->tail = NULL; - - if (node) - _info->head = node->next; - - sem_post(&_info->llock); - - return node; -} - -static void list_free(struct io_info *_info) -{ - struct list_head *node = NULL; - struct list_head *prev_node = NULL; - - sem_wait(&_info->llock); -#ifdef DEBUG - printf("Need to free %llu nodes in thrd%u\n", _info->total_nodes - _info->freed_nodes, _info->thread_id); -#endif - node = _info->head; - - while (node != NULL) { - clear_events(_info, node); - io_destroy(node->ctxt); - prev_node = node; - node = node->next; - dma_free(&_info->ctxhandle, prev_node); -#ifdef DEBUG - _info->freed_nodes++; -#endif - } - sem_post(&_info->llock); -} - -/* Subtract timespec t2 from t1 - * - * Both t1 and t2 must already be normalized - * i.e. 0 <= nsec < 1000000000 - */ -static int timespec_check(struct timespec *t) -{ - if ((t->tv_nsec < 0) || (t->tv_nsec >= 1000000000)) - return -1; - return 0; - -} - -void xfer_timespec_sub(struct timespec *t1, struct timespec *t2) -{ - if (timespec_check(t1) < 0) { - fprintf(stderr, "invalid time #1: %lld.%.9ld.\n", - (long long)t1->tv_sec, t1->tv_nsec); - return; - } - if (timespec_check(t2) < 0) { - fprintf(stderr, "invalid time #2: %lld.%.9ld.\n", - (long long)t2->tv_sec, t2->tv_nsec); - return; - } - t1->tv_sec -= t2->tv_sec; - t1->tv_nsec -= t2->tv_nsec; - if (t1->tv_nsec >= 1000000000) { - t1->tv_sec++; - t1->tv_nsec -= 1000000000; - } else if (t1->tv_nsec < 0) { - t1->tv_sec--; - t1->tv_nsec += 1000000000; - } -} - -static void clear_events(struct io_info *_info, struct list_head *node) { - struct io_event *events = NULL; - int num_events = 0; - unsigned int j, bufcnt; - struct timespec ts_cur = {1, 0}; - struct mempool_handle *iocbhandle; - struct mempool_handle *datahandle; - - iocbhandle = &_info->iocbhandle; - datahandle = &_info->datahandle; - - if (node->max_events <= node->completed_events) - return; -#ifdef DEBUG - printf("Thrd%u: Need to clear %u/%u events in node %p\n", - _info->thread_id, node->max_events - node->completed_events, - node->max_events, node); -#endif - events = calloc(node->max_events - node->completed_events, sizeof(struct io_event)); - if (events == NULL) { - printf("[%s] OOM\n", __func__); - return; - } - do { - num_events = io_getevents(node->ctxt, 1, - node->max_events - node->completed_events, events, - &ts_cur); - for (j = 0; (num_events > 0) && (j < num_events); j++) { - struct iocb *iocb = (struct iocb *)events[j].obj; - struct iovec *iov; - - node->completed_events++; - if (!iocb) { - printf("Error: Invalid IOCB from events\n"); - continue; - } - - iov = (struct iovec *)iocb->u.c.buf; - - for (bufcnt = 0; bufcnt < iocb->u.c.nbytes; bufcnt++) - dma_free(datahandle, iov[bufcnt].iov_base); - dma_free(iocbhandle, iocb); - } - } while ((num_events > 0) && (node->max_events > node->completed_events)); - - free(events); -} - -static void *event_mon(void *handle) -{ - unsigned int j, bufcnt; - struct io_info *_info; - struct io_event *events = NULL; - int num_events = 0; - struct timespec ts_cur = {0, 0}; -#if DATA_VALIDATION - unsigned short *rcv_data; - unsigned int k; -#endif - struct mempool_handle *ctxhandle; - struct mempool_handle *iocbhandle; - struct mempool_handle *datahandle; - - _info = (struct io_info *) handle; - - - ctxhandle = &_info->ctxhandle; - iocbhandle = &_info->iocbhandle; - datahandle = &_info->datahandle; - - events = calloc(MAX_AIO_EVENTS, sizeof(struct io_event)); - if (events == NULL) { - printf("OOM AIO_EVENTS\n"); - return NULL; - } - while (_info->io_exit == 0 && _info->force_exit == 0) { - struct list_head *node = list_pop(_info); - - if (!node) - continue; - - memset(events, 0, MAX_AIO_EVENTS * sizeof(struct io_event)); - do { - num_events = io_getevents(node->ctxt, 1, - node->max_events - node->completed_events, - events, &ts_cur); - for (j = 0; (num_events > 0) && (j < num_events); j++) { - struct iocb *iocb = (struct iocb *)events[j].obj; - struct iovec *iov = NULL; - - if (!iocb) { - printf("Error: Invalid IOCB from events\n"); - continue; - } - _info->num_req_completed += events[j].res; - - iov = (struct iovec *)(iocb->u.c.buf); - if (!iov) { - printf("invalid buffer\n"); - continue; - } -#if DATA_VALIDATION - rcv_data = iov[0].iov_base; - for (k = 0; k < (iov[0].iov_len/2) && events[j].res && !(events[j].res2); k += 8) { - printf("%04x: %04x %04x %04x %04x %04x %04x %04x %04x\n", k, - rcv_data[k], rcv_data[k+1], rcv_data[k+2], - rcv_data[k+3], rcv_data[k+4], rcv_data[k+5], - rcv_data[k+6], rcv_data[k+7]); - } -#endif - for (bufcnt = 0; (bufcnt < iocb->u.c.nbytes) && iov; bufcnt++) - dma_free(datahandle, iov[bufcnt].iov_base); - dma_free(iocbhandle, iocb); - } - if (num_events > 0) - node->completed_events += num_events; - if (node->completed_events >= node->max_events) { - io_destroy(node->ctxt); - dma_free(ctxhandle, node); - break; - } - } while ((_info->io_exit == 0) && (_info->force_exit == 0)); - - if (node->completed_events < node->max_events) - list_add_head(_info, node); - } - free(events); -#ifdef DEBUG - printf("Exiting evt_thrd: %u\n", _info->thread_id); -#endif - - return NULL; -} - -static void io_proc_cleanup(struct io_info *_info) -{ - _info->io_exit = 1; - pthread_join(_info->evt_id, NULL); - list_free(_info); - mempool_free(&_info->iocbhandle); - mempool_free(&_info->ctxhandle); - mempool_free(&_info->datahandle); - close(_info->fd); -} - -static void *io_thread(struct io_info *_info) -{ - struct dmaxfer_io_info *dinfo; - int ret; - int s; - unsigned int tsecs; - unsigned int max_io = MAX_AIO_EVENTS; - unsigned int cnt = 0; - pthread_attr_t attr; - unsigned int io_sz; - unsigned int burst_cnt; - unsigned int num_desc; - unsigned int max_reqs; - struct iocb *io_list[1]; - struct mempool_handle *ctxhandle; - struct mempool_handle *iocbhandle; - struct mempool_handle *datahandle; - - ctxhandle = &_info->ctxhandle; - iocbhandle = &_info->iocbhandle; - datahandle = &_info->datahandle; - - dinfo = _info->dinfo; - io_sz = dinfo->pkt_sz; - burst_cnt = dinfo->pkt_burst; - tsecs = dinfo->runtime; - num_desc = (io_sz + DMAPERF_PAGE_SIZE - 1) >> DMAPERF_PAGE_SHIFT; - max_reqs = _info->max_reqs; - - mempool_create(datahandle, num_desc*DMAPERF_PAGE_SIZE, - max_reqs + (burst_cnt * num_desc)); - mempool_create(ctxhandle, sizeof(struct list_head), max_reqs); - mempool_create(iocbhandle, - sizeof(struct iocb) + (burst_cnt * sizeof(struct iovec)), - max_reqs + (burst_cnt * num_desc)); -#ifdef DEBUG - ctxhandle->id = 1; - datahandle->id = 0; - iocbhandle->id = 2; -#endif - s = pthread_attr_init(&attr); - if (s != 0) - printf("pthread_attr_init failed\n"); - if (pthread_create(&_info->evt_id, &attr, event_mon, _info)) - return NULL; - - clock_gettime(CLOCK_MONOTONIC, &_info->g_ts_start); - - do { - struct list_head *node = NULL; - struct timespec ts_cur; - - if (tsecs) { - ret = clock_gettime(CLOCK_MONOTONIC, &ts_cur); - xfer_timespec_sub(&ts_cur, &_info->g_ts_start); - if (ts_cur.tv_sec >= tsecs) - break; - } - node = dma_memalloc(ctxhandle, 1); - if (!node) { - continue; - } - ret = io_queue_init(max_io, &node->ctxt); - if (ret != 0) { - printf("Error: io_setup error %d on %u\n", ret, _info->thread_id); - dma_free(ctxhandle, node); - sched_yield(); - continue; - } - cnt = 0; - node->max_events = max_io; - list_add_tail(_info, node); - do { - struct iovec *iov = NULL; - unsigned int iovcnt; - if (tsecs) { - ret = clock_gettime(CLOCK_MONOTONIC, &ts_cur); - xfer_timespec_sub(&ts_cur, &_info->g_ts_start); - if (ts_cur.tv_sec >= tsecs) { - node->max_events = cnt; - break; - } - } - - if (((_info->num_req_submitted - _info->num_req_completed) * - num_desc) > max_reqs) { - sched_yield(); - continue; - } - - io_list[0] = dma_memalloc(iocbhandle, 1); - if (io_list[0] == NULL) { - if (cnt) { - node->max_events = cnt; - break; - } - else { - sched_yield(); - continue; - } - } - iov = (struct iovec *)(io_list[0] + 1); - for (iovcnt = 0; iovcnt < burst_cnt; iovcnt++) { - iov[iovcnt].iov_base = dma_memalloc(datahandle, 1); - if (iov[iovcnt].iov_base == NULL) - break; - iov[iovcnt].iov_len = io_sz; - } - if (iovcnt == 0) { - dma_free(iocbhandle, io_list[0]); - continue; - } - if (_info->dir == DMAIO_WRITE) { -#if 0 - printf("DEBUG WRITE: _info->fd :%d iov:%d iovcnt:%d\n", - - _info->fd, iov, iovcnt); -#endif - io_prep_pwritev(io_list[0], - _info->fd, - iov, - iovcnt, - 0); - } else { - io_prep_preadv(io_list[0], - _info->fd, - iov, - iovcnt, - 0); - } - - ret = io_submit(node->ctxt, 1, io_list); - if(ret != 1) { - for (; iovcnt > 0; iovcnt--) - dma_free(datahandle, iov[iovcnt].iov_base); - dma_free(iocbhandle, io_list[0]); - node->max_events = cnt; - break; - } else { - cnt++; - _info->num_req_submitted += iovcnt; - sched_yield(); - } - } while (!_info->force_exit && (cnt < max_io)); - } while (!_info->force_exit); - io_proc_cleanup(_info); - - return _info; -} - -#ifdef DEBUG -static void dump_result(unsigned long long total_io_sz) -{ - unsigned long long gig_div = ((unsigned long long)tsecs * 1000000000); - unsigned long long meg_div = ((unsigned long long)tsecs * 1000000); - unsigned long long kil_div = ((unsigned long long)tsecs * 1000); - unsigned long long byt_div = ((unsigned long long)tsecs); - - if ((total_io_sz/gig_div)) { - printf("BW = %f GB/sec\n", ((double)total_io_sz/gig_div)); - } else if ((total_io_sz/meg_div)) { - printf("BW = %f MB/sec\n", ((double)total_io_sz/meg_div)); - } else if ((total_io_sz/kil_div)) { - printf("BW = %f KB/sec\n", ((double)total_io_sz/kil_div)); - } else - printf("BW = %f Bytes/sec\n", ((double)total_io_sz/byt_div)); -} -#endif - -int is_valid_fd(int fd) -{ - return fcntl(fd, F_GETFL) != -1 || errno != EBADF; -} - -static void cleanup(struct dmaxfer_io_info *list, - unsigned int num_entries, - unsigned int num_threads) -{ - struct io_info *info; - struct dmaxfer_io_info *dinfo; - struct dmaxfer_perf_handle *handle; - int shmid; - int i; - - if (!list || !num_entries) - return; - - handle = (struct dmaxfer_perf_handle *)list->handle; - if (!handle) - return; - - if (handle->shmid > 0) - shmid = handle->shmid; - else - return; - - if ((info = (struct io_info *)shmat(shmid, NULL, 0)) == - (struct io_info *) -1) { - perror("Process shmat returned NULL\n"); - error(-1, errno, " "); - return; - } - - /* accumulate the statistics */ - for (i = 0; i < num_threads; i++) { - dinfo = info[i].dinfo; - dinfo->pps += info[i].num_req_completed; - } - for (i = 0; i < num_entries; i++) { - dinfo = &list[i]; - dinfo->pps /= dinfo->runtime; - } - - if (shmdt(info) == -1) { - perror("shmdt returned -1\n"); - error(-1, errno, " "); - } - - if (shmctl(shmid, IPC_RMID, NULL) == -1) { - perror("shmctl returned -1\n"); - error(-1, errno, " "); - } -} - -int dmaxfer_perf_run(struct dmaxfer_io_info *list, - unsigned int num_entries) -{ - unsigned int i; - unsigned int aio_max_nr = 0xFFFFFFFF; - char aio_max_nr_cmd[100] = {'\0'}; - unsigned int num_thrds = 0; - unsigned int tot_num_jobs; - struct dmaxfer_perf_handle *handle; - struct io_info *info; - int shmid; - int base_pid; - int *child_pid_lst; - -#if DATA_VALIDATION - for (i = 0; i < 2*1024; i++) - valid_data[i] = i; -#endif - - if (!list) { - perror("Invalid configuration\n"); - return -EINVAL; - } - - - snprintf(aio_max_nr_cmd, 100, "echo %u > /proc/sys/fs/aio-max-nr", - aio_max_nr); - system(aio_max_nr_cmd); - - handle = (struct dmaxfer_perf_handle *)calloc(1, sizeof(struct dmaxfer_perf_handle)); - if (!handle) - return -ENOMEM; - - /** Validate input config and calculate SHM segments required */ - tot_num_jobs = 0; - for (i = 0; i < num_entries; i++) { - if (!list[i].file_name) { - perror("Invalid device File Name\n"); - error(-1, errno, " "); - return -EINVAL; - } - - if (list[i].num_jobs <= 0) { - perror("Invalid number of jobs at entry\n"); - return -EINVAL; - } - if (list[i].write == DMAIO_RDWR) - tot_num_jobs += list[i].num_jobs * 2; - else - tot_num_jobs += list[i].num_jobs; - list[i].handle = (unsigned long)handle; - } - - shmid = create_thread_info(list, num_entries, tot_num_jobs); - if (shmid < 0) { - printf("ERROR: Invalid SHMID\n"); - return shmid; - } - - handle->shmid = shmid; - handle->active_threads = num_thrds = tot_num_jobs; - printf("dmautils(%u) threads\n", num_thrds); - base_pid = getpid(); - if (num_thrds > 1) { - handle->child_pid_lst = child_pid_lst = calloc(num_thrds, sizeof(int)); - child_pid_lst[0] = base_pid; - for (i = 1; i < num_thrds; i++) { - if (getpid() == base_pid) - child_pid_lst[i] = fork(); - else - break; - } - } - - if ((info = (struct io_info *) shmat(shmid, NULL, 0)) == (struct io_info *) -1) { - perror("Process shmat returned NULL\n"); - error(-1, errno, " "); - return -EINVAL; - } - - if (getpid() == base_pid) { - info->pid = base_pid; - io_thread(info); - if (num_thrds > 1) { - for(i = 1; i < num_thrds; i++) { - waitpid(child_pid_lst[i], NULL, 0); - info[i].pid = 0; - handle->active_threads--; - } - free(handle->child_pid_lst); - handle->child_pid_lst = NULL; - } - if ((shmdt(info) == -1)) { - perror("shmdt returned -1\n"); - error(-1, errno, " "); - } - cleanup(list, num_entries, num_thrds); - //active_threads = 0; - } else { - info[i - 1].pid = getpid(); - io_thread(&info[i - 1]); - if ((shmdt(info) == -1)) { - perror("shmdt returned -1\n"); - error(-1, errno, " "); - } - return (i - 1); - } - - return 0; -} - -#define RW_MAX_SIZE 0x7ffff000 -static ssize_t write_from_buffer(int fd, char *buffer, uint64_t size, - uint64_t base) -{ - ssize_t rc; - uint64_t count = 0; - char *buf = buffer; - off_t offset = base; - - do { /* Support zero byte transfer */ - uint64_t bytes = size - count; - - if (bytes > RW_MAX_SIZE) - bytes = RW_MAX_SIZE; - - if (offset) { - rc = lseek(fd, offset, SEEK_SET); - if (rc < 0) { - fprintf(stderr, - "seek off 0x%lx failed %zd.\n", - offset, rc); - perror("seek file"); - return -EIO; - } - if (rc != offset) { - fprintf(stderr, - "seek off 0x%lx != 0x%lx.\n", - rc, offset); - return -EIO; - } - } - - /* write data to file from memory buffer */ - rc = write(fd, buf, bytes); - if (rc < 0) { - fprintf(stderr, "W off 0x%lx, 0x%lx failed %zd.\n", - offset, bytes, rc); - perror("write file"); - return -EIO; - } - if (rc != bytes) { - fprintf(stderr, "W off 0x%lx, 0x%lx != 0x%lx.\n", - offset, rc, bytes); - return -EIO; - } - - count += bytes; - buf += bytes; - offset += bytes; - } while (count < size); - - if (count != size) { - fprintf(stderr, "R failed 0x%lx != 0x%lx.\n", - count, size); - return -EIO; - } - - return count; -} - -static ssize_t read_to_buffer(int fd, char *buffer, uint64_t size, - uint64_t base) -{ - ssize_t rc; - uint64_t count = 0; - char *buf = buffer; - off_t offset = base; - - do { /* Support zero byte transfer */ - uint64_t bytes = size - count; - - if (bytes > RW_MAX_SIZE) - bytes = RW_MAX_SIZE; - - if (offset) { - rc = lseek(fd, offset, SEEK_SET); - if (rc < 0) { - fprintf(stderr, - "seek off 0x%lx failed %zd.\n", - offset, rc); - perror("seek file"); - return -EIO; - } - if (rc != offset) { - fprintf(stderr, - "seek off 0x%lx != 0x%lx.\n", - rc, offset); - return -EIO; - } - } - - /* read data from file into memory buffer */ - rc = read(fd, buf, bytes); - if (rc < 0) { - fprintf(stderr, - "read off 0x%lx + 0x%lx failed %zd.\n", - offset, bytes, rc); - perror("read file"); - return -EIO; - } - if (rc != bytes) { - fprintf(stderr, - "R off 0x%lx, 0x%lx != 0x%lx.\n", - count, rc, bytes); - return -EIO; - } - - count += bytes; - buf += bytes; - offset += bytes; - } while (count < size); - - if (count != size) { - fprintf(stderr, "R failed 0x%lx != 0x%lx.\n", - count, size); - return -EIO; - } - - return count; -} - -ssize_t dmaperf_asynciosubmit(int fd, char *buffer, ssize_t size, - uint64_t offset, bool write) -{ - io_context_t aioctx; - struct iocb *iocb; - struct iocb *iocbp; - struct iovec *iov; - struct io_event event; - struct timespec ts_cur = {1, 0}; - unsigned int num_events; - int ret; - - memset(&aioctx, 0, sizeof(aioctx)); - ret = io_queue_init(1, &aioctx); - if (ret != 0) { - printf("Error: io_setup error %d\n", ret); - return ret; - } - - iocb = (struct iocb *) calloc(sizeof(struct iocb), 1); - if (!iocb) { - printf("Error: OOM iocb\n"); - return -ENOMEM; - } - - if (write) - io_prep_pwrite(iocb, fd, buffer, 1, offset); - else - io_prep_pread(iocb, fd, buffer, 1, offset); - - ret = io_submit(aioctx, 1, &iocb); - if(ret != 1) { - printf("Error: io_submit failed\n"); - io_destroy(aioctx); - return ret; - } - - num_events = io_getevents(aioctx, 1, 1, - &event, &ts_cur); - - if (num_events != 1) { - printf("Error: io_getevents timed out\n"); - return -EIO; - } - - iocbp = (struct iocb *)event.obj; - if (!iocbp) { - printf("Error: Invalid IOCB from events\n"); - return -EIO; - } - - iov = (struct iovec *)(iocbp->u.c.buf); - if (!iov) { - printf("invalid buffer\n"); - return -EIO; - } - - return size; -} - -ssize_t dmaxfer_iosubmit(char *fname, unsigned char write, - enum dmaxfer_io_type io_type, char *buffer, - uint64_t size) -{ - unsigned int flags; - ssize_t count; - int fd; - unsigned int base = 0; - - if (!fname || !buffer || size == 0) { - printf("Invalid arguments\n"); - return -EINVAL; - } - - if (write) - flags = O_WRONLY | O_NONBLOCK; - else - flags = O_RDONLY | O_NONBLOCK; - - fd = open(fname, flags); - if (fd < 0) - return fd; - - if (io_type == DMAXFER_IO_SYNC) - if (write) - count = write_from_buffer(fd, buffer, size, base); - else - count = read_to_buffer(fd, buffer, size, base); - else - count = dmaperf_asynciosubmit(fd, buffer, size, base, write); - - close(fd); - - return count; -} - -void dmaxfer_perf_stop(struct dmaxfer_io_info *list, - unsigned int num_entries) -{ - struct dmaxfer_perf_handle *handle; - struct io_info *info; - int shmid; - int i; - - handle = (struct dmaxfer_perf_handle *)list->handle; - if (!handle) - return; - - if (handle->shmid <= 0) - return; - shmid = handle->shmid; - - if ((info = (struct io_info *)shmat(shmid, NULL, 0)) == (struct io_info *) -1) { - perror("Process shmat returned NULL\n"); - error(-1, errno, " "); - return; - } - - for (i = 0; i < handle->active_threads; i++) { - sem_wait(&info[i].llock); - info[i].io_exit = 1; - sem_post(&info[i].llock); - } -} diff --git a/QDMA/linux-kernel/apps/dma-utils/dmaxfer.h b/QDMA/linux-kernel/apps/dma-utils/dmaxfer.h deleted file mode 100755 index 0dda0d1d2..000000000 --- a/QDMA/linux-kernel/apps/dma-utils/dmaxfer.h +++ /dev/null @@ -1,46 +0,0 @@ -/* - * This file is part of the QDMA userspace application - * to enable the user to execute the QDMA functionality - * - * Copyright (c) 2019 - 2022, Xilinx, Inc. - * All rights reserved. - * - * This source code is licensed under BSD-style license (found in the - * LICENSE file in the root directory of this source tree) - */ - -#ifndef __DMAXFER_H__ -#define __DMAXFER_H__ - -#include "dmautils.h" -#define DMAPERF_PAGE_SIZE 4096 -#define DMAPERF_PAGE_SHIFT 12 - - -enum dmaxfer_io_type { - DMAXFER_IO_SYNC, - DMAXFER_IO_ASYNC -}; - -struct dmaxfer_io_info { - char *file_name; - unsigned char write; - int num_jobs; - int pkt_sz; - int pkt_burst; - int runtime; - unsigned int max_req_outstanding; - unsigned long long int pps; - int (*app_env_init)(unsigned long *handle); - int (*app_env_exit)(unsigned long *handle); - unsigned long handle; -}; - -int dmaxfer_perf_run(struct dmaxfer_io_info *list, - unsigned int num_entries); -void dmaxfer_perf_stop(struct dmaxfer_io_info *list, - unsigned int num_entries); -ssize_t dmaxfer_iosubmit(char *fname, unsigned char write, - enum dmaxfer_io_type io_type, char *buffer, - uint64_t size); -#endif /* __DMAXFER_H__ */ diff --git a/QDMA/linux-kernel/apps/dma-utils/version.h b/QDMA/linux-kernel/apps/dma-utils/version.h deleted file mode 100755 index 7e540efcb..000000000 --- a/QDMA/linux-kernel/apps/dma-utils/version.h +++ /dev/null @@ -1,19 +0,0 @@ -/* - * This file is part of the QDMA userspace application - * to enable the user to execute the QDMA functionality - * - * Copyright (c) 2019-2022, Xilinx, Inc. All rights reserved. - * Copyright (c) 2022-2023, Advanced Micro Devices, Inc. All rights reserved. - * - * This source code is licensed under BSD-style license (found in the - * LICENSE file in the root directory of this source tree) - */ - -#ifndef __DMA_UTILS_VERSION_H -#define __DMA_UTILS_VERSION_H - -#define LIBNAME "dma-utils" -#define QDMATUILS_VERSION "2023.2.0" -#define COPYRIGHT "Copyright (c) 2022-2023 Advanced Micro Devices Inc." - -#endif diff --git a/QDMA/linux-kernel/apps/dma-xfer/Makefile b/QDMA/linux-kernel/apps/dma-xfer/Makefile deleted file mode 100755 index f30478ae1..000000000 --- a/QDMA/linux-kernel/apps/dma-xfer/Makefile +++ /dev/null @@ -1,39 +0,0 @@ -# -#/* -# * This file is part of the QDMA userspace application -# * to enable the user to execute the QDMA functionality -# * -# * Copyright (c) 2018-2022, Xilinx, Inc. All rights reserved. -# * Copyright (c) 2022-2023, Advanced Micro Devices, Inc. All rights reserved. -# * -# * This source code is licensed under BSD-style license (found in the -# * LICENSE file in the root directory of this source tree) -# */ - -CC ?= gcc - -CFLAGS += -g -#CFLAGS += -O2 -fno-inline -Wall -Wstrict-prototypes -CFLAGS += -I. -I../include -I../dma-utils -CFLAGS += $(EXTRA_FLAGS) - -DMA-XFER = dma-xfer -DMA-UTILS_OBJS := $(patsubst %.c,%.o,$(wildcard ../dma-utils/*.c)) -DMA-XFER_OBJS := dmaxfer.o -DMA-XFER_OBJS += $(DMA-UTILS_OBJS) - -ifneq ($(CROSS_COMPILE_FLAG),) - CC=$(CROSS_COMPILE_FLAG)gcc -endif - -all: clean dma-xfer - -dma-xfer: $(DMA-XFER_OBJS) - $(CC) -pthread -lrt $^ -o $(DMA-XFER) -laio -D_FILE_OFFSET_BITS=64 -D_GNU_SOURCE -D_LARGE_FILE_SOURCE - -%.o: %.c - $(CC) $(CFLAGS) -c -std=c99 -o $@ $< -D_FILE_OFFSET_BITS=64 -D_GNU_SOURCE -D_LARGE_FILE_SOURCE -D_AIO_AIX_SOURCE - -clean: - @rm -f *.o */*.o ../dma-utils/*.o - rm -rf *.o *.bin dma-xfer diff --git a/QDMA/linux-kernel/apps/dma-xfer/dmaxfer.c b/QDMA/linux-kernel/apps/dma-xfer/dmaxfer.c deleted file mode 100755 index 23945bd3f..000000000 --- a/QDMA/linux-kernel/apps/dma-xfer/dmaxfer.c +++ /dev/null @@ -1,1266 +0,0 @@ -/* - * This file is part of the QDMA userspace application - * to enable the user to execute the QDMA functionality - * - * Copyright (c) 2018-2022, Xilinx, Inc. All rights reserved. - * Copyright (c) 2022-2023, Advanced Micro Devices, Inc. All rights reserved. - * - * This source code is licensed under BSD-style license (found in the - * LICENSE file in the root directory of this source tree) - */ -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include "version.h" -#include "dmautils.h" -#include "qdma_nl.h" -#include "dmaxfer.h" - -#define QDMA_Q_NAME_LEN 100 -#define QDMA_ST_MAX_PKT_SIZE 0x7000 -#define QDMA_RW_MAX_SIZE 0x7ffff000 -#define QDMA_GLBL_MAX_ENTRIES (16) - -static struct queue_info *q_info; -static int q_count; - -enum qdma_q_dir { - QDMA_Q_DIR_H2C, - QDMA_Q_DIR_C2H, - QDMA_Q_DIR_BIDI -}; - -enum qdma_q_mode { - QDMA_Q_MODE_MM, - QDMA_Q_MODE_ST -}; - -struct queue_info { - char *q_name; - int qid; - int pf; - enum qdmautils_io_dir dir; -}; - -enum qdma_q_mode mode; -enum qdma_q_dir dir; -static char cfg_name[64]; -static unsigned int pkt_sz; -static unsigned int pci_bus; -static unsigned int pci_dev; -static int fun_id = -1; -static int is_vf; -static unsigned int q_start; -static unsigned int num_q; -static unsigned int idx_rngsz; -static unsigned int idx_tmr; -static unsigned int idx_cnt; -static unsigned int pfetch_en; -static unsigned int cmptsz; -static char input_file[128]; -static char output_file[128]; -static int io_type; -static char trigmode_str[10]; -static unsigned char trig_mode; - -static struct option const long_opts[] = { - {"config", required_argument, NULL, 'c'}, - {0, 0, 0, 0} -}; - -static void prep_reg_dump(void); - -static void usage(const char *name) -{ - fprintf(stdout, "%s\n\n", name); - fprintf(stdout, "usage: %s [OPTIONS]\n\n", name); - - fprintf(stdout, " -%c (--%s) config file that has configration for IO\n", - long_opts[0].val, long_opts[0].name); - fprintf(stdout, " -v (--version), to print version name\n"); -} - -static unsigned int num_trailing_blanks(char *word) -{ - unsigned int i = 0; - unsigned int slen = strlen(word); - - if (!slen) return 0; - while (isspace(word[slen - i - 1])) { - i++; - } - - return i; -} - -static char * strip_blanks(char *word, long unsigned int *banlks) -{ - char *p = word; - unsigned int i = 0; - - while (isblank(p[0])) { - p++; - i++; - } - if (banlks) - *banlks = i; - - return p; -} - -static unsigned int copy_value(char *src, char *dst, unsigned int max_len) -{ - char *p = src; - unsigned int i = 0; - - while (max_len && !isspace(p[0])) { - dst[i] = p[0]; - p++; - i++; - max_len--; - } - - return i; -} - -static char * strip_comments(char *word) -{ - size_t numblanks; - char *p = strip_blanks(word, &numblanks); - - if (p[0] == '#') - return NULL; - else - p = strtok(word, "#"); - - return p; -} - -static int arg_read_int(char *s, uint32_t *v) -{ - char *p = NULL; - - - *v = strtoul(s, &p, 0); - if (*p && (*p != '\n') && !isblank(*p)) { - printf("Error:something not right%s %s %s", - s, p, isblank(*p)? "true": "false"); - return -EINVAL; - } - return 0; -} - -static int arg_read_int_array(char *s, unsigned int *v, unsigned int max_arr_size) -{ - unsigned int slen = strlen(s); - unsigned int trail_blanks = num_trailing_blanks(s); - char *str = (char *)malloc(slen - trail_blanks + 1); - char *elem; - int cnt = 0; - int ret; - - memset(str, '\0', slen + 1); - strncpy(str, s + 1, slen - trail_blanks - 2); - str[slen] = '\0'; - - elem = strtok(str, " ,");/* space or comma separated */ - while (elem != NULL) { - ret = arg_read_int(elem, &v[cnt]); - if (ret < 0) { - printf("ERROR: Invalid array element %sin %s\n", elem, s); - exit(0); - } - cnt++; - elem = strtok(NULL, " ,"); - if (cnt > (int)max_arr_size) { /* to avoid out of bounds */ - printf("ERROR: More than expected number of elements in %s - expected = %u\n", - str, max_arr_size); - exit(0); - } - } - free(str); - - return cnt; -} - -static int get_array_len(char *s) -{ - int i, len = 0; - - if (strlen(s) < 2) - return -EINVAL; - if ((s[0] != '(') && (s[strlen(s) - 1] != ')')) - return -EINVAL; - if ((s[0] == '(') && (s[1] == ')')) - return 0; - for (i = 0; i < (int)strlen(s); i++) { - if ((s[i] == ' ') || (s[i] == ',')) /* space or comma separated */ - len++; - if (s[i] == ')') - break; - } - - return (len + 1); - -} - -static ssize_t read_to_buffer(char *fname, int fd, char *buffer, - uint64_t size, uint64_t base) -{ - ssize_t rc; - uint64_t count = 0; - char *buf = buffer; - off_t offset = base; - - do { /* Support zero byte transfer */ - uint64_t bytes = size - count; - - if (bytes > QDMA_RW_MAX_SIZE) - bytes = QDMA_RW_MAX_SIZE; - - if (offset) { - rc = lseek(fd, offset, SEEK_SET); - if (rc < 0) { - printf("Error: %s, seek off 0x%lx failed %zd\n", - fname, offset, rc); - return -EIO; - } - if (rc != offset) { - printf("Error: %s, seek off 0x%lx != 0x%lx\n", - fname, rc, offset); - return -EIO; - } - } - - /* read data from file into memory buffer */ - rc = read(fd, buf, bytes); - if (rc < 0) { - printf("Failed to Read %s, read off 0x%lx + 0x%lx failed %zd\n", - fname, offset, bytes, rc); - return -EIO; - } - if (rc != bytes) { - printf("Failed to read %lx bytes from file %s, curr read:%lx\n", - bytes, fname, rc); - return -EIO; - } - - count += bytes; - buf += bytes; - offset += bytes; - - } while (count < size); - - if (count != size) { - printf("Failed to read %lx bytes from %s 0x%lx != 0x%lx.\n", - size, fname, count, size); - return -EIO; - } - - return count; -} - -static ssize_t write_from_buffer(char *fname, int fd, char *buffer, - uint64_t size, uint64_t base) -{ - ssize_t rc; - uint64_t count = 0; - char *buf = buffer; - off_t offset = base; - - do { /* Support zero byte transfer */ - uint64_t bytes = size - count; - - if (bytes > QDMA_RW_MAX_SIZE) - bytes = QDMA_RW_MAX_SIZE; - - if (offset) { - rc = lseek(fd, offset, SEEK_SET); - if (rc < 0) { - printf("Error: %s, seek off 0x%lx failed %zd\n", - fname, offset, rc); - return -EIO; - } - if (rc != offset) { - printf("Error: %s, seek off 0x%lx != 0x%lx\n", - fname, rc, offset); - return -EIO; - } - } - - /* write data to file from memory buffer */ - rc = write(fd, buf, bytes); - if (rc < 0) { - printf("Failed to Read %s, read off 0x%lx + 0x%lx failed %zd\n", - fname, offset, bytes, rc); - return -EIO; - } - if (rc != bytes) { - printf("Failed to read %lx bytes from file %s, curr read:%lx\n", - bytes, fname, rc); - return -EIO; - } - - count += bytes; - buf += bytes; - offset += bytes; - - } while (count < size); - - if (count != size) { - printf("Failed to read %lx bytes from %s 0x%lx != 0x%lx\n", - size, fname, count, size); - return -EIO; - } - - return count; -} - -static int parse_config_file(const char *cfg_fname) -{ - char *linebuf = NULL; - char *realbuf; - FILE *fp; - size_t linelen = 0; - size_t numread; - size_t numblanks; - unsigned int linenum = 0; - char *config, *value; - unsigned int dir_factor = 1; - char rng_sz[100] = {'\0'}; - char rng_sz_path[200] = {'\0'}; - int rng_sz_fd, ret = 0; - int input_file_provided = 0; - int output_file_provided = 0; - struct stat st; - - fp = fopen(cfg_fname, "r"); - if (fp == NULL) { - printf("Failed to open Config File [%s]\n", cfg_fname); - return -EINVAL; - } - - while ((numread = getline(&linebuf, &linelen, fp)) != -1) { - numread--; - linenum++; - linebuf = strip_comments(linebuf); - if (linebuf == NULL) - continue; - realbuf = strip_blanks(linebuf, &numblanks); - linelen -= numblanks; - if (0 == linelen) - continue; - config = strtok(realbuf, "="); - value = strtok(NULL, "="); - if (!strncmp(config, "mode", 4)) { - if (!strncmp(value, "mm", 2)) - mode = QDMA_Q_MODE_MM; - else if(!strncmp(value, "st", 2)) - mode = QDMA_Q_MODE_ST; - else { - printf("Error: Unknown mode\n"); - goto prase_cleanup; - } - } else if (!strncmp(config, "dir", 3)) { - if (!strncmp(value, "h2c", 3)) - dir = QDMA_Q_DIR_H2C; - else if(!strncmp(value, "c2h", 3)) - dir = QDMA_Q_DIR_C2H; - else if(!strncmp(value, "bi", 2)) - dir = QDMA_Q_DIR_BIDI; - else if(!strncmp(value, "cmpt", 4)) { - printf("Error: cmpt type queue validation is not supported\n"); - goto prase_cleanup; - } else { - printf("Error: Unknown direction\n"); - goto prase_cleanup; - } - } else if (!strncmp(config, "name", 3)) { - copy_value(value, cfg_name, 64); - } else if (!strncmp(config, "function", 8)) { - if (arg_read_int(value, &fun_id)) { - printf("Error: Invalid function:%s\n", value); - goto prase_cleanup; - } - } else if (!strncmp(config, "is_vf", 5)) { - if (arg_read_int(value, &is_vf)) { - printf("Error: Invalid is_vf param:%s\n", value); - goto prase_cleanup; - } - if (is_vf > 1) { - printf("Error: is_vf value is %d, expected 0 or 1\n", - is_vf); - goto prase_cleanup; - } - } else if (!strncmp(config, "q_range", 7)) { - char *q_range_start = strtok(value, ":"); - char *q_range_end = strtok(NULL, ":"); - unsigned int start; - unsigned int end; - if (arg_read_int(q_range_start, &start)) { - printf("Error: Invalid q range start:%s\n", q_range_start); - goto prase_cleanup; - } - if (arg_read_int(q_range_end, &end)) { - printf("Error: Invalid q range end:%s\n", q_range_end); - goto prase_cleanup; - } - - q_start = start; - num_q = end - start + 1; - } else if (!strncmp(config, "rngidx", 6)) { - if (arg_read_int(value, &idx_rngsz)) { - printf("Error: Invalid idx_rngsz:%s\n", value); - goto prase_cleanup; - } - } else if (!strncmp(config, "tmr_idx", 7)) { - if (arg_read_int(value, &idx_tmr)) { - printf("Error: Invalid idx_tmr:%s\n", value); - goto prase_cleanup; - } - } - if (!strncmp(config, "cntr_idx", 8)) { - if (arg_read_int(value, &idx_cnt)) { - printf("Error: Invalid idx_cnt:%s\n", value); - goto prase_cleanup; - } - } else if (!strncmp(config, "pfetch_en", 9)) { - if (arg_read_int(value, &pfetch_en)) { - printf("Error: Invalid pfetch_en:%s\n", value); - goto prase_cleanup; - } - } else if (!strncmp(config, "cmptsz", 5)) { - if (arg_read_int(value, &cmptsz)) { - printf("Error: Invalid cmptsz:%s\n", value); - goto prase_cleanup; - } - } else if (!strncmp(config, "trig_mode", 9)) { - copy_value(value, trigmode_str, 10); - } else if (!strncmp(config, "pkt_sz", 6)) { - if (arg_read_int(value, &pkt_sz)) { - printf("Error: Invalid pkt_sz:%s\n", value); - goto prase_cleanup; - } - } else if (!strncmp(config, "pci_bus", 7)) { - char *p; - - pci_bus = strtoul(value, &p, 16); - if (*p && (*p != '\n')) { - printf("Error: bad parameter \"%s\", integer expected", value); - goto prase_cleanup; - } - } else if (!strncmp(config, "pci_dev", 7)) { - char *p; - - pci_dev = strtoul(value, &p, 16); - if (*p && (*p != '\n')) { - printf("Error: bad parameter \"%s\", integer expected", value); - goto prase_cleanup; - } - } else if (!strncmp(config, "inputfile", 7)) { - copy_value(value, input_file, 128); - input_file_provided = 1; - } else if (!strncmp(config, "outputfile", 7)) { - copy_value(value, output_file, 128); - output_file_provided = 1; - } else if (!strncmp(config, "io_type", 6)) { - if (!strncmp(value, "io_sync", 6)) - io_type = 0; - else if (!strncmp(value, "io_async", 6)) - io_type = 1; - else { - printf("Error: Unknown io_type\n"); - goto prase_cleanup; - } - } - } - fclose(fp); - - if (!pci_bus && !pci_dev) { - printf("Error: PCI bus information not provided\n"); - return -EINVAL; - } - - if (fun_id < 0) { - printf("Error: Valid function required\n"); - return -EINVAL; - } - - if (fun_id <= 3 && is_vf) { - printf("Error: invalid is_vf and fun_id values." - "Fun_id for vf must be higer than 3\n"); - return -EINVAL; - } - - if (mode == QDMA_Q_MODE_ST && pkt_sz > QDMA_ST_MAX_PKT_SIZE) { - printf("Error: Pkt size [%u] larger than supported size [%d]\n", - pkt_sz, QDMA_ST_MAX_PKT_SIZE); - return -EINVAL; - } - - if ((dir == QDMA_Q_DIR_H2C) || (dir == QDMA_Q_DIR_BIDI)) { - if (!input_file_provided) { - printf("Error: Input File required for Host to Card transfers\n"); - return -EINVAL; - } - - ret = stat(input_file, &st); - if (ret < 0) { - printf("Error: Failed to read input file [%s] length\n", - input_file); - return ret; - } - - if (pkt_sz > st.st_size) { - printf("Error: File [%s] length is lesser than pkt_sz %u\n", - input_file, pkt_sz); - return -EINVAL; - } - } - - if (((dir == QDMA_Q_DIR_C2H) || (dir == QDMA_Q_DIR_BIDI)) && - !output_file_provided) { - printf("Error: Data output file was not provided\n"); - return -EINVAL; - } - - if (!strcmp(trigmode_str, "every")) - trig_mode = 1; - else if (!strcmp(trigmode_str, "usr_cnt")) - trig_mode = 2; - else if (!strcmp(trigmode_str, "usr")) - trig_mode = 3; - else if (!strcmp(trigmode_str, "usr_tmr")) - trig_mode=4; - else if (!strcmp(trigmode_str, "cntr_tmr")) - trig_mode=5; - else if (!strcmp(trigmode_str, "dis")) - trig_mode = 0; - else { - printf("Error: unknown q trigmode %s.\n", trigmode_str); - return -EINVAL; - } - - return 0; - -prase_cleanup: - fclose(fp); - return -EINVAL; -} - -static inline void qdma_q_prep_name(struct queue_info *q_info, int qid, int pf) -{ - q_info->q_name = calloc(QDMA_Q_NAME_LEN, 1); - snprintf(q_info->q_name, QDMA_Q_NAME_LEN, "/dev/qdma%s%05x-%s-%d", - (is_vf) ? "vf" : "", - (pci_bus << 12) | (pci_dev << 4) | pf, - (mode == QDMA_Q_MODE_MM) ? "MM" : "ST", - qid); -} - -static int qdma_validate_qrange(void) -{ - struct xcmd_info xcmd; - int ret; - - memset(&xcmd, 0, sizeof(struct xcmd_info)); - xcmd.op = XNL_CMD_DEV_INFO; - xcmd.vf = is_vf; - xcmd.if_bdf = (pci_bus << 12) | (pci_dev << 4) | fun_id; - - /* Get dev info from qdma driver */ - ret = qdma_dev_info(&xcmd); - if (ret < 0) { - printf("Failed to read qmax for PF: %d\n", fun_id); - return ret; - } - - if (!xcmd.resp.dev_info.qmax) { - printf("Error: invalid qmax assigned to function :%d qmax :%u\n", - fun_id, xcmd.resp.dev_info.qmax); - return -EINVAL; - } - - if (xcmd.resp.dev_info.qmax < num_q) { - printf("Error: Q Range is beyond QMAX %u " - "Funtion: %x Q start :%u Q Range End :%u\n", - xcmd.resp.dev_info.qmax, fun_id, q_start, q_start + num_q); - return -EINVAL; - } - - return 0; -} - -static int qdma_prepare_q_stop(struct xcmd_info *xcmd, - enum qdmautils_io_dir dir, - int qid, int pf) -{ - struct xcmd_q_parm *qparm; - - if (!xcmd) - return -EINVAL; - - qparm = &xcmd->req.qparm; - - xcmd->op = XNL_CMD_Q_STOP; - xcmd->vf = is_vf; - xcmd->if_bdf = (pci_bus << 12) | (pci_dev << 4) | pf; - qparm->idx = qid; - qparm->num_q = 1; - - if (mode == QDMA_Q_MODE_MM) - qparm->flags |= XNL_F_QMODE_MM; - else if (mode == QDMA_Q_MODE_ST) - qparm->flags |= XNL_F_QMODE_ST; - else - return -EINVAL; - - if (dir == DMAXFER_IO_WRITE) - qparm->flags |= XNL_F_QDIR_H2C; - else if (dir == DMAXFER_IO_READ) - qparm->flags |= XNL_F_QDIR_C2H; - else - return -EINVAL; - - - return 0; -} - -static int qdma_prepare_q_start(struct xcmd_info *xcmd, - enum qdmautils_io_dir dir, - int qid, int pf) -{ - struct xcmd_q_parm *qparm; - - - if (!xcmd) { - printf("Error: Invalid Input Param\n"); - return -EINVAL; - } - qparm = &xcmd->req.qparm; - - xcmd->op = XNL_CMD_Q_START; - xcmd->vf = is_vf; - xcmd->if_bdf = (pci_bus << 12) | (pci_dev << 4) | pf; - qparm->idx = qid; - qparm->num_q = 1; - - if (mode == QDMA_Q_MODE_MM) - qparm->flags |= XNL_F_QMODE_MM; - else if (mode == QDMA_Q_MODE_ST) - qparm->flags |= XNL_F_QMODE_ST; - else { - printf("Error: Invalid mode\n"); - return -EINVAL; - } - - if (dir == DMAXFER_IO_WRITE) - qparm->flags |= XNL_F_QDIR_H2C; - else if (dir == DMAXFER_IO_READ) - qparm->flags |= XNL_F_QDIR_C2H; - else { - printf("Error: Invalid Direction\n"); - return -EINVAL; - } - - qparm->qrngsz_idx = idx_rngsz; - - if ((dir == QDMA_Q_DIR_C2H) && (mode == QDMA_Q_MODE_ST)) { - if (cmptsz) - qparm->cmpt_entry_size = cmptsz; - else - qparm->cmpt_entry_size = XNL_ST_C2H_CMPT_DESC_SIZE_8B; - qparm->cmpt_tmr_idx = idx_tmr; - qparm->cmpt_cntr_idx = idx_cnt; - qparm->cmpt_trig_mode = trig_mode; - if (pfetch_en) - qparm->flags |= XNL_F_PFETCH_EN; - } - - qparm->flags |= (XNL_F_CMPL_STATUS_EN | XNL_F_CMPL_STATUS_ACC_EN | - XNL_F_CMPL_STATUS_PEND_CHK | XNL_F_CMPL_STATUS_DESC_EN | - XNL_F_FETCH_CREDIT); - - return 0; -} - -static int qdma_prepare_q_del(struct xcmd_info *xcmd, - enum qdmautils_io_dir dir, - int qid, int pf) -{ - struct xcmd_q_parm *qparm; - - if (!xcmd) { - printf("Error: Invalid Input Param\n"); - return -EINVAL; - } - - qparm = &xcmd->req.qparm; - - xcmd->op = XNL_CMD_Q_DEL; - xcmd->vf = is_vf; - xcmd->if_bdf = (pci_bus << 12) | (pci_dev << 4) | pf; - qparm->idx = qid; - qparm->num_q = 1; - - if (mode == QDMA_Q_MODE_MM) - qparm->flags |= XNL_F_QMODE_MM; - else if (mode == QDMA_Q_MODE_ST) - qparm->flags |= XNL_F_QMODE_ST; - else { - printf("Error: Invalid mode\n"); - return -EINVAL; - } - - if (dir == DMAXFER_IO_WRITE) - qparm->flags |= XNL_F_QDIR_H2C; - else if (dir == DMAXFER_IO_READ) - qparm->flags |= XNL_F_QDIR_C2H; - else { - printf("Error: Invalid Direction\n"); - return -EINVAL; - } - - return 0; -} - -static int qdma_prepare_q_add(struct xcmd_info *xcmd, - enum qdmautils_io_dir dir, - int qid, int pf) -{ - struct xcmd_q_parm *qparm; - - if (!xcmd) { - printf("Error: Invalid Input Param\n"); - return -EINVAL; - } - - qparm = &xcmd->req.qparm; - - xcmd->op = XNL_CMD_Q_ADD; - xcmd->vf = is_vf; - xcmd->if_bdf = (pci_bus << 12) | (pci_dev << 4) | pf; - qparm->idx = qid; - qparm->num_q = 1; - - if (mode == QDMA_Q_MODE_MM) - qparm->flags |= XNL_F_QMODE_MM; - else if (mode == QDMA_Q_MODE_ST) - qparm->flags |= XNL_F_QMODE_ST; - else { - printf("Error: Invalid mode\n"); - return -EINVAL; - } - if (dir == DMAXFER_IO_WRITE) - qparm->flags |= XNL_F_QDIR_H2C; - else if (dir == DMAXFER_IO_READ) - qparm->flags |= XNL_F_QDIR_C2H; - else { - printf("Error: Invalid Direction\n"); - return -EINVAL; - } - qparm->sflags = qparm->flags; - - return 0; -} - -static int qdma_destroy_queue(enum qdmautils_io_dir dir, - int qid, int pf) -{ - struct xcmd_info xcmd; - int ret; - - memset(&xcmd, 0, sizeof(struct xcmd_info)); - ret = qdma_prepare_q_stop(&xcmd, dir, qid, pf); - if (ret < 0) - return ret; - - ret = qdma_q_stop(&xcmd); - if (ret < 0) - printf("Q_STOP failed, ret :%d\n", ret); - - memset(&xcmd, 0, sizeof(struct xcmd_info)); - qdma_prepare_q_del(&xcmd, dir, qid, pf); - ret = qdma_q_del(&xcmd); - if (ret < 0) - printf("Q_DEL failed, ret :%d\n", ret); - - return ret; -} - -static int qdma_create_queue(enum qdmautils_io_dir dir, - int qid, int pf) -{ - struct xcmd_info xcmd; - int ret; - - memset(&xcmd, 0, sizeof(struct xcmd_info)); - ret = qdma_prepare_q_add(&xcmd, dir, qid, pf); - if (ret < 0) - return ret; - - ret = qdma_q_add(&xcmd); - if (ret < 0) { - printf("Q_ADD failed, ret :%d\n", ret); - return ret; - } - - memset(&xcmd, 0, sizeof(struct xcmd_info)); - ret = qdma_prepare_q_start(&xcmd, dir, qid, pf); - if (ret < 0) - return ret; - - ret = qdma_q_start(&xcmd); - if (ret < 0) { - printf("Q_START failed, ret :%d\n", ret); - qdma_prepare_q_del(&xcmd, dir, qid, pf); - qdma_q_del(&xcmd); - } - - return ret; -} - -static int qdma_prepare_queue(struct queue_info *q_info, - enum qdmautils_io_dir dir, int qid, int pf) -{ - int ret; - - if (!q_info) { - printf("Error: Invalid queue info\n"); - return -EINVAL; - } - - qdma_q_prep_name(q_info, qid, pf); - q_info->dir = dir; - ret = qdma_create_queue(q_info->dir, qid, pf); - if (ret < 0) { - printf("Q creation Failed PF:%d QID:%d\n", - pf, qid); - return ret; - } - q_info->qid = qid; - q_info->pf = pf; - - return ret; -} - -static int qdma_register_write(unsigned int pf, int bar, - unsigned long reg, unsigned long value) -{ - struct xcmd_info xcmd; - struct xcmd_reg *regcmd; - int ret; - regcmd = &xcmd.req.reg; - xcmd.op = XNL_CMD_REG_WRT; - xcmd.vf = is_vf; - xcmd.if_bdf = (pci_bus << 12) | (pci_dev << 4) | pf; - regcmd->bar = bar; - regcmd->reg = reg; - regcmd->val = value; - regcmd->sflags = XCMD_REG_F_BAR_SET | - XCMD_REG_F_REG_SET | - XCMD_REG_F_VAL_SET; - - ret = qdma_reg_write(&xcmd); - if (ret < 0) - printf("QDMA_REG_WRITE Failed, ret :%d\n", ret); - - return ret; -} - -static void qdma_queues_cleanup(struct queue_info *q_info, int q_count) -{ - unsigned int q_index; - - if (!q_info || q_count < 0) - return; - - for (q_index = 0; q_index < q_count; q_index++) { - qdma_destroy_queue(q_info[q_index].dir, - q_info[q_index].qid, - q_info[q_index].pf); - free(q_info[q_index].q_name); - } -} - -static int qdma_setup_queues(struct queue_info **pq_info) -{ - struct queue_info *q_info; - unsigned int qid; - unsigned int q_count; - unsigned int q_index; - int ret; - - if (!pq_info) { - printf("Error: Invalid queue info\n"); - return -EINVAL; - } - - if (dir == QDMA_Q_DIR_BIDI) - q_count = num_q * 2; - else - q_count = num_q; - - *pq_info = q_info = (struct queue_info *)calloc(q_count, sizeof(struct queue_info)); - if (!q_info) { - printf("Error: OOM\n"); - return -ENOMEM; - } - - q_index = 0; - for (qid = 0; qid < num_q; qid++) { - if ((dir == QDMA_Q_DIR_BIDI) || - (dir == QDMA_Q_DIR_H2C)) { - ret = qdma_prepare_queue(q_info + q_index, - DMAXFER_IO_WRITE, - qid + q_start, - fun_id); - if (ret < 0) - break; - q_index++; - } - if ((dir == QDMA_Q_DIR_BIDI) || - (dir == QDMA_Q_DIR_C2H)) { - ret = qdma_prepare_queue(q_info + q_index, - DMAXFER_IO_READ, - qid + q_start, - fun_id); - if (ret < 0) - break; - q_index++; - } - } - if (ret < 0) { - qdma_queues_cleanup(q_info, q_index); - return ret; - } - - return q_count; -} - - -static void qdma_env_cleanup() -{ - qdma_queues_cleanup(q_info, q_count); - - if (q_info) - free(q_info); - q_info = NULL; - q_count = 0; -} - -static int qdma_trigger_data_generator(struct queue_info *q_info) -{ - struct xcmd_info xcmd; - unsigned char user_bar; - unsigned int qbase; - int ret; - - if (!q_info) { - printf("Error: Invalid queue info\n"); - return -EINVAL; - } - - memset(&xcmd, 0, sizeof(struct xcmd_info)); - xcmd.op = XNL_CMD_DEV_INFO; - xcmd.vf = is_vf; - xcmd.if_bdf = (pci_bus << 12) | (pci_dev << 4) | q_info->pf; - - ret = qdma_dev_info(&xcmd); - if (ret < 0) { - printf("Failed to read qmax for PF: %d\n", q_info->pf); - return ret; - } - - user_bar = xcmd.resp.dev_info.user_bar; - qbase = xcmd.resp.dev_info.qbase; - - /* Disable DMA Bypass */ - ret = qdma_register_write(q_info->pf, user_bar, 0x90, 0); - if (ret < 0) { - printf("Failed to program HWQID PF :%d QID :%d\n", - q_info->pf, q_info->qid); - return ret; - } - - /* Program HW QID */ - ret = qdma_register_write(q_info->pf, user_bar, 0x0, - q_info->qid + qbase); - if (ret < 0) { - printf("Failed to program HWQID PF :%d QID :%d\n", - q_info->pf, q_info->qid); - } - - /* Set the transfer size to data generator */ - ret = qdma_register_write(q_info->pf, user_bar, 0x04, - pkt_sz); - if (ret < 0) { - printf("Failed to set transfer size PF :%d QID :%d\n", - q_info->pf, q_info->qid); - } - - /* num packets to generate, setting to 1 */ - ret = qdma_register_write(q_info->pf, user_bar, 0x20, - 1); - if (ret < 0) { - printf("Failed to set transfer size PF :%d QID :%d\n", - q_info->pf, q_info->qid); - } - - /* trigger data generator */ - ret = qdma_register_write(q_info->pf, user_bar, 0x08, - 2); - if (ret < 0) { - printf("Failed to set transfer size PF :%d QID :%d\n", - q_info->pf, q_info->qid); - } - - return 0; -} - -static int qdmautils_read(struct queue_info *q_info, - char *output_file, int io_type) -{ - int outfile_fd = -1; - char *buffer = NULL; - char *allocated = NULL; - unsigned int size; - unsigned int offset; - int ret; - - if (!q_info || !input_file) { - printf("Error: Invalid input params\n"); - return -EINVAL; - } - - size = pkt_sz; - - outfile_fd = open(output_file, O_WRONLY | O_CREAT | O_TRUNC | O_SYNC); - if (outfile_fd < 0) { - printf("Error: unable to open/create output file %s, ret :%d\n", - output_file, outfile_fd); - perror("open/create output file"); - return outfile_fd; - } - - offset = 0; - posix_memalign((void **)&allocated, 4096 /*alignment */ , size + 4096); - if (!allocated) { - printf("Error: OOM %u.\n", size + 4096); - ret = -ENOMEM; - goto out; - } - buffer = allocated + offset; - - if (io_type == 0) { - ret = qdmautils_sync_xfer(q_info->q_name, - q_info->dir, buffer, size); - if (ret < 0) - printf("Error: QDMA SYNC transfer Failed, ret :%d\n", ret); - else - printf("PF :%d Queue :%d C2H Sync transfer success\n", q_info->pf, q_info->qid); - } else { - ret = qdmautils_async_xfer(q_info->q_name, - q_info->dir, buffer, size); - if (ret < 0) - printf("Error: QDMA ASYNC transfer Failed, ret :%d\n", ret); - else - printf("PF :%d Queue :%d C2H ASync transfer success\n", q_info->pf, q_info->qid); - } - if (ret < 0) - goto out; - - ret = write_from_buffer(output_file, outfile_fd, buffer, size, offset); - if (ret < 0) - printf("Error: Write from buffer to %s failed\n", output_file); -out: - free(allocated); - close(outfile_fd); - - return ret; -} - -static int qdmautils_write(struct queue_info *q_info, - char *input_file, int io_type) -{ - int infile_fd = -1; - int outfile_fd = -1; - char *buffer = NULL; - char *allocated = NULL; - unsigned int size; - unsigned int offset; - int ret; - enum qdmautils_io_dir dir; - - if (!q_info || !input_file) { - printf("Error: Invalid input params\n"); - return -EINVAL; - } - - size = pkt_sz; - - infile_fd = open(input_file, O_RDONLY | O_NONBLOCK); - if (infile_fd < 0) { - printf("Error: unable to open input file %s, ret :%d\n", - input_file, infile_fd); - return infile_fd; - } - - offset = 0; - posix_memalign((void **)&allocated, 4096 /*alignment */ , size + 4096); - if (!allocated) { - printf("Error: OOM %u.\n", size + 4096); - ret = -ENOMEM; - goto out; - } - - buffer = allocated + offset; - ret = read_to_buffer(input_file, infile_fd, buffer, size, 0); - if (ret < 0) - goto out; - - if (io_type == 0) { - ret = qdmautils_sync_xfer(q_info->q_name, - q_info->dir, buffer, size); - if (ret < 0) - printf("Error: QDMA SYNC transfer Failed, ret :%d\n", ret); - else - printf("PF :%d Queue :%d H2C Sync transfer success\n", q_info->pf, q_info->qid); - } else { - ret = qdmautils_async_xfer(q_info->q_name, - q_info->dir, buffer, size); - if (ret < 0) - printf("Error: QDMA ASYNC transfer Failed, ret :%d\n", ret); - else - printf("PF :%d Queue :%d H2C Async transfer success\n", q_info->pf, q_info->qid); - } - -out: - free(allocated); - close(infile_fd); - - return ret; -} - -static int qdmautils_xfer(struct queue_info *q_info, - unsigned int count, int io_type) -{ - int ret; - int i; - - if (!q_info || count == 0) { - printf("Error: Invalid input params\n"); - return -EINVAL; - } - - for (i = 0; i < count; i++) { - if (q_info[i].dir == DMAXFER_IO_WRITE) { - /* Transfer DATA from inputfile to Device */ - ret = qdmautils_write(q_info + i, input_file, io_type); - if (ret < 0) - printf("qdmautils_write failed, ret :%d\n", ret); - } else { - if (mode == QDMA_Q_MODE_ST) { - /* Generate ST - C2H Data before trying to read from Card */ - ret = qdma_trigger_data_generator(q_info + i); - if (ret < 0) { - printf("Failed to trigger data generator\n"); - return ret; - } - } - /* Reads data from Device and writes into output file */ - ret = qdmautils_read(q_info + i, output_file, io_type); - if (ret < 0) - printf("qdmautils_read failed, ret :%d\n", ret); - } - - if (ret < 0) - break; - } - - return ret; -} - -int main(int argc, char *argv[]) -{ - char *cfg_fname; - int cmd_opt; - int ret; - - if (argc == 2) { - if (!strcmp(argv[1], "-v") || !strcmp(argv[1], "--version")) { - printf("%s version %s\n", PROGNAME, VERSION); - printf("%s\n", COPYRIGHT); - return 0; - } - } - - cfg_fname = NULL; - while ((cmd_opt = getopt_long(argc, argv, "vhxc:c:", long_opts, - NULL)) != -1) { - switch (cmd_opt) { - case 0: - /* long option */ - break; - case 'c': - /* config file name */ - cfg_fname = strdup(optarg); - break; - default: - usage(argv[0]); - exit(0); - break; - } - } - - if (cfg_fname == NULL) { - printf("Config file required.\n"); - usage(argv[0]); - return -EINVAL; - } - - ret = parse_config_file(cfg_fname); - if (ret < 0) { - printf("Config File has invalid parameters\n"); - return ret; - } - - ret = qdma_validate_qrange(); - if (ret < 0) - return ret; - - q_count = 0; - /* Addition and Starting of queues handled here */ - q_count = qdma_setup_queues(&q_info); - if (q_count < 0) { - printf("qdma_setup_queues failed, ret:%d\n", q_count); - return q_count; - } - - /* queues has to be deleted upon termination */ - atexit(qdma_env_cleanup); - /* Perform DMA transfers on each Queue */ - ret = qdmautils_xfer(q_info, q_count, io_type); - if (ret < 0) - printf("Qdmautils Transfer Failed, ret :%d\n", ret); - - return ret; -} diff --git a/QDMA/linux-kernel/apps/dma-xfer/sample_qdma_xfer_config.txt b/QDMA/linux-kernel/apps/dma-xfer/sample_qdma_xfer_config.txt deleted file mode 100755 index d4a2c828e..000000000 --- a/QDMA/linux-kernel/apps/dma-xfer/sample_qdma_xfer_config.txt +++ /dev/null @@ -1,30 +0,0 @@ -# -#/* -# * This file is part of the QDMA userspace application -# * to enable the user to execute the QDMA functionality -# * -# * Copyright (c) 2018-2022, Xilinx, Inc. All rights reserved. -# * Copyright (c) 2022-2023, Advanced Micro Devices, Inc. All rights reserved. -# * -# * This source code is licensed under BSD-style license (found in the -# * LICENSE file in the root directory of this source tree) -# */ - -name=mm_sample -pci_bus=d8 -pci_device=00 -function=0 #fun_id -is_vf=0 -mode=mm #mode -dir=bi #dir -q_range=0:0 #no spaces -tmr_idx=6 -cntr_idx=6 -cmptsz=0 -trig_mode=cntr_tmr -pfetch_en=0 -rngidx=0 -pkt_sz=1024 -io_type=io_async -inputfile=INPUT -outputfile=OUTPUT diff --git a/QDMA/linux-kernel/apps/dma-xfer/version.h b/QDMA/linux-kernel/apps/dma-xfer/version.h deleted file mode 100755 index 31e865440..000000000 --- a/QDMA/linux-kernel/apps/dma-xfer/version.h +++ /dev/null @@ -1,18 +0,0 @@ -/* - * This file is part of the QDMA userspace application - * to enable the user to execute the QDMA functionality - * - * Copyright (c) 2019-2022, Xilinx, Inc. All rights reserved. - * Copyright (c) 2022-2023, Advanced Micro Devices, Inc. All rights reserved. - * - * This source code is licensed under BSD-style license (found in the - * LICENSE file in the root directory of this source tree) - */ -#ifndef __DMA_XFER_VERSION_H -#define __DMA_XFER_VERSION_H - -#define PROGNAME "dma-xfer" -#define VERSION "2023.2.0" -#define COPYRIGHT "Copyright (c) 2022-2023 Advanced Micro Devices Inc." - -#endif diff --git a/QDMA/linux-kernel/apps/include/qdma_nl.h b/QDMA/linux-kernel/apps/include/qdma_nl.h deleted file mode 100755 index fd8b43cd8..000000000 --- a/QDMA/linux-kernel/apps/include/qdma_nl.h +++ /dev/null @@ -1,480 +0,0 @@ -/* - * This file is part of the Xilinx DMA IP Core driver for Linux - * - * Copyright (c) 2018-2022, Xilinx, Inc. All rights reserved. - * Copyright (c) 2022-2023, Advanced Micro Devices, Inc. All rights reserved. - * - * This source code is licensed under both the BSD-style license (found in the - * LICENSE file in the root directory of this source tree) and the GPLv2 (found - * in the COPYING file in the root directory of this source tree). - * You may select, at your option, one of the above-listed licenses. - */ - -#ifndef QDMA_NL_H__ -#define QDMA_NL_H__ -/** - * @file - * @brief This file contains the declarations for qdma netlink interfaces - * - ** physical function name (no more than 15 characters) */ -#define XNL_NAME_PF "xnl_pf" -/** virtual function name */ -#define XNL_NAME_VF "xnl_vf" -/** qdma netlink interface version number */ -#define XNL_VERSION 0x1 - -/** qdma nl interface minimum response buffer length*/ -#define XNL_RESP_BUFLEN_MIN 256 -/** qdma nl interface maximum response buffer length*/ -#define XNL_RESP_BUFLEN_MAX (2048 * 10) -/** qdma nl interface error buffer length*/ -#define XNL_ERR_BUFLEN 64 -/** qdma nl command parameter length*/ -#define XNL_STR_LEN_MAX 20 - -/** Q parameter: value to indicate invalid qid*/ -#define XNL_QIDX_INVALID 0xFFFF -/** Q parameter: streaming mode*/ -#define XNL_F_QMODE_ST 0x00000001 -/** Q parameter: memory management mode*/ -#define XNL_F_QMODE_MM 0x00000002 -/** Q parameter: queue in h2c direction*/ -#define XNL_F_QDIR_H2C 0x00000004 -/** Q parameter: queue in c2h direction*/ -#define XNL_F_QDIR_C2H 0x00000008 -/** Q parameter: queue in both directions*/ -#define XNL_F_QDIR_BOTH (XNL_F_QDIR_H2C | XNL_F_QDIR_C2H) -/** Q parameter: queue in prefetch mode*/ -#define XNL_F_PFETCH_EN 0x00000010 -/** Q parameter: enable the bypass for the queue*/ -#define XNL_F_DESC_BYPASS_EN 0x00000020 -/** Q parameter: fetch credits*/ -#define XNL_F_FETCH_CREDIT 0x00000040 -/** Q parameter: enable writeback accumulation*/ -#define XNL_F_CMPL_STATUS_ACC_EN 0x00000080 -/** Q parameter: enable writeback*/ -#define XNL_F_CMPL_STATUS_EN 0x00000100 -/** Q parameter: enable writeback pending check*/ -#define XNL_F_CMPL_STATUS_PEND_CHK 0x00000200 -/** Q parameter: enable writeback status descriptor*/ -#define XNL_F_CMPL_STATUS_DESC_EN 0x00000400 -/** Q parameter: enable queue completion interrupt*/ -#define XNL_F_C2H_CMPL_INTR_EN 0x00000800 -/** Q parameter: enable user defined data*/ -#define XNL_F_CMPL_UDD_EN 0x00001000 -/** Q parameter: enable the pfetch bypass for the queue */ -#define XNL_F_PFETCH_BYPASS_EN 0x00002000 -/** Q parameter: disable CMPT overflow check */ -#define XNL_F_CMPT_OVF_CHK_DIS 0x00004000 -/** Q parameter: Completion Queue? */ -#define XNL_F_Q_CMPL 0x00008000 - -/** maximum number of queue flags to control queue configuration*/ -#define MAX_QFLAGS 17 - -/** maximum number of interrupt ring entries*/ -#define QDMA_MAX_INT_RING_ENTRIES 512 - -/** - * xnl_attr_t netlink attributes for qdma(variables): - * the index in this enum is used as a reference for the type, - * userspace application has to indicate the corresponding type - * the policy is used for security considerations - */ -enum xnl_attr_t { - XNL_ATTR_GENMSG, /**< generatl message */ - XNL_ATTR_DRV_INFO, /**< device info */ - - XNL_ATTR_DEV_IDX, /**< device index */ - XNL_ATTR_PCI_BUS, /**< pci bus number */ - XNL_ATTR_PCI_DEV, /**< pci device number */ - XNL_ATTR_PCI_FUNC, /**< pci function id */ - - XNL_ATTR_DEV_STAT_MMH2C_PKTS1, /**< number of MM H2C packets */ - XNL_ATTR_DEV_STAT_MMH2C_PKTS2, /**< number of MM H2C packets */ - XNL_ATTR_DEV_STAT_MMC2H_PKTS1, /**< number of MM C2H packets */ - XNL_ATTR_DEV_STAT_MMC2H_PKTS2, /**< number of MM C2H packets */ - XNL_ATTR_DEV_STAT_STH2C_PKTS1, /**< number of ST H2C packets */ - XNL_ATTR_DEV_STAT_STH2C_PKTS2, /**< number of ST H2C packets */ - XNL_ATTR_DEV_STAT_STC2H_PKTS1, /**< number of ST C2H packets */ - XNL_ATTR_DEV_STAT_STC2H_PKTS2, /**< number of ST C2H packets */ - - XNL_ATTR_DEV_CFG_BAR, /**< device config bar number */ - XNL_ATTR_DEV_USR_BAR, /**< device AXI Master Lite(user bar) number */ - XNL_ATTR_DEV_QSET_MAX, /**< max queue sets */ - XNL_ATTR_DEV_QSET_QBASE, /**< queue base start */ - - XNL_ATTR_VERSION_INFO, /**< version info */ - XNL_ATTR_DEVICE_TYPE, /**< device type */ - XNL_ATTR_IP_TYPE, /**< ip type */ - XNL_ATTR_DEV_NUMQS, /**< num of queues */ - XNL_ATTR_DEV_NUM_PFS, /**< num of PFs */ - XNL_ATTR_DEV_MM_CHANNEL_MAX, /**< mm channels */ - XNL_ATTR_DEV_MAILBOX_ENABLE, /**< mailbox enable */ - XNL_ATTR_DEV_FLR_PRESENT, /**< flr present */ - XNL_ATTR_DEV_ST_ENABLE, /**< device st capability */ - XNL_ATTR_DEV_MM_ENABLE, /**< device mm capability */ - XNL_ATTR_DEV_MM_CMPT_ENABLE, /**< device mm cmpt capability */ - - XNL_ATTR_REG_BAR_NUM, /**< register bar number */ - XNL_ATTR_REG_ADDR, /**< register address */ - XNL_ATTR_REG_VAL, /**< register value */ - - XNL_ATTR_CSR_INDEX, /**< csr index */ - XNL_ATTR_CSR_COUNT, /**< csr count */ - - XNL_ATTR_QIDX, /**< queue index */ - XNL_ATTR_NUM_Q, /**< number of queues */ - XNL_ATTR_QFLAG, /**< queue config flags */ - - XNL_ATTR_CMPT_DESC_SIZE, /**< completion descriptor size */ - XNL_ATTR_SW_DESC_SIZE, /**< software descriptor size */ - XNL_ATTR_QRNGSZ_IDX, /**< queue ring index */ - XNL_ATTR_C2H_BUFSZ_IDX, /**< c2h buffer idex */ - XNL_ATTR_CMPT_TIMER_IDX, /**< completion timer index */ - XNL_ATTR_CMPT_CNTR_IDX, /**< completion counter index */ - XNL_ATTR_CMPT_TRIG_MODE, /**< completion trigger mode */ - XNL_ATTR_MM_CHANNEL, /**< mm channel */ - XNL_ATTR_CMPT_ENTRIES_CNT, /**< completion entries count */ - - XNL_ATTR_RANGE_START, /**< range start */ - XNL_ATTR_RANGE_END, /**< range end */ - - XNL_ATTR_INTR_VECTOR_IDX, /**< interrupt vector index */ - XNL_ATTR_INTR_VECTOR_START_IDX, /**< interrupt vector start index */ - XNL_ATTR_INTR_VECTOR_END_IDX, /**< interrupt vector end index */ - XNL_ATTR_RSP_BUF_LEN, /**< response buffer length */ - XNL_ATTR_GLOBAL_CSR, /**< global csr data */ - XNL_ATTR_PIPE_GL_MAX, /**< max no. of gl for pipe */ - XNL_ATTR_PIPE_FLOW_ID, /**< pipe flow id */ - XNL_ATTR_PIPE_SLR_ID, /**< pipe slr id */ - XNL_ATTR_PIPE_TDEST, /**< pipe tdest */ - XNL_ATTR_DEV_STM_BAR, /**< device STM bar number */ - XNL_ATTR_Q_STATE, - XNL_ATTR_ERROR, - XNL_ATTR_PING_PONG_EN, - XNL_ATTR_APERTURE_SZ, - XNL_ATTR_DEV_STAT_PING_PONG_LATMIN1, - XNL_ATTR_DEV_STAT_PING_PONG_LATMIN2, - XNL_ATTR_DEV_STAT_PING_PONG_LATMAX1, - XNL_ATTR_DEV_STAT_PING_PONG_LATMAX2, - XNL_ATTR_DEV_STAT_PING_PONG_LATAVG1, - XNL_ATTR_DEV_STAT_PING_PONG_LATAVG2, - XNL_ATTR_DEV, - XNL_ATTR_DEBUG_EN, /** Debug Regs Capability*/ - XNL_ATTR_DESC_ENGINE_MODE, /** Descriptor Engine Capability */ -#ifdef ERR_DEBUG - XNL_ATTR_QPARAM_ERR_INFO, /**< queue param info */ -#endif - XNL_ATTR_NUM_REGS, /**< number of regs */ - XNL_ATTR_MAX, -}; - -/** - * xnl_st_c2h_cmpt_desc_size - * c2h writeback descriptor sizes - */ -enum xnl_st_c2h_cmpt_desc_size { - XNL_ST_C2H_CMPT_DESC_SIZE_8B, /**< 8B descriptor */ - XNL_ST_C2H_CMPT_DESC_SIZE_16B, /**< 16B descriptor */ - XNL_ST_C2H_CMPT_DESC_SIZE_32B, /**< 32B descriptor */ - XNL_ST_C2H_CMPT_DESC_SIZE_64B, /**< 64B descriptor */ - XNL_ST_C2H_NUM_CMPT_DESC_SIZES /**< Num of desc sizes */ -}; - -enum xnl_qdma_rngsz_idx { - XNL_QDMA_RNGSZ_2048_IDX, - XNL_QDMA_RNGSZ_64_IDX, - XNL_QDMA_RNGSZ_128_IDX, - XNL_QDMA_RNGSZ_192_IDX, - XNL_QDMA_RNGSZ_256_IDX, - XNL_QDMA_RNGSZ_384_IDX, - XNL_QDMA_RNGSZ_512_IDX, - XNL_QDMA_RNGSZ_768_IDX, - XNL_QDMA_RNGSZ_1024_IDX, - XNL_QDMA_RNGSZ_1536_IDX, - XNL_QDMA_RNGSZ_3072_IDX, - XNL_QDMA_RNGSZ_4096_IDX, - XNL_QDMA_RNGSZ_6144_IDX, - XNL_QDMA_RNGSZ_8192_IDX, - XNL_QDMA_RNGSZ_12288_IDX, - XNL_QDMA_RNGSZ_16384_IDX, - XNL_QDMA_RNGSZ_IDXS -}; - - -static const char *xnl_attr_str[XNL_ATTR_MAX + 1] = { - "GENMSG", /**< XNL_ATTR_GENMSG */ - "DRV_INFO", /**< XNL_ATTR_DRV_INFO */ - "DEV_IDX", /**< XNL_ATTR_DEV_IDX */ - "DEV_PCIBUS", /**< XNL_ATTR_PCI_BUS */ - "DEV_PCIDEV", /**< XNL_ATTR_PCI_DEV */ - "DEV_PCIFUNC", /**< XNL_ATTR_PCI_FUNC */ - "DEV_STAT_MMH2C_PKTS1", /**< number of MM H2C packkts */ - "DEV_STAT_MMH2C_PKTS2", /**< number of MM H2C packkts */ - "DEV_STAT_MMC2H_PKTS1", /**< number of MM C2H packkts */ - "DEV_STAT_MMC2H_PKTS2", /**< number of MM C2H packkts */ - "DEV_STAT_STH2C_PKTS1", /**< number of ST H2C packkts */ - "DEV_STAT_STH2C_PKTS2", /**< number of ST H2C packkts */ - "DEV_STAT_STC2H_PKTS1", /**< number of ST C2H packkts */ - "DEV_STAT_STC2H_PKTS2", /**< number of ST C2H packkts */ - "DEV_CFG_BAR", /**< XNL_ATTR_DEV_CFG_BAR */ - "DEV_USR_BAR", /**< XNL_ATTR_DEV_USER_BAR */ - "DEV_QSETMAX", /**< XNL_ATTR_DEV_QSET_MAX */ - "DEV_QBASE", /**< XNL_ATTR_DEV_QSET_QBASE */ - "VERSION_INFO", /**< XNL_ATTR_VERSION_INFO */ - "DEVICE_TYPE", /**< XNL_ATTR_DEVICE_TYPE */ - "IP_TYPE", /**< XNL_ATTR_IP_TYPE */ - "DEV_NUMQS", /**/qdma/ - - Run "make install-apps" to install the applications in "/user/local/sbin" - - Example application software to issue DMA requests: - dma-to-device for H2C queues and dma-from-device for C2H queues will be installed in /user/local/sbin. - - - 1.3 Loading the Kernel module: - -------------------------------- - - Kernel module cane be loaded in following different modes - 0 - Auto Mode, driver decides to process the request in poll or interrupt mode - 1 - Poll Mode - 2 - Direct Interrupt Mode - 3 - Interrupt Aggregation Mode or Indirect Interrupt Mode - 4 - Legacy Interrupt Mode - - Find the QDMA device bus number from lspci. Ex : 01:00.0 is the BDF of the device. - By default, all the functions are loaded in Auto Mode. - - In order to pass the module parameters while loading a driver, a config file "qdma.conf" needs to be placed in /etc/modprobe.d directory. Format of the qdma.conf is as below - - ------------------------------------------------------------------------------------------------------------------ - options mode=::,::,::,..... - options config_bar=::,::,::,..... - options master_pf=:,: - ------------------------------------------------------------------------------------------------------------------ - - - module_name: Name of the mode. For PF: qdma-pf and for VF: qdma-vf - - bus_num : Bus number of the PCIe endpoint card - - func_num : Function number of the corressponding bus_num - - mode: Mode in which the driver needs to be loaded - - config_bar: Config bar number - - master_pf: Master PF - - num_threads: number of threads for monitoring the writeback of completions - - Sample qdma.conf can be found below: - - ------------------------------------------------------------------------------------------------------------------ - options qdma-pf mode=0x06:0:2,0x06:1:3,0x06:2:0,0x07:2:1 - options qdma-vf mode=0x06:0:2,0x06:1:3 - ------------------------------------------------------------------------------------------------------------------ - - An auxillary script, qdma_generate_conf_file.sh has been added to the scripts folder which helps create the qdma.conf - config file and copies it to the /etc/modprobe.d location. The script can be used as shown below - - ./scripts/qdma_generate_conf_file.sh - - For loading the driver, execute the following command: - PF Driver: - modprobe qdma-pf - VF Driver: - modprobe qdma-vf - - Now the QDMA software is ready for use. - - Please note that having the qdma-pf.ko and qdma-vf.ko files in the /lib/modules//qdma/ will cause - automatic loading of the driver modules at boot time. To avoid this, it is recommended to have the drivers - blacklisted. - This can be done by adding the below 2 lines in the /etc/modprobe.d/blacklist.conf file - - blacklist qdma-pf - blacklist qdma-vf - - -2. Configuration - - 2.1 Configuring Queues - ------------------------------------- - - To configure a QDMA queue, there are three minimum required parameters - (in the form of key value pairs) needed to be configured. - - idx : The 0-based queue index on the function. - mode : queue mode, default to "mm" - dir : queue direction, default to "h2c" - - - "idx" is a 0-based unique index on the function. - *QDMA3.1, the range can be - 0 ~ 2047 on a physical function and - 0 ~ 2047 on a virtual function - - *QDMA4.0, the range can be - 0 ~ 2047 on a physical function and - 0 ~ 256 on a virtual function - - - "mode" is the operation mode of the queue. - It is either memory mapped (mm) or streaming mode (st) - - - "dir" is the direction of the queue. - It is either host to card (h2c) or card to host (c2h). - - A h2c queue and a c2h queue can share the same index. In other word, a index - represents a pair of queues: one on h2c direction and the other on the c2h - direction. - - -3. Xilinx "dma-ctl" Command-line Configuration Utility: - - The Xilinx QDMA control tool, dma-ctl, is a Command Line utility - which is installed in /usr/local/sbin/ and allows administration of the - Xilinx QDMA queues. It can perform the following functions: - - - query the qdma functions/devices the driver has bind into. - - - list all of the queues on a device/function - - add/configure a new queues on a device/function - - start an already added/configured queue (i.e., bring the queue online) - - stop an started queue (i.e., bring the queue offline) - - delete an already added/configured queue - - register access: - - read a register - - write a register - - dump the qdma config bar and user bar registers - - debug helper - - display a queue's configuration parameters - - display a queue's descriptor ring entries - - display a ch2 queue's completion ring entries - - display the interrupt ring entries in indirect interrupt mode - - Apart from the above basic commands, there are various other commands - available in dma-ctl to add/start/stop/del list of queues at the same time - - For help run: - dma-ctl -h - (or) - man dma-ctl - - - 3.1 Using dma-ctl for query the QDMA devices/functions - ------------------------------------- - - Please refer dma-ctl man page to find all options and parameters - available. - - 1. Get the list of devices the driver has bind with - - [root@]# dma-ctl dev list - - qdma06000 0000:06:00.0 max QP: 32 - qdma06001 0000:06:00.1 max QP: 32 - - The above example output shows 2 QDMA functions/devices. - one is at pci BDF: 06:00.0 - the other is at pci BDF: 06:00.1 - - - 3.2 Using dma-ctl for Queue control - ------------------------------------- - - Please refer dma-ctl man page to find all options and parameters available. - - a. Add/Configure a queue - - To add a MM H2C queue on qdma06000 in the above example: - - [root@]# dma-ctl qdma06000 q add idx 0 mode mm dir h2c - - *A character device /dev/qdma06000-MM-0 would be created. - - To add a MM C2H queue on qdma06000: - - [root@]# dma-ctl qdma06000 q add idx 0 mode mm dir c2h - - *A character device /dev/qdma06000-MM-0 would be created. - - b. Start an added queue - - To start the MM H2C queue on qdma06000 added in the previous example: - - [root@]# dma-ctl qdma06000 q start idx 0 dir h2c - - *After the queue is started the normal read and write operation can be - performed on the character device /dev/qdma06000-MM-0. - - To start the MM C2H queue on qdma06000 added in the previous example: - - [root@]# dma-ctl qdma06000 q start idx 0 dir c2h - - *After the queue is started the normal read and write operation can be - performed on the character device /dev/qdma06000-MM-0. - - c. Stop a queue - - [root@]# dma-ctl qdma06000 q stop idx 0 dir h2c - [root@]# dma-ctl qdma06000 q stop idx 0 dir c2h - - - d. Delete a queue - - [root@]# dma-ctl qdma06000 q del idx 0 dir h2c - [root@]# dma-ctl qdma06000 q del idx 0 dir c2h - - -4. QDMA test script - - Test scripts are in scripts/ directory - - To use the scripts in this directory, "make" and "make install" must be run - install the dma-from-device and dma-to-device applications. - - qdma_run_test.sh - The script does the following dma operations: - - PF AXI-MM : H2C/C2H AXI-MM transfer and check for data correctness. - PF AXI-ST-H2C : H2C AXI-ST transfer and read data register on user side - to check if the data if correct. - PF AXI-ST-C2H : C2H AXI-St transfer and check data for correctness. - - All the above transfers are done for 4 [0 to 3] Queues. - - qdma_run_test_mm_vf.sh - VF AXI-MM : Script runs H2C/C2H AXI-MM transfer and check for data - correctness. - - All the above transfers are done for 4 [0 to 3] Queues. - - qdma_run_test_st_vf.sh - VF AXI-ST-H2C : H2C AXI-ST transfer and read data register on user side - to check if the data if correct. - VF AXI-ST-C2H : C2H AXI-St transfer and check data for correctness. - - All the above transfers are done for 4 [0 to 3] Queues. - - - - - - - /* - * This file is part of the Xilinx DMA IP Core driver for Linux - * - * Copyright (c) 2017-2022, Xilinx, Inc. All rights reserved. - * Copyright (c) 2022, Advanced Micro Devices, Inc. All rights reserved. - * - * This source code is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * The full GNU General Public License is included in this distribution in - * the file called "COPYING". - */ - - - - diff --git a/QDMA/linux-kernel/docs/dma-ctl.8.gz b/QDMA/linux-kernel/docs/dma-ctl.8.gz deleted file mode 100755 index afbdec93ccc2ecc2688830be6dd5b0a5b9bf2f60..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 2403 zcmV-p37qyHiwFo+RX=3_17vMsEn{?SE;s<~T3K)7MiPGKuV~DRlE9{qB*4P!81alf z7yh@nGQl z!N~(PB`H^8AJD=&-_P;b zi4o7((9PLEK%a|PCf415r-T@KF<25;Z(#=325QQ0c{TB$Y&uhYbC5L?{Y;NzcL586#4Fl;AcK&@sV3MM| z90jjr4}xj_GahouS6f8nwHRmo5kd#O;Cj$4c}?OiNP!p_f?CVJGJ&e*HJuevstg5q z>h59#H>2Jwa?pb>hB2>O;`2fA$S@n55=EYdF1VxY@8nY;NZrhhI0;+E=8gFZ+CjShH{{{(|Z9(Mrc2jqN^A2Ul7H|PWuKbH4Q1&~8!7&!V*eoF;!ZYwhOfZ~_ zu?1-L-)=>je(jK_Rd#xc<2J`^Q!zp)l~|81?i! zqutP*Kf5?79hD`ZQ;#EiQd0JQV0X!ULFfiK!8)3$!+zM)a6GqKhEXHFP;yat;n&R0 zOeWh6DpW!a6aF(G?3Nv00@7|_Vc<+yl=xhI%;hACPM9-!C>wo|skY&vH-VC1G7u9l zN~NMgAKc0ZrEPva47esmJ`da?l<000nVJ9^QBkc8)HOl#3XgRnsACoGns?&i;|bKgPL%Q4XiCqWEk9#g^E2hArGT8Dk1#5VeMWUU9&plz9n zDpHuB5@^A=I_&@M*cylT*}?vL@jci#=@w*3q$9n*BF^>-Z%LnuR8K;oA7PzI##By2 z1Psjuj}llzMQ)nHbTLJT(NJWclAPk>!8BhZK!+5;2WX%G0%46{AWBVxL=I7+Dh3Xl zWvq4#VYHoLh1O%1iOamTnaR^_3^0@fCj06G%tS%Eo(ss4TK%*9h&UBzlIyROGyQbVw;NHRK zGDGOC%%}1VlW#}Iq|tZ!Ypv6CS&*0I67KIMargqONwsA&RjO>SNJ-MNMp4_nrbKCM z`);d9NmA$aMT)aaoEyv(z+@&0HjQBgVW8N2oq>$M~W! zQiny&d_v;#oX|zDOb|{jB*+`0KV^6$mD`$S;{%bY6W$H{P~4Rx?6Yx2wWtlI&gV{3!VbB#z(#RVu=N6ln@3m7;qy?p%w2D zR$OM@I;tPXgNrpy>!DCPp)9CexWoeG_~3+o;*-X}r)}(9E-pDVGjJ&W#w>~X_YF$l zpwt$Wwuz-X01c1W`y`Qn0fye=0j9o=b{^CHt?JIlc*x_1Jy`#kv75SRjXqNHbr*1@ VqB enable immediate data in writeback desc. -# - disable_st_c2h_completion=<0|1> disable completion -# - CROSS_COMPILE=, gcc compiler prefix for architecture eg. aarch64-linux-gnu- - -# Define grep error output to NULL, since -s is not portable. -grep = grep 2>/dev/null - -# ALL subdirectories -ALLSUBDIRS := src -DRIVER_SRC_DIR := src - -# subdirectories to be build -SUBDIRS := $(ALLSUBDIRS) - -# Honor the -s (silent) make option. -verbose := $(if $(filter s,$(MAKEFLAGS)),,-v) - -# Define paths. -srcdir := $(shell pwd) -topdir := $(shell cd $(srcdir)/.. && pwd) -bin_dir := $(topdir)/bin - -kernel_check = 1 -distro_check = 1 - -ifeq ($(filter clean,$(MAKECMDGOALS)),clean) - kernel_check = 0 - distro_check = 0 -endif - -ifeq ($(filter uninstall,$(MAKECMDGOALS)),uninstall) - distro_check = 0 -endif - -ifeq ($(kernel_check),1) - include make_rules/kernel_check.mk - - ifeq ($(distro_check),1) - include make_rules/distro_check.mk - endif -endif - -ifneq ($(wildcard $(KINC)/linux/kconfig.h),) - FLAGS += -DKERNEL_HAS_KCONFIG_H -endif -ifneq ($(wildcard $(KINC)/linux/export.h),) - FLAGS += -DKERNEL_HAS_EXPORT_H -endif - -# Debug flags. -ifeq ($(DEBUG),1) - FLAGS += -g -DDEBUG -endif - -# Debugfs flags -ifneq ($(DEBUGFS),0) - FLAGS += -DDEBUGFS -endif - -# LOOPBACK flags. -ifeq ($(LOOPBACK),1) - FLAGS += -DLOOPBACK_TEST -endif - -ifeq ($(DEBUG_THREADS),1) - FLAGS += -DDEBUG -DDEBUG_THREADS -endif - -ifeq ($(enable_cmpt_immediate_data),1) - FLAGS += -DXNL_IMM_DATA_EN -endif - -ifeq ($(disable_st_c2h_completion),1) - FLAGS += -DXMP_DISABLE_ST_C2H_CMPL -endif - -# 64B Descriptor Bypass flags. -ifeq ($(TEST_64B_DESC_BYPASS),1) - FLAGS += -DTEST_64B_DESC_BYPASS_FEATURE -endif - -ifeq ($(ERR_DEBUG),1) - EXTRA_FLAGS += -DERR_DEBUG -# FLAGS += -DERR_DEBUG - export EXTRA_FLAGS -endif - -ifeq ($(TANDEM_BOOT_SUPPORTED),1) - EXTRA_FLAGS += -DTANDEM_BOOT_SUPPORTED - export EXTRA_FLAGS -endif - -ifeq ($(EQDMA_CPM5_VF_GT_256Q_SUPPORTED),1) - EXTRA_FLAGS += -DEQDMA_CPM5_VF_GT_256Q_SUPPORTED - export EXTRA_FLAGS -endif - -ifeq ($(EQDMA_CPM5_10BIT_TAG_ENABLE),1) - EXTRA_FLAGS += -DEQDMA_CPM5_10BIT_TAG_ENABLE - export EXTRA_FLAGS -endif - -# Don't allow ARCH to overwrite the modified variable when passed to -# the sub-makes. -MAKEOVERRIDES := $(filter-out ARCH=%,$(MAKEOVERRIDES)) -# Don't allow CFLAGS/EXTRA_CFLAGS to clobber definitions in sub-make. -MAKEOVERRIDES := $(filter-out CFLAGS=%,$(MAKEOVERRIDES)) -MAKEOVERRIDES := $(filter-out EXTRA_CFLAGS=%,$(MAKEOVERRIDES)) - -# Exports. -export grep -export srcdir -export topdir -export bin_dir -export KERNELRELEASE -export KSRC -export KOBJ -export KINC -# arm64 specific fix to include /arch/ folder properly. -# This hack is motivated by the RHEL7.X/CentOS7.X release where the -# uname Architecture is indicated as "aarch64" but the real Architecture -# source directory is "arm64" -ifeq ($(ARCH),aarch64) - ifeq ($(wildcard $(KOBJ)/arch/$(ARCH)/Makefile),) - override MAKECMDGOALS = $(MAKECMDGOALS) "ARCH=arm64" - export ARCH - else - export ARCH - endif -else - export ARCH -endif -CFLAGS += -I$(srcdir)/src/libqdma/qdma_access -CFLAGS += -I$(srcdir)/src/libqdma -export FLAGS += $(CFLAGS) -#export FLAGS += $(CFLAGS) $(EXTRA_CFLAGS) $(CPPFLAGS) -export verbose -export utsrelease -export kversions -export kseries -export modulesymfile - -#export enable_xvc - -CROSS_COMPILE_FLAG = $(CROSS_COMPILE) -export CROSS_COMPILE_FLAG -$(info CROSS_COMPILE_FLAG = $(CROSS_COMPILE_FLAG).) -$(info ARCH = $(ARCH).) - -# evaluate install paths -ifeq ($(install_path),) - # defaults - kernel_install_path ?= $(PREFIX)/lib/modules/$(utsrelease)/updates/kernel/drivers/qdma - dev_install_path ?= /usr/local/include/qdma - docs_install_path ?= /usr/share/man/man8 -else # bundled install - kernel_install_path ?= $(install_path)/modules - dev_install_path ?= $(install_path)/include/qdma - docs_install_path ?= $(install_path)/doc -endif - -$(shell rm -f $(srcdir)/src/libqdma; ln -fs $(srcdir)/libqdma $(srcdir)/src;) - -.PHONY: eval.mak - -.PHONY: default -default: mod_pf mod_vf post - -.PHONY: pf -pf: mod_pf - -.PHONY: vf -vf: mod_vf - -.PHONY: mods -mod: mod_pf mod_vf - -.PHONY: mod_pf -mod_pf: - @if [ -n "$(verbose)" ]; then \ - echo "#######################";\ - printf "#### PF %-8s%5s####\n" $(DRIVER_SRC_DIR);\ - echo "#######################";\ - fi; - @srcdir=$(shell pwd)/$(DRIVER_SRC_DIR) $(MAKE) VF=0 -C $(DRIVER_SRC_DIR); - -.PHONY: mod_vf -mod_vf: - @if [ -n "$(verbose)" ]; then \ - echo "#######################";\ - printf "#### VF %-8s%5s####\n" $(DRIVER_SRC_DIR);\ - echo "#######################";\ - fi; - @srcdir=$(shell pwd)/$(DRIVER_SRC_DIR) $(MAKE) VF=1 -C $(DRIVER_SRC_DIR); - -.PHONY: post -post: - @if [ -n "$(post_msg)" ]; then \ - echo -e "\nWARNING:\n $(post_msg)";\ - fi; - -.PHONY: clean -clean: - @for dir in $(ALLSUBDIRS); do \ - echo "#######################";\ - printf "#### %-8s%5s####\n" $$dir;\ - echo "#######################";\ - srcdir=$(shell pwd)/$$dir $(MAKE) -C $$dir clean;\ - done; - @-/bin/rm -f *.symvers eval.mak 2>/dev/null; - @-/bin/rm -rf $(shell pwd)/libqdma/qdma_access/*.o $(shell pwd)/libqdma/qdma_access/.*.o.* $(shell pwd)/libqdma/qdma_access/.*.cmd $(shell pwd)/libqdma/qdma_access/.*.o.cmd - @-/bin/rm -rf $(shell pwd)/src/libqdma - -.PHONY: install-mods -install-mods: - @echo "installing kernel modules to $(kernel_install_path) ..." - @mkdir -p -m 755 $(kernel_install_path) - @install -v -m 644 $(bin_dir)/*.ko $(kernel_install_path) - @depmod -a || true - -.PHONY: uninstall-mods -uninstall-mods: - @echo "Un-installing $(kernel_install_path) ..." - @/bin/rm -rf $(kernel_install_path)/* - @depmod -a - -.PHONY: help -help: - @echo "Build Targets:";\ - echo " install-mods - Installs drivers.";\ - echo " uninstall-mods - Uninstalls drivers.";\ - echo;\ - echo "Build Options:";\ - echo " KOBJ= - Kernel build (object) path.";\ - echo " KSRC= - Kernel source path.";\ - echo " - Note: When using KSRC or KOBJ, both";\ - echo " variables must be specified.";\ - echo " KDIR= - Kernel build and source path. Shortcut";\ - echo " for KOBJ=KSRC=.";\ - echo " kernel_install_path=";\ - echo " - kernel module install path.";\ - diff --git a/QDMA/linux-kernel/driver/include/qdma_nl.h b/QDMA/linux-kernel/driver/include/qdma_nl.h deleted file mode 100755 index e0801c9e7..000000000 --- a/QDMA/linux-kernel/driver/include/qdma_nl.h +++ /dev/null @@ -1,488 +0,0 @@ -/* - * This file is part of the Xilinx DMA IP Core driver for Linux - * - * Copyright (c) 2017-2022, Xilinx, Inc. All rights reserved. - * Copyright (c) 2022-2023, Advanced Micro Devices, Inc. All rights reserved. - * - * This source code is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * The full GNU General Public License is included in this distribution in - * the file called "COPYING". - */ - -#ifndef QDMA_NL_H__ -#define QDMA_NL_H__ -/** - * @file - * @brief This file contains the declarations for qdma netlink interfaces - * - */ -/** physical function name (no more than 15 characters) */ -#define XNL_NAME_PF "xnl_pf" -/** virtual function name */ -#define XNL_NAME_VF "xnl_vf" -/** qdma netlink interface version number */ -#define XNL_VERSION 0x1 - -/** qdma nl interface minimum response buffer length*/ -#define XNL_RESP_BUFLEN_MIN 256 -/** qdma nl interface maximum response buffer length*/ -#define XNL_RESP_BUFLEN_MAX (2048 * 10) -/** qdma nl interface error buffer length*/ -#define XNL_ERR_BUFLEN 64 -/** qdma nl command parameter length*/ -#define XNL_STR_LEN_MAX 20 - -/** Q parameter: value to indicate invalid qid*/ -#define XNL_QIDX_INVALID 0xFFFF -/** Q parameter: streaming mode*/ -#define XNL_F_QMODE_ST 0x00000001 -/** Q parameter: memory management mode*/ -#define XNL_F_QMODE_MM 0x00000002 -/** Q parameter: queue in h2c direction*/ -#define XNL_F_QDIR_H2C 0x00000004 -/** Q parameter: queue in c2h direction*/ -#define XNL_F_QDIR_C2H 0x00000008 -/** Q parameter: queue in both directions*/ -#define XNL_F_QDIR_BOTH (XNL_F_QDIR_H2C | XNL_F_QDIR_C2H) -/** Q parameter: queue in prefetch mode*/ -#define XNL_F_PFETCH_EN 0x00000010 -/** Q parameter: enable the bypass for the queue*/ -#define XNL_F_DESC_BYPASS_EN 0x00000020 -/** Q parameter: fetch credits*/ -#define XNL_F_FETCH_CREDIT 0x00000040 -/** Q parameter: enable writeback accumulation*/ -#define XNL_F_CMPL_STATUS_ACC_EN 0x00000080 -/** Q parameter: enable writeback*/ -#define XNL_F_CMPL_STATUS_EN 0x00000100 -/** Q parameter: enable writeback pending check*/ -#define XNL_F_CMPL_STATUS_PEND_CHK 0x00000200 -/** Q parameter: enable writeback status descriptor*/ -#define XNL_F_CMPL_STATUS_DESC_EN 0x00000400 -/** Q parameter: enable queue completion interrupt*/ -#define XNL_F_C2H_CMPL_INTR_EN 0x00000800 -/** Q parameter: enable user defined data*/ -#define XNL_F_CMPL_UDD_EN 0x00001000 -/** Q parameter: enable the pfetch bypass for the queue */ -#define XNL_F_PFETCH_BYPASS_EN 0x00002000 -/** Q parameter: disable CMPT overflow check */ -#define XNL_F_CMPT_OVF_CHK_DIS 0x00004000 -/** Q parameter: Completion Queue? */ -#define XNL_F_Q_CMPL 0x00008000 - -/** maximum number of queue flags to control queue configuration*/ -#define MAX_QFLAGS 17 - -/** maximum number of interrupt ring entries*/ -#define QDMA_MAX_INT_RING_ENTRIES 512 - -/** - * xnl_attr_t netlink attributes for qdma(variables): - * the index in this enum is used as a reference for the type, - * userspace application has to indicate the corresponding type - * the policy is used for security considerations - */ -enum xnl_attr_t { - XNL_ATTR_GENMSG, /**< generatl message */ - XNL_ATTR_DRV_INFO, /**< device info */ - - XNL_ATTR_DEV_IDX, /**< device index */ - XNL_ATTR_PCI_BUS, /**< pci bus number */ - XNL_ATTR_PCI_DEV, /**< pci device number */ - XNL_ATTR_PCI_FUNC, /**< pci function id */ - - XNL_ATTR_DEV_STAT_MMH2C_PKTS1, /**< number of MM H2C packets */ - XNL_ATTR_DEV_STAT_MMH2C_PKTS2, /**< number of MM H2C packets */ - XNL_ATTR_DEV_STAT_MMC2H_PKTS1, /**< number of MM C2H packets */ - XNL_ATTR_DEV_STAT_MMC2H_PKTS2, /**< number of MM C2H packets */ - XNL_ATTR_DEV_STAT_STH2C_PKTS1, /**< number of ST H2C packets */ - XNL_ATTR_DEV_STAT_STH2C_PKTS2, /**< number of ST H2C packets */ - XNL_ATTR_DEV_STAT_STC2H_PKTS1, /**< number of ST C2H packets */ - XNL_ATTR_DEV_STAT_STC2H_PKTS2, /**< number of ST C2H packets */ - - XNL_ATTR_DEV_CFG_BAR, /**< device config bar number */ - XNL_ATTR_DEV_USR_BAR, /**< device AXI Master Lite(user bar) number */ - XNL_ATTR_DEV_QSET_MAX, /**< max queue sets */ - XNL_ATTR_DEV_QSET_QBASE, /**< queue base start */ - - XNL_ATTR_VERSION_INFO, /**< version info */ - XNL_ATTR_DEVICE_TYPE, /**< device type */ - XNL_ATTR_IP_TYPE, /**< ip type */ - XNL_ATTR_DEV_NUMQS, /**< num of queues */ - XNL_ATTR_DEV_NUM_PFS, /**< num of PFs */ - XNL_ATTR_DEV_MM_CHANNEL_MAX, /**< mm channels */ - XNL_ATTR_DEV_MAILBOX_ENABLE, /**< mailbox enable */ - XNL_ATTR_DEV_FLR_PRESENT, /**< flr present */ - XNL_ATTR_DEV_ST_ENABLE, /**< device st capability */ - XNL_ATTR_DEV_MM_ENABLE, /**< device mm capability */ - XNL_ATTR_DEV_MM_CMPT_ENABLE, /**< device mm cmpt capability */ - - XNL_ATTR_REG_BAR_NUM, /**< register bar number */ - XNL_ATTR_REG_ADDR, /**< register address */ - XNL_ATTR_REG_VAL, /**< register value */ - - XNL_ATTR_CSR_INDEX, /**< csr index */ - XNL_ATTR_CSR_COUNT, /**< csr count */ - - XNL_ATTR_QIDX, /**< queue index */ - XNL_ATTR_NUM_Q, /**< number of queues */ - XNL_ATTR_QFLAG, /**< queue config flags */ - - XNL_ATTR_CMPT_DESC_SIZE, /**< completion descriptor size */ - XNL_ATTR_SW_DESC_SIZE, /**< software descriptor size */ - XNL_ATTR_QRNGSZ_IDX, /**< queue ring index */ - XNL_ATTR_C2H_BUFSZ_IDX, /**< c2h buffer idex */ - XNL_ATTR_CMPT_TIMER_IDX, /**< completion timer index */ - XNL_ATTR_CMPT_CNTR_IDX, /**< completion counter index */ - XNL_ATTR_CMPT_TRIG_MODE, /**< completion trigger mode */ - XNL_ATTR_MM_CHANNEL, /**< mm channel */ - XNL_ATTR_CMPT_ENTRIES_CNT, /**< completion entries count */ - - XNL_ATTR_RANGE_START, /**< range start */ - XNL_ATTR_RANGE_END, /**< range end */ - - XNL_ATTR_INTR_VECTOR_IDX, /**< interrupt vector index */ - XNL_ATTR_INTR_VECTOR_START_IDX, /**< interrupt vector start index */ - XNL_ATTR_INTR_VECTOR_END_IDX, /**< interrupt vector end index */ - XNL_ATTR_RSP_BUF_LEN, /**< response buffer length */ - XNL_ATTR_GLOBAL_CSR, /**< global csr data */ - XNL_ATTR_PIPE_GL_MAX, /**< max no. of gl for pipe */ - XNL_ATTR_PIPE_FLOW_ID, /**< pipe flow id */ - XNL_ATTR_PIPE_SLR_ID, /**< pipe slr id */ - XNL_ATTR_PIPE_TDEST, /**< pipe tdest */ - XNL_ATTR_DEV_STM_BAR, /**< device STM bar number */ - XNL_ATTR_Q_STATE, - XNL_ATTR_ERROR, - XNL_ATTR_PING_PONG_EN, - XNL_ATTR_APERTURE_SZ, - XNL_ATTR_DEV_STAT_PING_PONG_LATMIN1, - XNL_ATTR_DEV_STAT_PING_PONG_LATMIN2, - XNL_ATTR_DEV_STAT_PING_PONG_LATMAX1, - XNL_ATTR_DEV_STAT_PING_PONG_LATMAX2, - XNL_ATTR_DEV_STAT_PING_PONG_LATAVG1, - XNL_ATTR_DEV_STAT_PING_PONG_LATAVG2, - XNL_ATTR_DEV, - XNL_ATTR_DEBUG_EN, /** Debug Regs Capability*/ - XNL_ATTR_DESC_ENGINE_MODE, /** Descriptor Engine Capability */ -#ifdef ERR_DEBUG - XNL_ATTR_QPARAM_ERR_INFO, /**< queue param info */ -#endif - XNL_ATTR_NUM_REGS, /**< number of regs */ - XNL_ATTR_MAX, -}; - -/** - * xnl_st_c2h_cmpt_desc_size - * c2h writeback descriptor sizes - */ -enum xnl_st_c2h_cmpt_desc_size { - XNL_ST_C2H_CMPT_DESC_SIZE_8B, /**< 8B descriptor */ - XNL_ST_C2H_CMPT_DESC_SIZE_16B, /**< 16B descriptor */ - XNL_ST_C2H_CMPT_DESC_SIZE_32B, /**< 32B descriptor */ - XNL_ST_C2H_CMPT_DESC_SIZE_64B, /**< 64B descriptor */ - XNL_ST_C2H_NUM_CMPT_DESC_SIZES /**< Num of desc sizes */ -}; - -enum xnl_qdma_rngsz_idx { - XNL_QDMA_RNGSZ_2048_IDX, - XNL_QDMA_RNGSZ_64_IDX, - XNL_QDMA_RNGSZ_128_IDX, - XNL_QDMA_RNGSZ_192_IDX, - XNL_QDMA_RNGSZ_256_IDX, - XNL_QDMA_RNGSZ_384_IDX, - XNL_QDMA_RNGSZ_512_IDX, - XNL_QDMA_RNGSZ_768_IDX, - XNL_QDMA_RNGSZ_1024_IDX, - XNL_QDMA_RNGSZ_1536_IDX, - XNL_QDMA_RNGSZ_3072_IDX, - XNL_QDMA_RNGSZ_4096_IDX, - XNL_QDMA_RNGSZ_6144_IDX, - XNL_QDMA_RNGSZ_8192_IDX, - XNL_QDMA_RNGSZ_12288_IDX, - XNL_QDMA_RNGSZ_16384_IDX, - XNL_QDMA_RNGSZ_IDXS -}; - - -static const char *xnl_attr_str[XNL_ATTR_MAX + 1] = { - "GENMSG", /**< XNL_ATTR_GENMSG */ - "DRV_INFO", /**< XNL_ATTR_DRV_INFO */ - "DEV_IDX", /**< XNL_ATTR_DEV_IDX */ - "DEV_PCIBUS", /**< XNL_ATTR_PCI_BUS */ - "DEV_PCIDEV", /**< XNL_ATTR_PCI_DEV */ - "DEV_PCIFUNC", /**< XNL_ATTR_PCI_FUNC */ - "DEV_STAT_MMH2C_PKTS1", /**< number of MM H2C packkts */ - "DEV_STAT_MMH2C_PKTS2", /**< number of MM H2C packkts */ - "DEV_STAT_MMC2H_PKTS1", /**< number of MM C2H packkts */ - "DEV_STAT_MMC2H_PKTS2", /**< number of MM C2H packkts */ - "DEV_STAT_STH2C_PKTS1", /**< number of ST H2C packkts */ - "DEV_STAT_STH2C_PKTS2", /**< number of ST H2C packkts */ - "DEV_STAT_STC2H_PKTS1", /**< number of ST C2H packkts */ - "DEV_STAT_STC2H_PKTS2", /**< number of ST C2H packkts */ - "DEV_CFG_BAR", /**< XNL_ATTR_DEV_CFG_BAR */ - "DEV_USR_BAR", /**< XNL_ATTR_DEV_USER_BAR */ - "DEV_QSETMAX", /**< XNL_ATTR_DEV_QSET_MAX */ - "DEV_QBASE", /**< XNL_ATTR_DEV_QSET_QBASE */ - "VERSION_INFO", /**< XNL_ATTR_VERSION_INFO */ - "DEVICE_TYPE", /**< XNL_ATTR_DEVICE_TYPE */ - "IP_TYPE", /**< XNL_ATTR_IP_TYPE */ - "DEV_NUMQS", /**dma_device_index, xdev->func_id, - qsets_max, &qbase); - if (rv < 0) { - pr_err("Failed to update dev entry, err = %d", rv); - return -EINVAL; - } - qdma_device_cleanup(xdev); - - rv = qdma_dev_qinfo_get(xdev->dma_device_index, xdev->func_id, - &qbase, &qsets_max); - if (rv < 0) { - pr_err("Failed to get qinfo, err = %d", rv); - return -EINVAL; - } - xdev->conf.qsets_max = qsets_max; - xdev->conf.qsets_base = qbase; - rv = qdma_device_init(xdev); - if (rv < 0) { - pr_warn("qdma_init failed, err = %d", rv); - qdma_device_cleanup(xdev); - return -EINVAL; - } - - return 0; -} -/*****************************************************************************/ -/** - * qdma_get_qmax() - Handler function to get the qmax configuration value - * - * @param[in] dev_hndl: qdma device handle - * - * @return qmax value on success - * @return < 0 on failure - *****************************************************************************/ -unsigned int qdma_get_qmax(unsigned long dev_hndl) -{ - struct xlnx_dma_dev *xdev = (struct xlnx_dma_dev *)dev_hndl; - - /** - * If xdev is NULL return error as Invalid parameter - */ - if (!xdev) { - pr_err("xdev is invalid"); - return -EINVAL; - } - - /** - * Return the current qsets_max value of the device - */ - return xdev->conf.qsets_max; -} - -/*****************************************************************************/ -/** - * qdma_set_intr_rngsz() - Handler function to set the intr_ring_size value - * - * @param[in] dev_hndl: qdma device handle - * @param[in] intr_rngsz: interrupt aggregation ring size - * - * @return 0 on success - * @return <0 on failure - *****************************************************************************/ -int qdma_set_intr_rngsz(unsigned long dev_hndl, u32 intr_rngsz) -{ - struct xlnx_dma_dev *xdev = (struct xlnx_dma_dev *)dev_hndl; - int rv = -1; - - /** - * If xdev is NULL, return error as Invalid parameter - */ - if (!xdev) { - pr_err("xdev is invalid"); - return -EINVAL; - } - - /** If the input intr_rngsz is same as the - * current xdev->conf.intr_rngsz, - * return, as there is nothing to be changed - */ - if (intr_rngsz == xdev->conf.intr_rngsz) { - pr_err("xdev 0x%p, Current intr_rngsz is same as [%d].Nothing to be done\n", - xdev, intr_rngsz); - return rv; - } - - /** If interrupt aggregation is not enabled, then no need to change the - * interrupt ring size. Retrun error in this case. - */ - if ((xdev->conf.qdma_drv_mode != INDIRECT_INTR_MODE) && - (xdev->conf.qdma_drv_mode != AUTO_MODE)) { - pr_err("xdev 0x%p, interrupt aggregation is disabled\n", xdev); - return rv; - } - - /** If qdma_get_active_queue_count() > 0, - * intr_rngsz is not allowed to change. - */ - if (qdma_get_active_queue_count(xdev->conf.pdev->bus->number)) { - pr_err("xdev 0x%p, FMAP prog done, cannot modify intr ring size [%d]\n", - xdev, - xdev->conf.intr_rngsz); - return rv; - } - - /** intr_rngsz > QDMA_INDIRECT_INTR_RING_SIZE_32KB, - * is invalid. - */ - if (intr_rngsz > QDMA_INDIRECT_INTR_RING_SIZE_32KB) { - pr_err("Invalid intr ring size\n"); - return rv; - } - - /** - * FMAP programming is not done yet, update the intr_rngsz - */ - qdma_device_interrupt_cleanup(xdev); - xdev->conf.intr_rngsz = intr_rngsz; - qdma_device_interrupt_setup(xdev); - - return 0; -} - -/*****************************************************************************/ -/** - * qdma_get_intr_rngsz() - Handler function to get the intr_ring_size value - * - * @param[in] dev_hndl: qdma device handle - * - * - * @return interrupt ring size on success - * @return <0 on failure - *****************************************************************************/ -unsigned int qdma_get_intr_rngsz(unsigned long dev_hndl) -{ - struct xlnx_dma_dev *xdev = (struct xlnx_dma_dev *)dev_hndl; - - /** - * If xdev is NULL return error as Invalid parameter - */ - if (!xdev) { - pr_err("xdev is invalid"); - return -EINVAL; - } - - /** If interrupt aggregation is not enabled, then return 0 - * As the intr_rngsz value is irrelevant in this case - */ - if ((xdev->conf.qdma_drv_mode != INDIRECT_INTR_MODE) && - (xdev->conf.qdma_drv_mode != AUTO_MODE)) { - pr_info("xdev 0x%p, interrupt aggregation is disabled\n", xdev); - return 0; - } - - pr_info("xdev 0x%p, intr ring_size = %d\n", - xdev, - xdev->conf.intr_rngsz); - /** - * Return the current intr_rngsz value of the device - */ - return xdev->conf.intr_rngsz; -} -#ifndef __QDMA_VF__ -#ifdef QDMA_CSR_REG_UPDATE -/*****************************************************************************/ -/** - * qdma_set_buf_sz() - Handler function to set the buf_sz value - * - * @param[in] dev_hndl: qdma device handle - * @param[in] buf_sz: interrupt aggregation ring size - * - * @return 0 on success - * @return <0 on failure - *****************************************************************************/ -int qdma_set_buf_sz(unsigned long dev_hndl, u32 *buf_sz) -{ - struct xlnx_dma_dev *xdev = (struct xlnx_dma_dev *)dev_hndl; - int rv = -1; - - /** - * If xdev is NULL, return error as Invalid parameter - */ - if (!xdev) { - pr_err("xdev is invalid"); - return -EINVAL; - } - - - /** If qdma_get_active_queue_count() > 0, - * buf_sz is not allowed to change. - */ - if (qdma_get_active_queue_count(xdev->conf.pdev->bus->number)) { - pr_err("xdev 0x%p, FMAP prog done, cannot modify buf size\n", - xdev); - return rv; - } - - /** - * Write the given buf sizes to the registers - */ - rv = xdev->hw.qdma_global_csr_conf(xdev, 0, QDMA_GLOBAL_CSR_ARRAY_SZ, - buf_sz, QDMA_CSR_BUF_SZ, QDMA_HW_ACCESS_WRITE); - if (rv < 0) { - pr_err("set global buffer size failed, err = %d", rv); - return xdev->hw.qdma_get_error_code(rv); - } - - qdma_csr_read(xdev, &xdev->csr_info); - - return rv; -} -#endif - -/*****************************************************************************/ -/** - * qdma_get_buf_sz() - Handler function to get the buf_sz value - * - * @param[in] dev_hndl: qdma device handle - * - * - * @return buffer size on success - * @return <0 on failure - *****************************************************************************/ -unsigned int qdma_get_buf_sz(unsigned long dev_hndl, u32 *buf_sz) -{ - struct xlnx_dma_dev *xdev = (struct xlnx_dma_dev *)dev_hndl; - - /** - * If xdev is NULL, return error as Invalid parameter - */ - if (!xdev) { - pr_err("xdev is invalid"); - return -EINVAL; - } - - if (xdev->hw.qdma_global_csr_conf(xdev, 0, QDMA_GLOBAL_CSR_ARRAY_SZ, - buf_sz, QDMA_CSR_BUF_SZ, QDMA_HW_ACCESS_READ)) - return -EINVAL; - - return 0; -} - -#ifdef QDMA_CSR_REG_UPDATE -/*****************************************************************************/ -/** - * qdma_set_glbl_rng_sz() - Handler function to set the buf_sz value - * - * @param[in] dev_hndl: qdma device handle - * @param[in] buf_sz: interrupt aggregation ring size - * - * @return 0 on success - * @return <0 on failure - *****************************************************************************/ -int qdma_set_glbl_rng_sz(unsigned long dev_hndl, u32 *glbl_rng_sz) -{ - struct xlnx_dma_dev *xdev = (struct xlnx_dma_dev *)dev_hndl; - int rv = -1; - - /** - * If xdev is NULL, return error as Invalid parameter - */ - if (!xdev) { - pr_err("xdev is invalid"); - return -EINVAL; - } - - - /** If qdma_get_active_queue_count() > 0, - * glbl_rng_sz is not allowed to change. - */ - if (qdma_get_active_queue_count(xdev->conf.pdev->bus->number)) { - pr_err("xdev 0x%p, FMAP prog done, cannot modify glbl_rng_sz\n", - xdev); - return rv; - } - - /** - * Write the given ring sizes to the registers - */ - rv = xdev->hw.qdma_global_csr_conf(xdev, 0, QDMA_GLOBAL_CSR_ARRAY_SZ, - glbl_rng_sz, QDMA_CSR_RING_SZ, QDMA_HW_ACCESS_WRITE); - if (rv < 0) { - pr_err("Failed to write glbl rng size, err = %d", rv); - return -EINVAL; - } - - rv = qdma_csr_read(xdev, &xdev->csr_info); - if (unlikely(rv < 0)) { - pr_err("Failed to read glbl csr, err = %d", rv); - return rv; - } - - return 0; -} -#endif - -/*****************************************************************************/ -/** - * qdma_get_glbl_rng_sz() - Handler function to get the glbl_rng_sz value - * - * @param[in] dev_hndl: qdma device handle - * - * - * @return glbl_rng_sz size on success - * @return <0 on failure - *****************************************************************************/ -unsigned int qdma_get_glbl_rng_sz(unsigned long dev_hndl, u32 *glbl_rng_sz) -{ - struct xlnx_dma_dev *xdev = (struct xlnx_dma_dev *)dev_hndl; - - /** - * If xdev is NULL, return error as Invalid parameter - */ - if (!xdev) { - pr_err("xdev is invalid"); - return -EINVAL; - } - - if (xdev->hw.qdma_global_csr_conf(xdev, 0, QDMA_GLOBAL_CSR_ARRAY_SZ, - glbl_rng_sz, QDMA_CSR_RING_SZ, QDMA_HW_ACCESS_READ)) - return -EINVAL; - - return 0; -} - -#ifdef QDMA_CSR_REG_UPDATE -/*****************************************************************************/ -/** - * qdma_set_timer_cnt() - Handler function to set the buf_sz value - * - * @param[in] dev_hndl: qdma device handle - * @param[in] tmr_cnt: Array of 16 timer count values - * - * @return 0 on success - * @return <0 on failure - *****************************************************************************/ -int qdma_set_timer_cnt(unsigned long dev_hndl, u32 *tmr_cnt) -{ - struct xlnx_dma_dev *xdev = (struct xlnx_dma_dev *)dev_hndl; - int rv = -1; - - if (!xdev) { - pr_err("xdev is invalid"); - return -EINVAL; - } - - /** If qdma_get_active_queue_count() > 0, - * tmr_cnt is not allowed to change. - */ - if (qdma_get_active_queue_count(xdev->conf.pdev->bus->number)) { - pr_err("xdev 0x%p, FMAP prog done, can not modify timer count\n", - xdev); - return rv; - } - - - rv = xdev->hw.qdma_global_csr_conf(xdev, 0, QDMA_GLOBAL_CSR_ARRAY_SZ, - tmr_cnt, QDMA_CSR_TIMER_CNT, QDMA_HW_ACCESS_WRITE); - if (unlikely(rv < 0)) { - pr_err("global timer set failed, err = %d", rv); - return xdev->hw.qdma_get_error_code(rv); - } - - rv = qdma_csr_read(xdev, &xdev->csr_info); - if (unlikely(rv < 0)) - return rv; - - return 0; -} -#endif - -/*****************************************************************************/ -/** - * qdma_get_timer_cnt() - Handler function to get the timer_cnt value - * - * @param[in] dev_hndl: qdma device handle - * - * - * @return timer_cnt on success - * @return <0 on failure - *****************************************************************************/ -unsigned int qdma_get_timer_cnt(unsigned long dev_hndl, u32 *tmr_cnt) -{ - struct xlnx_dma_dev *xdev = (struct xlnx_dma_dev *)dev_hndl; - int rv = -1; - - /** - * If xdev is NULL, return error as Invalid parameter - */ - if (!xdev) { - pr_err("xdev is invalid"); - return -EINVAL; - } - - rv = xdev->hw.qdma_global_csr_conf(xdev, 0, QDMA_GLOBAL_CSR_ARRAY_SZ, - tmr_cnt, QDMA_CSR_TIMER_CNT, QDMA_HW_ACCESS_READ); - if (unlikely(rv < 0)) { - pr_err("get global timer failed, err = %d", rv); - return xdev->hw.qdma_get_error_code(rv); - } - - return 0; -} - -#ifdef QDMA_CSR_REG_UPDATE -/*****************************************************************************/ -/** - * qdma_set_cnt_thresh() - Handler function to set the counter threshold value - * - * @param[in] dev_hndl: qdma device handle - * @param[in] cnt_th: Array of 16 timer count values - * - * @return QDMA_OPERATION_SUCCESSFUL on success - * @return <0 on failure - *****************************************************************************/ -int qdma_set_cnt_thresh(unsigned long dev_hndl, unsigned int *cnt_th) -{ - struct xlnx_dma_dev *xdev = (struct xlnx_dma_dev *)dev_hndl; - int rv = -1; - - if (!xdev) { - pr_err("xdev is invalid"); - return -EINVAL; - } - - /** If qdma_get_active_queue_count() > 0, - * cnt_th is not allowed to change. - */ - if (qdma_get_active_queue_count(xdev->conf.pdev->bus->number)) { - pr_err("xdev 0x%p, FMAP prog done, can not modify threshold count\n", - xdev); - return rv; - } - - rv = xdev->hw.qdma_global_csr_conf(xdev, 0, - QDMA_GLOBAL_CSR_ARRAY_SZ, cnt_th, - QDMA_CSR_CNT_TH, QDMA_HW_ACCESS_WRITE); - if (unlikely(rv < 0)) { - pr_err("set global counter failed, err = %d", rv); - return xdev->hw.qdma_get_error_code(rv); - } - - rv = qdma_csr_read(xdev, &xdev->csr_info); - if (unlikely(rv < 0)) - return rv; - - return 0; -} -#endif - -/*****************************************************************************/ -/** - * qdma_get_cnt_thresh() - Handler function to get the counter thresh value - * - * @param[in] dev_hndl: qdma device handle - * - * - * @return counter threshold values on success - * @return <0 on failure - *****************************************************************************/ -unsigned int qdma_get_cnt_thresh(unsigned long dev_hndl, u32 *cnt_th) -{ - struct xlnx_dma_dev *xdev = (struct xlnx_dma_dev *)dev_hndl; - int rv = -1; - - /** - * If xdev is NULL, return error as Invalid parameter - */ - if (!xdev) { - pr_err("xdev is invalid"); - return -EINVAL; - } - - rv = xdev->hw.qdma_global_csr_conf(xdev, 0, - QDMA_GLOBAL_CSR_ARRAY_SZ, cnt_th, - QDMA_CSR_CNT_TH, QDMA_HW_ACCESS_READ); - if (unlikely(rv < 0)) { - pr_err("get global counter failed, err = %d", rv); - return xdev->hw.qdma_get_error_code(rv); - } - - return 0; -} - -#ifdef QDMA_CSR_REG_UPDATE -/*****************************************************************************/ -/** - * qdma_set_cmpl_status_acc() - Handler function to set the cmpl_status_acc - * configuration value - * - * @param[in] dev_hndl: qdma device handle - * @param[in] cmpl_status_acc: Writeback Accumulation value - * - * @return QDMA_OPERATION_SUCCESSFUL on success - * @return <0 on failure - *****************************************************************************/ -int qdma_set_cmpl_status_acc(unsigned long dev_hndl, u32 cmpl_status_acc) -{ - struct xlnx_dma_dev *xdev = (struct xlnx_dma_dev *)dev_hndl; - int rv = 0; - - /** - * If xdev is NULL, return error as Invalid parameter - */ - if (!xdev) { - pr_err("xdev is invalid"); - return -EINVAL; - } - - /** If qdma_get_active_queue_count() > 0, - * cmpl_status_acc is not allowed to change. - */ - if (qdma_get_active_queue_count(xdev->conf.pdev->bus->number)) { - pr_err("xdev 0x%p, FMAP prog done, cannot modify cmpt acc\n", - xdev); - return -EINVAL; - } - /** - * Write the given cmpl_status_acc value to the register - */ - rv = xdev->hw.qdma_global_writeback_interval_conf(xdev, cmpl_status_acc, - QDMA_HW_ACCESS_WRITE); - if (unlikely(rv < 0)) { - pr_err("set global writeback intvl failed, err = %d", rv); - return xdev->hw.qdma_get_error_code(rv); - } - - rv = qdma_csr_read(xdev, &xdev->csr_info); - if (unlikely(rv < 0)) - return rv; - - return 0; -} -#endif - -/*****************************************************************************/ -/** - * qdma_get_cmpl_status_acc() - Handler function to get the cmpl_status_acc - * configuration value - * - * @param[in] dev_hndl: qdma device handle - * - * Handler function to get the writeback accumulation value - * - * @return cmpl_status_acc on success - * @return <0 on failure - * - *****************************************************************************/ -unsigned int qdma_get_wb_intvl(unsigned long dev_hndl) -{ - struct xlnx_dma_dev *xdev = (struct xlnx_dma_dev *)dev_hndl; - unsigned int wb_intvl; - int rv = -1; - - /** - * If xdev is NULL, return error as Invalid parameter - */ - if (!xdev) { - pr_err("xdev is invalid"); - return -EINVAL; - } - - /** - * Read the current cmpl_status_acc value from the register and return - */ - rv = xdev->hw.qdma_global_writeback_interval_conf(xdev, &wb_intvl, - QDMA_HW_ACCESS_READ); - if (unlikely(rv < 0)) { - pr_err("read global writeback intvl failed, err = %d", rv); - return xdev->hw.qdma_get_error_code(rv); - } - - return wb_intvl; -} -#endif diff --git a/QDMA/linux-kernel/driver/libqdma/libqdma_config.h b/QDMA/linux-kernel/driver/libqdma/libqdma_config.h deleted file mode 100755 index 99ae26137..000000000 --- a/QDMA/linux-kernel/driver/libqdma/libqdma_config.h +++ /dev/null @@ -1,264 +0,0 @@ -/* - * This file is part of the Xilinx DMA IP Core driver for Linux - * - * Copyright (c) 2017-2022, Xilinx, Inc. All rights reserved. - * Copyright (c) 2022, Advanced Micro Devices, Inc. All rights reserved. - * - * This source code is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * The full GNU General Public License is included in this distribution in - * the file called "COPYING". - */ - -#ifndef __LIBQDMA_CONFIG_H__ -#define __LIBQDMA_CONFIG_H__ -/** - * @file - * @brief This file contains the declarations for qdma configuration apis - * - */ -/***************************************************************************** - * GLOBAL CONSTANTS - *****************************************************************************/ -#include - -/** - * QDMA config bar number - */ -#define QDMA_CONFIG_BAR 0 - -/** - * STM bar - */ -#define STM_BAR 2 - -/** - * Maximum number of QDMA devices in the system - */ -#define MAX_DMA_DEV 32 - -/** - * Shift for bus 'B' in B:D:F - */ -#define PCI_SHIFT_BUS 12 - -/** - * Shift for device 'D' in B:D:F - */ -#define PCI_SHIFT_DEV 4 - -/** - * To shift the Bus number for getting BDF - */ -#define SHIFT_DEC_PCI_BUS 1000 - -/** - * To shift the device number for getting BDF - */ -#define SHIFT_DEC_PCI_DEV 10 - -/** - * Maximum number of MSI-X vector per function - */ -#define QDMA_DEV_MSIX_VEC_MAX 8 - -/** - * ring size is 4KB, i.e 512 entries - */ -#define QDMA_INTR_COAL_RING_SIZE INTR_RING_SZ_4KB - -/***************************************************************************** - * Function Declaration - *****************************************************************************/ - -/*****************************************************************************/ -/** - * qdma_set_qmax() - Handler function to set the qmax configuration value - * - * @param[in] dev_hndl: qdma device handle - * @param[in] qsets_max: qmax configuration value - * @param[in] forced: flag to force qmax change - * - * @return QDMA_OPERATION_SUCCESSFUL on success - * @return <0 on failure - *****************************************************************************/ -int qdma_set_qmax(unsigned long dev_hndl, int qbase, u32 qsets_max); - -/*****************************************************************************/ -/** - * qdma_get_qmax() - Handler function to get the qmax configuration value - * - * @param[in] dev_hndl: qdma device handle - * - * @return qmax value on success - * @return < 0 on failure - *****************************************************************************/ -unsigned int qdma_get_qmax(unsigned long dev_hndl); - -/*****************************************************************************/ -/** - * qdma_set_intr_rngsz() - Handler function to set the intr_ring_size value - * - * @param[in] dev_hndl: qdma device handle - * @param[in] intr_rngsz: interrupt aggregation ring size - * - * @return QDMA_OPERATION_SUCCESSFUL on success - * @return <0 on failure - *****************************************************************************/ -int qdma_set_intr_rngsz(unsigned long dev_hndl, u32 intr_rngsz); - -/*****************************************************************************/ -/** - * qdma_get_intr_rngsz() - Handler function to get the intr_ring_size value - * - * @param[in] dev_hndl: qdma device handle - * - * - * @return interrupt ring size on success - * @return <0 on failure - *****************************************************************************/ -unsigned int qdma_get_intr_rngsz(unsigned long dev_hndl); - -#ifndef __QDMA_VF__ -#ifdef QDMA_CSR_REG_UPDATE -/*****************************************************************************/ -/** - * qdma_set_cmpl_status_acc() - Handler function to set the cmpl_status_acc - * configuration value - * - * @param[in] dev_hndl: qdma device handle - * @param[in] cmpl_status_acc: Writeback Accumulation value - * - * @return QDMA_OPERATION_SUCCESSFUL on success - * @return <0 on failure - *****************************************************************************/ -int qdma_set_cmpl_status_acc(unsigned long dev_hndl, u32 cmpl_status_acc); -#endif - -/*****************************************************************************/ -/** - * qdma_get_cmpl_status_acc() - Handler function to get the cmpl_status_acc - * configuration value - * - * @param[in] dev_hndl: qdma device handle - * - * Handler function to get the writeback accumulation value - * - * @return cmpl_status_acc on success - * @return <0 on failure - *****************************************************************************/ -unsigned int qdma_get_wb_intvl(unsigned long dev_hndl); - -#ifdef QDMA_CSR_REG_UPDATE -/*****************************************************************************/ -/** - * qdma_set_buf_sz() - Handler function to set the buf_sz value - * - * @param[in] dev_hndl: qdma device handle - * @param[in] buf_sz: buf sizes - * - * @return QDMA_OPERATION_SUCCESSFUL on success - * @return <0 on failure - *****************************************************************************/ -int qdma_set_buf_sz(unsigned long dev_hndl, u32 *buf_sz); -#endif - -/*****************************************************************************/ -/** - * qdma_get_buf_sz() - Handler function to get the buf_sz value - * - * @param[in] dev_hndl: qdma device handle - * @param[in] buf_sz: buf sizes - * - * @return buf sizes on success - * @return <0 on failure - *****************************************************************************/ -unsigned int qdma_get_buf_sz(unsigned long dev_hndl, u32 *buf_sz); - -#ifdef QDMA_CSR_REG_UPDATE -/*****************************************************************************/ -/** - * qdma_set_glbl_rng_sz() - Handler function to set the glbl_rng_sz value - * - * @param[in] dev_hndl: qdma device handle - * @param[in] glbl_rng_sz: glbl_rng_sizes - * - * @return QDMA_OPERATION_SUCCESSFUL on success - * @return <0 on failure - *****************************************************************************/ -int qdma_set_glbl_rng_sz(unsigned long dev_hndl, u32 *glbl_rng_sz); -#endif - -/*****************************************************************************/ -/** - * qdma_get_glbl_rng_sz() - Handler function to get the glbl_rng_sz value - * - * @param[in] dev_hndl: qdma device handle - * @param[in] glbl_rng_sz: glbl_rng sizes - * - * @return glbl_rng_sz on success - * @return <0 on failure - *****************************************************************************/ -unsigned int qdma_get_glbl_rng_sz(unsigned long dev_hndl, u32 *glbl_rng_sz); - -#ifdef QDMA_CSR_REG_UPDATE -/*****************************************************************************/ -/** - * qdma_set_timer_cnt() - Handler function to set the buf_sz value - * - * @param[in] dev_hndl: qdma device handle - * @param[in] tmr_cnt: Array of 16 timer count values - * - * @return QDMA_OPERATION_SUCCESSFUL on success - * @return <0 on failure - *****************************************************************************/ -int qdma_set_timer_cnt(unsigned long dev_hndl, u32 *tmr_cnt); -#endif - -/*****************************************************************************/ -/** - * qdma_get_timer_cnt() - Handler function to get the timer_cnt value - * - * @param[in] dev_hndl: qdma device handle - * - * - * @return timer_cnt on success - * @return <0 on failure - *****************************************************************************/ -unsigned int qdma_get_timer_cnt(unsigned long dev_hndl, u32 *tmr_cnt); - -#ifdef QDMA_CSR_REG_UPDATE -/*****************************************************************************/ -/** - * qdma_set_cnt_thresh() - Handler function to set the counter threshold value - * - * @param[in] dev_hndl: qdma device handle - * @param[in] cnt_th: Array of 16 timer count values - * - * @return QDMA_OPERATION_SUCCESSFUL on success - * @return <0 on failure - *****************************************************************************/ -int qdma_set_cnt_thresh(unsigned long dev_hndl, unsigned int *cnt_th); -#endif - -/*****************************************************************************/ -/** - * qdma_get_cnt_thresh() - Handler function to get the counter thresh value - * - * @param[in] dev_hndl: qdma device handle - * - * - * @return counter threshold values on success - * @return <0 on failure - *****************************************************************************/ -unsigned int qdma_get_cnt_thresh(unsigned long dev_hndl, u32 *cnt_th); -#endif - -#endif diff --git a/QDMA/linux-kernel/driver/libqdma/libqdma_export.c b/QDMA/linux-kernel/driver/libqdma/libqdma_export.c deleted file mode 100755 index cf9ae2ce5..000000000 --- a/QDMA/linux-kernel/driver/libqdma/libqdma_export.c +++ /dev/null @@ -1,2818 +0,0 @@ -/* - * This file is part of the Xilinx DMA IP Core driver for Linux - * - * Copyright (c) 2017-2022, Xilinx, Inc. All rights reserved. - * Copyright (c) 2022, Advanced Micro Devices, Inc. All rights reserved. - * - * This source code is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * The full GNU General Public License is included in this distribution in - * the file called "COPYING". - */ - -/** - * @file - * @brief This file contains the definitions for libqdma interfaces - * - */ -#define pr_fmt(fmt) KBUILD_MODNAME ":%s: " fmt, __func__ - -#include "libqdma_export.h" - -#include "qdma_descq.h" -#include "qdma_device.h" -#include "qdma_thread.h" -#include "qdma_regs.h" -#include "qdma_context.h" -#include "qdma_intr.h" -#include "qdma_st_c2h.h" -#include "thread.h" -#include "version.h" -#include "qdma_resource_mgmt.h" -#include "qdma_mbox.h" -#include "qdma_platform.h" - -#ifdef DEBUGFS -#include "qdma_debugfs_queue.h" - -/** debugfs root */ -struct dentry *qdma_debugfs_root; -static bool qdma_debufs_cleanup = true; -#endif - - -#define QDMA_Q_PEND_LIST_COMPLETION_TIMEOUT 1000 /* msec */ - -struct drv_mode_name mode_name_list[] = { - { AUTO_MODE, "auto"}, - { POLL_MODE, "poll"}, - { DIRECT_INTR_MODE, "direct interrupt"}, - { INDIRECT_INTR_MODE, "indirect interrupt"}, - { LEGACY_INTR_MODE, "legacy interrupt"} -}; - - -struct qdma_q_type q_type_list[] = { - {"H2C", Q_H2C}, - {"C2H", Q_C2H}, - {"CMPT", Q_CMPT}, - {"BI", Q_H2C_C2H}, -}; - -/* ********************* static function definitions ************************ */ -#ifdef __QDMA_VF__ -static int qdma_dev_notify_qadd(struct qdma_descq *descq, - enum queue_type_t q_type) -{ - struct mbox_msg *m; - int rv = 0; - struct xlnx_dma_dev *xdev = descq->xdev; - - m = qdma_mbox_msg_alloc(); - if (!m) { - pr_err("Failed to allocate mbox msg"); - return -ENOMEM; - } - - - qdma_mbox_compose_vf_notify_qadd(xdev->func_id, - descq->qidx_hw, (enum qdma_dev_q_type)q_type, m->raw); - - rv = qdma_mbox_msg_send(xdev, m, 1, QDMA_MBOX_MSG_TIMEOUT_MS); - if (rv < 0) { - pr_err("%s, mbox failed for queue add %d.\n", - xdev->conf.name, rv); - goto free_msg; - } - rv = qdma_mbox_vf_response_status(m->raw); - if (rv < 0) { - pr_err("mbox_vf_response_status failed, err = %d", rv); - rv = -EINVAL; - } - -free_msg: - qdma_mbox_msg_free(m); - return rv; -} - -static int qdma_dev_notify_qdel(struct qdma_descq *descq, - enum queue_type_t q_type) -{ - struct mbox_msg *m; - int rv = 0; - struct xlnx_dma_dev *xdev = descq->xdev; - - m = qdma_mbox_msg_alloc(); - if (!m) { - pr_err("Failed to allocate mbox msg"); - return -ENOMEM; - } - - qdma_mbox_compose_vf_notify_qdel(xdev->func_id, descq->qidx_hw, - (enum qdma_dev_q_type)q_type, m->raw); - - rv = qdma_mbox_msg_send(xdev, m, 1, QDMA_MBOX_MSG_TIMEOUT_MS); - if (rv < 0) { - pr_err("%s, mbox failed for queue add %d.\n", - xdev->conf.name, rv); - goto free_msg; - } - rv = qdma_mbox_vf_response_status(m->raw); - if (rv < 0) { - pr_err("mbox_vf_response_status failed, err = %d", rv); - rv = -EINVAL; - } - -free_msg: - qdma_mbox_msg_free(m); - return rv; -} - -static int qdma_dev_get_active_qcnt(struct xlnx_dma_dev *xdev, - u32 *h2c_qs, u32 *c2h_qs, u32 *cmpt_qs) -{ - struct mbox_msg *m; - int rv = 0; - - m = qdma_mbox_msg_alloc(); - if (!m) { - pr_err("Failed to allocate mbox msg"); - return -ENOMEM; - } - - qdma_mbox_compose_vf_get_device_active_qcnt(xdev->func_id, m->raw); - - rv = qdma_mbox_msg_send(xdev, m, 1, QDMA_MBOX_MSG_TIMEOUT_MS); - if (rv < 0) { - pr_err("%s, mbox failed for queue add %d.\n", - xdev->conf.name, rv); - goto free_msg; - } - rv = qdma_mbox_vf_response_status(m->raw); - if (rv < 0) { - pr_err("mbox_vf_response_status failed, err = %d", rv); - rv = -EINVAL; - goto free_msg; - } - - *h2c_qs = (uint32_t)qdma_mbox_vf_active_queues_get(m->raw, - QDMA_DEV_Q_TYPE_H2C); - *c2h_qs = (uint32_t)qdma_mbox_vf_active_queues_get(m->raw, - QDMA_DEV_Q_TYPE_C2H); - *cmpt_qs = (uint32_t)qdma_mbox_vf_active_queues_get(m->raw, - QDMA_DEV_Q_TYPE_CMPT); - - return rv; - -free_msg: - qdma_mbox_msg_free(m); - return rv; -} - -#endif - -static int qdma_validate_qconfig(struct xlnx_dma_dev *xdev, - struct qdma_queue_conf *qconf, - char *buf, int buflen) -{ - - /** If xdev is NULL return error as Invalid parameter */ - if (!xdev || !qconf) { - pr_err("Invalid input received, xdev=%p, qconf =%p", - xdev, qconf); - return -EINVAL; - } - - /** make sure that input buffer is not empty, else return error */ - if (!buf || !buflen) { - pr_err("invalid argument: buf=%p, buflen=%d", buf, buflen); - return -EINVAL; - } - - if (qconf->cmpl_trig_mode > TRIG_MODE_COMBO) { - pr_err("Invalid trigger mode :%d", - qconf->cmpl_trig_mode); - snprintf(buf, buflen, - "qdma%05x : Invalid trigger mode %d passed\n", - xdev->conf.bdf, qconf->cmpl_trig_mode); - return -EINVAL; - } - - if (xdev->version_info.ip_type == QDMA_VERSAL_HARD_IP && - xdev->version_info.device_type == QDMA_DEVICE_VERSAL_CPM4) { - /* 64B desc size is not supported in 2018.2 release */ - if ((qconf->cmpl_desc_sz == CMPT_DESC_SZ_64B) || - (qconf->sw_desc_sz == DESC_SZ_64B)) { - pr_err("Invalid descriptor sw desc :%d, cmpl desc :%d", - qconf->sw_desc_sz, qconf->sw_desc_sz); - snprintf(buf, buflen, - "qdma%05x : 64B desc size is not supported\n", - xdev->conf.bdf); - return -EINVAL; - } - - if (qconf->cmpl_trig_mode == TRIG_MODE_COMBO) { - pr_err("Invalid trigger mode :%d", - qconf->cmpl_trig_mode); - snprintf(buf, buflen, - "qdma%05x : Trigger mode COMBO is not supported\n", - xdev->conf.bdf); - return -EINVAL; - } - } - - return 0; -} - -/*****************************************************************************/ -/** - * qdma_request_wait_for_cmpl() - static function to monitor the - * wait completion - * - * @param[in] xdev: pointer to xlnx_dma_dev structure - * @param[in] descq: pointer to qdma_descq structure - * @param[in] req: qdma request - * - * @return 0: success - * @return <0: error - *****************************************************************************/ -static int qdma_request_wait_for_cmpl(struct xlnx_dma_dev *xdev, - struct qdma_descq *descq, struct qdma_request *req) -{ - struct qdma_sgt_req_cb *cb = qdma_req_cb_get(req); - - /** if timeout is mentioned in the request, - * wait until the timeout occurs or wait until the - * call back is completed - */ - - if (req->timeout_ms) { -#ifdef __XRT__ - qdma_waitq_wait_event_timeout(cb->wq, cb->done && - (descq->pidx == descq->cidx), - msecs_to_jiffies(req->timeout_ms)); -#else - qdma_waitq_wait_event_timeout(cb->wq, cb->done, - msecs_to_jiffies(req->timeout_ms)); -#endif - } else { - qdma_waitq_wait_event(cb->wq, cb->done); - } - - lock_descq(descq); - /** if the call back is not done, request timed out - * delete the request list - */ - if (!cb->done) - list_del(&cb->list); - - /** if the call back is not done but the status is updated - * return i/o error - */ - if (!cb->done || cb->status) { - pr_err("%s: req 0x%p, %c,%u,%u/%u,0x%llx, done %d, err %d, tm %u.\n", - descq->conf.name, - req, req->write ? 'W' : 'R', - cb->offset, - cb->left, - req->count, - req->ep_addr, - cb->done, - cb->status, - req->timeout_ms); - qdma_descq_dump(descq, NULL, 0, 1); - unlock_descq(descq); - - return -EIO; - } - - unlock_descq(descq); - return 0; -} - -/*****************************************************************************/ -/** - * qdma_request_submit_st_c2h() - static function to handle the - * st c2h request - * - * @param[in] xdev: pointer to xlnx_dma_dev structure - * @param[in] descq: pointer to qdma_descq structure - * @param[in] req: qdma request - * - * @return 0: success - * @return <0: error - *****************************************************************************/ -static ssize_t qdma_request_submit_st_c2h(struct xlnx_dma_dev *xdev, - struct qdma_descq *descq, struct qdma_request *req) -{ - struct qdma_dev *qdev; - struct qdma_sgt_req_cb *cb = qdma_req_cb_get(req); - int wait = req->fp_done ? 0 : 1; - int rv = 0; - - /** If xdev is NULL return error as Invalid parameter */ - if (!xdev) { - pr_err("xdev is invalid"); - return -EINVAL; - } - - qdev = xdev_2_qdev(xdev); - /** make sure that qdev is not NULL, else return error */ - if (!qdev) { - pr_err("dev %s, qdev null.\n", - dev_name(&xdev->conf.pdev->dev)); - return -EINVAL; - } - - pr_debug("%s: data len %u, sgl 0x%p, sgl cnt %u, tm %u ms.\n", - descq->conf.name, - req->count, req->sgl, req->sgcnt, req->timeout_ms); - - /** get the request count */ - cb->left = req->count; - - lock_descq(descq); - if (descq->q_stop_wait) { - unlock_descq(descq); - return 0; - } - if ((descq->q_state == Q_STATE_ONLINE) && - !descq->q_stop_wait) { - /* add to pend list even before cidx/pidx update as it could - * cause an interrupt and may miss processing of writeback - */ - list_add_tail(&cb->list, &descq->pend_list); - /* any rcv'ed packet not yet read ? */ - /** read the data from the device */ - descq_st_c2h_read(descq, req, 1, 1); - if (!cb->left) { - list_del(&cb->list); - unlock_descq(descq); - return req->count; - } - descq->pend_list_empty = 0; - unlock_descq(descq); - } else { - unlock_descq(descq); - pr_err("%s descq %s NOT online.\n", - xdev->conf.name, descq->conf.name); - return -EINVAL; - } - - /** if there is a completion thread associated, - * wake up the completion thread to process the - * completion status - */ - if (descq->cmplthp) - qdma_kthread_wakeup(descq->cmplthp); - - if (!wait) { - pr_debug("%s: cb 0x%p, data len 0x%x NO wait.\n", - descq->conf.name, cb, req->count); - return 0; - } - - /** wait for the request completion */ - rv = qdma_request_wait_for_cmpl(xdev, descq, req); - if (rv < 0) { - if (!req->dma_mapped) - sgl_unmap(xdev->conf.pdev, req->sgl, req->sgcnt, - DMA_FROM_DEVICE); - return rv; - } - - /** Once the request completion received, - * return with the number of processed requests - */ - return req->count - cb->left; -} - -/* ********************* public function definitions ************************ */ - -/*****************************************************************************/ -/** - * qdma_queue_get_config() - retrieve the configuration of a queue - * - * @param[in] dev_hndl: dev_hndl retured from qdma_device_open() - * @param[in] id: queue index - * @param[in] buflen: length of the input buffer - * @param[out] buf: message buffer - * @param[out] qconf: pointer to hold the qdma_queue_conf structure. - * - * @return 0: success - * @return <0: error - *****************************************************************************/ -int qdma_queue_get_config(unsigned long dev_hndl, unsigned long id, - struct qdma_queue_conf *qconf, - char *buf, int buflen) -{ - struct xlnx_dma_dev *xdev = (struct xlnx_dma_dev *)dev_hndl; - struct qdma_descq *descq; - - /** make sure that input buffer is not empty, else return error */ - if (!buf || !buflen) { - pr_err("invalid argument: buf=%p, buflen=%d", buf, buflen); - return -EINVAL; - } - - /** make sure that the dev_hndl passed is Valid */ - if (!xdev) { - pr_err("dev_hndl is NULL"); - snprintf(buf, buflen, "dev_hndl is NULL"); - return -EINVAL; - } - - if (xdev_check_hndl(__func__, xdev->conf.pdev, dev_hndl) < 0) { - pr_err("Invalid dev_hndl passed"); - snprintf(buf, buflen, "Invalid dev_hndl passed"); - return -EINVAL; - } - - descq = qdma_device_get_descq_by_id(xdev, id, buf, buflen, 0); - /** make sure that descq is not NULL, else return error */ - if (!descq) { - pr_err("Invalid qid(%lu)", id); - snprintf(buf, buflen, - "Invalid qid(%lu)\n", id); - return -EINVAL; - } - - memcpy(qconf, &descq->conf, sizeof(struct qdma_queue_conf)); - - snprintf(buf, buflen, - "Queue configuration for %s id %u is stored in qconf param", - descq->conf.name, - descq->conf.qidx); - - return 0; -} - -/*****************************************************************************/ -/** - * qdma_device_capabilities_info() - retrieve the capabilities of a device. - * - * @dev_hndl: handle returned from qdma_device_open() - * @dev_attr: pointer to hold all the device attributes - * - * Return: 0 for success and <0 for error - * - *****************************************************************************/ -int qdma_device_capabilities_info(unsigned long dev_hndl, - struct qdma_dev_attributes *dev_attr) -{ - struct xlnx_dma_dev *xdev = (struct xlnx_dma_dev *)dev_hndl; - - if (!xdev) { - pr_err("dev_hndl is NULL"); - return -EINVAL; - } - - if (!dev_attr) { - pr_err("dev_attr is NULL"); - return -EINVAL; - } - - if (xdev_check_hndl(__func__, xdev->conf.pdev, dev_hndl) < 0) { - pr_err("Invalid dev_hndl passed"); - return -EINVAL; - } - - memcpy(dev_attr, &(xdev->dev_cap), sizeof(struct qdma_dev_attributes)); - - return 0; -} - -/*****************************************************************************/ -/** - * qdma_config_reg_info_dump() - dump the detailed field information of register - * - * @param[in] dev_hndl: handle returned from qdma_device_open() - * @param[in] reg_addr: register address info tobe dumped - * @param[in] num_regs: number of registers to be dumped - * @param[in] buf: buffer containing the o/p - * @param[in] buflen: length of the buffer - * - * @return: length of o/p buffer - * - *****************************************************************************/ -int qdma_config_reg_info_dump(unsigned long dev_hndl, uint32_t reg_addr, - uint32_t num_regs, char *buf, int buflen) -{ - struct xlnx_dma_dev *xdev = (struct xlnx_dma_dev *)dev_hndl; - int rv; - - /** make sure that input buffer is not empty, else return error */ - if (!buf || !buflen) { - pr_err("invalid argument: buf=%p, buflen=%d\n", buf, buflen); - return -EINVAL; - } - - /** make sure that the dev_hndl passed is Valid */ - if (!xdev) { - pr_err("dev_hndl is NULL"); - snprintf(buf, buflen, "dev_hndl is NULL"); - return -EINVAL; - } - - if (xdev_check_hndl(__func__, xdev->conf.pdev, dev_hndl) < 0) { - pr_err("Invalid dev_hndl passed"); - snprintf(buf, buflen, "Invalid dev_hndl passed\n"); - return -EINVAL; - } - - if (xdev->hw.qdma_dump_reg_info == NULL) { - pr_err("Err: Feature not supported\n"); - snprintf(buf, buflen, "Err: Feature not supported\n"); - return -EPERM; - } - - rv = xdev->hw.qdma_dump_reg_info((void *)dev_hndl, reg_addr, - num_regs, buf, buflen); - return rv; - -} - -#ifndef __QDMA_VF__ -/*****************************************************************************/ -/** - * qdma_config_reg_dump() - display a config registers in a string buffer - * - * @param[in] dev_hndl: dev_hndl returned from qdma_device_open() - * @param[in] buflen: length of the input buffer - * @param[out] buf: message buffer - * - * @return success: if optional message buffer used then strlen of buf, - * otherwise 0 - * @return <0: error - *****************************************************************************/ - -int qdma_config_reg_dump(unsigned long dev_hndl, char *buf, - int buflen) -{ - - struct xlnx_dma_dev *xdev = (struct xlnx_dma_dev *)dev_hndl; - int rv; - - /** make sure that input buffer is not empty, else return error */ - if (!buf || !buflen) { - pr_err("invalid argument: buf=%p, buflen=%d", buf, buflen); - return -EINVAL; - } - - /** make sure that the dev_hndl passed is Valid */ - if (!xdev) { - pr_err("dev_hndl is NULL"); - snprintf(buf, buflen, "dev_hndl is NULL"); - return -EINVAL; - } - - if (xdev_check_hndl(__func__, xdev->conf.pdev, dev_hndl) < 0) { - pr_err("Invalid dev_hndl passed"); - snprintf(buf, buflen, "Invalid dev_hndl passed"); - return -EINVAL; - } - - rv = xdev->hw.qdma_dump_config_regs((void *)dev_hndl, 0, - buf, buflen); - return rv; - -} - -#else - -static int qdma_config_read_reg_list(struct xlnx_dma_dev *xdev, - uint16_t group_num, - uint16_t *num_regs, struct qdma_reg_data *reg_list) -{ - struct mbox_msg *m = qdma_mbox_msg_alloc(); - int rv; - - if (!m) - return -ENOMEM; - - qdma_mbox_compose_reg_read(xdev->func_id, group_num, m->raw); - - rv = qdma_mbox_msg_send(xdev, m, 1, QDMA_MBOX_MSG_TIMEOUT_MS); - if (rv < 0) { - if (rv != -ENODEV) - pr_err("%s, reg read mbox failed %d.\n", - xdev->conf.name, rv); - goto err_out; - } - - rv = qdma_mbox_vf_reg_list_get(m->raw, num_regs, reg_list); - if (rv < 0) { - pr_err("qdma_mbox_vf_reg_list_get faled with error = %d", rv); - goto err_out; - } - -err_out: - qdma_mbox_msg_free(m); - return rv; -} - -/*****************************************************************************/ -/** - * qdma_config_reg_dump() - display a config registers in a string buffer - * - * @param[in] dev_hndl: dev_hndl returned from qdma_device_open() - * @param[in] buflen: length of the input buffer - * @param[out] buf: message buffer - * - * @return success: if optional message buffer used then strlen of buf, - * otherwise 0 - * @return <0: error - *****************************************************************************/ -int qdma_config_reg_dump(unsigned long dev_hndl, char *buf, int buflen) -{ - - struct xlnx_dma_dev *xdev = (struct xlnx_dma_dev *)dev_hndl; - int rv = 0; - struct qdma_reg_data *reg_list; - uint16_t num_regs = 0, group_num = 0; - int len = 0, rcv_len = 0; - - /** make sure that input buffer is not empty, else return error */ - if (!buf || !buflen) { - pr_err("invalid argument: buf=%p, buflen=%d", buf, buflen); - return -EINVAL; - } - - /** make sure that the dev_hndl passed is Valid */ - if (!xdev) { - pr_err("dev_hndl is NULL"); - snprintf(buf, buflen, "dev_hndl is NULL"); - return -EINVAL; - } - - if (xdev_check_hndl(__func__, xdev->conf.pdev, dev_hndl) < 0) { - pr_err("Invalid dev_hndl passed"); - snprintf(buf, buflen, "Invalid dev_hndl passed"); - return -EINVAL; - } - - reg_list = kzalloc((QDMA_MAX_REGISTER_DUMP * - sizeof(struct qdma_reg_data)), - GFP_KERNEL); - - if (!reg_list) { - pr_err("%s: reg_list OOM", xdev->conf.name); - snprintf(buf, buflen, "reg_list OOM"); - return -ENOMEM; - } - - for (group_num = 0; group_num < QDMA_REG_READ_GROUP_3; group_num++) { - /** Reset the reg_list with 0's */ - memset(reg_list, 0, (QDMA_MAX_REGISTER_DUMP * - sizeof(struct qdma_reg_data))); - rv = qdma_config_read_reg_list(xdev, - group_num, &num_regs, reg_list); - if (rv < 0) { - pr_err("Failed to read config registers, rv = %d", rv); - snprintf(buf, buflen, "Failed to read config regs"); - goto free_reg_list; - } - - rcv_len = xdev->hw.qdma_dump_config_reg_list((void *)dev_hndl, - num_regs, reg_list, buf + len, buflen - len); - if (len < 0) { - pr_err("%s: failed with error = %d", __func__, rv); - snprintf(buf, buflen, "Failed to dump config regs"); - goto free_reg_list; - } - len += rcv_len; - } - -free_reg_list: - kfree(reg_list); - return len; - -} -#endif -/*****************************************************************************/ -/** - * qdma_queue_dump() - display a queue's state in a string buffer - * - * @param[in] dev_hndl: dev_hndl returned from qdma_device_open() - * @param[in] id: queue index - * @param[in] buflen: length of the input buffer - * @param[out] buf: message buffer - * - * @return success: if optional message buffer used then strlen of buf, - * otherwise 0 - * @return <0: error - *****************************************************************************/ -int qdma_queue_dump(unsigned long dev_hndl, unsigned long id, char *buf, - int buflen) -{ - struct xlnx_dma_dev *xdev = (struct xlnx_dma_dev *)dev_hndl; - struct qdma_descq *descq; - int rv = 0; - - /** make sure that input buffer is not empty, else return error */ - if (!buf || !buflen) { - pr_err("invalid argument: buf=%p, buflen=%d", buf, buflen); - return -EINVAL; - } - - /** make sure that the dev_hndl passed is Valid */ - if (!xdev) { - pr_err("dev_hndl is NULL"); - snprintf(buf, buflen, "dev_hndl is NULL"); - return -EINVAL; - } - - if (xdev_check_hndl(__func__, xdev->conf.pdev, dev_hndl) < 0) { - pr_err("Invalid dev_hndl passed"); - snprintf(buf, buflen, "Invalid dev_hndl passed"); - return -EINVAL; - } - - descq = qdma_device_get_descq_by_id(xdev, id, buf, buflen, 0); - /** make sure that descq is not NULL, else return error */ - if (!descq) { - pr_err("Invalid qid(%lu)", id); - snprintf(buf, buflen, - "Invalid qid(%lu)\n", id); - return -EINVAL; - } - - /** read the descq context for the given qid */ - rv = qdma_descq_context_dump(descq, buf, buflen); - if (rv < 0) { - snprintf(buf, buflen, - "%s dump context failed %d.\n", - descq->conf.name, rv); - return rv; - } - - return buflen; -} - -/*****************************************************************************/ -/** - * qdma_queue_dump_desc() - display a queue's descriptor ring from index start - * ~ end in a string buffer - * - * @param[in] dev_hndl: dev_hndl returned from qdma_device_open() - * @param[in] id: queue index - * @param[in] start: start index - * @param[in] end: end index - * @param[in] buflen: length of the input buffer - * @param[out] buf: message buffer - * - * @return success: if optional message buffer used then strlen of buf, - * otherwise 0 - * @return <0: error - *****************************************************************************/ -int qdma_queue_dump_desc(unsigned long dev_hndl, unsigned long id, - unsigned int start, unsigned int end, char *buf, - int buflen) -{ - struct xlnx_dma_dev *xdev = (struct xlnx_dma_dev *)dev_hndl; - struct qdma_descq *descq; - int len = 0; - - /** make sure that input buffer is not empty, else return error */ - if (!buf || !buflen) { - pr_err("invalid argument: buf=%p, buflen=%d", buf, buflen); - return -EINVAL; - } - - /** make sure that the dev_hndl passed is Valid */ - if (!xdev) { - pr_err("dev_hndl is NULL"); - snprintf(buf, buflen, "dev_hndl is NULL"); - return -EINVAL; - } - - if (xdev_check_hndl(__func__, xdev->conf.pdev, dev_hndl) < 0) { - pr_err("Invalid dev_hndl passed"); - snprintf(buf, buflen, "Invalid dev_hndl passed"); - return -EINVAL; - } - - /** get the descq details based on the qid provided */ - descq = qdma_device_get_descq_by_id(xdev, id, buf, buflen, 1); - if (!descq) { - pr_err("Invalid qid(%lu)", id); - snprintf(buf, buflen, - "Invalid qid(%lu)\n", id); - return -EINVAL; - } - - /** make sure that intr ring entry indexes - * given are with in the range - */ - if (start > end) { - pr_err("start/end param passed is invalid , shall be less than "); - snprintf(buf, buflen, - "start/end param passed is invalid, shall be less than "); - return -EINVAL; - } - - /** dump the queue state */ - len = qdma_descq_dump_state(descq, buf, buflen); - if (descq->q_state != Q_STATE_ONLINE) - return len; - - /** dump the queue descriptor state */ - len += qdma_descq_dump_desc(descq, start, end, buf + len, buflen - len); - return len; -} - -/*****************************************************************************/ -/** - * qdma_queue_dump_cmpt() - display a queue's descriptor ring from index start - * ~ end in a string buffer - * - * @param[in] dev_hndl: dev_hndl returned from qdma_device_open() - * @param[in] id: queue index - * @param[in] start: start index - * @param[in] end: end index - * @param[in] buflen: length of the input buffer - * @param[out] buf: message buffer - * - * @return success: if optional message buffer used then strlen of buf, - * otherwise 0 - * @return <0: error - *****************************************************************************/ -int qdma_queue_dump_cmpt(unsigned long dev_hndl, unsigned long id, - unsigned int start, unsigned int end, char *buf, - int buflen) -{ - struct xlnx_dma_dev *xdev = (struct xlnx_dma_dev *)dev_hndl; - struct qdma_descq *descq; - int len = 0; - - /** make sure that input buffer is not empty, else return error */ - if (!buf || !buflen) { - pr_err("invalid argument: buf=%p, buflen=%d", buf, buflen); - return -EINVAL; - } - - /** make sure that the dev_hndl passed is Valid */ - if (!xdev) { - pr_err("dev_hndl is NULL"); - snprintf(buf, buflen, "dev_hndl is NULL"); - return -EINVAL; - } - - if (xdev_check_hndl(__func__, xdev->conf.pdev, dev_hndl) < 0) { - pr_err("Invalid dev_hndl passed"); - snprintf(buf, buflen, "Invalid dev_hndl passed"); - return -EINVAL; - } - - /** get the descq details based on the qid provided */ - descq = qdma_device_get_descq_by_id(xdev, id, buf, buflen, 1); - if (!descq) { - pr_err("Invalid qid(%lu)", id); - snprintf(buf, buflen, - "Invalid qid(%lu)\n", id); - return -EINVAL; - } - - /** make sure that intr ring entry indexes - * given are with in the range - */ - if (start > end) { - pr_err("start/end param passed is invalid, shall be less than "); - snprintf(buf, buflen, - "start/end param passed is invalid, shall be less than "); - return -EINVAL; - } - - /** dump the descriptor state */ - len = qdma_descq_dump_state(descq, buf, buflen); - /** if the descriptor is in online state, - * then, dump the completion state - */ - if (descq->q_state == Q_STATE_ONLINE) - len += qdma_descq_dump_cmpt(descq, start, end, buf + len, - buflen - len); - - return len; -} - -/*****************************************************************************/ -/** - * qdma_queue_remove() - remove a queue (i.e., offline, NOT ready for dma) - * - * @param[in] dev_hndl: dev_hndl returned from qdma_device_open() - * @param[in] id: queue index - * @param[in] buflen: length of the input buffer - * @param[out] buf: message buffer - * - * @return 0: success - * @return <0: error - *****************************************************************************/ -int qdma_queue_remove(unsigned long dev_hndl, unsigned long id, char *buf, - int buflen) -{ - struct xlnx_dma_dev *xdev = (struct xlnx_dma_dev *)dev_hndl; - struct qdma_descq *descq; -#ifdef DEBUGFS - struct qdma_descq *pair_descq; -#endif - struct qdma_dev *qdev; - int rv = 0; - - /** make sure that input buffer is not empty, else return error */ - if (!buf || !buflen) { - pr_err("invalid argument: buf=%p, buflen=%d", buf, buflen); - return -EINVAL; - } - - /** make sure that the dev_hndl passed is Valid */ - if (!xdev) { - pr_err("dev_hndl is NULL"); - snprintf(buf, buflen, "dev_hndl is NULL"); - return -EINVAL; - } - - if (xdev_check_hndl(__func__, xdev->conf.pdev, dev_hndl) < 0) { - pr_err("Invalid dev_hndl passed"); - snprintf(buf, buflen, "Invalid dev_hndl passed"); - return -EINVAL; - } - - descq = qdma_device_get_descq_by_id(xdev, id, buf, buflen, 1); -#ifdef DEBUGFS - pair_descq = qdma_device_get_pair_descq_by_id(xdev, id, buf, buflen, 1); -#endif - - qdev = xdev_2_qdev(xdev); - /** make sure that qdev is not NULL, else return error */ - if (!qdev) { - pr_err("dev %s, qdev null.\n", - dev_name(&xdev->conf.pdev->dev)); - return -EINVAL; - } - - /** make sure that descq is not NULL, else return error */ - if (!descq) { - pr_err("Invalid qid(%lu)", id); - snprintf(buf, buflen, - "Invalid qid(%lu)\n", id); - return -EINVAL; - } - - if (descq->q_state != Q_STATE_ENABLED) { - snprintf(buf, buflen, - "queue %s, id %u cannot be deleted. Invalid q state: %s\n", - descq->conf.name, - descq->conf.qidx, - q_state_list[descq->q_state].name); - - pr_err("queue %s, id %u cannot be deleted. Invalid q state: %s", - descq->conf.name, - descq->conf.qidx, - q_state_list[descq->q_state].name); - return -EINVAL; - } - -#ifdef DEBUGFS - if (pair_descq) - /** if pair_descq is not NULL, it means the queue - * is in ENABLED state - */ - dbgfs_queue_exit(&descq->conf, pair_descq); - else - dbgfs_queue_exit(&descq->conf, NULL); -#endif -#ifndef __QDMA_VF__ - rv = qdma_dev_decrement_active_queue(xdev->dma_device_index, - xdev->func_id, - (enum qdma_dev_q_type)descq->conf.q_type); - if (rv < 0) { - pr_err("Failed to decrement the active %s queue", - q_type_list[descq->conf.q_type].name); - return rv; - } - - if (descq->conf.st && (descq->conf.q_type == Q_C2H)) { - rv = qdma_dev_decrement_active_queue(xdev->dma_device_index, - xdev->func_id, QDMA_DEV_Q_TYPE_CMPT); - if (rv < 0) { - pr_err("Failed to decrement the active CMPT queue"); - qdma_dev_increment_active_queue(xdev->dma_device_index, - xdev->func_id, - (enum qdma_dev_q_type)descq->conf.q_type); - return rv; - } - } -#else - rv = qdma_dev_notify_qdel(descq, - (enum queue_type_t)descq->conf.q_type); - if (rv < 0) { - pr_err("Failed to decrement active %s queue count", - q_type_list[descq->conf.q_type].name); - return rv; - } - if (descq->conf.st && (descq->conf.q_type == Q_C2H)) { - rv = qdma_dev_notify_qdel(descq, Q_CMPT); - if (rv < 0) { - pr_err("Failed to decrement active CMPT queue count"); - qdma_dev_notify_qadd(descq, - (enum queue_type_t)descq->conf.q_type); - return rv; - } - } -#endif - - lock_descq(descq); - descq->q_state = Q_STATE_DISABLED; - unlock_descq(descq); - -#ifndef __QDMA_VF__ - if (xdev->conf.qdma_drv_mode == LEGACY_INTR_MODE) - intr_legacy_clear(descq); -#endif - snprintf(buf, buflen, "queue %s, id %u deleted.\n", - descq->conf.name, descq->conf.qidx); - - pr_debug("queue %s, id %u deleted.\n", - descq->conf.name, descq->conf.qidx); - - return 0; -} - -/*****************************************************************************/ -/** - * qdma_queue_config() - configure the queue with qconf parameters - * - * @param[in] dev_hndl: dev_hndl returned from qdma_device_open() - * @param[in] qid: queue id - * @param[in] qconf: queue configuration parameters - * @param[in] buflen: length of the input buffer - * @param[out] buf: message buffer - * - * @return 0: success - * @return <0: error - *****************************************************************************/ -int qdma_queue_config(unsigned long dev_hndl, unsigned long qid, - struct qdma_queue_conf *qconf, char *buf, int buflen) -{ - struct xlnx_dma_dev *xdev = (struct xlnx_dma_dev *)dev_hndl; - struct qdma_dev *qdev; - struct qdma_descq *descq = NULL; - int rv = 0; - - /** make sure that input buffer is not empty, else return error */ - if (!buf || !buflen) { - pr_err("invalid argument: buf=%p, buflen=%d", buf, buflen); - return -EINVAL; - } - - /** make sure that the dev_hndl passed is Valid */ - if (!xdev) { - pr_err("dev_hndl is NULL"); - snprintf(buf, buflen, "dev_hndl is NULL"); - return -EINVAL; - } - - if (xdev_check_hndl(__func__, xdev->conf.pdev, dev_hndl) < 0) { - pr_err("Invalid dev_hndl passed"); - snprintf(buf, buflen, "Invalid dev_hndl passed"); - return -EINVAL; - } - - qdev = xdev_2_qdev(xdev); - /** make sure that qdev is not NULL, else return error */ - if (!qdev) { - pr_err("dev %s, qdev null.\n", - dev_name(&xdev->conf.pdev->dev)); - snprintf(buf, buflen, "Q not already added. Add Q first\n"); - return -EINVAL; - } - - /** get the descq for the given qid */ - descq = qdma_device_get_descq_by_id(xdev, qid, NULL, 0, 0); - if (!descq) { - pr_err("Invalid queue ID! qid=%lu, max=%u\n", qid, qdev->qmax); - snprintf(buf, buflen, - "Invalid queue ID qid=%lu, max=%u, base=%u\n", - qid, qdev->qmax, qdev->qbase); - return -EINVAL; - } - - lock_descq(descq); - /* if descq is not in enabled state, return error */ - if (descq->q_state != Q_STATE_ENABLED) { - pr_err("queue_%lu Invalid state! Q not in enabled state\n", - qid); - snprintf(buf, buflen, - "Error. Required Q state=%s, Current Q state=%s\n", - q_state_list[Q_STATE_ENABLED].name, - q_state_list[descq->q_state].name); - unlock_descq(descq); - return -EINVAL; - } - unlock_descq(descq); - - rv = qdma_validate_qconfig(xdev, qconf, buf, buflen); - if (rv != 0) - return rv; - - /** configure descriptor queue */ - lock_descq(descq); - qdma_descq_config(descq, qconf, 1); - unlock_descq(descq); - - snprintf(buf, buflen, - "Queue %s id %u is configured with the qconf passed ", - descq->conf.name, - descq->conf.qidx); - - return 0; -} - -/*****************************************************************************/ -/** - * qdma_queue_list() - display all configured queues in a string buffer - * - * @param[in] dev_hndl: dev_hndl returned from qdma_device_open() - * @param[in] qidx: Queue index - * @param[in] num_q: Number of Queues to list - * @param[in] buflen: length of the input buffer - * @param[out] buf: message buffer - * - * @return success: if optional message buffer used then strlen of buf, - * otherwise 0 - * @return <0: error - *****************************************************************************/ -int qdma_queue_list(unsigned long dev_hndl, int qidx, int num_q, char *buf, - int buflen) -{ - struct xlnx_dma_dev *xdev = (struct xlnx_dma_dev *)dev_hndl; - struct qdma_dev *qdev; - struct qdma_descq *descq = NULL; - char *cur = buf; - char * const end = buf + buflen; - uint32_t h2c_qcnt = 0, c2h_qcnt = 0, cmpt_qcnt = 0; - int i; - - /** make sure that input buffer is not empty, else return error */ - if (!buf || !buflen) { - pr_err("invalid argument: buf=%p, buflen=%d", buf, buflen); - return -EINVAL; - } - - /** make sure that the dev_hndl passed is Valid */ - if (!xdev) { - pr_err("dev_hndl is NULL"); - snprintf(buf, buflen, "dev_hndl is NULL"); - return -EINVAL; - } - - if (xdev_check_hndl(__func__, xdev->conf.pdev, dev_hndl) < 0) { - pr_err("Invalid dev_hndl passed"); - snprintf(buf, buflen, "Invalid dev_hndl passed"); - return -EINVAL; - } - - qdev = xdev_2_qdev(xdev); - /** make sure that qdev is not NULL, else return error */ - if (!qdev) { - pr_err("dev %s, qdev null.\n", dev_name(&xdev->conf.pdev->dev)); - snprintf(buf, buflen, "Q not already added. Add Q first\n"); - return -EINVAL; - } -#ifndef __QDMA_VF__ - h2c_qcnt = qdma_get_device_active_queue_count( - xdev->dma_device_index, - xdev->func_id, - QDMA_DEV_Q_TYPE_H2C); - - c2h_qcnt = qdma_get_device_active_queue_count( - xdev->dma_device_index, - xdev->func_id, - QDMA_DEV_Q_TYPE_C2H); - - cmpt_qcnt = qdma_get_device_active_queue_count( - xdev->dma_device_index, - xdev->func_id, - QDMA_DEV_Q_TYPE_CMPT); -#else - qdma_dev_get_active_qcnt(xdev, &h2c_qcnt, &c2h_qcnt, &cmpt_qcnt); -#endif - cur += snprintf(cur, end - cur, "H2C Q: %u, C2H Q: %u, CMPT Q %u.\n", - h2c_qcnt, c2h_qcnt, cmpt_qcnt); - if (cur >= end) - goto handle_truncation; - - /** traverse through the h2c and c2h queue list - * and dump the descriptors - */ - if (h2c_qcnt) { - descq = qdev->h2c_descq; - descq = descq + qidx; - for (i = qidx; i < (qidx + num_q); i++, descq++) { - lock_descq(descq); - if (descq->q_state != Q_STATE_DISABLED) - cur += - qdma_descq_dump(descq, cur, end - cur, 0); - unlock_descq(descq); - - if (cur >= end) - goto handle_truncation; - } - } - - if (c2h_qcnt) { - descq = qdev->c2h_descq; - descq = descq + qidx; - for (i = qidx; i < (qidx + num_q); i++, descq++) { - lock_descq(descq); - if (descq->q_state != Q_STATE_DISABLED) - cur += - qdma_descq_dump(descq, cur, end - cur, 0); - unlock_descq(descq); - - if (cur >= end) - goto handle_truncation; - } - } - - if (cmpt_qcnt) { - descq = qdev->cmpt_descq; - descq = descq + qidx; - for (i = qidx; i < (qidx + num_q); i++, descq++) { - lock_descq(descq); - if (descq->q_state != Q_STATE_DISABLED) - cur += - qdma_descq_dump(descq, cur, end - cur, 0); - unlock_descq(descq); - - if (cur >= end) - goto handle_truncation; - } - } - - return cur - buf; - -handle_truncation: - *buf = '\0'; - return buf - cur; -} - -#define Q_PRESENT_H2C_MASK (1 << Q_H2C) -#define Q_PRESENT_C2H_MASK (1 << Q_C2H) -#define Q_PRESENT_CMPT_MASK (1 << Q_CMPT) -#define Q_MODE_SHIFT 3 -#define Q_MODE_MASK (1 << Q_MODE_SHIFT) - -static int is_usable_queue(struct xlnx_dma_dev *xdev, int qidx, - int q_type, int st) -{ - struct qdma_dev *qdev = xdev_2_qdev(xdev); - int refmask = 0x0; - int cmptq_chkmask = 0x0; - int h2cq_chkmask = 0x0; - int c2hq_chkmask = 0x0; - int reqmask = 0; - struct qdma_descq *h2c_descq = qdev->h2c_descq + qidx; - struct qdma_descq *c2h_descq = qdev->c2h_descq + qidx; - struct qdma_descq *cmpt_descq = qdev->cmpt_descq + qidx; - - lock_descq(h2c_descq); - if (h2c_descq->q_state != Q_STATE_DISABLED) { - refmask |= (1 << Q_H2C); - if (h2c_descq->conf.st) - refmask |= (1 << Q_MODE_SHIFT); - } - unlock_descq(h2c_descq); - - lock_descq(c2h_descq); - if (c2h_descq->q_state != Q_STATE_DISABLED) { - refmask |= (1 << Q_C2H); - if (c2h_descq->conf.st) - refmask |= (1 << Q_MODE_SHIFT); - } - unlock_descq(c2h_descq); - - lock_descq(cmpt_descq); - if (cmpt_descq->q_state != Q_STATE_DISABLED) - refmask |= (1 << Q_CMPT); - unlock_descq(cmpt_descq); - - reqmask = (1 << q_type); - if (st) - reqmask |= Q_MODE_MASK; - if (q_type == Q_CMPT) { - cmptq_chkmask |= (Q_PRESENT_CMPT_MASK | Q_MODE_MASK); - if (refmask & cmptq_chkmask) { - pr_err("Q_CMPT: refmask not valid"); - goto q_reject; - } - } else if (q_type == Q_H2C) { - c2hq_chkmask = (Q_PRESENT_C2H_MASK | Q_MODE_MASK); - if (st && (refmask & Q_PRESENT_CMPT_MASK)) { - pr_err("Q_H2C: CMPT q given to MM"); - goto q_reject; /* CMPT q given to MM */ - } - if (st && (refmask & Q_PRESENT_C2H_MASK) - && (refmask & c2hq_chkmask) - == Q_PRESENT_C2H_MASK) { - pr_err("Q_H2C: MM mode c2h q present"); - goto q_reject; /* MM mode c2h q present*/ - } - if (!st && (refmask & Q_PRESENT_C2H_MASK) - && (refmask & c2hq_chkmask) == c2hq_chkmask) { - pr_err("Q_H2C: ST mode c2h q present"); - goto q_reject; /* ST mode c2h q present*/ - } - if (refmask & Q_PRESENT_H2C_MASK) { - pr_err("Q_H2C: h2c q already present"); - goto q_reject; /* h2c q already present */ - } - } else { - h2cq_chkmask |= (Q_PRESENT_H2C_MASK | Q_MODE_MASK); - if (st && (refmask & Q_PRESENT_CMPT_MASK)) { - pr_err("!Q_H2C: CMPT q given to MM"); - goto q_reject; /* CMPT q given to MM */ - } - if (st && (refmask & Q_PRESENT_H2C_MASK) - && (refmask & h2cq_chkmask) - == Q_PRESENT_H2C_MASK) { - pr_err("!Q_H2C: MM mode h2c q present"); - goto q_reject; /* MM mode h2c q present*/ - } - if (!st && (refmask & Q_PRESENT_H2C_MASK) - && (refmask & h2cq_chkmask) == h2cq_chkmask) { - pr_err("!Q_H2C: ST mode h2c q present"); - goto q_reject; /* ST mode h2c q present*/ - } - if (refmask & Q_PRESENT_C2H_MASK) { - pr_err("!Q_H2C: c2h q already present"); - goto q_reject; /* c2h q already present */ - } - } - return 0; -q_reject: - pr_err("Q addition feasibility check failed"); - return -1; -} - -/*****************************************************************************/ -/** - * qdma_queue_add() - add a queue - * - * @param[in] dev_hndl: dev_hndl returned from qdma_device_open() - * @param[in] qconf: queue configuration parameters - * @param[in] qhndl: list of unsigned long values that are the opaque qhndl - * @param[in] buflen: length of the input buffer - * @param[out] buf: message buffer - * - * @return 0: success - * @return <0: error - *****************************************************************************/ -int qdma_queue_add(unsigned long dev_hndl, struct qdma_queue_conf *qconf, - unsigned long *qhndl, char *buf, int buflen) -{ - struct xlnx_dma_dev *xdev = (struct xlnx_dma_dev *)dev_hndl; - unsigned int qcnt; - struct qdma_descq *descq; - struct qdma_dev *qdev; -#ifdef DEBUGFS - struct qdma_descq *pairq; -#endif -#ifdef __QDMA_VF__ - uint32_t h2c_qcnt = 0, c2h_qcnt = 0, cmpt_qcnt = 0; -#endif - int rv = 0; - - /** make sure that input buffer is not empty, else return error */ - if (!buf || !buflen) { - pr_err("invalid argument: buf=%p, buflen=%d", buf, buflen); - return -EINVAL; - } - - /** make sure that the dev_hndl passed is Valid */ - if (!xdev) { - pr_err("dev_hndl is NULL"); - snprintf(buf, buflen, "dev_hndl is NULL"); - return -EINVAL; - } - - if (xdev_check_hndl(__func__, xdev->conf.pdev, dev_hndl) < 0) { - pr_err("Invalid dev_hndl passed"); - snprintf(buf, buflen, "Invalid dev_hndl passed"); - return -EINVAL; - } - - /** If qconf is NULL, return error*/ - if (!qconf) { - pr_err("Invalid qconf %p", qconf); - snprintf(buf, buflen, - "%s, add, qconf NULL.\n", - xdev->conf.name); - return -EINVAL; - } - - /** If qhndl is NULL, return error*/ - if (!qhndl) { - pr_warn("qhndl NULL.\n"); - snprintf(buf, buflen, - "%s, add, qhndl NULL.\n", - xdev->conf.name); - return -EINVAL; - } - - if (qconf->q_type > Q_CMPT) { - pr_err("Invalid queue type passed"); - snprintf(buf, buflen, "Invalid queue type passed"); - return -EINVAL; - } - - if (qconf->st && (qconf->q_type == Q_CMPT)) { - pr_err("Can not create independent completion ring for ST mode. It is supported along with C2H direction"); - snprintf(buf, buflen, - "Can not create independent completion ring for ST mode. It is supported along with C2H direction"); - return -EINVAL; - } - - if ((qconf->q_type == Q_CMPT) && !xdev->dev_cap.mm_cmpt_en) { - pr_err("MM Completions not enabled"); - snprintf(buf, buflen, "MM Completions not enabled"); - return -EINVAL; - } - - qdev = xdev_2_qdev(xdev); - - /** reset qhandle to an invalid value - * can't use 0 or NULL here because queue idx 0 has same value - */ - *qhndl = QDMA_QUEUE_IDX_INVALID; - - /** check if the requested mode is enabled? - * the request modes are read from the HW - * before serving any request, first check if the - * HW has the capability or not, else return error - */ - if ((qconf->st && !xdev->dev_cap.st_en) || - (!qconf->st && !xdev->dev_cap.mm_en)) { - pr_warn("%s, %s mode not enabled.\n", - xdev->conf.name, qconf->st ? "ST" : "MM"); - snprintf(buf, buflen, - "qdma%05x %s mode not enabled.\n", - xdev->conf.bdf, qconf->st ? "ST" : "MM"); - return -EINVAL; - } - - rv = qdma_validate_qconfig(xdev, qconf, buf, buflen); - if (rv < 0) - return rv; - - spin_lock(&qdev->lock); - /** if incase the qidx is not QDMA_QUEUE_IDX_INVALID - * then, make sure that the qidx range falls between - * 0 - qdev->qmax, else return error - */ - if ((qconf->qidx != QDMA_QUEUE_IDX_INVALID) && - (qconf->qidx >= qdev->qmax)) { - spin_unlock(&qdev->lock); - snprintf(buf, buflen, - "qdma%05x invalid idx %u >= %u.\n", - xdev->conf.bdf, qconf->qidx, qdev->qmax); - pr_err("Invalid queue index, qid = %d, qmax = %d", - qconf->qidx, qdev->qmax); - return -EINVAL; - } - - /** check if any free qidx available - * if qcnt is >= qdev->qmax, return error as - * no free queues found and descq is full - */ -#ifndef __QDMA_VF__ - qcnt = qdma_get_device_active_queue_count(xdev->dma_device_index, - xdev->func_id, qconf->q_type); -#else - spin_unlock(&qdev->lock); - qdma_dev_get_active_qcnt(xdev, &h2c_qcnt, &c2h_qcnt, &cmpt_qcnt); - spin_lock(&qdev->lock); - if (qconf->q_type == Q_H2C) - qcnt = h2c_qcnt; - else if (qconf->q_type == Q_C2H) - qcnt = c2h_qcnt; - else - qcnt = cmpt_qcnt; -#endif - if (qcnt >= qdev->qmax) { - spin_unlock(&qdev->lock); - pr_warn("No free queues %u/%u.\n", qcnt, qdev->qmax); - snprintf(buf, buflen, - "qdma%05x No free queues %u/%u.\n", - xdev->conf.bdf, qcnt, qdev->qmax); - return -EIO; - } - - - spin_unlock(&qdev->lock); - - if (qconf->q_type == Q_C2H) - descq = qdev->c2h_descq; - else if (qconf->q_type == Q_H2C) - descq = qdev->h2c_descq; - else - descq = qdev->cmpt_descq; - - /** need to allocate a free qidx if it has an invalid id - * ie. qidx is not specified in the add request - */ - if (qconf->qidx == QDMA_QUEUE_IDX_INVALID) { - int i; - - /** loop through the qlist till qmax and find an empty descq*/ - for (i = 0; i < qdev->qmax; i++, descq++) { - if (is_usable_queue(xdev, i, qconf->q_type, - qconf->st) < 0) - continue; - - descq += i; - lock_descq(descq); - - /** set the descq as enabled*/ - descq->q_state = Q_STATE_ENABLED; - /** assign the qidx */ - qconf->qidx = i; - unlock_descq(descq); - - break; - } - - /** we are reached here means no free descq found - * decrement the queue count and return error - */ - if (i == qdev->qmax) { - pr_warn("no free %s qp found, %u.\n", - qconf->st ? "ST" : "MM", qdev->qmax); - rv = -EPERM; - snprintf(buf, buflen, - "qdma%05x no %s QP, %u.\n", - xdev->conf.bdf, - qconf->st ? "ST" : "MM", qdev->qmax); - return rv; - } - } else { - if (is_usable_queue(xdev, qconf->qidx, qconf->q_type, - qconf->st) < 0) { - pr_err("Queue compatibility check failed against existing queues\n"); - snprintf(buf, buflen, - "Queue compatibility check failed against existing queues\n"); - return -EPERM; - } - - descq += qconf->qidx; - - lock_descq(descq); - - /** set the descq as enabled*/ - descq->q_state = Q_STATE_ENABLED; - - unlock_descq(descq); - } - - /** prepare the queue resources*/ - rv = qdma_device_prep_q_resource(xdev); - if (rv < 0) { -#ifdef __QDMA_VF__ - lock_descq(descq); - descq->q_state = Q_STATE_DISABLED; - unlock_descq(descq); -#endif - return rv; - } -#ifndef __QDMA_VF__ - if (xdev->conf.qdma_drv_mode == LEGACY_INTR_MODE) { - rv = intr_legacy_setup(descq); - if (rv > 0) { - /** support only 1 queue in legacy interrupt mode */ - intr_legacy_clear(descq); - lock_descq(descq); - descq->q_state = Q_STATE_DISABLED; - unlock_descq(descq); - pr_debug("qdma%05x - Q%u - No free queues %u/%u.\n", - xdev->conf.bdf, descq->conf.qidx, - rv, 1); - rv = -EINVAL; - snprintf(buf, buflen, - "qdma%05x No free queues %u/%d.\n", - xdev->conf.bdf, qcnt, 1); - return rv; - } else if (rv < 0) { - rv = -EINVAL; - lock_descq(descq); - descq->q_state = Q_STATE_DISABLED; - unlock_descq(descq); - pr_debug("qdma%05x Legacy interrupt setup failed.\n", - xdev->conf.bdf); - snprintf(buf, buflen, - "qdma%05x Legacy interrupt setup failed.\n", - xdev->conf.bdf); - return rv; - } - } -#endif - /** fill in config. info */ - qdma_descq_config(descq, qconf, 0); -#ifndef __QDMA_VF__ - rv = qdma_dev_increment_active_queue(xdev->dma_device_index, - xdev->func_id, (enum qdma_dev_q_type)qconf->q_type); - if (rv < 0) { - pr_err("Failed to increment active %s queue count", - q_type_list[qconf->q_type].name); - return rv; - } - if (qconf->st && (qconf->q_type == Q_C2H)) { - rv = qdma_dev_increment_active_queue(xdev->dma_device_index, - xdev->func_id, QDMA_DEV_Q_TYPE_CMPT); - if (rv < 0) { - pr_err("Failed to increment CMPT queue count"); - qdma_dev_decrement_active_queue(xdev->dma_device_index, - xdev->func_id, - (enum qdma_dev_q_type)qconf->q_type); - return rv; - } - } -#else - rv = qdma_dev_notify_qadd(descq, - (enum queue_type_t)qconf->q_type); - if (rv < 0) { - pr_err("Failed to increment active %s queue count", - q_type_list[qconf->q_type].name); - return rv; - } - if (qconf->st && (qconf->q_type == Q_C2H)) { - rv = qdma_dev_notify_qadd(descq, Q_CMPT); - if (rv < 0) { - pr_err("Failed to increment active CMPT queue count"); - qdma_dev_notify_qdel(descq, - (enum queue_type_t)qconf->q_type); - return rv; - } - } -#endif - - /** copy back the name in config*/ - memcpy(qconf->name, descq->conf.name, QDMA_QUEUE_NAME_MAXLEN); - *qhndl = (unsigned long)descq->conf.qidx; - if (qconf->q_type == Q_C2H) - *qhndl += qdev->qmax; - if (qconf->q_type == Q_CMPT) - *qhndl += (2 * qdev->qmax); - descq->q_hndl = *qhndl; - - -#ifdef DEBUGFS - if (qconf->q_type != Q_CMPT) { - if (qconf->q_type == Q_H2C) - pairq = qdev->c2h_descq + qconf->qidx; - else - pairq = qdev->h2c_descq + qconf->qidx; - - rv = dbgfs_queue_init(&descq->conf, pairq, - xdev->dbgfs_queues_root); - if (rv < 0) { - pr_err("failed to create queue debug files for the queueu %d\n", - descq->conf.qidx); - } - } -#endif - - pr_debug("added %s, %s, qidx %u.\n", - descq->conf.name, - q_type_list[qconf->q_type].name, - qconf->qidx); - - snprintf(buf, buflen, "%s %s added.\n", - descq->conf.name, - q_type_list[qconf->q_type].name); - - return 0; -} - -/*****************************************************************************/ -/** - * qdma_queue_start() - start a queue (i.e, online, ready for dma) - * - * @param[in] dev_hndl: dev_hndl returned from qdma_device_open() - * @param[in] id: queue index - * @param[in] buflen: length of the input buffer - * @param[out] buf: message buffer - * - * @return 0: success - * @return <0: error - *****************************************************************************/ -int qdma_queue_start(unsigned long dev_hndl, unsigned long id, - char *buf, int buflen) -{ - struct qdma_descq *descq; - struct xlnx_dma_dev *xdev = (struct xlnx_dma_dev *)dev_hndl; - int rv; - - /** make sure that input buffer is not empty, else return error */ - if (!buf || !buflen) { - pr_err("invalid argument: buf=%p, buflen=%d", buf, buflen); - return -EINVAL; - } - - /** make sure that the dev_hndl passed is Valid */ - if (!xdev) { - pr_err("dev_hndl is NULL"); - snprintf(buf, buflen, "dev_hndl is NULL"); - return -EINVAL; - } - - if (xdev_check_hndl(__func__, xdev->conf.pdev, dev_hndl) < 0) { - pr_err("Invalid dev_hndl passed"); - snprintf(buf, buflen, "Invalid dev_hndl passed"); - return -EINVAL; - } - - descq = qdma_device_get_descq_by_id(xdev, id, buf, buflen, 1); - /** make sure that descq is not NULL, else return error*/ - if (!descq) { - pr_err("Invalid qid(%lu)", id); - snprintf(buf, buflen, - "Invalid qid(%lu)\n", id); - return -EINVAL; - } - - lock_descq(descq); - /** if the descq is not enabled, - * it is in invalid state, return error - */ - if (descq->q_state != Q_STATE_ENABLED) { - pr_err("%s invalid state, q_status%d.\n", - descq->conf.name, descq->q_state); - snprintf(buf, buflen, - "%s invalid state, q_state %d.\n", - descq->conf.name, descq->q_state); - unlock_descq(descq); - return -EINVAL; - } - - if ((xdev->version_info.ip_type == EQDMA_SOFT_IP) && - (xdev->version_info.vivado_release >= QDMA_VIVADO_2020_2)) { - - if (xdev->dev_cap.desc_eng_mode - == QDMA_DESC_ENG_BYPASS_ONLY) { - pr_err("Err: Bypass Only Design is not supported\n"); - snprintf(buf, buflen, - "%s Bypass Only Design is not supported\n", - descq->conf.name); - unlock_descq(descq); - return -EINVAL; - } - - if (descq->conf.desc_bypass) { - if (xdev->dev_cap.desc_eng_mode - == QDMA_DESC_ENG_INTERNAL_ONLY) { - pr_err("Err: Bypass mode not supported in Internal Mode only design\n"); - snprintf(buf, buflen, - "%s Bypass mode not supported in Internal Mode only design\n", - descq->conf.name); - unlock_descq(descq); - return -EINVAL; - } - } - } - - - if ((descq->conf.aperture_size != 0) && - ((descq->conf.aperture_size & - (descq->conf.aperture_size - 1)))) { - pr_err("Err: %s Power of 2 aperture size supported\n", - descq->conf.name); - snprintf(buf, buflen, - "Err:%s Power of 2 aperture size supported\n", - descq->conf.name); - unlock_descq(descq); - return -ERANGE; - } - /** complete the queue configuration*/ - rv = qdma_descq_config_complete(descq); - if (rv < 0) { - pr_err("%s 0x%x setup failed.\n", - descq->conf.name, descq->qidx_hw); - snprintf(buf, buflen, - "%s config failed.\n", descq->conf.name); - unlock_descq(descq); - return -EIO; - } - unlock_descq(descq); - - /** allocate the queue resources*/ - rv = qdma_descq_alloc_resource(descq); - if (rv < 0) { - pr_err("%s alloc resource failed.\n", descq->conf.name); - snprintf(buf, buflen, - "%s alloc resource failed.\n", - descq->conf.name); - return rv; - } - - /** program the hw contexts*/ - rv = qdma_descq_prog_hw(descq); - if (rv < 0) { - pr_err("%s 0x%x setup failed.\n", - descq->conf.name, descq->qidx_hw); - snprintf(buf, buflen, - "%s prog. context failed.\n", - descq->conf.name); - goto clear_context; - } - - /** Interrupt mode */ - if (descq->xdev->num_vecs) { - unsigned long flags; - struct intr_info_t *dev_intr_info_list = - &descq->xdev->dev_intr_info_list[descq->intr_id]; - - spin_lock_irqsave(&dev_intr_info_list->vec_q_list, flags); - list_add_tail(&descq->intr_list, - &dev_intr_info_list->intr_list); - dev_intr_info_list->intr_list_cnt++; - spin_unlock_irqrestore(&dev_intr_info_list->vec_q_list, flags); - } - - qdma_thread_add_work(descq); - - snprintf(buf, buflen, "queue %s, idx %u started\n", - descq->conf.name, descq->conf.qidx); - - /** set the descq to online state*/ - lock_descq(descq); - descq->q_state = Q_STATE_ONLINE; - unlock_descq(descq); - - return 0; - -clear_context: - qdma_descq_context_clear(descq->xdev, descq->qidx_hw, - descq->conf.st, descq->conf.q_type, 1); - qdma_descq_free_resource(descq); - - return rv; -} - -int qdma_get_queue_state(unsigned long dev_hndl, unsigned long id, - struct qdma_q_state *q_state, char *buf, int buflen) -{ - struct qdma_descq *descq; - struct xlnx_dma_dev *xdev = (struct xlnx_dma_dev *)dev_hndl; - - /** make sure that input buffer is not empty, else return error */ - if (!buf || !buflen) { - pr_err("invalid argument: buf=%p, buflen=%d", buf, buflen); - return -EINVAL; - } - - /** make sure that the dev_hndl passed is Valid */ - if (!xdev) { - pr_err("dev_hndl is NULL"); - snprintf(buf, buflen, "dev_hndl is NULL"); - return -EINVAL; - } - - if (xdev_check_hndl(__func__, xdev->conf.pdev, dev_hndl) < 0) { - pr_err("Invalid dev_hndl passed"); - snprintf(buf, buflen, "Invalid dev_hndl passed"); - return -EINVAL; - } - - descq = qdma_device_get_descq_by_id(xdev, id, buf, buflen, 1); - /** make sure that descq is not NULL, else return error */ - if (!descq) { - pr_err("Invalid qid(%lu)", id); - snprintf(buf, buflen, - "Invalid qid(%lu)\n", id); - return -EINVAL; - } - - if (!q_state) { - pr_err("Invalid q_state:%p", q_state); - return -EINVAL; - } - - lock_descq(descq); - /** mode */ - q_state->st = descq->conf.st; - /** type */ - q_state->q_type = (enum queue_type_t)descq->conf.q_type; - /** qidx */ - q_state->qidx = descq->conf.qidx; - /** q state */ - q_state->qstate = descq->q_state; - - snprintf(buf, buflen, - "queue state for %s id %u : %s\n", - descq->conf.name, - descq->conf.qidx, - q_state_list[descq->q_state].name); - - unlock_descq(descq); - - return 0; -} - - - -/*****************************************************************************/ -/** - * qdma_queue_stop() - stop a queue (i.e., offline, NOT ready for dma) - * - * @param[in] dev_hndl: dev_hndl returned from qdma_device_open() - * @param[in] id: queue index - * @param[in] buflen: length of the input buffer - * @param[out] buf: message buffer - * - * @return 0: success - * @return <0: error - *****************************************************************************/ -int qdma_queue_stop(unsigned long dev_hndl, unsigned long id, char *buf, - int buflen) -{ - struct xlnx_dma_dev *xdev = (struct xlnx_dma_dev *)dev_hndl; - struct qdma_descq *descq; - struct qdma_sgt_req_cb *cb, *tmp; - struct qdma_request *req; - unsigned int pend_list_empty = 0; - - /** make sure that input buffer is not empty, else return error */ - if (!buf || !buflen) { - pr_err("invalid argument: buf=%p, buflen=%d", buf, buflen); - return -EINVAL; - } - - /** make sure that the dev_hndl passed is Valid */ - if (!xdev) { - pr_err("dev_hndl is NULL"); - snprintf(buf, buflen, "dev_hndl is NULL"); - return -EINVAL; - } - - if (xdev_check_hndl(__func__, xdev->conf.pdev, dev_hndl) < 0) { - pr_err("Invalid dev_hndl passed"); - snprintf(buf, buflen, "Invalid dev_hndl passed"); - return -EINVAL; - } - - descq = qdma_device_get_descq_by_id(xdev, id, buf, buflen, 1); - /** make sure that descq is not NULL, else return error */ - if (!descq) { - pr_err("Invalid qid(%ld)", id); - return -EINVAL; - } - - lock_descq(descq); - /** if the descq not online donot proceed */ - if (descq->q_state != Q_STATE_ONLINE) { - unlock_descq(descq); - pr_err("%s invalid state, q_state %d.\n", - descq->conf.name, descq->q_state); - snprintf(buf, buflen, - "queue %s, idx %u stop failed.\n", - descq->conf.name, descq->conf.qidx); - return -EINVAL; - } - pend_list_empty = descq->pend_list_empty; - - descq->q_stop_wait = 1; - unlock_descq(descq); - if (!pend_list_empty) { - qdma_waitq_wait_event_timeout(descq->pend_list_wq, - descq->pend_list_empty, - msecs_to_jiffies(QDMA_Q_PEND_LIST_COMPLETION_TIMEOUT)); - } - lock_descq(descq); - /** free the descq by updating the state */ - descq->q_state = Q_STATE_ENABLED; - descq->q_stop_wait = 0; - list_for_each_entry_safe(cb, tmp, &descq->pend_list, list) { - req = (struct qdma_request *)cb; - cb->done = 1; - cb->status = -ENXIO; - if (req->fp_done) { - list_del(&cb->list); - req->fp_done(req, 0, -ENXIO); - } else - qdma_waitq_wakeup(&cb->wq); - } - list_for_each_entry_safe(cb, tmp, &descq->work_list, list) { - req = (struct qdma_request *)cb; - cb->done = 1; - cb->status = -ENXIO; - if (req->fp_done) { - qdma_work_queue_del(descq, cb); - req->fp_done(req, 0, -ENXIO); - } else - qdma_waitq_wakeup(&cb->wq); - } - unlock_descq(descq); - - /** remove the work thread associated with the current queue */ - qdma_thread_remove_work(descq); - - /** clear the queue context */ - qdma_descq_context_clear(descq->xdev, descq->qidx_hw, - descq->conf.st, descq->conf.q_type, 0); - - /** if the device is in direct/indirect interrupt mode, - * delete the interrupt list for the queue - */ - if ((descq->xdev->conf.qdma_drv_mode != POLL_MODE) && - (descq->xdev->conf.qdma_drv_mode != LEGACY_INTR_MODE)) { - unsigned long flags; - struct intr_info_t *dev_intr_info_list = - &descq->xdev->dev_intr_info_list[descq->intr_id]; - - spin_lock_irqsave(&dev_intr_info_list->vec_q_list, flags); - list_del(&descq->intr_list); - dev_intr_info_list->intr_list_cnt--; - spin_unlock_irqrestore(&dev_intr_info_list->vec_q_list, flags); - } - - /** free the queue resources */ - qdma_descq_free_resource(descq); - /** free the descq by updating the state */ - descq->total_cmpl_descs = 0; - - /** fill the return buffer indicating that queue is stopped */ - snprintf(buf, buflen, "queue %s, idx %u stopped.\n", - descq->conf.name, descq->conf.qidx); - - return 0; -} - -/*****************************************************************************/ -/** - * qdma_get_queue_count() - Function to fetch the total number of queues - * - * @param[in] dev_hndl: dev_hndl returned from qdma_device_open() - * @param[out] q_count: total q count - * @param[out] buf: message buffer - * @param[in] buflen: length of the input buffer - * - * @return 0: success - * @return <0: error - *****************************************************************************/ -int qdma_get_queue_count(unsigned long dev_hndl, - struct qdma_queue_count *q_count, - char *buf, int buflen) -{ - struct xlnx_dma_dev *xdev = (struct xlnx_dma_dev *)dev_hndl; - - /** make sure that input buffer is not empty, else return error */ - if (!buf || !buflen || !q_count) { - pr_err("invalid argument: buf=%p, buflen=%d", buf, buflen); - return -EINVAL; - } - - /** make sure that the dev_hndl passed is Valid */ - if (!xdev) { - pr_err("dev_hndl is NULL"); - snprintf(buf, buflen, "dev_hndl is NULL"); - return -EINVAL; - } - -#ifndef __QDMA_VF__ - q_count->h2c_qcnt = qdma_get_device_active_queue_count( - xdev->dma_device_index, - xdev->func_id, - QDMA_DEV_Q_TYPE_H2C); - - q_count->c2h_qcnt = qdma_get_device_active_queue_count( - xdev->dma_device_index, - xdev->func_id, - QDMA_DEV_Q_TYPE_C2H); - - q_count->cmpt_qcnt = qdma_get_device_active_queue_count( - xdev->dma_device_index, - xdev->func_id, - QDMA_DEV_Q_TYPE_CMPT); -#else - qdma_dev_get_active_qcnt(xdev, &(q_count->h2c_qcnt), - &(q_count->c2h_qcnt), - &(q_count->cmpt_qcnt)); -#endif - - pr_debug("h2c_qcnt = %d, c2h_qcnt = %d, cmpt_qcnt = %d", - q_count->h2c_qcnt, - q_count->c2h_qcnt, - q_count->cmpt_qcnt); - return 0; -} -/*****************************************************************************/ -/** - * qdma_intr_ring_dump() - display the interrupt ring info of a vector - * - * @param[in] dev_hndl: dev_hndl returned from qdma_device_open() - * @param[in] vector_idx: vector number - * @param[in] start_idx: interrupt ring start idx - * @param[in] end_idx: interrupt ring end idx - * @param[in] buflen: length of the input buffer - * @param[out] buf: message buffer - * - * @return 0: success - * @return <0: error - *****************************************************************************/ -int qdma_intr_ring_dump(unsigned long dev_hndl, unsigned int vector_idx, - int start_idx, int end_idx, char *buf, int buflen) -{ - struct xlnx_dma_dev *xdev = (struct xlnx_dma_dev *)dev_hndl; - union qdma_intr_ring *ring_entry; - struct intr_coal_conf *coal_entry; - char *cur = buf; - char * const end = buf + buflen; - int counter = 0; - u32 data[2]; - - /** make sure that input buffer is not empty, else return error */ - if (!buf || !buflen) { - pr_err("invalid argument: buf=%p, buflen=%d", buf, buflen); - return -EINVAL; - } - - /** make sure that the dev_hndl passed is Valid */ - if (!xdev) { - pr_err("dev_hndl is NULL"); - snprintf(buf, buflen, "dev_hndl is NULL"); - return -EINVAL; - } - - if (xdev_check_hndl(__func__, xdev->conf.pdev, dev_hndl) < 0) { - pr_err("Invalid dev_hndl passed"); - snprintf(buf, buflen, "Invalid dev_hndl passed"); - return -EINVAL; - } - - /** if, interrupt aggregation is not enabled, - * interrupt ring is not created, return error - */ - if ((xdev->conf.qdma_drv_mode != INDIRECT_INTR_MODE) && - (xdev->conf.qdma_drv_mode != AUTO_MODE)) { - pr_err("Interrupt aggregation not enabled in %s mode", - mode_name_list[xdev->conf.qdma_drv_mode].name); - snprintf(buf, buflen, - "Interrupt aggregation not enabled in %s mode", - mode_name_list[xdev->conf.qdma_drv_mode].name); - return -EINVAL; - } - - /** make sure that vector index is with in the - * start and end vector limit, else return error - */ - if ((vector_idx < xdev->dvec_start_idx) || - (vector_idx >= - (xdev->dvec_start_idx + QDMA_NUM_DATA_VEC_FOR_INTR_CXT))) { - pr_err("Vector idx %u is invalid. Shall be in range: %d - %d.\n", - vector_idx, - xdev->dvec_start_idx, - (xdev->dvec_start_idx + - QDMA_NUM_DATA_VEC_FOR_INTR_CXT - 1)); - snprintf(buf, buflen, - "Vector idx %u is invalid. Shall be in range: %d - %d.\n", - vector_idx, - xdev->dvec_start_idx, - (xdev->dvec_start_idx + - QDMA_NUM_DATA_VEC_FOR_INTR_CXT - 1)); - return -EINVAL; - } - - /** get the intr entry based on vector index */ - coal_entry = xdev->intr_coal_list + (vector_idx - xdev->dvec_start_idx); - - /** make sure that intr ring entry indexes - * given are with in the range - */ - if (start_idx > coal_entry->intr_rng_num_entries) { - pr_err("start_idx %d is invalid. Shall be less than: %d\n", - start_idx, - coal_entry->intr_rng_num_entries); - snprintf(buf, buflen, - "start_idx %d is invalid. Shall be less than: %d\n", - start_idx, - coal_entry->intr_rng_num_entries); - return -EINVAL; - } - - if (end_idx == -1 || end_idx >= coal_entry->intr_rng_num_entries) - end_idx = coal_entry->intr_rng_num_entries - 1; - - if (start_idx == -1) - start_idx = 0; - - if (start_idx > end_idx) { - pr_err("start_idx can't be greater than end_idx\n"); - snprintf(buf, buflen, - "start_idx can't be greater than end_idx\n"); - return -EINVAL; - } - - /** read the ring entries based on the range given and - * update the input buffer with details - */ - for (counter = start_idx; counter <= end_idx; counter++) { - ring_entry = coal_entry->intr_ring_base + counter; - memcpy(data, ring_entry, sizeof(u32) * 2); - cur += snprintf(cur, end - cur, - "intr_ring_entry = %d: 0x%08x 0x%08x\n", - counter, data[1], data[0]); - if (cur >= end) - goto handle_truncation; - } - - return 0; -handle_truncation: - *buf = '\0'; - return 0; -} - - /*****************************************************************************/ - /** - * qdma_software_version_info Provides the qdma software version - * - * @param[out] software_version: libqdma software version - * - * @return 0: success - * @return <0: error - *****************************************************************************/ -int qdma_software_version_info(char *software_version, int length) -{ - if (!software_version) { - pr_err("Invalid input software_version:%p", software_version); - return -EINVAL; - } - - snprintf(software_version, length, "%s", LIBQDMA_VERSION_STR); - - return 0; -} - - -#ifdef __QDMA_VF__ - /*****************************************************************************/ - /** - * qdma_vf_qconf call for VF to request qmax number of Qs - * - * @param[in] dev_hndl: dev_hndl returned from qdma_device_open() - * @param[in] qmax: number of qs requested by vf - * - * @return 0: success - * @return <0: error - *****************************************************************************/ -int qdma_vf_qconf(unsigned long dev_hndl, int qmax) -{ - int err = 0; - int qbase = -1; - struct xlnx_dma_dev *xdev = (struct xlnx_dma_dev *)dev_hndl; - - if (!xdev) { - pr_err("Invalid dev handle\n"); - return -EINVAL; - } - - err = device_set_qconf(xdev, &qmax, &qbase); - if (err < 0) { - pr_err("Setting qconf failed\n"); - return err; - } - qdma_device_cleanup(xdev); - xdev->conf.qsets_base = qbase; - xdev->conf.qsets_max = qmax; - err = qdma_device_init(xdev); - if (err < 0) { - pr_warn("qdma_init failed %d.\n", err); - qdma_device_cleanup(xdev); - } - - return err; -} -#endif - -/*****************************************************************************/ -/** - * sgl_unmap() - unmap the sg list from host pages - * - * @param[in] pdev: pointer to struct pci_dev - * @param[in] sg: qdma sg request list - * @param[in] sgcnt: number of sg lists - * @param[in] dir: direction of the dma transfer - * DMA_BIDIRECTIONAL = 0, DMA_TO_DEVICE = 1, - * DMA_FROM_DEVICE = 2, DMA_NONE = 3, - * - * @return 0: success - * @return <0: error - *****************************************************************************/ -void sgl_unmap(struct pci_dev *pdev, struct qdma_sw_sg *sg, unsigned int sgcnt, - enum dma_data_direction dir) -{ - int i; - - /** unmap the sg list and set the dma_addr to 0 all sg entries */ - for (i = 0; i < sgcnt; i++, sg++) { - if (!sg->pg) - break; - if (sg->dma_addr) { - dma_unmap_page(&pdev->dev, sg->dma_addr - sg->offset, - PAGE_SIZE, dir); - sg->dma_addr = 0UL; - } - } -} - -/*****************************************************************************/ -/** - * sgl_map() - map sg list to host pages - * - * @param[in] pdev: pointer to struct pci_dev - * @param[in] sg: qdma sg request list - * @param[in] sgcnt: number of sg lists - * @param[in] dir: direction of the dma transfer - * DMA_BIDIRECTIONAL = 0, DMA_TO_DEVICE = 1, - * DMA_FROM_DEVICE = 2, DMA_NONE = 3, - * - * @return 0: success - * @return <0: error - *****************************************************************************/ -int sgl_map(struct pci_dev *pdev, struct qdma_sw_sg *sgl, unsigned int sgcnt, - enum dma_data_direction dir) -{ - int i; - struct qdma_sw_sg *sg = sgl; - - /** Map the sg list onto a dma pages where - * each page has max of PAGE_SIZE i.e 4K - */ - for (i = 0; i < sgcnt; i++, sg++) { - /* !! TODO page size !! */ - sg->dma_addr = dma_map_page(&pdev->dev, sg->pg, 0, PAGE_SIZE, - dir); - if (unlikely(dma_mapping_error(&pdev->dev, sg->dma_addr))) { - pr_err("map sgl failed, sg %d, %u.\n", i, sg->len); - if (i) - sgl_unmap(pdev, sgl, i, dir); - return -EIO; - } - sg->dma_addr += sg->offset; - } - - return 0; -} - -/*****************************************************************************/ -/** - * qdma_request_submit() - submit a scatter-gather list of data for dma - * operation (for both read and write) - * This is a callback function called from upper layer(character device) - * to handle the read/write request on the queues - * - * @param[in] dev_hndl: hndl retured from qdma_device_open() - * @param[in] id: queue index - * @param[in] req: qdma request - * - * @return # of bytes transferred - * @return <0: error - *****************************************************************************/ -ssize_t qdma_request_submit(unsigned long dev_hndl, unsigned long id, - struct qdma_request *req) -{ - struct xlnx_dma_dev *xdev = (struct xlnx_dma_dev *)dev_hndl; - struct qdma_descq *descq; - struct qdma_sgt_req_cb *cb; - enum dma_data_direction dir; - int wait = 0; - int rv = 0; - - /** make sure that the dev_hndl passed is Valid */ - if (!xdev) { - pr_err("dev_hndl is NULL"); - return -EINVAL; - } - - if (xdev_check_hndl(__func__, xdev->conf.pdev, dev_hndl) < 0) { - pr_err("Invalid dev_hndl passed"); - return -EINVAL; - } - - if (!req) { - pr_err("req is NULL"); - return -EINVAL; - } - - wait = req->fp_done ? 0 : 1; - - descq = qdma_device_get_descq_by_id(xdev, id, NULL, 0, 1); - if (!descq) { - pr_err("Invalid qid(%ld)", id); - return -EINVAL; - } - - if (descq->conf.q_type == Q_CMPT) { - pr_err("Error : Transfer initiated on completion queue\n"); - return -EINVAL; - } - - cb = qdma_req_cb_get(req); - - pr_debug("%s %s-%s, data len %u, sg cnt %u. ping_pong_en=%d\n", - descq->conf.name, descq->conf.st ? "ST" : "MM", - (descq->conf.q_type == Q_C2H) ? "C2H" : "H2C", - req->count, req->sgcnt, descq->conf.ping_pong_en); - - /** Identify the direction of the transfer */ - dir = (descq->conf.q_type == Q_C2H) ? DMA_FROM_DEVICE : DMA_TO_DEVICE; - - /** If write request is given on the C2H direction - * OR, a read request given on non C2H direction - * then, its an invalid request, return error in this case - */ - if ((req->write && (descq->conf.q_type != Q_H2C)) || - (!req->write && (descq->conf.q_type != Q_C2H))) { - pr_err("%s: bad direction, %c.\n", - descq->conf.name, req->write ? 'W' : 'R'); - return -EINVAL; - } - - /** Reset the local cb request with 0's */ - memset(cb, 0, QDMA_REQ_OPAQUE_SIZE); - /** Initialize the wait queue */ - qdma_waitq_init(&cb->wq); - - pr_debug("%s: data len %u, ep 0x%llx, sgl 0x%p, sgl cnt %u, tm %u ms.\n", - descq->conf.name, req->count, req->ep_addr, req->sgl, - req->sgcnt, req->timeout_ms); - - /** If the request is streaming mode C2H, invoke the - * handler to perform the read operation - */ - if (descq->conf.st && (descq->conf.q_type == Q_C2H)) - return qdma_request_submit_st_c2h(xdev, descq, req); - - if (!req->dma_mapped) { - rv = sgl_map(xdev->conf.pdev, req->sgl, req->sgcnt, dir); - if (rv < 0) { - pr_err("%s map sgl %u failed, %u.\n", - descq->conf.name, req->sgcnt, req->count); - goto unmap_sgl; - } - cb->unmap_needed = 1; - } - - lock_descq(descq); - /** if the descq is already in online state*/ - if (descq->q_state != Q_STATE_ONLINE) { - unlock_descq(descq); - pr_err("%s descq %s NOT online.\n", - xdev->conf.name, descq->conf.name); - rv = -EINVAL; - goto unmap_sgl; - } - qdma_work_queue_add(descq, cb); - unlock_descq(descq); - - pr_debug("%s: cb 0x%p submitted.\n", descq->conf.name, cb); - - qdma_descq_proc_sgt_request(descq); - - if (!wait) - return 0; - - rv = qdma_request_wait_for_cmpl(xdev, descq, req); - if (rv < 0) - goto unmap_sgl; - - return cb->offset; - -unmap_sgl: - if (!req->dma_mapped) - sgl_unmap(xdev->conf.pdev, req->sgl, req->sgcnt, dir); - - return rv; -} - -/*****************************************************************************/ -/** - * qdma_batch_request_submit() - submit a batch of scatter-gather list of data - * for dma operation (for both read and write) - * This is a callback function called from upper layer(character device) - * to handle the read/write request on the queues - * - * @param[in] dev_hndl: hndl retured from qdma_device_open() - * @param[in] id: queue index - * @param[in] count: Number of qdma requests - * @param[in] reqv: qdma request vector - * - * @return # of bytes transferred - * @return <0: error - *****************************************************************************/ -ssize_t qdma_batch_request_submit(unsigned long dev_hndl, unsigned long id, - unsigned long count, struct qdma_request **reqv) -{ - struct xlnx_dma_dev *xdev = (struct xlnx_dma_dev *)dev_hndl; - struct qdma_descq *descq; - struct qdma_sgt_req_cb *cb; - enum dma_data_direction dir; - int rv = 0; - unsigned long i; - struct qdma_request *req; - int st_c2h = 0; - - /** make sure that the dev_hndl passed is Valid */ - if (!xdev) { - pr_err("dev_hndl is NULL"); - return -EINVAL; - } - - if (xdev_check_hndl(__func__, xdev->conf.pdev, dev_hndl) < 0) { - pr_err("Invalid dev_hndl passed"); - return -EINVAL; - } - - if (!reqv) { - pr_err("reqv is NULL"); - return -EINVAL; - } - - descq = qdma_device_get_descq_by_id(xdev, id, NULL, 0, 0); - if (!descq) { - pr_err("Invalid qid(%ld)", id); - return -EINVAL; - } - - if (descq->conf.q_type == Q_CMPT) { - pr_err("Error : Transfer initiated on completion queue\n"); - return -EINVAL; - } - - st_c2h = (descq->conf.st && (descq->conf.q_type == Q_C2H)) ? 1 : 0; - - /** Identify the direction of the transfer */ - dir = (descq->conf.q_type == Q_C2H) ? DMA_FROM_DEVICE : DMA_TO_DEVICE; - - req = reqv[0]; - /** If write request is given on the C2H direction - * OR, a read request given on non C2H direction - * then, its an invalid request, return error in this case - */ - if ((req->write && (descq->conf.q_type != Q_H2C)) - || (!req->write && (descq->conf.q_type != Q_C2H))) { - pr_err("%s: bad direction, %c.\n", descq->conf.name, - req->write ? 'W' : 'R'); - return -EINVAL; - } - if (!req->fp_done) { - pr_err("%s: missing fp_done.\n", descq->conf.name); - return -EINVAL; - } - - if (st_c2h) { - for (i = 0; i < count; i++) { - req = reqv[i]; - cb = qdma_req_cb_get(req); - /** Reset the local cb request with 0's */ - memset(cb, 0, QDMA_REQ_OPAQUE_SIZE); - - rv = qdma_request_submit_st_c2h(xdev, descq, req); - if ((rv < 0) || (rv == req->count)) - req->fp_done(req, rv, rv); - } - - return 0; - - } else { - struct pci_dev *pdev = xdev->conf.pdev; - - for (i = 0; i < count; i++) { - req = reqv[i]; - cb = qdma_req_cb_get(req); - /** Reset the local cb request with 0's */ - memset(cb, 0, QDMA_REQ_OPAQUE_SIZE); - - if (!req->dma_mapped) { - rv = sgl_map(pdev, req->sgl, req->sgcnt, dir); - if (unlikely(rv < 0)) { - pr_err("%s map sgl %u failed, %u.\n", - descq->conf.name, - req->sgcnt, - req->count); - req->fp_done(req, 0, rv); - } - cb->unmap_needed = 1; - } - } - } - - lock_descq(descq); - /** if the descq is already in online state*/ - if (unlikely(descq->q_state != Q_STATE_ONLINE)) { - unlock_descq(descq); - pr_err("%s descq %s NOT online.\n", xdev->conf.name, - descq->conf.name); - return -EINVAL; - } - - for (i = 0; i < count; i++) { - req = reqv[i]; - cb = qdma_req_cb_get(req); - - list_add_tail(&cb->list, &descq->work_list); - } - unlock_descq(descq); - - qdma_descq_proc_sgt_request(descq); - - return 0; -} - -#ifdef TANDEM_BOOT_SUPPORTED -/*****************************************************************************/ -/** - * qdma_init_st_ctxt() initialize the QDMA ST context - * - * @param dev_hndl dev_hndl retunred from qdma_device_open() - * @param buflen input buffer length - * @param buf error message buffer, can be NULL/0 (i.e., optional - * - * @return 0: success - * @return <0: error - *****************************************************************************/ -int qdma_init_st_ctxt(unsigned long dev_hndl, char *buf, int buflen) -{ - struct xlnx_dma_dev *xdev = (struct xlnx_dma_dev *)dev_hndl; - int rv; - - /** make sure that input buffer is not empty, else return error */ - if (!buf || !buflen) { - pr_err("invalid argument: buf=%p, buflen=%d\n", buf, buflen); - return -EINVAL; - } - - /** make sure that the dev_hndl passed is Valid */ - if (!xdev) { - pr_err("dev_hndl is NULL"); - snprintf(buf, buflen, "dev_hndl is NULL"); - return -EINVAL; - } - - if (xdev_check_hndl(__func__, xdev->conf.pdev, dev_hndl) < 0) { - pr_err("Invalid dev_hndl passed"); - snprintf(buf, buflen, "Invalid dev_hndl passed\n"); - return -EINVAL; - } - - if ((xdev->version_info.ip_type == QDMA_VERSAL_HARD_IP) && - ((xdev->version_info.device_type == QDMA_DEVICE_VERSAL_CPM4) || - (xdev->version_info.device_type == QDMA_DEVICE_VERSAL_CPM5))) { - if (xdev->hw.qdma_init_st_ctxt == NULL) { - pr_err("Err: Feature not supported\n"); - snprintf(buf, buflen, "Err: Feature not supported\n"); - return -EPERM; - } - - rv = xdev->hw.qdma_init_st_ctxt((void *)dev_hndl); - - if (rv == QDMA_SUCCESS) { - snprintf(buf, buflen, - "qdma%05x : Steaming Enabled successfully\n", - xdev->conf.bdf); - pr_info("Steaming Enabled successfully\n"); - } else { - snprintf(buf, buflen, - "qdma%05x : Failed to Enable Steaming\n", - xdev->conf.bdf); - pr_info("Failed to Enable Steaming\n"); - return -EINVAL; - } - } else { - snprintf(buf, buflen, - "qdma%05x : Steaming Enabled during Initialization\n", - xdev->conf.bdf); - pr_info("Steaming Enabled during Initialization\n"); - } - - return rv; -} -#endif - -/*****************************************************************************/ -/** - * libqdma_init() initialize the QDMA core library - * - * @param[in] num_threads - number of threads to be created each for request - * processing and writeback processing - * - * @return 0: success - * @return <0: error - *****************************************************************************/ -int libqdma_init(unsigned int num_threads, void *debugfs_root) -{ - - int ret; - /** Make sure that the size of qdma scatter gather request size - * is less than the QDMA_REQ_OPAQUE_SIZE - * If not, return error - */ - if (sizeof(struct qdma_sgt_req_cb) > QDMA_REQ_OPAQUE_SIZE) { - pr_err("dma req. opaque data size too big %lu > %lu.\n", - sizeof(struct qdma_sgt_req_cb), QDMA_REQ_OPAQUE_SIZE); - return -1; - } - if (sizeof(struct qdma_flq) > QDMA_FLQ_SIZE) { - pr_err("qdma flq data size too big %lu > %d", - sizeof(struct qdma_flq), QDMA_FLQ_SIZE); - return -1; - } - - /** Create the qdma threads */ - ret = qdma_threads_create(num_threads); - if (ret < 0) { - pr_err("qdma_threads_create failed for num_thread=%d", - num_threads); - return ret; - } -#ifdef DEBUGFS - - if (debugfs_root) { - qdma_debugfs_root = debugfs_root; - qdma_debufs_cleanup = false; - return 0; - } - - ret = qdma_debugfs_init(&qdma_debugfs_root); - if (ret < 0) { - pr_err("qdma_debugfs_init failed for num_thread=%d", - num_threads); - return ret; - } -#endif - return 0; -} - -/*****************************************************************************/ -/** - * libqdma_exit() cleanup the QDMA core library before exiting - * - * @return none - *****************************************************************************/ -void libqdma_exit(void) -{ -#ifdef DEBUGFS - if (qdma_debufs_cleanup) - qdma_debugfs_exit(qdma_debugfs_root); -#endif - /** Destroy the qdma threads */ - qdma_threads_destroy(); -} - -#ifdef __LIBQDMA_MOD__ -/** for module support only */ -#include "version.h" - -static char version[] = - DRV_MODULE_DESC " " DRV_MODULE_NAME " v" DRV_MODULE_VERSION "\n"; - -MODULE_AUTHOR("Xilinx, Inc."); -MODULE_DESCRIPTION(DRV_MODULE_DESC); -MODULE_VERSION(DRV_MODULE_VERSION); -MODULE_LICENSE("Dual BSD/GPL"); - -/*****************************************************************************/ -/** - * libqdma_mod_init() libqdma module initialization routine - * - * Returns: none - *****************************************************************************/ -static int __init libqdma_mod_init(void) -{ - pr_info("%s", version); - - /** invoke libqdma_init to initialize the libqdma library */ - return libqdma_init(); -} - -/*****************************************************************************/ -/** - * libqdma_mod_exit() cleanup the QDMA core library before exiting - * - * Returns: none - *****************************************************************************/ -static void __exit libqdma_mod_exit(void) -{ - /** invoke libqdma_exit to cleanup the libqdma library resources */ - libqdma_exit(); -} - -module_init(libqdma_mod_init); -module_exit(libqdma_mod_exit); -#endif /* ifdef __LIBQDMA_MOD__ */ diff --git a/QDMA/linux-kernel/driver/libqdma/libqdma_export.h b/QDMA/linux-kernel/driver/libqdma/libqdma_export.h deleted file mode 100755 index fd6044667..000000000 --- a/QDMA/linux-kernel/driver/libqdma/libqdma_export.h +++ /dev/null @@ -1,1698 +0,0 @@ -/* - * This file is part of the Xilinx DMA IP Core driver for Linux - * - * Copyright (c) 2017-2022, Xilinx, Inc. All rights reserved. - * Copyright (c) 2022, Advanced Micro Devices, Inc. All rights reserved. - * - * This source code is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * The full GNU General Public License is included in this distribution in - * the file called "COPYING". - */ - -#ifndef __LIBQDMA_EXPORT_API_H__ -#define __LIBQDMA_EXPORT_API_H__ - - -/** - * @file libqdma_export.h - * - * Xilinx QDMA Library Interface Definitions - * - * Header file *libqdma_export.h* defines data structures and function - * signatures exported by Xilinx QDMA (libqdma) Library. - * libqdma is part of Xilinx QDMA Linux Driver. - * - * libqdma exports the configuration and control APIs for device and - * queue management and data processing APIs. Configuration APIs - * shall not be invoked in interrupt context by upper layers. - */ - -#include -#include -#include "libqdma_config.h" -#include "qdma_access_export.h" -#include "qdma_compat.h" - - -/** @defgroup libqdma_enums Enumerations - */ -/** @defgroup libqdma_struct Data Structures - */ -/** - * @defgroup libqdma_defines Definitions - * @{ - */ - -/** - * Invalid QDMA function number - */ -#define QDMA_FUNC_ID_INVALID 0xFFFF - -/** - * QDMA_DEV_NAME_MAXLEN - Maxinum length of the QDMA device name - */ -#define QDMA_DEV_NAME_MAXLEN 32 - -/** - * DEVICE_VERSION_INFO_STR_LENGTH - QDMA HW version string array length, - * change this if QDMA_HW_VERSION_STRING_LEN is changed in access code - */ -#define DEVICE_VERSION_INFO_STR_LENGTH (34) - -/** - * QDMA_QUEUE_NAME_MAXLEN - Maximum queue name length - */ -#define QDMA_QUEUE_NAME_MAXLEN 32 - -/** - * QDMA_QUEUE_IDX_INVALID - Invalid queue index - */ -#define QDMA_QUEUE_IDX_INVALID 0xFFFF - -/** - * QDMA_QUEUE_VEC_INVALID - Invalid MSIx vector index - */ -#define QDMA_QUEUE_VEC_INVALID 0xFF - -/** - * QDMA_REQ_OPAQUE_SIZE - Maximum request length. - * QDMA_REQ_OPAQUE_SIZE varies according to kernel params. - * Size of spinlock_t varies when spinlock debug params are enabled. - */ -#define QDMA_REQ_OPAQUE_SIZE (56 + sizeof(qdma_wait_queue)) - -/** - * QDMA_UDD_MAXLEN - Maximum length of the user defined data - */ -#define QDMA_UDD_MAXLEN 32 - -/** @} */ - - -/** - * Per queue DMA AXI Interface option - * @ingroup libqdma_enums - */ -enum qdma_q_mode { - /** AXI Memory Mapped Mode */ - QDMA_Q_MODE_MM, - /** AXI Stream Mode */ - QDMA_Q_MODE_ST -}; - -/** - * Direction of the queue - * @ingroup libqdma_enums - */ -enum qdma_q_dir { - /** host to card */ - QDMA_Q_DIR_H2C, - /** card to host */ - QDMA_Q_DIR_C2H -}; - - -/** - * PF/VF qdma driver modes - * - * QDMA PF/VF drivers can be loaded in one of these modes. - * Mode options is exposed as a user configurable module parameter - * @ingroup libqdma_enums - * - */ -enum qdma_drv_mode { - /** - * @param AUTO_MODE Auto mode is mix of Poll and Interrupt Aggregation - * mode. Driver polls for the write back status updates. Interrupt - * aggregation is used for processing the completion ring - */ - AUTO_MODE, - /** - * @param POLL_MODE In Poll Mode, Software polls for the write back - * completions (Status Descriptor Write Back) - */ - POLL_MODE, - /** - * @param DIRECT_INTR_MODE Direct Interrupt mode, each queue is - * assigned to one of the available interrupt vectors in a round robin - * fashion to service the requests. Interrupt is raised by the HW upon - * receiving the completions and software reads the completion status. - */ - DIRECT_INTR_MODE, - /** - * @param INDIRECT_INTR_MODE In Indirect Interrupt mode or Interrupt - * Aggregation mode, each vector has an associated Interrupt - * Aggregation Ring. The QID and status of queues requiring service - * are written into the Interrupt Aggregation Ring. When a PCIe MSI-X - * interrupt is received by the Host, the software reads the Interrupt - * Aggregation Ring to determine which queue needs service. Mapping of - * queues to vectors is programmable - */ - INDIRECT_INTR_MODE, - /** - * @param LEGACY_INTR_MODE Driver is inserted in legacy interrupt mode - * Software serves status updates upon receiving the legacy interrupt - */ - LEGACY_INTR_MODE -}; - -/** - * Queue direction types - * @ingroup libqdma_enums - * - */ -enum queue_type_t { - /** host to card */ - Q_H2C, - /** card to host */ - Q_C2H, - /** cmpt queue*/ - Q_CMPT, - /** Both H2C and C2H directions*/ - Q_H2C_C2H, -}; - - -/** - * Qdma interrupt ring size selection - * - * Each interrupt vector can be associated with 1 or more interrupt rings. - * The software can choose 8 different interrupt ring sizes. The ring size - * for each vector is programmed during interrupt context programming - * @ingroup libqdma_enums - * - */ -enum intr_ring_size_sel { - /** accommodates 512 entries */ - INTR_RING_SZ_4KB = 0, - /** accommodates 1024 entries */ - INTR_RING_SZ_8KB, - /** accommodates 1536 entries */ - INTR_RING_SZ_12KB, - /** accommodates 2048 entries */ - INTR_RING_SZ_16KB, - /** accommodates 2560 entries */ - INTR_RING_SZ_20KB, - /** accommodates 3072 entries */ - INTR_RING_SZ_24KB, - /** accommodates 3584 entries */ - INTR_RING_SZ_28KB, - /** accommodates 4096 entries */ - INTR_RING_SZ_32KB, -}; - -/** - * Qdma function states - * - * Each PF/VF device can be configured with 0 or more number of queues. - * When the queue is not assigned to any function, function is in unfonfigured - * state. Sysfs interface enables the users to configure the number of - * queues to different functions. Upon adding the queues, function moves to - * user configured state. - * @ingroup libqdma_enums - * - */ -enum qdma_dev_qmax_state { - /** @param QMAX_CFG_UNCONFIGURED queue max not configured */ - QMAX_CFG_UNCONFIGURED, - /** - * @param QMAX_CFG_INITIAL queue max configured with - * initial default values - */ - QMAX_CFG_INITIAL, - /** - * @param QMAX_CFG_USER queue max configured from - * sysfs as per user choice - */ - QMAX_CFG_USER, -}; - -/** - * Descriptor sizes - * @ingroup libqdma_enums - * - */ -enum cmpt_desc_sz_t { - /** completion size 8B */ - CMPT_DESC_SZ_8B = 0, - /** completion size 16B */ - CMPT_DESC_SZ_16B, - /** completion size 32B */ - CMPT_DESC_SZ_32B, - /** completion size 64B */ - CMPT_DESC_SZ_64B -}; - -/** - * Descriptor sizes - * @ingroup libqdma_enums - * - */ -enum desc_sz_t { - /** descriptor size 8B */ - DESC_SZ_8B = 0, - /** descriptor size 16B */ - DESC_SZ_16B, - /** descriptor size 32B */ - DESC_SZ_32B, - /** descriptor size 64B */ - DESC_SZ_64B -}; - -/** - * Trigger modes - * @ingroup libqdma_enums - * - */ -enum tigger_mode_t { - /** disable trigger mode */ - TRIG_MODE_DISABLE, - /** any trigger mode */ - TRIG_MODE_ANY, - /** counter trigger mode */ - TRIG_MODE_COUNTER, - /** trigger mode of user choice */ - TRIG_MODE_USER, - /** timer trigger mode */ - TRIG_MODE_TIMER, - /** timer and counter combo trigger mode */ - TRIG_MODE_COMBO, -}; - -/** - * Queue can be in one of the following states - * @ingroup libqdma_enums - * - */ -enum q_state_t { - /** @param Q_STATE_DISABLED Queue is not taken */ - Q_STATE_DISABLED = 0, - /** @param Q_STATE_ENABLED Assigned/taken. Partial config is done */ - Q_STATE_ENABLED, - /** - * @param Q_STATE_ONLINE Resource/context is initialized for the queue - * and is available for data consumption - */ - Q_STATE_ONLINE, -}; - -/** - * Structure to hold the driver name and mode - * - * Mode can be set for each PF or VF group using module parameters - * Refer enum qdma_drv_mode for different mode options - * @ingroup libqdma_struct - * - */ -struct drv_mode_name { - /** Mode of the function */ - enum qdma_drv_mode drv_mode; - /** Driver Name */ - char name[20]; -}; - - -/** - * Queue type - * - * Look up table for name of the queue type and enum - * @ingroup libqdma_struct - * - */ -struct qdma_q_type { - /** Queue type name */ - const char *name; - /** Queue type */ - enum queue_type_t q_type; -}; - - -/** - * Completion entry format - * - * Completion Entry is user logic dependent - * Current SW supported the following completion entry format - * @ingroup libqdma_struct - * - */ -struct qdma_ul_cmpt_info { - union { - /** Flag bits */ - u8 fbits; - struct cmpl_flag { - /** Format of the entry */ - u8 format:1; - /** Indicates the validity of the entry */ - u8 color:1; - /** Indicates the error status */ - u8 err:1; - /** Indicates the descriptor used status */ - u8 desc_used:1; - /** Indicates the end of transfer */ - u8 eot:1; - /** Filler bits */ - u8 filler:3; - } f; - }; - /** Reserved filed added for structure alignment */ - u8 rsvd; - /** Length of the completion entry */ - u16 len; - /** Producer Index */ - unsigned int pidx; - /** Completion entry */ - __be64 *entry; -}; - -/** - * Externel structure definition mode_name_list - * - * @ingroup libqdma_struct - */ -extern struct drv_mode_name mode_name_list[]; - -/** - * Externel structure definition q_type_list - * - * @ingroup libqdma_struct - */ -extern struct qdma_q_type q_type_list[]; - -/** - * Forward declaration for struct pci_dev - * - * @ingroup libqdma_struct - */ -struct pci_dev; - -/** - * Defines the per-device qdma property. - * - * @note if any of the max requested is less than supported, the value will - * be updated - * @ingroup libqdma_struct - */ -struct qdma_dev_conf { - /** pointer to pci_dev */ - struct pci_dev *pdev; - /** Maximum number of queue pairs per device */ - u32 qsets_max; - /** Reserved */ - unsigned short rsvd2; - /** - * Indicates whether zero length DMA is allowed or not - */ - u8 zerolen_dma:1; - /** - * Indicates whether the current pf - * is master_pf or not - */ - u8 master_pf:1; - /** - * moderate interrupt generation - */ - u8 intr_moderation:1; - /** Reserved1 */ - u8 rsvd1:5; - /** - * Maximum number of virtual functions for - * current physical function - */ - u8 vf_max; - /** Interrupt ring size */ - u8 intr_rngsz; - /** - * interrupt: - * - MSI-X only - * max of QDMA_DEV_MSIX_VEC_MAX per function, 32 in Versal - * - 1 vector is reserved for user interrupt - * - 1 vector is reserved mailbox - * - 1 vector on pf0 is reserved for error interrupt - * - the remaining vectors will be used for queues - */ - - /** - * max. of vectors used for queues. - * libqdma update w/ actual # - */ - u16 msix_qvec_max; - /** Max user msix vectors */ - u16 user_msix_qvec_max; - /** Max data msix vectors */ - u16 data_msix_qvec_max; - /** upper layer data, i.e. callback data */ - unsigned long uld; - /** qdma driver mode */ - enum qdma_drv_mode qdma_drv_mode; - /** - * an unique string to identify the dev. - * current format: qdma[pf|vf][idx] filled in by libqdma - */ - char name[QDMA_DEV_NAME_MAXLEN]; - - /** dma config bar #, < 0 not present */ - char bar_num_config; - /** AXI Master Lite(user bar) */ - char bar_num_user; - /** AXI Bridge Master(bypass bar) */ - char bar_num_bypass; - /** queue base for this function */ - int qsets_base; - /** device index */ - u32 bdf; - /** index of device in device list */ - u32 idx; -#ifndef __XRT__ - /** - * @brief user interrupt, if null, default libqdma handler is used - * - * @param dev_hndl Device Handler - * @param uld upper layer data, i.e. callback data - */ - void (*fp_user_isr_handler)(unsigned long dev_hndl, unsigned long uld); -#else - /** - * @brief user interrupt, if null, default libqdma handler is used - * - * @param dev_hndl Device Handler - * @param irq_index Interrupt index - * @param uld upper layer data, i.e. callback data - */ - void (*fp_user_isr_handler)(unsigned long dev_hndl, int irq_index, - unsigned long uld); -#endif - /** - * @brief Q interrupt top, - * per-device addtional handling code - * - * @param dev_hndl Device Handler - * @param uld upper layer data, i.e. callback data - */ - void (*fp_q_isr_top_dev)(unsigned long dev_hndl, unsigned long uld); - - /** - * @brief for freeing any resources in FLR process - * - * @param dev_hndl Device Handler - */ - void (*fp_flr_free_resource)(unsigned long dev_hndl); - - /** - * root path for debugfs - */ - void *debugfs_dev_root; -}; - -/** - * defines the per-device version information - * @ingroup libqdma_struct - * - */ -struct qdma_version_info { - /** Version string */ - char rtl_version_str[DEVICE_VERSION_INFO_STR_LENGTH]; - /** Release string */ - char vivado_release_str[DEVICE_VERSION_INFO_STR_LENGTH]; - /** IP version string */ - char ip_str[DEVICE_VERSION_INFO_STR_LENGTH]; - /** Qdma device type string */ - char device_type_str[DEVICE_VERSION_INFO_STR_LENGTH]; -}; - -/** - * global CSR configuration - * @ingroup libqdma_struct - * - */ -struct global_csr_conf { - /** Descriptor ring size ie. queue depth */ - unsigned int ring_sz[QDMA_GLOBAL_CSR_ARRAY_SZ]; - /** C2H timer count list */ - unsigned int c2h_timer_cnt[QDMA_GLOBAL_CSR_ARRAY_SZ]; - /** C2H counter threshold list*/ - unsigned int c2h_cnt_th[QDMA_GLOBAL_CSR_ARRAY_SZ]; - /** C2H buffer size list */ - unsigned int c2h_buf_sz[QDMA_GLOBAL_CSR_ARRAY_SZ]; - /** Writeback interval */ - unsigned int wb_intvl; -}; - - -/** - * qdma scatter gather request - * @ingroup libqdma_struct - * - */ -struct qdma_sw_sg { - /** pointer to next page */ - struct qdma_sw_sg *next; - /** pointer to current page */ - struct page *pg; - /** offset in current page */ - unsigned int offset; - /** length of the page */ - unsigned int len; - /** dma address of the allocated page */ - dma_addr_t dma_addr; -}; - -/** struct qdma_request forward declaration - * @ingroup libqdma_struct - */ -struct qdma_request; - -/** - * qdma configuration parameters - * - * qdma_queue_conf defines the per-dma Q property. - * if any of the max requested is less than supported, the value will - * be updated - * @ingroup libqdma_struct - * - */ -struct qdma_queue_conf { - /** - * @param qidx 0xFFFF: libqdma choose the queue idx 0 ~ - * (qdma_dev_conf.qsets_max - 1) the calling function choose the - * queue idx - */ - u32 qidx:24; - /** @note config flags: byte #1 */ - /** Indicates the streaming mode */ - u32 st:1; - /** queue_type_t */ - u32 q_type:2; - /** SDx only: inter-kernel communication pipe */ - u32 pipe:1; - /** poll or interrupt */ - u32 irq_en:1; - - /** descriptor ring */ - /** global_csr_conf.ringsz[N] */ - u32 desc_rng_sz_idx:4; - - /** @note config flags: byte #2 */ - /** writeback enable, disabled for ST C2H */ - u8 wb_status_en:1; - /** sw context.cmpl_status_acc_en */ - u8 cmpl_status_acc_en:1; - /** sw context.cmpl_stauts_pend_chk */ - u8 cmpl_status_pend_chk:1; - /** send descriptor to bypass out */ - u8 desc_bypass:1; - /** descriptor prefetch enable control */ - u8 pfetch_en:1; - /** sw context.frcd_en[32] */ - u8 fetch_credit:1; - /** - * @param st_pkt_mode SDx only: ST packet mode - * (i.e., with TLAST to identify the packet boundary) - */ - u8 st_pkt_mode:1; - - /** @note config flags: byte #3 */ - /** global_csr_conf.c2h_buf_sz[N] */ - u8 c2h_buf_sz_idx:4; - - /** ST C2H Completion/Writeback ring */ - /** global_csr_conf.ringsz[N] */ - u8 cmpl_rng_sz_idx:4; - - /** @note config flags: byte #4 */ - /** C2H ST cmpt + immediate data, desc_sz_t */ - u8 cmpl_desc_sz:2; - /** enable status desc. for CMPT */ - u8 cmpl_stat_en:1; - /** C2H Completion entry user-defined data */ - u8 cmpl_udd_en:1; - /** global_csr_conf.c2h_timer_cnt[N] */ - u8 cmpl_timer_idx:4; - - /** @note config flags byte #5 */ - /** global_csr_conf.c2h_cnt_th[N] */ - u8 cmpl_cnt_th_idx:4; - /** tigger_mode_t */ - u8 cmpl_trig_mode:3; - /** enable interrupt for CMPT */ - u8 cmpl_en_intr:1; - - /** @note config flags byte #6 */ - /** SW Context desc size, desc_sz_t */ - u8 sw_desc_sz:2; - /** prefetch bypass en */ - u8 pfetch_bypass:1; - /** OVF_DIS C2H ST over flow disable */ - u8 cmpl_ovf_chk_dis:1; - /** Port ID */ - u8 port_id:3; - /** Address Translation */ - u8 at:1; - /** Adaptive rx counter threshold */ - u8 adaptive_rx:1; - /** optimize for latency */ - u8 latency_optimize:1; - /** Disable pidx initialiaztion for ST C2H */ - u8 init_pidx_dis:1; - - /** MM Channel */ - u8 mm_channel:1; - - /** user provided per-Q irq handler */ - unsigned long quld; /* set by user for per Q data */ - /** acummulate PIDX to batch packets */ - u32 pidx_acc:8; - /** - * @brief Q interrupt top, per-queue additional handling - * code for example, network rx napi_schedule(&Q->napi) - * - * @param qhndl Queue handle - * @param quld Queue ID - * - */ - void (*fp_descq_isr_top)(unsigned long qhndl, unsigned long quld); - - /** - * @brief optional rx packet handler: - * called from irq BH (i.e.qdma_queue_service_bh()) - * - * @param qhndl Queue handle - * @param quld Queue ID - * @param len Packet Length - * @param sgcnt scatter gathher list count - * @param sgl packet data in scatter-gather list - * @param udd user defined data in the completion entry - * - * @note - * a. do NOT modify any field of sgl - * b. if zero copy, do a get_page() to prevent page freeing - * c. do loop through the sgl with sg->next and stop - * at sgcnt. the last sg may not have sg->next = NULL - * - * @returns - * 0 to allow libqdma free/re-task the sgl - * < 0, libqdma will keep the packet for processing again - * - * @details - * A single packet could contain: - * in the case of c2h_udd_en = 1: - * - * udd only (udd valid, sgcnt = 0, sgl = NULL), or - * udd + packet data in the case of c2h_udd_en = 0: - * packet data (udd = NULL, sgcnt > 0 and sgl valid) - * - */ - int (*fp_descq_c2h_packet)(unsigned long qhndl, unsigned long quld, - unsigned int len, unsigned int sgcnt, - struct qdma_sw_sg *sgl, void *udd); - /** - * @brief fill the all the descriptors required for - * transfer - * @param q_hndl handle with which bypass module can request back - * info from libqdma - * - * @param q_mode mode in which q is initialized - * @param q_dir direction in which q is initialized - * @param sgcnt number of scatter gather entries for this request - * @param sgl list of scatter gather entries - * - * @returns On calling this API, bypass module can request for - * descriptor using qdma_q_desc_get and set up as many descriptors - * as required for each scatter gather entry. If descriptors required - * are not available, it can return the number of sgcnt addressed - * till now and return <0 in case of any failure - */ - int (*fp_bypass_desc_fill)(void *q_hndl, enum qdma_q_mode q_mode, - enum qdma_q_dir, struct qdma_request *req); - /** - * @brief parse cmpt entry in bypass mode - * - * @param cmpt_entry cmpt entry descriptor - * @param cmpt_info parsed bypass related info from cmpt_entry - * - * @returns 0 for success - */ - int (*fp_proc_ul_cmpt_entry)(void *cmpt_entry, - struct qdma_ul_cmpt_info *cmpt_info); - - /** @note Following fileds are filled by libqdma */ - /** name of the qdma device */ - char name[QDMA_QUEUE_NAME_MAXLEN]; - /** ring size of the queue */ - unsigned int rngsz; - /** completion ring size of the queue */ - unsigned int rngsz_cmpt; - /** C2H buffer size */ - unsigned int c2h_bufsz; - /** Ping Pong measurement */ - u8 ping_pong_en:1; - /** Keyhole Aperture Size */ - u32 aperture_size; -}; - -/** - * display queue state in a string buffer - * @ingroup libqdma_struct - * - */ -struct qdma_q_state { - /** current q state */ - enum q_state_t qstate; - /** - * 0xFFFF: libqdma choose the queue idx 0 ~ - * (qdma_dev_conf.qsets_max - 1) the calling function choose the - * queue idx - */ - u32 qidx:24; - /** Indicates the streaming mode */ - u32 st:1; - /** queue type */ - enum queue_type_t q_type; -}; - - -/** - * qdma request for read or write - * @ingroup libqdma_struct - * - */ -struct qdma_request { - /** private to the dma driver, do NOT touch */ - unsigned char opaque[QDMA_REQ_OPAQUE_SIZE]; - /** - * filled in by the calling function - * for the calling function - */ - unsigned long uld_data; - /** set fp_done for non-blocking mode */ - int (*fp_done)(struct qdma_request *req, unsigned int bytes_done, - int err); - /** timeout in mili-seconds, 0 - no timeout */ - unsigned int timeout_ms; - /** total data size */ - unsigned int count; - /** MM only, DDR/BRAM memory addr */ - u64 ep_addr; - /** flag to indicate if memcpy is required */ - u8 no_memcpy:1; - /** if write to the device */ - u8 write:1; - /** if sgt is already dma mapped */ - u8 dma_mapped:1; - /** indicates end of transfer towards user kernel */ - u8 h2c_eot:1; - /** state check disbaled in queue pkt API */ - u8 check_qstate_disabled:1; - u8 _pad:3; - /** user defined data present */ - u8 udd_len; - /** number of scatter-gather entries < 64K */ - unsigned int sgcnt; - /** scatter-gather list of data bufs */ - struct qdma_sw_sg *sgl; - /** udd data */ - u8 udd[QDMA_UDD_MAXLEN]; -}; - -/** - * Completion control - * @ingroup libqdma_struct - */ -struct qdma_cmpl_ctrl { - /** global_csr_conf.c2h_cnt_th[N] */ - u8 cnt_th_idx:4; - /** global_csr_conf.c2h_timer_cnt[N] */ - u8 timer_idx:4; - /** tigger_mode */ - u8 trigger_mode:3; - /** enable status desc. for CMPT */ - u8 en_stat_desc:1; - /** enable interrupt for CMPT */ - u8 cmpl_en_intr:1; -}; - - -/** - * QDMA queue count - * @ingroup libqdma_struct - */ -struct qdma_queue_count { - /** H2C queue count */ - u32 h2c_qcnt; - /** C2H queue count */ - u32 c2h_qcnt; - /** CMPT queue count */ - u32 cmpt_qcnt; -}; - - -/** - * Initializes the QDMA core library - * - * @param num_threads number of threads to be created each for request - * processing and writeback processing - * - * @param debugfs_root root path for debugfs - * - * @returns 0: success <0: error - * - */ -int libqdma_init(unsigned int num_threads, void *debugfs_root); - -/*****************************************************************************/ -/** - * cleanup the QDMA core library before exiting - * - * - *****************************************************************************/ -void libqdma_exit(void); - - -/*****************************************************************************/ -/** - * legacy interrupt init - * - *****************************************************************************/ -void intr_legacy_init(void); - -/*****************************************************************************/ -/** - * Read the pci bars and configure the fpga - * This API should be called from probe() - * - * User interrupt will not be enabled until qdma_user_isr_enable() is called - * - * @param mod_name the module name, used for request_irq - * @param conf device configuration - * @param dev_hndl an opaque handle for libqdma to identify the device - * - * @returns 0 in case of success and <0 in case of error - * - *****************************************************************************/ -int qdma_device_open(const char *mod_name, struct qdma_dev_conf *conf, - unsigned long *dev_hndl); - -/*****************************************************************************/ -/** - * Prepare fpga for removal: disable all interrupts (users - * and qdma) and release all resources.This API should be called from remove() - * - * @param pdev ptr to struct pci_dev - * @param dev_hndl dev_hndl retured from qdma_device_open() - * - * @returns 0 in case of success and <0 in case of error - * - *****************************************************************************/ -int qdma_device_close(struct pci_dev *pdev, unsigned long dev_hndl); - -/*****************************************************************************/ -/** - * Set the device in offline mode - * - * @param pdev ptr to struct pci_dev - * @param dev_hndl dev_hndl retured from qdma_device_open() - * @param reset 0/1 function level reset active or not - * - * @returns 0 for success and <0 for error - * - *****************************************************************************/ -int qdma_device_offline(struct pci_dev *pdev, unsigned long dev_hndl, - int reset); - -/*****************************************************************************/ -/** - * Set the device in online mode and re-initialze it - * - * @param pdev ptr to struct pci_dev - * @param dev_hndl dev_hndl retured from qdma_device_open() - * @param reset 0/1 function level reset active or not - * - * @returns 0 for success and <0 for error - * - *****************************************************************************/ -int qdma_device_online(struct pci_dev *pdev, unsigned long dev_hndl, - int reset); - -/*****************************************************************************/ -/** - * Start pre-flr processing - * - * @param pdev ptr to struct pci_dev - * @param dev_hndl dev_hndl returned from qdma_device_open() - * - * @returns 0 for success and <0 for error - * - *****************************************************************************/ -int qdma_device_flr_quirk_set(struct pci_dev *pdev, unsigned long dev_hndl); - -/*****************************************************************************/ -/** - * Check if pre-flr processing completed - * - * @param pdev ptr to struct pci_dev - * @param dev_hndl dev_hndl retunred from qdma_device_open() - * - * @returns 0 for success <0 for error - * - *****************************************************************************/ -int qdma_device_flr_quirk_check(struct pci_dev *pdev, unsigned long dev_hndl); - -/*****************************************************************************/ -/** - * Retrieve the current device configuration - * - * @param dev_hndl dev_hndl retunred from qdma_device_open() - * @param conf device configuration - * @param buflen input buffer length - * @param buf error message buffer, can be NULL/0 (i.e., optional) - * - * @returns 0 for success and <0 for error - * - *****************************************************************************/ -int qdma_device_get_config(unsigned long dev_hndl, struct qdma_dev_conf *conf, - char *buf, int buflen); - -/*****************************************************************************/ -/** - * Clear device statistics - * - * @param dev_hndl dev_hndl retunred from qdma_device_open() - * - * @returns 0 for success and <0 for error - * - *****************************************************************************/ -int qdma_device_clear_stats(unsigned long dev_hndl); - -/*****************************************************************************/ -/** - * Get mm h2c packets processed - * - * @param dev_hndl dev_hndl retunred from qdma_device_open() - * @param mmh2c_pkts number of mm h2c packets processed - * - *@returns 0 for success and <0 for error - * - *****************************************************************************/ -int qdma_device_get_mmh2c_pkts(unsigned long dev_hndl, - unsigned long long *mmh2c_pkts); - -/*****************************************************************************/ -/** - * Get mm c2h packets processed - * - * @param dev_hndl dev_hndl retunred from qdma_device_open() - * @param mmc2h_pkts number of mm c2h packets processed - * - *@returns 0 for success and <0 for error - * - *****************************************************************************/ -int qdma_device_get_mmc2h_pkts(unsigned long dev_hndl, - unsigned long long *mmc2h_pkts); - -/*****************************************************************************/ -/** - * Get st h2c packets processed - * - * @param dev_hndl dev_hndl retunred from qdma_device_open() - * @param sth2c_pkts number of st h2c packets processed - * - *@returns 0 for success and <0 for error - * - *****************************************************************************/ -int qdma_device_get_sth2c_pkts(unsigned long dev_hndl, - unsigned long long *sth2c_pkts); - -/*****************************************************************************/ -/** - * Get st c2h packets processed - * - * @param dev_hndl dev_hndl retunred from qdma_device_open() - * @param stc2h_pkts number of st c2h packets processed - * - * @returns 0 for success and <0 for error - * - *****************************************************************************/ -int qdma_device_get_stc2h_pkts(unsigned long dev_hndl, - unsigned long long *stc2h_pkts); - -/*****************************************************************************/ -/** - * - * Min latency (in CPU ticks) observed for - * all packets to do H2C-C2H loopback. - * Packet is transmitted in ST H2C direction, the - * user-logic ST Traffic generator is configured to - * loop back the packet in C2H direction. Timestamp - * (in CPU ticks) of the H2C transmission - * is embedded in H2C packet at time of PIDX - * update, then timestamp of the loopback packet - * is taken at time when data interrupt is hit, - * diff is used to measure roundtrip latency. - * - * @param dev_hndl dev_hndl retunred from qdma_device_open() - * @param min_lat Minimum ping pong latency in CPU ticks. Divide with - * the nominal CPU freqeuncy to get latency in NS. - * - * @returns 0 for success and <0 for error - * - *****************************************************************************/ -int qdma_device_get_ping_pong_min_lat(unsigned long dev_hndl, - unsigned long long *min_lat); - -/*****************************************************************************/ -/** - * Max latency (in CPU ticks) observed for - * all packets to do H2C-C2H loopback. - * Packet is transmitted in ST H2C direction, the - * user-logic ST Traffic generator is configured to - * loop back the packet in C2H direction. Timestamp - * (in CPU ticks) of the H2C transmission - * is embedded in H2C packet at time of PIDX - * update, then timestamp of the loopback packet - * is taken at time when data interrupt is hit, - * diff is used to measure roundtrip latency. - * - * @param dev_hndl dev_hndl retunred from qdma_device_open() - * @param max_lat Max ping pong latency in CPU ticks. Divide with the - * nominal CPU freqeuncy to get latency in NS. - * - * @returns 0 for success and <0 for error - * - *****************************************************************************/ -int qdma_device_get_ping_pong_max_lat(unsigned long dev_hndl, - unsigned long long *max_lat); - -/*****************************************************************************/ -/** - * Total latency (in CPU ticks) observed for - * all packets to do H2C-C2H loopback. - * Packet is transmitted in ST H2C direction, the - * user-logic ST Traffic generator is configured to - * loop back the packet in C2H direction. Timestamp - * (in CPU ticks) of the H2C transmission - * is embedded in H2C packet at time of PIDX - * update, then timestamp of the loopback packet - * is taken at time when data interrupt is hit, - * diff is used to measure roundtrip latency. - * - * @param dev_hndl dev_hndl retunred from qdma_device_open() - * @param lat_total Total Ping Pong latency. Divide with total loopback - * C2H packets to get average ping pong latency. Divide further - * with the nominal CPU frequency to get the avg latency in NS. - * - * @returns 0 for success and <0 for error - * - *****************************************************************************/ -int qdma_device_get_ping_pong_tot_lat(unsigned long dev_hndl, - unsigned long long *lat_total); - -/*****************************************************************************/ -/** - * Set the current device configuration - * - * @param dev_hndl dev_hndl returned from qdma_device_open() - * @param conf device configuration to set - * - * @returns 0 for success and <0 for error - * - *****************************************************************************/ -int qdma_device_set_config(unsigned long dev_hndl, struct qdma_dev_conf *conf); - -/*****************************************************************************/ -/** - * Configure sriov - * - * @param pdev ptr to struct pci_dev - * @param dev_hndl dev_hndl returned from qdma_device_open() - * @param num_vfs # of VFs to be instantiated - * - * @returns 0 for success and <0 for error - * - * configures sriov - *****************************************************************************/ -int qdma_device_sriov_config(struct pci_dev *pdev, unsigned long dev_hndl, - int num_vfs); - -/*****************************************************************************/ -/** - * Read dma config register - * - * @param dev_hndl dev_hndl returned from qdma_device_open() - * @param reg_addr register address - * @param value pointer to hold the read value - * - * @returns 0 for success and <0 for error - * - * reads dma config register - * - *****************************************************************************/ -int qdma_device_read_config_register(unsigned long dev_hndl, - unsigned int reg_addr, - unsigned int *value); - -/*****************************************************************************/ -/** - * Write dma config register - * - * @param dev_hndl dev_hndl returned from qdma_device_open() - * @param reg_addr register address - * @param val register value to be writen - * - * @returns 0 for success and <0 for error - * writes dma config register - * - *****************************************************************************/ -int qdma_device_write_config_register(unsigned long dev_hndl, - unsigned int reg_addr, - unsigned int val); - -/*****************************************************************************/ -/** - * retrieve the capabilities of a device. - * - * @param dev_hndl: handle returned from qdma_device_open() - * @param dev_attr: pointer to hold all the device attributes - * - * @returns 0 for success and <0 for error - * - *****************************************************************************/ -int qdma_device_capabilities_info(unsigned long dev_hndl, - struct qdma_dev_attributes *dev_attr); - -/*****************************************************************************/ -/** - * Retrieve the RTL version , Vivado Release ID and Versal IP info - * - * @param dev_hndl handle returned from qdma_device_open() - * @param version_info pointer to hold all the version details - * - * @returns 0 for success and <0 for error - * - * retrieves the RTL version , Vivado Release ID and Versal IP info - * - *****************************************************************************/ -int qdma_device_version_info(unsigned long dev_hndl, - struct qdma_version_info *version_info); - -/*****************************************************************************/ -/** - * Retrieve the software version - * - * @param software_version A pointer to a null-terminated string - * @param length Length of the version name string - * - * @returns 0 for success and <0 for error - * - * retrieves the software version - * - *****************************************************************************/ -int qdma_software_version_info(char *software_version, int length); - -/*****************************************************************************/ -/** - * Retrieve the global csr settings - * - * @param dev_hndl handle returned from qdma_device_open() - * @param index Index from where the values needs to read - * @param count number of entries to be read - * @param csr data structures to hold the csr values - * - * @returns 0 for success and <0 for error - * - * retrieves the global csr settings - * - *****************************************************************************/ -int qdma_global_csr_get(unsigned long dev_hndl, u8 index, u8 count, - struct global_csr_conf *csr); - -/*****************************************************************************/ -/** - * Add a queue - * - * @param dev_hndl dev_hndl returned from qdma_device_open() - * @param qconf queue configuration parameters - * @param qhndl list of unsigned long values that are the opaque qhndl - * @param buflen length of the input buffer - * @param buf message buffer - * - * @returns 0 for success and <0 for error - * - *****************************************************************************/ -int qdma_queue_add(unsigned long dev_hndl, struct qdma_queue_conf *qconf, - unsigned long *qhndl, char *buf, int buflen); - -/*****************************************************************************/ -/** - * Configure the queue with qcong parameters - * - * @param dev_hndl dev_hndl returned from qdma_device_open() - * @param qid queue id - * @param qconf queue configuration parameters - * @param buflen length of the input buffer - * @param buf message buffer - * - * @returns 0: success <0: error - *****************************************************************************/ -int qdma_queue_config(unsigned long dev_hndl, unsigned long qid, - struct qdma_queue_conf *qconf, char *buf, int buflen); -/*****************************************************************************/ -/** - * start a queue (i.e, online, ready for dma) - * - * @param dev_hndl dev_hndl returned from qdma_device_open() - * @param id the opaque qhndl - * @param buflen length of the input buffer - * @param buf message buffer - * - * @returns 0 for success and <0 for error - * - *****************************************************************************/ -int qdma_queue_start(unsigned long dev_hndl, unsigned long id, - char *buf, int buflen); - -/*****************************************************************************/ -/** - * Stop a queue (i.e., offline, NOT ready for dma) - * - * @param dev_hndl dev_hndl returned from qdma_device_open() - * @param id the opaque qhndl - * @param buflen length of the input buffer - * @param buf message buffer - * - * @returns 0 for success and <0 for error - * - *****************************************************************************/ -int qdma_queue_stop(unsigned long dev_hndl, unsigned long id, char *buf, - int buflen); - -/*****************************************************************************/ -/** - * Get the state of the queue - * - * @param dev_hndl dev_hndl returned from qdma_device_open() - * @param id the opaque qhndl - * @param q_state state of the queue - * @param buflen length of the input buffer - * @param buf message buffer - * - * @returns 0 for success and <0 for error - * - *****************************************************************************/ -int qdma_get_queue_state(unsigned long dev_hndl, unsigned long id, - struct qdma_q_state *q_state, char *buf, int buflen); - -/*****************************************************************************/ -/** - * remove a queue - * - * @param dev_hndl dev_hndl returned from qdma_device_open() - * @param id the opaque qhndl - * @param buflen length of the input buffer - * @param buf message buffer - * - * @returns 0 for success and <0 for error - * - *****************************************************************************/ -int qdma_queue_remove(unsigned long dev_hndl, unsigned long id, char *buf, - int buflen); - -/*****************************************************************************/ -/** - * retrieve the configuration of a queue - * - * @param dev_hndl dev_hndl returned from qdma_device_open() - * @param id: an opaque queue handle of type unsigned long - * @param qconf pointer to hold the qdma_queue_conf structure. - * @param buflen length of the input buffer - * @param buf message buffer - * - * @returns 0: success <0: error - * - *****************************************************************************/ -int qdma_queue_get_config(unsigned long dev_hndl, unsigned long id, - struct qdma_queue_conf *qconf, - char *buf, int buflen); - -/*****************************************************************************/ -/** - * Display all configured queues in a string buffer - * - * @param dev_hndl dev_hndl returned from qdma_device_open() - * @param qidx Queue index - * @param num_q Number of Queues to list - * @param buflen length of the input buffer - * @param buf message buffer - * - * @returns if optional message buffer used then strlen of buf, - * otherwise QDMA_OPERATION_SUCCESSFUL and <0 for error - * - *****************************************************************************/ -int qdma_queue_list(unsigned long dev_hndl, int qidx, int num_q, char *buf, - int buflen); - -/*****************************************************************************/ -/** - * Display a config registers in a string buffer - * - * @param dev_hndl dev_hndl returned from qdma_device_open() - * @param buflen length of the input buffer - * @param buf message buffer - * - * @returns success: if optional message buffer used - * then strlen of buf, otherwise 0 and <0: error - * - *****************************************************************************/ -int qdma_config_reg_dump(unsigned long dev_hndl, char *buf, - int buflen); - -/*****************************************************************************/ -/** - * display a queue's state in a string buffer - * - * @param dev_hndl dev_hndl returned from qdma_device_open() - * @param id an opaque queue handle of type unsigned long - * @param buflen length of the input buffer - * @param buf message buffer - * - * @returns if optional message buffer used then strlen of buf, - * otherwise QDMA_OPERATION_SUCCESSFUL and <0 for error - * - *****************************************************************************/ -int qdma_queue_dump(unsigned long dev_hndl, unsigned long id, char *buf, - int buflen); - -/*****************************************************************************/ -/** - * Display a queue's descriptor ring from index start - * ~ end in a string buffer - * - * @param dev_hndl dev_hndl returned from qdma_device_open() - * @param id an opaque queue handle of type unsigned long - * @param start start index - * @param end end index - * @param buflen length of the input buffer - * @param buf message buffer - * - * @returns if optional message buffer used then strlen of buf, - * otherwise QDMA_OPERATION_SUCCESSFUL and <0 for error - * - *****************************************************************************/ -int qdma_queue_dump_desc(unsigned long dev_hndl, unsigned long id, - unsigned int start, unsigned int end, char *buf, - int buflen); - -/*****************************************************************************/ -/** - * display a queue's descriptor ring from index start - * ~ end in a string buffer - * - * @param dev_hndl dev_hndl returned from qdma_device_open() - * @param id an opaque queue handle of type unsigned long - * @param start start index - * @param end end index - * @param buflen length of the input buffer - * @param buf message buffer - * - * @returns if optional message buffer used then strlen of buf, - * otherwise QDMA_OPERATION_SUCCESSFUL and <0 for error - * - *****************************************************************************/ -int qdma_queue_dump_cmpt(unsigned long dev_hndl, unsigned long id, - unsigned int start, unsigned int end, char *buf, - int buflen); - -#ifdef ERR_DEBUG -/*****************************************************************************/ -/** - * Induce the error - * - * @param dev_hndl dev_hndl returned from qdma_device_open() - * @param id error id - * @param err error info - * @param buflen length of the input buffer - * @param buf message buffer - * - * @returns if optional message buffer used then strlen of buf, - * otherwise QDMA_OPERATION_SUCCESSFUL and <0 for error - * - *****************************************************************************/ -int qdma_queue_set_err_induction(unsigned long dev_hndl, unsigned long id, - u32 err, char *buf, int buflen); -#endif - -/*****************************************************************************/ -/** - * Submit a scatter-gather list of data for dma - * operation (for both read and write) - * - * @param dev_hndl hndl returned from qdma_device_open() - * @param id queue index - * @param req qdma request - * - * @returns # of bytes transferred for success and <0 for error - * - *****************************************************************************/ -ssize_t qdma_request_submit(unsigned long dev_hndl, unsigned long id, - struct qdma_request *req); - -/*****************************************************************************/ -/** - * Submit a scatter-gather list of data for dma - * operation (for both read and write) - * - * @param dev_hndl hndl returned from qdma_device_open() - * @param id queue index - * @param count number of requests - * @param reqv qdma request - * - * @returns # of bytes transferred for success and <0 for error - * - *****************************************************************************/ -ssize_t qdma_batch_request_submit(unsigned long dev_hndl, unsigned long id, - unsigned long count, struct qdma_request **reqv); - -/*****************************************************************************/ -/** - * Peek a receive (c2h) queue - * - * @param dev_hndl hndl returned from qdma_device_open() - * @param id queue hndl returned from qdma_queue_add() - * - * filled in by libqdma: - * @param udd_cnt # of udd received - * @param pkt_cnt # of packets received - * @param data_len # of bytes of packet data received - * - * @returns # of packets received in the Q or <0 for error - *****************************************************************************/ -int qdma_queue_c2h_peek(unsigned long dev_hndl, unsigned long id, - unsigned int *udd_cnt, unsigned int *pkt_cnt, - unsigned int *data_len); - - -/*****************************************************************************/ -/** - * Query of # of free descriptor - * - * @param dev_hndl hndl returned from qdma_device_open() - * @param id queue hndl returned from qdma_queue_add() - * - * @returns # of available desc in the queue or <0 for error - *****************************************************************************/ -int qdma_queue_avail_desc(unsigned long dev_hndl, unsigned long id); - -/** packet/streaming interfaces */ - -/*****************************************************************************/ -/** - * Read/set the c2h Q's completion control - * - * @param dev_hndl hndl returned from qdma_device_open() - * @param id hndl returned from qdma_queue_add() - * @param cctrl completion control - * @param set read or set - * - * @returns 0 for success or <0 for error - * - *****************************************************************************/ -int qdma_queue_cmpl_ctrl(unsigned long dev_hndl, unsigned long id, - struct qdma_cmpl_ctrl *cctrl, bool set); - -/*****************************************************************************/ -/** - * Read rcv'ed data (ST C2H dma operation) - * - * @param dev_hndl hndl returned from qdma_device_open() - * @param id queue hndl returned from qdma_queue_add() - * @param req pointer to the request data - * @param cctrl completion control, if no change is desired, - * set it to NULL - * - * @returns # of bytes transferred for success and <0 for error - * - *****************************************************************************/ -int qdma_queue_packet_read(unsigned long dev_hndl, unsigned long id, - struct qdma_request *req, struct qdma_cmpl_ctrl *cctrl); - -/*****************************************************************************/ -/** - * Submit data for ST H2C dma operation - * - * @param dev_hndl hndl returned from qdma_device_open() - * @param id queue hndl returned from qdma_queue_add() - * @param req pointer to the list of packet data - * - * @returns # of bytes transferred for success and <0 for error - * - *****************************************************************************/ -int qdma_queue_packet_write(unsigned long dev_hndl, unsigned long id, - struct qdma_request *req); - -/*****************************************************************************/ -/** - * Service the queue in the case of irq handler is registered by the user, - * the user should call qdma_queue_service() in its interrupt handler to - * service the queue - * - * @param dev_hndl dev_hndl returned from qdma_device_open() - * @param id queue hndl returned from qdma_queue_add() - * @param budget ST C2H only, max number of completions to be processed. - * @param c2h_upd_cmpl flag to update the completion - * - * Return: 0 for success or <0 for error - * - *****************************************************************************/ -int qdma_queue_service(unsigned long dev_hndl, unsigned long id, - int budget, bool c2h_upd_cmpl); - -/*****************************************************************************/ -/** - * Update queue pointers - * - * @param dev_hndl dev_hndl returned from qdma_device_open() - * @param qhndl hndl returned from qdma_queue_add() - * - * Return: 0 for success or <0 for error - * - *****************************************************************************/ -int qdma_queue_update_pointers(unsigned long dev_hndl, unsigned long qhndl); - -/*****************************************************************************/ -/** - * Display the interrupt ring info of a vector - * - * @param dev_hndl dev_hndl returned from qdma_device_open() - * @param vector_idx vector number - * @param start_idx interrupt ring start idx - * @param end_idx interrupt ring end idx - * @param buflen length of the input buffer - * @param buf message bufferuffer - * - * @returns 0 for success or <0 for error - * - *****************************************************************************/ -int qdma_intr_ring_dump(unsigned long dev_hndl, unsigned int vector_idx, - int start_idx, int end_idx, char *buf, int buflen); - -/*****************************************************************************/ -/** - * Function to receive the user defined data - * - * @param dev_hndl dev_hndl returned from qdma_device_open() - * @param id queue handle - * @param buflen length of the input buffer - * @param buf message bufferuffer - * - * @returns 0 for success or <0 for error - * - *****************************************************************************/ -int qdma_descq_get_cmpt_udd(unsigned long dev_hndl, unsigned long id, - char *buf, int buflen); - -/*****************************************************************************/ -/** - * Function to receive the completion data - * - * @param dev_hndl dev_hndl returned from qdma_device_open() - * @param id queue handle - * @param num_entries I/O number of entries - * @param cmpt_entries List of completion entries - * @param buflen length of the input buffer - * @param buf message bufferuffer - * - * @returns 0 for success or <0 for error - * - *****************************************************************************/ -int qdma_descq_read_cmpt_data(unsigned long dev_hndl, unsigned long id, - u32 *num_entries, u8 **cmpt_entries, - char *buf, int buflen); - -/*****************************************************************************/ -/** - * Function to receive the queue count - * - * @param dev_hndl dev_hndl returned from qdma_device_open() - * @param q_count queue count - * @param buflen length of the input buffer - * @param buf message bufferuffer - * - * @returns 0 for success or <0 for error - * - *****************************************************************************/ -int qdma_get_queue_count(unsigned long dev_hndl, - struct qdma_queue_count *q_count, - char *buf, int buflen); - -/*****************************************************************************/ -/** - * Function to print out detailed information for register value - * - * @param dev_hndl dev_hndl returned from qdma_device_open() - * @param reg_addr register address - * @param num_regs num of registerse to be dumped - * @param buf message bufferuffer - * @param buflen length of the input buffer - * - * @returns 0 for success or <0 for error - * - *****************************************************************************/ -int qdma_config_reg_info_dump(unsigned long dev_hndl, uint32_t reg_addr, - uint32_t num_regs, char *buf, int buflen); - -#ifdef __QDMA_VF__ -/*****************************************************************************/ -/** - * Call for VF to request qmax number of Qs - * - * @param dev_hndl dev_hndl returned from qdma_device_open() - * @param qmax number of qs requested by vf - * - * @returns 0 for success or <0 for error - * - *****************************************************************************/ -int qdma_vf_qconf(unsigned long dev_hndl, int qmax); -#endif - -#ifdef TANDEM_BOOT_SUPPORTED -/*****************************************************************************/ -/** - * Clear ST context for tandem boot designs - * - * @param dev_hndl dev_hndl retunred from qdma_device_open() - * @param buflen input buffer length - * @param buf error message buffer, can be NULL/0 (i.e., optional - * - * @returns 0 for success or <0 for error - * - *****************************************************************************/ -int qdma_init_st_ctxt(unsigned long dev_hndl, char *buf, int buflen); -#endif - -#endif diff --git a/QDMA/linux-kernel/driver/libqdma/qdma_access/eqdma_cpm5_access/eqdma_cpm5_access.c b/QDMA/linux-kernel/driver/libqdma/qdma_access/eqdma_cpm5_access/eqdma_cpm5_access.c deleted file mode 100755 index 9bb152fea..000000000 --- a/QDMA/linux-kernel/driver/libqdma/qdma_access/eqdma_cpm5_access/eqdma_cpm5_access.c +++ /dev/null @@ -1,6863 +0,0 @@ -/* - * Copyright (c) 2019-2022, Xilinx, Inc. All rights reserved. - * Copyright (c) 2022, Advanced Micro Devices, Inc. All rights reserved. - * - * This source code is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * The full GNU General Public License is included in this distribution in - * the file called "COPYING". - */ - -#include "eqdma_cpm5_access.h" -#include "eqdma_cpm5_reg.h" -#include "qdma_reg_dump.h" - -#ifdef ENABLE_WPP_TRACING -#include "eqdma_cpm5_access.tmh" -#endif - -#define UNUSED(x) (void)(x) - -/** EQDMA Context array size */ -#define EQDMA_CPM5_FMAP_NUM_WORDS 2 -#define EQDMA_CPM5_SW_CONTEXT_NUM_WORDS 8 -#define EQDMA_CPM5_HW_CONTEXT_NUM_WORDS 2 -#define EQDMA_CPM5_PFETCH_CONTEXT_NUM_WORDS 2 -#define EQDMA_CPM5_CR_CONTEXT_NUM_WORDS 1 -#define EQDMA_CPM5_CMPT_CONTEXT_NUM_WORDS 6 -#define EQDMA_CPM5_IND_INTR_CONTEXT_NUM_WORDS 4 - -#define EQDMA_CPM5_VF_USER_BAR_ID 2 - -#define EQDMA_CPM5_REG_GROUP_1_START_ADDR 0x000 -#define EQDMA_CPM5_REG_GROUP_2_START_ADDR 0x804 -#define EQDMA_CPM5_REG_GROUP_3_START_ADDR 0xB00 -#define EQDMA_CPM5_REG_GROUP_4_START_ADDR 0x5014 - -#define EQDMA_CPM5_TOTAL_LEAF_ERROR_AGGREGATORS 11 -#define EQDMA_CPM5_GLBL_TRQ_ERR_ALL_MASK 0XB3 -#define EQDMA_CPM5_GLBL_DSC_ERR_ALL_MASK 0X1F9037E -#define EQDMA_CPM5_C2H_ERR_ALL_MASK 0X3F6DF -#define EQDMA_CPM5_C2H_FATAL_ERR_ALL_MASK 0X1FDF1B -#define EQDMA_CPM5_H2C_ERR_ALL_MASK 0X3F -#define EQDMA_CPM5_SBE_ERR_ALL_MASK 0XFFFFFFFF -#define EQDMA_CPM5_DBE_ERR_ALL_MASK 0XFFFFFFFF -#define EQDMA_CPM5_MM_C2H_ERR_ALL_MASK 0X70000003 -#define EQDMA_CPM5_MM_H2C0_ERR_ALL_MASK 0X3041013E - -/* H2C Throttle settings */ -#define EQDMA_CPM5_H2C_THROT_DATA_THRESH 0x5000 -#define EQDMA_CPM5_THROT_EN_DATA 1 -#define EQDMA_CPM5_THROT_EN_REQ 0 -#define EQDMA_CPM5_H2C_THROT_REQ_THRESH 0xC0 - - -/** Auxillary Bitmasks for fields spanning multiple words */ -#define EQDMA_CPM5_SW_CTXT_PASID_GET_H_MASK GENMASK(21, 12) -#define EQDMA_CPM5_SW_CTXT_PASID_GET_L_MASK GENMASK(11, 0) -#define EQDMA_CPM5_SW_CTXT_VIRTIO_DSC_BASE_GET_H_MASK GENMASK_ULL(63, 53) -#define EQDMA_CPM5_SW_CTXT_VIRTIO_DSC_BASE_GET_M_MASK GENMASK_ULL(52, 21) -#define EQDMA_CPM5_SW_CTXT_VIRTIO_DSC_BASE_GET_L_MASK GENMASK_ULL(20, 0) -#define EQDMA_CPM5_CMPL_CTXT_PASID_GET_H_MASK GENMASK(21, 9) -#define EQDMA_CPM5_CMPL_CTXT_PASID_GET_L_MASK GENMASK(8, 0) -#define EQDMA_CPM5_INTR_CTXT_PASID_GET_H_MASK GENMASK(21, 9) -#define EQDMA_CPM5_INTR_CTXT_PASID_GET_L_MASK GENMASK(8, 0) - -#define EQDMA_CPM5_OFFSET_GLBL2_PF_BARLITE_EXT 0x10C - -#define QDMA_OFFSET_GLBL2_PF_BARLITE_INT 0x104 -#define QDMA_GLBL2_PF3_BAR_MAP_MASK GENMASK(23, 18) -#define QDMA_GLBL2_PF2_BAR_MAP_MASK GENMASK(17, 12) -#define QDMA_GLBL2_PF1_BAR_MAP_MASK GENMASK(11, 6) -#define QDMA_GLBL2_PF0_BAR_MAP_MASK GENMASK(5, 0) - -#define EQDMA_CPM5_GLBL2_DBG_MODE_EN_MASK BIT(4) -#define EQDMA_CPM5_GLBL2_DESC_ENG_MODE_MASK GENMASK(3, 2) -#define EQDMA_CPM5_GLBL2_FLR_PRESENT_MASK BIT(1) -#define EQDMA_CPM5_GLBL2_MAILBOX_EN_MASK BIT(0) - -#define EQDMA_CPM5_DEFAULT_C2H_INTR_TIMER_TICK 50 -#define PREFETCH_QUEUE_COUNT_STEP 4 -#define EQDMA_CPM5_DEFAULT_CMPT_COAL_MAX_BUF_SZ 0x3F - -/* TODO: This is work around and this needs to be auto generated from ODS */ -/** EQDMA_CPM5_IND_REG_SEL_FMAP */ -#define EQDMA_CPM5_FMAP_CTXT_W1_QID_MAX_MASK GENMASK(12, 0) -#define EQDMA_CPM5_FMAP_CTXT_W0_QID_MASK GENMASK(11, 0) - -static void eqdma_cpm5_hw_st_h2c_err_process(void *dev_hndl); -static void eqdma_cpm5_hw_st_c2h_err_process(void *dev_hndl); -static void eqdma_cpm5_hw_desc_err_process(void *dev_hndl); -static void eqdma_cpm5_hw_trq_err_process(void *dev_hndl); -static void eqdma_cpm5_hw_ram_sbe_err_process(void *dev_hndl); -static void eqdma_cpm5_hw_ram_dbe_err_process(void *dev_hndl); -static void eqdma_cpm5_mm_h2c0_err_process(void *dev_hndl); -static void eqdma_cpm5_mm_c2h0_err_process(void *dev_hndl); - -static struct eqdma_cpm5_hw_err_info - eqdma_cpm5_err_info[EQDMA_CPM5_ERRS_ALL] = { - /* Descriptor errors */ - { - EQDMA_CPM5_DSC_ERR_POISON, - "Poison error", - EQDMA_CPM5_GLBL_DSC_ERR_MSK_ADDR, - EQDMA_CPM5_GLBL_DSC_ERR_STS_ADDR, - GLBL_DSC_ERR_STS_POISON_MASK, - GLBL_ERR_STAT_ERR_DSC_MASK, - &eqdma_cpm5_hw_desc_err_process - }, - { - EQDMA_CPM5_DSC_ERR_UR_CA, - "Unsupported request or completer aborted error", - EQDMA_CPM5_GLBL_DSC_ERR_MSK_ADDR, - EQDMA_CPM5_GLBL_DSC_ERR_STS_ADDR, - GLBL_DSC_ERR_STS_UR_CA_MASK, - GLBL_ERR_STAT_ERR_DSC_MASK, - &eqdma_cpm5_hw_desc_err_process - }, - { - EQDMA_CPM5_DSC_ERR_BCNT, - "Unexpected Byte count in completion error", - EQDMA_CPM5_GLBL_DSC_ERR_MSK_ADDR, - EQDMA_CPM5_GLBL_DSC_ERR_STS_ADDR, - GLBL_DSC_ERR_STS_BCNT_MASK, - GLBL_ERR_STAT_ERR_DSC_MASK, - &eqdma_cpm5_hw_desc_err_process - }, - { - EQDMA_CPM5_DSC_ERR_PARAM, - "Parameter mismatch error", - EQDMA_CPM5_GLBL_DSC_ERR_MSK_ADDR, - EQDMA_CPM5_GLBL_DSC_ERR_STS_ADDR, - GLBL_DSC_ERR_STS_PARAM_MASK, - GLBL_ERR_STAT_ERR_DSC_MASK, - &eqdma_cpm5_hw_desc_err_process - }, - { - EQDMA_CPM5_DSC_ERR_ADDR, - "Address mismatch error", - EQDMA_CPM5_GLBL_DSC_ERR_MSK_ADDR, - EQDMA_CPM5_GLBL_DSC_ERR_STS_ADDR, - GLBL_DSC_ERR_STS_ADDR_MASK, - GLBL_ERR_STAT_ERR_DSC_MASK, - &eqdma_cpm5_hw_desc_err_process - }, - { - EQDMA_CPM5_DSC_ERR_TAG, - "Unexpected tag error", - EQDMA_CPM5_GLBL_DSC_ERR_MSK_ADDR, - EQDMA_CPM5_GLBL_DSC_ERR_STS_ADDR, - GLBL_DSC_ERR_STS_TAG_MASK, - GLBL_ERR_STAT_ERR_DSC_MASK, - &eqdma_cpm5_hw_desc_err_process - }, - { - EQDMA_CPM5_DSC_ERR_FLR, - "FLR error", - EQDMA_CPM5_GLBL_DSC_ERR_MSK_ADDR, - EQDMA_CPM5_GLBL_DSC_ERR_STS_ADDR, - GLBL_DSC_ERR_STS_FLR_MASK, - GLBL_ERR_STAT_ERR_DSC_MASK, - &eqdma_cpm5_hw_desc_err_process - }, - { - EQDMA_CPM5_DSC_ERR_TIMEOUT, - "Timed out error", - EQDMA_CPM5_GLBL_DSC_ERR_MSK_ADDR, - EQDMA_CPM5_GLBL_DSC_ERR_STS_ADDR, - GLBL_DSC_ERR_STS_TIMEOUT_MASK, - GLBL_ERR_STAT_ERR_DSC_MASK, - &eqdma_cpm5_hw_desc_err_process - }, - { - EQDMA_CPM5_DSC_ERR_DAT_POISON, - "Poison data error", - EQDMA_CPM5_GLBL_DSC_ERR_MSK_ADDR, - EQDMA_CPM5_GLBL_DSC_ERR_STS_ADDR, - GLBL_DSC_ERR_STS_DAT_POISON_MASK, - GLBL_ERR_STAT_ERR_DSC_MASK, - &eqdma_cpm5_hw_desc_err_process - }, - { - EQDMA_CPM5_DSC_ERR_FLR_CANCEL, - "Descriptor fetch cancelled due to FLR error", - EQDMA_CPM5_GLBL_DSC_ERR_MSK_ADDR, - EQDMA_CPM5_GLBL_DSC_ERR_STS_ADDR, - GLBL_DSC_ERR_STS_FLR_CANCEL_MASK, - GLBL_ERR_STAT_ERR_DSC_MASK, - &eqdma_cpm5_hw_desc_err_process - }, - { - EQDMA_CPM5_DSC_ERR_DMA, - "DMA engine error", - EQDMA_CPM5_GLBL_DSC_ERR_MSK_ADDR, - EQDMA_CPM5_GLBL_DSC_ERR_STS_ADDR, - GLBL_DSC_ERR_STS_DMA_MASK, - GLBL_ERR_STAT_ERR_DSC_MASK, - &eqdma_cpm5_hw_desc_err_process - }, - { - EQDMA_CPM5_DSC_ERR_DSC, - "Invalid PIDX update error", - EQDMA_CPM5_GLBL_DSC_ERR_MSK_ADDR, - EQDMA_CPM5_GLBL_DSC_ERR_STS_ADDR, - GLBL_DSC_ERR_STS_DSC_MASK, - GLBL_ERR_STAT_ERR_DSC_MASK, - &eqdma_cpm5_hw_desc_err_process - }, - { - EQDMA_CPM5_DSC_ERR_RQ_CANCEL, - "Descriptor fetch cancelled due to disable register status error", - EQDMA_CPM5_GLBL_DSC_ERR_MSK_ADDR, - EQDMA_CPM5_GLBL_DSC_ERR_STS_ADDR, - GLBL_DSC_ERR_STS_RQ_CANCEL_MASK, - GLBL_ERR_STAT_ERR_DSC_MASK, - &eqdma_cpm5_hw_desc_err_process - }, - { - EQDMA_CPM5_DSC_ERR_DBE, - "UNC_ERR_RAM_DBE error", - EQDMA_CPM5_GLBL_DSC_ERR_MSK_ADDR, - EQDMA_CPM5_GLBL_DSC_ERR_STS_ADDR, - GLBL_DSC_ERR_STS_DBE_MASK, - GLBL_ERR_STAT_ERR_DSC_MASK, - &eqdma_cpm5_hw_desc_err_process - }, - { - EQDMA_CPM5_DSC_ERR_SBE, - "UNC_ERR_RAM_SBE error", - EQDMA_CPM5_GLBL_DSC_ERR_MSK_ADDR, - EQDMA_CPM5_GLBL_DSC_ERR_STS_ADDR, - GLBL_DSC_ERR_STS_SBE_MASK, - GLBL_ERR_STAT_ERR_DSC_MASK, - &eqdma_cpm5_hw_desc_err_process - }, - { - EQDMA_CPM5_DSC_ERR_PORT_ID, - "Port ID Error", - EQDMA_CPM5_GLBL_DSC_ERR_MSK_ADDR, - EQDMA_CPM5_GLBL_DSC_ERR_STS_ADDR, - GLBL_DSC_ERR_STS_PORT_ID_MASK, - GLBL_ERR_STAT_ERR_DSC_MASK, - &eqdma_cpm5_hw_desc_err_process - }, - { - EQDMA_CPM5_DSC_ERR_ALL, - "All Descriptor errors", - EQDMA_CPM5_GLBL_DSC_ERR_MSK_ADDR, - EQDMA_CPM5_GLBL_DSC_ERR_STS_ADDR, - EQDMA_CPM5_GLBL_DSC_ERR_ALL_MASK, - GLBL_ERR_STAT_ERR_DSC_MASK, - &eqdma_cpm5_hw_desc_err_process - }, - - /* TRQ errors */ - { - EQDMA_CPM5_TRQ_ERR_CSR_UNMAPPED, - "Access targeted unmapped register space via CSR pathway error", - EQDMA_CPM5_GLBL_TRQ_ERR_MSK_ADDR, - EQDMA_CPM5_GLBL_TRQ_ERR_STS_ADDR, - GLBL_TRQ_ERR_STS_CSR_UNMAPPED_MASK, - GLBL_ERR_STAT_ERR_TRQ_MASK, - &eqdma_cpm5_hw_trq_err_process - }, - { - EQDMA_CPM5_TRQ_ERR_VF_ACCESS, - "VF attempted to access Global register space or Function map", - EQDMA_CPM5_GLBL_TRQ_ERR_MSK_ADDR, - EQDMA_CPM5_GLBL_TRQ_ERR_STS_ADDR, - GLBL_TRQ_ERR_STS_VF_ACCESS_ERR_MASK, - GLBL_ERR_STAT_ERR_TRQ_MASK, - &eqdma_cpm5_hw_trq_err_process - }, - { - EQDMA_CPM5_TRQ_ERR_TCP_CSR_TIMEOUT, - "Timeout on request to dma internal csr register", - EQDMA_CPM5_GLBL_TRQ_ERR_MSK_ADDR, - EQDMA_CPM5_GLBL_TRQ_ERR_STS_ADDR, - GLBL_TRQ_ERR_STS_TCP_CSR_TIMEOUT_MASK, - GLBL_ERR_STAT_ERR_TRQ_MASK, - &eqdma_cpm5_hw_trq_err_process - }, - { - EQDMA_CPM5_TRQ_ERR_QSPC_UNMAPPED, - "Access targeted unmapped register via queue space pathway", - EQDMA_CPM5_GLBL_TRQ_ERR_MSK_ADDR, - EQDMA_CPM5_GLBL_TRQ_ERR_STS_ADDR, - GLBL_TRQ_ERR_STS_QSPC_UNMAPPED_MASK, - GLBL_ERR_STAT_ERR_TRQ_MASK, - &eqdma_cpm5_hw_trq_err_process - }, - { - EQDMA_CPM5_TRQ_ERR_QID_RANGE, - "Qid range error", - EQDMA_CPM5_GLBL_TRQ_ERR_MSK_ADDR, - EQDMA_CPM5_GLBL_TRQ_ERR_STS_ADDR, - GLBL_TRQ_ERR_STS_QID_RANGE_MASK, - GLBL_ERR_STAT_ERR_TRQ_MASK, - &eqdma_cpm5_hw_trq_err_process - }, - { - EQDMA_CPM5_TRQ_ERR_TCP_QSPC_TIMEOUT, - "Timeout on request to dma internal queue space register", - EQDMA_CPM5_GLBL_TRQ_ERR_MSK_ADDR, - EQDMA_CPM5_GLBL_TRQ_ERR_STS_ADDR, - GLBL_TRQ_ERR_STS_TCP_QSPC_TIMEOUT_MASK, - GLBL_ERR_STAT_ERR_TRQ_MASK, - &eqdma_cpm5_hw_trq_err_process - }, - { - EQDMA_CPM5_TRQ_ERR_ALL, - "All TRQ errors", - EQDMA_CPM5_GLBL_TRQ_ERR_MSK_ADDR, - EQDMA_CPM5_GLBL_TRQ_ERR_STS_ADDR, - EQDMA_CPM5_GLBL_TRQ_ERR_ALL_MASK, - GLBL_ERR_STAT_ERR_TRQ_MASK, - &eqdma_cpm5_hw_trq_err_process - }, - - /* C2H Errors*/ - { - EQDMA_CPM5_ST_C2H_ERR_MTY_MISMATCH, - "MTY mismatch error", - EQDMA_CPM5_C2H_ERR_MASK_ADDR, - EQDMA_CPM5_C2H_ERR_STAT_ADDR, - C2H_ERR_STAT_MTY_MISMATCH_MASK, - GLBL_ERR_STAT_ERR_C2H_ST_MASK, - &eqdma_cpm5_hw_st_c2h_err_process - }, - { - EQDMA_CPM5_ST_C2H_ERR_LEN_MISMATCH, - "Packet length mismatch error", - EQDMA_CPM5_C2H_ERR_MASK_ADDR, - EQDMA_CPM5_C2H_ERR_STAT_ADDR, - C2H_ERR_STAT_LEN_MISMATCH_MASK, - GLBL_ERR_STAT_ERR_C2H_ST_MASK, - &eqdma_cpm5_hw_st_c2h_err_process - }, - { - EQDMA_CPM5_ST_C2H_ERR_SH_CMPT_DSC, - "A Shared CMPT queue has encountered a descriptor error", - EQDMA_CPM5_C2H_ERR_MASK_ADDR, - EQDMA_CPM5_C2H_ERR_STAT_ADDR, - C2H_ERR_STAT_SH_CMPT_DSC_ERR_MASK, - GLBL_ERR_STAT_ERR_C2H_ST_MASK, - &eqdma_cpm5_hw_st_c2h_err_process - }, - { - EQDMA_CPM5_ST_C2H_ERR_QID_MISMATCH, - "Qid mismatch error", - EQDMA_CPM5_C2H_ERR_MASK_ADDR, - EQDMA_CPM5_C2H_ERR_STAT_ADDR, - C2H_ERR_STAT_QID_MISMATCH_MASK, - GLBL_ERR_STAT_ERR_C2H_ST_MASK, - &eqdma_cpm5_hw_st_c2h_err_process - }, - { - EQDMA_CPM5_ST_C2H_ERR_DESC_RSP_ERR, - "Descriptor error bit set", - EQDMA_CPM5_C2H_ERR_MASK_ADDR, - EQDMA_CPM5_C2H_ERR_STAT_ADDR, - C2H_ERR_STAT_DESC_RSP_ERR_MASK, - GLBL_ERR_STAT_ERR_C2H_ST_MASK, - &eqdma_cpm5_hw_st_c2h_err_process - }, - { - EQDMA_CPM5_ST_C2H_ERR_ENG_WPL_DATA_PAR_ERR, - "Data parity error", - EQDMA_CPM5_C2H_ERR_MASK_ADDR, - EQDMA_CPM5_C2H_ERR_STAT_ADDR, - C2H_ERR_STAT_ENG_WPL_DATA_PAR_ERR_MASK, - GLBL_ERR_STAT_ERR_C2H_ST_MASK, - &eqdma_cpm5_hw_st_c2h_err_process - }, - { - EQDMA_CPM5_ST_C2H_ERR_MSI_INT_FAIL, - "MSI got a fail response error", - EQDMA_CPM5_C2H_ERR_MASK_ADDR, - EQDMA_CPM5_C2H_ERR_STAT_ADDR, - C2H_ERR_STAT_MSI_INT_FAIL_MASK, - GLBL_ERR_STAT_ERR_C2H_ST_MASK, - &eqdma_cpm5_hw_st_c2h_err_process - }, - { - EQDMA_CPM5_ST_C2H_ERR_ERR_DESC_CNT, - "Descriptor count error", - EQDMA_CPM5_C2H_ERR_MASK_ADDR, - EQDMA_CPM5_C2H_ERR_STAT_ADDR, - C2H_ERR_STAT_ERR_DESC_CNT_MASK, - GLBL_ERR_STAT_ERR_C2H_ST_MASK, - &eqdma_cpm5_hw_st_c2h_err_process - }, - { - EQDMA_CPM5_ST_C2H_ERR_PORTID_CTXT_MISMATCH, - "Port id in packet and pfetch ctxt mismatch error", - EQDMA_CPM5_C2H_ERR_MASK_ADDR, - EQDMA_CPM5_C2H_ERR_STAT_ADDR, - C2H_ERR_STAT_PORT_ID_CTXT_MISMATCH_MASK, - GLBL_ERR_STAT_ERR_C2H_ST_MASK, - &eqdma_cpm5_hw_st_c2h_err_process - }, - { - EQDMA_CPM5_ST_C2H_ERR_CMPT_INV_Q_ERR, - "Writeback on invalid queue error", - EQDMA_CPM5_C2H_ERR_MASK_ADDR, - EQDMA_CPM5_C2H_ERR_STAT_ADDR, - C2H_ERR_STAT_WRB_INV_Q_ERR_MASK, - GLBL_ERR_STAT_ERR_C2H_ST_MASK, - &eqdma_cpm5_hw_st_c2h_err_process - }, - { - EQDMA_CPM5_ST_C2H_ERR_CMPT_QFULL_ERR, - "Completion queue gets full error", - EQDMA_CPM5_C2H_ERR_MASK_ADDR, - EQDMA_CPM5_C2H_ERR_STAT_ADDR, - C2H_ERR_STAT_WRB_QFULL_ERR_MASK, - GLBL_ERR_STAT_ERR_C2H_ST_MASK, - &eqdma_cpm5_hw_st_c2h_err_process - }, - { - EQDMA_CPM5_ST_C2H_ERR_CMPT_CIDX_ERR, - "Bad CIDX update by the software error", - EQDMA_CPM5_C2H_ERR_MASK_ADDR, - EQDMA_CPM5_C2H_ERR_STAT_ADDR, - C2H_ERR_STAT_WRB_CIDX_ERR_MASK, - GLBL_ERR_STAT_ERR_C2H_ST_MASK, - &eqdma_cpm5_hw_st_c2h_err_process - }, - { - EQDMA_CPM5_ST_C2H_ERR_CMPT_PRTY_ERR, - "C2H completion Parity error", - EQDMA_CPM5_C2H_ERR_MASK_ADDR, - EQDMA_CPM5_C2H_ERR_STAT_ADDR, - C2H_ERR_STAT_WRB_PRTY_ERR_MASK, - GLBL_ERR_STAT_ERR_C2H_ST_MASK, - &eqdma_cpm5_hw_st_c2h_err_process - }, - { - EQDMA_CPM5_ST_C2H_ERR_AVL_RING_DSC, - "Available ring fetch returns descriptor with error", - EQDMA_CPM5_C2H_ERR_MASK_ADDR, - EQDMA_CPM5_C2H_ERR_STAT_ADDR, - C2H_ERR_STAT_AVL_RING_DSC_ERR_MASK, - GLBL_ERR_STAT_ERR_C2H_ST_MASK, - &eqdma_cpm5_hw_st_c2h_err_process - }, - { - EQDMA_CPM5_ST_C2H_ERR_HDR_ECC_UNC, - "multi-bit ecc error on c2h packet header", - EQDMA_CPM5_C2H_ERR_MASK_ADDR, - EQDMA_CPM5_C2H_ERR_STAT_ADDR, - C2H_ERR_STAT_HDR_ECC_UNC_ERR_MASK, - GLBL_ERR_STAT_ERR_C2H_ST_MASK, - &eqdma_cpm5_hw_st_c2h_err_process - }, - { - EQDMA_CPM5_ST_C2H_ERR_HDR_ECC_COR, - "single-bit ecc error on c2h packet header", - EQDMA_CPM5_C2H_ERR_MASK_ADDR, - EQDMA_CPM5_C2H_ERR_STAT_ADDR, - C2H_ERR_STAT_HDR_ECC_COR_ERR_MASK, - GLBL_ERR_STAT_ERR_C2H_ST_MASK, - &eqdma_cpm5_hw_st_c2h_err_process - }, - { - EQDMA_CPM5_ST_C2H_ERR_WRB_PORT_ID_ERR, - "Port ID error", - EQDMA_CPM5_C2H_ERR_MASK_ADDR, - EQDMA_CPM5_C2H_ERR_STAT_ADDR, - C2H_ERR_STAT_WRB_PORT_ID_ERR_MASK, - GLBL_ERR_STAT_ERR_C2H_ST_MASK, - &eqdma_cpm5_hw_st_c2h_err_process - }, - { - EQDMA_CPM5_ST_C2H_ERR_ALL, - "All C2h errors", - EQDMA_CPM5_C2H_ERR_MASK_ADDR, - EQDMA_CPM5_C2H_ERR_STAT_ADDR, - EQDMA_CPM5_C2H_ERR_ALL_MASK, - GLBL_ERR_STAT_ERR_C2H_ST_MASK, - &eqdma_cpm5_hw_st_c2h_err_process - }, - - /* C2H fatal errors */ - { - EQDMA_CPM5_ST_FATAL_ERR_MTY_MISMATCH, - "Fatal MTY mismatch error", - EQDMA_CPM5_C2H_FATAL_ERR_MASK_ADDR, - EQDMA_CPM5_C2H_FATAL_ERR_STAT_ADDR, - C2H_FATAL_ERR_STAT_MTY_MISMATCH_MASK, - GLBL_ERR_STAT_ERR_C2H_ST_MASK, - &eqdma_cpm5_hw_st_c2h_err_process - }, - { - EQDMA_CPM5_ST_FATAL_ERR_LEN_MISMATCH, - "Fatal Len mismatch error", - EQDMA_CPM5_C2H_FATAL_ERR_MASK_ADDR, - EQDMA_CPM5_C2H_FATAL_ERR_STAT_ADDR, - C2H_FATAL_ERR_STAT_LEN_MISMATCH_MASK, - GLBL_ERR_STAT_ERR_C2H_ST_MASK, - &eqdma_cpm5_hw_st_c2h_err_process - }, - { - EQDMA_CPM5_ST_FATAL_ERR_QID_MISMATCH, - "Fatal Qid mismatch error", - EQDMA_CPM5_C2H_FATAL_ERR_MASK_ADDR, - EQDMA_CPM5_C2H_FATAL_ERR_STAT_ADDR, - C2H_FATAL_ERR_STAT_QID_MISMATCH_MASK, - GLBL_ERR_STAT_ERR_C2H_ST_MASK, - &eqdma_cpm5_hw_st_c2h_err_process - }, - { - EQDMA_CPM5_ST_FATAL_ERR_TIMER_FIFO_RAM_RDBE, - "RAM double bit fatal error", - EQDMA_CPM5_C2H_FATAL_ERR_MASK_ADDR, - EQDMA_CPM5_C2H_FATAL_ERR_STAT_ADDR, - C2H_FATAL_ERR_STAT_TIMER_FIFO_RAM_RDBE_MASK, - GLBL_ERR_STAT_ERR_C2H_ST_MASK, - &eqdma_cpm5_hw_st_c2h_err_process - }, - { - EQDMA_CPM5_ST_FATAL_ERR_PFCH_II_RAM_RDBE, - "RAM double bit fatal error", - EQDMA_CPM5_C2H_FATAL_ERR_MASK_ADDR, - EQDMA_CPM5_C2H_FATAL_ERR_STAT_ADDR, - C2H_FATAL_ERR_STAT_PFCH_LL_RAM_RDBE_MASK, - GLBL_ERR_STAT_ERR_C2H_ST_MASK, - &eqdma_cpm5_hw_st_c2h_err_process - }, - { - EQDMA_CPM5_ST_FATAL_ERR_CMPT_CTXT_RAM_RDBE, - "RAM double bit fatal error", - EQDMA_CPM5_C2H_FATAL_ERR_MASK_ADDR, - EQDMA_CPM5_C2H_FATAL_ERR_STAT_ADDR, - C2H_FATAL_ERR_STAT_WRB_CTXT_RAM_RDBE_MASK, - GLBL_ERR_STAT_ERR_C2H_ST_MASK, - &eqdma_cpm5_hw_st_c2h_err_process - }, - { - EQDMA_CPM5_ST_FATAL_ERR_PFCH_CTXT_RAM_RDBE, - "RAM double bit fatal error", - EQDMA_CPM5_C2H_FATAL_ERR_MASK_ADDR, - EQDMA_CPM5_C2H_FATAL_ERR_STAT_ADDR, - C2H_FATAL_ERR_STAT_PFCH_CTXT_RAM_RDBE_MASK, - GLBL_ERR_STAT_ERR_C2H_ST_MASK, - &eqdma_cpm5_hw_st_c2h_err_process - }, - { - EQDMA_CPM5_ST_FATAL_ERR_DESC_REQ_FIFO_RAM_RDBE, - "RAM double bit fatal error", - EQDMA_CPM5_C2H_FATAL_ERR_MASK_ADDR, - EQDMA_CPM5_C2H_FATAL_ERR_STAT_ADDR, - C2H_FATAL_ERR_STAT_DESC_REQ_FIFO_RAM_RDBE_MASK, - GLBL_ERR_STAT_ERR_C2H_ST_MASK, - &eqdma_cpm5_hw_st_c2h_err_process - }, - { - EQDMA_CPM5_ST_FATAL_ERR_INT_CTXT_RAM_RDBE, - "RAM double bit fatal error", - EQDMA_CPM5_C2H_FATAL_ERR_MASK_ADDR, - EQDMA_CPM5_C2H_FATAL_ERR_STAT_ADDR, - C2H_FATAL_ERR_STAT_INT_CTXT_RAM_RDBE_MASK, - GLBL_ERR_STAT_ERR_C2H_ST_MASK, - &eqdma_cpm5_hw_st_c2h_err_process - }, - { - EQDMA_CPM5_ST_FATAL_ERR_CMPT_COAL_DATA_RAM_RDBE, - "RAM double bit fatal error", - EQDMA_CPM5_C2H_FATAL_ERR_MASK_ADDR, - EQDMA_CPM5_C2H_FATAL_ERR_STAT_ADDR, - C2H_FATAL_ERR_STAT_WRB_COAL_DATA_RAM_RDBE_MASK, - GLBL_ERR_STAT_ERR_C2H_ST_MASK, - &eqdma_cpm5_hw_st_c2h_err_process - }, - { - EQDMA_CPM5_ST_FATAL_ERR_CMPT_FIFO_RAM_RDBE, - "RAM double bit fatal error", - EQDMA_CPM5_C2H_FATAL_ERR_MASK_ADDR, - EQDMA_CPM5_C2H_FATAL_ERR_STAT_ADDR, - C2H_FATAL_ERR_STAT_CMPT_FIFO_RAM_RDBE_MASK, - GLBL_ERR_STAT_ERR_C2H_ST_MASK, - &eqdma_cpm5_hw_st_c2h_err_process - }, - { - EQDMA_CPM5_ST_FATAL_ERR_QID_FIFO_RAM_RDBE, - "RAM double bit fatal error", - EQDMA_CPM5_C2H_FATAL_ERR_MASK_ADDR, - EQDMA_CPM5_C2H_FATAL_ERR_STAT_ADDR, - C2H_FATAL_ERR_STAT_QID_FIFO_RAM_RDBE_MASK, - GLBL_ERR_STAT_ERR_C2H_ST_MASK, - &eqdma_cpm5_hw_st_c2h_err_process - }, - { - EQDMA_CPM5_ST_FATAL_ERR_PAYLOAD_FIFO_RAM_RDBE, - "RAM double bit fatal error", - EQDMA_CPM5_C2H_FATAL_ERR_MASK_ADDR, - EQDMA_CPM5_C2H_FATAL_ERR_STAT_ADDR, - C2H_FATAL_ERR_STAT_PLD_FIFO_RAM_RDBE_MASK, - GLBL_ERR_STAT_ERR_C2H_ST_MASK, - &eqdma_cpm5_hw_st_c2h_err_process - }, - { - EQDMA_CPM5_ST_FATAL_ERR_WPL_DATA_PAR, - "RAM double bit fatal error", - EQDMA_CPM5_C2H_FATAL_ERR_MASK_ADDR, - EQDMA_CPM5_C2H_FATAL_ERR_STAT_ADDR, - C2H_FATAL_ERR_STAT_WPL_DATA_PAR_ERR_MASK, - GLBL_ERR_STAT_ERR_C2H_ST_MASK, - &eqdma_cpm5_hw_st_c2h_err_process - }, - { - EQDMA_CPM5_ST_FATAL_ERR_AVL_RING_FIFO_RAM_RDBE, - "RAM double bit fatal error", - EQDMA_CPM5_C2H_FATAL_ERR_MASK_ADDR, - EQDMA_CPM5_C2H_FATAL_ERR_STAT_ADDR, - C2H_FATAL_ERR_STAT_AVL_RING_FIFO_RAM_RDBE_MASK, - GLBL_ERR_STAT_ERR_C2H_ST_MASK, - &eqdma_cpm5_hw_st_c2h_err_process - }, - { - EQDMA_CPM5_ST_FATAL_ERR_HDR_ECC_UNC, - "RAM double bit fatal error", - EQDMA_CPM5_C2H_FATAL_ERR_MASK_ADDR, - EQDMA_CPM5_C2H_FATAL_ERR_STAT_ADDR, - C2H_FATAL_ERR_STAT_HDR_ECC_UNC_ERR_MASK, - GLBL_ERR_STAT_ERR_C2H_ST_MASK, - &eqdma_cpm5_hw_st_c2h_err_process - }, - { - EQDMA_CPM5_ST_FATAL_ERR_ALL, - "All fatal errors", - EQDMA_CPM5_C2H_FATAL_ERR_MASK_ADDR, - EQDMA_CPM5_C2H_FATAL_ERR_STAT_ADDR, - EQDMA_CPM5_C2H_FATAL_ERR_ALL_MASK, - GLBL_ERR_STAT_ERR_C2H_ST_MASK, - &eqdma_cpm5_hw_st_c2h_err_process - }, - - /* H2C St errors */ - { - EQDMA_CPM5_ST_H2C_ERR_ZERO_LEN_DESC, - "Zero length descriptor error", - EQDMA_CPM5_H2C_ERR_MASK_ADDR, - EQDMA_CPM5_H2C_ERR_STAT_ADDR, - H2C_ERR_STAT_ZERO_LEN_DS_MASK, - GLBL_ERR_STAT_ERR_H2C_ST_MASK, - &eqdma_cpm5_hw_st_h2c_err_process - }, - { - EQDMA_CPM5_ST_H2C_ERR_SDI_MRKR_REQ_MOP, - "A non-EOP descriptor received", - EQDMA_CPM5_H2C_ERR_MASK_ADDR, - EQDMA_CPM5_H2C_ERR_STAT_ADDR, - H2C_ERR_STAT_SDI_MRKR_REQ_MOP_ERR_MASK, - GLBL_ERR_STAT_ERR_H2C_ST_MASK, - &eqdma_cpm5_hw_st_h2c_err_process - }, - { - EQDMA_CPM5_ST_H2C_ERR_NO_DMA_DSC, - "No DMA descriptor received error", - EQDMA_CPM5_H2C_ERR_MASK_ADDR, - EQDMA_CPM5_H2C_ERR_STAT_ADDR, - H2C_ERR_STAT_NO_DMA_DS_MASK, - GLBL_ERR_STAT_ERR_H2C_ST_MASK, - &eqdma_cpm5_hw_st_h2c_err_process - }, - { - EQDMA_CPM5_ST_H2C_ERR_SBE, - "Single bit error detected on H2C-ST data error", - EQDMA_CPM5_H2C_ERR_MASK_ADDR, - EQDMA_CPM5_H2C_ERR_STAT_ADDR, - H2C_ERR_STAT_SBE_MASK, - GLBL_ERR_STAT_ERR_H2C_ST_MASK, - &eqdma_cpm5_hw_st_h2c_err_process - }, - { - EQDMA_CPM5_ST_H2C_ERR_DBE, - "Double bit error detected on H2C-ST data error", - EQDMA_CPM5_H2C_ERR_MASK_ADDR, - EQDMA_CPM5_H2C_ERR_STAT_ADDR, - H2C_ERR_STAT_DBE_MASK, - GLBL_ERR_STAT_ERR_H2C_ST_MASK, - &eqdma_cpm5_hw_st_h2c_err_process - }, - { - EQDMA_CPM5_ST_H2C_ERR_PAR, - "Internal data parity error", - EQDMA_CPM5_H2C_ERR_MASK_ADDR, - EQDMA_CPM5_H2C_ERR_STAT_ADDR, - H2C_ERR_STAT_PAR_ERR_MASK, - GLBL_ERR_STAT_ERR_H2C_ST_MASK, - &eqdma_cpm5_hw_st_h2c_err_process - }, - { - EQDMA_CPM5_ST_H2C_ERR_ALL, - "All H2C errors", - EQDMA_CPM5_H2C_ERR_MASK_ADDR, - EQDMA_CPM5_H2C_ERR_STAT_ADDR, - EQDMA_CPM5_H2C_ERR_ALL_MASK, - GLBL_ERR_STAT_ERR_H2C_ST_MASK, - &eqdma_cpm5_hw_st_h2c_err_process - }, - - /* SBE errors */ - { - EQDMA_CPM5_SBE_1_ERR_RC_RRQ_EVEN_RAM, - "RC RRQ Even RAM single bit ECC error.", - EQDMA_CPM5_RAM_SBE_MSK_1_A_ADDR, - EQDMA_CPM5_RAM_SBE_STS_1_A_ADDR, - RAM_SBE_STS_1_A_RC_RRQ_EVEN_RAM_MASK, - GLBL_ERR_STAT_ERR_RAM_SBE_MASK, - &eqdma_cpm5_hw_ram_sbe_err_process - }, - { - EQDMA_CPM5_SBE_1_ERR_TAG_ODD_RAM, - "Tag Odd Ram single bit ECC error.", - EQDMA_CPM5_RAM_SBE_MSK_1_A_ADDR, - EQDMA_CPM5_RAM_SBE_STS_1_A_ADDR, - RAM_SBE_STS_1_A_TAG_ODD_RAM_MASK, - GLBL_ERR_STAT_ERR_RAM_SBE_MASK, - &eqdma_cpm5_hw_ram_sbe_err_process - }, - { - EQDMA_CPM5_SBE_1_ERR_TAG_EVEN_RAM, - "Tag Even Ram single bit ECC error.", - EQDMA_CPM5_RAM_SBE_MSK_1_A_ADDR, - EQDMA_CPM5_RAM_SBE_STS_1_A_ADDR, - RAM_SBE_STS_1_A_TAG_EVEN_RAM_MASK, - GLBL_ERR_STAT_ERR_RAM_SBE_MASK, - &eqdma_cpm5_hw_ram_sbe_err_process - }, - { - EQDMA_CPM5_SBE_1_ERR_PFCH_CTXT_CAM_RAM_0, - "Pfch Ctxt CAM RAM 0 single bit ECC error.", - EQDMA_CPM5_RAM_SBE_MSK_1_A_ADDR, - EQDMA_CPM5_RAM_SBE_STS_1_A_ADDR, - RAM_SBE_STS_1_A_PFCH_CTXT_CAM_RAM_0_MASK, - GLBL_ERR_STAT_ERR_RAM_SBE_MASK, - &eqdma_cpm5_hw_ram_sbe_err_process - }, - { - EQDMA_CPM5_SBE_1_ERR_PFCH_CTXT_CAM_RAM_1, - "Pfch Ctxt CAM RAM 1 single bit ECC error.", - EQDMA_CPM5_RAM_SBE_MSK_1_A_ADDR, - EQDMA_CPM5_RAM_SBE_STS_1_A_ADDR, - RAM_SBE_STS_1_A_PFCH_CTXT_CAM_RAM_1_MASK, - GLBL_ERR_STAT_ERR_RAM_SBE_MASK, - &eqdma_cpm5_hw_ram_sbe_err_process - }, - { - EQDMA_CPM5_SBE_1_ERR_ALL, - "All SBE Errors.", - EQDMA_CPM5_RAM_SBE_MSK_1_A_ADDR, - EQDMA_CPM5_RAM_SBE_STS_1_A_ADDR, - EQDMA_CPM5_SBE_ERR_ALL_MASK, - GLBL_ERR_STAT_ERR_RAM_SBE_MASK, - &eqdma_cpm5_hw_ram_sbe_err_process - }, - { - EQDMA_CPM5_SBE_ERR_MI_H2C0_DAT, - "H2C MM data buffer single bit ECC error", - EQDMA_CPM5_RAM_SBE_MSK_A_ADDR, - EQDMA_CPM5_RAM_SBE_STS_A_ADDR, - RAM_SBE_STS_A_MI_H2C0_DAT_MASK, - GLBL_ERR_STAT_ERR_RAM_SBE_MASK, - &eqdma_cpm5_hw_ram_sbe_err_process - }, - { - EQDMA_CPM5_SBE_ERR_MI_H2C1_DAT, - "H2C MM data buffer single bit ECC error", - EQDMA_CPM5_RAM_SBE_MSK_A_ADDR, - EQDMA_CPM5_RAM_SBE_STS_A_ADDR, - RAM_SBE_STS_A_MI_H2C1_DAT_MASK, - GLBL_ERR_STAT_ERR_RAM_SBE_MASK, - &eqdma_cpm5_hw_ram_sbe_err_process - }, - { - EQDMA_CPM5_SBE_ERR_MI_H2C2_DAT, - "H2C MM data buffer single bit ECC error", - EQDMA_CPM5_RAM_SBE_MSK_A_ADDR, - EQDMA_CPM5_RAM_SBE_STS_A_ADDR, - RAM_SBE_STS_A_MI_H2C2_DAT_MASK, - GLBL_ERR_STAT_ERR_RAM_SBE_MASK, - &eqdma_cpm5_hw_ram_sbe_err_process - }, - { - EQDMA_CPM5_SBE_ERR_MI_H2C3_DAT, - "H2C MM data buffer single bit ECC error", - EQDMA_CPM5_RAM_SBE_MSK_A_ADDR, - EQDMA_CPM5_RAM_SBE_STS_A_ADDR, - RAM_SBE_STS_A_MI_H2C3_DAT_MASK, - GLBL_ERR_STAT_ERR_RAM_SBE_MASK, - &eqdma_cpm5_hw_ram_sbe_err_process - }, - { - EQDMA_CPM5_SBE_ERR_MI_C2H0_DAT, - "C2H MM data buffer single bit ECC error", - EQDMA_CPM5_RAM_SBE_MSK_A_ADDR, - EQDMA_CPM5_RAM_SBE_STS_A_ADDR, - RAM_SBE_STS_A_MI_C2H0_DAT_MASK, - GLBL_ERR_STAT_ERR_RAM_SBE_MASK, - &eqdma_cpm5_hw_ram_sbe_err_process - }, - { - EQDMA_CPM5_SBE_ERR_MI_C2H1_DAT, - "C2H MM data buffer single bit ECC error", - EQDMA_CPM5_RAM_SBE_MSK_A_ADDR, - EQDMA_CPM5_RAM_SBE_STS_A_ADDR, - RAM_SBE_STS_A_MI_C2H1_DAT_MASK, - GLBL_ERR_STAT_ERR_RAM_SBE_MASK, - &eqdma_cpm5_hw_ram_sbe_err_process - }, -{ - EQDMA_CPM5_SBE_ERR_MI_C2H2_DAT, - "C2H MM data buffer single bit ECC error", - EQDMA_CPM5_RAM_SBE_MSK_A_ADDR, - EQDMA_CPM5_RAM_SBE_STS_A_ADDR, - RAM_SBE_STS_A_MI_C2H2_DAT_MASK, - GLBL_ERR_STAT_ERR_RAM_SBE_MASK, - &eqdma_cpm5_hw_ram_sbe_err_process - }, - { - EQDMA_CPM5_SBE_ERR_MI_C2H3_DAT, - "C2H MM data buffer single bit ECC error", - EQDMA_CPM5_RAM_SBE_MSK_A_ADDR, - EQDMA_CPM5_RAM_SBE_STS_A_ADDR, - RAM_SBE_STS_A_MI_C2H3_DAT_MASK, - GLBL_ERR_STAT_ERR_RAM_SBE_MASK, - &eqdma_cpm5_hw_ram_sbe_err_process - }, - { - EQDMA_CPM5_SBE_ERR_H2C_RD_BRG_DAT, - "Bridge master read single bit ECC error", - EQDMA_CPM5_RAM_SBE_MSK_A_ADDR, - EQDMA_CPM5_RAM_SBE_STS_A_ADDR, - RAM_SBE_STS_A_H2C_RD_BRG_DAT_MASK, - GLBL_ERR_STAT_ERR_RAM_SBE_MASK, - &eqdma_cpm5_hw_ram_sbe_err_process - }, - { - EQDMA_CPM5_SBE_ERR_H2C_WR_BRG_DAT, - "Bridge master write single bit ECC error", - EQDMA_CPM5_RAM_SBE_MSK_A_ADDR, - EQDMA_CPM5_RAM_SBE_STS_A_ADDR, - RAM_SBE_STS_A_H2C_WR_BRG_DAT_MASK, - GLBL_ERR_STAT_ERR_RAM_SBE_MASK, - &eqdma_cpm5_hw_ram_sbe_err_process - }, - { - EQDMA_CPM5_SBE_ERR_C2H_RD_BRG_DAT, - "Bridge slave read data buffer single bit ECC error", - EQDMA_CPM5_RAM_SBE_MSK_A_ADDR, - EQDMA_CPM5_RAM_SBE_STS_A_ADDR, - RAM_SBE_STS_A_C2H_RD_BRG_DAT_MASK, - GLBL_ERR_STAT_ERR_RAM_SBE_MASK, - &eqdma_cpm5_hw_ram_sbe_err_process - }, - { - EQDMA_CPM5_SBE_ERR_C2H_WR_BRG_DAT, - "Bridge slave write data buffer single bit ECC error", - EQDMA_CPM5_RAM_SBE_MSK_A_ADDR, - EQDMA_CPM5_RAM_SBE_STS_A_ADDR, - RAM_SBE_STS_A_C2H_WR_BRG_DAT_MASK, - GLBL_ERR_STAT_ERR_RAM_SBE_MASK, - &eqdma_cpm5_hw_ram_sbe_err_process - }, - { - EQDMA_CPM5_SBE_ERR_FUNC_MAP, - "Function map RAM single bit ECC error", - EQDMA_CPM5_RAM_SBE_MSK_A_ADDR, - EQDMA_CPM5_RAM_SBE_STS_A_ADDR, - RAM_SBE_STS_A_FUNC_MAP_MASK, - GLBL_ERR_STAT_ERR_RAM_SBE_MASK, - &eqdma_cpm5_hw_ram_sbe_err_process - }, - { - EQDMA_CPM5_SBE_ERR_DSC_HW_CTXT, - "Descriptor engine hardware context RAM single bit ECC error", - EQDMA_CPM5_RAM_SBE_MSK_A_ADDR, - EQDMA_CPM5_RAM_SBE_STS_A_ADDR, - RAM_SBE_STS_A_DSC_HW_CTXT_MASK, - GLBL_ERR_STAT_ERR_RAM_SBE_MASK, - &eqdma_cpm5_hw_ram_sbe_err_process - }, - { - EQDMA_CPM5_SBE_ERR_DSC_CRD_RCV, - "Descriptor engine receive credit context RAM single bit ECC error", - EQDMA_CPM5_RAM_SBE_MSK_A_ADDR, - EQDMA_CPM5_RAM_SBE_STS_A_ADDR, - RAM_SBE_STS_A_DSC_CRD_RCV_MASK, - GLBL_ERR_STAT_ERR_RAM_SBE_MASK, - &eqdma_cpm5_hw_ram_sbe_err_process - }, - { - EQDMA_CPM5_SBE_ERR_DSC_SW_CTXT, - "Descriptor engine software context RAM single bit ECC error", - EQDMA_CPM5_RAM_SBE_MSK_A_ADDR, - EQDMA_CPM5_RAM_SBE_STS_A_ADDR, - RAM_SBE_STS_A_DSC_SW_CTXT_MASK, - GLBL_ERR_STAT_ERR_RAM_SBE_MASK, - &eqdma_cpm5_hw_ram_sbe_err_process - }, - { - EQDMA_CPM5_SBE_ERR_DSC_CPLI, - "Descriptor engine fetch completion information RAM single bit ECC error", - EQDMA_CPM5_RAM_SBE_MSK_A_ADDR, - EQDMA_CPM5_RAM_SBE_STS_A_ADDR, - RAM_SBE_STS_A_DSC_CPLI_MASK, - GLBL_ERR_STAT_ERR_RAM_SBE_MASK, - &eqdma_cpm5_hw_ram_sbe_err_process - }, - { - EQDMA_CPM5_SBE_ERR_DSC_CPLD, - "Descriptor engine fetch completion data RAM single bit ECC error", - EQDMA_CPM5_RAM_SBE_MSK_A_ADDR, - EQDMA_CPM5_RAM_SBE_STS_A_ADDR, - RAM_SBE_STS_A_DSC_CPLD_MASK, - GLBL_ERR_STAT_ERR_RAM_SBE_MASK, - &eqdma_cpm5_hw_ram_sbe_err_process - }, - { - EQDMA_CPM5_SBE_ERR_MI_TL_SLV_FIFO_RAM, - "TL Slavle FIFO RAM single bit ECC error", - EQDMA_CPM5_RAM_SBE_MSK_A_ADDR, - EQDMA_CPM5_RAM_SBE_STS_A_ADDR, - RAM_SBE_STS_A_MI_TL_SLV_FIFO_RAM_MASK, - GLBL_ERR_STAT_ERR_RAM_SBE_MASK, - &eqdma_cpm5_hw_ram_sbe_err_process - }, - { - EQDMA_CPM5_SBE_ERR_TIMER_FIFO_RAM, - "Timer fifo RAM single bit ECC error", - EQDMA_CPM5_RAM_SBE_MSK_A_ADDR, - EQDMA_CPM5_RAM_SBE_STS_A_ADDR, - RAM_SBE_STS_A_TIMER_FIFO_RAM_MASK, - GLBL_ERR_STAT_ERR_RAM_SBE_MASK, - &eqdma_cpm5_hw_ram_sbe_err_process - }, - { - EQDMA_CPM5_SBE_ERR_QID_FIFO_RAM, - "C2H ST QID FIFO RAM single bit ECC error", - EQDMA_CPM5_RAM_SBE_MSK_A_ADDR, - EQDMA_CPM5_RAM_SBE_STS_A_ADDR, - RAM_SBE_STS_A_QID_FIFO_RAM_MASK, - GLBL_ERR_STAT_ERR_RAM_SBE_MASK, - &eqdma_cpm5_hw_ram_sbe_err_process - }, - { - EQDMA_CPM5_SBE_ERR_WRB_COAL_DATA_RAM, - "Writeback Coalescing RAM single bit ECC error", - EQDMA_CPM5_RAM_SBE_MSK_A_ADDR, - EQDMA_CPM5_RAM_SBE_STS_A_ADDR, - RAM_SBE_STS_A_WRB_COAL_DATA_RAM_MASK, - GLBL_ERR_STAT_ERR_RAM_SBE_MASK, - &eqdma_cpm5_hw_ram_sbe_err_process - }, - { - EQDMA_CPM5_SBE_ERR_INT_CTXT_RAM, - "Interrupt context RAM single bit ECC error", - EQDMA_CPM5_RAM_SBE_MSK_A_ADDR, - EQDMA_CPM5_RAM_SBE_STS_A_ADDR, - RAM_SBE_STS_A_INT_CTXT_RAM_MASK, - GLBL_ERR_STAT_ERR_RAM_SBE_MASK, - &eqdma_cpm5_hw_ram_sbe_err_process - }, - { - EQDMA_CPM5_SBE_ERR_DESC_REQ_FIFO_RAM, - "C2H ST descriptor request RAM single bit ECC error", - EQDMA_CPM5_RAM_SBE_MSK_A_ADDR, - EQDMA_CPM5_RAM_SBE_STS_A_ADDR, - RAM_SBE_STS_A_DESC_REQ_FIFO_RAM_MASK, - GLBL_ERR_STAT_ERR_RAM_SBE_MASK, - &eqdma_cpm5_hw_ram_sbe_err_process - }, - { - EQDMA_CPM5_SBE_ERR_PFCH_CTXT_RAM, - "C2H ST prefetch RAM single bit ECC error", - EQDMA_CPM5_RAM_SBE_MSK_A_ADDR, - EQDMA_CPM5_RAM_SBE_STS_A_ADDR, - RAM_SBE_STS_A_PFCH_CTXT_RAM_MASK, - GLBL_ERR_STAT_ERR_RAM_SBE_MASK, - &eqdma_cpm5_hw_ram_sbe_err_process - }, - { - EQDMA_CPM5_SBE_ERR_WRB_CTXT_RAM, - "C2H ST completion context RAM single bit ECC error", - EQDMA_CPM5_RAM_SBE_MSK_A_ADDR, - EQDMA_CPM5_RAM_SBE_STS_A_ADDR, - RAM_SBE_STS_A_WRB_CTXT_RAM_MASK, - GLBL_ERR_STAT_ERR_RAM_SBE_MASK, - &eqdma_cpm5_hw_ram_sbe_err_process - }, - { - EQDMA_CPM5_SBE_ERR_PFCH_LL_RAM, - "C2H ST prefetch list RAM single bit ECC error", - EQDMA_CPM5_RAM_SBE_MSK_A_ADDR, - EQDMA_CPM5_RAM_SBE_STS_A_ADDR, - RAM_SBE_STS_A_PFCH_LL_RAM_MASK, - GLBL_ERR_STAT_ERR_RAM_SBE_MASK, - &eqdma_cpm5_hw_ram_sbe_err_process - }, - { - EQDMA_CPM5_SBE_ERR_PEND_FIFO_RAM, - "Pend FIFO RAM single bit ECC error", - EQDMA_CPM5_RAM_SBE_MSK_A_ADDR, - EQDMA_CPM5_RAM_SBE_STS_A_ADDR, - RAM_SBE_STS_A_PEND_FIFO_RAM_MASK, - GLBL_ERR_STAT_ERR_RAM_SBE_MASK, - &eqdma_cpm5_hw_ram_sbe_err_process - }, - { - EQDMA_CPM5_SBE_ERR_RC_RRQ_ODD_RAM, - "RC RRQ Odd RAM single bit ECC error.", - EQDMA_CPM5_RAM_SBE_MSK_A_ADDR, - EQDMA_CPM5_RAM_SBE_STS_A_ADDR, - RAM_SBE_STS_A_RC_RRQ_ODD_RAM_MASK, - GLBL_ERR_STAT_ERR_RAM_SBE_MASK, - &eqdma_cpm5_hw_ram_sbe_err_process - }, - { - EQDMA_CPM5_SBE_ERR_ALL, - "All SBE errors", - EQDMA_CPM5_RAM_SBE_MSK_A_ADDR, - EQDMA_CPM5_RAM_SBE_STS_A_ADDR, - EQDMA_CPM5_SBE_ERR_ALL_MASK, - GLBL_ERR_STAT_ERR_RAM_SBE_MASK, - &eqdma_cpm5_hw_ram_sbe_err_process - }, - - - /* DBE errors */ - { - EQDMA_CPM5_DBE_1_ERR_RC_RRQ_EVEN_RAM, - "RC RRQ Odd RAM double bit ECC error.", - EQDMA_CPM5_RAM_DBE_MSK_1_A_ADDR, - EQDMA_CPM5_RAM_DBE_STS_1_A_ADDR, - RAM_DBE_STS_1_A_RC_RRQ_EVEN_RAM_MASK, - GLBL_ERR_STAT_ERR_RAM_DBE_MASK, - &eqdma_cpm5_hw_ram_dbe_err_process - }, - { - EQDMA_CPM5_DBE_1_ERR_TAG_ODD_RAM, - "Tag Odd Ram double bit ECC error.", - EQDMA_CPM5_RAM_DBE_MSK_1_A_ADDR, - EQDMA_CPM5_RAM_DBE_STS_1_A_ADDR, - RAM_DBE_STS_1_A_TAG_ODD_RAM_MASK, - GLBL_ERR_STAT_ERR_RAM_DBE_MASK, - &eqdma_cpm5_hw_ram_dbe_err_process - }, - { - EQDMA_CPM5_DBE_1_ERR_TAG_EVEN_RAM, - "Tag Even Ram double bit ECC error.", - EQDMA_CPM5_RAM_DBE_MSK_1_A_ADDR, - EQDMA_CPM5_RAM_DBE_STS_1_A_ADDR, - RAM_DBE_STS_1_A_TAG_EVEN_RAM_MASK, - GLBL_ERR_STAT_ERR_RAM_DBE_MASK, - &eqdma_cpm5_hw_ram_dbe_err_process - }, - { - EQDMA_CPM5_DBE_1_ERR_PFCH_CTXT_CAM_RAM_0, - "Pfch Ctxt CAM RAM 0 double bit ECC error.", - EQDMA_CPM5_RAM_DBE_MSK_1_A_ADDR, - EQDMA_CPM5_RAM_DBE_STS_1_A_ADDR, - RAM_DBE_STS_1_A_PFCH_CTXT_CAM_RAM_0_MASK, - GLBL_ERR_STAT_ERR_RAM_DBE_MASK, - &eqdma_cpm5_hw_ram_dbe_err_process - }, - { - EQDMA_CPM5_DBE_1_ERR_PFCH_CTXT_CAM_RAM_1, - "Pfch Ctxt CAM RAM double bit ECC error.", - EQDMA_CPM5_RAM_DBE_MSK_1_A_ADDR, - EQDMA_CPM5_RAM_DBE_STS_1_A_ADDR, - RAM_DBE_STS_1_A_PFCH_CTXT_CAM_RAM_0_MASK, - GLBL_ERR_STAT_ERR_RAM_DBE_MASK, - &eqdma_cpm5_hw_ram_dbe_err_process - }, - { - EQDMA_CPM5_DBE_1_ERR_ALL, - "All DBE errors", - EQDMA_CPM5_RAM_DBE_MSK_1_A_ADDR, - EQDMA_CPM5_RAM_DBE_STS_1_A_ADDR, - EQDMA_CPM5_DBE_ERR_ALL_MASK, - GLBL_ERR_STAT_ERR_RAM_DBE_MASK, - &eqdma_cpm5_hw_ram_dbe_err_process - }, - { - EQDMA_CPM5_DBE_ERR_MI_H2C0_DAT, - "H2C MM data buffer double bit ECC error", - EQDMA_CPM5_RAM_DBE_MSK_A_ADDR, - EQDMA_CPM5_RAM_DBE_STS_A_ADDR, - RAM_DBE_STS_A_MI_H2C0_DAT_MASK, - GLBL_ERR_STAT_ERR_RAM_DBE_MASK, - &eqdma_cpm5_hw_ram_dbe_err_process - }, - { - EQDMA_CPM5_DBE_ERR_MI_H2C1_DAT, - "H2C MM data buffer double bit ECC error", - EQDMA_CPM5_RAM_DBE_MSK_A_ADDR, - EQDMA_CPM5_RAM_DBE_STS_A_ADDR, - RAM_DBE_STS_A_MI_H2C1_DAT_MASK, - GLBL_ERR_STAT_ERR_RAM_DBE_MASK, - &eqdma_cpm5_hw_ram_dbe_err_process - }, - { - EQDMA_CPM5_DBE_ERR_MI_H2C2_DAT, - "H2C MM data buffer double bit ECC error", - EQDMA_CPM5_RAM_DBE_MSK_A_ADDR, - EQDMA_CPM5_RAM_DBE_STS_A_ADDR, - RAM_DBE_STS_A_MI_H2C2_DAT_MASK, - GLBL_ERR_STAT_ERR_RAM_DBE_MASK, - &eqdma_cpm5_hw_ram_dbe_err_process - }, - { - EQDMA_CPM5_DBE_ERR_MI_H2C3_DAT, - "H2C MM data buffer double bit ECC error", - EQDMA_CPM5_RAM_DBE_MSK_A_ADDR, - EQDMA_CPM5_RAM_DBE_STS_A_ADDR, - RAM_DBE_STS_A_MI_H2C3_DAT_MASK, - GLBL_ERR_STAT_ERR_RAM_DBE_MASK, - &eqdma_cpm5_hw_ram_dbe_err_process - }, - { - EQDMA_CPM5_DBE_ERR_MI_C2H0_DAT, - "C2H MM data buffer double bit ECC error", - EQDMA_CPM5_RAM_DBE_MSK_A_ADDR, - EQDMA_CPM5_RAM_DBE_STS_A_ADDR, - RAM_DBE_STS_A_MI_C2H0_DAT_MASK, - GLBL_ERR_STAT_ERR_RAM_DBE_MASK, - &eqdma_cpm5_hw_ram_dbe_err_process - }, - { - EQDMA_CPM5_DBE_ERR_MI_C2H1_DAT, - "C2H MM data buffer double bit ECC error", - EQDMA_CPM5_RAM_DBE_MSK_A_ADDR, - EQDMA_CPM5_RAM_DBE_STS_A_ADDR, - RAM_DBE_STS_A_MI_C2H1_DAT_MASK, - GLBL_ERR_STAT_ERR_RAM_DBE_MASK, - &eqdma_cpm5_hw_ram_dbe_err_process - }, - { - EQDMA_CPM5_DBE_ERR_MI_C2H2_DAT, - "C2H MM data buffer double bit ECC error", - EQDMA_CPM5_RAM_DBE_MSK_A_ADDR, - EQDMA_CPM5_RAM_DBE_STS_A_ADDR, - RAM_DBE_STS_A_MI_C2H2_DAT_MASK, - GLBL_ERR_STAT_ERR_RAM_DBE_MASK, - &eqdma_cpm5_hw_ram_dbe_err_process - }, - { - EQDMA_CPM5_DBE_ERR_MI_C2H3_DAT, - "C2H MM data buffer double bit ECC error", - EQDMA_CPM5_RAM_DBE_MSK_A_ADDR, - EQDMA_CPM5_RAM_DBE_STS_A_ADDR, - RAM_DBE_STS_A_MI_C2H3_DAT_MASK, - GLBL_ERR_STAT_ERR_RAM_DBE_MASK, - &eqdma_cpm5_hw_ram_dbe_err_process - }, - { - EQDMA_CPM5_DBE_ERR_H2C_RD_BRG_DAT, - "Bridge master read double bit ECC error", - EQDMA_CPM5_RAM_DBE_MSK_A_ADDR, - EQDMA_CPM5_RAM_DBE_STS_A_ADDR, - RAM_DBE_STS_A_H2C_RD_BRG_DAT_MASK, - GLBL_ERR_STAT_ERR_RAM_DBE_MASK, - &eqdma_cpm5_hw_ram_dbe_err_process - }, - { - EQDMA_CPM5_DBE_ERR_H2C_WR_BRG_DAT, - "Bridge master write double bit ECC error", - EQDMA_CPM5_RAM_DBE_MSK_A_ADDR, - EQDMA_CPM5_RAM_DBE_STS_A_ADDR, - RAM_DBE_STS_A_H2C_WR_BRG_DAT_MASK, - GLBL_ERR_STAT_ERR_RAM_DBE_MASK, - &eqdma_cpm5_hw_ram_dbe_err_process - }, - { - EQDMA_CPM5_DBE_ERR_C2H_RD_BRG_DAT, - "Bridge slave read data buffer double bit ECC error", - EQDMA_CPM5_RAM_DBE_MSK_A_ADDR, - EQDMA_CPM5_RAM_DBE_STS_A_ADDR, - RAM_DBE_STS_A_C2H_RD_BRG_DAT_MASK, - GLBL_ERR_STAT_ERR_RAM_DBE_MASK, - &eqdma_cpm5_hw_ram_dbe_err_process - }, - { - EQDMA_CPM5_DBE_ERR_C2H_WR_BRG_DAT, - "Bridge slave write data buffer double bit ECC error", - EQDMA_CPM5_RAM_DBE_MSK_A_ADDR, - EQDMA_CPM5_RAM_DBE_STS_A_ADDR, - RAM_DBE_STS_A_C2H_WR_BRG_DAT_MASK, - GLBL_ERR_STAT_ERR_RAM_DBE_MASK, - &eqdma_cpm5_hw_ram_dbe_err_process - }, - { - EQDMA_CPM5_DBE_ERR_FUNC_MAP, - "Function map RAM double bit ECC error", - EQDMA_CPM5_RAM_DBE_MSK_A_ADDR, - EQDMA_CPM5_RAM_DBE_STS_A_ADDR, - RAM_DBE_STS_A_FUNC_MAP_MASK, - GLBL_ERR_STAT_ERR_RAM_DBE_MASK, - &eqdma_cpm5_hw_ram_dbe_err_process - }, - { - EQDMA_CPM5_DBE_ERR_DSC_HW_CTXT, - "Descriptor engine hardware context RAM double bit ECC error", - EQDMA_CPM5_RAM_DBE_MSK_A_ADDR, - EQDMA_CPM5_RAM_DBE_STS_A_ADDR, - RAM_DBE_STS_A_DSC_HW_CTXT_MASK, - GLBL_ERR_STAT_ERR_RAM_DBE_MASK, - &eqdma_cpm5_hw_ram_dbe_err_process - }, - { - EQDMA_CPM5_DBE_ERR_DSC_CRD_RCV, - "Descriptor engine receive credit context RAM double bit ECC error", - EQDMA_CPM5_RAM_DBE_MSK_A_ADDR, - EQDMA_CPM5_RAM_DBE_STS_A_ADDR, - RAM_DBE_STS_A_DSC_CRD_RCV_MASK, - GLBL_ERR_STAT_ERR_RAM_DBE_MASK, - &eqdma_cpm5_hw_ram_dbe_err_process - }, - { - EQDMA_CPM5_DBE_ERR_DSC_SW_CTXT, - "Descriptor engine software context RAM double bit ECC error", - EQDMA_CPM5_RAM_DBE_MSK_A_ADDR, - EQDMA_CPM5_RAM_DBE_STS_A_ADDR, - RAM_DBE_STS_A_DSC_SW_CTXT_MASK, - GLBL_ERR_STAT_ERR_RAM_DBE_MASK, - &eqdma_cpm5_hw_ram_dbe_err_process - }, - { - EQDMA_CPM5_DBE_ERR_DSC_CPLI, - "Descriptor engine fetch completion information RAM double bit ECC error", - EQDMA_CPM5_RAM_DBE_MSK_A_ADDR, - EQDMA_CPM5_RAM_DBE_STS_A_ADDR, - RAM_DBE_STS_A_DSC_CPLI_MASK, - GLBL_ERR_STAT_ERR_RAM_DBE_MASK, - &eqdma_cpm5_hw_ram_dbe_err_process - }, - { - EQDMA_CPM5_DBE_ERR_DSC_CPLD, - "Descriptor engine fetch completion data RAM double bit ECC error", - EQDMA_CPM5_RAM_DBE_MSK_A_ADDR, - EQDMA_CPM5_RAM_DBE_STS_A_ADDR, - RAM_DBE_STS_A_DSC_CPLD_MASK, - GLBL_ERR_STAT_ERR_RAM_DBE_MASK, - &eqdma_cpm5_hw_ram_dbe_err_process - }, - { - EQDMA_CPM5_DBE_ERR_MI_TL_SLV_FIFO_RAM, - "TL Slave FIFO RAM double bit ECC error", - EQDMA_CPM5_RAM_DBE_MSK_A_ADDR, - EQDMA_CPM5_RAM_DBE_STS_A_ADDR, - RAM_DBE_STS_A_MI_TL_SLV_FIFO_RAM_MASK, - GLBL_ERR_STAT_ERR_RAM_DBE_MASK, - &eqdma_cpm5_hw_ram_dbe_err_process - }, - { - EQDMA_CPM5_DBE_ERR_TIMER_FIFO_RAM, - "Timer fifo RAM double bit ECC error", - EQDMA_CPM5_RAM_DBE_MSK_A_ADDR, - EQDMA_CPM5_RAM_DBE_STS_A_ADDR, - RAM_DBE_STS_A_TIMER_FIFO_RAM_MASK, - GLBL_ERR_STAT_ERR_RAM_DBE_MASK, - &eqdma_cpm5_hw_ram_dbe_err_process - }, - { - EQDMA_CPM5_DBE_ERR_QID_FIFO_RAM, - "C2H ST QID FIFO RAM double bit ECC error", - EQDMA_CPM5_RAM_DBE_MSK_A_ADDR, - EQDMA_CPM5_RAM_DBE_STS_A_ADDR, - RAM_DBE_STS_A_QID_FIFO_RAM_MASK, - GLBL_ERR_STAT_ERR_RAM_DBE_MASK, - &eqdma_cpm5_hw_ram_dbe_err_process - }, - { - EQDMA_CPM5_DBE_ERR_WRB_COAL_DATA_RAM, - "Writeback Coalescing RAM double bit ECC error", - EQDMA_CPM5_RAM_DBE_MSK_A_ADDR, - EQDMA_CPM5_RAM_DBE_STS_A_ADDR, - RAM_DBE_STS_A_WRB_COAL_DATA_RAM_MASK, - GLBL_ERR_STAT_ERR_RAM_DBE_MASK, - &eqdma_cpm5_hw_ram_dbe_err_process - }, - { - EQDMA_CPM5_DBE_ERR_INT_CTXT_RAM, - "Interrupt context RAM double bit ECC error", - EQDMA_CPM5_RAM_DBE_MSK_A_ADDR, - EQDMA_CPM5_RAM_DBE_STS_A_ADDR, - RAM_DBE_STS_A_INT_CTXT_RAM_MASK, - GLBL_ERR_STAT_ERR_RAM_DBE_MASK, - &eqdma_cpm5_hw_ram_dbe_err_process - }, - { - EQDMA_CPM5_DBE_ERR_DESC_REQ_FIFO_RAM, - "C2H ST descriptor request RAM double bit ECC error", - EQDMA_CPM5_RAM_DBE_MSK_A_ADDR, - EQDMA_CPM5_RAM_DBE_STS_A_ADDR, - RAM_DBE_STS_A_DESC_REQ_FIFO_RAM_MASK, - GLBL_ERR_STAT_ERR_RAM_DBE_MASK, - &eqdma_cpm5_hw_ram_dbe_err_process - }, - { - EQDMA_CPM5_DBE_ERR_PFCH_CTXT_RAM, - "C2H ST prefetch RAM double bit ECC error", - EQDMA_CPM5_RAM_DBE_MSK_A_ADDR, - EQDMA_CPM5_RAM_DBE_STS_A_ADDR, - RAM_DBE_STS_A_PFCH_CTXT_RAM_MASK, - GLBL_ERR_STAT_ERR_RAM_DBE_MASK, - &eqdma_cpm5_hw_ram_dbe_err_process - }, - { - EQDMA_CPM5_DBE_ERR_WRB_CTXT_RAM, - "C2H ST completion context RAM double bit ECC error", - EQDMA_CPM5_RAM_DBE_MSK_A_ADDR, - EQDMA_CPM5_RAM_DBE_STS_A_ADDR, - RAM_DBE_STS_A_WRB_CTXT_RAM_MASK, - GLBL_ERR_STAT_ERR_RAM_DBE_MASK, - &eqdma_cpm5_hw_ram_dbe_err_process - }, - { - EQDMA_CPM5_DBE_ERR_PFCH_LL_RAM, - "C2H ST prefetch list RAM double bit ECC error", - EQDMA_CPM5_RAM_DBE_MSK_A_ADDR, - EQDMA_CPM5_RAM_DBE_STS_A_ADDR, - RAM_DBE_STS_A_PFCH_LL_RAM_MASK, - GLBL_ERR_STAT_ERR_RAM_DBE_MASK, - &eqdma_cpm5_hw_ram_dbe_err_process - }, - { - EQDMA_CPM5_DBE_ERR_PEND_FIFO_RAM, - "Pend FIFO RAM double bit ECC error", - EQDMA_CPM5_RAM_DBE_MSK_A_ADDR, - EQDMA_CPM5_RAM_DBE_STS_A_ADDR, - RAM_DBE_STS_A_PEND_FIFO_RAM_MASK, - GLBL_ERR_STAT_ERR_RAM_DBE_MASK, - &eqdma_cpm5_hw_ram_dbe_err_process - }, - { - EQDMA_CPM5_DBE_ERR_RC_RRQ_ODD_RAM, - "RC RRQ Odd RAM double bit ECC error.", - EQDMA_CPM5_RAM_DBE_MSK_A_ADDR, - EQDMA_CPM5_RAM_DBE_STS_A_ADDR, - RAM_DBE_STS_A_RC_RRQ_ODD_RAM_MASK, - GLBL_ERR_STAT_ERR_RAM_DBE_MASK, - &eqdma_cpm5_hw_ram_dbe_err_process - }, - { - EQDMA_CPM5_DBE_ERR_ALL, - "All DBE errors", - EQDMA_CPM5_RAM_DBE_MSK_A_ADDR, - EQDMA_CPM5_RAM_DBE_STS_A_ADDR, - EQDMA_CPM5_DBE_ERR_ALL_MASK, - GLBL_ERR_STAT_ERR_RAM_DBE_MASK, - &eqdma_cpm5_hw_ram_dbe_err_process - }, - - /* MM C2H Engine 0 errors */ - { - EQDMA_CPM5_MM_C2H_WR_SLR_ERR, - "MM C2H0 WR SLV Error", - EQDMA_CPM5_C2H_MM_ERR_CODE_ENABLE_MASK_ADDR, - EQDMA_CPM5_C2H_MM_STATUS_ADDR, - C2H_MM_ERR_CODE_ENABLE_WR_SLV_ERR_MASK, - GLBL_ERR_STAT_ERR_C2H_MM_0_MASK, - &eqdma_cpm5_mm_c2h0_err_process - }, - { - EQDMA_CPM5_MM_C2H_RD_SLR_ERR, - "MM C2H0 RD SLV Error", - EQDMA_CPM5_C2H_MM_ERR_CODE_ENABLE_MASK_ADDR, - EQDMA_CPM5_C2H_MM_STATUS_ADDR, - C2H_MM_ERR_CODE_ENABLE_RD_SLV_ERR_MASK, - GLBL_ERR_STAT_ERR_C2H_MM_0_MASK, - &eqdma_cpm5_mm_c2h0_err_process - }, - { - EQDMA_CPM5_MM_C2H_WR_FLR_ERR, - "MM C2H0 WR FLR Error", - EQDMA_CPM5_C2H_MM_ERR_CODE_ENABLE_MASK_ADDR, - EQDMA_CPM5_C2H_MM_STATUS_ADDR, - C2H_MM_ERR_CODE_ENABLE_WR_FLR_MASK, - GLBL_ERR_STAT_ERR_C2H_MM_0_MASK, - &eqdma_cpm5_mm_c2h0_err_process - }, - { - EQDMA_CPM5_MM_C2H_UR_ERR, - "MM C2H0 Unsupported Request Error", - EQDMA_CPM5_C2H_MM_ERR_CODE_ENABLE_MASK_ADDR, - EQDMA_CPM5_C2H_MM_STATUS_ADDR, - C2H_MM_ERR_CODE_ENABLE_WR_UR_MASK, - GLBL_ERR_STAT_ERR_C2H_MM_0_MASK, - &eqdma_cpm5_mm_c2h0_err_process - }, - { - EQDMA_CPM5_MM_C2H_WR_UC_RAM_ERR, - "MM C2H0 Write Uncorrectable RAM Error", - EQDMA_CPM5_C2H_MM_ERR_CODE_ENABLE_MASK_ADDR, - EQDMA_CPM5_C2H_MM_STATUS_ADDR, - C2H_MM_ERR_CODE_ENABLE_WR_UC_RAM_MASK, - GLBL_ERR_STAT_ERR_C2H_MM_0_MASK, - &eqdma_cpm5_mm_c2h0_err_process - }, - { - EQDMA_CPM5_MM_C2H_ERR_ALL, - "All MM C2H Errors", - EQDMA_CPM5_C2H_MM_ERR_CODE_ENABLE_MASK_ADDR, - EQDMA_CPM5_C2H_MM_STATUS_ADDR, - EQDMA_CPM5_MM_C2H_ERR_ALL_MASK, - GLBL_ERR_STAT_ERR_C2H_MM_0_MASK, - &eqdma_cpm5_hw_desc_err_process - }, - /* MM H2C Engine 0 Errors */ - { - EQDMA_CPM5_MM_H2C0_RD_HDR_POISON_ERR, - "MM H2C0 Read cmpt header pison Error", - EQDMA_CPM5_H2C_MM_ERR_CODE_ENABLE_MASK_ADDR, - EQDMA_CPM5_H2C_MM_STATUS_ADDR, - H2C_MM_ERR_CODE_ENABLE_RD_HRD_POISON_ERR_MASK, - GLBL_ERR_STAT_ERR_H2C_MM_0_MASK, - &eqdma_cpm5_mm_h2c0_err_process - }, - { - EQDMA_CPM5_MM_H2C0_RD_UR_CA_ERR, - "MM H2C0 Read cmpt unsupported request Error", - EQDMA_CPM5_H2C_MM_ERR_CODE_ENABLE_MASK_ADDR, - EQDMA_CPM5_H2C_MM_STATUS_ADDR, - H2C_MM_ERR_CODE_ENABLE_RD_UR_CA_MASK, - GLBL_ERR_STAT_ERR_H2C_MM_0_MASK, - &eqdma_cpm5_mm_h2c0_err_process - }, - { - EQDMA_CPM5_MM_H2C0_RD_HDR_BYTE_ERR, - "MM H2C0 Read cmpt hdr byte cnt Error", - EQDMA_CPM5_H2C_MM_ERR_CODE_ENABLE_MASK_ADDR, - EQDMA_CPM5_H2C_MM_STATUS_ADDR, - H2C_MM_ERR_CODE_ENABLE_RD_HDR_BYTE_ERR_MASK, - GLBL_ERR_STAT_ERR_H2C_MM_0_MASK, - &eqdma_cpm5_mm_h2c0_err_process - }, - { - EQDMA_CPM5_MM_H2C0_RD_HDR_PARAM_ERR, - "MM H2C0 Read cmpt hdr param mismatch Error", - EQDMA_CPM5_H2C_MM_ERR_CODE_ENABLE_MASK_ADDR, - EQDMA_CPM5_H2C_MM_STATUS_ADDR, - H2C_MM_ERR_CODE_ENABLE_RD_HDR_PARA_MASK, - GLBL_ERR_STAT_ERR_H2C_MM_0_MASK, - &eqdma_cpm5_mm_h2c0_err_process - }, - { - EQDMA_CPM5_MM_H2C0_RD_HDR_ADR_ERR, - "MM H2C0 Read cmpt hdr address mismatch Error", - EQDMA_CPM5_H2C_MM_ERR_CODE_ENABLE_MASK_ADDR, - EQDMA_CPM5_H2C_MM_STATUS_ADDR, - H2C_MM_ERR_CODE_ENABLE_RD_HDR_ADR_ERR_MASK, - GLBL_ERR_STAT_ERR_H2C_MM_0_MASK, - &eqdma_cpm5_mm_h2c0_err_process - }, - { - EQDMA_CPM5_MM_H2C0_RD_FLR_ERR, - "MM H2C0 Read flr Error", - EQDMA_CPM5_H2C_MM_ERR_CODE_ENABLE_MASK_ADDR, - EQDMA_CPM5_H2C_MM_STATUS_ADDR, - H2C_MM_ERR_CODE_ENABLE_RD_FLR_ERR_MASK, - GLBL_ERR_STAT_ERR_H2C_MM_0_MASK, - &eqdma_cpm5_mm_h2c0_err_process - }, - { - EQDMA_CPM5_MM_H2C0_RD_DAT_POISON_ERR, - "MM H2C0 Read data poison Error", - EQDMA_CPM5_H2C_MM_ERR_CODE_ENABLE_MASK_ADDR, - EQDMA_CPM5_H2C_MM_STATUS_ADDR, - H2C_MM_ERR_CODE_ENABLE_RD_DAT_POISON_ERR_MASK, - GLBL_ERR_STAT_ERR_H2C_MM_0_MASK, - &eqdma_cpm5_mm_h2c0_err_process - }, - { - EQDMA_CPM5_MM_H2C0_RD_RQ_DIS_ERR, - "MM H2C0 Read request disable Error", - EQDMA_CPM5_H2C_MM_ERR_CODE_ENABLE_MASK_ADDR, - EQDMA_CPM5_H2C_MM_STATUS_ADDR, - H2C_MM_ERR_CODE_ENABLE_RD_RQ_DIS_ERR_MASK, - GLBL_ERR_STAT_ERR_H2C_MM_0_MASK, - &eqdma_cpm5_mm_h2c0_err_process - }, - { - EQDMA_CPM5_MM_H2C0_WR_DEC_ERR, - "MM H2C0 Write desc Error", - EQDMA_CPM5_H2C_MM_ERR_CODE_ENABLE_MASK_ADDR, - EQDMA_CPM5_H2C_MM_STATUS_ADDR, - H2C_MM_ERR_CODE_ENABLE_WR_DEC_ERR_MASK, - GLBL_ERR_STAT_ERR_H2C_MM_0_MASK, - &eqdma_cpm5_mm_h2c0_err_process - }, - { - EQDMA_CPM5_MM_H2C0_WR_SLV_ERR, - "MM H2C0 Write slv Error", - EQDMA_CPM5_H2C_MM_ERR_CODE_ENABLE_MASK_ADDR, - EQDMA_CPM5_H2C_MM_STATUS_ADDR, - H2C_MM_ERR_CODE_ENABLE_WR_SLV_ERR_MASK, - GLBL_ERR_STAT_ERR_H2C_MM_0_MASK, - &eqdma_cpm5_mm_h2c0_err_process - }, - { - EQDMA_CPM5_MM_H2C0_ERR_ALL, - "All MM H2C Errors", - EQDMA_CPM5_H2C_MM_ERR_CODE_ENABLE_MASK_ADDR, - EQDMA_CPM5_H2C_MM_STATUS_ADDR, - EQDMA_CPM5_MM_H2C0_ERR_ALL_MASK, - GLBL_ERR_STAT_ERR_H2C_MM_0_MASK, - &eqdma_cpm5_hw_desc_err_process - }, -}; - - -static int32_t -all_eqdma_cpm5_hw_errs[EQDMA_CPM5_TOTAL_LEAF_ERROR_AGGREGATORS] = { - - EQDMA_CPM5_DSC_ERR_ALL, - EQDMA_CPM5_TRQ_ERR_ALL, - EQDMA_CPM5_ST_C2H_ERR_ALL, - EQDMA_CPM5_ST_FATAL_ERR_ALL, - EQDMA_CPM5_ST_H2C_ERR_ALL, - EQDMA_CPM5_SBE_1_ERR_ALL, - EQDMA_CPM5_SBE_ERR_ALL, - EQDMA_CPM5_DBE_1_ERR_ALL, - EQDMA_CPM5_DBE_ERR_ALL, - EQDMA_CPM5_MM_C2H_ERR_ALL, - EQDMA_CPM5_MM_H2C0_ERR_ALL -}; - -static struct qctx_entry eqdma_cpm5_sw_ctxt_entries[] = { - {"PIDX", 0}, - {"IRQ Arm", 0}, - {"Function Id", 0}, - {"Queue Enable", 0}, - {"Fetch Credit Enable", 0}, - {"Write back/Intr Check", 0}, - {"Write back/Intr Interval", 0}, - {"Address Translation", 0}, - {"Fetch Max", 0}, - {"Ring Size", 0}, - {"Descriptor Size", 0}, - {"Bypass Enable", 0}, - {"MM Channel", 0}, - {"Writeback Enable", 0}, - {"Interrupt Enable", 0}, - {"Port Id", 0}, - {"Interrupt No Last", 0}, - {"Error", 0}, - {"Writeback Error Sent", 0}, - {"IRQ Request", 0}, - {"Marker Disable", 0}, - {"Is Memory Mapped", 0}, - {"Descriptor Ring Base Addr (Low)", 0}, - {"Descriptor Ring Base Addr (High)", 0}, - {"Interrupt Vector/Ring Index", 0}, - {"Interrupt Aggregation", 0}, - {"Disable Interrupt with VF", 0}, - {"Pack descriptor output interface", 0}, - {"Irq Bypass", 0}, -}; - -static struct qctx_entry eqdma_cpm5_hw_ctxt_entries[] = { - {"CIDX", 0}, - {"Credits Consumed", 0}, - {"Descriptors Pending", 0}, - {"Queue Invalid No Desc Pending", 0}, - {"Eviction Pending", 0}, - {"Fetch Pending", 0}, -}; - -static struct qctx_entry eqdma_cpm5_credit_ctxt_entries[] = { - {"Credit", 0}, -}; - -static struct qctx_entry eqdma_cpm5_cmpt_ctxt_entries[] = { - {"Enable Status Desc Update", 0}, - {"Enable Interrupt", 0}, - {"Trigger Mode", 0}, - {"Function Id", 0}, - {"Counter Index", 0}, - {"Timer Index", 0}, - {"Interrupt State", 0}, - {"Color", 0}, - {"Ring Size", 0}, - {"Base Addr High (L)[37:6]", 0}, - {"Base Addr High(H)[63:38]", 0}, - {"Descriptor Size", 0}, - {"PIDX", 0}, - {"CIDX", 0}, - {"Valid", 0}, - {"Error", 0}, - {"Trigger Pending", 0}, - {"Timer Running", 0}, - {"Full Update", 0}, - {"Over Flow Check Disable", 0}, - {"Address Translation", 0}, - {"Interrupt Vector/Ring Index", 0}, - {"Interrupt Aggregation", 0}, - {"Disable Insterrupt with VF", 0}, - {"c2h Direction", 0}, - {"Base Addr Low[5:2]", 0}, - {"Shared Completion Queue", 0}, -}; - -static struct qctx_entry eqdma_cpm5_c2h_pftch_ctxt_entries[] = { - {"Bypass", 0}, - {"Buffer Size Index", 0}, - {"Port Id", 0}, - {"Variable Descriptor", 0}, - {"Number of descriptors prefetched", 0}, - {"Error", 0}, - {"Prefetch Enable", 0}, - {"In Prefetch", 0}, - {"Software Credit", 0}, - {"Valid", 0}, -}; - -static struct qctx_entry eqdma_cpm5_ind_intr_ctxt_entries[] = { - {"valid", 0}, - {"vec", 0}, - {"int_st", 0}, - {"color", 0}, - {"baddr_4k (Low)", 0}, - {"baddr_4k (High)", 0}, - {"page_size", 0}, - {"pidx", 0}, - {"at", 0}, - {"Function Id", 0}, -}; - -static struct qctx_entry eqdma_cpm5_fmap_ctxt_entries[] = { - {"Queue Base", 0}, - {"Queue Max", 0}, -}; - -static int eqdma_cpm5_indirect_reg_invalidate(void *dev_hndl, - enum ind_ctxt_cmd_sel sel, uint16_t hw_qid); -static int eqdma_cpm5_indirect_reg_clear(void *dev_hndl, - enum ind_ctxt_cmd_sel sel, uint16_t hw_qid); -static int eqdma_cpm5_indirect_reg_read(void *dev_hndl, - enum ind_ctxt_cmd_sel sel, - uint16_t hw_qid, uint32_t cnt, uint32_t *data); -static int eqdma_cpm5_indirect_reg_write(void *dev_hndl, - enum ind_ctxt_cmd_sel sel, - uint16_t hw_qid, uint32_t *data, uint16_t cnt); - -uint32_t eqdma_cpm5_get_config_num_regs(void) -{ - return eqdma_cpm5_config_num_regs_get(); -} - -struct xreg_info *eqdma_cpm5_get_config_regs(void) -{ - return eqdma_cpm5_config_regs_get(); -} - -uint32_t eqdma_cpm5_reg_dump_buf_len(void) -{ - uint32_t length = (eqdma_cpm5_config_num_regs_get() + 1) - * REG_DUMP_SIZE_PER_LINE; - return length; -} - -int eqdma_cpm5_context_buf_len(uint8_t st, - enum qdma_dev_q_type q_type, uint32_t *buflen) -{ - int len = 0; - - if (q_type == QDMA_DEV_Q_TYPE_CMPT) { - len += (((sizeof(eqdma_cpm5_cmpt_ctxt_entries) / - sizeof(eqdma_cpm5_cmpt_ctxt_entries[0])) + 1) * - REG_DUMP_SIZE_PER_LINE); - } else { - len += (((sizeof(eqdma_cpm5_sw_ctxt_entries) / - sizeof(eqdma_cpm5_sw_ctxt_entries[0])) + 1) - * REG_DUMP_SIZE_PER_LINE); - - len += (((sizeof(eqdma_cpm5_hw_ctxt_entries) / - sizeof(eqdma_cpm5_hw_ctxt_entries[0])) + 1) * - REG_DUMP_SIZE_PER_LINE); - - len += (((sizeof(eqdma_cpm5_credit_ctxt_entries) / - sizeof(eqdma_cpm5_credit_ctxt_entries[0])) + 1) * - REG_DUMP_SIZE_PER_LINE); - - len += (((sizeof(eqdma_cpm5_fmap_ctxt_entries) / - sizeof(eqdma_cpm5_fmap_ctxt_entries[0])) + 1) * - REG_DUMP_SIZE_PER_LINE); - - if (st && (q_type == QDMA_DEV_Q_TYPE_C2H)) { - len += (((sizeof(eqdma_cpm5_cmpt_ctxt_entries) / - sizeof(eqdma_cpm5_cmpt_ctxt_entries[0])) + - 1) * - REG_DUMP_SIZE_PER_LINE); - - len += (((sizeof(eqdma_cpm5_c2h_pftch_ctxt_entries) - / - sizeof(eqdma_cpm5_c2h_pftch_ctxt_entries[0] - )) + 1) * REG_DUMP_SIZE_PER_LINE); - } - } - - *buflen = len; - return 0; -} - -static uint32_t eqdma_cpm5_intr_context_buf_len(void) -{ - uint32_t len = 0; - - len += (((sizeof(eqdma_cpm5_ind_intr_ctxt_entries) / - sizeof(eqdma_cpm5_ind_intr_ctxt_entries[0])) + 1) * - REG_DUMP_SIZE_PER_LINE); - return len; -} - -/* - * eqdma_cpm5_set_perf_opt() - Helper function to set the - * cpm5 perf optimizations. - * - */ -static void eqdma_cpm5_set_perf_opt(void *dev_hndl) -{ - uint32_t reg_val = 0; - uint32_t pftch_cache_depth = 0; - uint32_t pftch_qcnt = 0; - uint32_t pftch_evnt_qcnt_th = 0; - uint32_t crdt_coal_fifo_th = 0; - uint32_t crdt_coal_crdt_th = 0; - - /* C2H interrupt timer tick */ - qdma_reg_write(dev_hndl, EQDMA_CPM5_C2H_INT_TIMER_TICK_ADDR, - EQDMA_CPM5_DEFAULT_C2H_INTR_TIMER_TICK); - -/* - * #define EQDMA_CPM5_C2H_PFCH_CACHE_DEPTH_ADDR 0xBE0 - * #define C2H_PFCH_CACHE_DEPTH_MAX_STBUF_MASK GENMASK(23, 16) - * #define C2H_PFCH_CACHE_DEPTH_MASK GENMASK(7, 0) - */ - reg_val = qdma_reg_read(dev_hndl, EQDMA_CPM5_C2H_PFCH_CACHE_DEPTH_ADDR); - pftch_cache_depth = FIELD_GET(C2H_PFCH_CACHE_DEPTH_MASK, reg_val); - -/* - * #define EQDMA_CPM5_GLBL_DSC_CFG_ADDR 0x250 - * #define GLBL_DSC_CFG_RSVD_1_MASK GENMASK(31, 10) - * #define GLBL_DSC_CFG_UNC_OVR_COR_MASK BIT(9) - * #define GLBL_DSC_CFG_CTXT_FER_DIS_MASK BIT(8) - * #define GLBL_DSC_CFG_RSVD_2_MASK GENMASK(7, 6) - * #define GLBL_DSC_CFG_MAXFETCH_MASK GENMASK(5, 3) - * #define GLBL_DSC_CFG_WB_ACC_INT_MASK GENMASK(2, 0) - */ -#define GLBL_DSC_CFG_RSVD_1_DFLT 0 -#define GLBL_DSC_CFG_UNC_OVR_COR_DFLT 0 -#define GLBL_DSC_CFG_CTXT_FER_DIS_DFLT 0 -#define GLBL_DSC_CFG_RSVD_2_DFLT 0 -/* =IF(Internal mode, 2,5) */ -#define GLBL_DSC_CFG_MAXFETCH 2 -#define GLBL_DSC_CFG_WB_ACC_INT 5 - reg_val = - FIELD_SET(GLBL_DSC_CFG_RSVD_1_MASK, GLBL_DSC_CFG_RSVD_1_DFLT) | - FIELD_SET(GLBL_DSC_CFG_UNC_OVR_COR_MASK, - GLBL_DSC_CFG_UNC_OVR_COR_DFLT) | - FIELD_SET(GLBL_DSC_CFG_CTXT_FER_DIS_MASK, - GLBL_DSC_CFG_CTXT_FER_DIS_DFLT) | - FIELD_SET(GLBL_DSC_CFG_RSVD_2_MASK, GLBL_DSC_CFG_RSVD_2_DFLT) | - FIELD_SET(GLBL_DSC_CFG_MAXFETCH_MASK, - GLBL_DSC_CFG_MAXFETCH) | - FIELD_SET(GLBL_DSC_CFG_WB_ACC_INT_MASK, - GLBL_DSC_CFG_WB_ACC_INT); - qdma_reg_write(dev_hndl, EQDMA_CPM5_GLBL_DSC_CFG_ADDR, reg_val); - reg_val = qdma_reg_read(dev_hndl, EQDMA_CPM5_GLBL_DSC_CFG_ADDR); - qdma_log_info("%s: reg = 0x%08X val = 0x%08X\n", - __func__, EQDMA_CPM5_GLBL_DSC_CFG_ADDR, reg_val); - -/* - * #define EQDMA_CPM5_CFG_BLK_MISC_CTL_ADDR 0x4C - * #define CFG_BLK_MISC_CTL_RSVD_1_MASK GENMASK(31, 24) - * #define CFG_BLK_MISC_CTL_10B_TAG_EN_MASK BIT(23) - * #define CFG_BLK_MISC_CTL_RSVD_2_MASK BIT(22) - * #define CFG_BLK_MISC_CTL_AXI_WBK_MASK BIT(21) - * #define CFG_BLK_MISC_CTL_AXI_DSC_MASK BIT(20) - * #define CFG_BLK_MISC_CTL_NUM_TAG_MASK GENMASK(19, 8) - * #define CFG_BLK_MISC_CTL_RSVD_3_MASK GENMASK(7, 5) - * #define CFG_BLK_MISC_CTL_RQ_METERING_MULTIPLIER_MASK GENMASK(4, 0) - */ -#define CFG_BLK_MISC_CTL_RSVD_1_DFLT 0 -#define CFG_BLK_MISC_CTL_RSVD_2_DFLT 0 -#define CFG_BLK_MISC_CTL_AXI_WBK_DFLT 0 -#define CFG_BLK_MISC_CTL_AXI_DSC_DFLT 0 -/* IF(10bit tag enabled, 512,256) */ -#ifdef EQDMA_CPM5_10BIT_TAG_ENABLE -#define CFG_BLK_MISC_CTL_10B_TAG_DFLT 1 -#define CFG_BLK_MISC_CTL_NUM_TAG_DFLT 512 -#else -#define CFG_BLK_MISC_CTL_10B_TAG_DFLT 0 -#define CFG_BLK_MISC_CTL_NUM_TAG_DFLT 256 -#endif -#define CFG_BLK_MISC_CTL_RSVD_3_DFLT 0 -#define EQDMA_CFG_BLK_MISC_CTL_RQ_METERING_MUL 31 - reg_val = - FIELD_SET(CFG_BLK_MISC_CTL_RSVD_1_MASK, - CFG_BLK_MISC_CTL_RSVD_1_DFLT) | - FIELD_SET(CFG_BLK_MISC_CTL_10B_TAG_EN_MASK, - CFG_BLK_MISC_CTL_10B_TAG_DFLT) | - FIELD_SET(CFG_BLK_MISC_CTL_RSVD_2_MASK, - CFG_BLK_MISC_CTL_RSVD_2_DFLT) | - FIELD_SET(CFG_BLK_MISC_CTL_AXI_WBK_MASK, - CFG_BLK_MISC_CTL_AXI_WBK_DFLT) | - FIELD_SET(CFG_BLK_MISC_CTL_AXI_DSC_MASK, - CFG_BLK_MISC_CTL_AXI_DSC_DFLT) | - FIELD_SET(CFG_BLK_MISC_CTL_NUM_TAG_MASK, - CFG_BLK_MISC_CTL_NUM_TAG_DFLT) | - FIELD_SET(CFG_BLK_MISC_CTL_RSVD_3_MASK, - CFG_BLK_MISC_CTL_RSVD_3_DFLT) | - FIELD_SET(CFG_BLK_MISC_CTL_RQ_METERING_MULTIPLIER_MASK, - EQDMA_CFG_BLK_MISC_CTL_RQ_METERING_MUL); - qdma_reg_write(dev_hndl, EQDMA_CPM5_CFG_BLK_MISC_CTL_ADDR, reg_val); - reg_val = qdma_reg_read(dev_hndl, EQDMA_CPM5_CFG_BLK_MISC_CTL_ADDR); - qdma_log_info("%s: reg = 0x%08X val = 0x%08X\n", - __func__, EQDMA_CPM5_CFG_BLK_MISC_CTL_ADDR, reg_val); - -/* - * #define EQDMA_CPM5_C2H_PFCH_CFG_ADDR 0xB08 - * #define C2H_PFCH_CFG_EVTFL_TH_MASK GENMASK(31, 16) - * #define C2H_PFCH_CFG_FL_TH_MASK GENMASK(15, 0) - */ -#define EQDMA_PFTCH_CFG_EVT_PFTH_FL_TH 256 -#define C2H_PFCH_CFG_FL_TH_DFLT 256 - reg_val = - FIELD_SET(C2H_PFCH_CFG_EVTFL_TH_MASK, - EQDMA_PFTCH_CFG_EVT_PFTH_FL_TH) | - FIELD_SET(C2H_PFCH_CFG_FL_TH_MASK, - C2H_PFCH_CFG_FL_TH_DFLT); - - qdma_reg_write(dev_hndl, EQDMA_CPM5_C2H_PFCH_CFG_ADDR, reg_val); - reg_val = qdma_reg_read(dev_hndl, EQDMA_CPM5_C2H_PFCH_CFG_ADDR); - qdma_log_info("%s: reg = 0x%08X val = 0x%08X\n", - __func__, EQDMA_CPM5_C2H_PFCH_CFG_ADDR, reg_val); - -/* - * #define EQDMA_CPM5_C2H_PFCH_CFG_1_ADDR 0xA80 - * #define C2H_PFCH_CFG_1_EVT_QCNT_TH_MASK GENMASK(31, 16) - * #define C2H_PFCH_CFG_1_QCNT_MASK GENMASK(15, 0) - */ - pftch_qcnt = pftch_cache_depth - PREFETCH_QUEUE_COUNT_STEP; - pftch_evnt_qcnt_th = pftch_qcnt - PREFETCH_QUEUE_COUNT_STEP; - reg_val = - FIELD_SET(C2H_PFCH_CFG_1_EVT_QCNT_TH_MASK, pftch_evnt_qcnt_th) | - FIELD_SET(C2H_PFCH_CFG_1_QCNT_MASK, pftch_qcnt); - qdma_reg_write(dev_hndl, EQDMA_CPM5_C2H_PFCH_CFG_1_ADDR, reg_val); - reg_val = qdma_reg_read(dev_hndl, EQDMA_CPM5_C2H_PFCH_CFG_1_ADDR); - qdma_log_info("%s: reg = 0x%08X val = 0x%08X\n", - __func__, EQDMA_CPM5_C2H_PFCH_CFG_1_ADDR, reg_val); - -/* - * #define EQDMA_CPM5_C2H_PFCH_CFG_2_ADDR 0xA84 - * #define C2H_PFCH_CFG_2_FENCE_MASK BIT(31) - * #define C2H_PFCH_CFG_2_RSVD_MASK GENMASK(30, 29) - * #define C2H_PFCH_CFG_2_VAR_DESC_NO_DROP_MASK BIT(28) - * #define C2H_PFCH_CFG_2_LL_SZ_TH_MASK GENMASK(27, 12) - * #define C2H_PFCH_CFG_2_VAR_DESC_NUM_MASK GENMASK(11, 6) - * #define C2H_PFCH_CFG_2_NUM_MASK GENMASK(5, 0) - */ -#define C2H_PFCH_CFG_2_FENCE_EN 1 -#define C2H_PFCH_CFG_2_RSVD_DFLT 0 -#define C2H_PFCH_CFG_2_VAR_DESC_NO_DROP_DFLT 0 -#define C2H_PFCH_CFG_2_LL_SZ_TH_DFLT 1024 -#define C2H_PFCH_CFG_2_VAR_DESC_NUM 15 -#define C2H_PFCH_CFG_2_NUM_PFCH_DFLT 16 - reg_val = - FIELD_SET(C2H_PFCH_CFG_2_FENCE_MASK, - C2H_PFCH_CFG_2_FENCE_EN) | - FIELD_SET(C2H_PFCH_CFG_2_RSVD_MASK, - C2H_PFCH_CFG_2_RSVD_DFLT) | - FIELD_SET(C2H_PFCH_CFG_2_VAR_DESC_NO_DROP_MASK, - C2H_PFCH_CFG_2_VAR_DESC_NO_DROP_DFLT) | - FIELD_SET(C2H_PFCH_CFG_2_LL_SZ_TH_MASK, - C2H_PFCH_CFG_2_LL_SZ_TH_DFLT) | - FIELD_SET(C2H_PFCH_CFG_2_VAR_DESC_NUM_MASK, - C2H_PFCH_CFG_2_VAR_DESC_NUM) | - FIELD_SET(C2H_PFCH_CFG_2_NUM_MASK, - C2H_PFCH_CFG_2_NUM_PFCH_DFLT); - qdma_reg_write(dev_hndl, EQDMA_CPM5_C2H_PFCH_CFG_2_ADDR, reg_val); - reg_val = qdma_reg_read(dev_hndl, EQDMA_CPM5_C2H_PFCH_CFG_2_ADDR); - qdma_log_info("%s: reg = 0x%08X val = 0x%08X\n", - __func__, EQDMA_CPM5_C2H_PFCH_CFG_2_ADDR, reg_val); - -/* Registers Not Applicable for CPM5 - * #define EQDMA_PFCH_CFG_3_ADDR 0x147C - * #define EQDMA_PFCH_CFG_4_ADDR 0x1484 - */ - -/* - * #define EQDMA_CPM5_C2H_CRDT_COAL_CFG_1_ADDR 0x1400 - * #define C2H_CRDT_COAL_CFG_1_RSVD_1_MASK GENMASK(31, 18) - * #define C2H_CRDT_COAL_CFG_1_PLD_FIFO_TH_MASK GENMASK(17, 10) - * #define C2H_CRDT_COAL_CFG_1_TIMER_TH_MASK GENMASK(9, 0)4 - */ -#define C2H_CRDT_COAL_CFG_1_RSVD_1_DFLT 0 -#define C2H_CRDT_COAL_CFG_1_PLD_FIFO_TH_DFLT 16 -#define C2H_CRDT_COAL_CFG_1_TIMER_TH 16 - reg_val = - FIELD_SET(C2H_CRDT_COAL_CFG_1_RSVD_1_MASK, - C2H_CRDT_COAL_CFG_1_RSVD_1_DFLT) | - FIELD_SET(C2H_CRDT_COAL_CFG_1_PLD_FIFO_TH_MASK, - C2H_CRDT_COAL_CFG_1_PLD_FIFO_TH_DFLT) | - FIELD_SET(C2H_CRDT_COAL_CFG_1_TIMER_TH_MASK, - C2H_CRDT_COAL_CFG_1_TIMER_TH); - qdma_reg_write(dev_hndl, EQDMA_CPM5_C2H_CRDT_COAL_CFG_1_ADDR, reg_val); - reg_val = qdma_reg_read(dev_hndl, EQDMA_CPM5_C2H_CRDT_COAL_CFG_1_ADDR); - qdma_log_info("%s: reg = 0x%08X val = 0x%08X\n", - __func__, EQDMA_CPM5_C2H_CRDT_COAL_CFG_1_ADDR, reg_val); - -/* - * #define EQDMA_CPM5_C2H_CRDT_COAL_CFG_2_ADDR 0x1404 - * #define C2H_CRDT_COAL_CFG_2_RSVD_1_MASK GENMASK(31, 24) - * #define C2H_CRDT_COAL_CFG_2_FIFO_TH_MASK GENMASK(23, 16) - * #define C2H_CRDT_COAL_CFG_2_RESERVED1_MASK GENMASK(15, 11) - * #define C2H_CRDT_COAL_CFG_2_NT_TH_MASK GENMASK(10, 0) - */ -#define C2H_CRDT_COAL_CFG_2_RSVD_1_DFLT 0 -#define C2H_CRDT_COAL_CFG_2_RESERVED1_DFLT 0 -#define C2H_CRDT_COAL_CFG_2_CRDT_CNT_TH_DFLT 156 - crdt_coal_fifo_th = pftch_cache_depth - 8; - crdt_coal_crdt_th = C2H_CRDT_COAL_CFG_2_CRDT_CNT_TH_DFLT; - reg_val = - FIELD_SET(C2H_CRDT_COAL_CFG_2_RSVD_1_MASK, - C2H_CRDT_COAL_CFG_2_RSVD_1_DFLT) | - FIELD_SET(C2H_CRDT_COAL_CFG_2_FIFO_TH_MASK, - crdt_coal_fifo_th) | - FIELD_SET(C2H_CRDT_COAL_CFG_2_RESERVED1_MASK, - C2H_CRDT_COAL_CFG_2_RESERVED1_DFLT) | - FIELD_SET(C2H_CRDT_COAL_CFG_2_NT_TH_MASK, - crdt_coal_crdt_th); - qdma_reg_write(dev_hndl, EQDMA_CPM5_C2H_CRDT_COAL_CFG_2_ADDR, reg_val); - reg_val = qdma_reg_read(dev_hndl, EQDMA_CPM5_C2H_CRDT_COAL_CFG_2_ADDR); - qdma_log_info("%s: reg = 0x%08X val = 0x%08X\n", - __func__, EQDMA_CPM5_C2H_CRDT_COAL_CFG_2_ADDR, reg_val); - -/* - * #define EQDMA_CPM5_H2C_REQ_THROT_PCIE_ADDR 0xE24 - * #define H2C_REQ_THROT_PCIE_EN_REQ_MASK BIT(31) - * #define H2C_REQ_THROT_PCIE_MASK GENMASK(30, 19) - * #define H2C_REQ_THROT_PCIE_EN_DATA_MASK BIT(18) - * #define H2C_REQ_THROT_PCIE_DATA_THRESH_MASK GENMASK(17, 0) - */ -#define H2C_REQ_THROT_PCIE_EN_REQ 1 -/* IF(10bit tag enabled, 512-64, 192) */ -#ifdef EQDMA_CPM5_10BIT_TAG_ENABLE -#define H2C_REQ_THROT_PCIE_REQ_TH 448 -#else -#define H2C_REQ_THROT_PCIE_REQ_TH 192 -#endif -#define H2C_REQ_THROT_PCIE_EN_DATA 1 -#define H2C_REQ_THROT_PCIE_DATA_TH 57344 - reg_val = - FIELD_SET(H2C_REQ_THROT_PCIE_EN_REQ_MASK, - H2C_REQ_THROT_PCIE_EN_REQ) | - FIELD_SET(H2C_REQ_THROT_PCIE_MASK, - H2C_REQ_THROT_PCIE_REQ_TH) | - FIELD_SET(H2C_REQ_THROT_PCIE_EN_DATA_MASK, - H2C_REQ_THROT_PCIE_EN_DATA) | - FIELD_SET(H2C_REQ_THROT_PCIE_DATA_THRESH_MASK, - H2C_REQ_THROT_PCIE_DATA_TH); - qdma_reg_write(dev_hndl, EQDMA_CPM5_H2C_REQ_THROT_PCIE_ADDR, reg_val); - reg_val = qdma_reg_read(dev_hndl, EQDMA_CPM5_H2C_REQ_THROT_PCIE_ADDR); - qdma_log_info("%s: reg = 0x%08X val = 0x%08X\n", - __func__, EQDMA_CPM5_H2C_REQ_THROT_PCIE_ADDR, reg_val); - -/* - * #define EQDMA_CPM5_H2C_REQ_THROT_AXIMM_ADDR 0xE2C - * #define H2C_REQ_THROT_AXIMM_EN_REQ_MASK BIT(31) - * #define H2C_REQ_THROT_AXIMM_MASK GENMASK(30, 19) - * #define H2C_REQ_THROT_AXIMM_EN_DATA_MASK BIT(18) - * #define H2C_REQ_THROT_AXIMM_DATA_THRESH_MASK GENMASK(17, 0) - */ -#define H2C_REQ_THROT_AXIMM_EN_REQ 0 -/* IF(10bit tag en=1, 512-64, 192) */ -#ifdef EQDMA_CPM5_10BIT_TAG_ENABLE -#define H2C_REQ_THROT_AXIMM_REQ_TH 448 -#else -#define H2C_REQ_THROT_AXIMM_REQ_TH 192 -#endif -#define H2C_REQ_THROT_AXIMM_EN_DATA 0 -#define H2C_REQ_THROT_AXIMM_DATA_TH 65536 - reg_val = - FIELD_SET(H2C_REQ_THROT_AXIMM_EN_REQ_MASK, - H2C_REQ_THROT_AXIMM_EN_REQ) | - FIELD_SET(H2C_REQ_THROT_AXIMM_MASK, - H2C_REQ_THROT_AXIMM_REQ_TH) | - FIELD_SET(H2C_REQ_THROT_AXIMM_EN_DATA_MASK, - H2C_REQ_THROT_AXIMM_EN_DATA) | - FIELD_SET(H2C_REQ_THROT_AXIMM_DATA_THRESH_MASK, - H2C_REQ_THROT_AXIMM_DATA_TH); - qdma_reg_write(dev_hndl, EQDMA_CPM5_H2C_REQ_THROT_AXIMM_ADDR, reg_val); - reg_val = qdma_reg_read(dev_hndl, EQDMA_CPM5_H2C_REQ_THROT_AXIMM_ADDR); - qdma_log_info("%s: reg = 0x%08X val = 0x%08X\n", - __func__, EQDMA_CPM5_H2C_REQ_THROT_AXIMM_ADDR, reg_val); - -#define EQDMA_CPM5_H2C_MM_DATA_THROTTLE_ADDR 0x12EC -#define H2C_MM_DATA_THROTTLE_RSVD_1_MASK GENMASK(31, 17) -#define H2C_MM_DATA_THROTTLE_DAT_EN_MASK BIT(16) -#define H2C_MM_DATA_THROTTLE_DAT_MASK GENMASK(15, 0) -#define H2C_MM_DATA_THROTTLE_RSVD_1_DFLT 0 -#define H2C_MM_DATA_TH_EN 1 -#define H2C_MM_DATA_TH 57344 - reg_val = - FIELD_SET(H2C_MM_DATA_THROTTLE_RSVD_1_MASK, - H2C_MM_DATA_THROTTLE_RSVD_1_DFLT) | - FIELD_SET(H2C_MM_DATA_THROTTLE_DAT_EN_MASK, H2C_MM_DATA_TH_EN) | - FIELD_SET(H2C_MM_DATA_THROTTLE_DAT_MASK, H2C_MM_DATA_TH); - qdma_reg_write(dev_hndl, EQDMA_CPM5_H2C_MM_DATA_THROTTLE_ADDR, reg_val); - reg_val = qdma_reg_read(dev_hndl, EQDMA_CPM5_H2C_MM_DATA_THROTTLE_ADDR); - qdma_log_info("%s: reg = 0x%08X val = 0x%08X\n", - __func__, EQDMA_CPM5_H2C_MM_DATA_THROTTLE_ADDR, reg_val); -} - -/* - * eqdma_cpm5_indirect_reg_invalidate() - helper function to invalidate - * indirect context registers. - * - * return -QDMA_ERR_HWACC_BUSY_TIMEOUT if register - * value didn't match, QDMA_SUCCESS other wise - */ -static int eqdma_cpm5_indirect_reg_invalidate(void *dev_hndl, - enum ind_ctxt_cmd_sel sel, uint16_t hw_qid) -{ - union qdma_ind_ctxt_cmd cmd; - - qdma_reg_access_lock(dev_hndl); - - /* set command register */ - cmd.word = 0; - cmd.bits.qid = hw_qid; - cmd.bits.op = QDMA_CTXT_CMD_INV; - cmd.bits.sel = sel; - qdma_reg_write(dev_hndl, EQDMA_CPM5_IND_CTXT_CMD_ADDR, cmd.word); - - /* check if the operation went through well */ - if (hw_monitor_reg(dev_hndl, EQDMA_CPM5_IND_CTXT_CMD_ADDR, - IND_CTXT_CMD_BUSY_MASK, 0, - QDMA_REG_POLL_DFLT_INTERVAL_US, - QDMA_REG_POLL_DFLT_TIMEOUT_US)) { - qdma_reg_access_release(dev_hndl); - qdma_log_error("%s: hw_monitor_reg failed with err:%d\n", - __func__, - -QDMA_ERR_HWACC_BUSY_TIMEOUT); - return -QDMA_ERR_HWACC_BUSY_TIMEOUT; - } - - qdma_reg_access_release(dev_hndl); - - return QDMA_SUCCESS; -} - -/* - * eqdma_cpm5_indirect_reg_clear() - helper function to clear indirect - * context registers. - * - * return -QDMA_ERR_HWACC_BUSY_TIMEOUT if register - * value didn't match, QDMA_SUCCESS other wise - */ -static int eqdma_cpm5_indirect_reg_clear(void *dev_hndl, - enum ind_ctxt_cmd_sel sel, uint16_t hw_qid) -{ - union qdma_ind_ctxt_cmd cmd; - - qdma_reg_access_lock(dev_hndl); - - /* set command register */ - cmd.word = 0; - cmd.bits.qid = hw_qid; - cmd.bits.op = QDMA_CTXT_CMD_CLR; - cmd.bits.sel = sel; - qdma_reg_write(dev_hndl, EQDMA_CPM5_IND_CTXT_CMD_ADDR, cmd.word); - - /* check if the operation went through well */ - if (hw_monitor_reg(dev_hndl, EQDMA_CPM5_IND_CTXT_CMD_ADDR, - IND_CTXT_CMD_BUSY_MASK, 0, - QDMA_REG_POLL_DFLT_INTERVAL_US, - QDMA_REG_POLL_DFLT_TIMEOUT_US)) { - qdma_reg_access_release(dev_hndl); - qdma_log_error("%s: hw_monitor_reg failed with err:%d\n", - __func__, - -QDMA_ERR_HWACC_BUSY_TIMEOUT); - return -QDMA_ERR_HWACC_BUSY_TIMEOUT; - } - - qdma_reg_access_release(dev_hndl); - - return QDMA_SUCCESS; -} - -/* - * eqdma_cpm5_indirect_reg_read() - helper function to read indirect - * context registers. - * - * return -QDMA_ERR_HWACC_BUSY_TIMEOUT if register - * value didn't match, QDMA_SUCCESS other wise - */ -static int eqdma_cpm5_indirect_reg_read(void *dev_hndl, - enum ind_ctxt_cmd_sel sel, - uint16_t hw_qid, uint32_t cnt, uint32_t *data) -{ - uint32_t index = 0, reg_addr = EQDMA_CPM5_IND_CTXT_DATA_ADDR; - union qdma_ind_ctxt_cmd cmd; - - qdma_reg_access_lock(dev_hndl); - - /* set command register */ - cmd.word = 0; - cmd.bits.qid = hw_qid; - cmd.bits.op = QDMA_CTXT_CMD_RD; - cmd.bits.sel = sel; - - qdma_reg_write(dev_hndl, EQDMA_CPM5_IND_CTXT_CMD_ADDR, cmd.word); - - /* check if the operation went through well */ - if (hw_monitor_reg(dev_hndl, EQDMA_CPM5_IND_CTXT_CMD_ADDR, - IND_CTXT_CMD_BUSY_MASK, 0, - QDMA_REG_POLL_DFLT_INTERVAL_US, - QDMA_REG_POLL_DFLT_TIMEOUT_US)) { - qdma_reg_access_release(dev_hndl); - qdma_log_error("%s: hw_monitor_reg failed with err:%d\n", - __func__, - -QDMA_ERR_HWACC_BUSY_TIMEOUT); - return -QDMA_ERR_HWACC_BUSY_TIMEOUT; - } - - for (index = 0; index < cnt; index++, reg_addr += sizeof(uint32_t)) - data[index] = qdma_reg_read(dev_hndl, reg_addr); - - qdma_reg_access_release(dev_hndl); - - return QDMA_SUCCESS; -} - -/* - * eqdma_cpm5_indirect_reg_write() - helper function to write indirect - * context registers. - * - * return -QDMA_ERR_HWACC_BUSY_TIMEOUT if register - * value didn't match, QDMA_SUCCESS other wise - */ -static int eqdma_cpm5_indirect_reg_write(void *dev_hndl, - enum ind_ctxt_cmd_sel sel, - uint16_t hw_qid, uint32_t *data, uint16_t cnt) -{ - uint32_t index, reg_addr; - struct qdma_indirect_ctxt_regs regs; - uint32_t *wr_data = (uint32_t *)®s; - - qdma_reg_access_lock(dev_hndl); - - /* write the context data */ - for (index = 0; index < QDMA_IND_CTXT_DATA_NUM_REGS; index++) { - if (index < cnt) - regs.qdma_ind_ctxt_data[index] = data[index]; - else - regs.qdma_ind_ctxt_data[index] = 0; - regs.qdma_ind_ctxt_mask[index] = 0xFFFFFFFF; - } - - regs.cmd.word = 0; - regs.cmd.bits.qid = hw_qid; - regs.cmd.bits.op = QDMA_CTXT_CMD_WR; - regs.cmd.bits.sel = sel; - reg_addr = EQDMA_CPM5_IND_CTXT_DATA_ADDR; - - for (index = 0; index < ((2 * QDMA_IND_CTXT_DATA_NUM_REGS) + 1); - index++, reg_addr += sizeof(uint32_t)) - qdma_reg_write(dev_hndl, reg_addr, wr_data[index]); - - /* check if the operation went through well */ - if (hw_monitor_reg(dev_hndl, EQDMA_CPM5_IND_CTXT_CMD_ADDR, - IND_CTXT_CMD_BUSY_MASK, 0, - QDMA_REG_POLL_DFLT_INTERVAL_US, - QDMA_REG_POLL_DFLT_TIMEOUT_US)) { - qdma_reg_access_release(dev_hndl); - qdma_log_error("%s: hw_monitor_reg failed with err:%d\n", - __func__, - -QDMA_ERR_HWACC_BUSY_TIMEOUT); - return -QDMA_ERR_HWACC_BUSY_TIMEOUT; - } - - qdma_reg_access_release(dev_hndl); - - return QDMA_SUCCESS; -} - -/* - * eqdma_cpm5_fill_sw_ctxt() - Helper function to fill sw context into - * structure - * - */ -static void eqdma_cpm5_fill_sw_ctxt(struct qdma_descq_sw_ctxt *sw_ctxt) -{ - int i = 0; - - eqdma_cpm5_sw_ctxt_entries[i++].value = sw_ctxt->pidx; - eqdma_cpm5_sw_ctxt_entries[i++].value = sw_ctxt->irq_arm; - eqdma_cpm5_sw_ctxt_entries[i++].value = sw_ctxt->fnc_id; - eqdma_cpm5_sw_ctxt_entries[i++].value = sw_ctxt->qen; - eqdma_cpm5_sw_ctxt_entries[i++].value = sw_ctxt->frcd_en; - eqdma_cpm5_sw_ctxt_entries[i++].value = sw_ctxt->wbi_chk; - eqdma_cpm5_sw_ctxt_entries[i++].value = sw_ctxt->wbi_intvl_en; - eqdma_cpm5_sw_ctxt_entries[i++].value = sw_ctxt->at; - eqdma_cpm5_sw_ctxt_entries[i++].value = sw_ctxt->fetch_max; - eqdma_cpm5_sw_ctxt_entries[i++].value = sw_ctxt->rngsz_idx; - eqdma_cpm5_sw_ctxt_entries[i++].value = sw_ctxt->desc_sz; - eqdma_cpm5_sw_ctxt_entries[i++].value = sw_ctxt->bypass; - eqdma_cpm5_sw_ctxt_entries[i++].value = sw_ctxt->mm_chn; - eqdma_cpm5_sw_ctxt_entries[i++].value = sw_ctxt->wbk_en; - eqdma_cpm5_sw_ctxt_entries[i++].value = sw_ctxt->irq_en; - eqdma_cpm5_sw_ctxt_entries[i++].value = sw_ctxt->port_id; - eqdma_cpm5_sw_ctxt_entries[i++].value = sw_ctxt->irq_no_last; - eqdma_cpm5_sw_ctxt_entries[i++].value = sw_ctxt->err; - eqdma_cpm5_sw_ctxt_entries[i++].value = sw_ctxt->err_wb_sent; - eqdma_cpm5_sw_ctxt_entries[i++].value = sw_ctxt->irq_req; - eqdma_cpm5_sw_ctxt_entries[i++].value = sw_ctxt->mrkr_dis; - eqdma_cpm5_sw_ctxt_entries[i++].value = sw_ctxt->is_mm; - eqdma_cpm5_sw_ctxt_entries[i++].value = - sw_ctxt->ring_bs_addr & 0xFFFFFFFF; - eqdma_cpm5_sw_ctxt_entries[i++].value = - (sw_ctxt->ring_bs_addr >> 32) & 0xFFFFFFFF; - eqdma_cpm5_sw_ctxt_entries[i++].value = sw_ctxt->vec; - eqdma_cpm5_sw_ctxt_entries[i++].value = sw_ctxt->intr_aggr; - eqdma_cpm5_sw_ctxt_entries[i++].value = sw_ctxt->dis_intr_on_vf; - eqdma_cpm5_sw_ctxt_entries[i++].value = sw_ctxt->pack_byp_out; - eqdma_cpm5_sw_ctxt_entries[i++].value = sw_ctxt->irq_byp; - -} - -/* - * eqdma_cpm5_fill_cmpt_ctxt() - Helper function to fill completion context - * into structure - * - */ -static void eqdma_cpm5_fill_cmpt_ctxt(struct qdma_descq_cmpt_ctxt - *cmpt_ctxt) -{ - int i = 0; - - eqdma_cpm5_cmpt_ctxt_entries[i++].value = cmpt_ctxt->en_stat_desc; - eqdma_cpm5_cmpt_ctxt_entries[i++].value = cmpt_ctxt->en_int; - eqdma_cpm5_cmpt_ctxt_entries[i++].value = cmpt_ctxt->trig_mode; - eqdma_cpm5_cmpt_ctxt_entries[i++].value = cmpt_ctxt->fnc_id; - eqdma_cpm5_cmpt_ctxt_entries[i++].value = cmpt_ctxt->counter_idx; - eqdma_cpm5_cmpt_ctxt_entries[i++].value = cmpt_ctxt->timer_idx; - eqdma_cpm5_cmpt_ctxt_entries[i++].value = cmpt_ctxt->in_st; - eqdma_cpm5_cmpt_ctxt_entries[i++].value = cmpt_ctxt->color; - eqdma_cpm5_cmpt_ctxt_entries[i++].value = cmpt_ctxt->ringsz_idx; - eqdma_cpm5_cmpt_ctxt_entries[i++].value = (uint32_t)FIELD_GET( - EQDMA_CPM5_COMPL_CTXT_BADDR_HIGH_L_MASK, - cmpt_ctxt->bs_addr); - eqdma_cpm5_cmpt_ctxt_entries[i++].value = (uint32_t)FIELD_GET( - EQDMA_CPM5_COMPL_CTXT_BADDR_HIGH_H_MASK, - cmpt_ctxt->bs_addr); - eqdma_cpm5_cmpt_ctxt_entries[i++].value = cmpt_ctxt->desc_sz; - eqdma_cpm5_cmpt_ctxt_entries[i++].value = cmpt_ctxt->pidx; - eqdma_cpm5_cmpt_ctxt_entries[i++].value = cmpt_ctxt->cidx; - eqdma_cpm5_cmpt_ctxt_entries[i++].value = cmpt_ctxt->valid; - eqdma_cpm5_cmpt_ctxt_entries[i++].value = cmpt_ctxt->err; - eqdma_cpm5_cmpt_ctxt_entries[i++].value = cmpt_ctxt->user_trig_pend; - eqdma_cpm5_cmpt_ctxt_entries[i++].value = cmpt_ctxt->timer_running; - eqdma_cpm5_cmpt_ctxt_entries[i++].value = cmpt_ctxt->full_upd; - eqdma_cpm5_cmpt_ctxt_entries[i++].value = cmpt_ctxt->ovf_chk_dis; - eqdma_cpm5_cmpt_ctxt_entries[i++].value = cmpt_ctxt->at; - eqdma_cpm5_cmpt_ctxt_entries[i++].value = cmpt_ctxt->vec; - eqdma_cpm5_cmpt_ctxt_entries[i++].value = cmpt_ctxt->int_aggr; - eqdma_cpm5_cmpt_ctxt_entries[i++].value = cmpt_ctxt->dis_intr_on_vf; - eqdma_cpm5_cmpt_ctxt_entries[i++].value = cmpt_ctxt->dir_c2h; - eqdma_cpm5_cmpt_ctxt_entries[i++].value = (uint32_t)FIELD_GET( - EQDMA_CPM5_COMPL_CTXT_BADDR_LOW_MASK, - cmpt_ctxt->bs_addr); - eqdma_cpm5_cmpt_ctxt_entries[i++].value = cmpt_ctxt->sh_cmpt; -} - -/* - * eqdma_cpm5_fill_hw_ctxt() - Helper function to fill HW context into - * structure - * - */ -static void eqdma_cpm5_fill_hw_ctxt(struct qdma_descq_hw_ctxt *hw_ctxt) -{ - int i = 0; - - eqdma_cpm5_hw_ctxt_entries[i++].value = hw_ctxt->cidx; - eqdma_cpm5_hw_ctxt_entries[i++].value = hw_ctxt->crd_use; - eqdma_cpm5_hw_ctxt_entries[i++].value = hw_ctxt->dsc_pend; - eqdma_cpm5_hw_ctxt_entries[i++].value = hw_ctxt->idl_stp_b; - eqdma_cpm5_hw_ctxt_entries[i++].value = hw_ctxt->evt_pnd; - eqdma_cpm5_hw_ctxt_entries[i++].value = hw_ctxt->fetch_pnd; -} - -/* - * eqdma_cpm5_fill_credit_ctxt() - Helper function to fill Credit context - * into structure - * - */ -static void eqdma_cpm5_fill_credit_ctxt(struct qdma_descq_credit_ctxt - *cr_ctxt) -{ - eqdma_cpm5_credit_ctxt_entries[0].value = cr_ctxt->credit; -} - -/* - * eqdma_cpm5_fill_pfetch_ctxt() - Helper function to fill Prefetch context - * into structure - * - */ -static void eqdma_cpm5_fill_pfetch_ctxt(struct qdma_descq_prefetch_ctxt - *pfetch_ctxt) -{ - int i = 0; - - eqdma_cpm5_c2h_pftch_ctxt_entries[i++].value = pfetch_ctxt->bypass; - eqdma_cpm5_c2h_pftch_ctxt_entries[i++].value = - pfetch_ctxt->bufsz_idx; - eqdma_cpm5_c2h_pftch_ctxt_entries[i++].value = pfetch_ctxt->port_id; - eqdma_cpm5_c2h_pftch_ctxt_entries[i++].value = - pfetch_ctxt->var_desc; - eqdma_cpm5_c2h_pftch_ctxt_entries[i++].value = - pfetch_ctxt->num_pftch; - eqdma_cpm5_c2h_pftch_ctxt_entries[i++].value = pfetch_ctxt->err; - eqdma_cpm5_c2h_pftch_ctxt_entries[i++].value = pfetch_ctxt->pfch_en; - eqdma_cpm5_c2h_pftch_ctxt_entries[i++].value = pfetch_ctxt->pfch; - eqdma_cpm5_c2h_pftch_ctxt_entries[i++].value = pfetch_ctxt->sw_crdt; - eqdma_cpm5_c2h_pftch_ctxt_entries[i++].value = pfetch_ctxt->valid; -} - -/* - * eqdma_cpm5_fill_fmap_ctxt() - Helper function to fill fmap context - * into structure - * - */ -static void eqdma_cpm5_fill_fmap_ctxt(struct qdma_fmap_cfg *fmap_ctxt) -{ - eqdma_cpm5_fmap_ctxt_entries[0].value = fmap_ctxt->qbase; - eqdma_cpm5_fmap_ctxt_entries[1].value = fmap_ctxt->qmax; -} - -/* - * eqdma_cpm5_fill_intr_ctxt() - Helper function to fill interrupt context - * into structure - * - */ -static void eqdma_cpm5_fill_intr_ctxt(struct qdma_indirect_intr_ctxt - *intr_ctxt) -{ - int i = 0; - - eqdma_cpm5_ind_intr_ctxt_entries[i++].value = intr_ctxt->valid; - eqdma_cpm5_ind_intr_ctxt_entries[i++].value = intr_ctxt->vec; - eqdma_cpm5_ind_intr_ctxt_entries[i++].value = intr_ctxt->int_st; - eqdma_cpm5_ind_intr_ctxt_entries[i++].value = intr_ctxt->color; - eqdma_cpm5_ind_intr_ctxt_entries[i++].value = - intr_ctxt->baddr_4k & 0xFFFFFFFF; - eqdma_cpm5_ind_intr_ctxt_entries[i++].value = - (intr_ctxt->baddr_4k >> 32) & 0xFFFFFFFF; - eqdma_cpm5_ind_intr_ctxt_entries[i++].value = intr_ctxt->page_size; - eqdma_cpm5_ind_intr_ctxt_entries[i++].value = intr_ctxt->pidx; - eqdma_cpm5_ind_intr_ctxt_entries[i++].value = intr_ctxt->at; - eqdma_cpm5_ind_intr_ctxt_entries[i++].value = intr_ctxt->func_id; -} - -/*****************************************************************************/ -/** - * eqdma_cpm5_set_default_global_csr() - function to set the global CSR - * register to default values. The value can be modified later by using the - * set/get csr functions - * - * @dev_hndl: device handle - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -int eqdma_cpm5_set_default_global_csr(void *dev_hndl) -{ - /* Default values */ - uint32_t reg_val = 0; - uint32_t rng_sz[QDMA_NUM_RING_SIZES] = {2049, 65, 129, 193, 257, 385, - 513, 769, 1025, 1537, 3073, 4097, 6145, 8193, 12289, 16385}; - uint32_t tmr_cnt[QDMA_NUM_C2H_TIMERS] = {1, 2, 4, 5, 8, 10, 15, 20, 25, - 30, 50, 75, 100, 125, 150, 200}; - uint32_t cnt_th[QDMA_NUM_C2H_COUNTERS] = {2, 4, 8, 16, 24, 32, 48, 64, - 80, 96, 112, 128, 144, 160, 176, 192}; - uint32_t buf_sz[QDMA_NUM_C2H_BUFFER_SIZES] = {4096, 256, 512, 1024, - 2048, 3968, 4096, 4096, 4096, 4096, 4096, 4096, 4096, 8192, - 9018, 16384}; - struct qdma_dev_attributes dev_cap; - - if (!dev_hndl) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", __func__, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - eqdma_cpm5_get_device_attributes(dev_hndl, &dev_cap); - - /* Configuring CSR registers */ - /* Global ring sizes */ - qdma_write_csr_values(dev_hndl, EQDMA_CPM5_GLBL_RNG_SZ_1_ADDR, 0, - QDMA_NUM_RING_SIZES, rng_sz); - - if (dev_cap.st_en || dev_cap.mm_cmpt_en) { - /* Counter thresholds */ - qdma_write_csr_values(dev_hndl, EQDMA_CPM5_C2H_CNT_TH_ADDR, - 0, QDMA_NUM_C2H_COUNTERS, cnt_th); - - /* Timer Counters */ - qdma_write_csr_values(dev_hndl, - EQDMA_CPM5_C2H_TIMER_CNT_ADDR, 0, - QDMA_NUM_C2H_TIMERS, tmr_cnt); - - - /* Writeback Interval */ - reg_val = - FIELD_SET(GLBL_DSC_CFG_MAXFETCH_MASK, - DEFAULT_MAX_DSC_FETCH) | - FIELD_SET(GLBL_DSC_CFG_WB_ACC_INT_MASK, - DEFAULT_WRB_INT); - qdma_reg_write(dev_hndl, EQDMA_CPM5_GLBL_DSC_CFG_ADDR, - reg_val); - } - - if (dev_cap.st_en) { - /* Buffer Sizes */ - qdma_write_csr_values(dev_hndl, EQDMA_CPM5_C2H_BUF_SZ_ADDR, - 0, QDMA_NUM_C2H_BUFFER_SIZES, buf_sz); - - /* C2h Completion Coalesce Configuration */ - reg_val = - FIELD_SET(C2H_WRB_COAL_CFG_TICK_CNT_MASK, - DEFAULT_CMPT_COAL_TIMER_CNT) | - FIELD_SET(C2H_WRB_COAL_CFG_TICK_VAL_MASK, - DEFAULT_CMPT_COAL_TIMER_TICK) | - FIELD_SET(C2H_WRB_COAL_CFG_MAX_BUF_SZ_MASK, - EQDMA_CPM5_DEFAULT_CMPT_COAL_MAX_BUF_SZ); - qdma_reg_write(dev_hndl, EQDMA_CPM5_C2H_WRB_COAL_CFG_ADDR, - reg_val); - } - - eqdma_cpm5_set_perf_opt(dev_hndl); - return QDMA_SUCCESS; -} - -/* - * dump_eqdma_cpm5_context() - Helper function to dump queue context into - * string - * - * return len - length of the string copied into buffer - */ -static int dump_eqdma_cpm5_context(struct qdma_descq_context *queue_context, - uint8_t st, enum qdma_dev_q_type q_type, - char *buf, int buf_sz) -{ - int i = 0; - int n; - int len = 0; - int rv; - char banner[DEBGFS_LINE_SZ] = ""; - - if (queue_context == NULL) { - qdma_log_error("%s: queue_context is NULL, err:%d\n", - __func__, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - if (q_type == QDMA_DEV_Q_TYPE_CMPT) { - eqdma_cpm5_fill_cmpt_ctxt(&queue_context->cmpt_ctxt); - } else if (q_type == QDMA_DEV_Q_TYPE_H2C) { - eqdma_cpm5_fill_sw_ctxt(&queue_context->sw_ctxt); - eqdma_cpm5_fill_hw_ctxt(&queue_context->hw_ctxt); - eqdma_cpm5_fill_credit_ctxt(&queue_context->cr_ctxt); - } else if (q_type == QDMA_DEV_Q_TYPE_C2H) { - eqdma_cpm5_fill_sw_ctxt(&queue_context->sw_ctxt); - eqdma_cpm5_fill_hw_ctxt(&queue_context->hw_ctxt); - eqdma_cpm5_fill_credit_ctxt(&queue_context->cr_ctxt); - if (st) { - eqdma_cpm5_fill_pfetch_ctxt( - &queue_context->pfetch_ctxt); - eqdma_cpm5_fill_cmpt_ctxt( - &queue_context->cmpt_ctxt); - } - } - - eqdma_cpm5_fill_fmap_ctxt(&queue_context->fmap); - - if (q_type != QDMA_DEV_Q_TYPE_CMPT) { - for (i = 0; i < DEBGFS_LINE_SZ - 5; i++) { - rv = QDMA_SNPRINTF_S(banner + i, - (DEBGFS_LINE_SZ - i), - sizeof("-"), "-"); - if ((rv < 0) || (rv > (int)sizeof("-"))) { - qdma_log_error( - "%d:%s QDMA_SNPRINTF_S() failed, err:%d\n", - __LINE__, __func__, rv); - goto INSUF_BUF_EXIT; - } - } - - /* SW context dump */ - n = sizeof(eqdma_cpm5_sw_ctxt_entries) / - sizeof((eqdma_cpm5_sw_ctxt_entries)[0]); - for (i = 0; i < n; i++) { - if ((len >= buf_sz) || - ((len + DEBGFS_LINE_SZ) >= buf_sz)) - goto INSUF_BUF_EXIT; - - if (i == 0) { - if ((len + (3 * DEBGFS_LINE_SZ)) >= buf_sz) - goto INSUF_BUF_EXIT; - rv = QDMA_SNPRINTF_S(buf + len, (buf_sz - len), - DEBGFS_LINE_SZ, "\n%s", banner); - if ((rv < 0) || (rv > DEBGFS_LINE_SZ)) { - qdma_log_error( - "%d:%s QDMA_SNPRINTF_S() failed, err:%d\n", - __LINE__, __func__, - rv); - goto INSUF_BUF_EXIT; - } - len += rv; - - rv = QDMA_SNPRINTF_S(buf + len, (buf_sz - len), - DEBGFS_LINE_SZ, "\n%40s", "SW Context"); - if ((rv < 0) || (rv > DEBGFS_LINE_SZ)) { - qdma_log_error( - "%d:%s QDMA_SNPRINTF_S() failed, err:%d\n", - __LINE__, __func__, - rv); - goto INSUF_BUF_EXIT; - } - len += rv; - - rv = QDMA_SNPRINTF_S(buf + len, (buf_sz - len), - DEBGFS_LINE_SZ, "\n%s\n", banner); - if ((rv < 0) || (rv > DEBGFS_LINE_SZ)) { - qdma_log_error( - "%d:%s QDMA_SNPRINTF_S() failed, err:%d\n", - __LINE__, __func__, - rv); - goto INSUF_BUF_EXIT; - } - len += rv; - } - - rv = QDMA_SNPRINTF_S(buf + len, (buf_sz - len), - DEBGFS_LINE_SZ, - "%-47s %#-10x %u\n", - eqdma_cpm5_sw_ctxt_entries[i].name, - eqdma_cpm5_sw_ctxt_entries[i].value, - eqdma_cpm5_sw_ctxt_entries[i].value); - if ((rv < 0) || (rv > DEBGFS_LINE_SZ)) { - qdma_log_error( - "%d:%s QDMA_SNPRINTF_S() failed, err:%d\n", - __LINE__, __func__, - rv); - goto INSUF_BUF_EXIT; - } - len += rv; - } - - /* HW context dump */ - n = sizeof(eqdma_cpm5_hw_ctxt_entries) / - sizeof((eqdma_cpm5_hw_ctxt_entries)[0]); - for (i = 0; i < n; i++) { - if ((len >= buf_sz) || - ((len + DEBGFS_LINE_SZ) >= buf_sz)) - goto INSUF_BUF_EXIT; - - if (i == 0) { - if ((len + (3 * DEBGFS_LINE_SZ)) >= buf_sz) - goto INSUF_BUF_EXIT; - - rv = QDMA_SNPRINTF_S(buf + len, (buf_sz - len), - DEBGFS_LINE_SZ, "\n%s", banner); - if ((rv < 0) || (rv > DEBGFS_LINE_SZ)) { - qdma_log_error( - "%d:%s QDMA_SNPRINTF_S() failed, err:%d\n", - __LINE__, __func__, - rv); - goto INSUF_BUF_EXIT; - } - len += rv; - - rv = QDMA_SNPRINTF_S(buf + len, (buf_sz - len), - DEBGFS_LINE_SZ, "\n%40s", "HW Context"); - if ((rv < 0) || (rv > DEBGFS_LINE_SZ)) { - qdma_log_error( - "%d:%s QDMA_SNPRINTF_S() failed, err:%d\n", - __LINE__, __func__, - rv); - goto INSUF_BUF_EXIT; - } - len += rv; - - rv = QDMA_SNPRINTF_S(buf + len, (buf_sz - len), - DEBGFS_LINE_SZ, "\n%s\n", banner); - if ((rv < 0) || (rv > DEBGFS_LINE_SZ)) { - qdma_log_error( - "%d:%s QDMA_SNPRINTF_S() failed, err:%d\n", - __LINE__, __func__, - rv); - goto INSUF_BUF_EXIT; - } - len += rv; - } - - rv = QDMA_SNPRINTF_S(buf + len, (buf_sz - len), - DEBGFS_LINE_SZ, - "%-47s %#-10x %u\n", - eqdma_cpm5_hw_ctxt_entries[i].name, - eqdma_cpm5_hw_ctxt_entries[i].value, - eqdma_cpm5_hw_ctxt_entries[i].value); - if ((rv < 0) || (rv > DEBGFS_LINE_SZ)) { - qdma_log_error( - "%d:%s QDMA_SNPRINTF_S() failed, err:%d\n", - __LINE__, __func__, - rv); - goto INSUF_BUF_EXIT; - } - len += rv; - } - - /* Credit context dump */ - n = sizeof(eqdma_cpm5_credit_ctxt_entries) / - sizeof((eqdma_cpm5_credit_ctxt_entries)[0]); - for (i = 0; i < n; i++) { - if ((len >= buf_sz) || - ((len + DEBGFS_LINE_SZ) >= buf_sz)) - goto INSUF_BUF_EXIT; - - if (i == 0) { - if ((len + (3 * DEBGFS_LINE_SZ)) >= buf_sz) - goto INSUF_BUF_EXIT; - - rv = QDMA_SNPRINTF_S(buf + len, (buf_sz - len), - DEBGFS_LINE_SZ, "\n%s", banner); - if ((rv < 0) || (rv > DEBGFS_LINE_SZ)) { - qdma_log_error( - "%d:%s QDMA_SNPRINTF_S() failed, err:%d\n", - __LINE__, __func__, - rv); - goto INSUF_BUF_EXIT; - } - len += rv; - - rv = QDMA_SNPRINTF_S(buf + len, (buf_sz - len), - DEBGFS_LINE_SZ, "\n%40s", - "Credit Context"); - if ((rv < 0) || (rv > DEBGFS_LINE_SZ)) { - qdma_log_error( - "%d:%s QDMA_SNPRINTF_S() failed, err:%d\n", - __LINE__, __func__, - rv); - goto INSUF_BUF_EXIT; - } - len += rv; - - rv = QDMA_SNPRINTF_S(buf + len, (buf_sz - len), - DEBGFS_LINE_SZ, "\n%s\n", banner); - if ((rv < 0) || (rv > DEBGFS_LINE_SZ)) { - qdma_log_error( - "%d:%s QDMA_SNPRINTF_S() failed, err:%d\n", - __LINE__, __func__, - rv); - goto INSUF_BUF_EXIT; - } - len += rv; - } - - rv = QDMA_SNPRINTF_S(buf + len, (buf_sz - len), - DEBGFS_LINE_SZ, - "%-47s %#-10x %u\n", - eqdma_cpm5_credit_ctxt_entries[i].name, - eqdma_cpm5_credit_ctxt_entries[i].value, - eqdma_cpm5_credit_ctxt_entries[i].value); - if ((rv < 0) || (rv > DEBGFS_LINE_SZ)) { - qdma_log_error( - "%d:%s QDMA_SNPRINTF_S() failed, err:%d\n", - __LINE__, __func__, - rv); - goto INSUF_BUF_EXIT; - } - len += rv; - } - } - - if ((q_type == QDMA_DEV_Q_TYPE_CMPT) || - (st && q_type == QDMA_DEV_Q_TYPE_C2H)) { - /* Completion context dump */ - n = sizeof(eqdma_cpm5_cmpt_ctxt_entries) / - sizeof((eqdma_cpm5_cmpt_ctxt_entries)[0]); - for (i = 0; i < n; i++) { - if ((len >= buf_sz) || - ((len + DEBGFS_LINE_SZ) >= buf_sz)) - goto INSUF_BUF_EXIT; - - if (i == 0) { - if ((len + (3 * DEBGFS_LINE_SZ)) >= buf_sz) - goto INSUF_BUF_EXIT; - - rv = QDMA_SNPRINTF_S(buf + len, (buf_sz - len), - DEBGFS_LINE_SZ, "\n%s", banner); - if ((rv < 0) || (rv > DEBGFS_LINE_SZ)) { - qdma_log_error( - "%d:%s QDMA_SNPRINTF_S() failed, err:%d\n", - __LINE__, __func__, - rv); - goto INSUF_BUF_EXIT; - } - len += rv; - - rv = QDMA_SNPRINTF_S(buf + len, (buf_sz - len), - DEBGFS_LINE_SZ, "\n%40s", - "Completion Context"); - if ((rv < 0) || (rv > DEBGFS_LINE_SZ)) { - qdma_log_error( - "%d:%s QDMA_SNPRINTF_S() failed, err:%d\n", - __LINE__, __func__, - rv); - goto INSUF_BUF_EXIT; - } - len += rv; - - rv = QDMA_SNPRINTF_S(buf + len, (buf_sz - len), - DEBGFS_LINE_SZ, "\n%s\n", banner); - if ((rv < 0) || (rv > DEBGFS_LINE_SZ)) { - qdma_log_error( - "%d:%s QDMA_SNPRINTF_S() failed, err:%d\n", - __LINE__, __func__, - rv); - goto INSUF_BUF_EXIT; - } - len += rv; - } - - rv = QDMA_SNPRINTF_S(buf + len, (buf_sz - len), - DEBGFS_LINE_SZ, - "%-47s %#-10x %u\n", - eqdma_cpm5_cmpt_ctxt_entries[i].name, - eqdma_cpm5_cmpt_ctxt_entries[i].value, - eqdma_cpm5_cmpt_ctxt_entries[i].value); - if ((rv < 0) || (rv > DEBGFS_LINE_SZ)) { - qdma_log_error( - "%d:%s QDMA_SNPRINTF_S() failed, err:%d\n", - __LINE__, __func__, - rv); - goto INSUF_BUF_EXIT; - } - len += rv; - } - } - - if (st && q_type == QDMA_DEV_Q_TYPE_C2H) { - /* Prefetch context dump */ - n = sizeof(eqdma_cpm5_c2h_pftch_ctxt_entries) / - sizeof(eqdma_cpm5_c2h_pftch_ctxt_entries[0]); - for (i = 0; i < n; i++) { - if ((len >= buf_sz) || - ((len + DEBGFS_LINE_SZ) >= buf_sz)) - goto INSUF_BUF_EXIT; - - if (i == 0) { - if ((len + (3 * DEBGFS_LINE_SZ)) >= buf_sz) - goto INSUF_BUF_EXIT; - - rv = QDMA_SNPRINTF_S(buf + len, (buf_sz - len), - DEBGFS_LINE_SZ, "\n%s", banner); - if ((rv < 0) || (rv > DEBGFS_LINE_SZ)) { - qdma_log_error( - "%d:%s QDMA_SNPRINTF_S() failed, err:%d\n", - __LINE__, __func__, - rv); - goto INSUF_BUF_EXIT; - } - len += rv; - - rv = QDMA_SNPRINTF_S(buf + len, (buf_sz - len), - DEBGFS_LINE_SZ, "\n%40s", - "Prefetch Context"); - if ((rv < 0) || (rv > DEBGFS_LINE_SZ)) { - qdma_log_error( - "%d:%s QDMA_SNPRINTF_S() failed, err:%d\n", - __LINE__, __func__, - rv); - goto INSUF_BUF_EXIT; - } - len += rv; - - rv = QDMA_SNPRINTF_S(buf + len, (buf_sz - len), - DEBGFS_LINE_SZ, "\n%s\n", banner); - if ((rv < 0) || (rv > DEBGFS_LINE_SZ)) { - qdma_log_error( - "%d:%s QDMA_SNPRINTF_S() failed, err:%d\n", - __LINE__, __func__, - rv); - goto INSUF_BUF_EXIT; - } - len += rv; - } - - rv = QDMA_SNPRINTF_S(buf + len, (buf_sz - len), - DEBGFS_LINE_SZ, - "%-47s %#-10x %u\n", - eqdma_cpm5_c2h_pftch_ctxt_entries[i].name, - eqdma_cpm5_c2h_pftch_ctxt_entries[i].value, - eqdma_cpm5_c2h_pftch_ctxt_entries[i].value); - if ((rv < 0) || (rv > DEBGFS_LINE_SZ)) { - qdma_log_error( - "%d:%s QDMA_SNPRINTF_S() failed, err:%d\n", - __LINE__, __func__, - rv); - goto INSUF_BUF_EXIT; - } - len += rv; - } - } - - /* Fmap context dump */ - n = sizeof(eqdma_cpm5_fmap_ctxt_entries) / - sizeof(eqdma_cpm5_fmap_ctxt_entries[0]); - for (i = 0; i < n; i++) { - if ((len >= buf_sz) || - ((len + DEBGFS_LINE_SZ) >= buf_sz)) - goto INSUF_BUF_EXIT; - - if (i == 0) { - if ((len + (3 * DEBGFS_LINE_SZ)) >= buf_sz) - goto INSUF_BUF_EXIT; - - rv = QDMA_SNPRINTF_S(buf + len, (buf_sz - len), - DEBGFS_LINE_SZ, "\n%s", banner); - if ((rv < 0) || (rv > DEBGFS_LINE_SZ)) { - qdma_log_error( - "%d:%s QDMA_SNPRINTF_S() failed, err:%d\n", - __LINE__, __func__, - rv); - goto INSUF_BUF_EXIT; - } - len += rv; - - rv = QDMA_SNPRINTF_S(buf + len, (buf_sz - len), - DEBGFS_LINE_SZ, "\n%40s", - "Fmap Context"); - if ((rv < 0) || (rv > DEBGFS_LINE_SZ)) { - qdma_log_error( - "%d:%s QDMA_SNPRINTF_S() failed, err:%d\n", - __LINE__, __func__, - rv); - goto INSUF_BUF_EXIT; - } - len += rv; - - rv = QDMA_SNPRINTF_S(buf + len, (buf_sz - len), - DEBGFS_LINE_SZ, "\n%s\n", banner); - if ((rv < 0) || (rv > DEBGFS_LINE_SZ)) { - qdma_log_error( - "%d:%s QDMA_SNPRINTF_S() failed, err:%d\n", - __LINE__, __func__, - rv); - goto INSUF_BUF_EXIT; - } - len += rv; - } - - rv = QDMA_SNPRINTF_S(buf + len, - (buf_sz - len), DEBGFS_LINE_SZ, - "%-47s %#-10x %u\n", - eqdma_cpm5_fmap_ctxt_entries[i].name, - eqdma_cpm5_fmap_ctxt_entries[i].value, - eqdma_cpm5_fmap_ctxt_entries[i].value); - if ((rv < 0) || (rv > DEBGFS_LINE_SZ)) { - qdma_log_error( - "%d:%s QDMA_SNPRINTF_S() failed, err:%d\n", - __LINE__, __func__, - rv); - goto INSUF_BUF_EXIT; - } - len += rv; - } - - return len; - -INSUF_BUF_EXIT: - if (buf_sz > DEBGFS_LINE_SZ) { - rv = QDMA_SNPRINTF_S((buf + buf_sz - DEBGFS_LINE_SZ), - buf_sz, DEBGFS_LINE_SZ, - "\n\nInsufficient buffer size, partial context dump\n"); - if ((rv < 0) || (rv > DEBGFS_LINE_SZ)) { - qdma_log_error( - "%d:%s QDMA_SNPRINTF_S() failed, err:%d\n", - __LINE__, __func__, - rv); - } - } - - qdma_log_error("%s: Insufficient buffer size, err:%d\n", - __func__, -QDMA_ERR_NO_MEM); - - return -QDMA_ERR_NO_MEM; -} - -/* - * dump_eqdma_cpm5_intr_context() - Helper function to dump interrupt - * context into string - * - * return len - length of the string copied into buffer - */ -static int dump_eqdma_cpm5_intr_context(struct qdma_indirect_intr_ctxt - *intr_ctx, - int ring_index, - char *buf, int buf_sz) -{ - int i = 0; - int n; - int len = 0; - int rv; - char banner[DEBGFS_LINE_SZ] = ""; - - eqdma_cpm5_fill_intr_ctxt(intr_ctx); - - for (i = 0; i < DEBGFS_LINE_SZ - 5; i++) { - rv = QDMA_SNPRINTF_S(banner + i, - (DEBGFS_LINE_SZ - i), - sizeof("-"), "-"); - if ((rv < 0) || (rv > (int)sizeof("-"))) { - qdma_log_error( - "%d:%s QDMA_SNPRINTF_S() failed, err:%d\n", - __LINE__, __func__, - rv); - goto INSUF_BUF_EXIT; - } - } - - /* Interrupt context dump */ - n = sizeof(eqdma_cpm5_ind_intr_ctxt_entries) / - sizeof((eqdma_cpm5_ind_intr_ctxt_entries)[0]); - for (i = 0; i < n; i++) { - if ((len >= buf_sz) || ((len + DEBGFS_LINE_SZ) >= buf_sz)) - goto INSUF_BUF_EXIT; - - if (i == 0) { - if ((len + (3 * DEBGFS_LINE_SZ)) >= buf_sz) - goto INSUF_BUF_EXIT; - - rv = QDMA_SNPRINTF_S(buf + len, (buf_sz - len), - DEBGFS_LINE_SZ, "\n%s", banner); - if ((rv < 0) || (rv > DEBGFS_LINE_SZ)) { - qdma_log_error( - "%d:%s QDMA_SNPRINTF_S() failed, err:%d\n", - __LINE__, __func__, - rv); - goto INSUF_BUF_EXIT; - } - len += rv; - - rv = QDMA_SNPRINTF_S(buf + len, (buf_sz - len), - DEBGFS_LINE_SZ, "\n%50s %d", - "Interrupt Context for ring#", ring_index); - if ((rv < 0) || (rv > DEBGFS_LINE_SZ)) { - qdma_log_error( - "%d:%s QDMA_SNPRINTF_S() failed, err:%d\n", - __LINE__, __func__, - rv); - goto INSUF_BUF_EXIT; - } - len += rv; - - rv = QDMA_SNPRINTF_S(buf + len, (buf_sz - len), - DEBGFS_LINE_SZ, "\n%s\n", banner); - if ((rv < 0) || (rv > DEBGFS_LINE_SZ)) { - qdma_log_error( - "%d:%s QDMA_SNPRINTF_S() failed, err:%d\n", - __LINE__, __func__, - rv); - goto INSUF_BUF_EXIT; - } - len += rv; - } - - rv = QDMA_SNPRINTF_S(buf + len, (buf_sz - len), DEBGFS_LINE_SZ, - "%-47s %#-10x %u\n", - eqdma_cpm5_ind_intr_ctxt_entries[i].name, - eqdma_cpm5_ind_intr_ctxt_entries[i].value, - eqdma_cpm5_ind_intr_ctxt_entries[i].value); - if ((rv < 0) || (rv > DEBGFS_LINE_SZ)) { - qdma_log_error( - "%d:%s QDMA_SNPRINTF_S() failed, err:%d\n", - __LINE__, __func__, - rv); - goto INSUF_BUF_EXIT; - } - len += rv; - } - - return len; - -INSUF_BUF_EXIT: - if (buf_sz > DEBGFS_LINE_SZ) { - rv = QDMA_SNPRINTF_S((buf + buf_sz - DEBGFS_LINE_SZ), - buf_sz, DEBGFS_LINE_SZ, - "\n\nInsufficient buffer size, partial context dump\n"); - if ((rv < 0) || (rv > DEBGFS_LINE_SZ)) { - qdma_log_error( - "%d:%s QDMA_SNPRINTF_S() failed, err:%d\n", - __LINE__, __func__, - rv); - } - } - - qdma_log_error("%s: Insufficient buffer size, err:%d\n", - __func__, -QDMA_ERR_NO_MEM); - - return -QDMA_ERR_NO_MEM; -} - -/*****************************************************************************/ -/** - * eqdma_cpm5_get_version() - Function to get the eqdma version - * - * @dev_hndl: device handle - * @is_vf: Whether PF or VF - * @version_info: pointer to hold the version info - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -int eqdma_cpm5_get_version(void *dev_hndl, uint8_t is_vf, - struct qdma_hw_version_info *version_info) -{ - uint32_t reg_val = 0; - uint32_t reg_addr = (is_vf) ? EQDMA_CPM5_OFFSET_VF_VERSION : - EQDMA_CPM5_GLBL2_MISC_CAP_ADDR; - - if (!dev_hndl) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - reg_val = qdma_reg_read(dev_hndl, reg_addr); - - qdma_fetch_version_details(dev_hndl, is_vf, reg_val, version_info); - - return QDMA_SUCCESS; -} - -/*****************************************************************************/ -/** - * eqdma_cpm5_sw_context_write() - create sw context and program it - * - * @dev_hndl: device handle - * @c2h: is c2h queue - * @hw_qid: hardware qid of the queue - * @ctxt: pointer to the SW context data strucutre - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -static int eqdma_cpm5_sw_context_write(void *dev_hndl, uint8_t c2h, - uint16_t hw_qid, - const struct qdma_descq_sw_ctxt *ctxt) -{ - uint32_t sw_ctxt[EQDMA_CPM5_SW_CONTEXT_NUM_WORDS] = {0}; - uint16_t num_words_count = 0; - uint32_t pasid_l, pasid_h; - uint32_t virtio_desc_base_l, virtio_desc_base_m, virtio_desc_base_h; - enum ind_ctxt_cmd_sel sel = c2h ? - QDMA_CTXT_SEL_SW_C2H : QDMA_CTXT_SEL_SW_H2C; - - /* Input args check */ - if (!dev_hndl || !ctxt) { - qdma_log_error("%s: dev_handle=%p sw_ctxt=%p NULL, err:%d\n", - __func__, dev_hndl, ctxt, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - pasid_l = - FIELD_GET(EQDMA_CPM5_SW_CTXT_PASID_GET_L_MASK, ctxt->pasid); - pasid_h = - FIELD_GET(EQDMA_CPM5_SW_CTXT_PASID_GET_H_MASK, ctxt->pasid); - - virtio_desc_base_l = (uint32_t)FIELD_GET( - EQDMA_CPM5_SW_CTXT_VIRTIO_DSC_BASE_GET_L_MASK, - ctxt->virtio_dsc_base); - virtio_desc_base_m = (uint32_t)FIELD_GET( - EQDMA_CPM5_SW_CTXT_VIRTIO_DSC_BASE_GET_M_MASK, - ctxt->virtio_dsc_base); - virtio_desc_base_h = (uint32_t)FIELD_GET( - EQDMA_CPM5_SW_CTXT_VIRTIO_DSC_BASE_GET_H_MASK, - ctxt->virtio_dsc_base); - - sw_ctxt[num_words_count++] = - FIELD_SET(SW_IND_CTXT_DATA_W0_PIDX_MASK, ctxt->pidx) | - FIELD_SET(SW_IND_CTXT_DATA_W0_IRQ_ARM_MASK, ctxt->irq_arm) | - FIELD_SET(SW_IND_CTXT_DATA_W0_FNC_MASK, ctxt->fnc_id); - - qdma_log_debug("%s: pidx=%x, irq_arm=%x, fnc_id=%x\n", - __func__, ctxt->pidx, ctxt->irq_arm, ctxt->fnc_id); - - sw_ctxt[num_words_count++] = - FIELD_SET(SW_IND_CTXT_DATA_W1_QEN_MASK, ctxt->qen) | - FIELD_SET(SW_IND_CTXT_DATA_W1_FCRD_EN_MASK, ctxt->frcd_en) | - FIELD_SET(SW_IND_CTXT_DATA_W1_WBI_CHK_MASK, ctxt->wbi_chk) | - FIELD_SET(SW_IND_CTXT_DATA_W1_WBI_INTVL_EN_MASK, - ctxt->wbi_intvl_en) | - FIELD_SET(SW_IND_CTXT_DATA_W1_AT_MASK, ctxt->at) | - FIELD_SET(SW_IND_CTXT_DATA_W1_FETCH_MAX_MASK, ctxt->fetch_max) | - FIELD_SET(SW_IND_CTXT_DATA_W1_RNG_SZ_MASK, ctxt->rngsz_idx) | - FIELD_SET(SW_IND_CTXT_DATA_W1_DSC_SZ_MASK, ctxt->desc_sz) | - FIELD_SET(SW_IND_CTXT_DATA_W1_BYPASS_MASK, ctxt->bypass) | - FIELD_SET(SW_IND_CTXT_DATA_W1_MM_CHN_MASK, ctxt->mm_chn) | - FIELD_SET(SW_IND_CTXT_DATA_W1_WBK_EN_MASK, ctxt->wbk_en) | - FIELD_SET(SW_IND_CTXT_DATA_W1_IRQ_EN_MASK, ctxt->irq_en) | - FIELD_SET(SW_IND_CTXT_DATA_W1_PORT_ID_MASK, ctxt->port_id) | - FIELD_SET(SW_IND_CTXT_DATA_W1_IRQ_NO_LAST_MASK, - ctxt->irq_no_last) | - FIELD_SET(SW_IND_CTXT_DATA_W1_ERR_MASK, ctxt->err) | - FIELD_SET(SW_IND_CTXT_DATA_W1_ERR_WB_SENT_MASK, - ctxt->err_wb_sent) | - FIELD_SET(SW_IND_CTXT_DATA_W1_IRQ_REQ_MASK, ctxt->irq_req) | - FIELD_SET(SW_IND_CTXT_DATA_W1_MRKR_DIS_MASK, ctxt->mrkr_dis) | - FIELD_SET(SW_IND_CTXT_DATA_W1_IS_MM_MASK, ctxt->is_mm); - - qdma_log_debug("%s: qen=%x, frcd_en=%x, wbi_chk=%x, wbi_intvl_en=%x\n", - __func__, ctxt->qen, ctxt->frcd_en, ctxt->wbi_chk, - ctxt->wbi_intvl_en); - - qdma_log_debug("%s: at=%x, fetch_max=%x, rngsz_idx=%x, desc_sz=%x\n", - __func__, ctxt->at, ctxt->fetch_max, ctxt->rngsz_idx, - ctxt->desc_sz); - - qdma_log_debug("%s: bypass=%x, mm_chn=%x, wbk_en=%x, irq_en=%x\n", - __func__, ctxt->bypass, ctxt->mm_chn, ctxt->wbk_en, - ctxt->irq_en); - - qdma_log_debug("%s: port_id=%x, irq_no_last=%x,err=%x", - __func__, ctxt->port_id, ctxt->irq_no_last, ctxt->err); - qdma_log_debug(", err_wb_sent=%x\n", ctxt->err_wb_sent); - - qdma_log_debug("%s: irq_req=%x, mrkr_dis=%x, is_mm=%x\n", - __func__, ctxt->irq_req, ctxt->mrkr_dis, ctxt->is_mm); - - sw_ctxt[num_words_count++] = ctxt->ring_bs_addr & 0xffffffff; - sw_ctxt[num_words_count++] = (ctxt->ring_bs_addr >> 32) & 0xffffffff; - - sw_ctxt[num_words_count++] = - FIELD_SET(SW_IND_CTXT_DATA_W4_VEC_MASK, ctxt->vec) | - FIELD_SET(SW_IND_CTXT_DATA_W4_INT_AGGR_MASK, ctxt->intr_aggr) | - FIELD_SET(SW_IND_CTXT_DATA_W4_DIS_INTR_ON_VF_MASK, - ctxt->dis_intr_on_vf) | - FIELD_SET(SW_IND_CTXT_DATA_W4_VIRTIO_EN_MASK, - ctxt->virtio_en) | - FIELD_SET(SW_IND_CTXT_DATA_W4_PACK_BYP_OUT_MASK, - ctxt->pack_byp_out) | - FIELD_SET(SW_IND_CTXT_DATA_W4_IRQ_BYP_MASK, ctxt->irq_byp) | - FIELD_SET(SW_IND_CTXT_DATA_W4_HOST_ID_MASK, ctxt->host_id) | - FIELD_SET(SW_IND_CTXT_DATA_W4_PASID_L_MASK, pasid_l); - - sw_ctxt[num_words_count++] = - FIELD_SET(SW_IND_CTXT_DATA_W5_PASID_H_MASK, pasid_h) | - FIELD_SET(SW_IND_CTXT_DATA_W5_PASID_EN_MASK, ctxt->pasid_en) | - FIELD_SET(SW_IND_CTXT_DATA_W5_VIRTIO_DSC_BASE_L_MASK, - virtio_desc_base_l); - - sw_ctxt[num_words_count++] = - FIELD_SET(SW_IND_CTXT_DATA_W6_VIRTIO_DSC_BASE_M_MASK, - virtio_desc_base_m); - - sw_ctxt[num_words_count++] = - FIELD_SET(SW_IND_CTXT_DATA_W7_VIRTIO_DSC_BASE_H_MASK, - virtio_desc_base_h); - - - qdma_log_debug("%s: vec=%x, intr_aggr=%x\n", - __func__, ctxt->vec, ctxt->intr_aggr); - - return eqdma_cpm5_indirect_reg_write(dev_hndl, sel, hw_qid, - sw_ctxt, num_words_count); -} - -/*****************************************************************************/ -/** - * eqdma_cpm5_sw_context_read() - read sw context - * - * @dev_hndl: device handle - * @c2h: is c2h queue - * @hw_qid: hardware qid of the queue - * @ctxt: pointer to the output context data - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -static int eqdma_cpm5_sw_context_read(void *dev_hndl, uint8_t c2h, - uint16_t hw_qid, - struct qdma_descq_sw_ctxt *ctxt) -{ - int rv = QDMA_SUCCESS; - uint32_t sw_ctxt[EQDMA_CPM5_SW_CONTEXT_NUM_WORDS] = {0}; - uint32_t pasid_l, pasid_h; - uint32_t virtio_desc_base_l, virtio_desc_base_m, virtio_desc_base_h; - enum ind_ctxt_cmd_sel sel = c2h ? - QDMA_CTXT_SEL_SW_C2H : QDMA_CTXT_SEL_SW_H2C; - - if (!dev_hndl || !ctxt) { - qdma_log_error("%s: dev_handle=%p sw_ctxt=%p NULL, err:%d\n", - __func__, dev_hndl, ctxt, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - rv = eqdma_cpm5_indirect_reg_read(dev_hndl, sel, hw_qid, - EQDMA_CPM5_SW_CONTEXT_NUM_WORDS, sw_ctxt); - if (rv < 0) - return rv; - - ctxt->pidx = FIELD_GET(SW_IND_CTXT_DATA_W0_PIDX_MASK, sw_ctxt[0]); - ctxt->irq_arm = - (uint8_t)(FIELD_GET(SW_IND_CTXT_DATA_W0_IRQ_ARM_MASK, - sw_ctxt[0])); - ctxt->fnc_id = FIELD_GET(SW_IND_CTXT_DATA_W0_FNC_MASK, sw_ctxt[0]); - - qdma_log_debug("%s: pidx=%x, irq_arm=%x, fnc_id=%x", - __func__, ctxt->pidx, ctxt->irq_arm, ctxt->fnc_id); - - ctxt->qen = FIELD_GET(SW_IND_CTXT_DATA_W1_QEN_MASK, sw_ctxt[1]); - ctxt->frcd_en = FIELD_GET(SW_IND_CTXT_DATA_W1_FCRD_EN_MASK, sw_ctxt[1]); - ctxt->wbi_chk = FIELD_GET(SW_IND_CTXT_DATA_W1_WBI_CHK_MASK, sw_ctxt[1]); - ctxt->wbi_intvl_en = - FIELD_GET(SW_IND_CTXT_DATA_W1_WBI_INTVL_EN_MASK, sw_ctxt[1]); - ctxt->at = FIELD_GET(SW_IND_CTXT_DATA_W1_AT_MASK, sw_ctxt[1]); - ctxt->fetch_max = - (uint8_t)FIELD_GET(SW_IND_CTXT_DATA_W1_FETCH_MAX_MASK, - sw_ctxt[1]); - ctxt->rngsz_idx = - (uint8_t)(FIELD_GET(SW_IND_CTXT_DATA_W1_RNG_SZ_MASK, - sw_ctxt[1])); - ctxt->desc_sz = - (uint8_t)(FIELD_GET(SW_IND_CTXT_DATA_W1_DSC_SZ_MASK, - sw_ctxt[1])); - ctxt->bypass = - (uint8_t)(FIELD_GET(SW_IND_CTXT_DATA_W1_BYPASS_MASK, - sw_ctxt[1])); - ctxt->mm_chn = - (uint8_t)(FIELD_GET(SW_IND_CTXT_DATA_W1_MM_CHN_MASK, - sw_ctxt[1])); - ctxt->wbk_en = - (uint8_t)(FIELD_GET(SW_IND_CTXT_DATA_W1_WBK_EN_MASK, - sw_ctxt[1])); - ctxt->irq_en = - (uint8_t)(FIELD_GET(SW_IND_CTXT_DATA_W1_IRQ_EN_MASK, - sw_ctxt[1])); - ctxt->port_id = - (uint8_t)(FIELD_GET(SW_IND_CTXT_DATA_W1_PORT_ID_MASK, - sw_ctxt[1])); - ctxt->irq_no_last = - (uint8_t)(FIELD_GET(SW_IND_CTXT_DATA_W1_IRQ_NO_LAST_MASK, - sw_ctxt[1])); - ctxt->err = - (uint8_t)(FIELD_GET(SW_IND_CTXT_DATA_W1_ERR_MASK, sw_ctxt[1])); - ctxt->err_wb_sent = - (uint8_t)(FIELD_GET(SW_IND_CTXT_DATA_W1_ERR_WB_SENT_MASK, - sw_ctxt[1])); - ctxt->irq_req = - (uint8_t)(FIELD_GET(SW_IND_CTXT_DATA_W1_IRQ_REQ_MASK, - sw_ctxt[1])); - ctxt->mrkr_dis = - (uint8_t)(FIELD_GET(SW_IND_CTXT_DATA_W1_MRKR_DIS_MASK, - sw_ctxt[1])); - ctxt->is_mm = - (uint8_t)(FIELD_GET(SW_IND_CTXT_DATA_W1_IS_MM_MASK, - sw_ctxt[1])); - - qdma_log_debug("%s: qen=%x, frcd_en=%x, wbi_chk=%x, wbi_intvl_en=%x\n", - __func__, ctxt->qen, ctxt->frcd_en, ctxt->wbi_chk, - ctxt->wbi_intvl_en); - qdma_log_debug("%s: at=%x, fetch_max=%x, rngsz_idx=%x, desc_sz=%x\n", - __func__, ctxt->at, ctxt->fetch_max, ctxt->rngsz_idx, - ctxt->desc_sz); - qdma_log_debug("%s: bypass=%x, mm_chn=%x, wbk_en=%x, irq_en=%x\n", - __func__, ctxt->bypass, ctxt->mm_chn, ctxt->wbk_en, - ctxt->irq_en); - qdma_log_debug("%s: port_id=%x, irq_no_last=%x,", - __func__, ctxt->port_id, ctxt->irq_no_last); - qdma_log_debug(" err=%x, err_wb_sent=%x\n", - ctxt->err, ctxt->err_wb_sent); - qdma_log_debug("%s: irq_req=%x, mrkr_dis=%x, is_mm=%x\n", - __func__, ctxt->irq_req, ctxt->mrkr_dis, ctxt->is_mm); - - ctxt->ring_bs_addr = ((uint64_t)sw_ctxt[3] << 32) | (sw_ctxt[2]); - - ctxt->vec = FIELD_GET(SW_IND_CTXT_DATA_W4_VEC_MASK, sw_ctxt[4]); - ctxt->intr_aggr = (uint8_t)(FIELD_GET(SW_IND_CTXT_DATA_W4_INT_AGGR_MASK, - sw_ctxt[4])); - ctxt->dis_intr_on_vf = - (uint8_t)(FIELD_GET(SW_IND_CTXT_DATA_W4_DIS_INTR_ON_VF_MASK, - sw_ctxt[4])); - ctxt->virtio_en = - (uint8_t)(FIELD_GET(SW_IND_CTXT_DATA_W4_VIRTIO_EN_MASK, - sw_ctxt[4])); - ctxt->pack_byp_out = - (uint8_t)(FIELD_GET(SW_IND_CTXT_DATA_W4_PACK_BYP_OUT_MASK, - sw_ctxt[4])); - ctxt->irq_byp = - (uint8_t)(FIELD_GET(SW_IND_CTXT_DATA_W4_IRQ_BYP_MASK, - sw_ctxt[4])); - ctxt->host_id = - (uint8_t)(FIELD_GET(SW_IND_CTXT_DATA_W4_HOST_ID_MASK, - sw_ctxt[4])); - pasid_l = FIELD_GET(SW_IND_CTXT_DATA_W4_PASID_L_MASK, sw_ctxt[4]); - - pasid_h = FIELD_GET(SW_IND_CTXT_DATA_W5_PASID_H_MASK, sw_ctxt[5]); - ctxt->pasid_en = (uint8_t)FIELD_GET(SW_IND_CTXT_DATA_W5_PASID_EN_MASK, - sw_ctxt[5]); - virtio_desc_base_l = - FIELD_GET(SW_IND_CTXT_DATA_W5_VIRTIO_DSC_BASE_L_MASK, - sw_ctxt[5]); - virtio_desc_base_m = - FIELD_GET(SW_IND_CTXT_DATA_W6_VIRTIO_DSC_BASE_M_MASK, - sw_ctxt[6]); - - virtio_desc_base_h = - FIELD_GET(SW_IND_CTXT_DATA_W7_VIRTIO_DSC_BASE_H_MASK, - sw_ctxt[6]); - - ctxt->pasid = - FIELD_SET(EQDMA_CPM5_SW_CTXT_PASID_GET_L_MASK, pasid_l) | - FIELD_SET(EQDMA_CPM5_SW_CTXT_PASID_GET_H_MASK, pasid_h); - - ctxt->virtio_dsc_base = - FIELD_SET(EQDMA_CPM5_SW_CTXT_VIRTIO_DSC_BASE_GET_L_MASK, - (uint64_t)virtio_desc_base_l) | - FIELD_SET(EQDMA_CPM5_SW_CTXT_VIRTIO_DSC_BASE_GET_M_MASK, - (uint64_t)virtio_desc_base_m) | - FIELD_SET(EQDMA_CPM5_SW_CTXT_VIRTIO_DSC_BASE_GET_H_MASK, - (uint64_t)virtio_desc_base_h); - - qdma_log_debug("%s: vec=%x, intr_aggr=%x\n", - __func__, ctxt->vec, ctxt->intr_aggr); - - return QDMA_SUCCESS; -} - -/*****************************************************************************/ -/** - * eqdma_cpm5_sw_context_clear() - clear sw context - * - * @dev_hndl: device handle - * @c2h: is c2h queue - * @hw_qid: hardware qid of the queue - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -static int eqdma_cpm5_sw_context_clear(void *dev_hndl, uint8_t c2h, - uint16_t hw_qid) -{ - enum ind_ctxt_cmd_sel sel = c2h ? - QDMA_CTXT_SEL_SW_C2H : QDMA_CTXT_SEL_SW_H2C; - - if (!dev_hndl) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", __func__, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - return eqdma_cpm5_indirect_reg_clear(dev_hndl, sel, hw_qid); -} - -/*****************************************************************************/ -/** - * eqdma_cpm5_sw_context_invalidate() - invalidate sw context - * - * @dev_hndl: device handle - * @c2h: is c2h queue - * @hw_qid: hardware qid of the queue - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -static int eqdma_cpm5_sw_context_invalidate(void *dev_hndl, uint8_t c2h, - uint16_t hw_qid) -{ - enum ind_ctxt_cmd_sel sel = c2h ? - QDMA_CTXT_SEL_SW_C2H : QDMA_CTXT_SEL_SW_H2C; - - if (!dev_hndl) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", __func__, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - return eqdma_cpm5_indirect_reg_invalidate(dev_hndl, sel, hw_qid); -} - -/*****************************************************************************/ -/** - * eqdma_cpm5_sw_ctx_conf() - configure SW context - * - * @dev_hndl: device handle - * @c2h: is c2h queue - * @hw_qid: hardware qid of the queue - * @ctxt: pointer to the context data - * @access_type HW access type (qdma_hw_access_type enum) value - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -int eqdma_cpm5_sw_ctx_conf(void *dev_hndl, uint8_t c2h, uint16_t hw_qid, - struct qdma_descq_sw_ctxt *ctxt, - enum qdma_hw_access_type access_type) -{ - int rv = QDMA_SUCCESS; - - switch (access_type) { - case QDMA_HW_ACCESS_READ: - rv = eqdma_cpm5_sw_context_read(dev_hndl, c2h, hw_qid, - ctxt); - break; - case QDMA_HW_ACCESS_WRITE: - rv = eqdma_cpm5_sw_context_write(dev_hndl, c2h, hw_qid, - ctxt); - break; - case QDMA_HW_ACCESS_CLEAR: - rv = eqdma_cpm5_sw_context_clear(dev_hndl, c2h, hw_qid); - break; - case QDMA_HW_ACCESS_INVALIDATE: - rv = eqdma_cpm5_sw_context_invalidate(dev_hndl, c2h, - hw_qid); - break; - default: - qdma_log_error("%s: access_type(%d) invalid, err:%d\n", - __func__, - access_type, - -QDMA_ERR_INV_PARAM); - rv = -QDMA_ERR_INV_PARAM; - break; - } - - return rv; -} - -/*****************************************************************************/ -/** - * eqdma_cpm5_pfetch_context_write() - create prefetch context and program - * it - * - * @dev_hndl: device handle - * @hw_qid: hardware qid of the queue - * @ctxt: pointer to the prefetch context data strucutre - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -static int eqdma_cpm5_pfetch_context_write(void *dev_hndl, uint16_t hw_qid, - const struct qdma_descq_prefetch_ctxt *ctxt) -{ - uint32_t pfetch_ctxt[EQDMA_CPM5_PFETCH_CONTEXT_NUM_WORDS] = {0}; - enum ind_ctxt_cmd_sel sel = QDMA_CTXT_SEL_PFTCH; - uint32_t sw_crdt_l, sw_crdt_h; - uint16_t num_words_count = 0; - - if (!dev_hndl || !ctxt) { - qdma_log_error("%s: dev_handle or pfetch ctxt NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - sw_crdt_l = - FIELD_GET(QDMA_PFTCH_CTXT_SW_CRDT_GET_L_MASK, ctxt->sw_crdt); - sw_crdt_h = - FIELD_GET(QDMA_PFTCH_CTXT_SW_CRDT_GET_H_MASK, ctxt->sw_crdt); - - qdma_log_debug("%s: sw_crdt_l=%u, sw_crdt_h=%u, hw_qid=%hu\n", - __func__, sw_crdt_l, sw_crdt_h, hw_qid); - - pfetch_ctxt[num_words_count++] = - FIELD_SET(PREFETCH_CTXT_DATA_W0_BYPASS_MASK, ctxt->bypass) | - FIELD_SET(PREFETCH_CTXT_DATA_W0_BUF_SZ_IDX_MASK, - ctxt->bufsz_idx) | - FIELD_SET(PREFETCH_CTXT_DATA_W0_PORT_ID_MASK, ctxt->port_id) | - FIELD_SET(PREFETCH_CTXT_DATA_W0_NUM_PFCH_MASK, - ctxt->num_pftch) | - FIELD_SET(PREFETCH_CTXT_DATA_W0_VAR_DESC_MASK, - ctxt->var_desc) | - FIELD_SET(PREFETCH_CTXT_DATA_W0_ERR_MASK, ctxt->err) | - FIELD_SET(PREFETCH_CTXT_DATA_W0_PFCH_EN_MASK, ctxt->pfch_en) | - FIELD_SET(PREFETCH_CTXT_DATA_W0_PFCH_MASK, ctxt->pfch) | - FIELD_SET(PREFETCH_CTXT_DATA_W0_SW_CRDT_L_MASK, sw_crdt_l); - - qdma_log_debug("%s: bypass=%x, bufsz_idx=%x, port_id=%x\n", - __func__, ctxt->bypass, ctxt->bufsz_idx, ctxt->port_id); - qdma_log_debug("%s: err=%x, pfch_en=%x, pfch=%x, ctxt->valid=%x\n", - __func__, ctxt->err, ctxt->pfch_en, ctxt->pfch, - ctxt->valid); - - pfetch_ctxt[num_words_count++] = - FIELD_SET(PREFETCH_CTXT_DATA_W1_SW_CRDT_H_MASK, sw_crdt_h) | - FIELD_SET(PREFETCH_CTXT_DATA_W1_VALID_MASK, ctxt->valid); - - return eqdma_cpm5_indirect_reg_write(dev_hndl, sel, hw_qid, - pfetch_ctxt, num_words_count); -} - -/*****************************************************************************/ -/** - * eqdma_cpm5_pfetch_context_read() - read prefetch context - * - * @dev_hndl: device handle - * @hw_qid: hardware qid of the queue - * @ctxt: pointer to the output context data - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -static int eqdma_cpm5_pfetch_context_read(void *dev_hndl, uint16_t hw_qid, - struct qdma_descq_prefetch_ctxt *ctxt) -{ - int rv = QDMA_SUCCESS; - uint32_t pfetch_ctxt[EQDMA_CPM5_PFETCH_CONTEXT_NUM_WORDS] = {0}; - enum ind_ctxt_cmd_sel sel = QDMA_CTXT_SEL_PFTCH; - uint32_t sw_crdt_l, sw_crdt_h; - - if (!dev_hndl || !ctxt) { - qdma_log_error("%s: dev_handle or pfetch ctxt NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - rv = eqdma_cpm5_indirect_reg_read(dev_hndl, sel, hw_qid, - EQDMA_CPM5_PFETCH_CONTEXT_NUM_WORDS, pfetch_ctxt); - if (rv < 0) - return rv; - - ctxt->bypass = - FIELD_GET(PREFETCH_CTXT_DATA_W0_BYPASS_MASK, pfetch_ctxt[0]); - ctxt->bufsz_idx = - FIELD_GET(PREFETCH_CTXT_DATA_W0_BUF_SZ_IDX_MASK, - pfetch_ctxt[0]); - ctxt->num_pftch = (uint16_t) FIELD_GET( - PREFETCH_CTXT_DATA_W0_NUM_PFCH_MASK, pfetch_ctxt[0]); - ctxt->port_id = - FIELD_GET(PREFETCH_CTXT_DATA_W0_PORT_ID_MASK, pfetch_ctxt[0]); - ctxt->var_desc = (uint8_t) - FIELD_GET(PREFETCH_CTXT_DATA_W0_VAR_DESC_MASK, - pfetch_ctxt[0]); - ctxt->err = - (uint8_t)(FIELD_GET(PREFETCH_CTXT_DATA_W0_ERR_MASK, - pfetch_ctxt[0])); - ctxt->pfch_en = - (uint8_t)(FIELD_GET(PREFETCH_CTXT_DATA_W0_PFCH_EN_MASK, - pfetch_ctxt[0])); - ctxt->pfch = - (uint8_t)(FIELD_GET(PREFETCH_CTXT_DATA_W0_PFCH_MASK, - pfetch_ctxt[0])); - sw_crdt_l = - FIELD_GET(PREFETCH_CTXT_DATA_W0_SW_CRDT_L_MASK, pfetch_ctxt[0]); - - sw_crdt_h = - FIELD_GET(PREFETCH_CTXT_DATA_W1_SW_CRDT_H_MASK, pfetch_ctxt[1]); - ctxt->valid = - (uint8_t)(FIELD_GET(PREFETCH_CTXT_DATA_W1_VALID_MASK, - pfetch_ctxt[1])); - - ctxt->sw_crdt = - FIELD_SET(QDMA_PFTCH_CTXT_SW_CRDT_GET_L_MASK, sw_crdt_l) | - FIELD_SET(QDMA_PFTCH_CTXT_SW_CRDT_GET_H_MASK, sw_crdt_h); - - qdma_log_debug("%s: sw_crdt_l=%u, sw_crdt_h=%u, hw_qid=%hu\n", - __func__, sw_crdt_l, sw_crdt_h, hw_qid); - qdma_log_debug("%s: bypass=%x, bufsz_idx=%x, port_id=%x\n", - __func__, ctxt->bypass, ctxt->bufsz_idx, ctxt->port_id); - qdma_log_debug("%s: err=%x, pfch_en=%x, pfch=%x, ctxt->valid=%x\n", - __func__, ctxt->err, ctxt->pfch_en, ctxt->pfch, - ctxt->valid); - - return QDMA_SUCCESS; -} - -/*****************************************************************************/ -/** - * eqdma_cpm5_pfetch_context_clear() - clear prefetch context - * - * @dev_hndl: device handle - * @hw_qid: hardware qid of the queue - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -static int eqdma_cpm5_pfetch_context_clear(void *dev_hndl, uint16_t hw_qid) -{ - enum ind_ctxt_cmd_sel sel = QDMA_CTXT_SEL_PFTCH; - - if (!dev_hndl) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", __func__, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - return eqdma_cpm5_indirect_reg_clear(dev_hndl, sel, hw_qid); -} - -/*****************************************************************************/ -/** - * eqdma_cpm5_pfetch_context_invalidate() - invalidate prefetch context - * - * @dev_hndl: device handle - * @hw_qid: hardware qid of the queue - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -static int eqdma_cpm5_pfetch_context_invalidate(void *dev_hndl, - uint16_t hw_qid) -{ - enum ind_ctxt_cmd_sel sel = QDMA_CTXT_SEL_PFTCH; - - if (!dev_hndl) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", __func__, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - return eqdma_cpm5_indirect_reg_invalidate(dev_hndl, sel, hw_qid); -} - -/*****************************************************************************/ -/** - * eqdma_cpm5_pfetch_ctx_conf() - configure prefetch context - * - * @dev_hndl: device handle - * @hw_qid: hardware qid of the queue - * @ctxt: pointer to context data - * @access_type HW access type (qdma_hw_access_type enum) value - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -int eqdma_cpm5_pfetch_ctx_conf(void *dev_hndl, uint16_t hw_qid, - struct qdma_descq_prefetch_ctxt *ctxt, - enum qdma_hw_access_type access_type) -{ - int rv = QDMA_SUCCESS; - - switch (access_type) { - case QDMA_HW_ACCESS_READ: - rv = eqdma_cpm5_pfetch_context_read(dev_hndl, hw_qid, - ctxt); - break; - case QDMA_HW_ACCESS_WRITE: - rv = eqdma_cpm5_pfetch_context_write(dev_hndl, hw_qid, - ctxt); - break; - case QDMA_HW_ACCESS_CLEAR: - rv = eqdma_cpm5_pfetch_context_clear(dev_hndl, hw_qid); - break; - case QDMA_HW_ACCESS_INVALIDATE: - rv = eqdma_cpm5_pfetch_context_invalidate(dev_hndl, - hw_qid); - break; - default: - qdma_log_error("%s: access_type(%d) invalid, err:%d\n", - __func__, - access_type, - -QDMA_ERR_INV_PARAM); - rv = -QDMA_ERR_INV_PARAM; - break; - } - - return rv; -} - -/*****************************************************************************/ -/** - * eqdma_cpm5_cmpt_context_write() - create completion context and program - * it - * - * @dev_hndl: device handle - * @hw_qid: hardware qid of the queue - * @ctxt: pointer to the cmpt context data strucutre - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -static int eqdma_cpm5_cmpt_context_write(void *dev_hndl, uint16_t hw_qid, - const struct qdma_descq_cmpt_ctxt *ctxt) -{ - uint32_t cmpt_ctxt[EQDMA_CPM5_CMPT_CONTEXT_NUM_WORDS] = {0}; - uint16_t num_words_count = 0; - uint32_t baddr4_high_l, baddr4_high_h, - baddr4_low, pidx_l, pidx_h, pasid_l, pasid_h; - enum ind_ctxt_cmd_sel sel = QDMA_CTXT_SEL_CMPT; - - /* Input args check */ - if (!dev_hndl || !ctxt) { - qdma_log_error("%s: dev_handle or cmpt ctxt NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - if (ctxt->trig_mode > QDMA_CMPT_UPDATE_TRIG_MODE_TMR_CNTR) { - qdma_log_error("%s: trig_mode(%d) > (%d) is invalid, err:%d\n", - __func__, - ctxt->trig_mode, - QDMA_CMPT_UPDATE_TRIG_MODE_TMR_CNTR, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - baddr4_high_l = - (uint32_t)FIELD_GET(EQDMA_CPM5_COMPL_CTXT_BADDR_HIGH_L_MASK, - ctxt->bs_addr); - baddr4_high_h = - (uint32_t)FIELD_GET(EQDMA_CPM5_COMPL_CTXT_BADDR_HIGH_H_MASK, - ctxt->bs_addr); - baddr4_low = - (uint32_t)FIELD_GET(EQDMA_CPM5_COMPL_CTXT_BADDR_LOW_MASK, - ctxt->bs_addr); - - pidx_l = FIELD_GET(QDMA_COMPL_CTXT_PIDX_GET_L_MASK, ctxt->pidx); - pidx_h = FIELD_GET(QDMA_COMPL_CTXT_PIDX_GET_H_MASK, ctxt->pidx); - - pasid_l = - FIELD_GET(EQDMA_CPM5_CMPL_CTXT_PASID_GET_L_MASK, - ctxt->pasid); - pasid_h = - FIELD_GET(EQDMA_CPM5_CMPL_CTXT_PASID_GET_H_MASK, - ctxt->pasid); - - cmpt_ctxt[num_words_count++] = - FIELD_SET(CMPL_CTXT_DATA_W0_EN_STAT_DESC_MASK, - ctxt->en_stat_desc) | - FIELD_SET(CMPL_CTXT_DATA_W0_EN_INT_MASK, ctxt->en_int) | - FIELD_SET(CMPL_CTXT_DATA_W0_TRIG_MODE_MASK, ctxt->trig_mode) | - FIELD_SET(CMPL_CTXT_DATA_W0_FNC_ID_MASK, ctxt->fnc_id) | - FIELD_SET(CMPL_CTXT_DATA_W0_CNTER_IX_MASK, - ctxt->counter_idx) | - FIELD_SET(CMPL_CTXT_DATA_W0_TIMER_IX_MASK, ctxt->timer_idx) | - FIELD_SET(CMPL_CTXT_DATA_W0_INT_ST_MASK, ctxt->in_st) | - FIELD_SET(CMPL_CTXT_DATA_W0_COLOR_MASK, ctxt->color) | - FIELD_SET(CMPL_CTXT_DATA_W0_QSIZE_IX_MASK, ctxt->ringsz_idx); - - cmpt_ctxt[num_words_count++] = - FIELD_SET(CMPL_CTXT_DATA_W1_BADDR4_HIGH_L_MASK, baddr4_high_l); - - cmpt_ctxt[num_words_count++] = - FIELD_SET(CMPL_CTXT_DATA_W2_BADDR4_HIGH_H_MASK, baddr4_high_h) | - FIELD_SET(CMPL_CTXT_DATA_W2_DESC_SIZE_MASK, ctxt->desc_sz) | - FIELD_SET(CMPL_CTXT_DATA_W2_PIDX_L_MASK, pidx_l); - - cmpt_ctxt[num_words_count++] = - FIELD_SET(CMPL_CTXT_DATA_W3_PIDX_H_MASK, pidx_h) | - FIELD_SET(CMPL_CTXT_DATA_W3_CIDX_MASK, ctxt->cidx) | - FIELD_SET(CMPL_CTXT_DATA_W3_VALID_MASK, ctxt->valid) | - FIELD_SET(CMPL_CTXT_DATA_W3_ERR_MASK, ctxt->err) | - FIELD_SET(CMPL_CTXT_DATA_W3_USER_TRIG_PEND_MASK, - ctxt->user_trig_pend); - - cmpt_ctxt[num_words_count++] = - FIELD_SET(CMPL_CTXT_DATA_W4_TIMER_RUNNING_MASK, - ctxt->timer_running) | - FIELD_SET(CMPL_CTXT_DATA_W4_FULL_UPD_MASK, ctxt->full_upd) | - FIELD_SET(CMPL_CTXT_DATA_W4_OVF_CHK_DIS_MASK, - ctxt->ovf_chk_dis) | - FIELD_SET(CMPL_CTXT_DATA_W4_AT_MASK, ctxt->at) | - FIELD_SET(CMPL_CTXT_DATA_W4_VEC_MASK, ctxt->vec) | - FIELD_SET(CMPL_CTXT_DATA_W4_INT_AGGR_MASK, ctxt->int_aggr) | - FIELD_SET(CMPL_CTXT_DATA_W4_DIS_INTR_ON_VF_MASK, - ctxt->dis_intr_on_vf) | - FIELD_SET(CMPL_CTXT_DATA_W4_VIO_MASK, ctxt->vio) | - FIELD_SET(CMPL_CTXT_DATA_W4_DIR_C2H_MASK, ctxt->dir_c2h) | - FIELD_SET(CMPL_CTXT_DATA_W4_HOST_ID_MASK, ctxt->host_id) | - FIELD_SET(CMPL_CTXT_DATA_W4_PASID_L_MASK, pasid_l); - - cmpt_ctxt[num_words_count++] = - FIELD_SET(CMPL_CTXT_DATA_W5_PASID_H_MASK, pasid_h) | - FIELD_SET(CMPL_CTXT_DATA_W5_PASID_EN_MASK, - ctxt->pasid_en) | - FIELD_SET(CMPL_CTXT_DATA_W5_BADDR4_LOW_MASK, - baddr4_low) | - FIELD_SET(CMPL_CTXT_DATA_W5_VIO_EOP_MASK, ctxt->vio_eop) | - FIELD_SET(CMPL_CTXT_DATA_W5_SH_CMPT_MASK, ctxt->sh_cmpt); - - return eqdma_cpm5_indirect_reg_write(dev_hndl, sel, hw_qid, - cmpt_ctxt, num_words_count); -} - -/*****************************************************************************/ -/** - * eqdma_cpm5_cmpt_context_read() - read completion context - * - * @dev_hndl: device handle - * @hw_qid: hardware qid of the queue - * @ctxt: pointer to the context data - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -static int eqdma_cpm5_cmpt_context_read(void *dev_hndl, uint16_t hw_qid, - struct qdma_descq_cmpt_ctxt *ctxt) -{ - int rv = QDMA_SUCCESS; - uint32_t cmpt_ctxt[EQDMA_CPM5_CMPT_CONTEXT_NUM_WORDS] = {0}; - enum ind_ctxt_cmd_sel sel = QDMA_CTXT_SEL_CMPT; - uint32_t baddr4_high_l, baddr4_high_h, baddr4_low, - pidx_l, pidx_h, pasid_l, pasid_h; - - if (!dev_hndl || !ctxt) { - qdma_log_error("%s: dev_handle or cmpt ctxt NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - rv = eqdma_cpm5_indirect_reg_read(dev_hndl, sel, hw_qid, - EQDMA_CPM5_CMPT_CONTEXT_NUM_WORDS, cmpt_ctxt); - if (rv < 0) - return rv; - - ctxt->en_stat_desc = - FIELD_GET(CMPL_CTXT_DATA_W0_EN_STAT_DESC_MASK, cmpt_ctxt[0]); - ctxt->en_int = FIELD_GET(CMPL_CTXT_DATA_W0_EN_INT_MASK, cmpt_ctxt[0]); - ctxt->trig_mode = - FIELD_GET(CMPL_CTXT_DATA_W0_TRIG_MODE_MASK, cmpt_ctxt[0]); - ctxt->fnc_id = FIELD_GET(CMPL_CTXT_DATA_W0_FNC_ID_MASK, cmpt_ctxt[0]); - ctxt->counter_idx = - (uint8_t)(FIELD_GET(CMPL_CTXT_DATA_W0_CNTER_IX_MASK, - cmpt_ctxt[0])); - ctxt->timer_idx = - (uint8_t)(FIELD_GET(CMPL_CTXT_DATA_W0_TIMER_IX_MASK, - cmpt_ctxt[0])); - ctxt->in_st = - (uint8_t)(FIELD_GET(CMPL_CTXT_DATA_W0_INT_ST_MASK, - cmpt_ctxt[0])); - ctxt->color = - (uint8_t)(FIELD_GET(CMPL_CTXT_DATA_W0_COLOR_MASK, - cmpt_ctxt[0])); - ctxt->ringsz_idx = - (uint8_t)(FIELD_GET(CMPL_CTXT_DATA_W0_QSIZE_IX_MASK, - cmpt_ctxt[0])); - - baddr4_high_l = FIELD_GET(CMPL_CTXT_DATA_W1_BADDR4_HIGH_L_MASK, - cmpt_ctxt[1]); - - baddr4_high_h = FIELD_GET(CMPL_CTXT_DATA_W2_BADDR4_HIGH_H_MASK, - cmpt_ctxt[2]); - ctxt->desc_sz = - (uint8_t)(FIELD_GET(CMPL_CTXT_DATA_W2_DESC_SIZE_MASK, - cmpt_ctxt[2])); - pidx_l = FIELD_GET(CMPL_CTXT_DATA_W2_PIDX_L_MASK, cmpt_ctxt[2]); - - pidx_h = FIELD_GET(CMPL_CTXT_DATA_W3_PIDX_H_MASK, cmpt_ctxt[3]); - ctxt->cidx = - (uint16_t)(FIELD_GET(CMPL_CTXT_DATA_W3_CIDX_MASK, - cmpt_ctxt[3])); - ctxt->valid = - (uint8_t)(FIELD_GET(CMPL_CTXT_DATA_W3_VALID_MASK, - cmpt_ctxt[3])); - ctxt->err = - (uint8_t)(FIELD_GET(CMPL_CTXT_DATA_W3_ERR_MASK, - cmpt_ctxt[3])); - ctxt->user_trig_pend = (uint8_t) - (FIELD_GET(CMPL_CTXT_DATA_W3_USER_TRIG_PEND_MASK, - cmpt_ctxt[3])); - - ctxt->timer_running = - FIELD_GET(CMPL_CTXT_DATA_W4_TIMER_RUNNING_MASK, cmpt_ctxt[4]); - ctxt->full_upd = - FIELD_GET(CMPL_CTXT_DATA_W4_FULL_UPD_MASK, cmpt_ctxt[4]); - ctxt->ovf_chk_dis = - FIELD_GET(CMPL_CTXT_DATA_W4_OVF_CHK_DIS_MASK, cmpt_ctxt[4]); - ctxt->at = FIELD_GET(CMPL_CTXT_DATA_W4_AT_MASK, cmpt_ctxt[4]); - ctxt->vec = FIELD_GET(CMPL_CTXT_DATA_W4_VEC_MASK, cmpt_ctxt[4]); - ctxt->int_aggr = (uint8_t) - (FIELD_GET(CMPL_CTXT_DATA_W4_INT_AGGR_MASK, cmpt_ctxt[4])); - ctxt->dis_intr_on_vf = (uint8_t) - FIELD_GET(CMPL_CTXT_DATA_W4_DIS_INTR_ON_VF_MASK, - cmpt_ctxt[4]); - ctxt->vio = (uint8_t)FIELD_GET(CMPL_CTXT_DATA_W4_VIO_MASK, - cmpt_ctxt[4]); - ctxt->dir_c2h = (uint8_t)FIELD_GET(CMPL_CTXT_DATA_W4_DIR_C2H_MASK, - cmpt_ctxt[4]); - ctxt->host_id = (uint8_t)FIELD_GET(CMPL_CTXT_DATA_W4_HOST_ID_MASK, - cmpt_ctxt[4]); - pasid_l = FIELD_GET(CMPL_CTXT_DATA_W4_PASID_L_MASK, cmpt_ctxt[4]); - - pasid_h = (uint32_t)FIELD_GET(CMPL_CTXT_DATA_W5_PASID_H_MASK, - cmpt_ctxt[5]); - ctxt->pasid_en = (uint8_t)FIELD_GET(CMPL_CTXT_DATA_W5_PASID_EN_MASK, - cmpt_ctxt[5]); - baddr4_low = (uint8_t)FIELD_GET( - CMPL_CTXT_DATA_W5_BADDR4_LOW_MASK, cmpt_ctxt[5]); - ctxt->vio_eop = (uint8_t)FIELD_GET(CMPL_CTXT_DATA_W5_VIO_EOP_MASK, - cmpt_ctxt[5]); - ctxt->sh_cmpt = (uint8_t)FIELD_GET(CMPL_CTXT_DATA_W5_SH_CMPT_MASK, - cmpt_ctxt[5]); - - ctxt->bs_addr = - FIELD_SET(EQDMA_CPM5_COMPL_CTXT_BADDR_HIGH_L_MASK, - (uint64_t)baddr4_high_l) | - FIELD_SET(EQDMA_CPM5_COMPL_CTXT_BADDR_HIGH_H_MASK, - (uint64_t)baddr4_high_h) | - FIELD_SET(EQDMA_CPM5_COMPL_CTXT_BADDR_LOW_MASK, - (uint64_t)baddr4_low); - - ctxt->pasid = - FIELD_SET(EQDMA_CPM5_CMPL_CTXT_PASID_GET_L_MASK, pasid_l) | - FIELD_SET(EQDMA_CPM5_CMPL_CTXT_PASID_GET_H_MASK, - (uint64_t)pasid_h); - - ctxt->pidx = - FIELD_SET(QDMA_COMPL_CTXT_PIDX_GET_L_MASK, pidx_l) | - FIELD_SET(QDMA_COMPL_CTXT_PIDX_GET_H_MASK, pidx_h); - - return QDMA_SUCCESS; -} - -/*****************************************************************************/ -/** - * eqdma_cpm5_cmpt_context_clear() - clear completion context - * - * @dev_hndl: device handle - * @hw_qid: hardware qid of the queue - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -static int eqdma_cpm5_cmpt_context_clear(void *dev_hndl, uint16_t hw_qid) -{ - enum ind_ctxt_cmd_sel sel = QDMA_CTXT_SEL_CMPT; - - if (!dev_hndl) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", __func__, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - return eqdma_cpm5_indirect_reg_clear(dev_hndl, sel, hw_qid); -} - -/*****************************************************************************/ -/** - * eqdma_cpm5_cmpt_context_invalidate() - invalidate completion context - * - * @dev_hndl: device handle - * @hw_qid: hardware qid of the queue - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -static int eqdma_cpm5_cmpt_context_invalidate(void *dev_hndl, - uint16_t hw_qid) -{ - enum ind_ctxt_cmd_sel sel = QDMA_CTXT_SEL_CMPT; - - if (!dev_hndl) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", __func__, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - return eqdma_cpm5_indirect_reg_invalidate(dev_hndl, sel, hw_qid); -} - -/*****************************************************************************/ -/** - * eqdma_cpm5_cmpt_ctx_conf() - configure completion context - * - * @dev_hndl: device handle - * @hw_qid: hardware qid of the queue - * @ctxt: pointer to context data - * @access_type HW access type (qdma_hw_access_type enum) value - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -int eqdma_cpm5_cmpt_ctx_conf(void *dev_hndl, uint16_t hw_qid, - struct qdma_descq_cmpt_ctxt *ctxt, - enum qdma_hw_access_type access_type) -{ - int rv = QDMA_SUCCESS; - - switch (access_type) { - case QDMA_HW_ACCESS_READ: - rv = eqdma_cpm5_cmpt_context_read(dev_hndl, hw_qid, ctxt); - break; - case QDMA_HW_ACCESS_WRITE: - rv = eqdma_cpm5_cmpt_context_write(dev_hndl, hw_qid, ctxt); - break; - case QDMA_HW_ACCESS_CLEAR: - rv = eqdma_cpm5_cmpt_context_clear(dev_hndl, hw_qid); - break; - case QDMA_HW_ACCESS_INVALIDATE: - rv = eqdma_cpm5_cmpt_context_invalidate(dev_hndl, hw_qid); - break; - default: - qdma_log_error("%s: access_type(%d) invalid, err:%d\n", - __func__, - access_type, - -QDMA_ERR_INV_PARAM); - rv = -QDMA_ERR_INV_PARAM; - break; - } - - return rv; -} - -/*****************************************************************************/ -/** - * eqdma_cpm5_hw_context_read() - read hardware context - * - * @dev_hndl: device handle - * @c2h: is c2h queue - * @hw_qid: hardware qid of the queue - * @ctxt: pointer to the output context data - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -static int eqdma_cpm5_hw_context_read(void *dev_hndl, uint8_t c2h, - uint16_t hw_qid, struct qdma_descq_hw_ctxt *ctxt) -{ - int rv = QDMA_SUCCESS; - uint32_t hw_ctxt[EQDMA_CPM5_HW_CONTEXT_NUM_WORDS] = {0}; - enum ind_ctxt_cmd_sel sel = c2h ? QDMA_CTXT_SEL_HW_C2H : - QDMA_CTXT_SEL_HW_H2C; - - if (!dev_hndl || !ctxt) { - qdma_log_error("%s: dev_handle or hw_ctxt NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - rv = eqdma_cpm5_indirect_reg_read(dev_hndl, sel, hw_qid, - EQDMA_CPM5_HW_CONTEXT_NUM_WORDS, hw_ctxt); - if (rv < 0) - return rv; - - ctxt->cidx = FIELD_GET(HW_IND_CTXT_DATA_W0_CIDX_MASK, hw_ctxt[0]); - ctxt->crd_use = - (uint16_t)(FIELD_GET(HW_IND_CTXT_DATA_W0_CRD_USE_MASK, - hw_ctxt[0])); - - ctxt->dsc_pend = - (uint8_t)(FIELD_GET(HW_IND_CTXT_DATA_W1_DSC_PND_MASK, - hw_ctxt[1])); - ctxt->idl_stp_b = - (uint8_t)(FIELD_GET(HW_IND_CTXT_DATA_W1_IDL_STP_B_MASK, - hw_ctxt[1])); - ctxt->evt_pnd = - (uint8_t)(FIELD_GET(HW_IND_CTXT_DATA_W1_EVT_PND_MASK, - hw_ctxt[1])); - ctxt->fetch_pnd = (uint8_t) - (FIELD_GET(HW_IND_CTXT_DATA_W1_DSC_PND_MASK, hw_ctxt[1])); - - qdma_log_debug("%s: cidx=%hu, crd_use=%hu, dsc_pend=%x\n", - __func__, ctxt->cidx, ctxt->crd_use, ctxt->dsc_pend); - qdma_log_debug("%s: idl_stp_b=%x, evt_pnd=%x, fetch_pnd=%x\n", - __func__, ctxt->idl_stp_b, ctxt->evt_pnd, - ctxt->fetch_pnd); - - return QDMA_SUCCESS; -} - -/*****************************************************************************/ -/** - * eqdma_cpm5_hw_context_clear() - clear hardware context - * - * @dev_hndl: device handle - * @c2h: is c2h queue - * @hw_qid: hardware qid of the queue - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -static int eqdma_cpm5_hw_context_clear(void *dev_hndl, uint8_t c2h, - uint16_t hw_qid) -{ - enum ind_ctxt_cmd_sel sel = c2h ? QDMA_CTXT_SEL_HW_C2H : - QDMA_CTXT_SEL_HW_H2C; - - if (!dev_hndl) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", __func__, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - return eqdma_cpm5_indirect_reg_clear(dev_hndl, sel, hw_qid); -} - -/*****************************************************************************/ -/** - * eqdma_cpm5_hw_context_invalidate() - invalidate hardware context - * - * @dev_hndl: device handle - * @c2h: is c2h queue - * @hw_qid: hardware qid of the queue - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -static int eqdma_cpm5_hw_context_invalidate(void *dev_hndl, uint8_t c2h, - uint16_t hw_qid) -{ - enum ind_ctxt_cmd_sel sel = c2h ? QDMA_CTXT_SEL_HW_C2H : - QDMA_CTXT_SEL_HW_H2C; - - if (!dev_hndl) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", __func__, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - return eqdma_cpm5_indirect_reg_invalidate(dev_hndl, sel, hw_qid); -} - -/*****************************************************************************/ -/** - * eqdma_cpm5_hw_ctx_conf() - configure HW context - * - * @dev_hndl: device handle - * @c2h: is c2h queue - * @hw_qid: hardware qid of the queue - * @ctxt: pointer to context data - * @access_type HW access type (qdma_hw_access_type enum) value - * QDMA_HW_ACCESS_WRITE Not supported - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -int eqdma_cpm5_hw_ctx_conf(void *dev_hndl, uint8_t c2h, uint16_t hw_qid, - struct qdma_descq_hw_ctxt *ctxt, - enum qdma_hw_access_type access_type) -{ - int rv = QDMA_SUCCESS; - - /** ctxt requires only H2C-0 or C2H-1 - * return error for any other values - */ - if (c2h > 1) { - qdma_log_error("%s: c2h(%d) invalid, err:%d\n", - __func__, - c2h, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - switch (access_type) { - case QDMA_HW_ACCESS_READ: - rv = eqdma_cpm5_hw_context_read(dev_hndl, c2h, hw_qid, - ctxt); - break; - case QDMA_HW_ACCESS_CLEAR: - rv = eqdma_cpm5_hw_context_clear(dev_hndl, c2h, hw_qid); - break; - case QDMA_HW_ACCESS_INVALIDATE: - rv = eqdma_cpm5_hw_context_invalidate(dev_hndl, c2h, - hw_qid); - break; - case QDMA_HW_ACCESS_WRITE: - default: - qdma_log_error("%s: access_type=%d is invalid, err:%d\n", - __func__, access_type, - -QDMA_ERR_INV_PARAM); - rv = -QDMA_ERR_INV_PARAM; - break; - } - - return rv; -} - -/*****************************************************************************/ -/** - * eqdma_cpm5_credit_context_read() - read credit context - * - * @dev_hndl: device handle - * @c2h: is c2h queue - * @hw_qid: hardware qid of the queue - * @ctxt: pointer to the context data - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -static int eqdma_cpm5_credit_context_read(void *dev_hndl, uint8_t c2h, - uint16_t hw_qid, - struct qdma_descq_credit_ctxt *ctxt) -{ - int rv = QDMA_SUCCESS; - uint32_t cr_ctxt[EQDMA_CPM5_CR_CONTEXT_NUM_WORDS] = {0}; - enum ind_ctxt_cmd_sel sel = c2h ? QDMA_CTXT_SEL_CR_C2H : - QDMA_CTXT_SEL_CR_H2C; - - if (!dev_hndl || !ctxt) { - qdma_log_error("%s: dev_hndl=%p credit_ctxt=%p, err:%d\n", - __func__, dev_hndl, ctxt, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - rv = eqdma_cpm5_indirect_reg_read(dev_hndl, sel, hw_qid, - EQDMA_CPM5_CR_CONTEXT_NUM_WORDS, cr_ctxt); - if (rv < 0) - return rv; - - ctxt->credit = FIELD_GET(CRED_CTXT_DATA_W0_CREDT_MASK, cr_ctxt[0]); - - qdma_log_debug("%s: credit=%u\n", __func__, ctxt->credit); - - return QDMA_SUCCESS; -} - -/*****************************************************************************/ -/** - * eqdma_cpm5_credit_context_clear() - clear credit context - * - * @dev_hndl: device handle - * @c2h: is c2h queue - * @hw_qid: hardware qid of the queue - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -static int eqdma_cpm5_credit_context_clear(void *dev_hndl, uint8_t c2h, - uint16_t hw_qid) -{ - enum ind_ctxt_cmd_sel sel = c2h ? QDMA_CTXT_SEL_CR_C2H : - QDMA_CTXT_SEL_CR_H2C; - - if (!dev_hndl) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", __func__, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - return eqdma_cpm5_indirect_reg_clear(dev_hndl, sel, hw_qid); -} - -/*****************************************************************************/ -/** - * eqdma_cpm5_credit_context_invalidate() - invalidate credit context - * - * @dev_hndl: device handle - * @c2h: is c2h queue - * @hw_qid: hardware qid of the queue - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -static int eqdma_cpm5_credit_context_invalidate(void *dev_hndl, uint8_t c2h, - uint16_t hw_qid) -{ - enum ind_ctxt_cmd_sel sel = c2h ? QDMA_CTXT_SEL_CR_C2H : - QDMA_CTXT_SEL_CR_H2C; - - if (!dev_hndl) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", __func__, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - return eqdma_cpm5_indirect_reg_invalidate(dev_hndl, sel, hw_qid); -} - -/*****************************************************************************/ -/** - * eqdma_cpm5_credit_ctx_conf() - configure credit context - * - * @dev_hndl: device handle - * @c2h: is c2h queue - * @hw_qid: hardware qid of the queue - * @ctxt: pointer to the context data - * @access_type HW access type (qdma_hw_access_type enum) value - * QDMA_HW_ACCESS_WRITE Not supported - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -int eqdma_cpm5_credit_ctx_conf(void *dev_hndl, uint8_t c2h, - uint16_t hw_qid, struct qdma_descq_credit_ctxt *ctxt, - enum qdma_hw_access_type access_type) -{ - int rv = QDMA_SUCCESS; - - /** ctxt requires only H2C-0 or C2H-1 - * return error for any other values - */ - if (c2h > 1) { - qdma_log_error("%s: c2h(%d) invalid, err:%d\n", - __func__, - c2h, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - switch (access_type) { - case QDMA_HW_ACCESS_READ: - rv = eqdma_cpm5_credit_context_read(dev_hndl, c2h, hw_qid, - ctxt); - break; - case QDMA_HW_ACCESS_CLEAR: - rv = eqdma_cpm5_credit_context_clear(dev_hndl, c2h, - hw_qid); - break; - case QDMA_HW_ACCESS_INVALIDATE: - rv = eqdma_cpm5_credit_context_invalidate(dev_hndl, c2h, - hw_qid); - break; - case QDMA_HW_ACCESS_WRITE: - default: - qdma_log_error("%s: Invalid access type=%d, err:%d\n", - __func__, access_type, - -QDMA_ERR_INV_PARAM); - rv = -QDMA_ERR_INV_PARAM; - break; - } - - return rv; -} - -/*****************************************************************************/ -/** - * eqdma_cpm5_fmap_context_write() - create fmap context and program it - * - * @dev_hndl: device handle - * @func_id: function id of the device - * @config: pointer to the fmap data strucutre - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -static int eqdma_cpm5_fmap_context_write(void *dev_hndl, uint16_t func_id, - const struct qdma_fmap_cfg *config) -{ - uint32_t fmap[EQDMA_CPM5_FMAP_NUM_WORDS] = {0}; - uint16_t num_words_count = 0; - enum ind_ctxt_cmd_sel sel = QDMA_CTXT_SEL_FMAP; - - if (!dev_hndl || !config) { - qdma_log_error("%s: dev_handle=%p fmap=%p NULL, err:%d\n", - __func__, dev_hndl, config, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - qdma_log_debug("%s: func_id=%hu, qbase=%hu, qmax=%hu\n", __func__, - func_id, config->qbase, config->qmax); - fmap[num_words_count++] = - FIELD_SET(EQDMA_CPM5_FMAP_CTXT_W0_QID_MASK, config->qbase); - fmap[num_words_count++] = - FIELD_SET(EQDMA_CPM5_FMAP_CTXT_W1_QID_MAX_MASK, - config->qmax); - - return eqdma_cpm5_indirect_reg_write(dev_hndl, sel, func_id, - fmap, num_words_count); -} - -/*****************************************************************************/ -/** - * eqdma_cpm5_fmap_context_read() - read fmap context - * - * @dev_hndl: device handle - * @func_id: function id of the device - * @config: pointer to the output fmap data - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -static int eqdma_cpm5_fmap_context_read(void *dev_hndl, uint16_t func_id, - struct qdma_fmap_cfg *config) -{ - int rv = QDMA_SUCCESS; - uint32_t fmap[EQDMA_CPM5_FMAP_NUM_WORDS] = {0}; - enum ind_ctxt_cmd_sel sel = QDMA_CTXT_SEL_FMAP; - - if (!dev_hndl || !config) { - qdma_log_error("%s: dev_handle=%p fmap=%p NULL, err:%d\n", - __func__, dev_hndl, config, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - rv = eqdma_cpm5_indirect_reg_read(dev_hndl, sel, func_id, - EQDMA_CPM5_FMAP_NUM_WORDS, fmap); - if (rv < 0) - return rv; - - config->qbase = FIELD_GET(EQDMA_CPM5_FMAP_CTXT_W0_QID_MASK, - fmap[0]); - config->qmax = FIELD_GET(EQDMA_CPM5_FMAP_CTXT_W1_QID_MAX_MASK, - fmap[1]); - - qdma_log_debug("%s: func_id=%hu, qbase=%hu, qmax=%hu\n", __func__, - func_id, config->qbase, config->qmax); - - return QDMA_SUCCESS; -} - -/*****************************************************************************/ -/** - * eqdma_cpm5_fmap_context_clear() - clear fmap context - * - * @dev_hndl: device handle - * @func_id: function id of the device - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -static int eqdma_cpm5_fmap_context_clear(void *dev_hndl, uint16_t func_id) -{ - enum ind_ctxt_cmd_sel sel = QDMA_CTXT_SEL_FMAP; - - if (!dev_hndl) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", __func__, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - qdma_log_debug("%s: func_id=%hu\n", __func__, func_id); - return eqdma_cpm5_indirect_reg_clear(dev_hndl, sel, func_id); -} - -/*****************************************************************************/ -/** - * eqdma_cpm5_fmap_conf() - configure fmap context - * - * @dev_hndl: device handle - * @func_id: function id of the device - * @config: pointer to the fmap data - * @access_type HW access type (qdma_hw_access_type enum) value - * QDMA_HW_ACCESS_INVALIDATE Not supported - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -int eqdma_cpm5_fmap_conf(void *dev_hndl, uint16_t func_id, - struct qdma_fmap_cfg *config, - enum qdma_hw_access_type access_type) -{ - int rv = QDMA_SUCCESS; - - switch (access_type) { - case QDMA_HW_ACCESS_READ: - rv = eqdma_cpm5_fmap_context_read(dev_hndl, - func_id, config); - break; - case QDMA_HW_ACCESS_WRITE: - rv = eqdma_cpm5_fmap_context_write(dev_hndl, - func_id, config); - break; - case QDMA_HW_ACCESS_CLEAR: - rv = eqdma_cpm5_fmap_context_clear(dev_hndl, func_id); - break; - case QDMA_HW_ACCESS_INVALIDATE: - default: - qdma_log_error("%s: access_type(%d) invalid, err:%d\n", - __func__, - access_type, - -QDMA_ERR_INV_PARAM); - rv = -QDMA_ERR_INV_PARAM; - break; - } - - return rv; -} - -/*****************************************************************************/ -/** - * eqdma_cpm5_indirect_intr_context_write() - create indirect interrupt - * context and program it - * - * @dev_hndl: device handle - * @ring_index: indirect interrupt ring index - * @ctxt: pointer to the interrupt context data strucutre - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -static int eqdma_cpm5_indirect_intr_context_write(void *dev_hndl, - uint16_t ring_index, const struct qdma_indirect_intr_ctxt - *ctxt) -{ - uint32_t intr_ctxt[EQDMA_CPM5_IND_INTR_CONTEXT_NUM_WORDS] = {0}; - enum ind_ctxt_cmd_sel sel = QDMA_CTXT_SEL_INT_COAL; - uint32_t baddr_l, baddr_m, baddr_h, pasid_l, pasid_h; - uint16_t num_words_count = 0; - - if (!dev_hndl || !ctxt) { - qdma_log_error("%s: dev_hndl=%p intr_ctxt=%p, err:%d\n", - __func__, dev_hndl, ctxt, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - baddr_l = (uint32_t)FIELD_GET(QDMA_INTR_CTXT_BADDR_GET_L_MASK, - ctxt->baddr_4k); - baddr_m = (uint32_t)FIELD_GET(QDMA_INTR_CTXT_BADDR_GET_M_MASK, - ctxt->baddr_4k); - baddr_h = (uint32_t)FIELD_GET(QDMA_INTR_CTXT_BADDR_GET_H_MASK, - ctxt->baddr_4k); - - pasid_l = - FIELD_GET(EQDMA_CPM5_INTR_CTXT_PASID_GET_L_MASK, - ctxt->pasid); - pasid_h = - FIELD_GET(EQDMA_CPM5_INTR_CTXT_PASID_GET_H_MASK, - ctxt->pasid); - - intr_ctxt[num_words_count++] = - FIELD_SET(INTR_CTXT_DATA_W0_VALID_MASK, ctxt->valid) | - FIELD_SET(INTR_CTXT_DATA_W0_VEC_MASK, ctxt->vec) | - FIELD_SET(INTR_CTXT_DATA_W0_INT_ST_MASK, ctxt->int_st) | - FIELD_SET(INTR_CTXT_DATA_W0_COLOR_MASK, ctxt->color) | - FIELD_SET(INTR_CTXT_DATA_W0_BADDR_4K_L_MASK, baddr_l); - - intr_ctxt[num_words_count++] = - FIELD_SET(INTR_CTXT_DATA_W1_BADDR_4K_M_MASK, baddr_m); - - intr_ctxt[num_words_count++] = - FIELD_SET(INTR_CTXT_DATA_W2_BADDR_4K_H_MASK, baddr_h) | - FIELD_SET(INTR_CTXT_DATA_W2_PAGE_SIZE_MASK, ctxt->page_size) | - FIELD_SET(INTR_CTXT_DATA_W2_PIDX_MASK, ctxt->pidx) | - FIELD_SET(INTR_CTXT_DATA_W2_AT_MASK, ctxt->at) | - FIELD_SET(INTR_CTXT_DATA_W2_HOST_ID_MASK, ctxt->host_id) | - FIELD_SET(INTR_CTXT_DATA_W2_PASID_L_MASK, pasid_l); - - intr_ctxt[num_words_count++] = - FIELD_SET(INTR_CTXT_DATA_W3_PASID_H_MASK, pasid_h) | - FIELD_SET(INTR_CTXT_DATA_W3_PASID_EN_MASK, ctxt->pasid_en) | - FIELD_SET(INTR_CTXT_DATA_W3_FUNC_MASK, ctxt->func_id); - - return eqdma_cpm5_indirect_reg_write(dev_hndl, sel, ring_index, - intr_ctxt, num_words_count); -} - -/*****************************************************************************/ -/** - * eqdma_cpm5_indirect_intr_context_read() - read indirect interrupt - * context - * - * @dev_hndl: device handle - * @ring_index: indirect interrupt ring index - * @ctxt: pointer to the output context data - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -static int eqdma_cpm5_indirect_intr_context_read(void *dev_hndl, - uint16_t ring_index, struct qdma_indirect_intr_ctxt *ctxt) -{ - int rv = QDMA_SUCCESS; - uint32_t intr_ctxt[EQDMA_CPM5_IND_INTR_CONTEXT_NUM_WORDS] = {0}; - enum ind_ctxt_cmd_sel sel = QDMA_CTXT_SEL_INT_COAL; - uint64_t baddr_l, baddr_m, baddr_h, pasid_l, pasid_h; - - if (!dev_hndl || !ctxt) { - qdma_log_error("%s: dev_hndl=%p intr_ctxt=%p, err:%d\n", - __func__, dev_hndl, ctxt, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - rv = eqdma_cpm5_indirect_reg_read(dev_hndl, sel, ring_index, - EQDMA_CPM5_IND_INTR_CONTEXT_NUM_WORDS, intr_ctxt); - if (rv < 0) - return rv; - - ctxt->valid = FIELD_GET(INTR_CTXT_DATA_W0_VALID_MASK, intr_ctxt[0]); - ctxt->vec = FIELD_GET(INTR_CTXT_DATA_W0_VEC_MASK, intr_ctxt[0]); - ctxt->int_st = - (uint8_t)(FIELD_GET(INTR_CTXT_DATA_W0_INT_ST_MASK, - intr_ctxt[0])); - ctxt->color = - (uint8_t)(FIELD_GET(INTR_CTXT_DATA_W0_COLOR_MASK, - intr_ctxt[0])); - baddr_l = FIELD_GET(INTR_CTXT_DATA_W0_BADDR_4K_L_MASK, intr_ctxt[0]); - - baddr_m = FIELD_GET(INTR_CTXT_DATA_W1_BADDR_4K_M_MASK, intr_ctxt[1]); - - baddr_h = FIELD_GET(INTR_CTXT_DATA_W2_BADDR_4K_H_MASK, intr_ctxt[2]); - ctxt->page_size = - FIELD_GET(INTR_CTXT_DATA_W2_PAGE_SIZE_MASK, intr_ctxt[2]); - ctxt->pidx = - (uint16_t)(FIELD_GET(INTR_CTXT_DATA_W2_PIDX_MASK, - intr_ctxt[2])); - ctxt->at = - (uint8_t)(FIELD_GET(INTR_CTXT_DATA_W2_AT_MASK, intr_ctxt[2])); - ctxt->host_id = (uint8_t)(FIELD_GET(INTR_CTXT_DATA_W2_HOST_ID_MASK, - intr_ctxt[2])); - pasid_l = (uint8_t)(FIELD_GET(INTR_CTXT_DATA_W2_PASID_L_MASK, - intr_ctxt[2])); - - pasid_h = FIELD_GET(INTR_CTXT_DATA_W3_PASID_H_MASK, intr_ctxt[3]); - ctxt->pasid_en = (uint8_t)FIELD_GET(INTR_CTXT_DATA_W3_PASID_EN_MASK, - intr_ctxt[3]); - - ctxt->func_id = (uint16_t)FIELD_GET(INTR_CTXT_DATA_W3_FUNC_MASK, - intr_ctxt[3]); - - ctxt->baddr_4k = - FIELD_SET(QDMA_INTR_CTXT_BADDR_GET_L_MASK, baddr_l) | - FIELD_SET(QDMA_INTR_CTXT_BADDR_GET_M_MASK, baddr_m) | - FIELD_SET(QDMA_INTR_CTXT_BADDR_GET_H_MASK, baddr_h); - - ctxt->pasid = - FIELD_SET(EQDMA_CPM5_INTR_CTXT_PASID_GET_L_MASK, pasid_l) | - FIELD_SET(EQDMA_CPM5_INTR_CTXT_PASID_GET_H_MASK, pasid_h); - - return QDMA_SUCCESS; -} - -/*****************************************************************************/ -/** - * eqdma_cpm5_indirect_intr_context_clear() - clear indirect interrupt - * context - * - * @dev_hndl: device handle - * @ring_index: indirect interrupt ring index - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -static int eqdma_cpm5_indirect_intr_context_clear(void *dev_hndl, - uint16_t ring_index) -{ - enum ind_ctxt_cmd_sel sel = QDMA_CTXT_SEL_INT_COAL; - - if (!dev_hndl) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", __func__, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - return eqdma_cpm5_indirect_reg_clear(dev_hndl, sel, ring_index); -} - -/*****************************************************************************/ -/** - * eqdma_cpm5_indirect_intr_context_invalidate() - invalidate indirect - * interrupt context - * - * @dev_hndl: device handle - * @ring_index: indirect interrupt ring index - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -static int eqdma_cpm5_indirect_intr_context_invalidate(void *dev_hndl, - uint16_t ring_index) -{ - enum ind_ctxt_cmd_sel sel = QDMA_CTXT_SEL_INT_COAL; - - if (!dev_hndl) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", __func__, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - return eqdma_cpm5_indirect_reg_invalidate(dev_hndl, sel, - ring_index); -} - -/*****************************************************************************/ -/** - * eqdma_cpm5_indirect_intr_ctx_conf() - configure indirect interrupt - * context - * - * @dev_hndl: device handle - * @ring_index: indirect interrupt ring index - * @ctxt: pointer to context data - * @access_type HW access type (qdma_hw_access_type enum) value - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -int eqdma_cpm5_indirect_intr_ctx_conf(void *dev_hndl, uint16_t ring_index, - struct qdma_indirect_intr_ctxt *ctxt, - enum qdma_hw_access_type access_type) -{ - int rv = QDMA_SUCCESS; - - switch (access_type) { - case QDMA_HW_ACCESS_READ: - rv = eqdma_cpm5_indirect_intr_context_read(dev_hndl, - ring_index, ctxt); - break; - case QDMA_HW_ACCESS_WRITE: - rv = eqdma_cpm5_indirect_intr_context_write(dev_hndl, - ring_index, ctxt); - break; - case QDMA_HW_ACCESS_CLEAR: - rv = eqdma_cpm5_indirect_intr_context_clear(dev_hndl, - ring_index); - break; - case QDMA_HW_ACCESS_INVALIDATE: - rv = eqdma_cpm5_indirect_intr_context_invalidate(dev_hndl, - ring_index); - break; - default: - qdma_log_error("%s: access_type=%d is invalid, err:%d\n", - __func__, access_type, - -QDMA_ERR_INV_PARAM); - rv = -QDMA_ERR_INV_PARAM; - break; - } - - return rv; -} - -/*****************************************************************************/ -/** - * eqdma_cpm5_dump_config_regs() - Function to get qdma config register - * dump in a buffer - * - * @dev_hndl: device handle - * @is_vf: Whether PF or VF - * @buf : pointer to buffer to be filled - * @buflen : Length of the buffer - * - * Return: Length up-till the buffer is filled -success and < 0 - failure - *****************************************************************************/ -int eqdma_cpm5_dump_config_regs(void *dev_hndl, uint8_t is_vf, - char *buf, uint32_t buflen) -{ - uint32_t i = 0, j = 0; - struct xreg_info *reg_info; - uint32_t num_regs = eqdma_cpm5_config_num_regs_get(); - uint32_t len = 0, val = 0; - int rv = QDMA_SUCCESS; - char name[DEBGFS_GEN_NAME_SZ] = ""; - struct qdma_dev_attributes dev_cap; - - if (!dev_hndl) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - if (buflen < eqdma_cpm5_reg_dump_buf_len()) { - qdma_log_error("%s: Buffer too small, err:%d\n", - __func__, -QDMA_ERR_NO_MEM); - return -QDMA_ERR_NO_MEM; - } - - if (is_vf) { - qdma_log_error("%s: Wrong API used for VF, err:%d\n", - __func__, - -QDMA_ERR_HWACC_FEATURE_NOT_SUPPORTED); - return -QDMA_ERR_HWACC_FEATURE_NOT_SUPPORTED; - } - - eqdma_cpm5_get_device_attributes(dev_hndl, &dev_cap); - - reg_info = eqdma_cpm5_config_regs_get(); - - for (i = 0; i < num_regs; i++) { - if ((GET_CAPABILITY_MASK(dev_cap.mm_en, dev_cap.st_en, - dev_cap.mm_cmpt_en, dev_cap.mailbox_en) - & reg_info[i].mode) == 0) - continue; - - /* If Debug Mode not enabled and the current register - * is debug register, skip reading it. - */ - if (dev_cap.debug_mode == 0 && - reg_info[i].is_debug_reg == 1) - continue; - - for (j = 0; j < reg_info[i].repeat; j++) { - rv = QDMA_SNPRINTF_S(name, DEBGFS_GEN_NAME_SZ, - DEBGFS_GEN_NAME_SZ, - "%s", reg_info[i].name); - if ((rv < 0) || (rv > DEBGFS_GEN_NAME_SZ)) { - qdma_log_error( - "%d:%s QDMA_SNPRINTF_S() failed, err:%d\n", - __LINE__, __func__, - rv); - return -QDMA_ERR_NO_MEM; - } - val = qdma_reg_read(dev_hndl, - (reg_info[i].addr + (j * 4))); - rv = dump_reg(buf + len, buflen - len, - (reg_info[i].addr + (j * 4)), - name, val); - if (rv < 0) { - qdma_log_error( - "%s Buff too small, err:%d\n", - __func__, - -QDMA_ERR_NO_MEM); - return -QDMA_ERR_NO_MEM; - } - len += rv; - } - } - - return len; -} - -/*****************************************************************************/ -/** - * qdma_dump_cpm_queue_context() - Function to get qdma queue context dump - * in a buffer - * - * @dev_hndl: device handle - * @st: Queue Mode(ST or MM) - * @q_type: Queue type(H2C/C2H/CMPT) - * @context: Queue Context - * @buf : pointer to buffer to be filled - * @buflen : Length of the buffer - * - * Return: Length up-till the buffer is filled -success and < 0 - failure - *****************************************************************************/ -int eqdma_cpm5_dump_queue_context(void *dev_hndl, - uint8_t st, - enum qdma_dev_q_type q_type, - struct qdma_descq_context *ctxt_data, - char *buf, uint32_t buflen) -{ - int rv = 0; - uint32_t req_buflen = 0; - - if (!dev_hndl) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - - return -QDMA_ERR_INV_PARAM; - } - - if (!ctxt_data) { - qdma_log_error("%s: ctxt_data is NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - - return -QDMA_ERR_INV_PARAM; - } - - if (!buf) { - qdma_log_error("%s: buf is NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - - return -QDMA_ERR_INV_PARAM; - } - - if (q_type >= QDMA_DEV_Q_TYPE_MAX) { - qdma_log_error("%s: invalid q_type, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - - return -QDMA_ERR_INV_PARAM; - } - - rv = eqdma_cpm5_context_buf_len(st, q_type, &req_buflen); - if (rv != QDMA_SUCCESS) - return rv; - - if (buflen < req_buflen) { - qdma_log_error("%s: Too small buffer(%d), reqd(%d), err:%d\n", - __func__, buflen, req_buflen, -QDMA_ERR_NO_MEM); - return -QDMA_ERR_NO_MEM; - } - - rv = dump_eqdma_cpm5_context(ctxt_data, st, q_type, - buf, buflen); - - return rv; -} - -/*****************************************************************************/ -/** - * eqdma_cpm5_dump_intr_context() - Function to get qdma interrupt context - * dump in a buffer - * - * @dev_hndl: device handle - * @intr_ctx: Interrupt Context - * @ring_index: Ring index - * @buf : pointer to buffer to be filled - * @buflen : Length of the buffer - * - * Return: Length up-till the buffer is filled -success and < 0 - failure - *****************************************************************************/ -int eqdma_cpm5_dump_intr_context(void *dev_hndl, - struct qdma_indirect_intr_ctxt *intr_ctx, - int ring_index, - char *buf, uint32_t buflen) -{ - int rv = 0; - uint32_t req_buflen = 0; - - if (!dev_hndl) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - - return -QDMA_ERR_INV_PARAM; - } - if (!intr_ctx) { - qdma_log_error("%s: intr_ctx is NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - if (!buf) { - qdma_log_error("%s: buf is NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - req_buflen = eqdma_cpm5_intr_context_buf_len(); - if (buflen < req_buflen) { - qdma_log_error("%s: Too small buffer(%d), reqd(%d), err:%d\n", - __func__, buflen, req_buflen, -QDMA_ERR_NO_MEM); - return -QDMA_ERR_NO_MEM; - } - - rv = dump_eqdma_cpm5_intr_context(intr_ctx, ring_index, buf, - buflen); - - return rv; -} - -/*****************************************************************************/ -/** - * eqdma_cpm5_read_dump_queue_context() - Function to read and dump the - * queue context in a buffer - * - * @dev_hndl: device handle - * @func_id: function id - * @hw_qid: queue id - * @st: Queue Mode(ST or MM) - * @q_type: Queue type(H2C/C2H/CMPT) - * @buf : pointer to buffer to be filled - * @buflen : Length of the buffer - * - * Return: Length up-till the buffer is filled -success and < 0 - failure - *****************************************************************************/ -int eqdma_cpm5_read_dump_queue_context(void *dev_hndl, - uint16_t func_id, - uint16_t qid_hw, - uint8_t st, - enum qdma_dev_q_type q_type, - char *buf, uint32_t buflen) -{ - int rv = QDMA_SUCCESS; - uint32_t req_buflen = 0; - struct qdma_descq_context context; - - if (!dev_hndl) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - - return -QDMA_ERR_INV_PARAM; - } - - if (!buf) { - qdma_log_error("%s: buf is NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - - return -QDMA_ERR_INV_PARAM; - } - - if (q_type >= QDMA_DEV_Q_TYPE_MAX) { - qdma_log_error("%s: Not supported for q_type, err = %d\n", - __func__, -QDMA_ERR_INV_PARAM); - - return -QDMA_ERR_INV_PARAM; - } - - rv = eqdma_cpm5_context_buf_len(st, q_type, &req_buflen); - if (rv != QDMA_SUCCESS) - return rv; - - if (buflen < req_buflen) { - qdma_log_error("%s: Too small buffer(%d), reqd(%d), err:%d\n", - __func__, buflen, req_buflen, -QDMA_ERR_NO_MEM); - return -QDMA_ERR_NO_MEM; - } - - qdma_memset(&context, 0, sizeof(struct qdma_descq_context)); - - if (q_type != QDMA_DEV_Q_TYPE_CMPT) { - rv = eqdma_cpm5_sw_ctx_conf(dev_hndl, (uint8_t)q_type, - qid_hw, &(context.sw_ctxt), - QDMA_HW_ACCESS_READ); - if (rv < 0) { - qdma_log_error( - "%s: Failed to read sw context, err = %d", - __func__, rv); - return rv; - } - - rv = eqdma_cpm5_hw_ctx_conf(dev_hndl, (uint8_t)q_type, - qid_hw, &(context.hw_ctxt), - QDMA_HW_ACCESS_READ); - if (rv < 0) { - qdma_log_error( - "%s: Failed to read hw context, err = %d", - __func__, rv); - return rv; - } - - rv = eqdma_cpm5_credit_ctx_conf(dev_hndl, (uint8_t)q_type, - qid_hw, &(context.cr_ctxt), - QDMA_HW_ACCESS_READ); - if (rv < 0) { - qdma_log_error( - "%s: Failed to read credit context, err = %d", - __func__, rv); - return rv; - } - - if (st && (q_type == QDMA_DEV_Q_TYPE_C2H)) { - rv = eqdma_cpm5_pfetch_ctx_conf(dev_hndl, - qid_hw, - &(context.pfetch_ctxt), - QDMA_HW_ACCESS_READ); - if (rv < 0) { - qdma_log_error( - "%s: Failed to read pftech context, err = %d", - __func__, rv); - return rv; - } - } - } - - if ((st && (q_type == QDMA_DEV_Q_TYPE_C2H)) || - (!st && (q_type == QDMA_DEV_Q_TYPE_CMPT))) { - rv = eqdma_cpm5_cmpt_ctx_conf(dev_hndl, qid_hw, - &(context.cmpt_ctxt), - QDMA_HW_ACCESS_READ); - if (rv < 0) { - qdma_log_error( - "%s: Failed to read cmpt context, err = %d", - __func__, rv); - return rv; - } - } - - rv = eqdma_cpm5_fmap_conf(dev_hndl, func_id, - &(context.fmap), QDMA_HW_ACCESS_READ); - if (rv < 0) { - qdma_log_error( - "%s: Failed to read fmap context, err = %d", - __func__, rv); - return rv; - } - - rv = dump_eqdma_cpm5_context(&context, st, q_type, - buf, buflen); - - return rv; -} - -/*****************************************************************************/ -/** - * eqdma_cpm5_get_user_bar() - Function to get the AXI Master - * Lite(user bar) number - * - * @dev_hndl: device handle - * @is_vf: Whether PF or VF - * @func_id: function id of the PF - * @user_bar: pointer to hold the AXI Master Lite bar number - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -int eqdma_cpm5_get_user_bar(void *dev_hndl, uint8_t is_vf, - uint16_t func_id, uint8_t *user_bar) -{ - /* TODO: In future, user bar is identified using RR */ - if (!dev_hndl) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - - return -QDMA_ERR_INV_PARAM; - } - UNUSED(func_id); - UNUSED(is_vf); - - *user_bar = 2; - - return QDMA_SUCCESS; -} - -/*****************************************************************************/ -/** - * eqdma_cpm5_hw_ram_sbe_err_process() - Function to dump SBE error - * debug information - * - * @dev_hndl: device handle - * @buf: Bufffer for the debug info to be dumped in - * @buflen: Length of the buffer - * - * Return: void - *****************************************************************************/ -static void eqdma_cpm5_hw_ram_sbe_err_process(void *dev_hndl) -{ - eqdma_cpm5_dump_reg_info(dev_hndl, - EQDMA_CPM5_RAM_SBE_STS_A_ADDR, 1, NULL, 0); - eqdma_cpm5_dump_reg_info(dev_hndl, - EQDMA_CPM5_RAM_SBE_STS_1_A_ADDR, 1, NULL, 0); -} - -/*****************************************************************************/ -/** - * eqdma_cpm5_hw_ram_dbe_err_process() - Function to dump DBE error - * debug information - * - * @dev_hndl: device handle - * @buf: Bufffer for the debug info to be dumped in - * @buflen: Length of the buffer - * - * Return: void - *****************************************************************************/ -static void eqdma_cpm5_hw_ram_dbe_err_process(void *dev_hndl) -{ - eqdma_cpm5_dump_reg_info(dev_hndl, - EQDMA_CPM5_RAM_DBE_STS_A_ADDR, 1, NULL, 0); - eqdma_cpm5_dump_reg_info(dev_hndl, - EQDMA_CPM5_RAM_DBE_STS_1_A_ADDR, 1, NULL, 0); -} - -/*****************************************************************************/ -/** - * eqdma_cpm5_hw_desc_err_process() - Function to dump Descriptor - * Error information - * - * @dev_hndl: device handle - * @buf: Bufffer for the debug info to be dumped in - * @buflen: Length of the buffer - * - * Return: void - *****************************************************************************/ -static void eqdma_cpm5_hw_desc_err_process(void *dev_hndl) -{ - int i = 0; - uint32_t desc_err_reg_list[] = { - EQDMA_CPM5_GLBL_DSC_ERR_STS_ADDR, - EQDMA_CPM5_GLBL_DSC_ERR_LOG0_ADDR, - EQDMA_CPM5_GLBL_DSC_ERR_LOG1_ADDR, - EQDMA_CPM5_GLBL_DSC_DBG_DAT0_ADDR, - EQDMA_CPM5_GLBL_DSC_DBG_DAT1_ADDR, - EQDMA_CPM5_GLBL_DSC_ERR_LOG2_ADDR - }; - int desc_err_num_regs = sizeof(desc_err_reg_list)/sizeof(uint32_t); - - for (i = 0; i < desc_err_num_regs; i++) { - eqdma_cpm5_dump_reg_info(dev_hndl, desc_err_reg_list[i], - 1, NULL, 0); - } -} - -/*****************************************************************************/ -/** - * eqdma_cpm5_hw_trq_err_process() - Function to dump Target Access - * Error information - * - * @dev_hndl: device handle - * @buf: Bufffer for the debug info to be dumped in - * @buflen: Length of the buffer - * - * Return: void - *****************************************************************************/ -static void eqdma_cpm5_hw_trq_err_process(void *dev_hndl) -{ - int i = 0; - uint32_t trq_err_reg_list[] = { - EQDMA_CPM5_GLBL_TRQ_ERR_STS_ADDR, - EQDMA_CPM5_GLBL_TRQ_ERR_LOG_ADDR - }; - int trq_err_reg_num_regs = sizeof(trq_err_reg_list)/sizeof(uint32_t); - - for (i = 0; i < trq_err_reg_num_regs; i++) { - eqdma_cpm5_dump_reg_info(dev_hndl, trq_err_reg_list[i], - 1, NULL, 0); - } -} - -/*****************************************************************************/ -/** - * eqdma_cpm5_hw_err_dump_ctxt_info() - Dump the imp ctxt fields on HW error - * - * @dev_hndl: device handle - * @first_err_qid: First Error QID - * @en_st: ST Mode or MM Mode enabled - * @c2h: C2H or H2C Mode - * - * Return: void - *****************************************************************************/ -static void eqdma_cpm5_hw_err_dump_ctxt_info(void *dev_hndl, - uint32_t first_err_qid_reg, - uint8_t en_st, uint8_t c2h) -{ - uint16_t first_err_qid = 0; - struct qdma_descq_sw_ctxt sw_ctxt; - struct qdma_descq_hw_ctxt hw_ctxt; - struct qdma_descq_cmpt_ctxt cmpt_ctxt; - - first_err_qid = qdma_reg_read(dev_hndl, first_err_qid_reg); - - eqdma_cpm5_sw_context_read(dev_hndl, c2h, first_err_qid, &sw_ctxt); - eqdma_cpm5_hw_context_read(dev_hndl, c2h, first_err_qid, &hw_ctxt); - eqdma_cpm5_fill_sw_ctxt(&sw_ctxt); - eqdma_cpm5_fill_hw_ctxt(&hw_ctxt); - - if (sw_ctxt.pidx != hw_ctxt.cidx) { - qdma_log_info("\n%40s\n", "SW Context:"); - /** SW Context: PIDX ***/ - qdma_log_info("%-47s %#-10x %u\n", - eqdma_cpm5_sw_ctxt_entries[0].name, - eqdma_cpm5_sw_ctxt_entries[0].value, - eqdma_cpm5_sw_ctxt_entries[0].value); - qdma_log_info("\n%40s\n", "HW Context:"); - /*** HW Context: CIDX ***/ - qdma_log_info("%-47s %#-10x %u\n", - eqdma_cpm5_hw_ctxt_entries[0].name, - eqdma_cpm5_hw_ctxt_entries[0].value, - eqdma_cpm5_hw_ctxt_entries[0].value); - } - - if (sw_ctxt.err != 0) { - /*** SW Context: ERR ***/ - qdma_log_info("%-47s %#-10x %u\n", - eqdma_cpm5_sw_ctxt_entries[17].name, - eqdma_cpm5_sw_ctxt_entries[17].value, - eqdma_cpm5_sw_ctxt_entries[17].value); - } - - /*** SW Context: ERR WB SENT***/ - qdma_log_info("%-47s %#-10x %u\n", - eqdma_cpm5_sw_ctxt_entries[18].name, - eqdma_cpm5_sw_ctxt_entries[18].value, - eqdma_cpm5_sw_ctxt_entries[18].value); - - /*** SW Context: IRQ REQ***/ - qdma_log_info("%-47s %#-10x %u\n", - eqdma_cpm5_sw_ctxt_entries[19].name, - eqdma_cpm5_sw_ctxt_entries[19].value, - eqdma_cpm5_sw_ctxt_entries[19].value); - - if (en_st && c2h) { - eqdma_cpm5_cmpt_context_read(dev_hndl, - first_err_qid, &cmpt_ctxt); - eqdma_cpm5_fill_cmpt_ctxt(&cmpt_ctxt); - - qdma_log_info("\n%40s\n", "CMPT Context:"); - - /*** CMPT Context: int_st ***/ - qdma_log_info("%-47s %#-10x %u\n", - eqdma_cpm5_cmpt_ctxt_entries[6].name, - eqdma_cpm5_cmpt_ctxt_entries[6].value, - eqdma_cpm5_cmpt_ctxt_entries[6].value); - - /** CMPT Context: PIDX ***/ - qdma_log_info("%-47s %#-10x %u\n", - eqdma_cpm5_cmpt_ctxt_entries[12].name, - eqdma_cpm5_cmpt_ctxt_entries[12].value, - eqdma_cpm5_cmpt_ctxt_entries[12].value); - /*** CMPT Context: CIDX ***/ - qdma_log_info("%-47s %#-10x %u\n", - eqdma_cpm5_cmpt_ctxt_entries[13].name, - eqdma_cpm5_cmpt_ctxt_entries[13].value, - eqdma_cpm5_cmpt_ctxt_entries[13].value); - - if (cmpt_ctxt.err != 0) { - /*** CMPT Context: ERR ***/ - qdma_log_info("%-47s %#-10x %u\n", - eqdma_cpm5_cmpt_ctxt_entries[15].name, - eqdma_cpm5_cmpt_ctxt_entries[15].value, - eqdma_cpm5_cmpt_ctxt_entries[15].value); - } - } -} - -/*****************************************************************************/ -/** - * eqdma_cpm5_hw_st_h2c_err_process() - Function to dump MM H2C Error - * information - * - * @dev_hndl: device handle - * @buf: Bufffer for the debug info to be dumped in - * @buflen: Length of the buffer - * - * Return: void - *****************************************************************************/ -static void eqdma_cpm5_hw_st_h2c_err_process(void *dev_hndl) -{ - int i = 0; - uint32_t st_h2c_err_reg_list[] = { - EQDMA_CPM5_H2C_ERR_STAT_ADDR, - EQDMA_CPM5_H2C_FIRST_ERR_QID_ADDR, - EQDMA_CPM5_H2C_DBG_REG0_ADDR, - EQDMA_CPM5_H2C_DBG_REG1_ADDR, - EQDMA_CPM5_H2C_DBG_REG2_ADDR, - EQDMA_CPM5_H2C_DBG_REG3_ADDR, - EQDMA_CPM5_H2C_DBG_REG4_ADDR - }; - int st_h2c_err_num_regs = sizeof(st_h2c_err_reg_list)/sizeof(uint32_t); - - for (i = 0; i < st_h2c_err_num_regs; i++) { - eqdma_cpm5_dump_reg_info(dev_hndl, st_h2c_err_reg_list[i], - 1, NULL, 0); - } - - eqdma_cpm5_hw_err_dump_ctxt_info(dev_hndl, - EQDMA_CPM5_H2C_FIRST_ERR_QID_ADDR, 1, 1); -} - - -/*****************************************************************************/ -/** - * eqdma_cpm5_hw_st_c2h_err_process() - Function to dump MM H2C - * Error information - * - * @dev_hndl: device handle - * @buf: Bufffer for the debug info to be dumped in - * @buflen: Length of the buffer - * - * Return: void - *****************************************************************************/ -static void eqdma_cpm5_hw_st_c2h_err_process(void *dev_hndl) -{ - int i = 0; - uint32_t st_c2h_err_reg_list[] = { - EQDMA_CPM5_C2H_ERR_STAT_ADDR, - EQDMA_CPM5_C2H_FATAL_ERR_STAT_ADDR, - EQDMA_CPM5_C2H_FIRST_ERR_QID_ADDR, - EQDMA_CPM5_C2H_STAT_S_AXIS_C2H_ACCEPTED_ADDR, - EQDMA_CPM5_C2H_STAT_S_AXIS_WRB_ACCEPTED_ADDR, - EQDMA_CPM5_C2H_STAT_DESC_RSP_PKT_ACCEPTED_ADDR, - EQDMA_CPM5_C2H_STAT_AXIS_PKG_CMP_ADDR, - EQDMA_CPM5_C2H_STAT_DBG_DMA_ENG_0_ADDR, - EQDMA_CPM5_C2H_STAT_DBG_DMA_ENG_1_ADDR, - EQDMA_CPM5_C2H_STAT_DBG_DMA_ENG_2_ADDR, - EQDMA_CPM5_C2H_STAT_DBG_DMA_ENG_3_ADDR, - EQDMA_CPM5_C2H_STAT_DESC_RSP_DROP_ACCEPTED_ADDR, - EQDMA_CPM5_C2H_STAT_DESC_RSP_ERR_ACCEPTED_ADDR - }; - int st_c2h_err_num_regs = sizeof(st_c2h_err_reg_list)/sizeof(uint32_t); - - for (i = 0; i < st_c2h_err_num_regs; i++) { - eqdma_cpm5_dump_reg_info(dev_hndl, st_c2h_err_reg_list[i], - 1, NULL, 0); - } - - eqdma_cpm5_hw_err_dump_ctxt_info(dev_hndl, - EQDMA_CPM5_C2H_FIRST_ERR_QID_ADDR, 1, 1); -} - -/*****************************************************************************/ -/** - * eqdma_cpm5_mm_c2h0_err_process() - Function to dump MM C2H - * Error information - * - * @dev_hndl: device handle - * - * Return: void - *****************************************************************************/ -static void eqdma_cpm5_mm_c2h0_err_process(void *dev_hndl) -{ - int i = 0; - uint32_t mm_c2h_err_reg_list[] = { - EQDMA_CPM5_C2H_MM_STATUS_ADDR, - EQDMA_CPM5_C2H_MM_CMPL_DESC_CNT_ADDR, - EQDMA_CPM5_C2H_MM_ERR_CODE_ADDR, - EQDMA_CPM5_C2H_MM_ERR_INFO_ADDR, - EQDMA_CPM5_C2H_MM_DBG_ADDR - }; - int mm_c2h_err_num_regs = sizeof(mm_c2h_err_reg_list)/sizeof(uint32_t); - - for (i = 0; i < mm_c2h_err_num_regs; i++) { - eqdma_cpm5_dump_reg_info(dev_hndl, mm_c2h_err_reg_list[i], - 1, NULL, 0); - } - - eqdma_cpm5_hw_err_dump_ctxt_info(dev_hndl, - EQDMA_CPM5_C2H_MM_ERR_INFO_ADDR, 0, 1); -} - -/*****************************************************************************/ -/** - * eqdma_cpm5_mm_h2c0_err_process() - Function to dump MM H2C - * Error information - * - * @dev_hndl: device handle - * - * Return: void - *****************************************************************************/ -static void eqdma_cpm5_mm_h2c0_err_process(void *dev_hndl) -{ - int i = 0; - uint32_t mm_h2c_err_reg_list[] = { - EQDMA_CPM5_H2C_MM_STATUS_ADDR, - EQDMA_CPM5_H2C_MM_CMPL_DESC_CNT_ADDR, - EQDMA_CPM5_H2C_MM_ERR_CODE_ADDR, - EQDMA_CPM5_H2C_MM_ERR_INFO_ADDR, - EQDMA_CPM5_H2C_MM_DBG_ADDR - }; - int mm_h2c_err_num_regs = sizeof(mm_h2c_err_reg_list)/sizeof(uint32_t); - - for (i = 0; i < mm_h2c_err_num_regs; i++) { - eqdma_cpm5_dump_reg_info(dev_hndl, mm_h2c_err_reg_list[i], - 1, NULL, 0); - } - - eqdma_cpm5_hw_err_dump_ctxt_info(dev_hndl, - EQDMA_CPM5_H2C_MM_ERR_INFO_ADDR, 0, 1); -} - -/*****************************************************************************/ -/** - * eqdma_cpm5_hw_get_error_name() - Function to get the error in string - * format - * - * @err_idx: error index - * - * Return: string - success and NULL on failure - *****************************************************************************/ -const char *eqdma_cpm5_hw_get_error_name(uint32_t err_idx) -{ - if (err_idx >= EQDMA_CPM5_ERRS_ALL) { - qdma_log_error("%s: err_idx=%d is invalid, returning NULL\n", - __func__, - (enum eqdma_cpm5_error_idx)err_idx); - return NULL; - } - - return eqdma_cpm5_err_info[(enum - eqdma_cpm5_error_idx)err_idx].err_name; -} - -/*****************************************************************************/ -/** - * eqdma_cpm5_hw_error_process() - Function to find the error that got - * triggered and call the handler qdma_hw_error_handler of that - * particular error. - * - * @dev_hndl: device handle - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -int eqdma_cpm5_hw_error_process(void *dev_hndl) -{ - uint32_t glbl_err_stat = 0, err_stat = 0; - uint32_t bit = 0, i = 0; - int32_t idx = 0; - struct qdma_dev_attributes dev_cap; - uint32_t hw_err_position[ - EQDMA_CPM5_TOTAL_LEAF_ERROR_AGGREGATORS] = { - EQDMA_CPM5_DSC_ERR_POISON, - EQDMA_CPM5_TRQ_ERR_CSR_UNMAPPED, - EQDMA_CPM5_ST_C2H_ERR_MTY_MISMATCH, - EQDMA_CPM5_ST_FATAL_ERR_MTY_MISMATCH, - EQDMA_CPM5_ST_H2C_ERR_ZERO_LEN_DESC, - EQDMA_CPM5_SBE_1_ERR_RC_RRQ_EVEN_RAM, - EQDMA_CPM5_SBE_ERR_MI_H2C0_DAT, - EQDMA_CPM5_DBE_1_ERR_RC_RRQ_EVEN_RAM, - EQDMA_CPM5_DBE_ERR_MI_H2C0_DAT, - EQDMA_CPM5_MM_C2H_WR_SLR_ERR, - EQDMA_CPM5_MM_H2C0_RD_HDR_POISON_ERR - }; - - if (!dev_hndl) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - - eqdma_cpm5_get_device_attributes(dev_hndl, &dev_cap); - - glbl_err_stat = qdma_reg_read(dev_hndl, - EQDMA_CPM5_GLBL_ERR_STAT_ADDR); - - if (!glbl_err_stat) - return QDMA_HW_ERR_NOT_DETECTED; - - - qdma_log_info("%s: Global Err Reg(0x%x) = 0x%x\n", - __func__, EQDMA_CPM5_GLBL_ERR_STAT_ADDR, - glbl_err_stat); - - for (i = 0; i < EQDMA_CPM5_TOTAL_LEAF_ERROR_AGGREGATORS; i++) { - bit = hw_err_position[i]; - - if ((!dev_cap.st_en) && - (bit == EQDMA_CPM5_ST_C2H_ERR_MTY_MISMATCH || - bit == EQDMA_CPM5_ST_FATAL_ERR_MTY_MISMATCH || - bit == EQDMA_CPM5_ST_H2C_ERR_ZERO_LEN_DESC)) - continue; - - err_stat = qdma_reg_read(dev_hndl, - eqdma_cpm5_err_info[bit].stat_reg_addr); - if (err_stat) { - qdma_log_info("addr = 0x%08x val = 0x%08x", - eqdma_cpm5_err_info[bit].stat_reg_addr, - err_stat); - - eqdma_cpm5_err_info[ - bit].eqdma_cpm5_hw_err_process(dev_hndl); - for (idx = bit; idx < all_eqdma_cpm5_hw_errs[i]; - idx++) { - /* call the platform specific handler */ - if (err_stat & - eqdma_cpm5_err_info[idx].leaf_err_mask) - qdma_log_error("%s detected %s\n", - __func__, - eqdma_cpm5_hw_get_error_name(idx)); - } - qdma_reg_write(dev_hndl, - eqdma_cpm5_err_info[bit].stat_reg_addr, - err_stat); - } - - } - - /* Write 1 to the global status register to clear the bits */ - qdma_reg_write(dev_hndl, EQDMA_CPM5_GLBL_ERR_STAT_ADDR, - glbl_err_stat); - - return QDMA_SUCCESS; -} - -/*****************************************************************************/ -/** - * qdma_hw_error_enable() - Function to enable all or a specific error - * - * @dev_hndl: device handle - * @err_idx: error index - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -int eqdma_cpm5_hw_error_enable(void *dev_hndl, uint32_t err_idx) -{ - uint32_t idx = 0, i = 0; - uint32_t reg_val = 0; - struct qdma_dev_attributes dev_cap; - - if (!dev_hndl) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - if (err_idx > EQDMA_CPM5_ERRS_ALL) { - qdma_log_error("%s: err_idx=%d is invalid, err:%d\n", - __func__, - (enum eqdma_cpm5_error_idx)err_idx, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - eqdma_cpm5_get_device_attributes(dev_hndl, &dev_cap); - - if (err_idx == EQDMA_CPM5_ERRS_ALL) { - for (i = 0; i < EQDMA_CPM5_TOTAL_LEAF_ERROR_AGGREGATORS; - i++) { - - idx = all_eqdma_cpm5_hw_errs[i]; - - /* Don't access streaming registers in - * MM only bitstreams - */ - if (!dev_cap.st_en) { - if (idx == EQDMA_CPM5_ST_C2H_ERR_ALL || - idx == EQDMA_CPM5_ST_FATAL_ERR_ALL - || idx == EQDMA_CPM5_ST_H2C_ERR_ALL) - continue; - } - - reg_val = eqdma_cpm5_err_info[idx].leaf_err_mask; - qdma_reg_write(dev_hndl, - eqdma_cpm5_err_info[idx].mask_reg_addr, - reg_val); - - reg_val = qdma_reg_read(dev_hndl, - EQDMA_CPM5_GLBL_ERR_MASK_ADDR); - reg_val |= FIELD_SET( - eqdma_cpm5_err_info[idx].global_err_mask, - 1); - qdma_reg_write(dev_hndl, - EQDMA_CPM5_GLBL_ERR_MASK_ADDR, - reg_val); - } - - } else { - /* Don't access streaming registers in MM only bitstreams - * QDMA_C2H_ERR_MTY_MISMATCH to QDMA_H2C_ERR_ALL are all - * ST errors - */ - if (!dev_cap.st_en) { - if (err_idx >= EQDMA_CPM5_ST_C2H_ERR_MTY_MISMATCH - && err_idx <= - EQDMA_CPM5_ST_H2C_ERR_ALL) - return QDMA_SUCCESS; - } - - reg_val = qdma_reg_read(dev_hndl, - eqdma_cpm5_err_info[err_idx].mask_reg_addr); - reg_val |= - FIELD_SET( - eqdma_cpm5_err_info[err_idx].leaf_err_mask, - 1); - qdma_reg_write(dev_hndl, - eqdma_cpm5_err_info[err_idx].mask_reg_addr, - reg_val); - - reg_val = qdma_reg_read(dev_hndl, - EQDMA_CPM5_GLBL_ERR_MASK_ADDR); - reg_val |= - FIELD_SET - (eqdma_cpm5_err_info[err_idx].global_err_mask, 1); - qdma_reg_write(dev_hndl, EQDMA_CPM5_GLBL_ERR_MASK_ADDR, - reg_val); - } - - return QDMA_SUCCESS; -} - -/*****************************************************************************/ -/** - * eqdma_cpm5_get_device_attributes() - Function to get the qdma device - * attributes - * - * @dev_hndl: device handle - * @dev_info: pointer to hold the device info - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -int eqdma_cpm5_get_device_attributes(void *dev_hndl, - struct qdma_dev_attributes *dev_info) -{ - uint32_t reg_val = 0; - - if (!dev_hndl) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - if (!dev_info) { - qdma_log_error("%s: dev_info is NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - /* number of PFs */ - reg_val = qdma_reg_read(dev_hndl, QDMA_OFFSET_GLBL2_PF_BARLITE_INT); - dev_info->num_pfs = FIELD_GET(QDMA_GLBL2_PF0_BAR_MAP_MASK, reg_val); - - /* Number of Qs */ - reg_val = qdma_reg_read(dev_hndl, - EQDMA_CPM5_GLBL2_CHANNEL_CAP_ADDR); - dev_info->num_qs = - FIELD_GET(GLBL2_CHANNEL_CAP_MULTIQ_MAX_MASK, reg_val); - - /* There are 12 bits assigned in EQDMA_CPM5_GLBL2_CHANNEL_CAP_ADDR - * to represent the num_qs. For CPM5, max queues can be 4096 which needs - * 13 bits(0x1000). Adding a hack in driver to represent 4096 queues - * when HW sets the num_qs to 0xFFF - */ - if (dev_info->num_qs == 0xFFF) - dev_info->num_qs++; - - /* FLR present */ - reg_val = qdma_reg_read(dev_hndl, EQDMA_CPM5_GLBL2_MISC_CAP_ADDR); - dev_info->mailbox_en = FIELD_GET(EQDMA_CPM5_GLBL2_MAILBOX_EN_MASK, - reg_val); - dev_info->flr_present = FIELD_GET(EQDMA_CPM5_GLBL2_FLR_PRESENT_MASK, - reg_val); - dev_info->mm_cmpt_en = 0; - dev_info->debug_mode = FIELD_GET(EQDMA_CPM5_GLBL2_DBG_MODE_EN_MASK, - reg_val); - dev_info->desc_eng_mode = - FIELD_GET(EQDMA_CPM5_GLBL2_DESC_ENG_MODE_MASK, - reg_val); - - /* ST/MM enabled? */ - reg_val = qdma_reg_read(dev_hndl, - EQDMA_CPM5_GLBL2_CHANNEL_MDMA_ADDR); - dev_info->st_en = (FIELD_GET(GLBL2_CHANNEL_MDMA_C2H_ST_MASK, reg_val) - && FIELD_GET(GLBL2_CHANNEL_MDMA_H2C_ST_MASK, reg_val)) ? 1 : 0; - dev_info->mm_en = (FIELD_GET(GLBL2_CHANNEL_MDMA_C2H_ENG_MASK, reg_val) - && FIELD_GET(GLBL2_CHANNEL_MDMA_H2C_ENG_MASK, reg_val)) ? 1 : 0; - - /* num of mm channels */ - /* TODO : Register not yet defined for this. - * Hard coding it to 2 for CPM5 - */ - dev_info->mm_channel_max = 2; - - dev_info->qid2vec_ctx = 0; - dev_info->cmpt_ovf_chk_dis = 1; - dev_info->mailbox_intr = 1; - dev_info->sw_desc_64b = 1; - dev_info->cmpt_desc_64b = 1; - dev_info->dynamic_bar = 1; - dev_info->legacy_intr = 1; - dev_info->cmpt_trig_count_timer = 1; - - return QDMA_SUCCESS; -} - -/*****************************************************************************/ -/** - * eqdma_cpm5_init_ctxt_memory() - function to initialize the context - * memory - * - * @dev_hndl: device handle - * - * Return: returns the platform specific error code - *****************************************************************************/ -int eqdma_cpm5_init_ctxt_memory(void *dev_hndl) -{ -#ifdef ENABLE_INIT_CTXT_MEMORY - uint32_t data[QDMA_REG_IND_CTXT_REG_COUNT]; - uint16_t i = 0; - struct qdma_dev_attributes dev_info; - - if (!dev_hndl) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - qdma_memset(data, 0, sizeof(uint32_t) * QDMA_REG_IND_CTXT_REG_COUNT); - eqdma_cpm5_get_device_attributes(dev_hndl, &dev_info); - - for (; i < dev_info.num_qs; i++) { - int sel = QDMA_CTXT_SEL_SW_C2H; - int rv; - -#ifdef TANDEM_BOOT_SUPPORTED - for (; sel <= QDMA_CTXT_SEL_CR_H2C; sel++) { - rv = eqdma_cpm5_indirect_reg_clear(dev_hndl, - (enum ind_ctxt_cmd_sel)sel, i); - if (rv < 0) - return rv; - } -#else - for (; sel <= QDMA_CTXT_SEL_PFTCH; sel++) { - /** TODO: Check for Tandem boot **/ - /** if the st mode(h2c/c2h) not enabled - * in the design, then skip the PFTCH - * and CMPT context setup - */ - if ((dev_info.st_en == 0) && - ((sel == QDMA_CTXT_SEL_PFTCH) || - (sel == QDMA_CTXT_SEL_CMPT))) { - qdma_log_debug("%s: ST context is skipped:", - __func__); - qdma_log_debug("sel = %d\n", sel); - continue; - } - - rv = eqdma_cpm5_indirect_reg_clear(dev_hndl, - (enum ind_ctxt_cmd_sel)sel, i); - if (rv < 0) - return rv; - } -#endif - } - - /* fmap */ - for (i = 0; i < dev_info.num_pfs; i++) - eqdma_cpm5_indirect_reg_clear(dev_hndl, - QDMA_CTXT_SEL_FMAP, i); - -#else - if (!dev_hndl) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } -#endif - return QDMA_SUCCESS; - -} - -#ifdef TANDEM_BOOT_SUPPORTED -/*****************************************************************************/ -/** - * eqdma_cpm5_init_st_ctxt() - Initialize the ST context - * - * @dev_hndl: device handle - * - * Return: returns the platform specific error code - *****************************************************************************/ -int eqdma_cpm5_init_st_ctxt(void *dev_hndl) -{ - uint32_t data[QDMA_REG_IND_CTXT_REG_COUNT]; - uint16_t i = 0; - struct qdma_dev_attributes dev_info; - - if (!dev_hndl) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - qdma_memset(data, 0, sizeof(uint32_t) * QDMA_REG_IND_CTXT_REG_COUNT); - eqdma_cpm5_get_device_attributes(dev_hndl, &dev_info); - - for (; i < dev_info.num_qs; i++) { - int sel = QDMA_CTXT_SEL_CMPT; - int rv; - - for (; sel <= QDMA_CTXT_SEL_PFTCH; sel++) { - /** if the st mode(h2c/c2h) not enabled - * in the design, then skip the PFTCH - * and CMPT context setup - */ - if ((dev_info.st_en == 0) && - ((sel == QDMA_CTXT_SEL_PFTCH) || - (sel == QDMA_CTXT_SEL_CMPT))) { - qdma_log_debug("%s: ST context is skipped:", - __func__); - qdma_log_debug("sel = %d\n", sel); - continue; - } - - rv = eqdma_cpm5_indirect_reg_clear(dev_hndl, - (enum ind_ctxt_cmd_sel)sel, i); - if (rv < 0) - return rv; - } - } - - return QDMA_SUCCESS; - -} -#endif - -static int get_reg_entry(uint32_t reg_addr, int *reg_entry) -{ - uint32_t i = 0; - struct xreg_info *reg_info; - uint32_t num_regs = eqdma_cpm5_config_num_regs_get(); - - reg_info = eqdma_cpm5_config_regs_get(); - - for (i = 0; (i < num_regs - 1); i++) { - if (reg_info[i].addr == reg_addr) { - *reg_entry = i; - break; - } - } - - if (i >= num_regs - 1) { - qdma_log_error("%s: 0x%08x is missing register list, err:%d\n", - __func__, - reg_addr, - -QDMA_ERR_INV_PARAM); - *reg_entry = -1; - return -QDMA_ERR_INV_PARAM; - } - - return 0; -} - -/*****************************************************************************/ -/** - * eqdma_cpm5_dump_config_reg_list() - Dump the registers - * - * @dev_hndl: device handle - * @total_regs : Max registers to read - * @reg_list : array of reg addr and reg values - * @buf : pointer to buffer to be filled - * @buflen : Length of the buffer - * - * Return: returns the platform specific error code - *****************************************************************************/ -int eqdma_cpm5_dump_config_reg_list(void *dev_hndl, uint32_t total_regs, - struct qdma_reg_data *reg_list, char *buf, uint32_t buflen) -{ - uint32_t j = 0, len = 0; - uint32_t reg_count = 0; - int reg_data_entry; - int rv = 0; - char name[DEBGFS_GEN_NAME_SZ] = ""; - struct xreg_info *reg_info = eqdma_cpm5_config_regs_get(); - struct qdma_dev_attributes dev_cap; - - if (!dev_hndl) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - if (!buf) { - qdma_log_error("%s: buf is NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - eqdma_cpm5_get_device_attributes(dev_hndl, &dev_cap); - - for (reg_count = 0; - (reg_count < total_regs);) { - - /* If Debug Mode not enabled and the current register - * is debug register, skip reading it. - */ - if (dev_cap.debug_mode == 0 && - reg_info[reg_count].is_debug_reg == 1) - continue; - - rv = get_reg_entry(reg_list[reg_count].reg_addr, - ®_data_entry); - if (rv < 0) { - qdma_log_error("%s: register missing in list, err:%d\n", - __func__, - -QDMA_ERR_INV_PARAM); - return rv; - } - - for (j = 0; j < reg_info[reg_data_entry].repeat; j++) { - rv = QDMA_SNPRINTF_S(name, DEBGFS_GEN_NAME_SZ, - DEBGFS_GEN_NAME_SZ, - "%s_%d", - reg_info[reg_data_entry].name, j); - if ((rv < 0) || (rv > DEBGFS_GEN_NAME_SZ)) { - qdma_log_error( - "%d:%s snprintf failed, err:%d\n", - __LINE__, __func__, - rv); - return -QDMA_ERR_NO_MEM; - } - rv = dump_reg(buf + len, buflen - len, - (reg_info[reg_data_entry].addr + (j * 4)), - name, - reg_list[reg_count + j].reg_val); - if (rv < 0) { - qdma_log_error( - "%s Buff too small, err:%d\n", - __func__, - -QDMA_ERR_NO_MEM); - return -QDMA_ERR_NO_MEM; - } - len += rv; - } - reg_count += j; - } - - return len; - -} - - -/*****************************************************************************/ -/** - * qdma_read_reg_list() - read the register values - * - * @dev_hndl: device handle - * @is_vf: Whether PF or VF - * @total_regs : Max registers to read - * @reg_list : array of reg addr and reg values - * - * Return: returns the platform specific error code - *****************************************************************************/ -int eqdma_cpm5_read_reg_list(void *dev_hndl, uint8_t is_vf, - uint16_t reg_rd_group, - uint16_t *total_regs, - struct qdma_reg_data *reg_list) -{ - uint16_t reg_count = 0, i = 0, j = 0; - struct xreg_info *reg_info; - uint32_t num_regs = eqdma_cpm5_config_num_regs_get(); - struct xreg_info *eqdma_cpm5_config_regs = - eqdma_cpm5_config_regs_get(); - struct qdma_dev_attributes dev_cap; - uint32_t reg_start_addr = 0; - int reg_index = 0; - int rv = 0; - - if (!is_vf) { - qdma_log_error("%s: not supported for PF, err:%d\n", - __func__, - -QDMA_ERR_HWACC_FEATURE_NOT_SUPPORTED); - return -QDMA_ERR_HWACC_FEATURE_NOT_SUPPORTED; - } - - if (!dev_hndl) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - if (!reg_list) { - qdma_log_error("%s: reg_list is NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - eqdma_cpm5_get_device_attributes(dev_hndl, &dev_cap); - - switch (reg_rd_group) { - case QDMA_REG_READ_GROUP_1: - reg_start_addr = EQDMA_CPM5_REG_GROUP_1_START_ADDR; - break; - case QDMA_REG_READ_GROUP_2: - reg_start_addr = EQDMA_CPM5_REG_GROUP_2_START_ADDR; - break; - case QDMA_REG_READ_GROUP_3: - reg_start_addr = EQDMA_CPM5_REG_GROUP_3_START_ADDR; - break; - case QDMA_REG_READ_GROUP_4: - reg_start_addr = EQDMA_CPM5_REG_GROUP_4_START_ADDR; - break; - default: - qdma_log_error("%s: Invalid slot received\n", - __func__); - return -QDMA_ERR_INV_PARAM; - } - - rv = get_reg_entry(reg_start_addr, ®_index); - if (rv < 0) { - qdma_log_error("%s: register missing in list, err:%d\n", - __func__, - -QDMA_ERR_INV_PARAM); - return rv; - } - reg_info = &eqdma_cpm5_config_regs[reg_index]; - - for (i = 0, reg_count = 0; - ((i < num_regs - 1 - reg_index) && - (reg_count < QDMA_MAX_REGISTER_DUMP)); i++) { - - if (((GET_CAPABILITY_MASK(dev_cap.mm_en, dev_cap.st_en, - dev_cap.mm_cmpt_en, dev_cap.mailbox_en) - & reg_info[i].mode) == 0) || - (reg_info[i].read_type == QDMA_REG_READ_PF_ONLY)) - continue; - - /* If Debug Mode not enabled and the current register - * is debug register, skip reading it. - */ - if (dev_cap.debug_mode == 0 && - reg_info[i].is_debug_reg == 1) - continue; - - for (j = 0; j < reg_info[i].repeat && - (reg_count < QDMA_MAX_REGISTER_DUMP); - j++) { - reg_list[reg_count].reg_addr = - (reg_info[i].addr + (j * 4)); - reg_list[reg_count].reg_val = - qdma_reg_read(dev_hndl, - reg_list[reg_count].reg_addr); - reg_count++; - } - } - - *total_regs = reg_count; - return rv; -} - -/*****************************************************************************/ -/** - * eqdma_cpm5_write_global_ring_sizes() - function to set the global ring - * size array - * - * @dev_hndl: device handle - * @index: Index from where the values needs to written - * @count: number of entries to be written - * @glbl_rng_sz: pointer to the array having the values to write - * - * (index + count) shall not be more than 16 - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -static int eqdma_cpm5_write_global_ring_sizes(void *dev_hndl, uint8_t index, - uint8_t count, const uint32_t *glbl_rng_sz) -{ - if (!dev_hndl || !glbl_rng_sz || !count) { - qdma_log_error("%s: dev_hndl=%p glbl_rng_sz=%p, err:%d\n", - __func__, dev_hndl, glbl_rng_sz, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - if ((index + count) > QDMA_NUM_RING_SIZES) { - qdma_log_error("%s: index=%u count=%u > %d, err:%d\n", - __func__, index, count, - QDMA_NUM_RING_SIZES, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - qdma_write_csr_values(dev_hndl, EQDMA_CPM5_GLBL_RNG_SZ_1_ADDR, - index, count, - glbl_rng_sz); - - return QDMA_SUCCESS; -} - -/*****************************************************************************/ -/** - * eqdma_cpm5_read_global_ring_sizes() - function to get the global rng_sz - * array - * - * @dev_hndl: device handle - * @index: Index from where the values needs to read - * @count: number of entries to be read - * @glbl_rng_sz: pointer to array to hold the values read - * - * (index + count) shall not be more than 16 - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -static int eqdma_cpm5_read_global_ring_sizes(void *dev_hndl, uint8_t index, - uint8_t count, uint32_t *glbl_rng_sz) -{ - if (!dev_hndl || !glbl_rng_sz || !count) { - qdma_log_error("%s: dev_hndl=%p glbl_rng_sz=%p, err:%d\n", - __func__, dev_hndl, glbl_rng_sz, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - if ((index + count) > QDMA_NUM_RING_SIZES) { - qdma_log_error("%s: index=%u count=%u > %d, err:%d\n", - __func__, index, count, - QDMA_NUM_C2H_BUFFER_SIZES, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - qdma_read_csr_values(dev_hndl, EQDMA_CPM5_GLBL_RNG_SZ_1_ADDR, - index, count, - glbl_rng_sz); - - return QDMA_SUCCESS; -} - -/*****************************************************************************/ -/** - * eqdma_cpm5_write_global_timer_count() - function to set the timer values - * - * @dev_hndl: device handle - * @glbl_tmr_cnt: pointer to the array having the values to write - * @index: Index from where the values needs to written - * @count: number of entries to be written - * - * (index + count) shall not be more than 16 - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -static int eqdma_cpm5_write_global_timer_count(void *dev_hndl, uint8_t - index, uint8_t count, const uint32_t *glbl_tmr_cnt) -{ - struct qdma_dev_attributes dev_cap; - - if (!dev_hndl || !glbl_tmr_cnt || !count) { - qdma_log_error("%s: dev_hndl=%p glbl_tmr_cnt=%p, err:%d\n", - __func__, dev_hndl, glbl_tmr_cnt, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - if ((index + count) > QDMA_NUM_C2H_TIMERS) { - qdma_log_error("%s: index=%u count=%u > %d, err:%d\n", - __func__, index, count, - QDMA_NUM_C2H_TIMERS, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - eqdma_cpm5_get_device_attributes(dev_hndl, &dev_cap); - - if (dev_cap.st_en || dev_cap.mm_cmpt_en) - qdma_write_csr_values(dev_hndl, - EQDMA_CPM5_C2H_TIMER_CNT_ADDR, - index, count, glbl_tmr_cnt); - else { - qdma_log_error("%s: ST or MM cmpt not supported, err:%d\n", - __func__, - -QDMA_ERR_HWACC_FEATURE_NOT_SUPPORTED); - return -QDMA_ERR_HWACC_FEATURE_NOT_SUPPORTED; - } - - return QDMA_SUCCESS; -} - -/*****************************************************************************/ -/** - * eqdma_cpm5_read_global_timer_count() - function to get the timer values - * - * @dev_hndl: device handle - * @index: Index from where the values needs to read - * @count: number of entries to be read - * @glbl_tmr_cnt: pointer to array to hold the values read - * - * (index + count) shall not be more than 16 - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -static int eqdma_cpm5_read_global_timer_count(void *dev_hndl, - uint8_t index, uint8_t count, uint32_t *glbl_tmr_cnt) -{ - struct qdma_dev_attributes dev_cap; - - if (!dev_hndl || !glbl_tmr_cnt || !count) { - qdma_log_error("%s: dev_hndl=%p glbl_tmr_cnt=%p, err:%d\n", - __func__, dev_hndl, glbl_tmr_cnt, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - if ((index + count) > QDMA_NUM_C2H_TIMERS) { - qdma_log_error("%s: index=%u count=%u > %d, err:%d\n", - __func__, index, count, - QDMA_NUM_C2H_TIMERS, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - eqdma_cpm5_get_device_attributes(dev_hndl, &dev_cap); - - if (dev_cap.st_en || dev_cap.mm_cmpt_en) - qdma_read_csr_values(dev_hndl, - EQDMA_CPM5_C2H_TIMER_CNT_ADDR, index, - count, glbl_tmr_cnt); - else { - qdma_log_error("%s: ST or MM cmpt not supported, err:%d\n", - __func__, - -QDMA_ERR_HWACC_FEATURE_NOT_SUPPORTED); - return -QDMA_ERR_HWACC_FEATURE_NOT_SUPPORTED; - } - - return QDMA_SUCCESS; -} - -/*****************************************************************************/ -/** - * eqdma_cpm5_write_global_counter_threshold() - function to set the - * counter threshold values - * - * @dev_hndl: device handle - * @index: Index from where the values needs to written - * @count: number of entries to be written - * @glbl_cnt_th: pointer to the array having the values to write - * - * (index + count) shall not be more than 16 - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -static int eqdma_cpm5_write_global_counter_threshold(void *dev_hndl, - uint8_t index, uint8_t count, const uint32_t *glbl_cnt_th) -{ - struct qdma_dev_attributes dev_cap; - - if (!dev_hndl || !glbl_cnt_th || !count) { - qdma_log_error("%s: dev_hndl=%p glbl_cnt_th=%p, err:%d\n", - __func__, dev_hndl, glbl_cnt_th, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - if ((index + count) > QDMA_NUM_C2H_COUNTERS) { - qdma_log_error("%s: index=%u count=%u > %d, err:%d\n", - __func__, index, count, - QDMA_NUM_C2H_BUFFER_SIZES, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - eqdma_cpm5_get_device_attributes(dev_hndl, &dev_cap); - - if (dev_cap.st_en || dev_cap.mm_cmpt_en) - qdma_write_csr_values(dev_hndl, EQDMA_CPM5_C2H_CNT_TH_ADDR, - index, - count, glbl_cnt_th); - else { - qdma_log_error("%s: ST or MM cmpt not supported, err:%d\n", - __func__, - -QDMA_ERR_HWACC_FEATURE_NOT_SUPPORTED); - return -QDMA_ERR_HWACC_FEATURE_NOT_SUPPORTED; - } - - return QDMA_SUCCESS; -} - -/*****************************************************************************/ -/** - * eqdma_cpm5_read_global_counter_threshold() - function to get the counter - * threshold - * values - * - * @dev_hndl: device handle - * @index: Index from where the values needs to read - * @count: number of entries to be read - * @glbl_cnt_th: pointer to array to hold the values read - * - * (index + count) shall not be more than 16 - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -static int eqdma_cpm5_read_global_counter_threshold(void *dev_hndl, uint8_t - index, - uint8_t count, uint32_t *glbl_cnt_th) -{ - struct qdma_dev_attributes dev_cap; - - if (!dev_hndl || !glbl_cnt_th || !count) { - qdma_log_error("%s: dev_hndl=%p glbl_cnt_th=%p, err:%d\n", - __func__, dev_hndl, glbl_cnt_th, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - if ((index + count) > QDMA_NUM_C2H_COUNTERS) { - qdma_log_error("%s: index=%u count=%u > %d, err:%d\n", - __func__, index, count, - QDMA_NUM_C2H_COUNTERS, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - eqdma_cpm5_get_device_attributes(dev_hndl, &dev_cap); - - if (dev_cap.st_en || dev_cap.mm_cmpt_en) - qdma_read_csr_values(dev_hndl, EQDMA_CPM5_C2H_CNT_TH_ADDR, - index, count, glbl_cnt_th); - else { - qdma_log_error("%s: ST or MM cmpt not supported, err:%d\n", - __func__, -QDMA_ERR_HWACC_FEATURE_NOT_SUPPORTED); - return -QDMA_ERR_HWACC_FEATURE_NOT_SUPPORTED; - } - - return QDMA_SUCCESS; -} - -/*****************************************************************************/ -/** - * eqdma_cpm5_write_global_buffer_sizes() - function to set the buffer - * sizes - * - * @dev_hndl: device handle - * @index: Index from where the values needs to written - * @count: number of entries to be written - * @glbl_buf_sz: pointer to the array having the values to write - * - * (index + count) shall not be more than 16 - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -static int eqdma_cpm5_write_global_buffer_sizes(void *dev_hndl, uint8_t - index, - uint8_t count, const uint32_t *glbl_buf_sz) -{ - struct qdma_dev_attributes dev_cap; - - if (!dev_hndl || !glbl_buf_sz || !count) { - qdma_log_error("%s: dev_hndl=%p glbl_buf_sz=%p, err:%d\n", - __func__, dev_hndl, glbl_buf_sz, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - if ((index + count) > QDMA_NUM_C2H_BUFFER_SIZES) { - qdma_log_error("%s: index=%u count=%u > %d, err:%d\n", - __func__, index, count, - QDMA_NUM_C2H_BUFFER_SIZES, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - eqdma_cpm5_get_device_attributes(dev_hndl, &dev_cap); - - if (dev_cap.st_en) - qdma_write_csr_values(dev_hndl, EQDMA_CPM5_C2H_BUF_SZ_ADDR, - index, - count, glbl_buf_sz); - else { - qdma_log_error("%s: ST not supported, err:%d\n", - __func__, - -QDMA_ERR_HWACC_FEATURE_NOT_SUPPORTED); - return -QDMA_ERR_HWACC_FEATURE_NOT_SUPPORTED; - } - - return QDMA_SUCCESS; -} - -/*****************************************************************************/ -/** - * eqdma_cpm5_read_global_buffer_sizes() - function to get the buffer sizes - * - * @dev_hndl: device handle - * @index: Index from where the values needs to read - * @count: number of entries to be read - * @glbl_buf_sz: pointer to array to hold the values read - * - * (index + count) shall not be more than 16 - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -static int eqdma_cpm5_read_global_buffer_sizes(void *dev_hndl, uint8_t - index, uint8_t count, uint32_t *glbl_buf_sz) -{ - struct qdma_dev_attributes dev_cap; - - if (!dev_hndl || !glbl_buf_sz || !count) { - qdma_log_error("%s: dev_hndl=%p glbl_buf_sz=%p, err:%d\n", - __func__, dev_hndl, glbl_buf_sz, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - if ((index + count) > QDMA_NUM_C2H_BUFFER_SIZES) { - qdma_log_error("%s: index=%u count=%u > %d, err:%d\n", - __func__, index, count, - QDMA_NUM_C2H_BUFFER_SIZES, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - eqdma_cpm5_get_device_attributes(dev_hndl, &dev_cap); - - if (dev_cap.st_en) - qdma_read_csr_values(dev_hndl, EQDMA_CPM5_C2H_BUF_SZ_ADDR, - index, - count, glbl_buf_sz); - else { - qdma_log_error("%s: ST is not supported, err:%d\n", - __func__, - -QDMA_ERR_HWACC_FEATURE_NOT_SUPPORTED); - return -QDMA_ERR_HWACC_FEATURE_NOT_SUPPORTED; - } - - return QDMA_SUCCESS; -} - -/*****************************************************************************/ -/** - * eqdma_cpm5_global_csr_conf() - function to configure global csr - * - * @dev_hndl: device handle - * @index: Index from where the values needs to read - * @count: number of entries to be read - * @csr_val: uint32_t pointer to csr value - * @csr_type: Type of the CSR (qdma_global_csr_type enum) to configure - * @access_type HW access type (qdma_hw_access_type enum) value - * QDMA_HW_ACCESS_CLEAR - Not supported - * QDMA_HW_ACCESS_INVALIDATE - Not supported - * - * (index + count) shall not be more than 16 - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -int eqdma_cpm5_global_csr_conf(void *dev_hndl, uint8_t index, - uint8_t count, - uint32_t *csr_val, - enum qdma_global_csr_type csr_type, - enum qdma_hw_access_type access_type) -{ - int rv = QDMA_SUCCESS; - - switch (csr_type) { - case QDMA_CSR_RING_SZ: - switch (access_type) { - case QDMA_HW_ACCESS_READ: - rv = eqdma_cpm5_read_global_ring_sizes( - dev_hndl, - index, - count, - csr_val); - break; - case QDMA_HW_ACCESS_WRITE: - rv = eqdma_cpm5_write_global_ring_sizes( - dev_hndl, - index, - count, - csr_val); - break; - default: - qdma_log_error("%s: access_type(%d) invalid, err:%d\n", - __func__, - access_type, - -QDMA_ERR_INV_PARAM); - rv = -QDMA_ERR_INV_PARAM; - break; - } - break; - case QDMA_CSR_TIMER_CNT: - switch (access_type) { - case QDMA_HW_ACCESS_READ: - rv = eqdma_cpm5_read_global_timer_count( - dev_hndl, - index, - count, - csr_val); - break; - case QDMA_HW_ACCESS_WRITE: - rv = eqdma_cpm5_write_global_timer_count( - dev_hndl, - index, - count, - csr_val); - break; - default: - qdma_log_error("%s: access_type(%d) invalid, err:%d\n", - __func__, - access_type, - -QDMA_ERR_INV_PARAM); - rv = -QDMA_ERR_INV_PARAM; - break; - } - break; - case QDMA_CSR_CNT_TH: - switch (access_type) { - case QDMA_HW_ACCESS_READ: - rv = - eqdma_cpm5_read_global_counter_threshold( - dev_hndl, - index, - count, - csr_val); - break; - case QDMA_HW_ACCESS_WRITE: - rv = - eqdma_cpm5_write_global_counter_threshold( - dev_hndl, - index, - count, - csr_val); - break; - default: - qdma_log_error("%s: access_type(%d) invalid, err:%d\n", - __func__, - access_type, - -QDMA_ERR_INV_PARAM); - rv = -QDMA_ERR_INV_PARAM; - break; - } - break; - case QDMA_CSR_BUF_SZ: - switch (access_type) { - case QDMA_HW_ACCESS_READ: - rv = - eqdma_cpm5_read_global_buffer_sizes(dev_hndl, - index, - count, - csr_val); - break; - case QDMA_HW_ACCESS_WRITE: - rv = - eqdma_cpm5_write_global_buffer_sizes(dev_hndl, - index, - count, - csr_val); - break; - default: - qdma_log_error("%s: access_type(%d) invalid, err:%d\n", - __func__, - access_type, - -QDMA_ERR_INV_PARAM); - rv = -QDMA_ERR_INV_PARAM; - break; - } - break; - default: - qdma_log_error("%s: csr_type(%d) invalid, err:%d\n", - __func__, - csr_type, - -QDMA_ERR_INV_PARAM); - rv = -QDMA_ERR_INV_PARAM; - break; - } - - return rv; -} - -/*****************************************************************************/ -/** - * eqdma_cpm5_global_writeback_interval_write() - function to set - * the writeback interval - * - * @dev_hndl device handle - * @wb_int: Writeback Interval - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -static int eqdma_cpm5_global_writeback_interval_write(void *dev_hndl, - enum qdma_wrb_interval wb_int) -{ - uint32_t reg_val; - struct qdma_dev_attributes dev_cap; - - if (!dev_hndl) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", __func__, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - if (wb_int >= QDMA_NUM_WRB_INTERVALS) { - qdma_log_error("%s: wb_int=%d is invalid, err:%d\n", - __func__, wb_int, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - eqdma_cpm5_get_device_attributes(dev_hndl, &dev_cap); - - if (dev_cap.st_en || dev_cap.mm_cmpt_en) { - reg_val = qdma_reg_read(dev_hndl, - EQDMA_CPM5_GLBL_DSC_CFG_ADDR); - reg_val |= FIELD_SET(GLBL_DSC_CFG_WB_ACC_INT_MASK, wb_int); - qdma_reg_write(dev_hndl, EQDMA_CPM5_GLBL_DSC_CFG_ADDR, - reg_val); - } else { - qdma_log_error("%s: ST or MM cmpt not supported, err:%d\n", - __func__, -QDMA_ERR_HWACC_FEATURE_NOT_SUPPORTED); - return -QDMA_ERR_HWACC_FEATURE_NOT_SUPPORTED; - } - - return QDMA_SUCCESS; -} - -/*****************************************************************************/ -/** - * eqdma_cpm5_global_writeback_interval_read() - function to get the - * writeback - * interval - * - * @dev_hndl: device handle - * @wb_int: pointer to the data to hold Writeback Interval - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -static int eqdma_cpm5_global_writeback_interval_read(void *dev_hndl, - enum qdma_wrb_interval *wb_int) -{ - uint32_t reg_val; - struct qdma_dev_attributes dev_cap; - - if (!dev_hndl) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", __func__, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - if (!wb_int) { - qdma_log_error("%s: wb_int is NULL, err:%d\n", __func__, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - eqdma_cpm5_get_device_attributes(dev_hndl, &dev_cap); - - if (dev_cap.st_en || dev_cap.mm_cmpt_en) { - reg_val = qdma_reg_read(dev_hndl, - EQDMA_CPM5_GLBL_DSC_CFG_ADDR); - *wb_int = (enum qdma_wrb_interval)FIELD_GET( - GLBL_DSC_CFG_WB_ACC_INT_MASK, reg_val); - } else { - qdma_log_error("%s: ST or MM cmpt not supported, err:%d\n", - __func__, -QDMA_ERR_HWACC_FEATURE_NOT_SUPPORTED); - return -QDMA_ERR_HWACC_FEATURE_NOT_SUPPORTED; - } - - return QDMA_SUCCESS; -} - -/*****************************************************************************/ -/** - * eqdma_cpm5_global_writeback_interval_conf() - function to configure - * the writeback interval - * - * @dev_hndl: device handle - * @wb_int: pointer to the data to hold Writeback Interval - * @access_type HW access type (qdma_hw_access_type enum) value - * QDMA_HW_ACCESS_CLEAR - Not supported - * QDMA_HW_ACCESS_INVALIDATE - Not supported - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -int eqdma_cpm5_global_writeback_interval_conf(void *dev_hndl, - enum qdma_wrb_interval *wb_int, - enum qdma_hw_access_type access_type) -{ - int rv = QDMA_SUCCESS; - - switch (access_type) { - case QDMA_HW_ACCESS_READ: - rv = eqdma_cpm5_global_writeback_interval_read(dev_hndl, - wb_int); - break; - case QDMA_HW_ACCESS_WRITE: - rv = eqdma_cpm5_global_writeback_interval_write(dev_hndl, - *wb_int); - break; - case QDMA_HW_ACCESS_CLEAR: - case QDMA_HW_ACCESS_INVALIDATE: - default: - qdma_log_error("%s: access_type(%d) invalid, err:%d\n", - __func__, - access_type, - -QDMA_ERR_INV_PARAM); - rv = -QDMA_ERR_INV_PARAM; - break; - } - - return rv; -} - - -/*****************************************************************************/ -/** - * eqdma_cpm5_mm_channel_conf() - Function to enable/disable the MM channel - * - * @dev_hndl: device handle - * @channel: MM channel number - * @is_c2h: Queue direction. Set 1 for C2H and 0 for H2C - * @enable: Enable or disable MM channel - * - * Presently, we have only 1 MM channel - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -int eqdma_cpm5_mm_channel_conf(void *dev_hndl, uint8_t channel, - uint8_t is_c2h, uint8_t enable) -{ - uint32_t reg_addr = (is_c2h) ? EQDMA_CPM5_C2H_MM_CTL_ADDR : - EQDMA_CPM5_H2C_MM_CTL_ADDR; - struct qdma_dev_attributes dev_cap; - - if (!dev_hndl) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - eqdma_cpm5_get_device_attributes(dev_hndl, &dev_cap); - - if (dev_cap.mm_en) - qdma_reg_write(dev_hndl, - reg_addr + (channel * QDMA_MM_CONTROL_STEP), - enable); - - - return QDMA_SUCCESS; -} - -int eqdma_cpm5_dump_reg_info(void *dev_hndl, uint32_t reg_addr, - uint32_t num_regs, char *buf, uint32_t buflen) -{ - uint32_t total_num_regs = eqdma_cpm5_config_num_regs_get(); - struct xreg_info *config_regs = eqdma_cpm5_config_regs_get(); - struct qdma_dev_attributes dev_cap; - const char *bitfield_name; - uint32_t i = 0, num_regs_idx = 0, k = 0, j = 0, - bitfield = 0, lsb = 0, msb = 31; - int rv = 0; - uint32_t reg_val; - uint32_t data_len = 0; - - if (!dev_hndl) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - eqdma_cpm5_get_device_attributes(dev_hndl, &dev_cap); - - for (i = 0; i < total_num_regs; i++) { - if (reg_addr == config_regs[i].addr) { - j = i; - break; - } - } - - if (i == total_num_regs) { - qdma_log_error("%s: Register not found err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - if (buf) - QDMA_SNPRINTF_S(buf, buflen, - DEBGFS_LINE_SZ, - "Register not found 0x%x\n", reg_addr); - - return -QDMA_ERR_INV_PARAM; - } - - num_regs_idx = (j + num_regs < total_num_regs) ? - (j + num_regs) : total_num_regs; - - for (; j < num_regs_idx ; j++) { - reg_val = qdma_reg_read(dev_hndl, - config_regs[j].addr); - - if (buf) { - rv = QDMA_SNPRINTF_S(buf, buflen, - DEBGFS_LINE_SZ, - "\n%-40s 0x%-7x %-#10x %-10d\n", - config_regs[j].name, - config_regs[j].addr, - reg_val, reg_val); - if ((rv < 0) || (rv > DEBGFS_LINE_SZ)) { - qdma_log_error( - "%s: Insufficient buffer, err:%d\n", - __func__, -QDMA_ERR_NO_MEM); - return -QDMA_ERR_NO_MEM; - } - buf += rv; - data_len += rv; - buflen -= rv; - } else - qdma_log_info("%-40s 0x%-7x %-#10x %-10d\n", - config_regs[j].name, - config_regs[j].addr, - reg_val, reg_val); - - - for (k = 0; - k < config_regs[j].num_bitfields; k++) { - /* If Debug Mode not enabled and the current register - * is debug register, skip reading it. - */ - if (dev_cap.debug_mode == 0 && - config_regs[j].is_debug_reg == 1) - continue; - - bitfield = - config_regs[j].bitfields[k].field_mask; - bitfield_name = - config_regs[i].bitfields[k].field_name; - lsb = 0; - msb = 31; - - while (!(BIT(lsb) & bitfield)) - lsb++; - - while (!(BIT(msb) & bitfield)) - msb--; - - if (msb != lsb) { - if (buf) { - rv = QDMA_SNPRINTF_S(buf, buflen, - DEBGFS_LINE_SZ, - "%-40s [%2u,%2u] %#-10x\n", - bitfield_name, - msb, lsb, - (reg_val & bitfield) >> - lsb); - if ((rv < 0) || (rv > DEBGFS_LINE_SZ)) { - qdma_log_error( - "%s: Insufficient buffer, err:%d\n", - __func__, - -QDMA_ERR_NO_MEM); - return -QDMA_ERR_NO_MEM; - } - buf += rv; - data_len += rv; - buflen -= rv; - } else - qdma_log_info( - "%-40s [%2u,%2u] %#-10x\n", - bitfield_name, - msb, lsb, - (reg_val & bitfield) >> lsb); - - - } else { - if (buf) { - rv = QDMA_SNPRINTF_S(buf, buflen, - DEBGFS_LINE_SZ, - "%-40s [%5u] %#-10x\n", - bitfield_name, - lsb, - (reg_val & bitfield) >> - lsb); - if ((rv < 0) || (rv > DEBGFS_LINE_SZ)) { - qdma_log_error( - "%s: Insufficient buffer, err:%d\n", - __func__, - -QDMA_ERR_NO_MEM); - return -QDMA_ERR_NO_MEM; - } - buf += rv; - data_len += rv; - buflen -= rv; - } else - qdma_log_info( - "%-40s [%5u] %#-10x\n", - bitfield_name, - lsb, - (reg_val & bitfield) >> lsb); - - } - } - } - - return data_len; -} - diff --git a/QDMA/linux-kernel/driver/libqdma/qdma_access/eqdma_cpm5_access/eqdma_cpm5_access.h b/QDMA/linux-kernel/driver/libqdma/qdma_access/eqdma_cpm5_access/eqdma_cpm5_access.h deleted file mode 100755 index 93662d22f..000000000 --- a/QDMA/linux-kernel/driver/libqdma/qdma_access/eqdma_cpm5_access/eqdma_cpm5_access.h +++ /dev/null @@ -1,344 +0,0 @@ -/* - * Copyright (c) 2019-2022, Xilinx, Inc. All rights reserved. - * Copyright (c) 2022, Advanced Micro Devices, Inc. All rights reserved. - * - * This source code is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * The full GNU General Public License is included in this distribution in - * the file called "COPYING". - */ - -#ifndef __EQDMA_CPM5_SOFT_ACCESS_H_ -#define __EQDMA_CPM5_SOFT_ACCESS_H_ - -#ifdef __cplusplus -extern "C" { -#endif - -#include "qdma_platform.h" - -/** - * enum eqdma_cpm5_error_idx - qdma errors - */ -enum eqdma_cpm5_error_idx { - /* Descriptor errors */ - EQDMA_CPM5_DSC_ERR_POISON, - EQDMA_CPM5_DSC_ERR_UR_CA, - EQDMA_CPM5_DSC_ERR_BCNT, - EQDMA_CPM5_DSC_ERR_PARAM, - EQDMA_CPM5_DSC_ERR_ADDR, - EQDMA_CPM5_DSC_ERR_TAG, - EQDMA_CPM5_DSC_ERR_FLR, - EQDMA_CPM5_DSC_ERR_TIMEOUT, - EQDMA_CPM5_DSC_ERR_DAT_POISON, - EQDMA_CPM5_DSC_ERR_FLR_CANCEL, - EQDMA_CPM5_DSC_ERR_DMA, - EQDMA_CPM5_DSC_ERR_DSC, - EQDMA_CPM5_DSC_ERR_RQ_CANCEL, - EQDMA_CPM5_DSC_ERR_DBE, - EQDMA_CPM5_DSC_ERR_SBE, - EQDMA_CPM5_DSC_ERR_PORT_ID, - EQDMA_CPM5_DSC_ERR_ALL, - - /* TRQ Errors */ - EQDMA_CPM5_TRQ_ERR_CSR_UNMAPPED, - EQDMA_CPM5_TRQ_ERR_VF_ACCESS, - EQDMA_CPM5_TRQ_ERR_TCP_CSR_TIMEOUT, - EQDMA_CPM5_TRQ_ERR_QSPC_UNMAPPED, - EQDMA_CPM5_TRQ_ERR_QID_RANGE, - EQDMA_CPM5_TRQ_ERR_TCP_QSPC_TIMEOUT, - EQDMA_CPM5_TRQ_ERR_ALL, - - /* ST C2H Errors */ - EQDMA_CPM5_ST_C2H_ERR_MTY_MISMATCH, - EQDMA_CPM5_ST_C2H_ERR_LEN_MISMATCH, - EQDMA_CPM5_ST_C2H_ERR_SH_CMPT_DSC, - EQDMA_CPM5_ST_C2H_ERR_QID_MISMATCH, - EQDMA_CPM5_ST_C2H_ERR_DESC_RSP_ERR, - EQDMA_CPM5_ST_C2H_ERR_ENG_WPL_DATA_PAR_ERR, - EQDMA_CPM5_ST_C2H_ERR_MSI_INT_FAIL, - EQDMA_CPM5_ST_C2H_ERR_ERR_DESC_CNT, - EQDMA_CPM5_ST_C2H_ERR_PORTID_CTXT_MISMATCH, - EQDMA_CPM5_ST_C2H_ERR_CMPT_INV_Q_ERR, - EQDMA_CPM5_ST_C2H_ERR_CMPT_QFULL_ERR, - EQDMA_CPM5_ST_C2H_ERR_CMPT_CIDX_ERR, - EQDMA_CPM5_ST_C2H_ERR_CMPT_PRTY_ERR, - EQDMA_CPM5_ST_C2H_ERR_AVL_RING_DSC, - EQDMA_CPM5_ST_C2H_ERR_HDR_ECC_UNC, - EQDMA_CPM5_ST_C2H_ERR_HDR_ECC_COR, - EQDMA_CPM5_ST_C2H_ERR_WRB_PORT_ID_ERR, - EQDMA_CPM5_ST_C2H_ERR_ALL, - - /* Fatal Errors */ - EQDMA_CPM5_ST_FATAL_ERR_MTY_MISMATCH, - EQDMA_CPM5_ST_FATAL_ERR_LEN_MISMATCH, - EQDMA_CPM5_ST_FATAL_ERR_QID_MISMATCH, - EQDMA_CPM5_ST_FATAL_ERR_TIMER_FIFO_RAM_RDBE, - EQDMA_CPM5_ST_FATAL_ERR_PFCH_II_RAM_RDBE, - EQDMA_CPM5_ST_FATAL_ERR_CMPT_CTXT_RAM_RDBE, - EQDMA_CPM5_ST_FATAL_ERR_PFCH_CTXT_RAM_RDBE, - EQDMA_CPM5_ST_FATAL_ERR_DESC_REQ_FIFO_RAM_RDBE, - EQDMA_CPM5_ST_FATAL_ERR_INT_CTXT_RAM_RDBE, - EQDMA_CPM5_ST_FATAL_ERR_CMPT_COAL_DATA_RAM_RDBE, - EQDMA_CPM5_ST_FATAL_ERR_CMPT_FIFO_RAM_RDBE, - EQDMA_CPM5_ST_FATAL_ERR_QID_FIFO_RAM_RDBE, - EQDMA_CPM5_ST_FATAL_ERR_PAYLOAD_FIFO_RAM_RDBE, - EQDMA_CPM5_ST_FATAL_ERR_WPL_DATA_PAR, - EQDMA_CPM5_ST_FATAL_ERR_AVL_RING_FIFO_RAM_RDBE, - EQDMA_CPM5_ST_FATAL_ERR_HDR_ECC_UNC, - EQDMA_CPM5_ST_FATAL_ERR_ALL, - - /* H2C Errors */ - EQDMA_CPM5_ST_H2C_ERR_ZERO_LEN_DESC, - EQDMA_CPM5_ST_H2C_ERR_SDI_MRKR_REQ_MOP, - EQDMA_CPM5_ST_H2C_ERR_NO_DMA_DSC, - EQDMA_CPM5_ST_H2C_ERR_SBE, - EQDMA_CPM5_ST_H2C_ERR_DBE, - EQDMA_CPM5_ST_H2C_ERR_PAR, - EQDMA_CPM5_ST_H2C_ERR_ALL, - - /* Single bit errors */ - EQDMA_CPM5_SBE_1_ERR_RC_RRQ_EVEN_RAM, - EQDMA_CPM5_SBE_1_ERR_TAG_ODD_RAM, - EQDMA_CPM5_SBE_1_ERR_TAG_EVEN_RAM, - EQDMA_CPM5_SBE_1_ERR_PFCH_CTXT_CAM_RAM_0, - EQDMA_CPM5_SBE_1_ERR_PFCH_CTXT_CAM_RAM_1, - EQDMA_CPM5_SBE_1_ERR_ALL, - - /* Single bit errors */ - EQDMA_CPM5_SBE_ERR_MI_H2C0_DAT, - EQDMA_CPM5_SBE_ERR_MI_H2C1_DAT, - EQDMA_CPM5_SBE_ERR_MI_H2C2_DAT, - EQDMA_CPM5_SBE_ERR_MI_H2C3_DAT, - EQDMA_CPM5_SBE_ERR_MI_C2H0_DAT, - EQDMA_CPM5_SBE_ERR_MI_C2H1_DAT, - EQDMA_CPM5_SBE_ERR_MI_C2H2_DAT, - EQDMA_CPM5_SBE_ERR_MI_C2H3_DAT, - EQDMA_CPM5_SBE_ERR_H2C_RD_BRG_DAT, - EQDMA_CPM5_SBE_ERR_H2C_WR_BRG_DAT, - EQDMA_CPM5_SBE_ERR_C2H_RD_BRG_DAT, - EQDMA_CPM5_SBE_ERR_C2H_WR_BRG_DAT, - EQDMA_CPM5_SBE_ERR_FUNC_MAP, - EQDMA_CPM5_SBE_ERR_DSC_HW_CTXT, - EQDMA_CPM5_SBE_ERR_DSC_CRD_RCV, - EQDMA_CPM5_SBE_ERR_DSC_SW_CTXT, - EQDMA_CPM5_SBE_ERR_DSC_CPLI, - EQDMA_CPM5_SBE_ERR_DSC_CPLD, - EQDMA_CPM5_SBE_ERR_MI_TL_SLV_FIFO_RAM, - EQDMA_CPM5_SBE_ERR_TIMER_FIFO_RAM, - EQDMA_CPM5_SBE_ERR_QID_FIFO_RAM, - EQDMA_CPM5_SBE_ERR_WRB_COAL_DATA_RAM, - EQDMA_CPM5_SBE_ERR_INT_CTXT_RAM, - EQDMA_CPM5_SBE_ERR_DESC_REQ_FIFO_RAM, - EQDMA_CPM5_SBE_ERR_PFCH_CTXT_RAM, - EQDMA_CPM5_SBE_ERR_WRB_CTXT_RAM, - EQDMA_CPM5_SBE_ERR_PFCH_LL_RAM, - EQDMA_CPM5_SBE_ERR_PEND_FIFO_RAM, - EQDMA_CPM5_SBE_ERR_RC_RRQ_ODD_RAM, - EQDMA_CPM5_SBE_ERR_ALL, - - /* Double bit Errors */ - EQDMA_CPM5_DBE_1_ERR_RC_RRQ_EVEN_RAM, - EQDMA_CPM5_DBE_1_ERR_TAG_ODD_RAM, - EQDMA_CPM5_DBE_1_ERR_TAG_EVEN_RAM, - EQDMA_CPM5_DBE_1_ERR_PFCH_CTXT_CAM_RAM_0, - EQDMA_CPM5_DBE_1_ERR_PFCH_CTXT_CAM_RAM_1, - EQDMA_CPM5_DBE_1_ERR_ALL, - - /* Double bit Errors */ - EQDMA_CPM5_DBE_ERR_MI_H2C0_DAT, - EQDMA_CPM5_DBE_ERR_MI_H2C1_DAT, - EQDMA_CPM5_DBE_ERR_MI_H2C2_DAT, - EQDMA_CPM5_DBE_ERR_MI_H2C3_DAT, - EQDMA_CPM5_DBE_ERR_MI_C2H0_DAT, - EQDMA_CPM5_DBE_ERR_MI_C2H1_DAT, - EQDMA_CPM5_DBE_ERR_MI_C2H2_DAT, - EQDMA_CPM5_DBE_ERR_MI_C2H3_DAT, - EQDMA_CPM5_DBE_ERR_H2C_RD_BRG_DAT, - EQDMA_CPM5_DBE_ERR_H2C_WR_BRG_DAT, - EQDMA_CPM5_DBE_ERR_C2H_RD_BRG_DAT, - EQDMA_CPM5_DBE_ERR_C2H_WR_BRG_DAT, - EQDMA_CPM5_DBE_ERR_FUNC_MAP, - EQDMA_CPM5_DBE_ERR_DSC_HW_CTXT, - EQDMA_CPM5_DBE_ERR_DSC_CRD_RCV, - EQDMA_CPM5_DBE_ERR_DSC_SW_CTXT, - EQDMA_CPM5_DBE_ERR_DSC_CPLI, - EQDMA_CPM5_DBE_ERR_DSC_CPLD, - EQDMA_CPM5_DBE_ERR_MI_TL_SLV_FIFO_RAM, - EQDMA_CPM5_DBE_ERR_TIMER_FIFO_RAM, - EQDMA_CPM5_DBE_ERR_QID_FIFO_RAM, - EQDMA_CPM5_DBE_ERR_WRB_COAL_DATA_RAM, - EQDMA_CPM5_DBE_ERR_INT_CTXT_RAM, - EQDMA_CPM5_DBE_ERR_DESC_REQ_FIFO_RAM, - EQDMA_CPM5_DBE_ERR_PFCH_CTXT_RAM, - EQDMA_CPM5_DBE_ERR_WRB_CTXT_RAM, - EQDMA_CPM5_DBE_ERR_PFCH_LL_RAM, - EQDMA_CPM5_DBE_ERR_PEND_FIFO_RAM, - EQDMA_CPM5_DBE_ERR_RC_RRQ_ODD_RAM, - EQDMA_CPM5_DBE_ERR_ALL, - - /* MM C2H Errors */ - EQDMA_CPM5_MM_C2H_WR_SLR_ERR, - EQDMA_CPM5_MM_C2H_RD_SLR_ERR, - EQDMA_CPM5_MM_C2H_WR_FLR_ERR, - EQDMA_CPM5_MM_C2H_UR_ERR, - EQDMA_CPM5_MM_C2H_WR_UC_RAM_ERR, - EQDMA_CPM5_MM_C2H_ERR_ALL, - - /* MM H2C Engine0 Errors */ - EQDMA_CPM5_MM_H2C0_RD_HDR_POISON_ERR, - EQDMA_CPM5_MM_H2C0_RD_UR_CA_ERR, - EQDMA_CPM5_MM_H2C0_RD_HDR_BYTE_ERR, - EQDMA_CPM5_MM_H2C0_RD_HDR_PARAM_ERR, - EQDMA_CPM5_MM_H2C0_RD_HDR_ADR_ERR, - EQDMA_CPM5_MM_H2C0_RD_FLR_ERR, - EQDMA_CPM5_MM_H2C0_RD_DAT_POISON_ERR, - EQDMA_CPM5_MM_H2C0_RD_RQ_DIS_ERR, - EQDMA_CPM5_MM_H2C0_WR_DEC_ERR, - EQDMA_CPM5_MM_H2C0_WR_SLV_ERR, - EQDMA_CPM5_MM_H2C0_ERR_ALL, - - EQDMA_CPM5_ERRS_ALL -}; - -struct eqdma_cpm5_hw_err_info { - enum eqdma_cpm5_error_idx idx; - const char *err_name; - uint32_t mask_reg_addr; - uint32_t stat_reg_addr; - uint32_t leaf_err_mask; - uint32_t global_err_mask; - void (*eqdma_cpm5_hw_err_process)(void *dev_hndl); -}; - -#ifdef EQDMA_CPM5_VF_GT_256Q_SUPPORTED -#define EQDMA_CPM5_OFFSET_VF_VERSION 0x21014 -#define EQDMA_CPM5_OFFSET_MBOX_BASE_VF 0x21000 -#else -#define EQDMA_CPM5_OFFSET_VF_VERSION 0x5014 -#define EQDMA_CPM5_OFFSET_MBOX_BASE_VF 0x5000 -#endif - -#define EQDMA_CPM5_OFFSET_MBOX_BASE_PF 0x42400 -#define EQDMA_CPM5_OFFSET_VF_USER_BAR 0x5018 - -#define EQDMA_CPM5_COMPL_CTXT_BADDR_HIGH_H_MASK GENMASK_ULL(63, 38) -#define EQDMA_CPM5_COMPL_CTXT_BADDR_HIGH_L_MASK GENMASK_ULL(37, 6) -#define EQDMA_CPM5_COMPL_CTXT_BADDR_LOW_MASK GENMASK_ULL(5, 2) - -int eqdma_cpm5_init_ctxt_memory(void *dev_hndl); - -#ifdef TANDEM_BOOT_SUPPORTED -int eqdma_cpm5_init_st_ctxt(void *dev_hndl); -#endif - -int eqdma_cpm5_get_version(void *dev_hndl, uint8_t is_vf, - struct qdma_hw_version_info *version_info); - -int eqdma_cpm5_sw_ctx_conf(void *dev_hndl, uint8_t c2h, uint16_t hw_qid, - struct qdma_descq_sw_ctxt *ctxt, - enum qdma_hw_access_type access_type); - -int eqdma_cpm5_hw_ctx_conf(void *dev_hndl, uint8_t c2h, uint16_t hw_qid, - struct qdma_descq_hw_ctxt *ctxt, - enum qdma_hw_access_type access_type); - -int eqdma_cpm5_credit_ctx_conf(void *dev_hndl, uint8_t c2h, - uint16_t hw_qid, struct qdma_descq_credit_ctxt *ctxt, - enum qdma_hw_access_type access_type); - -int eqdma_cpm5_pfetch_ctx_conf(void *dev_hndl, uint16_t hw_qid, - struct qdma_descq_prefetch_ctxt *ctxt, - enum qdma_hw_access_type access_type); - -int eqdma_cpm5_cmpt_ctx_conf(void *dev_hndl, uint16_t hw_qid, - struct qdma_descq_cmpt_ctxt *ctxt, - enum qdma_hw_access_type access_type); - -int eqdma_cpm5_fmap_conf(void *dev_hndl, uint16_t func_id, - struct qdma_fmap_cfg *config, - enum qdma_hw_access_type access_type); - -int eqdma_cpm5_indirect_intr_ctx_conf(void *dev_hndl, uint16_t ring_index, - struct qdma_indirect_intr_ctxt *ctxt, - enum qdma_hw_access_type access_type); - -int eqdma_cpm5_dump_config_regs(void *dev_hndl, uint8_t is_vf, - char *buf, uint32_t buflen); - -int eqdma_cpm5_dump_intr_context(void *dev_hndl, - struct qdma_indirect_intr_ctxt *intr_ctx, - int ring_index, - char *buf, uint32_t buflen); - -int eqdma_cpm5_dump_queue_context(void *dev_hndl, - uint8_t st, - enum qdma_dev_q_type q_type, - struct qdma_descq_context *ctxt_data, - char *buf, uint32_t buflen); - -uint32_t eqdma_cpm5_reg_dump_buf_len(void); - -int eqdma_cpm5_context_buf_len(uint8_t st, - enum qdma_dev_q_type q_type, uint32_t *buflen); - -int eqdma_cpm5_hw_error_process(void *dev_hndl); -const char *eqdma_cpm5_hw_get_error_name(uint32_t err_idx); -int eqdma_cpm5_hw_error_enable(void *dev_hndl, uint32_t err_idx); - -int eqdma_cpm5_read_dump_queue_context(void *dev_hndl, - uint16_t func_id, - uint16_t qid_hw, - uint8_t st, - enum qdma_dev_q_type q_type, - char *buf, uint32_t buflen); - -int eqdma_cpm5_get_device_attributes(void *dev_hndl, - struct qdma_dev_attributes *dev_info); - -int eqdma_cpm5_get_user_bar(void *dev_hndl, uint8_t is_vf, - uint16_t func_id, uint8_t *user_bar); - -int eqdma_cpm5_dump_config_reg_list(void *dev_hndl, - uint32_t total_regs, - struct qdma_reg_data *reg_list, - char *buf, uint32_t buflen); - -int eqdma_cpm5_read_reg_list(void *dev_hndl, uint8_t is_vf, - uint16_t reg_rd_group, - uint16_t *total_regs, - struct qdma_reg_data *reg_list); - -int eqdma_cpm5_set_default_global_csr(void *dev_hndl); - -int eqdma_cpm5_global_csr_conf(void *dev_hndl, uint8_t index, uint8_t count, - uint32_t *csr_val, - enum qdma_global_csr_type csr_type, - enum qdma_hw_access_type access_type); - -int eqdma_cpm5_global_writeback_interval_conf(void *dev_hndl, - enum qdma_wrb_interval *wb_int, - enum qdma_hw_access_type access_type); - -int eqdma_cpm5_mm_channel_conf(void *dev_hndl, uint8_t channel, - uint8_t is_c2h, uint8_t enable); - -int eqdma_cpm5_dump_reg_info(void *dev_hndl, uint32_t reg_addr, - uint32_t num_regs, char *buf, uint32_t buflen); - -uint32_t eqdma_cpm5_get_config_num_regs(void); - -struct xreg_info *eqdma_cpm5_get_config_regs(void); - -#ifdef __cplusplus -} -#endif - -#endif /* __EQDMA_CPM5_SOFT_ACCESS_H_ */ diff --git a/QDMA/linux-kernel/driver/libqdma/qdma_access/eqdma_cpm5_access/eqdma_cpm5_reg.h b/QDMA/linux-kernel/driver/libqdma/qdma_access/eqdma_cpm5_access/eqdma_cpm5_reg.h deleted file mode 100755 index 402748439..000000000 --- a/QDMA/linux-kernel/driver/libqdma/qdma_access/eqdma_cpm5_access/eqdma_cpm5_reg.h +++ /dev/null @@ -1,1284 +0,0 @@ -/* - * Copyright (c) 2019-2022 Xilinx, Inc. All rights reserved. - * Copyright (c) 2022, Advanced Micro Devices, Inc. All rights reserved. - * - * This source code is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * The full GNU General Public License is included in this distribution in - * the file called "COPYING". - */ - -#ifndef __EQDMA_CPM5_REG_H -#define __EQDMA_CPM5_REG_H - - -#ifdef __cplusplus -extern "C" { -#endif - -#include "qdma_platform.h" - -#ifdef CHAR_BIT -#undef CHAR_BIT -#endif -#define CHAR_BIT 8 - -#ifdef BIT -#undef BIT -#endif -#define BIT(n) (1u << (n)) - -#ifdef BITS_PER_BYTE -#undef BITS_PER_BYTE -#endif -#define BITS_PER_BYTE CHAR_BIT - -#ifdef BITS_PER_LONG -#undef BITS_PER_LONG -#endif -#define BITS_PER_LONG (sizeof(uint32_t) * BITS_PER_BYTE) - -#ifdef BITS_PER_LONG_LONG -#undef BITS_PER_LONG_LONG -#endif -#define BITS_PER_LONG_LONG (sizeof(uint64_t) * BITS_PER_BYTE) - -#ifdef GENMASK -#undef GENMASK -#endif -#define GENMASK(h, l) \ - ((0xFFFFFFFF << (l)) & (0xFFFFFFFF >> (BITS_PER_LONG - 1 - (h)))) - -#ifdef GENMASK_ULL -#undef GENMASK_ULL -#endif -#define GENMASK_ULL(h, l) \ - ((0xFFFFFFFFFFFFFFFF << (l)) & \ - (0xFFFFFFFFFFFFFFFF >> (BITS_PER_LONG_LONG - 1 - (h)))) - -#define DEBGFS_LINE_SZ (81) - -#ifdef ARRAY_SIZE -#undef ARRAY_SIZE -#endif -#define ARRAY_SIZE(arr) (sizeof(arr) / \ - sizeof(arr[0])) - - -uint32_t eqdma_cpm5_config_num_regs_get(void); -struct xreg_info *eqdma_cpm5_config_regs_get(void); -#define EQDMA_CPM5_CFG_BLK_IDENTIFIER_ADDR 0x00 -#define CFG_BLK_IDENTIFIER_MASK GENMASK(31, 20) -#define CFG_BLK_IDENTIFIER_1_MASK GENMASK(19, 16) -#define CFG_BLK_IDENTIFIER_RSVD_1_MASK GENMASK(15, 8) -#define CFG_BLK_IDENTIFIER_VERSION_MASK GENMASK(7, 0) -#define EQDMA_CPM5_CFG_BLK_PCIE_MAX_PLD_SIZE_ADDR 0x08 -#define CFG_BLK_PCIE_MAX_PLD_SIZE_RSVD_1_MASK GENMASK(31, 7) -#define CFG_BLK_PCIE_MAX_PLD_SIZE_PROG_MASK GENMASK(6, 4) -#define CFG_BLK_PCIE_MAX_PLD_SIZE_RSVD_2_MASK BIT(3) -#define CFG_BLK_PCIE_MAX_PLD_SIZE_ISSUED_MASK GENMASK(2, 0) -#define EQDMA_CPM5_CFG_BLK_PCIE_MAX_READ_REQ_SIZE_ADDR 0x0C -#define CFG_BLK_PCIE_MAX_READ_REQ_SIZE_RSVD_1_MASK GENMASK(31, 7) -#define CFG_BLK_PCIE_MAX_READ_REQ_SIZE_PROG_MASK GENMASK(6, 4) -#define CFG_BLK_PCIE_MAX_READ_REQ_SIZE_RSVD_2_MASK BIT(3) -#define CFG_BLK_PCIE_MAX_READ_REQ_SIZE_ISSUED_MASK GENMASK(2, 0) -#define EQDMA_CPM5_CFG_BLK_SYSTEM_ID_ADDR 0x10 -#define CFG_BLK_SYSTEM_ID_RSVD_1_MASK GENMASK(31, 17) -#define CFG_BLK_SYSTEM_ID_INST_TYPE_MASK BIT(16) -#define CFG_BLK_SYSTEM_ID_MASK GENMASK(15, 0) -#define EQDMA_CPM5_CFG_BLK_MSIX_ENABLE_ADDR 0x014 -#define CFG_BLK_MSIX_ENABLE_MASK GENMASK(31, 0) -#define EQDMA_CPM5_CFG_PCIE_DATA_WIDTH_ADDR 0x18 -#define CFG_PCIE_DATA_WIDTH_RSVD_1_MASK GENMASK(31, 3) -#define CFG_PCIE_DATA_WIDTH_DATAPATH_MASK GENMASK(2, 0) -#define EQDMA_CPM5_CFG_PCIE_CTL_ADDR 0x1C -#define CFG_PCIE_CTL_RSVD_1_MASK GENMASK(31, 18) -#define CFG_PCIE_CTL_MGMT_AXIL_CTRL_MASK GENMASK(17, 16) -#define CFG_PCIE_CTL_RSVD_2_MASK GENMASK(15, 2) -#define CFG_PCIE_CTL_RRQ_DISABLE_MASK BIT(1) -#define CFG_PCIE_CTL_RELAXED_ORDERING_MASK BIT(0) -#define EQDMA_CPM5_CFG_BLK_MSI_ENABLE_ADDR 0x20 -#define CFG_BLK_MSI_ENABLE_MASK GENMASK(31, 0) -#define EQDMA_CPM5_CFG_AXI_USER_MAX_PLD_SIZE_ADDR 0x40 -#define CFG_AXI_USER_MAX_PLD_SIZE_RSVD_1_MASK GENMASK(31, 7) -#define CFG_AXI_USER_MAX_PLD_SIZE_ISSUED_MASK GENMASK(6, 4) -#define CFG_AXI_USER_MAX_PLD_SIZE_RSVD_2_MASK BIT(3) -#define CFG_AXI_USER_MAX_PLD_SIZE_PROG_MASK GENMASK(2, 0) -#define EQDMA_CPM5_CFG_AXI_USER_MAX_READ_REQ_SIZE_ADDR 0x44 -#define CFG_AXI_USER_MAX_READ_REQ_SIZE_RSVD_1_MASK GENMASK(31, 7) -#define CFG_AXI_USER_MAX_READ_REQ_SIZE_USISSUED_MASK GENMASK(6, 4) -#define CFG_AXI_USER_MAX_READ_REQ_SIZE_RSVD_2_MASK BIT(3) -#define CFG_AXI_USER_MAX_READ_REQ_SIZE_USPROG_MASK GENMASK(2, 0) -#define EQDMA_CPM5_CFG_BLK_MISC_CTL_ADDR 0x4C -#define CFG_BLK_MISC_CTL_RSVD_1_MASK GENMASK(31, 24) -#define CFG_BLK_MISC_CTL_10B_TAG_EN_MASK BIT(23) -#define CFG_BLK_MISC_CTL_RSVD_2_MASK BIT(22) -#define CFG_BLK_MISC_CTL_AXI_WBK_MASK BIT(21) -#define CFG_BLK_MISC_CTL_AXI_DSC_MASK BIT(20) -#define CFG_BLK_MISC_CTL_NUM_TAG_MASK GENMASK(19, 8) -#define CFG_BLK_MISC_CTL_RSVD_3_MASK GENMASK(7, 5) -#define CFG_BLK_MISC_CTL_RQ_METERING_MULTIPLIER_MASK GENMASK(4, 0) -#define EQDMA_CPM5_CFG_PL_CRED_CTL_ADDR 0x68 -#define CFG_PL_CRED_CTL_RSVD_1_MASK GENMASK(31, 5) -#define CFG_PL_CRED_CTL_SLAVE_CRD_RLS_MASK BIT(4) -#define CFG_PL_CRED_CTL_RSVD_2_MASK GENMASK(3, 1) -#define CFG_PL_CRED_CTL_MASTER_CRD_RST_MASK BIT(0) -#define EQDMA_CPM5_CFG_BLK_SCRATCH_ADDR 0x80 -#define CFG_BLK_SCRATCH_MASK GENMASK(31, 0) -#define EQDMA_CPM5_CFG_GIC_ADDR 0xA0 -#define CFG_GIC_RSVD_1_MASK GENMASK(31, 1) -#define CFG_GIC_GIC_IRQ_MASK BIT(0) -#define EQDMA_CPM5_RAM_SBE_MSK_1_A_ADDR 0xE0 -#define RAM_SBE_MSK_1_A_MASK GENMASK(31, 0) -#define EQDMA_CPM5_RAM_SBE_STS_1_A_ADDR 0xE4 -#define RAM_SBE_STS_1_A_RSVD_MASK GENMASK(31, 5) -#define RAM_SBE_STS_1_A_PFCH_CTXT_CAM_RAM_1_MASK BIT(4) -#define RAM_SBE_STS_1_A_PFCH_CTXT_CAM_RAM_0_MASK BIT(3) -#define RAM_SBE_STS_1_A_TAG_EVEN_RAM_MASK BIT(2) -#define RAM_SBE_STS_1_A_TAG_ODD_RAM_MASK BIT(1) -#define RAM_SBE_STS_1_A_RC_RRQ_EVEN_RAM_MASK BIT(0) -#define EQDMA_CPM5_RAM_DBE_MSK_1_A_ADDR 0xE8 -#define RAM_DBE_MSK_1_A_MASK GENMASK(31, 0) -#define EQDMA_CPM5_RAM_DBE_STS_1_A_ADDR 0xEC -#define RAM_DBE_STS_1_A_RSVD_MASK GENMASK(31, 5) -#define RAM_DBE_STS_1_A_PFCH_CTXT_CAM_RAM_1_MASK BIT(4) -#define RAM_DBE_STS_1_A_PFCH_CTXT_CAM_RAM_0_MASK BIT(3) -#define RAM_DBE_STS_1_A_TAG_EVEN_RAM_MASK BIT(2) -#define RAM_DBE_STS_1_A_TAG_ODD_RAM_MASK BIT(1) -#define RAM_DBE_STS_1_A_RC_RRQ_EVEN_RAM_MASK BIT(0) -#define EQDMA_CPM5_RAM_SBE_MSK_A_ADDR 0xF0 -#define RAM_SBE_MSK_A_MASK GENMASK(31, 0) -#define EQDMA_CPM5_RAM_SBE_STS_A_ADDR 0xF4 -#define RAM_SBE_STS_A_RC_RRQ_ODD_RAM_MASK BIT(31) -#define RAM_SBE_STS_A_PEND_FIFO_RAM_MASK BIT(30) -#define RAM_SBE_STS_A_PFCH_LL_RAM_MASK BIT(29) -#define RAM_SBE_STS_A_WRB_CTXT_RAM_MASK BIT(28) -#define RAM_SBE_STS_A_PFCH_CTXT_RAM_MASK BIT(27) -#define RAM_SBE_STS_A_DESC_REQ_FIFO_RAM_MASK BIT(26) -#define RAM_SBE_STS_A_INT_CTXT_RAM_MASK BIT(25) -#define RAM_SBE_STS_A_WRB_COAL_DATA_RAM_MASK BIT(24) -#define RAM_SBE_STS_A_QID_FIFO_RAM_MASK BIT(23) -#define RAM_SBE_STS_A_TIMER_FIFO_RAM_MASK GENMASK(22, 19) -#define RAM_SBE_STS_A_MI_TL_SLV_FIFO_RAM_MASK BIT(18) -#define RAM_SBE_STS_A_DSC_CPLD_MASK BIT(17) -#define RAM_SBE_STS_A_DSC_CPLI_MASK BIT(16) -#define RAM_SBE_STS_A_DSC_SW_CTXT_MASK BIT(15) -#define RAM_SBE_STS_A_DSC_CRD_RCV_MASK BIT(14) -#define RAM_SBE_STS_A_DSC_HW_CTXT_MASK BIT(13) -#define RAM_SBE_STS_A_FUNC_MAP_MASK BIT(12) -#define RAM_SBE_STS_A_C2H_WR_BRG_DAT_MASK BIT(11) -#define RAM_SBE_STS_A_C2H_RD_BRG_DAT_MASK BIT(10) -#define RAM_SBE_STS_A_H2C_WR_BRG_DAT_MASK BIT(9) -#define RAM_SBE_STS_A_H2C_RD_BRG_DAT_MASK BIT(8) -#define RAM_SBE_STS_A_MI_C2H3_DAT_MASK BIT(7) -#define RAM_SBE_STS_A_MI_C2H2_DAT_MASK BIT(6) -#define RAM_SBE_STS_A_MI_C2H1_DAT_MASK BIT(5) -#define RAM_SBE_STS_A_MI_C2H0_DAT_MASK BIT(4) -#define RAM_SBE_STS_A_MI_H2C3_DAT_MASK BIT(3) -#define RAM_SBE_STS_A_MI_H2C2_DAT_MASK BIT(2) -#define RAM_SBE_STS_A_MI_H2C1_DAT_MASK BIT(1) -#define RAM_SBE_STS_A_MI_H2C0_DAT_MASK BIT(0) -#define EQDMA_CPM5_RAM_DBE_MSK_A_ADDR 0xF8 -#define RAM_DBE_MSK_A_MASK GENMASK(31, 0) -#define EQDMA_CPM5_RAM_DBE_STS_A_ADDR 0xFC -#define RAM_DBE_STS_A_RC_RRQ_ODD_RAM_MASK BIT(31) -#define RAM_DBE_STS_A_PEND_FIFO_RAM_MASK BIT(30) -#define RAM_DBE_STS_A_PFCH_LL_RAM_MASK BIT(29) -#define RAM_DBE_STS_A_WRB_CTXT_RAM_MASK BIT(28) -#define RAM_DBE_STS_A_PFCH_CTXT_RAM_MASK BIT(27) -#define RAM_DBE_STS_A_DESC_REQ_FIFO_RAM_MASK BIT(26) -#define RAM_DBE_STS_A_INT_CTXT_RAM_MASK BIT(25) -#define RAM_DBE_STS_A_WRB_COAL_DATA_RAM_MASK BIT(24) -#define RAM_DBE_STS_A_QID_FIFO_RAM_MASK BIT(23) -#define RAM_DBE_STS_A_TIMER_FIFO_RAM_MASK GENMASK(22, 19) -#define RAM_DBE_STS_A_MI_TL_SLV_FIFO_RAM_MASK BIT(18) -#define RAM_DBE_STS_A_DSC_CPLD_MASK BIT(17) -#define RAM_DBE_STS_A_DSC_CPLI_MASK BIT(16) -#define RAM_DBE_STS_A_DSC_SW_CTXT_MASK BIT(15) -#define RAM_DBE_STS_A_DSC_CRD_RCV_MASK BIT(14) -#define RAM_DBE_STS_A_DSC_HW_CTXT_MASK BIT(13) -#define RAM_DBE_STS_A_FUNC_MAP_MASK BIT(12) -#define RAM_DBE_STS_A_C2H_WR_BRG_DAT_MASK BIT(11) -#define RAM_DBE_STS_A_C2H_RD_BRG_DAT_MASK BIT(10) -#define RAM_DBE_STS_A_H2C_WR_BRG_DAT_MASK BIT(9) -#define RAM_DBE_STS_A_H2C_RD_BRG_DAT_MASK BIT(8) -#define RAM_DBE_STS_A_MI_C2H3_DAT_MASK BIT(7) -#define RAM_DBE_STS_A_MI_C2H2_DAT_MASK BIT(6) -#define RAM_DBE_STS_A_MI_C2H1_DAT_MASK BIT(5) -#define RAM_DBE_STS_A_MI_C2H0_DAT_MASK BIT(4) -#define RAM_DBE_STS_A_MI_H2C3_DAT_MASK BIT(3) -#define RAM_DBE_STS_A_MI_H2C2_DAT_MASK BIT(2) -#define RAM_DBE_STS_A_MI_H2C1_DAT_MASK BIT(1) -#define RAM_DBE_STS_A_MI_H2C0_DAT_MASK BIT(0) -#define EQDMA_CPM5_GLBL2_IDENTIFIER_ADDR 0x100 -#define GLBL2_IDENTIFIER_MASK GENMASK(31, 8) -#define GLBL2_IDENTIFIER_VERSION_MASK GENMASK(7, 0) -#define EQDMA_CPM5_GLBL2_CHANNEL_INST_ADDR 0x114 -#define GLBL2_CHANNEL_INST_RSVD_1_MASK GENMASK(31, 18) -#define GLBL2_CHANNEL_INST_C2H_ST_MASK BIT(17) -#define GLBL2_CHANNEL_INST_H2C_ST_MASK BIT(16) -#define GLBL2_CHANNEL_INST_RSVD_2_MASK GENMASK(15, 12) -#define GLBL2_CHANNEL_INST_C2H_ENG_MASK GENMASK(11, 8) -#define GLBL2_CHANNEL_INST_RSVD_3_MASK GENMASK(7, 4) -#define GLBL2_CHANNEL_INST_H2C_ENG_MASK GENMASK(3, 0) -#define EQDMA_CPM5_GLBL2_CHANNEL_MDMA_ADDR 0x118 -#define GLBL2_CHANNEL_MDMA_RSVD_1_MASK GENMASK(31, 18) -#define GLBL2_CHANNEL_MDMA_C2H_ST_MASK BIT(17) -#define GLBL2_CHANNEL_MDMA_H2C_ST_MASK BIT(16) -#define GLBL2_CHANNEL_MDMA_RSVD_2_MASK GENMASK(15, 12) -#define GLBL2_CHANNEL_MDMA_C2H_ENG_MASK GENMASK(11, 8) -#define GLBL2_CHANNEL_MDMA_RSVD_3_MASK GENMASK(7, 4) -#define GLBL2_CHANNEL_MDMA_H2C_ENG_MASK GENMASK(3, 0) -#define EQDMA_CPM5_GLBL2_CHANNEL_STRM_ADDR 0x11C -#define GLBL2_CHANNEL_STRM_RSVD_1_MASK GENMASK(31, 18) -#define GLBL2_CHANNEL_STRM_C2H_ST_MASK BIT(17) -#define GLBL2_CHANNEL_STRM_H2C_ST_MASK BIT(16) -#define GLBL2_CHANNEL_STRM_RSVD_2_MASK GENMASK(15, 12) -#define GLBL2_CHANNEL_STRM_C2H_ENG_MASK GENMASK(11, 8) -#define GLBL2_CHANNEL_STRM_RSVD_3_MASK GENMASK(7, 4) -#define GLBL2_CHANNEL_STRM_H2C_ENG_MASK GENMASK(3, 0) -#define EQDMA_CPM5_GLBL2_CHANNEL_CAP_ADDR 0x120 -#define GLBL2_CHANNEL_CAP_RSVD_1_MASK GENMASK(31, 12) -#define GLBL2_CHANNEL_CAP_MULTIQ_MAX_MASK GENMASK(11, 0) -#define EQDMA_CPM5_GLBL2_CHANNEL_PASID_CAP_ADDR 0x128 -#define GLBL2_CHANNEL_PASID_CAP_RSVD_1_MASK GENMASK(31, 2) -#define GLBL2_CHANNEL_PASID_CAP_BRIDGEEN_MASK BIT(1) -#define GLBL2_CHANNEL_PASID_CAP_DMAEN_MASK BIT(0) -#define EQDMA_CPM5_GLBL2_SYSTEM_ID_ADDR 0x130 -#define GLBL2_SYSTEM_ID_RSVD_1_MASK GENMASK(31, 16) -#define GLBL2_SYSTEM_ID_MASK GENMASK(15, 0) -#define EQDMA_CPM5_GLBL2_MISC_CAP_ADDR 0x134 -#define GLBL2_MISC_CAP_MASK GENMASK(31, 0) -#define EQDMA_CPM5_GLBL2_DBG_PCIE_RQ0_ADDR 0x1B8 -#define GLBL2_PCIE_RQ0_NPH_AVL_MASK GENMASK(31, 20) -#define GLBL2_PCIE_RQ0_RCB_AVL_MASK GENMASK(19, 9) -#define GLBL2_PCIE_RQ0_SLV_RD_CREDS_MASK GENMASK(8, 2) -#define GLBL2_PCIE_RQ0_TAG_EP_MASK GENMASK(1, 0) -#define EQDMA_CPM5_GLBL2_DBG_PCIE_RQ1_ADDR 0x1BC -#define GLBL2_PCIE_RQ1_RSVD_1_MASK GENMASK(31, 21) -#define GLBL2_PCIE_RQ1_TAG_FL_MASK GENMASK(20, 19) -#define GLBL2_PCIE_RQ1_WTLP_HEADER_FIFO_FL_MASK BIT(18) -#define GLBL2_PCIE_RQ1_WTLP_HEADER_FIFO_EP_MASK BIT(17) -#define GLBL2_PCIE_RQ1_RQ_FIFO_EP_MASK BIT(16) -#define GLBL2_PCIE_RQ1_RQ_FIFO_FL_MASK BIT(15) -#define GLBL2_PCIE_RQ1_TLPSM_MASK GENMASK(14, 12) -#define GLBL2_PCIE_RQ1_TLPSM512_MASK GENMASK(11, 9) -#define GLBL2_PCIE_RQ1_RREQ_RCB_OK_MASK BIT(8) -#define GLBL2_PCIE_RQ1_RREQ0_SLV_MASK BIT(7) -#define GLBL2_PCIE_RQ1_RREQ0_VLD_MASK BIT(6) -#define GLBL2_PCIE_RQ1_RREQ0_RDY_MASK BIT(5) -#define GLBL2_PCIE_RQ1_RREQ1_SLV_MASK BIT(4) -#define GLBL2_PCIE_RQ1_RREQ1_VLD_MASK BIT(3) -#define GLBL2_PCIE_RQ1_RREQ1_RDY_MASK BIT(2) -#define GLBL2_PCIE_RQ1_WTLP_REQ_MASK BIT(1) -#define GLBL2_PCIE_RQ1_WTLP_STRADDLE_MASK BIT(0) -#define EQDMA_CPM5_GLBL2_DBG_AXIMM_WR0_ADDR 0x1C0 -#define GLBL2_AXIMM_WR0_RSVD_1_MASK GENMASK(31, 27) -#define GLBL2_AXIMM_WR0_WR_REQ_MASK BIT(26) -#define GLBL2_AXIMM_WR0_WR_CHN_MASK GENMASK(25, 23) -#define GLBL2_AXIMM_WR0_WTLP_DATA_FIFO_EP_MASK BIT(22) -#define GLBL2_AXIMM_WR0_WPL_FIFO_EP_MASK BIT(21) -#define GLBL2_AXIMM_WR0_BRSP_CLAIM_CHN_MASK GENMASK(20, 18) -#define GLBL2_AXIMM_WR0_WRREQ_CNT_MASK GENMASK(17, 12) -#define GLBL2_AXIMM_WR0_BID_MASK GENMASK(11, 9) -#define GLBL2_AXIMM_WR0_BVALID_MASK BIT(8) -#define GLBL2_AXIMM_WR0_BREADY_MASK BIT(7) -#define GLBL2_AXIMM_WR0_WVALID_MASK BIT(6) -#define GLBL2_AXIMM_WR0_WREADY_MASK BIT(5) -#define GLBL2_AXIMM_WR0_AWID_MASK GENMASK(4, 2) -#define GLBL2_AXIMM_WR0_AWVALID_MASK BIT(1) -#define GLBL2_AXIMM_WR0_AWREADY_MASK BIT(0) -#define EQDMA_CPM5_GLBL2_DBG_AXIMM_WR1_ADDR 0x1C4 -#define GLBL2_AXIMM_WR1_RSVD_1_MASK GENMASK(31, 30) -#define GLBL2_AXIMM_WR1_BRSP_CNT4_MASK GENMASK(29, 24) -#define GLBL2_AXIMM_WR1_BRSP_CNT3_MASK GENMASK(23, 18) -#define GLBL2_AXIMM_WR1_BRSP_CNT2_MASK GENMASK(17, 12) -#define GLBL2_AXIMM_WR1_BRSP_CNT1_MASK GENMASK(11, 6) -#define GLBL2_AXIMM_WR1_BRSP_CNT0_MASK GENMASK(5, 0) -#define EQDMA_CPM5_GLBL2_DBG_AXIMM_RD0_ADDR 0x1C8 -#define GLBL2_AXIMM_RD0_RSVD_1_MASK GENMASK(31, 23) -#define GLBL2_AXIMM_RD0_PND_CNT_MASK GENMASK(22, 17) -#define GLBL2_AXIMM_RD0_RD_REQ_MASK BIT(16) -#define GLBL2_AXIMM_RD0_RD_CHNL_MASK GENMASK(15, 13) -#define GLBL2_AXIMM_RD0_RRSP_CLAIM_CHNL_MASK GENMASK(12, 10) -#define GLBL2_AXIMM_RD0_RID_MASK GENMASK(9, 7) -#define GLBL2_AXIMM_RD0_RVALID_MASK BIT(6) -#define GLBL2_AXIMM_RD0_RREADY_MASK BIT(5) -#define GLBL2_AXIMM_RD0_ARID_MASK GENMASK(4, 2) -#define GLBL2_AXIMM_RD0_ARVALID_MASK BIT(1) -#define GLBL2_AXIMM_RD0_ARREADY_MASK BIT(0) -#define EQDMA_CPM5_GLBL2_DBG_AXIMM_RD1_ADDR 0x1CC -#define GLBL2_AXIMM_RD1_RSVD_1_MASK GENMASK(31, 30) -#define GLBL2_AXIMM_RD1_RRSP_CNT4_MASK GENMASK(29, 24) -#define GLBL2_AXIMM_RD1_RRSP_CNT3_MASK GENMASK(23, 18) -#define GLBL2_AXIMM_RD1_RRSP_CNT2_MASK GENMASK(17, 12) -#define GLBL2_AXIMM_RD1_RRSP_CNT1_MASK GENMASK(11, 6) -#define GLBL2_AXIMM_RD1_RRSP_CNT0_MASK GENMASK(5, 0) -#define EQDMA_CPM5_GLBL2_DBG_FAB0_ADDR 0x1D0 -#define GLBL2_FAB0_H2C_INB_CONV_IN_VLD_MASK BIT(31) -#define GLBL2_FAB0_H2C_INB_CONV_IN_RDY_MASK BIT(30) -#define GLBL2_FAB0_H2C_SEG_IN_VLD_MASK BIT(29) -#define GLBL2_FAB0_H2C_SEG_IN_RDY_MASK BIT(28) -#define GLBL2_FAB0_H2C_SEG_OUT_VLD_MASK GENMASK(27, 24) -#define GLBL2_FAB0_H2C_SEG_OUT_RDY_MASK BIT(23) -#define GLBL2_FAB0_H2C_MST_CRDT_STAT_MASK GENMASK(22, 16) -#define GLBL2_FAB0_C2H_SLV_AFIFO_FULL_MASK BIT(15) -#define GLBL2_FAB0_C2H_SLV_AFIFO_EMPTY_MASK BIT(14) -#define GLBL2_FAB0_C2H_DESEG_SEG_VLD_MASK GENMASK(13, 10) -#define GLBL2_FAB0_C2H_DESEG_SEG_RDY_MASK BIT(9) -#define GLBL2_FAB0_C2H_DESEG_OUT_VLD_MASK BIT(8) -#define GLBL2_FAB0_C2H_DESEG_OUT_RDY_MASK BIT(7) -#define GLBL2_FAB0_C2H_INB_DECONV_OUT_VLD_MASK BIT(6) -#define GLBL2_FAB0_C2H_INB_DECONV_OUT_RDY_MASK BIT(5) -#define GLBL2_FAB0_C2H_DSC_CRDT_AFIFO_FULL_MASK BIT(4) -#define GLBL2_FAB0_C2H_DSC_CRDT_AFIFO_EMPTY_MASK BIT(3) -#define GLBL2_FAB0_IRQ_IN_AFIFO_FULL_MASK BIT(2) -#define GLBL2_FAB0_IRQ_IN_AFIFO_EMPTY_MASK BIT(1) -#define GLBL2_FAB0_IMM_CRD_AFIFO_EMPTY_MASK BIT(0) -#define EQDMA_CPM5_GLBL2_DBG_FAB1_ADDR 0x1D4 -#define GLBL2_FAB1_BYP_OUT_CRDT_STAT_MASK GENMASK(31, 25) -#define GLBL2_FAB1_TM_DSC_STS_CRDT_STAT_MASK GENMASK(24, 18) -#define GLBL2_FAB1_C2H_CMN_AFIFO_FULL_MASK BIT(17) -#define GLBL2_FAB1_C2H_CMN_AFIFO_EMPTY_MASK BIT(16) -#define GLBL2_FAB1_RSVD_1_MASK GENMASK(15, 13) -#define GLBL2_FAB1_C2H_BYP_IN_AFIFO_FULL_MASK BIT(12) -#define GLBL2_FAB1_RSVD_2_MASK GENMASK(11, 9) -#define GLBL2_FAB1_C2H_BYP_IN_AFIFO_EMPTY_MASK BIT(8) -#define GLBL2_FAB1_RSVD_3_MASK GENMASK(7, 5) -#define GLBL2_FAB1_H2C_BYP_IN_AFIFO_FULL_MASK BIT(4) -#define GLBL2_FAB1_RSVD_4_MASK GENMASK(3, 1) -#define GLBL2_FAB1_H2C_BYP_IN_AFIFO_EMPTY_MASK BIT(0) -#define EQDMA_CPM5_GLBL2_DBG_MATCH_SEL_ADDR 0x1F4 -#define GLBL2_MATCH_SEL_RSV_MASK GENMASK(31, 18) -#define GLBL2_MATCH_SEL_CSR_SEL_MASK GENMASK(17, 13) -#define GLBL2_MATCH_SEL_CSR_EN_MASK BIT(12) -#define GLBL2_MATCH_SEL_ROTATE1_MASK GENMASK(11, 10) -#define GLBL2_MATCH_SEL_ROTATE0_MASK GENMASK(9, 8) -#define GLBL2_MATCH_SEL_SEL_MASK GENMASK(7, 0) -#define EQDMA_CPM5_GLBL2_DBG_MATCH_MSK_ADDR 0x1F8 -#define GLBL2_MATCH_MSK_MASK GENMASK(31, 0) -#define EQDMA_CPM5_GLBL2_DBG_MATCH_PAT_ADDR 0x1FC -#define GLBL2_MATCH_PAT_PATTERN_MASK GENMASK(31, 0) -#define EQDMA_CPM5_GLBL_RNG_SZ_1_ADDR 0x204 -#define GLBL_RNG_SZ_1_RSVD_1_MASK GENMASK(31, 16) -#define GLBL_RNG_SZ_1_RING_SIZE_MASK GENMASK(15, 0) -#define EQDMA_CPM5_GLBL_RNG_SZ_2_ADDR 0x208 -#define GLBL_RNG_SZ_2_RSVD_1_MASK GENMASK(31, 16) -#define GLBL_RNG_SZ_2_RING_SIZE_MASK GENMASK(15, 0) -#define EQDMA_CPM5_GLBL_RNG_SZ_3_ADDR 0x20C -#define GLBL_RNG_SZ_3_RSVD_1_MASK GENMASK(31, 16) -#define GLBL_RNG_SZ_3_RING_SIZE_MASK GENMASK(15, 0) -#define EQDMA_CPM5_GLBL_RNG_SZ_4_ADDR 0x210 -#define GLBL_RNG_SZ_4_RSVD_1_MASK GENMASK(31, 16) -#define GLBL_RNG_SZ_4_RING_SIZE_MASK GENMASK(15, 0) -#define EQDMA_CPM5_GLBL_RNG_SZ_5_ADDR 0x214 -#define GLBL_RNG_SZ_5_RSVD_1_MASK GENMASK(31, 16) -#define GLBL_RNG_SZ_5_RING_SIZE_MASK GENMASK(15, 0) -#define EQDMA_CPM5_GLBL_RNG_SZ_6_ADDR 0x218 -#define GLBL_RNG_SZ_6_RSVD_1_MASK GENMASK(31, 16) -#define GLBL_RNG_SZ_6_RING_SIZE_MASK GENMASK(15, 0) -#define EQDMA_CPM5_GLBL_RNG_SZ_7_ADDR 0x21C -#define GLBL_RNG_SZ_7_RSVD_1_MASK GENMASK(31, 16) -#define GLBL_RNG_SZ_7_RING_SIZE_MASK GENMASK(15, 0) -#define EQDMA_CPM5_GLBL_RNG_SZ_8_ADDR 0x220 -#define GLBL_RNG_SZ_8_RSVD_1_MASK GENMASK(31, 16) -#define GLBL_RNG_SZ_8_RING_SIZE_MASK GENMASK(15, 0) -#define EQDMA_CPM5_GLBL_RNG_SZ_9_ADDR 0x224 -#define GLBL_RNG_SZ_9_RSVD_1_MASK GENMASK(31, 16) -#define GLBL_RNG_SZ_9_RING_SIZE_MASK GENMASK(15, 0) -#define EQDMA_CPM5_GLBL_RNG_SZ_A_ADDR 0x228 -#define GLBL_RNG_SZ_A_RSVD_1_MASK GENMASK(31, 16) -#define GLBL_RNG_SZ_A_RING_SIZE_MASK GENMASK(15, 0) -#define EQDMA_CPM5_GLBL_RNG_SZ_B_ADDR 0x22C -#define GLBL_RNG_SZ_B_RSVD_1_MASK GENMASK(31, 16) -#define GLBL_RNG_SZ_B_RING_SIZE_MASK GENMASK(15, 0) -#define EQDMA_CPM5_GLBL_RNG_SZ_C_ADDR 0x230 -#define GLBL_RNG_SZ_C_RSVD_1_MASK GENMASK(31, 16) -#define GLBL_RNG_SZ_C_RING_SIZE_MASK GENMASK(15, 0) -#define EQDMA_CPM5_GLBL_RNG_SZ_D_ADDR 0x234 -#define GLBL_RNG_SZ_D_RSVD_1_MASK GENMASK(31, 16) -#define GLBL_RNG_SZ_D_RING_SIZE_MASK GENMASK(15, 0) -#define EQDMA_CPM5_GLBL_RNG_SZ_E_ADDR 0x238 -#define GLBL_RNG_SZ_E_RSVD_1_MASK GENMASK(31, 16) -#define GLBL_RNG_SZ_E_RING_SIZE_MASK GENMASK(15, 0) -#define EQDMA_CPM5_GLBL_RNG_SZ_F_ADDR 0x23C -#define GLBL_RNG_SZ_F_RSVD_1_MASK GENMASK(31, 16) -#define GLBL_RNG_SZ_F_RING_SIZE_MASK GENMASK(15, 0) -#define EQDMA_CPM5_GLBL_RNG_SZ_10_ADDR 0x240 -#define GLBL_RNG_SZ_10_RSVD_1_MASK GENMASK(31, 16) -#define GLBL_RNG_SZ_10_RING_SIZE_MASK GENMASK(15, 0) -#define EQDMA_CPM5_GLBL_ERR_STAT_ADDR 0x248 -#define GLBL_ERR_STAT_RSVD_1_MASK GENMASK(31, 18) -#define GLBL_ERR_STAT_ERR_FAB_MASK BIT(17) -#define GLBL_ERR_STAT_ERR_H2C_ST_MASK BIT(16) -#define GLBL_ERR_STAT_ERR_BDG_MASK BIT(15) -#define GLBL_ERR_STAT_IND_CTXT_CMD_ERR_MASK GENMASK(14, 9) -#define GLBL_ERR_STAT_ERR_C2H_ST_MASK BIT(8) -#define GLBL_ERR_STAT_ERR_C2H_MM_1_MASK BIT(7) -#define GLBL_ERR_STAT_ERR_C2H_MM_0_MASK BIT(6) -#define GLBL_ERR_STAT_ERR_H2C_MM_1_MASK BIT(5) -#define GLBL_ERR_STAT_ERR_H2C_MM_0_MASK BIT(4) -#define GLBL_ERR_STAT_ERR_TRQ_MASK BIT(3) -#define GLBL_ERR_STAT_ERR_DSC_MASK BIT(2) -#define GLBL_ERR_STAT_ERR_RAM_DBE_MASK BIT(1) -#define GLBL_ERR_STAT_ERR_RAM_SBE_MASK BIT(0) -#define EQDMA_CPM5_GLBL_ERR_MASK_ADDR 0x24C -#define GLBL_ERR_MASK GENMASK(31, 0) -#define EQDMA_CPM5_GLBL_DSC_CFG_ADDR 0x250 -#define GLBL_DSC_CFG_RSVD_1_MASK GENMASK(31, 10) -#define GLBL_DSC_CFG_UNC_OVR_COR_MASK BIT(9) -#define GLBL_DSC_CFG_CTXT_FER_DIS_MASK BIT(8) -#define GLBL_DSC_CFG_RSVD_2_MASK GENMASK(7, 6) -#define GLBL_DSC_CFG_MAXFETCH_MASK GENMASK(5, 3) -#define GLBL_DSC_CFG_WB_ACC_INT_MASK GENMASK(2, 0) -#define EQDMA_CPM5_GLBL_DSC_ERR_STS_ADDR 0x254 -#define GLBL_DSC_ERR_STS_RSVD_1_MASK GENMASK(31, 26) -#define GLBL_DSC_ERR_STS_PORT_ID_MASK BIT(25) -#define GLBL_DSC_ERR_STS_SBE_MASK BIT(24) -#define GLBL_DSC_ERR_STS_DBE_MASK BIT(23) -#define GLBL_DSC_ERR_STS_RQ_CANCEL_MASK BIT(22) -#define GLBL_DSC_ERR_STS_DSC_MASK BIT(21) -#define GLBL_DSC_ERR_STS_DMA_MASK BIT(20) -#define GLBL_DSC_ERR_STS_FLR_CANCEL_MASK BIT(19) -#define GLBL_DSC_ERR_STS_RSVD_2_MASK GENMASK(18, 17) -#define GLBL_DSC_ERR_STS_DAT_POISON_MASK BIT(16) -#define GLBL_DSC_ERR_STS_TIMEOUT_MASK BIT(9) -#define GLBL_DSC_ERR_STS_FLR_MASK BIT(8) -#define GLBL_DSC_ERR_STS_TAG_MASK BIT(6) -#define GLBL_DSC_ERR_STS_ADDR_MASK BIT(5) -#define GLBL_DSC_ERR_STS_PARAM_MASK BIT(4) -#define GLBL_DSC_ERR_STS_BCNT_MASK BIT(3) -#define GLBL_DSC_ERR_STS_UR_CA_MASK BIT(2) -#define GLBL_DSC_ERR_STS_POISON_MASK BIT(1) -#define EQDMA_CPM5_GLBL_DSC_ERR_MSK_ADDR 0x258 -#define GLBL_DSC_ERR_MSK_MASK GENMASK(31, 0) -#define EQDMA_CPM5_GLBL_DSC_ERR_LOG0_ADDR 0x25C -#define GLBL_DSC_ERR_LOG0_VALID_MASK BIT(31) -#define GLBL_DSC_ERR_LOG0_SEL_MASK BIT(30) -#define GLBL_DSC_ERR_LOG0_RSVD_1_MASK GENMASK(29, 13) -#define GLBL_DSC_ERR_LOG0_QID_MASK GENMASK(12, 0) -#define EQDMA_CPM5_GLBL_DSC_ERR_LOG1_ADDR 0x260 -#define GLBL_DSC_ERR_LOG1_RSVD_1_MASK GENMASK(31, 28) -#define GLBL_DSC_ERR_LOG1_CIDX_MASK GENMASK(27, 12) -#define GLBL_DSC_ERR_LOG1_RSVD_2_MASK GENMASK(11, 9) -#define GLBL_DSC_ERR_LOG1_SUB_TYPE_MASK GENMASK(8, 5) -#define GLBL_DSC_ERR_LOG1_ERR_TYPE_MASK GENMASK(4, 0) -#define EQDMA_CPM5_GLBL_TRQ_ERR_STS_ADDR 0x264 -#define GLBL_TRQ_ERR_STS_RSVD_1_MASK GENMASK(31, 8) -#define GLBL_TRQ_ERR_STS_TCP_QSPC_TIMEOUT_MASK BIT(7) -#define GLBL_TRQ_ERR_STS_RSVD_2_MASK BIT(6) -#define GLBL_TRQ_ERR_STS_QID_RANGE_MASK BIT(5) -#define GLBL_TRQ_ERR_STS_QSPC_UNMAPPED_MASK BIT(4) -#define GLBL_TRQ_ERR_STS_TCP_CSR_TIMEOUT_MASK BIT(3) -#define GLBL_TRQ_ERR_STS_RSVD_3_MASK BIT(2) -#define GLBL_TRQ_ERR_STS_VF_ACCESS_ERR_MASK BIT(1) -#define GLBL_TRQ_ERR_STS_CSR_UNMAPPED_MASK BIT(0) -#define EQDMA_CPM5_GLBL_TRQ_ERR_MSK_ADDR 0x268 -#define GLBL_TRQ_ERR_MSK_MASK GENMASK(31, 0) -#define EQDMA_CPM5_GLBL_TRQ_ERR_LOG_ADDR 0x26C -#define GLBL_TRQ_ERR_LOG_SRC_MASK BIT(31) -#define GLBL_TRQ_ERR_LOG_TARGET_MASK GENMASK(30, 27) -#define GLBL_TRQ_ERR_LOG_FUNC_MASK GENMASK(26, 17) -#define GLBL_TRQ_ERR_LOG_ADDRESS_MASK GENMASK(16, 0) -#define EQDMA_CPM5_GLBL_DSC_DBG_DAT0_ADDR 0x270 -#define GLBL_DSC_DAT0_RSVD_1_MASK GENMASK(31, 30) -#define GLBL_DSC_DAT0_CTXT_ARB_DIR_MASK BIT(29) -#define GLBL_DSC_DAT0_CTXT_ARB_QID_MASK GENMASK(28, 17) -#define GLBL_DSC_DAT0_CTXT_ARB_REQ_MASK GENMASK(16, 12) -#define GLBL_DSC_DAT0_IRQ_FIFO_FL_MASK BIT(11) -#define GLBL_DSC_DAT0_TMSTALL_MASK BIT(10) -#define GLBL_DSC_DAT0_RRQ_STALL_MASK GENMASK(9, 8) -#define GLBL_DSC_DAT0_RCP_FIFO_SPC_STALL_MASK GENMASK(7, 6) -#define GLBL_DSC_DAT0_RRQ_FIFO_SPC_STALL_MASK GENMASK(5, 4) -#define GLBL_DSC_DAT0_FAB_MRKR_RSP_STALL_MASK GENMASK(3, 2) -#define GLBL_DSC_DAT0_DSC_OUT_STALL_MASK GENMASK(1, 0) -#define EQDMA_CPM5_GLBL_DSC_DBG_DAT1_ADDR 0x274 -#define GLBL_DSC_DAT1_RSVD_1_MASK GENMASK(31, 28) -#define GLBL_DSC_DAT1_EVT_SPC_C2H_MASK GENMASK(27, 22) -#define GLBL_DSC_DAT1_EVT_SP_H2C_MASK GENMASK(21, 16) -#define GLBL_DSC_DAT1_DSC_SPC_C2H_MASK GENMASK(15, 8) -#define GLBL_DSC_DAT1_DSC_SPC_H2C_MASK GENMASK(7, 0) -#define EQDMA_CPM5_GLBL_DSC_DBG_CTL_ADDR 0x278 -#define GLBL_DSC_CTL_RSVD_1_MASK GENMASK(31, 3) -#define GLBL_DSC_CTL_SELECT_MASK GENMASK(2, 0) -#define EQDMA_CPM5_GLBL_DSC_ERR_LOG2_ADDR 0x27c -#define GLBL_DSC_ERR_LOG2_OLD_PIDX_MASK GENMASK(31, 16) -#define GLBL_DSC_ERR_LOG2_NEW_PIDX_MASK GENMASK(15, 0) -#define EQDMA_CPM5_GLBL_GLBL_INTERRUPT_CFG_ADDR 0x2c4 -#define GLBL_GLBL_INTERRUPT_CFG_RSVD_1_MASK GENMASK(31, 2) -#define GLBL_GLBL_INTERRUPT_CFG_LGCY_INTR_PENDING_MASK BIT(1) -#define GLBL_GLBL_INTERRUPT_CFG_EN_LGCY_INTR_MASK BIT(0) -#define EQDMA_CPM5_GLBL_VCH_HOST_PROFILE_ADDR 0x2c8 -#define GLBL_VCH_HOST_PROFILE_RSVD_1_MASK GENMASK(31, 28) -#define GLBL_VCH_HOST_PROFILE_2C_MM_MASK GENMASK(27, 24) -#define GLBL_VCH_HOST_PROFILE_2C_ST_MASK GENMASK(23, 20) -#define GLBL_VCH_HOST_PROFILE_VCH_DSC_MASK GENMASK(19, 16) -#define GLBL_VCH_HOST_PROFILE_VCH_INT_MSG_MASK GENMASK(15, 12) -#define GLBL_VCH_HOST_PROFILE_VCH_INT_AGGR_MASK GENMASK(11, 8) -#define GLBL_VCH_HOST_PROFILE_VCH_CMPT_MASK GENMASK(7, 4) -#define GLBL_VCH_HOST_PROFILE_VCH_C2H_PLD_MASK GENMASK(3, 0) -#define EQDMA_CPM5_GLBL_BRIDGE_HOST_PROFILE_ADDR 0x308 -#define GLBL_BRIDGE_HOST_PROFILE_RSVD_1_MASK GENMASK(31, 4) -#define GLBL_BRIDGE_HOST_PROFILE_BDGID_MASK GENMASK(3, 0) -#define EQDMA_CPM5_AXIMM_IRQ_DEST_ADDR_ADDR 0x30c -#define AXIMM_IRQ_DEST_ADDR_ADDR_MASK GENMASK(31, 0) -#define EQDMA_CPM5_FAB_ERR_LOG_ADDR 0x314 -#define FAB_ERR_LOG_RSVD_1_MASK GENMASK(31, 7) -#define FAB_ERR_LOG_SRC_MASK GENMASK(6, 0) -#define EQDMA_CPM5_IND_CTXT_DATA_ADDR 0x804 -#define IND_CTXT_DATA_DATA_MASK GENMASK(31, 0) -#define EQDMA_CPM5_IND_CTXT_MASK_ADDR 0x824 -#define IND_CTXT_MASK GENMASK(31, 0) -#define EQDMA_CPM5_IND_CTXT_CMD_ADDR 0x844 -#define IND_CTXT_CMD_RSVD_1_MASK GENMASK(31, 20) -#define IND_CTXT_CMD_QID_MASK GENMASK(19, 7) -#define IND_CTXT_CMD_OP_MASK GENMASK(6, 5) -#define IND_CTXT_CMD_SEL_MASK GENMASK(4, 1) -#define IND_CTXT_CMD_BUSY_MASK BIT(0) -#define EQDMA_CPM5_C2H_TIMER_CNT_ADDR 0xA00 -#define C2H_TIMER_CNT_RSVD_1_MASK GENMASK(31, 16) -#define C2H_TIMER_CNT_MASK GENMASK(15, 0) -#define EQDMA_CPM5_C2H_CNT_TH_ADDR 0xA40 -#define C2H_CNT_TH_RSVD_1_MASK GENMASK(31, 16) -#define C2H_CNT_TH_THESHOLD_CNT_MASK GENMASK(15, 0) -#define EQDMA_CPM5_C2H_STAT_S_AXIS_C2H_ACCEPTED_ADDR 0xA88 -#define C2H_STAT_S_AXIS_C2H_ACCEPTED_RSVD_1_MASK GENMASK(31, 18) -#define C2H_STAT_S_AXIS_C2H_ACCEPTED_MASK GENMASK(17, 0) -#define EQDMA_CPM5_C2H_STAT_S_AXIS_WRB_ACCEPTED_ADDR 0xA8C -#define C2H_STAT_S_AXIS_WRB_ACCEPTED_RSVD_1_MASK GENMASK(31, 18) -#define C2H_STAT_S_AXIS_WRB_ACCEPTED_MASK GENMASK(17, 0) -#define EQDMA_CPM5_C2H_STAT_DESC_RSP_PKT_ACCEPTED_ADDR 0xA90 -#define C2H_STAT_DESC_RSP_PKT_ACCEPTED_RSVD_1_MASK GENMASK(31, 18) -#define C2H_STAT_DESC_RSP_PKT_ACCEPTED_D_MASK GENMASK(17, 0) -#define EQDMA_CPM5_C2H_STAT_AXIS_PKG_CMP_ADDR 0xA94 -#define C2H_STAT_AXIS_PKG_CMP_RSVD_1_MASK GENMASK(31, 18) -#define C2H_STAT_AXIS_PKG_CMP_MASK GENMASK(17, 0) -#define EQDMA_CPM5_C2H_STAT_DESC_RSP_ACCEPTED_ADDR 0xA98 -#define C2H_STAT_DESC_RSP_ACCEPTED_RSVD_1_MASK GENMASK(31, 18) -#define C2H_STAT_DESC_RSP_ACCEPTED_D_MASK GENMASK(17, 0) -#define EQDMA_CPM5_C2H_STAT_DESC_RSP_CMP_ADDR 0xA9C -#define C2H_STAT_DESC_RSP_CMP_RSVD_1_MASK GENMASK(31, 18) -#define C2H_STAT_DESC_RSP_CMP_D_MASK GENMASK(17, 0) -#define EQDMA_CPM5_C2H_STAT_WRQ_OUT_ADDR 0xAA0 -#define C2H_STAT_WRQ_OUT_RSVD_1_MASK GENMASK(31, 18) -#define C2H_STAT_WRQ_OUT_MASK GENMASK(17, 0) -#define EQDMA_CPM5_C2H_STAT_WPL_REN_ACCEPTED_ADDR 0xAA4 -#define C2H_STAT_WPL_REN_ACCEPTED_RSVD_1_MASK GENMASK(31, 18) -#define C2H_STAT_WPL_REN_ACCEPTED_MASK GENMASK(17, 0) -#define EQDMA_CPM5_C2H_STAT_TOTAL_WRQ_LEN_ADDR 0xAA8 -#define C2H_STAT_TOTAL_WRQ_LEN_RSVD_1_MASK GENMASK(31, 18) -#define C2H_STAT_TOTAL_WRQ_LEN_MASK GENMASK(17, 0) -#define EQDMA_CPM5_C2H_STAT_TOTAL_WPL_LEN_ADDR 0xAAC -#define C2H_STAT_TOTAL_WPL_LEN_RSVD_1_MASK GENMASK(31, 18) -#define C2H_STAT_TOTAL_WPL_LEN_MASK GENMASK(17, 0) -#define EQDMA_CPM5_C2H_BUF_SZ_ADDR 0xAB0 -#define C2H_BUF_SZ_IZE_MASK GENMASK(31, 0) -#define EQDMA_CPM5_C2H_ERR_STAT_ADDR 0xAF0 -#define C2H_ERR_STAT_RSVD_1_MASK GENMASK(31, 21) -#define C2H_ERR_STAT_WRB_PORT_ID_ERR_MASK BIT(20) -#define C2H_ERR_STAT_HDR_PAR_ERR_MASK BIT(19) -#define C2H_ERR_STAT_HDR_ECC_COR_ERR_MASK BIT(18) -#define C2H_ERR_STAT_HDR_ECC_UNC_ERR_MASK BIT(17) -#define C2H_ERR_STAT_AVL_RING_DSC_ERR_MASK BIT(16) -#define C2H_ERR_STAT_WRB_PRTY_ERR_MASK BIT(15) -#define C2H_ERR_STAT_WRB_CIDX_ERR_MASK BIT(14) -#define C2H_ERR_STAT_WRB_QFULL_ERR_MASK BIT(13) -#define C2H_ERR_STAT_WRB_INV_Q_ERR_MASK BIT(12) -#define C2H_ERR_STAT_RSVD_2_MASK BIT(11) -#define C2H_ERR_STAT_PORT_ID_CTXT_MISMATCH_MASK BIT(10) -#define C2H_ERR_STAT_ERR_DESC_CNT_MASK BIT(9) -#define C2H_ERR_STAT_RSVD_3_MASK BIT(8) -#define C2H_ERR_STAT_MSI_INT_FAIL_MASK BIT(7) -#define C2H_ERR_STAT_ENG_WPL_DATA_PAR_ERR_MASK BIT(6) -#define C2H_ERR_STAT_RSVD_4_MASK BIT(5) -#define C2H_ERR_STAT_DESC_RSP_ERR_MASK BIT(4) -#define C2H_ERR_STAT_QID_MISMATCH_MASK BIT(3) -#define C2H_ERR_STAT_SH_CMPT_DSC_ERR_MASK BIT(2) -#define C2H_ERR_STAT_LEN_MISMATCH_MASK BIT(1) -#define C2H_ERR_STAT_MTY_MISMATCH_MASK BIT(0) -#define EQDMA_CPM5_C2H_ERR_MASK_ADDR 0xAF4 -#define C2H_ERR_EN_MASK GENMASK(31, 0) -#define EQDMA_CPM5_C2H_FATAL_ERR_STAT_ADDR 0xAF8 -#define C2H_FATAL_ERR_STAT_RSVD_1_MASK GENMASK(31, 21) -#define C2H_FATAL_ERR_STAT_HDR_ECC_UNC_ERR_MASK BIT(20) -#define C2H_FATAL_ERR_STAT_AVL_RING_FIFO_RAM_RDBE_MASK BIT(19) -#define C2H_FATAL_ERR_STAT_WPL_DATA_PAR_ERR_MASK BIT(18) -#define C2H_FATAL_ERR_STAT_PLD_FIFO_RAM_RDBE_MASK BIT(17) -#define C2H_FATAL_ERR_STAT_QID_FIFO_RAM_RDBE_MASK BIT(16) -#define C2H_FATAL_ERR_STAT_CMPT_FIFO_RAM_RDBE_MASK BIT(15) -#define C2H_FATAL_ERR_STAT_WRB_COAL_DATA_RAM_RDBE_MASK BIT(14) -#define C2H_FATAL_ERR_STAT_RESERVED2_MASK BIT(13) -#define C2H_FATAL_ERR_STAT_INT_CTXT_RAM_RDBE_MASK BIT(12) -#define C2H_FATAL_ERR_STAT_DESC_REQ_FIFO_RAM_RDBE_MASK BIT(11) -#define C2H_FATAL_ERR_STAT_PFCH_CTXT_RAM_RDBE_MASK BIT(10) -#define C2H_FATAL_ERR_STAT_WRB_CTXT_RAM_RDBE_MASK BIT(9) -#define C2H_FATAL_ERR_STAT_PFCH_LL_RAM_RDBE_MASK BIT(8) -#define C2H_FATAL_ERR_STAT_TIMER_FIFO_RAM_RDBE_MASK GENMASK(7, 4) -#define C2H_FATAL_ERR_STAT_QID_MISMATCH_MASK BIT(3) -#define C2H_FATAL_ERR_STAT_RESERVED1_MASK BIT(2) -#define C2H_FATAL_ERR_STAT_LEN_MISMATCH_MASK BIT(1) -#define C2H_FATAL_ERR_STAT_MTY_MISMATCH_MASK BIT(0) -#define EQDMA_CPM5_C2H_FATAL_ERR_MASK_ADDR 0xAFC -#define C2H_FATAL_ERR_C2HEN_MASK GENMASK(31, 0) -#define EQDMA_CPM5_C2H_FATAL_ERR_ENABLE_ADDR 0xB00 -#define C2H_FATAL_ERR_ENABLE_RSVD_1_MASK GENMASK(31, 2) -#define C2H_FATAL_ERR_ENABLE_WPL_PAR_INV_MASK BIT(1) -#define C2H_FATAL_ERR_ENABLE_WRQ_DIS_MASK BIT(0) -#define EQDMA_CPM5_GLBL_ERR_INT_ADDR 0xB04 -#define GLBL_ERR_INT_RSVD_1_MASK GENMASK(31, 30) -#define GLBL_ERR_INT_HOST_ID_MASK GENMASK(29, 26) -#define GLBL_ERR_INT_DIS_INTR_ON_VF_MASK BIT(25) -#define GLBL_ERR_INT_ARM_MASK BIT(24) -#define GLBL_ERR_INT_EN_COAL_MASK BIT(23) -#define GLBL_ERR_INT_VEC_MASK GENMASK(22, 12) -#define GLBL_ERR_INT_FUNC_MASK GENMASK(11, 0) -#define EQDMA_CPM5_C2H_PFCH_CFG_ADDR 0xB08 -#define C2H_PFCH_CFG_EVTFL_TH_MASK GENMASK(31, 16) -#define C2H_PFCH_CFG_FL_TH_MASK GENMASK(15, 0) -#define EQDMA_CPM5_C2H_PFCH_CFG_1_ADDR 0xA80 -#define C2H_PFCH_CFG_1_EVT_QCNT_TH_MASK GENMASK(31, 16) -#define C2H_PFCH_CFG_1_QCNT_MASK GENMASK(15, 0) -#define EQDMA_CPM5_C2H_PFCH_CFG_2_ADDR 0xA84 -#define C2H_PFCH_CFG_2_FENCE_MASK BIT(31) -#define C2H_PFCH_CFG_2_RSVD_MASK GENMASK(30, 29) -#define C2H_PFCH_CFG_2_VAR_DESC_NO_DROP_MASK BIT(28) -#define C2H_PFCH_CFG_2_LL_SZ_TH_MASK GENMASK(27, 12) -#define C2H_PFCH_CFG_2_VAR_DESC_NUM_MASK GENMASK(11, 6) -#define C2H_PFCH_CFG_2_NUM_MASK GENMASK(5, 0) -#define EQDMA_CPM5_C2H_INT_TIMER_TICK_ADDR 0xB0C -#define C2H_INT_TIMER_TICK_MASK GENMASK(31, 0) -#define EQDMA_CPM5_C2H_STAT_DESC_RSP_DROP_ACCEPTED_ADDR 0xB10 -#define C2H_STAT_DESC_RSP_DROP_ACCEPTED_RSVD_1_MASK GENMASK(31, 18) -#define C2H_STAT_DESC_RSP_DROP_ACCEPTED_D_MASK GENMASK(17, 0) -#define EQDMA_CPM5_C2H_STAT_DESC_RSP_ERR_ACCEPTED_ADDR 0xB14 -#define C2H_STAT_DESC_RSP_ERR_ACCEPTED_RSVD_1_MASK GENMASK(31, 18) -#define C2H_STAT_DESC_RSP_ERR_ACCEPTED_D_MASK GENMASK(17, 0) -#define EQDMA_CPM5_C2H_STAT_DESC_REQ_ADDR 0xB18 -#define C2H_STAT_DESC_REQ_RSVD_1_MASK GENMASK(31, 18) -#define C2H_STAT_DESC_REQ_MASK GENMASK(17, 0) -#define EQDMA_CPM5_C2H_STAT_DBG_DMA_ENG_0_ADDR 0xB1C -#define C2H_STAT_DMA_ENG_0_S_AXIS_C2H_TVALID_MASK BIT(31) -#define C2H_STAT_DMA_ENG_0_S_AXIS_C2H_TREADY_MASK BIT(30) -#define C2H_STAT_DMA_ENG_0_S_AXIS_WRB_TVALID_MASK GENMASK(29, 27) -#define C2H_STAT_DMA_ENG_0_S_AXIS_WRB_TREADY_MASK GENMASK(26, 24) -#define C2H_STAT_DMA_ENG_0_PLD_FIFO_IN_RDY_MASK BIT(23) -#define C2H_STAT_DMA_ENG_0_QID_FIFO_IN_RDY_MASK BIT(22) -#define C2H_STAT_DMA_ENG_0_ARB_FIFO_OUT_VLD_MASK BIT(21) -#define C2H_STAT_DMA_ENG_0_ARB_FIFO_OUT_QID_MASK GENMASK(20, 9) -#define C2H_STAT_DMA_ENG_0_WRB_FIFO_IN_RDY_MASK BIT(8) -#define C2H_STAT_DMA_ENG_0_WRB_FIFO_OUT_CNT_MASK GENMASK(7, 5) -#define C2H_STAT_DMA_ENG_0_WRB_SM_CS_MASK BIT(4) -#define C2H_STAT_DMA_ENG_0_MAIN_SM_CS_MASK GENMASK(3, 0) -#define EQDMA_CPM5_C2H_STAT_DBG_DMA_ENG_1_ADDR 0xB20 -#define C2H_STAT_DMA_ENG_1_RSVD_1_MASK GENMASK(31, 29) -#define C2H_STAT_DMA_ENG_1_QID_FIFO_OUT_CNT_MASK GENMASK(28, 18) -#define C2H_STAT_DMA_ENG_1_PLD_FIFO_OUT_CNT_MASK GENMASK(17, 7) -#define C2H_STAT_DMA_ENG_1_PLD_ST_FIFO_CNT_MASK GENMASK(6, 0) -#define EQDMA_CPM5_C2H_STAT_DBG_DMA_ENG_2_ADDR 0xB24 -#define C2H_STAT_DMA_ENG_2_RSVD_1_MASK GENMASK(31, 29) -#define C2H_STAT_DMA_ENG_2_QID_FIFO_OUT_CNT_MASK GENMASK(28, 18) -#define C2H_STAT_DMA_ENG_2_PLD_FIFO_OUT_CNT_MASK GENMASK(17, 7) -#define C2H_STAT_DMA_ENG_2_PLD_ST_FIFO_CNT_MASK GENMASK(6, 0) -#define EQDMA_CPM5_C2H_STAT_DBG_DMA_ENG_3_ADDR 0xB28 -#define C2H_STAT_DMA_ENG_3_RSVD_1_MASK GENMASK(31, 24) -#define C2H_STAT_DMA_ENG_3_WRQ_FIFO_OUT_CNT_MASK GENMASK(23, 19) -#define C2H_STAT_DMA_ENG_3_QID_FIFO_OUT_VLD_MASK BIT(18) -#define C2H_STAT_DMA_ENG_3_PLD_FIFO_OUT_VLD_MASK BIT(17) -#define C2H_STAT_DMA_ENG_3_PLD_ST_FIFO_OUT_VLD_MASK BIT(16) -#define C2H_STAT_DMA_ENG_3_PLD_ST_FIFO_OUT_DATA_EOP_MASK BIT(15) -#define C2H_STAT_DMA_ENG_3_PLD_ST_FIFO_OUT_DATA_AVL_IDX_ENABLE_MASK BIT(14) -#define C2H_STAT_DMA_ENG_3_PLD_ST_FIFO_OUT_DATA_DROP_MASK BIT(13) -#define C2H_STAT_DMA_ENG_3_PLD_ST_FIFO_OUT_DATA_ERR_MASK BIT(12) -#define C2H_STAT_DMA_ENG_3_DESC_CNT_FIFO_IN_RDY_MASK BIT(11) -#define C2H_STAT_DMA_ENG_3_DESC_RSP_FIFO_IN_RDY_MASK BIT(10) -#define C2H_STAT_DMA_ENG_3_PLD_PKT_ID_LARGER_0_MASK BIT(9) -#define C2H_STAT_DMA_ENG_3_WRQ_VLD_MASK BIT(8) -#define C2H_STAT_DMA_ENG_3_WRQ_RDY_MASK BIT(7) -#define C2H_STAT_DMA_ENG_3_WRQ_FIFO_OUT_RDY_MASK BIT(6) -#define C2H_STAT_DMA_ENG_3_WRQ_PACKET_OUT_DATA_DROP_MASK BIT(5) -#define C2H_STAT_DMA_ENG_3_WRQ_PACKET_OUT_DATA_ERR_MASK BIT(4) -#define C2H_STAT_DMA_ENG_3_WRQ_PACKET_OUT_DATA_MARKER_MASK BIT(3) -#define C2H_STAT_DMA_ENG_3_WRQ_PACKET_PRE_EOR_MASK BIT(2) -#define C2H_STAT_DMA_ENG_3_WCP_FIFO_IN_RDY_MASK BIT(1) -#define C2H_STAT_DMA_ENG_3_PLD_ST_FIFO_IN_RDY_MASK BIT(0) -#define EQDMA_CPM5_C2H_DBG_PFCH_ERR_CTXT_ADDR 0xB2C -#define C2H_PFCH_ERR_CTXT_RSVD_1_MASK GENMASK(31, 14) -#define C2H_PFCH_ERR_CTXT_ERR_STAT_MASK BIT(13) -#define C2H_PFCH_ERR_CTXT_CMD_WR_MASK BIT(12) -#define C2H_PFCH_ERR_CTXT_QID_MASK GENMASK(11, 1) -#define C2H_PFCH_ERR_CTXT_DONE_MASK BIT(0) -#define EQDMA_CPM5_C2H_FIRST_ERR_QID_ADDR 0xB30 -#define C2H_FIRST_ERR_QID_RSVD_1_MASK GENMASK(31, 21) -#define C2H_FIRST_ERR_QID_ERR_TYPE_MASK GENMASK(20, 16) -#define C2H_FIRST_ERR_QID_RSVD_MASK GENMASK(15, 13) -#define C2H_FIRST_ERR_QID_QID_MASK GENMASK(12, 0) -#define EQDMA_CPM5_STAT_NUM_WRB_IN_ADDR 0xB34 -#define STAT_NUM_WRB_IN_RSVD_1_MASK GENMASK(31, 16) -#define STAT_NUM_WRB_IN_WRB_CNT_MASK GENMASK(15, 0) -#define EQDMA_CPM5_STAT_NUM_WRB_OUT_ADDR 0xB38 -#define STAT_NUM_WRB_OUT_RSVD_1_MASK GENMASK(31, 16) -#define STAT_NUM_WRB_OUT_WRB_CNT_MASK GENMASK(15, 0) -#define EQDMA_CPM5_STAT_NUM_WRB_DRP_ADDR 0xB3C -#define STAT_NUM_WRB_DRP_RSVD_1_MASK GENMASK(31, 16) -#define STAT_NUM_WRB_DRP_WRB_CNT_MASK GENMASK(15, 0) -#define EQDMA_CPM5_STAT_NUM_STAT_DESC_OUT_ADDR 0xB40 -#define STAT_NUM_STAT_DESC_OUT_RSVD_1_MASK GENMASK(31, 16) -#define STAT_NUM_STAT_DESC_OUT_CNT_MASK GENMASK(15, 0) -#define EQDMA_CPM5_STAT_NUM_DSC_CRDT_SENT_ADDR 0xB44 -#define STAT_NUM_DSC_CRDT_SENT_RSVD_1_MASK GENMASK(31, 16) -#define STAT_NUM_DSC_CRDT_SENT_CNT_MASK GENMASK(15, 0) -#define EQDMA_CPM5_STAT_NUM_FCH_DSC_RCVD_ADDR 0xB48 -#define STAT_NUM_FCH_DSC_RCVD_RSVD_1_MASK GENMASK(31, 16) -#define STAT_NUM_FCH_DSC_RCVD_DSC_CNT_MASK GENMASK(15, 0) -#define EQDMA_CPM5_STAT_NUM_BYP_DSC_RCVD_ADDR 0xB4C -#define STAT_NUM_BYP_DSC_RCVD_RSVD_1_MASK GENMASK(31, 11) -#define STAT_NUM_BYP_DSC_RCVD_DSC_CNT_MASK GENMASK(10, 0) -#define EQDMA_CPM5_C2H_WRB_COAL_CFG_ADDR 0xB50 -#define C2H_WRB_COAL_CFG_MAX_BUF_SZ_MASK GENMASK(31, 26) -#define C2H_WRB_COAL_CFG_TICK_VAL_MASK GENMASK(25, 14) -#define C2H_WRB_COAL_CFG_TICK_CNT_MASK GENMASK(13, 2) -#define C2H_WRB_COAL_CFG_SET_GLB_FLUSH_MASK BIT(1) -#define C2H_WRB_COAL_CFG_DONE_GLB_FLUSH_MASK BIT(0) -#define EQDMA_CPM5_C2H_INTR_H2C_REQ_ADDR 0xB54 -#define C2H_INTR_H2C_REQ_RSVD_1_MASK GENMASK(31, 18) -#define C2H_INTR_H2C_REQ_CNT_MASK GENMASK(17, 0) -#define EQDMA_CPM5_C2H_INTR_C2H_MM_REQ_ADDR 0xB58 -#define C2H_INTR_C2H_MM_REQ_RSVD_1_MASK GENMASK(31, 18) -#define C2H_INTR_C2H_MM_REQ_CNT_MASK GENMASK(17, 0) -#define EQDMA_CPM5_C2H_INTR_ERR_INT_REQ_ADDR 0xB5C -#define C2H_INTR_ERR_INT_REQ_RSVD_1_MASK GENMASK(31, 18) -#define C2H_INTR_ERR_INT_REQ_CNT_MASK GENMASK(17, 0) -#define EQDMA_CPM5_C2H_INTR_C2H_ST_REQ_ADDR 0xB60 -#define C2H_INTR_C2H_ST_REQ_RSVD_1_MASK GENMASK(31, 18) -#define C2H_INTR_C2H_ST_REQ_CNT_MASK GENMASK(17, 0) -#define EQDMA_CPM5_C2H_INTR_H2C_ERR_C2H_MM_MSIX_ACK_ADDR 0xB64 -#define C2H_INTR_H2C_ERR_C2H_MM_MSIX_ACK_RSVD_1_MASK GENMASK(31, 18) -#define C2H_INTR_H2C_ERR_C2H_MM_MSIX_ACK_CNT_MASK GENMASK(17, 0) -#define EQDMA_CPM5_C2H_INTR_H2C_ERR_C2H_MM_MSIX_FAIL_ADDR 0xB68 -#define C2H_INTR_H2C_ERR_C2H_MM_MSIX_FAIL_RSVD_1_MASK GENMASK(31, 18) -#define C2H_INTR_H2C_ERR_C2H_MM_MSIX_FAIL_CNT_MASK GENMASK(17, 0) -#define EQDMA_CPM5_C2H_INTR_H2C_ERR_C2H_MM_MSIX_NO_MSIX_ADDR 0xB6C -#define C2H_INTR_H2C_ERR_C2H_MM_MSIX_NO_MSIX_RSVD_1_MASK GENMASK(31, 18) -#define C2H_INTR_H2C_ERR_C2H_MM_MSIX_NO_MSIX_CNT_MASK GENMASK(17, 0) -#define EQDMA_CPM5_C2H_INTR_H2C_ERR_C2H_MM_CTXT_INVAL_ADDR 0xB70 -#define C2H_INTR_H2C_ERR_C2H_MM_CTXT_INVAL_RSVD_1_MASK GENMASK(31, 18) -#define C2H_INTR_H2C_ERR_C2H_MM_CTXT_INVAL_CNT_MASK GENMASK(17, 0) -#define EQDMA_CPM5_C2H_INTR_C2H_ST_MSIX_ACK_ADDR 0xB74 -#define C2H_INTR_C2H_ST_MSIX_ACK_RSVD_1_MASK GENMASK(31, 18) -#define C2H_INTR_C2H_ST_MSIX_ACK_CNT_MASK GENMASK(17, 0) -#define EQDMA_CPM5_C2H_INTR_C2H_ST_MSIX_FAIL_ADDR 0xB78 -#define C2H_INTR_C2H_ST_MSIX_FAIL_RSVD_1_MASK GENMASK(31, 18) -#define C2H_INTR_C2H_ST_MSIX_FAIL_CNT_MASK GENMASK(17, 0) -#define EQDMA_CPM5_C2H_INTR_C2H_ST_NO_MSIX_ADDR 0xB7C -#define C2H_INTR_C2H_ST_NO_MSIX_RSVD_1_MASK GENMASK(31, 18) -#define C2H_INTR_C2H_ST_NO_MSIX_CNT_MASK GENMASK(17, 0) -#define EQDMA_CPM5_C2H_INTR_C2H_ST_CTXT_INVAL_ADDR 0xB80 -#define C2H_INTR_C2H_ST_CTXT_INVAL_RSVD_1_MASK GENMASK(31, 18) -#define C2H_INTR_C2H_ST_CTXT_INVAL_CNT_MASK GENMASK(17, 0) -#define EQDMA_CPM5_C2H_STAT_WR_CMP_ADDR 0xB84 -#define C2H_STAT_WR_CMP_RSVD_1_MASK GENMASK(31, 18) -#define C2H_STAT_WR_CMP_CNT_MASK GENMASK(17, 0) -#define EQDMA_CPM5_C2H_STAT_DBG_DMA_ENG_4_ADDR 0xB88 -#define C2H_STAT_DMA_ENG_4_RSVD_1_MASK GENMASK(31, 24) -#define C2H_STAT_DMA_ENG_4_WRQ_FIFO_OUT_CNT_MASK GENMASK(23, 19) -#define C2H_STAT_DMA_ENG_4_QID_FIFO_OUT_VLD_MASK BIT(18) -#define C2H_STAT_DMA_ENG_4_PLD_FIFO_OUT_VLD_MASK BIT(17) -#define C2H_STAT_DMA_ENG_4_PLD_ST_FIFO_OUT_VLD_MASK BIT(16) -#define C2H_STAT_DMA_ENG_4_PLD_ST_FIFO_OUT_DATA_EOP_MASK BIT(15) -#define C2H_STAT_DMA_ENG_4_PLD_ST_FIFO_OUT_DATA_AVL_IDX_ENABLE_MASK BIT(14) -#define C2H_STAT_DMA_ENG_4_PLD_ST_FIFO_OUT_DATA_DROP_MASK BIT(13) -#define C2H_STAT_DMA_ENG_4_PLD_ST_FIFO_OUT_DATA_ERR_MASK BIT(12) -#define C2H_STAT_DMA_ENG_4_DESC_CNT_FIFO_IN_RDY_MASK BIT(11) -#define C2H_STAT_DMA_ENG_4_DESC_RSP_FIFO_IN_RDY_MASK BIT(10) -#define C2H_STAT_DMA_ENG_4_PLD_PKT_ID_LARGER_0_MASK BIT(9) -#define C2H_STAT_DMA_ENG_4_WRQ_VLD_MASK BIT(8) -#define C2H_STAT_DMA_ENG_4_WRQ_RDY_MASK BIT(7) -#define C2H_STAT_DMA_ENG_4_WRQ_FIFO_OUT_RDY_MASK BIT(6) -#define C2H_STAT_DMA_ENG_4_WRQ_PACKET_OUT_DATA_DROP_MASK BIT(5) -#define C2H_STAT_DMA_ENG_4_WRQ_PACKET_OUT_DATA_ERR_MASK BIT(4) -#define C2H_STAT_DMA_ENG_4_WRQ_PACKET_OUT_DATA_MARKER_MASK BIT(3) -#define C2H_STAT_DMA_ENG_4_WRQ_PACKET_PRE_EOR_MASK BIT(2) -#define C2H_STAT_DMA_ENG_4_WCP_FIFO_IN_RDY_MASK BIT(1) -#define C2H_STAT_DMA_ENG_4_PLD_ST_FIFO_IN_RDY_MASK BIT(0) -#define EQDMA_CPM5_C2H_STAT_DBG_DMA_ENG_5_ADDR 0xB8C -#define C2H_STAT_DMA_ENG_5_RSVD_1_MASK GENMASK(31, 30) -#define C2H_STAT_DMA_ENG_5_WRB_SM_VIRT_CH_MASK BIT(29) -#define C2H_STAT_DMA_ENG_5_WRB_FIFO_IN_REQ_MASK GENMASK(28, 24) -#define C2H_STAT_DMA_ENG_5_ARB_FIFO_OUT_CNT_MASK GENMASK(23, 22) -#define C2H_STAT_DMA_ENG_5_ARB_FIFO_OUT_DATA_LEN_MASK GENMASK(21, 6) -#define C2H_STAT_DMA_ENG_5_ARB_FIFO_OUT_DATA_VIRT_CH_MASK BIT(5) -#define C2H_STAT_DMA_ENG_5_ARB_FIFO_OUT_DATA_VAR_DESC_MASK BIT(4) -#define C2H_STAT_DMA_ENG_5_ARB_FIFO_OUT_DATA_DROP_REQ_MASK BIT(3) -#define C2H_STAT_DMA_ENG_5_ARB_FIFO_OUT_DATA_NUM_BUF_OV_MASK BIT(2) -#define C2H_STAT_DMA_ENG_5_ARB_FIFO_OUT_DATA_MARKER_MASK BIT(1) -#define C2H_STAT_DMA_ENG_5_ARB_FIFO_OUT_DATA_HAS_CMPT_MASK BIT(0) -#define EQDMA_CPM5_C2H_DBG_PFCH_QID_ADDR 0xB90 -#define C2H_PFCH_QID_RSVD_1_MASK GENMASK(31, 16) -#define C2H_PFCH_QID_ERR_CTXT_MASK BIT(15) -#define C2H_PFCH_QID_TARGET_MASK GENMASK(14, 12) -#define C2H_PFCH_QID_QID_OR_TAG_MASK GENMASK(11, 0) -#define EQDMA_CPM5_C2H_DBG_PFCH_ADDR 0xB94 -#define C2H_PFCH_DATA_MASK GENMASK(31, 0) -#define EQDMA_CPM5_C2H_INT_DBG_ADDR 0xB98 -#define C2H_INT_RSVD_1_MASK GENMASK(31, 8) -#define C2H_INT_INT_COAL_SM_MASK GENMASK(7, 4) -#define C2H_INT_INT_SM_MASK GENMASK(3, 0) -#define EQDMA_CPM5_C2H_STAT_IMM_ACCEPTED_ADDR 0xB9C -#define C2H_STAT_IMM_ACCEPTED_RSVD_1_MASK GENMASK(31, 18) -#define C2H_STAT_IMM_ACCEPTED_CNT_MASK GENMASK(17, 0) -#define EQDMA_CPM5_C2H_STAT_MARKER_ACCEPTED_ADDR 0xBA0 -#define C2H_STAT_MARKER_ACCEPTED_RSVD_1_MASK GENMASK(31, 18) -#define C2H_STAT_MARKER_ACCEPTED_CNT_MASK GENMASK(17, 0) -#define EQDMA_CPM5_C2H_STAT_DISABLE_CMP_ACCEPTED_ADDR 0xBA4 -#define C2H_STAT_DISABLE_CMP_ACCEPTED_RSVD_1_MASK GENMASK(31, 18) -#define C2H_STAT_DISABLE_CMP_ACCEPTED_CNT_MASK GENMASK(17, 0) -#define EQDMA_CPM5_C2H_PLD_FIFO_CRDT_CNT_ADDR 0xBA8 -#define C2H_PLD_FIFO_CRDT_CNT_RSVD_1_MASK GENMASK(31, 18) -#define C2H_PLD_FIFO_CRDT_CNT_CNT_MASK GENMASK(17, 0) -#define EQDMA_CPM5_C2H_INTR_DYN_REQ_ADDR 0xBAC -#define C2H_INTR_DYN_REQ_RSVD_1_MASK GENMASK(31, 18) -#define C2H_INTR_DYN_REQ_CNT_MASK GENMASK(17, 0) -#define EQDMA_CPM5_C2H_INTR_DYN_MISC_ADDR 0xBB0 -#define C2H_INTR_DYN_MISC_RSVD_1_MASK GENMASK(31, 18) -#define C2H_INTR_DYN_MISC_CNT_MASK GENMASK(17, 0) -#define EQDMA_CPM5_C2H_DROP_LEN_MISMATCH_ADDR 0xBB4 -#define C2H_DROP_LEN_MISMATCH_RSVD_1_MASK GENMASK(31, 18) -#define C2H_DROP_LEN_MISMATCH_CNT_MASK GENMASK(17, 0) -#define EQDMA_CPM5_C2H_DROP_DESC_RSP_LEN_ADDR 0xBB8 -#define C2H_DROP_DESC_RSP_LEN_RSVD_1_MASK GENMASK(31, 18) -#define C2H_DROP_DESC_RSP_LEN_CNT_MASK GENMASK(17, 0) -#define EQDMA_CPM5_C2H_DROP_QID_FIFO_LEN_ADDR 0xBBC -#define C2H_DROP_QID_FIFO_LEN_RSVD_1_MASK GENMASK(31, 18) -#define C2H_DROP_QID_FIFO_LEN_CNT_MASK GENMASK(17, 0) -#define EQDMA_CPM5_C2H_DROP_PLD_CNT_ADDR 0xBC0 -#define C2H_DROP_PLD_CNT_RSVD_1_MASK GENMASK(31, 18) -#define C2H_DROP_PLD_CNT_CNT_MASK GENMASK(17, 0) -#define EQDMA_CPM5_C2H_CMPT_FORMAT_0_ADDR 0xBC4 -#define C2H_CMPT_FORMAT_0_DESC_ERR_LOC_MASK GENMASK(31, 16) -#define C2H_CMPT_FORMAT_0_COLOR_LOC_MASK GENMASK(15, 0) -#define EQDMA_CPM5_C2H_CMPT_FORMAT_1_ADDR 0xBC8 -#define C2H_CMPT_FORMAT_1_DESC_ERR_LOC_MASK GENMASK(31, 16) -#define C2H_CMPT_FORMAT_1_COLOR_LOC_MASK GENMASK(15, 0) -#define EQDMA_CPM5_C2H_CMPT_FORMAT_2_ADDR 0xBCC -#define C2H_CMPT_FORMAT_2_DESC_ERR_LOC_MASK GENMASK(31, 16) -#define C2H_CMPT_FORMAT_2_COLOR_LOC_MASK GENMASK(15, 0) -#define EQDMA_CPM5_C2H_CMPT_FORMAT_3_ADDR 0xBD0 -#define C2H_CMPT_FORMAT_3_DESC_ERR_LOC_MASK GENMASK(31, 16) -#define C2H_CMPT_FORMAT_3_COLOR_LOC_MASK GENMASK(15, 0) -#define EQDMA_CPM5_C2H_CMPT_FORMAT_4_ADDR 0xBD4 -#define C2H_CMPT_FORMAT_4_DESC_ERR_LOC_MASK GENMASK(31, 16) -#define C2H_CMPT_FORMAT_4_COLOR_LOC_MASK GENMASK(15, 0) -#define EQDMA_CPM5_C2H_CMPT_FORMAT_5_ADDR 0xBD8 -#define C2H_CMPT_FORMAT_5_DESC_ERR_LOC_MASK GENMASK(31, 16) -#define C2H_CMPT_FORMAT_5_COLOR_LOC_MASK GENMASK(15, 0) -#define EQDMA_CPM5_C2H_CMPT_FORMAT_6_ADDR 0xBDC -#define C2H_CMPT_FORMAT_6_DESC_ERR_LOC_MASK GENMASK(31, 16) -#define C2H_CMPT_FORMAT_6_COLOR_LOC_MASK GENMASK(15, 0) -#define EQDMA_CPM5_C2H_PFCH_CACHE_DEPTH_ADDR 0xBE0 -#define C2H_PFCH_CACHE_DEPTH_MAX_STBUF_MASK GENMASK(23, 16) -#define C2H_PFCH_CACHE_DEPTH_MASK GENMASK(7, 0) -#define EQDMA_CPM5_C2H_WRB_COAL_BUF_DEPTH_ADDR 0xBE4 -#define C2H_WRB_COAL_BUF_DEPTH_RSVD_1_MASK GENMASK(31, 8) -#define C2H_WRB_COAL_BUF_DEPTH_BUFFER_MASK GENMASK(7, 0) -#define EQDMA_CPM5_C2H_PFCH_CRDT_ADDR 0xBE8 -#define C2H_PFCH_CRDT_RSVD_1_MASK GENMASK(31, 1) -#define C2H_PFCH_CRDT_RSVD_2_MASK BIT(0) -#define EQDMA_CPM5_C2H_STAT_HAS_CMPT_ACCEPTED_ADDR 0xBEC -#define C2H_STAT_HAS_CMPT_ACCEPTED_RSVD_1_MASK GENMASK(31, 18) -#define C2H_STAT_HAS_CMPT_ACCEPTED_CNT_MASK GENMASK(17, 0) -#define EQDMA_CPM5_C2H_STAT_HAS_PLD_ACCEPTED_ADDR 0xBF0 -#define C2H_STAT_HAS_PLD_ACCEPTED_RSVD_1_MASK GENMASK(31, 18) -#define C2H_STAT_HAS_PLD_ACCEPTED_CNT_MASK GENMASK(17, 0) -#define EQDMA_CPM5_C2H_PLD_PKT_ID_ADDR 0xBF4 -#define C2H_PLD_PKT_ID_CMPT_WAIT_MASK GENMASK(31, 16) -#define C2H_PLD_PKT_ID_DATA_MASK GENMASK(15, 0) -#define EQDMA_CPM5_C2H_PLD_PKT_ID_1_ADDR 0xBF8 -#define C2H_PLD_PKT_ID_1_CMPT_WAIT_MASK GENMASK(31, 16) -#define C2H_PLD_PKT_ID_1_DATA_MASK GENMASK(15, 0) -#define EQDMA_CPM5_C2H_DROP_PLD_CNT_1_ADDR 0xBFC -#define C2H_DROP_PLD_CNT_1_RSVD_1_MASK GENMASK(31, 18) -#define C2H_DROP_PLD_CNT_1_CNT_MASK GENMASK(17, 0) -#define EQDMA_CPM5_H2C_ERR_STAT_ADDR 0xE00 -#define H2C_ERR_STAT_RSVD_1_MASK GENMASK(31, 6) -#define H2C_ERR_STAT_PAR_ERR_MASK BIT(5) -#define H2C_ERR_STAT_SBE_MASK BIT(4) -#define H2C_ERR_STAT_DBE_MASK BIT(3) -#define H2C_ERR_STAT_NO_DMA_DS_MASK BIT(2) -#define H2C_ERR_STAT_SDI_MRKR_REQ_MOP_ERR_MASK BIT(1) -#define H2C_ERR_STAT_ZERO_LEN_DS_MASK BIT(0) -#define EQDMA_CPM5_H2C_ERR_MASK_ADDR 0xE04 -#define H2C_ERR_EN_MASK GENMASK(31, 0) -#define EQDMA_CPM5_H2C_FIRST_ERR_QID_ADDR 0xE08 -#define H2C_FIRST_ERR_QID_RSVD_1_MASK GENMASK(31, 20) -#define H2C_FIRST_ERR_QID_ERR_TYPE_MASK GENMASK(19, 16) -#define H2C_FIRST_ERR_QID_RSVD_2_MASK GENMASK(15, 13) -#define H2C_FIRST_ERR_QID_QID_MASK GENMASK(12, 0) -#define EQDMA_CPM5_H2C_DBG_REG0_ADDR 0xE0C -#define H2C_REG0_NUM_DSC_RCVD_MASK GENMASK(31, 16) -#define H2C_REG0_NUM_WRB_SENT_MASK GENMASK(15, 0) -#define EQDMA_CPM5_H2C_DBG_REG1_ADDR 0xE10 -#define H2C_REG1_NUM_REQ_SENT_MASK GENMASK(31, 16) -#define H2C_REG1_NUM_CMP_SENT_MASK GENMASK(15, 0) -#define EQDMA_CPM5_H2C_DBG_REG2_ADDR 0xE14 -#define H2C_REG2_RSVD_1_MASK GENMASK(31, 16) -#define H2C_REG2_NUM_ERR_DSC_RCVD_MASK GENMASK(15, 0) -#define EQDMA_CPM5_H2C_DBG_REG3_ADDR 0xE18 -#define H2C_REG3_RSVD_1_MASK BIT(31) -#define H2C_REG3_DSCO_FIFO_EMPTY_MASK BIT(30) -#define H2C_REG3_DSCO_FIFO_FULL_MASK BIT(29) -#define H2C_REG3_CUR_RC_STATE_MASK GENMASK(28, 26) -#define H2C_REG3_RDREQ_LINES_MASK GENMASK(25, 16) -#define H2C_REG3_RDATA_LINES_AVAIL_MASK GENMASK(15, 6) -#define H2C_REG3_PEND_FIFO_EMPTY_MASK BIT(5) -#define H2C_REG3_PEND_FIFO_FULL_MASK BIT(4) -#define H2C_REG3_CUR_RQ_STATE_MASK GENMASK(3, 2) -#define H2C_REG3_DSCI_FIFO_FULL_MASK BIT(1) -#define H2C_REG3_DSCI_FIFO_EMPTY_MASK BIT(0) -#define EQDMA_CPM5_H2C_DBG_REG4_ADDR 0xE1C -#define H2C_REG4_RDREQ_ADDR_MASK GENMASK(31, 0) -#define EQDMA_CPM5_H2C_FATAL_ERR_EN_ADDR 0xE20 -#define H2C_FATAL_ERR_EN_RSVD_1_MASK GENMASK(31, 1) -#define H2C_FATAL_ERR_EN_H2C_MASK BIT(0) -#define EQDMA_CPM5_H2C_REQ_THROT_PCIE_ADDR 0xE24 -#define H2C_REQ_THROT_PCIE_EN_REQ_MASK BIT(31) -#define H2C_REQ_THROT_PCIE_MASK GENMASK(30, 19) -#define H2C_REQ_THROT_PCIE_EN_DATA_MASK BIT(18) -#define H2C_REQ_THROT_PCIE_DATA_THRESH_MASK GENMASK(17, 0) -#define EQDMA_CPM5_H2C_ALN_DBG_REG0_ADDR 0xE28 -#define H2C_ALN_REG0_NUM_PKT_SENT_MASK GENMASK(15, 0) -#define EQDMA_CPM5_H2C_REQ_THROT_AXIMM_ADDR 0xE2C -#define H2C_REQ_THROT_AXIMM_EN_REQ_MASK BIT(31) -#define H2C_REQ_THROT_AXIMM_MASK GENMASK(30, 19) -#define H2C_REQ_THROT_AXIMM_EN_DATA_MASK BIT(18) -#define H2C_REQ_THROT_AXIMM_DATA_THRESH_MASK GENMASK(17, 0) -#define EQDMA_CPM5_C2H_MM_CTL_ADDR 0x1004 -#define C2H_MM_CTL_RESERVED1_MASK GENMASK(31, 9) -#define C2H_MM_CTL_ERRC_EN_MASK BIT(8) -#define C2H_MM_CTL_RESERVED0_MASK GENMASK(7, 1) -#define C2H_MM_CTL_RUN_MASK BIT(0) -#define EQDMA_CPM5_C2H_MM_STATUS_ADDR 0x1040 -#define C2H_MM_STATUS_RSVD_1_MASK GENMASK(31, 1) -#define C2H_MM_STATUS_RUN_MASK BIT(0) -#define EQDMA_CPM5_C2H_MM_CMPL_DESC_CNT_ADDR 0x1048 -#define C2H_MM_CMPL_DESC_CNT_C2H_CO_MASK GENMASK(31, 0) -#define EQDMA_CPM5_C2H_MM_ERR_CODE_ENABLE_MASK_ADDR 0x1054 -#define C2H_MM_ERR_CODE_ENABLE_RESERVED1_MASK BIT(31) -#define C2H_MM_ERR_CODE_ENABLE_WR_UC_RAM_MASK BIT(30) -#define C2H_MM_ERR_CODE_ENABLE_WR_UR_MASK BIT(29) -#define C2H_MM_ERR_CODE_ENABLE_WR_FLR_MASK BIT(28) -#define C2H_MM_ERR_CODE_ENABLE_RESERVED0_MASK GENMASK(27, 2) -#define C2H_MM_ERR_CODE_ENABLE_RD_SLV_ERR_MASK BIT(1) -#define C2H_MM_ERR_CODE_ENABLE_WR_SLV_ERR_MASK BIT(0) -#define EQDMA_CPM5_C2H_MM_ERR_CODE_ADDR 0x1058 -#define C2H_MM_ERR_CODE_RESERVED1_MASK GENMASK(31, 28) -#define C2H_MM_ERR_CODE_CIDX_MASK GENMASK(27, 12) -#define C2H_MM_ERR_CODE_RESERVED0_MASK GENMASK(11, 10) -#define C2H_MM_ERR_CODE_SUB_TYPE_MASK GENMASK(9, 5) -#define C2H_MM_ERR_CODE_MASK GENMASK(4, 0) -#define EQDMA_CPM5_C2H_MM_ERR_INFO_ADDR 0x105C -#define C2H_MM_ERR_INFO_VALID_MASK BIT(31) -#define C2H_MM_ERR_INFO_SEL_MASK BIT(30) -#define C2H_MM_ERR_INFO_RSVD_1_MASK GENMASK(29, 24) -#define C2H_MM_ERR_INFO_QID_MASK GENMASK(23, 0) -#define EQDMA_CPM5_C2H_MM_PERF_MON_CTL_ADDR 0x10C0 -#define C2H_MM_PERF_MON_CTL_RSVD_1_MASK GENMASK(31, 4) -#define C2H_MM_PERF_MON_CTL_IMM_START_MASK BIT(3) -#define C2H_MM_PERF_MON_CTL_RUN_START_MASK BIT(2) -#define C2H_MM_PERF_MON_CTL_IMM_CLEAR_MASK BIT(1) -#define C2H_MM_PERF_MON_CTL_RUN_CLEAR_MASK BIT(0) -#define EQDMA_CPM5_C2H_MM_PERF_MON_CYCLE_CNT0_ADDR 0x10C4 -#define C2H_MM_PERF_MON_CYCLE_CNT0_CYC_CNT_MASK GENMASK(31, 0) -#define EQDMA_CPM5_C2H_MM_PERF_MON_CYCLE_CNT1_ADDR 0x10C8 -#define C2H_MM_PERF_MON_CYCLE_CNT1_RSVD_1_MASK GENMASK(31, 10) -#define C2H_MM_PERF_MON_CYCLE_CNT1_CYC_CNT_MASK GENMASK(9, 0) -#define EQDMA_CPM5_C2H_MM_PERF_MON_DATA_CNT0_ADDR 0x10CC -#define C2H_MM_PERF_MON_DATA_CNT0_DCNT_MASK GENMASK(31, 0) -#define EQDMA_CPM5_C2H_MM_PERF_MON_DATA_CNT1_ADDR 0x10D0 -#define C2H_MM_PERF_MON_DATA_CNT1_RSVD_1_MASK GENMASK(31, 10) -#define C2H_MM_PERF_MON_DATA_CNT1_DCNT_MASK GENMASK(9, 0) -#define EQDMA_CPM5_C2H_MM_DBG_ADDR 0x10E8 -#define C2H_MM_RSVD_1_MASK GENMASK(31, 24) -#define C2H_MM_RRQ_ENTRIES_MASK GENMASK(23, 17) -#define C2H_MM_DAT_FIFO_SPC_MASK GENMASK(16, 7) -#define C2H_MM_RD_STALL_MASK BIT(6) -#define C2H_MM_RRQ_FIFO_FI_MASK BIT(5) -#define C2H_MM_WR_STALL_MASK BIT(4) -#define C2H_MM_WRQ_FIFO_FI_MASK BIT(3) -#define C2H_MM_WBK_STALL_MASK BIT(2) -#define C2H_MM_DSC_FIFO_EP_MASK BIT(1) -#define C2H_MM_DSC_FIFO_FL_MASK BIT(0) -#define EQDMA_CPM5_H2C_MM_CTL_ADDR 0x1204 -#define H2C_MM_CTL_RESERVED1_MASK GENMASK(31, 9) -#define H2C_MM_CTL_ERRC_EN_MASK BIT(8) -#define H2C_MM_CTL_RESERVED0_MASK GENMASK(7, 1) -#define H2C_MM_CTL_RUN_MASK BIT(0) -#define EQDMA_CPM5_H2C_MM_STATUS_ADDR 0x1240 -#define H2C_MM_STATUS_RSVD_1_MASK GENMASK(31, 1) -#define H2C_MM_STATUS_RUN_MASK BIT(0) -#define EQDMA_CPM5_H2C_MM_CMPL_DESC_CNT_ADDR 0x1248 -#define H2C_MM_CMPL_DESC_CNT_H2C_CO_MASK GENMASK(31, 0) -#define EQDMA_CPM5_H2C_MM_ERR_CODE_ENABLE_MASK_ADDR 0x1254 -#define H2C_MM_ERR_CODE_ENABLE_RESERVED5_MASK GENMASK(31, 30) -#define H2C_MM_ERR_CODE_ENABLE_WR_SLV_ERR_MASK BIT(29) -#define H2C_MM_ERR_CODE_ENABLE_WR_DEC_ERR_MASK BIT(28) -#define H2C_MM_ERR_CODE_ENABLE_RESERVED4_MASK GENMASK(27, 23) -#define H2C_MM_ERR_CODE_ENABLE_RD_RQ_DIS_ERR_MASK BIT(22) -#define H2C_MM_ERR_CODE_ENABLE_RESERVED3_MASK GENMASK(21, 17) -#define H2C_MM_ERR_CODE_ENABLE_RD_DAT_POISON_ERR_MASK BIT(16) -#define H2C_MM_ERR_CODE_ENABLE_RESERVED2_MASK GENMASK(15, 9) -#define H2C_MM_ERR_CODE_ENABLE_RD_FLR_ERR_MASK BIT(8) -#define H2C_MM_ERR_CODE_ENABLE_RESERVED1_MASK GENMASK(7, 6) -#define H2C_MM_ERR_CODE_ENABLE_RD_HDR_ADR_ERR_MASK BIT(5) -#define H2C_MM_ERR_CODE_ENABLE_RD_HDR_PARA_MASK BIT(4) -#define H2C_MM_ERR_CODE_ENABLE_RD_HDR_BYTE_ERR_MASK BIT(3) -#define H2C_MM_ERR_CODE_ENABLE_RD_UR_CA_MASK BIT(2) -#define H2C_MM_ERR_CODE_ENABLE_RD_HRD_POISON_ERR_MASK BIT(1) -#define H2C_MM_ERR_CODE_ENABLE_RESERVED0_MASK BIT(0) -#define EQDMA_CPM5_H2C_MM_ERR_CODE_ADDR 0x1258 -#define H2C_MM_ERR_CODE_RSVD_1_MASK GENMASK(31, 28) -#define H2C_MM_ERR_CODE_CIDX_MASK GENMASK(27, 12) -#define H2C_MM_ERR_CODE_RESERVED0_MASK GENMASK(11, 10) -#define H2C_MM_ERR_CODE_SUB_TYPE_MASK GENMASK(9, 5) -#define H2C_MM_ERR_CODE_MASK GENMASK(4, 0) -#define EQDMA_CPM5_H2C_MM_ERR_INFO_ADDR 0x125C -#define H2C_MM_ERR_INFO_VALID_MASK BIT(31) -#define H2C_MM_ERR_INFO_SEL_MASK BIT(30) -#define H2C_MM_ERR_INFO_RSVD_1_MASK GENMASK(29, 24) -#define H2C_MM_ERR_INFO_QID_MASK GENMASK(23, 0) -#define EQDMA_CPM5_H2C_MM_PERF_MON_CTL_ADDR 0x12C0 -#define H2C_MM_PERF_MON_CTL_RSVD_1_MASK GENMASK(31, 4) -#define H2C_MM_PERF_MON_CTL_IMM_START_MASK BIT(3) -#define H2C_MM_PERF_MON_CTL_RUN_START_MASK BIT(2) -#define H2C_MM_PERF_MON_CTL_IMM_CLEAR_MASK BIT(1) -#define H2C_MM_PERF_MON_CTL_RUN_CLEAR_MASK BIT(0) -#define EQDMA_CPM5_H2C_MM_PERF_MON_CYCLE_CNT0_ADDR 0x12C4 -#define H2C_MM_PERF_MON_CYCLE_CNT0_CYC_CNT_MASK GENMASK(31, 0) -#define EQDMA_CPM5_H2C_MM_PERF_MON_CYCLE_CNT1_ADDR 0x12C8 -#define H2C_MM_PERF_MON_CYCLE_CNT1_RSVD_1_MASK GENMASK(31, 10) -#define H2C_MM_PERF_MON_CYCLE_CNT1_CYC_CNT_MASK GENMASK(9, 0) -#define EQDMA_CPM5_H2C_MM_PERF_MON_DATA_CNT0_ADDR 0x12CC -#define H2C_MM_PERF_MON_DATA_CNT0_DCNT_MASK GENMASK(31, 0) -#define EQDMA_CPM5_H2C_MM_PERF_MON_DATA_CNT1_ADDR 0x12D0 -#define H2C_MM_PERF_MON_DATA_CNT1_RSVD_1_MASK GENMASK(31, 10) -#define H2C_MM_PERF_MON_DATA_CNT1_DCNT_MASK GENMASK(9, 0) -#define EQDMA_CPM5_H2C_MM_DBG_ADDR 0x12E8 -#define H2C_MM_RSVD_1_MASK GENMASK(31, 24) -#define H2C_MM_RRQ_ENTRIES_MASK GENMASK(23, 17) -#define H2C_MM_DAT_FIFO_SPC_MASK GENMASK(16, 7) -#define H2C_MM_RD_STALL_MASK BIT(6) -#define H2C_MM_RRQ_FIFO_FI_MASK BIT(5) -#define H2C_MM_WR_STALL_MASK BIT(4) -#define H2C_MM_WRQ_FIFO_FI_MASK BIT(3) -#define H2C_MM_WBK_STALL_MASK BIT(2) -#define H2C_MM_DSC_FIFO_EP_MASK BIT(1) -#define H2C_MM_DSC_FIFO_FL_MASK BIT(0) -#define EQDMA_CPM5_C2H_CRDT_COAL_CFG_1_ADDR 0x1400 -#define C2H_CRDT_COAL_CFG_1_RSVD_1_MASK GENMASK(31, 18) -#define C2H_CRDT_COAL_CFG_1_PLD_FIFO_TH_MASK GENMASK(17, 10) -#define C2H_CRDT_COAL_CFG_1_TIMER_TH_MASK GENMASK(9, 0) -#define EQDMA_CPM5_C2H_CRDT_COAL_CFG_2_ADDR 0x1404 -#define C2H_CRDT_COAL_CFG_2_RSVD_1_MASK GENMASK(31, 24) -#define C2H_CRDT_COAL_CFG_2_FIFO_TH_MASK GENMASK(23, 16) -#define C2H_CRDT_COAL_CFG_2_RESERVED1_MASK GENMASK(15, 11) -#define C2H_CRDT_COAL_CFG_2_NT_TH_MASK GENMASK(10, 0) -#define EQDMA_CPM5_C2H_PFCH_BYP_QID_ADDR 0x1408 -#define C2H_PFCH_BYP_QID_RSVD_1_MASK GENMASK(31, 12) -#define C2H_PFCH_BYP_QID_MASK GENMASK(11, 0) -#define EQDMA_CPM5_C2H_PFCH_BYP_TAG_ADDR 0x140C -#define C2H_PFCH_BYP_TAG_RSVD_1_MASK GENMASK(31, 20) -#define C2H_PFCH_BYP_TAG_BYP_QID_MASK GENMASK(19, 8) -#define C2H_PFCH_BYP_TAG_RSVD_2_MASK BIT(7) -#define C2H_PFCH_BYP_TAG_MASK GENMASK(6, 0) -#define EQDMA_CPM5_C2H_WATER_MARK_ADDR 0x1500 -#define C2H_WATER_MARK_HIGH_WM_MASK GENMASK(31, 16) -#define C2H_WATER_MARK_LOW_WM_MASK GENMASK(15, 0) -#define EQDMA_CPM5_C2H_NOTIFY_EMPTY_ADDR 0x1800 -#define C2H_NOTIFY_EMPTY_RSVD_1_MASK GENMASK(31, 16) -#define C2H_NOTIFY_EMPTY_NOE_MASK GENMASK(15, 0) -#define EQDMA_CPM5_C2H_STAT_S_AXIS_C2H_ACCEPTED_1_ADDR 0x1804 -#define C2H_STAT_S_AXIS_C2H_ACCEPTED_1_MASK GENMASK(31, 0) -#define EQDMA_CPM5_C2H_STAT_S_AXIS_WRB_ACCEPTED_1_ADDR 0x1808 -#define C2H_STAT_S_AXIS_WRB_ACCEPTED_1_MASK GENMASK(31, 0) -#define EQDMA_CPM5_C2H_STAT_DESC_RSP_PKT_ACCEPTED_1_ADDR 0x180C -#define C2H_STAT_DESC_RSP_PKT_ACCEPTED_1_D_MASK GENMASK(31, 0) -#define EQDMA_CPM5_C2H_STAT_AXIS_PKG_CMP_1_ADDR 0x1810 -#define C2H_STAT_AXIS_PKG_CMP_1_MASK GENMASK(31, 0) -#define EQDMA_CPM5_C2H_STAT_S_AXIS_WRB_ACCEPTED_2_ADDR 0x1814 -#define C2H_STAT_S_AXIS_WRB_ACCEPTED_2_MASK GENMASK(31, 0) -#define EQDMA_CPM5_C2H_ST_PLD_FIFO_DEPTH_ADDR 0x1818 -#define C2H_ST_PLD_FIFO_DEPTH_MASK GENMASK(31, 0) -#define SW_IND_CTXT_DATA_W7_VIRTIO_DSC_BASE_H_MASK GENMASK(10, 0) -#define SW_IND_CTXT_DATA_W6_VIRTIO_DSC_BASE_M_MASK GENMASK(31, 0) -#define SW_IND_CTXT_DATA_W5_VIRTIO_DSC_BASE_L_MASK GENMASK(31, 11) -#define SW_IND_CTXT_DATA_W5_PASID_EN_MASK BIT(10) -#define SW_IND_CTXT_DATA_W5_PASID_H_MASK GENMASK(9, 0) -#define SW_IND_CTXT_DATA_W4_PASID_L_MASK GENMASK(31, 20) -#define SW_IND_CTXT_DATA_W4_HOST_ID_MASK GENMASK(19, 16) -#define SW_IND_CTXT_DATA_W4_IRQ_BYP_MASK BIT(15) -#define SW_IND_CTXT_DATA_W4_PACK_BYP_OUT_MASK BIT(14) -#define SW_IND_CTXT_DATA_W4_VIRTIO_EN_MASK BIT(13) -#define SW_IND_CTXT_DATA_W4_DIS_INTR_ON_VF_MASK BIT(12) -#define SW_IND_CTXT_DATA_W4_INT_AGGR_MASK BIT(11) -#define SW_IND_CTXT_DATA_W4_VEC_MASK GENMASK(10, 0) -#define SW_IND_CTXT_DATA_W3_DSC_BASE_H_MASK GENMASK(31, 0) -#define SW_IND_CTXT_DATA_W2_DSC_BASE_L_MASK GENMASK(31, 0) -#define SW_IND_CTXT_DATA_W1_IS_MM_MASK BIT(31) -#define SW_IND_CTXT_DATA_W1_MRKR_DIS_MASK BIT(30) -#define SW_IND_CTXT_DATA_W1_IRQ_REQ_MASK BIT(29) -#define SW_IND_CTXT_DATA_W1_ERR_WB_SENT_MASK BIT(28) -#define SW_IND_CTXT_DATA_W1_ERR_MASK GENMASK(27, 26) -#define SW_IND_CTXT_DATA_W1_IRQ_NO_LAST_MASK BIT(25) -#define SW_IND_CTXT_DATA_W1_PORT_ID_MASK GENMASK(24, 22) -#define SW_IND_CTXT_DATA_W1_IRQ_EN_MASK BIT(21) -#define SW_IND_CTXT_DATA_W1_WBK_EN_MASK BIT(20) -#define SW_IND_CTXT_DATA_W1_MM_CHN_MASK BIT(19) -#define SW_IND_CTXT_DATA_W1_BYPASS_MASK BIT(18) -#define SW_IND_CTXT_DATA_W1_DSC_SZ_MASK GENMASK(17, 16) -#define SW_IND_CTXT_DATA_W1_RNG_SZ_MASK GENMASK(15, 12) -#define SW_IND_CTXT_DATA_W1_RSVD_1_MASK GENMASK(11, 9) -#define SW_IND_CTXT_DATA_W1_FETCH_MAX_MASK GENMASK(8, 5) -#define SW_IND_CTXT_DATA_W1_AT_MASK BIT(4) -#define SW_IND_CTXT_DATA_W1_WBI_INTVL_EN_MASK BIT(3) -#define SW_IND_CTXT_DATA_W1_WBI_CHK_MASK BIT(2) -#define SW_IND_CTXT_DATA_W1_FCRD_EN_MASK BIT(1) -#define SW_IND_CTXT_DATA_W1_QEN_MASK BIT(0) -#define SW_IND_CTXT_DATA_W0_RSV_MASK GENMASK(31, 29) -#define SW_IND_CTXT_DATA_W0_FNC_MASK GENMASK(28, 17) -#define SW_IND_CTXT_DATA_W0_IRQ_ARM_MASK BIT(16) -#define SW_IND_CTXT_DATA_W0_PIDX_MASK GENMASK(15, 0) -#define HW_IND_CTXT_DATA_W1_RSVD_1_MASK BIT(15) -#define HW_IND_CTXT_DATA_W1_FETCH_PND_MASK GENMASK(14, 11) -#define HW_IND_CTXT_DATA_W1_EVT_PND_MASK BIT(10) -#define HW_IND_CTXT_DATA_W1_IDL_STP_B_MASK BIT(9) -#define HW_IND_CTXT_DATA_W1_DSC_PND_MASK BIT(8) -#define HW_IND_CTXT_DATA_W1_RSVD_2_MASK GENMASK(7, 0) -#define HW_IND_CTXT_DATA_W0_CRD_USE_MASK GENMASK(31, 16) -#define HW_IND_CTXT_DATA_W0_CIDX_MASK GENMASK(15, 0) -#define CRED_CTXT_DATA_W0_RSVD_1_MASK GENMASK(31, 16) -#define CRED_CTXT_DATA_W0_CREDT_MASK GENMASK(15, 0) -#define PREFETCH_CTXT_DATA_W1_VALID_MASK BIT(13) -#define PREFETCH_CTXT_DATA_W1_SW_CRDT_H_MASK GENMASK(12, 0) -#define PREFETCH_CTXT_DATA_W0_SW_CRDT_L_MASK GENMASK(31, 29) -#define PREFETCH_CTXT_DATA_W0_PFCH_MASK BIT(28) -#define PREFETCH_CTXT_DATA_W0_PFCH_EN_MASK BIT(27) -#define PREFETCH_CTXT_DATA_W0_ERR_MASK BIT(26) -#define PREFETCH_CTXT_DATA_W0_RSVD_MASK GENMASK(25, 22) -#define PREFETCH_CTXT_DATA_W0_PFCH_NEED_MASK GENMASK(21, 16) -#define PREFETCH_CTXT_DATA_W0_NUM_PFCH_MASK GENMASK(15, 10) -#define PREFETCH_CTXT_DATA_W0_VIRTIO_MASK BIT(9) -#define PREFETCH_CTXT_DATA_W0_VAR_DESC_MASK BIT(8) -#define PREFETCH_CTXT_DATA_W0_PORT_ID_MASK GENMASK(7, 5) -#define PREFETCH_CTXT_DATA_W0_BUF_SZ_IDX_MASK GENMASK(4, 1) -#define PREFETCH_CTXT_DATA_W0_BYPASS_MASK BIT(0) -#define CMPL_CTXT_DATA_W6_RSVD_1_H_MASK GENMASK(7, 0) -#define CMPL_CTXT_DATA_W5_RSVD_1_L_MASK GENMASK(31, 23) -#define CMPL_CTXT_DATA_W5_PORT_ID_MASK GENMASK(22, 20) -#define CMPL_CTXT_DATA_W5_SH_CMPT_MASK BIT(19) -#define CMPL_CTXT_DATA_W5_VIO_EOP_MASK BIT(18) -#define CMPL_CTXT_DATA_W5_BADDR4_LOW_MASK GENMASK(17, 14) -#define CMPL_CTXT_DATA_W5_PASID_EN_MASK BIT(13) -#define CMPL_CTXT_DATA_W5_PASID_H_MASK GENMASK(12, 0) -#define CMPL_CTXT_DATA_W4_PASID_L_MASK GENMASK(31, 23) -#define CMPL_CTXT_DATA_W4_HOST_ID_MASK GENMASK(22, 19) -#define CMPL_CTXT_DATA_W4_DIR_C2H_MASK BIT(18) -#define CMPL_CTXT_DATA_W4_VIO_MASK BIT(17) -#define CMPL_CTXT_DATA_W4_DIS_INTR_ON_VF_MASK BIT(16) -#define CMPL_CTXT_DATA_W4_INT_AGGR_MASK BIT(15) -#define CMPL_CTXT_DATA_W4_VEC_MASK GENMASK(14, 4) -#define CMPL_CTXT_DATA_W4_AT_MASK BIT(3) -#define CMPL_CTXT_DATA_W4_OVF_CHK_DIS_MASK BIT(2) -#define CMPL_CTXT_DATA_W4_FULL_UPD_MASK BIT(1) -#define CMPL_CTXT_DATA_W4_TIMER_RUNNING_MASK BIT(0) -#define CMPL_CTXT_DATA_W3_USER_TRIG_PEND_MASK BIT(31) -#define CMPL_CTXT_DATA_W3_ERR_MASK GENMASK(30, 29) -#define CMPL_CTXT_DATA_W3_VALID_MASK BIT(28) -#define CMPL_CTXT_DATA_W3_CIDX_MASK GENMASK(27, 12) -#define CMPL_CTXT_DATA_W3_PIDX_H_MASK GENMASK(11, 0) -#define CMPL_CTXT_DATA_W2_PIDX_L_MASK GENMASK(31, 28) -#define CMPL_CTXT_DATA_W2_DESC_SIZE_MASK GENMASK(27, 26) -#define CMPL_CTXT_DATA_W2_BADDR4_HIGH_H_MASK GENMASK(25, 0) -#define CMPL_CTXT_DATA_W1_BADDR4_HIGH_L_MASK GENMASK(31, 0) -#define CMPL_CTXT_DATA_W0_QSIZE_IX_MASK GENMASK(31, 28) -#define CMPL_CTXT_DATA_W0_COLOR_MASK BIT(27) -#define CMPL_CTXT_DATA_W0_INT_ST_MASK GENMASK(26, 25) -#define CMPL_CTXT_DATA_W0_TIMER_IX_MASK GENMASK(24, 21) -#define CMPL_CTXT_DATA_W0_CNTER_IX_MASK GENMASK(20, 17) -#define CMPL_CTXT_DATA_W0_FNC_ID_MASK GENMASK(16, 5) -#define CMPL_CTXT_DATA_W0_TRIG_MODE_MASK GENMASK(4, 2) -#define CMPL_CTXT_DATA_W0_EN_INT_MASK BIT(1) -#define CMPL_CTXT_DATA_W0_EN_STAT_DESC_MASK BIT(0) -#define INTR_CTXT_DATA_W3_FUNC_MASK GENMASK(29, 18) -#define INTR_CTXT_DATA_W3_RSVD_MASK GENMASK(17, 14) -#define INTR_CTXT_DATA_W3_PASID_EN_MASK BIT(13) -#define INTR_CTXT_DATA_W3_PASID_H_MASK GENMASK(12, 0) -#define INTR_CTXT_DATA_W2_PASID_L_MASK GENMASK(31, 23) -#define INTR_CTXT_DATA_W2_HOST_ID_MASK GENMASK(22, 19) -#define INTR_CTXT_DATA_W2_AT_MASK BIT(18) -#define INTR_CTXT_DATA_W2_PIDX_MASK GENMASK(17, 6) -#define INTR_CTXT_DATA_W2_PAGE_SIZE_MASK GENMASK(5, 3) -#define INTR_CTXT_DATA_W2_BADDR_4K_H_MASK GENMASK(2, 0) -#define INTR_CTXT_DATA_W1_BADDR_4K_M_MASK GENMASK(31, 0) -#define INTR_CTXT_DATA_W0_BADDR_4K_L_MASK GENMASK(31, 15) -#define INTR_CTXT_DATA_W0_COLOR_MASK BIT(14) -#define INTR_CTXT_DATA_W0_INT_ST_MASK BIT(13) -#define INTR_CTXT_DATA_W0_RSVD1_MASK BIT(12) -#define INTR_CTXT_DATA_W0_VEC_MASK GENMASK(11, 1) -#define INTR_CTXT_DATA_W0_VALID_MASK BIT(0) -#define HOSTID_TABLE_W6_SMID_MASK GENMASK(9, 0) -#define HOSTID_TABLE_W5_H2C_MM_AWPROT_MASK GENMASK(27, 26) -#define HOSTID_TABLE_W5_H2C_MM_AWCACHE_MASK GENMASK(25, 22) -#define HOSTID_TABLE_W5_H2C_MM_AWSTEERING_MASK GENMASK(20, 18) -#define HOSTID_TABLE_W5_DSC_AWPROT_MASK GENMASK(17, 16) -#define HOSTID_TABLE_W5_DSC_AWCACHE_MASK GENMASK(15, 12) -#define HOSTID_TABLE_W5_DSC_AWSTEERING_MASK GENMASK(11, 8) -#define HOSTID_TABLE_W5_INT_MSG_AWPROT_MASK GENMASK(7, 6) -#define HOSTID_TABLE_W5_INT_MSG_AWCACHE_MASK GENMASK(5, 2) -#define HOSTID_TABLE_W5_INT_MSG_AWSTEERING_H_MASK GENMASK(0, 0) -#define HOSTID_TABLE_W4_INT_MSG_AWSTEERING_L_MASK GENMASK(31, 30) -#define HOSTID_TABLE_W4_INT_AGGR_AWPROT_MASK GENMASK(29, 28) -#define HOSTID_TABLE_W4_INT_AGGR_AWCACHE_MASK GENMASK(27, 24) -#define HOSTID_TABLE_W4_INT_AGGR_AWSTEERING_MASK GENMASK(22, 20) -#define HOSTID_TABLE_W4_CMPT_AWPROT_MASK GENMASK(19, 18) -#define HOSTID_TABLE_W4_CMPT_AWCACHE_MASK GENMASK(17, 14) -#define HOSTID_TABLE_W4_CMPT_AWSTEERING_MASK GENMASK(12, 10) -#define HOSTID_TABLE_W4_C2H_PLD_AWPROT_MASK GENMASK(9, 8) -#define HOSTID_TABLE_W4_C2H_PLD_AWCACHE_MASK GENMASK(7, 4) -#define HOSTID_TABLE_W4_C2H_PLD_AWSTEERING_MASK GENMASK(2, 0) -#define HOSTID_TABLE_W3_C2H_MM_ARPROT_MASK GENMASK(7, 6) -#define HOSTID_TABLE_W3_C2H_MM_ARCACHE_MASK GENMASK(5, 2) -#define HOSTID_TABLE_W3_C2H_MM_ARSTEERING_H_MASK GENMASK(0, 0) -#define HOSTID_TABLE_W2_C2H_MM_ARSTEERING_L_MASK GENMASK(31, 30) -#define HOSTID_TABLE_W2_H2C_MM_ARPROT_MASK GENMASK(29, 28) -#define HOSTID_TABLE_W2_H2C_MM_ARCACHE_MASK GENMASK(27, 24) -#define HOSTID_TABLE_W2_H2C_MM_ARSTEERING_MASK GENMASK(22, 20) -#define HOSTID_TABLE_W2_H2C_ST_ARPROT_MASK GENMASK(19, 18) -#define HOSTID_TABLE_W2_H2C_ST_ARCACHE_MASK GENMASK(17, 14) -#define HOSTID_TABLE_W2_H2C_ST_ARSTEERING_MASK GENMASK(12, 10) -#define HOSTID_TABLE_W2_DSC_ARPOT_MASK GENMASK(9, 8) -#define HOSTID_TABLE_W2_DSC_ARCACHE_MASK GENMASK(7, 4) -#define HOSTID_TABLE_W2_DSC_ARSTEERING_MASK GENMASK(2, 0) -#define HOSTID_TABLE_W0_VCH_H2C_MM_MASK GENMASK(27, 24) -#define HOSTID_TABLE_W0_VCH_H2C_ST_MASK GENMASK(23, 20) -#define HOSTID_TABLE_W0_VCH_DSC_MASK GENMASK(19, 16) -#define HOSTID_TABLE_W0_VCH_INT_MSG_MASK GENMASK(15, 12) -#define HOSTID_TABLE_W0_VCH_INT_AGGR_MASK GENMASK(11, 8) -#define HOSTID_TABLE_W0_VCH_CMPT_MASK GENMASK(7, 4) -#define HOSTID_TABLE_W0_VCH_H2C_PLD_MASK GENMASK(3, 0) -#define CTXT_SELC_FNC_STS_W0_MSIX_MASK GENMASK(3, 3) -#define CTXT_SELC_FNC_STS_W0_MSIX_ENABLE_MASK GENMASK(2, 2) -#define CTXT_SELC_FNC_STS_W0_MEM_SPACE_ENABLE_MASK GENMASK(1, 1) -#define CTXT_SELC_FNC_STS_W0_BUS_MASTER_ENABLE_MASK GENMASK(0, 0) - -#ifdef __cplusplus -} -#endif - -#endif - diff --git a/QDMA/linux-kernel/driver/libqdma/qdma_access/eqdma_cpm5_access/eqdma_cpm5_reg_dump.c b/QDMA/linux-kernel/driver/libqdma/qdma_access/eqdma_cpm5_access/eqdma_cpm5_reg_dump.c deleted file mode 100755 index 2c71d0166..000000000 --- a/QDMA/linux-kernel/driver/libqdma/qdma_access/eqdma_cpm5_access/eqdma_cpm5_reg_dump.c +++ /dev/null @@ -1,4009 +0,0 @@ -/* - * Copyright (c) 2019-2022 Xilinx, Inc. All rights reserved. - * Copyright (c) 2022, Advanced Micro Devices, Inc. All rights reserved. - * - * This source code is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * The full GNU General Public License is included in this distribution in - * the file called "COPYING". - */ - -#include "eqdma_cpm5_reg.h" -#include "qdma_reg_dump.h" - -#ifdef ENABLE_WPP_TRACING -#include "eqdma_cpm5_reg_dump.tmh" -#endif - - -static struct regfield_info - cfg_blk_identifier_field_info[] = { - {"CFG_BLK_IDENTIFIER", - CFG_BLK_IDENTIFIER_MASK}, - {"CFG_BLK_IDENTIFIER_1", - CFG_BLK_IDENTIFIER_1_MASK}, - {"CFG_BLK_IDENTIFIER_RSVD_1", - CFG_BLK_IDENTIFIER_RSVD_1_MASK}, - {"CFG_BLK_IDENTIFIER_VERSION", - CFG_BLK_IDENTIFIER_VERSION_MASK}, -}; - - -static struct regfield_info - cfg_blk_pcie_max_pld_size_field_info[] = { - {"CFG_BLK_PCIE_MAX_PLD_SIZE_RSVD_1", - CFG_BLK_PCIE_MAX_PLD_SIZE_RSVD_1_MASK}, - {"CFG_BLK_PCIE_MAX_PLD_SIZE_PROG", - CFG_BLK_PCIE_MAX_PLD_SIZE_PROG_MASK}, - {"CFG_BLK_PCIE_MAX_PLD_SIZE_RSVD_2", - CFG_BLK_PCIE_MAX_PLD_SIZE_RSVD_2_MASK}, - {"CFG_BLK_PCIE_MAX_PLD_SIZE_ISSUED", - CFG_BLK_PCIE_MAX_PLD_SIZE_ISSUED_MASK}, -}; - - -static struct regfield_info - cfg_blk_pcie_max_read_req_size_field_info[] = { - {"CFG_BLK_PCIE_MAX_READ_REQ_SIZE_RSVD_1", - CFG_BLK_PCIE_MAX_READ_REQ_SIZE_RSVD_1_MASK}, - {"CFG_BLK_PCIE_MAX_READ_REQ_SIZE_PROG", - CFG_BLK_PCIE_MAX_READ_REQ_SIZE_PROG_MASK}, - {"CFG_BLK_PCIE_MAX_READ_REQ_SIZE_RSVD_2", - CFG_BLK_PCIE_MAX_READ_REQ_SIZE_RSVD_2_MASK}, - {"CFG_BLK_PCIE_MAX_READ_REQ_SIZE_ISSUED", - CFG_BLK_PCIE_MAX_READ_REQ_SIZE_ISSUED_MASK}, -}; - - -static struct regfield_info - cfg_blk_system_id_field_info[] = { - {"CFG_BLK_SYSTEM_ID_RSVD_1", - CFG_BLK_SYSTEM_ID_RSVD_1_MASK}, - {"CFG_BLK_SYSTEM_ID_INST_TYPE", - CFG_BLK_SYSTEM_ID_INST_TYPE_MASK}, - {"CFG_BLK_SYSTEM_ID", - CFG_BLK_SYSTEM_ID_MASK}, -}; - - -static struct regfield_info - cfg_blk_msix_enable_field_info[] = { - {"CFG_BLK_MSIX_ENABLE", - CFG_BLK_MSIX_ENABLE_MASK}, -}; - - -static struct regfield_info - cfg_pcie_data_width_field_info[] = { - {"CFG_PCIE_DATA_WIDTH_RSVD_1", - CFG_PCIE_DATA_WIDTH_RSVD_1_MASK}, - {"CFG_PCIE_DATA_WIDTH_DATAPATH", - CFG_PCIE_DATA_WIDTH_DATAPATH_MASK}, -}; - - -static struct regfield_info - cfg_pcie_ctl_field_info[] = { - {"CFG_PCIE_CTL_RSVD_1", - CFG_PCIE_CTL_RSVD_1_MASK}, - {"CFG_PCIE_CTL_MGMT_AXIL_CTRL", - CFG_PCIE_CTL_MGMT_AXIL_CTRL_MASK}, - {"CFG_PCIE_CTL_RSVD_2", - CFG_PCIE_CTL_RSVD_2_MASK}, - {"CFG_PCIE_CTL_RRQ_DISABLE", - CFG_PCIE_CTL_RRQ_DISABLE_MASK}, - {"CFG_PCIE_CTL_RELAXED_ORDERING", - CFG_PCIE_CTL_RELAXED_ORDERING_MASK}, -}; - - -static struct regfield_info - cfg_blk_msi_enable_field_info[] = { - {"CFG_BLK_MSI_ENABLE", - CFG_BLK_MSI_ENABLE_MASK}, -}; - - -static struct regfield_info - cfg_axi_user_max_pld_size_field_info[] = { - {"CFG_AXI_USER_MAX_PLD_SIZE_RSVD_1", - CFG_AXI_USER_MAX_PLD_SIZE_RSVD_1_MASK}, - {"CFG_AXI_USER_MAX_PLD_SIZE_ISSUED", - CFG_AXI_USER_MAX_PLD_SIZE_ISSUED_MASK}, - {"CFG_AXI_USER_MAX_PLD_SIZE_RSVD_2", - CFG_AXI_USER_MAX_PLD_SIZE_RSVD_2_MASK}, - {"CFG_AXI_USER_MAX_PLD_SIZE_PROG", - CFG_AXI_USER_MAX_PLD_SIZE_PROG_MASK}, -}; - - -static struct regfield_info - cfg_axi_user_max_read_req_size_field_info[] = { - {"CFG_AXI_USER_MAX_READ_REQ_SIZE_RSVD_1", - CFG_AXI_USER_MAX_READ_REQ_SIZE_RSVD_1_MASK}, - {"CFG_AXI_USER_MAX_READ_REQ_SIZE_USISSUED", - CFG_AXI_USER_MAX_READ_REQ_SIZE_USISSUED_MASK}, - {"CFG_AXI_USER_MAX_READ_REQ_SIZE_RSVD_2", - CFG_AXI_USER_MAX_READ_REQ_SIZE_RSVD_2_MASK}, - {"CFG_AXI_USER_MAX_READ_REQ_SIZE_USPROG", - CFG_AXI_USER_MAX_READ_REQ_SIZE_USPROG_MASK}, -}; - - -static struct regfield_info - cfg_blk_misc_ctl_field_info[] = { - {"CFG_BLK_MISC_CTL_RSVD_1", - CFG_BLK_MISC_CTL_RSVD_1_MASK}, - {"CFG_BLK_MISC_CTL_10B_TAG_EN", - CFG_BLK_MISC_CTL_10B_TAG_EN_MASK}, - {"CFG_BLK_MISC_CTL_RSVD_2", - CFG_BLK_MISC_CTL_RSVD_2_MASK}, - {"CFG_BLK_MISC_CTL_AXI_WBK", - CFG_BLK_MISC_CTL_AXI_WBK_MASK}, - {"CFG_BLK_MISC_CTL_AXI_DSC", - CFG_BLK_MISC_CTL_AXI_DSC_MASK}, - {"CFG_BLK_MISC_CTL_NUM_TAG", - CFG_BLK_MISC_CTL_NUM_TAG_MASK}, - {"CFG_BLK_MISC_CTL_RSVD_3", - CFG_BLK_MISC_CTL_RSVD_3_MASK}, - {"CFG_BLK_MISC_CTL_RQ_METERING_MULTIPLIER", - CFG_BLK_MISC_CTL_RQ_METERING_MULTIPLIER_MASK}, -}; - - -static struct regfield_info - cfg_pl_cred_ctl_field_info[] = { - {"CFG_PL_CRED_CTL_RSVD_1", - CFG_PL_CRED_CTL_RSVD_1_MASK}, - {"CFG_PL_CRED_CTL_SLAVE_CRD_RLS", - CFG_PL_CRED_CTL_SLAVE_CRD_RLS_MASK}, - {"CFG_PL_CRED_CTL_RSVD_2", - CFG_PL_CRED_CTL_RSVD_2_MASK}, - {"CFG_PL_CRED_CTL_MASTER_CRD_RST", - CFG_PL_CRED_CTL_MASTER_CRD_RST_MASK}, -}; - - -static struct regfield_info - cfg_blk_scratch_field_info[] = { - {"CFG_BLK_SCRATCH", - CFG_BLK_SCRATCH_MASK}, -}; - - -static struct regfield_info - cfg_gic_field_info[] = { - {"CFG_GIC_RSVD_1", - CFG_GIC_RSVD_1_MASK}, - {"CFG_GIC_GIC_IRQ", - CFG_GIC_GIC_IRQ_MASK}, -}; - - -static struct regfield_info - ram_sbe_msk_1_a_field_info[] = { - {"RAM_SBE_MSK_1_A", - RAM_SBE_MSK_1_A_MASK}, -}; - - -static struct regfield_info - ram_sbe_sts_1_a_field_info[] = { - {"RAM_SBE_STS_1_A_RSVD", - RAM_SBE_STS_1_A_RSVD_MASK}, - {"RAM_SBE_STS_1_A_PFCH_CTXT_CAM_RAM_1", - RAM_SBE_STS_1_A_PFCH_CTXT_CAM_RAM_1_MASK}, - {"RAM_SBE_STS_1_A_PFCH_CTXT_CAM_RAM_0", - RAM_SBE_STS_1_A_PFCH_CTXT_CAM_RAM_0_MASK}, - {"RAM_SBE_STS_1_A_TAG_EVEN_RAM", - RAM_SBE_STS_1_A_TAG_EVEN_RAM_MASK}, - {"RAM_SBE_STS_1_A_TAG_ODD_RAM", - RAM_SBE_STS_1_A_TAG_ODD_RAM_MASK}, - {"RAM_SBE_STS_1_A_RC_RRQ_EVEN_RAM", - RAM_SBE_STS_1_A_RC_RRQ_EVEN_RAM_MASK}, -}; - - -static struct regfield_info - ram_dbe_msk_1_a_field_info[] = { - {"RAM_DBE_MSK_1_A", - RAM_DBE_MSK_1_A_MASK}, -}; - - -static struct regfield_info - ram_dbe_sts_1_a_field_info[] = { - {"RAM_DBE_STS_1_A_RSVD", - RAM_DBE_STS_1_A_RSVD_MASK}, - {"RAM_DBE_STS_1_A_PFCH_CTXT_CAM_RAM_1", - RAM_DBE_STS_1_A_PFCH_CTXT_CAM_RAM_1_MASK}, - {"RAM_DBE_STS_1_A_PFCH_CTXT_CAM_RAM_0", - RAM_DBE_STS_1_A_PFCH_CTXT_CAM_RAM_0_MASK}, - {"RAM_DBE_STS_1_A_TAG_EVEN_RAM", - RAM_DBE_STS_1_A_TAG_EVEN_RAM_MASK}, - {"RAM_DBE_STS_1_A_TAG_ODD_RAM", - RAM_DBE_STS_1_A_TAG_ODD_RAM_MASK}, - {"RAM_DBE_STS_1_A_RC_RRQ_EVEN_RAM", - RAM_DBE_STS_1_A_RC_RRQ_EVEN_RAM_MASK}, -}; - - -static struct regfield_info - ram_sbe_msk_a_field_info[] = { - {"RAM_SBE_MSK_A", - RAM_SBE_MSK_A_MASK}, -}; - - -static struct regfield_info - ram_sbe_sts_a_field_info[] = { - {"RAM_SBE_STS_A_RC_RRQ_ODD_RAM", - RAM_SBE_STS_A_RC_RRQ_ODD_RAM_MASK}, - {"RAM_SBE_STS_A_PEND_FIFO_RAM", - RAM_SBE_STS_A_PEND_FIFO_RAM_MASK}, - {"RAM_SBE_STS_A_PFCH_LL_RAM", - RAM_SBE_STS_A_PFCH_LL_RAM_MASK}, - {"RAM_SBE_STS_A_WRB_CTXT_RAM", - RAM_SBE_STS_A_WRB_CTXT_RAM_MASK}, - {"RAM_SBE_STS_A_PFCH_CTXT_RAM", - RAM_SBE_STS_A_PFCH_CTXT_RAM_MASK}, - {"RAM_SBE_STS_A_DESC_REQ_FIFO_RAM", - RAM_SBE_STS_A_DESC_REQ_FIFO_RAM_MASK}, - {"RAM_SBE_STS_A_INT_CTXT_RAM", - RAM_SBE_STS_A_INT_CTXT_RAM_MASK}, - {"RAM_SBE_STS_A_WRB_COAL_DATA_RAM", - RAM_SBE_STS_A_WRB_COAL_DATA_RAM_MASK}, - {"RAM_SBE_STS_A_QID_FIFO_RAM", - RAM_SBE_STS_A_QID_FIFO_RAM_MASK}, - {"RAM_SBE_STS_A_TIMER_FIFO_RAM", - RAM_SBE_STS_A_TIMER_FIFO_RAM_MASK}, - {"RAM_SBE_STS_A_MI_TL_SLV_FIFO_RAM", - RAM_SBE_STS_A_MI_TL_SLV_FIFO_RAM_MASK}, - {"RAM_SBE_STS_A_DSC_CPLD", - RAM_SBE_STS_A_DSC_CPLD_MASK}, - {"RAM_SBE_STS_A_DSC_CPLI", - RAM_SBE_STS_A_DSC_CPLI_MASK}, - {"RAM_SBE_STS_A_DSC_SW_CTXT", - RAM_SBE_STS_A_DSC_SW_CTXT_MASK}, - {"RAM_SBE_STS_A_DSC_CRD_RCV", - RAM_SBE_STS_A_DSC_CRD_RCV_MASK}, - {"RAM_SBE_STS_A_DSC_HW_CTXT", - RAM_SBE_STS_A_DSC_HW_CTXT_MASK}, - {"RAM_SBE_STS_A_FUNC_MAP", - RAM_SBE_STS_A_FUNC_MAP_MASK}, - {"RAM_SBE_STS_A_C2H_WR_BRG_DAT", - RAM_SBE_STS_A_C2H_WR_BRG_DAT_MASK}, - {"RAM_SBE_STS_A_C2H_RD_BRG_DAT", - RAM_SBE_STS_A_C2H_RD_BRG_DAT_MASK}, - {"RAM_SBE_STS_A_H2C_WR_BRG_DAT", - RAM_SBE_STS_A_H2C_WR_BRG_DAT_MASK}, - {"RAM_SBE_STS_A_H2C_RD_BRG_DAT", - RAM_SBE_STS_A_H2C_RD_BRG_DAT_MASK}, - {"RAM_SBE_STS_A_MI_C2H3_DAT", - RAM_SBE_STS_A_MI_C2H3_DAT_MASK}, - {"RAM_SBE_STS_A_MI_C2H2_DAT", - RAM_SBE_STS_A_MI_C2H2_DAT_MASK}, - {"RAM_SBE_STS_A_MI_C2H1_DAT", - RAM_SBE_STS_A_MI_C2H1_DAT_MASK}, - {"RAM_SBE_STS_A_MI_C2H0_DAT", - RAM_SBE_STS_A_MI_C2H0_DAT_MASK}, - {"RAM_SBE_STS_A_MI_H2C3_DAT", - RAM_SBE_STS_A_MI_H2C3_DAT_MASK}, - {"RAM_SBE_STS_A_MI_H2C2_DAT", - RAM_SBE_STS_A_MI_H2C2_DAT_MASK}, - {"RAM_SBE_STS_A_MI_H2C1_DAT", - RAM_SBE_STS_A_MI_H2C1_DAT_MASK}, - {"RAM_SBE_STS_A_MI_H2C0_DAT", - RAM_SBE_STS_A_MI_H2C0_DAT_MASK}, -}; - - -static struct regfield_info - ram_dbe_msk_a_field_info[] = { - {"RAM_DBE_MSK_A", - RAM_DBE_MSK_A_MASK}, -}; - - -static struct regfield_info - ram_dbe_sts_a_field_info[] = { - {"RAM_DBE_STS_A_RC_RRQ_ODD_RAM", - RAM_DBE_STS_A_RC_RRQ_ODD_RAM_MASK}, - {"RAM_DBE_STS_A_PEND_FIFO_RAM", - RAM_DBE_STS_A_PEND_FIFO_RAM_MASK}, - {"RAM_DBE_STS_A_PFCH_LL_RAM", - RAM_DBE_STS_A_PFCH_LL_RAM_MASK}, - {"RAM_DBE_STS_A_WRB_CTXT_RAM", - RAM_DBE_STS_A_WRB_CTXT_RAM_MASK}, - {"RAM_DBE_STS_A_PFCH_CTXT_RAM", - RAM_DBE_STS_A_PFCH_CTXT_RAM_MASK}, - {"RAM_DBE_STS_A_DESC_REQ_FIFO_RAM", - RAM_DBE_STS_A_DESC_REQ_FIFO_RAM_MASK}, - {"RAM_DBE_STS_A_INT_CTXT_RAM", - RAM_DBE_STS_A_INT_CTXT_RAM_MASK}, - {"RAM_DBE_STS_A_WRB_COAL_DATA_RAM", - RAM_DBE_STS_A_WRB_COAL_DATA_RAM_MASK}, - {"RAM_DBE_STS_A_QID_FIFO_RAM", - RAM_DBE_STS_A_QID_FIFO_RAM_MASK}, - {"RAM_DBE_STS_A_TIMER_FIFO_RAM", - RAM_DBE_STS_A_TIMER_FIFO_RAM_MASK}, - {"RAM_DBE_STS_A_MI_TL_SLV_FIFO_RAM", - RAM_DBE_STS_A_MI_TL_SLV_FIFO_RAM_MASK}, - {"RAM_DBE_STS_A_DSC_CPLD", - RAM_DBE_STS_A_DSC_CPLD_MASK}, - {"RAM_DBE_STS_A_DSC_CPLI", - RAM_DBE_STS_A_DSC_CPLI_MASK}, - {"RAM_DBE_STS_A_DSC_SW_CTXT", - RAM_DBE_STS_A_DSC_SW_CTXT_MASK}, - {"RAM_DBE_STS_A_DSC_CRD_RCV", - RAM_DBE_STS_A_DSC_CRD_RCV_MASK}, - {"RAM_DBE_STS_A_DSC_HW_CTXT", - RAM_DBE_STS_A_DSC_HW_CTXT_MASK}, - {"RAM_DBE_STS_A_FUNC_MAP", - RAM_DBE_STS_A_FUNC_MAP_MASK}, - {"RAM_DBE_STS_A_C2H_WR_BRG_DAT", - RAM_DBE_STS_A_C2H_WR_BRG_DAT_MASK}, - {"RAM_DBE_STS_A_C2H_RD_BRG_DAT", - RAM_DBE_STS_A_C2H_RD_BRG_DAT_MASK}, - {"RAM_DBE_STS_A_H2C_WR_BRG_DAT", - RAM_DBE_STS_A_H2C_WR_BRG_DAT_MASK}, - {"RAM_DBE_STS_A_H2C_RD_BRG_DAT", - RAM_DBE_STS_A_H2C_RD_BRG_DAT_MASK}, - {"RAM_DBE_STS_A_MI_C2H3_DAT", - RAM_DBE_STS_A_MI_C2H3_DAT_MASK}, - {"RAM_DBE_STS_A_MI_C2H2_DAT", - RAM_DBE_STS_A_MI_C2H2_DAT_MASK}, - {"RAM_DBE_STS_A_MI_C2H1_DAT", - RAM_DBE_STS_A_MI_C2H1_DAT_MASK}, - {"RAM_DBE_STS_A_MI_C2H0_DAT", - RAM_DBE_STS_A_MI_C2H0_DAT_MASK}, - {"RAM_DBE_STS_A_MI_H2C3_DAT", - RAM_DBE_STS_A_MI_H2C3_DAT_MASK}, - {"RAM_DBE_STS_A_MI_H2C2_DAT", - RAM_DBE_STS_A_MI_H2C2_DAT_MASK}, - {"RAM_DBE_STS_A_MI_H2C1_DAT", - RAM_DBE_STS_A_MI_H2C1_DAT_MASK}, - {"RAM_DBE_STS_A_MI_H2C0_DAT", - RAM_DBE_STS_A_MI_H2C0_DAT_MASK}, -}; - - -static struct regfield_info - glbl2_identifier_field_info[] = { - {"GLBL2_IDENTIFIER", - GLBL2_IDENTIFIER_MASK}, - {"GLBL2_IDENTIFIER_VERSION", - GLBL2_IDENTIFIER_VERSION_MASK}, -}; - - -static struct regfield_info - glbl2_channel_inst_field_info[] = { - {"GLBL2_CHANNEL_INST_RSVD_1", - GLBL2_CHANNEL_INST_RSVD_1_MASK}, - {"GLBL2_CHANNEL_INST_C2H_ST", - GLBL2_CHANNEL_INST_C2H_ST_MASK}, - {"GLBL2_CHANNEL_INST_H2C_ST", - GLBL2_CHANNEL_INST_H2C_ST_MASK}, - {"GLBL2_CHANNEL_INST_RSVD_2", - GLBL2_CHANNEL_INST_RSVD_2_MASK}, - {"GLBL2_CHANNEL_INST_C2H_ENG", - GLBL2_CHANNEL_INST_C2H_ENG_MASK}, - {"GLBL2_CHANNEL_INST_RSVD_3", - GLBL2_CHANNEL_INST_RSVD_3_MASK}, - {"GLBL2_CHANNEL_INST_H2C_ENG", - GLBL2_CHANNEL_INST_H2C_ENG_MASK}, -}; - - -static struct regfield_info - glbl2_channel_mdma_field_info[] = { - {"GLBL2_CHANNEL_MDMA_RSVD_1", - GLBL2_CHANNEL_MDMA_RSVD_1_MASK}, - {"GLBL2_CHANNEL_MDMA_C2H_ST", - GLBL2_CHANNEL_MDMA_C2H_ST_MASK}, - {"GLBL2_CHANNEL_MDMA_H2C_ST", - GLBL2_CHANNEL_MDMA_H2C_ST_MASK}, - {"GLBL2_CHANNEL_MDMA_RSVD_2", - GLBL2_CHANNEL_MDMA_RSVD_2_MASK}, - {"GLBL2_CHANNEL_MDMA_C2H_ENG", - GLBL2_CHANNEL_MDMA_C2H_ENG_MASK}, - {"GLBL2_CHANNEL_MDMA_RSVD_3", - GLBL2_CHANNEL_MDMA_RSVD_3_MASK}, - {"GLBL2_CHANNEL_MDMA_H2C_ENG", - GLBL2_CHANNEL_MDMA_H2C_ENG_MASK}, -}; - - -static struct regfield_info - glbl2_channel_strm_field_info[] = { - {"GLBL2_CHANNEL_STRM_RSVD_1", - GLBL2_CHANNEL_STRM_RSVD_1_MASK}, - {"GLBL2_CHANNEL_STRM_C2H_ST", - GLBL2_CHANNEL_STRM_C2H_ST_MASK}, - {"GLBL2_CHANNEL_STRM_H2C_ST", - GLBL2_CHANNEL_STRM_H2C_ST_MASK}, - {"GLBL2_CHANNEL_STRM_RSVD_2", - GLBL2_CHANNEL_STRM_RSVD_2_MASK}, - {"GLBL2_CHANNEL_STRM_C2H_ENG", - GLBL2_CHANNEL_STRM_C2H_ENG_MASK}, - {"GLBL2_CHANNEL_STRM_RSVD_3", - GLBL2_CHANNEL_STRM_RSVD_3_MASK}, - {"GLBL2_CHANNEL_STRM_H2C_ENG", - GLBL2_CHANNEL_STRM_H2C_ENG_MASK}, -}; - - -static struct regfield_info - glbl2_channel_cap_field_info[] = { - {"GLBL2_CHANNEL_CAP_RSVD_1", - GLBL2_CHANNEL_CAP_RSVD_1_MASK}, - {"GLBL2_CHANNEL_CAP_MULTIQ_MAX", - GLBL2_CHANNEL_CAP_MULTIQ_MAX_MASK}, -}; - - -static struct regfield_info - glbl2_channel_pasid_cap_field_info[] = { - {"GLBL2_CHANNEL_PASID_CAP_RSVD_1", - GLBL2_CHANNEL_PASID_CAP_RSVD_1_MASK}, - {"GLBL2_CHANNEL_PASID_CAP_BRIDGEEN", - GLBL2_CHANNEL_PASID_CAP_BRIDGEEN_MASK}, - {"GLBL2_CHANNEL_PASID_CAP_DMAEN", - GLBL2_CHANNEL_PASID_CAP_DMAEN_MASK}, -}; - - -static struct regfield_info - glbl2_system_id_field_info[] = { - {"GLBL2_SYSTEM_ID_RSVD_1", - GLBL2_SYSTEM_ID_RSVD_1_MASK}, - {"GLBL2_SYSTEM_ID", - GLBL2_SYSTEM_ID_MASK}, -}; - - -static struct regfield_info - glbl2_misc_cap_field_info[] = { - {"GLBL2_MISC_CAP", - GLBL2_MISC_CAP_MASK}, -}; - - -static struct regfield_info - glbl2_dbg_pcie_rq0_field_info[] = { - {"GLBL2_PCIE_RQ0_NPH_AVL", - GLBL2_PCIE_RQ0_NPH_AVL_MASK}, - {"GLBL2_PCIE_RQ0_RCB_AVL", - GLBL2_PCIE_RQ0_RCB_AVL_MASK}, - {"GLBL2_PCIE_RQ0_SLV_RD_CREDS", - GLBL2_PCIE_RQ0_SLV_RD_CREDS_MASK}, - {"GLBL2_PCIE_RQ0_TAG_EP", - GLBL2_PCIE_RQ0_TAG_EP_MASK}, -}; - - -static struct regfield_info - glbl2_dbg_pcie_rq1_field_info[] = { - {"GLBL2_PCIE_RQ1_RSVD_1", - GLBL2_PCIE_RQ1_RSVD_1_MASK}, - {"GLBL2_PCIE_RQ1_TAG_FL", - GLBL2_PCIE_RQ1_TAG_FL_MASK}, - {"GLBL2_PCIE_RQ1_WTLP_HEADER_FIFO_FL", - GLBL2_PCIE_RQ1_WTLP_HEADER_FIFO_FL_MASK}, - {"GLBL2_PCIE_RQ1_WTLP_HEADER_FIFO_EP", - GLBL2_PCIE_RQ1_WTLP_HEADER_FIFO_EP_MASK}, - {"GLBL2_PCIE_RQ1_RQ_FIFO_EP", - GLBL2_PCIE_RQ1_RQ_FIFO_EP_MASK}, - {"GLBL2_PCIE_RQ1_RQ_FIFO_FL", - GLBL2_PCIE_RQ1_RQ_FIFO_FL_MASK}, - {"GLBL2_PCIE_RQ1_TLPSM", - GLBL2_PCIE_RQ1_TLPSM_MASK}, - {"GLBL2_PCIE_RQ1_TLPSM512", - GLBL2_PCIE_RQ1_TLPSM512_MASK}, - {"GLBL2_PCIE_RQ1_RREQ_RCB_OK", - GLBL2_PCIE_RQ1_RREQ_RCB_OK_MASK}, - {"GLBL2_PCIE_RQ1_RREQ0_SLV", - GLBL2_PCIE_RQ1_RREQ0_SLV_MASK}, - {"GLBL2_PCIE_RQ1_RREQ0_VLD", - GLBL2_PCIE_RQ1_RREQ0_VLD_MASK}, - {"GLBL2_PCIE_RQ1_RREQ0_RDY", - GLBL2_PCIE_RQ1_RREQ0_RDY_MASK}, - {"GLBL2_PCIE_RQ1_RREQ1_SLV", - GLBL2_PCIE_RQ1_RREQ1_SLV_MASK}, - {"GLBL2_PCIE_RQ1_RREQ1_VLD", - GLBL2_PCIE_RQ1_RREQ1_VLD_MASK}, - {"GLBL2_PCIE_RQ1_RREQ1_RDY", - GLBL2_PCIE_RQ1_RREQ1_RDY_MASK}, - {"GLBL2_PCIE_RQ1_WTLP_REQ", - GLBL2_PCIE_RQ1_WTLP_REQ_MASK}, - {"GLBL2_PCIE_RQ1_WTLP_STRADDLE", - GLBL2_PCIE_RQ1_WTLP_STRADDLE_MASK}, -}; - - -static struct regfield_info - glbl2_dbg_aximm_wr0_field_info[] = { - {"GLBL2_AXIMM_WR0_RSVD_1", - GLBL2_AXIMM_WR0_RSVD_1_MASK}, - {"GLBL2_AXIMM_WR0_WR_REQ", - GLBL2_AXIMM_WR0_WR_REQ_MASK}, - {"GLBL2_AXIMM_WR0_WR_CHN", - GLBL2_AXIMM_WR0_WR_CHN_MASK}, - {"GLBL2_AXIMM_WR0_WTLP_DATA_FIFO_EP", - GLBL2_AXIMM_WR0_WTLP_DATA_FIFO_EP_MASK}, - {"GLBL2_AXIMM_WR0_WPL_FIFO_EP", - GLBL2_AXIMM_WR0_WPL_FIFO_EP_MASK}, - {"GLBL2_AXIMM_WR0_BRSP_CLAIM_CHN", - GLBL2_AXIMM_WR0_BRSP_CLAIM_CHN_MASK}, - {"GLBL2_AXIMM_WR0_WRREQ_CNT", - GLBL2_AXIMM_WR0_WRREQ_CNT_MASK}, - {"GLBL2_AXIMM_WR0_BID", - GLBL2_AXIMM_WR0_BID_MASK}, - {"GLBL2_AXIMM_WR0_BVALID", - GLBL2_AXIMM_WR0_BVALID_MASK}, - {"GLBL2_AXIMM_WR0_BREADY", - GLBL2_AXIMM_WR0_BREADY_MASK}, - {"GLBL2_AXIMM_WR0_WVALID", - GLBL2_AXIMM_WR0_WVALID_MASK}, - {"GLBL2_AXIMM_WR0_WREADY", - GLBL2_AXIMM_WR0_WREADY_MASK}, - {"GLBL2_AXIMM_WR0_AWID", - GLBL2_AXIMM_WR0_AWID_MASK}, - {"GLBL2_AXIMM_WR0_AWVALID", - GLBL2_AXIMM_WR0_AWVALID_MASK}, - {"GLBL2_AXIMM_WR0_AWREADY", - GLBL2_AXIMM_WR0_AWREADY_MASK}, -}; - - -static struct regfield_info - glbl2_dbg_aximm_wr1_field_info[] = { - {"GLBL2_AXIMM_WR1_RSVD_1", - GLBL2_AXIMM_WR1_RSVD_1_MASK}, - {"GLBL2_AXIMM_WR1_BRSP_CNT4", - GLBL2_AXIMM_WR1_BRSP_CNT4_MASK}, - {"GLBL2_AXIMM_WR1_BRSP_CNT3", - GLBL2_AXIMM_WR1_BRSP_CNT3_MASK}, - {"GLBL2_AXIMM_WR1_BRSP_CNT2", - GLBL2_AXIMM_WR1_BRSP_CNT2_MASK}, - {"GLBL2_AXIMM_WR1_BRSP_CNT1", - GLBL2_AXIMM_WR1_BRSP_CNT1_MASK}, - {"GLBL2_AXIMM_WR1_BRSP_CNT0", - GLBL2_AXIMM_WR1_BRSP_CNT0_MASK}, -}; - - -static struct regfield_info - glbl2_dbg_aximm_rd0_field_info[] = { - {"GLBL2_AXIMM_RD0_RSVD_1", - GLBL2_AXIMM_RD0_RSVD_1_MASK}, - {"GLBL2_AXIMM_RD0_PND_CNT", - GLBL2_AXIMM_RD0_PND_CNT_MASK}, - {"GLBL2_AXIMM_RD0_RD_REQ", - GLBL2_AXIMM_RD0_RD_REQ_MASK}, - {"GLBL2_AXIMM_RD0_RD_CHNL", - GLBL2_AXIMM_RD0_RD_CHNL_MASK}, - {"GLBL2_AXIMM_RD0_RRSP_CLAIM_CHNL", - GLBL2_AXIMM_RD0_RRSP_CLAIM_CHNL_MASK}, - {"GLBL2_AXIMM_RD0_RID", - GLBL2_AXIMM_RD0_RID_MASK}, - {"GLBL2_AXIMM_RD0_RVALID", - GLBL2_AXIMM_RD0_RVALID_MASK}, - {"GLBL2_AXIMM_RD0_RREADY", - GLBL2_AXIMM_RD0_RREADY_MASK}, - {"GLBL2_AXIMM_RD0_ARID", - GLBL2_AXIMM_RD0_ARID_MASK}, - {"GLBL2_AXIMM_RD0_ARVALID", - GLBL2_AXIMM_RD0_ARVALID_MASK}, - {"GLBL2_AXIMM_RD0_ARREADY", - GLBL2_AXIMM_RD0_ARREADY_MASK}, -}; - - -static struct regfield_info - glbl2_dbg_aximm_rd1_field_info[] = { - {"GLBL2_AXIMM_RD1_RSVD_1", - GLBL2_AXIMM_RD1_RSVD_1_MASK}, - {"GLBL2_AXIMM_RD1_RRSP_CNT4", - GLBL2_AXIMM_RD1_RRSP_CNT4_MASK}, - {"GLBL2_AXIMM_RD1_RRSP_CNT3", - GLBL2_AXIMM_RD1_RRSP_CNT3_MASK}, - {"GLBL2_AXIMM_RD1_RRSP_CNT2", - GLBL2_AXIMM_RD1_RRSP_CNT2_MASK}, - {"GLBL2_AXIMM_RD1_RRSP_CNT1", - GLBL2_AXIMM_RD1_RRSP_CNT1_MASK}, - {"GLBL2_AXIMM_RD1_RRSP_CNT0", - GLBL2_AXIMM_RD1_RRSP_CNT0_MASK}, -}; - - -static struct regfield_info - glbl2_dbg_fab0_field_info[] = { - {"GLBL2_FAB0_H2C_INB_CONV_IN_VLD", - GLBL2_FAB0_H2C_INB_CONV_IN_VLD_MASK}, - {"GLBL2_FAB0_H2C_INB_CONV_IN_RDY", - GLBL2_FAB0_H2C_INB_CONV_IN_RDY_MASK}, - {"GLBL2_FAB0_H2C_SEG_IN_VLD", - GLBL2_FAB0_H2C_SEG_IN_VLD_MASK}, - {"GLBL2_FAB0_H2C_SEG_IN_RDY", - GLBL2_FAB0_H2C_SEG_IN_RDY_MASK}, - {"GLBL2_FAB0_H2C_SEG_OUT_VLD", - GLBL2_FAB0_H2C_SEG_OUT_VLD_MASK}, - {"GLBL2_FAB0_H2C_SEG_OUT_RDY", - GLBL2_FAB0_H2C_SEG_OUT_RDY_MASK}, - {"GLBL2_FAB0_H2C_MST_CRDT_STAT", - GLBL2_FAB0_H2C_MST_CRDT_STAT_MASK}, - {"GLBL2_FAB0_C2H_SLV_AFIFO_FULL", - GLBL2_FAB0_C2H_SLV_AFIFO_FULL_MASK}, - {"GLBL2_FAB0_C2H_SLV_AFIFO_EMPTY", - GLBL2_FAB0_C2H_SLV_AFIFO_EMPTY_MASK}, - {"GLBL2_FAB0_C2H_DESEG_SEG_VLD", - GLBL2_FAB0_C2H_DESEG_SEG_VLD_MASK}, - {"GLBL2_FAB0_C2H_DESEG_SEG_RDY", - GLBL2_FAB0_C2H_DESEG_SEG_RDY_MASK}, - {"GLBL2_FAB0_C2H_DESEG_OUT_VLD", - GLBL2_FAB0_C2H_DESEG_OUT_VLD_MASK}, - {"GLBL2_FAB0_C2H_DESEG_OUT_RDY", - GLBL2_FAB0_C2H_DESEG_OUT_RDY_MASK}, - {"GLBL2_FAB0_C2H_INB_DECONV_OUT_VLD", - GLBL2_FAB0_C2H_INB_DECONV_OUT_VLD_MASK}, - {"GLBL2_FAB0_C2H_INB_DECONV_OUT_RDY", - GLBL2_FAB0_C2H_INB_DECONV_OUT_RDY_MASK}, - {"GLBL2_FAB0_C2H_DSC_CRDT_AFIFO_FULL", - GLBL2_FAB0_C2H_DSC_CRDT_AFIFO_FULL_MASK}, - {"GLBL2_FAB0_C2H_DSC_CRDT_AFIFO_EMPTY", - GLBL2_FAB0_C2H_DSC_CRDT_AFIFO_EMPTY_MASK}, - {"GLBL2_FAB0_IRQ_IN_AFIFO_FULL", - GLBL2_FAB0_IRQ_IN_AFIFO_FULL_MASK}, - {"GLBL2_FAB0_IRQ_IN_AFIFO_EMPTY", - GLBL2_FAB0_IRQ_IN_AFIFO_EMPTY_MASK}, - {"GLBL2_FAB0_IMM_CRD_AFIFO_EMPTY", - GLBL2_FAB0_IMM_CRD_AFIFO_EMPTY_MASK}, -}; - - -static struct regfield_info - glbl2_dbg_fab1_field_info[] = { - {"GLBL2_FAB1_BYP_OUT_CRDT_STAT", - GLBL2_FAB1_BYP_OUT_CRDT_STAT_MASK}, - {"GLBL2_FAB1_TM_DSC_STS_CRDT_STAT", - GLBL2_FAB1_TM_DSC_STS_CRDT_STAT_MASK}, - {"GLBL2_FAB1_C2H_CMN_AFIFO_FULL", - GLBL2_FAB1_C2H_CMN_AFIFO_FULL_MASK}, - {"GLBL2_FAB1_C2H_CMN_AFIFO_EMPTY", - GLBL2_FAB1_C2H_CMN_AFIFO_EMPTY_MASK}, - {"GLBL2_FAB1_RSVD_1", - GLBL2_FAB1_RSVD_1_MASK}, - {"GLBL2_FAB1_C2H_BYP_IN_AFIFO_FULL", - GLBL2_FAB1_C2H_BYP_IN_AFIFO_FULL_MASK}, - {"GLBL2_FAB1_RSVD_2", - GLBL2_FAB1_RSVD_2_MASK}, - {"GLBL2_FAB1_C2H_BYP_IN_AFIFO_EMPTY", - GLBL2_FAB1_C2H_BYP_IN_AFIFO_EMPTY_MASK}, - {"GLBL2_FAB1_RSVD_3", - GLBL2_FAB1_RSVD_3_MASK}, - {"GLBL2_FAB1_H2C_BYP_IN_AFIFO_FULL", - GLBL2_FAB1_H2C_BYP_IN_AFIFO_FULL_MASK}, - {"GLBL2_FAB1_RSVD_4", - GLBL2_FAB1_RSVD_4_MASK}, - {"GLBL2_FAB1_H2C_BYP_IN_AFIFO_EMPTY", - GLBL2_FAB1_H2C_BYP_IN_AFIFO_EMPTY_MASK}, -}; - - -static struct regfield_info - glbl2_dbg_match_sel_field_info[] = { - {"GLBL2_MATCH_SEL_RSV", - GLBL2_MATCH_SEL_RSV_MASK}, - {"GLBL2_MATCH_SEL_CSR_SEL", - GLBL2_MATCH_SEL_CSR_SEL_MASK}, - {"GLBL2_MATCH_SEL_CSR_EN", - GLBL2_MATCH_SEL_CSR_EN_MASK}, - {"GLBL2_MATCH_SEL_ROTATE1", - GLBL2_MATCH_SEL_ROTATE1_MASK}, - {"GLBL2_MATCH_SEL_ROTATE0", - GLBL2_MATCH_SEL_ROTATE0_MASK}, - {"GLBL2_MATCH_SEL_SEL", - GLBL2_MATCH_SEL_SEL_MASK}, -}; - - -static struct regfield_info - glbl2_dbg_match_msk_field_info[] = { - {"GLBL2_MATCH_MSK", - GLBL2_MATCH_MSK_MASK}, -}; - - -static struct regfield_info - glbl2_dbg_match_pat_field_info[] = { - {"GLBL2_MATCH_PAT_PATTERN", - GLBL2_MATCH_PAT_PATTERN_MASK}, -}; - - -static struct regfield_info - glbl_rng_sz_1_field_info[] = { - {"GLBL_RNG_SZ_1_RSVD_1", - GLBL_RNG_SZ_1_RSVD_1_MASK}, - {"GLBL_RNG_SZ_1_RING_SIZE", - GLBL_RNG_SZ_1_RING_SIZE_MASK}, -}; - - -static struct regfield_info - glbl_rng_sz_2_field_info[] = { - {"GLBL_RNG_SZ_2_RSVD_1", - GLBL_RNG_SZ_2_RSVD_1_MASK}, - {"GLBL_RNG_SZ_2_RING_SIZE", - GLBL_RNG_SZ_2_RING_SIZE_MASK}, -}; - - -static struct regfield_info - glbl_rng_sz_3_field_info[] = { - {"GLBL_RNG_SZ_3_RSVD_1", - GLBL_RNG_SZ_3_RSVD_1_MASK}, - {"GLBL_RNG_SZ_3_RING_SIZE", - GLBL_RNG_SZ_3_RING_SIZE_MASK}, -}; - - -static struct regfield_info - glbl_rng_sz_4_field_info[] = { - {"GLBL_RNG_SZ_4_RSVD_1", - GLBL_RNG_SZ_4_RSVD_1_MASK}, - {"GLBL_RNG_SZ_4_RING_SIZE", - GLBL_RNG_SZ_4_RING_SIZE_MASK}, -}; - - -static struct regfield_info - glbl_rng_sz_5_field_info[] = { - {"GLBL_RNG_SZ_5_RSVD_1", - GLBL_RNG_SZ_5_RSVD_1_MASK}, - {"GLBL_RNG_SZ_5_RING_SIZE", - GLBL_RNG_SZ_5_RING_SIZE_MASK}, -}; - - -static struct regfield_info - glbl_rng_sz_6_field_info[] = { - {"GLBL_RNG_SZ_6_RSVD_1", - GLBL_RNG_SZ_6_RSVD_1_MASK}, - {"GLBL_RNG_SZ_6_RING_SIZE", - GLBL_RNG_SZ_6_RING_SIZE_MASK}, -}; - - -static struct regfield_info - glbl_rng_sz_7_field_info[] = { - {"GLBL_RNG_SZ_7_RSVD_1", - GLBL_RNG_SZ_7_RSVD_1_MASK}, - {"GLBL_RNG_SZ_7_RING_SIZE", - GLBL_RNG_SZ_7_RING_SIZE_MASK}, -}; - - -static struct regfield_info - glbl_rng_sz_8_field_info[] = { - {"GLBL_RNG_SZ_8_RSVD_1", - GLBL_RNG_SZ_8_RSVD_1_MASK}, - {"GLBL_RNG_SZ_8_RING_SIZE", - GLBL_RNG_SZ_8_RING_SIZE_MASK}, -}; - - -static struct regfield_info - glbl_rng_sz_9_field_info[] = { - {"GLBL_RNG_SZ_9_RSVD_1", - GLBL_RNG_SZ_9_RSVD_1_MASK}, - {"GLBL_RNG_SZ_9_RING_SIZE", - GLBL_RNG_SZ_9_RING_SIZE_MASK}, -}; - - -static struct regfield_info - glbl_rng_sz_a_field_info[] = { - {"GLBL_RNG_SZ_A_RSVD_1", - GLBL_RNG_SZ_A_RSVD_1_MASK}, - {"GLBL_RNG_SZ_A_RING_SIZE", - GLBL_RNG_SZ_A_RING_SIZE_MASK}, -}; - - -static struct regfield_info - glbl_rng_sz_b_field_info[] = { - {"GLBL_RNG_SZ_B_RSVD_1", - GLBL_RNG_SZ_B_RSVD_1_MASK}, - {"GLBL_RNG_SZ_B_RING_SIZE", - GLBL_RNG_SZ_B_RING_SIZE_MASK}, -}; - - -static struct regfield_info - glbl_rng_sz_c_field_info[] = { - {"GLBL_RNG_SZ_C_RSVD_1", - GLBL_RNG_SZ_C_RSVD_1_MASK}, - {"GLBL_RNG_SZ_C_RING_SIZE", - GLBL_RNG_SZ_C_RING_SIZE_MASK}, -}; - - -static struct regfield_info - glbl_rng_sz_d_field_info[] = { - {"GLBL_RNG_SZ_D_RSVD_1", - GLBL_RNG_SZ_D_RSVD_1_MASK}, - {"GLBL_RNG_SZ_D_RING_SIZE", - GLBL_RNG_SZ_D_RING_SIZE_MASK}, -}; - - -static struct regfield_info - glbl_rng_sz_e_field_info[] = { - {"GLBL_RNG_SZ_E_RSVD_1", - GLBL_RNG_SZ_E_RSVD_1_MASK}, - {"GLBL_RNG_SZ_E_RING_SIZE", - GLBL_RNG_SZ_E_RING_SIZE_MASK}, -}; - - -static struct regfield_info - glbl_rng_sz_f_field_info[] = { - {"GLBL_RNG_SZ_F_RSVD_1", - GLBL_RNG_SZ_F_RSVD_1_MASK}, - {"GLBL_RNG_SZ_F_RING_SIZE", - GLBL_RNG_SZ_F_RING_SIZE_MASK}, -}; - - -static struct regfield_info - glbl_rng_sz_10_field_info[] = { - {"GLBL_RNG_SZ_10_RSVD_1", - GLBL_RNG_SZ_10_RSVD_1_MASK}, - {"GLBL_RNG_SZ_10_RING_SIZE", - GLBL_RNG_SZ_10_RING_SIZE_MASK}, -}; - - -static struct regfield_info - glbl_err_stat_field_info[] = { - {"GLBL_ERR_STAT_RSVD_1", - GLBL_ERR_STAT_RSVD_1_MASK}, - {"GLBL_ERR_STAT_ERR_FAB", - GLBL_ERR_STAT_ERR_FAB_MASK}, - {"GLBL_ERR_STAT_ERR_H2C_ST", - GLBL_ERR_STAT_ERR_H2C_ST_MASK}, - {"GLBL_ERR_STAT_ERR_BDG", - GLBL_ERR_STAT_ERR_BDG_MASK}, - {"GLBL_ERR_STAT_IND_CTXT_CMD_ERR", - GLBL_ERR_STAT_IND_CTXT_CMD_ERR_MASK}, - {"GLBL_ERR_STAT_ERR_C2H_ST", - GLBL_ERR_STAT_ERR_C2H_ST_MASK}, - {"GLBL_ERR_STAT_ERR_C2H_MM_1", - GLBL_ERR_STAT_ERR_C2H_MM_1_MASK}, - {"GLBL_ERR_STAT_ERR_C2H_MM_0", - GLBL_ERR_STAT_ERR_C2H_MM_0_MASK}, - {"GLBL_ERR_STAT_ERR_H2C_MM_1", - GLBL_ERR_STAT_ERR_H2C_MM_1_MASK}, - {"GLBL_ERR_STAT_ERR_H2C_MM_0", - GLBL_ERR_STAT_ERR_H2C_MM_0_MASK}, - {"GLBL_ERR_STAT_ERR_TRQ", - GLBL_ERR_STAT_ERR_TRQ_MASK}, - {"GLBL_ERR_STAT_ERR_DSC", - GLBL_ERR_STAT_ERR_DSC_MASK}, - {"GLBL_ERR_STAT_ERR_RAM_DBE", - GLBL_ERR_STAT_ERR_RAM_DBE_MASK}, - {"GLBL_ERR_STAT_ERR_RAM_SBE", - GLBL_ERR_STAT_ERR_RAM_SBE_MASK}, -}; - - -static struct regfield_info - glbl_err_mask_field_info[] = { - {"GLBL_ERR", - GLBL_ERR_MASK}, -}; - - -static struct regfield_info - glbl_dsc_cfg_field_info[] = { - {"GLBL_DSC_CFG_RSVD_1", - GLBL_DSC_CFG_RSVD_1_MASK}, - {"GLBL_DSC_CFG_UNC_OVR_COR", - GLBL_DSC_CFG_UNC_OVR_COR_MASK}, - {"GLBL_DSC_CFG_CTXT_FER_DIS", - GLBL_DSC_CFG_CTXT_FER_DIS_MASK}, - {"GLBL_DSC_CFG_RSVD_2", - GLBL_DSC_CFG_RSVD_2_MASK}, - {"GLBL_DSC_CFG_MAXFETCH", - GLBL_DSC_CFG_MAXFETCH_MASK}, - {"GLBL_DSC_CFG_WB_ACC_INT", - GLBL_DSC_CFG_WB_ACC_INT_MASK}, -}; - - -static struct regfield_info - glbl_dsc_err_sts_field_info[] = { - {"GLBL_DSC_ERR_STS_RSVD_1", - GLBL_DSC_ERR_STS_RSVD_1_MASK}, - {"GLBL_DSC_ERR_STS_PORT_ID", - GLBL_DSC_ERR_STS_PORT_ID_MASK}, - {"GLBL_DSC_ERR_STS_SBE", - GLBL_DSC_ERR_STS_SBE_MASK}, - {"GLBL_DSC_ERR_STS_DBE", - GLBL_DSC_ERR_STS_DBE_MASK}, - {"GLBL_DSC_ERR_STS_RQ_CANCEL", - GLBL_DSC_ERR_STS_RQ_CANCEL_MASK}, - {"GLBL_DSC_ERR_STS_DSC", - GLBL_DSC_ERR_STS_DSC_MASK}, - {"GLBL_DSC_ERR_STS_DMA", - GLBL_DSC_ERR_STS_DMA_MASK}, - {"GLBL_DSC_ERR_STS_FLR_CANCEL", - GLBL_DSC_ERR_STS_FLR_CANCEL_MASK}, - {"GLBL_DSC_ERR_STS_RSVD_2", - GLBL_DSC_ERR_STS_RSVD_2_MASK}, - {"GLBL_DSC_ERR_STS_DAT_POISON", - GLBL_DSC_ERR_STS_DAT_POISON_MASK}, - {"GLBL_DSC_ERR_STS_TIMEOUT", - GLBL_DSC_ERR_STS_TIMEOUT_MASK}, - {"GLBL_DSC_ERR_STS_FLR", - GLBL_DSC_ERR_STS_FLR_MASK}, - {"GLBL_DSC_ERR_STS_TAG", - GLBL_DSC_ERR_STS_TAG_MASK}, - {"GLBL_DSC_ERR_STS_ADDR", - GLBL_DSC_ERR_STS_ADDR_MASK}, - {"GLBL_DSC_ERR_STS_PARAM", - GLBL_DSC_ERR_STS_PARAM_MASK}, - {"GLBL_DSC_ERR_STS_BCNT", - GLBL_DSC_ERR_STS_BCNT_MASK}, - {"GLBL_DSC_ERR_STS_UR_CA", - GLBL_DSC_ERR_STS_UR_CA_MASK}, - {"GLBL_DSC_ERR_STS_POISON", - GLBL_DSC_ERR_STS_POISON_MASK}, -}; - - -static struct regfield_info - glbl_dsc_err_msk_field_info[] = { - {"GLBL_DSC_ERR_MSK", - GLBL_DSC_ERR_MSK_MASK}, -}; - - -static struct regfield_info - glbl_dsc_err_log0_field_info[] = { - {"GLBL_DSC_ERR_LOG0_VALID", - GLBL_DSC_ERR_LOG0_VALID_MASK}, - {"GLBL_DSC_ERR_LOG0_SEL", - GLBL_DSC_ERR_LOG0_SEL_MASK}, - {"GLBL_DSC_ERR_LOG0_RSVD_1", - GLBL_DSC_ERR_LOG0_RSVD_1_MASK}, - {"GLBL_DSC_ERR_LOG0_QID", - GLBL_DSC_ERR_LOG0_QID_MASK}, -}; - - -static struct regfield_info - glbl_dsc_err_log1_field_info[] = { - {"GLBL_DSC_ERR_LOG1_RSVD_1", - GLBL_DSC_ERR_LOG1_RSVD_1_MASK}, - {"GLBL_DSC_ERR_LOG1_CIDX", - GLBL_DSC_ERR_LOG1_CIDX_MASK}, - {"GLBL_DSC_ERR_LOG1_RSVD_2", - GLBL_DSC_ERR_LOG1_RSVD_2_MASK}, - {"GLBL_DSC_ERR_LOG1_SUB_TYPE", - GLBL_DSC_ERR_LOG1_SUB_TYPE_MASK}, - {"GLBL_DSC_ERR_LOG1_ERR_TYPE", - GLBL_DSC_ERR_LOG1_ERR_TYPE_MASK}, -}; - - -static struct regfield_info - glbl_trq_err_sts_field_info[] = { - {"GLBL_TRQ_ERR_STS_RSVD_1", - GLBL_TRQ_ERR_STS_RSVD_1_MASK}, - {"GLBL_TRQ_ERR_STS_TCP_QSPC_TIMEOUT", - GLBL_TRQ_ERR_STS_TCP_QSPC_TIMEOUT_MASK}, - {"GLBL_TRQ_ERR_STS_RSVD_2", - GLBL_TRQ_ERR_STS_RSVD_2_MASK}, - {"GLBL_TRQ_ERR_STS_QID_RANGE", - GLBL_TRQ_ERR_STS_QID_RANGE_MASK}, - {"GLBL_TRQ_ERR_STS_QSPC_UNMAPPED", - GLBL_TRQ_ERR_STS_QSPC_UNMAPPED_MASK}, - {"GLBL_TRQ_ERR_STS_TCP_CSR_TIMEOUT", - GLBL_TRQ_ERR_STS_TCP_CSR_TIMEOUT_MASK}, - {"GLBL_TRQ_ERR_STS_RSVD_3", - GLBL_TRQ_ERR_STS_RSVD_3_MASK}, - {"GLBL_TRQ_ERR_STS_VF_ACCESS_ERR", - GLBL_TRQ_ERR_STS_VF_ACCESS_ERR_MASK}, - {"GLBL_TRQ_ERR_STS_CSR_UNMAPPED", - GLBL_TRQ_ERR_STS_CSR_UNMAPPED_MASK}, -}; - - -static struct regfield_info - glbl_trq_err_msk_field_info[] = { - {"GLBL_TRQ_ERR_MSK", - GLBL_TRQ_ERR_MSK_MASK}, -}; - - -static struct regfield_info - glbl_trq_err_log_field_info[] = { - {"GLBL_TRQ_ERR_LOG_SRC", - GLBL_TRQ_ERR_LOG_SRC_MASK}, - {"GLBL_TRQ_ERR_LOG_TARGET", - GLBL_TRQ_ERR_LOG_TARGET_MASK}, - {"GLBL_TRQ_ERR_LOG_FUNC", - GLBL_TRQ_ERR_LOG_FUNC_MASK}, - {"GLBL_TRQ_ERR_LOG_ADDRESS", - GLBL_TRQ_ERR_LOG_ADDRESS_MASK}, -}; - - -static struct regfield_info - glbl_dsc_dbg_dat0_field_info[] = { - {"GLBL_DSC_DAT0_RSVD_1", - GLBL_DSC_DAT0_RSVD_1_MASK}, - {"GLBL_DSC_DAT0_CTXT_ARB_DIR", - GLBL_DSC_DAT0_CTXT_ARB_DIR_MASK}, - {"GLBL_DSC_DAT0_CTXT_ARB_QID", - GLBL_DSC_DAT0_CTXT_ARB_QID_MASK}, - {"GLBL_DSC_DAT0_CTXT_ARB_REQ", - GLBL_DSC_DAT0_CTXT_ARB_REQ_MASK}, - {"GLBL_DSC_DAT0_IRQ_FIFO_FL", - GLBL_DSC_DAT0_IRQ_FIFO_FL_MASK}, - {"GLBL_DSC_DAT0_TMSTALL", - GLBL_DSC_DAT0_TMSTALL_MASK}, - {"GLBL_DSC_DAT0_RRQ_STALL", - GLBL_DSC_DAT0_RRQ_STALL_MASK}, - {"GLBL_DSC_DAT0_RCP_FIFO_SPC_STALL", - GLBL_DSC_DAT0_RCP_FIFO_SPC_STALL_MASK}, - {"GLBL_DSC_DAT0_RRQ_FIFO_SPC_STALL", - GLBL_DSC_DAT0_RRQ_FIFO_SPC_STALL_MASK}, - {"GLBL_DSC_DAT0_FAB_MRKR_RSP_STALL", - GLBL_DSC_DAT0_FAB_MRKR_RSP_STALL_MASK}, - {"GLBL_DSC_DAT0_DSC_OUT_STALL", - GLBL_DSC_DAT0_DSC_OUT_STALL_MASK}, -}; - - -static struct regfield_info - glbl_dsc_dbg_dat1_field_info[] = { - {"GLBL_DSC_DAT1_RSVD_1", - GLBL_DSC_DAT1_RSVD_1_MASK}, - {"GLBL_DSC_DAT1_EVT_SPC_C2H", - GLBL_DSC_DAT1_EVT_SPC_C2H_MASK}, - {"GLBL_DSC_DAT1_EVT_SP_H2C", - GLBL_DSC_DAT1_EVT_SP_H2C_MASK}, - {"GLBL_DSC_DAT1_DSC_SPC_C2H", - GLBL_DSC_DAT1_DSC_SPC_C2H_MASK}, - {"GLBL_DSC_DAT1_DSC_SPC_H2C", - GLBL_DSC_DAT1_DSC_SPC_H2C_MASK}, -}; - - -static struct regfield_info - glbl_dsc_dbg_ctl_field_info[] = { - {"GLBL_DSC_CTL_RSVD_1", - GLBL_DSC_CTL_RSVD_1_MASK}, - {"GLBL_DSC_CTL_SELECT", - GLBL_DSC_CTL_SELECT_MASK}, -}; - - -static struct regfield_info - glbl_dsc_err_log2_field_info[] = { - {"GLBL_DSC_ERR_LOG2_OLD_PIDX", - GLBL_DSC_ERR_LOG2_OLD_PIDX_MASK}, - {"GLBL_DSC_ERR_LOG2_NEW_PIDX", - GLBL_DSC_ERR_LOG2_NEW_PIDX_MASK}, -}; - - -static struct regfield_info - glbl_glbl_interrupt_cfg_field_info[] = { - {"GLBL_GLBL_INTERRUPT_CFG_RSVD_1", - GLBL_GLBL_INTERRUPT_CFG_RSVD_1_MASK}, - {"GLBL_GLBL_INTERRUPT_CFG_LGCY_INTR_PENDING", - GLBL_GLBL_INTERRUPT_CFG_LGCY_INTR_PENDING_MASK}, - {"GLBL_GLBL_INTERRUPT_CFG_EN_LGCY_INTR", - GLBL_GLBL_INTERRUPT_CFG_EN_LGCY_INTR_MASK}, -}; - - -static struct regfield_info - glbl_vch_host_profile_field_info[] = { - {"GLBL_VCH_HOST_PROFILE_RSVD_1", - GLBL_VCH_HOST_PROFILE_RSVD_1_MASK}, - {"GLBL_VCH_HOST_PROFILE_2C_MM", - GLBL_VCH_HOST_PROFILE_2C_MM_MASK}, - {"GLBL_VCH_HOST_PROFILE_2C_ST", - GLBL_VCH_HOST_PROFILE_2C_ST_MASK}, - {"GLBL_VCH_HOST_PROFILE_VCH_DSC", - GLBL_VCH_HOST_PROFILE_VCH_DSC_MASK}, - {"GLBL_VCH_HOST_PROFILE_VCH_INT_MSG", - GLBL_VCH_HOST_PROFILE_VCH_INT_MSG_MASK}, - {"GLBL_VCH_HOST_PROFILE_VCH_INT_AGGR", - GLBL_VCH_HOST_PROFILE_VCH_INT_AGGR_MASK}, - {"GLBL_VCH_HOST_PROFILE_VCH_CMPT", - GLBL_VCH_HOST_PROFILE_VCH_CMPT_MASK}, - {"GLBL_VCH_HOST_PROFILE_VCH_C2H_PLD", - GLBL_VCH_HOST_PROFILE_VCH_C2H_PLD_MASK}, -}; - - -static struct regfield_info - glbl_bridge_host_profile_field_info[] = { - {"GLBL_BRIDGE_HOST_PROFILE_RSVD_1", - GLBL_BRIDGE_HOST_PROFILE_RSVD_1_MASK}, - {"GLBL_BRIDGE_HOST_PROFILE_BDGID", - GLBL_BRIDGE_HOST_PROFILE_BDGID_MASK}, -}; - - -static struct regfield_info - aximm_irq_dest_addr_field_info[] = { - {"AXIMM_IRQ_DEST_ADDR_ADDR", - AXIMM_IRQ_DEST_ADDR_ADDR_MASK}, -}; - - -static struct regfield_info - fab_err_log_field_info[] = { - {"FAB_ERR_LOG_RSVD_1", - FAB_ERR_LOG_RSVD_1_MASK}, - {"FAB_ERR_LOG_SRC", - FAB_ERR_LOG_SRC_MASK}, -}; - - -static struct regfield_info - ind_ctxt_data_field_info[] = { - {"IND_CTXT_DATA_DATA", - IND_CTXT_DATA_DATA_MASK}, -}; - - -static struct regfield_info - ind_ctxt_mask_field_info[] = { - {"IND_CTXT", - IND_CTXT_MASK}, -}; - - -static struct regfield_info - ind_ctxt_cmd_field_info[] = { - {"IND_CTXT_CMD_RSVD_1", - IND_CTXT_CMD_RSVD_1_MASK}, - {"IND_CTXT_CMD_QID", - IND_CTXT_CMD_QID_MASK}, - {"IND_CTXT_CMD_OP", - IND_CTXT_CMD_OP_MASK}, - {"IND_CTXT_CMD_SEL", - IND_CTXT_CMD_SEL_MASK}, - {"IND_CTXT_CMD_BUSY", - IND_CTXT_CMD_BUSY_MASK}, -}; - - -static struct regfield_info - c2h_timer_cnt_field_info[] = { - {"C2H_TIMER_CNT_RSVD_1", - C2H_TIMER_CNT_RSVD_1_MASK}, - {"C2H_TIMER_CNT", - C2H_TIMER_CNT_MASK}, -}; - - -static struct regfield_info - c2h_cnt_th_field_info[] = { - {"C2H_CNT_TH_RSVD_1", - C2H_CNT_TH_RSVD_1_MASK}, - {"C2H_CNT_TH_THESHOLD_CNT", - C2H_CNT_TH_THESHOLD_CNT_MASK}, -}; - - -static struct regfield_info - c2h_stat_s_axis_c2h_accepted_field_info[] = { - {"C2H_STAT_S_AXIS_C2H_ACCEPTED_RSVD_1", - C2H_STAT_S_AXIS_C2H_ACCEPTED_RSVD_1_MASK}, - {"C2H_STAT_S_AXIS_C2H_ACCEPTED", - C2H_STAT_S_AXIS_C2H_ACCEPTED_MASK}, -}; - - -static struct regfield_info - c2h_stat_s_axis_wrb_accepted_field_info[] = { - {"C2H_STAT_S_AXIS_WRB_ACCEPTED_RSVD_1", - C2H_STAT_S_AXIS_WRB_ACCEPTED_RSVD_1_MASK}, - {"C2H_STAT_S_AXIS_WRB_ACCEPTED", - C2H_STAT_S_AXIS_WRB_ACCEPTED_MASK}, -}; - - -static struct regfield_info - c2h_stat_desc_rsp_pkt_accepted_field_info[] = { - {"C2H_STAT_DESC_RSP_PKT_ACCEPTED_RSVD_1", - C2H_STAT_DESC_RSP_PKT_ACCEPTED_RSVD_1_MASK}, - {"C2H_STAT_DESC_RSP_PKT_ACCEPTED_D", - C2H_STAT_DESC_RSP_PKT_ACCEPTED_D_MASK}, -}; - - -static struct regfield_info - c2h_stat_axis_pkg_cmp_field_info[] = { - {"C2H_STAT_AXIS_PKG_CMP_RSVD_1", - C2H_STAT_AXIS_PKG_CMP_RSVD_1_MASK}, - {"C2H_STAT_AXIS_PKG_CMP", - C2H_STAT_AXIS_PKG_CMP_MASK}, -}; - - -static struct regfield_info - c2h_stat_desc_rsp_accepted_field_info[] = { - {"C2H_STAT_DESC_RSP_ACCEPTED_RSVD_1", - C2H_STAT_DESC_RSP_ACCEPTED_RSVD_1_MASK}, - {"C2H_STAT_DESC_RSP_ACCEPTED_D", - C2H_STAT_DESC_RSP_ACCEPTED_D_MASK}, -}; - - -static struct regfield_info - c2h_stat_desc_rsp_cmp_field_info[] = { - {"C2H_STAT_DESC_RSP_CMP_RSVD_1", - C2H_STAT_DESC_RSP_CMP_RSVD_1_MASK}, - {"C2H_STAT_DESC_RSP_CMP_D", - C2H_STAT_DESC_RSP_CMP_D_MASK}, -}; - - -static struct regfield_info - c2h_stat_wrq_out_field_info[] = { - {"C2H_STAT_WRQ_OUT_RSVD_1", - C2H_STAT_WRQ_OUT_RSVD_1_MASK}, - {"C2H_STAT_WRQ_OUT", - C2H_STAT_WRQ_OUT_MASK}, -}; - - -static struct regfield_info - c2h_stat_wpl_ren_accepted_field_info[] = { - {"C2H_STAT_WPL_REN_ACCEPTED_RSVD_1", - C2H_STAT_WPL_REN_ACCEPTED_RSVD_1_MASK}, - {"C2H_STAT_WPL_REN_ACCEPTED", - C2H_STAT_WPL_REN_ACCEPTED_MASK}, -}; - - -static struct regfield_info - c2h_stat_total_wrq_len_field_info[] = { - {"C2H_STAT_TOTAL_WRQ_LEN_RSVD_1", - C2H_STAT_TOTAL_WRQ_LEN_RSVD_1_MASK}, - {"C2H_STAT_TOTAL_WRQ_LEN", - C2H_STAT_TOTAL_WRQ_LEN_MASK}, -}; - - -static struct regfield_info - c2h_stat_total_wpl_len_field_info[] = { - {"C2H_STAT_TOTAL_WPL_LEN_RSVD_1", - C2H_STAT_TOTAL_WPL_LEN_RSVD_1_MASK}, - {"C2H_STAT_TOTAL_WPL_LEN", - C2H_STAT_TOTAL_WPL_LEN_MASK}, -}; - - -static struct regfield_info - c2h_buf_sz_field_info[] = { - {"C2H_BUF_SZ_IZE", - C2H_BUF_SZ_IZE_MASK}, -}; - - -static struct regfield_info - c2h_err_stat_field_info[] = { - {"C2H_ERR_STAT_RSVD_1", - C2H_ERR_STAT_RSVD_1_MASK}, - {"C2H_ERR_STAT_WRB_PORT_ID_ERR", - C2H_ERR_STAT_WRB_PORT_ID_ERR_MASK}, - {"C2H_ERR_STAT_HDR_PAR_ERR", - C2H_ERR_STAT_HDR_PAR_ERR_MASK}, - {"C2H_ERR_STAT_HDR_ECC_COR_ERR", - C2H_ERR_STAT_HDR_ECC_COR_ERR_MASK}, - {"C2H_ERR_STAT_HDR_ECC_UNC_ERR", - C2H_ERR_STAT_HDR_ECC_UNC_ERR_MASK}, - {"C2H_ERR_STAT_AVL_RING_DSC_ERR", - C2H_ERR_STAT_AVL_RING_DSC_ERR_MASK}, - {"C2H_ERR_STAT_WRB_PRTY_ERR", - C2H_ERR_STAT_WRB_PRTY_ERR_MASK}, - {"C2H_ERR_STAT_WRB_CIDX_ERR", - C2H_ERR_STAT_WRB_CIDX_ERR_MASK}, - {"C2H_ERR_STAT_WRB_QFULL_ERR", - C2H_ERR_STAT_WRB_QFULL_ERR_MASK}, - {"C2H_ERR_STAT_WRB_INV_Q_ERR", - C2H_ERR_STAT_WRB_INV_Q_ERR_MASK}, - {"C2H_ERR_STAT_RSVD_2", - C2H_ERR_STAT_RSVD_2_MASK}, - {"C2H_ERR_STAT_PORT_ID_CTXT_MISMATCH", - C2H_ERR_STAT_PORT_ID_CTXT_MISMATCH_MASK}, - {"C2H_ERR_STAT_ERR_DESC_CNT", - C2H_ERR_STAT_ERR_DESC_CNT_MASK}, - {"C2H_ERR_STAT_RSVD_3", - C2H_ERR_STAT_RSVD_3_MASK}, - {"C2H_ERR_STAT_MSI_INT_FAIL", - C2H_ERR_STAT_MSI_INT_FAIL_MASK}, - {"C2H_ERR_STAT_ENG_WPL_DATA_PAR_ERR", - C2H_ERR_STAT_ENG_WPL_DATA_PAR_ERR_MASK}, - {"C2H_ERR_STAT_RSVD_4", - C2H_ERR_STAT_RSVD_4_MASK}, - {"C2H_ERR_STAT_DESC_RSP_ERR", - C2H_ERR_STAT_DESC_RSP_ERR_MASK}, - {"C2H_ERR_STAT_QID_MISMATCH", - C2H_ERR_STAT_QID_MISMATCH_MASK}, - {"C2H_ERR_STAT_SH_CMPT_DSC_ERR", - C2H_ERR_STAT_SH_CMPT_DSC_ERR_MASK}, - {"C2H_ERR_STAT_LEN_MISMATCH", - C2H_ERR_STAT_LEN_MISMATCH_MASK}, - {"C2H_ERR_STAT_MTY_MISMATCH", - C2H_ERR_STAT_MTY_MISMATCH_MASK}, -}; - - -static struct regfield_info - c2h_err_mask_field_info[] = { - {"C2H_ERR_EN", - C2H_ERR_EN_MASK}, -}; - - -static struct regfield_info - c2h_fatal_err_stat_field_info[] = { - {"C2H_FATAL_ERR_STAT_RSVD_1", - C2H_FATAL_ERR_STAT_RSVD_1_MASK}, - {"C2H_FATAL_ERR_STAT_HDR_ECC_UNC_ERR", - C2H_FATAL_ERR_STAT_HDR_ECC_UNC_ERR_MASK}, - {"C2H_FATAL_ERR_STAT_AVL_RING_FIFO_RAM_RDBE", - C2H_FATAL_ERR_STAT_AVL_RING_FIFO_RAM_RDBE_MASK}, - {"C2H_FATAL_ERR_STAT_WPL_DATA_PAR_ERR", - C2H_FATAL_ERR_STAT_WPL_DATA_PAR_ERR_MASK}, - {"C2H_FATAL_ERR_STAT_PLD_FIFO_RAM_RDBE", - C2H_FATAL_ERR_STAT_PLD_FIFO_RAM_RDBE_MASK}, - {"C2H_FATAL_ERR_STAT_QID_FIFO_RAM_RDBE", - C2H_FATAL_ERR_STAT_QID_FIFO_RAM_RDBE_MASK}, - {"C2H_FATAL_ERR_STAT_CMPT_FIFO_RAM_RDBE", - C2H_FATAL_ERR_STAT_CMPT_FIFO_RAM_RDBE_MASK}, - {"C2H_FATAL_ERR_STAT_WRB_COAL_DATA_RAM_RDBE", - C2H_FATAL_ERR_STAT_WRB_COAL_DATA_RAM_RDBE_MASK}, - {"C2H_FATAL_ERR_STAT_RESERVED2", - C2H_FATAL_ERR_STAT_RESERVED2_MASK}, - {"C2H_FATAL_ERR_STAT_INT_CTXT_RAM_RDBE", - C2H_FATAL_ERR_STAT_INT_CTXT_RAM_RDBE_MASK}, - {"C2H_FATAL_ERR_STAT_DESC_REQ_FIFO_RAM_RDBE", - C2H_FATAL_ERR_STAT_DESC_REQ_FIFO_RAM_RDBE_MASK}, - {"C2H_FATAL_ERR_STAT_PFCH_CTXT_RAM_RDBE", - C2H_FATAL_ERR_STAT_PFCH_CTXT_RAM_RDBE_MASK}, - {"C2H_FATAL_ERR_STAT_WRB_CTXT_RAM_RDBE", - C2H_FATAL_ERR_STAT_WRB_CTXT_RAM_RDBE_MASK}, - {"C2H_FATAL_ERR_STAT_PFCH_LL_RAM_RDBE", - C2H_FATAL_ERR_STAT_PFCH_LL_RAM_RDBE_MASK}, - {"C2H_FATAL_ERR_STAT_TIMER_FIFO_RAM_RDBE", - C2H_FATAL_ERR_STAT_TIMER_FIFO_RAM_RDBE_MASK}, - {"C2H_FATAL_ERR_STAT_QID_MISMATCH", - C2H_FATAL_ERR_STAT_QID_MISMATCH_MASK}, - {"C2H_FATAL_ERR_STAT_RESERVED1", - C2H_FATAL_ERR_STAT_RESERVED1_MASK}, - {"C2H_FATAL_ERR_STAT_LEN_MISMATCH", - C2H_FATAL_ERR_STAT_LEN_MISMATCH_MASK}, - {"C2H_FATAL_ERR_STAT_MTY_MISMATCH", - C2H_FATAL_ERR_STAT_MTY_MISMATCH_MASK}, -}; - - -static struct regfield_info - c2h_fatal_err_mask_field_info[] = { - {"C2H_FATAL_ERR_C2HEN", - C2H_FATAL_ERR_C2HEN_MASK}, -}; - - -static struct regfield_info - c2h_fatal_err_enable_field_info[] = { - {"C2H_FATAL_ERR_ENABLE_RSVD_1", - C2H_FATAL_ERR_ENABLE_RSVD_1_MASK}, - {"C2H_FATAL_ERR_ENABLE_WPL_PAR_INV", - C2H_FATAL_ERR_ENABLE_WPL_PAR_INV_MASK}, - {"C2H_FATAL_ERR_ENABLE_WRQ_DIS", - C2H_FATAL_ERR_ENABLE_WRQ_DIS_MASK}, -}; - - -static struct regfield_info - glbl_err_int_field_info[] = { - {"GLBL_ERR_INT_RSVD_1", - GLBL_ERR_INT_RSVD_1_MASK}, - {"GLBL_ERR_INT_HOST_ID", - GLBL_ERR_INT_HOST_ID_MASK}, - {"GLBL_ERR_INT_DIS_INTR_ON_VF", - GLBL_ERR_INT_DIS_INTR_ON_VF_MASK}, - {"GLBL_ERR_INT_ARM", - GLBL_ERR_INT_ARM_MASK}, - {"GLBL_ERR_INT_EN_COAL", - GLBL_ERR_INT_EN_COAL_MASK}, - {"GLBL_ERR_INT_VEC", - GLBL_ERR_INT_VEC_MASK}, - {"GLBL_ERR_INT_FUNC", - GLBL_ERR_INT_FUNC_MASK}, -}; - - -static struct regfield_info - c2h_pfch_cfg_field_info[] = { - {"C2H_PFCH_CFG_EVTFL_TH", - C2H_PFCH_CFG_EVTFL_TH_MASK}, - {"C2H_PFCH_CFG_FL_TH", - C2H_PFCH_CFG_FL_TH_MASK}, -}; - - -static struct regfield_info - c2h_pfch_cfg_1_field_info[] = { - {"C2H_PFCH_CFG_1_EVT_QCNT_TH", - C2H_PFCH_CFG_1_EVT_QCNT_TH_MASK}, - {"C2H_PFCH_CFG_1_QCNT", - C2H_PFCH_CFG_1_QCNT_MASK}, -}; - - -static struct regfield_info - c2h_pfch_cfg_2_field_info[] = { - {"C2H_PFCH_CFG_2_FENCE", - C2H_PFCH_CFG_2_FENCE_MASK}, - {"C2H_PFCH_CFG_2_RSVD", - C2H_PFCH_CFG_2_RSVD_MASK}, - {"C2H_PFCH_CFG_2_VAR_DESC_NO_DROP", - C2H_PFCH_CFG_2_VAR_DESC_NO_DROP_MASK}, - {"C2H_PFCH_CFG_2_LL_SZ_TH", - C2H_PFCH_CFG_2_LL_SZ_TH_MASK}, - {"C2H_PFCH_CFG_2_VAR_DESC_NUM", - C2H_PFCH_CFG_2_VAR_DESC_NUM_MASK}, - {"C2H_PFCH_CFG_2_NUM", - C2H_PFCH_CFG_2_NUM_MASK}, -}; - - -static struct regfield_info - c2h_int_timer_tick_field_info[] = { - {"C2H_INT_TIMER_TICK", - C2H_INT_TIMER_TICK_MASK}, -}; - - -static struct regfield_info - c2h_stat_desc_rsp_drop_accepted_field_info[] = { - {"C2H_STAT_DESC_RSP_DROP_ACCEPTED_RSVD_1", - C2H_STAT_DESC_RSP_DROP_ACCEPTED_RSVD_1_MASK}, - {"C2H_STAT_DESC_RSP_DROP_ACCEPTED_D", - C2H_STAT_DESC_RSP_DROP_ACCEPTED_D_MASK}, -}; - - -static struct regfield_info - c2h_stat_desc_rsp_err_accepted_field_info[] = { - {"C2H_STAT_DESC_RSP_ERR_ACCEPTED_RSVD_1", - C2H_STAT_DESC_RSP_ERR_ACCEPTED_RSVD_1_MASK}, - {"C2H_STAT_DESC_RSP_ERR_ACCEPTED_D", - C2H_STAT_DESC_RSP_ERR_ACCEPTED_D_MASK}, -}; - - -static struct regfield_info - c2h_stat_desc_req_field_info[] = { - {"C2H_STAT_DESC_REQ_RSVD_1", - C2H_STAT_DESC_REQ_RSVD_1_MASK}, - {"C2H_STAT_DESC_REQ", - C2H_STAT_DESC_REQ_MASK}, -}; - - -static struct regfield_info - c2h_stat_dbg_dma_eng_0_field_info[] = { - {"C2H_STAT_DMA_ENG_0_S_AXIS_C2H_TVALID", - C2H_STAT_DMA_ENG_0_S_AXIS_C2H_TVALID_MASK}, - {"C2H_STAT_DMA_ENG_0_S_AXIS_C2H_TREADY", - C2H_STAT_DMA_ENG_0_S_AXIS_C2H_TREADY_MASK}, - {"C2H_STAT_DMA_ENG_0_S_AXIS_WRB_TVALID", - C2H_STAT_DMA_ENG_0_S_AXIS_WRB_TVALID_MASK}, - {"C2H_STAT_DMA_ENG_0_S_AXIS_WRB_TREADY", - C2H_STAT_DMA_ENG_0_S_AXIS_WRB_TREADY_MASK}, - {"C2H_STAT_DMA_ENG_0_PLD_FIFO_IN_RDY", - C2H_STAT_DMA_ENG_0_PLD_FIFO_IN_RDY_MASK}, - {"C2H_STAT_DMA_ENG_0_QID_FIFO_IN_RDY", - C2H_STAT_DMA_ENG_0_QID_FIFO_IN_RDY_MASK}, - {"C2H_STAT_DMA_ENG_0_ARB_FIFO_OUT_VLD", - C2H_STAT_DMA_ENG_0_ARB_FIFO_OUT_VLD_MASK}, - {"C2H_STAT_DMA_ENG_0_ARB_FIFO_OUT_QID", - C2H_STAT_DMA_ENG_0_ARB_FIFO_OUT_QID_MASK}, - {"C2H_STAT_DMA_ENG_0_WRB_FIFO_IN_RDY", - C2H_STAT_DMA_ENG_0_WRB_FIFO_IN_RDY_MASK}, - {"C2H_STAT_DMA_ENG_0_WRB_FIFO_OUT_CNT", - C2H_STAT_DMA_ENG_0_WRB_FIFO_OUT_CNT_MASK}, - {"C2H_STAT_DMA_ENG_0_WRB_SM_CS", - C2H_STAT_DMA_ENG_0_WRB_SM_CS_MASK}, - {"C2H_STAT_DMA_ENG_0_MAIN_SM_CS", - C2H_STAT_DMA_ENG_0_MAIN_SM_CS_MASK}, -}; - - -static struct regfield_info - c2h_stat_dbg_dma_eng_1_field_info[] = { - {"C2H_STAT_DMA_ENG_1_RSVD_1", - C2H_STAT_DMA_ENG_1_RSVD_1_MASK}, - {"C2H_STAT_DMA_ENG_1_QID_FIFO_OUT_CNT", - C2H_STAT_DMA_ENG_1_QID_FIFO_OUT_CNT_MASK}, - {"C2H_STAT_DMA_ENG_1_PLD_FIFO_OUT_CNT", - C2H_STAT_DMA_ENG_1_PLD_FIFO_OUT_CNT_MASK}, - {"C2H_STAT_DMA_ENG_1_PLD_ST_FIFO_CNT", - C2H_STAT_DMA_ENG_1_PLD_ST_FIFO_CNT_MASK}, -}; - - -static struct regfield_info - c2h_stat_dbg_dma_eng_2_field_info[] = { - {"C2H_STAT_DMA_ENG_2_RSVD_1", - C2H_STAT_DMA_ENG_2_RSVD_1_MASK}, - {"C2H_STAT_DMA_ENG_2_QID_FIFO_OUT_CNT", - C2H_STAT_DMA_ENG_2_QID_FIFO_OUT_CNT_MASK}, - {"C2H_STAT_DMA_ENG_2_PLD_FIFO_OUT_CNT", - C2H_STAT_DMA_ENG_2_PLD_FIFO_OUT_CNT_MASK}, - {"C2H_STAT_DMA_ENG_2_PLD_ST_FIFO_CNT", - C2H_STAT_DMA_ENG_2_PLD_ST_FIFO_CNT_MASK}, -}; - - -static struct regfield_info - c2h_stat_dbg_dma_eng_3_field_info[] = { - {"C2H_STAT_DMA_ENG_3_RSVD_1", - C2H_STAT_DMA_ENG_3_RSVD_1_MASK}, - {"C2H_STAT_DMA_ENG_3_WRQ_FIFO_OUT_CNT", - C2H_STAT_DMA_ENG_3_WRQ_FIFO_OUT_CNT_MASK}, - {"C2H_STAT_DMA_ENG_3_QID_FIFO_OUT_VLD", - C2H_STAT_DMA_ENG_3_QID_FIFO_OUT_VLD_MASK}, - {"C2H_STAT_DMA_ENG_3_PLD_FIFO_OUT_VLD", - C2H_STAT_DMA_ENG_3_PLD_FIFO_OUT_VLD_MASK}, - {"C2H_STAT_DMA_ENG_3_PLD_ST_FIFO_OUT_VLD", - C2H_STAT_DMA_ENG_3_PLD_ST_FIFO_OUT_VLD_MASK}, - {"C2H_STAT_DMA_ENG_3_PLD_ST_FIFO_OUT_DATA_EOP", - C2H_STAT_DMA_ENG_3_PLD_ST_FIFO_OUT_DATA_EOP_MASK}, - {"C2H_STAT_DMA_ENG_3_PLD_ST_FIFO_OUT_DATA_AVL_IDX_ENABLE", - C2H_STAT_DMA_ENG_3_PLD_ST_FIFO_OUT_DATA_AVL_IDX_ENABLE_MASK}, - {"C2H_STAT_DMA_ENG_3_PLD_ST_FIFO_OUT_DATA_DROP", - C2H_STAT_DMA_ENG_3_PLD_ST_FIFO_OUT_DATA_DROP_MASK}, - {"C2H_STAT_DMA_ENG_3_PLD_ST_FIFO_OUT_DATA_ERR", - C2H_STAT_DMA_ENG_3_PLD_ST_FIFO_OUT_DATA_ERR_MASK}, - {"C2H_STAT_DMA_ENG_3_DESC_CNT_FIFO_IN_RDY", - C2H_STAT_DMA_ENG_3_DESC_CNT_FIFO_IN_RDY_MASK}, - {"C2H_STAT_DMA_ENG_3_DESC_RSP_FIFO_IN_RDY", - C2H_STAT_DMA_ENG_3_DESC_RSP_FIFO_IN_RDY_MASK}, - {"C2H_STAT_DMA_ENG_3_PLD_PKT_ID_LARGER_0", - C2H_STAT_DMA_ENG_3_PLD_PKT_ID_LARGER_0_MASK}, - {"C2H_STAT_DMA_ENG_3_WRQ_VLD", - C2H_STAT_DMA_ENG_3_WRQ_VLD_MASK}, - {"C2H_STAT_DMA_ENG_3_WRQ_RDY", - C2H_STAT_DMA_ENG_3_WRQ_RDY_MASK}, - {"C2H_STAT_DMA_ENG_3_WRQ_FIFO_OUT_RDY", - C2H_STAT_DMA_ENG_3_WRQ_FIFO_OUT_RDY_MASK}, - {"C2H_STAT_DMA_ENG_3_WRQ_PACKET_OUT_DATA_DROP", - C2H_STAT_DMA_ENG_3_WRQ_PACKET_OUT_DATA_DROP_MASK}, - {"C2H_STAT_DMA_ENG_3_WRQ_PACKET_OUT_DATA_ERR", - C2H_STAT_DMA_ENG_3_WRQ_PACKET_OUT_DATA_ERR_MASK}, - {"C2H_STAT_DMA_ENG_3_WRQ_PACKET_OUT_DATA_MARKER", - C2H_STAT_DMA_ENG_3_WRQ_PACKET_OUT_DATA_MARKER_MASK}, - {"C2H_STAT_DMA_ENG_3_WRQ_PACKET_PRE_EOR", - C2H_STAT_DMA_ENG_3_WRQ_PACKET_PRE_EOR_MASK}, - {"C2H_STAT_DMA_ENG_3_WCP_FIFO_IN_RDY", - C2H_STAT_DMA_ENG_3_WCP_FIFO_IN_RDY_MASK}, - {"C2H_STAT_DMA_ENG_3_PLD_ST_FIFO_IN_RDY", - C2H_STAT_DMA_ENG_3_PLD_ST_FIFO_IN_RDY_MASK}, -}; - - -static struct regfield_info - c2h_dbg_pfch_err_ctxt_field_info[] = { - {"C2H_PFCH_ERR_CTXT_RSVD_1", - C2H_PFCH_ERR_CTXT_RSVD_1_MASK}, - {"C2H_PFCH_ERR_CTXT_ERR_STAT", - C2H_PFCH_ERR_CTXT_ERR_STAT_MASK}, - {"C2H_PFCH_ERR_CTXT_CMD_WR", - C2H_PFCH_ERR_CTXT_CMD_WR_MASK}, - {"C2H_PFCH_ERR_CTXT_QID", - C2H_PFCH_ERR_CTXT_QID_MASK}, - {"C2H_PFCH_ERR_CTXT_DONE", - C2H_PFCH_ERR_CTXT_DONE_MASK}, -}; - - -static struct regfield_info - c2h_first_err_qid_field_info[] = { - {"C2H_FIRST_ERR_QID_RSVD_1", - C2H_FIRST_ERR_QID_RSVD_1_MASK}, - {"C2H_FIRST_ERR_QID_ERR_TYPE", - C2H_FIRST_ERR_QID_ERR_TYPE_MASK}, - {"C2H_FIRST_ERR_QID_RSVD", - C2H_FIRST_ERR_QID_RSVD_MASK}, - {"C2H_FIRST_ERR_QID_QID", - C2H_FIRST_ERR_QID_QID_MASK}, -}; - - -static struct regfield_info - stat_num_wrb_in_field_info[] = { - {"STAT_NUM_WRB_IN_RSVD_1", - STAT_NUM_WRB_IN_RSVD_1_MASK}, - {"STAT_NUM_WRB_IN_WRB_CNT", - STAT_NUM_WRB_IN_WRB_CNT_MASK}, -}; - - -static struct regfield_info - stat_num_wrb_out_field_info[] = { - {"STAT_NUM_WRB_OUT_RSVD_1", - STAT_NUM_WRB_OUT_RSVD_1_MASK}, - {"STAT_NUM_WRB_OUT_WRB_CNT", - STAT_NUM_WRB_OUT_WRB_CNT_MASK}, -}; - - -static struct regfield_info - stat_num_wrb_drp_field_info[] = { - {"STAT_NUM_WRB_DRP_RSVD_1", - STAT_NUM_WRB_DRP_RSVD_1_MASK}, - {"STAT_NUM_WRB_DRP_WRB_CNT", - STAT_NUM_WRB_DRP_WRB_CNT_MASK}, -}; - - -static struct regfield_info - stat_num_stat_desc_out_field_info[] = { - {"STAT_NUM_STAT_DESC_OUT_RSVD_1", - STAT_NUM_STAT_DESC_OUT_RSVD_1_MASK}, - {"STAT_NUM_STAT_DESC_OUT_CNT", - STAT_NUM_STAT_DESC_OUT_CNT_MASK}, -}; - - -static struct regfield_info - stat_num_dsc_crdt_sent_field_info[] = { - {"STAT_NUM_DSC_CRDT_SENT_RSVD_1", - STAT_NUM_DSC_CRDT_SENT_RSVD_1_MASK}, - {"STAT_NUM_DSC_CRDT_SENT_CNT", - STAT_NUM_DSC_CRDT_SENT_CNT_MASK}, -}; - - -static struct regfield_info - stat_num_fch_dsc_rcvd_field_info[] = { - {"STAT_NUM_FCH_DSC_RCVD_RSVD_1", - STAT_NUM_FCH_DSC_RCVD_RSVD_1_MASK}, - {"STAT_NUM_FCH_DSC_RCVD_DSC_CNT", - STAT_NUM_FCH_DSC_RCVD_DSC_CNT_MASK}, -}; - - -static struct regfield_info - stat_num_byp_dsc_rcvd_field_info[] = { - {"STAT_NUM_BYP_DSC_RCVD_RSVD_1", - STAT_NUM_BYP_DSC_RCVD_RSVD_1_MASK}, - {"STAT_NUM_BYP_DSC_RCVD_DSC_CNT", - STAT_NUM_BYP_DSC_RCVD_DSC_CNT_MASK}, -}; - - -static struct regfield_info - c2h_wrb_coal_cfg_field_info[] = { - {"C2H_WRB_COAL_CFG_MAX_BUF_SZ", - C2H_WRB_COAL_CFG_MAX_BUF_SZ_MASK}, - {"C2H_WRB_COAL_CFG_TICK_VAL", - C2H_WRB_COAL_CFG_TICK_VAL_MASK}, - {"C2H_WRB_COAL_CFG_TICK_CNT", - C2H_WRB_COAL_CFG_TICK_CNT_MASK}, - {"C2H_WRB_COAL_CFG_SET_GLB_FLUSH", - C2H_WRB_COAL_CFG_SET_GLB_FLUSH_MASK}, - {"C2H_WRB_COAL_CFG_DONE_GLB_FLUSH", - C2H_WRB_COAL_CFG_DONE_GLB_FLUSH_MASK}, -}; - - -static struct regfield_info - c2h_intr_h2c_req_field_info[] = { - {"C2H_INTR_H2C_REQ_RSVD_1", - C2H_INTR_H2C_REQ_RSVD_1_MASK}, - {"C2H_INTR_H2C_REQ_CNT", - C2H_INTR_H2C_REQ_CNT_MASK}, -}; - - -static struct regfield_info - c2h_intr_c2h_mm_req_field_info[] = { - {"C2H_INTR_C2H_MM_REQ_RSVD_1", - C2H_INTR_C2H_MM_REQ_RSVD_1_MASK}, - {"C2H_INTR_C2H_MM_REQ_CNT", - C2H_INTR_C2H_MM_REQ_CNT_MASK}, -}; - - -static struct regfield_info - c2h_intr_err_int_req_field_info[] = { - {"C2H_INTR_ERR_INT_REQ_RSVD_1", - C2H_INTR_ERR_INT_REQ_RSVD_1_MASK}, - {"C2H_INTR_ERR_INT_REQ_CNT", - C2H_INTR_ERR_INT_REQ_CNT_MASK}, -}; - - -static struct regfield_info - c2h_intr_c2h_st_req_field_info[] = { - {"C2H_INTR_C2H_ST_REQ_RSVD_1", - C2H_INTR_C2H_ST_REQ_RSVD_1_MASK}, - {"C2H_INTR_C2H_ST_REQ_CNT", - C2H_INTR_C2H_ST_REQ_CNT_MASK}, -}; - - -static struct regfield_info - c2h_intr_h2c_err_c2h_mm_msix_ack_field_info[] = { - {"C2H_INTR_H2C_ERR_C2H_MM_MSIX_ACK_RSVD_1", - C2H_INTR_H2C_ERR_C2H_MM_MSIX_ACK_RSVD_1_MASK}, - {"C2H_INTR_H2C_ERR_C2H_MM_MSIX_ACK_CNT", - C2H_INTR_H2C_ERR_C2H_MM_MSIX_ACK_CNT_MASK}, -}; - - -static struct regfield_info - c2h_intr_h2c_err_c2h_mm_msix_fail_field_info[] = { - {"C2H_INTR_H2C_ERR_C2H_MM_MSIX_FAIL_RSVD_1", - C2H_INTR_H2C_ERR_C2H_MM_MSIX_FAIL_RSVD_1_MASK}, - {"C2H_INTR_H2C_ERR_C2H_MM_MSIX_FAIL_CNT", - C2H_INTR_H2C_ERR_C2H_MM_MSIX_FAIL_CNT_MASK}, -}; - - -static struct regfield_info - c2h_intr_h2c_err_c2h_mm_msix_no_msix_field_info[] = { - {"C2H_INTR_H2C_ERR_C2H_MM_MSIX_NO_MSIX_RSVD_1", - C2H_INTR_H2C_ERR_C2H_MM_MSIX_NO_MSIX_RSVD_1_MASK}, - {"C2H_INTR_H2C_ERR_C2H_MM_MSIX_NO_MSIX_CNT", - C2H_INTR_H2C_ERR_C2H_MM_MSIX_NO_MSIX_CNT_MASK}, -}; - - -static struct regfield_info - c2h_intr_h2c_err_c2h_mm_ctxt_inval_field_info[] = { - {"C2H_INTR_H2C_ERR_C2H_MM_CTXT_INVAL_RSVD_1", - C2H_INTR_H2C_ERR_C2H_MM_CTXT_INVAL_RSVD_1_MASK}, - {"C2H_INTR_H2C_ERR_C2H_MM_CTXT_INVAL_CNT", - C2H_INTR_H2C_ERR_C2H_MM_CTXT_INVAL_CNT_MASK}, -}; - - -static struct regfield_info - c2h_intr_c2h_st_msix_ack_field_info[] = { - {"C2H_INTR_C2H_ST_MSIX_ACK_RSVD_1", - C2H_INTR_C2H_ST_MSIX_ACK_RSVD_1_MASK}, - {"C2H_INTR_C2H_ST_MSIX_ACK_CNT", - C2H_INTR_C2H_ST_MSIX_ACK_CNT_MASK}, -}; - - -static struct regfield_info - c2h_intr_c2h_st_msix_fail_field_info[] = { - {"C2H_INTR_C2H_ST_MSIX_FAIL_RSVD_1", - C2H_INTR_C2H_ST_MSIX_FAIL_RSVD_1_MASK}, - {"C2H_INTR_C2H_ST_MSIX_FAIL_CNT", - C2H_INTR_C2H_ST_MSIX_FAIL_CNT_MASK}, -}; - - -static struct regfield_info - c2h_intr_c2h_st_no_msix_field_info[] = { - {"C2H_INTR_C2H_ST_NO_MSIX_RSVD_1", - C2H_INTR_C2H_ST_NO_MSIX_RSVD_1_MASK}, - {"C2H_INTR_C2H_ST_NO_MSIX_CNT", - C2H_INTR_C2H_ST_NO_MSIX_CNT_MASK}, -}; - - -static struct regfield_info - c2h_intr_c2h_st_ctxt_inval_field_info[] = { - {"C2H_INTR_C2H_ST_CTXT_INVAL_RSVD_1", - C2H_INTR_C2H_ST_CTXT_INVAL_RSVD_1_MASK}, - {"C2H_INTR_C2H_ST_CTXT_INVAL_CNT", - C2H_INTR_C2H_ST_CTXT_INVAL_CNT_MASK}, -}; - - -static struct regfield_info - c2h_stat_wr_cmp_field_info[] = { - {"C2H_STAT_WR_CMP_RSVD_1", - C2H_STAT_WR_CMP_RSVD_1_MASK}, - {"C2H_STAT_WR_CMP_CNT", - C2H_STAT_WR_CMP_CNT_MASK}, -}; - - -static struct regfield_info - c2h_stat_dbg_dma_eng_4_field_info[] = { - {"C2H_STAT_DMA_ENG_4_RSVD_1", - C2H_STAT_DMA_ENG_4_RSVD_1_MASK}, - {"C2H_STAT_DMA_ENG_4_WRQ_FIFO_OUT_CNT", - C2H_STAT_DMA_ENG_4_WRQ_FIFO_OUT_CNT_MASK}, - {"C2H_STAT_DMA_ENG_4_QID_FIFO_OUT_VLD", - C2H_STAT_DMA_ENG_4_QID_FIFO_OUT_VLD_MASK}, - {"C2H_STAT_DMA_ENG_4_PLD_FIFO_OUT_VLD", - C2H_STAT_DMA_ENG_4_PLD_FIFO_OUT_VLD_MASK}, - {"C2H_STAT_DMA_ENG_4_PLD_ST_FIFO_OUT_VLD", - C2H_STAT_DMA_ENG_4_PLD_ST_FIFO_OUT_VLD_MASK}, - {"C2H_STAT_DMA_ENG_4_PLD_ST_FIFO_OUT_DATA_EOP", - C2H_STAT_DMA_ENG_4_PLD_ST_FIFO_OUT_DATA_EOP_MASK}, - {"C2H_STAT_DMA_ENG_4_PLD_ST_FIFO_OUT_DATA_AVL_IDX_ENABLE", - C2H_STAT_DMA_ENG_4_PLD_ST_FIFO_OUT_DATA_AVL_IDX_ENABLE_MASK}, - {"C2H_STAT_DMA_ENG_4_PLD_ST_FIFO_OUT_DATA_DROP", - C2H_STAT_DMA_ENG_4_PLD_ST_FIFO_OUT_DATA_DROP_MASK}, - {"C2H_STAT_DMA_ENG_4_PLD_ST_FIFO_OUT_DATA_ERR", - C2H_STAT_DMA_ENG_4_PLD_ST_FIFO_OUT_DATA_ERR_MASK}, - {"C2H_STAT_DMA_ENG_4_DESC_CNT_FIFO_IN_RDY", - C2H_STAT_DMA_ENG_4_DESC_CNT_FIFO_IN_RDY_MASK}, - {"C2H_STAT_DMA_ENG_4_DESC_RSP_FIFO_IN_RDY", - C2H_STAT_DMA_ENG_4_DESC_RSP_FIFO_IN_RDY_MASK}, - {"C2H_STAT_DMA_ENG_4_PLD_PKT_ID_LARGER_0", - C2H_STAT_DMA_ENG_4_PLD_PKT_ID_LARGER_0_MASK}, - {"C2H_STAT_DMA_ENG_4_WRQ_VLD", - C2H_STAT_DMA_ENG_4_WRQ_VLD_MASK}, - {"C2H_STAT_DMA_ENG_4_WRQ_RDY", - C2H_STAT_DMA_ENG_4_WRQ_RDY_MASK}, - {"C2H_STAT_DMA_ENG_4_WRQ_FIFO_OUT_RDY", - C2H_STAT_DMA_ENG_4_WRQ_FIFO_OUT_RDY_MASK}, - {"C2H_STAT_DMA_ENG_4_WRQ_PACKET_OUT_DATA_DROP", - C2H_STAT_DMA_ENG_4_WRQ_PACKET_OUT_DATA_DROP_MASK}, - {"C2H_STAT_DMA_ENG_4_WRQ_PACKET_OUT_DATA_ERR", - C2H_STAT_DMA_ENG_4_WRQ_PACKET_OUT_DATA_ERR_MASK}, - {"C2H_STAT_DMA_ENG_4_WRQ_PACKET_OUT_DATA_MARKER", - C2H_STAT_DMA_ENG_4_WRQ_PACKET_OUT_DATA_MARKER_MASK}, - {"C2H_STAT_DMA_ENG_4_WRQ_PACKET_PRE_EOR", - C2H_STAT_DMA_ENG_4_WRQ_PACKET_PRE_EOR_MASK}, - {"C2H_STAT_DMA_ENG_4_WCP_FIFO_IN_RDY", - C2H_STAT_DMA_ENG_4_WCP_FIFO_IN_RDY_MASK}, - {"C2H_STAT_DMA_ENG_4_PLD_ST_FIFO_IN_RDY", - C2H_STAT_DMA_ENG_4_PLD_ST_FIFO_IN_RDY_MASK}, -}; - - -static struct regfield_info - c2h_stat_dbg_dma_eng_5_field_info[] = { - {"C2H_STAT_DMA_ENG_5_RSVD_1", - C2H_STAT_DMA_ENG_5_RSVD_1_MASK}, - {"C2H_STAT_DMA_ENG_5_WRB_SM_VIRT_CH", - C2H_STAT_DMA_ENG_5_WRB_SM_VIRT_CH_MASK}, - {"C2H_STAT_DMA_ENG_5_WRB_FIFO_IN_REQ", - C2H_STAT_DMA_ENG_5_WRB_FIFO_IN_REQ_MASK}, - {"C2H_STAT_DMA_ENG_5_ARB_FIFO_OUT_CNT", - C2H_STAT_DMA_ENG_5_ARB_FIFO_OUT_CNT_MASK}, - {"C2H_STAT_DMA_ENG_5_ARB_FIFO_OUT_DATA_LEN", - C2H_STAT_DMA_ENG_5_ARB_FIFO_OUT_DATA_LEN_MASK}, - {"C2H_STAT_DMA_ENG_5_ARB_FIFO_OUT_DATA_VIRT_CH", - C2H_STAT_DMA_ENG_5_ARB_FIFO_OUT_DATA_VIRT_CH_MASK}, - {"C2H_STAT_DMA_ENG_5_ARB_FIFO_OUT_DATA_VAR_DESC", - C2H_STAT_DMA_ENG_5_ARB_FIFO_OUT_DATA_VAR_DESC_MASK}, - {"C2H_STAT_DMA_ENG_5_ARB_FIFO_OUT_DATA_DROP_REQ", - C2H_STAT_DMA_ENG_5_ARB_FIFO_OUT_DATA_DROP_REQ_MASK}, - {"C2H_STAT_DMA_ENG_5_ARB_FIFO_OUT_DATA_NUM_BUF_OV", - C2H_STAT_DMA_ENG_5_ARB_FIFO_OUT_DATA_NUM_BUF_OV_MASK}, - {"C2H_STAT_DMA_ENG_5_ARB_FIFO_OUT_DATA_MARKER", - C2H_STAT_DMA_ENG_5_ARB_FIFO_OUT_DATA_MARKER_MASK}, - {"C2H_STAT_DMA_ENG_5_ARB_FIFO_OUT_DATA_HAS_CMPT", - C2H_STAT_DMA_ENG_5_ARB_FIFO_OUT_DATA_HAS_CMPT_MASK}, -}; - - -static struct regfield_info - c2h_dbg_pfch_qid_field_info[] = { - {"C2H_PFCH_QID_RSVD_1", - C2H_PFCH_QID_RSVD_1_MASK}, - {"C2H_PFCH_QID_ERR_CTXT", - C2H_PFCH_QID_ERR_CTXT_MASK}, - {"C2H_PFCH_QID_TARGET", - C2H_PFCH_QID_TARGET_MASK}, - {"C2H_PFCH_QID_QID_OR_TAG", - C2H_PFCH_QID_QID_OR_TAG_MASK}, -}; - - -static struct regfield_info - c2h_dbg_pfch_field_info[] = { - {"C2H_PFCH_DATA", - C2H_PFCH_DATA_MASK}, -}; - - -static struct regfield_info - c2h_int_dbg_field_info[] = { - {"C2H_INT_RSVD_1", - C2H_INT_RSVD_1_MASK}, - {"C2H_INT_INT_COAL_SM", - C2H_INT_INT_COAL_SM_MASK}, - {"C2H_INT_INT_SM", - C2H_INT_INT_SM_MASK}, -}; - - -static struct regfield_info - c2h_stat_imm_accepted_field_info[] = { - {"C2H_STAT_IMM_ACCEPTED_RSVD_1", - C2H_STAT_IMM_ACCEPTED_RSVD_1_MASK}, - {"C2H_STAT_IMM_ACCEPTED_CNT", - C2H_STAT_IMM_ACCEPTED_CNT_MASK}, -}; - - -static struct regfield_info - c2h_stat_marker_accepted_field_info[] = { - {"C2H_STAT_MARKER_ACCEPTED_RSVD_1", - C2H_STAT_MARKER_ACCEPTED_RSVD_1_MASK}, - {"C2H_STAT_MARKER_ACCEPTED_CNT", - C2H_STAT_MARKER_ACCEPTED_CNT_MASK}, -}; - - -static struct regfield_info - c2h_stat_disable_cmp_accepted_field_info[] = { - {"C2H_STAT_DISABLE_CMP_ACCEPTED_RSVD_1", - C2H_STAT_DISABLE_CMP_ACCEPTED_RSVD_1_MASK}, - {"C2H_STAT_DISABLE_CMP_ACCEPTED_CNT", - C2H_STAT_DISABLE_CMP_ACCEPTED_CNT_MASK}, -}; - - -static struct regfield_info - c2h_pld_fifo_crdt_cnt_field_info[] = { - {"C2H_PLD_FIFO_CRDT_CNT_RSVD_1", - C2H_PLD_FIFO_CRDT_CNT_RSVD_1_MASK}, - {"C2H_PLD_FIFO_CRDT_CNT_CNT", - C2H_PLD_FIFO_CRDT_CNT_CNT_MASK}, -}; - - -static struct regfield_info - c2h_intr_dyn_req_field_info[] = { - {"C2H_INTR_DYN_REQ_RSVD_1", - C2H_INTR_DYN_REQ_RSVD_1_MASK}, - {"C2H_INTR_DYN_REQ_CNT", - C2H_INTR_DYN_REQ_CNT_MASK}, -}; - - -static struct regfield_info - c2h_intr_dyn_misc_field_info[] = { - {"C2H_INTR_DYN_MISC_RSVD_1", - C2H_INTR_DYN_MISC_RSVD_1_MASK}, - {"C2H_INTR_DYN_MISC_CNT", - C2H_INTR_DYN_MISC_CNT_MASK}, -}; - - -static struct regfield_info - c2h_drop_len_mismatch_field_info[] = { - {"C2H_DROP_LEN_MISMATCH_RSVD_1", - C2H_DROP_LEN_MISMATCH_RSVD_1_MASK}, - {"C2H_DROP_LEN_MISMATCH_CNT", - C2H_DROP_LEN_MISMATCH_CNT_MASK}, -}; - - -static struct regfield_info - c2h_drop_desc_rsp_len_field_info[] = { - {"C2H_DROP_DESC_RSP_LEN_RSVD_1", - C2H_DROP_DESC_RSP_LEN_RSVD_1_MASK}, - {"C2H_DROP_DESC_RSP_LEN_CNT", - C2H_DROP_DESC_RSP_LEN_CNT_MASK}, -}; - - -static struct regfield_info - c2h_drop_qid_fifo_len_field_info[] = { - {"C2H_DROP_QID_FIFO_LEN_RSVD_1", - C2H_DROP_QID_FIFO_LEN_RSVD_1_MASK}, - {"C2H_DROP_QID_FIFO_LEN_CNT", - C2H_DROP_QID_FIFO_LEN_CNT_MASK}, -}; - - -static struct regfield_info - c2h_drop_pld_cnt_field_info[] = { - {"C2H_DROP_PLD_CNT_RSVD_1", - C2H_DROP_PLD_CNT_RSVD_1_MASK}, - {"C2H_DROP_PLD_CNT_CNT", - C2H_DROP_PLD_CNT_CNT_MASK}, -}; - - -static struct regfield_info - c2h_cmpt_format_0_field_info[] = { - {"C2H_CMPT_FORMAT_0_DESC_ERR_LOC", - C2H_CMPT_FORMAT_0_DESC_ERR_LOC_MASK}, - {"C2H_CMPT_FORMAT_0_COLOR_LOC", - C2H_CMPT_FORMAT_0_COLOR_LOC_MASK}, -}; - - -static struct regfield_info - c2h_cmpt_format_1_field_info[] = { - {"C2H_CMPT_FORMAT_1_DESC_ERR_LOC", - C2H_CMPT_FORMAT_1_DESC_ERR_LOC_MASK}, - {"C2H_CMPT_FORMAT_1_COLOR_LOC", - C2H_CMPT_FORMAT_1_COLOR_LOC_MASK}, -}; - - -static struct regfield_info - c2h_cmpt_format_2_field_info[] = { - {"C2H_CMPT_FORMAT_2_DESC_ERR_LOC", - C2H_CMPT_FORMAT_2_DESC_ERR_LOC_MASK}, - {"C2H_CMPT_FORMAT_2_COLOR_LOC", - C2H_CMPT_FORMAT_2_COLOR_LOC_MASK}, -}; - - -static struct regfield_info - c2h_cmpt_format_3_field_info[] = { - {"C2H_CMPT_FORMAT_3_DESC_ERR_LOC", - C2H_CMPT_FORMAT_3_DESC_ERR_LOC_MASK}, - {"C2H_CMPT_FORMAT_3_COLOR_LOC", - C2H_CMPT_FORMAT_3_COLOR_LOC_MASK}, -}; - - -static struct regfield_info - c2h_cmpt_format_4_field_info[] = { - {"C2H_CMPT_FORMAT_4_DESC_ERR_LOC", - C2H_CMPT_FORMAT_4_DESC_ERR_LOC_MASK}, - {"C2H_CMPT_FORMAT_4_COLOR_LOC", - C2H_CMPT_FORMAT_4_COLOR_LOC_MASK}, -}; - - -static struct regfield_info - c2h_cmpt_format_5_field_info[] = { - {"C2H_CMPT_FORMAT_5_DESC_ERR_LOC", - C2H_CMPT_FORMAT_5_DESC_ERR_LOC_MASK}, - {"C2H_CMPT_FORMAT_5_COLOR_LOC", - C2H_CMPT_FORMAT_5_COLOR_LOC_MASK}, -}; - - -static struct regfield_info - c2h_cmpt_format_6_field_info[] = { - {"C2H_CMPT_FORMAT_6_DESC_ERR_LOC", - C2H_CMPT_FORMAT_6_DESC_ERR_LOC_MASK}, - {"C2H_CMPT_FORMAT_6_COLOR_LOC", - C2H_CMPT_FORMAT_6_COLOR_LOC_MASK}, -}; - - -static struct regfield_info - c2h_pfch_cache_depth_field_info[] = { - {"C2H_PFCH_CACHE_DEPTH_MAX_STBUF", - C2H_PFCH_CACHE_DEPTH_MAX_STBUF_MASK}, - {"C2H_PFCH_CACHE_DEPTH", - C2H_PFCH_CACHE_DEPTH_MASK}, -}; - - -static struct regfield_info - c2h_wrb_coal_buf_depth_field_info[] = { - {"C2H_WRB_COAL_BUF_DEPTH_RSVD_1", - C2H_WRB_COAL_BUF_DEPTH_RSVD_1_MASK}, - {"C2H_WRB_COAL_BUF_DEPTH_BUFFER", - C2H_WRB_COAL_BUF_DEPTH_BUFFER_MASK}, -}; - - -static struct regfield_info - c2h_pfch_crdt_field_info[] = { - {"C2H_PFCH_CRDT_RSVD_1", - C2H_PFCH_CRDT_RSVD_1_MASK}, - {"C2H_PFCH_CRDT_RSVD_2", - C2H_PFCH_CRDT_RSVD_2_MASK}, -}; - - -static struct regfield_info - c2h_stat_has_cmpt_accepted_field_info[] = { - {"C2H_STAT_HAS_CMPT_ACCEPTED_RSVD_1", - C2H_STAT_HAS_CMPT_ACCEPTED_RSVD_1_MASK}, - {"C2H_STAT_HAS_CMPT_ACCEPTED_CNT", - C2H_STAT_HAS_CMPT_ACCEPTED_CNT_MASK}, -}; - - -static struct regfield_info - c2h_stat_has_pld_accepted_field_info[] = { - {"C2H_STAT_HAS_PLD_ACCEPTED_RSVD_1", - C2H_STAT_HAS_PLD_ACCEPTED_RSVD_1_MASK}, - {"C2H_STAT_HAS_PLD_ACCEPTED_CNT", - C2H_STAT_HAS_PLD_ACCEPTED_CNT_MASK}, -}; - - -static struct regfield_info - c2h_pld_pkt_id_field_info[] = { - {"C2H_PLD_PKT_ID_CMPT_WAIT", - C2H_PLD_PKT_ID_CMPT_WAIT_MASK}, - {"C2H_PLD_PKT_ID_DATA", - C2H_PLD_PKT_ID_DATA_MASK}, -}; - - -static struct regfield_info - c2h_pld_pkt_id_1_field_info[] = { - {"C2H_PLD_PKT_ID_1_CMPT_WAIT", - C2H_PLD_PKT_ID_1_CMPT_WAIT_MASK}, - {"C2H_PLD_PKT_ID_1_DATA", - C2H_PLD_PKT_ID_1_DATA_MASK}, -}; - - -static struct regfield_info - c2h_drop_pld_cnt_1_field_info[] = { - {"C2H_DROP_PLD_CNT_1_RSVD_1", - C2H_DROP_PLD_CNT_1_RSVD_1_MASK}, - {"C2H_DROP_PLD_CNT_1_CNT", - C2H_DROP_PLD_CNT_1_CNT_MASK}, -}; - - -static struct regfield_info - h2c_err_stat_field_info[] = { - {"H2C_ERR_STAT_RSVD_1", - H2C_ERR_STAT_RSVD_1_MASK}, - {"H2C_ERR_STAT_PAR_ERR", - H2C_ERR_STAT_PAR_ERR_MASK}, - {"H2C_ERR_STAT_SBE", - H2C_ERR_STAT_SBE_MASK}, - {"H2C_ERR_STAT_DBE", - H2C_ERR_STAT_DBE_MASK}, - {"H2C_ERR_STAT_NO_DMA_DS", - H2C_ERR_STAT_NO_DMA_DS_MASK}, - {"H2C_ERR_STAT_SDI_MRKR_REQ_MOP_ERR", - H2C_ERR_STAT_SDI_MRKR_REQ_MOP_ERR_MASK}, - {"H2C_ERR_STAT_ZERO_LEN_DS", - H2C_ERR_STAT_ZERO_LEN_DS_MASK}, -}; - - -static struct regfield_info - h2c_err_mask_field_info[] = { - {"H2C_ERR_EN", - H2C_ERR_EN_MASK}, -}; - - -static struct regfield_info - h2c_first_err_qid_field_info[] = { - {"H2C_FIRST_ERR_QID_RSVD_1", - H2C_FIRST_ERR_QID_RSVD_1_MASK}, - {"H2C_FIRST_ERR_QID_ERR_TYPE", - H2C_FIRST_ERR_QID_ERR_TYPE_MASK}, - {"H2C_FIRST_ERR_QID_RSVD_2", - H2C_FIRST_ERR_QID_RSVD_2_MASK}, - {"H2C_FIRST_ERR_QID_QID", - H2C_FIRST_ERR_QID_QID_MASK}, -}; - - -static struct regfield_info - h2c_dbg_reg0_field_info[] = { - {"H2C_REG0_NUM_DSC_RCVD", - H2C_REG0_NUM_DSC_RCVD_MASK}, - {"H2C_REG0_NUM_WRB_SENT", - H2C_REG0_NUM_WRB_SENT_MASK}, -}; - - -static struct regfield_info - h2c_dbg_reg1_field_info[] = { - {"H2C_REG1_NUM_REQ_SENT", - H2C_REG1_NUM_REQ_SENT_MASK}, - {"H2C_REG1_NUM_CMP_SENT", - H2C_REG1_NUM_CMP_SENT_MASK}, -}; - - -static struct regfield_info - h2c_dbg_reg2_field_info[] = { - {"H2C_REG2_RSVD_1", - H2C_REG2_RSVD_1_MASK}, - {"H2C_REG2_NUM_ERR_DSC_RCVD", - H2C_REG2_NUM_ERR_DSC_RCVD_MASK}, -}; - - -static struct regfield_info - h2c_dbg_reg3_field_info[] = { - {"H2C_REG3_RSVD_1", - H2C_REG3_RSVD_1_MASK}, - {"H2C_REG3_DSCO_FIFO_EMPTY", - H2C_REG3_DSCO_FIFO_EMPTY_MASK}, - {"H2C_REG3_DSCO_FIFO_FULL", - H2C_REG3_DSCO_FIFO_FULL_MASK}, - {"H2C_REG3_CUR_RC_STATE", - H2C_REG3_CUR_RC_STATE_MASK}, - {"H2C_REG3_RDREQ_LINES", - H2C_REG3_RDREQ_LINES_MASK}, - {"H2C_REG3_RDATA_LINES_AVAIL", - H2C_REG3_RDATA_LINES_AVAIL_MASK}, - {"H2C_REG3_PEND_FIFO_EMPTY", - H2C_REG3_PEND_FIFO_EMPTY_MASK}, - {"H2C_REG3_PEND_FIFO_FULL", - H2C_REG3_PEND_FIFO_FULL_MASK}, - {"H2C_REG3_CUR_RQ_STATE", - H2C_REG3_CUR_RQ_STATE_MASK}, - {"H2C_REG3_DSCI_FIFO_FULL", - H2C_REG3_DSCI_FIFO_FULL_MASK}, - {"H2C_REG3_DSCI_FIFO_EMPTY", - H2C_REG3_DSCI_FIFO_EMPTY_MASK}, -}; - - -static struct regfield_info - h2c_dbg_reg4_field_info[] = { - {"H2C_REG4_RDREQ_ADDR", - H2C_REG4_RDREQ_ADDR_MASK}, -}; - - -static struct regfield_info - h2c_fatal_err_en_field_info[] = { - {"H2C_FATAL_ERR_EN_RSVD_1", - H2C_FATAL_ERR_EN_RSVD_1_MASK}, - {"H2C_FATAL_ERR_EN_H2C", - H2C_FATAL_ERR_EN_H2C_MASK}, -}; - - -static struct regfield_info - h2c_req_throt_pcie_field_info[] = { - {"H2C_REQ_THROT_PCIE_EN_REQ", - H2C_REQ_THROT_PCIE_EN_REQ_MASK}, - {"H2C_REQ_THROT_PCIE", - H2C_REQ_THROT_PCIE_MASK}, - {"H2C_REQ_THROT_PCIE_EN_DATA", - H2C_REQ_THROT_PCIE_EN_DATA_MASK}, - {"H2C_REQ_THROT_PCIE_DATA_THRESH", - H2C_REQ_THROT_PCIE_DATA_THRESH_MASK}, -}; - - -static struct regfield_info - h2c_aln_dbg_reg0_field_info[] = { - {"H2C_ALN_REG0_NUM_PKT_SENT", - H2C_ALN_REG0_NUM_PKT_SENT_MASK}, -}; - - -static struct regfield_info - h2c_req_throt_aximm_field_info[] = { - {"H2C_REQ_THROT_AXIMM_EN_REQ", - H2C_REQ_THROT_AXIMM_EN_REQ_MASK}, - {"H2C_REQ_THROT_AXIMM", - H2C_REQ_THROT_AXIMM_MASK}, - {"H2C_REQ_THROT_AXIMM_EN_DATA", - H2C_REQ_THROT_AXIMM_EN_DATA_MASK}, - {"H2C_REQ_THROT_AXIMM_DATA_THRESH", - H2C_REQ_THROT_AXIMM_DATA_THRESH_MASK}, -}; - - -static struct regfield_info - c2h_mm_ctl_field_info[] = { - {"C2H_MM_CTL_RESERVED1", - C2H_MM_CTL_RESERVED1_MASK}, - {"C2H_MM_CTL_ERRC_EN", - C2H_MM_CTL_ERRC_EN_MASK}, - {"C2H_MM_CTL_RESERVED0", - C2H_MM_CTL_RESERVED0_MASK}, - {"C2H_MM_CTL_RUN", - C2H_MM_CTL_RUN_MASK}, -}; - - -static struct regfield_info - c2h_mm_status_field_info[] = { - {"C2H_MM_STATUS_RSVD_1", - C2H_MM_STATUS_RSVD_1_MASK}, - {"C2H_MM_STATUS_RUN", - C2H_MM_STATUS_RUN_MASK}, -}; - - -static struct regfield_info - c2h_mm_cmpl_desc_cnt_field_info[] = { - {"C2H_MM_CMPL_DESC_CNT_C2H_CO", - C2H_MM_CMPL_DESC_CNT_C2H_CO_MASK}, -}; - - -static struct regfield_info - c2h_mm_err_code_enable_mask_field_info[] = { - {"C2H_MM_ERR_CODE_ENABLE_RESERVED1", - C2H_MM_ERR_CODE_ENABLE_RESERVED1_MASK}, - {"C2H_MM_ERR_CODE_ENABLE_WR_UC_RAM", - C2H_MM_ERR_CODE_ENABLE_WR_UC_RAM_MASK}, - {"C2H_MM_ERR_CODE_ENABLE_WR_UR", - C2H_MM_ERR_CODE_ENABLE_WR_UR_MASK}, - {"C2H_MM_ERR_CODE_ENABLE_WR_FLR", - C2H_MM_ERR_CODE_ENABLE_WR_FLR_MASK}, - {"C2H_MM_ERR_CODE_ENABLE_RESERVED0", - C2H_MM_ERR_CODE_ENABLE_RESERVED0_MASK}, - {"C2H_MM_ERR_CODE_ENABLE_RD_SLV_ERR", - C2H_MM_ERR_CODE_ENABLE_RD_SLV_ERR_MASK}, - {"C2H_MM_ERR_CODE_ENABLE_WR_SLV_ERR", - C2H_MM_ERR_CODE_ENABLE_WR_SLV_ERR_MASK}, -}; - - -static struct regfield_info - c2h_mm_err_code_field_info[] = { - {"C2H_MM_ERR_CODE_RESERVED1", - C2H_MM_ERR_CODE_RESERVED1_MASK}, - {"C2H_MM_ERR_CODE_CIDX", - C2H_MM_ERR_CODE_CIDX_MASK}, - {"C2H_MM_ERR_CODE_RESERVED0", - C2H_MM_ERR_CODE_RESERVED0_MASK}, - {"C2H_MM_ERR_CODE_SUB_TYPE", - C2H_MM_ERR_CODE_SUB_TYPE_MASK}, - {"C2H_MM_ERR_CODE", - C2H_MM_ERR_CODE_MASK}, -}; - - -static struct regfield_info - c2h_mm_err_info_field_info[] = { - {"C2H_MM_ERR_INFO_VALID", - C2H_MM_ERR_INFO_VALID_MASK}, - {"C2H_MM_ERR_INFO_SEL", - C2H_MM_ERR_INFO_SEL_MASK}, - {"C2H_MM_ERR_INFO_RSVD_1", - C2H_MM_ERR_INFO_RSVD_1_MASK}, - {"C2H_MM_ERR_INFO_QID", - C2H_MM_ERR_INFO_QID_MASK}, -}; - - -static struct regfield_info - c2h_mm_perf_mon_ctl_field_info[] = { - {"C2H_MM_PERF_MON_CTL_RSVD_1", - C2H_MM_PERF_MON_CTL_RSVD_1_MASK}, - {"C2H_MM_PERF_MON_CTL_IMM_START", - C2H_MM_PERF_MON_CTL_IMM_START_MASK}, - {"C2H_MM_PERF_MON_CTL_RUN_START", - C2H_MM_PERF_MON_CTL_RUN_START_MASK}, - {"C2H_MM_PERF_MON_CTL_IMM_CLEAR", - C2H_MM_PERF_MON_CTL_IMM_CLEAR_MASK}, - {"C2H_MM_PERF_MON_CTL_RUN_CLEAR", - C2H_MM_PERF_MON_CTL_RUN_CLEAR_MASK}, -}; - - -static struct regfield_info - c2h_mm_perf_mon_cycle_cnt0_field_info[] = { - {"C2H_MM_PERF_MON_CYCLE_CNT0_CYC_CNT", - C2H_MM_PERF_MON_CYCLE_CNT0_CYC_CNT_MASK}, -}; - - -static struct regfield_info - c2h_mm_perf_mon_cycle_cnt1_field_info[] = { - {"C2H_MM_PERF_MON_CYCLE_CNT1_RSVD_1", - C2H_MM_PERF_MON_CYCLE_CNT1_RSVD_1_MASK}, - {"C2H_MM_PERF_MON_CYCLE_CNT1_CYC_CNT", - C2H_MM_PERF_MON_CYCLE_CNT1_CYC_CNT_MASK}, -}; - - -static struct regfield_info - c2h_mm_perf_mon_data_cnt0_field_info[] = { - {"C2H_MM_PERF_MON_DATA_CNT0_DCNT", - C2H_MM_PERF_MON_DATA_CNT0_DCNT_MASK}, -}; - - -static struct regfield_info - c2h_mm_perf_mon_data_cnt1_field_info[] = { - {"C2H_MM_PERF_MON_DATA_CNT1_RSVD_1", - C2H_MM_PERF_MON_DATA_CNT1_RSVD_1_MASK}, - {"C2H_MM_PERF_MON_DATA_CNT1_DCNT", - C2H_MM_PERF_MON_DATA_CNT1_DCNT_MASK}, -}; - - -static struct regfield_info - c2h_mm_dbg_field_info[] = { - {"C2H_MM_RSVD_1", - C2H_MM_RSVD_1_MASK}, - {"C2H_MM_RRQ_ENTRIES", - C2H_MM_RRQ_ENTRIES_MASK}, - {"C2H_MM_DAT_FIFO_SPC", - C2H_MM_DAT_FIFO_SPC_MASK}, - {"C2H_MM_RD_STALL", - C2H_MM_RD_STALL_MASK}, - {"C2H_MM_RRQ_FIFO_FI", - C2H_MM_RRQ_FIFO_FI_MASK}, - {"C2H_MM_WR_STALL", - C2H_MM_WR_STALL_MASK}, - {"C2H_MM_WRQ_FIFO_FI", - C2H_MM_WRQ_FIFO_FI_MASK}, - {"C2H_MM_WBK_STALL", - C2H_MM_WBK_STALL_MASK}, - {"C2H_MM_DSC_FIFO_EP", - C2H_MM_DSC_FIFO_EP_MASK}, - {"C2H_MM_DSC_FIFO_FL", - C2H_MM_DSC_FIFO_FL_MASK}, -}; - - -static struct regfield_info - h2c_mm_ctl_field_info[] = { - {"H2C_MM_CTL_RESERVED1", - H2C_MM_CTL_RESERVED1_MASK}, - {"H2C_MM_CTL_ERRC_EN", - H2C_MM_CTL_ERRC_EN_MASK}, - {"H2C_MM_CTL_RESERVED0", - H2C_MM_CTL_RESERVED0_MASK}, - {"H2C_MM_CTL_RUN", - H2C_MM_CTL_RUN_MASK}, -}; - - -static struct regfield_info - h2c_mm_status_field_info[] = { - {"H2C_MM_STATUS_RSVD_1", - H2C_MM_STATUS_RSVD_1_MASK}, - {"H2C_MM_STATUS_RUN", - H2C_MM_STATUS_RUN_MASK}, -}; - - -static struct regfield_info - h2c_mm_cmpl_desc_cnt_field_info[] = { - {"H2C_MM_CMPL_DESC_CNT_H2C_CO", - H2C_MM_CMPL_DESC_CNT_H2C_CO_MASK}, -}; - - -static struct regfield_info - h2c_mm_err_code_enable_mask_field_info[] = { - {"H2C_MM_ERR_CODE_ENABLE_RESERVED5", - H2C_MM_ERR_CODE_ENABLE_RESERVED5_MASK}, - {"H2C_MM_ERR_CODE_ENABLE_WR_SLV_ERR", - H2C_MM_ERR_CODE_ENABLE_WR_SLV_ERR_MASK}, - {"H2C_MM_ERR_CODE_ENABLE_WR_DEC_ERR", - H2C_MM_ERR_CODE_ENABLE_WR_DEC_ERR_MASK}, - {"H2C_MM_ERR_CODE_ENABLE_RESERVED4", - H2C_MM_ERR_CODE_ENABLE_RESERVED4_MASK}, - {"H2C_MM_ERR_CODE_ENABLE_RD_RQ_DIS_ERR", - H2C_MM_ERR_CODE_ENABLE_RD_RQ_DIS_ERR_MASK}, - {"H2C_MM_ERR_CODE_ENABLE_RESERVED3", - H2C_MM_ERR_CODE_ENABLE_RESERVED3_MASK}, - {"H2C_MM_ERR_CODE_ENABLE_RD_DAT_POISON_ERR", - H2C_MM_ERR_CODE_ENABLE_RD_DAT_POISON_ERR_MASK}, - {"H2C_MM_ERR_CODE_ENABLE_RESERVED2", - H2C_MM_ERR_CODE_ENABLE_RESERVED2_MASK}, - {"H2C_MM_ERR_CODE_ENABLE_RD_FLR_ERR", - H2C_MM_ERR_CODE_ENABLE_RD_FLR_ERR_MASK}, - {"H2C_MM_ERR_CODE_ENABLE_RESERVED1", - H2C_MM_ERR_CODE_ENABLE_RESERVED1_MASK}, - {"H2C_MM_ERR_CODE_ENABLE_RD_HDR_ADR_ERR", - H2C_MM_ERR_CODE_ENABLE_RD_HDR_ADR_ERR_MASK}, - {"H2C_MM_ERR_CODE_ENABLE_RD_HDR_PARA", - H2C_MM_ERR_CODE_ENABLE_RD_HDR_PARA_MASK}, - {"H2C_MM_ERR_CODE_ENABLE_RD_HDR_BYTE_ERR", - H2C_MM_ERR_CODE_ENABLE_RD_HDR_BYTE_ERR_MASK}, - {"H2C_MM_ERR_CODE_ENABLE_RD_UR_CA", - H2C_MM_ERR_CODE_ENABLE_RD_UR_CA_MASK}, - {"H2C_MM_ERR_CODE_ENABLE_RD_HRD_POISON_ERR", - H2C_MM_ERR_CODE_ENABLE_RD_HRD_POISON_ERR_MASK}, - {"H2C_MM_ERR_CODE_ENABLE_RESERVED0", - H2C_MM_ERR_CODE_ENABLE_RESERVED0_MASK}, -}; - - -static struct regfield_info - h2c_mm_err_code_field_info[] = { - {"H2C_MM_ERR_CODE_RSVD_1", - H2C_MM_ERR_CODE_RSVD_1_MASK}, - {"H2C_MM_ERR_CODE_CIDX", - H2C_MM_ERR_CODE_CIDX_MASK}, - {"H2C_MM_ERR_CODE_RESERVED0", - H2C_MM_ERR_CODE_RESERVED0_MASK}, - {"H2C_MM_ERR_CODE_SUB_TYPE", - H2C_MM_ERR_CODE_SUB_TYPE_MASK}, - {"H2C_MM_ERR_CODE", - H2C_MM_ERR_CODE_MASK}, -}; - - -static struct regfield_info - h2c_mm_err_info_field_info[] = { - {"H2C_MM_ERR_INFO_VALID", - H2C_MM_ERR_INFO_VALID_MASK}, - {"H2C_MM_ERR_INFO_SEL", - H2C_MM_ERR_INFO_SEL_MASK}, - {"H2C_MM_ERR_INFO_RSVD_1", - H2C_MM_ERR_INFO_RSVD_1_MASK}, - {"H2C_MM_ERR_INFO_QID", - H2C_MM_ERR_INFO_QID_MASK}, -}; - - -static struct regfield_info - h2c_mm_perf_mon_ctl_field_info[] = { - {"H2C_MM_PERF_MON_CTL_RSVD_1", - H2C_MM_PERF_MON_CTL_RSVD_1_MASK}, - {"H2C_MM_PERF_MON_CTL_IMM_START", - H2C_MM_PERF_MON_CTL_IMM_START_MASK}, - {"H2C_MM_PERF_MON_CTL_RUN_START", - H2C_MM_PERF_MON_CTL_RUN_START_MASK}, - {"H2C_MM_PERF_MON_CTL_IMM_CLEAR", - H2C_MM_PERF_MON_CTL_IMM_CLEAR_MASK}, - {"H2C_MM_PERF_MON_CTL_RUN_CLEAR", - H2C_MM_PERF_MON_CTL_RUN_CLEAR_MASK}, -}; - - -static struct regfield_info - h2c_mm_perf_mon_cycle_cnt0_field_info[] = { - {"H2C_MM_PERF_MON_CYCLE_CNT0_CYC_CNT", - H2C_MM_PERF_MON_CYCLE_CNT0_CYC_CNT_MASK}, -}; - - -static struct regfield_info - h2c_mm_perf_mon_cycle_cnt1_field_info[] = { - {"H2C_MM_PERF_MON_CYCLE_CNT1_RSVD_1", - H2C_MM_PERF_MON_CYCLE_CNT1_RSVD_1_MASK}, - {"H2C_MM_PERF_MON_CYCLE_CNT1_CYC_CNT", - H2C_MM_PERF_MON_CYCLE_CNT1_CYC_CNT_MASK}, -}; - - -static struct regfield_info - h2c_mm_perf_mon_data_cnt0_field_info[] = { - {"H2C_MM_PERF_MON_DATA_CNT0_DCNT", - H2C_MM_PERF_MON_DATA_CNT0_DCNT_MASK}, -}; - - -static struct regfield_info - h2c_mm_perf_mon_data_cnt1_field_info[] = { - {"H2C_MM_PERF_MON_DATA_CNT1_RSVD_1", - H2C_MM_PERF_MON_DATA_CNT1_RSVD_1_MASK}, - {"H2C_MM_PERF_MON_DATA_CNT1_DCNT", - H2C_MM_PERF_MON_DATA_CNT1_DCNT_MASK}, -}; - - -static struct regfield_info - h2c_mm_dbg_field_info[] = { - {"H2C_MM_RSVD_1", - H2C_MM_RSVD_1_MASK}, - {"H2C_MM_RRQ_ENTRIES", - H2C_MM_RRQ_ENTRIES_MASK}, - {"H2C_MM_DAT_FIFO_SPC", - H2C_MM_DAT_FIFO_SPC_MASK}, - {"H2C_MM_RD_STALL", - H2C_MM_RD_STALL_MASK}, - {"H2C_MM_RRQ_FIFO_FI", - H2C_MM_RRQ_FIFO_FI_MASK}, - {"H2C_MM_WR_STALL", - H2C_MM_WR_STALL_MASK}, - {"H2C_MM_WRQ_FIFO_FI", - H2C_MM_WRQ_FIFO_FI_MASK}, - {"H2C_MM_WBK_STALL", - H2C_MM_WBK_STALL_MASK}, - {"H2C_MM_DSC_FIFO_EP", - H2C_MM_DSC_FIFO_EP_MASK}, - {"H2C_MM_DSC_FIFO_FL", - H2C_MM_DSC_FIFO_FL_MASK}, -}; - - -static struct regfield_info - c2h_crdt_coal_cfg_1_field_info[] = { - {"C2H_CRDT_COAL_CFG_1_RSVD_1", - C2H_CRDT_COAL_CFG_1_RSVD_1_MASK}, - {"C2H_CRDT_COAL_CFG_1_PLD_FIFO_TH", - C2H_CRDT_COAL_CFG_1_PLD_FIFO_TH_MASK}, - {"C2H_CRDT_COAL_CFG_1_TIMER_TH", - C2H_CRDT_COAL_CFG_1_TIMER_TH_MASK}, -}; - - -static struct regfield_info - c2h_crdt_coal_cfg_2_field_info[] = { - {"C2H_CRDT_COAL_CFG_2_RSVD_1", - C2H_CRDT_COAL_CFG_2_RSVD_1_MASK}, - {"C2H_CRDT_COAL_CFG_2_FIFO_TH", - C2H_CRDT_COAL_CFG_2_FIFO_TH_MASK}, - {"C2H_CRDT_COAL_CFG_2_RESERVED1", - C2H_CRDT_COAL_CFG_2_RESERVED1_MASK}, - {"C2H_CRDT_COAL_CFG_2_NT_TH", - C2H_CRDT_COAL_CFG_2_NT_TH_MASK}, -}; - - -static struct regfield_info - c2h_pfch_byp_qid_field_info[] = { - {"C2H_PFCH_BYP_QID_RSVD_1", - C2H_PFCH_BYP_QID_RSVD_1_MASK}, - {"C2H_PFCH_BYP_QID", - C2H_PFCH_BYP_QID_MASK}, -}; - - -static struct regfield_info - c2h_pfch_byp_tag_field_info[] = { - {"C2H_PFCH_BYP_TAG_RSVD_1", - C2H_PFCH_BYP_TAG_RSVD_1_MASK}, - {"C2H_PFCH_BYP_TAG_BYP_QID", - C2H_PFCH_BYP_TAG_BYP_QID_MASK}, - {"C2H_PFCH_BYP_TAG_RSVD_2", - C2H_PFCH_BYP_TAG_RSVD_2_MASK}, - {"C2H_PFCH_BYP_TAG", - C2H_PFCH_BYP_TAG_MASK}, -}; - - -static struct regfield_info - c2h_water_mark_field_info[] = { - {"C2H_WATER_MARK_HIGH_WM", - C2H_WATER_MARK_HIGH_WM_MASK}, - {"C2H_WATER_MARK_LOW_WM", - C2H_WATER_MARK_LOW_WM_MASK}, -}; - - -static struct regfield_info - c2h_notify_empty_field_info[] = { - {"C2H_NOTIFY_EMPTY_RSVD_1", - C2H_NOTIFY_EMPTY_RSVD_1_MASK}, - {"C2H_NOTIFY_EMPTY_NOE", - C2H_NOTIFY_EMPTY_NOE_MASK}, -}; - - -static struct regfield_info - c2h_stat_s_axis_c2h_accepted_1_field_info[] = { - {"C2H_STAT_S_AXIS_C2H_ACCEPTED_1", - C2H_STAT_S_AXIS_C2H_ACCEPTED_1_MASK}, -}; - - -static struct regfield_info - c2h_stat_s_axis_wrb_accepted_1_field_info[] = { - {"C2H_STAT_S_AXIS_WRB_ACCEPTED_1", - C2H_STAT_S_AXIS_WRB_ACCEPTED_1_MASK}, -}; - - -static struct regfield_info - c2h_stat_desc_rsp_pkt_accepted_1_field_info[] = { - {"C2H_STAT_DESC_RSP_PKT_ACCEPTED_1_D", - C2H_STAT_DESC_RSP_PKT_ACCEPTED_1_D_MASK}, -}; - - -static struct regfield_info - c2h_stat_axis_pkg_cmp_1_field_info[] = { - {"C2H_STAT_AXIS_PKG_CMP_1", - C2H_STAT_AXIS_PKG_CMP_1_MASK}, -}; - - -static struct regfield_info - c2h_stat_s_axis_wrb_accepted_2_field_info[] = { - {"C2H_STAT_S_AXIS_WRB_ACCEPTED_2", - C2H_STAT_S_AXIS_WRB_ACCEPTED_2_MASK}, -}; - - -static struct regfield_info - c2h_st_pld_fifo_depth_field_info[] = { - {"C2H_ST_PLD_FIFO_DEPTH", - C2H_ST_PLD_FIFO_DEPTH_MASK}, -}; - -static struct xreg_info eqdma_cpm5_config_regs[] = { -{"CFG_BLK_IDENTIFIER", 0x00, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(cfg_blk_identifier_field_info), - cfg_blk_identifier_field_info -}, -{"CFG_BLK_PCIE_MAX_PLD_SIZE", 0x08, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(cfg_blk_pcie_max_pld_size_field_info), - cfg_blk_pcie_max_pld_size_field_info -}, -{"CFG_BLK_PCIE_MAX_READ_REQ_SIZE", 0x0c, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(cfg_blk_pcie_max_read_req_size_field_info), - cfg_blk_pcie_max_read_req_size_field_info -}, -{"CFG_BLK_SYSTEM_ID", 0x10, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(cfg_blk_system_id_field_info), - cfg_blk_system_id_field_info -}, -{"CFG_BLK_MSIX_ENABLE", 0x014, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(cfg_blk_msix_enable_field_info), - cfg_blk_msix_enable_field_info -}, -{"CFG_PCIE_DATA_WIDTH", 0x18, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(cfg_pcie_data_width_field_info), - cfg_pcie_data_width_field_info -}, -{"CFG_PCIE_CTL", 0x1c, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(cfg_pcie_ctl_field_info), - cfg_pcie_ctl_field_info -}, -{"CFG_BLK_MSI_ENABLE", 0x20, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(cfg_blk_msi_enable_field_info), - cfg_blk_msi_enable_field_info -}, -{"CFG_AXI_USER_MAX_PLD_SIZE", 0x40, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(cfg_axi_user_max_pld_size_field_info), - cfg_axi_user_max_pld_size_field_info -}, -{"CFG_AXI_USER_MAX_READ_REQ_SIZE", 0x44, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(cfg_axi_user_max_read_req_size_field_info), - cfg_axi_user_max_read_req_size_field_info -}, -{"CFG_BLK_MISC_CTL", 0x4c, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(cfg_blk_misc_ctl_field_info), - cfg_blk_misc_ctl_field_info -}, -{"CFG_PL_CRED_CTL", 0x68, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(cfg_pl_cred_ctl_field_info), - cfg_pl_cred_ctl_field_info -}, -{"CFG_BLK_SCRATCH", 0x80, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(cfg_blk_scratch_field_info), - cfg_blk_scratch_field_info -}, -{"CFG_GIC", 0xa0, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(cfg_gic_field_info), - cfg_gic_field_info -}, -{"RAM_SBE_MSK_1_A", 0xe0, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(ram_sbe_msk_1_a_field_info), - ram_sbe_msk_1_a_field_info -}, -{"RAM_SBE_STS_1_A", 0xe4, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(ram_sbe_sts_1_a_field_info), - ram_sbe_sts_1_a_field_info -}, -{"RAM_DBE_MSK_1_A", 0xe8, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(ram_dbe_msk_1_a_field_info), - ram_dbe_msk_1_a_field_info -}, -{"RAM_DBE_STS_1_A", 0xec, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(ram_dbe_sts_1_a_field_info), - ram_dbe_sts_1_a_field_info -}, -{"RAM_SBE_MSK_A", 0xf0, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(ram_sbe_msk_a_field_info), - ram_sbe_msk_a_field_info -}, -{"RAM_SBE_STS_A", 0xf4, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(ram_sbe_sts_a_field_info), - ram_sbe_sts_a_field_info -}, -{"RAM_DBE_MSK_A", 0xf8, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(ram_dbe_msk_a_field_info), - ram_dbe_msk_a_field_info -}, -{"RAM_DBE_STS_A", 0xfc, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(ram_dbe_sts_a_field_info), - ram_dbe_sts_a_field_info -}, -{"GLBL2_IDENTIFIER", 0x100, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(glbl2_identifier_field_info), - glbl2_identifier_field_info -}, -{"GLBL2_CHANNEL_INST", 0x114, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(glbl2_channel_inst_field_info), - glbl2_channel_inst_field_info -}, -{"GLBL2_CHANNEL_MDMA", 0x118, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(glbl2_channel_mdma_field_info), - glbl2_channel_mdma_field_info -}, -{"GLBL2_CHANNEL_STRM", 0x11c, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(glbl2_channel_strm_field_info), - glbl2_channel_strm_field_info -}, -{"GLBL2_CHANNEL_CAP", 0x120, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(glbl2_channel_cap_field_info), - glbl2_channel_cap_field_info -}, -{"GLBL2_CHANNEL_PASID_CAP", 0x128, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(glbl2_channel_pasid_cap_field_info), - glbl2_channel_pasid_cap_field_info -}, -{"GLBL2_SYSTEM_ID", 0x130, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(glbl2_system_id_field_info), - glbl2_system_id_field_info -}, -{"GLBL2_MISC_CAP", 0x134, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(glbl2_misc_cap_field_info), - glbl2_misc_cap_field_info -}, -{"GLBL2_DBG_PCIE_RQ0", 0x1b8, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(glbl2_dbg_pcie_rq0_field_info), - glbl2_dbg_pcie_rq0_field_info -}, -{"GLBL2_DBG_PCIE_RQ1", 0x1bc, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(glbl2_dbg_pcie_rq1_field_info), - glbl2_dbg_pcie_rq1_field_info -}, -{"GLBL2_DBG_AXIMM_WR0", 0x1c0, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(glbl2_dbg_aximm_wr0_field_info), - glbl2_dbg_aximm_wr0_field_info -}, -{"GLBL2_DBG_AXIMM_WR1", 0x1c4, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(glbl2_dbg_aximm_wr1_field_info), - glbl2_dbg_aximm_wr1_field_info -}, -{"GLBL2_DBG_AXIMM_RD0", 0x1c8, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(glbl2_dbg_aximm_rd0_field_info), - glbl2_dbg_aximm_rd0_field_info -}, -{"GLBL2_DBG_AXIMM_RD1", 0x1cc, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(glbl2_dbg_aximm_rd1_field_info), - glbl2_dbg_aximm_rd1_field_info -}, -{"GLBL2_DBG_FAB0", 0x1d0, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(glbl2_dbg_fab0_field_info), - glbl2_dbg_fab0_field_info -}, -{"GLBL2_DBG_FAB1", 0x1d4, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(glbl2_dbg_fab1_field_info), - glbl2_dbg_fab1_field_info -}, -{"GLBL2_DBG_MATCH_SEL", 0x1f4, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(glbl2_dbg_match_sel_field_info), - glbl2_dbg_match_sel_field_info -}, -{"GLBL2_DBG_MATCH_MSK", 0x1f8, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(glbl2_dbg_match_msk_field_info), - glbl2_dbg_match_msk_field_info -}, -{"GLBL2_DBG_MATCH_PAT", 0x1fc, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(glbl2_dbg_match_pat_field_info), - glbl2_dbg_match_pat_field_info -}, -{"GLBL_RNG_SZ_1", 0x204, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(glbl_rng_sz_1_field_info), - glbl_rng_sz_1_field_info -}, -{"GLBL_RNG_SZ_2", 0x208, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(glbl_rng_sz_2_field_info), - glbl_rng_sz_2_field_info -}, -{"GLBL_RNG_SZ_3", 0x20c, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(glbl_rng_sz_3_field_info), - glbl_rng_sz_3_field_info -}, -{"GLBL_RNG_SZ_4", 0x210, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(glbl_rng_sz_4_field_info), - glbl_rng_sz_4_field_info -}, -{"GLBL_RNG_SZ_5", 0x214, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(glbl_rng_sz_5_field_info), - glbl_rng_sz_5_field_info -}, -{"GLBL_RNG_SZ_6", 0x218, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(glbl_rng_sz_6_field_info), - glbl_rng_sz_6_field_info -}, -{"GLBL_RNG_SZ_7", 0x21c, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(glbl_rng_sz_7_field_info), - glbl_rng_sz_7_field_info -}, -{"GLBL_RNG_SZ_8", 0x220, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(glbl_rng_sz_8_field_info), - glbl_rng_sz_8_field_info -}, -{"GLBL_RNG_SZ_9", 0x224, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(glbl_rng_sz_9_field_info), - glbl_rng_sz_9_field_info -}, -{"GLBL_RNG_SZ_A", 0x228, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(glbl_rng_sz_a_field_info), - glbl_rng_sz_a_field_info -}, -{"GLBL_RNG_SZ_B", 0x22c, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(glbl_rng_sz_b_field_info), - glbl_rng_sz_b_field_info -}, -{"GLBL_RNG_SZ_C", 0x230, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(glbl_rng_sz_c_field_info), - glbl_rng_sz_c_field_info -}, -{"GLBL_RNG_SZ_D", 0x234, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(glbl_rng_sz_d_field_info), - glbl_rng_sz_d_field_info -}, -{"GLBL_RNG_SZ_E", 0x238, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(glbl_rng_sz_e_field_info), - glbl_rng_sz_e_field_info -}, -{"GLBL_RNG_SZ_F", 0x23c, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(glbl_rng_sz_f_field_info), - glbl_rng_sz_f_field_info -}, -{"GLBL_RNG_SZ_10", 0x240, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(glbl_rng_sz_10_field_info), - glbl_rng_sz_10_field_info -}, -{"GLBL_ERR_STAT", 0x248, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(glbl_err_stat_field_info), - glbl_err_stat_field_info -}, -{"GLBL_ERR_MASK", 0x24c, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(glbl_err_mask_field_info), - glbl_err_mask_field_info -}, -{"GLBL_DSC_CFG", 0x250, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(glbl_dsc_cfg_field_info), - glbl_dsc_cfg_field_info -}, -{"GLBL_DSC_ERR_STS", 0x254, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(glbl_dsc_err_sts_field_info), - glbl_dsc_err_sts_field_info -}, -{"GLBL_DSC_ERR_MSK", 0x258, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(glbl_dsc_err_msk_field_info), - glbl_dsc_err_msk_field_info -}, -{"GLBL_DSC_ERR_LOG0", 0x25c, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(glbl_dsc_err_log0_field_info), - glbl_dsc_err_log0_field_info -}, -{"GLBL_DSC_ERR_LOG1", 0x260, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(glbl_dsc_err_log1_field_info), - glbl_dsc_err_log1_field_info -}, -{"GLBL_TRQ_ERR_STS", 0x264, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(glbl_trq_err_sts_field_info), - glbl_trq_err_sts_field_info -}, -{"GLBL_TRQ_ERR_MSK", 0x268, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(glbl_trq_err_msk_field_info), - glbl_trq_err_msk_field_info -}, -{"GLBL_TRQ_ERR_LOG", 0x26c, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(glbl_trq_err_log_field_info), - glbl_trq_err_log_field_info -}, -{"GLBL_DSC_DBG_DAT0", 0x270, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(glbl_dsc_dbg_dat0_field_info), - glbl_dsc_dbg_dat0_field_info -}, -{"GLBL_DSC_DBG_DAT1", 0x274, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(glbl_dsc_dbg_dat1_field_info), - glbl_dsc_dbg_dat1_field_info -}, -{"GLBL_DSC_DBG_CTL", 0x278, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(glbl_dsc_dbg_ctl_field_info), - glbl_dsc_dbg_ctl_field_info -}, -{"GLBL_DSC_ERR_LOG2", 0x27c, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(glbl_dsc_err_log2_field_info), - glbl_dsc_err_log2_field_info -}, -{"GLBL_GLBL_INTERRUPT_CFG", 0x2c4, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(glbl_glbl_interrupt_cfg_field_info), - glbl_glbl_interrupt_cfg_field_info -}, -{"GLBL_VCH_HOST_PROFILE", 0x2c8, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(glbl_vch_host_profile_field_info), - glbl_vch_host_profile_field_info -}, -{"GLBL_BRIDGE_HOST_PROFILE", 0x308, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(glbl_bridge_host_profile_field_info), - glbl_bridge_host_profile_field_info -}, -{"AXIMM_IRQ_DEST_ADDR", 0x30c, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(aximm_irq_dest_addr_field_info), - aximm_irq_dest_addr_field_info -}, -{"FAB_ERR_LOG", 0x314, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(fab_err_log_field_info), - fab_err_log_field_info -}, -{"IND_CTXT_DATA", 0x804, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(ind_ctxt_data_field_info), - ind_ctxt_data_field_info -}, -{"IND_CTXT_MASK", 0x824, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(ind_ctxt_mask_field_info), - ind_ctxt_mask_field_info -}, -{"IND_CTXT_CMD", 0x844, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(ind_ctxt_cmd_field_info), - ind_ctxt_cmd_field_info -}, -{"C2H_TIMER_CNT", 0xa00, - 1, 0, 0, 0, - 0, QDMA_COMPLETION_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_timer_cnt_field_info), - c2h_timer_cnt_field_info -}, -{"C2H_CNT_TH", 0xa40, - 1, 0, 0, 0, - 0, QDMA_COMPLETION_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_cnt_th_field_info), - c2h_cnt_th_field_info -}, -{"C2H_STAT_S_AXIS_C2H_ACCEPTED", 0xa88, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(c2h_stat_s_axis_c2h_accepted_field_info), - c2h_stat_s_axis_c2h_accepted_field_info -}, -{"C2H_STAT_S_AXIS_WRB_ACCEPTED", 0xa8c, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(c2h_stat_s_axis_wrb_accepted_field_info), - c2h_stat_s_axis_wrb_accepted_field_info -}, -{"C2H_STAT_DESC_RSP_PKT_ACCEPTED", 0xa90, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(c2h_stat_desc_rsp_pkt_accepted_field_info), - c2h_stat_desc_rsp_pkt_accepted_field_info -}, -{"C2H_STAT_AXIS_PKG_CMP", 0xa94, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(c2h_stat_axis_pkg_cmp_field_info), - c2h_stat_axis_pkg_cmp_field_info -}, -{"C2H_STAT_DESC_RSP_ACCEPTED", 0xa98, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_stat_desc_rsp_accepted_field_info), - c2h_stat_desc_rsp_accepted_field_info -}, -{"C2H_STAT_DESC_RSP_CMP", 0xa9c, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_stat_desc_rsp_cmp_field_info), - c2h_stat_desc_rsp_cmp_field_info -}, -{"C2H_STAT_WRQ_OUT", 0xaa0, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_stat_wrq_out_field_info), - c2h_stat_wrq_out_field_info -}, -{"C2H_STAT_WPL_REN_ACCEPTED", 0xaa4, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_stat_wpl_ren_accepted_field_info), - c2h_stat_wpl_ren_accepted_field_info -}, -{"C2H_STAT_TOTAL_WRQ_LEN", 0xaa8, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_stat_total_wrq_len_field_info), - c2h_stat_total_wrq_len_field_info -}, -{"C2H_STAT_TOTAL_WPL_LEN", 0xaac, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_stat_total_wpl_len_field_info), - c2h_stat_total_wpl_len_field_info -}, -{"C2H_BUF_SZ", 0xab0, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_buf_sz_field_info), - c2h_buf_sz_field_info -}, -{"C2H_ERR_STAT", 0xaf0, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(c2h_err_stat_field_info), - c2h_err_stat_field_info -}, -{"C2H_ERR_MASK", 0xaf4, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(c2h_err_mask_field_info), - c2h_err_mask_field_info -}, -{"C2H_FATAL_ERR_STAT", 0xaf8, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(c2h_fatal_err_stat_field_info), - c2h_fatal_err_stat_field_info -}, -{"C2H_FATAL_ERR_MASK", 0xafc, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(c2h_fatal_err_mask_field_info), - c2h_fatal_err_mask_field_info -}, -{"C2H_FATAL_ERR_ENABLE", 0xb00, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(c2h_fatal_err_enable_field_info), - c2h_fatal_err_enable_field_info -}, -{"GLBL_ERR_INT", 0xb04, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(glbl_err_int_field_info), - glbl_err_int_field_info -}, -{"C2H_PFCH_CFG", 0xb08, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_pfch_cfg_field_info), - c2h_pfch_cfg_field_info -}, -{"C2H_PFCH_CFG_1", 0xa80, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(c2h_pfch_cfg_1_field_info), - c2h_pfch_cfg_1_field_info -}, -{"C2H_PFCH_CFG_2", 0xa84, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(c2h_pfch_cfg_2_field_info), - c2h_pfch_cfg_2_field_info -}, -{"C2H_INT_TIMER_TICK", 0xb0c, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_int_timer_tick_field_info), - c2h_int_timer_tick_field_info -}, -{"C2H_STAT_DESC_RSP_DROP_ACCEPTED", 0xb10, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(c2h_stat_desc_rsp_drop_accepted_field_info), - c2h_stat_desc_rsp_drop_accepted_field_info -}, -{"C2H_STAT_DESC_RSP_ERR_ACCEPTED", 0xb14, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(c2h_stat_desc_rsp_err_accepted_field_info), - c2h_stat_desc_rsp_err_accepted_field_info -}, -{"C2H_STAT_DESC_REQ", 0xb18, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_stat_desc_req_field_info), - c2h_stat_desc_req_field_info -}, -{"C2H_STAT_DBG_DMA_ENG_0", 0xb1c, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_stat_dbg_dma_eng_0_field_info), - c2h_stat_dbg_dma_eng_0_field_info -}, -{"C2H_STAT_DBG_DMA_ENG_1", 0xb20, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_stat_dbg_dma_eng_1_field_info), - c2h_stat_dbg_dma_eng_1_field_info -}, -{"C2H_STAT_DBG_DMA_ENG_2", 0xb24, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_stat_dbg_dma_eng_2_field_info), - c2h_stat_dbg_dma_eng_2_field_info -}, -{"C2H_STAT_DBG_DMA_ENG_3", 0xb28, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_stat_dbg_dma_eng_3_field_info), - c2h_stat_dbg_dma_eng_3_field_info -}, -{"C2H_DBG_PFCH_ERR_CTXT", 0xb2c, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_dbg_pfch_err_ctxt_field_info), - c2h_dbg_pfch_err_ctxt_field_info -}, -{"C2H_FIRST_ERR_QID", 0xb30, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(c2h_first_err_qid_field_info), - c2h_first_err_qid_field_info -}, -{"STAT_NUM_WRB_IN", 0xb34, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(stat_num_wrb_in_field_info), - stat_num_wrb_in_field_info -}, -{"STAT_NUM_WRB_OUT", 0xb38, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(stat_num_wrb_out_field_info), - stat_num_wrb_out_field_info -}, -{"STAT_NUM_WRB_DRP", 0xb3c, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(stat_num_wrb_drp_field_info), - stat_num_wrb_drp_field_info -}, -{"STAT_NUM_STAT_DESC_OUT", 0xb40, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(stat_num_stat_desc_out_field_info), - stat_num_stat_desc_out_field_info -}, -{"STAT_NUM_DSC_CRDT_SENT", 0xb44, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(stat_num_dsc_crdt_sent_field_info), - stat_num_dsc_crdt_sent_field_info -}, -{"STAT_NUM_FCH_DSC_RCVD", 0xb48, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(stat_num_fch_dsc_rcvd_field_info), - stat_num_fch_dsc_rcvd_field_info -}, -{"STAT_NUM_BYP_DSC_RCVD", 0xb4c, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(stat_num_byp_dsc_rcvd_field_info), - stat_num_byp_dsc_rcvd_field_info -}, -{"C2H_WRB_COAL_CFG", 0xb50, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_wrb_coal_cfg_field_info), - c2h_wrb_coal_cfg_field_info -}, -{"C2H_INTR_H2C_REQ", 0xb54, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(c2h_intr_h2c_req_field_info), - c2h_intr_h2c_req_field_info -}, -{"C2H_INTR_C2H_MM_REQ", 0xb58, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(c2h_intr_c2h_mm_req_field_info), - c2h_intr_c2h_mm_req_field_info -}, -{"C2H_INTR_ERR_INT_REQ", 0xb5c, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(c2h_intr_err_int_req_field_info), - c2h_intr_err_int_req_field_info -}, -{"C2H_INTR_C2H_ST_REQ", 0xb60, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(c2h_intr_c2h_st_req_field_info), - c2h_intr_c2h_st_req_field_info -}, -{"C2H_INTR_H2C_ERR_C2H_MM_MSIX_ACK", 0xb64, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_intr_h2c_err_c2h_mm_msix_ack_field_info), - c2h_intr_h2c_err_c2h_mm_msix_ack_field_info -}, -{"C2H_INTR_H2C_ERR_C2H_MM_MSIX_FAIL", 0xb68, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_intr_h2c_err_c2h_mm_msix_fail_field_info), - c2h_intr_h2c_err_c2h_mm_msix_fail_field_info -}, -{"C2H_INTR_H2C_ERR_C2H_MM_MSIX_NO_MSIX", 0xb6c, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_intr_h2c_err_c2h_mm_msix_no_msix_field_info), - c2h_intr_h2c_err_c2h_mm_msix_no_msix_field_info -}, -{"C2H_INTR_H2C_ERR_C2H_MM_CTXT_INVAL", 0xb70, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_intr_h2c_err_c2h_mm_ctxt_inval_field_info), - c2h_intr_h2c_err_c2h_mm_ctxt_inval_field_info -}, -{"C2H_INTR_C2H_ST_MSIX_ACK", 0xb74, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(c2h_intr_c2h_st_msix_ack_field_info), - c2h_intr_c2h_st_msix_ack_field_info -}, -{"C2H_INTR_C2H_ST_MSIX_FAIL", 0xb78, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(c2h_intr_c2h_st_msix_fail_field_info), - c2h_intr_c2h_st_msix_fail_field_info -}, -{"C2H_INTR_C2H_ST_NO_MSIX", 0xb7c, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_intr_c2h_st_no_msix_field_info), - c2h_intr_c2h_st_no_msix_field_info -}, -{"C2H_INTR_C2H_ST_CTXT_INVAL", 0xb80, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_intr_c2h_st_ctxt_inval_field_info), - c2h_intr_c2h_st_ctxt_inval_field_info -}, -{"C2H_STAT_WR_CMP", 0xb84, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_stat_wr_cmp_field_info), - c2h_stat_wr_cmp_field_info -}, -{"C2H_STAT_DBG_DMA_ENG_4", 0xb88, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_stat_dbg_dma_eng_4_field_info), - c2h_stat_dbg_dma_eng_4_field_info -}, -{"C2H_STAT_DBG_DMA_ENG_5", 0xb8c, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_stat_dbg_dma_eng_5_field_info), - c2h_stat_dbg_dma_eng_5_field_info -}, -{"C2H_DBG_PFCH_QID", 0xb90, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_dbg_pfch_qid_field_info), - c2h_dbg_pfch_qid_field_info -}, -{"C2H_DBG_PFCH", 0xb94, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_dbg_pfch_field_info), - c2h_dbg_pfch_field_info -}, -{"C2H_INT_DBG", 0xb98, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_int_dbg_field_info), - c2h_int_dbg_field_info -}, -{"C2H_STAT_IMM_ACCEPTED", 0xb9c, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_stat_imm_accepted_field_info), - c2h_stat_imm_accepted_field_info -}, -{"C2H_STAT_MARKER_ACCEPTED", 0xba0, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_stat_marker_accepted_field_info), - c2h_stat_marker_accepted_field_info -}, -{"C2H_STAT_DISABLE_CMP_ACCEPTED", 0xba4, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_stat_disable_cmp_accepted_field_info), - c2h_stat_disable_cmp_accepted_field_info -}, -{"C2H_PLD_FIFO_CRDT_CNT", 0xba8, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_pld_fifo_crdt_cnt_field_info), - c2h_pld_fifo_crdt_cnt_field_info -}, -{"C2H_INTR_DYN_REQ", 0xbac, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_intr_dyn_req_field_info), - c2h_intr_dyn_req_field_info -}, -{"C2H_INTR_DYN_MISC", 0xbb0, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_intr_dyn_misc_field_info), - c2h_intr_dyn_misc_field_info -}, -{"C2H_DROP_LEN_MISMATCH", 0xbb4, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_drop_len_mismatch_field_info), - c2h_drop_len_mismatch_field_info -}, -{"C2H_DROP_DESC_RSP_LEN", 0xbb8, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_drop_desc_rsp_len_field_info), - c2h_drop_desc_rsp_len_field_info -}, -{"C2H_DROP_QID_FIFO_LEN", 0xbbc, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_drop_qid_fifo_len_field_info), - c2h_drop_qid_fifo_len_field_info -}, -{"C2H_DROP_PLD_CNT", 0xbc0, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_drop_pld_cnt_field_info), - c2h_drop_pld_cnt_field_info -}, -{"C2H_CMPT_FORMAT_0", 0xbc4, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_cmpt_format_0_field_info), - c2h_cmpt_format_0_field_info -}, -{"C2H_CMPT_FORMAT_1", 0xbc8, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_cmpt_format_1_field_info), - c2h_cmpt_format_1_field_info -}, -{"C2H_CMPT_FORMAT_2", 0xbcc, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_cmpt_format_2_field_info), - c2h_cmpt_format_2_field_info -}, -{"C2H_CMPT_FORMAT_3", 0xbd0, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_cmpt_format_3_field_info), - c2h_cmpt_format_3_field_info -}, -{"C2H_CMPT_FORMAT_4", 0xbd4, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_cmpt_format_4_field_info), - c2h_cmpt_format_4_field_info -}, -{"C2H_CMPT_FORMAT_5", 0xbd8, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_cmpt_format_5_field_info), - c2h_cmpt_format_5_field_info -}, -{"C2H_CMPT_FORMAT_6", 0xbdc, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_cmpt_format_6_field_info), - c2h_cmpt_format_6_field_info -}, -{"C2H_PFCH_CACHE_DEPTH", 0xbe0, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_pfch_cache_depth_field_info), - c2h_pfch_cache_depth_field_info -}, -{"C2H_WRB_COAL_BUF_DEPTH", 0xbe4, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_wrb_coal_buf_depth_field_info), - c2h_wrb_coal_buf_depth_field_info -}, -{"C2H_PFCH_CRDT", 0xbe8, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_pfch_crdt_field_info), - c2h_pfch_crdt_field_info -}, -{"C2H_STAT_HAS_CMPT_ACCEPTED", 0xbec, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_stat_has_cmpt_accepted_field_info), - c2h_stat_has_cmpt_accepted_field_info -}, -{"C2H_STAT_HAS_PLD_ACCEPTED", 0xbf0, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_stat_has_pld_accepted_field_info), - c2h_stat_has_pld_accepted_field_info -}, -{"C2H_PLD_PKT_ID", 0xbf4, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_pld_pkt_id_field_info), - c2h_pld_pkt_id_field_info -}, -{"C2H_PLD_PKT_ID_1", 0xbf8, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_pld_pkt_id_1_field_info), - c2h_pld_pkt_id_1_field_info -}, -{"C2H_DROP_PLD_CNT_1", 0xbfc, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_drop_pld_cnt_1_field_info), - c2h_drop_pld_cnt_1_field_info -}, -{"H2C_ERR_STAT", 0xe00, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(h2c_err_stat_field_info), - h2c_err_stat_field_info -}, -{"H2C_ERR_MASK", 0xe04, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(h2c_err_mask_field_info), - h2c_err_mask_field_info -}, -{"H2C_FIRST_ERR_QID", 0xe08, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(h2c_first_err_qid_field_info), - h2c_first_err_qid_field_info -}, -{"H2C_DBG_REG0", 0xe0c, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(h2c_dbg_reg0_field_info), - h2c_dbg_reg0_field_info -}, -{"H2C_DBG_REG1", 0xe10, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(h2c_dbg_reg1_field_info), - h2c_dbg_reg1_field_info -}, -{"H2C_DBG_REG2", 0xe14, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(h2c_dbg_reg2_field_info), - h2c_dbg_reg2_field_info -}, -{"H2C_DBG_REG3", 0xe18, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(h2c_dbg_reg3_field_info), - h2c_dbg_reg3_field_info -}, -{"H2C_DBG_REG4", 0xe1c, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(h2c_dbg_reg4_field_info), - h2c_dbg_reg4_field_info -}, -{"H2C_FATAL_ERR_EN", 0xe20, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(h2c_fatal_err_en_field_info), - h2c_fatal_err_en_field_info -}, -{"H2C_REQ_THROT_PCIE", 0xe24, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(h2c_req_throt_pcie_field_info), - h2c_req_throt_pcie_field_info -}, -{"H2C_ALN_DBG_REG0", 0xe28, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(h2c_aln_dbg_reg0_field_info), - h2c_aln_dbg_reg0_field_info -}, -{"H2C_REQ_THROT_AXIMM", 0xe2c, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(h2c_req_throt_aximm_field_info), - h2c_req_throt_aximm_field_info -}, -{"C2H_MM_CTL", 0x1004, - 1, 0, 0, 0, - 0, QDMA_MM_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_mm_ctl_field_info), - c2h_mm_ctl_field_info -}, -{"C2H_MM_STATUS", 0x1040, - 1, 0, 0, 0, - 0, QDMA_MM_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_mm_status_field_info), - c2h_mm_status_field_info -}, -{"C2H_MM_CMPL_DESC_CNT", 0x1048, - 1, 0, 0, 0, - 0, QDMA_MM_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_mm_cmpl_desc_cnt_field_info), - c2h_mm_cmpl_desc_cnt_field_info -}, -{"C2H_MM_ERR_CODE_ENABLE_MASK", 0x1054, - 1, 0, 0, 0, - 0, QDMA_MM_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_mm_err_code_enable_mask_field_info), - c2h_mm_err_code_enable_mask_field_info -}, -{"C2H_MM_ERR_CODE", 0x1058, - 1, 0, 0, 0, - 0, QDMA_MM_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_mm_err_code_field_info), - c2h_mm_err_code_field_info -}, -{"C2H_MM_ERR_INFO", 0x105c, - 1, 0, 0, 0, - 0, QDMA_MM_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_mm_err_info_field_info), - c2h_mm_err_info_field_info -}, -{"C2H_MM_PERF_MON_CTL", 0x10c0, - 1, 0, 0, 0, - 0, QDMA_MM_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_mm_perf_mon_ctl_field_info), - c2h_mm_perf_mon_ctl_field_info -}, -{"C2H_MM_PERF_MON_CYCLE_CNT0", 0x10c4, - 1, 0, 0, 0, - 0, QDMA_MM_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_mm_perf_mon_cycle_cnt0_field_info), - c2h_mm_perf_mon_cycle_cnt0_field_info -}, -{"C2H_MM_PERF_MON_CYCLE_CNT1", 0x10c8, - 1, 0, 0, 0, - 0, QDMA_MM_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_mm_perf_mon_cycle_cnt1_field_info), - c2h_mm_perf_mon_cycle_cnt1_field_info -}, -{"C2H_MM_PERF_MON_DATA_CNT0", 0x10cc, - 1, 0, 0, 0, - 0, QDMA_MM_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_mm_perf_mon_data_cnt0_field_info), - c2h_mm_perf_mon_data_cnt0_field_info -}, -{"C2H_MM_PERF_MON_DATA_CNT1", 0x10d0, - 1, 0, 0, 0, - 0, QDMA_MM_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_mm_perf_mon_data_cnt1_field_info), - c2h_mm_perf_mon_data_cnt1_field_info -}, -{"C2H_MM_DBG", 0x10e8, - 1, 0, 0, 0, - 0, QDMA_MM_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_mm_dbg_field_info), - c2h_mm_dbg_field_info -}, -{"H2C_MM_CTL", 0x1204, - 1, 0, 0, 0, - 0, QDMA_MM_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(h2c_mm_ctl_field_info), - h2c_mm_ctl_field_info -}, -{"H2C_MM_STATUS", 0x1240, - 1, 0, 0, 0, - 0, QDMA_MM_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(h2c_mm_status_field_info), - h2c_mm_status_field_info -}, -{"H2C_MM_CMPL_DESC_CNT", 0x1248, - 1, 0, 0, 0, - 0, QDMA_MM_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(h2c_mm_cmpl_desc_cnt_field_info), - h2c_mm_cmpl_desc_cnt_field_info -}, -{"H2C_MM_ERR_CODE_ENABLE_MASK", 0x1254, - 1, 0, 0, 0, - 0, QDMA_MM_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(h2c_mm_err_code_enable_mask_field_info), - h2c_mm_err_code_enable_mask_field_info -}, -{"H2C_MM_ERR_CODE", 0x1258, - 1, 0, 0, 0, - 0, QDMA_MM_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(h2c_mm_err_code_field_info), - h2c_mm_err_code_field_info -}, -{"H2C_MM_ERR_INFO", 0x125c, - 1, 0, 0, 0, - 0, QDMA_MM_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(h2c_mm_err_info_field_info), - h2c_mm_err_info_field_info -}, -{"H2C_MM_PERF_MON_CTL", 0x12c0, - 1, 0, 0, 0, - 0, QDMA_MM_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(h2c_mm_perf_mon_ctl_field_info), - h2c_mm_perf_mon_ctl_field_info -}, -{"H2C_MM_PERF_MON_CYCLE_CNT0", 0x12c4, - 1, 0, 0, 0, - 0, QDMA_MM_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(h2c_mm_perf_mon_cycle_cnt0_field_info), - h2c_mm_perf_mon_cycle_cnt0_field_info -}, -{"H2C_MM_PERF_MON_CYCLE_CNT1", 0x12c8, - 1, 0, 0, 0, - 0, QDMA_MM_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(h2c_mm_perf_mon_cycle_cnt1_field_info), - h2c_mm_perf_mon_cycle_cnt1_field_info -}, -{"H2C_MM_PERF_MON_DATA_CNT0", 0x12cc, - 1, 0, 0, 0, - 0, QDMA_MM_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(h2c_mm_perf_mon_data_cnt0_field_info), - h2c_mm_perf_mon_data_cnt0_field_info -}, -{"H2C_MM_PERF_MON_DATA_CNT1", 0x12d0, - 1, 0, 0, 0, - 0, QDMA_MM_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(h2c_mm_perf_mon_data_cnt1_field_info), - h2c_mm_perf_mon_data_cnt1_field_info -}, -{"H2C_MM_DBG", 0x12e8, - 1, 0, 0, 0, - 0, QDMA_MM_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(h2c_mm_dbg_field_info), - h2c_mm_dbg_field_info -}, -{"C2H_CRDT_COAL_CFG_1", 0x1400, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_crdt_coal_cfg_1_field_info), - c2h_crdt_coal_cfg_1_field_info -}, -{"C2H_CRDT_COAL_CFG_2", 0x1404, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_crdt_coal_cfg_2_field_info), - c2h_crdt_coal_cfg_2_field_info -}, -{"C2H_PFCH_BYP_QID", 0x1408, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_pfch_byp_qid_field_info), - c2h_pfch_byp_qid_field_info -}, -{"C2H_PFCH_BYP_TAG", 0x140c, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_pfch_byp_tag_field_info), - c2h_pfch_byp_tag_field_info -}, -{"C2H_WATER_MARK", 0x1500, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_water_mark_field_info), - c2h_water_mark_field_info -}, -{"C2H_NOTIFY_EMPTY", 0x1800, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_notify_empty_field_info), - c2h_notify_empty_field_info -}, -{"C2H_STAT_S_AXIS_C2H_ACCEPTED_1", 0x1804, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_stat_s_axis_c2h_accepted_1_field_info), - c2h_stat_s_axis_c2h_accepted_1_field_info -}, -{"C2H_STAT_S_AXIS_WRB_ACCEPTED_1", 0x1808, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_stat_s_axis_wrb_accepted_1_field_info), - c2h_stat_s_axis_wrb_accepted_1_field_info -}, -{"C2H_STAT_DESC_RSP_PKT_ACCEPTED_1", 0x180c, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_stat_desc_rsp_pkt_accepted_1_field_info), - c2h_stat_desc_rsp_pkt_accepted_1_field_info -}, -{"C2H_STAT_AXIS_PKG_CMP_1", 0x1810, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_stat_axis_pkg_cmp_1_field_info), - c2h_stat_axis_pkg_cmp_1_field_info -}, -{"C2H_STAT_S_AXIS_WRB_ACCEPTED_2", 0x1814, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_stat_s_axis_wrb_accepted_2_field_info), - c2h_stat_s_axis_wrb_accepted_2_field_info -}, -{"C2H_ST_PLD_FIFO_DEPTH", 0x1818, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_st_pld_fifo_depth_field_info), - c2h_st_pld_fifo_depth_field_info -}, - -}; - -uint32_t eqdma_cpm5_config_num_regs_get(void) -{ - return (sizeof(eqdma_cpm5_config_regs)/ - sizeof(eqdma_cpm5_config_regs[0])); -} - -struct xreg_info *eqdma_cpm5_config_regs_get(void) -{ - return eqdma_cpm5_config_regs; -} - diff --git a/QDMA/linux-kernel/driver/libqdma/qdma_access/eqdma_soft_access/eqdma_soft_access.c b/QDMA/linux-kernel/driver/libqdma/qdma_access/eqdma_soft_access/eqdma_soft_access.c deleted file mode 100755 index 0a65fbacb..000000000 --- a/QDMA/linux-kernel/driver/libqdma/qdma_access/eqdma_soft_access/eqdma_soft_access.c +++ /dev/null @@ -1,6817 +0,0 @@ -/* - * Copyright (c) 2019-2022, Xilinx, Inc. All rights reserved. - * Copyright (c) 2022, Advanced Micro Devices, Inc. All rights reserved. - * - * This source code is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * The full GNU General Public License is included in this distribution in - * the file called "COPYING". - */ - -#include "eqdma_soft_access.h" -#include "eqdma_soft_reg.h" -#include "qdma_reg_dump.h" - -#ifdef ENABLE_WPP_TRACING -#include "eqdma_soft_access.tmh" -#endif - -/** EQDMA Context array size */ -#define EQDMA_FMAP_NUM_WORDS 2 -#define EQDMA_SW_CONTEXT_NUM_WORDS 8 -#define EQDMA_HW_CONTEXT_NUM_WORDS 2 -#define EQDMA_PFETCH_CONTEXT_NUM_WORDS 2 -#define EQDMA_CR_CONTEXT_NUM_WORDS 1 -#define EQDMA_CMPT_CONTEXT_NUM_WORDS 6 -#define EQDMA_IND_INTR_CONTEXT_NUM_WORDS 4 - -#define EQDMA_VF_USER_BAR_ID 2 - -#define EQDMA_REG_GROUP_1_START_ADDR 0x000 -#define EQDMA_REG_GROUP_2_START_ADDR 0x804 -#define EQDMA_REG_GROUP_3_START_ADDR 0xB00 -#define EQDMA_REG_GROUP_4_START_ADDR 0x5014 - -#define EQDMA_TOTAL_LEAF_ERROR_AGGREGATORS 11 -#define EQDMA_GLBL_TRQ_ERR_ALL_MASK 0XB3 -#define EQDMA_GLBL_DSC_ERR_ALL_MASK 0X1F9037E -#define EQDMA_C2H_ERR_ALL_MASK 0X3F6DF -#define EQDMA_C2H_FATAL_ERR_ALL_MASK 0X1FDF1B -#define EQDMA_H2C_ERR_ALL_MASK 0X3F -#define EQDMA_SBE_ERR_ALL_MASK 0XFFFFFFFF -#define EQDMA_DBE_ERR_ALL_MASK 0XFFFFFFFF -#define EQDMA_MM_C2H_ERR_ALL_MASK 0X70000003 -#define EQDMA_MM_H2C0_ERR_ALL_MASK 0X3041013E - - - - -/* H2C Throttle settings for QDMA 4.0 */ -#define EQDMA_H2C_THROT_DATA_THRESH 0x5000 -#define EQDMA_THROT_EN_DATA 1 -#define EQDMA_THROT_EN_REQ 0 -#define EQDMA_H2C_THROT_REQ_THRESH 0xC0 - -/* H2C Throttle settings for QDMA 5.0 */ -#define EQDMA5_H2C_THROT_DATA_THRESH 0x5000 -#define EQDMA5_THROT_EN_DATA 1 -#define EQDMA5_THROT_EN_REQ 1 -#define EQDMA5_H2C_THROT_REQ_THRESH 0xC0 - -/* CSR Default values for QDMA 5.0 */ -#define EQDMA5_DEFAULT_C2H_UODSC_LIMIT 5 -#define EQDMA5_DEFAULT_H2C_UODSC_LIMIT 8 -#define EQDMA5_DEFAULT_MAX_DSC_FETCH 5 -#define EQDMA5_DEFAULT_WRB_INT QDMA_WRB_INTERVAL_128 - -/* C2H prefetch Throttle configuration. */ -#define EQDMA5_DEFAULT_C2H_EVT_QCNT_TH 0x38 -#define EQDMA5_DEFAULT_C2H_PFCH_QCNT 0x3c - -/** Auxillary Bitmasks for fields spanning multiple words */ -#define EQDMA_SW_CTXT_PASID_GET_H_MASK GENMASK(21, 12) -#define EQDMA_SW_CTXT_PASID_GET_L_MASK GENMASK(11, 0) -#define EQDMA_SW_CTXT_VIRTIO_DSC_BASE_GET_H_MASK GENMASK_ULL(63, 53) -#define EQDMA_SW_CTXT_VIRTIO_DSC_BASE_GET_M_MASK GENMASK_ULL(52, 21) -#define EQDMA_SW_CTXT_VIRTIO_DSC_BASE_GET_L_MASK GENMASK_ULL(20, 0) -#define EQDMA_CMPL_CTXT_PASID_GET_H_MASK GENMASK(21, 9) -#define EQDMA_CMPL_CTXT_PASID_GET_L_MASK GENMASK(8, 0) -#define EQDMA_INTR_CTXT_PASID_GET_H_MASK GENMASK(21, 9) -#define EQDMA_INTR_CTXT_PASID_GET_L_MASK GENMASK(8, 0) - - -#define EQDMA_OFFSET_GLBL2_PF_BARLITE_EXT 0x10C - -#define QDMA_OFFSET_GLBL2_PF_BARLITE_INT 0x104 -#define QDMA_GLBL2_PF3_BAR_MAP_MASK GENMASK(23, 18) -#define QDMA_GLBL2_PF2_BAR_MAP_MASK GENMASK(17, 12) -#define QDMA_GLBL2_PF1_BAR_MAP_MASK GENMASK(11, 6) -#define QDMA_GLBL2_PF0_BAR_MAP_MASK GENMASK(5, 0) - -#define EQDMA_GLBL2_DBG_MODE_EN_MASK BIT(4) -#define EQDMA_GLBL2_DESC_ENG_MODE_MASK GENMASK(3, 2) -#define EQDMA_GLBL2_FLR_PRESENT_MASK BIT(1) -#define EQDMA_GLBL2_MAILBOX_EN_MASK BIT(0) - -/** EQDMA_IND_REG_SEL_FMAP */ -#define EQDMA_FMAP_CTXT_W1_QID_MAX_MASK GENMASK(11, 0) -#define EQDMA_FMAP_CTXT_W0_QID_MASK GENMASK(10, 0) - -#define EQDMA_GLBL2_IP_VERSION_MASK GENMASK(23, 20) -#define EQDMA_GLBL2_VF_IP_VERSION_MASK GENMASK(7, 4) - -static void eqdma_hw_st_h2c_err_process(void *dev_hndl); -static void eqdma_hw_st_c2h_err_process(void *dev_hndl); -static void eqdma_hw_desc_err_process(void *dev_hndl); -static void eqdma_hw_trq_err_process(void *dev_hndl); -static void eqdma_hw_ram_sbe_err_process(void *dev_hndl); -static void eqdma_hw_ram_dbe_err_process(void *dev_hndl); -static void eqdma_mm_h2c0_err_process(void *dev_hndl); -static void eqdma_mm_c2h0_err_process(void *dev_hndl); - -static struct eqdma_hw_err_info eqdma_err_info[EQDMA_ERRS_ALL] = { - /* Descriptor errors */ - { - EQDMA_DSC_ERR_POISON, - "Poison error", - EQDMA_GLBL_DSC_ERR_MSK_ADDR, - EQDMA_GLBL_DSC_ERR_STS_ADDR, - GLBL_DSC_ERR_STS_POISON_MASK, - GLBL_ERR_STAT_ERR_DSC_MASK, - &eqdma_hw_desc_err_process - }, - { - EQDMA_DSC_ERR_UR_CA, - "Unsupported request or completer aborted error", - EQDMA_GLBL_DSC_ERR_MSK_ADDR, - EQDMA_GLBL_DSC_ERR_STS_ADDR, - GLBL_DSC_ERR_STS_UR_CA_MASK, - GLBL_ERR_STAT_ERR_DSC_MASK, - &eqdma_hw_desc_err_process - }, - { - EQDMA_DSC_ERR_BCNT, - "Unexpected Byte count in completion error", - EQDMA_GLBL_DSC_ERR_MSK_ADDR, - EQDMA_GLBL_DSC_ERR_STS_ADDR, - GLBL_DSC_ERR_STS_BCNT_MASK, - GLBL_ERR_STAT_ERR_DSC_MASK, - &eqdma_hw_desc_err_process - }, - { - EQDMA_DSC_ERR_PARAM, - "Parameter mismatch error", - EQDMA_GLBL_DSC_ERR_MSK_ADDR, - EQDMA_GLBL_DSC_ERR_STS_ADDR, - GLBL_DSC_ERR_STS_PARAM_MASK, - GLBL_ERR_STAT_ERR_DSC_MASK, - &eqdma_hw_desc_err_process - }, - { - EQDMA_DSC_ERR_ADDR, - "Address mismatch error", - EQDMA_GLBL_DSC_ERR_MSK_ADDR, - EQDMA_GLBL_DSC_ERR_STS_ADDR, - GLBL_DSC_ERR_STS_ADDR_MASK, - GLBL_ERR_STAT_ERR_DSC_MASK, - &eqdma_hw_desc_err_process - }, - { - EQDMA_DSC_ERR_TAG, - "Unexpected tag error", - EQDMA_GLBL_DSC_ERR_MSK_ADDR, - EQDMA_GLBL_DSC_ERR_STS_ADDR, - GLBL_DSC_ERR_STS_TAG_MASK, - GLBL_ERR_STAT_ERR_DSC_MASK, - &eqdma_hw_desc_err_process - }, - { - EQDMA_DSC_ERR_FLR, - "FLR error", - EQDMA_GLBL_DSC_ERR_MSK_ADDR, - EQDMA_GLBL_DSC_ERR_STS_ADDR, - GLBL_DSC_ERR_STS_FLR_MASK, - GLBL_ERR_STAT_ERR_DSC_MASK, - &eqdma_hw_desc_err_process - }, - { - EQDMA_DSC_ERR_TIMEOUT, - "Timed out error", - EQDMA_GLBL_DSC_ERR_MSK_ADDR, - EQDMA_GLBL_DSC_ERR_STS_ADDR, - GLBL_DSC_ERR_STS_TIMEOUT_MASK, - GLBL_ERR_STAT_ERR_DSC_MASK, - &eqdma_hw_desc_err_process - }, - { - EQDMA_DSC_ERR_DAT_POISON, - "Poison data error", - EQDMA_GLBL_DSC_ERR_MSK_ADDR, - EQDMA_GLBL_DSC_ERR_STS_ADDR, - GLBL_DSC_ERR_STS_DAT_POISON_MASK, - GLBL_ERR_STAT_ERR_DSC_MASK, - &eqdma_hw_desc_err_process - }, - { - EQDMA_DSC_ERR_FLR_CANCEL, - "Descriptor fetch cancelled due to FLR error", - EQDMA_GLBL_DSC_ERR_MSK_ADDR, - EQDMA_GLBL_DSC_ERR_STS_ADDR, - GLBL_DSC_ERR_STS_FLR_CANCEL_MASK, - GLBL_ERR_STAT_ERR_DSC_MASK, - &eqdma_hw_desc_err_process - }, - { - EQDMA_DSC_ERR_DMA, - "DMA engine error", - EQDMA_GLBL_DSC_ERR_MSK_ADDR, - EQDMA_GLBL_DSC_ERR_STS_ADDR, - GLBL_DSC_ERR_STS_DMA_MASK, - GLBL_ERR_STAT_ERR_DSC_MASK, - &eqdma_hw_desc_err_process - }, - { - EQDMA_DSC_ERR_DSC, - "Invalid PIDX update error", - EQDMA_GLBL_DSC_ERR_MSK_ADDR, - EQDMA_GLBL_DSC_ERR_STS_ADDR, - GLBL_DSC_ERR_STS_DSC_MASK, - GLBL_ERR_STAT_ERR_DSC_MASK, - &eqdma_hw_desc_err_process - }, - { - EQDMA_DSC_ERR_RQ_CANCEL, - "Descriptor fetch cancelled due to disable register status error", - EQDMA_GLBL_DSC_ERR_MSK_ADDR, - EQDMA_GLBL_DSC_ERR_STS_ADDR, - GLBL_DSC_ERR_STS_RQ_CANCEL_MASK, - GLBL_ERR_STAT_ERR_DSC_MASK, - &eqdma_hw_desc_err_process - }, - { - EQDMA_DSC_ERR_DBE, - "UNC_ERR_RAM_DBE error", - EQDMA_GLBL_DSC_ERR_MSK_ADDR, - EQDMA_GLBL_DSC_ERR_STS_ADDR, - GLBL_DSC_ERR_STS_DBE_MASK, - GLBL_ERR_STAT_ERR_DSC_MASK, - &eqdma_hw_desc_err_process - }, - { - EQDMA_DSC_ERR_SBE, - "UNC_ERR_RAM_SBE error", - EQDMA_GLBL_DSC_ERR_MSK_ADDR, - EQDMA_GLBL_DSC_ERR_STS_ADDR, - GLBL_DSC_ERR_STS_SBE_MASK, - GLBL_ERR_STAT_ERR_DSC_MASK, - &eqdma_hw_desc_err_process - }, - { - EQDMA_DSC_ERR_PORT_ID, - "Port ID Error", - EQDMA_GLBL_DSC_ERR_MSK_ADDR, - EQDMA_GLBL_DSC_ERR_STS_ADDR, - GLBL_DSC_ERR_STS_PORT_ID_MASK, - GLBL_ERR_STAT_ERR_DSC_MASK, - &eqdma_hw_desc_err_process - }, - { - EQDMA_DSC_ERR_ALL, - "All Descriptor errors", - EQDMA_GLBL_DSC_ERR_MSK_ADDR, - EQDMA_GLBL_DSC_ERR_STS_ADDR, - EQDMA_GLBL_DSC_ERR_ALL_MASK, - GLBL_ERR_STAT_ERR_DSC_MASK, - &eqdma_hw_desc_err_process - }, - - /* TRQ errors */ - { - EQDMA_TRQ_ERR_CSR_UNMAPPED, - "Access targeted unmapped register space via CSR pathway error", - EQDMA_GLBL_TRQ_ERR_MSK_ADDR, - EQDMA_GLBL_TRQ_ERR_STS_ADDR, - GLBL_TRQ_ERR_STS_CSR_UNMAPPED_MASK, - GLBL_ERR_STAT_ERR_TRQ_MASK, - &eqdma_hw_trq_err_process - }, - { - EQDMA_TRQ_ERR_VF_ACCESS, - "VF attempted to access Global register space or Function map", - EQDMA_GLBL_TRQ_ERR_MSK_ADDR, - EQDMA_GLBL_TRQ_ERR_STS_ADDR, - GLBL_TRQ_ERR_STS_VF_ACCESS_ERR_MASK, - GLBL_ERR_STAT_ERR_TRQ_MASK, - &eqdma_hw_trq_err_process - }, - { - EQDMA_TRQ_ERR_TCP_CSR_TIMEOUT, - "Timeout on request to dma internal csr register", - EQDMA_GLBL_TRQ_ERR_MSK_ADDR, - EQDMA_GLBL_TRQ_ERR_STS_ADDR, - GLBL_TRQ_ERR_STS_TCP_CSR_TIMEOUT_MASK, - GLBL_ERR_STAT_ERR_TRQ_MASK, - &eqdma_hw_trq_err_process - }, - { - EQDMA_TRQ_ERR_QSPC_UNMAPPED, - "Access targeted unmapped register via queue space pathway", - EQDMA_GLBL_TRQ_ERR_MSK_ADDR, - EQDMA_GLBL_TRQ_ERR_STS_ADDR, - GLBL_TRQ_ERR_STS_QSPC_UNMAPPED_MASK, - GLBL_ERR_STAT_ERR_TRQ_MASK, - &eqdma_hw_trq_err_process - }, - { - EQDMA_TRQ_ERR_QID_RANGE, - "Qid range error", - EQDMA_GLBL_TRQ_ERR_MSK_ADDR, - EQDMA_GLBL_TRQ_ERR_STS_ADDR, - GLBL_TRQ_ERR_STS_QID_RANGE_MASK, - GLBL_ERR_STAT_ERR_TRQ_MASK, - &eqdma_hw_trq_err_process - }, - { - EQDMA_TRQ_ERR_TCP_QSPC_TIMEOUT, - "Timeout on request to dma internal queue space register", - EQDMA_GLBL_TRQ_ERR_MSK_ADDR, - EQDMA_GLBL_TRQ_ERR_STS_ADDR, - GLBL_TRQ_ERR_STS_TCP_QSPC_TIMEOUT_MASK, - GLBL_ERR_STAT_ERR_TRQ_MASK, - &eqdma_hw_trq_err_process - }, - { - EQDMA_TRQ_ERR_ALL, - "All TRQ errors", - EQDMA_GLBL_TRQ_ERR_MSK_ADDR, - EQDMA_GLBL_TRQ_ERR_STS_ADDR, - EQDMA_GLBL_TRQ_ERR_ALL_MASK, - GLBL_ERR_STAT_ERR_TRQ_MASK, - &eqdma_hw_trq_err_process - }, - - /* C2H Errors*/ - { - EQDMA_ST_C2H_ERR_MTY_MISMATCH, - "MTY mismatch error", - EQDMA_C2H_ERR_MASK_ADDR, - EQDMA_C2H_ERR_STAT_ADDR, - C2H_ERR_STAT_MTY_MISMATCH_MASK, - GLBL_ERR_STAT_ERR_C2H_ST_MASK, - &eqdma_hw_st_c2h_err_process - }, - { - EQDMA_ST_C2H_ERR_LEN_MISMATCH, - "Packet length mismatch error", - EQDMA_C2H_ERR_MASK_ADDR, - EQDMA_C2H_ERR_STAT_ADDR, - C2H_ERR_STAT_LEN_MISMATCH_MASK, - GLBL_ERR_STAT_ERR_C2H_ST_MASK, - &eqdma_hw_st_c2h_err_process - }, - { - EQDMA_ST_C2H_ERR_SH_CMPT_DSC, - "A Shared CMPT queue has encountered a descriptor error", - EQDMA_C2H_ERR_MASK_ADDR, - EQDMA_C2H_ERR_STAT_ADDR, - C2H_ERR_STAT_SH_CMPT_DSC_ERR_MASK, - GLBL_ERR_STAT_ERR_C2H_ST_MASK, - &eqdma_hw_st_c2h_err_process - }, - { - EQDMA_ST_C2H_ERR_QID_MISMATCH, - "Qid mismatch error", - EQDMA_C2H_ERR_MASK_ADDR, - EQDMA_C2H_ERR_STAT_ADDR, - C2H_ERR_STAT_QID_MISMATCH_MASK, - GLBL_ERR_STAT_ERR_C2H_ST_MASK, - &eqdma_hw_st_c2h_err_process - }, - { - EQDMA_ST_C2H_ERR_DESC_RSP_ERR, - "Descriptor error bit set", - EQDMA_C2H_ERR_MASK_ADDR, - EQDMA_C2H_ERR_STAT_ADDR, - C2H_ERR_STAT_DESC_RSP_ERR_MASK, - GLBL_ERR_STAT_ERR_C2H_ST_MASK, - &eqdma_hw_st_c2h_err_process - }, - { - EQDMA_ST_C2H_ERR_ENG_WPL_DATA_PAR_ERR, - "Data parity error", - EQDMA_C2H_ERR_MASK_ADDR, - EQDMA_C2H_ERR_STAT_ADDR, - C2H_ERR_STAT_ENG_WPL_DATA_PAR_ERR_MASK, - GLBL_ERR_STAT_ERR_C2H_ST_MASK, - &eqdma_hw_st_c2h_err_process - }, - { - EQDMA_ST_C2H_ERR_MSI_INT_FAIL, - "MSI got a fail response error", - EQDMA_C2H_ERR_MASK_ADDR, - EQDMA_C2H_ERR_STAT_ADDR, - C2H_ERR_STAT_MSI_INT_FAIL_MASK, - GLBL_ERR_STAT_ERR_C2H_ST_MASK, - &eqdma_hw_st_c2h_err_process - }, - { - EQDMA_ST_C2H_ERR_ERR_DESC_CNT, - "Descriptor count error", - EQDMA_C2H_ERR_MASK_ADDR, - EQDMA_C2H_ERR_STAT_ADDR, - C2H_ERR_STAT_ERR_DESC_CNT_MASK, - GLBL_ERR_STAT_ERR_C2H_ST_MASK, - &eqdma_hw_st_c2h_err_process - }, - { - EQDMA_ST_C2H_ERR_PORTID_CTXT_MISMATCH, - "Port id in packet and pfetch ctxt mismatch error", - EQDMA_C2H_ERR_MASK_ADDR, - EQDMA_C2H_ERR_STAT_ADDR, - C2H_ERR_STAT_PORT_ID_CTXT_MISMATCH_MASK, - GLBL_ERR_STAT_ERR_C2H_ST_MASK, - &eqdma_hw_st_c2h_err_process - }, - { - EQDMA_ST_C2H_ERR_CMPT_INV_Q_ERR, - "Writeback on invalid queue error", - EQDMA_C2H_ERR_MASK_ADDR, - EQDMA_C2H_ERR_STAT_ADDR, - C2H_ERR_STAT_WRB_INV_Q_ERR_MASK, - GLBL_ERR_STAT_ERR_C2H_ST_MASK, - &eqdma_hw_st_c2h_err_process - }, - { - EQDMA_ST_C2H_ERR_CMPT_QFULL_ERR, - "Completion queue gets full error", - EQDMA_C2H_ERR_MASK_ADDR, - EQDMA_C2H_ERR_STAT_ADDR, - C2H_ERR_STAT_WRB_QFULL_ERR_MASK, - GLBL_ERR_STAT_ERR_C2H_ST_MASK, - &eqdma_hw_st_c2h_err_process - }, - { - EQDMA_ST_C2H_ERR_CMPT_CIDX_ERR, - "Bad CIDX update by the software error", - EQDMA_C2H_ERR_MASK_ADDR, - EQDMA_C2H_ERR_STAT_ADDR, - C2H_ERR_STAT_WRB_CIDX_ERR_MASK, - GLBL_ERR_STAT_ERR_C2H_ST_MASK, - &eqdma_hw_st_c2h_err_process - }, - { - EQDMA_ST_C2H_ERR_CMPT_PRTY_ERR, - "C2H completion Parity error", - EQDMA_C2H_ERR_MASK_ADDR, - EQDMA_C2H_ERR_STAT_ADDR, - C2H_ERR_STAT_WRB_PRTY_ERR_MASK, - GLBL_ERR_STAT_ERR_C2H_ST_MASK, - &eqdma_hw_st_c2h_err_process - }, - { - EQDMA_ST_C2H_ERR_AVL_RING_DSC, - "Available ring fetch returns descriptor with error", - EQDMA_C2H_ERR_MASK_ADDR, - EQDMA_C2H_ERR_STAT_ADDR, - C2H_ERR_STAT_AVL_RING_DSC_ERR_MASK, - GLBL_ERR_STAT_ERR_C2H_ST_MASK, - &eqdma_hw_st_c2h_err_process - }, - { - EQDMA_ST_C2H_ERR_HDR_ECC_UNC, - "multi-bit ecc error on c2h packet header", - EQDMA_C2H_ERR_MASK_ADDR, - EQDMA_C2H_ERR_STAT_ADDR, - C2H_ERR_STAT_HDR_ECC_UNC_ERR_MASK, - GLBL_ERR_STAT_ERR_C2H_ST_MASK, - &eqdma_hw_st_c2h_err_process - }, - { - EQDMA_ST_C2H_ERR_HDR_ECC_COR, - "single-bit ecc error on c2h packet header", - EQDMA_C2H_ERR_MASK_ADDR, - EQDMA_C2H_ERR_STAT_ADDR, - C2H_ERR_STAT_HDR_ECC_COR_ERR_MASK, - GLBL_ERR_STAT_ERR_C2H_ST_MASK, - &eqdma_hw_st_c2h_err_process - }, - { - EQDMA_ST_C2H_ERR_WRB_PORT_ID_ERR, - "Port ID error", - EQDMA_C2H_ERR_MASK_ADDR, - EQDMA_C2H_ERR_STAT_ADDR, - C2H_ERR_STAT_WRB_PORT_ID_ERR_MASK, - GLBL_ERR_STAT_ERR_C2H_ST_MASK, - &eqdma_hw_st_c2h_err_process - }, - { - EQDMA_ST_C2H_ERR_ALL, - "All C2h errors", - EQDMA_C2H_ERR_MASK_ADDR, - EQDMA_C2H_ERR_STAT_ADDR, - EQDMA_C2H_ERR_ALL_MASK, - GLBL_ERR_STAT_ERR_C2H_ST_MASK, - &eqdma_hw_st_c2h_err_process - }, - - /* C2H fatal errors */ - { - EQDMA_ST_FATAL_ERR_MTY_MISMATCH, - "Fatal MTY mismatch error", - EQDMA_C2H_FATAL_ERR_MASK_ADDR, - EQDMA_C2H_FATAL_ERR_STAT_ADDR, - C2H_FATAL_ERR_STAT_MTY_MISMATCH_MASK, - GLBL_ERR_STAT_ERR_C2H_ST_MASK, - &eqdma_hw_st_c2h_err_process - }, - { - EQDMA_ST_FATAL_ERR_LEN_MISMATCH, - "Fatal Len mismatch error", - EQDMA_C2H_FATAL_ERR_MASK_ADDR, - EQDMA_C2H_FATAL_ERR_STAT_ADDR, - C2H_FATAL_ERR_STAT_LEN_MISMATCH_MASK, - GLBL_ERR_STAT_ERR_C2H_ST_MASK, - &eqdma_hw_st_c2h_err_process - }, - { - EQDMA_ST_FATAL_ERR_QID_MISMATCH, - "Fatal Qid mismatch error", - EQDMA_C2H_FATAL_ERR_MASK_ADDR, - EQDMA_C2H_FATAL_ERR_STAT_ADDR, - C2H_FATAL_ERR_STAT_QID_MISMATCH_MASK, - GLBL_ERR_STAT_ERR_C2H_ST_MASK, - &eqdma_hw_st_c2h_err_process - }, - { - EQDMA_ST_FATAL_ERR_TIMER_FIFO_RAM_RDBE, - "RAM double bit fatal error", - EQDMA_C2H_FATAL_ERR_MASK_ADDR, - EQDMA_C2H_FATAL_ERR_STAT_ADDR, - C2H_FATAL_ERR_STAT_TIMER_FIFO_RAM_RDBE_MASK, - GLBL_ERR_STAT_ERR_C2H_ST_MASK, - &eqdma_hw_st_c2h_err_process - }, - { - EQDMA_ST_FATAL_ERR_PFCH_II_RAM_RDBE, - "RAM double bit fatal error", - EQDMA_C2H_FATAL_ERR_MASK_ADDR, - EQDMA_C2H_FATAL_ERR_STAT_ADDR, - C2H_FATAL_ERR_STAT_PFCH_LL_RAM_RDBE_MASK, - GLBL_ERR_STAT_ERR_C2H_ST_MASK, - &eqdma_hw_st_c2h_err_process - }, - { - EQDMA_ST_FATAL_ERR_CMPT_CTXT_RAM_RDBE, - "RAM double bit fatal error", - EQDMA_C2H_FATAL_ERR_MASK_ADDR, - EQDMA_C2H_FATAL_ERR_STAT_ADDR, - C2H_FATAL_ERR_STAT_WRB_CTXT_RAM_RDBE_MASK, - GLBL_ERR_STAT_ERR_C2H_ST_MASK, - &eqdma_hw_st_c2h_err_process - }, - { - EQDMA_ST_FATAL_ERR_PFCH_CTXT_RAM_RDBE, - "RAM double bit fatal error", - EQDMA_C2H_FATAL_ERR_MASK_ADDR, - EQDMA_C2H_FATAL_ERR_STAT_ADDR, - C2H_FATAL_ERR_STAT_PFCH_CTXT_RAM_RDBE_MASK, - GLBL_ERR_STAT_ERR_C2H_ST_MASK, - &eqdma_hw_st_c2h_err_process - }, - { - EQDMA_ST_FATAL_ERR_DESC_REQ_FIFO_RAM_RDBE, - "RAM double bit fatal error", - EQDMA_C2H_FATAL_ERR_MASK_ADDR, - EQDMA_C2H_FATAL_ERR_STAT_ADDR, - C2H_FATAL_ERR_STAT_DESC_REQ_FIFO_RAM_RDBE_MASK, - GLBL_ERR_STAT_ERR_C2H_ST_MASK, - &eqdma_hw_st_c2h_err_process - }, - { - EQDMA_ST_FATAL_ERR_INT_CTXT_RAM_RDBE, - "RAM double bit fatal error", - EQDMA_C2H_FATAL_ERR_MASK_ADDR, - EQDMA_C2H_FATAL_ERR_STAT_ADDR, - C2H_FATAL_ERR_STAT_INT_CTXT_RAM_RDBE_MASK, - GLBL_ERR_STAT_ERR_C2H_ST_MASK, - &eqdma_hw_st_c2h_err_process - }, - { - EQDMA_ST_FATAL_ERR_CMPT_COAL_DATA_RAM_RDBE, - "RAM double bit fatal error", - EQDMA_C2H_FATAL_ERR_MASK_ADDR, - EQDMA_C2H_FATAL_ERR_STAT_ADDR, - C2H_FATAL_ERR_STAT_WRB_COAL_DATA_RAM_RDBE_MASK, - GLBL_ERR_STAT_ERR_C2H_ST_MASK, - &eqdma_hw_st_c2h_err_process - }, - { - EQDMA_ST_FATAL_ERR_CMPT_FIFO_RAM_RDBE, - "RAM double bit fatal error", - EQDMA_C2H_FATAL_ERR_MASK_ADDR, - EQDMA_C2H_FATAL_ERR_STAT_ADDR, - C2H_FATAL_ERR_STAT_CMPT_FIFO_RAM_RDBE_MASK, - GLBL_ERR_STAT_ERR_C2H_ST_MASK, - &eqdma_hw_st_c2h_err_process - }, - { - EQDMA_ST_FATAL_ERR_QID_FIFO_RAM_RDBE, - "RAM double bit fatal error", - EQDMA_C2H_FATAL_ERR_MASK_ADDR, - EQDMA_C2H_FATAL_ERR_STAT_ADDR, - C2H_FATAL_ERR_STAT_QID_FIFO_RAM_RDBE_MASK, - GLBL_ERR_STAT_ERR_C2H_ST_MASK, - &eqdma_hw_st_c2h_err_process - }, - { - EQDMA_ST_FATAL_ERR_PAYLOAD_FIFO_RAM_RDBE, - "RAM double bit fatal error", - EQDMA_C2H_FATAL_ERR_MASK_ADDR, - EQDMA_C2H_FATAL_ERR_STAT_ADDR, - C2H_FATAL_ERR_STAT_PLD_FIFO_RAM_RDBE_MASK, - GLBL_ERR_STAT_ERR_C2H_ST_MASK, - &eqdma_hw_st_c2h_err_process - }, - { - EQDMA_ST_FATAL_ERR_WPL_DATA_PAR, - "RAM double bit fatal error", - EQDMA_C2H_FATAL_ERR_MASK_ADDR, - EQDMA_C2H_FATAL_ERR_STAT_ADDR, - C2H_FATAL_ERR_STAT_WPL_DATA_PAR_ERR_MASK, - GLBL_ERR_STAT_ERR_C2H_ST_MASK, - &eqdma_hw_st_c2h_err_process - }, - { - EQDMA_ST_FATAL_ERR_AVL_RING_FIFO_RAM_RDBE, - "RAM double bit fatal error", - EQDMA_C2H_FATAL_ERR_MASK_ADDR, - EQDMA_C2H_FATAL_ERR_STAT_ADDR, - C2H_FATAL_ERR_STAT_AVL_RING_FIFO_RAM_RDBE_MASK, - GLBL_ERR_STAT_ERR_C2H_ST_MASK, - &eqdma_hw_st_c2h_err_process - }, - { - EQDMA_ST_FATAL_ERR_HDR_ECC_UNC, - "RAM double bit fatal error", - EQDMA_C2H_FATAL_ERR_MASK_ADDR, - EQDMA_C2H_FATAL_ERR_STAT_ADDR, - C2H_FATAL_ERR_STAT_HDR_ECC_UNC_ERR_MASK, - GLBL_ERR_STAT_ERR_C2H_ST_MASK, - &eqdma_hw_st_c2h_err_process - }, - { - EQDMA_ST_FATAL_ERR_ALL, - "All fatal errors", - EQDMA_C2H_FATAL_ERR_MASK_ADDR, - EQDMA_C2H_FATAL_ERR_STAT_ADDR, - EQDMA_C2H_FATAL_ERR_ALL_MASK, - GLBL_ERR_STAT_ERR_C2H_ST_MASK, - &eqdma_hw_st_c2h_err_process - }, - - /* H2C St errors */ - { - EQDMA_ST_H2C_ERR_ZERO_LEN_DESC, - "Zero length descriptor error", - EQDMA_H2C_ERR_MASK_ADDR, - EQDMA_H2C_ERR_STAT_ADDR, - H2C_ERR_STAT_ZERO_LEN_DS_MASK, - GLBL_ERR_STAT_ERR_H2C_ST_MASK, - &eqdma_hw_st_h2c_err_process - }, - { - EQDMA_ST_H2C_ERR_SDI_MRKR_REQ_MOP, - "A non-EOP descriptor received", - EQDMA_H2C_ERR_MASK_ADDR, - EQDMA_H2C_ERR_STAT_ADDR, - H2C_ERR_STAT_SDI_MRKR_REQ_MOP_ERR_MASK, - GLBL_ERR_STAT_ERR_H2C_ST_MASK, - &eqdma_hw_st_h2c_err_process - }, - { - EQDMA_ST_H2C_ERR_NO_DMA_DSC, - "No DMA descriptor received error", - EQDMA_H2C_ERR_MASK_ADDR, - EQDMA_H2C_ERR_STAT_ADDR, - H2C_ERR_STAT_NO_DMA_DS_MASK, - GLBL_ERR_STAT_ERR_H2C_ST_MASK, - &eqdma_hw_st_h2c_err_process - }, - { - EQDMA_ST_H2C_ERR_SBE, - "Single bit error detected on H2C-ST data error", - EQDMA_H2C_ERR_MASK_ADDR, - EQDMA_H2C_ERR_STAT_ADDR, - H2C_ERR_STAT_SBE_MASK, - GLBL_ERR_STAT_ERR_H2C_ST_MASK, - &eqdma_hw_st_h2c_err_process - }, - { - EQDMA_ST_H2C_ERR_DBE, - "Double bit error detected on H2C-ST data error", - EQDMA_H2C_ERR_MASK_ADDR, - EQDMA_H2C_ERR_STAT_ADDR, - H2C_ERR_STAT_DBE_MASK, - GLBL_ERR_STAT_ERR_H2C_ST_MASK, - &eqdma_hw_st_h2c_err_process - }, - { - EQDMA_ST_H2C_ERR_PAR, - "Internal data parity error", - EQDMA_H2C_ERR_MASK_ADDR, - EQDMA_H2C_ERR_STAT_ADDR, - H2C_ERR_STAT_PAR_ERR_MASK, - GLBL_ERR_STAT_ERR_H2C_ST_MASK, - &eqdma_hw_st_h2c_err_process - }, - { - EQDMA_ST_H2C_ERR_ALL, - "All H2C errors", - EQDMA_H2C_ERR_MASK_ADDR, - EQDMA_H2C_ERR_STAT_ADDR, - EQDMA_H2C_ERR_ALL_MASK, - GLBL_ERR_STAT_ERR_H2C_ST_MASK, - &eqdma_hw_st_h2c_err_process - }, - - /* SBE errors */ - { - EQDMA_SBE_1_ERR_RC_RRQ_EVEN_RAM, - "RC RRQ Even RAM single bit ECC error.", - EQDMA_RAM_SBE_MSK_1_A_ADDR, - EQDMA_RAM_SBE_STS_1_A_ADDR, - RAM_SBE_STS_1_A_RC_RRQ_EVEN_RAM_MASK, - GLBL_ERR_STAT_ERR_RAM_SBE_MASK, - &eqdma_hw_ram_sbe_err_process - }, - { - EQDMA_SBE_1_ERR_TAG_ODD_RAM, - "Tag Odd Ram single bit ECC error.", - EQDMA_RAM_SBE_MSK_1_A_ADDR, - EQDMA_RAM_SBE_STS_1_A_ADDR, - RAM_SBE_STS_1_A_TAG_ODD_RAM_MASK, - GLBL_ERR_STAT_ERR_RAM_SBE_MASK, - &eqdma_hw_ram_sbe_err_process - }, - { - EQDMA_SBE_1_ERR_TAG_EVEN_RAM, - "Tag Even Ram single bit ECC error.", - EQDMA_RAM_SBE_MSK_1_A_ADDR, - EQDMA_RAM_SBE_STS_1_A_ADDR, - RAM_SBE_STS_1_A_TAG_EVEN_RAM_MASK, - GLBL_ERR_STAT_ERR_RAM_SBE_MASK, - &eqdma_hw_ram_sbe_err_process - }, - { - EQDMA_SBE_1_ERR_PFCH_CTXT_CAM_RAM_0, - "Pfch Ctxt CAM RAM 0 single bit ECC error.", - EQDMA_RAM_SBE_MSK_1_A_ADDR, - EQDMA_RAM_SBE_STS_1_A_ADDR, - RAM_SBE_STS_1_A_PFCH_CTXT_CAM_RAM_0_MASK, - GLBL_ERR_STAT_ERR_RAM_SBE_MASK, - &eqdma_hw_ram_sbe_err_process - }, - { - EQDMA_SBE_1_ERR_PFCH_CTXT_CAM_RAM_1, - "Pfch Ctxt CAM RAM 1 single bit ECC error.", - EQDMA_RAM_SBE_MSK_1_A_ADDR, - EQDMA_RAM_SBE_STS_1_A_ADDR, - RAM_SBE_STS_1_A_PFCH_CTXT_CAM_RAM_1_MASK, - GLBL_ERR_STAT_ERR_RAM_SBE_MASK, - &eqdma_hw_ram_sbe_err_process - }, - { - EQDMA_SBE_1_ERR_ALL, - "All SBE Errors.", - EQDMA_RAM_SBE_MSK_1_A_ADDR, - EQDMA_RAM_SBE_STS_1_A_ADDR, - EQDMA_SBE_ERR_ALL_MASK, - GLBL_ERR_STAT_ERR_RAM_SBE_MASK, - &eqdma_hw_ram_sbe_err_process - }, - { - EQDMA_SBE_ERR_MI_H2C0_DAT, - "H2C MM data buffer single bit ECC error", - EQDMA_RAM_SBE_MSK_A_ADDR, - EQDMA_RAM_SBE_STS_A_ADDR, - RAM_SBE_STS_A_MI_H2C0_DAT_MASK, - GLBL_ERR_STAT_ERR_RAM_SBE_MASK, - &eqdma_hw_ram_sbe_err_process - }, - { - EQDMA_SBE_ERR_MI_H2C1_DAT, - "H2C MM data buffer single bit ECC error", - EQDMA_RAM_SBE_MSK_A_ADDR, - EQDMA_RAM_SBE_STS_A_ADDR, - RAM_SBE_STS_A_MI_H2C1_DAT_MASK, - GLBL_ERR_STAT_ERR_RAM_SBE_MASK, - &eqdma_hw_ram_sbe_err_process - }, - { - EQDMA_SBE_ERR_MI_H2C2_DAT, - "H2C MM data buffer single bit ECC error", - EQDMA_RAM_SBE_MSK_A_ADDR, - EQDMA_RAM_SBE_STS_A_ADDR, - RAM_SBE_STS_A_MI_H2C2_DAT_MASK, - GLBL_ERR_STAT_ERR_RAM_SBE_MASK, - &eqdma_hw_ram_sbe_err_process - }, - { - EQDMA_SBE_ERR_MI_H2C3_DAT, - "H2C MM data buffer single bit ECC error", - EQDMA_RAM_SBE_MSK_A_ADDR, - EQDMA_RAM_SBE_STS_A_ADDR, - RAM_SBE_STS_A_MI_H2C3_DAT_MASK, - GLBL_ERR_STAT_ERR_RAM_SBE_MASK, - &eqdma_hw_ram_sbe_err_process - }, - { - EQDMA_SBE_ERR_MI_C2H0_DAT, - "C2H MM data buffer single bit ECC error", - EQDMA_RAM_SBE_MSK_A_ADDR, - EQDMA_RAM_SBE_STS_A_ADDR, - RAM_SBE_STS_A_MI_C2H0_DAT_MASK, - GLBL_ERR_STAT_ERR_RAM_SBE_MASK, - &eqdma_hw_ram_sbe_err_process - }, - { - EQDMA_SBE_ERR_MI_C2H1_DAT, - "C2H MM data buffer single bit ECC error", - EQDMA_RAM_SBE_MSK_A_ADDR, - EQDMA_RAM_SBE_STS_A_ADDR, - RAM_SBE_STS_A_MI_C2H1_DAT_MASK, - GLBL_ERR_STAT_ERR_RAM_SBE_MASK, - &eqdma_hw_ram_sbe_err_process - }, -{ - EQDMA_SBE_ERR_MI_C2H2_DAT, - "C2H MM data buffer single bit ECC error", - EQDMA_RAM_SBE_MSK_A_ADDR, - EQDMA_RAM_SBE_STS_A_ADDR, - RAM_SBE_STS_A_MI_C2H2_DAT_MASK, - GLBL_ERR_STAT_ERR_RAM_SBE_MASK, - &eqdma_hw_ram_sbe_err_process - }, - { - EQDMA_SBE_ERR_MI_C2H3_DAT, - "C2H MM data buffer single bit ECC error", - EQDMA_RAM_SBE_MSK_A_ADDR, - EQDMA_RAM_SBE_STS_A_ADDR, - RAM_SBE_STS_A_MI_C2H3_DAT_MASK, - GLBL_ERR_STAT_ERR_RAM_SBE_MASK, - &eqdma_hw_ram_sbe_err_process - }, - { - EQDMA_SBE_ERR_H2C_RD_BRG_DAT, - "Bridge master read single bit ECC error", - EQDMA_RAM_SBE_MSK_A_ADDR, - EQDMA_RAM_SBE_STS_A_ADDR, - RAM_SBE_STS_A_H2C_RD_BRG_DAT_MASK, - GLBL_ERR_STAT_ERR_RAM_SBE_MASK, - &eqdma_hw_ram_sbe_err_process - }, - { - EQDMA_SBE_ERR_H2C_WR_BRG_DAT, - "Bridge master write single bit ECC error", - EQDMA_RAM_SBE_MSK_A_ADDR, - EQDMA_RAM_SBE_STS_A_ADDR, - RAM_SBE_STS_A_H2C_WR_BRG_DAT_MASK, - GLBL_ERR_STAT_ERR_RAM_SBE_MASK, - &eqdma_hw_ram_sbe_err_process - }, - { - EQDMA_SBE_ERR_C2H_RD_BRG_DAT, - "Bridge slave read data buffer single bit ECC error", - EQDMA_RAM_SBE_MSK_A_ADDR, - EQDMA_RAM_SBE_STS_A_ADDR, - RAM_SBE_STS_A_C2H_RD_BRG_DAT_MASK, - GLBL_ERR_STAT_ERR_RAM_SBE_MASK, - &eqdma_hw_ram_sbe_err_process - }, - { - EQDMA_SBE_ERR_C2H_WR_BRG_DAT, - "Bridge slave write data buffer single bit ECC error", - EQDMA_RAM_SBE_MSK_A_ADDR, - EQDMA_RAM_SBE_STS_A_ADDR, - RAM_SBE_STS_A_C2H_WR_BRG_DAT_MASK, - GLBL_ERR_STAT_ERR_RAM_SBE_MASK, - &eqdma_hw_ram_sbe_err_process - }, - { - EQDMA_SBE_ERR_FUNC_MAP, - "Function map RAM single bit ECC error", - EQDMA_RAM_SBE_MSK_A_ADDR, - EQDMA_RAM_SBE_STS_A_ADDR, - RAM_SBE_STS_A_FUNC_MAP_MASK, - GLBL_ERR_STAT_ERR_RAM_SBE_MASK, - &eqdma_hw_ram_sbe_err_process - }, - { - EQDMA_SBE_ERR_DSC_HW_CTXT, - "Descriptor engine hardware context RAM single bit ECC error", - EQDMA_RAM_SBE_MSK_A_ADDR, - EQDMA_RAM_SBE_STS_A_ADDR, - RAM_SBE_STS_A_DSC_HW_CTXT_MASK, - GLBL_ERR_STAT_ERR_RAM_SBE_MASK, - &eqdma_hw_ram_sbe_err_process - }, - { - EQDMA_SBE_ERR_DSC_CRD_RCV, - "Descriptor engine receive credit context RAM single bit ECC error", - EQDMA_RAM_SBE_MSK_A_ADDR, - EQDMA_RAM_SBE_STS_A_ADDR, - RAM_SBE_STS_A_DSC_CRD_RCV_MASK, - GLBL_ERR_STAT_ERR_RAM_SBE_MASK, - &eqdma_hw_ram_sbe_err_process - }, - { - EQDMA_SBE_ERR_DSC_SW_CTXT, - "Descriptor engine software context RAM single bit ECC error", - EQDMA_RAM_SBE_MSK_A_ADDR, - EQDMA_RAM_SBE_STS_A_ADDR, - RAM_SBE_STS_A_DSC_SW_CTXT_MASK, - GLBL_ERR_STAT_ERR_RAM_SBE_MASK, - &eqdma_hw_ram_sbe_err_process - }, - { - EQDMA_SBE_ERR_DSC_CPLI, - "Descriptor engine fetch completion information RAM single bit ECC error", - EQDMA_RAM_SBE_MSK_A_ADDR, - EQDMA_RAM_SBE_STS_A_ADDR, - RAM_SBE_STS_A_DSC_CPLI_MASK, - GLBL_ERR_STAT_ERR_RAM_SBE_MASK, - &eqdma_hw_ram_sbe_err_process - }, - { - EQDMA_SBE_ERR_DSC_CPLD, - "Descriptor engine fetch completion data RAM single bit ECC error", - EQDMA_RAM_SBE_MSK_A_ADDR, - EQDMA_RAM_SBE_STS_A_ADDR, - RAM_SBE_STS_A_DSC_CPLD_MASK, - GLBL_ERR_STAT_ERR_RAM_SBE_MASK, - &eqdma_hw_ram_sbe_err_process - }, - { - EQDMA_SBE_ERR_MI_TL_SLV_FIFO_RAM, - "TL Slavle FIFO RAM single bit ECC error", - EQDMA_RAM_SBE_MSK_A_ADDR, - EQDMA_RAM_SBE_STS_A_ADDR, - RAM_SBE_STS_A_MI_TL_SLV_FIFO_RAM_MASK, - GLBL_ERR_STAT_ERR_RAM_SBE_MASK, - &eqdma_hw_ram_sbe_err_process - }, - { - EQDMA_SBE_ERR_TIMER_FIFO_RAM, - "Timer fifo RAM single bit ECC error", - EQDMA_RAM_SBE_MSK_A_ADDR, - EQDMA_RAM_SBE_STS_A_ADDR, - RAM_SBE_STS_A_TIMER_FIFO_RAM_MASK, - GLBL_ERR_STAT_ERR_RAM_SBE_MASK, - &eqdma_hw_ram_sbe_err_process - }, - { - EQDMA_SBE_ERR_QID_FIFO_RAM, - "C2H ST QID FIFO RAM single bit ECC error", - EQDMA_RAM_SBE_MSK_A_ADDR, - EQDMA_RAM_SBE_STS_A_ADDR, - RAM_SBE_STS_A_QID_FIFO_RAM_MASK, - GLBL_ERR_STAT_ERR_RAM_SBE_MASK, - &eqdma_hw_ram_sbe_err_process - }, - { - EQDMA_SBE_ERR_WRB_COAL_DATA_RAM, - "Writeback Coalescing RAM single bit ECC error", - EQDMA_RAM_SBE_MSK_A_ADDR, - EQDMA_RAM_SBE_STS_A_ADDR, - RAM_SBE_STS_A_WRB_COAL_DATA_RAM_MASK, - GLBL_ERR_STAT_ERR_RAM_SBE_MASK, - &eqdma_hw_ram_sbe_err_process - }, - { - EQDMA_SBE_ERR_INT_CTXT_RAM, - "Interrupt context RAM single bit ECC error", - EQDMA_RAM_SBE_MSK_A_ADDR, - EQDMA_RAM_SBE_STS_A_ADDR, - RAM_SBE_STS_A_INT_CTXT_RAM_MASK, - GLBL_ERR_STAT_ERR_RAM_SBE_MASK, - &eqdma_hw_ram_sbe_err_process - }, - { - EQDMA_SBE_ERR_DESC_REQ_FIFO_RAM, - "C2H ST descriptor request RAM single bit ECC error", - EQDMA_RAM_SBE_MSK_A_ADDR, - EQDMA_RAM_SBE_STS_A_ADDR, - RAM_SBE_STS_A_DESC_REQ_FIFO_RAM_MASK, - GLBL_ERR_STAT_ERR_RAM_SBE_MASK, - &eqdma_hw_ram_sbe_err_process - }, - { - EQDMA_SBE_ERR_PFCH_CTXT_RAM, - "C2H ST prefetch RAM single bit ECC error", - EQDMA_RAM_SBE_MSK_A_ADDR, - EQDMA_RAM_SBE_STS_A_ADDR, - RAM_SBE_STS_A_PFCH_CTXT_RAM_MASK, - GLBL_ERR_STAT_ERR_RAM_SBE_MASK, - &eqdma_hw_ram_sbe_err_process - }, - { - EQDMA_SBE_ERR_WRB_CTXT_RAM, - "C2H ST completion context RAM single bit ECC error", - EQDMA_RAM_SBE_MSK_A_ADDR, - EQDMA_RAM_SBE_STS_A_ADDR, - RAM_SBE_STS_A_WRB_CTXT_RAM_MASK, - GLBL_ERR_STAT_ERR_RAM_SBE_MASK, - &eqdma_hw_ram_sbe_err_process - }, - { - EQDMA_SBE_ERR_PFCH_LL_RAM, - "C2H ST prefetch list RAM single bit ECC error", - EQDMA_RAM_SBE_MSK_A_ADDR, - EQDMA_RAM_SBE_STS_A_ADDR, - RAM_SBE_STS_A_PFCH_LL_RAM_MASK, - GLBL_ERR_STAT_ERR_RAM_SBE_MASK, - &eqdma_hw_ram_sbe_err_process - }, - { - EQDMA_SBE_ERR_PEND_FIFO_RAM, - "Pend FIFO RAM single bit ECC error", - EQDMA_RAM_SBE_MSK_A_ADDR, - EQDMA_RAM_SBE_STS_A_ADDR, - RAM_SBE_STS_A_PEND_FIFO_RAM_MASK, - GLBL_ERR_STAT_ERR_RAM_SBE_MASK, - &eqdma_hw_ram_sbe_err_process - }, - { - EQDMA_SBE_ERR_RC_RRQ_ODD_RAM, - "RC RRQ Odd RAM single bit ECC error.", - EQDMA_RAM_SBE_MSK_A_ADDR, - EQDMA_RAM_SBE_STS_A_ADDR, - RAM_SBE_STS_A_RC_RRQ_ODD_RAM_MASK, - GLBL_ERR_STAT_ERR_RAM_SBE_MASK, - &eqdma_hw_ram_sbe_err_process - }, - { - EQDMA_SBE_ERR_ALL, - "All SBE errors", - EQDMA_RAM_SBE_MSK_A_ADDR, - EQDMA_RAM_SBE_STS_A_ADDR, - EQDMA_SBE_ERR_ALL_MASK, - GLBL_ERR_STAT_ERR_RAM_SBE_MASK, - &eqdma_hw_ram_sbe_err_process - }, - - - /* DBE errors */ - { - EQDMA_DBE_1_ERR_RC_RRQ_EVEN_RAM, - "RC RRQ Odd RAM double bit ECC error.", - EQDMA_RAM_DBE_MSK_1_A_ADDR, - EQDMA_RAM_DBE_STS_1_A_ADDR, - RAM_DBE_STS_1_A_RC_RRQ_EVEN_RAM_MASK, - GLBL_ERR_STAT_ERR_RAM_DBE_MASK, - &eqdma_hw_ram_dbe_err_process - }, - { - EQDMA_DBE_1_ERR_TAG_ODD_RAM, - "Tag Odd Ram double bit ECC error.", - EQDMA_RAM_DBE_MSK_1_A_ADDR, - EQDMA_RAM_DBE_STS_1_A_ADDR, - RAM_DBE_STS_1_A_TAG_ODD_RAM_MASK, - GLBL_ERR_STAT_ERR_RAM_DBE_MASK, - &eqdma_hw_ram_dbe_err_process - }, - { - EQDMA_DBE_1_ERR_TAG_EVEN_RAM, - "Tag Even Ram double bit ECC error.", - EQDMA_RAM_DBE_MSK_1_A_ADDR, - EQDMA_RAM_DBE_STS_1_A_ADDR, - RAM_DBE_STS_1_A_TAG_EVEN_RAM_MASK, - GLBL_ERR_STAT_ERR_RAM_DBE_MASK, - &eqdma_hw_ram_dbe_err_process - }, - { - EQDMA_DBE_1_ERR_PFCH_CTXT_CAM_RAM_0, - "Pfch Ctxt CAM RAM 0 double bit ECC error.", - EQDMA_RAM_DBE_MSK_1_A_ADDR, - EQDMA_RAM_DBE_STS_1_A_ADDR, - RAM_DBE_STS_1_A_PFCH_CTXT_CAM_RAM_0_MASK, - GLBL_ERR_STAT_ERR_RAM_DBE_MASK, - &eqdma_hw_ram_dbe_err_process - }, - { - EQDMA_DBE_1_ERR_PFCH_CTXT_CAM_RAM_1, - "Pfch Ctxt CAM RAM double bit ECC error.", - EQDMA_RAM_DBE_MSK_1_A_ADDR, - EQDMA_RAM_DBE_STS_1_A_ADDR, - RAM_DBE_STS_1_A_PFCH_CTXT_CAM_RAM_0_MASK, - GLBL_ERR_STAT_ERR_RAM_DBE_MASK, - &eqdma_hw_ram_dbe_err_process - }, - { - EQDMA_DBE_1_ERR_ALL, - "All DBE errors", - EQDMA_RAM_DBE_MSK_1_A_ADDR, - EQDMA_RAM_DBE_STS_1_A_ADDR, - EQDMA_DBE_ERR_ALL_MASK, - GLBL_ERR_STAT_ERR_RAM_DBE_MASK, - &eqdma_hw_ram_dbe_err_process - }, - { - EQDMA_DBE_ERR_MI_H2C0_DAT, - "H2C MM data buffer double bit ECC error", - EQDMA_RAM_DBE_MSK_A_ADDR, - EQDMA_RAM_DBE_STS_A_ADDR, - RAM_DBE_STS_A_MI_H2C0_DAT_MASK, - GLBL_ERR_STAT_ERR_RAM_DBE_MASK, - &eqdma_hw_ram_dbe_err_process - }, - { - EQDMA_DBE_ERR_MI_H2C1_DAT, - "H2C MM data buffer double bit ECC error", - EQDMA_RAM_DBE_MSK_A_ADDR, - EQDMA_RAM_DBE_STS_A_ADDR, - RAM_DBE_STS_A_MI_H2C1_DAT_MASK, - GLBL_ERR_STAT_ERR_RAM_DBE_MASK, - &eqdma_hw_ram_dbe_err_process - }, - { - EQDMA_DBE_ERR_MI_H2C2_DAT, - "H2C MM data buffer double bit ECC error", - EQDMA_RAM_DBE_MSK_A_ADDR, - EQDMA_RAM_DBE_STS_A_ADDR, - RAM_DBE_STS_A_MI_H2C2_DAT_MASK, - GLBL_ERR_STAT_ERR_RAM_DBE_MASK, - &eqdma_hw_ram_dbe_err_process - }, - { - EQDMA_DBE_ERR_MI_H2C3_DAT, - "H2C MM data buffer double bit ECC error", - EQDMA_RAM_DBE_MSK_A_ADDR, - EQDMA_RAM_DBE_STS_A_ADDR, - RAM_DBE_STS_A_MI_H2C3_DAT_MASK, - GLBL_ERR_STAT_ERR_RAM_DBE_MASK, - &eqdma_hw_ram_dbe_err_process - }, - { - EQDMA_DBE_ERR_MI_C2H0_DAT, - "C2H MM data buffer double bit ECC error", - EQDMA_RAM_DBE_MSK_A_ADDR, - EQDMA_RAM_DBE_STS_A_ADDR, - RAM_DBE_STS_A_MI_C2H0_DAT_MASK, - GLBL_ERR_STAT_ERR_RAM_DBE_MASK, - &eqdma_hw_ram_dbe_err_process - }, - { - EQDMA_DBE_ERR_MI_C2H1_DAT, - "C2H MM data buffer double bit ECC error", - EQDMA_RAM_DBE_MSK_A_ADDR, - EQDMA_RAM_DBE_STS_A_ADDR, - RAM_DBE_STS_A_MI_C2H1_DAT_MASK, - GLBL_ERR_STAT_ERR_RAM_DBE_MASK, - &eqdma_hw_ram_dbe_err_process - }, - { - EQDMA_DBE_ERR_MI_C2H2_DAT, - "C2H MM data buffer double bit ECC error", - EQDMA_RAM_DBE_MSK_A_ADDR, - EQDMA_RAM_DBE_STS_A_ADDR, - RAM_DBE_STS_A_MI_C2H2_DAT_MASK, - GLBL_ERR_STAT_ERR_RAM_DBE_MASK, - &eqdma_hw_ram_dbe_err_process - }, - { - EQDMA_DBE_ERR_MI_C2H3_DAT, - "C2H MM data buffer double bit ECC error", - EQDMA_RAM_DBE_MSK_A_ADDR, - EQDMA_RAM_DBE_STS_A_ADDR, - RAM_DBE_STS_A_MI_C2H3_DAT_MASK, - GLBL_ERR_STAT_ERR_RAM_DBE_MASK, - &eqdma_hw_ram_dbe_err_process - }, - { - EQDMA_DBE_ERR_H2C_RD_BRG_DAT, - "Bridge master read double bit ECC error", - EQDMA_RAM_DBE_MSK_A_ADDR, - EQDMA_RAM_DBE_STS_A_ADDR, - RAM_DBE_STS_A_H2C_RD_BRG_DAT_MASK, - GLBL_ERR_STAT_ERR_RAM_DBE_MASK, - &eqdma_hw_ram_dbe_err_process - }, - { - EQDMA_DBE_ERR_H2C_WR_BRG_DAT, - "Bridge master write double bit ECC error", - EQDMA_RAM_DBE_MSK_A_ADDR, - EQDMA_RAM_DBE_STS_A_ADDR, - RAM_DBE_STS_A_H2C_WR_BRG_DAT_MASK, - GLBL_ERR_STAT_ERR_RAM_DBE_MASK, - &eqdma_hw_ram_dbe_err_process - }, - { - EQDMA_DBE_ERR_C2H_RD_BRG_DAT, - "Bridge slave read data buffer double bit ECC error", - EQDMA_RAM_DBE_MSK_A_ADDR, - EQDMA_RAM_DBE_STS_A_ADDR, - RAM_DBE_STS_A_C2H_RD_BRG_DAT_MASK, - GLBL_ERR_STAT_ERR_RAM_DBE_MASK, - &eqdma_hw_ram_dbe_err_process - }, - { - EQDMA_DBE_ERR_C2H_WR_BRG_DAT, - "Bridge slave write data buffer double bit ECC error", - EQDMA_RAM_DBE_MSK_A_ADDR, - EQDMA_RAM_DBE_STS_A_ADDR, - RAM_DBE_STS_A_C2H_WR_BRG_DAT_MASK, - GLBL_ERR_STAT_ERR_RAM_DBE_MASK, - &eqdma_hw_ram_dbe_err_process - }, - { - EQDMA_DBE_ERR_FUNC_MAP, - "Function map RAM double bit ECC error", - EQDMA_RAM_DBE_MSK_A_ADDR, - EQDMA_RAM_DBE_STS_A_ADDR, - RAM_DBE_STS_A_FUNC_MAP_MASK, - GLBL_ERR_STAT_ERR_RAM_DBE_MASK, - &eqdma_hw_ram_dbe_err_process - }, - { - EQDMA_DBE_ERR_DSC_HW_CTXT, - "Descriptor engine hardware context RAM double bit ECC error", - EQDMA_RAM_DBE_MSK_A_ADDR, - EQDMA_RAM_DBE_STS_A_ADDR, - RAM_DBE_STS_A_DSC_HW_CTXT_MASK, - GLBL_ERR_STAT_ERR_RAM_DBE_MASK, - &eqdma_hw_ram_dbe_err_process - }, - { - EQDMA_DBE_ERR_DSC_CRD_RCV, - "Descriptor engine receive credit context RAM double bit ECC error", - EQDMA_RAM_DBE_MSK_A_ADDR, - EQDMA_RAM_DBE_STS_A_ADDR, - RAM_DBE_STS_A_DSC_CRD_RCV_MASK, - GLBL_ERR_STAT_ERR_RAM_DBE_MASK, - &eqdma_hw_ram_dbe_err_process - }, - { - EQDMA_DBE_ERR_DSC_SW_CTXT, - "Descriptor engine software context RAM double bit ECC error", - EQDMA_RAM_DBE_MSK_A_ADDR, - EQDMA_RAM_DBE_STS_A_ADDR, - RAM_DBE_STS_A_DSC_SW_CTXT_MASK, - GLBL_ERR_STAT_ERR_RAM_DBE_MASK, - &eqdma_hw_ram_dbe_err_process - }, - { - EQDMA_DBE_ERR_DSC_CPLI, - "Descriptor engine fetch completion information RAM double bit ECC error", - EQDMA_RAM_DBE_MSK_A_ADDR, - EQDMA_RAM_DBE_STS_A_ADDR, - RAM_DBE_STS_A_DSC_CPLI_MASK, - GLBL_ERR_STAT_ERR_RAM_DBE_MASK, - &eqdma_hw_ram_dbe_err_process - }, - { - EQDMA_DBE_ERR_DSC_CPLD, - "Descriptor engine fetch completion data RAM double bit ECC error", - EQDMA_RAM_DBE_MSK_A_ADDR, - EQDMA_RAM_DBE_STS_A_ADDR, - RAM_DBE_STS_A_DSC_CPLD_MASK, - GLBL_ERR_STAT_ERR_RAM_DBE_MASK, - &eqdma_hw_ram_dbe_err_process - }, - { - EQDMA_DBE_ERR_MI_TL_SLV_FIFO_RAM, - "TL Slave FIFO RAM double bit ECC error", - EQDMA_RAM_DBE_MSK_A_ADDR, - EQDMA_RAM_DBE_STS_A_ADDR, - RAM_DBE_STS_A_MI_TL_SLV_FIFO_RAM_MASK, - GLBL_ERR_STAT_ERR_RAM_DBE_MASK, - &eqdma_hw_ram_dbe_err_process - }, - { - EQDMA_DBE_ERR_TIMER_FIFO_RAM, - "Timer fifo RAM double bit ECC error", - EQDMA_RAM_DBE_MSK_A_ADDR, - EQDMA_RAM_DBE_STS_A_ADDR, - RAM_DBE_STS_A_TIMER_FIFO_RAM_MASK, - GLBL_ERR_STAT_ERR_RAM_DBE_MASK, - &eqdma_hw_ram_dbe_err_process - }, - { - EQDMA_DBE_ERR_QID_FIFO_RAM, - "C2H ST QID FIFO RAM double bit ECC error", - EQDMA_RAM_DBE_MSK_A_ADDR, - EQDMA_RAM_DBE_STS_A_ADDR, - RAM_DBE_STS_A_QID_FIFO_RAM_MASK, - GLBL_ERR_STAT_ERR_RAM_DBE_MASK, - &eqdma_hw_ram_dbe_err_process - }, - { - EQDMA_DBE_ERR_WRB_COAL_DATA_RAM, - "Writeback Coalescing RAM double bit ECC error", - EQDMA_RAM_DBE_MSK_A_ADDR, - EQDMA_RAM_DBE_STS_A_ADDR, - RAM_DBE_STS_A_WRB_COAL_DATA_RAM_MASK, - GLBL_ERR_STAT_ERR_RAM_DBE_MASK, - &eqdma_hw_ram_dbe_err_process - }, - { - EQDMA_DBE_ERR_INT_CTXT_RAM, - "Interrupt context RAM double bit ECC error", - EQDMA_RAM_DBE_MSK_A_ADDR, - EQDMA_RAM_DBE_STS_A_ADDR, - RAM_DBE_STS_A_INT_CTXT_RAM_MASK, - GLBL_ERR_STAT_ERR_RAM_DBE_MASK, - &eqdma_hw_ram_dbe_err_process - }, - { - EQDMA_DBE_ERR_DESC_REQ_FIFO_RAM, - "C2H ST descriptor request RAM double bit ECC error", - EQDMA_RAM_DBE_MSK_A_ADDR, - EQDMA_RAM_DBE_STS_A_ADDR, - RAM_DBE_STS_A_DESC_REQ_FIFO_RAM_MASK, - GLBL_ERR_STAT_ERR_RAM_DBE_MASK, - &eqdma_hw_ram_dbe_err_process - }, - { - EQDMA_DBE_ERR_PFCH_CTXT_RAM, - "C2H ST prefetch RAM double bit ECC error", - EQDMA_RAM_DBE_MSK_A_ADDR, - EQDMA_RAM_DBE_STS_A_ADDR, - RAM_DBE_STS_A_PFCH_CTXT_RAM_MASK, - GLBL_ERR_STAT_ERR_RAM_DBE_MASK, - &eqdma_hw_ram_dbe_err_process - }, - { - EQDMA_DBE_ERR_WRB_CTXT_RAM, - "C2H ST completion context RAM double bit ECC error", - EQDMA_RAM_DBE_MSK_A_ADDR, - EQDMA_RAM_DBE_STS_A_ADDR, - RAM_DBE_STS_A_WRB_CTXT_RAM_MASK, - GLBL_ERR_STAT_ERR_RAM_DBE_MASK, - &eqdma_hw_ram_dbe_err_process - }, - { - EQDMA_DBE_ERR_PFCH_LL_RAM, - "C2H ST prefetch list RAM double bit ECC error", - EQDMA_RAM_DBE_MSK_A_ADDR, - EQDMA_RAM_DBE_STS_A_ADDR, - RAM_DBE_STS_A_PFCH_LL_RAM_MASK, - GLBL_ERR_STAT_ERR_RAM_DBE_MASK, - &eqdma_hw_ram_dbe_err_process - }, - { - EQDMA_DBE_ERR_PEND_FIFO_RAM, - "Pend FIFO RAM double bit ECC error", - EQDMA_RAM_DBE_MSK_A_ADDR, - EQDMA_RAM_DBE_STS_A_ADDR, - RAM_DBE_STS_A_PEND_FIFO_RAM_MASK, - GLBL_ERR_STAT_ERR_RAM_DBE_MASK, - &eqdma_hw_ram_dbe_err_process - }, - { - EQDMA_DBE_ERR_RC_RRQ_ODD_RAM, - "RC RRQ Odd RAM double bit ECC error.", - EQDMA_RAM_DBE_MSK_A_ADDR, - EQDMA_RAM_DBE_STS_A_ADDR, - RAM_DBE_STS_A_RC_RRQ_ODD_RAM_MASK, - GLBL_ERR_STAT_ERR_RAM_DBE_MASK, - &eqdma_hw_ram_dbe_err_process - }, - { - EQDMA_DBE_ERR_ALL, - "All DBE errors", - EQDMA_RAM_DBE_MSK_A_ADDR, - EQDMA_RAM_DBE_STS_A_ADDR, - EQDMA_DBE_ERR_ALL_MASK, - GLBL_ERR_STAT_ERR_RAM_DBE_MASK, - &eqdma_hw_ram_dbe_err_process - }, - /* MM C2H Engine 0 errors */ - { - EQDMA_MM_C2H_WR_SLR_ERR, - "MM C2H0 WR SLV Error", - EQDMA_C2H_MM_ERR_CODE_ENABLE_MASK_ADDR, - EQDMA_C2H_MM_STATUS_ADDR, - C2H_MM_ERR_CODE_ENABLE_WR_SLV_ERR_MASK, - GLBL_ERR_STAT_ERR_C2H_MM_0_MASK, - &eqdma_mm_c2h0_err_process - }, - { - EQDMA_MM_C2H_RD_SLR_ERR, - "MM C2H0 RD SLV Error", - EQDMA_C2H_MM_ERR_CODE_ENABLE_MASK_ADDR, - EQDMA_C2H_MM_STATUS_ADDR, - C2H_MM_ERR_CODE_ENABLE_RD_SLV_ERR_MASK, - GLBL_ERR_STAT_ERR_C2H_MM_0_MASK, - &eqdma_mm_c2h0_err_process - }, - { - EQDMA_MM_C2H_WR_FLR_ERR, - "MM C2H0 WR FLR Error", - EQDMA_C2H_MM_ERR_CODE_ENABLE_MASK_ADDR, - EQDMA_C2H_MM_STATUS_ADDR, - C2H_MM_ERR_CODE_ENABLE_WR_FLR_MASK, - GLBL_ERR_STAT_ERR_C2H_MM_0_MASK, - &eqdma_mm_c2h0_err_process - }, - { - EQDMA_MM_C2H_UR_ERR, - "MM C2H0 Unsupported Request Error", - EQDMA_C2H_MM_ERR_CODE_ENABLE_MASK_ADDR, - EQDMA_C2H_MM_STATUS_ADDR, - C2H_MM_ERR_CODE_ENABLE_WR_UR_MASK, - GLBL_ERR_STAT_ERR_C2H_MM_0_MASK, - &eqdma_mm_c2h0_err_process - }, - { - EQDMA_MM_C2H_WR_UC_RAM_ERR, - "MM C2H0 Write Uncorrectable RAM Error", - EQDMA_C2H_MM_ERR_CODE_ENABLE_MASK_ADDR, - EQDMA_C2H_MM_STATUS_ADDR, - C2H_MM_ERR_CODE_ENABLE_WR_UC_RAM_MASK, - GLBL_ERR_STAT_ERR_C2H_MM_0_MASK, - &eqdma_mm_c2h0_err_process - }, - { - EQDMA_MM_C2H_ERR_ALL, - "All MM C2H Errors", - EQDMA_C2H_MM_ERR_CODE_ENABLE_MASK_ADDR, - EQDMA_C2H_MM_STATUS_ADDR, - EQDMA_MM_C2H_ERR_ALL_MASK, - GLBL_ERR_STAT_ERR_C2H_MM_0_MASK, - &eqdma_mm_c2h0_err_process - }, - /* MM H2C Engine 0 Errors */ - { - EQDMA_MM_H2C0_RD_HDR_POISON_ERR, - "MM H2C0 Read cmpt header pison Error", - EQDMA_H2C_MM_ERR_CODE_ENABLE_MASK_ADDR, - EQDMA_H2C_MM_STATUS_ADDR, - H2C_MM_ERR_CODE_ENABLE_RD_HRD_POISON_ERR_MASK, - GLBL_ERR_STAT_ERR_H2C_MM_0_MASK, - &eqdma_mm_h2c0_err_process - }, - { - EQDMA_MM_H2C0_RD_UR_CA_ERR, - "MM H2C0 Read cmpt unsupported request Error", - EQDMA_H2C_MM_ERR_CODE_ENABLE_MASK_ADDR, - EQDMA_H2C_MM_STATUS_ADDR, - H2C_MM_ERR_CODE_ENABLE_RD_UR_CA_MASK, - GLBL_ERR_STAT_ERR_H2C_MM_0_MASK, - &eqdma_mm_h2c0_err_process - }, - { - EQDMA_MM_H2C0_RD_HDR_BYTE_ERR, - "MM H2C0 Read cmpt hdr byte cnt Error", - EQDMA_H2C_MM_ERR_CODE_ENABLE_MASK_ADDR, - EQDMA_H2C_MM_STATUS_ADDR, - H2C_MM_ERR_CODE_ENABLE_RD_HDR_BYTE_ERR_MASK, - GLBL_ERR_STAT_ERR_H2C_MM_0_MASK, - &eqdma_mm_h2c0_err_process - }, - { - EQDMA_MM_H2C0_RD_HDR_PARAM_ERR, - "MM H2C0 Read cmpt hdr param mismatch Error", - EQDMA_H2C_MM_ERR_CODE_ENABLE_MASK_ADDR, - EQDMA_H2C_MM_STATUS_ADDR, - H2C_MM_ERR_CODE_ENABLE_RD_HDR_PARA_MASK, - GLBL_ERR_STAT_ERR_H2C_MM_0_MASK, - &eqdma_mm_h2c0_err_process - }, - { - EQDMA_MM_H2C0_RD_HDR_ADR_ERR, - "MM H2C0 Read cmpt hdr address mismatch Error", - EQDMA_H2C_MM_ERR_CODE_ENABLE_MASK_ADDR, - EQDMA_H2C_MM_STATUS_ADDR, - H2C_MM_ERR_CODE_ENABLE_RD_HDR_ADR_ERR_MASK, - GLBL_ERR_STAT_ERR_H2C_MM_0_MASK, - &eqdma_mm_h2c0_err_process - }, - { - EQDMA_MM_H2C0_RD_FLR_ERR, - "MM H2C0 Read flr Error", - EQDMA_H2C_MM_ERR_CODE_ENABLE_MASK_ADDR, - EQDMA_H2C_MM_STATUS_ADDR, - H2C_MM_ERR_CODE_ENABLE_RD_FLR_ERR_MASK, - GLBL_ERR_STAT_ERR_H2C_MM_0_MASK, - &eqdma_mm_h2c0_err_process - }, - { - EQDMA_MM_H2C0_RD_DAT_POISON_ERR, - "MM H2C0 Read data poison Error", - EQDMA_H2C_MM_ERR_CODE_ENABLE_MASK_ADDR, - EQDMA_H2C_MM_STATUS_ADDR, - H2C_MM_ERR_CODE_ENABLE_RD_DAT_POISON_ERR_MASK, - GLBL_ERR_STAT_ERR_H2C_MM_0_MASK, - &eqdma_mm_h2c0_err_process - }, - { - EQDMA_MM_H2C0_RD_RQ_DIS_ERR, - "MM H2C0 Read request disable Error", - EQDMA_H2C_MM_ERR_CODE_ENABLE_MASK_ADDR, - EQDMA_H2C_MM_STATUS_ADDR, - H2C_MM_ERR_CODE_ENABLE_RD_RQ_DIS_ERR_MASK, - GLBL_ERR_STAT_ERR_H2C_MM_0_MASK, - &eqdma_mm_h2c0_err_process - }, - { - EQDMA_MM_H2C0_WR_DEC_ERR, - "MM H2C0 Write desc Error", - EQDMA_H2C_MM_ERR_CODE_ENABLE_MASK_ADDR, - EQDMA_H2C_MM_STATUS_ADDR, - H2C_MM_ERR_CODE_ENABLE_WR_DEC_ERR_MASK, - GLBL_ERR_STAT_ERR_H2C_MM_0_MASK, - &eqdma_mm_h2c0_err_process - }, - { - EQDMA_MM_H2C0_WR_SLV_ERR, - "MM H2C0 Write slv Error", - EQDMA_H2C_MM_ERR_CODE_ENABLE_MASK_ADDR, - EQDMA_H2C_MM_STATUS_ADDR, - H2C_MM_ERR_CODE_ENABLE_WR_SLV_ERR_MASK, - GLBL_ERR_STAT_ERR_H2C_MM_0_MASK, - &eqdma_mm_h2c0_err_process - }, - { - EQDMA_MM_H2C0_ERR_ALL, - "All MM H2C Errors", - EQDMA_H2C_MM_ERR_CODE_ENABLE_MASK_ADDR, - EQDMA_H2C_MM_STATUS_ADDR, - EQDMA_MM_H2C0_ERR_ALL_MASK, - GLBL_ERR_STAT_ERR_H2C_MM_0_MASK, - &eqdma_mm_h2c0_err_process - }, - -}; - -static int32_t all_eqdma_hw_errs[EQDMA_TOTAL_LEAF_ERROR_AGGREGATORS] = { - - EQDMA_DSC_ERR_ALL, - EQDMA_TRQ_ERR_ALL, - EQDMA_ST_C2H_ERR_ALL, - EQDMA_ST_FATAL_ERR_ALL, - EQDMA_ST_H2C_ERR_ALL, - EQDMA_SBE_1_ERR_ALL, - EQDMA_SBE_ERR_ALL, - EQDMA_DBE_1_ERR_ALL, - EQDMA_DBE_ERR_ALL, - EQDMA_MM_C2H_ERR_ALL, - EQDMA_MM_H2C0_ERR_ALL -}; - -static struct qctx_entry eqdma_sw_ctxt_entries[] = { - {"PIDX", 0}, - {"IRQ Arm", 0}, - {"Function Id", 0}, - {"Queue Enable", 0}, - {"Fetch Credit Enable", 0}, - {"Write back/Intr Check", 0}, - {"Write back/Intr Interval", 0}, - {"Address Translation", 0}, - {"Fetch Max", 0}, - {"Ring Size", 0}, - {"Descriptor Size", 0}, - {"Bypass Enable", 0}, - {"MM Channel", 0}, - {"Writeback Enable", 0}, - {"Interrupt Enable", 0}, - {"Port Id", 0}, - {"Interrupt No Last", 0}, - {"Error", 0}, - {"Writeback Error Sent", 0}, - {"IRQ Request", 0}, - {"Marker Disable", 0}, - {"Is Memory Mapped", 0}, - {"Descriptor Ring Base Addr (Low)", 0}, - {"Descriptor Ring Base Addr (High)", 0}, - {"Interrupt Vector/Ring Index", 0}, - {"Interrupt Aggregation", 0}, - {"Disable Interrupt with VF", 0}, - {"Pack descriptor output interface", 0}, - {"Irq Bypass", 0}, -}; - -static struct qctx_entry eqdma_hw_ctxt_entries[] = { - {"CIDX", 0}, - {"Credits Consumed", 0}, - {"Descriptors Pending", 0}, - {"Queue Invalid No Desc Pending", 0}, - {"Eviction Pending", 0}, - {"Fetch Pending", 0}, -}; - -static struct qctx_entry eqdma_credit_ctxt_entries[] = { - {"Credit", 0}, -}; - -static struct qctx_entry eqdma_fmap_ctxt_entries[] = { - {"Queue Base", 0}, - {"Queue Max", 0}, -}; - -static struct qctx_entry eqdma_cmpt_ctxt_entries[] = { - {"Enable Status Desc Update", 0}, - {"Enable Interrupt", 0}, - {"Trigger Mode", 0}, - {"Function Id", 0}, - {"Counter Index", 0}, - {"Timer Index", 0}, - {"Interrupt State", 0}, - {"Color", 0}, - {"Ring Size", 0}, - {"Base Addr High (L)[37:6]", 0}, - {"Base Addr High(H)[63:38]", 0}, - {"Descriptor Size", 0}, - {"PIDX", 0}, - {"CIDX", 0}, - {"Valid", 0}, - {"Error", 0}, - {"Trigger Pending", 0}, - {"Timer Running", 0}, - {"Full Update", 0}, - {"Over Flow Check Disable", 0}, - {"Address Translation", 0}, - {"Interrupt Vector/Ring Index", 0}, - {"Interrupt Aggregation", 0}, - {"Disable Insterrupt with VF", 0}, - {"c2h Direction", 0}, - {"Base Addr Low[5:2]", 0}, - {"Shared Completion Queue", 0}, -}; - -static struct qctx_entry eqdma_c2h_pftch_ctxt_entries[] = { - {"Bypass", 0}, - {"Buffer Size Index", 0}, - {"Port Id", 0}, - {"Variable Descriptor", 0}, - {"Number of descriptors prefetched", 0}, - {"Error", 0}, - {"Prefetch Enable", 0}, - {"In Prefetch", 0}, - {"Software Credit", 0}, - {"Valid", 0}, -}; - -static struct qctx_entry eqdma_ind_intr_ctxt_entries[] = { - {"valid", 0}, - {"vec", 0}, - {"int_st", 0}, - {"color", 0}, - {"baddr_4k (Low)", 0}, - {"baddr_4k (High)", 0}, - {"page_size", 0}, - {"pidx", 0}, - {"at", 0}, - {"Function Id", 0}, -}; - -static int eqdma_indirect_reg_invalidate(void *dev_hndl, - enum ind_ctxt_cmd_sel sel, uint16_t hw_qid); -static int eqdma_indirect_reg_clear(void *dev_hndl, - enum ind_ctxt_cmd_sel sel, uint16_t hw_qid); -static int eqdma_indirect_reg_read(void *dev_hndl, enum ind_ctxt_cmd_sel sel, - uint16_t hw_qid, uint32_t cnt, uint32_t *data); -static int eqdma_indirect_reg_write(void *dev_hndl, enum ind_ctxt_cmd_sel sel, - uint16_t hw_qid, uint32_t *data, uint16_t cnt); - -uint32_t eqdma_get_config_num_regs(void) -{ - return eqdma_config_num_regs_get(); -} - -struct xreg_info *eqdma_get_config_regs(void) -{ - return eqdma_config_regs_get(); -} - -uint32_t eqdma_reg_dump_buf_len(void) -{ - uint32_t length = (eqdma_config_num_regs_get() + 1) - * REG_DUMP_SIZE_PER_LINE; - return length; -} - -int eqdma_context_buf_len(uint8_t st, - enum qdma_dev_q_type q_type, uint32_t *buflen) -{ - int len = 0; - - if (q_type == QDMA_DEV_Q_TYPE_CMPT) { - len += (((sizeof(eqdma_cmpt_ctxt_entries) / - sizeof(eqdma_cmpt_ctxt_entries[0])) + 1) * - REG_DUMP_SIZE_PER_LINE); - } else { - len += (((sizeof(eqdma_sw_ctxt_entries) / - sizeof(eqdma_sw_ctxt_entries[0])) + 1) * - REG_DUMP_SIZE_PER_LINE); - - len += (((sizeof(eqdma_hw_ctxt_entries) / - sizeof(eqdma_hw_ctxt_entries[0])) + 1) * - REG_DUMP_SIZE_PER_LINE); - - len += (((sizeof(eqdma_credit_ctxt_entries) / - sizeof(eqdma_credit_ctxt_entries[0])) + 1) * - REG_DUMP_SIZE_PER_LINE); - - len += (((sizeof(eqdma_fmap_ctxt_entries) / - sizeof(eqdma_fmap_ctxt_entries[0])) + 1) * - REG_DUMP_SIZE_PER_LINE); - - if (st && (q_type == QDMA_DEV_Q_TYPE_C2H)) { - len += (((sizeof(eqdma_cmpt_ctxt_entries) / - sizeof(eqdma_cmpt_ctxt_entries[0])) + 1) * - REG_DUMP_SIZE_PER_LINE); - - len += (((sizeof(eqdma_c2h_pftch_ctxt_entries) / - sizeof(eqdma_c2h_pftch_ctxt_entries[0])) + 1) * - REG_DUMP_SIZE_PER_LINE); - } - } - - *buflen = len; - return 0; -} - - -static uint32_t eqdma_intr_context_buf_len(void) -{ - uint32_t len = 0; - - len += (((sizeof(eqdma_ind_intr_ctxt_entries) / - sizeof(eqdma_ind_intr_ctxt_entries[0])) + 1) * - REG_DUMP_SIZE_PER_LINE); - return len; -} - - -static void eqdma_set_perf_opt(void *dev_hndl) -{ - uint32_t reg_val = 0, data_th = 0, pfch_cache_dpth = 0; - /**** - * TODO: All the below settings are for QDMA5.0 - * Need to add the QDMA4.0 settings - */ -#define EQDMA_PFTCH_CACHE_DEPTH 64 -#define GLBL_DSC_CFG_RSVD_1_DFLT 0 -#define EQDMA_GLBL_DSC_CFG_C2H_UODSC_LIMIT 5 -#define EQDMA_GLBL_DSC_CFG_H2C_UODSC_LIMIT 8 -#define GLBL_DSC_CFG_UNC_OVR_COR_DFLT 0 -#define GLBL_DSC_CFG_CTXT_FER_DIS_DFLT 0 -#define GLBL_DSC_CFG_RSVD_2_DFLT 0 -#define EQDMA_GLBL_DSC_CFG_MAXFETCH 2 -#define EQDMA_GLBL_DSC_CFG_WB_ACC_INT 5 - - reg_val = - FIELD_SET(GLBL_DSC_CFG_RSVD_1_MASK, GLBL_DSC_CFG_RSVD_1_DFLT) | - FIELD_SET(GLBL_DSC_CFG_C2H_UODSC_LIMIT_MASK, - EQDMA_GLBL_DSC_CFG_C2H_UODSC_LIMIT) | - FIELD_SET(GLBL_DSC_CFG_H2C_UODSC_LIMIT_MASK, - EQDMA_GLBL_DSC_CFG_H2C_UODSC_LIMIT) | - FIELD_SET(GLBL_DSC_CFG_UNC_OVR_COR_MASK, - GLBL_DSC_CFG_UNC_OVR_COR_DFLT) | - FIELD_SET(GLBL_DSC_CFG_CTXT_FER_DIS_MASK, - GLBL_DSC_CFG_CTXT_FER_DIS_DFLT) | - FIELD_SET(GLBL_DSC_CFG_RSVD_2_MASK, GLBL_DSC_CFG_RSVD_2_DFLT) | - FIELD_SET(GLBL_DSC_CFG_MAXFETCH_MASK, - EQDMA_GLBL_DSC_CFG_MAXFETCH) | - FIELD_SET(GLBL_DSC_CFG_WB_ACC_INT_MASK, - EQDMA_GLBL_DSC_CFG_WB_ACC_INT); - qdma_reg_write(dev_hndl, EQDMA_GLBL_DSC_CFG_ADDR, reg_val); - reg_val = qdma_reg_read(dev_hndl, EQDMA_GLBL_DSC_CFG_ADDR); - qdma_log_info("%s: reg = 0x%08X val = 0x%08X\n", - __func__, EQDMA_GLBL_DSC_CFG_ADDR, reg_val); - -#define CFG_BLK_MISC_CTL_RSVD_1_DFLT 0 -#define CFG_BLK_MISC_CTL_10B_TAG_DFLT 0 -#define CFG_BLK_MISC_CTL_RSVD_2_DFLT 0 -#define CFG_BLK_MISC_CTL_AXI_WBK_DFLT 0 -#define CFG_BLK_MISC_CTL_AXI_DSC_DFLT 0 -#define CFG_BLK_MISC_CTL_NUM_TAG_DFLT 256 -#define CFG_BLK_MISC_CTL_RSVD_3_DFLT 0 -#define EQDMA_CFG_BLK_MISC_CTL_RQ_METERING_MUL 9 - - - reg_val = - FIELD_SET(CFG_BLK_MISC_CTL_RSVD_1_MASK, - CFG_BLK_MISC_CTL_RSVD_1_DFLT) | - FIELD_SET(CFG_BLK_MISC_CTL_10B_TAG_EN_MASK, - CFG_BLK_MISC_CTL_10B_TAG_DFLT) | - FIELD_SET(CFG_BLK_MISC_CTL_RSVD_2_MASK, - CFG_BLK_MISC_CTL_RSVD_2_DFLT) | - FIELD_SET(CFG_BLK_MISC_CTL_AXI_WBK_MASK, - CFG_BLK_MISC_CTL_AXI_WBK_DFLT) | - FIELD_SET(CFG_BLK_MISC_CTL_AXI_DSC_MASK, - CFG_BLK_MISC_CTL_AXI_DSC_DFLT) | - FIELD_SET(CFG_BLK_MISC_CTL_NUM_TAG_MASK, - CFG_BLK_MISC_CTL_NUM_TAG_DFLT) | - FIELD_SET(CFG_BLK_MISC_CTL_RSVD_3_MASK, - CFG_BLK_MISC_CTL_RSVD_3_DFLT) | - FIELD_SET(CFG_BLK_MISC_CTL_RQ_METERING_MULTIPLIER_MASK, - EQDMA_CFG_BLK_MISC_CTL_RQ_METERING_MUL); - qdma_reg_write(dev_hndl, EQDMA_CFG_BLK_MISC_CTL_ADDR, reg_val); - reg_val = qdma_reg_read(dev_hndl, EQDMA_CFG_BLK_MISC_CTL_ADDR); - qdma_log_info("%s: reg = 0x%08X val = 0x%08X\n", - __func__, EQDMA_CFG_BLK_MISC_CTL_ADDR, reg_val); - -#define EQDMA_PFTCH_CFG_EVT_PFTH_FL_TH 256 -#define C2H_PFCH_CFG_FL_TH_DFLT 256 - - reg_val = - FIELD_SET(C2H_PFCH_CFG_EVTFL_TH_MASK, - EQDMA_PFTCH_CFG_EVT_PFTH_FL_TH) | - FIELD_SET(C2H_PFCH_CFG_FL_TH_MASK, C2H_PFCH_CFG_FL_TH_DFLT); - - qdma_reg_write(dev_hndl, EQDMA_C2H_PFCH_CFG_ADDR, reg_val); - reg_val = qdma_reg_read(dev_hndl, EQDMA_C2H_PFCH_CFG_ADDR); - qdma_log_info("%s: reg = 0x%08X val = 0x%08X\n", - __func__, EQDMA_C2H_PFCH_CFG_ADDR, reg_val); - -#define EQDMA_C2H_PFCH_CFG_1_QCNT_MASK (EQDMA_PFTCH_CACHE_DEPTH - 4) -#define EQDMA_C2H_PFCH_CFG_1_EVNT_QCNT_TH EQDMA_C2H_PFCH_CFG_1_QCNT_MASK - pfch_cache_dpth = qdma_reg_read(dev_hndl, - EQDMA_C2H_PFCH_CACHE_DEPTH_ADDR); - - reg_val = - FIELD_SET(C2H_PFCH_CFG_1_EVT_QCNT_TH_MASK, - (pfch_cache_dpth - 4)) | - FIELD_SET(C2H_PFCH_CFG_1_QCNT_MASK, (pfch_cache_dpth - 4)); - qdma_reg_write(dev_hndl, EQDMA_C2H_PFCH_CFG_1_ADDR, reg_val); - reg_val = qdma_reg_read(dev_hndl, EQDMA_C2H_PFCH_CFG_1_ADDR); - qdma_log_info("%s: reg = 0x%08X val = 0x%08X\n", - __func__, EQDMA_C2H_PFCH_CFG_1_ADDR, reg_val); - -#define EQDMA_C2H_PFCH_CFG_2_FENCE_EN 1 -#define C2H_PFCH_CFG_2_RSVD_DFLT 0 -#define C2H_PFCH_CFG_2_VAR_DESC_NO_DROP_DFLT 0 -#define C2H_PFCH_CFG_2_LL_SZ_TH_DFLT 1024 -#define C2H_PFCH_CFG_2_VAR_DESC_NUM 15 -#define C2H_PFCH_CFG_2_NUM_DFLT 8 - - reg_val = - FIELD_SET(C2H_PFCH_CFG_2_FENCE_MASK, - EQDMA_C2H_PFCH_CFG_2_FENCE_EN) | - FIELD_SET(C2H_PFCH_CFG_2_RSVD_MASK, C2H_PFCH_CFG_2_RSVD_DFLT) | - FIELD_SET(C2H_PFCH_CFG_2_VAR_DESC_NO_DROP_MASK, - C2H_PFCH_CFG_2_VAR_DESC_NO_DROP_DFLT) | - FIELD_SET(C2H_PFCH_CFG_2_LL_SZ_TH_MASK, - C2H_PFCH_CFG_2_LL_SZ_TH_DFLT) | - FIELD_SET(C2H_PFCH_CFG_2_VAR_DESC_NUM_MASK, - C2H_PFCH_CFG_2_VAR_DESC_NUM) | - FIELD_SET(C2H_PFCH_CFG_2_NUM_MASK, C2H_PFCH_CFG_2_NUM_DFLT); - qdma_reg_write(dev_hndl, EQDMA_C2H_PFCH_CFG_2_ADDR, reg_val); - reg_val = qdma_reg_read(dev_hndl, EQDMA_C2H_PFCH_CFG_2_ADDR); - qdma_log_info("%s: reg = 0x%08X val = 0x%08X\n", - __func__, EQDMA_C2H_PFCH_CFG_2_ADDR, reg_val); -#define PFCH_CFG_3_RSVD_DFLT 0 -#define PFCH_CFG_3_VAR_DESC_FL_FREE_CNT_TH_DFLT 256 -#define PFCH_CFG_3_VAR_DESC_LG_PKT_CAM_CN_TH_DFLT 0 - - - reg_val = - FIELD_SET(PFCH_CFG_3_RSVD_MASK, PFCH_CFG_3_RSVD_DFLT) | - FIELD_SET(PFCH_CFG_3_VAR_DESC_FL_FREE_CNT_TH_MASK, - PFCH_CFG_3_VAR_DESC_FL_FREE_CNT_TH_DFLT) | - FIELD_SET(PFCH_CFG_3_VAR_DESC_LG_PKT_CAM_CN_TH_MASK, - PFCH_CFG_3_VAR_DESC_LG_PKT_CAM_CN_TH_DFLT); - qdma_reg_write(dev_hndl, EQDMA_PFCH_CFG_3_ADDR, reg_val); - reg_val = qdma_reg_read(dev_hndl, EQDMA_PFCH_CFG_3_ADDR); - qdma_log_info("%s: reg = 0x%08X val = 0x%08X\n", - __func__, EQDMA_C2H_PFCH_CFG_2_ADDR, reg_val); -#define EQDMA_PFCH_CFG_4_GLB_EVT_TIMER_TICK 64 -#define PFCH_CFG_4_DISABLE_GLB_EVT_TIMER_DFLT 0 -#define EQDMA_PFCH_CFG_4_EVT_TIMER_TICK 400 -#define PFCH_CFG_4_DISABLE_EVT_TIMER_DFLT 0 - - - reg_val = - FIELD_SET(PFCH_CFG_4_GLB_EVT_TIMER_TICK_MASK, - EQDMA_PFCH_CFG_4_GLB_EVT_TIMER_TICK) | - FIELD_SET(PFCH_CFG_4_DISABLE_GLB_EVT_TIMER_MASK, - PFCH_CFG_4_DISABLE_GLB_EVT_TIMER_DFLT) | - FIELD_SET(PFCH_CFG_4_EVT_TIMER_TICK_MASK, - EQDMA_PFCH_CFG_4_EVT_TIMER_TICK) | - FIELD_SET(PFCH_CFG_4_DISABLE_EVT_TIMER_MASK, - PFCH_CFG_4_DISABLE_EVT_TIMER_DFLT); - qdma_reg_write(dev_hndl, EQDMA_PFCH_CFG_4_ADDR, reg_val); - reg_val = qdma_reg_read(dev_hndl, EQDMA_PFCH_CFG_4_ADDR); - qdma_log_info("%s: reg = 0x%08X val = 0x%08X\n", - __func__, EQDMA_PFCH_CFG_4_ADDR, reg_val); -/**************** SET_2 *******************/ -#define C2H_CRDT_COAL_CFG_1_RSVD_1_DFLT 0 -#define C2H_CRDT_COAL_CFG_1_PLD_FIFO_TH_DFLT 16 -#define EQDMA_C2H_CRDT_COAL_CFG_1_TIMER_TH 16 //64 - - - reg_val = - FIELD_SET(C2H_CRDT_COAL_CFG_1_RSVD_1_MASK, - C2H_CRDT_COAL_CFG_1_RSVD_1_DFLT) | - FIELD_SET(C2H_CRDT_COAL_CFG_1_PLD_FIFO_TH_MASK, - C2H_CRDT_COAL_CFG_1_PLD_FIFO_TH_DFLT) | - FIELD_SET(C2H_CRDT_COAL_CFG_1_TIMER_TH_MASK, - EQDMA_C2H_CRDT_COAL_CFG_1_TIMER_TH); - qdma_reg_write(dev_hndl, EQDMA_C2H_CRDT_COAL_CFG_1_ADDR, reg_val); - reg_val = qdma_reg_read(dev_hndl, EQDMA_C2H_CRDT_COAL_CFG_1_ADDR); - qdma_log_info("%s: reg = 0x%08X val = 0x%08X\n", - __func__, EQDMA_C2H_CRDT_COAL_CFG_1_ADDR, reg_val); -#define C2H_CRDT_COAL_CFG_2_RSVD_1_DFLT 0 -#define EQDMA_C2H_CRDT_COAL_CFG_2_FIFO_TH (EQDMA_PFTCH_CACHE_DEPTH - 8) -#define C2H_CRDT_COAL_CFG_2_RESERVED1_DFLT 0 -#define EQDMA_C2H_CRDT_COAL_CFG_2_CRDT_TH 96 - - reg_val = - FIELD_SET(C2H_CRDT_COAL_CFG_2_RSVD_1_MASK, - C2H_CRDT_COAL_CFG_2_RSVD_1_DFLT) | - FIELD_SET(C2H_CRDT_COAL_CFG_2_FIFO_TH_MASK, - (pfch_cache_dpth - 8)) | - FIELD_SET(C2H_CRDT_COAL_CFG_2_RESERVED1_MASK, - C2H_CRDT_COAL_CFG_2_RESERVED1_DFLT) | - FIELD_SET(C2H_CRDT_COAL_CFG_2_NT_TH_MASK, - EQDMA_C2H_CRDT_COAL_CFG_2_CRDT_TH); - qdma_reg_write(dev_hndl, EQDMA_C2H_CRDT_COAL_CFG_2_ADDR, reg_val); - reg_val = qdma_reg_read(dev_hndl, EQDMA_C2H_CRDT_COAL_CFG_2_ADDR); - qdma_log_info("%s: reg = 0x%08X val = 0x%08X\n", - __func__, EQDMA_C2H_CRDT_COAL_CFG_2_ADDR, reg_val); - -/**************** SET_3 *******************/ -#define EQDMA_GLBL2_RRQ_PCIE_THROT_REQ_EN 0 -#define GLBL2_RRQ_PCIE_THROT_REQ_DFLT 192 -#define GLBL2_RRQ_PCIE_THROT_DAT_EN_DFLT 1 -#define GLBL2_RRQ_PCIE_THROT_DAT_DFLT 20480 - - - reg_val = - FIELD_SET(GLBL2_RRQ_PCIE_THROT_REQ_EN_MASK, - EQDMA_GLBL2_RRQ_PCIE_THROT_REQ_EN) | - FIELD_SET(GLBL2_RRQ_PCIE_THROT_REQ_MASK, - GLBL2_RRQ_PCIE_THROT_REQ_DFLT) | - FIELD_SET(GLBL2_RRQ_PCIE_THROT_DAT_EN_MASK, - GLBL2_RRQ_PCIE_THROT_DAT_EN_DFLT) | - FIELD_SET(GLBL2_RRQ_PCIE_THROT_DAT_MASK, - GLBL2_RRQ_PCIE_THROT_DAT_DFLT); - qdma_reg_write(dev_hndl, EQDMA_GLBL2_RRQ_PCIE_THROT_ADDR, reg_val); - reg_val = qdma_reg_read(dev_hndl, EQDMA_GLBL2_RRQ_PCIE_THROT_ADDR); - qdma_log_info("%s: reg = 0x%08X val = 0x%08X\n", - __func__, EQDMA_GLBL2_RRQ_PCIE_THROT_ADDR, reg_val); -#define GLBL2_RRQ_AXIMM_THROT_REQ_EN_DFLT 0 -#define GLBL2_RRQ_AXIMM_THROT_REQ_DFLT 0 -#define GLBL2_RRQ_AXIMM_THROT_DAT_EN_DFLT 0 -#define GLBL2_RRQ_AXIMM_THROT_DAT_DFLT 0 - - reg_val = - FIELD_SET(GLBL2_RRQ_AXIMM_THROT_REQ_EN_MASK, - GLBL2_RRQ_AXIMM_THROT_REQ_EN_DFLT) | - FIELD_SET(GLBL2_RRQ_AXIMM_THROT_REQ_MASK, - GLBL2_RRQ_AXIMM_THROT_REQ_DFLT) | - FIELD_SET(GLBL2_RRQ_AXIMM_THROT_DAT_EN_MASK, - GLBL2_RRQ_AXIMM_THROT_DAT_EN_DFLT) | - FIELD_SET(GLBL2_RRQ_AXIMM_THROT_DAT_MASK, - GLBL2_RRQ_AXIMM_THROT_DAT_DFLT); - qdma_reg_write(dev_hndl, EQDMA_GLBL2_RRQ_AXIMM_THROT_ADDR, reg_val); - reg_val = qdma_reg_read(dev_hndl, EQDMA_GLBL2_RRQ_AXIMM_THROT_ADDR); - qdma_log_info("%s: reg = 0x%08X val = 0x%08X\n", - __func__, EQDMA_GLBL2_RRQ_AXIMM_THROT_ADDR, reg_val); -#define GLBL2_RRQ_BRG_THROT_REQ_EN_DFLT 1 -#define GLBL2_RRQ_BRG_THROT_REQ_DFLT GLBL2_RRQ_PCIE_THROT_REQ_DFLT -#define GLBL2_RRQ_BRG_THROT_DAT_EN_DFLT 1 - - - reg_val = qdma_reg_read(dev_hndl, EQDMA_GLBL2_RRQ_PCIE_THROT_ADDR); - qdma_log_info("%s: BF reg = 0x%08X val = 0x%08X\n", - __func__, EQDMA_GLBL2_RRQ_PCIE_THROT_ADDR, reg_val); - data_th = FIELD_GET(GLBL2_RRQ_PCIE_THROT_DAT_MASK, reg_val); - - reg_val = - FIELD_SET(GLBL2_RRQ_BRG_THROT_REQ_EN_MASK, - GLBL2_RRQ_BRG_THROT_REQ_EN_DFLT) | - FIELD_SET(GLBL2_RRQ_BRG_THROT_REQ_MASK, - GLBL2_RRQ_BRG_THROT_REQ_DFLT) | - FIELD_SET(GLBL2_RRQ_BRG_THROT_DAT_EN_MASK, - GLBL2_RRQ_BRG_THROT_DAT_EN_DFLT) | - FIELD_SET(GLBL2_RRQ_BRG_THROT_DAT_MASK, data_th); - qdma_reg_write(dev_hndl, EQDMA_GLBL2_RRQ_BRG_THROT_ADDR, reg_val); - reg_val = qdma_reg_read(dev_hndl, EQDMA_GLBL2_RRQ_BRG_THROT_ADDR); - qdma_log_info("%s: reg = 0x%08X val = 0x%08X\n", - __func__, EQDMA_GLBL2_RRQ_BRG_THROT_ADDR, reg_val); - -/******************* SET_4 *************************/ -#define EQDMA_H2C_REQ_THROT_PCIE_EN_REQ 1 -#define EQDMA_H2C_REQ_THROT_PCIE_REQ_TH GLBL2_RRQ_PCIE_THROT_REQ_DFLT -#define EQDMA_H2C_REQ_THROT_PCIE_EN_DATA 1 -#define EQDMA_H2C_REQ_THROT_PCIE_DATA_TH 24576 - - reg_val = - FIELD_SET(H2C_REQ_THROT_PCIE_EN_REQ_MASK, - EQDMA_H2C_REQ_THROT_PCIE_EN_REQ) | - FIELD_SET(H2C_REQ_THROT_PCIE_MASK, - EQDMA_H2C_REQ_THROT_PCIE_REQ_TH) | - FIELD_SET(H2C_REQ_THROT_PCIE_EN_DATA_MASK, - EQDMA_H2C_REQ_THROT_PCIE_EN_DATA) | - FIELD_SET(H2C_REQ_THROT_PCIE_DATA_THRESH_MASK, - EQDMA_H2C_REQ_THROT_PCIE_DATA_TH); - qdma_reg_write(dev_hndl, EQDMA_H2C_REQ_THROT_PCIE_ADDR, reg_val); - reg_val = qdma_reg_read(dev_hndl, EQDMA_H2C_REQ_THROT_PCIE_ADDR); - qdma_log_info("%s: reg = 0x%08X val = 0x%08X\n", - __func__, EQDMA_H2C_REQ_THROT_PCIE_ADDR, reg_val); -#define EQDMA_H2C_REQ_THROT_AXIMM_EN_REQ 1 -#define EQDMA_H2C_REQ_THROT_AXIMM_REQ_TH 64 -#define EQDMA_H2C_REQ_THROT_AXIMM_EN_DATA 1 -#define EQDMA_H2C_REQ_THROT_AXIMM_DATA_TH 16384 - - reg_val = - FIELD_SET(H2C_REQ_THROT_AXIMM_EN_REQ_MASK, - EQDMA_H2C_REQ_THROT_AXIMM_EN_REQ) | - FIELD_SET(H2C_REQ_THROT_AXIMM_MASK, - EQDMA_H2C_REQ_THROT_AXIMM_REQ_TH) | - FIELD_SET(H2C_REQ_THROT_AXIMM_EN_DATA_MASK, - EQDMA_H2C_REQ_THROT_AXIMM_EN_DATA) | - FIELD_SET(H2C_REQ_THROT_AXIMM_DATA_THRESH_MASK, - EQDMA_H2C_REQ_THROT_AXIMM_DATA_TH); - qdma_reg_write(dev_hndl, EQDMA_H2C_REQ_THROT_AXIMM_ADDR, reg_val); - reg_val = qdma_reg_read(dev_hndl, EQDMA_H2C_REQ_THROT_AXIMM_ADDR); - qdma_log_info("%s: reg = 0x%08X val = 0x%08X\n", - __func__, EQDMA_H2C_REQ_THROT_AXIMM_ADDR, reg_val); - -#define H2C_MM_DATA_THROTTLE_RSVD_1_DFLT 0 -#define EQDMA_H2C_MM_DATA_TH_EN GLBL2_RRQ_PCIE_THROT_DAT_EN_DFLT -#define EQDMA_H2C_MM_DATA_TH GLBL2_RRQ_PCIE_THROT_DAT_DFLT - - reg_val = - FIELD_SET(H2C_MM_DATA_THROTTLE_RSVD_1_MASK, - H2C_MM_DATA_THROTTLE_RSVD_1_DFLT) | - FIELD_SET(H2C_MM_DATA_THROTTLE_DAT_EN_MASK, - EQDMA_H2C_MM_DATA_TH_EN) | - FIELD_SET(H2C_MM_DATA_THROTTLE_DAT_MASK, EQDMA_H2C_MM_DATA_TH); - qdma_reg_write(dev_hndl, EQDMA_H2C_MM_DATA_THROTTLE_ADDR, reg_val); - reg_val = qdma_reg_read(dev_hndl, EQDMA_H2C_MM_DATA_THROTTLE_ADDR); - qdma_log_info("%s: reg = 0x%08X val = 0x%08X\n", - __func__, EQDMA_H2C_MM_DATA_THROTTLE_ADDR, reg_val); - -} - - -/* - * eqdma_indirect_reg_invalidate() - helper function to invalidate indirect - * context registers. - * - * return -QDMA_ERR_HWACC_BUSY_TIMEOUT if register - * value didn't match, QDMA_SUCCESS other wise - */ -static int eqdma_indirect_reg_invalidate(void *dev_hndl, - enum ind_ctxt_cmd_sel sel, uint16_t hw_qid) -{ - union qdma_ind_ctxt_cmd cmd; - - qdma_reg_access_lock(dev_hndl); - - /* set command register */ - cmd.word = 0; - cmd.bits.qid = hw_qid; - cmd.bits.op = QDMA_CTXT_CMD_INV; - cmd.bits.sel = sel; - qdma_reg_write(dev_hndl, EQDMA_IND_CTXT_CMD_ADDR, cmd.word); - - /* check if the operation went through well */ - if (hw_monitor_reg(dev_hndl, EQDMA_IND_CTXT_CMD_ADDR, - IND_CTXT_CMD_BUSY_MASK, 0, - QDMA_REG_POLL_DFLT_INTERVAL_US, - QDMA_REG_POLL_DFLT_TIMEOUT_US)) { - qdma_reg_access_release(dev_hndl); - qdma_log_error("%s: hw_monitor_reg failed with err:%d\n", - __func__, - -QDMA_ERR_HWACC_BUSY_TIMEOUT); - return -QDMA_ERR_HWACC_BUSY_TIMEOUT; - } - - qdma_reg_access_release(dev_hndl); - - return QDMA_SUCCESS; -} - -/* - * eqdma_indirect_reg_clear() - helper function to clear indirect - * context registers. - * - * return -QDMA_ERR_HWACC_BUSY_TIMEOUT if register - * value didn't match, QDMA_SUCCESS other wise - */ -static int eqdma_indirect_reg_clear(void *dev_hndl, - enum ind_ctxt_cmd_sel sel, uint16_t hw_qid) -{ - union qdma_ind_ctxt_cmd cmd; - - qdma_reg_access_lock(dev_hndl); - - /* set command register */ - cmd.word = 0; - cmd.bits.qid = hw_qid; - cmd.bits.op = QDMA_CTXT_CMD_CLR; - cmd.bits.sel = sel; - qdma_reg_write(dev_hndl, EQDMA_IND_CTXT_CMD_ADDR, cmd.word); - - /* check if the operation went through well */ - if (hw_monitor_reg(dev_hndl, EQDMA_IND_CTXT_CMD_ADDR, - IND_CTXT_CMD_BUSY_MASK, 0, - QDMA_REG_POLL_DFLT_INTERVAL_US, - QDMA_REG_POLL_DFLT_TIMEOUT_US)) { - qdma_reg_access_release(dev_hndl); - qdma_log_error("%s: hw_monitor_reg failed with err:%d\n", - __func__, - -QDMA_ERR_HWACC_BUSY_TIMEOUT); - return -QDMA_ERR_HWACC_BUSY_TIMEOUT; - } - - qdma_reg_access_release(dev_hndl); - - return QDMA_SUCCESS; -} - -/* - * eqdma_indirect_reg_read() - helper function to read indirect - * context registers. - * - * return -QDMA_ERR_HWACC_BUSY_TIMEOUT if register - * value didn't match, QDMA_SUCCESS other wise - */ -static int eqdma_indirect_reg_read(void *dev_hndl, enum ind_ctxt_cmd_sel sel, - uint16_t hw_qid, uint32_t cnt, uint32_t *data) -{ - uint32_t index = 0, reg_addr = EQDMA_IND_CTXT_DATA_ADDR; - union qdma_ind_ctxt_cmd cmd; - - qdma_reg_access_lock(dev_hndl); - - /* set command register */ - cmd.word = 0; - cmd.bits.qid = hw_qid; - cmd.bits.op = QDMA_CTXT_CMD_RD; - cmd.bits.sel = sel; - - qdma_reg_write(dev_hndl, EQDMA_IND_CTXT_CMD_ADDR, cmd.word); - - /* check if the operation went through well */ - if (hw_monitor_reg(dev_hndl, EQDMA_IND_CTXT_CMD_ADDR, - IND_CTXT_CMD_BUSY_MASK, 0, - QDMA_REG_POLL_DFLT_INTERVAL_US, - QDMA_REG_POLL_DFLT_TIMEOUT_US)) { - qdma_reg_access_release(dev_hndl); - qdma_log_error("%s: hw_monitor_reg failed with err:%d\n", - __func__, - -QDMA_ERR_HWACC_BUSY_TIMEOUT); - return -QDMA_ERR_HWACC_BUSY_TIMEOUT; - } - - for (index = 0; index < cnt; index++, reg_addr += sizeof(uint32_t)) - data[index] = qdma_reg_read(dev_hndl, reg_addr); - - qdma_reg_access_release(dev_hndl); - - return QDMA_SUCCESS; -} - -/* - * eqdma_indirect_reg_write() - helper function to write indirect - * context registers. - * - * return -QDMA_ERR_HWACC_BUSY_TIMEOUT if register - * value didn't match, QDMA_SUCCESS other wise - */ -static int eqdma_indirect_reg_write(void *dev_hndl, enum ind_ctxt_cmd_sel sel, - uint16_t hw_qid, uint32_t *data, uint16_t cnt) -{ - uint32_t index, reg_addr; - struct qdma_indirect_ctxt_regs regs; - uint32_t *wr_data = (uint32_t *)®s; - - qdma_reg_access_lock(dev_hndl); - - /* write the context data */ - for (index = 0; index < QDMA_IND_CTXT_DATA_NUM_REGS; index++) { - if (index < cnt) - regs.qdma_ind_ctxt_data[index] = data[index]; - else - regs.qdma_ind_ctxt_data[index] = 0; - regs.qdma_ind_ctxt_mask[index] = 0xFFFFFFFF; - } - - regs.cmd.word = 0; - regs.cmd.bits.qid = hw_qid; - regs.cmd.bits.op = QDMA_CTXT_CMD_WR; - regs.cmd.bits.sel = sel; - reg_addr = EQDMA_IND_CTXT_DATA_ADDR; - - for (index = 0; index < ((2 * QDMA_IND_CTXT_DATA_NUM_REGS) + 1); - index++, reg_addr += sizeof(uint32_t)) - qdma_reg_write(dev_hndl, reg_addr, wr_data[index]); - - /* check if the operation went through well */ - if (hw_monitor_reg(dev_hndl, EQDMA_IND_CTXT_CMD_ADDR, - IND_CTXT_CMD_BUSY_MASK, 0, - QDMA_REG_POLL_DFLT_INTERVAL_US, - QDMA_REG_POLL_DFLT_TIMEOUT_US)) { - qdma_reg_access_release(dev_hndl); - qdma_log_error("%s: hw_monitor_reg failed with err:%d\n", - __func__, - -QDMA_ERR_HWACC_BUSY_TIMEOUT); - return -QDMA_ERR_HWACC_BUSY_TIMEOUT; - } - - qdma_reg_access_release(dev_hndl); - - return QDMA_SUCCESS; -} - -int eqdma_get_ip_version(void *dev_hndl, uint8_t is_vf, - uint32_t *ip_version) -{ - uint32_t ver_reg_val = 0; - uint32_t reg_addr = (is_vf) ? EQDMA_OFFSET_VF_VERSION : - EQDMA_GLBL2_MISC_CAP_ADDR; - - if (!dev_hndl) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - ver_reg_val = qdma_reg_read(dev_hndl, reg_addr); - - if (!is_vf) { - *ip_version = - FIELD_GET(EQDMA_GLBL2_IP_VERSION_MASK, - ver_reg_val); - } else { - *ip_version = - FIELD_GET(EQDMA_GLBL2_VF_IP_VERSION_MASK, - ver_reg_val); - } - - return QDMA_SUCCESS; -} - -/* - * eqdma_fill_sw_ctxt() - Helper function to fill sw context into structure - * - */ -static void eqdma_fill_sw_ctxt(struct qdma_descq_sw_ctxt *sw_ctxt) -{ - int i = 0; - - eqdma_sw_ctxt_entries[i++].value = sw_ctxt->pidx; - eqdma_sw_ctxt_entries[i++].value = sw_ctxt->irq_arm; - eqdma_sw_ctxt_entries[i++].value = sw_ctxt->fnc_id; - eqdma_sw_ctxt_entries[i++].value = sw_ctxt->qen; - eqdma_sw_ctxt_entries[i++].value = sw_ctxt->frcd_en; - eqdma_sw_ctxt_entries[i++].value = sw_ctxt->wbi_chk; - eqdma_sw_ctxt_entries[i++].value = sw_ctxt->wbi_intvl_en; - eqdma_sw_ctxt_entries[i++].value = sw_ctxt->at; - eqdma_sw_ctxt_entries[i++].value = sw_ctxt->fetch_max; - eqdma_sw_ctxt_entries[i++].value = sw_ctxt->rngsz_idx; - eqdma_sw_ctxt_entries[i++].value = sw_ctxt->desc_sz; - eqdma_sw_ctxt_entries[i++].value = sw_ctxt->bypass; - eqdma_sw_ctxt_entries[i++].value = sw_ctxt->mm_chn; - eqdma_sw_ctxt_entries[i++].value = sw_ctxt->wbk_en; - eqdma_sw_ctxt_entries[i++].value = sw_ctxt->irq_en; - eqdma_sw_ctxt_entries[i++].value = sw_ctxt->port_id; - eqdma_sw_ctxt_entries[i++].value = sw_ctxt->irq_no_last; - eqdma_sw_ctxt_entries[i++].value = sw_ctxt->err; - eqdma_sw_ctxt_entries[i++].value = sw_ctxt->err_wb_sent; - eqdma_sw_ctxt_entries[i++].value = sw_ctxt->irq_req; - eqdma_sw_ctxt_entries[i++].value = sw_ctxt->mrkr_dis; - eqdma_sw_ctxt_entries[i++].value = sw_ctxt->is_mm; - eqdma_sw_ctxt_entries[i++].value = sw_ctxt->ring_bs_addr & 0xFFFFFFFF; - eqdma_sw_ctxt_entries[i++].value = - (sw_ctxt->ring_bs_addr >> 32) & 0xFFFFFFFF; - eqdma_sw_ctxt_entries[i++].value = sw_ctxt->vec; - eqdma_sw_ctxt_entries[i++].value = sw_ctxt->intr_aggr; - eqdma_sw_ctxt_entries[i++].value = sw_ctxt->dis_intr_on_vf; - eqdma_sw_ctxt_entries[i++].value = sw_ctxt->pack_byp_out; - eqdma_sw_ctxt_entries[i++].value = sw_ctxt->irq_byp; - -} - -/* - * eqdma_fill_cmpt_ctxt() - Helper function to fill completion context - * into structure - * - */ -static void eqdma_fill_cmpt_ctxt(struct qdma_descq_cmpt_ctxt *cmpt_ctxt) -{ - int i = 0; - - eqdma_cmpt_ctxt_entries[i++].value = cmpt_ctxt->en_stat_desc; - eqdma_cmpt_ctxt_entries[i++].value = cmpt_ctxt->en_int; - eqdma_cmpt_ctxt_entries[i++].value = cmpt_ctxt->trig_mode; - eqdma_cmpt_ctxt_entries[i++].value = cmpt_ctxt->fnc_id; - eqdma_cmpt_ctxt_entries[i++].value = cmpt_ctxt->counter_idx; - eqdma_cmpt_ctxt_entries[i++].value = cmpt_ctxt->timer_idx; - eqdma_cmpt_ctxt_entries[i++].value = cmpt_ctxt->in_st; - eqdma_cmpt_ctxt_entries[i++].value = cmpt_ctxt->color; - eqdma_cmpt_ctxt_entries[i++].value = cmpt_ctxt->ringsz_idx; - eqdma_cmpt_ctxt_entries[i++].value = (uint32_t)FIELD_GET( - EQDMA_COMPL_CTXT_BADDR_HIGH_L_MASK, - cmpt_ctxt->bs_addr); - eqdma_cmpt_ctxt_entries[i++].value = (uint32_t)FIELD_GET( - EQDMA_COMPL_CTXT_BADDR_HIGH_H_MASK, - cmpt_ctxt->bs_addr); - eqdma_cmpt_ctxt_entries[i++].value = cmpt_ctxt->desc_sz; - eqdma_cmpt_ctxt_entries[i++].value = cmpt_ctxt->pidx; - eqdma_cmpt_ctxt_entries[i++].value = cmpt_ctxt->cidx; - eqdma_cmpt_ctxt_entries[i++].value = cmpt_ctxt->valid; - eqdma_cmpt_ctxt_entries[i++].value = cmpt_ctxt->err; - eqdma_cmpt_ctxt_entries[i++].value = cmpt_ctxt->user_trig_pend; - eqdma_cmpt_ctxt_entries[i++].value = cmpt_ctxt->timer_running; - eqdma_cmpt_ctxt_entries[i++].value = cmpt_ctxt->full_upd; - eqdma_cmpt_ctxt_entries[i++].value = cmpt_ctxt->ovf_chk_dis; - eqdma_cmpt_ctxt_entries[i++].value = cmpt_ctxt->at; - eqdma_cmpt_ctxt_entries[i++].value = cmpt_ctxt->vec; - eqdma_cmpt_ctxt_entries[i++].value = cmpt_ctxt->int_aggr; - eqdma_cmpt_ctxt_entries[i++].value = cmpt_ctxt->dis_intr_on_vf; - eqdma_cmpt_ctxt_entries[i++].value = cmpt_ctxt->dir_c2h; - eqdma_cmpt_ctxt_entries[i++].value = (uint32_t)FIELD_GET( - EQDMA_COMPL_CTXT_BADDR_LOW_MASK, - cmpt_ctxt->bs_addr); - eqdma_cmpt_ctxt_entries[i++].value = cmpt_ctxt->sh_cmpt; -} - -/* - * eqdma_fill_hw_ctxt() - Helper function to fill HW context into structure - * - */ -static void eqdma_fill_hw_ctxt(struct qdma_descq_hw_ctxt *hw_ctxt) -{ - int i = 0; - - eqdma_hw_ctxt_entries[i++].value = hw_ctxt->cidx; - eqdma_hw_ctxt_entries[i++].value = hw_ctxt->crd_use; - eqdma_hw_ctxt_entries[i++].value = hw_ctxt->dsc_pend; - eqdma_hw_ctxt_entries[i++].value = hw_ctxt->idl_stp_b; - eqdma_hw_ctxt_entries[i++].value = hw_ctxt->evt_pnd; - eqdma_hw_ctxt_entries[i++].value = hw_ctxt->fetch_pnd; -} - -/* - * eqdma_fill_credit_ctxt() - Helper function to fill Credit context - * into structure - * - */ -static void eqdma_fill_credit_ctxt(struct qdma_descq_credit_ctxt *cr_ctxt) -{ - eqdma_credit_ctxt_entries[0].value = cr_ctxt->credit; -} - -/* - * eqdma_fill_pfetch_ctxt() - Helper function to fill Prefetch context - * into structure - * - */ -static void eqdma_fill_pfetch_ctxt(struct qdma_descq_prefetch_ctxt - *pfetch_ctxt) -{ - int i = 0; - - eqdma_c2h_pftch_ctxt_entries[i++].value = pfetch_ctxt->bypass; - eqdma_c2h_pftch_ctxt_entries[i++].value = pfetch_ctxt->bufsz_idx; - eqdma_c2h_pftch_ctxt_entries[i++].value = pfetch_ctxt->port_id; - eqdma_c2h_pftch_ctxt_entries[i++].value = pfetch_ctxt->var_desc; - eqdma_c2h_pftch_ctxt_entries[i++].value = pfetch_ctxt->num_pftch; - eqdma_c2h_pftch_ctxt_entries[i++].value = pfetch_ctxt->err; - eqdma_c2h_pftch_ctxt_entries[i++].value = pfetch_ctxt->pfch_en; - eqdma_c2h_pftch_ctxt_entries[i++].value = pfetch_ctxt->pfch; - eqdma_c2h_pftch_ctxt_entries[i++].value = pfetch_ctxt->sw_crdt; - eqdma_c2h_pftch_ctxt_entries[i++].value = pfetch_ctxt->valid; -} - -/* - * eqdma_fill_fmap_ctxt() - Helper function to fill fmap context - * into structure - * - */ -static void eqdma_fill_fmap_ctxt(struct qdma_fmap_cfg *fmap_ctxt) -{ - eqdma_fmap_ctxt_entries[0].value = fmap_ctxt->qbase; - eqdma_fmap_ctxt_entries[1].value = fmap_ctxt->qmax; -} - -/* - * eqdma_fill_intr_ctxt() - Helper function to fill interrupt context - * into structure - * - */ -static void eqdma_fill_intr_ctxt(struct qdma_indirect_intr_ctxt *intr_ctxt) -{ - int i = 0; - - eqdma_ind_intr_ctxt_entries[i++].value = intr_ctxt->valid; - eqdma_ind_intr_ctxt_entries[i++].value = intr_ctxt->vec; - eqdma_ind_intr_ctxt_entries[i++].value = intr_ctxt->int_st; - eqdma_ind_intr_ctxt_entries[i++].value = intr_ctxt->color; - eqdma_ind_intr_ctxt_entries[i++].value = - intr_ctxt->baddr_4k & 0xFFFFFFFF; - eqdma_ind_intr_ctxt_entries[i++].value = - (intr_ctxt->baddr_4k >> 32) & 0xFFFFFFFF; - eqdma_ind_intr_ctxt_entries[i++].value = intr_ctxt->page_size; - eqdma_ind_intr_ctxt_entries[i++].value = intr_ctxt->pidx; - eqdma_ind_intr_ctxt_entries[i++].value = intr_ctxt->at; - eqdma_ind_intr_ctxt_entries[i++].value = intr_ctxt->func_id; -} - -/*****************************************************************************/ -/** - * eqdma_set_default_global_csr() - function to set the global CSR register to - * default values. The value can be modified later by using the set/get csr - * functions - * - * @dev_hndl: device handle - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -int eqdma_set_default_global_csr(void *dev_hndl) -{ - int rv = QDMA_SUCCESS; - - /* Default values */ - uint32_t cfg_val = 0, reg_val = 0; - uint32_t rng_sz[QDMA_NUM_RING_SIZES] = {2049, 65, 129, 193, 257, 385, - 513, 769, 1025, 1537, 3073, 4097, 6145, 8193, 12289, 16385}; - uint32_t tmr_cnt[QDMA_NUM_C2H_TIMERS] = {1, 2, 4, 5, 8, 10, 15, 20, 25, - 30, 50, 75, 100, 125, 150, 200}; - uint32_t cnt_th[QDMA_NUM_C2H_COUNTERS] = {2, 4, 8, 16, 24, 32, 48, 64, - 80, 96, 112, 128, 144, 160, 176, 192}; - uint32_t buf_sz[QDMA_NUM_C2H_BUFFER_SIZES] = {4096, 256, 512, 1024, - 2048, 3968, 4096, 4096, 4096, 4096, 4096, 4096, 4096, 8192, - 9018, 16384}; - struct qdma_dev_attributes dev_cap; - uint32_t eqdma_ip_version; - - if (!dev_hndl) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", __func__, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - eqdma_get_device_attributes(dev_hndl, &dev_cap); - - rv = eqdma_get_ip_version(dev_hndl, 0, &eqdma_ip_version); - if (rv != QDMA_SUCCESS) - return rv; - - /* Configuring CSR registers */ - /* Global ring sizes */ - qdma_write_csr_values(dev_hndl, EQDMA_GLBL_RNG_SZ_1_ADDR, 0, - QDMA_NUM_RING_SIZES, rng_sz); - - if (dev_cap.st_en || dev_cap.mm_cmpt_en) { - /* Counter thresholds */ - qdma_write_csr_values(dev_hndl, EQDMA_C2H_CNT_TH_ADDR, 0, - QDMA_NUM_C2H_COUNTERS, cnt_th); - - /* Timer Counters */ - qdma_write_csr_values(dev_hndl, EQDMA_C2H_TIMER_CNT_ADDR, 0, - QDMA_NUM_C2H_TIMERS, tmr_cnt); - - /* Writeback Interval */ - if (eqdma_ip_version == EQDMA_IP_VERSION_4) { - reg_val = - FIELD_SET(GLBL_DSC_CFG_MAXFETCH_MASK, - DEFAULT_MAX_DSC_FETCH) | - FIELD_SET(GLBL_DSC_CFG_WB_ACC_INT_MASK, - DEFAULT_WRB_INT); - - qdma_reg_write(dev_hndl, EQDMA_GLBL_DSC_CFG_ADDR, - reg_val); - } - } - - if (dev_cap.st_en) { - /* Buffer Sizes */ - qdma_write_csr_values(dev_hndl, EQDMA_C2H_BUF_SZ_ADDR, 0, - QDMA_NUM_C2H_BUFFER_SIZES, buf_sz); - - /* Prefetch Configuration */ - if (eqdma_ip_version == EQDMA_IP_VERSION_4) { - reg_val = qdma_reg_read(dev_hndl, - EQDMA_C2H_PFCH_CACHE_DEPTH_ADDR); - cfg_val = FIELD_GET(C2H_PFCH_CACHE_DEPTH_MASK, reg_val); - reg_val = FIELD_SET(C2H_PFCH_CFG_1_QCNT_MASK, - (cfg_val >> 2)) | - FIELD_SET(C2H_PFCH_CFG_1_EVT_QCNT_TH_MASK, - ((cfg_val >> 2) - 4)); - - qdma_reg_write(dev_hndl, EQDMA_C2H_PFCH_CFG_1_ADDR, - reg_val); - - reg_val = qdma_reg_read(dev_hndl, - EQDMA_C2H_PFCH_CFG_2_ADDR); - reg_val |= FIELD_SET(C2H_PFCH_CFG_2_FENCE_MASK, 1); - qdma_reg_write(dev_hndl, EQDMA_C2H_PFCH_CFG_2_ADDR, - reg_val); - } - - /* C2H interrupt timer tick */ - qdma_reg_write(dev_hndl, EQDMA_C2H_INT_TIMER_TICK_ADDR, - DEFAULT_C2H_INTR_TIMER_TICK); - - /* C2h Completion Coalesce Configuration */ - cfg_val = qdma_reg_read(dev_hndl, - EQDMA_C2H_WRB_COAL_BUF_DEPTH_ADDR); - reg_val = - FIELD_SET(C2H_WRB_COAL_CFG_TICK_CNT_MASK, - DEFAULT_CMPT_COAL_TIMER_CNT) | - FIELD_SET(C2H_WRB_COAL_CFG_TICK_VAL_MASK, - DEFAULT_CMPT_COAL_TIMER_TICK) | - FIELD_SET(C2H_WRB_COAL_CFG_MAX_BUF_SZ_MASK, cfg_val); - qdma_reg_write(dev_hndl, EQDMA_C2H_WRB_COAL_CFG_ADDR, reg_val); - - /* H2C throttle Configuration*/ - if (eqdma_ip_version == EQDMA_IP_VERSION_4) { - reg_val = - FIELD_SET(H2C_REQ_THROT_PCIE_DATA_THRESH_MASK, - EQDMA_H2C_THROT_DATA_THRESH) | - FIELD_SET(H2C_REQ_THROT_PCIE_EN_DATA_MASK, - EQDMA_THROT_EN_DATA) | - FIELD_SET(H2C_REQ_THROT_PCIE_MASK, - EQDMA_H2C_THROT_REQ_THRESH) | - FIELD_SET(H2C_REQ_THROT_PCIE_EN_REQ_MASK, - EQDMA_THROT_EN_REQ); - - qdma_reg_write(dev_hndl, EQDMA_H2C_REQ_THROT_PCIE_ADDR, - reg_val); - } - } - - if (eqdma_ip_version == EQDMA_IP_VERSION_5) - eqdma_set_perf_opt(dev_hndl); - return QDMA_SUCCESS; -} - -/* - * dump_eqdma_context() - Helper function to dump queue context into string - * - * return len - length of the string copied into buffer - */ -static int dump_eqdma_context(struct qdma_descq_context *queue_context, - uint8_t st, enum qdma_dev_q_type q_type, - char *buf, int buf_sz) -{ - int i = 0; - int n; - int len = 0; - int rv; - char banner[DEBGFS_LINE_SZ] = ""; - - if (queue_context == NULL) { - qdma_log_error("%s: queue_context is NULL, err:%d\n", - __func__, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - if (q_type == QDMA_DEV_Q_TYPE_CMPT) { - eqdma_fill_cmpt_ctxt(&queue_context->cmpt_ctxt); - } else if (q_type == QDMA_DEV_Q_TYPE_H2C) { - eqdma_fill_sw_ctxt(&queue_context->sw_ctxt); - eqdma_fill_hw_ctxt(&queue_context->hw_ctxt); - eqdma_fill_credit_ctxt(&queue_context->cr_ctxt); - } else if (q_type == QDMA_DEV_Q_TYPE_C2H) { - eqdma_fill_sw_ctxt(&queue_context->sw_ctxt); - eqdma_fill_hw_ctxt(&queue_context->hw_ctxt); - eqdma_fill_credit_ctxt(&queue_context->cr_ctxt); - if (st) { - eqdma_fill_pfetch_ctxt(&queue_context->pfetch_ctxt); - eqdma_fill_cmpt_ctxt(&queue_context->cmpt_ctxt); - } - } - - eqdma_fill_fmap_ctxt(&queue_context->fmap); - - if (q_type != QDMA_DEV_Q_TYPE_CMPT) { - for (i = 0; i < DEBGFS_LINE_SZ - 5; i++) { - rv = QDMA_SNPRINTF_S(banner + i, - (DEBGFS_LINE_SZ - i), - sizeof("-"), "-"); - if ((rv < 0) || (rv > (int)sizeof("-"))) { - qdma_log_error( - "%d:%s QDMA_SNPRINTF_S() failed, err:%d\n", - __LINE__, __func__, - rv); - goto INSUF_BUF_EXIT; - } - } - - /* SW context dump */ - n = sizeof(eqdma_sw_ctxt_entries) / - sizeof((eqdma_sw_ctxt_entries)[0]); - for (i = 0; i < n; i++) { - if ((len >= buf_sz) || - ((len + DEBGFS_LINE_SZ) >= buf_sz)) - goto INSUF_BUF_EXIT; - - if (i == 0) { - if ((len + (3 * DEBGFS_LINE_SZ)) >= buf_sz) - goto INSUF_BUF_EXIT; - rv = QDMA_SNPRINTF_S(buf + len, (buf_sz - len), - DEBGFS_LINE_SZ, "\n%s", banner); - if ((rv < 0) || (rv > DEBGFS_LINE_SZ)) { - qdma_log_error( - "%d:%s QDMA_SNPRINTF_S() failed, err:%d\n", - __LINE__, __func__, - rv); - goto INSUF_BUF_EXIT; - } - len += rv; - - rv = QDMA_SNPRINTF_S(buf + len, (buf_sz - len), - DEBGFS_LINE_SZ, "\n%40s", "SW Context"); - if ((rv < 0) || (rv > DEBGFS_LINE_SZ)) { - qdma_log_error( - "%d:%s QDMA_SNPRINTF_S() failed, err:%d\n", - __LINE__, __func__, - rv); - goto INSUF_BUF_EXIT; - } - len += rv; - - rv = QDMA_SNPRINTF_S(buf + len, (buf_sz - len), - DEBGFS_LINE_SZ, "\n%s\n", banner); - if ((rv < 0) || (rv > DEBGFS_LINE_SZ)) { - qdma_log_error( - "%d:%s QDMA_SNPRINTF_S() failed, err:%d\n", - __LINE__, __func__, - rv); - goto INSUF_BUF_EXIT; - } - len += rv; - } - - rv = QDMA_SNPRINTF_S(buf + len, (buf_sz - len), - DEBGFS_LINE_SZ, - "%-47s %#-10x %u\n", - eqdma_sw_ctxt_entries[i].name, - eqdma_sw_ctxt_entries[i].value, - eqdma_sw_ctxt_entries[i].value); - if ((rv < 0) || (rv > DEBGFS_LINE_SZ)) { - qdma_log_error( - "%d:%s QDMA_SNPRINTF_S() failed, err:%d\n", - __LINE__, __func__, - rv); - goto INSUF_BUF_EXIT; - } - len += rv; - } - - /* HW context dump */ - n = sizeof(eqdma_hw_ctxt_entries) / - sizeof((eqdma_hw_ctxt_entries)[0]); - for (i = 0; i < n; i++) { - if ((len >= buf_sz) || - ((len + DEBGFS_LINE_SZ) >= buf_sz)) - goto INSUF_BUF_EXIT; - - if (i == 0) { - if ((len + (3 * DEBGFS_LINE_SZ)) >= buf_sz) - goto INSUF_BUF_EXIT; - - rv = QDMA_SNPRINTF_S(buf + len, (buf_sz - len), - DEBGFS_LINE_SZ, "\n%s", banner); - if ((rv < 0) || (rv > DEBGFS_LINE_SZ)) { - qdma_log_error( - "%d:%s QDMA_SNPRINTF_S() failed, err:%d\n", - __LINE__, __func__, - rv); - goto INSUF_BUF_EXIT; - } - len += rv; - - rv = QDMA_SNPRINTF_S(buf + len, (buf_sz - len), - DEBGFS_LINE_SZ, "\n%40s", "HW Context"); - if ((rv < 0) || (rv > DEBGFS_LINE_SZ)) { - qdma_log_error( - "%d:%s QDMA_SNPRINTF_S() failed, err:%d\n", - __LINE__, __func__, - rv); - goto INSUF_BUF_EXIT; - } - len += rv; - - rv = QDMA_SNPRINTF_S(buf + len, (buf_sz - len), - DEBGFS_LINE_SZ, "\n%s\n", banner); - if ((rv < 0) || (rv > DEBGFS_LINE_SZ)) { - qdma_log_error( - "%d:%s QDMA_SNPRINTF_S() failed, err:%d\n", - __LINE__, __func__, - rv); - goto INSUF_BUF_EXIT; - } - len += rv; - } - - rv = QDMA_SNPRINTF_S(buf + len, (buf_sz - len), - DEBGFS_LINE_SZ, - "%-47s %#-10x %u\n", - eqdma_hw_ctxt_entries[i].name, - eqdma_hw_ctxt_entries[i].value, - eqdma_hw_ctxt_entries[i].value); - if ((rv < 0) || (rv > DEBGFS_LINE_SZ)) { - qdma_log_error( - "%d:%s QDMA_SNPRINTF_S() failed, err:%d\n", - __LINE__, __func__, - rv); - goto INSUF_BUF_EXIT; - } - len += rv; - } - - /* Credit context dump */ - n = sizeof(eqdma_credit_ctxt_entries) / - sizeof((eqdma_credit_ctxt_entries)[0]); - for (i = 0; i < n; i++) { - if ((len >= buf_sz) || - ((len + DEBGFS_LINE_SZ) >= buf_sz)) - goto INSUF_BUF_EXIT; - - if (i == 0) { - if ((len + (3 * DEBGFS_LINE_SZ)) >= buf_sz) - goto INSUF_BUF_EXIT; - - rv = QDMA_SNPRINTF_S(buf + len, (buf_sz - len), - DEBGFS_LINE_SZ, "\n%s", banner); - if ((rv < 0) || (rv > DEBGFS_LINE_SZ)) { - qdma_log_error( - "%d:%s QDMA_SNPRINTF_S() failed, err:%d\n", - __LINE__, __func__, - rv); - goto INSUF_BUF_EXIT; - } - len += rv; - - rv = QDMA_SNPRINTF_S(buf + len, (buf_sz - len), - DEBGFS_LINE_SZ, "\n%40s", - "Credit Context"); - if ((rv < 0) || (rv > DEBGFS_LINE_SZ)) { - qdma_log_error( - "%d:%s QDMA_SNPRINTF_S() failed, err:%d\n", - __LINE__, __func__, - rv); - goto INSUF_BUF_EXIT; - } - len += rv; - - rv = QDMA_SNPRINTF_S(buf + len, (buf_sz - len), - DEBGFS_LINE_SZ, "\n%s\n", banner); - if ((rv < 0) || (rv > DEBGFS_LINE_SZ)) { - qdma_log_error( - "%d:%s QDMA_SNPRINTF_S() failed, err:%d\n", - __LINE__, __func__, - rv); - goto INSUF_BUF_EXIT; - } - len += rv; - } - - rv = QDMA_SNPRINTF_S(buf + len, (buf_sz - len), - DEBGFS_LINE_SZ, - "%-47s %#-10x %u\n", - eqdma_credit_ctxt_entries[i].name, - eqdma_credit_ctxt_entries[i].value, - eqdma_credit_ctxt_entries[i].value); - if ((rv < 0) || (rv > DEBGFS_LINE_SZ)) { - qdma_log_error( - "%d:%s QDMA_SNPRINTF_S() failed, err:%d\n", - __LINE__, __func__, - rv); - goto INSUF_BUF_EXIT; - } - len += rv; - } - } - - if ((q_type == QDMA_DEV_Q_TYPE_CMPT) || - (st && q_type == QDMA_DEV_Q_TYPE_C2H)) { - /* Completion context dump */ - n = sizeof(eqdma_cmpt_ctxt_entries) / - sizeof((eqdma_cmpt_ctxt_entries)[0]); - for (i = 0; i < n; i++) { - if ((len >= buf_sz) || - ((len + DEBGFS_LINE_SZ) >= buf_sz)) - goto INSUF_BUF_EXIT; - - if (i == 0) { - if ((len + (3 * DEBGFS_LINE_SZ)) >= buf_sz) - goto INSUF_BUF_EXIT; - - rv = QDMA_SNPRINTF_S(buf + len, (buf_sz - len), - DEBGFS_LINE_SZ, "\n%s", banner); - if ((rv < 0) || (rv > DEBGFS_LINE_SZ)) { - qdma_log_error( - "%d:%s QDMA_SNPRINTF_S() failed, err:%d\n", - __LINE__, __func__, - rv); - goto INSUF_BUF_EXIT; - } - len += rv; - - rv = QDMA_SNPRINTF_S(buf + len, (buf_sz - len), - DEBGFS_LINE_SZ, "\n%40s", - "Completion Context"); - if ((rv < 0) || (rv > DEBGFS_LINE_SZ)) { - qdma_log_error( - "%d:%s QDMA_SNPRINTF_S() failed, err:%d\n", - __LINE__, __func__, - rv); - goto INSUF_BUF_EXIT; - } - len += rv; - - rv = QDMA_SNPRINTF_S(buf + len, (buf_sz - len), - DEBGFS_LINE_SZ, "\n%s\n", banner); - if ((rv < 0) || (rv > DEBGFS_LINE_SZ)) { - qdma_log_error( - "%d:%s QDMA_SNPRINTF_S() failed, err:%d\n", - __LINE__, __func__, - rv); - goto INSUF_BUF_EXIT; - } - len += rv; - } - - rv = QDMA_SNPRINTF_S(buf + len, (buf_sz - len), - DEBGFS_LINE_SZ, - "%-47s %#-10x %u\n", - eqdma_cmpt_ctxt_entries[i].name, - eqdma_cmpt_ctxt_entries[i].value, - eqdma_cmpt_ctxt_entries[i].value); - if ((rv < 0) || (rv > DEBGFS_LINE_SZ)) { - qdma_log_error( - "%d:%s QDMA_SNPRINTF_S() failed, err:%d\n", - __LINE__, __func__, - rv); - goto INSUF_BUF_EXIT; - } - len += rv; - } - } - - if (st && q_type == QDMA_DEV_Q_TYPE_C2H) { - /* Prefetch context dump */ - n = sizeof(eqdma_c2h_pftch_ctxt_entries) / - sizeof(eqdma_c2h_pftch_ctxt_entries[0]); - for (i = 0; i < n; i++) { - if ((len >= buf_sz) || - ((len + DEBGFS_LINE_SZ) >= buf_sz)) - goto INSUF_BUF_EXIT; - - if (i == 0) { - if ((len + (3 * DEBGFS_LINE_SZ)) >= buf_sz) - goto INSUF_BUF_EXIT; - - rv = QDMA_SNPRINTF_S(buf + len, (buf_sz - len), - DEBGFS_LINE_SZ, "\n%s", banner); - if ((rv < 0) || (rv > DEBGFS_LINE_SZ)) { - qdma_log_error( - "%d:%s QDMA_SNPRINTF_S() failed, err:%d\n", - __LINE__, __func__, - rv); - goto INSUF_BUF_EXIT; - } - len += rv; - - rv = QDMA_SNPRINTF_S(buf + len, (buf_sz - len), - DEBGFS_LINE_SZ, "\n%40s", - "Prefetch Context"); - if ((rv < 0) || (rv > DEBGFS_LINE_SZ)) { - qdma_log_error( - "%d:%s QDMA_SNPRINTF_S() failed, err:%d\n", - __LINE__, __func__, - rv); - goto INSUF_BUF_EXIT; - } - len += rv; - - rv = QDMA_SNPRINTF_S(buf + len, (buf_sz - len), - DEBGFS_LINE_SZ, "\n%s\n", banner); - if ((rv < 0) || (rv > DEBGFS_LINE_SZ)) { - qdma_log_error( - "%d:%s QDMA_SNPRINTF_S() failed, err:%d\n", - __LINE__, __func__, - rv); - goto INSUF_BUF_EXIT; - } - len += rv; - } - - rv = QDMA_SNPRINTF_S(buf + len, (buf_sz - len), - DEBGFS_LINE_SZ, - "%-47s %#-10x %u\n", - eqdma_c2h_pftch_ctxt_entries[i].name, - eqdma_c2h_pftch_ctxt_entries[i].value, - eqdma_c2h_pftch_ctxt_entries[i].value); - if ((rv < 0) || (rv > DEBGFS_LINE_SZ)) { - qdma_log_error( - "%d:%s QDMA_SNPRINTF_S() failed, err:%d\n", - __LINE__, __func__, - rv); - goto INSUF_BUF_EXIT; - } - len += rv; - } - } - - /* FMAP context dump */ - n = sizeof(eqdma_fmap_ctxt_entries) / - sizeof((eqdma_fmap_ctxt_entries)[0]); - for (i = 0; i < n; i++) { - if ((len >= buf_sz) || - ((len + DEBGFS_LINE_SZ) >= buf_sz)) - goto INSUF_BUF_EXIT; - - if (i == 0) { - if ((len + (3 * DEBGFS_LINE_SZ)) >= buf_sz) - goto INSUF_BUF_EXIT; - - rv = QDMA_SNPRINTF_S(buf + len, (buf_sz - len), - DEBGFS_LINE_SZ, "\n%s", banner); - if ((rv < 0) || (rv > DEBGFS_LINE_SZ)) { - qdma_log_error( - "%d:%s QDMA_SNPRINTF_S() failed, err:%d\n", - __LINE__, __func__, - rv); - goto INSUF_BUF_EXIT; - } - len += rv; - - rv = QDMA_SNPRINTF_S(buf + len, (buf_sz - len), - DEBGFS_LINE_SZ, "\n%40s", - "FMAP Context"); - if ((rv < 0) || (rv > DEBGFS_LINE_SZ)) { - qdma_log_error( - "%d:%s QDMA_SNPRINTF_S() failed, err:%d\n", - __LINE__, __func__, - rv); - goto INSUF_BUF_EXIT; - } - len += rv; - - rv = QDMA_SNPRINTF_S(buf + len, (buf_sz - len), - DEBGFS_LINE_SZ, "\n%s\n", banner); - if ((rv < 0) || (rv > DEBGFS_LINE_SZ)) { - qdma_log_error( - "%d:%s QDMA_SNPRINTF_S() failed, err:%d\n", - __LINE__, __func__, - rv); - goto INSUF_BUF_EXIT; - } - len += rv; - } - - rv = QDMA_SNPRINTF_S(buf + len, (buf_sz - len), - DEBGFS_LINE_SZ, - "%-47s %#-10x %u\n", - eqdma_fmap_ctxt_entries[i].name, - eqdma_fmap_ctxt_entries[i].value, - eqdma_fmap_ctxt_entries[i].value); - if ((rv < 0) || (rv > DEBGFS_LINE_SZ)) { - qdma_log_error( - "%d:%s QDMA_SNPRINTF_S() failed, err:%d\n", - __LINE__, __func__, - rv); - goto INSUF_BUF_EXIT; - } - len += rv; - } - - return len; - -INSUF_BUF_EXIT: - if (buf_sz > DEBGFS_LINE_SZ) { - rv = QDMA_SNPRINTF_S((buf + buf_sz - DEBGFS_LINE_SZ), - buf_sz, DEBGFS_LINE_SZ, - "\n\nInsufficient buffer size, partial context dump\n"); - if ((rv < 0) || (rv > DEBGFS_LINE_SZ)) { - qdma_log_error( - "%d:%s QDMA_SNPRINTF_S() failed, err:%d\n", - __LINE__, __func__, - rv); - } - } - - qdma_log_error("%s: Insufficient buffer size, err:%d\n", - __func__, -QDMA_ERR_NO_MEM); - - return -QDMA_ERR_NO_MEM; -} - -/* - * dump_eqdma_intr_context() - Helper function to dump interrupt context into - * string - * - * return len - length of the string copied into buffer - */ -static int dump_eqdma_intr_context(struct qdma_indirect_intr_ctxt *intr_ctx, - int ring_index, - char *buf, int buf_sz) -{ - int i = 0; - int n; - int len = 0; - int rv; - char banner[DEBGFS_LINE_SZ]; - - eqdma_fill_intr_ctxt(intr_ctx); - - for (i = 0; i < DEBGFS_LINE_SZ - 5; i++) { - rv = QDMA_SNPRINTF_S(banner + i, - (DEBGFS_LINE_SZ - i), - sizeof("-"), "-"); - if ((rv < 0) || (rv > (int)sizeof("-"))) { - qdma_log_error( - "%d:%s QDMA_SNPRINTF_S() failed, err:%d\n", - __LINE__, __func__, - rv); - goto INSUF_BUF_EXIT; - } - } - - /* Interrupt context dump */ - n = sizeof(eqdma_ind_intr_ctxt_entries) / - sizeof((eqdma_ind_intr_ctxt_entries)[0]); - for (i = 0; i < n; i++) { - if ((len >= buf_sz) || ((len + DEBGFS_LINE_SZ) >= buf_sz)) - goto INSUF_BUF_EXIT; - - if (i == 0) { - if ((len + (3 * DEBGFS_LINE_SZ)) >= buf_sz) - goto INSUF_BUF_EXIT; - - rv = QDMA_SNPRINTF_S(buf + len, (buf_sz - len), - DEBGFS_LINE_SZ, "\n%s", banner); - if ((rv < 0) || (rv > DEBGFS_LINE_SZ)) { - qdma_log_error( - "%d:%s QDMA_SNPRINTF_S() failed, err:%d\n", - __LINE__, __func__, - rv); - goto INSUF_BUF_EXIT; - } - len += rv; - - rv = QDMA_SNPRINTF_S(buf + len, (buf_sz - len), - DEBGFS_LINE_SZ, "\n%50s %d", - "Interrupt Context for ring#", ring_index); - if ((rv < 0) || (rv > DEBGFS_LINE_SZ)) { - qdma_log_error( - "%d:%s QDMA_SNPRINTF_S() failed, err:%d\n", - __LINE__, __func__, - rv); - goto INSUF_BUF_EXIT; - } - len += rv; - - rv = QDMA_SNPRINTF_S(buf + len, (buf_sz - len), - DEBGFS_LINE_SZ, "\n%s\n", banner); - if ((rv < 0) || (rv > DEBGFS_LINE_SZ)) { - qdma_log_error( - "%d:%s QDMA_SNPRINTF_S() failed, err:%d\n", - __LINE__, __func__, - rv); - goto INSUF_BUF_EXIT; - } - len += rv; - } - - rv = QDMA_SNPRINTF_S(buf + len, (buf_sz - len), DEBGFS_LINE_SZ, - "%-47s %#-10x %u\n", - eqdma_ind_intr_ctxt_entries[i].name, - eqdma_ind_intr_ctxt_entries[i].value, - eqdma_ind_intr_ctxt_entries[i].value); - if ((rv < 0) || (rv > DEBGFS_LINE_SZ)) { - qdma_log_error( - "%d:%s QDMA_SNPRINTF_S() failed, err:%d\n", - __LINE__, __func__, - rv); - goto INSUF_BUF_EXIT; - } - len += rv; - } - - return len; - -INSUF_BUF_EXIT: - if (buf_sz > DEBGFS_LINE_SZ) { - rv = QDMA_SNPRINTF_S((buf + buf_sz - DEBGFS_LINE_SZ), - buf_sz, DEBGFS_LINE_SZ, - "\n\nInsufficient buffer size, partial context dump\n"); - if ((rv < 0) || (rv > DEBGFS_LINE_SZ)) { - qdma_log_error( - "%d:%s QDMA_SNPRINTF_S() failed, err:%d\n", - __LINE__, __func__, - rv); - } - } - - qdma_log_error("%s: Insufficient buffer size, err:%d\n", - __func__, -QDMA_ERR_NO_MEM); - - return -QDMA_ERR_NO_MEM; -} - -/*****************************************************************************/ -/** - * eqdma_get_version() - Function to get the eqdma version - * - * @dev_hndl: device handle - * @is_vf: Whether PF or VF - * @version_info: pointer to hold the version info - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -int eqdma_get_version(void *dev_hndl, uint8_t is_vf, - struct qdma_hw_version_info *version_info) -{ - uint32_t reg_val = 0; - uint32_t reg_addr = (is_vf) ? EQDMA_OFFSET_VF_VERSION : - EQDMA_GLBL2_MISC_CAP_ADDR; - - if (!dev_hndl) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - reg_val = qdma_reg_read(dev_hndl, reg_addr); - - qdma_fetch_version_details(dev_hndl, is_vf, reg_val, version_info); - - return QDMA_SUCCESS; -} - -/*****************************************************************************/ -/** - * eqdma_sw_context_write() - create sw context and program it - * - * @dev_hndl: device handle - * @c2h: is c2h queue - * @hw_qid: hardware qid of the queue - * @ctxt: pointer to the SW context data strucutre - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -static int eqdma_sw_context_write(void *dev_hndl, uint8_t c2h, - uint16_t hw_qid, - const struct qdma_descq_sw_ctxt *ctxt) -{ - uint32_t sw_ctxt[EQDMA_SW_CONTEXT_NUM_WORDS] = {0}; - uint16_t num_words_count = 0; - uint32_t pasid_l, pasid_h; - uint32_t virtio_desc_base_l, virtio_desc_base_m, virtio_desc_base_h; - enum ind_ctxt_cmd_sel sel = c2h ? - QDMA_CTXT_SEL_SW_C2H : QDMA_CTXT_SEL_SW_H2C; - - /* Input args check */ - if (!dev_hndl || !ctxt) { - qdma_log_error("%s: dev_handle=%p sw_ctxt=%p NULL, err:%d\n", - __func__, dev_hndl, ctxt, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - pasid_l = - FIELD_GET(EQDMA_SW_CTXT_PASID_GET_L_MASK, ctxt->pasid); - pasid_h = - FIELD_GET(EQDMA_SW_CTXT_PASID_GET_H_MASK, ctxt->pasid); - - virtio_desc_base_l = (uint32_t)FIELD_GET( - EQDMA_SW_CTXT_VIRTIO_DSC_BASE_GET_L_MASK, - ctxt->virtio_dsc_base); - virtio_desc_base_m = (uint32_t)FIELD_GET( - EQDMA_SW_CTXT_VIRTIO_DSC_BASE_GET_M_MASK, - ctxt->virtio_dsc_base); - virtio_desc_base_h = (uint32_t)FIELD_GET( - EQDMA_SW_CTXT_VIRTIO_DSC_BASE_GET_H_MASK, - ctxt->virtio_dsc_base); - - sw_ctxt[num_words_count++] = - FIELD_SET(SW_IND_CTXT_DATA_W0_PIDX_MASK, ctxt->pidx) | - FIELD_SET(SW_IND_CTXT_DATA_W0_IRQ_ARM_MASK, ctxt->irq_arm) | - FIELD_SET(SW_IND_CTXT_DATA_W0_FNC_MASK, ctxt->fnc_id); - - qdma_log_debug("%s: pidx=%x, irq_arm=%x, fnc_id=%x\n", - __func__, ctxt->pidx, ctxt->irq_arm, ctxt->fnc_id); - - sw_ctxt[num_words_count++] = - FIELD_SET(SW_IND_CTXT_DATA_W1_QEN_MASK, ctxt->qen) | - FIELD_SET(SW_IND_CTXT_DATA_W1_FCRD_EN_MASK, ctxt->frcd_en) | - FIELD_SET(SW_IND_CTXT_DATA_W1_WBI_CHK_MASK, ctxt->wbi_chk) | - FIELD_SET(SW_IND_CTXT_DATA_W1_WBI_INTVL_EN_MASK, - ctxt->wbi_intvl_en) | - FIELD_SET(SW_IND_CTXT_DATA_W1_AT_MASK, ctxt->at) | - FIELD_SET(SW_IND_CTXT_DATA_W1_FETCH_MAX_MASK, ctxt->fetch_max) | - FIELD_SET(SW_IND_CTXT_DATA_W1_RNG_SZ_MASK, ctxt->rngsz_idx) | - FIELD_SET(SW_IND_CTXT_DATA_W1_DSC_SZ_MASK, ctxt->desc_sz) | - FIELD_SET(SW_IND_CTXT_DATA_W1_BYPASS_MASK, ctxt->bypass) | - FIELD_SET(SW_IND_CTXT_DATA_W1_MM_CHN_MASK, ctxt->mm_chn) | - FIELD_SET(SW_IND_CTXT_DATA_W1_WBK_EN_MASK, ctxt->wbk_en) | - FIELD_SET(SW_IND_CTXT_DATA_W1_IRQ_EN_MASK, ctxt->irq_en) | - FIELD_SET(SW_IND_CTXT_DATA_W1_PORT_ID_MASK, ctxt->port_id) | - FIELD_SET(SW_IND_CTXT_DATA_W1_IRQ_NO_LAST_MASK, - ctxt->irq_no_last) | - FIELD_SET(SW_IND_CTXT_DATA_W1_ERR_MASK, ctxt->err) | - FIELD_SET(SW_IND_CTXT_DATA_W1_ERR_WB_SENT_MASK, - ctxt->err_wb_sent) | - FIELD_SET(SW_IND_CTXT_DATA_W1_IRQ_REQ_MASK, ctxt->irq_req) | - FIELD_SET(SW_IND_CTXT_DATA_W1_MRKR_DIS_MASK, ctxt->mrkr_dis) | - FIELD_SET(SW_IND_CTXT_DATA_W1_IS_MM_MASK, ctxt->is_mm); - - qdma_log_debug("%s: qen=%x, frcd_en=%x, wbi_chk=%x, wbi_intvl_en=%x\n", - __func__, ctxt->qen, ctxt->frcd_en, ctxt->wbi_chk, - ctxt->wbi_intvl_en); - - qdma_log_debug("%s: at=%x, fetch_max=%x, rngsz_idx=%x, desc_sz=%x\n", - __func__, ctxt->at, ctxt->fetch_max, ctxt->rngsz_idx, - ctxt->desc_sz); - - qdma_log_debug("%s: bypass=%x, mm_chn=%x, wbk_en=%x, irq_en=%x\n", - __func__, ctxt->bypass, ctxt->mm_chn, ctxt->wbk_en, - ctxt->irq_en); - - qdma_log_debug("%s: port_id=%x, irq_no_last=%x,err=%x", - __func__, ctxt->port_id, ctxt->irq_no_last, ctxt->err); - qdma_log_debug(", err_wb_sent=%x\n", ctxt->err_wb_sent); - - qdma_log_debug("%s: irq_req=%x, mrkr_dis=%x, is_mm=%x\n", - __func__, ctxt->irq_req, ctxt->mrkr_dis, ctxt->is_mm); - - sw_ctxt[num_words_count++] = ctxt->ring_bs_addr & 0xffffffff; - sw_ctxt[num_words_count++] = (ctxt->ring_bs_addr >> 32) & 0xffffffff; - - sw_ctxt[num_words_count++] = - FIELD_SET(SW_IND_CTXT_DATA_W4_VEC_MASK, ctxt->vec) | - FIELD_SET(SW_IND_CTXT_DATA_W4_INT_AGGR_MASK, ctxt->intr_aggr) | - FIELD_SET(SW_IND_CTXT_DATA_W4_DIS_INTR_ON_VF_MASK, - ctxt->dis_intr_on_vf) | - FIELD_SET(SW_IND_CTXT_DATA_W4_VIRTIO_EN_MASK, - ctxt->virtio_en) | - FIELD_SET(SW_IND_CTXT_DATA_W4_PACK_BYP_OUT_MASK, - ctxt->pack_byp_out) | - FIELD_SET(SW_IND_CTXT_DATA_W4_IRQ_BYP_MASK, ctxt->irq_byp) | - FIELD_SET(SW_IND_CTXT_DATA_W4_HOST_ID_MASK, ctxt->host_id) | - FIELD_SET(SW_IND_CTXT_DATA_W4_PASID_L_MASK, pasid_l); - - sw_ctxt[num_words_count++] = - FIELD_SET(SW_IND_CTXT_DATA_W5_PASID_H_MASK, pasid_h) | - FIELD_SET(SW_IND_CTXT_DATA_W5_PASID_EN_MASK, ctxt->pasid_en) | - FIELD_SET(SW_IND_CTXT_DATA_W5_VIRTIO_DSC_BASE_L_MASK, - virtio_desc_base_l); - - sw_ctxt[num_words_count++] = - FIELD_SET(SW_IND_CTXT_DATA_W6_VIRTIO_DSC_BASE_M_MASK, - virtio_desc_base_m); - - sw_ctxt[num_words_count++] = - FIELD_SET(SW_IND_CTXT_DATA_W7_VIRTIO_DSC_BASE_H_MASK, - virtio_desc_base_h); - - - qdma_log_debug("%s: vec=%x, intr_aggr=%x\n", - __func__, ctxt->vec, ctxt->intr_aggr); - - return eqdma_indirect_reg_write(dev_hndl, sel, hw_qid, - sw_ctxt, num_words_count); -} - -/*****************************************************************************/ -/** - * eqdma_sw_context_read() - read sw context - * - * @dev_hndl: device handle - * @c2h: is c2h queue - * @hw_qid: hardware qid of the queue - * @ctxt: pointer to the output context data - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -static int eqdma_sw_context_read(void *dev_hndl, uint8_t c2h, - uint16_t hw_qid, - struct qdma_descq_sw_ctxt *ctxt) -{ - int rv = QDMA_SUCCESS; - uint32_t sw_ctxt[EQDMA_SW_CONTEXT_NUM_WORDS] = {0}; - uint32_t pasid_l, pasid_h; - uint32_t virtio_desc_base_l, virtio_desc_base_m, virtio_desc_base_h; - enum ind_ctxt_cmd_sel sel = c2h ? - QDMA_CTXT_SEL_SW_C2H : QDMA_CTXT_SEL_SW_H2C; - - if (!dev_hndl || !ctxt) { - qdma_log_error("%s: dev_handle=%p sw_ctxt=%p NULL, err:%d\n", - __func__, dev_hndl, ctxt, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - rv = eqdma_indirect_reg_read(dev_hndl, sel, hw_qid, - EQDMA_SW_CONTEXT_NUM_WORDS, sw_ctxt); - if (rv < 0) - return rv; - - ctxt->pidx = FIELD_GET(SW_IND_CTXT_DATA_W0_PIDX_MASK, sw_ctxt[0]); - ctxt->irq_arm = - (uint8_t)(FIELD_GET(SW_IND_CTXT_DATA_W0_IRQ_ARM_MASK, - sw_ctxt[0])); - ctxt->fnc_id = - (uint8_t)(FIELD_GET(SW_IND_CTXT_DATA_W0_FNC_MASK, - sw_ctxt[0])); - - qdma_log_debug("%s: pidx=%x, irq_arm=%x, fnc_id=%x", - __func__, ctxt->pidx, ctxt->irq_arm, ctxt->fnc_id); - - ctxt->qen = FIELD_GET(SW_IND_CTXT_DATA_W1_QEN_MASK, sw_ctxt[1]); - ctxt->frcd_en = FIELD_GET(SW_IND_CTXT_DATA_W1_FCRD_EN_MASK, sw_ctxt[1]); - ctxt->wbi_chk = FIELD_GET(SW_IND_CTXT_DATA_W1_WBI_CHK_MASK, sw_ctxt[1]); - ctxt->wbi_intvl_en = - FIELD_GET(SW_IND_CTXT_DATA_W1_WBI_INTVL_EN_MASK, sw_ctxt[1]); - ctxt->at = FIELD_GET(SW_IND_CTXT_DATA_W1_AT_MASK, sw_ctxt[1]); - ctxt->fetch_max = - (uint8_t)FIELD_GET(SW_IND_CTXT_DATA_W1_FETCH_MAX_MASK, - sw_ctxt[1]); - ctxt->rngsz_idx = - (uint8_t)(FIELD_GET(SW_IND_CTXT_DATA_W1_RNG_SZ_MASK, - sw_ctxt[1])); - ctxt->desc_sz = - (uint8_t)(FIELD_GET(SW_IND_CTXT_DATA_W1_DSC_SZ_MASK, - sw_ctxt[1])); - ctxt->bypass = - (uint8_t)(FIELD_GET(SW_IND_CTXT_DATA_W1_BYPASS_MASK, - sw_ctxt[1])); - ctxt->mm_chn = - (uint8_t)(FIELD_GET(SW_IND_CTXT_DATA_W1_MM_CHN_MASK, - sw_ctxt[1])); - ctxt->wbk_en = - (uint8_t)(FIELD_GET(SW_IND_CTXT_DATA_W1_WBK_EN_MASK, - sw_ctxt[1])); - ctxt->irq_en = - (uint8_t)(FIELD_GET(SW_IND_CTXT_DATA_W1_IRQ_EN_MASK, - sw_ctxt[1])); - ctxt->port_id = - (uint8_t)(FIELD_GET(SW_IND_CTXT_DATA_W1_PORT_ID_MASK, - sw_ctxt[1])); - ctxt->irq_no_last = - (uint8_t)(FIELD_GET(SW_IND_CTXT_DATA_W1_IRQ_NO_LAST_MASK, - sw_ctxt[1])); - ctxt->err = - (uint8_t)(FIELD_GET(SW_IND_CTXT_DATA_W1_ERR_MASK, sw_ctxt[1])); - ctxt->err_wb_sent = - (uint8_t)(FIELD_GET(SW_IND_CTXT_DATA_W1_ERR_WB_SENT_MASK, - sw_ctxt[1])); - ctxt->irq_req = - (uint8_t)(FIELD_GET(SW_IND_CTXT_DATA_W1_IRQ_REQ_MASK, - sw_ctxt[1])); - ctxt->mrkr_dis = - (uint8_t)(FIELD_GET(SW_IND_CTXT_DATA_W1_MRKR_DIS_MASK, - sw_ctxt[1])); - ctxt->is_mm = - (uint8_t)(FIELD_GET(SW_IND_CTXT_DATA_W1_IS_MM_MASK, - sw_ctxt[1])); - - qdma_log_debug("%s: qen=%x, frcd_en=%x, wbi_chk=%x, wbi_intvl_en=%x\n", - __func__, ctxt->qen, ctxt->frcd_en, ctxt->wbi_chk, - ctxt->wbi_intvl_en); - qdma_log_debug("%s: at=%x, fetch_max=%x, rngsz_idx=%x, desc_sz=%x\n", - __func__, ctxt->at, ctxt->fetch_max, ctxt->rngsz_idx, - ctxt->desc_sz); - qdma_log_debug("%s: bypass=%x, mm_chn=%x, wbk_en=%x, irq_en=%x\n", - __func__, ctxt->bypass, ctxt->mm_chn, ctxt->wbk_en, - ctxt->irq_en); - qdma_log_debug("%s: port_id=%x, irq_no_last=%x,", - __func__, ctxt->port_id, ctxt->irq_no_last); - qdma_log_debug(" err=%x, err_wb_sent=%x\n", - ctxt->err, ctxt->err_wb_sent); - qdma_log_debug("%s: irq_req=%x, mrkr_dis=%x, is_mm=%x\n", - __func__, ctxt->irq_req, ctxt->mrkr_dis, ctxt->is_mm); - - ctxt->ring_bs_addr = ((uint64_t)sw_ctxt[3] << 32) | (sw_ctxt[2]); - - ctxt->vec = FIELD_GET(SW_IND_CTXT_DATA_W4_VEC_MASK, sw_ctxt[4]); - ctxt->intr_aggr = (uint8_t)(FIELD_GET(SW_IND_CTXT_DATA_W4_INT_AGGR_MASK, - sw_ctxt[4])); - ctxt->dis_intr_on_vf = - (uint8_t)(FIELD_GET(SW_IND_CTXT_DATA_W4_DIS_INTR_ON_VF_MASK, - sw_ctxt[4])); - ctxt->virtio_en = - (uint8_t)(FIELD_GET(SW_IND_CTXT_DATA_W4_VIRTIO_EN_MASK, - sw_ctxt[4])); - ctxt->pack_byp_out = - (uint8_t)(FIELD_GET(SW_IND_CTXT_DATA_W4_PACK_BYP_OUT_MASK, - sw_ctxt[4])); - ctxt->irq_byp = - (uint8_t)(FIELD_GET(SW_IND_CTXT_DATA_W4_IRQ_BYP_MASK, - sw_ctxt[4])); - ctxt->host_id = - (uint8_t)(FIELD_GET(SW_IND_CTXT_DATA_W4_HOST_ID_MASK, - sw_ctxt[4])); - pasid_l = FIELD_GET(SW_IND_CTXT_DATA_W4_PASID_L_MASK, sw_ctxt[4]); - - pasid_h = FIELD_GET(SW_IND_CTXT_DATA_W5_PASID_H_MASK, sw_ctxt[5]); - ctxt->pasid_en = (uint8_t)FIELD_GET(SW_IND_CTXT_DATA_W5_PASID_EN_MASK, - sw_ctxt[5]); - virtio_desc_base_l = - FIELD_GET(SW_IND_CTXT_DATA_W5_VIRTIO_DSC_BASE_L_MASK, - sw_ctxt[5]); - virtio_desc_base_m = - FIELD_GET(SW_IND_CTXT_DATA_W6_VIRTIO_DSC_BASE_M_MASK, - sw_ctxt[6]); - - virtio_desc_base_h = - FIELD_GET(SW_IND_CTXT_DATA_W7_VIRTIO_DSC_BASE_H_MASK, - sw_ctxt[6]); - - ctxt->pasid = - FIELD_SET(EQDMA_SW_CTXT_PASID_GET_L_MASK, pasid_l) | - FIELD_SET(EQDMA_SW_CTXT_PASID_GET_H_MASK, pasid_h); - - ctxt->virtio_dsc_base = - FIELD_SET(EQDMA_SW_CTXT_VIRTIO_DSC_BASE_GET_L_MASK, - (uint64_t)virtio_desc_base_l) | - FIELD_SET(EQDMA_SW_CTXT_VIRTIO_DSC_BASE_GET_M_MASK, - (uint64_t)virtio_desc_base_m) | - FIELD_SET(EQDMA_SW_CTXT_VIRTIO_DSC_BASE_GET_H_MASK, - (uint64_t)virtio_desc_base_h); - - qdma_log_debug("%s: vec=%x, intr_aggr=%x\n", - __func__, ctxt->vec, ctxt->intr_aggr); - - return QDMA_SUCCESS; -} - -/*****************************************************************************/ -/** - * eqdma_sw_context_clear() - clear sw context - * - * @dev_hndl: device handle - * @c2h: is c2h queue - * @hw_qid: hardware qid of the queue - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -static int eqdma_sw_context_clear(void *dev_hndl, uint8_t c2h, - uint16_t hw_qid) -{ - enum ind_ctxt_cmd_sel sel = c2h ? - QDMA_CTXT_SEL_SW_C2H : QDMA_CTXT_SEL_SW_H2C; - - if (!dev_hndl) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", __func__, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - return eqdma_indirect_reg_clear(dev_hndl, sel, hw_qid); -} - -/*****************************************************************************/ -/** - * eqdma_sw_context_invalidate() - invalidate sw context - * - * @dev_hndl: device handle - * @c2h: is c2h queue - * @hw_qid: hardware qid of the queue - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -static int eqdma_sw_context_invalidate(void *dev_hndl, uint8_t c2h, - uint16_t hw_qid) -{ - enum ind_ctxt_cmd_sel sel = c2h ? - QDMA_CTXT_SEL_SW_C2H : QDMA_CTXT_SEL_SW_H2C; - - if (!dev_hndl) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", __func__, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - return eqdma_indirect_reg_invalidate(dev_hndl, sel, hw_qid); -} - -/*****************************************************************************/ -/** - * eqdma_sw_ctx_conf() - configure SW context - * - * @dev_hndl: device handle - * @c2h: is c2h queue - * @hw_qid: hardware qid of the queue - * @ctxt: pointer to the context data - * @access_type HW access type (qdma_hw_access_type enum) value - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -int eqdma_sw_ctx_conf(void *dev_hndl, uint8_t c2h, uint16_t hw_qid, - struct qdma_descq_sw_ctxt *ctxt, - enum qdma_hw_access_type access_type) -{ - int rv = QDMA_SUCCESS; - - switch (access_type) { - case QDMA_HW_ACCESS_READ: - rv = eqdma_sw_context_read(dev_hndl, c2h, hw_qid, ctxt); - break; - case QDMA_HW_ACCESS_WRITE: - rv = eqdma_sw_context_write(dev_hndl, c2h, hw_qid, ctxt); - break; - case QDMA_HW_ACCESS_CLEAR: - rv = eqdma_sw_context_clear(dev_hndl, c2h, hw_qid); - break; - case QDMA_HW_ACCESS_INVALIDATE: - rv = eqdma_sw_context_invalidate(dev_hndl, c2h, hw_qid); - break; - default: - qdma_log_error("%s: access_type(%d) invalid, err:%d\n", - __func__, - access_type, - -QDMA_ERR_INV_PARAM); - rv = -QDMA_ERR_INV_PARAM; - break; - } - - return rv; -} - -/*****************************************************************************/ -/** - * eqdma_pfetch_context_write() - create prefetch context and program it - * - * @dev_hndl: device handle - * @hw_qid: hardware qid of the queue - * @ctxt: pointer to the prefetch context data strucutre - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -static int eqdma_pfetch_context_write(void *dev_hndl, uint16_t hw_qid, - const struct qdma_descq_prefetch_ctxt *ctxt) -{ - uint32_t pfetch_ctxt[EQDMA_PFETCH_CONTEXT_NUM_WORDS] = {0}; - enum ind_ctxt_cmd_sel sel = QDMA_CTXT_SEL_PFTCH; - uint32_t sw_crdt_l, sw_crdt_h; - uint16_t num_words_count = 0; - - if (!dev_hndl || !ctxt) { - qdma_log_error("%s: dev_handle or pfetch ctxt NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - sw_crdt_l = - FIELD_GET(QDMA_PFTCH_CTXT_SW_CRDT_GET_L_MASK, ctxt->sw_crdt); - sw_crdt_h = - FIELD_GET(QDMA_PFTCH_CTXT_SW_CRDT_GET_H_MASK, ctxt->sw_crdt); - - qdma_log_debug("%s: sw_crdt_l=%u, sw_crdt_h=%u, hw_qid=%hu\n", - __func__, sw_crdt_l, sw_crdt_h, hw_qid); - - pfetch_ctxt[num_words_count++] = - FIELD_SET(PREFETCH_CTXT_DATA_W0_BYPASS_MASK, ctxt->bypass) | - FIELD_SET(PREFETCH_CTXT_DATA_W0_BUF_SZ_IDX_MASK, - ctxt->bufsz_idx) | - FIELD_SET(PREFETCH_CTXT_DATA_W0_PORT_ID_MASK, ctxt->port_id) | - FIELD_SET(PREFETCH_CTXT_DATA_W0_NUM_PFCH_MASK, - ctxt->num_pftch) | - FIELD_SET(PREFETCH_CTXT_DATA_W0_VAR_DESC_MASK, - ctxt->var_desc) | - FIELD_SET(PREFETCH_CTXT_DATA_W0_ERR_MASK, ctxt->err) | - FIELD_SET(PREFETCH_CTXT_DATA_W0_PFCH_EN_MASK, ctxt->pfch_en) | - FIELD_SET(PREFETCH_CTXT_DATA_W0_PFCH_MASK, ctxt->pfch) | - FIELD_SET(PREFETCH_CTXT_DATA_W0_SW_CRDT_L_MASK, sw_crdt_l); - - qdma_log_debug("%s: bypass=%x, bufsz_idx=%x, port_id=%x\n", - __func__, ctxt->bypass, ctxt->bufsz_idx, ctxt->port_id); - qdma_log_debug("%s: err=%x, pfch_en=%x, pfch=%x, ctxt->valid=%x\n", - __func__, ctxt->err, ctxt->pfch_en, ctxt->pfch, - ctxt->valid); - - pfetch_ctxt[num_words_count++] = - FIELD_SET(PREFETCH_CTXT_DATA_W1_SW_CRDT_H_MASK, sw_crdt_h) | - FIELD_SET(PREFETCH_CTXT_DATA_W1_VALID_MASK, ctxt->valid); - - return eqdma_indirect_reg_write(dev_hndl, sel, hw_qid, - pfetch_ctxt, num_words_count); -} - -/*****************************************************************************/ -/** - * eqdma_pfetch_context_read() - read prefetch context - * - * @dev_hndl: device handle - * @hw_qid: hardware qid of the queue - * @ctxt: pointer to the output context data - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -static int eqdma_pfetch_context_read(void *dev_hndl, uint16_t hw_qid, - struct qdma_descq_prefetch_ctxt *ctxt) -{ - int rv = QDMA_SUCCESS; - uint32_t pfetch_ctxt[EQDMA_PFETCH_CONTEXT_NUM_WORDS] = {0}; - enum ind_ctxt_cmd_sel sel = QDMA_CTXT_SEL_PFTCH; - uint32_t sw_crdt_l, sw_crdt_h; - - if (!dev_hndl || !ctxt) { - qdma_log_error("%s: dev_handle or pfetch ctxt NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - rv = eqdma_indirect_reg_read(dev_hndl, sel, hw_qid, - EQDMA_PFETCH_CONTEXT_NUM_WORDS, pfetch_ctxt); - if (rv < 0) - return rv; - - ctxt->bypass = - FIELD_GET(PREFETCH_CTXT_DATA_W0_BYPASS_MASK, pfetch_ctxt[0]); - ctxt->bufsz_idx = - FIELD_GET(PREFETCH_CTXT_DATA_W0_BUF_SZ_IDX_MASK, - pfetch_ctxt[0]); - ctxt->num_pftch = (uint16_t) FIELD_GET( - PREFETCH_CTXT_DATA_W0_NUM_PFCH_MASK, pfetch_ctxt[0]); - ctxt->port_id = - FIELD_GET(PREFETCH_CTXT_DATA_W0_PORT_ID_MASK, pfetch_ctxt[0]); - ctxt->var_desc = (uint8_t) - FIELD_GET(PREFETCH_CTXT_DATA_W0_VAR_DESC_MASK, - pfetch_ctxt[0]); - ctxt->err = - (uint8_t)(FIELD_GET(PREFETCH_CTXT_DATA_W0_ERR_MASK, - pfetch_ctxt[0])); - ctxt->pfch_en = - (uint8_t)(FIELD_GET(PREFETCH_CTXT_DATA_W0_PFCH_EN_MASK, - pfetch_ctxt[0])); - ctxt->pfch = - (uint8_t)(FIELD_GET(PREFETCH_CTXT_DATA_W0_PFCH_MASK, - pfetch_ctxt[0])); - sw_crdt_l = - FIELD_GET(PREFETCH_CTXT_DATA_W0_SW_CRDT_L_MASK, pfetch_ctxt[0]); - - sw_crdt_h = - FIELD_GET(PREFETCH_CTXT_DATA_W1_SW_CRDT_H_MASK, pfetch_ctxt[1]); - ctxt->valid = - (uint8_t)(FIELD_GET(PREFETCH_CTXT_DATA_W1_VALID_MASK, - pfetch_ctxt[1])); - - ctxt->sw_crdt = - FIELD_SET(QDMA_PFTCH_CTXT_SW_CRDT_GET_L_MASK, sw_crdt_l) | - FIELD_SET(QDMA_PFTCH_CTXT_SW_CRDT_GET_H_MASK, sw_crdt_h); - - qdma_log_debug("%s: sw_crdt_l=%u, sw_crdt_h=%u, hw_qid=%hu\n", - __func__, sw_crdt_l, sw_crdt_h, hw_qid); - qdma_log_debug("%s: bypass=%x, bufsz_idx=%x, port_id=%x\n", - __func__, ctxt->bypass, ctxt->bufsz_idx, ctxt->port_id); - qdma_log_debug("%s: err=%x, pfch_en=%x, pfch=%x, ctxt->valid=%x\n", - __func__, ctxt->err, ctxt->pfch_en, ctxt->pfch, - ctxt->valid); - - return QDMA_SUCCESS; -} - -/*****************************************************************************/ -/** - * eqdma_pfetch_context_clear() - clear prefetch context - * - * @dev_hndl: device handle - * @hw_qid: hardware qid of the queue - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -static int eqdma_pfetch_context_clear(void *dev_hndl, uint16_t hw_qid) -{ - enum ind_ctxt_cmd_sel sel = QDMA_CTXT_SEL_PFTCH; - - if (!dev_hndl) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", __func__, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - return eqdma_indirect_reg_clear(dev_hndl, sel, hw_qid); -} - -/*****************************************************************************/ -/** - * eqdma_pfetch_context_invalidate() - invalidate prefetch context - * - * @dev_hndl: device handle - * @hw_qid: hardware qid of the queue - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -static int eqdma_pfetch_context_invalidate(void *dev_hndl, uint16_t hw_qid) -{ - enum ind_ctxt_cmd_sel sel = QDMA_CTXT_SEL_PFTCH; - - if (!dev_hndl) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", __func__, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - return eqdma_indirect_reg_invalidate(dev_hndl, sel, hw_qid); -} - -/*****************************************************************************/ -/** - * eqdma_pfetch_ctx_conf() - configure prefetch context - * - * @dev_hndl: device handle - * @hw_qid: hardware qid of the queue - * @ctxt: pointer to context data - * @access_type HW access type (qdma_hw_access_type enum) value - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -int eqdma_pfetch_ctx_conf(void *dev_hndl, uint16_t hw_qid, - struct qdma_descq_prefetch_ctxt *ctxt, - enum qdma_hw_access_type access_type) -{ - int rv = QDMA_SUCCESS; - - switch (access_type) { - case QDMA_HW_ACCESS_READ: - rv = eqdma_pfetch_context_read(dev_hndl, hw_qid, ctxt); - break; - case QDMA_HW_ACCESS_WRITE: - rv = eqdma_pfetch_context_write(dev_hndl, hw_qid, ctxt); - break; - case QDMA_HW_ACCESS_CLEAR: - rv = eqdma_pfetch_context_clear(dev_hndl, hw_qid); - break; - case QDMA_HW_ACCESS_INVALIDATE: - rv = eqdma_pfetch_context_invalidate(dev_hndl, hw_qid); - break; - default: - qdma_log_error("%s: access_type(%d) invalid, err:%d\n", - __func__, - access_type, - -QDMA_ERR_INV_PARAM); - rv = -QDMA_ERR_INV_PARAM; - break; - } - - return rv; -} - -/*****************************************************************************/ -/** - * eqdma_cmpt_context_write() - create completion context and program it - * - * @dev_hndl: device handle - * @hw_qid: hardware qid of the queue - * @ctxt: pointer to the cmpt context data strucutre - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -static int eqdma_cmpt_context_write(void *dev_hndl, uint16_t hw_qid, - const struct qdma_descq_cmpt_ctxt *ctxt) -{ - uint32_t cmpt_ctxt[EQDMA_CMPT_CONTEXT_NUM_WORDS] = {0}; - uint16_t num_words_count = 0; - uint32_t baddr4_high_l, baddr4_high_h, - baddr4_low, pidx_l, pidx_h, pasid_l, pasid_h; - enum ind_ctxt_cmd_sel sel = QDMA_CTXT_SEL_CMPT; - - /* Input args check */ - if (!dev_hndl || !ctxt) { - qdma_log_error("%s: dev_handle or cmpt ctxt NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - if (ctxt->trig_mode > QDMA_CMPT_UPDATE_TRIG_MODE_TMR_CNTR) { - qdma_log_error("%s: trig_mode(%d) > (%d) is invalid, err:%d\n", - __func__, - ctxt->trig_mode, - QDMA_CMPT_UPDATE_TRIG_MODE_TMR_CNTR, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - baddr4_high_l = (uint32_t)FIELD_GET(EQDMA_COMPL_CTXT_BADDR_HIGH_L_MASK, - ctxt->bs_addr); - baddr4_high_h = (uint32_t)FIELD_GET(EQDMA_COMPL_CTXT_BADDR_HIGH_H_MASK, - ctxt->bs_addr); - baddr4_low = (uint32_t)FIELD_GET(EQDMA_COMPL_CTXT_BADDR_LOW_MASK, - ctxt->bs_addr); - - pidx_l = FIELD_GET(QDMA_COMPL_CTXT_PIDX_GET_L_MASK, ctxt->pidx); - pidx_h = FIELD_GET(QDMA_COMPL_CTXT_PIDX_GET_H_MASK, ctxt->pidx); - - pasid_l = - FIELD_GET(EQDMA_CMPL_CTXT_PASID_GET_L_MASK, ctxt->pasid); - pasid_h = - FIELD_GET(EQDMA_CMPL_CTXT_PASID_GET_H_MASK, ctxt->pasid); - - cmpt_ctxt[num_words_count++] = - FIELD_SET(CMPL_CTXT_DATA_W0_EN_STAT_DESC_MASK, - ctxt->en_stat_desc) | - FIELD_SET(CMPL_CTXT_DATA_W0_EN_INT_MASK, ctxt->en_int) | - FIELD_SET(CMPL_CTXT_DATA_W0_TRIG_MODE_MASK, ctxt->trig_mode) | - FIELD_SET(CMPL_CTXT_DATA_W0_FNC_ID_MASK, ctxt->fnc_id) | - FIELD_SET(CMPL_CTXT_DATA_W0_CNTER_IX_MASK, - ctxt->counter_idx) | - FIELD_SET(CMPL_CTXT_DATA_W0_TIMER_IX_MASK, ctxt->timer_idx) | - FIELD_SET(CMPL_CTXT_DATA_W0_INT_ST_MASK, ctxt->in_st) | - FIELD_SET(CMPL_CTXT_DATA_W0_COLOR_MASK, ctxt->color) | - FIELD_SET(CMPL_CTXT_DATA_W0_QSIZE_IX_MASK, ctxt->ringsz_idx); - - cmpt_ctxt[num_words_count++] = - FIELD_SET(CMPL_CTXT_DATA_W1_BADDR4_HIGH_L_MASK, baddr4_high_l); - - cmpt_ctxt[num_words_count++] = - FIELD_SET(CMPL_CTXT_DATA_W2_BADDR4_HIGH_H_MASK, baddr4_high_h) | - FIELD_SET(CMPL_CTXT_DATA_W2_DESC_SIZE_MASK, ctxt->desc_sz) | - FIELD_SET(CMPL_CTXT_DATA_W2_PIDX_L_MASK, pidx_l); - - cmpt_ctxt[num_words_count++] = - FIELD_SET(CMPL_CTXT_DATA_W3_PIDX_H_MASK, pidx_h) | - FIELD_SET(CMPL_CTXT_DATA_W3_CIDX_MASK, ctxt->cidx) | - FIELD_SET(CMPL_CTXT_DATA_W3_VALID_MASK, ctxt->valid) | - FIELD_SET(CMPL_CTXT_DATA_W3_ERR_MASK, ctxt->err) | - FIELD_SET(CMPL_CTXT_DATA_W3_USER_TRIG_PEND_MASK, - ctxt->user_trig_pend); - - cmpt_ctxt[num_words_count++] = - FIELD_SET(CMPL_CTXT_DATA_W4_TIMER_RUNNING_MASK, - ctxt->timer_running) | - FIELD_SET(CMPL_CTXT_DATA_W4_FULL_UPD_MASK, ctxt->full_upd) | - FIELD_SET(CMPL_CTXT_DATA_W4_OVF_CHK_DIS_MASK, - ctxt->ovf_chk_dis) | - FIELD_SET(CMPL_CTXT_DATA_W4_AT_MASK, ctxt->at) | - FIELD_SET(CMPL_CTXT_DATA_W4_VEC_MASK, ctxt->vec) | - FIELD_SET(CMPL_CTXT_DATA_W4_INT_AGGR_MASK, ctxt->int_aggr) | - FIELD_SET(CMPL_CTXT_DATA_W4_DIS_INTR_ON_VF_MASK, - ctxt->dis_intr_on_vf) | - FIELD_SET(CMPL_CTXT_DATA_W4_VIO_MASK, ctxt->vio) | - FIELD_SET(CMPL_CTXT_DATA_W4_DIR_C2H_MASK, ctxt->dir_c2h) | - FIELD_SET(CMPL_CTXT_DATA_W4_HOST_ID_MASK, ctxt->host_id) | - FIELD_SET(CMPL_CTXT_DATA_W4_PASID_L_MASK, pasid_l); - - cmpt_ctxt[num_words_count++] = - FIELD_SET(CMPL_CTXT_DATA_W5_PASID_H_MASK, pasid_h) | - FIELD_SET(CMPL_CTXT_DATA_W5_PASID_EN_MASK, - ctxt->pasid_en) | - FIELD_SET(CMPL_CTXT_DATA_W5_BADDR4_LOW_MASK, - baddr4_low) | - FIELD_SET(CMPL_CTXT_DATA_W5_VIO_EOP_MASK, ctxt->vio_eop) | - FIELD_SET(CMPL_CTXT_DATA_W5_SH_CMPT_MASK, ctxt->sh_cmpt); - - return eqdma_indirect_reg_write(dev_hndl, sel, hw_qid, - cmpt_ctxt, num_words_count); -} - -/*****************************************************************************/ -/** - * eqdma_cmpt_context_read() - read completion context - * - * @dev_hndl: device handle - * @hw_qid: hardware qid of the queue - * @ctxt: pointer to the context data - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -static int eqdma_cmpt_context_read(void *dev_hndl, uint16_t hw_qid, - struct qdma_descq_cmpt_ctxt *ctxt) -{ - int rv = QDMA_SUCCESS; - uint32_t cmpt_ctxt[EQDMA_CMPT_CONTEXT_NUM_WORDS] = {0}; - enum ind_ctxt_cmd_sel sel = QDMA_CTXT_SEL_CMPT; - uint32_t baddr4_high_l, baddr4_high_h, baddr4_low, - pidx_l, pidx_h, pasid_l, pasid_h; - - if (!dev_hndl || !ctxt) { - qdma_log_error("%s: dev_handle or cmpt ctxt NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - rv = eqdma_indirect_reg_read(dev_hndl, sel, hw_qid, - EQDMA_CMPT_CONTEXT_NUM_WORDS, cmpt_ctxt); - if (rv < 0) - return rv; - - ctxt->en_stat_desc = - FIELD_GET(CMPL_CTXT_DATA_W0_EN_STAT_DESC_MASK, cmpt_ctxt[0]); - ctxt->en_int = FIELD_GET(CMPL_CTXT_DATA_W0_EN_INT_MASK, cmpt_ctxt[0]); - ctxt->trig_mode = - FIELD_GET(CMPL_CTXT_DATA_W0_TRIG_MODE_MASK, cmpt_ctxt[0]); - ctxt->fnc_id = - (uint8_t)(FIELD_GET(CMPL_CTXT_DATA_W0_FNC_ID_MASK, - cmpt_ctxt[0])); - ctxt->counter_idx = - (uint8_t)(FIELD_GET(CMPL_CTXT_DATA_W0_CNTER_IX_MASK, - cmpt_ctxt[0])); - ctxt->timer_idx = - (uint8_t)(FIELD_GET(CMPL_CTXT_DATA_W0_TIMER_IX_MASK, - cmpt_ctxt[0])); - ctxt->in_st = - (uint8_t)(FIELD_GET(CMPL_CTXT_DATA_W0_INT_ST_MASK, - cmpt_ctxt[0])); - ctxt->color = - (uint8_t)(FIELD_GET(CMPL_CTXT_DATA_W0_COLOR_MASK, - cmpt_ctxt[0])); - ctxt->ringsz_idx = - (uint8_t)(FIELD_GET(CMPL_CTXT_DATA_W0_QSIZE_IX_MASK, - cmpt_ctxt[0])); - - baddr4_high_l = FIELD_GET(CMPL_CTXT_DATA_W1_BADDR4_HIGH_L_MASK, - cmpt_ctxt[1]); - - baddr4_high_h = FIELD_GET(CMPL_CTXT_DATA_W2_BADDR4_HIGH_H_MASK, - cmpt_ctxt[2]); - ctxt->desc_sz = - (uint8_t)(FIELD_GET(CMPL_CTXT_DATA_W2_DESC_SIZE_MASK, - cmpt_ctxt[2])); - pidx_l = FIELD_GET(CMPL_CTXT_DATA_W2_PIDX_L_MASK, cmpt_ctxt[2]); - - pidx_h = FIELD_GET(CMPL_CTXT_DATA_W3_PIDX_H_MASK, cmpt_ctxt[3]); - ctxt->cidx = - (uint16_t)(FIELD_GET(CMPL_CTXT_DATA_W3_CIDX_MASK, - cmpt_ctxt[3])); - ctxt->valid = - (uint8_t)(FIELD_GET(CMPL_CTXT_DATA_W3_VALID_MASK, - cmpt_ctxt[3])); - ctxt->err = - (uint8_t)(FIELD_GET(CMPL_CTXT_DATA_W3_ERR_MASK, - cmpt_ctxt[3])); - ctxt->user_trig_pend = (uint8_t) - (FIELD_GET(CMPL_CTXT_DATA_W3_USER_TRIG_PEND_MASK, - cmpt_ctxt[3])); - - ctxt->timer_running = - FIELD_GET(CMPL_CTXT_DATA_W4_TIMER_RUNNING_MASK, cmpt_ctxt[4]); - ctxt->full_upd = - FIELD_GET(CMPL_CTXT_DATA_W4_FULL_UPD_MASK, cmpt_ctxt[4]); - ctxt->ovf_chk_dis = - FIELD_GET(CMPL_CTXT_DATA_W4_OVF_CHK_DIS_MASK, cmpt_ctxt[4]); - ctxt->at = FIELD_GET(CMPL_CTXT_DATA_W4_AT_MASK, cmpt_ctxt[4]); - ctxt->vec = FIELD_GET(CMPL_CTXT_DATA_W4_VEC_MASK, cmpt_ctxt[4]); - ctxt->int_aggr = (uint8_t) - (FIELD_GET(CMPL_CTXT_DATA_W4_INT_AGGR_MASK, cmpt_ctxt[4])); - ctxt->dis_intr_on_vf = (uint8_t) - FIELD_GET(CMPL_CTXT_DATA_W4_DIS_INTR_ON_VF_MASK, - cmpt_ctxt[4]); - ctxt->vio = (uint8_t)FIELD_GET(CMPL_CTXT_DATA_W4_VIO_MASK, - cmpt_ctxt[4]); - ctxt->dir_c2h = (uint8_t)FIELD_GET(CMPL_CTXT_DATA_W4_DIR_C2H_MASK, - cmpt_ctxt[4]); - ctxt->host_id = (uint8_t)FIELD_GET(CMPL_CTXT_DATA_W4_HOST_ID_MASK, - cmpt_ctxt[4]); - pasid_l = FIELD_GET(CMPL_CTXT_DATA_W4_PASID_L_MASK, cmpt_ctxt[4]); - - pasid_h = (uint32_t)FIELD_GET(CMPL_CTXT_DATA_W5_PASID_H_MASK, - cmpt_ctxt[5]); - ctxt->pasid_en = (uint8_t)FIELD_GET(CMPL_CTXT_DATA_W5_PASID_EN_MASK, - cmpt_ctxt[5]); - baddr4_low = (uint8_t)FIELD_GET( - CMPL_CTXT_DATA_W5_BADDR4_LOW_MASK, cmpt_ctxt[5]); - ctxt->vio_eop = (uint8_t)FIELD_GET(CMPL_CTXT_DATA_W5_VIO_EOP_MASK, - cmpt_ctxt[5]); - ctxt->sh_cmpt = (uint8_t)FIELD_GET(CMPL_CTXT_DATA_W5_SH_CMPT_MASK, - cmpt_ctxt[5]); - - ctxt->bs_addr = - FIELD_SET(EQDMA_COMPL_CTXT_BADDR_HIGH_L_MASK, - (uint64_t)baddr4_high_l) | - FIELD_SET(EQDMA_COMPL_CTXT_BADDR_HIGH_H_MASK, - (uint64_t)baddr4_high_h) | - FIELD_SET(EQDMA_COMPL_CTXT_BADDR_LOW_MASK, - (uint64_t)baddr4_low); - - ctxt->pasid = - FIELD_SET(EQDMA_CMPL_CTXT_PASID_GET_L_MASK, pasid_l) | - FIELD_SET(EQDMA_CMPL_CTXT_PASID_GET_H_MASK, - (uint64_t)pasid_h); - - ctxt->pidx = - FIELD_SET(QDMA_COMPL_CTXT_PIDX_GET_L_MASK, pidx_l) | - FIELD_SET(QDMA_COMPL_CTXT_PIDX_GET_H_MASK, pidx_h); - - return QDMA_SUCCESS; -} - -/*****************************************************************************/ -/** - * eqdma_cmpt_context_clear() - clear completion context - * - * @dev_hndl: device handle - * @hw_qid: hardware qid of the queue - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -static int eqdma_cmpt_context_clear(void *dev_hndl, uint16_t hw_qid) -{ - enum ind_ctxt_cmd_sel sel = QDMA_CTXT_SEL_CMPT; - - if (!dev_hndl) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", __func__, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - return eqdma_indirect_reg_clear(dev_hndl, sel, hw_qid); -} - -/*****************************************************************************/ -/** - * eqdma_cmpt_context_invalidate() - invalidate completion context - * - * @dev_hndl: device handle - * @hw_qid: hardware qid of the queue - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -static int eqdma_cmpt_context_invalidate(void *dev_hndl, uint16_t hw_qid) -{ - enum ind_ctxt_cmd_sel sel = QDMA_CTXT_SEL_CMPT; - - if (!dev_hndl) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", __func__, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - return eqdma_indirect_reg_invalidate(dev_hndl, sel, hw_qid); -} - -/*****************************************************************************/ -/** - * eqdma_cmpt_ctx_conf() - configure completion context - * - * @dev_hndl: device handle - * @hw_qid: hardware qid of the queue - * @ctxt: pointer to context data - * @access_type HW access type (qdma_hw_access_type enum) value - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -int eqdma_cmpt_ctx_conf(void *dev_hndl, uint16_t hw_qid, - struct qdma_descq_cmpt_ctxt *ctxt, - enum qdma_hw_access_type access_type) -{ - int rv = QDMA_SUCCESS; - - switch (access_type) { - case QDMA_HW_ACCESS_READ: - rv = eqdma_cmpt_context_read(dev_hndl, hw_qid, ctxt); - break; - case QDMA_HW_ACCESS_WRITE: - rv = eqdma_cmpt_context_write(dev_hndl, hw_qid, ctxt); - break; - case QDMA_HW_ACCESS_CLEAR: - rv = eqdma_cmpt_context_clear(dev_hndl, hw_qid); - break; - case QDMA_HW_ACCESS_INVALIDATE: - rv = eqdma_cmpt_context_invalidate(dev_hndl, hw_qid); - break; - default: - qdma_log_error("%s: access_type(%d) invalid, err:%d\n", - __func__, - access_type, - -QDMA_ERR_INV_PARAM); - rv = -QDMA_ERR_INV_PARAM; - break; - } - - return rv; -} - -/*****************************************************************************/ -/** - * eqdma_hw_context_read() - read hardware context - * - * @dev_hndl: device handle - * @c2h: is c2h queue - * @hw_qid: hardware qid of the queue - * @ctxt: pointer to the output context data - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -static int eqdma_hw_context_read(void *dev_hndl, uint8_t c2h, - uint16_t hw_qid, struct qdma_descq_hw_ctxt *ctxt) -{ - int rv = QDMA_SUCCESS; - uint32_t hw_ctxt[EQDMA_HW_CONTEXT_NUM_WORDS] = {0}; - enum ind_ctxt_cmd_sel sel = c2h ? QDMA_CTXT_SEL_HW_C2H : - QDMA_CTXT_SEL_HW_H2C; - - if (!dev_hndl || !ctxt) { - qdma_log_error("%s: dev_handle or hw_ctxt NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - rv = eqdma_indirect_reg_read(dev_hndl, sel, hw_qid, - EQDMA_HW_CONTEXT_NUM_WORDS, hw_ctxt); - if (rv < 0) - return rv; - - ctxt->cidx = FIELD_GET(HW_IND_CTXT_DATA_W0_CIDX_MASK, hw_ctxt[0]); - ctxt->crd_use = - (uint16_t)(FIELD_GET(HW_IND_CTXT_DATA_W0_CRD_USE_MASK, - hw_ctxt[0])); - - ctxt->dsc_pend = - (uint8_t)(FIELD_GET(HW_IND_CTXT_DATA_W1_DSC_PND_MASK, - hw_ctxt[1])); - ctxt->idl_stp_b = - (uint8_t)(FIELD_GET(HW_IND_CTXT_DATA_W1_IDL_STP_B_MASK, - hw_ctxt[1])); - ctxt->evt_pnd = - (uint8_t)(FIELD_GET(HW_IND_CTXT_DATA_W1_EVT_PND_MASK, - hw_ctxt[1])); - ctxt->fetch_pnd = (uint8_t) - (FIELD_GET(HW_IND_CTXT_DATA_W1_DSC_PND_MASK, hw_ctxt[1])); - - qdma_log_debug("%s: cidx=%hu, crd_use=%hu, dsc_pend=%x\n", - __func__, ctxt->cidx, ctxt->crd_use, ctxt->dsc_pend); - qdma_log_debug("%s: idl_stp_b=%x, evt_pnd=%x, fetch_pnd=%x\n", - __func__, ctxt->idl_stp_b, ctxt->evt_pnd, - ctxt->fetch_pnd); - - return QDMA_SUCCESS; -} - -/*****************************************************************************/ -/** - * eqdma_hw_context_clear() - clear hardware context - * - * @dev_hndl: device handle - * @c2h: is c2h queue - * @hw_qid: hardware qid of the queue - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -static int eqdma_hw_context_clear(void *dev_hndl, uint8_t c2h, - uint16_t hw_qid) -{ - enum ind_ctxt_cmd_sel sel = c2h ? QDMA_CTXT_SEL_HW_C2H : - QDMA_CTXT_SEL_HW_H2C; - - if (!dev_hndl) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", __func__, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - return eqdma_indirect_reg_clear(dev_hndl, sel, hw_qid); -} - -/*****************************************************************************/ -/** - * eqdma_hw_context_invalidate() - invalidate hardware context - * - * @dev_hndl: device handle - * @c2h: is c2h queue - * @hw_qid: hardware qid of the queue - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -static int eqdma_hw_context_invalidate(void *dev_hndl, uint8_t c2h, - uint16_t hw_qid) -{ - enum ind_ctxt_cmd_sel sel = c2h ? QDMA_CTXT_SEL_HW_C2H : - QDMA_CTXT_SEL_HW_H2C; - - if (!dev_hndl) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", __func__, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - return eqdma_indirect_reg_invalidate(dev_hndl, sel, hw_qid); -} - -/*****************************************************************************/ -/** - * eqdma_hw_ctx_conf() - configure HW context - * - * @dev_hndl: device handle - * @c2h: is c2h queue - * @hw_qid: hardware qid of the queue - * @ctxt: pointer to context data - * @access_type HW access type (qdma_hw_access_type enum) value - * QDMA_HW_ACCESS_WRITE Not supported - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -int eqdma_hw_ctx_conf(void *dev_hndl, uint8_t c2h, uint16_t hw_qid, - struct qdma_descq_hw_ctxt *ctxt, - enum qdma_hw_access_type access_type) -{ - int rv = QDMA_SUCCESS; - - /** ctxt requires only H2C-0 or C2H-1 - * return error for any other values - */ - if (c2h > 1) { - qdma_log_error("%s: c2h(%d) invalid, err:%d\n", - __func__, - c2h, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - switch (access_type) { - case QDMA_HW_ACCESS_READ: - rv = eqdma_hw_context_read(dev_hndl, c2h, hw_qid, ctxt); - break; - case QDMA_HW_ACCESS_CLEAR: - rv = eqdma_hw_context_clear(dev_hndl, c2h, hw_qid); - break; - case QDMA_HW_ACCESS_INVALIDATE: - rv = eqdma_hw_context_invalidate(dev_hndl, c2h, hw_qid); - break; - case QDMA_HW_ACCESS_WRITE: - default: - qdma_log_error("%s: access_type=%d is invalid, err:%d\n", - __func__, access_type, - -QDMA_ERR_INV_PARAM); - rv = -QDMA_ERR_INV_PARAM; - break; - } - - return rv; -} - -/*****************************************************************************/ -/** - * eqdma_credit_context_read() - read credit context - * - * @dev_hndl: device handle - * @c2h: is c2h queue - * @hw_qid: hardware qid of the queue - * @ctxt: pointer to the context data - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -static int eqdma_credit_context_read(void *dev_hndl, uint8_t c2h, - uint16_t hw_qid, - struct qdma_descq_credit_ctxt *ctxt) -{ - int rv = QDMA_SUCCESS; - uint32_t cr_ctxt[EQDMA_CR_CONTEXT_NUM_WORDS] = {0}; - enum ind_ctxt_cmd_sel sel = c2h ? QDMA_CTXT_SEL_CR_C2H : - QDMA_CTXT_SEL_CR_H2C; - - if (!dev_hndl || !ctxt) { - qdma_log_error("%s: dev_hndl=%p credit_ctxt=%p, err:%d\n", - __func__, dev_hndl, ctxt, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - rv = eqdma_indirect_reg_read(dev_hndl, sel, hw_qid, - EQDMA_CR_CONTEXT_NUM_WORDS, cr_ctxt); - if (rv < 0) - return rv; - - ctxt->credit = FIELD_GET(CRED_CTXT_DATA_W0_CREDT_MASK, cr_ctxt[0]); - - qdma_log_debug("%s: credit=%u\n", __func__, ctxt->credit); - - return QDMA_SUCCESS; -} - -/*****************************************************************************/ -/** - * eqdma_credit_context_clear() - clear credit context - * - * @dev_hndl: device handle - * @c2h: is c2h queue - * @hw_qid: hardware qid of the queue - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -static int eqdma_credit_context_clear(void *dev_hndl, uint8_t c2h, - uint16_t hw_qid) -{ - enum ind_ctxt_cmd_sel sel = c2h ? QDMA_CTXT_SEL_CR_C2H : - QDMA_CTXT_SEL_CR_H2C; - - if (!dev_hndl) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", __func__, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - return eqdma_indirect_reg_clear(dev_hndl, sel, hw_qid); -} - -/*****************************************************************************/ -/** - * eqdma_credit_context_invalidate() - invalidate credit context - * - * @dev_hndl: device handle - * @c2h: is c2h queue - * @hw_qid: hardware qid of the queue - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -static int eqdma_credit_context_invalidate(void *dev_hndl, uint8_t c2h, - uint16_t hw_qid) -{ - enum ind_ctxt_cmd_sel sel = c2h ? QDMA_CTXT_SEL_CR_C2H : - QDMA_CTXT_SEL_CR_H2C; - - if (!dev_hndl) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", __func__, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - return eqdma_indirect_reg_invalidate(dev_hndl, sel, hw_qid); -} - -/*****************************************************************************/ -/** - * eqdma_credit_ctx_conf() - configure credit context - * - * @dev_hndl: device handle - * @c2h: is c2h queue - * @hw_qid: hardware qid of the queue - * @ctxt: pointer to the context data - * @access_type HW access type (qdma_hw_access_type enum) value - * QDMA_HW_ACCESS_WRITE Not supported - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -int eqdma_credit_ctx_conf(void *dev_hndl, uint8_t c2h, - uint16_t hw_qid, struct qdma_descq_credit_ctxt *ctxt, - enum qdma_hw_access_type access_type) -{ - int rv = QDMA_SUCCESS; - - /** ctxt requires only H2C-0 or C2H-1 - * return error for any other values - */ - if (c2h > 1) { - qdma_log_error("%s: c2h(%d) invalid, err:%d\n", - __func__, - c2h, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - switch (access_type) { - case QDMA_HW_ACCESS_READ: - rv = eqdma_credit_context_read(dev_hndl, c2h, hw_qid, ctxt); - break; - case QDMA_HW_ACCESS_CLEAR: - rv = eqdma_credit_context_clear(dev_hndl, c2h, hw_qid); - break; - case QDMA_HW_ACCESS_INVALIDATE: - rv = eqdma_credit_context_invalidate(dev_hndl, c2h, hw_qid); - break; - case QDMA_HW_ACCESS_WRITE: - default: - qdma_log_error("%s: Invalid access type=%d, err:%d\n", - __func__, access_type, - -QDMA_ERR_INV_PARAM); - rv = -QDMA_ERR_INV_PARAM; - break; - } - - return rv; -} - -/*****************************************************************************/ -/** - * eqdma_fmap_context_write() - create fmap context and program it - * - * @dev_hndl: device handle - * @func_id: function id of the device - * @config: pointer to the fmap data strucutre - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -static int eqdma_fmap_context_write(void *dev_hndl, uint16_t func_id, - const struct qdma_fmap_cfg *config) -{ - uint32_t fmap[EQDMA_FMAP_NUM_WORDS] = {0}; - uint16_t num_words_count = 0; - enum ind_ctxt_cmd_sel sel = QDMA_CTXT_SEL_FMAP; - - if (!dev_hndl || !config) { - qdma_log_error("%s: dev_handle=%p fmap=%p NULL, err:%d\n", - __func__, dev_hndl, config, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - qdma_log_debug("%s: func_id=%hu, qbase=%hu, qmax=%hu\n", __func__, - func_id, config->qbase, config->qmax); - fmap[num_words_count++] = - FIELD_SET(EQDMA_FMAP_CTXT_W0_QID_MASK, config->qbase); - fmap[num_words_count++] = - FIELD_SET(EQDMA_FMAP_CTXT_W1_QID_MAX_MASK, config->qmax); - - return eqdma_indirect_reg_write(dev_hndl, sel, func_id, - fmap, num_words_count); -} - -/*****************************************************************************/ -/** - * eqdma_fmap_context_read() - read fmap context - * - * @dev_hndl: device handle - * @func_id: function id of the device - * @config: pointer to the output fmap data - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -static int eqdma_fmap_context_read(void *dev_hndl, uint16_t func_id, - struct qdma_fmap_cfg *config) -{ - int rv = QDMA_SUCCESS; - uint32_t fmap[EQDMA_FMAP_NUM_WORDS] = {0}; - enum ind_ctxt_cmd_sel sel = QDMA_CTXT_SEL_FMAP; - - if (!dev_hndl || !config) { - qdma_log_error("%s: dev_handle=%p fmap=%p NULL, err:%d\n", - __func__, dev_hndl, config, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - rv = eqdma_indirect_reg_read(dev_hndl, sel, func_id, - EQDMA_FMAP_NUM_WORDS, fmap); - if (rv < 0) - return rv; - - config->qbase = FIELD_GET(EQDMA_FMAP_CTXT_W0_QID_MASK, fmap[0]); - config->qmax = FIELD_GET(EQDMA_FMAP_CTXT_W1_QID_MAX_MASK, fmap[1]); - - qdma_log_debug("%s: func_id=%hu, qbase=%hu, qmax=%hu\n", __func__, - func_id, config->qbase, config->qmax); - - return QDMA_SUCCESS; -} - -/*****************************************************************************/ -/** - * eqdma_fmap_context_clear() - clear fmap context - * - * @dev_hndl: device handle - * @func_id: function id of the device - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -static int eqdma_fmap_context_clear(void *dev_hndl, uint16_t func_id) -{ - enum ind_ctxt_cmd_sel sel = QDMA_CTXT_SEL_FMAP; - - if (!dev_hndl) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", __func__, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - qdma_log_debug("%s: func_id=%hu\n", __func__, func_id); - return eqdma_indirect_reg_clear(dev_hndl, sel, func_id); -} - -/*****************************************************************************/ -/** - * eqdma_fmap_conf() - configure fmap context - * - * @dev_hndl: device handle - * @func_id: function id of the device - * @config: pointer to the fmap data - * @access_type HW access type (qdma_hw_access_type enum) value - * QDMA_HW_ACCESS_INVALIDATE Not supported - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -int eqdma_fmap_conf(void *dev_hndl, uint16_t func_id, - struct qdma_fmap_cfg *config, - enum qdma_hw_access_type access_type) -{ - int rv = QDMA_SUCCESS; - - switch (access_type) { - case QDMA_HW_ACCESS_READ: - rv = eqdma_fmap_context_read(dev_hndl, func_id, config); - break; - case QDMA_HW_ACCESS_WRITE: - rv = eqdma_fmap_context_write(dev_hndl, func_id, config); - break; - case QDMA_HW_ACCESS_CLEAR: - rv = eqdma_fmap_context_clear(dev_hndl, func_id); - break; - case QDMA_HW_ACCESS_INVALIDATE: - default: - qdma_log_error("%s: access_type(%d) invalid, err:%d\n", - __func__, - access_type, - -QDMA_ERR_INV_PARAM); - rv = -QDMA_ERR_INV_PARAM; - break; - } - - return rv; -} - -/*****************************************************************************/ -/** - * eqdma_indirect_intr_context_write() - create indirect interrupt context - * and program it - * - * @dev_hndl: device handle - * @ring_index: indirect interrupt ring index - * @ctxt: pointer to the interrupt context data strucutre - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -static int eqdma_indirect_intr_context_write(void *dev_hndl, - uint16_t ring_index, const struct qdma_indirect_intr_ctxt *ctxt) -{ - uint32_t intr_ctxt[EQDMA_IND_INTR_CONTEXT_NUM_WORDS] = {0}; - enum ind_ctxt_cmd_sel sel = QDMA_CTXT_SEL_INT_COAL; - uint32_t baddr_l, baddr_m, baddr_h, pasid_l, pasid_h; - uint16_t num_words_count = 0; - - if (!dev_hndl || !ctxt) { - qdma_log_error("%s: dev_hndl=%p intr_ctxt=%p, err:%d\n", - __func__, dev_hndl, ctxt, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - baddr_l = (uint32_t)FIELD_GET(QDMA_INTR_CTXT_BADDR_GET_L_MASK, - ctxt->baddr_4k); - baddr_m = (uint32_t)FIELD_GET(QDMA_INTR_CTXT_BADDR_GET_M_MASK, - ctxt->baddr_4k); - baddr_h = (uint32_t)FIELD_GET(QDMA_INTR_CTXT_BADDR_GET_H_MASK, - ctxt->baddr_4k); - - pasid_l = - FIELD_GET(EQDMA_INTR_CTXT_PASID_GET_L_MASK, ctxt->pasid); - pasid_h = - FIELD_GET(EQDMA_INTR_CTXT_PASID_GET_H_MASK, ctxt->pasid); - - intr_ctxt[num_words_count++] = - FIELD_SET(INTR_CTXT_DATA_W0_VALID_MASK, ctxt->valid) | - FIELD_SET(INTR_CTXT_DATA_W0_VEC_MASK, ctxt->vec) | - FIELD_SET(INTR_CTXT_DATA_W0_INT_ST_MASK, ctxt->int_st) | - FIELD_SET(INTR_CTXT_DATA_W0_COLOR_MASK, ctxt->color) | - FIELD_SET(INTR_CTXT_DATA_W0_BADDR_4K_L_MASK, baddr_l); - - intr_ctxt[num_words_count++] = - FIELD_SET(INTR_CTXT_DATA_W1_BADDR_4K_M_MASK, baddr_m); - - intr_ctxt[num_words_count++] = - FIELD_SET(INTR_CTXT_DATA_W2_BADDR_4K_H_MASK, baddr_h) | - FIELD_SET(INTR_CTXT_DATA_W2_PAGE_SIZE_MASK, ctxt->page_size) | - FIELD_SET(INTR_CTXT_DATA_W2_PIDX_MASK, ctxt->pidx) | - FIELD_SET(INTR_CTXT_DATA_W2_AT_MASK, ctxt->at) | - FIELD_SET(INTR_CTXT_DATA_W2_HOST_ID_MASK, ctxt->host_id) | - FIELD_SET(INTR_CTXT_DATA_W2_PASID_L_MASK, pasid_l); - - intr_ctxt[num_words_count++] = - FIELD_SET(INTR_CTXT_DATA_W3_PASID_H_MASK, pasid_h) | - FIELD_SET(INTR_CTXT_DATA_W3_PASID_EN_MASK, ctxt->pasid_en) | - FIELD_SET(INTR_CTXT_DATA_W3_FUNC_MASK, ctxt->func_id); - - return eqdma_indirect_reg_write(dev_hndl, sel, ring_index, - intr_ctxt, num_words_count); -} - -/*****************************************************************************/ -/** - * eqdma_indirect_intr_context_read() - read indirect interrupt context - * - * @dev_hndl: device handle - * @ring_index: indirect interrupt ring index - * @ctxt: pointer to the output context data - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -static int eqdma_indirect_intr_context_read(void *dev_hndl, - uint16_t ring_index, struct qdma_indirect_intr_ctxt *ctxt) -{ - int rv = QDMA_SUCCESS; - uint32_t intr_ctxt[EQDMA_IND_INTR_CONTEXT_NUM_WORDS] = {0}; - enum ind_ctxt_cmd_sel sel = QDMA_CTXT_SEL_INT_COAL; - uint64_t baddr_l, baddr_m, baddr_h, pasid_l, pasid_h; - - if (!dev_hndl || !ctxt) { - qdma_log_error("%s: dev_hndl=%p intr_ctxt=%p, err:%d\n", - __func__, dev_hndl, ctxt, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - rv = eqdma_indirect_reg_read(dev_hndl, sel, ring_index, - EQDMA_IND_INTR_CONTEXT_NUM_WORDS, intr_ctxt); - if (rv < 0) - return rv; - - ctxt->valid = FIELD_GET(INTR_CTXT_DATA_W0_VALID_MASK, intr_ctxt[0]); - ctxt->vec = FIELD_GET(INTR_CTXT_DATA_W0_VEC_MASK, intr_ctxt[0]); - ctxt->int_st = - (uint8_t)(FIELD_GET(INTR_CTXT_DATA_W0_INT_ST_MASK, - intr_ctxt[0])); - ctxt->color = - (uint8_t)(FIELD_GET(INTR_CTXT_DATA_W0_COLOR_MASK, - intr_ctxt[0])); - baddr_l = FIELD_GET(INTR_CTXT_DATA_W0_BADDR_4K_L_MASK, intr_ctxt[0]); - - baddr_m = FIELD_GET(INTR_CTXT_DATA_W1_BADDR_4K_M_MASK, intr_ctxt[1]); - - baddr_h = FIELD_GET(INTR_CTXT_DATA_W2_BADDR_4K_H_MASK, intr_ctxt[2]); - ctxt->page_size = - FIELD_GET(INTR_CTXT_DATA_W2_PAGE_SIZE_MASK, intr_ctxt[2]); - ctxt->pidx = - (uint16_t)(FIELD_GET(INTR_CTXT_DATA_W2_PIDX_MASK, - intr_ctxt[2])); - ctxt->at = - (uint8_t)(FIELD_GET(INTR_CTXT_DATA_W2_AT_MASK, intr_ctxt[2])); - ctxt->host_id = (uint8_t)(FIELD_GET(INTR_CTXT_DATA_W2_HOST_ID_MASK, - intr_ctxt[2])); - pasid_l = (uint8_t)(FIELD_GET(INTR_CTXT_DATA_W2_PASID_L_MASK, - intr_ctxt[2])); - - pasid_h = FIELD_GET(INTR_CTXT_DATA_W3_PASID_H_MASK, intr_ctxt[3]); - ctxt->pasid_en = (uint8_t)FIELD_GET(INTR_CTXT_DATA_W3_PASID_EN_MASK, - intr_ctxt[3]); - - ctxt->func_id = (uint16_t)FIELD_GET(INTR_CTXT_DATA_W3_FUNC_MASK, - intr_ctxt[3]); - - ctxt->baddr_4k = - FIELD_SET(QDMA_INTR_CTXT_BADDR_GET_L_MASK, baddr_l) | - FIELD_SET(QDMA_INTR_CTXT_BADDR_GET_M_MASK, baddr_m) | - FIELD_SET(QDMA_INTR_CTXT_BADDR_GET_H_MASK, baddr_h); - - ctxt->pasid = - FIELD_SET(EQDMA_INTR_CTXT_PASID_GET_L_MASK, pasid_l) | - FIELD_SET(EQDMA_INTR_CTXT_PASID_GET_H_MASK, pasid_h); - - return QDMA_SUCCESS; -} - -/*****************************************************************************/ -/** - * eqdma_indirect_intr_context_clear() - clear indirect interrupt context - * - * @dev_hndl: device handle - * @ring_index: indirect interrupt ring index - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -static int eqdma_indirect_intr_context_clear(void *dev_hndl, - uint16_t ring_index) -{ - enum ind_ctxt_cmd_sel sel = QDMA_CTXT_SEL_INT_COAL; - - if (!dev_hndl) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", __func__, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - return eqdma_indirect_reg_clear(dev_hndl, sel, ring_index); -} - -/*****************************************************************************/ -/** - * eqdma_indirect_intr_context_invalidate() - invalidate indirect interrupt - * context - * - * @dev_hndl: device handle - * @ring_index: indirect interrupt ring index - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -static int eqdma_indirect_intr_context_invalidate(void *dev_hndl, - uint16_t ring_index) -{ - enum ind_ctxt_cmd_sel sel = QDMA_CTXT_SEL_INT_COAL; - - if (!dev_hndl) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", __func__, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - return eqdma_indirect_reg_invalidate(dev_hndl, sel, ring_index); -} - -/*****************************************************************************/ -/** - * eqdma_indirect_intr_ctx_conf() - configure indirect interrupt context - * - * @dev_hndl: device handle - * @ring_index: indirect interrupt ring index - * @ctxt: pointer to context data - * @access_type HW access type (qdma_hw_access_type enum) value - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -int eqdma_indirect_intr_ctx_conf(void *dev_hndl, uint16_t ring_index, - struct qdma_indirect_intr_ctxt *ctxt, - enum qdma_hw_access_type access_type) -{ - int rv = QDMA_SUCCESS; - - switch (access_type) { - case QDMA_HW_ACCESS_READ: - rv = eqdma_indirect_intr_context_read(dev_hndl, ring_index, - ctxt); - break; - case QDMA_HW_ACCESS_WRITE: - rv = eqdma_indirect_intr_context_write(dev_hndl, ring_index, - ctxt); - break; - case QDMA_HW_ACCESS_CLEAR: - rv = eqdma_indirect_intr_context_clear(dev_hndl, - ring_index); - break; - case QDMA_HW_ACCESS_INVALIDATE: - rv = eqdma_indirect_intr_context_invalidate(dev_hndl, - ring_index); - break; - default: - qdma_log_error("%s: access_type=%d is invalid, err:%d\n", - __func__, access_type, - -QDMA_ERR_INV_PARAM); - rv = -QDMA_ERR_INV_PARAM; - break; - } - - return rv; -} - -/*****************************************************************************/ -/** - * eqdma_dump_config_regs() - Function to get qdma config register dump in a - * buffer - * - * @dev_hndl: device handle - * @is_vf: Whether PF or VF - * @buf : pointer to buffer to be filled - * @buflen : Length of the buffer - * - * Return: Length up-till the buffer is filled -success and < 0 - failure - *****************************************************************************/ -int eqdma_dump_config_regs(void *dev_hndl, uint8_t is_vf, - char *buf, uint32_t buflen) -{ - uint32_t i = 0, j = 0; - struct xreg_info *reg_info; - uint32_t num_regs = eqdma_config_num_regs_get(); - uint32_t len = 0, val = 0; - int rv = QDMA_SUCCESS; - char name[DEBGFS_GEN_NAME_SZ] = ""; - struct qdma_dev_attributes dev_cap; - - if (!dev_hndl) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - if (buflen < eqdma_reg_dump_buf_len()) { - qdma_log_error("%s: Buffer too small, err:%d\n", - __func__, -QDMA_ERR_NO_MEM); - return -QDMA_ERR_NO_MEM; - } - - if (is_vf) { - qdma_log_error("%s: Wrong API used for VF, err:%d\n", - __func__, - -QDMA_ERR_HWACC_FEATURE_NOT_SUPPORTED); - return -QDMA_ERR_HWACC_FEATURE_NOT_SUPPORTED; - } - - eqdma_get_device_attributes(dev_hndl, &dev_cap); - - reg_info = eqdma_config_regs_get(); - - for (i = 0; i < num_regs; i++) { - if ((GET_CAPABILITY_MASK(dev_cap.mm_en, dev_cap.st_en, - dev_cap.mm_cmpt_en, dev_cap.mailbox_en) - & reg_info[i].mode) == 0) - continue; - - /* If Debug Mode not enabled and the current register - * is debug register, skip reading it. - */ - if (dev_cap.debug_mode == 0 && - reg_info[i].is_debug_reg == 1) - continue; - - for (j = 0; j < reg_info[i].repeat; j++) { - rv = QDMA_SNPRINTF_S(name, DEBGFS_GEN_NAME_SZ, - DEBGFS_GEN_NAME_SZ, - "%s", reg_info[i].name); - if ((rv < 0) || (rv > DEBGFS_GEN_NAME_SZ)) { - qdma_log_error( - "%d:%s QDMA_SNPRINTF_S() failed, err:%d\n", - __LINE__, __func__, - rv); - return -QDMA_ERR_NO_MEM; - } - val = qdma_reg_read(dev_hndl, - (reg_info[i].addr + (j * 4))); - rv = dump_reg(buf + len, buflen - len, - (reg_info[i].addr + (j * 4)), - name, val); - if (rv < 0) { - qdma_log_error( - "%s Buff too small, err:%d\n", - __func__, - -QDMA_ERR_NO_MEM); - return -QDMA_ERR_NO_MEM; - } - len += rv; - } - } - - return len; -} - -/*****************************************************************************/ -/** - * qdma_dump_cpm_queue_context() - Function to get qdma queue context dump - * in a buffer - * - * @dev_hndl: device handle - * @st: Queue Mode(ST or MM) - * @q_type: Queue type(H2C/C2H/CMPT) - * @context: Queue Context - * @buf : pointer to buffer to be filled - * @buflen : Length of the buffer - * - * Return: Length up-till the buffer is filled -success and < 0 - failure - *****************************************************************************/ -int eqdma_dump_queue_context(void *dev_hndl, - uint8_t st, - enum qdma_dev_q_type q_type, - struct qdma_descq_context *ctxt_data, - char *buf, uint32_t buflen) -{ - int rv = 0; - uint32_t req_buflen = 0; - - if (!dev_hndl) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - - return -QDMA_ERR_INV_PARAM; - } - - if (!ctxt_data) { - qdma_log_error("%s: ctxt_data is NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - - return -QDMA_ERR_INV_PARAM; - } - - if (!buf) { - qdma_log_error("%s: buf is NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - - return -QDMA_ERR_INV_PARAM; - } - - if (q_type >= QDMA_DEV_Q_TYPE_MAX) { - qdma_log_error("%s: invalid q_type, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - - return -QDMA_ERR_INV_PARAM; - } - - rv = eqdma_context_buf_len(st, q_type, &req_buflen); - if (rv != QDMA_SUCCESS) - return rv; - - if (buflen < req_buflen) { - qdma_log_error("%s: Too small buffer(%d), reqd(%d), err:%d\n", - __func__, buflen, req_buflen, -QDMA_ERR_NO_MEM); - return -QDMA_ERR_NO_MEM; - } - - rv = dump_eqdma_context(ctxt_data, st, q_type, - buf, buflen); - - return rv; -} - -/*****************************************************************************/ -/** - * eqdma_dump_intr_context() - Function to get qdma interrupt context dump - * in a buffer - * - * @dev_hndl: device handle - * @intr_ctx: Interrupt Context - * @ring_index: Ring index - * @buf : pointer to buffer to be filled - * @buflen : Length of the buffer - * - * Return: Length up-till the buffer is filled -success and < 0 - failure - *****************************************************************************/ -int eqdma_dump_intr_context(void *dev_hndl, - struct qdma_indirect_intr_ctxt *intr_ctx, - int ring_index, - char *buf, uint32_t buflen) -{ - int rv = 0; - uint32_t req_buflen = 0; - - if (!dev_hndl) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - - return -QDMA_ERR_INV_PARAM; - } - if (!intr_ctx) { - qdma_log_error("%s: intr_ctx is NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - if (!buf) { - qdma_log_error("%s: buf is NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - req_buflen = eqdma_intr_context_buf_len(); - if (buflen < req_buflen) { - qdma_log_error("%s: Too small buffer(%d), reqd(%d), err:%d\n", - __func__, buflen, req_buflen, -QDMA_ERR_NO_MEM); - return -QDMA_ERR_NO_MEM; - } - - rv = dump_eqdma_intr_context(intr_ctx, ring_index, buf, buflen); - - return rv; -} - -/*****************************************************************************/ -/** - * eqdma_read_dump_queue_context() - Function to read and dump the queue - * context in a buffer - * - * @dev_hndl: device handle - * @func_id: function id - * @hw_qid: queue id - * @st: Queue Mode(ST or MM) - * @q_type: Queue type(H2C/C2H/CMPT) - * @buf : pointer to buffer to be filled - * @buflen : Length of the buffer - * - * Return: Length up-till the buffer is filled -success and < 0 - failure - *****************************************************************************/ -int eqdma_read_dump_queue_context(void *dev_hndl, - uint16_t func_id, - uint16_t qid_hw, - uint8_t st, - enum qdma_dev_q_type q_type, - char *buf, uint32_t buflen) -{ - int rv = QDMA_SUCCESS; - uint32_t req_buflen = 0; - struct qdma_descq_context context; - - if (!dev_hndl) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - - return -QDMA_ERR_INV_PARAM; - } - - if (!buf) { - qdma_log_error("%s: buf is NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - - return -QDMA_ERR_INV_PARAM; - } - - if (q_type >= QDMA_DEV_Q_TYPE_MAX) { - qdma_log_error("%s: Not supported for q_type, err = %d\n", - __func__, -QDMA_ERR_INV_PARAM); - - return -QDMA_ERR_INV_PARAM; - } - - rv = eqdma_context_buf_len(st, q_type, &req_buflen); - if (rv != QDMA_SUCCESS) - return rv; - - if (buflen < req_buflen) { - qdma_log_error("%s: Too small buffer(%d), reqd(%d), err:%d\n", - __func__, buflen, req_buflen, -QDMA_ERR_NO_MEM); - return -QDMA_ERR_NO_MEM; - } - - qdma_memset(&context, 0, sizeof(struct qdma_descq_context)); - - if (q_type != QDMA_DEV_Q_TYPE_CMPT) { - rv = eqdma_sw_ctx_conf(dev_hndl, (uint8_t)q_type, qid_hw, - &(context.sw_ctxt), QDMA_HW_ACCESS_READ); - if (rv < 0) { - qdma_log_error( - "%s: Failed to read sw context, err = %d", - __func__, rv); - return rv; - } - - rv = eqdma_hw_ctx_conf(dev_hndl, (uint8_t)q_type, qid_hw, - &(context.hw_ctxt), QDMA_HW_ACCESS_READ); - if (rv < 0) { - qdma_log_error( - "%s: Failed to read hw context, err = %d", - __func__, rv); - return rv; - } - - rv = eqdma_credit_ctx_conf(dev_hndl, (uint8_t)q_type, - qid_hw, &(context.cr_ctxt), - QDMA_HW_ACCESS_READ); - if (rv < 0) { - qdma_log_error( - "%s: Failed to read credit context, err = %d", - __func__, rv); - return rv; - } - - if (st && (q_type == QDMA_DEV_Q_TYPE_C2H)) { - rv = eqdma_pfetch_ctx_conf(dev_hndl, - qid_hw, - &(context.pfetch_ctxt), - QDMA_HW_ACCESS_READ); - if (rv < 0) { - qdma_log_error( - "%s: Failed to read pftech context, err = %d", - __func__, rv); - return rv; - } - } - } - - if ((st && (q_type == QDMA_DEV_Q_TYPE_C2H)) || - (!st && (q_type == QDMA_DEV_Q_TYPE_CMPT))) { - rv = eqdma_cmpt_ctx_conf(dev_hndl, qid_hw, - &(context.cmpt_ctxt), - QDMA_HW_ACCESS_READ); - if (rv < 0) { - qdma_log_error( - "%s: Failed to read cmpt context, err = %d", - __func__, rv); - return rv; - } - } - - rv = eqdma_fmap_conf(dev_hndl, func_id, - &(context.fmap), QDMA_HW_ACCESS_READ); - if (rv < 0) { - qdma_log_error( - "%s: Failed to read fmap context, err = %d", - __func__, rv); - return rv; - } - - rv = dump_eqdma_context(&context, st, q_type, - buf, buflen); - - return rv; -} - -/*****************************************************************************/ -/** - * eqdma_get_user_bar() - Function to get the AXI Master Lite(user bar) number - * - * @dev_hndl: device handle - * @is_vf: Whether PF or VF - * @func_id: function id of the PF - * @user_bar: pointer to hold the AXI Master Lite bar number - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -int eqdma_get_user_bar(void *dev_hndl, uint8_t is_vf, - uint16_t func_id, uint8_t *user_bar) -{ - uint8_t bar_found = 0; - uint8_t bar_idx = 0; - uint32_t user_bar_id = 0; - uint32_t reg_addr = (is_vf) ? EQDMA_OFFSET_VF_USER_BAR : - EQDMA_OFFSET_GLBL2_PF_BARLITE_EXT; - - if (!dev_hndl) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - if (!user_bar) { - qdma_log_error("%s: AXI Master Lite bar is NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - user_bar_id = qdma_reg_read(dev_hndl, reg_addr); - user_bar_id = (user_bar_id >> (6 * func_id)) & 0x3F; - - for (bar_idx = 0; bar_idx < QDMA_BAR_NUM; bar_idx++) { - if (user_bar_id & (1 << bar_idx)) { - *user_bar = bar_idx; - bar_found = 1; - break; - } - } - if (bar_found == 0) { - *user_bar = 0; - qdma_log_error("%s: Bar not found, err:%d\n", - __func__, - -QDMA_ERR_HWACC_BAR_NOT_FOUND); - return -QDMA_ERR_HWACC_BAR_NOT_FOUND; - } - - return QDMA_SUCCESS; -} - -/*****************************************************************************/ -/** - * eqdma_hw_ram_sbe_err_process() - Function to dump SBE error debug information - * - * @dev_hndl: device handle - * @buf: Bufffer for the debug info to be dumped in - * @buflen: Length of the buffer - * - * Return: void - *****************************************************************************/ -static void eqdma_hw_ram_sbe_err_process(void *dev_hndl) -{ - eqdma_dump_reg_info(dev_hndl, EQDMA_RAM_SBE_STS_A_ADDR, - 1, NULL, 0); - eqdma_dump_reg_info(dev_hndl, EQDMA_RAM_SBE_STS_1_A_ADDR, - 1, NULL, 0); -} - -/*****************************************************************************/ -/** - * eqdma_hw_ram_dbe_err_process() - Function to dump DBE error debug information - * - * @dev_hndl: device handle - * @buf: Bufffer for the debug info to be dumped in - * @buflen: Length of the buffer - * - * Return: void - *****************************************************************************/ -static void eqdma_hw_ram_dbe_err_process(void *dev_hndl) -{ - eqdma_dump_reg_info(dev_hndl, EQDMA_RAM_DBE_STS_A_ADDR, - 1, NULL, 0); - eqdma_dump_reg_info(dev_hndl, EQDMA_RAM_DBE_STS_1_A_ADDR, - 1, NULL, 0); -} - -/*****************************************************************************/ -/** - * eqdma_hw_desc_err_process() - Function to dump Descriptor Error information - * - * @dev_hndl: device handle - * @buf: Bufffer for the debug info to be dumped in - * @buflen: Length of the buffer - * - * Return: void - *****************************************************************************/ -static void eqdma_hw_desc_err_process(void *dev_hndl) -{ - int i = 0; - uint32_t desc_err_reg_list[] = { - EQDMA_GLBL_DSC_ERR_STS_ADDR, - EQDMA_GLBL_DSC_ERR_LOG0_ADDR, - EQDMA_GLBL_DSC_ERR_LOG1_ADDR, - EQDMA_GLBL_DSC_DBG_DAT0_ADDR, - EQDMA_GLBL_DSC_DBG_DAT1_ADDR, - EQDMA_GLBL_DSC_ERR_LOG2_ADDR - }; - int desc_err_num_regs = sizeof(desc_err_reg_list)/sizeof(uint32_t); - - for (i = 0; i < desc_err_num_regs; i++) { - eqdma_dump_reg_info(dev_hndl, desc_err_reg_list[i], - 1, NULL, 0); - } -} - -/*****************************************************************************/ -/** - * eqdma_hw_trq_err_process() - Function to dump Target Access Error information - * - * @dev_hndl: device handle - * @buf: Bufffer for the debug info to be dumped in - * @buflen: Length of the buffer - * - * Return: void - *****************************************************************************/ -static void eqdma_hw_trq_err_process(void *dev_hndl) -{ - int i = 0; - uint32_t trq_err_reg_list[] = { - EQDMA_GLBL_TRQ_ERR_STS_ADDR, - EQDMA_GLBL_TRQ_ERR_LOG_ADDR - }; - int trq_err_reg_num_regs = sizeof(trq_err_reg_list)/sizeof(uint32_t); - - for (i = 0; i < trq_err_reg_num_regs; i++) { - eqdma_dump_reg_info(dev_hndl, trq_err_reg_list[i], - 1, NULL, 0); - } -} - -/*****************************************************************************/ -/** - * eqdma_hw_err_dump_ctxt_info() - Dump the imp ctxt fields on HW error - * - * @dev_hndl: device handle - * @first_err_qid: First Error QID - * @en_st: ST Mode or MM Mode enabled - * @c2h: C2H or H2C Mode - * - * Return: void - *****************************************************************************/ -static void eqdma_hw_err_dump_ctxt_info(void *dev_hndl, - uint32_t first_err_qid_reg, - uint8_t en_st, uint8_t c2h) -{ - uint16_t first_err_qid = 0; - struct qdma_descq_sw_ctxt sw_ctxt; - struct qdma_descq_hw_ctxt hw_ctxt; - struct qdma_descq_cmpt_ctxt cmpt_ctxt; - - first_err_qid = qdma_reg_read(dev_hndl, first_err_qid_reg); - - eqdma_sw_context_read(dev_hndl, c2h, first_err_qid, &sw_ctxt); - eqdma_hw_context_read(dev_hndl, c2h, first_err_qid, &hw_ctxt); - eqdma_fill_sw_ctxt(&sw_ctxt); - eqdma_fill_hw_ctxt(&hw_ctxt); - - if (sw_ctxt.pidx != hw_ctxt.cidx) { - qdma_log_info("\n%40s\n", "SW Context:"); - /** SW Context: PIDX ***/ - qdma_log_info("%-47s %#-10x %u\n", - eqdma_sw_ctxt_entries[0].name, - eqdma_sw_ctxt_entries[0].value, - eqdma_sw_ctxt_entries[0].value); - qdma_log_info("\n%40s\n", "HW Context:"); - /*** HW Context: CIDX ***/ - qdma_log_info("%-47s %#-10x %u\n", - eqdma_hw_ctxt_entries[0].name, - eqdma_hw_ctxt_entries[0].value, - eqdma_hw_ctxt_entries[0].value); - } - - if (sw_ctxt.err != 0) { - /*** SW Context: ERR ***/ - qdma_log_info("%-47s %#-10x %u\n", - eqdma_sw_ctxt_entries[17].name, - eqdma_sw_ctxt_entries[17].value, - eqdma_sw_ctxt_entries[17].value); - } - - /*** SW Context: ERR WB SENT***/ - qdma_log_info("%-47s %#-10x %u\n", - eqdma_sw_ctxt_entries[18].name, - eqdma_sw_ctxt_entries[18].value, - eqdma_sw_ctxt_entries[18].value); - - /*** SW Context: IRQ REQ***/ - qdma_log_info("%-47s %#-10x %u\n", - eqdma_sw_ctxt_entries[19].name, - eqdma_sw_ctxt_entries[19].value, - eqdma_sw_ctxt_entries[19].value); - - if (en_st && c2h) { - eqdma_cmpt_context_read(dev_hndl, first_err_qid, &cmpt_ctxt); - eqdma_fill_cmpt_ctxt(&cmpt_ctxt); - - qdma_log_info("\n%40s\n", "CMPT Context:"); - - /*** CMPT Context: int_st ***/ - qdma_log_info("%-47s %#-10x %u\n", - eqdma_cmpt_ctxt_entries[6].name, - eqdma_cmpt_ctxt_entries[6].value, - eqdma_cmpt_ctxt_entries[6].value); - - /** CMPT Context: PIDX ***/ - qdma_log_info("%-47s %#-10x %u\n", - eqdma_cmpt_ctxt_entries[12].name, - eqdma_cmpt_ctxt_entries[12].value, - eqdma_cmpt_ctxt_entries[12].value); - /*** CMPT Context: CIDX ***/ - qdma_log_info("%-47s %#-10x %u\n", - eqdma_cmpt_ctxt_entries[13].name, - eqdma_cmpt_ctxt_entries[13].value, - eqdma_cmpt_ctxt_entries[13].value); - - if (cmpt_ctxt.err != 0) { - /*** CMPT Context: ERR ***/ - qdma_log_info("%-47s %#-10x %u\n", - eqdma_cmpt_ctxt_entries[15].name, - eqdma_cmpt_ctxt_entries[15].value, - eqdma_cmpt_ctxt_entries[15].value); - } - } -} -/*****************************************************************************/ -/** - * eqdma_hw_st_h2c_err_process() - Function to dump MM H2C Error information - * - * @dev_hndl: device handle - * @buf: Bufffer for the debug info to be dumped in - * @buflen: Length of the buffer - * - * Return: void - *****************************************************************************/ -static void eqdma_hw_st_h2c_err_process(void *dev_hndl) -{ - int i = 0; - uint32_t st_h2c_err_reg_list[] = { - EQDMA_H2C_ERR_STAT_ADDR, - EQDMA_H2C_FIRST_ERR_QID_ADDR, - EQDMA_H2C_DBG_REG0_ADDR, - EQDMA_H2C_DBG_REG1_ADDR, - EQDMA_H2C_DBG_REG2_ADDR, - EQDMA_H2C_DBG_REG3_ADDR, - EQDMA_H2C_DBG_REG4_ADDR - }; - int st_h2c_err_num_regs = sizeof(st_h2c_err_reg_list)/sizeof(uint32_t); - - for (i = 0; i < st_h2c_err_num_regs; i++) { - eqdma_dump_reg_info(dev_hndl, st_h2c_err_reg_list[i], - 1, NULL, 0); - } - - eqdma_hw_err_dump_ctxt_info(dev_hndl, - EQDMA_H2C_FIRST_ERR_QID_ADDR, 1, 0); - -} - - -/*****************************************************************************/ -/** - * eqdma_hw_st_c2h_err_process() - Function to dump MM H2C Error information - * - * @dev_hndl: device handle - * @buf: Bufffer for the debug info to be dumped in - * @buflen: Length of the buffer - * - * Return: void - *****************************************************************************/ -static void eqdma_hw_st_c2h_err_process(void *dev_hndl) -{ - int i = 0; - - uint32_t st_c2h_err_reg_list[] = { - EQDMA_C2H_ERR_STAT_ADDR, - EQDMA_C2H_FATAL_ERR_STAT_ADDR, - EQDMA_C2H_FIRST_ERR_QID_ADDR, - EQDMA_C2H_STAT_S_AXIS_C2H_ACCEPTED_ADDR, - EQDMA_C2H_STAT_S_AXIS_WRB_ACCEPTED_ADDR, - EQDMA_C2H_STAT_DESC_RSP_PKT_ACCEPTED_ADDR, - EQDMA_C2H_STAT_AXIS_PKG_CMP_ADDR, - EQDMA_C2H_STAT_DBG_DMA_ENG_0_ADDR, - EQDMA_C2H_STAT_DBG_DMA_ENG_1_ADDR, - EQDMA_C2H_STAT_DBG_DMA_ENG_2_ADDR, - EQDMA_C2H_STAT_DBG_DMA_ENG_3_ADDR, - EQDMA_C2H_STAT_DESC_RSP_DROP_ACCEPTED_ADDR, - EQDMA_C2H_STAT_DESC_RSP_ERR_ACCEPTED_ADDR - }; - int st_c2h_err_num_regs = sizeof(st_c2h_err_reg_list)/sizeof(uint32_t); - - for (i = 0; i < st_c2h_err_num_regs; i++) { - eqdma_dump_reg_info(dev_hndl, st_c2h_err_reg_list[i], - 1, NULL, 0); - } - - eqdma_hw_err_dump_ctxt_info(dev_hndl, - EQDMA_C2H_FIRST_ERR_QID_ADDR, 1, 1); - -} - -/*****************************************************************************/ -/** - * eqdma_mm_c2h0_err_process() - Function to dump MM C2H - * Error information - * - * @dev_hndl: device handle - * - * Return: void - *****************************************************************************/ -static void eqdma_mm_c2h0_err_process(void *dev_hndl) -{ - int i = 0; - uint32_t mm_c2h_err_reg_list[] = { - EQDMA_C2H_MM_STATUS_ADDR, - EQDMA_C2H_MM_CMPL_DESC_CNT_ADDR, - EQDMA_C2H_MM_ERR_CODE_ADDR, - EQDMA_C2H_MM_ERR_INFO_ADDR, - EQDMA_C2H_MM_DBG_ADDR - }; - int mm_c2h_err_num_regs = sizeof(mm_c2h_err_reg_list)/sizeof(uint32_t); - - for (i = 0; i < mm_c2h_err_num_regs; i++) { - eqdma_dump_reg_info(dev_hndl, mm_c2h_err_reg_list[i], - 1, NULL, 0); - } - - eqdma_hw_err_dump_ctxt_info(dev_hndl, - EQDMA_C2H_MM_ERR_INFO_ADDR, 0, 1); -} - -/*****************************************************************************/ -/** - * eqdma_mm_h2c0_err_process() - Function to dump MM H2C - * Error information - * - * @dev_hndl: device handle - * - * Return: void - *****************************************************************************/ -static void eqdma_mm_h2c0_err_process(void *dev_hndl) -{ - int i = 0; - uint32_t mm_h2c_err_reg_list[] = { - EQDMA_H2C_MM_STATUS_ADDR, - EQDMA_H2C_MM_CMPL_DESC_CNT_ADDR, - EQDMA_H2C_MM_ERR_CODE_ADDR, - EQDMA_H2C_MM_ERR_INFO_ADDR, - EQDMA_H2C_MM_DBG_ADDR - }; - int mm_h2c_err_num_regs = sizeof(mm_h2c_err_reg_list)/sizeof(uint32_t); - - for (i = 0; i < mm_h2c_err_num_regs; i++) { - eqdma_dump_reg_info(dev_hndl, mm_h2c_err_reg_list[i], - 1, NULL, 0); - } - - eqdma_hw_err_dump_ctxt_info(dev_hndl, - EQDMA_H2C_MM_ERR_INFO_ADDR, 0, 1); -} - -/*****************************************************************************/ -/** - * eqdma_hw_get_error_name() - Function to get the error in string format - * - * @err_idx: error index - * - * Return: string - success and NULL on failure - *****************************************************************************/ -const char *eqdma_hw_get_error_name(uint32_t err_idx) -{ - if (err_idx >= EQDMA_ERRS_ALL) { - qdma_log_error("%s: err_idx=%d is invalid, returning NULL\n", - __func__, (enum eqdma_error_idx)err_idx); - return NULL; - } - - return eqdma_err_info[(enum eqdma_error_idx)err_idx].err_name; -} - -/*****************************************************************************/ -/** - * eqdma_hw_error_process() - Function to find the error that got - * triggered and call the handler qdma_hw_error_handler of that - * particular error. - * - * @dev_hndl: device handle - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -int eqdma_hw_error_process(void *dev_hndl) -{ - uint32_t glbl_err_stat = 0, err_stat = 0; - uint32_t bit = 0, i = 0; - int32_t idx = 0; - struct qdma_dev_attributes dev_cap; - uint32_t hw_err_position[EQDMA_TOTAL_LEAF_ERROR_AGGREGATORS] = { - EQDMA_DSC_ERR_POISON, - EQDMA_TRQ_ERR_CSR_UNMAPPED, - EQDMA_ST_C2H_ERR_MTY_MISMATCH, - EQDMA_ST_FATAL_ERR_MTY_MISMATCH, - EQDMA_ST_H2C_ERR_ZERO_LEN_DESC, - EQDMA_SBE_1_ERR_RC_RRQ_EVEN_RAM, - EQDMA_SBE_ERR_MI_H2C0_DAT, - EQDMA_DBE_1_ERR_RC_RRQ_EVEN_RAM, - EQDMA_DBE_ERR_MI_H2C0_DAT, - EQDMA_MM_C2H_WR_SLR_ERR, - EQDMA_MM_H2C0_RD_HDR_POISON_ERR - }; - - if (!dev_hndl) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - - eqdma_get_device_attributes(dev_hndl, &dev_cap); - - glbl_err_stat = qdma_reg_read(dev_hndl, EQDMA_GLBL_ERR_STAT_ADDR); - - if (!glbl_err_stat) - return QDMA_HW_ERR_NOT_DETECTED; - - - qdma_log_info("%s: Global Err Reg(0x%x) = 0x%x\n", - __func__, EQDMA_GLBL_ERR_STAT_ADDR, - glbl_err_stat); - - for (i = 0; i < EQDMA_TOTAL_LEAF_ERROR_AGGREGATORS; i++) { - bit = hw_err_position[i]; - - if ((!dev_cap.st_en) && (bit == EQDMA_ST_C2H_ERR_MTY_MISMATCH || - bit == EQDMA_ST_FATAL_ERR_MTY_MISMATCH || - bit == EQDMA_ST_H2C_ERR_ZERO_LEN_DESC)) - continue; - - err_stat = qdma_reg_read(dev_hndl, - eqdma_err_info[bit].stat_reg_addr); - if (err_stat) { - qdma_log_info("addr = 0x%08x val = 0x%08x", - eqdma_err_info[bit].stat_reg_addr, - err_stat); - - eqdma_err_info[bit].eqdma_hw_err_process( - dev_hndl); - for (idx = bit; idx < all_eqdma_hw_errs[i]; idx++) { - /* call the platform specific handler */ - if (err_stat & - eqdma_err_info[idx].leaf_err_mask) - qdma_log_error("%s detected %s\n", - __func__, - eqdma_hw_get_error_name(idx)); - } - qdma_reg_write(dev_hndl, - eqdma_err_info[bit].stat_reg_addr, - err_stat); - } - - } - - /* Write 1 to the global status register to clear the bits */ - qdma_reg_write(dev_hndl, EQDMA_GLBL_ERR_STAT_ADDR, glbl_err_stat); - - return QDMA_SUCCESS; -} - -/*****************************************************************************/ -/** - * qdma_hw_error_enable() - Function to enable all or a specific error - * - * @dev_hndl: device handle - * @err_idx: error index - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -int eqdma_hw_error_enable(void *dev_hndl, uint32_t err_idx) -{ - uint32_t idx = 0, i = 0; - uint32_t reg_val = 0; - struct qdma_dev_attributes dev_cap; - - if (!dev_hndl) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - if (err_idx > EQDMA_ERRS_ALL) { - qdma_log_error("%s: err_idx=%d is invalid, err:%d\n", - __func__, (enum eqdma_error_idx)err_idx, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - eqdma_get_device_attributes(dev_hndl, &dev_cap); - - if (err_idx == EQDMA_ERRS_ALL) { - for (i = 0; i < EQDMA_TOTAL_LEAF_ERROR_AGGREGATORS; i++) { - - idx = all_eqdma_hw_errs[i]; - - /* Don't access streaming registers in - * MM only bitstreams - */ - if (!dev_cap.st_en) { - if (idx == EQDMA_ST_C2H_ERR_ALL || - idx == EQDMA_ST_FATAL_ERR_ALL || - idx == EQDMA_ST_H2C_ERR_ALL) - continue; - } - - reg_val = eqdma_err_info[idx].leaf_err_mask; - qdma_reg_write(dev_hndl, - eqdma_err_info[idx].mask_reg_addr, reg_val); - - reg_val = qdma_reg_read(dev_hndl, - EQDMA_GLBL_ERR_MASK_ADDR); - reg_val |= FIELD_SET( - eqdma_err_info[idx].global_err_mask, 1); - qdma_reg_write(dev_hndl, EQDMA_GLBL_ERR_MASK_ADDR, - reg_val); - } - - } else { - /* Don't access streaming registers in MM only bitstreams - * QDMA_C2H_ERR_MTY_MISMATCH to QDMA_H2C_ERR_ALL are all - * ST errors - */ - if (!dev_cap.st_en) { - if (err_idx >= EQDMA_ST_C2H_ERR_MTY_MISMATCH && - err_idx <= EQDMA_ST_H2C_ERR_ALL) - return QDMA_SUCCESS; - } - - reg_val = qdma_reg_read(dev_hndl, - eqdma_err_info[err_idx].mask_reg_addr); - reg_val |= FIELD_SET(eqdma_err_info[err_idx].leaf_err_mask, 1); - qdma_reg_write(dev_hndl, - eqdma_err_info[err_idx].mask_reg_addr, reg_val); - - reg_val = qdma_reg_read(dev_hndl, EQDMA_GLBL_ERR_MASK_ADDR); - reg_val |= - FIELD_SET(eqdma_err_info[err_idx].global_err_mask, 1); - qdma_reg_write(dev_hndl, EQDMA_GLBL_ERR_MASK_ADDR, reg_val); - } - - return QDMA_SUCCESS; -} - -/*****************************************************************************/ -/** - * eqdma_get_device_attributes() - Function to get the qdma device - * attributes - * - * @dev_hndl: device handle - * @dev_info: pointer to hold the device info - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -int eqdma_get_device_attributes(void *dev_hndl, - struct qdma_dev_attributes *dev_info) -{ - uint8_t count = 0; - uint32_t reg_val = 0; - - if (!dev_hndl) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - if (!dev_info) { - qdma_log_error("%s: dev_info is NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - /* number of PFs */ - reg_val = qdma_reg_read(dev_hndl, QDMA_OFFSET_GLBL2_PF_BARLITE_INT); - if (FIELD_GET(QDMA_GLBL2_PF0_BAR_MAP_MASK, reg_val)) - count++; - if (FIELD_GET(QDMA_GLBL2_PF1_BAR_MAP_MASK, reg_val)) - count++; - if (FIELD_GET(QDMA_GLBL2_PF2_BAR_MAP_MASK, reg_val)) - count++; - if (FIELD_GET(QDMA_GLBL2_PF3_BAR_MAP_MASK, reg_val)) - count++; - dev_info->num_pfs = count; - - /* Number of Qs */ - reg_val = qdma_reg_read(dev_hndl, EQDMA_GLBL2_CHANNEL_CAP_ADDR); - dev_info->num_qs = - FIELD_GET(GLBL2_CHANNEL_CAP_MULTIQ_MAX_MASK, reg_val); - - /* FLR present */ - reg_val = qdma_reg_read(dev_hndl, EQDMA_GLBL2_MISC_CAP_ADDR); - dev_info->mailbox_en = FIELD_GET(EQDMA_GLBL2_MAILBOX_EN_MASK, - reg_val); - dev_info->flr_present = FIELD_GET(EQDMA_GLBL2_FLR_PRESENT_MASK, - reg_val); - dev_info->mm_cmpt_en = 0; - dev_info->debug_mode = FIELD_GET(EQDMA_GLBL2_DBG_MODE_EN_MASK, - reg_val); - dev_info->desc_eng_mode = FIELD_GET(EQDMA_GLBL2_DESC_ENG_MODE_MASK, - reg_val); - - /* ST/MM enabled? */ - reg_val = qdma_reg_read(dev_hndl, EQDMA_GLBL2_CHANNEL_MDMA_ADDR); - dev_info->st_en = (FIELD_GET(GLBL2_CHANNEL_MDMA_C2H_ST_MASK, reg_val) - && FIELD_GET(GLBL2_CHANNEL_MDMA_H2C_ST_MASK, reg_val)) ? 1 : 0; - dev_info->mm_en = (FIELD_GET(GLBL2_CHANNEL_MDMA_C2H_ENG_MASK, reg_val) - && FIELD_GET(GLBL2_CHANNEL_MDMA_H2C_ENG_MASK, reg_val)) ? 1 : 0; - - /* num of mm channels */ - /* TODO : Register not yet defined for this. Hard coding it to 1.*/ - dev_info->mm_channel_max = 1; - - dev_info->qid2vec_ctx = 0; - dev_info->cmpt_ovf_chk_dis = 1; - dev_info->mailbox_intr = 1; - dev_info->sw_desc_64b = 1; - dev_info->cmpt_desc_64b = 1; - dev_info->dynamic_bar = 1; - dev_info->legacy_intr = 1; - dev_info->cmpt_trig_count_timer = 1; - - return QDMA_SUCCESS; -} - -/*****************************************************************************/ -/** - * eqdma_init_ctxt_memory() - function to initialize the context memory - * - * @dev_hndl: device handle - * - * Return: returns the platform specific error code - *****************************************************************************/ -int eqdma_init_ctxt_memory(void *dev_hndl) -{ -#ifdef ENABLE_INIT_CTXT_MEMORY - uint32_t data[QDMA_REG_IND_CTXT_REG_COUNT]; - uint16_t i = 0; - struct qdma_dev_attributes dev_info; - - if (!dev_hndl) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - qdma_memset(data, 0, sizeof(uint32_t) * QDMA_REG_IND_CTXT_REG_COUNT); - eqdma_get_device_attributes(dev_hndl, &dev_info); - - for (; i < dev_info.num_qs; i++) { - int sel = QDMA_CTXT_SEL_SW_C2H; - int rv; - - for (; sel <= QDMA_CTXT_SEL_PFTCH; sel++) { - /** if the st mode(h2c/c2h) not enabled - * in the design, then skip the PFTCH - * and CMPT context setup - */ - if ((dev_info.st_en == 0) && - ((sel == QDMA_CTXT_SEL_PFTCH) || - (sel == QDMA_CTXT_SEL_CMPT))) { - qdma_log_debug("%s: ST context is skipped:", - __func__); - qdma_log_debug("sel = %d\n", sel); - continue; - } - - rv = eqdma_indirect_reg_clear(dev_hndl, - (enum ind_ctxt_cmd_sel)sel, i); - if (rv < 0) - return rv; - } - } - - /* fmap */ - for (i = 0; i < dev_info.num_pfs; i++) - eqdma_indirect_reg_clear(dev_hndl, - QDMA_CTXT_SEL_FMAP, i); - -#else - if (!dev_hndl) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } -#endif - return QDMA_SUCCESS; - -} - - -static int get_reg_entry(uint32_t reg_addr, int *reg_entry) -{ - uint32_t i = 0; - struct xreg_info *reg_info; - uint32_t num_regs = eqdma_config_num_regs_get(); - - reg_info = eqdma_config_regs_get(); - - for (i = 0; (i < num_regs - 1); i++) { - if (reg_info[i].addr == reg_addr) { - *reg_entry = i; - break; - } - } - - if (i >= num_regs - 1) { - qdma_log_error("%s: 0x%08x is missing register list, err:%d\n", - __func__, - reg_addr, - -QDMA_ERR_INV_PARAM); - *reg_entry = -1; - return -QDMA_ERR_INV_PARAM; - } - - return 0; -} - -/*****************************************************************************/ -/** - * eqdma_dump_config_reg_list() - Dump the registers - * - * @dev_hndl: device handle - * @total_regs : Max registers to read - * @reg_list : array of reg addr and reg values - * @buf : pointer to buffer to be filled - * @buflen : Length of the buffer - * - * Return: returns the platform specific error code - *****************************************************************************/ -int eqdma_dump_config_reg_list(void *dev_hndl, uint32_t total_regs, - struct qdma_reg_data *reg_list, char *buf, uint32_t buflen) -{ - uint32_t j = 0, len = 0; - uint32_t reg_count = 0; - int reg_data_entry; - int rv = 0; - char name[DEBGFS_GEN_NAME_SZ] = ""; - struct xreg_info *reg_info = eqdma_config_regs_get(); - struct qdma_dev_attributes dev_cap; - - if (!dev_hndl) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - if (!buf) { - qdma_log_error("%s: buf is NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - eqdma_get_device_attributes(dev_hndl, &dev_cap); - - for (reg_count = 0; - (reg_count < total_regs);) { - - /* If Debug Mode not enabled and the current register - * is debug register, skip reading it. - */ - if (dev_cap.debug_mode == 0 && - reg_info[reg_count].is_debug_reg == 1) - continue; - - rv = get_reg_entry(reg_list[reg_count].reg_addr, - ®_data_entry); - if (rv < 0) { - qdma_log_error("%s: register missing in list, err:%d\n", - __func__, - -QDMA_ERR_INV_PARAM); - return rv; - } - - for (j = 0; j < reg_info[reg_data_entry].repeat; j++) { - rv = QDMA_SNPRINTF_S(name, DEBGFS_GEN_NAME_SZ, - DEBGFS_GEN_NAME_SZ, - "%s_%d", - reg_info[reg_data_entry].name, j); - if ((rv < 0) || (rv > DEBGFS_GEN_NAME_SZ)) { - qdma_log_error( - "%d:%s snprintf failed, err:%d\n", - __LINE__, __func__, - rv); - return -QDMA_ERR_NO_MEM; - } - rv = dump_reg(buf + len, buflen - len, - (reg_info[reg_data_entry].addr + (j * 4)), - name, - reg_list[reg_count + j].reg_val); - if (rv < 0) { - qdma_log_error( - "%s Buff too small, err:%d\n", - __func__, - -QDMA_ERR_NO_MEM); - return -QDMA_ERR_NO_MEM; - } - len += rv; - } - reg_count += j; - } - - return len; - -} - - -/*****************************************************************************/ -/** - * qdma_read_reg_list() - read the register values - * - * @dev_hndl: device handle - * @is_vf: Whether PF or VF - * @total_regs : Max registers to read - * @reg_list : array of reg addr and reg values - * - * Return: returns the platform specific error code - *****************************************************************************/ -int eqdma_read_reg_list(void *dev_hndl, uint8_t is_vf, - uint16_t reg_rd_group, - uint16_t *total_regs, - struct qdma_reg_data *reg_list) -{ - uint16_t reg_count = 0, i = 0, j = 0; - struct xreg_info *reg_info; - uint32_t num_regs = eqdma_config_num_regs_get(); - struct xreg_info *eqdma_config_regs = eqdma_config_regs_get(); - struct qdma_dev_attributes dev_cap; - uint32_t reg_start_addr = 0; - int reg_index = 0; - int rv = 0; - - if (!is_vf) { - qdma_log_error("%s: not supported for PF, err:%d\n", - __func__, - -QDMA_ERR_HWACC_FEATURE_NOT_SUPPORTED); - return -QDMA_ERR_HWACC_FEATURE_NOT_SUPPORTED; - } - - if (!dev_hndl) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - if (!reg_list) { - qdma_log_error("%s: reg_list is NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - eqdma_get_device_attributes(dev_hndl, &dev_cap); - - switch (reg_rd_group) { - case QDMA_REG_READ_GROUP_1: - reg_start_addr = EQDMA_REG_GROUP_1_START_ADDR; - break; - case QDMA_REG_READ_GROUP_2: - reg_start_addr = EQDMA_REG_GROUP_2_START_ADDR; - break; - case QDMA_REG_READ_GROUP_3: - reg_start_addr = EQDMA_REG_GROUP_3_START_ADDR; - break; - case QDMA_REG_READ_GROUP_4: - reg_start_addr = EQDMA_REG_GROUP_4_START_ADDR; - break; - default: - qdma_log_error("%s: Invalid slot received\n", - __func__); - return -QDMA_ERR_INV_PARAM; - } - - rv = get_reg_entry(reg_start_addr, ®_index); - if (rv < 0) { - qdma_log_error("%s: register missing in list, err:%d\n", - __func__, - -QDMA_ERR_INV_PARAM); - return rv; - } - reg_info = &eqdma_config_regs[reg_index]; - - for (i = 0, reg_count = 0; - ((i < num_regs - 1 - reg_index) && - (reg_count < QDMA_MAX_REGISTER_DUMP)); i++) { - - if (((GET_CAPABILITY_MASK(dev_cap.mm_en, dev_cap.st_en, - dev_cap.mm_cmpt_en, dev_cap.mailbox_en) - & reg_info[i].mode) == 0) || - (reg_info[i].read_type == QDMA_REG_READ_PF_ONLY)) - continue; - - /* If Debug Mode not enabled and the current register - * is debug register, skip reading it. - */ - if (dev_cap.debug_mode == 0 && - reg_info[i].is_debug_reg == 1) - continue; - - for (j = 0; j < reg_info[i].repeat && - (reg_count < QDMA_MAX_REGISTER_DUMP); - j++) { - reg_list[reg_count].reg_addr = - (reg_info[i].addr + (j * 4)); - reg_list[reg_count].reg_val = - qdma_reg_read(dev_hndl, - reg_list[reg_count].reg_addr); - reg_count++; - } - } - - *total_regs = reg_count; - return rv; -} - -/*****************************************************************************/ -/** - * eqdma_write_global_ring_sizes() - function to set the global ring size array - * - * @dev_hndl: device handle - * @index: Index from where the values needs to written - * @count: number of entries to be written - * @glbl_rng_sz: pointer to the array having the values to write - * - * (index + count) shall not be more than 16 - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -static int eqdma_write_global_ring_sizes(void *dev_hndl, uint8_t index, - uint8_t count, const uint32_t *glbl_rng_sz) -{ - if (!dev_hndl || !glbl_rng_sz || !count) { - qdma_log_error("%s: dev_hndl=%p glbl_rng_sz=%p, err:%d\n", - __func__, dev_hndl, glbl_rng_sz, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - if ((index + count) > QDMA_NUM_RING_SIZES) { - qdma_log_error("%s: index=%u count=%u > %d, err:%d\n", - __func__, index, count, - QDMA_NUM_RING_SIZES, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - qdma_write_csr_values(dev_hndl, EQDMA_GLBL_RNG_SZ_1_ADDR, index, count, - glbl_rng_sz); - - return QDMA_SUCCESS; -} - -/*****************************************************************************/ -/** - * eqdma_read_global_ring_sizes() - function to get the global rng_sz array - * - * @dev_hndl: device handle - * @index: Index from where the values needs to read - * @count: number of entries to be read - * @glbl_rng_sz: pointer to array to hold the values read - * - * (index + count) shall not be more than 16 - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -static int eqdma_read_global_ring_sizes(void *dev_hndl, uint8_t index, - uint8_t count, uint32_t *glbl_rng_sz) -{ - if (!dev_hndl || !glbl_rng_sz || !count) { - qdma_log_error("%s: dev_hndl=%p glbl_rng_sz=%p, err:%d\n", - __func__, dev_hndl, glbl_rng_sz, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - if ((index + count) > QDMA_NUM_RING_SIZES) { - qdma_log_error("%s: index=%u count=%u > %d, err:%d\n", - __func__, index, count, - QDMA_NUM_C2H_BUFFER_SIZES, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - qdma_read_csr_values(dev_hndl, EQDMA_GLBL_RNG_SZ_1_ADDR, index, count, - glbl_rng_sz); - - return QDMA_SUCCESS; -} - -/*****************************************************************************/ -/** - * eqdma_write_global_timer_count() - function to set the timer values - * - * @dev_hndl: device handle - * @glbl_tmr_cnt: pointer to the array having the values to write - * @index: Index from where the values needs to written - * @count: number of entries to be written - * - * (index + count) shall not be more than 16 - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -static int eqdma_write_global_timer_count(void *dev_hndl, uint8_t index, - uint8_t count, const uint32_t *glbl_tmr_cnt) -{ - struct qdma_dev_attributes dev_cap; - - if (!dev_hndl || !glbl_tmr_cnt || !count) { - qdma_log_error("%s: dev_hndl=%p glbl_tmr_cnt=%p, err:%d\n", - __func__, dev_hndl, glbl_tmr_cnt, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - if ((index + count) > QDMA_NUM_C2H_TIMERS) { - qdma_log_error("%s: index=%u count=%u > %d, err:%d\n", - __func__, index, count, - QDMA_NUM_C2H_TIMERS, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - eqdma_get_device_attributes(dev_hndl, &dev_cap); - - if (dev_cap.st_en || dev_cap.mm_cmpt_en) - qdma_write_csr_values(dev_hndl, EQDMA_C2H_TIMER_CNT_ADDR, - index, count, glbl_tmr_cnt); - else { - qdma_log_error("%s: ST or MM cmpt not supported, err:%d\n", - __func__, - -QDMA_ERR_HWACC_FEATURE_NOT_SUPPORTED); - return -QDMA_ERR_HWACC_FEATURE_NOT_SUPPORTED; - } - - return QDMA_SUCCESS; -} - -/*****************************************************************************/ -/** - * eqdma_read_global_timer_count() - function to get the timer values - * - * @dev_hndl: device handle - * @index: Index from where the values needs to read - * @count: number of entries to be read - * @glbl_tmr_cnt: pointer to array to hold the values read - * - * (index + count) shall not be more than 16 - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -static int eqdma_read_global_timer_count(void *dev_hndl, uint8_t index, - uint8_t count, uint32_t *glbl_tmr_cnt) -{ - struct qdma_dev_attributes dev_cap; - - if (!dev_hndl || !glbl_tmr_cnt || !count) { - qdma_log_error("%s: dev_hndl=%p glbl_tmr_cnt=%p, err:%d\n", - __func__, dev_hndl, glbl_tmr_cnt, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - if ((index + count) > QDMA_NUM_C2H_TIMERS) { - qdma_log_error("%s: index=%u count=%u > %d, err:%d\n", - __func__, index, count, - QDMA_NUM_C2H_TIMERS, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - eqdma_get_device_attributes(dev_hndl, &dev_cap); - - if (dev_cap.st_en || dev_cap.mm_cmpt_en) - qdma_read_csr_values(dev_hndl, - EQDMA_C2H_TIMER_CNT_ADDR, index, - count, glbl_tmr_cnt); - else { - qdma_log_error("%s: ST or MM cmpt not supported, err:%d\n", - __func__, - -QDMA_ERR_HWACC_FEATURE_NOT_SUPPORTED); - return -QDMA_ERR_HWACC_FEATURE_NOT_SUPPORTED; - } - - return QDMA_SUCCESS; -} - -/*****************************************************************************/ -/** - * eqdma_write_global_counter_threshold() - function to set the counter - * threshold values - * - * @dev_hndl: device handle - * @index: Index from where the values needs to written - * @count: number of entries to be written - * @glbl_cnt_th: pointer to the array having the values to write - * - * (index + count) shall not be more than 16 - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -static int eqdma_write_global_counter_threshold(void *dev_hndl, uint8_t index, - uint8_t count, const uint32_t *glbl_cnt_th) -{ - struct qdma_dev_attributes dev_cap; - - if (!dev_hndl || !glbl_cnt_th || !count) { - qdma_log_error("%s: dev_hndl=%p glbl_cnt_th=%p, err:%d\n", - __func__, dev_hndl, glbl_cnt_th, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - if ((index + count) > QDMA_NUM_C2H_COUNTERS) { - qdma_log_error("%s: index=%u count=%u > %d, err:%d\n", - __func__, index, count, - QDMA_NUM_C2H_BUFFER_SIZES, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - eqdma_get_device_attributes(dev_hndl, &dev_cap); - - if (dev_cap.st_en || dev_cap.mm_cmpt_en) - qdma_write_csr_values(dev_hndl, EQDMA_C2H_CNT_TH_ADDR, index, - count, glbl_cnt_th); - else { - qdma_log_error("%s: ST or MM cmpt not supported, err:%d\n", - __func__, - -QDMA_ERR_HWACC_FEATURE_NOT_SUPPORTED); - return -QDMA_ERR_HWACC_FEATURE_NOT_SUPPORTED; - } - - return QDMA_SUCCESS; -} - -/*****************************************************************************/ -/** - * eqdma_read_global_counter_threshold() - function to get the counter threshold - * values - * - * @dev_hndl: device handle - * @index: Index from where the values needs to read - * @count: number of entries to be read - * @glbl_cnt_th: pointer to array to hold the values read - * - * (index + count) shall not be more than 16 - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -static int eqdma_read_global_counter_threshold(void *dev_hndl, uint8_t index, - uint8_t count, uint32_t *glbl_cnt_th) -{ - struct qdma_dev_attributes dev_cap; - - if (!dev_hndl || !glbl_cnt_th || !count) { - qdma_log_error("%s: dev_hndl=%p glbl_cnt_th=%p, err:%d\n", - __func__, dev_hndl, glbl_cnt_th, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - if ((index + count) > QDMA_NUM_C2H_COUNTERS) { - qdma_log_error("%s: index=%u count=%u > %d, err:%d\n", - __func__, index, count, - QDMA_NUM_C2H_COUNTERS, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - eqdma_get_device_attributes(dev_hndl, &dev_cap); - - if (dev_cap.st_en || dev_cap.mm_cmpt_en) - qdma_read_csr_values(dev_hndl, EQDMA_C2H_CNT_TH_ADDR, index, - count, glbl_cnt_th); - else { - qdma_log_error("%s: ST or MM cmpt not supported, err:%d\n", - __func__, -QDMA_ERR_HWACC_FEATURE_NOT_SUPPORTED); - return -QDMA_ERR_HWACC_FEATURE_NOT_SUPPORTED; - } - - return QDMA_SUCCESS; -} - -/*****************************************************************************/ -/** - * eqdma_write_global_buffer_sizes() - function to set the buffer sizes - * - * @dev_hndl: device handle - * @index: Index from where the values needs to written - * @count: number of entries to be written - * @glbl_buf_sz: pointer to the array having the values to write - * - * (index + count) shall not be more than 16 - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -static int eqdma_write_global_buffer_sizes(void *dev_hndl, uint8_t index, - uint8_t count, const uint32_t *glbl_buf_sz) -{ - struct qdma_dev_attributes dev_cap; - - if (!dev_hndl || !glbl_buf_sz || !count) { - qdma_log_error("%s: dev_hndl=%p glbl_buf_sz=%p, err:%d\n", - __func__, dev_hndl, glbl_buf_sz, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - if ((index + count) > QDMA_NUM_C2H_BUFFER_SIZES) { - qdma_log_error("%s: index=%u count=%u > %d, err:%d\n", - __func__, index, count, - QDMA_NUM_C2H_BUFFER_SIZES, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - eqdma_get_device_attributes(dev_hndl, &dev_cap); - - if (dev_cap.st_en) - qdma_write_csr_values(dev_hndl, EQDMA_C2H_BUF_SZ_ADDR, index, - count, glbl_buf_sz); - else { - qdma_log_error("%s: ST not supported, err:%d\n", - __func__, - -QDMA_ERR_HWACC_FEATURE_NOT_SUPPORTED); - return -QDMA_ERR_HWACC_FEATURE_NOT_SUPPORTED; - } - - return QDMA_SUCCESS; -} - -/*****************************************************************************/ -/** - * eqdma_read_global_buffer_sizes() - function to get the buffer sizes - * - * @dev_hndl: device handle - * @index: Index from where the values needs to read - * @count: number of entries to be read - * @glbl_buf_sz: pointer to array to hold the values read - * - * (index + count) shall not be more than 16 - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -static int eqdma_read_global_buffer_sizes(void *dev_hndl, uint8_t index, - uint8_t count, uint32_t *glbl_buf_sz) -{ - struct qdma_dev_attributes dev_cap; - - if (!dev_hndl || !glbl_buf_sz || !count) { - qdma_log_error("%s: dev_hndl=%p glbl_buf_sz=%p, err:%d\n", - __func__, dev_hndl, glbl_buf_sz, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - if ((index + count) > QDMA_NUM_C2H_BUFFER_SIZES) { - qdma_log_error("%s: index=%u count=%u > %d, err:%d\n", - __func__, index, count, - QDMA_NUM_C2H_BUFFER_SIZES, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - eqdma_get_device_attributes(dev_hndl, &dev_cap); - - if (dev_cap.st_en) - qdma_read_csr_values(dev_hndl, EQDMA_C2H_BUF_SZ_ADDR, index, - count, glbl_buf_sz); - else { - qdma_log_error("%s: ST is not supported, err:%d\n", - __func__, - -QDMA_ERR_HWACC_FEATURE_NOT_SUPPORTED); - return -QDMA_ERR_HWACC_FEATURE_NOT_SUPPORTED; - } - - return QDMA_SUCCESS; -} - -/*****************************************************************************/ -/** - * eqdma_global_csr_conf() - function to configure global csr - * - * @dev_hndl: device handle - * @index: Index from where the values needs to read - * @count: number of entries to be read - * @csr_val: uint32_t pointer to csr value - * @csr_type: Type of the CSR (qdma_global_csr_type enum) to configure - * @access_type HW access type (qdma_hw_access_type enum) value - * QDMA_HW_ACCESS_CLEAR - Not supported - * QDMA_HW_ACCESS_INVALIDATE - Not supported - * - * (index + count) shall not be more than 16 - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -int eqdma_global_csr_conf(void *dev_hndl, uint8_t index, uint8_t count, - uint32_t *csr_val, - enum qdma_global_csr_type csr_type, - enum qdma_hw_access_type access_type) -{ - int rv = QDMA_SUCCESS; - - switch (csr_type) { - case QDMA_CSR_RING_SZ: - switch (access_type) { - case QDMA_HW_ACCESS_READ: - rv = eqdma_read_global_ring_sizes( - dev_hndl, - index, - count, - csr_val); - break; - case QDMA_HW_ACCESS_WRITE: - rv = eqdma_write_global_ring_sizes( - dev_hndl, - index, - count, - csr_val); - break; - default: - qdma_log_error("%s: access_type(%d) invalid, err:%d\n", - __func__, - access_type, - -QDMA_ERR_INV_PARAM); - rv = -QDMA_ERR_INV_PARAM; - break; - } - break; - case QDMA_CSR_TIMER_CNT: - switch (access_type) { - case QDMA_HW_ACCESS_READ: - rv = eqdma_read_global_timer_count( - dev_hndl, - index, - count, - csr_val); - break; - case QDMA_HW_ACCESS_WRITE: - rv = eqdma_write_global_timer_count( - dev_hndl, - index, - count, - csr_val); - break; - default: - qdma_log_error("%s: access_type(%d) invalid, err:%d\n", - __func__, - access_type, - -QDMA_ERR_INV_PARAM); - rv = -QDMA_ERR_INV_PARAM; - break; - } - break; - case QDMA_CSR_CNT_TH: - switch (access_type) { - case QDMA_HW_ACCESS_READ: - rv = - eqdma_read_global_counter_threshold( - dev_hndl, - index, - count, - csr_val); - break; - case QDMA_HW_ACCESS_WRITE: - rv = - eqdma_write_global_counter_threshold( - dev_hndl, - index, - count, - csr_val); - break; - default: - qdma_log_error("%s: access_type(%d) invalid, err:%d\n", - __func__, - access_type, - -QDMA_ERR_INV_PARAM); - rv = -QDMA_ERR_INV_PARAM; - break; - } - break; - case QDMA_CSR_BUF_SZ: - switch (access_type) { - case QDMA_HW_ACCESS_READ: - rv = - eqdma_read_global_buffer_sizes(dev_hndl, - index, - count, - csr_val); - break; - case QDMA_HW_ACCESS_WRITE: - rv = - eqdma_write_global_buffer_sizes(dev_hndl, - index, - count, - csr_val); - break; - default: - qdma_log_error("%s: access_type(%d) invalid, err:%d\n", - __func__, - access_type, - -QDMA_ERR_INV_PARAM); - rv = -QDMA_ERR_INV_PARAM; - break; - } - break; - default: - qdma_log_error("%s: csr_type(%d) invalid, err:%d\n", - __func__, - csr_type, - -QDMA_ERR_INV_PARAM); - rv = -QDMA_ERR_INV_PARAM; - break; - } - - return rv; -} - -/*****************************************************************************/ -/** - * eqdma_global_writeback_interval_write() - function to set the writeback - * interval - * - * @dev_hndl device handle - * @wb_int: Writeback Interval - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -static int eqdma_global_writeback_interval_write(void *dev_hndl, - enum qdma_wrb_interval wb_int) -{ - uint32_t reg_val; - struct qdma_dev_attributes dev_cap; - - if (!dev_hndl) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", __func__, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - if (wb_int >= QDMA_NUM_WRB_INTERVALS) { - qdma_log_error("%s: wb_int=%d is invalid, err:%d\n", - __func__, wb_int, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - eqdma_get_device_attributes(dev_hndl, &dev_cap); - - if (dev_cap.st_en || dev_cap.mm_cmpt_en) { - reg_val = qdma_reg_read(dev_hndl, EQDMA_GLBL_DSC_CFG_ADDR); - reg_val |= FIELD_SET(GLBL_DSC_CFG_WB_ACC_INT_MASK, wb_int); - qdma_reg_write(dev_hndl, EQDMA_GLBL_DSC_CFG_ADDR, reg_val); - } else { - qdma_log_error("%s: ST or MM cmpt not supported, err:%d\n", - __func__, -QDMA_ERR_HWACC_FEATURE_NOT_SUPPORTED); - return -QDMA_ERR_HWACC_FEATURE_NOT_SUPPORTED; - } - - return QDMA_SUCCESS; -} - -/*****************************************************************************/ -/** - * eqdma_global_writeback_interval_read() - function to get the writeback - * interval - * - * @dev_hndl: device handle - * @wb_int: pointer to the data to hold Writeback Interval - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -static int eqdma_global_writeback_interval_read(void *dev_hndl, - enum qdma_wrb_interval *wb_int) -{ - uint32_t reg_val; - struct qdma_dev_attributes dev_cap; - - if (!dev_hndl) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", __func__, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - if (!wb_int) { - qdma_log_error("%s: wb_int is NULL, err:%d\n", __func__, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - eqdma_get_device_attributes(dev_hndl, &dev_cap); - - if (dev_cap.st_en || dev_cap.mm_cmpt_en) { - reg_val = qdma_reg_read(dev_hndl, EQDMA_GLBL_DSC_CFG_ADDR); - *wb_int = (enum qdma_wrb_interval)FIELD_GET( - GLBL_DSC_CFG_WB_ACC_INT_MASK, reg_val); - } else { - qdma_log_error("%s: ST or MM cmpt not supported, err:%d\n", - __func__, -QDMA_ERR_HWACC_FEATURE_NOT_SUPPORTED); - return -QDMA_ERR_HWACC_FEATURE_NOT_SUPPORTED; - } - - return QDMA_SUCCESS; -} - -/*****************************************************************************/ -/** - * eqdma_global_writeback_interval_conf() - function to configure - * the writeback interval - * - * @dev_hndl: device handle - * @wb_int: pointer to the data to hold Writeback Interval - * @access_type HW access type (qdma_hw_access_type enum) value - * QDMA_HW_ACCESS_CLEAR - Not supported - * QDMA_HW_ACCESS_INVALIDATE - Not supported - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -int eqdma_global_writeback_interval_conf(void *dev_hndl, - enum qdma_wrb_interval *wb_int, - enum qdma_hw_access_type access_type) -{ - int rv = QDMA_SUCCESS; - - switch (access_type) { - case QDMA_HW_ACCESS_READ: - rv = eqdma_global_writeback_interval_read(dev_hndl, wb_int); - break; - case QDMA_HW_ACCESS_WRITE: - rv = eqdma_global_writeback_interval_write(dev_hndl, *wb_int); - break; - case QDMA_HW_ACCESS_CLEAR: - case QDMA_HW_ACCESS_INVALIDATE: - default: - qdma_log_error("%s: access_type(%d) invalid, err:%d\n", - __func__, - access_type, - -QDMA_ERR_INV_PARAM); - rv = -QDMA_ERR_INV_PARAM; - break; - } - - return rv; -} - - -/*****************************************************************************/ -/** - * eqdma_mm_channel_conf() - Function to enable/disable the MM channel - * - * @dev_hndl: device handle - * @channel: MM channel number - * @is_c2h: Queue direction. Set 1 for C2H and 0 for H2C - * @enable: Enable or disable MM channel - * - * Presently, we have only 1 MM channel - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -int eqdma_mm_channel_conf(void *dev_hndl, uint8_t channel, uint8_t is_c2h, - uint8_t enable) -{ - uint32_t reg_addr = (is_c2h) ? EQDMA_C2H_MM_CTL_ADDR : - EQDMA_H2C_MM_CTL_ADDR; - struct qdma_dev_attributes dev_cap; - - if (!dev_hndl) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - eqdma_get_device_attributes(dev_hndl, &dev_cap); - - if (dev_cap.mm_en) - qdma_reg_write(dev_hndl, - reg_addr + (channel * QDMA_MM_CONTROL_STEP), - enable); - - - return QDMA_SUCCESS; -} - -int eqdma_dump_reg_info(void *dev_hndl, uint32_t reg_addr, - uint32_t num_regs, char *buf, uint32_t buflen) -{ - uint32_t total_num_regs = eqdma_config_num_regs_get(); - struct xreg_info *config_regs = eqdma_config_regs_get(); - struct qdma_dev_attributes dev_cap; - const char *bitfield_name; - uint32_t i = 0, num_regs_idx = 0, k = 0, j = 0, - bitfield = 0, lsb = 0, msb = 31; - int rv = 0; - uint32_t reg_val; - uint32_t data_len = 0; - - if (!dev_hndl) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - eqdma_get_device_attributes(dev_hndl, &dev_cap); - - for (i = 0; i < total_num_regs; i++) { - if (reg_addr == config_regs[i].addr) { - j = i; - break; - } - } - - if (i == total_num_regs) { - qdma_log_error("%s: Register not found err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - if (buf) - QDMA_SNPRINTF_S(buf, buflen, - DEBGFS_LINE_SZ, - "Register not found 0x%x\n", reg_addr); - - return -QDMA_ERR_INV_PARAM; - } - - num_regs_idx = (j + num_regs < total_num_regs) ? - (j + num_regs) : total_num_regs; - - for (; j < num_regs_idx ; j++) { - reg_val = qdma_reg_read(dev_hndl, - config_regs[j].addr); - - if (buf) { - rv = QDMA_SNPRINTF_S(buf, buflen, - DEBGFS_LINE_SZ, - "\n%-40s 0x%-7x %-#10x %-10d\n", - config_regs[j].name, - config_regs[j].addr, - reg_val, reg_val); - if ((rv < 0) || (rv > DEBGFS_LINE_SZ)) { - qdma_log_error( - "%s: Insufficient buffer, err:%d\n", - __func__, -QDMA_ERR_NO_MEM); - return -QDMA_ERR_NO_MEM; - } - buf += rv; - data_len += rv; - buflen -= rv; - } else - qdma_log_info("%-40s 0x%-7x %-#10x %-10d\n", - config_regs[j].name, - config_regs[j].addr, - reg_val, reg_val); - - - for (k = 0; - k < config_regs[j].num_bitfields; k++) { - /* If Debug Mode not enabled and the current register - * is debug register, skip reading it. - */ - if (dev_cap.debug_mode == 0 && - config_regs[j].is_debug_reg == 1) - continue; - - bitfield = - config_regs[j].bitfields[k].field_mask; - bitfield_name = - config_regs[i].bitfields[k].field_name; - lsb = 0; - msb = 31; - - while (!(BIT(lsb) & bitfield)) - lsb++; - - while (!(BIT(msb) & bitfield)) - msb--; - - if (msb != lsb) { - if (buf) { - rv = QDMA_SNPRINTF_S(buf, buflen, - DEBGFS_LINE_SZ, - "%-40s [%2u,%2u] %#-10x\n", - bitfield_name, - msb, lsb, - (reg_val & bitfield) >> - lsb); - if ((rv < 0) || (rv > DEBGFS_LINE_SZ)) { - qdma_log_error( - "%s: Insufficient buffer, err:%d\n", - __func__, - -QDMA_ERR_NO_MEM); - return -QDMA_ERR_NO_MEM; - } - buf += rv; - data_len += rv; - buflen -= rv; - } else - qdma_log_info( - "%-40s [%2u,%2u] %#-10x\n", - bitfield_name, - msb, lsb, - (reg_val & bitfield) >> lsb); - - - } else { - if (buf) { - rv = QDMA_SNPRINTF_S(buf, buflen, - DEBGFS_LINE_SZ, - "%-40s [%5u] %#-10x\n", - bitfield_name, - lsb, - (reg_val & bitfield) >> - lsb); - if ((rv < 0) || (rv > DEBGFS_LINE_SZ)) { - qdma_log_error( - "%s: Insufficient buffer, err:%d\n", - __func__, - -QDMA_ERR_NO_MEM); - return -QDMA_ERR_NO_MEM; - } - buf += rv; - data_len += rv; - buflen -= rv; - } else - qdma_log_info( - "%-40s [%5u] %#-10x\n", - bitfield_name, - lsb, - (reg_val & bitfield) >> lsb); - - } - } - } - - return data_len; -} diff --git a/QDMA/linux-kernel/driver/libqdma/qdma_access/eqdma_soft_access/eqdma_soft_access.h b/QDMA/linux-kernel/driver/libqdma/qdma_access/eqdma_soft_access/eqdma_soft_access.h deleted file mode 100755 index 4cc8ca96b..000000000 --- a/QDMA/linux-kernel/driver/libqdma/qdma_access/eqdma_soft_access/eqdma_soft_access.h +++ /dev/null @@ -1,345 +0,0 @@ -/* - * Copyright (c) 2019-2022, Xilinx, Inc. All rights reserved. - * Copyright (c) 2022, Advanced Micro Devices, Inc. All rights reserved. - * - * This source code is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * The full GNU General Public License is included in this distribution in - * the file called "COPYING". - */ - -#ifndef __EQDMA_SOFT_ACCESS_H_ -#define __EQDMA_SOFT_ACCESS_H_ - -#ifdef __cplusplus -extern "C" { -#endif - -#include "qdma_platform.h" - -/** - * enum qdma_error_idx - qdma errors - */ -enum eqdma_error_idx { - /* Descriptor errors */ - EQDMA_DSC_ERR_POISON, - EQDMA_DSC_ERR_UR_CA, - EQDMA_DSC_ERR_BCNT, - EQDMA_DSC_ERR_PARAM, - EQDMA_DSC_ERR_ADDR, - EQDMA_DSC_ERR_TAG, - EQDMA_DSC_ERR_FLR, - EQDMA_DSC_ERR_TIMEOUT, - EQDMA_DSC_ERR_DAT_POISON, - EQDMA_DSC_ERR_FLR_CANCEL, - EQDMA_DSC_ERR_DMA, - EQDMA_DSC_ERR_DSC, - EQDMA_DSC_ERR_RQ_CANCEL, - EQDMA_DSC_ERR_DBE, - EQDMA_DSC_ERR_SBE, - EQDMA_DSC_ERR_PORT_ID, - EQDMA_DSC_ERR_ALL, - - /* TRQ Errors */ - EQDMA_TRQ_ERR_CSR_UNMAPPED, - EQDMA_TRQ_ERR_VF_ACCESS, - EQDMA_TRQ_ERR_TCP_CSR_TIMEOUT, - EQDMA_TRQ_ERR_QSPC_UNMAPPED, - EQDMA_TRQ_ERR_QID_RANGE, - EQDMA_TRQ_ERR_TCP_QSPC_TIMEOUT, - EQDMA_TRQ_ERR_ALL, - - /* C2H Errors */ - EQDMA_ST_C2H_ERR_MTY_MISMATCH, - EQDMA_ST_C2H_ERR_LEN_MISMATCH, - EQDMA_ST_C2H_ERR_SH_CMPT_DSC, - EQDMA_ST_C2H_ERR_QID_MISMATCH, - EQDMA_ST_C2H_ERR_DESC_RSP_ERR, - EQDMA_ST_C2H_ERR_ENG_WPL_DATA_PAR_ERR, - EQDMA_ST_C2H_ERR_MSI_INT_FAIL, - EQDMA_ST_C2H_ERR_ERR_DESC_CNT, - EQDMA_ST_C2H_ERR_PORTID_CTXT_MISMATCH, - EQDMA_ST_C2H_ERR_CMPT_INV_Q_ERR, - EQDMA_ST_C2H_ERR_CMPT_QFULL_ERR, - EQDMA_ST_C2H_ERR_CMPT_CIDX_ERR, - EQDMA_ST_C2H_ERR_CMPT_PRTY_ERR, - EQDMA_ST_C2H_ERR_AVL_RING_DSC, - EQDMA_ST_C2H_ERR_HDR_ECC_UNC, - EQDMA_ST_C2H_ERR_HDR_ECC_COR, - EQDMA_ST_C2H_ERR_WRB_PORT_ID_ERR, - EQDMA_ST_C2H_ERR_ALL, - - /* Fatal Errors */ - EQDMA_ST_FATAL_ERR_MTY_MISMATCH, - EQDMA_ST_FATAL_ERR_LEN_MISMATCH, - EQDMA_ST_FATAL_ERR_QID_MISMATCH, - EQDMA_ST_FATAL_ERR_TIMER_FIFO_RAM_RDBE, - EQDMA_ST_FATAL_ERR_PFCH_II_RAM_RDBE, - EQDMA_ST_FATAL_ERR_CMPT_CTXT_RAM_RDBE, - EQDMA_ST_FATAL_ERR_PFCH_CTXT_RAM_RDBE, - EQDMA_ST_FATAL_ERR_DESC_REQ_FIFO_RAM_RDBE, - EQDMA_ST_FATAL_ERR_INT_CTXT_RAM_RDBE, - EQDMA_ST_FATAL_ERR_CMPT_COAL_DATA_RAM_RDBE, - EQDMA_ST_FATAL_ERR_CMPT_FIFO_RAM_RDBE, - EQDMA_ST_FATAL_ERR_QID_FIFO_RAM_RDBE, - EQDMA_ST_FATAL_ERR_PAYLOAD_FIFO_RAM_RDBE, - EQDMA_ST_FATAL_ERR_WPL_DATA_PAR, - EQDMA_ST_FATAL_ERR_AVL_RING_FIFO_RAM_RDBE, - EQDMA_ST_FATAL_ERR_HDR_ECC_UNC, - EQDMA_ST_FATAL_ERR_ALL, - - /* H2C Errors */ - EQDMA_ST_H2C_ERR_ZERO_LEN_DESC, - EQDMA_ST_H2C_ERR_SDI_MRKR_REQ_MOP, - EQDMA_ST_H2C_ERR_NO_DMA_DSC, - EQDMA_ST_H2C_ERR_SBE, - EQDMA_ST_H2C_ERR_DBE, - EQDMA_ST_H2C_ERR_PAR, - EQDMA_ST_H2C_ERR_ALL, - - /* Single bit errors */ - EQDMA_SBE_1_ERR_RC_RRQ_EVEN_RAM, - EQDMA_SBE_1_ERR_TAG_ODD_RAM, - EQDMA_SBE_1_ERR_TAG_EVEN_RAM, - EQDMA_SBE_1_ERR_PFCH_CTXT_CAM_RAM_0, - EQDMA_SBE_1_ERR_PFCH_CTXT_CAM_RAM_1, - EQDMA_SBE_1_ERR_ALL, - - /* Single bit errors */ - EQDMA_SBE_ERR_MI_H2C0_DAT, - EQDMA_SBE_ERR_MI_H2C1_DAT, - EQDMA_SBE_ERR_MI_H2C2_DAT, - EQDMA_SBE_ERR_MI_H2C3_DAT, - EQDMA_SBE_ERR_MI_C2H0_DAT, - EQDMA_SBE_ERR_MI_C2H1_DAT, - EQDMA_SBE_ERR_MI_C2H2_DAT, - EQDMA_SBE_ERR_MI_C2H3_DAT, - EQDMA_SBE_ERR_H2C_RD_BRG_DAT, - EQDMA_SBE_ERR_H2C_WR_BRG_DAT, - EQDMA_SBE_ERR_C2H_RD_BRG_DAT, - EQDMA_SBE_ERR_C2H_WR_BRG_DAT, - EQDMA_SBE_ERR_FUNC_MAP, - EQDMA_SBE_ERR_DSC_HW_CTXT, - EQDMA_SBE_ERR_DSC_CRD_RCV, - EQDMA_SBE_ERR_DSC_SW_CTXT, - EQDMA_SBE_ERR_DSC_CPLI, - EQDMA_SBE_ERR_DSC_CPLD, - EQDMA_SBE_ERR_MI_TL_SLV_FIFO_RAM, - EQDMA_SBE_ERR_TIMER_FIFO_RAM, - EQDMA_SBE_ERR_QID_FIFO_RAM, - EQDMA_SBE_ERR_WRB_COAL_DATA_RAM, - EQDMA_SBE_ERR_INT_CTXT_RAM, - EQDMA_SBE_ERR_DESC_REQ_FIFO_RAM, - EQDMA_SBE_ERR_PFCH_CTXT_RAM, - EQDMA_SBE_ERR_WRB_CTXT_RAM, - EQDMA_SBE_ERR_PFCH_LL_RAM, - EQDMA_SBE_ERR_PEND_FIFO_RAM, - EQDMA_SBE_ERR_RC_RRQ_ODD_RAM, - EQDMA_SBE_ERR_ALL, - - /* Double bit Errors */ - EQDMA_DBE_1_ERR_RC_RRQ_EVEN_RAM, - EQDMA_DBE_1_ERR_TAG_ODD_RAM, - EQDMA_DBE_1_ERR_TAG_EVEN_RAM, - EQDMA_DBE_1_ERR_PFCH_CTXT_CAM_RAM_0, - EQDMA_DBE_1_ERR_PFCH_CTXT_CAM_RAM_1, - EQDMA_DBE_1_ERR_ALL, - - /* Double bit Errors */ - EQDMA_DBE_ERR_MI_H2C0_DAT, - EQDMA_DBE_ERR_MI_H2C1_DAT, - EQDMA_DBE_ERR_MI_H2C2_DAT, - EQDMA_DBE_ERR_MI_H2C3_DAT, - EQDMA_DBE_ERR_MI_C2H0_DAT, - EQDMA_DBE_ERR_MI_C2H1_DAT, - EQDMA_DBE_ERR_MI_C2H2_DAT, - EQDMA_DBE_ERR_MI_C2H3_DAT, - EQDMA_DBE_ERR_H2C_RD_BRG_DAT, - EQDMA_DBE_ERR_H2C_WR_BRG_DAT, - EQDMA_DBE_ERR_C2H_RD_BRG_DAT, - EQDMA_DBE_ERR_C2H_WR_BRG_DAT, - EQDMA_DBE_ERR_FUNC_MAP, - EQDMA_DBE_ERR_DSC_HW_CTXT, - EQDMA_DBE_ERR_DSC_CRD_RCV, - EQDMA_DBE_ERR_DSC_SW_CTXT, - EQDMA_DBE_ERR_DSC_CPLI, - EQDMA_DBE_ERR_DSC_CPLD, - EQDMA_DBE_ERR_MI_TL_SLV_FIFO_RAM, - EQDMA_DBE_ERR_TIMER_FIFO_RAM, - EQDMA_DBE_ERR_QID_FIFO_RAM, - EQDMA_DBE_ERR_WRB_COAL_DATA_RAM, - EQDMA_DBE_ERR_INT_CTXT_RAM, - EQDMA_DBE_ERR_DESC_REQ_FIFO_RAM, - EQDMA_DBE_ERR_PFCH_CTXT_RAM, - EQDMA_DBE_ERR_WRB_CTXT_RAM, - EQDMA_DBE_ERR_PFCH_LL_RAM, - EQDMA_DBE_ERR_PEND_FIFO_RAM, - EQDMA_DBE_ERR_RC_RRQ_ODD_RAM, - EQDMA_DBE_ERR_ALL, - - /* MM C2H Errors */ - EQDMA_MM_C2H_WR_SLR_ERR, - EQDMA_MM_C2H_RD_SLR_ERR, - EQDMA_MM_C2H_WR_FLR_ERR, - EQDMA_MM_C2H_UR_ERR, - EQDMA_MM_C2H_WR_UC_RAM_ERR, - EQDMA_MM_C2H_ERR_ALL, - - /* MM H2C Engine0 Errors */ - EQDMA_MM_H2C0_RD_HDR_POISON_ERR, - EQDMA_MM_H2C0_RD_UR_CA_ERR, - EQDMA_MM_H2C0_RD_HDR_BYTE_ERR, - EQDMA_MM_H2C0_RD_HDR_PARAM_ERR, - EQDMA_MM_H2C0_RD_HDR_ADR_ERR, - EQDMA_MM_H2C0_RD_FLR_ERR, - EQDMA_MM_H2C0_RD_DAT_POISON_ERR, - EQDMA_MM_H2C0_RD_RQ_DIS_ERR, - EQDMA_MM_H2C0_WR_DEC_ERR, - EQDMA_MM_H2C0_WR_SLV_ERR, - EQDMA_MM_H2C0_ERR_ALL, - - EQDMA_ERRS_ALL -}; - -struct eqdma_hw_err_info { - enum eqdma_error_idx idx; - const char *err_name; - uint32_t mask_reg_addr; - uint32_t stat_reg_addr; - uint32_t leaf_err_mask; - uint32_t global_err_mask; - void (*eqdma_hw_err_process)(void *dev_hndl); -}; - -/* In QDMA_GLBL2_MISC_CAP(0x134) register, - * Bits [23:20] gives QDMA IP version. - * 0: QDMA3.1, 1: QDMA4.0, 2: QDMA5.0 - */ -#define EQDMA_IP_VERSION_4 1 -#define EQDMA_IP_VERSION_5 2 - -#define EQDMA_OFFSET_VF_VERSION 0x5014 -#define EQDMA_OFFSET_VF_USER_BAR 0x5018 - -#define EQDMA_OFFSET_MBOX_BASE_PF 0x22400 -#define EQDMA_OFFSET_MBOX_BASE_VF 0x5000 - -#define EQDMA_COMPL_CTXT_BADDR_HIGH_H_MASK GENMASK_ULL(63, 38) -#define EQDMA_COMPL_CTXT_BADDR_HIGH_L_MASK GENMASK_ULL(37, 6) -#define EQDMA_COMPL_CTXT_BADDR_LOW_MASK GENMASK_ULL(5, 2) - -int eqdma_init_ctxt_memory(void *dev_hndl); - -int eqdma_get_version(void *dev_hndl, uint8_t is_vf, - struct qdma_hw_version_info *version_info); - -int eqdma_get_ip_version(void *dev_hndl, uint8_t is_vf, - uint32_t *ip_version); - -int eqdma_sw_ctx_conf(void *dev_hndl, uint8_t c2h, uint16_t hw_qid, - struct qdma_descq_sw_ctxt *ctxt, - enum qdma_hw_access_type access_type); - -int eqdma_hw_ctx_conf(void *dev_hndl, uint8_t c2h, uint16_t hw_qid, - struct qdma_descq_hw_ctxt *ctxt, - enum qdma_hw_access_type access_type); - -int eqdma_credit_ctx_conf(void *dev_hndl, uint8_t c2h, - uint16_t hw_qid, struct qdma_descq_credit_ctxt *ctxt, - enum qdma_hw_access_type access_type); - -int eqdma_pfetch_ctx_conf(void *dev_hndl, uint16_t hw_qid, - struct qdma_descq_prefetch_ctxt *ctxt, - enum qdma_hw_access_type access_type); - -int eqdma_cmpt_ctx_conf(void *dev_hndl, uint16_t hw_qid, - struct qdma_descq_cmpt_ctxt *ctxt, - enum qdma_hw_access_type access_type); - -int eqdma_fmap_conf(void *dev_hndl, uint16_t func_id, - struct qdma_fmap_cfg *config, - enum qdma_hw_access_type access_type); - -int eqdma_indirect_intr_ctx_conf(void *dev_hndl, uint16_t ring_index, - struct qdma_indirect_intr_ctxt *ctxt, - enum qdma_hw_access_type access_type); - -int eqdma_dump_config_regs(void *dev_hndl, uint8_t is_vf, - char *buf, uint32_t buflen); - -int eqdma_dump_intr_context(void *dev_hndl, - struct qdma_indirect_intr_ctxt *intr_ctx, - int ring_index, - char *buf, uint32_t buflen); - -int eqdma_dump_queue_context(void *dev_hndl, - uint8_t st, - enum qdma_dev_q_type q_type, - struct qdma_descq_context *ctxt_data, - char *buf, uint32_t buflen); - -uint32_t eqdma_reg_dump_buf_len(void); - -int eqdma_context_buf_len(uint8_t st, - enum qdma_dev_q_type q_type, uint32_t *buflen); - -int eqdma_hw_error_process(void *dev_hndl); -const char *eqdma_hw_get_error_name(uint32_t err_idx); -int eqdma_hw_error_enable(void *dev_hndl, uint32_t err_idx); - -int eqdma_read_dump_queue_context(void *dev_hndl, - uint16_t func_id, - uint16_t qid_hw, - uint8_t st, - enum qdma_dev_q_type q_type, - char *buf, uint32_t buflen); - -int eqdma_get_device_attributes(void *dev_hndl, - struct qdma_dev_attributes *dev_info); - -int eqdma_get_user_bar(void *dev_hndl, uint8_t is_vf, - uint16_t func_id, uint8_t *user_bar); - -int eqdma_dump_config_reg_list(void *dev_hndl, - uint32_t total_regs, - struct qdma_reg_data *reg_list, - char *buf, uint32_t buflen); - -int eqdma_read_reg_list(void *dev_hndl, uint8_t is_vf, - uint16_t reg_rd_group, - uint16_t *total_regs, - struct qdma_reg_data *reg_list); - -int eqdma_set_default_global_csr(void *dev_hndl); - -int eqdma_global_csr_conf(void *dev_hndl, uint8_t index, uint8_t count, - uint32_t *csr_val, - enum qdma_global_csr_type csr_type, - enum qdma_hw_access_type access_type); - -int eqdma_global_writeback_interval_conf(void *dev_hndl, - enum qdma_wrb_interval *wb_int, - enum qdma_hw_access_type access_type); - -int eqdma_mm_channel_conf(void *dev_hndl, uint8_t channel, uint8_t is_c2h, - uint8_t enable); - -int eqdma_dump_reg_info(void *dev_hndl, uint32_t reg_addr, - uint32_t num_regs, char *buf, uint32_t buflen); - -uint32_t eqdma_get_config_num_regs(void); - -struct xreg_info *eqdma_get_config_regs(void); - -#ifdef __cplusplus -} -#endif - -#endif /* __EQDMA_SOFT_ACCESS_H_ */ diff --git a/QDMA/linux-kernel/driver/libqdma/qdma_access/eqdma_soft_access/eqdma_soft_reg.h b/QDMA/linux-kernel/driver/libqdma/qdma_access/eqdma_soft_access/eqdma_soft_reg.h deleted file mode 100755 index 0905d5093..000000000 --- a/QDMA/linux-kernel/driver/libqdma/qdma_access/eqdma_soft_access/eqdma_soft_reg.h +++ /dev/null @@ -1,1524 +0,0 @@ -/* - * Copyright (c) 2019-2022 Xilinx, Inc. All rights reserved. - * Copyright (c) 2022, Advanced Micro Devices, Inc. All rights reserved. - * - * This source code is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * The full GNU General Public License is included in this distribution in - * the file called "COPYING". - */ - -#ifndef __EQDMA_SOFT_REG_H -#define __EQDMA_SOFT_REG_H - - -#ifdef __cplusplus -extern "C" { -#endif - -#include "qdma_platform.h" - -#ifdef CHAR_BIT -#undef CHAR_BIT -#endif -#define CHAR_BIT 8 - -#ifdef BIT -#undef BIT -#endif -#define BIT(n) (1u << (n)) - -#ifdef BITS_PER_BYTE -#undef BITS_PER_BYTE -#endif -#define BITS_PER_BYTE CHAR_BIT - -#ifdef BITS_PER_LONG -#undef BITS_PER_LONG -#endif -#define BITS_PER_LONG (sizeof(uint32_t) * BITS_PER_BYTE) - -#ifdef BITS_PER_LONG_LONG -#undef BITS_PER_LONG_LONG -#endif -#define BITS_PER_LONG_LONG (sizeof(uint64_t) * BITS_PER_BYTE) - -#ifdef GENMASK -#undef GENMASK -#endif -#define GENMASK(h, l) \ - ((0xFFFFFFFF << (l)) & (0xFFFFFFFF >> (BITS_PER_LONG - 1 - (h)))) - -#ifdef GENMASK_ULL -#undef GENMASK_ULL -#endif -#define GENMASK_ULL(h, l) \ - ((0xFFFFFFFFFFFFFFFF << (l)) & \ - (0xFFFFFFFFFFFFFFFF >> (BITS_PER_LONG_LONG - 1 - (h)))) - -#define DEBGFS_LINE_SZ (81) - -#ifdef ARRAY_SIZE -#undef ARRAY_SIZE -#endif -#define ARRAY_SIZE(arr) (sizeof(arr) / \ - sizeof(arr[0])) - - -uint32_t eqdma_config_num_regs_get(void); -struct xreg_info *eqdma_config_regs_get(void); -#define EQDMA_CFG_BLK_IDENTIFIER_ADDR 0x00 -#define CFG_BLK_IDENTIFIER_MASK GENMASK(31, 20) -#define CFG_BLK_IDENTIFIER_1_MASK GENMASK(19, 16) -#define CFG_BLK_IDENTIFIER_RSVD_1_MASK GENMASK(15, 8) -#define CFG_BLK_IDENTIFIER_VERSION_MASK GENMASK(7, 0) -#define EQDMA_CFG_BLK_PCIE_MAX_PLD_SIZE_ADDR 0x08 -#define CFG_BLK_PCIE_MAX_PLD_SIZE_RSVD_1_MASK GENMASK(31, 7) -#define CFG_BLK_PCIE_MAX_PLD_SIZE_PROG_MASK GENMASK(6, 4) -#define CFG_BLK_PCIE_MAX_PLD_SIZE_RSVD_2_MASK BIT(3) -#define CFG_BLK_PCIE_MAX_PLD_SIZE_ISSUED_MASK GENMASK(2, 0) -#define EQDMA_CFG_BLK_PCIE_MAX_READ_REQ_SIZE_ADDR 0x0C -#define CFG_BLK_PCIE_MAX_READ_REQ_SIZE_RSVD_1_MASK GENMASK(31, 7) -#define CFG_BLK_PCIE_MAX_READ_REQ_SIZE_PROG_MASK GENMASK(6, 4) -#define CFG_BLK_PCIE_MAX_READ_REQ_SIZE_RSVD_2_MASK BIT(3) -#define CFG_BLK_PCIE_MAX_READ_REQ_SIZE_ISSUED_MASK GENMASK(2, 0) -#define EQDMA_CFG_BLK_SYSTEM_ID_ADDR 0x10 -#define CFG_BLK_SYSTEM_ID_RSVD_1_MASK GENMASK(31, 17) -#define CFG_BLK_SYSTEM_ID_INST_TYPE_MASK BIT(16) -#define CFG_BLK_SYSTEM_ID_MASK GENMASK(15, 0) -#define EQDMA_CFG_BLK_MSIX_ENABLE_ADDR 0x014 -#define CFG_BLK_MSIX_ENABLE_MASK GENMASK(31, 0) -#define EQDMA_CFG_PCIE_DATA_WIDTH_ADDR 0x18 -#define CFG_PCIE_DATA_WIDTH_RSVD_1_MASK GENMASK(31, 3) -#define CFG_PCIE_DATA_WIDTH_DATAPATH_MASK GENMASK(2, 0) -#define EQDMA_CFG_PCIE_CTL_ADDR 0x1C -#define CFG_PCIE_CTL_RSVD_1_MASK GENMASK(31, 18) -#define CFG_PCIE_CTL_MGMT_AXIL_CTRL_MASK GENMASK(17, 16) -#define CFG_PCIE_CTL_RSVD_2_MASK GENMASK(15, 2) -#define CFG_PCIE_CTL_RRQ_DISABLE_MASK BIT(1) -#define CFG_PCIE_CTL_RELAXED_ORDERING_MASK BIT(0) -#define EQDMA_CFG_BLK_MSI_ENABLE_ADDR 0x20 -#define CFG_BLK_MSI_ENABLE_MASK GENMASK(31, 0) -#define EQDMA_CFG_AXI_USER_MAX_PLD_SIZE_ADDR 0x40 -#define CFG_AXI_USER_MAX_PLD_SIZE_RSVD_1_MASK GENMASK(31, 7) -#define CFG_AXI_USER_MAX_PLD_SIZE_ISSUED_MASK GENMASK(6, 4) -#define CFG_AXI_USER_MAX_PLD_SIZE_RSVD_2_MASK BIT(3) -#define CFG_AXI_USER_MAX_PLD_SIZE_PROG_MASK GENMASK(2, 0) -#define EQDMA_CFG_AXI_USER_MAX_READ_REQ_SIZE_ADDR 0x44 -#define CFG_AXI_USER_MAX_READ_REQ_SIZE_RSVD_1_MASK GENMASK(31, 7) -#define CFG_AXI_USER_MAX_READ_REQ_SIZE_USISSUED_MASK GENMASK(6, 4) -#define CFG_AXI_USER_MAX_READ_REQ_SIZE_RSVD_2_MASK BIT(3) -#define CFG_AXI_USER_MAX_READ_REQ_SIZE_USPROG_MASK GENMASK(2, 0) -#define EQDMA_CFG_BLK_MISC_CTL_ADDR 0x4C -#define CFG_BLK_MISC_CTL_RSVD_1_MASK GENMASK(31, 24) -#define CFG_BLK_MISC_CTL_10B_TAG_EN_MASK BIT(23) -#define CFG_BLK_MISC_CTL_RSVD_2_MASK BIT(22) -#define CFG_BLK_MISC_CTL_AXI_WBK_MASK BIT(21) -#define CFG_BLK_MISC_CTL_AXI_DSC_MASK BIT(20) -#define CFG_BLK_MISC_CTL_NUM_TAG_MASK GENMASK(19, 8) -#define CFG_BLK_MISC_CTL_RSVD_3_MASK GENMASK(7, 5) -#define CFG_BLK_MISC_CTL_RQ_METERING_MULTIPLIER_MASK GENMASK(4, 0) -#define EQDMA_CFG_PL_CRED_CTL_ADDR 0x68 -#define CFG_PL_CRED_CTL_RSVD_1_MASK GENMASK(31, 5) -#define CFG_PL_CRED_CTL_SLAVE_CRD_RLS_MASK BIT(4) -#define CFG_PL_CRED_CTL_RSVD_2_MASK GENMASK(3, 1) -#define CFG_PL_CRED_CTL_MASTER_CRD_RST_MASK BIT(0) -#define EQDMA_CFG_BLK_SCRATCH_ADDR 0x80 -#define CFG_BLK_SCRATCH_MASK GENMASK(31, 0) -#define EQDMA_CFG_GIC_ADDR 0xA0 -#define CFG_GIC_RSVD_1_MASK GENMASK(31, 1) -#define CFG_GIC_GIC_IRQ_MASK BIT(0) -#define EQDMA_RAM_SBE_MSK_1_A_ADDR 0xE0 -#define RAM_SBE_MSK_1_A_MASK GENMASK(31, 0) -#define EQDMA_RAM_SBE_STS_1_A_ADDR 0xE4 -#define RAM_SBE_STS_1_A_RSVD_MASK GENMASK(31, 5) -#define RAM_SBE_STS_1_A_PFCH_CTXT_CAM_RAM_1_MASK BIT(4) -#define RAM_SBE_STS_1_A_PFCH_CTXT_CAM_RAM_0_MASK BIT(3) -#define RAM_SBE_STS_1_A_TAG_EVEN_RAM_MASK BIT(2) -#define RAM_SBE_STS_1_A_TAG_ODD_RAM_MASK BIT(1) -#define RAM_SBE_STS_1_A_RC_RRQ_EVEN_RAM_MASK BIT(0) -#define EQDMA_RAM_DBE_MSK_1_A_ADDR 0xE8 -#define RAM_DBE_MSK_1_A_MASK GENMASK(31, 0) -#define EQDMA_RAM_DBE_STS_1_A_ADDR 0xEC -#define RAM_DBE_STS_1_A_RSVD_MASK GENMASK(31, 5) -#define RAM_DBE_STS_1_A_PFCH_CTXT_CAM_RAM_1_MASK BIT(4) -#define RAM_DBE_STS_1_A_PFCH_CTXT_CAM_RAM_0_MASK BIT(3) -#define RAM_DBE_STS_1_A_TAG_EVEN_RAM_MASK BIT(2) -#define RAM_DBE_STS_1_A_TAG_ODD_RAM_MASK BIT(1) -#define RAM_DBE_STS_1_A_RC_RRQ_EVEN_RAM_MASK BIT(0) -#define EQDMA_RAM_SBE_MSK_A_ADDR 0xF0 -#define RAM_SBE_MSK_A_MASK GENMASK(31, 0) -#define EQDMA_RAM_SBE_STS_A_ADDR 0xF4 -#define RAM_SBE_STS_A_RC_RRQ_ODD_RAM_MASK BIT(31) -#define RAM_SBE_STS_A_PEND_FIFO_RAM_MASK BIT(30) -#define RAM_SBE_STS_A_PFCH_LL_RAM_MASK BIT(29) -#define RAM_SBE_STS_A_WRB_CTXT_RAM_MASK BIT(28) -#define RAM_SBE_STS_A_PFCH_CTXT_RAM_MASK BIT(27) -#define RAM_SBE_STS_A_DESC_REQ_FIFO_RAM_MASK BIT(26) -#define RAM_SBE_STS_A_INT_CTXT_RAM_MASK BIT(25) -#define RAM_SBE_STS_A_WRB_COAL_DATA_RAM_MASK BIT(24) -#define RAM_SBE_STS_A_QID_FIFO_RAM_MASK BIT(23) -#define RAM_SBE_STS_A_TIMER_FIFO_RAM_MASK GENMASK(22, 19) -#define RAM_SBE_STS_A_MI_TL_SLV_FIFO_RAM_MASK BIT(18) -#define RAM_SBE_STS_A_DSC_CPLD_MASK BIT(17) -#define RAM_SBE_STS_A_DSC_CPLI_MASK BIT(16) -#define RAM_SBE_STS_A_DSC_SW_CTXT_MASK BIT(15) -#define RAM_SBE_STS_A_DSC_CRD_RCV_MASK BIT(14) -#define RAM_SBE_STS_A_DSC_HW_CTXT_MASK BIT(13) -#define RAM_SBE_STS_A_FUNC_MAP_MASK BIT(12) -#define RAM_SBE_STS_A_C2H_WR_BRG_DAT_MASK BIT(11) -#define RAM_SBE_STS_A_C2H_RD_BRG_DAT_MASK BIT(10) -#define RAM_SBE_STS_A_H2C_WR_BRG_DAT_MASK BIT(9) -#define RAM_SBE_STS_A_H2C_RD_BRG_DAT_MASK BIT(8) -#define RAM_SBE_STS_A_MI_C2H3_DAT_MASK BIT(7) -#define RAM_SBE_STS_A_MI_C2H2_DAT_MASK BIT(6) -#define RAM_SBE_STS_A_MI_C2H1_DAT_MASK BIT(5) -#define RAM_SBE_STS_A_MI_C2H0_DAT_MASK BIT(4) -#define RAM_SBE_STS_A_MI_H2C3_DAT_MASK BIT(3) -#define RAM_SBE_STS_A_MI_H2C2_DAT_MASK BIT(2) -#define RAM_SBE_STS_A_MI_H2C1_DAT_MASK BIT(1) -#define RAM_SBE_STS_A_MI_H2C0_DAT_MASK BIT(0) -#define EQDMA_RAM_DBE_MSK_A_ADDR 0xF8 -#define RAM_DBE_MSK_A_MASK GENMASK(31, 0) -#define EQDMA_RAM_DBE_STS_A_ADDR 0xFC -#define RAM_DBE_STS_A_RC_RRQ_ODD_RAM_MASK BIT(31) -#define RAM_DBE_STS_A_PEND_FIFO_RAM_MASK BIT(30) -#define RAM_DBE_STS_A_PFCH_LL_RAM_MASK BIT(29) -#define RAM_DBE_STS_A_WRB_CTXT_RAM_MASK BIT(28) -#define RAM_DBE_STS_A_PFCH_CTXT_RAM_MASK BIT(27) -#define RAM_DBE_STS_A_DESC_REQ_FIFO_RAM_MASK BIT(26) -#define RAM_DBE_STS_A_INT_CTXT_RAM_MASK BIT(25) -#define RAM_DBE_STS_A_WRB_COAL_DATA_RAM_MASK BIT(24) -#define RAM_DBE_STS_A_QID_FIFO_RAM_MASK BIT(23) -#define RAM_DBE_STS_A_TIMER_FIFO_RAM_MASK GENMASK(22, 19) -#define RAM_DBE_STS_A_MI_TL_SLV_FIFO_RAM_MASK BIT(18) -#define RAM_DBE_STS_A_DSC_CPLD_MASK BIT(17) -#define RAM_DBE_STS_A_DSC_CPLI_MASK BIT(16) -#define RAM_DBE_STS_A_DSC_SW_CTXT_MASK BIT(15) -#define RAM_DBE_STS_A_DSC_CRD_RCV_MASK BIT(14) -#define RAM_DBE_STS_A_DSC_HW_CTXT_MASK BIT(13) -#define RAM_DBE_STS_A_FUNC_MAP_MASK BIT(12) -#define RAM_DBE_STS_A_C2H_WR_BRG_DAT_MASK BIT(11) -#define RAM_DBE_STS_A_C2H_RD_BRG_DAT_MASK BIT(10) -#define RAM_DBE_STS_A_H2C_WR_BRG_DAT_MASK BIT(9) -#define RAM_DBE_STS_A_H2C_RD_BRG_DAT_MASK BIT(8) -#define RAM_DBE_STS_A_MI_C2H3_DAT_MASK BIT(7) -#define RAM_DBE_STS_A_MI_C2H2_DAT_MASK BIT(6) -#define RAM_DBE_STS_A_MI_C2H1_DAT_MASK BIT(5) -#define RAM_DBE_STS_A_MI_C2H0_DAT_MASK BIT(4) -#define RAM_DBE_STS_A_MI_H2C3_DAT_MASK BIT(3) -#define RAM_DBE_STS_A_MI_H2C2_DAT_MASK BIT(2) -#define RAM_DBE_STS_A_MI_H2C1_DAT_MASK BIT(1) -#define RAM_DBE_STS_A_MI_H2C0_DAT_MASK BIT(0) -#define EQDMA_GLBL2_IDENTIFIER_ADDR 0x100 -#define GLBL2_IDENTIFIER_MASK GENMASK(31, 8) -#define GLBL2_IDENTIFIER_VERSION_MASK GENMASK(7, 0) -#define EQDMA_GLBL2_CHANNEL_INST_ADDR 0x114 -#define GLBL2_CHANNEL_INST_RSVD_1_MASK GENMASK(31, 18) -#define GLBL2_CHANNEL_INST_C2H_ST_MASK BIT(17) -#define GLBL2_CHANNEL_INST_H2C_ST_MASK BIT(16) -#define GLBL2_CHANNEL_INST_RSVD_2_MASK GENMASK(15, 12) -#define GLBL2_CHANNEL_INST_C2H_ENG_MASK GENMASK(11, 8) -#define GLBL2_CHANNEL_INST_RSVD_3_MASK GENMASK(7, 4) -#define GLBL2_CHANNEL_INST_H2C_ENG_MASK GENMASK(3, 0) -#define EQDMA_GLBL2_CHANNEL_MDMA_ADDR 0x118 -#define GLBL2_CHANNEL_MDMA_RSVD_1_MASK GENMASK(31, 18) -#define GLBL2_CHANNEL_MDMA_C2H_ST_MASK BIT(17) -#define GLBL2_CHANNEL_MDMA_H2C_ST_MASK BIT(16) -#define GLBL2_CHANNEL_MDMA_RSVD_2_MASK GENMASK(15, 12) -#define GLBL2_CHANNEL_MDMA_C2H_ENG_MASK GENMASK(11, 8) -#define GLBL2_CHANNEL_MDMA_RSVD_3_MASK GENMASK(7, 4) -#define GLBL2_CHANNEL_MDMA_H2C_ENG_MASK GENMASK(3, 0) -#define EQDMA_GLBL2_CHANNEL_STRM_ADDR 0x11C -#define GLBL2_CHANNEL_STRM_RSVD_1_MASK GENMASK(31, 18) -#define GLBL2_CHANNEL_STRM_C2H_ST_MASK BIT(17) -#define GLBL2_CHANNEL_STRM_H2C_ST_MASK BIT(16) -#define GLBL2_CHANNEL_STRM_RSVD_2_MASK GENMASK(15, 12) -#define GLBL2_CHANNEL_STRM_C2H_ENG_MASK GENMASK(11, 8) -#define GLBL2_CHANNEL_STRM_RSVD_3_MASK GENMASK(7, 4) -#define GLBL2_CHANNEL_STRM_H2C_ENG_MASK GENMASK(3, 0) -#define EQDMA_GLBL2_CHANNEL_CAP_ADDR 0x120 -#define GLBL2_CHANNEL_CAP_RSVD_1_MASK GENMASK(31, 12) -#define GLBL2_CHANNEL_CAP_MULTIQ_MAX_MASK GENMASK(11, 0) -#define EQDMA_GLBL2_CHANNEL_PASID_CAP_ADDR 0x128 -#define GLBL2_CHANNEL_PASID_CAP_RSVD_1_MASK GENMASK(31, 2) -#define GLBL2_CHANNEL_PASID_CAP_BRIDGEEN_MASK BIT(1) -#define GLBL2_CHANNEL_PASID_CAP_DMAEN_MASK BIT(0) -#define EQDMA_GLBL2_SYSTEM_ID_ADDR 0x130 -#define GLBL2_SYSTEM_ID_RSVD_1_MASK GENMASK(31, 16) -#define GLBL2_SYSTEM_ID_MASK GENMASK(15, 0) -#define EQDMA_GLBL2_MISC_CAP_ADDR 0x134 -#define GLBL2_MISC_CAP_MASK GENMASK(31, 0) -#define EQDMA_GLBL2_RRQ_BRG_THROT_ADDR 0x158 -#define GLBL2_RRQ_BRG_THROT_REQ_EN_MASK BIT(31) -#define GLBL2_RRQ_BRG_THROT_REQ_MASK GENMASK(30, 19) -#define GLBL2_RRQ_BRG_THROT_DAT_EN_MASK BIT(18) -#define GLBL2_RRQ_BRG_THROT_DAT_MASK GENMASK(17, 0) -#define EQDMA_GLBL2_RRQ_PCIE_THROT_ADDR 0x15C -#define GLBL2_RRQ_PCIE_THROT_REQ_EN_MASK BIT(31) -#define GLBL2_RRQ_PCIE_THROT_REQ_MASK GENMASK(30, 19) -#define GLBL2_RRQ_PCIE_THROT_DAT_EN_MASK BIT(18) -#define GLBL2_RRQ_PCIE_THROT_DAT_MASK GENMASK(17, 0) -#define EQDMA_GLBL2_RRQ_AXIMM_THROT_ADDR 0x160 -#define GLBL2_RRQ_AXIMM_THROT_REQ_EN_MASK BIT(31) -#define GLBL2_RRQ_AXIMM_THROT_REQ_MASK GENMASK(30, 19) -#define GLBL2_RRQ_AXIMM_THROT_DAT_EN_MASK BIT(18) -#define GLBL2_RRQ_AXIMM_THROT_DAT_MASK GENMASK(17, 0) -#define EQDMA_GLBL2_RRQ_PCIE_LAT0_ADDR 0x164 -#define GLBL2_RRQ_PCIE_LAT0_MAX_MASK GENMASK(31, 16) -#define GLBL2_RRQ_PCIE_LAT0_MIN_MASK GENMASK(15, 0) -#define EQDMA_GLBL2_RRQ_PCIE_LAT1_ADDR 0x168 -#define GLBL2_RRQ_PCIE_LAT1_RSVD_MASK GENMASK(31, 17) -#define GLBL2_RRQ_PCIE_LAT1_OVFL_MASK BIT(16) -#define GLBL2_RRQ_PCIE_LAT1_AVG_MASK GENMASK(15, 0) -#define EQDMA_GLBL2_RRQ_AXIMM_LAT0_ADDR 0x16C -#define GLBL2_RRQ_AXIMM_LAT0_MAX_MASK GENMASK(31, 16) -#define GLBL2_RRQ_AXIMM_LAT0_MIN_MASK GENMASK(15, 0) -#define EQDMA_GLBL2_RRQ_AXIMM_LAT1_ADDR 0x170 -#define GLBL2_RRQ_AXIMM_LAT1_RSVD_MASK GENMASK(31, 17) -#define GLBL2_RRQ_AXIMM_LAT1_OVFL_MASK BIT(16) -#define GLBL2_RRQ_AXIMM_LAT1_AVG_MASK GENMASK(15, 0) -#define EQDMA_GLBL2_DBG_PCIE_RQ0_ADDR 0x1B8 -#define GLBL2_PCIE_RQ0_NPH_AVL_MASK GENMASK(31, 20) -#define GLBL2_PCIE_RQ0_RCB_AVL_MASK GENMASK(19, 9) -#define GLBL2_PCIE_RQ0_SLV_RD_CREDS_MASK GENMASK(8, 2) -#define GLBL2_PCIE_RQ0_TAG_EP_MASK GENMASK(1, 0) -#define EQDMA_GLBL2_DBG_PCIE_RQ1_ADDR 0x1BC -#define GLBL2_PCIE_RQ1_RSVD_1_MASK GENMASK(31, 21) -#define GLBL2_PCIE_RQ1_TAG_FL_MASK GENMASK(20, 19) -#define GLBL2_PCIE_RQ1_WTLP_HEADER_FIFO_FL_MASK BIT(18) -#define GLBL2_PCIE_RQ1_WTLP_HEADER_FIFO_EP_MASK BIT(17) -#define GLBL2_PCIE_RQ1_RQ_FIFO_EP_MASK BIT(16) -#define GLBL2_PCIE_RQ1_RQ_FIFO_FL_MASK BIT(15) -#define GLBL2_PCIE_RQ1_TLPSM_MASK GENMASK(14, 12) -#define GLBL2_PCIE_RQ1_TLPSM512_MASK GENMASK(11, 9) -#define GLBL2_PCIE_RQ1_RREQ_RCB_OK_MASK BIT(8) -#define GLBL2_PCIE_RQ1_RREQ0_SLV_MASK BIT(7) -#define GLBL2_PCIE_RQ1_RREQ0_VLD_MASK BIT(6) -#define GLBL2_PCIE_RQ1_RREQ0_RDY_MASK BIT(5) -#define GLBL2_PCIE_RQ1_RREQ1_SLV_MASK BIT(4) -#define GLBL2_PCIE_RQ1_RREQ1_VLD_MASK BIT(3) -#define GLBL2_PCIE_RQ1_RREQ1_RDY_MASK BIT(2) -#define GLBL2_PCIE_RQ1_WTLP_REQ_MASK BIT(1) -#define GLBL2_PCIE_RQ1_WTLP_STRADDLE_MASK BIT(0) -#define EQDMA_GLBL2_DBG_AXIMM_WR0_ADDR 0x1C0 -#define GLBL2_AXIMM_WR0_RSVD_1_MASK GENMASK(31, 27) -#define GLBL2_AXIMM_WR0_WR_REQ_MASK BIT(26) -#define GLBL2_AXIMM_WR0_WR_CHN_MASK GENMASK(25, 23) -#define GLBL2_AXIMM_WR0_WTLP_DATA_FIFO_EP_MASK BIT(22) -#define GLBL2_AXIMM_WR0_WPL_FIFO_EP_MASK BIT(21) -#define GLBL2_AXIMM_WR0_BRSP_CLAIM_CHN_MASK GENMASK(20, 18) -#define GLBL2_AXIMM_WR0_WRREQ_CNT_MASK GENMASK(17, 12) -#define GLBL2_AXIMM_WR0_BID_MASK GENMASK(11, 9) -#define GLBL2_AXIMM_WR0_BVALID_MASK BIT(8) -#define GLBL2_AXIMM_WR0_BREADY_MASK BIT(7) -#define GLBL2_AXIMM_WR0_WVALID_MASK BIT(6) -#define GLBL2_AXIMM_WR0_WREADY_MASK BIT(5) -#define GLBL2_AXIMM_WR0_AWID_MASK GENMASK(4, 2) -#define GLBL2_AXIMM_WR0_AWVALID_MASK BIT(1) -#define GLBL2_AXIMM_WR0_AWREADY_MASK BIT(0) -#define EQDMA_GLBL2_DBG_AXIMM_WR1_ADDR 0x1C4 -#define GLBL2_AXIMM_WR1_RSVD_1_MASK GENMASK(31, 30) -#define GLBL2_AXIMM_WR1_BRSP_CNT4_MASK GENMASK(29, 24) -#define GLBL2_AXIMM_WR1_BRSP_CNT3_MASK GENMASK(23, 18) -#define GLBL2_AXIMM_WR1_BRSP_CNT2_MASK GENMASK(17, 12) -#define GLBL2_AXIMM_WR1_BRSP_CNT1_MASK GENMASK(11, 6) -#define GLBL2_AXIMM_WR1_BRSP_CNT0_MASK GENMASK(5, 0) -#define EQDMA_GLBL2_DBG_AXIMM_RD0_ADDR 0x1C8 -#define GLBL2_AXIMM_RD0_RSVD_1_MASK GENMASK(31, 23) -#define GLBL2_AXIMM_RD0_PND_CNT_MASK GENMASK(22, 17) -#define GLBL2_AXIMM_RD0_RD_REQ_MASK BIT(16) -#define GLBL2_AXIMM_RD0_RD_CHNL_MASK GENMASK(15, 13) -#define GLBL2_AXIMM_RD0_RRSP_CLAIM_CHNL_MASK GENMASK(12, 10) -#define GLBL2_AXIMM_RD0_RID_MASK GENMASK(9, 7) -#define GLBL2_AXIMM_RD0_RVALID_MASK BIT(6) -#define GLBL2_AXIMM_RD0_RREADY_MASK BIT(5) -#define GLBL2_AXIMM_RD0_ARID_MASK GENMASK(4, 2) -#define GLBL2_AXIMM_RD0_ARVALID_MASK BIT(1) -#define GLBL2_AXIMM_RD0_ARREADY_MASK BIT(0) -#define EQDMA_GLBL2_DBG_AXIMM_RD1_ADDR 0x1CC -#define GLBL2_AXIMM_RD1_RSVD_1_MASK GENMASK(31, 30) -#define GLBL2_AXIMM_RD1_RRSP_CNT4_MASK GENMASK(29, 24) -#define GLBL2_AXIMM_RD1_RRSP_CNT3_MASK GENMASK(23, 18) -#define GLBL2_AXIMM_RD1_RRSP_CNT2_MASK GENMASK(17, 12) -#define GLBL2_AXIMM_RD1_RRSP_CNT1_MASK GENMASK(11, 6) -#define GLBL2_AXIMM_RD1_RRSP_CNT0_MASK GENMASK(5, 0) -#define EQDMA_GLBL2_DBG_FAB0_ADDR 0x1D0 -#define GLBL2_FAB0_H2C_INB_CONV_IN_VLD_MASK BIT(31) -#define GLBL2_FAB0_H2C_INB_CONV_IN_RDY_MASK BIT(30) -#define GLBL2_FAB0_H2C_SEG_IN_VLD_MASK BIT(29) -#define GLBL2_FAB0_H2C_SEG_IN_RDY_MASK BIT(28) -#define GLBL2_FAB0_H2C_SEG_OUT_VLD_MASK GENMASK(27, 24) -#define GLBL2_FAB0_H2C_SEG_OUT_RDY_MASK BIT(23) -#define GLBL2_FAB0_H2C_MST_CRDT_STAT_MASK GENMASK(22, 16) -#define GLBL2_FAB0_C2H_SLV_AFIFO_FULL_MASK BIT(15) -#define GLBL2_FAB0_C2H_SLV_AFIFO_EMPTY_MASK BIT(14) -#define GLBL2_FAB0_C2H_DESEG_SEG_VLD_MASK GENMASK(13, 10) -#define GLBL2_FAB0_C2H_DESEG_SEG_RDY_MASK BIT(9) -#define GLBL2_FAB0_C2H_DESEG_OUT_VLD_MASK BIT(8) -#define GLBL2_FAB0_C2H_DESEG_OUT_RDY_MASK BIT(7) -#define GLBL2_FAB0_C2H_INB_DECONV_OUT_VLD_MASK BIT(6) -#define GLBL2_FAB0_C2H_INB_DECONV_OUT_RDY_MASK BIT(5) -#define GLBL2_FAB0_C2H_DSC_CRDT_AFIFO_FULL_MASK BIT(4) -#define GLBL2_FAB0_C2H_DSC_CRDT_AFIFO_EMPTY_MASK BIT(3) -#define GLBL2_FAB0_IRQ_IN_AFIFO_FULL_MASK BIT(2) -#define GLBL2_FAB0_IRQ_IN_AFIFO_EMPTY_MASK BIT(1) -#define GLBL2_FAB0_IMM_CRD_AFIFO_EMPTY_MASK BIT(0) -#define EQDMA_GLBL2_DBG_FAB1_ADDR 0x1D4 -#define GLBL2_FAB1_BYP_OUT_CRDT_STAT_MASK GENMASK(31, 25) -#define GLBL2_FAB1_TM_DSC_STS_CRDT_STAT_MASK GENMASK(24, 18) -#define GLBL2_FAB1_C2H_CMN_AFIFO_FULL_MASK BIT(17) -#define GLBL2_FAB1_C2H_CMN_AFIFO_EMPTY_MASK BIT(16) -#define GLBL2_FAB1_RSVD_1_MASK GENMASK(15, 13) -#define GLBL2_FAB1_C2H_BYP_IN_AFIFO_FULL_MASK BIT(12) -#define GLBL2_FAB1_RSVD_2_MASK GENMASK(11, 9) -#define GLBL2_FAB1_C2H_BYP_IN_AFIFO_EMPTY_MASK BIT(8) -#define GLBL2_FAB1_RSVD_3_MASK GENMASK(7, 5) -#define GLBL2_FAB1_H2C_BYP_IN_AFIFO_FULL_MASK BIT(4) -#define GLBL2_FAB1_RSVD_4_MASK GENMASK(3, 1) -#define GLBL2_FAB1_H2C_BYP_IN_AFIFO_EMPTY_MASK BIT(0) -#define EQDMA_GLBL2_DBG_MATCH_SEL_ADDR 0x1F4 -#define GLBL2_MATCH_SEL_RSV_MASK GENMASK(31, 18) -#define GLBL2_MATCH_SEL_CSR_SEL_MASK GENMASK(17, 13) -#define GLBL2_MATCH_SEL_CSR_EN_MASK BIT(12) -#define GLBL2_MATCH_SEL_ROTATE1_MASK GENMASK(11, 10) -#define GLBL2_MATCH_SEL_ROTATE0_MASK GENMASK(9, 8) -#define GLBL2_MATCH_SEL_SEL_MASK GENMASK(7, 0) -#define EQDMA_GLBL2_DBG_MATCH_MSK_ADDR 0x1F8 -#define GLBL2_MATCH_MSK_MASK GENMASK(31, 0) -#define EQDMA_GLBL2_DBG_MATCH_PAT_ADDR 0x1FC -#define GLBL2_MATCH_PAT_PATTERN_MASK GENMASK(31, 0) -#define EQDMA_GLBL_RNG_SZ_1_ADDR 0x204 -#define GLBL_RNG_SZ_1_RSVD_1_MASK GENMASK(31, 16) -#define GLBL_RNG_SZ_1_RING_SIZE_MASK GENMASK(15, 0) -#define EQDMA_GLBL_RNG_SZ_2_ADDR 0x208 -#define GLBL_RNG_SZ_2_RSVD_1_MASK GENMASK(31, 16) -#define GLBL_RNG_SZ_2_RING_SIZE_MASK GENMASK(15, 0) -#define EQDMA_GLBL_RNG_SZ_3_ADDR 0x20C -#define GLBL_RNG_SZ_3_RSVD_1_MASK GENMASK(31, 16) -#define GLBL_RNG_SZ_3_RING_SIZE_MASK GENMASK(15, 0) -#define EQDMA_GLBL_RNG_SZ_4_ADDR 0x210 -#define GLBL_RNG_SZ_4_RSVD_1_MASK GENMASK(31, 16) -#define GLBL_RNG_SZ_4_RING_SIZE_MASK GENMASK(15, 0) -#define EQDMA_GLBL_RNG_SZ_5_ADDR 0x214 -#define GLBL_RNG_SZ_5_RSVD_1_MASK GENMASK(31, 16) -#define GLBL_RNG_SZ_5_RING_SIZE_MASK GENMASK(15, 0) -#define EQDMA_GLBL_RNG_SZ_6_ADDR 0x218 -#define GLBL_RNG_SZ_6_RSVD_1_MASK GENMASK(31, 16) -#define GLBL_RNG_SZ_6_RING_SIZE_MASK GENMASK(15, 0) -#define EQDMA_GLBL_RNG_SZ_7_ADDR 0x21C -#define GLBL_RNG_SZ_7_RSVD_1_MASK GENMASK(31, 16) -#define GLBL_RNG_SZ_7_RING_SIZE_MASK GENMASK(15, 0) -#define EQDMA_GLBL_RNG_SZ_8_ADDR 0x220 -#define GLBL_RNG_SZ_8_RSVD_1_MASK GENMASK(31, 16) -#define GLBL_RNG_SZ_8_RING_SIZE_MASK GENMASK(15, 0) -#define EQDMA_GLBL_RNG_SZ_9_ADDR 0x224 -#define GLBL_RNG_SZ_9_RSVD_1_MASK GENMASK(31, 16) -#define GLBL_RNG_SZ_9_RING_SIZE_MASK GENMASK(15, 0) -#define EQDMA_GLBL_RNG_SZ_A_ADDR 0x228 -#define GLBL_RNG_SZ_A_RSVD_1_MASK GENMASK(31, 16) -#define GLBL_RNG_SZ_A_RING_SIZE_MASK GENMASK(15, 0) -#define EQDMA_GLBL_RNG_SZ_B_ADDR 0x22C -#define GLBL_RNG_SZ_B_RSVD_1_MASK GENMASK(31, 16) -#define GLBL_RNG_SZ_B_RING_SIZE_MASK GENMASK(15, 0) -#define EQDMA_GLBL_RNG_SZ_C_ADDR 0x230 -#define GLBL_RNG_SZ_C_RSVD_1_MASK GENMASK(31, 16) -#define GLBL_RNG_SZ_C_RING_SIZE_MASK GENMASK(15, 0) -#define EQDMA_GLBL_RNG_SZ_D_ADDR 0x234 -#define GLBL_RNG_SZ_D_RSVD_1_MASK GENMASK(31, 16) -#define GLBL_RNG_SZ_D_RING_SIZE_MASK GENMASK(15, 0) -#define EQDMA_GLBL_RNG_SZ_E_ADDR 0x238 -#define GLBL_RNG_SZ_E_RSVD_1_MASK GENMASK(31, 16) -#define GLBL_RNG_SZ_E_RING_SIZE_MASK GENMASK(15, 0) -#define EQDMA_GLBL_RNG_SZ_F_ADDR 0x23C -#define GLBL_RNG_SZ_F_RSVD_1_MASK GENMASK(31, 16) -#define GLBL_RNG_SZ_F_RING_SIZE_MASK GENMASK(15, 0) -#define EQDMA_GLBL_RNG_SZ_10_ADDR 0x240 -#define GLBL_RNG_SZ_10_RSVD_1_MASK GENMASK(31, 16) -#define GLBL_RNG_SZ_10_RING_SIZE_MASK GENMASK(15, 0) -#define EQDMA_GLBL_ERR_STAT_ADDR 0x248 -#define GLBL_ERR_STAT_RSVD_1_MASK GENMASK(31, 18) -#define GLBL_ERR_STAT_ERR_FAB_MASK BIT(17) -#define GLBL_ERR_STAT_ERR_H2C_ST_MASK BIT(16) -#define GLBL_ERR_STAT_ERR_BDG_MASK BIT(15) -#define GLBL_ERR_STAT_IND_CTXT_CMD_ERR_MASK GENMASK(14, 9) -#define GLBL_ERR_STAT_ERR_C2H_ST_MASK BIT(8) -#define GLBL_ERR_STAT_ERR_C2H_MM_1_MASK BIT(7) -#define GLBL_ERR_STAT_ERR_C2H_MM_0_MASK BIT(6) -#define GLBL_ERR_STAT_ERR_H2C_MM_1_MASK BIT(5) -#define GLBL_ERR_STAT_ERR_H2C_MM_0_MASK BIT(4) -#define GLBL_ERR_STAT_ERR_TRQ_MASK BIT(3) -#define GLBL_ERR_STAT_ERR_DSC_MASK BIT(2) -#define GLBL_ERR_STAT_ERR_RAM_DBE_MASK BIT(1) -#define GLBL_ERR_STAT_ERR_RAM_SBE_MASK BIT(0) -#define EQDMA_GLBL_ERR_MASK_ADDR 0x24C -#define GLBL_ERR_MASK GENMASK(31, 0) -#define EQDMA_GLBL_DSC_CFG_ADDR 0x250 -#define GLBL_DSC_CFG_RSVD_1_MASK GENMASK(31, 30) -#define GLBL_DSC_CFG_C2H_UODSC_LIMIT_MASK GENMASK(29, 20) -#define GLBL_DSC_CFG_H2C_UODSC_LIMIT_MASK GENMASK(19, 10) -#define GLBL_DSC_CFG_UNC_OVR_COR_MASK BIT(9) -#define GLBL_DSC_CFG_CTXT_FER_DIS_MASK BIT(8) -#define GLBL_DSC_CFG_RSVD_2_MASK GENMASK(7, 6) -#define GLBL_DSC_CFG_MAXFETCH_MASK GENMASK(5, 3) -#define GLBL_DSC_CFG_WB_ACC_INT_MASK GENMASK(2, 0) -#define EQDMA_GLBL_DSC_ERR_STS_ADDR 0x254 -#define GLBL_DSC_ERR_STS_RSVD_1_MASK GENMASK(31, 26) -#define GLBL_DSC_ERR_STS_PORT_ID_MASK BIT(25) -#define GLBL_DSC_ERR_STS_SBE_MASK BIT(24) -#define GLBL_DSC_ERR_STS_DBE_MASK BIT(23) -#define GLBL_DSC_ERR_STS_RQ_CANCEL_MASK BIT(22) -#define GLBL_DSC_ERR_STS_DSC_MASK BIT(21) -#define GLBL_DSC_ERR_STS_DMA_MASK BIT(20) -#define GLBL_DSC_ERR_STS_FLR_CANCEL_MASK BIT(19) -#define GLBL_DSC_ERR_STS_RSVD_2_MASK GENMASK(18, 17) -#define GLBL_DSC_ERR_STS_DAT_POISON_MASK BIT(16) -#define GLBL_DSC_ERR_STS_TIMEOUT_MASK BIT(9) -#define GLBL_DSC_ERR_STS_FLR_MASK BIT(8) -#define GLBL_DSC_ERR_STS_TAG_MASK BIT(6) -#define GLBL_DSC_ERR_STS_ADDR_MASK BIT(5) -#define GLBL_DSC_ERR_STS_PARAM_MASK BIT(4) -#define GLBL_DSC_ERR_STS_BCNT_MASK BIT(3) -#define GLBL_DSC_ERR_STS_UR_CA_MASK BIT(2) -#define GLBL_DSC_ERR_STS_POISON_MASK BIT(1) -#define EQDMA_GLBL_DSC_ERR_MSK_ADDR 0x258 -#define GLBL_DSC_ERR_MSK_MASK GENMASK(31, 0) -#define EQDMA_GLBL_DSC_ERR_LOG0_ADDR 0x25C -#define GLBL_DSC_ERR_LOG0_VALID_MASK BIT(31) -#define GLBL_DSC_ERR_LOG0_SEL_MASK BIT(30) -#define GLBL_DSC_ERR_LOG0_RSVD_1_MASK GENMASK(29, 13) -#define GLBL_DSC_ERR_LOG0_QID_MASK GENMASK(12, 0) -#define EQDMA_GLBL_DSC_ERR_LOG1_ADDR 0x260 -#define GLBL_DSC_ERR_LOG1_RSVD_1_MASK GENMASK(31, 28) -#define GLBL_DSC_ERR_LOG1_CIDX_MASK GENMASK(27, 12) -#define GLBL_DSC_ERR_LOG1_RSVD_2_MASK GENMASK(11, 9) -#define GLBL_DSC_ERR_LOG1_SUB_TYPE_MASK GENMASK(8, 5) -#define GLBL_DSC_ERR_LOG1_ERR_TYPE_MASK GENMASK(4, 0) -#define EQDMA_GLBL_TRQ_ERR_STS_ADDR 0x264 -#define GLBL_TRQ_ERR_STS_RSVD_1_MASK GENMASK(31, 8) -#define GLBL_TRQ_ERR_STS_TCP_QSPC_TIMEOUT_MASK BIT(7) -#define GLBL_TRQ_ERR_STS_RSVD_2_MASK BIT(6) -#define GLBL_TRQ_ERR_STS_QID_RANGE_MASK BIT(5) -#define GLBL_TRQ_ERR_STS_QSPC_UNMAPPED_MASK BIT(4) -#define GLBL_TRQ_ERR_STS_TCP_CSR_TIMEOUT_MASK BIT(3) -#define GLBL_TRQ_ERR_STS_RSVD_3_MASK BIT(2) -#define GLBL_TRQ_ERR_STS_VF_ACCESS_ERR_MASK BIT(1) -#define GLBL_TRQ_ERR_STS_CSR_UNMAPPED_MASK BIT(0) -#define EQDMA_GLBL_TRQ_ERR_MSK_ADDR 0x268 -#define GLBL_TRQ_ERR_MSK_MASK GENMASK(31, 0) -#define EQDMA_GLBL_TRQ_ERR_LOG_ADDR 0x26C -#define GLBL_TRQ_ERR_LOG_SRC_MASK BIT(31) -#define GLBL_TRQ_ERR_LOG_TARGET_MASK GENMASK(30, 27) -#define GLBL_TRQ_ERR_LOG_FUNC_MASK GENMASK(26, 17) -#define GLBL_TRQ_ERR_LOG_ADDRESS_MASK GENMASK(16, 0) -#define EQDMA_GLBL_DSC_DBG_DAT0_ADDR 0x270 -#define GLBL_DSC_DAT0_RSVD_1_MASK GENMASK(31, 30) -#define GLBL_DSC_DAT0_CTXT_ARB_DIR_MASK BIT(29) -#define GLBL_DSC_DAT0_CTXT_ARB_QID_MASK GENMASK(28, 17) -#define GLBL_DSC_DAT0_CTXT_ARB_REQ_MASK GENMASK(16, 12) -#define GLBL_DSC_DAT0_IRQ_FIFO_FL_MASK BIT(11) -#define GLBL_DSC_DAT0_TMSTALL_MASK BIT(10) -#define GLBL_DSC_DAT0_RRQ_STALL_MASK GENMASK(9, 8) -#define GLBL_DSC_DAT0_RCP_FIFO_SPC_STALL_MASK GENMASK(7, 6) -#define GLBL_DSC_DAT0_RRQ_FIFO_SPC_STALL_MASK GENMASK(5, 4) -#define GLBL_DSC_DAT0_FAB_MRKR_RSP_STALL_MASK GENMASK(3, 2) -#define GLBL_DSC_DAT0_DSC_OUT_STALL_MASK GENMASK(1, 0) -#define EQDMA_GLBL_DSC_DBG_DAT1_ADDR 0x274 -#define GLBL_DSC_DAT1_RSVD_1_MASK GENMASK(31, 28) -#define GLBL_DSC_DAT1_EVT_SPC_C2H_MASK GENMASK(27, 22) -#define GLBL_DSC_DAT1_EVT_SP_H2C_MASK GENMASK(21, 16) -#define GLBL_DSC_DAT1_DSC_SPC_C2H_MASK GENMASK(15, 8) -#define GLBL_DSC_DAT1_DSC_SPC_H2C_MASK GENMASK(7, 0) -#define EQDMA_GLBL_DSC_DBG_CTL_ADDR 0x278 -#define GLBL_DSC_CTL_RSVD_1_MASK GENMASK(31, 16) -#define GLBL_DSC_CTL_LAT_QID_MASK GENMASK(15, 4) -#define GLBL_DSC_CTL_DSC_ENG_LAT_CLR_MASK BIT(3) -#define GLBL_DSC_CTL_SELECT_MASK GENMASK(2, 0) -#define EQDMA_GLBL_DSC_ERR_LOG2_ADDR 0x27c -#define GLBL_DSC_ERR_LOG2_OLD_PIDX_MASK GENMASK(31, 16) -#define GLBL_DSC_ERR_LOG2_NEW_PIDX_MASK GENMASK(15, 0) -#define EQDMA_GLBL_GLBL_INTERRUPT_CFG_ADDR 0x2c4 -#define GLBL_GLBL_INTERRUPT_CFG_RSVD_1_MASK GENMASK(31, 2) -#define GLBL_GLBL_INTERRUPT_CFG_LGCY_INTR_PENDING_MASK BIT(1) -#define GLBL_GLBL_INTERRUPT_CFG_EN_LGCY_INTR_MASK BIT(0) -#define EQDMA_GLBL_VCH_HOST_PROFILE_ADDR 0x2c8 -#define GLBL_VCH_HOST_PROFILE_RSVD_1_MASK GENMASK(31, 28) -#define GLBL_VCH_HOST_PROFILE_2C_MM_MASK GENMASK(27, 24) -#define GLBL_VCH_HOST_PROFILE_2C_ST_MASK GENMASK(23, 20) -#define GLBL_VCH_HOST_PROFILE_VCH_DSC_MASK GENMASK(19, 16) -#define GLBL_VCH_HOST_PROFILE_VCH_INT_MSG_MASK GENMASK(15, 12) -#define GLBL_VCH_HOST_PROFILE_VCH_INT_AGGR_MASK GENMASK(11, 8) -#define GLBL_VCH_HOST_PROFILE_VCH_CMPT_MASK GENMASK(7, 4) -#define GLBL_VCH_HOST_PROFILE_VCH_C2H_PLD_MASK GENMASK(3, 0) -#define EQDMA_GLBL_BRIDGE_HOST_PROFILE_ADDR 0x308 -#define GLBL_BRIDGE_HOST_PROFILE_RSVD_1_MASK GENMASK(31, 4) -#define GLBL_BRIDGE_HOST_PROFILE_BDGID_MASK GENMASK(3, 0) -#define EQDMA_AXIMM_IRQ_DEST_ADDR_ADDR 0x30c -#define AXIMM_IRQ_DEST_ADDR_ADDR_MASK GENMASK(31, 0) -#define EQDMA_FAB_ERR_LOG_ADDR 0x314 -#define FAB_ERR_LOG_RSVD_1_MASK GENMASK(31, 7) -#define FAB_ERR_LOG_SRC_MASK GENMASK(6, 0) -#define EQDMA_GLBL_REQ_ERR_STS_ADDR 0x318 -#define GLBL_REQ_ERR_STS_RSVD_1_MASK GENMASK(31, 11) -#define GLBL_REQ_ERR_STS_RC_DISCONTINUE_MASK BIT(10) -#define GLBL_REQ_ERR_STS_RC_PRTY_MASK BIT(9) -#define GLBL_REQ_ERR_STS_RC_FLR_MASK BIT(8) -#define GLBL_REQ_ERR_STS_RC_TIMEOUT_MASK BIT(7) -#define GLBL_REQ_ERR_STS_RC_INV_BCNT_MASK BIT(6) -#define GLBL_REQ_ERR_STS_RC_INV_TAG_MASK BIT(5) -#define GLBL_REQ_ERR_STS_RC_START_ADDR_MISMCH_MASK BIT(4) -#define GLBL_REQ_ERR_STS_RC_RID_TC_ATTR_MISMCH_MASK BIT(3) -#define GLBL_REQ_ERR_STS_RC_NO_DATA_MASK BIT(2) -#define GLBL_REQ_ERR_STS_RC_UR_CA_CRS_MASK BIT(1) -#define GLBL_REQ_ERR_STS_RC_POISONED_MASK BIT(0) -#define EQDMA_GLBL_REQ_ERR_MSK_ADDR 0x31C -#define GLBL_REQ_ERR_MSK_MASK GENMASK(31, 0) -#define EQDMA_GLBL_DSC_DBG_LAT0_A_ADDR 0x320 -#define GLBL_DSC_LAT0_A_LAT_MAX_MASK GENMASK(31, 16) -#define GLBL_DSC_LAT0_A_LAT_MIN_MASK GENMASK(15, 0) -#define EQDMA_GLBL_DSC_DBG_LAT1_A_ADDR 0x324 -#define GLBL_DSC_LAT1_A_RSVD_MASK GENMASK(31, 17) -#define GLBL_DSC_LAT1_A_LAT_OVF_MASK BIT(16) -#define GLBL_DSC_LAT1_A_LAT_AVG_MASK GENMASK(15, 0) -#define EQDMA_GLBL_DSC_CRD_CTR0_A_ADDR 0x328 -#define GLBL_DSC_CRD_CTR0_A_CRD_RCV_CNT_MASK GENMASK(31, 0) -#define EQDMA_GLBL_DSC_CRD_CTR1_A_ADDR 0x32C -#define GLBL_DSC_CRD_CTR1_A_CRD_RCV_CNT_MASK GENMASK(31, 0) -#define EQDMA_GLBL_DSC_CRD_CTR2_A_ADDR 0x330 -#define GLBL_DSC_CRD_CTR2_A_CRD_RCV_NRDY_CNT_MASK GENMASK(31, 0) -#define EQDMA_GLBL_DSC_CRD_CTR3_A_ADDR 0x334 -#define GLBL_DSC_CRD_CTR3_A_CRD_RCV_NRDY_CNT_MASK GENMASK(31, 0) -#define EQDMA_GLBL_DSC_IMM_CRD_CTR0_A_ADDR 0x338 -#define GLBL_DSC_IMM_CRD_CTR0_A_RCV_CNT_MASK GENMASK(31, 0) -#define EQDMA_GLBL_DSC_IMM_CRD_CTR1_A_ADDR 0x33C -#define GLBL_DSC_IMM_CRD_CTR1_A_RCV_CNT_MASK GENMASK(31, 0) -#define EQDMA_GLBL_DSC_IMM_CRD_CTR2_A_ADDR 0x340 -#define GLBL_DSC_IMM_CRD_CTR2_A_RCV_NRDY_CNT_MASK GENMASK(31, 0) -#define EQDMA_GLBL_DSC_IMM_CRD_CTR3_A_ADDR 0x344 -#define GLBL_DSC_IMM_CRD_CTR3_A_RCV_NRDY_CNT_MASK GENMASK(31, 0) -#define EQDMA_GLBL_DSC_H2C_OUT_CTR0_A_ADDR 0x348 -#define GLBL_DSC_H2C_OUT_CTR0_A_H2CVLD_CNT_MASK GENMASK(31, 0) -#define EQDMA_GLBL_DSC_H2C_OUT_CTR1_A_ADDR 0x34C -#define GLBL_DSC_H2C_OUT_CTR1_A_H2CVLD_CNT_MASK GENMASK(31, 0) -#define EQDMA_GLBL_DSC_H2C_OUT_CTR2_A_ADDR 0x350 -#define GLBL_DSC_H2C_OUT_CTR2_A_H2CVLD_NRDY_CNT_MASK GENMASK(31, 0) -#define EQDMA_GLBL_DSC_H2C_OUT_CTR3_A_ADDR 0x354 -#define GLBL_DSC_H2C_OUT_CTR3_A_H2CVLD_NRDY_CNT_MASK GENMASK(31, 0) -#define EQDMA_GLBL_DSC_C2H_OUT_CTR0_A_ADDR 0x358 -#define GLBL_DSC_C2H_OUT_CTR0_A_C2HVLD_CNT_MASK GENMASK(31, 0) -#define EQDMA_GLBL_DSC_C2H_OUT_CTR1_A_ADDR 0x35C -#define GLBL_DSC_C2H_OUT_CTR1_A_C2HVLD_CNT_MASK GENMASK(31, 0) -#define EQDMA_GLBL_DSC_C2H_OUT_CTR2_A_ADDR 0x360 -#define GLBL_DSC_C2H_OUT_CTR2_A_C2HVLD_NRDY_CNT_MASK GENMASK(31, 0) -#define EQDMA_GLBL_DSC_C2H_OUT_CTR3_A_ADDR 0x364 -#define GLBL_DSC_C2H_OUT_CTR3_A_C2HVLD_NRDY_CNT_MASK GENMASK(31, 0) -#define EQDMA_T_ADDR 0x368 -#define T_USER_CTR_MAX_MASK GENMASK(31, 0) -#define EQDMA_GLBL_PERF_CNTR_CTL_A1_ADDR 0x36C -#define GLBL_PERF_CNTR_CTL_A1_RSVD_MASK GENMASK(31, 18) -#define GLBL_PERF_CNTR_CTL_A1_USER_CTR_CLEAR_MASK BIT(17) -#define GLBL_PERF_CNTR_CTL_A1_USER_CTR_READ_MASK BIT(16) -#define GLBL_PERF_CNTR_CTL_A1_USER_CTR_MAX_MASK GENMASK(15, 0) -#define EQDMA_GLBL_FREE_CNT_A0_ADDR 0x370 -#define GLBL_FREE_CNT_A0_S_MASK GENMASK(31, 0) -#define EQDMA_GLBL_FREE_CNT_A1_ADDR 0x374 -#define GLBL_FREE_CNT_A1_RSVD_MASK GENMASK(31, 16) -#define GLBL_FREE_CNT_A1_S_MASK GENMASK(15, 0) -#define EQDMA_GLBL_AXIS_H2C_CNT_A0_ADDR 0x378 -#define GLBL_AXIS_H2C_CNT_A0_MPKT_CNTS_MASK GENMASK(31, 0) -#define EQDMA_GLBL_AXIS_H2C_CNT_A1_ADDR 0x37C -#define GLBL_AXIS_H2C_CNT_A1_MIDLE_CNTS_MASK GENMASK(15, 0) -#define GLBL_AXIS_H2C_CNT_A1_MPKT_CNTS_MASK GENMASK(15, 0) -#define EQDMA_GLBL_AXIS_H2C_CNT_A2_ADDR 0x380 -#define GLBL_AXIS_H2C_CNT_A2_MIDLE_CNTS_MASK GENMASK(31, 0) -#define EQDMA_GLBL_AXIS_H2C_CNT_A3_ADDR 0x384 -#define GLBL_AXIS_H2C_CNT_A3_MACTV_CNTS_MASK GENMASK(31, 0) -#define EQDMA_GLBL_AXIS_H2C_CNT_A4_ADDR 0x388 -#define GLBL_AXIS_H2C_CNT_A4_MBUSY_CNTS_MASK GENMASK(15, 0) -#define GLBL_AXIS_H2C_CNT_A4_MACTV_CNTS_MASK GENMASK(15, 0) -#define EQDMA_GLBL_AXIS_H2C_CNT_A5_ADDR 0x38C -#define GLBL_AXIS_H2C_CNT_A5_MBUSY_CNTS_MASK GENMASK(31, 0) -#define EQDMA_GLBL_AXIS_C2H_CNT_A0_ADDR 0x390 -#define GLBL_AXIS_C2H_CNT_A0_SPKT_CNTS_MASK GENMASK(31, 0) -#define EQDMA_GLBL_AXIS_C2H_CNT_A1_ADDR 0x394 -#define GLBL_AXIS_C2H_CNT_A1_SIDLE_CNTS_MASK GENMASK(15, 0) -#define GLBL_AXIS_C2H_CNT_A1_SPKT_CNTS_MASK GENMASK(15, 0) -#define EQDMA_GLBL_AXIS_C2H_CNT_A2_ADDR 0x398 -#define GLBL_AXIS_C2H_CNT_A2_SIDLE_CNTS_MASK GENMASK(31, 0) -#define EQDMA_GLBL_AXIS_C2H_CNT_A3_ADDR 0x39C -#define GLBL_AXIS_C2H_CNT_A3_SACTV_CNTS_MASK GENMASK(31, 0) -#define EQDMA_GLBL_AXIS_C2H_CNT_A4_ADDR 0x3A0 -#define GLBL_AXIS_C2H_CNT_A4_SBUSY_CNTS_MASK GENMASK(15, 0) -#define GLBL_AXIS_C2H_CNT_A4_SACTV_CNTS_MASK GENMASK(15, 0) -#define EQDMA_GLBL_AXIS_C2H_CNT_A5_ADDR 0x3A4 -#define GLBL_AXIS_C2H_CNT_A5_SBUSY_CNTS_MASK GENMASK(31, 0) -#define EQDMA_GLBL_M_AXI_WR_CNT_A0_ADDR 0x3A8 -#define GLBL_M_AXI_WR_CNT_A0_PKT_CNTS_MASK GENMASK(31, 0) -#define EQDMA_GLBL_M_AXI_WR_CNT_A1_ADDR 0x3AC -#define GLBL_M_AXI_WR_CNT_A1_IDLE_CNTS_MASK GENMASK(15, 0) -#define GLBL_M_AXI_WR_CNT_A1_PKT_CNTS_MASK GENMASK(15, 0) -#define EQDMA_GLBL_M_AXI_WR_CNT_A2_ADDR 0x3B0 -#define GLBL_M_AXI_WR_CNT_A2_IDLE_CNTS_MASK GENMASK(31, 0) -#define EQDMA_GLBL_M_AXI_WR_CNT_A3_ADDR 0x3B4 -#define GLBL_M_AXI_WR_CNT_A3_ACTV_CNTS_MASK GENMASK(31, 0) -#define EQDMA_GLBL_M_AXI_WR_CNT_A4_ADDR 0x3B8 -#define GLBL_M_AXI_WR_CNT_A4_BUSY_CNTS_MASK GENMASK(15, 0) -#define GLBL_M_AXI_WR_CNT_A4_ACTV_CNTS_MASK GENMASK(15, 0) -#define EQDMA_GLBL_M_AXI_WR_CNT_A5_ADDR 0x3BC -#define GLBL_M_AXI_WR_CNT_A5_BUSY_CNTS_MASK GENMASK(31, 0) -#define EQDMA_GLBL_M_AXI_RD_CNT_A0_ADDR 0x3C0 -#define GLBL_M_AXI_RD_CNT_A0_PKT_CNTS_MASK GENMASK(31, 0) -#define EQDMA_GLBL_M_AXI_RD_CNT_A1_ADDR 0x3C4 -#define GLBL_M_AXI_RD_CNT_A1_IDLE_CNTS_MASK GENMASK(15, 0) -#define GLBL_M_AXI_RD_CNT_A1_PKT_CNTS_MASK GENMASK(15, 0) -#define EQDMA_GLBL_M_AXI_RD_CNT_A2_ADDR 0x3C8 -#define GLBL_M_AXI_RD_CNT_A2_IDLE_CNTS_MASK GENMASK(31, 0) -#define EQDMA_GLBL_M_AXI_RD_CNT_A3_ADDR 0x3CC -#define GLBL_M_AXI_RD_CNT_A3_ACTV_CNTS_MASK GENMASK(31, 0) -#define EQDMA_GLBL_M_AXI_RD_CNT_A4_ADDR 0x3D0 -#define GLBL_M_AXI_RD_CNT_A4_BUSY_CNTS_MASK GENMASK(15, 0) -#define GLBL_M_AXI_RD_CNT_A4_ACTV_CNTS_MASK GENMASK(15, 0) -#define EQDMA_GLBL_M_AXI_RD_CNT_A5_ADDR 0x3D4 -#define GLBL_M_AXI_RD_CNT_A5_BUSY_CNTS_MASK GENMASK(31, 0) -#define EQDMA_GLBL_M_AXIB_WR_CNT_A0_ADDR 0x3D8 -#define GLBL_M_AXIB_WR_CNT_A0_PKT_CNTS_MASK GENMASK(31, 0) -#define EQDMA_GLBL_M_AXIB_WR_CNT_A1_ADDR 0x3DC -#define GLBL_M_AXIB_WR_CNT_A1_IDLE_CNTS_MASK GENMASK(15, 0) -#define GLBL_M_AXIB_WR_CNT_A1_PKT_CNTS_MASK GENMASK(15, 0) -#define EQDMA_GLBL_M_AXIB_WR_CNT_A2_ADDR 0x3E0 -#define GLBL_M_AXIB_WR_CNT_A2_IDLE_CNTS_MASK GENMASK(31, 0) -#define EQDMA_GLBL_M_AXIB_WR_CNT_A3_ADDR 0x3E4 -#define GLBL_M_AXIB_WR_CNT_A3_ACTV_CNTS_MASK GENMASK(31, 0) -#define EQDMA_GLBL_M_AXIB_WR_CNT_A4_ADDR 0x3E8 -#define GLBL_M_AXIB_WR_CNT_A4_BUSY_CNTS_MASK GENMASK(15, 0) -#define GLBL_M_AXIB_WR_CNT_A4_ACTV_CNTS_MASK GENMASK(15, 0) -#define EQDMA_GLBL_M_AXIB_WR_CNT_A5_ADDR 0x3EC -#define GLBL_M_AXIB_WR_CNT_A5_BUSY_CNTS_MASK GENMASK(31, 0) -#define EQDMA_GLBL_M_AXIB_RD_CNT_A0_ADDR 0x3F0 -#define GLBL_M_AXIB_RD_CNT_A0_PKT_CNTS_MASK GENMASK(31, 0) -#define EQDMA_GLBL_M_AXIB_RD_CNT_A1_ADDR 0x3F4 -#define GLBL_M_AXIB_RD_CNT_A1_IDLE_CNTS_MASK GENMASK(15, 0) -#define GLBL_M_AXIB_RD_CNT_A1_PKT_CNTS_MASK GENMASK(15, 0) -#define EQDMA_GLBL_M_AXIB_RD_CNT_A2_ADDR 0x3F8 -#define GLBL_M_AXIB_RD_CNT_A2_IDLE_CNTS_MASK GENMASK(31, 0) -#define EQDMA_GLBL_M_AXIB_RD_CNT_A3_ADDR 0x3FC -#define GLBL_M_AXIB_RD_CNT_A3_ACTV_CNTS_MASK GENMASK(31, 0) -#define EQDMA_GLBL_M_AXIB_RD_CNT_A4_ADDR 0x400 -#define GLBL_M_AXIB_RD_CNT_A4_BUSY_CNTS_MASK GENMASK(15, 0) -#define GLBL_M_AXIB_RD_CNT_A4_ACTV_CNTS_MASK GENMASK(15, 0) -#define EQDMA_GLBL_M_AXIB_RD_CNT_A5_ADDR 0x404 -#define GLBL_M_AXIB_RD_CNT_A5_BUSY_CNTS_MASK GENMASK(31, 0) -#define EQDMA_GLBL_S_AXI_WR_CNT_A0_ADDR 0x408 -#define GLBL_S_AXI_WR_CNT_A0_PKT_CNTS_MASK GENMASK(31, 0) -#define EQDMA_GLBL_S_AXI_WR_CNT_A1_ADDR 0x40C -#define GLBL_S_AXI_WR_CNT_A1_IDLE_CNTS_MASK GENMASK(15, 0) -#define GLBL_S_AXI_WR_CNT_A1_PKT_CNTS_MASK GENMASK(15, 0) -#define EQDMA_GLBL_S_AXI_WR_CNT_A2_ADDR 0x410 -#define GLBL_S_AXI_WR_CNT_A2_IDLE_CNTS_MASK GENMASK(31, 0) -#define EQDMA_GLBL_S_AXI_WR_CNT_A3_ADDR 0x414 -#define GLBL_S_AXI_WR_CNT_A3_ACTV_CNTS_MASK GENMASK(31, 0) -#define EQDMA_GLBL_S_AXI_WR_CNT_A4_ADDR 0x418 -#define GLBL_S_AXI_WR_CNT_A4_BUSY_CNTS_MASK GENMASK(15, 0) -#define GLBL_S_AXI_WR_CNT_A4_ACTV_CNTS_MASK GENMASK(15, 0) -#define EQDMA_GLBL_S_AXI_WR_CNT_A5_ADDR 0x41C -#define GLBL_S_AXI_WR_CNT_A5_BUSY_CNTS_MASK GENMASK(31, 0) -#define EQDMA_GLBL_S_AXI_RD_CNT_A0_ADDR 0x420 -#define GLBL_S_AXI_RD_CNT_A0_PKT_CNTS_MASK GENMASK(31, 0) -#define EQDMA_GLBL_S_AXI_RD_CNT_A1_ADDR 0x424 -#define GLBL_S_AXI_RD_CNT_A1_IDLE_CNTS_MASK GENMASK(15, 0) -#define GLBL_S_AXI_RD_CNT_A1_PKT_CNTS_MASK GENMASK(15, 0) -#define EQDMA_GLBL_S_AXI_RD_CNT_A2_ADDR 0x428 -#define GLBL_S_AXI_RD_CNT_A2_IDLE_CNTS_MASK GENMASK(31, 0) -#define EQDMA_GLBL_S_AXI_RD_CNT_A3_ADDR 0x42C -#define GLBL_S_AXI_RD_CNT_A3_ACTV_CNTS_MASK GENMASK(31, 0) -#define EQDMA_GLBL_S_AXI_RD_CNT_A4_ADDR 0x430 -#define GLBL_S_AXI_RD_CNT_A4_BUSY_CNTS_MASK GENMASK(15, 0) -#define GLBL_S_AXI_RD_CNT_A4_ACTV_CNTS_MASK GENMASK(15, 0) -#define EQDMA_GLBL_S_AXI_RD_CNT_A5_ADDR 0x434 -#define GLBL_S_AXI_RD_CNT_A5_BUSY_CNTS_MASK GENMASK(31, 0) -#define EQDMA_GLBL_S_AXIS_CMP_CNT_A0_ADDR 0x438 -#define GLBL_S_AXIS_CMP_CNT_A0_PKT_CNTS_MASK GENMASK(31, 0) -#define EQDMA_GLBL_S_AXIS_CMP_CNT_A1_ADDR 0x43C -#define GLBL_S_AXIS_CMP_CNT_A1_IDLE_CNTS_MASK GENMASK(15, 0) -#define GLBL_S_AXIS_CMP_CNT_A1_PKT_CNTS_MASK GENMASK(15, 0) -#define EQDMA_GLBL_S_AXIS_CMP_CNT_A2_ADDR 0x440 -#define GLBL_S_AXIS_CMP_CNT_A2_IDLE_CNTS_MASK GENMASK(31, 0) -#define EQDMA_GLBL_S_AXIS_CMP_CNT_A3_ADDR 0x444 -#define GLBL_S_AXIS_CMP_CNT_A3_ACTV_CNTS_MASK GENMASK(31, 0) -#define EQDMA_GLBL_S_AXIS_CMP_CNT_A4_ADDR 0x448 -#define GLBL_S_AXIS_CMP_CNT_A4_BUSY_CNTS_MASK GENMASK(15, 0) -#define GLBL_S_AXIS_CMP_CNT_A4_ACTV_CNTS_MASK GENMASK(15, 0) -#define EQDMA_GLBL_S_AXIS_CMP_CNT_A5_ADDR 0x44C -#define GLBL_S_AXIS_CMP_CNT_A5_BUSY_CNTS_MASK GENMASK(31, 0) -#define EQDMA_IND_CTXT_DATA_ADDR 0x804 -#define IND_CTXT_DATA_DATA_MASK GENMASK(31, 0) -#define EQDMA_IND_CTXT_MASK_ADDR 0x824 -#define IND_CTXT_MASK GENMASK(31, 0) -#define EQDMA_IND_CTXT_CMD_ADDR 0x844 -#define IND_CTXT_CMD_RSVD_1_MASK GENMASK(31, 20) -#define IND_CTXT_CMD_QID_MASK GENMASK(19, 7) -#define IND_CTXT_CMD_OP_MASK GENMASK(6, 5) -#define IND_CTXT_CMD_SEL_MASK GENMASK(4, 1) -#define IND_CTXT_CMD_BUSY_MASK BIT(0) -#define EQDMA_C2H_TIMER_CNT_ADDR 0xA00 -#define C2H_TIMER_CNT_RSVD_1_MASK GENMASK(31, 16) -#define C2H_TIMER_CNT_MASK GENMASK(15, 0) -#define EQDMA_C2H_CNT_TH_ADDR 0xA40 -#define C2H_CNT_TH_RSVD_1_MASK GENMASK(31, 16) -#define C2H_CNT_TH_THESHOLD_CNT_MASK GENMASK(15, 0) -#define EQDMA_C2H_PFCH_CFG_1_ADDR 0xA80 -#define C2H_PFCH_CFG_1_EVT_QCNT_TH_MASK GENMASK(31, 16) -#define C2H_PFCH_CFG_1_QCNT_MASK GENMASK(15, 0) -#define EQDMA_C2H_PFCH_CFG_2_ADDR 0xA84 -#define C2H_PFCH_CFG_2_FENCE_MASK BIT(31) -#define C2H_PFCH_CFG_2_RSVD_MASK GENMASK(30, 29) -#define C2H_PFCH_CFG_2_VAR_DESC_NO_DROP_MASK BIT(28) -#define C2H_PFCH_CFG_2_LL_SZ_TH_MASK GENMASK(27, 12) -#define C2H_PFCH_CFG_2_VAR_DESC_NUM_MASK GENMASK(11, 6) -#define C2H_PFCH_CFG_2_NUM_MASK GENMASK(5, 0) -#define EQDMA_C2H_STAT_S_AXIS_C2H_ACCEPTED_ADDR 0xA88 -#define C2H_STAT_S_AXIS_C2H_ACCEPTED_MASK GENMASK(31, 0) -#define EQDMA_C2H_STAT_S_AXIS_WRB_ACCEPTED_ADDR 0xA8C -#define C2H_STAT_S_AXIS_WRB_ACCEPTED_MASK GENMASK(31, 0) -#define EQDMA_C2H_STAT_DESC_RSP_PKT_ACCEPTED_ADDR 0xA90 -#define C2H_STAT_DESC_RSP_PKT_ACCEPTED_D_MASK GENMASK(31, 0) -#define EQDMA_C2H_STAT_AXIS_PKG_CMP_ADDR 0xA94 -#define C2H_STAT_AXIS_PKG_CMP_MASK GENMASK(31, 0) -#define EQDMA_C2H_STAT_DESC_RSP_ACCEPTED_ADDR 0xA98 -#define C2H_STAT_DESC_RSP_ACCEPTED_D_MASK GENMASK(31, 0) -#define EQDMA_C2H_STAT_DESC_RSP_CMP_ADDR 0xA9C -#define C2H_STAT_DESC_RSP_CMP_D_MASK GENMASK(31, 0) -#define EQDMA_C2H_STAT_WRQ_OUT_ADDR 0xAA0 -#define C2H_STAT_WRQ_OUT_MASK GENMASK(31, 0) -#define EQDMA_C2H_STAT_WPL_REN_ACCEPTED_ADDR 0xAA4 -#define C2H_STAT_WPL_REN_ACCEPTED_MASK GENMASK(31, 0) -#define EQDMA_C2H_STAT_TOTAL_WRQ_LEN_ADDR 0xAA8 -#define C2H_STAT_TOTAL_WRQ_LEN_MASK GENMASK(31, 0) -#define EQDMA_C2H_STAT_TOTAL_WPL_LEN_ADDR 0xAAC -#define C2H_STAT_TOTAL_WPL_LEN_MASK GENMASK(31, 0) -#define EQDMA_C2H_BUF_SZ_ADDR 0xAB0 -#define C2H_BUF_SZ_IZE_MASK GENMASK(31, 0) -#define EQDMA_C2H_ERR_STAT_ADDR 0xAF0 -#define C2H_ERR_STAT_RSVD_1_MASK GENMASK(31, 21) -#define C2H_ERR_STAT_WRB_PORT_ID_ERR_MASK BIT(20) -#define C2H_ERR_STAT_HDR_PAR_ERR_MASK BIT(19) -#define C2H_ERR_STAT_HDR_ECC_COR_ERR_MASK BIT(18) -#define C2H_ERR_STAT_HDR_ECC_UNC_ERR_MASK BIT(17) -#define C2H_ERR_STAT_AVL_RING_DSC_ERR_MASK BIT(16) -#define C2H_ERR_STAT_WRB_PRTY_ERR_MASK BIT(15) -#define C2H_ERR_STAT_WRB_CIDX_ERR_MASK BIT(14) -#define C2H_ERR_STAT_WRB_QFULL_ERR_MASK BIT(13) -#define C2H_ERR_STAT_WRB_INV_Q_ERR_MASK BIT(12) -#define C2H_ERR_STAT_RSVD_2_MASK BIT(11) -#define C2H_ERR_STAT_PORT_ID_CTXT_MISMATCH_MASK BIT(10) -#define C2H_ERR_STAT_ERR_DESC_CNT_MASK BIT(9) -#define C2H_ERR_STAT_RSVD_3_MASK BIT(8) -#define C2H_ERR_STAT_MSI_INT_FAIL_MASK BIT(7) -#define C2H_ERR_STAT_ENG_WPL_DATA_PAR_ERR_MASK BIT(6) -#define C2H_ERR_STAT_RSVD_4_MASK BIT(5) -#define C2H_ERR_STAT_DESC_RSP_ERR_MASK BIT(4) -#define C2H_ERR_STAT_QID_MISMATCH_MASK BIT(3) -#define C2H_ERR_STAT_SH_CMPT_DSC_ERR_MASK BIT(2) -#define C2H_ERR_STAT_LEN_MISMATCH_MASK BIT(1) -#define C2H_ERR_STAT_MTY_MISMATCH_MASK BIT(0) -#define EQDMA_C2H_ERR_MASK_ADDR 0xAF4 -#define C2H_ERR_EN_MASK GENMASK(31, 0) -#define EQDMA_C2H_FATAL_ERR_STAT_ADDR 0xAF8 -#define C2H_FATAL_ERR_STAT_RSVD_1_MASK GENMASK(31, 21) -#define C2H_FATAL_ERR_STAT_HDR_ECC_UNC_ERR_MASK BIT(20) -#define C2H_FATAL_ERR_STAT_AVL_RING_FIFO_RAM_RDBE_MASK BIT(19) -#define C2H_FATAL_ERR_STAT_WPL_DATA_PAR_ERR_MASK BIT(18) -#define C2H_FATAL_ERR_STAT_PLD_FIFO_RAM_RDBE_MASK BIT(17) -#define C2H_FATAL_ERR_STAT_QID_FIFO_RAM_RDBE_MASK BIT(16) -#define C2H_FATAL_ERR_STAT_CMPT_FIFO_RAM_RDBE_MASK BIT(15) -#define C2H_FATAL_ERR_STAT_WRB_COAL_DATA_RAM_RDBE_MASK BIT(14) -#define C2H_FATAL_ERR_STAT_RESERVED2_MASK BIT(13) -#define C2H_FATAL_ERR_STAT_INT_CTXT_RAM_RDBE_MASK BIT(12) -#define C2H_FATAL_ERR_STAT_DESC_REQ_FIFO_RAM_RDBE_MASK BIT(11) -#define C2H_FATAL_ERR_STAT_PFCH_CTXT_RAM_RDBE_MASK BIT(10) -#define C2H_FATAL_ERR_STAT_WRB_CTXT_RAM_RDBE_MASK BIT(9) -#define C2H_FATAL_ERR_STAT_PFCH_LL_RAM_RDBE_MASK BIT(8) -#define C2H_FATAL_ERR_STAT_TIMER_FIFO_RAM_RDBE_MASK GENMASK(7, 4) -#define C2H_FATAL_ERR_STAT_QID_MISMATCH_MASK BIT(3) -#define C2H_FATAL_ERR_STAT_RESERVED1_MASK BIT(2) -#define C2H_FATAL_ERR_STAT_LEN_MISMATCH_MASK BIT(1) -#define C2H_FATAL_ERR_STAT_MTY_MISMATCH_MASK BIT(0) -#define EQDMA_C2H_FATAL_ERR_MASK_ADDR 0xAFC -#define C2H_FATAL_ERR_C2HEN_MASK GENMASK(31, 0) -#define EQDMA_C2H_FATAL_ERR_ENABLE_ADDR 0xB00 -#define C2H_FATAL_ERR_ENABLE_RSVD_1_MASK GENMASK(31, 2) -#define C2H_FATAL_ERR_ENABLE_WPL_PAR_INV_MASK BIT(1) -#define C2H_FATAL_ERR_ENABLE_WRQ_DIS_MASK BIT(0) -#define EQDMA_GLBL_ERR_INT_ADDR 0xB04 -#define GLBL_ERR_INT_RSVD_1_MASK GENMASK(31, 30) -#define GLBL_ERR_INT_HOST_ID_MASK GENMASK(29, 26) -#define GLBL_ERR_INT_DIS_INTR_ON_VF_MASK BIT(25) -#define GLBL_ERR_INT_ARM_MASK BIT(24) -#define GLBL_ERR_INT_EN_COAL_MASK BIT(23) -#define GLBL_ERR_INT_VEC_MASK GENMASK(22, 12) -#define GLBL_ERR_INT_FUNC_MASK GENMASK(11, 0) -#define EQDMA_C2H_PFCH_CFG_ADDR 0xB08 -#define C2H_PFCH_CFG_EVTFL_TH_MASK GENMASK(31, 16) -#define C2H_PFCH_CFG_FL_TH_MASK GENMASK(15, 0) -#define EQDMA_C2H_INT_TIMER_TICK_ADDR 0xB0C -#define C2H_INT_TIMER_TICK_MASK GENMASK(31, 0) -#define EQDMA_C2H_STAT_DESC_RSP_DROP_ACCEPTED_ADDR 0xB10 -#define C2H_STAT_DESC_RSP_DROP_ACCEPTED_D_MASK GENMASK(31, 0) -#define EQDMA_C2H_STAT_DESC_RSP_ERR_ACCEPTED_ADDR 0xB14 -#define C2H_STAT_DESC_RSP_ERR_ACCEPTED_D_MASK GENMASK(31, 0) -#define EQDMA_C2H_STAT_DESC_REQ_ADDR 0xB18 -#define C2H_STAT_DESC_REQ_MASK GENMASK(31, 0) -#define EQDMA_C2H_STAT_DBG_DMA_ENG_0_ADDR 0xB1C -#define C2H_STAT_DMA_ENG_0_S_AXIS_C2H_TVALID_MASK BIT(31) -#define C2H_STAT_DMA_ENG_0_S_AXIS_C2H_TREADY_MASK BIT(30) -#define C2H_STAT_DMA_ENG_0_S_AXIS_WRB_TVALID_MASK GENMASK(29, 27) -#define C2H_STAT_DMA_ENG_0_S_AXIS_WRB_TREADY_MASK GENMASK(26, 24) -#define C2H_STAT_DMA_ENG_0_PLD_FIFO_IN_RDY_MASK BIT(23) -#define C2H_STAT_DMA_ENG_0_QID_FIFO_IN_RDY_MASK BIT(22) -#define C2H_STAT_DMA_ENG_0_ARB_FIFO_OUT_VLD_MASK BIT(21) -#define C2H_STAT_DMA_ENG_0_ARB_FIFO_OUT_QID_MASK GENMASK(20, 9) -#define C2H_STAT_DMA_ENG_0_WRB_FIFO_IN_RDY_MASK BIT(8) -#define C2H_STAT_DMA_ENG_0_WRB_FIFO_OUT_CNT_MASK GENMASK(7, 5) -#define C2H_STAT_DMA_ENG_0_WRB_SM_CS_MASK BIT(4) -#define C2H_STAT_DMA_ENG_0_MAIN_SM_CS_MASK GENMASK(3, 0) -#define EQDMA_C2H_STAT_DBG_DMA_ENG_1_ADDR 0xB20 -#define C2H_STAT_DMA_ENG_1_WRB_USER_0_CMPT_TYPE_MASK GENMASK(31, 30) -#define C2H_STAT_DMA_ENG_1_DESC_RSP_FIFO_OUT_VLD_MASK GENMASK(29, 29) -#define C2H_STAT_DMA_ENG_1_QID_FIFO_OUT_CNT_MASK GENMASK(28, 18) -#define C2H_STAT_DMA_ENG_1_PLD_FIFO_OUT_CNT_MASK GENMASK(17, 7) -#define C2H_STAT_DMA_ENG_1_PLD_ST_FIFO_CNT_MASK GENMASK(6, 0) -#define EQDMA_C2H_STAT_DBG_DMA_ENG_2_ADDR 0xB24 -#define C2H_STAT_DMA_ENG_2_WRB_USER_1_CMPT_TYPE_MASK GENMASK(31, 30) -#define C2H_STAT_DMA_ENG_2_DESC_RSP_FIFO_OUT_VLD_1_MASK GENMASK(29, 29) -#define C2H_STAT_DMA_ENG_2_QID_FIFO_OUT_CNT_1_MASK GENMASK(28, 18) -#define C2H_STAT_DMA_ENG_2_PLD_FIFO_OUT_CNT_1_MASK GENMASK(17, 7) -#define C2H_STAT_DMA_ENG_2_PLD_ST_FIFO_CNT_1_MASK GENMASK(6, 0) -#define EQDMA_C2H_STAT_DBG_DMA_ENG_3_ADDR 0xB28 -#define C2H_STAT_DMA_ENG_3_QID_FIFO_OUT_DAT_HAS_CMPT_MASK BIT(31) -#define C2H_STAT_DMA_ENG_3_QID_FIFO_OUT_DAT_MARKER_MASK BIT(30) -#define C2H_STAT_DMA_ENG_3_QID_FIFO_OUT_DAT_DROP_REQ_MASK BIT(29) -#define C2H_STAT_DMA_ENG_3_QID_FIFO_OUT_DAT_QID_MASK GENMASK(28, 17) -#define C2H_STAT_DMA_ENG_3_WR_HDR_FIFO_OUT_CNT_MASK GENMASK(16, 12) -#define C2H_STAT_DMA_ENG_3_QID_FIFO_OUT_VLD_MASK BIT(11) -#define C2H_STAT_DMA_ENG_3_PLD_FIFO_OUT_VLD_MASK BIT(10) -#define C2H_STAT_DMA_ENG_3_PLD_ST_FIFO_OUT_VLD_MASK BIT(9) -#define C2H_STAT_DMA_ENG_3_PLD_ST_FIFO_OUT_DATA_EOP_MASK BIT(8) -#define C2H_STAT_DMA_ENG_3_PLD_ST_FIFO_OUT_DATA_AVL_IDX_ENABLE_MASK BIT(7) -#define C2H_STAT_DMA_ENG_3_PLD_ST_FIFO_OUT_DATA_DROP_MASK BIT(6) -#define C2H_STAT_DMA_ENG_3_PLD_ST_FIFO_OUT_DATA_ERR_MASK BIT(5) -#define C2H_STAT_DMA_ENG_3_DESC_CNT_FIFO_IN_RDY_MASK BIT(4) -#define C2H_STAT_DMA_ENG_3_DESC_RSP_FIFO_IN_RDY_MASK BIT(3) -#define C2H_STAT_DMA_ENG_3_PLD_PKT_ID_LARGER_MASK BIT(2) -#define C2H_STAT_DMA_ENG_3_WCP_FIFO_IN_RDY_MASK BIT(1) -#define C2H_STAT_DMA_ENG_3_PLD_ST_FIFO_IN_RDY_MASK BIT(0) -#define EQDMA_C2H_DBG_PFCH_ERR_CTXT_ADDR 0xB2C -#define C2H_PFCH_ERR_CTXT_RSVD_1_MASK GENMASK(31, 14) -#define C2H_PFCH_ERR_CTXT_ERR_STAT_MASK BIT(13) -#define C2H_PFCH_ERR_CTXT_CMD_WR_MASK BIT(12) -#define C2H_PFCH_ERR_CTXT_QID_MASK GENMASK(11, 1) -#define C2H_PFCH_ERR_CTXT_DONE_MASK BIT(0) -#define EQDMA_C2H_FIRST_ERR_QID_ADDR 0xB30 -#define C2H_FIRST_ERR_QID_RSVD_1_MASK GENMASK(31, 21) -#define C2H_FIRST_ERR_QID_ERR_TYPE_MASK GENMASK(20, 16) -#define C2H_FIRST_ERR_QID_RSVD_MASK GENMASK(15, 13) -#define C2H_FIRST_ERR_QID_QID_MASK GENMASK(12, 0) -#define EQDMA_STAT_NUM_WRB_IN_ADDR 0xB34 -#define STAT_NUM_WRB_IN_RSVD_1_MASK GENMASK(31, 16) -#define STAT_NUM_WRB_IN_WRB_CNT_MASK GENMASK(15, 0) -#define EQDMA_STAT_NUM_WRB_OUT_ADDR 0xB38 -#define STAT_NUM_WRB_OUT_RSVD_1_MASK GENMASK(31, 16) -#define STAT_NUM_WRB_OUT_WRB_CNT_MASK GENMASK(15, 0) -#define EQDMA_STAT_NUM_WRB_DRP_ADDR 0xB3C -#define STAT_NUM_WRB_DRP_RSVD_1_MASK GENMASK(31, 16) -#define STAT_NUM_WRB_DRP_WRB_CNT_MASK GENMASK(15, 0) -#define EQDMA_STAT_NUM_STAT_DESC_OUT_ADDR 0xB40 -#define STAT_NUM_STAT_DESC_OUT_RSVD_1_MASK GENMASK(31, 16) -#define STAT_NUM_STAT_DESC_OUT_CNT_MASK GENMASK(15, 0) -#define EQDMA_STAT_NUM_DSC_CRDT_SENT_ADDR 0xB44 -#define STAT_NUM_DSC_CRDT_SENT_RSVD_1_MASK GENMASK(31, 16) -#define STAT_NUM_DSC_CRDT_SENT_CNT_MASK GENMASK(15, 0) -#define EQDMA_STAT_NUM_FCH_DSC_RCVD_ADDR 0xB48 -#define STAT_NUM_FCH_DSC_RCVD_RSVD_1_MASK GENMASK(31, 16) -#define STAT_NUM_FCH_DSC_RCVD_DSC_CNT_MASK GENMASK(15, 0) -#define EQDMA_STAT_NUM_BYP_DSC_RCVD_ADDR 0xB4C -#define STAT_NUM_BYP_DSC_RCVD_RSVD_1_MASK GENMASK(31, 11) -#define STAT_NUM_BYP_DSC_RCVD_DSC_CNT_MASK GENMASK(10, 0) -#define EQDMA_C2H_WRB_COAL_CFG_ADDR 0xB50 -#define C2H_WRB_COAL_CFG_MAX_BUF_SZ_MASK GENMASK(31, 26) -#define C2H_WRB_COAL_CFG_TICK_VAL_MASK GENMASK(25, 14) -#define C2H_WRB_COAL_CFG_TICK_CNT_MASK GENMASK(13, 2) -#define C2H_WRB_COAL_CFG_SET_GLB_FLUSH_MASK BIT(1) -#define C2H_WRB_COAL_CFG_DONE_GLB_FLUSH_MASK BIT(0) -#define EQDMA_C2H_INTR_H2C_REQ_ADDR 0xB54 -#define C2H_INTR_H2C_REQ_RSVD_1_MASK GENMASK(31, 18) -#define C2H_INTR_H2C_REQ_CNT_MASK GENMASK(17, 0) -#define EQDMA_C2H_INTR_C2H_MM_REQ_ADDR 0xB58 -#define C2H_INTR_C2H_MM_REQ_RSVD_1_MASK GENMASK(31, 18) -#define C2H_INTR_C2H_MM_REQ_CNT_MASK GENMASK(17, 0) -#define EQDMA_C2H_INTR_ERR_INT_REQ_ADDR 0xB5C -#define C2H_INTR_ERR_INT_REQ_RSVD_1_MASK GENMASK(31, 18) -#define C2H_INTR_ERR_INT_REQ_CNT_MASK GENMASK(17, 0) -#define EQDMA_C2H_INTR_C2H_ST_REQ_ADDR 0xB60 -#define C2H_INTR_C2H_ST_REQ_RSVD_1_MASK GENMASK(31, 18) -#define C2H_INTR_C2H_ST_REQ_CNT_MASK GENMASK(17, 0) -#define EQDMA_C2H_INTR_H2C_ERR_C2H_MM_MSIX_ACK_ADDR 0xB64 -#define C2H_INTR_H2C_ERR_C2H_MM_MSIX_ACK_RSVD_1_MASK GENMASK(31, 18) -#define C2H_INTR_H2C_ERR_C2H_MM_MSIX_ACK_CNT_MASK GENMASK(17, 0) -#define EQDMA_C2H_INTR_H2C_ERR_C2H_MM_MSIX_FAIL_ADDR 0xB68 -#define C2H_INTR_H2C_ERR_C2H_MM_MSIX_FAIL_RSVD_1_MASK GENMASK(31, 18) -#define C2H_INTR_H2C_ERR_C2H_MM_MSIX_FAIL_CNT_MASK GENMASK(17, 0) -#define EQDMA_C2H_INTR_H2C_ERR_C2H_MM_MSIX_NO_MSIX_ADDR 0xB6C -#define C2H_INTR_H2C_ERR_C2H_MM_MSIX_NO_MSIX_RSVD_1_MASK GENMASK(31, 18) -#define C2H_INTR_H2C_ERR_C2H_MM_MSIX_NO_MSIX_CNT_MASK GENMASK(17, 0) -#define EQDMA_C2H_INTR_H2C_ERR_C2H_MM_CTXT_INVAL_ADDR 0xB70 -#define C2H_INTR_H2C_ERR_C2H_MM_CTXT_INVAL_RSVD_1_MASK GENMASK(31, 18) -#define C2H_INTR_H2C_ERR_C2H_MM_CTXT_INVAL_CNT_MASK GENMASK(17, 0) -#define EQDMA_C2H_INTR_C2H_ST_MSIX_ACK_ADDR 0xB74 -#define C2H_INTR_C2H_ST_MSIX_ACK_RSVD_1_MASK GENMASK(31, 18) -#define C2H_INTR_C2H_ST_MSIX_ACK_CNT_MASK GENMASK(17, 0) -#define EQDMA_C2H_INTR_C2H_ST_MSIX_FAIL_ADDR 0xB78 -#define C2H_INTR_C2H_ST_MSIX_FAIL_RSVD_1_MASK GENMASK(31, 18) -#define C2H_INTR_C2H_ST_MSIX_FAIL_CNT_MASK GENMASK(17, 0) -#define EQDMA_C2H_INTR_C2H_ST_NO_MSIX_ADDR 0xB7C -#define C2H_INTR_C2H_ST_NO_MSIX_RSVD_1_MASK GENMASK(31, 18) -#define C2H_INTR_C2H_ST_NO_MSIX_CNT_MASK GENMASK(17, 0) -#define EQDMA_C2H_INTR_C2H_ST_CTXT_INVAL_ADDR 0xB80 -#define C2H_INTR_C2H_ST_CTXT_INVAL_RSVD_1_MASK GENMASK(31, 18) -#define C2H_INTR_C2H_ST_CTXT_INVAL_CNT_MASK GENMASK(17, 0) -#define EQDMA_C2H_STAT_WR_CMP_ADDR 0xB84 -#define C2H_STAT_WR_CMP_RSVD_1_MASK GENMASK(31, 18) -#define C2H_STAT_WR_CMP_CNT_MASK GENMASK(17, 0) -#define EQDMA_C2H_STAT_DBG_DMA_ENG_4_ADDR 0xB88 -#define C2H_STAT_DMA_ENG_4_QID_FIFO_OUT_DAT_HAS_CMPT_1_MASK BIT(31) -#define C2H_STAT_DMA_ENG_4_QID_FIFO_OUT_DAT_MARKER_1_MASK BIT(30) -#define C2H_STAT_DMA_ENG_4_QID_FIFO_OUT_DAT_DROP_REQ_1_MASK BIT(29) -#define C2H_STAT_DMA_ENG_4_QID_FIFO_OUT_DAT_QID_1_MASK GENMASK(28, 17) -#define C2H_STAT_DMA_ENG_4_WR_HDR_FIFO_OUT_CNT_1_MASK GENMASK(16, 12) -#define C2H_STAT_DMA_ENG_4_QID_FIFO_OUT_VLD_1_MASK BIT(11) -#define C2H_STAT_DMA_ENG_4_PLD_FIFO_OUT_VLD_1_MASK BIT(10) -#define C2H_STAT_DMA_ENG_4_PLD_ST_FIFO_OUT_VLD_1_MASK BIT(9) -#define C2H_STAT_DMA_ENG_4_PLD_ST_FIFO_OUT_DATA_EOP_1_MASK BIT(8) -#define C2H_STAT_DMA_ENG_4_PLD_ST_FIFO_OUT_DATA_AVL_IDX_ENABLE_1_MASK BIT(7) -#define C2H_STAT_DMA_ENG_4_PLD_ST_FIFO_OUT_DATA_DROP_1_MASK BIT(6) -#define C2H_STAT_DMA_ENG_4_PLD_ST_FIFO_OUT_DATA_ERR_1_MASK BIT(5) -#define C2H_STAT_DMA_ENG_4_DESC_CNT_FIFO_IN_RDY_1_MASK BIT(4) -#define C2H_STAT_DMA_ENG_4_DESC_RSP_FIFO_IN_RDY_1_MASK BIT(3) -#define C2H_STAT_DMA_ENG_4_PLD_PKT_ID_LARGER_1_MASK BIT(2) -#define C2H_STAT_DMA_ENG_4_WCP_FIFO_IN_RDY_1_MASK BIT(1) -#define C2H_STAT_DMA_ENG_4_PLD_ST_FIFO_IN_RDY_1_MASK BIT(0) -#define EQDMA_C2H_STAT_DBG_DMA_ENG_5_ADDR 0xB8C -#define C2H_STAT_DMA_ENG_5_ARB_FIFO_IN_RDY_MASK BIT(31) -#define C2H_STAT_DMA_ENG_5_WRB_SM_VIRT_CH_MASK BIT(30) -#define C2H_STAT_DMA_ENG_5_WRB_FIFO_IN_REQ_MASK GENMASK(29, 24) -#define C2H_STAT_DMA_ENG_5_ARB_FIFO_OUT_CNT_MASK GENMASK(23, 22) -#define C2H_STAT_DMA_ENG_5_ARB_FIFO_OUT_DATA_LEN_MASK GENMASK(21, 6) -#define C2H_STAT_DMA_ENG_5_ARB_FIFO_OUT_DATA_VIRT_CH_MASK BIT(5) -#define C2H_STAT_DMA_ENG_5_ARB_FIFO_OUT_DATA_VAR_DESC_MASK BIT(4) -#define C2H_STAT_DMA_ENG_5_ARB_FIFO_OUT_DATA_DROP_REQ_MASK BIT(3) -#define C2H_STAT_DMA_ENG_5_ARB_FIFO_OUT_DATA_NUM_BUF_OV_MASK BIT(2) -#define C2H_STAT_DMA_ENG_5_ARB_FIFO_OUT_DATA_MARKER_MASK BIT(1) -#define C2H_STAT_DMA_ENG_5_ARB_FIFO_OUT_DATA_HAS_CMPT_MASK BIT(0) -#define EQDMA_C2H_DBG_PFCH_QID_ADDR 0xB90 -#define C2H_PFCH_QID_RSVD_1_MASK GENMASK(31, 16) -#define C2H_PFCH_QID_ERR_CTXT_MASK BIT(15) -#define C2H_PFCH_QID_TARGET_MASK GENMASK(14, 12) -#define C2H_PFCH_QID_QID_OR_TAG_MASK GENMASK(11, 0) -#define EQDMA_C2H_DBG_PFCH_ADDR 0xB94 -#define C2H_PFCH_DATA_MASK GENMASK(31, 0) -#define EQDMA_C2H_INT_DBG_ADDR 0xB98 -#define C2H_INT_RSVD_1_MASK GENMASK(31, 8) -#define C2H_INT_INT_COAL_SM_MASK GENMASK(7, 4) -#define C2H_INT_INT_SM_MASK GENMASK(3, 0) -#define EQDMA_C2H_STAT_IMM_ACCEPTED_ADDR 0xB9C -#define C2H_STAT_IMM_ACCEPTED_RSVD_1_MASK GENMASK(31, 18) -#define C2H_STAT_IMM_ACCEPTED_CNT_MASK GENMASK(17, 0) -#define EQDMA_C2H_STAT_MARKER_ACCEPTED_ADDR 0xBA0 -#define C2H_STAT_MARKER_ACCEPTED_RSVD_1_MASK GENMASK(31, 18) -#define C2H_STAT_MARKER_ACCEPTED_CNT_MASK GENMASK(17, 0) -#define EQDMA_C2H_STAT_DISABLE_CMP_ACCEPTED_ADDR 0xBA4 -#define C2H_STAT_DISABLE_CMP_ACCEPTED_RSVD_1_MASK GENMASK(31, 18) -#define C2H_STAT_DISABLE_CMP_ACCEPTED_CNT_MASK GENMASK(17, 0) -#define EQDMA_C2H_PLD_FIFO_CRDT_CNT_ADDR 0xBA8 -#define C2H_PLD_FIFO_CRDT_CNT_RSVD_1_MASK GENMASK(31, 18) -#define C2H_PLD_FIFO_CRDT_CNT_CNT_MASK GENMASK(17, 0) -#define EQDMA_C2H_INTR_DYN_REQ_ADDR 0xBAC -#define C2H_INTR_DYN_REQ_RSVD_1_MASK GENMASK(31, 18) -#define C2H_INTR_DYN_REQ_CNT_MASK GENMASK(17, 0) -#define EQDMA_C2H_INTR_DYN_MISC_ADDR 0xBB0 -#define C2H_INTR_DYN_MISC_RSVD_1_MASK GENMASK(31, 18) -#define C2H_INTR_DYN_MISC_CNT_MASK GENMASK(17, 0) -#define EQDMA_C2H_DROP_LEN_MISMATCH_ADDR 0xBB4 -#define C2H_DROP_LEN_MISMATCH_RSVD_1_MASK GENMASK(31, 18) -#define C2H_DROP_LEN_MISMATCH_CNT_MASK GENMASK(17, 0) -#define EQDMA_C2H_DROP_DESC_RSP_LEN_ADDR 0xBB8 -#define C2H_DROP_DESC_RSP_LEN_RSVD_1_MASK GENMASK(31, 18) -#define C2H_DROP_DESC_RSP_LEN_CNT_MASK GENMASK(17, 0) -#define EQDMA_C2H_DROP_QID_FIFO_LEN_ADDR 0xBBC -#define C2H_DROP_QID_FIFO_LEN_RSVD_1_MASK GENMASK(31, 18) -#define C2H_DROP_QID_FIFO_LEN_CNT_MASK GENMASK(17, 0) -#define EQDMA_C2H_DROP_PLD_CNT_ADDR 0xBC0 -#define C2H_DROP_PLD_CNT_RSVD_1_MASK GENMASK(31, 18) -#define C2H_DROP_PLD_CNT_CNT_MASK GENMASK(17, 0) -#define EQDMA_C2H_CMPT_FORMAT_0_ADDR 0xBC4 -#define C2H_CMPT_FORMAT_0_DESC_ERR_LOC_MASK GENMASK(31, 16) -#define C2H_CMPT_FORMAT_0_COLOR_LOC_MASK GENMASK(15, 0) -#define EQDMA_C2H_CMPT_FORMAT_1_ADDR 0xBC8 -#define C2H_CMPT_FORMAT_1_DESC_ERR_LOC_MASK GENMASK(31, 16) -#define C2H_CMPT_FORMAT_1_COLOR_LOC_MASK GENMASK(15, 0) -#define EQDMA_C2H_CMPT_FORMAT_2_ADDR 0xBCC -#define C2H_CMPT_FORMAT_2_DESC_ERR_LOC_MASK GENMASK(31, 16) -#define C2H_CMPT_FORMAT_2_COLOR_LOC_MASK GENMASK(15, 0) -#define EQDMA_C2H_CMPT_FORMAT_3_ADDR 0xBD0 -#define C2H_CMPT_FORMAT_3_DESC_ERR_LOC_MASK GENMASK(31, 16) -#define C2H_CMPT_FORMAT_3_COLOR_LOC_MASK GENMASK(15, 0) -#define EQDMA_C2H_CMPT_FORMAT_4_ADDR 0xBD4 -#define C2H_CMPT_FORMAT_4_DESC_ERR_LOC_MASK GENMASK(31, 16) -#define C2H_CMPT_FORMAT_4_COLOR_LOC_MASK GENMASK(15, 0) -#define EQDMA_C2H_CMPT_FORMAT_5_ADDR 0xBD8 -#define C2H_CMPT_FORMAT_5_DESC_ERR_LOC_MASK GENMASK(31, 16) -#define C2H_CMPT_FORMAT_5_COLOR_LOC_MASK GENMASK(15, 0) -#define EQDMA_C2H_CMPT_FORMAT_6_ADDR 0xBDC -#define C2H_CMPT_FORMAT_6_DESC_ERR_LOC_MASK GENMASK(31, 16) -#define C2H_CMPT_FORMAT_6_COLOR_LOC_MASK GENMASK(15, 0) -#define EQDMA_C2H_PFCH_CACHE_DEPTH_ADDR 0xBE0 -#define C2H_PFCH_CACHE_DEPTH_MAX_STBUF_MASK GENMASK(23, 16) -#define C2H_PFCH_CACHE_DEPTH_MASK GENMASK(7, 0) -#define EQDMA_C2H_WRB_COAL_BUF_DEPTH_ADDR 0xBE4 -#define C2H_WRB_COAL_BUF_DEPTH_RSVD_1_MASK GENMASK(31, 8) -#define C2H_WRB_COAL_BUF_DEPTH_BUFFER_MASK GENMASK(7, 0) -#define EQDMA_C2H_PFCH_CRDT_ADDR 0xBE8 -#define C2H_PFCH_CRDT_RSVD_1_MASK GENMASK(31, 1) -#define C2H_PFCH_CRDT_RSVD_2_MASK BIT(0) -#define EQDMA_C2H_STAT_HAS_CMPT_ACCEPTED_ADDR 0xBEC -#define C2H_STAT_HAS_CMPT_ACCEPTED_RSVD_1_MASK GENMASK(31, 18) -#define C2H_STAT_HAS_CMPT_ACCEPTED_CNT_MASK GENMASK(17, 0) -#define EQDMA_C2H_STAT_HAS_PLD_ACCEPTED_ADDR 0xBF0 -#define C2H_STAT_HAS_PLD_ACCEPTED_RSVD_1_MASK GENMASK(31, 18) -#define C2H_STAT_HAS_PLD_ACCEPTED_CNT_MASK GENMASK(17, 0) -#define EQDMA_C2H_PLD_PKT_ID_ADDR 0xBF4 -#define C2H_PLD_PKT_ID_CMPT_WAIT_MASK GENMASK(31, 16) -#define C2H_PLD_PKT_ID_DATA_MASK GENMASK(15, 0) -#define EQDMA_C2H_PLD_PKT_ID_1_ADDR 0xBF8 -#define C2H_PLD_PKT_ID_1_CMPT_WAIT_MASK GENMASK(31, 16) -#define C2H_PLD_PKT_ID_1_DATA_MASK GENMASK(15, 0) -#define EQDMA_C2H_DROP_PLD_CNT_1_ADDR 0xBFC -#define C2H_DROP_PLD_CNT_1_RSVD_1_MASK GENMASK(31, 18) -#define C2H_DROP_PLD_CNT_1_CNT_MASK GENMASK(17, 0) -#define EQDMA_H2C_ERR_STAT_ADDR 0xE00 -#define H2C_ERR_STAT_RSVD_1_MASK GENMASK(31, 6) -#define H2C_ERR_STAT_PAR_ERR_MASK BIT(5) -#define H2C_ERR_STAT_SBE_MASK BIT(4) -#define H2C_ERR_STAT_DBE_MASK BIT(3) -#define H2C_ERR_STAT_NO_DMA_DS_MASK BIT(2) -#define H2C_ERR_STAT_SDI_MRKR_REQ_MOP_ERR_MASK BIT(1) -#define H2C_ERR_STAT_ZERO_LEN_DS_MASK BIT(0) -#define EQDMA_H2C_ERR_MASK_ADDR 0xE04 -#define H2C_ERR_EN_MASK GENMASK(31, 0) -#define EQDMA_H2C_FIRST_ERR_QID_ADDR 0xE08 -#define H2C_FIRST_ERR_QID_RSVD_1_MASK GENMASK(31, 20) -#define H2C_FIRST_ERR_QID_ERR_TYPE_MASK GENMASK(19, 16) -#define H2C_FIRST_ERR_QID_RSVD_2_MASK GENMASK(15, 13) -#define H2C_FIRST_ERR_QID_QID_MASK GENMASK(12, 0) -#define EQDMA_H2C_DBG_REG0_ADDR 0xE0C -#define H2C_REG0_NUM_DSC_RCVD_MASK GENMASK(31, 16) -#define H2C_REG0_NUM_WRB_SENT_MASK GENMASK(15, 0) -#define EQDMA_H2C_DBG_REG1_ADDR 0xE10 -#define H2C_REG1_NUM_REQ_SENT_MASK GENMASK(31, 16) -#define H2C_REG1_NUM_CMP_SENT_MASK GENMASK(15, 0) -#define EQDMA_H2C_DBG_REG2_ADDR 0xE14 -#define H2C_REG2_RSVD_1_MASK GENMASK(31, 16) -#define H2C_REG2_NUM_ERR_DSC_RCVD_MASK GENMASK(15, 0) -#define EQDMA_H2C_DBG_REG3_ADDR 0xE18 -#define H2C_REG3_RSVD_1_MASK BIT(31) -#define H2C_REG3_DSCO_FIFO_EMPTY_MASK BIT(30) -#define H2C_REG3_DSCO_FIFO_FULL_MASK BIT(29) -#define H2C_REG3_CUR_RC_STATE_MASK GENMASK(28, 26) -#define H2C_REG3_RDREQ_LINES_MASK GENMASK(25, 16) -#define H2C_REG3_RDATA_LINES_AVAIL_MASK GENMASK(15, 6) -#define H2C_REG3_PEND_FIFO_EMPTY_MASK BIT(5) -#define H2C_REG3_PEND_FIFO_FULL_MASK BIT(4) -#define H2C_REG3_CUR_RQ_STATE_MASK GENMASK(3, 2) -#define H2C_REG3_DSCI_FIFO_FULL_MASK BIT(1) -#define H2C_REG3_DSCI_FIFO_EMPTY_MASK BIT(0) -#define EQDMA_H2C_DBG_REG4_ADDR 0xE1C -#define H2C_REG4_RDREQ_ADDR_MASK GENMASK(31, 0) -#define EQDMA_H2C_FATAL_ERR_EN_ADDR 0xE20 -#define H2C_FATAL_ERR_EN_RSVD_1_MASK GENMASK(31, 1) -#define H2C_FATAL_ERR_EN_H2C_MASK BIT(0) -#define EQDMA_H2C_REQ_THROT_PCIE_ADDR 0xE24 -#define H2C_REQ_THROT_PCIE_EN_REQ_MASK BIT(31) -#define H2C_REQ_THROT_PCIE_MASK GENMASK(30, 19) -#define H2C_REQ_THROT_PCIE_EN_DATA_MASK BIT(18) -#define H2C_REQ_THROT_PCIE_DATA_THRESH_MASK GENMASK(17, 0) -#define EQDMA_H2C_ALN_DBG_REG0_ADDR 0xE28 -#define H2C_ALN_REG0_NUM_PKT_SENT_MASK GENMASK(15, 0) -#define EQDMA_H2C_REQ_THROT_AXIMM_ADDR 0xE2C -#define H2C_REQ_THROT_AXIMM_EN_REQ_MASK BIT(31) -#define H2C_REQ_THROT_AXIMM_MASK GENMASK(30, 19) -#define H2C_REQ_THROT_AXIMM_EN_DATA_MASK BIT(18) -#define H2C_REQ_THROT_AXIMM_DATA_THRESH_MASK GENMASK(17, 0) -#define EQDMA_C2H_MM_CTL_ADDR 0x1004 -#define C2H_MM_CTL_RESERVED1_MASK GENMASK(31, 9) -#define C2H_MM_CTL_ERRC_EN_MASK BIT(8) -#define C2H_MM_CTL_RESERVED0_MASK GENMASK(7, 1) -#define C2H_MM_CTL_RUN_MASK BIT(0) -#define EQDMA_C2H_MM_STATUS_ADDR 0x1040 -#define C2H_MM_STATUS_RSVD_1_MASK GENMASK(31, 1) -#define C2H_MM_STATUS_RUN_MASK BIT(0) -#define EQDMA_C2H_MM_CMPL_DESC_CNT_ADDR 0x1048 -#define C2H_MM_CMPL_DESC_CNT_C2H_CO_MASK GENMASK(31, 0) -#define EQDMA_C2H_MM_ERR_CODE_ENABLE_MASK_ADDR 0x1054 -#define C2H_MM_ERR_CODE_ENABLE_RESERVED1_MASK BIT(31) -#define C2H_MM_ERR_CODE_ENABLE_WR_UC_RAM_MASK BIT(30) -#define C2H_MM_ERR_CODE_ENABLE_WR_UR_MASK BIT(29) -#define C2H_MM_ERR_CODE_ENABLE_WR_FLR_MASK BIT(28) -#define C2H_MM_ERR_CODE_ENABLE_RESERVED0_MASK GENMASK(27, 2) -#define C2H_MM_ERR_CODE_ENABLE_RD_SLV_ERR_MASK BIT(1) -#define C2H_MM_ERR_CODE_ENABLE_WR_SLV_ERR_MASK BIT(0) -#define EQDMA_C2H_MM_ERR_CODE_ADDR 0x1058 -#define C2H_MM_ERR_CODE_RESERVED1_MASK GENMASK(31, 28) -#define C2H_MM_ERR_CODE_CIDX_MASK GENMASK(27, 12) -#define C2H_MM_ERR_CODE_RESERVED0_MASK GENMASK(11, 10) -#define C2H_MM_ERR_CODE_SUB_TYPE_MASK GENMASK(9, 5) -#define C2H_MM_ERR_CODE_MASK GENMASK(4, 0) -#define EQDMA_C2H_MM_ERR_INFO_ADDR 0x105C -#define C2H_MM_ERR_INFO_VALID_MASK BIT(31) -#define C2H_MM_ERR_INFO_SEL_MASK BIT(30) -#define C2H_MM_ERR_INFO_RSVD_1_MASK GENMASK(29, 24) -#define C2H_MM_ERR_INFO_QID_MASK GENMASK(23, 0) -#define EQDMA_C2H_MM_PERF_MON_CTL_ADDR 0x10C0 -#define C2H_MM_PERF_MON_CTL_RSVD_1_MASK GENMASK(31, 4) -#define C2H_MM_PERF_MON_CTL_IMM_START_MASK BIT(3) -#define C2H_MM_PERF_MON_CTL_RUN_START_MASK BIT(2) -#define C2H_MM_PERF_MON_CTL_IMM_CLEAR_MASK BIT(1) -#define C2H_MM_PERF_MON_CTL_RUN_CLEAR_MASK BIT(0) -#define EQDMA_C2H_MM_PERF_MON_CYCLE_CNT0_ADDR 0x10C4 -#define C2H_MM_PERF_MON_CYCLE_CNT0_CYC_CNT_MASK GENMASK(31, 0) -#define EQDMA_C2H_MM_PERF_MON_CYCLE_CNT1_ADDR 0x10C8 -#define C2H_MM_PERF_MON_CYCLE_CNT1_RSVD_1_MASK GENMASK(31, 10) -#define C2H_MM_PERF_MON_CYCLE_CNT1_CYC_CNT_MASK GENMASK(9, 0) -#define EQDMA_C2H_MM_PERF_MON_DATA_CNT0_ADDR 0x10CC -#define C2H_MM_PERF_MON_DATA_CNT0_DCNT_MASK GENMASK(31, 0) -#define EQDMA_C2H_MM_PERF_MON_DATA_CNT1_ADDR 0x10D0 -#define C2H_MM_PERF_MON_DATA_CNT1_RSVD_1_MASK GENMASK(31, 10) -#define C2H_MM_PERF_MON_DATA_CNT1_DCNT_MASK GENMASK(9, 0) -#define EQDMA_C2H_MM_DBG_ADDR 0x10E8 -#define C2H_MM_RSVD_1_MASK GENMASK(31, 24) -#define C2H_MM_RRQ_ENTRIES_MASK GENMASK(23, 17) -#define C2H_MM_DAT_FIFO_SPC_MASK GENMASK(16, 7) -#define C2H_MM_RD_STALL_MASK BIT(6) -#define C2H_MM_RRQ_FIFO_FI_MASK BIT(5) -#define C2H_MM_WR_STALL_MASK BIT(4) -#define C2H_MM_WRQ_FIFO_FI_MASK BIT(3) -#define C2H_MM_WBK_STALL_MASK BIT(2) -#define C2H_MM_DSC_FIFO_EP_MASK BIT(1) -#define C2H_MM_DSC_FIFO_FL_MASK BIT(0) -#define EQDMA_H2C_MM_CTL_ADDR 0x1204 -#define H2C_MM_CTL_RESERVED1_MASK GENMASK(31, 9) -#define H2C_MM_CTL_ERRC_EN_MASK BIT(8) -#define H2C_MM_CTL_RESERVED0_MASK GENMASK(7, 1) -#define H2C_MM_CTL_RUN_MASK BIT(0) -#define EQDMA_H2C_MM_STATUS_ADDR 0x1240 -#define H2C_MM_STATUS_RSVD_1_MASK GENMASK(31, 1) -#define H2C_MM_STATUS_RUN_MASK BIT(0) -#define EQDMA_H2C_MM_CMPL_DESC_CNT_ADDR 0x1248 -#define H2C_MM_CMPL_DESC_CNT_H2C_CO_MASK GENMASK(31, 0) -#define EQDMA_H2C_MM_ERR_CODE_ENABLE_MASK_ADDR 0x1254 -#define H2C_MM_ERR_CODE_ENABLE_RESERVED5_MASK GENMASK(31, 30) -#define H2C_MM_ERR_CODE_ENABLE_WR_SLV_ERR_MASK BIT(29) -#define H2C_MM_ERR_CODE_ENABLE_WR_DEC_ERR_MASK BIT(28) -#define H2C_MM_ERR_CODE_ENABLE_RESERVED4_MASK GENMASK(27, 23) -#define H2C_MM_ERR_CODE_ENABLE_RD_RQ_DIS_ERR_MASK BIT(22) -#define H2C_MM_ERR_CODE_ENABLE_RESERVED3_MASK GENMASK(21, 17) -#define H2C_MM_ERR_CODE_ENABLE_RD_DAT_POISON_ERR_MASK BIT(16) -#define H2C_MM_ERR_CODE_ENABLE_RESERVED2_MASK GENMASK(15, 9) -#define H2C_MM_ERR_CODE_ENABLE_RD_FLR_ERR_MASK BIT(8) -#define H2C_MM_ERR_CODE_ENABLE_RESERVED1_MASK GENMASK(7, 6) -#define H2C_MM_ERR_CODE_ENABLE_RD_HDR_ADR_ERR_MASK BIT(5) -#define H2C_MM_ERR_CODE_ENABLE_RD_HDR_PARA_MASK BIT(4) -#define H2C_MM_ERR_CODE_ENABLE_RD_HDR_BYTE_ERR_MASK BIT(3) -#define H2C_MM_ERR_CODE_ENABLE_RD_UR_CA_MASK BIT(2) -#define H2C_MM_ERR_CODE_ENABLE_RD_HRD_POISON_ERR_MASK BIT(1) -#define H2C_MM_ERR_CODE_ENABLE_RESERVED0_MASK BIT(0) -#define EQDMA_H2C_MM_ERR_CODE_ADDR 0x1258 -#define H2C_MM_ERR_CODE_RSVD_1_MASK GENMASK(31, 28) -#define H2C_MM_ERR_CODE_CIDX_MASK GENMASK(27, 12) -#define H2C_MM_ERR_CODE_RESERVED0_MASK GENMASK(11, 10) -#define H2C_MM_ERR_CODE_SUB_TYPE_MASK GENMASK(9, 5) -#define H2C_MM_ERR_CODE_MASK GENMASK(4, 0) -#define EQDMA_H2C_MM_ERR_INFO_ADDR 0x125C -#define H2C_MM_ERR_INFO_VALID_MASK BIT(31) -#define H2C_MM_ERR_INFO_SEL_MASK BIT(30) -#define H2C_MM_ERR_INFO_RSVD_1_MASK GENMASK(29, 24) -#define H2C_MM_ERR_INFO_QID_MASK GENMASK(23, 0) -#define EQDMA_H2C_MM_PERF_MON_CTL_ADDR 0x12C0 -#define H2C_MM_PERF_MON_CTL_RSVD_1_MASK GENMASK(31, 4) -#define H2C_MM_PERF_MON_CTL_IMM_START_MASK BIT(3) -#define H2C_MM_PERF_MON_CTL_RUN_START_MASK BIT(2) -#define H2C_MM_PERF_MON_CTL_IMM_CLEAR_MASK BIT(1) -#define H2C_MM_PERF_MON_CTL_RUN_CLEAR_MASK BIT(0) -#define EQDMA_H2C_MM_PERF_MON_CYCLE_CNT0_ADDR 0x12C4 -#define H2C_MM_PERF_MON_CYCLE_CNT0_CYC_CNT_MASK GENMASK(31, 0) -#define EQDMA_H2C_MM_PERF_MON_CYCLE_CNT1_ADDR 0x12C8 -#define H2C_MM_PERF_MON_CYCLE_CNT1_RSVD_1_MASK GENMASK(31, 10) -#define H2C_MM_PERF_MON_CYCLE_CNT1_CYC_CNT_MASK GENMASK(9, 0) -#define EQDMA_H2C_MM_PERF_MON_DATA_CNT0_ADDR 0x12CC -#define H2C_MM_PERF_MON_DATA_CNT0_DCNT_MASK GENMASK(31, 0) -#define EQDMA_H2C_MM_PERF_MON_DATA_CNT1_ADDR 0x12D0 -#define H2C_MM_PERF_MON_DATA_CNT1_RSVD_1_MASK GENMASK(31, 10) -#define H2C_MM_PERF_MON_DATA_CNT1_DCNT_MASK GENMASK(9, 0) -#define EQDMA_H2C_MM_DBG_ADDR 0x12E8 -#define H2C_MM_RSVD_1_MASK GENMASK(31, 24) -#define H2C_MM_RRQ_ENTRIES_MASK GENMASK(23, 17) -#define H2C_MM_DAT_FIFO_SPC_MASK GENMASK(16, 7) -#define H2C_MM_RD_STALL_MASK BIT(6) -#define H2C_MM_RRQ_FIFO_FI_MASK BIT(5) -#define H2C_MM_WR_STALL_MASK BIT(4) -#define H2C_MM_WRQ_FIFO_FI_MASK BIT(3) -#define H2C_MM_WBK_STALL_MASK BIT(2) -#define H2C_MM_DSC_FIFO_EP_MASK BIT(1) -#define H2C_MM_DSC_FIFO_FL_MASK BIT(0) -#define EQDMA_H2C_MM_DATA_THROTTLE_ADDR 0x12EC -#define H2C_MM_DATA_THROTTLE_RSVD_1_MASK GENMASK(31, 17) -#define H2C_MM_DATA_THROTTLE_DAT_EN_MASK BIT(16) -#define H2C_MM_DATA_THROTTLE_DAT_MASK GENMASK(15, 0) -#define EQDMA_C2H_CRDT_COAL_CFG_1_ADDR 0x1400 -#define C2H_CRDT_COAL_CFG_1_RSVD_1_MASK GENMASK(31, 18) -#define C2H_CRDT_COAL_CFG_1_PLD_FIFO_TH_MASK GENMASK(17, 10) -#define C2H_CRDT_COAL_CFG_1_TIMER_TH_MASK GENMASK(9, 0) -#define EQDMA_C2H_CRDT_COAL_CFG_2_ADDR 0x1404 -#define C2H_CRDT_COAL_CFG_2_RSVD_1_MASK GENMASK(31, 24) -#define C2H_CRDT_COAL_CFG_2_FIFO_TH_MASK GENMASK(23, 16) -#define C2H_CRDT_COAL_CFG_2_RESERVED1_MASK GENMASK(15, 11) -#define C2H_CRDT_COAL_CFG_2_NT_TH_MASK GENMASK(10, 0) -#define EQDMA_C2H_PFCH_BYP_QID_ADDR 0x1408 -#define C2H_PFCH_BYP_QID_RSVD_1_MASK GENMASK(31, 12) -#define C2H_PFCH_BYP_QID_MASK GENMASK(11, 0) -#define EQDMA_C2H_PFCH_BYP_TAG_ADDR 0x140C -#define C2H_PFCH_BYP_TAG_RSVD_1_MASK GENMASK(31, 20) -#define C2H_PFCH_BYP_TAG_BYP_QID_MASK GENMASK(19, 8) -#define C2H_PFCH_BYP_TAG_RSVD_2_MASK BIT(7) -#define C2H_PFCH_BYP_TAG_MASK GENMASK(6, 0) -#define EQDMA_C2H_WATER_MARK_ADDR 0x1410 -#define C2H_WATER_MARK_HIGH_WM_MASK GENMASK(31, 16) -#define C2H_WATER_MARK_LOW_WM_MASK GENMASK(15, 0) -#define EQDMA_C2H_NOTIFY_EMPTY_ADDR 0x1450 -#define C2H_NOTIFY_EMPTY_RSVD_1_MASK GENMASK(31, 16) -#define C2H_NOTIFY_EMPTY_NOE_MASK GENMASK(15, 0) -#define EQDMA_C2H_STAT_S_AXIS_C2H_ACCEPTED_1_ADDR 0x1454 -#define C2H_STAT_S_AXIS_C2H_ACCEPTED_1_MASK GENMASK(31, 0) -#define EQDMA_C2H_STAT_S_AXIS_WRB_ACCEPTED_1_ADDR 0x1458 -#define C2H_STAT_S_AXIS_WRB_ACCEPTED_1_MASK GENMASK(31, 0) -#define EQDMA_C2H_STAT_DESC_RSP_PKT_ACCEPTED_1_ADDR 0x145C -#define C2H_STAT_DESC_RSP_PKT_ACCEPTED_1_D_MASK GENMASK(31, 0) -#define EQDMA_C2H_STAT_AXIS_PKG_CMP_1_ADDR 0x1460 -#define C2H_STAT_AXIS_PKG_CMP_1_MASK GENMASK(31, 0) -#define EQDMA_C2H_STAT_S_AXIS_WRB_ACCEPTED_2_ADDR 0x1464 -#define C2H_STAT_S_AXIS_WRB_ACCEPTED_2_MASK GENMASK(31, 0) -#define EQDMA_C2H_ST_PLD_FIFO_DEPTH_ADDR 0x1468 -#define C2H_ST_PLD_FIFO_DEPTH_MASK GENMASK(31, 0) -#define EQDMA_C2H_STAT_DBG_DMA_ENG_6_ADDR 0x146C -#define C2H_STAT_DMA_ENG_6_RSVD_MASK GENMASK(31, 29) -#define C2H_STAT_DMA_ENG_6_PLD_ST_FIFO_OUT_DATA_QID_MASK GENMASK(28, 17) -#define C2H_STAT_DMA_ENG_6_PLD_STS_FIFO_OUT_DATA_PLD_ST_PKT_ID_MASK \ - GENMASK(16, 1) -#define C2H_STAT_DMA_ENG_6_PLD_PKT_ID_LARGER_PLD_ST_MASK BIT(0) -#define EQDMA_C2H_STAT_DBG_DMA_ENG_7_ADDR 0x1470 -#define C2H_STAT_DMA_ENG_7_RSVD_MASK GENMASK(31, 29) -#define C2H_STAT_DMA_ENG_7_PLD_ST_FIFO_OUT_DATA_QID_1_MASK GENMASK(28, 17) -#define C2H_STAT_DMA_ENG_7_PLD_STS_FIFO_OUT_DATA_PLD_ST_PKT_ID_1_MASK \ - GENMASK(16, 1) -#define C2H_STAT_DMA_ENG_7_PLD_PKT_ID_LARGER_PLD_ST_1_MASK BIT(0) -#define EQDMA_C2H_STAT_PCIE_CMP_1_ADDR 0x1474 -#define C2H_STAT_PCIE_CMP_1_DEPTH_MASK GENMASK(31, 0) -#define EQDMA_C2H_PLD_FIFO_ALMOST_FULL_ADDR 0x1478 -#define C2H_PLD_FIFO_ALMOST_FULL_ENABLE_MASK BIT(31) -#define C2H_PLD_FIFO_ALMOST_FULL_TH_MASK GENMASK(30, 0) -#define EQDMA_PFCH_CFG_3_ADDR 0x147C -#define PFCH_CFG_3_RSVD_MASK GENMASK(31, 16) -#define PFCH_CFG_3_VAR_DESC_FL_FREE_CNT_TH_MASK GENMASK(15, 7) -#define PFCH_CFG_3_VAR_DESC_LG_PKT_CAM_CN_TH_MASK GENMASK(6, 0) -#define EQDMA_CMPT_CFG_0_ADDR 0x1480 -#define CMPT_CFG_0_RSVD_MASK GENMASK(31, 2) -#define CMPT_CFG_0_VIO_SPRS_INT_AFTER_RTY_MASK BIT(1) -#define CMPT_CFG_0_VIO_EVNT_SUP_EN_MASK BIT(0) -#define EQDMA_PFCH_CFG_4_ADDR 0x1484 -#define PFCH_CFG_4_GLB_EVT_TIMER_TICK_MASK GENMASK(31, 17) -#define PFCH_CFG_4_DISABLE_GLB_EVT_TIMER_MASK BIT(16) -#define PFCH_CFG_4_EVT_TIMER_TICK_MASK GENMASK(15, 1) -#define PFCH_CFG_4_DISABLE_EVT_TIMER_MASK BIT(0) -#define SW_IND_CTXT_DATA_W7_VIRTIO_DSC_BASE_H_MASK GENMASK(10, 0) -#define SW_IND_CTXT_DATA_W6_VIRTIO_DSC_BASE_M_MASK GENMASK(31, 0) -#define SW_IND_CTXT_DATA_W5_VIRTIO_DSC_BASE_L_MASK GENMASK(31, 11) -#define SW_IND_CTXT_DATA_W5_PASID_EN_MASK BIT(10) -#define SW_IND_CTXT_DATA_W5_PASID_H_MASK GENMASK(9, 0) -#define SW_IND_CTXT_DATA_W4_PASID_L_MASK GENMASK(31, 20) -#define SW_IND_CTXT_DATA_W4_HOST_ID_MASK GENMASK(19, 16) -#define SW_IND_CTXT_DATA_W4_IRQ_BYP_MASK BIT(15) -#define SW_IND_CTXT_DATA_W4_PACK_BYP_OUT_MASK BIT(14) -#define SW_IND_CTXT_DATA_W4_VIRTIO_EN_MASK BIT(13) -#define SW_IND_CTXT_DATA_W4_DIS_INTR_ON_VF_MASK BIT(12) -#define SW_IND_CTXT_DATA_W4_INT_AGGR_MASK BIT(11) -#define SW_IND_CTXT_DATA_W4_VEC_MASK GENMASK(10, 0) -#define SW_IND_CTXT_DATA_W3_DSC_BASE_H_MASK GENMASK(31, 0) -#define SW_IND_CTXT_DATA_W2_DSC_BASE_L_MASK GENMASK(31, 0) -#define SW_IND_CTXT_DATA_W1_IS_MM_MASK BIT(31) -#define SW_IND_CTXT_DATA_W1_MRKR_DIS_MASK BIT(30) -#define SW_IND_CTXT_DATA_W1_IRQ_REQ_MASK BIT(29) -#define SW_IND_CTXT_DATA_W1_ERR_WB_SENT_MASK BIT(28) -#define SW_IND_CTXT_DATA_W1_ERR_MASK GENMASK(27, 26) -#define SW_IND_CTXT_DATA_W1_IRQ_NO_LAST_MASK BIT(25) -#define SW_IND_CTXT_DATA_W1_PORT_ID_MASK GENMASK(24, 22) -#define SW_IND_CTXT_DATA_W1_IRQ_EN_MASK BIT(21) -#define SW_IND_CTXT_DATA_W1_WBK_EN_MASK BIT(20) -#define SW_IND_CTXT_DATA_W1_MM_CHN_MASK BIT(19) -#define SW_IND_CTXT_DATA_W1_BYPASS_MASK BIT(18) -#define SW_IND_CTXT_DATA_W1_DSC_SZ_MASK GENMASK(17, 16) -#define SW_IND_CTXT_DATA_W1_RNG_SZ_MASK GENMASK(15, 12) -#define SW_IND_CTXT_DATA_W1_RSVD_1_MASK GENMASK(11, 9) -#define SW_IND_CTXT_DATA_W1_FETCH_MAX_MASK GENMASK(8, 5) -#define SW_IND_CTXT_DATA_W1_AT_MASK BIT(4) -#define SW_IND_CTXT_DATA_W1_WBI_INTVL_EN_MASK BIT(3) -#define SW_IND_CTXT_DATA_W1_WBI_CHK_MASK BIT(2) -#define SW_IND_CTXT_DATA_W1_FCRD_EN_MASK BIT(1) -#define SW_IND_CTXT_DATA_W1_QEN_MASK BIT(0) -#define SW_IND_CTXT_DATA_W0_RSV_MASK GENMASK(31, 29) -#define SW_IND_CTXT_DATA_W0_FNC_MASK GENMASK(28, 17) -#define SW_IND_CTXT_DATA_W0_IRQ_ARM_MASK BIT(16) -#define SW_IND_CTXT_DATA_W0_PIDX_MASK GENMASK(15, 0) -#define HW_IND_CTXT_DATA_W1_RSVD_1_MASK BIT(15) -#define HW_IND_CTXT_DATA_W1_FETCH_PND_MASK GENMASK(14, 11) -#define HW_IND_CTXT_DATA_W1_EVT_PND_MASK BIT(10) -#define HW_IND_CTXT_DATA_W1_IDL_STP_B_MASK BIT(9) -#define HW_IND_CTXT_DATA_W1_DSC_PND_MASK BIT(8) -#define HW_IND_CTXT_DATA_W1_RSVD_2_MASK GENMASK(7, 0) -#define HW_IND_CTXT_DATA_W0_CRD_USE_MASK GENMASK(31, 16) -#define HW_IND_CTXT_DATA_W0_CIDX_MASK GENMASK(15, 0) -#define CRED_CTXT_DATA_W0_RSVD_1_MASK GENMASK(31, 16) -#define CRED_CTXT_DATA_W0_CREDT_MASK GENMASK(15, 0) -#define PREFETCH_CTXT_DATA_W1_VALID_MASK BIT(13) -#define PREFETCH_CTXT_DATA_W1_SW_CRDT_H_MASK GENMASK(12, 0) -#define PREFETCH_CTXT_DATA_W0_SW_CRDT_L_MASK GENMASK(31, 29) -#define PREFETCH_CTXT_DATA_W0_PFCH_MASK BIT(28) -#define PREFETCH_CTXT_DATA_W0_PFCH_EN_MASK BIT(27) -#define PREFETCH_CTXT_DATA_W0_ERR_MASK BIT(26) -#define PREFETCH_CTXT_DATA_W0_RSVD_MASK GENMASK(25, 22) -#define PREFETCH_CTXT_DATA_W0_PFCH_NEED_MASK GENMASK(21, 16) -#define PREFETCH_CTXT_DATA_W0_NUM_PFCH_MASK GENMASK(15, 10) -#define PREFETCH_CTXT_DATA_W0_VIRTIO_MASK BIT(9) -#define PREFETCH_CTXT_DATA_W0_VAR_DESC_MASK BIT(8) -#define PREFETCH_CTXT_DATA_W0_PORT_ID_MASK GENMASK(7, 5) -#define PREFETCH_CTXT_DATA_W0_BUF_SZ_IDX_MASK GENMASK(4, 1) -#define PREFETCH_CTXT_DATA_W0_BYPASS_MASK BIT(0) -#define CMPL_CTXT_DATA_W6_RSVD_1_H_MASK GENMASK(7, 0) -#define CMPL_CTXT_DATA_W5_RSVD_1_L_MASK GENMASK(31, 23) -#define CMPL_CTXT_DATA_W5_PORT_ID_MASK GENMASK(22, 20) -#define CMPL_CTXT_DATA_W5_SH_CMPT_MASK BIT(19) -#define CMPL_CTXT_DATA_W5_VIO_EOP_MASK BIT(18) -#define CMPL_CTXT_DATA_W5_BADDR4_LOW_MASK GENMASK(17, 14) -#define CMPL_CTXT_DATA_W5_PASID_EN_MASK BIT(13) -#define CMPL_CTXT_DATA_W5_PASID_H_MASK GENMASK(12, 0) -#define CMPL_CTXT_DATA_W4_PASID_L_MASK GENMASK(31, 23) -#define CMPL_CTXT_DATA_W4_HOST_ID_MASK GENMASK(22, 19) -#define CMPL_CTXT_DATA_W4_DIR_C2H_MASK BIT(18) -#define CMPL_CTXT_DATA_W4_VIO_MASK BIT(17) -#define CMPL_CTXT_DATA_W4_DIS_INTR_ON_VF_MASK BIT(16) -#define CMPL_CTXT_DATA_W4_INT_AGGR_MASK BIT(15) -#define CMPL_CTXT_DATA_W4_VEC_MASK GENMASK(14, 4) -#define CMPL_CTXT_DATA_W4_AT_MASK BIT(3) -#define CMPL_CTXT_DATA_W4_OVF_CHK_DIS_MASK BIT(2) -#define CMPL_CTXT_DATA_W4_FULL_UPD_MASK BIT(1) -#define CMPL_CTXT_DATA_W4_TIMER_RUNNING_MASK BIT(0) -#define CMPL_CTXT_DATA_W3_USER_TRIG_PEND_MASK BIT(31) -#define CMPL_CTXT_DATA_W3_ERR_MASK GENMASK(30, 29) -#define CMPL_CTXT_DATA_W3_VALID_MASK BIT(28) -#define CMPL_CTXT_DATA_W3_CIDX_MASK GENMASK(27, 12) -#define CMPL_CTXT_DATA_W3_PIDX_H_MASK GENMASK(11, 0) -#define CMPL_CTXT_DATA_W2_PIDX_L_MASK GENMASK(31, 28) -#define CMPL_CTXT_DATA_W2_DESC_SIZE_MASK GENMASK(27, 26) -#define CMPL_CTXT_DATA_W2_BADDR4_HIGH_H_MASK GENMASK(25, 0) -#define CMPL_CTXT_DATA_W1_BADDR4_HIGH_L_MASK GENMASK(31, 0) -#define CMPL_CTXT_DATA_W0_QSIZE_IX_MASK GENMASK(31, 28) -#define CMPL_CTXT_DATA_W0_COLOR_MASK BIT(27) -#define CMPL_CTXT_DATA_W0_INT_ST_MASK GENMASK(26, 25) -#define CMPL_CTXT_DATA_W0_TIMER_IX_MASK GENMASK(24, 21) -#define CMPL_CTXT_DATA_W0_CNTER_IX_MASK GENMASK(20, 17) -#define CMPL_CTXT_DATA_W0_FNC_ID_MASK GENMASK(16, 5) -#define CMPL_CTXT_DATA_W0_TRIG_MODE_MASK GENMASK(4, 2) -#define CMPL_CTXT_DATA_W0_EN_INT_MASK BIT(1) -#define CMPL_CTXT_DATA_W0_EN_STAT_DESC_MASK BIT(0) -#define INTR_CTXT_DATA_W3_FUNC_MASK GENMASK(29, 18) -#define INTR_CTXT_DATA_W3_RSVD_MASK GENMASK(17, 14) -#define INTR_CTXT_DATA_W3_PASID_EN_MASK BIT(13) -#define INTR_CTXT_DATA_W3_PASID_H_MASK GENMASK(12, 0) -#define INTR_CTXT_DATA_W2_PASID_L_MASK GENMASK(31, 23) -#define INTR_CTXT_DATA_W2_HOST_ID_MASK GENMASK(22, 19) -#define INTR_CTXT_DATA_W2_AT_MASK BIT(18) -#define INTR_CTXT_DATA_W2_PIDX_MASK GENMASK(17, 6) -#define INTR_CTXT_DATA_W2_PAGE_SIZE_MASK GENMASK(5, 3) -#define INTR_CTXT_DATA_W2_BADDR_4K_H_MASK GENMASK(2, 0) -#define INTR_CTXT_DATA_W1_BADDR_4K_M_MASK GENMASK(31, 0) -#define INTR_CTXT_DATA_W0_BADDR_4K_L_MASK GENMASK(31, 15) -#define INTR_CTXT_DATA_W0_COLOR_MASK BIT(14) -#define INTR_CTXT_DATA_W0_INT_ST_MASK BIT(13) -#define INTR_CTXT_DATA_W0_RSVD1_MASK BIT(12) -#define INTR_CTXT_DATA_W0_VEC_MASK GENMASK(11, 1) -#define INTR_CTXT_DATA_W0_VALID_MASK BIT(0) -#define HOSTID_TABLE_W6_SMID_MASK GENMASK(9, 0) -#define HOSTID_TABLE_W5_H2C_MM_AWPROT_MASK GENMASK(27, 26) -#define HOSTID_TABLE_W5_H2C_MM_AWCACHE_MASK GENMASK(25, 22) -#define HOSTID_TABLE_W5_H2C_MM_AWSTEERING_MASK GENMASK(20, 18) -#define HOSTID_TABLE_W5_DSC_AWPROT_MASK GENMASK(17, 16) -#define HOSTID_TABLE_W5_DSC_AWCACHE_MASK GENMASK(15, 12) -#define HOSTID_TABLE_W5_DSC_AWSTEERING_MASK GENMASK(11, 8) -#define HOSTID_TABLE_W5_INT_MSG_AWPROT_MASK GENMASK(7, 6) -#define HOSTID_TABLE_W5_INT_MSG_AWCACHE_MASK GENMASK(5, 2) -#define HOSTID_TABLE_W5_INT_MSG_AWSTEERING_H_MASK GENMASK(0, 0) -#define HOSTID_TABLE_W4_INT_MSG_AWSTEERING_L_MASK GENMASK(31, 30) -#define HOSTID_TABLE_W4_INT_AGGR_AWPROT_MASK GENMASK(29, 28) -#define HOSTID_TABLE_W4_INT_AGGR_AWCACHE_MASK GENMASK(27, 24) -#define HOSTID_TABLE_W4_INT_AGGR_AWSTEERING_MASK GENMASK(22, 20) -#define HOSTID_TABLE_W4_CMPT_AWPROT_MASK GENMASK(19, 18) -#define HOSTID_TABLE_W4_CMPT_AWCACHE_MASK GENMASK(17, 14) -#define HOSTID_TABLE_W4_CMPT_AWSTEERING_MASK GENMASK(12, 10) -#define HOSTID_TABLE_W4_C2H_PLD_AWPROT_MASK GENMASK(9, 8) -#define HOSTID_TABLE_W4_C2H_PLD_AWCACHE_MASK GENMASK(7, 4) -#define HOSTID_TABLE_W4_C2H_PLD_AWSTEERING_MASK GENMASK(2, 0) -#define HOSTID_TABLE_W3_C2H_MM_ARPROT_MASK GENMASK(7, 6) -#define HOSTID_TABLE_W3_C2H_MM_ARCACHE_MASK GENMASK(5, 2) -#define HOSTID_TABLE_W3_C2H_MM_ARSTEERING_H_MASK GENMASK(0, 0) -#define HOSTID_TABLE_W2_C2H_MM_ARSTEERING_L_MASK GENMASK(31, 30) -#define HOSTID_TABLE_W2_H2C_MM_ARPROT_MASK GENMASK(29, 28) -#define HOSTID_TABLE_W2_H2C_MM_ARCACHE_MASK GENMASK(27, 24) -#define HOSTID_TABLE_W2_H2C_MM_ARSTEERING_MASK GENMASK(22, 20) -#define HOSTID_TABLE_W2_H2C_ST_ARPROT_MASK GENMASK(19, 18) -#define HOSTID_TABLE_W2_H2C_ST_ARCACHE_MASK GENMASK(17, 14) -#define HOSTID_TABLE_W2_H2C_ST_ARSTEERING_MASK GENMASK(12, 10) -#define HOSTID_TABLE_W2_DSC_ARPOT_MASK GENMASK(9, 8) -#define HOSTID_TABLE_W2_DSC_ARCACHE_MASK GENMASK(7, 4) -#define HOSTID_TABLE_W2_DSC_ARSTEERING_MASK GENMASK(2, 0) -#define HOSTID_TABLE_W0_VCH_H2C_MM_MASK GENMASK(27, 24) -#define HOSTID_TABLE_W0_VCH_H2C_ST_MASK GENMASK(23, 20) -#define HOSTID_TABLE_W0_VCH_DSC_MASK GENMASK(19, 16) -#define HOSTID_TABLE_W0_VCH_INT_MSG_MASK GENMASK(15, 12) -#define HOSTID_TABLE_W0_VCH_INT_AGGR_MASK GENMASK(11, 8) -#define HOSTID_TABLE_W0_VCH_CMPT_MASK GENMASK(7, 4) -#define HOSTID_TABLE_W0_VCH_H2C_PLD_MASK GENMASK(3, 0) -#define CTXT_SELC_FNC_STS_W0_MSIX_MASK GENMASK(3, 3) -#define CTXT_SELC_FNC_STS_W0_MSIX_ENABLE_MASK GENMASK(2, 2) -#define CTXT_SELC_FNC_STS_W0_MEM_SPACE_ENABLE_MASK GENMASK(1, 1) -#define CTXT_SELC_FNC_STS_W0_BUS_MASTER_ENABLE_MASK GENMASK(0, 0) - -#ifdef __cplusplus -} -#endif - -#endif - diff --git a/QDMA/linux-kernel/driver/libqdma/qdma_access/eqdma_soft_access/eqdma_soft_reg_dump.c b/QDMA/linux-kernel/driver/libqdma/qdma_access/eqdma_soft_access/eqdma_soft_reg_dump.c deleted file mode 100755 index 8754fb7cb..000000000 --- a/QDMA/linux-kernel/driver/libqdma/qdma_access/eqdma_soft_access/eqdma_soft_reg_dump.c +++ /dev/null @@ -1,5322 +0,0 @@ -/* - * Copyright (c) 2019-2022 Xilinx, Inc. All rights reserved. - * Copyright (c) 2022, Advanced Micro Devices, Inc. All rights reserved. - * - * This source code is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * The full GNU General Public License is included in this distribution in - * the file called "COPYING". - */ - -#include "eqdma_soft_reg.h" -#include "qdma_reg_dump.h" - -#ifdef ENABLE_WPP_TRACING -#include "eqdma_soft_reg_dump.tmh" -#endif - - -static struct regfield_info - cfg_blk_identifier_field_info[] = { - {"CFG_BLK_IDENTIFIER", - CFG_BLK_IDENTIFIER_MASK}, - {"CFG_BLK_IDENTIFIER_1", - CFG_BLK_IDENTIFIER_1_MASK}, - {"CFG_BLK_IDENTIFIER_RSVD_1", - CFG_BLK_IDENTIFIER_RSVD_1_MASK}, - {"CFG_BLK_IDENTIFIER_VERSION", - CFG_BLK_IDENTIFIER_VERSION_MASK}, -}; - - -static struct regfield_info - cfg_blk_pcie_max_pld_size_field_info[] = { - {"CFG_BLK_PCIE_MAX_PLD_SIZE_RSVD_1", - CFG_BLK_PCIE_MAX_PLD_SIZE_RSVD_1_MASK}, - {"CFG_BLK_PCIE_MAX_PLD_SIZE_PROG", - CFG_BLK_PCIE_MAX_PLD_SIZE_PROG_MASK}, - {"CFG_BLK_PCIE_MAX_PLD_SIZE_RSVD_2", - CFG_BLK_PCIE_MAX_PLD_SIZE_RSVD_2_MASK}, - {"CFG_BLK_PCIE_MAX_PLD_SIZE_ISSUED", - CFG_BLK_PCIE_MAX_PLD_SIZE_ISSUED_MASK}, -}; - - -static struct regfield_info - cfg_blk_pcie_max_read_req_size_field_info[] = { - {"CFG_BLK_PCIE_MAX_READ_REQ_SIZE_RSVD_1", - CFG_BLK_PCIE_MAX_READ_REQ_SIZE_RSVD_1_MASK}, - {"CFG_BLK_PCIE_MAX_READ_REQ_SIZE_PROG", - CFG_BLK_PCIE_MAX_READ_REQ_SIZE_PROG_MASK}, - {"CFG_BLK_PCIE_MAX_READ_REQ_SIZE_RSVD_2", - CFG_BLK_PCIE_MAX_READ_REQ_SIZE_RSVD_2_MASK}, - {"CFG_BLK_PCIE_MAX_READ_REQ_SIZE_ISSUED", - CFG_BLK_PCIE_MAX_READ_REQ_SIZE_ISSUED_MASK}, -}; - - -static struct regfield_info - cfg_blk_system_id_field_info[] = { - {"CFG_BLK_SYSTEM_ID_RSVD_1", - CFG_BLK_SYSTEM_ID_RSVD_1_MASK}, - {"CFG_BLK_SYSTEM_ID_INST_TYPE", - CFG_BLK_SYSTEM_ID_INST_TYPE_MASK}, - {"CFG_BLK_SYSTEM_ID", - CFG_BLK_SYSTEM_ID_MASK}, -}; - - -static struct regfield_info - cfg_blk_msix_enable_field_info[] = { - {"CFG_BLK_MSIX_ENABLE", - CFG_BLK_MSIX_ENABLE_MASK}, -}; - - -static struct regfield_info - cfg_pcie_data_width_field_info[] = { - {"CFG_PCIE_DATA_WIDTH_RSVD_1", - CFG_PCIE_DATA_WIDTH_RSVD_1_MASK}, - {"CFG_PCIE_DATA_WIDTH_DATAPATH", - CFG_PCIE_DATA_WIDTH_DATAPATH_MASK}, -}; - - -static struct regfield_info - cfg_pcie_ctl_field_info[] = { - {"CFG_PCIE_CTL_RSVD_1", - CFG_PCIE_CTL_RSVD_1_MASK}, - {"CFG_PCIE_CTL_MGMT_AXIL_CTRL", - CFG_PCIE_CTL_MGMT_AXIL_CTRL_MASK}, - {"CFG_PCIE_CTL_RSVD_2", - CFG_PCIE_CTL_RSVD_2_MASK}, - {"CFG_PCIE_CTL_RRQ_DISABLE", - CFG_PCIE_CTL_RRQ_DISABLE_MASK}, - {"CFG_PCIE_CTL_RELAXED_ORDERING", - CFG_PCIE_CTL_RELAXED_ORDERING_MASK}, -}; - - -static struct regfield_info - cfg_blk_msi_enable_field_info[] = { - {"CFG_BLK_MSI_ENABLE", - CFG_BLK_MSI_ENABLE_MASK}, -}; - - -static struct regfield_info - cfg_axi_user_max_pld_size_field_info[] = { - {"CFG_AXI_USER_MAX_PLD_SIZE_RSVD_1", - CFG_AXI_USER_MAX_PLD_SIZE_RSVD_1_MASK}, - {"CFG_AXI_USER_MAX_PLD_SIZE_ISSUED", - CFG_AXI_USER_MAX_PLD_SIZE_ISSUED_MASK}, - {"CFG_AXI_USER_MAX_PLD_SIZE_RSVD_2", - CFG_AXI_USER_MAX_PLD_SIZE_RSVD_2_MASK}, - {"CFG_AXI_USER_MAX_PLD_SIZE_PROG", - CFG_AXI_USER_MAX_PLD_SIZE_PROG_MASK}, -}; - - -static struct regfield_info - cfg_axi_user_max_read_req_size_field_info[] = { - {"CFG_AXI_USER_MAX_READ_REQ_SIZE_RSVD_1", - CFG_AXI_USER_MAX_READ_REQ_SIZE_RSVD_1_MASK}, - {"CFG_AXI_USER_MAX_READ_REQ_SIZE_USISSUED", - CFG_AXI_USER_MAX_READ_REQ_SIZE_USISSUED_MASK}, - {"CFG_AXI_USER_MAX_READ_REQ_SIZE_RSVD_2", - CFG_AXI_USER_MAX_READ_REQ_SIZE_RSVD_2_MASK}, - {"CFG_AXI_USER_MAX_READ_REQ_SIZE_USPROG", - CFG_AXI_USER_MAX_READ_REQ_SIZE_USPROG_MASK}, -}; - - -static struct regfield_info - cfg_blk_misc_ctl_field_info[] = { - {"CFG_BLK_MISC_CTL_RSVD_1", - CFG_BLK_MISC_CTL_RSVD_1_MASK}, - {"CFG_BLK_MISC_CTL_10B_TAG_EN", - CFG_BLK_MISC_CTL_10B_TAG_EN_MASK}, - {"CFG_BLK_MISC_CTL_RSVD_2", - CFG_BLK_MISC_CTL_RSVD_2_MASK}, - {"CFG_BLK_MISC_CTL_AXI_WBK", - CFG_BLK_MISC_CTL_AXI_WBK_MASK}, - {"CFG_BLK_MISC_CTL_AXI_DSC", - CFG_BLK_MISC_CTL_AXI_DSC_MASK}, - {"CFG_BLK_MISC_CTL_NUM_TAG", - CFG_BLK_MISC_CTL_NUM_TAG_MASK}, - {"CFG_BLK_MISC_CTL_RSVD_3", - CFG_BLK_MISC_CTL_RSVD_3_MASK}, - {"CFG_BLK_MISC_CTL_RQ_METERING_MULTIPLIER", - CFG_BLK_MISC_CTL_RQ_METERING_MULTIPLIER_MASK}, -}; - - -static struct regfield_info - cfg_pl_cred_ctl_field_info[] = { - {"CFG_PL_CRED_CTL_RSVD_1", - CFG_PL_CRED_CTL_RSVD_1_MASK}, - {"CFG_PL_CRED_CTL_SLAVE_CRD_RLS", - CFG_PL_CRED_CTL_SLAVE_CRD_RLS_MASK}, - {"CFG_PL_CRED_CTL_RSVD_2", - CFG_PL_CRED_CTL_RSVD_2_MASK}, - {"CFG_PL_CRED_CTL_MASTER_CRD_RST", - CFG_PL_CRED_CTL_MASTER_CRD_RST_MASK}, -}; - - -static struct regfield_info - cfg_blk_scratch_field_info[] = { - {"CFG_BLK_SCRATCH", - CFG_BLK_SCRATCH_MASK}, -}; - - -static struct regfield_info - cfg_gic_field_info[] = { - {"CFG_GIC_RSVD_1", - CFG_GIC_RSVD_1_MASK}, - {"CFG_GIC_GIC_IRQ", - CFG_GIC_GIC_IRQ_MASK}, -}; - - -static struct regfield_info - ram_sbe_msk_1_a_field_info[] = { - {"RAM_SBE_MSK_1_A", - RAM_SBE_MSK_1_A_MASK}, -}; - - -static struct regfield_info - ram_sbe_sts_1_a_field_info[] = { - {"RAM_SBE_STS_1_A_RSVD", - RAM_SBE_STS_1_A_RSVD_MASK}, - {"RAM_SBE_STS_1_A_PFCH_CTXT_CAM_RAM_1", - RAM_SBE_STS_1_A_PFCH_CTXT_CAM_RAM_1_MASK}, - {"RAM_SBE_STS_1_A_PFCH_CTXT_CAM_RAM_0", - RAM_SBE_STS_1_A_PFCH_CTXT_CAM_RAM_0_MASK}, - {"RAM_SBE_STS_1_A_TAG_EVEN_RAM", - RAM_SBE_STS_1_A_TAG_EVEN_RAM_MASK}, - {"RAM_SBE_STS_1_A_TAG_ODD_RAM", - RAM_SBE_STS_1_A_TAG_ODD_RAM_MASK}, - {"RAM_SBE_STS_1_A_RC_RRQ_EVEN_RAM", - RAM_SBE_STS_1_A_RC_RRQ_EVEN_RAM_MASK}, -}; - - -static struct regfield_info - ram_dbe_msk_1_a_field_info[] = { - {"RAM_DBE_MSK_1_A", - RAM_DBE_MSK_1_A_MASK}, -}; - - -static struct regfield_info - ram_dbe_sts_1_a_field_info[] = { - {"RAM_DBE_STS_1_A_RSVD", - RAM_DBE_STS_1_A_RSVD_MASK}, - {"RAM_DBE_STS_1_A_PFCH_CTXT_CAM_RAM_1", - RAM_DBE_STS_1_A_PFCH_CTXT_CAM_RAM_1_MASK}, - {"RAM_DBE_STS_1_A_PFCH_CTXT_CAM_RAM_0", - RAM_DBE_STS_1_A_PFCH_CTXT_CAM_RAM_0_MASK}, - {"RAM_DBE_STS_1_A_TAG_EVEN_RAM", - RAM_DBE_STS_1_A_TAG_EVEN_RAM_MASK}, - {"RAM_DBE_STS_1_A_TAG_ODD_RAM", - RAM_DBE_STS_1_A_TAG_ODD_RAM_MASK}, - {"RAM_DBE_STS_1_A_RC_RRQ_EVEN_RAM", - RAM_DBE_STS_1_A_RC_RRQ_EVEN_RAM_MASK}, -}; - - -static struct regfield_info - ram_sbe_msk_a_field_info[] = { - {"RAM_SBE_MSK_A", - RAM_SBE_MSK_A_MASK}, -}; - - -static struct regfield_info - ram_sbe_sts_a_field_info[] = { - {"RAM_SBE_STS_A_RC_RRQ_ODD_RAM", - RAM_SBE_STS_A_RC_RRQ_ODD_RAM_MASK}, - {"RAM_SBE_STS_A_PEND_FIFO_RAM", - RAM_SBE_STS_A_PEND_FIFO_RAM_MASK}, - {"RAM_SBE_STS_A_PFCH_LL_RAM", - RAM_SBE_STS_A_PFCH_LL_RAM_MASK}, - {"RAM_SBE_STS_A_WRB_CTXT_RAM", - RAM_SBE_STS_A_WRB_CTXT_RAM_MASK}, - {"RAM_SBE_STS_A_PFCH_CTXT_RAM", - RAM_SBE_STS_A_PFCH_CTXT_RAM_MASK}, - {"RAM_SBE_STS_A_DESC_REQ_FIFO_RAM", - RAM_SBE_STS_A_DESC_REQ_FIFO_RAM_MASK}, - {"RAM_SBE_STS_A_INT_CTXT_RAM", - RAM_SBE_STS_A_INT_CTXT_RAM_MASK}, - {"RAM_SBE_STS_A_WRB_COAL_DATA_RAM", - RAM_SBE_STS_A_WRB_COAL_DATA_RAM_MASK}, - {"RAM_SBE_STS_A_QID_FIFO_RAM", - RAM_SBE_STS_A_QID_FIFO_RAM_MASK}, - {"RAM_SBE_STS_A_TIMER_FIFO_RAM", - RAM_SBE_STS_A_TIMER_FIFO_RAM_MASK}, - {"RAM_SBE_STS_A_MI_TL_SLV_FIFO_RAM", - RAM_SBE_STS_A_MI_TL_SLV_FIFO_RAM_MASK}, - {"RAM_SBE_STS_A_DSC_CPLD", - RAM_SBE_STS_A_DSC_CPLD_MASK}, - {"RAM_SBE_STS_A_DSC_CPLI", - RAM_SBE_STS_A_DSC_CPLI_MASK}, - {"RAM_SBE_STS_A_DSC_SW_CTXT", - RAM_SBE_STS_A_DSC_SW_CTXT_MASK}, - {"RAM_SBE_STS_A_DSC_CRD_RCV", - RAM_SBE_STS_A_DSC_CRD_RCV_MASK}, - {"RAM_SBE_STS_A_DSC_HW_CTXT", - RAM_SBE_STS_A_DSC_HW_CTXT_MASK}, - {"RAM_SBE_STS_A_FUNC_MAP", - RAM_SBE_STS_A_FUNC_MAP_MASK}, - {"RAM_SBE_STS_A_C2H_WR_BRG_DAT", - RAM_SBE_STS_A_C2H_WR_BRG_DAT_MASK}, - {"RAM_SBE_STS_A_C2H_RD_BRG_DAT", - RAM_SBE_STS_A_C2H_RD_BRG_DAT_MASK}, - {"RAM_SBE_STS_A_H2C_WR_BRG_DAT", - RAM_SBE_STS_A_H2C_WR_BRG_DAT_MASK}, - {"RAM_SBE_STS_A_H2C_RD_BRG_DAT", - RAM_SBE_STS_A_H2C_RD_BRG_DAT_MASK}, - {"RAM_SBE_STS_A_MI_C2H3_DAT", - RAM_SBE_STS_A_MI_C2H3_DAT_MASK}, - {"RAM_SBE_STS_A_MI_C2H2_DAT", - RAM_SBE_STS_A_MI_C2H2_DAT_MASK}, - {"RAM_SBE_STS_A_MI_C2H1_DAT", - RAM_SBE_STS_A_MI_C2H1_DAT_MASK}, - {"RAM_SBE_STS_A_MI_C2H0_DAT", - RAM_SBE_STS_A_MI_C2H0_DAT_MASK}, - {"RAM_SBE_STS_A_MI_H2C3_DAT", - RAM_SBE_STS_A_MI_H2C3_DAT_MASK}, - {"RAM_SBE_STS_A_MI_H2C2_DAT", - RAM_SBE_STS_A_MI_H2C2_DAT_MASK}, - {"RAM_SBE_STS_A_MI_H2C1_DAT", - RAM_SBE_STS_A_MI_H2C1_DAT_MASK}, - {"RAM_SBE_STS_A_MI_H2C0_DAT", - RAM_SBE_STS_A_MI_H2C0_DAT_MASK}, -}; - - -static struct regfield_info - ram_dbe_msk_a_field_info[] = { - {"RAM_DBE_MSK_A", - RAM_DBE_MSK_A_MASK}, -}; - - -static struct regfield_info - ram_dbe_sts_a_field_info[] = { - {"RAM_DBE_STS_A_RC_RRQ_ODD_RAM", - RAM_DBE_STS_A_RC_RRQ_ODD_RAM_MASK}, - {"RAM_DBE_STS_A_PEND_FIFO_RAM", - RAM_DBE_STS_A_PEND_FIFO_RAM_MASK}, - {"RAM_DBE_STS_A_PFCH_LL_RAM", - RAM_DBE_STS_A_PFCH_LL_RAM_MASK}, - {"RAM_DBE_STS_A_WRB_CTXT_RAM", - RAM_DBE_STS_A_WRB_CTXT_RAM_MASK}, - {"RAM_DBE_STS_A_PFCH_CTXT_RAM", - RAM_DBE_STS_A_PFCH_CTXT_RAM_MASK}, - {"RAM_DBE_STS_A_DESC_REQ_FIFO_RAM", - RAM_DBE_STS_A_DESC_REQ_FIFO_RAM_MASK}, - {"RAM_DBE_STS_A_INT_CTXT_RAM", - RAM_DBE_STS_A_INT_CTXT_RAM_MASK}, - {"RAM_DBE_STS_A_WRB_COAL_DATA_RAM", - RAM_DBE_STS_A_WRB_COAL_DATA_RAM_MASK}, - {"RAM_DBE_STS_A_QID_FIFO_RAM", - RAM_DBE_STS_A_QID_FIFO_RAM_MASK}, - {"RAM_DBE_STS_A_TIMER_FIFO_RAM", - RAM_DBE_STS_A_TIMER_FIFO_RAM_MASK}, - {"RAM_DBE_STS_A_MI_TL_SLV_FIFO_RAM", - RAM_DBE_STS_A_MI_TL_SLV_FIFO_RAM_MASK}, - {"RAM_DBE_STS_A_DSC_CPLD", - RAM_DBE_STS_A_DSC_CPLD_MASK}, - {"RAM_DBE_STS_A_DSC_CPLI", - RAM_DBE_STS_A_DSC_CPLI_MASK}, - {"RAM_DBE_STS_A_DSC_SW_CTXT", - RAM_DBE_STS_A_DSC_SW_CTXT_MASK}, - {"RAM_DBE_STS_A_DSC_CRD_RCV", - RAM_DBE_STS_A_DSC_CRD_RCV_MASK}, - {"RAM_DBE_STS_A_DSC_HW_CTXT", - RAM_DBE_STS_A_DSC_HW_CTXT_MASK}, - {"RAM_DBE_STS_A_FUNC_MAP", - RAM_DBE_STS_A_FUNC_MAP_MASK}, - {"RAM_DBE_STS_A_C2H_WR_BRG_DAT", - RAM_DBE_STS_A_C2H_WR_BRG_DAT_MASK}, - {"RAM_DBE_STS_A_C2H_RD_BRG_DAT", - RAM_DBE_STS_A_C2H_RD_BRG_DAT_MASK}, - {"RAM_DBE_STS_A_H2C_WR_BRG_DAT", - RAM_DBE_STS_A_H2C_WR_BRG_DAT_MASK}, - {"RAM_DBE_STS_A_H2C_RD_BRG_DAT", - RAM_DBE_STS_A_H2C_RD_BRG_DAT_MASK}, - {"RAM_DBE_STS_A_MI_C2H3_DAT", - RAM_DBE_STS_A_MI_C2H3_DAT_MASK}, - {"RAM_DBE_STS_A_MI_C2H2_DAT", - RAM_DBE_STS_A_MI_C2H2_DAT_MASK}, - {"RAM_DBE_STS_A_MI_C2H1_DAT", - RAM_DBE_STS_A_MI_C2H1_DAT_MASK}, - {"RAM_DBE_STS_A_MI_C2H0_DAT", - RAM_DBE_STS_A_MI_C2H0_DAT_MASK}, - {"RAM_DBE_STS_A_MI_H2C3_DAT", - RAM_DBE_STS_A_MI_H2C3_DAT_MASK}, - {"RAM_DBE_STS_A_MI_H2C2_DAT", - RAM_DBE_STS_A_MI_H2C2_DAT_MASK}, - {"RAM_DBE_STS_A_MI_H2C1_DAT", - RAM_DBE_STS_A_MI_H2C1_DAT_MASK}, - {"RAM_DBE_STS_A_MI_H2C0_DAT", - RAM_DBE_STS_A_MI_H2C0_DAT_MASK}, -}; - - -static struct regfield_info - glbl2_identifier_field_info[] = { - {"GLBL2_IDENTIFIER", - GLBL2_IDENTIFIER_MASK}, - {"GLBL2_IDENTIFIER_VERSION", - GLBL2_IDENTIFIER_VERSION_MASK}, -}; - - -static struct regfield_info - glbl2_channel_inst_field_info[] = { - {"GLBL2_CHANNEL_INST_RSVD_1", - GLBL2_CHANNEL_INST_RSVD_1_MASK}, - {"GLBL2_CHANNEL_INST_C2H_ST", - GLBL2_CHANNEL_INST_C2H_ST_MASK}, - {"GLBL2_CHANNEL_INST_H2C_ST", - GLBL2_CHANNEL_INST_H2C_ST_MASK}, - {"GLBL2_CHANNEL_INST_RSVD_2", - GLBL2_CHANNEL_INST_RSVD_2_MASK}, - {"GLBL2_CHANNEL_INST_C2H_ENG", - GLBL2_CHANNEL_INST_C2H_ENG_MASK}, - {"GLBL2_CHANNEL_INST_RSVD_3", - GLBL2_CHANNEL_INST_RSVD_3_MASK}, - {"GLBL2_CHANNEL_INST_H2C_ENG", - GLBL2_CHANNEL_INST_H2C_ENG_MASK}, -}; - - -static struct regfield_info - glbl2_channel_mdma_field_info[] = { - {"GLBL2_CHANNEL_MDMA_RSVD_1", - GLBL2_CHANNEL_MDMA_RSVD_1_MASK}, - {"GLBL2_CHANNEL_MDMA_C2H_ST", - GLBL2_CHANNEL_MDMA_C2H_ST_MASK}, - {"GLBL2_CHANNEL_MDMA_H2C_ST", - GLBL2_CHANNEL_MDMA_H2C_ST_MASK}, - {"GLBL2_CHANNEL_MDMA_RSVD_2", - GLBL2_CHANNEL_MDMA_RSVD_2_MASK}, - {"GLBL2_CHANNEL_MDMA_C2H_ENG", - GLBL2_CHANNEL_MDMA_C2H_ENG_MASK}, - {"GLBL2_CHANNEL_MDMA_RSVD_3", - GLBL2_CHANNEL_MDMA_RSVD_3_MASK}, - {"GLBL2_CHANNEL_MDMA_H2C_ENG", - GLBL2_CHANNEL_MDMA_H2C_ENG_MASK}, -}; - - -static struct regfield_info - glbl2_channel_strm_field_info[] = { - {"GLBL2_CHANNEL_STRM_RSVD_1", - GLBL2_CHANNEL_STRM_RSVD_1_MASK}, - {"GLBL2_CHANNEL_STRM_C2H_ST", - GLBL2_CHANNEL_STRM_C2H_ST_MASK}, - {"GLBL2_CHANNEL_STRM_H2C_ST", - GLBL2_CHANNEL_STRM_H2C_ST_MASK}, - {"GLBL2_CHANNEL_STRM_RSVD_2", - GLBL2_CHANNEL_STRM_RSVD_2_MASK}, - {"GLBL2_CHANNEL_STRM_C2H_ENG", - GLBL2_CHANNEL_STRM_C2H_ENG_MASK}, - {"GLBL2_CHANNEL_STRM_RSVD_3", - GLBL2_CHANNEL_STRM_RSVD_3_MASK}, - {"GLBL2_CHANNEL_STRM_H2C_ENG", - GLBL2_CHANNEL_STRM_H2C_ENG_MASK}, -}; - - -static struct regfield_info - glbl2_channel_cap_field_info[] = { - {"GLBL2_CHANNEL_CAP_RSVD_1", - GLBL2_CHANNEL_CAP_RSVD_1_MASK}, - {"GLBL2_CHANNEL_CAP_MULTIQ_MAX", - GLBL2_CHANNEL_CAP_MULTIQ_MAX_MASK}, -}; - - -static struct regfield_info - glbl2_channel_pasid_cap_field_info[] = { - {"GLBL2_CHANNEL_PASID_CAP_RSVD_1", - GLBL2_CHANNEL_PASID_CAP_RSVD_1_MASK}, - {"GLBL2_CHANNEL_PASID_CAP_BRIDGEEN", - GLBL2_CHANNEL_PASID_CAP_BRIDGEEN_MASK}, - {"GLBL2_CHANNEL_PASID_CAP_DMAEN", - GLBL2_CHANNEL_PASID_CAP_DMAEN_MASK}, -}; - - -static struct regfield_info - glbl2_system_id_field_info[] = { - {"GLBL2_SYSTEM_ID_RSVD_1", - GLBL2_SYSTEM_ID_RSVD_1_MASK}, - {"GLBL2_SYSTEM_ID", - GLBL2_SYSTEM_ID_MASK}, -}; - - -static struct regfield_info - glbl2_misc_cap_field_info[] = { - {"GLBL2_MISC_CAP", - GLBL2_MISC_CAP_MASK}, -}; - - -static struct regfield_info - glbl2_rrq_brg_throt_field_info[] = { - {"GLBL2_RRQ_BRG_THROT_REQ_EN", - GLBL2_RRQ_BRG_THROT_REQ_EN_MASK}, - {"GLBL2_RRQ_BRG_THROT_REQ", - GLBL2_RRQ_BRG_THROT_REQ_MASK}, - {"GLBL2_RRQ_BRG_THROT_DAT_EN", - GLBL2_RRQ_BRG_THROT_DAT_EN_MASK}, - {"GLBL2_RRQ_BRG_THROT_DAT", - GLBL2_RRQ_BRG_THROT_DAT_MASK}, -}; - - -static struct regfield_info - glbl2_rrq_pcie_throt_field_info[] = { - {"GLBL2_RRQ_PCIE_THROT_REQ_EN", - GLBL2_RRQ_PCIE_THROT_REQ_EN_MASK}, - {"GLBL2_RRQ_PCIE_THROT_REQ", - GLBL2_RRQ_PCIE_THROT_REQ_MASK}, - {"GLBL2_RRQ_PCIE_THROT_DAT_EN", - GLBL2_RRQ_PCIE_THROT_DAT_EN_MASK}, - {"GLBL2_RRQ_PCIE_THROT_DAT", - GLBL2_RRQ_PCIE_THROT_DAT_MASK}, -}; - - -static struct regfield_info - glbl2_rrq_aximm_throt_field_info[] = { - {"GLBL2_RRQ_AXIMM_THROT_REQ_EN", - GLBL2_RRQ_AXIMM_THROT_REQ_EN_MASK}, - {"GLBL2_RRQ_AXIMM_THROT_REQ", - GLBL2_RRQ_AXIMM_THROT_REQ_MASK}, - {"GLBL2_RRQ_AXIMM_THROT_DAT_EN", - GLBL2_RRQ_AXIMM_THROT_DAT_EN_MASK}, - {"GLBL2_RRQ_AXIMM_THROT_DAT", - GLBL2_RRQ_AXIMM_THROT_DAT_MASK}, -}; - - -static struct regfield_info - glbl2_rrq_pcie_lat0_field_info[] = { - {"GLBL2_RRQ_PCIE_LAT0_MAX", - GLBL2_RRQ_PCIE_LAT0_MAX_MASK}, - {"GLBL2_RRQ_PCIE_LAT0_MIN", - GLBL2_RRQ_PCIE_LAT0_MIN_MASK}, -}; - - -static struct regfield_info - glbl2_rrq_pcie_lat1_field_info[] = { - {"GLBL2_RRQ_PCIE_LAT1_RSVD", - GLBL2_RRQ_PCIE_LAT1_RSVD_MASK}, - {"GLBL2_RRQ_PCIE_LAT1_OVFL", - GLBL2_RRQ_PCIE_LAT1_OVFL_MASK}, - {"GLBL2_RRQ_PCIE_LAT1_AVG", - GLBL2_RRQ_PCIE_LAT1_AVG_MASK}, -}; - - -static struct regfield_info - glbl2_rrq_aximm_lat0_field_info[] = { - {"GLBL2_RRQ_AXIMM_LAT0_MAX", - GLBL2_RRQ_AXIMM_LAT0_MAX_MASK}, - {"GLBL2_RRQ_AXIMM_LAT0_MIN", - GLBL2_RRQ_AXIMM_LAT0_MIN_MASK}, -}; - - -static struct regfield_info - glbl2_rrq_aximm_lat1_field_info[] = { - {"GLBL2_RRQ_AXIMM_LAT1_RSVD", - GLBL2_RRQ_AXIMM_LAT1_RSVD_MASK}, - {"GLBL2_RRQ_AXIMM_LAT1_OVFL", - GLBL2_RRQ_AXIMM_LAT1_OVFL_MASK}, - {"GLBL2_RRQ_AXIMM_LAT1_AVG", - GLBL2_RRQ_AXIMM_LAT1_AVG_MASK}, -}; - - -static struct regfield_info - glbl2_dbg_pcie_rq0_field_info[] = { - {"GLBL2_PCIE_RQ0_NPH_AVL", - GLBL2_PCIE_RQ0_NPH_AVL_MASK}, - {"GLBL2_PCIE_RQ0_RCB_AVL", - GLBL2_PCIE_RQ0_RCB_AVL_MASK}, - {"GLBL2_PCIE_RQ0_SLV_RD_CREDS", - GLBL2_PCIE_RQ0_SLV_RD_CREDS_MASK}, - {"GLBL2_PCIE_RQ0_TAG_EP", - GLBL2_PCIE_RQ0_TAG_EP_MASK}, -}; - - -static struct regfield_info - glbl2_dbg_pcie_rq1_field_info[] = { - {"GLBL2_PCIE_RQ1_RSVD_1", - GLBL2_PCIE_RQ1_RSVD_1_MASK}, - {"GLBL2_PCIE_RQ1_TAG_FL", - GLBL2_PCIE_RQ1_TAG_FL_MASK}, - {"GLBL2_PCIE_RQ1_WTLP_HEADER_FIFO_FL", - GLBL2_PCIE_RQ1_WTLP_HEADER_FIFO_FL_MASK}, - {"GLBL2_PCIE_RQ1_WTLP_HEADER_FIFO_EP", - GLBL2_PCIE_RQ1_WTLP_HEADER_FIFO_EP_MASK}, - {"GLBL2_PCIE_RQ1_RQ_FIFO_EP", - GLBL2_PCIE_RQ1_RQ_FIFO_EP_MASK}, - {"GLBL2_PCIE_RQ1_RQ_FIFO_FL", - GLBL2_PCIE_RQ1_RQ_FIFO_FL_MASK}, - {"GLBL2_PCIE_RQ1_TLPSM", - GLBL2_PCIE_RQ1_TLPSM_MASK}, - {"GLBL2_PCIE_RQ1_TLPSM512", - GLBL2_PCIE_RQ1_TLPSM512_MASK}, - {"GLBL2_PCIE_RQ1_RREQ_RCB_OK", - GLBL2_PCIE_RQ1_RREQ_RCB_OK_MASK}, - {"GLBL2_PCIE_RQ1_RREQ0_SLV", - GLBL2_PCIE_RQ1_RREQ0_SLV_MASK}, - {"GLBL2_PCIE_RQ1_RREQ0_VLD", - GLBL2_PCIE_RQ1_RREQ0_VLD_MASK}, - {"GLBL2_PCIE_RQ1_RREQ0_RDY", - GLBL2_PCIE_RQ1_RREQ0_RDY_MASK}, - {"GLBL2_PCIE_RQ1_RREQ1_SLV", - GLBL2_PCIE_RQ1_RREQ1_SLV_MASK}, - {"GLBL2_PCIE_RQ1_RREQ1_VLD", - GLBL2_PCIE_RQ1_RREQ1_VLD_MASK}, - {"GLBL2_PCIE_RQ1_RREQ1_RDY", - GLBL2_PCIE_RQ1_RREQ1_RDY_MASK}, - {"GLBL2_PCIE_RQ1_WTLP_REQ", - GLBL2_PCIE_RQ1_WTLP_REQ_MASK}, - {"GLBL2_PCIE_RQ1_WTLP_STRADDLE", - GLBL2_PCIE_RQ1_WTLP_STRADDLE_MASK}, -}; - - -static struct regfield_info - glbl2_dbg_aximm_wr0_field_info[] = { - {"GLBL2_AXIMM_WR0_RSVD_1", - GLBL2_AXIMM_WR0_RSVD_1_MASK}, - {"GLBL2_AXIMM_WR0_WR_REQ", - GLBL2_AXIMM_WR0_WR_REQ_MASK}, - {"GLBL2_AXIMM_WR0_WR_CHN", - GLBL2_AXIMM_WR0_WR_CHN_MASK}, - {"GLBL2_AXIMM_WR0_WTLP_DATA_FIFO_EP", - GLBL2_AXIMM_WR0_WTLP_DATA_FIFO_EP_MASK}, - {"GLBL2_AXIMM_WR0_WPL_FIFO_EP", - GLBL2_AXIMM_WR0_WPL_FIFO_EP_MASK}, - {"GLBL2_AXIMM_WR0_BRSP_CLAIM_CHN", - GLBL2_AXIMM_WR0_BRSP_CLAIM_CHN_MASK}, - {"GLBL2_AXIMM_WR0_WRREQ_CNT", - GLBL2_AXIMM_WR0_WRREQ_CNT_MASK}, - {"GLBL2_AXIMM_WR0_BID", - GLBL2_AXIMM_WR0_BID_MASK}, - {"GLBL2_AXIMM_WR0_BVALID", - GLBL2_AXIMM_WR0_BVALID_MASK}, - {"GLBL2_AXIMM_WR0_BREADY", - GLBL2_AXIMM_WR0_BREADY_MASK}, - {"GLBL2_AXIMM_WR0_WVALID", - GLBL2_AXIMM_WR0_WVALID_MASK}, - {"GLBL2_AXIMM_WR0_WREADY", - GLBL2_AXIMM_WR0_WREADY_MASK}, - {"GLBL2_AXIMM_WR0_AWID", - GLBL2_AXIMM_WR0_AWID_MASK}, - {"GLBL2_AXIMM_WR0_AWVALID", - GLBL2_AXIMM_WR0_AWVALID_MASK}, - {"GLBL2_AXIMM_WR0_AWREADY", - GLBL2_AXIMM_WR0_AWREADY_MASK}, -}; - - -static struct regfield_info - glbl2_dbg_aximm_wr1_field_info[] = { - {"GLBL2_AXIMM_WR1_RSVD_1", - GLBL2_AXIMM_WR1_RSVD_1_MASK}, - {"GLBL2_AXIMM_WR1_BRSP_CNT4", - GLBL2_AXIMM_WR1_BRSP_CNT4_MASK}, - {"GLBL2_AXIMM_WR1_BRSP_CNT3", - GLBL2_AXIMM_WR1_BRSP_CNT3_MASK}, - {"GLBL2_AXIMM_WR1_BRSP_CNT2", - GLBL2_AXIMM_WR1_BRSP_CNT2_MASK}, - {"GLBL2_AXIMM_WR1_BRSP_CNT1", - GLBL2_AXIMM_WR1_BRSP_CNT1_MASK}, - {"GLBL2_AXIMM_WR1_BRSP_CNT0", - GLBL2_AXIMM_WR1_BRSP_CNT0_MASK}, -}; - - -static struct regfield_info - glbl2_dbg_aximm_rd0_field_info[] = { - {"GLBL2_AXIMM_RD0_RSVD_1", - GLBL2_AXIMM_RD0_RSVD_1_MASK}, - {"GLBL2_AXIMM_RD0_PND_CNT", - GLBL2_AXIMM_RD0_PND_CNT_MASK}, - {"GLBL2_AXIMM_RD0_RD_REQ", - GLBL2_AXIMM_RD0_RD_REQ_MASK}, - {"GLBL2_AXIMM_RD0_RD_CHNL", - GLBL2_AXIMM_RD0_RD_CHNL_MASK}, - {"GLBL2_AXIMM_RD0_RRSP_CLAIM_CHNL", - GLBL2_AXIMM_RD0_RRSP_CLAIM_CHNL_MASK}, - {"GLBL2_AXIMM_RD0_RID", - GLBL2_AXIMM_RD0_RID_MASK}, - {"GLBL2_AXIMM_RD0_RVALID", - GLBL2_AXIMM_RD0_RVALID_MASK}, - {"GLBL2_AXIMM_RD0_RREADY", - GLBL2_AXIMM_RD0_RREADY_MASK}, - {"GLBL2_AXIMM_RD0_ARID", - GLBL2_AXIMM_RD0_ARID_MASK}, - {"GLBL2_AXIMM_RD0_ARVALID", - GLBL2_AXIMM_RD0_ARVALID_MASK}, - {"GLBL2_AXIMM_RD0_ARREADY", - GLBL2_AXIMM_RD0_ARREADY_MASK}, -}; - - -static struct regfield_info - glbl2_dbg_aximm_rd1_field_info[] = { - {"GLBL2_AXIMM_RD1_RSVD_1", - GLBL2_AXIMM_RD1_RSVD_1_MASK}, - {"GLBL2_AXIMM_RD1_RRSP_CNT4", - GLBL2_AXIMM_RD1_RRSP_CNT4_MASK}, - {"GLBL2_AXIMM_RD1_RRSP_CNT3", - GLBL2_AXIMM_RD1_RRSP_CNT3_MASK}, - {"GLBL2_AXIMM_RD1_RRSP_CNT2", - GLBL2_AXIMM_RD1_RRSP_CNT2_MASK}, - {"GLBL2_AXIMM_RD1_RRSP_CNT1", - GLBL2_AXIMM_RD1_RRSP_CNT1_MASK}, - {"GLBL2_AXIMM_RD1_RRSP_CNT0", - GLBL2_AXIMM_RD1_RRSP_CNT0_MASK}, -}; - - -static struct regfield_info - glbl2_dbg_fab0_field_info[] = { - {"GLBL2_FAB0_H2C_INB_CONV_IN_VLD", - GLBL2_FAB0_H2C_INB_CONV_IN_VLD_MASK}, - {"GLBL2_FAB0_H2C_INB_CONV_IN_RDY", - GLBL2_FAB0_H2C_INB_CONV_IN_RDY_MASK}, - {"GLBL2_FAB0_H2C_SEG_IN_VLD", - GLBL2_FAB0_H2C_SEG_IN_VLD_MASK}, - {"GLBL2_FAB0_H2C_SEG_IN_RDY", - GLBL2_FAB0_H2C_SEG_IN_RDY_MASK}, - {"GLBL2_FAB0_H2C_SEG_OUT_VLD", - GLBL2_FAB0_H2C_SEG_OUT_VLD_MASK}, - {"GLBL2_FAB0_H2C_SEG_OUT_RDY", - GLBL2_FAB0_H2C_SEG_OUT_RDY_MASK}, - {"GLBL2_FAB0_H2C_MST_CRDT_STAT", - GLBL2_FAB0_H2C_MST_CRDT_STAT_MASK}, - {"GLBL2_FAB0_C2H_SLV_AFIFO_FULL", - GLBL2_FAB0_C2H_SLV_AFIFO_FULL_MASK}, - {"GLBL2_FAB0_C2H_SLV_AFIFO_EMPTY", - GLBL2_FAB0_C2H_SLV_AFIFO_EMPTY_MASK}, - {"GLBL2_FAB0_C2H_DESEG_SEG_VLD", - GLBL2_FAB0_C2H_DESEG_SEG_VLD_MASK}, - {"GLBL2_FAB0_C2H_DESEG_SEG_RDY", - GLBL2_FAB0_C2H_DESEG_SEG_RDY_MASK}, - {"GLBL2_FAB0_C2H_DESEG_OUT_VLD", - GLBL2_FAB0_C2H_DESEG_OUT_VLD_MASK}, - {"GLBL2_FAB0_C2H_DESEG_OUT_RDY", - GLBL2_FAB0_C2H_DESEG_OUT_RDY_MASK}, - {"GLBL2_FAB0_C2H_INB_DECONV_OUT_VLD", - GLBL2_FAB0_C2H_INB_DECONV_OUT_VLD_MASK}, - {"GLBL2_FAB0_C2H_INB_DECONV_OUT_RDY", - GLBL2_FAB0_C2H_INB_DECONV_OUT_RDY_MASK}, - {"GLBL2_FAB0_C2H_DSC_CRDT_AFIFO_FULL", - GLBL2_FAB0_C2H_DSC_CRDT_AFIFO_FULL_MASK}, - {"GLBL2_FAB0_C2H_DSC_CRDT_AFIFO_EMPTY", - GLBL2_FAB0_C2H_DSC_CRDT_AFIFO_EMPTY_MASK}, - {"GLBL2_FAB0_IRQ_IN_AFIFO_FULL", - GLBL2_FAB0_IRQ_IN_AFIFO_FULL_MASK}, - {"GLBL2_FAB0_IRQ_IN_AFIFO_EMPTY", - GLBL2_FAB0_IRQ_IN_AFIFO_EMPTY_MASK}, - {"GLBL2_FAB0_IMM_CRD_AFIFO_EMPTY", - GLBL2_FAB0_IMM_CRD_AFIFO_EMPTY_MASK}, -}; - - -static struct regfield_info - glbl2_dbg_fab1_field_info[] = { - {"GLBL2_FAB1_BYP_OUT_CRDT_STAT", - GLBL2_FAB1_BYP_OUT_CRDT_STAT_MASK}, - {"GLBL2_FAB1_TM_DSC_STS_CRDT_STAT", - GLBL2_FAB1_TM_DSC_STS_CRDT_STAT_MASK}, - {"GLBL2_FAB1_C2H_CMN_AFIFO_FULL", - GLBL2_FAB1_C2H_CMN_AFIFO_FULL_MASK}, - {"GLBL2_FAB1_C2H_CMN_AFIFO_EMPTY", - GLBL2_FAB1_C2H_CMN_AFIFO_EMPTY_MASK}, - {"GLBL2_FAB1_RSVD_1", - GLBL2_FAB1_RSVD_1_MASK}, - {"GLBL2_FAB1_C2H_BYP_IN_AFIFO_FULL", - GLBL2_FAB1_C2H_BYP_IN_AFIFO_FULL_MASK}, - {"GLBL2_FAB1_RSVD_2", - GLBL2_FAB1_RSVD_2_MASK}, - {"GLBL2_FAB1_C2H_BYP_IN_AFIFO_EMPTY", - GLBL2_FAB1_C2H_BYP_IN_AFIFO_EMPTY_MASK}, - {"GLBL2_FAB1_RSVD_3", - GLBL2_FAB1_RSVD_3_MASK}, - {"GLBL2_FAB1_H2C_BYP_IN_AFIFO_FULL", - GLBL2_FAB1_H2C_BYP_IN_AFIFO_FULL_MASK}, - {"GLBL2_FAB1_RSVD_4", - GLBL2_FAB1_RSVD_4_MASK}, - {"GLBL2_FAB1_H2C_BYP_IN_AFIFO_EMPTY", - GLBL2_FAB1_H2C_BYP_IN_AFIFO_EMPTY_MASK}, -}; - - -static struct regfield_info - glbl2_dbg_match_sel_field_info[] = { - {"GLBL2_MATCH_SEL_RSV", - GLBL2_MATCH_SEL_RSV_MASK}, - {"GLBL2_MATCH_SEL_CSR_SEL", - GLBL2_MATCH_SEL_CSR_SEL_MASK}, - {"GLBL2_MATCH_SEL_CSR_EN", - GLBL2_MATCH_SEL_CSR_EN_MASK}, - {"GLBL2_MATCH_SEL_ROTATE1", - GLBL2_MATCH_SEL_ROTATE1_MASK}, - {"GLBL2_MATCH_SEL_ROTATE0", - GLBL2_MATCH_SEL_ROTATE0_MASK}, - {"GLBL2_MATCH_SEL_SEL", - GLBL2_MATCH_SEL_SEL_MASK}, -}; - - -static struct regfield_info - glbl2_dbg_match_msk_field_info[] = { - {"GLBL2_MATCH_MSK", - GLBL2_MATCH_MSK_MASK}, -}; - - -static struct regfield_info - glbl2_dbg_match_pat_field_info[] = { - {"GLBL2_MATCH_PAT_PATTERN", - GLBL2_MATCH_PAT_PATTERN_MASK}, -}; - - -static struct regfield_info - glbl_rng_sz_1_field_info[] = { - {"GLBL_RNG_SZ_1_RSVD_1", - GLBL_RNG_SZ_1_RSVD_1_MASK}, - {"GLBL_RNG_SZ_1_RING_SIZE", - GLBL_RNG_SZ_1_RING_SIZE_MASK}, -}; - - -static struct regfield_info - glbl_rng_sz_2_field_info[] = { - {"GLBL_RNG_SZ_2_RSVD_1", - GLBL_RNG_SZ_2_RSVD_1_MASK}, - {"GLBL_RNG_SZ_2_RING_SIZE", - GLBL_RNG_SZ_2_RING_SIZE_MASK}, -}; - - -static struct regfield_info - glbl_rng_sz_3_field_info[] = { - {"GLBL_RNG_SZ_3_RSVD_1", - GLBL_RNG_SZ_3_RSVD_1_MASK}, - {"GLBL_RNG_SZ_3_RING_SIZE", - GLBL_RNG_SZ_3_RING_SIZE_MASK}, -}; - - -static struct regfield_info - glbl_rng_sz_4_field_info[] = { - {"GLBL_RNG_SZ_4_RSVD_1", - GLBL_RNG_SZ_4_RSVD_1_MASK}, - {"GLBL_RNG_SZ_4_RING_SIZE", - GLBL_RNG_SZ_4_RING_SIZE_MASK}, -}; - - -static struct regfield_info - glbl_rng_sz_5_field_info[] = { - {"GLBL_RNG_SZ_5_RSVD_1", - GLBL_RNG_SZ_5_RSVD_1_MASK}, - {"GLBL_RNG_SZ_5_RING_SIZE", - GLBL_RNG_SZ_5_RING_SIZE_MASK}, -}; - - -static struct regfield_info - glbl_rng_sz_6_field_info[] = { - {"GLBL_RNG_SZ_6_RSVD_1", - GLBL_RNG_SZ_6_RSVD_1_MASK}, - {"GLBL_RNG_SZ_6_RING_SIZE", - GLBL_RNG_SZ_6_RING_SIZE_MASK}, -}; - - -static struct regfield_info - glbl_rng_sz_7_field_info[] = { - {"GLBL_RNG_SZ_7_RSVD_1", - GLBL_RNG_SZ_7_RSVD_1_MASK}, - {"GLBL_RNG_SZ_7_RING_SIZE", - GLBL_RNG_SZ_7_RING_SIZE_MASK}, -}; - - -static struct regfield_info - glbl_rng_sz_8_field_info[] = { - {"GLBL_RNG_SZ_8_RSVD_1", - GLBL_RNG_SZ_8_RSVD_1_MASK}, - {"GLBL_RNG_SZ_8_RING_SIZE", - GLBL_RNG_SZ_8_RING_SIZE_MASK}, -}; - - -static struct regfield_info - glbl_rng_sz_9_field_info[] = { - {"GLBL_RNG_SZ_9_RSVD_1", - GLBL_RNG_SZ_9_RSVD_1_MASK}, - {"GLBL_RNG_SZ_9_RING_SIZE", - GLBL_RNG_SZ_9_RING_SIZE_MASK}, -}; - - -static struct regfield_info - glbl_rng_sz_a_field_info[] = { - {"GLBL_RNG_SZ_A_RSVD_1", - GLBL_RNG_SZ_A_RSVD_1_MASK}, - {"GLBL_RNG_SZ_A_RING_SIZE", - GLBL_RNG_SZ_A_RING_SIZE_MASK}, -}; - - -static struct regfield_info - glbl_rng_sz_b_field_info[] = { - {"GLBL_RNG_SZ_B_RSVD_1", - GLBL_RNG_SZ_B_RSVD_1_MASK}, - {"GLBL_RNG_SZ_B_RING_SIZE", - GLBL_RNG_SZ_B_RING_SIZE_MASK}, -}; - - -static struct regfield_info - glbl_rng_sz_c_field_info[] = { - {"GLBL_RNG_SZ_C_RSVD_1", - GLBL_RNG_SZ_C_RSVD_1_MASK}, - {"GLBL_RNG_SZ_C_RING_SIZE", - GLBL_RNG_SZ_C_RING_SIZE_MASK}, -}; - - -static struct regfield_info - glbl_rng_sz_d_field_info[] = { - {"GLBL_RNG_SZ_D_RSVD_1", - GLBL_RNG_SZ_D_RSVD_1_MASK}, - {"GLBL_RNG_SZ_D_RING_SIZE", - GLBL_RNG_SZ_D_RING_SIZE_MASK}, -}; - - -static struct regfield_info - glbl_rng_sz_e_field_info[] = { - {"GLBL_RNG_SZ_E_RSVD_1", - GLBL_RNG_SZ_E_RSVD_1_MASK}, - {"GLBL_RNG_SZ_E_RING_SIZE", - GLBL_RNG_SZ_E_RING_SIZE_MASK}, -}; - - -static struct regfield_info - glbl_rng_sz_f_field_info[] = { - {"GLBL_RNG_SZ_F_RSVD_1", - GLBL_RNG_SZ_F_RSVD_1_MASK}, - {"GLBL_RNG_SZ_F_RING_SIZE", - GLBL_RNG_SZ_F_RING_SIZE_MASK}, -}; - - -static struct regfield_info - glbl_rng_sz_10_field_info[] = { - {"GLBL_RNG_SZ_10_RSVD_1", - GLBL_RNG_SZ_10_RSVD_1_MASK}, - {"GLBL_RNG_SZ_10_RING_SIZE", - GLBL_RNG_SZ_10_RING_SIZE_MASK}, -}; - - -static struct regfield_info - glbl_err_stat_field_info[] = { - {"GLBL_ERR_STAT_RSVD_1", - GLBL_ERR_STAT_RSVD_1_MASK}, - {"GLBL_ERR_STAT_ERR_FAB", - GLBL_ERR_STAT_ERR_FAB_MASK}, - {"GLBL_ERR_STAT_ERR_H2C_ST", - GLBL_ERR_STAT_ERR_H2C_ST_MASK}, - {"GLBL_ERR_STAT_ERR_BDG", - GLBL_ERR_STAT_ERR_BDG_MASK}, - {"GLBL_ERR_STAT_IND_CTXT_CMD_ERR", - GLBL_ERR_STAT_IND_CTXT_CMD_ERR_MASK}, - {"GLBL_ERR_STAT_ERR_C2H_ST", - GLBL_ERR_STAT_ERR_C2H_ST_MASK}, - {"GLBL_ERR_STAT_ERR_C2H_MM_1", - GLBL_ERR_STAT_ERR_C2H_MM_1_MASK}, - {"GLBL_ERR_STAT_ERR_C2H_MM_0", - GLBL_ERR_STAT_ERR_C2H_MM_0_MASK}, - {"GLBL_ERR_STAT_ERR_H2C_MM_1", - GLBL_ERR_STAT_ERR_H2C_MM_1_MASK}, - {"GLBL_ERR_STAT_ERR_H2C_MM_0", - GLBL_ERR_STAT_ERR_H2C_MM_0_MASK}, - {"GLBL_ERR_STAT_ERR_TRQ", - GLBL_ERR_STAT_ERR_TRQ_MASK}, - {"GLBL_ERR_STAT_ERR_DSC", - GLBL_ERR_STAT_ERR_DSC_MASK}, - {"GLBL_ERR_STAT_ERR_RAM_DBE", - GLBL_ERR_STAT_ERR_RAM_DBE_MASK}, - {"GLBL_ERR_STAT_ERR_RAM_SBE", - GLBL_ERR_STAT_ERR_RAM_SBE_MASK}, -}; - - -static struct regfield_info - glbl_err_mask_field_info[] = { - {"GLBL_ERR", - GLBL_ERR_MASK}, -}; - - -static struct regfield_info - glbl_dsc_cfg_field_info[] = { - {"GLBL_DSC_CFG_RSVD_1", - GLBL_DSC_CFG_RSVD_1_MASK}, - {"GLBL_DSC_CFG_C2H_UODSC_LIMIT", - GLBL_DSC_CFG_C2H_UODSC_LIMIT_MASK}, - {"GLBL_DSC_CFG_H2C_UODSC_LIMIT", - GLBL_DSC_CFG_H2C_UODSC_LIMIT_MASK}, - {"GLBL_DSC_CFG_UNC_OVR_COR", - GLBL_DSC_CFG_UNC_OVR_COR_MASK}, - {"GLBL_DSC_CFG_CTXT_FER_DIS", - GLBL_DSC_CFG_CTXT_FER_DIS_MASK}, - {"GLBL_DSC_CFG_RSVD_2", - GLBL_DSC_CFG_RSVD_2_MASK}, - {"GLBL_DSC_CFG_MAXFETCH", - GLBL_DSC_CFG_MAXFETCH_MASK}, - {"GLBL_DSC_CFG_WB_ACC_INT", - GLBL_DSC_CFG_WB_ACC_INT_MASK}, -}; - - -static struct regfield_info - glbl_dsc_err_sts_field_info[] = { - {"GLBL_DSC_ERR_STS_RSVD_1", - GLBL_DSC_ERR_STS_RSVD_1_MASK}, - {"GLBL_DSC_ERR_STS_PORT_ID", - GLBL_DSC_ERR_STS_PORT_ID_MASK}, - {"GLBL_DSC_ERR_STS_SBE", - GLBL_DSC_ERR_STS_SBE_MASK}, - {"GLBL_DSC_ERR_STS_DBE", - GLBL_DSC_ERR_STS_DBE_MASK}, - {"GLBL_DSC_ERR_STS_RQ_CANCEL", - GLBL_DSC_ERR_STS_RQ_CANCEL_MASK}, - {"GLBL_DSC_ERR_STS_DSC", - GLBL_DSC_ERR_STS_DSC_MASK}, - {"GLBL_DSC_ERR_STS_DMA", - GLBL_DSC_ERR_STS_DMA_MASK}, - {"GLBL_DSC_ERR_STS_FLR_CANCEL", - GLBL_DSC_ERR_STS_FLR_CANCEL_MASK}, - {"GLBL_DSC_ERR_STS_RSVD_2", - GLBL_DSC_ERR_STS_RSVD_2_MASK}, - {"GLBL_DSC_ERR_STS_DAT_POISON", - GLBL_DSC_ERR_STS_DAT_POISON_MASK}, - {"GLBL_DSC_ERR_STS_TIMEOUT", - GLBL_DSC_ERR_STS_TIMEOUT_MASK}, - {"GLBL_DSC_ERR_STS_FLR", - GLBL_DSC_ERR_STS_FLR_MASK}, - {"GLBL_DSC_ERR_STS_TAG", - GLBL_DSC_ERR_STS_TAG_MASK}, - {"GLBL_DSC_ERR_STS_ADDR", - GLBL_DSC_ERR_STS_ADDR_MASK}, - {"GLBL_DSC_ERR_STS_PARAM", - GLBL_DSC_ERR_STS_PARAM_MASK}, - {"GLBL_DSC_ERR_STS_BCNT", - GLBL_DSC_ERR_STS_BCNT_MASK}, - {"GLBL_DSC_ERR_STS_UR_CA", - GLBL_DSC_ERR_STS_UR_CA_MASK}, - {"GLBL_DSC_ERR_STS_POISON", - GLBL_DSC_ERR_STS_POISON_MASK}, -}; - - -static struct regfield_info - glbl_dsc_err_msk_field_info[] = { - {"GLBL_DSC_ERR_MSK", - GLBL_DSC_ERR_MSK_MASK}, -}; - - -static struct regfield_info - glbl_dsc_err_log0_field_info[] = { - {"GLBL_DSC_ERR_LOG0_VALID", - GLBL_DSC_ERR_LOG0_VALID_MASK}, - {"GLBL_DSC_ERR_LOG0_SEL", - GLBL_DSC_ERR_LOG0_SEL_MASK}, - {"GLBL_DSC_ERR_LOG0_RSVD_1", - GLBL_DSC_ERR_LOG0_RSVD_1_MASK}, - {"GLBL_DSC_ERR_LOG0_QID", - GLBL_DSC_ERR_LOG0_QID_MASK}, -}; - - -static struct regfield_info - glbl_dsc_err_log1_field_info[] = { - {"GLBL_DSC_ERR_LOG1_RSVD_1", - GLBL_DSC_ERR_LOG1_RSVD_1_MASK}, - {"GLBL_DSC_ERR_LOG1_CIDX", - GLBL_DSC_ERR_LOG1_CIDX_MASK}, - {"GLBL_DSC_ERR_LOG1_RSVD_2", - GLBL_DSC_ERR_LOG1_RSVD_2_MASK}, - {"GLBL_DSC_ERR_LOG1_SUB_TYPE", - GLBL_DSC_ERR_LOG1_SUB_TYPE_MASK}, - {"GLBL_DSC_ERR_LOG1_ERR_TYPE", - GLBL_DSC_ERR_LOG1_ERR_TYPE_MASK}, -}; - - -static struct regfield_info - glbl_trq_err_sts_field_info[] = { - {"GLBL_TRQ_ERR_STS_RSVD_1", - GLBL_TRQ_ERR_STS_RSVD_1_MASK}, - {"GLBL_TRQ_ERR_STS_TCP_QSPC_TIMEOUT", - GLBL_TRQ_ERR_STS_TCP_QSPC_TIMEOUT_MASK}, - {"GLBL_TRQ_ERR_STS_RSVD_2", - GLBL_TRQ_ERR_STS_RSVD_2_MASK}, - {"GLBL_TRQ_ERR_STS_QID_RANGE", - GLBL_TRQ_ERR_STS_QID_RANGE_MASK}, - {"GLBL_TRQ_ERR_STS_QSPC_UNMAPPED", - GLBL_TRQ_ERR_STS_QSPC_UNMAPPED_MASK}, - {"GLBL_TRQ_ERR_STS_TCP_CSR_TIMEOUT", - GLBL_TRQ_ERR_STS_TCP_CSR_TIMEOUT_MASK}, - {"GLBL_TRQ_ERR_STS_RSVD_3", - GLBL_TRQ_ERR_STS_RSVD_3_MASK}, - {"GLBL_TRQ_ERR_STS_VF_ACCESS_ERR", - GLBL_TRQ_ERR_STS_VF_ACCESS_ERR_MASK}, - {"GLBL_TRQ_ERR_STS_CSR_UNMAPPED", - GLBL_TRQ_ERR_STS_CSR_UNMAPPED_MASK}, -}; - - -static struct regfield_info - glbl_trq_err_msk_field_info[] = { - {"GLBL_TRQ_ERR_MSK", - GLBL_TRQ_ERR_MSK_MASK}, -}; - - -static struct regfield_info - glbl_trq_err_log_field_info[] = { - {"GLBL_TRQ_ERR_LOG_SRC", - GLBL_TRQ_ERR_LOG_SRC_MASK}, - {"GLBL_TRQ_ERR_LOG_TARGET", - GLBL_TRQ_ERR_LOG_TARGET_MASK}, - {"GLBL_TRQ_ERR_LOG_FUNC", - GLBL_TRQ_ERR_LOG_FUNC_MASK}, - {"GLBL_TRQ_ERR_LOG_ADDRESS", - GLBL_TRQ_ERR_LOG_ADDRESS_MASK}, -}; - - -static struct regfield_info - glbl_dsc_dbg_dat0_field_info[] = { - {"GLBL_DSC_DAT0_RSVD_1", - GLBL_DSC_DAT0_RSVD_1_MASK}, - {"GLBL_DSC_DAT0_CTXT_ARB_DIR", - GLBL_DSC_DAT0_CTXT_ARB_DIR_MASK}, - {"GLBL_DSC_DAT0_CTXT_ARB_QID", - GLBL_DSC_DAT0_CTXT_ARB_QID_MASK}, - {"GLBL_DSC_DAT0_CTXT_ARB_REQ", - GLBL_DSC_DAT0_CTXT_ARB_REQ_MASK}, - {"GLBL_DSC_DAT0_IRQ_FIFO_FL", - GLBL_DSC_DAT0_IRQ_FIFO_FL_MASK}, - {"GLBL_DSC_DAT0_TMSTALL", - GLBL_DSC_DAT0_TMSTALL_MASK}, - {"GLBL_DSC_DAT0_RRQ_STALL", - GLBL_DSC_DAT0_RRQ_STALL_MASK}, - {"GLBL_DSC_DAT0_RCP_FIFO_SPC_STALL", - GLBL_DSC_DAT0_RCP_FIFO_SPC_STALL_MASK}, - {"GLBL_DSC_DAT0_RRQ_FIFO_SPC_STALL", - GLBL_DSC_DAT0_RRQ_FIFO_SPC_STALL_MASK}, - {"GLBL_DSC_DAT0_FAB_MRKR_RSP_STALL", - GLBL_DSC_DAT0_FAB_MRKR_RSP_STALL_MASK}, - {"GLBL_DSC_DAT0_DSC_OUT_STALL", - GLBL_DSC_DAT0_DSC_OUT_STALL_MASK}, -}; - - -static struct regfield_info - glbl_dsc_dbg_dat1_field_info[] = { - {"GLBL_DSC_DAT1_RSVD_1", - GLBL_DSC_DAT1_RSVD_1_MASK}, - {"GLBL_DSC_DAT1_EVT_SPC_C2H", - GLBL_DSC_DAT1_EVT_SPC_C2H_MASK}, - {"GLBL_DSC_DAT1_EVT_SP_H2C", - GLBL_DSC_DAT1_EVT_SP_H2C_MASK}, - {"GLBL_DSC_DAT1_DSC_SPC_C2H", - GLBL_DSC_DAT1_DSC_SPC_C2H_MASK}, - {"GLBL_DSC_DAT1_DSC_SPC_H2C", - GLBL_DSC_DAT1_DSC_SPC_H2C_MASK}, -}; - - -static struct regfield_info - glbl_dsc_dbg_ctl_field_info[] = { - {"GLBL_DSC_CTL_RSVD_1", - GLBL_DSC_CTL_RSVD_1_MASK}, - {"GLBL_DSC_CTL_LAT_QID", - GLBL_DSC_CTL_LAT_QID_MASK}, - {"GLBL_DSC_CTL_DSC_ENG_LAT_CLR", - GLBL_DSC_CTL_DSC_ENG_LAT_CLR_MASK}, - {"GLBL_DSC_CTL_SELECT", - GLBL_DSC_CTL_SELECT_MASK}, -}; - - -static struct regfield_info - glbl_dsc_err_log2_field_info[] = { - {"GLBL_DSC_ERR_LOG2_OLD_PIDX", - GLBL_DSC_ERR_LOG2_OLD_PIDX_MASK}, - {"GLBL_DSC_ERR_LOG2_NEW_PIDX", - GLBL_DSC_ERR_LOG2_NEW_PIDX_MASK}, -}; - - -static struct regfield_info - glbl_glbl_interrupt_cfg_field_info[] = { - {"GLBL_GLBL_INTERRUPT_CFG_RSVD_1", - GLBL_GLBL_INTERRUPT_CFG_RSVD_1_MASK}, - {"GLBL_GLBL_INTERRUPT_CFG_LGCY_INTR_PENDING", - GLBL_GLBL_INTERRUPT_CFG_LGCY_INTR_PENDING_MASK}, - {"GLBL_GLBL_INTERRUPT_CFG_EN_LGCY_INTR", - GLBL_GLBL_INTERRUPT_CFG_EN_LGCY_INTR_MASK}, -}; - - -static struct regfield_info - glbl_vch_host_profile_field_info[] = { - {"GLBL_VCH_HOST_PROFILE_RSVD_1", - GLBL_VCH_HOST_PROFILE_RSVD_1_MASK}, - {"GLBL_VCH_HOST_PROFILE_2C_MM", - GLBL_VCH_HOST_PROFILE_2C_MM_MASK}, - {"GLBL_VCH_HOST_PROFILE_2C_ST", - GLBL_VCH_HOST_PROFILE_2C_ST_MASK}, - {"GLBL_VCH_HOST_PROFILE_VCH_DSC", - GLBL_VCH_HOST_PROFILE_VCH_DSC_MASK}, - {"GLBL_VCH_HOST_PROFILE_VCH_INT_MSG", - GLBL_VCH_HOST_PROFILE_VCH_INT_MSG_MASK}, - {"GLBL_VCH_HOST_PROFILE_VCH_INT_AGGR", - GLBL_VCH_HOST_PROFILE_VCH_INT_AGGR_MASK}, - {"GLBL_VCH_HOST_PROFILE_VCH_CMPT", - GLBL_VCH_HOST_PROFILE_VCH_CMPT_MASK}, - {"GLBL_VCH_HOST_PROFILE_VCH_C2H_PLD", - GLBL_VCH_HOST_PROFILE_VCH_C2H_PLD_MASK}, -}; - - -static struct regfield_info - glbl_bridge_host_profile_field_info[] = { - {"GLBL_BRIDGE_HOST_PROFILE_RSVD_1", - GLBL_BRIDGE_HOST_PROFILE_RSVD_1_MASK}, - {"GLBL_BRIDGE_HOST_PROFILE_BDGID", - GLBL_BRIDGE_HOST_PROFILE_BDGID_MASK}, -}; - - -static struct regfield_info - aximm_irq_dest_addr_field_info[] = { - {"AXIMM_IRQ_DEST_ADDR_ADDR", - AXIMM_IRQ_DEST_ADDR_ADDR_MASK}, -}; - - -static struct regfield_info - fab_err_log_field_info[] = { - {"FAB_ERR_LOG_RSVD_1", - FAB_ERR_LOG_RSVD_1_MASK}, - {"FAB_ERR_LOG_SRC", - FAB_ERR_LOG_SRC_MASK}, -}; - - -static struct regfield_info - glbl_req_err_sts_field_info[] = { - {"GLBL_REQ_ERR_STS_RSVD_1", - GLBL_REQ_ERR_STS_RSVD_1_MASK}, - {"GLBL_REQ_ERR_STS_RC_DISCONTINUE", - GLBL_REQ_ERR_STS_RC_DISCONTINUE_MASK}, - {"GLBL_REQ_ERR_STS_RC_PRTY", - GLBL_REQ_ERR_STS_RC_PRTY_MASK}, - {"GLBL_REQ_ERR_STS_RC_FLR", - GLBL_REQ_ERR_STS_RC_FLR_MASK}, - {"GLBL_REQ_ERR_STS_RC_TIMEOUT", - GLBL_REQ_ERR_STS_RC_TIMEOUT_MASK}, - {"GLBL_REQ_ERR_STS_RC_INV_BCNT", - GLBL_REQ_ERR_STS_RC_INV_BCNT_MASK}, - {"GLBL_REQ_ERR_STS_RC_INV_TAG", - GLBL_REQ_ERR_STS_RC_INV_TAG_MASK}, - {"GLBL_REQ_ERR_STS_RC_START_ADDR_MISMCH", - GLBL_REQ_ERR_STS_RC_START_ADDR_MISMCH_MASK}, - {"GLBL_REQ_ERR_STS_RC_RID_TC_ATTR_MISMCH", - GLBL_REQ_ERR_STS_RC_RID_TC_ATTR_MISMCH_MASK}, - {"GLBL_REQ_ERR_STS_RC_NO_DATA", - GLBL_REQ_ERR_STS_RC_NO_DATA_MASK}, - {"GLBL_REQ_ERR_STS_RC_UR_CA_CRS", - GLBL_REQ_ERR_STS_RC_UR_CA_CRS_MASK}, - {"GLBL_REQ_ERR_STS_RC_POISONED", - GLBL_REQ_ERR_STS_RC_POISONED_MASK}, -}; - - -static struct regfield_info - glbl_req_err_msk_field_info[] = { - {"GLBL_REQ_ERR_MSK", - GLBL_REQ_ERR_MSK_MASK}, -}; - - -static struct regfield_info - glbl_dsc_dbg_lat0_a_field_info[] = { - {"GLBL_DSC_LAT0_A_LAT_MAX", - GLBL_DSC_LAT0_A_LAT_MAX_MASK}, - {"GLBL_DSC_LAT0_A_LAT_MIN", - GLBL_DSC_LAT0_A_LAT_MIN_MASK}, -}; - - -static struct regfield_info - glbl_dsc_dbg_lat1_a_field_info[] = { - {"GLBL_DSC_LAT1_A_RSVD", - GLBL_DSC_LAT1_A_RSVD_MASK}, - {"GLBL_DSC_LAT1_A_LAT_OVF", - GLBL_DSC_LAT1_A_LAT_OVF_MASK}, - {"GLBL_DSC_LAT1_A_LAT_AVG", - GLBL_DSC_LAT1_A_LAT_AVG_MASK}, -}; - - -static struct regfield_info - glbl_dsc_crd_ctr0_a_field_info[] = { - {"GLBL_DSC_CRD_CTR0_A_CRD_RCV_CNT", - GLBL_DSC_CRD_CTR0_A_CRD_RCV_CNT_MASK}, -}; - - -static struct regfield_info - glbl_dsc_crd_ctr1_a_field_info[] = { - {"GLBL_DSC_CRD_CTR1_A_CRD_RCV_CNT", - GLBL_DSC_CRD_CTR1_A_CRD_RCV_CNT_MASK}, -}; - - -static struct regfield_info - glbl_dsc_crd_ctr2_a_field_info[] = { - {"GLBL_DSC_CRD_CTR2_A_CRD_RCV_NRDY_CNT", - GLBL_DSC_CRD_CTR2_A_CRD_RCV_NRDY_CNT_MASK}, -}; - - -static struct regfield_info - glbl_dsc_crd_ctr3_a_field_info[] = { - {"GLBL_DSC_CRD_CTR3_A_CRD_RCV_NRDY_CNT", - GLBL_DSC_CRD_CTR3_A_CRD_RCV_NRDY_CNT_MASK}, -}; - - -static struct regfield_info - glbl_dsc_imm_crd_ctr0_a_field_info[] = { - {"GLBL_DSC_IMM_CRD_CTR0_A_RCV_CNT", - GLBL_DSC_IMM_CRD_CTR0_A_RCV_CNT_MASK}, -}; - - -static struct regfield_info - glbl_dsc_imm_crd_ctr1_a_field_info[] = { - {"GLBL_DSC_IMM_CRD_CTR1_A_RCV_CNT", - GLBL_DSC_IMM_CRD_CTR1_A_RCV_CNT_MASK}, -}; - - -static struct regfield_info - glbl_dsc_imm_crd_ctr2_a_field_info[] = { - {"GLBL_DSC_IMM_CRD_CTR2_A_RCV_NRDY_CNT", - GLBL_DSC_IMM_CRD_CTR2_A_RCV_NRDY_CNT_MASK}, -}; - - -static struct regfield_info - glbl_dsc_imm_crd_ctr3_a_field_info[] = { - {"GLBL_DSC_IMM_CRD_CTR3_A_RCV_NRDY_CNT", - GLBL_DSC_IMM_CRD_CTR3_A_RCV_NRDY_CNT_MASK}, -}; - - -static struct regfield_info - glbl_dsc_h2c_out_ctr0_a_field_info[] = { - {"GLBL_DSC_H2C_OUT_CTR0_A_H2CVLD_CNT", - GLBL_DSC_H2C_OUT_CTR0_A_H2CVLD_CNT_MASK}, -}; - - -static struct regfield_info - glbl_dsc_h2c_out_ctr1_a_field_info[] = { - {"GLBL_DSC_H2C_OUT_CTR1_A_H2CVLD_CNT", - GLBL_DSC_H2C_OUT_CTR1_A_H2CVLD_CNT_MASK}, -}; - - -static struct regfield_info - glbl_dsc_h2c_out_ctr2_a_field_info[] = { - {"GLBL_DSC_H2C_OUT_CTR2_A_H2CVLD_NRDY_CNT", - GLBL_DSC_H2C_OUT_CTR2_A_H2CVLD_NRDY_CNT_MASK}, -}; - - -static struct regfield_info - glbl_dsc_h2c_out_ctr3_a_field_info[] = { - {"GLBL_DSC_H2C_OUT_CTR3_A_H2CVLD_NRDY_CNT", - GLBL_DSC_H2C_OUT_CTR3_A_H2CVLD_NRDY_CNT_MASK}, -}; - - -static struct regfield_info - glbl_dsc_c2h_out_ctr0_a_field_info[] = { - {"GLBL_DSC_C2H_OUT_CTR0_A_C2HVLD_CNT", - GLBL_DSC_C2H_OUT_CTR0_A_C2HVLD_CNT_MASK}, -}; - - -static struct regfield_info - glbl_dsc_c2h_out_ctr1_a_field_info[] = { - {"GLBL_DSC_C2H_OUT_CTR1_A_C2HVLD_CNT", - GLBL_DSC_C2H_OUT_CTR1_A_C2HVLD_CNT_MASK}, -}; - - -static struct regfield_info - glbl_dsc_c2h_out_ctr2_a_field_info[] = { - {"GLBL_DSC_C2H_OUT_CTR2_A_C2HVLD_NRDY_CNT", - GLBL_DSC_C2H_OUT_CTR2_A_C2HVLD_NRDY_CNT_MASK}, -}; - - -static struct regfield_info - glbl_dsc_c2h_out_ctr3_a_field_info[] = { - {"GLBL_DSC_C2H_OUT_CTR3_A_C2HVLD_NRDY_CNT", - GLBL_DSC_C2H_OUT_CTR3_A_C2HVLD_NRDY_CNT_MASK}, -}; - - -static struct regfield_info - t_field_info[] = { - {"T_USER_CTR_MAX", - T_USER_CTR_MAX_MASK}, -}; - - -static struct regfield_info - glbl_perf_cntr_ctl_a1_field_info[] = { - {"GLBL_PERF_CNTR_CTL_A1_RSVD", - GLBL_PERF_CNTR_CTL_A1_RSVD_MASK}, - {"GLBL_PERF_CNTR_CTL_A1_USER_CTR_CLEAR", - GLBL_PERF_CNTR_CTL_A1_USER_CTR_CLEAR_MASK}, - {"GLBL_PERF_CNTR_CTL_A1_USER_CTR_READ", - GLBL_PERF_CNTR_CTL_A1_USER_CTR_READ_MASK}, - {"GLBL_PERF_CNTR_CTL_A1_USER_CTR_MAX", - GLBL_PERF_CNTR_CTL_A1_USER_CTR_MAX_MASK}, -}; - - -static struct regfield_info - glbl_free_cnt_a0_field_info[] = { - {"GLBL_FREE_CNT_A0_S", - GLBL_FREE_CNT_A0_S_MASK}, -}; - - -static struct regfield_info - glbl_free_cnt_a1_field_info[] = { - {"GLBL_FREE_CNT_A1_RSVD", - GLBL_FREE_CNT_A1_RSVD_MASK}, - {"GLBL_FREE_CNT_A1_S", - GLBL_FREE_CNT_A1_S_MASK}, -}; - - -static struct regfield_info - glbl_axis_h2c_cnt_a0_field_info[] = { - {"GLBL_AXIS_H2C_CNT_A0_MPKT_CNTS", - GLBL_AXIS_H2C_CNT_A0_MPKT_CNTS_MASK}, -}; - - -static struct regfield_info - glbl_axis_h2c_cnt_a1_field_info[] = { - {"GLBL_AXIS_H2C_CNT_A1_MIDLE_CNTS", - GLBL_AXIS_H2C_CNT_A1_MIDLE_CNTS_MASK}, - {"GLBL_AXIS_H2C_CNT_A1_MPKT_CNTS", - GLBL_AXIS_H2C_CNT_A1_MPKT_CNTS_MASK}, -}; - - -static struct regfield_info - glbl_axis_h2c_cnt_a2_field_info[] = { - {"GLBL_AXIS_H2C_CNT_A2_MIDLE_CNTS", - GLBL_AXIS_H2C_CNT_A2_MIDLE_CNTS_MASK}, -}; - - -static struct regfield_info - glbl_axis_h2c_cnt_a3_field_info[] = { - {"GLBL_AXIS_H2C_CNT_A3_MACTV_CNTS", - GLBL_AXIS_H2C_CNT_A3_MACTV_CNTS_MASK}, -}; - - -static struct regfield_info - glbl_axis_h2c_cnt_a4_field_info[] = { - {"GLBL_AXIS_H2C_CNT_A4_MBUSY_CNTS", - GLBL_AXIS_H2C_CNT_A4_MBUSY_CNTS_MASK}, - {"GLBL_AXIS_H2C_CNT_A4_MACTV_CNTS", - GLBL_AXIS_H2C_CNT_A4_MACTV_CNTS_MASK}, -}; - - -static struct regfield_info - glbl_axis_h2c_cnt_a5_field_info[] = { - {"GLBL_AXIS_H2C_CNT_A5_MBUSY_CNTS", - GLBL_AXIS_H2C_CNT_A5_MBUSY_CNTS_MASK}, -}; - - -static struct regfield_info - glbl_axis_c2h_cnt_a0_field_info[] = { - {"GLBL_AXIS_C2H_CNT_A0_SPKT_CNTS", - GLBL_AXIS_C2H_CNT_A0_SPKT_CNTS_MASK}, -}; - - -static struct regfield_info - glbl_axis_c2h_cnt_a1_field_info[] = { - {"GLBL_AXIS_C2H_CNT_A1_SIDLE_CNTS", - GLBL_AXIS_C2H_CNT_A1_SIDLE_CNTS_MASK}, - {"GLBL_AXIS_C2H_CNT_A1_SPKT_CNTS", - GLBL_AXIS_C2H_CNT_A1_SPKT_CNTS_MASK}, -}; - - -static struct regfield_info - glbl_axis_c2h_cnt_a2_field_info[] = { - {"GLBL_AXIS_C2H_CNT_A2_SIDLE_CNTS", - GLBL_AXIS_C2H_CNT_A2_SIDLE_CNTS_MASK}, -}; - - -static struct regfield_info - glbl_axis_c2h_cnt_a3_field_info[] = { - {"GLBL_AXIS_C2H_CNT_A3_SACTV_CNTS", - GLBL_AXIS_C2H_CNT_A3_SACTV_CNTS_MASK}, -}; - - -static struct regfield_info - glbl_axis_c2h_cnt_a4_field_info[] = { - {"GLBL_AXIS_C2H_CNT_A4_SBUSY_CNTS", - GLBL_AXIS_C2H_CNT_A4_SBUSY_CNTS_MASK}, - {"GLBL_AXIS_C2H_CNT_A4_SACTV_CNTS", - GLBL_AXIS_C2H_CNT_A4_SACTV_CNTS_MASK}, -}; - - -static struct regfield_info - glbl_axis_c2h_cnt_a5_field_info[] = { - {"GLBL_AXIS_C2H_CNT_A5_SBUSY_CNTS", - GLBL_AXIS_C2H_CNT_A5_SBUSY_CNTS_MASK}, -}; - - -static struct regfield_info - glbl_m_axi_wr_cnt_a0_field_info[] = { - {"GLBL_M_AXI_WR_CNT_A0_PKT_CNTS", - GLBL_M_AXI_WR_CNT_A0_PKT_CNTS_MASK}, -}; - - -static struct regfield_info - glbl_m_axi_wr_cnt_a1_field_info[] = { - {"GLBL_M_AXI_WR_CNT_A1_IDLE_CNTS", - GLBL_M_AXI_WR_CNT_A1_IDLE_CNTS_MASK}, - {"GLBL_M_AXI_WR_CNT_A1_PKT_CNTS", - GLBL_M_AXI_WR_CNT_A1_PKT_CNTS_MASK}, -}; - - -static struct regfield_info - glbl_m_axi_wr_cnt_a2_field_info[] = { - {"GLBL_M_AXI_WR_CNT_A2_IDLE_CNTS", - GLBL_M_AXI_WR_CNT_A2_IDLE_CNTS_MASK}, -}; - - -static struct regfield_info - glbl_m_axi_wr_cnt_a3_field_info[] = { - {"GLBL_M_AXI_WR_CNT_A3_ACTV_CNTS", - GLBL_M_AXI_WR_CNT_A3_ACTV_CNTS_MASK}, -}; - - -static struct regfield_info - glbl_m_axi_wr_cnt_a4_field_info[] = { - {"GLBL_M_AXI_WR_CNT_A4_BUSY_CNTS", - GLBL_M_AXI_WR_CNT_A4_BUSY_CNTS_MASK}, - {"GLBL_M_AXI_WR_CNT_A4_ACTV_CNTS", - GLBL_M_AXI_WR_CNT_A4_ACTV_CNTS_MASK}, -}; - - -static struct regfield_info - glbl_m_axi_wr_cnt_a5_field_info[] = { - {"GLBL_M_AXI_WR_CNT_A5_BUSY_CNTS", - GLBL_M_AXI_WR_CNT_A5_BUSY_CNTS_MASK}, -}; - - -static struct regfield_info - glbl_m_axi_rd_cnt_a0_field_info[] = { - {"GLBL_M_AXI_RD_CNT_A0_PKT_CNTS", - GLBL_M_AXI_RD_CNT_A0_PKT_CNTS_MASK}, -}; - - -static struct regfield_info - glbl_m_axi_rd_cnt_a1_field_info[] = { - {"GLBL_M_AXI_RD_CNT_A1_IDLE_CNTS", - GLBL_M_AXI_RD_CNT_A1_IDLE_CNTS_MASK}, - {"GLBL_M_AXI_RD_CNT_A1_PKT_CNTS", - GLBL_M_AXI_RD_CNT_A1_PKT_CNTS_MASK}, -}; - - -static struct regfield_info - glbl_m_axi_rd_cnt_a2_field_info[] = { - {"GLBL_M_AXI_RD_CNT_A2_IDLE_CNTS", - GLBL_M_AXI_RD_CNT_A2_IDLE_CNTS_MASK}, -}; - - -static struct regfield_info - glbl_m_axi_rd_cnt_a3_field_info[] = { - {"GLBL_M_AXI_RD_CNT_A3_ACTV_CNTS", - GLBL_M_AXI_RD_CNT_A3_ACTV_CNTS_MASK}, -}; - - -static struct regfield_info - glbl_m_axi_rd_cnt_a4_field_info[] = { - {"GLBL_M_AXI_RD_CNT_A4_BUSY_CNTS", - GLBL_M_AXI_RD_CNT_A4_BUSY_CNTS_MASK}, - {"GLBL_M_AXI_RD_CNT_A4_ACTV_CNTS", - GLBL_M_AXI_RD_CNT_A4_ACTV_CNTS_MASK}, -}; - - -static struct regfield_info - glbl_m_axi_rd_cnt_a5_field_info[] = { - {"GLBL_M_AXI_RD_CNT_A5_BUSY_CNTS", - GLBL_M_AXI_RD_CNT_A5_BUSY_CNTS_MASK}, -}; - - -static struct regfield_info - glbl_m_axib_wr_cnt_a0_field_info[] = { - {"GLBL_M_AXIB_WR_CNT_A0_PKT_CNTS", - GLBL_M_AXIB_WR_CNT_A0_PKT_CNTS_MASK}, -}; - - -static struct regfield_info - glbl_m_axib_wr_cnt_a1_field_info[] = { - {"GLBL_M_AXIB_WR_CNT_A1_IDLE_CNTS", - GLBL_M_AXIB_WR_CNT_A1_IDLE_CNTS_MASK}, - {"GLBL_M_AXIB_WR_CNT_A1_PKT_CNTS", - GLBL_M_AXIB_WR_CNT_A1_PKT_CNTS_MASK}, -}; - - -static struct regfield_info - glbl_m_axib_wr_cnt_a2_field_info[] = { - {"GLBL_M_AXIB_WR_CNT_A2_IDLE_CNTS", - GLBL_M_AXIB_WR_CNT_A2_IDLE_CNTS_MASK}, -}; - - -static struct regfield_info - glbl_m_axib_wr_cnt_a3_field_info[] = { - {"GLBL_M_AXIB_WR_CNT_A3_ACTV_CNTS", - GLBL_M_AXIB_WR_CNT_A3_ACTV_CNTS_MASK}, -}; - - -static struct regfield_info - glbl_m_axib_wr_cnt_a4_field_info[] = { - {"GLBL_M_AXIB_WR_CNT_A4_BUSY_CNTS", - GLBL_M_AXIB_WR_CNT_A4_BUSY_CNTS_MASK}, - {"GLBL_M_AXIB_WR_CNT_A4_ACTV_CNTS", - GLBL_M_AXIB_WR_CNT_A4_ACTV_CNTS_MASK}, -}; - - -static struct regfield_info - glbl_m_axib_wr_cnt_a5_field_info[] = { - {"GLBL_M_AXIB_WR_CNT_A5_BUSY_CNTS", - GLBL_M_AXIB_WR_CNT_A5_BUSY_CNTS_MASK}, -}; - - -static struct regfield_info - glbl_m_axib_rd_cnt_a0_field_info[] = { - {"GLBL_M_AXIB_RD_CNT_A0_PKT_CNTS", - GLBL_M_AXIB_RD_CNT_A0_PKT_CNTS_MASK}, -}; - - -static struct regfield_info - glbl_m_axib_rd_cnt_a1_field_info[] = { - {"GLBL_M_AXIB_RD_CNT_A1_IDLE_CNTS", - GLBL_M_AXIB_RD_CNT_A1_IDLE_CNTS_MASK}, - {"GLBL_M_AXIB_RD_CNT_A1_PKT_CNTS", - GLBL_M_AXIB_RD_CNT_A1_PKT_CNTS_MASK}, -}; - - -static struct regfield_info - glbl_m_axib_rd_cnt_a2_field_info[] = { - {"GLBL_M_AXIB_RD_CNT_A2_IDLE_CNTS", - GLBL_M_AXIB_RD_CNT_A2_IDLE_CNTS_MASK}, -}; - - -static struct regfield_info - glbl_m_axib_rd_cnt_a3_field_info[] = { - {"GLBL_M_AXIB_RD_CNT_A3_ACTV_CNTS", - GLBL_M_AXIB_RD_CNT_A3_ACTV_CNTS_MASK}, -}; - - -static struct regfield_info - glbl_m_axib_rd_cnt_a4_field_info[] = { - {"GLBL_M_AXIB_RD_CNT_A4_BUSY_CNTS", - GLBL_M_AXIB_RD_CNT_A4_BUSY_CNTS_MASK}, - {"GLBL_M_AXIB_RD_CNT_A4_ACTV_CNTS", - GLBL_M_AXIB_RD_CNT_A4_ACTV_CNTS_MASK}, -}; - - -static struct regfield_info - glbl_m_axib_rd_cnt_a5_field_info[] = { - {"GLBL_M_AXIB_RD_CNT_A5_BUSY_CNTS", - GLBL_M_AXIB_RD_CNT_A5_BUSY_CNTS_MASK}, -}; - - -static struct regfield_info - glbl_s_axi_wr_cnt_a0_field_info[] = { - {"GLBL_S_AXI_WR_CNT_A0_PKT_CNTS", - GLBL_S_AXI_WR_CNT_A0_PKT_CNTS_MASK}, -}; - - -static struct regfield_info - glbl_s_axi_wr_cnt_a1_field_info[] = { - {"GLBL_S_AXI_WR_CNT_A1_IDLE_CNTS", - GLBL_S_AXI_WR_CNT_A1_IDLE_CNTS_MASK}, - {"GLBL_S_AXI_WR_CNT_A1_PKT_CNTS", - GLBL_S_AXI_WR_CNT_A1_PKT_CNTS_MASK}, -}; - - -static struct regfield_info - glbl_s_axi_wr_cnt_a2_field_info[] = { - {"GLBL_S_AXI_WR_CNT_A2_IDLE_CNTS", - GLBL_S_AXI_WR_CNT_A2_IDLE_CNTS_MASK}, -}; - - -static struct regfield_info - glbl_s_axi_wr_cnt_a3_field_info[] = { - {"GLBL_S_AXI_WR_CNT_A3_ACTV_CNTS", - GLBL_S_AXI_WR_CNT_A3_ACTV_CNTS_MASK}, -}; - - -static struct regfield_info - glbl_s_axi_wr_cnt_a4_field_info[] = { - {"GLBL_S_AXI_WR_CNT_A4_BUSY_CNTS", - GLBL_S_AXI_WR_CNT_A4_BUSY_CNTS_MASK}, - {"GLBL_S_AXI_WR_CNT_A4_ACTV_CNTS", - GLBL_S_AXI_WR_CNT_A4_ACTV_CNTS_MASK}, -}; - - -static struct regfield_info - glbl_s_axi_wr_cnt_a5_field_info[] = { - {"GLBL_S_AXI_WR_CNT_A5_BUSY_CNTS", - GLBL_S_AXI_WR_CNT_A5_BUSY_CNTS_MASK}, -}; - - -static struct regfield_info - glbl_s_axi_rd_cnt_a0_field_info[] = { - {"GLBL_S_AXI_RD_CNT_A0_PKT_CNTS", - GLBL_S_AXI_RD_CNT_A0_PKT_CNTS_MASK}, -}; - - -static struct regfield_info - glbl_s_axi_rd_cnt_a1_field_info[] = { - {"GLBL_S_AXI_RD_CNT_A1_IDLE_CNTS", - GLBL_S_AXI_RD_CNT_A1_IDLE_CNTS_MASK}, - {"GLBL_S_AXI_RD_CNT_A1_PKT_CNTS", - GLBL_S_AXI_RD_CNT_A1_PKT_CNTS_MASK}, -}; - - -static struct regfield_info - glbl_s_axi_rd_cnt_a2_field_info[] = { - {"GLBL_S_AXI_RD_CNT_A2_IDLE_CNTS", - GLBL_S_AXI_RD_CNT_A2_IDLE_CNTS_MASK}, -}; - - -static struct regfield_info - glbl_s_axi_rd_cnt_a3_field_info[] = { - {"GLBL_S_AXI_RD_CNT_A3_ACTV_CNTS", - GLBL_S_AXI_RD_CNT_A3_ACTV_CNTS_MASK}, -}; - - -static struct regfield_info - glbl_s_axi_rd_cnt_a4_field_info[] = { - {"GLBL_S_AXI_RD_CNT_A4_BUSY_CNTS", - GLBL_S_AXI_RD_CNT_A4_BUSY_CNTS_MASK}, - {"GLBL_S_AXI_RD_CNT_A4_ACTV_CNTS", - GLBL_S_AXI_RD_CNT_A4_ACTV_CNTS_MASK}, -}; - - -static struct regfield_info - glbl_s_axi_rd_cnt_a5_field_info[] = { - {"GLBL_S_AXI_RD_CNT_A5_BUSY_CNTS", - GLBL_S_AXI_RD_CNT_A5_BUSY_CNTS_MASK}, -}; - - -static struct regfield_info - glbl_s_axis_cmp_cnt_a0_field_info[] = { - {"GLBL_S_AXIS_CMP_CNT_A0_PKT_CNTS", - GLBL_S_AXIS_CMP_CNT_A0_PKT_CNTS_MASK}, -}; - - -static struct regfield_info - glbl_s_axis_cmp_cnt_a1_field_info[] = { - {"GLBL_S_AXIS_CMP_CNT_A1_IDLE_CNTS", - GLBL_S_AXIS_CMP_CNT_A1_IDLE_CNTS_MASK}, - {"GLBL_S_AXIS_CMP_CNT_A1_PKT_CNTS", - GLBL_S_AXIS_CMP_CNT_A1_PKT_CNTS_MASK}, -}; - - -static struct regfield_info - glbl_s_axis_cmp_cnt_a2_field_info[] = { - {"GLBL_S_AXIS_CMP_CNT_A2_IDLE_CNTS", - GLBL_S_AXIS_CMP_CNT_A2_IDLE_CNTS_MASK}, -}; - - -static struct regfield_info - glbl_s_axis_cmp_cnt_a3_field_info[] = { - {"GLBL_S_AXIS_CMP_CNT_A3_ACTV_CNTS", - GLBL_S_AXIS_CMP_CNT_A3_ACTV_CNTS_MASK}, -}; - - -static struct regfield_info - glbl_s_axis_cmp_cnt_a4_field_info[] = { - {"GLBL_S_AXIS_CMP_CNT_A4_BUSY_CNTS", - GLBL_S_AXIS_CMP_CNT_A4_BUSY_CNTS_MASK}, - {"GLBL_S_AXIS_CMP_CNT_A4_ACTV_CNTS", - GLBL_S_AXIS_CMP_CNT_A4_ACTV_CNTS_MASK}, -}; - - -static struct regfield_info - glbl_s_axis_cmp_cnt_a5_field_info[] = { - {"GLBL_S_AXIS_CMP_CNT_A5_BUSY_CNTS", - GLBL_S_AXIS_CMP_CNT_A5_BUSY_CNTS_MASK}, -}; - - -static struct regfield_info - ind_ctxt_data_field_info[] = { - {"IND_CTXT_DATA_DATA", - IND_CTXT_DATA_DATA_MASK}, -}; - - -static struct regfield_info - ind_ctxt_mask_field_info[] = { - {"IND_CTXT", - IND_CTXT_MASK}, -}; - - -static struct regfield_info - ind_ctxt_cmd_field_info[] = { - {"IND_CTXT_CMD_RSVD_1", - IND_CTXT_CMD_RSVD_1_MASK}, - {"IND_CTXT_CMD_QID", - IND_CTXT_CMD_QID_MASK}, - {"IND_CTXT_CMD_OP", - IND_CTXT_CMD_OP_MASK}, - {"IND_CTXT_CMD_SEL", - IND_CTXT_CMD_SEL_MASK}, - {"IND_CTXT_CMD_BUSY", - IND_CTXT_CMD_BUSY_MASK}, -}; - - -static struct regfield_info - c2h_timer_cnt_field_info[] = { - {"C2H_TIMER_CNT_RSVD_1", - C2H_TIMER_CNT_RSVD_1_MASK}, - {"C2H_TIMER_CNT", - C2H_TIMER_CNT_MASK}, -}; - - -static struct regfield_info - c2h_cnt_th_field_info[] = { - {"C2H_CNT_TH_RSVD_1", - C2H_CNT_TH_RSVD_1_MASK}, - {"C2H_CNT_TH_THESHOLD_CNT", - C2H_CNT_TH_THESHOLD_CNT_MASK}, -}; - - -static struct regfield_info - c2h_pfch_cfg_1_field_info[] = { - {"C2H_PFCH_CFG_1_EVT_QCNT_TH", - C2H_PFCH_CFG_1_EVT_QCNT_TH_MASK}, - {"C2H_PFCH_CFG_1_QCNT", - C2H_PFCH_CFG_1_QCNT_MASK}, -}; - - -static struct regfield_info - c2h_pfch_cfg_2_field_info[] = { - {"C2H_PFCH_CFG_2_FENCE", - C2H_PFCH_CFG_2_FENCE_MASK}, - {"C2H_PFCH_CFG_2_RSVD", - C2H_PFCH_CFG_2_RSVD_MASK}, - {"C2H_PFCH_CFG_2_VAR_DESC_NO_DROP", - C2H_PFCH_CFG_2_VAR_DESC_NO_DROP_MASK}, - {"C2H_PFCH_CFG_2_LL_SZ_TH", - C2H_PFCH_CFG_2_LL_SZ_TH_MASK}, - {"C2H_PFCH_CFG_2_VAR_DESC_NUM", - C2H_PFCH_CFG_2_VAR_DESC_NUM_MASK}, - {"C2H_PFCH_CFG_2_NUM", - C2H_PFCH_CFG_2_NUM_MASK}, -}; - - -static struct regfield_info - c2h_stat_s_axis_c2h_accepted_field_info[] = { - {"C2H_STAT_S_AXIS_C2H_ACCEPTED", - C2H_STAT_S_AXIS_C2H_ACCEPTED_MASK}, -}; - - -static struct regfield_info - c2h_stat_s_axis_wrb_accepted_field_info[] = { - {"C2H_STAT_S_AXIS_WRB_ACCEPTED", - C2H_STAT_S_AXIS_WRB_ACCEPTED_MASK}, -}; - - -static struct regfield_info - c2h_stat_desc_rsp_pkt_accepted_field_info[] = { - {"C2H_STAT_DESC_RSP_PKT_ACCEPTED_D", - C2H_STAT_DESC_RSP_PKT_ACCEPTED_D_MASK}, -}; - - -static struct regfield_info - c2h_stat_axis_pkg_cmp_field_info[] = { - {"C2H_STAT_AXIS_PKG_CMP", - C2H_STAT_AXIS_PKG_CMP_MASK}, -}; - - -static struct regfield_info - c2h_stat_desc_rsp_accepted_field_info[] = { - {"C2H_STAT_DESC_RSP_ACCEPTED_D", - C2H_STAT_DESC_RSP_ACCEPTED_D_MASK}, -}; - - -static struct regfield_info - c2h_stat_desc_rsp_cmp_field_info[] = { - {"C2H_STAT_DESC_RSP_CMP_D", - C2H_STAT_DESC_RSP_CMP_D_MASK}, -}; - - -static struct regfield_info - c2h_stat_wrq_out_field_info[] = { - {"C2H_STAT_WRQ_OUT", - C2H_STAT_WRQ_OUT_MASK}, -}; - - -static struct regfield_info - c2h_stat_wpl_ren_accepted_field_info[] = { - {"C2H_STAT_WPL_REN_ACCEPTED", - C2H_STAT_WPL_REN_ACCEPTED_MASK}, -}; - - -static struct regfield_info - c2h_stat_total_wrq_len_field_info[] = { - {"C2H_STAT_TOTAL_WRQ_LEN", - C2H_STAT_TOTAL_WRQ_LEN_MASK}, -}; - - -static struct regfield_info - c2h_stat_total_wpl_len_field_info[] = { - {"C2H_STAT_TOTAL_WPL_LEN", - C2H_STAT_TOTAL_WPL_LEN_MASK}, -}; - - -static struct regfield_info - c2h_buf_sz_field_info[] = { - {"C2H_BUF_SZ_IZE", - C2H_BUF_SZ_IZE_MASK}, -}; - - -static struct regfield_info - c2h_err_stat_field_info[] = { - {"C2H_ERR_STAT_RSVD_1", - C2H_ERR_STAT_RSVD_1_MASK}, - {"C2H_ERR_STAT_WRB_PORT_ID_ERR", - C2H_ERR_STAT_WRB_PORT_ID_ERR_MASK}, - {"C2H_ERR_STAT_HDR_PAR_ERR", - C2H_ERR_STAT_HDR_PAR_ERR_MASK}, - {"C2H_ERR_STAT_HDR_ECC_COR_ERR", - C2H_ERR_STAT_HDR_ECC_COR_ERR_MASK}, - {"C2H_ERR_STAT_HDR_ECC_UNC_ERR", - C2H_ERR_STAT_HDR_ECC_UNC_ERR_MASK}, - {"C2H_ERR_STAT_AVL_RING_DSC_ERR", - C2H_ERR_STAT_AVL_RING_DSC_ERR_MASK}, - {"C2H_ERR_STAT_WRB_PRTY_ERR", - C2H_ERR_STAT_WRB_PRTY_ERR_MASK}, - {"C2H_ERR_STAT_WRB_CIDX_ERR", - C2H_ERR_STAT_WRB_CIDX_ERR_MASK}, - {"C2H_ERR_STAT_WRB_QFULL_ERR", - C2H_ERR_STAT_WRB_QFULL_ERR_MASK}, - {"C2H_ERR_STAT_WRB_INV_Q_ERR", - C2H_ERR_STAT_WRB_INV_Q_ERR_MASK}, - {"C2H_ERR_STAT_RSVD_2", - C2H_ERR_STAT_RSVD_2_MASK}, - {"C2H_ERR_STAT_PORT_ID_CTXT_MISMATCH", - C2H_ERR_STAT_PORT_ID_CTXT_MISMATCH_MASK}, - {"C2H_ERR_STAT_ERR_DESC_CNT", - C2H_ERR_STAT_ERR_DESC_CNT_MASK}, - {"C2H_ERR_STAT_RSVD_3", - C2H_ERR_STAT_RSVD_3_MASK}, - {"C2H_ERR_STAT_MSI_INT_FAIL", - C2H_ERR_STAT_MSI_INT_FAIL_MASK}, - {"C2H_ERR_STAT_ENG_WPL_DATA_PAR_ERR", - C2H_ERR_STAT_ENG_WPL_DATA_PAR_ERR_MASK}, - {"C2H_ERR_STAT_RSVD_4", - C2H_ERR_STAT_RSVD_4_MASK}, - {"C2H_ERR_STAT_DESC_RSP_ERR", - C2H_ERR_STAT_DESC_RSP_ERR_MASK}, - {"C2H_ERR_STAT_QID_MISMATCH", - C2H_ERR_STAT_QID_MISMATCH_MASK}, - {"C2H_ERR_STAT_SH_CMPT_DSC_ERR", - C2H_ERR_STAT_SH_CMPT_DSC_ERR_MASK}, - {"C2H_ERR_STAT_LEN_MISMATCH", - C2H_ERR_STAT_LEN_MISMATCH_MASK}, - {"C2H_ERR_STAT_MTY_MISMATCH", - C2H_ERR_STAT_MTY_MISMATCH_MASK}, -}; - - -static struct regfield_info - c2h_err_mask_field_info[] = { - {"C2H_ERR_EN", - C2H_ERR_EN_MASK}, -}; - - -static struct regfield_info - c2h_fatal_err_stat_field_info[] = { - {"C2H_FATAL_ERR_STAT_RSVD_1", - C2H_FATAL_ERR_STAT_RSVD_1_MASK}, - {"C2H_FATAL_ERR_STAT_HDR_ECC_UNC_ERR", - C2H_FATAL_ERR_STAT_HDR_ECC_UNC_ERR_MASK}, - {"C2H_FATAL_ERR_STAT_AVL_RING_FIFO_RAM_RDBE", - C2H_FATAL_ERR_STAT_AVL_RING_FIFO_RAM_RDBE_MASK}, - {"C2H_FATAL_ERR_STAT_WPL_DATA_PAR_ERR", - C2H_FATAL_ERR_STAT_WPL_DATA_PAR_ERR_MASK}, - {"C2H_FATAL_ERR_STAT_PLD_FIFO_RAM_RDBE", - C2H_FATAL_ERR_STAT_PLD_FIFO_RAM_RDBE_MASK}, - {"C2H_FATAL_ERR_STAT_QID_FIFO_RAM_RDBE", - C2H_FATAL_ERR_STAT_QID_FIFO_RAM_RDBE_MASK}, - {"C2H_FATAL_ERR_STAT_CMPT_FIFO_RAM_RDBE", - C2H_FATAL_ERR_STAT_CMPT_FIFO_RAM_RDBE_MASK}, - {"C2H_FATAL_ERR_STAT_WRB_COAL_DATA_RAM_RDBE", - C2H_FATAL_ERR_STAT_WRB_COAL_DATA_RAM_RDBE_MASK}, - {"C2H_FATAL_ERR_STAT_RESERVED2", - C2H_FATAL_ERR_STAT_RESERVED2_MASK}, - {"C2H_FATAL_ERR_STAT_INT_CTXT_RAM_RDBE", - C2H_FATAL_ERR_STAT_INT_CTXT_RAM_RDBE_MASK}, - {"C2H_FATAL_ERR_STAT_DESC_REQ_FIFO_RAM_RDBE", - C2H_FATAL_ERR_STAT_DESC_REQ_FIFO_RAM_RDBE_MASK}, - {"C2H_FATAL_ERR_STAT_PFCH_CTXT_RAM_RDBE", - C2H_FATAL_ERR_STAT_PFCH_CTXT_RAM_RDBE_MASK}, - {"C2H_FATAL_ERR_STAT_WRB_CTXT_RAM_RDBE", - C2H_FATAL_ERR_STAT_WRB_CTXT_RAM_RDBE_MASK}, - {"C2H_FATAL_ERR_STAT_PFCH_LL_RAM_RDBE", - C2H_FATAL_ERR_STAT_PFCH_LL_RAM_RDBE_MASK}, - {"C2H_FATAL_ERR_STAT_TIMER_FIFO_RAM_RDBE", - C2H_FATAL_ERR_STAT_TIMER_FIFO_RAM_RDBE_MASK}, - {"C2H_FATAL_ERR_STAT_QID_MISMATCH", - C2H_FATAL_ERR_STAT_QID_MISMATCH_MASK}, - {"C2H_FATAL_ERR_STAT_RESERVED1", - C2H_FATAL_ERR_STAT_RESERVED1_MASK}, - {"C2H_FATAL_ERR_STAT_LEN_MISMATCH", - C2H_FATAL_ERR_STAT_LEN_MISMATCH_MASK}, - {"C2H_FATAL_ERR_STAT_MTY_MISMATCH", - C2H_FATAL_ERR_STAT_MTY_MISMATCH_MASK}, -}; - - -static struct regfield_info - c2h_fatal_err_mask_field_info[] = { - {"C2H_FATAL_ERR_C2HEN", - C2H_FATAL_ERR_C2HEN_MASK}, -}; - - -static struct regfield_info - c2h_fatal_err_enable_field_info[] = { - {"C2H_FATAL_ERR_ENABLE_RSVD_1", - C2H_FATAL_ERR_ENABLE_RSVD_1_MASK}, - {"C2H_FATAL_ERR_ENABLE_WPL_PAR_INV", - C2H_FATAL_ERR_ENABLE_WPL_PAR_INV_MASK}, - {"C2H_FATAL_ERR_ENABLE_WRQ_DIS", - C2H_FATAL_ERR_ENABLE_WRQ_DIS_MASK}, -}; - - -static struct regfield_info - glbl_err_int_field_info[] = { - {"GLBL_ERR_INT_RSVD_1", - GLBL_ERR_INT_RSVD_1_MASK}, - {"GLBL_ERR_INT_HOST_ID", - GLBL_ERR_INT_HOST_ID_MASK}, - {"GLBL_ERR_INT_DIS_INTR_ON_VF", - GLBL_ERR_INT_DIS_INTR_ON_VF_MASK}, - {"GLBL_ERR_INT_ARM", - GLBL_ERR_INT_ARM_MASK}, - {"GLBL_ERR_INT_EN_COAL", - GLBL_ERR_INT_EN_COAL_MASK}, - {"GLBL_ERR_INT_VEC", - GLBL_ERR_INT_VEC_MASK}, - {"GLBL_ERR_INT_FUNC", - GLBL_ERR_INT_FUNC_MASK}, -}; - - -static struct regfield_info - c2h_pfch_cfg_field_info[] = { - {"C2H_PFCH_CFG_EVTFL_TH", - C2H_PFCH_CFG_EVTFL_TH_MASK}, - {"C2H_PFCH_CFG_FL_TH", - C2H_PFCH_CFG_FL_TH_MASK}, -}; - - -static struct regfield_info - c2h_int_timer_tick_field_info[] = { - {"C2H_INT_TIMER_TICK", - C2H_INT_TIMER_TICK_MASK}, -}; - - -static struct regfield_info - c2h_stat_desc_rsp_drop_accepted_field_info[] = { - {"C2H_STAT_DESC_RSP_DROP_ACCEPTED_D", - C2H_STAT_DESC_RSP_DROP_ACCEPTED_D_MASK}, -}; - - -static struct regfield_info - c2h_stat_desc_rsp_err_accepted_field_info[] = { - {"C2H_STAT_DESC_RSP_ERR_ACCEPTED_D", - C2H_STAT_DESC_RSP_ERR_ACCEPTED_D_MASK}, -}; - - -static struct regfield_info - c2h_stat_desc_req_field_info[] = { - {"C2H_STAT_DESC_REQ", - C2H_STAT_DESC_REQ_MASK}, -}; - - -static struct regfield_info - c2h_stat_dbg_dma_eng_0_field_info[] = { - {"C2H_STAT_DMA_ENG_0_S_AXIS_C2H_TVALID", - C2H_STAT_DMA_ENG_0_S_AXIS_C2H_TVALID_MASK}, - {"C2H_STAT_DMA_ENG_0_S_AXIS_C2H_TREADY", - C2H_STAT_DMA_ENG_0_S_AXIS_C2H_TREADY_MASK}, - {"C2H_STAT_DMA_ENG_0_S_AXIS_WRB_TVALID", - C2H_STAT_DMA_ENG_0_S_AXIS_WRB_TVALID_MASK}, - {"C2H_STAT_DMA_ENG_0_S_AXIS_WRB_TREADY", - C2H_STAT_DMA_ENG_0_S_AXIS_WRB_TREADY_MASK}, - {"C2H_STAT_DMA_ENG_0_PLD_FIFO_IN_RDY", - C2H_STAT_DMA_ENG_0_PLD_FIFO_IN_RDY_MASK}, - {"C2H_STAT_DMA_ENG_0_QID_FIFO_IN_RDY", - C2H_STAT_DMA_ENG_0_QID_FIFO_IN_RDY_MASK}, - {"C2H_STAT_DMA_ENG_0_ARB_FIFO_OUT_VLD", - C2H_STAT_DMA_ENG_0_ARB_FIFO_OUT_VLD_MASK}, - {"C2H_STAT_DMA_ENG_0_ARB_FIFO_OUT_QID", - C2H_STAT_DMA_ENG_0_ARB_FIFO_OUT_QID_MASK}, - {"C2H_STAT_DMA_ENG_0_WRB_FIFO_IN_RDY", - C2H_STAT_DMA_ENG_0_WRB_FIFO_IN_RDY_MASK}, - {"C2H_STAT_DMA_ENG_0_WRB_FIFO_OUT_CNT", - C2H_STAT_DMA_ENG_0_WRB_FIFO_OUT_CNT_MASK}, - {"C2H_STAT_DMA_ENG_0_WRB_SM_CS", - C2H_STAT_DMA_ENG_0_WRB_SM_CS_MASK}, - {"C2H_STAT_DMA_ENG_0_MAIN_SM_CS", - C2H_STAT_DMA_ENG_0_MAIN_SM_CS_MASK}, -}; - - -static struct regfield_info - c2h_stat_dbg_dma_eng_1_field_info[] = { - {"C2H_STAT_DMA_ENG_1_WRB_USER_0_CMPT_TYPE", - C2H_STAT_DMA_ENG_1_WRB_USER_0_CMPT_TYPE_MASK}, - {"C2H_STAT_DMA_ENG_1_DESC_RSP_FIFO_OUT_VLD", - C2H_STAT_DMA_ENG_1_DESC_RSP_FIFO_OUT_VLD_MASK}, - {"C2H_STAT_DMA_ENG_1_QID_FIFO_OUT_CNT", - C2H_STAT_DMA_ENG_1_QID_FIFO_OUT_CNT_MASK}, - {"C2H_STAT_DMA_ENG_1_PLD_FIFO_OUT_CNT", - C2H_STAT_DMA_ENG_1_PLD_FIFO_OUT_CNT_MASK}, - {"C2H_STAT_DMA_ENG_1_PLD_ST_FIFO_CNT", - C2H_STAT_DMA_ENG_1_PLD_ST_FIFO_CNT_MASK}, -}; - - -static struct regfield_info - c2h_stat_dbg_dma_eng_2_field_info[] = { - {"C2H_STAT_DMA_ENG_2_WRB_USER_1_CMPT_TYPE", - C2H_STAT_DMA_ENG_2_WRB_USER_1_CMPT_TYPE_MASK}, - {"C2H_STAT_DMA_ENG_2_DESC_RSP_FIFO_OUT_VLD_1", - C2H_STAT_DMA_ENG_2_DESC_RSP_FIFO_OUT_VLD_1_MASK}, - {"C2H_STAT_DMA_ENG_2_QID_FIFO_OUT_CNT_1", - C2H_STAT_DMA_ENG_2_QID_FIFO_OUT_CNT_1_MASK}, - {"C2H_STAT_DMA_ENG_2_PLD_FIFO_OUT_CNT_1", - C2H_STAT_DMA_ENG_2_PLD_FIFO_OUT_CNT_1_MASK}, - {"C2H_STAT_DMA_ENG_2_PLD_ST_FIFO_CNT_1", - C2H_STAT_DMA_ENG_2_PLD_ST_FIFO_CNT_1_MASK}, -}; - - -static struct regfield_info - c2h_stat_dbg_dma_eng_3_field_info[] = { - {"C2H_STAT_DMA_ENG_3_QID_FIFO_OUT_DAT_HAS_CMPT", - C2H_STAT_DMA_ENG_3_QID_FIFO_OUT_DAT_HAS_CMPT_MASK}, - {"C2H_STAT_DMA_ENG_3_QID_FIFO_OUT_DAT_MARKER", - C2H_STAT_DMA_ENG_3_QID_FIFO_OUT_DAT_MARKER_MASK}, - {"C2H_STAT_DMA_ENG_3_QID_FIFO_OUT_DAT_DROP_REQ", - C2H_STAT_DMA_ENG_3_QID_FIFO_OUT_DAT_DROP_REQ_MASK}, - {"C2H_STAT_DMA_ENG_3_QID_FIFO_OUT_DAT_QID", - C2H_STAT_DMA_ENG_3_QID_FIFO_OUT_DAT_QID_MASK}, - {"C2H_STAT_DMA_ENG_3_WR_HDR_FIFO_OUT_CNT", - C2H_STAT_DMA_ENG_3_WR_HDR_FIFO_OUT_CNT_MASK}, - {"C2H_STAT_DMA_ENG_3_QID_FIFO_OUT_VLD", - C2H_STAT_DMA_ENG_3_QID_FIFO_OUT_VLD_MASK}, - {"C2H_STAT_DMA_ENG_3_PLD_FIFO_OUT_VLD", - C2H_STAT_DMA_ENG_3_PLD_FIFO_OUT_VLD_MASK}, - {"C2H_STAT_DMA_ENG_3_PLD_ST_FIFO_OUT_VLD", - C2H_STAT_DMA_ENG_3_PLD_ST_FIFO_OUT_VLD_MASK}, - {"C2H_STAT_DMA_ENG_3_PLD_ST_FIFO_OUT_DATA_EOP", - C2H_STAT_DMA_ENG_3_PLD_ST_FIFO_OUT_DATA_EOP_MASK}, - {"C2H_STAT_DMA_ENG_3_PLD_ST_FIFO_OUT_DATA_AVL_IDX_ENABLE", - C2H_STAT_DMA_ENG_3_PLD_ST_FIFO_OUT_DATA_AVL_IDX_ENABLE_MASK}, - {"C2H_STAT_DMA_ENG_3_PLD_ST_FIFO_OUT_DATA_DROP", - C2H_STAT_DMA_ENG_3_PLD_ST_FIFO_OUT_DATA_DROP_MASK}, - {"C2H_STAT_DMA_ENG_3_PLD_ST_FIFO_OUT_DATA_ERR", - C2H_STAT_DMA_ENG_3_PLD_ST_FIFO_OUT_DATA_ERR_MASK}, - {"C2H_STAT_DMA_ENG_3_DESC_CNT_FIFO_IN_RDY", - C2H_STAT_DMA_ENG_3_DESC_CNT_FIFO_IN_RDY_MASK}, - {"C2H_STAT_DMA_ENG_3_DESC_RSP_FIFO_IN_RDY", - C2H_STAT_DMA_ENG_3_DESC_RSP_FIFO_IN_RDY_MASK}, - {"C2H_STAT_DMA_ENG_3_PLD_PKT_ID_LARGER", - C2H_STAT_DMA_ENG_3_PLD_PKT_ID_LARGER_MASK}, - {"C2H_STAT_DMA_ENG_3_WCP_FIFO_IN_RDY", - C2H_STAT_DMA_ENG_3_WCP_FIFO_IN_RDY_MASK}, - {"C2H_STAT_DMA_ENG_3_PLD_ST_FIFO_IN_RDY", - C2H_STAT_DMA_ENG_3_PLD_ST_FIFO_IN_RDY_MASK}, -}; - - -static struct regfield_info - c2h_dbg_pfch_err_ctxt_field_info[] = { - {"C2H_PFCH_ERR_CTXT_RSVD_1", - C2H_PFCH_ERR_CTXT_RSVD_1_MASK}, - {"C2H_PFCH_ERR_CTXT_ERR_STAT", - C2H_PFCH_ERR_CTXT_ERR_STAT_MASK}, - {"C2H_PFCH_ERR_CTXT_CMD_WR", - C2H_PFCH_ERR_CTXT_CMD_WR_MASK}, - {"C2H_PFCH_ERR_CTXT_QID", - C2H_PFCH_ERR_CTXT_QID_MASK}, - {"C2H_PFCH_ERR_CTXT_DONE", - C2H_PFCH_ERR_CTXT_DONE_MASK}, -}; - - -static struct regfield_info - c2h_first_err_qid_field_info[] = { - {"C2H_FIRST_ERR_QID_RSVD_1", - C2H_FIRST_ERR_QID_RSVD_1_MASK}, - {"C2H_FIRST_ERR_QID_ERR_TYPE", - C2H_FIRST_ERR_QID_ERR_TYPE_MASK}, - {"C2H_FIRST_ERR_QID_RSVD", - C2H_FIRST_ERR_QID_RSVD_MASK}, - {"C2H_FIRST_ERR_QID_QID", - C2H_FIRST_ERR_QID_QID_MASK}, -}; - - -static struct regfield_info - stat_num_wrb_in_field_info[] = { - {"STAT_NUM_WRB_IN_RSVD_1", - STAT_NUM_WRB_IN_RSVD_1_MASK}, - {"STAT_NUM_WRB_IN_WRB_CNT", - STAT_NUM_WRB_IN_WRB_CNT_MASK}, -}; - - -static struct regfield_info - stat_num_wrb_out_field_info[] = { - {"STAT_NUM_WRB_OUT_RSVD_1", - STAT_NUM_WRB_OUT_RSVD_1_MASK}, - {"STAT_NUM_WRB_OUT_WRB_CNT", - STAT_NUM_WRB_OUT_WRB_CNT_MASK}, -}; - - -static struct regfield_info - stat_num_wrb_drp_field_info[] = { - {"STAT_NUM_WRB_DRP_RSVD_1", - STAT_NUM_WRB_DRP_RSVD_1_MASK}, - {"STAT_NUM_WRB_DRP_WRB_CNT", - STAT_NUM_WRB_DRP_WRB_CNT_MASK}, -}; - - -static struct regfield_info - stat_num_stat_desc_out_field_info[] = { - {"STAT_NUM_STAT_DESC_OUT_RSVD_1", - STAT_NUM_STAT_DESC_OUT_RSVD_1_MASK}, - {"STAT_NUM_STAT_DESC_OUT_CNT", - STAT_NUM_STAT_DESC_OUT_CNT_MASK}, -}; - - -static struct regfield_info - stat_num_dsc_crdt_sent_field_info[] = { - {"STAT_NUM_DSC_CRDT_SENT_RSVD_1", - STAT_NUM_DSC_CRDT_SENT_RSVD_1_MASK}, - {"STAT_NUM_DSC_CRDT_SENT_CNT", - STAT_NUM_DSC_CRDT_SENT_CNT_MASK}, -}; - - -static struct regfield_info - stat_num_fch_dsc_rcvd_field_info[] = { - {"STAT_NUM_FCH_DSC_RCVD_RSVD_1", - STAT_NUM_FCH_DSC_RCVD_RSVD_1_MASK}, - {"STAT_NUM_FCH_DSC_RCVD_DSC_CNT", - STAT_NUM_FCH_DSC_RCVD_DSC_CNT_MASK}, -}; - - -static struct regfield_info - stat_num_byp_dsc_rcvd_field_info[] = { - {"STAT_NUM_BYP_DSC_RCVD_RSVD_1", - STAT_NUM_BYP_DSC_RCVD_RSVD_1_MASK}, - {"STAT_NUM_BYP_DSC_RCVD_DSC_CNT", - STAT_NUM_BYP_DSC_RCVD_DSC_CNT_MASK}, -}; - - -static struct regfield_info - c2h_wrb_coal_cfg_field_info[] = { - {"C2H_WRB_COAL_CFG_MAX_BUF_SZ", - C2H_WRB_COAL_CFG_MAX_BUF_SZ_MASK}, - {"C2H_WRB_COAL_CFG_TICK_VAL", - C2H_WRB_COAL_CFG_TICK_VAL_MASK}, - {"C2H_WRB_COAL_CFG_TICK_CNT", - C2H_WRB_COAL_CFG_TICK_CNT_MASK}, - {"C2H_WRB_COAL_CFG_SET_GLB_FLUSH", - C2H_WRB_COAL_CFG_SET_GLB_FLUSH_MASK}, - {"C2H_WRB_COAL_CFG_DONE_GLB_FLUSH", - C2H_WRB_COAL_CFG_DONE_GLB_FLUSH_MASK}, -}; - - -static struct regfield_info - c2h_intr_h2c_req_field_info[] = { - {"C2H_INTR_H2C_REQ_RSVD_1", - C2H_INTR_H2C_REQ_RSVD_1_MASK}, - {"C2H_INTR_H2C_REQ_CNT", - C2H_INTR_H2C_REQ_CNT_MASK}, -}; - - -static struct regfield_info - c2h_intr_c2h_mm_req_field_info[] = { - {"C2H_INTR_C2H_MM_REQ_RSVD_1", - C2H_INTR_C2H_MM_REQ_RSVD_1_MASK}, - {"C2H_INTR_C2H_MM_REQ_CNT", - C2H_INTR_C2H_MM_REQ_CNT_MASK}, -}; - - -static struct regfield_info - c2h_intr_err_int_req_field_info[] = { - {"C2H_INTR_ERR_INT_REQ_RSVD_1", - C2H_INTR_ERR_INT_REQ_RSVD_1_MASK}, - {"C2H_INTR_ERR_INT_REQ_CNT", - C2H_INTR_ERR_INT_REQ_CNT_MASK}, -}; - - -static struct regfield_info - c2h_intr_c2h_st_req_field_info[] = { - {"C2H_INTR_C2H_ST_REQ_RSVD_1", - C2H_INTR_C2H_ST_REQ_RSVD_1_MASK}, - {"C2H_INTR_C2H_ST_REQ_CNT", - C2H_INTR_C2H_ST_REQ_CNT_MASK}, -}; - - -static struct regfield_info - c2h_intr_h2c_err_c2h_mm_msix_ack_field_info[] = { - {"C2H_INTR_H2C_ERR_C2H_MM_MSIX_ACK_RSVD_1", - C2H_INTR_H2C_ERR_C2H_MM_MSIX_ACK_RSVD_1_MASK}, - {"C2H_INTR_H2C_ERR_C2H_MM_MSIX_ACK_CNT", - C2H_INTR_H2C_ERR_C2H_MM_MSIX_ACK_CNT_MASK}, -}; - - -static struct regfield_info - c2h_intr_h2c_err_c2h_mm_msix_fail_field_info[] = { - {"C2H_INTR_H2C_ERR_C2H_MM_MSIX_FAIL_RSVD_1", - C2H_INTR_H2C_ERR_C2H_MM_MSIX_FAIL_RSVD_1_MASK}, - {"C2H_INTR_H2C_ERR_C2H_MM_MSIX_FAIL_CNT", - C2H_INTR_H2C_ERR_C2H_MM_MSIX_FAIL_CNT_MASK}, -}; - - -static struct regfield_info - c2h_intr_h2c_err_c2h_mm_msix_no_msix_field_info[] = { - {"C2H_INTR_H2C_ERR_C2H_MM_MSIX_NO_MSIX_RSVD_1", - C2H_INTR_H2C_ERR_C2H_MM_MSIX_NO_MSIX_RSVD_1_MASK}, - {"C2H_INTR_H2C_ERR_C2H_MM_MSIX_NO_MSIX_CNT", - C2H_INTR_H2C_ERR_C2H_MM_MSIX_NO_MSIX_CNT_MASK}, -}; - - -static struct regfield_info - c2h_intr_h2c_err_c2h_mm_ctxt_inval_field_info[] = { - {"C2H_INTR_H2C_ERR_C2H_MM_CTXT_INVAL_RSVD_1", - C2H_INTR_H2C_ERR_C2H_MM_CTXT_INVAL_RSVD_1_MASK}, - {"C2H_INTR_H2C_ERR_C2H_MM_CTXT_INVAL_CNT", - C2H_INTR_H2C_ERR_C2H_MM_CTXT_INVAL_CNT_MASK}, -}; - - -static struct regfield_info - c2h_intr_c2h_st_msix_ack_field_info[] = { - {"C2H_INTR_C2H_ST_MSIX_ACK_RSVD_1", - C2H_INTR_C2H_ST_MSIX_ACK_RSVD_1_MASK}, - {"C2H_INTR_C2H_ST_MSIX_ACK_CNT", - C2H_INTR_C2H_ST_MSIX_ACK_CNT_MASK}, -}; - - -static struct regfield_info - c2h_intr_c2h_st_msix_fail_field_info[] = { - {"C2H_INTR_C2H_ST_MSIX_FAIL_RSVD_1", - C2H_INTR_C2H_ST_MSIX_FAIL_RSVD_1_MASK}, - {"C2H_INTR_C2H_ST_MSIX_FAIL_CNT", - C2H_INTR_C2H_ST_MSIX_FAIL_CNT_MASK}, -}; - - -static struct regfield_info - c2h_intr_c2h_st_no_msix_field_info[] = { - {"C2H_INTR_C2H_ST_NO_MSIX_RSVD_1", - C2H_INTR_C2H_ST_NO_MSIX_RSVD_1_MASK}, - {"C2H_INTR_C2H_ST_NO_MSIX_CNT", - C2H_INTR_C2H_ST_NO_MSIX_CNT_MASK}, -}; - - -static struct regfield_info - c2h_intr_c2h_st_ctxt_inval_field_info[] = { - {"C2H_INTR_C2H_ST_CTXT_INVAL_RSVD_1", - C2H_INTR_C2H_ST_CTXT_INVAL_RSVD_1_MASK}, - {"C2H_INTR_C2H_ST_CTXT_INVAL_CNT", - C2H_INTR_C2H_ST_CTXT_INVAL_CNT_MASK}, -}; - - -static struct regfield_info - c2h_stat_wr_cmp_field_info[] = { - {"C2H_STAT_WR_CMP_RSVD_1", - C2H_STAT_WR_CMP_RSVD_1_MASK}, - {"C2H_STAT_WR_CMP_CNT", - C2H_STAT_WR_CMP_CNT_MASK}, -}; - - -static struct regfield_info - c2h_stat_dbg_dma_eng_4_field_info[] = { - {"C2H_STAT_DMA_ENG_4_QID_FIFO_OUT_DAT_HAS_CMPT_1", - C2H_STAT_DMA_ENG_4_QID_FIFO_OUT_DAT_HAS_CMPT_1_MASK}, - {"C2H_STAT_DMA_ENG_4_QID_FIFO_OUT_DAT_MARKER_1", - C2H_STAT_DMA_ENG_4_QID_FIFO_OUT_DAT_MARKER_1_MASK}, - {"C2H_STAT_DMA_ENG_4_QID_FIFO_OUT_DAT_DROP_REQ_1", - C2H_STAT_DMA_ENG_4_QID_FIFO_OUT_DAT_DROP_REQ_1_MASK}, - {"C2H_STAT_DMA_ENG_4_QID_FIFO_OUT_DAT_QID_1", - C2H_STAT_DMA_ENG_4_QID_FIFO_OUT_DAT_QID_1_MASK}, - {"C2H_STAT_DMA_ENG_4_WR_HDR_FIFO_OUT_CNT_1", - C2H_STAT_DMA_ENG_4_WR_HDR_FIFO_OUT_CNT_1_MASK}, - {"C2H_STAT_DMA_ENG_4_QID_FIFO_OUT_VLD_1", - C2H_STAT_DMA_ENG_4_QID_FIFO_OUT_VLD_1_MASK}, - {"C2H_STAT_DMA_ENG_4_PLD_FIFO_OUT_VLD_1", - C2H_STAT_DMA_ENG_4_PLD_FIFO_OUT_VLD_1_MASK}, - {"C2H_STAT_DMA_ENG_4_PLD_ST_FIFO_OUT_VLD_1", - C2H_STAT_DMA_ENG_4_PLD_ST_FIFO_OUT_VLD_1_MASK}, - {"C2H_STAT_DMA_ENG_4_PLD_ST_FIFO_OUT_DATA_EOP_1", - C2H_STAT_DMA_ENG_4_PLD_ST_FIFO_OUT_DATA_EOP_1_MASK}, - {"C2H_STAT_DMA_ENG_4_PLD_ST_FIFO_OUT_DATA_AVL_IDX_ENABLE_1", - C2H_STAT_DMA_ENG_4_PLD_ST_FIFO_OUT_DATA_AVL_IDX_ENABLE_1_MASK}, - {"C2H_STAT_DMA_ENG_4_PLD_ST_FIFO_OUT_DATA_DROP_1", - C2H_STAT_DMA_ENG_4_PLD_ST_FIFO_OUT_DATA_DROP_1_MASK}, - {"C2H_STAT_DMA_ENG_4_PLD_ST_FIFO_OUT_DATA_ERR_1", - C2H_STAT_DMA_ENG_4_PLD_ST_FIFO_OUT_DATA_ERR_1_MASK}, - {"C2H_STAT_DMA_ENG_4_DESC_CNT_FIFO_IN_RDY_1", - C2H_STAT_DMA_ENG_4_DESC_CNT_FIFO_IN_RDY_1_MASK}, - {"C2H_STAT_DMA_ENG_4_DESC_RSP_FIFO_IN_RDY_1", - C2H_STAT_DMA_ENG_4_DESC_RSP_FIFO_IN_RDY_1_MASK}, - {"C2H_STAT_DMA_ENG_4_PLD_PKT_ID_LARGER_1", - C2H_STAT_DMA_ENG_4_PLD_PKT_ID_LARGER_1_MASK}, - {"C2H_STAT_DMA_ENG_4_WCP_FIFO_IN_RDY_1", - C2H_STAT_DMA_ENG_4_WCP_FIFO_IN_RDY_1_MASK}, - {"C2H_STAT_DMA_ENG_4_PLD_ST_FIFO_IN_RDY_1", - C2H_STAT_DMA_ENG_4_PLD_ST_FIFO_IN_RDY_1_MASK}, -}; - - -static struct regfield_info - c2h_stat_dbg_dma_eng_5_field_info[] = { - {"C2H_STAT_DMA_ENG_5_ARB_FIFO_IN_RDY", - C2H_STAT_DMA_ENG_5_ARB_FIFO_IN_RDY_MASK}, - {"C2H_STAT_DMA_ENG_5_WRB_SM_VIRT_CH", - C2H_STAT_DMA_ENG_5_WRB_SM_VIRT_CH_MASK}, - {"C2H_STAT_DMA_ENG_5_WRB_FIFO_IN_REQ", - C2H_STAT_DMA_ENG_5_WRB_FIFO_IN_REQ_MASK}, - {"C2H_STAT_DMA_ENG_5_ARB_FIFO_OUT_CNT", - C2H_STAT_DMA_ENG_5_ARB_FIFO_OUT_CNT_MASK}, - {"C2H_STAT_DMA_ENG_5_ARB_FIFO_OUT_DATA_LEN", - C2H_STAT_DMA_ENG_5_ARB_FIFO_OUT_DATA_LEN_MASK}, - {"C2H_STAT_DMA_ENG_5_ARB_FIFO_OUT_DATA_VIRT_CH", - C2H_STAT_DMA_ENG_5_ARB_FIFO_OUT_DATA_VIRT_CH_MASK}, - {"C2H_STAT_DMA_ENG_5_ARB_FIFO_OUT_DATA_VAR_DESC", - C2H_STAT_DMA_ENG_5_ARB_FIFO_OUT_DATA_VAR_DESC_MASK}, - {"C2H_STAT_DMA_ENG_5_ARB_FIFO_OUT_DATA_DROP_REQ", - C2H_STAT_DMA_ENG_5_ARB_FIFO_OUT_DATA_DROP_REQ_MASK}, - {"C2H_STAT_DMA_ENG_5_ARB_FIFO_OUT_DATA_NUM_BUF_OV", - C2H_STAT_DMA_ENG_5_ARB_FIFO_OUT_DATA_NUM_BUF_OV_MASK}, - {"C2H_STAT_DMA_ENG_5_ARB_FIFO_OUT_DATA_MARKER", - C2H_STAT_DMA_ENG_5_ARB_FIFO_OUT_DATA_MARKER_MASK}, - {"C2H_STAT_DMA_ENG_5_ARB_FIFO_OUT_DATA_HAS_CMPT", - C2H_STAT_DMA_ENG_5_ARB_FIFO_OUT_DATA_HAS_CMPT_MASK}, -}; - - -static struct regfield_info - c2h_dbg_pfch_qid_field_info[] = { - {"C2H_PFCH_QID_RSVD_1", - C2H_PFCH_QID_RSVD_1_MASK}, - {"C2H_PFCH_QID_ERR_CTXT", - C2H_PFCH_QID_ERR_CTXT_MASK}, - {"C2H_PFCH_QID_TARGET", - C2H_PFCH_QID_TARGET_MASK}, - {"C2H_PFCH_QID_QID_OR_TAG", - C2H_PFCH_QID_QID_OR_TAG_MASK}, -}; - - -static struct regfield_info - c2h_dbg_pfch_field_info[] = { - {"C2H_PFCH_DATA", - C2H_PFCH_DATA_MASK}, -}; - - -static struct regfield_info - c2h_int_dbg_field_info[] = { - {"C2H_INT_RSVD_1", - C2H_INT_RSVD_1_MASK}, - {"C2H_INT_INT_COAL_SM", - C2H_INT_INT_COAL_SM_MASK}, - {"C2H_INT_INT_SM", - C2H_INT_INT_SM_MASK}, -}; - - -static struct regfield_info - c2h_stat_imm_accepted_field_info[] = { - {"C2H_STAT_IMM_ACCEPTED_RSVD_1", - C2H_STAT_IMM_ACCEPTED_RSVD_1_MASK}, - {"C2H_STAT_IMM_ACCEPTED_CNT", - C2H_STAT_IMM_ACCEPTED_CNT_MASK}, -}; - - -static struct regfield_info - c2h_stat_marker_accepted_field_info[] = { - {"C2H_STAT_MARKER_ACCEPTED_RSVD_1", - C2H_STAT_MARKER_ACCEPTED_RSVD_1_MASK}, - {"C2H_STAT_MARKER_ACCEPTED_CNT", - C2H_STAT_MARKER_ACCEPTED_CNT_MASK}, -}; - - -static struct regfield_info - c2h_stat_disable_cmp_accepted_field_info[] = { - {"C2H_STAT_DISABLE_CMP_ACCEPTED_RSVD_1", - C2H_STAT_DISABLE_CMP_ACCEPTED_RSVD_1_MASK}, - {"C2H_STAT_DISABLE_CMP_ACCEPTED_CNT", - C2H_STAT_DISABLE_CMP_ACCEPTED_CNT_MASK}, -}; - - -static struct regfield_info - c2h_pld_fifo_crdt_cnt_field_info[] = { - {"C2H_PLD_FIFO_CRDT_CNT_RSVD_1", - C2H_PLD_FIFO_CRDT_CNT_RSVD_1_MASK}, - {"C2H_PLD_FIFO_CRDT_CNT_CNT", - C2H_PLD_FIFO_CRDT_CNT_CNT_MASK}, -}; - - -static struct regfield_info - c2h_intr_dyn_req_field_info[] = { - {"C2H_INTR_DYN_REQ_RSVD_1", - C2H_INTR_DYN_REQ_RSVD_1_MASK}, - {"C2H_INTR_DYN_REQ_CNT", - C2H_INTR_DYN_REQ_CNT_MASK}, -}; - - -static struct regfield_info - c2h_intr_dyn_misc_field_info[] = { - {"C2H_INTR_DYN_MISC_RSVD_1", - C2H_INTR_DYN_MISC_RSVD_1_MASK}, - {"C2H_INTR_DYN_MISC_CNT", - C2H_INTR_DYN_MISC_CNT_MASK}, -}; - - -static struct regfield_info - c2h_drop_len_mismatch_field_info[] = { - {"C2H_DROP_LEN_MISMATCH_RSVD_1", - C2H_DROP_LEN_MISMATCH_RSVD_1_MASK}, - {"C2H_DROP_LEN_MISMATCH_CNT", - C2H_DROP_LEN_MISMATCH_CNT_MASK}, -}; - - -static struct regfield_info - c2h_drop_desc_rsp_len_field_info[] = { - {"C2H_DROP_DESC_RSP_LEN_RSVD_1", - C2H_DROP_DESC_RSP_LEN_RSVD_1_MASK}, - {"C2H_DROP_DESC_RSP_LEN_CNT", - C2H_DROP_DESC_RSP_LEN_CNT_MASK}, -}; - - -static struct regfield_info - c2h_drop_qid_fifo_len_field_info[] = { - {"C2H_DROP_QID_FIFO_LEN_RSVD_1", - C2H_DROP_QID_FIFO_LEN_RSVD_1_MASK}, - {"C2H_DROP_QID_FIFO_LEN_CNT", - C2H_DROP_QID_FIFO_LEN_CNT_MASK}, -}; - - -static struct regfield_info - c2h_drop_pld_cnt_field_info[] = { - {"C2H_DROP_PLD_CNT_RSVD_1", - C2H_DROP_PLD_CNT_RSVD_1_MASK}, - {"C2H_DROP_PLD_CNT_CNT", - C2H_DROP_PLD_CNT_CNT_MASK}, -}; - - -static struct regfield_info - c2h_cmpt_format_0_field_info[] = { - {"C2H_CMPT_FORMAT_0_DESC_ERR_LOC", - C2H_CMPT_FORMAT_0_DESC_ERR_LOC_MASK}, - {"C2H_CMPT_FORMAT_0_COLOR_LOC", - C2H_CMPT_FORMAT_0_COLOR_LOC_MASK}, -}; - - -static struct regfield_info - c2h_cmpt_format_1_field_info[] = { - {"C2H_CMPT_FORMAT_1_DESC_ERR_LOC", - C2H_CMPT_FORMAT_1_DESC_ERR_LOC_MASK}, - {"C2H_CMPT_FORMAT_1_COLOR_LOC", - C2H_CMPT_FORMAT_1_COLOR_LOC_MASK}, -}; - - -static struct regfield_info - c2h_cmpt_format_2_field_info[] = { - {"C2H_CMPT_FORMAT_2_DESC_ERR_LOC", - C2H_CMPT_FORMAT_2_DESC_ERR_LOC_MASK}, - {"C2H_CMPT_FORMAT_2_COLOR_LOC", - C2H_CMPT_FORMAT_2_COLOR_LOC_MASK}, -}; - - -static struct regfield_info - c2h_cmpt_format_3_field_info[] = { - {"C2H_CMPT_FORMAT_3_DESC_ERR_LOC", - C2H_CMPT_FORMAT_3_DESC_ERR_LOC_MASK}, - {"C2H_CMPT_FORMAT_3_COLOR_LOC", - C2H_CMPT_FORMAT_3_COLOR_LOC_MASK}, -}; - - -static struct regfield_info - c2h_cmpt_format_4_field_info[] = { - {"C2H_CMPT_FORMAT_4_DESC_ERR_LOC", - C2H_CMPT_FORMAT_4_DESC_ERR_LOC_MASK}, - {"C2H_CMPT_FORMAT_4_COLOR_LOC", - C2H_CMPT_FORMAT_4_COLOR_LOC_MASK}, -}; - - -static struct regfield_info - c2h_cmpt_format_5_field_info[] = { - {"C2H_CMPT_FORMAT_5_DESC_ERR_LOC", - C2H_CMPT_FORMAT_5_DESC_ERR_LOC_MASK}, - {"C2H_CMPT_FORMAT_5_COLOR_LOC", - C2H_CMPT_FORMAT_5_COLOR_LOC_MASK}, -}; - - -static struct regfield_info - c2h_cmpt_format_6_field_info[] = { - {"C2H_CMPT_FORMAT_6_DESC_ERR_LOC", - C2H_CMPT_FORMAT_6_DESC_ERR_LOC_MASK}, - {"C2H_CMPT_FORMAT_6_COLOR_LOC", - C2H_CMPT_FORMAT_6_COLOR_LOC_MASK}, -}; - - -static struct regfield_info - c2h_pfch_cache_depth_field_info[] = { - {"C2H_PFCH_CACHE_DEPTH_MAX_STBUF", - C2H_PFCH_CACHE_DEPTH_MAX_STBUF_MASK}, - {"C2H_PFCH_CACHE_DEPTH", - C2H_PFCH_CACHE_DEPTH_MASK}, -}; - - -static struct regfield_info - c2h_wrb_coal_buf_depth_field_info[] = { - {"C2H_WRB_COAL_BUF_DEPTH_RSVD_1", - C2H_WRB_COAL_BUF_DEPTH_RSVD_1_MASK}, - {"C2H_WRB_COAL_BUF_DEPTH_BUFFER", - C2H_WRB_COAL_BUF_DEPTH_BUFFER_MASK}, -}; - - -static struct regfield_info - c2h_pfch_crdt_field_info[] = { - {"C2H_PFCH_CRDT_RSVD_1", - C2H_PFCH_CRDT_RSVD_1_MASK}, - {"C2H_PFCH_CRDT_RSVD_2", - C2H_PFCH_CRDT_RSVD_2_MASK}, -}; - - -static struct regfield_info - c2h_stat_has_cmpt_accepted_field_info[] = { - {"C2H_STAT_HAS_CMPT_ACCEPTED_RSVD_1", - C2H_STAT_HAS_CMPT_ACCEPTED_RSVD_1_MASK}, - {"C2H_STAT_HAS_CMPT_ACCEPTED_CNT", - C2H_STAT_HAS_CMPT_ACCEPTED_CNT_MASK}, -}; - - -static struct regfield_info - c2h_stat_has_pld_accepted_field_info[] = { - {"C2H_STAT_HAS_PLD_ACCEPTED_RSVD_1", - C2H_STAT_HAS_PLD_ACCEPTED_RSVD_1_MASK}, - {"C2H_STAT_HAS_PLD_ACCEPTED_CNT", - C2H_STAT_HAS_PLD_ACCEPTED_CNT_MASK}, -}; - - -static struct regfield_info - c2h_pld_pkt_id_field_info[] = { - {"C2H_PLD_PKT_ID_CMPT_WAIT", - C2H_PLD_PKT_ID_CMPT_WAIT_MASK}, - {"C2H_PLD_PKT_ID_DATA", - C2H_PLD_PKT_ID_DATA_MASK}, -}; - - -static struct regfield_info - c2h_pld_pkt_id_1_field_info[] = { - {"C2H_PLD_PKT_ID_1_CMPT_WAIT", - C2H_PLD_PKT_ID_1_CMPT_WAIT_MASK}, - {"C2H_PLD_PKT_ID_1_DATA", - C2H_PLD_PKT_ID_1_DATA_MASK}, -}; - - -static struct regfield_info - c2h_drop_pld_cnt_1_field_info[] = { - {"C2H_DROP_PLD_CNT_1_RSVD_1", - C2H_DROP_PLD_CNT_1_RSVD_1_MASK}, - {"C2H_DROP_PLD_CNT_1_CNT", - C2H_DROP_PLD_CNT_1_CNT_MASK}, -}; - - -static struct regfield_info - h2c_err_stat_field_info[] = { - {"H2C_ERR_STAT_RSVD_1", - H2C_ERR_STAT_RSVD_1_MASK}, - {"H2C_ERR_STAT_PAR_ERR", - H2C_ERR_STAT_PAR_ERR_MASK}, - {"H2C_ERR_STAT_SBE", - H2C_ERR_STAT_SBE_MASK}, - {"H2C_ERR_STAT_DBE", - H2C_ERR_STAT_DBE_MASK}, - {"H2C_ERR_STAT_NO_DMA_DS", - H2C_ERR_STAT_NO_DMA_DS_MASK}, - {"H2C_ERR_STAT_SDI_MRKR_REQ_MOP_ERR", - H2C_ERR_STAT_SDI_MRKR_REQ_MOP_ERR_MASK}, - {"H2C_ERR_STAT_ZERO_LEN_DS", - H2C_ERR_STAT_ZERO_LEN_DS_MASK}, -}; - - -static struct regfield_info - h2c_err_mask_field_info[] = { - {"H2C_ERR_EN", - H2C_ERR_EN_MASK}, -}; - - -static struct regfield_info - h2c_first_err_qid_field_info[] = { - {"H2C_FIRST_ERR_QID_RSVD_1", - H2C_FIRST_ERR_QID_RSVD_1_MASK}, - {"H2C_FIRST_ERR_QID_ERR_TYPE", - H2C_FIRST_ERR_QID_ERR_TYPE_MASK}, - {"H2C_FIRST_ERR_QID_RSVD_2", - H2C_FIRST_ERR_QID_RSVD_2_MASK}, - {"H2C_FIRST_ERR_QID_QID", - H2C_FIRST_ERR_QID_QID_MASK}, -}; - - -static struct regfield_info - h2c_dbg_reg0_field_info[] = { - {"H2C_REG0_NUM_DSC_RCVD", - H2C_REG0_NUM_DSC_RCVD_MASK}, - {"H2C_REG0_NUM_WRB_SENT", - H2C_REG0_NUM_WRB_SENT_MASK}, -}; - - -static struct regfield_info - h2c_dbg_reg1_field_info[] = { - {"H2C_REG1_NUM_REQ_SENT", - H2C_REG1_NUM_REQ_SENT_MASK}, - {"H2C_REG1_NUM_CMP_SENT", - H2C_REG1_NUM_CMP_SENT_MASK}, -}; - - -static struct regfield_info - h2c_dbg_reg2_field_info[] = { - {"H2C_REG2_RSVD_1", - H2C_REG2_RSVD_1_MASK}, - {"H2C_REG2_NUM_ERR_DSC_RCVD", - H2C_REG2_NUM_ERR_DSC_RCVD_MASK}, -}; - - -static struct regfield_info - h2c_dbg_reg3_field_info[] = { - {"H2C_REG3_RSVD_1", - H2C_REG3_RSVD_1_MASK}, - {"H2C_REG3_DSCO_FIFO_EMPTY", - H2C_REG3_DSCO_FIFO_EMPTY_MASK}, - {"H2C_REG3_DSCO_FIFO_FULL", - H2C_REG3_DSCO_FIFO_FULL_MASK}, - {"H2C_REG3_CUR_RC_STATE", - H2C_REG3_CUR_RC_STATE_MASK}, - {"H2C_REG3_RDREQ_LINES", - H2C_REG3_RDREQ_LINES_MASK}, - {"H2C_REG3_RDATA_LINES_AVAIL", - H2C_REG3_RDATA_LINES_AVAIL_MASK}, - {"H2C_REG3_PEND_FIFO_EMPTY", - H2C_REG3_PEND_FIFO_EMPTY_MASK}, - {"H2C_REG3_PEND_FIFO_FULL", - H2C_REG3_PEND_FIFO_FULL_MASK}, - {"H2C_REG3_CUR_RQ_STATE", - H2C_REG3_CUR_RQ_STATE_MASK}, - {"H2C_REG3_DSCI_FIFO_FULL", - H2C_REG3_DSCI_FIFO_FULL_MASK}, - {"H2C_REG3_DSCI_FIFO_EMPTY", - H2C_REG3_DSCI_FIFO_EMPTY_MASK}, -}; - - -static struct regfield_info - h2c_dbg_reg4_field_info[] = { - {"H2C_REG4_RDREQ_ADDR", - H2C_REG4_RDREQ_ADDR_MASK}, -}; - - -static struct regfield_info - h2c_fatal_err_en_field_info[] = { - {"H2C_FATAL_ERR_EN_RSVD_1", - H2C_FATAL_ERR_EN_RSVD_1_MASK}, - {"H2C_FATAL_ERR_EN_H2C", - H2C_FATAL_ERR_EN_H2C_MASK}, -}; - - -static struct regfield_info - h2c_req_throt_pcie_field_info[] = { - {"H2C_REQ_THROT_PCIE_EN_REQ", - H2C_REQ_THROT_PCIE_EN_REQ_MASK}, - {"H2C_REQ_THROT_PCIE", - H2C_REQ_THROT_PCIE_MASK}, - {"H2C_REQ_THROT_PCIE_EN_DATA", - H2C_REQ_THROT_PCIE_EN_DATA_MASK}, - {"H2C_REQ_THROT_PCIE_DATA_THRESH", - H2C_REQ_THROT_PCIE_DATA_THRESH_MASK}, -}; - - -static struct regfield_info - h2c_aln_dbg_reg0_field_info[] = { - {"H2C_ALN_REG0_NUM_PKT_SENT", - H2C_ALN_REG0_NUM_PKT_SENT_MASK}, -}; - - -static struct regfield_info - h2c_req_throt_aximm_field_info[] = { - {"H2C_REQ_THROT_AXIMM_EN_REQ", - H2C_REQ_THROT_AXIMM_EN_REQ_MASK}, - {"H2C_REQ_THROT_AXIMM", - H2C_REQ_THROT_AXIMM_MASK}, - {"H2C_REQ_THROT_AXIMM_EN_DATA", - H2C_REQ_THROT_AXIMM_EN_DATA_MASK}, - {"H2C_REQ_THROT_AXIMM_DATA_THRESH", - H2C_REQ_THROT_AXIMM_DATA_THRESH_MASK}, -}; - - -static struct regfield_info - c2h_mm_ctl_field_info[] = { - {"C2H_MM_CTL_RESERVED1", - C2H_MM_CTL_RESERVED1_MASK}, - {"C2H_MM_CTL_ERRC_EN", - C2H_MM_CTL_ERRC_EN_MASK}, - {"C2H_MM_CTL_RESERVED0", - C2H_MM_CTL_RESERVED0_MASK}, - {"C2H_MM_CTL_RUN", - C2H_MM_CTL_RUN_MASK}, -}; - - -static struct regfield_info - c2h_mm_status_field_info[] = { - {"C2H_MM_STATUS_RSVD_1", - C2H_MM_STATUS_RSVD_1_MASK}, - {"C2H_MM_STATUS_RUN", - C2H_MM_STATUS_RUN_MASK}, -}; - - -static struct regfield_info - c2h_mm_cmpl_desc_cnt_field_info[] = { - {"C2H_MM_CMPL_DESC_CNT_C2H_CO", - C2H_MM_CMPL_DESC_CNT_C2H_CO_MASK}, -}; - - -static struct regfield_info - c2h_mm_err_code_enable_mask_field_info[] = { - {"C2H_MM_ERR_CODE_ENABLE_RESERVED1", - C2H_MM_ERR_CODE_ENABLE_RESERVED1_MASK}, - {"C2H_MM_ERR_CODE_ENABLE_WR_UC_RAM", - C2H_MM_ERR_CODE_ENABLE_WR_UC_RAM_MASK}, - {"C2H_MM_ERR_CODE_ENABLE_WR_UR", - C2H_MM_ERR_CODE_ENABLE_WR_UR_MASK}, - {"C2H_MM_ERR_CODE_ENABLE_WR_FLR", - C2H_MM_ERR_CODE_ENABLE_WR_FLR_MASK}, - {"C2H_MM_ERR_CODE_ENABLE_RESERVED0", - C2H_MM_ERR_CODE_ENABLE_RESERVED0_MASK}, - {"C2H_MM_ERR_CODE_ENABLE_RD_SLV_ERR", - C2H_MM_ERR_CODE_ENABLE_RD_SLV_ERR_MASK}, - {"C2H_MM_ERR_CODE_ENABLE_WR_SLV_ERR", - C2H_MM_ERR_CODE_ENABLE_WR_SLV_ERR_MASK}, -}; - - -static struct regfield_info - c2h_mm_err_code_field_info[] = { - {"C2H_MM_ERR_CODE_RESERVED1", - C2H_MM_ERR_CODE_RESERVED1_MASK}, - {"C2H_MM_ERR_CODE_CIDX", - C2H_MM_ERR_CODE_CIDX_MASK}, - {"C2H_MM_ERR_CODE_RESERVED0", - C2H_MM_ERR_CODE_RESERVED0_MASK}, - {"C2H_MM_ERR_CODE_SUB_TYPE", - C2H_MM_ERR_CODE_SUB_TYPE_MASK}, - {"C2H_MM_ERR_CODE", - C2H_MM_ERR_CODE_MASK}, -}; - - -static struct regfield_info - c2h_mm_err_info_field_info[] = { - {"C2H_MM_ERR_INFO_VALID", - C2H_MM_ERR_INFO_VALID_MASK}, - {"C2H_MM_ERR_INFO_SEL", - C2H_MM_ERR_INFO_SEL_MASK}, - {"C2H_MM_ERR_INFO_RSVD_1", - C2H_MM_ERR_INFO_RSVD_1_MASK}, - {"C2H_MM_ERR_INFO_QID", - C2H_MM_ERR_INFO_QID_MASK}, -}; - - -static struct regfield_info - c2h_mm_perf_mon_ctl_field_info[] = { - {"C2H_MM_PERF_MON_CTL_RSVD_1", - C2H_MM_PERF_MON_CTL_RSVD_1_MASK}, - {"C2H_MM_PERF_MON_CTL_IMM_START", - C2H_MM_PERF_MON_CTL_IMM_START_MASK}, - {"C2H_MM_PERF_MON_CTL_RUN_START", - C2H_MM_PERF_MON_CTL_RUN_START_MASK}, - {"C2H_MM_PERF_MON_CTL_IMM_CLEAR", - C2H_MM_PERF_MON_CTL_IMM_CLEAR_MASK}, - {"C2H_MM_PERF_MON_CTL_RUN_CLEAR", - C2H_MM_PERF_MON_CTL_RUN_CLEAR_MASK}, -}; - - -static struct regfield_info - c2h_mm_perf_mon_cycle_cnt0_field_info[] = { - {"C2H_MM_PERF_MON_CYCLE_CNT0_CYC_CNT", - C2H_MM_PERF_MON_CYCLE_CNT0_CYC_CNT_MASK}, -}; - - -static struct regfield_info - c2h_mm_perf_mon_cycle_cnt1_field_info[] = { - {"C2H_MM_PERF_MON_CYCLE_CNT1_RSVD_1", - C2H_MM_PERF_MON_CYCLE_CNT1_RSVD_1_MASK}, - {"C2H_MM_PERF_MON_CYCLE_CNT1_CYC_CNT", - C2H_MM_PERF_MON_CYCLE_CNT1_CYC_CNT_MASK}, -}; - - -static struct regfield_info - c2h_mm_perf_mon_data_cnt0_field_info[] = { - {"C2H_MM_PERF_MON_DATA_CNT0_DCNT", - C2H_MM_PERF_MON_DATA_CNT0_DCNT_MASK}, -}; - - -static struct regfield_info - c2h_mm_perf_mon_data_cnt1_field_info[] = { - {"C2H_MM_PERF_MON_DATA_CNT1_RSVD_1", - C2H_MM_PERF_MON_DATA_CNT1_RSVD_1_MASK}, - {"C2H_MM_PERF_MON_DATA_CNT1_DCNT", - C2H_MM_PERF_MON_DATA_CNT1_DCNT_MASK}, -}; - - -static struct regfield_info - c2h_mm_dbg_field_info[] = { - {"C2H_MM_RSVD_1", - C2H_MM_RSVD_1_MASK}, - {"C2H_MM_RRQ_ENTRIES", - C2H_MM_RRQ_ENTRIES_MASK}, - {"C2H_MM_DAT_FIFO_SPC", - C2H_MM_DAT_FIFO_SPC_MASK}, - {"C2H_MM_RD_STALL", - C2H_MM_RD_STALL_MASK}, - {"C2H_MM_RRQ_FIFO_FI", - C2H_MM_RRQ_FIFO_FI_MASK}, - {"C2H_MM_WR_STALL", - C2H_MM_WR_STALL_MASK}, - {"C2H_MM_WRQ_FIFO_FI", - C2H_MM_WRQ_FIFO_FI_MASK}, - {"C2H_MM_WBK_STALL", - C2H_MM_WBK_STALL_MASK}, - {"C2H_MM_DSC_FIFO_EP", - C2H_MM_DSC_FIFO_EP_MASK}, - {"C2H_MM_DSC_FIFO_FL", - C2H_MM_DSC_FIFO_FL_MASK}, -}; - - -static struct regfield_info - h2c_mm_ctl_field_info[] = { - {"H2C_MM_CTL_RESERVED1", - H2C_MM_CTL_RESERVED1_MASK}, - {"H2C_MM_CTL_ERRC_EN", - H2C_MM_CTL_ERRC_EN_MASK}, - {"H2C_MM_CTL_RESERVED0", - H2C_MM_CTL_RESERVED0_MASK}, - {"H2C_MM_CTL_RUN", - H2C_MM_CTL_RUN_MASK}, -}; - - -static struct regfield_info - h2c_mm_status_field_info[] = { - {"H2C_MM_STATUS_RSVD_1", - H2C_MM_STATUS_RSVD_1_MASK}, - {"H2C_MM_STATUS_RUN", - H2C_MM_STATUS_RUN_MASK}, -}; - - -static struct regfield_info - h2c_mm_cmpl_desc_cnt_field_info[] = { - {"H2C_MM_CMPL_DESC_CNT_H2C_CO", - H2C_MM_CMPL_DESC_CNT_H2C_CO_MASK}, -}; - - -static struct regfield_info - h2c_mm_err_code_enable_mask_field_info[] = { - {"H2C_MM_ERR_CODE_ENABLE_RESERVED5", - H2C_MM_ERR_CODE_ENABLE_RESERVED5_MASK}, - {"H2C_MM_ERR_CODE_ENABLE_WR_SLV_ERR", - H2C_MM_ERR_CODE_ENABLE_WR_SLV_ERR_MASK}, - {"H2C_MM_ERR_CODE_ENABLE_WR_DEC_ERR", - H2C_MM_ERR_CODE_ENABLE_WR_DEC_ERR_MASK}, - {"H2C_MM_ERR_CODE_ENABLE_RESERVED4", - H2C_MM_ERR_CODE_ENABLE_RESERVED4_MASK}, - {"H2C_MM_ERR_CODE_ENABLE_RD_RQ_DIS_ERR", - H2C_MM_ERR_CODE_ENABLE_RD_RQ_DIS_ERR_MASK}, - {"H2C_MM_ERR_CODE_ENABLE_RESERVED3", - H2C_MM_ERR_CODE_ENABLE_RESERVED3_MASK}, - {"H2C_MM_ERR_CODE_ENABLE_RD_DAT_POISON_ERR", - H2C_MM_ERR_CODE_ENABLE_RD_DAT_POISON_ERR_MASK}, - {"H2C_MM_ERR_CODE_ENABLE_RESERVED2", - H2C_MM_ERR_CODE_ENABLE_RESERVED2_MASK}, - {"H2C_MM_ERR_CODE_ENABLE_RD_FLR_ERR", - H2C_MM_ERR_CODE_ENABLE_RD_FLR_ERR_MASK}, - {"H2C_MM_ERR_CODE_ENABLE_RESERVED1", - H2C_MM_ERR_CODE_ENABLE_RESERVED1_MASK}, - {"H2C_MM_ERR_CODE_ENABLE_RD_HDR_ADR_ERR", - H2C_MM_ERR_CODE_ENABLE_RD_HDR_ADR_ERR_MASK}, - {"H2C_MM_ERR_CODE_ENABLE_RD_HDR_PARA", - H2C_MM_ERR_CODE_ENABLE_RD_HDR_PARA_MASK}, - {"H2C_MM_ERR_CODE_ENABLE_RD_HDR_BYTE_ERR", - H2C_MM_ERR_CODE_ENABLE_RD_HDR_BYTE_ERR_MASK}, - {"H2C_MM_ERR_CODE_ENABLE_RD_UR_CA", - H2C_MM_ERR_CODE_ENABLE_RD_UR_CA_MASK}, - {"H2C_MM_ERR_CODE_ENABLE_RD_HRD_POISON_ERR", - H2C_MM_ERR_CODE_ENABLE_RD_HRD_POISON_ERR_MASK}, - {"H2C_MM_ERR_CODE_ENABLE_RESERVED0", - H2C_MM_ERR_CODE_ENABLE_RESERVED0_MASK}, -}; - - -static struct regfield_info - h2c_mm_err_code_field_info[] = { - {"H2C_MM_ERR_CODE_RSVD_1", - H2C_MM_ERR_CODE_RSVD_1_MASK}, - {"H2C_MM_ERR_CODE_CIDX", - H2C_MM_ERR_CODE_CIDX_MASK}, - {"H2C_MM_ERR_CODE_RESERVED0", - H2C_MM_ERR_CODE_RESERVED0_MASK}, - {"H2C_MM_ERR_CODE_SUB_TYPE", - H2C_MM_ERR_CODE_SUB_TYPE_MASK}, - {"H2C_MM_ERR_CODE", - H2C_MM_ERR_CODE_MASK}, -}; - - -static struct regfield_info - h2c_mm_err_info_field_info[] = { - {"H2C_MM_ERR_INFO_VALID", - H2C_MM_ERR_INFO_VALID_MASK}, - {"H2C_MM_ERR_INFO_SEL", - H2C_MM_ERR_INFO_SEL_MASK}, - {"H2C_MM_ERR_INFO_RSVD_1", - H2C_MM_ERR_INFO_RSVD_1_MASK}, - {"H2C_MM_ERR_INFO_QID", - H2C_MM_ERR_INFO_QID_MASK}, -}; - - -static struct regfield_info - h2c_mm_perf_mon_ctl_field_info[] = { - {"H2C_MM_PERF_MON_CTL_RSVD_1", - H2C_MM_PERF_MON_CTL_RSVD_1_MASK}, - {"H2C_MM_PERF_MON_CTL_IMM_START", - H2C_MM_PERF_MON_CTL_IMM_START_MASK}, - {"H2C_MM_PERF_MON_CTL_RUN_START", - H2C_MM_PERF_MON_CTL_RUN_START_MASK}, - {"H2C_MM_PERF_MON_CTL_IMM_CLEAR", - H2C_MM_PERF_MON_CTL_IMM_CLEAR_MASK}, - {"H2C_MM_PERF_MON_CTL_RUN_CLEAR", - H2C_MM_PERF_MON_CTL_RUN_CLEAR_MASK}, -}; - - -static struct regfield_info - h2c_mm_perf_mon_cycle_cnt0_field_info[] = { - {"H2C_MM_PERF_MON_CYCLE_CNT0_CYC_CNT", - H2C_MM_PERF_MON_CYCLE_CNT0_CYC_CNT_MASK}, -}; - - -static struct regfield_info - h2c_mm_perf_mon_cycle_cnt1_field_info[] = { - {"H2C_MM_PERF_MON_CYCLE_CNT1_RSVD_1", - H2C_MM_PERF_MON_CYCLE_CNT1_RSVD_1_MASK}, - {"H2C_MM_PERF_MON_CYCLE_CNT1_CYC_CNT", - H2C_MM_PERF_MON_CYCLE_CNT1_CYC_CNT_MASK}, -}; - - -static struct regfield_info - h2c_mm_perf_mon_data_cnt0_field_info[] = { - {"H2C_MM_PERF_MON_DATA_CNT0_DCNT", - H2C_MM_PERF_MON_DATA_CNT0_DCNT_MASK}, -}; - - -static struct regfield_info - h2c_mm_perf_mon_data_cnt1_field_info[] = { - {"H2C_MM_PERF_MON_DATA_CNT1_RSVD_1", - H2C_MM_PERF_MON_DATA_CNT1_RSVD_1_MASK}, - {"H2C_MM_PERF_MON_DATA_CNT1_DCNT", - H2C_MM_PERF_MON_DATA_CNT1_DCNT_MASK}, -}; - - -static struct regfield_info - h2c_mm_dbg_field_info[] = { - {"H2C_MM_RSVD_1", - H2C_MM_RSVD_1_MASK}, - {"H2C_MM_RRQ_ENTRIES", - H2C_MM_RRQ_ENTRIES_MASK}, - {"H2C_MM_DAT_FIFO_SPC", - H2C_MM_DAT_FIFO_SPC_MASK}, - {"H2C_MM_RD_STALL", - H2C_MM_RD_STALL_MASK}, - {"H2C_MM_RRQ_FIFO_FI", - H2C_MM_RRQ_FIFO_FI_MASK}, - {"H2C_MM_WR_STALL", - H2C_MM_WR_STALL_MASK}, - {"H2C_MM_WRQ_FIFO_FI", - H2C_MM_WRQ_FIFO_FI_MASK}, - {"H2C_MM_WBK_STALL", - H2C_MM_WBK_STALL_MASK}, - {"H2C_MM_DSC_FIFO_EP", - H2C_MM_DSC_FIFO_EP_MASK}, - {"H2C_MM_DSC_FIFO_FL", - H2C_MM_DSC_FIFO_FL_MASK}, -}; - - -static struct regfield_info - h2c_mm_data_throttle_field_info[] = { - {"H2C_MM_DATA_THROTTLE_RSVD_1", - H2C_MM_DATA_THROTTLE_RSVD_1_MASK}, - {"H2C_MM_DATA_THROTTLE_DAT_EN", - H2C_MM_DATA_THROTTLE_DAT_EN_MASK}, - {"H2C_MM_DATA_THROTTLE_DAT", - H2C_MM_DATA_THROTTLE_DAT_MASK}, -}; - - -static struct regfield_info - c2h_crdt_coal_cfg_1_field_info[] = { - {"C2H_CRDT_COAL_CFG_1_RSVD_1", - C2H_CRDT_COAL_CFG_1_RSVD_1_MASK}, - {"C2H_CRDT_COAL_CFG_1_PLD_FIFO_TH", - C2H_CRDT_COAL_CFG_1_PLD_FIFO_TH_MASK}, - {"C2H_CRDT_COAL_CFG_1_TIMER_TH", - C2H_CRDT_COAL_CFG_1_TIMER_TH_MASK}, -}; - - -static struct regfield_info - c2h_crdt_coal_cfg_2_field_info[] = { - {"C2H_CRDT_COAL_CFG_2_RSVD_1", - C2H_CRDT_COAL_CFG_2_RSVD_1_MASK}, - {"C2H_CRDT_COAL_CFG_2_FIFO_TH", - C2H_CRDT_COAL_CFG_2_FIFO_TH_MASK}, - {"C2H_CRDT_COAL_CFG_2_RESERVED1", - C2H_CRDT_COAL_CFG_2_RESERVED1_MASK}, - {"C2H_CRDT_COAL_CFG_2_NT_TH", - C2H_CRDT_COAL_CFG_2_NT_TH_MASK}, -}; - - -static struct regfield_info - c2h_pfch_byp_qid_field_info[] = { - {"C2H_PFCH_BYP_QID_RSVD_1", - C2H_PFCH_BYP_QID_RSVD_1_MASK}, - {"C2H_PFCH_BYP_QID", - C2H_PFCH_BYP_QID_MASK}, -}; - - -static struct regfield_info - c2h_pfch_byp_tag_field_info[] = { - {"C2H_PFCH_BYP_TAG_RSVD_1", - C2H_PFCH_BYP_TAG_RSVD_1_MASK}, - {"C2H_PFCH_BYP_TAG_BYP_QID", - C2H_PFCH_BYP_TAG_BYP_QID_MASK}, - {"C2H_PFCH_BYP_TAG_RSVD_2", - C2H_PFCH_BYP_TAG_RSVD_2_MASK}, - {"C2H_PFCH_BYP_TAG", - C2H_PFCH_BYP_TAG_MASK}, -}; - - -static struct regfield_info - c2h_water_mark_field_info[] = { - {"C2H_WATER_MARK_HIGH_WM", - C2H_WATER_MARK_HIGH_WM_MASK}, - {"C2H_WATER_MARK_LOW_WM", - C2H_WATER_MARK_LOW_WM_MASK}, -}; - - -static struct regfield_info - c2h_notify_empty_field_info[] = { - {"C2H_NOTIFY_EMPTY_RSVD_1", - C2H_NOTIFY_EMPTY_RSVD_1_MASK}, - {"C2H_NOTIFY_EMPTY_NOE", - C2H_NOTIFY_EMPTY_NOE_MASK}, -}; - - -static struct regfield_info - c2h_stat_s_axis_c2h_accepted_1_field_info[] = { - {"C2H_STAT_S_AXIS_C2H_ACCEPTED_1", - C2H_STAT_S_AXIS_C2H_ACCEPTED_1_MASK}, -}; - - -static struct regfield_info - c2h_stat_s_axis_wrb_accepted_1_field_info[] = { - {"C2H_STAT_S_AXIS_WRB_ACCEPTED_1", - C2H_STAT_S_AXIS_WRB_ACCEPTED_1_MASK}, -}; - - -static struct regfield_info - c2h_stat_desc_rsp_pkt_accepted_1_field_info[] = { - {"C2H_STAT_DESC_RSP_PKT_ACCEPTED_1_D", - C2H_STAT_DESC_RSP_PKT_ACCEPTED_1_D_MASK}, -}; - - -static struct regfield_info - c2h_stat_axis_pkg_cmp_1_field_info[] = { - {"C2H_STAT_AXIS_PKG_CMP_1", - C2H_STAT_AXIS_PKG_CMP_1_MASK}, -}; - - -static struct regfield_info - c2h_stat_s_axis_wrb_accepted_2_field_info[] = { - {"C2H_STAT_S_AXIS_WRB_ACCEPTED_2", - C2H_STAT_S_AXIS_WRB_ACCEPTED_2_MASK}, -}; - - -static struct regfield_info - c2h_st_pld_fifo_depth_field_info[] = { - {"C2H_ST_PLD_FIFO_DEPTH", - C2H_ST_PLD_FIFO_DEPTH_MASK}, -}; - - -static struct regfield_info - c2h_stat_dbg_dma_eng_6_field_info[] = { - {"C2H_STAT_DMA_ENG_6_RSVD", - C2H_STAT_DMA_ENG_6_RSVD_MASK}, - {"C2H_STAT_DMA_ENG_6_PLD_ST_FIFO_OUT_DATA_QID", - C2H_STAT_DMA_ENG_6_PLD_ST_FIFO_OUT_DATA_QID_MASK}, - {"C2H_STAT_DMA_ENG_6_PLD_STS_FIFO_OUT_DATA_PLD_ST_PKT_ID", - C2H_STAT_DMA_ENG_6_PLD_STS_FIFO_OUT_DATA_PLD_ST_PKT_ID_MASK}, - {"C2H_STAT_DMA_ENG_6_PLD_PKT_ID_LARGER_PLD_ST", - C2H_STAT_DMA_ENG_6_PLD_PKT_ID_LARGER_PLD_ST_MASK}, -}; - - -static struct regfield_info - c2h_stat_dbg_dma_eng_7_field_info[] = { - {"C2H_STAT_DMA_ENG_7_RSVD", - C2H_STAT_DMA_ENG_7_RSVD_MASK}, - {"C2H_STAT_DMA_ENG_7_PLD_ST_FIFO_OUT_DATA_QID_1", - C2H_STAT_DMA_ENG_7_PLD_ST_FIFO_OUT_DATA_QID_1_MASK}, - {"C2H_STAT_DMA_ENG_7_PLD_STS_FIFO_OUT_DATA_PLD_ST_PKT_ID_1", - C2H_STAT_DMA_ENG_7_PLD_STS_FIFO_OUT_DATA_PLD_ST_PKT_ID_1_MASK}, - {"C2H_STAT_DMA_ENG_7_PLD_PKT_ID_LARGER_PLD_ST_1", - C2H_STAT_DMA_ENG_7_PLD_PKT_ID_LARGER_PLD_ST_1_MASK}, -}; - - -static struct regfield_info - c2h_stat_pcie_cmp_1_field_info[] = { - {"C2H_STAT_PCIE_CMP_1_DEPTH", - C2H_STAT_PCIE_CMP_1_DEPTH_MASK}, -}; - - -static struct regfield_info - c2h_pld_fifo_almost_full_field_info[] = { - {"C2H_PLD_FIFO_ALMOST_FULL_ENABLE", - C2H_PLD_FIFO_ALMOST_FULL_ENABLE_MASK}, - {"C2H_PLD_FIFO_ALMOST_FULL_TH", - C2H_PLD_FIFO_ALMOST_FULL_TH_MASK}, -}; - - -static struct regfield_info - pfch_cfg_3_field_info[] = { - {"PFCH_CFG_3_RSVD", - PFCH_CFG_3_RSVD_MASK}, - {"PFCH_CFG_3_VAR_DESC_FL_FREE_CNT_TH", - PFCH_CFG_3_VAR_DESC_FL_FREE_CNT_TH_MASK}, - {"PFCH_CFG_3_VAR_DESC_LG_PKT_CAM_CN_TH", - PFCH_CFG_3_VAR_DESC_LG_PKT_CAM_CN_TH_MASK}, -}; - - -static struct regfield_info - cmpt_cfg_0_field_info[] = { - {"CMPT_CFG_0_RSVD", - CMPT_CFG_0_RSVD_MASK}, - {"CMPT_CFG_0_VIO_SPRS_INT_AFTER_RTY", - CMPT_CFG_0_VIO_SPRS_INT_AFTER_RTY_MASK}, - {"CMPT_CFG_0_VIO_EVNT_SUP_EN", - CMPT_CFG_0_VIO_EVNT_SUP_EN_MASK}, -}; - - -static struct regfield_info - pfch_cfg_4_field_info[] = { - {"PFCH_CFG_4_GLB_EVT_TIMER_TICK", - PFCH_CFG_4_GLB_EVT_TIMER_TICK_MASK}, - {"PFCH_CFG_4_DISABLE_GLB_EVT_TIMER", - PFCH_CFG_4_DISABLE_GLB_EVT_TIMER_MASK}, - {"PFCH_CFG_4_EVT_TIMER_TICK", - PFCH_CFG_4_EVT_TIMER_TICK_MASK}, - {"PFCH_CFG_4_DISABLE_EVT_TIMER", - PFCH_CFG_4_DISABLE_EVT_TIMER_MASK}, -}; - -static struct xreg_info eqdma_config_regs[] = { -{"CFG_BLK_IDENTIFIER", 0x00, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(cfg_blk_identifier_field_info), - cfg_blk_identifier_field_info -}, -{"CFG_BLK_PCIE_MAX_PLD_SIZE", 0x08, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(cfg_blk_pcie_max_pld_size_field_info), - cfg_blk_pcie_max_pld_size_field_info -}, -{"CFG_BLK_PCIE_MAX_READ_REQ_SIZE", 0x0c, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(cfg_blk_pcie_max_read_req_size_field_info), - cfg_blk_pcie_max_read_req_size_field_info -}, -{"CFG_BLK_SYSTEM_ID", 0x10, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(cfg_blk_system_id_field_info), - cfg_blk_system_id_field_info -}, -{"CFG_BLK_MSIX_ENABLE", 0x014, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(cfg_blk_msix_enable_field_info), - cfg_blk_msix_enable_field_info -}, -{"CFG_PCIE_DATA_WIDTH", 0x18, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(cfg_pcie_data_width_field_info), - cfg_pcie_data_width_field_info -}, -{"CFG_PCIE_CTL", 0x1c, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(cfg_pcie_ctl_field_info), - cfg_pcie_ctl_field_info -}, -{"CFG_BLK_MSI_ENABLE", 0x20, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(cfg_blk_msi_enable_field_info), - cfg_blk_msi_enable_field_info -}, -{"CFG_AXI_USER_MAX_PLD_SIZE", 0x40, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(cfg_axi_user_max_pld_size_field_info), - cfg_axi_user_max_pld_size_field_info -}, -{"CFG_AXI_USER_MAX_READ_REQ_SIZE", 0x44, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(cfg_axi_user_max_read_req_size_field_info), - cfg_axi_user_max_read_req_size_field_info -}, -{"CFG_BLK_MISC_CTL", 0x4c, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(cfg_blk_misc_ctl_field_info), - cfg_blk_misc_ctl_field_info -}, -{"CFG_PL_CRED_CTL", 0x68, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(cfg_pl_cred_ctl_field_info), - cfg_pl_cred_ctl_field_info -}, -{"CFG_BLK_SCRATCH", 0x80, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(cfg_blk_scratch_field_info), - cfg_blk_scratch_field_info -}, -{"CFG_GIC", 0xa0, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(cfg_gic_field_info), - cfg_gic_field_info -}, -{"RAM_SBE_MSK_1_A", 0xe0, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(ram_sbe_msk_1_a_field_info), - ram_sbe_msk_1_a_field_info -}, -{"RAM_SBE_STS_1_A", 0xe4, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(ram_sbe_sts_1_a_field_info), - ram_sbe_sts_1_a_field_info -}, -{"RAM_DBE_MSK_1_A", 0xe8, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(ram_dbe_msk_1_a_field_info), - ram_dbe_msk_1_a_field_info -}, -{"RAM_DBE_STS_1_A", 0xec, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(ram_dbe_sts_1_a_field_info), - ram_dbe_sts_1_a_field_info -}, -{"RAM_SBE_MSK_A", 0xf0, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(ram_sbe_msk_a_field_info), - ram_sbe_msk_a_field_info -}, -{"RAM_SBE_STS_A", 0xf4, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(ram_sbe_sts_a_field_info), - ram_sbe_sts_a_field_info -}, -{"RAM_DBE_MSK_A", 0xf8, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(ram_dbe_msk_a_field_info), - ram_dbe_msk_a_field_info -}, -{"RAM_DBE_STS_A", 0xfc, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(ram_dbe_sts_a_field_info), - ram_dbe_sts_a_field_info -}, -{"GLBL2_IDENTIFIER", 0x100, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(glbl2_identifier_field_info), - glbl2_identifier_field_info -}, -{"GLBL2_CHANNEL_INST", 0x114, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(glbl2_channel_inst_field_info), - glbl2_channel_inst_field_info -}, -{"GLBL2_CHANNEL_MDMA", 0x118, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(glbl2_channel_mdma_field_info), - glbl2_channel_mdma_field_info -}, -{"GLBL2_CHANNEL_STRM", 0x11c, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(glbl2_channel_strm_field_info), - glbl2_channel_strm_field_info -}, -{"GLBL2_CHANNEL_CAP", 0x120, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(glbl2_channel_cap_field_info), - glbl2_channel_cap_field_info -}, -{"GLBL2_CHANNEL_PASID_CAP", 0x128, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(glbl2_channel_pasid_cap_field_info), - glbl2_channel_pasid_cap_field_info -}, -{"GLBL2_SYSTEM_ID", 0x130, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(glbl2_system_id_field_info), - glbl2_system_id_field_info -}, -{"GLBL2_MISC_CAP", 0x134, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(glbl2_misc_cap_field_info), - glbl2_misc_cap_field_info -}, -{"GLBL2_RRQ_BRG_THROT", 0x158, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(glbl2_rrq_brg_throt_field_info), - glbl2_rrq_brg_throt_field_info -}, -{"GLBL2_RRQ_PCIE_THROT", 0x15c, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(glbl2_rrq_pcie_throt_field_info), - glbl2_rrq_pcie_throt_field_info -}, -{"GLBL2_RRQ_AXIMM_THROT", 0x160, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(glbl2_rrq_aximm_throt_field_info), - glbl2_rrq_aximm_throt_field_info -}, -{"GLBL2_RRQ_PCIE_LAT0", 0x164, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(glbl2_rrq_pcie_lat0_field_info), - glbl2_rrq_pcie_lat0_field_info -}, -{"GLBL2_RRQ_PCIE_LAT1", 0x168, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(glbl2_rrq_pcie_lat1_field_info), - glbl2_rrq_pcie_lat1_field_info -}, -{"GLBL2_RRQ_AXIMM_LAT0", 0x16c, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(glbl2_rrq_aximm_lat0_field_info), - glbl2_rrq_aximm_lat0_field_info -}, -{"GLBL2_RRQ_AXIMM_LAT1", 0x170, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(glbl2_rrq_aximm_lat1_field_info), - glbl2_rrq_aximm_lat1_field_info -}, -{"GLBL2_DBG_PCIE_RQ0", 0x1b8, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(glbl2_dbg_pcie_rq0_field_info), - glbl2_dbg_pcie_rq0_field_info -}, -{"GLBL2_DBG_PCIE_RQ1", 0x1bc, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(glbl2_dbg_pcie_rq1_field_info), - glbl2_dbg_pcie_rq1_field_info -}, -{"GLBL2_DBG_AXIMM_WR0", 0x1c0, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(glbl2_dbg_aximm_wr0_field_info), - glbl2_dbg_aximm_wr0_field_info -}, -{"GLBL2_DBG_AXIMM_WR1", 0x1c4, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(glbl2_dbg_aximm_wr1_field_info), - glbl2_dbg_aximm_wr1_field_info -}, -{"GLBL2_DBG_AXIMM_RD0", 0x1c8, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(glbl2_dbg_aximm_rd0_field_info), - glbl2_dbg_aximm_rd0_field_info -}, -{"GLBL2_DBG_AXIMM_RD1", 0x1cc, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(glbl2_dbg_aximm_rd1_field_info), - glbl2_dbg_aximm_rd1_field_info -}, -{"GLBL2_DBG_FAB0", 0x1d0, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(glbl2_dbg_fab0_field_info), - glbl2_dbg_fab0_field_info -}, -{"GLBL2_DBG_FAB1", 0x1d4, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(glbl2_dbg_fab1_field_info), - glbl2_dbg_fab1_field_info -}, -{"GLBL2_DBG_MATCH_SEL", 0x1f4, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(glbl2_dbg_match_sel_field_info), - glbl2_dbg_match_sel_field_info -}, -{"GLBL2_DBG_MATCH_MSK", 0x1f8, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(glbl2_dbg_match_msk_field_info), - glbl2_dbg_match_msk_field_info -}, -{"GLBL2_DBG_MATCH_PAT", 0x1fc, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(glbl2_dbg_match_pat_field_info), - glbl2_dbg_match_pat_field_info -}, -{"GLBL_RNG_SZ_1", 0x204, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(glbl_rng_sz_1_field_info), - glbl_rng_sz_1_field_info -}, -{"GLBL_RNG_SZ_2", 0x208, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(glbl_rng_sz_2_field_info), - glbl_rng_sz_2_field_info -}, -{"GLBL_RNG_SZ_3", 0x20c, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(glbl_rng_sz_3_field_info), - glbl_rng_sz_3_field_info -}, -{"GLBL_RNG_SZ_4", 0x210, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(glbl_rng_sz_4_field_info), - glbl_rng_sz_4_field_info -}, -{"GLBL_RNG_SZ_5", 0x214, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(glbl_rng_sz_5_field_info), - glbl_rng_sz_5_field_info -}, -{"GLBL_RNG_SZ_6", 0x218, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(glbl_rng_sz_6_field_info), - glbl_rng_sz_6_field_info -}, -{"GLBL_RNG_SZ_7", 0x21c, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(glbl_rng_sz_7_field_info), - glbl_rng_sz_7_field_info -}, -{"GLBL_RNG_SZ_8", 0x220, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(glbl_rng_sz_8_field_info), - glbl_rng_sz_8_field_info -}, -{"GLBL_RNG_SZ_9", 0x224, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(glbl_rng_sz_9_field_info), - glbl_rng_sz_9_field_info -}, -{"GLBL_RNG_SZ_A", 0x228, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(glbl_rng_sz_a_field_info), - glbl_rng_sz_a_field_info -}, -{"GLBL_RNG_SZ_B", 0x22c, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(glbl_rng_sz_b_field_info), - glbl_rng_sz_b_field_info -}, -{"GLBL_RNG_SZ_C", 0x230, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(glbl_rng_sz_c_field_info), - glbl_rng_sz_c_field_info -}, -{"GLBL_RNG_SZ_D", 0x234, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(glbl_rng_sz_d_field_info), - glbl_rng_sz_d_field_info -}, -{"GLBL_RNG_SZ_E", 0x238, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(glbl_rng_sz_e_field_info), - glbl_rng_sz_e_field_info -}, -{"GLBL_RNG_SZ_F", 0x23c, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(glbl_rng_sz_f_field_info), - glbl_rng_sz_f_field_info -}, -{"GLBL_RNG_SZ_10", 0x240, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(glbl_rng_sz_10_field_info), - glbl_rng_sz_10_field_info -}, -{"GLBL_ERR_STAT", 0x248, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(glbl_err_stat_field_info), - glbl_err_stat_field_info -}, -{"GLBL_ERR_MASK", 0x24c, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(glbl_err_mask_field_info), - glbl_err_mask_field_info -}, -{"GLBL_DSC_CFG", 0x250, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(glbl_dsc_cfg_field_info), - glbl_dsc_cfg_field_info -}, -{"GLBL_DSC_ERR_STS", 0x254, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(glbl_dsc_err_sts_field_info), - glbl_dsc_err_sts_field_info -}, -{"GLBL_DSC_ERR_MSK", 0x258, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(glbl_dsc_err_msk_field_info), - glbl_dsc_err_msk_field_info -}, -{"GLBL_DSC_ERR_LOG0", 0x25c, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(glbl_dsc_err_log0_field_info), - glbl_dsc_err_log0_field_info -}, -{"GLBL_DSC_ERR_LOG1", 0x260, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(glbl_dsc_err_log1_field_info), - glbl_dsc_err_log1_field_info -}, -{"GLBL_TRQ_ERR_STS", 0x264, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(glbl_trq_err_sts_field_info), - glbl_trq_err_sts_field_info -}, -{"GLBL_TRQ_ERR_MSK", 0x268, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(glbl_trq_err_msk_field_info), - glbl_trq_err_msk_field_info -}, -{"GLBL_TRQ_ERR_LOG", 0x26c, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(glbl_trq_err_log_field_info), - glbl_trq_err_log_field_info -}, -{"GLBL_DSC_DBG_DAT0", 0x270, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(glbl_dsc_dbg_dat0_field_info), - glbl_dsc_dbg_dat0_field_info -}, -{"GLBL_DSC_DBG_DAT1", 0x274, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(glbl_dsc_dbg_dat1_field_info), - glbl_dsc_dbg_dat1_field_info -}, -{"GLBL_DSC_DBG_CTL", 0x278, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(glbl_dsc_dbg_ctl_field_info), - glbl_dsc_dbg_ctl_field_info -}, -{"GLBL_DSC_ERR_LOG2", 0x27c, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(glbl_dsc_err_log2_field_info), - glbl_dsc_err_log2_field_info -}, -{"GLBL_GLBL_INTERRUPT_CFG", 0x2c4, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(glbl_glbl_interrupt_cfg_field_info), - glbl_glbl_interrupt_cfg_field_info -}, -{"GLBL_VCH_HOST_PROFILE", 0x2c8, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(glbl_vch_host_profile_field_info), - glbl_vch_host_profile_field_info -}, -{"GLBL_BRIDGE_HOST_PROFILE", 0x308, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(glbl_bridge_host_profile_field_info), - glbl_bridge_host_profile_field_info -}, -{"AXIMM_IRQ_DEST_ADDR", 0x30c, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(aximm_irq_dest_addr_field_info), - aximm_irq_dest_addr_field_info -}, -{"FAB_ERR_LOG", 0x314, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(fab_err_log_field_info), - fab_err_log_field_info -}, -{"GLBL_REQ_ERR_STS", 0x318, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(glbl_req_err_sts_field_info), - glbl_req_err_sts_field_info -}, -{"GLBL_REQ_ERR_MSK", 0x31c, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(glbl_req_err_msk_field_info), - glbl_req_err_msk_field_info -}, -{"GLBL_DSC_DBG_LAT0_A", 0x320, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(glbl_dsc_dbg_lat0_a_field_info), - glbl_dsc_dbg_lat0_a_field_info -}, -{"GLBL_DSC_DBG_LAT1_A", 0x324, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(glbl_dsc_dbg_lat1_a_field_info), - glbl_dsc_dbg_lat1_a_field_info -}, -{"GLBL_DSC_CRD_CTR0_A", 0x328, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(glbl_dsc_crd_ctr0_a_field_info), - glbl_dsc_crd_ctr0_a_field_info -}, -{"GLBL_DSC_CRD_CTR1_A", 0x32c, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(glbl_dsc_crd_ctr1_a_field_info), - glbl_dsc_crd_ctr1_a_field_info -}, -{"GLBL_DSC_CRD_CTR2_A", 0x330, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(glbl_dsc_crd_ctr2_a_field_info), - glbl_dsc_crd_ctr2_a_field_info -}, -{"GLBL_DSC_CRD_CTR3_A", 0x334, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(glbl_dsc_crd_ctr3_a_field_info), - glbl_dsc_crd_ctr3_a_field_info -}, -{"GLBL_DSC_IMM_CRD_CTR0_A", 0x338, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(glbl_dsc_imm_crd_ctr0_a_field_info), - glbl_dsc_imm_crd_ctr0_a_field_info -}, -{"GLBL_DSC_IMM_CRD_CTR1_A", 0x33c, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(glbl_dsc_imm_crd_ctr1_a_field_info), - glbl_dsc_imm_crd_ctr1_a_field_info -}, -{"GLBL_DSC_IMM_CRD_CTR2_A", 0x340, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(glbl_dsc_imm_crd_ctr2_a_field_info), - glbl_dsc_imm_crd_ctr2_a_field_info -}, -{"GLBL_DSC_IMM_CRD_CTR3_A", 0x344, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(glbl_dsc_imm_crd_ctr3_a_field_info), - glbl_dsc_imm_crd_ctr3_a_field_info -}, -{"GLBL_DSC_H2C_OUT_CTR0_A", 0x348, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(glbl_dsc_h2c_out_ctr0_a_field_info), - glbl_dsc_h2c_out_ctr0_a_field_info -}, -{"GLBL_DSC_H2C_OUT_CTR1_A", 0x34c, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(glbl_dsc_h2c_out_ctr1_a_field_info), - glbl_dsc_h2c_out_ctr1_a_field_info -}, -{"GLBL_DSC_H2C_OUT_CTR2_A", 0x350, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(glbl_dsc_h2c_out_ctr2_a_field_info), - glbl_dsc_h2c_out_ctr2_a_field_info -}, -{"GLBL_DSC_H2C_OUT_CTR3_A", 0x354, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(glbl_dsc_h2c_out_ctr3_a_field_info), - glbl_dsc_h2c_out_ctr3_a_field_info -}, -{"GLBL_DSC_C2H_OUT_CTR0_A", 0x358, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(glbl_dsc_c2h_out_ctr0_a_field_info), - glbl_dsc_c2h_out_ctr0_a_field_info -}, -{"GLBL_DSC_C2H_OUT_CTR1_A", 0x35c, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(glbl_dsc_c2h_out_ctr1_a_field_info), - glbl_dsc_c2h_out_ctr1_a_field_info -}, -{"GLBL_DSC_C2H_OUT_CTR2_A", 0x360, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(glbl_dsc_c2h_out_ctr2_a_field_info), - glbl_dsc_c2h_out_ctr2_a_field_info -}, -{"GLBL_DSC_C2H_OUT_CTR3_A", 0x364, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(glbl_dsc_c2h_out_ctr3_a_field_info), - glbl_dsc_c2h_out_ctr3_a_field_info -}, -{"T", 0x368, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(t_field_info), - t_field_info -}, -{"GLBL_PERF_CNTR_CTL_A1", 0x36c, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(glbl_perf_cntr_ctl_a1_field_info), - glbl_perf_cntr_ctl_a1_field_info -}, -{"GLBL_FREE_CNT_A0", 0x370, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(glbl_free_cnt_a0_field_info), - glbl_free_cnt_a0_field_info -}, -{"GLBL_FREE_CNT_A1", 0x374, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(glbl_free_cnt_a1_field_info), - glbl_free_cnt_a1_field_info -}, -{"GLBL_AXIS_H2C_CNT_A0", 0x378, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(glbl_axis_h2c_cnt_a0_field_info), - glbl_axis_h2c_cnt_a0_field_info -}, -{"GLBL_AXIS_H2C_CNT_A1", 0x37c, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(glbl_axis_h2c_cnt_a1_field_info), - glbl_axis_h2c_cnt_a1_field_info -}, -{"GLBL_AXIS_H2C_CNT_A2", 0x380, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(glbl_axis_h2c_cnt_a2_field_info), - glbl_axis_h2c_cnt_a2_field_info -}, -{"GLBL_AXIS_H2C_CNT_A3", 0x384, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(glbl_axis_h2c_cnt_a3_field_info), - glbl_axis_h2c_cnt_a3_field_info -}, -{"GLBL_AXIS_H2C_CNT_A4", 0x388, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(glbl_axis_h2c_cnt_a4_field_info), - glbl_axis_h2c_cnt_a4_field_info -}, -{"GLBL_AXIS_H2C_CNT_A5", 0x38c, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(glbl_axis_h2c_cnt_a5_field_info), - glbl_axis_h2c_cnt_a5_field_info -}, -{"GLBL_AXIS_C2H_CNT_A0", 0x390, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(glbl_axis_c2h_cnt_a0_field_info), - glbl_axis_c2h_cnt_a0_field_info -}, -{"GLBL_AXIS_C2H_CNT_A1", 0x394, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(glbl_axis_c2h_cnt_a1_field_info), - glbl_axis_c2h_cnt_a1_field_info -}, -{"GLBL_AXIS_C2H_CNT_A2", 0x398, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(glbl_axis_c2h_cnt_a2_field_info), - glbl_axis_c2h_cnt_a2_field_info -}, -{"GLBL_AXIS_C2H_CNT_A3", 0x39c, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(glbl_axis_c2h_cnt_a3_field_info), - glbl_axis_c2h_cnt_a3_field_info -}, -{"GLBL_AXIS_C2H_CNT_A4", 0x3a0, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(glbl_axis_c2h_cnt_a4_field_info), - glbl_axis_c2h_cnt_a4_field_info -}, -{"GLBL_AXIS_C2H_CNT_A5", 0x3a4, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(glbl_axis_c2h_cnt_a5_field_info), - glbl_axis_c2h_cnt_a5_field_info -}, -{"GLBL_M_AXI_WR_CNT_A0", 0x3a8, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(glbl_m_axi_wr_cnt_a0_field_info), - glbl_m_axi_wr_cnt_a0_field_info -}, -{"GLBL_M_AXI_WR_CNT_A1", 0x3ac, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(glbl_m_axi_wr_cnt_a1_field_info), - glbl_m_axi_wr_cnt_a1_field_info -}, -{"GLBL_M_AXI_WR_CNT_A2", 0x3b0, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(glbl_m_axi_wr_cnt_a2_field_info), - glbl_m_axi_wr_cnt_a2_field_info -}, -{"GLBL_M_AXI_WR_CNT_A3", 0x3b4, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(glbl_m_axi_wr_cnt_a3_field_info), - glbl_m_axi_wr_cnt_a3_field_info -}, -{"GLBL_M_AXI_WR_CNT_A4", 0x3b8, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(glbl_m_axi_wr_cnt_a4_field_info), - glbl_m_axi_wr_cnt_a4_field_info -}, -{"GLBL_M_AXI_WR_CNT_A5", 0x3bc, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(glbl_m_axi_wr_cnt_a5_field_info), - glbl_m_axi_wr_cnt_a5_field_info -}, -{"GLBL_M_AXI_RD_CNT_A0", 0x3c0, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(glbl_m_axi_rd_cnt_a0_field_info), - glbl_m_axi_rd_cnt_a0_field_info -}, -{"GLBL_M_AXI_RD_CNT_A1", 0x3c4, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(glbl_m_axi_rd_cnt_a1_field_info), - glbl_m_axi_rd_cnt_a1_field_info -}, -{"GLBL_M_AXI_RD_CNT_A2", 0x3c8, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(glbl_m_axi_rd_cnt_a2_field_info), - glbl_m_axi_rd_cnt_a2_field_info -}, -{"GLBL_M_AXI_RD_CNT_A3", 0x3cc, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(glbl_m_axi_rd_cnt_a3_field_info), - glbl_m_axi_rd_cnt_a3_field_info -}, -{"GLBL_M_AXI_RD_CNT_A4", 0x3d0, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(glbl_m_axi_rd_cnt_a4_field_info), - glbl_m_axi_rd_cnt_a4_field_info -}, -{"GLBL_M_AXI_RD_CNT_A5", 0x3d4, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(glbl_m_axi_rd_cnt_a5_field_info), - glbl_m_axi_rd_cnt_a5_field_info -}, -{"GLBL_M_AXIB_WR_CNT_A0", 0x3d8, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(glbl_m_axib_wr_cnt_a0_field_info), - glbl_m_axib_wr_cnt_a0_field_info -}, -{"GLBL_M_AXIB_WR_CNT_A1", 0x3dc, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(glbl_m_axib_wr_cnt_a1_field_info), - glbl_m_axib_wr_cnt_a1_field_info -}, -{"GLBL_M_AXIB_WR_CNT_A2", 0x3e0, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(glbl_m_axib_wr_cnt_a2_field_info), - glbl_m_axib_wr_cnt_a2_field_info -}, -{"GLBL_M_AXIB_WR_CNT_A3", 0x3e4, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(glbl_m_axib_wr_cnt_a3_field_info), - glbl_m_axib_wr_cnt_a3_field_info -}, -{"GLBL_M_AXIB_WR_CNT_A4", 0x3e8, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(glbl_m_axib_wr_cnt_a4_field_info), - glbl_m_axib_wr_cnt_a4_field_info -}, -{"GLBL_M_AXIB_WR_CNT_A5", 0x3ec, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(glbl_m_axib_wr_cnt_a5_field_info), - glbl_m_axib_wr_cnt_a5_field_info -}, -{"GLBL_M_AXIB_RD_CNT_A0", 0x3f0, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(glbl_m_axib_rd_cnt_a0_field_info), - glbl_m_axib_rd_cnt_a0_field_info -}, -{"GLBL_M_AXIB_RD_CNT_A1", 0x3f4, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(glbl_m_axib_rd_cnt_a1_field_info), - glbl_m_axib_rd_cnt_a1_field_info -}, -{"GLBL_M_AXIB_RD_CNT_A2", 0x3f8, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(glbl_m_axib_rd_cnt_a2_field_info), - glbl_m_axib_rd_cnt_a2_field_info -}, -{"GLBL_M_AXIB_RD_CNT_A3", 0x3fc, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(glbl_m_axib_rd_cnt_a3_field_info), - glbl_m_axib_rd_cnt_a3_field_info -}, -{"GLBL_M_AXIB_RD_CNT_A4", 0x400, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(glbl_m_axib_rd_cnt_a4_field_info), - glbl_m_axib_rd_cnt_a4_field_info -}, -{"GLBL_M_AXIB_RD_CNT_A5", 0x404, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(glbl_m_axib_rd_cnt_a5_field_info), - glbl_m_axib_rd_cnt_a5_field_info -}, -{"GLBL_S_AXI_WR_CNT_A0", 0x408, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(glbl_s_axi_wr_cnt_a0_field_info), - glbl_s_axi_wr_cnt_a0_field_info -}, -{"GLBL_S_AXI_WR_CNT_A1", 0x40c, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(glbl_s_axi_wr_cnt_a1_field_info), - glbl_s_axi_wr_cnt_a1_field_info -}, -{"GLBL_S_AXI_WR_CNT_A2", 0x410, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(glbl_s_axi_wr_cnt_a2_field_info), - glbl_s_axi_wr_cnt_a2_field_info -}, -{"GLBL_S_AXI_WR_CNT_A3", 0x414, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(glbl_s_axi_wr_cnt_a3_field_info), - glbl_s_axi_wr_cnt_a3_field_info -}, -{"GLBL_S_AXI_WR_CNT_A4", 0x418, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(glbl_s_axi_wr_cnt_a4_field_info), - glbl_s_axi_wr_cnt_a4_field_info -}, -{"GLBL_S_AXI_WR_CNT_A5", 0x41c, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(glbl_s_axi_wr_cnt_a5_field_info), - glbl_s_axi_wr_cnt_a5_field_info -}, -{"GLBL_S_AXI_RD_CNT_A0", 0x420, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(glbl_s_axi_rd_cnt_a0_field_info), - glbl_s_axi_rd_cnt_a0_field_info -}, -{"GLBL_S_AXI_RD_CNT_A1", 0x424, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(glbl_s_axi_rd_cnt_a1_field_info), - glbl_s_axi_rd_cnt_a1_field_info -}, -{"GLBL_S_AXI_RD_CNT_A2", 0x428, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(glbl_s_axi_rd_cnt_a2_field_info), - glbl_s_axi_rd_cnt_a2_field_info -}, -{"GLBL_S_AXI_RD_CNT_A3", 0x42c, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(glbl_s_axi_rd_cnt_a3_field_info), - glbl_s_axi_rd_cnt_a3_field_info -}, -{"GLBL_S_AXI_RD_CNT_A4", 0x430, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(glbl_s_axi_rd_cnt_a4_field_info), - glbl_s_axi_rd_cnt_a4_field_info -}, -{"GLBL_S_AXI_RD_CNT_A5", 0x434, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(glbl_s_axi_rd_cnt_a5_field_info), - glbl_s_axi_rd_cnt_a5_field_info -}, -{"GLBL_S_AXIS_CMP_CNT_A0", 0x438, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(glbl_s_axis_cmp_cnt_a0_field_info), - glbl_s_axis_cmp_cnt_a0_field_info -}, -{"GLBL_S_AXIS_CMP_CNT_A1", 0x43c, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(glbl_s_axis_cmp_cnt_a1_field_info), - glbl_s_axis_cmp_cnt_a1_field_info -}, -{"GLBL_S_AXIS_CMP_CNT_A2", 0x440, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(glbl_s_axis_cmp_cnt_a2_field_info), - glbl_s_axis_cmp_cnt_a2_field_info -}, -{"GLBL_S_AXIS_CMP_CNT_A3", 0x444, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(glbl_s_axis_cmp_cnt_a3_field_info), - glbl_s_axis_cmp_cnt_a3_field_info -}, -{"GLBL_S_AXIS_CMP_CNT_A4", 0x448, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(glbl_s_axis_cmp_cnt_a4_field_info), - glbl_s_axis_cmp_cnt_a4_field_info -}, -{"GLBL_S_AXIS_CMP_CNT_A5", 0x44c, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(glbl_s_axis_cmp_cnt_a5_field_info), - glbl_s_axis_cmp_cnt_a5_field_info -}, -{"IND_CTXT_DATA", 0x804, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(ind_ctxt_data_field_info), - ind_ctxt_data_field_info -}, -{"IND_CTXT_MASK", 0x824, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(ind_ctxt_mask_field_info), - ind_ctxt_mask_field_info -}, -{"IND_CTXT_CMD", 0x844, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(ind_ctxt_cmd_field_info), - ind_ctxt_cmd_field_info -}, -{"C2H_TIMER_CNT", 0xa00, - 1, 0, 0, 0, - 0, QDMA_COMPLETION_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_timer_cnt_field_info), - c2h_timer_cnt_field_info -}, -{"C2H_CNT_TH", 0xa40, - 1, 0, 0, 0, - 0, QDMA_COMPLETION_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_cnt_th_field_info), - c2h_cnt_th_field_info -}, -{"C2H_PFCH_CFG_1", 0xa80, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(c2h_pfch_cfg_1_field_info), - c2h_pfch_cfg_1_field_info -}, -{"C2H_PFCH_CFG_2", 0xa84, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(c2h_pfch_cfg_2_field_info), - c2h_pfch_cfg_2_field_info -}, -{"C2H_STAT_S_AXIS_C2H_ACCEPTED", 0xa88, - 1, 0, 0, 0, - 1, QDMA_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(c2h_stat_s_axis_c2h_accepted_field_info), - c2h_stat_s_axis_c2h_accepted_field_info -}, -{"C2H_STAT_S_AXIS_WRB_ACCEPTED", 0xa8c, - 1, 0, 0, 0, - 1, QDMA_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(c2h_stat_s_axis_wrb_accepted_field_info), - c2h_stat_s_axis_wrb_accepted_field_info -}, -{"C2H_STAT_DESC_RSP_PKT_ACCEPTED", 0xa90, - 1, 0, 0, 0, - 1, QDMA_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(c2h_stat_desc_rsp_pkt_accepted_field_info), - c2h_stat_desc_rsp_pkt_accepted_field_info -}, -{"C2H_STAT_AXIS_PKG_CMP", 0xa94, - 1, 0, 0, 0, - 1, QDMA_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(c2h_stat_axis_pkg_cmp_field_info), - c2h_stat_axis_pkg_cmp_field_info -}, -{"C2H_STAT_DESC_RSP_ACCEPTED", 0xa98, - 1, 0, 0, 0, - 1, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_stat_desc_rsp_accepted_field_info), - c2h_stat_desc_rsp_accepted_field_info -}, -{"C2H_STAT_DESC_RSP_CMP", 0xa9c, - 1, 0, 0, 0, - 1, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_stat_desc_rsp_cmp_field_info), - c2h_stat_desc_rsp_cmp_field_info -}, -{"C2H_STAT_WRQ_OUT", 0xaa0, - 1, 0, 0, 0, - 1, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_stat_wrq_out_field_info), - c2h_stat_wrq_out_field_info -}, -{"C2H_STAT_WPL_REN_ACCEPTED", 0xaa4, - 1, 0, 0, 0, - 1, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_stat_wpl_ren_accepted_field_info), - c2h_stat_wpl_ren_accepted_field_info -}, -{"C2H_STAT_TOTAL_WRQ_LEN", 0xaa8, - 1, 0, 0, 0, - 1, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_stat_total_wrq_len_field_info), - c2h_stat_total_wrq_len_field_info -}, -{"C2H_STAT_TOTAL_WPL_LEN", 0xaac, - 1, 0, 0, 0, - 1, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_stat_total_wpl_len_field_info), - c2h_stat_total_wpl_len_field_info -}, -{"C2H_BUF_SZ", 0xab0, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_buf_sz_field_info), - c2h_buf_sz_field_info -}, -{"C2H_ERR_STAT", 0xaf0, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(c2h_err_stat_field_info), - c2h_err_stat_field_info -}, -{"C2H_ERR_MASK", 0xaf4, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(c2h_err_mask_field_info), - c2h_err_mask_field_info -}, -{"C2H_FATAL_ERR_STAT", 0xaf8, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(c2h_fatal_err_stat_field_info), - c2h_fatal_err_stat_field_info -}, -{"C2H_FATAL_ERR_MASK", 0xafc, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(c2h_fatal_err_mask_field_info), - c2h_fatal_err_mask_field_info -}, -{"C2H_FATAL_ERR_ENABLE", 0xb00, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(c2h_fatal_err_enable_field_info), - c2h_fatal_err_enable_field_info -}, -{"GLBL_ERR_INT", 0xb04, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(glbl_err_int_field_info), - glbl_err_int_field_info -}, -{"C2H_PFCH_CFG", 0xb08, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_pfch_cfg_field_info), - c2h_pfch_cfg_field_info -}, -{"C2H_INT_TIMER_TICK", 0xb0c, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_int_timer_tick_field_info), - c2h_int_timer_tick_field_info -}, -{"C2H_STAT_DESC_RSP_DROP_ACCEPTED", 0xb10, - 1, 0, 0, 0, - 1, QDMA_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(c2h_stat_desc_rsp_drop_accepted_field_info), - c2h_stat_desc_rsp_drop_accepted_field_info -}, -{"C2H_STAT_DESC_RSP_ERR_ACCEPTED", 0xb14, - 1, 0, 0, 0, - 1, QDMA_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(c2h_stat_desc_rsp_err_accepted_field_info), - c2h_stat_desc_rsp_err_accepted_field_info -}, -{"C2H_STAT_DESC_REQ", 0xb18, - 1, 0, 0, 0, - 1, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_stat_desc_req_field_info), - c2h_stat_desc_req_field_info -}, -{"C2H_STAT_DBG_DMA_ENG_0", 0xb1c, - 1, 0, 0, 0, - 1, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_stat_dbg_dma_eng_0_field_info), - c2h_stat_dbg_dma_eng_0_field_info -}, -{"C2H_STAT_DBG_DMA_ENG_1", 0xb20, - 1, 0, 0, 0, - 1, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_stat_dbg_dma_eng_1_field_info), - c2h_stat_dbg_dma_eng_1_field_info -}, -{"C2H_STAT_DBG_DMA_ENG_2", 0xb24, - 1, 0, 0, 0, - 1, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_stat_dbg_dma_eng_2_field_info), - c2h_stat_dbg_dma_eng_2_field_info -}, -{"C2H_STAT_DBG_DMA_ENG_3", 0xb28, - 1, 0, 0, 0, - 1, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_stat_dbg_dma_eng_3_field_info), - c2h_stat_dbg_dma_eng_3_field_info -}, -{"C2H_DBG_PFCH_ERR_CTXT", 0xb2c, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_dbg_pfch_err_ctxt_field_info), - c2h_dbg_pfch_err_ctxt_field_info -}, -{"C2H_FIRST_ERR_QID", 0xb30, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(c2h_first_err_qid_field_info), - c2h_first_err_qid_field_info -}, -{"STAT_NUM_WRB_IN", 0xb34, - 1, 0, 0, 0, - 1, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(stat_num_wrb_in_field_info), - stat_num_wrb_in_field_info -}, -{"STAT_NUM_WRB_OUT", 0xb38, - 1, 0, 0, 0, - 1, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(stat_num_wrb_out_field_info), - stat_num_wrb_out_field_info -}, -{"STAT_NUM_WRB_DRP", 0xb3c, - 1, 0, 0, 0, - 1, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(stat_num_wrb_drp_field_info), - stat_num_wrb_drp_field_info -}, -{"STAT_NUM_STAT_DESC_OUT", 0xb40, - 1, 0, 0, 0, - 1, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(stat_num_stat_desc_out_field_info), - stat_num_stat_desc_out_field_info -}, -{"STAT_NUM_DSC_CRDT_SENT", 0xb44, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(stat_num_dsc_crdt_sent_field_info), - stat_num_dsc_crdt_sent_field_info -}, -{"STAT_NUM_FCH_DSC_RCVD", 0xb48, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(stat_num_fch_dsc_rcvd_field_info), - stat_num_fch_dsc_rcvd_field_info -}, -{"STAT_NUM_BYP_DSC_RCVD", 0xb4c, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(stat_num_byp_dsc_rcvd_field_info), - stat_num_byp_dsc_rcvd_field_info -}, -{"C2H_WRB_COAL_CFG", 0xb50, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_wrb_coal_cfg_field_info), - c2h_wrb_coal_cfg_field_info -}, -{"C2H_INTR_H2C_REQ", 0xb54, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(c2h_intr_h2c_req_field_info), - c2h_intr_h2c_req_field_info -}, -{"C2H_INTR_C2H_MM_REQ", 0xb58, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(c2h_intr_c2h_mm_req_field_info), - c2h_intr_c2h_mm_req_field_info -}, -{"C2H_INTR_ERR_INT_REQ", 0xb5c, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(c2h_intr_err_int_req_field_info), - c2h_intr_err_int_req_field_info -}, -{"C2H_INTR_C2H_ST_REQ", 0xb60, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(c2h_intr_c2h_st_req_field_info), - c2h_intr_c2h_st_req_field_info -}, -{"C2H_INTR_H2C_ERR_C2H_MM_MSIX_ACK", 0xb64, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_intr_h2c_err_c2h_mm_msix_ack_field_info), - c2h_intr_h2c_err_c2h_mm_msix_ack_field_info -}, -{"C2H_INTR_H2C_ERR_C2H_MM_MSIX_FAIL", 0xb68, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_intr_h2c_err_c2h_mm_msix_fail_field_info), - c2h_intr_h2c_err_c2h_mm_msix_fail_field_info -}, -{"C2H_INTR_H2C_ERR_C2H_MM_MSIX_NO_MSIX", 0xb6c, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_intr_h2c_err_c2h_mm_msix_no_msix_field_info), - c2h_intr_h2c_err_c2h_mm_msix_no_msix_field_info -}, -{"C2H_INTR_H2C_ERR_C2H_MM_CTXT_INVAL", 0xb70, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_intr_h2c_err_c2h_mm_ctxt_inval_field_info), - c2h_intr_h2c_err_c2h_mm_ctxt_inval_field_info -}, -{"C2H_INTR_C2H_ST_MSIX_ACK", 0xb74, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(c2h_intr_c2h_st_msix_ack_field_info), - c2h_intr_c2h_st_msix_ack_field_info -}, -{"C2H_INTR_C2H_ST_MSIX_FAIL", 0xb78, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(c2h_intr_c2h_st_msix_fail_field_info), - c2h_intr_c2h_st_msix_fail_field_info -}, -{"C2H_INTR_C2H_ST_NO_MSIX", 0xb7c, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_intr_c2h_st_no_msix_field_info), - c2h_intr_c2h_st_no_msix_field_info -}, -{"C2H_INTR_C2H_ST_CTXT_INVAL", 0xb80, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_intr_c2h_st_ctxt_inval_field_info), - c2h_intr_c2h_st_ctxt_inval_field_info -}, -{"C2H_STAT_WR_CMP", 0xb84, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_stat_wr_cmp_field_info), - c2h_stat_wr_cmp_field_info -}, -{"C2H_STAT_DBG_DMA_ENG_4", 0xb88, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_stat_dbg_dma_eng_4_field_info), - c2h_stat_dbg_dma_eng_4_field_info -}, -{"C2H_STAT_DBG_DMA_ENG_5", 0xb8c, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_stat_dbg_dma_eng_5_field_info), - c2h_stat_dbg_dma_eng_5_field_info -}, -{"C2H_DBG_PFCH_QID", 0xb90, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_dbg_pfch_qid_field_info), - c2h_dbg_pfch_qid_field_info -}, -{"C2H_DBG_PFCH", 0xb94, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_dbg_pfch_field_info), - c2h_dbg_pfch_field_info -}, -{"C2H_INT_DBG", 0xb98, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_int_dbg_field_info), - c2h_int_dbg_field_info -}, -{"C2H_STAT_IMM_ACCEPTED", 0xb9c, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_stat_imm_accepted_field_info), - c2h_stat_imm_accepted_field_info -}, -{"C2H_STAT_MARKER_ACCEPTED", 0xba0, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_stat_marker_accepted_field_info), - c2h_stat_marker_accepted_field_info -}, -{"C2H_STAT_DISABLE_CMP_ACCEPTED", 0xba4, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_stat_disable_cmp_accepted_field_info), - c2h_stat_disable_cmp_accepted_field_info -}, -{"C2H_PLD_FIFO_CRDT_CNT", 0xba8, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_pld_fifo_crdt_cnt_field_info), - c2h_pld_fifo_crdt_cnt_field_info -}, -{"C2H_INTR_DYN_REQ", 0xbac, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_intr_dyn_req_field_info), - c2h_intr_dyn_req_field_info -}, -{"C2H_INTR_DYN_MISC", 0xbb0, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_intr_dyn_misc_field_info), - c2h_intr_dyn_misc_field_info -}, -{"C2H_DROP_LEN_MISMATCH", 0xbb4, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_drop_len_mismatch_field_info), - c2h_drop_len_mismatch_field_info -}, -{"C2H_DROP_DESC_RSP_LEN", 0xbb8, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_drop_desc_rsp_len_field_info), - c2h_drop_desc_rsp_len_field_info -}, -{"C2H_DROP_QID_FIFO_LEN", 0xbbc, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_drop_qid_fifo_len_field_info), - c2h_drop_qid_fifo_len_field_info -}, -{"C2H_DROP_PLD_CNT", 0xbc0, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_drop_pld_cnt_field_info), - c2h_drop_pld_cnt_field_info -}, -{"C2H_CMPT_FORMAT_0", 0xbc4, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_cmpt_format_0_field_info), - c2h_cmpt_format_0_field_info -}, -{"C2H_CMPT_FORMAT_1", 0xbc8, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_cmpt_format_1_field_info), - c2h_cmpt_format_1_field_info -}, -{"C2H_CMPT_FORMAT_2", 0xbcc, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_cmpt_format_2_field_info), - c2h_cmpt_format_2_field_info -}, -{"C2H_CMPT_FORMAT_3", 0xbd0, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_cmpt_format_3_field_info), - c2h_cmpt_format_3_field_info -}, -{"C2H_CMPT_FORMAT_4", 0xbd4, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_cmpt_format_4_field_info), - c2h_cmpt_format_4_field_info -}, -{"C2H_CMPT_FORMAT_5", 0xbd8, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_cmpt_format_5_field_info), - c2h_cmpt_format_5_field_info -}, -{"C2H_CMPT_FORMAT_6", 0xbdc, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_cmpt_format_6_field_info), - c2h_cmpt_format_6_field_info -}, -{"C2H_PFCH_CACHE_DEPTH", 0xbe0, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_pfch_cache_depth_field_info), - c2h_pfch_cache_depth_field_info -}, -{"C2H_WRB_COAL_BUF_DEPTH", 0xbe4, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_wrb_coal_buf_depth_field_info), - c2h_wrb_coal_buf_depth_field_info -}, -{"C2H_PFCH_CRDT", 0xbe8, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_pfch_crdt_field_info), - c2h_pfch_crdt_field_info -}, -{"C2H_STAT_HAS_CMPT_ACCEPTED", 0xbec, - 1, 0, 0, 0, - 1, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_stat_has_cmpt_accepted_field_info), - c2h_stat_has_cmpt_accepted_field_info -}, -{"C2H_STAT_HAS_PLD_ACCEPTED", 0xbf0, - 1, 0, 0, 0, - 1, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_stat_has_pld_accepted_field_info), - c2h_stat_has_pld_accepted_field_info -}, -{"C2H_PLD_PKT_ID", 0xbf4, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_pld_pkt_id_field_info), - c2h_pld_pkt_id_field_info -}, -{"C2H_PLD_PKT_ID_1", 0xbf8, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_pld_pkt_id_1_field_info), - c2h_pld_pkt_id_1_field_info -}, -{"C2H_DROP_PLD_CNT_1", 0xbfc, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_drop_pld_cnt_1_field_info), - c2h_drop_pld_cnt_1_field_info -}, -{"H2C_ERR_STAT", 0xe00, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(h2c_err_stat_field_info), - h2c_err_stat_field_info -}, -{"H2C_ERR_MASK", 0xe04, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(h2c_err_mask_field_info), - h2c_err_mask_field_info -}, -{"H2C_FIRST_ERR_QID", 0xe08, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(h2c_first_err_qid_field_info), - h2c_first_err_qid_field_info -}, -{"H2C_DBG_REG0", 0xe0c, - 1, 0, 0, 0, - 1, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(h2c_dbg_reg0_field_info), - h2c_dbg_reg0_field_info -}, -{"H2C_DBG_REG1", 0xe10, - 1, 0, 0, 0, - 1, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(h2c_dbg_reg1_field_info), - h2c_dbg_reg1_field_info -}, -{"H2C_DBG_REG2", 0xe14, - 1, 0, 0, 0, - 1, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(h2c_dbg_reg2_field_info), - h2c_dbg_reg2_field_info -}, -{"H2C_DBG_REG3", 0xe18, - 1, 0, 0, 0, - 1, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(h2c_dbg_reg3_field_info), - h2c_dbg_reg3_field_info -}, -{"H2C_DBG_REG4", 0xe1c, - 1, 0, 0, 0, - 1, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(h2c_dbg_reg4_field_info), - h2c_dbg_reg4_field_info -}, -{"H2C_FATAL_ERR_EN", 0xe20, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(h2c_fatal_err_en_field_info), - h2c_fatal_err_en_field_info -}, -{"H2C_REQ_THROT_PCIE", 0xe24, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(h2c_req_throt_pcie_field_info), - h2c_req_throt_pcie_field_info -}, -{"H2C_ALN_DBG_REG0", 0xe28, - 1, 0, 0, 0, - 1, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(h2c_aln_dbg_reg0_field_info), - h2c_aln_dbg_reg0_field_info -}, -{"H2C_REQ_THROT_AXIMM", 0xe2c, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(h2c_req_throt_aximm_field_info), - h2c_req_throt_aximm_field_info -}, -{"C2H_MM_CTL", 0x1004, - 1, 0, 0, 0, - 0, QDMA_MM_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_mm_ctl_field_info), - c2h_mm_ctl_field_info -}, -{"C2H_MM_STATUS", 0x1040, - 1, 0, 0, 0, - 0, QDMA_MM_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_mm_status_field_info), - c2h_mm_status_field_info -}, -{"C2H_MM_CMPL_DESC_CNT", 0x1048, - 1, 0, 0, 0, - 0, QDMA_MM_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_mm_cmpl_desc_cnt_field_info), - c2h_mm_cmpl_desc_cnt_field_info -}, -{"C2H_MM_ERR_CODE_ENABLE_MASK", 0x1054, - 1, 0, 0, 0, - 0, QDMA_MM_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_mm_err_code_enable_mask_field_info), - c2h_mm_err_code_enable_mask_field_info -}, -{"C2H_MM_ERR_CODE", 0x1058, - 1, 0, 0, 0, - 0, QDMA_MM_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_mm_err_code_field_info), - c2h_mm_err_code_field_info -}, -{"C2H_MM_ERR_INFO", 0x105c, - 1, 0, 0, 0, - 0, QDMA_MM_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_mm_err_info_field_info), - c2h_mm_err_info_field_info -}, -{"C2H_MM_PERF_MON_CTL", 0x10c0, - 1, 0, 0, 0, - 0, QDMA_MM_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_mm_perf_mon_ctl_field_info), - c2h_mm_perf_mon_ctl_field_info -}, -{"C2H_MM_PERF_MON_CYCLE_CNT0", 0x10c4, - 1, 0, 0, 0, - 0, QDMA_MM_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_mm_perf_mon_cycle_cnt0_field_info), - c2h_mm_perf_mon_cycle_cnt0_field_info -}, -{"C2H_MM_PERF_MON_CYCLE_CNT1", 0x10c8, - 1, 0, 0, 0, - 0, QDMA_MM_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_mm_perf_mon_cycle_cnt1_field_info), - c2h_mm_perf_mon_cycle_cnt1_field_info -}, -{"C2H_MM_PERF_MON_DATA_CNT0", 0x10cc, - 1, 0, 0, 0, - 0, QDMA_MM_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_mm_perf_mon_data_cnt0_field_info), - c2h_mm_perf_mon_data_cnt0_field_info -}, -{"C2H_MM_PERF_MON_DATA_CNT1", 0x10d0, - 1, 0, 0, 0, - 0, QDMA_MM_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_mm_perf_mon_data_cnt1_field_info), - c2h_mm_perf_mon_data_cnt1_field_info -}, -{"C2H_MM_DBG", 0x10e8, - 1, 0, 0, 0, - 0, QDMA_MM_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_mm_dbg_field_info), - c2h_mm_dbg_field_info -}, -{"H2C_MM_CTL", 0x1204, - 1, 0, 0, 0, - 0, QDMA_MM_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(h2c_mm_ctl_field_info), - h2c_mm_ctl_field_info -}, -{"H2C_MM_STATUS", 0x1240, - 1, 0, 0, 0, - 0, QDMA_MM_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(h2c_mm_status_field_info), - h2c_mm_status_field_info -}, -{"H2C_MM_CMPL_DESC_CNT", 0x1248, - 1, 0, 0, 0, - 0, QDMA_MM_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(h2c_mm_cmpl_desc_cnt_field_info), - h2c_mm_cmpl_desc_cnt_field_info -}, -{"H2C_MM_ERR_CODE_ENABLE_MASK", 0x1254, - 1, 0, 0, 0, - 0, QDMA_MM_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(h2c_mm_err_code_enable_mask_field_info), - h2c_mm_err_code_enable_mask_field_info -}, -{"H2C_MM_ERR_CODE", 0x1258, - 1, 0, 0, 0, - 0, QDMA_MM_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(h2c_mm_err_code_field_info), - h2c_mm_err_code_field_info -}, -{"H2C_MM_ERR_INFO", 0x125c, - 1, 0, 0, 0, - 0, QDMA_MM_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(h2c_mm_err_info_field_info), - h2c_mm_err_info_field_info -}, -{"H2C_MM_PERF_MON_CTL", 0x12c0, - 1, 0, 0, 0, - 0, QDMA_MM_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(h2c_mm_perf_mon_ctl_field_info), - h2c_mm_perf_mon_ctl_field_info -}, -{"H2C_MM_PERF_MON_CYCLE_CNT0", 0x12c4, - 1, 0, 0, 0, - 0, QDMA_MM_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(h2c_mm_perf_mon_cycle_cnt0_field_info), - h2c_mm_perf_mon_cycle_cnt0_field_info -}, -{"H2C_MM_PERF_MON_CYCLE_CNT1", 0x12c8, - 1, 0, 0, 0, - 0, QDMA_MM_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(h2c_mm_perf_mon_cycle_cnt1_field_info), - h2c_mm_perf_mon_cycle_cnt1_field_info -}, -{"H2C_MM_PERF_MON_DATA_CNT0", 0x12cc, - 1, 0, 0, 0, - 0, QDMA_MM_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(h2c_mm_perf_mon_data_cnt0_field_info), - h2c_mm_perf_mon_data_cnt0_field_info -}, -{"H2C_MM_PERF_MON_DATA_CNT1", 0x12d0, - 1, 0, 0, 0, - 0, QDMA_MM_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(h2c_mm_perf_mon_data_cnt1_field_info), - h2c_mm_perf_mon_data_cnt1_field_info -}, -{"H2C_MM_DBG", 0x12e8, - 1, 0, 0, 0, - 0, QDMA_MM_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(h2c_mm_dbg_field_info), - h2c_mm_dbg_field_info -}, -{"H2C_MM_DATA_THROTTLE", 0x12ec, - 1, 0, 0, 0, - 0, QDMA_MM_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(h2c_mm_data_throttle_field_info), - h2c_mm_data_throttle_field_info -}, -{"C2H_CRDT_COAL_CFG_1", 0x1400, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_crdt_coal_cfg_1_field_info), - c2h_crdt_coal_cfg_1_field_info -}, -{"C2H_CRDT_COAL_CFG_2", 0x1404, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_crdt_coal_cfg_2_field_info), - c2h_crdt_coal_cfg_2_field_info -}, -{"C2H_PFCH_BYP_QID", 0x1408, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_pfch_byp_qid_field_info), - c2h_pfch_byp_qid_field_info -}, -{"C2H_PFCH_BYP_TAG", 0x140c, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_pfch_byp_tag_field_info), - c2h_pfch_byp_tag_field_info -}, -{"C2H_WATER_MARK", 0x1410, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_water_mark_field_info), - c2h_water_mark_field_info -}, -{"C2H_NOTIFY_EMPTY", 0x1450, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_notify_empty_field_info), - c2h_notify_empty_field_info -}, -{"C2H_STAT_S_AXIS_C2H_ACCEPTED_1", 0x1454, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_stat_s_axis_c2h_accepted_1_field_info), - c2h_stat_s_axis_c2h_accepted_1_field_info -}, -{"C2H_STAT_S_AXIS_WRB_ACCEPTED_1", 0x1458, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_stat_s_axis_wrb_accepted_1_field_info), - c2h_stat_s_axis_wrb_accepted_1_field_info -}, -{"C2H_STAT_DESC_RSP_PKT_ACCEPTED_1", 0x145c, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_stat_desc_rsp_pkt_accepted_1_field_info), - c2h_stat_desc_rsp_pkt_accepted_1_field_info -}, -{"C2H_STAT_AXIS_PKG_CMP_1", 0x1460, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_stat_axis_pkg_cmp_1_field_info), - c2h_stat_axis_pkg_cmp_1_field_info -}, -{"C2H_STAT_S_AXIS_WRB_ACCEPTED_2", 0x1464, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_stat_s_axis_wrb_accepted_2_field_info), - c2h_stat_s_axis_wrb_accepted_2_field_info -}, -{"C2H_ST_PLD_FIFO_DEPTH", 0x1468, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_st_pld_fifo_depth_field_info), - c2h_st_pld_fifo_depth_field_info -}, -{"C2H_STAT_DBG_DMA_ENG_6", 0x146c, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_stat_dbg_dma_eng_6_field_info), - c2h_stat_dbg_dma_eng_6_field_info -}, -{"C2H_STAT_DBG_DMA_ENG_7", 0x1470, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_stat_dbg_dma_eng_7_field_info), - c2h_stat_dbg_dma_eng_7_field_info -}, -{"C2H_STAT_PCIE_CMP_1", 0x1474, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_stat_pcie_cmp_1_field_info), - c2h_stat_pcie_cmp_1_field_info -}, -{"C2H_PLD_FIFO_ALMOST_FULL", 0x1478, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_pld_fifo_almost_full_field_info), - c2h_pld_fifo_almost_full_field_info -}, -{"PFCH_CFG_3", 0x147c, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(pfch_cfg_3_field_info), - pfch_cfg_3_field_info -}, -{"CMPT_CFG_0", 0x1480, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(cmpt_cfg_0_field_info), - cmpt_cfg_0_field_info -}, -{"PFCH_CFG_4", 0x1484, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(pfch_cfg_4_field_info), - pfch_cfg_4_field_info -}, - -}; - -uint32_t eqdma_config_num_regs_get(void) -{ - return (sizeof(eqdma_config_regs)/ - sizeof(eqdma_config_regs[0])); -} - -struct xreg_info *eqdma_config_regs_get(void) -{ - return eqdma_config_regs; -} - diff --git a/QDMA/linux-kernel/driver/libqdma/qdma_access/qdma_access_common.c b/QDMA/linux-kernel/driver/libqdma/qdma_access/qdma_access_common.c deleted file mode 100755 index 6b468d574..000000000 --- a/QDMA/linux-kernel/driver/libqdma/qdma_access/qdma_access_common.c +++ /dev/null @@ -1,1514 +0,0 @@ -/* - * Copyright (c) 2019-2022, Xilinx, Inc. All rights reserved. - * Copyright (c) 2022, Advanced Micro Devices, Inc. All rights reserved. - * - * This source code is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * The full GNU General Public License is included in this distribution in - * the file called "COPYING". - */ - -#include "qdma_access_common.h" -#include "qdma_platform.h" -#include "qdma_soft_reg.h" -#include "qdma_soft_access.h" -#include "qdma_cpm4_access/qdma_cpm4_access.h" -#include "eqdma_soft_access.h" -#include "eqdma_cpm5_access/eqdma_cpm5_access.h" -#include "qdma_reg_dump.h" - -#ifdef ENABLE_WPP_TRACING -#include "qdma_access_common.tmh" -#endif - -/* qdma version info */ -#define RTL_BASE_VERSION 2 -#define RTL_PATCH_VERSION 3 - -/** - * enum qdma_ip - To hold ip type - */ -enum qdma_ip { - QDMA_OR_VERSAL_IP, - EQDMA_IP, - EQDMA_CPM5_IP -}; - - -/* - * hw_monitor_reg() - polling a register repeatly until - * (the register value & mask) == val or time is up - * - * return -QDMA_BUSY_IIMEOUT_ERR if register value didn't match, 0 other wise - */ -int hw_monitor_reg(void *dev_hndl, uint32_t reg, uint32_t mask, - uint32_t val, uint32_t interval_us, uint32_t timeout_us) -{ - int count; - uint32_t v; - - if (!interval_us) - interval_us = QDMA_REG_POLL_DFLT_INTERVAL_US; - if (!timeout_us) - timeout_us = QDMA_REG_POLL_DFLT_TIMEOUT_US; - - count = timeout_us / interval_us; - - do { - v = qdma_reg_read(dev_hndl, reg); - if ((v & mask) == val) - return QDMA_SUCCESS; - qdma_udelay(interval_us); - } while (--count); - - v = qdma_reg_read(dev_hndl, reg); - if ((v & mask) == val) - return QDMA_SUCCESS; - - qdma_log_error("%s: Reg read=%u Expected=%u, err:%d\n", - __func__, v, val, - -QDMA_ERR_HWACC_BUSY_TIMEOUT); - return -QDMA_ERR_HWACC_BUSY_TIMEOUT; -} - -/*****************************************************************************/ -/** - * qdma_get_rtl_version() - Function to get the rtl_version in - * string format - * - * @rtl_version: Vivado release ID - * - * Return: string - success and NULL on failure - *****************************************************************************/ -static const char *qdma_get_rtl_version(enum qdma_rtl_version rtl_version) -{ - switch (rtl_version) { - case QDMA_RTL_PATCH: - return "RTL Patch"; - case QDMA_RTL_BASE: - return "RTL Base"; - default: - qdma_log_error("%s: invalid rtl_version(%d), err:%d\n", - __func__, rtl_version, -QDMA_ERR_INV_PARAM); - return NULL; - } -} - -/*****************************************************************************/ -/** - * qdma_get_ip_type() - Function to get the ip type in string format - * - * @dev_hndl: device handle - * @is_vf: Whether PF or VF - * @ip_type: IP Type - * - * Return: string - success and NULL on failure - *****************************************************************************/ -static const char *qdma_get_ip_type(void *dev_hndl, uint8_t is_vf, - enum qdma_ip_type ip_type) -{ - uint32_t ip_version; - int rv = QDMA_SUCCESS; - - if (!dev_hndl) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - return NULL; - } - - switch (ip_type) { - case QDMA_VERSAL_HARD_IP: - return "Versal Hard IP"; - case QDMA_VERSAL_SOFT_IP: - return "Versal Soft IP"; - case QDMA_SOFT_IP: - return "QDMA Soft IP"; - case EQDMA_SOFT_IP: - rv = eqdma_get_ip_version(dev_hndl, is_vf, &ip_version); - if (rv != QDMA_SUCCESS) - return NULL; - - if (ip_version == EQDMA_IP_VERSION_4) - return "EQDMA4.0 Soft IP"; - else if (ip_version == EQDMA_IP_VERSION_5) - return "EQDMA5.0 Soft IP"; - - qdma_log_error("%s: invalid eqdma ip version(%d), err:%d\n", - __func__, ip_version, -QDMA_ERR_INV_PARAM); - return NULL; - default: - qdma_log_error("%s: invalid ip type(%d), err:%d\n", - __func__, ip_type, -QDMA_ERR_INV_PARAM); - return NULL; - } -} - -/*****************************************************************************/ -/** - * qdma_get_device_type() - Function to get the device type in - * string format - * - * @device_type: Device Type - * - * Return: string - success and NULL on failure - *****************************************************************************/ -static const char *qdma_get_device_type(enum qdma_device_type device_type) -{ - switch (device_type) { - case QDMA_DEVICE_SOFT: - return "Soft IP"; - case QDMA_DEVICE_VERSAL_CPM4: - return "Versal CPM4 Hard IP"; - case QDMA_DEVICE_VERSAL_CPM5: - return "Versal Hard CPM5"; - default: - qdma_log_error("%s: invalid device type(%d), err:%d\n", - __func__, device_type, -QDMA_ERR_INV_PARAM); - return NULL; - } -} - -/*****************************************************************************/ -/** - * qdma_get_vivado_release_id() - Function to get the vivado release id in - * string format - * - * @vivado_release_id: Vivado release ID - * - * Return: string - success and NULL on failure - *****************************************************************************/ -static const char *qdma_get_vivado_release_id( - enum qdma_vivado_release_id vivado_release_id) -{ - switch (vivado_release_id) { - case QDMA_VIVADO_2018_3: - return "vivado 2018.3"; - case QDMA_VIVADO_2019_1: - return "vivado 2019.1"; - case QDMA_VIVADO_2019_2: - return "vivado 2019.2"; - case QDMA_VIVADO_2020_1: - return "vivado 2020.1"; - case QDMA_VIVADO_2020_2: - return "vivado 2020.2"; - case QDMA_VIVADO_2021_1: - return "vivado 2021.1"; - case QDMA_VIVADO_2022_1: - return "vivado 2022.1"; - default: - qdma_log_error("%s: invalid vivado_release_id(%d), err:%d\n", - __func__, - vivado_release_id, - -QDMA_ERR_INV_PARAM); - return NULL; - } -} - - -void qdma_write_csr_values(void *dev_hndl, uint32_t reg_offst, - uint32_t idx, uint32_t cnt, const uint32_t *values) -{ - uint32_t index, reg_addr; - - for (index = idx; index < (idx + cnt); index++) { - reg_addr = reg_offst + (index * sizeof(uint32_t)); - qdma_reg_write(dev_hndl, reg_addr, values[index - idx]); - } -} - -void qdma_read_csr_values(void *dev_hndl, uint32_t reg_offst, - uint32_t idx, uint32_t cnt, uint32_t *values) -{ - uint32_t index, reg_addr; - - reg_addr = reg_offst + (idx * sizeof(uint32_t)); - for (index = 0; index < cnt; index++) { - values[index] = qdma_reg_read(dev_hndl, reg_addr + - (index * sizeof(uint32_t))); - } -} - -void qdma_fetch_version_details(void *dev_hndl, uint8_t is_vf, - uint32_t version_reg_val, struct qdma_hw_version_info *version_info) -{ - uint32_t rtl_version, vivado_release_id, ip_type, device_type; - const char *version_str; - - if (!dev_hndl) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - return; - } - - if (!is_vf) { - rtl_version = FIELD_GET(QDMA_GLBL2_RTL_VERSION_MASK, - version_reg_val); - vivado_release_id = - FIELD_GET(QDMA_GLBL2_VIVADO_RELEASE_MASK, - version_reg_val); - device_type = FIELD_GET(QDMA_GLBL2_DEVICE_ID_MASK, - version_reg_val); - ip_type = FIELD_GET(QDMA_GLBL2_VERSAL_IP_MASK, - version_reg_val); - } else { - rtl_version = - FIELD_GET(QDMA_GLBL2_VF_RTL_VERSION_MASK, - version_reg_val); - vivado_release_id = - FIELD_GET(QDMA_GLBL2_VF_VIVADO_RELEASE_MASK, - version_reg_val); - device_type = FIELD_GET(QDMA_GLBL2_VF_DEVICE_ID_MASK, - version_reg_val); - ip_type = - FIELD_GET(QDMA_GLBL2_VF_VERSAL_IP_MASK, - version_reg_val); - } - - switch (rtl_version) { - case 0: - version_info->rtl_version = QDMA_RTL_BASE; - break; - case 1: - version_info->rtl_version = QDMA_RTL_PATCH; - break; - default: - version_info->rtl_version = QDMA_RTL_NONE; - break; - } - - version_str = qdma_get_rtl_version(version_info->rtl_version); - if (version_str != NULL) - qdma_strncpy(version_info->qdma_rtl_version_str, - version_str, - QDMA_HW_VERSION_STRING_LEN); - - switch (device_type) { - case 0: - version_info->device_type = QDMA_DEVICE_SOFT; - break; - case 1: - version_info->device_type = QDMA_DEVICE_VERSAL_CPM4; - break; - case 2: - version_info->device_type = QDMA_DEVICE_VERSAL_CPM5; - break; - default: - version_info->device_type = QDMA_DEVICE_NONE; - break; - } - - version_str = qdma_get_device_type(version_info->device_type); - if (version_str != NULL) - qdma_strncpy(version_info->qdma_device_type_str, - version_str, - QDMA_HW_VERSION_STRING_LEN); - - - if (version_info->device_type == QDMA_DEVICE_SOFT) { - switch (ip_type) { - case 0: - version_info->ip_type = QDMA_SOFT_IP; - break; - case 1: - case 2: - /* For QDMA4.0 and QDMA5.0, HW design and - * register map is same except some - * performance optimizations - */ - version_info->ip_type = EQDMA_SOFT_IP; - break; - default: - version_info->ip_type = QDMA_NONE_IP; - } - } else { - switch (ip_type) { - case 0: - version_info->ip_type = QDMA_VERSAL_HARD_IP; - break; - case 1: - version_info->ip_type = QDMA_VERSAL_SOFT_IP; - break; - default: - version_info->ip_type = QDMA_NONE_IP; - } - } - - version_str = qdma_get_ip_type(dev_hndl, is_vf, version_info->ip_type); - if (version_str != NULL) - qdma_strncpy(version_info->qdma_ip_type_str, - version_str, - QDMA_HW_VERSION_STRING_LEN); - - if (version_info->ip_type == QDMA_SOFT_IP) { - switch (vivado_release_id) { - case 0: - version_info->vivado_release = QDMA_VIVADO_2018_3; - break; - case 1: - version_info->vivado_release = QDMA_VIVADO_2019_1; - break; - case 2: - version_info->vivado_release = QDMA_VIVADO_2019_2; - break; - default: - version_info->vivado_release = QDMA_VIVADO_NONE; - break; - } - } else if (version_info->ip_type == EQDMA_SOFT_IP) { - switch (vivado_release_id) { - case 0: - version_info->vivado_release = QDMA_VIVADO_2020_1; - break; - case 1: - version_info->vivado_release = QDMA_VIVADO_2020_2; - break; - case 2: - version_info->vivado_release = QDMA_VIVADO_2022_1; - break; - default: - version_info->vivado_release = QDMA_VIVADO_NONE; - break; - } - } else if (version_info->device_type == QDMA_DEVICE_VERSAL_CPM5) { - switch (vivado_release_id) { - case 0: - version_info->vivado_release = QDMA_VIVADO_2021_1; - break; - case 1: - version_info->vivado_release = QDMA_VIVADO_2022_1; - break; - default: - version_info->vivado_release = QDMA_VIVADO_NONE; - break; - } - } else { /* Versal case */ - switch (vivado_release_id) { - case 0: - version_info->vivado_release = QDMA_VIVADO_2019_2; - break; - default: - version_info->vivado_release = QDMA_VIVADO_NONE; - break; - } - } - - version_str = qdma_get_vivado_release_id( - version_info->vivado_release); - if (version_str != NULL) - qdma_strncpy(version_info->qdma_vivado_release_id_str, - version_str, - QDMA_HW_VERSION_STRING_LEN); -} - - -/* - * dump_reg() - Helper function to dump register value into string - * - * return len - length of the string copied into buffer - */ -int dump_reg(char *buf, int buf_sz, uint32_t raddr, - const char *rname, uint32_t rval) -{ - /* length of the line should be minimum 80 chars. - * If below print pattern is changed, check for - * new buffer size requirement - */ - if (buf_sz < DEBGFS_LINE_SZ) { - qdma_log_error("%s: buf_sz(%d) < expected(%d): err: %d\n", - __func__, - buf_sz, DEBGFS_LINE_SZ, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - return QDMA_SNPRINTF_S(buf, buf_sz, DEBGFS_LINE_SZ, - "[%#7x] %-47s %#-10x %u\n", - raddr, rname, rval, rval); - -} - -void qdma_memset(void *to, uint8_t val, uint32_t size) -{ - uint32_t i; - uint8_t *_to = (uint8_t *)to; - - for (i = 0; i < size; i++) - _to[i] = val; -} - -/*****************************************************************************/ -/** - * qdma_queue_cmpt_cidx_read() - function to read the CMPT CIDX register - * - * @dev_hndl: device handle - * @is_vf: Whether PF or VF - * @qid: Queue id relative to the PF/VF calling this API - * @reg_info: pointer to array to hold the values read - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -static int qdma_queue_cmpt_cidx_read(void *dev_hndl, uint8_t is_vf, - uint16_t qid, struct qdma_q_cmpt_cidx_reg_info *reg_info) -{ - uint32_t reg_val = 0; - uint32_t reg_addr = (is_vf) ? QDMA_OFFSET_VF_DMAP_SEL_CMPT_CIDX : - QDMA_OFFSET_DMAP_SEL_CMPT_CIDX; - - if (!dev_hndl) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - if (!reg_info) { - qdma_log_error("%s: reg_info is NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - - reg_addr += qid * QDMA_CMPT_CIDX_STEP; - - reg_val = qdma_reg_read(dev_hndl, reg_addr); - - reg_info->wrb_cidx = - FIELD_GET(QDMA_DMAP_SEL_CMPT_WRB_CIDX_MASK, reg_val); - reg_info->counter_idx = - (uint8_t)(FIELD_GET(QDMA_DMAP_SEL_CMPT_CNT_THRESH_MASK, - reg_val)); - reg_info->wrb_en = - (uint8_t)(FIELD_GET(QDMA_DMAP_SEL_CMPT_STS_DESC_EN_MASK, - reg_val)); - reg_info->irq_en = - (uint8_t)(FIELD_GET(QDMA_DMAP_SEL_CMPT_IRQ_EN_MASK, reg_val)); - reg_info->timer_idx = - (uint8_t)(FIELD_GET(QDMA_DMAP_SEL_CMPT_TMR_CNT_MASK, reg_val)); - reg_info->trig_mode = - (uint8_t)(FIELD_GET(QDMA_DMAP_SEL_CMPT_TRG_MODE_MASK, reg_val)); - - return QDMA_SUCCESS; -} - - -/*****************************************************************************/ -/** - * qdma_initiate_flr() - function to initiate Function Level Reset - * - * @dev_hndl: device handle - * @is_vf: Whether PF or VF - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -static int qdma_initiate_flr(void *dev_hndl, uint8_t is_vf) -{ - uint32_t reg_addr = (is_vf) ? QDMA_OFFSET_VF_REG_FLR_STATUS : - QDMA_OFFSET_PF_REG_FLR_STATUS; - - if (!dev_hndl) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - qdma_reg_write(dev_hndl, reg_addr, 1); - - return QDMA_SUCCESS; -} - -/*****************************************************************************/ -/** - * qdma_is_flr_done() - function to check whether the FLR is done or not - * - * @dev_hndl: device handle - * @is_vf: Whether PF or VF - * @done: if FLR process completed , done is 1 else 0. - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -static int qdma_is_flr_done(void *dev_hndl, uint8_t is_vf, uint8_t *done) -{ - int rv; - uint32_t reg_addr = (is_vf) ? QDMA_OFFSET_VF_REG_FLR_STATUS : - QDMA_OFFSET_PF_REG_FLR_STATUS; - - if (!dev_hndl) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - if (!done) { - qdma_log_error("%s: done is NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - /* wait for it to become zero */ - rv = hw_monitor_reg(dev_hndl, reg_addr, QDMA_FLR_STATUS_MASK, - 0, 5 * QDMA_REG_POLL_DFLT_INTERVAL_US, - QDMA_REG_POLL_DFLT_TIMEOUT_US); - if (rv < 0) - *done = 0; - else - *done = 1; - - return QDMA_SUCCESS; -} - -/*****************************************************************************/ -/** - * qdma_is_config_bar() - function for the config bar verification - * - * @dev_hndl: device handle - * @is_vf: Whether PF or VF - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -static int qdma_is_config_bar(void *dev_hndl, uint8_t is_vf, enum qdma_ip *ip) -{ - uint32_t reg_val = 0; - uint32_t reg_addr = (is_vf) ? QDMA_OFFSET_VF_VERSION : - QDMA_OFFSET_CONFIG_BLOCK_ID; - - if (!dev_hndl) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - reg_val = qdma_reg_read(dev_hndl, reg_addr); - - /** TODO: Version register for VFs is 0x5014 for EQDMA and - * 0x1014 for QDMA/Versal. First time reading 0x5014 for - * all the device and based on the upper 16 bits value - * (i.e. 0x1fd3), finding out whether its EQDMA or QDMA/Versal - * for EQDMA VFs. - * Need to modify this logic once the hardware team - * comes up with a common register for VFs - */ - if (is_vf) { - if (FIELD_GET(QDMA_GLBL2_VF_UNIQUE_ID_MASK, reg_val) - != QDMA_MAGIC_NUMBER) { - /* Its either QDMA or Versal */ - -#ifdef EQDMA_CPM5_VF_GT_256Q_SUPPORTED - *ip = EQDMA_CPM5_IP; - reg_addr = EQDMA_CPM5_OFFSET_VF_VERSION; -#else - *ip = EQDMA_IP; - reg_addr = EQDMA_OFFSET_VF_VERSION; -#endif - reg_val = qdma_reg_read(dev_hndl, reg_addr); - } else { - *ip = QDMA_OR_VERSAL_IP; - return QDMA_SUCCESS; - } - } - - if (FIELD_GET(QDMA_CONFIG_BLOCK_ID_MASK, reg_val) - != QDMA_MAGIC_NUMBER) { - qdma_log_error("%s: Invalid config bar, err:%d\n", - __func__, - -QDMA_ERR_HWACC_INV_CONFIG_BAR); - return -QDMA_ERR_HWACC_INV_CONFIG_BAR; - } - - return QDMA_SUCCESS; -} - -int qdma_acc_reg_dump_buf_len(void *dev_hndl, enum qdma_ip_type ip_type, - enum qdma_device_type device_type, int *buflen) -{ - uint32_t len = 0; - int rv = 0; - - *buflen = 0; - - if (!dev_hndl) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - - return -QDMA_ERR_INV_PARAM; - } - - switch (ip_type) { - case QDMA_SOFT_IP: - len = qdma_soft_reg_dump_buf_len(); - break; - case QDMA_VERSAL_HARD_IP: - if (device_type == QDMA_DEVICE_VERSAL_CPM4) - len = qdma_cpm4_reg_dump_buf_len(); - else if (device_type == QDMA_DEVICE_VERSAL_CPM5) - len = eqdma_cpm5_reg_dump_buf_len(); - else { - qdma_log_error("%s: Invalid device type, err = %d", - __func__, -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - break; - case EQDMA_SOFT_IP: - len = eqdma_reg_dump_buf_len(); - break; - default: - qdma_log_error("%s: Invalid version number, err = %d", - __func__, -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - *buflen = (int)len; - return rv; -} - -int qdma_acc_reg_info_len(void *dev_hndl, enum qdma_ip_type ip_type, - enum qdma_device_type device_type, int *buflen, int *num_regs) -{ - uint32_t len = 0; - int rv = 0; - - if (!dev_hndl) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - - return -QDMA_ERR_INV_PARAM; - } - - if (!buflen) { - qdma_log_error("%s: buflen is NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - - return -QDMA_ERR_INV_PARAM; - } - - if (!num_regs) { - qdma_log_error("%s: num_regs is NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - - return -QDMA_ERR_INV_PARAM; - } - - *buflen = 0; - - switch (ip_type) { - case QDMA_SOFT_IP: - len = 0; - *num_regs = 0; - break; - case QDMA_VERSAL_HARD_IP: - if (device_type == QDMA_DEVICE_VERSAL_CPM4) { - len = qdma_cpm4_reg_dump_buf_len(); - *num_regs = (int)((len / REG_DUMP_SIZE_PER_LINE) - 1); - } else if (device_type == QDMA_DEVICE_VERSAL_CPM5) { - len = eqdma_cpm5_reg_dump_buf_len(); - *num_regs = (int)((len / REG_DUMP_SIZE_PER_LINE) - 1); - } else { - qdma_log_error("%s: Invalid device type, err = %d", - __func__, -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - break; - case EQDMA_SOFT_IP: - len = eqdma_reg_dump_buf_len(); - *num_regs = (int)((len / REG_DUMP_SIZE_PER_LINE) - 1); - break; - default: - qdma_log_error("%s: Invalid version number, err = %d", - __func__, -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - *buflen = (int)len; - return rv; -} - -int qdma_acc_context_buf_len(void *dev_hndl, enum qdma_ip_type ip_type, - enum qdma_device_type device_type, uint8_t st, - enum qdma_dev_q_type q_type, uint32_t *buflen) -{ - int rv = 0; - - *buflen = 0; - if (!dev_hndl) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - - return -QDMA_ERR_INV_PARAM; - } - - switch (ip_type) { - case QDMA_SOFT_IP: - rv = qdma_soft_context_buf_len(st, q_type, buflen); - break; - case QDMA_VERSAL_HARD_IP: - if (device_type == QDMA_DEVICE_VERSAL_CPM4) - rv = qdma_cpm4_context_buf_len(st, q_type, buflen); - else if (device_type == QDMA_DEVICE_VERSAL_CPM5) - rv = eqdma_cpm5_context_buf_len(st, q_type, buflen); - else { - qdma_log_error("%s: Invalid device type, err = %d", - __func__, -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - break; - case EQDMA_SOFT_IP: - rv = eqdma_context_buf_len(st, q_type, buflen); - break; - default: - qdma_log_error("%s: Invalid version number, err = %d", - __func__, -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - return rv; -} - -int qdma_acc_get_num_config_regs(void *dev_hndl, enum qdma_ip_type ip_type, - enum qdma_device_type device_type, uint32_t *num_regs) -{ - int rv = 0; - - *num_regs = 0; - if (!dev_hndl) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - - return -QDMA_ERR_INV_PARAM; - } - - switch (ip_type) { - case QDMA_SOFT_IP: - rv = qdma_get_config_num_regs(); - break; - case QDMA_VERSAL_HARD_IP: - if (device_type == QDMA_DEVICE_VERSAL_CPM4) - rv = qdma_cpm4_get_config_num_regs(); - else if (device_type == QDMA_DEVICE_VERSAL_CPM5) - rv = eqdma_cpm5_get_config_num_regs(); - else { - qdma_log_error("%s: Invalid device type, err = %d", - __func__, -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - break; - case EQDMA_SOFT_IP: - rv = eqdma_get_config_num_regs(); - break; - default: - qdma_log_error("%s: Invalid version number, err = %d", - __func__, -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - *num_regs = rv; - - return 0; -} - -/*****************************************************************************/ -/** - * qdma_acc_get_config_regs() - Function to get qdma config registers. - * - * @dev_hndl: device handle - * @is_vf: Whether PF or VF - * @ip_type: QDMA IP Type - * @device_type:QDMA DEVICE Type - * @reg_data: pointer to register data to be filled - * - * Return: Length up-till the buffer is filled -success and < 0 - failure - *****************************************************************************/ -int qdma_acc_get_config_regs(void *dev_hndl, uint8_t is_vf, - enum qdma_ip_type ip_type, enum qdma_device_type device_type, - uint32_t *reg_data) -{ - struct xreg_info *reg_info; - uint32_t count = 0; - uint32_t num_regs; - int rv = 0; - - if (!dev_hndl) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - if (is_vf) { - qdma_log_error("%s: Get Config regs not valid for VF, err:%d\n", - __func__, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - if (reg_data == NULL) { - qdma_log_error("%s: reg_data is NULL, err:%d\n", - __func__, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - switch (ip_type) { - case QDMA_SOFT_IP: - num_regs = qdma_get_config_num_regs(); - reg_info = qdma_get_config_regs(); - break; - case QDMA_VERSAL_HARD_IP: - if (device_type == QDMA_DEVICE_VERSAL_CPM4) { - num_regs = qdma_cpm4_get_config_num_regs(); - reg_info = qdma_cpm4_get_config_regs(); - } else if (device_type == QDMA_DEVICE_VERSAL_CPM5) { - num_regs = eqdma_cpm5_get_config_num_regs(); - reg_info = eqdma_cpm5_get_config_regs(); - } else { - qdma_log_error("%s: Invalid device type, err = %d", - __func__, -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - break; - case EQDMA_SOFT_IP: - num_regs = eqdma_get_config_num_regs(); - reg_info = eqdma_get_config_regs(); - break; - default: - qdma_log_error("%s: Invalid version number, err = %d", - __func__, -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - for (count = 0; count < num_regs - 1; count++) { - reg_data[count] = qdma_reg_read(dev_hndl, - reg_info[count].addr); - } - - return rv; -} - - -/*****************************************************************************/ -/** - * qdma_acc_dump_config_regs() - Function to get qdma config register dump in a - * buffer - * - * @dev_hndl: device handle - * @is_vf: Whether PF or VF - * @ip_type: QDMA IP Type - * @device_type:QDMA DEVICE Type - * @buf : pointer to buffer to be filled - * @buflen : Length of the buffer - * - * Return: Length up-till the buffer is filled -success and < 0 - failure - *****************************************************************************/ -int qdma_acc_dump_config_regs(void *dev_hndl, uint8_t is_vf, - enum qdma_ip_type ip_type, enum qdma_device_type device_type, - char *buf, uint32_t buflen) -{ - int rv = 0; - - switch (ip_type) { - case QDMA_SOFT_IP: - rv = qdma_soft_dump_config_regs(dev_hndl, is_vf, - buf, buflen); - break; - case QDMA_VERSAL_HARD_IP: - if (device_type == QDMA_DEVICE_VERSAL_CPM4) - rv = qdma_cpm4_dump_config_regs(dev_hndl, is_vf, - buf, buflen); - else if (device_type == QDMA_DEVICE_VERSAL_CPM5) - rv = eqdma_cpm5_dump_config_regs(dev_hndl, is_vf, - buf, buflen); - else { - qdma_log_error("%s: Invalid device type, err = %d", - __func__, -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - break; - case EQDMA_SOFT_IP: - rv = eqdma_dump_config_regs(dev_hndl, is_vf, - buf, buflen); - break; - default: - qdma_log_error("%s: Invalid version number, err = %d", - __func__, -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - return rv; -} - -/*****************************************************************************/ -/** - * qdma_acc_dump_reg_info() - Function to dump fileds in - * a specified register. - * - * @dev_hndl: device handle - * @ip_type: QDMA IP Type - * @device_type:QDMA DEVICE Type - * @buf : pointer to buffer to be filled - * @buflen : Length of the buffer - * - * Return: Length up-till the buffer is filled -success and < 0 - failure - *****************************************************************************/ -int qdma_acc_dump_reg_info(void *dev_hndl, enum qdma_ip_type ip_type, - enum qdma_device_type device_type, uint32_t reg_addr, - uint32_t num_regs, char *buf, uint32_t buflen) -{ - int rv = 0; - - if (!dev_hndl) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - if (!buf || !buflen) { - qdma_log_error("%s: Invalid input buffer, err = %d", - __func__, -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - switch (ip_type) { - case QDMA_SOFT_IP: - QDMA_SNPRINTF_S(buf, buflen, DEBGFS_LINE_SZ, - "QDMA reg field info not supported for QDMA_SOFT_IP\n"); - break; - case QDMA_VERSAL_HARD_IP: - if (device_type == QDMA_DEVICE_VERSAL_CPM4) - rv = qdma_cpm4_dump_reg_info(dev_hndl, reg_addr, - num_regs, buf, buflen); - else if (device_type == QDMA_DEVICE_VERSAL_CPM5) - rv = eqdma_cpm5_dump_reg_info(dev_hndl, reg_addr, - num_regs, buf, buflen); - else { - qdma_log_error("%s: Invalid device type, err = %d", - __func__, -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - break; - case EQDMA_SOFT_IP: - rv = eqdma_dump_reg_info(dev_hndl, reg_addr, - num_regs, buf, buflen); - break; - default: - qdma_log_error("%s: Invalid version number, err = %d", - __func__, -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - return rv; -} - -/*****************************************************************************/ -/** - * qdma_acc_dump_queue_context() - Function to get qdma queue context dump in a - * buffer - * - * @dev_hndl: device handle - * @ip_type: QDMA IP Type - * @device_type:QDMA DEVICE Type - * @st: Queue Mode (ST or MM) - * @q_type: Queue Type - * @ctxt_data: Context Data - * @buf : pointer to buffer to be filled - * @buflen : Length of the buffer - * - * Return: Length up-till the buffer is filled -success and < 0 - failure - *****************************************************************************/ -int qdma_acc_dump_queue_context(void *dev_hndl, - enum qdma_ip_type ip_type, - enum qdma_device_type device_type, - uint8_t st, - enum qdma_dev_q_type q_type, - struct qdma_descq_context *ctxt_data, - char *buf, uint32_t buflen) -{ - int rv = 0; - - switch (ip_type) { - case QDMA_SOFT_IP: - rv = qdma_soft_dump_queue_context(dev_hndl, - st, q_type, ctxt_data, buf, buflen); - break; - case QDMA_VERSAL_HARD_IP: - if (device_type == QDMA_DEVICE_VERSAL_CPM4) - rv = qdma_cpm4_dump_queue_context(dev_hndl, - st, q_type, ctxt_data, buf, buflen); - else if (device_type == QDMA_DEVICE_VERSAL_CPM5) - rv = eqdma_cpm5_dump_queue_context(dev_hndl, - st, q_type, ctxt_data, buf, buflen); - else { - qdma_log_error("%s: Invalid device type, err = %d", - __func__, -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - break; - case EQDMA_SOFT_IP: - rv = eqdma_dump_queue_context(dev_hndl, - st, q_type, ctxt_data, buf, buflen); - break; - default: - qdma_log_error("%s: Invalid version number, err = %d", - __func__, -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - return rv; -} - -/*****************************************************************************/ -/** - * qdma_acc_read_dump_queue_context() - Function to read and dump the queue - * context in the user-provided buffer. This API is valid only for PF and - * should not be used for VFs. For VF's use qdma_dump_queue_context() API - * after reading the context through mailbox. - * - * @dev_hndl: device handle - * @ip_type: QDMA IP type - * @device_type:QDMA DEVICE Type - * @hw_qid: queue id - * @st: Queue Mode(ST or MM) - * @q_type: Queue type(H2C/C2H/CMPT)* - * @buf : pointer to buffer to be filled - * @buflen : Length of the buffer - * - * Return: Length up-till the buffer is filled -success and < 0 - failure - *****************************************************************************/ -int qdma_acc_read_dump_queue_context(void *dev_hndl, - enum qdma_ip_type ip_type, - enum qdma_device_type device_type, - uint16_t func_id, - uint16_t qid_hw, - uint8_t st, - enum qdma_dev_q_type q_type, - char *buf, uint32_t buflen) -{ - int rv = QDMA_SUCCESS; - - switch (ip_type) { - case QDMA_SOFT_IP: - rv = qdma_soft_read_dump_queue_context(dev_hndl, func_id, - qid_hw, st, q_type, buf, buflen); - break; - case QDMA_VERSAL_HARD_IP: - if (device_type == QDMA_DEVICE_VERSAL_CPM4) - rv = qdma_cpm4_read_dump_queue_context(dev_hndl, - func_id, qid_hw, st, q_type, buf, buflen); - else if (device_type == QDMA_DEVICE_VERSAL_CPM5) - rv = eqdma_cpm5_read_dump_queue_context(dev_hndl, - func_id, qid_hw, st, q_type, buf, buflen); - else { - qdma_log_error("%s: Invalid device type, err = %d", - __func__, -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - break; - case EQDMA_SOFT_IP: - rv = eqdma_read_dump_queue_context(dev_hndl, func_id, - qid_hw, st, q_type, buf, buflen); - break; - default: - qdma_log_error("%s: Invalid version number, err = %d", - __func__, -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - return rv; -} - -/*****************************************************************************/ -/** - * qdma_acc_dump_config_reg_list() - Dump the registers - * - * @dev_hndl: device handle - * @ip_type: QDMA ip type - * @num_regs : Max registers to read - * @reg_list : array of reg addr and reg values - * @buf : pointer to buffer to be filled - * @buflen : Length of the buffer - * - * Return: returns the platform specific error code - *****************************************************************************/ -int qdma_acc_dump_config_reg_list(void *dev_hndl, - enum qdma_ip_type ip_type, - enum qdma_device_type device_type, - uint32_t num_regs, - struct qdma_reg_data *reg_list, - char *buf, uint32_t buflen) -{ - int rv = 0; - - switch (ip_type) { - case QDMA_SOFT_IP: - rv = qdma_soft_dump_config_reg_list(dev_hndl, - num_regs, - reg_list, buf, buflen); - break; - case QDMA_VERSAL_HARD_IP: - if (device_type == QDMA_DEVICE_VERSAL_CPM4) - rv = qdma_cpm4_dump_config_reg_list(dev_hndl, - num_regs, - reg_list, buf, buflen); - else if (device_type == QDMA_DEVICE_VERSAL_CPM5) - rv = eqdma_cpm5_dump_config_reg_list(dev_hndl, - num_regs, - reg_list, buf, buflen); - else { - qdma_log_error("%s: Invalid device type, err = %d", - __func__, -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - break; - case EQDMA_SOFT_IP: - rv = eqdma_dump_config_reg_list(dev_hndl, - num_regs, - reg_list, buf, buflen); - break; - default: - qdma_log_error("%s: Invalid version number, err = %d", - __func__, -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - return rv; -} - - -/*****************************************************************************/ -/** - * qdma_get_function_number() - Function to get the function number - * - * @dev_hndl: device handle - * @func_id: pointer to hold the function id - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -static int qdma_get_function_number(void *dev_hndl, uint16_t *func_id) -{ - if (!dev_hndl || !func_id) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - *func_id = (uint8_t)qdma_reg_read(dev_hndl, - QDMA_OFFSET_GLBL2_CHANNEL_FUNC_RET); - - return QDMA_SUCCESS; -} - - -/*****************************************************************************/ -/** - * qdma_hw_error_intr_setup() - Function to set up the qdma error - * interrupt - * - * @dev_hndl: device handle - * @func_id: Function id - * @err_intr_index: Interrupt vector - * @rearm: rearm or not - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -static int qdma_hw_error_intr_setup(void *dev_hndl, uint16_t func_id, - uint8_t err_intr_index) -{ - uint32_t reg_val = 0; - - if (!dev_hndl) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - reg_val = - FIELD_SET(QDMA_GLBL_ERR_FUNC_MASK, func_id) | - FIELD_SET(QDMA_GLBL_ERR_VEC_MASK, err_intr_index); - - qdma_reg_write(dev_hndl, QDMA_OFFSET_GLBL_ERR_INT, reg_val); - - return QDMA_SUCCESS; -} - -/*****************************************************************************/ -/** - * qdma_hw_error_intr_rearm() - Function to re-arm the error interrupt - * - * @dev_hndl: device handle - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -static int qdma_hw_error_intr_rearm(void *dev_hndl) -{ - uint32_t reg_val = 0; - - if (!dev_hndl) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - reg_val = qdma_reg_read(dev_hndl, QDMA_OFFSET_GLBL_ERR_INT); - reg_val |= FIELD_SET(QDMA_GLBL_ERR_ARM_MASK, 1); - - qdma_reg_write(dev_hndl, QDMA_OFFSET_GLBL_ERR_INT, reg_val); - - return QDMA_SUCCESS; -} - -/*****************************************************************************/ -/** - * qdma_get_error_code() - function to get the qdma access mapped - * error code - * - * @acc_err_code: qdma access error code - * - * Return: returns the platform specific error code - *****************************************************************************/ -int qdma_get_error_code(int acc_err_code) -{ - return qdma_get_err_code(acc_err_code); -} - -int qdma_hw_access_init(void *dev_hndl, uint8_t is_vf, - struct qdma_hw_access *hw_access) -{ - int rv = QDMA_SUCCESS; - enum qdma_ip ip = EQDMA_IP; - - struct qdma_hw_version_info version_info; - - if (!dev_hndl) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - if (!hw_access) { - qdma_log_error("%s: hw_access is NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - rv = qdma_is_config_bar(dev_hndl, is_vf, &ip); - if (rv != QDMA_SUCCESS) { - qdma_log_error("%s: config bar passed is INVALID, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - return rv; - } - - qdma_memset(hw_access, 0, sizeof(struct qdma_hw_access)); - - if (ip == EQDMA_IP) - hw_access->qdma_get_version = &eqdma_get_version; - else if (ip == EQDMA_CPM5_IP) - hw_access->qdma_get_version = &eqdma_cpm5_get_version; - else - hw_access->qdma_get_version = &qdma_get_version; - - hw_access->qdma_init_ctxt_memory = &qdma_init_ctxt_memory; - hw_access->qdma_fmap_conf = &qdma_fmap_conf; - hw_access->qdma_sw_ctx_conf = &qdma_sw_ctx_conf; - hw_access->qdma_pfetch_ctx_conf = &qdma_pfetch_ctx_conf; - hw_access->qdma_cmpt_ctx_conf = &qdma_cmpt_ctx_conf; - hw_access->qdma_hw_ctx_conf = &qdma_hw_ctx_conf; - hw_access->qdma_credit_ctx_conf = &qdma_credit_ctx_conf; - hw_access->qdma_indirect_intr_ctx_conf = &qdma_indirect_intr_ctx_conf; - hw_access->qdma_set_default_global_csr = &qdma_set_default_global_csr; - hw_access->qdma_global_csr_conf = &qdma_global_csr_conf; - hw_access->qdma_global_writeback_interval_conf = - &qdma_global_writeback_interval_conf; - hw_access->qdma_queue_pidx_update = &qdma_queue_pidx_update; - hw_access->qdma_queue_cmpt_cidx_read = &qdma_queue_cmpt_cidx_read; - hw_access->qdma_queue_cmpt_cidx_update = &qdma_queue_cmpt_cidx_update; - hw_access->qdma_queue_intr_cidx_update = &qdma_queue_intr_cidx_update; - hw_access->qdma_mm_channel_conf = &qdma_mm_channel_conf; - hw_access->qdma_get_user_bar = &qdma_get_user_bar; - hw_access->qdma_get_function_number = &qdma_get_function_number; - hw_access->qdma_get_device_attributes = &qdma_get_device_attributes; - hw_access->qdma_hw_error_intr_setup = &qdma_hw_error_intr_setup; - hw_access->qdma_hw_error_intr_rearm = &qdma_hw_error_intr_rearm; - hw_access->qdma_hw_error_enable = &qdma_hw_error_enable; - hw_access->qdma_hw_get_error_name = &qdma_hw_get_error_name; - hw_access->qdma_hw_error_process = &qdma_hw_error_process; - hw_access->qdma_dump_config_regs = &qdma_soft_dump_config_regs; - hw_access->qdma_dump_queue_context = &qdma_soft_dump_queue_context; - hw_access->qdma_read_dump_queue_context = - &qdma_soft_read_dump_queue_context; - hw_access->qdma_dump_intr_context = &qdma_dump_intr_context; - hw_access->qdma_is_legacy_intr_pend = &qdma_is_legacy_intr_pend; - hw_access->qdma_clear_pend_legacy_intr = &qdma_clear_pend_legacy_intr; - hw_access->qdma_legacy_intr_conf = &qdma_legacy_intr_conf; - hw_access->qdma_initiate_flr = &qdma_initiate_flr; - hw_access->qdma_is_flr_done = &qdma_is_flr_done; - hw_access->qdma_get_error_code = &qdma_get_error_code; - hw_access->qdma_read_reg_list = &qdma_read_reg_list; - hw_access->qdma_dump_config_reg_list = - &qdma_soft_dump_config_reg_list; - hw_access->qdma_dump_reg_info = &qdma_dump_reg_info; - hw_access->mbox_base_pf = QDMA_OFFSET_MBOX_BASE_PF; - hw_access->mbox_base_vf = QDMA_OFFSET_MBOX_BASE_VF; - hw_access->qdma_max_errors = QDMA_ERRS_ALL; - - rv = hw_access->qdma_get_version(dev_hndl, is_vf, &version_info); - if (rv != QDMA_SUCCESS) - return rv; - - qdma_log_info("Device Type: %s\n", - qdma_get_device_type(version_info.device_type)); - - qdma_log_info("IP Type: %s\n", - qdma_get_ip_type(dev_hndl, is_vf, version_info.ip_type)); - - qdma_log_info("Vivado Release: %s\n", - qdma_get_vivado_release_id(version_info.vivado_release)); - - if (version_info.ip_type == QDMA_VERSAL_HARD_IP && - version_info.device_type == QDMA_DEVICE_VERSAL_CPM4) { - hw_access->qdma_init_ctxt_memory = - &qdma_cpm4_init_ctxt_memory; - hw_access->qdma_qid2vec_conf = &qdma_cpm4_qid2vec_conf; - hw_access->qdma_fmap_conf = &qdma_cpm4_fmap_conf; - hw_access->qdma_sw_ctx_conf = &qdma_cpm4_sw_ctx_conf; - hw_access->qdma_pfetch_ctx_conf = - &qdma_cpm4_pfetch_ctx_conf; - hw_access->qdma_cmpt_ctx_conf = &qdma_cpm4_cmpt_ctx_conf; - hw_access->qdma_hw_ctx_conf = &qdma_cpm4_hw_ctx_conf; - hw_access->qdma_credit_ctx_conf = - &qdma_cpm4_credit_ctx_conf; - hw_access->qdma_indirect_intr_ctx_conf = - &qdma_cpm4_indirect_intr_ctx_conf; - hw_access->qdma_set_default_global_csr = - &qdma_cpm4_set_default_global_csr; - hw_access->qdma_queue_pidx_update = - &qdma_cpm4_queue_pidx_update; - hw_access->qdma_queue_cmpt_cidx_update = - &qdma_cpm4_queue_cmpt_cidx_update; - hw_access->qdma_queue_intr_cidx_update = - &qdma_cpm4_queue_intr_cidx_update; - hw_access->qdma_get_user_bar = &qdma_cmp_get_user_bar; - hw_access->qdma_get_device_attributes = - &qdma_cpm4_get_device_attributes; - hw_access->qdma_dump_config_regs = - &qdma_cpm4_dump_config_regs; - hw_access->qdma_dump_intr_context = - &qdma_cpm4_dump_intr_context; - hw_access->qdma_hw_error_enable = - &qdma_cpm4_hw_error_enable; - hw_access->qdma_hw_error_process = - &qdma_cpm4_hw_error_process; - hw_access->qdma_hw_get_error_name = - &qdma_cpm4_hw_get_error_name; - hw_access->qdma_legacy_intr_conf = NULL; - hw_access->qdma_read_reg_list = &qdma_cpm4_read_reg_list; - hw_access->qdma_dump_config_reg_list = - &qdma_cpm4_dump_config_reg_list; - hw_access->qdma_dump_queue_context = - &qdma_cpm4_dump_queue_context; - hw_access->qdma_read_dump_queue_context = - &qdma_cpm4_read_dump_queue_context; - hw_access->qdma_dump_reg_info = &qdma_cpm4_dump_reg_info; - hw_access->qdma_max_errors = QDMA_CPM4_ERRS_ALL; - } - - if (version_info.ip_type == QDMA_VERSAL_HARD_IP && - version_info.device_type == QDMA_DEVICE_VERSAL_CPM5) { - hw_access->qdma_init_ctxt_memory = - &eqdma_cpm5_init_ctxt_memory; -#ifdef TANDEM_BOOT_SUPPORTED - hw_access->qdma_init_st_ctxt = - &eqdma_cpm5_init_st_ctxt; -#endif - hw_access->qdma_sw_ctx_conf = &eqdma_cpm5_sw_ctx_conf; - hw_access->qdma_fmap_conf = &eqdma_cpm5_fmap_conf; - hw_access->qdma_pfetch_ctx_conf = - &eqdma_cpm5_pfetch_ctx_conf; - hw_access->qdma_cmpt_ctx_conf = &eqdma_cpm5_cmpt_ctx_conf; - hw_access->qdma_indirect_intr_ctx_conf = - &eqdma_cpm5_indirect_intr_ctx_conf; - hw_access->qdma_dump_config_regs = - &eqdma_cpm5_dump_config_regs; - hw_access->qdma_dump_intr_context = - &eqdma_cpm5_dump_intr_context; - hw_access->qdma_hw_error_enable = - &eqdma_cpm5_hw_error_enable; - hw_access->qdma_hw_error_process = - &eqdma_cpm5_hw_error_process; - hw_access->qdma_hw_get_error_name = - &eqdma_cpm5_hw_get_error_name; - hw_access->qdma_hw_ctx_conf = &eqdma_cpm5_hw_ctx_conf; - hw_access->qdma_credit_ctx_conf = - &eqdma_cpm5_credit_ctx_conf; - hw_access->qdma_set_default_global_csr = - &eqdma_cpm5_set_default_global_csr; - hw_access->qdma_get_device_attributes = - &eqdma_cpm5_get_device_attributes; - hw_access->qdma_get_user_bar = &eqdma_cpm5_get_user_bar; - hw_access->qdma_read_reg_list = &eqdma_cpm5_read_reg_list; - hw_access->qdma_dump_config_reg_list = - &eqdma_cpm5_dump_config_reg_list; - hw_access->qdma_dump_queue_context = - &eqdma_cpm5_dump_queue_context; - hw_access->qdma_read_dump_queue_context = - &eqdma_cpm5_read_dump_queue_context; - hw_access->qdma_dump_reg_info = &eqdma_cpm5_dump_reg_info; - /* All CSR and Queue space register belongs to Window 0. - * Mailbox and MSIX register belongs to Window 1 - * Therefore, Mailbox offsets are different for EQDMA - * Mailbox offset for PF : 128K + original address - * Mailbox offset for VF : 16K + original address - */ - hw_access->mbox_base_pf = EQDMA_CPM5_OFFSET_MBOX_BASE_PF; - hw_access->mbox_base_vf = EQDMA_CPM5_OFFSET_MBOX_BASE_VF; - hw_access->qdma_max_errors = EQDMA_CPM5_ERRS_ALL; - -} - - if (version_info.ip_type == EQDMA_SOFT_IP) { - hw_access->qdma_init_ctxt_memory = &eqdma_init_ctxt_memory; - hw_access->qdma_sw_ctx_conf = &eqdma_sw_ctx_conf; - hw_access->qdma_fmap_conf = &eqdma_fmap_conf; - hw_access->qdma_pfetch_ctx_conf = &eqdma_pfetch_ctx_conf; - hw_access->qdma_cmpt_ctx_conf = &eqdma_cmpt_ctx_conf; - hw_access->qdma_indirect_intr_ctx_conf = - &eqdma_indirect_intr_ctx_conf; - hw_access->qdma_dump_config_regs = &eqdma_dump_config_regs; - hw_access->qdma_dump_intr_context = &eqdma_dump_intr_context; - hw_access->qdma_hw_error_enable = &eqdma_hw_error_enable; - hw_access->qdma_hw_error_process = &eqdma_hw_error_process; - hw_access->qdma_hw_get_error_name = &eqdma_hw_get_error_name; - hw_access->qdma_hw_ctx_conf = &eqdma_hw_ctx_conf; - hw_access->qdma_credit_ctx_conf = &eqdma_credit_ctx_conf; - hw_access->qdma_set_default_global_csr = - &eqdma_set_default_global_csr; - hw_access->qdma_get_device_attributes = - &eqdma_get_device_attributes; - hw_access->qdma_get_user_bar = &eqdma_get_user_bar; - hw_access->qdma_read_reg_list = &eqdma_read_reg_list; - hw_access->qdma_dump_config_reg_list = - &eqdma_dump_config_reg_list; - hw_access->qdma_dump_queue_context = - &eqdma_dump_queue_context; - hw_access->qdma_read_dump_queue_context = - &eqdma_read_dump_queue_context; - hw_access->qdma_dump_reg_info = &eqdma_dump_reg_info; - /* All CSR and Queue space register belongs to Window 0. - * Mailbox and MSIX register belongs to Window 1 - * Therefore, Mailbox offsets are different for EQDMA - * Mailbox offset for PF : 128K + original address - * Mailbox offset for VF : 16K + original address - */ - hw_access->mbox_base_pf = EQDMA_OFFSET_MBOX_BASE_PF; - hw_access->mbox_base_vf = EQDMA_OFFSET_MBOX_BASE_VF; - hw_access->qdma_max_errors = EQDMA_ERRS_ALL; - } - - return QDMA_SUCCESS; -} diff --git a/QDMA/linux-kernel/driver/libqdma/qdma_access/qdma_access_common.h b/QDMA/linux-kernel/driver/libqdma/qdma_access/qdma_access_common.h deleted file mode 100755 index f88c015d9..000000000 --- a/QDMA/linux-kernel/driver/libqdma/qdma_access/qdma_access_common.h +++ /dev/null @@ -1,926 +0,0 @@ -/* - * Copyright (c) 2019-2022, Xilinx, Inc. All rights reserved. - * Copyright (c) 2022, Advanced Micro Devices, Inc. All rights reserved. - * - * This source code is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * The full GNU General Public License is included in this distribution in - * the file called "COPYING". - */ - -#ifndef __QDMA_ACCESS_COMMON_H_ -#define __QDMA_ACCESS_COMMON_H_ - -#ifdef __cplusplus -extern "C" { -#endif - -#include "qdma_access_export.h" -#include "qdma_access_errors.h" - -/* QDMA HW version string array length */ -#define QDMA_HW_VERSION_STRING_LEN 32 - -#define ENABLE_INIT_CTXT_MEMORY 1 - -#ifdef GCC_COMPILER -static inline uint32_t get_trailing_zeros(uint64_t x) -{ - uint32_t rv = - __builtin_ffsll(x) - 1; - return rv; -} -#else -static inline uint32_t get_trailing_zeros(uint64_t value) -{ - uint32_t pos = 0; - - if ((value & 0xffffffff) == 0) { - pos += 32; - value >>= 32; - } - if ((value & 0xffff) == 0) { - pos += 16; - value >>= 16; - } - if ((value & 0xff) == 0) { - pos += 8; - value >>= 8; - } - if ((value & 0xf) == 0) { - pos += 4; - value >>= 4; - } - if ((value & 0x3) == 0) { - pos += 2; - value >>= 2; - } - if ((value & 0x1) == 0) - pos += 1; - - return pos; -} -#endif - -#define FIELD_SHIFT(mask) get_trailing_zeros(mask) -#define FIELD_SET(mask, val) ((val << FIELD_SHIFT(mask)) & mask) -#define FIELD_GET(mask, reg) ((reg & mask) >> FIELD_SHIFT(mask)) - - -/* CSR Default values */ -#define DEFAULT_MAX_DSC_FETCH 6 -#define DEFAULT_WRB_INT QDMA_WRB_INTERVAL_128 - -/* Default values for 0xB08 */ -#define DEFAULT_PFCH_NUM_ENTRIES_PER_Q 8 -#define DEFAULT_PFCH_MAX_Q_CNT 16 -#define DEFAULT_C2H_INTR_TIMER_TICK 25 -#define DEFAULT_CMPT_COAL_TIMER_TICK 25 -#define DEFAULT_CMPT_COAL_MAX_BUF_SZ 32 - -#ifdef THROUGHPUT_MEASUREMENT -/* Update WRB coalesce timer count for throughput measurement */ -#define DEFAULT_CMPT_COAL_TIMER_CNT 10 -#else -/* Update WRB coalesce timer count for low latency measurement */ -#define DEFAULT_CMPT_COAL_TIMER_CNT 5 -#endif - -#define QDMA_BAR_NUM 6 - -/** Maximum data vectors to be used for each function - * TODO: Please note that for 2018.2 only one vector would be used - * per pf and only one ring would be created for this vector - * It is also assumed that all functions have the same number of data vectors - * and currently different number of vectors per PF is not supported - */ -#define QDMA_NUM_DATA_VEC_FOR_INTR_CXT 1 - -enum ind_ctxt_cmd_op { - QDMA_CTXT_CMD_CLR, - QDMA_CTXT_CMD_WR, - QDMA_CTXT_CMD_RD, - QDMA_CTXT_CMD_INV -}; - -enum ind_ctxt_cmd_sel { - QDMA_CTXT_SEL_SW_C2H, - QDMA_CTXT_SEL_SW_H2C, - QDMA_CTXT_SEL_HW_C2H, - QDMA_CTXT_SEL_HW_H2C, - QDMA_CTXT_SEL_CR_C2H, - QDMA_CTXT_SEL_CR_H2C, - QDMA_CTXT_SEL_CMPT, - QDMA_CTXT_SEL_PFTCH, - QDMA_CTXT_SEL_INT_COAL, - QDMA_CTXT_SEL_PASID_RAM_LOW, - QDMA_CTXT_SEL_PASID_RAM_HIGH, - QDMA_CTXT_SEL_TIMER, - QDMA_CTXT_SEL_FMAP, -}; - -/* polling a register */ -#define QDMA_REG_POLL_DFLT_INTERVAL_US 10 /* 10us per poll */ -#define QDMA_REG_POLL_DFLT_TIMEOUT_US (500*1000) /* 500ms */ - -/** Constants */ -#define QDMA_NUM_RING_SIZES 16 -#define QDMA_NUM_C2H_TIMERS 16 -#define QDMA_NUM_C2H_BUFFER_SIZES 16 -#define QDMA_NUM_C2H_COUNTERS 16 -#define QDMA_MM_CONTROL_RUN 0x1 -#define QDMA_MM_CONTROL_STEP 0x100 -#define QDMA_MAGIC_NUMBER 0x1fd3 -#define QDMA_PIDX_STEP 0x10 -#define QDMA_CMPT_CIDX_STEP 0x10 -#define QDMA_INT_CIDX_STEP 0x10 - - -/** QDMA_IND_REG_SEL_PFTCH */ -#define QDMA_PFTCH_CTXT_SW_CRDT_GET_H_MASK GENMASK(15, 3) -#define QDMA_PFTCH_CTXT_SW_CRDT_GET_L_MASK GENMASK(2, 0) - -/** QDMA_IND_REG_SEL_CMPT */ -#define QDMA_COMPL_CTXT_BADDR_GET_H_MASK GENMASK_ULL(63, 38) -#define QDMA_COMPL_CTXT_BADDR_GET_L_MASK GENMASK_ULL(37, 12) -#define QDMA_COMPL_CTXT_PIDX_GET_H_MASK GENMASK(15, 4) -#define QDMA_COMPL_CTXT_PIDX_GET_L_MASK GENMASK(3, 0) - -#define QDMA_INTR_CTXT_BADDR_GET_H_MASK GENMASK_ULL(63, 61) -#define QDMA_INTR_CTXT_BADDR_GET_M_MASK GENMASK_ULL(60, 29) -#define QDMA_INTR_CTXT_BADDR_GET_L_MASK GENMASK_ULL(28, 12) - -#define QDMA_GLBL2_MM_CMPT_EN_MASK BIT(2) -#define QDMA_GLBL2_FLR_PRESENT_MASK BIT(1) -#define QDMA_GLBL2_MAILBOX_EN_MASK BIT(0) - -#define QDMA_REG_IND_CTXT_REG_COUNT 8 - -/* ------------------------ indirect register context fields -----------*/ -union qdma_ind_ctxt_cmd { - uint32_t word; - struct { - uint32_t busy:1; - uint32_t sel:4; - uint32_t op:2; - uint32_t qid:12; - uint32_t rsvd:14; - } bits; -}; - -#define QDMA_IND_CTXT_DATA_NUM_REGS 8 - -/** - * struct qdma_indirect_ctxt_regs - Inirect Context programming registers - */ -struct qdma_indirect_ctxt_regs { - uint32_t qdma_ind_ctxt_data[QDMA_IND_CTXT_DATA_NUM_REGS]; - uint32_t qdma_ind_ctxt_mask[QDMA_IND_CTXT_DATA_NUM_REGS]; - union qdma_ind_ctxt_cmd cmd; -}; - -/** - * struct qdma_fmap_cfg - fmap config data structure - */ -struct qdma_fmap_cfg { - - /** @qbase - queue base for the function */ - uint16_t qbase; - /** @qmax - maximum queues in the function */ - uint16_t qmax; -}; - -/** - * struct qdma_qid2vec - qid to vector mapping data structure - */ -struct qdma_qid2vec { - - /** @c2h_vector - For direct interrupt, it is the interrupt - * vector index of msix table; - * for indirect interrupt, it is the ring index - */ - uint8_t c2h_vector; - /** @c2h_en_coal - C2H Interrupt aggregation enable */ - uint8_t c2h_en_coal; - /** @h2c_vector - For direct interrupt, it is the interrupt - * vector index of msix table; - * for indirect interrupt, it is the ring index - */ - uint8_t h2c_vector; - /** @h2c_en_coal - H2C Interrupt aggregation enable */ - uint8_t h2c_en_coal; -}; - -/** - * struct qdma_descq_sw_ctxt - descq SW context config data structure - */ -struct qdma_descq_sw_ctxt { - - /** @ring_bs_addr - ring base address */ - uint64_t ring_bs_addr; - /** @vec - vector number */ - uint16_t vec; - /** @pidx - initial producer index */ - uint16_t pidx; - /** @irq_arm - Interrupt Arm */ - uint8_t irq_arm; - /** @fnc_id - Function ID */ - uint8_t fnc_id; - /** @qen - Indicates that the queue is enabled */ - uint8_t qen; - /** @frcd_en -Enable fetch credit */ - uint8_t frcd_en; - /** @wbi_chk -Writeback/Interrupt after pending check */ - uint8_t wbi_chk; - /** @wbi_intvl_en -Write back/Interrupt interval */ - uint8_t wbi_intvl_en; - /** @at - Address tanslation */ - uint8_t at; - /** @fetch_max - Maximum number of descriptor fetches outstanding */ - uint8_t fetch_max; - /** @rngsz_idx - Descriptor ring size index */ - uint8_t rngsz_idx; - /** @desc_sz -Descriptor fetch size */ - uint8_t desc_sz; - /** @bypass - bypass enable */ - uint8_t bypass; - /** @mm_chn - MM channel */ - uint8_t mm_chn; - /** @wbk_en -Writeback enable */ - uint8_t wbk_en; - /** @irq_en -Interrupt enable */ - uint8_t irq_en; - /** @port_id -Port_id */ - uint8_t port_id; - /** @irq_no_last - No interrupt was sent */ - uint8_t irq_no_last; - /** @err - Error status */ - uint8_t err; - /** @err_wb_sent -writeback/interrupt was sent for an error */ - uint8_t err_wb_sent; - /** @irq_req - Interrupt due to error waiting to be sent */ - uint8_t irq_req; - /** @mrkr_dis - Marker disable */ - uint8_t mrkr_dis; - /** @is_mm - MM mode */ - uint8_t is_mm; - /** @intr_aggr - interrupt aggregation enable */ - uint8_t intr_aggr; - /** @pasid_en - PASID Enable */ - uint8_t pasid_en; - /** @dis_intr_on_vf - Disbale interrupt with VF */ - uint8_t dis_intr_on_vf; - /** @virtio_en - Queue is in Virtio Mode */ - uint8_t virtio_en; - /** @pack_byp_out - descs on desc output interface can be packed */ - uint8_t pack_byp_out; - /** @irq_byp - IRQ Bypass mode */ - uint8_t irq_byp; - /** @host_id - Host ID */ - uint8_t host_id; - /** @pasid - PASID */ - uint32_t pasid; - /** @virtio_dsc_base - Virtio Desc Base Address */ - uint64_t virtio_dsc_base; -}; - -/** - * struct qdma_descq_hw_ctxt - descq hw context config data structure - */ -struct qdma_descq_hw_ctxt { - /** @cidx - consumer index */ - uint16_t cidx; - /** @crd_use - credits consumed */ - uint16_t crd_use; - /** @dsc_pend - descriptors pending */ - uint8_t dsc_pend; - /** @idl_stp_b -Queue invalid and no descriptors pending */ - uint8_t idl_stp_b; - /** @evt_pnd - Event pending */ - uint8_t evt_pnd; - /** @fetch_pnd -Descriptor fetch pending */ - uint8_t fetch_pnd; -}; - -/** - * struct qdma_descq_credit_ctxt - descq credit context config data structure - */ -struct qdma_descq_credit_ctxt { - - /** @credit -Fetch credits received. */ - uint32_t credit; -}; - -/** - * struct qdma_descq_prefetch_ctxt - descq pfetch context config data structure - */ -struct qdma_descq_prefetch_ctxt { - /** @sw_crdt -Software credit */ - uint16_t sw_crdt; - /** @bypass - bypass enable */ - uint8_t bypass; - /** @bufsz_idx - c2h buffer size index */ - uint8_t bufsz_idx; - /** @port_id - port ID */ - uint8_t port_id; - /** @var_desc - Variable Descriptor */ - uint8_t var_desc; - /** @num_pftch - Number of descs prefetched */ - uint16_t num_pftch; - /** @err -Error detected on this queue */ - uint8_t err; - /** @pfch_en - Enable prefetch */ - uint8_t pfch_en; - /** @pfch - Queue is in prefetch */ - uint8_t pfch; - /** @valid - context is valid */ - uint8_t valid; -}; - -/** - * struct qdma_descq_cmpt_ctxt - descq completion context config data structure - */ -struct qdma_descq_cmpt_ctxt { - /** @bs_addr - completion ring base address */ - uint64_t bs_addr; - /** @vec - Interrupt Vector */ - uint16_t vec; - /** @pidx_l - producer index low */ - uint16_t pidx; - /** @cidx - consumer index */ - uint16_t cidx; - /** @en_stat_desc - Enable Completion Status writes */ - uint8_t en_stat_desc; - /** @en_int - Enable Completion interrupts */ - uint8_t en_int; - /** @trig_mode - Interrupt and Completion Status Write Trigger Mode */ - uint8_t trig_mode; - /** @fnc_id - Function ID */ - uint8_t fnc_id; - /** @counter_idx - Index to counter register */ - uint8_t counter_idx; - /** @timer_idx - Index to timer register */ - uint8_t timer_idx; - /** @in_st - Interrupt State */ - uint8_t in_st; - /** @color - initial color bit to be used on Completion */ - uint8_t color; - /** @ringsz_idx - Completion ring size index to ring size registers */ - uint8_t ringsz_idx; - /** @desc_sz -descriptor size */ - uint8_t desc_sz; - /** @valid - context valid */ - uint8_t valid; - /** @err - error status */ - uint8_t err; - /** - * @user_trig_pend - user logic initiated interrupt is - * pending to be generate - */ - uint8_t user_trig_pend; - /** @timer_running - timer is running on this queue */ - uint8_t timer_running; - /** @full_upd - Full update */ - uint8_t full_upd; - /** @ovf_chk_dis - Completion Ring Overflow Check Disable */ - uint8_t ovf_chk_dis; - /** @at -Address Translation */ - uint8_t at; - /** @int_aggr -Interrupt Aggregation */ - uint8_t int_aggr; - /** @dis_intr_on_vf - Disbale interrupt with VF */ - uint8_t dis_intr_on_vf; - /** @vio - queue is in VirtIO mode */ - uint8_t vio; - /** @dir_c2h - DMA direction is C2H */ - uint8_t dir_c2h; - /** @host_id - Host ID */ - uint8_t host_id; - /** @pasid - PASID */ - uint32_t pasid; - /** @pasid_en - PASID Enable */ - uint8_t pasid_en; - /** @vio_eop - Virtio End-of-packet */ - uint8_t vio_eop; - /** @sh_cmpt - Shared Completion Queue */ - uint8_t sh_cmpt; -}; - -/** - * struct qdma_indirect_intr_ctxt - indirect interrupt context config data - * structure - */ -struct qdma_indirect_intr_ctxt { - /** @baddr_4k -Base address of Interrupt Aggregation Ring */ - uint64_t baddr_4k; - /** @vec - Interrupt vector index in msix table */ - uint16_t vec; - /** @pidx - Producer Index */ - uint16_t pidx; - /** @valid - context valid */ - uint8_t valid; - /** @int_st -Interrupt State */ - uint8_t int_st; - /** @color - Color bit */ - uint8_t color; - /** @page_size - Interrupt Aggregation Ring size */ - uint8_t page_size; - /** @at - Address translation */ - uint8_t at; - /** @host_id - Host ID */ - uint8_t host_id; - /** @pasid - PASID */ - uint32_t pasid; - /** @pasid_en - PASID Enable */ - uint8_t pasid_en; - /** @func_id - Function ID */ - uint16_t func_id; -}; - -struct qdma_hw_version_info { - /** @rtl_version - RTL Version */ - enum qdma_rtl_version rtl_version; - /** @vivado_release - Vivado Release id */ - enum qdma_vivado_release_id vivado_release; - /** @versal_ip_state - Versal IP state */ - enum qdma_ip_type ip_type; - /** @device_type - Device Type */ - enum qdma_device_type device_type; - /** @qdma_rtl_version_str - RTL Version string*/ - char qdma_rtl_version_str[QDMA_HW_VERSION_STRING_LEN]; - /** @qdma_vivado_release_id_str - Vivado Release id string*/ - char qdma_vivado_release_id_str[QDMA_HW_VERSION_STRING_LEN]; - /** @qdma_device_type_str - Qdma device type string*/ - char qdma_device_type_str[QDMA_HW_VERSION_STRING_LEN]; - /** @qdma_versal_ip_state_str - Versal IP state string*/ - char qdma_ip_type_str[QDMA_HW_VERSION_STRING_LEN]; -}; - -#define CTXT_ENTRY_NAME_SZ 64 -struct qctx_entry { - char name[CTXT_ENTRY_NAME_SZ]; - uint32_t value; -}; - -/** - * @struct - qdma_descq_context - * @brief queue context information - */ -struct qdma_descq_context { - struct qdma_qid2vec qid2vec; - struct qdma_fmap_cfg fmap; - struct qdma_descq_sw_ctxt sw_ctxt; - struct qdma_descq_hw_ctxt hw_ctxt; - struct qdma_descq_credit_ctxt cr_ctxt; - struct qdma_descq_prefetch_ctxt pfetch_ctxt; - struct qdma_descq_cmpt_ctxt cmpt_ctxt; -}; - -/** - * struct qdma_q_pidx_reg_info - Software PIDX register fields - */ -struct qdma_q_pidx_reg_info { - /** @pidx - Producer Index */ - uint16_t pidx; - /** @irq_en - Interrupt enable */ - uint8_t irq_en; -}; - -/** - * struct qdma_q_intr_cidx_reg_info - Interrupt Ring CIDX register fields - */ -struct qdma_intr_cidx_reg_info { - /** @sw_cidx - Software Consumer Index */ - uint16_t sw_cidx; - /** @rng_idx - Ring Index of the Interrupt Aggregation ring */ - uint8_t rng_idx; -}; - -/** - * struct qdma_q_cmpt_cidx_reg_info - CMPT CIDX register fields - */ -struct qdma_q_cmpt_cidx_reg_info { - /** @wrb_cidx - CMPT Consumer Index */ - uint16_t wrb_cidx; - /** @counter_idx - Counter Threshold Index */ - uint8_t counter_idx; - /** @timer_idx - Timer Count Index */ - uint8_t timer_idx; - /** @trig_mode - Trigger mode */ - uint8_t trig_mode; - /** @wrb_en - Enable status descriptor for CMPT */ - uint8_t wrb_en; - /** @irq_en - Enable Interrupt for CMPT */ - uint8_t irq_en; -}; - - -/** - * struct qdma_csr_info - Global CSR info data structure - */ -struct qdma_csr_info { - /** @ringsz: ring size values */ - uint16_t ringsz[QDMA_GLOBAL_CSR_ARRAY_SZ]; - /** @bufsz: buffer size values */ - uint16_t bufsz[QDMA_GLOBAL_CSR_ARRAY_SZ]; - /** @timer_cnt: timer threshold values */ - uint8_t timer_cnt[QDMA_GLOBAL_CSR_ARRAY_SZ]; - /** @cnt_thres: counter threshold values */ - uint8_t cnt_thres[QDMA_GLOBAL_CSR_ARRAY_SZ]; - /** @wb_intvl: writeback interval */ - uint8_t wb_intvl; -}; - -#define QDMA_MAX_REGISTER_DUMP 14 - -/** - * struct qdma_reg_data - Structure to - * hold address value and pair - */ -struct qdma_reg_data { - /** @reg_addr: register address */ - uint32_t reg_addr; - /** @reg_val: register value */ - uint32_t reg_val; -}; - -/** - * enum qdma_hw_access_type - To hold hw access type - */ -enum qdma_hw_access_type { - QDMA_HW_ACCESS_READ, - QDMA_HW_ACCESS_WRITE, - QDMA_HW_ACCESS_CLEAR, - QDMA_HW_ACCESS_INVALIDATE, - QDMA_HW_ACCESS_MAX -}; - -/** - * enum qdma_global_csr_type - To hold global csr type - */ -enum qdma_global_csr_type { - QDMA_CSR_RING_SZ, - QDMA_CSR_TIMER_CNT, - QDMA_CSR_CNT_TH, - QDMA_CSR_BUF_SZ, - QDMA_CSR_MAX -}; - -/** - * enum status_type - To hold enable/disable status type - */ -enum status_type { - DISABLE = 0, - ENABLE = 1, -}; - -/** - * enum qdma_reg_read_type - Indicates reg read type - */ -enum qdma_reg_read_type { - /** @QDMA_REG_READ_PF_ONLY: Read the register for PFs only */ - QDMA_REG_READ_PF_ONLY, - /** @QDMA_REG_READ_VF_ONLY: Read the register for VFs only */ - QDMA_REG_READ_VF_ONLY, - /** @QDMA_REG_READ_PF_VF: Read the register for both PF and VF */ - QDMA_REG_READ_PF_VF, - /** @QDMA_REG_READ_MAX: Reg read enum max */ - QDMA_REG_READ_MAX -}; - -/** - * enum qdma_reg_read_groups - Indicates reg read groups - */ -enum qdma_reg_read_groups { - /** @QDMA_REG_READ_GROUP_1: Read the register from 0x000 to 0x288 */ - QDMA_REG_READ_GROUP_1, - /** @QDMA_REG_READ_GROUP_2: Read the register from 0x400 to 0xAFC */ - QDMA_REG_READ_GROUP_2, - /** @QDMA_REG_READ_GROUP_3: Read the register from 0xB00 to 0xE28 */ - QDMA_REG_READ_GROUP_3, - /** @QDMA_REG_READ_GROUP_4: Read the register Mailbox Registers */ - QDMA_REG_READ_GROUP_4, - /** @QDMA_REG_READ_GROUP_MAX: Reg read max groups */ - QDMA_REG_READ_GROUP_MAX -}; - -void qdma_write_csr_values(void *dev_hndl, uint32_t reg_offst, - uint32_t idx, uint32_t cnt, const uint32_t *values); - -void qdma_read_csr_values(void *dev_hndl, uint32_t reg_offst, - uint32_t idx, uint32_t cnt, uint32_t *values); - -int dump_reg(char *buf, int buf_sz, uint32_t raddr, - const char *rname, uint32_t rval); - -int hw_monitor_reg(void *dev_hndl, uint32_t reg, uint32_t mask, - uint32_t val, uint32_t interval_us, - uint32_t timeout_us); - -void qdma_memset(void *to, uint8_t val, uint32_t size); - -int qdma_acc_reg_dump_buf_len(void *dev_hndl, enum qdma_ip_type ip_type, - enum qdma_device_type device_type, int *buflen); - -int qdma_acc_reg_info_len(void *dev_hndl, enum qdma_ip_type ip_type, - enum qdma_device_type device_type, int *buflen, int *num_regs); - -int qdma_acc_context_buf_len(void *dev_hndl, enum qdma_ip_type ip_type, - enum qdma_device_type device_type, uint8_t st, - enum qdma_dev_q_type q_type, uint32_t *buflen); - -int qdma_acc_get_num_config_regs(void *dev_hndl, enum qdma_ip_type ip_type, - enum qdma_device_type device_type, uint32_t *num_regs); - -/* - * struct qdma_hw_access - Structure to hold HW access function pointers - */ -struct qdma_hw_access { - int (*qdma_set_default_global_csr)(void *dev_hndl); - int (*qdma_global_csr_conf)(void *dev_hndl, uint8_t index, - uint8_t count, uint32_t *csr_val, - enum qdma_global_csr_type csr_type, - enum qdma_hw_access_type access_type); - int (*qdma_global_writeback_interval_conf)(void *dev_hndl, - enum qdma_wrb_interval *wb_int, - enum qdma_hw_access_type access_type); - int (*qdma_init_ctxt_memory)(void *dev_hndl); - int (*qdma_qid2vec_conf)(void *dev_hndl, uint8_t c2h, uint16_t hw_qid, - struct qdma_qid2vec *ctxt, - enum qdma_hw_access_type access_type); - int (*qdma_fmap_conf)(void *dev_hndl, uint16_t func_id, - struct qdma_fmap_cfg *config, - enum qdma_hw_access_type access_type); - int (*qdma_sw_ctx_conf)(void *dev_hndl, uint8_t c2h, uint16_t hw_qid, - struct qdma_descq_sw_ctxt *ctxt, - enum qdma_hw_access_type access_type); - int (*qdma_pfetch_ctx_conf)(void *dev_hndl, uint16_t hw_qid, - struct qdma_descq_prefetch_ctxt *ctxt, - enum qdma_hw_access_type access_type); - int (*qdma_cmpt_ctx_conf)(void *dev_hndl, uint16_t hw_qid, - struct qdma_descq_cmpt_ctxt *ctxt, - enum qdma_hw_access_type access_type); - int (*qdma_hw_ctx_conf)(void *dev_hndl, uint8_t c2h, uint16_t hw_qid, - struct qdma_descq_hw_ctxt *ctxt, - enum qdma_hw_access_type access_type); - int (*qdma_credit_ctx_conf)(void *dev_hndl, uint8_t c2h, - uint16_t hw_qid, - struct qdma_descq_credit_ctxt *ctxt, - enum qdma_hw_access_type access_type); - int (*qdma_indirect_intr_ctx_conf)(void *dev_hndl, uint16_t ring_index, - struct qdma_indirect_intr_ctxt *ctxt, - enum qdma_hw_access_type access_type); - int (*qdma_queue_pidx_update)(void *dev_hndl, uint8_t is_vf, - uint16_t qid, - uint8_t is_c2h, - const struct qdma_q_pidx_reg_info *reg_info); - int (*qdma_queue_cmpt_cidx_read)(void *dev_hndl, uint8_t is_vf, - uint16_t qid, - struct qdma_q_cmpt_cidx_reg_info *reg_info); - int (*qdma_queue_cmpt_cidx_update)(void *dev_hndl, uint8_t is_vf, - uint16_t qid, - const struct qdma_q_cmpt_cidx_reg_info *reg_info); - int (*qdma_queue_intr_cidx_update)(void *dev_hndl, uint8_t is_vf, - uint16_t qid, - const struct qdma_intr_cidx_reg_info *reg_info); - int (*qdma_mm_channel_conf)(void *dev_hndl, uint8_t channel, - uint8_t is_c2h, uint8_t enable); - int (*qdma_get_user_bar)(void *dev_hndl, uint8_t is_vf, - uint16_t func_id, uint8_t *user_bar); - int (*qdma_get_function_number)(void *dev_hndl, uint16_t *func_id); - int (*qdma_get_version)(void *dev_hndl, uint8_t is_vf, - struct qdma_hw_version_info *version_info); - int (*qdma_get_device_attributes)(void *dev_hndl, - struct qdma_dev_attributes *dev_info); - int (*qdma_hw_error_intr_setup)(void *dev_hndl, uint16_t func_id, - uint8_t err_intr_index); - int (*qdma_hw_error_intr_rearm)(void *dev_hndl); - int (*qdma_hw_error_enable)(void *dev_hndl, - uint32_t err_idx); - const char *(*qdma_hw_get_error_name)(uint32_t err_idx); - int (*qdma_hw_error_process)(void *dev_hndl); - int (*qdma_dump_config_regs)(void *dev_hndl, uint8_t is_vf, char *buf, - uint32_t buflen); - int (*qdma_dump_reg_info)(void *dev_hndl, uint32_t reg_addr, - uint32_t num_regs, - char *buf, - uint32_t buflen); - int (*qdma_dump_queue_context)(void *dev_hndl, - uint8_t st, - enum qdma_dev_q_type q_type, - struct qdma_descq_context *ctxt_data, - char *buf, uint32_t buflen); - int (*qdma_read_dump_queue_context)(void *dev_hndl, - uint16_t func_id, - uint16_t qid_hw, - uint8_t st, - enum qdma_dev_q_type q_type, - char *buf, uint32_t buflen); - int (*qdma_dump_intr_context)(void *dev_hndl, - struct qdma_indirect_intr_ctxt *intr_ctx, - int ring_index, - char *buf, uint32_t buflen); - int (*qdma_is_legacy_intr_pend)(void *dev_hndl); - int (*qdma_clear_pend_legacy_intr)(void *dev_hndl); - int (*qdma_legacy_intr_conf)(void *dev_hndl, enum status_type enable); - int (*qdma_initiate_flr)(void *dev_hndl, uint8_t is_vf); - int (*qdma_is_flr_done)(void *dev_hndl, uint8_t is_vf, uint8_t *done); - int (*qdma_get_error_code)(int acc_err_code); - int (*qdma_read_reg_list)(void *dev_hndl, uint8_t is_vf, - uint16_t reg_rd_group, - uint16_t *total_regs, - struct qdma_reg_data *reg_list); - int (*qdma_dump_config_reg_list)(void *dev_hndl, - uint32_t num_regs, - struct qdma_reg_data *reg_list, - char *buf, uint32_t buflen); -#ifdef TANDEM_BOOT_SUPPORTED - int (*qdma_init_st_ctxt)(void *dev_hndl); -#endif - uint32_t mbox_base_pf; - uint32_t mbox_base_vf; - uint32_t qdma_max_errors; -}; - -/*****************************************************************************/ -/** - * qdma_hw_access_init() - Function to get the QDMA hardware - * access function pointers - * This function should be called once per device from - * device_open()/probe(). Caller shall allocate memory for - * qdma_hw_access structure and store pointer to it in their - * per device structure. Config BAR validation will be done - * inside this function - * - * @dev_hndl: device handle - * @is_vf: Whether PF or VF - * @hw_access: qdma_hw_access structure pointer. - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -int qdma_hw_access_init(void *dev_hndl, uint8_t is_vf, - struct qdma_hw_access *hw_access); - -/*****************************************************************************/ -/** - * qdma_acc_get_config_regs() - Function to get qdma config registers - * - * @dev_hndl: device handle - * @is_vf: Whether PF or VF - * @ip_type: QDMA IP Type - * @device_type:QDMA DEVICE Type - * @reg_data: pointer to register data to be filled - * - * Return: Length up-till the buffer is filled -success and < 0 - failure - *****************************************************************************/ -int qdma_acc_get_config_regs(void *dev_hndl, uint8_t is_vf, - enum qdma_ip_type ip_type, - enum qdma_device_type device_type, - uint32_t *reg_data); - -/*****************************************************************************/ -/** - * qdma_acc_dump_config_regs() - Function to get qdma config register dump in a - * buffer - * - * @dev_hndl: device handle - * @is_vf: Whether PF or VF - * @ip_type: QDMA IP Type - * @device_type:QDMA DEVICE Type - * @buf : pointer to buffer to be filled - * @buflen : Length of the buffer - * - * Return: Length up-till the buffer is filled -success and < 0 - failure - *****************************************************************************/ -int qdma_acc_dump_config_regs(void *dev_hndl, uint8_t is_vf, - enum qdma_ip_type ip_type, - enum qdma_device_type device_type, - char *buf, uint32_t buflen); - -/*****************************************************************************/ -/** - * qdma_acc_dump_reg_info() - Function to get qdma reg info in a buffer - * - * @dev_hndl: device handle - * @ip_type: QDMA IP Type - * @device_type:QDMA DEVICE Type - * @reg_addr: Register Address - * @num_regs: Number of Registers - * @buf : pointer to buffer to be filled - * @buflen : Length of the buffer - * - * Return: Length up-till the buffer is filled -success and < 0 - failure - *****************************************************************************/ -int qdma_acc_dump_reg_info(void *dev_hndl, enum qdma_ip_type ip_type, - enum qdma_device_type device_type, uint32_t reg_addr, - uint32_t num_regs, char *buf, uint32_t buflen); - -/*****************************************************************************/ -/** - * qdma_acc_dump_queue_context() - Function to dump qdma queue context data in a - * buffer where context information is already available in 'ctxt_data' - * structure pointer buffer - * - * @dev_hndl: device handle - * @ip_type: QDMA IP Type - * @device_type:QDMA DEVICE Type - * @st: ST or MM - * @q_type: Queue Type - * @ctxt_data: Context Data - * @buf : pointer to buffer to be filled - * @buflen : Length of the buffer - * - * Return: Length up-till the buffer is filled -success and < 0 - failure - *****************************************************************************/ -int qdma_acc_dump_queue_context(void *dev_hndl, - enum qdma_ip_type ip_type, - enum qdma_device_type device_type, - uint8_t st, - enum qdma_dev_q_type q_type, - struct qdma_descq_context *ctxt_data, - char *buf, uint32_t buflen); - -/*****************************************************************************/ -/** - * qdma_acc_read_dump_queue_context() - Function to read and dump the queue - * context in a buffer - * - * @dev_hndl: device handle - * @ip_type: QDMA IP Type - * @device_type:QDMA DEVICE Type - * @qid_hw: queue id - * @st: ST or MM - * @q_type: Queue Type - * @buf : pointer to buffer to be filled - * @buflen : Length of the buffer - * - * Return: Length up-till the buffer is filled -success and < 0 - failure - *****************************************************************************/ -int qdma_acc_read_dump_queue_context(void *dev_hndl, - enum qdma_ip_type ip_type, - enum qdma_device_type device_type, - uint16_t func_id, - uint16_t qid_hw, - uint8_t st, - enum qdma_dev_q_type q_type, - char *buf, uint32_t buflen); - - -/*****************************************************************************/ -/** - * qdma_acc_dump_config_reg_list() - Dump the registers - * - * @dev_hndl: device handle - * @ip_type: QDMA IP Type - * @device_type: QDMA DEVICE Type - * @total_regs : Max registers to read - * @reg_list : array of reg addr and reg values - * @buf : pointer to buffer to be filled - * @buflen : Length of the buffer - * - * Return: returns the platform specific error code - *****************************************************************************/ -int qdma_acc_dump_config_reg_list(void *dev_hndl, - enum qdma_ip_type ip_type, - enum qdma_device_type device_type, - uint32_t num_regs, - struct qdma_reg_data *reg_list, - char *buf, uint32_t buflen); - -/*****************************************************************************/ -/** - * qdma_get_error_code() - function to get the qdma access mapped - * error code - * - * @acc_err_code: qdma access error code - * - * Return: returns the platform specific error code - *****************************************************************************/ -int qdma_get_error_code(int acc_err_code); - -/*****************************************************************************/ -/** - * qdma_fetch_version_details() - Function to fetch the version details from the - * version register value - * - * @is_vf : Whether PF or VF - * @version_reg_val : Value of the version register - * @version_info : Pointer to store the version details. - * - * Return: Nothing - *****************************************************************************/ -void qdma_fetch_version_details(void *dev_hndl, uint8_t is_vf, - uint32_t version_reg_val, struct qdma_hw_version_info *version_info); - -#ifdef __cplusplus -} -#endif - -#endif /* QDMA_ACCESS_COMMON_H_ */ diff --git a/QDMA/linux-kernel/driver/libqdma/qdma_access/qdma_access_errors.h b/QDMA/linux-kernel/driver/libqdma/qdma_access/qdma_access_errors.h deleted file mode 100755 index c8b28c9ff..000000000 --- a/QDMA/linux-kernel/driver/libqdma/qdma_access/qdma_access_errors.h +++ /dev/null @@ -1,73 +0,0 @@ -/* - * Copyright (c) 2019-2022, Xilinx, Inc. All rights reserved. - * Copyright (c) 2022, Advanced Micro Devices, Inc. All rights reserved. - * - * This source code is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * The full GNU General Public License is included in this distribution in - * the file called "COPYING". - */ - -#ifndef __QDMA_ACCESS_ERRORS_H_ -#define __QDMA_ACCESS_ERRORS_H_ - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * DOC: QDMA common library error codes definitions - * - * Header file *qdma_access_errors.h* defines error codes for common library - */ - -struct err_code_map { - int acc_err_code; - int err_code; -}; - -#define QDMA_HW_ERR_NOT_DETECTED 1 - -enum qdma_access_error_codes { - QDMA_SUCCESS = 0, - QDMA_ERR_INV_PARAM, - QDMA_ERR_NO_MEM, - QDMA_ERR_HWACC_BUSY_TIMEOUT, - QDMA_ERR_HWACC_INV_CONFIG_BAR, - QDMA_ERR_HWACC_NO_PEND_LEGCY_INTR, - QDMA_ERR_HWACC_BAR_NOT_FOUND, - QDMA_ERR_HWACC_FEATURE_NOT_SUPPORTED, /* 7 */ - - QDMA_ERR_RM_RES_EXISTS, /* 8 */ - QDMA_ERR_RM_RES_NOT_EXISTS, - QDMA_ERR_RM_DEV_EXISTS, - QDMA_ERR_RM_DEV_NOT_EXISTS, - QDMA_ERR_RM_NO_QUEUES_LEFT, - QDMA_ERR_RM_QMAX_CONF_REJECTED, /* 13 */ - - QDMA_ERR_MBOX_FMAP_WR_FAILED, /* 14 */ - QDMA_ERR_MBOX_NUM_QUEUES, - QDMA_ERR_MBOX_INV_QID, - QDMA_ERR_MBOX_INV_RINGSZ, - QDMA_ERR_MBOX_INV_BUFSZ, - QDMA_ERR_MBOX_INV_CNTR_TH, - QDMA_ERR_MBOX_INV_TMR_TH, - QDMA_ERR_MBOX_INV_MSG, - QDMA_ERR_MBOX_SEND_BUSY, - QDMA_ERR_MBOX_NO_MSG_IN, - QDMA_ERR_MBOX_REG_READ_FAILED, - QDMA_ERR_MBOX_ALL_ZERO_MSG, /* 25 */ -}; - -#ifdef __cplusplus -} -#endif - -#endif /* __QDMA_ACCESS_ERRORS_H_ */ diff --git a/QDMA/linux-kernel/driver/libqdma/qdma_access/qdma_access_export.h b/QDMA/linux-kernel/driver/libqdma/qdma_access/qdma_access_export.h deleted file mode 100755 index 66eaa3222..000000000 --- a/QDMA/linux-kernel/driver/libqdma/qdma_access/qdma_access_export.h +++ /dev/null @@ -1,262 +0,0 @@ -/* - * Copyright (c) 2019-2022, Xilinx, Inc. All rights reserved. - * Copyright (c) 2022, Advanced Micro Devices, Inc. All rights reserved. - * - * This source code is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * The full GNU General Public License is included in this distribution in - * the file called "COPYING". - */ - -#ifndef __QDMA_ACCESS_EXPORT_H_ -#define __QDMA_ACCESS_EXPORT_H_ - -#ifdef __cplusplus -extern "C" { -#endif - -#include "qdma_platform_env.h" - -/** QDMA Global CSR array size */ -#define QDMA_GLOBAL_CSR_ARRAY_SZ 16 - -/** - * struct qdma_dev_attributes - QDMA device attributes - */ -struct qdma_dev_attributes { - /** @num_pfs - Num of PFs*/ - uint8_t num_pfs; - /** @num_qs - Num of Queues */ - uint16_t num_qs; - /** @flr_present - FLR resent or not? */ - uint8_t flr_present:1; - /** @st_en - ST mode supported or not? */ - uint8_t st_en:1; - /** @mm_en - MM mode supported or not? */ - uint8_t mm_en:1; - /** @mm_cmpt_en - MM with Completions supported or not? */ - uint8_t mm_cmpt_en:1; - /** @mailbox_en - Mailbox supported or not? */ - uint8_t mailbox_en:1; - /** @debug_mode - Debug mode is enabled/disabled for IP */ - uint8_t debug_mode:1; - /** @desc_eng_mode - Descriptor Engine mode: - * Internal only/Bypass only/Internal & Bypass - */ - uint8_t desc_eng_mode:2; - /** @mm_channel_max - Num of MM channels */ - uint8_t mm_channel_max; - - /** Below are the list of HW features which are populated by qdma_access - * based on RTL version - */ - /** @qid2vec_ctx - To indicate support of qid2vec context */ - uint8_t qid2vec_ctx:1; - /** @cmpt_ovf_chk_dis - To indicate support of overflow check - * disable in CMPT ring - */ - uint8_t cmpt_ovf_chk_dis:1; - /** @mailbox_intr - To indicate support of mailbox interrupt */ - uint8_t mailbox_intr:1; - /** @sw_desc_64b - To indicate support of 64 bytes C2H/H2C - * descriptor format - */ - uint8_t sw_desc_64b:1; - /** @cmpt_desc_64b - To indicate support of 64 bytes CMPT - * descriptor format - */ - uint8_t cmpt_desc_64b:1; - /** @dynamic_bar - To indicate support of dynamic bar detection */ - uint8_t dynamic_bar:1; - /** @legacy_intr - To indicate support of legacy interrupt */ - uint8_t legacy_intr:1; - /** @cmpt_trig_count_timer - To indicate support of counter + timer - * trigger mode - */ - uint8_t cmpt_trig_count_timer:1; -}; - -/** qdma_dev_attributes structure size */ -#define QDMA_DEV_ATTR_STRUCT_SIZE (sizeof(struct qdma_dev_attributes)) - -/** global_csr_conf structure size */ -#define QDMA_DEV_GLOBAL_CSR_STRUCT_SIZE (sizeof(struct global_csr_conf)) - -/** - * enum qdma_dev_type - To hold qdma device type - */ -enum qdma_dev_type { - QDMA_DEV_PF, - QDMA_DEV_VF -}; - -/** - * enum qdma_dev_q_type: Q type - */ -enum qdma_dev_q_type { - /** @QDMA_DEV_Q_TYPE_H2C: H2C Q */ - QDMA_DEV_Q_TYPE_H2C, - /** @QDMA_DEV_Q_TYPE_C2H: C2H Q */ - QDMA_DEV_Q_TYPE_C2H, - /** @QDMA_DEV_Q_TYPE_CMPT: CMPT Q */ - QDMA_DEV_Q_TYPE_CMPT, - /** @QDMA_DEV_Q_TYPE_MAX: Total Q types */ - QDMA_DEV_Q_TYPE_MAX -}; - -/** - * @enum qdma_desc_size - QDMA queue descriptor size - */ -enum qdma_desc_size { - /** @QDMA_DESC_SIZE_8B - 8 byte descriptor */ - QDMA_DESC_SIZE_8B, - /** @QDMA_DESC_SIZE_16B - 16 byte descriptor */ - QDMA_DESC_SIZE_16B, - /** @QDMA_DESC_SIZE_32B - 32 byte descriptor */ - QDMA_DESC_SIZE_32B, - /** @QDMA_DESC_SIZE_64B - 64 byte descriptor */ - QDMA_DESC_SIZE_64B -}; - -/** - * @enum qdma_cmpt_update_trig_mode - Interrupt and Completion status write - * trigger mode - */ -enum qdma_cmpt_update_trig_mode { - /** @QDMA_CMPT_UPDATE_TRIG_MODE_DIS - disabled */ - QDMA_CMPT_UPDATE_TRIG_MODE_DIS, - /** @QDMA_CMPT_UPDATE_TRIG_MODE_EVERY - every */ - QDMA_CMPT_UPDATE_TRIG_MODE_EVERY, - /** @QDMA_CMPT_UPDATE_TRIG_MODE_USR_CNT - user counter */ - QDMA_CMPT_UPDATE_TRIG_MODE_USR_CNT, - /** @QDMA_CMPT_UPDATE_TRIG_MODE_USR - user */ - QDMA_CMPT_UPDATE_TRIG_MODE_USR, - /** @QDMA_CMPT_UPDATE_TRIG_MODE_USR_TMR - user timer */ - QDMA_CMPT_UPDATE_TRIG_MODE_USR_TMR, - /** @QDMA_CMPT_UPDATE_TRIG_MODE_TMR_CNTR - timer + counter combo */ - QDMA_CMPT_UPDATE_TRIG_MODE_TMR_CNTR -}; - - -/** - * @enum qdma_indirect_intr_ring_size - Indirect interrupt ring size - */ -enum qdma_indirect_intr_ring_size { - /** @QDMA_INDIRECT_INTR_RING_SIZE_4KB - Accommodates 512 entries */ - QDMA_INDIRECT_INTR_RING_SIZE_4KB, - /** @QDMA_INDIRECT_INTR_RING_SIZE_8KB - Accommodates 1024 entries */ - QDMA_INDIRECT_INTR_RING_SIZE_8KB, - /** @QDMA_INDIRECT_INTR_RING_SIZE_12KB - Accommodates 1536 entries */ - QDMA_INDIRECT_INTR_RING_SIZE_12KB, - /** @QDMA_INDIRECT_INTR_RING_SIZE_16KB - Accommodates 2048 entries */ - QDMA_INDIRECT_INTR_RING_SIZE_16KB, - /** @QDMA_INDIRECT_INTR_RING_SIZE_20KB - Accommodates 2560 entries */ - QDMA_INDIRECT_INTR_RING_SIZE_20KB, - /** @QDMA_INDIRECT_INTR_RING_SIZE_24KB - Accommodates 3072 entries */ - QDMA_INDIRECT_INTR_RING_SIZE_24KB, - /** @QDMA_INDIRECT_INTR_RING_SIZE_28KB - Accommodates 3584 entries */ - QDMA_INDIRECT_INTR_RING_SIZE_28KB, - /** @QDMA_INDIRECT_INTR_RING_SIZE_32KB - Accommodates 4096 entries */ - QDMA_INDIRECT_INTR_RING_SIZE_32KB -}; - -/** - * @enum qdma_wrb_interval - writeback update interval - */ -enum qdma_wrb_interval { - /** @QDMA_WRB_INTERVAL_4 - writeback update interval of 4 */ - QDMA_WRB_INTERVAL_4, - /** @QDMA_WRB_INTERVAL_8 - writeback update interval of 8 */ - QDMA_WRB_INTERVAL_8, - /** @QDMA_WRB_INTERVAL_16 - writeback update interval of 16 */ - QDMA_WRB_INTERVAL_16, - /** @QDMA_WRB_INTERVAL_32 - writeback update interval of 32 */ - QDMA_WRB_INTERVAL_32, - /** @QDMA_WRB_INTERVAL_64 - writeback update interval of 64 */ - QDMA_WRB_INTERVAL_64, - /** @QDMA_WRB_INTERVAL_128 - writeback update interval of 128 */ - QDMA_WRB_INTERVAL_128, - /** @QDMA_WRB_INTERVAL_256 - writeback update interval of 256 */ - QDMA_WRB_INTERVAL_256, - /** @QDMA_WRB_INTERVAL_512 - writeback update interval of 512 */ - QDMA_WRB_INTERVAL_512, - /** @QDMA_NUM_WRB_INTERVALS - total number of writeback intervals */ - QDMA_NUM_WRB_INTERVALS -}; - -enum qdma_rtl_version { - /** @QDMA_RTL_BASE - RTL Base */ - QDMA_RTL_BASE, - /** @QDMA_RTL_PATCH - RTL Patch */ - QDMA_RTL_PATCH, - /** @QDMA_RTL_NONE - Not a valid RTL version */ - QDMA_RTL_NONE, -}; - -enum qdma_vivado_release_id { - /** @QDMA_VIVADO_2018_3 - Vivado version 2018.3 */ - QDMA_VIVADO_2018_3, - /** @QDMA_VIVADO_2019_1 - Vivado version 2019.1 */ - QDMA_VIVADO_2019_1, - /** @QDMA_VIVADO_2019_2 - Vivado version 2019.2 */ - QDMA_VIVADO_2019_2, - /** @QDMA_VIVADO_2020_1 - Vivado version 2020.1 */ - QDMA_VIVADO_2020_1, - /** @QDMA_VIVADO_2020_2 - Vivado version 2020.2 */ - QDMA_VIVADO_2020_2, - /** @QDMA_VIVADO_2021_1 - Vivado version 2021.1 */ - QDMA_VIVADO_2021_1, - /** @QDMA_VIVADO_2022_1 - Vivado version 2022.1 */ - QDMA_VIVADO_2022_1, - /** @QDMA_VIVADO_NONE - Not a valid Vivado version*/ - QDMA_VIVADO_NONE -}; - -enum qdma_ip_type { - /** @QDMA_VERSAL_HARD_IP - Hard IP */ - QDMA_VERSAL_HARD_IP, - /** @QDMA_VERSAL_SOFT_IP - Soft IP */ - QDMA_VERSAL_SOFT_IP, - /** @QDMA_SOFT_IP - Hard IP */ - QDMA_SOFT_IP, - /** @EQDMA_SOFT_IP - Soft IP */ - EQDMA_SOFT_IP, - /** @QDMA_VERSAL_NONE - Not versal device */ - QDMA_NONE_IP -}; - - -enum qdma_device_type { - /** @QDMA_DEVICE_SOFT - UltraScale+ IP's */ - QDMA_DEVICE_SOFT, - /** @QDMA_DEVICE_VERSAL_CPM4 -VERSAL IP */ - QDMA_DEVICE_VERSAL_CPM4, - /** @QDMA_DEVICE_VERSAL_CPM5 -VERSAL IP */ - QDMA_DEVICE_VERSAL_CPM5, - /** @QDMA_DEVICE_NONE - Not a valid device */ - QDMA_DEVICE_NONE -}; - -enum qdma_desc_eng_mode { - /** @QDMA_DESC_ENG_INTERNAL_BYPASS - Internal and Bypass mode */ - QDMA_DESC_ENG_INTERNAL_BYPASS, - /** @QDMA_DESC_ENG_BYPASS_ONLY - Only Bypass mode */ - QDMA_DESC_ENG_BYPASS_ONLY, - /** @QDMA_DESC_ENG_INTERNAL_ONLY - Only Internal mode */ - QDMA_DESC_ENG_INTERNAL_ONLY, - /** @QDMA_DESC_ENG_MODE_MAX - Max of desc engine modes */ - QDMA_DESC_ENG_MODE_MAX -}; - -#ifdef __cplusplus -} -#endif - -#endif /* __QDMA_ACCESS_EXPORT_H_ */ diff --git a/QDMA/linux-kernel/driver/libqdma/qdma_access/qdma_access_version.h b/QDMA/linux-kernel/driver/libqdma/qdma_access/qdma_access_version.h deleted file mode 100755 index f65591813..000000000 --- a/QDMA/linux-kernel/driver/libqdma/qdma_access/qdma_access_version.h +++ /dev/null @@ -1,37 +0,0 @@ -/* - * Copyright (c) 2019-2022, Xilinx, Inc. All rights reserved. - * Copyright (c) 2022-2023, Advanced Micro Devices, Inc. All rights reserved. - * - * This source code is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * The full GNU General Public License is included in this distribution in - * the file called "COPYING". - */ - -#ifndef __QDMA_ACCESS_VERSION_H_ -#define __QDMA_ACCESS_VERSION_H_ - - -#define QDMA_VERSION_MAJOR 2023 -#define QDMA_VERSION_MINOR 2 -#define QDMA_VERSION_PATCH 1 - -#define QDMA_VERSION_STR \ - __stringify(QDMA_VERSION_MAJOR) "." \ - __stringify(QDMA_VERSION_MINOR) "." \ - __stringify(QDMA_VERSION_PATCH) - -#define QDMA_VERSION \ - ((QDMA_VERSION_MAJOR)*1000 + \ - (QDMA_VERSION_MINOR)*100 + \ - QDMA_VERSION_PATCH) - - -#endif /* __QDMA_ACCESS_VERSION_H_ */ diff --git a/QDMA/linux-kernel/driver/libqdma/qdma_access/qdma_cpm4_access/qdma_cpm4_access.c b/QDMA/linux-kernel/driver/libqdma/qdma_access/qdma_cpm4_access/qdma_cpm4_access.c deleted file mode 100755 index 33c45ff65..000000000 --- a/QDMA/linux-kernel/driver/libqdma/qdma_access/qdma_cpm4_access/qdma_cpm4_access.c +++ /dev/null @@ -1,6055 +0,0 @@ -/* - * Copyright (c) 2019-2022, Xilinx, Inc. All rights reserved. - * Copyright (c) 2022, Advanced Micro Devices, Inc. All rights reserved. - * - * This source code is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * The full GNU General Public License is included in this distribution in - * the file called "COPYING". - */ - -#include "qdma_cpm4_access.h" -#include "qdma_cpm4_reg.h" -#include "qdma_reg_dump.h" - -#ifdef ENABLE_WPP_TRACING -#include "qdma_cpm4_access.tmh" -#endif - -/** QDMA CPM4 Hard Context array size */ -#define QDMA_CPM4_SW_CONTEXT_NUM_WORDS 4 -#define QDMA_CPM4_CMPT_CONTEXT_NUM_WORDS 4 -#define QDMA_CPM4_QID2VEC_CONTEXT_NUM_WORDS 1 -#define QDMA_CPM4_HW_CONTEXT_NUM_WORDS 2 -#define QDMA_CPM4_CR_CONTEXT_NUM_WORDS 1 -#define QDMA_CPM4_IND_INTR_CONTEXT_NUM_WORDS 3 -#define QDMA_CPM4_PFETCH_CONTEXT_NUM_WORDS 2 - -#define QDMA_CPM4_VF_USER_BAR_ID 2 - -#define QDMA_CPM4_REG_GROUP_1_START_ADDR 0x000 -#define QDMA_CPM4_REG_GROUP_2_START_ADDR 0x400 -#define QDMA_CPM4_REG_GROUP_3_START_ADDR 0xB00 -#define QDMA_CPM4_REG_GROUP_4_START_ADDR 0x1014 - -#define QDMA_CPM4_REG_TRQ_SEL_FMAP_STEP 4 - -#define QDMA_CPM4_IND_CTXT_DATA_NUM_REGS 4 - -#define QDMA_CPM4_TOTAL_LEAF_ERROR_AGGREGATORS 7 -#define QDMA_CPM4_GLBL_TRQ_ERR_ALL_MASK 0XB3 -#define QDMA_CPM4_GLBL_DSC_ERR_ALL_MASK 0X1F9037E -#define QDMA_CPM4_C2H_ERR_ALL_MASK 0X3F6DF -#define QDMA_CPM4_C2H_FATAL_ERR_ALL_MASK 0X1FDF1B -#define QDMA_CPM4_H2C_ERR_ALL_MASK 0X3F -#define QDMA_CPM4_SBE_ERR_ALL_MASK 0XFFFFFFFF -#define QDMA_CPM4_DBE_ERR_ALL_MASK 0XFFFFFFFF - -#define QDMA_CPM4_OFFSET_DMAP_SEL_INT_CIDX 0x6400 -#define QDMA_CPM4_OFFSET_DMAP_SEL_H2C_DSC_PIDX 0x6404 -#define QDMA_CPM4_OFFSET_DMAP_SEL_C2H_DSC_PIDX 0x6408 -#define QDMA_CPM4_OFFSET_DMAP_SEL_CMPT_CIDX 0x640C - -#define QDMA_CPM4_OFFSET_VF_DMAP_SEL_INT_CIDX 0x3000 -#define QDMA_CPM4_OFFSET_VF_DMAP_SEL_H2C_DSC_PIDX 0x3004 -#define QDMA_CPM4_OFFSET_VF_DMAP_SEL_C2H_DSC_PIDX 0x3008 -#define QDMA_CPM4_OFFSET_VF_DMAP_SEL_CMPT_CIDX 0x300C - -#define QDMA_CPM4_DMA_SEL_INT_SW_CIDX_MASK GENMASK(15, 0) -#define QDMA_CPM4_DMA_SEL_INT_RING_IDX_MASK GENMASK(23, 16) -#define QDMA_CPM4_DMA_SEL_DESC_PIDX_MASK GENMASK(15, 0) -#define QDMA_CPM4_DMA_SEL_IRQ_EN_MASK BIT(16) -#define QDMA_CPM4_DMAP_SEL_CMPT_IRQ_EN_MASK BIT(28) -#define QDMA_CPM4_DMAP_SEL_CMPT_STS_DESC_EN_MASK BIT(27) -#define QDMA_CPM4_DMAP_SEL_CMPT_TRG_MODE_MASK GENMASK(26, 24) -#define QDMA_CPM4_DMAP_SEL_CMPT_TMR_CNT_MASK GENMASK(23, 20) -#define QDMA_CPM4_DMAP_SEL_CMPT_CNT_THRESH_MASK GENMASK(19, 16) -#define QDMA_CPM4_DMAP_SEL_CMPT_WRB_CIDX_MASK GENMASK(15, 0) -#define QDMA_CPM4_INTR_CTXT_BADDR_GET_H_MASK GENMASK_ULL(63, 35) -#define QDMA_CPM4_INTR_CTXT_BADDR_GET_L_MASK GENMASK_ULL(34, 12) -#define QDMA_CPM4_COMPL_CTXT_BADDR_GET_H_MASK GENMASK_ULL(63, 42) -#define QDMA_CPM4_COMPL_CTXT_BADDR_GET_M_MASK GENMASK_ULL(41, 10) -#define QDMA_CPM4_COMPL_CTXT_BADDR_GET_L_MASK GENMASK_ULL(9, 6) -#define QDMA_CPM4_COMPL_CTXT_PIDX_GET_H_MASK GENMASK(15, 8) -#define QDMA_CPM4_COMPL_CTXT_PIDX_GET_L_MASK GENMASK(7, 0) -#define QDMA_CPM4_QID2VEC_H2C_VECTOR GENMASK(16, 9) -#define QDMA_CPM4_QID2VEC_H2C_COAL_EN BIT(17) - -#define QDMA_CPM4_DEFAULT_PFCH_STOP_THRESH 256 - -static void qdma_cpm4_hw_st_h2c_err_process(void *dev_hndl); -static void qdma_cpm4_hw_st_c2h_err_process(void *dev_hndl); -static void qdma_cpm4_hw_desc_err_process(void *dev_hndl); -static void qdma_cpm4_hw_trq_err_process(void *dev_hndl); -static void qdma_cpm4_hw_ram_sbe_err_process(void *dev_hndl); -static void qdma_cpm4_hw_ram_dbe_err_process(void *dev_hndl); - -static struct qdma_cpm4_hw_err_info - qdma_cpm4_err_info[QDMA_CPM4_ERRS_ALL] = { - /* Descriptor errors */ - { - QDMA_CPM4_DSC_ERR_POISON, - "Poison error", - QDMA_CPM4_GLBL_DSC_ERR_MSK_ADDR, - QDMA_CPM4_GLBL_DSC_ERR_STS_ADDR, - GLBL_DSC_ERR_STS_POISON_MASK, - GLBL_ERR_STAT_ERR_DSC_MASK, - &qdma_cpm4_hw_desc_err_process - }, - { - QDMA_CPM4_DSC_ERR_UR_CA, - "Unsupported request or completer aborted error", - QDMA_CPM4_GLBL_DSC_ERR_MSK_ADDR, - QDMA_CPM4_GLBL_DSC_ERR_STS_ADDR, - GLBL_DSC_ERR_STS_UR_CA_MASK, - GLBL_ERR_STAT_ERR_DSC_MASK, - &qdma_cpm4_hw_desc_err_process - }, - { - QDMA_CPM4_DSC_ERR_PARAM, - "Parameter mismatch error", - QDMA_CPM4_GLBL_DSC_ERR_MSK_ADDR, - QDMA_CPM4_GLBL_DSC_ERR_STS_ADDR, - GLBL_DSC_ERR_STS_PARAM_MASK, - GLBL_ERR_STAT_ERR_DSC_MASK, - &qdma_cpm4_hw_desc_err_process - }, - { - QDMA_CPM4_DSC_ERR_ADDR, - "Address mismatch error", - QDMA_CPM4_GLBL_DSC_ERR_MSK_ADDR, - QDMA_CPM4_GLBL_DSC_ERR_STS_ADDR, - GLBL_DSC_ERR_STS_ADDR_MASK, - GLBL_ERR_STAT_ERR_DSC_MASK, - &qdma_cpm4_hw_desc_err_process - }, - { - QDMA_CPM4_DSC_ERR_TAG, - "Unexpected tag error", - QDMA_CPM4_GLBL_DSC_ERR_MSK_ADDR, - QDMA_CPM4_GLBL_DSC_ERR_STS_ADDR, - GLBL_DSC_ERR_STS_TAG_MASK, - GLBL_ERR_STAT_ERR_DSC_MASK, - &qdma_cpm4_hw_desc_err_process - }, - { - QDMA_CPM4_DSC_ERR_FLR, - "FLR error", - QDMA_CPM4_GLBL_DSC_ERR_MSK_ADDR, - QDMA_CPM4_GLBL_DSC_ERR_STS_ADDR, - GLBL_DSC_ERR_STS_FLR_MASK, - GLBL_ERR_STAT_ERR_DSC_MASK, - &qdma_cpm4_hw_desc_err_process - }, - { - QDMA_CPM4_DSC_ERR_TIMEOUT, - "Timed out error", - QDMA_CPM4_GLBL_DSC_ERR_MSK_ADDR, - QDMA_CPM4_GLBL_DSC_ERR_STS_ADDR, - GLBL_DSC_ERR_STS_TIMEOUT_MASK, - GLBL_ERR_STAT_ERR_DSC_MASK, - &qdma_cpm4_hw_desc_err_process - }, - { - QDMA_CPM4_DSC_ERR_DAT_POISON, - "Poison data error", - QDMA_CPM4_GLBL_DSC_ERR_MSK_ADDR, - QDMA_CPM4_GLBL_DSC_ERR_STS_ADDR, - GLBL_DSC_ERR_STS_DAT_POISON_MASK, - GLBL_ERR_STAT_ERR_DSC_MASK, - &qdma_cpm4_hw_desc_err_process - }, - { - QDMA_CPM4_DSC_ERR_FLR_CANCEL, - "Descriptor fetch cancelled due to FLR error", - QDMA_CPM4_GLBL_DSC_ERR_MSK_ADDR, - QDMA_CPM4_GLBL_DSC_ERR_STS_ADDR, - GLBL_DSC_ERR_STS_FLR_CANCEL_MASK, - GLBL_ERR_STAT_ERR_DSC_MASK, - &qdma_cpm4_hw_desc_err_process - }, - { - QDMA_CPM4_DSC_ERR_DMA, - "DMA engine error", - QDMA_CPM4_GLBL_DSC_ERR_MSK_ADDR, - QDMA_CPM4_GLBL_DSC_ERR_STS_ADDR, - GLBL_DSC_ERR_STS_DMA_MASK, - GLBL_ERR_STAT_ERR_DSC_MASK, - &qdma_cpm4_hw_desc_err_process - }, - { - QDMA_CPM4_DSC_ERR_DSC, - "Invalid PIDX update error", - QDMA_CPM4_GLBL_DSC_ERR_MSK_ADDR, - QDMA_CPM4_GLBL_DSC_ERR_STS_ADDR, - GLBL_DSC_ERR_STS_DSC_MASK, - GLBL_ERR_STAT_ERR_DSC_MASK, - &qdma_cpm4_hw_desc_err_process - }, - { - QDMA_CPM4_DSC_ERR_RQ_CANCEL, - "Descriptor fetch cancelled due to disable register status error", - QDMA_CPM4_GLBL_DSC_ERR_MSK_ADDR, - QDMA_CPM4_GLBL_DSC_ERR_STS_ADDR, - GLBL_DSC_ERR_STS_RQ_CANCEL_MASK, - GLBL_ERR_STAT_ERR_DSC_MASK, - &qdma_cpm4_hw_desc_err_process - }, - { - QDMA_CPM4_DSC_ERR_DBE, - "UNC_ERR_RAM_DBE error", - QDMA_CPM4_GLBL_DSC_ERR_MSK_ADDR, - QDMA_CPM4_GLBL_DSC_ERR_STS_ADDR, - GLBL_DSC_ERR_STS_DBE_MASK, - GLBL_ERR_STAT_ERR_DSC_MASK, - &qdma_cpm4_hw_desc_err_process - }, - { - QDMA_CPM4_DSC_ERR_SBE, - "UNC_ERR_RAM_SBE error", - QDMA_CPM4_GLBL_DSC_ERR_MSK_ADDR, - QDMA_CPM4_GLBL_DSC_ERR_STS_ADDR, - GLBL_DSC_ERR_STS_SBE_MASK, - GLBL_ERR_STAT_ERR_DSC_MASK, - &qdma_cpm4_hw_desc_err_process - }, - { - QDMA_CPM4_DSC_ERR_ALL, - "All Descriptor errors", - QDMA_CPM4_GLBL_DSC_ERR_MSK_ADDR, - QDMA_CPM4_GLBL_DSC_ERR_STS_ADDR, - QDMA_CPM4_DBE_ERR_ALL_MASK, - GLBL_ERR_STAT_ERR_DSC_MASK, - &qdma_cpm4_hw_desc_err_process - }, - - /* TRQ errors */ - { - QDMA_CPM4_TRQ_ERR_UNMAPPED, - "Access targeted unmapped register space via CSR pathway error", - QDMA_CPM4_GLBL_TRQ_ERR_MSK_ADDR, - QDMA_CPM4_GLBL_TRQ_ERR_STS_ADDR, - GLBL_TRQ_ERR_STS_UNMAPPED_MASK, - GLBL_ERR_STAT_ERR_TRQ_MASK, - &qdma_cpm4_hw_trq_err_process - }, - { - QDMA_CPM4_TRQ_ERR_QID_RANGE, - "Qid range error", - QDMA_CPM4_GLBL_TRQ_ERR_MSK_ADDR, - QDMA_CPM4_GLBL_TRQ_ERR_STS_ADDR, - GLBL_TRQ_ERR_STS_QID_RANGE_MASK, - GLBL_ERR_STAT_ERR_TRQ_MASK, - &qdma_cpm4_hw_trq_err_process - }, - { - QDMA_CPM4_TRQ_ERR_VF_ACCESS_ERR, - "VF attempted to access Global register space or Function map", - QDMA_CPM4_GLBL_TRQ_ERR_MSK_ADDR, - QDMA_CPM4_GLBL_TRQ_ERR_STS_ADDR, - GLBL_TRQ_ERR_STS_VF_ACCESS_ERR_MASK, - GLBL_ERR_STAT_ERR_TRQ_MASK, - &qdma_cpm4_hw_trq_err_process - }, - { - QDMA_CPM4_TRQ_ERR_TCP_TIMEOUT, - "Timeout on request to dma internal csr register", - QDMA_CPM4_GLBL_TRQ_ERR_MSK_ADDR, - QDMA_CPM4_GLBL_TRQ_ERR_STS_ADDR, - GLBL_TRQ_ERR_STS_TCP_TIMEOUT_MASK, - GLBL_ERR_STAT_ERR_TRQ_MASK, - &qdma_cpm4_hw_trq_err_process - }, - { - QDMA_CPM4_TRQ_ERR_ALL, - "All TRQ errors", - QDMA_CPM4_GLBL_TRQ_ERR_MSK_ADDR, - QDMA_CPM4_GLBL_TRQ_ERR_STS_ADDR, - QDMA_CPM4_GLBL_TRQ_ERR_ALL_MASK, - GLBL_ERR_STAT_ERR_TRQ_MASK, - &qdma_cpm4_hw_trq_err_process - }, - - /* C2H Errors*/ - { - QDMA_CPM4_ST_C2H_ERR_MTY_MISMATCH, - "MTY mismatch error", - QDMA_CPM4_C2H_ERR_MASK_ADDR, - QDMA_CPM4_C2H_ERR_STAT_ADDR, - C2H_ERR_STAT_MTY_MISMATCH_MASK, - GLBL_ERR_STAT_ERR_C2H_ST_MASK, - &qdma_cpm4_hw_st_c2h_err_process - }, - { - QDMA_CPM4_ST_C2H_ERR_LEN_MISMATCH, - "Packet length mismatch error", - QDMA_CPM4_C2H_ERR_MASK_ADDR, - QDMA_CPM4_C2H_ERR_STAT_ADDR, - C2H_ERR_STAT_LEN_MISMATCH_MASK, - GLBL_ERR_STAT_ERR_C2H_ST_MASK, - &qdma_cpm4_hw_st_c2h_err_process - }, - { - QDMA_CPM4_ST_C2H_ERR_QID_MISMATCH, - "Qid mismatch error", - QDMA_CPM4_C2H_ERR_MASK_ADDR, - QDMA_CPM4_C2H_ERR_STAT_ADDR, - C2H_ERR_STAT_QID_MISMATCH_MASK, - GLBL_ERR_STAT_ERR_C2H_ST_MASK, - &qdma_cpm4_hw_st_c2h_err_process - }, - { - QDMA_CPM4_ST_C2H_ERR_DESC_RSP_ERR, - "Descriptor error bit set", - QDMA_CPM4_C2H_ERR_MASK_ADDR, - QDMA_CPM4_C2H_ERR_STAT_ADDR, - C2H_ERR_STAT_DESC_RSP_ERR_MASK, - GLBL_ERR_STAT_ERR_C2H_ST_MASK, - &qdma_cpm4_hw_st_c2h_err_process - }, - { - QDMA_CPM4_ST_C2H_ERR_ENG_WPL_DATA_PAR_ERR, - "Data parity error", - QDMA_CPM4_C2H_ERR_MASK_ADDR, - QDMA_CPM4_C2H_ERR_STAT_ADDR, - C2H_ERR_STAT_ENG_WPL_DATA_PAR_ERR_MASK, - GLBL_ERR_STAT_ERR_C2H_ST_MASK, - &qdma_cpm4_hw_st_c2h_err_process - }, - { - QDMA_CPM4_ST_C2H_ERR_MSI_INT_FAIL, - "MSI got a fail response error", - QDMA_CPM4_C2H_ERR_MASK_ADDR, - QDMA_CPM4_C2H_ERR_STAT_ADDR, - C2H_ERR_STAT_MSI_INT_FAIL_MASK, - GLBL_ERR_STAT_ERR_C2H_ST_MASK, - &qdma_cpm4_hw_st_c2h_err_process - }, - { - QDMA_CPM4_ST_C2H_ERR_ERR_DESC_CNT, - "Descriptor count error", - QDMA_CPM4_C2H_ERR_MASK_ADDR, - QDMA_CPM4_C2H_ERR_STAT_ADDR, - C2H_ERR_STAT_ERR_DESC_CNT_MASK, - GLBL_ERR_STAT_ERR_C2H_ST_MASK, - &qdma_cpm4_hw_st_c2h_err_process - }, - { - QDMA_CPM4_ST_C2H_ERR_PORTID_CTXT_MISMATCH, - "Port id in packet and pfetch ctxt mismatch error", - QDMA_CPM4_C2H_ERR_MASK_ADDR, - QDMA_CPM4_C2H_ERR_STAT_ADDR, - C2H_ERR_STAT_PORT_ID_CTXT_MISMATCH_MASK, - GLBL_ERR_STAT_ERR_C2H_ST_MASK, - &qdma_cpm4_hw_st_c2h_err_process - }, - { - QDMA_CPM4_ST_C2H_ERR_PORTID_BYP_IN_MISMATCH, - "Port id in packet and bypass in mismatch error", - QDMA_CPM4_C2H_ERR_MASK_ADDR, - QDMA_CPM4_C2H_ERR_STAT_ADDR, - C2H_ERR_STAT_PORT_ID_CTXT_MISMATCH_MASK, - GLBL_ERR_STAT_ERR_C2H_ST_MASK, - &qdma_cpm4_hw_st_c2h_err_process - }, - { - QDMA_CPM4_ST_C2H_ERR_WRB_INV_Q_ERR, - "Writeback on invalid queue error", - QDMA_CPM4_C2H_ERR_MASK_ADDR, - QDMA_CPM4_C2H_ERR_STAT_ADDR, - C2H_ERR_STAT_WRB_INV_Q_ERR_MASK, - GLBL_ERR_STAT_ERR_C2H_ST_MASK, - &qdma_cpm4_hw_st_c2h_err_process - }, - { - QDMA_CPM4_ST_C2H_ERR_WRB_QFULL_ERR, - "Completion queue gets full error", - QDMA_CPM4_C2H_ERR_MASK_ADDR, - QDMA_CPM4_C2H_ERR_STAT_ADDR, - C2H_ERR_STAT_WRB_QFULL_ERR_MASK, - GLBL_ERR_STAT_ERR_C2H_ST_MASK, - &qdma_cpm4_hw_st_c2h_err_process - }, - { - QDMA_CPM4_ST_C2H_ERR_WRB_CIDX_ERR, - "Bad CIDX update by the software error", - QDMA_CPM4_C2H_ERR_MASK_ADDR, - QDMA_CPM4_C2H_ERR_STAT_ADDR, - C2H_ERR_STAT_WRB_CIDX_ERR_MASK, - GLBL_ERR_STAT_ERR_C2H_ST_MASK, - &qdma_cpm4_hw_st_c2h_err_process - }, - { - QDMA_CPM4_ST_C2H_ERR_WRB_PRTY_ERR, - "C2H completion Parity error", - QDMA_CPM4_C2H_ERR_MASK_ADDR, - QDMA_CPM4_C2H_ERR_STAT_ADDR, - C2H_ERR_STAT_WRB_PRTY_ERR_MASK, - GLBL_ERR_STAT_ERR_C2H_ST_MASK, - &qdma_cpm4_hw_st_c2h_err_process - }, - { - QDMA_CPM4_ST_C2H_ERR_ALL, - "All C2h errors", - QDMA_CPM4_C2H_ERR_MASK_ADDR, - QDMA_CPM4_C2H_ERR_STAT_ADDR, - QDMA_CPM4_C2H_ERR_ALL_MASK, - GLBL_ERR_STAT_ERR_C2H_ST_MASK, - &qdma_cpm4_hw_st_c2h_err_process - }, - - /* C2H fatal errors */ - { - QDMA_CPM4_ST_FATAL_ERR_MTY_MISMATCH, - "Fatal MTY mismatch error", - QDMA_CPM4_C2H_FATAL_ERR_MASK_ADDR, - QDMA_CPM4_C2H_FATAL_ERR_STAT_ADDR, - C2H_FATAL_ERR_STAT_MTY_MISMATCH_MASK, - GLBL_ERR_STAT_ERR_C2H_ST_MASK, - &qdma_cpm4_hw_st_c2h_err_process - }, - { - QDMA_CPM4_ST_FATAL_ERR_LEN_MISMATCH, - "Fatal Len mismatch error", - QDMA_CPM4_C2H_FATAL_ERR_MASK_ADDR, - QDMA_CPM4_C2H_FATAL_ERR_STAT_ADDR, - C2H_FATAL_ERR_STAT_LEN_MISMATCH_MASK, - GLBL_ERR_STAT_ERR_C2H_ST_MASK, - &qdma_cpm4_hw_st_c2h_err_process - }, - { - QDMA_CPM4_ST_FATAL_ERR_QID_MISMATCH, - "Fatal Qid mismatch error", - QDMA_CPM4_C2H_FATAL_ERR_MASK_ADDR, - QDMA_CPM4_C2H_FATAL_ERR_STAT_ADDR, - C2H_FATAL_ERR_STAT_QID_MISMATCH_MASK, - GLBL_ERR_STAT_ERR_C2H_ST_MASK, - &qdma_cpm4_hw_st_c2h_err_process - }, - { - QDMA_CPM4_ST_FATAL_ERR_TIMER_FIFO_RAM_RDBE, - "RAM double bit fatal error", - QDMA_CPM4_C2H_FATAL_ERR_MASK_ADDR, - QDMA_CPM4_C2H_FATAL_ERR_STAT_ADDR, - C2H_FATAL_ERR_STAT_TIMER_FIFO_RAM_RDBE_MASK, - GLBL_ERR_STAT_ERR_C2H_ST_MASK, - &qdma_cpm4_hw_st_c2h_err_process - }, - { - QDMA_CPM4_ST_FATAL_ERR_PFCH_II_RAM_RDBE, - "RAM double bit fatal error", - QDMA_CPM4_C2H_FATAL_ERR_MASK_ADDR, - QDMA_CPM4_C2H_FATAL_ERR_STAT_ADDR, - C2H_FATAL_ERR_STAT_PFCH_LL_RAM_RDBE_MASK, - GLBL_ERR_STAT_ERR_C2H_ST_MASK, - &qdma_cpm4_hw_st_c2h_err_process - }, - { - QDMA_CPM4_ST_FATAL_ERR_WRB_CTXT_RAM_RDBE, - "RAM double bit fatal error", - QDMA_CPM4_C2H_FATAL_ERR_MASK_ADDR, - QDMA_CPM4_C2H_FATAL_ERR_STAT_ADDR, - C2H_FATAL_ERR_STAT_WRB_CTXT_RAM_RDBE_MASK, - GLBL_ERR_STAT_ERR_C2H_ST_MASK, - &qdma_cpm4_hw_st_c2h_err_process - }, - { - QDMA_CPM4_ST_FATAL_ERR_PFCH_CTXT_RAM_RDBE, - "RAM double bit fatal error", - QDMA_CPM4_C2H_FATAL_ERR_MASK_ADDR, - QDMA_CPM4_C2H_FATAL_ERR_STAT_ADDR, - C2H_FATAL_ERR_STAT_PFCH_CTXT_RAM_RDBE_MASK, - GLBL_ERR_STAT_ERR_C2H_ST_MASK, - &qdma_cpm4_hw_st_c2h_err_process - }, - { - QDMA_CPM4_ST_FATAL_ERR_DESC_REQ_FIFO_RAM_RDBE, - "RAM double bit fatal error", - QDMA_CPM4_C2H_FATAL_ERR_MASK_ADDR, - QDMA_CPM4_C2H_FATAL_ERR_STAT_ADDR, - C2H_FATAL_ERR_STAT_DESC_REQ_FIFO_RAM_RDBE_MASK, - GLBL_ERR_STAT_ERR_C2H_ST_MASK, - &qdma_cpm4_hw_st_c2h_err_process - }, - { - QDMA_CPM4_ST_FATAL_ERR_INT_CTXT_RAM_RDBE, - "RAM double bit fatal error", - QDMA_CPM4_C2H_FATAL_ERR_MASK_ADDR, - QDMA_CPM4_C2H_FATAL_ERR_STAT_ADDR, - C2H_FATAL_ERR_STAT_INT_CTXT_RAM_RDBE_MASK, - GLBL_ERR_STAT_ERR_C2H_ST_MASK, - &qdma_cpm4_hw_st_c2h_err_process - }, - { - QDMA_CPM4_ST_FATAL_ERR_INT_QID2VEC_RAM_RDBE, - "RAM double bit fatal error", - QDMA_CPM4_C2H_FATAL_ERR_MASK_ADDR, - QDMA_CPM4_C2H_FATAL_ERR_STAT_ADDR, - C2H_FATAL_ERR_STAT_INT_QID2VEC_RAM_RDBE_MASK, - GLBL_ERR_STAT_ERR_C2H_ST_MASK, - &qdma_cpm4_hw_st_c2h_err_process - }, - { - QDMA_CPM4_ST_FATAL_ERR_WRB_COAL_DATA_RAM_RDBE, - "RAM double bit fatal error", - QDMA_CPM4_C2H_FATAL_ERR_MASK_ADDR, - QDMA_CPM4_C2H_FATAL_ERR_STAT_ADDR, - C2H_FATAL_ERR_STAT_WRB_COAL_DATA_RAM_RDBE_MASK, - GLBL_ERR_STAT_ERR_C2H_ST_MASK, - &qdma_cpm4_hw_st_c2h_err_process - }, - { - QDMA_CPM4_ST_FATAL_ERR_TUSER_FIFO_RAM_RDBE, - "RAM double bit fatal error", - QDMA_CPM4_C2H_FATAL_ERR_MASK_ADDR, - QDMA_CPM4_C2H_FATAL_ERR_STAT_ADDR, - C2H_FATAL_ERR_STAT_TUSER_FIFO_RAM_RDBE_MASK, - GLBL_ERR_STAT_ERR_C2H_ST_MASK, - &qdma_cpm4_hw_st_c2h_err_process - }, - { - QDMA_CPM4_ST_FATAL_ERR_QID_FIFO_RAM_RDBE, - "RAM double bit fatal error", - QDMA_CPM4_C2H_FATAL_ERR_MASK_ADDR, - QDMA_CPM4_C2H_FATAL_ERR_STAT_ADDR, - C2H_FATAL_ERR_STAT_QID_FIFO_RAM_RDBE_MASK, - GLBL_ERR_STAT_ERR_C2H_ST_MASK, - &qdma_cpm4_hw_st_c2h_err_process - }, - { - QDMA_CPM4_ST_FATAL_ERR_PAYLOAD_FIFO_RAM_RDBE, - "RAM double bit fatal error", - QDMA_CPM4_C2H_FATAL_ERR_MASK_ADDR, - QDMA_CPM4_C2H_FATAL_ERR_STAT_ADDR, - C2H_FATAL_ERR_STAT_PLD_FIFO_RAM_RDBE_MASK, - GLBL_ERR_STAT_ERR_C2H_ST_MASK, - &qdma_cpm4_hw_st_c2h_err_process - }, - { - QDMA_CPM4_ST_FATAL_ERR_WPL_DATA_PAR_ERR, - "RAM double bit fatal error", - QDMA_CPM4_C2H_FATAL_ERR_MASK_ADDR, - QDMA_CPM4_C2H_FATAL_ERR_STAT_ADDR, - C2H_FATAL_ERR_STAT_WPL_DATA_PAR_ERR_MASK, - GLBL_ERR_STAT_ERR_C2H_ST_MASK, - &qdma_cpm4_hw_st_c2h_err_process - }, - { - QDMA_CPM4_ST_FATAL_ERR_ALL, - "All fatal errors", - QDMA_CPM4_C2H_FATAL_ERR_MASK_ADDR, - QDMA_CPM4_C2H_FATAL_ERR_STAT_ADDR, - QDMA_CPM4_C2H_FATAL_ERR_ALL_MASK, - GLBL_ERR_STAT_ERR_C2H_ST_MASK, - &qdma_cpm4_hw_st_c2h_err_process - }, - - /* H2C St errors */ - { - QDMA_CPM4_ST_H2C_ERR_ZERO_LEN_DESC_ERR, - "Zero length descriptor error", - QDMA_CPM4_H2C_ERR_MASK_ADDR, - QDMA_CPM4_H2C_ERR_STAT_ADDR, - H2C_ERR_STAT_ZERO_LEN_DS_MASK, - GLBL_ERR_STAT_ERR_H2C_ST_MASK, - &qdma_cpm4_hw_st_h2c_err_process - }, - { - QDMA_CPM4_ST_H2C_ERR_SDI_MRKR_REQ_MOP_ERR, - "A non-EOP descriptor received", - QDMA_CPM4_H2C_ERR_MASK_ADDR, - QDMA_CPM4_H2C_ERR_STAT_ADDR, - H2C_ERR_STAT_SDI_MRKR_REQ_MOP_ERR_MASK, - GLBL_ERR_STAT_ERR_H2C_ST_MASK, - &qdma_cpm4_hw_st_h2c_err_process - }, - { - QDMA_CPM4_ST_H2C_ERR_NO_DMA_DSC, - "No DMA descriptor received error", - QDMA_CPM4_H2C_ERR_MASK_ADDR, - QDMA_CPM4_H2C_ERR_STAT_ADDR, - H2C_ERR_STAT_NO_DMA_DS_MASK, - GLBL_ERR_STAT_ERR_H2C_ST_MASK, - &qdma_cpm4_hw_st_h2c_err_process - }, - { - QDMA_CPM4_ST_H2C_ERR_DBE, - "Double bit error detected on H2C-ST data error", - QDMA_CPM4_H2C_ERR_MASK_ADDR, - QDMA_CPM4_H2C_ERR_STAT_ADDR, - H2C_ERR_STAT_DBE_MASK, - GLBL_ERR_STAT_ERR_H2C_ST_MASK, - &qdma_cpm4_hw_st_h2c_err_process - }, - { - QDMA_CPM4_ST_H2C_ERR_SBE, - "Single bit error detected on H2C-ST data error", - QDMA_CPM4_H2C_ERR_MASK_ADDR, - QDMA_CPM4_H2C_ERR_STAT_ADDR, - H2C_ERR_STAT_SBE_MASK, - GLBL_ERR_STAT_ERR_H2C_ST_MASK, - &qdma_cpm4_hw_st_h2c_err_process - }, - { - QDMA_CPM4_ST_H2C_ERR_ALL, - "All H2C errors", - QDMA_CPM4_H2C_ERR_MASK_ADDR, - QDMA_CPM4_H2C_ERR_STAT_ADDR, - QDMA_CPM4_H2C_ERR_ALL_MASK, - GLBL_ERR_STAT_ERR_H2C_ST_MASK, - &qdma_cpm4_hw_st_h2c_err_process - }, - - /* SBE errors */ - { - QDMA_CPM4_SBE_ERR_MI_H2C0_DAT, - "H2C MM data buffer single bit ECC error", - QDMA_CPM4_RAM_SBE_MSK_A_ADDR, - QDMA_CPM4_RAM_SBE_STS_A_ADDR, - RAM_SBE_STS_A_MI_H2C0_DAT_MASK, - GLBL_ERR_STAT_ERR_RAM_SBE_MASK, - &qdma_cpm4_hw_ram_sbe_err_process - }, - { - QDMA_CPM4_SBE_ERR_MI_C2H0_DAT, - "C2H MM data buffer single bit ECC error", - QDMA_CPM4_RAM_SBE_MSK_A_ADDR, - QDMA_CPM4_RAM_SBE_STS_A_ADDR, - RAM_SBE_STS_A_MI_C2H0_DAT_MASK, - GLBL_ERR_STAT_ERR_RAM_SBE_MASK, - &qdma_cpm4_hw_ram_sbe_err_process - }, - { - QDMA_CPM4_SBE_ERR_H2C_RD_BRG_DAT, - "Bridge master read single bit ECC error", - QDMA_CPM4_RAM_SBE_MSK_A_ADDR, - QDMA_CPM4_RAM_SBE_STS_A_ADDR, - RAM_SBE_STS_A_H2C_RD_BRG_DAT_MASK, - GLBL_ERR_STAT_ERR_RAM_SBE_MASK, - &qdma_cpm4_hw_ram_sbe_err_process - }, - { - QDMA_CPM4_SBE_ERR_H2C_WR_BRG_DAT, - "Bridge master write single bit ECC error", - QDMA_CPM4_RAM_SBE_MSK_A_ADDR, - QDMA_CPM4_RAM_SBE_STS_A_ADDR, - RAM_SBE_STS_A_H2C_WR_BRG_DAT_MASK, - GLBL_ERR_STAT_ERR_RAM_SBE_MASK, - &qdma_cpm4_hw_ram_sbe_err_process - }, - { - QDMA_CPM4_SBE_ERR_C2H_RD_BRG_DAT, - "Bridge slave read data buffer single bit ECC error", - QDMA_CPM4_RAM_SBE_MSK_A_ADDR, - QDMA_CPM4_RAM_SBE_STS_A_ADDR, - RAM_SBE_STS_A_C2H_RD_BRG_DAT_MASK, - GLBL_ERR_STAT_ERR_RAM_SBE_MASK, - &qdma_cpm4_hw_ram_sbe_err_process - }, - { - QDMA_CPM4_SBE_ERR_C2H_WR_BRG_DAT, - "Bridge slave write data buffer single bit ECC error", - QDMA_CPM4_RAM_SBE_MSK_A_ADDR, - QDMA_CPM4_RAM_SBE_STS_A_ADDR, - RAM_SBE_STS_A_C2H_WR_BRG_DAT_MASK, - GLBL_ERR_STAT_ERR_RAM_SBE_MASK, - &qdma_cpm4_hw_ram_sbe_err_process - }, - { - QDMA_CPM4_SBE_ERR_FUNC_MAP, - "Function map RAM single bit ECC error", - QDMA_CPM4_RAM_SBE_MSK_A_ADDR, - QDMA_CPM4_RAM_SBE_STS_A_ADDR, - RAM_SBE_STS_A_FUNC_MAP_MASK, - GLBL_ERR_STAT_ERR_RAM_SBE_MASK, - &qdma_cpm4_hw_ram_sbe_err_process - }, - { - QDMA_CPM4_SBE_ERR_DSC_HW_CTXT, - "Descriptor engine hardware context RAM single bit ECC error", - QDMA_CPM4_RAM_SBE_MSK_A_ADDR, - QDMA_CPM4_RAM_SBE_STS_A_ADDR, - RAM_SBE_STS_A_DSC_HW_CTXT_MASK, - GLBL_ERR_STAT_ERR_RAM_SBE_MASK, - &qdma_cpm4_hw_ram_sbe_err_process - }, - { - QDMA_CPM4_SBE_ERR_DSC_CRD_RCV, - "Descriptor engine receive credit context RAM single bit ECC error", - QDMA_CPM4_RAM_SBE_MSK_A_ADDR, - QDMA_CPM4_RAM_SBE_STS_A_ADDR, - RAM_SBE_STS_A_DSC_CRD_RCV_MASK, - GLBL_ERR_STAT_ERR_RAM_SBE_MASK, - &qdma_cpm4_hw_ram_sbe_err_process - }, - { - QDMA_CPM4_SBE_ERR_DSC_SW_CTXT, - "Descriptor engine software context RAM single bit ECC error", - QDMA_CPM4_RAM_SBE_MSK_A_ADDR, - QDMA_CPM4_RAM_SBE_STS_A_ADDR, - RAM_SBE_STS_A_DSC_SW_CTXT_MASK, - GLBL_ERR_STAT_ERR_RAM_SBE_MASK, - &qdma_cpm4_hw_ram_sbe_err_process - }, - { - QDMA_CPM4_SBE_ERR_DSC_CPLI, - "Descriptor engine fetch completion information RAM single bit ECC error", - QDMA_CPM4_RAM_SBE_MSK_A_ADDR, - QDMA_CPM4_RAM_SBE_STS_A_ADDR, - RAM_SBE_STS_A_DSC_CPLI_MASK, - GLBL_ERR_STAT_ERR_RAM_SBE_MASK, - &qdma_cpm4_hw_ram_sbe_err_process - }, - { - QDMA_CPM4_SBE_ERR_DSC_CPLD, - "Descriptor engine fetch completion data RAM single bit ECC error", - QDMA_CPM4_RAM_SBE_MSK_A_ADDR, - QDMA_CPM4_RAM_SBE_STS_A_ADDR, - RAM_SBE_STS_A_DSC_CPLD_MASK, - GLBL_ERR_STAT_ERR_RAM_SBE_MASK, - &qdma_cpm4_hw_ram_sbe_err_process - }, - { - QDMA_CPM4_SBE_ERR_PASID_CTXT_RAM, - "Pasid ctxt FIFO RAM single bit ECC error", - QDMA_CPM4_RAM_SBE_MSK_A_ADDR, - QDMA_CPM4_RAM_SBE_STS_A_ADDR, - RAM_SBE_STS_A_PASID_CTXT_RAM_MASK, - GLBL_ERR_STAT_ERR_RAM_SBE_MASK, - &qdma_cpm4_hw_ram_sbe_err_process - }, - { - QDMA_CPM4_SBE_ERR_TIMER_FIFO_RAM, - "Timer fifo RAM single bit ECC error", - QDMA_CPM4_RAM_SBE_MSK_A_ADDR, - QDMA_CPM4_RAM_SBE_STS_A_ADDR, - RAM_SBE_STS_A_TIMER_FIFO_RAM_MASK, - GLBL_ERR_STAT_ERR_RAM_SBE_MASK, - &qdma_cpm4_hw_ram_sbe_err_process - }, - { - QDMA_CPM4_SBE_ERR_PAYLOAD_FIFO_RAM, - "C2H ST payload FIFO RAM single bit ECC error", - QDMA_CPM4_RAM_SBE_MSK_A_ADDR, - QDMA_CPM4_RAM_SBE_STS_A_ADDR, - RAM_SBE_STS_A_PLD_FIFO_RAM_MASK, - GLBL_ERR_STAT_ERR_RAM_SBE_MASK, - &qdma_cpm4_hw_ram_sbe_err_process - }, - { - QDMA_CPM4_SBE_ERR_QID_FIFO_RAM, - "C2H ST QID FIFO RAM single bit ECC error", - QDMA_CPM4_RAM_SBE_MSK_A_ADDR, - QDMA_CPM4_RAM_SBE_STS_A_ADDR, - RAM_SBE_STS_A_QID_FIFO_RAM_MASK, - GLBL_ERR_STAT_ERR_RAM_SBE_MASK, - &qdma_cpm4_hw_ram_sbe_err_process - }, - { - QDMA_CPM4_SBE_ERR_TUSER_FIFO_RAM, - "C2H ST TUSER FIFO RAM single bit ECC error", - QDMA_CPM4_RAM_SBE_MSK_A_ADDR, - QDMA_CPM4_RAM_SBE_STS_A_ADDR, - RAM_SBE_STS_A_TUSER_FIFO_RAM_MASK, - GLBL_ERR_STAT_ERR_RAM_SBE_MASK, - &qdma_cpm4_hw_ram_sbe_err_process - }, - { - QDMA_CPM4_SBE_ERR_WRB_COAL_DATA_RAM, - "Writeback Coalescing RAM single bit ECC error", - QDMA_CPM4_RAM_SBE_MSK_A_ADDR, - QDMA_CPM4_RAM_SBE_STS_A_ADDR, - RAM_SBE_STS_A_WRB_COAL_DATA_RAM_MASK, - GLBL_ERR_STAT_ERR_RAM_SBE_MASK, - &qdma_cpm4_hw_ram_sbe_err_process - }, - { - QDMA_CPM4_SBE_ERR_INT_QID2VEC_RAM, - "Interrupt QID2VEC RAM single bit ECC error", - QDMA_CPM4_RAM_SBE_MSK_A_ADDR, - QDMA_CPM4_RAM_SBE_STS_A_ADDR, - RAM_SBE_STS_A_INT_QID2VEC_RAM_MASK, - GLBL_ERR_STAT_ERR_RAM_SBE_MASK, - &qdma_cpm4_hw_ram_sbe_err_process - }, - { - QDMA_CPM4_SBE_ERR_INT_CTXT_RAM, - "Interrupt context RAM single bit ECC error", - QDMA_CPM4_RAM_SBE_MSK_A_ADDR, - QDMA_CPM4_RAM_SBE_STS_A_ADDR, - RAM_SBE_STS_A_INT_CTXT_RAM_MASK, - GLBL_ERR_STAT_ERR_RAM_SBE_MASK, - &qdma_cpm4_hw_ram_sbe_err_process - }, - { - QDMA_CPM4_SBE_ERR_DESC_REQ_FIFO_RAM, - "C2H ST descriptor request RAM single bit ECC error", - QDMA_CPM4_RAM_SBE_MSK_A_ADDR, - QDMA_CPM4_RAM_SBE_STS_A_ADDR, - RAM_SBE_STS_A_DESC_REQ_FIFO_RAM_MASK, - GLBL_ERR_STAT_ERR_RAM_SBE_MASK, - &qdma_cpm4_hw_ram_sbe_err_process - }, - { - QDMA_CPM4_SBE_ERR_PFCH_CTXT_RAM, - "C2H ST prefetch RAM single bit ECC error", - QDMA_CPM4_RAM_SBE_MSK_A_ADDR, - QDMA_CPM4_RAM_SBE_STS_A_ADDR, - RAM_SBE_STS_A_PFCH_CTXT_RAM_MASK, - GLBL_ERR_STAT_ERR_RAM_SBE_MASK, - &qdma_cpm4_hw_ram_sbe_err_process - }, - { - QDMA_CPM4_SBE_ERR_WRB_CTXT_RAM, - "C2H ST completion context RAM single bit ECC error", - QDMA_CPM4_RAM_SBE_MSK_A_ADDR, - QDMA_CPM4_RAM_SBE_STS_A_ADDR, - RAM_SBE_STS_A_WRB_CTXT_RAM_MASK, - GLBL_ERR_STAT_ERR_RAM_SBE_MASK, - &qdma_cpm4_hw_ram_sbe_err_process - }, - { - QDMA_CPM4_SBE_ERR_PFCH_LL_RAM, - "C2H ST prefetch list RAM single bit ECC error", - QDMA_CPM4_RAM_SBE_MSK_A_ADDR, - QDMA_CPM4_RAM_SBE_STS_A_ADDR, - RAM_SBE_STS_A_PFCH_LL_RAM_MASK, - GLBL_ERR_STAT_ERR_RAM_SBE_MASK, - &qdma_cpm4_hw_ram_sbe_err_process - }, - { - QDMA_CPM4_SBE_ERR_ALL, - "All SBE errors", - QDMA_CPM4_RAM_SBE_MSK_A_ADDR, - QDMA_CPM4_RAM_SBE_STS_A_ADDR, - QDMA_CPM4_SBE_ERR_ALL_MASK, - GLBL_ERR_STAT_ERR_RAM_SBE_MASK, - &qdma_cpm4_hw_ram_sbe_err_process - }, - - - /* DBE errors */ - { - QDMA_CPM4_DBE_ERR_MI_H2C0_DAT, - "H2C MM data buffer single bit ECC error", - QDMA_CPM4_RAM_DBE_MSK_A_ADDR, - QDMA_CPM4_RAM_DBE_STS_A_ADDR, - RAM_DBE_STS_A_MI_H2C0_DAT_MASK, - GLBL_ERR_STAT_ERR_RAM_DBE_MASK, - &qdma_cpm4_hw_ram_dbe_err_process - }, - { - QDMA_CPM4_DBE_ERR_MI_C2H0_DAT, - "C2H MM data buffer single bit ECC error", - QDMA_CPM4_RAM_DBE_MSK_A_ADDR, - QDMA_CPM4_RAM_DBE_STS_A_ADDR, - RAM_DBE_STS_A_MI_C2H0_DAT_MASK, - GLBL_ERR_STAT_ERR_RAM_DBE_MASK, - &qdma_cpm4_hw_ram_dbe_err_process - }, - { - QDMA_CPM4_DBE_ERR_H2C_RD_BRG_DAT, - "Bridge master read single bit ECC error", - QDMA_CPM4_RAM_DBE_MSK_A_ADDR, - QDMA_CPM4_RAM_DBE_STS_A_ADDR, - RAM_DBE_STS_A_H2C_RD_BRG_DAT_MASK, - GLBL_ERR_STAT_ERR_RAM_DBE_MASK, - &qdma_cpm4_hw_ram_dbe_err_process - }, - { - QDMA_CPM4_DBE_ERR_H2C_WR_BRG_DAT, - "Bridge master write single bit ECC error", - QDMA_CPM4_RAM_DBE_MSK_A_ADDR, - QDMA_CPM4_RAM_DBE_STS_A_ADDR, - RAM_DBE_STS_A_H2C_WR_BRG_DAT_MASK, - GLBL_ERR_STAT_ERR_RAM_DBE_MASK, - &qdma_cpm4_hw_ram_dbe_err_process - }, - { - QDMA_CPM4_DBE_ERR_C2H_RD_BRG_DAT, - "Bridge slave read data buffer single bit ECC error", - QDMA_CPM4_RAM_DBE_MSK_A_ADDR, - QDMA_CPM4_RAM_DBE_STS_A_ADDR, - RAM_DBE_STS_A_C2H_RD_BRG_DAT_MASK, - GLBL_ERR_STAT_ERR_RAM_DBE_MASK, - &qdma_cpm4_hw_ram_dbe_err_process - }, - { - QDMA_CPM4_DBE_ERR_C2H_WR_BRG_DAT, - "Bridge slave write data buffer single bit ECC error", - QDMA_CPM4_RAM_DBE_MSK_A_ADDR, - QDMA_CPM4_RAM_DBE_STS_A_ADDR, - RAM_DBE_STS_A_C2H_WR_BRG_DAT_MASK, - GLBL_ERR_STAT_ERR_RAM_DBE_MASK, - &qdma_cpm4_hw_ram_dbe_err_process - }, - { - QDMA_CPM4_DBE_ERR_FUNC_MAP, - "Function map RAM single bit ECC error", - QDMA_CPM4_RAM_DBE_MSK_A_ADDR, - QDMA_CPM4_RAM_DBE_STS_A_ADDR, - RAM_DBE_STS_A_FUNC_MAP_MASK, - GLBL_ERR_STAT_ERR_RAM_DBE_MASK, - &qdma_cpm4_hw_ram_dbe_err_process - }, - { - QDMA_CPM4_DBE_ERR_DSC_HW_CTXT, - "Descriptor engine hardware context RAM single bit ECC error", - QDMA_CPM4_RAM_DBE_MSK_A_ADDR, - QDMA_CPM4_RAM_DBE_STS_A_ADDR, - RAM_DBE_STS_A_DSC_HW_CTXT_MASK, - GLBL_ERR_STAT_ERR_RAM_DBE_MASK, - &qdma_cpm4_hw_ram_dbe_err_process - }, - { - QDMA_CPM4_DBE_ERR_DSC_CRD_RCV, - "Descriptor engine receive credit context RAM single bit ECC error", - QDMA_CPM4_RAM_DBE_MSK_A_ADDR, - QDMA_CPM4_RAM_DBE_STS_A_ADDR, - RAM_DBE_STS_A_DSC_CRD_RCV_MASK, - GLBL_ERR_STAT_ERR_RAM_DBE_MASK, - &qdma_cpm4_hw_ram_dbe_err_process - }, - { - QDMA_CPM4_DBE_ERR_DSC_SW_CTXT, - "Descriptor engine software context RAM single bit ECC error", - QDMA_CPM4_RAM_DBE_MSK_A_ADDR, - QDMA_CPM4_RAM_DBE_STS_A_ADDR, - RAM_DBE_STS_A_DSC_SW_CTXT_MASK, - GLBL_ERR_STAT_ERR_RAM_DBE_MASK, - &qdma_cpm4_hw_ram_dbe_err_process - }, - { - QDMA_CPM4_DBE_ERR_DSC_CPLI, - "Descriptor engine fetch completion information RAM single bit ECC error", - QDMA_CPM4_RAM_DBE_MSK_A_ADDR, - QDMA_CPM4_RAM_DBE_STS_A_ADDR, - RAM_DBE_STS_A_DSC_CPLI_MASK, - GLBL_ERR_STAT_ERR_RAM_DBE_MASK, - &qdma_cpm4_hw_ram_dbe_err_process - }, - { - QDMA_CPM4_DBE_ERR_DSC_CPLD, - "Descriptor engine fetch completion data RAM single bit ECC error", - QDMA_CPM4_RAM_DBE_MSK_A_ADDR, - QDMA_CPM4_RAM_DBE_STS_A_ADDR, - RAM_DBE_STS_A_DSC_CPLD_MASK, - GLBL_ERR_STAT_ERR_RAM_DBE_MASK, - &qdma_cpm4_hw_ram_dbe_err_process - }, - { - QDMA_CPM4_DBE_ERR_PASID_CTXT_RAM, - "PASID CTXT RAM single bit ECC error", - QDMA_CPM4_RAM_DBE_MSK_A_ADDR, - QDMA_CPM4_RAM_DBE_STS_A_ADDR, - RAM_DBE_STS_A_PASID_CTXT_RAM_MASK, - GLBL_ERR_STAT_ERR_RAM_DBE_MASK, - &qdma_cpm4_hw_ram_dbe_err_process - }, - { - QDMA_CPM4_DBE_ERR_TIMER_FIFO_RAM, - "Timer fifo RAM single bit ECC error", - QDMA_CPM4_RAM_DBE_MSK_A_ADDR, - QDMA_CPM4_RAM_DBE_STS_A_ADDR, - RAM_DBE_STS_A_TIMER_FIFO_RAM_MASK, - GLBL_ERR_STAT_ERR_RAM_DBE_MASK, - &qdma_cpm4_hw_ram_dbe_err_process - }, - { - QDMA_CPM4_DBE_ERR_PAYLOAD_FIFO_RAM, - "Payload fifo RAM single bit ECC error", - QDMA_CPM4_RAM_DBE_MSK_A_ADDR, - QDMA_CPM4_RAM_DBE_STS_A_ADDR, - RAM_DBE_STS_A_PLD_FIFO_RAM_MASK, - GLBL_ERR_STAT_ERR_RAM_DBE_MASK, - &qdma_cpm4_hw_ram_dbe_err_process - }, - { - QDMA_CPM4_DBE_ERR_QID_FIFO_RAM, - "C2H ST QID FIFO RAM single bit ECC error", - QDMA_CPM4_RAM_DBE_MSK_A_ADDR, - QDMA_CPM4_RAM_DBE_STS_A_ADDR, - RAM_DBE_STS_A_QID_FIFO_RAM_MASK, - GLBL_ERR_STAT_ERR_RAM_DBE_MASK, - &qdma_cpm4_hw_ram_dbe_err_process - }, - { - QDMA_CPM4_DBE_ERR_WRB_COAL_DATA_RAM, - "Writeback Coalescing RAM single bit ECC error", - QDMA_CPM4_RAM_DBE_MSK_A_ADDR, - QDMA_CPM4_RAM_DBE_STS_A_ADDR, - RAM_DBE_STS_A_WRB_COAL_DATA_RAM_MASK, - GLBL_ERR_STAT_ERR_RAM_DBE_MASK, - &qdma_cpm4_hw_ram_dbe_err_process - }, - { - QDMA_CPM4_DBE_ERR_INT_QID2VEC_RAM, - "QID2VEC RAM single bit ECC error", - QDMA_CPM4_RAM_DBE_MSK_A_ADDR, - QDMA_CPM4_RAM_DBE_STS_A_ADDR, - RAM_DBE_STS_A_INT_QID2VEC_RAM_MASK, - GLBL_ERR_STAT_ERR_RAM_DBE_MASK, - &qdma_cpm4_hw_ram_dbe_err_process - }, - { - QDMA_CPM4_DBE_ERR_INT_CTXT_RAM, - "Interrupt context RAM single bit ECC error", - QDMA_CPM4_RAM_DBE_MSK_A_ADDR, - QDMA_CPM4_RAM_DBE_STS_A_ADDR, - RAM_DBE_STS_A_INT_CTXT_RAM_MASK, - GLBL_ERR_STAT_ERR_RAM_DBE_MASK, - &qdma_cpm4_hw_ram_dbe_err_process - }, - { - QDMA_CPM4_DBE_ERR_DESC_REQ_FIFO_RAM, - "C2H ST descriptor request RAM single bit ECC error", - QDMA_CPM4_RAM_DBE_MSK_A_ADDR, - QDMA_CPM4_RAM_DBE_STS_A_ADDR, - RAM_DBE_STS_A_DESC_REQ_FIFO_RAM_MASK, - GLBL_ERR_STAT_ERR_RAM_DBE_MASK, - &qdma_cpm4_hw_ram_dbe_err_process - }, - { - QDMA_CPM4_DBE_ERR_PFCH_CTXT_RAM, - "C2H ST prefetch RAM single bit ECC error", - QDMA_CPM4_RAM_DBE_MSK_A_ADDR, - QDMA_CPM4_RAM_DBE_STS_A_ADDR, - RAM_DBE_STS_A_PFCH_CTXT_RAM_MASK, - GLBL_ERR_STAT_ERR_RAM_DBE_MASK, - &qdma_cpm4_hw_ram_dbe_err_process - }, - { - QDMA_CPM4_DBE_ERR_WRB_CTXT_RAM, - "C2H ST completion context RAM single bit ECC error", - QDMA_CPM4_RAM_DBE_MSK_A_ADDR, - QDMA_CPM4_RAM_DBE_STS_A_ADDR, - RAM_DBE_STS_A_WRB_CTXT_RAM_MASK, - GLBL_ERR_STAT_ERR_RAM_DBE_MASK, - &qdma_cpm4_hw_ram_dbe_err_process - }, - { - QDMA_CPM4_DBE_ERR_PFCH_LL_RAM, - "C2H ST prefetch list RAM single bit ECC error", - QDMA_CPM4_RAM_DBE_MSK_A_ADDR, - QDMA_CPM4_RAM_DBE_STS_A_ADDR, - RAM_DBE_STS_A_PFCH_LL_RAM_MASK, - GLBL_ERR_STAT_ERR_RAM_DBE_MASK, - &qdma_cpm4_hw_ram_dbe_err_process - }, - { - QDMA_CPM4_DBE_ERR_ALL, - "All DBE errors", - QDMA_CPM4_RAM_DBE_MSK_A_ADDR, - QDMA_CPM4_RAM_DBE_STS_A_ADDR, - QDMA_CPM4_DBE_ERR_ALL_MASK, - GLBL_ERR_STAT_ERR_RAM_DBE_MASK, - &qdma_cpm4_hw_ram_dbe_err_process - } -}; - -static int32_t all_qdma_cpm4_hw_errs[ - QDMA_CPM4_TOTAL_LEAF_ERROR_AGGREGATORS] = { - - QDMA_CPM4_DSC_ERR_ALL, - QDMA_CPM4_TRQ_ERR_ALL, - QDMA_CPM4_ST_C2H_ERR_ALL, - QDMA_CPM4_ST_FATAL_ERR_ALL, - QDMA_CPM4_ST_H2C_ERR_ALL, - QDMA_CPM4_SBE_ERR_ALL, - QDMA_CPM4_DBE_ERR_ALL -}; - - - -union qdma_cpm4_ind_ctxt_cmd { - uint32_t word; - struct { - uint32_t busy:1; - uint32_t sel:4; - uint32_t op:2; - uint32_t qid:11; - uint32_t rsvd:14; - } bits; -}; - -struct qdma_cpm4_indirect_ctxt_regs { - uint32_t qdma_ind_ctxt_data[QDMA_CPM4_IND_CTXT_DATA_NUM_REGS]; - uint32_t qdma_ind_ctxt_mask[QDMA_CPM4_IND_CTXT_DATA_NUM_REGS]; - union qdma_cpm4_ind_ctxt_cmd cmd; -}; - -static struct qctx_entry qdma_cpm4_sw_ctxt_entries[] = { - {"PIDX", 0}, - {"IRQ Arm", 0}, - {"Queue Enable", 0}, - {"Fetch Credit Enable", 0}, - {"Write back/Intr Check", 0}, - {"Write back/Intr Interval", 0}, - {"Function Id", 0}, - {"Ring Size", 0}, - {"Descriptor Size", 0}, - {"Bypass Enable", 0}, - {"MM Channel", 0}, - {"Writeback Enable", 0}, - {"Interrupt Enable", 0}, - {"Port Id", 0}, - {"Interrupt No Last", 0}, - {"Error", 0}, - {"Writeback Error Sent", 0}, - {"IRQ Request", 0}, - {"Marker Disable", 0}, - {"Is Memory Mapped", 0}, - {"Descriptor Ring Base Addr (Low)", 0}, - {"Descriptor Ring Base Addr (High)", 0}, -}; - -static struct qctx_entry qdma_cpm4_hw_ctxt_entries[] = { - {"CIDX", 0}, - {"Credits Consumed", 0}, - {"Descriptors Pending", 0}, - {"Queue Invalid No Desc Pending", 0}, - {"Eviction Pending", 0}, - {"Fetch Pending", 0}, -}; - -static struct qctx_entry qdma_cpm4_credit_ctxt_entries[] = { - {"Credit", 0}, -}; - -static struct qctx_entry qdma_cpm4_fmap_ctxt_entries[] = { - {"Queue Base", 0}, - {"Queue Max", 0}, -}; - -static struct qctx_entry qdma_cpm4_cmpt_ctxt_entries[] = { - {"Enable Status Desc Update", 0}, - {"Enable Interrupt", 0}, - {"Trigger Mode", 0}, - {"Function Id", 0}, - {"Counter Index", 0}, - {"Timer Index", 0}, - {"Interrupt State", 0}, - {"Color", 0}, - {"Ring Size", 0}, - {"Base Address (Low)", 0}, - {"Base Address (High)", 0}, - {"Descriptor Size", 0}, - {"PIDX", 0}, - {"CIDX", 0}, - {"Valid", 0}, - {"Error", 0}, - {"Trigger Pending", 0}, - {"Timer Running", 0}, - {"Full Update", 0}, -}; - -static struct qctx_entry qdma_cpm4_c2h_pftch_ctxt_entries[] = { - {"Bypass", 0}, - {"Buffer Size Index", 0}, - {"Port Id", 0}, - {"Error", 0}, - {"Prefetch Enable", 0}, - {"In Prefetch", 0}, - {"Software Credit", 0}, - {"Valid", 0}, -}; - -static struct qctx_entry qdma_cpm4_qid2vec_ctxt_entries[] = { - {"c2h_vector", 0}, - {"c2h_en_coal", 0}, - {"h2c_vector", 0}, - {"h2c_en_coal", 0}, -}; - -static struct qctx_entry qdma_cpm4_ind_intr_ctxt_entries[] = { - {"valid", 0}, - {"vec", 0}, - {"int_st", 0}, - {"color", 0}, - {"baddr_4k (Low)", 0}, - {"baddr_4k (High)", 0}, - {"page_size", 0}, - {"pidx", 0}, -}; - -static int qdma_cpm4_indirect_reg_invalidate(void *dev_hndl, - enum ind_ctxt_cmd_sel sel, uint16_t hw_qid); -static int qdma_cpm4_indirect_reg_clear(void *dev_hndl, - enum ind_ctxt_cmd_sel sel, uint16_t hw_qid); -static int qdma_cpm4_indirect_reg_read(void *dev_hndl, - enum ind_ctxt_cmd_sel sel, - uint16_t hw_qid, uint32_t cnt, uint32_t *data); -static int qdma_cpm4_indirect_reg_write(void *dev_hndl, - enum ind_ctxt_cmd_sel sel, - uint16_t hw_qid, uint32_t *data, uint16_t cnt); - -uint32_t qdma_cpm4_get_config_num_regs(void) -{ - return qdma_cpm4_config_num_regs_get(); -} - -struct xreg_info *qdma_cpm4_get_config_regs(void) -{ - return qdma_cpm4_config_regs_get(); -} - -uint32_t qdma_cpm4_reg_dump_buf_len(void) -{ - uint32_t length = (qdma_cpm4_config_num_regs_get() + 1) - * REG_DUMP_SIZE_PER_LINE; - return length; -} - -int qdma_cpm4_context_buf_len(uint8_t st, - enum qdma_dev_q_type q_type, uint32_t *req_buflen) -{ - uint32_t len = 0; - int rv = 0; - - if (q_type == QDMA_DEV_Q_TYPE_CMPT) { - len += (((sizeof(qdma_cpm4_cmpt_ctxt_entries) / - sizeof(qdma_cpm4_cmpt_ctxt_entries[0])) + 1) * - REG_DUMP_SIZE_PER_LINE); - } else { - len += (((sizeof(qdma_cpm4_sw_ctxt_entries) / - sizeof(qdma_cpm4_sw_ctxt_entries[0])) + 1) * - REG_DUMP_SIZE_PER_LINE); - - len += (((sizeof(qdma_cpm4_hw_ctxt_entries) / - sizeof(qdma_cpm4_hw_ctxt_entries[0])) + 1) * - REG_DUMP_SIZE_PER_LINE); - - len += (((sizeof(qdma_cpm4_credit_ctxt_entries) / - sizeof(qdma_cpm4_credit_ctxt_entries[0])) + 1) * - REG_DUMP_SIZE_PER_LINE); - - len += (((sizeof(qdma_cpm4_fmap_ctxt_entries) / - sizeof(qdma_cpm4_fmap_ctxt_entries[0])) + 1) * - REG_DUMP_SIZE_PER_LINE); - - if (st && (q_type == QDMA_DEV_Q_TYPE_C2H)) { - len += (((sizeof(qdma_cpm4_cmpt_ctxt_entries) / - sizeof(qdma_cpm4_cmpt_ctxt_entries[0])) + 1) * - REG_DUMP_SIZE_PER_LINE); - - len += (((sizeof(qdma_cpm4_c2h_pftch_ctxt_entries) / - sizeof(qdma_cpm4_c2h_pftch_ctxt_entries[0])) + 1) * - REG_DUMP_SIZE_PER_LINE); - } - } - - *req_buflen = len; - return rv; -} - -static uint32_t qdma_cpm4_intr_context_buf_len(void) -{ - uint32_t len = 0; - - len += (((sizeof(qdma_cpm4_ind_intr_ctxt_entries) / - sizeof(qdma_cpm4_ind_intr_ctxt_entries[0])) + 1) * - REG_DUMP_SIZE_PER_LINE); - return len; -} - -/* - * qdma_acc_fill_sw_ctxt() - Helper function to fill sw context into structure - * - */ -static void qdma_cpm4_fill_sw_ctxt(struct qdma_descq_sw_ctxt *sw_ctxt) -{ - qdma_cpm4_sw_ctxt_entries[0].value = sw_ctxt->pidx; - qdma_cpm4_sw_ctxt_entries[1].value = sw_ctxt->irq_arm; - qdma_cpm4_sw_ctxt_entries[2].value = sw_ctxt->qen; - qdma_cpm4_sw_ctxt_entries[3].value = sw_ctxt->frcd_en; - qdma_cpm4_sw_ctxt_entries[4].value = sw_ctxt->wbi_chk; - qdma_cpm4_sw_ctxt_entries[5].value = sw_ctxt->wbi_intvl_en; - qdma_cpm4_sw_ctxt_entries[6].value = sw_ctxt->fnc_id; - qdma_cpm4_sw_ctxt_entries[7].value = sw_ctxt->rngsz_idx; - qdma_cpm4_sw_ctxt_entries[8].value = sw_ctxt->desc_sz; - qdma_cpm4_sw_ctxt_entries[9].value = sw_ctxt->bypass; - qdma_cpm4_sw_ctxt_entries[10].value = sw_ctxt->mm_chn; - qdma_cpm4_sw_ctxt_entries[11].value = sw_ctxt->wbk_en; - qdma_cpm4_sw_ctxt_entries[12].value = sw_ctxt->irq_en; - qdma_cpm4_sw_ctxt_entries[13].value = sw_ctxt->port_id; - qdma_cpm4_sw_ctxt_entries[14].value = sw_ctxt->irq_no_last; - qdma_cpm4_sw_ctxt_entries[15].value = sw_ctxt->err; - qdma_cpm4_sw_ctxt_entries[16].value = sw_ctxt->err_wb_sent; - qdma_cpm4_sw_ctxt_entries[17].value = sw_ctxt->irq_req; - qdma_cpm4_sw_ctxt_entries[18].value = sw_ctxt->mrkr_dis; - qdma_cpm4_sw_ctxt_entries[19].value = sw_ctxt->is_mm; - qdma_cpm4_sw_ctxt_entries[20].value = - sw_ctxt->ring_bs_addr & 0xFFFFFFFF; - qdma_cpm4_sw_ctxt_entries[21].value = - (sw_ctxt->ring_bs_addr >> 32) & 0xFFFFFFFF; -} - -/* - * qdma_acc_fill_cmpt_ctxt() - Helper function to fill completion context - * into structure - * - */ -static void qdma_cpm4_fill_cmpt_ctxt(struct qdma_descq_cmpt_ctxt *cmpt_ctxt) -{ - qdma_cpm4_cmpt_ctxt_entries[0].value = cmpt_ctxt->en_stat_desc; - qdma_cpm4_cmpt_ctxt_entries[1].value = cmpt_ctxt->en_int; - qdma_cpm4_cmpt_ctxt_entries[2].value = cmpt_ctxt->trig_mode; - qdma_cpm4_cmpt_ctxt_entries[3].value = cmpt_ctxt->fnc_id; - qdma_cpm4_cmpt_ctxt_entries[4].value = cmpt_ctxt->counter_idx; - qdma_cpm4_cmpt_ctxt_entries[5].value = cmpt_ctxt->timer_idx; - qdma_cpm4_cmpt_ctxt_entries[6].value = cmpt_ctxt->in_st; - qdma_cpm4_cmpt_ctxt_entries[7].value = cmpt_ctxt->color; - qdma_cpm4_cmpt_ctxt_entries[8].value = cmpt_ctxt->ringsz_idx; - qdma_cpm4_cmpt_ctxt_entries[9].value = - cmpt_ctxt->bs_addr & 0xFFFFFFFF; - qdma_cpm4_cmpt_ctxt_entries[10].value = - (cmpt_ctxt->bs_addr >> 32) & 0xFFFFFFFF; - qdma_cpm4_cmpt_ctxt_entries[11].value = cmpt_ctxt->desc_sz; - qdma_cpm4_cmpt_ctxt_entries[12].value = cmpt_ctxt->pidx; - qdma_cpm4_cmpt_ctxt_entries[13].value = cmpt_ctxt->cidx; - qdma_cpm4_cmpt_ctxt_entries[14].value = cmpt_ctxt->valid; - qdma_cpm4_cmpt_ctxt_entries[15].value = cmpt_ctxt->err; - qdma_cpm4_cmpt_ctxt_entries[16].value = cmpt_ctxt->user_trig_pend; - qdma_cpm4_cmpt_ctxt_entries[17].value = cmpt_ctxt->timer_running; - qdma_cpm4_cmpt_ctxt_entries[18].value = cmpt_ctxt->full_upd; - -} - -/* - * qdma_acc_fill_hw_ctxt() - Helper function to fill HW context into structure - * - */ -static void qdma_cpm4_fill_hw_ctxt(struct qdma_descq_hw_ctxt *hw_ctxt) -{ - qdma_cpm4_hw_ctxt_entries[0].value = hw_ctxt->cidx; - qdma_cpm4_hw_ctxt_entries[1].value = hw_ctxt->crd_use; - qdma_cpm4_hw_ctxt_entries[2].value = hw_ctxt->dsc_pend; - qdma_cpm4_hw_ctxt_entries[3].value = hw_ctxt->idl_stp_b; - qdma_cpm4_hw_ctxt_entries[4].value = hw_ctxt->evt_pnd; - qdma_cpm4_hw_ctxt_entries[5].value = hw_ctxt->fetch_pnd; -} - -/* - * qdma_acc_fill_credit_ctxt() - Helper function to fill Credit context - * into structure - * - */ -static void qdma_cpm4_fill_credit_ctxt( - struct qdma_descq_credit_ctxt *cr_ctxt) -{ - qdma_cpm4_credit_ctxt_entries[0].value = cr_ctxt->credit; -} - -/* - * qdma_acc_fill_pfetch_ctxt() - Helper function to fill Prefetch context - * into structure - * - */ -static void qdma_cpm4_fill_pfetch_ctxt( - struct qdma_descq_prefetch_ctxt *pfetch_ctxt) -{ - qdma_cpm4_c2h_pftch_ctxt_entries[0].value = pfetch_ctxt->bypass; - qdma_cpm4_c2h_pftch_ctxt_entries[1].value = pfetch_ctxt->bufsz_idx; - qdma_cpm4_c2h_pftch_ctxt_entries[2].value = pfetch_ctxt->port_id; - qdma_cpm4_c2h_pftch_ctxt_entries[3].value = pfetch_ctxt->err; - qdma_cpm4_c2h_pftch_ctxt_entries[4].value = pfetch_ctxt->pfch_en; - qdma_cpm4_c2h_pftch_ctxt_entries[5].value = pfetch_ctxt->pfch; - qdma_cpm4_c2h_pftch_ctxt_entries[6].value = pfetch_ctxt->sw_crdt; - qdma_cpm4_c2h_pftch_ctxt_entries[7].value = pfetch_ctxt->valid; -} - -/* - * qdma_cpm4_fill_fmap_ctxt() - Helper function to fill fmap context - * into structure - * - */ -static void qdma_cpm4_fill_fmap_ctxt(struct qdma_fmap_cfg *fmap_ctxt) -{ - qdma_cpm4_fmap_ctxt_entries[0].value = fmap_ctxt->qbase; - qdma_cpm4_fmap_ctxt_entries[1].value = fmap_ctxt->qmax; -} - -static void qdma_cpm4_fill_qid2vec_ctxt(struct qdma_qid2vec *qid2vec_ctxt) -{ - qdma_cpm4_qid2vec_ctxt_entries[0].value = qid2vec_ctxt->c2h_vector; - qdma_cpm4_qid2vec_ctxt_entries[1].value = qid2vec_ctxt->c2h_en_coal; - qdma_cpm4_qid2vec_ctxt_entries[2].value = qid2vec_ctxt->h2c_vector; - qdma_cpm4_qid2vec_ctxt_entries[3].value = qid2vec_ctxt->h2c_en_coal; -} - -static void qdma_cpm4_fill_intr_ctxt( - struct qdma_indirect_intr_ctxt *intr_ctxt) -{ - qdma_cpm4_ind_intr_ctxt_entries[0].value = intr_ctxt->valid; - qdma_cpm4_ind_intr_ctxt_entries[1].value = intr_ctxt->vec; - qdma_cpm4_ind_intr_ctxt_entries[2].value = intr_ctxt->int_st; - qdma_cpm4_ind_intr_ctxt_entries[3].value = intr_ctxt->color; - qdma_cpm4_ind_intr_ctxt_entries[4].value = - intr_ctxt->baddr_4k & 0xFFFFFFFF; - qdma_cpm4_ind_intr_ctxt_entries[5].value = - (intr_ctxt->baddr_4k >> 32) & 0xFFFFFFFF; - qdma_cpm4_ind_intr_ctxt_entries[6].value = intr_ctxt->page_size; - qdma_cpm4_ind_intr_ctxt_entries[7].value = intr_ctxt->pidx; -} - -/* - * dump_cpm4_context() - Helper function to dump queue context into string - * - * return len - length of the string copied into buffer - */ -static int dump_cpm4_context(struct qdma_descq_context *queue_context, - uint8_t st, enum qdma_dev_q_type q_type, - char *buf, int buf_sz) -{ - int i = 0; - int n; - int len = 0; - int rv; - char banner[DEBGFS_LINE_SZ] = ""; - - if (queue_context == NULL) { - qdma_log_error("%s: queue_context is NULL, err:%d\n", - __func__, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - if (q_type >= QDMA_DEV_Q_TYPE_CMPT) { - qdma_log_error("%s: Invalid queue type(%d), err:%d\n", - __func__, - q_type, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - qdma_cpm4_fill_sw_ctxt(&queue_context->sw_ctxt); - qdma_cpm4_fill_hw_ctxt(&queue_context->hw_ctxt); - qdma_cpm4_fill_credit_ctxt(&queue_context->cr_ctxt); - qdma_cpm4_fill_qid2vec_ctxt(&queue_context->qid2vec); - if (st && (q_type == QDMA_DEV_Q_TYPE_C2H)) { - qdma_cpm4_fill_pfetch_ctxt(&queue_context->pfetch_ctxt); - qdma_cpm4_fill_cmpt_ctxt(&queue_context->cmpt_ctxt); - } - - qdma_cpm4_fill_fmap_ctxt(&queue_context->fmap); - - if (q_type != QDMA_DEV_Q_TYPE_CMPT) { - for (i = 0; i < DEBGFS_LINE_SZ - 5; i++) { - rv = QDMA_SNPRINTF_S(banner + i, - (DEBGFS_LINE_SZ - i), - sizeof("-"), "-"); - if ((rv < 0) || (rv > (int)sizeof("-"))) { - qdma_log_error( - "%d:%s QDMA_SNPRINTF_S() failed, err:%d\n", - __LINE__, __func__, - rv); - goto INSUF_BUF_EXIT; - } - } - - /* SW context dump */ - n = sizeof(qdma_cpm4_sw_ctxt_entries) / - sizeof((qdma_cpm4_sw_ctxt_entries)[0]); - for (i = 0; i < n; i++) { - if ((len >= buf_sz) || - ((len + DEBGFS_LINE_SZ) >= buf_sz)) - goto INSUF_BUF_EXIT; - - if (i == 0) { - if ((len + (3 * DEBGFS_LINE_SZ)) >= buf_sz) - goto INSUF_BUF_EXIT; - rv = QDMA_SNPRINTF_S(buf + len, (buf_sz - len), - DEBGFS_LINE_SZ, "\n%s", banner); - if ((rv < 0) || (rv > DEBGFS_LINE_SZ)) { - qdma_log_error( - "%d:%s QDMA_SNPRINTF_S() failed, err:%d\n", - __LINE__, __func__, - rv); - goto INSUF_BUF_EXIT; - } - len += rv; - - rv = QDMA_SNPRINTF_S(buf + len, (buf_sz - len), - DEBGFS_LINE_SZ, "\n%40s", "SW Context"); - if ((rv < 0) || (rv > DEBGFS_LINE_SZ)) { - qdma_log_error( - "%d:%s QDMA_SNPRINTF_S() failed, err:%d\n", - __LINE__, __func__, - rv); - goto INSUF_BUF_EXIT; - } - len += rv; - - rv = QDMA_SNPRINTF_S(buf + len, (buf_sz - len), - DEBGFS_LINE_SZ, "\n%s\n", banner); - if ((rv < 0) || (rv > DEBGFS_LINE_SZ)) { - qdma_log_error( - "%d:%s QDMA_SNPRINTF_S() failed, err:%d\n", - __LINE__, __func__, - rv); - goto INSUF_BUF_EXIT; - } - len += rv; - } - - rv = QDMA_SNPRINTF_S(buf + len, (buf_sz - len), - DEBGFS_LINE_SZ, - "%-47s %#-10x %u\n", - qdma_cpm4_sw_ctxt_entries[i].name, - qdma_cpm4_sw_ctxt_entries[i].value, - qdma_cpm4_sw_ctxt_entries[i].value); - if ((rv < 0) || (rv > DEBGFS_LINE_SZ)) { - qdma_log_error( - "%d:%s QDMA_SNPRINTF_S() failed, err:%d\n", - __LINE__, __func__, - rv); - goto INSUF_BUF_EXIT; - } - len += rv; - } - - /* HW context dump */ - n = sizeof(qdma_cpm4_hw_ctxt_entries) / - sizeof((qdma_cpm4_hw_ctxt_entries)[0]); - for (i = 0; i < n; i++) { - if ((len >= buf_sz) || - ((len + DEBGFS_LINE_SZ) >= buf_sz)) - goto INSUF_BUF_EXIT; - - if (i == 0) { - if ((len + (3 * DEBGFS_LINE_SZ)) >= buf_sz) - goto INSUF_BUF_EXIT; - - rv = QDMA_SNPRINTF_S(buf + len, (buf_sz - len), - DEBGFS_LINE_SZ, "\n%s", banner); - if ((rv < 0) || (rv > DEBGFS_LINE_SZ)) { - qdma_log_error( - "%d:%s QDMA_SNPRINTF_S() failed, err:%d\n", - __LINE__, __func__, - rv); - goto INSUF_BUF_EXIT; - } - len += rv; - - rv = QDMA_SNPRINTF_S(buf + len, (buf_sz - len), - DEBGFS_LINE_SZ, "\n%40s", "HW Context"); - if ((rv < 0) || (rv > DEBGFS_LINE_SZ)) { - qdma_log_error( - "%d:%s QDMA_SNPRINTF_S() failed, err:%d\n", - __LINE__, __func__, - rv); - goto INSUF_BUF_EXIT; - } - len += rv; - - rv = QDMA_SNPRINTF_S(buf + len, (buf_sz - len), - DEBGFS_LINE_SZ, "\n%s\n", banner); - if ((rv < 0) || (rv > DEBGFS_LINE_SZ)) { - qdma_log_error( - "%d:%s QDMA_SNPRINTF_S() failed, err:%d\n", - __LINE__, __func__, - rv); - goto INSUF_BUF_EXIT; - } - len += rv; - } - - rv = QDMA_SNPRINTF_S(buf + len, (buf_sz - len), - DEBGFS_LINE_SZ, - "%-47s %#-10x %u\n", - qdma_cpm4_hw_ctxt_entries[i].name, - qdma_cpm4_hw_ctxt_entries[i].value, - qdma_cpm4_hw_ctxt_entries[i].value); - if ((rv < 0) || (rv > DEBGFS_LINE_SZ)) { - qdma_log_error( - "%d:%s QDMA_SNPRINTF_S() failed, err:%d\n", - __LINE__, __func__, - rv); - goto INSUF_BUF_EXIT; - } - len += rv; - } - - /* Credit context dump */ - n = sizeof(qdma_cpm4_credit_ctxt_entries) / - sizeof((qdma_cpm4_credit_ctxt_entries)[0]); - for (i = 0; i < n; i++) { - if ((len >= buf_sz) || - ((len + DEBGFS_LINE_SZ) >= buf_sz)) - goto INSUF_BUF_EXIT; - - if (i == 0) { - if ((len + (3 * DEBGFS_LINE_SZ)) >= buf_sz) - goto INSUF_BUF_EXIT; - - rv = QDMA_SNPRINTF_S(buf + len, (buf_sz - len), - DEBGFS_LINE_SZ, "\n%s", banner); - if ((rv < 0) || (rv > DEBGFS_LINE_SZ)) { - qdma_log_error( - "%d:%s QDMA_SNPRINTF_S() failed, err:%d\n", - __LINE__, __func__, - rv); - goto INSUF_BUF_EXIT; - } - len += rv; - - rv = QDMA_SNPRINTF_S(buf + len, (buf_sz - len), - DEBGFS_LINE_SZ, "\n%40s", - "Credit Context"); - if ((rv < 0) || (rv > DEBGFS_LINE_SZ)) { - qdma_log_error( - "%d:%s QDMA_SNPRINTF_S() failed, err:%d\n", - __LINE__, __func__, - rv); - goto INSUF_BUF_EXIT; - } - len += rv; - - rv = QDMA_SNPRINTF_S(buf + len, (buf_sz - len), - DEBGFS_LINE_SZ, "\n%s\n", banner); - if ((rv < 0) || (rv > DEBGFS_LINE_SZ)) { - qdma_log_error( - "%d:%s QDMA_SNPRINTF_S() failed, err:%d\n", - __LINE__, __func__, - rv); - goto INSUF_BUF_EXIT; - } - len += rv; - } - - rv = QDMA_SNPRINTF_S(buf + len, (buf_sz - len), - DEBGFS_LINE_SZ, - "%-47s %#-10x %u\n", - qdma_cpm4_credit_ctxt_entries[i].name, - qdma_cpm4_credit_ctxt_entries[i].value, - qdma_cpm4_credit_ctxt_entries[i].value); - if ((rv < 0) || (rv > DEBGFS_LINE_SZ)) { - qdma_log_error( - "%d:%s QDMA_SNPRINTF_S() failed, err:%d\n", - __LINE__, __func__, - rv); - goto INSUF_BUF_EXIT; - } - len += rv; - } - } - - /* SW context dump */ - n = sizeof(qdma_cpm4_qid2vec_ctxt_entries) / - sizeof((qdma_cpm4_qid2vec_ctxt_entries)[0]); - for (i = 0; i < n; i++) { - if ((len >= buf_sz) || - ((len + DEBGFS_LINE_SZ) >= buf_sz)) - goto INSUF_BUF_EXIT; - - if (i == 0) { - if ((len + (3 * DEBGFS_LINE_SZ)) >= buf_sz) - goto INSUF_BUF_EXIT; - rv = QDMA_SNPRINTF_S(buf + len, (buf_sz - len), - DEBGFS_LINE_SZ, "\n%s", banner); - if ((rv < 0) || (rv > DEBGFS_LINE_SZ)) { - qdma_log_error( - "%d:%s QDMA_SNPRINTF_S() failed, err:%d\n", - __LINE__, __func__, - rv); - goto INSUF_BUF_EXIT; - } - len += rv; - - rv = QDMA_SNPRINTF_S(buf + len, (buf_sz - len), - DEBGFS_LINE_SZ, "\n%40s", - "QID2VEC Context"); - if ((rv < 0) || (rv > DEBGFS_LINE_SZ)) { - qdma_log_error( - "%d:%s QDMA_SNPRINTF_S() failed, err:%d\n", - __LINE__, __func__, - rv); - goto INSUF_BUF_EXIT; - } - len += rv; - - rv = QDMA_SNPRINTF_S(buf + len, (buf_sz - len), - DEBGFS_LINE_SZ, "\n%s\n", banner); - if ((rv < 0) || (rv > DEBGFS_LINE_SZ)) { - qdma_log_error( - "%d:%s QDMA_SNPRINTF_S() failed, err:%d\n", - __LINE__, __func__, - rv); - goto INSUF_BUF_EXIT; - } - len += rv; - } - - rv = QDMA_SNPRINTF_S(buf + len, (buf_sz - len), DEBGFS_LINE_SZ, - "%-47s %#-10x %u\n", - qdma_cpm4_qid2vec_ctxt_entries[i].name, - qdma_cpm4_qid2vec_ctxt_entries[i].value, - qdma_cpm4_qid2vec_ctxt_entries[i].value); - if ((rv < 0) || (rv > DEBGFS_LINE_SZ)) { - qdma_log_error( - "%d:%s QDMA_SNPRINTF_S() failed, err:%d\n", - __LINE__, __func__, - rv); - goto INSUF_BUF_EXIT; - } - len += rv; - } - - - if ((q_type == QDMA_DEV_Q_TYPE_CMPT) || - (st && q_type == QDMA_DEV_Q_TYPE_C2H)) { - /* Completion context dump */ - n = sizeof(qdma_cpm4_cmpt_ctxt_entries) / - sizeof((qdma_cpm4_cmpt_ctxt_entries)[0]); - for (i = 0; i < n; i++) { - if ((len >= buf_sz) || - ((len + DEBGFS_LINE_SZ) >= buf_sz)) - goto INSUF_BUF_EXIT; - - if (i == 0) { - if ((len + (3 * DEBGFS_LINE_SZ)) >= buf_sz) - goto INSUF_BUF_EXIT; - - rv = QDMA_SNPRINTF_S(buf + len, (buf_sz - len), - DEBGFS_LINE_SZ, "\n%s", banner); - if ((rv < 0) || (rv > DEBGFS_LINE_SZ)) { - qdma_log_error( - "%d:%s QDMA_SNPRINTF_S() failed, err:%d\n", - __LINE__, __func__, - rv); - goto INSUF_BUF_EXIT; - } - len += rv; - - rv = QDMA_SNPRINTF_S(buf + len, (buf_sz - len), - DEBGFS_LINE_SZ, "\n%40s", - "Completion Context"); - if ((rv < 0) || (rv > DEBGFS_LINE_SZ)) { - qdma_log_error( - "%d:%s QDMA_SNPRINTF_S() failed, err:%d\n", - __LINE__, __func__, - rv); - goto INSUF_BUF_EXIT; - } - len += rv; - - rv = QDMA_SNPRINTF_S(buf + len, (buf_sz - len), - DEBGFS_LINE_SZ, "\n%s\n", banner); - if ((rv < 0) || (rv > DEBGFS_LINE_SZ)) { - qdma_log_error( - "%d:%s QDMA_SNPRINTF_S() failed, err:%d\n", - __LINE__, __func__, - rv); - goto INSUF_BUF_EXIT; - } - len += rv; - } - - rv = QDMA_SNPRINTF_S(buf + len, (buf_sz - len), - DEBGFS_LINE_SZ, - "%-47s %#-10x %u\n", - qdma_cpm4_cmpt_ctxt_entries[i].name, - qdma_cpm4_cmpt_ctxt_entries[i].value, - qdma_cpm4_cmpt_ctxt_entries[i].value); - if ((rv < 0) || (rv > DEBGFS_LINE_SZ)) { - qdma_log_error( - "%d:%s QDMA_SNPRINTF_S() failed, err:%d\n", - __LINE__, __func__, - rv); - goto INSUF_BUF_EXIT; - } - len += rv; - } - } - - if (st && q_type == QDMA_DEV_Q_TYPE_C2H) { - /* Prefetch context dump */ - n = sizeof(qdma_cpm4_c2h_pftch_ctxt_entries) / - sizeof(qdma_cpm4_c2h_pftch_ctxt_entries[0]); - for (i = 0; i < n; i++) { - if ((len >= buf_sz) || - ((len + DEBGFS_LINE_SZ) >= buf_sz)) - goto INSUF_BUF_EXIT; - - if (i == 0) { - if ((len + (3 * DEBGFS_LINE_SZ)) >= buf_sz) - goto INSUF_BUF_EXIT; - - rv = QDMA_SNPRINTF_S(buf + len, (buf_sz - len), - DEBGFS_LINE_SZ, "\n%s", banner); - if ((rv < 0) || (rv > DEBGFS_LINE_SZ)) { - qdma_log_error( - "%d:%s QDMA_SNPRINTF_S() failed, err:%d\n", - __LINE__, __func__, - rv); - goto INSUF_BUF_EXIT; - } - len += rv; - - rv = QDMA_SNPRINTF_S(buf + len, (buf_sz - len), - DEBGFS_LINE_SZ, "\n%40s", - "Prefetch Context"); - if ((rv < 0) || (rv > DEBGFS_LINE_SZ)) { - qdma_log_error( - "%d:%s QDMA_SNPRINTF_S() failed, err:%d\n", - __LINE__, __func__, - rv); - goto INSUF_BUF_EXIT; - } - len += rv; - - rv = QDMA_SNPRINTF_S(buf + len, (buf_sz - len), - DEBGFS_LINE_SZ, "\n%s\n", banner); - if ((rv < 0) || (rv > DEBGFS_LINE_SZ)) { - qdma_log_error( - "%d:%s QDMA_SNPRINTF_S() failed, err:%d\n", - __LINE__, __func__, - rv); - goto INSUF_BUF_EXIT; - } - len += rv; - } - - rv = QDMA_SNPRINTF_S(buf + len, (buf_sz - len), - DEBGFS_LINE_SZ, - "%-47s %#-10x %u\n", - qdma_cpm4_c2h_pftch_ctxt_entries[i].name, - qdma_cpm4_c2h_pftch_ctxt_entries[i].value, - qdma_cpm4_c2h_pftch_ctxt_entries[i].value); - if ((rv < 0) || (rv > DEBGFS_LINE_SZ)) { - qdma_log_error( - "%d:%s QDMA_SNPRINTF_S() failed, err:%d\n", - __LINE__, __func__, - rv); - goto INSUF_BUF_EXIT; - } - len += rv; - } - } - - /* Fmap context dump */ - n = sizeof(qdma_cpm4_fmap_ctxt_entries) / - sizeof(qdma_cpm4_fmap_ctxt_entries[0]); - for (i = 0; i < n; i++) { - if ((len >= buf_sz) || - ((len + DEBGFS_LINE_SZ) >= buf_sz)) - goto INSUF_BUF_EXIT; - - if (i == 0) { - if ((len + (3 * DEBGFS_LINE_SZ)) >= buf_sz) - goto INSUF_BUF_EXIT; - - rv = QDMA_SNPRINTF_S(buf + len, (buf_sz - len), - DEBGFS_LINE_SZ, "\n%s", banner); - if ((rv < 0) || (rv > DEBGFS_LINE_SZ)) { - qdma_log_error( - "%d:%s QDMA_SNPRINTF_S() failed, err:%d\n", - __LINE__, __func__, - rv); - goto INSUF_BUF_EXIT; - } - len += rv; - - rv = QDMA_SNPRINTF_S(buf + len, (buf_sz - len), - DEBGFS_LINE_SZ, "\n%40s", - "Fmap Context"); - if ((rv < 0) || (rv > DEBGFS_LINE_SZ)) { - qdma_log_error( - "%d:%s QDMA_SNPRINTF_S() failed, err:%d\n", - __LINE__, __func__, - rv); - goto INSUF_BUF_EXIT; - } - len += rv; - - rv = QDMA_SNPRINTF_S(buf + len, (buf_sz - len), - DEBGFS_LINE_SZ, "\n%s\n", banner); - if ((rv < 0) || (rv > DEBGFS_LINE_SZ)) { - qdma_log_error( - "%d:%s QDMA_SNPRINTF_S() failed, err:%d\n", - __LINE__, __func__, - rv); - goto INSUF_BUF_EXIT; - } - len += rv; - } - - rv = QDMA_SNPRINTF_S(buf + len, - (buf_sz - len), DEBGFS_LINE_SZ, - "%-47s %#-10x %u\n", - qdma_cpm4_fmap_ctxt_entries[i].name, - qdma_cpm4_fmap_ctxt_entries[i].value, - qdma_cpm4_fmap_ctxt_entries[i].value); - if ((rv < 0) || (rv > DEBGFS_LINE_SZ)) { - qdma_log_error( - "%d:%s QDMA_SNPRINTF_S() failed, err:%d\n", - __LINE__, __func__, - rv); - goto INSUF_BUF_EXIT; - } - len += rv; - } - - return len; - -INSUF_BUF_EXIT: - if (buf_sz > DEBGFS_LINE_SZ) { - rv = QDMA_SNPRINTF_S((buf + buf_sz - DEBGFS_LINE_SZ), - buf_sz, DEBGFS_LINE_SZ, - "\n\nInsufficient buffer size, partial context dump\n"); - if ((rv < 0) || (rv > DEBGFS_LINE_SZ)) { - qdma_log_error( - "%d:%s QDMA_SNPRINTF_S() failed, err:%d\n", - __LINE__, __func__, - rv); - } - } - - qdma_log_error("%s: Insufficient buffer size, err:%d\n", - __func__, -QDMA_ERR_NO_MEM); - - return -QDMA_ERR_NO_MEM; -} - -static int dump_cpm4_intr_context(struct qdma_indirect_intr_ctxt *intr_ctx, - int ring_index, - char *buf, int buf_sz) -{ - int i = 0; - int n; - int len = 0; - int rv; - char banner[DEBGFS_LINE_SZ] = ""; - - qdma_cpm4_fill_intr_ctxt(intr_ctx); - - for (i = 0; i < DEBGFS_LINE_SZ - 5; i++) { - rv = QDMA_SNPRINTF_S(banner + i, - (DEBGFS_LINE_SZ - i), - sizeof("-"), "-"); - if ((rv < 0) || (rv > (int)sizeof("-"))) { - qdma_log_error( - "%d:%s QDMA_SNPRINTF_S() failed, err:%d\n", - __LINE__, __func__, - rv); - goto INSUF_BUF_EXIT; - } - } - - /* Interrupt context dump */ - n = sizeof(qdma_cpm4_ind_intr_ctxt_entries) / - sizeof((qdma_cpm4_ind_intr_ctxt_entries)[0]); - for (i = 0; i < n; i++) { - if ((len >= buf_sz) || ((len + DEBGFS_LINE_SZ) >= buf_sz)) - goto INSUF_BUF_EXIT; - - if (i == 0) { - if ((len + (3 * DEBGFS_LINE_SZ)) >= buf_sz) - goto INSUF_BUF_EXIT; - - rv = QDMA_SNPRINTF_S(buf + len, (buf_sz - len), - DEBGFS_LINE_SZ, "\n%s", banner); - if ((rv < 0) || (rv > DEBGFS_LINE_SZ)) { - qdma_log_error( - "%d:%s QDMA_SNPRINTF_S() failed, err:%d\n", - __LINE__, __func__, - rv); - goto INSUF_BUF_EXIT; - } - len += rv; - - rv = QDMA_SNPRINTF_S(buf + len, (buf_sz - len), - DEBGFS_LINE_SZ, "\n%50s %d", - "Interrupt Context for ring#", ring_index); - if ((rv < 0) || (rv > DEBGFS_LINE_SZ)) { - qdma_log_error( - "%d:%s QDMA_SNPRINTF_S() failed, err:%d\n", - __LINE__, __func__, - rv); - goto INSUF_BUF_EXIT; - } - len += rv; - - rv = QDMA_SNPRINTF_S(buf + len, (buf_sz - len), - DEBGFS_LINE_SZ, "\n%s\n", banner); - if ((rv < 0) || (rv > DEBGFS_LINE_SZ)) { - qdma_log_error( - "%d:%s QDMA_SNPRINTF_S() failed, err:%d\n", - __LINE__, __func__, - rv); - goto INSUF_BUF_EXIT; - } - len += rv; - } - - rv = QDMA_SNPRINTF_S(buf + len, (buf_sz - len), DEBGFS_LINE_SZ, - "%-47s %#-10x %u\n", - qdma_cpm4_ind_intr_ctxt_entries[i].name, - qdma_cpm4_ind_intr_ctxt_entries[i].value, - qdma_cpm4_ind_intr_ctxt_entries[i].value); - if ((rv < 0) || (rv > DEBGFS_LINE_SZ)) { - qdma_log_error( - "%d:%s QDMA_SNPRINTF_S() failed, err:%d\n", - __LINE__, __func__, - rv); - goto INSUF_BUF_EXIT; - } - len += rv; - } - - return len; - -INSUF_BUF_EXIT: - if (buf_sz > DEBGFS_LINE_SZ) { - rv = QDMA_SNPRINTF_S((buf + buf_sz - DEBGFS_LINE_SZ), - buf_sz, DEBGFS_LINE_SZ, - "\n\nInsufficient buffer size, partial intr context dump\n"); - if ((rv < 0) || (rv > DEBGFS_LINE_SZ)) { - qdma_log_error( - "%d:%s QDMA_SNPRINTF_S() failed, err:%d\n", - __LINE__, __func__, - rv); - } - } - - qdma_log_error("%s: Insufficient buffer size, err:%d\n", - __func__, -QDMA_ERR_NO_MEM); - - return -QDMA_ERR_NO_MEM; -} - -/* - * qdma_cpm4_indirect_reg_invalidate() - helper function to invalidate - * indirect context registers. - * - * return -QDMA_ERR_HWACC_BUSY_TIMEOUT if register - * value didn't match, QDMA_SUCCESS other wise - */ -static int qdma_cpm4_indirect_reg_invalidate(void *dev_hndl, - enum ind_ctxt_cmd_sel sel, uint16_t hw_qid) -{ - union qdma_cpm4_ind_ctxt_cmd cmd; - - qdma_reg_access_lock(dev_hndl); - - /* set command register */ - cmd.word = 0; - cmd.bits.qid = hw_qid; - cmd.bits.op = QDMA_CTXT_CMD_INV; - cmd.bits.sel = sel; - qdma_reg_write(dev_hndl, QDMA_CPM4_IND_CTXT_CMD_ADDR, cmd.word); - - /* check if the operation went through well */ - if (hw_monitor_reg(dev_hndl, QDMA_CPM4_IND_CTXT_CMD_ADDR, - IND_CTXT_CMD_BUSY_MASK, 0, - QDMA_REG_POLL_DFLT_INTERVAL_US, - QDMA_REG_POLL_DFLT_TIMEOUT_US)) { - qdma_reg_access_release(dev_hndl); - qdma_log_error("%s: hw_monitor_reg failed, err:%d\n", - __func__, - -QDMA_ERR_HWACC_BUSY_TIMEOUT); - return -QDMA_ERR_HWACC_BUSY_TIMEOUT; - } - - qdma_reg_access_release(dev_hndl); - - return QDMA_SUCCESS; -} - -/* - * qdma_cpm4_indirect_reg_clear() - helper function to clear indirect - * context registers. - * - * return -QDMA_ERR_HWACC_BUSY_TIMEOUT if register - * value didn't match, QDMA_SUCCESS other wise - */ -static int qdma_cpm4_indirect_reg_clear(void *dev_hndl, - enum ind_ctxt_cmd_sel sel, uint16_t hw_qid) -{ - union qdma_cpm4_ind_ctxt_cmd cmd; - - qdma_reg_access_lock(dev_hndl); - - /* set command register */ - cmd.word = 0; - cmd.bits.qid = hw_qid; - cmd.bits.op = QDMA_CTXT_CMD_CLR; - cmd.bits.sel = sel; - - qdma_reg_write(dev_hndl, QDMA_CPM4_IND_CTXT_CMD_ADDR, cmd.word); - - /* check if the operation went through well */ - if (hw_monitor_reg(dev_hndl, QDMA_CPM4_IND_CTXT_CMD_ADDR, - IND_CTXT_CMD_BUSY_MASK, 0, - QDMA_REG_POLL_DFLT_INTERVAL_US, - QDMA_REG_POLL_DFLT_TIMEOUT_US)) { - qdma_reg_access_release(dev_hndl); - qdma_log_error("%s: hw_monitor_reg failed, err:%d\n", - __func__, - -QDMA_ERR_HWACC_BUSY_TIMEOUT); - return -QDMA_ERR_HWACC_BUSY_TIMEOUT; - } - - qdma_reg_access_release(dev_hndl); - - return QDMA_SUCCESS; -} - -/* - * qdma_cpm4_indirect_reg_read() - helper function to read indirect - * context registers. - * - * return -QDMA_ERR_HWACC_BUSY_TIMEOUT if register - * value didn't match, QDMA_SUCCESS other wise - */ -static int qdma_cpm4_indirect_reg_read(void *dev_hndl, - enum ind_ctxt_cmd_sel sel, - uint16_t hw_qid, uint32_t cnt, uint32_t *data) -{ - uint32_t index = 0, reg_addr = QDMA_CPM4_IND_CTXT_DATA_3_ADDR; - union qdma_cpm4_ind_ctxt_cmd cmd; - - qdma_reg_access_lock(dev_hndl); - - /* set command register */ - cmd.word = 0; - cmd.bits.qid = hw_qid; - cmd.bits.op = QDMA_CTXT_CMD_RD; - cmd.bits.sel = sel; - qdma_reg_write(dev_hndl, QDMA_CPM4_IND_CTXT_CMD_ADDR, cmd.word); - - /* check if the operation went through well */ - if (hw_monitor_reg(dev_hndl, QDMA_CPM4_IND_CTXT_CMD_ADDR, - IND_CTXT_CMD_BUSY_MASK, 0, - QDMA_REG_POLL_DFLT_INTERVAL_US, - QDMA_REG_POLL_DFLT_TIMEOUT_US)) { - qdma_reg_access_release(dev_hndl); - qdma_log_error("%s: hw_monitor_reg failed, err:%d\n", - __func__, - -QDMA_ERR_HWACC_BUSY_TIMEOUT); - return -QDMA_ERR_HWACC_BUSY_TIMEOUT; - } - - for (index = 0; index < cnt; index++, reg_addr += sizeof(uint32_t)) - data[index] = qdma_reg_read(dev_hndl, reg_addr); - - qdma_reg_access_release(dev_hndl); - - return QDMA_SUCCESS; -} - -/* - * qdma_cpm4_indirect_reg_write() - helper function to write indirect - * context registers. - * - * return -QDMA_ERR_HWACC_BUSY_TIMEOUT if register - * value didn't match, QDMA_SUCCESS other wise - */ -static int qdma_cpm4_indirect_reg_write(void *dev_hndl, - enum ind_ctxt_cmd_sel sel, - uint16_t hw_qid, uint32_t *data, uint16_t cnt) -{ - uint32_t index, reg_addr; - struct qdma_cpm4_indirect_ctxt_regs regs; - uint32_t *wr_data = (uint32_t *)®s; - - qdma_reg_access_lock(dev_hndl); - - /* write the context data */ - for (index = 0; index < QDMA_CPM4_IND_CTXT_DATA_NUM_REGS; - index++) { - if (index < cnt) - regs.qdma_ind_ctxt_data[index] = data[index]; - else - regs.qdma_ind_ctxt_data[index] = 0; - regs.qdma_ind_ctxt_mask[index] = 0xFFFFFFFF; - } - - regs.cmd.word = 0; - regs.cmd.bits.qid = hw_qid; - regs.cmd.bits.op = QDMA_CTXT_CMD_WR; - regs.cmd.bits.sel = sel; - reg_addr = QDMA_CPM4_IND_CTXT_DATA_3_ADDR; - - for (index = 0; - index < ((2 * QDMA_CPM4_IND_CTXT_DATA_NUM_REGS) + 1); - index++, reg_addr += sizeof(uint32_t)) - qdma_reg_write(dev_hndl, reg_addr, wr_data[index]); - - /* check if the operation went through well */ - if (hw_monitor_reg(dev_hndl, QDMA_CPM4_IND_CTXT_CMD_ADDR, - IND_CTXT_CMD_BUSY_MASK, 0, - QDMA_REG_POLL_DFLT_INTERVAL_US, - QDMA_REG_POLL_DFLT_TIMEOUT_US)) { - qdma_reg_access_release(dev_hndl); - qdma_log_error("%s: hw_monitor_reg failed, err:%d\n", - __func__, - -QDMA_ERR_HWACC_BUSY_TIMEOUT); - return -QDMA_ERR_HWACC_BUSY_TIMEOUT; - } - - qdma_reg_access_release(dev_hndl); - - return QDMA_SUCCESS; -} - -/*****************************************************************************/ -/** - * qdma_cpm4_qid2vec_write() - create qid2vec context and program it - * - * @dev_hndl: device handle - * @c2h: is c2h queue - * @hw_qid: hardware qid of the queue - * @ctxt: pointer to the context data - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -static int qdma_cpm4_qid2vec_write(void *dev_hndl, uint8_t c2h, - uint16_t hw_qid, struct qdma_qid2vec *ctxt) -{ - uint32_t qid2vec = 0; - enum ind_ctxt_cmd_sel sel = QDMA_CTXT_SEL_FMAP; - int rv = 0; - - if (!dev_hndl || !ctxt) { - qdma_log_error("%s: dev_hndl=%p qid2vec=%p, err:%d\n", - __func__, dev_hndl, ctxt, -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - rv = qdma_cpm4_indirect_reg_read(dev_hndl, sel, hw_qid, - 1, &qid2vec); - if (rv < 0) - return rv; - if (c2h) { - qid2vec = qid2vec & (QDMA_CPM4_QID2VEC_H2C_VECTOR | - QDMA_CPM4_QID2VEC_H2C_COAL_EN); - qid2vec |= FIELD_SET(C2H_QID2VEC_MAP_C2H_VECTOR_MASK, - ctxt->c2h_vector) | - FIELD_SET(C2H_QID2VEC_MAP_C2H_EN_COAL_MASK, - ctxt->c2h_en_coal); - } else { - qid2vec = qid2vec & (C2H_QID2VEC_MAP_C2H_VECTOR_MASK | - C2H_QID2VEC_MAP_C2H_EN_COAL_MASK); - qid2vec |= - FIELD_SET(QDMA_CPM4_QID2VEC_H2C_VECTOR, - ctxt->h2c_vector) | - FIELD_SET(QDMA_CPM4_QID2VEC_H2C_COAL_EN, - ctxt->h2c_en_coal); - } - - return qdma_cpm4_indirect_reg_write(dev_hndl, sel, hw_qid, - &qid2vec, QDMA_CPM4_QID2VEC_CONTEXT_NUM_WORDS); - -} - -/*****************************************************************************/ -/** - * qdma_cpm4_qid2vec_read() - read qid2vec context - * - * @dev_hndl: device handle - * @c2h: is c2h queue - * @hw_qid: hardware qid of the queue - * @ctxt: pointer to the context data - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -static int qdma_cpm4_qid2vec_read(void *dev_hndl, uint8_t c2h, - uint16_t hw_qid, struct qdma_qid2vec *ctxt) -{ - int rv = 0; - uint32_t qid2vec[QDMA_CPM4_QID2VEC_CONTEXT_NUM_WORDS] = {0}; - enum ind_ctxt_cmd_sel sel = QDMA_CTXT_SEL_FMAP; - - if (!dev_hndl || !ctxt) { - qdma_log_error("%s: dev_hndl=%p qid2vec=%p, err:%d\n", - __func__, dev_hndl, ctxt, -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - rv = qdma_cpm4_indirect_reg_read(dev_hndl, sel, hw_qid, - QDMA_CPM4_QID2VEC_CONTEXT_NUM_WORDS, qid2vec); - if (rv < 0) - return rv; - - if (c2h) { - ctxt->c2h_vector = FIELD_GET(C2H_QID2VEC_MAP_C2H_VECTOR_MASK, - qid2vec[0]); - ctxt->c2h_en_coal = - (uint8_t)(FIELD_GET(C2H_QID2VEC_MAP_C2H_EN_COAL_MASK, - qid2vec[0])); - } else { - ctxt->h2c_vector = - (uint8_t)(FIELD_GET(QDMA_CPM4_QID2VEC_H2C_VECTOR, - qid2vec[0])); - ctxt->h2c_en_coal = - (uint8_t)(FIELD_GET(QDMA_CPM4_QID2VEC_H2C_COAL_EN, - qid2vec[0])); - } - - return QDMA_SUCCESS; -} - -/*****************************************************************************/ -/** - * qdma_cpm4_qid2vec_clear() - clear qid2vec context - * - * @dev_hndl: device handle - * @hw_qid: hardware qid of the queue - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -static int qdma_cpm4_qid2vec_clear(void *dev_hndl, uint16_t hw_qid) -{ - enum ind_ctxt_cmd_sel sel = QDMA_CTXT_SEL_FMAP; - - if (!dev_hndl) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - return qdma_cpm4_indirect_reg_clear(dev_hndl, sel, hw_qid); -} - -/*****************************************************************************/ -/** - * qdma_cpm4_qid2vec_invalidate() - invalidate qid2vec context - * - * @dev_hndl: device handle - * @hw_qid: hardware qid of the queue - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -static int qdma_cpm4_qid2vec_invalidate(void *dev_hndl, uint16_t hw_qid) -{ - enum ind_ctxt_cmd_sel sel = QDMA_CTXT_SEL_FMAP; - - if (!dev_hndl) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - return qdma_cpm4_indirect_reg_invalidate(dev_hndl, sel, hw_qid); -} - -/*****************************************************************************/ -/** - * qdma_cpm4_qid2vec_conf() - configure qid2vector context - * - * @dev_hndl: device handle - * @c2h: is c2h queue - * @hw_qid: hardware qid of the queue - * @ctxt: pointer to the context data - * @access_type HW access type (qdma_hw_access_type enum) value - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -int qdma_cpm4_qid2vec_conf(void *dev_hndl, uint8_t c2h, uint16_t hw_qid, - struct qdma_qid2vec *ctxt, - enum qdma_hw_access_type access_type) -{ - int ret_val = 0; - - switch (access_type) { - case QDMA_HW_ACCESS_READ: - ret_val = qdma_cpm4_qid2vec_read(dev_hndl, c2h, - hw_qid, ctxt); - break; - case QDMA_HW_ACCESS_WRITE: - ret_val = qdma_cpm4_qid2vec_write(dev_hndl, c2h, - hw_qid, ctxt); - break; - case QDMA_HW_ACCESS_CLEAR: - ret_val = qdma_cpm4_qid2vec_clear(dev_hndl, hw_qid); - break; - case QDMA_HW_ACCESS_INVALIDATE: - ret_val = qdma_cpm4_qid2vec_invalidate(dev_hndl, hw_qid); - break; - default: - qdma_log_error("%s: access_type=%d is invalid, err:%d\n", - __func__, access_type, - -QDMA_ERR_INV_PARAM); - ret_val = -QDMA_ERR_INV_PARAM; - break; - } - - return ret_val; -} - -/*****************************************************************************/ -/** - * qdma_cpm4_fmap_write() - create fmap context and program it - * - * @dev_hndl: device handle - * @func_id: function id of the device - * @config: pointer to the fmap data strucutre - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -static int qdma_cpm4_fmap_write(void *dev_hndl, uint16_t func_id, - const struct qdma_fmap_cfg *config) -{ - uint32_t fmap = 0; - - if (!dev_hndl || !config) { - qdma_log_error("%s: dev_handle or config is NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - fmap = FIELD_SET(TRQ_SEL_FMAP_0_QID_BASE_MASK, config->qbase) | - FIELD_SET(TRQ_SEL_FMAP_0_QID_MAX_MASK, - config->qmax); - - qdma_reg_write(dev_hndl, QDMA_CPM4_TRQ_SEL_FMAP_0_ADDR + - func_id * QDMA_CPM4_REG_TRQ_SEL_FMAP_STEP, - fmap); - return QDMA_SUCCESS; -} - -/*****************************************************************************/ -/** - * qdma_cpm4_fmap_read() - read fmap context - * - * @dev_hndl: device handle - * @func_id: function id of the device - * @config: pointer to the output fmap data - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -static int qdma_cpm4_fmap_read(void *dev_hndl, uint16_t func_id, - struct qdma_fmap_cfg *config) -{ - uint32_t fmap = 0; - - if (!dev_hndl || !config) { - qdma_log_error("%s: dev_handle=%p fmap=%p NULL, err:%d\n", - __func__, dev_hndl, config, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - fmap = qdma_reg_read(dev_hndl, QDMA_CPM4_TRQ_SEL_FMAP_0_ADDR + - func_id * QDMA_CPM4_REG_TRQ_SEL_FMAP_STEP); - - config->qbase = FIELD_GET(TRQ_SEL_FMAP_0_QID_BASE_MASK, fmap); - config->qmax = - (uint16_t)(FIELD_GET(TRQ_SEL_FMAP_0_QID_MAX_MASK, - fmap)); - - return QDMA_SUCCESS; -} - -/*****************************************************************************/ -/** - * qdma_cpm4_fmap_clear() - clear fmap context - * - * @dev_hndl: device handle - * @func_id: function id of the device - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -static int qdma_cpm4_fmap_clear(void *dev_hndl, uint16_t func_id) -{ - uint32_t fmap = 0; - - if (!dev_hndl) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - qdma_reg_write(dev_hndl, QDMA_CPM4_TRQ_SEL_FMAP_0_ADDR + - func_id * QDMA_CPM4_REG_TRQ_SEL_FMAP_STEP, - fmap); - - return QDMA_SUCCESS; -} - -/*****************************************************************************/ -/** - * qdma_cpm4_fmap_conf() - configure fmap context - * - * @dev_hndl: device handle - * @func_id: function id of the device - * @config: pointer to the fmap data - * @access_type HW access type (qdma_hw_access_type enum) value - * QDMA_HW_ACCESS_INVALIDATE unsupported - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -int qdma_cpm4_fmap_conf(void *dev_hndl, uint16_t func_id, - struct qdma_fmap_cfg *config, - enum qdma_hw_access_type access_type) -{ - int ret_val = 0; - - switch (access_type) { - case QDMA_HW_ACCESS_READ: - ret_val = qdma_cpm4_fmap_read(dev_hndl, func_id, config); - break; - case QDMA_HW_ACCESS_WRITE: - ret_val = qdma_cpm4_fmap_write(dev_hndl, func_id, config); - break; - case QDMA_HW_ACCESS_CLEAR: - ret_val = qdma_cpm4_fmap_clear(dev_hndl, func_id); - break; - case QDMA_HW_ACCESS_INVALIDATE: - default: - qdma_log_error("%s: access_type=%d is invalid, err:%d\n", - __func__, access_type, - -QDMA_ERR_INV_PARAM); - ret_val = -QDMA_ERR_INV_PARAM; - break; - } - - return ret_val; -} - -/*****************************************************************************/ -/** - * qdma_cpm4_sw_context_write() - create sw context and program it - * - * @dev_hndl: device handle - * @c2h: is c2h queue - * @hw_qid: hardware qid of the queue - * @ctxt: pointer to the SW context data strucutre - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -static int qdma_cpm4_sw_context_write(void *dev_hndl, uint8_t c2h, - uint16_t hw_qid, - const struct qdma_descq_sw_ctxt *ctxt) -{ - uint32_t sw_ctxt[QDMA_CPM4_SW_CONTEXT_NUM_WORDS] = {0}; - uint16_t num_words_count = 0; - enum ind_ctxt_cmd_sel sel = c2h ? - QDMA_CTXT_SEL_SW_C2H : QDMA_CTXT_SEL_SW_H2C; - - /* Input args check */ - if (!dev_hndl || !ctxt) { - qdma_log_error("%s: dev_hndl or ctxt is NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - if ((ctxt->desc_sz > QDMA_DESC_SIZE_64B) || - (ctxt->rngsz_idx >= QDMA_NUM_RING_SIZES)) { - qdma_log_error("%s: Invalid desc_sz(%d)/rngidx(%d), err:%d\n", - __func__, - ctxt->desc_sz, - ctxt->rngsz_idx, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - sw_ctxt[num_words_count++] = - FIELD_SET(SW_IND_CTXT_DATA_W0_PIDX_MASK, ctxt->pidx) | - FIELD_SET(SW_IND_CTXT_DATA_W0_IRQ_ARM_MASK, ctxt->irq_arm); - - sw_ctxt[num_words_count++] = - FIELD_SET(SW_IND_CTXT_DATA_W1_QEN_MASK, ctxt->qen) | - FIELD_SET(SW_IND_CTXT_DATA_W1_FCRD_EN_MASK, ctxt->frcd_en) | - FIELD_SET(SW_IND_CTXT_DATA_W1_WBI_CHK_MASK, ctxt->wbi_chk) | - FIELD_SET(SW_IND_CTXT_DATA_W1_WBI_INTVL_EN_MASK, - ctxt->wbi_intvl_en) | - FIELD_SET(SW_IND_CTXT_DATA_W1_FNC_ID_MASK, ctxt->fnc_id) | - FIELD_SET(SW_IND_CTXT_DATA_W1_RNG_SZ_MASK, ctxt->rngsz_idx) | - FIELD_SET(SW_IND_CTXT_DATA_W1_DSC_SZ_MASK, ctxt->desc_sz) | - FIELD_SET(SW_IND_CTXT_DATA_W1_BYPASS_MASK, ctxt->bypass) | - FIELD_SET(SW_IND_CTXT_DATA_W1_MM_CHN_MASK, ctxt->mm_chn) | - FIELD_SET(SW_IND_CTXT_DATA_W1_WBK_EN_MASK, ctxt->wbk_en) | - FIELD_SET(SW_IND_CTXT_DATA_W1_IRQ_EN_MASK, ctxt->irq_en) | - FIELD_SET(SW_IND_CTXT_DATA_W1_PORT_ID_MASK, ctxt->port_id) | - FIELD_SET(SW_IND_CTXT_DATA_W1_IRQ_NO_LAST_MASK, - ctxt->irq_no_last) | - FIELD_SET(SW_IND_CTXT_DATA_W1_ERR_MASK, ctxt->err) | - FIELD_SET(SW_IND_CTXT_DATA_W1_ERR_WB_SENT_MASK, - ctxt->err_wb_sent) | - FIELD_SET(SW_IND_CTXT_DATA_W1_IRQ_REQ_MASK, ctxt->irq_req) | - FIELD_SET(SW_IND_CTXT_DATA_W1_MRKR_DIS_MASK, ctxt->mrkr_dis) | - FIELD_SET(SW_IND_CTXT_DATA_W1_IS_MM_MASK, ctxt->is_mm); - - sw_ctxt[num_words_count++] = ctxt->ring_bs_addr & 0xffffffff; - sw_ctxt[num_words_count++] = (ctxt->ring_bs_addr >> 32) & 0xffffffff; - - return qdma_cpm4_indirect_reg_write(dev_hndl, sel, hw_qid, - sw_ctxt, num_words_count); -} - -/*****************************************************************************/ -/** - * qdma_cpm4_sw_context_read() - read sw context - * - * @dev_hndl: device handle - * @c2h: is c2h queue - * @hw_qid: hardware qid of the queue - * @ctxt: pointer to the output context data - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -static int qdma_cpm4_sw_context_read(void *dev_hndl, uint8_t c2h, - uint16_t hw_qid, - struct qdma_descq_sw_ctxt *ctxt) -{ - int rv = 0; - uint32_t sw_ctxt[QDMA_CPM4_SW_CONTEXT_NUM_WORDS] = {0}; - enum ind_ctxt_cmd_sel sel = c2h ? - QDMA_CTXT_SEL_SW_C2H : QDMA_CTXT_SEL_SW_H2C; - struct qdma_qid2vec qid2vec_ctxt = {0}; - - if (!dev_hndl || !ctxt) { - qdma_log_error("%s: dev_hndl=%p sw_ctxt=%p, err:%d\n", - __func__, dev_hndl, ctxt, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - rv = qdma_cpm4_indirect_reg_read(dev_hndl, sel, hw_qid, - QDMA_CPM4_SW_CONTEXT_NUM_WORDS, sw_ctxt); - if (rv < 0) - return rv; - - ctxt->pidx = FIELD_GET(SW_IND_CTXT_DATA_W0_PIDX_MASK, sw_ctxt[0]); - ctxt->irq_arm = - (uint8_t)(FIELD_GET(SW_IND_CTXT_DATA_W0_IRQ_ARM_MASK, - sw_ctxt[0])); - - ctxt->qen = FIELD_GET(SW_IND_CTXT_DATA_W1_QEN_MASK, sw_ctxt[1]); - ctxt->frcd_en = FIELD_GET(SW_IND_CTXT_DATA_W1_FCRD_EN_MASK, - sw_ctxt[1]); - ctxt->wbi_chk = FIELD_GET(SW_IND_CTXT_DATA_W1_WBI_CHK_MASK, - sw_ctxt[1]); - ctxt->wbi_intvl_en = - FIELD_GET(SW_IND_CTXT_DATA_W1_WBI_INTVL_EN_MASK, - sw_ctxt[1]); - ctxt->fnc_id = - (uint8_t)(FIELD_GET(SW_IND_CTXT_DATA_W1_FNC_ID_MASK, - sw_ctxt[1])); - ctxt->rngsz_idx = - (uint8_t)(FIELD_GET(SW_IND_CTXT_DATA_W1_RNG_SZ_MASK, - sw_ctxt[1])); - ctxt->desc_sz = - (uint8_t)(FIELD_GET(SW_IND_CTXT_DATA_W1_DSC_SZ_MASK, - sw_ctxt[1])); - ctxt->bypass = - (uint8_t)(FIELD_GET(SW_IND_CTXT_DATA_W1_BYPASS_MASK, - sw_ctxt[1])); - ctxt->mm_chn = - (uint8_t)(FIELD_GET(SW_IND_CTXT_DATA_W1_MM_CHN_MASK, - sw_ctxt[1])); - ctxt->wbk_en = - (uint8_t)(FIELD_GET(SW_IND_CTXT_DATA_W1_WBK_EN_MASK, - sw_ctxt[1])); - ctxt->irq_en = - (uint8_t)(FIELD_GET(SW_IND_CTXT_DATA_W1_IRQ_EN_MASK, - sw_ctxt[1])); - ctxt->port_id = - (uint8_t)(FIELD_GET(SW_IND_CTXT_DATA_W1_PORT_ID_MASK, - sw_ctxt[1])); - ctxt->irq_no_last = - (uint8_t)(FIELD_GET(SW_IND_CTXT_DATA_W1_IRQ_NO_LAST_MASK, - sw_ctxt[1])); - ctxt->err = - (uint8_t)(FIELD_GET(SW_IND_CTXT_DATA_W1_ERR_MASK, sw_ctxt[1])); - ctxt->err_wb_sent = - (uint8_t)(FIELD_GET(SW_IND_CTXT_DATA_W1_ERR_WB_SENT_MASK, - sw_ctxt[1])); - ctxt->irq_req = - (uint8_t)(FIELD_GET(SW_IND_CTXT_DATA_W1_IRQ_REQ_MASK, - sw_ctxt[1])); - ctxt->mrkr_dis = - (uint8_t)(FIELD_GET(SW_IND_CTXT_DATA_W1_MRKR_DIS_MASK, - sw_ctxt[1])); - ctxt->is_mm = - (uint8_t)(FIELD_GET(SW_IND_CTXT_DATA_W1_IS_MM_MASK, - sw_ctxt[1])); - - ctxt->ring_bs_addr = ((uint64_t)sw_ctxt[3] << 32) | (sw_ctxt[2]); - - /** Read the QID2VEC Context Data */ - rv = qdma_cpm4_qid2vec_read(dev_hndl, c2h, hw_qid, &qid2vec_ctxt); - if (rv < 0) - return rv; - - if (c2h) { - ctxt->vec = qid2vec_ctxt.c2h_vector; - ctxt->intr_aggr = qid2vec_ctxt.c2h_en_coal; - } else { - ctxt->vec = qid2vec_ctxt.h2c_vector; - ctxt->intr_aggr = qid2vec_ctxt.h2c_en_coal; - } - - - return QDMA_SUCCESS; -} - -/*****************************************************************************/ -/** - * qdma_cpm4_sw_context_clear() - clear sw context - * - * @dev_hndl: device handle - * @c2h: is c2h queue - * @hw_qid: hardware qid of the queue - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -static int qdma_cpm4_sw_context_clear(void *dev_hndl, uint8_t c2h, - uint16_t hw_qid) -{ - enum ind_ctxt_cmd_sel sel = c2h ? - QDMA_CTXT_SEL_SW_C2H : QDMA_CTXT_SEL_SW_H2C; - - if (!dev_hndl) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - return qdma_cpm4_indirect_reg_clear(dev_hndl, sel, hw_qid); -} - -/*****************************************************************************/ -/** - * qdma_cpm4_sw_context_invalidate() - invalidate sw context - * - * @dev_hndl: device handle - * @c2h: is c2h queue - * @hw_qid: hardware qid of the queue - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -static int qdma_cpm4_sw_context_invalidate(void *dev_hndl, uint8_t c2h, - uint16_t hw_qid) -{ - enum ind_ctxt_cmd_sel sel = c2h ? - QDMA_CTXT_SEL_SW_C2H : QDMA_CTXT_SEL_SW_H2C; - - if (!dev_hndl) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - return qdma_cpm4_indirect_reg_invalidate(dev_hndl, sel, hw_qid); -} - -/*****************************************************************************/ -/** - * qdma_cpm4_sw_ctx_conf() - configure SW context - * - * @dev_hndl: device handle - * @c2h: is c2h queue - * @hw_qid: hardware qid of the queue - * @ctxt: pointer to the context data - * @access_type HW access type (qdma_hw_access_type enum) value - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -int qdma_cpm4_sw_ctx_conf(void *dev_hndl, uint8_t c2h, uint16_t hw_qid, - struct qdma_descq_sw_ctxt *ctxt, - enum qdma_hw_access_type access_type) -{ - int ret_val = 0; - - switch (access_type) { - case QDMA_HW_ACCESS_READ: - ret_val = qdma_cpm4_sw_context_read(dev_hndl, c2h, hw_qid, - ctxt); - break; - case QDMA_HW_ACCESS_WRITE: - ret_val = qdma_cpm4_sw_context_write(dev_hndl, c2h, hw_qid, - ctxt); - break; - case QDMA_HW_ACCESS_CLEAR: - ret_val = qdma_cpm4_sw_context_clear(dev_hndl, c2h, hw_qid); - break; - case QDMA_HW_ACCESS_INVALIDATE: - ret_val = qdma_cpm4_sw_context_invalidate(dev_hndl, - c2h, hw_qid); - break; - default: - qdma_log_error("%s: access_type=%d is invalid, err:%d\n", - __func__, access_type, - -QDMA_ERR_INV_PARAM); - ret_val = -QDMA_ERR_INV_PARAM; - break; - } - return ret_val; -} - -/*****************************************************************************/ -/** - * qdma_cpm4_pfetch_context_write() - create prefetch context and program it - * - * @dev_hndl: device handle - * @hw_qid: hardware qid of the queue - * @ctxt: pointer to the prefetch context data strucutre - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -static int qdma_cpm4_pfetch_context_write(void *dev_hndl, uint16_t hw_qid, - const struct qdma_descq_prefetch_ctxt *ctxt) -{ - uint32_t pfetch_ctxt[QDMA_CPM4_PFETCH_CONTEXT_NUM_WORDS] = {0}; - enum ind_ctxt_cmd_sel sel = QDMA_CTXT_SEL_PFTCH; - uint32_t sw_crdt_l, sw_crdt_h; - uint16_t num_words_count = 0; - - if (!dev_hndl || !ctxt) { - qdma_log_error("%s: dev_hndl=%p pfetch_ctxt=%p, err:%d\n", - __func__, dev_hndl, ctxt, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - sw_crdt_l = - FIELD_GET(QDMA_PFTCH_CTXT_SW_CRDT_GET_L_MASK, ctxt->sw_crdt); - sw_crdt_h = - FIELD_GET(QDMA_PFTCH_CTXT_SW_CRDT_GET_H_MASK, ctxt->sw_crdt); - - pfetch_ctxt[num_words_count++] = - FIELD_SET(PREFETCH_CTXT_DATA_W0_BYPASS_MASK, ctxt->bypass) | - FIELD_SET(PREFETCH_CTXT_DATA_W0_BUF_SIZE_IDX_MASK, - ctxt->bufsz_idx) | - FIELD_SET(PREFETCH_CTXT_DATA_W0_PORT_ID_MASK, ctxt->port_id) | - FIELD_SET(PREFETCH_CTXT_DATA_W0_ERR_MASK, ctxt->err) | - FIELD_SET(PREFETCH_CTXT_DATA_W0_PFCH_EN_MASK, ctxt->pfch_en) | - FIELD_SET(PREFETCH_CTXT_DATA_W0_PFCH_MASK, ctxt->pfch) | - FIELD_SET(PREFETCH_CTXT_DATA_W0_SW_CRDT_L_MASK, sw_crdt_l); - - pfetch_ctxt[num_words_count++] = - FIELD_SET(PREFETCH_CTXT_DATA_W1_SW_CRDT_H_MASK, sw_crdt_h) | - FIELD_SET(PREFETCH_CTXT_DATA_W1_VALID_MASK, ctxt->valid); - - return qdma_cpm4_indirect_reg_write(dev_hndl, sel, hw_qid, - pfetch_ctxt, num_words_count); -} - -/*****************************************************************************/ -/** - * qdma_cpm4_pfetch_context_read() - read prefetch context - * - * @dev_hndl: device handle - * @hw_qid: hardware qid of the queue - * @ctxt: pointer to the output context data - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -static int qdma_cpm4_pfetch_context_read(void *dev_hndl, uint16_t hw_qid, - struct qdma_descq_prefetch_ctxt *ctxt) -{ - int rv = 0; - uint32_t pfetch_ctxt[QDMA_CPM4_PFETCH_CONTEXT_NUM_WORDS] = {0}; - enum ind_ctxt_cmd_sel sel = QDMA_CTXT_SEL_PFTCH; - uint32_t sw_crdt_l, sw_crdt_h; - - if (!dev_hndl || !ctxt) { - qdma_log_error("%s: dev_hndl=%p pfetch_ctxt=%p, err:%d\n", - __func__, dev_hndl, ctxt, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - rv = qdma_cpm4_indirect_reg_read(dev_hndl, sel, hw_qid, - QDMA_CPM4_PFETCH_CONTEXT_NUM_WORDS, pfetch_ctxt); - if (rv < 0) - return rv; - - ctxt->bypass = - (uint8_t)(FIELD_GET(PREFETCH_CTXT_DATA_W0_BYPASS_MASK, - pfetch_ctxt[0])); - ctxt->bufsz_idx = - (uint8_t)(FIELD_GET(PREFETCH_CTXT_DATA_W0_BUF_SIZE_IDX_MASK, - pfetch_ctxt[0])); - ctxt->port_id = - (uint8_t)(FIELD_GET(PREFETCH_CTXT_DATA_W0_PORT_ID_MASK, - pfetch_ctxt[0])); - ctxt->err = - (uint8_t)(FIELD_GET(PREFETCH_CTXT_DATA_W0_ERR_MASK, - pfetch_ctxt[0])); - ctxt->pfch_en = - (uint8_t)(FIELD_GET(PREFETCH_CTXT_DATA_W0_PFCH_EN_MASK, - pfetch_ctxt[0])); - ctxt->pfch = - (uint8_t)(FIELD_GET(PREFETCH_CTXT_DATA_W0_PFCH_MASK, - pfetch_ctxt[0])); - sw_crdt_l = - (uint32_t)FIELD_GET(PREFETCH_CTXT_DATA_W0_SW_CRDT_L_MASK, - pfetch_ctxt[0]); - - sw_crdt_h = - (uint32_t)FIELD_GET(PREFETCH_CTXT_DATA_W1_SW_CRDT_H_MASK, - pfetch_ctxt[1]); - ctxt->valid = - (uint8_t)(FIELD_GET(PREFETCH_CTXT_DATA_W1_VALID_MASK, - pfetch_ctxt[1])); - - ctxt->sw_crdt = - (uint16_t)(FIELD_SET(QDMA_PFTCH_CTXT_SW_CRDT_GET_L_MASK, - sw_crdt_l) | - FIELD_SET(QDMA_PFTCH_CTXT_SW_CRDT_GET_H_MASK, sw_crdt_h)); - - return QDMA_SUCCESS; -} - -/*****************************************************************************/ -/** - * qdma_cpm4_pfetch_context_clear() - clear prefetch context - * - * @dev_hndl: device handle - * @hw_qid: hardware qid of the queue - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -static int qdma_cpm4_pfetch_context_clear(void *dev_hndl, uint16_t hw_qid) -{ - enum ind_ctxt_cmd_sel sel = QDMA_CTXT_SEL_PFTCH; - - if (!dev_hndl) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - return qdma_cpm4_indirect_reg_clear(dev_hndl, sel, hw_qid); -} - -/*****************************************************************************/ -/** - * qdma_cpm4_pfetch_context_invalidate() - invalidate prefetch context - * - * @dev_hndl: device handle - * @hw_qid: hardware qid of the queue - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -static int qdma_cpm4_pfetch_context_invalidate(void *dev_hndl, - uint16_t hw_qid) -{ - enum ind_ctxt_cmd_sel sel = QDMA_CTXT_SEL_PFTCH; - - if (!dev_hndl) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - return qdma_cpm4_indirect_reg_invalidate(dev_hndl, sel, hw_qid); -} - -/*****************************************************************************/ -/** - * qdma_cpm4_pfetch_ctx_conf() - configure prefetch context - * - * @dev_hndl: device handle - * @hw_qid: hardware qid of the queue - * @ctxt: pointer to context data - * @access_type HW access type (qdma_hw_access_type enum) value - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -int qdma_cpm4_pfetch_ctx_conf(void *dev_hndl, uint16_t hw_qid, - struct qdma_descq_prefetch_ctxt *ctxt, - enum qdma_hw_access_type access_type) -{ - int ret_val = 0; - - switch (access_type) { - case QDMA_HW_ACCESS_READ: - ret_val = qdma_cpm4_pfetch_context_read(dev_hndl, - hw_qid, ctxt); - break; - case QDMA_HW_ACCESS_WRITE: - ret_val = qdma_cpm4_pfetch_context_write(dev_hndl, - hw_qid, ctxt); - break; - case QDMA_HW_ACCESS_CLEAR: - ret_val = qdma_cpm4_pfetch_context_clear(dev_hndl, hw_qid); - break; - case QDMA_HW_ACCESS_INVALIDATE: - ret_val = qdma_cpm4_pfetch_context_invalidate(dev_hndl, - hw_qid); - break; - default: - qdma_log_error("%s: access_type=%d is invalid, err:%d\n", - __func__, access_type, - -QDMA_ERR_INV_PARAM); - ret_val = -QDMA_ERR_INV_PARAM; - break; - } - - return ret_val; -} - -/*****************************************************************************/ -/** - * qdma_cpm4_cmpt_context_write() - create completion context and program it - * - * @dev_hndl: device handle - * @hw_qid: hardware qid of the queue - * @ctxt: pointer to the cmpt context data strucutre - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -static int qdma_cpm4_cmpt_context_write(void *dev_hndl, uint16_t hw_qid, - const struct qdma_descq_cmpt_ctxt *ctxt) -{ - uint32_t cmpt_ctxt[QDMA_CPM4_CMPT_CONTEXT_NUM_WORDS] = {0}; - uint16_t num_words_count = 0; - uint32_t baddr_l, baddr_h, baddr_m, pidx_l, pidx_h; - enum ind_ctxt_cmd_sel sel = QDMA_CTXT_SEL_CMPT; - - /* Input args check */ - if (!dev_hndl || !ctxt) { - qdma_log_error("%s: dev_hndl=%p cmpt_ctxt=%p, err:%d\n", - __func__, dev_hndl, ctxt, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - if ((ctxt->desc_sz > QDMA_DESC_SIZE_32B) || - (ctxt->ringsz_idx >= QDMA_NUM_RING_SIZES) || - (ctxt->counter_idx >= QDMA_NUM_C2H_COUNTERS) || - (ctxt->timer_idx >= QDMA_NUM_C2H_TIMERS) || - (ctxt->trig_mode > QDMA_CMPT_UPDATE_TRIG_MODE_TMR_CNTR)) { - qdma_log_error - ("%s Inv dsz(%d)/ridx(%d)/cntr(%d)/tmr(%d)/tm(%d), err:%d\n", - __func__, - ctxt->desc_sz, - ctxt->ringsz_idx, - ctxt->counter_idx, - ctxt->timer_idx, - ctxt->trig_mode, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - baddr_l = - (uint32_t)FIELD_GET(QDMA_CPM4_COMPL_CTXT_BADDR_GET_L_MASK, - ctxt->bs_addr); - baddr_m = - (uint32_t)FIELD_GET(QDMA_CPM4_COMPL_CTXT_BADDR_GET_M_MASK, - ctxt->bs_addr); - baddr_h = - (uint32_t)FIELD_GET(QDMA_CPM4_COMPL_CTXT_BADDR_GET_H_MASK, - ctxt->bs_addr); - - pidx_l = FIELD_GET(QDMA_CPM4_COMPL_CTXT_PIDX_GET_L_MASK, - ctxt->pidx); - pidx_h = FIELD_GET(QDMA_CPM4_COMPL_CTXT_PIDX_GET_H_MASK, - ctxt->pidx); - - cmpt_ctxt[num_words_count++] = - FIELD_SET(CMPL_CTXT_DATA_W0_EN_STAT_DESC_MASK, - ctxt->en_stat_desc) | - FIELD_SET(CMPL_CTXT_DATA_W0_EN_INT_MASK, ctxt->en_int) | - FIELD_SET(CMPL_CTXT_DATA_W0_TRIG_MODE_MASK, ctxt->trig_mode) | - FIELD_SET(CMPL_CTXT_DATA_W0_FNC_ID_MASK, ctxt->fnc_id) | - FIELD_SET(CMPL_CTXT_DATA_W0_CNTER_IDX_MASK, - ctxt->counter_idx) | - FIELD_SET(CMPL_CTXT_DATA_W0_TIMER_IDX_MASK, - ctxt->timer_idx) | - FIELD_SET(CMPL_CTXT_DATA_W0_INT_ST_MASK, - ctxt->in_st) | - FIELD_SET(CMPL_CTXT_DATA_W0_COLOR_MASK, - ctxt->color) | - FIELD_SET(CMPL_CTXT_DATA_W0_QSIZE_IDX_MASK, - ctxt->ringsz_idx) | - FIELD_SET(CMPL_CTXT_DATA_W0_BADDR_64_L_MASK, - baddr_l); - - cmpt_ctxt[num_words_count++] = - FIELD_SET(CMPL_CTXT_DATA_W1_BADDR_64_M_MASK, - baddr_m); - - cmpt_ctxt[num_words_count++] = - FIELD_SET(CMPL_CTXT_DATA_W2_BADDR_64_H_MASK, - baddr_h) | - FIELD_SET(CMPL_CTXT_DATA_W2_DESC_SIZE_MASK, - ctxt->desc_sz) | - FIELD_SET(CMPL_CTXT_DATA_W2_PIDX_L_MASK, - pidx_l); - - cmpt_ctxt[num_words_count++] = - FIELD_SET(CMPL_CTXT_DATA_W3_PIDX_H_MASK, - pidx_h) | - FIELD_SET(CMPL_CTXT_DATA_W3_CIDX_MASK, ctxt->cidx) | - FIELD_SET(CMPL_CTXT_DATA_W3_VALID_MASK, ctxt->valid) | - FIELD_SET(CMPL_CTXT_DATA_W3_ERR_MASK, ctxt->err) | - FIELD_SET(CMPL_CTXT_DATA_W3_USER_TRIG_PEND_MASK, - ctxt->user_trig_pend) | - FIELD_SET(CMPL_CTXT_DATA_W3_TIMER_RUNNING_MASK, - ctxt->timer_running) | - FIELD_SET(CMPL_CTXT_DATA_W3_FULL_UPD_MASK, - ctxt->full_upd); - - return qdma_cpm4_indirect_reg_write(dev_hndl, sel, hw_qid, - cmpt_ctxt, num_words_count); - -} - -/*****************************************************************************/ -/** - * qdma_cpm4_cmpt_context_read() - read completion context - * - * @dev_hndl: device handle - * @hw_qid: hardware qid of the queue - * @ctxt: pointer to the context data - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -static int qdma_cpm4_cmpt_context_read(void *dev_hndl, uint16_t hw_qid, - struct qdma_descq_cmpt_ctxt *ctxt) -{ - int rv = 0; - uint32_t cmpt_ctxt[QDMA_CPM4_CMPT_CONTEXT_NUM_WORDS] = {0}; - enum ind_ctxt_cmd_sel sel = QDMA_CTXT_SEL_CMPT; - uint32_t baddr_l, baddr_h, baddr_m, - pidx_l, pidx_h; - - if (!dev_hndl || !ctxt) { - qdma_log_error("%s: dev_hndl=%p cmpt_ctxt=%p, err:%d\n", - __func__, dev_hndl, ctxt, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - rv = qdma_cpm4_indirect_reg_read(dev_hndl, sel, hw_qid, - QDMA_CPM4_CMPT_CONTEXT_NUM_WORDS, cmpt_ctxt); - if (rv < 0) - return rv; - - ctxt->en_stat_desc = - FIELD_GET(CMPL_CTXT_DATA_W0_EN_STAT_DESC_MASK, cmpt_ctxt[0]); - ctxt->en_int = FIELD_GET(CMPL_CTXT_DATA_W0_EN_INT_MASK, - cmpt_ctxt[0]); - ctxt->trig_mode = - FIELD_GET(CMPL_CTXT_DATA_W0_TRIG_MODE_MASK, cmpt_ctxt[0]); - ctxt->fnc_id = - (uint8_t)(FIELD_GET(CMPL_CTXT_DATA_W0_FNC_ID_MASK, - cmpt_ctxt[0])); - ctxt->counter_idx = - (uint8_t)(FIELD_GET( - CMPL_CTXT_DATA_W0_CNTER_IDX_MASK, - cmpt_ctxt[0])); - ctxt->timer_idx = - (uint8_t)(FIELD_GET(CMPL_CTXT_DATA_W0_TIMER_IDX_MASK, - cmpt_ctxt[0])); - ctxt->in_st = - (uint8_t)(FIELD_GET(CMPL_CTXT_DATA_W0_INT_ST_MASK, - cmpt_ctxt[0])); - ctxt->color = - (uint8_t)(FIELD_GET(CMPL_CTXT_DATA_W0_COLOR_MASK, - cmpt_ctxt[0])); - ctxt->ringsz_idx = - (uint8_t)(FIELD_GET(CMPL_CTXT_DATA_W0_QSIZE_IDX_MASK, - cmpt_ctxt[0])); - - baddr_l = - FIELD_GET(CMPL_CTXT_DATA_W0_BADDR_64_L_MASK, - cmpt_ctxt[0]); - baddr_m = - FIELD_GET(CMPL_CTXT_DATA_W1_BADDR_64_M_MASK, - cmpt_ctxt[1]); - baddr_h = - FIELD_GET(CMPL_CTXT_DATA_W2_BADDR_64_H_MASK, - cmpt_ctxt[2]); - - ctxt->desc_sz = - (uint8_t)(FIELD_GET(CMPL_CTXT_DATA_W2_DESC_SIZE_MASK, - cmpt_ctxt[2])); - pidx_l = FIELD_GET(CMPL_CTXT_DATA_W2_PIDX_L_MASK, - cmpt_ctxt[2]); - - pidx_h = FIELD_GET(CMPL_CTXT_DATA_W3_PIDX_H_MASK, - cmpt_ctxt[3]); - ctxt->cidx = - (uint16_t)(FIELD_GET(CMPL_CTXT_DATA_W3_CIDX_MASK, - cmpt_ctxt[3])); - ctxt->valid = - (uint8_t)(FIELD_GET(CMPL_CTXT_DATA_W3_VALID_MASK, - cmpt_ctxt[3])); - ctxt->err = - (uint8_t)(FIELD_GET(CMPL_CTXT_DATA_W3_ERR_MASK, - cmpt_ctxt[3])); - ctxt->user_trig_pend = - (uint8_t)(FIELD_GET( - CMPL_CTXT_DATA_W3_USER_TRIG_PEND_MASK, cmpt_ctxt[3])); - - ctxt->timer_running = - (uint8_t)(FIELD_GET(CMPL_CTXT_DATA_W3_TIMER_RUNNING_MASK, - cmpt_ctxt[3])); - ctxt->full_upd = - (uint8_t)(FIELD_GET(CMPL_CTXT_DATA_W3_FULL_UPD_MASK, - cmpt_ctxt[3])); - - ctxt->bs_addr = - FIELD_SET(QDMA_CPM4_COMPL_CTXT_BADDR_GET_L_MASK, - (uint64_t)baddr_l) | - FIELD_SET(QDMA_CPM4_COMPL_CTXT_BADDR_GET_M_MASK, - (uint64_t)baddr_m) | - FIELD_SET(QDMA_CPM4_COMPL_CTXT_BADDR_GET_H_MASK, - (uint64_t)baddr_h); - - ctxt->pidx = - (uint16_t)(FIELD_SET(QDMA_CPM4_COMPL_CTXT_PIDX_GET_L_MASK, - pidx_l) | - FIELD_SET(QDMA_CPM4_COMPL_CTXT_PIDX_GET_H_MASK, - pidx_h)); - - return QDMA_SUCCESS; -} - -/*****************************************************************************/ -/** - * qdma_cpm4_cmpt_context_clear() - clear completion context - * - * @dev_hndl: device handle - * @hw_qid: hardware qid of the queue - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -static int qdma_cpm4_cmpt_context_clear(void *dev_hndl, uint16_t hw_qid) -{ - enum ind_ctxt_cmd_sel sel = QDMA_CTXT_SEL_CMPT; - - if (!dev_hndl) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - return qdma_cpm4_indirect_reg_clear(dev_hndl, sel, hw_qid); -} - -/*****************************************************************************/ -/** - * qdma_cpm4_cmpt_context_invalidate() - invalidate completion context - * - * @dev_hndl: device handle - * @hw_qid: hardware qid of the queue - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -static int qdma_cpm4_cmpt_context_invalidate(void *dev_hndl, - uint16_t hw_qid) -{ - enum ind_ctxt_cmd_sel sel = QDMA_CTXT_SEL_CMPT; - - if (!dev_hndl) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - return qdma_cpm4_indirect_reg_invalidate(dev_hndl, sel, hw_qid); -} - -/*****************************************************************************/ -/** - * qdma_cpm4_cmpt_ctx_conf() - configure completion context - * - * @dev_hndl: device handle - * @hw_qid: hardware qid of the queue - * @ctxt: pointer to context data - * @access_type HW access type (qdma_hw_access_type enum) value - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -int qdma_cpm4_cmpt_ctx_conf(void *dev_hndl, uint16_t hw_qid, - struct qdma_descq_cmpt_ctxt *ctxt, - enum qdma_hw_access_type access_type) -{ - int ret_val = 0; - - if (!dev_hndl) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - switch (access_type) { - case QDMA_HW_ACCESS_READ: - ret_val = qdma_cpm4_cmpt_context_read(dev_hndl, - hw_qid, ctxt); - break; - case QDMA_HW_ACCESS_WRITE: - ret_val = qdma_cpm4_cmpt_context_write(dev_hndl, - hw_qid, ctxt); - break; - case QDMA_HW_ACCESS_CLEAR: - ret_val = qdma_cpm4_cmpt_context_clear(dev_hndl, hw_qid); - break; - case QDMA_HW_ACCESS_INVALIDATE: - ret_val = qdma_cpm4_cmpt_context_invalidate(dev_hndl, - hw_qid); - break; - default: - qdma_log_error("%s: access_type=%d is invalid, err:%d\n", - __func__, access_type, - -QDMA_ERR_INV_PARAM); - ret_val = -QDMA_ERR_INV_PARAM; - break; - } - - return ret_val; -} - -/*****************************************************************************/ -/** - * qdma_cpm4_hw_context_read() - read hardware context - * - * @dev_hndl: device handle - * @c2h: is c2h queue - * @hw_qid: hardware qid of the queue - * @ctxt: pointer to the output context data - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -static int qdma_cpm4_hw_context_read(void *dev_hndl, uint8_t c2h, - uint16_t hw_qid, struct qdma_descq_hw_ctxt *ctxt) -{ - int rv = 0; - uint32_t hw_ctxt[QDMA_CPM4_HW_CONTEXT_NUM_WORDS] = {0}; - enum ind_ctxt_cmd_sel sel = c2h ? QDMA_CTXT_SEL_HW_C2H : - QDMA_CTXT_SEL_HW_H2C; - - if (!dev_hndl || !ctxt) { - qdma_log_error("%s: dev_hndl=%p hw_ctxt=%p, err:%d\n", - __func__, dev_hndl, ctxt, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - rv = qdma_cpm4_indirect_reg_read(dev_hndl, sel, hw_qid, - QDMA_CPM4_HW_CONTEXT_NUM_WORDS, hw_ctxt); - if (rv < 0) - return rv; - - ctxt->cidx = FIELD_GET(HW_IND_CTXT_DATA_W0_CIDX_MASK, hw_ctxt[0]); - ctxt->crd_use = - (uint16_t)(FIELD_GET(HW_IND_CTXT_DATA_W0_CRD_USE_MASK, - hw_ctxt[0])); - - ctxt->dsc_pend = - (uint8_t)(FIELD_GET(HW_IND_CTXT_DATA_W1_DSC_PND_MASK, - hw_ctxt[1])); - ctxt->idl_stp_b = - (uint8_t)(FIELD_GET(HW_IND_CTXT_DATA_W1_IDL_STP_B_MASK, - hw_ctxt[1])); - ctxt->fetch_pnd = - (uint8_t)(FIELD_GET(HW_IND_CTXT_DATA_W1_FETCH_PND_MASK, - hw_ctxt[1])); - - return QDMA_SUCCESS; -} - -/*****************************************************************************/ -/** - * qdma_cpm4_hw_context_clear() - clear hardware context - * - * @dev_hndl: device handle - * @c2h: is c2h queue - * @hw_qid: hardware qid of the queue - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -static int qdma_cpm4_hw_context_clear(void *dev_hndl, uint8_t c2h, - uint16_t hw_qid) -{ - enum ind_ctxt_cmd_sel sel = c2h ? QDMA_CTXT_SEL_HW_C2H : - QDMA_CTXT_SEL_HW_H2C; - - if (!dev_hndl) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - return qdma_cpm4_indirect_reg_clear(dev_hndl, sel, hw_qid); -} - -/*****************************************************************************/ -/** - * qdma_cpm4_hw_context_invalidate() - invalidate hardware context - * - * @dev_hndl: device handle - * @c2h: is c2h queue - * @hw_qid: hardware qid of the queue - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -static int qdma_cpm4_hw_context_invalidate(void *dev_hndl, uint8_t c2h, - uint16_t hw_qid) -{ - enum ind_ctxt_cmd_sel sel = c2h ? QDMA_CTXT_SEL_HW_C2H : - QDMA_CTXT_SEL_HW_H2C; - - if (!dev_hndl) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - return qdma_cpm4_indirect_reg_invalidate(dev_hndl, sel, hw_qid); -} - -/*****************************************************************************/ -/** - * qdma_cpm4_hw_ctx_conf() - configure HW context - * - * @dev_hndl: device handle - * @c2h: is c2h queue - * @hw_qid: hardware qid of the queue - * @ctxt: pointer to context data - * @access_type HW access type (qdma_hw_access_type enum) value - * QDMA_HW_ACCESS_WRITE unsupported - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -int qdma_cpm4_hw_ctx_conf(void *dev_hndl, uint8_t c2h, uint16_t hw_qid, - struct qdma_descq_hw_ctxt *ctxt, - enum qdma_hw_access_type access_type) -{ - int ret_val = 0; - - switch (access_type) { - case QDMA_HW_ACCESS_READ: - ret_val = qdma_cpm4_hw_context_read(dev_hndl, c2h, hw_qid, - ctxt); - break; - case QDMA_HW_ACCESS_CLEAR: - ret_val = qdma_cpm4_hw_context_clear(dev_hndl, c2h, hw_qid); - break; - case QDMA_HW_ACCESS_INVALIDATE: - ret_val = qdma_cpm4_hw_context_invalidate(dev_hndl, c2h, - hw_qid); - break; - case QDMA_HW_ACCESS_WRITE: - default: - qdma_log_error("%s: access_type=%d is invalid, err:%d\n", - __func__, access_type, - -QDMA_ERR_INV_PARAM); - ret_val = -QDMA_ERR_INV_PARAM; - break; - } - - - return ret_val; -} - -/*****************************************************************************/ -/** - * qdma_cpm4_indirect_intr_context_write() - create indirect - * interrupt context and program it - * - * @dev_hndl: device handle - * @ring_index: indirect interrupt ring index - * @ctxt: pointer to the interrupt context data strucutre - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -static int qdma_cpm4_indirect_intr_context_write(void *dev_hndl, - uint16_t ring_index, const struct qdma_indirect_intr_ctxt *ctxt) -{ - uint32_t intr_ctxt[QDMA_CPM4_IND_INTR_CONTEXT_NUM_WORDS] = {0}; - enum ind_ctxt_cmd_sel sel = QDMA_CTXT_SEL_INT_COAL; - uint16_t num_words_count = 0; - uint32_t baddr_l, baddr_h; - - if (!dev_hndl || !ctxt) { - qdma_log_error("%s: dev_hndl=%p intr_ctxt=%p, err:%d\n", - __func__, dev_hndl, ctxt, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - if (ctxt->page_size > QDMA_INDIRECT_INTR_RING_SIZE_32KB) { - qdma_log_error("%s: ctxt->page_size=%u is too big, err:%d\n", - __func__, ctxt->page_size, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - baddr_l = - (uint32_t)FIELD_GET(QDMA_CPM4_INTR_CTXT_BADDR_GET_L_MASK, - ctxt->baddr_4k); - baddr_h = - (uint32_t)FIELD_GET(QDMA_CPM4_INTR_CTXT_BADDR_GET_H_MASK, - ctxt->baddr_4k); - - intr_ctxt[num_words_count++] = - FIELD_SET(INTR_CTXT_DATA_W0_VALID_MASK, ctxt->valid) | - FIELD_SET(INTR_CTXT_DATA_W0_VEC_MASK, ctxt->vec) | - FIELD_SET(INTR_CTXT_DATA_W0_INT_ST_MASK, - ctxt->int_st) | - FIELD_SET(INTR_CTXT_DATA_W0_COLOR_MASK, ctxt->color) | - FIELD_SET(INTR_CTXT_DATA_W0_BADDR_4K_L_MASK, baddr_l); - - intr_ctxt[num_words_count++] = - FIELD_SET(INTR_CTXT_DATA_W1_BADDR_4K_H_MASK, baddr_h) | - FIELD_SET(INTR_CTXT_DATA_W1_PAGE_SIZE_MASK, - ctxt->page_size); - - intr_ctxt[num_words_count++] = - FIELD_SET(INTR_CTXT_DATA_W2_PIDX_MASK, ctxt->pidx); - - return qdma_cpm4_indirect_reg_write(dev_hndl, sel, ring_index, - intr_ctxt, num_words_count); -} - -/*****************************************************************************/ -/** - * qdma_indirect_intr_context_read() - read indirect interrupt context - * - * @dev_hndl: device handle - * @ring_index: indirect interrupt ring index - * @ctxt: pointer to the output context data - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -static int qdma_cpm4_indirect_intr_context_read(void *dev_hndl, - uint16_t ring_index, struct qdma_indirect_intr_ctxt *ctxt) -{ - int rv = 0; - uint32_t intr_ctxt[QDMA_CPM4_IND_INTR_CONTEXT_NUM_WORDS] = {0}; - enum ind_ctxt_cmd_sel sel = QDMA_CTXT_SEL_INT_COAL; - uint64_t baddr_l, baddr_h; - - if (!dev_hndl || !ctxt) { - qdma_log_error("%s: dev_hndl=%p intr_ctxt=%p, err:%d\n", - __func__, dev_hndl, ctxt, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - rv = qdma_cpm4_indirect_reg_read(dev_hndl, sel, ring_index, - QDMA_CPM4_IND_INTR_CONTEXT_NUM_WORDS, intr_ctxt); - if (rv < 0) - return rv; - - ctxt->valid = FIELD_GET(INTR_CTXT_DATA_W0_VALID_MASK, intr_ctxt[0]); - ctxt->vec = FIELD_GET(INTR_CTXT_DATA_W0_VEC_MASK, - intr_ctxt[0]); - ctxt->int_st = FIELD_GET(INTR_CTXT_DATA_W0_INT_ST_MASK, - intr_ctxt[0]); - ctxt->color = - (uint8_t)(FIELD_GET(INTR_CTXT_DATA_W0_COLOR_MASK, - intr_ctxt[0])); - baddr_l = FIELD_GET(INTR_CTXT_DATA_W0_BADDR_4K_L_MASK, - intr_ctxt[0]); - - baddr_h = FIELD_GET(INTR_CTXT_DATA_W1_BADDR_4K_H_MASK, - intr_ctxt[1]); - ctxt->page_size = - (uint8_t)(FIELD_GET(INTR_CTXT_DATA_W1_PAGE_SIZE_MASK, - intr_ctxt[1])); - ctxt->pidx = FIELD_GET(INTR_CTXT_DATA_W2_PIDX_MASK, - intr_ctxt[2]); - - ctxt->baddr_4k = - FIELD_SET(QDMA_CPM4_INTR_CTXT_BADDR_GET_L_MASK, baddr_l) | - FIELD_SET(QDMA_CPM4_INTR_CTXT_BADDR_GET_H_MASK, baddr_h); - - return QDMA_SUCCESS; -} - -/*****************************************************************************/ -/** - * qdma_cpm4_indirect_intr_context_clear() - clear indirect - * interrupt context - * - * @dev_hndl: device handle - * @ring_index: indirect interrupt ring index - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -static int qdma_cpm4_indirect_intr_context_clear(void *dev_hndl, - uint16_t ring_index) -{ - enum ind_ctxt_cmd_sel sel = QDMA_CTXT_SEL_INT_COAL; - - if (!dev_hndl) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - return qdma_cpm4_indirect_reg_clear(dev_hndl, sel, ring_index); -} - -/*****************************************************************************/ -/** - * qdma_cpm4_indirect_intr_context_invalidate() - invalidate - * indirect interrupt context - * - * @dev_hndl: device handle - * @ring_index: indirect interrupt ring index - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -static int qdma_cpm4_indirect_intr_context_invalidate(void *dev_hndl, - uint16_t ring_index) -{ - enum ind_ctxt_cmd_sel sel = QDMA_CTXT_SEL_INT_COAL; - - if (!dev_hndl) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - return qdma_cpm4_indirect_reg_invalidate(dev_hndl, sel, ring_index); -} - -/*****************************************************************************/ -/** - * qdma_cpm4_indirect_intr_ctx_conf() - configure indirect interrupt context - * - * @dev_hndl: device handle - * @ring_index: indirect interrupt ring index - * @ctxt: pointer to context data - * @access_type HW access type (qdma_hw_access_type enum) value - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -int qdma_cpm4_indirect_intr_ctx_conf(void *dev_hndl, uint16_t ring_index, - struct qdma_indirect_intr_ctxt *ctxt, - enum qdma_hw_access_type access_type) -{ - int ret_val = 0; - - switch (access_type) { - case QDMA_HW_ACCESS_READ: - ret_val = qdma_cpm4_indirect_intr_context_read(dev_hndl, - ring_index, - ctxt); - break; - case QDMA_HW_ACCESS_WRITE: - ret_val = qdma_cpm4_indirect_intr_context_write(dev_hndl, - ring_index, - ctxt); - break; - case QDMA_HW_ACCESS_CLEAR: - ret_val = qdma_cpm4_indirect_intr_context_clear(dev_hndl, - ring_index); - break; - case QDMA_HW_ACCESS_INVALIDATE: - ret_val = qdma_cpm4_indirect_intr_context_invalidate( - dev_hndl, ring_index); - break; - default: - qdma_log_error("%s: access_type=%d is invalid, err:%d\n", - __func__, access_type, - -QDMA_ERR_INV_PARAM); - ret_val = -QDMA_ERR_INV_PARAM; - break; - } - - return ret_val; -} - -/*****************************************************************************/ -/** - * qdma_cpm4_set_default_global_csr() - function to set the global - * CSR register to default values. The value can be modified later by using - * the set/get csr functions - * - * @dev_hndl: device handle - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -int qdma_cpm4_set_default_global_csr(void *dev_hndl) -{ - /* Default values */ - uint32_t reg_val = 0; - uint32_t rng_sz[QDMA_NUM_RING_SIZES] = {2049, 65, 129, 193, 257, - 385, 513, 769, 1025, 1537, 3073, 4097, 6145, - 8193, 12289, 16385}; - uint32_t tmr_cnt[QDMA_NUM_C2H_TIMERS] = {1, 2, 4, 5, 8, 10, 15, 20, 25, - 30, 50, 75, 100, 125, 150, 200}; - uint32_t cnt_th[QDMA_NUM_C2H_COUNTERS] = {2, 4, 8, 16, 24, - 32, 48, 64, 80, 96, 112, 128, 144, - 160, 176, 192}; - uint32_t buf_sz[QDMA_NUM_C2H_BUFFER_SIZES] = {4096, 256, 512, 1024, - 2048, 3968, 4096, 4096, 4096, 4096, 4096, 4096, - 4096, 8192, 9018, 16384}; - struct qdma_dev_attributes dev_cap; - - if (!dev_hndl) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - qdma_cpm4_get_device_attributes(dev_hndl, &dev_cap); - - /* Configuring CSR registers */ - /* Global ring sizes */ - qdma_write_csr_values(dev_hndl, QDMA_CPM4_GLBL_RNG_SZ_1_ADDR, 0, - QDMA_NUM_RING_SIZES, rng_sz); - - if (dev_cap.st_en || dev_cap.mm_cmpt_en) { - /* Counter thresholds */ - qdma_write_csr_values(dev_hndl, - QDMA_CPM4_C2H_CNT_TH_1_ADDR, 0, - QDMA_NUM_C2H_COUNTERS, cnt_th); - - /* Timer Counters */ - qdma_write_csr_values(dev_hndl, - QDMA_CPM4_C2H_TIMER_CNT_1_ADDR, 0, - QDMA_NUM_C2H_TIMERS, tmr_cnt); - - - /* Writeback Interval */ - reg_val = - FIELD_SET(GLBL_DSC_CFG_MAXFETCH_MASK, - DEFAULT_MAX_DSC_FETCH) | - FIELD_SET(GLBL_DSC_CFG_WB_ACC_INT_MASK, - DEFAULT_WRB_INT); - qdma_reg_write(dev_hndl, - QDMA_CPM4_GLBL_DSC_CFG_ADDR, reg_val); - } - - if (dev_cap.st_en) { - /* Buffer Sizes */ - qdma_write_csr_values(dev_hndl, - QDMA_CPM4_C2H_BUF_SZ_0_ADDR, 0, - QDMA_NUM_C2H_BUFFER_SIZES, buf_sz); - - /* Prefetch Configuration */ - reg_val = - FIELD_SET(C2H_PFCH_CFG_FL_TH_MASK, - QDMA_CPM4_DEFAULT_PFCH_STOP_THRESH) | - FIELD_SET(C2H_PFCH_CFG_NUM_MASK, - DEFAULT_PFCH_NUM_ENTRIES_PER_Q) | - FIELD_SET(C2H_PFCH_CFG_QCNT_MASK, - DEFAULT_PFCH_MAX_Q_CNT) | - FIELD_SET(C2H_PFCH_CFG_EVT_QCNT_TH_MASK, - DEFAULT_C2H_INTR_TIMER_TICK); - qdma_reg_write(dev_hndl, - QDMA_CPM4_C2H_PFCH_CFG_ADDR, reg_val); - - /* C2H interrupt timer tick */ - qdma_reg_write(dev_hndl, QDMA_CPM4_C2H_INT_TIMER_TICK_ADDR, - DEFAULT_C2H_INTR_TIMER_TICK); - - /* C2h Completion Coalesce Configuration */ - reg_val = - FIELD_SET(C2H_WRB_COAL_CFG_TICK_CNT_MASK, - DEFAULT_CMPT_COAL_TIMER_CNT) | - FIELD_SET(C2H_WRB_COAL_CFG_TICK_VAL_MASK, - DEFAULT_CMPT_COAL_TIMER_TICK) | - FIELD_SET(C2H_WRB_COAL_CFG_MAX_BUF_SZ_MASK, - DEFAULT_CMPT_COAL_MAX_BUF_SZ); - qdma_reg_write(dev_hndl, - QDMA_CPM4_C2H_WRB_COAL_CFG_ADDR, reg_val); - -#if 0 - /* H2C throttle Configuration*/ - reg_val = - FIELD_SET(QDMA_H2C_DATA_THRESH_MASK, - DEFAULT_H2C_THROT_DATA_THRESH) | - FIELD_SET(QDMA_H2C_REQ_THROT_EN_DATA_MASK, - DEFAULT_THROT_EN_DATA); - qdma_reg_write(dev_hndl, QDMA_OFFSET_H2C_REQ_THROT, reg_val); -#endif - } - - return QDMA_SUCCESS; -} - -/*****************************************************************************/ -/** - * qdma_cpm4_queue_pidx_update() - function to update the desc PIDX - * - * @dev_hndl: device handle - * @is_vf: Whether PF or VF - * @qid: Queue id relative to the PF/VF calling this API - * @is_c2h: Queue direction. Set 1 for C2H and 0 for H2C - * @reg_info: data needed for the PIDX register update - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -int qdma_cpm4_queue_pidx_update(void *dev_hndl, uint8_t is_vf, uint16_t qid, - uint8_t is_c2h, const struct qdma_q_pidx_reg_info *reg_info) -{ - uint32_t reg_addr = 0; - uint32_t reg_val = 0; - - if (!dev_hndl) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - if (!reg_info) { - qdma_log_error("%s: reg_info is NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - if (!is_vf) { - reg_addr = (is_c2h) ? - QDMA_CPM4_OFFSET_DMAP_SEL_C2H_DSC_PIDX : - QDMA_CPM4_OFFSET_DMAP_SEL_H2C_DSC_PIDX; - } else { - reg_addr = (is_c2h) ? - QDMA_CPM4_OFFSET_VF_DMAP_SEL_C2H_DSC_PIDX : - QDMA_CPM4_OFFSET_VF_DMAP_SEL_H2C_DSC_PIDX; - } - - reg_addr += (qid * QDMA_PIDX_STEP); - - reg_val = FIELD_SET(QDMA_CPM4_DMA_SEL_DESC_PIDX_MASK, - reg_info->pidx) | - FIELD_SET(QDMA_CPM4_DMA_SEL_IRQ_EN_MASK, - reg_info->irq_en); - - qdma_reg_write(dev_hndl, reg_addr, reg_val); - - return QDMA_SUCCESS; -} - -/*****************************************************************************/ -/** - * qdma_cpm4_queue_cmpt_cidx_update() - function to update the CMPT - * CIDX update - * - * @dev_hndl: device handle - * @is_vf: Whether PF or VF - * @qid: Queue id relative to the PF/VF calling this API - * @reg_info: data needed for the CIDX register update - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -int qdma_cpm4_queue_cmpt_cidx_update(void *dev_hndl, uint8_t is_vf, - uint16_t qid, const struct qdma_q_cmpt_cidx_reg_info *reg_info) -{ - uint32_t reg_addr = (is_vf) ? - QDMA_CPM4_OFFSET_VF_DMAP_SEL_CMPT_CIDX : - QDMA_CPM4_OFFSET_DMAP_SEL_CMPT_CIDX; - uint32_t reg_val = 0; - - if (!dev_hndl) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - if (!reg_info) { - qdma_log_error("%s: reg_info is NULL, err:%d\n", - __func__, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - reg_addr += (qid * QDMA_CMPT_CIDX_STEP); - - reg_val = - FIELD_SET(QDMA_CPM4_DMAP_SEL_CMPT_WRB_CIDX_MASK, - reg_info->wrb_cidx) | - FIELD_SET(QDMA_CPM4_DMAP_SEL_CMPT_CNT_THRESH_MASK, - reg_info->counter_idx) | - FIELD_SET(QDMA_CPM4_DMAP_SEL_CMPT_TMR_CNT_MASK, - reg_info->timer_idx) | - FIELD_SET(QDMA_CPM4_DMAP_SEL_CMPT_TRG_MODE_MASK, - reg_info->trig_mode) | - FIELD_SET(QDMA_CPM4_DMAP_SEL_CMPT_STS_DESC_EN_MASK, - reg_info->wrb_en) | - FIELD_SET(QDMA_CPM4_DMAP_SEL_CMPT_IRQ_EN_MASK, - reg_info->irq_en); - - qdma_reg_write(dev_hndl, reg_addr, reg_val); - - return QDMA_SUCCESS; -} - -/*****************************************************************************/ -/** - * qdma_cpm4_queue_intr_cidx_update() - function to update the - * CMPT CIDX update - * - * @dev_hndl: device handle - * @is_vf: Whether PF or VF - * @qid: Queue id relative to the PF/VF calling this API - * @reg_info: data needed for the CIDX register update - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -int qdma_cpm4_queue_intr_cidx_update(void *dev_hndl, uint8_t is_vf, - uint16_t qid, const struct qdma_intr_cidx_reg_info *reg_info) -{ - uint32_t reg_addr = (is_vf) ? - QDMA_CPM4_OFFSET_VF_DMAP_SEL_INT_CIDX : - QDMA_CPM4_OFFSET_DMAP_SEL_INT_CIDX; - uint32_t reg_val = 0; - - if (!dev_hndl) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - if (!reg_info) { - qdma_log_error("%s: reg_info is NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - reg_addr += qid * QDMA_INT_CIDX_STEP; - - reg_val = - FIELD_SET(QDMA_CPM4_DMA_SEL_INT_SW_CIDX_MASK, - reg_info->sw_cidx) | - FIELD_SET(QDMA_CPM4_DMA_SEL_INT_RING_IDX_MASK, - reg_info->rng_idx); - - qdma_reg_write(dev_hndl, reg_addr, reg_val); - - return QDMA_SUCCESS; -} - -/*****************************************************************************/ -/** - * qdma_cmp_get_user_bar() - Function to get the - * AXI Master Lite(user bar) number - * @dev_hndl: device handle - * @is_vf: Whether PF or VF - * @func_id: function id of the PF - * @user_bar: pointer to hold the AXI Master Lite(user bar) number - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -int qdma_cmp_get_user_bar(void *dev_hndl, uint8_t is_vf, - uint16_t func_id, uint8_t *user_bar) -{ - uint8_t bar_found = 0; - uint8_t bar_idx = 0; - uint32_t user_bar_id = 0; - uint32_t reg_addr = 0; - - if (!dev_hndl) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - if (!user_bar) { - qdma_log_error("%s: user_bar is NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - reg_addr = (is_vf) ? QDMA_CPM4_GLBL2_PF_VF_BARLITE_EXT_ADDR : - QDMA_CPM4_GLBL2_PF_BARLITE_EXT_ADDR; - - if (!is_vf) { - user_bar_id = qdma_reg_read(dev_hndl, reg_addr); - user_bar_id = (user_bar_id >> (6 * func_id)) & 0x3F; - } else { - *user_bar = QDMA_CPM4_VF_USER_BAR_ID; - return QDMA_SUCCESS; - } - - for (bar_idx = 0; bar_idx < QDMA_BAR_NUM; bar_idx++) { - if (user_bar_id & (1 << bar_idx)) { - *user_bar = bar_idx; - bar_found = 1; - break; - } - } - if (bar_found == 0) { - *user_bar = 0; - qdma_log_error("%s: Bar not found, err:%d\n", - __func__, - -QDMA_ERR_HWACC_BAR_NOT_FOUND); - return -QDMA_ERR_HWACC_BAR_NOT_FOUND; - } - - return QDMA_SUCCESS; -} - -/*****************************************************************************/ -/** - * qdma_cpm4_hw_ram_sbe_err_process() -Function to dump SBE err debug info - * - * @dev_hndl: device handle - * @buf: Bufffer for the debug info to be dumped in - * @buflen: Length of the buffer - * - * Return: void - *****************************************************************************/ -static void qdma_cpm4_hw_ram_sbe_err_process(void *dev_hndl) -{ - qdma_cpm4_dump_reg_info(dev_hndl, QDMA_CPM4_RAM_SBE_STS_A_ADDR, - 1, NULL, 0); -} - -/*****************************************************************************/ -/** - * qdma_cpm4_hw_ram_dbe_err_process() -Function to dump DBE err debug info - * - * @dev_hndl: device handle - * @buf: Bufffer for the debug info to be dumped in - * @buflen: Length of the buffer - * - * Return: void - *****************************************************************************/ -static void qdma_cpm4_hw_ram_dbe_err_process(void *dev_hndl) -{ - qdma_cpm4_dump_reg_info(dev_hndl, QDMA_CPM4_RAM_DBE_STS_A_ADDR, - 1, NULL, 0); -} - -/*****************************************************************************/ -/** - * qdma_cpm4_hw_desc_err_process() -Function to dump Descriptor Error info - * - * @dev_hndl: device handle - * @buf: Bufffer for the debug info to be dumped in - * @buflen: Length of the buffer - * - * Return: void - *****************************************************************************/ -static void qdma_cpm4_hw_desc_err_process(void *dev_hndl) -{ - int i = 0; - uint32_t desc_err_reg_list[] = { - QDMA_CPM4_GLBL_DSC_ERR_STS_ADDR, - QDMA_CPM4_GLBL_DSC_ERR_LOG0_ADDR, - QDMA_CPM4_GLBL_DSC_ERR_LOG1_ADDR, - QDMA_CPM4_GLBL_DSC_DBG_DAT0_ADDR, - QDMA_CPM4_GLBL_DSC_DBG_DAT1_ADDR - }; - int desc_err_num_regs = sizeof(desc_err_reg_list)/sizeof(uint32_t); - - for (i = 0; i < desc_err_num_regs; i++) { - qdma_cpm4_dump_reg_info(dev_hndl, - desc_err_reg_list[i], - 1, NULL, 0); - } -} - -/*****************************************************************************/ -/** - * qdma_cpm4_hw_trq_err_process() -Function to dump Target Access Err info - * - * @dev_hndl: device handle - * @buf: Bufffer for the debug info to be dumped in - * @buflen: Length of the buffer - * - * Return: void - *****************************************************************************/ -static void qdma_cpm4_hw_trq_err_process(void *dev_hndl) -{ - int i = 0; - uint32_t trq_err_reg_list[] = { - QDMA_CPM4_GLBL_TRQ_ERR_STS_ADDR, - QDMA_CPM4_GLBL_TRQ_ERR_LOG_ADDR - }; - int trq_err_reg_num_regs = sizeof(trq_err_reg_list)/sizeof(uint32_t); - - for (i = 0; i < trq_err_reg_num_regs; i++) { - qdma_cpm4_dump_reg_info(dev_hndl, trq_err_reg_list[i], - 1, NULL, 0); - } - - -} - -/*****************************************************************************/ -/** - * qdma_cpm4_hw_st_h2c_err_process() - Function to dump MM H2C Error info - * - * @dev_hndl: device handle - * @buf: Bufffer for the debug info to be dumped in - * @buflen: Length of the buffer - * - * Return: void - *****************************************************************************/ -static void qdma_cpm4_hw_st_h2c_err_process(void *dev_hndl) -{ - int i = 0; - uint32_t st_h2c_err_reg_list[] = { - QDMA_CPM4_H2C_ERR_STAT_ADDR, - QDMA_CPM4_H2C_FIRST_ERR_QID_ADDR, - QDMA_CPM4_H2C_DBG_REG0_ADDR, - QDMA_CPM4_H2C_DBG_REG1_ADDR, - QDMA_CPM4_H2C_DBG_REG2_ADDR, - QDMA_CPM4_H2C_DBG_REG3_ADDR, - QDMA_CPM4_H2C_DBG_REG4_ADDR - }; - int st_h2c_err_num_regs = sizeof(st_h2c_err_reg_list)/sizeof(uint32_t); - - for (i = 0; i < st_h2c_err_num_regs; i++) { - qdma_cpm4_dump_reg_info(dev_hndl, - st_h2c_err_reg_list[i], - 1, NULL, 0); - } -} - - -/*****************************************************************************/ -/** - * qdma_cpm4_hw_st_c2h_err_process() - Function to dump MM H2C Error info - * - * @dev_hndl: device handle - * @buf: Bufffer for the debug info to be dumped in - * @buflen: Length of the buffer - * - * Return: void - *****************************************************************************/ -static void qdma_cpm4_hw_st_c2h_err_process(void *dev_hndl) -{ - int i = 0; - uint32_t st_c2h_err_reg_list[] = { - QDMA_CPM4_C2H_ERR_STAT_ADDR, - QDMA_CPM4_C2H_FATAL_ERR_STAT_ADDR, - QDMA_CPM4_C2H_FIRST_ERR_QID_ADDR, - QDMA_CPM4_C2H_STAT_S_AXIS_C2H_ACCEPTED_ADDR, - QDMA_CPM4_C2H_STAT_S_AXIS_WRB_ACCEPTED_ADDR, - QDMA_CPM4_C2H_STAT_DESC_RSP_PKT_ACCEPTED_ADDR, - QDMA_CPM4_C2H_STAT_AXIS_PKG_CMP_ADDR, - QDMA_CPM4_C2H_STAT_DBG_DMA_ENG_0_ADDR, - QDMA_CPM4_C2H_STAT_DBG_DMA_ENG_1_ADDR, - QDMA_CPM4_C2H_STAT_DBG_DMA_ENG_2_ADDR, - QDMA_CPM4_C2H_STAT_DBG_DMA_ENG_3_ADDR, - QDMA_CPM4_C2H_STAT_DESC_RSP_DROP_ACCEPTED_ADDR, - QDMA_CPM4_C2H_STAT_DESC_RSP_ERR_ACCEPTED_ADDR - }; - int st_c2h_err_num_regs = sizeof(st_c2h_err_reg_list)/sizeof(uint32_t); - - for (i = 0; i < st_c2h_err_num_regs; i++) { - qdma_cpm4_dump_reg_info(dev_hndl, - st_c2h_err_reg_list[i], - 1, NULL, 0); - } -} - - - -/*****************************************************************************/ -/** - * qdma_cpm4_hw_get_error_name() - Function to get the error in str format - * - * @err_idx: error index - * - * Return: string - success and NULL on failure - *****************************************************************************/ -const char *qdma_cpm4_hw_get_error_name(uint32_t err_idx) -{ - if (err_idx >= QDMA_CPM4_ERRS_ALL) { - qdma_log_error("%s: err_idx=%d is invalid, returning NULL\n", - __func__, - (enum qdma_cpm4_error_idx)err_idx); - return NULL; - } - - return qdma_cpm4_err_info[ - (enum qdma_cpm4_error_idx)err_idx].err_name; -} - -/*****************************************************************************/ -/** - * qdma_cpm4_hw_error_process() - Function to find the error that got - * triggered and call the handler qdma_hw_error_handler of that - * particular error. - * - * @dev_hndl: device handle - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -int qdma_cpm4_hw_error_process(void *dev_hndl) -{ - uint32_t glbl_err_stat = 0, err_stat = 0; - uint32_t i = 0, j = 0; - int32_t idx = 0; - struct qdma_dev_attributes dev_cap; - uint32_t hw_err_position[QDMA_CPM4_TOTAL_LEAF_ERROR_AGGREGATORS] = { - QDMA_CPM4_DSC_ERR_POISON, - QDMA_CPM4_TRQ_ERR_UNMAPPED, - QDMA_CPM4_ST_C2H_ERR_MTY_MISMATCH, - QDMA_CPM4_ST_FATAL_ERR_MTY_MISMATCH, - QDMA_CPM4_ST_H2C_ERR_ZERO_LEN_DESC_ERR, - QDMA_CPM4_SBE_ERR_MI_H2C0_DAT, - QDMA_CPM4_DBE_ERR_MI_H2C0_DAT - }; - - if (!dev_hndl) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - - qdma_cpm4_get_device_attributes(dev_hndl, &dev_cap); - - glbl_err_stat = qdma_reg_read(dev_hndl, - QDMA_CPM4_GLBL_ERR_STAT_ADDR); - if (!glbl_err_stat) - return QDMA_HW_ERR_NOT_DETECTED; - - qdma_log_info("%s: Global Err Reg(0x%x) = 0x%x\n", - __func__, QDMA_CPM4_GLBL_ERR_STAT_ADDR, - glbl_err_stat); - - for (i = 0; i < QDMA_CPM4_TOTAL_LEAF_ERROR_AGGREGATORS; i++) { - j = hw_err_position[i]; - - if ((!dev_cap.st_en) && - (j == QDMA_CPM4_ST_C2H_ERR_MTY_MISMATCH || - j == QDMA_CPM4_ST_FATAL_ERR_MTY_MISMATCH || - j == QDMA_CPM4_ST_H2C_ERR_ZERO_LEN_DESC_ERR)) - continue; - - err_stat = qdma_reg_read(dev_hndl, - qdma_cpm4_err_info[j].stat_reg_addr); - if (err_stat) { - qdma_log_info("addr = 0x%08x val = 0x%08x", - qdma_cpm4_err_info[j].stat_reg_addr, - err_stat); - - qdma_cpm4_err_info[j].qdma_cpm4_hw_err_process( - dev_hndl); - for (idx = j; - idx < all_qdma_cpm4_hw_errs[i]; - idx++) { - /* call the platform specific handler */ - if (err_stat & - qdma_cpm4_err_info[idx].leaf_err_mask) - qdma_log_error("%s detected %s\n", - __func__, - qdma_cpm4_hw_get_error_name( - idx)); - } - qdma_reg_write(dev_hndl, - qdma_cpm4_err_info[j].stat_reg_addr, - err_stat); - } - - } - - /* Write 1 to the global status register to clear the bits */ - qdma_reg_write(dev_hndl, - QDMA_CPM4_GLBL_ERR_STAT_ADDR, glbl_err_stat); - - return QDMA_SUCCESS; -} - -/*****************************************************************************/ -/** - * qdma_hw_error_enable() - Function to enable all or a specific error - * - * @dev_hndl: device handle - * @err_idx: error index - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -int qdma_cpm4_hw_error_enable(void *dev_hndl, uint32_t err_idx) -{ - uint32_t idx = 0, i = 0; - uint32_t reg_val = 0; - struct qdma_dev_attributes dev_cap; - - if (!dev_hndl) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - if (err_idx > QDMA_CPM4_ERRS_ALL) { - qdma_log_error("%s: err_idx=%d is invalid, err:%d\n", - __func__, (enum qdma_cpm4_error_idx)err_idx, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - qdma_cpm4_get_device_attributes(dev_hndl, &dev_cap); - - if (err_idx == QDMA_CPM4_ERRS_ALL) { - for (i = 0; - i < QDMA_CPM4_TOTAL_LEAF_ERROR_AGGREGATORS; - i++) { - - idx = all_qdma_cpm4_hw_errs[i]; - - /* Don't access streaming registers in - * MM only bitstreams - */ - if (!dev_cap.st_en) { - if (idx == QDMA_CPM4_ST_C2H_ERR_ALL || - idx == QDMA_CPM4_ST_FATAL_ERR_ALL || - idx == QDMA_CPM4_ST_H2C_ERR_ALL) - continue; - } - - reg_val = qdma_cpm4_err_info[idx].leaf_err_mask; - qdma_reg_write(dev_hndl, - qdma_cpm4_err_info[idx].mask_reg_addr, - reg_val); - - reg_val = qdma_reg_read(dev_hndl, - QDMA_CPM4_GLBL_ERR_MASK_ADDR); - reg_val |= FIELD_SET( - qdma_cpm4_err_info[idx].global_err_mask, 1); - qdma_reg_write(dev_hndl, - QDMA_CPM4_GLBL_ERR_MASK_ADDR, - reg_val); - } - - } else { - /* Don't access streaming registers in MM only bitstreams - * QDMA_C2H_ERR_MTY_MISMATCH to QDMA_H2C_ERR_ALL are all - * ST errors - */ - if (!dev_cap.st_en) { - if (err_idx >= QDMA_CPM4_ST_C2H_ERR_MTY_MISMATCH && - err_idx <= QDMA_CPM4_ST_H2C_ERR_ALL) - return QDMA_SUCCESS; - } - - reg_val = qdma_reg_read(dev_hndl, - qdma_cpm4_err_info[err_idx].mask_reg_addr); - reg_val |= - FIELD_SET(qdma_cpm4_err_info[err_idx].leaf_err_mask, - 1); - qdma_reg_write(dev_hndl, - qdma_cpm4_err_info[err_idx].mask_reg_addr, - reg_val); - - reg_val = qdma_reg_read(dev_hndl, - QDMA_CPM4_GLBL_ERR_MASK_ADDR); - reg_val |= - FIELD_SET( - qdma_cpm4_err_info[err_idx].global_err_mask, - 1); - qdma_reg_write(dev_hndl, - QDMA_CPM4_GLBL_ERR_MASK_ADDR, reg_val); - } - - return QDMA_SUCCESS; -} - -/*****************************************************************************/ -/** - * qdma_cpm4_get_device_attributes() - Function to get the qdma - * device attributes - * - * @dev_hndl: device handle - * @dev_info: pointer to hold the device info - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -int qdma_cpm4_get_device_attributes(void *dev_hndl, - struct qdma_dev_attributes *dev_info) -{ - uint8_t count = 0; - uint32_t reg_val = 0; - - if (!dev_hndl) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - if (!dev_info) { - qdma_log_error("%s: dev_info is NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - /* number of PFs */ - reg_val = qdma_reg_read(dev_hndl, - QDMA_CPM4_GLBL2_PF_BARLITE_INT_ADDR); - if (FIELD_GET(GLBL2_PF_BARLITE_INT_PF0_BAR_MAP_MASK, reg_val)) - count++; - if (FIELD_GET(GLBL2_PF_BARLITE_INT_PF1_BAR_MAP_MASK, reg_val)) - count++; - if (FIELD_GET(GLBL2_PF_BARLITE_INT_PF2_BAR_MAP_MASK, reg_val)) - count++; - if (FIELD_GET(GLBL2_PF_BARLITE_INT_PF3_BAR_MAP_MASK, reg_val)) - count++; - dev_info->num_pfs = count; - - /* Number of Qs */ - reg_val = qdma_reg_read(dev_hndl, QDMA_CPM4_GLBL2_CHANNEL_CAP_ADDR); - dev_info->num_qs = (FIELD_GET(GLBL2_CHANNEL_CAP_MULTIQ_MAX_MASK, - reg_val)); - - /* FLR present */ - reg_val = qdma_reg_read(dev_hndl, QDMA_CPM4_GLBL2_MISC_CAP_ADDR); - dev_info->mailbox_en = FIELD_GET(QDMA_GLBL2_MAILBOX_EN_MASK, reg_val); - dev_info->flr_present = FIELD_GET(QDMA_GLBL2_FLR_PRESENT_MASK, reg_val); - dev_info->mm_cmpt_en = 0; - - /* ST/MM enabled? */ - reg_val = qdma_reg_read(dev_hndl, - QDMA_CPM4_GLBL2_CHANNEL_MDMA_ADDR); - dev_info->mm_en = (FIELD_GET(GLBL2_CHANNEL_MDMA_C2H_ENG_MASK, reg_val) - && FIELD_GET(GLBL2_CHANNEL_MDMA_H2C_ENG_MASK, reg_val)) ? 1 : 0; - dev_info->st_en = (FIELD_GET(GLBL2_CHANNEL_MDMA_C2H_ST_MASK, reg_val) - && FIELD_GET(GLBL2_CHANNEL_MDMA_H2C_ST_MASK, - reg_val)) ? 1 : 0; - - /* num of mm channels for Versal Hard is 2 */ - dev_info->mm_channel_max = 2; - - dev_info->debug_mode = 0; - dev_info->desc_eng_mode = 0; - dev_info->qid2vec_ctx = 1; - dev_info->cmpt_ovf_chk_dis = 0; - dev_info->mailbox_intr = 0; - dev_info->sw_desc_64b = 0; - dev_info->cmpt_desc_64b = 0; - dev_info->dynamic_bar = 0; - dev_info->legacy_intr = 0; - dev_info->cmpt_trig_count_timer = 0; - - return QDMA_SUCCESS; -} - - -/*****************************************************************************/ -/** - * qdma_cpm4_credit_context_read() - read credit context - * - * @dev_hndl: device handle - * @c2h : is c2h queue - * @hw_qid : hardware qid of the queue - * @ctxt : pointer to the context data - * - * Return : 0 - success and < 0 - failure - *****************************************************************************/ -static int qdma_cpm4_credit_context_read(void *dev_hndl, uint8_t c2h, - uint16_t hw_qid, - struct qdma_descq_credit_ctxt *ctxt) -{ - int rv = QDMA_SUCCESS; - uint32_t cr_ctxt[QDMA_CPM4_CR_CONTEXT_NUM_WORDS] = {0}; - enum ind_ctxt_cmd_sel sel = c2h ? QDMA_CTXT_SEL_CR_C2H : - QDMA_CTXT_SEL_CR_H2C; - - if (!dev_hndl || !ctxt) { - qdma_log_error("%s: dev_hndl=%p credit_ctxt=%p, err:%d\n", - __func__, dev_hndl, ctxt, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - rv = qdma_cpm4_indirect_reg_read(dev_hndl, sel, hw_qid, - QDMA_CPM4_CR_CONTEXT_NUM_WORDS, cr_ctxt); - if (rv < 0) - return rv; - - ctxt->credit = FIELD_GET(CRED_CTXT_DATA_W0_CREDT_MASK, - cr_ctxt[0]); - - qdma_log_debug("%s: credit=%u\n", __func__, ctxt->credit); - - return QDMA_SUCCESS; -} - -/*****************************************************************************/ -/** - * qdma_cpm4_credit_context_clear() - clear credit context - * - * @dev_hndl: device handle - * @c2h : is c2h queue - * @hw_qid : hardware qid of the queue - * - * Return : 0 - success and < 0 - failure - *****************************************************************************/ -static int qdma_cpm4_credit_context_clear(void *dev_hndl, uint8_t c2h, - uint16_t hw_qid) -{ - enum ind_ctxt_cmd_sel sel = c2h ? QDMA_CTXT_SEL_CR_C2H : - QDMA_CTXT_SEL_CR_H2C; - - if (!dev_hndl) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", __func__, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - return qdma_cpm4_indirect_reg_clear(dev_hndl, sel, hw_qid); -} - -/*****************************************************************************/ -/** - * qdma_cpm4_credit_context_invalidate() - invalidate credit context - * - * @dev_hndl: device handle - * @c2h : is c2h queue - * @hw_qid : hardware qid of the queue - * - * Return : 0 - success and < 0 - failure - *****************************************************************************/ -static int qdma_cpm4_credit_context_invalidate(void *dev_hndl, uint8_t c2h, - uint16_t hw_qid) -{ - enum ind_ctxt_cmd_sel sel = c2h ? QDMA_CTXT_SEL_CR_C2H : - QDMA_CTXT_SEL_CR_H2C; - - if (!dev_hndl) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", __func__, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - return qdma_cpm4_indirect_reg_invalidate(dev_hndl, sel, hw_qid); -} - -/*****************************************************************************/ -/** - * qdma_cpm4_credit_ctx_conf() - configure credit context - * - * @dev_hndl : device handle - * @c2h : is c2h queue - * @hw_qid : hardware qid of the queue - * @ctxt : pointer to the context data - * @access_type : HW access type (qdma_hw_access_type enum) value - * QDMA_HW_ACCESS_WRITE Not supported - * - * Return : 0 - success and < 0 - failure - *****************************************************************************/ -int qdma_cpm4_credit_ctx_conf(void *dev_hndl, uint8_t c2h, uint16_t hw_qid, - struct qdma_descq_credit_ctxt *ctxt, - enum qdma_hw_access_type access_type) -{ - int rv = QDMA_SUCCESS; - - switch (access_type) { - case QDMA_HW_ACCESS_READ: - rv = qdma_cpm4_credit_context_read(dev_hndl, c2h, - hw_qid, ctxt); - break; - case QDMA_HW_ACCESS_CLEAR: - rv = qdma_cpm4_credit_context_clear(dev_hndl, c2h, hw_qid); - break; - case QDMA_HW_ACCESS_INVALIDATE: - rv = qdma_cpm4_credit_context_invalidate(dev_hndl, c2h, - hw_qid); - break; - case QDMA_HW_ACCESS_WRITE: - default: - qdma_log_error("%s: Invalid access type=%d, err:%d\n", - __func__, access_type, - -QDMA_ERR_INV_PARAM); - rv = -QDMA_ERR_INV_PARAM; - break; - } - - return rv; -} - - -/*****************************************************************************/ -/** - * qdma_cpm4_dump_config_regs() - Function to get qdma config register - * dump in a buffer - * - * @dev_hndl: device handle - * @is_vf: Whether PF or VF - * @buf : pointer to buffer to be filled - * @buflen : Length of the buffer - * - * Return: Length up-till the buffer is filled -success and < 0 - failure - *****************************************************************************/ -int qdma_cpm4_dump_config_regs(void *dev_hndl, uint8_t is_vf, - char *buf, uint32_t buflen) -{ - uint32_t i = 0, j = 0; - struct xreg_info *reg_info; - uint32_t num_regs = qdma_cpm4_config_num_regs_get(); - uint32_t len = 0, val = 0; - int rv = QDMA_SUCCESS; - char name[DEBGFS_GEN_NAME_SZ] = ""; - struct qdma_dev_attributes dev_cap; - - if (!dev_hndl) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - if (buflen < qdma_cpm4_reg_dump_buf_len()) { - qdma_log_error("%s: Buffer too small, err:%d\n", __func__, - -QDMA_ERR_NO_MEM); - return -QDMA_ERR_NO_MEM; - } - - if (is_vf) { - qdma_log_error("%s: Wrong API used for VF, err:%d\n", - __func__, - -QDMA_ERR_HWACC_FEATURE_NOT_SUPPORTED); - return -QDMA_ERR_HWACC_FEATURE_NOT_SUPPORTED; - } - - qdma_cpm4_get_device_attributes(dev_hndl, &dev_cap); - - reg_info = qdma_cpm4_config_regs_get(); - - for (i = 0; i < num_regs; i++) { - if ((GET_CAPABILITY_MASK(dev_cap.mm_en, dev_cap.st_en, - dev_cap.mm_cmpt_en, dev_cap.mailbox_en) - & reg_info[i].mode) == 0) - continue; - - for (j = 0; j < reg_info[i].repeat; j++) { - rv = QDMA_SNPRINTF_S(name, DEBGFS_GEN_NAME_SZ, - DEBGFS_GEN_NAME_SZ, - "%s_%d", reg_info[i].name, j); - if ((rv < 0) || (rv > DEBGFS_GEN_NAME_SZ)) { - qdma_log_error( - "%d:%s QDMA_SNPRINTF_S() failed, err:%d\n", - __LINE__, __func__, - rv); - return -QDMA_ERR_NO_MEM; - } - - val = qdma_reg_read(dev_hndl, - (reg_info[i].addr + (j * 4))); - rv = dump_reg(buf + len, buflen - len, - (reg_info[i].addr + (j * 4)), - name, val); - if (rv < 0) { - qdma_log_error( - "%s Buff too small, err:%d\n", - __func__, - -QDMA_ERR_NO_MEM); - return -QDMA_ERR_NO_MEM; - } - len += rv; - } - } - - return len; -} - -/*****************************************************************************/ -/** - * qdma_dump_cpm4_queue_context() - Function to get qdma queue context dump - * in a buffer - * - * @dev_hndl: device handle - * @hw_qid: queue id - * @buf : pointer to buffer to be filled - * @buflen : Length of the buffer - * - * Return: Length up-till the buffer is filled -success and < 0 - failure - *****************************************************************************/ -int qdma_cpm4_dump_queue_context(void *dev_hndl, - uint8_t st, - enum qdma_dev_q_type q_type, - struct qdma_descq_context *ctxt_data, - char *buf, uint32_t buflen) -{ - int rv = 0; - uint32_t req_buflen = 0; - - if (!dev_hndl) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - - return -QDMA_ERR_INV_PARAM; - } - - if (!ctxt_data) { - qdma_log_error("%s: ctxt_data is NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - - return -QDMA_ERR_INV_PARAM; - } - - if (!buf) { - qdma_log_error("%s: buf is NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - - return -QDMA_ERR_INV_PARAM; - } - if (q_type >= QDMA_DEV_Q_TYPE_MAX) { - qdma_log_error("%s: invalid q_type, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - - return -QDMA_ERR_INV_PARAM; - } - - rv = qdma_cpm4_context_buf_len(st, q_type, &req_buflen); - if (rv != QDMA_SUCCESS) - return rv; - - if (buflen < req_buflen) { - qdma_log_error("%s: Too small buffer(%d), reqd(%d), err:%d\n", - __func__, buflen, req_buflen, -QDMA_ERR_NO_MEM); - return -QDMA_ERR_NO_MEM; - } - - rv = dump_cpm4_context(ctxt_data, st, q_type, - buf, buflen); - - return rv; -} - -/*****************************************************************************/ -/** - * qdma_dump_cpm4_intr_context() - Function to get qdma interrupt - * context dump in a buffer - * - * @dev_hndl: device handle - * @hw_qid: queue id - * @buf : pointer to buffer to be filled - * @buflen : Length of the buffer - * - * Return: Length up-till the buffer is filled -success and < 0 - failure - *****************************************************************************/ -int qdma_cpm4_dump_intr_context(void *dev_hndl, - struct qdma_indirect_intr_ctxt *intr_ctx, - int ring_index, - char *buf, uint32_t buflen) -{ - int rv = 0; - uint32_t req_buflen = 0; - - if (!dev_hndl) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - - return -QDMA_ERR_INV_PARAM; - } - - if (!intr_ctx) { - qdma_log_error("%s: intr_ctx is NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - - return -QDMA_ERR_INV_PARAM; - } - - if (!buf) { - qdma_log_error("%s: buf is NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - req_buflen = qdma_cpm4_intr_context_buf_len(); - if (buflen < req_buflen) { - qdma_log_error("%s: Too small buffer(%d), reqd(%d), err:%d\n", - __func__, buflen, req_buflen, -QDMA_ERR_NO_MEM); - return -QDMA_ERR_NO_MEM; - } - - rv = dump_cpm4_intr_context(intr_ctx, ring_index, buf, buflen); - - return rv; -} - -/*****************************************************************************/ -/** - * qdma_cpm4_read_dump_queue_context() - Function to read and dump the queue - * context in a buffer - * - * @dev_hndl: device handle - * @func_id: function id - * @hw_qid: queue id - * @st: Queue Mode(ST or MM) - * @q_type: Queue type(H2C/C2H/CMPT) - * @buf : pointer to buffer to be filled - * @buflen : Length of the buffer - * - * Return: Length up-till the buffer is filled -success and < 0 - failure - *****************************************************************************/ -int qdma_cpm4_read_dump_queue_context(void *dev_hndl, - uint16_t func_id, - uint16_t qid_hw, - uint8_t st, - enum qdma_dev_q_type q_type, - char *buf, uint32_t buflen) -{ - int rv = QDMA_SUCCESS; - uint32_t req_buflen = 0; - struct qdma_descq_context context; - - if (!dev_hndl) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - - return -QDMA_ERR_INV_PARAM; - } - - if (!buf) { - qdma_log_error("%s: buf is NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - - return -QDMA_ERR_INV_PARAM; - } - - if (q_type >= QDMA_DEV_Q_TYPE_CMPT) { - qdma_log_error("%s: Not supported for q_type, err = %d\n", - __func__, -QDMA_ERR_INV_PARAM); - - return -QDMA_ERR_INV_PARAM; - } - - rv = qdma_cpm4_context_buf_len(st, q_type, &req_buflen); - - if (rv != QDMA_SUCCESS) - return rv; - - if (buflen < req_buflen) { - qdma_log_error("%s: Too small buffer(%d), reqd(%d), err:%d\n", - __func__, buflen, req_buflen, -QDMA_ERR_NO_MEM); - return -QDMA_ERR_NO_MEM; - } - - qdma_memset(&context, 0, sizeof(struct qdma_descq_context)); - - if (q_type != QDMA_DEV_Q_TYPE_CMPT) { - rv = qdma_cpm4_sw_ctx_conf(dev_hndl, (uint8_t)q_type, - qid_hw, &(context.sw_ctxt), - QDMA_HW_ACCESS_READ); - if (rv < 0) { - qdma_log_error( - "%s: Failed to read sw context, err = %d", - __func__, rv); - return rv; - } - - rv = qdma_cpm4_hw_ctx_conf(dev_hndl, (uint8_t)q_type, - qid_hw, &(context.hw_ctxt), - QDMA_HW_ACCESS_READ); - if (rv < 0) { - qdma_log_error( - "%s: Failed to read hw context, err = %d", - __func__, rv); - return rv; - } - - rv = qdma_cpm4_qid2vec_conf(dev_hndl, (uint8_t)q_type, - qid_hw, &(context.qid2vec), - QDMA_HW_ACCESS_READ); - if (rv < 0) { - qdma_log_error( - "%s: Failed to read qid2vec context, err = %d", - __func__, rv); - return rv; - } - - rv = qdma_cpm4_credit_ctx_conf(dev_hndl, (uint8_t)q_type, - qid_hw, &(context.cr_ctxt), - QDMA_HW_ACCESS_READ); - if (rv < 0) { - qdma_log_error( - "%s: Failed to read credit context, err = %d", - __func__, rv); - return rv; - } - - if (st && (q_type == QDMA_DEV_Q_TYPE_C2H)) { - rv = qdma_cpm4_pfetch_ctx_conf(dev_hndl, - qid_hw, - &(context.pfetch_ctxt), - QDMA_HW_ACCESS_READ); - if (rv < 0) { - qdma_log_error( - "%s: Failed to read pftech context, err = %d", - __func__, rv); - return rv; - } - } - } - - if ((st && (q_type == QDMA_DEV_Q_TYPE_C2H)) || - (!st && (q_type == QDMA_DEV_Q_TYPE_CMPT))) { - rv = qdma_cpm4_cmpt_ctx_conf(dev_hndl, qid_hw, - &(context.cmpt_ctxt), - QDMA_HW_ACCESS_READ); - if (rv < 0) { - qdma_log_error( - "%s: Failed to read cmpt context, err = %d", - __func__, rv); - return rv; - } - } - - rv = qdma_cpm4_fmap_conf(dev_hndl, func_id, - &(context.fmap), QDMA_HW_ACCESS_READ); - if (rv < 0) { - qdma_log_error( - "%s: Failed to read fmap context, err = %d", - __func__, rv); - return rv; - } - - rv = dump_cpm4_context(&context, st, q_type, - buf, buflen); - - return rv; -} - -/*****************************************************************************/ -/** - * qdma_cpm4_init_ctxt_memory() - Initialize the context for all queues - * - * @dev_hndl : device handle - * - * Return : 0 - success and < 0 - failure - *****************************************************************************/ - -int qdma_cpm4_init_ctxt_memory(void *dev_hndl) -{ -#ifdef ENABLE_INIT_CTXT_MEMORY - uint32_t data[QDMA_REG_IND_CTXT_REG_COUNT]; - uint16_t i = 0; - struct qdma_dev_attributes dev_info; - - if (!dev_hndl) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - qdma_memset(data, 0, sizeof(uint32_t) * QDMA_REG_IND_CTXT_REG_COUNT); - qdma_cpm4_get_device_attributes(dev_hndl, &dev_info); - qdma_log_info("%s: clearing the context for all qs", - __func__); - for (; i < dev_info.num_qs; i++) { - int sel = QDMA_CTXT_SEL_SW_C2H; - int rv; - - -#ifdef TANDEM_BOOT_SUPPORTED - for (; sel <= QDMA_CTXT_SEL_CR_H2C; sel++) { - rv = qdma_cpm4_indirect_reg_clear(dev_hndl, - (enum ind_ctxt_cmd_sel)sel, i); - if (rv < 0) - return rv; - } -#else - for (; sel <= QDMA_CTXT_SEL_PFTCH; sel++) { - /** if the st mode(h2c/c2h) not enabled - * in the design, then skip the PFTCH - * and CMPT context setup - */ - if ((dev_info.st_en == 0) && - (sel == QDMA_CTXT_SEL_PFTCH || - sel == QDMA_CTXT_SEL_CMPT)) { - qdma_log_debug("%s: ST context is skipped:", - __func__); - qdma_log_debug(" sel = %d", sel); - continue; - } - - rv = qdma_cpm4_indirect_reg_clear(dev_hndl, - (enum ind_ctxt_cmd_sel)sel, i); - if (rv < 0) - return rv; - } -#endif - } - - /* fmap */ - for (i = 0; i < dev_info.num_pfs; i++) - qdma_cpm4_fmap_clear(dev_hndl, i); -#else - if (!dev_hndl) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } -#endif - return 0; -} - -#ifdef TANDEM_BOOT_SUPPORTED -/*****************************************************************************/ -/** - * qdma_cpm4_init_st_ctxt() - Initialize the ST context - * - * @dev_hndl: device handle - * - * Return: returns the platform specific error code - *****************************************************************************/ -int qdma_cpm4_init_st_ctxt(void *dev_hndl) -{ - uint32_t data[QDMA_REG_IND_CTXT_REG_COUNT]; - uint16_t i = 0; - struct qdma_dev_attributes dev_info; - - if (!dev_hndl) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - qdma_memset(data, 0, sizeof(uint32_t) * QDMA_REG_IND_CTXT_REG_COUNT); - qdma_cpm4_get_device_attributes(dev_hndl, &dev_info); - - for (; i < dev_info.num_qs; i++) { - int sel = QDMA_CTXT_SEL_CMPT; - int rv; - - for (; sel <= QDMA_CTXT_SEL_PFTCH; sel++) { - /** if the st mode(h2c/c2h) not enabled - * in the design, then skip the PFTCH - * and CMPT context setup - */ - if ((dev_info.st_en == 0) && - ((sel == QDMA_CTXT_SEL_PFTCH) || - (sel == QDMA_CTXT_SEL_CMPT))) { - qdma_log_debug("%s: ST context is skipped:", - __func__); - qdma_log_debug("sel = %d\n", sel); - continue; - } - - rv = qdma_cpm4_indirect_reg_clear(dev_hndl, - (enum ind_ctxt_cmd_sel)sel, i); - if (rv < 0) - return rv; - } - } - - return QDMA_SUCCESS; - -} -#endif - -static int get_reg_entry(uint32_t reg_addr, int *reg_entry) -{ - uint32_t i = 0; - struct xreg_info *reg_info; - uint32_t num_regs = qdma_cpm4_config_num_regs_get(); - - reg_info = qdma_cpm4_config_regs_get(); - - for (i = 0; (i < num_regs - 1); i++) { - if (reg_info[i].addr == reg_addr) { - *reg_entry = i; - break; - } - } - - if (i >= num_regs - 1) { - qdma_log_error("%s: 0x%08x is missing register list, err:%d\n", - __func__, - reg_addr, - -QDMA_ERR_INV_PARAM); - *reg_entry = -1; - return -QDMA_ERR_INV_PARAM; - } - - return 0; -} - -/*****************************************************************************/ -/** - * qdma_cpm4_dump_config_reg_list() - Dump the registers - * - * @dev_hndl: device handle - * @total_regs : Max registers to read - * @reg_list : array of reg addr and reg values - * @buf : pointer to buffer to be filled - * @buflen : Length of the buffer - * - * Return: returns the platform specific error code - *****************************************************************************/ -int qdma_cpm4_dump_config_reg_list(void *dev_hndl, uint32_t total_regs, - struct qdma_reg_data *reg_list, char *buf, uint32_t buflen) -{ - uint32_t j = 0, len = 0; - uint32_t reg_count = 0; - int reg_data_entry; - int rv = 0; - char name[DEBGFS_GEN_NAME_SZ] = ""; - struct xreg_info *reg_info = qdma_cpm4_config_regs_get(); - - if (!dev_hndl) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - if (!buf) { - qdma_log_error("%s: buf is NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - for (reg_count = 0; - (reg_count < total_regs);) { - - rv = get_reg_entry(reg_list[reg_count].reg_addr, - ®_data_entry); - if (rv < 0) { - qdma_log_error("%s: register missing in list, err:%d\n", - __func__, - -QDMA_ERR_INV_PARAM); - return rv; - } - - for (j = 0; j < reg_info[reg_data_entry].repeat; j++) { - rv = QDMA_SNPRINTF_S(name, DEBGFS_GEN_NAME_SZ, - DEBGFS_GEN_NAME_SZ, - "%s_%d", - reg_info[reg_data_entry].name, j); - if ((rv < 0) || (rv > DEBGFS_GEN_NAME_SZ)) { - qdma_log_error( - "%d:%s snprintf failed, err:%d\n", - __LINE__, __func__, - rv); - return -QDMA_ERR_NO_MEM; - } - rv = dump_reg(buf + len, buflen - len, - (reg_info[reg_data_entry].addr + (j * 4)), - name, - reg_list[reg_count + j].reg_val); - if (rv < 0) { - qdma_log_error( - "%s Buff too small, err:%d\n", - __func__, - -QDMA_ERR_NO_MEM); - return -QDMA_ERR_NO_MEM; - } - len += rv; - } - reg_count += j; - } - - return len; - -} - - -/*****************************************************************************/ -/** - * qdma_read_reg_list() - read the register values - * - * @dev_hndl: device handle - * @is_vf: Whether PF or VF - * @total_regs : Max registers to read - * @reg_list : array of reg addr and reg values - * - * Return: returns the platform specific error code - *****************************************************************************/ -int qdma_cpm4_read_reg_list(void *dev_hndl, uint8_t is_vf, - uint16_t reg_rd_slot, - uint16_t *total_regs, - struct qdma_reg_data *reg_list) -{ - uint16_t reg_count = 0, i = 0, j = 0; - uint32_t num_regs = qdma_cpm4_config_num_regs_get(); - struct xreg_info *reg_info = qdma_cpm4_config_regs_get(); - struct qdma_dev_attributes dev_cap; - uint32_t reg_start_addr = 0; - int reg_index = 0; - int rv = 0; - - if (!is_vf) { - qdma_log_error("%s: not supported for PF, err:%d\n", - __func__, - -QDMA_ERR_HWACC_FEATURE_NOT_SUPPORTED); - return -QDMA_ERR_HWACC_FEATURE_NOT_SUPPORTED; - } - - if (!dev_hndl) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - if (!reg_list) { - qdma_log_error("%s: reg_list is NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - qdma_cpm4_get_device_attributes(dev_hndl, &dev_cap); - - switch (reg_rd_slot) { - case QDMA_REG_READ_GROUP_1: - reg_start_addr = QDMA_CPM4_REG_GROUP_1_START_ADDR; - break; - case QDMA_REG_READ_GROUP_2: - reg_start_addr = QDMA_CPM4_REG_GROUP_2_START_ADDR; - break; - case QDMA_REG_READ_GROUP_3: - reg_start_addr = QDMA_CPM4_REG_GROUP_3_START_ADDR; - break; - case QDMA_REG_READ_GROUP_4: - reg_start_addr = QDMA_CPM4_REG_GROUP_4_START_ADDR; - break; - default: - qdma_log_error("%s: Invalid slot received\n", - __func__); - return -QDMA_ERR_INV_PARAM; - } - - rv = get_reg_entry(reg_start_addr, ®_index); - if (rv < 0) { - qdma_log_error("%s: register missing in list, err:%d\n", - __func__, - -QDMA_ERR_INV_PARAM); - return rv; - } - - for (i = 0, reg_count = 0; - ((i < num_regs - 1 - reg_index) && - (reg_count < QDMA_MAX_REGISTER_DUMP)); i++) { - - if (((GET_CAPABILITY_MASK(dev_cap.mm_en, dev_cap.st_en, - dev_cap.mm_cmpt_en, dev_cap.mailbox_en) - & reg_info[i].mode) == 0) || - (reg_info[i].read_type == QDMA_REG_READ_PF_ONLY)) - continue; - - for (j = 0; j < reg_info[i].repeat && - (reg_count < QDMA_MAX_REGISTER_DUMP); - j++) { - reg_list[reg_count].reg_addr = - (reg_info[i].addr + (j * 4)); - reg_list[reg_count].reg_val = - qdma_reg_read(dev_hndl, - reg_list[reg_count].reg_addr); - reg_count++; - } - } - - *total_regs = reg_count; - return rv; -} - -/*****************************************************************************/ -/** - * qdma_cpm4_write_global_ring_sizes() - set the global ring size array - * - * @dev_hndl: device handle - * @index: Index from where the values needs to written - * @count: number of entries to be written - * @glbl_rng_sz: pointer to the array having the values to write - * - * (index + count) shall not be more than 16 - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -static int qdma_cpm4_write_global_ring_sizes(void *dev_hndl, uint8_t index, - uint8_t count, const uint32_t *glbl_rng_sz) -{ - if (!dev_hndl || !glbl_rng_sz || !count) { - qdma_log_error("%s: dev_hndl=%p glbl_rng_sz=%p, err:%d\n", - __func__, dev_hndl, glbl_rng_sz, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - if ((index + count) > QDMA_NUM_RING_SIZES) { - qdma_log_error("%s: index=%u count=%u > %d, err:%d\n", - __func__, index, count, - QDMA_NUM_RING_SIZES, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - qdma_write_csr_values(dev_hndl, - QDMA_CPM4_GLBL_RNG_SZ_1_ADDR, index, count, - glbl_rng_sz); - - return QDMA_SUCCESS; -} - -/*****************************************************************************/ -/** - * qdma_cpm4_read_global_ring_sizes() - function to get the - * global rng_sz array - * - * @dev_hndl: device handle - * @index: Index from where the values needs to read - * @count: number of entries to be read - * @glbl_rng_sz: pointer to array to hold the values read - * - * (index + count) shall not be more than 16 - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -static int qdma_cpm4_read_global_ring_sizes(void *dev_hndl, uint8_t index, - uint8_t count, uint32_t *glbl_rng_sz) -{ - if (!dev_hndl || !glbl_rng_sz || !count) { - qdma_log_error("%s: dev_hndl=%p glbl_rng_sz=%p, err:%d\n", - __func__, dev_hndl, glbl_rng_sz, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - if ((index + count) > QDMA_NUM_RING_SIZES) { - qdma_log_error("%s: index=%u count=%u > %d, err:%d\n", - __func__, index, count, - QDMA_NUM_C2H_BUFFER_SIZES, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - qdma_read_csr_values(dev_hndl, - QDMA_CPM4_GLBL_RNG_SZ_1_ADDR, index, count, - glbl_rng_sz); - - return QDMA_SUCCESS; -} - -/*****************************************************************************/ -/** - * qdma_cpm4_write_global_timer_count() - function to set the timer values - * - * @dev_hndl: device handle - * @glbl_tmr_cnt: pointer to the array having the values to write - * @index: Index from where the values needs to written - * @count: number of entries to be written - * - * (index + count) shall not be more than 16 - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -static int qdma_cpm4_write_global_timer_count(void *dev_hndl, uint8_t index, - uint8_t count, const uint32_t *glbl_tmr_cnt) -{ - struct qdma_dev_attributes dev_cap; - - if (!dev_hndl || !glbl_tmr_cnt || !count) { - qdma_log_error("%s: dev_hndl=%p glbl_tmr_cnt=%p, err:%d\n", - __func__, dev_hndl, glbl_tmr_cnt, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - if ((index + count) > QDMA_NUM_C2H_TIMERS) { - qdma_log_error("%s: index=%u count=%u > %d, err:%d\n", - __func__, index, count, - QDMA_NUM_C2H_TIMERS, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - qdma_cpm4_get_device_attributes(dev_hndl, &dev_cap); - - if (dev_cap.st_en || dev_cap.mm_cmpt_en) - qdma_write_csr_values(dev_hndl, - QDMA_CPM4_C2H_TIMER_CNT_1_ADDR, - index, count, glbl_tmr_cnt); - else { - qdma_log_error("%s: ST or MM cmpt not supported, err:%d\n", - __func__, - -QDMA_ERR_HWACC_FEATURE_NOT_SUPPORTED); - return -QDMA_ERR_HWACC_FEATURE_NOT_SUPPORTED; - } - - return QDMA_SUCCESS; -} - -/*****************************************************************************/ -/** - * qdma_cpm4_read_global_timer_count() - function to get the timer values - * - * @dev_hndl: device handle - * @index: Index from where the values needs to read - * @count: number of entries to be read - * @glbl_tmr_cnt: pointer to array to hold the values read - * - * (index + count) shall not be more than 16 - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -static int qdma_cpm4_read_global_timer_count(void *dev_hndl, uint8_t index, - uint8_t count, uint32_t *glbl_tmr_cnt) -{ - struct qdma_dev_attributes dev_cap; - - if (!dev_hndl || !glbl_tmr_cnt || !count) { - qdma_log_error("%s: dev_hndl=%p glbl_tmr_cnt=%p, err:%d\n", - __func__, dev_hndl, glbl_tmr_cnt, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - if ((index + count) > QDMA_NUM_C2H_TIMERS) { - qdma_log_error("%s: index=%u count=%u > %d, err:%d\n", - __func__, index, count, - QDMA_NUM_C2H_TIMERS, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - qdma_cpm4_get_device_attributes(dev_hndl, &dev_cap); - - if (dev_cap.st_en || dev_cap.mm_cmpt_en) - qdma_read_csr_values(dev_hndl, - QDMA_CPM4_C2H_TIMER_CNT_1_ADDR, index, - count, glbl_tmr_cnt); - else { - qdma_log_error("%s: ST or MM cmpt not supported, err:%d\n", - __func__, - -QDMA_ERR_HWACC_FEATURE_NOT_SUPPORTED); - return -QDMA_ERR_HWACC_FEATURE_NOT_SUPPORTED; - } - - return QDMA_SUCCESS; -} - -/*****************************************************************************/ -/** - * qdma_cpm4_write_global_counter_threshold() - function to set the counter - * threshold values - * - * @dev_hndl: device handle - * @index: Index from where the values needs to written - * @count: number of entries to be written - * @glbl_cnt_th: pointer to the array having the values to write - * - * (index + count) shall not be more than 16 - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -static int qdma_cpm4_write_global_counter_threshold(void *dev_hndl, - uint8_t index, - uint8_t count, const uint32_t *glbl_cnt_th) -{ - struct qdma_dev_attributes dev_cap; - - if (!dev_hndl || !glbl_cnt_th || !count) { - qdma_log_error("%s: dev_hndl=%p glbl_cnt_th=%p, err:%d\n", - __func__, dev_hndl, glbl_cnt_th, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - if ((index + count) > QDMA_NUM_C2H_COUNTERS) { - qdma_log_error("%s: index=%u count=%u > %d, err:%d\n", - __func__, index, count, - QDMA_NUM_C2H_BUFFER_SIZES, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - qdma_cpm4_get_device_attributes(dev_hndl, &dev_cap); - - if (dev_cap.st_en || dev_cap.mm_cmpt_en) - qdma_write_csr_values(dev_hndl, - QDMA_CPM4_C2H_CNT_TH_1_ADDR, index, - count, glbl_cnt_th); - else { - qdma_log_error("%s: ST or MM cmpt not supported, err:%d\n", - __func__, - -QDMA_ERR_HWACC_FEATURE_NOT_SUPPORTED); - return -QDMA_ERR_HWACC_FEATURE_NOT_SUPPORTED; - } - - return QDMA_SUCCESS; -} - -/*****************************************************************************/ -/** - * qdma_cpm4_read_global_counter_threshold() - get the counter - * threshold values - * - * @dev_hndl: device handle - * @index: Index from where the values needs to read - * @count: number of entries to be read - * @glbl_cnt_th: pointer to array to hold the values read - * - * (index + count) shall not be more than 16 - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -static int qdma_cpm4_read_global_counter_threshold(void *dev_hndl, - uint8_t index, - uint8_t count, uint32_t *glbl_cnt_th) -{ - struct qdma_dev_attributes dev_cap; - - if (!dev_hndl || !glbl_cnt_th || !count) { - qdma_log_error("%s: dev_hndl=%p glbl_cnt_th=%p, err:%d\n", - __func__, dev_hndl, glbl_cnt_th, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - if ((index + count) > QDMA_NUM_C2H_COUNTERS) { - qdma_log_error("%s: index=%u count=%u > %d, err:%d\n", - __func__, index, count, - QDMA_NUM_C2H_COUNTERS, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - qdma_cpm4_get_device_attributes(dev_hndl, &dev_cap); - - if (dev_cap.st_en || dev_cap.mm_cmpt_en) - qdma_read_csr_values(dev_hndl, - QDMA_CPM4_C2H_CNT_TH_1_ADDR, index, - count, glbl_cnt_th); - else { - qdma_log_error("%s: ST or MM cmpt not supported, err:%d\n", - __func__, -QDMA_ERR_HWACC_FEATURE_NOT_SUPPORTED); - return -QDMA_ERR_HWACC_FEATURE_NOT_SUPPORTED; - } - - return QDMA_SUCCESS; -} - -/*****************************************************************************/ -/** - * qdma_cpm4_write_global_buffer_sizes() - function to set the buffer sizes - * - * @dev_hndl: device handle - * @index: Index from where the values needs to written - * @count: number of entries to be written - * @glbl_buf_sz: pointer to the array having the values to write - * - * (index + count) shall not be more than 16 - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -static int qdma_cpm4_write_global_buffer_sizes(void *dev_hndl, - uint8_t index, - uint8_t count, const uint32_t *glbl_buf_sz) -{ - struct qdma_dev_attributes dev_cap; - - if (!dev_hndl || !glbl_buf_sz || !count) { - qdma_log_error("%s: dev_hndl=%p glbl_buf_sz=%p, err:%d\n", - __func__, dev_hndl, glbl_buf_sz, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - if ((index + count) > QDMA_NUM_C2H_BUFFER_SIZES) { - qdma_log_error("%s: index=%u count=%u > %d, err:%d\n", - __func__, index, count, - QDMA_NUM_C2H_BUFFER_SIZES, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - qdma_cpm4_get_device_attributes(dev_hndl, &dev_cap); - - if (dev_cap.st_en) - qdma_write_csr_values(dev_hndl, - QDMA_CPM4_C2H_BUF_SZ_0_ADDR, index, - count, glbl_buf_sz); - else { - qdma_log_error("%s: ST not supported, err:%d\n", - __func__, - -QDMA_ERR_HWACC_FEATURE_NOT_SUPPORTED); - return -QDMA_ERR_HWACC_FEATURE_NOT_SUPPORTED; - } - - return QDMA_SUCCESS; -} - -/*****************************************************************************/ -/** - * qdma_cpm4_read_global_buffer_sizes() - function to get the buffer sizes - * - * @dev_hndl: device handle - * @index: Index from where the values needs to read - * @count: number of entries to be read - * @glbl_buf_sz: pointer to array to hold the values read - * - * (index + count) shall not be more than 16 - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -static int qdma_cpm4_read_global_buffer_sizes(void *dev_hndl, uint8_t index, - uint8_t count, uint32_t *glbl_buf_sz) -{ - struct qdma_dev_attributes dev_cap; - - if (!dev_hndl || !glbl_buf_sz || !count) { - qdma_log_error("%s: dev_hndl=%p glbl_buf_sz=%p, err:%d\n", - __func__, dev_hndl, glbl_buf_sz, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - if ((index + count) > QDMA_NUM_C2H_BUFFER_SIZES) { - qdma_log_error("%s: index=%u count=%u > %d, err:%d\n", - __func__, index, count, - QDMA_NUM_C2H_BUFFER_SIZES, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - qdma_cpm4_get_device_attributes(dev_hndl, &dev_cap); - - if (dev_cap.st_en) - qdma_read_csr_values(dev_hndl, - QDMA_CPM4_C2H_BUF_SZ_0_ADDR, index, - count, glbl_buf_sz); - else { - qdma_log_error("%s: ST is not supported, err:%d\n", - __func__, - -QDMA_ERR_HWACC_FEATURE_NOT_SUPPORTED); - return -QDMA_ERR_HWACC_FEATURE_NOT_SUPPORTED; - } - - return QDMA_SUCCESS; -} - -/*****************************************************************************/ -/** - * qdma_cpm4_global_csr_conf() - function to configure global csr - * - * @dev_hndl: device handle - * @index: Index from where the values needs to read - * @count: number of entries to be read - * @csr_val: uint32_t pointer to csr value - * @csr_type: Type of the CSR (qdma_global_csr_type enum) to configure - * @access_type HW access type (qdma_hw_access_type enum) value - * QDMA_HW_ACCESS_CLEAR - Not supported - * QDMA_HW_ACCESS_INVALIDATE - Not supported - * - * (index + count) shall not be more than 16 - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -int qdma_cpm4_global_csr_conf(void *dev_hndl, uint8_t index, uint8_t count, - uint32_t *csr_val, - enum qdma_global_csr_type csr_type, - enum qdma_hw_access_type access_type) -{ - int rv = QDMA_SUCCESS; - - switch (csr_type) { - case QDMA_CSR_RING_SZ: - switch (access_type) { - case QDMA_HW_ACCESS_READ: - rv = qdma_cpm4_read_global_ring_sizes( - dev_hndl, - index, - count, - csr_val); - break; - case QDMA_HW_ACCESS_WRITE: - rv = qdma_cpm4_write_global_ring_sizes( - dev_hndl, - index, - count, - csr_val); - break; - default: - qdma_log_error("%s: access_type(%d) invalid, err:%d\n", - __func__, - access_type, - -QDMA_ERR_INV_PARAM); - rv = -QDMA_ERR_INV_PARAM; - break; - } - break; - case QDMA_CSR_TIMER_CNT: - switch (access_type) { - case QDMA_HW_ACCESS_READ: - rv = qdma_cpm4_read_global_timer_count( - dev_hndl, - index, - count, - csr_val); - break; - case QDMA_HW_ACCESS_WRITE: - rv = qdma_cpm4_write_global_timer_count( - dev_hndl, - index, - count, - csr_val); - break; - default: - qdma_log_error("%s: access_type(%d) invalid, err:%d\n", - __func__, - access_type, - -QDMA_ERR_INV_PARAM); - rv = -QDMA_ERR_INV_PARAM; - break; - } - break; - case QDMA_CSR_CNT_TH: - switch (access_type) { - case QDMA_HW_ACCESS_READ: - rv = - qdma_cpm4_read_global_counter_threshold( - dev_hndl, - index, - count, - csr_val); - break; - case QDMA_HW_ACCESS_WRITE: - rv = - qdma_cpm4_write_global_counter_threshold( - dev_hndl, - index, - count, - csr_val); - break; - default: - qdma_log_error("%s: access_type(%d) invalid, err:%d\n", - __func__, - access_type, - -QDMA_ERR_INV_PARAM); - rv = -QDMA_ERR_INV_PARAM; - break; - } - break; - case QDMA_CSR_BUF_SZ: - switch (access_type) { - case QDMA_HW_ACCESS_READ: - rv = - qdma_cpm4_read_global_buffer_sizes(dev_hndl, - index, - count, - csr_val); - break; - case QDMA_HW_ACCESS_WRITE: - rv = - qdma_cpm4_write_global_buffer_sizes(dev_hndl, - index, - count, - csr_val); - break; - default: - qdma_log_error("%s: access_type(%d) invalid, err:%d\n", - __func__, - access_type, - -QDMA_ERR_INV_PARAM); - rv = -QDMA_ERR_INV_PARAM; - break; - } - break; - default: - qdma_log_error("%s: csr_type(%d) invalid, err:%d\n", - __func__, - csr_type, - -QDMA_ERR_INV_PARAM); - rv = -QDMA_ERR_INV_PARAM; - break; - } - - return rv; -} - -/*****************************************************************************/ -/** - * qdma_cpm4_global_writeback_interval_write() - function to set the - * writeback interval - * - * @dev_hndl device handle - * @wb_int: Writeback Interval - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -static int qdma_cpm4_global_writeback_interval_write(void *dev_hndl, - enum qdma_wrb_interval wb_int) -{ - uint32_t reg_val; - struct qdma_dev_attributes dev_cap; - - if (!dev_hndl) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", __func__, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - if (wb_int >= QDMA_NUM_WRB_INTERVALS) { - qdma_log_error("%s: wb_int=%d is invalid, err:%d\n", - __func__, wb_int, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - qdma_cpm4_get_device_attributes(dev_hndl, &dev_cap); - - if (dev_cap.st_en || dev_cap.mm_cmpt_en) { - reg_val = qdma_reg_read(dev_hndl, - QDMA_CPM4_GLBL_DSC_CFG_ADDR); - reg_val |= FIELD_SET(GLBL_DSC_CFG_WB_ACC_INT_MASK, wb_int); - - qdma_reg_write(dev_hndl, - QDMA_CPM4_GLBL_DSC_CFG_ADDR, reg_val); - } else { - qdma_log_error("%s: ST or MM cmpt not supported, err:%d\n", - __func__, -QDMA_ERR_HWACC_FEATURE_NOT_SUPPORTED); - return -QDMA_ERR_HWACC_FEATURE_NOT_SUPPORTED; - } - - return QDMA_SUCCESS; -} - -/*****************************************************************************/ -/** - * qdma_cpm4_global_writeback_interval_read() - function to get the - * writeback interval - * - * @dev_hndl: device handle - * @wb_int: pointer to the data to hold Writeback Interval - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -static int qdma_cpm4_global_writeback_interval_read(void *dev_hndl, - enum qdma_wrb_interval *wb_int) -{ - uint32_t reg_val; - struct qdma_dev_attributes dev_cap; - - if (!dev_hndl) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", __func__, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - if (!wb_int) { - qdma_log_error("%s: wb_int is NULL, err:%d\n", __func__, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - qdma_cpm4_get_device_attributes(dev_hndl, &dev_cap); - - if (dev_cap.st_en || dev_cap.mm_cmpt_en) { - reg_val = qdma_reg_read(dev_hndl, - QDMA_CPM4_GLBL_DSC_CFG_ADDR); - *wb_int = (enum qdma_wrb_interval)FIELD_GET( - GLBL_DSC_CFG_WB_ACC_INT_MASK, reg_val); - } else { - qdma_log_error("%s: ST or MM cmpt not supported, err:%d\n", - __func__, -QDMA_ERR_HWACC_FEATURE_NOT_SUPPORTED); - return -QDMA_ERR_HWACC_FEATURE_NOT_SUPPORTED; - } - - return QDMA_SUCCESS; -} - -/*****************************************************************************/ -/** - * qdma_cpm4_global_writeback_interval_conf() - function to configure - * the writeback interval - * - * @dev_hndl: device handle - * @wb_int: pointer to the data to hold Writeback Interval - * @access_type HW access type (qdma_hw_access_type enum) value - * QDMA_HW_ACCESS_CLEAR - Not supported - * QDMA_HW_ACCESS_INVALIDATE - Not supported - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -int qdma_cpm4_global_writeback_interval_conf(void *dev_hndl, - enum qdma_wrb_interval *wb_int, - enum qdma_hw_access_type access_type) -{ - int rv = QDMA_SUCCESS; - - switch (access_type) { - case QDMA_HW_ACCESS_READ: - rv = - qdma_cpm4_global_writeback_interval_read(dev_hndl, wb_int); - break; - case QDMA_HW_ACCESS_WRITE: - rv = - qdma_cpm4_global_writeback_interval_write(dev_hndl, - *wb_int); - break; - case QDMA_HW_ACCESS_CLEAR: - case QDMA_HW_ACCESS_INVALIDATE: - default: - qdma_log_error("%s: access_type(%d) invalid, err:%d\n", - __func__, - access_type, - -QDMA_ERR_INV_PARAM); - rv = -QDMA_ERR_INV_PARAM; - break; - } - - return rv; -} - - -/*****************************************************************************/ -/** - * qdma_cpm4_mm_channel_conf() - Function to enable/disable the MM channel - * - * @dev_hndl: device handle - * @channel: MM channel number - * @is_c2h: Queue direction. Set 1 for C2H and 0 for H2C - * @enable: Enable or disable MM channel - * - * Presently, we have only 1 MM channel - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -int qdma_cpm4_mm_channel_conf(void *dev_hndl, uint8_t channel, - uint8_t is_c2h, - uint8_t enable) -{ - uint32_t reg_addr = (is_c2h) ? QDMA_CPM4_C2H_CHANNEL_CTL_ADDR : - QDMA_CPM4_H2C_CHANNEL_CTL_ADDR; - struct qdma_dev_attributes dev_cap; - - if (!dev_hndl) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - qdma_cpm4_get_device_attributes(dev_hndl, &dev_cap); - - if (dev_cap.mm_en) { - qdma_reg_write(dev_hndl, - reg_addr + (channel * QDMA_MM_CONTROL_STEP), - enable); - } - - return QDMA_SUCCESS; -} - -int qdma_cpm4_dump_reg_info(void *dev_hndl, uint32_t reg_addr, - uint32_t num_regs, char *buf, uint32_t buflen) -{ - uint32_t total_num_regs = qdma_cpm4_config_num_regs_get(); - struct xreg_info *config_regs = qdma_cpm4_config_regs_get(); - const char *bitfield_name; - uint32_t i = 0, num_regs_idx = 0, k = 0, j = 0, - bitfield = 0, lsb = 0, msb = 31; - int rv = 0; - uint32_t reg_val; - uint32_t data_len = 0; - - if (!dev_hndl) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - for (i = 0; i < total_num_regs; i++) { - if (reg_addr == config_regs[i].addr) { - j = i; - break; - } - } - - if (i == total_num_regs) { - qdma_log_error("%s: Register not found err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - if (buf) - QDMA_SNPRINTF_S(buf, buflen, - DEBGFS_LINE_SZ, - "Register not found 0x%x\n", reg_addr); - return -QDMA_ERR_INV_PARAM; - } - - num_regs_idx = (j + num_regs < total_num_regs) ? - (j + num_regs) : total_num_regs; - - for (; j < num_regs_idx ; j++) { - reg_val = qdma_reg_read(dev_hndl, - config_regs[j].addr); - - if (buf) { - rv = QDMA_SNPRINTF_S(buf, buflen, - DEBGFS_LINE_SZ, - "\n%-40s 0x%-7x %-#10x %-10d\n", - config_regs[j].name, - config_regs[j].addr, - reg_val, reg_val); - if ((rv < 0) || (rv > DEBGFS_LINE_SZ)) { - qdma_log_error( - "%s: Insufficient buffer, err:%d\n", - __func__, -QDMA_ERR_NO_MEM); - return -QDMA_ERR_NO_MEM; - } - buf += rv; - data_len += rv; - buflen -= rv; - } else - qdma_log_info("%-40s 0x%-7x %-#10x %-10d\n", - config_regs[j].name, - config_regs[j].addr, - reg_val, reg_val); - - - for (k = 0; - k < config_regs[j].num_bitfields; k++) { - - bitfield = - config_regs[j].bitfields[k].field_mask; - bitfield_name = - config_regs[i].bitfields[k].field_name; - lsb = 0; - msb = 31; - - while (!(BIT(lsb) & bitfield)) - lsb++; - - while (!(BIT(msb) & bitfield)) - msb--; - - if (msb != lsb) { - if (buf) { - rv = QDMA_SNPRINTF_S(buf, buflen, - DEBGFS_LINE_SZ, - "%-40s [%2u,%2u] %#-10x\n", - bitfield_name, - msb, lsb, - (reg_val & bitfield) >> - lsb); - if ((rv < 0) || (rv > DEBGFS_LINE_SZ)) { - qdma_log_error( - "%s: Insufficient buffer, err:%d\n", - __func__, - -QDMA_ERR_NO_MEM); - return -QDMA_ERR_NO_MEM; - } - buf += rv; - data_len += rv; - buflen -= rv; - } else - qdma_log_info( - "%-40s [%2u,%2u] %#-10x\n", - bitfield_name, - msb, lsb, - (reg_val & bitfield) >> lsb); - - - } else { - if (buf) { - rv = QDMA_SNPRINTF_S(buf, buflen, - DEBGFS_LINE_SZ, - "%-40s [%5u] %#-10x\n", - bitfield_name, - lsb, - (reg_val & bitfield) >> - lsb); - if ((rv < 0) || (rv > DEBGFS_LINE_SZ)) { - qdma_log_error( - "%s: Insufficient buffer, err:%d\n", - __func__, - -QDMA_ERR_NO_MEM); - return -QDMA_ERR_NO_MEM; - } - buf += rv; - data_len += rv; - buflen -= rv; - } else - qdma_log_info( - "%-40s [%5u] %#-10x\n", - bitfield_name, - lsb, - (reg_val & bitfield) >> lsb); - - } - } - } - - return data_len; - -} diff --git a/QDMA/linux-kernel/driver/libqdma/qdma_access/qdma_cpm4_access/qdma_cpm4_access.h b/QDMA/linux-kernel/driver/libqdma/qdma_access/qdma_cpm4_access/qdma_cpm4_access.h deleted file mode 100755 index cecb0d731..000000000 --- a/QDMA/linux-kernel/driver/libqdma/qdma_access/qdma_cpm4_access/qdma_cpm4_access.h +++ /dev/null @@ -1,284 +0,0 @@ -/* - * Copyright (c) 2019-2022, Xilinx, Inc. All rights reserved. - * Copyright (c) 2022, Advanced Micro Devices, Inc. All rights reserved. - * - * This source code is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * The full GNU General Public License is included in this distribution in - * the file called "COPYING". - */ - -#ifndef __QDMA_CPM4_ACCESS_H_ -#define __QDMA_CPM4_ACCESS_H_ - -#ifdef __cplusplus -extern "C" { -#endif - -#include "qdma_platform.h" - -/** - * enum qdma_error_idx - qdma errors - */ -enum qdma_cpm4_error_idx { - /* Descriptor errors */ - QDMA_CPM4_DSC_ERR_POISON, - QDMA_CPM4_DSC_ERR_UR_CA, - QDMA_CPM4_DSC_ERR_PARAM, - QDMA_CPM4_DSC_ERR_ADDR, - QDMA_CPM4_DSC_ERR_TAG, - QDMA_CPM4_DSC_ERR_FLR, - QDMA_CPM4_DSC_ERR_TIMEOUT, - QDMA_CPM4_DSC_ERR_DAT_POISON, - QDMA_CPM4_DSC_ERR_FLR_CANCEL, - QDMA_CPM4_DSC_ERR_DMA, - QDMA_CPM4_DSC_ERR_DSC, - QDMA_CPM4_DSC_ERR_RQ_CANCEL, - QDMA_CPM4_DSC_ERR_DBE, - QDMA_CPM4_DSC_ERR_SBE, - QDMA_CPM4_DSC_ERR_ALL, - - /* TRQ Errors */ - QDMA_CPM4_TRQ_ERR_UNMAPPED, - QDMA_CPM4_TRQ_ERR_QID_RANGE, - QDMA_CPM4_TRQ_ERR_VF_ACCESS_ERR, - QDMA_CPM4_TRQ_ERR_TCP_TIMEOUT, - QDMA_CPM4_TRQ_ERR_ALL, - - /* C2H Errors */ - QDMA_CPM4_ST_C2H_ERR_MTY_MISMATCH, - QDMA_CPM4_ST_C2H_ERR_LEN_MISMATCH, - QDMA_CPM4_ST_C2H_ERR_QID_MISMATCH, - QDMA_CPM4_ST_C2H_ERR_DESC_RSP_ERR, - QDMA_CPM4_ST_C2H_ERR_ENG_WPL_DATA_PAR_ERR, - QDMA_CPM4_ST_C2H_ERR_MSI_INT_FAIL, - QDMA_CPM4_ST_C2H_ERR_ERR_DESC_CNT, - QDMA_CPM4_ST_C2H_ERR_PORTID_CTXT_MISMATCH, - QDMA_CPM4_ST_C2H_ERR_PORTID_BYP_IN_MISMATCH, - QDMA_CPM4_ST_C2H_ERR_WRB_INV_Q_ERR, - QDMA_CPM4_ST_C2H_ERR_WRB_QFULL_ERR, - QDMA_CPM4_ST_C2H_ERR_WRB_CIDX_ERR, - QDMA_CPM4_ST_C2H_ERR_WRB_PRTY_ERR, - QDMA_CPM4_ST_C2H_ERR_ALL, - - /* Fatal Errors */ - QDMA_CPM4_ST_FATAL_ERR_MTY_MISMATCH, - QDMA_CPM4_ST_FATAL_ERR_LEN_MISMATCH, - QDMA_CPM4_ST_FATAL_ERR_QID_MISMATCH, - QDMA_CPM4_ST_FATAL_ERR_TIMER_FIFO_RAM_RDBE, - QDMA_CPM4_ST_FATAL_ERR_PFCH_II_RAM_RDBE, - QDMA_CPM4_ST_FATAL_ERR_WRB_CTXT_RAM_RDBE, - QDMA_CPM4_ST_FATAL_ERR_PFCH_CTXT_RAM_RDBE, - QDMA_CPM4_ST_FATAL_ERR_DESC_REQ_FIFO_RAM_RDBE, - QDMA_CPM4_ST_FATAL_ERR_INT_CTXT_RAM_RDBE, - QDMA_CPM4_ST_FATAL_ERR_INT_QID2VEC_RAM_RDBE, - QDMA_CPM4_ST_FATAL_ERR_WRB_COAL_DATA_RAM_RDBE, - QDMA_CPM4_ST_FATAL_ERR_TUSER_FIFO_RAM_RDBE, - QDMA_CPM4_ST_FATAL_ERR_QID_FIFO_RAM_RDBE, - QDMA_CPM4_ST_FATAL_ERR_PAYLOAD_FIFO_RAM_RDBE, - QDMA_CPM4_ST_FATAL_ERR_WPL_DATA_PAR_ERR, - QDMA_CPM4_ST_FATAL_ERR_ALL, - - /* H2C Errors */ - QDMA_CPM4_ST_H2C_ERR_ZERO_LEN_DESC_ERR, - QDMA_CPM4_ST_H2C_ERR_SDI_MRKR_REQ_MOP_ERR, - QDMA_CPM4_ST_H2C_ERR_NO_DMA_DSC, - QDMA_CPM4_ST_H2C_ERR_DBE, - QDMA_CPM4_ST_H2C_ERR_SBE, - QDMA_CPM4_ST_H2C_ERR_ALL, - - /* Single bit errors */ - QDMA_CPM4_SBE_ERR_MI_H2C0_DAT, - QDMA_CPM4_SBE_ERR_MI_C2H0_DAT, - QDMA_CPM4_SBE_ERR_H2C_RD_BRG_DAT, - QDMA_CPM4_SBE_ERR_H2C_WR_BRG_DAT, - QDMA_CPM4_SBE_ERR_C2H_RD_BRG_DAT, - QDMA_CPM4_SBE_ERR_C2H_WR_BRG_DAT, - QDMA_CPM4_SBE_ERR_FUNC_MAP, - QDMA_CPM4_SBE_ERR_DSC_HW_CTXT, - QDMA_CPM4_SBE_ERR_DSC_CRD_RCV, - QDMA_CPM4_SBE_ERR_DSC_SW_CTXT, - QDMA_CPM4_SBE_ERR_DSC_CPLI, - QDMA_CPM4_SBE_ERR_DSC_CPLD, - QDMA_CPM4_SBE_ERR_PASID_CTXT_RAM, - QDMA_CPM4_SBE_ERR_TIMER_FIFO_RAM, - QDMA_CPM4_SBE_ERR_PAYLOAD_FIFO_RAM, - QDMA_CPM4_SBE_ERR_QID_FIFO_RAM, - QDMA_CPM4_SBE_ERR_TUSER_FIFO_RAM, - QDMA_CPM4_SBE_ERR_WRB_COAL_DATA_RAM, - QDMA_CPM4_SBE_ERR_INT_QID2VEC_RAM, - QDMA_CPM4_SBE_ERR_INT_CTXT_RAM, - QDMA_CPM4_SBE_ERR_DESC_REQ_FIFO_RAM, - QDMA_CPM4_SBE_ERR_PFCH_CTXT_RAM, - QDMA_CPM4_SBE_ERR_WRB_CTXT_RAM, - QDMA_CPM4_SBE_ERR_PFCH_LL_RAM, - QDMA_CPM4_SBE_ERR_ALL, - - /* Double bit Errors */ - QDMA_CPM4_DBE_ERR_MI_H2C0_DAT, - QDMA_CPM4_DBE_ERR_MI_C2H0_DAT, - QDMA_CPM4_DBE_ERR_H2C_RD_BRG_DAT, - QDMA_CPM4_DBE_ERR_H2C_WR_BRG_DAT, - QDMA_CPM4_DBE_ERR_C2H_RD_BRG_DAT, - QDMA_CPM4_DBE_ERR_C2H_WR_BRG_DAT, - QDMA_CPM4_DBE_ERR_FUNC_MAP, - QDMA_CPM4_DBE_ERR_DSC_HW_CTXT, - QDMA_CPM4_DBE_ERR_DSC_CRD_RCV, - QDMA_CPM4_DBE_ERR_DSC_SW_CTXT, - QDMA_CPM4_DBE_ERR_DSC_CPLI, - QDMA_CPM4_DBE_ERR_DSC_CPLD, - QDMA_CPM4_DBE_ERR_PASID_CTXT_RAM, - QDMA_CPM4_DBE_ERR_TIMER_FIFO_RAM, - QDMA_CPM4_DBE_ERR_PAYLOAD_FIFO_RAM, - QDMA_CPM4_DBE_ERR_QID_FIFO_RAM, - QDMA_CPM4_DBE_ERR_WRB_COAL_DATA_RAM, - QDMA_CPM4_DBE_ERR_INT_QID2VEC_RAM, - QDMA_CPM4_DBE_ERR_INT_CTXT_RAM, - QDMA_CPM4_DBE_ERR_DESC_REQ_FIFO_RAM, - QDMA_CPM4_DBE_ERR_PFCH_CTXT_RAM, - QDMA_CPM4_DBE_ERR_WRB_CTXT_RAM, - QDMA_CPM4_DBE_ERR_PFCH_LL_RAM, - QDMA_CPM4_DBE_ERR_ALL, - - QDMA_CPM4_ERRS_ALL -}; - -struct qdma_cpm4_hw_err_info { - enum qdma_cpm4_error_idx idx; - const char *err_name; - uint32_t mask_reg_addr; - uint32_t stat_reg_addr; - uint32_t leaf_err_mask; - uint32_t global_err_mask; - void (*qdma_cpm4_hw_err_process)(void *dev_hndl); -}; - - -int qdma_cpm4_init_ctxt_memory(void *dev_hndl); - -#ifdef TANDEM_BOOT_SUPPORTED -int qdma_cpm4_init_st_ctxt(void *dev_hndl); -#endif - -int qdma_cpm4_qid2vec_conf(void *dev_hndl, uint8_t c2h, uint16_t hw_qid, - struct qdma_qid2vec *ctxt, - enum qdma_hw_access_type access_type); - -int qdma_cpm4_fmap_conf(void *dev_hndl, uint16_t func_id, - struct qdma_fmap_cfg *config, - enum qdma_hw_access_type access_type); - -int qdma_cpm4_sw_ctx_conf(void *dev_hndl, uint8_t c2h, uint16_t hw_qid, - struct qdma_descq_sw_ctxt *ctxt, - enum qdma_hw_access_type access_type); - -int qdma_cpm4_pfetch_ctx_conf(void *dev_hndl, uint16_t hw_qid, - struct qdma_descq_prefetch_ctxt *ctxt, - enum qdma_hw_access_type access_type); - -int qdma_cpm4_cmpt_ctx_conf(void *dev_hndl, uint16_t hw_qid, - struct qdma_descq_cmpt_ctxt *ctxt, - enum qdma_hw_access_type access_type); - -int qdma_cpm4_hw_ctx_conf(void *dev_hndl, uint8_t c2h, uint16_t hw_qid, - struct qdma_descq_hw_ctxt *ctxt, - enum qdma_hw_access_type access_type); - -int qdma_cpm4_credit_ctx_conf(void *dev_hndl, uint8_t c2h, uint16_t hw_qid, - struct qdma_descq_credit_ctxt *ctxt, - enum qdma_hw_access_type access_type); - -int qdma_cpm4_indirect_intr_ctx_conf(void *dev_hndl, uint16_t ring_index, - struct qdma_indirect_intr_ctxt *ctxt, - enum qdma_hw_access_type access_type); - -int qdma_cpm4_set_default_global_csr(void *dev_hndl); - -int qdma_cpm4_queue_pidx_update(void *dev_hndl, uint8_t is_vf, uint16_t qid, - uint8_t is_c2h, const struct qdma_q_pidx_reg_info *reg_info); - -int qdma_cpm4_queue_cmpt_cidx_update(void *dev_hndl, uint8_t is_vf, - uint16_t qid, const struct qdma_q_cmpt_cidx_reg_info *reg_info); - -int qdma_cpm4_queue_intr_cidx_update(void *dev_hndl, uint8_t is_vf, - uint16_t qid, const struct qdma_intr_cidx_reg_info *reg_info); - -int qdma_cmp_get_user_bar(void *dev_hndl, uint8_t is_vf, - uint16_t func_id, uint8_t *user_bar); - -int qdma_cpm4_get_device_attributes(void *dev_hndl, - struct qdma_dev_attributes *dev_info); - -uint32_t qdma_cpm4_reg_dump_buf_len(void); - -int qdma_cpm4_context_buf_len(uint8_t st, - enum qdma_dev_q_type q_type, uint32_t *req_buflen); - -int qdma_cpm4_dump_config_regs(void *dev_hndl, uint8_t is_vf, - char *buf, uint32_t buflen); - -int qdma_cpm4_hw_error_process(void *dev_hndl); -const char *qdma_cpm4_hw_get_error_name(uint32_t err_idx); -int qdma_cpm4_hw_error_enable(void *dev_hndl, uint32_t err_idx); - -int qdma_cpm4_dump_queue_context(void *dev_hndl, - uint8_t st, - enum qdma_dev_q_type q_type, - struct qdma_descq_context *ctxt_data, - char *buf, uint32_t buflen); - -int qdma_cpm4_dump_intr_context(void *dev_hndl, - struct qdma_indirect_intr_ctxt *intr_ctx, - int ring_index, - char *buf, uint32_t buflen); - -int qdma_cpm4_read_dump_queue_context(void *dev_hndl, - uint16_t func_id, - uint16_t qid_hw, - uint8_t st, - enum qdma_dev_q_type q_type, - char *buf, uint32_t buflen); - -int qdma_cpm4_dump_config_reg_list(void *dev_hndl, - uint32_t total_regs, - struct qdma_reg_data *reg_list, - char *buf, uint32_t buflen); - -int qdma_cpm4_read_reg_list(void *dev_hndl, uint8_t is_vf, - uint16_t reg_rd_slot, - uint16_t *total_regs, - struct qdma_reg_data *reg_list); - -int qdma_cpm4_global_csr_conf(void *dev_hndl, uint8_t index, - uint8_t count, - uint32_t *csr_val, - enum qdma_global_csr_type csr_type, - enum qdma_hw_access_type access_type); - -int qdma_cpm4_global_writeback_interval_conf(void *dev_hndl, - enum qdma_wrb_interval *wb_int, - enum qdma_hw_access_type access_type); - -int qdma_cpm4_mm_channel_conf(void *dev_hndl, uint8_t channel, - uint8_t is_c2h, - uint8_t enable); - -int qdma_cpm4_dump_reg_info(void *dev_hndl, uint32_t reg_addr, - uint32_t num_regs, char *buf, uint32_t buflen); - -uint32_t qdma_cpm4_get_config_num_regs(void); - -struct xreg_info *qdma_cpm4_get_config_regs(void); - -#ifdef __cplusplus -} -#endif - -#endif /* __QDMA_CPM4_ACCESS_H_ */ diff --git a/QDMA/linux-kernel/driver/libqdma/qdma_access/qdma_cpm4_access/qdma_cpm4_reg.h b/QDMA/linux-kernel/driver/libqdma/qdma_access/qdma_cpm4_access/qdma_cpm4_reg.h deleted file mode 100755 index dee28b4d2..000000000 --- a/QDMA/linux-kernel/driver/libqdma/qdma_access/qdma_cpm4_access/qdma_cpm4_reg.h +++ /dev/null @@ -1,2046 +0,0 @@ -/* - * Copyright (c) 2019-2022, Xilinx, Inc. All rights reserved. - * Copyright (c) 2022, Advanced Micro Devices, Inc. All rights reserved. - * - * This source code is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * The full GNU General Public License is included in this distribution in - * the file called "COPYING". - */ - -#ifndef __QDMA_CPM4_REG_H -#define __QDMA_CPM4_REG_H - - -#ifdef __cplusplus -extern "C" { -#endif - -#include "qdma_platform.h" - -#ifdef CHAR_BIT -#undef CHAR_BIT -#endif -#define CHAR_BIT 8 - -#ifdef BIT -#undef BIT -#endif -#define BIT(n) (1u << (n)) - -#ifdef BITS_PER_BYTE -#undef BITS_PER_BYTE -#endif -#define BITS_PER_BYTE CHAR_BIT - -#ifdef BITS_PER_LONG -#undef BITS_PER_LONG -#endif -#define BITS_PER_LONG (sizeof(uint32_t) * BITS_PER_BYTE) - -#ifdef BITS_PER_LONG_LONG -#undef BITS_PER_LONG_LONG -#endif -#define BITS_PER_LONG_LONG (sizeof(uint64_t) * BITS_PER_BYTE) - -#ifdef GENMASK -#undef GENMASK -#endif -#define GENMASK(h, l) \ - ((0xFFFFFFFF << (l)) & (0xFFFFFFFF >> (BITS_PER_LONG - 1 - (h)))) - -#ifdef GENMASK_ULL -#undef GENMASK_ULL -#endif -#define GENMASK_ULL(h, l) \ - ((0xFFFFFFFFFFFFFFFF << (l)) & \ - (0xFFFFFFFFFFFFFFFF >> (BITS_PER_LONG_LONG - 1 - (h)))) - -#define DEBGFS_LINE_SZ (81) - -#ifdef ARRAY_SIZE -#undef ARRAY_SIZE -#endif -#define ARRAY_SIZE(arr) (sizeof(arr) / \ - sizeof(arr[0])) - - -uint32_t qdma_cpm4_config_num_regs_get(void); -struct xreg_info *qdma_cpm4_config_regs_get(void); -#define QDMA_CPM4_CFG_BLK_IDENTIFIER_ADDR 0x00 -#define CFG_BLK_IDENTIFIER_MASK GENMASK(31, 20) -#define CFG_BLK_IDENTIFIER_1_MASK GENMASK(19, 16) -#define CFG_BLK_IDENTIFIER_RSVD_1_MASK GENMASK(15, 8) -#define CFG_BLK_IDENTIFIER_VERSION_MASK GENMASK(7, 0) -#define QDMA_CPM4_CFG_BLK_BUSDEV_ADDR 0x04 -#define CFG_BLK_BUSDEV_BDF_MASK GENMASK(15, 0) -#define QDMA_CPM4_CFG_BLK_PCIE_MAX_PLD_SIZE_ADDR 0x08 -#define CFG_BLK_PCIE_MAX_PLD_SIZE_MASK GENMASK(2, 0) -#define QDMA_CPM4_CFG_BLK_PCIE_MAX_READ_REQ_SIZE_ADDR 0x0C -#define CFG_BLK_PCIE_MAX_READ_REQ_SIZE_MASK GENMASK(2, 0) -#define QDMA_CPM4_CFG_BLK_SYSTEM_ID_ADDR 0x10 -#define CFG_BLK_SYSTEM_ID_MASK GENMASK(15, 0) -#define QDMA_CPM4_CFG_BLK_MSI_ENABLE_ADDR 0x014 -#define CFG_BLK_MSI_ENABLE_3_MASK BIT(17) -#define CFG_BLK_MSI_ENABLE_MSIX3_MASK BIT(16) -#define CFG_BLK_MSI_ENABLE_2_MASK BIT(13) -#define CFG_BLK_MSI_ENABLE_MSIX2_MASK BIT(12) -#define CFG_BLK_MSI_ENABLE_1_MASK BIT(9) -#define CFG_BLK_MSI_ENABLE_MSIX1_MASK BIT(8) -#define CFG_BLK_MSI_ENABLE_0_MASK BIT(1) -#define CFG_BLK_MSI_ENABLE_MSIX0_MASK BIT(0) -#define QDMA_CPM4_CFG_PCIE_DATA_WIDTH_ADDR 0x18 -#define CFG_PCIE_DATA_WIDTH_DATAPATH_MASK GENMASK(2, 0) -#define QDMA_CPM4_CFG_PCIE_CTL_ADDR 0x1C -#define CFG_PCIE_CTL_RRQ_DISABLE_MASK BIT(1) -#define CFG_PCIE_CTL_RELAXED_ORDERING_MASK BIT(0) -#define QDMA_CPM4_CFG_AXI_USER_MAX_PLD_SIZE_ADDR 0x40 -#define CFG_AXI_USER_MAX_PLD_SIZE_ISSUED_MASK GENMASK(6, 4) -#define CFG_AXI_USER_MAX_PLD_SIZE_PROG_MASK GENMASK(2, 0) -#define QDMA_CPM4_CFG_AXI_USER_MAX_READ_REQ_SIZE_ADDR 0x44 -#define CFG_AXI_USER_MAX_READ_REQ_SIZE_USISSUED_MASK GENMASK(6, 4) -#define CFG_AXI_USER_MAX_READ_REQ_SIZE_USPROG_MASK GENMASK(2, 0) -#define QDMA_CPM4_CFG_BLK_MISC_CTL_ADDR 0x4C -#define CFG_BLK_MISC_CTL_NUM_TAG_MASK GENMASK(19, 8) -#define CFG_BLK_MISC_CTL_RQ_METERING_MULTIPLIER_MASK GENMASK(4, 0) -#define QDMA_CPM4_CFG_BLK_SCRATCH_0_ADDR 0x80 -#define CFG_BLK_SCRATCH_0_MASK GENMASK(31, 0) -#define QDMA_CPM4_CFG_BLK_SCRATCH_1_ADDR 0x84 -#define CFG_BLK_SCRATCH_1_MASK GENMASK(31, 0) -#define QDMA_CPM4_CFG_BLK_SCRATCH_2_ADDR 0x88 -#define CFG_BLK_SCRATCH_2_MASK GENMASK(31, 0) -#define QDMA_CPM4_CFG_BLK_SCRATCH_3_ADDR 0x8C -#define CFG_BLK_SCRATCH_3_MASK GENMASK(31, 0) -#define QDMA_CPM4_CFG_BLK_SCRATCH_4_ADDR 0x90 -#define CFG_BLK_SCRATCH_4_MASK GENMASK(31, 0) -#define QDMA_CPM4_CFG_BLK_SCRATCH_5_ADDR 0x94 -#define CFG_BLK_SCRATCH_5_MASK GENMASK(31, 0) -#define QDMA_CPM4_CFG_BLK_SCRATCH_6_ADDR 0x98 -#define CFG_BLK_SCRATCH_6_MASK GENMASK(31, 0) -#define QDMA_CPM4_CFG_BLK_SCRATCH_7_ADDR 0x9C -#define CFG_BLK_SCRATCH_7_MASK GENMASK(31, 0) -#define QDMA_CPM4_RAM_SBE_MSK_A_ADDR 0xF0 -#define RAM_SBE_MSK_A_MASK GENMASK(31, 0) -#define QDMA_CPM4_RAM_SBE_STS_A_ADDR 0xF4 -#define RAM_SBE_STS_A_RSVD_1_MASK BIT(31) -#define RAM_SBE_STS_A_PFCH_LL_RAM_MASK BIT(30) -#define RAM_SBE_STS_A_WRB_CTXT_RAM_MASK BIT(29) -#define RAM_SBE_STS_A_PFCH_CTXT_RAM_MASK BIT(28) -#define RAM_SBE_STS_A_DESC_REQ_FIFO_RAM_MASK BIT(27) -#define RAM_SBE_STS_A_INT_CTXT_RAM_MASK BIT(26) -#define RAM_SBE_STS_A_INT_QID2VEC_RAM_MASK BIT(25) -#define RAM_SBE_STS_A_WRB_COAL_DATA_RAM_MASK BIT(24) -#define RAM_SBE_STS_A_TUSER_FIFO_RAM_MASK BIT(23) -#define RAM_SBE_STS_A_QID_FIFO_RAM_MASK BIT(22) -#define RAM_SBE_STS_A_PLD_FIFO_RAM_MASK BIT(21) -#define RAM_SBE_STS_A_TIMER_FIFO_RAM_MASK BIT(20) -#define RAM_SBE_STS_A_PASID_CTXT_RAM_MASK BIT(19) -#define RAM_SBE_STS_A_DSC_CPLD_MASK BIT(18) -#define RAM_SBE_STS_A_DSC_CPLI_MASK BIT(17) -#define RAM_SBE_STS_A_DSC_SW_CTXT_MASK BIT(16) -#define RAM_SBE_STS_A_DSC_CRD_RCV_MASK BIT(15) -#define RAM_SBE_STS_A_DSC_HW_CTXT_MASK BIT(14) -#define RAM_SBE_STS_A_FUNC_MAP_MASK BIT(13) -#define RAM_SBE_STS_A_C2H_WR_BRG_DAT_MASK BIT(12) -#define RAM_SBE_STS_A_C2H_RD_BRG_DAT_MASK BIT(11) -#define RAM_SBE_STS_A_H2C_WR_BRG_DAT_MASK BIT(10) -#define RAM_SBE_STS_A_H2C_RD_BRG_DAT_MASK BIT(9) -#define RAM_SBE_STS_A_RSVD_2_MASK GENMASK(8, 5) -#define RAM_SBE_STS_A_MI_C2H0_DAT_MASK BIT(4) -#define RAM_SBE_STS_A_RSVD_3_MASK GENMASK(3, 1) -#define RAM_SBE_STS_A_MI_H2C0_DAT_MASK BIT(0) -#define QDMA_CPM4_RAM_DBE_MSK_A_ADDR 0xF8 -#define RAM_DBE_MSK_A_MASK GENMASK(31, 0) -#define QDMA_CPM4_RAM_DBE_STS_A_ADDR 0xFC -#define RAM_DBE_STS_A_RSVD_1_MASK BIT(31) -#define RAM_DBE_STS_A_PFCH_LL_RAM_MASK BIT(30) -#define RAM_DBE_STS_A_WRB_CTXT_RAM_MASK BIT(29) -#define RAM_DBE_STS_A_PFCH_CTXT_RAM_MASK BIT(28) -#define RAM_DBE_STS_A_DESC_REQ_FIFO_RAM_MASK BIT(27) -#define RAM_DBE_STS_A_INT_CTXT_RAM_MASK BIT(26) -#define RAM_DBE_STS_A_INT_QID2VEC_RAM_MASK BIT(25) -#define RAM_DBE_STS_A_WRB_COAL_DATA_RAM_MASK BIT(24) -#define RAM_DBE_STS_A_TUSER_FIFO_RAM_MASK BIT(23) -#define RAM_DBE_STS_A_QID_FIFO_RAM_MASK BIT(22) -#define RAM_DBE_STS_A_PLD_FIFO_RAM_MASK BIT(21) -#define RAM_DBE_STS_A_TIMER_FIFO_RAM_MASK BIT(20) -#define RAM_DBE_STS_A_PASID_CTXT_RAM_MASK BIT(19) -#define RAM_DBE_STS_A_DSC_CPLD_MASK BIT(18) -#define RAM_DBE_STS_A_DSC_CPLI_MASK BIT(17) -#define RAM_DBE_STS_A_DSC_SW_CTXT_MASK BIT(16) -#define RAM_DBE_STS_A_DSC_CRD_RCV_MASK BIT(15) -#define RAM_DBE_STS_A_DSC_HW_CTXT_MASK BIT(14) -#define RAM_DBE_STS_A_FUNC_MAP_MASK BIT(13) -#define RAM_DBE_STS_A_C2H_WR_BRG_DAT_MASK BIT(12) -#define RAM_DBE_STS_A_C2H_RD_BRG_DAT_MASK BIT(11) -#define RAM_DBE_STS_A_H2C_WR_BRG_DAT_MASK BIT(10) -#define RAM_DBE_STS_A_H2C_RD_BRG_DAT_MASK BIT(9) -#define RAM_DBE_STS_A_RSVD_2_MASK GENMASK(8, 5) -#define RAM_DBE_STS_A_MI_C2H0_DAT_MASK BIT(4) -#define RAM_DBE_STS_A_RSVD_3_MASK GENMASK(3, 1) -#define RAM_DBE_STS_A_MI_H2C0_DAT_MASK BIT(0) -#define QDMA_CPM4_GLBL2_IDENTIFIER_ADDR 0x100 -#define GLBL2_IDENTIFIER_MASK GENMASK(31, 8) -#define GLBL2_IDENTIFIER_VERSION_MASK GENMASK(7, 0) -#define QDMA_CPM4_GLBL2_PF_BARLITE_INT_ADDR 0x104 -#define GLBL2_PF_BARLITE_INT_PF3_BAR_MAP_MASK GENMASK(23, 18) -#define GLBL2_PF_BARLITE_INT_PF2_BAR_MAP_MASK GENMASK(17, 12) -#define GLBL2_PF_BARLITE_INT_PF1_BAR_MAP_MASK GENMASK(11, 6) -#define GLBL2_PF_BARLITE_INT_PF0_BAR_MAP_MASK GENMASK(5, 0) -#define QDMA_CPM4_GLBL2_PF_VF_BARLITE_INT_ADDR 0x108 -#define GLBL2_PF_VF_BARLITE_INT_PF3_MAP_MASK GENMASK(23, 18) -#define GLBL2_PF_VF_BARLITE_INT_PF2_MAP_MASK GENMASK(17, 12) -#define GLBL2_PF_VF_BARLITE_INT_PF1_MAP_MASK GENMASK(11, 6) -#define GLBL2_PF_VF_BARLITE_INT_PF0_MAP_MASK GENMASK(5, 0) -#define QDMA_CPM4_GLBL2_PF_BARLITE_EXT_ADDR 0x10C -#define GLBL2_PF_BARLITE_EXT_PF3_BAR_MAP_MASK GENMASK(23, 18) -#define GLBL2_PF_BARLITE_EXT_PF2_BAR_MAP_MASK GENMASK(17, 12) -#define GLBL2_PF_BARLITE_EXT_PF1_BAR_MAP_MASK GENMASK(11, 6) -#define GLBL2_PF_BARLITE_EXT_PF0_BAR_MAP_MASK GENMASK(5, 0) -#define QDMA_CPM4_GLBL2_PF_VF_BARLITE_EXT_ADDR 0x110 -#define GLBL2_PF_VF_BARLITE_EXT_PF3_MAP_MASK GENMASK(23, 18) -#define GLBL2_PF_VF_BARLITE_EXT_PF2_MAP_MASK GENMASK(17, 12) -#define GLBL2_PF_VF_BARLITE_EXT_PF1_MAP_MASK GENMASK(11, 6) -#define GLBL2_PF_VF_BARLITE_EXT_PF0_MAP_MASK GENMASK(5, 0) -#define QDMA_CPM4_GLBL2_CHANNEL_INST_ADDR 0x114 -#define GLBL2_CHANNEL_INST_RSVD_1_MASK GENMASK(31, 18) -#define GLBL2_CHANNEL_INST_C2H_ST_MASK BIT(17) -#define GLBL2_CHANNEL_INST_H2C_ST_MASK BIT(16) -#define GLBL2_CHANNEL_INST_RSVD_2_MASK GENMASK(15, 9) -#define GLBL2_CHANNEL_INST_C2H_ENG_MASK BIT(8) -#define GLBL2_CHANNEL_INST_RSVD_3_MASK GENMASK(7, 1) -#define GLBL2_CHANNEL_INST_H2C_ENG_MASK BIT(0) -#define QDMA_CPM4_GLBL2_CHANNEL_MDMA_ADDR 0x118 -#define GLBL2_CHANNEL_MDMA_RSVD_1_MASK GENMASK(31, 18) -#define GLBL2_CHANNEL_MDMA_C2H_ST_MASK BIT(17) -#define GLBL2_CHANNEL_MDMA_H2C_ST_MASK BIT(16) -#define GLBL2_CHANNEL_MDMA_RSVD_2_MASK GENMASK(15, 9) -#define GLBL2_CHANNEL_MDMA_C2H_ENG_MASK BIT(8) -#define GLBL2_CHANNEL_MDMA_RSVD_3_MASK GENMASK(7, 1) -#define GLBL2_CHANNEL_MDMA_H2C_ENG_MASK BIT(0) -#define QDMA_CPM4_GLBL2_CHANNEL_STRM_ADDR 0x11C -#define GLBL2_CHANNEL_STRM_RSVD_1_MASK GENMASK(31, 18) -#define GLBL2_CHANNEL_STRM_C2H_ST_MASK BIT(17) -#define GLBL2_CHANNEL_STRM_H2C_ST_MASK BIT(16) -#define GLBL2_CHANNEL_STRM_RSVD_2_MASK GENMASK(15, 9) -#define GLBL2_CHANNEL_STRM_C2H_ENG_MASK BIT(8) -#define GLBL2_CHANNEL_STRM_RSVD_3_MASK GENMASK(7, 1) -#define GLBL2_CHANNEL_STRM_H2C_ENG_MASK BIT(0) -#define QDMA_CPM4_GLBL2_CHANNEL_CAP_ADDR 0x120 -#define GLBL2_CHANNEL_CAP_RSVD_1_MASK GENMASK(31, 12) -#define GLBL2_CHANNEL_CAP_MULTIQ_MAX_MASK GENMASK(11, 0) -#define QDMA_CPM4_GLBL2_CHANNEL_PASID_CAP_ADDR 0x128 -#define GLBL2_CHANNEL_PASID_CAP_RSVD_1_MASK GENMASK(31, 16) -#define GLBL2_CHANNEL_PASID_CAP_BRIDGEOFFSET_MASK GENMASK(15, 4) -#define GLBL2_CHANNEL_PASID_CAP_RSVD_2_MASK GENMASK(3, 2) -#define GLBL2_CHANNEL_PASID_CAP_BRIDGEEN_MASK BIT(1) -#define GLBL2_CHANNEL_PASID_CAP_DMAEN_MASK BIT(0) -#define QDMA_CPM4_GLBL2_CHANNEL_FUNC_RET_ADDR 0x12C -#define GLBL2_CHANNEL_FUNC_RET_RSVD_1_MASK GENMASK(31, 8) -#define GLBL2_CHANNEL_FUNC_RET_FUNC_MASK GENMASK(7, 0) -#define QDMA_CPM4_GLBL2_SYSTEM_ID_ADDR 0x130 -#define GLBL2_SYSTEM_ID_RSVD_1_MASK GENMASK(31, 16) -#define GLBL2_SYSTEM_ID_MASK GENMASK(15, 0) -#define QDMA_CPM4_GLBL2_MISC_CAP_ADDR 0x134 -#define GLBL2_MISC_CAP_RSVD_1_MASK GENMASK(31, 0) -#define QDMA_CPM4_GLBL2_DBG_PCIE_RQ0_ADDR 0x1B8 -#define GLBL2_PCIE_RQ0_NPH_AVL_MASK GENMASK(31, 20) -#define GLBL2_PCIE_RQ0_RCB_AVL_MASK GENMASK(19, 10) -#define GLBL2_PCIE_RQ0_SLV_RD_CREDS_MASK GENMASK(9, 4) -#define GLBL2_PCIE_RQ0_TAG_EP_MASK GENMASK(3, 2) -#define GLBL2_PCIE_RQ0_TAG_FL_MASK GENMASK(1, 0) -#define QDMA_CPM4_GLBL2_DBG_PCIE_RQ1_ADDR 0x1BC -#define GLBL2_PCIE_RQ1_RSVD_1_MASK GENMASK(31, 17) -#define GLBL2_PCIE_RQ1_WTLP_REQ_MASK BIT(16) -#define GLBL2_PCIE_RQ1_WTLP_HEADER_FIFO_FL_MASK BIT(15) -#define GLBL2_PCIE_RQ1_WTLP_HEADER_FIFO_EP_MASK BIT(14) -#define GLBL2_PCIE_RQ1_RQ_FIFO_EP_MASK BIT(13) -#define GLBL2_PCIE_RQ1_RQ_FIFO_FL_MASK BIT(12) -#define GLBL2_PCIE_RQ1_TLPSM_MASK GENMASK(11, 9) -#define GLBL2_PCIE_RQ1_TLPSM512_MASK GENMASK(8, 6) -#define GLBL2_PCIE_RQ1_RREQ0_RCB_OK_MASK BIT(5) -#define GLBL2_PCIE_RQ1_RREQ0_SLV_MASK BIT(4) -#define GLBL2_PCIE_RQ1_RREQ0_VLD_MASK BIT(3) -#define GLBL2_PCIE_RQ1_RREQ1_RCB_OK_MASK BIT(2) -#define GLBL2_PCIE_RQ1_RREQ1_SLV_MASK BIT(1) -#define GLBL2_PCIE_RQ1_RREQ1_VLD_MASK BIT(0) -#define QDMA_CPM4_GLBL2_DBG_AXIMM_WR0_ADDR 0x1C0 -#define GLBL2_AXIMM_WR0_RSVD_1_MASK GENMASK(31, 27) -#define GLBL2_AXIMM_WR0_WR_REQ_MASK BIT(26) -#define GLBL2_AXIMM_WR0_WR_CHN_MASK GENMASK(25, 23) -#define GLBL2_AXIMM_WR0_WTLP_DATA_FIFO_EP_MASK BIT(22) -#define GLBL2_AXIMM_WR0_WPL_FIFO_EP_MASK BIT(21) -#define GLBL2_AXIMM_WR0_BRSP_CLAIM_CHN_MASK GENMASK(20, 18) -#define GLBL2_AXIMM_WR0_WRREQ_CNT_MASK GENMASK(17, 12) -#define GLBL2_AXIMM_WR0_BID_MASK GENMASK(11, 9) -#define GLBL2_AXIMM_WR0_BVALID_MASK BIT(8) -#define GLBL2_AXIMM_WR0_BREADY_MASK BIT(7) -#define GLBL2_AXIMM_WR0_WVALID_MASK BIT(6) -#define GLBL2_AXIMM_WR0_WREADY_MASK BIT(5) -#define GLBL2_AXIMM_WR0_AWID_MASK GENMASK(4, 2) -#define GLBL2_AXIMM_WR0_AWVALID_MASK BIT(1) -#define GLBL2_AXIMM_WR0_AWREADY_MASK BIT(0) -#define QDMA_CPM4_GLBL2_DBG_AXIMM_WR1_ADDR 0x1C4 -#define GLBL2_AXIMM_WR1_RSVD_1_MASK GENMASK(31, 30) -#define GLBL2_AXIMM_WR1_BRSP_CNT4_MASK GENMASK(29, 24) -#define GLBL2_AXIMM_WR1_BRSP_CNT3_MASK GENMASK(23, 18) -#define GLBL2_AXIMM_WR1_BRSP_CNT2_MASK GENMASK(17, 12) -#define GLBL2_AXIMM_WR1_BRSP_CNT1_MASK GENMASK(11, 6) -#define GLBL2_AXIMM_WR1_BRSP_CNT0_MASK GENMASK(5, 0) -#define QDMA_CPM4_GLBL2_DBG_AXIMM_RD0_ADDR 0x1C8 -#define GLBL2_AXIMM_RD0_RSVD_1_MASK GENMASK(31, 23) -#define GLBL2_AXIMM_RD0_PND_CNT_MASK GENMASK(22, 17) -#define GLBL2_AXIMM_RD0_RD_CHNL_MASK GENMASK(16, 14) -#define GLBL2_AXIMM_RD0_RD_REQ_MASK BIT(13) -#define GLBL2_AXIMM_RD0_RRSP_CLAIM_CHNL_MASK GENMASK(12, 10) -#define GLBL2_AXIMM_RD0_RID_MASK GENMASK(9, 7) -#define GLBL2_AXIMM_RD0_RVALID_MASK BIT(6) -#define GLBL2_AXIMM_RD0_RREADY_MASK BIT(5) -#define GLBL2_AXIMM_RD0_ARID_MASK GENMASK(4, 2) -#define GLBL2_AXIMM_RD0_ARVALID_MASK BIT(1) -#define GLBL2_AXIMM_RD0_ARREADY_MASK BIT(0) -#define QDMA_CPM4_GLBL2_DBG_AXIMM_RD1_ADDR 0x1CC -#define GLBL2_AXIMM_RD1_RSVD_1_MASK GENMASK(31, 30) -#define GLBL2_AXIMM_RD1_RRSP_CNT4_MASK GENMASK(29, 24) -#define GLBL2_AXIMM_RD1_RRSP_CNT3_MASK GENMASK(23, 18) -#define GLBL2_AXIMM_RD1_RRSP_CNT2_MASK GENMASK(17, 12) -#define GLBL2_AXIMM_RD1_RRSP_CNT1_MASK GENMASK(11, 6) -#define GLBL2_AXIMM_RD1_RRSP_CNT0_MASK GENMASK(5, 0) -#define QDMA_CPM4_GLBL_RNG_SZ_1_ADDR 0x204 -#define GLBL_RNG_SZ_1_RSVD_1_MASK GENMASK(31, 16) -#define GLBL_RNG_SZ_1_RING_SIZE_MASK GENMASK(15, 0) -#define QDMA_CPM4_GLBL_RNG_SZ_2_ADDR 0x208 -#define GLBL_RNG_SZ_2_RSVD_1_MASK GENMASK(31, 16) -#define GLBL_RNG_SZ_2_RING_SIZE_MASK GENMASK(15, 0) -#define QDMA_CPM4_GLBL_RNG_SZ_3_ADDR 0x20C -#define GLBL_RNG_SZ_3_RSVD_1_MASK GENMASK(31, 16) -#define GLBL_RNG_SZ_3_RING_SIZE_MASK GENMASK(15, 0) -#define QDMA_CPM4_GLBL_RNG_SZ_4_ADDR 0x210 -#define GLBL_RNG_SZ_4_RSVD_1_MASK GENMASK(31, 16) -#define GLBL_RNG_SZ_4_RING_SIZE_MASK GENMASK(15, 0) -#define QDMA_CPM4_GLBL_RNG_SZ_5_ADDR 0x214 -#define GLBL_RNG_SZ_5_RSVD_1_MASK GENMASK(31, 16) -#define GLBL_RNG_SZ_5_RING_SIZE_MASK GENMASK(15, 0) -#define QDMA_CPM4_GLBL_RNG_SZ_6_ADDR 0x218 -#define GLBL_RNG_SZ_6_RSVD_1_MASK GENMASK(31, 16) -#define GLBL_RNG_SZ_6_RING_SIZE_MASK GENMASK(15, 0) -#define QDMA_CPM4_GLBL_RNG_SZ_7_ADDR 0x21C -#define GLBL_RNG_SZ_7_RSVD_1_MASK GENMASK(31, 16) -#define GLBL_RNG_SZ_7_RING_SIZE_MASK GENMASK(15, 0) -#define QDMA_CPM4_GLBL_RNG_SZ_8_ADDR 0x220 -#define GLBL_RNG_SZ_8_RSVD_1_MASK GENMASK(31, 16) -#define GLBL_RNG_SZ_8_RING_SIZE_MASK GENMASK(15, 0) -#define QDMA_CPM4_GLBL_RNG_SZ_9_ADDR 0x224 -#define GLBL_RNG_SZ_9_RSVD_1_MASK GENMASK(31, 16) -#define GLBL_RNG_SZ_9_RING_SIZE_MASK GENMASK(15, 0) -#define QDMA_CPM4_GLBL_RNG_SZ_A_ADDR 0x228 -#define GLBL_RNG_SZ_A_RSVD_1_MASK GENMASK(31, 16) -#define GLBL_RNG_SZ_A_RING_SIZE_MASK GENMASK(15, 0) -#define QDMA_CPM4_GLBL_RNG_SZ_B_ADDR 0x22C -#define GLBL_RNG_SZ_B_RSVD_1_MASK GENMASK(31, 16) -#define GLBL_RNG_SZ_B_RING_SIZE_MASK GENMASK(15, 0) -#define QDMA_CPM4_GLBL_RNG_SZ_C_ADDR 0x230 -#define GLBL_RNG_SZ_C_RSVD_1_MASK GENMASK(31, 16) -#define GLBL_RNG_SZ_C_RING_SIZE_MASK GENMASK(15, 0) -#define QDMA_CPM4_GLBL_RNG_SZ_D_ADDR 0x234 -#define GLBL_RNG_SZ_D_RSVD_1_MASK GENMASK(31, 16) -#define GLBL_RNG_SZ_D_RING_SIZE_MASK GENMASK(15, 0) -#define QDMA_CPM4_GLBL_RNG_SZ_E_ADDR 0x238 -#define GLBL_RNG_SZ_E_RSVD_1_MASK GENMASK(31, 16) -#define GLBL_RNG_SZ_E_RING_SIZE_MASK GENMASK(15, 0) -#define QDMA_CPM4_GLBL_RNG_SZ_F_ADDR 0x23C -#define GLBL_RNG_SZ_F_RSVD_1_MASK GENMASK(31, 16) -#define GLBL_RNG_SZ_F_RING_SIZE_MASK GENMASK(15, 0) -#define QDMA_CPM4_GLBL_RNG_SZ_10_ADDR 0x240 -#define GLBL_RNG_SZ_10_RSVD_1_MASK GENMASK(31, 16) -#define GLBL_RNG_SZ_10_RING_SIZE_MASK GENMASK(15, 0) -#define QDMA_CPM4_GLBL_ERR_STAT_ADDR 0x248 -#define GLBL_ERR_STAT_RSVD_1_MASK GENMASK(31, 12) -#define GLBL_ERR_STAT_ERR_H2C_ST_MASK BIT(11) -#define GLBL_ERR_STAT_ERR_BDG_MASK BIT(10) -#define GLBL_ERR_STAT_IND_CTXT_CMD_ERR_MASK BIT(9) -#define GLBL_ERR_STAT_ERR_C2H_ST_MASK BIT(8) -#define GLBL_ERR_STAT_ERR_C2H_MM_1_MASK BIT(7) -#define GLBL_ERR_STAT_ERR_C2H_MM_0_MASK BIT(6) -#define GLBL_ERR_STAT_ERR_H2C_MM_1_MASK BIT(5) -#define GLBL_ERR_STAT_ERR_H2C_MM_0_MASK BIT(4) -#define GLBL_ERR_STAT_ERR_TRQ_MASK BIT(3) -#define GLBL_ERR_STAT_ERR_DSC_MASK BIT(2) -#define GLBL_ERR_STAT_ERR_RAM_DBE_MASK BIT(1) -#define GLBL_ERR_STAT_ERR_RAM_SBE_MASK BIT(0) -#define QDMA_CPM4_GLBL_ERR_MASK_ADDR 0x24C -#define GLBL_ERR_RSVD_1_MASK GENMASK(31, 9) -#define GLBL_ERR_MASK GENMASK(8, 0) -#define QDMA_CPM4_GLBL_DSC_CFG_ADDR 0x250 -#define GLBL_DSC_CFG_RSVD_1_MASK GENMASK(31, 10) -#define GLBL_DSC_CFG_UNC_OVR_COR_MASK BIT(9) -#define GLBL_DSC_CFG_CTXT_FER_DIS_MASK BIT(8) -#define GLBL_DSC_CFG_RSVD_2_MASK GENMASK(7, 6) -#define GLBL_DSC_CFG_MAXFETCH_MASK GENMASK(5, 3) -#define GLBL_DSC_CFG_WB_ACC_INT_MASK GENMASK(2, 0) -#define QDMA_CPM4_GLBL_DSC_ERR_STS_ADDR 0x254 -#define GLBL_DSC_ERR_STS_RSVD_1_MASK GENMASK(31, 25) -#define GLBL_DSC_ERR_STS_SBE_MASK BIT(24) -#define GLBL_DSC_ERR_STS_DBE_MASK BIT(23) -#define GLBL_DSC_ERR_STS_RQ_CANCEL_MASK BIT(22) -#define GLBL_DSC_ERR_STS_DSC_MASK BIT(21) -#define GLBL_DSC_ERR_STS_DMA_MASK BIT(20) -#define GLBL_DSC_ERR_STS_FLR_CANCEL_MASK BIT(19) -#define GLBL_DSC_ERR_STS_RSVD_2_MASK GENMASK(18, 17) -#define GLBL_DSC_ERR_STS_DAT_POISON_MASK BIT(16) -#define GLBL_DSC_ERR_STS_TIMEOUT_MASK BIT(9) -#define GLBL_DSC_ERR_STS_FLR_MASK BIT(5) -#define GLBL_DSC_ERR_STS_TAG_MASK BIT(4) -#define GLBL_DSC_ERR_STS_ADDR_MASK BIT(3) -#define GLBL_DSC_ERR_STS_PARAM_MASK BIT(2) -#define GLBL_DSC_ERR_STS_UR_CA_MASK BIT(1) -#define GLBL_DSC_ERR_STS_POISON_MASK BIT(0) -#define QDMA_CPM4_GLBL_DSC_ERR_MSK_ADDR 0x258 -#define GLBL_DSC_ERR_MSK_MASK GENMASK(8, 0) -#define QDMA_CPM4_GLBL_DSC_ERR_LOG0_ADDR 0x25C -#define GLBL_DSC_ERR_LOG0_VALID_MASK BIT(31) -#define GLBL_DSC_ERR_LOG0_RSVD_1_MASK GENMASK(30, 29) -#define GLBL_DSC_ERR_LOG0_QID_MASK GENMASK(28, 17) -#define GLBL_DSC_ERR_LOG0_SEL_MASK BIT(16) -#define GLBL_DSC_ERR_LOG0_CIDX_MASK GENMASK(15, 0) -#define QDMA_CPM4_GLBL_DSC_ERR_LOG1_ADDR 0x260 -#define GLBL_DSC_ERR_LOG1_RSVD_1_MASK GENMASK(31, 9) -#define GLBL_DSC_ERR_LOG1_SUB_TYPE_MASK GENMASK(8, 5) -#define GLBL_DSC_ERR_LOG1_ERR_TYPE_MASK GENMASK(4, 0) -#define QDMA_CPM4_GLBL_TRQ_ERR_STS_ADDR 0x264 -#define GLBL_TRQ_ERR_STS_RSVD_1_MASK GENMASK(31, 4) -#define GLBL_TRQ_ERR_STS_TCP_TIMEOUT_MASK BIT(3) -#define GLBL_TRQ_ERR_STS_VF_ACCESS_ERR_MASK BIT(2) -#define GLBL_TRQ_ERR_STS_QID_RANGE_MASK BIT(1) -#define GLBL_TRQ_ERR_STS_UNMAPPED_MASK BIT(0) -#define QDMA_CPM4_GLBL_TRQ_ERR_MSK_ADDR 0x268 -#define GLBL_TRQ_ERR_MSK_MASK GENMASK(31, 0) -#define QDMA_CPM4_GLBL_TRQ_ERR_LOG_ADDR 0x26C -#define GLBL_TRQ_ERR_LOG_RSVD_1_MASK GENMASK(31, 28) -#define GLBL_TRQ_ERR_LOG_TARGET_MASK GENMASK(27, 24) -#define GLBL_TRQ_ERR_LOG_FUNC_MASK GENMASK(23, 16) -#define GLBL_TRQ_ERR_LOG_ADDRESS_MASK GENMASK(15, 0) -#define QDMA_CPM4_GLBL_DSC_DBG_DAT0_ADDR 0x270 -#define GLBL_DSC_DAT0_RSVD_1_MASK GENMASK(31, 30) -#define GLBL_DSC_DAT0_CTXT_ARB_DIR_MASK BIT(29) -#define GLBL_DSC_DAT0_CTXT_ARB_QID_MASK GENMASK(28, 17) -#define GLBL_DSC_DAT0_CTXT_ARB_REQ_MASK GENMASK(16, 12) -#define GLBL_DSC_DAT0_IRQ_FIFO_FL_MASK BIT(11) -#define GLBL_DSC_DAT0_TMSTALL_MASK BIT(10) -#define GLBL_DSC_DAT0_RRQ_STALL_MASK GENMASK(9, 8) -#define GLBL_DSC_DAT0_RCP_FIFO_SPC_STALL_MASK GENMASK(7, 6) -#define GLBL_DSC_DAT0_RRQ_FIFO_SPC_STALL_MASK GENMASK(5, 4) -#define GLBL_DSC_DAT0_FAB_MRKR_RSP_STALL_MASK GENMASK(3, 2) -#define GLBL_DSC_DAT0_DSC_OUT_STALL_MASK GENMASK(1, 0) -#define QDMA_CPM4_GLBL_DSC_DBG_DAT1_ADDR 0x274 -#define GLBL_DSC_DAT1_RSVD_1_MASK GENMASK(31, 28) -#define GLBL_DSC_DAT1_EVT_SPC_C2H_MASK GENMASK(27, 22) -#define GLBL_DSC_DAT1_EVT_SP_H2C_MASK GENMASK(21, 16) -#define GLBL_DSC_DAT1_DSC_SPC_C2H_MASK GENMASK(15, 8) -#define GLBL_DSC_DAT1_DSC_SPC_H2C_MASK GENMASK(7, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_0_ADDR 0x400 -#define TRQ_SEL_FMAP_0_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_0_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_0_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_1_ADDR 0x404 -#define TRQ_SEL_FMAP_1_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_1_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_1_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_2_ADDR 0x408 -#define TRQ_SEL_FMAP_2_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_2_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_2_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_3_ADDR 0x40C -#define TRQ_SEL_FMAP_3_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_3_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_3_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_4_ADDR 0x410 -#define TRQ_SEL_FMAP_4_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_4_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_4_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_5_ADDR 0x414 -#define TRQ_SEL_FMAP_5_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_5_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_5_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_6_ADDR 0x418 -#define TRQ_SEL_FMAP_6_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_6_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_6_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_7_ADDR 0x41C -#define TRQ_SEL_FMAP_7_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_7_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_7_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_8_ADDR 0x420 -#define TRQ_SEL_FMAP_8_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_8_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_8_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_9_ADDR 0x424 -#define TRQ_SEL_FMAP_9_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_9_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_9_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_A_ADDR 0x428 -#define TRQ_SEL_FMAP_A_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_A_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_A_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_B_ADDR 0x42C -#define TRQ_SEL_FMAP_B_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_B_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_B_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_D_ADDR 0x430 -#define TRQ_SEL_FMAP_D_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_D_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_D_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_E_ADDR 0x434 -#define TRQ_SEL_FMAP_E_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_E_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_E_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_F_ADDR 0x438 -#define TRQ_SEL_FMAP_F_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_F_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_F_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_10_ADDR 0x43C -#define TRQ_SEL_FMAP_10_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_10_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_10_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_11_ADDR 0x440 -#define TRQ_SEL_FMAP_11_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_11_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_11_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_12_ADDR 0x444 -#define TRQ_SEL_FMAP_12_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_12_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_12_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_13_ADDR 0x448 -#define TRQ_SEL_FMAP_13_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_13_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_13_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_14_ADDR 0x44C -#define TRQ_SEL_FMAP_14_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_14_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_14_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_15_ADDR 0x450 -#define TRQ_SEL_FMAP_15_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_15_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_15_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_16_ADDR 0x454 -#define TRQ_SEL_FMAP_16_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_16_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_16_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_17_ADDR 0x458 -#define TRQ_SEL_FMAP_17_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_17_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_17_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_18_ADDR 0x45C -#define TRQ_SEL_FMAP_18_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_18_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_18_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_19_ADDR 0x460 -#define TRQ_SEL_FMAP_19_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_19_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_19_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_1A_ADDR 0x464 -#define TRQ_SEL_FMAP_1A_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_1A_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_1A_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_1B_ADDR 0x468 -#define TRQ_SEL_FMAP_1B_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_1B_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_1B_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_1C_ADDR 0x46C -#define TRQ_SEL_FMAP_1C_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_1C_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_1C_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_1D_ADDR 0x470 -#define TRQ_SEL_FMAP_1D_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_1D_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_1D_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_1E_ADDR 0x474 -#define TRQ_SEL_FMAP_1E_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_1E_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_1E_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_1F_ADDR 0x478 -#define TRQ_SEL_FMAP_1F_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_1F_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_1F_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_20_ADDR 0x47C -#define TRQ_SEL_FMAP_20_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_20_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_20_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_21_ADDR 0x480 -#define TRQ_SEL_FMAP_21_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_21_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_21_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_22_ADDR 0x484 -#define TRQ_SEL_FMAP_22_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_22_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_22_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_23_ADDR 0x488 -#define TRQ_SEL_FMAP_23_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_23_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_23_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_24_ADDR 0x48C -#define TRQ_SEL_FMAP_24_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_24_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_24_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_25_ADDR 0x490 -#define TRQ_SEL_FMAP_25_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_25_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_25_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_26_ADDR 0x494 -#define TRQ_SEL_FMAP_26_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_26_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_26_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_27_ADDR 0x498 -#define TRQ_SEL_FMAP_27_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_27_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_27_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_28_ADDR 0x49C -#define TRQ_SEL_FMAP_28_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_28_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_28_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_29_ADDR 0x4A0 -#define TRQ_SEL_FMAP_29_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_29_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_29_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_2A_ADDR 0x4A4 -#define TRQ_SEL_FMAP_2A_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_2A_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_2A_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_2B_ADDR 0x4A8 -#define TRQ_SEL_FMAP_2B_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_2B_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_2B_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_2C_ADDR 0x4AC -#define TRQ_SEL_FMAP_2C_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_2C_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_2C_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_2D_ADDR 0x4B0 -#define TRQ_SEL_FMAP_2D_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_2D_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_2D_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_2E_ADDR 0x4B4 -#define TRQ_SEL_FMAP_2E_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_2E_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_2E_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_2F_ADDR 0x4B8 -#define TRQ_SEL_FMAP_2F_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_2F_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_2F_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_30_ADDR 0x4BC -#define TRQ_SEL_FMAP_30_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_30_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_30_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_31_ADDR 0x4D0 -#define TRQ_SEL_FMAP_31_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_31_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_31_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_32_ADDR 0x4D4 -#define TRQ_SEL_FMAP_32_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_32_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_32_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_33_ADDR 0x4D8 -#define TRQ_SEL_FMAP_33_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_33_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_33_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_34_ADDR 0x4DC -#define TRQ_SEL_FMAP_34_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_34_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_34_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_35_ADDR 0x4E0 -#define TRQ_SEL_FMAP_35_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_35_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_35_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_36_ADDR 0x4E4 -#define TRQ_SEL_FMAP_36_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_36_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_36_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_37_ADDR 0x4E8 -#define TRQ_SEL_FMAP_37_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_37_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_37_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_38_ADDR 0x4EC -#define TRQ_SEL_FMAP_38_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_38_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_38_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_39_ADDR 0x4F0 -#define TRQ_SEL_FMAP_39_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_39_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_39_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_3A_ADDR 0x4F4 -#define TRQ_SEL_FMAP_3A_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_3A_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_3A_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_3B_ADDR 0x4F8 -#define TRQ_SEL_FMAP_3B_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_3B_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_3B_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_3C_ADDR 0x4FC -#define TRQ_SEL_FMAP_3C_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_3C_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_3C_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_3D_ADDR 0x500 -#define TRQ_SEL_FMAP_3D_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_3D_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_3D_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_3E_ADDR 0x504 -#define TRQ_SEL_FMAP_3E_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_3E_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_3E_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_3F_ADDR 0x508 -#define TRQ_SEL_FMAP_3F_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_3F_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_3F_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_40_ADDR 0x50C -#define TRQ_SEL_FMAP_40_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_40_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_40_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_41_ADDR 0x510 -#define TRQ_SEL_FMAP_41_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_41_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_41_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_42_ADDR 0x514 -#define TRQ_SEL_FMAP_42_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_42_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_42_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_43_ADDR 0x518 -#define TRQ_SEL_FMAP_43_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_43_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_43_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_44_ADDR 0x51C -#define TRQ_SEL_FMAP_44_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_44_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_44_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_45_ADDR 0x520 -#define TRQ_SEL_FMAP_45_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_45_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_45_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_46_ADDR 0x524 -#define TRQ_SEL_FMAP_46_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_46_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_46_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_47_ADDR 0x528 -#define TRQ_SEL_FMAP_47_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_47_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_47_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_48_ADDR 0x52C -#define TRQ_SEL_FMAP_48_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_48_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_48_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_49_ADDR 0x530 -#define TRQ_SEL_FMAP_49_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_49_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_49_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_4A_ADDR 0x534 -#define TRQ_SEL_FMAP_4A_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_4A_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_4A_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_4B_ADDR 0x538 -#define TRQ_SEL_FMAP_4B_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_4B_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_4B_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_4C_ADDR 0x53C -#define TRQ_SEL_FMAP_4C_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_4C_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_4C_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_4D_ADDR 0x540 -#define TRQ_SEL_FMAP_4D_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_4D_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_4D_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_4E_ADDR 0x544 -#define TRQ_SEL_FMAP_4E_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_4E_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_4E_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_4F_ADDR 0x548 -#define TRQ_SEL_FMAP_4F_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_4F_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_4F_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_50_ADDR 0x54C -#define TRQ_SEL_FMAP_50_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_50_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_50_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_51_ADDR 0x550 -#define TRQ_SEL_FMAP_51_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_51_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_51_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_52_ADDR 0x554 -#define TRQ_SEL_FMAP_52_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_52_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_52_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_53_ADDR 0x558 -#define TRQ_SEL_FMAP_53_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_53_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_53_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_54_ADDR 0x55C -#define TRQ_SEL_FMAP_54_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_54_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_54_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_55_ADDR 0x560 -#define TRQ_SEL_FMAP_55_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_55_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_55_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_56_ADDR 0x564 -#define TRQ_SEL_FMAP_56_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_56_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_56_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_57_ADDR 0x568 -#define TRQ_SEL_FMAP_57_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_57_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_57_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_58_ADDR 0x56C -#define TRQ_SEL_FMAP_58_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_58_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_58_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_59_ADDR 0x570 -#define TRQ_SEL_FMAP_59_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_59_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_59_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_5A_ADDR 0x574 -#define TRQ_SEL_FMAP_5A_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_5A_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_5A_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_5B_ADDR 0x578 -#define TRQ_SEL_FMAP_5B_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_5B_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_5B_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_5C_ADDR 0x57C -#define TRQ_SEL_FMAP_5C_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_5C_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_5C_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_5D_ADDR 0x580 -#define TRQ_SEL_FMAP_5D_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_5D_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_5D_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_5E_ADDR 0x584 -#define TRQ_SEL_FMAP_5E_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_5E_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_5E_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_5F_ADDR 0x588 -#define TRQ_SEL_FMAP_5F_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_5F_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_5F_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_60_ADDR 0x58C -#define TRQ_SEL_FMAP_60_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_60_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_60_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_61_ADDR 0x590 -#define TRQ_SEL_FMAP_61_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_61_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_61_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_62_ADDR 0x594 -#define TRQ_SEL_FMAP_62_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_62_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_62_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_63_ADDR 0x598 -#define TRQ_SEL_FMAP_63_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_63_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_63_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_64_ADDR 0x59C -#define TRQ_SEL_FMAP_64_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_64_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_64_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_65_ADDR 0x5A0 -#define TRQ_SEL_FMAP_65_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_65_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_65_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_66_ADDR 0x5A4 -#define TRQ_SEL_FMAP_66_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_66_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_66_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_67_ADDR 0x5A8 -#define TRQ_SEL_FMAP_67_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_67_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_67_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_68_ADDR 0x5AC -#define TRQ_SEL_FMAP_68_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_68_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_68_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_69_ADDR 0x5B0 -#define TRQ_SEL_FMAP_69_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_69_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_69_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_6A_ADDR 0x5B4 -#define TRQ_SEL_FMAP_6A_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_6A_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_6A_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_6B_ADDR 0x5B8 -#define TRQ_SEL_FMAP_6B_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_6B_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_6B_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_6C_ADDR 0x5BC -#define TRQ_SEL_FMAP_6C_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_6C_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_6C_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_6D_ADDR 0x5C0 -#define TRQ_SEL_FMAP_6D_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_6D_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_6D_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_6E_ADDR 0x5C4 -#define TRQ_SEL_FMAP_6E_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_6E_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_6E_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_6F_ADDR 0x5C8 -#define TRQ_SEL_FMAP_6F_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_6F_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_6F_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_70_ADDR 0x5CC -#define TRQ_SEL_FMAP_70_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_70_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_70_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_71_ADDR 0x5D0 -#define TRQ_SEL_FMAP_71_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_71_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_71_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_72_ADDR 0x5D4 -#define TRQ_SEL_FMAP_72_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_72_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_72_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_73_ADDR 0x5D8 -#define TRQ_SEL_FMAP_73_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_73_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_73_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_74_ADDR 0x5DC -#define TRQ_SEL_FMAP_74_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_74_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_74_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_75_ADDR 0x5E0 -#define TRQ_SEL_FMAP_75_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_75_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_75_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_76_ADDR 0x5E4 -#define TRQ_SEL_FMAP_76_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_76_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_76_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_77_ADDR 0x5E8 -#define TRQ_SEL_FMAP_77_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_77_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_77_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_78_ADDR 0x5EC -#define TRQ_SEL_FMAP_78_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_78_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_78_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_79_ADDR 0x5F0 -#define TRQ_SEL_FMAP_79_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_79_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_79_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_7A_ADDR 0x5F4 -#define TRQ_SEL_FMAP_7A_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_7A_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_7A_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_7B_ADDR 0x5F8 -#define TRQ_SEL_FMAP_7B_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_7B_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_7B_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_7C_ADDR 0x5FC -#define TRQ_SEL_FMAP_7C_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_7C_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_7C_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_7D_ADDR 0x600 -#define TRQ_SEL_FMAP_7D_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_7D_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_7D_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_7E_ADDR 0x604 -#define TRQ_SEL_FMAP_7E_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_7E_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_7E_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_7F_ADDR 0x608 -#define TRQ_SEL_FMAP_7F_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_7F_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_7F_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_80_ADDR 0x60C -#define TRQ_SEL_FMAP_80_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_80_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_80_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_81_ADDR 0x610 -#define TRQ_SEL_FMAP_81_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_81_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_81_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_82_ADDR 0x614 -#define TRQ_SEL_FMAP_82_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_82_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_82_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_83_ADDR 0x618 -#define TRQ_SEL_FMAP_83_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_83_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_83_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_84_ADDR 0x61C -#define TRQ_SEL_FMAP_84_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_84_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_84_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_85_ADDR 0x620 -#define TRQ_SEL_FMAP_85_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_85_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_85_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_86_ADDR 0x624 -#define TRQ_SEL_FMAP_86_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_86_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_86_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_87_ADDR 0x628 -#define TRQ_SEL_FMAP_87_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_87_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_87_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_88_ADDR 0x62C -#define TRQ_SEL_FMAP_88_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_88_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_88_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_89_ADDR 0x630 -#define TRQ_SEL_FMAP_89_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_89_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_89_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_8A_ADDR 0x634 -#define TRQ_SEL_FMAP_8A_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_8A_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_8A_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_8B_ADDR 0x638 -#define TRQ_SEL_FMAP_8B_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_8B_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_8B_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_8C_ADDR 0x63C -#define TRQ_SEL_FMAP_8C_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_8C_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_8C_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_8D_ADDR 0x640 -#define TRQ_SEL_FMAP_8D_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_8D_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_8D_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_8E_ADDR 0x644 -#define TRQ_SEL_FMAP_8E_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_8E_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_8E_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_8F_ADDR 0x648 -#define TRQ_SEL_FMAP_8F_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_8F_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_8F_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_90_ADDR 0x64C -#define TRQ_SEL_FMAP_90_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_90_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_90_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_91_ADDR 0x650 -#define TRQ_SEL_FMAP_91_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_91_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_91_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_92_ADDR 0x654 -#define TRQ_SEL_FMAP_92_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_92_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_92_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_93_ADDR 0x658 -#define TRQ_SEL_FMAP_93_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_93_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_93_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_94_ADDR 0x65C -#define TRQ_SEL_FMAP_94_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_94_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_94_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_95_ADDR 0x660 -#define TRQ_SEL_FMAP_95_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_95_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_95_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_96_ADDR 0x664 -#define TRQ_SEL_FMAP_96_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_96_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_96_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_97_ADDR 0x668 -#define TRQ_SEL_FMAP_97_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_97_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_97_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_98_ADDR 0x66C -#define TRQ_SEL_FMAP_98_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_98_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_98_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_99_ADDR 0x670 -#define TRQ_SEL_FMAP_99_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_99_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_99_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_9A_ADDR 0x674 -#define TRQ_SEL_FMAP_9A_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_9A_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_9A_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_9B_ADDR 0x678 -#define TRQ_SEL_FMAP_9B_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_9B_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_9B_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_9C_ADDR 0x67C -#define TRQ_SEL_FMAP_9C_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_9C_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_9C_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_9D_ADDR 0x680 -#define TRQ_SEL_FMAP_9D_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_9D_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_9D_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_9E_ADDR 0x684 -#define TRQ_SEL_FMAP_9E_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_9E_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_9E_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_9F_ADDR 0x688 -#define TRQ_SEL_FMAP_9F_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_9F_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_9F_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_A0_ADDR 0x68C -#define TRQ_SEL_FMAP_A0_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_A0_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_A0_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_A1_ADDR 0x690 -#define TRQ_SEL_FMAP_A1_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_A1_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_A1_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_A2_ADDR 0x694 -#define TRQ_SEL_FMAP_A2_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_A2_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_A2_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_A3_ADDR 0x698 -#define TRQ_SEL_FMAP_A3_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_A3_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_A3_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_A4_ADDR 0x69C -#define TRQ_SEL_FMAP_A4_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_A4_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_A4_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_A5_ADDR 0x6A0 -#define TRQ_SEL_FMAP_A5_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_A5_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_A5_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_A6_ADDR 0x6A4 -#define TRQ_SEL_FMAP_A6_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_A6_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_A6_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_A7_ADDR 0x6A8 -#define TRQ_SEL_FMAP_A7_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_A7_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_A7_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_A8_ADDR 0x6AC -#define TRQ_SEL_FMAP_A8_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_A8_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_A8_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_A9_ADDR 0x6B0 -#define TRQ_SEL_FMAP_A9_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_A9_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_A9_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_AA_ADDR 0x6B4 -#define TRQ_SEL_FMAP_AA_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_AA_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_AA_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_AB_ADDR 0x6B8 -#define TRQ_SEL_FMAP_AB_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_AB_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_AB_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_AC_ADDR 0x6BC -#define TRQ_SEL_FMAP_AC_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_AC_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_AC_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_AD_ADDR 0x6D0 -#define TRQ_SEL_FMAP_AD_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_AD_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_AD_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_AE_ADDR 0x6D4 -#define TRQ_SEL_FMAP_AE_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_AE_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_AE_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_AF_ADDR 0x6D8 -#define TRQ_SEL_FMAP_AF_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_AF_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_AF_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_B0_ADDR 0x6DC -#define TRQ_SEL_FMAP_B0_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_B0_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_B0_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_B1_ADDR 0x6E0 -#define TRQ_SEL_FMAP_B1_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_B1_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_B1_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_B2_ADDR 0x6E4 -#define TRQ_SEL_FMAP_B2_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_B2_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_B2_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_B3_ADDR 0x6E8 -#define TRQ_SEL_FMAP_B3_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_B3_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_B3_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_B4_ADDR 0x6EC -#define TRQ_SEL_FMAP_B4_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_B4_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_B4_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_B5_ADDR 0x6F0 -#define TRQ_SEL_FMAP_B5_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_B5_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_B5_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_B6_ADDR 0x6F4 -#define TRQ_SEL_FMAP_B6_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_B6_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_B6_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_B7_ADDR 0x6F8 -#define TRQ_SEL_FMAP_B7_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_B7_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_B7_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_B8_ADDR 0x6FC -#define TRQ_SEL_FMAP_B8_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_B8_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_B8_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_B9_ADDR 0x700 -#define TRQ_SEL_FMAP_B9_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_B9_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_B9_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_BA_ADDR 0x704 -#define TRQ_SEL_FMAP_BA_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_BA_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_BA_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_BB_ADDR 0x708 -#define TRQ_SEL_FMAP_BB_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_BB_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_BB_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_BC_ADDR 0x70C -#define TRQ_SEL_FMAP_BC_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_BC_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_BC_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_BD_ADDR 0x710 -#define TRQ_SEL_FMAP_BD_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_BD_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_BD_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_BE_ADDR 0x714 -#define TRQ_SEL_FMAP_BE_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_BE_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_BE_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_BF_ADDR 0x718 -#define TRQ_SEL_FMAP_BF_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_BF_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_BF_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_C0_ADDR 0x71C -#define TRQ_SEL_FMAP_C0_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_C0_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_C0_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_C1_ADDR 0x720 -#define TRQ_SEL_FMAP_C1_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_C1_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_C1_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_C2_ADDR 0x734 -#define TRQ_SEL_FMAP_C2_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_C2_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_C2_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_C3_ADDR 0x748 -#define TRQ_SEL_FMAP_C3_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_C3_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_C3_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_C4_ADDR 0x74C -#define TRQ_SEL_FMAP_C4_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_C4_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_C4_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_C5_ADDR 0x750 -#define TRQ_SEL_FMAP_C5_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_C5_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_C5_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_C6_ADDR 0x754 -#define TRQ_SEL_FMAP_C6_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_C6_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_C6_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_C7_ADDR 0x758 -#define TRQ_SEL_FMAP_C7_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_C7_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_C7_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_C8_ADDR 0x75C -#define TRQ_SEL_FMAP_C8_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_C8_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_C8_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_C9_ADDR 0x760 -#define TRQ_SEL_FMAP_C9_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_C9_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_C9_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_CA_ADDR 0x764 -#define TRQ_SEL_FMAP_CA_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_CA_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_CA_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_CB_ADDR 0x768 -#define TRQ_SEL_FMAP_CB_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_CB_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_CB_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_CC_ADDR 0x76C -#define TRQ_SEL_FMAP_CC_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_CC_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_CC_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_CD_ADDR 0x770 -#define TRQ_SEL_FMAP_CD_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_CD_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_CD_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_CE_ADDR 0x774 -#define TRQ_SEL_FMAP_CE_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_CE_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_CE_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_CF_ADDR 0x778 -#define TRQ_SEL_FMAP_CF_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_CF_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_CF_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_D0_ADDR 0x77C -#define TRQ_SEL_FMAP_D0_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_D0_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_D0_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_D1_ADDR 0x780 -#define TRQ_SEL_FMAP_D1_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_D1_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_D1_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_D2_ADDR 0x784 -#define TRQ_SEL_FMAP_D2_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_D2_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_D2_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_D3_ADDR 0x788 -#define TRQ_SEL_FMAP_D3_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_D3_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_D3_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_D4_ADDR 0x78C -#define TRQ_SEL_FMAP_D4_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_D4_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_D4_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_D5_ADDR 0x790 -#define TRQ_SEL_FMAP_D5_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_D5_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_D5_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_D6_ADDR 0x794 -#define TRQ_SEL_FMAP_D6_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_D6_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_D6_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_D7_ADDR 0x798 -#define TRQ_SEL_FMAP_D7_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_D7_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_D7_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_D8_ADDR 0x79C -#define TRQ_SEL_FMAP_D8_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_D8_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_D8_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_D9_ADDR 0x7A0 -#define TRQ_SEL_FMAP_D9_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_D9_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_D9_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_DA_ADDR 0x7A4 -#define TRQ_SEL_FMAP_DA_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_DA_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_DA_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_DB_ADDR 0x7A8 -#define TRQ_SEL_FMAP_DB_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_DB_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_DB_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_DC_ADDR 0x7AC -#define TRQ_SEL_FMAP_DC_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_DC_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_DC_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_DD_ADDR 0x7B0 -#define TRQ_SEL_FMAP_DD_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_DD_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_DD_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_DE_ADDR 0x7B4 -#define TRQ_SEL_FMAP_DE_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_DE_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_DE_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_DF_ADDR 0x7B8 -#define TRQ_SEL_FMAP_DF_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_DF_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_DF_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_E0_ADDR 0x7BC -#define TRQ_SEL_FMAP_E0_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_E0_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_E0_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_E1_ADDR 0x7C0 -#define TRQ_SEL_FMAP_E1_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_E1_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_E1_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_E2_ADDR 0x7C4 -#define TRQ_SEL_FMAP_E2_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_E2_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_E2_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_E3_ADDR 0x7C8 -#define TRQ_SEL_FMAP_E3_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_E3_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_E3_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_E4_ADDR 0x7CC -#define TRQ_SEL_FMAP_E4_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_E4_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_E4_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_E5_ADDR 0x7D0 -#define TRQ_SEL_FMAP_E5_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_E5_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_E5_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_E6_ADDR 0x7D4 -#define TRQ_SEL_FMAP_E6_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_E6_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_E6_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_E7_ADDR 0x7D8 -#define TRQ_SEL_FMAP_E7_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_E7_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_E7_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_E8_ADDR 0x7DC -#define TRQ_SEL_FMAP_E8_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_E8_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_E8_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_E9_ADDR 0x7E0 -#define TRQ_SEL_FMAP_E9_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_E9_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_E9_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_EA_ADDR 0x7E4 -#define TRQ_SEL_FMAP_EA_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_EA_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_EA_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_EB_ADDR 0x7E8 -#define TRQ_SEL_FMAP_EB_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_EB_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_EB_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_EC_ADDR 0x7EC -#define TRQ_SEL_FMAP_EC_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_EC_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_EC_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_ED_ADDR 0x7F0 -#define TRQ_SEL_FMAP_ED_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_ED_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_ED_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_EE_ADDR 0x7F4 -#define TRQ_SEL_FMAP_EE_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_EE_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_EE_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_EF_ADDR 0x7F8 -#define TRQ_SEL_FMAP_EF_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_EF_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_EF_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_TRQ_SEL_FMAP_F0_ADDR 0x7FC -#define TRQ_SEL_FMAP_F0_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_F0_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_F0_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_CPM4_IND_CTXT_DATA_3_ADDR 0x804 -#define IND_CTXT_DATA_3_DATA_MASK GENMASK(31, 0) -#define QDMA_CPM4_IND_CTXT_DATA_2_ADDR 0x808 -#define IND_CTXT_DATA_2_DATA_MASK GENMASK(31, 0) -#define QDMA_CPM4_IND_CTXT_DATA_1_ADDR 0x80C -#define IND_CTXT_DATA_1_DATA_MASK GENMASK(31, 0) -#define QDMA_CPM4_IND_CTXT_DATA_0_ADDR 0x810 -#define IND_CTXT_DATA_0_DATA_MASK GENMASK(31, 0) -#define QDMA_CPM4_IND_CTXT3_ADDR 0x814 -#define IND_CTXT3_MASK GENMASK(31, 0) -#define QDMA_CPM4_IND_CTXT2_ADDR 0x818 -#define IND_CTXT2_MASK GENMASK(31, 0) -#define QDMA_CPM4_IND_CTXT1_ADDR 0x81C -#define IND_CTXT1_MASK GENMASK(31, 0) -#define QDMA_CPM4_IND_CTXT0_ADDR 0x820 -#define IND_CTXT0_MASK GENMASK(31, 0) -#define QDMA_CPM4_IND_CTXT_CMD_ADDR 0x824 -#define IND_CTXT_CMD_RSVD_1_MASK GENMASK(31, 18) -#define IND_CTXT_CMD_QID_MASK GENMASK(17, 7) -#define IND_CTXT_CMD_OP_MASK GENMASK(6, 5) -#define IND_CTXT_CMD_SET_MASK GENMASK(4, 1) -#define IND_CTXT_CMD_BUSY_MASK BIT(0) -#define QDMA_CPM4_C2H_TIMER_CNT_1_ADDR 0xA00 -#define C2H_TIMER_CNT_1_RSVD_1_MASK GENMASK(31, 8) -#define C2H_TIMER_CNT_1_MASK GENMASK(7, 0) -#define QDMA_CPM4_C2H_TIMER_CNT_2_ADDR 0xA04 -#define C2H_TIMER_CNT_2_RSVD_1_MASK GENMASK(31, 8) -#define C2H_TIMER_CNT_2_MASK GENMASK(7, 0) -#define QDMA_CPM4_C2H_TIMER_CNT_3_ADDR 0xA08 -#define C2H_TIMER_CNT_3_RSVD_1_MASK GENMASK(31, 8) -#define C2H_TIMER_CNT_3_MASK GENMASK(7, 0) -#define QDMA_CPM4_C2H_TIMER_CNT_4_ADDR 0xA0C -#define C2H_TIMER_CNT_4_RSVD_1_MASK GENMASK(31, 8) -#define C2H_TIMER_CNT_4_MASK GENMASK(7, 0) -#define QDMA_CPM4_C2H_TIMER_CNT_5_ADDR 0xA10 -#define C2H_TIMER_CNT_5_RSVD_1_MASK GENMASK(31, 8) -#define C2H_TIMER_CNT_5_MASK GENMASK(7, 0) -#define QDMA_CPM4_C2H_TIMER_CNT_6_ADDR 0xA14 -#define C2H_TIMER_CNT_6_RSVD_1_MASK GENMASK(31, 8) -#define C2H_TIMER_CNT_6_MASK GENMASK(7, 0) -#define QDMA_CPM4_C2H_TIMER_CNT_7_ADDR 0xA18 -#define C2H_TIMER_CNT_7_RSVD_1_MASK GENMASK(31, 8) -#define C2H_TIMER_CNT_7_MASK GENMASK(7, 0) -#define QDMA_CPM4_C2H_TIMER_CNT_8_ADDR 0xA1C -#define C2H_TIMER_CNT_8_RSVD_1_MASK GENMASK(31, 8) -#define C2H_TIMER_CNT_8_MASK GENMASK(7, 0) -#define QDMA_CPM4_C2H_TIMER_CNT_9_ADDR 0xA20 -#define C2H_TIMER_CNT_9_RSVD_1_MASK GENMASK(31, 8) -#define C2H_TIMER_CNT_9_MASK GENMASK(7, 0) -#define QDMA_CPM4_C2H_TIMER_CNT_A_ADDR 0xA24 -#define C2H_TIMER_CNT_A_RSVD_1_MASK GENMASK(31, 8) -#define C2H_TIMER_CNT_A_MASK GENMASK(7, 0) -#define QDMA_CPM4_C2H_TIMER_CNT_B_ADDR 0xA28 -#define C2H_TIMER_CNT_B_RSVD_1_MASK GENMASK(31, 8) -#define C2H_TIMER_CNT_B_MASK GENMASK(7, 0) -#define QDMA_CPM4_C2H_TIMER_CNT_C_ADDR 0xA2C -#define C2H_TIMER_CNT_C_RSVD_1_MASK GENMASK(31, 8) -#define C2H_TIMER_CNT_C_MASK GENMASK(7, 0) -#define QDMA_CPM4_C2H_TIMER_CNT_D_ADDR 0xA30 -#define C2H_TIMER_CNT_D_RSVD_1_MASK GENMASK(31, 8) -#define C2H_TIMER_CNT_D_MASK GENMASK(7, 0) -#define QDMA_CPM4_C2H_TIMER_CNT_E_ADDR 0xA34 -#define C2H_TIMER_CNT_E_RSVD_1_MASK GENMASK(31, 8) -#define C2H_TIMER_CNT_E_MASK GENMASK(7, 0) -#define QDMA_CPM4_C2H_TIMER_CNT_F_ADDR 0xA38 -#define C2H_TIMER_CNT_F_RSVD_1_MASK GENMASK(31, 8) -#define C2H_TIMER_CNT_F_MASK GENMASK(7, 0) -#define QDMA_CPM4_C2H_TIMER_CNT_10_ADDR 0xA3C -#define C2H_TIMER_CNT_10_RSVD_1_MASK GENMASK(31, 8) -#define C2H_TIMER_CNT_10_MASK GENMASK(7, 0) -#define QDMA_CPM4_C2H_CNT_TH_1_ADDR 0xA40 -#define C2H_CNT_TH_1_RSVD_1_MASK GENMASK(31, 8) -#define C2H_CNT_TH_1_THESHOLD_CNT_MASK GENMASK(7, 0) -#define QDMA_CPM4_C2H_CNT_TH_2_ADDR 0xA44 -#define C2H_CNT_TH_2_RSVD_1_MASK GENMASK(31, 8) -#define C2H_CNT_TH_2_THESHOLD_CNT_MASK GENMASK(7, 0) -#define QDMA_CPM4_C2H_CNT_TH_3_ADDR 0xA48 -#define C2H_CNT_TH_3_RSVD_1_MASK GENMASK(31, 8) -#define C2H_CNT_TH_3_THESHOLD_CNT_MASK GENMASK(7, 0) -#define QDMA_CPM4_C2H_CNT_TH_4_ADDR 0xA4C -#define C2H_CNT_TH_4_RSVD_1_MASK GENMASK(31, 8) -#define C2H_CNT_TH_4_THESHOLD_CNT_MASK GENMASK(7, 0) -#define QDMA_CPM4_C2H_CNT_TH_5_ADDR 0xA50 -#define C2H_CNT_TH_5_RSVD_1_MASK GENMASK(31, 8) -#define C2H_CNT_TH_5_THESHOLD_CNT_MASK GENMASK(7, 0) -#define QDMA_CPM4_C2H_CNT_TH_6_ADDR 0xA54 -#define C2H_CNT_TH_6_RSVD_1_MASK GENMASK(31, 8) -#define C2H_CNT_TH_6_THESHOLD_CNT_MASK GENMASK(7, 0) -#define QDMA_CPM4_C2H_CNT_TH_7_ADDR 0xA58 -#define C2H_CNT_TH_7_RSVD_1_MASK GENMASK(31, 8) -#define C2H_CNT_TH_7_THESHOLD_CNT_MASK GENMASK(7, 0) -#define QDMA_CPM4_C2H_CNT_TH_8_ADDR 0xA5C -#define C2H_CNT_TH_8_RSVD_1_MASK GENMASK(31, 8) -#define C2H_CNT_TH_8_THESHOLD_CNT_MASK GENMASK(7, 0) -#define QDMA_CPM4_C2H_CNT_TH_9_ADDR 0xA60 -#define C2H_CNT_TH_9_RSVD_1_MASK GENMASK(31, 8) -#define C2H_CNT_TH_9_THESHOLD_CNT_MASK GENMASK(7, 0) -#define QDMA_CPM4_C2H_CNT_TH_A_ADDR 0xA64 -#define C2H_CNT_TH_A_RSVD_1_MASK GENMASK(31, 8) -#define C2H_CNT_TH_A_THESHOLD_CNT_MASK GENMASK(7, 0) -#define QDMA_CPM4_C2H_CNT_TH_B_ADDR 0xA68 -#define C2H_CNT_TH_B_RSVD_1_MASK GENMASK(31, 8) -#define C2H_CNT_TH_B_THESHOLD_CNT_MASK GENMASK(7, 0) -#define QDMA_CPM4_C2H_CNT_TH_C_ADDR 0xA6C -#define C2H_CNT_TH_C_RSVD_1_MASK GENMASK(31, 8) -#define C2H_CNT_TH_C_THESHOLD_CNT_MASK GENMASK(7, 0) -#define QDMA_CPM4_C2H_CNT_TH_D_ADDR 0xA70 -#define C2H_CNT_TH_D_RSVD_1_MASK GENMASK(31, 8) -#define C2H_CNT_TH_D_THESHOLD_CNT_MASK GENMASK(7, 0) -#define QDMA_CPM4_C2H_CNT_TH_E_ADDR 0xA74 -#define C2H_CNT_TH_E_RSVD_1_MASK GENMASK(31, 8) -#define C2H_CNT_TH_E_THESHOLD_CNT_MASK GENMASK(7, 0) -#define QDMA_CPM4_C2H_CNT_TH_F_ADDR 0xA78 -#define C2H_CNT_TH_F_RSVD_1_MASK GENMASK(31, 8) -#define C2H_CNT_TH_F_THESHOLD_CNT_MASK GENMASK(7, 0) -#define QDMA_CPM4_C2H_CNT_TH_10_ADDR 0xA7C -#define C2H_CNT_TH_10_RSVD_1_MASK GENMASK(31, 8) -#define C2H_CNT_TH_10_THESHOLD_CNT_MASK GENMASK(7, 0) -#define QDMA_CPM4_C2H_QID2VEC_MAP_QID_ADDR 0xA80 -#define C2H_QID2VEC_MAP_QID_RSVD_1_MASK GENMASK(31, 11) -#define C2H_QID2VEC_MAP_QID_QID_MASK GENMASK(10, 0) -#define QDMA_CPM4_C2H_QID2VEC_MAP_ADDR 0xA84 -#define C2H_QID2VEC_MAP_RSVD_1_MASK GENMASK(31, 19) -#define C2H_QID2VEC_MAP_H2C_EN_COAL_MASK BIT(18) -#define C2H_QID2VEC_MAP_H2C_VECTOR_MASK GENMASK(17, 9) -#define C2H_QID2VEC_MAP_C2H_EN_COAL_MASK BIT(8) -#define C2H_QID2VEC_MAP_C2H_VECTOR_MASK GENMASK(7, 0) -#define QDMA_CPM4_C2H_STAT_S_AXIS_C2H_ACCEPTED_ADDR 0xA88 -#define C2H_STAT_S_AXIS_C2H_ACCEPTED_MASK GENMASK(31, 0) -#define QDMA_CPM4_C2H_STAT_S_AXIS_WRB_ACCEPTED_ADDR 0xA8C -#define C2H_STAT_S_AXIS_WRB_ACCEPTED_MASK GENMASK(31, 0) -#define QDMA_CPM4_C2H_STAT_DESC_RSP_PKT_ACCEPTED_ADDR 0xA90 -#define C2H_STAT_DESC_RSP_PKT_ACCEPTED_D_MASK GENMASK(31, 0) -#define QDMA_CPM4_C2H_STAT_AXIS_PKG_CMP_ADDR 0xA94 -#define C2H_STAT_AXIS_PKG_CMP_MASK GENMASK(31, 0) -#define QDMA_CPM4_C2H_STAT_DESC_RSP_ACCEPTED_ADDR 0xA98 -#define C2H_STAT_DESC_RSP_ACCEPTED_D_MASK GENMASK(31, 0) -#define QDMA_CPM4_C2H_STAT_DESC_RSP_CMP_ADDR 0xA9C -#define C2H_STAT_DESC_RSP_CMP_D_MASK GENMASK(31, 0) -#define QDMA_CPM4_C2H_STAT_WRQ_OUT_ADDR 0xAA0 -#define C2H_STAT_WRQ_OUT_MASK GENMASK(31, 0) -#define QDMA_CPM4_C2H_STAT_WPL_REN_ACCEPTED_ADDR 0xAA4 -#define C2H_STAT_WPL_REN_ACCEPTED_MASK GENMASK(31, 0) -#define QDMA_CPM4_C2H_STAT_TOTAL_WRQ_LEN_ADDR 0xAA8 -#define C2H_STAT_TOTAL_WRQ_LEN_MASK GENMASK(31, 0) -#define QDMA_CPM4_C2H_STAT_TOTAL_WPL_LEN_ADDR 0xAAC -#define C2H_STAT_TOTAL_WPL_LEN_MASK GENMASK(31, 0) -#define QDMA_CPM4_C2H_BUF_SZ_0_ADDR 0xAB0 -#define C2H_BUF_SZ_0_SIZE_MASK GENMASK(31, 0) -#define QDMA_CPM4_C2H_BUF_SZ_1_ADDR 0xAB4 -#define C2H_BUF_SZ_1_SIZE_MASK GENMASK(31, 0) -#define QDMA_CPM4_C2H_BUF_SZ_2_ADDR 0xAB8 -#define C2H_BUF_SZ_2_SIZE_MASK GENMASK(31, 0) -#define QDMA_CPM4_C2H_BUF_SZ_3_ADDR 0xABC -#define C2H_BUF_SZ_3_SIZE_MASK GENMASK(31, 0) -#define QDMA_CPM4_C2H_BUF_SZ_4_ADDR 0xAC0 -#define C2H_BUF_SZ_4_SIZE_MASK GENMASK(31, 0) -#define QDMA_CPM4_C2H_BUF_SZ_5_ADDR 0xAC4 -#define C2H_BUF_SZ_5_SIZE_MASK GENMASK(31, 0) -#define QDMA_CPM4_C2H_BUF_SZ_7_ADDR 0XAC8 -#define C2H_BUF_SZ_7_SIZE_MASK GENMASK(31, 0) -#define QDMA_CPM4_C2H_BUF_SZ_8_ADDR 0XACC -#define C2H_BUF_SZ_8_SIZE_MASK GENMASK(31, 0) -#define QDMA_CPM4_C2H_BUF_SZ_9_ADDR 0xAD0 -#define C2H_BUF_SZ_9_SIZE_MASK GENMASK(31, 0) -#define QDMA_CPM4_C2H_BUF_SZ_10_ADDR 0xAD4 -#define C2H_BUF_SZ_10_SIZE_MASK GENMASK(31, 0) -#define QDMA_CPM4_C2H_BUF_SZ_11_ADDR 0xAD8 -#define C2H_BUF_SZ_11_SIZE_MASK GENMASK(31, 0) -#define QDMA_CPM4_C2H_BUF_SZ_12_ADDR 0xAE0 -#define C2H_BUF_SZ_12_SIZE_MASK GENMASK(31, 0) -#define QDMA_CPM4_C2H_BUF_SZ_13_ADDR 0xAE4 -#define C2H_BUF_SZ_13_SIZE_MASK GENMASK(31, 0) -#define QDMA_CPM4_C2H_BUF_SZ_14_ADDR 0xAE8 -#define C2H_BUF_SZ_14_SIZE_MASK GENMASK(31, 0) -#define QDMA_CPM4_C2H_BUF_SZ_15_ADDR 0XAEC -#define C2H_BUF_SZ_15_SIZE_MASK GENMASK(31, 0) -#define QDMA_CPM4_C2H_ERR_STAT_ADDR 0xAF0 -#define C2H_ERR_STAT_RSVD_1_MASK GENMASK(31, 16) -#define C2H_ERR_STAT_WRB_PRTY_ERR_MASK BIT(15) -#define C2H_ERR_STAT_WRB_CIDX_ERR_MASK BIT(14) -#define C2H_ERR_STAT_WRB_QFULL_ERR_MASK BIT(13) -#define C2H_ERR_STAT_WRB_INV_Q_ERR_MASK BIT(12) -#define C2H_ERR_STAT_PORT_ID_BYP_IN_MISMATCH_MASK BIT(11) -#define C2H_ERR_STAT_PORT_ID_CTXT_MISMATCH_MASK BIT(10) -#define C2H_ERR_STAT_ERR_DESC_CNT_MASK BIT(9) -#define C2H_ERR_STAT_RSVD_2_MASK BIT(8) -#define C2H_ERR_STAT_MSI_INT_FAIL_MASK BIT(7) -#define C2H_ERR_STAT_ENG_WPL_DATA_PAR_ERR_MASK BIT(6) -#define C2H_ERR_STAT_RSVD_3_MASK BIT(5) -#define C2H_ERR_STAT_DESC_RSP_ERR_MASK BIT(4) -#define C2H_ERR_STAT_QID_MISMATCH_MASK BIT(3) -#define C2H_ERR_STAT_RSVD_4_MASK BIT(2) -#define C2H_ERR_STAT_LEN_MISMATCH_MASK BIT(1) -#define C2H_ERR_STAT_MTY_MISMATCH_MASK BIT(0) -#define QDMA_CPM4_C2H_ERR_MASK_ADDR 0xAF4 -#define C2H_ERR_EN_MASK GENMASK(31, 0) -#define QDMA_CPM4_C2H_FATAL_ERR_STAT_ADDR 0xAF8 -#define C2H_FATAL_ERR_STAT_RSVD_1_MASK GENMASK(31, 19) -#define C2H_FATAL_ERR_STAT_WPL_DATA_PAR_ERR_MASK BIT(18) -#define C2H_FATAL_ERR_STAT_PLD_FIFO_RAM_RDBE_MASK BIT(17) -#define C2H_FATAL_ERR_STAT_QID_FIFO_RAM_RDBE_MASK BIT(16) -#define C2H_FATAL_ERR_STAT_TUSER_FIFO_RAM_RDBE_MASK BIT(15) -#define C2H_FATAL_ERR_STAT_WRB_COAL_DATA_RAM_RDBE_MASK BIT(14) -#define C2H_FATAL_ERR_STAT_INT_QID2VEC_RAM_RDBE_MASK BIT(13) -#define C2H_FATAL_ERR_STAT_INT_CTXT_RAM_RDBE_MASK BIT(12) -#define C2H_FATAL_ERR_STAT_DESC_REQ_FIFO_RAM_RDBE_MASK BIT(11) -#define C2H_FATAL_ERR_STAT_PFCH_CTXT_RAM_RDBE_MASK BIT(10) -#define C2H_FATAL_ERR_STAT_WRB_CTXT_RAM_RDBE_MASK BIT(9) -#define C2H_FATAL_ERR_STAT_PFCH_LL_RAM_RDBE_MASK BIT(8) -#define C2H_FATAL_ERR_STAT_TIMER_FIFO_RAM_RDBE_MASK GENMASK(7, 4) -#define C2H_FATAL_ERR_STAT_QID_MISMATCH_MASK BIT(3) -#define C2H_FATAL_ERR_STAT_RSVD_2_MASK BIT(2) -#define C2H_FATAL_ERR_STAT_LEN_MISMATCH_MASK BIT(1) -#define C2H_FATAL_ERR_STAT_MTY_MISMATCH_MASK BIT(0) -#define QDMA_CPM4_C2H_FATAL_ERR_MASK_ADDR 0xAFC -#define C2H_FATAL_ERR_C2HEN_MASK GENMASK(31, 0) -#define QDMA_CPM4_C2H_FATAL_ERR_ENABLE_ADDR 0xB00 -#define C2H_FATAL_ERR_ENABLE_RSVD_1_MASK GENMASK(31, 2) -#define C2H_FATAL_ERR_ENABLE_WPL_PAR_INV_MASK BIT(1) -#define C2H_FATAL_ERR_ENABLE_WRQ_DIS_MASK BIT(0) -#define QDMA_CPM4_GLBL_ERR_INT_ADDR 0xB04 -#define GLBL_ERR_INT_RSVD_1_MASK GENMASK(31, 18) -#define GLBL_ERR_INT_ARM_MASK BIT(17) -#define GLBL_ERR_INT_EN_COAL_MASK BIT(16) -#define GLBL_ERR_INT_VEC_MASK GENMASK(15, 8) -#define GLBL_ERR_INT_FUNC_MASK GENMASK(7, 0) -#define QDMA_CPM4_C2H_PFCH_CFG_ADDR 0xB08 -#define C2H_PFCH_CFG_EVT_QCNT_TH_MASK GENMASK(31, 25) -#define C2H_PFCH_CFG_QCNT_MASK GENMASK(24, 16) -#define C2H_PFCH_CFG_NUM_MASK GENMASK(15, 8) -#define C2H_PFCH_CFG_FL_TH_MASK GENMASK(7, 0) -#define QDMA_CPM4_C2H_INT_TIMER_TICK_ADDR 0xB0C -#define C2H_INT_TIMER_TICK_MASK GENMASK(31, 0) -#define QDMA_CPM4_C2H_STAT_DESC_RSP_DROP_ACCEPTED_ADDR 0xB10 -#define C2H_STAT_DESC_RSP_DROP_ACCEPTED_D_MASK GENMASK(31, 0) -#define QDMA_CPM4_C2H_STAT_DESC_RSP_ERR_ACCEPTED_ADDR 0xB14 -#define C2H_STAT_DESC_RSP_ERR_ACCEPTED_D_MASK GENMASK(31, 0) -#define QDMA_CPM4_C2H_STAT_DESC_REQ_ADDR 0xB18 -#define C2H_STAT_DESC_REQ_MASK GENMASK(31, 0) -#define QDMA_CPM4_C2H_STAT_DBG_DMA_ENG_0_ADDR 0xB1C -#define C2H_STAT_DMA_ENG_0_RSVD_1_MASK BIT(31) -#define C2H_STAT_DMA_ENG_0_WRB_FIFO_OUT_CNT_MASK GENMASK(30, 28) -#define C2H_STAT_DMA_ENG_0_QID_FIFO_OUT_CNT_MASK GENMASK(27, 18) -#define C2H_STAT_DMA_ENG_0_PLD_FIFO_OUT_CNT_MASK GENMASK(17, 8) -#define C2H_STAT_DMA_ENG_0_WRQ_FIFO_OUT_CNT_MASK GENMASK(7, 5) -#define C2H_STAT_DMA_ENG_0_WRB_SM_CS_MASK BIT(4) -#define C2H_STAT_DMA_ENG_0_MAIN_SM_CS_MASK GENMASK(3, 0) -#define QDMA_CPM4_C2H_STAT_DBG_DMA_ENG_1_ADDR 0xB20 -#define C2H_STAT_DMA_ENG_1_RSVD_1_MASK BIT(31) -#define C2H_STAT_DMA_ENG_1_DESC_RSP_LAST_MASK BIT(30) -#define C2H_STAT_DMA_ENG_1_PLD_FIFO_IN_CNT_MASK GENMASK(29, 20) -#define C2H_STAT_DMA_ENG_1_PLD_FIFO_OUTPUT_CNT_MASK GENMASK(19, 10) -#define C2H_STAT_DMA_ENG_1_QID_FIFO_IN_CNT_MASK GENMASK(9, 0) -#define QDMA_CPM4_C2H_STAT_DBG_DMA_ENG_2_ADDR 0xB24 -#define C2H_STAT_DMA_ENG_2_RSVD_1_MASK GENMASK(31, 30) -#define C2H_STAT_DMA_ENG_2_WRB_FIFO_IN_CNT_MASK GENMASK(29, 20) -#define C2H_STAT_DMA_ENG_2_WRB_FIFO_OUTPUT_CNT_MASK GENMASK(19, 10) -#define C2H_STAT_DMA_ENG_2_QID_FIFO_OUTPUT_CNT_MASK GENMASK(9, 0) -#define QDMA_CPM4_C2H_STAT_DBG_DMA_ENG_3_ADDR 0xB28 -#define C2H_STAT_DMA_ENG_3_RSVD_1_MASK GENMASK(31, 30) -#define C2H_STAT_DMA_ENG_3_ADDR_4K_SPLIT_CNT_MASK GENMASK(29, 20) -#define C2H_STAT_DMA_ENG_3_WRQ_FIFO_IN_CNT_MASK GENMASK(19, 10) -#define C2H_STAT_DMA_ENG_3_WRQ_FIFO_OUTPUT_CNT_MASK GENMASK(9, 0) -#define QDMA_CPM4_C2H_DBG_PFCH_ERR_CTXT_ADDR 0xB2C -#define C2H_PFCH_ERR_CTXT_RSVD_1_MASK GENMASK(31, 14) -#define C2H_PFCH_ERR_CTXT_ERR_STAT_MASK BIT(13) -#define C2H_PFCH_ERR_CTXT_CMD_WR_MASK BIT(12) -#define C2H_PFCH_ERR_CTXT_QID_MASK GENMASK(11, 1) -#define C2H_PFCH_ERR_CTXT_DONE_MASK BIT(0) -#define QDMA_CPM4_C2H_FIRST_ERR_QID_ADDR 0xB30 -#define C2H_FIRST_ERR_QID_RSVD_1_MASK GENMASK(31, 21) -#define C2H_FIRST_ERR_QID_ERR_STAT_MASK GENMASK(20, 16) -#define C2H_FIRST_ERR_QID_CMD_WR_MASK GENMASK(15, 12) -#define C2H_FIRST_ERR_QID_QID_MASK GENMASK(11, 0) -#define QDMA_CPM4_STAT_NUM_WRB_IN_ADDR 0xB34 -#define STAT_NUM_WRB_IN_RSVD_1_MASK GENMASK(31, 16) -#define STAT_NUM_WRB_IN_WRB_CNT_MASK GENMASK(15, 0) -#define QDMA_CPM4_STAT_NUM_WRB_OUT_ADDR 0xB38 -#define STAT_NUM_WRB_OUT_RSVD_1_MASK GENMASK(31, 16) -#define STAT_NUM_WRB_OUT_WRB_CNT_MASK GENMASK(15, 0) -#define QDMA_CPM4_STAT_NUM_WRB_DRP_ADDR 0xB3C -#define STAT_NUM_WRB_DRP_RSVD_1_MASK GENMASK(31, 16) -#define STAT_NUM_WRB_DRP_WRB_CNT_MASK GENMASK(15, 0) -#define QDMA_CPM4_STAT_NUM_STAT_DESC_OUT_ADDR 0xB40 -#define STAT_NUM_STAT_DESC_OUT_RSVD_1_MASK GENMASK(31, 16) -#define STAT_NUM_STAT_DESC_OUT_CNT_MASK GENMASK(15, 0) -#define QDMA_CPM4_STAT_NUM_DSC_CRDT_SENT_ADDR 0xB44 -#define STAT_NUM_DSC_CRDT_SENT_RSVD_1_MASK GENMASK(31, 16) -#define STAT_NUM_DSC_CRDT_SENT_CNT_MASK GENMASK(15, 0) -#define QDMA_CPM4_STAT_NUM_FCH_DSC_RCVD_ADDR 0xB48 -#define STAT_NUM_FCH_DSC_RCVD_RSVD_1_MASK GENMASK(31, 16) -#define STAT_NUM_FCH_DSC_RCVD_DSC_CNT_MASK GENMASK(15, 0) -#define QDMA_CPM4_STAT_NUM_BYP_DSC_RCVD_ADDR 0xB4C -#define STAT_NUM_BYP_DSC_RCVD_RSVD_1_MASK GENMASK(31, 11) -#define STAT_NUM_BYP_DSC_RCVD_DSC_CNT_MASK GENMASK(10, 0) -#define QDMA_CPM4_C2H_WRB_COAL_CFG_ADDR 0xB50 -#define C2H_WRB_COAL_CFG_MAX_BUF_SZ_MASK GENMASK(31, 26) -#define C2H_WRB_COAL_CFG_TICK_VAL_MASK GENMASK(25, 14) -#define C2H_WRB_COAL_CFG_TICK_CNT_MASK GENMASK(13, 2) -#define C2H_WRB_COAL_CFG_SET_GLB_FLUSH_MASK BIT(1) -#define C2H_WRB_COAL_CFG_DONE_GLB_FLUSH_MASK BIT(0) -#define QDMA_CPM4_C2H_INTR_H2C_REQ_ADDR 0xB54 -#define C2H_INTR_H2C_REQ_RSVD_1_MASK GENMASK(31, 18) -#define C2H_INTR_H2C_REQ_CNT_MASK GENMASK(17, 0) -#define QDMA_CPM4_C2H_INTR_C2H_MM_REQ_ADDR 0xB58 -#define C2H_INTR_C2H_MM_REQ_RSVD_1_MASK GENMASK(31, 18) -#define C2H_INTR_C2H_MM_REQ_CNT_MASK GENMASK(17, 0) -#define QDMA_CPM4_C2H_INTR_ERR_INT_REQ_ADDR 0xB5C -#define C2H_INTR_ERR_INT_REQ_RSVD_1_MASK GENMASK(31, 18) -#define C2H_INTR_ERR_INT_REQ_CNT_MASK GENMASK(17, 0) -#define QDMA_CPM4_C2H_INTR_C2H_ST_REQ_ADDR 0xB60 -#define C2H_INTR_C2H_ST_REQ_RSVD_1_MASK GENMASK(31, 18) -#define C2H_INTR_C2H_ST_REQ_CNT_MASK GENMASK(17, 0) -#define QDMA_CPM4_C2H_INTR_H2C_ERR_C2H_MM_MSIX_ACK_ADDR 0xB64 -#define C2H_INTR_H2C_ERR_C2H_MM_MSIX_ACK_RSVD_1_MASK GENMASK(31, 18) -#define C2H_INTR_H2C_ERR_C2H_MM_MSIX_ACK_CNT_MASK GENMASK(17, 0) -#define QDMA_CPM4_C2H_INTR_H2C_ERR_C2H_MM_MSIX_FAIL_ADDR 0xB68 -#define C2H_INTR_H2C_ERR_C2H_MM_MSIX_FAIL_RSVD_1_MASK GENMASK(31, 18) -#define C2H_INTR_H2C_ERR_C2H_MM_MSIX_FAIL_CNT_MASK GENMASK(17, 0) -#define QDMA_CPM4_C2H_INTR_H2C_ERR_C2H_MM_MSIX_NO_MSIX_ADDR 0xB6C -#define C2H_INTR_H2C_ERR_C2H_MM_MSIX_NO_MSIX_RSVD_1_MASK GENMASK(31, 18) -#define C2H_INTR_H2C_ERR_C2H_MM_MSIX_NO_MSIX_CNT_MASK GENMASK(17, 0) -#define QDMA_CPM4_C2H_INTR_H2C_ERR_C2H_MM_CTXT_INVAL_ADDR 0xB70 -#define C2H_INTR_H2C_ERR_C2H_MM_CTXT_INVAL_RSVD_1_MASK GENMASK(31, 18) -#define C2H_INTR_H2C_ERR_C2H_MM_CTXT_INVAL_CNT_MASK GENMASK(17, 0) -#define QDMA_CPM4_C2H_INTR_C2H_ST_MSIX_ACK_ADDR 0xB74 -#define C2H_INTR_C2H_ST_MSIX_ACK_RSVD_1_MASK GENMASK(31, 18) -#define C2H_INTR_C2H_ST_MSIX_ACK_CNT_MASK GENMASK(17, 0) -#define QDMA_CPM4_C2H_INTR_C2H_ST_MSIX_FAIL_ADDR 0xB78 -#define C2H_INTR_C2H_ST_MSIX_FAIL_RSVD_1_MASK GENMASK(31, 18) -#define C2H_INTR_C2H_ST_MSIX_FAIL_CNT_MASK GENMASK(17, 0) -#define QDMA_CPM4_C2H_INTR_C2H_ST_NO_MSIX_ADDR 0xB7C -#define C2H_INTR_C2H_ST_NO_MSIX_RSVD_1_MASK GENMASK(31, 18) -#define C2H_INTR_C2H_ST_NO_MSIX_CNT_MASK GENMASK(17, 0) -#define QDMA_CPM4_C2H_INTR_C2H_ST_CTXT_INVAL_ADDR 0xB80 -#define C2H_INTR_C2H_ST_CTXT_INVAL_RSVD_1_MASK GENMASK(31, 18) -#define C2H_INTR_C2H_ST_CTXT_INVAL_CNT_MASK GENMASK(17, 0) -#define QDMA_CPM4_C2H_STAT_WR_CMP_ADDR 0xB84 -#define C2H_STAT_WR_CMP_RSVD_1_MASK GENMASK(31, 18) -#define C2H_STAT_WR_CMP_CNT_MASK GENMASK(17, 0) -#define QDMA_CPM4_C2H_STAT_DBG_DMA_ENG_4_ADDR 0xB88 -#define C2H_STAT_DMA_ENG_4_TUSER_FIFO_OUT_VLD_MASK BIT(31) -#define C2H_STAT_DMA_ENG_4_WRB_FIFO_IN_RDY_MASK BIT(30) -#define C2H_STAT_DMA_ENG_4_TUSER_FIFO_IN_CNT_MASK GENMASK(29, 20) -#define C2H_STAT_DMA_ENG_4_TUSER_FIFO_OUTPUT_CNT_MASK GENMASK(19, 10) -#define C2H_STAT_DMA_ENG_4_TUSER_FIFO_OUT_CNT_MASK GENMASK(9, 0) -#define QDMA_CPM4_C2H_STAT_DBG_DMA_ENG_5_ADDR 0xB8C -#define C2H_STAT_DMA_ENG_5_RSVD_1_MASK GENMASK(31, 25) -#define C2H_STAT_DMA_ENG_5_TUSER_COMB_OUT_VLD_MASK BIT(24) -#define C2H_STAT_DMA_ENG_5_TUSER_FIFO_IN_RDY_MASK BIT(23) -#define C2H_STAT_DMA_ENG_5_TUSER_COMB_IN_CNT_MASK GENMASK(22, 13) -#define C2H_STAT_DMA_ENG_5_TUSE_COMB_OUTPUT_CNT_MASK GENMASK(12, 3) -#define C2H_STAT_DMA_ENG_5_TUSER_COMB_CNT_MASK GENMASK(2, 0) -#define QDMA_CPM4_C2H_DBG_PFCH_QID_ADDR 0xB90 -#define C2H_PFCH_QID_RSVD_1_MASK GENMASK(31, 15) -#define C2H_PFCH_QID_ERR_CTXT_MASK BIT(14) -#define C2H_PFCH_QID_TARGET_MASK GENMASK(13, 11) -#define C2H_PFCH_QID_QID_OR_TAG_MASK GENMASK(10, 0) -#define QDMA_CPM4_C2H_DBG_PFCH_ADDR 0xB94 -#define C2H_PFCH_DATA_MASK GENMASK(31, 0) -#define QDMA_CPM4_C2H_INT_DBG_ADDR 0xB98 -#define C2H_INT_RSVD_1_MASK GENMASK(31, 8) -#define C2H_INT_INT_COAL_SM_MASK GENMASK(7, 4) -#define C2H_INT_INT_SM_MASK GENMASK(3, 0) -#define QDMA_CPM4_C2H_STAT_IMM_ACCEPTED_ADDR 0xB9C -#define C2H_STAT_IMM_ACCEPTED_RSVD_1_MASK GENMASK(31, 18) -#define C2H_STAT_IMM_ACCEPTED_CNT_MASK GENMASK(17, 0) -#define QDMA_CPM4_C2H_STAT_MARKER_ACCEPTED_ADDR 0xBA0 -#define C2H_STAT_MARKER_ACCEPTED_RSVD_1_MASK GENMASK(31, 18) -#define C2H_STAT_MARKER_ACCEPTED_CNT_MASK GENMASK(17, 0) -#define QDMA_CPM4_C2H_STAT_DISABLE_CMP_ACCEPTED_ADDR 0xBA4 -#define C2H_STAT_DISABLE_CMP_ACCEPTED_RSVD_1_MASK GENMASK(31, 18) -#define C2H_STAT_DISABLE_CMP_ACCEPTED_CNT_MASK GENMASK(17, 0) -#define QDMA_CPM4_C2H_PLD_FIFO_CRDT_CNT_ADDR 0xBA8 -#define C2H_PLD_FIFO_CRDT_CNT_RSVD_1_MASK GENMASK(31, 18) -#define C2H_PLD_FIFO_CRDT_CNT_CNT_MASK GENMASK(17, 0) -#define QDMA_CPM4_H2C_ERR_STAT_ADDR 0xE00 -#define H2C_ERR_STAT_RSVD_1_MASK GENMASK(31, 5) -#define H2C_ERR_STAT_SBE_MASK BIT(4) -#define H2C_ERR_STAT_DBE_MASK BIT(3) -#define H2C_ERR_STAT_NO_DMA_DS_MASK BIT(2) -#define H2C_ERR_STAT_SDI_MRKR_REQ_MOP_ERR_MASK BIT(1) -#define H2C_ERR_STAT_ZERO_LEN_DS_MASK BIT(0) -#define QDMA_CPM4_H2C_ERR_MASK_ADDR 0xE04 -#define H2C_ERR_EN_MASK GENMASK(31, 0) -#define QDMA_CPM4_H2C_FIRST_ERR_QID_ADDR 0xE08 -#define H2C_FIRST_ERR_QID_RSVD_1_MASK GENMASK(31, 20) -#define H2C_FIRST_ERR_QID_ERR_TYPE_MASK GENMASK(19, 16) -#define H2C_FIRST_ERR_QID_RSVD_2_MASK GENMASK(15, 12) -#define H2C_FIRST_ERR_QID_QID_MASK GENMASK(11, 0) -#define QDMA_CPM4_H2C_DBG_REG0_ADDR 0xE0C -#define H2C_REG0_NUM_DSC_RCVD_MASK GENMASK(31, 16) -#define H2C_REG0_NUM_WRB_SENT_MASK GENMASK(15, 0) -#define QDMA_CPM4_H2C_DBG_REG1_ADDR 0xE10 -#define H2C_REG1_NUM_REQ_SENT_MASK GENMASK(31, 16) -#define H2C_REG1_NUM_CMP_SENT_MASK GENMASK(15, 0) -#define QDMA_CPM4_H2C_DBG_REG2_ADDR 0xE14 -#define H2C_REG2_RSVD_1_MASK GENMASK(31, 16) -#define H2C_REG2_NUM_ERR_DSC_RCVD_MASK GENMASK(15, 0) -#define QDMA_CPM4_H2C_DBG_REG3_ADDR 0xE18 -#define H2C_REG3_MASK BIT(31) -#define H2C_REG3_DSCO_FIFO_EMPTY_MASK BIT(30) -#define H2C_REG3_DSCO_FIFO_FULL_MASK BIT(29) -#define H2C_REG3_CUR_RC_STATE_MASK GENMASK(28, 26) -#define H2C_REG3_RDREQ_LINES_MASK GENMASK(25, 16) -#define H2C_REG3_RDATA_LINES_AVAIL_MASK GENMASK(15, 6) -#define H2C_REG3_PEND_FIFO_EMPTY_MASK BIT(5) -#define H2C_REG3_PEND_FIFO_FULL_MASK BIT(4) -#define H2C_REG3_CUR_RQ_STATE_MASK GENMASK(3, 2) -#define H2C_REG3_DSCI_FIFO_FULL_MASK BIT(1) -#define H2C_REG3_DSCI_FIFO_EMPTY_MASK BIT(0) -#define QDMA_CPM4_H2C_DBG_REG4_ADDR 0xE1C -#define H2C_REG4_RDREQ_ADDR_MASK GENMASK(31, 0) -#define QDMA_CPM4_H2C_FATAL_ERR_EN_ADDR 0xE20 -#define H2C_FATAL_ERR_EN_RSVD_1_MASK GENMASK(31, 1) -#define H2C_FATAL_ERR_EN_H2C_MASK BIT(0) -#define QDMA_CPM4_C2H_CHANNEL_CTL_ADDR 0x1004 -#define C2H_CHANNEL_CTL_RSVD_1_MASK GENMASK(31, 1) -#define C2H_CHANNEL_CTL_RUN_MASK BIT(0) -#define QDMA_CPM4_C2H_CHANNEL_CTL_1_ADDR 0x1008 -#define C2H_CHANNEL_CTL_1_RUN_MASK GENMASK(31, 1) -#define C2H_CHANNEL_CTL_1_RUN_1_MASK BIT(0) -#define QDMA_CPM4_C2H_MM_STATUS_ADDR 0x1040 -#define C2H_MM_STATUS_RSVD_1_MASK GENMASK(31, 1) -#define C2H_MM_STATUS_RUN_MASK BIT(0) -#define QDMA_CPM4_C2H_CHANNEL_CMPL_DESC_CNT_ADDR 0x1048 -#define C2H_CHANNEL_CMPL_DESC_CNT_C2H_CO_MASK GENMASK(31, 0) -#define QDMA_CPM4_C2H_MM_ERR_CODE_ENABLE_MASK_ADDR 0x1054 -#define C2H_MM_ERR_CODE_ENABLE_RSVD_1_MASK BIT(31) -#define C2H_MM_ERR_CODE_ENABLE_WR_UC_RAM_MASK BIT(30) -#define C2H_MM_ERR_CODE_ENABLE_WR_UR_MASK BIT(29) -#define C2H_MM_ERR_CODE_ENABLE_WR_FLR_MASK BIT(28) -#define C2H_MM_ERR_CODE_ENABLE_RSVD_2_MASK GENMASK(27, 2) -#define C2H_MM_ERR_CODE_ENABLE_RD_SLV_ERR_MASK BIT(1) -#define C2H_MM_ERR_CODE_ENABLE_WR_SLV_ERR_MASK BIT(0) -#define QDMA_CPM4_C2H_MM_ERR_CODE_ADDR 0x1058 -#define C2H_MM_ERR_CODE_RSVD_1_MASK GENMASK(31, 18) -#define C2H_MM_ERR_CODE_VALID_MASK BIT(17) -#define C2H_MM_ERR_CODE_RDWR_MASK BIT(16) -#define C2H_MM_ERR_CODE_MASK GENMASK(4, 0) -#define QDMA_CPM4_C2H_MM_ERR_INFO_ADDR 0x105C -#define C2H_MM_ERR_INFO_RSVD_1_MASK GENMASK(31, 29) -#define C2H_MM_ERR_INFO_QID_MASK GENMASK(28, 17) -#define C2H_MM_ERR_INFO_DIR_MASK BIT(16) -#define C2H_MM_ERR_INFO_CIDX_MASK GENMASK(15, 0) -#define QDMA_CPM4_C2H_MM_PERF_MON_CTL_ADDR 0x10C0 -#define C2H_MM_PERF_MON_CTL_RSVD_1_MASK GENMASK(31, 4) -#define C2H_MM_PERF_MON_CTL_IMM_START_MASK BIT(3) -#define C2H_MM_PERF_MON_CTL_RUN_START_MASK BIT(2) -#define C2H_MM_PERF_MON_CTL_IMM_CLEAR_MASK BIT(1) -#define C2H_MM_PERF_MON_CTL_RUN_CLEAR_MASK BIT(0) -#define QDMA_CPM4_C2H_MM_PERF_MON_CYCLE_CNT0_ADDR 0x10C4 -#define C2H_MM_PERF_MON_CYCLE_CNT0_CYC_CNT_MASK GENMASK(31, 0) -#define QDMA_CPM4_C2H_MM_PERF_MON_CYCLE_CNT1_ADDR 0x10C8 -#define C2H_MM_PERF_MON_CYCLE_CNT1_RSVD_1_MASK GENMASK(31, 10) -#define C2H_MM_PERF_MON_CYCLE_CNT1_CYC_CNT_MASK GENMASK(9, 0) -#define QDMA_CPM4_C2H_MM_PERF_MON_DATA_CNT0_ADDR 0x10CC -#define C2H_MM_PERF_MON_DATA_CNT0_DCNT_MASK GENMASK(31, 0) -#define QDMA_CPM4_C2H_MM_PERF_MON_DATA_CNT1_ADDR 0x10D0 -#define C2H_MM_PERF_MON_DATA_CNT1_RSVD_1_MASK GENMASK(31, 10) -#define C2H_MM_PERF_MON_DATA_CNT1_DCNT_MASK GENMASK(9, 0) -#define QDMA_CPM4_C2H_MM_DBG_ADDR 0x10E8 -#define C2H_MM_RSVD_1_MASK GENMASK(31, 24) -#define C2H_MM_RRQ_ENTRIES_MASK GENMASK(23, 17) -#define C2H_MM_DAT_FIFO_SPC_MASK GENMASK(16, 7) -#define C2H_MM_RD_STALL_MASK BIT(6) -#define C2H_MM_RRQ_FIFO_FI_MASK BIT(5) -#define C2H_MM_WR_STALL_MASK BIT(4) -#define C2H_MM_WRQ_FIFO_FI_MASK BIT(3) -#define C2H_MM_WBK_STALL_MASK BIT(2) -#define C2H_MM_DSC_FIFO_EP_MASK BIT(1) -#define C2H_MM_DSC_FIFO_FL_MASK BIT(0) -#define QDMA_CPM4_H2C_CHANNEL_CTL_ADDR 0x1204 -#define H2C_CHANNEL_CTL_RSVD_1_MASK GENMASK(31, 1) -#define H2C_CHANNEL_CTL_RUN_MASK BIT(0) -#define QDMA_CPM4_H2C_CHANNEL_CTL_1_ADDR 0x1208 -#define H2C_CHANNEL_CTL_1_RUN_MASK BIT(0) -#define QDMA_CPM4_H2C_CHANNEL_CTL_2_ADDR 0x120C -#define H2C_CHANNEL_CTL_2_RUN_MASK BIT(0) -#define QDMA_CPM4_H2C_MM_STATUS_ADDR 0x1240 -#define H2C_MM_STATUS_RSVD_1_MASK GENMASK(31, 1) -#define H2C_MM_STATUS_RUN_MASK BIT(0) -#define QDMA_CPM4_H2C_CHANNEL_CMPL_DESC_CNT_ADDR 0x1248 -#define H2C_CHANNEL_CMPL_DESC_CNT_H2C_CO_MASK GENMASK(31, 0) -#define QDMA_CPM4_H2C_MM_ERR_CODE_ENABLE_MASK_ADDR 0x1254 -#define H2C_MM_ERR_CODE_ENABLE_RSVD_1_MASK GENMASK(31, 30) -#define H2C_MM_ERR_CODE_ENABLE_WR_SLV_ERR_MASK BIT(29) -#define H2C_MM_ERR_CODE_ENABLE_WR_DEC_ERR_MASK BIT(28) -#define H2C_MM_ERR_CODE_ENABLE_RSVD_2_MASK GENMASK(27, 23) -#define H2C_MM_ERR_CODE_ENABLE_RD_RQ_DIS_ERR_MASK BIT(22) -#define H2C_MM_ERR_CODE_ENABLE_RSVD_3_MASK GENMASK(21, 17) -#define H2C_MM_ERR_CODE_ENABLE_RD_DAT_POISON_ERR_MASK BIT(16) -#define H2C_MM_ERR_CODE_ENABLE_RSVD_4_MASK GENMASK(15, 9) -#define H2C_MM_ERR_CODE_ENABLE_RD_FLR_ERR_MASK BIT(8) -#define H2C_MM_ERR_CODE_ENABLE_RSVD_5_MASK GENMASK(7, 6) -#define H2C_MM_ERR_CODE_ENABLE_RD_HDR_ADR_ERR_MASK BIT(5) -#define H2C_MM_ERR_CODE_ENABLE_RD_HDR_PARA_MASK BIT(4) -#define H2C_MM_ERR_CODE_ENABLE_RD_HDR_BYTE_ERR_MASK BIT(3) -#define H2C_MM_ERR_CODE_ENABLE_RD_UR_CA_MASK BIT(2) -#define H2C_MM_ERR_CODE_ENABLE_RD_HRD_POISON_ERR_MASK BIT(1) -#define H2C_MM_ERR_CODE_ENABLE_RSVD_6_MASK BIT(0) -#define QDMA_CPM4_H2C_MM_ERR_CODE_ADDR 0x1258 -#define H2C_MM_ERR_CODE_RSVD_1_MASK GENMASK(31, 18) -#define H2C_MM_ERR_CODE_VALID_MASK BIT(17) -#define H2C_MM_ERR_CODE_RDWR_MASK BIT(16) -#define H2C_MM_ERR_CODE_MASK GENMASK(4, 0) -#define QDMA_CPM4_H2C_MM_ERR_INFO_ADDR 0x125C -#define H2C_MM_ERR_INFO_RSVD_1_MASK GENMASK(31, 29) -#define H2C_MM_ERR_INFO_QID_MASK GENMASK(28, 17) -#define H2C_MM_ERR_INFO_DIR_MASK BIT(16) -#define H2C_MM_ERR_INFO_CIDX_MASK GENMASK(15, 0) -#define QDMA_CPM4_H2C_MM_PERF_MON_CTL_ADDR 0x12C0 -#define H2C_MM_PERF_MON_CTL_RSVD_1_MASK GENMASK(31, 4) -#define H2C_MM_PERF_MON_CTL_IMM_START_MASK BIT(3) -#define H2C_MM_PERF_MON_CTL_RUN_START_MASK BIT(2) -#define H2C_MM_PERF_MON_CTL_IMM_CLEAR_MASK BIT(1) -#define H2C_MM_PERF_MON_CTL_RUN_CLEAR_MASK BIT(0) -#define QDMA_CPM4_H2C_MM_PERF_MON_CYCLE_CNT0_ADDR 0x12C4 -#define H2C_MM_PERF_MON_CYCLE_CNT0_CYC_CNT_MASK GENMASK(31, 0) -#define QDMA_CPM4_H2C_MM_PERF_MON_CYCLE_CNT1_ADDR 0x12C8 -#define H2C_MM_PERF_MON_CYCLE_CNT1_RSVD_1_MASK GENMASK(31, 10) -#define H2C_MM_PERF_MON_CYCLE_CNT1_CYC_CNT_MASK GENMASK(9, 0) -#define QDMA_CPM4_H2C_MM_PERF_MON_DATA_CNT0_ADDR 0x12CC -#define H2C_MM_PERF_MON_DATA_CNT0_DCNT_MASK GENMASK(31, 0) -#define QDMA_CPM4_H2C_MM_PERF_MON_DATA_CNT1_ADDR 0x12D0 -#define H2C_MM_PERF_MON_DATA_CNT1_RSVD_1_MASK GENMASK(31, 10) -#define H2C_MM_PERF_MON_DATA_CNT1_DCNT_MASK GENMASK(9, 0) -#define QDMA_CPM4_H2C_MM_DBG_ADDR 0x12E8 -#define H2C_MM_RSVD_1_MASK GENMASK(31, 24) -#define H2C_MM_RRQ_ENTRIES_MASK GENMASK(23, 17) -#define H2C_MM_DAT_FIFO_SPC_MASK GENMASK(16, 7) -#define H2C_MM_RD_STALL_MASK BIT(6) -#define H2C_MM_RRQ_FIFO_FI_MASK BIT(5) -#define H2C_MM_WR_STALL_MASK BIT(4) -#define H2C_MM_WRQ_FIFO_FI_MASK BIT(3) -#define H2C_MM_WBK_STALL_MASK BIT(2) -#define H2C_MM_DSC_FIFO_EP_MASK BIT(1) -#define H2C_MM_DSC_FIFO_FL_MASK BIT(0) -#define QDMA_CPM4_FUNC_STATUS_REG_ADDR 0x2400 -#define FUNC_STATUS_REG_RSVD_1_MASK GENMASK(31, 12) -#define FUNC_STATUS_REG_CUR_SRC_FN_MASK GENMASK(11, 4) -#define FUNC_STATUS_REG_ACK_MASK BIT(2) -#define FUNC_STATUS_REG_O_MSG_MASK BIT(1) -#define FUNC_STATUS_REG_I_MSG_MASK BIT(0) -#define QDMA_CPM4_FUNC_CMD_REG_ADDR 0x2404 -#define FUNC_CMD_REG_RSVD_1_MASK GENMASK(31, 3) -#define FUNC_CMD_REG_RSVD_2_MASK BIT(2) -#define FUNC_CMD_REG_MSG_RCV_MASK BIT(1) -#define FUNC_CMD_REG_MSG_SENT_MASK BIT(0) -#define QDMA_CPM4_FUNC_INTERRUPT_VECTOR_REG_ADDR 0x2408 -#define FUNC_INTERRUPT_VECTOR_REG_RSVD_1_MASK GENMASK(31, 5) -#define FUNC_INTERRUPT_VECTOR_REG_IN_MASK GENMASK(4, 0) -#define QDMA_CPM4_TARGET_FUNC_REG_ADDR 0x240C -#define TARGET_FUNC_REG_RSVD_1_MASK GENMASK(31, 8) -#define TARGET_FUNC_REG_N_ID_MASK GENMASK(7, 0) -#define QDMA_CPM4_FUNC_INTERRUPT_CTL_REG_ADDR 0x2410 -#define FUNC_INTERRUPT_CTL_REG_RSVD_1_MASK GENMASK(31, 1) -#define FUNC_INTERRUPT_CTL_REG_INT_EN_MASK BIT(0) -#define SW_IND_CTXT_DATA_W3_DSC_BASE_H_MASK GENMASK(31, 0) -#define SW_IND_CTXT_DATA_W2_DSC_BASE_L_MASK GENMASK(31, 0) -#define SW_IND_CTXT_DATA_W1_IS_MM_MASK BIT(31) -#define SW_IND_CTXT_DATA_W1_MRKR_DIS_MASK BIT(30) -#define SW_IND_CTXT_DATA_W1_IRQ_REQ_MASK BIT(29) -#define SW_IND_CTXT_DATA_W1_ERR_WB_SENT_MASK BIT(28) -#define SW_IND_CTXT_DATA_W1_ERR_MASK GENMASK(27, 26) -#define SW_IND_CTXT_DATA_W1_IRQ_NO_LAST_MASK BIT(25) -#define SW_IND_CTXT_DATA_W1_PORT_ID_MASK GENMASK(24, 22) -#define SW_IND_CTXT_DATA_W1_IRQ_EN_MASK BIT(21) -#define SW_IND_CTXT_DATA_W1_WBK_EN_MASK BIT(20) -#define SW_IND_CTXT_DATA_W1_MM_CHN_MASK BIT(19) -#define SW_IND_CTXT_DATA_W1_BYPASS_MASK BIT(18) -#define SW_IND_CTXT_DATA_W1_DSC_SZ_MASK GENMASK(17, 16) -#define SW_IND_CTXT_DATA_W1_RNG_SZ_MASK GENMASK(15, 12) -#define SW_IND_CTXT_DATA_W1_FNC_ID_MASK GENMASK(11, 4) -#define SW_IND_CTXT_DATA_W1_WBI_INTVL_EN_MASK BIT(3) -#define SW_IND_CTXT_DATA_W1_WBI_CHK_MASK BIT(2) -#define SW_IND_CTXT_DATA_W1_FCRD_EN_MASK BIT(1) -#define SW_IND_CTXT_DATA_W1_QEN_MASK BIT(0) -#define SW_IND_CTXT_DATA_W0_RSV_MASK GENMASK(31, 17) -#define SW_IND_CTXT_DATA_W0_IRQ_ARM_MASK BIT(16) -#define SW_IND_CTXT_DATA_W0_PIDX_MASK GENMASK(15, 0) -#define HW_IND_CTXT_DATA_W1_RSVD_MASK GENMASK(15, 11) -#define HW_IND_CTXT_DATA_W1_FETCH_PND_MASK BIT(10) -#define HW_IND_CTXT_DATA_W1_IDL_STP_B_MASK BIT(9) -#define HW_IND_CTXT_DATA_W1_DSC_PND_MASK BIT(8) -#define HW_IND_CTXT_DATA_W1_RSVD_1_MASK GENMASK(7, 0) -#define HW_IND_CTXT_DATA_W0_CRD_USE_MASK GENMASK(31, 16) -#define HW_IND_CTXT_DATA_W0_CIDX_MASK GENMASK(15, 0) -#define CRED_CTXT_DATA_W0_RSVD_1_MASK GENMASK(31, 16) -#define CRED_CTXT_DATA_W0_CREDT_MASK GENMASK(15, 0) -#define PREFETCH_CTXT_DATA_W1_VALID_MASK BIT(13) -#define PREFETCH_CTXT_DATA_W1_SW_CRDT_H_MASK GENMASK(12, 0) -#define PREFETCH_CTXT_DATA_W0_SW_CRDT_L_MASK GENMASK(31, 29) -#define PREFETCH_CTXT_DATA_W0_PFCH_MASK BIT(28) -#define PREFETCH_CTXT_DATA_W0_PFCH_EN_MASK BIT(27) -#define PREFETCH_CTXT_DATA_W0_ERR_MASK BIT(26) -#define PREFETCH_CTXT_DATA_W0_RSVD_MASK GENMASK(25, 8) -#define PREFETCH_CTXT_DATA_W0_PORT_ID_MASK GENMASK(7, 5) -#define PREFETCH_CTXT_DATA_W0_BUF_SIZE_IDX_MASK GENMASK(4, 1) -#define PREFETCH_CTXT_DATA_W0_BYPASS_MASK BIT(0) -#define CMPL_CTXT_DATA_W3_RSVD_MASK GENMASK(31, 30) -#define CMPL_CTXT_DATA_W3_FULL_UPD_MASK BIT(29) -#define CMPL_CTXT_DATA_W3_TIMER_RUNNING_MASK BIT(28) -#define CMPL_CTXT_DATA_W3_USER_TRIG_PEND_MASK BIT(27) -#define CMPL_CTXT_DATA_W3_ERR_MASK GENMASK(26, 25) -#define CMPL_CTXT_DATA_W3_VALID_MASK BIT(24) -#define CMPL_CTXT_DATA_W3_CIDX_MASK GENMASK(23, 8) -#define CMPL_CTXT_DATA_W3_PIDX_H_MASK GENMASK(7, 0) -#define CMPL_CTXT_DATA_W2_PIDX_L_MASK GENMASK(31, 24) -#define CMPL_CTXT_DATA_W2_DESC_SIZE_MASK GENMASK(23, 22) -#define CMPL_CTXT_DATA_W2_BADDR_64_H_MASK GENMASK(21, 0) -#define CMPL_CTXT_DATA_W1_BADDR_64_M_MASK GENMASK(31, 0) -#define CMPL_CTXT_DATA_W0_BADDR_64_L_MASK GENMASK(31, 28) -#define CMPL_CTXT_DATA_W0_QSIZE_IDX_MASK GENMASK(27, 24) -#define CMPL_CTXT_DATA_W0_COLOR_MASK BIT(23) -#define CMPL_CTXT_DATA_W0_INT_ST_MASK GENMASK(22, 21) -#define CMPL_CTXT_DATA_W0_TIMER_IDX_MASK GENMASK(20, 17) -#define CMPL_CTXT_DATA_W0_CNTER_IDX_MASK GENMASK(16, 13) -#define CMPL_CTXT_DATA_W0_FNC_ID_MASK GENMASK(12, 5) -#define CMPL_CTXT_DATA_W0_TRIG_MODE_MASK GENMASK(4, 2) -#define CMPL_CTXT_DATA_W0_EN_INT_MASK BIT(1) -#define CMPL_CTXT_DATA_W0_EN_STAT_DESC_MASK BIT(0) -#define INTR_CTXT_DATA_W2_PIDX_MASK GENMASK(11, 0) -#define INTR_CTXT_DATA_W1_PAGE_SIZE_MASK GENMASK(31, 29) -#define INTR_CTXT_DATA_W1_BADDR_4K_H_MASK GENMASK(28, 0) -#define INTR_CTXT_DATA_W0_BADDR_4K_L_MASK GENMASK(31, 9) -#define INTR_CTXT_DATA_W0_COLOR_MASK BIT(8) -#define INTR_CTXT_DATA_W0_INT_ST_MASK BIT(7) -#define INTR_CTXT_DATA_W0_RSVD_MASK BIT(6) -#define INTR_CTXT_DATA_W0_VEC_MASK GENMASK(5, 1) -#define INTR_CTXT_DATA_W0_VALID_MASK BIT(0) - -#ifdef __cplusplus -} -#endif - -#endif - diff --git a/QDMA/linux-kernel/driver/libqdma/qdma_access/qdma_cpm4_access/qdma_cpm4_reg_dump.c b/QDMA/linux-kernel/driver/libqdma/qdma_access/qdma_cpm4_access/qdma_cpm4_reg_dump.c deleted file mode 100755 index dcfb94f47..000000000 --- a/QDMA/linux-kernel/driver/libqdma/qdma_access/qdma_cpm4_access/qdma_cpm4_reg_dump.c +++ /dev/null @@ -1,8013 +0,0 @@ -/* - * Copyright (c) 2019-2022, Xilinx, Inc. All rights reserved. - * Copyright (c) 2022, Advanced Micro Devices, Inc. All rights reserved. - * - * This source code is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * The full GNU General Public License is included in this distribution in - * the file called "COPYING". - */ - -#include "qdma_cpm4_reg.h" -#include "qdma_reg_dump.h" - -#ifdef ENABLE_WPP_TRACING -#include "qdma_cpm4_reg_dump.tmh" -#endif - - -static struct regfield_info - cfg_blk_identifier_field_info[] = { - {"CFG_BLK_IDENTIFIER", - CFG_BLK_IDENTIFIER_MASK}, - {"CFG_BLK_IDENTIFIER_1", - CFG_BLK_IDENTIFIER_1_MASK}, - {"CFG_BLK_IDENTIFIER_RSVD_1", - CFG_BLK_IDENTIFIER_RSVD_1_MASK}, - {"CFG_BLK_IDENTIFIER_VERSION", - CFG_BLK_IDENTIFIER_VERSION_MASK}, -}; - - -static struct regfield_info - cfg_blk_busdev_field_info[] = { - {"CFG_BLK_BUSDEV_BDF", - CFG_BLK_BUSDEV_BDF_MASK}, -}; - - -static struct regfield_info - cfg_blk_pcie_max_pld_size_field_info[] = { - {"CFG_BLK_PCIE_MAX_PLD_SIZE", - CFG_BLK_PCIE_MAX_PLD_SIZE_MASK}, -}; - - -static struct regfield_info - cfg_blk_pcie_max_read_req_size_field_info[] = { - {"CFG_BLK_PCIE_MAX_READ_REQ_SIZE", - CFG_BLK_PCIE_MAX_READ_REQ_SIZE_MASK}, -}; - - -static struct regfield_info - cfg_blk_system_id_field_info[] = { - {"CFG_BLK_SYSTEM_ID", - CFG_BLK_SYSTEM_ID_MASK}, -}; - - -static struct regfield_info - cfg_blk_msi_enable_field_info[] = { - {"CFG_BLK_MSI_ENABLE_3", - CFG_BLK_MSI_ENABLE_3_MASK}, - {"CFG_BLK_MSI_ENABLE_MSIX3", - CFG_BLK_MSI_ENABLE_MSIX3_MASK}, - {"CFG_BLK_MSI_ENABLE_2", - CFG_BLK_MSI_ENABLE_2_MASK}, - {"CFG_BLK_MSI_ENABLE_MSIX2", - CFG_BLK_MSI_ENABLE_MSIX2_MASK}, - {"CFG_BLK_MSI_ENABLE_1", - CFG_BLK_MSI_ENABLE_1_MASK}, - {"CFG_BLK_MSI_ENABLE_MSIX1", - CFG_BLK_MSI_ENABLE_MSIX1_MASK}, - {"CFG_BLK_MSI_ENABLE_0", - CFG_BLK_MSI_ENABLE_0_MASK}, - {"CFG_BLK_MSI_ENABLE_MSIX0", - CFG_BLK_MSI_ENABLE_MSIX0_MASK}, -}; - - -static struct regfield_info - cfg_pcie_data_width_field_info[] = { - {"CFG_PCIE_DATA_WIDTH_DATAPATH", - CFG_PCIE_DATA_WIDTH_DATAPATH_MASK}, -}; - - -static struct regfield_info - cfg_pcie_ctl_field_info[] = { - {"CFG_PCIE_CTL_RRQ_DISABLE", - CFG_PCIE_CTL_RRQ_DISABLE_MASK}, - {"CFG_PCIE_CTL_RELAXED_ORDERING", - CFG_PCIE_CTL_RELAXED_ORDERING_MASK}, -}; - - -static struct regfield_info - cfg_axi_user_max_pld_size_field_info[] = { - {"CFG_AXI_USER_MAX_PLD_SIZE_ISSUED", - CFG_AXI_USER_MAX_PLD_SIZE_ISSUED_MASK}, - {"CFG_AXI_USER_MAX_PLD_SIZE_PROG", - CFG_AXI_USER_MAX_PLD_SIZE_PROG_MASK}, -}; - - -static struct regfield_info - cfg_axi_user_max_read_req_size_field_info[] = { - {"CFG_AXI_USER_MAX_READ_REQ_SIZE_USISSUED", - CFG_AXI_USER_MAX_READ_REQ_SIZE_USISSUED_MASK}, - {"CFG_AXI_USER_MAX_READ_REQ_SIZE_USPROG", - CFG_AXI_USER_MAX_READ_REQ_SIZE_USPROG_MASK}, -}; - - -static struct regfield_info - cfg_blk_misc_ctl_field_info[] = { - {"CFG_BLK_MISC_CTL_NUM_TAG", - CFG_BLK_MISC_CTL_NUM_TAG_MASK}, - {"CFG_BLK_MISC_CTL_RQ_METERING_MULTIPLIER", - CFG_BLK_MISC_CTL_RQ_METERING_MULTIPLIER_MASK}, -}; - - -static struct regfield_info - cfg_blk_scratch_0_field_info[] = { - {"CFG_BLK_SCRATCH_0", - CFG_BLK_SCRATCH_0_MASK}, -}; - - -static struct regfield_info - cfg_blk_scratch_1_field_info[] = { - {"CFG_BLK_SCRATCH_1", - CFG_BLK_SCRATCH_1_MASK}, -}; - - -static struct regfield_info - cfg_blk_scratch_2_field_info[] = { - {"CFG_BLK_SCRATCH_2", - CFG_BLK_SCRATCH_2_MASK}, -}; - - -static struct regfield_info - cfg_blk_scratch_3_field_info[] = { - {"CFG_BLK_SCRATCH_3", - CFG_BLK_SCRATCH_3_MASK}, -}; - - -static struct regfield_info - cfg_blk_scratch_4_field_info[] = { - {"CFG_BLK_SCRATCH_4", - CFG_BLK_SCRATCH_4_MASK}, -}; - - -static struct regfield_info - cfg_blk_scratch_5_field_info[] = { - {"CFG_BLK_SCRATCH_5", - CFG_BLK_SCRATCH_5_MASK}, -}; - - -static struct regfield_info - cfg_blk_scratch_6_field_info[] = { - {"CFG_BLK_SCRATCH_6", - CFG_BLK_SCRATCH_6_MASK}, -}; - - -static struct regfield_info - cfg_blk_scratch_7_field_info[] = { - {"CFG_BLK_SCRATCH_7", - CFG_BLK_SCRATCH_7_MASK}, -}; - - -static struct regfield_info - ram_sbe_msk_a_field_info[] = { - {"RAM_SBE_MSK_A", - RAM_SBE_MSK_A_MASK}, -}; - - -static struct regfield_info - ram_sbe_sts_a_field_info[] = { - {"RAM_SBE_STS_A_RSVD_1", - RAM_SBE_STS_A_RSVD_1_MASK}, - {"RAM_SBE_STS_A_PFCH_LL_RAM", - RAM_SBE_STS_A_PFCH_LL_RAM_MASK}, - {"RAM_SBE_STS_A_WRB_CTXT_RAM", - RAM_SBE_STS_A_WRB_CTXT_RAM_MASK}, - {"RAM_SBE_STS_A_PFCH_CTXT_RAM", - RAM_SBE_STS_A_PFCH_CTXT_RAM_MASK}, - {"RAM_SBE_STS_A_DESC_REQ_FIFO_RAM", - RAM_SBE_STS_A_DESC_REQ_FIFO_RAM_MASK}, - {"RAM_SBE_STS_A_INT_CTXT_RAM", - RAM_SBE_STS_A_INT_CTXT_RAM_MASK}, - {"RAM_SBE_STS_A_INT_QID2VEC_RAM", - RAM_SBE_STS_A_INT_QID2VEC_RAM_MASK}, - {"RAM_SBE_STS_A_WRB_COAL_DATA_RAM", - RAM_SBE_STS_A_WRB_COAL_DATA_RAM_MASK}, - {"RAM_SBE_STS_A_TUSER_FIFO_RAM", - RAM_SBE_STS_A_TUSER_FIFO_RAM_MASK}, - {"RAM_SBE_STS_A_QID_FIFO_RAM", - RAM_SBE_STS_A_QID_FIFO_RAM_MASK}, - {"RAM_SBE_STS_A_PLD_FIFO_RAM", - RAM_SBE_STS_A_PLD_FIFO_RAM_MASK}, - {"RAM_SBE_STS_A_TIMER_FIFO_RAM", - RAM_SBE_STS_A_TIMER_FIFO_RAM_MASK}, - {"RAM_SBE_STS_A_PASID_CTXT_RAM", - RAM_SBE_STS_A_PASID_CTXT_RAM_MASK}, - {"RAM_SBE_STS_A_DSC_CPLD", - RAM_SBE_STS_A_DSC_CPLD_MASK}, - {"RAM_SBE_STS_A_DSC_CPLI", - RAM_SBE_STS_A_DSC_CPLI_MASK}, - {"RAM_SBE_STS_A_DSC_SW_CTXT", - RAM_SBE_STS_A_DSC_SW_CTXT_MASK}, - {"RAM_SBE_STS_A_DSC_CRD_RCV", - RAM_SBE_STS_A_DSC_CRD_RCV_MASK}, - {"RAM_SBE_STS_A_DSC_HW_CTXT", - RAM_SBE_STS_A_DSC_HW_CTXT_MASK}, - {"RAM_SBE_STS_A_FUNC_MAP", - RAM_SBE_STS_A_FUNC_MAP_MASK}, - {"RAM_SBE_STS_A_C2H_WR_BRG_DAT", - RAM_SBE_STS_A_C2H_WR_BRG_DAT_MASK}, - {"RAM_SBE_STS_A_C2H_RD_BRG_DAT", - RAM_SBE_STS_A_C2H_RD_BRG_DAT_MASK}, - {"RAM_SBE_STS_A_H2C_WR_BRG_DAT", - RAM_SBE_STS_A_H2C_WR_BRG_DAT_MASK}, - {"RAM_SBE_STS_A_H2C_RD_BRG_DAT", - RAM_SBE_STS_A_H2C_RD_BRG_DAT_MASK}, - {"RAM_SBE_STS_A_RSVD_2", - RAM_SBE_STS_A_RSVD_2_MASK}, - {"RAM_SBE_STS_A_MI_C2H0_DAT", - RAM_SBE_STS_A_MI_C2H0_DAT_MASK}, - {"RAM_SBE_STS_A_RSVD_3", - RAM_SBE_STS_A_RSVD_3_MASK}, - {"RAM_SBE_STS_A_MI_H2C0_DAT", - RAM_SBE_STS_A_MI_H2C0_DAT_MASK}, -}; - - -static struct regfield_info - ram_dbe_msk_a_field_info[] = { - {"RAM_DBE_MSK_A", - RAM_DBE_MSK_A_MASK}, -}; - - -static struct regfield_info - ram_dbe_sts_a_field_info[] = { - {"RAM_DBE_STS_A_RSVD_1", - RAM_DBE_STS_A_RSVD_1_MASK}, - {"RAM_DBE_STS_A_PFCH_LL_RAM", - RAM_DBE_STS_A_PFCH_LL_RAM_MASK}, - {"RAM_DBE_STS_A_WRB_CTXT_RAM", - RAM_DBE_STS_A_WRB_CTXT_RAM_MASK}, - {"RAM_DBE_STS_A_PFCH_CTXT_RAM", - RAM_DBE_STS_A_PFCH_CTXT_RAM_MASK}, - {"RAM_DBE_STS_A_DESC_REQ_FIFO_RAM", - RAM_DBE_STS_A_DESC_REQ_FIFO_RAM_MASK}, - {"RAM_DBE_STS_A_INT_CTXT_RAM", - RAM_DBE_STS_A_INT_CTXT_RAM_MASK}, - {"RAM_DBE_STS_A_INT_QID2VEC_RAM", - RAM_DBE_STS_A_INT_QID2VEC_RAM_MASK}, - {"RAM_DBE_STS_A_WRB_COAL_DATA_RAM", - RAM_DBE_STS_A_WRB_COAL_DATA_RAM_MASK}, - {"RAM_DBE_STS_A_TUSER_FIFO_RAM", - RAM_DBE_STS_A_TUSER_FIFO_RAM_MASK}, - {"RAM_DBE_STS_A_QID_FIFO_RAM", - RAM_DBE_STS_A_QID_FIFO_RAM_MASK}, - {"RAM_DBE_STS_A_PLD_FIFO_RAM", - RAM_DBE_STS_A_PLD_FIFO_RAM_MASK}, - {"RAM_DBE_STS_A_TIMER_FIFO_RAM", - RAM_DBE_STS_A_TIMER_FIFO_RAM_MASK}, - {"RAM_DBE_STS_A_PASID_CTXT_RAM", - RAM_DBE_STS_A_PASID_CTXT_RAM_MASK}, - {"RAM_DBE_STS_A_DSC_CPLD", - RAM_DBE_STS_A_DSC_CPLD_MASK}, - {"RAM_DBE_STS_A_DSC_CPLI", - RAM_DBE_STS_A_DSC_CPLI_MASK}, - {"RAM_DBE_STS_A_DSC_SW_CTXT", - RAM_DBE_STS_A_DSC_SW_CTXT_MASK}, - {"RAM_DBE_STS_A_DSC_CRD_RCV", - RAM_DBE_STS_A_DSC_CRD_RCV_MASK}, - {"RAM_DBE_STS_A_DSC_HW_CTXT", - RAM_DBE_STS_A_DSC_HW_CTXT_MASK}, - {"RAM_DBE_STS_A_FUNC_MAP", - RAM_DBE_STS_A_FUNC_MAP_MASK}, - {"RAM_DBE_STS_A_C2H_WR_BRG_DAT", - RAM_DBE_STS_A_C2H_WR_BRG_DAT_MASK}, - {"RAM_DBE_STS_A_C2H_RD_BRG_DAT", - RAM_DBE_STS_A_C2H_RD_BRG_DAT_MASK}, - {"RAM_DBE_STS_A_H2C_WR_BRG_DAT", - RAM_DBE_STS_A_H2C_WR_BRG_DAT_MASK}, - {"RAM_DBE_STS_A_H2C_RD_BRG_DAT", - RAM_DBE_STS_A_H2C_RD_BRG_DAT_MASK}, - {"RAM_DBE_STS_A_RSVD_2", - RAM_DBE_STS_A_RSVD_2_MASK}, - {"RAM_DBE_STS_A_MI_C2H0_DAT", - RAM_DBE_STS_A_MI_C2H0_DAT_MASK}, - {"RAM_DBE_STS_A_RSVD_3", - RAM_DBE_STS_A_RSVD_3_MASK}, - {"RAM_DBE_STS_A_MI_H2C0_DAT", - RAM_DBE_STS_A_MI_H2C0_DAT_MASK}, -}; - - -static struct regfield_info - glbl2_identifier_field_info[] = { - {"GLBL2_IDENTIFIER", - GLBL2_IDENTIFIER_MASK}, - {"GLBL2_IDENTIFIER_VERSION", - GLBL2_IDENTIFIER_VERSION_MASK}, -}; - - -static struct regfield_info - glbl2_pf_barlite_int_field_info[] = { - {"GLBL2_PF_BARLITE_INT_PF3_BAR_MAP", - GLBL2_PF_BARLITE_INT_PF3_BAR_MAP_MASK}, - {"GLBL2_PF_BARLITE_INT_PF2_BAR_MAP", - GLBL2_PF_BARLITE_INT_PF2_BAR_MAP_MASK}, - {"GLBL2_PF_BARLITE_INT_PF1_BAR_MAP", - GLBL2_PF_BARLITE_INT_PF1_BAR_MAP_MASK}, - {"GLBL2_PF_BARLITE_INT_PF0_BAR_MAP", - GLBL2_PF_BARLITE_INT_PF0_BAR_MAP_MASK}, -}; - - -static struct regfield_info - glbl2_pf_vf_barlite_int_field_info[] = { - {"GLBL2_PF_VF_BARLITE_INT_PF3_MAP", - GLBL2_PF_VF_BARLITE_INT_PF3_MAP_MASK}, - {"GLBL2_PF_VF_BARLITE_INT_PF2_MAP", - GLBL2_PF_VF_BARLITE_INT_PF2_MAP_MASK}, - {"GLBL2_PF_VF_BARLITE_INT_PF1_MAP", - GLBL2_PF_VF_BARLITE_INT_PF1_MAP_MASK}, - {"GLBL2_PF_VF_BARLITE_INT_PF0_MAP", - GLBL2_PF_VF_BARLITE_INT_PF0_MAP_MASK}, -}; - - -static struct regfield_info - glbl2_pf_barlite_ext_field_info[] = { - {"GLBL2_PF_BARLITE_EXT_PF3_BAR_MAP", - GLBL2_PF_BARLITE_EXT_PF3_BAR_MAP_MASK}, - {"GLBL2_PF_BARLITE_EXT_PF2_BAR_MAP", - GLBL2_PF_BARLITE_EXT_PF2_BAR_MAP_MASK}, - {"GLBL2_PF_BARLITE_EXT_PF1_BAR_MAP", - GLBL2_PF_BARLITE_EXT_PF1_BAR_MAP_MASK}, - {"GLBL2_PF_BARLITE_EXT_PF0_BAR_MAP", - GLBL2_PF_BARLITE_EXT_PF0_BAR_MAP_MASK}, -}; - - -static struct regfield_info - glbl2_pf_vf_barlite_ext_field_info[] = { - {"GLBL2_PF_VF_BARLITE_EXT_PF3_MAP", - GLBL2_PF_VF_BARLITE_EXT_PF3_MAP_MASK}, - {"GLBL2_PF_VF_BARLITE_EXT_PF2_MAP", - GLBL2_PF_VF_BARLITE_EXT_PF2_MAP_MASK}, - {"GLBL2_PF_VF_BARLITE_EXT_PF1_MAP", - GLBL2_PF_VF_BARLITE_EXT_PF1_MAP_MASK}, - {"GLBL2_PF_VF_BARLITE_EXT_PF0_MAP", - GLBL2_PF_VF_BARLITE_EXT_PF0_MAP_MASK}, -}; - - -static struct regfield_info - glbl2_channel_inst_field_info[] = { - {"GLBL2_CHANNEL_INST_RSVD_1", - GLBL2_CHANNEL_INST_RSVD_1_MASK}, - {"GLBL2_CHANNEL_INST_C2H_ST", - GLBL2_CHANNEL_INST_C2H_ST_MASK}, - {"GLBL2_CHANNEL_INST_H2C_ST", - GLBL2_CHANNEL_INST_H2C_ST_MASK}, - {"GLBL2_CHANNEL_INST_RSVD_2", - GLBL2_CHANNEL_INST_RSVD_2_MASK}, - {"GLBL2_CHANNEL_INST_C2H_ENG", - GLBL2_CHANNEL_INST_C2H_ENG_MASK}, - {"GLBL2_CHANNEL_INST_RSVD_3", - GLBL2_CHANNEL_INST_RSVD_3_MASK}, - {"GLBL2_CHANNEL_INST_H2C_ENG", - GLBL2_CHANNEL_INST_H2C_ENG_MASK}, -}; - - -static struct regfield_info - glbl2_channel_mdma_field_info[] = { - {"GLBL2_CHANNEL_MDMA_RSVD_1", - GLBL2_CHANNEL_MDMA_RSVD_1_MASK}, - {"GLBL2_CHANNEL_MDMA_C2H_ST", - GLBL2_CHANNEL_MDMA_C2H_ST_MASK}, - {"GLBL2_CHANNEL_MDMA_H2C_ST", - GLBL2_CHANNEL_MDMA_H2C_ST_MASK}, - {"GLBL2_CHANNEL_MDMA_RSVD_2", - GLBL2_CHANNEL_MDMA_RSVD_2_MASK}, - {"GLBL2_CHANNEL_MDMA_C2H_ENG", - GLBL2_CHANNEL_MDMA_C2H_ENG_MASK}, - {"GLBL2_CHANNEL_MDMA_RSVD_3", - GLBL2_CHANNEL_MDMA_RSVD_3_MASK}, - {"GLBL2_CHANNEL_MDMA_H2C_ENG", - GLBL2_CHANNEL_MDMA_H2C_ENG_MASK}, -}; - - -static struct regfield_info - glbl2_channel_strm_field_info[] = { - {"GLBL2_CHANNEL_STRM_RSVD_1", - GLBL2_CHANNEL_STRM_RSVD_1_MASK}, - {"GLBL2_CHANNEL_STRM_C2H_ST", - GLBL2_CHANNEL_STRM_C2H_ST_MASK}, - {"GLBL2_CHANNEL_STRM_H2C_ST", - GLBL2_CHANNEL_STRM_H2C_ST_MASK}, - {"GLBL2_CHANNEL_STRM_RSVD_2", - GLBL2_CHANNEL_STRM_RSVD_2_MASK}, - {"GLBL2_CHANNEL_STRM_C2H_ENG", - GLBL2_CHANNEL_STRM_C2H_ENG_MASK}, - {"GLBL2_CHANNEL_STRM_RSVD_3", - GLBL2_CHANNEL_STRM_RSVD_3_MASK}, - {"GLBL2_CHANNEL_STRM_H2C_ENG", - GLBL2_CHANNEL_STRM_H2C_ENG_MASK}, -}; - - -static struct regfield_info - glbl2_channel_cap_field_info[] = { - {"GLBL2_CHANNEL_CAP_RSVD_1", - GLBL2_CHANNEL_CAP_RSVD_1_MASK}, - {"GLBL2_CHANNEL_CAP_MULTIQ_MAX", - GLBL2_CHANNEL_CAP_MULTIQ_MAX_MASK}, -}; - - -static struct regfield_info - glbl2_channel_pasid_cap_field_info[] = { - {"GLBL2_CHANNEL_PASID_CAP_RSVD_1", - GLBL2_CHANNEL_PASID_CAP_RSVD_1_MASK}, - {"GLBL2_CHANNEL_PASID_CAP_BRIDGEOFFSET", - GLBL2_CHANNEL_PASID_CAP_BRIDGEOFFSET_MASK}, - {"GLBL2_CHANNEL_PASID_CAP_RSVD_2", - GLBL2_CHANNEL_PASID_CAP_RSVD_2_MASK}, - {"GLBL2_CHANNEL_PASID_CAP_BRIDGEEN", - GLBL2_CHANNEL_PASID_CAP_BRIDGEEN_MASK}, - {"GLBL2_CHANNEL_PASID_CAP_DMAEN", - GLBL2_CHANNEL_PASID_CAP_DMAEN_MASK}, -}; - - -static struct regfield_info - glbl2_channel_func_ret_field_info[] = { - {"GLBL2_CHANNEL_FUNC_RET_RSVD_1", - GLBL2_CHANNEL_FUNC_RET_RSVD_1_MASK}, - {"GLBL2_CHANNEL_FUNC_RET_FUNC", - GLBL2_CHANNEL_FUNC_RET_FUNC_MASK}, -}; - - -static struct regfield_info - glbl2_system_id_field_info[] = { - {"GLBL2_SYSTEM_ID_RSVD_1", - GLBL2_SYSTEM_ID_RSVD_1_MASK}, - {"GLBL2_SYSTEM_ID", - GLBL2_SYSTEM_ID_MASK}, -}; - - -static struct regfield_info - glbl2_misc_cap_field_info[] = { - {"GLBL2_MISC_CAP_RSVD_1", - GLBL2_MISC_CAP_RSVD_1_MASK}, -}; - - -static struct regfield_info - glbl2_dbg_pcie_rq0_field_info[] = { - {"GLBL2_PCIE_RQ0_NPH_AVL", - GLBL2_PCIE_RQ0_NPH_AVL_MASK}, - {"GLBL2_PCIE_RQ0_RCB_AVL", - GLBL2_PCIE_RQ0_RCB_AVL_MASK}, - {"GLBL2_PCIE_RQ0_SLV_RD_CREDS", - GLBL2_PCIE_RQ0_SLV_RD_CREDS_MASK}, - {"GLBL2_PCIE_RQ0_TAG_EP", - GLBL2_PCIE_RQ0_TAG_EP_MASK}, - {"GLBL2_PCIE_RQ0_TAG_FL", - GLBL2_PCIE_RQ0_TAG_FL_MASK}, -}; - - -static struct regfield_info - glbl2_dbg_pcie_rq1_field_info[] = { - {"GLBL2_PCIE_RQ1_RSVD_1", - GLBL2_PCIE_RQ1_RSVD_1_MASK}, - {"GLBL2_PCIE_RQ1_WTLP_REQ", - GLBL2_PCIE_RQ1_WTLP_REQ_MASK}, - {"GLBL2_PCIE_RQ1_WTLP_HEADER_FIFO_FL", - GLBL2_PCIE_RQ1_WTLP_HEADER_FIFO_FL_MASK}, - {"GLBL2_PCIE_RQ1_WTLP_HEADER_FIFO_EP", - GLBL2_PCIE_RQ1_WTLP_HEADER_FIFO_EP_MASK}, - {"GLBL2_PCIE_RQ1_RQ_FIFO_EP", - GLBL2_PCIE_RQ1_RQ_FIFO_EP_MASK}, - {"GLBL2_PCIE_RQ1_RQ_FIFO_FL", - GLBL2_PCIE_RQ1_RQ_FIFO_FL_MASK}, - {"GLBL2_PCIE_RQ1_TLPSM", - GLBL2_PCIE_RQ1_TLPSM_MASK}, - {"GLBL2_PCIE_RQ1_TLPSM512", - GLBL2_PCIE_RQ1_TLPSM512_MASK}, - {"GLBL2_PCIE_RQ1_RREQ0_RCB_OK", - GLBL2_PCIE_RQ1_RREQ0_RCB_OK_MASK}, - {"GLBL2_PCIE_RQ1_RREQ0_SLV", - GLBL2_PCIE_RQ1_RREQ0_SLV_MASK}, - {"GLBL2_PCIE_RQ1_RREQ0_VLD", - GLBL2_PCIE_RQ1_RREQ0_VLD_MASK}, - {"GLBL2_PCIE_RQ1_RREQ1_RCB_OK", - GLBL2_PCIE_RQ1_RREQ1_RCB_OK_MASK}, - {"GLBL2_PCIE_RQ1_RREQ1_SLV", - GLBL2_PCIE_RQ1_RREQ1_SLV_MASK}, - {"GLBL2_PCIE_RQ1_RREQ1_VLD", - GLBL2_PCIE_RQ1_RREQ1_VLD_MASK}, -}; - - -static struct regfield_info - glbl2_dbg_aximm_wr0_field_info[] = { - {"GLBL2_AXIMM_WR0_RSVD_1", - GLBL2_AXIMM_WR0_RSVD_1_MASK}, - {"GLBL2_AXIMM_WR0_WR_REQ", - GLBL2_AXIMM_WR0_WR_REQ_MASK}, - {"GLBL2_AXIMM_WR0_WR_CHN", - GLBL2_AXIMM_WR0_WR_CHN_MASK}, - {"GLBL2_AXIMM_WR0_WTLP_DATA_FIFO_EP", - GLBL2_AXIMM_WR0_WTLP_DATA_FIFO_EP_MASK}, - {"GLBL2_AXIMM_WR0_WPL_FIFO_EP", - GLBL2_AXIMM_WR0_WPL_FIFO_EP_MASK}, - {"GLBL2_AXIMM_WR0_BRSP_CLAIM_CHN", - GLBL2_AXIMM_WR0_BRSP_CLAIM_CHN_MASK}, - {"GLBL2_AXIMM_WR0_WRREQ_CNT", - GLBL2_AXIMM_WR0_WRREQ_CNT_MASK}, - {"GLBL2_AXIMM_WR0_BID", - GLBL2_AXIMM_WR0_BID_MASK}, - {"GLBL2_AXIMM_WR0_BVALID", - GLBL2_AXIMM_WR0_BVALID_MASK}, - {"GLBL2_AXIMM_WR0_BREADY", - GLBL2_AXIMM_WR0_BREADY_MASK}, - {"GLBL2_AXIMM_WR0_WVALID", - GLBL2_AXIMM_WR0_WVALID_MASK}, - {"GLBL2_AXIMM_WR0_WREADY", - GLBL2_AXIMM_WR0_WREADY_MASK}, - {"GLBL2_AXIMM_WR0_AWID", - GLBL2_AXIMM_WR0_AWID_MASK}, - {"GLBL2_AXIMM_WR0_AWVALID", - GLBL2_AXIMM_WR0_AWVALID_MASK}, - {"GLBL2_AXIMM_WR0_AWREADY", - GLBL2_AXIMM_WR0_AWREADY_MASK}, -}; - - -static struct regfield_info - glbl2_dbg_aximm_wr1_field_info[] = { - {"GLBL2_AXIMM_WR1_RSVD_1", - GLBL2_AXIMM_WR1_RSVD_1_MASK}, - {"GLBL2_AXIMM_WR1_BRSP_CNT4", - GLBL2_AXIMM_WR1_BRSP_CNT4_MASK}, - {"GLBL2_AXIMM_WR1_BRSP_CNT3", - GLBL2_AXIMM_WR1_BRSP_CNT3_MASK}, - {"GLBL2_AXIMM_WR1_BRSP_CNT2", - GLBL2_AXIMM_WR1_BRSP_CNT2_MASK}, - {"GLBL2_AXIMM_WR1_BRSP_CNT1", - GLBL2_AXIMM_WR1_BRSP_CNT1_MASK}, - {"GLBL2_AXIMM_WR1_BRSP_CNT0", - GLBL2_AXIMM_WR1_BRSP_CNT0_MASK}, -}; - - -static struct regfield_info - glbl2_dbg_aximm_rd0_field_info[] = { - {"GLBL2_AXIMM_RD0_RSVD_1", - GLBL2_AXIMM_RD0_RSVD_1_MASK}, - {"GLBL2_AXIMM_RD0_PND_CNT", - GLBL2_AXIMM_RD0_PND_CNT_MASK}, - {"GLBL2_AXIMM_RD0_RD_CHNL", - GLBL2_AXIMM_RD0_RD_CHNL_MASK}, - {"GLBL2_AXIMM_RD0_RD_REQ", - GLBL2_AXIMM_RD0_RD_REQ_MASK}, - {"GLBL2_AXIMM_RD0_RRSP_CLAIM_CHNL", - GLBL2_AXIMM_RD0_RRSP_CLAIM_CHNL_MASK}, - {"GLBL2_AXIMM_RD0_RID", - GLBL2_AXIMM_RD0_RID_MASK}, - {"GLBL2_AXIMM_RD0_RVALID", - GLBL2_AXIMM_RD0_RVALID_MASK}, - {"GLBL2_AXIMM_RD0_RREADY", - GLBL2_AXIMM_RD0_RREADY_MASK}, - {"GLBL2_AXIMM_RD0_ARID", - GLBL2_AXIMM_RD0_ARID_MASK}, - {"GLBL2_AXIMM_RD0_ARVALID", - GLBL2_AXIMM_RD0_ARVALID_MASK}, - {"GLBL2_AXIMM_RD0_ARREADY", - GLBL2_AXIMM_RD0_ARREADY_MASK}, -}; - - -static struct regfield_info - glbl2_dbg_aximm_rd1_field_info[] = { - {"GLBL2_AXIMM_RD1_RSVD_1", - GLBL2_AXIMM_RD1_RSVD_1_MASK}, - {"GLBL2_AXIMM_RD1_RRSP_CNT4", - GLBL2_AXIMM_RD1_RRSP_CNT4_MASK}, - {"GLBL2_AXIMM_RD1_RRSP_CNT3", - GLBL2_AXIMM_RD1_RRSP_CNT3_MASK}, - {"GLBL2_AXIMM_RD1_RRSP_CNT2", - GLBL2_AXIMM_RD1_RRSP_CNT2_MASK}, - {"GLBL2_AXIMM_RD1_RRSP_CNT1", - GLBL2_AXIMM_RD1_RRSP_CNT1_MASK}, - {"GLBL2_AXIMM_RD1_RRSP_CNT0", - GLBL2_AXIMM_RD1_RRSP_CNT0_MASK}, -}; - - -static struct regfield_info - glbl_rng_sz_1_field_info[] = { - {"GLBL_RNG_SZ_1_RSVD_1", - GLBL_RNG_SZ_1_RSVD_1_MASK}, - {"GLBL_RNG_SZ_1_RING_SIZE", - GLBL_RNG_SZ_1_RING_SIZE_MASK}, -}; - - -static struct regfield_info - glbl_rng_sz_2_field_info[] = { - {"GLBL_RNG_SZ_2_RSVD_1", - GLBL_RNG_SZ_2_RSVD_1_MASK}, - {"GLBL_RNG_SZ_2_RING_SIZE", - GLBL_RNG_SZ_2_RING_SIZE_MASK}, -}; - - -static struct regfield_info - glbl_rng_sz_3_field_info[] = { - {"GLBL_RNG_SZ_3_RSVD_1", - GLBL_RNG_SZ_3_RSVD_1_MASK}, - {"GLBL_RNG_SZ_3_RING_SIZE", - GLBL_RNG_SZ_3_RING_SIZE_MASK}, -}; - - -static struct regfield_info - glbl_rng_sz_4_field_info[] = { - {"GLBL_RNG_SZ_4_RSVD_1", - GLBL_RNG_SZ_4_RSVD_1_MASK}, - {"GLBL_RNG_SZ_4_RING_SIZE", - GLBL_RNG_SZ_4_RING_SIZE_MASK}, -}; - - -static struct regfield_info - glbl_rng_sz_5_field_info[] = { - {"GLBL_RNG_SZ_5_RSVD_1", - GLBL_RNG_SZ_5_RSVD_1_MASK}, - {"GLBL_RNG_SZ_5_RING_SIZE", - GLBL_RNG_SZ_5_RING_SIZE_MASK}, -}; - - -static struct regfield_info - glbl_rng_sz_6_field_info[] = { - {"GLBL_RNG_SZ_6_RSVD_1", - GLBL_RNG_SZ_6_RSVD_1_MASK}, - {"GLBL_RNG_SZ_6_RING_SIZE", - GLBL_RNG_SZ_6_RING_SIZE_MASK}, -}; - - -static struct regfield_info - glbl_rng_sz_7_field_info[] = { - {"GLBL_RNG_SZ_7_RSVD_1", - GLBL_RNG_SZ_7_RSVD_1_MASK}, - {"GLBL_RNG_SZ_7_RING_SIZE", - GLBL_RNG_SZ_7_RING_SIZE_MASK}, -}; - - -static struct regfield_info - glbl_rng_sz_8_field_info[] = { - {"GLBL_RNG_SZ_8_RSVD_1", - GLBL_RNG_SZ_8_RSVD_1_MASK}, - {"GLBL_RNG_SZ_8_RING_SIZE", - GLBL_RNG_SZ_8_RING_SIZE_MASK}, -}; - - -static struct regfield_info - glbl_rng_sz_9_field_info[] = { - {"GLBL_RNG_SZ_9_RSVD_1", - GLBL_RNG_SZ_9_RSVD_1_MASK}, - {"GLBL_RNG_SZ_9_RING_SIZE", - GLBL_RNG_SZ_9_RING_SIZE_MASK}, -}; - - -static struct regfield_info - glbl_rng_sz_a_field_info[] = { - {"GLBL_RNG_SZ_A_RSVD_1", - GLBL_RNG_SZ_A_RSVD_1_MASK}, - {"GLBL_RNG_SZ_A_RING_SIZE", - GLBL_RNG_SZ_A_RING_SIZE_MASK}, -}; - - -static struct regfield_info - glbl_rng_sz_b_field_info[] = { - {"GLBL_RNG_SZ_B_RSVD_1", - GLBL_RNG_SZ_B_RSVD_1_MASK}, - {"GLBL_RNG_SZ_B_RING_SIZE", - GLBL_RNG_SZ_B_RING_SIZE_MASK}, -}; - - -static struct regfield_info - glbl_rng_sz_c_field_info[] = { - {"GLBL_RNG_SZ_C_RSVD_1", - GLBL_RNG_SZ_C_RSVD_1_MASK}, - {"GLBL_RNG_SZ_C_RING_SIZE", - GLBL_RNG_SZ_C_RING_SIZE_MASK}, -}; - - -static struct regfield_info - glbl_rng_sz_d_field_info[] = { - {"GLBL_RNG_SZ_D_RSVD_1", - GLBL_RNG_SZ_D_RSVD_1_MASK}, - {"GLBL_RNG_SZ_D_RING_SIZE", - GLBL_RNG_SZ_D_RING_SIZE_MASK}, -}; - - -static struct regfield_info - glbl_rng_sz_e_field_info[] = { - {"GLBL_RNG_SZ_E_RSVD_1", - GLBL_RNG_SZ_E_RSVD_1_MASK}, - {"GLBL_RNG_SZ_E_RING_SIZE", - GLBL_RNG_SZ_E_RING_SIZE_MASK}, -}; - - -static struct regfield_info - glbl_rng_sz_f_field_info[] = { - {"GLBL_RNG_SZ_F_RSVD_1", - GLBL_RNG_SZ_F_RSVD_1_MASK}, - {"GLBL_RNG_SZ_F_RING_SIZE", - GLBL_RNG_SZ_F_RING_SIZE_MASK}, -}; - - -static struct regfield_info - glbl_rng_sz_10_field_info[] = { - {"GLBL_RNG_SZ_10_RSVD_1", - GLBL_RNG_SZ_10_RSVD_1_MASK}, - {"GLBL_RNG_SZ_10_RING_SIZE", - GLBL_RNG_SZ_10_RING_SIZE_MASK}, -}; - - -static struct regfield_info - glbl_err_stat_field_info[] = { - {"GLBL_ERR_STAT_RSVD_1", - GLBL_ERR_STAT_RSVD_1_MASK}, - {"GLBL_ERR_STAT_ERR_H2C_ST", - GLBL_ERR_STAT_ERR_H2C_ST_MASK}, - {"GLBL_ERR_STAT_ERR_BDG", - GLBL_ERR_STAT_ERR_BDG_MASK}, - {"GLBL_ERR_STAT_IND_CTXT_CMD_ERR", - GLBL_ERR_STAT_IND_CTXT_CMD_ERR_MASK}, - {"GLBL_ERR_STAT_ERR_C2H_ST", - GLBL_ERR_STAT_ERR_C2H_ST_MASK}, - {"GLBL_ERR_STAT_ERR_C2H_MM_1", - GLBL_ERR_STAT_ERR_C2H_MM_1_MASK}, - {"GLBL_ERR_STAT_ERR_C2H_MM_0", - GLBL_ERR_STAT_ERR_C2H_MM_0_MASK}, - {"GLBL_ERR_STAT_ERR_H2C_MM_1", - GLBL_ERR_STAT_ERR_H2C_MM_1_MASK}, - {"GLBL_ERR_STAT_ERR_H2C_MM_0", - GLBL_ERR_STAT_ERR_H2C_MM_0_MASK}, - {"GLBL_ERR_STAT_ERR_TRQ", - GLBL_ERR_STAT_ERR_TRQ_MASK}, - {"GLBL_ERR_STAT_ERR_DSC", - GLBL_ERR_STAT_ERR_DSC_MASK}, - {"GLBL_ERR_STAT_ERR_RAM_DBE", - GLBL_ERR_STAT_ERR_RAM_DBE_MASK}, - {"GLBL_ERR_STAT_ERR_RAM_SBE", - GLBL_ERR_STAT_ERR_RAM_SBE_MASK}, -}; - - -static struct regfield_info - glbl_err_mask_field_info[] = { - {"GLBL_ERR_RSVD_1", - GLBL_ERR_RSVD_1_MASK}, - {"GLBL_ERR", - GLBL_ERR_MASK}, -}; - - -static struct regfield_info - glbl_dsc_cfg_field_info[] = { - {"GLBL_DSC_CFG_RSVD_1", - GLBL_DSC_CFG_RSVD_1_MASK}, - {"GLBL_DSC_CFG_UNC_OVR_COR", - GLBL_DSC_CFG_UNC_OVR_COR_MASK}, - {"GLBL_DSC_CFG_CTXT_FER_DIS", - GLBL_DSC_CFG_CTXT_FER_DIS_MASK}, - {"GLBL_DSC_CFG_RSVD_2", - GLBL_DSC_CFG_RSVD_2_MASK}, - {"GLBL_DSC_CFG_MAXFETCH", - GLBL_DSC_CFG_MAXFETCH_MASK}, - {"GLBL_DSC_CFG_WB_ACC_INT", - GLBL_DSC_CFG_WB_ACC_INT_MASK}, -}; - - -static struct regfield_info - glbl_dsc_err_sts_field_info[] = { - {"GLBL_DSC_ERR_STS_RSVD_1", - GLBL_DSC_ERR_STS_RSVD_1_MASK}, - {"GLBL_DSC_ERR_STS_SBE", - GLBL_DSC_ERR_STS_SBE_MASK}, - {"GLBL_DSC_ERR_STS_DBE", - GLBL_DSC_ERR_STS_DBE_MASK}, - {"GLBL_DSC_ERR_STS_RQ_CANCEL", - GLBL_DSC_ERR_STS_RQ_CANCEL_MASK}, - {"GLBL_DSC_ERR_STS_DSC", - GLBL_DSC_ERR_STS_DSC_MASK}, - {"GLBL_DSC_ERR_STS_DMA", - GLBL_DSC_ERR_STS_DMA_MASK}, - {"GLBL_DSC_ERR_STS_FLR_CANCEL", - GLBL_DSC_ERR_STS_FLR_CANCEL_MASK}, - {"GLBL_DSC_ERR_STS_RSVD_2", - GLBL_DSC_ERR_STS_RSVD_2_MASK}, - {"GLBL_DSC_ERR_STS_DAT_POISON", - GLBL_DSC_ERR_STS_DAT_POISON_MASK}, - {"GLBL_DSC_ERR_STS_TIMEOUT", - GLBL_DSC_ERR_STS_TIMEOUT_MASK}, - {"GLBL_DSC_ERR_STS_FLR", - GLBL_DSC_ERR_STS_FLR_MASK}, - {"GLBL_DSC_ERR_STS_TAG", - GLBL_DSC_ERR_STS_TAG_MASK}, - {"GLBL_DSC_ERR_STS_ADDR", - GLBL_DSC_ERR_STS_ADDR_MASK}, - {"GLBL_DSC_ERR_STS_PARAM", - GLBL_DSC_ERR_STS_PARAM_MASK}, - {"GLBL_DSC_ERR_STS_UR_CA", - GLBL_DSC_ERR_STS_UR_CA_MASK}, - {"GLBL_DSC_ERR_STS_POISON", - GLBL_DSC_ERR_STS_POISON_MASK}, -}; - - -static struct regfield_info - glbl_dsc_err_msk_field_info[] = { - {"GLBL_DSC_ERR_MSK", - GLBL_DSC_ERR_MSK_MASK}, -}; - - -static struct regfield_info - glbl_dsc_err_log0_field_info[] = { - {"GLBL_DSC_ERR_LOG0_VALID", - GLBL_DSC_ERR_LOG0_VALID_MASK}, - {"GLBL_DSC_ERR_LOG0_RSVD_1", - GLBL_DSC_ERR_LOG0_RSVD_1_MASK}, - {"GLBL_DSC_ERR_LOG0_QID", - GLBL_DSC_ERR_LOG0_QID_MASK}, - {"GLBL_DSC_ERR_LOG0_SEL", - GLBL_DSC_ERR_LOG0_SEL_MASK}, - {"GLBL_DSC_ERR_LOG0_CIDX", - GLBL_DSC_ERR_LOG0_CIDX_MASK}, -}; - - -static struct regfield_info - glbl_dsc_err_log1_field_info[] = { - {"GLBL_DSC_ERR_LOG1_RSVD_1", - GLBL_DSC_ERR_LOG1_RSVD_1_MASK}, - {"GLBL_DSC_ERR_LOG1_SUB_TYPE", - GLBL_DSC_ERR_LOG1_SUB_TYPE_MASK}, - {"GLBL_DSC_ERR_LOG1_ERR_TYPE", - GLBL_DSC_ERR_LOG1_ERR_TYPE_MASK}, -}; - - -static struct regfield_info - glbl_trq_err_sts_field_info[] = { - {"GLBL_TRQ_ERR_STS_RSVD_1", - GLBL_TRQ_ERR_STS_RSVD_1_MASK}, - {"GLBL_TRQ_ERR_STS_TCP_TIMEOUT", - GLBL_TRQ_ERR_STS_TCP_TIMEOUT_MASK}, - {"GLBL_TRQ_ERR_STS_VF_ACCESS_ERR", - GLBL_TRQ_ERR_STS_VF_ACCESS_ERR_MASK}, - {"GLBL_TRQ_ERR_STS_QID_RANGE", - GLBL_TRQ_ERR_STS_QID_RANGE_MASK}, - {"GLBL_TRQ_ERR_STS_UNMAPPED", - GLBL_TRQ_ERR_STS_UNMAPPED_MASK}, -}; - - -static struct regfield_info - glbl_trq_err_msk_field_info[] = { - {"GLBL_TRQ_ERR_MSK", - GLBL_TRQ_ERR_MSK_MASK}, -}; - - -static struct regfield_info - glbl_trq_err_log_field_info[] = { - {"GLBL_TRQ_ERR_LOG_RSVD_1", - GLBL_TRQ_ERR_LOG_RSVD_1_MASK}, - {"GLBL_TRQ_ERR_LOG_TARGET", - GLBL_TRQ_ERR_LOG_TARGET_MASK}, - {"GLBL_TRQ_ERR_LOG_FUNC", - GLBL_TRQ_ERR_LOG_FUNC_MASK}, - {"GLBL_TRQ_ERR_LOG_ADDRESS", - GLBL_TRQ_ERR_LOG_ADDRESS_MASK}, -}; - - -static struct regfield_info - glbl_dsc_dbg_dat0_field_info[] = { - {"GLBL_DSC_DAT0_RSVD_1", - GLBL_DSC_DAT0_RSVD_1_MASK}, - {"GLBL_DSC_DAT0_CTXT_ARB_DIR", - GLBL_DSC_DAT0_CTXT_ARB_DIR_MASK}, - {"GLBL_DSC_DAT0_CTXT_ARB_QID", - GLBL_DSC_DAT0_CTXT_ARB_QID_MASK}, - {"GLBL_DSC_DAT0_CTXT_ARB_REQ", - GLBL_DSC_DAT0_CTXT_ARB_REQ_MASK}, - {"GLBL_DSC_DAT0_IRQ_FIFO_FL", - GLBL_DSC_DAT0_IRQ_FIFO_FL_MASK}, - {"GLBL_DSC_DAT0_TMSTALL", - GLBL_DSC_DAT0_TMSTALL_MASK}, - {"GLBL_DSC_DAT0_RRQ_STALL", - GLBL_DSC_DAT0_RRQ_STALL_MASK}, - {"GLBL_DSC_DAT0_RCP_FIFO_SPC_STALL", - GLBL_DSC_DAT0_RCP_FIFO_SPC_STALL_MASK}, - {"GLBL_DSC_DAT0_RRQ_FIFO_SPC_STALL", - GLBL_DSC_DAT0_RRQ_FIFO_SPC_STALL_MASK}, - {"GLBL_DSC_DAT0_FAB_MRKR_RSP_STALL", - GLBL_DSC_DAT0_FAB_MRKR_RSP_STALL_MASK}, - {"GLBL_DSC_DAT0_DSC_OUT_STALL", - GLBL_DSC_DAT0_DSC_OUT_STALL_MASK}, -}; - - -static struct regfield_info - glbl_dsc_dbg_dat1_field_info[] = { - {"GLBL_DSC_DAT1_RSVD_1", - GLBL_DSC_DAT1_RSVD_1_MASK}, - {"GLBL_DSC_DAT1_EVT_SPC_C2H", - GLBL_DSC_DAT1_EVT_SPC_C2H_MASK}, - {"GLBL_DSC_DAT1_EVT_SP_H2C", - GLBL_DSC_DAT1_EVT_SP_H2C_MASK}, - {"GLBL_DSC_DAT1_DSC_SPC_C2H", - GLBL_DSC_DAT1_DSC_SPC_C2H_MASK}, - {"GLBL_DSC_DAT1_DSC_SPC_H2C", - GLBL_DSC_DAT1_DSC_SPC_H2C_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_0_field_info[] = { - {"TRQ_SEL_FMAP_0_RSVD_1", - TRQ_SEL_FMAP_0_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_0_QID_MAX", - TRQ_SEL_FMAP_0_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_0_QID_BASE", - TRQ_SEL_FMAP_0_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_1_field_info[] = { - {"TRQ_SEL_FMAP_1_RSVD_1", - TRQ_SEL_FMAP_1_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_1_QID_MAX", - TRQ_SEL_FMAP_1_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_1_QID_BASE", - TRQ_SEL_FMAP_1_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_2_field_info[] = { - {"TRQ_SEL_FMAP_2_RSVD_1", - TRQ_SEL_FMAP_2_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_2_QID_MAX", - TRQ_SEL_FMAP_2_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_2_QID_BASE", - TRQ_SEL_FMAP_2_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_3_field_info[] = { - {"TRQ_SEL_FMAP_3_RSVD_1", - TRQ_SEL_FMAP_3_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_3_QID_MAX", - TRQ_SEL_FMAP_3_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_3_QID_BASE", - TRQ_SEL_FMAP_3_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_4_field_info[] = { - {"TRQ_SEL_FMAP_4_RSVD_1", - TRQ_SEL_FMAP_4_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_4_QID_MAX", - TRQ_SEL_FMAP_4_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_4_QID_BASE", - TRQ_SEL_FMAP_4_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_5_field_info[] = { - {"TRQ_SEL_FMAP_5_RSVD_1", - TRQ_SEL_FMAP_5_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_5_QID_MAX", - TRQ_SEL_FMAP_5_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_5_QID_BASE", - TRQ_SEL_FMAP_5_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_6_field_info[] = { - {"TRQ_SEL_FMAP_6_RSVD_1", - TRQ_SEL_FMAP_6_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_6_QID_MAX", - TRQ_SEL_FMAP_6_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_6_QID_BASE", - TRQ_SEL_FMAP_6_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_7_field_info[] = { - {"TRQ_SEL_FMAP_7_RSVD_1", - TRQ_SEL_FMAP_7_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_7_QID_MAX", - TRQ_SEL_FMAP_7_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_7_QID_BASE", - TRQ_SEL_FMAP_7_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_8_field_info[] = { - {"TRQ_SEL_FMAP_8_RSVD_1", - TRQ_SEL_FMAP_8_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_8_QID_MAX", - TRQ_SEL_FMAP_8_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_8_QID_BASE", - TRQ_SEL_FMAP_8_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_9_field_info[] = { - {"TRQ_SEL_FMAP_9_RSVD_1", - TRQ_SEL_FMAP_9_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_9_QID_MAX", - TRQ_SEL_FMAP_9_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_9_QID_BASE", - TRQ_SEL_FMAP_9_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_a_field_info[] = { - {"TRQ_SEL_FMAP_A_RSVD_1", - TRQ_SEL_FMAP_A_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_A_QID_MAX", - TRQ_SEL_FMAP_A_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_A_QID_BASE", - TRQ_SEL_FMAP_A_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_b_field_info[] = { - {"TRQ_SEL_FMAP_B_RSVD_1", - TRQ_SEL_FMAP_B_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_B_QID_MAX", - TRQ_SEL_FMAP_B_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_B_QID_BASE", - TRQ_SEL_FMAP_B_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_d_field_info[] = { - {"TRQ_SEL_FMAP_D_RSVD_1", - TRQ_SEL_FMAP_D_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_D_QID_MAX", - TRQ_SEL_FMAP_D_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_D_QID_BASE", - TRQ_SEL_FMAP_D_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_e_field_info[] = { - {"TRQ_SEL_FMAP_E_RSVD_1", - TRQ_SEL_FMAP_E_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_E_QID_MAX", - TRQ_SEL_FMAP_E_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_E_QID_BASE", - TRQ_SEL_FMAP_E_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_f_field_info[] = { - {"TRQ_SEL_FMAP_F_RSVD_1", - TRQ_SEL_FMAP_F_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_F_QID_MAX", - TRQ_SEL_FMAP_F_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_F_QID_BASE", - TRQ_SEL_FMAP_F_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_10_field_info[] = { - {"TRQ_SEL_FMAP_10_RSVD_1", - TRQ_SEL_FMAP_10_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_10_QID_MAX", - TRQ_SEL_FMAP_10_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_10_QID_BASE", - TRQ_SEL_FMAP_10_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_11_field_info[] = { - {"TRQ_SEL_FMAP_11_RSVD_1", - TRQ_SEL_FMAP_11_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_11_QID_MAX", - TRQ_SEL_FMAP_11_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_11_QID_BASE", - TRQ_SEL_FMAP_11_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_12_field_info[] = { - {"TRQ_SEL_FMAP_12_RSVD_1", - TRQ_SEL_FMAP_12_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_12_QID_MAX", - TRQ_SEL_FMAP_12_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_12_QID_BASE", - TRQ_SEL_FMAP_12_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_13_field_info[] = { - {"TRQ_SEL_FMAP_13_RSVD_1", - TRQ_SEL_FMAP_13_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_13_QID_MAX", - TRQ_SEL_FMAP_13_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_13_QID_BASE", - TRQ_SEL_FMAP_13_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_14_field_info[] = { - {"TRQ_SEL_FMAP_14_RSVD_1", - TRQ_SEL_FMAP_14_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_14_QID_MAX", - TRQ_SEL_FMAP_14_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_14_QID_BASE", - TRQ_SEL_FMAP_14_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_15_field_info[] = { - {"TRQ_SEL_FMAP_15_RSVD_1", - TRQ_SEL_FMAP_15_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_15_QID_MAX", - TRQ_SEL_FMAP_15_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_15_QID_BASE", - TRQ_SEL_FMAP_15_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_16_field_info[] = { - {"TRQ_SEL_FMAP_16_RSVD_1", - TRQ_SEL_FMAP_16_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_16_QID_MAX", - TRQ_SEL_FMAP_16_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_16_QID_BASE", - TRQ_SEL_FMAP_16_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_17_field_info[] = { - {"TRQ_SEL_FMAP_17_RSVD_1", - TRQ_SEL_FMAP_17_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_17_QID_MAX", - TRQ_SEL_FMAP_17_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_17_QID_BASE", - TRQ_SEL_FMAP_17_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_18_field_info[] = { - {"TRQ_SEL_FMAP_18_RSVD_1", - TRQ_SEL_FMAP_18_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_18_QID_MAX", - TRQ_SEL_FMAP_18_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_18_QID_BASE", - TRQ_SEL_FMAP_18_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_19_field_info[] = { - {"TRQ_SEL_FMAP_19_RSVD_1", - TRQ_SEL_FMAP_19_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_19_QID_MAX", - TRQ_SEL_FMAP_19_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_19_QID_BASE", - TRQ_SEL_FMAP_19_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_1a_field_info[] = { - {"TRQ_SEL_FMAP_1A_RSVD_1", - TRQ_SEL_FMAP_1A_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_1A_QID_MAX", - TRQ_SEL_FMAP_1A_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_1A_QID_BASE", - TRQ_SEL_FMAP_1A_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_1b_field_info[] = { - {"TRQ_SEL_FMAP_1B_RSVD_1", - TRQ_SEL_FMAP_1B_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_1B_QID_MAX", - TRQ_SEL_FMAP_1B_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_1B_QID_BASE", - TRQ_SEL_FMAP_1B_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_1c_field_info[] = { - {"TRQ_SEL_FMAP_1C_RSVD_1", - TRQ_SEL_FMAP_1C_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_1C_QID_MAX", - TRQ_SEL_FMAP_1C_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_1C_QID_BASE", - TRQ_SEL_FMAP_1C_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_1d_field_info[] = { - {"TRQ_SEL_FMAP_1D_RSVD_1", - TRQ_SEL_FMAP_1D_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_1D_QID_MAX", - TRQ_SEL_FMAP_1D_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_1D_QID_BASE", - TRQ_SEL_FMAP_1D_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_1e_field_info[] = { - {"TRQ_SEL_FMAP_1E_RSVD_1", - TRQ_SEL_FMAP_1E_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_1E_QID_MAX", - TRQ_SEL_FMAP_1E_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_1E_QID_BASE", - TRQ_SEL_FMAP_1E_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_1f_field_info[] = { - {"TRQ_SEL_FMAP_1F_RSVD_1", - TRQ_SEL_FMAP_1F_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_1F_QID_MAX", - TRQ_SEL_FMAP_1F_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_1F_QID_BASE", - TRQ_SEL_FMAP_1F_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_20_field_info[] = { - {"TRQ_SEL_FMAP_20_RSVD_1", - TRQ_SEL_FMAP_20_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_20_QID_MAX", - TRQ_SEL_FMAP_20_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_20_QID_BASE", - TRQ_SEL_FMAP_20_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_21_field_info[] = { - {"TRQ_SEL_FMAP_21_RSVD_1", - TRQ_SEL_FMAP_21_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_21_QID_MAX", - TRQ_SEL_FMAP_21_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_21_QID_BASE", - TRQ_SEL_FMAP_21_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_22_field_info[] = { - {"TRQ_SEL_FMAP_22_RSVD_1", - TRQ_SEL_FMAP_22_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_22_QID_MAX", - TRQ_SEL_FMAP_22_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_22_QID_BASE", - TRQ_SEL_FMAP_22_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_23_field_info[] = { - {"TRQ_SEL_FMAP_23_RSVD_1", - TRQ_SEL_FMAP_23_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_23_QID_MAX", - TRQ_SEL_FMAP_23_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_23_QID_BASE", - TRQ_SEL_FMAP_23_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_24_field_info[] = { - {"TRQ_SEL_FMAP_24_RSVD_1", - TRQ_SEL_FMAP_24_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_24_QID_MAX", - TRQ_SEL_FMAP_24_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_24_QID_BASE", - TRQ_SEL_FMAP_24_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_25_field_info[] = { - {"TRQ_SEL_FMAP_25_RSVD_1", - TRQ_SEL_FMAP_25_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_25_QID_MAX", - TRQ_SEL_FMAP_25_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_25_QID_BASE", - TRQ_SEL_FMAP_25_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_26_field_info[] = { - {"TRQ_SEL_FMAP_26_RSVD_1", - TRQ_SEL_FMAP_26_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_26_QID_MAX", - TRQ_SEL_FMAP_26_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_26_QID_BASE", - TRQ_SEL_FMAP_26_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_27_field_info[] = { - {"TRQ_SEL_FMAP_27_RSVD_1", - TRQ_SEL_FMAP_27_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_27_QID_MAX", - TRQ_SEL_FMAP_27_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_27_QID_BASE", - TRQ_SEL_FMAP_27_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_28_field_info[] = { - {"TRQ_SEL_FMAP_28_RSVD_1", - TRQ_SEL_FMAP_28_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_28_QID_MAX", - TRQ_SEL_FMAP_28_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_28_QID_BASE", - TRQ_SEL_FMAP_28_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_29_field_info[] = { - {"TRQ_SEL_FMAP_29_RSVD_1", - TRQ_SEL_FMAP_29_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_29_QID_MAX", - TRQ_SEL_FMAP_29_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_29_QID_BASE", - TRQ_SEL_FMAP_29_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_2a_field_info[] = { - {"TRQ_SEL_FMAP_2A_RSVD_1", - TRQ_SEL_FMAP_2A_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_2A_QID_MAX", - TRQ_SEL_FMAP_2A_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_2A_QID_BASE", - TRQ_SEL_FMAP_2A_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_2b_field_info[] = { - {"TRQ_SEL_FMAP_2B_RSVD_1", - TRQ_SEL_FMAP_2B_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_2B_QID_MAX", - TRQ_SEL_FMAP_2B_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_2B_QID_BASE", - TRQ_SEL_FMAP_2B_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_2c_field_info[] = { - {"TRQ_SEL_FMAP_2C_RSVD_1", - TRQ_SEL_FMAP_2C_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_2C_QID_MAX", - TRQ_SEL_FMAP_2C_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_2C_QID_BASE", - TRQ_SEL_FMAP_2C_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_2d_field_info[] = { - {"TRQ_SEL_FMAP_2D_RSVD_1", - TRQ_SEL_FMAP_2D_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_2D_QID_MAX", - TRQ_SEL_FMAP_2D_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_2D_QID_BASE", - TRQ_SEL_FMAP_2D_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_2e_field_info[] = { - {"TRQ_SEL_FMAP_2E_RSVD_1", - TRQ_SEL_FMAP_2E_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_2E_QID_MAX", - TRQ_SEL_FMAP_2E_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_2E_QID_BASE", - TRQ_SEL_FMAP_2E_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_2f_field_info[] = { - {"TRQ_SEL_FMAP_2F_RSVD_1", - TRQ_SEL_FMAP_2F_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_2F_QID_MAX", - TRQ_SEL_FMAP_2F_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_2F_QID_BASE", - TRQ_SEL_FMAP_2F_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_30_field_info[] = { - {"TRQ_SEL_FMAP_30_RSVD_1", - TRQ_SEL_FMAP_30_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_30_QID_MAX", - TRQ_SEL_FMAP_30_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_30_QID_BASE", - TRQ_SEL_FMAP_30_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_31_field_info[] = { - {"TRQ_SEL_FMAP_31_RSVD_1", - TRQ_SEL_FMAP_31_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_31_QID_MAX", - TRQ_SEL_FMAP_31_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_31_QID_BASE", - TRQ_SEL_FMAP_31_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_32_field_info[] = { - {"TRQ_SEL_FMAP_32_RSVD_1", - TRQ_SEL_FMAP_32_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_32_QID_MAX", - TRQ_SEL_FMAP_32_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_32_QID_BASE", - TRQ_SEL_FMAP_32_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_33_field_info[] = { - {"TRQ_SEL_FMAP_33_RSVD_1", - TRQ_SEL_FMAP_33_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_33_QID_MAX", - TRQ_SEL_FMAP_33_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_33_QID_BASE", - TRQ_SEL_FMAP_33_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_34_field_info[] = { - {"TRQ_SEL_FMAP_34_RSVD_1", - TRQ_SEL_FMAP_34_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_34_QID_MAX", - TRQ_SEL_FMAP_34_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_34_QID_BASE", - TRQ_SEL_FMAP_34_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_35_field_info[] = { - {"TRQ_SEL_FMAP_35_RSVD_1", - TRQ_SEL_FMAP_35_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_35_QID_MAX", - TRQ_SEL_FMAP_35_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_35_QID_BASE", - TRQ_SEL_FMAP_35_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_36_field_info[] = { - {"TRQ_SEL_FMAP_36_RSVD_1", - TRQ_SEL_FMAP_36_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_36_QID_MAX", - TRQ_SEL_FMAP_36_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_36_QID_BASE", - TRQ_SEL_FMAP_36_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_37_field_info[] = { - {"TRQ_SEL_FMAP_37_RSVD_1", - TRQ_SEL_FMAP_37_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_37_QID_MAX", - TRQ_SEL_FMAP_37_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_37_QID_BASE", - TRQ_SEL_FMAP_37_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_38_field_info[] = { - {"TRQ_SEL_FMAP_38_RSVD_1", - TRQ_SEL_FMAP_38_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_38_QID_MAX", - TRQ_SEL_FMAP_38_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_38_QID_BASE", - TRQ_SEL_FMAP_38_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_39_field_info[] = { - {"TRQ_SEL_FMAP_39_RSVD_1", - TRQ_SEL_FMAP_39_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_39_QID_MAX", - TRQ_SEL_FMAP_39_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_39_QID_BASE", - TRQ_SEL_FMAP_39_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_3a_field_info[] = { - {"TRQ_SEL_FMAP_3A_RSVD_1", - TRQ_SEL_FMAP_3A_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_3A_QID_MAX", - TRQ_SEL_FMAP_3A_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_3A_QID_BASE", - TRQ_SEL_FMAP_3A_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_3b_field_info[] = { - {"TRQ_SEL_FMAP_3B_RSVD_1", - TRQ_SEL_FMAP_3B_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_3B_QID_MAX", - TRQ_SEL_FMAP_3B_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_3B_QID_BASE", - TRQ_SEL_FMAP_3B_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_3c_field_info[] = { - {"TRQ_SEL_FMAP_3C_RSVD_1", - TRQ_SEL_FMAP_3C_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_3C_QID_MAX", - TRQ_SEL_FMAP_3C_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_3C_QID_BASE", - TRQ_SEL_FMAP_3C_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_3d_field_info[] = { - {"TRQ_SEL_FMAP_3D_RSVD_1", - TRQ_SEL_FMAP_3D_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_3D_QID_MAX", - TRQ_SEL_FMAP_3D_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_3D_QID_BASE", - TRQ_SEL_FMAP_3D_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_3e_field_info[] = { - {"TRQ_SEL_FMAP_3E_RSVD_1", - TRQ_SEL_FMAP_3E_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_3E_QID_MAX", - TRQ_SEL_FMAP_3E_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_3E_QID_BASE", - TRQ_SEL_FMAP_3E_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_3f_field_info[] = { - {"TRQ_SEL_FMAP_3F_RSVD_1", - TRQ_SEL_FMAP_3F_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_3F_QID_MAX", - TRQ_SEL_FMAP_3F_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_3F_QID_BASE", - TRQ_SEL_FMAP_3F_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_40_field_info[] = { - {"TRQ_SEL_FMAP_40_RSVD_1", - TRQ_SEL_FMAP_40_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_40_QID_MAX", - TRQ_SEL_FMAP_40_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_40_QID_BASE", - TRQ_SEL_FMAP_40_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_41_field_info[] = { - {"TRQ_SEL_FMAP_41_RSVD_1", - TRQ_SEL_FMAP_41_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_41_QID_MAX", - TRQ_SEL_FMAP_41_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_41_QID_BASE", - TRQ_SEL_FMAP_41_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_42_field_info[] = { - {"TRQ_SEL_FMAP_42_RSVD_1", - TRQ_SEL_FMAP_42_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_42_QID_MAX", - TRQ_SEL_FMAP_42_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_42_QID_BASE", - TRQ_SEL_FMAP_42_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_43_field_info[] = { - {"TRQ_SEL_FMAP_43_RSVD_1", - TRQ_SEL_FMAP_43_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_43_QID_MAX", - TRQ_SEL_FMAP_43_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_43_QID_BASE", - TRQ_SEL_FMAP_43_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_44_field_info[] = { - {"TRQ_SEL_FMAP_44_RSVD_1", - TRQ_SEL_FMAP_44_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_44_QID_MAX", - TRQ_SEL_FMAP_44_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_44_QID_BASE", - TRQ_SEL_FMAP_44_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_45_field_info[] = { - {"TRQ_SEL_FMAP_45_RSVD_1", - TRQ_SEL_FMAP_45_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_45_QID_MAX", - TRQ_SEL_FMAP_45_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_45_QID_BASE", - TRQ_SEL_FMAP_45_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_46_field_info[] = { - {"TRQ_SEL_FMAP_46_RSVD_1", - TRQ_SEL_FMAP_46_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_46_QID_MAX", - TRQ_SEL_FMAP_46_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_46_QID_BASE", - TRQ_SEL_FMAP_46_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_47_field_info[] = { - {"TRQ_SEL_FMAP_47_RSVD_1", - TRQ_SEL_FMAP_47_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_47_QID_MAX", - TRQ_SEL_FMAP_47_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_47_QID_BASE", - TRQ_SEL_FMAP_47_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_48_field_info[] = { - {"TRQ_SEL_FMAP_48_RSVD_1", - TRQ_SEL_FMAP_48_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_48_QID_MAX", - TRQ_SEL_FMAP_48_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_48_QID_BASE", - TRQ_SEL_FMAP_48_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_49_field_info[] = { - {"TRQ_SEL_FMAP_49_RSVD_1", - TRQ_SEL_FMAP_49_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_49_QID_MAX", - TRQ_SEL_FMAP_49_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_49_QID_BASE", - TRQ_SEL_FMAP_49_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_4a_field_info[] = { - {"TRQ_SEL_FMAP_4A_RSVD_1", - TRQ_SEL_FMAP_4A_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_4A_QID_MAX", - TRQ_SEL_FMAP_4A_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_4A_QID_BASE", - TRQ_SEL_FMAP_4A_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_4b_field_info[] = { - {"TRQ_SEL_FMAP_4B_RSVD_1", - TRQ_SEL_FMAP_4B_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_4B_QID_MAX", - TRQ_SEL_FMAP_4B_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_4B_QID_BASE", - TRQ_SEL_FMAP_4B_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_4c_field_info[] = { - {"TRQ_SEL_FMAP_4C_RSVD_1", - TRQ_SEL_FMAP_4C_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_4C_QID_MAX", - TRQ_SEL_FMAP_4C_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_4C_QID_BASE", - TRQ_SEL_FMAP_4C_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_4d_field_info[] = { - {"TRQ_SEL_FMAP_4D_RSVD_1", - TRQ_SEL_FMAP_4D_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_4D_QID_MAX", - TRQ_SEL_FMAP_4D_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_4D_QID_BASE", - TRQ_SEL_FMAP_4D_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_4e_field_info[] = { - {"TRQ_SEL_FMAP_4E_RSVD_1", - TRQ_SEL_FMAP_4E_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_4E_QID_MAX", - TRQ_SEL_FMAP_4E_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_4E_QID_BASE", - TRQ_SEL_FMAP_4E_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_4f_field_info[] = { - {"TRQ_SEL_FMAP_4F_RSVD_1", - TRQ_SEL_FMAP_4F_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_4F_QID_MAX", - TRQ_SEL_FMAP_4F_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_4F_QID_BASE", - TRQ_SEL_FMAP_4F_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_50_field_info[] = { - {"TRQ_SEL_FMAP_50_RSVD_1", - TRQ_SEL_FMAP_50_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_50_QID_MAX", - TRQ_SEL_FMAP_50_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_50_QID_BASE", - TRQ_SEL_FMAP_50_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_51_field_info[] = { - {"TRQ_SEL_FMAP_51_RSVD_1", - TRQ_SEL_FMAP_51_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_51_QID_MAX", - TRQ_SEL_FMAP_51_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_51_QID_BASE", - TRQ_SEL_FMAP_51_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_52_field_info[] = { - {"TRQ_SEL_FMAP_52_RSVD_1", - TRQ_SEL_FMAP_52_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_52_QID_MAX", - TRQ_SEL_FMAP_52_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_52_QID_BASE", - TRQ_SEL_FMAP_52_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_53_field_info[] = { - {"TRQ_SEL_FMAP_53_RSVD_1", - TRQ_SEL_FMAP_53_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_53_QID_MAX", - TRQ_SEL_FMAP_53_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_53_QID_BASE", - TRQ_SEL_FMAP_53_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_54_field_info[] = { - {"TRQ_SEL_FMAP_54_RSVD_1", - TRQ_SEL_FMAP_54_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_54_QID_MAX", - TRQ_SEL_FMAP_54_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_54_QID_BASE", - TRQ_SEL_FMAP_54_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_55_field_info[] = { - {"TRQ_SEL_FMAP_55_RSVD_1", - TRQ_SEL_FMAP_55_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_55_QID_MAX", - TRQ_SEL_FMAP_55_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_55_QID_BASE", - TRQ_SEL_FMAP_55_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_56_field_info[] = { - {"TRQ_SEL_FMAP_56_RSVD_1", - TRQ_SEL_FMAP_56_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_56_QID_MAX", - TRQ_SEL_FMAP_56_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_56_QID_BASE", - TRQ_SEL_FMAP_56_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_57_field_info[] = { - {"TRQ_SEL_FMAP_57_RSVD_1", - TRQ_SEL_FMAP_57_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_57_QID_MAX", - TRQ_SEL_FMAP_57_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_57_QID_BASE", - TRQ_SEL_FMAP_57_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_58_field_info[] = { - {"TRQ_SEL_FMAP_58_RSVD_1", - TRQ_SEL_FMAP_58_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_58_QID_MAX", - TRQ_SEL_FMAP_58_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_58_QID_BASE", - TRQ_SEL_FMAP_58_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_59_field_info[] = { - {"TRQ_SEL_FMAP_59_RSVD_1", - TRQ_SEL_FMAP_59_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_59_QID_MAX", - TRQ_SEL_FMAP_59_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_59_QID_BASE", - TRQ_SEL_FMAP_59_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_5a_field_info[] = { - {"TRQ_SEL_FMAP_5A_RSVD_1", - TRQ_SEL_FMAP_5A_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_5A_QID_MAX", - TRQ_SEL_FMAP_5A_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_5A_QID_BASE", - TRQ_SEL_FMAP_5A_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_5b_field_info[] = { - {"TRQ_SEL_FMAP_5B_RSVD_1", - TRQ_SEL_FMAP_5B_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_5B_QID_MAX", - TRQ_SEL_FMAP_5B_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_5B_QID_BASE", - TRQ_SEL_FMAP_5B_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_5c_field_info[] = { - {"TRQ_SEL_FMAP_5C_RSVD_1", - TRQ_SEL_FMAP_5C_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_5C_QID_MAX", - TRQ_SEL_FMAP_5C_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_5C_QID_BASE", - TRQ_SEL_FMAP_5C_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_5d_field_info[] = { - {"TRQ_SEL_FMAP_5D_RSVD_1", - TRQ_SEL_FMAP_5D_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_5D_QID_MAX", - TRQ_SEL_FMAP_5D_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_5D_QID_BASE", - TRQ_SEL_FMAP_5D_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_5e_field_info[] = { - {"TRQ_SEL_FMAP_5E_RSVD_1", - TRQ_SEL_FMAP_5E_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_5E_QID_MAX", - TRQ_SEL_FMAP_5E_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_5E_QID_BASE", - TRQ_SEL_FMAP_5E_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_5f_field_info[] = { - {"TRQ_SEL_FMAP_5F_RSVD_1", - TRQ_SEL_FMAP_5F_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_5F_QID_MAX", - TRQ_SEL_FMAP_5F_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_5F_QID_BASE", - TRQ_SEL_FMAP_5F_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_60_field_info[] = { - {"TRQ_SEL_FMAP_60_RSVD_1", - TRQ_SEL_FMAP_60_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_60_QID_MAX", - TRQ_SEL_FMAP_60_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_60_QID_BASE", - TRQ_SEL_FMAP_60_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_61_field_info[] = { - {"TRQ_SEL_FMAP_61_RSVD_1", - TRQ_SEL_FMAP_61_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_61_QID_MAX", - TRQ_SEL_FMAP_61_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_61_QID_BASE", - TRQ_SEL_FMAP_61_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_62_field_info[] = { - {"TRQ_SEL_FMAP_62_RSVD_1", - TRQ_SEL_FMAP_62_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_62_QID_MAX", - TRQ_SEL_FMAP_62_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_62_QID_BASE", - TRQ_SEL_FMAP_62_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_63_field_info[] = { - {"TRQ_SEL_FMAP_63_RSVD_1", - TRQ_SEL_FMAP_63_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_63_QID_MAX", - TRQ_SEL_FMAP_63_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_63_QID_BASE", - TRQ_SEL_FMAP_63_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_64_field_info[] = { - {"TRQ_SEL_FMAP_64_RSVD_1", - TRQ_SEL_FMAP_64_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_64_QID_MAX", - TRQ_SEL_FMAP_64_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_64_QID_BASE", - TRQ_SEL_FMAP_64_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_65_field_info[] = { - {"TRQ_SEL_FMAP_65_RSVD_1", - TRQ_SEL_FMAP_65_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_65_QID_MAX", - TRQ_SEL_FMAP_65_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_65_QID_BASE", - TRQ_SEL_FMAP_65_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_66_field_info[] = { - {"TRQ_SEL_FMAP_66_RSVD_1", - TRQ_SEL_FMAP_66_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_66_QID_MAX", - TRQ_SEL_FMAP_66_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_66_QID_BASE", - TRQ_SEL_FMAP_66_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_67_field_info[] = { - {"TRQ_SEL_FMAP_67_RSVD_1", - TRQ_SEL_FMAP_67_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_67_QID_MAX", - TRQ_SEL_FMAP_67_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_67_QID_BASE", - TRQ_SEL_FMAP_67_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_68_field_info[] = { - {"TRQ_SEL_FMAP_68_RSVD_1", - TRQ_SEL_FMAP_68_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_68_QID_MAX", - TRQ_SEL_FMAP_68_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_68_QID_BASE", - TRQ_SEL_FMAP_68_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_69_field_info[] = { - {"TRQ_SEL_FMAP_69_RSVD_1", - TRQ_SEL_FMAP_69_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_69_QID_MAX", - TRQ_SEL_FMAP_69_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_69_QID_BASE", - TRQ_SEL_FMAP_69_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_6a_field_info[] = { - {"TRQ_SEL_FMAP_6A_RSVD_1", - TRQ_SEL_FMAP_6A_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_6A_QID_MAX", - TRQ_SEL_FMAP_6A_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_6A_QID_BASE", - TRQ_SEL_FMAP_6A_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_6b_field_info[] = { - {"TRQ_SEL_FMAP_6B_RSVD_1", - TRQ_SEL_FMAP_6B_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_6B_QID_MAX", - TRQ_SEL_FMAP_6B_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_6B_QID_BASE", - TRQ_SEL_FMAP_6B_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_6c_field_info[] = { - {"TRQ_SEL_FMAP_6C_RSVD_1", - TRQ_SEL_FMAP_6C_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_6C_QID_MAX", - TRQ_SEL_FMAP_6C_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_6C_QID_BASE", - TRQ_SEL_FMAP_6C_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_6d_field_info[] = { - {"TRQ_SEL_FMAP_6D_RSVD_1", - TRQ_SEL_FMAP_6D_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_6D_QID_MAX", - TRQ_SEL_FMAP_6D_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_6D_QID_BASE", - TRQ_SEL_FMAP_6D_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_6e_field_info[] = { - {"TRQ_SEL_FMAP_6E_RSVD_1", - TRQ_SEL_FMAP_6E_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_6E_QID_MAX", - TRQ_SEL_FMAP_6E_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_6E_QID_BASE", - TRQ_SEL_FMAP_6E_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_6f_field_info[] = { - {"TRQ_SEL_FMAP_6F_RSVD_1", - TRQ_SEL_FMAP_6F_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_6F_QID_MAX", - TRQ_SEL_FMAP_6F_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_6F_QID_BASE", - TRQ_SEL_FMAP_6F_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_70_field_info[] = { - {"TRQ_SEL_FMAP_70_RSVD_1", - TRQ_SEL_FMAP_70_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_70_QID_MAX", - TRQ_SEL_FMAP_70_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_70_QID_BASE", - TRQ_SEL_FMAP_70_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_71_field_info[] = { - {"TRQ_SEL_FMAP_71_RSVD_1", - TRQ_SEL_FMAP_71_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_71_QID_MAX", - TRQ_SEL_FMAP_71_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_71_QID_BASE", - TRQ_SEL_FMAP_71_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_72_field_info[] = { - {"TRQ_SEL_FMAP_72_RSVD_1", - TRQ_SEL_FMAP_72_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_72_QID_MAX", - TRQ_SEL_FMAP_72_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_72_QID_BASE", - TRQ_SEL_FMAP_72_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_73_field_info[] = { - {"TRQ_SEL_FMAP_73_RSVD_1", - TRQ_SEL_FMAP_73_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_73_QID_MAX", - TRQ_SEL_FMAP_73_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_73_QID_BASE", - TRQ_SEL_FMAP_73_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_74_field_info[] = { - {"TRQ_SEL_FMAP_74_RSVD_1", - TRQ_SEL_FMAP_74_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_74_QID_MAX", - TRQ_SEL_FMAP_74_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_74_QID_BASE", - TRQ_SEL_FMAP_74_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_75_field_info[] = { - {"TRQ_SEL_FMAP_75_RSVD_1", - TRQ_SEL_FMAP_75_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_75_QID_MAX", - TRQ_SEL_FMAP_75_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_75_QID_BASE", - TRQ_SEL_FMAP_75_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_76_field_info[] = { - {"TRQ_SEL_FMAP_76_RSVD_1", - TRQ_SEL_FMAP_76_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_76_QID_MAX", - TRQ_SEL_FMAP_76_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_76_QID_BASE", - TRQ_SEL_FMAP_76_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_77_field_info[] = { - {"TRQ_SEL_FMAP_77_RSVD_1", - TRQ_SEL_FMAP_77_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_77_QID_MAX", - TRQ_SEL_FMAP_77_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_77_QID_BASE", - TRQ_SEL_FMAP_77_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_78_field_info[] = { - {"TRQ_SEL_FMAP_78_RSVD_1", - TRQ_SEL_FMAP_78_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_78_QID_MAX", - TRQ_SEL_FMAP_78_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_78_QID_BASE", - TRQ_SEL_FMAP_78_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_79_field_info[] = { - {"TRQ_SEL_FMAP_79_RSVD_1", - TRQ_SEL_FMAP_79_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_79_QID_MAX", - TRQ_SEL_FMAP_79_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_79_QID_BASE", - TRQ_SEL_FMAP_79_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_7a_field_info[] = { - {"TRQ_SEL_FMAP_7A_RSVD_1", - TRQ_SEL_FMAP_7A_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_7A_QID_MAX", - TRQ_SEL_FMAP_7A_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_7A_QID_BASE", - TRQ_SEL_FMAP_7A_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_7b_field_info[] = { - {"TRQ_SEL_FMAP_7B_RSVD_1", - TRQ_SEL_FMAP_7B_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_7B_QID_MAX", - TRQ_SEL_FMAP_7B_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_7B_QID_BASE", - TRQ_SEL_FMAP_7B_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_7c_field_info[] = { - {"TRQ_SEL_FMAP_7C_RSVD_1", - TRQ_SEL_FMAP_7C_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_7C_QID_MAX", - TRQ_SEL_FMAP_7C_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_7C_QID_BASE", - TRQ_SEL_FMAP_7C_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_7d_field_info[] = { - {"TRQ_SEL_FMAP_7D_RSVD_1", - TRQ_SEL_FMAP_7D_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_7D_QID_MAX", - TRQ_SEL_FMAP_7D_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_7D_QID_BASE", - TRQ_SEL_FMAP_7D_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_7e_field_info[] = { - {"TRQ_SEL_FMAP_7E_RSVD_1", - TRQ_SEL_FMAP_7E_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_7E_QID_MAX", - TRQ_SEL_FMAP_7E_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_7E_QID_BASE", - TRQ_SEL_FMAP_7E_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_7f_field_info[] = { - {"TRQ_SEL_FMAP_7F_RSVD_1", - TRQ_SEL_FMAP_7F_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_7F_QID_MAX", - TRQ_SEL_FMAP_7F_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_7F_QID_BASE", - TRQ_SEL_FMAP_7F_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_80_field_info[] = { - {"TRQ_SEL_FMAP_80_RSVD_1", - TRQ_SEL_FMAP_80_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_80_QID_MAX", - TRQ_SEL_FMAP_80_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_80_QID_BASE", - TRQ_SEL_FMAP_80_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_81_field_info[] = { - {"TRQ_SEL_FMAP_81_RSVD_1", - TRQ_SEL_FMAP_81_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_81_QID_MAX", - TRQ_SEL_FMAP_81_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_81_QID_BASE", - TRQ_SEL_FMAP_81_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_82_field_info[] = { - {"TRQ_SEL_FMAP_82_RSVD_1", - TRQ_SEL_FMAP_82_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_82_QID_MAX", - TRQ_SEL_FMAP_82_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_82_QID_BASE", - TRQ_SEL_FMAP_82_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_83_field_info[] = { - {"TRQ_SEL_FMAP_83_RSVD_1", - TRQ_SEL_FMAP_83_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_83_QID_MAX", - TRQ_SEL_FMAP_83_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_83_QID_BASE", - TRQ_SEL_FMAP_83_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_84_field_info[] = { - {"TRQ_SEL_FMAP_84_RSVD_1", - TRQ_SEL_FMAP_84_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_84_QID_MAX", - TRQ_SEL_FMAP_84_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_84_QID_BASE", - TRQ_SEL_FMAP_84_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_85_field_info[] = { - {"TRQ_SEL_FMAP_85_RSVD_1", - TRQ_SEL_FMAP_85_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_85_QID_MAX", - TRQ_SEL_FMAP_85_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_85_QID_BASE", - TRQ_SEL_FMAP_85_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_86_field_info[] = { - {"TRQ_SEL_FMAP_86_RSVD_1", - TRQ_SEL_FMAP_86_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_86_QID_MAX", - TRQ_SEL_FMAP_86_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_86_QID_BASE", - TRQ_SEL_FMAP_86_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_87_field_info[] = { - {"TRQ_SEL_FMAP_87_RSVD_1", - TRQ_SEL_FMAP_87_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_87_QID_MAX", - TRQ_SEL_FMAP_87_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_87_QID_BASE", - TRQ_SEL_FMAP_87_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_88_field_info[] = { - {"TRQ_SEL_FMAP_88_RSVD_1", - TRQ_SEL_FMAP_88_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_88_QID_MAX", - TRQ_SEL_FMAP_88_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_88_QID_BASE", - TRQ_SEL_FMAP_88_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_89_field_info[] = { - {"TRQ_SEL_FMAP_89_RSVD_1", - TRQ_SEL_FMAP_89_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_89_QID_MAX", - TRQ_SEL_FMAP_89_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_89_QID_BASE", - TRQ_SEL_FMAP_89_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_8a_field_info[] = { - {"TRQ_SEL_FMAP_8A_RSVD_1", - TRQ_SEL_FMAP_8A_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_8A_QID_MAX", - TRQ_SEL_FMAP_8A_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_8A_QID_BASE", - TRQ_SEL_FMAP_8A_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_8b_field_info[] = { - {"TRQ_SEL_FMAP_8B_RSVD_1", - TRQ_SEL_FMAP_8B_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_8B_QID_MAX", - TRQ_SEL_FMAP_8B_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_8B_QID_BASE", - TRQ_SEL_FMAP_8B_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_8c_field_info[] = { - {"TRQ_SEL_FMAP_8C_RSVD_1", - TRQ_SEL_FMAP_8C_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_8C_QID_MAX", - TRQ_SEL_FMAP_8C_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_8C_QID_BASE", - TRQ_SEL_FMAP_8C_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_8d_field_info[] = { - {"TRQ_SEL_FMAP_8D_RSVD_1", - TRQ_SEL_FMAP_8D_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_8D_QID_MAX", - TRQ_SEL_FMAP_8D_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_8D_QID_BASE", - TRQ_SEL_FMAP_8D_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_8e_field_info[] = { - {"TRQ_SEL_FMAP_8E_RSVD_1", - TRQ_SEL_FMAP_8E_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_8E_QID_MAX", - TRQ_SEL_FMAP_8E_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_8E_QID_BASE", - TRQ_SEL_FMAP_8E_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_8f_field_info[] = { - {"TRQ_SEL_FMAP_8F_RSVD_1", - TRQ_SEL_FMAP_8F_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_8F_QID_MAX", - TRQ_SEL_FMAP_8F_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_8F_QID_BASE", - TRQ_SEL_FMAP_8F_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_90_field_info[] = { - {"TRQ_SEL_FMAP_90_RSVD_1", - TRQ_SEL_FMAP_90_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_90_QID_MAX", - TRQ_SEL_FMAP_90_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_90_QID_BASE", - TRQ_SEL_FMAP_90_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_91_field_info[] = { - {"TRQ_SEL_FMAP_91_RSVD_1", - TRQ_SEL_FMAP_91_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_91_QID_MAX", - TRQ_SEL_FMAP_91_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_91_QID_BASE", - TRQ_SEL_FMAP_91_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_92_field_info[] = { - {"TRQ_SEL_FMAP_92_RSVD_1", - TRQ_SEL_FMAP_92_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_92_QID_MAX", - TRQ_SEL_FMAP_92_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_92_QID_BASE", - TRQ_SEL_FMAP_92_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_93_field_info[] = { - {"TRQ_SEL_FMAP_93_RSVD_1", - TRQ_SEL_FMAP_93_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_93_QID_MAX", - TRQ_SEL_FMAP_93_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_93_QID_BASE", - TRQ_SEL_FMAP_93_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_94_field_info[] = { - {"TRQ_SEL_FMAP_94_RSVD_1", - TRQ_SEL_FMAP_94_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_94_QID_MAX", - TRQ_SEL_FMAP_94_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_94_QID_BASE", - TRQ_SEL_FMAP_94_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_95_field_info[] = { - {"TRQ_SEL_FMAP_95_RSVD_1", - TRQ_SEL_FMAP_95_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_95_QID_MAX", - TRQ_SEL_FMAP_95_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_95_QID_BASE", - TRQ_SEL_FMAP_95_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_96_field_info[] = { - {"TRQ_SEL_FMAP_96_RSVD_1", - TRQ_SEL_FMAP_96_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_96_QID_MAX", - TRQ_SEL_FMAP_96_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_96_QID_BASE", - TRQ_SEL_FMAP_96_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_97_field_info[] = { - {"TRQ_SEL_FMAP_97_RSVD_1", - TRQ_SEL_FMAP_97_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_97_QID_MAX", - TRQ_SEL_FMAP_97_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_97_QID_BASE", - TRQ_SEL_FMAP_97_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_98_field_info[] = { - {"TRQ_SEL_FMAP_98_RSVD_1", - TRQ_SEL_FMAP_98_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_98_QID_MAX", - TRQ_SEL_FMAP_98_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_98_QID_BASE", - TRQ_SEL_FMAP_98_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_99_field_info[] = { - {"TRQ_SEL_FMAP_99_RSVD_1", - TRQ_SEL_FMAP_99_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_99_QID_MAX", - TRQ_SEL_FMAP_99_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_99_QID_BASE", - TRQ_SEL_FMAP_99_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_9a_field_info[] = { - {"TRQ_SEL_FMAP_9A_RSVD_1", - TRQ_SEL_FMAP_9A_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_9A_QID_MAX", - TRQ_SEL_FMAP_9A_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_9A_QID_BASE", - TRQ_SEL_FMAP_9A_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_9b_field_info[] = { - {"TRQ_SEL_FMAP_9B_RSVD_1", - TRQ_SEL_FMAP_9B_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_9B_QID_MAX", - TRQ_SEL_FMAP_9B_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_9B_QID_BASE", - TRQ_SEL_FMAP_9B_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_9c_field_info[] = { - {"TRQ_SEL_FMAP_9C_RSVD_1", - TRQ_SEL_FMAP_9C_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_9C_QID_MAX", - TRQ_SEL_FMAP_9C_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_9C_QID_BASE", - TRQ_SEL_FMAP_9C_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_9d_field_info[] = { - {"TRQ_SEL_FMAP_9D_RSVD_1", - TRQ_SEL_FMAP_9D_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_9D_QID_MAX", - TRQ_SEL_FMAP_9D_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_9D_QID_BASE", - TRQ_SEL_FMAP_9D_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_9e_field_info[] = { - {"TRQ_SEL_FMAP_9E_RSVD_1", - TRQ_SEL_FMAP_9E_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_9E_QID_MAX", - TRQ_SEL_FMAP_9E_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_9E_QID_BASE", - TRQ_SEL_FMAP_9E_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_9f_field_info[] = { - {"TRQ_SEL_FMAP_9F_RSVD_1", - TRQ_SEL_FMAP_9F_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_9F_QID_MAX", - TRQ_SEL_FMAP_9F_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_9F_QID_BASE", - TRQ_SEL_FMAP_9F_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_a0_field_info[] = { - {"TRQ_SEL_FMAP_A0_RSVD_1", - TRQ_SEL_FMAP_A0_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_A0_QID_MAX", - TRQ_SEL_FMAP_A0_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_A0_QID_BASE", - TRQ_SEL_FMAP_A0_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_a1_field_info[] = { - {"TRQ_SEL_FMAP_A1_RSVD_1", - TRQ_SEL_FMAP_A1_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_A1_QID_MAX", - TRQ_SEL_FMAP_A1_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_A1_QID_BASE", - TRQ_SEL_FMAP_A1_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_a2_field_info[] = { - {"TRQ_SEL_FMAP_A2_RSVD_1", - TRQ_SEL_FMAP_A2_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_A2_QID_MAX", - TRQ_SEL_FMAP_A2_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_A2_QID_BASE", - TRQ_SEL_FMAP_A2_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_a3_field_info[] = { - {"TRQ_SEL_FMAP_A3_RSVD_1", - TRQ_SEL_FMAP_A3_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_A3_QID_MAX", - TRQ_SEL_FMAP_A3_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_A3_QID_BASE", - TRQ_SEL_FMAP_A3_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_a4_field_info[] = { - {"TRQ_SEL_FMAP_A4_RSVD_1", - TRQ_SEL_FMAP_A4_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_A4_QID_MAX", - TRQ_SEL_FMAP_A4_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_A4_QID_BASE", - TRQ_SEL_FMAP_A4_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_a5_field_info[] = { - {"TRQ_SEL_FMAP_A5_RSVD_1", - TRQ_SEL_FMAP_A5_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_A5_QID_MAX", - TRQ_SEL_FMAP_A5_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_A5_QID_BASE", - TRQ_SEL_FMAP_A5_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_a6_field_info[] = { - {"TRQ_SEL_FMAP_A6_RSVD_1", - TRQ_SEL_FMAP_A6_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_A6_QID_MAX", - TRQ_SEL_FMAP_A6_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_A6_QID_BASE", - TRQ_SEL_FMAP_A6_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_a7_field_info[] = { - {"TRQ_SEL_FMAP_A7_RSVD_1", - TRQ_SEL_FMAP_A7_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_A7_QID_MAX", - TRQ_SEL_FMAP_A7_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_A7_QID_BASE", - TRQ_SEL_FMAP_A7_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_a8_field_info[] = { - {"TRQ_SEL_FMAP_A8_RSVD_1", - TRQ_SEL_FMAP_A8_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_A8_QID_MAX", - TRQ_SEL_FMAP_A8_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_A8_QID_BASE", - TRQ_SEL_FMAP_A8_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_a9_field_info[] = { - {"TRQ_SEL_FMAP_A9_RSVD_1", - TRQ_SEL_FMAP_A9_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_A9_QID_MAX", - TRQ_SEL_FMAP_A9_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_A9_QID_BASE", - TRQ_SEL_FMAP_A9_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_aa_field_info[] = { - {"TRQ_SEL_FMAP_AA_RSVD_1", - TRQ_SEL_FMAP_AA_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_AA_QID_MAX", - TRQ_SEL_FMAP_AA_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_AA_QID_BASE", - TRQ_SEL_FMAP_AA_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_ab_field_info[] = { - {"TRQ_SEL_FMAP_AB_RSVD_1", - TRQ_SEL_FMAP_AB_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_AB_QID_MAX", - TRQ_SEL_FMAP_AB_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_AB_QID_BASE", - TRQ_SEL_FMAP_AB_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_ac_field_info[] = { - {"TRQ_SEL_FMAP_AC_RSVD_1", - TRQ_SEL_FMAP_AC_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_AC_QID_MAX", - TRQ_SEL_FMAP_AC_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_AC_QID_BASE", - TRQ_SEL_FMAP_AC_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_ad_field_info[] = { - {"TRQ_SEL_FMAP_AD_RSVD_1", - TRQ_SEL_FMAP_AD_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_AD_QID_MAX", - TRQ_SEL_FMAP_AD_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_AD_QID_BASE", - TRQ_SEL_FMAP_AD_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_ae_field_info[] = { - {"TRQ_SEL_FMAP_AE_RSVD_1", - TRQ_SEL_FMAP_AE_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_AE_QID_MAX", - TRQ_SEL_FMAP_AE_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_AE_QID_BASE", - TRQ_SEL_FMAP_AE_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_af_field_info[] = { - {"TRQ_SEL_FMAP_AF_RSVD_1", - TRQ_SEL_FMAP_AF_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_AF_QID_MAX", - TRQ_SEL_FMAP_AF_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_AF_QID_BASE", - TRQ_SEL_FMAP_AF_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_b0_field_info[] = { - {"TRQ_SEL_FMAP_B0_RSVD_1", - TRQ_SEL_FMAP_B0_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_B0_QID_MAX", - TRQ_SEL_FMAP_B0_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_B0_QID_BASE", - TRQ_SEL_FMAP_B0_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_b1_field_info[] = { - {"TRQ_SEL_FMAP_B1_RSVD_1", - TRQ_SEL_FMAP_B1_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_B1_QID_MAX", - TRQ_SEL_FMAP_B1_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_B1_QID_BASE", - TRQ_SEL_FMAP_B1_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_b2_field_info[] = { - {"TRQ_SEL_FMAP_B2_RSVD_1", - TRQ_SEL_FMAP_B2_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_B2_QID_MAX", - TRQ_SEL_FMAP_B2_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_B2_QID_BASE", - TRQ_SEL_FMAP_B2_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_b3_field_info[] = { - {"TRQ_SEL_FMAP_B3_RSVD_1", - TRQ_SEL_FMAP_B3_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_B3_QID_MAX", - TRQ_SEL_FMAP_B3_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_B3_QID_BASE", - TRQ_SEL_FMAP_B3_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_b4_field_info[] = { - {"TRQ_SEL_FMAP_B4_RSVD_1", - TRQ_SEL_FMAP_B4_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_B4_QID_MAX", - TRQ_SEL_FMAP_B4_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_B4_QID_BASE", - TRQ_SEL_FMAP_B4_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_b5_field_info[] = { - {"TRQ_SEL_FMAP_B5_RSVD_1", - TRQ_SEL_FMAP_B5_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_B5_QID_MAX", - TRQ_SEL_FMAP_B5_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_B5_QID_BASE", - TRQ_SEL_FMAP_B5_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_b6_field_info[] = { - {"TRQ_SEL_FMAP_B6_RSVD_1", - TRQ_SEL_FMAP_B6_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_B6_QID_MAX", - TRQ_SEL_FMAP_B6_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_B6_QID_BASE", - TRQ_SEL_FMAP_B6_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_b7_field_info[] = { - {"TRQ_SEL_FMAP_B7_RSVD_1", - TRQ_SEL_FMAP_B7_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_B7_QID_MAX", - TRQ_SEL_FMAP_B7_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_B7_QID_BASE", - TRQ_SEL_FMAP_B7_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_b8_field_info[] = { - {"TRQ_SEL_FMAP_B8_RSVD_1", - TRQ_SEL_FMAP_B8_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_B8_QID_MAX", - TRQ_SEL_FMAP_B8_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_B8_QID_BASE", - TRQ_SEL_FMAP_B8_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_b9_field_info[] = { - {"TRQ_SEL_FMAP_B9_RSVD_1", - TRQ_SEL_FMAP_B9_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_B9_QID_MAX", - TRQ_SEL_FMAP_B9_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_B9_QID_BASE", - TRQ_SEL_FMAP_B9_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_ba_field_info[] = { - {"TRQ_SEL_FMAP_BA_RSVD_1", - TRQ_SEL_FMAP_BA_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_BA_QID_MAX", - TRQ_SEL_FMAP_BA_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_BA_QID_BASE", - TRQ_SEL_FMAP_BA_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_bb_field_info[] = { - {"TRQ_SEL_FMAP_BB_RSVD_1", - TRQ_SEL_FMAP_BB_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_BB_QID_MAX", - TRQ_SEL_FMAP_BB_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_BB_QID_BASE", - TRQ_SEL_FMAP_BB_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_bc_field_info[] = { - {"TRQ_SEL_FMAP_BC_RSVD_1", - TRQ_SEL_FMAP_BC_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_BC_QID_MAX", - TRQ_SEL_FMAP_BC_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_BC_QID_BASE", - TRQ_SEL_FMAP_BC_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_bd_field_info[] = { - {"TRQ_SEL_FMAP_BD_RSVD_1", - TRQ_SEL_FMAP_BD_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_BD_QID_MAX", - TRQ_SEL_FMAP_BD_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_BD_QID_BASE", - TRQ_SEL_FMAP_BD_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_be_field_info[] = { - {"TRQ_SEL_FMAP_BE_RSVD_1", - TRQ_SEL_FMAP_BE_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_BE_QID_MAX", - TRQ_SEL_FMAP_BE_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_BE_QID_BASE", - TRQ_SEL_FMAP_BE_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_bf_field_info[] = { - {"TRQ_SEL_FMAP_BF_RSVD_1", - TRQ_SEL_FMAP_BF_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_BF_QID_MAX", - TRQ_SEL_FMAP_BF_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_BF_QID_BASE", - TRQ_SEL_FMAP_BF_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_c0_field_info[] = { - {"TRQ_SEL_FMAP_C0_RSVD_1", - TRQ_SEL_FMAP_C0_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_C0_QID_MAX", - TRQ_SEL_FMAP_C0_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_C0_QID_BASE", - TRQ_SEL_FMAP_C0_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_c1_field_info[] = { - {"TRQ_SEL_FMAP_C1_RSVD_1", - TRQ_SEL_FMAP_C1_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_C1_QID_MAX", - TRQ_SEL_FMAP_C1_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_C1_QID_BASE", - TRQ_SEL_FMAP_C1_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_c2_field_info[] = { - {"TRQ_SEL_FMAP_C2_RSVD_1", - TRQ_SEL_FMAP_C2_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_C2_QID_MAX", - TRQ_SEL_FMAP_C2_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_C2_QID_BASE", - TRQ_SEL_FMAP_C2_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_c3_field_info[] = { - {"TRQ_SEL_FMAP_C3_RSVD_1", - TRQ_SEL_FMAP_C3_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_C3_QID_MAX", - TRQ_SEL_FMAP_C3_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_C3_QID_BASE", - TRQ_SEL_FMAP_C3_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_c4_field_info[] = { - {"TRQ_SEL_FMAP_C4_RSVD_1", - TRQ_SEL_FMAP_C4_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_C4_QID_MAX", - TRQ_SEL_FMAP_C4_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_C4_QID_BASE", - TRQ_SEL_FMAP_C4_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_c5_field_info[] = { - {"TRQ_SEL_FMAP_C5_RSVD_1", - TRQ_SEL_FMAP_C5_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_C5_QID_MAX", - TRQ_SEL_FMAP_C5_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_C5_QID_BASE", - TRQ_SEL_FMAP_C5_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_c6_field_info[] = { - {"TRQ_SEL_FMAP_C6_RSVD_1", - TRQ_SEL_FMAP_C6_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_C6_QID_MAX", - TRQ_SEL_FMAP_C6_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_C6_QID_BASE", - TRQ_SEL_FMAP_C6_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_c7_field_info[] = { - {"TRQ_SEL_FMAP_C7_RSVD_1", - TRQ_SEL_FMAP_C7_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_C7_QID_MAX", - TRQ_SEL_FMAP_C7_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_C7_QID_BASE", - TRQ_SEL_FMAP_C7_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_c8_field_info[] = { - {"TRQ_SEL_FMAP_C8_RSVD_1", - TRQ_SEL_FMAP_C8_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_C8_QID_MAX", - TRQ_SEL_FMAP_C8_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_C8_QID_BASE", - TRQ_SEL_FMAP_C8_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_c9_field_info[] = { - {"TRQ_SEL_FMAP_C9_RSVD_1", - TRQ_SEL_FMAP_C9_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_C9_QID_MAX", - TRQ_SEL_FMAP_C9_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_C9_QID_BASE", - TRQ_SEL_FMAP_C9_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_ca_field_info[] = { - {"TRQ_SEL_FMAP_CA_RSVD_1", - TRQ_SEL_FMAP_CA_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_CA_QID_MAX", - TRQ_SEL_FMAP_CA_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_CA_QID_BASE", - TRQ_SEL_FMAP_CA_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_cb_field_info[] = { - {"TRQ_SEL_FMAP_CB_RSVD_1", - TRQ_SEL_FMAP_CB_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_CB_QID_MAX", - TRQ_SEL_FMAP_CB_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_CB_QID_BASE", - TRQ_SEL_FMAP_CB_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_cc_field_info[] = { - {"TRQ_SEL_FMAP_CC_RSVD_1", - TRQ_SEL_FMAP_CC_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_CC_QID_MAX", - TRQ_SEL_FMAP_CC_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_CC_QID_BASE", - TRQ_SEL_FMAP_CC_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_cd_field_info[] = { - {"TRQ_SEL_FMAP_CD_RSVD_1", - TRQ_SEL_FMAP_CD_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_CD_QID_MAX", - TRQ_SEL_FMAP_CD_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_CD_QID_BASE", - TRQ_SEL_FMAP_CD_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_ce_field_info[] = { - {"TRQ_SEL_FMAP_CE_RSVD_1", - TRQ_SEL_FMAP_CE_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_CE_QID_MAX", - TRQ_SEL_FMAP_CE_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_CE_QID_BASE", - TRQ_SEL_FMAP_CE_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_cf_field_info[] = { - {"TRQ_SEL_FMAP_CF_RSVD_1", - TRQ_SEL_FMAP_CF_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_CF_QID_MAX", - TRQ_SEL_FMAP_CF_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_CF_QID_BASE", - TRQ_SEL_FMAP_CF_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_d0_field_info[] = { - {"TRQ_SEL_FMAP_D0_RSVD_1", - TRQ_SEL_FMAP_D0_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_D0_QID_MAX", - TRQ_SEL_FMAP_D0_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_D0_QID_BASE", - TRQ_SEL_FMAP_D0_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_d1_field_info[] = { - {"TRQ_SEL_FMAP_D1_RSVD_1", - TRQ_SEL_FMAP_D1_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_D1_QID_MAX", - TRQ_SEL_FMAP_D1_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_D1_QID_BASE", - TRQ_SEL_FMAP_D1_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_d2_field_info[] = { - {"TRQ_SEL_FMAP_D2_RSVD_1", - TRQ_SEL_FMAP_D2_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_D2_QID_MAX", - TRQ_SEL_FMAP_D2_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_D2_QID_BASE", - TRQ_SEL_FMAP_D2_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_d3_field_info[] = { - {"TRQ_SEL_FMAP_D3_RSVD_1", - TRQ_SEL_FMAP_D3_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_D3_QID_MAX", - TRQ_SEL_FMAP_D3_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_D3_QID_BASE", - TRQ_SEL_FMAP_D3_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_d4_field_info[] = { - {"TRQ_SEL_FMAP_D4_RSVD_1", - TRQ_SEL_FMAP_D4_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_D4_QID_MAX", - TRQ_SEL_FMAP_D4_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_D4_QID_BASE", - TRQ_SEL_FMAP_D4_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_d5_field_info[] = { - {"TRQ_SEL_FMAP_D5_RSVD_1", - TRQ_SEL_FMAP_D5_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_D5_QID_MAX", - TRQ_SEL_FMAP_D5_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_D5_QID_BASE", - TRQ_SEL_FMAP_D5_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_d6_field_info[] = { - {"TRQ_SEL_FMAP_D6_RSVD_1", - TRQ_SEL_FMAP_D6_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_D6_QID_MAX", - TRQ_SEL_FMAP_D6_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_D6_QID_BASE", - TRQ_SEL_FMAP_D6_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_d7_field_info[] = { - {"TRQ_SEL_FMAP_D7_RSVD_1", - TRQ_SEL_FMAP_D7_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_D7_QID_MAX", - TRQ_SEL_FMAP_D7_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_D7_QID_BASE", - TRQ_SEL_FMAP_D7_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_d8_field_info[] = { - {"TRQ_SEL_FMAP_D8_RSVD_1", - TRQ_SEL_FMAP_D8_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_D8_QID_MAX", - TRQ_SEL_FMAP_D8_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_D8_QID_BASE", - TRQ_SEL_FMAP_D8_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_d9_field_info[] = { - {"TRQ_SEL_FMAP_D9_RSVD_1", - TRQ_SEL_FMAP_D9_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_D9_QID_MAX", - TRQ_SEL_FMAP_D9_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_D9_QID_BASE", - TRQ_SEL_FMAP_D9_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_da_field_info[] = { - {"TRQ_SEL_FMAP_DA_RSVD_1", - TRQ_SEL_FMAP_DA_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_DA_QID_MAX", - TRQ_SEL_FMAP_DA_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_DA_QID_BASE", - TRQ_SEL_FMAP_DA_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_db_field_info[] = { - {"TRQ_SEL_FMAP_DB_RSVD_1", - TRQ_SEL_FMAP_DB_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_DB_QID_MAX", - TRQ_SEL_FMAP_DB_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_DB_QID_BASE", - TRQ_SEL_FMAP_DB_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_dc_field_info[] = { - {"TRQ_SEL_FMAP_DC_RSVD_1", - TRQ_SEL_FMAP_DC_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_DC_QID_MAX", - TRQ_SEL_FMAP_DC_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_DC_QID_BASE", - TRQ_SEL_FMAP_DC_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_dd_field_info[] = { - {"TRQ_SEL_FMAP_DD_RSVD_1", - TRQ_SEL_FMAP_DD_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_DD_QID_MAX", - TRQ_SEL_FMAP_DD_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_DD_QID_BASE", - TRQ_SEL_FMAP_DD_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_de_field_info[] = { - {"TRQ_SEL_FMAP_DE_RSVD_1", - TRQ_SEL_FMAP_DE_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_DE_QID_MAX", - TRQ_SEL_FMAP_DE_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_DE_QID_BASE", - TRQ_SEL_FMAP_DE_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_df_field_info[] = { - {"TRQ_SEL_FMAP_DF_RSVD_1", - TRQ_SEL_FMAP_DF_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_DF_QID_MAX", - TRQ_SEL_FMAP_DF_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_DF_QID_BASE", - TRQ_SEL_FMAP_DF_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_e0_field_info[] = { - {"TRQ_SEL_FMAP_E0_RSVD_1", - TRQ_SEL_FMAP_E0_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_E0_QID_MAX", - TRQ_SEL_FMAP_E0_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_E0_QID_BASE", - TRQ_SEL_FMAP_E0_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_e1_field_info[] = { - {"TRQ_SEL_FMAP_E1_RSVD_1", - TRQ_SEL_FMAP_E1_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_E1_QID_MAX", - TRQ_SEL_FMAP_E1_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_E1_QID_BASE", - TRQ_SEL_FMAP_E1_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_e2_field_info[] = { - {"TRQ_SEL_FMAP_E2_RSVD_1", - TRQ_SEL_FMAP_E2_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_E2_QID_MAX", - TRQ_SEL_FMAP_E2_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_E2_QID_BASE", - TRQ_SEL_FMAP_E2_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_e3_field_info[] = { - {"TRQ_SEL_FMAP_E3_RSVD_1", - TRQ_SEL_FMAP_E3_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_E3_QID_MAX", - TRQ_SEL_FMAP_E3_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_E3_QID_BASE", - TRQ_SEL_FMAP_E3_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_e4_field_info[] = { - {"TRQ_SEL_FMAP_E4_RSVD_1", - TRQ_SEL_FMAP_E4_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_E4_QID_MAX", - TRQ_SEL_FMAP_E4_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_E4_QID_BASE", - TRQ_SEL_FMAP_E4_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_e5_field_info[] = { - {"TRQ_SEL_FMAP_E5_RSVD_1", - TRQ_SEL_FMAP_E5_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_E5_QID_MAX", - TRQ_SEL_FMAP_E5_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_E5_QID_BASE", - TRQ_SEL_FMAP_E5_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_e6_field_info[] = { - {"TRQ_SEL_FMAP_E6_RSVD_1", - TRQ_SEL_FMAP_E6_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_E6_QID_MAX", - TRQ_SEL_FMAP_E6_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_E6_QID_BASE", - TRQ_SEL_FMAP_E6_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_e7_field_info[] = { - {"TRQ_SEL_FMAP_E7_RSVD_1", - TRQ_SEL_FMAP_E7_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_E7_QID_MAX", - TRQ_SEL_FMAP_E7_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_E7_QID_BASE", - TRQ_SEL_FMAP_E7_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_e8_field_info[] = { - {"TRQ_SEL_FMAP_E8_RSVD_1", - TRQ_SEL_FMAP_E8_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_E8_QID_MAX", - TRQ_SEL_FMAP_E8_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_E8_QID_BASE", - TRQ_SEL_FMAP_E8_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_e9_field_info[] = { - {"TRQ_SEL_FMAP_E9_RSVD_1", - TRQ_SEL_FMAP_E9_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_E9_QID_MAX", - TRQ_SEL_FMAP_E9_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_E9_QID_BASE", - TRQ_SEL_FMAP_E9_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_ea_field_info[] = { - {"TRQ_SEL_FMAP_EA_RSVD_1", - TRQ_SEL_FMAP_EA_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_EA_QID_MAX", - TRQ_SEL_FMAP_EA_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_EA_QID_BASE", - TRQ_SEL_FMAP_EA_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_eb_field_info[] = { - {"TRQ_SEL_FMAP_EB_RSVD_1", - TRQ_SEL_FMAP_EB_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_EB_QID_MAX", - TRQ_SEL_FMAP_EB_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_EB_QID_BASE", - TRQ_SEL_FMAP_EB_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_ec_field_info[] = { - {"TRQ_SEL_FMAP_EC_RSVD_1", - TRQ_SEL_FMAP_EC_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_EC_QID_MAX", - TRQ_SEL_FMAP_EC_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_EC_QID_BASE", - TRQ_SEL_FMAP_EC_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_ed_field_info[] = { - {"TRQ_SEL_FMAP_ED_RSVD_1", - TRQ_SEL_FMAP_ED_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_ED_QID_MAX", - TRQ_SEL_FMAP_ED_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_ED_QID_BASE", - TRQ_SEL_FMAP_ED_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_ee_field_info[] = { - {"TRQ_SEL_FMAP_EE_RSVD_1", - TRQ_SEL_FMAP_EE_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_EE_QID_MAX", - TRQ_SEL_FMAP_EE_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_EE_QID_BASE", - TRQ_SEL_FMAP_EE_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_ef_field_info[] = { - {"TRQ_SEL_FMAP_EF_RSVD_1", - TRQ_SEL_FMAP_EF_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_EF_QID_MAX", - TRQ_SEL_FMAP_EF_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_EF_QID_BASE", - TRQ_SEL_FMAP_EF_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_f0_field_info[] = { - {"TRQ_SEL_FMAP_F0_RSVD_1", - TRQ_SEL_FMAP_F0_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_F0_QID_MAX", - TRQ_SEL_FMAP_F0_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_F0_QID_BASE", - TRQ_SEL_FMAP_F0_QID_BASE_MASK}, -}; - - -static struct regfield_info - ind_ctxt_data_3_field_info[] = { - {"IND_CTXT_DATA_3_DATA", - IND_CTXT_DATA_3_DATA_MASK}, -}; - - -static struct regfield_info - ind_ctxt_data_2_field_info[] = { - {"IND_CTXT_DATA_2_DATA", - IND_CTXT_DATA_2_DATA_MASK}, -}; - - -static struct regfield_info - ind_ctxt_data_1_field_info[] = { - {"IND_CTXT_DATA_1_DATA", - IND_CTXT_DATA_1_DATA_MASK}, -}; - - -static struct regfield_info - ind_ctxt_data_0_field_info[] = { - {"IND_CTXT_DATA_0_DATA", - IND_CTXT_DATA_0_DATA_MASK}, -}; - - -static struct regfield_info - ind_ctxt3_field_info[] = { - {"IND_CTXT3", - IND_CTXT3_MASK}, -}; - - -static struct regfield_info - ind_ctxt2_field_info[] = { - {"IND_CTXT2", - IND_CTXT2_MASK}, -}; - - -static struct regfield_info - ind_ctxt1_field_info[] = { - {"IND_CTXT1", - IND_CTXT1_MASK}, -}; - - -static struct regfield_info - ind_ctxt0_field_info[] = { - {"IND_CTXT0", - IND_CTXT0_MASK}, -}; - - -static struct regfield_info - ind_ctxt_cmd_field_info[] = { - {"IND_CTXT_CMD_RSVD_1", - IND_CTXT_CMD_RSVD_1_MASK}, - {"IND_CTXT_CMD_QID", - IND_CTXT_CMD_QID_MASK}, - {"IND_CTXT_CMD_OP", - IND_CTXT_CMD_OP_MASK}, - {"IND_CTXT_CMD_SET", - IND_CTXT_CMD_SET_MASK}, - {"IND_CTXT_CMD_BUSY", - IND_CTXT_CMD_BUSY_MASK}, -}; - - -static struct regfield_info - c2h_timer_cnt_1_field_info[] = { - {"C2H_TIMER_CNT_1_RSVD_1", - C2H_TIMER_CNT_1_RSVD_1_MASK}, - {"C2H_TIMER_CNT_1", - C2H_TIMER_CNT_1_MASK}, -}; - - -static struct regfield_info - c2h_timer_cnt_2_field_info[] = { - {"C2H_TIMER_CNT_2_RSVD_1", - C2H_TIMER_CNT_2_RSVD_1_MASK}, - {"C2H_TIMER_CNT_2", - C2H_TIMER_CNT_2_MASK}, -}; - - -static struct regfield_info - c2h_timer_cnt_3_field_info[] = { - {"C2H_TIMER_CNT_3_RSVD_1", - C2H_TIMER_CNT_3_RSVD_1_MASK}, - {"C2H_TIMER_CNT_3", - C2H_TIMER_CNT_3_MASK}, -}; - - -static struct regfield_info - c2h_timer_cnt_4_field_info[] = { - {"C2H_TIMER_CNT_4_RSVD_1", - C2H_TIMER_CNT_4_RSVD_1_MASK}, - {"C2H_TIMER_CNT_4", - C2H_TIMER_CNT_4_MASK}, -}; - - -static struct regfield_info - c2h_timer_cnt_5_field_info[] = { - {"C2H_TIMER_CNT_5_RSVD_1", - C2H_TIMER_CNT_5_RSVD_1_MASK}, - {"C2H_TIMER_CNT_5", - C2H_TIMER_CNT_5_MASK}, -}; - - -static struct regfield_info - c2h_timer_cnt_6_field_info[] = { - {"C2H_TIMER_CNT_6_RSVD_1", - C2H_TIMER_CNT_6_RSVD_1_MASK}, - {"C2H_TIMER_CNT_6", - C2H_TIMER_CNT_6_MASK}, -}; - - -static struct regfield_info - c2h_timer_cnt_7_field_info[] = { - {"C2H_TIMER_CNT_7_RSVD_1", - C2H_TIMER_CNT_7_RSVD_1_MASK}, - {"C2H_TIMER_CNT_7", - C2H_TIMER_CNT_7_MASK}, -}; - - -static struct regfield_info - c2h_timer_cnt_8_field_info[] = { - {"C2H_TIMER_CNT_8_RSVD_1", - C2H_TIMER_CNT_8_RSVD_1_MASK}, - {"C2H_TIMER_CNT_8", - C2H_TIMER_CNT_8_MASK}, -}; - - -static struct regfield_info - c2h_timer_cnt_9_field_info[] = { - {"C2H_TIMER_CNT_9_RSVD_1", - C2H_TIMER_CNT_9_RSVD_1_MASK}, - {"C2H_TIMER_CNT_9", - C2H_TIMER_CNT_9_MASK}, -}; - - -static struct regfield_info - c2h_timer_cnt_a_field_info[] = { - {"C2H_TIMER_CNT_A_RSVD_1", - C2H_TIMER_CNT_A_RSVD_1_MASK}, - {"C2H_TIMER_CNT_A", - C2H_TIMER_CNT_A_MASK}, -}; - - -static struct regfield_info - c2h_timer_cnt_b_field_info[] = { - {"C2H_TIMER_CNT_B_RSVD_1", - C2H_TIMER_CNT_B_RSVD_1_MASK}, - {"C2H_TIMER_CNT_B", - C2H_TIMER_CNT_B_MASK}, -}; - - -static struct regfield_info - c2h_timer_cnt_c_field_info[] = { - {"C2H_TIMER_CNT_C_RSVD_1", - C2H_TIMER_CNT_C_RSVD_1_MASK}, - {"C2H_TIMER_CNT_C", - C2H_TIMER_CNT_C_MASK}, -}; - - -static struct regfield_info - c2h_timer_cnt_d_field_info[] = { - {"C2H_TIMER_CNT_D_RSVD_1", - C2H_TIMER_CNT_D_RSVD_1_MASK}, - {"C2H_TIMER_CNT_D", - C2H_TIMER_CNT_D_MASK}, -}; - - -static struct regfield_info - c2h_timer_cnt_e_field_info[] = { - {"C2H_TIMER_CNT_E_RSVD_1", - C2H_TIMER_CNT_E_RSVD_1_MASK}, - {"C2H_TIMER_CNT_E", - C2H_TIMER_CNT_E_MASK}, -}; - - -static struct regfield_info - c2h_timer_cnt_f_field_info[] = { - {"C2H_TIMER_CNT_F_RSVD_1", - C2H_TIMER_CNT_F_RSVD_1_MASK}, - {"C2H_TIMER_CNT_F", - C2H_TIMER_CNT_F_MASK}, -}; - - -static struct regfield_info - c2h_timer_cnt_10_field_info[] = { - {"C2H_TIMER_CNT_10_RSVD_1", - C2H_TIMER_CNT_10_RSVD_1_MASK}, - {"C2H_TIMER_CNT_10", - C2H_TIMER_CNT_10_MASK}, -}; - - -static struct regfield_info - c2h_cnt_th_1_field_info[] = { - {"C2H_CNT_TH_1_RSVD_1", - C2H_CNT_TH_1_RSVD_1_MASK}, - {"C2H_CNT_TH_1_THESHOLD_CNT", - C2H_CNT_TH_1_THESHOLD_CNT_MASK}, -}; - - -static struct regfield_info - c2h_cnt_th_2_field_info[] = { - {"C2H_CNT_TH_2_RSVD_1", - C2H_CNT_TH_2_RSVD_1_MASK}, - {"C2H_CNT_TH_2_THESHOLD_CNT", - C2H_CNT_TH_2_THESHOLD_CNT_MASK}, -}; - - -static struct regfield_info - c2h_cnt_th_3_field_info[] = { - {"C2H_CNT_TH_3_RSVD_1", - C2H_CNT_TH_3_RSVD_1_MASK}, - {"C2H_CNT_TH_3_THESHOLD_CNT", - C2H_CNT_TH_3_THESHOLD_CNT_MASK}, -}; - - -static struct regfield_info - c2h_cnt_th_4_field_info[] = { - {"C2H_CNT_TH_4_RSVD_1", - C2H_CNT_TH_4_RSVD_1_MASK}, - {"C2H_CNT_TH_4_THESHOLD_CNT", - C2H_CNT_TH_4_THESHOLD_CNT_MASK}, -}; - - -static struct regfield_info - c2h_cnt_th_5_field_info[] = { - {"C2H_CNT_TH_5_RSVD_1", - C2H_CNT_TH_5_RSVD_1_MASK}, - {"C2H_CNT_TH_5_THESHOLD_CNT", - C2H_CNT_TH_5_THESHOLD_CNT_MASK}, -}; - - -static struct regfield_info - c2h_cnt_th_6_field_info[] = { - {"C2H_CNT_TH_6_RSVD_1", - C2H_CNT_TH_6_RSVD_1_MASK}, - {"C2H_CNT_TH_6_THESHOLD_CNT", - C2H_CNT_TH_6_THESHOLD_CNT_MASK}, -}; - - -static struct regfield_info - c2h_cnt_th_7_field_info[] = { - {"C2H_CNT_TH_7_RSVD_1", - C2H_CNT_TH_7_RSVD_1_MASK}, - {"C2H_CNT_TH_7_THESHOLD_CNT", - C2H_CNT_TH_7_THESHOLD_CNT_MASK}, -}; - - -static struct regfield_info - c2h_cnt_th_8_field_info[] = { - {"C2H_CNT_TH_8_RSVD_1", - C2H_CNT_TH_8_RSVD_1_MASK}, - {"C2H_CNT_TH_8_THESHOLD_CNT", - C2H_CNT_TH_8_THESHOLD_CNT_MASK}, -}; - - -static struct regfield_info - c2h_cnt_th_9_field_info[] = { - {"C2H_CNT_TH_9_RSVD_1", - C2H_CNT_TH_9_RSVD_1_MASK}, - {"C2H_CNT_TH_9_THESHOLD_CNT", - C2H_CNT_TH_9_THESHOLD_CNT_MASK}, -}; - - -static struct regfield_info - c2h_cnt_th_a_field_info[] = { - {"C2H_CNT_TH_A_RSVD_1", - C2H_CNT_TH_A_RSVD_1_MASK}, - {"C2H_CNT_TH_A_THESHOLD_CNT", - C2H_CNT_TH_A_THESHOLD_CNT_MASK}, -}; - - -static struct regfield_info - c2h_cnt_th_b_field_info[] = { - {"C2H_CNT_TH_B_RSVD_1", - C2H_CNT_TH_B_RSVD_1_MASK}, - {"C2H_CNT_TH_B_THESHOLD_CNT", - C2H_CNT_TH_B_THESHOLD_CNT_MASK}, -}; - - -static struct regfield_info - c2h_cnt_th_c_field_info[] = { - {"C2H_CNT_TH_C_RSVD_1", - C2H_CNT_TH_C_RSVD_1_MASK}, - {"C2H_CNT_TH_C_THESHOLD_CNT", - C2H_CNT_TH_C_THESHOLD_CNT_MASK}, -}; - - -static struct regfield_info - c2h_cnt_th_d_field_info[] = { - {"C2H_CNT_TH_D_RSVD_1", - C2H_CNT_TH_D_RSVD_1_MASK}, - {"C2H_CNT_TH_D_THESHOLD_CNT", - C2H_CNT_TH_D_THESHOLD_CNT_MASK}, -}; - - -static struct regfield_info - c2h_cnt_th_e_field_info[] = { - {"C2H_CNT_TH_E_RSVD_1", - C2H_CNT_TH_E_RSVD_1_MASK}, - {"C2H_CNT_TH_E_THESHOLD_CNT", - C2H_CNT_TH_E_THESHOLD_CNT_MASK}, -}; - - -static struct regfield_info - c2h_cnt_th_f_field_info[] = { - {"C2H_CNT_TH_F_RSVD_1", - C2H_CNT_TH_F_RSVD_1_MASK}, - {"C2H_CNT_TH_F_THESHOLD_CNT", - C2H_CNT_TH_F_THESHOLD_CNT_MASK}, -}; - - -static struct regfield_info - c2h_cnt_th_10_field_info[] = { - {"C2H_CNT_TH_10_RSVD_1", - C2H_CNT_TH_10_RSVD_1_MASK}, - {"C2H_CNT_TH_10_THESHOLD_CNT", - C2H_CNT_TH_10_THESHOLD_CNT_MASK}, -}; - - -static struct regfield_info - c2h_qid2vec_map_qid_field_info[] = { - {"C2H_QID2VEC_MAP_QID_RSVD_1", - C2H_QID2VEC_MAP_QID_RSVD_1_MASK}, - {"C2H_QID2VEC_MAP_QID_QID", - C2H_QID2VEC_MAP_QID_QID_MASK}, -}; - - -static struct regfield_info - c2h_qid2vec_map_field_info[] = { - {"C2H_QID2VEC_MAP_RSVD_1", - C2H_QID2VEC_MAP_RSVD_1_MASK}, - {"C2H_QID2VEC_MAP_H2C_EN_COAL", - C2H_QID2VEC_MAP_H2C_EN_COAL_MASK}, - {"C2H_QID2VEC_MAP_H2C_VECTOR", - C2H_QID2VEC_MAP_H2C_VECTOR_MASK}, - {"C2H_QID2VEC_MAP_C2H_EN_COAL", - C2H_QID2VEC_MAP_C2H_EN_COAL_MASK}, - {"C2H_QID2VEC_MAP_C2H_VECTOR", - C2H_QID2VEC_MAP_C2H_VECTOR_MASK}, -}; - - -static struct regfield_info - c2h_stat_s_axis_c2h_accepted_field_info[] = { - {"C2H_STAT_S_AXIS_C2H_ACCEPTED", - C2H_STAT_S_AXIS_C2H_ACCEPTED_MASK}, -}; - - -static struct regfield_info - c2h_stat_s_axis_wrb_accepted_field_info[] = { - {"C2H_STAT_S_AXIS_WRB_ACCEPTED", - C2H_STAT_S_AXIS_WRB_ACCEPTED_MASK}, -}; - - -static struct regfield_info - c2h_stat_desc_rsp_pkt_accepted_field_info[] = { - {"C2H_STAT_DESC_RSP_PKT_ACCEPTED_D", - C2H_STAT_DESC_RSP_PKT_ACCEPTED_D_MASK}, -}; - - -static struct regfield_info - c2h_stat_axis_pkg_cmp_field_info[] = { - {"C2H_STAT_AXIS_PKG_CMP", - C2H_STAT_AXIS_PKG_CMP_MASK}, -}; - - -static struct regfield_info - c2h_stat_desc_rsp_accepted_field_info[] = { - {"C2H_STAT_DESC_RSP_ACCEPTED_D", - C2H_STAT_DESC_RSP_ACCEPTED_D_MASK}, -}; - - -static struct regfield_info - c2h_stat_desc_rsp_cmp_field_info[] = { - {"C2H_STAT_DESC_RSP_CMP_D", - C2H_STAT_DESC_RSP_CMP_D_MASK}, -}; - - -static struct regfield_info - c2h_stat_wrq_out_field_info[] = { - {"C2H_STAT_WRQ_OUT", - C2H_STAT_WRQ_OUT_MASK}, -}; - - -static struct regfield_info - c2h_stat_wpl_ren_accepted_field_info[] = { - {"C2H_STAT_WPL_REN_ACCEPTED", - C2H_STAT_WPL_REN_ACCEPTED_MASK}, -}; - - -static struct regfield_info - c2h_stat_total_wrq_len_field_info[] = { - {"C2H_STAT_TOTAL_WRQ_LEN", - C2H_STAT_TOTAL_WRQ_LEN_MASK}, -}; - - -static struct regfield_info - c2h_stat_total_wpl_len_field_info[] = { - {"C2H_STAT_TOTAL_WPL_LEN", - C2H_STAT_TOTAL_WPL_LEN_MASK}, -}; - - -static struct regfield_info - c2h_buf_sz_0_field_info[] = { - {"C2H_BUF_SZ_0_SIZE", - C2H_BUF_SZ_0_SIZE_MASK}, -}; - - -static struct regfield_info - c2h_buf_sz_1_field_info[] = { - {"C2H_BUF_SZ_1_SIZE", - C2H_BUF_SZ_1_SIZE_MASK}, -}; - - -static struct regfield_info - c2h_buf_sz_2_field_info[] = { - {"C2H_BUF_SZ_2_SIZE", - C2H_BUF_SZ_2_SIZE_MASK}, -}; - - -static struct regfield_info - c2h_buf_sz_3_field_info[] = { - {"C2H_BUF_SZ_3_SIZE", - C2H_BUF_SZ_3_SIZE_MASK}, -}; - - -static struct regfield_info - c2h_buf_sz_4_field_info[] = { - {"C2H_BUF_SZ_4_SIZE", - C2H_BUF_SZ_4_SIZE_MASK}, -}; - - -static struct regfield_info - c2h_buf_sz_5_field_info[] = { - {"C2H_BUF_SZ_5_SIZE", - C2H_BUF_SZ_5_SIZE_MASK}, -}; - - -static struct regfield_info - c2h_buf_sz_7_field_info[] = { - {"C2H_BUF_SZ_7_SIZE", - C2H_BUF_SZ_7_SIZE_MASK}, -}; - - -static struct regfield_info - c2h_buf_sz_8_field_info[] = { - {"C2H_BUF_SZ_8_SIZE", - C2H_BUF_SZ_8_SIZE_MASK}, -}; - - -static struct regfield_info - c2h_buf_sz_9_field_info[] = { - {"C2H_BUF_SZ_9_SIZE", - C2H_BUF_SZ_9_SIZE_MASK}, -}; - - -static struct regfield_info - c2h_buf_sz_10_field_info[] = { - {"C2H_BUF_SZ_10_SIZE", - C2H_BUF_SZ_10_SIZE_MASK}, -}; - - -static struct regfield_info - c2h_buf_sz_11_field_info[] = { - {"C2H_BUF_SZ_11_SIZE", - C2H_BUF_SZ_11_SIZE_MASK}, -}; - - -static struct regfield_info - c2h_buf_sz_12_field_info[] = { - {"C2H_BUF_SZ_12_SIZE", - C2H_BUF_SZ_12_SIZE_MASK}, -}; - - -static struct regfield_info - c2h_buf_sz_13_field_info[] = { - {"C2H_BUF_SZ_13_SIZE", - C2H_BUF_SZ_13_SIZE_MASK}, -}; - - -static struct regfield_info - c2h_buf_sz_14_field_info[] = { - {"C2H_BUF_SZ_14_SIZE", - C2H_BUF_SZ_14_SIZE_MASK}, -}; - - -static struct regfield_info - c2h_buf_sz_15_field_info[] = { - {"C2H_BUF_SZ_15_SIZE", - C2H_BUF_SZ_15_SIZE_MASK}, -}; - - -static struct regfield_info - c2h_err_stat_field_info[] = { - {"C2H_ERR_STAT_RSVD_1", - C2H_ERR_STAT_RSVD_1_MASK}, - {"C2H_ERR_STAT_WRB_PRTY_ERR", - C2H_ERR_STAT_WRB_PRTY_ERR_MASK}, - {"C2H_ERR_STAT_WRB_CIDX_ERR", - C2H_ERR_STAT_WRB_CIDX_ERR_MASK}, - {"C2H_ERR_STAT_WRB_QFULL_ERR", - C2H_ERR_STAT_WRB_QFULL_ERR_MASK}, - {"C2H_ERR_STAT_WRB_INV_Q_ERR", - C2H_ERR_STAT_WRB_INV_Q_ERR_MASK}, - {"C2H_ERR_STAT_PORT_ID_BYP_IN_MISMATCH", - C2H_ERR_STAT_PORT_ID_BYP_IN_MISMATCH_MASK}, - {"C2H_ERR_STAT_PORT_ID_CTXT_MISMATCH", - C2H_ERR_STAT_PORT_ID_CTXT_MISMATCH_MASK}, - {"C2H_ERR_STAT_ERR_DESC_CNT", - C2H_ERR_STAT_ERR_DESC_CNT_MASK}, - {"C2H_ERR_STAT_RSVD_2", - C2H_ERR_STAT_RSVD_2_MASK}, - {"C2H_ERR_STAT_MSI_INT_FAIL", - C2H_ERR_STAT_MSI_INT_FAIL_MASK}, - {"C2H_ERR_STAT_ENG_WPL_DATA_PAR_ERR", - C2H_ERR_STAT_ENG_WPL_DATA_PAR_ERR_MASK}, - {"C2H_ERR_STAT_RSVD_3", - C2H_ERR_STAT_RSVD_3_MASK}, - {"C2H_ERR_STAT_DESC_RSP_ERR", - C2H_ERR_STAT_DESC_RSP_ERR_MASK}, - {"C2H_ERR_STAT_QID_MISMATCH", - C2H_ERR_STAT_QID_MISMATCH_MASK}, - {"C2H_ERR_STAT_RSVD_4", - C2H_ERR_STAT_RSVD_4_MASK}, - {"C2H_ERR_STAT_LEN_MISMATCH", - C2H_ERR_STAT_LEN_MISMATCH_MASK}, - {"C2H_ERR_STAT_MTY_MISMATCH", - C2H_ERR_STAT_MTY_MISMATCH_MASK}, -}; - - -static struct regfield_info - c2h_err_mask_field_info[] = { - {"C2H_ERR_EN", - C2H_ERR_EN_MASK}, -}; - - -static struct regfield_info - c2h_fatal_err_stat_field_info[] = { - {"C2H_FATAL_ERR_STAT_RSVD_1", - C2H_FATAL_ERR_STAT_RSVD_1_MASK}, - {"C2H_FATAL_ERR_STAT_WPL_DATA_PAR_ERR", - C2H_FATAL_ERR_STAT_WPL_DATA_PAR_ERR_MASK}, - {"C2H_FATAL_ERR_STAT_PLD_FIFO_RAM_RDBE", - C2H_FATAL_ERR_STAT_PLD_FIFO_RAM_RDBE_MASK}, - {"C2H_FATAL_ERR_STAT_QID_FIFO_RAM_RDBE", - C2H_FATAL_ERR_STAT_QID_FIFO_RAM_RDBE_MASK}, - {"C2H_FATAL_ERR_STAT_TUSER_FIFO_RAM_RDBE", - C2H_FATAL_ERR_STAT_TUSER_FIFO_RAM_RDBE_MASK}, - {"C2H_FATAL_ERR_STAT_WRB_COAL_DATA_RAM_RDBE", - C2H_FATAL_ERR_STAT_WRB_COAL_DATA_RAM_RDBE_MASK}, - {"C2H_FATAL_ERR_STAT_INT_QID2VEC_RAM_RDBE", - C2H_FATAL_ERR_STAT_INT_QID2VEC_RAM_RDBE_MASK}, - {"C2H_FATAL_ERR_STAT_INT_CTXT_RAM_RDBE", - C2H_FATAL_ERR_STAT_INT_CTXT_RAM_RDBE_MASK}, - {"C2H_FATAL_ERR_STAT_DESC_REQ_FIFO_RAM_RDBE", - C2H_FATAL_ERR_STAT_DESC_REQ_FIFO_RAM_RDBE_MASK}, - {"C2H_FATAL_ERR_STAT_PFCH_CTXT_RAM_RDBE", - C2H_FATAL_ERR_STAT_PFCH_CTXT_RAM_RDBE_MASK}, - {"C2H_FATAL_ERR_STAT_WRB_CTXT_RAM_RDBE", - C2H_FATAL_ERR_STAT_WRB_CTXT_RAM_RDBE_MASK}, - {"C2H_FATAL_ERR_STAT_PFCH_LL_RAM_RDBE", - C2H_FATAL_ERR_STAT_PFCH_LL_RAM_RDBE_MASK}, - {"C2H_FATAL_ERR_STAT_TIMER_FIFO_RAM_RDBE", - C2H_FATAL_ERR_STAT_TIMER_FIFO_RAM_RDBE_MASK}, - {"C2H_FATAL_ERR_STAT_QID_MISMATCH", - C2H_FATAL_ERR_STAT_QID_MISMATCH_MASK}, - {"C2H_FATAL_ERR_STAT_RSVD_2", - C2H_FATAL_ERR_STAT_RSVD_2_MASK}, - {"C2H_FATAL_ERR_STAT_LEN_MISMATCH", - C2H_FATAL_ERR_STAT_LEN_MISMATCH_MASK}, - {"C2H_FATAL_ERR_STAT_MTY_MISMATCH", - C2H_FATAL_ERR_STAT_MTY_MISMATCH_MASK}, -}; - - -static struct regfield_info - c2h_fatal_err_mask_field_info[] = { - {"C2H_FATAL_ERR_C2HEN", - C2H_FATAL_ERR_C2HEN_MASK}, -}; - - -static struct regfield_info - c2h_fatal_err_enable_field_info[] = { - {"C2H_FATAL_ERR_ENABLE_RSVD_1", - C2H_FATAL_ERR_ENABLE_RSVD_1_MASK}, - {"C2H_FATAL_ERR_ENABLE_WPL_PAR_INV", - C2H_FATAL_ERR_ENABLE_WPL_PAR_INV_MASK}, - {"C2H_FATAL_ERR_ENABLE_WRQ_DIS", - C2H_FATAL_ERR_ENABLE_WRQ_DIS_MASK}, -}; - - -static struct regfield_info - glbl_err_int_field_info[] = { - {"GLBL_ERR_INT_RSVD_1", - GLBL_ERR_INT_RSVD_1_MASK}, - {"GLBL_ERR_INT_ARM", - GLBL_ERR_INT_ARM_MASK}, - {"GLBL_ERR_INT_EN_COAL", - GLBL_ERR_INT_EN_COAL_MASK}, - {"GLBL_ERR_INT_VEC", - GLBL_ERR_INT_VEC_MASK}, - {"GLBL_ERR_INT_FUNC", - GLBL_ERR_INT_FUNC_MASK}, -}; - - -static struct regfield_info - c2h_pfch_cfg_field_info[] = { - {"C2H_PFCH_CFG_EVT_QCNT_TH", - C2H_PFCH_CFG_EVT_QCNT_TH_MASK}, - {"C2H_PFCH_CFG_QCNT", - C2H_PFCH_CFG_QCNT_MASK}, - {"C2H_PFCH_CFG_NUM", - C2H_PFCH_CFG_NUM_MASK}, - {"C2H_PFCH_CFG_FL_TH", - C2H_PFCH_CFG_FL_TH_MASK}, -}; - - -static struct regfield_info - c2h_int_timer_tick_field_info[] = { - {"C2H_INT_TIMER_TICK", - C2H_INT_TIMER_TICK_MASK}, -}; - - -static struct regfield_info - c2h_stat_desc_rsp_drop_accepted_field_info[] = { - {"C2H_STAT_DESC_RSP_DROP_ACCEPTED_D", - C2H_STAT_DESC_RSP_DROP_ACCEPTED_D_MASK}, -}; - - -static struct regfield_info - c2h_stat_desc_rsp_err_accepted_field_info[] = { - {"C2H_STAT_DESC_RSP_ERR_ACCEPTED_D", - C2H_STAT_DESC_RSP_ERR_ACCEPTED_D_MASK}, -}; - - -static struct regfield_info - c2h_stat_desc_req_field_info[] = { - {"C2H_STAT_DESC_REQ", - C2H_STAT_DESC_REQ_MASK}, -}; - - -static struct regfield_info - c2h_stat_dbg_dma_eng_0_field_info[] = { - {"C2H_STAT_DMA_ENG_0_RSVD_1", - C2H_STAT_DMA_ENG_0_RSVD_1_MASK}, - {"C2H_STAT_DMA_ENG_0_WRB_FIFO_OUT_CNT", - C2H_STAT_DMA_ENG_0_WRB_FIFO_OUT_CNT_MASK}, - {"C2H_STAT_DMA_ENG_0_QID_FIFO_OUT_CNT", - C2H_STAT_DMA_ENG_0_QID_FIFO_OUT_CNT_MASK}, - {"C2H_STAT_DMA_ENG_0_PLD_FIFO_OUT_CNT", - C2H_STAT_DMA_ENG_0_PLD_FIFO_OUT_CNT_MASK}, - {"C2H_STAT_DMA_ENG_0_WRQ_FIFO_OUT_CNT", - C2H_STAT_DMA_ENG_0_WRQ_FIFO_OUT_CNT_MASK}, - {"C2H_STAT_DMA_ENG_0_WRB_SM_CS", - C2H_STAT_DMA_ENG_0_WRB_SM_CS_MASK}, - {"C2H_STAT_DMA_ENG_0_MAIN_SM_CS", - C2H_STAT_DMA_ENG_0_MAIN_SM_CS_MASK}, -}; - - -static struct regfield_info - c2h_stat_dbg_dma_eng_1_field_info[] = { - {"C2H_STAT_DMA_ENG_1_RSVD_1", - C2H_STAT_DMA_ENG_1_RSVD_1_MASK}, - {"C2H_STAT_DMA_ENG_1_DESC_RSP_LAST", - C2H_STAT_DMA_ENG_1_DESC_RSP_LAST_MASK}, - {"C2H_STAT_DMA_ENG_1_PLD_FIFO_IN_CNT", - C2H_STAT_DMA_ENG_1_PLD_FIFO_IN_CNT_MASK}, - {"C2H_STAT_DMA_ENG_1_PLD_FIFO_OUTPUT_CNT", - C2H_STAT_DMA_ENG_1_PLD_FIFO_OUTPUT_CNT_MASK}, - {"C2H_STAT_DMA_ENG_1_QID_FIFO_IN_CNT", - C2H_STAT_DMA_ENG_1_QID_FIFO_IN_CNT_MASK}, -}; - - -static struct regfield_info - c2h_stat_dbg_dma_eng_2_field_info[] = { - {"C2H_STAT_DMA_ENG_2_RSVD_1", - C2H_STAT_DMA_ENG_2_RSVD_1_MASK}, - {"C2H_STAT_DMA_ENG_2_WRB_FIFO_IN_CNT", - C2H_STAT_DMA_ENG_2_WRB_FIFO_IN_CNT_MASK}, - {"C2H_STAT_DMA_ENG_2_WRB_FIFO_OUTPUT_CNT", - C2H_STAT_DMA_ENG_2_WRB_FIFO_OUTPUT_CNT_MASK}, - {"C2H_STAT_DMA_ENG_2_QID_FIFO_OUTPUT_CNT", - C2H_STAT_DMA_ENG_2_QID_FIFO_OUTPUT_CNT_MASK}, -}; - - -static struct regfield_info - c2h_stat_dbg_dma_eng_3_field_info[] = { - {"C2H_STAT_DMA_ENG_3_RSVD_1", - C2H_STAT_DMA_ENG_3_RSVD_1_MASK}, - {"C2H_STAT_DMA_ENG_3_ADDR_4K_SPLIT_CNT", - C2H_STAT_DMA_ENG_3_ADDR_4K_SPLIT_CNT_MASK}, - {"C2H_STAT_DMA_ENG_3_WRQ_FIFO_IN_CNT", - C2H_STAT_DMA_ENG_3_WRQ_FIFO_IN_CNT_MASK}, - {"C2H_STAT_DMA_ENG_3_WRQ_FIFO_OUTPUT_CNT", - C2H_STAT_DMA_ENG_3_WRQ_FIFO_OUTPUT_CNT_MASK}, -}; - - -static struct regfield_info - c2h_dbg_pfch_err_ctxt_field_info[] = { - {"C2H_PFCH_ERR_CTXT_RSVD_1", - C2H_PFCH_ERR_CTXT_RSVD_1_MASK}, - {"C2H_PFCH_ERR_CTXT_ERR_STAT", - C2H_PFCH_ERR_CTXT_ERR_STAT_MASK}, - {"C2H_PFCH_ERR_CTXT_CMD_WR", - C2H_PFCH_ERR_CTXT_CMD_WR_MASK}, - {"C2H_PFCH_ERR_CTXT_QID", - C2H_PFCH_ERR_CTXT_QID_MASK}, - {"C2H_PFCH_ERR_CTXT_DONE", - C2H_PFCH_ERR_CTXT_DONE_MASK}, -}; - - -static struct regfield_info - c2h_first_err_qid_field_info[] = { - {"C2H_FIRST_ERR_QID_RSVD_1", - C2H_FIRST_ERR_QID_RSVD_1_MASK}, - {"C2H_FIRST_ERR_QID_ERR_STAT", - C2H_FIRST_ERR_QID_ERR_STAT_MASK}, - {"C2H_FIRST_ERR_QID_CMD_WR", - C2H_FIRST_ERR_QID_CMD_WR_MASK}, - {"C2H_FIRST_ERR_QID_QID", - C2H_FIRST_ERR_QID_QID_MASK}, -}; - - -static struct regfield_info - stat_num_wrb_in_field_info[] = { - {"STAT_NUM_WRB_IN_RSVD_1", - STAT_NUM_WRB_IN_RSVD_1_MASK}, - {"STAT_NUM_WRB_IN_WRB_CNT", - STAT_NUM_WRB_IN_WRB_CNT_MASK}, -}; - - -static struct regfield_info - stat_num_wrb_out_field_info[] = { - {"STAT_NUM_WRB_OUT_RSVD_1", - STAT_NUM_WRB_OUT_RSVD_1_MASK}, - {"STAT_NUM_WRB_OUT_WRB_CNT", - STAT_NUM_WRB_OUT_WRB_CNT_MASK}, -}; - - -static struct regfield_info - stat_num_wrb_drp_field_info[] = { - {"STAT_NUM_WRB_DRP_RSVD_1", - STAT_NUM_WRB_DRP_RSVD_1_MASK}, - {"STAT_NUM_WRB_DRP_WRB_CNT", - STAT_NUM_WRB_DRP_WRB_CNT_MASK}, -}; - - -static struct regfield_info - stat_num_stat_desc_out_field_info[] = { - {"STAT_NUM_STAT_DESC_OUT_RSVD_1", - STAT_NUM_STAT_DESC_OUT_RSVD_1_MASK}, - {"STAT_NUM_STAT_DESC_OUT_CNT", - STAT_NUM_STAT_DESC_OUT_CNT_MASK}, -}; - - -static struct regfield_info - stat_num_dsc_crdt_sent_field_info[] = { - {"STAT_NUM_DSC_CRDT_SENT_RSVD_1", - STAT_NUM_DSC_CRDT_SENT_RSVD_1_MASK}, - {"STAT_NUM_DSC_CRDT_SENT_CNT", - STAT_NUM_DSC_CRDT_SENT_CNT_MASK}, -}; - - -static struct regfield_info - stat_num_fch_dsc_rcvd_field_info[] = { - {"STAT_NUM_FCH_DSC_RCVD_RSVD_1", - STAT_NUM_FCH_DSC_RCVD_RSVD_1_MASK}, - {"STAT_NUM_FCH_DSC_RCVD_DSC_CNT", - STAT_NUM_FCH_DSC_RCVD_DSC_CNT_MASK}, -}; - - -static struct regfield_info - stat_num_byp_dsc_rcvd_field_info[] = { - {"STAT_NUM_BYP_DSC_RCVD_RSVD_1", - STAT_NUM_BYP_DSC_RCVD_RSVD_1_MASK}, - {"STAT_NUM_BYP_DSC_RCVD_DSC_CNT", - STAT_NUM_BYP_DSC_RCVD_DSC_CNT_MASK}, -}; - - -static struct regfield_info - c2h_wrb_coal_cfg_field_info[] = { - {"C2H_WRB_COAL_CFG_MAX_BUF_SZ", - C2H_WRB_COAL_CFG_MAX_BUF_SZ_MASK}, - {"C2H_WRB_COAL_CFG_TICK_VAL", - C2H_WRB_COAL_CFG_TICK_VAL_MASK}, - {"C2H_WRB_COAL_CFG_TICK_CNT", - C2H_WRB_COAL_CFG_TICK_CNT_MASK}, - {"C2H_WRB_COAL_CFG_SET_GLB_FLUSH", - C2H_WRB_COAL_CFG_SET_GLB_FLUSH_MASK}, - {"C2H_WRB_COAL_CFG_DONE_GLB_FLUSH", - C2H_WRB_COAL_CFG_DONE_GLB_FLUSH_MASK}, -}; - - -static struct regfield_info - c2h_intr_h2c_req_field_info[] = { - {"C2H_INTR_H2C_REQ_RSVD_1", - C2H_INTR_H2C_REQ_RSVD_1_MASK}, - {"C2H_INTR_H2C_REQ_CNT", - C2H_INTR_H2C_REQ_CNT_MASK}, -}; - - -static struct regfield_info - c2h_intr_c2h_mm_req_field_info[] = { - {"C2H_INTR_C2H_MM_REQ_RSVD_1", - C2H_INTR_C2H_MM_REQ_RSVD_1_MASK}, - {"C2H_INTR_C2H_MM_REQ_CNT", - C2H_INTR_C2H_MM_REQ_CNT_MASK}, -}; - - -static struct regfield_info - c2h_intr_err_int_req_field_info[] = { - {"C2H_INTR_ERR_INT_REQ_RSVD_1", - C2H_INTR_ERR_INT_REQ_RSVD_1_MASK}, - {"C2H_INTR_ERR_INT_REQ_CNT", - C2H_INTR_ERR_INT_REQ_CNT_MASK}, -}; - - -static struct regfield_info - c2h_intr_c2h_st_req_field_info[] = { - {"C2H_INTR_C2H_ST_REQ_RSVD_1", - C2H_INTR_C2H_ST_REQ_RSVD_1_MASK}, - {"C2H_INTR_C2H_ST_REQ_CNT", - C2H_INTR_C2H_ST_REQ_CNT_MASK}, -}; - - -static struct regfield_info - c2h_intr_h2c_err_c2h_mm_msix_ack_field_info[] = { - {"C2H_INTR_H2C_ERR_C2H_MM_MSIX_ACK_RSVD_1", - C2H_INTR_H2C_ERR_C2H_MM_MSIX_ACK_RSVD_1_MASK}, - {"C2H_INTR_H2C_ERR_C2H_MM_MSIX_ACK_CNT", - C2H_INTR_H2C_ERR_C2H_MM_MSIX_ACK_CNT_MASK}, -}; - - -static struct regfield_info - c2h_intr_h2c_err_c2h_mm_msix_fail_field_info[] = { - {"C2H_INTR_H2C_ERR_C2H_MM_MSIX_FAIL_RSVD_1", - C2H_INTR_H2C_ERR_C2H_MM_MSIX_FAIL_RSVD_1_MASK}, - {"C2H_INTR_H2C_ERR_C2H_MM_MSIX_FAIL_CNT", - C2H_INTR_H2C_ERR_C2H_MM_MSIX_FAIL_CNT_MASK}, -}; - - -static struct regfield_info - c2h_intr_h2c_err_c2h_mm_msix_no_msix_field_info[] = { - {"C2H_INTR_H2C_ERR_C2H_MM_MSIX_NO_MSIX_RSVD_1", - C2H_INTR_H2C_ERR_C2H_MM_MSIX_NO_MSIX_RSVD_1_MASK}, - {"C2H_INTR_H2C_ERR_C2H_MM_MSIX_NO_MSIX_CNT", - C2H_INTR_H2C_ERR_C2H_MM_MSIX_NO_MSIX_CNT_MASK}, -}; - - -static struct regfield_info - c2h_intr_h2c_err_c2h_mm_ctxt_inval_field_info[] = { - {"C2H_INTR_H2C_ERR_C2H_MM_CTXT_INVAL_RSVD_1", - C2H_INTR_H2C_ERR_C2H_MM_CTXT_INVAL_RSVD_1_MASK}, - {"C2H_INTR_H2C_ERR_C2H_MM_CTXT_INVAL_CNT", - C2H_INTR_H2C_ERR_C2H_MM_CTXT_INVAL_CNT_MASK}, -}; - - -static struct regfield_info - c2h_intr_c2h_st_msix_ack_field_info[] = { - {"C2H_INTR_C2H_ST_MSIX_ACK_RSVD_1", - C2H_INTR_C2H_ST_MSIX_ACK_RSVD_1_MASK}, - {"C2H_INTR_C2H_ST_MSIX_ACK_CNT", - C2H_INTR_C2H_ST_MSIX_ACK_CNT_MASK}, -}; - - -static struct regfield_info - c2h_intr_c2h_st_msix_fail_field_info[] = { - {"C2H_INTR_C2H_ST_MSIX_FAIL_RSVD_1", - C2H_INTR_C2H_ST_MSIX_FAIL_RSVD_1_MASK}, - {"C2H_INTR_C2H_ST_MSIX_FAIL_CNT", - C2H_INTR_C2H_ST_MSIX_FAIL_CNT_MASK}, -}; - - -static struct regfield_info - c2h_intr_c2h_st_no_msix_field_info[] = { - {"C2H_INTR_C2H_ST_NO_MSIX_RSVD_1", - C2H_INTR_C2H_ST_NO_MSIX_RSVD_1_MASK}, - {"C2H_INTR_C2H_ST_NO_MSIX_CNT", - C2H_INTR_C2H_ST_NO_MSIX_CNT_MASK}, -}; - - -static struct regfield_info - c2h_intr_c2h_st_ctxt_inval_field_info[] = { - {"C2H_INTR_C2H_ST_CTXT_INVAL_RSVD_1", - C2H_INTR_C2H_ST_CTXT_INVAL_RSVD_1_MASK}, - {"C2H_INTR_C2H_ST_CTXT_INVAL_CNT", - C2H_INTR_C2H_ST_CTXT_INVAL_CNT_MASK}, -}; - - -static struct regfield_info - c2h_stat_wr_cmp_field_info[] = { - {"C2H_STAT_WR_CMP_RSVD_1", - C2H_STAT_WR_CMP_RSVD_1_MASK}, - {"C2H_STAT_WR_CMP_CNT", - C2H_STAT_WR_CMP_CNT_MASK}, -}; - - -static struct regfield_info - c2h_stat_dbg_dma_eng_4_field_info[] = { - {"C2H_STAT_DMA_ENG_4_TUSER_FIFO_OUT_VLD", - C2H_STAT_DMA_ENG_4_TUSER_FIFO_OUT_VLD_MASK}, - {"C2H_STAT_DMA_ENG_4_WRB_FIFO_IN_RDY", - C2H_STAT_DMA_ENG_4_WRB_FIFO_IN_RDY_MASK}, - {"C2H_STAT_DMA_ENG_4_TUSER_FIFO_IN_CNT", - C2H_STAT_DMA_ENG_4_TUSER_FIFO_IN_CNT_MASK}, - {"C2H_STAT_DMA_ENG_4_TUSER_FIFO_OUTPUT_CNT", - C2H_STAT_DMA_ENG_4_TUSER_FIFO_OUTPUT_CNT_MASK}, - {"C2H_STAT_DMA_ENG_4_TUSER_FIFO_OUT_CNT", - C2H_STAT_DMA_ENG_4_TUSER_FIFO_OUT_CNT_MASK}, -}; - - -static struct regfield_info - c2h_stat_dbg_dma_eng_5_field_info[] = { - {"C2H_STAT_DMA_ENG_5_RSVD_1", - C2H_STAT_DMA_ENG_5_RSVD_1_MASK}, - {"C2H_STAT_DMA_ENG_5_TUSER_COMB_OUT_VLD", - C2H_STAT_DMA_ENG_5_TUSER_COMB_OUT_VLD_MASK}, - {"C2H_STAT_DMA_ENG_5_TUSER_FIFO_IN_RDY", - C2H_STAT_DMA_ENG_5_TUSER_FIFO_IN_RDY_MASK}, - {"C2H_STAT_DMA_ENG_5_TUSER_COMB_IN_CNT", - C2H_STAT_DMA_ENG_5_TUSER_COMB_IN_CNT_MASK}, - {"C2H_STAT_DMA_ENG_5_TUSE_COMB_OUTPUT_CNT", - C2H_STAT_DMA_ENG_5_TUSE_COMB_OUTPUT_CNT_MASK}, - {"C2H_STAT_DMA_ENG_5_TUSER_COMB_CNT", - C2H_STAT_DMA_ENG_5_TUSER_COMB_CNT_MASK}, -}; - - -static struct regfield_info - c2h_dbg_pfch_qid_field_info[] = { - {"C2H_PFCH_QID_RSVD_1", - C2H_PFCH_QID_RSVD_1_MASK}, - {"C2H_PFCH_QID_ERR_CTXT", - C2H_PFCH_QID_ERR_CTXT_MASK}, - {"C2H_PFCH_QID_TARGET", - C2H_PFCH_QID_TARGET_MASK}, - {"C2H_PFCH_QID_QID_OR_TAG", - C2H_PFCH_QID_QID_OR_TAG_MASK}, -}; - - -static struct regfield_info - c2h_dbg_pfch_field_info[] = { - {"C2H_PFCH_DATA", - C2H_PFCH_DATA_MASK}, -}; - - -static struct regfield_info - c2h_int_dbg_field_info[] = { - {"C2H_INT_RSVD_1", - C2H_INT_RSVD_1_MASK}, - {"C2H_INT_INT_COAL_SM", - C2H_INT_INT_COAL_SM_MASK}, - {"C2H_INT_INT_SM", - C2H_INT_INT_SM_MASK}, -}; - - -static struct regfield_info - c2h_stat_imm_accepted_field_info[] = { - {"C2H_STAT_IMM_ACCEPTED_RSVD_1", - C2H_STAT_IMM_ACCEPTED_RSVD_1_MASK}, - {"C2H_STAT_IMM_ACCEPTED_CNT", - C2H_STAT_IMM_ACCEPTED_CNT_MASK}, -}; - - -static struct regfield_info - c2h_stat_marker_accepted_field_info[] = { - {"C2H_STAT_MARKER_ACCEPTED_RSVD_1", - C2H_STAT_MARKER_ACCEPTED_RSVD_1_MASK}, - {"C2H_STAT_MARKER_ACCEPTED_CNT", - C2H_STAT_MARKER_ACCEPTED_CNT_MASK}, -}; - - -static struct regfield_info - c2h_stat_disable_cmp_accepted_field_info[] = { - {"C2H_STAT_DISABLE_CMP_ACCEPTED_RSVD_1", - C2H_STAT_DISABLE_CMP_ACCEPTED_RSVD_1_MASK}, - {"C2H_STAT_DISABLE_CMP_ACCEPTED_CNT", - C2H_STAT_DISABLE_CMP_ACCEPTED_CNT_MASK}, -}; - - -static struct regfield_info - c2h_pld_fifo_crdt_cnt_field_info[] = { - {"C2H_PLD_FIFO_CRDT_CNT_RSVD_1", - C2H_PLD_FIFO_CRDT_CNT_RSVD_1_MASK}, - {"C2H_PLD_FIFO_CRDT_CNT_CNT", - C2H_PLD_FIFO_CRDT_CNT_CNT_MASK}, -}; - - -static struct regfield_info - h2c_err_stat_field_info[] = { - {"H2C_ERR_STAT_RSVD_1", - H2C_ERR_STAT_RSVD_1_MASK}, - {"H2C_ERR_STAT_SBE", - H2C_ERR_STAT_SBE_MASK}, - {"H2C_ERR_STAT_DBE", - H2C_ERR_STAT_DBE_MASK}, - {"H2C_ERR_STAT_NO_DMA_DS", - H2C_ERR_STAT_NO_DMA_DS_MASK}, - {"H2C_ERR_STAT_SDI_MRKR_REQ_MOP_ERR", - H2C_ERR_STAT_SDI_MRKR_REQ_MOP_ERR_MASK}, - {"H2C_ERR_STAT_ZERO_LEN_DS", - H2C_ERR_STAT_ZERO_LEN_DS_MASK}, -}; - - -static struct regfield_info - h2c_err_mask_field_info[] = { - {"H2C_ERR_EN", - H2C_ERR_EN_MASK}, -}; - - -static struct regfield_info - h2c_first_err_qid_field_info[] = { - {"H2C_FIRST_ERR_QID_RSVD_1", - H2C_FIRST_ERR_QID_RSVD_1_MASK}, - {"H2C_FIRST_ERR_QID_ERR_TYPE", - H2C_FIRST_ERR_QID_ERR_TYPE_MASK}, - {"H2C_FIRST_ERR_QID_RSVD_2", - H2C_FIRST_ERR_QID_RSVD_2_MASK}, - {"H2C_FIRST_ERR_QID_QID", - H2C_FIRST_ERR_QID_QID_MASK}, -}; - - -static struct regfield_info - h2c_dbg_reg0_field_info[] = { - {"H2C_REG0_NUM_DSC_RCVD", - H2C_REG0_NUM_DSC_RCVD_MASK}, - {"H2C_REG0_NUM_WRB_SENT", - H2C_REG0_NUM_WRB_SENT_MASK}, -}; - - -static struct regfield_info - h2c_dbg_reg1_field_info[] = { - {"H2C_REG1_NUM_REQ_SENT", - H2C_REG1_NUM_REQ_SENT_MASK}, - {"H2C_REG1_NUM_CMP_SENT", - H2C_REG1_NUM_CMP_SENT_MASK}, -}; - - -static struct regfield_info - h2c_dbg_reg2_field_info[] = { - {"H2C_REG2_RSVD_1", - H2C_REG2_RSVD_1_MASK}, - {"H2C_REG2_NUM_ERR_DSC_RCVD", - H2C_REG2_NUM_ERR_DSC_RCVD_MASK}, -}; - - -static struct regfield_info - h2c_dbg_reg3_field_info[] = { - {"H2C_REG3", - H2C_REG3_MASK}, - {"H2C_REG3_DSCO_FIFO_EMPTY", - H2C_REG3_DSCO_FIFO_EMPTY_MASK}, - {"H2C_REG3_DSCO_FIFO_FULL", - H2C_REG3_DSCO_FIFO_FULL_MASK}, - {"H2C_REG3_CUR_RC_STATE", - H2C_REG3_CUR_RC_STATE_MASK}, - {"H2C_REG3_RDREQ_LINES", - H2C_REG3_RDREQ_LINES_MASK}, - {"H2C_REG3_RDATA_LINES_AVAIL", - H2C_REG3_RDATA_LINES_AVAIL_MASK}, - {"H2C_REG3_PEND_FIFO_EMPTY", - H2C_REG3_PEND_FIFO_EMPTY_MASK}, - {"H2C_REG3_PEND_FIFO_FULL", - H2C_REG3_PEND_FIFO_FULL_MASK}, - {"H2C_REG3_CUR_RQ_STATE", - H2C_REG3_CUR_RQ_STATE_MASK}, - {"H2C_REG3_DSCI_FIFO_FULL", - H2C_REG3_DSCI_FIFO_FULL_MASK}, - {"H2C_REG3_DSCI_FIFO_EMPTY", - H2C_REG3_DSCI_FIFO_EMPTY_MASK}, -}; - - -static struct regfield_info - h2c_dbg_reg4_field_info[] = { - {"H2C_REG4_RDREQ_ADDR", - H2C_REG4_RDREQ_ADDR_MASK}, -}; - - -static struct regfield_info - h2c_fatal_err_en_field_info[] = { - {"H2C_FATAL_ERR_EN_RSVD_1", - H2C_FATAL_ERR_EN_RSVD_1_MASK}, - {"H2C_FATAL_ERR_EN_H2C", - H2C_FATAL_ERR_EN_H2C_MASK}, -}; - - -static struct regfield_info - c2h_channel_ctl_field_info[] = { - {"C2H_CHANNEL_CTL_RSVD_1", - C2H_CHANNEL_CTL_RSVD_1_MASK}, - {"C2H_CHANNEL_CTL_RUN", - C2H_CHANNEL_CTL_RUN_MASK}, -}; - - -static struct regfield_info - c2h_channel_ctl_1_field_info[] = { - {"C2H_CHANNEL_CTL_1_RUN", - C2H_CHANNEL_CTL_1_RUN_MASK}, - {"C2H_CHANNEL_CTL_1_RUN_1", - C2H_CHANNEL_CTL_1_RUN_1_MASK}, -}; - - -static struct regfield_info - c2h_mm_status_field_info[] = { - {"C2H_MM_STATUS_RSVD_1", - C2H_MM_STATUS_RSVD_1_MASK}, - {"C2H_MM_STATUS_RUN", - C2H_MM_STATUS_RUN_MASK}, -}; - - -static struct regfield_info - c2h_channel_cmpl_desc_cnt_field_info[] = { - {"C2H_CHANNEL_CMPL_DESC_CNT_C2H_CO", - C2H_CHANNEL_CMPL_DESC_CNT_C2H_CO_MASK}, -}; - - -static struct regfield_info - c2h_mm_err_code_enable_mask_field_info[] = { - {"C2H_MM_ERR_CODE_ENABLE_RSVD_1", - C2H_MM_ERR_CODE_ENABLE_RSVD_1_MASK}, - {"C2H_MM_ERR_CODE_ENABLE_WR_UC_RAM", - C2H_MM_ERR_CODE_ENABLE_WR_UC_RAM_MASK}, - {"C2H_MM_ERR_CODE_ENABLE_WR_UR", - C2H_MM_ERR_CODE_ENABLE_WR_UR_MASK}, - {"C2H_MM_ERR_CODE_ENABLE_WR_FLR", - C2H_MM_ERR_CODE_ENABLE_WR_FLR_MASK}, - {"C2H_MM_ERR_CODE_ENABLE_RSVD_2", - C2H_MM_ERR_CODE_ENABLE_RSVD_2_MASK}, - {"C2H_MM_ERR_CODE_ENABLE_RD_SLV_ERR", - C2H_MM_ERR_CODE_ENABLE_RD_SLV_ERR_MASK}, - {"C2H_MM_ERR_CODE_ENABLE_WR_SLV_ERR", - C2H_MM_ERR_CODE_ENABLE_WR_SLV_ERR_MASK}, -}; - - -static struct regfield_info - c2h_mm_err_code_field_info[] = { - {"C2H_MM_ERR_CODE_RSVD_1", - C2H_MM_ERR_CODE_RSVD_1_MASK}, - {"C2H_MM_ERR_CODE_VALID", - C2H_MM_ERR_CODE_VALID_MASK}, - {"C2H_MM_ERR_CODE_RDWR", - C2H_MM_ERR_CODE_RDWR_MASK}, - {"C2H_MM_ERR_CODE", - C2H_MM_ERR_CODE_MASK}, -}; - - -static struct regfield_info - c2h_mm_err_info_field_info[] = { - {"C2H_MM_ERR_INFO_RSVD_1", - C2H_MM_ERR_INFO_RSVD_1_MASK}, - {"C2H_MM_ERR_INFO_QID", - C2H_MM_ERR_INFO_QID_MASK}, - {"C2H_MM_ERR_INFO_DIR", - C2H_MM_ERR_INFO_DIR_MASK}, - {"C2H_MM_ERR_INFO_CIDX", - C2H_MM_ERR_INFO_CIDX_MASK}, -}; - - -static struct regfield_info - c2h_mm_perf_mon_ctl_field_info[] = { - {"C2H_MM_PERF_MON_CTL_RSVD_1", - C2H_MM_PERF_MON_CTL_RSVD_1_MASK}, - {"C2H_MM_PERF_MON_CTL_IMM_START", - C2H_MM_PERF_MON_CTL_IMM_START_MASK}, - {"C2H_MM_PERF_MON_CTL_RUN_START", - C2H_MM_PERF_MON_CTL_RUN_START_MASK}, - {"C2H_MM_PERF_MON_CTL_IMM_CLEAR", - C2H_MM_PERF_MON_CTL_IMM_CLEAR_MASK}, - {"C2H_MM_PERF_MON_CTL_RUN_CLEAR", - C2H_MM_PERF_MON_CTL_RUN_CLEAR_MASK}, -}; - - -static struct regfield_info - c2h_mm_perf_mon_cycle_cnt0_field_info[] = { - {"C2H_MM_PERF_MON_CYCLE_CNT0_CYC_CNT", - C2H_MM_PERF_MON_CYCLE_CNT0_CYC_CNT_MASK}, -}; - - -static struct regfield_info - c2h_mm_perf_mon_cycle_cnt1_field_info[] = { - {"C2H_MM_PERF_MON_CYCLE_CNT1_RSVD_1", - C2H_MM_PERF_MON_CYCLE_CNT1_RSVD_1_MASK}, - {"C2H_MM_PERF_MON_CYCLE_CNT1_CYC_CNT", - C2H_MM_PERF_MON_CYCLE_CNT1_CYC_CNT_MASK}, -}; - - -static struct regfield_info - c2h_mm_perf_mon_data_cnt0_field_info[] = { - {"C2H_MM_PERF_MON_DATA_CNT0_DCNT", - C2H_MM_PERF_MON_DATA_CNT0_DCNT_MASK}, -}; - - -static struct regfield_info - c2h_mm_perf_mon_data_cnt1_field_info[] = { - {"C2H_MM_PERF_MON_DATA_CNT1_RSVD_1", - C2H_MM_PERF_MON_DATA_CNT1_RSVD_1_MASK}, - {"C2H_MM_PERF_MON_DATA_CNT1_DCNT", - C2H_MM_PERF_MON_DATA_CNT1_DCNT_MASK}, -}; - - -static struct regfield_info - c2h_mm_dbg_field_info[] = { - {"C2H_MM_RSVD_1", - C2H_MM_RSVD_1_MASK}, - {"C2H_MM_RRQ_ENTRIES", - C2H_MM_RRQ_ENTRIES_MASK}, - {"C2H_MM_DAT_FIFO_SPC", - C2H_MM_DAT_FIFO_SPC_MASK}, - {"C2H_MM_RD_STALL", - C2H_MM_RD_STALL_MASK}, - {"C2H_MM_RRQ_FIFO_FI", - C2H_MM_RRQ_FIFO_FI_MASK}, - {"C2H_MM_WR_STALL", - C2H_MM_WR_STALL_MASK}, - {"C2H_MM_WRQ_FIFO_FI", - C2H_MM_WRQ_FIFO_FI_MASK}, - {"C2H_MM_WBK_STALL", - C2H_MM_WBK_STALL_MASK}, - {"C2H_MM_DSC_FIFO_EP", - C2H_MM_DSC_FIFO_EP_MASK}, - {"C2H_MM_DSC_FIFO_FL", - C2H_MM_DSC_FIFO_FL_MASK}, -}; - - -static struct regfield_info - h2c_channel_ctl_field_info[] = { - {"H2C_CHANNEL_CTL_RSVD_1", - H2C_CHANNEL_CTL_RSVD_1_MASK}, - {"H2C_CHANNEL_CTL_RUN", - H2C_CHANNEL_CTL_RUN_MASK}, -}; - - -static struct regfield_info - h2c_channel_ctl_1_field_info[] = { - {"H2C_CHANNEL_CTL_1_RUN", - H2C_CHANNEL_CTL_1_RUN_MASK}, -}; - - -static struct regfield_info - h2c_channel_ctl_2_field_info[] = { - {"H2C_CHANNEL_CTL_2_RUN", - H2C_CHANNEL_CTL_2_RUN_MASK}, -}; - - -static struct regfield_info - h2c_mm_status_field_info[] = { - {"H2C_MM_STATUS_RSVD_1", - H2C_MM_STATUS_RSVD_1_MASK}, - {"H2C_MM_STATUS_RUN", - H2C_MM_STATUS_RUN_MASK}, -}; - - -static struct regfield_info - h2c_channel_cmpl_desc_cnt_field_info[] = { - {"H2C_CHANNEL_CMPL_DESC_CNT_H2C_CO", - H2C_CHANNEL_CMPL_DESC_CNT_H2C_CO_MASK}, -}; - - -static struct regfield_info - h2c_mm_err_code_enable_mask_field_info[] = { - {"H2C_MM_ERR_CODE_ENABLE_RSVD_1", - H2C_MM_ERR_CODE_ENABLE_RSVD_1_MASK}, - {"H2C_MM_ERR_CODE_ENABLE_WR_SLV_ERR", - H2C_MM_ERR_CODE_ENABLE_WR_SLV_ERR_MASK}, - {"H2C_MM_ERR_CODE_ENABLE_WR_DEC_ERR", - H2C_MM_ERR_CODE_ENABLE_WR_DEC_ERR_MASK}, - {"H2C_MM_ERR_CODE_ENABLE_RSVD_2", - H2C_MM_ERR_CODE_ENABLE_RSVD_2_MASK}, - {"H2C_MM_ERR_CODE_ENABLE_RD_RQ_DIS_ERR", - H2C_MM_ERR_CODE_ENABLE_RD_RQ_DIS_ERR_MASK}, - {"H2C_MM_ERR_CODE_ENABLE_RSVD_3", - H2C_MM_ERR_CODE_ENABLE_RSVD_3_MASK}, - {"H2C_MM_ERR_CODE_ENABLE_RD_DAT_POISON_ERR", - H2C_MM_ERR_CODE_ENABLE_RD_DAT_POISON_ERR_MASK}, - {"H2C_MM_ERR_CODE_ENABLE_RSVD_4", - H2C_MM_ERR_CODE_ENABLE_RSVD_4_MASK}, - {"H2C_MM_ERR_CODE_ENABLE_RD_FLR_ERR", - H2C_MM_ERR_CODE_ENABLE_RD_FLR_ERR_MASK}, - {"H2C_MM_ERR_CODE_ENABLE_RSVD_5", - H2C_MM_ERR_CODE_ENABLE_RSVD_5_MASK}, - {"H2C_MM_ERR_CODE_ENABLE_RD_HDR_ADR_ERR", - H2C_MM_ERR_CODE_ENABLE_RD_HDR_ADR_ERR_MASK}, - {"H2C_MM_ERR_CODE_ENABLE_RD_HDR_PARA", - H2C_MM_ERR_CODE_ENABLE_RD_HDR_PARA_MASK}, - {"H2C_MM_ERR_CODE_ENABLE_RD_HDR_BYTE_ERR", - H2C_MM_ERR_CODE_ENABLE_RD_HDR_BYTE_ERR_MASK}, - {"H2C_MM_ERR_CODE_ENABLE_RD_UR_CA", - H2C_MM_ERR_CODE_ENABLE_RD_UR_CA_MASK}, - {"H2C_MM_ERR_CODE_ENABLE_RD_HRD_POISON_ERR", - H2C_MM_ERR_CODE_ENABLE_RD_HRD_POISON_ERR_MASK}, - {"H2C_MM_ERR_CODE_ENABLE_RSVD_6", - H2C_MM_ERR_CODE_ENABLE_RSVD_6_MASK}, -}; - - -static struct regfield_info - h2c_mm_err_code_field_info[] = { - {"H2C_MM_ERR_CODE_RSVD_1", - H2C_MM_ERR_CODE_RSVD_1_MASK}, - {"H2C_MM_ERR_CODE_VALID", - H2C_MM_ERR_CODE_VALID_MASK}, - {"H2C_MM_ERR_CODE_RDWR", - H2C_MM_ERR_CODE_RDWR_MASK}, - {"H2C_MM_ERR_CODE", - H2C_MM_ERR_CODE_MASK}, -}; - - -static struct regfield_info - h2c_mm_err_info_field_info[] = { - {"H2C_MM_ERR_INFO_RSVD_1", - H2C_MM_ERR_INFO_RSVD_1_MASK}, - {"H2C_MM_ERR_INFO_QID", - H2C_MM_ERR_INFO_QID_MASK}, - {"H2C_MM_ERR_INFO_DIR", - H2C_MM_ERR_INFO_DIR_MASK}, - {"H2C_MM_ERR_INFO_CIDX", - H2C_MM_ERR_INFO_CIDX_MASK}, -}; - - -static struct regfield_info - h2c_mm_perf_mon_ctl_field_info[] = { - {"H2C_MM_PERF_MON_CTL_RSVD_1", - H2C_MM_PERF_MON_CTL_RSVD_1_MASK}, - {"H2C_MM_PERF_MON_CTL_IMM_START", - H2C_MM_PERF_MON_CTL_IMM_START_MASK}, - {"H2C_MM_PERF_MON_CTL_RUN_START", - H2C_MM_PERF_MON_CTL_RUN_START_MASK}, - {"H2C_MM_PERF_MON_CTL_IMM_CLEAR", - H2C_MM_PERF_MON_CTL_IMM_CLEAR_MASK}, - {"H2C_MM_PERF_MON_CTL_RUN_CLEAR", - H2C_MM_PERF_MON_CTL_RUN_CLEAR_MASK}, -}; - - -static struct regfield_info - h2c_mm_perf_mon_cycle_cnt0_field_info[] = { - {"H2C_MM_PERF_MON_CYCLE_CNT0_CYC_CNT", - H2C_MM_PERF_MON_CYCLE_CNT0_CYC_CNT_MASK}, -}; - - -static struct regfield_info - h2c_mm_perf_mon_cycle_cnt1_field_info[] = { - {"H2C_MM_PERF_MON_CYCLE_CNT1_RSVD_1", - H2C_MM_PERF_MON_CYCLE_CNT1_RSVD_1_MASK}, - {"H2C_MM_PERF_MON_CYCLE_CNT1_CYC_CNT", - H2C_MM_PERF_MON_CYCLE_CNT1_CYC_CNT_MASK}, -}; - - -static struct regfield_info - h2c_mm_perf_mon_data_cnt0_field_info[] = { - {"H2C_MM_PERF_MON_DATA_CNT0_DCNT", - H2C_MM_PERF_MON_DATA_CNT0_DCNT_MASK}, -}; - - -static struct regfield_info - h2c_mm_perf_mon_data_cnt1_field_info[] = { - {"H2C_MM_PERF_MON_DATA_CNT1_RSVD_1", - H2C_MM_PERF_MON_DATA_CNT1_RSVD_1_MASK}, - {"H2C_MM_PERF_MON_DATA_CNT1_DCNT", - H2C_MM_PERF_MON_DATA_CNT1_DCNT_MASK}, -}; - - -static struct regfield_info - h2c_mm_dbg_field_info[] = { - {"H2C_MM_RSVD_1", - H2C_MM_RSVD_1_MASK}, - {"H2C_MM_RRQ_ENTRIES", - H2C_MM_RRQ_ENTRIES_MASK}, - {"H2C_MM_DAT_FIFO_SPC", - H2C_MM_DAT_FIFO_SPC_MASK}, - {"H2C_MM_RD_STALL", - H2C_MM_RD_STALL_MASK}, - {"H2C_MM_RRQ_FIFO_FI", - H2C_MM_RRQ_FIFO_FI_MASK}, - {"H2C_MM_WR_STALL", - H2C_MM_WR_STALL_MASK}, - {"H2C_MM_WRQ_FIFO_FI", - H2C_MM_WRQ_FIFO_FI_MASK}, - {"H2C_MM_WBK_STALL", - H2C_MM_WBK_STALL_MASK}, - {"H2C_MM_DSC_FIFO_EP", - H2C_MM_DSC_FIFO_EP_MASK}, - {"H2C_MM_DSC_FIFO_FL", - H2C_MM_DSC_FIFO_FL_MASK}, -}; - - -static struct regfield_info - func_status_reg_field_info[] = { - {"FUNC_STATUS_REG_RSVD_1", - FUNC_STATUS_REG_RSVD_1_MASK}, - {"FUNC_STATUS_REG_CUR_SRC_FN", - FUNC_STATUS_REG_CUR_SRC_FN_MASK}, - {"FUNC_STATUS_REG_ACK", - FUNC_STATUS_REG_ACK_MASK}, - {"FUNC_STATUS_REG_O_MSG", - FUNC_STATUS_REG_O_MSG_MASK}, - {"FUNC_STATUS_REG_I_MSG", - FUNC_STATUS_REG_I_MSG_MASK}, -}; - - -static struct regfield_info - func_cmd_reg_field_info[] = { - {"FUNC_CMD_REG_RSVD_1", - FUNC_CMD_REG_RSVD_1_MASK}, - {"FUNC_CMD_REG_RSVD_2", - FUNC_CMD_REG_RSVD_2_MASK}, - {"FUNC_CMD_REG_MSG_RCV", - FUNC_CMD_REG_MSG_RCV_MASK}, - {"FUNC_CMD_REG_MSG_SENT", - FUNC_CMD_REG_MSG_SENT_MASK}, -}; - - -static struct regfield_info - func_interrupt_vector_reg_field_info[] = { - {"FUNC_INTERRUPT_VECTOR_REG_RSVD_1", - FUNC_INTERRUPT_VECTOR_REG_RSVD_1_MASK}, - {"FUNC_INTERRUPT_VECTOR_REG_IN", - FUNC_INTERRUPT_VECTOR_REG_IN_MASK}, -}; - - -static struct regfield_info - target_func_reg_field_info[] = { - {"TARGET_FUNC_REG_RSVD_1", - TARGET_FUNC_REG_RSVD_1_MASK}, - {"TARGET_FUNC_REG_N_ID", - TARGET_FUNC_REG_N_ID_MASK}, -}; - - -static struct regfield_info - func_interrupt_ctl_reg_field_info[] = { - {"FUNC_INTERRUPT_CTL_REG_RSVD_1", - FUNC_INTERRUPT_CTL_REG_RSVD_1_MASK}, - {"FUNC_INTERRUPT_CTL_REG_INT_EN", - FUNC_INTERRUPT_CTL_REG_INT_EN_MASK}, -}; - -static struct xreg_info qdma_cpm4_config_regs[] = { -{"CFG_BLK_IDENTIFIER", 0x00, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(cfg_blk_identifier_field_info), - cfg_blk_identifier_field_info -}, -{"CFG_BLK_BUSDEV", 0x04, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(cfg_blk_busdev_field_info), - cfg_blk_busdev_field_info -}, -{"CFG_BLK_PCIE_MAX_PLD_SIZE", 0x08, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(cfg_blk_pcie_max_pld_size_field_info), - cfg_blk_pcie_max_pld_size_field_info -}, -{"CFG_BLK_PCIE_MAX_READ_REQ_SIZE", 0x0c, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(cfg_blk_pcie_max_read_req_size_field_info), - cfg_blk_pcie_max_read_req_size_field_info -}, -{"CFG_BLK_SYSTEM_ID", 0x10, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(cfg_blk_system_id_field_info), - cfg_blk_system_id_field_info -}, -{"CFG_BLK_MSI_ENABLE", 0x014, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(cfg_blk_msi_enable_field_info), - cfg_blk_msi_enable_field_info -}, -{"CFG_PCIE_DATA_WIDTH", 0x18, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(cfg_pcie_data_width_field_info), - cfg_pcie_data_width_field_info -}, -{"CFG_PCIE_CTL", 0x1c, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(cfg_pcie_ctl_field_info), - cfg_pcie_ctl_field_info -}, -{"CFG_AXI_USER_MAX_PLD_SIZE", 0x40, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(cfg_axi_user_max_pld_size_field_info), - cfg_axi_user_max_pld_size_field_info -}, -{"CFG_AXI_USER_MAX_READ_REQ_SIZE", 0x44, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(cfg_axi_user_max_read_req_size_field_info), - cfg_axi_user_max_read_req_size_field_info -}, -{"CFG_BLK_MISC_CTL", 0x4c, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(cfg_blk_misc_ctl_field_info), - cfg_blk_misc_ctl_field_info -}, -{"CFG_BLK_SCRATCH_0", 0x80, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(cfg_blk_scratch_0_field_info), - cfg_blk_scratch_0_field_info -}, -{"CFG_BLK_SCRATCH_1", 0x84, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(cfg_blk_scratch_1_field_info), - cfg_blk_scratch_1_field_info -}, -{"CFG_BLK_SCRATCH_2", 0x88, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(cfg_blk_scratch_2_field_info), - cfg_blk_scratch_2_field_info -}, -{"CFG_BLK_SCRATCH_3", 0x8c, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(cfg_blk_scratch_3_field_info), - cfg_blk_scratch_3_field_info -}, -{"CFG_BLK_SCRATCH_4", 0x90, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(cfg_blk_scratch_4_field_info), - cfg_blk_scratch_4_field_info -}, -{"CFG_BLK_SCRATCH_5", 0x94, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(cfg_blk_scratch_5_field_info), - cfg_blk_scratch_5_field_info -}, -{"CFG_BLK_SCRATCH_6", 0x98, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(cfg_blk_scratch_6_field_info), - cfg_blk_scratch_6_field_info -}, -{"CFG_BLK_SCRATCH_7", 0x9c, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(cfg_blk_scratch_7_field_info), - cfg_blk_scratch_7_field_info -}, -{"RAM_SBE_MSK_A", 0xf0, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(ram_sbe_msk_a_field_info), - ram_sbe_msk_a_field_info -}, -{"RAM_SBE_STS_A", 0xf4, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(ram_sbe_sts_a_field_info), - ram_sbe_sts_a_field_info -}, -{"RAM_DBE_MSK_A", 0xf8, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(ram_dbe_msk_a_field_info), - ram_dbe_msk_a_field_info -}, -{"RAM_DBE_STS_A", 0xfc, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(ram_dbe_sts_a_field_info), - ram_dbe_sts_a_field_info -}, -{"GLBL2_IDENTIFIER", 0x100, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(glbl2_identifier_field_info), - glbl2_identifier_field_info -}, -{"GLBL2_PF_BARLITE_INT", 0x104, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(glbl2_pf_barlite_int_field_info), - glbl2_pf_barlite_int_field_info -}, -{"GLBL2_PF_VF_BARLITE_INT", 0x108, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(glbl2_pf_vf_barlite_int_field_info), - glbl2_pf_vf_barlite_int_field_info -}, -{"GLBL2_PF_BARLITE_EXT", 0x10c, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(glbl2_pf_barlite_ext_field_info), - glbl2_pf_barlite_ext_field_info -}, -{"GLBL2_PF_VF_BARLITE_EXT", 0x110, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(glbl2_pf_vf_barlite_ext_field_info), - glbl2_pf_vf_barlite_ext_field_info -}, -{"GLBL2_CHANNEL_INST", 0x114, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(glbl2_channel_inst_field_info), - glbl2_channel_inst_field_info -}, -{"GLBL2_CHANNEL_MDMA", 0x118, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(glbl2_channel_mdma_field_info), - glbl2_channel_mdma_field_info -}, -{"GLBL2_CHANNEL_STRM", 0x11c, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(glbl2_channel_strm_field_info), - glbl2_channel_strm_field_info -}, -{"GLBL2_CHANNEL_CAP", 0x120, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(glbl2_channel_cap_field_info), - glbl2_channel_cap_field_info -}, -{"GLBL2_CHANNEL_PASID_CAP", 0x128, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(glbl2_channel_pasid_cap_field_info), - glbl2_channel_pasid_cap_field_info -}, -{"GLBL2_CHANNEL_FUNC_RET", 0x12c, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(glbl2_channel_func_ret_field_info), - glbl2_channel_func_ret_field_info -}, -{"GLBL2_SYSTEM_ID", 0x130, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(glbl2_system_id_field_info), - glbl2_system_id_field_info -}, -{"GLBL2_MISC_CAP", 0x134, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(glbl2_misc_cap_field_info), - glbl2_misc_cap_field_info -}, -{"GLBL2_DBG_PCIE_RQ0", 0x1b8, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(glbl2_dbg_pcie_rq0_field_info), - glbl2_dbg_pcie_rq0_field_info -}, -{"GLBL2_DBG_PCIE_RQ1", 0x1bc, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(glbl2_dbg_pcie_rq1_field_info), - glbl2_dbg_pcie_rq1_field_info -}, -{"GLBL2_DBG_AXIMM_WR0", 0x1c0, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(glbl2_dbg_aximm_wr0_field_info), - glbl2_dbg_aximm_wr0_field_info -}, -{"GLBL2_DBG_AXIMM_WR1", 0x1c4, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(glbl2_dbg_aximm_wr1_field_info), - glbl2_dbg_aximm_wr1_field_info -}, -{"GLBL2_DBG_AXIMM_RD0", 0x1c8, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(glbl2_dbg_aximm_rd0_field_info), - glbl2_dbg_aximm_rd0_field_info -}, -{"GLBL2_DBG_AXIMM_RD1", 0x1cc, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(glbl2_dbg_aximm_rd1_field_info), - glbl2_dbg_aximm_rd1_field_info -}, -{"GLBL_RNG_SZ_1", 0x204, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(glbl_rng_sz_1_field_info), - glbl_rng_sz_1_field_info -}, -{"GLBL_RNG_SZ_2", 0x208, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(glbl_rng_sz_2_field_info), - glbl_rng_sz_2_field_info -}, -{"GLBL_RNG_SZ_3", 0x20c, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(glbl_rng_sz_3_field_info), - glbl_rng_sz_3_field_info -}, -{"GLBL_RNG_SZ_4", 0x210, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(glbl_rng_sz_4_field_info), - glbl_rng_sz_4_field_info -}, -{"GLBL_RNG_SZ_5", 0x214, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(glbl_rng_sz_5_field_info), - glbl_rng_sz_5_field_info -}, -{"GLBL_RNG_SZ_6", 0x218, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(glbl_rng_sz_6_field_info), - glbl_rng_sz_6_field_info -}, -{"GLBL_RNG_SZ_7", 0x21c, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(glbl_rng_sz_7_field_info), - glbl_rng_sz_7_field_info -}, -{"GLBL_RNG_SZ_8", 0x220, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(glbl_rng_sz_8_field_info), - glbl_rng_sz_8_field_info -}, -{"GLBL_RNG_SZ_9", 0x224, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(glbl_rng_sz_9_field_info), - glbl_rng_sz_9_field_info -}, -{"GLBL_RNG_SZ_A", 0x228, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(glbl_rng_sz_a_field_info), - glbl_rng_sz_a_field_info -}, -{"GLBL_RNG_SZ_B", 0x22c, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(glbl_rng_sz_b_field_info), - glbl_rng_sz_b_field_info -}, -{"GLBL_RNG_SZ_C", 0x230, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(glbl_rng_sz_c_field_info), - glbl_rng_sz_c_field_info -}, -{"GLBL_RNG_SZ_D", 0x234, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(glbl_rng_sz_d_field_info), - glbl_rng_sz_d_field_info -}, -{"GLBL_RNG_SZ_E", 0x238, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(glbl_rng_sz_e_field_info), - glbl_rng_sz_e_field_info -}, -{"GLBL_RNG_SZ_F", 0x23c, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(glbl_rng_sz_f_field_info), - glbl_rng_sz_f_field_info -}, -{"GLBL_RNG_SZ_10", 0x240, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(glbl_rng_sz_10_field_info), - glbl_rng_sz_10_field_info -}, -{"GLBL_ERR_STAT", 0x248, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(glbl_err_stat_field_info), - glbl_err_stat_field_info -}, -{"GLBL_ERR_MASK", 0x24c, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(glbl_err_mask_field_info), - glbl_err_mask_field_info -}, -{"GLBL_DSC_CFG", 0x250, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(glbl_dsc_cfg_field_info), - glbl_dsc_cfg_field_info -}, -{"GLBL_DSC_ERR_STS", 0x254, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(glbl_dsc_err_sts_field_info), - glbl_dsc_err_sts_field_info -}, -{"GLBL_DSC_ERR_MSK", 0x258, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(glbl_dsc_err_msk_field_info), - glbl_dsc_err_msk_field_info -}, -{"GLBL_DSC_ERR_LOG0", 0x25c, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(glbl_dsc_err_log0_field_info), - glbl_dsc_err_log0_field_info -}, -{"GLBL_DSC_ERR_LOG1", 0x260, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(glbl_dsc_err_log1_field_info), - glbl_dsc_err_log1_field_info -}, -{"GLBL_TRQ_ERR_STS", 0x264, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(glbl_trq_err_sts_field_info), - glbl_trq_err_sts_field_info -}, -{"GLBL_TRQ_ERR_MSK", 0x268, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(glbl_trq_err_msk_field_info), - glbl_trq_err_msk_field_info -}, -{"GLBL_TRQ_ERR_LOG", 0x26c, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(glbl_trq_err_log_field_info), - glbl_trq_err_log_field_info -}, -{"GLBL_DSC_DBG_DAT0", 0x270, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(glbl_dsc_dbg_dat0_field_info), - glbl_dsc_dbg_dat0_field_info -}, -{"GLBL_DSC_DBG_DAT1", 0x274, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(glbl_dsc_dbg_dat1_field_info), - glbl_dsc_dbg_dat1_field_info -}, -{"TRQ_SEL_FMAP_0", 0x400, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_0_field_info), - trq_sel_fmap_0_field_info -}, -{"TRQ_SEL_FMAP_1", 0x404, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_1_field_info), - trq_sel_fmap_1_field_info -}, -{"TRQ_SEL_FMAP_2", 0x408, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_2_field_info), - trq_sel_fmap_2_field_info -}, -{"TRQ_SEL_FMAP_3", 0x40c, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_3_field_info), - trq_sel_fmap_3_field_info -}, -{"TRQ_SEL_FMAP_4", 0x410, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_4_field_info), - trq_sel_fmap_4_field_info -}, -{"TRQ_SEL_FMAP_5", 0x414, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_5_field_info), - trq_sel_fmap_5_field_info -}, -{"TRQ_SEL_FMAP_6", 0x418, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_6_field_info), - trq_sel_fmap_6_field_info -}, -{"TRQ_SEL_FMAP_7", 0x41c, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_7_field_info), - trq_sel_fmap_7_field_info -}, -{"TRQ_SEL_FMAP_8", 0x420, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_8_field_info), - trq_sel_fmap_8_field_info -}, -{"TRQ_SEL_FMAP_9", 0x424, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_9_field_info), - trq_sel_fmap_9_field_info -}, -{"TRQ_SEL_FMAP_A", 0x428, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_a_field_info), - trq_sel_fmap_a_field_info -}, -{"TRQ_SEL_FMAP_B", 0x42c, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_b_field_info), - trq_sel_fmap_b_field_info -}, -{"TRQ_SEL_FMAP_D", 0x430, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_d_field_info), - trq_sel_fmap_d_field_info -}, -{"TRQ_SEL_FMAP_E", 0x434, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_e_field_info), - trq_sel_fmap_e_field_info -}, -{"TRQ_SEL_FMAP_F", 0x438, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_f_field_info), - trq_sel_fmap_f_field_info -}, -{"TRQ_SEL_FMAP_10", 0x43c, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_10_field_info), - trq_sel_fmap_10_field_info -}, -{"TRQ_SEL_FMAP_11", 0x440, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_11_field_info), - trq_sel_fmap_11_field_info -}, -{"TRQ_SEL_FMAP_12", 0x444, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_12_field_info), - trq_sel_fmap_12_field_info -}, -{"TRQ_SEL_FMAP_13", 0x448, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_13_field_info), - trq_sel_fmap_13_field_info -}, -{"TRQ_SEL_FMAP_14", 0x44c, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_14_field_info), - trq_sel_fmap_14_field_info -}, -{"TRQ_SEL_FMAP_15", 0x450, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_15_field_info), - trq_sel_fmap_15_field_info -}, -{"TRQ_SEL_FMAP_16", 0x454, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_16_field_info), - trq_sel_fmap_16_field_info -}, -{"TRQ_SEL_FMAP_17", 0x458, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_17_field_info), - trq_sel_fmap_17_field_info -}, -{"TRQ_SEL_FMAP_18", 0x45c, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_18_field_info), - trq_sel_fmap_18_field_info -}, -{"TRQ_SEL_FMAP_19", 0x460, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_19_field_info), - trq_sel_fmap_19_field_info -}, -{"TRQ_SEL_FMAP_1A", 0x464, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_1a_field_info), - trq_sel_fmap_1a_field_info -}, -{"TRQ_SEL_FMAP_1B", 0x468, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_1b_field_info), - trq_sel_fmap_1b_field_info -}, -{"TRQ_SEL_FMAP_1C", 0x46c, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_1c_field_info), - trq_sel_fmap_1c_field_info -}, -{"TRQ_SEL_FMAP_1D", 0x470, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_1d_field_info), - trq_sel_fmap_1d_field_info -}, -{"TRQ_SEL_FMAP_1E", 0x474, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_1e_field_info), - trq_sel_fmap_1e_field_info -}, -{"TRQ_SEL_FMAP_1F", 0x478, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_1f_field_info), - trq_sel_fmap_1f_field_info -}, -{"TRQ_SEL_FMAP_20", 0x47c, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_20_field_info), - trq_sel_fmap_20_field_info -}, -{"TRQ_SEL_FMAP_21", 0x480, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_21_field_info), - trq_sel_fmap_21_field_info -}, -{"TRQ_SEL_FMAP_22", 0x484, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_22_field_info), - trq_sel_fmap_22_field_info -}, -{"TRQ_SEL_FMAP_23", 0x488, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_23_field_info), - trq_sel_fmap_23_field_info -}, -{"TRQ_SEL_FMAP_24", 0x48c, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_24_field_info), - trq_sel_fmap_24_field_info -}, -{"TRQ_SEL_FMAP_25", 0x490, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_25_field_info), - trq_sel_fmap_25_field_info -}, -{"TRQ_SEL_FMAP_26", 0x494, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_26_field_info), - trq_sel_fmap_26_field_info -}, -{"TRQ_SEL_FMAP_27", 0x498, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_27_field_info), - trq_sel_fmap_27_field_info -}, -{"TRQ_SEL_FMAP_28", 0x49c, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_28_field_info), - trq_sel_fmap_28_field_info -}, -{"TRQ_SEL_FMAP_29", 0x4a0, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_29_field_info), - trq_sel_fmap_29_field_info -}, -{"TRQ_SEL_FMAP_2A", 0x4a4, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_2a_field_info), - trq_sel_fmap_2a_field_info -}, -{"TRQ_SEL_FMAP_2B", 0x4a8, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_2b_field_info), - trq_sel_fmap_2b_field_info -}, -{"TRQ_SEL_FMAP_2C", 0x4ac, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_2c_field_info), - trq_sel_fmap_2c_field_info -}, -{"TRQ_SEL_FMAP_2D", 0x4b0, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_2d_field_info), - trq_sel_fmap_2d_field_info -}, -{"TRQ_SEL_FMAP_2E", 0x4b4, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_2e_field_info), - trq_sel_fmap_2e_field_info -}, -{"TRQ_SEL_FMAP_2F", 0x4b8, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_2f_field_info), - trq_sel_fmap_2f_field_info -}, -{"TRQ_SEL_FMAP_30", 0x4bc, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_30_field_info), - trq_sel_fmap_30_field_info -}, -{"TRQ_SEL_FMAP_31", 0x4d0, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_31_field_info), - trq_sel_fmap_31_field_info -}, -{"TRQ_SEL_FMAP_32", 0x4d4, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_32_field_info), - trq_sel_fmap_32_field_info -}, -{"TRQ_SEL_FMAP_33", 0x4d8, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_33_field_info), - trq_sel_fmap_33_field_info -}, -{"TRQ_SEL_FMAP_34", 0x4dc, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_34_field_info), - trq_sel_fmap_34_field_info -}, -{"TRQ_SEL_FMAP_35", 0x4e0, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_35_field_info), - trq_sel_fmap_35_field_info -}, -{"TRQ_SEL_FMAP_36", 0x4e4, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_36_field_info), - trq_sel_fmap_36_field_info -}, -{"TRQ_SEL_FMAP_37", 0x4e8, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_37_field_info), - trq_sel_fmap_37_field_info -}, -{"TRQ_SEL_FMAP_38", 0x4ec, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_38_field_info), - trq_sel_fmap_38_field_info -}, -{"TRQ_SEL_FMAP_39", 0x4f0, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_39_field_info), - trq_sel_fmap_39_field_info -}, -{"TRQ_SEL_FMAP_3A", 0x4f4, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_3a_field_info), - trq_sel_fmap_3a_field_info -}, -{"TRQ_SEL_FMAP_3B", 0x4f8, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_3b_field_info), - trq_sel_fmap_3b_field_info -}, -{"TRQ_SEL_FMAP_3C", 0x4fc, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_3c_field_info), - trq_sel_fmap_3c_field_info -}, -{"TRQ_SEL_FMAP_3D", 0x500, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_3d_field_info), - trq_sel_fmap_3d_field_info -}, -{"TRQ_SEL_FMAP_3E", 0x504, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_3e_field_info), - trq_sel_fmap_3e_field_info -}, -{"TRQ_SEL_FMAP_3F", 0x508, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_3f_field_info), - trq_sel_fmap_3f_field_info -}, -{"TRQ_SEL_FMAP_40", 0x50c, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_40_field_info), - trq_sel_fmap_40_field_info -}, -{"TRQ_SEL_FMAP_41", 0x510, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_41_field_info), - trq_sel_fmap_41_field_info -}, -{"TRQ_SEL_FMAP_42", 0x514, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_42_field_info), - trq_sel_fmap_42_field_info -}, -{"TRQ_SEL_FMAP_43", 0x518, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_43_field_info), - trq_sel_fmap_43_field_info -}, -{"TRQ_SEL_FMAP_44", 0x51c, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_44_field_info), - trq_sel_fmap_44_field_info -}, -{"TRQ_SEL_FMAP_45", 0x520, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_45_field_info), - trq_sel_fmap_45_field_info -}, -{"TRQ_SEL_FMAP_46", 0x524, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_46_field_info), - trq_sel_fmap_46_field_info -}, -{"TRQ_SEL_FMAP_47", 0x528, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_47_field_info), - trq_sel_fmap_47_field_info -}, -{"TRQ_SEL_FMAP_48", 0x52c, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_48_field_info), - trq_sel_fmap_48_field_info -}, -{"TRQ_SEL_FMAP_49", 0x530, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_49_field_info), - trq_sel_fmap_49_field_info -}, -{"TRQ_SEL_FMAP_4A", 0x534, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_4a_field_info), - trq_sel_fmap_4a_field_info -}, -{"TRQ_SEL_FMAP_4B", 0x538, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_4b_field_info), - trq_sel_fmap_4b_field_info -}, -{"TRQ_SEL_FMAP_4C", 0x53c, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_4c_field_info), - trq_sel_fmap_4c_field_info -}, -{"TRQ_SEL_FMAP_4D", 0x540, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_4d_field_info), - trq_sel_fmap_4d_field_info -}, -{"TRQ_SEL_FMAP_4E", 0x544, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_4e_field_info), - trq_sel_fmap_4e_field_info -}, -{"TRQ_SEL_FMAP_4F", 0x548, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_4f_field_info), - trq_sel_fmap_4f_field_info -}, -{"TRQ_SEL_FMAP_50", 0x54c, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_50_field_info), - trq_sel_fmap_50_field_info -}, -{"TRQ_SEL_FMAP_51", 0x550, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_51_field_info), - trq_sel_fmap_51_field_info -}, -{"TRQ_SEL_FMAP_52", 0x554, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_52_field_info), - trq_sel_fmap_52_field_info -}, -{"TRQ_SEL_FMAP_53", 0x558, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_53_field_info), - trq_sel_fmap_53_field_info -}, -{"TRQ_SEL_FMAP_54", 0x55c, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_54_field_info), - trq_sel_fmap_54_field_info -}, -{"TRQ_SEL_FMAP_55", 0x560, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_55_field_info), - trq_sel_fmap_55_field_info -}, -{"TRQ_SEL_FMAP_56", 0x564, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_56_field_info), - trq_sel_fmap_56_field_info -}, -{"TRQ_SEL_FMAP_57", 0x568, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_57_field_info), - trq_sel_fmap_57_field_info -}, -{"TRQ_SEL_FMAP_58", 0x56c, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_58_field_info), - trq_sel_fmap_58_field_info -}, -{"TRQ_SEL_FMAP_59", 0x570, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_59_field_info), - trq_sel_fmap_59_field_info -}, -{"TRQ_SEL_FMAP_5A", 0x574, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_5a_field_info), - trq_sel_fmap_5a_field_info -}, -{"TRQ_SEL_FMAP_5B", 0x578, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_5b_field_info), - trq_sel_fmap_5b_field_info -}, -{"TRQ_SEL_FMAP_5C", 0x57c, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_5c_field_info), - trq_sel_fmap_5c_field_info -}, -{"TRQ_SEL_FMAP_5D", 0x580, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_5d_field_info), - trq_sel_fmap_5d_field_info -}, -{"TRQ_SEL_FMAP_5E", 0x584, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_5e_field_info), - trq_sel_fmap_5e_field_info -}, -{"TRQ_SEL_FMAP_5F", 0x588, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_5f_field_info), - trq_sel_fmap_5f_field_info -}, -{"TRQ_SEL_FMAP_60", 0x58c, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_60_field_info), - trq_sel_fmap_60_field_info -}, -{"TRQ_SEL_FMAP_61", 0x590, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_61_field_info), - trq_sel_fmap_61_field_info -}, -{"TRQ_SEL_FMAP_62", 0x594, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_62_field_info), - trq_sel_fmap_62_field_info -}, -{"TRQ_SEL_FMAP_63", 0x598, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_63_field_info), - trq_sel_fmap_63_field_info -}, -{"TRQ_SEL_FMAP_64", 0x59c, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_64_field_info), - trq_sel_fmap_64_field_info -}, -{"TRQ_SEL_FMAP_65", 0x5a0, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_65_field_info), - trq_sel_fmap_65_field_info -}, -{"TRQ_SEL_FMAP_66", 0x5a4, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_66_field_info), - trq_sel_fmap_66_field_info -}, -{"TRQ_SEL_FMAP_67", 0x5a8, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_67_field_info), - trq_sel_fmap_67_field_info -}, -{"TRQ_SEL_FMAP_68", 0x5ac, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_68_field_info), - trq_sel_fmap_68_field_info -}, -{"TRQ_SEL_FMAP_69", 0x5b0, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_69_field_info), - trq_sel_fmap_69_field_info -}, -{"TRQ_SEL_FMAP_6A", 0x5b4, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_6a_field_info), - trq_sel_fmap_6a_field_info -}, -{"TRQ_SEL_FMAP_6B", 0x5b8, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_6b_field_info), - trq_sel_fmap_6b_field_info -}, -{"TRQ_SEL_FMAP_6C", 0x5bc, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_6c_field_info), - trq_sel_fmap_6c_field_info -}, -{"TRQ_SEL_FMAP_6D", 0x5c0, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_6d_field_info), - trq_sel_fmap_6d_field_info -}, -{"TRQ_SEL_FMAP_6E", 0x5c4, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_6e_field_info), - trq_sel_fmap_6e_field_info -}, -{"TRQ_SEL_FMAP_6F", 0x5c8, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_6f_field_info), - trq_sel_fmap_6f_field_info -}, -{"TRQ_SEL_FMAP_70", 0x5cc, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_70_field_info), - trq_sel_fmap_70_field_info -}, -{"TRQ_SEL_FMAP_71", 0x5d0, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_71_field_info), - trq_sel_fmap_71_field_info -}, -{"TRQ_SEL_FMAP_72", 0x5d4, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_72_field_info), - trq_sel_fmap_72_field_info -}, -{"TRQ_SEL_FMAP_73", 0x5d8, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_73_field_info), - trq_sel_fmap_73_field_info -}, -{"TRQ_SEL_FMAP_74", 0x5dc, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_74_field_info), - trq_sel_fmap_74_field_info -}, -{"TRQ_SEL_FMAP_75", 0x5e0, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_75_field_info), - trq_sel_fmap_75_field_info -}, -{"TRQ_SEL_FMAP_76", 0x5e4, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_76_field_info), - trq_sel_fmap_76_field_info -}, -{"TRQ_SEL_FMAP_77", 0x5e8, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_77_field_info), - trq_sel_fmap_77_field_info -}, -{"TRQ_SEL_FMAP_78", 0x5ec, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_78_field_info), - trq_sel_fmap_78_field_info -}, -{"TRQ_SEL_FMAP_79", 0x5f0, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_79_field_info), - trq_sel_fmap_79_field_info -}, -{"TRQ_SEL_FMAP_7A", 0x5f4, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_7a_field_info), - trq_sel_fmap_7a_field_info -}, -{"TRQ_SEL_FMAP_7B", 0x5f8, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_7b_field_info), - trq_sel_fmap_7b_field_info -}, -{"TRQ_SEL_FMAP_7C", 0x5fc, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_7c_field_info), - trq_sel_fmap_7c_field_info -}, -{"TRQ_SEL_FMAP_7D", 0x600, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_7d_field_info), - trq_sel_fmap_7d_field_info -}, -{"TRQ_SEL_FMAP_7E", 0x604, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_7e_field_info), - trq_sel_fmap_7e_field_info -}, -{"TRQ_SEL_FMAP_7F", 0x608, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_7f_field_info), - trq_sel_fmap_7f_field_info -}, -{"TRQ_SEL_FMAP_80", 0x60c, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_80_field_info), - trq_sel_fmap_80_field_info -}, -{"TRQ_SEL_FMAP_81", 0x610, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_81_field_info), - trq_sel_fmap_81_field_info -}, -{"TRQ_SEL_FMAP_82", 0x614, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_82_field_info), - trq_sel_fmap_82_field_info -}, -{"TRQ_SEL_FMAP_83", 0x618, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_83_field_info), - trq_sel_fmap_83_field_info -}, -{"TRQ_SEL_FMAP_84", 0x61c, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_84_field_info), - trq_sel_fmap_84_field_info -}, -{"TRQ_SEL_FMAP_85", 0x620, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_85_field_info), - trq_sel_fmap_85_field_info -}, -{"TRQ_SEL_FMAP_86", 0x624, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_86_field_info), - trq_sel_fmap_86_field_info -}, -{"TRQ_SEL_FMAP_87", 0x628, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_87_field_info), - trq_sel_fmap_87_field_info -}, -{"TRQ_SEL_FMAP_88", 0x62c, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_88_field_info), - trq_sel_fmap_88_field_info -}, -{"TRQ_SEL_FMAP_89", 0x630, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_89_field_info), - trq_sel_fmap_89_field_info -}, -{"TRQ_SEL_FMAP_8A", 0x634, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_8a_field_info), - trq_sel_fmap_8a_field_info -}, -{"TRQ_SEL_FMAP_8B", 0x638, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_8b_field_info), - trq_sel_fmap_8b_field_info -}, -{"TRQ_SEL_FMAP_8C", 0x63c, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_8c_field_info), - trq_sel_fmap_8c_field_info -}, -{"TRQ_SEL_FMAP_8D", 0x640, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_8d_field_info), - trq_sel_fmap_8d_field_info -}, -{"TRQ_SEL_FMAP_8E", 0x644, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_8e_field_info), - trq_sel_fmap_8e_field_info -}, -{"TRQ_SEL_FMAP_8F", 0x648, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_8f_field_info), - trq_sel_fmap_8f_field_info -}, -{"TRQ_SEL_FMAP_90", 0x64c, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_90_field_info), - trq_sel_fmap_90_field_info -}, -{"TRQ_SEL_FMAP_91", 0x650, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_91_field_info), - trq_sel_fmap_91_field_info -}, -{"TRQ_SEL_FMAP_92", 0x654, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_92_field_info), - trq_sel_fmap_92_field_info -}, -{"TRQ_SEL_FMAP_93", 0x658, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_93_field_info), - trq_sel_fmap_93_field_info -}, -{"TRQ_SEL_FMAP_94", 0x65c, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_94_field_info), - trq_sel_fmap_94_field_info -}, -{"TRQ_SEL_FMAP_95", 0x660, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_95_field_info), - trq_sel_fmap_95_field_info -}, -{"TRQ_SEL_FMAP_96", 0x664, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_96_field_info), - trq_sel_fmap_96_field_info -}, -{"TRQ_SEL_FMAP_97", 0x668, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_97_field_info), - trq_sel_fmap_97_field_info -}, -{"TRQ_SEL_FMAP_98", 0x66c, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_98_field_info), - trq_sel_fmap_98_field_info -}, -{"TRQ_SEL_FMAP_99", 0x670, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_99_field_info), - trq_sel_fmap_99_field_info -}, -{"TRQ_SEL_FMAP_9A", 0x674, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_9a_field_info), - trq_sel_fmap_9a_field_info -}, -{"TRQ_SEL_FMAP_9B", 0x678, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_9b_field_info), - trq_sel_fmap_9b_field_info -}, -{"TRQ_SEL_FMAP_9C", 0x67c, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_9c_field_info), - trq_sel_fmap_9c_field_info -}, -{"TRQ_SEL_FMAP_9D", 0x680, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_9d_field_info), - trq_sel_fmap_9d_field_info -}, -{"TRQ_SEL_FMAP_9E", 0x684, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_9e_field_info), - trq_sel_fmap_9e_field_info -}, -{"TRQ_SEL_FMAP_9F", 0x688, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_9f_field_info), - trq_sel_fmap_9f_field_info -}, -{"TRQ_SEL_FMAP_A0", 0x68c, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_a0_field_info), - trq_sel_fmap_a0_field_info -}, -{"TRQ_SEL_FMAP_A1", 0x690, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_a1_field_info), - trq_sel_fmap_a1_field_info -}, -{"TRQ_SEL_FMAP_A2", 0x694, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_a2_field_info), - trq_sel_fmap_a2_field_info -}, -{"TRQ_SEL_FMAP_A3", 0x698, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_a3_field_info), - trq_sel_fmap_a3_field_info -}, -{"TRQ_SEL_FMAP_A4", 0x69c, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_a4_field_info), - trq_sel_fmap_a4_field_info -}, -{"TRQ_SEL_FMAP_A5", 0x6a0, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_a5_field_info), - trq_sel_fmap_a5_field_info -}, -{"TRQ_SEL_FMAP_A6", 0x6a4, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_a6_field_info), - trq_sel_fmap_a6_field_info -}, -{"TRQ_SEL_FMAP_A7", 0x6a8, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_a7_field_info), - trq_sel_fmap_a7_field_info -}, -{"TRQ_SEL_FMAP_A8", 0x6ac, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_a8_field_info), - trq_sel_fmap_a8_field_info -}, -{"TRQ_SEL_FMAP_A9", 0x6b0, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_a9_field_info), - trq_sel_fmap_a9_field_info -}, -{"TRQ_SEL_FMAP_AA", 0x6b4, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_aa_field_info), - trq_sel_fmap_aa_field_info -}, -{"TRQ_SEL_FMAP_AB", 0x6b8, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_ab_field_info), - trq_sel_fmap_ab_field_info -}, -{"TRQ_SEL_FMAP_AC", 0x6bc, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_ac_field_info), - trq_sel_fmap_ac_field_info -}, -{"TRQ_SEL_FMAP_AD", 0x6d0, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_ad_field_info), - trq_sel_fmap_ad_field_info -}, -{"TRQ_SEL_FMAP_AE", 0x6d4, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_ae_field_info), - trq_sel_fmap_ae_field_info -}, -{"TRQ_SEL_FMAP_AF", 0x6d8, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_af_field_info), - trq_sel_fmap_af_field_info -}, -{"TRQ_SEL_FMAP_B0", 0x6dc, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_b0_field_info), - trq_sel_fmap_b0_field_info -}, -{"TRQ_SEL_FMAP_B1", 0x6e0, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_b1_field_info), - trq_sel_fmap_b1_field_info -}, -{"TRQ_SEL_FMAP_B2", 0x6e4, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_b2_field_info), - trq_sel_fmap_b2_field_info -}, -{"TRQ_SEL_FMAP_B3", 0x6e8, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_b3_field_info), - trq_sel_fmap_b3_field_info -}, -{"TRQ_SEL_FMAP_B4", 0x6ec, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_b4_field_info), - trq_sel_fmap_b4_field_info -}, -{"TRQ_SEL_FMAP_B5", 0x6f0, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_b5_field_info), - trq_sel_fmap_b5_field_info -}, -{"TRQ_SEL_FMAP_B6", 0x6f4, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_b6_field_info), - trq_sel_fmap_b6_field_info -}, -{"TRQ_SEL_FMAP_B7", 0x6f8, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_b7_field_info), - trq_sel_fmap_b7_field_info -}, -{"TRQ_SEL_FMAP_B8", 0x6fc, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_b8_field_info), - trq_sel_fmap_b8_field_info -}, -{"TRQ_SEL_FMAP_B9", 0x700, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_b9_field_info), - trq_sel_fmap_b9_field_info -}, -{"TRQ_SEL_FMAP_BA", 0x704, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_ba_field_info), - trq_sel_fmap_ba_field_info -}, -{"TRQ_SEL_FMAP_BB", 0x708, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_bb_field_info), - trq_sel_fmap_bb_field_info -}, -{"TRQ_SEL_FMAP_BC", 0x70c, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_bc_field_info), - trq_sel_fmap_bc_field_info -}, -{"TRQ_SEL_FMAP_BD", 0x710, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_bd_field_info), - trq_sel_fmap_bd_field_info -}, -{"TRQ_SEL_FMAP_BE", 0x714, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_be_field_info), - trq_sel_fmap_be_field_info -}, -{"TRQ_SEL_FMAP_BF", 0x718, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_bf_field_info), - trq_sel_fmap_bf_field_info -}, -{"TRQ_SEL_FMAP_C0", 0x71c, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_c0_field_info), - trq_sel_fmap_c0_field_info -}, -{"TRQ_SEL_FMAP_C1", 0x720, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_c1_field_info), - trq_sel_fmap_c1_field_info -}, -{"TRQ_SEL_FMAP_C2", 0x734, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_c2_field_info), - trq_sel_fmap_c2_field_info -}, -{"TRQ_SEL_FMAP_C3", 0x748, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_c3_field_info), - trq_sel_fmap_c3_field_info -}, -{"TRQ_SEL_FMAP_C4", 0x74c, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_c4_field_info), - trq_sel_fmap_c4_field_info -}, -{"TRQ_SEL_FMAP_C5", 0x750, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_c5_field_info), - trq_sel_fmap_c5_field_info -}, -{"TRQ_SEL_FMAP_C6", 0x754, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_c6_field_info), - trq_sel_fmap_c6_field_info -}, -{"TRQ_SEL_FMAP_C7", 0x758, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_c7_field_info), - trq_sel_fmap_c7_field_info -}, -{"TRQ_SEL_FMAP_C8", 0x75c, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_c8_field_info), - trq_sel_fmap_c8_field_info -}, -{"TRQ_SEL_FMAP_C9", 0x760, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_c9_field_info), - trq_sel_fmap_c9_field_info -}, -{"TRQ_SEL_FMAP_CA", 0x764, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_ca_field_info), - trq_sel_fmap_ca_field_info -}, -{"TRQ_SEL_FMAP_CB", 0x768, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_cb_field_info), - trq_sel_fmap_cb_field_info -}, -{"TRQ_SEL_FMAP_CC", 0x76c, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_cc_field_info), - trq_sel_fmap_cc_field_info -}, -{"TRQ_SEL_FMAP_CD", 0x770, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_cd_field_info), - trq_sel_fmap_cd_field_info -}, -{"TRQ_SEL_FMAP_CE", 0x774, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_ce_field_info), - trq_sel_fmap_ce_field_info -}, -{"TRQ_SEL_FMAP_CF", 0x778, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_cf_field_info), - trq_sel_fmap_cf_field_info -}, -{"TRQ_SEL_FMAP_D0", 0x77c, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_d0_field_info), - trq_sel_fmap_d0_field_info -}, -{"TRQ_SEL_FMAP_D1", 0x780, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_d1_field_info), - trq_sel_fmap_d1_field_info -}, -{"TRQ_SEL_FMAP_D2", 0x784, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_d2_field_info), - trq_sel_fmap_d2_field_info -}, -{"TRQ_SEL_FMAP_D3", 0x788, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_d3_field_info), - trq_sel_fmap_d3_field_info -}, -{"TRQ_SEL_FMAP_D4", 0x78c, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_d4_field_info), - trq_sel_fmap_d4_field_info -}, -{"TRQ_SEL_FMAP_D5", 0x790, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_d5_field_info), - trq_sel_fmap_d5_field_info -}, -{"TRQ_SEL_FMAP_D6", 0x794, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_d6_field_info), - trq_sel_fmap_d6_field_info -}, -{"TRQ_SEL_FMAP_D7", 0x798, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_d7_field_info), - trq_sel_fmap_d7_field_info -}, -{"TRQ_SEL_FMAP_D8", 0x79c, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_d8_field_info), - trq_sel_fmap_d8_field_info -}, -{"TRQ_SEL_FMAP_D9", 0x7a0, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_d9_field_info), - trq_sel_fmap_d9_field_info -}, -{"TRQ_SEL_FMAP_DA", 0x7a4, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_da_field_info), - trq_sel_fmap_da_field_info -}, -{"TRQ_SEL_FMAP_DB", 0x7a8, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_db_field_info), - trq_sel_fmap_db_field_info -}, -{"TRQ_SEL_FMAP_DC", 0x7ac, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_dc_field_info), - trq_sel_fmap_dc_field_info -}, -{"TRQ_SEL_FMAP_DD", 0x7b0, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_dd_field_info), - trq_sel_fmap_dd_field_info -}, -{"TRQ_SEL_FMAP_DE", 0x7b4, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_de_field_info), - trq_sel_fmap_de_field_info -}, -{"TRQ_SEL_FMAP_DF", 0x7b8, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_df_field_info), - trq_sel_fmap_df_field_info -}, -{"TRQ_SEL_FMAP_E0", 0x7bc, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_e0_field_info), - trq_sel_fmap_e0_field_info -}, -{"TRQ_SEL_FMAP_E1", 0x7c0, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_e1_field_info), - trq_sel_fmap_e1_field_info -}, -{"TRQ_SEL_FMAP_E2", 0x7c4, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_e2_field_info), - trq_sel_fmap_e2_field_info -}, -{"TRQ_SEL_FMAP_E3", 0x7c8, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_e3_field_info), - trq_sel_fmap_e3_field_info -}, -{"TRQ_SEL_FMAP_E4", 0x7cc, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_e4_field_info), - trq_sel_fmap_e4_field_info -}, -{"TRQ_SEL_FMAP_E5", 0x7d0, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_e5_field_info), - trq_sel_fmap_e5_field_info -}, -{"TRQ_SEL_FMAP_E6", 0x7d4, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_e6_field_info), - trq_sel_fmap_e6_field_info -}, -{"TRQ_SEL_FMAP_E7", 0x7d8, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_e7_field_info), - trq_sel_fmap_e7_field_info -}, -{"TRQ_SEL_FMAP_E8", 0x7dc, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_e8_field_info), - trq_sel_fmap_e8_field_info -}, -{"TRQ_SEL_FMAP_E9", 0x7e0, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_e9_field_info), - trq_sel_fmap_e9_field_info -}, -{"TRQ_SEL_FMAP_EA", 0x7e4, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_ea_field_info), - trq_sel_fmap_ea_field_info -}, -{"TRQ_SEL_FMAP_EB", 0x7e8, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_eb_field_info), - trq_sel_fmap_eb_field_info -}, -{"TRQ_SEL_FMAP_EC", 0x7ec, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_ec_field_info), - trq_sel_fmap_ec_field_info -}, -{"TRQ_SEL_FMAP_ED", 0x7f0, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_ed_field_info), - trq_sel_fmap_ed_field_info -}, -{"TRQ_SEL_FMAP_EE", 0x7f4, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_ee_field_info), - trq_sel_fmap_ee_field_info -}, -{"TRQ_SEL_FMAP_EF", 0x7f8, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_ef_field_info), - trq_sel_fmap_ef_field_info -}, -{"TRQ_SEL_FMAP_F0", 0x7fc, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_f0_field_info), - trq_sel_fmap_f0_field_info -}, -{"IND_CTXT_DATA_3", 0x804, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(ind_ctxt_data_3_field_info), - ind_ctxt_data_3_field_info -}, -{"IND_CTXT_DATA_2", 0x808, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(ind_ctxt_data_2_field_info), - ind_ctxt_data_2_field_info -}, -{"IND_CTXT_DATA_1", 0x80c, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(ind_ctxt_data_1_field_info), - ind_ctxt_data_1_field_info -}, -{"IND_CTXT_DATA_0", 0x810, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(ind_ctxt_data_0_field_info), - ind_ctxt_data_0_field_info -}, -{"IND_CTXT3", 0x814, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(ind_ctxt3_field_info), - ind_ctxt3_field_info -}, -{"IND_CTXT2", 0x818, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(ind_ctxt2_field_info), - ind_ctxt2_field_info -}, -{"IND_CTXT1", 0x81c, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(ind_ctxt1_field_info), - ind_ctxt1_field_info -}, -{"IND_CTXT0", 0x820, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(ind_ctxt0_field_info), - ind_ctxt0_field_info -}, -{"IND_CTXT_CMD", 0x824, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(ind_ctxt_cmd_field_info), - ind_ctxt_cmd_field_info -}, -{"C2H_TIMER_CNT_1", 0xa00, - 1, 0, 0, 0, - 0, QDMA_COMPLETION_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_timer_cnt_1_field_info), - c2h_timer_cnt_1_field_info -}, -{"C2H_TIMER_CNT_2", 0xa04, - 1, 0, 0, 0, - 0, QDMA_COMPLETION_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_timer_cnt_2_field_info), - c2h_timer_cnt_2_field_info -}, -{"C2H_TIMER_CNT_3", 0xa08, - 1, 0, 0, 0, - 0, QDMA_COMPLETION_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_timer_cnt_3_field_info), - c2h_timer_cnt_3_field_info -}, -{"C2H_TIMER_CNT_4", 0xa0c, - 1, 0, 0, 0, - 0, QDMA_COMPLETION_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_timer_cnt_4_field_info), - c2h_timer_cnt_4_field_info -}, -{"C2H_TIMER_CNT_5", 0xa10, - 1, 0, 0, 0, - 0, QDMA_COMPLETION_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_timer_cnt_5_field_info), - c2h_timer_cnt_5_field_info -}, -{"C2H_TIMER_CNT_6", 0xa14, - 1, 0, 0, 0, - 0, QDMA_COMPLETION_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_timer_cnt_6_field_info), - c2h_timer_cnt_6_field_info -}, -{"C2H_TIMER_CNT_7", 0xa18, - 1, 0, 0, 0, - 0, QDMA_COMPLETION_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_timer_cnt_7_field_info), - c2h_timer_cnt_7_field_info -}, -{"C2H_TIMER_CNT_8", 0xa1c, - 1, 0, 0, 0, - 0, QDMA_COMPLETION_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_timer_cnt_8_field_info), - c2h_timer_cnt_8_field_info -}, -{"C2H_TIMER_CNT_9", 0xa20, - 1, 0, 0, 0, - 0, QDMA_COMPLETION_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_timer_cnt_9_field_info), - c2h_timer_cnt_9_field_info -}, -{"C2H_TIMER_CNT_A", 0xa24, - 1, 0, 0, 0, - 0, QDMA_COMPLETION_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_timer_cnt_a_field_info), - c2h_timer_cnt_a_field_info -}, -{"C2H_TIMER_CNT_B", 0xa28, - 1, 0, 0, 0, - 0, QDMA_COMPLETION_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_timer_cnt_b_field_info), - c2h_timer_cnt_b_field_info -}, -{"C2H_TIMER_CNT_C", 0xa2c, - 1, 0, 0, 0, - 0, QDMA_COMPLETION_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_timer_cnt_c_field_info), - c2h_timer_cnt_c_field_info -}, -{"C2H_TIMER_CNT_D", 0xa30, - 1, 0, 0, 0, - 0, QDMA_COMPLETION_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_timer_cnt_d_field_info), - c2h_timer_cnt_d_field_info -}, -{"C2H_TIMER_CNT_E", 0xa34, - 1, 0, 0, 0, - 0, QDMA_COMPLETION_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_timer_cnt_e_field_info), - c2h_timer_cnt_e_field_info -}, -{"C2H_TIMER_CNT_F", 0xa38, - 1, 0, 0, 0, - 0, QDMA_COMPLETION_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_timer_cnt_f_field_info), - c2h_timer_cnt_f_field_info -}, -{"C2H_TIMER_CNT_10", 0xa3c, - 1, 0, 0, 0, - 0, QDMA_COMPLETION_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_timer_cnt_10_field_info), - c2h_timer_cnt_10_field_info -}, -{"C2H_CNT_TH_1", 0xa40, - 1, 0, 0, 0, - 0, QDMA_COMPLETION_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_cnt_th_1_field_info), - c2h_cnt_th_1_field_info -}, -{"C2H_CNT_TH_2", 0xa44, - 1, 0, 0, 0, - 0, QDMA_COMPLETION_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_cnt_th_2_field_info), - c2h_cnt_th_2_field_info -}, -{"C2H_CNT_TH_3", 0xa48, - 1, 0, 0, 0, - 0, QDMA_COMPLETION_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_cnt_th_3_field_info), - c2h_cnt_th_3_field_info -}, -{"C2H_CNT_TH_4", 0xa4c, - 1, 0, 0, 0, - 0, QDMA_COMPLETION_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_cnt_th_4_field_info), - c2h_cnt_th_4_field_info -}, -{"C2H_CNT_TH_5", 0xa50, - 1, 0, 0, 0, - 0, QDMA_COMPLETION_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_cnt_th_5_field_info), - c2h_cnt_th_5_field_info -}, -{"C2H_CNT_TH_6", 0xa54, - 1, 0, 0, 0, - 0, QDMA_COMPLETION_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_cnt_th_6_field_info), - c2h_cnt_th_6_field_info -}, -{"C2H_CNT_TH_7", 0xa58, - 1, 0, 0, 0, - 0, QDMA_COMPLETION_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_cnt_th_7_field_info), - c2h_cnt_th_7_field_info -}, -{"C2H_CNT_TH_8", 0xa5c, - 1, 0, 0, 0, - 0, QDMA_COMPLETION_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_cnt_th_8_field_info), - c2h_cnt_th_8_field_info -}, -{"C2H_CNT_TH_9", 0xa60, - 1, 0, 0, 0, - 0, QDMA_COMPLETION_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_cnt_th_9_field_info), - c2h_cnt_th_9_field_info -}, -{"C2H_CNT_TH_A", 0xa64, - 1, 0, 0, 0, - 0, QDMA_COMPLETION_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_cnt_th_a_field_info), - c2h_cnt_th_a_field_info -}, -{"C2H_CNT_TH_B", 0xa68, - 1, 0, 0, 0, - 0, QDMA_COMPLETION_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_cnt_th_b_field_info), - c2h_cnt_th_b_field_info -}, -{"C2H_CNT_TH_C", 0xa6c, - 1, 0, 0, 0, - 0, QDMA_COMPLETION_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_cnt_th_c_field_info), - c2h_cnt_th_c_field_info -}, -{"C2H_CNT_TH_D", 0xa70, - 1, 0, 0, 0, - 0, QDMA_COMPLETION_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_cnt_th_d_field_info), - c2h_cnt_th_d_field_info -}, -{"C2H_CNT_TH_E", 0xa74, - 1, 0, 0, 0, - 0, QDMA_COMPLETION_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_cnt_th_e_field_info), - c2h_cnt_th_e_field_info -}, -{"C2H_CNT_TH_F", 0xa78, - 1, 0, 0, 0, - 0, QDMA_COMPLETION_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_cnt_th_f_field_info), - c2h_cnt_th_f_field_info -}, -{"C2H_CNT_TH_10", 0xa7c, - 1, 0, 0, 0, - 0, QDMA_COMPLETION_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_cnt_th_10_field_info), - c2h_cnt_th_10_field_info -}, -{"C2H_QID2VEC_MAP_QID", 0xa80, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_qid2vec_map_qid_field_info), - c2h_qid2vec_map_qid_field_info -}, -{"C2H_QID2VEC_MAP", 0xa84, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_qid2vec_map_field_info), - c2h_qid2vec_map_field_info -}, -{"C2H_STAT_S_AXIS_C2H_ACCEPTED", 0xa88, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(c2h_stat_s_axis_c2h_accepted_field_info), - c2h_stat_s_axis_c2h_accepted_field_info -}, -{"C2H_STAT_S_AXIS_WRB_ACCEPTED", 0xa8c, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(c2h_stat_s_axis_wrb_accepted_field_info), - c2h_stat_s_axis_wrb_accepted_field_info -}, -{"C2H_STAT_DESC_RSP_PKT_ACCEPTED", 0xa90, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(c2h_stat_desc_rsp_pkt_accepted_field_info), - c2h_stat_desc_rsp_pkt_accepted_field_info -}, -{"C2H_STAT_AXIS_PKG_CMP", 0xa94, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(c2h_stat_axis_pkg_cmp_field_info), - c2h_stat_axis_pkg_cmp_field_info -}, -{"C2H_STAT_DESC_RSP_ACCEPTED", 0xa98, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_stat_desc_rsp_accepted_field_info), - c2h_stat_desc_rsp_accepted_field_info -}, -{"C2H_STAT_DESC_RSP_CMP", 0xa9c, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_stat_desc_rsp_cmp_field_info), - c2h_stat_desc_rsp_cmp_field_info -}, -{"C2H_STAT_WRQ_OUT", 0xaa0, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_stat_wrq_out_field_info), - c2h_stat_wrq_out_field_info -}, -{"C2H_STAT_WPL_REN_ACCEPTED", 0xaa4, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_stat_wpl_ren_accepted_field_info), - c2h_stat_wpl_ren_accepted_field_info -}, -{"C2H_STAT_TOTAL_WRQ_LEN", 0xaa8, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_stat_total_wrq_len_field_info), - c2h_stat_total_wrq_len_field_info -}, -{"C2H_STAT_TOTAL_WPL_LEN", 0xaac, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_stat_total_wpl_len_field_info), - c2h_stat_total_wpl_len_field_info -}, -{"C2H_BUF_SZ_0", 0xab0, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_buf_sz_0_field_info), - c2h_buf_sz_0_field_info -}, -{"C2H_BUF_SZ_1", 0xab4, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_buf_sz_1_field_info), - c2h_buf_sz_1_field_info -}, -{"C2H_BUF_SZ_2", 0xab8, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_buf_sz_2_field_info), - c2h_buf_sz_2_field_info -}, -{"C2H_BUF_SZ_3", 0xabc, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_buf_sz_3_field_info), - c2h_buf_sz_3_field_info -}, -{"C2H_BUF_SZ_4", 0xac0, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_buf_sz_4_field_info), - c2h_buf_sz_4_field_info -}, -{"C2H_BUF_SZ_5", 0xac4, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_buf_sz_5_field_info), - c2h_buf_sz_5_field_info -}, -{"C2H_BUF_SZ_7", 0xac8, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_buf_sz_7_field_info), - c2h_buf_sz_7_field_info -}, -{"C2H_BUF_SZ_8", 0xacc, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_buf_sz_8_field_info), - c2h_buf_sz_8_field_info -}, -{"C2H_BUF_SZ_9", 0xad0, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_buf_sz_9_field_info), - c2h_buf_sz_9_field_info -}, -{"C2H_BUF_SZ_10", 0xad4, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_buf_sz_10_field_info), - c2h_buf_sz_10_field_info -}, -{"C2H_BUF_SZ_11", 0xad8, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_buf_sz_11_field_info), - c2h_buf_sz_11_field_info -}, -{"C2H_BUF_SZ_12", 0xae0, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_buf_sz_12_field_info), - c2h_buf_sz_12_field_info -}, -{"C2H_BUF_SZ_13", 0xae4, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_buf_sz_13_field_info), - c2h_buf_sz_13_field_info -}, -{"C2H_BUF_SZ_14", 0xae8, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_buf_sz_14_field_info), - c2h_buf_sz_14_field_info -}, -{"C2H_BUF_SZ_15", 0xaec, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_buf_sz_15_field_info), - c2h_buf_sz_15_field_info -}, -{"C2H_ERR_STAT", 0xaf0, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(c2h_err_stat_field_info), - c2h_err_stat_field_info -}, -{"C2H_ERR_MASK", 0xaf4, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(c2h_err_mask_field_info), - c2h_err_mask_field_info -}, -{"C2H_FATAL_ERR_STAT", 0xaf8, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(c2h_fatal_err_stat_field_info), - c2h_fatal_err_stat_field_info -}, -{"C2H_FATAL_ERR_MASK", 0xafc, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(c2h_fatal_err_mask_field_info), - c2h_fatal_err_mask_field_info -}, -{"C2H_FATAL_ERR_ENABLE", 0xb00, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(c2h_fatal_err_enable_field_info), - c2h_fatal_err_enable_field_info -}, -{"GLBL_ERR_INT", 0xb04, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(glbl_err_int_field_info), - glbl_err_int_field_info -}, -{"C2H_PFCH_CFG", 0xb08, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_pfch_cfg_field_info), - c2h_pfch_cfg_field_info -}, -{"C2H_INT_TIMER_TICK", 0xb0c, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_int_timer_tick_field_info), - c2h_int_timer_tick_field_info -}, -{"C2H_STAT_DESC_RSP_DROP_ACCEPTED", 0xb10, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(c2h_stat_desc_rsp_drop_accepted_field_info), - c2h_stat_desc_rsp_drop_accepted_field_info -}, -{"C2H_STAT_DESC_RSP_ERR_ACCEPTED", 0xb14, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(c2h_stat_desc_rsp_err_accepted_field_info), - c2h_stat_desc_rsp_err_accepted_field_info -}, -{"C2H_STAT_DESC_REQ", 0xb18, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_stat_desc_req_field_info), - c2h_stat_desc_req_field_info -}, -{"C2H_STAT_DBG_DMA_ENG_0", 0xb1c, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_stat_dbg_dma_eng_0_field_info), - c2h_stat_dbg_dma_eng_0_field_info -}, -{"C2H_STAT_DBG_DMA_ENG_1", 0xb20, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_stat_dbg_dma_eng_1_field_info), - c2h_stat_dbg_dma_eng_1_field_info -}, -{"C2H_STAT_DBG_DMA_ENG_2", 0xb24, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_stat_dbg_dma_eng_2_field_info), - c2h_stat_dbg_dma_eng_2_field_info -}, -{"C2H_STAT_DBG_DMA_ENG_3", 0xb28, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_stat_dbg_dma_eng_3_field_info), - c2h_stat_dbg_dma_eng_3_field_info -}, -{"C2H_DBG_PFCH_ERR_CTXT", 0xb2c, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_dbg_pfch_err_ctxt_field_info), - c2h_dbg_pfch_err_ctxt_field_info -}, -{"C2H_FIRST_ERR_QID", 0xb30, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(c2h_first_err_qid_field_info), - c2h_first_err_qid_field_info -}, -{"STAT_NUM_WRB_IN", 0xb34, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(stat_num_wrb_in_field_info), - stat_num_wrb_in_field_info -}, -{"STAT_NUM_WRB_OUT", 0xb38, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(stat_num_wrb_out_field_info), - stat_num_wrb_out_field_info -}, -{"STAT_NUM_WRB_DRP", 0xb3c, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(stat_num_wrb_drp_field_info), - stat_num_wrb_drp_field_info -}, -{"STAT_NUM_STAT_DESC_OUT", 0xb40, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(stat_num_stat_desc_out_field_info), - stat_num_stat_desc_out_field_info -}, -{"STAT_NUM_DSC_CRDT_SENT", 0xb44, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(stat_num_dsc_crdt_sent_field_info), - stat_num_dsc_crdt_sent_field_info -}, -{"STAT_NUM_FCH_DSC_RCVD", 0xb48, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(stat_num_fch_dsc_rcvd_field_info), - stat_num_fch_dsc_rcvd_field_info -}, -{"STAT_NUM_BYP_DSC_RCVD", 0xb4c, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(stat_num_byp_dsc_rcvd_field_info), - stat_num_byp_dsc_rcvd_field_info -}, -{"C2H_WRB_COAL_CFG", 0xb50, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_wrb_coal_cfg_field_info), - c2h_wrb_coal_cfg_field_info -}, -{"C2H_INTR_H2C_REQ", 0xb54, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(c2h_intr_h2c_req_field_info), - c2h_intr_h2c_req_field_info -}, -{"C2H_INTR_C2H_MM_REQ", 0xb58, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(c2h_intr_c2h_mm_req_field_info), - c2h_intr_c2h_mm_req_field_info -}, -{"C2H_INTR_ERR_INT_REQ", 0xb5c, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(c2h_intr_err_int_req_field_info), - c2h_intr_err_int_req_field_info -}, -{"C2H_INTR_C2H_ST_REQ", 0xb60, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(c2h_intr_c2h_st_req_field_info), - c2h_intr_c2h_st_req_field_info -}, -{"C2H_INTR_H2C_ERR_C2H_MM_MSIX_ACK", 0xb64, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_intr_h2c_err_c2h_mm_msix_ack_field_info), - c2h_intr_h2c_err_c2h_mm_msix_ack_field_info -}, -{"C2H_INTR_H2C_ERR_C2H_MM_MSIX_FAIL", 0xb68, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_intr_h2c_err_c2h_mm_msix_fail_field_info), - c2h_intr_h2c_err_c2h_mm_msix_fail_field_info -}, -{"C2H_INTR_H2C_ERR_C2H_MM_MSIX_NO_MSIX", 0xb6c, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_intr_h2c_err_c2h_mm_msix_no_msix_field_info), - c2h_intr_h2c_err_c2h_mm_msix_no_msix_field_info -}, -{"C2H_INTR_H2C_ERR_C2H_MM_CTXT_INVAL", 0xb70, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_intr_h2c_err_c2h_mm_ctxt_inval_field_info), - c2h_intr_h2c_err_c2h_mm_ctxt_inval_field_info -}, -{"C2H_INTR_C2H_ST_MSIX_ACK", 0xb74, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(c2h_intr_c2h_st_msix_ack_field_info), - c2h_intr_c2h_st_msix_ack_field_info -}, -{"C2H_INTR_C2H_ST_MSIX_FAIL", 0xb78, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(c2h_intr_c2h_st_msix_fail_field_info), - c2h_intr_c2h_st_msix_fail_field_info -}, -{"C2H_INTR_C2H_ST_NO_MSIX", 0xb7c, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_intr_c2h_st_no_msix_field_info), - c2h_intr_c2h_st_no_msix_field_info -}, -{"C2H_INTR_C2H_ST_CTXT_INVAL", 0xb80, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_intr_c2h_st_ctxt_inval_field_info), - c2h_intr_c2h_st_ctxt_inval_field_info -}, -{"C2H_STAT_WR_CMP", 0xb84, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_stat_wr_cmp_field_info), - c2h_stat_wr_cmp_field_info -}, -{"C2H_STAT_DBG_DMA_ENG_4", 0xb88, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_stat_dbg_dma_eng_4_field_info), - c2h_stat_dbg_dma_eng_4_field_info -}, -{"C2H_STAT_DBG_DMA_ENG_5", 0xb8c, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_stat_dbg_dma_eng_5_field_info), - c2h_stat_dbg_dma_eng_5_field_info -}, -{"C2H_DBG_PFCH_QID", 0xb90, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_dbg_pfch_qid_field_info), - c2h_dbg_pfch_qid_field_info -}, -{"C2H_DBG_PFCH", 0xb94, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_dbg_pfch_field_info), - c2h_dbg_pfch_field_info -}, -{"C2H_INT_DBG", 0xb98, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_int_dbg_field_info), - c2h_int_dbg_field_info -}, -{"C2H_STAT_IMM_ACCEPTED", 0xb9c, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_stat_imm_accepted_field_info), - c2h_stat_imm_accepted_field_info -}, -{"C2H_STAT_MARKER_ACCEPTED", 0xba0, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_stat_marker_accepted_field_info), - c2h_stat_marker_accepted_field_info -}, -{"C2H_STAT_DISABLE_CMP_ACCEPTED", 0xba4, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_stat_disable_cmp_accepted_field_info), - c2h_stat_disable_cmp_accepted_field_info -}, -{"C2H_PLD_FIFO_CRDT_CNT", 0xba8, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_pld_fifo_crdt_cnt_field_info), - c2h_pld_fifo_crdt_cnt_field_info -}, -{"H2C_ERR_STAT", 0xe00, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(h2c_err_stat_field_info), - h2c_err_stat_field_info -}, -{"H2C_ERR_MASK", 0xe04, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(h2c_err_mask_field_info), - h2c_err_mask_field_info -}, -{"H2C_FIRST_ERR_QID", 0xe08, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(h2c_first_err_qid_field_info), - h2c_first_err_qid_field_info -}, -{"H2C_DBG_REG0", 0xe0c, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(h2c_dbg_reg0_field_info), - h2c_dbg_reg0_field_info -}, -{"H2C_DBG_REG1", 0xe10, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(h2c_dbg_reg1_field_info), - h2c_dbg_reg1_field_info -}, -{"H2C_DBG_REG2", 0xe14, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(h2c_dbg_reg2_field_info), - h2c_dbg_reg2_field_info -}, -{"H2C_DBG_REG3", 0xe18, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(h2c_dbg_reg3_field_info), - h2c_dbg_reg3_field_info -}, -{"H2C_DBG_REG4", 0xe1c, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(h2c_dbg_reg4_field_info), - h2c_dbg_reg4_field_info -}, -{"H2C_FATAL_ERR_EN", 0xe20, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(h2c_fatal_err_en_field_info), - h2c_fatal_err_en_field_info -}, -{"C2H_CHANNEL_CTL", 0x1004, - 1, 0, 0, 0, - 0, QDMA_MM_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_channel_ctl_field_info), - c2h_channel_ctl_field_info -}, -{"C2H_CHANNEL_CTL_1", 0x1008, - 1, 0, 0, 0, - 0, QDMA_MM_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_channel_ctl_1_field_info), - c2h_channel_ctl_1_field_info -}, -{"C2H_MM_STATUS", 0x1040, - 1, 0, 0, 0, - 0, QDMA_MM_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_mm_status_field_info), - c2h_mm_status_field_info -}, -{"C2H_CHANNEL_CMPL_DESC_CNT", 0x1048, - 1, 0, 0, 0, - 0, QDMA_MM_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_channel_cmpl_desc_cnt_field_info), - c2h_channel_cmpl_desc_cnt_field_info -}, -{"C2H_MM_ERR_CODE_ENABLE_MASK", 0x1054, - 1, 0, 0, 0, - 0, QDMA_MM_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_mm_err_code_enable_mask_field_info), - c2h_mm_err_code_enable_mask_field_info -}, -{"C2H_MM_ERR_CODE", 0x1058, - 1, 0, 0, 0, - 0, QDMA_MM_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_mm_err_code_field_info), - c2h_mm_err_code_field_info -}, -{"C2H_MM_ERR_INFO", 0x105c, - 1, 0, 0, 0, - 0, QDMA_MM_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_mm_err_info_field_info), - c2h_mm_err_info_field_info -}, -{"C2H_MM_PERF_MON_CTL", 0x10c0, - 1, 0, 0, 0, - 0, QDMA_MM_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_mm_perf_mon_ctl_field_info), - c2h_mm_perf_mon_ctl_field_info -}, -{"C2H_MM_PERF_MON_CYCLE_CNT0", 0x10c4, - 1, 0, 0, 0, - 0, QDMA_MM_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_mm_perf_mon_cycle_cnt0_field_info), - c2h_mm_perf_mon_cycle_cnt0_field_info -}, -{"C2H_MM_PERF_MON_CYCLE_CNT1", 0x10c8, - 1, 0, 0, 0, - 0, QDMA_MM_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_mm_perf_mon_cycle_cnt1_field_info), - c2h_mm_perf_mon_cycle_cnt1_field_info -}, -{"C2H_MM_PERF_MON_DATA_CNT0", 0x10cc, - 1, 0, 0, 0, - 0, QDMA_MM_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_mm_perf_mon_data_cnt0_field_info), - c2h_mm_perf_mon_data_cnt0_field_info -}, -{"C2H_MM_PERF_MON_DATA_CNT1", 0x10d0, - 1, 0, 0, 0, - 0, QDMA_MM_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_mm_perf_mon_data_cnt1_field_info), - c2h_mm_perf_mon_data_cnt1_field_info -}, -{"C2H_MM_DBG", 0x10e8, - 1, 0, 0, 0, - 0, QDMA_MM_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_mm_dbg_field_info), - c2h_mm_dbg_field_info -}, -{"H2C_CHANNEL_CTL", 0x1204, - 1, 0, 0, 0, - 0, QDMA_MM_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(h2c_channel_ctl_field_info), - h2c_channel_ctl_field_info -}, -{"H2C_CHANNEL_CTL_1", 0x1208, - 1, 0, 0, 0, - 0, QDMA_MM_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(h2c_channel_ctl_1_field_info), - h2c_channel_ctl_1_field_info -}, -{"H2C_CHANNEL_CTL_2", 0x120c, - 1, 0, 0, 0, - 0, QDMA_MM_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(h2c_channel_ctl_2_field_info), - h2c_channel_ctl_2_field_info -}, -{"H2C_MM_STATUS", 0x1240, - 1, 0, 0, 0, - 0, QDMA_MM_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(h2c_mm_status_field_info), - h2c_mm_status_field_info -}, -{"H2C_CHANNEL_CMPL_DESC_CNT", 0x1248, - 1, 0, 0, 0, - 0, QDMA_MM_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(h2c_channel_cmpl_desc_cnt_field_info), - h2c_channel_cmpl_desc_cnt_field_info -}, -{"H2C_MM_ERR_CODE_ENABLE_MASK", 0x1254, - 1, 0, 0, 0, - 0, QDMA_MM_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(h2c_mm_err_code_enable_mask_field_info), - h2c_mm_err_code_enable_mask_field_info -}, -{"H2C_MM_ERR_CODE", 0x1258, - 1, 0, 0, 0, - 0, QDMA_MM_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(h2c_mm_err_code_field_info), - h2c_mm_err_code_field_info -}, -{"H2C_MM_ERR_INFO", 0x125c, - 1, 0, 0, 0, - 0, QDMA_MM_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(h2c_mm_err_info_field_info), - h2c_mm_err_info_field_info -}, -{"H2C_MM_PERF_MON_CTL", 0x12c0, - 1, 0, 0, 0, - 0, QDMA_MM_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(h2c_mm_perf_mon_ctl_field_info), - h2c_mm_perf_mon_ctl_field_info -}, -{"H2C_MM_PERF_MON_CYCLE_CNT0", 0x12c4, - 1, 0, 0, 0, - 0, QDMA_MM_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(h2c_mm_perf_mon_cycle_cnt0_field_info), - h2c_mm_perf_mon_cycle_cnt0_field_info -}, -{"H2C_MM_PERF_MON_CYCLE_CNT1", 0x12c8, - 1, 0, 0, 0, - 0, QDMA_MM_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(h2c_mm_perf_mon_cycle_cnt1_field_info), - h2c_mm_perf_mon_cycle_cnt1_field_info -}, -{"H2C_MM_PERF_MON_DATA_CNT0", 0x12cc, - 1, 0, 0, 0, - 0, QDMA_MM_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(h2c_mm_perf_mon_data_cnt0_field_info), - h2c_mm_perf_mon_data_cnt0_field_info -}, -{"H2C_MM_PERF_MON_DATA_CNT1", 0x12d0, - 1, 0, 0, 0, - 0, QDMA_MM_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(h2c_mm_perf_mon_data_cnt1_field_info), - h2c_mm_perf_mon_data_cnt1_field_info -}, -{"H2C_MM_DBG", 0x12e8, - 1, 0, 0, 0, - 0, QDMA_MM_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(h2c_mm_dbg_field_info), - h2c_mm_dbg_field_info -}, -{"FUNC_STATUS_REG", 0x2400, - 1, 0, 0, 0, - 0, QDMA_MAILBOX, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(func_status_reg_field_info), - func_status_reg_field_info -}, -{"FUNC_CMD_REG", 0x2404, - 1, 0, 0, 0, - 0, QDMA_MAILBOX, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(func_cmd_reg_field_info), - func_cmd_reg_field_info -}, -{"FUNC_INTERRUPT_VECTOR_REG", 0x2408, - 1, 0, 0, 0, - 0, QDMA_MAILBOX, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(func_interrupt_vector_reg_field_info), - func_interrupt_vector_reg_field_info -}, -{"TARGET_FUNC_REG", 0x240c, - 1, 0, 0, 0, - 0, QDMA_MAILBOX, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(target_func_reg_field_info), - target_func_reg_field_info -}, -{"FUNC_INTERRUPT_CTL_REG", 0x2410, - 1, 0, 0, 0, - 0, QDMA_MAILBOX, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(func_interrupt_ctl_reg_field_info), - func_interrupt_ctl_reg_field_info -}, - -}; - -uint32_t qdma_cpm4_config_num_regs_get(void) -{ - return (sizeof(qdma_cpm4_config_regs)/ - sizeof(qdma_cpm4_config_regs[0])); -} - -struct xreg_info *qdma_cpm4_config_regs_get(void) -{ - return qdma_cpm4_config_regs; -} - diff --git a/QDMA/linux-kernel/driver/libqdma/qdma_access/qdma_list.c b/QDMA/linux-kernel/driver/libqdma/qdma_access/qdma_list.c deleted file mode 100755 index b7fabf75a..000000000 --- a/QDMA/linux-kernel/driver/libqdma/qdma_access/qdma_list.c +++ /dev/null @@ -1,62 +0,0 @@ -/* - * Copyright (c) 2019-2022, Xilinx, Inc. All rights reserved. - * Copyright (c) 2022, Advanced Micro Devices, Inc. All rights reserved. - * - * This source code is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * The full GNU General Public License is included in this distribution in - * the file called "COPYING". - */ - -#include "qdma_list.h" - -void qdma_list_init_head(struct qdma_list_head *head) -{ - if (head) - head->prev = head->next = head; -} - -void qdma_list_add_tail(struct qdma_list_head *node, - struct qdma_list_head *head) -{ - head->prev->next = node; - node->next = head; - node->prev = head->prev; - head->prev = node; -} - -void qdma_list_insert_before(struct qdma_list_head *new_node, - struct qdma_list_head *node) -{ - node->prev->next = new_node; - new_node->prev = node->prev; - new_node->next = node; - node->prev = new_node; -} - -void qdma_list_insert_after(struct qdma_list_head *new_node, - struct qdma_list_head *node) -{ - new_node->prev = node; - new_node->next = node->next; - node->next->prev = new_node; - node->next = new_node; -} - - -void qdma_list_del(struct qdma_list_head *node) -{ - if (node) { - if (node->prev) - node->prev->next = node->next; - if (node->next) - node->next->prev = node->prev; - } -} diff --git a/QDMA/linux-kernel/driver/libqdma/qdma_access/qdma_list.h b/QDMA/linux-kernel/driver/libqdma/qdma_access/qdma_list.h deleted file mode 100755 index dd5f7d4bd..000000000 --- a/QDMA/linux-kernel/driver/libqdma/qdma_access/qdma_list.h +++ /dev/null @@ -1,126 +0,0 @@ -/* - * Copyright (c) 2019-2022, Xilinx, Inc. All rights reserved. - * Copyright (c) 2022, Advanced Micro Devices, Inc. All rights reserved. - * - * This source code is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * The full GNU General Public License is included in this distribution in - * the file called "COPYING". - */ - -#ifndef __QDMA_LIST_H_ -#define __QDMA_LIST_H_ - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * DOC: QDMA common library provided list implementation definitions - * - * Header file *qdma_list.h* defines APIs for creating and managing list. - */ - -/** - * struct qdma_list_head - data type for creating a list node - */ -struct qdma_list_head { - struct qdma_list_head *prev; - struct qdma_list_head *next; - void *priv; -}; - -#define QDMA_LIST_HEAD_INIT(name) { &(name), &(name), NULL } - -#define QDMA_LIST_HEAD(name) \ - struct qdma_list_head name = QDMA_LIST_HEAD_INIT(name) - -#define QDMA_LIST_GET_DATA(node) (node->priv) -#define QDMA_LIST_SET_DATA(node, data) ((node)->priv = data) - - -#define qdma_list_for_each_safe(pos, n, head) \ - for (pos = (head)->next, n = pos->next; pos != (head); \ - pos = n, n = pos->next) - - -#define qdma_list_is_last_entry(entry, head) ((entry)->next == (head)) - -#define qdma_list_is_empty(head) ((head)->next == (head)) - -/*****************************************************************************/ -/** - * qdma_list_init_head(): Init the list head - * - * @head: head of the list - * - * Return: None - *****************************************************************************/ -void qdma_list_init_head(struct qdma_list_head *head); - -/*****************************************************************************/ -/** - * qdma_list_add_tail(): add the given @node at the end of the list with @head - * - * @node: new entry which has to be added at the end of the list with @head - * @head: head of the list - * - * This API needs to be called with holding the lock to the list - * - * Return: None - *****************************************************************************/ -void qdma_list_add_tail(struct qdma_list_head *node, - struct qdma_list_head *head); - -/*****************************************************************************/ -/** - * qdma_list_insert_before(): add the given @node at the before a @node - * - * @new_node: new entry which has to be added before @node - * @node: reference node in the list - * - * This API needs to be called with holding the lock to the list - * - * Return: None - *****************************************************************************/ -void qdma_list_insert_before(struct qdma_list_head *new_node, - struct qdma_list_head *node); - -/*****************************************************************************/ -/** - * qdma_list_insert_after(): add the given @node at the after a @node - * - * @new_node: new entry which has to be added after @node - * @node: reference node in the list - * - * This API needs to be called with holding the lock to the list - * - * Return: None - *****************************************************************************/ -void qdma_list_insert_after(struct qdma_list_head *new_node, - struct qdma_list_head *node); - -/*****************************************************************************/ -/** - * qdma_list_del(): delete an node from the list - * - * @node: node in a list - * - * This API needs to be called with holding the lock to the list - * - * Return: None - *****************************************************************************/ -void qdma_list_del(struct qdma_list_head *node); - -#ifdef __cplusplus -} -#endif - -#endif /* __QDMA_LIST_H_ */ diff --git a/QDMA/linux-kernel/driver/libqdma/qdma_access/qdma_mbox_protocol.c b/QDMA/linux-kernel/driver/libqdma/qdma_access/qdma_mbox_protocol.c deleted file mode 100755 index 67e7268cb..000000000 --- a/QDMA/linux-kernel/driver/libqdma/qdma_access/qdma_mbox_protocol.c +++ /dev/null @@ -1,2140 +0,0 @@ -/* - * Copyright (c) 2019-2022, Xilinx, Inc. All rights reserved. - * Copyright (c) 2022, Advanced Micro Devices, Inc. All rights reserved. - * - * This source code is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * The full GNU General Public License is included in this distribution in - * the file called "COPYING". - */ - -#include "qdma_mbox_protocol.h" - -/** mailbox function status */ -#define MBOX_FN_STATUS 0x0 -/** shift value for mailbox function status in msg */ -#define S_MBOX_FN_STATUS_IN_MSG 0 -/** mask value for mailbox function status in msg*/ -#define M_MBOX_FN_STATUS_IN_MSG 0x1 -/** face value for mailbox function status in msg */ -#define F_MBOX_FN_STATUS_IN_MSG 0x1 - -/** shift value for out msg */ -#define S_MBOX_FN_STATUS_OUT_MSG 1 -/** mask value for out msg */ -#define M_MBOX_FN_STATUS_OUT_MSG 0x1 -/** face value for out msg */ -#define F_MBOX_FN_STATUS_OUT_MSG (1 << S_MBOX_FN_STATUS_OUT_MSG) -/** shift value for status ack */ -#define S_MBOX_FN_STATUS_ACK 2 /* PF only, ack status */ -/** mask value for status ack */ -#define M_MBOX_FN_STATUS_ACK 0x1 -/** face value for status ack */ -#define F_MBOX_FN_STATUS_ACK (1 << S_MBOX_FN_STATUS_ACK) -/** shift value for status src */ -#define S_MBOX_FN_STATUS_SRC 4 /* PF only, source func.*/ -/** mask value for status src */ -#define M_MBOX_FN_STATUS_SRC 0xFFF -/** face value for status src */ -#define G_MBOX_FN_STATUS_SRC(x) \ - (((x) >> S_MBOX_FN_STATUS_SRC) & M_MBOX_FN_STATUS_SRC) -/** face value for mailbox function status */ -#define MBOX_FN_STATUS_MASK \ - (F_MBOX_FN_STATUS_IN_MSG | \ - F_MBOX_FN_STATUS_OUT_MSG | \ - F_MBOX_FN_STATUS_ACK) - -/** mailbox function commands register */ -#define MBOX_FN_CMD 0x4 -/** shift value for send command */ -#define S_MBOX_FN_CMD_SND 0 -/** mask value for send command */ -#define M_MBOX_FN_CMD_SND 0x1 -/** face value for send command */ -#define F_MBOX_FN_CMD_SND (1 << S_MBOX_FN_CMD_SND) -/** shift value for receive command */ -#define S_MBOX_FN_CMD_RCV 1 -/** mask value for receive command */ -#define M_MBOX_FN_CMD_RCV 0x1 -/** face value for receive command */ -#define F_MBOX_FN_CMD_RCV (1 << S_MBOX_FN_CMD_RCV) -/** shift value for vf reset */ -#define S_MBOX_FN_CMD_VF_RESET 3 /* TBD PF only: reset VF */ -/** mask value for vf reset */ -#define M_MBOX_FN_CMD_VF_RESET 0x1 -/** mailbox isr vector register */ -#define MBOX_ISR_VEC 0x8 -/** shift value for isr vector */ -#define S_MBOX_ISR_VEC 0 -/** mask value for isr vector */ -#define M_MBOX_ISR_VEC 0x1F -/** face value for isr vector */ -#define V_MBOX_ISR_VEC(x) ((x) & M_MBOX_ISR_VEC) -/** mailbox FN target register */ -#define MBOX_FN_TARGET 0xC -/** shift value for FN target id */ -#define S_MBOX_FN_TARGET_ID 0 -/** mask value for FN target id */ -#define M_MBOX_FN_TARGET_ID 0xFFF -/** face value for FN target id */ -#define V_MBOX_FN_TARGET_ID(x) ((x) & M_MBOX_FN_TARGET_ID) -/** mailbox isr enable register */ -#define MBOX_ISR_EN 0x10 -/** shift value for isr enable */ -#define S_MBOX_ISR_EN 0 -/** mask value for isr enable */ -#define M_MBOX_ISR_EN 0x1 -/** face value for isr enable */ -#define F_MBOX_ISR_EN 0x1 -/** pf acknowledge base */ -#define MBOX_PF_ACK_BASE 0x20 -/** pf acknowledge step */ -#define MBOX_PF_ACK_STEP 4 -/** pf acknowledge count */ -#define MBOX_PF_ACK_COUNT 8 -/** mailbox incoming msg base */ -#define MBOX_IN_MSG_BASE 0x800 -/** mailbox outgoing msg base */ -#define MBOX_OUT_MSG_BASE 0xc00 -/** mailbox msg step */ -#define MBOX_MSG_STEP 4 -/** mailbox register max */ -#define MBOX_MSG_REG_MAX 32 - -/** - * enum mbox_msg_op - mailbox messages opcode - */ -#define MBOX_MSG_OP_RSP_OFFSET 0x80 -enum mbox_msg_op { - /** @MBOX_OP_BYE: vf offline, response not required*/ - MBOX_OP_VF_BYE, - /** @MBOX_OP_HELLO: vf online */ - MBOX_OP_HELLO, - /** @: FMAP programming request */ - MBOX_OP_FMAP, - /** @MBOX_OP_CSR: global CSR registers request */ - MBOX_OP_CSR, - /** @MBOX_OP_QREQ: request queues */ - MBOX_OP_QREQ, - /** @MBOX_OP_QADD: notify of queue addition */ - MBOX_OP_QNOTIFY_ADD, - /** @MBOX_OP_QNOTIFY_DEL: notify of queue deletion */ - MBOX_OP_QNOTIFY_DEL, - /** @MBOX_OP_QACTIVE_CNT: get active q count */ - MBOX_OP_GET_QACTIVE_CNT, - /** @MBOX_OP_QCTXT_WRT: queue context write */ - MBOX_OP_QCTXT_WRT, - /** @MBOX_OP_QCTXT_RD: queue context read */ - MBOX_OP_QCTXT_RD, - /** @MBOX_OP_QCTXT_CLR: queue context clear */ - MBOX_OP_QCTXT_CLR, - /** @MBOX_OP_QCTXT_INV: queue context invalidate */ - MBOX_OP_QCTXT_INV, - /** @MBOX_OP_INTR_CTXT_WRT: interrupt context write */ - MBOX_OP_INTR_CTXT_WRT, - /** @MBOX_OP_INTR_CTXT_RD: interrupt context read */ - MBOX_OP_INTR_CTXT_RD, - /** @MBOX_OP_INTR_CTXT_CLR: interrupt context clear */ - MBOX_OP_INTR_CTXT_CLR, - /** @MBOX_OP_INTR_CTXT_INV: interrupt context invalidate */ - MBOX_OP_INTR_CTXT_INV, - /** @MBOX_OP_RESET_PREPARE: PF to VF message for VF reset*/ - MBOX_OP_RESET_PREPARE, - /** @MBOX_OP_RESET_DONE: PF reset done */ - MBOX_OP_RESET_DONE, - /** @MBOX_OP_REG_LIST_READ: Read the register list */ - MBOX_OP_REG_LIST_READ, - /** @MBOX_OP_PF_BYE: pf offline, response required */ - MBOX_OP_PF_BYE, - /** @MBOX_OP_PF_RESET_VF_BYE: VF reset BYE, response required*/ - MBOX_OP_PF_RESET_VF_BYE, - - /** @MBOX_OP_HELLO_RESP: response to @MBOX_OP_HELLO */ - MBOX_OP_HELLO_RESP = 0x81, - /** @MBOX_OP_FMAP_RESP: response to @MBOX_OP_FMAP */ - MBOX_OP_FMAP_RESP, - /** @MBOX_OP_CSR_RESP: response to @MBOX_OP_CSR */ - MBOX_OP_CSR_RESP, - /** @MBOX_OP_QREQ_RESP: response to @MBOX_OP_QREQ */ - MBOX_OP_QREQ_RESP, - /** @MBOX_OP_QADD: notify of queue addition */ - MBOX_OP_QNOTIFY_ADD_RESP, - /** @MBOX_OP_QNOTIFY_DEL: notify of queue deletion */ - MBOX_OP_QNOTIFY_DEL_RESP, - /** @MBOX_OP_QACTIVE_CNT_RESP: get active q count */ - MBOX_OP_GET_QACTIVE_CNT_RESP, - /** @MBOX_OP_QCTXT_WRT_RESP: response to @MBOX_OP_QCTXT_WRT */ - MBOX_OP_QCTXT_WRT_RESP, - /** @MBOX_OP_QCTXT_RD_RESP: response to @MBOX_OP_QCTXT_RD */ - MBOX_OP_QCTXT_RD_RESP, - /** @MBOX_OP_QCTXT_CLR_RESP: response to @MBOX_OP_QCTXT_CLR */ - MBOX_OP_QCTXT_CLR_RESP, - /** @MBOX_OP_QCTXT_INV_RESP: response to @MBOX_OP_QCTXT_INV */ - MBOX_OP_QCTXT_INV_RESP, - /** @MBOX_OP_INTR_CTXT_WRT_RESP: response to @MBOX_OP_INTR_CTXT_WRT */ - MBOX_OP_INTR_CTXT_WRT_RESP, - /** @MBOX_OP_INTR_CTXT_RD_RESP: response to @MBOX_OP_INTR_CTXT_RD */ - MBOX_OP_INTR_CTXT_RD_RESP, - /** @MBOX_OP_INTR_CTXT_CLR_RESP: response to @MBOX_OP_INTR_CTXT_CLR */ - MBOX_OP_INTR_CTXT_CLR_RESP, - /** @MBOX_OP_INTR_CTXT_INV_RESP: response to @MBOX_OP_INTR_CTXT_INV */ - MBOX_OP_INTR_CTXT_INV_RESP, - /** @MBOX_OP_RESET_PREPARE_RESP: response to @MBOX_OP_RESET_PREPARE */ - MBOX_OP_RESET_PREPARE_RESP, - /** @MBOX_OP_RESET_DONE_RESP: response to @MBOX_OP_PF_VF_RESET */ - MBOX_OP_RESET_DONE_RESP, - /** @MBOX_OP_REG_LIST_READ_RESP: response to @MBOX_OP_REG_LIST_READ */ - MBOX_OP_REG_LIST_READ_RESP, - /** @MBOX_OP_PF_BYE_RESP: response to @MBOX_OP_PF_BYE */ - MBOX_OP_PF_BYE_RESP, - /** @MBOX_OP_PF_RESET_VF_BYE_RESP: - * response to @MBOX_OP_PF_RESET_VF_BYE - */ - MBOX_OP_PF_RESET_VF_BYE_RESP, - /** @MBOX_OP_MAX: total mbox opcodes*/ - MBOX_OP_MAX -}; - -/** - * struct mbox_msg_hdr - mailbox message header - */ -struct mbox_msg_hdr { - /** @op: opcode */ - uint8_t op; - /** @status: execution status */ - char status; - /** @src_func_id: src function */ - uint16_t src_func_id; - /** @dst_func_id: dst function */ - uint16_t dst_func_id; -}; - -/** - * struct mbox_msg_fmap - FMAP programming command - */ -struct mbox_msg_hello { - /** @hdr: mailbox message header */ - struct mbox_msg_hdr hdr; - /** @qbase: start queue number in the queue range */ - uint32_t qbase; - /** @qmax: max queue number in the queue range(0-2k) */ - uint32_t qmax; - /** @dev_cap: device capability */ - struct qdma_dev_attributes dev_cap; - /** @dma_device_index: dma_device_index */ - uint32_t dma_device_index; -}; - -/** - * struct mbox_msg_active_qcnt - get active queue count command - */ -struct mbox_msg_active_qcnt { - /** @hdr: mailbox message header */ - struct mbox_msg_hdr hdr; - /** @h2c_queues: number of h2c queues */ - uint32_t h2c_queues; - /** @c2h_queues: number of c2h queues */ - uint32_t c2h_queues; - /** @cmpt_queues: number of cmpt queues */ - uint32_t cmpt_queues; -}; - -/** - * struct mbox_msg_fmap - FMAP programming command - */ -struct mbox_msg_fmap { - /** @hdr: mailbox message header */ - struct mbox_msg_hdr hdr; - /** @qbase: start queue number in the queue range */ - int qbase; - /** @qmax: max queue number in the queue range(0-2k) */ - uint32_t qmax; -}; - -/** - * struct mbox_msg_csr - mailbox csr reading message - */ -struct mbox_msg_csr { - /** @hdr - mailbox message header */ - struct mbox_msg_hdr hdr; - /** @csr_info: csr info data strucutre */ - struct qdma_csr_info csr_info; -}; - -/** - * struct mbox_msg_q_nitfy - queue add/del notify message - */ -struct mbox_msg_q_nitfy { - /** @hdr - mailbox message header */ - struct mbox_msg_hdr hdr; - /** @qid_hw: queue ID */ - uint16_t qid_hw; - /** @q_type: type of q */ - enum qdma_dev_q_type q_type; -}; - -/** - * @struct - mbox_msg_qctxt - * @brief queue context mailbox message header - */ -struct mbox_msg_qctxt { - /** @hdr: mailbox message header*/ - struct mbox_msg_hdr hdr; - /** @qid_hw: queue ID */ - uint16_t qid_hw; - /** @st: streaming mode */ - uint8_t st:1; - /** @c2h: c2h direction */ - uint8_t c2h:1; - /** @cmpt_ctxt_type: completion context type */ - enum mbox_cmpt_ctxt_type cmpt_ctxt_type:2; - /** @rsvd: reserved */ - uint8_t rsvd:4; - /** union compiled_message - complete hw configuration */ - union { - /** @descq_conf: mailbox message for queue context write*/ - struct mbox_descq_conf descq_conf; - /** @descq_ctxt: mailbox message for queue context read*/ - struct qdma_descq_context descq_ctxt; - }; -}; - -/** - * @struct - mbox_intr_ctxt - * @brief queue context mailbox message header - */ -struct mbox_intr_ctxt { - /** @hdr: mailbox message header*/ - struct mbox_msg_hdr hdr; - /** interrupt context mailbox message */ - struct mbox_msg_intr_ctxt ctxt; -}; - -/** - * @struct - mbox_read_reg_list - * @brief read register mailbox message header - */ -struct mbox_read_reg_list { - /** @hdr: mailbox message header*/ - struct mbox_msg_hdr hdr; - /** @group_num: reg group to read */ - uint16_t group_num; - /** @num_regs: number of registers to read */ - uint16_t num_regs; - /** @reg_list: register list */ - struct qdma_reg_data reg_list[QDMA_MAX_REGISTER_DUMP]; -}; - -union qdma_mbox_txrx { - /** mailbox message header*/ - struct mbox_msg_hdr hdr; - /** hello mailbox message */ - struct mbox_msg_hello hello; - /** fmap mailbox message */ - struct mbox_msg_fmap fmap; - /** interrupt context mailbox message */ - struct mbox_intr_ctxt intr_ctxt; - /** queue context mailbox message*/ - struct mbox_msg_qctxt qctxt; - /** global csr mailbox message */ - struct mbox_msg_csr csr; - /** acive q count */ - struct mbox_msg_active_qcnt qcnt; - /** q add/del notify message */ - struct mbox_msg_q_nitfy q_notify; - /** reg list mailbox message */ - struct mbox_read_reg_list reg_read_list; - /** buffer to hold raw data between pf and vf */ - uint32_t raw[MBOX_MSG_REG_MAX]; -}; - - -static inline uint32_t get_mbox_offset(void *dev_hndl, uint8_t is_vf) -{ - uint32_t mbox_base; - struct qdma_hw_access *hw = NULL; - - qdma_get_hw_access(dev_hndl, &hw); - mbox_base = (is_vf) ? - hw->mbox_base_vf : hw->mbox_base_pf; - - return mbox_base; -} - -static inline void mbox_pf_hw_clear_func_ack(void *dev_hndl, uint16_t func_id) -{ - int idx = func_id / 32; /* bitmask, uint32_t reg */ - int bit = func_id % 32; - uint32_t mbox_base = get_mbox_offset(dev_hndl, 0); - - /* clear the function's ack status */ - qdma_reg_write(dev_hndl, - mbox_base + MBOX_PF_ACK_BASE + idx * MBOX_PF_ACK_STEP, - (1 << bit)); -} - -static void qdma_mbox_memcpy(void *to, void *from, uint8_t size) -{ - uint8_t i; - uint8_t *_to = (uint8_t *)to; - uint8_t *_from = (uint8_t *)from; - - for (i = 0; i < size; i++) - _to[i] = _from[i]; -} - -static void qdma_mbox_memset(void *to, uint8_t val, uint8_t size) -{ - uint8_t i; - uint8_t *_to = (uint8_t *)to; - - for (i = 0; i < size; i++) - _to[i] = val; -} - -static int get_ring_idx(void *dev_hndl, uint16_t ring_sz, uint16_t *rng_idx) -{ - uint32_t rng_sz[QDMA_GLOBAL_CSR_ARRAY_SZ] = { 0 }; - int i, rv; - struct qdma_hw_access *hw = NULL; - - qdma_get_hw_access(dev_hndl, &hw); - rv = hw->qdma_global_csr_conf(dev_hndl, 0, - QDMA_GLOBAL_CSR_ARRAY_SZ, rng_sz, - QDMA_CSR_RING_SZ, QDMA_HW_ACCESS_READ); - - if (rv) - return rv; - for (i = 0; i < QDMA_GLOBAL_CSR_ARRAY_SZ; i++) { - if (ring_sz == (rng_sz[i] - 1)) { - *rng_idx = i; - return QDMA_SUCCESS; - } - } - - qdma_log_error("%s: Ring size not found, err:%d\n", - __func__, -QDMA_ERR_MBOX_INV_RINGSZ); - return -QDMA_ERR_MBOX_INV_RINGSZ; -} - -static int get_buf_idx(void *dev_hndl, uint16_t buf_sz, uint16_t *buf_idx) -{ - uint32_t c2h_buf_sz[QDMA_GLOBAL_CSR_ARRAY_SZ] = { 0 }; - int i, rv; - struct qdma_hw_access *hw = NULL; - - qdma_get_hw_access(dev_hndl, &hw); - - rv = hw->qdma_global_csr_conf(dev_hndl, 0, - QDMA_GLOBAL_CSR_ARRAY_SZ, c2h_buf_sz, - QDMA_CSR_BUF_SZ, QDMA_HW_ACCESS_READ); - if (rv) - return rv; - for (i = 0; i < QDMA_GLOBAL_CSR_ARRAY_SZ; i++) { - if (c2h_buf_sz[i] == buf_sz) { - *buf_idx = i; - return QDMA_SUCCESS; - } - } - - qdma_log_error("%s: Buf index not found, err:%d\n", - __func__, -QDMA_ERR_MBOX_INV_BUFSZ); - return -QDMA_ERR_MBOX_INV_BUFSZ; -} - -static int get_cntr_idx(void *dev_hndl, uint8_t cntr_val, uint8_t *cntr_idx) -{ - uint32_t cntr_th[QDMA_GLOBAL_CSR_ARRAY_SZ] = { 0 }; - int i, rv; - struct qdma_hw_access *hw = NULL; - - qdma_get_hw_access(dev_hndl, &hw); - - rv = hw->qdma_global_csr_conf(dev_hndl, 0, - QDMA_GLOBAL_CSR_ARRAY_SZ, cntr_th, - QDMA_CSR_CNT_TH, QDMA_HW_ACCESS_READ); - - if (rv) - return rv; - for (i = 0; i < QDMA_GLOBAL_CSR_ARRAY_SZ; i++) { - if (cntr_th[i] == cntr_val) { - *cntr_idx = i; - return QDMA_SUCCESS; - } - } - - qdma_log_error("%s: Counter val not found, err:%d\n", - __func__, -QDMA_ERR_MBOX_INV_CNTR_TH); - return -QDMA_ERR_MBOX_INV_CNTR_TH; -} - -static int get_tmr_idx(void *dev_hndl, uint8_t tmr_val, uint8_t *tmr_idx) -{ - uint32_t tmr_th[QDMA_GLOBAL_CSR_ARRAY_SZ] = { 0 }; - int i, rv; - struct qdma_hw_access *hw = NULL; - - qdma_get_hw_access(dev_hndl, &hw); - - rv = hw->qdma_global_csr_conf(dev_hndl, 0, - QDMA_GLOBAL_CSR_ARRAY_SZ, tmr_th, - QDMA_CSR_TIMER_CNT, QDMA_HW_ACCESS_READ); - if (rv) - return rv; - for (i = 0; i < QDMA_GLOBAL_CSR_ARRAY_SZ; i++) { - if (tmr_th[i] == tmr_val) { - *tmr_idx = i; - return QDMA_SUCCESS; - } - } - - qdma_log_error("%s: Timer val not found, err:%d\n", - __func__, -QDMA_ERR_MBOX_INV_TMR_TH); - return -QDMA_ERR_MBOX_INV_TMR_TH; -} - -static int mbox_compose_sw_context(void *dev_hndl, - struct mbox_msg_qctxt *qctxt, - struct qdma_descq_sw_ctxt *sw_ctxt) -{ - uint16_t rng_idx = 0; - int rv = QDMA_SUCCESS; - - if (!qctxt || !sw_ctxt) { - qdma_log_error("%s: qctxt=%p sw_ctxt=%p, err:%d\n", - __func__, - qctxt, sw_ctxt, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - rv = get_ring_idx(dev_hndl, qctxt->descq_conf.ringsz, &rng_idx); - if (rv < 0) { - qdma_log_error("%s: failed to get ring index, err:%d\n", - __func__, rv); - return rv; - } - /* compose sw context */ - sw_ctxt->vec = qctxt->descq_conf.intr_id; - sw_ctxt->intr_aggr = qctxt->descq_conf.intr_aggr; - - sw_ctxt->ring_bs_addr = qctxt->descq_conf.ring_bs_addr; - sw_ctxt->wbi_chk = qctxt->descq_conf.wbi_chk; - sw_ctxt->wbi_intvl_en = qctxt->descq_conf.wbi_intvl_en; - sw_ctxt->rngsz_idx = rng_idx; - sw_ctxt->bypass = qctxt->descq_conf.en_bypass; - sw_ctxt->wbk_en = qctxt->descq_conf.wbk_en; - sw_ctxt->irq_en = qctxt->descq_conf.irq_en; - sw_ctxt->is_mm = ~qctxt->st; - sw_ctxt->mm_chn = 0; - sw_ctxt->qen = 1; - sw_ctxt->frcd_en = qctxt->descq_conf.forced_en; - - sw_ctxt->desc_sz = qctxt->descq_conf.desc_sz; - - /* pidx = 0; irq_ack = 0 */ - sw_ctxt->fnc_id = qctxt->descq_conf.func_id; - sw_ctxt->irq_arm = qctxt->descq_conf.irq_arm; - - if (qctxt->st && qctxt->c2h) { - sw_ctxt->irq_en = 0; - sw_ctxt->irq_arm = 0; - sw_ctxt->wbk_en = 0; - sw_ctxt->wbi_chk = 0; - } - - return QDMA_SUCCESS; -} - -static int mbox_compose_prefetch_context(void *dev_hndl, - struct mbox_msg_qctxt *qctxt, - struct qdma_descq_prefetch_ctxt *pfetch_ctxt) -{ - uint16_t buf_idx = 0; - int rv = QDMA_SUCCESS; - - if (!qctxt || !pfetch_ctxt) { - qdma_log_error("%s: qctxt=%p pfetch_ctxt=%p, err:%d\n", - __func__, - qctxt, - pfetch_ctxt, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - rv = get_buf_idx(dev_hndl, qctxt->descq_conf.bufsz, &buf_idx); - if (rv < 0) { - qdma_log_error("%s: failed to get buf index, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - return rv; - } - /* prefetch context */ - pfetch_ctxt->valid = 1; - pfetch_ctxt->bypass = qctxt->descq_conf.en_bypass_prefetch; - pfetch_ctxt->bufsz_idx = buf_idx; - pfetch_ctxt->pfch_en = qctxt->descq_conf.pfch_en; - - return QDMA_SUCCESS; -} - - -static int mbox_compose_cmpt_context(void *dev_hndl, - struct mbox_msg_qctxt *qctxt, - struct qdma_descq_cmpt_ctxt *cmpt_ctxt) -{ - uint16_t rng_idx = 0; - uint8_t cntr_idx = 0, tmr_idx = 0; - int rv = QDMA_SUCCESS; - - if (!qctxt || !cmpt_ctxt) { - qdma_log_error("%s: qctxt=%p cmpt_ctxt=%p, err:%d\n", - __func__, qctxt, cmpt_ctxt, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - rv = get_cntr_idx(dev_hndl, qctxt->descq_conf.cnt_thres, &cntr_idx); - if (rv < 0) - return rv; - rv = get_tmr_idx(dev_hndl, qctxt->descq_conf.timer_thres, &tmr_idx); - if (rv < 0) - return rv; - rv = get_ring_idx(dev_hndl, qctxt->descq_conf.cmpt_ringsz, &rng_idx); - if (rv < 0) - return rv; - /* writeback context */ - - cmpt_ctxt->bs_addr = qctxt->descq_conf.cmpt_ring_bs_addr; - cmpt_ctxt->en_stat_desc = qctxt->descq_conf.cmpl_stat_en; - cmpt_ctxt->en_int = qctxt->descq_conf.cmpt_int_en; - cmpt_ctxt->trig_mode = qctxt->descq_conf.triggermode; - cmpt_ctxt->fnc_id = qctxt->descq_conf.func_id; - cmpt_ctxt->timer_idx = tmr_idx; - cmpt_ctxt->counter_idx = cntr_idx; - cmpt_ctxt->color = 1; - cmpt_ctxt->ringsz_idx = rng_idx; - - cmpt_ctxt->desc_sz = qctxt->descq_conf.cmpt_desc_sz; - - cmpt_ctxt->valid = 1; - - cmpt_ctxt->ovf_chk_dis = qctxt->descq_conf.dis_overflow_check; - cmpt_ctxt->vec = qctxt->descq_conf.intr_id; - cmpt_ctxt->int_aggr = qctxt->descq_conf.intr_aggr; - - return QDMA_SUCCESS; -} - -static int mbox_clear_queue_contexts(void *dev_hndl, uint8_t dma_device_index, - uint16_t func_id, uint16_t qid_hw, uint8_t st, - uint8_t c2h, - enum mbox_cmpt_ctxt_type cmpt_ctxt_type) -{ - int rv; - int qbase; - uint32_t qmax; - enum qdma_dev_q_range q_range; - struct qdma_hw_access *hw = NULL; - - qdma_get_hw_access(dev_hndl, &hw); - - if (cmpt_ctxt_type == QDMA_MBOX_CMPT_CTXT_ONLY) { - rv = hw->qdma_cmpt_ctx_conf(dev_hndl, qid_hw, - NULL, QDMA_HW_ACCESS_CLEAR); - if (rv < 0) { - qdma_log_error("%s: clear cmpt ctxt, err:%d\n", - __func__, rv); - return rv; - } - } else { - rv = qdma_dev_qinfo_get(dma_device_index, - func_id, &qbase, &qmax); - if (rv < 0) { - qdma_log_error("%s: failed to get qinfo, err:%d\n", - __func__, rv); - return rv; - } - - q_range = qdma_dev_is_queue_in_range(dma_device_index, - func_id, qid_hw); - if (q_range != QDMA_DEV_Q_IN_RANGE) { - qdma_log_error("%s: q_range invalid, err:%d\n", - __func__, rv); - return rv; - } - - rv = hw->qdma_sw_ctx_conf(dev_hndl, c2h, qid_hw, - NULL, QDMA_HW_ACCESS_CLEAR); - if (rv < 0) { - qdma_log_error("%s: clear sw_ctxt, err:%d\n", - __func__, rv); - return rv; - } - - rv = hw->qdma_hw_ctx_conf(dev_hndl, c2h, qid_hw, NULL, - QDMA_HW_ACCESS_CLEAR); - if (rv < 0) { - qdma_log_error("%s: clear hw_ctxt, err:%d\n", - __func__, rv); - return rv; - } - - rv = hw->qdma_credit_ctx_conf(dev_hndl, c2h, qid_hw, NULL, - QDMA_HW_ACCESS_CLEAR); - if (rv < 0) { - qdma_log_error("%s: clear cr_ctxt, err:%d\n", - __func__, rv); - return rv; - } - - if (st && c2h) { - rv = hw->qdma_pfetch_ctx_conf(dev_hndl, qid_hw, - NULL, - QDMA_HW_ACCESS_CLEAR); - if (rv < 0) { - qdma_log_error("%s:clear pfetch ctxt, err:%d\n", - __func__, rv); - return rv; - } - } - - if ((cmpt_ctxt_type == QDMA_MBOX_CMPT_WITH_MM) || - (cmpt_ctxt_type == QDMA_MBOX_CMPT_WITH_ST)) { - rv = hw->qdma_cmpt_ctx_conf(dev_hndl, qid_hw, - NULL, - QDMA_HW_ACCESS_CLEAR); - if (rv < 0) { - qdma_log_error("%s: clear cmpt ctxt, err:%d\n", - __func__, rv); - return rv; - } - } - } - - return QDMA_SUCCESS; -} - -static int mbox_invalidate_queue_contexts(void *dev_hndl, - uint8_t dma_device_index, uint16_t func_id, - uint16_t qid_hw, uint8_t st, - uint8_t c2h, enum mbox_cmpt_ctxt_type cmpt_ctxt_type) -{ - int rv; - int qbase; - uint32_t qmax; - enum qdma_dev_q_range q_range; - struct qdma_hw_access *hw = NULL; - - qdma_get_hw_access(dev_hndl, &hw); - - if (cmpt_ctxt_type == QDMA_MBOX_CMPT_CTXT_ONLY) { - rv = hw->qdma_cmpt_ctx_conf(dev_hndl, qid_hw, NULL, - QDMA_HW_ACCESS_INVALIDATE); - if (rv < 0) { - qdma_log_error("%s: inv cmpt ctxt, err:%d\n", - __func__, rv); - return rv; - } - } else { - rv = qdma_dev_qinfo_get(dma_device_index, func_id, - &qbase, &qmax); - if (rv < 0) { - qdma_log_error("%s: failed to get qinfo, err:%d\n", - __func__, rv); - return rv; - } - - q_range = qdma_dev_is_queue_in_range(dma_device_index, - func_id, qid_hw); - if (q_range != QDMA_DEV_Q_IN_RANGE) { - qdma_log_error("%s: Invalid qrange, err:%d\n", - __func__, rv); - return rv; - } - - rv = hw->qdma_sw_ctx_conf(dev_hndl, c2h, qid_hw, - NULL, QDMA_HW_ACCESS_INVALIDATE); - if (rv < 0) { - qdma_log_error("%s: inv sw ctxt, err:%d\n", - __func__, rv); - return rv; - } - - rv = hw->qdma_hw_ctx_conf(dev_hndl, c2h, qid_hw, NULL, - QDMA_HW_ACCESS_INVALIDATE); - if (rv < 0) { - qdma_log_error("%s: clear hw_ctxt, err:%d\n", - __func__, rv); - return rv; - } - - rv = hw->qdma_credit_ctx_conf(dev_hndl, c2h, qid_hw, NULL, - QDMA_HW_ACCESS_INVALIDATE); - if (rv < 0) { - qdma_log_error("%s: clear cr_ctxt, err:%d\n", - __func__, rv); - return rv; - } - - if (st && c2h) { - rv = hw->qdma_pfetch_ctx_conf(dev_hndl, qid_hw, - NULL, - QDMA_HW_ACCESS_INVALIDATE); - if (rv < 0) { - qdma_log_error("%s: inv pfetch ctxt, err:%d\n", - __func__, rv); - return rv; - } - } - - if ((cmpt_ctxt_type == QDMA_MBOX_CMPT_WITH_MM) || - (cmpt_ctxt_type == QDMA_MBOX_CMPT_WITH_ST)) { - rv = hw->qdma_cmpt_ctx_conf(dev_hndl, qid_hw, - NULL, - QDMA_HW_ACCESS_INVALIDATE); - if (rv < 0) { - qdma_log_error("%s: inv cmpt ctxt, err:%d\n", - __func__, rv); - return rv; - } - } - } - - return QDMA_SUCCESS; -} - -static int mbox_write_queue_contexts(void *dev_hndl, uint8_t dma_device_index, - struct mbox_msg_qctxt *qctxt) -{ - int rv; - int qbase; - uint32_t qmax; - enum qdma_dev_q_range q_range; - struct qdma_descq_context descq_ctxt; - uint16_t qid_hw = qctxt->qid_hw; - struct qdma_hw_access *hw = NULL; - - qdma_get_hw_access(dev_hndl, &hw); - - rv = qdma_dev_qinfo_get(dma_device_index, qctxt->descq_conf.func_id, - &qbase, &qmax); - if (rv < 0) - return rv; - - q_range = qdma_dev_is_queue_in_range(dma_device_index, - qctxt->descq_conf.func_id, - qctxt->qid_hw); - if (q_range != QDMA_DEV_Q_IN_RANGE) { - qdma_log_error("%s: Invalid qrange, err:%d\n", - __func__, rv); - return rv; - } - - qdma_mbox_memset(&descq_ctxt, 0, sizeof(struct qdma_descq_context)); - - if (qctxt->cmpt_ctxt_type == QDMA_MBOX_CMPT_CTXT_ONLY) { - rv = mbox_compose_cmpt_context(dev_hndl, qctxt, - &descq_ctxt.cmpt_ctxt); - if (rv < 0) - return rv; - - rv = hw->qdma_cmpt_ctx_conf(dev_hndl, qid_hw, - NULL, QDMA_HW_ACCESS_CLEAR); - if (rv < 0) { - qdma_log_error("%s: clear cmpt ctxt, err:%d\n", - __func__, rv); - return rv; - } - - rv = hw->qdma_cmpt_ctx_conf(dev_hndl, qid_hw, - &descq_ctxt.cmpt_ctxt, QDMA_HW_ACCESS_WRITE); - if (rv < 0) { - qdma_log_error("%s: write cmpt ctxt, err:%d\n", - __func__, rv); - return rv; - } - - } else { - rv = mbox_compose_sw_context(dev_hndl, qctxt, - &descq_ctxt.sw_ctxt); - if (rv < 0) - return rv; - - if (qctxt->st && qctxt->c2h) { - rv = mbox_compose_prefetch_context(dev_hndl, qctxt, - &descq_ctxt.pfetch_ctxt); - if (rv < 0) - return rv; - } - - if ((qctxt->cmpt_ctxt_type == QDMA_MBOX_CMPT_WITH_MM) || - (qctxt->cmpt_ctxt_type == QDMA_MBOX_CMPT_WITH_ST)) { - rv = mbox_compose_cmpt_context(dev_hndl, qctxt, - &descq_ctxt.cmpt_ctxt); - if (rv < 0) - return rv; - } - - rv = mbox_clear_queue_contexts(dev_hndl, dma_device_index, - qctxt->descq_conf.func_id, - qctxt->qid_hw, - qctxt->st, - qctxt->c2h, - qctxt->cmpt_ctxt_type); - if (rv < 0) - return rv; - rv = hw->qdma_sw_ctx_conf(dev_hndl, qctxt->c2h, qid_hw, - &descq_ctxt.sw_ctxt, - QDMA_HW_ACCESS_WRITE); - if (rv < 0) { - qdma_log_error("%s: write sw ctxt, err:%d\n", - __func__, rv); - return rv; - } - - if (qctxt->st && qctxt->c2h) { - rv = hw->qdma_pfetch_ctx_conf(dev_hndl, qid_hw, - &descq_ctxt.pfetch_ctxt, - QDMA_HW_ACCESS_WRITE); - if (rv < 0) { - qdma_log_error("%s:write pfetch ctxt, err:%d\n", - __func__, rv); - return rv; - } - } - - if ((qctxt->cmpt_ctxt_type == QDMA_MBOX_CMPT_WITH_MM) || - (qctxt->cmpt_ctxt_type == QDMA_MBOX_CMPT_WITH_ST)) { - rv = hw->qdma_cmpt_ctx_conf(dev_hndl, qid_hw, - &descq_ctxt.cmpt_ctxt, - QDMA_HW_ACCESS_WRITE); - if (rv < 0) { - qdma_log_error("%s: write cmpt ctxt, err:%d\n", - __func__, rv); - return rv; - } - } - } - return QDMA_SUCCESS; -} - -static int mbox_read_queue_contexts(void *dev_hndl, uint16_t func_id, - uint16_t qid_hw, uint8_t st, uint8_t c2h, - enum mbox_cmpt_ctxt_type cmpt_ctxt_type, - struct qdma_descq_context *ctxt) -{ - int rv; - struct qdma_hw_access *hw = NULL; - - qdma_get_hw_access(dev_hndl, &hw); - - rv = hw->qdma_sw_ctx_conf(dev_hndl, c2h, qid_hw, &ctxt->sw_ctxt, - QDMA_HW_ACCESS_READ); - if (rv < 0) { - qdma_log_error("%s: read sw ctxt, err:%d\n", - __func__, rv); - return rv; - } - - rv = hw->qdma_hw_ctx_conf(dev_hndl, c2h, qid_hw, &ctxt->hw_ctxt, - QDMA_HW_ACCESS_READ); - if (rv < 0) { - qdma_log_error("%s: read hw ctxt, err:%d\n", - __func__, rv); - return rv; - } - - rv = hw->qdma_credit_ctx_conf(dev_hndl, c2h, qid_hw, &ctxt->cr_ctxt, - QDMA_HW_ACCESS_READ); - if (rv < 0) { - qdma_log_error("%s: read credit ctxt, err:%d\n", - __func__, rv); - return rv; - } - - rv = hw->qdma_fmap_conf(dev_hndl, func_id, &ctxt->fmap, - QDMA_HW_ACCESS_READ); - if (rv < 0) { - qdma_log_error("%s: read fmap ctxt, err:%d\n", - __func__, rv); - return rv; - } - - if (st && c2h) { - rv = hw->qdma_pfetch_ctx_conf(dev_hndl, - qid_hw, &ctxt->pfetch_ctxt, - QDMA_HW_ACCESS_READ); - if (rv < 0) { - qdma_log_error("%s: read pfetch ctxt, err:%d\n", - __func__, rv); - return rv; - } - } - - if ((cmpt_ctxt_type == QDMA_MBOX_CMPT_WITH_MM) || - (cmpt_ctxt_type == QDMA_MBOX_CMPT_WITH_ST)) { - rv = hw->qdma_cmpt_ctx_conf(dev_hndl, - qid_hw, &ctxt->cmpt_ctxt, - QDMA_HW_ACCESS_READ); - if (rv < 0) { - qdma_log_error("%s: read cmpt ctxt, err:%d\n", - __func__, rv); - return rv; - } - } - - return QDMA_SUCCESS; -} - -int qdma_mbox_pf_rcv_msg_handler(void *dev_hndl, uint8_t dma_device_index, - uint16_t func_id, uint32_t *rcv_msg, - uint32_t *resp_msg) -{ - union qdma_mbox_txrx *rcv = (union qdma_mbox_txrx *)rcv_msg; - union qdma_mbox_txrx *resp = (union qdma_mbox_txrx *)resp_msg; - struct mbox_msg_hdr *hdr = &rcv->hdr; - struct qdma_hw_access *hw = NULL; - int rv = QDMA_SUCCESS; - int ret = 0; - - if (!rcv) { - qdma_log_error("%s: rcv_msg=%p failure:%d\n", - __func__, rcv, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - qdma_get_hw_access(dev_hndl, &hw); - - switch (rcv->hdr.op) { - case MBOX_OP_VF_BYE: - { - struct qdma_fmap_cfg fmap; - - fmap.qbase = 0; - fmap.qmax = 0; - rv = hw->qdma_fmap_conf(dev_hndl, hdr->src_func_id, &fmap, - QDMA_HW_ACCESS_WRITE); - - qdma_dev_entry_destroy(dma_device_index, hdr->src_func_id); - - ret = QDMA_MBOX_VF_OFFLINE; - } - break; - case MBOX_OP_PF_RESET_VF_BYE: - { - struct qdma_fmap_cfg fmap; - - fmap.qbase = 0; - fmap.qmax = 0; - rv = hw->qdma_fmap_conf(dev_hndl, hdr->src_func_id, &fmap, - QDMA_HW_ACCESS_WRITE); - - qdma_dev_entry_destroy(dma_device_index, hdr->src_func_id); - - ret = QDMA_MBOX_VF_RESET_BYE; - } - break; - case MBOX_OP_HELLO: - { - struct mbox_msg_fmap *fmap = &rcv->fmap; - struct qdma_fmap_cfg fmap_cfg; - struct mbox_msg_hello *rsp_hello = &resp->hello; - - rv = qdma_dev_qinfo_get(dma_device_index, hdr->src_func_id, - &fmap->qbase, &fmap->qmax); - if (rv < 0) - rv = qdma_dev_entry_create(dma_device_index, - hdr->src_func_id); - - if (!rv) { - rsp_hello->qbase = fmap->qbase; - rsp_hello->qmax = fmap->qmax; - rsp_hello->dma_device_index = dma_device_index; - hw->qdma_get_device_attributes(dev_hndl, - &rsp_hello->dev_cap); - } - qdma_mbox_memset(&fmap_cfg, 0, - sizeof(struct qdma_fmap_cfg)); - hw->qdma_fmap_conf(dev_hndl, hdr->src_func_id, &fmap_cfg, - QDMA_HW_ACCESS_WRITE); - - ret = QDMA_MBOX_VF_ONLINE; - } - break; - case MBOX_OP_FMAP: - { - struct mbox_msg_fmap *fmap = &rcv->fmap; - struct qdma_fmap_cfg fmap_cfg; - - fmap_cfg.qbase = fmap->qbase; - fmap_cfg.qmax = fmap->qmax; - - rv = hw->qdma_fmap_conf(dev_hndl, hdr->src_func_id, - &fmap_cfg, QDMA_HW_ACCESS_WRITE); - if (rv < 0) { - qdma_log_error("%s: failed to write fmap, err:%d\n", - __func__, rv); - return rv; - } - } - break; - case MBOX_OP_CSR: - { - struct mbox_msg_csr *rsp_csr = &resp->csr; - struct qdma_dev_attributes dev_cap; - - uint32_t ringsz[QDMA_GLOBAL_CSR_ARRAY_SZ] = {0}; - uint32_t bufsz[QDMA_GLOBAL_CSR_ARRAY_SZ] = {0}; - uint32_t tmr_th[QDMA_GLOBAL_CSR_ARRAY_SZ] = {0}; - uint32_t cntr_th[QDMA_GLOBAL_CSR_ARRAY_SZ] = {0}; - int i; - - rv = hw->qdma_global_csr_conf(dev_hndl, 0, - QDMA_GLOBAL_CSR_ARRAY_SZ, ringsz, - QDMA_CSR_RING_SZ, QDMA_HW_ACCESS_READ); - if (rv < 0) - goto exit_func; - - hw->qdma_get_device_attributes(dev_hndl, &dev_cap); - - if (dev_cap.st_en) { - rv = hw->qdma_global_csr_conf(dev_hndl, 0, - QDMA_GLOBAL_CSR_ARRAY_SZ, bufsz, - QDMA_CSR_BUF_SZ, QDMA_HW_ACCESS_READ); - if (rv < 0 && - (rv != -QDMA_ERR_HWACC_FEATURE_NOT_SUPPORTED)) - goto exit_func; - } - - if (dev_cap.st_en || dev_cap.mm_cmpt_en) { - rv = hw->qdma_global_csr_conf(dev_hndl, 0, - QDMA_GLOBAL_CSR_ARRAY_SZ, tmr_th, - QDMA_CSR_TIMER_CNT, QDMA_HW_ACCESS_READ); - if (rv < 0 && - (rv != -QDMA_ERR_HWACC_FEATURE_NOT_SUPPORTED)) - goto exit_func; - - rv = hw->qdma_global_csr_conf(dev_hndl, 0, - QDMA_GLOBAL_CSR_ARRAY_SZ, cntr_th, - QDMA_CSR_CNT_TH, QDMA_HW_ACCESS_READ); - if (rv < 0 && - (rv != -QDMA_ERR_HWACC_FEATURE_NOT_SUPPORTED)) - goto exit_func; - } - - for (i = 0; i < QDMA_GLOBAL_CSR_ARRAY_SZ; i++) { - rsp_csr->csr_info.ringsz[i] = ringsz[i] & - 0xFFFF; - if (!rv) { - rsp_csr->csr_info.bufsz[i] = bufsz[i] & 0xFFFF; - rsp_csr->csr_info.timer_cnt[i] = tmr_th[i] & - 0xFF; - rsp_csr->csr_info.cnt_thres[i] = cntr_th[i] & - 0xFF; - } - } - - if (rv == -QDMA_ERR_HWACC_FEATURE_NOT_SUPPORTED) - rv = QDMA_SUCCESS; - } - break; - case MBOX_OP_QREQ: - { - struct mbox_msg_fmap *fmap = &rcv->fmap; - - rv = qdma_dev_update(dma_device_index, - hdr->src_func_id, - fmap->qmax, &fmap->qbase); - if (rv == 0) - rv = qdma_dev_qinfo_get(dma_device_index, - hdr->src_func_id, - &resp->fmap.qbase, - &resp->fmap.qmax); - if (rv < 0) - rv = -QDMA_ERR_MBOX_NUM_QUEUES; - else { - struct qdma_fmap_cfg fmap_cfg; - - qdma_mbox_memset(&fmap_cfg, 0, - sizeof(struct qdma_fmap_cfg)); - hw->qdma_fmap_conf(dev_hndl, hdr->src_func_id, - &fmap_cfg, QDMA_HW_ACCESS_WRITE); - } - } - break; - case MBOX_OP_QNOTIFY_ADD: - { - struct mbox_msg_q_nitfy *q_notify = &rcv->q_notify; - enum qdma_dev_q_range q_range; - - q_range = qdma_dev_is_queue_in_range( - dma_device_index, - q_notify->hdr.src_func_id, - q_notify->qid_hw); - if (q_range != QDMA_DEV_Q_IN_RANGE) - rv = -QDMA_ERR_MBOX_INV_QID; - else - rv = qdma_dev_increment_active_queue( - dma_device_index, - q_notify->hdr.src_func_id, - q_notify->q_type); - } - break; - case MBOX_OP_QNOTIFY_DEL: - { - struct mbox_msg_q_nitfy *q_notify = &rcv->q_notify; - enum qdma_dev_q_range q_range; - - q_range = qdma_dev_is_queue_in_range( - dma_device_index, - q_notify->hdr.src_func_id, - q_notify->qid_hw); - if (q_range != QDMA_DEV_Q_IN_RANGE) - rv = -QDMA_ERR_MBOX_INV_QID; - else - rv = qdma_dev_decrement_active_queue( - dma_device_index, - q_notify->hdr.src_func_id, - q_notify->q_type); - } - break; - case MBOX_OP_GET_QACTIVE_CNT: - { - rv = qdma_get_device_active_queue_count( - dma_device_index, - rcv->hdr.src_func_id, - QDMA_DEV_Q_TYPE_H2C); - - resp->qcnt.h2c_queues = rv; - - rv = qdma_get_device_active_queue_count( - dma_device_index, - rcv->hdr.src_func_id, - QDMA_DEV_Q_TYPE_C2H); - - resp->qcnt.c2h_queues = rv; - - rv = qdma_get_device_active_queue_count( - dma_device_index, - rcv->hdr.src_func_id, - QDMA_DEV_Q_TYPE_CMPT); - - resp->qcnt.cmpt_queues = rv; - } - break; - case MBOX_OP_INTR_CTXT_WRT: - { - struct mbox_msg_intr_ctxt *ictxt = &rcv->intr_ctxt.ctxt; - struct qdma_indirect_intr_ctxt *ctxt; - uint8_t i; - uint32_t ring_index; - - for (i = 0; i < ictxt->num_rings; i++) { - ring_index = ictxt->ring_index_list[i]; - - ctxt = &ictxt->ictxt[i]; - rv = hw->qdma_indirect_intr_ctx_conf(dev_hndl, - ring_index, - NULL, - QDMA_HW_ACCESS_CLEAR); - if (rv < 0) - resp->hdr.status = rv; - rv = hw->qdma_indirect_intr_ctx_conf(dev_hndl, - ring_index, ctxt, - QDMA_HW_ACCESS_WRITE); - if (rv < 0) - resp->hdr.status = rv; - } - } - break; - case MBOX_OP_INTR_CTXT_RD: - { - struct mbox_msg_intr_ctxt *rcv_ictxt = &rcv->intr_ctxt.ctxt; - struct mbox_msg_intr_ctxt *rsp_ictxt = &resp->intr_ctxt.ctxt; - uint8_t i; - uint32_t ring_index; - - for (i = 0; i < rcv_ictxt->num_rings; i++) { - ring_index = rcv_ictxt->ring_index_list[i]; - - rv = hw->qdma_indirect_intr_ctx_conf(dev_hndl, - ring_index, - &rsp_ictxt->ictxt[i], - QDMA_HW_ACCESS_READ); - if (rv < 0) - resp->hdr.status = rv; - - } - } - break; - case MBOX_OP_INTR_CTXT_CLR: - { - int i; - struct mbox_msg_intr_ctxt *ictxt = &rcv->intr_ctxt.ctxt; - - for (i = 0; i < ictxt->num_rings; i++) { - rv = hw->qdma_indirect_intr_ctx_conf( - dev_hndl, - ictxt->ring_index_list[i], - NULL, QDMA_HW_ACCESS_CLEAR); - if (rv < 0) - resp->hdr.status = rv; - } - } - break; - case MBOX_OP_INTR_CTXT_INV: - { - struct mbox_msg_intr_ctxt *ictxt = &rcv->intr_ctxt.ctxt; - int i; - - for (i = 0; i < ictxt->num_rings; i++) { - rv = hw->qdma_indirect_intr_ctx_conf( - dev_hndl, - ictxt->ring_index_list[i], - NULL, QDMA_HW_ACCESS_INVALIDATE); - if (rv < 0) - resp->hdr.status = rv; - } - } - break; - case MBOX_OP_QCTXT_INV: - { - struct mbox_msg_qctxt *qctxt = &rcv->qctxt; - - rv = mbox_invalidate_queue_contexts(dev_hndl, - dma_device_index, - hdr->src_func_id, - qctxt->qid_hw, - qctxt->st, - qctxt->c2h, - qctxt->cmpt_ctxt_type); - } - break; - case MBOX_OP_QCTXT_CLR: - { - struct mbox_msg_qctxt *qctxt = &rcv->qctxt; - - rv = mbox_clear_queue_contexts(dev_hndl, - dma_device_index, - hdr->src_func_id, - qctxt->qid_hw, - qctxt->st, - qctxt->c2h, - qctxt->cmpt_ctxt_type); - } - break; - case MBOX_OP_QCTXT_RD: - { - struct mbox_msg_qctxt *qctxt = &rcv->qctxt; - - rv = mbox_read_queue_contexts(dev_hndl, hdr->src_func_id, - qctxt->qid_hw, - qctxt->st, - qctxt->c2h, - qctxt->cmpt_ctxt_type, - &resp->qctxt.descq_ctxt); - } - break; - case MBOX_OP_QCTXT_WRT: - { - struct mbox_msg_qctxt *qctxt = &rcv->qctxt; - - qctxt->descq_conf.func_id = hdr->src_func_id; - rv = mbox_write_queue_contexts(dev_hndl, - dma_device_index, qctxt); - } - break; - case MBOX_OP_RESET_PREPARE_RESP: - return QDMA_MBOX_VF_RESET; - case MBOX_OP_RESET_DONE_RESP: - return QDMA_MBOX_PF_RESET_DONE; - case MBOX_OP_REG_LIST_READ: - { - struct mbox_read_reg_list *rcv_read_reg_list = - &rcv->reg_read_list; - struct mbox_read_reg_list *rsp_read_reg_list = - &resp->reg_read_list; - - rv = hw->qdma_read_reg_list((void *)dev_hndl, 1, - rcv_read_reg_list->group_num, - &rsp_read_reg_list->num_regs, - rsp_read_reg_list->reg_list); - - if (rv < 0 || rsp_read_reg_list->num_regs == 0) { - rv = -QDMA_ERR_MBOX_REG_READ_FAILED; - goto exit_func; - } - - } - break; - case MBOX_OP_PF_BYE_RESP: - return QDMA_MBOX_PF_BYE; - default: - qdma_log_error("%s: op=%d invalid, err:%d\n", - __func__, - rcv->hdr.op, - -QDMA_ERR_MBOX_INV_MSG); - return -QDMA_ERR_MBOX_INV_MSG; - break; - } - -exit_func: - resp->hdr.op = rcv->hdr.op + MBOX_MSG_OP_RSP_OFFSET; - resp->hdr.dst_func_id = rcv->hdr.src_func_id; - resp->hdr.src_func_id = func_id; - - resp->hdr.status = rv; - - return ret; -} - -int qmda_mbox_compose_vf_online(uint16_t func_id, - uint16_t qmax, int *qbase, uint32_t *raw_data) -{ - union qdma_mbox_txrx *msg = (union qdma_mbox_txrx *)raw_data; - - if (!raw_data) { - qdma_log_error("%s: raw_data=%p, err:%d\n", - __func__, raw_data, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - qdma_mbox_memset(raw_data, 0, sizeof(union qdma_mbox_txrx)); - msg->hdr.op = MBOX_OP_HELLO; - msg->hdr.src_func_id = func_id; - msg->fmap.qbase = (uint32_t)*qbase; - msg->fmap.qmax = qmax; - - return QDMA_SUCCESS; -} - -int qdma_mbox_compose_vf_offline(uint16_t func_id, - uint32_t *raw_data) -{ - union qdma_mbox_txrx *msg = (union qdma_mbox_txrx *)raw_data; - - if (!raw_data) { - qdma_log_error("%s: raw_data=%p, err:%d\n", - __func__, raw_data, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - qdma_mbox_memset(raw_data, 0, sizeof(union qdma_mbox_txrx)); - msg->hdr.op = MBOX_OP_VF_BYE; - msg->hdr.src_func_id = func_id; - - return QDMA_SUCCESS; -} - -int qdma_mbox_compose_vf_reset_offline(uint16_t func_id, - uint32_t *raw_data) -{ - union qdma_mbox_txrx *msg = (union qdma_mbox_txrx *)raw_data; - - if (!raw_data) { - qdma_log_error("%s: raw_data=%p, err:%d\n", - __func__, raw_data, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - qdma_mbox_memset(raw_data, 0, sizeof(union qdma_mbox_txrx)); - msg->hdr.op = MBOX_OP_PF_RESET_VF_BYE; - msg->hdr.src_func_id = func_id; - - return QDMA_SUCCESS; -} - - - -int qdma_mbox_compose_vf_qreq(uint16_t func_id, - uint16_t qmax, int qbase, uint32_t *raw_data) -{ - union qdma_mbox_txrx *msg = (union qdma_mbox_txrx *)raw_data; - - if (!raw_data) { - qdma_log_error("%s: raw_data=%p, err:%d\n", - __func__, raw_data, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - qdma_mbox_memset(raw_data, 0, sizeof(union qdma_mbox_txrx)); - msg->hdr.op = MBOX_OP_QREQ; - msg->hdr.src_func_id = func_id; - msg->fmap.qbase = qbase; - msg->fmap.qmax = qmax; - - return QDMA_SUCCESS; -} - -int qdma_mbox_compose_vf_notify_qadd(uint16_t func_id, - uint16_t qid_hw, - enum qdma_dev_q_type q_type, - uint32_t *raw_data) -{ - union qdma_mbox_txrx *msg = (union qdma_mbox_txrx *)raw_data; - - if (!raw_data) { - qdma_log_error("%s: raw_data=%p, err:%d\n", - __func__, raw_data, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - qdma_mbox_memset(raw_data, 0, sizeof(union qdma_mbox_txrx)); - msg->hdr.op = MBOX_OP_QNOTIFY_ADD; - msg->hdr.src_func_id = func_id; - msg->q_notify.qid_hw = qid_hw; - msg->q_notify.q_type = q_type; - - return QDMA_SUCCESS; -} - -int qdma_mbox_compose_vf_get_device_active_qcnt(uint16_t func_id, - uint32_t *raw_data) -{ - union qdma_mbox_txrx *msg = (union qdma_mbox_txrx *)raw_data; - - if (!raw_data) { - qdma_log_error("%s: raw_data=%p, err:%d\n", - __func__, raw_data, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - qdma_mbox_memset(raw_data, 0, sizeof(union qdma_mbox_txrx)); - msg->hdr.op = MBOX_OP_GET_QACTIVE_CNT; - msg->hdr.src_func_id = func_id; - - return QDMA_SUCCESS; -} - -int qdma_mbox_compose_vf_notify_qdel(uint16_t func_id, - uint16_t qid_hw, - enum qdma_dev_q_type q_type, - uint32_t *raw_data) -{ - union qdma_mbox_txrx *msg = (union qdma_mbox_txrx *)raw_data; - - if (!raw_data) { - qdma_log_error("%s: raw_data=%p, err:%d\n", - __func__, raw_data, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - qdma_mbox_memset(raw_data, 0, sizeof(union qdma_mbox_txrx)); - msg->hdr.op = MBOX_OP_QNOTIFY_DEL; - msg->hdr.src_func_id = func_id; - msg->q_notify.qid_hw = qid_hw; - msg->q_notify.q_type = q_type; - - return QDMA_SUCCESS; -} - -int qdma_mbox_compose_vf_fmap_prog(uint16_t func_id, - uint16_t qmax, int qbase, - uint32_t *raw_data) -{ - union qdma_mbox_txrx *msg = (union qdma_mbox_txrx *)raw_data; - - if (!raw_data) { - qdma_log_error("%s: raw_data=%p, err:%d\n", - __func__, raw_data, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - qdma_mbox_memset(raw_data, 0, sizeof(union qdma_mbox_txrx)); - msg->hdr.op = MBOX_OP_FMAP; - msg->hdr.src_func_id = func_id; - msg->fmap.qbase = (uint32_t)qbase; - msg->fmap.qmax = qmax; - - return QDMA_SUCCESS; -} - -int qdma_mbox_compose_vf_qctxt_write(uint16_t func_id, - uint16_t qid_hw, uint8_t st, uint8_t c2h, - enum mbox_cmpt_ctxt_type cmpt_ctxt_type, - struct mbox_descq_conf *descq_conf, - uint32_t *raw_data) -{ - union qdma_mbox_txrx *msg = (union qdma_mbox_txrx *)raw_data; - - if (!raw_data) { - qdma_log_error("%s: raw_data=%p, err:%d\n", - __func__, raw_data, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - qdma_mbox_memset(raw_data, 0, sizeof(union qdma_mbox_txrx)); - msg->hdr.op = MBOX_OP_QCTXT_WRT; - msg->hdr.src_func_id = func_id; - msg->qctxt.qid_hw = qid_hw; - msg->qctxt.c2h = c2h; - msg->qctxt.st = st; - msg->qctxt.cmpt_ctxt_type = cmpt_ctxt_type; - - qdma_mbox_memcpy(&msg->qctxt.descq_conf, descq_conf, - sizeof(struct mbox_descq_conf)); - - return QDMA_SUCCESS; -} - -int qdma_mbox_compose_vf_qctxt_read(uint16_t func_id, - uint16_t qid_hw, uint8_t st, uint8_t c2h, - enum mbox_cmpt_ctxt_type cmpt_ctxt_type, - uint32_t *raw_data) -{ - union qdma_mbox_txrx *msg = (union qdma_mbox_txrx *)raw_data; - - if (!raw_data) { - qdma_log_error("%s: raw_data=%p, err:%d\n", - __func__, raw_data, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - qdma_mbox_memset(raw_data, 0, sizeof(union qdma_mbox_txrx)); - msg->hdr.op = MBOX_OP_QCTXT_RD; - msg->hdr.src_func_id = func_id; - msg->qctxt.qid_hw = qid_hw; - msg->qctxt.c2h = c2h; - msg->qctxt.st = st; - msg->qctxt.cmpt_ctxt_type = cmpt_ctxt_type; - - return QDMA_SUCCESS; -} - -int qdma_mbox_compose_vf_qctxt_invalidate(uint16_t func_id, - uint16_t qid_hw, uint8_t st, uint8_t c2h, - enum mbox_cmpt_ctxt_type cmpt_ctxt_type, - uint32_t *raw_data) -{ - union qdma_mbox_txrx *msg = (union qdma_mbox_txrx *)raw_data; - - if (!raw_data) { - qdma_log_error("%s: raw_data=%p, err:%d\n", - __func__, raw_data, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - qdma_mbox_memset(raw_data, 0, sizeof(union qdma_mbox_txrx)); - msg->hdr.op = MBOX_OP_QCTXT_INV; - msg->hdr.src_func_id = func_id; - msg->qctxt.qid_hw = qid_hw; - msg->qctxt.c2h = c2h; - msg->qctxt.st = st; - msg->qctxt.cmpt_ctxt_type = cmpt_ctxt_type; - - return QDMA_SUCCESS; -} - -int qdma_mbox_compose_vf_qctxt_clear(uint16_t func_id, - uint16_t qid_hw, uint8_t st, uint8_t c2h, - enum mbox_cmpt_ctxt_type cmpt_ctxt_type, - uint32_t *raw_data) -{ - union qdma_mbox_txrx *msg = (union qdma_mbox_txrx *)raw_data; - - if (!raw_data) { - qdma_log_error("%s: raw_data=%p, err:%d\n", - __func__, raw_data, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - qdma_mbox_memset(raw_data, 0, sizeof(union qdma_mbox_txrx)); - msg->hdr.op = MBOX_OP_QCTXT_CLR; - msg->hdr.src_func_id = func_id; - msg->qctxt.qid_hw = qid_hw; - msg->qctxt.c2h = c2h; - msg->qctxt.st = st; - msg->qctxt.cmpt_ctxt_type = cmpt_ctxt_type; - - return QDMA_SUCCESS; -} - -int qdma_mbox_compose_csr_read(uint16_t func_id, - uint32_t *raw_data) -{ - union qdma_mbox_txrx *msg = (union qdma_mbox_txrx *)raw_data; - - if (!raw_data) { - qdma_log_error("%s: raw_data=%p, err:%d\n", - __func__, raw_data, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - qdma_mbox_memset(raw_data, 0, sizeof(union qdma_mbox_txrx)); - msg->hdr.op = MBOX_OP_CSR; - msg->hdr.src_func_id = func_id; - - return QDMA_SUCCESS; -} - -int qdma_mbox_compose_reg_read(uint16_t func_id, - uint16_t group_num, - uint32_t *raw_data) -{ - union qdma_mbox_txrx *msg = (union qdma_mbox_txrx *)raw_data; - - if (!raw_data) { - qdma_log_error("%s: raw_data=%p, err:%d\n", - __func__, raw_data, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - qdma_mbox_memset(raw_data, 0, sizeof(union qdma_mbox_txrx)); - msg->hdr.op = MBOX_OP_REG_LIST_READ; - msg->hdr.src_func_id = func_id; - msg->reg_read_list.group_num = group_num; - - return QDMA_SUCCESS; -} - -int qdma_mbox_compose_vf_intr_ctxt_write(uint16_t func_id, - struct mbox_msg_intr_ctxt *intr_ctxt, - uint32_t *raw_data) -{ - union qdma_mbox_txrx *msg = (union qdma_mbox_txrx *)raw_data; - - if (!raw_data) { - qdma_log_error("%s: raw_data=%p, err:%d\n", - __func__, raw_data, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - qdma_mbox_memset(raw_data, 0, sizeof(union qdma_mbox_txrx)); - msg->hdr.op = MBOX_OP_INTR_CTXT_WRT; - msg->hdr.src_func_id = func_id; - qdma_mbox_memcpy(&msg->intr_ctxt.ctxt, intr_ctxt, - sizeof(struct mbox_msg_intr_ctxt)); - - return QDMA_SUCCESS; -} - -int qdma_mbox_compose_vf_intr_ctxt_read(uint16_t func_id, - struct mbox_msg_intr_ctxt *intr_ctxt, - uint32_t *raw_data) -{ - union qdma_mbox_txrx *msg = (union qdma_mbox_txrx *)raw_data; - - if (!raw_data) { - qdma_log_error("%s: raw_data=%p, err:%d\n", - __func__, raw_data, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - qdma_mbox_memset(raw_data, 0, sizeof(union qdma_mbox_txrx)); - msg->hdr.op = MBOX_OP_INTR_CTXT_RD; - msg->hdr.src_func_id = func_id; - qdma_mbox_memcpy(&msg->intr_ctxt.ctxt, intr_ctxt, - sizeof(struct mbox_msg_intr_ctxt)); - - return QDMA_SUCCESS; -} - -int qdma_mbox_compose_vf_intr_ctxt_clear(uint16_t func_id, - struct mbox_msg_intr_ctxt *intr_ctxt, - uint32_t *raw_data) -{ - union qdma_mbox_txrx *msg = (union qdma_mbox_txrx *)raw_data; - - if (!raw_data) { - qdma_log_error("%s: raw_data=%p, err:%d\n", - __func__, raw_data, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - qdma_mbox_memset(raw_data, 0, sizeof(union qdma_mbox_txrx)); - msg->hdr.op = MBOX_OP_INTR_CTXT_CLR; - msg->hdr.src_func_id = func_id; - qdma_mbox_memcpy(&msg->intr_ctxt.ctxt, intr_ctxt, - sizeof(struct mbox_msg_intr_ctxt)); - - return QDMA_SUCCESS; -} - -int qdma_mbox_compose_vf_intr_ctxt_invalidate(uint16_t func_id, - struct mbox_msg_intr_ctxt *intr_ctxt, - uint32_t *raw_data) -{ - union qdma_mbox_txrx *msg = (union qdma_mbox_txrx *)raw_data; - - if (!raw_data) { - qdma_log_error("%s: raw_data=%p, err:%d\n", - __func__, raw_data, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - qdma_mbox_memset(raw_data, 0, sizeof(union qdma_mbox_txrx)); - msg->hdr.op = MBOX_OP_INTR_CTXT_INV; - msg->hdr.src_func_id = func_id; - qdma_mbox_memcpy(&msg->intr_ctxt.ctxt, intr_ctxt, - sizeof(struct mbox_msg_intr_ctxt)); - - return QDMA_SUCCESS; -} - -uint8_t qdma_mbox_is_msg_response(uint32_t *send_data, uint32_t *rcv_data) -{ - union qdma_mbox_txrx *tx_msg = (union qdma_mbox_txrx *)send_data; - union qdma_mbox_txrx *rx_msg = (union qdma_mbox_txrx *)rcv_data; - - return ((tx_msg->hdr.op + MBOX_MSG_OP_RSP_OFFSET) == rx_msg->hdr.op) ? - 1 : 0; -} - -int qdma_mbox_vf_response_status(uint32_t *rcv_data) -{ - union qdma_mbox_txrx *msg = (union qdma_mbox_txrx *)rcv_data; - - return msg->hdr.status; -} - -uint8_t qdma_mbox_vf_func_id_get(uint32_t *rcv_data, uint8_t is_vf) -{ - union qdma_mbox_txrx *msg = (union qdma_mbox_txrx *)rcv_data; - uint16_t func_id; - - if (is_vf) - func_id = msg->hdr.dst_func_id; - else - func_id = msg->hdr.src_func_id; - - return func_id; -} - -int qdma_mbox_vf_active_queues_get(uint32_t *rcv_data, - enum qdma_dev_q_type q_type) -{ - union qdma_mbox_txrx *msg = (union qdma_mbox_txrx *)rcv_data; - int queues = 0; - - if (q_type == QDMA_DEV_Q_TYPE_H2C) - queues = msg->qcnt.h2c_queues; - - if (q_type == QDMA_DEV_Q_TYPE_C2H) - queues = msg->qcnt.c2h_queues; - - if (q_type == QDMA_DEV_Q_TYPE_CMPT) - queues = msg->qcnt.cmpt_queues; - - return queues; -} - - -uint8_t qdma_mbox_vf_parent_func_id_get(uint32_t *rcv_data) -{ - union qdma_mbox_txrx *msg = (union qdma_mbox_txrx *)rcv_data; - - return msg->hdr.src_func_id; -} - -int qdma_mbox_vf_dev_info_get(uint32_t *rcv_data, - struct qdma_dev_attributes *dev_cap, uint32_t *dma_device_index) -{ - union qdma_mbox_txrx *msg = (union qdma_mbox_txrx *)rcv_data; - - *dev_cap = msg->hello.dev_cap; - *dma_device_index = msg->hello.dma_device_index; - - return msg->hdr.status; -} - -int qdma_mbox_vf_qinfo_get(uint32_t *rcv_data, int *qbase, uint16_t *qmax) -{ - union qdma_mbox_txrx *msg = (union qdma_mbox_txrx *)rcv_data; - - *qbase = msg->fmap.qbase; - *qmax = msg->fmap.qmax; - - return msg->hdr.status; -} - -int qdma_mbox_vf_csr_get(uint32_t *rcv_data, struct qdma_csr_info *csr) -{ - union qdma_mbox_txrx *msg = (union qdma_mbox_txrx *)rcv_data; - - qdma_mbox_memcpy(csr, &msg->csr.csr_info, sizeof(struct qdma_csr_info)); - - return msg->hdr.status; - -} - -int qdma_mbox_vf_reg_list_get(uint32_t *rcv_data, - uint16_t *num_regs, struct qdma_reg_data *reg_list) -{ - union qdma_mbox_txrx *msg = (union qdma_mbox_txrx *)rcv_data; - - *num_regs = msg->reg_read_list.num_regs; - qdma_mbox_memcpy(reg_list, &(msg->reg_read_list.reg_list), - (*num_regs * sizeof(struct qdma_reg_data))); - - return msg->hdr.status; - -} - -int qdma_mbox_vf_context_get(uint32_t *rcv_data, - struct qdma_descq_context *ctxt) -{ - union qdma_mbox_txrx *msg = (union qdma_mbox_txrx *)rcv_data; - - qdma_mbox_memcpy(ctxt, &msg->qctxt.descq_ctxt, - sizeof(struct qdma_descq_context)); - - return msg->hdr.status; -} - -int qdma_mbox_vf_intr_context_get(uint32_t *rcv_data, - struct mbox_msg_intr_ctxt *ictxt) -{ - union qdma_mbox_txrx *msg = (union qdma_mbox_txrx *)rcv_data; - - qdma_mbox_memcpy(ictxt, &msg->intr_ctxt.ctxt, - sizeof(struct mbox_msg_intr_ctxt)); - - return msg->hdr.status; -} - -void qdma_mbox_pf_hw_clear_ack(void *dev_hndl) -{ - uint32_t v; - uint32_t reg; - int i; - uint32_t mbox_base = get_mbox_offset(dev_hndl, 0); - - reg = mbox_base + MBOX_PF_ACK_BASE; - - v = qdma_reg_read(dev_hndl, mbox_base + MBOX_FN_STATUS); - if ((v & F_MBOX_FN_STATUS_ACK) == 0) - return; - - for (i = 0; i < MBOX_PF_ACK_COUNT; i++, reg += MBOX_PF_ACK_STEP) { - v = qdma_reg_read(dev_hndl, reg); - - if (!v) - continue; - - /* clear the ack status */ - qdma_reg_write(dev_hndl, reg, v); - } -} - -int qdma_mbox_send(void *dev_hndl, uint8_t is_vf, uint32_t *raw_data) -{ - int i; - uint32_t reg = MBOX_OUT_MSG_BASE; - uint32_t v; - union qdma_mbox_txrx *msg = (union qdma_mbox_txrx *)raw_data; - uint16_t dst_func_id = msg->hdr.dst_func_id; - uint32_t mbox_base = get_mbox_offset(dev_hndl, is_vf); - - v = qdma_reg_read(dev_hndl, mbox_base + MBOX_FN_STATUS); - if (v & F_MBOX_FN_STATUS_OUT_MSG) - return -QDMA_ERR_MBOX_SEND_BUSY; - - if (!is_vf) - qdma_reg_write(dev_hndl, mbox_base + MBOX_FN_TARGET, - V_MBOX_FN_TARGET_ID(dst_func_id)); - - for (i = 0; i < MBOX_MSG_REG_MAX; i++, reg += MBOX_MSG_STEP) - qdma_reg_write(dev_hndl, mbox_base + reg, raw_data[i]); - - /* clear the outgoing ack */ - if (!is_vf) - mbox_pf_hw_clear_func_ack(dev_hndl, dst_func_id); - - - qdma_log_debug("%s %s tx from_id=%d, to_id=%d, opcode=0x%x\n", __func__, - is_vf?"VF":"PF", msg->hdr.src_func_id, - msg->hdr.dst_func_id, msg->hdr.op); - qdma_reg_write(dev_hndl, mbox_base + MBOX_FN_CMD, F_MBOX_FN_CMD_SND); - - return QDMA_SUCCESS; -} - -int qdma_mbox_rcv(void *dev_hndl, uint8_t is_vf, uint32_t *raw_data) -{ - uint32_t reg = MBOX_IN_MSG_BASE; - uint32_t v = 0; - int all_zero_msg = 1; - int i; - uint32_t from_id = 0; - union qdma_mbox_txrx *msg = (union qdma_mbox_txrx *)raw_data; - uint32_t mbox_base = get_mbox_offset(dev_hndl, is_vf); - - v = qdma_reg_read(dev_hndl, mbox_base + MBOX_FN_STATUS); - - if (!(v & M_MBOX_FN_STATUS_IN_MSG)) - return -QDMA_ERR_MBOX_NO_MSG_IN; - - if (!is_vf) { - from_id = G_MBOX_FN_STATUS_SRC(v); - qdma_reg_write(dev_hndl, mbox_base + MBOX_FN_TARGET, from_id); - } - - for (i = 0; i < MBOX_MSG_REG_MAX; i++, reg += MBOX_MSG_STEP) { - raw_data[i] = qdma_reg_read(dev_hndl, mbox_base + reg); - /* if rcv'ed message is all zero, stop and disable the mbox, - * the h/w mbox is not working properly - */ - if (raw_data[i]) - all_zero_msg = 0; - } - - /* ack'ed the sender */ - qdma_reg_write(dev_hndl, mbox_base + MBOX_FN_CMD, F_MBOX_FN_CMD_RCV); - if (all_zero_msg) { - qdma_log_error("%s: Message recv'd is all zeros. failure:%d\n", - __func__, - -QDMA_ERR_MBOX_ALL_ZERO_MSG); - return -QDMA_ERR_MBOX_ALL_ZERO_MSG; - } - - - qdma_log_debug("%s %s fid=%d, opcode=0x%x\n", __func__, - is_vf?"VF":"PF", msg->hdr.dst_func_id, - msg->hdr.op); - if (!is_vf && (from_id != msg->hdr.src_func_id)) - msg->hdr.src_func_id = from_id; - - return QDMA_SUCCESS; -} - -void qdma_mbox_hw_init(void *dev_hndl, uint8_t is_vf) -{ - uint32_t v; - uint32_t mbox_base = get_mbox_offset(dev_hndl, is_vf); - - if (is_vf) { - v = qdma_reg_read(dev_hndl, mbox_base + MBOX_FN_STATUS); - if (v & M_MBOX_FN_STATUS_IN_MSG) - qdma_reg_write(dev_hndl, mbox_base + MBOX_FN_CMD, - F_MBOX_FN_CMD_RCV); - } else - qdma_mbox_pf_hw_clear_ack(dev_hndl); -} - -void qdma_mbox_enable_interrupts(void *dev_hndl, uint8_t is_vf) -{ - int vector = 0x0; - uint32_t mbox_base = get_mbox_offset(dev_hndl, is_vf); - - qdma_reg_write(dev_hndl, mbox_base + MBOX_ISR_VEC, vector); - qdma_reg_write(dev_hndl, mbox_base + MBOX_ISR_EN, 0x1); -} - -void qdma_mbox_disable_interrupts(void *dev_hndl, uint8_t is_vf) -{ - uint32_t mbox_base = get_mbox_offset(dev_hndl, is_vf); - - qdma_reg_write(dev_hndl, mbox_base + MBOX_ISR_EN, 0x0); -} - - -int qdma_mbox_compose_vf_reset_message(uint32_t *raw_data, uint8_t src_funcid, - uint8_t dest_funcid) -{ - union qdma_mbox_txrx *msg = (union qdma_mbox_txrx *)raw_data; - - if (!raw_data) - return -QDMA_ERR_INV_PARAM; - - qdma_mbox_memset(raw_data, 0, sizeof(union qdma_mbox_txrx)); - msg->hdr.op = MBOX_OP_RESET_PREPARE; - msg->hdr.src_func_id = src_funcid; - msg->hdr.dst_func_id = dest_funcid; - return 0; -} - -int qdma_mbox_compose_pf_reset_done_message(uint32_t *raw_data, - uint8_t src_funcid, uint8_t dest_funcid) -{ - union qdma_mbox_txrx *msg = (union qdma_mbox_txrx *)raw_data; - - if (!raw_data) - return -QDMA_ERR_INV_PARAM; - - qdma_mbox_memset(raw_data, 0, sizeof(union qdma_mbox_txrx)); - msg->hdr.op = MBOX_OP_RESET_DONE; - msg->hdr.src_func_id = src_funcid; - msg->hdr.dst_func_id = dest_funcid; - return 0; -} - -int qdma_mbox_compose_pf_offline(uint32_t *raw_data, uint8_t src_funcid, - uint8_t dest_funcid) -{ - union qdma_mbox_txrx *msg = (union qdma_mbox_txrx *)raw_data; - - if (!raw_data) - return -QDMA_ERR_INV_PARAM; - - qdma_mbox_memset(raw_data, 0, sizeof(union qdma_mbox_txrx)); - msg->hdr.op = MBOX_OP_PF_BYE; - msg->hdr.src_func_id = src_funcid; - msg->hdr.dst_func_id = dest_funcid; - return 0; -} - -int qdma_mbox_vf_rcv_msg_handler(uint32_t *rcv_msg, uint32_t *resp_msg) -{ - union qdma_mbox_txrx *rcv = (union qdma_mbox_txrx *)rcv_msg; - union qdma_mbox_txrx *resp = (union qdma_mbox_txrx *)resp_msg; - int rv = 0; - - switch (rcv->hdr.op) { - case MBOX_OP_RESET_PREPARE: - resp->hdr.op = rcv->hdr.op + MBOX_MSG_OP_RSP_OFFSET; - resp->hdr.dst_func_id = rcv->hdr.src_func_id; - resp->hdr.src_func_id = rcv->hdr.dst_func_id; - rv = QDMA_MBOX_VF_RESET; - break; - case MBOX_OP_RESET_DONE: - resp->hdr.op = rcv->hdr.op + MBOX_MSG_OP_RSP_OFFSET; - resp->hdr.dst_func_id = rcv->hdr.src_func_id; - resp->hdr.src_func_id = rcv->hdr.dst_func_id; - rv = QDMA_MBOX_PF_RESET_DONE; - break; - case MBOX_OP_PF_BYE: - resp->hdr.op = rcv->hdr.op + MBOX_MSG_OP_RSP_OFFSET; - resp->hdr.dst_func_id = rcv->hdr.src_func_id; - resp->hdr.src_func_id = rcv->hdr.dst_func_id; - rv = QDMA_MBOX_PF_BYE; - break; - default: - break; - } - return rv; -} - -uint8_t qdma_mbox_out_status(void *dev_hndl, uint8_t is_vf) -{ - uint32_t v; - uint32_t mbox_base = get_mbox_offset(dev_hndl, is_vf); - - v = qdma_reg_read(dev_hndl, mbox_base + MBOX_FN_STATUS); - if (v & F_MBOX_FN_STATUS_OUT_MSG) - return 1; - else - return 0; -} diff --git a/QDMA/linux-kernel/driver/libqdma/qdma_access/qdma_mbox_protocol.h b/QDMA/linux-kernel/driver/libqdma/qdma_access/qdma_mbox_protocol.h deleted file mode 100755 index b29a8c0bc..000000000 --- a/QDMA/linux-kernel/driver/libqdma/qdma_access/qdma_mbox_protocol.h +++ /dev/null @@ -1,695 +0,0 @@ -/* - * Copyright (c) 2019-2022, Xilinx, Inc. All rights reserved. - * Copyright (c) 2022, Advanced Micro Devices, Inc. All rights reserved. - * - * This source code is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * The full GNU General Public License is included in this distribution in - * the file called "COPYING". - */ - -#ifndef __QDMA_MBOX_PROTOCOL_H_ -#define __QDMA_MBOX_PROTOCOL_H_ - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * DOC: QDMA message box handling interface definitions - * - * Header file *qdma_mbox_protocol.h* defines data structures and function - * signatures exported for QDMA Mbox message handling. - */ - -#include "qdma_platform.h" -#include "qdma_resource_mgmt.h" - - -#define QDMA_MBOX_VF_ONLINE (1) -#define QDMA_MBOX_VF_OFFLINE (-1) -#define QDMA_MBOX_VF_RESET (2) -#define QDMA_MBOX_PF_RESET_DONE (3) -#define QDMA_MBOX_PF_BYE (4) -#define QDMA_MBOX_VF_RESET_BYE (5) - -/** mailbox register max */ -#define MBOX_MSG_REG_MAX 32 - -#define mbox_invalidate_msg(m) { (m)->hdr.op = MBOX_OP_NOOP; } - -/** - * struct mbox_descq_conf - collective bit-fields of all contexts - */ -struct mbox_descq_conf { - - /** @ring_bs_addr: ring base address */ - uint64_t ring_bs_addr; - /** @cmpt_ring_bs_addr: completion ring base address */ - uint64_t cmpt_ring_bs_addr; - /** @forced_en: enable fetch credit */ - uint32_t forced_en:1; - /** @en_bypass: bypass enable */ - uint32_t en_bypass:1; - /** @irq_arm: arm irq */ - uint32_t irq_arm:1; - /** @wbi_intvl_en: writeback interval enable */ - uint32_t wbi_intvl_en:1; - /** @wbi_chk: writeback pending check */ - uint32_t wbi_chk:1; - /** @at: address translation */ - uint32_t at:1; - /** @wbk_en: writeback enable */ - uint32_t wbk_en:1; - /** @irq_en: irq enable */ - uint32_t irq_en:1; - /** @pfch_en: prefetch enable */ - uint32_t pfch_en:1; - /** @en_bypass_prefetch: prefetch bypass enable */ - uint32_t en_bypass_prefetch:1; - /** @dis_overflow_check: disable overflow check */ - uint32_t dis_overflow_check:1; - /** @cmpt_int_en: completion interrupt enable */ - uint32_t cmpt_int_en:1; - /** @cmpt_at: completion address translation */ - uint32_t cmpt_at:1; - /** @cmpt_color: completion ring initial color bit */ - uint32_t cmpt_color:1; - /** @cmpt_full_upd: completion full update */ - uint32_t cmpt_full_upd:1; - /** @cmpl_stat_en: completion status enable */ - uint32_t cmpl_stat_en:1; - /** @desc_sz: descriptor size */ - uint32_t desc_sz:2; - /** @cmpt_desc_sz: completion ring descriptor size */ - uint32_t cmpt_desc_sz:2; - /** @triggermode: trigger mode */ - uint32_t triggermode:3; - /** @rsvd: reserved */ - uint32_t rsvd:9; - /** @func_id: function ID */ - uint32_t func_id:16; - /** @cnt_thres: counter threshold */ - uint32_t cnt_thres:8; - /** @timer_thres: timer threshold */ - uint32_t timer_thres:8; - /** @intr_id: interrupt id */ - uint16_t intr_id:11; - /** @intr_aggr: interrupt aggregation */ - uint16_t intr_aggr:1; - /** @filler: filler bits */ - uint16_t filler:4; - /** @ringsz: ring size */ - uint16_t ringsz; - /** @bufsz: c2h buffer size */ - uint16_t bufsz; - /** @cmpt_ringsz: completion ring size */ - uint16_t cmpt_ringsz; -}; - -/** - * @enum - mbox_cmpt_ctxt_type - * @brief specifies whether cmpt is enabled with MM/ST - */ -enum mbox_cmpt_ctxt_type { - /** @QDMA_MBOX_CMPT_CTXT_ONLY: only cmpt context programming required */ - QDMA_MBOX_CMPT_CTXT_ONLY, - /** @QDMA_MBOX_CMPT_WITH_MM: completion context with MM */ - QDMA_MBOX_CMPT_WITH_MM, - /** @QDMA_MBOX_CMPT_WITH_ST: complete context with ST */ - QDMA_MBOX_CMPT_WITH_ST, - /** @QDMA_MBOX_CMPT_CTXT_NONE: No completion context */ - QDMA_MBOX_CMPT_CTXT_NONE -}; - -/** - * @struct - mbox_msg_intr_ctxt - * @brief interrupt context mailbox message - */ -struct mbox_msg_intr_ctxt { - /** @num_rings: number of intr context rings be assigned - * for virtual function - */ - uint8_t num_rings; /* 1 ~ 8 */ - /** @ring_index_list: ring index associated for each vector */ - uint32_t ring_index_list[QDMA_NUM_DATA_VEC_FOR_INTR_CXT]; - /** @w: interrupt context data for all rings*/ - struct qdma_indirect_intr_ctxt ictxt[QDMA_NUM_DATA_VEC_FOR_INTR_CXT]; -}; - -/*****************************************************************************/ -/** - * qdma_mbox_hw_init(): Initialize the mobx HW - * - * @dev_hndl: device handle - * @is_vf: is VF mbox - * - * Return: None - *****************************************************************************/ -void qdma_mbox_hw_init(void *dev_hndl, uint8_t is_vf); - -/*****************************************************************************/ -/** - * qdma_mbox_pf_rcv_msg_handler(): handles the raw message received in pf - * - * @dma_device_index: pci bus number - * @dev_hndl: device handle - * @func_id: own function id - * @rcv_msg: received raw message - * @resp_msg: raw response message - * - * Return: 0 : success and < 0: failure - *****************************************************************************/ -int qdma_mbox_pf_rcv_msg_handler(void *dev_hndl, uint8_t dma_device_index, - uint16_t func_id, uint32_t *rcv_msg, - uint32_t *resp_msg); - -/*****************************************************************************/ -/** - * qmda_mbox_compose_vf_online(): compose VF online message - * - * @func_id: destination function id - * @qmax: number of queues being requested - * @qbase: q base at which queues are allocated - * @raw_data: output raw message to be sent - * - * Return: 0 : success and < 0: failure - *****************************************************************************/ -int qmda_mbox_compose_vf_online(uint16_t func_id, - uint16_t qmax, int *qbase, uint32_t *raw_data); - -/*****************************************************************************/ -/** - * qdma_mbox_compose_vf_offline(): compose VF offline message - * - * @func_id: destination function id - * @raw_data: output raw message to be sent - * - * Return: 0 : success and < 0: failure - *****************************************************************************/ -int qdma_mbox_compose_vf_offline(uint16_t func_id, - uint32_t *raw_data); - -/*****************************************************************************/ -/** - * qdma_mbox_compose_vf_reset_message(): compose VF reset message - * - * @raw_data: output raw message to be sent - * @src_funcid: own function id - * @dest_funcid: destination function id - * - * Return: 0 : success and < 0: failure - *****************************************************************************/ -int qdma_mbox_compose_vf_reset_message(uint32_t *raw_data, uint8_t src_funcid, - uint8_t dest_funcid); - -/*****************************************************************************/ -/** - * qdma_mbox_compose_vf_reset_offline(): compose VF BYE for PF initiated RESET - * - * @func_id: own function id - * @raw_data: output raw message to be sent - * - * Return: 0 : success and < 0: failure - *****************************************************************************/ -int qdma_mbox_compose_vf_reset_offline(uint16_t func_id, - uint32_t *raw_data); -/*****************************************************************************/ -/** - * qdma_mbox_compose_pf_reset_done_message(): compose PF reset done message - * - * @raw_data: output raw message to be sent - * @src_funcid: own function id - * @dest_funcid: destination function id - * - * Return: 0 : success and < 0: failure - *****************************************************************************/ -int qdma_mbox_compose_pf_reset_done_message(uint32_t *raw_data, - uint8_t src_funcid, uint8_t dest_funcid); - -/*****************************************************************************/ -/** - * qdma_mbox_compose_pf_offline(): compose PF offline message - * - * @raw_data: output raw message to be sent - * @src_funcid: own function id - * @dest_funcid: destination function id - * - * Return: 0 : success and < 0: failure - *****************************************************************************/ -int qdma_mbox_compose_pf_offline(uint32_t *raw_data, uint8_t src_funcid, - uint8_t dest_funcid); - -/*****************************************************************************/ -/** - * qdma_mbox_compose_vf_qreq(): compose message to request queues - * - * @func_id: destination function id - * @qmax: number of queues being requested - * @qbase: q base at which queues are allocated - * @raw_data: output raw message to be sent - * - * Return: 0 : success and < 0: failure - *****************************************************************************/ -int qdma_mbox_compose_vf_qreq(uint16_t func_id, - uint16_t qmax, int qbase, uint32_t *raw_data); - -/*****************************************************************************/ -/** - * qdma_mbox_compose_vf_notify_qadd(): compose message to notify queue add - * - * @func_id: destination function id - * @qid_hw: number of queues being requested - * @q_type: direction of the of queue - * @raw_data: output raw message to be sent - * - * Return: 0 : success and < 0: failure - *****************************************************************************/ -int qdma_mbox_compose_vf_notify_qadd(uint16_t func_id, - uint16_t qid_hw, - enum qdma_dev_q_type q_type, - uint32_t *raw_data); - -/*****************************************************************************/ -/** - * qdma_mbox_compose_vf_notify_qdel(): compose message to notify queue delete - * - * @func_id: destination function id - * @qid_hw: number of queues being requested - * @q_type: direction of the of queue - * @raw_data: output raw message to be sent - * - * Return: 0 : success and < 0: failure - *****************************************************************************/ -int qdma_mbox_compose_vf_notify_qdel(uint16_t func_id, - uint16_t qid_hw, - enum qdma_dev_q_type q_type, - uint32_t *raw_data); - -/*****************************************************************************/ -/** - * qdma_mbox_compose_vf_notify_qdel(): compose message to get the active - * queue count - * - * @func_id: destination function id - * @raw_data: output raw message to be sent - * - * Return: 0 : success and < 0: failure - *****************************************************************************/ -int qdma_mbox_compose_vf_get_device_active_qcnt(uint16_t func_id, - uint32_t *raw_data); - -/*****************************************************************************/ -/** - * qdma_mbox_compose_vf_fmap_prog(): handles the raw message received - * - * @func_id: destination function id - * @qmax: number of queues being requested - * @qbase: q base at which queues are allocated - * @raw_data: output raw message to be sent - * - * Return: 0 : success and < 0: failure - *****************************************************************************/ -int qdma_mbox_compose_vf_fmap_prog(uint16_t func_id, - uint16_t qmax, int qbase, - uint32_t *raw_data); - -/*****************************************************************************/ -/** - * qdma_mbox_compose_vf_qctxt_write(): compose queue configuration data for - * compose and program - * - * @func_id: destination function id - * @qid_hw: HW queue for which the context has to be read - * @st: is st mode - * @c2h: is c2h direction - * @cmpt_ctxt_type: completion context type - * @descq_conf: pointer to queue config data structure - * @raw_data: output raw message to be sent - * - * Return: 0 : success and < 0: failure - *****************************************************************************/ -int qdma_mbox_compose_vf_qctxt_write(uint16_t func_id, - uint16_t qid_hw, uint8_t st, uint8_t c2h, - enum mbox_cmpt_ctxt_type cmpt_ctxt_type, - struct mbox_descq_conf *descq_conf, - uint32_t *raw_data); - -/*****************************************************************************/ -/** - * qdma_mbox_compose_vf_qctxt_read(): compose message to read context data of a - * queue - * - * @func_id: destination function id - * @qid_hw: HW queue for which the context has to be read - * @st: is st mode - * @c2h: is c2h direction - * @cmpt_ctxt_type: completion context type - * @raw_data: output raw message to be sent - * - * Return: 0 : success and < 0: failure - *****************************************************************************/ -int qdma_mbox_compose_vf_qctxt_read(uint16_t func_id, - uint16_t qid_hw, uint8_t st, uint8_t c2h, - enum mbox_cmpt_ctxt_type cmpt_ctxt_type, - uint32_t *raw_data); - -/*****************************************************************************/ -/** - * qdma_mbox_compose_vf_qctxt_invalidate(): compose queue context invalidate - * message - * - * @func_id: destination function id - * @qid_hw: HW queue for which the context has to be invalidated - * @st: is st mode - * @c2h: is c2h direction - * @cmpt_ctxt_type: completion context type - * @raw_data: output raw message to be sent - * - * Return: 0 : success and < 0: failure - *****************************************************************************/ -int qdma_mbox_compose_vf_qctxt_invalidate(uint16_t func_id, - uint16_t qid_hw, uint8_t st, uint8_t c2h, - enum mbox_cmpt_ctxt_type cmpt_ctxt_type, - uint32_t *raw_data); - -/*****************************************************************************/ -/** - * qdma_mbox_compose_vf_qctxt_clear(): compose queue context clear message - * - * @func_id: destination function id - * @qid_hw: HW queue for which the context has to be cleared - * @st: is st mode - * @c2h: is c2h direction - * @cmpt_ctxt_type: completion context type - * @raw_data: output raw message to be sent - * - * Return: 0 : success and < 0: failure - *****************************************************************************/ -int qdma_mbox_compose_vf_qctxt_clear(uint16_t func_id, - uint16_t qid_hw, uint8_t st, uint8_t c2h, - enum mbox_cmpt_ctxt_type cmpt_ctxt_type, - uint32_t *raw_data); - -/*****************************************************************************/ -/** - * qdma_mbox_compose_csr_read(): compose message to read csr info - * - * @func_id: destination function id - * @raw_data: output raw message to be sent - * - * Return: 0 : success and < 0: failure - *****************************************************************************/ -int qdma_mbox_compose_csr_read(uint16_t func_id, - uint32_t *raw_data); - -/*****************************************************************************/ -/** - * qdma_mbox_compose_reg_read(): compose message to read the register values - * - * @func_id: destination function id - * @group_num: group number for the registers to read - * @raw_data: output raw message to be sent - * - * Return: 0 : success and < 0: failure - *****************************************************************************/ -int qdma_mbox_compose_reg_read(uint16_t func_id, uint16_t group_num, - uint32_t *raw_data); - -/*****************************************************************************/ -/** - * qdma_mbox_compose_vf_intr_ctxt_write(): compose interrupt ring context - * programming message - * - * @func_id: destination function id - * @intr_ctxt: pointer to interrupt context data structure - * @raw_data: output raw message to be sent - * - * Return: 0 : success and < 0: failure - *****************************************************************************/ -int qdma_mbox_compose_vf_intr_ctxt_write(uint16_t func_id, - struct mbox_msg_intr_ctxt *intr_ctxt, - uint32_t *raw_data); - -/*****************************************************************************/ -/** - * qdma_mbox_compose_vf_intr_ctxt_read(): handles the raw message received - * - * @func_id: destination function id - * @intr_ctxt: pointer to interrupt context data structure - * @raw_data: output raw message to be sent - * - * Return: 0 : success and < 0: failure - *****************************************************************************/ -int qdma_mbox_compose_vf_intr_ctxt_read(uint16_t func_id, - struct mbox_msg_intr_ctxt *intr_ctxt, - uint32_t *raw_data); - -/*****************************************************************************/ -/** - * qdma_mbox_compose_vf_intr_ctxt_clear(): compose interrupt ring context - * clear message - * - * @func_id: destination function id - * @intr_ctxt: pointer to interrupt context data structure - * @raw_data: output raw message to be sent - * - * Return: 0 : success and < 0: failure - *****************************************************************************/ -int qdma_mbox_compose_vf_intr_ctxt_clear(uint16_t func_id, - struct mbox_msg_intr_ctxt *intr_ctxt, - uint32_t *raw_data); - -/*****************************************************************************/ -/** - * qdma_mbox_compose_vf_qctxt_invalidate(): compose interrupt ring context - * invalidate message - * - * @func_id: destination function id - * @intr_ctxt: pointer to interrupt context data structure - * @raw_data: output raw message to be sent - * - * Return: 0 : success and < 0: failure - *****************************************************************************/ -int qdma_mbox_compose_vf_intr_ctxt_invalidate(uint16_t func_id, - struct mbox_msg_intr_ctxt *intr_ctxt, - uint32_t *raw_data); - -/*****************************************************************************/ -/** - * qdma_mbox_is_msg_response(): check if the received msg opcode is response - * sent message opcode - * - * @send_data: mbox message sent - * @rcv_data: mbox message recieved - * - * Return: 1 : match and 0: does not match - *****************************************************************************/ -uint8_t qdma_mbox_is_msg_response(uint32_t *send_data, uint32_t *rcv_data); - -/*****************************************************************************/ -/** - * qdma_mbox_vf_response_status(): return the response received for the sent msg - * - * @rcv_data: mbox message recieved - * - * Return: response status received to the sent message - *****************************************************************************/ -int qdma_mbox_vf_response_status(uint32_t *rcv_data); - -/*****************************************************************************/ -/** - * qdma_mbox_vf_func_id_get(): return the vf function id - * - * @rcv_data: mbox message recieved - * @is_vf: is VF mbox - * - * Return: vf function id - *****************************************************************************/ -uint8_t qdma_mbox_vf_func_id_get(uint32_t *rcv_data, uint8_t is_vf); - -int qdma_mbox_vf_active_queues_get(uint32_t *rcv_data, - enum qdma_dev_q_type q_type); - -/*****************************************************************************/ -/** - * qdma_mbox_vf_parent_func_id_get(): return the vf parent function id - * - * @rcv_data: mbox message recieved - * - * Return: vf function id - *****************************************************************************/ -uint8_t qdma_mbox_vf_parent_func_id_get(uint32_t *rcv_data); - -/*****************************************************************************/ -/** - * qdma_mbox_vf_dev_info_get(): get dev info from received message - * - * @rcv_data: mbox message recieved - * @dev_cap: device capability information - * @dma_device_index: DMA Identifier to be read using the mbox. - * - * Return: response status with dev info received to the sent message - *****************************************************************************/ -int qdma_mbox_vf_dev_info_get(uint32_t *rcv_data, - struct qdma_dev_attributes *dev_cap, - uint32_t *dma_device_index); - -/*****************************************************************************/ -/** - * qdma_mbox_vf_qinfo_get(): get qinfo from received message - * - * @rcv_data: mbox message recieved - * @qmax: number of queues - * @qbase: q base at which queues are allocated - * - * Return: response status received to the sent message - *****************************************************************************/ -int qdma_mbox_vf_qinfo_get(uint32_t *rcv_data, int *qbase, uint16_t *qmax); - -/*****************************************************************************/ -/** - * qdma_mbox_vf_csr_get(): get csr info from received message - * - * @rcv_data: mbox message recieved - * @csr: pointer to the csr info - * - * Return: response status received to the sent message - *****************************************************************************/ -int qdma_mbox_vf_csr_get(uint32_t *rcv_data, struct qdma_csr_info *csr); - -/*****************************************************************************/ -/** - * qdma_mbox_vf_reg_list_get(): get reg info from received message - * - * @rcv_data: mbox message recieved - * @num_regs: number of register read - * @reg_list: pointer to the register info - * - * Return: response status received to the sent message - *****************************************************************************/ -int qdma_mbox_vf_reg_list_get(uint32_t *rcv_data, - uint16_t *num_regs, struct qdma_reg_data *reg_list); - -/*****************************************************************************/ -/** - * qdma_mbox_vf_context_get(): get queue context info from received message - * - * @rcv_data: mbox message recieved - * @ctxt: pointer to the queue context info - * - * Return: response status received to the sent message - *****************************************************************************/ -int qdma_mbox_vf_context_get(uint32_t *rcv_data, - struct qdma_descq_context *ctxt); - -/*****************************************************************************/ -/** - * qdma_mbox_vf_context_get(): get intr context info from received message - * - * @rcv_data: mbox message recieved - * @ctxt: pointer to the intr context info - * - * Return: response status received to the sent message - *****************************************************************************/ -int qdma_mbox_vf_intr_context_get(uint32_t *rcv_data, - struct mbox_msg_intr_ctxt *ictxt); - - -/*****************************************************************************/ -/** - * qdma_mbox_pf_hw_clear_ack() - clear the HW ack - * - * @dev_hndl: device handle - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -void qdma_mbox_pf_hw_clear_ack(void *dev_hndl); - -/*****************************************************************************/ -/** - * qdma_mbox_send() - function to send raw data via qdma mailbox - * - * @dev_hndl: device handle - * @is_vf: Whether PF or VF - * @raw_data: pointer to message being sent - * - * The function sends the raw_data to the outgoing mailbox memory and if PF, - * then assert the acknowledge status register bit. - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -int qdma_mbox_send(void *dev_hndl, uint8_t is_vf, uint32_t *raw_data); - -/*****************************************************************************/ -/** - * qdma_mbox_rcv() - function to receive raw data via qdma mailbox - * - * @dev_hndl: device handle - * @is_vf: Whether PF or VF - * @raw_data: pointer to the message being received - * - * The function receives the raw_data from the incoming mailbox memory and - * then acknowledge the sender by setting msg_rcv field in the command - * register. - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -int qdma_mbox_rcv(void *dev_hndl, uint8_t is_vf, uint32_t *raw_data); - -/*****************************************************************************/ -/** - * qdma_mbox_enable_interrupts() - Enable the QDMA mailbox interrupt - * - * @dev_hndl: pointer to xlnx_dma_dev - * @is_vf: Whether PF or VF - * - * @return none - *****************************************************************************/ -void qdma_mbox_enable_interrupts(void *dev_hndl, uint8_t is_vf); - -/*****************************************************************************/ -/** - * qdma_mbox_disable_interrupts() - Disable the QDMA mailbox interrupt - * - * @dev_hndl: pointer to xlnx_dma_dev - * @is_vf: Whether PF or VF - * - * @return none - *****************************************************************************/ -void qdma_mbox_disable_interrupts(void *dev_hndl, uint8_t is_vf); - -/*****************************************************************************/ -/** - * qdma_mbox_vf_rcv_msg_handler(): handles the raw message received in VF - * - * @rcv_msg: received raw message - * @resp_msg: raw response message - * - * Return: 0 : success and < 0: failure - *****************************************************************************/ -int qdma_mbox_vf_rcv_msg_handler(uint32_t *rcv_msg, uint32_t *resp_msg); - -/*****************************************************************************/ -/** - * qdma_mbox_out_status(): - * - * @dev_hndl: pointer to xlnx_dma_dev - * @is_vf: Whether PF or VF - * - * Return: 0 if MBOX outbox is empty, 1 if MBOX is not empty - *****************************************************************************/ -uint8_t qdma_mbox_out_status(void *dev_hndl, uint8_t is_vf); - -#ifdef __cplusplus -} -#endif - -#endif /* __QDMA_MBOX_PROTOCOL_H_ */ diff --git a/QDMA/linux-kernel/driver/libqdma/qdma_access/qdma_platform.h b/QDMA/linux-kernel/driver/libqdma/qdma_access/qdma_platform.h deleted file mode 100755 index 996b89168..000000000 --- a/QDMA/linux-kernel/driver/libqdma/qdma_access/qdma_platform.h +++ /dev/null @@ -1,177 +0,0 @@ -/* - * Copyright (c) 2019-2022, Xilinx, Inc. All rights reserved. - * Copyright (c) 2022, Advanced Micro Devices, Inc. All rights reserved. - * - * This source code is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * The full GNU General Public License is included in this distribution in - * the file called "COPYING". - */ - -#ifndef __QDMA_PLATFORM_H_ -#define __QDMA_PLATFORM_H_ - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * DOC: QDMA platform specific interface definitions - * - * Header file *qdma_platform_env.h* defines function signatures that are - * required to be implemented by platform specific drivers. - */ - -#include "qdma_access_common.h" - -/*****************************************************************************/ -/** - * qdma_calloc(): allocate memory and initialize with 0 - * - * @num_blocks: number of blocks of contiguous memory of @size - * @size: size of each chunk of memory - * - * Return: pointer to the memory block created on success and NULL on failure - *****************************************************************************/ -void *qdma_calloc(uint32_t num_blocks, uint32_t size); - -/*****************************************************************************/ -/** - * qdma_memfree(): free the memory - * - * @memptr: pointer to the memory block - * - * Return: None - *****************************************************************************/ -void qdma_memfree(void *memptr); - -/*****************************************************************************/ -/** - * qdma_resource_lock_init() - Init lock to access resource management APIs - * - * @return None - *****************************************************************************/ -int qdma_resource_lock_init(void); - -/*****************************************************************************/ -/** - * qdma_resource_lock_take() - take lock to access resource management APIs - * - * @return None - *****************************************************************************/ -void qdma_resource_lock_take(void); - -/*****************************************************************************/ -/** - * qdma_resource_lock_give() - release lock after accessing resource management - * APIs - * - * @return None - *****************************************************************************/ -void qdma_resource_lock_give(void); - -/*****************************************************************************/ -/** - * qdma_reg_write() - Register write API. - * - * @dev_hndl: device handle - * @reg_offst: QDMA Config bar register offset to write - * @val: value to be written - * - * Return: Nothing - *****************************************************************************/ -void qdma_reg_write(void *dev_hndl, uint32_t reg_offst, uint32_t val); - -/*****************************************************************************/ -/** - * qdma_reg_read() - Register read API. - * - * @dev_hndl: device handle - * @reg_offst: QDMA Config bar register offset to be read - * - * Return: Value read - *****************************************************************************/ -uint32_t qdma_reg_read(void *dev_hndl, uint32_t reg_offst); - -/*****************************************************************************/ -/** - * qdma_reg_access_lock() - Lock function for Register access - * - * @dev_hndl: device handle - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -int qdma_reg_access_lock(void *dev_hndl); - -/*****************************************************************************/ -/** - * qdma_reg_access_release() - Release function for Register access - * - * @dev_hndl: device handle - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -int qdma_reg_access_release(void *dev_hndl); - -/*****************************************************************************/ -/** - * qdma_udelay() - delay function to be used in the common library - * - * @delay_usec: delay in microseconds - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -void qdma_udelay(uint32_t delay_usec); - -/*****************************************************************************/ -/** - * qdma_get_hw_access() - function to get the qdma_hw_access - * - * @dev_hndl: device handle - * @dev_cap: pointer to hold qdma_hw_access structure - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -void qdma_get_hw_access(void *dev_hndl, struct qdma_hw_access **hw); - -/*****************************************************************************/ -/** - * qdma_strncpy(): copy n size string from source to destination buffer - * - * @memptr: pointer to the memory block - * - * Return: None - *****************************************************************************/ -void qdma_strncpy(char *dest, const char *src, size_t n); - - -/*****************************************************************************/ -/** - * qdma_get_err_code() - function to get the qdma access mapped error code - * - * @acc_err_code: qdma access error code - * - * Return: returns the platform specific error code - *****************************************************************************/ -int qdma_get_err_code(int acc_err_code); - -/*****************************************************************************/ -/** - * qdma_io_wmb() - Write memory barrier for IO device - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -int qdma_io_wmb(void); - -#ifdef __cplusplus -} -#endif - -#endif /* __QDMA_PLATFORM_H_ */ diff --git a/QDMA/linux-kernel/driver/libqdma/qdma_access/qdma_reg_dump.h b/QDMA/linux-kernel/driver/libqdma/qdma_access/qdma_reg_dump.h deleted file mode 100755 index f774bf651..000000000 --- a/QDMA/linux-kernel/driver/libqdma/qdma_access/qdma_reg_dump.h +++ /dev/null @@ -1,83 +0,0 @@ -/* - * Copyright (c) 2019-2022, Xilinx, Inc. All rights reserved. - * Copyright (c) 2022, Advanced Micro Devices, Inc. All rights reserved. - * - * This source code is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * The full GNU General Public License is included in this distribution in - * the file called "COPYING". - */ - -#ifndef __QDMA_REG_DUMP_H__ -#define __QDMA_REG_DUMP_H__ - -#ifdef __cplusplus -extern "C" { -#endif - -#include "qdma_platform_env.h" -#include "qdma_access_common.h" - -#define DEBUGFS_DEV_INFO_SZ (300) - -#define QDMA_REG_NAME_LENGTH 64 -#define DEBUGFS_INTR_CNTX_SZ (2048 * 2) -#define DBGFS_ERR_BUFLEN (64) -#define DEBGFS_LINE_SZ (81) -#define DEBGFS_GEN_NAME_SZ (40) -#define REG_DUMP_SIZE_PER_LINE (256) - -#define MAX_QDMA_CFG_REGS (200) - -#define QDMA_MM_EN_SHIFT 0 -#define QDMA_CMPT_EN_SHIFT 1 -#define QDMA_ST_EN_SHIFT 2 -#define QDMA_MAILBOX_EN_SHIFT 3 - -#define QDMA_MM_MODE (1 << QDMA_MM_EN_SHIFT) -#define QDMA_COMPLETION_MODE (1 << QDMA_CMPT_EN_SHIFT) -#define QDMA_ST_MODE (1 << QDMA_ST_EN_SHIFT) -#define QDMA_MAILBOX (1 << QDMA_MAILBOX_EN_SHIFT) - - -#define QDMA_MM_ST_MODE \ - (QDMA_MM_MODE | QDMA_COMPLETION_MODE | QDMA_ST_MODE) - -#define GET_CAPABILITY_MASK(mm_en, st_en, mm_cmpt_en, mailbox_en) \ - ((mm_en << QDMA_MM_EN_SHIFT) | \ - ((mm_cmpt_en | st_en) << QDMA_CMPT_EN_SHIFT) | \ - (st_en << QDMA_ST_EN_SHIFT) | \ - (mailbox_en << QDMA_MAILBOX_EN_SHIFT)) - - -struct regfield_info { - const char *field_name; - uint32_t field_mask; -}; - -struct xreg_info { - const char *name; - uint32_t addr; - uint32_t repeat; - uint32_t step; - uint8_t shift; - uint8_t len; - uint8_t is_debug_reg; - uint8_t mode; - uint8_t read_type; - uint8_t num_bitfields; - struct regfield_info *bitfields; -}; - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/QDMA/linux-kernel/driver/libqdma/qdma_access/qdma_resource_mgmt.c b/QDMA/linux-kernel/driver/libqdma/qdma_access/qdma_resource_mgmt.c deleted file mode 100755 index 1875ac4dc..000000000 --- a/QDMA/linux-kernel/driver/libqdma/qdma_access/qdma_resource_mgmt.c +++ /dev/null @@ -1,795 +0,0 @@ -/* - * Copyright (c) 2019-2022, Xilinx, Inc. All rights reserved. - * Copyright (c) 2022, Advanced Micro Devices, Inc. All rights reserved. - * - * This source code is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * The full GNU General Public License is included in this distribution in - * the file called "COPYING". - */ - -#include "qdma_resource_mgmt.h" -#include "qdma_platform.h" -#include "qdma_list.h" -#include "qdma_access_errors.h" - -#ifdef ENABLE_WPP_TRACING -#include "qdma_resource_mgmt.tmh" -#endif - -struct qdma_resource_entry { - int qbase; - uint32_t total_q; - struct qdma_list_head node; -}; - -/** per function entry */ -struct qdma_dev_entry { - uint16_t func_id; - uint32_t active_h2c_qcnt; - uint32_t active_c2h_qcnt; - uint32_t active_cmpt_qcnt; - struct qdma_resource_entry entry; -}; - -/** for hodling the qconf_entry structure */ -struct qdma_resource_master { - /** DMA device index this resource belongs to */ - uint32_t dma_device_index; - /** starting pci bus number this resource belongs to */ - uint32_t pci_bus_start; - /** ending pci bus number this resource belongs to */ - uint32_t pci_bus_end; - /** total queue this resource manager handles */ - uint32_t total_q; - /** queue base from which this resource manger handles */ - int qbase; - /** for attaching to master resource list */ - struct qdma_list_head node; - /** for holding device entries */ - struct qdma_list_head dev_list; - /** for holding free resource list */ - struct qdma_list_head free_list; - /** active queue count per resource*/ - uint32_t active_qcnt; -}; - -static QDMA_LIST_HEAD(master_resource_list); - -static struct qdma_resource_master *qdma_find_master_resource_entry( - uint32_t bus_start, uint32_t bus_end) -{ - struct qdma_list_head *entry, *tmp; - - qdma_resource_lock_take(); - qdma_list_for_each_safe(entry, tmp, &master_resource_list) { - struct qdma_resource_master *q_resource = - (struct qdma_resource_master *) - QDMA_LIST_GET_DATA(entry); - - if (q_resource->pci_bus_start == bus_start && - q_resource->pci_bus_end == bus_end) { - qdma_resource_lock_give(); - return q_resource; - } - } - qdma_resource_lock_give(); - - return NULL; -} - -static struct qdma_resource_master *qdma_get_master_resource_entry( - uint32_t dma_device_index) -{ - struct qdma_list_head *entry, *tmp; - - qdma_resource_lock_take(); - qdma_list_for_each_safe(entry, tmp, &master_resource_list) { - struct qdma_resource_master *q_resource = - (struct qdma_resource_master *) - QDMA_LIST_GET_DATA(entry); - - if (q_resource->dma_device_index == dma_device_index) { - qdma_resource_lock_give(); - return q_resource; - } - } - qdma_resource_lock_give(); - - return NULL; -} - -static struct qdma_dev_entry *qdma_get_dev_entry(uint32_t dma_device_index, - uint16_t func_id) -{ - struct qdma_list_head *entry, *tmp; - struct qdma_resource_master *q_resource = - qdma_get_master_resource_entry(dma_device_index); - - if (!q_resource) - return NULL; - - qdma_resource_lock_take(); - qdma_list_for_each_safe(entry, tmp, &q_resource->dev_list) { - struct qdma_dev_entry *dev_entry = (struct qdma_dev_entry *) - QDMA_LIST_GET_DATA(entry); - - if (dev_entry->func_id == func_id) { - qdma_resource_lock_give(); - return dev_entry; - } - } - qdma_resource_lock_give(); - - return NULL; -} - -static struct qdma_resource_entry *qdma_free_entry_create(int q_base, - uint32_t total_q) -{ - struct qdma_resource_entry *entry = (struct qdma_resource_entry *) - qdma_calloc(1, sizeof(struct qdma_resource_master)); - if (entry == NULL) - return NULL; - - entry->total_q = total_q; - entry->qbase = q_base; - - return entry; -} - -static void qdma_submit_to_free_list(struct qdma_dev_entry *dev_entry, - struct qdma_list_head *head) -{ - struct qdma_resource_entry *streach_node = NULL; - struct qdma_list_head *entry, *tmp; - /* create a new node to be added to empty free list */ - struct qdma_resource_entry *new_node = NULL; - - if (!dev_entry->entry.total_q) - return; - - if (qdma_list_is_empty(head)) { - new_node = qdma_free_entry_create(dev_entry->entry.qbase, - dev_entry->entry.total_q); - if (new_node == NULL) - return; - QDMA_LIST_SET_DATA(&new_node->node, new_node); - qdma_list_add_tail(&new_node->node, head); - /* reset device entry q resource params */ - dev_entry->entry.qbase = -1; - dev_entry->entry.total_q = 0; - } else { - qdma_list_for_each_safe(entry, tmp, head) { - struct qdma_resource_entry *node = - (struct qdma_resource_entry *) - QDMA_LIST_GET_DATA(entry); - - /* insert the free slot at appropriate place */ - if ((node->qbase > dev_entry->entry.qbase) || - qdma_list_is_last_entry(entry, head)) { - new_node = qdma_free_entry_create( - dev_entry->entry.qbase, - dev_entry->entry.total_q); - if (new_node == NULL) - return; - QDMA_LIST_SET_DATA(&new_node->node, new_node); - if (node->qbase > dev_entry->entry.qbase) - qdma_list_insert_before(&new_node->node, - &node->node); - else - qdma_list_add_tail(&new_node->node, - head); - /* reset device entry q resource params */ - dev_entry->entry.qbase = -1; - dev_entry->entry.total_q = 0; - break; - } - } - } - - /* de-fragment (merge contiguous resource chunks) if possible */ - qdma_list_for_each_safe(entry, tmp, head) { - struct qdma_resource_entry *node = - (struct qdma_resource_entry *)QDMA_LIST_GET_DATA(entry); - - if (!streach_node) - streach_node = node; - else { - if ((streach_node->qbase + streach_node->total_q) == - (uint32_t)node->qbase) { - streach_node->total_q += node->total_q; - qdma_list_del(&node->node); - qdma_memfree(node); - } else - streach_node = node; - } - } -} - -/** - * qdma_resource_entry() - return the best free list entry node that can - * accommodate the new request - */ -static struct qdma_resource_entry *qdma_get_resource_node(uint32_t qmax, - int qbase, - struct qdma_list_head *free_list_head) -{ - struct qdma_list_head *entry, *tmp; - struct qdma_resource_entry *best_fit_node = NULL; - - /* try to honor requested qbase */ - if (qbase >= 0) { - qdma_list_for_each_safe(entry, tmp, free_list_head) { - struct qdma_resource_entry *node = - (struct qdma_resource_entry *)QDMA_LIST_GET_DATA(entry); - - if ((qbase >= node->qbase) && - (node->qbase + node->total_q) >= - (qbase + qmax)) { - best_fit_node = node; - goto fragment_free_list; - } - } - } - best_fit_node = NULL; - - /* find a best node to accommodate q resource request */ - qdma_list_for_each_safe(entry, tmp, free_list_head) { - struct qdma_resource_entry *node = - (struct qdma_resource_entry *)QDMA_LIST_GET_DATA(entry); - - if (node->total_q >= qmax) { - if (!best_fit_node || (best_fit_node->total_q >= - node->total_q)) { - best_fit_node = node; - qbase = best_fit_node->qbase; - } - } - } - -fragment_free_list: - if (!best_fit_node) - return NULL; - - if ((qbase == best_fit_node->qbase) && - (qmax == best_fit_node->total_q)) - return best_fit_node; - - /* split free resource node accordingly */ - if ((qbase == best_fit_node->qbase) && - (qmax != best_fit_node->total_q)) { - /* - * create an extra node to hold the extra queues from this node - */ - struct qdma_resource_entry *new_entry = NULL; - int lqbase = best_fit_node->qbase + qmax; - uint32_t lqmax = best_fit_node->total_q - qmax; - - new_entry = qdma_free_entry_create(lqbase, lqmax); - if (new_entry == NULL) - return NULL; - QDMA_LIST_SET_DATA(&new_entry->node, new_entry); - qdma_list_insert_after(&new_entry->node, - &best_fit_node->node); - best_fit_node->total_q -= lqmax; - } else if ((qbase > best_fit_node->qbase) && - ((qbase + qmax) == (best_fit_node->qbase + - best_fit_node->total_q))) { - /* - * create an extra node to hold the extra queues from this node - */ - struct qdma_resource_entry *new_entry = NULL; - int lqbase = best_fit_node->qbase; - uint32_t lqmax = qbase - best_fit_node->qbase; - - new_entry = qdma_free_entry_create(lqbase, lqmax); - if (new_entry == NULL) - return NULL; - QDMA_LIST_SET_DATA(&new_entry->node, new_entry); - qdma_list_insert_before(&new_entry->node, - &best_fit_node->node); - best_fit_node->total_q = qmax; - best_fit_node->qbase = qbase; - } else { - /* - * create two extra node to hold the extra queues from this node - */ - struct qdma_resource_entry *new_entry = NULL; - int lqbase = best_fit_node->qbase; - uint32_t lqmax = qbase - best_fit_node->qbase; - - new_entry = qdma_free_entry_create(lqbase, lqmax); - if (new_entry == NULL) - return NULL; - QDMA_LIST_SET_DATA(&new_entry->node, new_entry); - qdma_list_insert_before(&new_entry->node, - &best_fit_node->node); - - best_fit_node->qbase = qbase; - best_fit_node->total_q -= lqmax; - - lqbase = best_fit_node->qbase + qmax; - lqmax = best_fit_node->total_q - qmax; - - new_entry = qdma_free_entry_create(lqbase, lqmax); - if (new_entry == NULL) - return NULL; - QDMA_LIST_SET_DATA(&new_entry->node, new_entry); - qdma_list_insert_after(&new_entry->node, - &best_fit_node->node); - best_fit_node->total_q = qmax; - } - - return best_fit_node; -} - -static int qdma_request_q_resource(struct qdma_dev_entry *dev_entry, - uint32_t new_qmax, int new_qbase, - struct qdma_list_head *free_list_head) -{ - uint32_t qmax = dev_entry->entry.total_q; - int qbase = dev_entry->entry.qbase; - struct qdma_resource_entry *free_entry_node = NULL; - int rv = QDMA_SUCCESS; - - /* submit already allocated queues back to free list before requesting - * new resource - */ - qdma_submit_to_free_list(dev_entry, free_list_head); - - if (!new_qmax) - return 0; - /* check if the request can be accomodated */ - free_entry_node = qdma_get_resource_node(new_qmax, new_qbase, - free_list_head); - if (free_entry_node == NULL) { - /* request cannot be accommodated. Restore the dev_entry */ - free_entry_node = qdma_get_resource_node(qmax, qbase, - free_list_head); - rv = -QDMA_ERR_RM_NO_QUEUES_LEFT; - qdma_log_error("%s: Not enough queues, err:%d\n", __func__, - -QDMA_ERR_RM_NO_QUEUES_LEFT); - if (free_entry_node == NULL) { - dev_entry->entry.qbase = -1; - dev_entry->entry.total_q = 0; - - return rv; - } - } - - dev_entry->entry.qbase = free_entry_node->qbase; - dev_entry->entry.total_q = free_entry_node->total_q; - - qdma_list_del(&free_entry_node->node); - qdma_memfree(free_entry_node); - - return rv; -} - -int qdma_master_resource_create(uint32_t bus_start, uint32_t bus_end, - int q_base, uint32_t total_q, uint32_t *dma_device_index) -{ - struct qdma_resource_master *q_resource; - struct qdma_resource_entry *free_entry; - static int index; - - q_resource = qdma_find_master_resource_entry(bus_start, bus_end); - if (q_resource) { - *dma_device_index = q_resource->dma_device_index; - qdma_log_debug("%s: Resource already created", __func__); - qdma_log_debug("for this device(%d)\n", - q_resource->dma_device_index); - return -QDMA_ERR_RM_RES_EXISTS; - } - - *dma_device_index = index; - - q_resource = (struct qdma_resource_master *)qdma_calloc(1, - sizeof(struct qdma_resource_master)); - if (!q_resource) { - qdma_log_error("%s: no memory for q_resource, err:%d\n", - __func__, - -QDMA_ERR_NO_MEM); - return -QDMA_ERR_NO_MEM; - } - - free_entry = (struct qdma_resource_entry *) - qdma_calloc(1, sizeof(struct qdma_resource_entry)); - if (!free_entry) { - qdma_memfree(q_resource); - qdma_log_error("%s: no memory for free_entry, err:%d\n", - __func__, - -QDMA_ERR_NO_MEM); - return -QDMA_ERR_NO_MEM; - } - - qdma_resource_lock_take(); - q_resource->dma_device_index = index; - q_resource->pci_bus_start = bus_start; - q_resource->pci_bus_end = bus_end; - q_resource->total_q = total_q; - q_resource->qbase = q_base; - qdma_list_init_head(&q_resource->dev_list); - qdma_list_init_head(&q_resource->free_list); - QDMA_LIST_SET_DATA(&q_resource->node, q_resource); - QDMA_LIST_SET_DATA(&q_resource->free_list, q_resource); - qdma_list_add_tail(&q_resource->node, &master_resource_list); - - - free_entry->total_q = total_q; - free_entry->qbase = q_base; - QDMA_LIST_SET_DATA(&free_entry->node, free_entry); - qdma_list_add_tail(&free_entry->node, &q_resource->free_list); - qdma_resource_lock_give(); - - qdma_log_debug("%s: New master resource created at %d", - __func__, index); - ++index; - - return QDMA_SUCCESS; -} - -void qdma_master_resource_destroy(uint32_t dma_device_index) -{ - struct qdma_resource_master *q_resource = - qdma_get_master_resource_entry(dma_device_index); - struct qdma_list_head *entry, *tmp; - - if (!q_resource) - return; - qdma_resource_lock_take(); - if (!qdma_list_is_empty(&q_resource->dev_list)) { - qdma_resource_lock_give(); - return; - } - qdma_list_for_each_safe(entry, tmp, &q_resource->free_list) { - struct qdma_resource_entry *free_entry = - (struct qdma_resource_entry *) - QDMA_LIST_GET_DATA(entry); - - qdma_list_del(&free_entry->node); - qdma_memfree(free_entry); - } - qdma_list_del(&q_resource->node); - qdma_memfree(q_resource); - qdma_resource_lock_give(); -} - - -int qdma_dev_entry_create(uint32_t dma_device_index, uint16_t func_id) -{ - struct qdma_resource_master *q_resource = - qdma_get_master_resource_entry(dma_device_index); - struct qdma_dev_entry *dev_entry; - - if (!q_resource) { - qdma_log_error("%s: Queue resource not found, err: %d\n", - __func__, - -QDMA_ERR_RM_RES_NOT_EXISTS); - return -QDMA_ERR_RM_RES_NOT_EXISTS; - } - - dev_entry = qdma_get_dev_entry(dma_device_index, func_id); - if (!dev_entry) { - qdma_resource_lock_take(); - dev_entry = (struct qdma_dev_entry *) - qdma_calloc(1, sizeof(struct qdma_dev_entry)); - if (dev_entry == NULL) { - qdma_resource_lock_give(); - qdma_log_error("%s: Insufficient memory, err:%d\n", - __func__, - -QDMA_ERR_NO_MEM); - return -QDMA_ERR_NO_MEM; - } - dev_entry->func_id = func_id; - dev_entry->entry.qbase = -1; - dev_entry->entry.total_q = 0; - QDMA_LIST_SET_DATA(&dev_entry->entry.node, dev_entry); - qdma_list_add_tail(&dev_entry->entry.node, - &q_resource->dev_list); - qdma_resource_lock_give(); - qdma_log_info("%s: Created the dev entry successfully\n", - __func__); - } else { - qdma_log_error("%s: Dev entry already created, err = %d\n", - __func__, - -QDMA_ERR_RM_DEV_EXISTS); - return -QDMA_ERR_RM_DEV_EXISTS; - } - - return QDMA_SUCCESS; -} - -void qdma_dev_entry_destroy(uint32_t dma_device_index, uint16_t func_id) -{ - struct qdma_resource_master *q_resource = - qdma_get_master_resource_entry(dma_device_index); - struct qdma_dev_entry *dev_entry; - - if (!q_resource) { - qdma_log_error("%s: Queue resource not found.\n", __func__); - return; - } - - dev_entry = qdma_get_dev_entry(dma_device_index, func_id); - if (!dev_entry) { - qdma_log_error("%s: Dev entry not found\n", __func__); - return; - } - qdma_resource_lock_take(); - qdma_submit_to_free_list(dev_entry, &q_resource->free_list); - - qdma_list_del(&dev_entry->entry.node); - qdma_memfree(dev_entry); - qdma_resource_lock_give(); -} - -int qdma_dev_update(uint32_t dma_device_index, uint16_t func_id, - uint32_t qmax, int *qbase) -{ - struct qdma_resource_master *q_resource = - qdma_get_master_resource_entry(dma_device_index); - struct qdma_dev_entry *dev_entry; - int rv; - - if (!q_resource) { - qdma_log_error("%s: Queue resource not found, err: %d\n", - __func__, -QDMA_ERR_RM_RES_NOT_EXISTS); - return -QDMA_ERR_RM_RES_NOT_EXISTS; - } - - dev_entry = qdma_get_dev_entry(dma_device_index, func_id); - - if (!dev_entry) { - qdma_log_error("%s: Dev Entry not found, err: %d\n", - __func__, - -QDMA_ERR_RM_DEV_NOT_EXISTS); - return -QDMA_ERR_RM_DEV_NOT_EXISTS; - } - - qdma_resource_lock_take(); - - /* if any active queue on device, no more new qmax - * configuration allowed - */ - if (dev_entry->active_h2c_qcnt || - dev_entry->active_c2h_qcnt || - dev_entry->active_cmpt_qcnt) { - qdma_resource_lock_give(); - qdma_log_error("%s: Qs active. Config blocked, err: %d\n", - __func__, -QDMA_ERR_RM_QMAX_CONF_REJECTED); - return -QDMA_ERR_RM_QMAX_CONF_REJECTED; - } - - rv = qdma_request_q_resource(dev_entry, qmax, *qbase, - &q_resource->free_list); - - *qbase = dev_entry->entry.qbase; - qdma_resource_lock_give(); - - - return rv; -} - -int qdma_dev_qinfo_get(uint32_t dma_device_index, uint16_t func_id, - int *qbase, uint32_t *qmax) -{ - struct qdma_resource_master *q_resource = - qdma_get_master_resource_entry(dma_device_index); - struct qdma_dev_entry *dev_entry; - - if (!q_resource) { - qdma_log_error("%s: Queue resource not found, err: %d\n", - __func__, -QDMA_ERR_RM_RES_NOT_EXISTS); - return -QDMA_ERR_RM_RES_NOT_EXISTS; - } - - dev_entry = qdma_get_dev_entry(dma_device_index, func_id); - - if (!dev_entry) { - qdma_log_debug("%s: Dev Entry not created yet\n", __func__); - return -QDMA_ERR_RM_DEV_NOT_EXISTS; - } - - qdma_resource_lock_take(); - *qbase = dev_entry->entry.qbase; - *qmax = dev_entry->entry.total_q; - qdma_resource_lock_give(); - - return QDMA_SUCCESS; -} - -enum qdma_dev_q_range qdma_dev_is_queue_in_range(uint32_t dma_device_index, - uint16_t func_id, - uint32_t qid_hw) -{ - struct qdma_resource_master *q_resource = - qdma_get_master_resource_entry(dma_device_index); - struct qdma_dev_entry *dev_entry; - uint32_t qmax; - - if (!q_resource) { - qdma_log_error("%s: Queue resource not found, err: %d\n", - __func__, -QDMA_ERR_RM_RES_NOT_EXISTS); - return QDMA_DEV_Q_OUT_OF_RANGE; - } - - dev_entry = qdma_get_dev_entry(dma_device_index, func_id); - - if (!dev_entry) { - qdma_log_error("%s: Dev entry not found, err: %d\n", - __func__, -QDMA_ERR_RM_DEV_NOT_EXISTS); - return QDMA_DEV_Q_OUT_OF_RANGE; - } - - qdma_resource_lock_take(); - qmax = dev_entry->entry.qbase + dev_entry->entry.total_q; - if (dev_entry->entry.total_q && (qid_hw < qmax) && - ((int)qid_hw >= dev_entry->entry.qbase)) { - qdma_resource_lock_give(); - return QDMA_DEV_Q_IN_RANGE; - } - qdma_resource_lock_give(); - - return QDMA_DEV_Q_OUT_OF_RANGE; -} - -int qdma_dev_increment_active_queue(uint32_t dma_device_index, uint16_t func_id, - enum qdma_dev_q_type q_type) -{ - struct qdma_resource_master *q_resource = - qdma_get_master_resource_entry(dma_device_index); - struct qdma_dev_entry *dev_entry; - int rv = QDMA_SUCCESS; - uint32_t *active_qcnt = NULL; - - if (!q_resource) { - qdma_log_error("%s: Queue resource not found, err: %d\n", - __func__, -QDMA_ERR_RM_RES_NOT_EXISTS); - return -QDMA_ERR_RM_RES_NOT_EXISTS; - } - - dev_entry = qdma_get_dev_entry(dma_device_index, func_id); - - if (!dev_entry) { - qdma_log_error("%s: Dev Entry not found, err: %d\n", - __func__, - -QDMA_ERR_RM_DEV_NOT_EXISTS); - return -QDMA_ERR_RM_DEV_NOT_EXISTS; - } - - qdma_resource_lock_take(); - switch (q_type) { - case QDMA_DEV_Q_TYPE_H2C: - active_qcnt = &dev_entry->active_h2c_qcnt; - break; - case QDMA_DEV_Q_TYPE_C2H: - active_qcnt = &dev_entry->active_c2h_qcnt; - break; - case QDMA_DEV_Q_TYPE_CMPT: - active_qcnt = &dev_entry->active_cmpt_qcnt; - break; - default: - rv = -QDMA_ERR_RM_DEV_NOT_EXISTS; - } - - if (active_qcnt && (dev_entry->entry.total_q < ((*active_qcnt) + 1))) { - qdma_resource_lock_give(); - return -QDMA_ERR_RM_NO_QUEUES_LEFT; - } - - if (active_qcnt) { - *active_qcnt = (*active_qcnt) + 1; - q_resource->active_qcnt++; - } - qdma_resource_lock_give(); - - return rv; -} - - -int qdma_dev_decrement_active_queue(uint32_t dma_device_index, uint16_t func_id, - enum qdma_dev_q_type q_type) -{ - struct qdma_resource_master *q_resource = - qdma_get_master_resource_entry(dma_device_index); - struct qdma_dev_entry *dev_entry; - int rv = QDMA_SUCCESS; - - if (!q_resource) { - qdma_log_error("%s: Queue resource not found, err: %d\n", - __func__, - -QDMA_ERR_RM_RES_NOT_EXISTS); - return -QDMA_ERR_RM_RES_NOT_EXISTS; - } - - dev_entry = qdma_get_dev_entry(dma_device_index, func_id); - - if (!dev_entry) { - qdma_log_error("%s: Dev entry not found, err: %d\n", - __func__, -QDMA_ERR_RM_DEV_NOT_EXISTS); - return -QDMA_ERR_RM_DEV_NOT_EXISTS; - } - - qdma_resource_lock_take(); - switch (q_type) { - case QDMA_DEV_Q_TYPE_H2C: - if (dev_entry->active_h2c_qcnt) - dev_entry->active_h2c_qcnt--; - break; - case QDMA_DEV_Q_TYPE_C2H: - if (dev_entry->active_c2h_qcnt) - dev_entry->active_c2h_qcnt--; - break; - case QDMA_DEV_Q_TYPE_CMPT: - if (dev_entry->active_cmpt_qcnt) - dev_entry->active_cmpt_qcnt--; - break; - default: - rv = -QDMA_ERR_RM_DEV_NOT_EXISTS; - } - q_resource->active_qcnt--; - qdma_resource_lock_give(); - - return rv; -} - -uint32_t qdma_get_active_queue_count(uint32_t dma_device_index) -{ - struct qdma_resource_master *q_resource = - qdma_get_master_resource_entry(dma_device_index); - uint32_t q_cnt; - - if (!q_resource) - return QDMA_SUCCESS; - - qdma_resource_lock_take(); - q_cnt = q_resource->active_qcnt; - qdma_resource_lock_give(); - - return q_cnt; -} - -int qdma_get_device_active_queue_count(uint32_t dma_device_index, - uint16_t func_id, - enum qdma_dev_q_type q_type) -{ - struct qdma_resource_master *q_resource = - qdma_get_master_resource_entry(dma_device_index); - struct qdma_dev_entry *dev_entry; - uint32_t dev_active_qcnt = 0; - - if (!q_resource) - return -QDMA_ERR_RM_RES_NOT_EXISTS; - - dev_entry = qdma_get_dev_entry(dma_device_index, func_id); - - if (!dev_entry) - return -QDMA_ERR_RM_DEV_NOT_EXISTS; - - qdma_resource_lock_take(); - switch (q_type) { - case QDMA_DEV_Q_TYPE_H2C: - dev_active_qcnt = dev_entry->active_h2c_qcnt; - break; - case QDMA_DEV_Q_TYPE_C2H: - dev_active_qcnt = dev_entry->active_c2h_qcnt; - break; - case QDMA_DEV_Q_TYPE_CMPT: - dev_active_qcnt = dev_entry->active_cmpt_qcnt; - break; - default: - dev_active_qcnt = 0; - } - qdma_resource_lock_give(); - - return dev_active_qcnt; -} diff --git a/QDMA/linux-kernel/driver/libqdma/qdma_access/qdma_resource_mgmt.h b/QDMA/linux-kernel/driver/libqdma/qdma_access/qdma_resource_mgmt.h deleted file mode 100755 index 5c53c4765..000000000 --- a/QDMA/linux-kernel/driver/libqdma/qdma_access/qdma_resource_mgmt.h +++ /dev/null @@ -1,214 +0,0 @@ -/* - * Copyright (c) 2019-2022, Xilinx, Inc. All rights reserved. - * Copyright (c) 2022, Advanced Micro Devices, Inc. All rights reserved. - * - * This source code is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * The full GNU General Public License is included in this distribution in - * the file called "COPYING". - */ - -#ifndef __QDMA_RESOURCE_MGMT_H_ -#define __QDMA_RESOURCE_MGMT_H_ - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * DOC: QDMA resource management interface definitions - * - * Header file *qdma_resource_mgmt.h* defines data structures and function - * signatures exported for QDMA queue management. - */ - -#include "qdma_platform_env.h" -#include "qdma_access_export.h" - -/** - * enum qdma_dev_q_range: Q ranage check - */ -enum qdma_dev_q_range { - /** @QDMA_DEV_Q_IN_RANGE: Q belongs to dev */ - QDMA_DEV_Q_IN_RANGE, - /** @QDMA_DEV_Q_OUT_OF_RANGE: Q does not belong to dev */ - QDMA_DEV_Q_OUT_OF_RANGE, - /** @QDMA_DEV_Q_RANGE_MAX: total Q validity states */ - QDMA_DEV_Q_RANGE_MAX -}; - -/*****************************************************************************/ -/** - * qdma_master_resource_create(): create the master q resource - * - * @bus_start: Bus number of the device i.e. pdev->bus->number - * @bus_end: Ending bus number i.e. the subordinate bus number of the - * parent bridge - * @q_base: base from which this master resource needs to be created - * @total_q: total queues in this master resource - * @dma_device_index: DMA device identifier assigned by resource manager to - * track the number of devices - * - * A master resource per driver per board is created to manage the queues - * allocated to this driver. - * - * Return: 0 : success and < 0: failure - *****************************************************************************/ -int qdma_master_resource_create(uint32_t bus_start, uint32_t bus_end, - int q_base, uint32_t total_q, uint32_t *dma_device_index); - -/*****************************************************************************/ -/** - * qdma_master_resource_destroy(): destroy the master q resource - * - * @dma_device_index: DMA device identifier this master resource belongs to - * - * Return: None - *****************************************************************************/ -void qdma_master_resource_destroy(uint32_t dma_device_index); - -/*****************************************************************************/ -/** - * qdma_dev_entry_create(): create a device entry for @func_id - * - * @dma_device_index: DMA device identifier that this device belongs to - * @func_id: device identification id - * - * A device entry is to be created on every function probe. - * - * Return: 0 : success and < 0: failure - *****************************************************************************/ -int qdma_dev_entry_create(uint32_t dma_device_index, uint16_t func_id); - -/*****************************************************************************/ -/** - * qdma_dev_entry_destroy(): destroy device entry for @func_id - * - * @dma_device_index: DMA device identifier that this device belongs to - * @func_id: device identification id - * - * Return: None - *****************************************************************************/ -void qdma_dev_entry_destroy(uint32_t dma_device_index, uint16_t func_id); - -/*****************************************************************************/ -/** - * qdma_dev_update(): update qmax for the device - * - * @dma_device_index: DMA device identifier that this device belongs to - * @func_id: device identification id - * @dev_type: device type - * @qmax: qmax for this device - * @qbase: output qbase for this device - * - * This API is to be called for update request of qmax of any function. - * - * Return: 0 : success and < 0: failure - *****************************************************************************/ -int qdma_dev_update(uint32_t dma_device_index, uint16_t func_id, - uint32_t qmax, int *qbase); - -/*****************************************************************************/ -/** - * qdma_dev_qinfo_get(): get device info - * - * @dma_device_index: DMA device identifier that this device belongs to - * @func_id: device identification id - * @dev_type: device type - * @qmax: output qmax for this device - * @qbase: output qbase for this device - * - * This API can be used get the qbase and qmax for any function - * - * Return: 0 : success and < 0: failure - *****************************************************************************/ -int qdma_dev_qinfo_get(uint32_t dma_device_index, uint16_t func_id, - int *qbase, uint32_t *qmax); - -/*****************************************************************************/ -/** - * qdma_dev_is_queue_in_range(): check if queue belongs to this device - * - * @dma_device_index: DMA device identifier that this device belongs to - * @func_id: device identification id - * @qid_hw: hardware queue id - * - * This API checks if the queue ID is in valid range for function specified - * - * Return: @QDMA_DEV_Q_IN_RANGE : valid and - * @QDMA_DEV_Q_OUT_OF_RANGE: invalid - *****************************************************************************/ -enum qdma_dev_q_range qdma_dev_is_queue_in_range(uint32_t dma_device_index, - uint16_t func_id, - uint32_t qid_hw); - -/*****************************************************************************/ -/** - * qdma_dev_increment_active_queue(): increment active queue count - * - * @dma_device_index: DMA device identifier that this device belongs to - * @func_id: device identification id - * @q_type: Queue type i.e. C2H or H2C or CMPT - * - * This API is used to increment the active queue count of this function - * - * Return: 0 : success and < 0: failure - *****************************************************************************/ -int qdma_dev_increment_active_queue(uint32_t dma_device_index, uint16_t func_id, - enum qdma_dev_q_type q_type); - -/*****************************************************************************/ -/** - * qdma_dev_decrement_active_queue(): increment active queue count - * - * @dma_device_index: DMA device identifier that this device belongs to - * @func_id: device identification id - * @q_type: Queue type i.e. C2H or H2C or CMPT - * - * This API is used to increment the active queue count of this function - * - * Return: 0 : success and < 0: failure - *****************************************************************************/ -int qdma_dev_decrement_active_queue(uint32_t dma_device_index, uint16_t func_id, - enum qdma_dev_q_type q_type); - -/*****************************************************************************/ -/** - * qdma_is_active_queue(): check if any queue is active - * - * @dma_device_index: DMA device identifier that this resource belongs to - * - * This API is used to check if any active queue is present. - * - * Return: active queue count - *****************************************************************************/ -uint32_t qdma_get_active_queue_count(uint32_t dma_device_index); - -/*****************************************************************************/ -/** - * qdma_get_device_active_queue_count(): get device active queue count - * - * @dma_device_index: DMA device identifier that this device belongs to - * @func_id: device identification id - * @q_type: Queue type i.e. C2H or H2C or CMPT - * - * This API is used to get the active queue count of this function - * - * Return: 0 : success and < 0: failure - *****************************************************************************/ -int qdma_get_device_active_queue_count(uint32_t dma_device_index, - uint16_t func_id, - enum qdma_dev_q_type q_type); - -#ifdef __cplusplus -} -#endif - -#endif /* __QDMA_RESOURCE_MGMT_H_ */ diff --git a/QDMA/linux-kernel/driver/libqdma/qdma_access/qdma_soft_access/qdma_soft_access.c b/QDMA/linux-kernel/driver/libqdma/qdma_access/qdma_soft_access/qdma_soft_access.c deleted file mode 100755 index b23a4df57..000000000 --- a/QDMA/linux-kernel/driver/libqdma/qdma_access/qdma_soft_access/qdma_soft_access.c +++ /dev/null @@ -1,6239 +0,0 @@ -/* - * Copyright (c) 2019-2022, Xilinx, Inc. All rights reserved. - * Copyright (c) 2022, Advanced Micro Devices, Inc. All rights reserved. - * - * This source code is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * The full GNU General Public License is included in this distribution in - * the file called "COPYING". - */ - -#include "qdma_soft_access.h" -#include "qdma_soft_reg.h" -#include "qdma_reg_dump.h" - - -#ifdef ENABLE_WPP_TRACING -#include "qdma_soft_access.tmh" -#endif - -/** QDMA Context array size */ -#define QDMA_FMAP_NUM_WORDS 2 -#define QDMA_SW_CONTEXT_NUM_WORDS 5 -#define QDMA_PFETCH_CONTEXT_NUM_WORDS 2 -#define QDMA_CMPT_CONTEXT_NUM_WORDS 5 -#define QDMA_HW_CONTEXT_NUM_WORDS 2 -#define QDMA_CR_CONTEXT_NUM_WORDS 1 -#define QDMA_IND_INTR_CONTEXT_NUM_WORDS 3 -#define QDMA_REG_IND_CTXT_REG_COUNT 8 - - -#define QDMA_REG_GROUP_1_START_ADDR 0x000 -#define QDMA_REG_GROUP_2_START_ADDR 0x400 -#define QDMA_REG_GROUP_3_START_ADDR 0xB00 -#define QDMA_REG_GROUP_4_START_ADDR 0x1014 - -#define QDMA_DEFAULT_PFCH_STOP_THRESH 256 - -static void qdma_hw_st_h2c_err_process(void *dev_hndl); -static void qdma_hw_st_c2h_err_process(void *dev_hndl); -static void qdma_hw_desc_err_process(void *dev_hndl); -static void qdma_hw_trq_err_process(void *dev_hndl); -static void qdma_hw_ram_sbe_err_process(void *dev_hndl); -static void qdma_hw_ram_dbe_err_process(void *dev_hndl); - -static struct xreg_info qdma_config_regs[] = { - - /* QDMA_TRQ_SEL_GLBL1 (0x00000) */ - {"CFG_BLOCK_ID", - 0x00, 1, 0, 0, 0, 0, - QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, 0, NULL}, - {"CFG_BUSDEV", - 0x04, 1, 0, 0, 0, 0, - QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, 0, NULL}, - {"CFG_PCIE_MAX_PL_SZ", - 0x08, 1, 0, 0, 0, 0, - QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, 0, NULL}, - {"CFG_PCIE_MAX_RDRQ_SZ", - 0x0C, 1, 0, 0, 0, 0, - QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, 0, NULL}, - {"CFG_SYS_ID", - 0x10, 1, 0, 0, 0, 0, - QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, 0, NULL}, - {"CFG_MSI_EN", - 0x14, 1, 0, 0, 0, 0, - QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, 0, NULL}, - {"CFG_PCIE_DATA_WIDTH", - 0x18, 1, 0, 0, 0, 0, - QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, 0, NULL}, - {"CFG_PCIE_CTRL", - 0x1C, 1, 0, 0, 0, 0, - QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, 0, NULL}, - {"CFG_AXI_USR_MAX_PL_SZ", - 0x40, 1, 0, 0, 0, 0, - QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, 0, NULL}, - {"CFG_AXI_USR_MAX_RDRQ_SZ", - 0x44, 1, 0, 0, 0, 0, - QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, 0, NULL}, - {"CFG_MISC_CTRL", - 0x4C, 1, 0, 0, 0, 0, - QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, 0, NULL}, - {"CFG_SCRATCH_REG", - 0x80, 8, 0, 0, 0, 0, - QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, 0, NULL}, - {"QDMA_RAM_SBE_MSK_A", - 0xF0, 1, 0, 0, 0, 0, - QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, 0, NULL}, - {"QDMA_RAM_SBE_STS_A", - 0xF4, 1, 0, 0, 0, 0, - QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, 0, NULL}, - {"QDMA_RAM_DBE_MSK_A", - 0xF8, 1, 0, 0, 0, 0, - QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, 0, NULL}, - {"QDMA_RAM_DBE_STS_A", - 0xFC, 1, 0, 0, 0, 0, - QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, 0, NULL}, - - /* QDMA_TRQ_SEL_GLBL2 (0x00100) */ - {"GLBL2_ID", - 0x100, 1, 0, 0, 0, 0, - QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, 0, NULL}, - {"GLBL2_PF_BL_INT", - 0x104, 1, 0, 0, 0, 0, - QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, 0, NULL}, - {"GLBL2_PF_VF_BL_INT", - 0x108, 1, 0, 0, 0, 0, - QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, 0, NULL}, - {"GLBL2_PF_BL_EXT", - 0x10C, 1, 0, 0, 0, 0, - QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, 0, NULL}, - {"GLBL2_PF_VF_BL_EXT", - 0x110, 1, 0, 0, 0, 0, - QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, 0, NULL}, - {"GLBL2_CHNL_INST", - 0x114, 1, 0, 0, 0, 0, - QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, 0, NULL}, - {"GLBL2_CHNL_QDMA", - 0x118, 1, 0, 0, 0, 0, - QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, 0, NULL}, - {"GLBL2_CHNL_STRM", - 0x11C, 1, 0, 0, 0, 0, - QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, 0, NULL}, - {"GLBL2_QDMA_CAP", - 0x120, 1, 0, 0, 0, 0, - QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, 0, NULL}, - {"GLBL2_PASID_CAP", - 0x128, 1, 0, 0, 0, 0, - QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, 0, NULL}, - {"GLBL2_FUNC_RET", - 0x12C, 1, 0, 0, 0, 0, - QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, 0, NULL}, - {"GLBL2_SYS_ID", - 0x130, 1, 0, 0, 0, 0, - QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, 0, NULL}, - {"GLBL2_MISC_CAP", - 0x134, 1, 0, 0, 0, 0, - QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, 0, NULL}, - {"GLBL2_DBG_PCIE_RQ", - 0x1B8, 2, 0, 0, 0, 0, - QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, 0, NULL}, - {"GLBL2_DBG_AXIMM_WR", - 0x1C0, 2, 0, 0, 0, 0, - QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, 0, NULL}, - {"GLBL2_DBG_AXIMM_RD", - 0x1C8, 2, 0, 0, 0, 0, - QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, 0, NULL}, - - /* QDMA_TRQ_SEL_GLBL (0x00200) */ - {"GLBL_RNGSZ", - 0x204, 16, 1, 0, 0, 0, - QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, 0, NULL}, - {"GLBL_ERR_STAT", - 0x248, 1, 0, 0, 0, 0, - QDMA_MM_ST_MODE, QDMA_REG_READ_PF_VF, 0, NULL}, - {"GLBL_ERR_MASK", - 0x24C, 1, 0, 0, 0, 0, - QDMA_MM_ST_MODE, QDMA_REG_READ_PF_VF, 0, NULL}, - {"GLBL_DSC_CFG", - 0x250, 1, 0, 0, 0, 0, - QDMA_MM_ST_MODE, QDMA_REG_READ_PF_VF, 0, NULL}, - {"GLBL_DSC_ERR_STS", - 0x254, 1, 0, 0, 0, 0, - QDMA_MM_ST_MODE, QDMA_REG_READ_PF_VF, 0, NULL}, - {"GLBL_DSC_ERR_MSK", - 0x258, 1, 0, 0, 0, 0, - QDMA_MM_ST_MODE, QDMA_REG_READ_PF_VF, 0, NULL}, - {"GLBL_DSC_ERR_LOG", - 0x25C, 2, 0, 0, 0, 0, - QDMA_MM_ST_MODE, QDMA_REG_READ_PF_VF, 0, NULL}, - {"GLBL_TRQ_ERR_STS", - 0x264, 1, 0, 0, 0, 0, - QDMA_MM_ST_MODE, QDMA_REG_READ_PF_VF, 0, NULL}, - {"GLBL_TRQ_ERR_MSK", - 0x268, 1, 0, 0, 0, 0, - QDMA_MM_ST_MODE, QDMA_REG_READ_PF_VF, 0, NULL}, - {"GLBL_TRQ_ERR_LOG", - 0x26C, 1, 0, 0, 0, 0, - QDMA_MM_ST_MODE, QDMA_REG_READ_PF_VF, 0, NULL}, - {"GLBL_DSC_DBG_DAT", - 0x270, 2, 0, 0, 0, 0, - QDMA_MM_ST_MODE, QDMA_REG_READ_PF_VF, 0, NULL}, - {"GLBL_DSC_ERR_LOG2", - 0x27C, 1, 0, 0, 0, 0, - QDMA_MM_ST_MODE, QDMA_REG_READ_PF_VF, 0, NULL}, - {"GLBL_INTERRUPT_CFG", - 0x288, 1, 0, 0, 0, 0, - QDMA_MM_ST_MODE, QDMA_REG_READ_PF_VF, 0, NULL}, - - /* QDMA_TRQ_SEL_FMAP (0x00400 - 0x7FC) */ - /* TODO: max 256, display 4 for now */ - {"TRQ_SEL_FMAP", - 0x400, 4, 0, 0, 0, 0, - QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, 0, NULL}, - - /* QDMA_TRQ_SEL_IND (0x00800) */ - {"IND_CTXT_DATA", - 0x804, 8, 0, 0, 0, 0, - QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, 0, NULL}, - {"IND_CTXT_MASK", - 0x824, 8, 0, 0, 0, 0, - QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, 0, NULL}, - {"IND_CTXT_CMD", - 0x844, 1, 0, 0, 0, 0, - QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, 0, NULL}, - - /* QDMA_TRQ_SEL_C2H (0x00A00) */ - {"C2H_TIMER_CNT", - 0xA00, 16, 0, 0, 0, 0, - QDMA_COMPLETION_MODE, QDMA_REG_READ_PF_ONLY, 0, NULL}, - {"C2H_CNT_THRESH", - 0xA40, 16, 0, 0, 0, 0, - QDMA_COMPLETION_MODE, QDMA_REG_READ_PF_ONLY, 0, NULL}, - {"C2H_STAT_S_AXIS_C2H_ACCEPTED", - 0xA88, 1, 0, 0, 0, 0, - QDMA_ST_MODE, QDMA_REG_READ_PF_VF, 0, NULL}, - {"C2H_STAT_S_AXIS_CMPT_ACCEPTED", - 0xA8C, 1, 0, 0, 0, 0, - QDMA_ST_MODE, QDMA_REG_READ_PF_VF, 0, NULL}, - {"C2H_STAT_DESC_RSP_PKT_ACCEPTED", - 0xA90, 1, 0, 0, 0, 0, - QDMA_ST_MODE, QDMA_REG_READ_PF_VF, 0, NULL}, - {"C2H_STAT_AXIS_PKG_CMP", - 0xA94, 1, 0, 0, 0, 0, - QDMA_ST_MODE, QDMA_REG_READ_PF_VF, 0, NULL}, - {"C2H_STAT_DESC_RSP_ACCEPTED", - 0xA98, 1, 0, 0, 0, 0, - QDMA_ST_MODE, QDMA_REG_READ_PF_VF, 0, NULL}, - {"C2H_STAT_DESC_RSP_CMP", - 0xA9C, 1, 0, 0, 0, 0, - QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, 0, NULL}, - {"C2H_STAT_WRQ_OUT", - 0xAA0, 1, 0, 0, 0, 0, - QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, 0, NULL}, - {"C2H_STAT_WPL_REN_ACCEPTED", - 0xAA4, 1, 0, 0, 0, 0, - QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, 0, NULL}, - {"C2H_STAT_TOTAL_WRQ_LEN", - 0xAA8, 1, 0, 0, 0, 0, - QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, 0, NULL}, - {"C2H_STAT_TOTAL_WPL_LEN", - 0xAAC, 1, 0, 0, 0, 0, - QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, 0, NULL}, - {"C2H_BUF_SZ", - 0xAB0, 16, 0, 0, 0, 0, - QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, 0, NULL}, - {"C2H_ERR_STAT", - 0xAF0, 1, 0, 0, 0, 0, - QDMA_ST_MODE, QDMA_REG_READ_PF_VF, 0, NULL}, - {"C2H_ERR_MASK", - 0xAF4, 1, 0, 0, 0, 0, - QDMA_ST_MODE, QDMA_REG_READ_PF_VF, 0, NULL}, - {"C2H_FATAL_ERR_STAT", - 0xAF8, 1, 0, 0, 0, 0, - QDMA_ST_MODE, QDMA_REG_READ_PF_VF, 0, NULL}, - {"C2H_FATAL_ERR_MASK", - 0xAFC, 1, 0, 0, 0, 0, - QDMA_ST_MODE, QDMA_REG_READ_PF_VF, 0, NULL}, - {"C2H_FATAL_ERR_ENABLE", - 0xB00, 1, 0, 0, 0, 0, - QDMA_ST_MODE, QDMA_REG_READ_PF_VF, 0, NULL}, - {"GLBL_ERR_INT", - 0xB04, 1, 0, 0, 0, 0, - QDMA_ST_MODE, QDMA_REG_READ_PF_VF, 0, NULL}, - {"C2H_PFCH_CFG", - 0xB08, 1, 0, 0, 0, 0, - QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, 0, NULL}, - {"C2H_INT_TIMER_TICK", - 0xB0C, 1, 0, 0, 0, 0, - QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, 0, NULL}, - {"C2H_STAT_DESC_RSP_DROP_ACCEPTED", - 0xB10, 1, 0, 0, 0, 0, - QDMA_ST_MODE, QDMA_REG_READ_PF_VF, 0, NULL}, - {"C2H_STAT_DESC_RSP_ERR_ACCEPTED", - 0xB14, 1, 0, 0, 0, 0, - QDMA_ST_MODE, QDMA_REG_READ_PF_VF, 0, NULL}, - {"C2H_STAT_DESC_REQ", - 0xB18, 1, 0, 0, 0, 0, - QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, 0, NULL}, - {"C2H_STAT_DEBUG_DMA_ENG", - 0xB1C, 4, 0, 0, 0, 0, - QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, 0, NULL}, - {"C2H_DBG_PFCH_ERR_CTXT", - 0xB2C, 1, 0, 0, 0, 0, - QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, 0, NULL}, - {"C2H_FIRST_ERR_QID", - 0xB30, 1, 0, 0, 0, 0, - QDMA_ST_MODE, QDMA_REG_READ_PF_VF, 0, NULL}, - {"STAT_NUM_CMPT_IN", - 0xB34, 1, 0, 0, 0, 0, - QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, 0, NULL}, - {"STAT_NUM_CMPT_OUT", - 0xB38, 1, 0, 0, 0, 0, - QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, 0, NULL}, - {"STAT_NUM_CMPT_DRP", - 0xB3C, 1, 0, 0, 0, 0, - QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, 0, NULL}, - {"STAT_NUM_STAT_DESC_OUT", - 0xB40, 1, 0, 0, 0, 0, - QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, 0, NULL}, - {"STAT_NUM_DSC_CRDT_SENT", - 0xB44, 1, 0, 0, 0, 0, - QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, 0, NULL}, - {"STAT_NUM_FCH_DSC_RCVD", - 0xB48, 1, 0, 0, 0, 0, - QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, 0, NULL}, - {"STAT_NUM_BYP_DSC_RCVD", - 0xB4C, 1, 0, 0, 0, 0, - QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, 0, NULL}, - {"C2H_CMPT_COAL_CFG", - 0xB50, 1, 0, 0, 0, 0, - QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, 0, NULL}, - {"C2H_INTR_H2C_REQ", - 0xB54, 1, 0, 0, 0, 0, - QDMA_ST_MODE, QDMA_REG_READ_PF_VF, 0, NULL}, - {"C2H_INTR_C2H_MM_REQ", - 0xB58, 1, 0, 0, 0, 0, - QDMA_ST_MODE, QDMA_REG_READ_PF_VF, 0, NULL}, - {"C2H_INTR_ERR_INT_REQ", - 0xB5C, 1, 0, 0, 0, 0, - QDMA_ST_MODE, QDMA_REG_READ_PF_VF, 0, NULL}, - {"C2H_INTR_C2H_ST_REQ", - 0xB60, 1, 0, 0, 0, 0, - QDMA_ST_MODE, QDMA_REG_READ_PF_VF, 0, NULL}, - {"C2H_INTR_H2C_ERR_MM_MSIX_ACK", - 0xB64, 1, 0, 0, 0, 0, - QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, 0, NULL}, - {"C2H_INTR_H2C_ERR_MM_MSIX_FAIL", - 0xB68, 1, 0, 0, 0, 0, - QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, 0, NULL}, - {"C2H_INTR_H2C_ERR_MM_NO_MSIX", - 0xB6C, 1, 0, 0, 0, 0, - QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, 0, NULL}, - {"C2H_INTR_H2C_ERR_MM_CTXT_INVAL", - 0xB70, 1, 0, 0, 0, 0, - QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, 0, NULL}, - {"C2H_INTR_C2H_ST_MSIX_ACK", - 0xB74, 1, 0, 0, 0, 0, - QDMA_ST_MODE, QDMA_REG_READ_PF_VF, 0, NULL}, - {"C2H_INTR_C2H_ST_MSIX_FAIL", - 0xB78, 1, 0, 0, 0, 0, - QDMA_ST_MODE, QDMA_REG_READ_PF_VF, 0, NULL}, - {"C2H_INTR_C2H_ST_NO_MSIX", - 0xB7C, 1, 0, 0, 0, 0, - QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, 0, NULL}, - {"C2H_INTR_C2H_ST_CTXT_INVAL", - 0xB80, 1, 0, 0, 0, 0, - QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, 0, NULL}, - {"C2H_STAT_WR_CMP", - 0xB84, 1, 0, 0, 0, 0, - QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, 0, NULL}, - {"C2H_STAT_DEBUG_DMA_ENG_4", - 0xB88, 1, 0, 0, 0, 0, - QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, 0, NULL}, - {"C2H_STAT_DEBUG_DMA_ENG_5", - 0xB8C, 1, 0, 0, 0, 0, - QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, 0, NULL}, - {"C2H_DBG_PFCH_QID", - 0xB90, 1, 0, 0, 0, 0, - QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, 0, NULL}, - {"C2H_DBG_PFCH", - 0xB94, 1, 0, 0, 0, 0, - QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, 0, NULL}, - {"C2H_INT_DEBUG", - 0xB98, 1, 0, 0, 0, 0, - QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, 0, NULL}, - {"C2H_STAT_IMM_ACCEPTED", - 0xB9C, 1, 0, 0, 0, 0, - QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, 0, NULL}, - {"C2H_STAT_MARKER_ACCEPTED", - 0xBA0, 1, 0, 0, 0, 0, - QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, 0, NULL}, - {"C2H_STAT_DISABLE_CMP_ACCEPTED", - 0xBA4, 1, 0, 0, 0, 0, - QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, 0, NULL}, - {"C2H_C2H_PAYLOAD_FIFO_CRDT_CNT", - 0xBA8, 1, 0, 0, 0, 0, - QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, 0, NULL}, - {"C2H_INTR_DYN_REQ", - 0xBAC, 1, 0, 0, 0, 0, - QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, 0, NULL}, - {"C2H_INTR_DYN_MSIX", - 0xBB0, 1, 0, 0, 0, 0, - QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, 0, NULL}, - {"C2H_DROP_LEN_MISMATCH", - 0xBB4, 1, 0, 0, 0, 0, - QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, 0, NULL}, - {"C2H_DROP_DESC_RSP_LEN", - 0xBB8, 1, 0, 0, 0, 0, - QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, 0, NULL}, - {"C2H_DROP_QID_FIFO_LEN", - 0xBBC, 1, 0, 0, 0, 0, - QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, 0, NULL}, - {"C2H_DROP_PAYLOAD_CNT", - 0xBC0, 1, 0, 0, 0, 0, - QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, 0, NULL}, - {"QDMA_C2H_CMPT_FORMAT", - 0xBC4, 7, 0, 0, 0, 0, - QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, 0, NULL}, - {"C2H_PFCH_CACHE_DEPTH", - 0xBE0, 1, 0, 0, 0, 0, - QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, 0, NULL}, - {"C2H_CMPT_COAL_BUF_DEPTH", - 0xBE4, 1, 0, 0, 0, 0, - QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, 0, NULL}, - {"C2H_PFCH_CRDT", - 0xBE8, 1, 0, 0, 0, 0, - QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, 0, NULL}, - - /* QDMA_TRQ_SEL_H2C(0x00E00) Register Space*/ - {"H2C_ERR_STAT", - 0xE00, 1, 0, 0, 0, 0, - QDMA_ST_MODE, QDMA_REG_READ_PF_VF, 0, NULL}, - {"H2C_ERR_MASK", - 0xE04, 1, 0, 0, 0, 0, - QDMA_ST_MODE, QDMA_REG_READ_PF_VF, 0, NULL}, - {"H2C_FIRST_ERR_QID", - 0xE08, 1, 0, 0, 0, 0, - QDMA_ST_MODE, QDMA_REG_READ_PF_VF, 0, NULL}, - {"H2C_DBG_REG", - 0xE0C, 5, 0, 0, 0, 0, - QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, 0, NULL}, - {"H2C_FATAL_ERR_EN", - 0xE20, 1, 0, 0, 0, 0, - QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, 0, NULL}, - {"H2C_REQ_THROT", - 0xE24, 1, 0, 0, 0, 0, - QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, 0, NULL}, - {"H2C_ALN_DBG_REG0", - 0xE28, 1, 0, 0, 0, 0, - QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, 0, NULL}, - - /* QDMA_TRQ_SEL_C2H_MM (0x1000) */ - {"C2H_MM_CONTROL", - 0x1004, 3, 0, 0, 0, 0, - QDMA_MM_MODE, QDMA_REG_READ_PF_ONLY, 0, NULL}, - {"C2H_MM_STATUS", - 0x1040, 2, 0, 0, 0, 0, - QDMA_MM_MODE, QDMA_REG_READ_PF_ONLY, 0, NULL}, - {"C2H_MM_CMPL_DSC_CNT", - 0x1048, 1, 0, 0, 0, 0, - QDMA_MM_MODE, QDMA_REG_READ_PF_ONLY, 0, NULL}, - {"C2H_MM_ERR_CODE_EN_MASK", - 0x1054, 1, 0, 0, 0, 0, - QDMA_MM_MODE, QDMA_REG_READ_PF_ONLY, 0, NULL}, - {"C2H_MM_ERR_CODE", - 0x1058, 1, 0, 0, 0, 0, - QDMA_MM_MODE, QDMA_REG_READ_PF_ONLY, 0, NULL}, - {"C2H_MM_ERR_INFO", - 0x105C, 1, 0, 0, 0, 0, - QDMA_MM_MODE, QDMA_REG_READ_PF_ONLY, 0, NULL}, - {"C2H_MM_PERF_MON_CTRL", - 0x10C0, 1, 0, 0, 0, 0, - QDMA_MM_MODE, QDMA_REG_READ_PF_ONLY, 0, NULL}, - {"C2H_MM_PERF_MON_CY_CNT", - 0x10C4, 2, 0, 0, 0, 0, - QDMA_MM_MODE, QDMA_REG_READ_PF_ONLY, 0, NULL}, - {"C2H_MM_PERF_MON_DATA_CNT", - 0x10CC, 2, 0, 0, 0, 0, - QDMA_MM_MODE, QDMA_REG_READ_PF_ONLY, 0, NULL}, - {"C2H_MM_DBG_INFO", - 0x10E8, 2, 0, 0, 0, 0, - QDMA_MM_MODE, QDMA_REG_READ_PF_ONLY, 0, NULL}, - - /* QDMA_TRQ_SEL_H2C_MM (0x1200)*/ - {"H2C_MM_CONTROL", - 0x1204, 3, 0, 0, 0, 0, - QDMA_MM_MODE, QDMA_REG_READ_PF_ONLY, 0, NULL}, - {"H2C_MM_STATUS", - 0x1240, 1, 0, 0, 0, 0, - QDMA_MM_MODE, QDMA_REG_READ_PF_ONLY, 0, NULL}, - {"H2C_MM_CMPL_DSC_CNT", - 0x1248, 1, 0, 0, 0, 0, - QDMA_MM_MODE, QDMA_REG_READ_PF_ONLY, 0, NULL}, - {"H2C_MM_ERR_CODE_EN_MASK", - 0x1254, 1, 0, 0, 0, 0, - QDMA_MM_MODE, QDMA_REG_READ_PF_ONLY, 0, NULL}, - {"H2C_MM_ERR_CODE", - 0x1258, 1, 0, 0, 0, 0, - QDMA_MM_MODE, QDMA_REG_READ_PF_ONLY, 0, NULL}, - {"H2C_MM_ERR_INFO", - 0x125C, 1, 0, 0, 0, 0, - QDMA_MM_MODE, QDMA_REG_READ_PF_ONLY, 0, NULL}, - {"H2C_MM_PERF_MON_CTRL", - 0x12C0, 1, 0, 0, 0, 0, - QDMA_MM_MODE, QDMA_REG_READ_PF_ONLY, 0, NULL}, - {"H2C_MM_PERF_MON_CY_CNT", - 0x12C4, 2, 0, 0, 0, 0, - QDMA_MM_MODE, QDMA_REG_READ_PF_ONLY, 0, NULL}, - {"H2C_MM_PERF_MON_DATA_CNT", - 0x12CC, 2, 0, 0, 0, 0, - QDMA_MM_MODE, QDMA_REG_READ_PF_ONLY, 0, NULL}, - {"H2C_MM_DBG_INFO", - 0x12E8, 1, 0, 0, 0, 0, - QDMA_MM_MODE, QDMA_REG_READ_PF_ONLY, 0, NULL}, - {"H2C_MM_REQ_THROT", - 0x12EC, 1, 0, 0, 0, 0, - QDMA_MM_MODE, QDMA_REG_READ_PF_ONLY, 0, NULL}, - - /* QDMA_PF_MAILBOX (0x2400) */ - {"FUNC_STATUS", - 0x2400, 1, 0, 0, 0, 0, - QDMA_MAILBOX, QDMA_REG_READ_PF_ONLY, 0, NULL}, - {"FUNC_CMD", - 0x2404, 1, 0, 0, 0, 0, - QDMA_MAILBOX, QDMA_REG_READ_PF_ONLY, 0, NULL}, - {"FUNC_INTR_VEC", - 0x2408, 1, 0, 0, 0, 0, - QDMA_MAILBOX, QDMA_REG_READ_PF_ONLY, 0, NULL}, - {"TARGET_FUNC", - 0x240C, 1, 0, 0, 0, 0, - QDMA_MAILBOX, QDMA_REG_READ_PF_ONLY, 0, NULL}, - {"INTR_CTRL", - 0x2410, 1, 0, 0, 0, 0, - QDMA_MAILBOX, QDMA_REG_READ_PF_ONLY, 0, NULL}, - {"PF_ACK", - 0x2420, 8, 0, 0, 0, 0, - QDMA_MAILBOX, QDMA_REG_READ_PF_ONLY, 0, NULL}, - {"FLR_CTRL_STATUS", - 0x2500, 1, 0, 0, 0, 0, - QDMA_MAILBOX, QDMA_REG_READ_PF_ONLY, 0, NULL}, - {"MSG_IN", - 0x2800, 32, 0, 0, 0, 0, - QDMA_MAILBOX, QDMA_REG_READ_PF_ONLY, 0, NULL}, - {"MSG_OUT", - 0x2C00, 32, 0, 0, 0, 0, - QDMA_MAILBOX, QDMA_REG_READ_PF_ONLY, 0, NULL}, - - {"", 0, 0, 0, 0, 0, 0, 0, 0, 0, NULL } -}; - - -static struct qdma_hw_err_info qdma_err_info[QDMA_ERRS_ALL] = { - /* Descriptor errors */ - { - QDMA_DSC_ERR_POISON, - "Poison error", - QDMA_OFFSET_GLBL_DSC_ERR_MASK, - QDMA_OFFSET_GLBL_DSC_ERR_STAT, - QDMA_GLBL_DSC_ERR_POISON_MASK, - QDMA_GLBL_ERR_DSC_MASK, - &qdma_hw_desc_err_process - }, - { - QDMA_DSC_ERR_UR_CA, - "Unsupported request or completer aborted error", - QDMA_OFFSET_GLBL_DSC_ERR_MASK, - QDMA_OFFSET_GLBL_DSC_ERR_STAT, - QDMA_GLBL_DSC_ERR_UR_CA_MASK, - QDMA_GLBL_ERR_DSC_MASK, - &qdma_hw_desc_err_process - }, - { - QDMA_DSC_ERR_PARAM, - "Parameter mismatch error", - QDMA_OFFSET_GLBL_DSC_ERR_MASK, - QDMA_OFFSET_GLBL_DSC_ERR_STAT, - QDMA_GLBL_DSC_ERR_PARAM_MASK, - QDMA_GLBL_ERR_DSC_MASK, - &qdma_hw_desc_err_process - }, - { - QDMA_DSC_ERR_ADDR, - "Address mismatch error", - QDMA_OFFSET_GLBL_DSC_ERR_MASK, - QDMA_OFFSET_GLBL_DSC_ERR_STAT, - QDMA_GLBL_DSC_ERR_ADDR_MASK, - QDMA_GLBL_ERR_DSC_MASK, - &qdma_hw_desc_err_process - }, - { - QDMA_DSC_ERR_TAG, - "Unexpected tag error", - QDMA_OFFSET_GLBL_DSC_ERR_MASK, - QDMA_OFFSET_GLBL_DSC_ERR_STAT, - QDMA_GLBL_DSC_ERR_TAG_MASK, - QDMA_GLBL_ERR_DSC_MASK, - &qdma_hw_desc_err_process - }, - { - QDMA_DSC_ERR_FLR, - "FLR error", - QDMA_OFFSET_GLBL_DSC_ERR_MASK, - QDMA_OFFSET_GLBL_DSC_ERR_STAT, - QDMA_GLBL_DSC_ERR_FLR_MASK, - QDMA_GLBL_ERR_DSC_MASK, - &qdma_hw_desc_err_process - }, - { - QDMA_DSC_ERR_TIMEOUT, - "Timed out error", - QDMA_OFFSET_GLBL_DSC_ERR_MASK, - QDMA_OFFSET_GLBL_DSC_ERR_STAT, - QDMA_GLBL_DSC_ERR_TIMEOUT_MASK, - QDMA_GLBL_ERR_DSC_MASK, - &qdma_hw_desc_err_process - }, - { - QDMA_DSC_ERR_DAT_POISON, - "Poison data error", - QDMA_OFFSET_GLBL_DSC_ERR_MASK, - QDMA_OFFSET_GLBL_DSC_ERR_STAT, - QDMA_GLBL_DSC_ERR_DAT_POISON_MASK, - QDMA_GLBL_ERR_DSC_MASK, - &qdma_hw_desc_err_process - }, - { - QDMA_DSC_ERR_FLR_CANCEL, - "Descriptor fetch cancelled due to FLR error", - QDMA_OFFSET_GLBL_DSC_ERR_MASK, - QDMA_OFFSET_GLBL_DSC_ERR_STAT, - QDMA_GLBL_DSC_ERR_FLR_CANCEL_MASK, - QDMA_GLBL_ERR_DSC_MASK, - &qdma_hw_desc_err_process - }, - { - QDMA_DSC_ERR_DMA, - "DMA engine error", - QDMA_OFFSET_GLBL_DSC_ERR_MASK, - QDMA_OFFSET_GLBL_DSC_ERR_STAT, - QDMA_GLBL_DSC_ERR_DMA_MASK, - QDMA_GLBL_ERR_DSC_MASK, - &qdma_hw_desc_err_process - }, - { - QDMA_DSC_ERR_DSC, - "Invalid PIDX update error", - QDMA_OFFSET_GLBL_DSC_ERR_MASK, - QDMA_OFFSET_GLBL_DSC_ERR_STAT, - QDMA_GLBL_DSC_ERR_DSC_MASK, - QDMA_GLBL_ERR_DSC_MASK, - &qdma_hw_desc_err_process - }, - { - QDMA_DSC_ERR_RQ_CANCEL, - "Descriptor fetch cancelled due to disable register status error", - QDMA_OFFSET_GLBL_DSC_ERR_MASK, - QDMA_OFFSET_GLBL_DSC_ERR_STAT, - QDMA_GLBL_DSC_ERR_RQ_CANCEL_MASK, - QDMA_GLBL_ERR_DSC_MASK, - &qdma_hw_desc_err_process - }, - { - QDMA_DSC_ERR_DBE, - "UNC_ERR_RAM_DBE error", - QDMA_OFFSET_GLBL_DSC_ERR_MASK, - QDMA_OFFSET_GLBL_DSC_ERR_STAT, - QDMA_GLBL_DSC_ERR_DBE_MASK, - QDMA_GLBL_ERR_DSC_MASK, - &qdma_hw_desc_err_process - }, - { - QDMA_DSC_ERR_SBE, - "UNC_ERR_RAM_SBE error", - QDMA_OFFSET_GLBL_DSC_ERR_MASK, - QDMA_OFFSET_GLBL_DSC_ERR_STAT, - QDMA_GLBL_DSC_ERR_SBE_MASK, - QDMA_GLBL_ERR_DSC_MASK, - &qdma_hw_desc_err_process - }, - { - QDMA_DSC_ERR_ALL, - "All Descriptor errors", - QDMA_OFFSET_GLBL_DSC_ERR_MASK, - QDMA_OFFSET_GLBL_DSC_ERR_STAT, - QDMA_GLBL_DSC_ERR_ALL_MASK, - QDMA_GLBL_ERR_DSC_MASK, - &qdma_hw_desc_err_process - }, - - /* TRQ errors */ - { - QDMA_TRQ_ERR_UNMAPPED, - "Access targeted unmapped register space error", - QDMA_OFFSET_GLBL_TRQ_ERR_MASK, - QDMA_OFFSET_GLBL_TRQ_ERR_STAT, - QDMA_GLBL_TRQ_ERR_UNMAPPED_MASK, - QDMA_GLBL_ERR_TRQ_MASK, - &qdma_hw_trq_err_process - }, - { - QDMA_TRQ_ERR_QID_RANGE, - "Qid range error", - QDMA_OFFSET_GLBL_TRQ_ERR_MASK, - QDMA_OFFSET_GLBL_TRQ_ERR_STAT, - QDMA_GLBL_TRQ_ERR_QID_RANGE_MASK, - QDMA_GLBL_ERR_TRQ_MASK, - &qdma_hw_trq_err_process - }, - { - QDMA_TRQ_ERR_VF_ACCESS, - "Invalid VF access error", - QDMA_OFFSET_GLBL_TRQ_ERR_MASK, - QDMA_OFFSET_GLBL_TRQ_ERR_STAT, - QDMA_GLBL_TRQ_ERR_VF_ACCESS_MASK, - QDMA_GLBL_ERR_TRQ_MASK, - &qdma_hw_trq_err_process - }, - { - QDMA_TRQ_ERR_TCP_TIMEOUT, - "Timeout on request error", - QDMA_OFFSET_GLBL_TRQ_ERR_MASK, - QDMA_OFFSET_GLBL_TRQ_ERR_STAT, - QDMA_GLBL_TRQ_ERR_TCP_TIMEOUT_MASK, - QDMA_GLBL_ERR_TRQ_MASK, - &qdma_hw_trq_err_process - }, - { - QDMA_TRQ_ERR_ALL, - "All TRQ errors", - QDMA_OFFSET_GLBL_TRQ_ERR_MASK, - QDMA_OFFSET_GLBL_TRQ_ERR_STAT, - QDMA_GLBL_TRQ_ERR_ALL_MASK, - QDMA_GLBL_ERR_TRQ_MASK, - &qdma_hw_trq_err_process - }, - - /* C2H Errors*/ - { - QDMA_ST_C2H_ERR_MTY_MISMATCH, - "MTY mismatch error", - QDMA_OFFSET_C2H_ERR_MASK, - QDMA_OFFSET_C2H_ERR_STAT, - QDMA_C2H_ERR_MTY_MISMATCH_MASK, - QDMA_GLBL_ERR_ST_C2H_MASK, - &qdma_hw_st_c2h_err_process - }, - { - QDMA_ST_C2H_ERR_LEN_MISMATCH, - "Packet length mismatch error", - QDMA_OFFSET_C2H_ERR_MASK, - QDMA_OFFSET_C2H_ERR_STAT, - QDMA_C2H_ERR_LEN_MISMATCH_MASK, - QDMA_GLBL_ERR_ST_C2H_MASK, - &qdma_hw_st_c2h_err_process - }, - { - QDMA_ST_C2H_ERR_QID_MISMATCH, - "Qid mismatch error", - QDMA_OFFSET_C2H_ERR_MASK, - QDMA_OFFSET_C2H_ERR_STAT, - QDMA_C2H_ERR_QID_MISMATCH_MASK, - QDMA_GLBL_ERR_ST_C2H_MASK, - &qdma_hw_st_c2h_err_process - }, - { - QDMA_ST_C2H_ERR_DESC_RSP_ERR, - "Descriptor error bit set", - QDMA_OFFSET_C2H_ERR_MASK, - QDMA_OFFSET_C2H_ERR_STAT, - QDMA_C2H_ERR_DESC_RSP_ERR_MASK, - QDMA_GLBL_ERR_ST_C2H_MASK, - &qdma_hw_st_c2h_err_process - }, - { - QDMA_ST_C2H_ERR_ENG_WPL_DATA_PAR_ERR, - "Data parity error", - QDMA_OFFSET_C2H_ERR_MASK, - QDMA_OFFSET_C2H_ERR_STAT, - QDMA_C2H_ERR_ENG_WPL_DATA_PAR_ERR_MASK, - QDMA_GLBL_ERR_ST_C2H_MASK, - &qdma_hw_st_c2h_err_process - }, - { - QDMA_ST_C2H_ERR_MSI_INT_FAIL, - "MSI got a fail response error", - QDMA_OFFSET_C2H_ERR_MASK, - QDMA_OFFSET_C2H_ERR_STAT, - QDMA_C2H_ERR_MSI_INT_FAIL_MASK, - QDMA_GLBL_ERR_ST_C2H_MASK, - &qdma_hw_st_c2h_err_process - }, - { - QDMA_ST_C2H_ERR_ERR_DESC_CNT, - "Descriptor count error", - QDMA_OFFSET_C2H_ERR_MASK, - QDMA_OFFSET_C2H_ERR_STAT, - QDMA_C2H_ERR_ERR_DESC_CNT_MASK, - QDMA_GLBL_ERR_ST_C2H_MASK, - &qdma_hw_st_c2h_err_process - }, - { - QDMA_ST_C2H_ERR_PORTID_CTXT_MISMATCH, - "Port id in packet and pfetch ctxt mismatch error", - QDMA_OFFSET_C2H_ERR_MASK, - QDMA_OFFSET_C2H_ERR_STAT, - QDMA_C2H_ERR_PORTID_CTXT_MISMATCH_MASK, - QDMA_GLBL_ERR_ST_C2H_MASK, - &qdma_hw_st_c2h_err_process - }, - { - QDMA_ST_C2H_ERR_PORTID_BYP_IN_MISMATCH, - "Port id in packet and bypass interface mismatch error", - QDMA_OFFSET_C2H_ERR_MASK, - QDMA_OFFSET_C2H_ERR_STAT, - QDMA_C2H_ERR_PORTID_BYP_IN_MISMATCH_MASK, - QDMA_GLBL_ERR_ST_C2H_MASK, - &qdma_hw_st_c2h_err_process - }, - { - QDMA_ST_C2H_ERR_CMPT_INV_Q_ERR, - "Writeback on invalid queue error", - QDMA_OFFSET_C2H_ERR_MASK, - QDMA_OFFSET_C2H_ERR_STAT, - QDMA_C2H_ERR_CMPT_INV_Q_ERR_MASK, - QDMA_GLBL_ERR_ST_C2H_MASK, - &qdma_hw_st_c2h_err_process - }, - { - QDMA_ST_C2H_ERR_CMPT_QFULL_ERR, - "Completion queue gets full error", - QDMA_OFFSET_C2H_ERR_MASK, - QDMA_OFFSET_C2H_ERR_STAT, - QDMA_C2H_ERR_CMPT_QFULL_ERR_MASK, - QDMA_GLBL_ERR_ST_C2H_MASK, - &qdma_hw_st_c2h_err_process - }, - { - QDMA_ST_C2H_ERR_CMPT_CIDX_ERR, - "Bad CIDX update by the software error", - QDMA_OFFSET_C2H_ERR_MASK, - QDMA_OFFSET_C2H_ERR_STAT, - QDMA_C2H_ERR_CMPT_CIDX_ERR_MASK, - QDMA_GLBL_ERR_ST_C2H_MASK, - &qdma_hw_st_c2h_err_process - }, - { - QDMA_ST_C2H_ERR_CMPT_PRTY_ERR, - "C2H completion Parity error", - QDMA_OFFSET_C2H_ERR_MASK, - QDMA_OFFSET_C2H_ERR_STAT, - QDMA_C2H_ERR_CMPT_PRTY_ERR_MASK, - QDMA_GLBL_ERR_ST_C2H_MASK, - &qdma_hw_st_c2h_err_process - }, - { - QDMA_ST_C2H_ERR_ALL, - "All C2h errors", - QDMA_OFFSET_C2H_ERR_MASK, - QDMA_OFFSET_C2H_ERR_STAT, - QDMA_C2H_ERR_ALL_MASK, - QDMA_GLBL_ERR_ST_C2H_MASK, - &qdma_hw_st_c2h_err_process - }, - - /* C2H fatal errors */ - { - QDMA_ST_FATAL_ERR_MTY_MISMATCH, - "Fatal MTY mismatch error", - QDMA_OFFSET_C2H_FATAL_ERR_MASK, - QDMA_OFFSET_C2H_FATAL_ERR_STAT, - QDMA_C2H_FATAL_ERR_MTY_MISMATCH_MASK, - QDMA_GLBL_ERR_ST_C2H_MASK, - &qdma_hw_st_c2h_err_process - }, - { - QDMA_ST_FATAL_ERR_LEN_MISMATCH, - "Fatal Len mismatch error", - QDMA_OFFSET_C2H_FATAL_ERR_MASK, - QDMA_OFFSET_C2H_FATAL_ERR_STAT, - QDMA_C2H_FATAL_ERR_LEN_MISMATCH_MASK, - QDMA_GLBL_ERR_ST_C2H_MASK, - &qdma_hw_st_c2h_err_process - }, - { - QDMA_ST_FATAL_ERR_QID_MISMATCH, - "Fatal Qid mismatch error", - QDMA_OFFSET_C2H_FATAL_ERR_MASK, - QDMA_OFFSET_C2H_FATAL_ERR_STAT, - QDMA_C2H_FATAL_ERR_QID_MISMATCH_MASK, - QDMA_GLBL_ERR_ST_C2H_MASK, - &qdma_hw_st_c2h_err_process - }, - { - QDMA_ST_FATAL_ERR_TIMER_FIFO_RAM_RDBE, - "RAM double bit fatal error", - QDMA_OFFSET_C2H_FATAL_ERR_MASK, - QDMA_OFFSET_C2H_FATAL_ERR_STAT, - QDMA_C2H_FATAL_ERR_TIMER_FIFO_RAM_RDBE_MASK, - QDMA_GLBL_ERR_ST_C2H_MASK, - &qdma_hw_st_c2h_err_process - }, - { - QDMA_ST_FATAL_ERR_PFCH_II_RAM_RDBE, - "RAM double bit fatal error", - QDMA_OFFSET_C2H_FATAL_ERR_MASK, - QDMA_OFFSET_C2H_FATAL_ERR_STAT, - QDMA_C2H_FATAL_ERR_PFCH_II_RAM_RDBE_MASK, - QDMA_GLBL_ERR_ST_C2H_MASK, - &qdma_hw_st_c2h_err_process - }, - { - QDMA_ST_FATAL_ERR_CMPT_CTXT_RAM_RDBE, - "RAM double bit fatal error", - QDMA_OFFSET_C2H_FATAL_ERR_MASK, - QDMA_OFFSET_C2H_FATAL_ERR_STAT, - QDMA_C2H_FATAL_ERR_CMPT_CTXT_RAM_RDBE_MASK, - QDMA_GLBL_ERR_ST_C2H_MASK, - &qdma_hw_st_c2h_err_process - }, - { - QDMA_ST_FATAL_ERR_PFCH_CTXT_RAM_RDBE, - "RAM double bit fatal error", - QDMA_OFFSET_C2H_FATAL_ERR_MASK, - QDMA_OFFSET_C2H_FATAL_ERR_STAT, - QDMA_C2H_FATAL_ERR_PFCH_CTXT_RAM_RDBE_MASK, - QDMA_GLBL_ERR_ST_C2H_MASK, - &qdma_hw_st_c2h_err_process - }, - { - QDMA_ST_FATAL_ERR_DESC_REQ_FIFO_RAM_RDBE, - "RAM double bit fatal error", - QDMA_OFFSET_C2H_FATAL_ERR_MASK, - QDMA_OFFSET_C2H_FATAL_ERR_STAT, - QDMA_C2H_FATAL_ERR_DESC_REQ_FIFO_RAM_RDBE_MASK, - QDMA_GLBL_ERR_ST_C2H_MASK, - &qdma_hw_st_c2h_err_process - }, - { - QDMA_ST_FATAL_ERR_INT_CTXT_RAM_RDBE, - "RAM double bit fatal error", - QDMA_OFFSET_C2H_FATAL_ERR_MASK, - QDMA_OFFSET_C2H_FATAL_ERR_STAT, - QDMA_C2H_FATAL_ERR_INT_CTXT_RAM_RDBE_MASK, - QDMA_GLBL_ERR_ST_C2H_MASK, - &qdma_hw_st_c2h_err_process - }, - { - QDMA_ST_FATAL_ERR_CMPT_COAL_DATA_RAM_RDBE, - "RAM double bit fatal error", - QDMA_OFFSET_C2H_FATAL_ERR_MASK, - QDMA_OFFSET_C2H_FATAL_ERR_STAT, - QDMA_C2H_FATAL_ERR_CMPT_COAL_DATA_RAM_RDBE_MASK, - QDMA_GLBL_ERR_ST_C2H_MASK, - &qdma_hw_st_c2h_err_process - }, - { - QDMA_ST_FATAL_ERR_TUSER_FIFO_RAM_RDBE, - "RAM double bit fatal error", - QDMA_OFFSET_C2H_FATAL_ERR_MASK, - QDMA_OFFSET_C2H_FATAL_ERR_STAT, - QDMA_C2H_FATAL_ERR_TUSER_FIFO_RAM_RDBE_MASK, - QDMA_GLBL_ERR_ST_C2H_MASK, - &qdma_hw_st_c2h_err_process - }, - { - QDMA_ST_FATAL_ERR_QID_FIFO_RAM_RDBE, - "RAM double bit fatal error", - QDMA_OFFSET_C2H_FATAL_ERR_MASK, - QDMA_OFFSET_C2H_FATAL_ERR_STAT, - QDMA_C2H_FATAL_ERR_QID_FIFO_RAM_RDBE_MASK, - QDMA_GLBL_ERR_ST_C2H_MASK, - &qdma_hw_st_c2h_err_process - }, - { - QDMA_ST_FATAL_ERR_PAYLOAD_FIFO_RAM_RDBE, - "RAM double bit fatal error", - QDMA_OFFSET_C2H_FATAL_ERR_MASK, - QDMA_OFFSET_C2H_FATAL_ERR_STAT, - QDMA_C2H_FATAL_ERR_PAYLOAD_FIFO_RAM_RDBE_MASK, - QDMA_GLBL_ERR_ST_C2H_MASK, - &qdma_hw_st_c2h_err_process - }, - { - QDMA_ST_FATAL_ERR_WPL_DATA_PAR, - "RAM double bit fatal error", - QDMA_OFFSET_C2H_FATAL_ERR_MASK, - QDMA_OFFSET_C2H_FATAL_ERR_STAT, - QDMA_C2H_FATAL_ERR_WPL_DATA_PAR_MASK, - QDMA_GLBL_ERR_ST_C2H_MASK, - &qdma_hw_st_c2h_err_process - }, - { - QDMA_ST_FATAL_ERR_ALL, - "All fatal errors", - QDMA_OFFSET_C2H_FATAL_ERR_MASK, - QDMA_OFFSET_C2H_FATAL_ERR_STAT, - QDMA_C2H_FATAL_ERR_ALL_MASK, - QDMA_GLBL_ERR_ST_C2H_MASK, - &qdma_hw_st_c2h_err_process - }, - - /* H2C St errors */ - { - QDMA_ST_H2C_ERR_ZERO_LEN_DESC, - "Zero length descriptor error", - QDMA_OFFSET_H2C_ERR_MASK, - QDMA_OFFSET_H2C_ERR_STAT, - QDMA_H2C_ERR_ZERO_LEN_DESC_MASK, - QDMA_GLBL_ERR_ST_H2C_MASK, - &qdma_hw_st_h2c_err_process - }, - { - QDMA_ST_H2C_ERR_CSI_MOP, - "Non EOP descriptor received error", - QDMA_OFFSET_H2C_ERR_MASK, - QDMA_OFFSET_H2C_ERR_STAT, - QDMA_H2C_ERR_CSI_MOP_MASK, - QDMA_GLBL_ERR_ST_H2C_MASK, - &qdma_hw_st_h2c_err_process - }, - { - QDMA_ST_H2C_ERR_NO_DMA_DSC, - "No DMA descriptor received error", - QDMA_OFFSET_H2C_ERR_MASK, - QDMA_OFFSET_H2C_ERR_STAT, - QDMA_H2C_ERR_NO_DMA_DSC_MASK, - QDMA_GLBL_ERR_ST_H2C_MASK, - &qdma_hw_st_h2c_err_process - }, - { - QDMA_ST_H2C_ERR_SBE, - "Single bit error detected on H2C-ST data error", - QDMA_OFFSET_H2C_ERR_MASK, - QDMA_OFFSET_H2C_ERR_STAT, - QDMA_H2C_ERR_SBE_MASK, - QDMA_GLBL_ERR_ST_H2C_MASK, - &qdma_hw_st_h2c_err_process - }, - { - QDMA_ST_H2C_ERR_DBE, - "Double bit error detected on H2C-ST data error", - QDMA_OFFSET_H2C_ERR_MASK, - QDMA_OFFSET_H2C_ERR_STAT, - QDMA_H2C_ERR_DBE_MASK, - QDMA_GLBL_ERR_ST_H2C_MASK, - &qdma_hw_st_h2c_err_process - }, - { - QDMA_ST_H2C_ERR_ALL, - "All H2C errors", - QDMA_OFFSET_H2C_ERR_MASK, - QDMA_OFFSET_H2C_ERR_STAT, - QDMA_H2C_ERR_ALL_MASK, - QDMA_GLBL_ERR_ST_H2C_MASK, - &qdma_hw_st_h2c_err_process - }, - - /* SBE errors */ - { - QDMA_SBE_ERR_MI_H2C0_DAT, - "H2C MM data buffer single bit ECC error", - QDMA_OFFSET_RAM_SBE_MASK, - QDMA_OFFSET_RAM_SBE_STAT, - QDMA_SBE_ERR_MI_H2C0_DAT_MASK, - QDMA_GLBL_ERR_RAM_SBE_MASK, - &qdma_hw_ram_sbe_err_process - }, - { - QDMA_SBE_ERR_MI_C2H0_DAT, - "C2H MM data buffer single bit ECC error", - QDMA_OFFSET_RAM_SBE_MASK, - QDMA_OFFSET_RAM_SBE_STAT, - QDMA_SBE_ERR_MI_C2H0_DAT_MASK, - QDMA_GLBL_ERR_RAM_SBE_MASK, - &qdma_hw_ram_sbe_err_process - }, - { - QDMA_SBE_ERR_H2C_RD_BRG_DAT, - "Bridge master read single bit ECC error", - QDMA_OFFSET_RAM_SBE_MASK, - QDMA_OFFSET_RAM_SBE_STAT, - QDMA_SBE_ERR_H2C_RD_BRG_DAT_MASK, - QDMA_GLBL_ERR_RAM_SBE_MASK, - &qdma_hw_ram_sbe_err_process - }, - { - QDMA_SBE_ERR_H2C_WR_BRG_DAT, - "Bridge master write single bit ECC error", - QDMA_OFFSET_RAM_SBE_MASK, - QDMA_OFFSET_RAM_SBE_STAT, - QDMA_SBE_ERR_H2C_WR_BRG_DAT_MASK, - QDMA_GLBL_ERR_RAM_SBE_MASK, - &qdma_hw_ram_sbe_err_process - }, - { - QDMA_SBE_ERR_C2H_RD_BRG_DAT, - "Bridge slave read data buffer single bit ECC error", - QDMA_OFFSET_RAM_SBE_MASK, - QDMA_OFFSET_RAM_SBE_STAT, - QDMA_SBE_ERR_C2H_RD_BRG_DAT_MASK, - QDMA_GLBL_ERR_RAM_SBE_MASK, - &qdma_hw_ram_sbe_err_process - }, - { - QDMA_SBE_ERR_C2H_WR_BRG_DAT, - "Bridge slave write data buffer single bit ECC error", - QDMA_OFFSET_RAM_SBE_MASK, - QDMA_OFFSET_RAM_SBE_STAT, - QDMA_SBE_ERR_C2H_WR_BRG_DAT_MASK, - QDMA_GLBL_ERR_RAM_SBE_MASK, - &qdma_hw_ram_sbe_err_process - }, - { - QDMA_SBE_ERR_FUNC_MAP, - "Function map RAM single bit ECC error", - QDMA_OFFSET_RAM_SBE_MASK, - QDMA_OFFSET_RAM_SBE_STAT, - QDMA_SBE_ERR_FUNC_MAP_MASK, - QDMA_GLBL_ERR_RAM_SBE_MASK, - &qdma_hw_ram_sbe_err_process - }, - { - QDMA_SBE_ERR_DSC_HW_CTXT, - "Descriptor engine hardware context RAM single bit ECC error", - QDMA_OFFSET_RAM_SBE_MASK, - QDMA_OFFSET_RAM_SBE_STAT, - QDMA_SBE_ERR_DSC_HW_CTXT_MASK, - QDMA_GLBL_ERR_RAM_SBE_MASK, - &qdma_hw_ram_sbe_err_process - }, - { - QDMA_SBE_ERR_DSC_CRD_RCV, - "Descriptor engine receive credit context RAM single bit ECC error", - QDMA_OFFSET_RAM_SBE_MASK, - QDMA_OFFSET_RAM_SBE_STAT, - QDMA_SBE_ERR_DSC_CRD_RCV_MASK, - QDMA_GLBL_ERR_RAM_SBE_MASK, - &qdma_hw_ram_sbe_err_process - }, - { - QDMA_SBE_ERR_DSC_SW_CTXT, - "Descriptor engine software context RAM single bit ECC error", - QDMA_OFFSET_RAM_SBE_MASK, - QDMA_OFFSET_RAM_SBE_STAT, - QDMA_SBE_ERR_DSC_SW_CTXT_MASK, - QDMA_GLBL_ERR_RAM_SBE_MASK, - &qdma_hw_ram_sbe_err_process - }, - { - QDMA_SBE_ERR_DSC_CPLI, - "Descriptor engine fetch completion information RAM single bit ECC error", - QDMA_OFFSET_RAM_SBE_MASK, - QDMA_OFFSET_RAM_SBE_STAT, - QDMA_SBE_ERR_DSC_CPLI_MASK, - QDMA_GLBL_ERR_RAM_SBE_MASK, - &qdma_hw_ram_sbe_err_process - }, - { - QDMA_SBE_ERR_DSC_CPLD, - "Descriptor engine fetch completion data RAM single bit ECC error", - QDMA_OFFSET_RAM_SBE_MASK, - QDMA_OFFSET_RAM_SBE_STAT, - QDMA_SBE_ERR_DSC_CPLD_MASK, - QDMA_GLBL_ERR_RAM_SBE_MASK, - &qdma_hw_ram_sbe_err_process - }, - { - QDMA_SBE_ERR_PASID_CTXT_RAM, - "PASID configuration RAM single bit ECC error", - QDMA_OFFSET_RAM_SBE_MASK, - QDMA_OFFSET_RAM_SBE_STAT, - QDMA_SBE_ERR_PASID_CTXT_RAM_MASK, - QDMA_GLBL_ERR_RAM_SBE_MASK, - &qdma_hw_ram_sbe_err_process - }, - { - QDMA_SBE_ERR_TIMER_FIFO_RAM, - "Timer fifo RAM single bit ECC error", - QDMA_OFFSET_RAM_SBE_MASK, - QDMA_OFFSET_RAM_SBE_STAT, - QDMA_SBE_ERR_TIMER_FIFO_RAM_MASK, - QDMA_GLBL_ERR_RAM_SBE_MASK, - &qdma_hw_ram_sbe_err_process - }, - { - QDMA_SBE_ERR_PAYLOAD_FIFO_RAM, - "C2H ST payload RAM single bit ECC error", - QDMA_OFFSET_RAM_SBE_MASK, - QDMA_OFFSET_RAM_SBE_STAT, - QDMA_SBE_ERR_PAYLOAD_FIFO_RAM_MASK, - QDMA_GLBL_ERR_RAM_SBE_MASK, - &qdma_hw_ram_sbe_err_process - }, - { - QDMA_SBE_ERR_QID_FIFO_RAM, - "C2H ST QID FIFO RAM single bit ECC error", - QDMA_OFFSET_RAM_SBE_MASK, - QDMA_OFFSET_RAM_SBE_STAT, - QDMA_SBE_ERR_QID_FIFO_RAM_MASK, - QDMA_GLBL_ERR_RAM_SBE_MASK, - &qdma_hw_ram_sbe_err_process - }, - { - QDMA_SBE_ERR_TUSER_FIFO_RAM, - "C2H ST TUSER RAM single bit ECC error", - QDMA_OFFSET_RAM_SBE_MASK, - QDMA_OFFSET_RAM_SBE_STAT, - QDMA_SBE_ERR_TUSER_FIFO_RAM_MASK, - QDMA_GLBL_ERR_RAM_SBE_MASK, - &qdma_hw_ram_sbe_err_process - }, - { - QDMA_SBE_ERR_WRB_COAL_DATA_RAM, - "Completion Coalescing RAM single bit ECC error", - QDMA_OFFSET_RAM_SBE_MASK, - QDMA_OFFSET_RAM_SBE_STAT, - QDMA_SBE_ERR_WRB_COAL_DATA_RAM_MASK, - QDMA_GLBL_ERR_RAM_SBE_MASK, - &qdma_hw_ram_sbe_err_process - }, - { - QDMA_SBE_ERR_INT_QID2VEC_RAM, - "Interrupt QID2VEC RAM single bit ECC error", - QDMA_OFFSET_RAM_SBE_MASK, - QDMA_OFFSET_RAM_SBE_STAT, - QDMA_SBE_ERR_INT_QID2VEC_RAM_MASK, - QDMA_GLBL_ERR_RAM_SBE_MASK, - &qdma_hw_ram_sbe_err_process - }, - { - QDMA_SBE_ERR_INT_CTXT_RAM, - "Interrupt context RAM single bit ECC error", - QDMA_OFFSET_RAM_SBE_MASK, - QDMA_OFFSET_RAM_SBE_STAT, - QDMA_SBE_ERR_INT_CTXT_RAM_MASK, - QDMA_GLBL_ERR_RAM_SBE_MASK, - &qdma_hw_ram_sbe_err_process - }, - { - QDMA_SBE_ERR_DESC_REQ_FIFO_RAM, - "C2H ST descriptor request RAM single bit ECC error", - QDMA_OFFSET_RAM_SBE_MASK, - QDMA_OFFSET_RAM_SBE_STAT, - QDMA_SBE_ERR_DESC_REQ_FIFO_RAM_MASK, - QDMA_GLBL_ERR_RAM_SBE_MASK, - &qdma_hw_ram_sbe_err_process - }, - { - QDMA_SBE_ERR_PFCH_CTXT_RAM, - "C2H ST prefetch RAM single bit ECC error", - QDMA_OFFSET_RAM_SBE_MASK, - QDMA_OFFSET_RAM_SBE_STAT, - QDMA_SBE_ERR_PFCH_CTXT_RAM_MASK, - QDMA_GLBL_ERR_RAM_SBE_MASK, - &qdma_hw_ram_sbe_err_process - }, - { - QDMA_SBE_ERR_WRB_CTXT_RAM, - "C2H ST completion context RAM single bit ECC error", - QDMA_OFFSET_RAM_SBE_MASK, - QDMA_OFFSET_RAM_SBE_STAT, - QDMA_SBE_ERR_WRB_CTXT_RAM_MASK, - QDMA_GLBL_ERR_RAM_SBE_MASK, - &qdma_hw_ram_sbe_err_process - }, - { - QDMA_SBE_ERR_PFCH_LL_RAM, - "C2H ST prefetch list RAM single bit ECC error", - QDMA_OFFSET_RAM_SBE_MASK, - QDMA_OFFSET_RAM_SBE_STAT, - QDMA_SBE_ERR_PFCH_LL_RAM_MASK, - QDMA_GLBL_ERR_RAM_SBE_MASK, - &qdma_hw_ram_sbe_err_process - }, - { - QDMA_SBE_ERR_H2C_PEND_FIFO, - "H2C ST pending fifo RAM single bit ECC error", - QDMA_OFFSET_RAM_SBE_MASK, - QDMA_OFFSET_RAM_SBE_STAT, - QDMA_SBE_ERR_H2C_PEND_FIFO_MASK, - QDMA_GLBL_ERR_RAM_SBE_MASK, - &qdma_hw_ram_sbe_err_process - }, - { - QDMA_SBE_ERR_ALL, - "All SBE errors", - QDMA_OFFSET_RAM_SBE_MASK, - QDMA_OFFSET_RAM_SBE_STAT, - QDMA_SBE_ERR_ALL_MASK, - QDMA_GLBL_ERR_RAM_SBE_MASK, - &qdma_hw_ram_sbe_err_process - }, - - - /* DBE Errors */ - { - QDMA_DBE_ERR_MI_H2C0_DAT, - "H2C MM data buffer double bit ECC error", - QDMA_OFFSET_RAM_DBE_MASK, - QDMA_OFFSET_RAM_DBE_STAT, - QDMA_DBE_ERR_MI_H2C0_DAT_MASK, - QDMA_GLBL_ERR_RAM_DBE_MASK, - &qdma_hw_ram_dbe_err_process - }, - { - QDMA_DBE_ERR_MI_C2H0_DAT, - "C2H MM data buffer double bit ECC error", - QDMA_OFFSET_RAM_DBE_MASK, - QDMA_OFFSET_RAM_DBE_STAT, - QDMA_DBE_ERR_MI_C2H0_DAT_MASK, - QDMA_GLBL_ERR_RAM_DBE_MASK, - &qdma_hw_ram_dbe_err_process - }, - { - QDMA_DBE_ERR_H2C_RD_BRG_DAT, - "Bridge master read double bit ECC error", - QDMA_OFFSET_RAM_DBE_MASK, - QDMA_OFFSET_RAM_DBE_STAT, - QDMA_DBE_ERR_H2C_RD_BRG_DAT_MASK, - QDMA_GLBL_ERR_RAM_DBE_MASK, - &qdma_hw_ram_dbe_err_process - }, - { - QDMA_DBE_ERR_H2C_WR_BRG_DAT, - "Bridge master write double bit ECC error", - QDMA_OFFSET_RAM_DBE_MASK, - QDMA_OFFSET_RAM_DBE_STAT, - QDMA_DBE_ERR_H2C_WR_BRG_DAT_MASK, - QDMA_GLBL_ERR_RAM_DBE_MASK, - &qdma_hw_ram_dbe_err_process - }, - { - QDMA_DBE_ERR_C2H_RD_BRG_DAT, - "Bridge slave read data buffer double bit ECC error", - QDMA_OFFSET_RAM_DBE_MASK, - QDMA_OFFSET_RAM_DBE_STAT, - QDMA_DBE_ERR_C2H_RD_BRG_DAT_MASK, - QDMA_GLBL_ERR_RAM_DBE_MASK, - &qdma_hw_ram_dbe_err_process - }, - { - QDMA_DBE_ERR_C2H_WR_BRG_DAT, - "Bridge slave write data buffer double bit ECC error", - QDMA_OFFSET_RAM_DBE_MASK, - QDMA_OFFSET_RAM_DBE_STAT, - QDMA_DBE_ERR_C2H_WR_BRG_DAT_MASK, - QDMA_GLBL_ERR_RAM_DBE_MASK, - &qdma_hw_ram_dbe_err_process - }, - { - QDMA_DBE_ERR_FUNC_MAP, - "Function map RAM double bit ECC error", - QDMA_OFFSET_RAM_DBE_MASK, - QDMA_OFFSET_RAM_DBE_STAT, - QDMA_DBE_ERR_FUNC_MAP_MASK, - QDMA_GLBL_ERR_RAM_DBE_MASK, - &qdma_hw_ram_dbe_err_process - }, - { - QDMA_DBE_ERR_DSC_HW_CTXT, - "Descriptor engine hardware context RAM double bit ECC error", - QDMA_OFFSET_RAM_DBE_MASK, - QDMA_OFFSET_RAM_DBE_STAT, - QDMA_DBE_ERR_DSC_HW_CTXT_MASK, - QDMA_GLBL_ERR_RAM_DBE_MASK, - &qdma_hw_ram_dbe_err_process - }, - { - QDMA_DBE_ERR_DSC_CRD_RCV, - "Descriptor engine receive credit context RAM double bit ECC error", - QDMA_OFFSET_RAM_DBE_MASK, - QDMA_OFFSET_RAM_DBE_STAT, - QDMA_DBE_ERR_DSC_CRD_RCV_MASK, - QDMA_GLBL_ERR_RAM_DBE_MASK, - &qdma_hw_ram_dbe_err_process - }, - { - QDMA_DBE_ERR_DSC_SW_CTXT, - "Descriptor engine software context RAM double bit ECC error", - QDMA_OFFSET_RAM_DBE_MASK, - QDMA_OFFSET_RAM_DBE_STAT, - QDMA_DBE_ERR_DSC_SW_CTXT_MASK, - QDMA_GLBL_ERR_RAM_DBE_MASK, - &qdma_hw_ram_dbe_err_process - }, - { - QDMA_DBE_ERR_DSC_CPLI, - "Descriptor engine fetch completion information RAM double bit ECC error", - QDMA_OFFSET_RAM_DBE_MASK, - QDMA_OFFSET_RAM_DBE_STAT, - QDMA_DBE_ERR_DSC_CPLI_MASK, - QDMA_GLBL_ERR_RAM_DBE_MASK, - &qdma_hw_ram_dbe_err_process - }, - { - QDMA_DBE_ERR_DSC_CPLD, - "Descriptor engine fetch completion data RAM double bit ECC error", - QDMA_OFFSET_RAM_DBE_MASK, - QDMA_OFFSET_RAM_DBE_STAT, - QDMA_DBE_ERR_DSC_CPLD_MASK, - QDMA_GLBL_ERR_RAM_DBE_MASK, - &qdma_hw_ram_dbe_err_process - }, - { - QDMA_DBE_ERR_PASID_CTXT_RAM, - "PASID configuration RAM double bit ECC error", - QDMA_OFFSET_RAM_DBE_MASK, - QDMA_OFFSET_RAM_DBE_STAT, - QDMA_DBE_ERR_PASID_CTXT_RAM_MASK, - QDMA_GLBL_ERR_RAM_DBE_MASK, - &qdma_hw_ram_dbe_err_process - }, - { - QDMA_DBE_ERR_TIMER_FIFO_RAM, - "Timer fifo RAM double bit ECC error", - QDMA_OFFSET_RAM_DBE_MASK, - QDMA_OFFSET_RAM_DBE_STAT, - QDMA_DBE_ERR_TIMER_FIFO_RAM_MASK, - QDMA_GLBL_ERR_RAM_DBE_MASK, - &qdma_hw_ram_dbe_err_process - }, - { - QDMA_DBE_ERR_PAYLOAD_FIFO_RAM, - "C2H ST payload RAM double bit ECC error", - QDMA_OFFSET_RAM_DBE_MASK, - QDMA_OFFSET_RAM_DBE_STAT, - QDMA_DBE_ERR_PAYLOAD_FIFO_RAM_MASK, - QDMA_GLBL_ERR_RAM_DBE_MASK, - &qdma_hw_ram_dbe_err_process - }, - { - QDMA_DBE_ERR_QID_FIFO_RAM, - "C2H ST QID FIFO RAM double bit ECC error", - QDMA_OFFSET_RAM_DBE_MASK, - QDMA_OFFSET_RAM_DBE_STAT, - QDMA_DBE_ERR_QID_FIFO_RAM_MASK, - QDMA_GLBL_ERR_RAM_DBE_MASK, - &qdma_hw_ram_dbe_err_process - }, - { - QDMA_DBE_ERR_TUSER_FIFO_RAM, - "C2H ST TUSER RAM double bit ECC error", - QDMA_OFFSET_RAM_DBE_MASK, - QDMA_OFFSET_RAM_DBE_STAT, - QDMA_DBE_ERR_TUSER_FIFO_RAM_MASK, - QDMA_GLBL_ERR_RAM_DBE_MASK, - &qdma_hw_ram_dbe_err_process - }, - { - QDMA_DBE_ERR_WRB_COAL_DATA_RAM, - "Completion Coalescing RAM double bit ECC error", - QDMA_OFFSET_RAM_DBE_MASK, - QDMA_OFFSET_RAM_DBE_STAT, - QDMA_DBE_ERR_WRB_COAL_DATA_RAM_MASK, - QDMA_GLBL_ERR_RAM_DBE_MASK, - &qdma_hw_ram_dbe_err_process - }, - { - QDMA_DBE_ERR_INT_QID2VEC_RAM, - "Interrupt QID2VEC RAM double bit ECC error", - QDMA_OFFSET_RAM_DBE_MASK, - QDMA_OFFSET_RAM_DBE_STAT, - QDMA_DBE_ERR_INT_QID2VEC_RAM_MASK, - QDMA_GLBL_ERR_RAM_DBE_MASK, - &qdma_hw_ram_dbe_err_process - }, - { - QDMA_DBE_ERR_INT_CTXT_RAM, - "Interrupt context RAM double bit ECC error", - QDMA_OFFSET_RAM_DBE_MASK, - QDMA_OFFSET_RAM_DBE_STAT, - QDMA_DBE_ERR_INT_CTXT_RAM_MASK, - QDMA_GLBL_ERR_RAM_DBE_MASK, - &qdma_hw_ram_dbe_err_process - }, - { - QDMA_DBE_ERR_DESC_REQ_FIFO_RAM, - "C2H ST descriptor request RAM double bit ECC error", - QDMA_OFFSET_RAM_DBE_MASK, - QDMA_OFFSET_RAM_DBE_STAT, - QDMA_DBE_ERR_DESC_REQ_FIFO_RAM_MASK, - QDMA_GLBL_ERR_RAM_DBE_MASK, - &qdma_hw_ram_dbe_err_process - }, - { - QDMA_DBE_ERR_PFCH_CTXT_RAM, - "C2H ST prefetch RAM double bit ECC error", - QDMA_OFFSET_RAM_DBE_MASK, - QDMA_OFFSET_RAM_DBE_STAT, - QDMA_DBE_ERR_PFCH_CTXT_RAM_MASK, - QDMA_GLBL_ERR_RAM_DBE_MASK, - &qdma_hw_ram_dbe_err_process - }, - { - QDMA_DBE_ERR_WRB_CTXT_RAM, - "C2H ST completion context RAM double bit ECC error", - QDMA_OFFSET_RAM_DBE_MASK, - QDMA_OFFSET_RAM_DBE_STAT, - QDMA_DBE_ERR_WRB_CTXT_RAM_MASK, - QDMA_GLBL_ERR_RAM_DBE_MASK, - &qdma_hw_ram_dbe_err_process - }, - { - QDMA_DBE_ERR_PFCH_LL_RAM, - "C2H ST prefetch list RAM double bit ECC error", - QDMA_OFFSET_RAM_DBE_MASK, - QDMA_OFFSET_RAM_DBE_STAT, - QDMA_DBE_ERR_PFCH_LL_RAM_MASK, - QDMA_GLBL_ERR_RAM_DBE_MASK, - &qdma_hw_ram_dbe_err_process - }, - { - QDMA_DBE_ERR_H2C_PEND_FIFO, - "H2C pending fifo RAM double bit ECC error", - QDMA_OFFSET_RAM_DBE_MASK, - QDMA_OFFSET_RAM_DBE_STAT, - QDMA_DBE_ERR_H2C_PEND_FIFO_MASK, - QDMA_GLBL_ERR_RAM_DBE_MASK, - &qdma_hw_ram_dbe_err_process - }, - { - QDMA_DBE_ERR_ALL, - "All DBE errors", - QDMA_OFFSET_RAM_DBE_MASK, - QDMA_OFFSET_RAM_DBE_STAT, - QDMA_DBE_ERR_ALL_MASK, - QDMA_GLBL_ERR_RAM_DBE_MASK, - &qdma_hw_ram_dbe_err_process - } -}; - -static int32_t all_hw_errs[TOTAL_LEAF_ERROR_AGGREGATORS] = { - - QDMA_DSC_ERR_ALL, - QDMA_TRQ_ERR_ALL, - QDMA_ST_C2H_ERR_ALL, - QDMA_ST_FATAL_ERR_ALL, - QDMA_ST_H2C_ERR_ALL, - QDMA_SBE_ERR_ALL, - QDMA_DBE_ERR_ALL -}; - -static int qdma_indirect_reg_invalidate(void *dev_hndl, - enum ind_ctxt_cmd_sel sel, uint16_t hw_qid); -static int qdma_indirect_reg_clear(void *dev_hndl, - enum ind_ctxt_cmd_sel sel, uint16_t hw_qid); -static int qdma_indirect_reg_read(void *dev_hndl, enum ind_ctxt_cmd_sel sel, - uint16_t hw_qid, uint32_t cnt, uint32_t *data); -static int qdma_indirect_reg_write(void *dev_hndl, enum ind_ctxt_cmd_sel sel, - uint16_t hw_qid, uint32_t *data, uint16_t cnt); - - -static struct qctx_entry sw_ctxt_entries[] = { - {"PIDX", 0}, - {"IRQ Arm", 0}, - {"Function Id", 0}, - {"Queue Enable", 0}, - {"Fetch Credit Enable", 0}, - {"Write back/Intr Check", 0}, - {"Write back/Intr Interval", 0}, - {"Address Translation", 0}, - {"Fetch Max", 0}, - {"Ring Size", 0}, - {"Descriptor Size", 0}, - {"Bypass Enable", 0}, - {"MM Channel", 0}, - {"Writeback Enable", 0}, - {"Interrupt Enable", 0}, - {"Port Id", 0}, - {"Interrupt No Last", 0}, - {"Error", 0}, - {"Writeback Error Sent", 0}, - {"IRQ Request", 0}, - {"Marker Disable", 0}, - {"Is Memory Mapped", 0}, - {"Descriptor Ring Base Addr (Low)", 0}, - {"Descriptor Ring Base Addr (High)", 0}, - {"Interrupt Vector/Ring Index", 0}, - {"Interrupt Aggregation", 0}, -}; - -static struct qctx_entry hw_ctxt_entries[] = { - {"CIDX", 0}, - {"Credits Consumed", 0}, - {"Descriptors Pending", 0}, - {"Queue Invalid No Desc Pending", 0}, - {"Eviction Pending", 0}, - {"Fetch Pending", 0}, -}; - -static struct qctx_entry credit_ctxt_entries[] = { - {"Credit", 0}, -}; - -static struct qctx_entry cmpt_ctxt_entries[] = { - {"Enable Status Desc Update", 0}, - {"Enable Interrupt", 0}, - {"Trigger Mode", 0}, - {"Function Id", 0}, - {"Counter Index", 0}, - {"Timer Index", 0}, - {"Interrupt State", 0}, - {"Color", 0}, - {"Ring Size", 0}, - {"Base Address (Low)", 0}, - {"Base Address (High)", 0}, - {"Descriptor Size", 0}, - {"PIDX", 0}, - {"CIDX", 0}, - {"Valid", 0}, - {"Error", 0}, - {"Trigger Pending", 0}, - {"Timer Running", 0}, - {"Full Update", 0}, - {"Over Flow Check Disable", 0}, - {"Address Translation", 0}, - {"Interrupt Vector/Ring Index", 0}, - {"Interrupt Aggregation", 0}, -}; - -static struct qctx_entry c2h_pftch_ctxt_entries[] = { - {"Bypass", 0}, - {"Buffer Size Index", 0}, - {"Port Id", 0}, - {"Error", 0}, - {"Prefetch Enable", 0}, - {"In Prefetch", 0}, - {"Software Credit", 0}, - {"Valid", 0}, -}; - -static struct qctx_entry fmap_ctxt_entries[] = { - {"Queue Base", 0}, - {"Queue Max", 0}, -}; - -static struct qctx_entry ind_intr_ctxt_entries[] = { - {"valid", 0}, - {"vec", 0}, - {"int_st", 0}, - {"color", 0}, - {"baddr_4k (Low)", 0}, - {"baddr_4k (High)", 0}, - {"page_size", 0}, - {"pidx", 0}, - {"at", 0}, -}; - -uint32_t qdma_soft_reg_dump_buf_len(void) -{ - uint32_t length = ((sizeof(qdma_config_regs) / - sizeof(qdma_config_regs[0])) + 1) * - REG_DUMP_SIZE_PER_LINE; - return length; -} - -uint32_t qdma_get_config_num_regs(void) -{ - return (sizeof(qdma_config_regs)/ - sizeof(qdma_config_regs[0])); -} - -struct xreg_info *qdma_get_config_regs(void) -{ - return qdma_config_regs; -} - -int qdma_soft_context_buf_len(uint8_t st, - enum qdma_dev_q_type q_type, uint32_t *buflen) -{ - uint32_t len = 0; - int rv = 0; - - *buflen = 0; - - if (q_type == QDMA_DEV_Q_TYPE_CMPT) { - len += (((sizeof(cmpt_ctxt_entries) / - sizeof(cmpt_ctxt_entries[0])) + 1) * - REG_DUMP_SIZE_PER_LINE); - } else { - len += (((sizeof(sw_ctxt_entries) / - sizeof(sw_ctxt_entries[0])) + 1) * - REG_DUMP_SIZE_PER_LINE); - - len += (((sizeof(hw_ctxt_entries) / - sizeof(hw_ctxt_entries[0])) + 1) * - REG_DUMP_SIZE_PER_LINE); - - len += (((sizeof(credit_ctxt_entries) / - sizeof(credit_ctxt_entries[0])) + 1) * - REG_DUMP_SIZE_PER_LINE); - - len += (((sizeof(fmap_ctxt_entries) / - sizeof(fmap_ctxt_entries[0])) + 1) * - REG_DUMP_SIZE_PER_LINE); - - if (st && (q_type == QDMA_DEV_Q_TYPE_C2H)) { - len += (((sizeof(cmpt_ctxt_entries) / - sizeof(cmpt_ctxt_entries[0])) + 1) * - REG_DUMP_SIZE_PER_LINE); - - len += (((sizeof(c2h_pftch_ctxt_entries) / - sizeof(c2h_pftch_ctxt_entries[0])) - + 1) * REG_DUMP_SIZE_PER_LINE); - } - } - - *buflen = len; - return rv; -} - -/* - * qdma_acc_fill_sw_ctxt() - Helper function to fill sw context into structure - * - */ -static void qdma_fill_sw_ctxt(struct qdma_descq_sw_ctxt *sw_ctxt) -{ - sw_ctxt_entries[0].value = sw_ctxt->pidx; - sw_ctxt_entries[1].value = sw_ctxt->irq_arm; - sw_ctxt_entries[2].value = sw_ctxt->fnc_id; - sw_ctxt_entries[3].value = sw_ctxt->qen; - sw_ctxt_entries[4].value = sw_ctxt->frcd_en; - sw_ctxt_entries[5].value = sw_ctxt->wbi_chk; - sw_ctxt_entries[6].value = sw_ctxt->wbi_intvl_en; - sw_ctxt_entries[7].value = sw_ctxt->at; - sw_ctxt_entries[8].value = sw_ctxt->fetch_max; - sw_ctxt_entries[9].value = sw_ctxt->rngsz_idx; - sw_ctxt_entries[10].value = sw_ctxt->desc_sz; - sw_ctxt_entries[11].value = sw_ctxt->bypass; - sw_ctxt_entries[12].value = sw_ctxt->mm_chn; - sw_ctxt_entries[13].value = sw_ctxt->wbk_en; - sw_ctxt_entries[14].value = sw_ctxt->irq_en; - sw_ctxt_entries[15].value = sw_ctxt->port_id; - sw_ctxt_entries[16].value = sw_ctxt->irq_no_last; - sw_ctxt_entries[17].value = sw_ctxt->err; - sw_ctxt_entries[18].value = sw_ctxt->err_wb_sent; - sw_ctxt_entries[19].value = sw_ctxt->irq_req; - sw_ctxt_entries[20].value = sw_ctxt->mrkr_dis; - sw_ctxt_entries[21].value = sw_ctxt->is_mm; - sw_ctxt_entries[22].value = sw_ctxt->ring_bs_addr & 0xFFFFFFFF; - sw_ctxt_entries[23].value = - (sw_ctxt->ring_bs_addr >> 32) & 0xFFFFFFFF; - sw_ctxt_entries[24].value = sw_ctxt->vec; - sw_ctxt_entries[25].value = sw_ctxt->intr_aggr; -} - -/* - * qdma_acc_fill_cmpt_ctxt() - Helper function to fill completion context - * into structure - * - */ -static void qdma_fill_cmpt_ctxt(struct qdma_descq_cmpt_ctxt *cmpt_ctxt) -{ - cmpt_ctxt_entries[0].value = cmpt_ctxt->en_stat_desc; - cmpt_ctxt_entries[1].value = cmpt_ctxt->en_int; - cmpt_ctxt_entries[2].value = cmpt_ctxt->trig_mode; - cmpt_ctxt_entries[3].value = cmpt_ctxt->fnc_id; - cmpt_ctxt_entries[4].value = cmpt_ctxt->counter_idx; - cmpt_ctxt_entries[5].value = cmpt_ctxt->timer_idx; - cmpt_ctxt_entries[6].value = cmpt_ctxt->in_st; - cmpt_ctxt_entries[7].value = cmpt_ctxt->color; - cmpt_ctxt_entries[8].value = cmpt_ctxt->ringsz_idx; - cmpt_ctxt_entries[9].value = cmpt_ctxt->bs_addr & 0xFFFFFFFF; - cmpt_ctxt_entries[10].value = - (cmpt_ctxt->bs_addr >> 32) & 0xFFFFFFFF; - cmpt_ctxt_entries[11].value = cmpt_ctxt->desc_sz; - cmpt_ctxt_entries[12].value = cmpt_ctxt->pidx; - cmpt_ctxt_entries[13].value = cmpt_ctxt->cidx; - cmpt_ctxt_entries[14].value = cmpt_ctxt->valid; - cmpt_ctxt_entries[15].value = cmpt_ctxt->err; - cmpt_ctxt_entries[16].value = cmpt_ctxt->user_trig_pend; - cmpt_ctxt_entries[17].value = cmpt_ctxt->timer_running; - cmpt_ctxt_entries[18].value = cmpt_ctxt->full_upd; - cmpt_ctxt_entries[19].value = cmpt_ctxt->ovf_chk_dis; - cmpt_ctxt_entries[20].value = cmpt_ctxt->at; - cmpt_ctxt_entries[21].value = cmpt_ctxt->vec; - cmpt_ctxt_entries[22].value = cmpt_ctxt->int_aggr; -} - -/* - * qdma_acc_fill_hw_ctxt() - Helper function to fill HW context into structure - * - */ -static void qdma_fill_hw_ctxt(struct qdma_descq_hw_ctxt *hw_ctxt) -{ - hw_ctxt_entries[0].value = hw_ctxt->cidx; - hw_ctxt_entries[1].value = hw_ctxt->crd_use; - hw_ctxt_entries[2].value = hw_ctxt->dsc_pend; - hw_ctxt_entries[3].value = hw_ctxt->idl_stp_b; - hw_ctxt_entries[4].value = hw_ctxt->evt_pnd; - hw_ctxt_entries[5].value = hw_ctxt->fetch_pnd; -} - -/* - * qdma_acc_fill_credit_ctxt() - Helper function to fill Credit context - * into structure - * - */ -static void qdma_fill_credit_ctxt(struct qdma_descq_credit_ctxt *cr_ctxt) -{ - credit_ctxt_entries[0].value = cr_ctxt->credit; -} - -/* - * qdma_acc_fill_pfetch_ctxt() - Helper function to fill Prefetch context - * into structure - * - */ -static void qdma_fill_pfetch_ctxt(struct qdma_descq_prefetch_ctxt *pfetch_ctxt) -{ - c2h_pftch_ctxt_entries[0].value = pfetch_ctxt->bypass; - c2h_pftch_ctxt_entries[1].value = pfetch_ctxt->bufsz_idx; - c2h_pftch_ctxt_entries[2].value = pfetch_ctxt->port_id; - c2h_pftch_ctxt_entries[3].value = pfetch_ctxt->err; - c2h_pftch_ctxt_entries[4].value = pfetch_ctxt->pfch_en; - c2h_pftch_ctxt_entries[5].value = pfetch_ctxt->pfch; - c2h_pftch_ctxt_entries[6].value = pfetch_ctxt->sw_crdt; - c2h_pftch_ctxt_entries[7].value = pfetch_ctxt->valid; -} - -/* - * qdma_acc_fill_fmap_ctxt() - Helper function to fill fmap context - * into structure - * - */ -static void qdma_fill_fmap_ctxt(struct qdma_fmap_cfg *fmap_ctxt) -{ - fmap_ctxt_entries[0].value = fmap_ctxt->qbase; - fmap_ctxt_entries[1].value = fmap_ctxt->qmax; -} - -/* - * dump_soft_context() - Helper function to dump queue context into string - * - * return len - length of the string copied into buffer - */ -static int dump_soft_context(struct qdma_descq_context *queue_context, - uint8_t st, enum qdma_dev_q_type q_type, - char *buf, int buf_sz) -{ - int i = 0; - int n; - int len = 0; - int rv; - char banner[DEBGFS_LINE_SZ]; - - if (queue_context == NULL) { - qdma_log_error("%s: queue_context is NULL, err:%d\n", - __func__, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - if (q_type == QDMA_DEV_Q_TYPE_CMPT) { - qdma_fill_cmpt_ctxt(&queue_context->cmpt_ctxt); - } else if (q_type == QDMA_DEV_Q_TYPE_H2C) { - qdma_fill_sw_ctxt(&queue_context->sw_ctxt); - qdma_fill_hw_ctxt(&queue_context->hw_ctxt); - qdma_fill_credit_ctxt(&queue_context->cr_ctxt); - } else if (q_type == QDMA_DEV_Q_TYPE_C2H) { - qdma_fill_sw_ctxt(&queue_context->sw_ctxt); - qdma_fill_hw_ctxt(&queue_context->hw_ctxt); - qdma_fill_credit_ctxt(&queue_context->cr_ctxt); - if (st) { - qdma_fill_pfetch_ctxt(&queue_context->pfetch_ctxt); - qdma_fill_cmpt_ctxt(&queue_context->cmpt_ctxt); - } - } - - qdma_fill_fmap_ctxt(&queue_context->fmap); - - for (i = 0; i < DEBGFS_LINE_SZ - 5; i++) { - rv = QDMA_SNPRINTF_S(banner + i, - (DEBGFS_LINE_SZ - i), - sizeof("-"), "-"); - if ((rv < 0) || (rv > (int)sizeof("-"))) { - qdma_log_error( - "%d:%s QDMA_SNPRINTF_S() failed, err:%d\n", - __LINE__, __func__, - rv); - goto INSUF_BUF_EXIT; - } - } - - if (q_type != QDMA_DEV_Q_TYPE_CMPT) { - /* SW context dump */ - n = sizeof(sw_ctxt_entries) / sizeof((sw_ctxt_entries)[0]); - for (i = 0; i < n; i++) { - if ((len >= buf_sz) || - ((len + DEBGFS_LINE_SZ) >= buf_sz)) - goto INSUF_BUF_EXIT; - - if (i == 0) { - if ((len + (3 * DEBGFS_LINE_SZ)) >= buf_sz) - goto INSUF_BUF_EXIT; - rv = QDMA_SNPRINTF_S(buf + len, (buf_sz - len), - DEBGFS_LINE_SZ, "\n%s", banner); - if ((rv < 0) || (rv > DEBGFS_LINE_SZ)) { - qdma_log_error( - "%d:%s QDMA_SNPRINTF_S() failed, err:%d\n", - __LINE__, __func__, - rv); - goto INSUF_BUF_EXIT; - } - len += rv; - - rv = QDMA_SNPRINTF_S(buf + len, (buf_sz - len), - DEBGFS_LINE_SZ, "\n%40s", "SW Context"); - if ((rv < 0) || (rv > DEBGFS_LINE_SZ)) { - qdma_log_error( - "%d:%s QDMA_SNPRINTF_S() failed, err:%d\n", - __LINE__, __func__, - rv); - goto INSUF_BUF_EXIT; - } - len += rv; - - rv = QDMA_SNPRINTF_S(buf + len, (buf_sz - len), - DEBGFS_LINE_SZ, "\n%s\n", banner); - if ((rv < 0) || (rv > DEBGFS_LINE_SZ)) { - qdma_log_error( - "%d:%s QDMA_SNPRINTF_S() failed, err:%d\n", - __LINE__, __func__, - rv); - goto INSUF_BUF_EXIT; - } - len += rv; - } - - rv = QDMA_SNPRINTF_S(buf + len, - (buf_sz - len), DEBGFS_LINE_SZ, - "%-47s %#-10x %u\n", - sw_ctxt_entries[i].name, - sw_ctxt_entries[i].value, - sw_ctxt_entries[i].value); - if ((rv < 0) || (rv > DEBGFS_LINE_SZ)) { - qdma_log_error( - "%d:%s QDMA_SNPRINTF_S() failed, err:%d\n", - __LINE__, __func__, - rv); - goto INSUF_BUF_EXIT; - } - len += rv; - } - - /* HW context dump */ - n = sizeof(hw_ctxt_entries) / sizeof((hw_ctxt_entries)[0]); - for (i = 0; i < n; i++) { - if ((len >= buf_sz) || - ((len + DEBGFS_LINE_SZ) >= buf_sz)) - goto INSUF_BUF_EXIT; - - if (i == 0) { - if ((len + (3 * DEBGFS_LINE_SZ)) >= buf_sz) - goto INSUF_BUF_EXIT; - - rv = QDMA_SNPRINTF_S(buf + len, (buf_sz - len), - DEBGFS_LINE_SZ, "\n%s", banner); - if ((rv < 0) || (rv > DEBGFS_LINE_SZ)) { - qdma_log_error( - "%d:%s QDMA_SNPRINTF_S() failed, err:%d\n", - __LINE__, __func__, - rv); - goto INSUF_BUF_EXIT; - } - len += rv; - - rv = QDMA_SNPRINTF_S(buf + len, (buf_sz - len), - DEBGFS_LINE_SZ, "\n%40s", "HW Context"); - if ((rv < 0) || (rv > DEBGFS_LINE_SZ)) { - qdma_log_error( - "%d:%s QDMA_SNPRINTF_S() failed, err:%d\n", - __LINE__, __func__, - rv); - goto INSUF_BUF_EXIT; - } - len += rv; - - rv = QDMA_SNPRINTF_S(buf + len, (buf_sz - len), - DEBGFS_LINE_SZ, "\n%s\n", banner); - if ((rv < 0) || (rv > DEBGFS_LINE_SZ)) { - qdma_log_error( - "%d:%s QDMA_SNPRINTF_S() failed, err:%d\n", - __LINE__, __func__, - rv); - goto INSUF_BUF_EXIT; - } - len += rv; - } - - rv = QDMA_SNPRINTF_S(buf + len, - (buf_sz - len), DEBGFS_LINE_SZ, - "%-47s %#-10x %u\n", - hw_ctxt_entries[i].name, - hw_ctxt_entries[i].value, - hw_ctxt_entries[i].value); - if ((rv < 0) || (rv > DEBGFS_LINE_SZ)) { - qdma_log_error( - "%d:%s QDMA_SNPRINTF_S() failed, err:%d\n", - __LINE__, __func__, - rv); - goto INSUF_BUF_EXIT; - } - len += rv; - } - - /* Credit context dump */ - n = sizeof(credit_ctxt_entries) / - sizeof((credit_ctxt_entries)[0]); - for (i = 0; i < n; i++) { - if ((len >= buf_sz) || - ((len + DEBGFS_LINE_SZ) >= buf_sz)) - goto INSUF_BUF_EXIT; - - if (i == 0) { - if ((len + (3 * DEBGFS_LINE_SZ)) >= buf_sz) - goto INSUF_BUF_EXIT; - - rv = QDMA_SNPRINTF_S(buf + len, (buf_sz - len), - DEBGFS_LINE_SZ, "\n%s", banner); - if ((rv < 0) || (rv > DEBGFS_LINE_SZ)) { - qdma_log_error( - "%d:%s QDMA_SNPRINTF_S() failed, err:%d\n", - __LINE__, __func__, - rv); - goto INSUF_BUF_EXIT; - } - len += rv; - - rv = QDMA_SNPRINTF_S(buf + len, (buf_sz - len), - DEBGFS_LINE_SZ, "\n%40s", - "Credit Context"); - if ((rv < 0) || (rv > DEBGFS_LINE_SZ)) { - qdma_log_error( - "%d:%s QDMA_SNPRINTF_S() failed, err:%d\n", - __LINE__, __func__, - rv); - goto INSUF_BUF_EXIT; - } - len += rv; - - rv = QDMA_SNPRINTF_S(buf + len, (buf_sz - len), - DEBGFS_LINE_SZ, "\n%s\n", banner); - if ((rv < 0) || (rv > DEBGFS_LINE_SZ)) { - qdma_log_error( - "%d:%s QDMA_SNPRINTF_S() failed, err:%d\n", - __LINE__, __func__, - rv); - goto INSUF_BUF_EXIT; - } - len += rv; - } - - rv = QDMA_SNPRINTF_S(buf + len, - (buf_sz - len), DEBGFS_LINE_SZ, - "%-47s %#-10x %u\n", - credit_ctxt_entries[i].name, - credit_ctxt_entries[i].value, - credit_ctxt_entries[i].value); - if ((rv < 0) || (rv > DEBGFS_LINE_SZ)) { - qdma_log_error( - "%d:%s QDMA_SNPRINTF_S() failed, err:%d\n", - __LINE__, __func__, - rv); - goto INSUF_BUF_EXIT; - } - len += rv; - } - } - - if ((q_type == QDMA_DEV_Q_TYPE_CMPT) || - (st && q_type == QDMA_DEV_Q_TYPE_C2H)) { - /* Completion context dump */ - n = sizeof(cmpt_ctxt_entries) / sizeof((cmpt_ctxt_entries)[0]); - for (i = 0; i < n; i++) { - if ((len >= buf_sz) || - ((len + DEBGFS_LINE_SZ) >= buf_sz)) - goto INSUF_BUF_EXIT; - - if (i == 0) { - if ((len + (3 * DEBGFS_LINE_SZ)) >= buf_sz) - goto INSUF_BUF_EXIT; - - rv = QDMA_SNPRINTF_S(buf + len, (buf_sz - len), - DEBGFS_LINE_SZ, "\n%s", banner); - if ((rv < 0) || (rv > DEBGFS_LINE_SZ)) { - qdma_log_error( - "%d:%s QDMA_SNPRINTF_S() failed, err:%d\n", - __LINE__, __func__, - rv); - goto INSUF_BUF_EXIT; - } - len += rv; - - rv = QDMA_SNPRINTF_S(buf + len, (buf_sz - len), - DEBGFS_LINE_SZ, "\n%40s", - "Completion Context"); - if ((rv < 0) || (rv > DEBGFS_LINE_SZ)) { - qdma_log_error( - "%d:%s QDMA_SNPRINTF_S() failed, err:%d\n", - __LINE__, __func__, - rv); - goto INSUF_BUF_EXIT; - } - len += rv; - - rv = QDMA_SNPRINTF_S(buf + len, (buf_sz - len), - DEBGFS_LINE_SZ, "\n%s\n", banner); - if ((rv < 0) || (rv > DEBGFS_LINE_SZ)) { - qdma_log_error( - "%d:%s QDMA_SNPRINTF_S() failed, err:%d\n", - __LINE__, __func__, - rv); - goto INSUF_BUF_EXIT; - } - len += rv; - } - - rv = QDMA_SNPRINTF_S(buf + len, - (buf_sz - len), DEBGFS_LINE_SZ, - "%-47s %#-10x %u\n", - cmpt_ctxt_entries[i].name, - cmpt_ctxt_entries[i].value, - cmpt_ctxt_entries[i].value); - if ((rv < 0) || (rv > DEBGFS_LINE_SZ)) { - qdma_log_error( - "%d:%s QDMA_SNPRINTF_S() failed, err:%d\n", - __LINE__, __func__, - rv); - goto INSUF_BUF_EXIT; - } - len += rv; - } - } - - if (st && q_type == QDMA_DEV_Q_TYPE_C2H) { - /* Prefetch context dump */ - n = sizeof(c2h_pftch_ctxt_entries) / - sizeof(c2h_pftch_ctxt_entries[0]); - for (i = 0; i < n; i++) { - if ((len >= buf_sz) || - ((len + DEBGFS_LINE_SZ) >= buf_sz)) - goto INSUF_BUF_EXIT; - - if (i == 0) { - if ((len + (3 * DEBGFS_LINE_SZ)) >= buf_sz) - goto INSUF_BUF_EXIT; - - rv = QDMA_SNPRINTF_S(buf + len, (buf_sz - len), - DEBGFS_LINE_SZ, "\n%s", banner); - if ((rv < 0) || (rv > DEBGFS_LINE_SZ)) { - qdma_log_error( - "%d:%s QDMA_SNPRINTF_S() failed, err:%d\n", - __LINE__, __func__, - rv); - goto INSUF_BUF_EXIT; - } - len += rv; - - rv = QDMA_SNPRINTF_S(buf + len, (buf_sz - len), - DEBGFS_LINE_SZ, "\n%40s", - "Prefetch Context"); - if ((rv < 0) || (rv > DEBGFS_LINE_SZ)) { - qdma_log_error( - "%d:%s QDMA_SNPRINTF_S() failed, err:%d\n", - __LINE__, __func__, - rv); - goto INSUF_BUF_EXIT; - } - len += rv; - - rv = QDMA_SNPRINTF_S(buf + len, (buf_sz - len), - DEBGFS_LINE_SZ, "\n%s\n", banner); - if ((rv < 0) || (rv > DEBGFS_LINE_SZ)) { - qdma_log_error( - "%d:%s QDMA_SNPRINTF_S() failed, err:%d\n", - __LINE__, __func__, - rv); - goto INSUF_BUF_EXIT; - } - len += rv; - } - - rv = QDMA_SNPRINTF_S(buf + len, - (buf_sz - len), DEBGFS_LINE_SZ, - "%-47s %#-10x %u\n", - c2h_pftch_ctxt_entries[i].name, - c2h_pftch_ctxt_entries[i].value, - c2h_pftch_ctxt_entries[i].value); - if ((rv < 0) || (rv > DEBGFS_LINE_SZ)) { - qdma_log_error( - "%d:%s QDMA_SNPRINTF_S() failed, err:%d\n", - __LINE__, __func__, - rv); - goto INSUF_BUF_EXIT; - } - len += rv; - } - } - - /* Fmap context dump */ - n = sizeof(fmap_ctxt_entries) / - sizeof(fmap_ctxt_entries[0]); - for (i = 0; i < n; i++) { - if ((len >= buf_sz) || - ((len + DEBGFS_LINE_SZ) >= buf_sz)) - goto INSUF_BUF_EXIT; - - if (i == 0) { - if ((len + (3 * DEBGFS_LINE_SZ)) >= buf_sz) - goto INSUF_BUF_EXIT; - - rv = QDMA_SNPRINTF_S(buf + len, (buf_sz - len), - DEBGFS_LINE_SZ, "\n%s", banner); - if ((rv < 0) || (rv > DEBGFS_LINE_SZ)) { - qdma_log_error( - "%d:%s QDMA_SNPRINTF_S() failed, err:%d\n", - __LINE__, __func__, - rv); - goto INSUF_BUF_EXIT; - } - len += rv; - - rv = QDMA_SNPRINTF_S(buf + len, (buf_sz - len), - DEBGFS_LINE_SZ, "\n%40s", - "Fmap Context"); - if ((rv < 0) || (rv > DEBGFS_LINE_SZ)) { - qdma_log_error( - "%d:%s QDMA_SNPRINTF_S() failed, err:%d\n", - __LINE__, __func__, - rv); - goto INSUF_BUF_EXIT; - } - len += rv; - - rv = QDMA_SNPRINTF_S(buf + len, (buf_sz - len), - DEBGFS_LINE_SZ, "\n%s\n", banner); - if ((rv < 0) || (rv > DEBGFS_LINE_SZ)) { - qdma_log_error( - "%d:%s QDMA_SNPRINTF_S() failed, err:%d\n", - __LINE__, __func__, - rv); - goto INSUF_BUF_EXIT; - } - len += rv; - } - - rv = QDMA_SNPRINTF_S(buf + len, - (buf_sz - len), DEBGFS_LINE_SZ, - "%-47s %#-10x %u\n", - fmap_ctxt_entries[i].name, - fmap_ctxt_entries[i].value, - fmap_ctxt_entries[i].value); - if ((rv < 0) || (rv > DEBGFS_LINE_SZ)) { - qdma_log_error( - "%d:%s QDMA_SNPRINTF_S() failed, err:%d\n", - __LINE__, __func__, - rv); - goto INSUF_BUF_EXIT; - } - len += rv; - } - - return len; - -INSUF_BUF_EXIT: - if (buf_sz > DEBGFS_LINE_SZ) { - rv = QDMA_SNPRINTF_S((buf + buf_sz - DEBGFS_LINE_SZ), - buf_sz, DEBGFS_LINE_SZ, - "\n\nInsufficient buffer size, partial context dump\n"); - if ((rv < 0) || (rv > DEBGFS_LINE_SZ)) { - qdma_log_error( - "%d:%s QDMA_SNPRINTF_S() failed, err:%d\n", - __LINE__, __func__, - rv); - } - } - - qdma_log_error("%s: Insufficient buffer size, err:%d\n", - __func__, -QDMA_ERR_NO_MEM); - - return -QDMA_ERR_NO_MEM; -} - -/* - * qdma_indirect_reg_invalidate() - helper function to invalidate indirect - * context registers. - * - * return -QDMA_ERR_HWACC_BUSY_TIMEOUT if register - * value didn't match, QDMA_SUCCESS other wise - */ -static int qdma_indirect_reg_invalidate(void *dev_hndl, - enum ind_ctxt_cmd_sel sel, uint16_t hw_qid) -{ - union qdma_ind_ctxt_cmd cmd; - - qdma_reg_access_lock(dev_hndl); - - /* set command register */ - cmd.word = 0; - cmd.bits.qid = hw_qid; - cmd.bits.op = QDMA_CTXT_CMD_INV; - cmd.bits.sel = sel; - qdma_reg_write(dev_hndl, QDMA_OFFSET_IND_CTXT_CMD, cmd.word); - - /* check if the operation went through well */ - if (hw_monitor_reg(dev_hndl, QDMA_OFFSET_IND_CTXT_CMD, - QDMA_IND_CTXT_CMD_BUSY_MASK, 0, - QDMA_REG_POLL_DFLT_INTERVAL_US, - QDMA_REG_POLL_DFLT_TIMEOUT_US)) { - qdma_reg_access_release(dev_hndl); - qdma_log_error("%s: hw_monitor_reg failed with err:%d\n", - __func__, - -QDMA_ERR_HWACC_BUSY_TIMEOUT); - return -QDMA_ERR_HWACC_BUSY_TIMEOUT; - } - - qdma_reg_access_release(dev_hndl); - - return QDMA_SUCCESS; -} - -/* - * qdma_indirect_reg_clear() - helper function to clear indirect - * context registers. - * - * return -QDMA_ERR_HWACC_BUSY_TIMEOUT if register - * value didn't match, QDMA_SUCCESS other wise - */ -static int qdma_indirect_reg_clear(void *dev_hndl, - enum ind_ctxt_cmd_sel sel, uint16_t hw_qid) -{ - union qdma_ind_ctxt_cmd cmd; - - qdma_reg_access_lock(dev_hndl); - - /* set command register */ - cmd.word = 0; - cmd.bits.qid = hw_qid; - cmd.bits.op = QDMA_CTXT_CMD_CLR; - cmd.bits.sel = sel; - qdma_reg_write(dev_hndl, QDMA_OFFSET_IND_CTXT_CMD, cmd.word); - - /* check if the operation went through well */ - if (hw_monitor_reg(dev_hndl, QDMA_OFFSET_IND_CTXT_CMD, - QDMA_IND_CTXT_CMD_BUSY_MASK, 0, - QDMA_REG_POLL_DFLT_INTERVAL_US, - QDMA_REG_POLL_DFLT_TIMEOUT_US)) { - qdma_reg_access_release(dev_hndl); - qdma_log_error("%s: hw_monitor_reg failed with err:%d\n", - __func__, - -QDMA_ERR_HWACC_BUSY_TIMEOUT); - return -QDMA_ERR_HWACC_BUSY_TIMEOUT; - } - - qdma_reg_access_release(dev_hndl); - - return QDMA_SUCCESS; -} - -/* - * qdma_indirect_reg_read() - helper function to read indirect - * context registers. - * - * return -QDMA_ERR_HWACC_BUSY_TIMEOUT if register - * value didn't match, QDMA_SUCCESS other wise - */ -static int qdma_indirect_reg_read(void *dev_hndl, enum ind_ctxt_cmd_sel sel, - uint16_t hw_qid, uint32_t cnt, uint32_t *data) -{ - uint32_t index = 0, reg_addr = QDMA_OFFSET_IND_CTXT_DATA; - union qdma_ind_ctxt_cmd cmd; - - qdma_reg_access_lock(dev_hndl); - - /* set command register */ - cmd.word = 0; - cmd.bits.qid = hw_qid; - cmd.bits.op = QDMA_CTXT_CMD_RD; - cmd.bits.sel = sel; - qdma_reg_write(dev_hndl, QDMA_OFFSET_IND_CTXT_CMD, cmd.word); - - /* check if the operation went through well */ - if (hw_monitor_reg(dev_hndl, QDMA_OFFSET_IND_CTXT_CMD, - QDMA_IND_CTXT_CMD_BUSY_MASK, 0, - QDMA_REG_POLL_DFLT_INTERVAL_US, - QDMA_REG_POLL_DFLT_TIMEOUT_US)) { - qdma_reg_access_release(dev_hndl); - qdma_log_error("%s: hw_monitor_reg failed with err:%d\n", - __func__, - -QDMA_ERR_HWACC_BUSY_TIMEOUT); - return -QDMA_ERR_HWACC_BUSY_TIMEOUT; - } - - for (index = 0; index < cnt; index++, reg_addr += sizeof(uint32_t)) - data[index] = qdma_reg_read(dev_hndl, reg_addr); - - qdma_reg_access_release(dev_hndl); - - return QDMA_SUCCESS; -} - -/* - * qdma_indirect_reg_write() - helper function to write indirect - * context registers. - * - * return -QDMA_ERR_HWACC_BUSY_TIMEOUT if register - * value didn't match, QDMA_SUCCESS other wise - */ -static int qdma_indirect_reg_write(void *dev_hndl, enum ind_ctxt_cmd_sel sel, - uint16_t hw_qid, uint32_t *data, uint16_t cnt) -{ - uint32_t index, reg_addr; - struct qdma_indirect_ctxt_regs regs; - uint32_t *wr_data = (uint32_t *)®s; - - qdma_reg_access_lock(dev_hndl); - - /* write the context data */ - for (index = 0; index < QDMA_IND_CTXT_DATA_NUM_REGS; index++) { - if (index < cnt) - regs.qdma_ind_ctxt_data[index] = data[index]; - else - regs.qdma_ind_ctxt_data[index] = 0; - regs.qdma_ind_ctxt_mask[index] = 0xFFFFFFFF; - } - - regs.cmd.word = 0; - regs.cmd.bits.qid = hw_qid; - regs.cmd.bits.op = QDMA_CTXT_CMD_WR; - regs.cmd.bits.sel = sel; - reg_addr = QDMA_OFFSET_IND_CTXT_DATA; - - for (index = 0; index < ((2 * QDMA_IND_CTXT_DATA_NUM_REGS) + 1); - index++, reg_addr += sizeof(uint32_t)) - qdma_reg_write(dev_hndl, reg_addr, wr_data[index]); - - /* check if the operation went through well */ - if (hw_monitor_reg(dev_hndl, QDMA_OFFSET_IND_CTXT_CMD, - QDMA_IND_CTXT_CMD_BUSY_MASK, 0, - QDMA_REG_POLL_DFLT_INTERVAL_US, - QDMA_REG_POLL_DFLT_TIMEOUT_US)) { - qdma_reg_access_release(dev_hndl); - qdma_log_error("%s: hw_monitor_reg failed with err:%d\n", - __func__, - -QDMA_ERR_HWACC_BUSY_TIMEOUT); - return -QDMA_ERR_HWACC_BUSY_TIMEOUT; - } - - qdma_reg_access_release(dev_hndl); - - return QDMA_SUCCESS; -} - -/*****************************************************************************/ -/** - * qdma_get_version() - Function to get the qdma version - * - * @dev_hndl: device handle - * @is_vf: Whether PF or VF - * @version_info: pointer to hold the version info - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -int qdma_get_version(void *dev_hndl, uint8_t is_vf, - struct qdma_hw_version_info *version_info) -{ - uint32_t reg_val = 0; - uint32_t reg_addr = (is_vf) ? QDMA_OFFSET_VF_VERSION : - QDMA_OFFSET_GLBL2_MISC_CAP; - - if (!dev_hndl) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - reg_val = qdma_reg_read(dev_hndl, reg_addr); - - qdma_fetch_version_details(dev_hndl, is_vf, reg_val, version_info); - - return QDMA_SUCCESS; -} - -/*****************************************************************************/ -/** - * qdma_fmap_write() - create fmap context and program it - * - * @dev_hndl: device handle - * @func_id: function id of the device - * @config: pointer to the fmap data strucutre - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -static int qdma_fmap_write(void *dev_hndl, uint16_t func_id, - const struct qdma_fmap_cfg *config) -{ - uint32_t fmap[QDMA_FMAP_NUM_WORDS] = {0}; - uint16_t num_words_count = 0; - enum ind_ctxt_cmd_sel sel = QDMA_CTXT_SEL_FMAP; - - if (!dev_hndl || !config) { - qdma_log_error("%s: dev_handle=%p fmap=%p NULL, err:%d\n", - __func__, dev_hndl, config, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - qdma_log_debug("%s: func_id=%hu, qbase=%hu, qmax=%hu\n", __func__, - func_id, config->qbase, config->qmax); - fmap[num_words_count++] = - FIELD_SET(QDMA_FMAP_CTXT_W0_QID_MASK, config->qbase); - fmap[num_words_count++] = - FIELD_SET(QDMA_FMAP_CTXT_W1_QID_MAX_MASK, config->qmax); - - return qdma_indirect_reg_write(dev_hndl, sel, func_id, - fmap, num_words_count); -} - -/*****************************************************************************/ -/** - * qdma_fmap_read() - read fmap context - * - * @dev_hndl: device handle - * @func_id: function id of the device - * @config: pointer to the output fmap data - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -static int qdma_fmap_read(void *dev_hndl, uint16_t func_id, - struct qdma_fmap_cfg *config) -{ - int rv = QDMA_SUCCESS; - uint32_t fmap[QDMA_FMAP_NUM_WORDS] = {0}; - enum ind_ctxt_cmd_sel sel = QDMA_CTXT_SEL_FMAP; - - if (!dev_hndl || !config) { - qdma_log_error("%s: dev_handle=%p fmap=%p NULL, err:%d\n", - __func__, dev_hndl, config, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - rv = qdma_indirect_reg_read(dev_hndl, sel, func_id, - QDMA_FMAP_NUM_WORDS, fmap); - if (rv < 0) - return rv; - - config->qbase = FIELD_GET(QDMA_FMAP_CTXT_W0_QID_MASK, fmap[0]); - config->qmax = FIELD_GET(QDMA_FMAP_CTXT_W1_QID_MAX_MASK, fmap[1]); - - qdma_log_debug("%s: func_id=%hu, qbase=%hu, qmax=%hu\n", __func__, - func_id, config->qbase, config->qmax); - - return QDMA_SUCCESS; -} - -/*****************************************************************************/ -/** - * qdma_fmap_clear() - clear fmap context - * - * @dev_hndl: device handle - * @func_id: function id of the device - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -static int qdma_fmap_clear(void *dev_hndl, uint16_t func_id) -{ - enum ind_ctxt_cmd_sel sel = QDMA_CTXT_SEL_FMAP; - - if (!dev_hndl) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", __func__, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - qdma_log_debug("%s: func_id=%hu\n", __func__, func_id); - return qdma_indirect_reg_clear(dev_hndl, sel, func_id); -} - -/*****************************************************************************/ -/** - * qdma_fmap_conf() - configure fmap context - * - * @dev_hndl: device handle - * @func_id: function id of the device - * @config: pointer to the fmap data - * @access_type HW access type (qdma_hw_access_type enum) value - * QDMA_HW_ACCESS_INVALIDATE Not supported - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -int qdma_fmap_conf(void *dev_hndl, uint16_t func_id, - struct qdma_fmap_cfg *config, - enum qdma_hw_access_type access_type) -{ - int rv = QDMA_SUCCESS; - - switch (access_type) { - case QDMA_HW_ACCESS_READ: - rv = qdma_fmap_read(dev_hndl, func_id, config); - break; - case QDMA_HW_ACCESS_WRITE: - rv = qdma_fmap_write(dev_hndl, func_id, config); - break; - case QDMA_HW_ACCESS_CLEAR: - rv = qdma_fmap_clear(dev_hndl, func_id); - break; - case QDMA_HW_ACCESS_INVALIDATE: - default: - qdma_log_error("%s: access_type(%d) invalid, err:%d\n", - __func__, - access_type, - -QDMA_ERR_INV_PARAM); - rv = -QDMA_ERR_INV_PARAM; - break; - } - - return rv; -} - -/*****************************************************************************/ -/** - * qdma_sw_context_write() - create sw context and program it - * - * @dev_hndl: device handle - * @c2h: is c2h queue - * @hw_qid: hardware qid of the queue - * @ctxt: pointer to the SW context data strucutre - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -static int qdma_sw_context_write(void *dev_hndl, uint8_t c2h, - uint16_t hw_qid, - const struct qdma_descq_sw_ctxt *ctxt) -{ - uint32_t sw_ctxt[QDMA_SW_CONTEXT_NUM_WORDS] = {0}; - uint16_t num_words_count = 0; - enum ind_ctxt_cmd_sel sel = c2h ? - QDMA_CTXT_SEL_SW_C2H : QDMA_CTXT_SEL_SW_H2C; - - /* Input args check */ - if (!dev_hndl || !ctxt) { - qdma_log_error("%s: dev_handle=%p sw_ctxt=%p NULL, err:%d\n", - __func__, dev_hndl, ctxt, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - sw_ctxt[num_words_count++] = - FIELD_SET(QDMA_SW_CTXT_W0_PIDX, ctxt->pidx) | - FIELD_SET(QDMA_SW_CTXT_W0_IRQ_ARM_MASK, ctxt->irq_arm) | - FIELD_SET(QDMA_SW_CTXT_W0_FUNC_ID_MASK, ctxt->fnc_id); - - qdma_log_debug("%s: pidx=%x, irq_arm=%x, fnc_id=%x\n", - __func__, ctxt->pidx, ctxt->irq_arm, ctxt->fnc_id); - - sw_ctxt[num_words_count++] = - FIELD_SET(QDMA_SW_CTXT_W1_QEN_MASK, ctxt->qen) | - FIELD_SET(QDMA_SW_CTXT_W1_FCRD_EN_MASK, ctxt->frcd_en) | - FIELD_SET(QDMA_SW_CTXT_W1_WBI_CHK_MASK, ctxt->wbi_chk) | - FIELD_SET(QDMA_SW_CTXT_W1_WB_INT_EN_MASK, ctxt->wbi_intvl_en) | - FIELD_SET(QDMA_SW_CTXT_W1_AT_MASK, ctxt->at) | - FIELD_SET(QDMA_SW_CTXT_W1_FETCH_MAX_MASK, ctxt->fetch_max) | - FIELD_SET(QDMA_SW_CTXT_W1_RNG_SZ_MASK, ctxt->rngsz_idx) | - FIELD_SET(QDMA_SW_CTXT_W1_DSC_SZ_MASK, ctxt->desc_sz) | - FIELD_SET(QDMA_SW_CTXT_W1_BYP_MASK, ctxt->bypass) | - FIELD_SET(QDMA_SW_CTXT_W1_MM_CHN_MASK, ctxt->mm_chn) | - FIELD_SET(QDMA_SW_CTXT_W1_WBK_EN_MASK, ctxt->wbk_en) | - FIELD_SET(QDMA_SW_CTXT_W1_IRQ_EN_MASK, ctxt->irq_en) | - FIELD_SET(QDMA_SW_CTXT_W1_PORT_ID_MASK, ctxt->port_id) | - FIELD_SET(QDMA_SW_CTXT_W1_IRQ_NO_LAST_MASK, ctxt->irq_no_last) | - FIELD_SET(QDMA_SW_CTXT_W1_ERR_MASK, ctxt->err) | - FIELD_SET(QDMA_SW_CTXT_W1_ERR_WB_SENT_MASK, ctxt->err_wb_sent) | - FIELD_SET(QDMA_SW_CTXT_W1_IRQ_REQ_MASK, ctxt->irq_req) | - FIELD_SET(QDMA_SW_CTXT_W1_MRKR_DIS_MASK, ctxt->mrkr_dis) | - FIELD_SET(QDMA_SW_CTXT_W1_IS_MM_MASK, ctxt->is_mm); - - qdma_log_debug("%s: qen=%x, frcd_en=%x, wbi_chk=%x, wbi_intvl_en=%x\n", - __func__, ctxt->qen, ctxt->frcd_en, ctxt->wbi_chk, - ctxt->wbi_intvl_en); - - qdma_log_debug("%s: at=%x, fetch_max=%x, rngsz_idx=%x, desc_sz=%x\n", - __func__, ctxt->at, ctxt->fetch_max, ctxt->rngsz_idx, - ctxt->desc_sz); - - qdma_log_debug("%s: bypass=%x, mm_chn=%x, wbk_en=%x, irq_en=%x\n", - __func__, ctxt->bypass, ctxt->mm_chn, ctxt->wbk_en, - ctxt->irq_en); - - qdma_log_debug("%s: port_id=%x, irq_no_last=%x,err=%x", - __func__, ctxt->port_id, ctxt->irq_no_last, ctxt->err); - qdma_log_debug(", err_wb_sent=%x\n", ctxt->err_wb_sent); - - qdma_log_debug("%s: irq_req=%x, mrkr_dis=%x, is_mm=%x\n", - __func__, ctxt->irq_req, ctxt->mrkr_dis, ctxt->is_mm); - - sw_ctxt[num_words_count++] = ctxt->ring_bs_addr & 0xffffffff; - sw_ctxt[num_words_count++] = (ctxt->ring_bs_addr >> 32) & 0xffffffff; - - sw_ctxt[num_words_count++] = - FIELD_SET(QDMA_SW_CTXT_W4_VEC_MASK, ctxt->vec) | - FIELD_SET(QDMA_SW_CTXT_W4_INTR_AGGR_MASK, ctxt->intr_aggr); - - qdma_log_debug("%s: vec=%x, intr_aggr=%x\n", - __func__, ctxt->vec, ctxt->intr_aggr); - - return qdma_indirect_reg_write(dev_hndl, sel, hw_qid, - sw_ctxt, num_words_count); -} - -/*****************************************************************************/ -/** - * qdma_sw_context_read() - read sw context - * - * @dev_hndl: device handle - * @c2h: is c2h queue - * @hw_qid: hardware qid of the queue - * @ctxt: pointer to the output context data - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -static int qdma_sw_context_read(void *dev_hndl, uint8_t c2h, - uint16_t hw_qid, - struct qdma_descq_sw_ctxt *ctxt) -{ - int rv = QDMA_SUCCESS; - uint32_t sw_ctxt[QDMA_SW_CONTEXT_NUM_WORDS] = {0}; - enum ind_ctxt_cmd_sel sel = c2h ? - QDMA_CTXT_SEL_SW_C2H : QDMA_CTXT_SEL_SW_H2C; - - if (!dev_hndl || !ctxt) { - qdma_log_error("%s: dev_handle=%p sw_ctxt=%p NULL, err:%d\n", - __func__, dev_hndl, ctxt, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - rv = qdma_indirect_reg_read(dev_hndl, sel, hw_qid, - QDMA_SW_CONTEXT_NUM_WORDS, sw_ctxt); - if (rv < 0) - return rv; - - ctxt->pidx = FIELD_GET(QDMA_SW_CTXT_W0_PIDX, sw_ctxt[0]); - ctxt->irq_arm = - (uint8_t)(FIELD_GET(QDMA_SW_CTXT_W0_IRQ_ARM_MASK, sw_ctxt[0])); - ctxt->fnc_id = - (uint8_t)(FIELD_GET(QDMA_SW_CTXT_W0_FUNC_ID_MASK, sw_ctxt[0])); - - qdma_log_debug("%s: pidx=%x, irq_arm=%x, fnc_id=%x", - __func__, ctxt->pidx, ctxt->irq_arm, ctxt->fnc_id); - - ctxt->qen = FIELD_GET(QDMA_SW_CTXT_W1_QEN_MASK, sw_ctxt[1]); - ctxt->frcd_en = FIELD_GET(QDMA_SW_CTXT_W1_FCRD_EN_MASK, sw_ctxt[1]); - ctxt->wbi_chk = FIELD_GET(QDMA_SW_CTXT_W1_WBI_CHK_MASK, sw_ctxt[1]); - ctxt->wbi_intvl_en = - FIELD_GET(QDMA_SW_CTXT_W1_WB_INT_EN_MASK, sw_ctxt[1]); - ctxt->at = FIELD_GET(QDMA_SW_CTXT_W1_AT_MASK, sw_ctxt[1]); - ctxt->fetch_max = - FIELD_GET(QDMA_SW_CTXT_W1_FETCH_MAX_MASK, sw_ctxt[1]); - ctxt->rngsz_idx = - (uint8_t)(FIELD_GET(QDMA_SW_CTXT_W1_RNG_SZ_MASK, sw_ctxt[1])); - ctxt->desc_sz = - (uint8_t)(FIELD_GET(QDMA_SW_CTXT_W1_DSC_SZ_MASK, sw_ctxt[1])); - ctxt->bypass = - (uint8_t)(FIELD_GET(QDMA_SW_CTXT_W1_BYP_MASK, sw_ctxt[1])); - ctxt->mm_chn = - (uint8_t)(FIELD_GET(QDMA_SW_CTXT_W1_MM_CHN_MASK, sw_ctxt[1])); - ctxt->wbk_en = - (uint8_t)(FIELD_GET(QDMA_SW_CTXT_W1_WBK_EN_MASK, sw_ctxt[1])); - ctxt->irq_en = - (uint8_t)(FIELD_GET(QDMA_SW_CTXT_W1_IRQ_EN_MASK, sw_ctxt[1])); - ctxt->port_id = - (uint8_t)(FIELD_GET(QDMA_SW_CTXT_W1_PORT_ID_MASK, sw_ctxt[1])); - ctxt->irq_no_last = - (uint8_t)(FIELD_GET(QDMA_SW_CTXT_W1_IRQ_NO_LAST_MASK, - sw_ctxt[1])); - ctxt->err = - (uint8_t)(FIELD_GET(QDMA_SW_CTXT_W1_ERR_MASK, sw_ctxt[1])); - ctxt->err_wb_sent = - (uint8_t)(FIELD_GET(QDMA_SW_CTXT_W1_ERR_WB_SENT_MASK, - sw_ctxt[1])); - ctxt->irq_req = - (uint8_t)(FIELD_GET(QDMA_SW_CTXT_W1_IRQ_REQ_MASK, sw_ctxt[1])); - ctxt->mrkr_dis = - (uint8_t)(FIELD_GET(QDMA_SW_CTXT_W1_MRKR_DIS_MASK, sw_ctxt[1])); - ctxt->is_mm = - (uint8_t)(FIELD_GET(QDMA_SW_CTXT_W1_IS_MM_MASK, sw_ctxt[1])); - - qdma_log_debug("%s: qen=%x, frcd_en=%x, wbi_chk=%x, wbi_intvl_en=%x\n", - __func__, ctxt->qen, ctxt->frcd_en, ctxt->wbi_chk, - ctxt->wbi_intvl_en); - qdma_log_debug("%s: at=%x, fetch_max=%x, rngsz_idx=%x, desc_sz=%x\n", - __func__, ctxt->at, ctxt->fetch_max, ctxt->rngsz_idx, - ctxt->desc_sz); - qdma_log_debug("%s: bypass=%x, mm_chn=%x, wbk_en=%x, irq_en=%x\n", - __func__, ctxt->bypass, ctxt->mm_chn, ctxt->wbk_en, - ctxt->irq_en); - qdma_log_debug("%s: port_id=%x, irq_no_last=%x,", - __func__, ctxt->port_id, ctxt->irq_no_last); - qdma_log_debug(" err=%x, err_wb_sent=%x\n", - ctxt->err, ctxt->err_wb_sent); - qdma_log_debug("%s: irq_req=%x, mrkr_dis=%x, is_mm=%x\n", - __func__, ctxt->irq_req, ctxt->mrkr_dis, ctxt->is_mm); - - ctxt->ring_bs_addr = ((uint64_t)sw_ctxt[3] << 32) | (sw_ctxt[2]); - - ctxt->vec = FIELD_GET(QDMA_SW_CTXT_W4_VEC_MASK, sw_ctxt[4]); - ctxt->intr_aggr = - (uint8_t)(FIELD_GET(QDMA_SW_CTXT_W4_INTR_AGGR_MASK, - sw_ctxt[4])); - - qdma_log_debug("%s: vec=%x, intr_aggr=%x\n", - __func__, ctxt->vec, ctxt->intr_aggr); - - return QDMA_SUCCESS; -} - -/*****************************************************************************/ -/** - * qdma_sw_context_clear() - clear sw context - * - * @dev_hndl: device handle - * @c2h: is c2h queue - * @hw_qid: hardware qid of the queue - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -static int qdma_sw_context_clear(void *dev_hndl, uint8_t c2h, - uint16_t hw_qid) -{ - enum ind_ctxt_cmd_sel sel = c2h ? - QDMA_CTXT_SEL_SW_C2H : QDMA_CTXT_SEL_SW_H2C; - - if (!dev_hndl) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", __func__, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - return qdma_indirect_reg_clear(dev_hndl, sel, hw_qid); -} - -/*****************************************************************************/ -/** - * qdma_sw_context_invalidate() - invalidate sw context - * - * @dev_hndl: device handle - * @c2h: is c2h queue - * @hw_qid: hardware qid of the queue - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -static int qdma_sw_context_invalidate(void *dev_hndl, uint8_t c2h, - uint16_t hw_qid) -{ - enum ind_ctxt_cmd_sel sel = c2h ? - QDMA_CTXT_SEL_SW_C2H : QDMA_CTXT_SEL_SW_H2C; - - if (!dev_hndl) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", __func__, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - return qdma_indirect_reg_invalidate(dev_hndl, sel, hw_qid); -} - -/*****************************************************************************/ -/** - * qdma_sw_ctx_conf() - configure SW context - * - * @dev_hndl: device handle - * @c2h: is c2h queue - * @hw_qid: hardware qid of the queue - * @ctxt: pointer to the context data - * @access_type HW access type (qdma_hw_access_type enum) value - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -int qdma_sw_ctx_conf(void *dev_hndl, uint8_t c2h, uint16_t hw_qid, - struct qdma_descq_sw_ctxt *ctxt, - enum qdma_hw_access_type access_type) -{ - int rv = QDMA_SUCCESS; - - /** ctxt requires only H2C-0 or C2H-1 - * return error for any other values - */ - if (c2h > 1) { - qdma_log_error("%s: c2h(%d) invalid, err:%d\n", - __func__, - c2h, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - switch (access_type) { - case QDMA_HW_ACCESS_READ: - rv = qdma_sw_context_read(dev_hndl, c2h, hw_qid, ctxt); - break; - case QDMA_HW_ACCESS_WRITE: - rv = qdma_sw_context_write(dev_hndl, c2h, hw_qid, ctxt); - break; - case QDMA_HW_ACCESS_CLEAR: - rv = qdma_sw_context_clear(dev_hndl, c2h, hw_qid); - break; - case QDMA_HW_ACCESS_INVALIDATE: - rv = qdma_sw_context_invalidate(dev_hndl, c2h, hw_qid); - break; - default: - qdma_log_error("%s: access_type(%d) invalid, err:%d\n", - __func__, - access_type, - -QDMA_ERR_INV_PARAM); - rv = -QDMA_ERR_INV_PARAM; - break; - } - - return rv; -} - -/*****************************************************************************/ -/** - * qdma_pfetch_context_write() - create prefetch context and program it - * - * @dev_hndl: device handle - * @hw_qid: hardware qid of the queue - * @ctxt: pointer to the prefetch context data strucutre - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -static int qdma_pfetch_context_write(void *dev_hndl, uint16_t hw_qid, - const struct qdma_descq_prefetch_ctxt *ctxt) -{ - uint32_t pfetch_ctxt[QDMA_PFETCH_CONTEXT_NUM_WORDS] = {0}; - enum ind_ctxt_cmd_sel sel = QDMA_CTXT_SEL_PFTCH; - uint32_t sw_crdt_l, sw_crdt_h; - uint16_t num_words_count = 0; - - if (!dev_hndl || !ctxt) { - qdma_log_error("%s: dev_handle or pfetch ctxt NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - sw_crdt_l = - FIELD_GET(QDMA_PFTCH_CTXT_SW_CRDT_GET_L_MASK, ctxt->sw_crdt); - sw_crdt_h = - FIELD_GET(QDMA_PFTCH_CTXT_SW_CRDT_GET_H_MASK, ctxt->sw_crdt); - - qdma_log_debug("%s: sw_crdt_l=%u, sw_crdt_h=%u, hw_qid=%hu\n", - __func__, sw_crdt_l, sw_crdt_h, hw_qid); - - pfetch_ctxt[num_words_count++] = - FIELD_SET(QDMA_PFTCH_CTXT_W0_BYPASS_MASK, ctxt->bypass) | - FIELD_SET(QDMA_PFTCH_CTXT_W0_BUF_SIZE_IDX_MASK, - ctxt->bufsz_idx) | - FIELD_SET(QDMA_PFTCH_CTXT_W0_PORT_ID_MASK, ctxt->port_id) | - FIELD_SET(QDMA_PFTCH_CTXT_W0_ERR_MASK, ctxt->err) | - FIELD_SET(QDMA_PFTCH_CTXT_W0_PFETCH_EN_MASK, ctxt->pfch_en) | - FIELD_SET(QDMA_PFTCH_CTXT_W0_Q_IN_PFETCH_MASK, ctxt->pfch) | - FIELD_SET(QDMA_PFTCH_CTXT_W0_SW_CRDT_L_MASK, sw_crdt_l); - - qdma_log_debug("%s: bypass=%x, bufsz_idx=%x, port_id=%x\n", - __func__, ctxt->bypass, ctxt->bufsz_idx, ctxt->port_id); - qdma_log_debug("%s: err=%x, pfch_en=%x, pfch=%x, ctxt->valid=%x\n", - __func__, ctxt->err, ctxt->pfch_en, ctxt->pfch, - ctxt->valid); - - pfetch_ctxt[num_words_count++] = - FIELD_SET(QDMA_PFTCH_CTXT_W1_SW_CRDT_H_MASK, sw_crdt_h) | - FIELD_SET(QDMA_PFTCH_CTXT_W1_VALID_MASK, ctxt->valid); - - return qdma_indirect_reg_write(dev_hndl, sel, hw_qid, - pfetch_ctxt, num_words_count); -} - -/*****************************************************************************/ -/** - * qdma_pfetch_context_read() - read prefetch context - * - * @dev_hndl: device handle - * @hw_qid: hardware qid of the queue - * @ctxt: pointer to the output context data - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -static int qdma_pfetch_context_read(void *dev_hndl, uint16_t hw_qid, - struct qdma_descq_prefetch_ctxt *ctxt) -{ - int rv = QDMA_SUCCESS; - uint32_t pfetch_ctxt[QDMA_PFETCH_CONTEXT_NUM_WORDS] = {0}; - enum ind_ctxt_cmd_sel sel = QDMA_CTXT_SEL_PFTCH; - uint32_t sw_crdt_l, sw_crdt_h; - - if (!dev_hndl || !ctxt) { - qdma_log_error("%s: dev_handle or pfetch ctxt NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - rv = qdma_indirect_reg_read(dev_hndl, sel, hw_qid, - QDMA_PFETCH_CONTEXT_NUM_WORDS, pfetch_ctxt); - if (rv < 0) - return rv; - - ctxt->bypass = - FIELD_GET(QDMA_PFTCH_CTXT_W0_BYPASS_MASK, pfetch_ctxt[0]); - ctxt->bufsz_idx = - FIELD_GET(QDMA_PFTCH_CTXT_W0_BUF_SIZE_IDX_MASK, pfetch_ctxt[0]); - ctxt->port_id = - FIELD_GET(QDMA_PFTCH_CTXT_W0_PORT_ID_MASK, pfetch_ctxt[0]); - ctxt->err = - (uint8_t)(FIELD_GET(QDMA_PFTCH_CTXT_W0_ERR_MASK, - pfetch_ctxt[0])); - ctxt->pfch_en = - (uint8_t)(FIELD_GET(QDMA_PFTCH_CTXT_W0_PFETCH_EN_MASK, - pfetch_ctxt[0])); - ctxt->pfch = - (uint8_t)(FIELD_GET(QDMA_PFTCH_CTXT_W0_Q_IN_PFETCH_MASK, - pfetch_ctxt[0])); - sw_crdt_l = - FIELD_GET(QDMA_PFTCH_CTXT_W0_SW_CRDT_L_MASK, pfetch_ctxt[0]); - - sw_crdt_h = - FIELD_GET(QDMA_PFTCH_CTXT_W1_SW_CRDT_H_MASK, pfetch_ctxt[1]); - ctxt->valid = - (uint8_t)(FIELD_GET(QDMA_PFTCH_CTXT_W1_VALID_MASK, - pfetch_ctxt[1])); - - ctxt->sw_crdt = - FIELD_SET(QDMA_PFTCH_CTXT_SW_CRDT_GET_L_MASK, sw_crdt_l) | - FIELD_SET(QDMA_PFTCH_CTXT_SW_CRDT_GET_H_MASK, sw_crdt_h); - - qdma_log_debug("%s: sw_crdt_l=%u, sw_crdt_h=%u, hw_qid=%hu\n", - __func__, sw_crdt_l, sw_crdt_h, hw_qid); - qdma_log_debug("%s: bypass=%x, bufsz_idx=%x, port_id=%x\n", - __func__, ctxt->bypass, ctxt->bufsz_idx, ctxt->port_id); - qdma_log_debug("%s: err=%x, pfch_en=%x, pfch=%x, ctxt->valid=%x\n", - __func__, ctxt->err, ctxt->pfch_en, ctxt->pfch, - ctxt->valid); - - return QDMA_SUCCESS; -} - -/*****************************************************************************/ -/** - * qdma_pfetch_context_clear() - clear prefetch context - * - * @dev_hndl: device handle - * @hw_qid: hardware qid of the queue - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -static int qdma_pfetch_context_clear(void *dev_hndl, uint16_t hw_qid) -{ - enum ind_ctxt_cmd_sel sel = QDMA_CTXT_SEL_PFTCH; - - if (!dev_hndl) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", __func__, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - return qdma_indirect_reg_clear(dev_hndl, sel, hw_qid); -} - -/*****************************************************************************/ -/** - * qdma_pfetch_context_invalidate() - invalidate prefetch context - * - * @dev_hndl: device handle - * @hw_qid: hardware qid of the queue - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -static int qdma_pfetch_context_invalidate(void *dev_hndl, uint16_t hw_qid) -{ - enum ind_ctxt_cmd_sel sel = QDMA_CTXT_SEL_PFTCH; - - if (!dev_hndl) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", __func__, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - return qdma_indirect_reg_invalidate(dev_hndl, sel, hw_qid); -} - -/*****************************************************************************/ -/** - * qdma_pfetch_ctx_conf() - configure prefetch context - * - * @dev_hndl: device handle - * @hw_qid: hardware qid of the queue - * @ctxt: pointer to context data - * @access_type HW access type (qdma_hw_access_type enum) value - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -int qdma_pfetch_ctx_conf(void *dev_hndl, uint16_t hw_qid, - struct qdma_descq_prefetch_ctxt *ctxt, - enum qdma_hw_access_type access_type) -{ - int rv = QDMA_SUCCESS; - - switch (access_type) { - case QDMA_HW_ACCESS_READ: - rv = qdma_pfetch_context_read(dev_hndl, hw_qid, ctxt); - break; - case QDMA_HW_ACCESS_WRITE: - rv = qdma_pfetch_context_write(dev_hndl, hw_qid, ctxt); - break; - case QDMA_HW_ACCESS_CLEAR: - rv = qdma_pfetch_context_clear(dev_hndl, hw_qid); - break; - case QDMA_HW_ACCESS_INVALIDATE: - rv = qdma_pfetch_context_invalidate(dev_hndl, hw_qid); - break; - default: - qdma_log_error("%s: access_type(%d) invalid, err:%d\n", - __func__, - access_type, - -QDMA_ERR_INV_PARAM); - rv = -QDMA_ERR_INV_PARAM; - break; - } - - return rv; -} - -/*****************************************************************************/ -/** - * qdma_cmpt_context_write() - create completion context and program it - * - * @dev_hndl: device handle - * @hw_qid: hardware qid of the queue - * @ctxt: pointer to the cmpt context data strucutre - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -static int qdma_cmpt_context_write(void *dev_hndl, uint16_t hw_qid, - const struct qdma_descq_cmpt_ctxt *ctxt) -{ - uint32_t cmpt_ctxt[QDMA_CMPT_CONTEXT_NUM_WORDS] = {0}; - uint16_t num_words_count = 0; - uint32_t baddr_l, baddr_h, pidx_l, pidx_h; - enum ind_ctxt_cmd_sel sel = QDMA_CTXT_SEL_CMPT; - - /* Input args check */ - if (!dev_hndl || !ctxt) { - qdma_log_error("%s: dev_handle or cmpt ctxt NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - if (ctxt->trig_mode > QDMA_CMPT_UPDATE_TRIG_MODE_TMR_CNTR) { - qdma_log_error("%s: trig_mode(%d) > (%d) is invalid, err:%d\n", - __func__, - ctxt->trig_mode, - QDMA_CMPT_UPDATE_TRIG_MODE_TMR_CNTR, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - baddr_l = (uint32_t)FIELD_GET(QDMA_COMPL_CTXT_BADDR_GET_L_MASK, - ctxt->bs_addr); - baddr_h = (uint32_t)FIELD_GET(QDMA_COMPL_CTXT_BADDR_GET_H_MASK, - ctxt->bs_addr); - pidx_l = FIELD_GET(QDMA_COMPL_CTXT_PIDX_GET_L_MASK, ctxt->pidx); - pidx_h = FIELD_GET(QDMA_COMPL_CTXT_PIDX_GET_H_MASK, ctxt->pidx); - - cmpt_ctxt[num_words_count++] = - FIELD_SET(QDMA_COMPL_CTXT_W0_EN_STAT_DESC_MASK, - ctxt->en_stat_desc) | - FIELD_SET(QDMA_COMPL_CTXT_W0_EN_INT_MASK, ctxt->en_int) | - FIELD_SET(QDMA_COMPL_CTXT_W0_TRIG_MODE_MASK, ctxt->trig_mode) | - FIELD_SET(QDMA_COMPL_CTXT_W0_FNC_ID_MASK, ctxt->fnc_id) | - FIELD_SET(QDMA_COMPL_CTXT_W0_COUNTER_IDX_MASK, - ctxt->counter_idx) | - FIELD_SET(QDMA_COMPL_CTXT_W0_TIMER_IDX_MASK, ctxt->timer_idx) | - FIELD_SET(QDMA_COMPL_CTXT_W0_INT_ST_MASK, ctxt->in_st) | - FIELD_SET(QDMA_COMPL_CTXT_W0_COLOR_MASK, ctxt->color) | - FIELD_SET(QDMA_COMPL_CTXT_W0_RING_SZ_MASK, ctxt->ringsz_idx); - - cmpt_ctxt[num_words_count++] = - FIELD_SET(QDMA_COMPL_CTXT_W1_BADDR_64_L_MASK, baddr_l); - - cmpt_ctxt[num_words_count++] = - FIELD_SET(QDMA_COMPL_CTXT_W2_BADDR_64_H_MASK, baddr_h) | - FIELD_SET(QDMA_COMPL_CTXT_W2_DESC_SIZE_MASK, ctxt->desc_sz) | - FIELD_SET(QDMA_COMPL_CTXT_W2_PIDX_L_MASK, pidx_l); - - - cmpt_ctxt[num_words_count++] = - FIELD_SET(QDMA_COMPL_CTXT_W3_PIDX_H_MASK, pidx_h) | - FIELD_SET(QDMA_COMPL_CTXT_W3_CIDX_MASK, ctxt->cidx) | - FIELD_SET(QDMA_COMPL_CTXT_W3_VALID_MASK, ctxt->valid) | - FIELD_SET(QDMA_COMPL_CTXT_W3_ERR_MASK, ctxt->err) | - FIELD_SET(QDMA_COMPL_CTXT_W3_USR_TRG_PND_MASK, - ctxt->user_trig_pend); - - cmpt_ctxt[num_words_count++] = - FIELD_SET(QDMA_COMPL_CTXT_W4_TMR_RUN_MASK, - ctxt->timer_running) | - FIELD_SET(QDMA_COMPL_CTXT_W4_FULL_UPDT_MASK, ctxt->full_upd) | - FIELD_SET(QDMA_COMPL_CTXT_W4_OVF_CHK_DIS_MASK, - ctxt->ovf_chk_dis) | - FIELD_SET(QDMA_COMPL_CTXT_W4_AT_MASK, ctxt->at) | - FIELD_SET(QDMA_COMPL_CTXT_W4_INTR_VEC_MASK, ctxt->vec) | - FIELD_SET(QDMA_COMPL_CTXT_W4_INTR_AGGR_MASK, ctxt->int_aggr); - - return qdma_indirect_reg_write(dev_hndl, sel, hw_qid, - cmpt_ctxt, num_words_count); -} - -/*****************************************************************************/ -/** - * qdma_cmpt_context_read() - read completion context - * - * @dev_hndl: device handle - * @hw_qid: hardware qid of the queue - * @ctxt: pointer to the context data - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -static int qdma_cmpt_context_read(void *dev_hndl, uint16_t hw_qid, - struct qdma_descq_cmpt_ctxt *ctxt) -{ - int rv = QDMA_SUCCESS; - uint32_t cmpt_ctxt[QDMA_CMPT_CONTEXT_NUM_WORDS] = {0}; - enum ind_ctxt_cmd_sel sel = QDMA_CTXT_SEL_CMPT; - uint32_t baddr_l, baddr_h, pidx_l, pidx_h; - - if (!dev_hndl || !ctxt) { - qdma_log_error("%s: dev_handle or cmpt ctxt NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - rv = qdma_indirect_reg_read(dev_hndl, sel, hw_qid, - QDMA_CMPT_CONTEXT_NUM_WORDS, cmpt_ctxt); - if (rv < 0) - return rv; - - ctxt->en_stat_desc = - FIELD_GET(QDMA_COMPL_CTXT_W0_EN_STAT_DESC_MASK, cmpt_ctxt[0]); - ctxt->en_int = FIELD_GET(QDMA_COMPL_CTXT_W0_EN_INT_MASK, cmpt_ctxt[0]); - ctxt->trig_mode = - FIELD_GET(QDMA_COMPL_CTXT_W0_TRIG_MODE_MASK, cmpt_ctxt[0]); - ctxt->fnc_id = - (uint8_t)(FIELD_GET(QDMA_COMPL_CTXT_W0_FNC_ID_MASK, - cmpt_ctxt[0])); - ctxt->counter_idx = - (uint8_t)(FIELD_GET(QDMA_COMPL_CTXT_W0_COUNTER_IDX_MASK, - cmpt_ctxt[0])); - ctxt->timer_idx = - (uint8_t)(FIELD_GET(QDMA_COMPL_CTXT_W0_TIMER_IDX_MASK, - cmpt_ctxt[0])); - ctxt->in_st = - (uint8_t)(FIELD_GET(QDMA_COMPL_CTXT_W0_INT_ST_MASK, - cmpt_ctxt[0])); - ctxt->color = - (uint8_t)(FIELD_GET(QDMA_COMPL_CTXT_W0_COLOR_MASK, - cmpt_ctxt[0])); - ctxt->ringsz_idx = - (uint8_t)(FIELD_GET(QDMA_COMPL_CTXT_W0_RING_SZ_MASK, - cmpt_ctxt[0])); - - baddr_l = FIELD_GET(QDMA_COMPL_CTXT_W1_BADDR_64_L_MASK, cmpt_ctxt[1]); - - baddr_h = FIELD_GET(QDMA_COMPL_CTXT_W2_BADDR_64_H_MASK, cmpt_ctxt[2]); - ctxt->desc_sz = - (uint8_t)(FIELD_GET(QDMA_COMPL_CTXT_W2_DESC_SIZE_MASK, - cmpt_ctxt[2])); - pidx_l = FIELD_GET(QDMA_COMPL_CTXT_W2_PIDX_L_MASK, cmpt_ctxt[2]); - - pidx_h = FIELD_GET(QDMA_COMPL_CTXT_W3_PIDX_H_MASK, cmpt_ctxt[3]); - ctxt->cidx = - (uint16_t)(FIELD_GET(QDMA_COMPL_CTXT_W3_CIDX_MASK, - cmpt_ctxt[3])); - ctxt->valid = - (uint8_t)(FIELD_GET(QDMA_COMPL_CTXT_W3_VALID_MASK, - cmpt_ctxt[3])); - ctxt->err = - (uint8_t)(FIELD_GET(QDMA_COMPL_CTXT_W3_ERR_MASK, cmpt_ctxt[3])); - ctxt->user_trig_pend = (uint8_t) - (FIELD_GET(QDMA_COMPL_CTXT_W3_USR_TRG_PND_MASK, cmpt_ctxt[3])); - - ctxt->timer_running = - FIELD_GET(QDMA_COMPL_CTXT_W4_TMR_RUN_MASK, cmpt_ctxt[4]); - ctxt->full_upd = - FIELD_GET(QDMA_COMPL_CTXT_W4_FULL_UPDT_MASK, cmpt_ctxt[4]); - ctxt->ovf_chk_dis = - FIELD_GET(QDMA_COMPL_CTXT_W4_OVF_CHK_DIS_MASK, cmpt_ctxt[4]); - ctxt->at = FIELD_GET(QDMA_COMPL_CTXT_W4_AT_MASK, cmpt_ctxt[4]); - ctxt->vec = FIELD_GET(QDMA_COMPL_CTXT_W4_INTR_VEC_MASK, cmpt_ctxt[4]); - ctxt->int_aggr = (uint8_t) - (FIELD_GET(QDMA_COMPL_CTXT_W4_INTR_AGGR_MASK, cmpt_ctxt[4])); - - ctxt->bs_addr = - FIELD_SET(QDMA_COMPL_CTXT_BADDR_GET_L_MASK, (uint64_t)baddr_l) | - FIELD_SET(QDMA_COMPL_CTXT_BADDR_GET_H_MASK, (uint64_t)baddr_h); - - ctxt->pidx = - FIELD_SET(QDMA_COMPL_CTXT_PIDX_GET_L_MASK, pidx_l) | - FIELD_SET(QDMA_COMPL_CTXT_PIDX_GET_H_MASK, pidx_h); - - return QDMA_SUCCESS; -} - -/*****************************************************************************/ -/** - * qdma_cmpt_context_clear() - clear completion context - * - * @dev_hndl: device handle - * @hw_qid: hardware qid of the queue - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -static int qdma_cmpt_context_clear(void *dev_hndl, uint16_t hw_qid) -{ - enum ind_ctxt_cmd_sel sel = QDMA_CTXT_SEL_CMPT; - - if (!dev_hndl) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", __func__, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - return qdma_indirect_reg_clear(dev_hndl, sel, hw_qid); -} - -/*****************************************************************************/ -/** - * qdma_cmpt_context_invalidate() - invalidate completion context - * - * @dev_hndl: device handle - * @hw_qid: hardware qid of the queue - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -static int qdma_cmpt_context_invalidate(void *dev_hndl, uint16_t hw_qid) -{ - enum ind_ctxt_cmd_sel sel = QDMA_CTXT_SEL_CMPT; - - if (!dev_hndl) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", __func__, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - return qdma_indirect_reg_invalidate(dev_hndl, sel, hw_qid); -} - -/*****************************************************************************/ -/** - * qdma_cmpt_ctx_conf() - configure completion context - * - * @dev_hndl: device handle - * @hw_qid: hardware qid of the queue - * @ctxt: pointer to context data - * @access_type HW access type (qdma_hw_access_type enum) value - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -int qdma_cmpt_ctx_conf(void *dev_hndl, uint16_t hw_qid, - struct qdma_descq_cmpt_ctxt *ctxt, - enum qdma_hw_access_type access_type) -{ - int rv = QDMA_SUCCESS; - - switch (access_type) { - case QDMA_HW_ACCESS_READ: - rv = qdma_cmpt_context_read(dev_hndl, hw_qid, ctxt); - break; - case QDMA_HW_ACCESS_WRITE: - rv = qdma_cmpt_context_write(dev_hndl, hw_qid, ctxt); - break; - case QDMA_HW_ACCESS_CLEAR: - rv = qdma_cmpt_context_clear(dev_hndl, hw_qid); - break; - case QDMA_HW_ACCESS_INVALIDATE: - rv = qdma_cmpt_context_invalidate(dev_hndl, hw_qid); - break; - default: - qdma_log_error("%s: access_type(%d) invalid, err:%d\n", - __func__, - access_type, - -QDMA_ERR_INV_PARAM); - rv = -QDMA_ERR_INV_PARAM; - break; - } - - return rv; -} - -/*****************************************************************************/ -/** - * qdma_hw_context_read() - read hardware context - * - * @dev_hndl: device handle - * @c2h: is c2h queue - * @hw_qid: hardware qid of the queue - * @ctxt: pointer to the output context data - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -static int qdma_hw_context_read(void *dev_hndl, uint8_t c2h, - uint16_t hw_qid, struct qdma_descq_hw_ctxt *ctxt) -{ - int rv = QDMA_SUCCESS; - uint32_t hw_ctxt[QDMA_HW_CONTEXT_NUM_WORDS] = {0}; - enum ind_ctxt_cmd_sel sel = c2h ? QDMA_CTXT_SEL_HW_C2H : - QDMA_CTXT_SEL_HW_H2C; - - if (!dev_hndl || !ctxt) { - qdma_log_error("%s: dev_handle or hw_ctxt NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - rv = qdma_indirect_reg_read(dev_hndl, sel, hw_qid, - QDMA_HW_CONTEXT_NUM_WORDS, hw_ctxt); - if (rv < 0) - return rv; - - ctxt->cidx = FIELD_GET(QDMA_HW_CTXT_W0_CIDX_MASK, hw_ctxt[0]); - ctxt->crd_use = - (uint16_t)(FIELD_GET(QDMA_HW_CTXT_W0_CRD_USE_MASK, hw_ctxt[0])); - - ctxt->dsc_pend = - (uint8_t)(FIELD_GET(QDMA_HW_CTXT_W1_DSC_PND_MASK, hw_ctxt[1])); - ctxt->idl_stp_b = - (uint8_t)(FIELD_GET(QDMA_HW_CTXT_W1_IDL_STP_B_MASK, - hw_ctxt[1])); - ctxt->evt_pnd = - (uint8_t)(FIELD_GET(QDMA_HW_CTXT_W1_EVENT_PEND_MASK, - hw_ctxt[1])); - ctxt->fetch_pnd = (uint8_t) - (FIELD_GET(QDMA_HW_CTXT_W1_FETCH_PEND_MASK, hw_ctxt[1])); - - qdma_log_debug("%s: cidx=%hu, crd_use=%hu, dsc_pend=%x\n", - __func__, ctxt->cidx, ctxt->crd_use, ctxt->dsc_pend); - qdma_log_debug("%s: idl_stp_b=%x, evt_pnd=%x, fetch_pnd=%x\n", - __func__, ctxt->idl_stp_b, ctxt->evt_pnd, - ctxt->fetch_pnd); - - return QDMA_SUCCESS; -} - -/*****************************************************************************/ -/** - * qdma_hw_context_clear() - clear hardware context - * - * @dev_hndl: device handle - * @c2h: is c2h queue - * @hw_qid: hardware qid of the queue - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -static int qdma_hw_context_clear(void *dev_hndl, uint8_t c2h, - uint16_t hw_qid) -{ - enum ind_ctxt_cmd_sel sel = c2h ? QDMA_CTXT_SEL_HW_C2H : - QDMA_CTXT_SEL_HW_H2C; - - if (!dev_hndl) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", __func__, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - return qdma_indirect_reg_clear(dev_hndl, sel, hw_qid); -} - -/*****************************************************************************/ -/** - * qdma_hw_context_invalidate() - invalidate hardware context - * - * @dev_hndl: device handle - * @c2h: is c2h queue - * @hw_qid: hardware qid of the queue - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -static int qdma_hw_context_invalidate(void *dev_hndl, uint8_t c2h, - uint16_t hw_qid) -{ - enum ind_ctxt_cmd_sel sel = c2h ? QDMA_CTXT_SEL_HW_C2H : - QDMA_CTXT_SEL_HW_H2C; - - if (!dev_hndl) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", __func__, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - return qdma_indirect_reg_invalidate(dev_hndl, sel, hw_qid); -} - -/*****************************************************************************/ -/** - * qdma_hw_ctx_conf() - configure HW context - * - * @dev_hndl: device handle - * @c2h: is c2h queue - * @hw_qid: hardware qid of the queue - * @ctxt: pointer to context data - * @access_type HW access type (qdma_hw_access_type enum) value - * QDMA_HW_ACCESS_WRITE Not supported - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -int qdma_hw_ctx_conf(void *dev_hndl, uint8_t c2h, uint16_t hw_qid, - struct qdma_descq_hw_ctxt *ctxt, - enum qdma_hw_access_type access_type) -{ - int rv = QDMA_SUCCESS; - - /** ctxt requires only H2C-0 or C2H-1 - * return error for any other values - */ - if (c2h > 1) { - qdma_log_error("%s: c2h(%d) invalid, err:%d\n", - __func__, - c2h, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - switch (access_type) { - case QDMA_HW_ACCESS_READ: - rv = qdma_hw_context_read(dev_hndl, c2h, hw_qid, ctxt); - break; - case QDMA_HW_ACCESS_CLEAR: - rv = qdma_hw_context_clear(dev_hndl, c2h, hw_qid); - break; - case QDMA_HW_ACCESS_INVALIDATE: - rv = qdma_hw_context_invalidate(dev_hndl, c2h, hw_qid); - break; - case QDMA_HW_ACCESS_WRITE: - default: - qdma_log_error("%s: access_type=%d is invalid, err:%d\n", - __func__, access_type, - -QDMA_ERR_INV_PARAM); - rv = -QDMA_ERR_INV_PARAM; - break; - } - - return rv; -} - -/*****************************************************************************/ -/** - * qdma_credit_context_read() - read credit context - * - * @dev_hndl: device handle - * @c2h: is c2h queue - * @hw_qid: hardware qid of the queue - * @ctxt: pointer to the context data - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -static int qdma_credit_context_read(void *dev_hndl, uint8_t c2h, - uint16_t hw_qid, - struct qdma_descq_credit_ctxt *ctxt) -{ - int rv = QDMA_SUCCESS; - uint32_t cr_ctxt[QDMA_CR_CONTEXT_NUM_WORDS] = {0}; - enum ind_ctxt_cmd_sel sel = c2h ? QDMA_CTXT_SEL_CR_C2H : - QDMA_CTXT_SEL_CR_H2C; - - if (!dev_hndl || !ctxt) { - qdma_log_error("%s: dev_hndl=%p credit_ctxt=%p, err:%d\n", - __func__, dev_hndl, ctxt, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - rv = qdma_indirect_reg_read(dev_hndl, sel, hw_qid, - QDMA_CR_CONTEXT_NUM_WORDS, cr_ctxt); - if (rv < 0) - return rv; - - ctxt->credit = FIELD_GET(QDMA_CR_CTXT_W0_CREDT_MASK, cr_ctxt[0]); - - qdma_log_debug("%s: credit=%u\n", __func__, ctxt->credit); - - return QDMA_SUCCESS; -} - -/*****************************************************************************/ -/** - * qdma_credit_context_clear() - clear credit context - * - * @dev_hndl: device handle - * @c2h: is c2h queue - * @hw_qid: hardware qid of the queue - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -static int qdma_credit_context_clear(void *dev_hndl, uint8_t c2h, - uint16_t hw_qid) -{ - enum ind_ctxt_cmd_sel sel = c2h ? QDMA_CTXT_SEL_CR_C2H : - QDMA_CTXT_SEL_CR_H2C; - - if (!dev_hndl) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", __func__, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - return qdma_indirect_reg_clear(dev_hndl, sel, hw_qid); -} - -/*****************************************************************************/ -/** - * qdma_credit_context_invalidate() - invalidate credit context - * - * @dev_hndl: device handle - * @c2h: is c2h queue - * @hw_qid: hardware qid of the queue - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -static int qdma_credit_context_invalidate(void *dev_hndl, uint8_t c2h, - uint16_t hw_qid) -{ - enum ind_ctxt_cmd_sel sel = c2h ? QDMA_CTXT_SEL_CR_C2H : - QDMA_CTXT_SEL_CR_H2C; - - if (!dev_hndl) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", __func__, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - return qdma_indirect_reg_invalidate(dev_hndl, sel, hw_qid); -} - -/*****************************************************************************/ -/** - * qdma_credit_ctx_conf() - configure credit context - * - * @dev_hndl: device handle - * @c2h: is c2h queue - * @hw_qid: hardware qid of the queue - * @ctxt: pointer to the context data - * @access_type HW access type (qdma_hw_access_type enum) value - * QDMA_HW_ACCESS_WRITE Not supported - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -int qdma_credit_ctx_conf(void *dev_hndl, uint8_t c2h, uint16_t hw_qid, - struct qdma_descq_credit_ctxt *ctxt, - enum qdma_hw_access_type access_type) -{ - int rv = QDMA_SUCCESS; - - /** ctxt requires only H2C-0 or C2H-1 - * return error for any other values - */ - if (c2h > 1) { - qdma_log_error("%s: c2h(%d) invalid, err:%d\n", - __func__, - c2h, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - switch (access_type) { - case QDMA_HW_ACCESS_READ: - rv = qdma_credit_context_read(dev_hndl, c2h, hw_qid, ctxt); - break; - case QDMA_HW_ACCESS_CLEAR: - rv = qdma_credit_context_clear(dev_hndl, c2h, hw_qid); - break; - case QDMA_HW_ACCESS_INVALIDATE: - rv = qdma_credit_context_invalidate(dev_hndl, c2h, hw_qid); - break; - case QDMA_HW_ACCESS_WRITE: - default: - qdma_log_error("%s: Invalid access type=%d, err:%d\n", - __func__, access_type, - -QDMA_ERR_INV_PARAM); - rv = -QDMA_ERR_INV_PARAM; - break; - } - - return rv; -} - -/*****************************************************************************/ -/** - * qdma_indirect_intr_context_write() - create indirect interrupt context - * and program it - * - * @dev_hndl: device handle - * @ring_index: indirect interrupt ring index - * @ctxt: pointer to the interrupt context data strucutre - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -static int qdma_indirect_intr_context_write(void *dev_hndl, uint16_t ring_index, - const struct qdma_indirect_intr_ctxt *ctxt) -{ - uint32_t intr_ctxt[QDMA_IND_INTR_CONTEXT_NUM_WORDS] = {0}; - enum ind_ctxt_cmd_sel sel = QDMA_CTXT_SEL_INT_COAL; - uint32_t baddr_l, baddr_m, baddr_h; - uint16_t num_words_count = 0; - - if (!dev_hndl || !ctxt) { - qdma_log_error("%s: dev_hndl=%p intr_ctxt=%p, err:%d\n", - __func__, dev_hndl, ctxt, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - baddr_l = (uint32_t)FIELD_GET(QDMA_INTR_CTXT_BADDR_GET_L_MASK, - ctxt->baddr_4k); - baddr_m = (uint32_t)FIELD_GET(QDMA_INTR_CTXT_BADDR_GET_M_MASK, - ctxt->baddr_4k); - baddr_h = (uint32_t)FIELD_GET(QDMA_INTR_CTXT_BADDR_GET_H_MASK, - ctxt->baddr_4k); - - intr_ctxt[num_words_count++] = - FIELD_SET(QDMA_INTR_CTXT_W0_VALID_MASK, ctxt->valid) | - FIELD_SET(QDMA_INTR_CTXT_W0_VEC_ID_MASK, ctxt->vec) | - FIELD_SET(QDMA_INTR_CTXT_W0_INT_ST_MASK, ctxt->int_st) | - FIELD_SET(QDMA_INTR_CTXT_W0_COLOR_MASK, ctxt->color) | - FIELD_SET(QDMA_INTR_CTXT_W0_BADDR_64_MASK, baddr_l); - - intr_ctxt[num_words_count++] = - FIELD_SET(QDMA_INTR_CTXT_W1_BADDR_64_MASK, baddr_m); - - intr_ctxt[num_words_count++] = - FIELD_SET(QDMA_INTR_CTXT_W2_BADDR_64_MASK, baddr_h) | - FIELD_SET(QDMA_INTR_CTXT_W2_PAGE_SIZE_MASK, ctxt->page_size) | - FIELD_SET(QDMA_INTR_CTXT_W2_PIDX_MASK, ctxt->pidx) | - FIELD_SET(QDMA_INTR_CTXT_W2_AT_MASK, ctxt->at); - - return qdma_indirect_reg_write(dev_hndl, sel, ring_index, - intr_ctxt, num_words_count); -} - -/*****************************************************************************/ -/** - * qdma_indirect_intr_context_read() - read indirect interrupt context - * - * @dev_hndl: device handle - * @ring_index: indirect interrupt ring index - * @ctxt: pointer to the output context data - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -static int qdma_indirect_intr_context_read(void *dev_hndl, uint16_t ring_index, - struct qdma_indirect_intr_ctxt *ctxt) -{ - int rv = QDMA_SUCCESS; - uint32_t intr_ctxt[QDMA_IND_INTR_CONTEXT_NUM_WORDS] = {0}; - enum ind_ctxt_cmd_sel sel = QDMA_CTXT_SEL_INT_COAL; - uint64_t baddr_l, baddr_m, baddr_h; - - if (!dev_hndl || !ctxt) { - qdma_log_error("%s: dev_hndl=%p intr_ctxt=%p, err:%d\n", - __func__, dev_hndl, ctxt, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - rv = qdma_indirect_reg_read(dev_hndl, sel, ring_index, - QDMA_IND_INTR_CONTEXT_NUM_WORDS, intr_ctxt); - if (rv < 0) - return rv; - - ctxt->valid = FIELD_GET(QDMA_INTR_CTXT_W0_VALID_MASK, intr_ctxt[0]); - ctxt->vec = FIELD_GET(QDMA_INTR_CTXT_W0_VEC_ID_MASK, intr_ctxt[0]); - ctxt->int_st = - (uint8_t)(FIELD_GET(QDMA_INTR_CTXT_W0_INT_ST_MASK, - intr_ctxt[0])); - ctxt->color = - (uint8_t)(FIELD_GET(QDMA_INTR_CTXT_W0_COLOR_MASK, - intr_ctxt[0])); - - baddr_l = FIELD_GET(QDMA_INTR_CTXT_W0_BADDR_64_MASK, intr_ctxt[0]); - - baddr_m = FIELD_GET(QDMA_INTR_CTXT_W1_BADDR_64_MASK, intr_ctxt[1]); - - baddr_h = FIELD_GET(QDMA_INTR_CTXT_W2_BADDR_64_MASK, intr_ctxt[2]); - ctxt->page_size = - FIELD_GET(QDMA_INTR_CTXT_W2_PAGE_SIZE_MASK, intr_ctxt[2]); - ctxt->pidx = - (uint16_t)(FIELD_GET(QDMA_INTR_CTXT_W2_PIDX_MASK, - intr_ctxt[2])); - ctxt->at = - (uint8_t)(FIELD_GET(QDMA_INTR_CTXT_W2_AT_MASK, intr_ctxt[2])); - - ctxt->baddr_4k = - FIELD_SET(QDMA_INTR_CTXT_BADDR_GET_L_MASK, baddr_l) | - FIELD_SET(QDMA_INTR_CTXT_BADDR_GET_M_MASK, baddr_m) | - FIELD_SET(QDMA_INTR_CTXT_BADDR_GET_H_MASK, baddr_h); - - return QDMA_SUCCESS; -} - -/*****************************************************************************/ -/** - * qdma_indirect_intr_context_clear() - clear indirect interrupt context - * - * @dev_hndl: device handle - * @ring_index: indirect interrupt ring index - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -static int qdma_indirect_intr_context_clear(void *dev_hndl, uint16_t ring_index) -{ - enum ind_ctxt_cmd_sel sel = QDMA_CTXT_SEL_INT_COAL; - - if (!dev_hndl) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", __func__, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - return qdma_indirect_reg_clear(dev_hndl, sel, ring_index); -} - -/*****************************************************************************/ -/** - * qdma_indirect_intr_context_invalidate() - invalidate indirect interrupt - * context - * - * @dev_hndl: device handle - * @ring_index: indirect interrupt ring index - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -static int qdma_indirect_intr_context_invalidate(void *dev_hndl, - uint16_t ring_index) -{ - enum ind_ctxt_cmd_sel sel = QDMA_CTXT_SEL_INT_COAL; - - if (!dev_hndl) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", __func__, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - return qdma_indirect_reg_invalidate(dev_hndl, sel, ring_index); -} - -/*****************************************************************************/ -/** - * qdma_indirect_intr_ctx_conf() - configure indirect interrupt context - * - * @dev_hndl: device handle - * @ring_index: indirect interrupt ring index - * @ctxt: pointer to context data - * @access_type HW access type (qdma_hw_access_type enum) value - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -int qdma_indirect_intr_ctx_conf(void *dev_hndl, uint16_t ring_index, - struct qdma_indirect_intr_ctxt *ctxt, - enum qdma_hw_access_type access_type) -{ - int rv = QDMA_SUCCESS; - - switch (access_type) { - case QDMA_HW_ACCESS_READ: - rv = qdma_indirect_intr_context_read(dev_hndl, ring_index, - ctxt); - break; - case QDMA_HW_ACCESS_WRITE: - rv = qdma_indirect_intr_context_write(dev_hndl, ring_index, - ctxt); - break; - case QDMA_HW_ACCESS_CLEAR: - rv = qdma_indirect_intr_context_clear(dev_hndl, - ring_index); - break; - case QDMA_HW_ACCESS_INVALIDATE: - rv = qdma_indirect_intr_context_invalidate(dev_hndl, - ring_index); - break; - default: - qdma_log_error("%s: access_type=%d is invalid, err:%d\n", - __func__, access_type, - -QDMA_ERR_INV_PARAM); - rv = -QDMA_ERR_INV_PARAM; - break; - } - - return rv; -} - -/*****************************************************************************/ -/** - * qdma_set_default_global_csr() - function to set the global CSR register to - * default values. The value can be modified later by using the set/get csr - * functions - * - * @dev_hndl: device handle - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -int qdma_set_default_global_csr(void *dev_hndl) -{ - /* Default values */ - uint32_t cfg_val = 0, reg_val = 0; - uint32_t rng_sz[QDMA_NUM_RING_SIZES] = {2049, 65, 129, 193, 257, 385, - 513, 769, 1025, 1537, 3073, 4097, 6145, 8193, 12289, 16385}; - uint32_t tmr_cnt[QDMA_NUM_C2H_TIMERS] = {1, 2, 4, 5, 8, 10, 15, 20, 25, - 30, 50, 75, 100, 125, 150, 200}; - uint32_t cnt_th[QDMA_NUM_C2H_COUNTERS] = {2, 4, 8, 16, 24, 32, 48, 64, - 80, 96, 112, 128, 144, 160, 176, 192}; - uint32_t buf_sz[QDMA_NUM_C2H_BUFFER_SIZES] = {4096, 256, 512, 1024, - 2048, 3968, 4096, 4096, 4096, 4096, 4096, 4096, 4096, 8192, - 9018, 16384}; - struct qdma_dev_attributes dev_cap; - - if (!dev_hndl) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", __func__, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - qdma_get_device_attributes(dev_hndl, &dev_cap); - - /* Configuring CSR registers */ - /* Global ring sizes */ - qdma_write_csr_values(dev_hndl, QDMA_OFFSET_GLBL_RNG_SZ, 0, - QDMA_NUM_RING_SIZES, rng_sz); - - if (dev_cap.st_en || dev_cap.mm_cmpt_en) { - /* Counter thresholds */ - qdma_write_csr_values(dev_hndl, QDMA_OFFSET_C2H_CNT_TH, 0, - QDMA_NUM_C2H_COUNTERS, cnt_th); - - /* Timer Counters */ - qdma_write_csr_values(dev_hndl, QDMA_OFFSET_C2H_TIMER_CNT, 0, - QDMA_NUM_C2H_TIMERS, tmr_cnt); - - - /* Writeback Interval */ - reg_val = - FIELD_SET(QDMA_GLBL_DSC_CFG_MAX_DSC_FETCH_MASK, - DEFAULT_MAX_DSC_FETCH) | - FIELD_SET(QDMA_GLBL_DSC_CFG_WB_ACC_INT_MASK, - DEFAULT_WRB_INT); - qdma_reg_write(dev_hndl, QDMA_OFFSET_GLBL_DSC_CFG, reg_val); - } - - if (dev_cap.st_en) { - /* Buffer Sizes */ - qdma_write_csr_values(dev_hndl, QDMA_OFFSET_C2H_BUF_SZ, 0, - QDMA_NUM_C2H_BUFFER_SIZES, buf_sz); - - /* Prefetch Configuration */ - cfg_val = qdma_reg_read(dev_hndl, - QDMA_OFFSET_C2H_PFETCH_CACHE_DEPTH); - reg_val = - FIELD_SET(QDMA_C2H_PFCH_FL_TH_MASK, - QDMA_DEFAULT_PFCH_STOP_THRESH) | - FIELD_SET(QDMA_C2H_NUM_PFCH_MASK, - DEFAULT_PFCH_NUM_ENTRIES_PER_Q) | - FIELD_SET(QDMA_C2H_PFCH_QCNT_MASK, (cfg_val >> 1)) | - FIELD_SET(QDMA_C2H_EVT_QCNT_TH_MASK, - ((cfg_val >> 1) - 2)); - qdma_reg_write(dev_hndl, QDMA_OFFSET_C2H_PFETCH_CFG, reg_val); - - /* C2H interrupt timer tick */ - qdma_reg_write(dev_hndl, QDMA_OFFSET_C2H_INT_TIMER_TICK, - DEFAULT_C2H_INTR_TIMER_TICK); - - /* C2h Completion Coalesce Configuration */ - cfg_val = qdma_reg_read(dev_hndl, - QDMA_OFFSET_C2H_CMPT_COAL_BUF_DEPTH); - reg_val = - FIELD_SET(QDMA_C2H_TICK_CNT_MASK, - DEFAULT_CMPT_COAL_TIMER_CNT) | - FIELD_SET(QDMA_C2H_TICK_VAL_MASK, - DEFAULT_CMPT_COAL_TIMER_TICK) | - FIELD_SET(QDMA_C2H_MAX_BUF_SZ_MASK, cfg_val); - qdma_reg_write(dev_hndl, QDMA_OFFSET_C2H_WRB_COAL_CFG, reg_val); - - /* H2C throttle Configuration*/ - reg_val = - FIELD_SET(QDMA_H2C_DATA_THRESH_MASK, - QDMA_H2C_THROT_DATA_THRESH) | - FIELD_SET(QDMA_H2C_REQ_THROT_EN_DATA_MASK, - QDMA_THROT_EN_DATA) | - FIELD_SET(QDMA_H2C_REQ_THRESH_MASK, - QDMA_H2C_THROT_REQ_THRESH) | - FIELD_SET(QDMA_H2C_REQ_THROT_EN_REQ_MASK, - QDMA_THROT_EN_REQ); - qdma_reg_write(dev_hndl, QDMA_OFFSET_H2C_REQ_THROT, reg_val); - } - - return QDMA_SUCCESS; -} - -/*****************************************************************************/ -/** - * qdma_queue_pidx_update() - function to update the desc PIDX - * - * @dev_hndl: device handle - * @is_vf: Whether PF or VF - * @qid: Queue id relative to the PF/VF calling this API - * @is_c2h: Queue direction. Set 1 for C2H and 0 for H2C - * @reg_info: data needed for the PIDX register update - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -int qdma_queue_pidx_update(void *dev_hndl, uint8_t is_vf, uint16_t qid, - uint8_t is_c2h, const struct qdma_q_pidx_reg_info *reg_info) -{ - uint32_t reg_addr = 0; - uint32_t reg_val = 0; - - if (!dev_hndl || !reg_info) { - qdma_log_error("%s: dev_hndl:(%p), reg_info:(%p), err:%d\n", - __func__, dev_hndl, reg_info, -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - if (!is_vf) { - reg_addr = (is_c2h) ? QDMA_OFFSET_DMAP_SEL_C2H_DSC_PIDX : - QDMA_OFFSET_DMAP_SEL_H2C_DSC_PIDX; - } else { - reg_addr = (is_c2h) ? QDMA_OFFSET_VF_DMAP_SEL_C2H_DSC_PIDX : - QDMA_OFFSET_VF_DMAP_SEL_H2C_DSC_PIDX; - } - - reg_addr += (qid * QDMA_PIDX_STEP); - - reg_val = FIELD_SET(QDMA_DMA_SEL_DESC_PIDX_MASK, reg_info->pidx) | - FIELD_SET(QDMA_DMA_SEL_IRQ_EN_MASK, - reg_info->irq_en); - - /* Make sure writes to the H2C/C2H descriptors are synchronized - * before updating PIDX - */ - qdma_io_wmb(); - - qdma_reg_write(dev_hndl, reg_addr, reg_val); - - return QDMA_SUCCESS; -} - -/*****************************************************************************/ -/** - * qdma_queue_cmpt_cidx_update() - function to update the CMPT CIDX update - * - * @dev_hndl: device handle - * @is_vf: Whether PF or VF - * @qid: Queue id relative to the PF/VF calling this API - * @reg_info: data needed for the CIDX register update - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -int qdma_queue_cmpt_cidx_update(void *dev_hndl, uint8_t is_vf, - uint16_t qid, const struct qdma_q_cmpt_cidx_reg_info *reg_info) -{ - uint32_t reg_addr = (is_vf) ? QDMA_OFFSET_VF_DMAP_SEL_CMPT_CIDX : - QDMA_OFFSET_DMAP_SEL_CMPT_CIDX; - uint32_t reg_val = 0; - - if (!dev_hndl || !reg_info) { - qdma_log_error("%s: dev_handle (%p) reg_info (%p) , err:%d\n", - __func__, dev_hndl, reg_info, -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - reg_addr += (qid * QDMA_CMPT_CIDX_STEP); - - reg_val = - FIELD_SET(QDMA_DMAP_SEL_CMPT_WRB_CIDX_MASK, - reg_info->wrb_cidx) | - FIELD_SET(QDMA_DMAP_SEL_CMPT_CNT_THRESH_MASK, - reg_info->counter_idx) | - FIELD_SET(QDMA_DMAP_SEL_CMPT_TMR_CNT_MASK, - reg_info->timer_idx) | - FIELD_SET(QDMA_DMAP_SEL_CMPT_TRG_MODE_MASK, - reg_info->trig_mode) | - FIELD_SET(QDMA_DMAP_SEL_CMPT_STS_DESC_EN_MASK, - reg_info->wrb_en) | - FIELD_SET(QDMA_DMAP_SEL_CMPT_IRQ_EN_MASK, reg_info->irq_en); - - /* Make sure writes to the CMPT ring are synchronized - * before updating CIDX - */ - qdma_io_wmb(); - - qdma_reg_write(dev_hndl, reg_addr, reg_val); - - return QDMA_SUCCESS; -} - -/*****************************************************************************/ -/** - * qdma_queue_intr_cidx_update() - function to update the CMPT CIDX update - * - * @dev_hndl: device handle - * @is_vf: Whether PF or VF - * @qid: Queue id relative to the PF/VF calling this API - * @reg_info: data needed for the CIDX register update - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -int qdma_queue_intr_cidx_update(void *dev_hndl, uint8_t is_vf, - uint16_t qid, const struct qdma_intr_cidx_reg_info *reg_info) -{ - uint32_t reg_addr = (is_vf) ? QDMA_OFFSET_VF_DMAP_SEL_INT_CIDX : - QDMA_OFFSET_DMAP_SEL_INT_CIDX; - uint32_t reg_val = 0; - - if (!dev_hndl || !reg_info) { - qdma_log_error("%s: dev_handle (%p) reg_info (%p), err:%d\n", - __func__, dev_hndl, reg_info, -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - reg_addr += qid * QDMA_INT_CIDX_STEP; - - reg_val = - FIELD_SET(QDMA_DMA_SEL_INT_SW_CIDX_MASK, reg_info->sw_cidx) | - FIELD_SET(QDMA_DMA_SEL_INT_RING_IDX_MASK, reg_info->rng_idx); - - qdma_reg_write(dev_hndl, reg_addr, reg_val); - - return QDMA_SUCCESS; -} - -/*****************************************************************************/ -/** - * qdma_get_user_bar() - Function to get the - * AXI Master Lite(user bar) number - * - * @dev_hndl: device handle - * @is_vf: Whether PF or VF - * @func_id: function id of the PF - * @user_bar: pointer to hold the AXI Master Lite number - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -int qdma_get_user_bar(void *dev_hndl, uint8_t is_vf, - uint16_t func_id, uint8_t *user_bar) -{ - uint8_t bar_found = 0; - uint8_t bar_idx = 0; - uint32_t user_bar_id = 0; - uint32_t reg_addr = (is_vf) ? QDMA_OFFSET_VF_USER_BAR_ID : - QDMA_OFFSET_GLBL2_PF_BARLITE_EXT; - - if (!dev_hndl) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - if (!user_bar) { - qdma_log_error("%s: user_bar is NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - user_bar_id = qdma_reg_read(dev_hndl, reg_addr); - - if (!is_vf) - user_bar_id = (user_bar_id >> (6 * func_id)) & 0x3F; - else - user_bar_id = user_bar_id & 0x3F; - - for (bar_idx = 0; bar_idx < QDMA_BAR_NUM; bar_idx++) { - if (user_bar_id & (1 << bar_idx)) { - *user_bar = bar_idx; - bar_found = 1; - break; - } - } - if (bar_found == 0) { - *user_bar = 0; - qdma_log_error("%s: Bar not found, vf:%d, usrbar:%d, err:%d\n", - __func__, - is_vf, - *user_bar, - -QDMA_ERR_HWACC_BAR_NOT_FOUND); - return -QDMA_ERR_HWACC_BAR_NOT_FOUND; - } - - return QDMA_SUCCESS; -} - -/*****************************************************************************/ -/** - * qdma_get_device_attributes() - Function to get the qdma device attributes - * - * @dev_hndl: device handle - * @dev_info: pointer to hold the device info - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -int qdma_get_device_attributes(void *dev_hndl, - struct qdma_dev_attributes *dev_info) -{ - uint8_t count = 0; - uint32_t reg_val = 0; - - if (!dev_hndl) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - if (!dev_info) { - qdma_log_error("%s: dev_info is NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - /* number of PFs */ - reg_val = qdma_reg_read(dev_hndl, QDMA_OFFSET_GLBL2_PF_BARLITE_INT); - if (FIELD_GET(QDMA_GLBL2_PF0_BAR_MAP_MASK, reg_val)) - count++; - if (FIELD_GET(QDMA_GLBL2_PF1_BAR_MAP_MASK, reg_val)) - count++; - if (FIELD_GET(QDMA_GLBL2_PF2_BAR_MAP_MASK, reg_val)) - count++; - if (FIELD_GET(QDMA_GLBL2_PF3_BAR_MAP_MASK, reg_val)) - count++; - dev_info->num_pfs = count; - - /* Number of Qs */ - reg_val = qdma_reg_read(dev_hndl, QDMA_OFFSET_GLBL2_CHANNEL_QDMA_CAP); - dev_info->num_qs = FIELD_GET(QDMA_GLBL2_MULTQ_MAX_MASK, reg_val); - - /* FLR present */ - reg_val = qdma_reg_read(dev_hndl, QDMA_OFFSET_GLBL2_MISC_CAP); - dev_info->mailbox_en = FIELD_GET(QDMA_GLBL2_MAILBOX_EN_MASK, reg_val); - dev_info->flr_present = FIELD_GET(QDMA_GLBL2_FLR_PRESENT_MASK, reg_val); - dev_info->mm_cmpt_en = FIELD_GET(QDMA_GLBL2_MM_CMPT_EN_MASK, reg_val); - - /* ST/MM enabled? */ - reg_val = qdma_reg_read(dev_hndl, QDMA_OFFSET_GLBL2_CHANNEL_MDMA); - dev_info->mm_en = (FIELD_GET(QDMA_GLBL2_MM_C2H_MASK, reg_val) - && FIELD_GET(QDMA_GLBL2_MM_H2C_MASK, reg_val)) ? 1 : 0; - dev_info->st_en = (FIELD_GET(QDMA_GLBL2_ST_C2H_MASK, reg_val) - && FIELD_GET(QDMA_GLBL2_ST_H2C_MASK, reg_val)) ? 1 : 0; - - /* num of mm channels */ - /* TODO : Register not yet defined for this. Hard coding it to 1.*/ - dev_info->mm_channel_max = 1; - - dev_info->debug_mode = 0; - dev_info->desc_eng_mode = 0; - dev_info->qid2vec_ctx = 0; - dev_info->cmpt_ovf_chk_dis = 1; - dev_info->mailbox_intr = 1; - dev_info->sw_desc_64b = 1; - dev_info->cmpt_desc_64b = 1; - dev_info->dynamic_bar = 1; - dev_info->legacy_intr = 1; - dev_info->cmpt_trig_count_timer = 1; - - return QDMA_SUCCESS; -} - -/*****************************************************************************/ -/** - * qdma_hw_ram_sbe_err_process() - Function to dump SBE error debug information - * - * @dev_hndl: device handle - * @buf: Bufffer for the debug info to be dumped in - * @buflen: Length of the buffer - * - * Return: void - *****************************************************************************/ -static void qdma_hw_ram_sbe_err_process(void *dev_hndl) -{ - qdma_dump_reg_info(dev_hndl, QDMA_OFFSET_RAM_SBE_STAT, - 1, NULL, 0); -} - -/*****************************************************************************/ -/** - * qdma_hw_ram_dbe_err_process() - Function to dump DBE error debug information - * - * @dev_hndl: device handle - * @buf: Bufffer for the debug info to be dumped in - * @buflen: Length of the buffer - * - * Return: void - *****************************************************************************/ -static void qdma_hw_ram_dbe_err_process(void *dev_hndl) -{ - qdma_dump_reg_info(dev_hndl, QDMA_OFFSET_RAM_DBE_STAT, - 1, NULL, 0); -} - -/*****************************************************************************/ -/** - * qdma_hw_desc_err_process() - Function to dump Descriptor Error information - * - * @dev_hndl: device handle - * @buf: Bufffer for the debug info to be dumped in - * @buflen: Length of the buffer - * - * Return: void - *****************************************************************************/ -static void qdma_hw_desc_err_process(void *dev_hndl) -{ - int i = 0; - uint32_t desc_err_reg_list[] = { - QDMA_OFFSET_GLBL_DSC_ERR_STS, - QDMA_OFFSET_GLBL_DSC_ERR_LOG0, - QDMA_OFFSET_GLBL_DSC_ERR_LOG1, - QDMA_OFFSET_GLBL_DSC_DBG_DAT0, - QDMA_OFFSET_GLBL_DSC_DBG_DAT1, - QDMA_OFFSET_GLBL_DSC_ERR_LOG2 - }; - int desc_err_num_regs = sizeof(desc_err_reg_list)/sizeof(uint32_t); - - for (i = 0; i < desc_err_num_regs; i++) { - qdma_dump_reg_info(dev_hndl, desc_err_reg_list[i], - 1, NULL, 0); - } -} - -/*****************************************************************************/ -/** - * qdma_hw_trq_err_process() - Function to dump Target Access Error information - * - * @dev_hndl: device handle - * @buf: Bufffer for the debug info to be dumped in - * @buflen: Length of the buffer - * - * Return: void - *****************************************************************************/ -static void qdma_hw_trq_err_process(void *dev_hndl) -{ - int i = 0; - uint32_t trq_err_reg_list[] = { - QDMA_OFFSET_GLBL_TRQ_ERR_STS, - QDMA_OFFSET_GLBL_TRQ_ERR_LOG - }; - int trq_err_reg_num_regs = sizeof(trq_err_reg_list)/sizeof(uint32_t); - - for (i = 0; i < trq_err_reg_num_regs; i++) { - qdma_dump_reg_info(dev_hndl, trq_err_reg_list[i], - 1, NULL, 0); - } - - -} - -/*****************************************************************************/ -/** - * qdma_hw_st_h2c_err_process() - Function to dump MM H2C Error information - * - * @dev_hndl: device handle - * @buf: Bufffer for the debug info to be dumped in - * @buflen: Length of the buffer - * - * Return: void - *****************************************************************************/ -static void qdma_hw_st_h2c_err_process(void *dev_hndl) -{ - int i = 0; - uint32_t st_h2c_err_reg_list[] = { - QDMA_OFFSET_H2C_ERR_STAT, - QDMA_OFFSET_H2C_FIRST_ERR_QID, - QDMA_OFFSET_H2C_DBG_REG0, - QDMA_OFFSET_H2C_DBG_REG1, - QDMA_OFFSET_H2C_DBG_REG2, - QDMA_OFFSET_H2C_DBG_REG3, - QDMA_OFFSET_H2C_DBG_REG4 - }; - int st_h2c_err_num_regs = sizeof(st_h2c_err_reg_list)/sizeof(uint32_t); - - for (i = 0; i < st_h2c_err_num_regs; i++) { - qdma_dump_reg_info(dev_hndl, st_h2c_err_reg_list[i], - 1, NULL, 0); - } -} - - -/*****************************************************************************/ -/** - * qdma_hw_st_c2h_err_process() - Function to dump MM H2C Error information - * - * @dev_hndl: device handle - * @buf: Bufffer for the debug info to be dumped in - * @buflen: Length of the buffer - * - * Return: void - *****************************************************************************/ -static void qdma_hw_st_c2h_err_process(void *dev_hndl) -{ - int i = 0; - uint32_t st_c2h_err_reg_list[] = { - QDMA_OFFSET_C2H_ERR_STAT, - QDMA_OFFSET_C2H_FATAL_ERR_STAT, - QDMA_OFFSET_C2H_FIRST_ERR_QID, - QDMA_OFFSET_C2H_STAT_S_AXIS_C2H_ACCEPTED, - QDMA_OFFSET_C2H_STAT_S_AXIS_CMPT_ACCEPTED, - QDMA_OFFSET_C2H_STAT_DESC_RSP_PKT_ACCEPTED, - QDMA_OFFSET_C2H_STAT_AXIS_PKG_CMP, - QDMA_OFFSET_C2H_STAT_DEBUG_DMA_ENG_0, - QDMA_OFFSET_C2H_STAT_DEBUG_DMA_ENG_1, - QDMA_OFFSET_C2H_STAT_DEBUG_DMA_ENG_2, - QDMA_OFFSET_C2H_STAT_DEBUG_DMA_ENG_3, - QDMA_OFFSET_C2H_STAT_DESC_RSP_DROP_ACCEPTED, - QDMA_OFFSET_C2H_STAT_DESC_RSP_ERR_ACCEPTED - }; - int st_c2h_err_num_regs = sizeof(st_c2h_err_reg_list)/sizeof(uint32_t); - - for (i = 0; i < st_c2h_err_num_regs; i++) { - qdma_dump_reg_info(dev_hndl, st_c2h_err_reg_list[i], - 1, NULL, 0); - } -} - - -/*****************************************************************************/ -/** - * qdma_hw_get_error_name() - Function to get the error in string format - * - * @err_idx: error index - * - * Return: string - success and NULL on failure - *****************************************************************************/ -const char *qdma_hw_get_error_name(uint32_t err_idx) -{ - if (err_idx >= QDMA_ERRS_ALL) { - qdma_log_error("%s: err_idx=%d is invalid, returning NULL\n", - __func__, (enum qdma_error_idx)err_idx); - return NULL; - } - - return qdma_err_info[(enum qdma_error_idx)err_idx].err_name; -} - -/*****************************************************************************/ -/** - * qdma_hw_error_process() - Function to find the error that got - * triggered and call the handler qdma_hw_error_handler of that - * particular error. - * - * @dev_hndl: device handle - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -int qdma_hw_error_process(void *dev_hndl) -{ - uint32_t glbl_err_stat = 0, err_stat = 0; - uint32_t bit = 0, i = 0; - int32_t idx = 0; - struct qdma_dev_attributes dev_cap; - uint32_t hw_err_position[TOTAL_LEAF_ERROR_AGGREGATORS] = { - QDMA_DSC_ERR_POISON, - QDMA_TRQ_ERR_UNMAPPED, - QDMA_ST_C2H_ERR_MTY_MISMATCH, - QDMA_ST_FATAL_ERR_MTY_MISMATCH, - QDMA_ST_H2C_ERR_ZERO_LEN_DESC, - QDMA_SBE_ERR_MI_H2C0_DAT, - QDMA_DBE_ERR_MI_H2C0_DAT - }; - - if (!dev_hndl) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - qdma_get_device_attributes(dev_hndl, &dev_cap); - - glbl_err_stat = qdma_reg_read(dev_hndl, QDMA_OFFSET_GLBL_ERR_STAT); - if (!glbl_err_stat) - return QDMA_HW_ERR_NOT_DETECTED; - - qdma_log_info("addr = 0x%08x val = 0x%08x", - QDMA_OFFSET_GLBL_ERR_STAT, - glbl_err_stat); - for (i = 0; i < TOTAL_LEAF_ERROR_AGGREGATORS; i++) { - bit = hw_err_position[i]; - - if ((!dev_cap.st_en) && (bit == QDMA_ST_C2H_ERR_MTY_MISMATCH || - bit == QDMA_ST_FATAL_ERR_MTY_MISMATCH || - bit == QDMA_ST_H2C_ERR_ZERO_LEN_DESC)) - continue; - - err_stat = qdma_reg_read(dev_hndl, - qdma_err_info[bit].stat_reg_addr); - - if (err_stat) { - qdma_log_info("addr = 0x%08x val = 0x%08x", - qdma_err_info[bit].stat_reg_addr, - err_stat); - - qdma_err_info[bit].qdma_hw_err_process( - dev_hndl); - - for (idx = bit; idx < all_hw_errs[i]; idx++) { - /* call the platform specific handler */ - if (err_stat & qdma_err_info[idx].leaf_err_mask) - qdma_log_error("%s detected %s", - __func__, - qdma_hw_get_error_name(idx)); - } - - qdma_reg_write(dev_hndl, - qdma_err_info[bit].stat_reg_addr, - err_stat); - - } - - } - - /* Write 1 to the global status register to clear the bits */ - qdma_reg_write(dev_hndl, QDMA_OFFSET_GLBL_ERR_STAT, glbl_err_stat); - - return QDMA_SUCCESS; -} - - -/*****************************************************************************/ -/** - * qdma_hw_error_enable() - Function to enable all or a specific error - * - * @dev_hndl: device handle - * @err_idx: error index - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -int qdma_hw_error_enable(void *dev_hndl, uint32_t err_idx) -{ - uint32_t idx = 0, i = 0; - uint32_t reg_val = 0; - struct qdma_dev_attributes dev_cap; - - if (!dev_hndl) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - if (err_idx > QDMA_ERRS_ALL) { - qdma_log_error("%s: err_idx=%d is invalid, err:%d\n", - __func__, err_idx, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - qdma_get_device_attributes(dev_hndl, &dev_cap); - - if (err_idx == QDMA_ERRS_ALL) { - for (i = 0; i < TOTAL_LEAF_ERROR_AGGREGATORS; i++) { - - idx = all_hw_errs[i]; - - /* Don't access streaming registers in - * MM only bitstreams - */ - if (!dev_cap.st_en) { - if (idx == QDMA_ST_C2H_ERR_ALL || - idx == QDMA_ST_FATAL_ERR_ALL || - idx == QDMA_ST_H2C_ERR_ALL) - continue; - } - - reg_val = qdma_err_info[idx].leaf_err_mask; - qdma_reg_write(dev_hndl, - qdma_err_info[idx].mask_reg_addr, reg_val); - - reg_val = qdma_reg_read(dev_hndl, - QDMA_OFFSET_GLBL_ERR_MASK); - reg_val |= FIELD_SET( - qdma_err_info[idx].global_err_mask, 1); - qdma_reg_write(dev_hndl, QDMA_OFFSET_GLBL_ERR_MASK, - reg_val); - } - - } else { - /* Don't access streaming registers in MM only bitstreams - * QDMA_C2H_ERR_MTY_MISMATCH to QDMA_H2C_ERR_ALL are all - * ST errors - */ - if (!dev_cap.st_en) { - if (err_idx >= QDMA_ST_C2H_ERR_MTY_MISMATCH && - err_idx <= QDMA_ST_H2C_ERR_ALL) - return QDMA_SUCCESS; - } - - reg_val = qdma_reg_read(dev_hndl, - qdma_err_info[err_idx].mask_reg_addr); - reg_val |= FIELD_SET(qdma_err_info[err_idx].leaf_err_mask, 1); - qdma_reg_write(dev_hndl, - qdma_err_info[err_idx].mask_reg_addr, reg_val); - - reg_val = qdma_reg_read(dev_hndl, QDMA_OFFSET_GLBL_ERR_MASK); - reg_val |= FIELD_SET(qdma_err_info[err_idx].global_err_mask, 1); - qdma_reg_write(dev_hndl, QDMA_OFFSET_GLBL_ERR_MASK, reg_val); - } - - return QDMA_SUCCESS; -} - - -/*****************************************************************************/ -/** - * qdma_soft_dump_config_regs() - Function to get qdma config register dump in a - * buffer - * - * @dev_hndl: device handle - * @is_vf: Whether PF or VF - * @buf : pointer to buffer to be filled - * @buflen : Length of the buffer - * - * Return: Length up-till the buffer is filled -success and < 0 - failure - *****************************************************************************/ -int qdma_soft_dump_config_regs(void *dev_hndl, uint8_t is_vf, - char *buf, uint32_t buflen) -{ - uint32_t i = 0, j = 0; - struct xreg_info *reg_info; - uint32_t num_regs = - sizeof(qdma_config_regs) / sizeof((qdma_config_regs)[0]); - uint32_t len = 0, val = 0; - int rv = QDMA_SUCCESS; - char name[DEBGFS_GEN_NAME_SZ] = ""; - struct qdma_dev_attributes dev_cap; - - if (!dev_hndl) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - if (buflen < qdma_soft_reg_dump_buf_len()) { - qdma_log_error("%s: Buffer too small, err:%d\n", - __func__, -QDMA_ERR_NO_MEM); - return -QDMA_ERR_NO_MEM; - } - - if (is_vf) { - qdma_log_error("%s: Wrong API used for VF, err:%d\n", - __func__, - -QDMA_ERR_HWACC_FEATURE_NOT_SUPPORTED); - return -QDMA_ERR_HWACC_FEATURE_NOT_SUPPORTED; - } - - qdma_get_device_attributes(dev_hndl, &dev_cap); - - reg_info = qdma_config_regs; - for (i = 0; i < num_regs; i++) { - if ((GET_CAPABILITY_MASK(dev_cap.mm_en, dev_cap.st_en, - dev_cap.mm_cmpt_en, dev_cap.mailbox_en) - & reg_info[i].mode) == 0) - continue; - - for (j = 0; j < reg_info[i].repeat; j++) { - rv = QDMA_SNPRINTF_S(name, DEBGFS_GEN_NAME_SZ, - DEBGFS_GEN_NAME_SZ, - "%s_%d", reg_info[i].name, j); - if ((rv < 0) || (rv > DEBGFS_GEN_NAME_SZ)) { - qdma_log_error( - "%d:%s QDMA_SNPRINTF_S() failed, err:%d\n", - __LINE__, __func__, - rv); - return -QDMA_ERR_NO_MEM; - } - val = qdma_reg_read(dev_hndl, - (reg_info[i].addr + (j * 4))); - rv = dump_reg(buf + len, buflen - len, - (reg_info[i].addr + (j * 4)), - name, val); - if (rv < 0) { - qdma_log_error( - "%s Buff too small, err:%d\n", - __func__, - -QDMA_ERR_NO_MEM); - return -QDMA_ERR_NO_MEM; - } - len += rv; - } - } - - return len; -} - -/* - * qdma_fill_intr_ctxt() - Helper function to fill interrupt context - * into structure - * - */ -static void qdma_fill_intr_ctxt(struct qdma_indirect_intr_ctxt *intr_ctxt) -{ - ind_intr_ctxt_entries[0].value = intr_ctxt->valid; - ind_intr_ctxt_entries[1].value = intr_ctxt->vec; - ind_intr_ctxt_entries[2].value = intr_ctxt->int_st; - ind_intr_ctxt_entries[3].value = intr_ctxt->color; - ind_intr_ctxt_entries[4].value = - intr_ctxt->baddr_4k & 0xFFFFFFFF; - ind_intr_ctxt_entries[5].value = - (intr_ctxt->baddr_4k >> 32) & 0xFFFFFFFF; - ind_intr_ctxt_entries[6].value = intr_ctxt->page_size; - ind_intr_ctxt_entries[7].value = intr_ctxt->pidx; - ind_intr_ctxt_entries[8].value = intr_ctxt->at; -} - - -static uint32_t qdma_intr_context_buf_len(void) -{ - uint32_t len = 0; - - len += (((sizeof(ind_intr_ctxt_entries) / - sizeof(ind_intr_ctxt_entries[0])) + 1) * - REG_DUMP_SIZE_PER_LINE); - return len; -} - -/* - * dump_intr_context() - Helper function to dump interrupt context into string - * - * return len - length of the string copied into buffer - */ -static int dump_intr_context(struct qdma_indirect_intr_ctxt *intr_ctx, - int ring_index, - char *buf, int buf_sz) -{ - int i = 0; - int n; - int len = 0; - int rv; - char banner[DEBGFS_LINE_SZ]; - - qdma_fill_intr_ctxt(intr_ctx); - - for (i = 0; i < DEBGFS_LINE_SZ - 5; i++) { - rv = QDMA_SNPRINTF_S(banner + i, - (DEBGFS_LINE_SZ - i), - sizeof("-"), "-"); - if ((rv < 0) || (rv > (int)sizeof("-"))) { - qdma_log_error( - "%d:%s QDMA_SNPRINTF_S() failed, err:%d\n", - __LINE__, __func__, - rv); - goto INSUF_BUF_EXIT; - } - } - - /* Interrupt context dump */ - n = sizeof(ind_intr_ctxt_entries) / - sizeof((ind_intr_ctxt_entries)[0]); - for (i = 0; i < n; i++) { - if ((len >= buf_sz) || ((len + DEBGFS_LINE_SZ) >= buf_sz)) - goto INSUF_BUF_EXIT; - - if (i == 0) { - if ((len + (3 * DEBGFS_LINE_SZ)) >= buf_sz) - goto INSUF_BUF_EXIT; - - rv = QDMA_SNPRINTF_S(buf + len, (buf_sz - len), - DEBGFS_LINE_SZ, "\n%s", banner); - if ((rv < 0) || (rv > DEBGFS_LINE_SZ)) { - qdma_log_error( - "%d:%s QDMA_SNPRINTF_S() failed, err:%d\n", - __LINE__, __func__, - rv); - goto INSUF_BUF_EXIT; - } - len += rv; - - rv = QDMA_SNPRINTF_S(buf + len, (buf_sz - len), - DEBGFS_LINE_SZ, "\n%50s %d", - "Interrupt Context for ring#", ring_index); - if ((rv < 0) || (rv > DEBGFS_LINE_SZ)) { - qdma_log_error( - "%d:%s QDMA_SNPRINTF_S() failed, err:%d\n", - __LINE__, __func__, - rv); - goto INSUF_BUF_EXIT; - } - len += rv; - - rv = QDMA_SNPRINTF_S(buf + len, (buf_sz - len), - DEBGFS_LINE_SZ, "\n%s\n", banner); - if ((rv < 0) || (rv > DEBGFS_LINE_SZ)) { - qdma_log_error( - "%d:%s QDMA_SNPRINTF_S() failed, err:%d\n", - __LINE__, __func__, - rv); - goto INSUF_BUF_EXIT; - } - len += rv; - } - - rv = QDMA_SNPRINTF_S(buf + len, (buf_sz - len), DEBGFS_LINE_SZ, - "%-47s %#-10x %u\n", - ind_intr_ctxt_entries[i].name, - ind_intr_ctxt_entries[i].value, - ind_intr_ctxt_entries[i].value); - if ((rv < 0) || (rv > DEBGFS_LINE_SZ)) { - qdma_log_error( - "%d:%s QDMA_SNPRINTF_S() failed, err:%d\n", - __LINE__, __func__, - rv); - goto INSUF_BUF_EXIT; - } - len += rv; - } - - return len; - -INSUF_BUF_EXIT: - if (buf_sz > DEBGFS_LINE_SZ) { - rv = QDMA_SNPRINTF_S((buf + buf_sz - DEBGFS_LINE_SZ), - buf_sz, DEBGFS_LINE_SZ, - "\n\nInsufficient buffer size, partial context dump\n"); - if ((rv < 0) || (rv > DEBGFS_LINE_SZ)) { - qdma_log_error( - "%d:%s QDMA_SNPRINTF_S() failed, err:%d\n", - __LINE__, __func__, - rv); - } - } - - qdma_log_error("%s: Insufficient buffer size, err:%d\n", - __func__, -QDMA_ERR_NO_MEM); - - return -QDMA_ERR_NO_MEM; -} - - -/*****************************************************************************/ -/** - * qdma_dump_intr_context() - Function to get qdma interrupt context dump in a - * buffer - * - * @dev_hndl: device handle - * @hw_qid: queue id - * @buf : pointer to buffer to be filled - * @buflen : Length of the buffer - * - * Return: Length up-till the buffer is filled -success and < 0 - failure - *****************************************************************************/ -int qdma_dump_intr_context(void *dev_hndl, - struct qdma_indirect_intr_ctxt *intr_ctx, - int ring_index, - char *buf, uint32_t buflen) -{ - int rv = 0; - uint32_t req_buflen = 0; - - if (!dev_hndl) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - - return -QDMA_ERR_INV_PARAM; - } - - if (!buf) { - qdma_log_error("%s: buf is NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - - return -QDMA_ERR_INV_PARAM; - } - - if (!intr_ctx) { - qdma_log_error("%s: intr_ctx is NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - - return -QDMA_ERR_INV_PARAM; - } - - req_buflen = qdma_intr_context_buf_len(); - if (buflen < req_buflen) { - qdma_log_error("%s: Too small buffer(%d), reqd(%d), err:%d\n", - __func__, buflen, req_buflen, -QDMA_ERR_NO_MEM); - return -QDMA_ERR_NO_MEM; - } - - rv = dump_intr_context(intr_ctx, ring_index, buf, buflen); - - return rv; -} - -/*****************************************************************************/ -/** - * qdma_soft_dump_queue_context() - Function to get qdma queue context dump in a - * buffer - * - * @dev_hndl: device handle - * @st: Queue Mode (ST or MM) - * @q_type: Queue Type - * @ctxt_data: Context Data - * @buf : pointer to buffer to be filled - * @buflen : Length of the buffer - * - * Return: Length up-till the buffer is filled -success and < 0 - failure - *****************************************************************************/ -int qdma_soft_dump_queue_context(void *dev_hndl, - uint8_t st, - enum qdma_dev_q_type q_type, - struct qdma_descq_context *ctxt_data, - char *buf, uint32_t buflen) -{ - int rv = 0; - uint32_t req_buflen = 0; - - if (!dev_hndl) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - - return -QDMA_ERR_INV_PARAM; - } - - if (!ctxt_data) { - qdma_log_error("%s: ctxt_data is NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - - return -QDMA_ERR_INV_PARAM; - } - - if (!buf) { - qdma_log_error("%s: buf is NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - - return -QDMA_ERR_INV_PARAM; - } - if (q_type >= QDMA_DEV_Q_TYPE_MAX) { - qdma_log_error("%s: invalid q_type, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - - return -QDMA_ERR_INV_PARAM; - } - - rv = qdma_soft_context_buf_len(st, q_type, &req_buflen); - if (rv != QDMA_SUCCESS) - return rv; - - if (buflen < req_buflen) { - qdma_log_error( - "%s: Too small buffer(%d), reqd(%d), err:%d\n", - __func__, buflen, req_buflen, -QDMA_ERR_NO_MEM); - return -QDMA_ERR_NO_MEM; - } - - rv = dump_soft_context(ctxt_data, st, q_type, buf, buflen); - - return rv; -} - -/*****************************************************************************/ -/** - * qdma_read_dump_queue_context() - Function to read and dump the queue - * context in the user-provided buffer. This API is valid only for PF and - * should not be used for VFs. For VF's use qdma_dump_queue_context() API - * after reading the context through mailbox. - * - * @dev_hndl: device handle - * @is_vf: VF or PF - * @hw_qid: queue id - * @st: Queue Mode(ST or MM) - * @q_type: Queue type(H2C/C2H/CMPT)* - * @buf : pointer to buffer to be filled - * @buflen : Length of the buffer - * - * Return: Length up-till the buffer is filled -success and < 0 - failure - *****************************************************************************/ -int qdma_soft_read_dump_queue_context(void *dev_hndl, - uint16_t func_id, - uint16_t qid_hw, - uint8_t st, - enum qdma_dev_q_type q_type, - char *buf, uint32_t buflen) -{ - int rv = QDMA_SUCCESS; - uint32_t req_buflen = 0; - struct qdma_descq_context context; - - if (!dev_hndl) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - - return -QDMA_ERR_INV_PARAM; - } - - if (!buf) { - qdma_log_error("%s: buf is NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - - return -QDMA_ERR_INV_PARAM; - } - - if (q_type >= QDMA_DEV_Q_TYPE_MAX) { - qdma_log_error("%s: Not supported for q_type, err = %d\n", - __func__, -QDMA_ERR_INV_PARAM); - - return -QDMA_ERR_INV_PARAM; - } - - rv = qdma_soft_context_buf_len(st, q_type, &req_buflen); - - if (rv != QDMA_SUCCESS) - return rv; - - if (buflen < req_buflen) { - qdma_log_error( - "%s: Too small buffer(%d), reqd(%d), err:%d\n", - __func__, buflen, req_buflen, -QDMA_ERR_NO_MEM); - return -QDMA_ERR_NO_MEM; - } - - qdma_memset(&context, 0, sizeof(struct qdma_descq_context)); - - if (q_type != QDMA_DEV_Q_TYPE_CMPT) { - rv = qdma_sw_ctx_conf(dev_hndl, (uint8_t)q_type, qid_hw, - &(context.sw_ctxt), - QDMA_HW_ACCESS_READ); - if (rv < 0) { - qdma_log_error("%s:sw ctxt read fail, err = %d", - __func__, rv); - return rv; - } - - rv = qdma_hw_ctx_conf(dev_hndl, (uint8_t)q_type, qid_hw, - &(context.hw_ctxt), - QDMA_HW_ACCESS_READ); - if (rv < 0) { - qdma_log_error("%s:hw ctxt read fail, err = %d", - __func__, rv); - return rv; - } - - rv = qdma_credit_ctx_conf(dev_hndl, (uint8_t)q_type, - qid_hw, - &(context.cr_ctxt), - QDMA_HW_ACCESS_READ); - if (rv < 0) { - qdma_log_error("%s:cr ctxt read fail, err = %d", - __func__, rv); - return rv; - } - - if (st && (q_type == QDMA_DEV_Q_TYPE_C2H)) { - rv = qdma_pfetch_ctx_conf(dev_hndl, - qid_hw, &(context.pfetch_ctxt), - QDMA_HW_ACCESS_READ); - if (rv < 0) { - qdma_log_error( - "%s:pftch ctxt read fail, err = %d", - __func__, rv); - return rv; - } - } - } - - if ((st && (q_type == QDMA_DEV_Q_TYPE_C2H)) || - (!st && (q_type == QDMA_DEV_Q_TYPE_CMPT))) { - rv = qdma_cmpt_ctx_conf(dev_hndl, qid_hw, - &(context.cmpt_ctxt), - QDMA_HW_ACCESS_READ); - if (rv < 0) { - qdma_log_error( - "%s:cmpt ctxt read fail, err = %d", - __func__, rv); - return rv; - } - } - - rv = qdma_fmap_conf(dev_hndl, func_id, - &(context.fmap), - QDMA_HW_ACCESS_READ); - if (rv < 0) { - qdma_log_error( - "%s:fmap ctxt read fail, err = %d", - __func__, rv); - return rv; - } - - rv = dump_soft_context(&context, st, q_type, buf, buflen); - - return rv; -} -/*****************************************************************************/ -/** - * qdma_is_legacy_intr_pend() - function to get legacy_intr_pending status bit - * - * @dev_hndl: device handle - * - * Return: legacy interrupt pending status bit value - *****************************************************************************/ -int qdma_is_legacy_intr_pend(void *dev_hndl) -{ - uint32_t reg_val; - - if (!dev_hndl) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - reg_val = qdma_reg_read(dev_hndl, QDMA_OFFSET_GLBL_INTERRUPT_CFG); - if (FIELD_GET(QDMA_GLBL_INTR_LGCY_INTR_PEND_MASK, reg_val)) - return QDMA_SUCCESS; - - qdma_log_error("%s: no pending legacy intr, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_HWACC_NO_PEND_LEGCY_INTR; -} - -/*****************************************************************************/ -/** - * qdma_clear_pend_legacy_intr() - function to clear legacy_intr_pending bit - * - * @dev_hndl: device handle - * - * Return: void - *****************************************************************************/ -int qdma_clear_pend_legacy_intr(void *dev_hndl) -{ - uint32_t reg_val; - - if (!dev_hndl) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - reg_val = qdma_reg_read(dev_hndl, QDMA_OFFSET_GLBL_INTERRUPT_CFG); - reg_val |= FIELD_SET(QDMA_GLBL_INTR_LGCY_INTR_PEND_MASK, 1); - qdma_reg_write(dev_hndl, QDMA_OFFSET_GLBL_INTERRUPT_CFG, reg_val); - - return QDMA_SUCCESS; -} - -/*****************************************************************************/ -/** - * qdma_legacy_intr_conf() - function to disable/enable legacy interrupt - * - * @dev_hndl: device handle - * @enable: enable/disable flag. 1 - enable, 0 - disable - * - * Return: void - *****************************************************************************/ -int qdma_legacy_intr_conf(void *dev_hndl, enum status_type enable) -{ - uint32_t reg_val; - - if (!dev_hndl) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - reg_val = qdma_reg_read(dev_hndl, QDMA_OFFSET_GLBL_INTERRUPT_CFG); - reg_val |= FIELD_SET(QDMA_GLBL_INTR_CFG_EN_LGCY_INTR_MASK, enable); - qdma_reg_write(dev_hndl, QDMA_OFFSET_GLBL_INTERRUPT_CFG, reg_val); - - return QDMA_SUCCESS; -} - -/*****************************************************************************/ -/** - * qdma_init_ctxt_memory() - function to initialize the context memory - * - * @dev_hndl: device handle - * - * Return: returns the platform specific error code - *****************************************************************************/ -int qdma_init_ctxt_memory(void *dev_hndl) -{ -#ifdef ENABLE_INIT_CTXT_MEMORY - uint32_t data[QDMA_REG_IND_CTXT_REG_COUNT]; - uint16_t i = 0; - struct qdma_dev_attributes dev_info; - - if (!dev_hndl) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - qdma_memset(data, 0, sizeof(uint32_t) * QDMA_REG_IND_CTXT_REG_COUNT); - qdma_get_device_attributes(dev_hndl, &dev_info); - - for (; i < dev_info.num_qs; i++) { - int sel = QDMA_CTXT_SEL_SW_C2H; - int rv; - - for (; sel <= QDMA_CTXT_SEL_PFTCH; sel++) { - /** if the st mode(h2c/c2h) not enabled - * in the design, then skip the PFTCH - * and CMPT context setup - */ - if ((dev_info.st_en == 0) && - ((sel == QDMA_CTXT_SEL_PFTCH) || - (sel == QDMA_CTXT_SEL_CMPT))) { - qdma_log_debug("%s: ST context is skipped:", - __func__); - qdma_log_debug("sel = %d\n", sel); - continue; - } - - rv = qdma_indirect_reg_clear(dev_hndl, - (enum ind_ctxt_cmd_sel)sel, i); - if (rv < 0) - return rv; - } - } - - /* fmap */ - for (i = 0; i < dev_info.num_pfs; i++) - qdma_indirect_reg_clear(dev_hndl, - QDMA_CTXT_SEL_FMAP, i); - -#else - if (!dev_hndl) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } -#endif - return QDMA_SUCCESS; - -} - -static int get_reg_entry(uint32_t reg_addr, int *reg_entry) -{ - uint32_t i = 0; - struct xreg_info *reg_info; - uint32_t num_regs = - sizeof(qdma_config_regs)/ - sizeof((qdma_config_regs)[0]); - - reg_info = qdma_config_regs; - - for (i = 0; (i < num_regs - 1); i++) { - if (reg_info[i].addr == reg_addr) { - *reg_entry = i; - break; - } - } - - if (i >= num_regs - 1) { - qdma_log_error("%s: 0x%08x is missing register list, err:%d\n", - __func__, - reg_addr, - -QDMA_ERR_INV_PARAM); - *reg_entry = -1; - return -QDMA_ERR_INV_PARAM; - } - - return 0; -} - -/*****************************************************************************/ -/** - * qdma_soft_dump_config_reg_list() - Dump the registers - * - * @dev_hndl: device handle - * @total_regs : Max registers to read - * @reg_list : array of reg addr and reg values - * @buf : pointer to buffer to be filled - * @buflen : Length of the buffer - * - * Return: returns the platform specific error code - *****************************************************************************/ -int qdma_soft_dump_config_reg_list(void *dev_hndl, uint32_t total_regs, - struct qdma_reg_data *reg_list, char *buf, uint32_t buflen) -{ - uint32_t j = 0, len = 0; - uint32_t reg_count = 0; - int reg_data_entry; - int rv = 0; - char name[DEBGFS_GEN_NAME_SZ] = ""; - struct xreg_info *reg_info = qdma_config_regs; - - if (!dev_hndl) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - if (!buf) { - qdma_log_error("%s: buf is NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - for (reg_count = 0; - (reg_count < total_regs);) { - - rv = get_reg_entry(reg_list[reg_count].reg_addr, - ®_data_entry); - if (rv < 0) { - qdma_log_error("%s: register missing in list, err:%d\n", - __func__, - -QDMA_ERR_INV_PARAM); - return rv; - } - - for (j = 0; j < reg_info[reg_data_entry].repeat; j++) { - rv = QDMA_SNPRINTF_S(name, DEBGFS_GEN_NAME_SZ, - DEBGFS_GEN_NAME_SZ, - "%s_%d", - reg_info[reg_data_entry].name, j); - if ((rv < 0) || (rv > DEBGFS_GEN_NAME_SZ)) { - qdma_log_error( - "%d:%s snprintf failed, err:%d\n", - __LINE__, __func__, - rv); - return -QDMA_ERR_NO_MEM; - } - rv = dump_reg(buf + len, buflen - len, - (reg_info[reg_data_entry].addr + (j * 4)), - name, - reg_list[reg_count + j].reg_val); - if (rv < 0) { - qdma_log_error( - "%s Buff too small, err:%d\n", - __func__, - -QDMA_ERR_NO_MEM); - return -QDMA_ERR_NO_MEM; - } - len += rv; - } - reg_count += j; - } - - return len; -} - - -/*****************************************************************************/ -/** - * qdma_read_reg_list() - read the register values - * - * @dev_hndl: device handle - * @is_vf: Whether PF or VF - * @total_regs : Max registers to read - * @reg_list : array of reg addr and reg values - * - * Return: returns the platform specific error code - *****************************************************************************/ -int qdma_read_reg_list(void *dev_hndl, uint8_t is_vf, - uint16_t reg_rd_group, - uint16_t *total_regs, - struct qdma_reg_data *reg_list) -{ - uint16_t reg_count = 0, i = 0, j = 0; - struct xreg_info *reg_info; - uint32_t num_regs = - sizeof(qdma_config_regs)/ - sizeof((qdma_config_regs)[0]); - struct qdma_dev_attributes dev_cap; - uint32_t reg_start_addr = 0; - int reg_index = 0; - int rv = 0; - - if (!is_vf) { - qdma_log_error("%s: not supported for PF, err:%d\n", - __func__, - -QDMA_ERR_HWACC_FEATURE_NOT_SUPPORTED); - return -QDMA_ERR_HWACC_FEATURE_NOT_SUPPORTED; - } - - if (!dev_hndl) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - if (!reg_list) { - qdma_log_error("%s: reg_list is NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - qdma_get_device_attributes(dev_hndl, &dev_cap); - - switch (reg_rd_group) { - case QDMA_REG_READ_GROUP_1: - reg_start_addr = QDMA_REG_GROUP_1_START_ADDR; - break; - case QDMA_REG_READ_GROUP_2: - reg_start_addr = QDMA_REG_GROUP_2_START_ADDR; - break; - case QDMA_REG_READ_GROUP_3: - reg_start_addr = QDMA_REG_GROUP_3_START_ADDR; - break; - case QDMA_REG_READ_GROUP_4: - reg_start_addr = QDMA_REG_GROUP_4_START_ADDR; - break; - default: - qdma_log_error("%s: Invalid group received\n", - __func__); - return -QDMA_ERR_INV_PARAM; - } - - rv = get_reg_entry(reg_start_addr, ®_index); - if (rv < 0) { - qdma_log_error("%s: register missing in list, err:%d\n", - __func__, - -QDMA_ERR_INV_PARAM); - return rv; - } - reg_info = &qdma_config_regs[reg_index]; - - for (i = 0, reg_count = 0; - ((i < num_regs - 1 - reg_index) && - (reg_count < QDMA_MAX_REGISTER_DUMP)); i++) { - - if (((GET_CAPABILITY_MASK(dev_cap.mm_en, dev_cap.st_en, - dev_cap.mm_cmpt_en, dev_cap.mailbox_en) - & reg_info[i].mode) == 0) || - (reg_info[i].read_type == QDMA_REG_READ_PF_ONLY)) - continue; - - for (j = 0; j < reg_info[i].repeat && - (reg_count < QDMA_MAX_REGISTER_DUMP); - j++) { - reg_list[reg_count].reg_addr = - (reg_info[i].addr + (j * 4)); - reg_list[reg_count].reg_val = - qdma_reg_read(dev_hndl, - reg_list[reg_count].reg_addr); - reg_count++; - } - } - - *total_regs = reg_count; - return rv; -} - -/*****************************************************************************/ -/** - * qdma_write_global_ring_sizes() - function to set the global ring size array - * - * @dev_hndl: device handle - * @index: Index from where the values needs to written - * @count: number of entries to be written - * @glbl_rng_sz: pointer to the array having the values to write - * - * (index + count) shall not be more than 16 - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -static int qdma_write_global_ring_sizes(void *dev_hndl, uint8_t index, - uint8_t count, const uint32_t *glbl_rng_sz) -{ - if (!dev_hndl || !glbl_rng_sz || !count) { - qdma_log_error("%s: dev_hndl=%p glbl_rng_sz=%p, err:%d\n", - __func__, dev_hndl, glbl_rng_sz, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - if ((index + count) > QDMA_NUM_RING_SIZES) { - qdma_log_error("%s: index=%u count=%u > %d, err:%d\n", - __func__, index, count, - QDMA_NUM_RING_SIZES, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - qdma_write_csr_values(dev_hndl, QDMA_OFFSET_GLBL_RNG_SZ, index, count, - glbl_rng_sz); - - return QDMA_SUCCESS; -} - -/*****************************************************************************/ -/** - * qdma_read_global_ring_sizes() - function to get the global rng_sz array - * - * @dev_hndl: device handle - * @index: Index from where the values needs to read - * @count: number of entries to be read - * @glbl_rng_sz: pointer to array to hold the values read - * - * (index + count) shall not be more than 16 - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -static int qdma_read_global_ring_sizes(void *dev_hndl, uint8_t index, - uint8_t count, uint32_t *glbl_rng_sz) -{ - if (!dev_hndl || !glbl_rng_sz || !count) { - qdma_log_error("%s: dev_hndl=%p glbl_rng_sz=%p, err:%d\n", - __func__, dev_hndl, glbl_rng_sz, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - if ((index + count) > QDMA_NUM_RING_SIZES) { - qdma_log_error("%s: index=%u count=%u > %d, err:%d\n", - __func__, index, count, - QDMA_NUM_C2H_BUFFER_SIZES, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - qdma_read_csr_values(dev_hndl, QDMA_OFFSET_GLBL_RNG_SZ, index, count, - glbl_rng_sz); - - return QDMA_SUCCESS; -} - -/*****************************************************************************/ -/** - * qdma_write_global_timer_count() - function to set the timer values - * - * @dev_hndl: device handle - * @glbl_tmr_cnt: pointer to the array having the values to write - * @index: Index from where the values needs to written - * @count: number of entries to be written - * - * (index + count) shall not be more than 16 - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -static int qdma_write_global_timer_count(void *dev_hndl, uint8_t index, - uint8_t count, const uint32_t *glbl_tmr_cnt) -{ - struct qdma_dev_attributes dev_cap; - - - - if (!dev_hndl || !glbl_tmr_cnt || !count) { - qdma_log_error("%s: dev_hndl=%p glbl_tmr_cnt=%p, err:%d\n", - __func__, dev_hndl, glbl_tmr_cnt, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - if ((index + count) > QDMA_NUM_C2H_TIMERS) { - qdma_log_error("%s: index=%u count=%u > %d, err:%d\n", - __func__, index, count, - QDMA_NUM_C2H_TIMERS, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - qdma_get_device_attributes(dev_hndl, &dev_cap); - - if (dev_cap.st_en || dev_cap.mm_cmpt_en) - qdma_write_csr_values(dev_hndl, QDMA_OFFSET_C2H_TIMER_CNT, - index, count, glbl_tmr_cnt); - else { - qdma_log_error("%s: ST or MM cmpt not supported, err:%d\n", - __func__, - -QDMA_ERR_HWACC_FEATURE_NOT_SUPPORTED); - return -QDMA_ERR_HWACC_FEATURE_NOT_SUPPORTED; - } - - return QDMA_SUCCESS; -} - -/*****************************************************************************/ -/** - * qdma_read_global_timer_count() - function to get the timer values - * - * @dev_hndl: device handle - * @index: Index from where the values needs to read - * @count: number of entries to be read - * @glbl_tmr_cnt: pointer to array to hold the values read - * - * (index + count) shall not be more than 16 - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -static int qdma_read_global_timer_count(void *dev_hndl, uint8_t index, - uint8_t count, uint32_t *glbl_tmr_cnt) -{ - struct qdma_dev_attributes dev_cap; - - if (!dev_hndl || !glbl_tmr_cnt || !count) { - qdma_log_error("%s: dev_hndl=%p glbl_tmr_cnt=%p, err:%d\n", - __func__, dev_hndl, glbl_tmr_cnt, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - if ((index + count) > QDMA_NUM_C2H_TIMERS) { - qdma_log_error("%s: index=%u count=%u > %d, err:%d\n", - __func__, index, count, - QDMA_NUM_C2H_TIMERS, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - qdma_get_device_attributes(dev_hndl, &dev_cap); - - if (dev_cap.st_en || dev_cap.mm_cmpt_en) - qdma_read_csr_values(dev_hndl, - QDMA_OFFSET_C2H_TIMER_CNT, index, - count, glbl_tmr_cnt); - else { - qdma_log_error("%s: ST or MM cmpt not supported, err:%d\n", - __func__, - -QDMA_ERR_HWACC_FEATURE_NOT_SUPPORTED); - return -QDMA_ERR_HWACC_FEATURE_NOT_SUPPORTED; - } - - return QDMA_SUCCESS; -} - -/*****************************************************************************/ -/** - * qdma_write_global_counter_threshold() - function to set the counter - * threshold values - * - * @dev_hndl: device handle - * @index: Index from where the values needs to written - * @count: number of entries to be written - * @glbl_cnt_th: pointer to the array having the values to write - * - * (index + count) shall not be more than 16 - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -static int qdma_write_global_counter_threshold(void *dev_hndl, uint8_t index, - uint8_t count, const uint32_t *glbl_cnt_th) -{ - struct qdma_dev_attributes dev_cap; - - if (!dev_hndl || !glbl_cnt_th || !count) { - qdma_log_error("%s: dev_hndl=%p glbl_cnt_th=%p, err:%d\n", - __func__, dev_hndl, glbl_cnt_th, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - if ((index + count) > QDMA_NUM_C2H_COUNTERS) { - qdma_log_error("%s: index=%u count=%u > %d, err:%d\n", - __func__, index, count, - QDMA_NUM_C2H_BUFFER_SIZES, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - qdma_get_device_attributes(dev_hndl, &dev_cap); - - if (dev_cap.st_en || dev_cap.mm_cmpt_en) - qdma_write_csr_values(dev_hndl, QDMA_OFFSET_C2H_CNT_TH, index, - count, glbl_cnt_th); - else { - qdma_log_error("%s: ST or MM cmpt not supported, err:%d\n", - __func__, - -QDMA_ERR_HWACC_FEATURE_NOT_SUPPORTED); - return -QDMA_ERR_HWACC_FEATURE_NOT_SUPPORTED; - } - - return QDMA_SUCCESS; -} - -/*****************************************************************************/ -/** - * qdma_read_global_counter_threshold() - function to get the counter threshold - * values - * - * @dev_hndl: device handle - * @index: Index from where the values needs to read - * @count: number of entries to be read - * @glbl_cnt_th: pointer to array to hold the values read - * - * (index + count) shall not be more than 16 - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -static int qdma_read_global_counter_threshold(void *dev_hndl, uint8_t index, - uint8_t count, uint32_t *glbl_cnt_th) -{ - struct qdma_dev_attributes dev_cap; - - if (!dev_hndl || !glbl_cnt_th || !count) { - qdma_log_error("%s: dev_hndl=%p glbl_cnt_th=%p, err:%d\n", - __func__, dev_hndl, glbl_cnt_th, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - if ((index + count) > QDMA_NUM_C2H_COUNTERS) { - qdma_log_error("%s: index=%u count=%u > %d, err:%d\n", - __func__, index, count, - QDMA_NUM_C2H_COUNTERS, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - qdma_get_device_attributes(dev_hndl, &dev_cap); - - if (dev_cap.st_en || dev_cap.mm_cmpt_en) - qdma_read_csr_values(dev_hndl, QDMA_OFFSET_C2H_CNT_TH, index, - count, glbl_cnt_th); - else { - qdma_log_error("%s: ST or MM cmpt not supported, err:%d\n", - __func__, -QDMA_ERR_HWACC_FEATURE_NOT_SUPPORTED); - return -QDMA_ERR_HWACC_FEATURE_NOT_SUPPORTED; - } - - return QDMA_SUCCESS; -} - -/*****************************************************************************/ -/** - * qdma_write_global_buffer_sizes() - function to set the buffer sizes - * - * @dev_hndl: device handle - * @index: Index from where the values needs to written - * @count: number of entries to be written - * @glbl_buf_sz: pointer to the array having the values to write - * - * (index + count) shall not be more than 16 - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -static int qdma_write_global_buffer_sizes(void *dev_hndl, uint8_t index, - uint8_t count, const uint32_t *glbl_buf_sz) -{ - struct qdma_dev_attributes dev_cap; - - if (!dev_hndl || !glbl_buf_sz || !count) { - qdma_log_error("%s: dev_hndl=%p glbl_buf_sz=%p, err:%d\n", - __func__, dev_hndl, glbl_buf_sz, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - if ((index + count) > QDMA_NUM_C2H_BUFFER_SIZES) { - qdma_log_error("%s: index=%u count=%u > %d, err:%d\n", - __func__, index, count, - QDMA_NUM_C2H_BUFFER_SIZES, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - qdma_get_device_attributes(dev_hndl, &dev_cap); - - if (dev_cap.st_en) - qdma_write_csr_values(dev_hndl, QDMA_OFFSET_C2H_BUF_SZ, index, - count, glbl_buf_sz); - else { - qdma_log_error("%s: ST not supported, err:%d\n", - __func__, - -QDMA_ERR_HWACC_FEATURE_NOT_SUPPORTED); - return -QDMA_ERR_HWACC_FEATURE_NOT_SUPPORTED; - } - - return QDMA_SUCCESS; -} - -/*****************************************************************************/ -/** - * qdma_read_global_buffer_sizes() - function to get the buffer sizes - * - * @dev_hndl: device handle - * @index: Index from where the values needs to read - * @count: number of entries to be read - * @glbl_buf_sz: pointer to array to hold the values read - * - * (index + count) shall not be more than 16 - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -static int qdma_read_global_buffer_sizes(void *dev_hndl, uint8_t index, - uint8_t count, uint32_t *glbl_buf_sz) -{ - struct qdma_dev_attributes dev_cap; - - if (!dev_hndl || !glbl_buf_sz || !count) { - qdma_log_error("%s: dev_hndl=%p glbl_buf_sz=%p, err:%d\n", - __func__, dev_hndl, glbl_buf_sz, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - if ((index + count) > QDMA_NUM_C2H_BUFFER_SIZES) { - qdma_log_error("%s: index=%u count=%u > %d, err:%d\n", - __func__, index, count, - QDMA_NUM_C2H_BUFFER_SIZES, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - qdma_get_device_attributes(dev_hndl, &dev_cap); - - if (dev_cap.st_en) - qdma_read_csr_values(dev_hndl, QDMA_OFFSET_C2H_BUF_SZ, index, - count, glbl_buf_sz); - else { - qdma_log_error("%s: ST is not supported, err:%d\n", - __func__, - -QDMA_ERR_HWACC_FEATURE_NOT_SUPPORTED); - return -QDMA_ERR_HWACC_FEATURE_NOT_SUPPORTED; - } - - return QDMA_SUCCESS; -} - -/*****************************************************************************/ -/** - * qdma_global_csr_conf() - function to configure global csr - * - * @dev_hndl: device handle - * @index: Index from where the values needs to read - * @count: number of entries to be read - * @csr_val: uint32_t pointer to csr value - * @csr_type: Type of the CSR (qdma_global_csr_type enum) to configure - * @access_type HW access type (qdma_hw_access_type enum) value - * QDMA_HW_ACCESS_CLEAR - Not supported - * QDMA_HW_ACCESS_INVALIDATE - Not supported - * - * (index + count) shall not be more than 16 - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -int qdma_global_csr_conf(void *dev_hndl, uint8_t index, uint8_t count, - uint32_t *csr_val, - enum qdma_global_csr_type csr_type, - enum qdma_hw_access_type access_type) -{ - int rv = QDMA_SUCCESS; - - switch (csr_type) { - case QDMA_CSR_RING_SZ: - switch (access_type) { - case QDMA_HW_ACCESS_READ: - rv = qdma_read_global_ring_sizes( - dev_hndl, - index, - count, - csr_val); - break; - case QDMA_HW_ACCESS_WRITE: - rv = qdma_write_global_ring_sizes( - dev_hndl, - index, - count, - csr_val); - break; - default: - qdma_log_error("%s: access_type(%d) invalid, err:%d\n", - __func__, - access_type, - -QDMA_ERR_INV_PARAM); - rv = -QDMA_ERR_INV_PARAM; - break; - } - break; - case QDMA_CSR_TIMER_CNT: - switch (access_type) { - case QDMA_HW_ACCESS_READ: - rv = qdma_read_global_timer_count( - dev_hndl, - index, - count, - csr_val); - break; - case QDMA_HW_ACCESS_WRITE: - rv = qdma_write_global_timer_count( - dev_hndl, - index, - count, - csr_val); - break; - default: - qdma_log_error("%s: access_type(%d) invalid, err:%d\n", - __func__, - access_type, - -QDMA_ERR_INV_PARAM); - rv = -QDMA_ERR_INV_PARAM; - break; - } - break; - case QDMA_CSR_CNT_TH: - switch (access_type) { - case QDMA_HW_ACCESS_READ: - rv = - qdma_read_global_counter_threshold( - dev_hndl, - index, - count, - csr_val); - break; - case QDMA_HW_ACCESS_WRITE: - rv = - qdma_write_global_counter_threshold( - dev_hndl, - index, - count, - csr_val); - break; - default: - qdma_log_error("%s: access_type(%d) invalid, err:%d\n", - __func__, - access_type, - -QDMA_ERR_INV_PARAM); - rv = -QDMA_ERR_INV_PARAM; - break; - } - break; - case QDMA_CSR_BUF_SZ: - switch (access_type) { - case QDMA_HW_ACCESS_READ: - rv = - qdma_read_global_buffer_sizes(dev_hndl, - index, - count, - csr_val); - break; - case QDMA_HW_ACCESS_WRITE: - rv = - qdma_write_global_buffer_sizes(dev_hndl, - index, - count, - csr_val); - break; - default: - qdma_log_error("%s: access_type(%d) invalid, err:%d\n", - __func__, - access_type, - -QDMA_ERR_INV_PARAM); - rv = -QDMA_ERR_INV_PARAM; - break; - } - break; - default: - qdma_log_error("%s: csr_type(%d) invalid, err:%d\n", - __func__, - csr_type, - -QDMA_ERR_INV_PARAM); - rv = -QDMA_ERR_INV_PARAM; - break; - } - - return rv; -} - -/*****************************************************************************/ -/** - * qdma_global_writeback_interval_write() - function to set the writeback - * interval - * - * @dev_hndl device handle - * @wb_int: Writeback Interval - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -static int qdma_global_writeback_interval_write(void *dev_hndl, - enum qdma_wrb_interval wb_int) -{ - uint32_t reg_val; - struct qdma_dev_attributes dev_cap; - - if (!dev_hndl) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", __func__, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - if (wb_int >= QDMA_NUM_WRB_INTERVALS) { - qdma_log_error("%s: wb_int=%d is invalid, err:%d\n", - __func__, wb_int, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - qdma_get_device_attributes(dev_hndl, &dev_cap); - - if (dev_cap.st_en || dev_cap.mm_cmpt_en) { - reg_val = qdma_reg_read(dev_hndl, QDMA_OFFSET_GLBL_DSC_CFG); - reg_val |= FIELD_SET(QDMA_GLBL_DSC_CFG_WB_ACC_INT_MASK, wb_int); - - qdma_reg_write(dev_hndl, QDMA_OFFSET_GLBL_DSC_CFG, reg_val); - } else { - qdma_log_error("%s: ST or MM cmpt not supported, err:%d\n", - __func__, -QDMA_ERR_HWACC_FEATURE_NOT_SUPPORTED); - return -QDMA_ERR_HWACC_FEATURE_NOT_SUPPORTED; - } - - return QDMA_SUCCESS; -} - -/*****************************************************************************/ -/** - * qdma_global_writeback_interval_read() - function to get the writeback - * interval - * - * @dev_hndl: device handle - * @wb_int: pointer to the data to hold Writeback Interval - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -static int qdma_global_writeback_interval_read(void *dev_hndl, - enum qdma_wrb_interval *wb_int) -{ - uint32_t reg_val; - struct qdma_dev_attributes dev_cap; - - if (!dev_hndl) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", __func__, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - if (!wb_int) { - qdma_log_error("%s: wb_int is NULL, err:%d\n", __func__, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - qdma_get_device_attributes(dev_hndl, &dev_cap); - - if (dev_cap.st_en || dev_cap.mm_cmpt_en) { - reg_val = qdma_reg_read(dev_hndl, QDMA_OFFSET_GLBL_DSC_CFG); - *wb_int = (enum qdma_wrb_interval)FIELD_GET( - QDMA_GLBL_DSC_CFG_WB_ACC_INT_MASK, reg_val); - } else { - qdma_log_error("%s: ST or MM cmpt not supported, err:%d\n", - __func__, -QDMA_ERR_HWACC_FEATURE_NOT_SUPPORTED); - return -QDMA_ERR_HWACC_FEATURE_NOT_SUPPORTED; - } - - return QDMA_SUCCESS; -} - -/*****************************************************************************/ -/** - * qdma_global_writeback_interval_conf() - function to configure - * the writeback interval - * - * @dev_hndl: device handle - * @wb_int: pointer to the data to hold Writeback Interval - * @access_type HW access type (qdma_hw_access_type enum) value - * QDMA_HW_ACCESS_CLEAR - Not supported - * QDMA_HW_ACCESS_INVALIDATE - Not supported - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -int qdma_global_writeback_interval_conf(void *dev_hndl, - enum qdma_wrb_interval *wb_int, - enum qdma_hw_access_type access_type) -{ - int rv = QDMA_SUCCESS; - - switch (access_type) { - case QDMA_HW_ACCESS_READ: - rv = qdma_global_writeback_interval_read(dev_hndl, wb_int); - break; - case QDMA_HW_ACCESS_WRITE: - rv = qdma_global_writeback_interval_write(dev_hndl, *wb_int); - break; - case QDMA_HW_ACCESS_CLEAR: - case QDMA_HW_ACCESS_INVALIDATE: - default: - qdma_log_error("%s: access_type(%d) invalid, err:%d\n", - __func__, - access_type, - -QDMA_ERR_INV_PARAM); - rv = -QDMA_ERR_INV_PARAM; - break; - } - - return rv; -} - - -/*****************************************************************************/ -/** - * qdma_mm_channel_conf() - Function to enable/disable the MM channel - * - * @dev_hndl: device handle - * @channel: MM channel number - * @is_c2h: Queue direction. Set 1 for C2H and 0 for H2C - * @enable: Enable or disable MM channel - * - * Presently, we have only 1 MM channel - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -int qdma_mm_channel_conf(void *dev_hndl, uint8_t channel, uint8_t is_c2h, - uint8_t enable) -{ - uint32_t reg_addr = (is_c2h) ? QDMA_OFFSET_C2H_MM_CONTROL : - QDMA_OFFSET_H2C_MM_CONTROL; - struct qdma_dev_attributes dev_cap; - - if (!dev_hndl) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - qdma_get_device_attributes(dev_hndl, &dev_cap); - - if (dev_cap.mm_en) { - qdma_reg_write(dev_hndl, - reg_addr + (channel * QDMA_MM_CONTROL_STEP), - enable); - } - - return QDMA_SUCCESS; -} - - -int qdma_dump_reg_info(void *dev_hndl, uint32_t reg_addr, - uint32_t num_regs, char *buf, uint32_t buflen) -{ - uint32_t total_num_regs = qdma_get_config_num_regs(); - struct xreg_info *config_regs = qdma_get_config_regs(); - const char *bitfield_name; - uint32_t i = 0, num_regs_idx = 0, k = 0, j = 0, - bitfield = 0, lsb = 0, msb = 31; - int rv = 0; - uint32_t reg_val; - uint32_t data_len = 0; - - if (!dev_hndl) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - for (i = 0; i < total_num_regs; i++) { - if (reg_addr == config_regs[i].addr) { - j = i; - break; - } - } - - if (i == total_num_regs) { - qdma_log_error("%s: Register not found err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - if (buf) - QDMA_SNPRINTF_S(buf, buflen, - DEBGFS_LINE_SZ, - "Register not found 0x%x\n", reg_addr); - return -QDMA_ERR_INV_PARAM; - } - - num_regs_idx = (j + num_regs < total_num_regs) ? - (j + num_regs) : total_num_regs; - - for (; j < num_regs_idx ; j++) { - reg_val = qdma_reg_read(dev_hndl, - config_regs[j].addr); - - if (buf) { - rv = QDMA_SNPRINTF_S(buf, buflen, - DEBGFS_LINE_SZ, - "\n%-40s 0x%-7x %-#10x %-10d\n", - config_regs[j].name, - config_regs[j].addr, - reg_val, reg_val); - if ((rv < 0) || (rv > DEBGFS_LINE_SZ)) { - qdma_log_error( - "%s: Insufficient buffer, err:%d\n", - __func__, -QDMA_ERR_NO_MEM); - return -QDMA_ERR_NO_MEM; - } - buf += rv; - data_len += rv; - buflen -= rv; - } else - qdma_log_info("%-40s 0x%-7x %-#10x %-10d\n", - config_regs[j].name, - config_regs[j].addr, - reg_val, reg_val); - - - for (k = 0; - k < config_regs[j].num_bitfields; k++) { - - bitfield = - config_regs[j].bitfields[k].field_mask; - bitfield_name = - config_regs[i].bitfields[k].field_name; - lsb = 0; - msb = 31; - - while (!(BIT(lsb) & bitfield)) - lsb++; - - while (!(BIT(msb) & bitfield)) - msb--; - - if (msb != lsb) { - if (buf) { - rv = QDMA_SNPRINTF_S(buf, buflen, - DEBGFS_LINE_SZ, - "%-40s [%2u,%2u] %#-10x\n", - bitfield_name, - msb, lsb, - (reg_val & bitfield) >> - lsb); - if ((rv < 0) || (rv > DEBGFS_LINE_SZ)) { - qdma_log_error( - "%s: Insufficient buffer, err:%d\n", - __func__, - -QDMA_ERR_NO_MEM); - return -QDMA_ERR_NO_MEM; - } - buf += rv; - data_len += rv; - buflen -= rv; - } else - qdma_log_info( - "%-40s [%2u,%2u] %#-10x\n", - bitfield_name, - msb, lsb, - (reg_val & bitfield) >> lsb); - - - } else { - if (buf) { - rv = QDMA_SNPRINTF_S(buf, buflen, - DEBGFS_LINE_SZ, - "%-40s [%5u] %#-10x\n", - bitfield_name, - lsb, - (reg_val & bitfield) >> - lsb); - if ((rv < 0) || (rv > DEBGFS_LINE_SZ)) { - qdma_log_error( - "%s: Insufficient buffer, err:%d\n", - __func__, - -QDMA_ERR_NO_MEM); - return -QDMA_ERR_NO_MEM; - } - buf += rv; - data_len += rv; - buflen -= rv; - } else - qdma_log_info( - "%-40s [%5u] %#-10x\n", - bitfield_name, - lsb, - (reg_val & bitfield) >> lsb); - - } - } - } - - return data_len; - -} - diff --git a/QDMA/linux-kernel/driver/libqdma/qdma_access/qdma_soft_access/qdma_soft_access.h b/QDMA/linux-kernel/driver/libqdma/qdma_access/qdma_soft_access/qdma_soft_access.h deleted file mode 100755 index 9cb5247f2..000000000 --- a/QDMA/linux-kernel/driver/libqdma/qdma_access/qdma_soft_access/qdma_soft_access.h +++ /dev/null @@ -1,294 +0,0 @@ -/* - * Copyright (c) 2019-2022, Xilinx, Inc. All rights reserved. - * Copyright (c) 2022, Advanced Micro Devices, Inc. All rights reserved. - * - * This source code is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * The full GNU General Public License is included in this distribution in - * the file called "COPYING". - */ - -#ifndef __QDMA_SOFT_ACCESS_H_ -#define __QDMA_SOFT_ACCESS_H_ - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * DOC: QDMA common library interface definitions - * - * Header file *qdma_access.h* defines data structures and function signatures - * exported by QDMA common library. - */ - -#include "qdma_platform.h" - -/** - * enum qdma_error_idx - qdma errors - */ -enum qdma_error_idx { - /* Descriptor errors */ - QDMA_DSC_ERR_POISON, - QDMA_DSC_ERR_UR_CA, - QDMA_DSC_ERR_PARAM, - QDMA_DSC_ERR_ADDR, - QDMA_DSC_ERR_TAG, - QDMA_DSC_ERR_FLR, - QDMA_DSC_ERR_TIMEOUT, - QDMA_DSC_ERR_DAT_POISON, - QDMA_DSC_ERR_FLR_CANCEL, - QDMA_DSC_ERR_DMA, - QDMA_DSC_ERR_DSC, - QDMA_DSC_ERR_RQ_CANCEL, - QDMA_DSC_ERR_DBE, - QDMA_DSC_ERR_SBE, - QDMA_DSC_ERR_ALL, - - /* TRQ Errors */ - QDMA_TRQ_ERR_UNMAPPED, - QDMA_TRQ_ERR_QID_RANGE, - QDMA_TRQ_ERR_VF_ACCESS, - QDMA_TRQ_ERR_TCP_TIMEOUT, - QDMA_TRQ_ERR_ALL, - - /* C2H Errors */ - QDMA_ST_C2H_ERR_MTY_MISMATCH, - QDMA_ST_C2H_ERR_LEN_MISMATCH, - QDMA_ST_C2H_ERR_QID_MISMATCH, - QDMA_ST_C2H_ERR_DESC_RSP_ERR, - QDMA_ST_C2H_ERR_ENG_WPL_DATA_PAR_ERR, - QDMA_ST_C2H_ERR_MSI_INT_FAIL, - QDMA_ST_C2H_ERR_ERR_DESC_CNT, - QDMA_ST_C2H_ERR_PORTID_CTXT_MISMATCH, - QDMA_ST_C2H_ERR_PORTID_BYP_IN_MISMATCH, - QDMA_ST_C2H_ERR_CMPT_INV_Q_ERR, - QDMA_ST_C2H_ERR_CMPT_QFULL_ERR, - QDMA_ST_C2H_ERR_CMPT_CIDX_ERR, - QDMA_ST_C2H_ERR_CMPT_PRTY_ERR, - QDMA_ST_C2H_ERR_ALL, - - /* Fatal Errors */ - QDMA_ST_FATAL_ERR_MTY_MISMATCH, - QDMA_ST_FATAL_ERR_LEN_MISMATCH, - QDMA_ST_FATAL_ERR_QID_MISMATCH, - QDMA_ST_FATAL_ERR_TIMER_FIFO_RAM_RDBE, - QDMA_ST_FATAL_ERR_PFCH_II_RAM_RDBE, - QDMA_ST_FATAL_ERR_CMPT_CTXT_RAM_RDBE, - QDMA_ST_FATAL_ERR_PFCH_CTXT_RAM_RDBE, - QDMA_ST_FATAL_ERR_DESC_REQ_FIFO_RAM_RDBE, - QDMA_ST_FATAL_ERR_INT_CTXT_RAM_RDBE, - QDMA_ST_FATAL_ERR_CMPT_COAL_DATA_RAM_RDBE, - QDMA_ST_FATAL_ERR_TUSER_FIFO_RAM_RDBE, - QDMA_ST_FATAL_ERR_QID_FIFO_RAM_RDBE, - QDMA_ST_FATAL_ERR_PAYLOAD_FIFO_RAM_RDBE, - QDMA_ST_FATAL_ERR_WPL_DATA_PAR, - QDMA_ST_FATAL_ERR_ALL, - - /* H2C Errors */ - QDMA_ST_H2C_ERR_ZERO_LEN_DESC, - QDMA_ST_H2C_ERR_CSI_MOP, - QDMA_ST_H2C_ERR_NO_DMA_DSC, - QDMA_ST_H2C_ERR_SBE, - QDMA_ST_H2C_ERR_DBE, - QDMA_ST_H2C_ERR_ALL, - - /* Single bit errors */ - QDMA_SBE_ERR_MI_H2C0_DAT, - QDMA_SBE_ERR_MI_C2H0_DAT, - QDMA_SBE_ERR_H2C_RD_BRG_DAT, - QDMA_SBE_ERR_H2C_WR_BRG_DAT, - QDMA_SBE_ERR_C2H_RD_BRG_DAT, - QDMA_SBE_ERR_C2H_WR_BRG_DAT, - QDMA_SBE_ERR_FUNC_MAP, - QDMA_SBE_ERR_DSC_HW_CTXT, - QDMA_SBE_ERR_DSC_CRD_RCV, - QDMA_SBE_ERR_DSC_SW_CTXT, - QDMA_SBE_ERR_DSC_CPLI, - QDMA_SBE_ERR_DSC_CPLD, - QDMA_SBE_ERR_PASID_CTXT_RAM, - QDMA_SBE_ERR_TIMER_FIFO_RAM, - QDMA_SBE_ERR_PAYLOAD_FIFO_RAM, - QDMA_SBE_ERR_QID_FIFO_RAM, - QDMA_SBE_ERR_TUSER_FIFO_RAM, - QDMA_SBE_ERR_WRB_COAL_DATA_RAM, - QDMA_SBE_ERR_INT_QID2VEC_RAM, - QDMA_SBE_ERR_INT_CTXT_RAM, - QDMA_SBE_ERR_DESC_REQ_FIFO_RAM, - QDMA_SBE_ERR_PFCH_CTXT_RAM, - QDMA_SBE_ERR_WRB_CTXT_RAM, - QDMA_SBE_ERR_PFCH_LL_RAM, - QDMA_SBE_ERR_H2C_PEND_FIFO, - QDMA_SBE_ERR_ALL, - - /* Double bit Errors */ - QDMA_DBE_ERR_MI_H2C0_DAT, - QDMA_DBE_ERR_MI_C2H0_DAT, - QDMA_DBE_ERR_H2C_RD_BRG_DAT, - QDMA_DBE_ERR_H2C_WR_BRG_DAT, - QDMA_DBE_ERR_C2H_RD_BRG_DAT, - QDMA_DBE_ERR_C2H_WR_BRG_DAT, - QDMA_DBE_ERR_FUNC_MAP, - QDMA_DBE_ERR_DSC_HW_CTXT, - QDMA_DBE_ERR_DSC_CRD_RCV, - QDMA_DBE_ERR_DSC_SW_CTXT, - QDMA_DBE_ERR_DSC_CPLI, - QDMA_DBE_ERR_DSC_CPLD, - QDMA_DBE_ERR_PASID_CTXT_RAM, - QDMA_DBE_ERR_TIMER_FIFO_RAM, - QDMA_DBE_ERR_PAYLOAD_FIFO_RAM, - QDMA_DBE_ERR_QID_FIFO_RAM, - QDMA_DBE_ERR_TUSER_FIFO_RAM, - QDMA_DBE_ERR_WRB_COAL_DATA_RAM, - QDMA_DBE_ERR_INT_QID2VEC_RAM, - QDMA_DBE_ERR_INT_CTXT_RAM, - QDMA_DBE_ERR_DESC_REQ_FIFO_RAM, - QDMA_DBE_ERR_PFCH_CTXT_RAM, - QDMA_DBE_ERR_WRB_CTXT_RAM, - QDMA_DBE_ERR_PFCH_LL_RAM, - QDMA_DBE_ERR_H2C_PEND_FIFO, - QDMA_DBE_ERR_ALL, - - QDMA_ERRS_ALL -}; - -struct qdma_hw_err_info { - enum qdma_error_idx idx; - const char *err_name; - uint32_t mask_reg_addr; - uint32_t stat_reg_addr; - uint32_t leaf_err_mask; - uint32_t global_err_mask; - void (*qdma_hw_err_process)(void *dev_hndl); -}; - - -int qdma_set_default_global_csr(void *dev_hndl); - -int qdma_get_version(void *dev_hndl, uint8_t is_vf, - struct qdma_hw_version_info *version_info); - -int qdma_pfetch_ctx_conf(void *dev_hndl, uint16_t hw_qid, - struct qdma_descq_prefetch_ctxt *ctxt, - enum qdma_hw_access_type access_type); - -int qdma_sw_ctx_conf(void *dev_hndl, uint8_t c2h, uint16_t hw_qid, - struct qdma_descq_sw_ctxt *ctxt, - enum qdma_hw_access_type access_type); - -int qdma_fmap_conf(void *dev_hndl, uint16_t func_id, - struct qdma_fmap_cfg *config, - enum qdma_hw_access_type access_type); - -int qdma_cmpt_ctx_conf(void *dev_hndl, uint16_t hw_qid, - struct qdma_descq_cmpt_ctxt *ctxt, - enum qdma_hw_access_type access_type); - -int qdma_hw_ctx_conf(void *dev_hndl, uint8_t c2h, uint16_t hw_qid, - struct qdma_descq_hw_ctxt *ctxt, - enum qdma_hw_access_type access_type); - -int qdma_credit_ctx_conf(void *dev_hndl, uint8_t c2h, uint16_t hw_qid, - struct qdma_descq_credit_ctxt *ctxt, - enum qdma_hw_access_type access_type); - -int qdma_indirect_intr_ctx_conf(void *dev_hndl, uint16_t ring_index, - struct qdma_indirect_intr_ctxt *ctxt, - enum qdma_hw_access_type access_type); - -int qdma_queue_pidx_update(void *dev_hndl, uint8_t is_vf, uint16_t qid, - uint8_t is_c2h, const struct qdma_q_pidx_reg_info *reg_info); - -int qdma_queue_cmpt_cidx_update(void *dev_hndl, uint8_t is_vf, - uint16_t qid, const struct qdma_q_cmpt_cidx_reg_info *reg_info); - -int qdma_queue_intr_cidx_update(void *dev_hndl, uint8_t is_vf, - uint16_t qid, const struct qdma_intr_cidx_reg_info *reg_info); - -int qdma_init_ctxt_memory(void *dev_hndl); - -int qdma_legacy_intr_conf(void *dev_hndl, enum status_type enable); - -int qdma_clear_pend_legacy_intr(void *dev_hndl); - -int qdma_is_legacy_intr_pend(void *dev_hndl); - -int qdma_dump_intr_context(void *dev_hndl, - struct qdma_indirect_intr_ctxt *intr_ctx, - int ring_index, - char *buf, uint32_t buflen); - -uint32_t qdma_soft_reg_dump_buf_len(void); - -uint32_t qdma_get_config_num_regs(void); - -struct xreg_info *qdma_get_config_regs(void); - -int qdma_soft_context_buf_len(uint8_t st, - enum qdma_dev_q_type q_type, uint32_t *buflen); - -int qdma_soft_dump_config_regs(void *dev_hndl, uint8_t is_vf, - char *buf, uint32_t buflen); - -int qdma_soft_dump_queue_context(void *dev_hndl, - uint8_t st, - enum qdma_dev_q_type q_type, - struct qdma_descq_context *ctxt_data, - char *buf, uint32_t buflen); - -int qdma_soft_read_dump_queue_context(void *dev_hndl, - uint16_t func_id, - uint16_t qid_hw, - uint8_t st, - enum qdma_dev_q_type q_type, - char *buf, uint32_t buflen); - -int qdma_hw_error_process(void *dev_hndl); - -const char *qdma_hw_get_error_name(uint32_t err_idx); - -int qdma_hw_error_enable(void *dev_hndl, uint32_t err_idx); - -int qdma_get_device_attributes(void *dev_hndl, - struct qdma_dev_attributes *dev_info); - -int qdma_get_user_bar(void *dev_hndl, uint8_t is_vf, - uint16_t func_id, uint8_t *user_bar); - -int qdma_soft_dump_config_reg_list(void *dev_hndl, - uint32_t total_regs, - struct qdma_reg_data *reg_list, - char *buf, uint32_t buflen); - -int qdma_read_reg_list(void *dev_hndl, uint8_t is_vf, - uint16_t reg_rd_group, - uint16_t *total_regs, - struct qdma_reg_data *reg_list); - -int qdma_global_csr_conf(void *dev_hndl, uint8_t index, uint8_t count, - uint32_t *csr_val, - enum qdma_global_csr_type csr_type, - enum qdma_hw_access_type access_type); - -int qdma_global_writeback_interval_conf(void *dev_hndl, - enum qdma_wrb_interval *wb_int, - enum qdma_hw_access_type access_type); - -int qdma_mm_channel_conf(void *dev_hndl, uint8_t channel, uint8_t is_c2h, - uint8_t enable); - -int qdma_dump_reg_info(void *dev_hndl, uint32_t reg_addr, - uint32_t num_regs, char *buf, uint32_t buflen); - -#ifdef __cplusplus -} -#endif - -#endif /* __QDMA_SOFT_ACCESS_H_ */ diff --git a/QDMA/linux-kernel/driver/libqdma/qdma_access/qdma_soft_access/qdma_soft_reg.h b/QDMA/linux-kernel/driver/libqdma/qdma_access/qdma_soft_access/qdma_soft_reg.h deleted file mode 100755 index d3876c0c1..000000000 --- a/QDMA/linux-kernel/driver/libqdma/qdma_access/qdma_soft_access/qdma_soft_reg.h +++ /dev/null @@ -1,583 +0,0 @@ -/* - * Copyright (c) 2019-2022, Xilinx, Inc. All rights reserved. - * Copyright (c) 2022, Advanced Micro Devices, Inc. All rights reserved. - * - * This source code is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * The full GNU General Public License is included in this distribution in - * the file called "COPYING". - */ - -#ifndef __QDMA_SOFT_REG_H__ -#define __QDMA_SOFT_REG_H__ - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * User defined helper macros for masks and shifts. If the same macros are - * defined in linux kernel code , then undefined them and used the user - * defined macros - */ -#ifdef CHAR_BIT -#undef CHAR_BIT -#endif -#define CHAR_BIT 8 - -#ifdef BIT -#undef BIT -#endif -#define BIT(n) (1u << (n)) - -#ifdef BITS_PER_BYTE -#undef BITS_PER_BYTE -#endif -#define BITS_PER_BYTE CHAR_BIT - -#ifdef BITS_PER_LONG -#undef BITS_PER_LONG -#endif -#define BITS_PER_LONG (sizeof(uint32_t) * BITS_PER_BYTE) - -#ifdef BITS_PER_LONG_LONG -#undef BITS_PER_LONG_LONG -#endif -#define BITS_PER_LONG_LONG (sizeof(uint64_t) * BITS_PER_BYTE) - -#ifdef GENMASK -#undef GENMASK -#endif -#define GENMASK(h, l) \ - ((0xFFFFFFFF << (l)) & (0xFFFFFFFF >> (BITS_PER_LONG - 1 - (h)))) - -#ifdef GENMASK_ULL -#undef GENMASK_ULL -#endif -#define GENMASK_ULL(h, l) \ - ((0xFFFFFFFFFFFFFFFF << (l)) & \ - (0xFFFFFFFFFFFFFFFF >> (BITS_PER_LONG_LONG - 1 - (h)))) - - -#define DEBGFS_LINE_SZ (81) - - -#define QDMA_H2C_THROT_DATA_THRESH 0x4000 -#define QDMA_THROT_EN_DATA 1 -#define QDMA_THROT_EN_REQ 0 -#define QDMA_H2C_THROT_REQ_THRESH 0x60 - -/* - * Q Context programming (indirect) - */ - -#define QDMA_REG_IND_CTXT_REG_COUNT 8 -#define QDMA_REG_IND_CTXT_WCNT_1 1 -#define QDMA_REG_IND_CTXT_WCNT_2 2 -#define QDMA_REG_IND_CTXT_WCNT_3 3 -#define QDMA_REG_IND_CTXT_WCNT_4 4 -#define QDMA_REG_IND_CTXT_WCNT_5 5 -#define QDMA_REG_IND_CTXT_WCNT_6 6 -#define QDMA_REG_IND_CTXT_WCNT_7 7 -#define QDMA_REG_IND_CTXT_WCNT_8 8 - -/* ------------------------- QDMA_TRQ_SEL_IND (0x00800) ----------------*/ -#define QDMA_OFFSET_IND_CTXT_DATA 0x804 -#define QDMA_OFFSET_IND_CTXT_MASK 0x824 -#define QDMA_OFFSET_IND_CTXT_CMD 0x844 -#define QDMA_IND_CTXT_CMD_BUSY_MASK 0x1 - -/** QDMA_IND_REG_SEL_FMAP */ -#define QDMA_FMAP_CTXT_W1_QID_MAX_MASK GENMASK(11, 0) -#define QDMA_FMAP_CTXT_W0_QID_MASK GENMASK(10, 0) - -/** QDMA_IND_REG_SEL_SW_C2H */ -/** QDMA_IND_REG_SEL_SW_H2C */ -#define QDMA_SW_CTXT_W4_INTR_AGGR_MASK BIT(11) -#define QDMA_SW_CTXT_W4_VEC_MASK GENMASK(10, 0) -#define QDMA_SW_CTXT_W3_DSC_H_MASK GENMASK(31, 0) -#define QDMA_SW_CTXT_W2_DSC_L_MASK GENMASK(31, 0) -#define QDMA_SW_CTXT_W1_IS_MM_MASK BIT(31) -#define QDMA_SW_CTXT_W1_MRKR_DIS_MASK BIT(30) -#define QDMA_SW_CTXT_W1_IRQ_REQ_MASK BIT(29) -#define QDMA_SW_CTXT_W1_ERR_WB_SENT_MASK BIT(28) -#define QDMA_SW_CTXT_W1_ERR_MASK GENMASK(27, 26) -#define QDMA_SW_CTXT_W1_IRQ_NO_LAST_MASK BIT(25) -#define QDMA_SW_CTXT_W1_PORT_ID_MASK GENMASK(24, 22) -#define QDMA_SW_CTXT_W1_IRQ_EN_MASK BIT(21) -#define QDMA_SW_CTXT_W1_WBK_EN_MASK BIT(20) -#define QDMA_SW_CTXT_W1_MM_CHN_MASK BIT(19) -#define QDMA_SW_CTXT_W1_BYP_MASK BIT(18) -#define QDMA_SW_CTXT_W1_DSC_SZ_MASK GENMASK(17, 16) -#define QDMA_SW_CTXT_W1_RNG_SZ_MASK GENMASK(15, 12) -#define QDMA_SW_CTXT_W1_FETCH_MAX_MASK GENMASK(7, 5) -#define QDMA_SW_CTXT_W1_AT_MASK BIT(4) -#define QDMA_SW_CTXT_W1_WB_INT_EN_MASK BIT(3) -#define QDMA_SW_CTXT_W1_WBI_CHK_MASK BIT(2) -#define QDMA_SW_CTXT_W1_FCRD_EN_MASK BIT(1) -#define QDMA_SW_CTXT_W1_QEN_MASK BIT(0) -#define QDMA_SW_CTXT_W0_FUNC_ID_MASK GENMASK(24, 17) -#define QDMA_SW_CTXT_W0_IRQ_ARM_MASK BIT(16) -#define QDMA_SW_CTXT_W0_PIDX GENMASK(15, 0) - - - -#define QDMA_PFTCH_CTXT_W1_VALID_MASK BIT(13) -#define QDMA_PFTCH_CTXT_W1_SW_CRDT_H_MASK GENMASK(12, 0) -#define QDMA_PFTCH_CTXT_W0_SW_CRDT_L_MASK GENMASK(31, 29) -#define QDMA_PFTCH_CTXT_W0_Q_IN_PFETCH_MASK BIT(28) -#define QDMA_PFTCH_CTXT_W0_PFETCH_EN_MASK BIT(27) -#define QDMA_PFTCH_CTXT_W0_ERR_MASK BIT(26) -#define QDMA_PFTCH_CTXT_W0_PORT_ID_MASK GENMASK(7, 5) -#define QDMA_PFTCH_CTXT_W0_BUF_SIZE_IDX_MASK GENMASK(4, 1) -#define QDMA_PFTCH_CTXT_W0_BYPASS_MASK BIT(0) - - - - -#define QDMA_COMPL_CTXT_W4_INTR_AGGR_MASK BIT(15) -#define QDMA_COMPL_CTXT_W4_INTR_VEC_MASK GENMASK(14, 4) -#define QDMA_COMPL_CTXT_W4_AT_MASK BIT(3) -#define QDMA_COMPL_CTXT_W4_OVF_CHK_DIS_MASK BIT(2) -#define QDMA_COMPL_CTXT_W4_FULL_UPDT_MASK BIT(1) -#define QDMA_COMPL_CTXT_W4_TMR_RUN_MASK BIT(0) -#define QDMA_COMPL_CTXT_W3_USR_TRG_PND_MASK BIT(31) -#define QDMA_COMPL_CTXT_W3_ERR_MASK GENMASK(30, 29) -#define QDMA_COMPL_CTXT_W3_VALID_MASK BIT(28) -#define QDMA_COMPL_CTXT_W3_CIDX_MASK GENMASK(27, 12) -#define QDMA_COMPL_CTXT_W3_PIDX_H_MASK GENMASK(11, 0) -#define QDMA_COMPL_CTXT_W2_PIDX_L_MASK GENMASK(31, 28) -#define QDMA_COMPL_CTXT_W2_DESC_SIZE_MASK GENMASK(27, 26) -#define QDMA_COMPL_CTXT_W2_BADDR_64_H_MASK GENMASK(25, 0) -#define QDMA_COMPL_CTXT_W1_BADDR_64_L_MASK GENMASK(31, 6) -#define QDMA_COMPL_CTXT_W0_RING_SZ_MASK GENMASK(31, 28) -#define QDMA_COMPL_CTXT_W0_COLOR_MASK BIT(27) -#define QDMA_COMPL_CTXT_W0_INT_ST_MASK GENMASK(26, 25) -#define QDMA_COMPL_CTXT_W0_TIMER_IDX_MASK GENMASK(24, 21) -#define QDMA_COMPL_CTXT_W0_COUNTER_IDX_MASK GENMASK(20, 17) -#define QDMA_COMPL_CTXT_W0_FNC_ID_MASK GENMASK(12, 5) -#define QDMA_COMPL_CTXT_W0_TRIG_MODE_MASK GENMASK(4, 2) -#define QDMA_COMPL_CTXT_W0_EN_INT_MASK BIT(1) -#define QDMA_COMPL_CTXT_W0_EN_STAT_DESC_MASK BIT(0) - -/** QDMA_IND_REG_SEL_HW_C2H */ -/** QDMA_IND_REG_SEL_HW_H2C */ -#define QDMA_HW_CTXT_W1_FETCH_PEND_MASK GENMASK(14, 11) -#define QDMA_HW_CTXT_W1_EVENT_PEND_MASK BIT(10) -#define QDMA_HW_CTXT_W1_IDL_STP_B_MASK BIT(9) -#define QDMA_HW_CTXT_W1_DSC_PND_MASK BIT(8) -#define QDMA_HW_CTXT_W0_CRD_USE_MASK GENMASK(31, 16) -#define QDMA_HW_CTXT_W0_CIDX_MASK GENMASK(15, 0) - -/** QDMA_IND_REG_SEL_CR_C2H */ -/** QDMA_IND_REG_SEL_CR_H2C */ -#define QDMA_CR_CTXT_W0_CREDT_MASK GENMASK(15, 0) - -/** QDMA_IND_REG_SEL_INTR */ - - -#define QDMA_INTR_CTXT_W2_AT_MASK BIT(18) -#define QDMA_INTR_CTXT_W2_PIDX_MASK GENMASK(17, 6) -#define QDMA_INTR_CTXT_W2_PAGE_SIZE_MASK GENMASK(5, 3) -#define QDMA_INTR_CTXT_W2_BADDR_64_MASK GENMASK(2, 0) -#define QDMA_INTR_CTXT_W1_BADDR_64_MASK GENMASK(31, 0) -#define QDMA_INTR_CTXT_W0_BADDR_64_MASK GENMASK(31, 15) -#define QDMA_INTR_CTXT_W0_COLOR_MASK BIT(14) -#define QDMA_INTR_CTXT_W0_INT_ST_MASK BIT(13) -#define QDMA_INTR_CTXT_W0_VEC_ID_MASK GENMASK(11, 1) -#define QDMA_INTR_CTXT_W0_VALID_MASK BIT(0) - - - - - -/* ------------------------ QDMA_TRQ_SEL_GLBL (0x00200)-------------------*/ -#define QDMA_OFFSET_GLBL_RNG_SZ 0x204 -#define QDMA_OFFSET_GLBL_SCRATCH 0x244 -#define QDMA_OFFSET_GLBL_ERR_STAT 0x248 -#define QDMA_OFFSET_GLBL_ERR_MASK 0x24C -#define QDMA_OFFSET_GLBL_DSC_CFG 0x250 -#define QDMA_GLBL_DSC_CFG_WB_ACC_INT_MASK GENMASK(2, 0) -#define QDMA_GLBL_DSC_CFG_MAX_DSC_FETCH_MASK GENMASK(5, 3) -#define QDMA_OFFSET_GLBL_DSC_ERR_STS 0x254 -#define QDMA_OFFSET_GLBL_DSC_ERR_MSK 0x258 -#define QDMA_OFFSET_GLBL_DSC_ERR_LOG0 0x25C -#define QDMA_OFFSET_GLBL_DSC_ERR_LOG1 0x260 -#define QDMA_OFFSET_GLBL_TRQ_ERR_STS 0x264 -#define QDMA_OFFSET_GLBL_TRQ_ERR_MSK 0x268 -#define QDMA_OFFSET_GLBL_TRQ_ERR_LOG 0x26C -#define QDMA_OFFSET_GLBL_DSC_DBG_DAT0 0x270 -#define QDMA_OFFSET_GLBL_DSC_DBG_DAT1 0x274 -#define QDMA_OFFSET_GLBL_DSC_ERR_LOG2 0x27C -#define QDMA_OFFSET_GLBL_INTERRUPT_CFG 0x2C4 -#define QDMA_GLBL_INTR_CFG_EN_LGCY_INTR_MASK BIT(0) -#define QDMA_GLBL_INTR_LGCY_INTR_PEND_MASK BIT(1) - -/* ------------------------- QDMA_TRQ_SEL_C2H (0x00A00) ------------------*/ -#define QDMA_OFFSET_C2H_TIMER_CNT 0xA00 -#define QDMA_OFFSET_C2H_CNT_TH 0xA40 -#define QDMA_OFFSET_C2H_QID2VEC_MAP_QID 0xA80 -#define QDMA_OFFSET_C2H_QID2VEC_MAP 0xA84 -#define QDMA_OFFSET_C2H_STAT_S_AXIS_C2H_ACCEPTED 0xA88 -#define QDMA_OFFSET_C2H_STAT_S_AXIS_CMPT_ACCEPTED 0xA8C -#define QDMA_OFFSET_C2H_STAT_DESC_RSP_PKT_ACCEPTED 0xA90 -#define QDMA_OFFSET_C2H_STAT_AXIS_PKG_CMP 0xA94 -#define QDMA_OFFSET_C2H_STAT_DESC_RSP_ACCEPTED 0xA98 -#define QDMA_OFFSET_C2H_STAT_DESC_RSP_CMP 0xA9C -#define QDMA_OFFSET_C2H_STAT_WRQ_OUT 0xAA0 -#define QDMA_OFFSET_C2H_STAT_WPL_REN_ACCEPTED 0xAA4 -#define QDMA_OFFSET_C2H_STAT_TOTAL_WRQ_LEN 0xAA8 -#define QDMA_OFFSET_C2H_STAT_TOTAL_WPL_LEN 0xAAC -#define QDMA_OFFSET_C2H_BUF_SZ 0xAB0 -#define QDMA_OFFSET_C2H_ERR_STAT 0xAF0 -#define QDMA_OFFSET_C2H_ERR_MASK 0xAF4 -#define QDMA_OFFSET_C2H_FATAL_ERR_STAT 0xAF8 -#define QDMA_OFFSET_C2H_FATAL_ERR_MASK 0xAFC -#define QDMA_OFFSET_C2H_FATAL_ERR_ENABLE 0xB00 -#define QDMA_OFFSET_C2H_ERR_INT 0xB04 -#define QDMA_OFFSET_C2H_PFETCH_CFG 0xB08 -#define QDMA_C2H_EVT_QCNT_TH_MASK GENMASK(31, 25) -#define QDMA_C2H_PFCH_QCNT_MASK GENMASK(24, 18) -#define QDMA_C2H_NUM_PFCH_MASK GENMASK(17, 9) -#define QDMA_C2H_PFCH_FL_TH_MASK GENMASK(8, 0) -#define QDMA_OFFSET_C2H_INT_TIMER_TICK 0xB0C -#define QDMA_OFFSET_C2H_STAT_DESC_RSP_DROP_ACCEPTED 0xB10 -#define QDMA_OFFSET_C2H_STAT_DESC_RSP_ERR_ACCEPTED 0xB14 -#define QDMA_OFFSET_C2H_STAT_DESC_REQ 0xB18 -#define QDMA_OFFSET_C2H_STAT_DEBUG_DMA_ENG_0 0xB1C -#define QDMA_OFFSET_C2H_STAT_DEBUG_DMA_ENG_1 0xB20 -#define QDMA_OFFSET_C2H_STAT_DEBUG_DMA_ENG_2 0xB24 -#define QDMA_OFFSET_C2H_STAT_DEBUG_DMA_ENG_3 0xB28 -#define QDMA_OFFSET_C2H_DBG_PFCH_ERR_CTXT 0xB2C -#define QDMA_OFFSET_C2H_FIRST_ERR_QID 0xB30 -#define QDMA_OFFSET_C2H_STAT_NUM_CMPT_IN 0xB34 -#define QDMA_OFFSET_C2H_STAT_NUM_CMPT_OUT 0xB38 -#define QDMA_OFFSET_C2H_STAT_NUM_CMPT_DRP 0xB3C -#define QDMA_OFFSET_C2H_STAT_NUM_STAT_DESC_OUT 0xB40 -#define QDMA_OFFSET_C2H_STAT_NUM_DSC_CRDT_SENT 0xB44 -#define QDMA_OFFSET_C2H_STAT_NUM_FCH_DSC_RCVD 0xB48 -#define QDMA_OFFSET_C2H_STAT_NUM_BYP_DSC_RCVD 0xB4C -#define QDMA_OFFSET_C2H_WRB_COAL_CFG 0xB50 -#define QDMA_C2H_MAX_BUF_SZ_MASK GENMASK(31, 26) -#define QDMA_C2H_TICK_VAL_MASK GENMASK(25, 14) -#define QDMA_C2H_TICK_CNT_MASK GENMASK(13, 2) -#define QDMA_C2H_SET_GLB_FLUSH_MASK BIT(1) -#define QDMA_C2H_DONE_GLB_FLUSH_MASK BIT(0) -#define QDMA_OFFSET_C2H_INTR_H2C_REQ 0xB54 -#define QDMA_OFFSET_C2H_INTR_C2H_MM_REQ 0xB58 -#define QDMA_OFFSET_C2H_INTR_ERR_INT_REQ 0xB5C -#define QDMA_OFFSET_C2H_INTR_C2H_ST_REQ 0xB60 -#define QDMA_OFFSET_C2H_INTR_H2C_ERR_C2H_MM_MSIX_ACK 0xB64 -#define QDMA_OFFSET_C2H_INTR_H2C_ERR_C2H_MM_MSIX_FAIL 0xB68 -#define QDMA_OFFSET_C2H_INTR_H2C_ERR_C2H_MM_MSIX_NO_MSIX 0xB6C -#define QDMA_OFFSET_C2H_INTR_H2C_ERR_C2H_MM_CTXT_INVAL 0xB70 -#define QDMA_OFFSET_C2H_INTR_C2H_ST_MSIX_ACK 0xB74 -#define QDMA_OFFSET_C2H_INTR_C2H_ST_MSIX_FAIL 0xB78 -#define QDMA_OFFSET_C2H_INTR_C2H_ST_NO_MSIX 0xB7C -#define QDMA_OFFSET_C2H_INTR_C2H_ST_CTXT_INVAL 0xB80 -#define QDMA_OFFSET_C2H_STAT_WR_CMP 0xB84 -#define QDMA_OFFSET_C2H_STAT_DEBUG_DMA_ENG_4 0xB88 -#define QDMA_OFFSET_C2H_STAT_DEBUG_DMA_ENG_5 0xB8C -#define QDMA_OFFSET_C2H_DBG_PFCH_QID 0xB90 -#define QDMA_OFFSET_C2H_DBG_PFCH 0xB94 -#define QDMA_OFFSET_C2H_INT_DEBUG 0xB98 -#define QDMA_OFFSET_C2H_STAT_IMM_ACCEPTED 0xB9C -#define QDMA_OFFSET_C2H_STAT_MARKER_ACCEPTED 0xBA0 -#define QDMA_OFFSET_C2H_STAT_DISABLE_CMP_ACCEPTED 0xBA4 -#define QDMA_OFFSET_C2H_PAYLOAD_FIFO_CRDT_CNT 0xBA8 -#define QDMA_OFFSET_C2H_PFETCH_CACHE_DEPTH 0xBE0 -#define QDMA_OFFSET_C2H_CMPT_COAL_BUF_DEPTH 0xBE4 - -/* ------------------------- QDMA_TRQ_SEL_H2C (0x00E00) ------------------*/ -#define QDMA_OFFSET_H2C_ERR_STAT 0xE00 -#define QDMA_OFFSET_H2C_ERR_MASK 0xE04 -#define QDMA_OFFSET_H2C_FIRST_ERR_QID 0xE08 -#define QDMA_OFFSET_H2C_DBG_REG0 0xE0C -#define QDMA_OFFSET_H2C_DBG_REG1 0xE10 -#define QDMA_OFFSET_H2C_DBG_REG2 0xE14 -#define QDMA_OFFSET_H2C_DBG_REG3 0xE18 -#define QDMA_OFFSET_H2C_DBG_REG4 0xE1C -#define QDMA_OFFSET_H2C_FATAL_ERR_EN 0xE20 -#define QDMA_OFFSET_H2C_REQ_THROT 0xE24 -#define QDMA_H2C_REQ_THROT_EN_REQ_MASK BIT(31) -#define QDMA_H2C_REQ_THRESH_MASK GENMASK(25, 17) -#define QDMA_H2C_REQ_THROT_EN_DATA_MASK BIT(16) -#define QDMA_H2C_DATA_THRESH_MASK GENMASK(15, 0) - - -/* ------------------------- QDMA_TRQ_SEL_H2C_MM (0x1200) ----------------*/ -#define QDMA_OFFSET_H2C_MM_CONTROL 0x1204 -#define QDMA_OFFSET_H2C_MM_CONTROL_W1S 0x1208 -#define QDMA_OFFSET_H2C_MM_CONTROL_W1C 0x120C -#define QDMA_OFFSET_H2C_MM_STATUS 0x1240 -#define QDMA_OFFSET_H2C_MM_STATUS_RC 0x1244 -#define QDMA_OFFSET_H2C_MM_COMPLETED_DESC_COUNT 0x1248 -#define QDMA_OFFSET_H2C_MM_ERR_CODE_EN_MASK 0x1254 -#define QDMA_OFFSET_H2C_MM_ERR_CODE 0x1258 -#define QDMA_OFFSET_H2C_MM_ERR_INFO 0x125C -#define QDMA_OFFSET_H2C_MM_PERF_MON_CONTROL 0x12C0 -#define QDMA_OFFSET_H2C_MM_PERF_MON_CYCLE_COUNT_0 0x12C4 -#define QDMA_OFFSET_H2C_MM_PERF_MON_CYCLE_COUNT_1 0x12C8 -#define QDMA_OFFSET_H2C_MM_PERF_MON_DATA_COUNT_0 0x12CC -#define QDMA_OFFSET_H2C_MM_PERF_MON_DATA_COUNT_1 0x12D0 -#define QDMA_OFFSET_H2C_MM_DEBUG 0x12E8 - -/* ------------------------- QDMA_TRQ_SEL_C2H_MM (0x1000) ----------------*/ -#define QDMA_OFFSET_C2H_MM_CONTROL 0x1004 -#define QDMA_OFFSET_C2H_MM_CONTROL_W1S 0x1008 -#define QDMA_OFFSET_C2H_MM_CONTROL_W1C 0x100C -#define QDMA_OFFSET_C2H_MM_STATUS 0x1040 -#define QDMA_OFFSET_C2H_MM_STATUS_RC 0x1044 -#define QDMA_OFFSET_C2H_MM_COMPLETED_DESC_COUNT 0x1048 -#define QDMA_OFFSET_C2H_MM_ERR_CODE_EN_MASK 0x1054 -#define QDMA_OFFSET_C2H_MM_ERR_CODE 0x1058 -#define QDMA_OFFSET_C2H_MM_ERR_INFO 0x105C -#define QDMA_OFFSET_C2H_MM_PERF_MON_CONTROL 0x10C0 -#define QDMA_OFFSET_C2H_MM_PERF_MON_CYCLE_COUNT_0 0x10C4 -#define QDMA_OFFSET_C2H_MM_PERF_MON_CYCLE_COUNT_1 0x10C8 -#define QDMA_OFFSET_C2H_MM_PERF_MON_DATA_COUNT_0 0x10CC -#define QDMA_OFFSET_C2H_MM_PERF_MON_DATA_COUNT_1 0x10D0 -#define QDMA_OFFSET_C2H_MM_DEBUG 0x10E8 - -/* ------------------------- QDMA_TRQ_SEL_GLBL1 (0x0) -----------------*/ -#define QDMA_OFFSET_CONFIG_BLOCK_ID 0x0 -#define QDMA_CONFIG_BLOCK_ID_MASK GENMASK(31, 16) - - -/* ------------------------- QDMA_TRQ_SEL_GLBL2 (0x00100) ----------------*/ -#define QDMA_OFFSET_GLBL2_ID 0x100 -#define QDMA_OFFSET_GLBL2_PF_BARLITE_INT 0x104 -#define QDMA_GLBL2_PF3_BAR_MAP_MASK GENMASK(23, 18) -#define QDMA_GLBL2_PF2_BAR_MAP_MASK GENMASK(17, 12) -#define QDMA_GLBL2_PF1_BAR_MAP_MASK GENMASK(11, 6) -#define QDMA_GLBL2_PF0_BAR_MAP_MASK GENMASK(5, 0) -#define QDMA_OFFSET_GLBL2_PF_VF_BARLITE_INT 0x108 -#define QDMA_OFFSET_GLBL2_PF_BARLITE_EXT 0x10C -#define QDMA_OFFSET_GLBL2_PF_VF_BARLITE_EXT 0x110 -#define QDMA_OFFSET_GLBL2_CHANNEL_INST 0x114 -#define QDMA_OFFSET_GLBL2_CHANNEL_MDMA 0x118 -#define QDMA_GLBL2_ST_C2H_MASK BIT(17) -#define QDMA_GLBL2_ST_H2C_MASK BIT(16) -#define QDMA_GLBL2_MM_C2H_MASK BIT(8) -#define QDMA_GLBL2_MM_H2C_MASK BIT(0) -#define QDMA_OFFSET_GLBL2_CHANNEL_STRM 0x11C -#define QDMA_OFFSET_GLBL2_CHANNEL_QDMA_CAP 0x120 -#define QDMA_GLBL2_MULTQ_MAX_MASK GENMASK(11, 0) -#define QDMA_OFFSET_GLBL2_CHANNEL_PASID_CAP 0x128 -#define QDMA_OFFSET_GLBL2_CHANNEL_FUNC_RET 0x12C -#define QDMA_OFFSET_GLBL2_SYSTEM_ID 0x130 -#define QDMA_OFFSET_GLBL2_MISC_CAP 0x134 - -#define QDMA_GLBL2_DEVICE_ID_MASK GENMASK(31, 28) -#define QDMA_GLBL2_VIVADO_RELEASE_MASK GENMASK(27, 24) -#define QDMA_GLBL2_VERSAL_IP_MASK GENMASK(23, 20) -#define QDMA_GLBL2_RTL_VERSION_MASK GENMASK(19, 16) -#define QDMA_OFFSET_GLBL2_DBG_PCIE_RQ0 0x1B8 -#define QDMA_OFFSET_GLBL2_DBG_PCIE_RQ1 0x1BC -#define QDMA_OFFSET_GLBL2_DBG_AXIMM_WR0 0x1C0 -#define QDMA_OFFSET_GLBL2_DBG_AXIMM_WR1 0x1C4 -#define QDMA_OFFSET_GLBL2_DBG_AXIMM_RD0 0x1C8 -#define QDMA_OFFSET_GLBL2_DBG_AXIMM_RD1 0x1CC - -/* used for VF bars identification */ -#define QDMA_OFFSET_VF_USER_BAR_ID 0x1018 -#define QDMA_OFFSET_VF_CONFIG_BAR_ID 0x1014 - -/* FLR programming */ -#define QDMA_OFFSET_VF_REG_FLR_STATUS 0x1100 -#define QDMA_OFFSET_PF_REG_FLR_STATUS 0x2500 -#define QDMA_FLR_STATUS_MASK 0x1 - -/* VF qdma version */ -#define QDMA_OFFSET_VF_VERSION 0x1014 -#define QDMA_OFFSET_PF_VERSION 0x2414 -#define QDMA_GLBL2_VF_UNIQUE_ID_MASK GENMASK(31, 16) -#define QDMA_GLBL2_VF_DEVICE_ID_MASK GENMASK(15, 12) -#define QDMA_GLBL2_VF_VIVADO_RELEASE_MASK GENMASK(11, 8) -#define QDMA_GLBL2_VF_VERSAL_IP_MASK GENMASK(7, 4) -#define QDMA_GLBL2_VF_RTL_VERSION_MASK GENMASK(3, 0) - - -/* ------------------------- QDMA_TRQ_SEL_QUEUE_PF (0x18000) ----------------*/ - -#define QDMA_OFFSET_DMAP_SEL_INT_CIDX 0x18000 -#define QDMA_OFFSET_DMAP_SEL_H2C_DSC_PIDX 0x18004 -#define QDMA_OFFSET_DMAP_SEL_C2H_DSC_PIDX 0x18008 -#define QDMA_OFFSET_DMAP_SEL_CMPT_CIDX 0x1800C - -#define QDMA_OFFSET_VF_DMAP_SEL_INT_CIDX 0x3000 -#define QDMA_OFFSET_VF_DMAP_SEL_H2C_DSC_PIDX 0x3004 -#define QDMA_OFFSET_VF_DMAP_SEL_C2H_DSC_PIDX 0x3008 -#define QDMA_OFFSET_VF_DMAP_SEL_CMPT_CIDX 0x300C - -#define QDMA_DMA_SEL_INT_SW_CIDX_MASK GENMASK(15, 0) -#define QDMA_DMA_SEL_INT_RING_IDX_MASK GENMASK(23, 16) -#define QDMA_DMA_SEL_DESC_PIDX_MASK GENMASK(15, 0) -#define QDMA_DMA_SEL_IRQ_EN_MASK BIT(16) -#define QDMA_DMAP_SEL_CMPT_IRQ_EN_MASK BIT(28) -#define QDMA_DMAP_SEL_CMPT_STS_DESC_EN_MASK BIT(27) -#define QDMA_DMAP_SEL_CMPT_TRG_MODE_MASK GENMASK(26, 24) -#define QDMA_DMAP_SEL_CMPT_TMR_CNT_MASK GENMASK(23, 20) -#define QDMA_DMAP_SEL_CMPT_CNT_THRESH_MASK GENMASK(19, 16) -#define QDMA_DMAP_SEL_CMPT_WRB_CIDX_MASK GENMASK(15, 0) - -/* ------------------------- Hardware Errors ------------------------------ */ -#define TOTAL_LEAF_ERROR_AGGREGATORS 7 - -#define QDMA_OFFSET_GLBL_ERR_INT 0xB04 -#define QDMA_GLBL_ERR_FUNC_MASK GENMASK(7, 0) -#define QDMA_GLBL_ERR_VEC_MASK GENMASK(22, 12) -#define QDMA_GLBL_ERR_ARM_MASK BIT(24) - -#define QDMA_OFFSET_GLBL_ERR_STAT 0x248 -#define QDMA_OFFSET_GLBL_ERR_MASK 0x24C -#define QDMA_GLBL_ERR_RAM_SBE_MASK BIT(0) -#define QDMA_GLBL_ERR_RAM_DBE_MASK BIT(1) -#define QDMA_GLBL_ERR_DSC_MASK BIT(2) -#define QDMA_GLBL_ERR_TRQ_MASK BIT(3) -#define QDMA_GLBL_ERR_ST_C2H_MASK BIT(8) -#define QDMA_GLBL_ERR_ST_H2C_MASK BIT(11) - -#define QDMA_OFFSET_C2H_ERR_STAT 0xAF0 -#define QDMA_OFFSET_C2H_ERR_MASK 0xAF4 -#define QDMA_C2H_ERR_MTY_MISMATCH_MASK BIT(0) -#define QDMA_C2H_ERR_LEN_MISMATCH_MASK BIT(1) -#define QDMA_C2H_ERR_QID_MISMATCH_MASK BIT(3) -#define QDMA_C2H_ERR_DESC_RSP_ERR_MASK BIT(4) -#define QDMA_C2H_ERR_ENG_WPL_DATA_PAR_ERR_MASK BIT(6) -#define QDMA_C2H_ERR_MSI_INT_FAIL_MASK BIT(7) -#define QDMA_C2H_ERR_ERR_DESC_CNT_MASK BIT(9) -#define QDMA_C2H_ERR_PORTID_CTXT_MISMATCH_MASK BIT(10) -#define QDMA_C2H_ERR_PORTID_BYP_IN_MISMATCH_MASK BIT(11) -#define QDMA_C2H_ERR_CMPT_INV_Q_ERR_MASK BIT(12) -#define QDMA_C2H_ERR_CMPT_QFULL_ERR_MASK BIT(13) -#define QDMA_C2H_ERR_CMPT_CIDX_ERR_MASK BIT(14) -#define QDMA_C2H_ERR_CMPT_PRTY_ERR_MASK BIT(15) -#define QDMA_C2H_ERR_ALL_MASK 0xFEDB - -#define QDMA_OFFSET_C2H_FATAL_ERR_STAT 0xAF8 -#define QDMA_OFFSET_C2H_FATAL_ERR_MASK 0xAFC -#define QDMA_C2H_FATAL_ERR_MTY_MISMATCH_MASK BIT(0) -#define QDMA_C2H_FATAL_ERR_LEN_MISMATCH_MASK BIT(1) -#define QDMA_C2H_FATAL_ERR_QID_MISMATCH_MASK BIT(3) -#define QDMA_C2H_FATAL_ERR_TIMER_FIFO_RAM_RDBE_MASK BIT(4) -#define QDMA_C2H_FATAL_ERR_PFCH_II_RAM_RDBE_MASK BIT(8) -#define QDMA_C2H_FATAL_ERR_CMPT_CTXT_RAM_RDBE_MASK BIT(9) -#define QDMA_C2H_FATAL_ERR_PFCH_CTXT_RAM_RDBE_MASK BIT(10) -#define QDMA_C2H_FATAL_ERR_DESC_REQ_FIFO_RAM_RDBE_MASK BIT(11) -#define QDMA_C2H_FATAL_ERR_INT_CTXT_RAM_RDBE_MASK BIT(12) -#define QDMA_C2H_FATAL_ERR_CMPT_COAL_DATA_RAM_RDBE_MASK BIT(14) -#define QDMA_C2H_FATAL_ERR_TUSER_FIFO_RAM_RDBE_MASK BIT(15) -#define QDMA_C2H_FATAL_ERR_QID_FIFO_RAM_RDBE_MASK BIT(16) -#define QDMA_C2H_FATAL_ERR_PAYLOAD_FIFO_RAM_RDBE_MASK BIT(17) -#define QDMA_C2H_FATAL_ERR_WPL_DATA_PAR_MASK BIT(18) -#define QDMA_C2H_FATAL_ERR_ALL_MASK 0x7DF1B - -#define QDMA_OFFSET_H2C_ERR_STAT 0xE00 -#define QDMA_OFFSET_H2C_ERR_MASK 0xE04 -#define QDMA_H2C_ERR_ZERO_LEN_DESC_MASK BIT(0) -#define QDMA_H2C_ERR_CSI_MOP_MASK BIT(1) -#define QDMA_H2C_ERR_NO_DMA_DSC_MASK BIT(2) -#define QDMA_H2C_ERR_SBE_MASK BIT(3) -#define QDMA_H2C_ERR_DBE_MASK BIT(4) -#define QDMA_H2C_ERR_ALL_MASK 0x1F - -#define QDMA_OFFSET_GLBL_DSC_ERR_STAT 0x254 -#define QDMA_OFFSET_GLBL_DSC_ERR_MASK 0x258 -#define QDMA_GLBL_DSC_ERR_POISON_MASK BIT(0) -#define QDMA_GLBL_DSC_ERR_UR_CA_MASK BIT(1) -#define QDMA_GLBL_DSC_ERR_PARAM_MASK BIT(2) -#define QDMA_GLBL_DSC_ERR_ADDR_MASK BIT(3) -#define QDMA_GLBL_DSC_ERR_TAG_MASK BIT(4) -#define QDMA_GLBL_DSC_ERR_FLR_MASK BIT(5) -#define QDMA_GLBL_DSC_ERR_TIMEOUT_MASK BIT(9) -#define QDMA_GLBL_DSC_ERR_DAT_POISON_MASK BIT(16) -#define QDMA_GLBL_DSC_ERR_FLR_CANCEL_MASK BIT(19) -#define QDMA_GLBL_DSC_ERR_DMA_MASK BIT(20) -#define QDMA_GLBL_DSC_ERR_DSC_MASK BIT(21) -#define QDMA_GLBL_DSC_ERR_RQ_CANCEL_MASK BIT(22) -#define QDMA_GLBL_DSC_ERR_DBE_MASK BIT(23) -#define QDMA_GLBL_DSC_ERR_SBE_MASK BIT(24) -#define QDMA_GLBL_DSC_ERR_ALL_MASK 0x1F9023F - -#define QDMA_OFFSET_GLBL_TRQ_ERR_STAT 0x264 -#define QDMA_OFFSET_GLBL_TRQ_ERR_MASK 0x268 -#define QDMA_GLBL_TRQ_ERR_UNMAPPED_MASK BIT(0) -#define QDMA_GLBL_TRQ_ERR_QID_RANGE_MASK BIT(1) -#define QDMA_GLBL_TRQ_ERR_VF_ACCESS_MASK BIT(2) -#define QDMA_GLBL_TRQ_ERR_TCP_TIMEOUT_MASK BIT(3) -#define QDMA_GLBL_TRQ_ERR_ALL_MASK 0xF - -#define QDMA_OFFSET_RAM_SBE_STAT 0xF4 -#define QDMA_OFFSET_RAM_SBE_MASK 0xF0 -#define QDMA_SBE_ERR_MI_H2C0_DAT_MASK BIT(0) -#define QDMA_SBE_ERR_MI_C2H0_DAT_MASK BIT(4) -#define QDMA_SBE_ERR_H2C_RD_BRG_DAT_MASK BIT(9) -#define QDMA_SBE_ERR_H2C_WR_BRG_DAT_MASK BIT(10) -#define QDMA_SBE_ERR_C2H_RD_BRG_DAT_MASK BIT(11) -#define QDMA_SBE_ERR_C2H_WR_BRG_DAT_MASK BIT(12) -#define QDMA_SBE_ERR_FUNC_MAP_MASK BIT(13) -#define QDMA_SBE_ERR_DSC_HW_CTXT_MASK BIT(14) -#define QDMA_SBE_ERR_DSC_CRD_RCV_MASK BIT(15) -#define QDMA_SBE_ERR_DSC_SW_CTXT_MASK BIT(16) -#define QDMA_SBE_ERR_DSC_CPLI_MASK BIT(17) -#define QDMA_SBE_ERR_DSC_CPLD_MASK BIT(18) -#define QDMA_SBE_ERR_PASID_CTXT_RAM_MASK BIT(19) -#define QDMA_SBE_ERR_TIMER_FIFO_RAM_MASK BIT(20) -#define QDMA_SBE_ERR_PAYLOAD_FIFO_RAM_MASK BIT(21) -#define QDMA_SBE_ERR_QID_FIFO_RAM_MASK BIT(22) -#define QDMA_SBE_ERR_TUSER_FIFO_RAM_MASK BIT(23) -#define QDMA_SBE_ERR_WRB_COAL_DATA_RAM_MASK BIT(24) -#define QDMA_SBE_ERR_INT_QID2VEC_RAM_MASK BIT(25) -#define QDMA_SBE_ERR_INT_CTXT_RAM_MASK BIT(26) -#define QDMA_SBE_ERR_DESC_REQ_FIFO_RAM_MASK BIT(27) -#define QDMA_SBE_ERR_PFCH_CTXT_RAM_MASK BIT(28) -#define QDMA_SBE_ERR_WRB_CTXT_RAM_MASK BIT(29) -#define QDMA_SBE_ERR_PFCH_LL_RAM_MASK BIT(30) -#define QDMA_SBE_ERR_H2C_PEND_FIFO_MASK BIT(31) -#define QDMA_SBE_ERR_ALL_MASK 0xFFFFFF11 - -#define QDMA_OFFSET_RAM_DBE_STAT 0xFC -#define QDMA_OFFSET_RAM_DBE_MASK 0xF8 -#define QDMA_DBE_ERR_MI_H2C0_DAT_MASK BIT(0) -#define QDMA_DBE_ERR_MI_C2H0_DAT_MASK BIT(4) -#define QDMA_DBE_ERR_H2C_RD_BRG_DAT_MASK BIT(9) -#define QDMA_DBE_ERR_H2C_WR_BRG_DAT_MASK BIT(10) -#define QDMA_DBE_ERR_C2H_RD_BRG_DAT_MASK BIT(11) -#define QDMA_DBE_ERR_C2H_WR_BRG_DAT_MASK BIT(12) -#define QDMA_DBE_ERR_FUNC_MAP_MASK BIT(13) -#define QDMA_DBE_ERR_DSC_HW_CTXT_MASK BIT(14) -#define QDMA_DBE_ERR_DSC_CRD_RCV_MASK BIT(15) -#define QDMA_DBE_ERR_DSC_SW_CTXT_MASK BIT(16) -#define QDMA_DBE_ERR_DSC_CPLI_MASK BIT(17) -#define QDMA_DBE_ERR_DSC_CPLD_MASK BIT(18) -#define QDMA_DBE_ERR_PASID_CTXT_RAM_MASK BIT(19) -#define QDMA_DBE_ERR_TIMER_FIFO_RAM_MASK BIT(20) -#define QDMA_DBE_ERR_PAYLOAD_FIFO_RAM_MASK BIT(21) -#define QDMA_DBE_ERR_QID_FIFO_RAM_MASK BIT(22) -#define QDMA_DBE_ERR_TUSER_FIFO_RAM_MASK BIT(23) -#define QDMA_DBE_ERR_WRB_COAL_DATA_RAM_MASK BIT(24) -#define QDMA_DBE_ERR_INT_QID2VEC_RAM_MASK BIT(25) -#define QDMA_DBE_ERR_INT_CTXT_RAM_MASK BIT(26) -#define QDMA_DBE_ERR_DESC_REQ_FIFO_RAM_MASK BIT(27) -#define QDMA_DBE_ERR_PFCH_CTXT_RAM_MASK BIT(28) -#define QDMA_DBE_ERR_WRB_CTXT_RAM_MASK BIT(29) -#define QDMA_DBE_ERR_PFCH_LL_RAM_MASK BIT(30) -#define QDMA_DBE_ERR_H2C_PEND_FIFO_MASK BIT(31) -#define QDMA_DBE_ERR_ALL_MASK 0xFFFFFF11 - -#define QDMA_OFFSET_MBOX_BASE_VF 0x1000 -#define QDMA_OFFSET_MBOX_BASE_PF 0x2400 - -#ifdef __cplusplus -} -#endif - -#endif /* __QDMA_SOFT_REG_H__ */ diff --git a/QDMA/linux-kernel/driver/libqdma/qdma_compat.h b/QDMA/linux-kernel/driver/libqdma/qdma_compat.h deleted file mode 100755 index ded71b588..000000000 --- a/QDMA/linux-kernel/driver/libqdma/qdma_compat.h +++ /dev/null @@ -1,107 +0,0 @@ -/* - * This file is part of the Xilinx DMA IP Core driver for Linux - * - * Copyright (c) 2017-2022, Xilinx, Inc. All rights reserved. - * Copyright (c) 2022, Advanced Micro Devices, Inc. All rights reserved. - * - * This source code is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * The full GNU General Public License is included in this distribution in - * the file called "COPYING". - */ - -/** - * @file - * @brief This file is used to allow the driver to be compiled under multiple - * versions of Linux with as few obtrusive in-line ifdef's as possible. - */ - -#ifndef __QDMA_COMPAT_H -#define __QDMA_COMPAT_H - -#include -#include -#include - -/** - * if linux kernel version is < 3.19.0 - * then define the dma_rmb and dma_wmb - */ -#if KERNEL_VERSION(3, 19, 0) > LINUX_VERSION_CODE - -#ifndef dma_rmb -#define dma_rmb rmb -#endif /* #ifndef dma_rmb */ - -#ifndef dma_wmb -#define dma_wmb wmb -#endif /* #ifndef dma_wmb */ - -#endif - -#ifdef RHEL_RELEASE_VERSION -#define qdma_wait_queue wait_queue_head_t -#define qdma_waitq_init init_waitqueue_head -#define qdma_waitq_wakeup wake_up_interruptible -#define qdma_waitq_wait_event wait_event_interruptible -#define qdma_waitq_wait_event_timeout wait_event_interruptible_timeout -#else -/* use simple wait queue (swaitq) with kernels > 4.6.0 but < 4.19.0 */ -#if ((KERNEL_VERSION(4, 6, 0) <= LINUX_VERSION_CODE) && \ - (KERNEL_VERSION(4, 19, 0) >= LINUX_VERSION_CODE)) -#include - -#define qdma_wait_queue struct swait_queue_head -#define qdma_waitq_init init_swait_queue_head -#define qdma_waitq_wakeup swake_up -#define qdma_waitq_wait_event swait_event_interruptible -#define qdma_waitq_wait_event_timeout swait_event_interruptible_timeout - -#else -#include - -#define qdma_wait_queue wait_queue_head_t -#define qdma_waitq_init init_waitqueue_head -#define qdma_waitq_wakeup wake_up_interruptible -#define qdma_waitq_wait_event wait_event_interruptible -#define qdma_waitq_wait_event_timeout wait_event_interruptible_timeout - -#endif /* swaitq */ -#endif - -/* timer */ -#if KERNEL_VERSION(4, 15, 0) <= LINUX_VERSION_CODE -#define qdma_timer_setup(timer, fp_handler, data) \ - timer_setup(timer, fp_handler, 0) - -#define qdma_timer_start(timer, expires) \ - mod_timer(timer, round_jiffies(jiffies + (expires))) - -#else -#define qdma_timer_setup(timer, fp_handler, priv) \ - do { \ - init_timer(timer); \ - timer->data = (unsigned long)priv; \ - timer->function = fp_handler; \ - del_timer(timer); \ - } while (0) - -#define qdma_timer_start(timer, timeout) \ - do { \ - del_timer(timer); \ - timer->expires = jiffies + (timeout); \ - add_timer(timer); \ - } while (0) - - -#endif /* timer */ - - -#endif /* #ifndef __QDMA_COMPAT_H */ diff --git a/QDMA/linux-kernel/driver/libqdma/qdma_context.c b/QDMA/linux-kernel/driver/libqdma/qdma_context.c deleted file mode 100755 index 246280b32..000000000 --- a/QDMA/linux-kernel/driver/libqdma/qdma_context.c +++ /dev/null @@ -1,952 +0,0 @@ -/* - * This file is part of the Xilinx DMA IP Core driver for Linux - * - * Copyright (c) 2017-2022, Xilinx, Inc. All rights reserved. - * Copyright (c) 2022, Advanced Micro Devices, Inc. All rights reserved. - * - * This source code is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * The full GNU General Public License is included in this distribution in - * the file called "COPYING". - */ - -#define pr_fmt(fmt) KBUILD_MODNAME ":%s: " fmt, __func__ - -#include -#include -#include "qdma_device.h" -#include "qdma_descq.h" -#include "qdma_intr.h" -#include "qdma_regs.h" -#include "qdma_context.h" -#include "qdma_access_common.h" -#include "qdma_mbox_protocol.h" - -/** - * Make the interrupt context - */ -static int make_intr_context(struct xlnx_dma_dev *xdev, - struct qdma_indirect_intr_ctxt *ctxt) -{ - int i; - - if ((xdev->conf.qdma_drv_mode != INDIRECT_INTR_MODE) && - (xdev->conf.qdma_drv_mode != AUTO_MODE)) { - pr_err("Invalid driver mode: %d", xdev->conf.qdma_drv_mode); - return -EINVAL; - } - - /** program the coalescing context - * i -> Number of vectors - */ - for (i = 0; i < QDMA_NUM_DATA_VEC_FOR_INTR_CXT; i++) { - struct intr_coal_conf *entry = (xdev->intr_coal_list + i); - - ctxt[i].valid = 1; - ctxt[i].vec = entry->vec_id; - ctxt[i].baddr_4k = entry->intr_ring_bus; - ctxt[i].color = entry->color; - ctxt[i].page_size = xdev->conf.intr_rngsz; - ctxt[i].func_id = xdev->func_id; - } - - return 0; -} - -#ifndef __QDMA_VF__ -static int make_sw_context(struct qdma_descq *descq, - struct qdma_descq_sw_ctxt *sw_ctxt) -{ - memset(sw_ctxt, 0, sizeof(struct qdma_descq_sw_ctxt)); - - /* sw context */ - if ((descq->xdev->conf.qdma_drv_mode == INDIRECT_INTR_MODE) || - (descq->xdev->conf.qdma_drv_mode == AUTO_MODE)) { - sw_ctxt->vec = get_intr_ring_index(descq->xdev, - descq->intr_id); - sw_ctxt->intr_aggr = 0x01; - } else { - sw_ctxt->vec = descq->intr_id; - } - - sw_ctxt->ring_bs_addr = descq->desc_bus; - sw_ctxt->wbi_chk = descq->conf.cmpl_status_pend_chk; - sw_ctxt->wbi_intvl_en = descq->conf.cmpl_status_acc_en; - sw_ctxt->rngsz_idx = descq->conf.desc_rng_sz_idx; - sw_ctxt->bypass = descq->conf.desc_bypass; - sw_ctxt->wbk_en = descq->conf.wb_status_en; - sw_ctxt->irq_en = descq->conf.irq_en; - sw_ctxt->is_mm = ~descq->conf.st; - sw_ctxt->qen = 1; - - if (descq->conf.desc_bypass && - (descq->conf.sw_desc_sz == DESC_SZ_64B)) { - sw_ctxt->desc_sz = descq->conf.sw_desc_sz; - } else { - sw_ctxt->fetch_max = FETCH_MAX_NUM; - if (!descq->conf.st) { /* mm h2c/c2h */ - sw_ctxt->desc_sz = DESC_SZ_32B; - sw_ctxt->mm_chn = descq->channel; - sw_ctxt->host_id = descq->channel; - } else if (descq->conf.q_type == Q_C2H) { /* st c2h */ - sw_ctxt->frcd_en = descq->conf.fetch_credit; - sw_ctxt->desc_sz = DESC_SZ_8B; - } else if (descq->conf.q_type == Q_H2C) { /* st h2c */ - sw_ctxt->frcd_en = descq->conf.fetch_credit; - sw_ctxt->desc_sz = DESC_SZ_16B; - } else - sw_ctxt->desc_sz = DESC_SZ_16B; - } - - /* pidx = 0; irq_ack = 0 */ - sw_ctxt->fnc_id = descq->xdev->func_id; - sw_ctxt->irq_arm = descq->conf.irq_en; - - if (descq->conf.st && (descq->conf.q_type == Q_C2H)) { - sw_ctxt->irq_en = 0; - sw_ctxt->irq_arm = 0; - sw_ctxt->wbk_en = 0; - sw_ctxt->wbi_chk = 0; - } - - /* Disable the marker response. Not applicable for ST C2H */ - if ((!descq->conf.desc_bypass) && - ((!descq->conf.st) || (descq->conf.q_type == Q_H2C))) - sw_ctxt->mrkr_dis = 1; - -#ifdef ERR_DEBUG - if (descq->induce_err & (1 << param)) { - sw_ctxt->fnc_id = 0xFFF; - pr_info("induced error %d", ind_ctxt_cmd_err); - } -#endif - - return 0; -} - -static int make_qid2vec_context(struct qdma_descq *descq, - struct qdma_qid2vec *cntxt) -{ - u32 vec_num = 0; - u32 en_coal = 0; - struct xlnx_dma_dev *xdev = NULL; - - BUG_ON(!descq); - BUG_ON(!cntxt); - - vec_num = descq->intr_id; - xdev = descq->xdev; - - memset(cntxt, 0, sizeof(struct qdma_qid2vec)); - /* - * Enable interrupt coalescing - * In case of Indirect interrupt, interrupt ring index and enable - * coalescing should be programmed. In case of Direct interrupt, - * interrupt vector number should be programmed - */ - if ((descq->xdev->conf.qdma_drv_mode == INDIRECT_INTR_MODE) || - (descq->xdev->conf.qdma_drv_mode == AUTO_MODE)) { - vec_num = get_intr_ring_index(xdev, descq->intr_id); - en_coal = 1; - } - if (descq->conf.q_type == Q_C2H) { - cntxt->c2h_en_coal = en_coal; - cntxt->c2h_vector = vec_num; - } else if (descq->conf.q_type == Q_H2C) { - cntxt->h2c_en_coal = en_coal; - cntxt->h2c_vector = vec_num; - } - - pr_debug("qid2vec context :\n c2h_vector = %x\n" - "c2h_en_coal = %x\n" - "h2c_vector = %x\nh2c_en_coal = %x\n", - cntxt->c2h_vector, - cntxt->c2h_en_coal, cntxt->h2c_vector, cntxt->h2c_en_coal); - return 0; -} - -/* ST: prefetch context setup */ -static int make_prefetch_context(struct qdma_descq *descq, - struct qdma_descq_prefetch_ctxt *pfetch_ctxt) -{ - BUG_ON(!descq); - BUG_ON(!pfetch_ctxt); - - memset(pfetch_ctxt, 0, sizeof(struct qdma_descq_prefetch_ctxt)); - - /* prefetch context */ - pfetch_ctxt->valid = 1; - pfetch_ctxt->bypass = descq->conf.pfetch_bypass; - pfetch_ctxt->bufsz_idx = descq->conf.c2h_buf_sz_idx; - pfetch_ctxt->pfch_en = descq->conf.pfetch_en; - - return 0; -} - -/* ST C2H : writeback context setup */ -static int make_cmpt_context(struct qdma_descq *descq, - struct qdma_descq_cmpt_ctxt *cmpt_ctxt) -{ - int ring_index; - - memset(cmpt_ctxt, 0, sizeof(struct qdma_descq_cmpt_ctxt)); - - cmpt_ctxt->en_stat_desc = descq->conf.cmpl_stat_en; - cmpt_ctxt->en_int = descq->conf.cmpl_en_intr; - cmpt_ctxt->trig_mode = descq->conf.cmpl_trig_mode; - cmpt_ctxt->fnc_id = descq->xdev->func_id; - cmpt_ctxt->timer_idx = descq->conf.cmpl_timer_idx; - cmpt_ctxt->counter_idx = descq->conf.cmpl_cnt_th_idx; - cmpt_ctxt->color = 1; - cmpt_ctxt->ringsz_idx = descq->conf.cmpl_rng_sz_idx; - - cmpt_ctxt->bs_addr = descq->desc_cmpt_bus; - cmpt_ctxt->desc_sz = descq->conf.cmpl_desc_sz; - cmpt_ctxt->full_upd = descq->conf.adaptive_rx; - - cmpt_ctxt->valid = 1; - - cmpt_ctxt->ovf_chk_dis = descq->conf.cmpl_ovf_chk_dis; - if ((descq->xdev->conf.qdma_drv_mode == INDIRECT_INTR_MODE) || - (descq->xdev->conf.qdma_drv_mode == AUTO_MODE)) { - ring_index = get_intr_ring_index(descq->xdev, descq->intr_id); - cmpt_ctxt->vec = ring_index; - cmpt_ctxt->int_aggr = 1; - } else { - cmpt_ctxt->vec = descq->intr_id; - } - - return 0; -} -#endif - -#ifdef __QDMA_VF__ -int qdma_intr_context_setup(struct xlnx_dma_dev *xdev) -{ - int i = 0; - int rv; - struct mbox_msg *m = NULL; - struct mbox_msg_intr_ctxt ictxt; - - if ((xdev->conf.qdma_drv_mode != INDIRECT_INTR_MODE) && - (xdev->conf.qdma_drv_mode != AUTO_MODE)) - return 0; - - m = qdma_mbox_msg_alloc(); - if (!m) - return -ENOMEM; - - memset(&ictxt, 0, sizeof(struct mbox_msg_intr_ctxt)); - - ictxt.num_rings = QDMA_NUM_DATA_VEC_FOR_INTR_CXT; - - for (i = 0; i < QDMA_NUM_DATA_VEC_FOR_INTR_CXT; i++) { - ictxt.ring_index_list[i] = - get_intr_ring_index(xdev, xdev->dvec_start_idx + i); - } - - rv = make_intr_context(xdev, ictxt.ictxt); - if (rv < 0) - goto free_msg; - - qdma_mbox_compose_vf_intr_ctxt_write(xdev->func_id, &ictxt, m->raw); - rv = qdma_mbox_msg_send(xdev, m, 1, QDMA_MBOX_MSG_TIMEOUT_MS); - if (rv < 0) { - pr_err("%s, mbox failed for interrupt context %d.\n", - xdev->conf.name, rv); - goto free_msg; - } - rv = qdma_mbox_vf_response_status(m->raw); - if (rv < 0) { - pr_err("mbox_vf_response_status failed, err = %d", rv); - rv = -EINVAL; - } - -free_msg: - qdma_mbox_msg_free(m); - return rv; -} - -int qdma_intr_context_read(struct xlnx_dma_dev *xdev, - int ring_index, - struct qdma_indirect_intr_ctxt *ctxt) -{ - struct mbox_msg *m; - int rv = 0; - struct mbox_msg_intr_ctxt ictxt; - - m = qdma_mbox_msg_alloc(); - if (!m) - return -ENOMEM; - memset(&ictxt, 0, sizeof(struct mbox_msg_intr_ctxt)); - ictxt.num_rings = 1; - - ictxt.ring_index_list[0] = ring_index; - qdma_mbox_compose_vf_intr_ctxt_read(xdev->func_id, - &ictxt, m->raw); - rv = qdma_mbox_msg_send(xdev, m, 1, QDMA_MBOX_MSG_TIMEOUT_MS); - if (rv < 0) { - pr_err("%s invalidate interrupt context failed %d.\n", - xdev->conf.name, rv); - } - rv = qdma_mbox_vf_intr_context_get(m->raw, &ictxt); - if (rv < 0) { - pr_err("mbox_vf_intr_context_get failed, err = %d", rv); - rv = -EINVAL; - } else - memcpy(ctxt, &ictxt.ictxt[0], - sizeof(struct qdma_indirect_intr_ctxt)); - - qdma_mbox_msg_free(m); - - return rv; -} - -int qdma_descq_context_clear(struct xlnx_dma_dev *xdev, unsigned int qid_hw, - bool st, u8 type, bool clr) -{ - struct mbox_msg *m = qdma_mbox_msg_alloc(); - int rv; - enum mbox_cmpt_ctxt_type cmpt_ctxt_type = QDMA_MBOX_CMPT_CTXT_NONE; - - if (!m) - return -ENOMEM; - - if (!st) { - if (type == Q_CMPT) - cmpt_ctxt_type = QDMA_MBOX_CMPT_CTXT_ONLY; - else - cmpt_ctxt_type = QDMA_MBOX_CMPT_CTXT_NONE; - } else { - if (type == Q_C2H) - cmpt_ctxt_type = QDMA_MBOX_CMPT_WITH_ST; - } - - if (clr) - qdma_mbox_compose_vf_qctxt_clear(xdev->func_id, - qid_hw, st, type, cmpt_ctxt_type, m->raw); - else - qdma_mbox_compose_vf_qctxt_invalidate(xdev->func_id, - qid_hw, st, type, cmpt_ctxt_type, m->raw); - - rv = qdma_mbox_msg_send(xdev, m, 1, QDMA_MBOX_MSG_TIMEOUT_MS); - if (rv < 0) { - if (rv != -ENODEV) - pr_err("%s, qid_hw 0x%x mbox failed %d.\n", - xdev->conf.name, qid_hw, rv); - goto err_out; - } - - rv = qdma_mbox_vf_response_status(m->raw); - if (rv < 0) { - pr_err("mbox_vf_response_status failed, err = %d", rv); - rv = -EINVAL; - } - -err_out: - qdma_mbox_msg_free(m); - return rv; -} - -int qdma_descq_context_read(struct xlnx_dma_dev *xdev, unsigned int qid_hw, - bool st, u8 type, struct qdma_descq_context *context) -{ - struct mbox_msg *m = qdma_mbox_msg_alloc(); - int rv; - enum mbox_cmpt_ctxt_type cmpt_ctxt_type = QDMA_MBOX_CMPT_CTXT_NONE; - - if (!m) - return -ENOMEM; - - if (!st) { - if (type == Q_CMPT) - cmpt_ctxt_type = QDMA_MBOX_CMPT_CTXT_ONLY; - else - cmpt_ctxt_type = QDMA_MBOX_CMPT_CTXT_NONE; - } else { - if (type == Q_C2H) - cmpt_ctxt_type = QDMA_MBOX_CMPT_WITH_ST; - } - - qdma_mbox_compose_vf_qctxt_read(xdev->func_id, - qid_hw, st, type, cmpt_ctxt_type, m->raw); - - rv = qdma_mbox_msg_send(xdev, m, 1, QDMA_MBOX_MSG_TIMEOUT_MS); - if (rv < 0) { - if (rv != -ENODEV) - pr_err("%s, qid_hw 0x%x mbox failed %d.\n", - xdev->conf.name, qid_hw, rv); - goto err_out; - } - - rv = qdma_mbox_vf_context_get(m->raw, context); - if (rv < 0) { - pr_err("mbox_vf_context_get faled with error = %d", rv); - rv = -EINVAL; - } -err_out: - qdma_mbox_msg_free(m); - return rv; -} - -int qdma_descq_context_setup(struct qdma_descq *descq) -{ - struct xlnx_dma_dev *xdev = descq->xdev; - struct mbox_msg *m = qdma_mbox_msg_alloc(); - struct mbox_descq_conf descq_conf; - int rv; - enum mbox_cmpt_ctxt_type cmpt_ctxt_type = QDMA_MBOX_CMPT_CTXT_NONE; - - if (!m) - return -ENOMEM; - - memset(&descq_conf, 0, sizeof(struct mbox_descq_conf)); - descq_conf.ring_bs_addr = descq->desc_bus; - descq_conf.cmpt_ring_bs_addr = descq->desc_cmpt_bus; - descq_conf.en_bypass = descq->conf.desc_bypass; - descq_conf.irq_arm = descq->conf.irq_en; - descq_conf.wbi_intvl_en = descq->conf.cmpl_status_acc_en; - descq_conf.wbi_chk = descq->conf.cmpl_status_pend_chk; - descq_conf.at = descq->conf.at; - descq_conf.wbk_en = descq->conf.wb_status_en; - descq_conf.irq_en = descq->conf.irq_en; - descq_conf.pfch_en = descq->conf.pfetch_en; - descq_conf.en_bypass_prefetch = descq->conf.pfetch_bypass; - descq_conf.dis_overflow_check = descq->conf.cmpl_ovf_chk_dis; - descq_conf.cmpt_int_en = descq->conf.cmpl_en_intr; - descq_conf.cmpl_stat_en = descq->conf.cmpl_stat_en; - if (descq->conf.desc_bypass && - (descq->conf.sw_desc_sz == DESC_SZ_64B)) - descq_conf.desc_sz = descq->conf.sw_desc_sz; - else { - if (descq->conf.q_type != Q_CMPT) { - if (!descq->conf.st) /* mm h2c/c2h */ - descq_conf.desc_sz = DESC_SZ_32B; - else if (descq->conf.q_type) {/* st c2h */ - descq_conf.desc_sz = DESC_SZ_8B; - descq_conf.forced_en = descq->conf.fetch_credit; - } else /* st h2c */ - descq_conf.desc_sz = DESC_SZ_16B; - } - } - descq_conf.cmpt_desc_sz = descq->conf.cmpl_desc_sz; - descq_conf.triggermode = descq->conf.cmpl_trig_mode; - descq_conf.cmpt_at = descq->conf.at; - descq_conf.cmpt_color = 1; - descq_conf.cmpt_full_upd = 0; - descq_conf.func_id = descq->xdev->func_id; - descq_conf.cnt_thres = - xdev->csr_info.c2h_cnt_th[descq->conf.cmpl_cnt_th_idx]; - descq_conf.timer_thres = - xdev->csr_info.c2h_timer_cnt[descq->conf.cmpl_timer_idx]; - descq_conf.ringsz = descq->conf.rngsz; - descq_conf.bufsz = descq->conf.c2h_bufsz; - descq_conf.cmpt_ringsz = descq->conf.rngsz_cmpt; - if ((descq->xdev->conf.qdma_drv_mode == INDIRECT_INTR_MODE) || - (descq->xdev->conf.qdma_drv_mode == AUTO_MODE)) { - int ring_index = get_intr_ring_index(descq->xdev, - descq->intr_id); - descq_conf.intr_id = ring_index & 0xFFF; - descq_conf.intr_aggr = 1; - } else - descq_conf.intr_id = descq->intr_id; - - if (!descq->conf.st) { - if (descq->conf.q_type == Q_CMPT) - cmpt_ctxt_type = QDMA_MBOX_CMPT_CTXT_ONLY; - else - cmpt_ctxt_type = QDMA_MBOX_CMPT_CTXT_NONE; - } else { - if (descq->conf.q_type == Q_C2H) - cmpt_ctxt_type = QDMA_MBOX_CMPT_WITH_ST; - } - - qdma_mbox_compose_vf_qctxt_write(xdev->func_id, descq->qidx_hw, - descq->conf.st, descq->conf.q_type, - cmpt_ctxt_type, &descq_conf, m->raw); - - rv = qdma_mbox_msg_send(xdev, m, 1, QDMA_MBOX_MSG_TIMEOUT_MS); - if (rv < 0) { - if (rv != -ENODEV) - pr_err("%s, qid_hw 0x%x, %s mbox failed %d.\n", - xdev->conf.name, descq->qidx_hw, - descq->conf.name, rv); - goto err_out; - } - - rv = qdma_mbox_vf_response_status(m->raw); - if (rv < 0) { - pr_err("mbox_vf_response_status failed, err = %d", rv); - rv = -EINVAL; - } -err_out: - qdma_mbox_msg_free(m); - return rv; -} - -int qdma_descq_context_dump(struct qdma_descq *descq, char *buf, int buflen) -{ - int rv = 0; - int ring_index = -1; - int ring_count = 0; - int len = 0; - struct qdma_descq_context queue_context; - struct qdma_indirect_intr_ctxt intr_ctxt; - - rv = qdma_descq_context_read(descq->xdev, descq->qidx_hw, - descq->conf.st, descq->conf.q_type, &queue_context); - if (rv < 0) { - pr_err("Failed to read queue context, rv = %d", rv); - return rv; - } - - rv = descq->xdev->hw.qdma_dump_queue_context(descq->xdev, - descq->conf.st, - (enum qdma_dev_q_type)descq->conf.q_type, - &queue_context, - buf, buflen); - if (rv < 0) { - pr_err("Failed to dump queue context, rv = %d", rv); - return descq->xdev->hw.qdma_get_error_code(rv); - } - len = rv; - - /** if interrupt aggregation is enabled - * add the interrupt context - */ - if ((descq->xdev->conf.qdma_drv_mode == INDIRECT_INTR_MODE) || - (descq->xdev->conf.qdma_drv_mode == AUTO_MODE)) { - for (ring_count = 0; - ring_count < QDMA_NUM_DATA_VEC_FOR_INTR_CXT; - ring_count++) { - ring_index = get_intr_ring_index( - descq->xdev, - (descq->xdev->dvec_start_idx + - ring_count)); - - rv = qdma_intr_context_read(descq->xdev, - ring_index, &intr_ctxt); - if (rv < 0) { - pr_err("Failed to read intr context for ring %d, rv = %d", - ring_index, rv); - return rv; - } - - rv = descq->xdev->hw.qdma_dump_intr_context(descq->xdev, - &intr_ctxt, ring_index, - buf + len, buflen - len); - if (rv < 0) { - pr_err("Failed to dump intr context, rv = %d", - rv); - return descq->xdev->hw.qdma_get_error_code(rv); - } - len += rv; - } - } - - return len; -} - -#else /* PF only */ - -int qdma_prog_intr_context(struct xlnx_dma_dev *xdev, - struct mbox_msg_intr_ctxt *ictxt) -{ - int i = 0; - int rv; - int ring_index; - struct qdma_indirect_intr_ctxt *ctxt; - - for (i = 0; i < ictxt->num_rings; i++) { - ring_index = ictxt->ring_index_list[i]; - - ctxt = &ictxt->ictxt[i]; - rv = xdev->hw.qdma_indirect_intr_ctx_conf(xdev, ring_index, - ctxt, - QDMA_HW_ACCESS_WRITE); - if (rv < 0) { - pr_err("Intr ctxt write failed, err = %d\n", rv); - return xdev->hw.qdma_get_error_code(rv); - } - } - - return 0; -} - -int qdma_intr_context_setup(struct xlnx_dma_dev *xdev) -{ - struct qdma_indirect_intr_ctxt ctxt[QDMA_NUM_DATA_VEC_FOR_INTR_CXT]; - int i = 0; - int rv; - int ring_index; - - if ((xdev->conf.qdma_drv_mode != INDIRECT_INTR_MODE) && - (xdev->conf.qdma_drv_mode != AUTO_MODE)) - return 0; - - memset(ctxt, 0, sizeof(struct qdma_indirect_intr_ctxt) * - QDMA_NUM_DATA_VEC_FOR_INTR_CXT); - /** Preparing the interrupt context for all the vectors - * each vector's context width is QDMA_REG_IND_CTXT_WCNT_3(3) - */ - rv = make_intr_context(xdev, ctxt); - if (rv < 0) - return rv; - - for (i = 0; i < QDMA_NUM_DATA_VEC_FOR_INTR_CXT; i++) { - ring_index = get_intr_ring_index(xdev, - (i + xdev->dvec_start_idx)); - rv = xdev->hw.qdma_indirect_intr_ctx_conf(xdev, ring_index, - NULL, - QDMA_HW_ACCESS_CLEAR); - if (rv < 0) { - pr_err("Intr ctxt clear failed, err = %d\n", rv); - return xdev->hw.qdma_get_error_code(rv); - } - rv = xdev->hw.qdma_indirect_intr_ctx_conf(xdev, - ring_index, &ctxt[i], QDMA_HW_ACCESS_WRITE); - if (rv < 0) { - pr_err("Intr ctxt write failed, err = %d\n", rv); - return xdev->hw.qdma_get_error_code(rv); - } - } - - return 0; -} - -int qdma_descq_context_clear(struct xlnx_dma_dev *xdev, unsigned int qid_hw, - bool st, u8 type, bool clr) -{ - int rv = 0; - - - if (clr) { - - if (type != Q_CMPT) { - rv = xdev->hw.qdma_sw_ctx_conf(xdev, type, qid_hw, - NULL, QDMA_HW_ACCESS_CLEAR); - if (rv < 0) { - pr_err("Fail to clear sw context, rv = %d", rv); - return xdev->hw.qdma_get_error_code(rv); - } - - rv = xdev->hw.qdma_hw_ctx_conf(xdev, type, qid_hw, - NULL, QDMA_HW_ACCESS_CLEAR); - if (rv < 0) { - pr_err("Fail to clear hw context, rv = %d", rv); - return xdev->hw.qdma_get_error_code(rv); - } - - rv = xdev->hw.qdma_credit_ctx_conf(xdev, type, qid_hw, - NULL, QDMA_HW_ACCESS_CLEAR); - if (rv < 0) { - pr_err("Fail to clear credit context, rv = %d", - rv); - return xdev->hw.qdma_get_error_code(rv); - } - - /* Only clear prefetch and writeback contexts - * if this queue is ST C2H - */ - if (st && (type == Q_C2H)) { - rv = xdev->hw.qdma_pfetch_ctx_conf(xdev, qid_hw, - NULL, QDMA_HW_ACCESS_CLEAR); - if (rv < 0) { - pr_err("Fail to clear pfetch context, rv = %d", - rv); - return xdev->hw.qdma_get_error_code(rv); - } - } - } - - /* Only clear cmpt context if this queue is ST C2H or MM cmpt*/ - if ((st && (type == Q_C2H)) || (!st && (type == Q_CMPT))) { - rv = xdev->hw.qdma_cmpt_ctx_conf(xdev, qid_hw, NULL, - QDMA_HW_ACCESS_CLEAR); - if (rv < 0) { - pr_err("Fail to clear cmpt context, rv = %d", - rv); - return xdev->hw.qdma_get_error_code(rv); - } - } - - } else { - if (type != Q_CMPT) { - - rv = xdev->hw.qdma_sw_ctx_conf(xdev, type, qid_hw, - NULL, QDMA_HW_ACCESS_INVALIDATE); - if (rv < 0) { - pr_err("Fail to invalidate sw context, rv = %d", - rv); - return xdev->hw.qdma_get_error_code(rv); - } - - rv = xdev->hw.qdma_hw_ctx_conf(xdev, type, qid_hw, - NULL, QDMA_HW_ACCESS_INVALIDATE); - if (rv < 0) { - pr_err("Fail to invalidate hw context, rv = %d", - rv); - return xdev->hw.qdma_get_error_code(rv); - } - - rv = xdev->hw.qdma_credit_ctx_conf(xdev, type, qid_hw, - NULL, QDMA_HW_ACCESS_INVALIDATE); - if (rv < 0) { - pr_err("Fail to invalidate credit context, rv = %d", - rv); - return xdev->hw.qdma_get_error_code(rv); - } - - /* Only clear prefetch and writeback contexts if this - * queue is ST C2H - */ - if (st && (type == Q_C2H)) { - rv = xdev->hw.qdma_pfetch_ctx_conf(xdev, qid_hw, - NULL, QDMA_HW_ACCESS_INVALIDATE); - if (rv < 0) { - pr_err("Fail to invalidate pfetch context, rv = %d", - rv); - return xdev->hw.qdma_get_error_code(rv); - } - } - } - - /* Only clear cmpt context if this queue is ST C2H MM cmpt*/ - if ((st && (type == Q_C2H)) || (!st && (type == Q_CMPT))) { - rv = xdev->hw.qdma_cmpt_ctx_conf(xdev, qid_hw, - NULL, QDMA_HW_ACCESS_INVALIDATE); - if (rv < 0) { - pr_err("Fail to invalidate cmpt context, rv = %d", - rv); - return xdev->hw.qdma_get_error_code(rv); - } - } - } - - return 0; -} - -int qdma_descq_context_setup(struct qdma_descq *descq) -{ - struct qdma_descq_context context; - - memset(&context, 0, sizeof(context)); - - if (descq->conf.q_type != Q_CMPT) { - - make_sw_context(descq, &context.sw_ctxt); - - if (descq->xdev->dev_cap.qid2vec_ctx) { - if (descq->xdev->conf.qdma_drv_mode != POLL_MODE) - make_qid2vec_context(descq, &context.qid2vec); - } - - if (descq->conf.st && (descq->conf.q_type == Q_C2H)) - make_prefetch_context(descq, &context.pfetch_ctxt); - } - - if ((descq->conf.st && (descq->conf.q_type == Q_C2H)) || - (!descq->conf.st && (descq->conf.q_type == Q_CMPT))) - make_cmpt_context(descq, &context.cmpt_ctxt); - - return qdma_descq_context_program(descq->xdev, descq->qidx_hw, - descq->conf.st, descq->conf.q_type, &context); -} - -int qdma_descq_context_read(struct xlnx_dma_dev *xdev, unsigned int qid_hw, - bool st, u8 type, struct qdma_descq_context *context) -{ - int rv = 0; - - memset(context, 0, sizeof(struct qdma_descq_context)); - - if (type != Q_CMPT) { - rv = xdev->hw.qdma_sw_ctx_conf(xdev, type, qid_hw, - &(context->sw_ctxt), QDMA_HW_ACCESS_READ); - if (rv < 0) { - pr_err("Failed to read sw context, rv = %d", rv); - return xdev->hw.qdma_get_error_code(rv); - } - - rv = xdev->hw.qdma_hw_ctx_conf(xdev, type, qid_hw, - &(context->hw_ctxt), QDMA_HW_ACCESS_READ); - if (rv < 0) { - pr_err("Failed to read hw context, rv = %d", rv); - return xdev->hw.qdma_get_error_code(rv); - } - - rv = xdev->hw.qdma_credit_ctx_conf(xdev, type, qid_hw, - &(context->cr_ctxt), QDMA_HW_ACCESS_READ); - if (rv < 0) { - pr_err("Failed to read hw context, rv = %d", rv); - return xdev->hw.qdma_get_error_code(rv); - } - - rv = xdev->hw.qdma_fmap_conf(xdev, xdev->func_id, - &(context->fmap), QDMA_HW_ACCESS_READ); - if (rv < 0) { - pr_err("Failed to read fmap context, rv = %d", rv); - return xdev->hw.qdma_get_error_code(rv); - } - - if (st && type) { - rv = xdev->hw.qdma_pfetch_ctx_conf(xdev, qid_hw, - &(context->pfetch_ctxt), - QDMA_HW_ACCESS_READ); - if (rv < 0) { - pr_err("Failed to read pftch context, rv = %d", - rv); - return xdev->hw.qdma_get_error_code(rv); - } - } - } - - if ((st && (type == Q_C2H)) || (!st && (type == Q_CMPT))) { - rv = xdev->hw.qdma_cmpt_ctx_conf(xdev, qid_hw, - &(context->cmpt_ctxt), - QDMA_HW_ACCESS_READ); - if (rv < 0) { - pr_err("Failed to read cmpt context, rv = %d", rv); - return xdev->hw.qdma_get_error_code(rv); - } - - } - - return 0; -} - -int qdma_intr_context_read(struct xlnx_dma_dev *xdev, - int ring_index, struct qdma_indirect_intr_ctxt *ctxt) -{ - int rv = 0; - - memset(ctxt, 0, sizeof(struct qdma_indirect_intr_ctxt)); - rv = xdev->hw.qdma_indirect_intr_ctx_conf(xdev, ring_index, ctxt, - QDMA_HW_ACCESS_READ); - if (rv < 0) { - pr_err("Failed to read intr context, rv = %d", rv); - return xdev->hw.qdma_get_error_code(rv); - } - - return 0; -} - -int qdma_descq_context_program(struct xlnx_dma_dev *xdev, unsigned int qid_hw, - bool st, u8 type, struct qdma_descq_context *context) -{ - int rv; - - /* always clear first */ - rv = qdma_descq_context_clear(xdev, qid_hw, st, type, 1); - if (rv < 0) { - pr_err("failed to clear the context, rv= %d", rv); - return xdev->hw.qdma_get_error_code(rv); - } - - if (type != Q_CMPT) { - rv = xdev->hw.qdma_sw_ctx_conf(xdev, type, qid_hw, - &context->sw_ctxt, QDMA_HW_ACCESS_WRITE); - if (rv < 0) { - pr_err("failed to program sw context, rv= %d", rv); - return xdev->hw.qdma_get_error_code(rv); - } - - if (xdev->dev_cap.qid2vec_ctx) { - if (xdev->conf.qdma_drv_mode != POLL_MODE) - xdev->hw.qdma_qid2vec_conf(xdev, type, qid_hw, - &context->qid2vec, - QDMA_HW_ACCESS_WRITE); - } - - if (st && type) { - /* prefetch context */ - rv = xdev->hw.qdma_pfetch_ctx_conf(xdev, qid_hw, - &context->pfetch_ctxt, - QDMA_HW_ACCESS_WRITE); - if (rv < 0) { - pr_err("failed to program pfetch context, rv= %d", - rv); - return xdev->hw.qdma_get_error_code(rv); - } - } - } - - if ((st && (type == Q_C2H)) || (!st && (type == Q_CMPT))) { - /* cmpt context */ - rv = xdev->hw.qdma_cmpt_ctx_conf(xdev, qid_hw, - &context->cmpt_ctxt, - QDMA_HW_ACCESS_WRITE); - if (rv < 0) { - pr_err("failed to program cmpt context, rv= %d", rv); - return xdev->hw.qdma_get_error_code(rv); - } - } - - return 0; -} - -int qdma_descq_context_dump(struct qdma_descq *descq, char *buf, int buflen) -{ - int rv = 0; - int ring_index = -1; - int ring_count = 0; - int len = 0; - struct qdma_indirect_intr_ctxt intr_ctxt; - - rv = descq->xdev->hw.qdma_read_dump_queue_context(descq->xdev, - descq->xdev->func_id, - descq->qidx_hw, - descq->conf.st, descq->conf.q_type, - buf, buflen); - if (rv < 0) { - pr_err("Failed to dump queue context, rv = %d", rv); - return descq->xdev->hw.qdma_get_error_code(rv); - } - len = rv; - - /** if interrupt aggregation is enabled - * add the interrupt context - */ - if ((descq->xdev->conf.qdma_drv_mode == INDIRECT_INTR_MODE) || - (descq->xdev->conf.qdma_drv_mode == AUTO_MODE)) { - for (ring_count = 0; - ring_count < QDMA_NUM_DATA_VEC_FOR_INTR_CXT; - ring_count++) { - ring_index = get_intr_ring_index( - descq->xdev, - (descq->xdev->dvec_start_idx + - ring_count)); - - rv = qdma_intr_context_read(descq->xdev, - ring_index, &intr_ctxt); - if (rv < 0) { - pr_err("Failed to read intr context for ring %d, rv = %d", - ring_index, rv); - return rv; - } - - rv = descq->xdev->hw.qdma_dump_intr_context(descq->xdev, - &intr_ctxt, ring_index, - buf + len, buflen - len); - if (rv < 0) { - pr_err("Failed to dump intr context, rv = %d", - rv); - return descq->xdev->hw.qdma_get_error_code(rv); - } - len += rv; - } - } - - return len; -} - -#endif - - diff --git a/QDMA/linux-kernel/driver/libqdma/qdma_context.h b/QDMA/linux-kernel/driver/libqdma/qdma_context.h deleted file mode 100755 index 9d21d4843..000000000 --- a/QDMA/linux-kernel/driver/libqdma/qdma_context.h +++ /dev/null @@ -1,159 +0,0 @@ -/* - * This file is part of the Xilinx DMA IP Core driver for Linux - * - * Copyright (c) 2017-2022, Xilinx, Inc. All rights reserved. - * Copyright (c) 2022, Advanced Micro Devices, Inc. All rights reserved. - * - * This source code is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * The full GNU General Public License is included in this distribution in - * the file called "COPYING". - */ - -#ifndef __LIBQDMA_CONTEXT_H__ -#define __LIBQDMA_CONTEXT_H__ -/** - * @file - * @brief This file contains the declarations for qdma context handlers - * - */ -#include "xdev.h" -#include "qdma_mbox.h" - -/* - * fetch_max [40:37] - * Description: Maximum number of descriptor fetches outstanding for this queue. - * The max outstanding is fetch_max + 1 . - * Higher value can increase the single queue performance. - */ -#define FETCH_MAX_NUM 7 - -/*****************************************************************************/ -/** - * qdma_intr_context_setup() - handler to set the qdma interrupt context - * - * @param[in] xdev: pointer to xdev - * - * @return 0: success - * @return <0: failure - *****************************************************************************/ -int qdma_intr_context_setup(struct xlnx_dma_dev *xdev); - -/*****************************************************************************/ -/** - * qdma_prog_intr_context() - - * handler to program the qdma interrupt context for - * VF from PF - * - * @param[in] xdev: pointer to xdev - * @param[in] ictxt: interrupt context - * - * @return 0: success - * @return <0: failure - *****************************************************************************/ - -int qdma_prog_intr_context(struct xlnx_dma_dev *xdev, - struct mbox_msg_intr_ctxt *ictxt); - -/*****************************************************************************/ -/** - * qdma_descq_context_setup() - handler to set the qdma sw descriptor context - * - * @param[in] descq: pointer to qdma_descq - * - * @return 0: success - * @return <0: failure - *****************************************************************************/ -int qdma_descq_context_setup(struct qdma_descq *descq); - -/*****************************************************************************/ -/** - * qdma_descq_context_clear() - handler to clear the qdma sw descriptor context - * - * @param[in] xdev: pointer to xdev - * @param[in] qid_hw: hw qidx - * @param[in] st: indicated whether the mm mode or st mode - * @param[in] c2h: indicates whether the h2c or c2h direction - * @param[in] mm_cmpt_en: indicates whether cmpt is enabled for mm or not - * @param[in] clr: flag to indicate whether to clear the context or not - * - * @return 0: success - * @return <0: failure - *****************************************************************************/ -int qdma_descq_context_clear(struct xlnx_dma_dev *xdev, unsigned int qid_hw, - bool st, u8 type, bool clr); - -/*****************************************************************************/ -/** - * qdma_descq_context_read() - handler to read the queue context - * - * @param[in] xdev: pointer to xdev - * @param[in] qid_hw: hw qidx - * @param[in] st: indicated whether the mm mode or st mode - * @param[in] c2h: indicates whether the h2c or c2h direction - * @param[in] mm_cmpt_en: indicates whether cmpt is enabled for mm or not - * @param[out] ctxt: pointer to context data - * - * @return 0: success - * @return <0: failure - *****************************************************************************/ -int qdma_descq_context_read(struct xlnx_dma_dev *xdev, unsigned int qid_hw, - bool st, u8 type, struct qdma_descq_context *context); - -/*****************************************************************************/ -/** - * qdma_descq_context_dump() - handler to dump the queue context - * - * - * @param[in] descq: pointer to qdma_descq - * @param[out] buflen: length of the input buffer - * @param[out] buf: message buffer - * - * @return 0: success - * @return <0: failure - *****************************************************************************/ -int qdma_descq_context_dump(struct qdma_descq *descq, char *buf, int buflen); - -/*****************************************************************************/ -/** - * qdma_intr_context_read() - handler to read the interrupt context - * - * @param[in] xdev: pointer to xdev - * @param[in] ring_index: interrupt ring index - * @param[in] ctxt_sz: context size - * @param[out] context: pointer to interrupt context* - * - * @return 0: success - * @return <0: failure - *****************************************************************************/ -int qdma_intr_context_read(struct xlnx_dma_dev *xdev, - int ring_index, struct qdma_indirect_intr_ctxt *ctxt); - -#ifndef __QDMA_VF__ -/*****************************************************************************/ -/** - * qdma_descq_context_read() - handler to program the context for vf - * - * @param[in] xdev: pointer to xdev - * @param[in] qid_hw: hw qidx - * @param[in] st: indicated whether the mm mode or st mode - * @param[in] c2h: indicates whether the h2c or c2h direction - * @param[in] mm_cmpt_en: indicates whether cmpt is enabled for mm or not* - * @param[out] ctxt: pointer to context data - * - * @return 0: success - * @return <0: failure - *****************************************************************************/ -int qdma_descq_context_program(struct xlnx_dma_dev *xdev, unsigned int qid_hw, - bool st, u8 type, struct qdma_descq_context *context); - -#endif - -#endif /* ifndef __LIBQDMA_CONTEXT_H__ */ diff --git a/QDMA/linux-kernel/driver/libqdma/qdma_debugfs.c b/QDMA/linux-kernel/driver/libqdma/qdma_debugfs.c deleted file mode 100755 index 0c61bad94..000000000 --- a/QDMA/linux-kernel/driver/libqdma/qdma_debugfs.c +++ /dev/null @@ -1,74 +0,0 @@ -/* - * This file is part of the Xilinx DMA IP Core driver for Linux - * - * Copyright (c) 2017-2022, Xilinx, Inc. All rights reserved. - * Copyright (c) 2022, Advanced Micro Devices, Inc. All rights reserved. - * - * This source code is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * The full GNU General Public License is included in this distribution in - * the file called "COPYING". - */ - -#define pr_fmt(fmt) KBUILD_MODNAME ":%s: " fmt, __func__ - -#include "qdma_debugfs.h" - -/*****************************************************************************/ -/** - * qdma_debugfs_init() - function to initialize debugfs - * - * param[in]: qdma_debugfs_root - debugfs root - * - * @return 0: success - * @return <0: error - *****************************************************************************/ -int qdma_debugfs_init(struct dentry **qdma_debugfs_root) -{ - struct dentry *debugfs_root = NULL; - /* create a directory by the name qdma in - * /sys/kernel/debugfs - */ -#ifndef __QDMA_VF__ - debugfs_root = debugfs_create_dir("qdma-pf", NULL); - if (!debugfs_root) - return -ENOENT; - pr_debug("created qdma-pf dir in Linux debug file system\n"); - -#else - debugfs_root = debugfs_create_dir("qdma-vf", NULL); - if (!debugfs_root) - return -ENOENT; - pr_debug("created qdma-vf dir in Linux debug file system\n"); - -#endif - - *qdma_debugfs_root = debugfs_root; - return 0; -} - -/*****************************************************************************/ -/** - * qdma_debugfs_exit() - function to cleanup debugfs - * - * param[in]: qdma_debugfs_root - debugfs root - * - * @return 0: success - * @return <0: error - *****************************************************************************/ -void qdma_debugfs_exit(struct dentry *qdma_debugfs_root) -{ - debugfs_remove_recursive(qdma_debugfs_root); -#ifndef __QDMA_VF__ - pr_debug("removed qdma_pf directory from Linux debug file system\n"); -#else - pr_debug("removed qdma_vf directory from Linux debug file system\n"); -#endif -} diff --git a/QDMA/linux-kernel/driver/libqdma/qdma_debugfs.h b/QDMA/linux-kernel/driver/libqdma/qdma_debugfs.h deleted file mode 100755 index 2b3600a3b..000000000 --- a/QDMA/linux-kernel/driver/libqdma/qdma_debugfs.h +++ /dev/null @@ -1,51 +0,0 @@ -/* - * This file is part of the Xilinx DMA IP Core driver for Linux - * - * Copyright (c) 2017-2022, Xilinx, Inc. All rights reserved. - * Copyright (c) 2022, Advanced Micro Devices, Inc. All rights reserved. - * - * This source code is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * The full GNU General Public License is included in this distribution in - * the file called "COPYING". - */ - -#ifndef __QDMA_DEBUGFS_H__ -#define __QDMA_DEBUGFS_H__ - -#include -#include -#include -#include -#include -#include - -#define DBGFS_DBG_FNAME_SZ (64) -#define QDMA_DEV_NAME_SZ (64) - -/*****************************************************************************/ -/** - * qdma_debugfs_init() - function to initialize debugfs - * - * @return 0: success - * @return <0: error - *****************************************************************************/ -int qdma_debugfs_init(struct dentry **qdma_debugfs_root); - -/*****************************************************************************/ -/** - * qdma_debugfs_exit() - function to cleanup debugfs - * - * @return 0: success - * @return <0: error - *****************************************************************************/ -void qdma_debugfs_exit(struct dentry *qdma_debugfs_root); - -#endif diff --git a/QDMA/linux-kernel/driver/libqdma/qdma_debugfs_dev.c b/QDMA/linux-kernel/driver/libqdma/qdma_debugfs_dev.c deleted file mode 100755 index 3daa36ac0..000000000 --- a/QDMA/linux-kernel/driver/libqdma/qdma_debugfs_dev.c +++ /dev/null @@ -1,1009 +0,0 @@ -/* - * This file is part of the Xilinx DMA IP Core driver for Linux - * - * Copyright (c) 2017-2022, Xilinx, Inc. All rights reserved. - * Copyright (c) 2022, Advanced Micro Devices, Inc. All rights reserved. - * - * This source code is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * The full GNU General Public License is included in this distribution in - * the file called "COPYING". - */ - - -#ifdef DEBUGFS -#define pr_fmt(fmt) KBUILD_MODNAME ":%s: " fmt, __func__ - -#include "qdma_debugfs_dev.h" -#include "qdma_reg_dump.h" -#include "qdma_access_common.h" -#include "qdma_context.h" -#include "libqdma_export.h" -#include "qdma_intr.h" -#include -#include -#include - - -enum dbgfs_dev_dbg_file_type { - DBGFS_DEV_DBGF_INFO = 0, - DBGFS_DEV_DBGF_REGS = 1, - DBGFS_DEV_DBGF_REG_INFO = 2, - DBGFS_DEV_DBGF_END, -}; - -enum dbgfs_dev_intr_file_type { - DBFS_DEV_INTR_CTX = 0, - DBFS_DEV_INTR_ENTRIES = 1, - DBGFS_DEV_INTR_END, -}; - -struct dbgfs_dev_dbgf { - char name[DBGFS_DBG_FNAME_SZ]; - struct file_operations fops; -}; - -struct dbgfs_dev_intr_dbgf { - char name[DBGFS_DBG_FNAME_SZ]; - struct file_operations fops; -}; - -struct dbgfs_dev_priv { - unsigned long dev_hndl; - char dev_name[QDMA_DEV_NAME_SZ]; - char *data; - int datalen; -}; - -enum bar_type { - DEBUGFS_BAR_CONFIG = 0, - DEBUGFS_BAR_USER = 1, - DEBUGFS_BAR_BYPASS = 2, -}; - -/** structure to hold file ops */ -static struct dbgfs_dev_dbgf dbgf[DBGFS_DEV_DBGF_END]; - -/** structure to hold interrupt file ops */ -static struct dbgfs_dev_dbgf dbg_intrf[DBGFS_DEV_INTR_END]; - -/*****************************************************************************/ -/** - * dump_banner() - static helper function to dump a device banner - * - * @param[in] dev_name: qdma device name - * @param[out] buf: buffer to which banner is dumped - * @param[in] buf_sz: size of the buffer passed to func - * - * @return len: length of the buffer printed - *****************************************************************************/ -static int dump_banner(char *dev_name, char *buf, int buf_sz) -{ - int len = 0; - char seperator[81] = {0}; - - memset(seperator, '#', 80); - - /** Banner consumes three lines, so size should be min 240 (80 * 3) - * If changed, check the minimum buffer size required - */ - if (buf_sz < (3 * DEBGFS_LINE_SZ)) - return -1; - - len += snprintf(buf + len, buf_sz - len, "%s\n", seperator); - len += snprintf(buf + len, buf_sz - len, - "###\t\t\t\tqdma%s, reg dump\n", - dev_name); - len += snprintf(buf + len, buf_sz - len, "%s\n", seperator); - - return len; -} - - -#define BANNER_LEN (81 * 5) - -/*****************************************************************************/ -/** - * dbgfs_dump_qdma_regs() - static function to dump qdma device registers - * - * @param[in] xpdev: pointer to qdma pci device structure - * @param[in] buf: buffer to dump the registers - * @param[in] buf_len:size of the buffer passed - * - * @return 0: success - * @return <0: error - *****************************************************************************/ -static int dbgfs_dump_qdma_regs(unsigned long dev_hndl, char *dev_name, - char **data, int *data_len) -{ - int len = 0; - int rv; - char *buf = NULL; - int buflen; - struct xlnx_dma_dev *xdev = (struct xlnx_dma_dev *)dev_hndl; - - if (!xdev) - return -EINVAL; - -#ifndef __QDMA_VF__ - rv = qdma_acc_reg_dump_buf_len((void *)dev_hndl, - xdev->version_info.ip_type, - xdev->version_info.device_type, &buflen); -#else - rv = qdma_acc_reg_dump_buf_len((void *)dev_hndl, - xdev->version_info.ip_type, - xdev->version_info.device_type, &buflen); -#endif - if (rv < 0) { - pr_err("Failed to get reg dump buffer length\n"); - return rv; - } - buflen += BANNER_LEN; - - /** allocate memory */ - buf = (char *) kzalloc(buflen, GFP_KERNEL); - if (!buf) - return -ENOMEM; - - /* print the banner with device info */ - rv = dump_banner(dev_name, buf + len, buflen - len); - if (rv < 0) { - pr_warn("insufficient space to dump register banner, err =%d\n", - rv); - kfree(buf); - return len; - } - len += rv; - - rv = qdma_config_reg_dump(dev_hndl, buf + len, buflen - len); - if (rv < 0) { - pr_warn("Not able to dump Config Bar register values, err = %d\n", - rv); - *data = buf; - *data_len = buflen; - return len; - } - len += rv; - - *data = buf; - *data_len = buflen; - - return len; -} - -/*****************************************************************************/ -/** - * dbgfs_dump_qdma_reg_info() - static function to dump qdma device registers - * - * @param[in] xpdev: pointer to qdma pci device structure - * @param[in] buf: buffer to dump the registers - * @param[in] buf_len:size of the buffer passed - * - * @return 0: success - * @return <0: error - *****************************************************************************/ -static int dbgfs_dump_qdma_reg_info(unsigned long dev_hndl, char *dev_name, - char **data, int *data_len) -{ - int len = 0; - int rv; - char *buf = NULL; - int buflen; - int num_regs; - struct xlnx_dma_dev *xdev = (struct xlnx_dma_dev *)dev_hndl; - - if (!xdev) - return -EINVAL; - - rv = qdma_acc_reg_info_len((void *)dev_hndl, - xdev->version_info.ip_type, - xdev->version_info.device_type, &buflen, &num_regs); - - if (rv < 0) { - pr_err("Failed to get reg dump buffer length\n"); - return rv; - } - buflen += BANNER_LEN; - - /** allocate memory */ - buf = (char *) kzalloc(buflen, GFP_KERNEL); - if (!buf) - return -ENOMEM; - - /* print the banner with device info */ - rv = dump_banner(dev_name, buf + len, buflen - len); - if (rv < 0) { - pr_warn("insufficient space to dump register banner, err =%d\n", - rv); - kfree(buf); - return len; - } - len += rv; - - rv = qdma_config_reg_info_dump(dev_hndl, 0, num_regs, buf + len, - buflen - len); - if (rv < 0) { - pr_warn("Not able to dump Config Bar register values, err = %d\n", - rv); - *data = buf; - *data_len = buflen; - return len; - } - len += rv; - - *data = buf; - *data_len = buflen; - - return len; -} - -/*****************************************************************************/ -/** - * dbgfs_dump_qdma_info() - static function to dump qdma device registers - * - * @xpdev: pointer to qdma pci device structure - * @buf: buffer to dump the registers - * @buf_len:size of the buffer passed - * - * @return 0: success - * @return <0: error - *****************************************************************************/ -static int dbgfs_dump_qdma_info(unsigned long dev_hndl, char *dev_name, - char **data, int *data_len) -{ - int len = 0; - char *buf = NULL; - int buflen = DEBUGFS_DEV_INFO_SZ; - struct xlnx_dma_dev *xdev = (struct xlnx_dma_dev *)dev_hndl; - struct qdma_dev_conf *conf = NULL; - - if (!xdev) - return -EINVAL; - - if (xdev_check_hndl(__func__, xdev->conf.pdev, dev_hndl) < 0) - return -EINVAL; - - conf = &xdev->conf; - - /** allocate memory */ - buf = (char *) kzalloc(buflen, GFP_KERNEL); - if (!buf) - return -ENOMEM; - - len += snprintf(buf + len, buflen - len, "%-36s: %s\n", "Master PF", - (conf->master_pf) ? "True" : "False"); - len += snprintf(buf + len, buflen - len, "%-36s: %d\n", "QBase", - conf->qsets_base); - len += snprintf(buf + len, buflen - len, "%-36s: %u\n", "Max Qsets", - conf->qsets_max); - len += snprintf(buf + len, buflen - len, "%-36s: %d\n", - "Number of VFs", xdev->vf_count); - len += snprintf(buf + len, buflen - len, "%-36s: %d\n", - "Max number of VFs", conf->vf_max); - len += snprintf(buf + len, buflen - len, "%-36s: %s mode\n", - "Driver Mode", - mode_name_list[conf->qdma_drv_mode].name); - - *data = buf; - *data_len = buflen; - - return len; -} - -/*****************************************************************************/ -/** - * dbgfs_dump_intr_cntx() - static function to dump interrupt context - * - * @param[in] xpdev: pointer to qdma pci device structure - * @param[in] buf: buffer to dump the interrupt context - * @param[in] buf_len:size of the buffer passed - * - * @return 0: success - * @return <0: error - *****************************************************************************/ -static int dbgfs_dump_intr_cntx(unsigned long dev_hndl, char *dev_name, - char **data, int *data_len) -{ - - int len = 0; - int rv = 0; - char *buf = NULL; - int i = 0; - int ring_index = 0; - struct qdma_indirect_intr_ctxt intr_ctxt; - struct xlnx_dma_dev *xdev = (struct xlnx_dma_dev *)dev_hndl; - int buflen = DEBUGFS_INTR_CNTX_SZ; - - - /** allocate memory */ - buf = (char *) kzalloc(buflen, GFP_KERNEL); - if (!buf) - return -ENOMEM; - - /** if interrupt aggregation is enabled - * add the interrupt context - */ - if ((xdev->conf.qdma_drv_mode == INDIRECT_INTR_MODE) || - (xdev->conf.qdma_drv_mode == AUTO_MODE)) { - for (i = 0; i < QDMA_NUM_DATA_VEC_FOR_INTR_CXT; i++) { - ring_index = get_intr_ring_index( - xdev, - (i + xdev->dvec_start_idx)); - rv = qdma_intr_context_read( - xdev, - ring_index, - &intr_ctxt); - if (rv < 0) { - len += snprintf(buf + len, buflen - len, - "%s read intr context failed %d.\n", - xdev->conf.name, rv); - *data = buf; - *data_len = buflen; - return rv; - } - - rv = xdev->hw.qdma_dump_intr_context(xdev, - &intr_ctxt, ring_index, - buf + len, buflen - len); - if (rv < 0) { - pr_err("Failed to dump intr context, rv = %d", - rv); - return xdev->hw.qdma_get_error_code(rv); - } - len += rv; - } - } - - *data = buf; - *data_len = buflen; - - return len; -} - -/*****************************************************************************/ -/** - * dbgfs_dump_intr_ring() - static function to dump interrupt ring - * - * @param[in] xpdev: pointer to qdma pci device structure - * @param[in] buf: buffer to dump the interrupt ring - * @param[in] buf_len:size of the buffer passed - * - * @return 0: success - * @return <0: error - *****************************************************************************/ -static int dbgfs_dump_intr_ring(unsigned long dev_hndl, char *dev_name, - char **data, int *data_len) -{ - int len = 0; - int rv = 0; - char *buf = NULL; - struct xlnx_dma_dev *xdev = (struct xlnx_dma_dev *)dev_hndl; - - unsigned int vector_idx = xdev->msix[xdev->dvec_start_idx].entry; - int num_entries = (xdev->conf.intr_rngsz + 1) * 512; - int buflen = (45 * num_entries) + 1; - - - /** allocate memory */ - buf = (char *) kzalloc(buflen, GFP_KERNEL); - if (!buf) - return -ENOMEM; - - rv = qdma_intr_ring_dump(dev_hndl, vector_idx, 0, - num_entries - 1, buf, buflen); - if (rv < 0) { - len += snprintf(buf + len, buflen - len, - "%s read intr context failed %d.\n", - xdev->conf.name, rv); - kfree(buf); - return rv; - } - - len = strlen(buf); - buf[len++] = '\n'; - *data = buf; - *data_len = buflen; - - return len; -} -/*****************************************************************************/ -/** - * dev_dbg_file_open() - static function that provides generic open - * - * @param[in] inode: pointer to file inode - * @param[in] fp: pointer to file structure - * - * @return 0: success - * @return <0: error - *****************************************************************************/ -static int dev_dbg_file_open(struct inode *inode, struct file *fp) -{ - unsigned long dev_id = -1; - int rv = 0; - unsigned char dev_name[QDMA_DEV_NAME_SZ] = {0}; - unsigned char *lptr = NULL, *rptr = NULL; - struct dentry *dev_dir = NULL; - struct dbgfs_dev_priv *priv = NULL; - struct xlnx_dma_dev *xdev = NULL; - - if (!inode || !fp) - return -EINVAL; - dev_dir = fp->f_path.dentry->d_parent; - xdev = inode->i_private; - if (!xdev) - return -EINVAL; - - /* convert colon sepearted b:d:f to hex */ - rptr = dev_dir->d_iname; - lptr = dev_name; - while (*rptr) { - if (*rptr == ':') { - rptr++; - continue; - } - *lptr++ = *rptr++; - } - - /* convert this string as hex integer */ - rv = kstrtoul((const char *)dev_name, 16, &dev_id); - if (rv < 0) { - rv = -ENODEV; - return rv; - } - - - priv = (struct dbgfs_dev_priv *) kzalloc(sizeof(struct dbgfs_dev_priv), - GFP_KERNEL); - if (!priv) { - rv = -ENOMEM; - return rv; - } - - priv->dev_hndl = (unsigned long)xdev; - snprintf(priv->dev_name, QDMA_DEV_NAME_SZ, "%s", dev_name); - fp->private_data = priv; - - return 0; -} - -/*****************************************************************************/ -/** - * dev_dbg_file_release() - static function that provides generic release - * - * @param[in] inode: pointer to file inode - * @param[in] fp: pointer to file structure - * - * @return 0: success - * @return <0: error - *****************************************************************************/ -static int dev_dbg_file_release(struct inode *inode, struct file *fp) -{ - kfree(fp->private_data); - - fp->private_data = NULL; - - return 0; -} - -/*****************************************************************************/ -/** - * dev_dbg_file_read() - static function that provides common read - * - * @param[in] fp: pointer to file structure - * @param[out] user_buffer: pointer to user buffer - * @param[in] count: size of data to read - * @param[in/out] ppos: pointer to offset read - * @param[in] type: information type - * - * @return >0: size read - * @return <0: error - *****************************************************************************/ -static ssize_t dev_dbg_file_read(struct file *fp, char __user *user_buffer, - size_t count, loff_t *ppos, enum dbgfs_dev_dbg_file_type type) -{ - char *buf = NULL; - int buf_len = 0; - int len = 0; - int rv = 0; - struct dbgfs_dev_priv *dev_priv = - (struct dbgfs_dev_priv *)fp->private_data; - - if (dev_priv->data == NULL && dev_priv->datalen == 0) { - if (type == DBGFS_DEV_DBGF_INFO) { - rv = dbgfs_dump_qdma_info(dev_priv->dev_hndl, - dev_priv->dev_name, &buf, &buf_len); - } else if (type == DBGFS_DEV_DBGF_REGS) { - rv = dbgfs_dump_qdma_regs(dev_priv->dev_hndl, - dev_priv->dev_name, &buf, &buf_len); - } else if (type == DBGFS_DEV_DBGF_REG_INFO) { - rv = dbgfs_dump_qdma_reg_info(dev_priv->dev_hndl, - dev_priv->dev_name, &buf, &buf_len); - } - - if (rv < 0) - goto dev_dbg_file_read_exit; - - dev_priv->datalen = rv; - dev_priv->data = buf; - } - - buf = dev_priv->data; - len = dev_priv->datalen; - - if (!buf) - goto dev_dbg_file_read_exit; - - /** write to user buffer */ - if (*ppos >= len) { - rv = 0; - goto dev_dbg_file_read_exit; - } - - if (*ppos + count > len) - count = len - *ppos; - - if (copy_to_user(user_buffer, buf + *ppos, count)) { - rv = -EFAULT; - goto dev_dbg_file_read_exit; - } - - *ppos += count; - rv = count; - - pr_debug("number of bytes written to user space is %zu\n", count); - -dev_dbg_file_read_exit: - kfree(buf); - dev_priv->data = NULL; - dev_priv->datalen = 0; - return rv; -} - -/*****************************************************************************/ -/** - * dev_intr_file_read() - static function that provides common read - * - * @param[in] fp: pointer to file structure - * @param[out] user_buffer: pointer to user buffer - * @param[in] count: size of data to read - * @param[in/out] ppos: pointer to offset read - * @param[in] type: information type - * - * @return >0: size read - * @return <0: error - *****************************************************************************/ -static ssize_t dev_intr_file_read(struct file *fp, char __user *user_buffer, - size_t count, loff_t *ppos, enum dbgfs_dev_intr_file_type type) -{ - char *buf = NULL; - int buf_len = 0; - int len = 0; - int rv = 0; - struct dbgfs_dev_priv *dev_priv = - (struct dbgfs_dev_priv *)fp->private_data; - - if (dev_priv->data == NULL && dev_priv->datalen == 0) { - if (type == DBFS_DEV_INTR_CTX) { - rv = dbgfs_dump_intr_cntx(dev_priv->dev_hndl, - dev_priv->dev_name, &buf, &buf_len); - } else if (type == DBFS_DEV_INTR_ENTRIES) { - rv = dbgfs_dump_intr_ring(dev_priv->dev_hndl, - dev_priv->dev_name, &buf, &buf_len); - } - - if (rv < 0) - goto dev_intr_file_read_exit; - - dev_priv->datalen = rv; - dev_priv->data = buf; - } - - buf = dev_priv->data; - len = dev_priv->datalen; - - if (!buf) - goto dev_intr_file_read_exit; - - /** write to user buffer */ - if (*ppos >= len) { - rv = 0; - goto dev_intr_file_read_exit; - } - - if (*ppos + count > len) - count = len - *ppos; - - if (copy_to_user(user_buffer, buf + *ppos, count)) { - rv = -EFAULT; - goto dev_intr_file_read_exit; - } - - *ppos += count; - rv = count; - - pr_debug("nuber of bytes written to user space is %zu\n", count); - -dev_intr_file_read_exit: - kfree(buf); - dev_priv->data = NULL; - dev_priv->datalen = 0; - return rv; -} - -/*****************************************************************************/ -/** - * dev_info_open() - static function that executes info open - * - * @param[in] inode: pointer to file inode - * @param[in] fp: pointer to file structure - * - * @return 0: success - * @return <0: error - *****************************************************************************/ -static int dev_info_open(struct inode *inode, struct file *fp) -{ - return dev_dbg_file_open(inode, fp); -} - -/*****************************************************************************/ -/** - * dev_info_read() - static function that executes info read - * - * @param[in] fp: pointer to file structure - * @param[out] user_buffer: pointer to user buffer - * @param[in] count: size of data to read - * @param[in/out] ppos: pointer to offset read - * - * @return >0: size read - * @return <0: error - *****************************************************************************/ -static ssize_t dev_info_read(struct file *fp, char __user *user_buffer, - size_t count, loff_t *ppos) -{ - return dev_dbg_file_read(fp, user_buffer, count, ppos, - DBGFS_DEV_DBGF_INFO); -} - -/*****************************************************************************/ -/** - * dev_regs_open() - static function that opens regs debug file - * - * @param[in] inode: pointer to file inode - * @param[in] fp: pointer to file structure - * - * @return 0: success - * @return <0: error - *****************************************************************************/ -static int dev_regs_open(struct inode *inode, struct file *fp) -{ - return dev_dbg_file_open(inode, fp); -} - -/*****************************************************************************/ -/** - * dev_reg_info_open() - static function that opens regInfo debug file - * - * @param[in] inode: pointer to file inode - * @param[in] fp: pointer to file structure - * - * @return 0: success - * @return <0: error - *****************************************************************************/ -static int dev_reg_info_open(struct inode *inode, struct file *fp) -{ - return dev_dbg_file_open(inode, fp); -} - -/*****************************************************************************/ -/** - * dev_regs_read() - static function that executes info read - * - * @param[in] fp: pointer to file structure - * @param[out] user_buffer: pointer to user buffer - * @param[in] count: size of data to read - * @param[in/out] ppos: pointer to offset read - * - * @return >0: size read - * @return <0: error - *****************************************************************************/ -static ssize_t dev_regs_read(struct file *fp, char __user *user_buffer, - size_t count, loff_t *ppos) -{ - return dev_dbg_file_read(fp, user_buffer, count, ppos, - DBGFS_DEV_DBGF_REGS); -} - -/*****************************************************************************/ -/** - * dev_reg_info_read() - static function that executes info read - * - * @param[in] fp: pointer to file structure - * @param[out] user_buffer: pointer to user buffer - * @param[in] count: size of data to read - * @param[in/out] ppos: pointer to offset read - * - * @return >0: size read - * @return <0: error - *****************************************************************************/ -static ssize_t dev_reg_info_read(struct file *fp, char __user *user_buffer, - size_t count, loff_t *ppos) -{ - return dev_dbg_file_read(fp, user_buffer, count, ppos, - DBGFS_DEV_DBGF_REG_INFO); -} -/*****************************************************************************/ -/** - * dev_intr_cntx_open() -static function to open interrupt context debug file - * - * @param[in] inode: pointer to file inode - * @param[in] fp: pointer to file structure - * - * @return 0: success - * @return <0: error - *****************************************************************************/ -static int dev_intr_cntx_open(struct inode *inode, struct file *fp) -{ - return dev_dbg_file_open(inode, fp); -} - -/*****************************************************************************/ -/** - * dev_intr_cntx_read() - static function that executes interrupt context read - * file - * - * @param[in] fp: pointer to file structure - * @param[out] user_buffer: pointer to user buffer - * @param[in] count: size of data to read - * @param[in/out] ppos: pointer to offset read - * - * @return >0: size read - * @return <0: error - *****************************************************************************/ -static ssize_t dev_intr_cntx_read(struct file *fp, char __user *user_buffer, - size_t count, loff_t *ppos) -{ - return dev_intr_file_read(fp, user_buffer, count, ppos, - DBFS_DEV_INTR_CTX); -} - -/*****************************************************************************/ -/** - * dev_intr_ring_open() -static function to open interrupt ring entries file - * - * @param[in] inode: pointer to file inode - * @param[in] fp: pointer to file structure - * - * @return 0: success - * @return <0: error - *****************************************************************************/ -static int dev_intr_ring_open(struct inode *inode, struct file *fp) -{ - return dev_dbg_file_open(inode, fp); -} -/*****************************************************************************/ -/** - * dev_intr_ring_read() - static function that reads interrupt ring entries to - * file - * - * @param[in] fp: pointer to file structure - * @param[out] user_buffer: pointer to user buffer - * @param[in] count: size of data to read - * @param[in/out] ppos: pointer to offset read - * - * @return >0: size read - * @return <0: error - *****************************************************************************/ -static ssize_t dev_intr_ring_read(struct file *fp, char __user *user_buffer, - size_t count, loff_t *ppos) -{ - return dev_intr_file_read(fp, user_buffer, count, ppos, - DBFS_DEV_INTR_ENTRIES); -} -/*****************************************************************************/ -/** - * create_dev_dbg_files() - static function to create queue debug files - * - * @param[in] dev_root: debugfs root for the device - * - * @return >0: size read - * @return <0: error - *****************************************************************************/ -static int create_dev_dbg_files(struct xlnx_dma_dev *xdev, - struct dentry *dev_root) -{ - struct dentry *fp[DBGFS_DEV_DBGF_END] = { NULL }; - struct file_operations *fops = NULL; - int i = 0; - - memset(dbgf, 0, sizeof(struct dbgfs_dev_dbgf) * DBGFS_DEV_DBGF_END); - - for (i = 0; i < DBGFS_DEV_DBGF_END; i++) { - fops = &dbgf[i].fops; - fops->owner = THIS_MODULE; - switch (i) { - case DBGFS_DEV_DBGF_INFO: - snprintf(dbgf[i].name, 64, "%s", "qdma_info"); - fops->open = dev_info_open; - fops->read = dev_info_read; - fops->release = dev_dbg_file_release; - break; - case DBGFS_DEV_DBGF_REGS: - snprintf(dbgf[i].name, 64, "%s", "qdma_regs"); - fops->open = dev_regs_open; - fops->read = dev_regs_read; - fops->release = dev_dbg_file_release; - break; - case DBGFS_DEV_DBGF_REG_INFO: - snprintf(dbgf[i].name, 64, "%s", "qdma_reg_info"); - fops->open = dev_reg_info_open; - fops->read = dev_reg_info_read; - fops->release = dev_dbg_file_release; - break; - } - } - - for (i = 0; i < DBGFS_DEV_DBGF_END; i++) { - fp[i] = debugfs_create_file(dbgf[i].name, 0644, dev_root, - xdev, &dbgf[i].fops); - if (!fp[i]) - return -1; - } - return 0; -} - -/*****************************************************************************/ -/** - * create_dev_intr_files() - static function to create intr ring files - * - * @param[in] dev_root: debugfs root for the device - * - * @return >0: size read - * @return <0: error - *****************************************************************************/ -static int create_dev_intr_files(struct xlnx_dma_dev *xdev, - struct dentry *intr_root) -{ - struct dentry *fp[DBGFS_DEV_DBGF_END] = { NULL }; - struct file_operations *fops = NULL; - int i = 0; - char intr_dir[16] = {0}; - struct dentry *dbgfs_intr_ring = NULL; - - snprintf(intr_dir, 8, "%d", - get_intr_ring_index(xdev, - xdev->dvec_start_idx)); - - dbgfs_intr_ring = debugfs_create_dir(intr_dir, intr_root); - memset(dbg_intrf, 0, sizeof( - struct dbgfs_dev_intr_dbgf) * DBGFS_DEV_INTR_END); - - for (i = 0; i < DBGFS_DEV_INTR_END; i++) { - fops = &dbg_intrf[i].fops; - fops->owner = THIS_MODULE; - switch (i) { - case DBFS_DEV_INTR_CTX: - snprintf(dbg_intrf[i].name, 64, "%s", "cntxt"); - fops->open = dev_intr_cntx_open; - fops->read = dev_intr_cntx_read; - fops->release = dev_dbg_file_release; - break; - case DBFS_DEV_INTR_ENTRIES: - snprintf(dbg_intrf[i].name, 64, "%s", "entries"); - fops->open = dev_intr_ring_open; - fops->read = dev_intr_ring_read; - fops->release = dev_dbg_file_release; - break; - } - } - - for (i = 0; i < DBGFS_DEV_INTR_END; i++) { - fp[i] = debugfs_create_file(dbg_intrf[i].name, 0644, - dbgfs_intr_ring, - xdev, &dbg_intrf[i].fops); - if (!fp[i]) - return -1; - } - return 0; -} - -/*****************************************************************************/ -/** - * dbgfs_dev_init() - function to initialize device debugfs files - * - * @param[in] xdev: Xilinx dma device - * @param[in] qdma_debugfs_root: root file in debugfs - * - * @return =0: success - * @return <0: error - *****************************************************************************/ -int dbgfs_dev_init(struct xlnx_dma_dev *xdev) -{ - char dname[QDMA_DEV_NAME_SZ] = {0}; - struct dentry *dbgfs_dev_root = NULL; - struct dentry *dbgfs_queues_root = NULL; - struct dentry *dbgfs_intr_root = NULL; - struct pci_dev *pdev = xdev->conf.pdev; - int rv = 0; - - if (!xdev->conf.debugfs_dev_root) { - snprintf(dname, QDMA_DEV_NAME_SZ, "%04x:%02x:%02x:%x", - pci_domain_nr(pdev->bus), - pdev->bus->number, - PCI_SLOT(pdev->devfn), - PCI_FUNC(pdev->devfn)); - /* create a directory for the device in debugfs */ - dbgfs_dev_root = debugfs_create_dir(dname, qdma_debugfs_root); - if (!dbgfs_dev_root) { - pr_err("Failed to create device direcotry\n"); - return -1; - } - xdev->dbgfs_dev_root = dbgfs_dev_root; - } else - xdev->dbgfs_dev_root = xdev->conf.debugfs_dev_root; - - /* create debug files for qdma device */ - rv = create_dev_dbg_files(xdev, xdev->dbgfs_dev_root); - if (rv < 0) { - pr_err("Failed to create device debug files\n"); - goto dbgfs_dev_init_fail; - } - - /* create a directory for the queues in debugfs */ - dbgfs_queues_root = debugfs_create_dir("queues", xdev->dbgfs_dev_root); - if (!dbgfs_queues_root) { - pr_err("Failed to create queues directory under device directory\n"); - goto dbgfs_dev_init_fail; - } - if ((xdev->conf.qdma_drv_mode == INDIRECT_INTR_MODE) || - (xdev->conf.qdma_drv_mode == AUTO_MODE)) { - /* create a directory for the intr in debugfs */ - dbgfs_intr_root = debugfs_create_dir("intr_rings", - xdev->dbgfs_dev_root); - if (!dbgfs_queues_root) { - pr_err("Failed to create intr_ring directory under device directory\n"); - goto dbgfs_dev_init_fail; - } - - /* create debug files for intr */ - rv = create_dev_intr_files(xdev, dbgfs_intr_root); - if (rv < 0) { - pr_err("Failed to create intr ring files\n"); - goto dbgfs_dev_init_fail; - } - } - xdev->dbgfs_queues_root = dbgfs_queues_root; - xdev->dbgfs_intr_root = dbgfs_intr_root; - spin_lock_init(&xdev->qidx_lock); - - return 0; - -dbgfs_dev_init_fail: - - debugfs_remove_recursive(xdev->dbgfs_dev_root); - return -1; -} - -/*****************************************************************************/ -/** - * dbgfs_dev_exit() - function to cleanup device debugfs files - * - * @param[in] xdev: Xilinx dma device - * - *****************************************************************************/ -void dbgfs_dev_exit(struct xlnx_dma_dev *xdev) -{ - if (!xdev->conf.debugfs_dev_root) - debugfs_remove_recursive(xdev->dbgfs_dev_root); - xdev->dbgfs_dev_root = NULL; - xdev->dbgfs_queues_root = NULL; - xdev->dbgfs_intr_root = NULL; -} - -#endif diff --git a/QDMA/linux-kernel/driver/libqdma/qdma_debugfs_dev.h b/QDMA/linux-kernel/driver/libqdma/qdma_debugfs_dev.h deleted file mode 100755 index 5a74c7919..000000000 --- a/QDMA/linux-kernel/driver/libqdma/qdma_debugfs_dev.h +++ /dev/null @@ -1,29 +0,0 @@ -/* - * This file is part of the Xilinx DMA IP Core driver for Linux - * - * Copyright (c) 2017-2022, Xilinx, Inc. All rights reserved. - * Copyright (c) 2022, Advanced Micro Devices, Inc. All rights reserved. - * - * This source code is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * The full GNU General Public License is included in this distribution in - * the file called "COPYING". - */ - -#ifndef __QDMA_DEBUGFS_DEV_H__ -#define __QDMA_DEBUGFS_DEV_H__ - -#include "qdma_debugfs.h" -#include "xdev.h" - -int dbgfs_dev_init(struct xlnx_dma_dev *xdev); -void dbgfs_dev_exit(struct xlnx_dma_dev *xdev); - -#endif diff --git a/QDMA/linux-kernel/driver/libqdma/qdma_debugfs_queue.c b/QDMA/linux-kernel/driver/libqdma/qdma_debugfs_queue.c deleted file mode 100755 index c323c4756..000000000 --- a/QDMA/linux-kernel/driver/libqdma/qdma_debugfs_queue.c +++ /dev/null @@ -1,964 +0,0 @@ -/* - * This file is part of the Xilinx DMA IP Core driver for Linux - * - * Copyright (c) 2017-2022, Xilinx, Inc. All rights reserved. - * Copyright (c) 2022, Advanced Micro Devices, Inc. All rights reserved. - * - * This source code is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * The full GNU General Public License is included in this distribution in - * the file called "COPYING". - */ - -#define pr_fmt(fmt) KBUILD_MODNAME ":%s: " fmt, __func__ - -#include "qdma_debugfs_queue.h" -#include "libqdma_export.h" -#include "qdma_regs.h" -#include "qdma_context.h" -#include "qdma_descq.h" -#include "qdma_regs.h" -#include - -#ifdef DEBUGFS -#define DEBUGFS_QUEUE_DESC_SZ (100) -#define DEBUGFS_QUEUE_INFO_SZ (256) -#define DEBUGFS_QUEUE_CTXT_SZ (24 * 1024) - -#define DEBUGFS_CTXT_ELEM(reg, pos, size) \ - ((reg >> pos) & ~(~0 << size)) - -#define DBGFS_QUEUE_INFO_SZ 256 -#define DBGFS_ERR_BUFLEN (64) - -enum dbgfs_queue_info_type { - DBGFS_QINFO_INFO = 0, - DBGFS_QINFO_CNTXT = 1, - DBGFS_QINFO_DESC = 2, - DBGFS_QINFO_END, -}; - -enum dbgfs_cntxt_word { - DBGFS_CNTXT_W0 = 0, - DBGFS_CNTXT_W1 = 1, - DBGFS_CNTXT_W2 = 2, - DBGFS_CNTXT_W3 = 3, - DBGFS_CNTXT_W4 = 4, - DBGFS_CNTXT_W5 = 5, - DBGFS_CNTXT_W6 = 6, - DBGFS_CNTXT_W7 = 7, -}; - -enum dbgfs_cmpt_queue_info_type { - DBGFS_CMPT_QINFO_INFO = 0, - DBGFS_CMPT_QINFO_CNTXT = 1, - DBGFS_CMPT_QINFO_DESC = 2, - DBGFS_CMPT_QINFO_END, -}; - -struct dbgfs_q_dbgf { - char name[DBGFS_DBG_FNAME_SZ]; - struct file_operations fops; -}; - -struct dbgfs_q_priv { - unsigned long dev_hndl; - unsigned long qhndl; - char *data; - int datalen; -}; - -enum dbgfs_desc_type { - DBGFS_DESC_TYPE_C2H = 0, - DBGFS_DESC_TYPE_H2C = DBGFS_DESC_TYPE_C2H, - DBGFS_DESC_TYPE_CMPT = 1, - DBGFS_DESC_TYPE_END = 2, -}; - -/** structure to hold file ops */ -static struct dbgfs_q_dbgf qf[DBGFS_QINFO_END]; - -/** structure to hold file ops */ -static struct dbgfs_q_dbgf cmpt_qf[DBGFS_CMPT_QINFO_END]; -static int q_dbg_file_open(struct inode *inode, struct file *fp); -static int q_dbg_file_release(struct inode *inode, struct file *fp); -static int qdbg_info_read(unsigned long dev_hndl, unsigned long id, char **data, - int *data_len, enum dbgfs_desc_type type); -static int qdbg_desc_read(unsigned long dev_hndl, unsigned long id, char **data, - int *data_len, enum dbgfs_desc_type type); -static int qdbg_cntxt_read(unsigned long dev_hndl, unsigned long id, - char **data, int *data_len, enum dbgfs_desc_type type); - -/*****************************************************************************/ -/** - * cmpt_q_dbg_file_open() - static function that provides generic open - * - * @param[in] inode: pointer to file inode - * @param[in] fp: pointer to file structure - * - * @return 0: success - * @return <0: error - *****************************************************************************/ -static int cmpt_q_dbg_file_open(struct inode *inode, struct file *fp) -{ - return q_dbg_file_open(inode, fp); -} - -/*****************************************************************************/ -/** - * cmpt_q_dbg_file_release() - static function that provides generic release - * - * @param[in] inode: pointer to file inode - * @param[in] fp: pointer to file structure - * - * @return 0: success - * @return <0: error - *****************************************************************************/ -static int cmpt_q_dbg_file_release(struct inode *inode, struct file *fp) -{ - return q_dbg_file_release(inode, fp); -} - -/*****************************************************************************/ -/** - * cmpt_q_dbg_file_read() - static function that provides common read - * - * @param[in] fp: pointer to file structure - * @param[out] user_buffer: pointer to user buffer - * @param[in] count: size of data to read - * @param[in/out] ppos: pointer to offset read - * @param[in] type: information type - * - * @return >0: size read - * @return <0: error - *****************************************************************************/ -static ssize_t cmpt_q_dbg_file_read(struct file *fp, - char __user *user_buffer, - size_t count, loff_t *ppos, - enum dbgfs_queue_info_type type) -{ - char *buf = NULL; - int buf_len = 0; - int len = 0; - int rv = 0; - struct dbgfs_q_priv *qpriv = - (struct dbgfs_q_priv *)fp->private_data; - - if (qpriv->data == NULL && qpriv->datalen == 0) { - if (type == DBGFS_QINFO_INFO) { - rv = qdbg_info_read(qpriv->dev_hndl, qpriv->qhndl, - &buf, &buf_len, DBGFS_DESC_TYPE_CMPT); - } else if (type == DBGFS_QINFO_CNTXT) { - rv = qdbg_cntxt_read(qpriv->dev_hndl, qpriv->qhndl, - &buf, &buf_len, DBGFS_DESC_TYPE_CMPT); - } else if (type == DBGFS_QINFO_DESC) { - rv = qdbg_desc_read(qpriv->dev_hndl, qpriv->qhndl, - &buf, &buf_len, DBGFS_DESC_TYPE_CMPT); - } - - if (rv < 0) - goto cmpt_q_dbg_file_read_exit; - - qpriv->datalen = rv; - qpriv->data = buf; - } - - buf = qpriv->data; - len = qpriv->datalen; - - if (!buf) - goto cmpt_q_dbg_file_read_exit; - - /** write to user buffer */ - if (*ppos >= len) { - rv = 0; - goto cmpt_q_dbg_file_read_exit; - } - - if (*ppos + count > len) - count = len - *ppos; - - if (copy_to_user(user_buffer, buf + *ppos, count)) { - rv = -EFAULT; - goto cmpt_q_dbg_file_read_exit; - } - - *ppos += count; - - pr_debug("cmpt q read size %zu\n", count); - - return count; - -cmpt_q_dbg_file_read_exit: - kfree(buf); - qpriv->data = NULL; - qpriv->datalen = 0; - return rv; -} - -/*****************************************************************************/ -/** - * cmpt_q_info_open() - static function that executes info open - * - * @param[in] inode: pointer to file inode - * @param[in] fp: pointer to file structure - * - * @return 0: success - * @return <0: error - *****************************************************************************/ -static int cmpt_q_info_open(struct inode *inode, struct file *fp) -{ - return cmpt_q_dbg_file_open(inode, fp); -} - -/*****************************************************************************/ -/** - * cmpt_q_info_read() - static function that executes info read - * - * @param[in] fp: pointer to file structure - * @param[out] user_buffer: pointer to user buffer - * @param[in] count: size of data to read - * @param[in/out] ppos: pointer to offset read - * - * @return >0: size read - * @return <0: error - *****************************************************************************/ -static ssize_t cmpt_q_info_read(struct file *fp, char __user *user_buffer, - size_t count, loff_t *ppos) -{ - return cmpt_q_dbg_file_read(fp, user_buffer, count, ppos, - DBGFS_QINFO_INFO); -} - -/*****************************************************************************/ -/** - * cmpt_q_cntxt_open() - static function that executes info open - * - * @param[in] inode: pointer to file inode - * @param[in] fp: pointer to file structure - * - * @return 0: success - * @return <0: error - *****************************************************************************/ -static int cmpt_q_cntxt_open(struct inode *inode, struct file *fp) -{ - return cmpt_q_dbg_file_open(inode, fp); -} - -/*****************************************************************************/ -/** - * cmpt_q_cntxt_read() - static function that executes info read - * - * @param[in] fp: pointer to file structure - * @param[out] user_buffer: pointer to user buffer - * @param[in] count: size of data to read - * @param[in/out] ppos: pointer to offset read - * - * @return >0: size read - * @return <0: error - *****************************************************************************/ -static ssize_t cmpt_q_cntxt_read(struct file *fp, char __user *user_buffer, - size_t count, loff_t *ppos) -{ - return cmpt_q_dbg_file_read(fp, user_buffer, count, ppos, - DBGFS_QINFO_CNTXT); -} - -/*****************************************************************************/ -/** - * cmpt_q_desc_open() - static function that executes descriptor open - * - * @param[in] inode: pointer to file inode - * @param[in] fp: pointer to file structure - * - * @return 0: success - * @return <0: error - *****************************************************************************/ -static int cmpt_q_desc_open(struct inode *inode, struct file *fp) -{ - return cmpt_q_dbg_file_open(inode, fp); -} - -/*****************************************************************************/ -/** - * cmpt_q_desc_read() - static function that executes descriptor read - * - * @param[in] fp: pointer to file structure - * @param[out] user_buffer: pointer to user buffer - * @param[in] count: size of data to read - * @param[in/out] ppos: pointer to offset read - * - * @return >0: size read - * @return <0: error - *****************************************************************************/ -static ssize_t cmpt_q_desc_read(struct file *fp, char __user *user_buffer, - size_t count, loff_t *ppos) -{ - return cmpt_q_dbg_file_read(fp, user_buffer, count, ppos, - DBGFS_QINFO_DESC); -} - -/*****************************************************************************/ -/** - * create_cmpt_q_dbg_files() - static function to create cmpt queue dbg files - * - * @param[in] queue_root: debugfs root for a queue - * - * @return >0: size read - * @return <0: error - *****************************************************************************/ -static int create_cmpt_q_dbg_files(struct qdma_descq *descq, - struct dentry *queue_root) -{ - struct dentry *fp[DBGFS_QINFO_END] = { NULL }; - struct file_operations *fops = NULL; - int i = 0; - - memset(cmpt_qf, 0, sizeof(struct dbgfs_q_dbgf) * DBGFS_CMPT_QINFO_END); - - for (i = 0; i < DBGFS_CMPT_QINFO_END; i++) { - fops = &cmpt_qf[i].fops; - fops->owner = THIS_MODULE; - switch (i) { - case DBGFS_CMPT_QINFO_INFO: - snprintf(cmpt_qf[i].name, DBGFS_DBG_FNAME_SZ, - "%s", "info"); - fops->open = cmpt_q_info_open; - fops->read = cmpt_q_info_read; - fops->release = cmpt_q_dbg_file_release; - break; - case DBGFS_CMPT_QINFO_CNTXT: - snprintf(cmpt_qf[i].name, DBGFS_DBG_FNAME_SZ, - "%s", "cntxt"); - fops->open = cmpt_q_cntxt_open; - fops->read = cmpt_q_cntxt_read; - fops->release = cmpt_q_dbg_file_release; - break; - case DBGFS_CMPT_QINFO_DESC: - snprintf(cmpt_qf[i].name, DBGFS_DBG_FNAME_SZ, - "%s", "desc"); - fops->open = cmpt_q_desc_open; - fops->read = cmpt_q_desc_read; - fops->release = cmpt_q_dbg_file_release; - break; - } - } - - for (i = 0; i < DBGFS_CMPT_QINFO_END; i++) { - fp[i] = debugfs_create_file(cmpt_qf[i].name, 0644, queue_root, - descq, &cmpt_qf[i].fops); - if (!fp[i]) - return -1; - } - return 0; -} - -/*****************************************************************************/ -/** - * q_dbg_file_open() - generic queue debug file open - * - * @param[in] inode: pointer to file inode - * @param[in] fp: pointer to file structure - * - * @return 0: success - * @return <0: error - *****************************************************************************/ -static int q_dbg_file_open(struct inode *inode, struct file *fp) -{ - unsigned long dev_id = -1; - int qidx = -1; - struct dbgfs_q_priv *priv = NULL; - int rv = 0; - unsigned char dev_name[QDMA_DEV_NAME_SZ] = {0}; - unsigned char *lptr = NULL, *rptr = NULL; - struct dentry *direction_dir = NULL; - struct dentry *qid_dir = NULL; - struct dentry *qroot_dir = NULL; - struct dentry *dev_dir = NULL; - struct qdma_descq *descq = NULL; - - if (!inode || !fp) - return -EINVAL; - descq = inode->i_private; - if (!descq) - return -EINVAL; - - direction_dir = fp->f_path.dentry->d_parent; - qid_dir = direction_dir->d_parent; - qroot_dir = qid_dir->d_parent; - dev_dir = qroot_dir->d_parent; - - /* convert this string as integer */ - rv = kstrtoint((const char *)qid_dir->d_iname, 0, &qidx); - if (rv < 0) { - rv = -ENODEV; - return rv; - } - - /* convert colon sepearted b:d:f to hex */ - rptr = dev_dir->d_iname; - lptr = dev_name; - while (*rptr) { - if (*rptr == ':') { - rptr++; - continue; - } - *lptr++ = *rptr++; - } - - /* convert this string as hex integer */ - rv = kstrtoul((const char *)dev_name, 16, &dev_id); - if (rv < 0) { - pr_err("%s, kstrtoint failed for %s, Error:%d\n", __func__, - dev_dir->d_iname, rv); - rv = -ENODEV; - return rv; - } - - priv = (struct dbgfs_q_priv *) kzalloc(sizeof(struct dbgfs_q_priv), - GFP_KERNEL); - if (!priv) { - rv = -ENOMEM; - return rv; - } - - priv->dev_hndl = (unsigned long)descq->xdev; - priv->qhndl = qdma_device_get_id_from_descq(descq->xdev, descq); - - fp->private_data = priv; - - return 0; -} - -/*****************************************************************************/ -/** - * q_dbg_file_release() - function that provides generic release - * - * @param[in] inode: pointer to file inode - * @param[in] fp: pointer to file structure - * - * @return 0: success - * @return <0: error - *****************************************************************************/ -static int q_dbg_file_release(struct inode *inode, struct file *fp) -{ - kfree(fp->private_data); - - fp->private_data = NULL; - - return 0; -} - -/*****************************************************************************/ -/** - * qdbg_cntxt_read() - reads queue context for a queue - * - * @param[in] dev_hndl: xdev device handle - * @param[in] id: queue handle - * @param[out] buf: buffer to collect the context info - * @param[in] buflen: buffer len - * @param[in] type: context type - * - * @return >0: size read - * @return <0: error - *****************************************************************************/ -static int qdbg_cntxt_read(unsigned long dev_hndl, unsigned long id, - char **data, int *data_len, enum dbgfs_desc_type type) -{ - int rv = 0; - char *buf = NULL; - int buflen = DEBUGFS_QUEUE_CTXT_SZ; - struct qdma_descq *descq = NULL; - struct xlnx_dma_dev *xdev = (struct xlnx_dma_dev *)dev_hndl; - - if (!xdev) - return -EINVAL; - - if (xdev_check_hndl(__func__, xdev->conf.pdev, dev_hndl) < 0) - return -EINVAL; - - /* allocate memory */ - buf = (char *) kzalloc(buflen, GFP_KERNEL); - if (!buf) - return -ENOMEM; - - /** get descq by id */ - descq = qdma_device_get_descq_by_id(xdev, id, buf, buflen, 0); - if (!descq) { - kfree(buf); - return -EINVAL; - } - - rv = qdma_descq_context_dump(descq, buf, buflen); - if (rv < 0) { - pr_err("%s: Failed to dump the context, rv = %d", - descq->conf.name, rv); - return descq->xdev->hw.qdma_get_error_code(rv); - } - - - buf[rv] = '\0'; - - *data = buf; - *data_len = buflen; - - return rv; -} - -/*****************************************************************************/ -/** - * qdbg_info_read() - reads queue info for a queue - * - * @param[in] dev_hndl: xdev device handle - * @param[in] id: queue handle - * @param[out] data: buffer pointer to collect the queue info - * @param[out] data_len: buffer len pointer - * @param[in] type: ring type - * - * @return >0: size read - * @return <0: error - *****************************************************************************/ -static int qdbg_info_read(unsigned long dev_hndl, unsigned long id, char **data, - int *data_len, enum dbgfs_desc_type type) -{ - int len = 0; - char *buf = NULL; - int buflen = DEBUGFS_QUEUE_INFO_SZ; - struct qdma_descq *descq = NULL; - struct xlnx_dma_dev *xdev = (struct xlnx_dma_dev *)dev_hndl; - - /** allocate memory */ - buf = (char *) kzalloc(buflen, GFP_KERNEL); - if (!buf) - return -ENOMEM; - - descq = qdma_device_get_descq_by_id(xdev, id, buf, buflen, 0); - if (!descq) { - kfree(buf); - return -EINVAL; - } - - len = qdma_descq_dump_state(descq, buf + len, buflen - len); - - *data = buf; - *data_len = buflen; - - return len; -} - -/*****************************************************************************/ -/** - * qdbg_desc_read() - reads descriptors of a queue - * - * @param[in] dev_hndl: xdev device handle - * @param[in] id: queue handle - * @param[out] data: buffer pointer to collect the queue descriptors - * @param[out] data_len: buffer len pointer - * @param[in] type: ring type - * - * @return >0: size read - * @return <0: error - *****************************************************************************/ -static int qdbg_desc_read(unsigned long dev_hndl, unsigned long id, char **data, - int *data_len, enum dbgfs_desc_type type) -{ - int len = 0; - int rngsz = 0; - struct qdma_descq *descq = NULL; - struct xlnx_dma_dev *xdev = (struct xlnx_dma_dev *)dev_hndl; - char *buf = NULL; - int buflen = 0; - - descq = qdma_device_get_descq_by_id(xdev, id, buf, buflen, 0); - if (!descq) - return -EINVAL; - - /** get the ring size */ - if (type != DBGFS_DESC_TYPE_CMPT) - rngsz = descq->conf.rngsz; - else - rngsz = descq->conf.rngsz_cmpt; - - /** 128 bytes is to accomodate header printed in the begining */ - buflen = (rngsz * DEBUGFS_QUEUE_DESC_SZ) + 128; - - /* allocate memory */ - buf = (char *) kzalloc(buflen, GFP_KERNEL); - if (!buf) - return -ENOMEM; - - if (type != DBGFS_DESC_TYPE_CMPT) { - len += qdma_queue_dump_desc(dev_hndl, id, - 0, rngsz-1, buf + len, buflen - len); - } else { - len += qdma_queue_dump_cmpt(dev_hndl, id, - 0, rngsz-1, buf + len, buflen - len); - } - - *data = buf; - *data_len = buflen; - - return len; -} - -/*****************************************************************************/ -/** - * q_dbg_file_read() - static function that provides common read - * - * @param[in] fp: pointer to file structure - * @param[out] user_buffer: pointer to user buffer - * @param[in] count: size of data to read - * @param[in/out] ppos: pointer to offset read - * @param[in] type: information type - * - * @return >0: size read - * @return <0: error - *****************************************************************************/ -static ssize_t q_dbg_file_read(struct file *fp, char __user *user_buffer, - size_t count, loff_t *ppos, enum dbgfs_queue_info_type type) -{ - char *buf = NULL; - int buf_len = 0, len = 0, rv = 0; - struct dbgfs_q_priv *qpriv = (struct dbgfs_q_priv *)fp->private_data; - - if (qpriv->data == NULL && qpriv->datalen == 0) { - if (type == DBGFS_QINFO_INFO) { - rv = qdbg_info_read(qpriv->dev_hndl, qpriv->qhndl, - &buf, &buf_len, DBGFS_DESC_TYPE_C2H); - } else if (type == DBGFS_QINFO_CNTXT) { - rv = qdbg_cntxt_read(qpriv->dev_hndl, qpriv->qhndl, - &buf, &buf_len, DBGFS_DESC_TYPE_C2H); - } else if (type == DBGFS_QINFO_DESC) { - rv = qdbg_desc_read(qpriv->dev_hndl, qpriv->qhndl, - &buf, &buf_len, DBGFS_DESC_TYPE_C2H); - } - - if (rv < 0) - goto q_dbg_file_read_exit; - - qpriv->datalen = rv; - qpriv->data = buf; - } - - buf = qpriv->data; - len = qpriv->datalen; - - if (!buf) - goto q_dbg_file_read_exit; - - /** write to user buffer */ - if (*ppos >= len) { - rv = 0; - goto q_dbg_file_read_exit; - } - - if (*ppos + count > len) - count = len - *ppos; - - if (copy_to_user(user_buffer, buf + *ppos, count)) { - rv = -EFAULT; - goto q_dbg_file_read_exit; - } - - *ppos += count; - rv = count; - - pr_debug("number of bytes written to user space is %zu\n", count); - -q_dbg_file_read_exit: - kfree(buf); - qpriv->data = NULL; - qpriv->datalen = 0; - return rv; -} - -/*****************************************************************************/ -/** - * q_info_open() - static function that executes info file open - * - * @param[in] inode: pointer to file inode - * @param[in] fp: pointer to file structure - * - * @return 0: success - * @return <0: error - *****************************************************************************/ -static int q_info_open(struct inode *inode, struct file *fp) -{ - return q_dbg_file_open(inode, fp); -} - -/*****************************************************************************/ -/** - * q_info_read() - static function that executes info file read - * - * @param[in] fp: pointer to file structure - * @param[out] user_buffer: pointer to user buffer - * @param[in] count: size of data to read - * @param[in/out] ppos: pointer to offset read - * - * @return >0: size read - * @return <0: error - *****************************************************************************/ -static ssize_t q_info_read(struct file *fp, char __user *user_buffer, - size_t count, loff_t *ppos) -{ - return q_dbg_file_read(fp, user_buffer, count, ppos, DBGFS_QINFO_INFO); -} - -/*****************************************************************************/ -/** - * q_cntxt_open() - static function that executes cntxt file open - * - * @param[in] inode: pointer to file inode - * @param[in] fp: pointer to file structure - * - * @return 0: success - * @return <0: error - *****************************************************************************/ -static int q_cntxt_open(struct inode *inode, struct file *fp) -{ - return q_dbg_file_open(inode, fp); -} - -/*****************************************************************************/ -/** - * q_cntxt_read() - static function that performs cntxt file read - * - * @param[in] fp: pointer to file structure - * @param[out] user_buffer: pointer to user buffer - * @param[in] count: size of data to read - * @param[in/out] ppos: pointer to offset read - * - * @return >0: size read - * @return <0: error - *****************************************************************************/ -static ssize_t q_cntxt_read(struct file *fp, char __user *user_buffer, - size_t count, loff_t *ppos) -{ - return q_dbg_file_read(fp, user_buffer, count, ppos, DBGFS_QINFO_CNTXT); -} - -/*****************************************************************************/ -/** - * q_desc_open() - static function that executes desc file open - * - * @param[in] inode: pointer to file inode - * @param[in] fp: pointer to file structure - * - * @return 0: success - * @return <0: error - *****************************************************************************/ -static int q_desc_open(struct inode *inode, struct file *fp) -{ - return q_dbg_file_open(inode, fp); -} - -/*****************************************************************************/ -/** - * q_desc_read() - static function that executes desc read - * - * @param[in] fp: pointer to file structure - * @param[out] user_buffer: pointer to user buffer - * @param[in] count: size of data to read - * @param[in/out] ppos: pointer to offset read - * - * @return >0: size read - * @return <0: error - *****************************************************************************/ -static ssize_t q_desc_read(struct file *fp, char __user *user_buffer, - size_t count, loff_t *ppos) -{ - return q_dbg_file_read(fp, user_buffer, count, ppos, DBGFS_QINFO_DESC); -} - -/*****************************************************************************/ -/** - * create_q_dbg_files() - static function to create queue debug files - * - * @param[in] queue_root: debugfs root for a queue - * - * @return >0: size read - * @return <0: error - *****************************************************************************/ -static int create_q_dbg_files(struct qdma_descq *descq, - struct dentry *queue_root) -{ - struct dentry *fp[DBGFS_QINFO_END] = { NULL }; - struct file_operations *fops = NULL; - int i = 0; - - memset(qf, 0, sizeof(struct dbgfs_q_dbgf) * DBGFS_QINFO_END); - - for (i = 0; i < DBGFS_QINFO_END; i++) { - fops = &qf[i].fops; - fops->owner = THIS_MODULE; - switch (i) { - case DBGFS_QINFO_INFO: - snprintf(qf[i].name, DBGFS_DBG_FNAME_SZ, "%s", "info"); - fops->open = q_info_open; - fops->read = q_info_read; - fops->release = q_dbg_file_release; - break; - case DBGFS_QINFO_CNTXT: - snprintf(qf[i].name, DBGFS_DBG_FNAME_SZ, "%s", "cntxt"); - fops->open = q_cntxt_open; - fops->read = q_cntxt_read; - fops->release = q_dbg_file_release; - break; - case DBGFS_QINFO_DESC: - snprintf(qf[i].name, DBGFS_DBG_FNAME_SZ, "%s", "desc"); - fops->open = q_desc_open; - fops->read = q_desc_read; - fops->release = q_dbg_file_release; - break; - } - } - - for (i = 0; i < DBGFS_QINFO_END; i++) { - fp[i] = debugfs_create_file(qf[i].name, 0644, queue_root, - descq, &qf[i].fops); - if (!fp[i]) - return -1; - } - return 0; -} - -/*****************************************************************************/ -/** - * dbgfs_queue_init() - queue initialization function - * - * @param[in] conf: queue configuration - * @param[in] pair_conf: pair queue configuration - * @param[in] dbgfs_queues_root: root directory for all queues - * - * @return 0: success - * @return <0: error - *****************************************************************************/ -int dbgfs_queue_init(struct qdma_queue_conf *conf, - struct qdma_descq *pairq, - struct dentry *dbgfs_queues_root) -{ - char qname[16] = {0}; - char qdir[8] = {0}; - struct dentry *dbgfs_qidx_root = NULL; - struct dentry *dbgfs_queue_root = NULL; - struct dentry *dbgfs_cmpt_queue_root = NULL; - struct qdma_descq *descq = container_of(conf, struct qdma_descq, conf); - int rv = 0; - - if (!descq) - return -EINVAL; - snprintf(qname, 16, "%u", conf->qidx); - - spin_lock(&descq->xdev->qidx_lock); - /** create queue root only if it is not created */ - if (pairq->dbgfs_qidx_root) { - dbgfs_qidx_root = pairq->dbgfs_qidx_root; - } else { - /* create a directory for the queue in debugfs */ - dbgfs_qidx_root = debugfs_create_dir(qname, - dbgfs_queues_root); - if (!dbgfs_qidx_root) { - pr_err("Failed to create queue [%s] directory\n", - qname); - spin_unlock(&descq->xdev->qidx_lock); - return -1; - } - } - - /* create a directory for direction */ - if (conf->q_type == Q_C2H) - snprintf(qdir, 8, "%s", "c2h"); - else if (conf->q_type == Q_H2C) - snprintf(qdir, 8, "%s", "h2c"); - else - snprintf(qdir, 8, "%s", "cmpt"); - - dbgfs_queue_root = debugfs_create_dir(qdir, - dbgfs_qidx_root); - if (!dbgfs_queue_root) { - pr_err("Failed to create %s directory under %s", - qdir, qname); - goto dbgfs_queue_init_fail; - } - - if ((conf->q_type == Q_C2H) && conf->st) { - /* create a directory for the cmpt in debugfs */ - dbgfs_cmpt_queue_root = debugfs_create_dir("cmpt", - dbgfs_qidx_root); - if (!dbgfs_cmpt_queue_root) { - pr_err("Failed to create cmpt directory under %s", - qname); - goto dbgfs_queue_init_fail; - } - } - - /* intialize fops and create all the files */ - rv = create_q_dbg_files(descq, dbgfs_queue_root); - if (rv < 0) { - pr_err("Failed to create qdbg files, removing %s dir\n", - qdir); - debugfs_remove_recursive(dbgfs_queue_root); - goto dbgfs_queue_init_fail; - } - - if (dbgfs_cmpt_queue_root) { - rv = create_cmpt_q_dbg_files(descq, dbgfs_cmpt_queue_root); - if (rv < 0) { - pr_err("Failed to create cmptq dbg files,removing cmpt dir\n"); - debugfs_remove_recursive(dbgfs_cmpt_queue_root); - goto dbgfs_queue_init_fail; - } - } - - descq->dbgfs_qidx_root = dbgfs_qidx_root; - descq->dbgfs_queue_root = dbgfs_queue_root; - descq->dbgfs_cmpt_queue_root = dbgfs_cmpt_queue_root; - spin_unlock(&descq->xdev->qidx_lock); - - return 0; - -dbgfs_queue_init_fail: - if (pairq->dbgfs_qidx_root) { - spin_unlock(&descq->xdev->qidx_lock); - return -1; - } - pr_err("Failed to init q debug files, removing [%s] dir\n", qname); - debugfs_remove_recursive(dbgfs_qidx_root); - spin_unlock(&descq->xdev->qidx_lock); - return -1; -} - -/*****************************************************************************/ -/** - * dbgfs_queue_exit() - debugfs queue teardown function - * - * @param[in] conf: queue configuration - * @param[in] conf: pair queue configuration - * - *****************************************************************************/ -void dbgfs_queue_exit(struct qdma_queue_conf *conf, - struct qdma_descq *pairq) -{ - struct qdma_descq *descq = container_of(conf, struct qdma_descq, conf); - - if (!descq) - return; - debugfs_remove_recursive(descq->dbgfs_queue_root); - debugfs_remove_recursive(descq->dbgfs_cmpt_queue_root); - descq->dbgfs_queue_root = NULL; - descq->dbgfs_cmpt_queue_root = NULL; - if (!pairq) - debugfs_remove_recursive(descq->dbgfs_qidx_root); - - descq->dbgfs_qidx_root = NULL; -} - -#endif diff --git a/QDMA/linux-kernel/driver/libqdma/qdma_debugfs_queue.h b/QDMA/linux-kernel/driver/libqdma/qdma_debugfs_queue.h deleted file mode 100755 index 37d62e7d0..000000000 --- a/QDMA/linux-kernel/driver/libqdma/qdma_debugfs_queue.h +++ /dev/null @@ -1,33 +0,0 @@ -/* - * This file is part of the Xilinx DMA IP Core driver for Linux - * - * Copyright (c) 2017-2022, Xilinx, Inc. All rights reserved. - * Copyright (c) 2022, Advanced Micro Devices, Inc. All rights reserved. - * - * This source code is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * The full GNU General Public License is included in this distribution in - * the file called "COPYING". - */ - -#ifndef __QDMA_DEBUGFS_QUEUE_H__ -#define __QDMA_DEBUGFS_QUEUE_H__ - -#include "qdma_debugfs.h" -#include "qdma_descq.h" - - -int dbgfs_queue_init(struct qdma_queue_conf *conf, - struct qdma_descq *pairq, - struct dentry *dbgfs_queues_root); -void dbgfs_queue_exit(struct qdma_queue_conf *conf, - struct qdma_descq *pairq); - -#endif diff --git a/QDMA/linux-kernel/driver/libqdma/qdma_descq.c b/QDMA/linux-kernel/driver/libqdma/qdma_descq.c deleted file mode 100755 index db8e44e50..000000000 --- a/QDMA/linux-kernel/driver/libqdma/qdma_descq.c +++ /dev/null @@ -1,2120 +0,0 @@ -/* - * This file is part of the Xilinx DMA IP Core driver for Linux - * - * Copyright (c) 2017-2022, Xilinx, Inc. All rights reserved. - * Copyright (c) 2022, Advanced Micro Devices, Inc. All rights reserved. - * - * This source code is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * The full GNU General Public License is included in this distribution in - * the file called "COPYING". - */ - -#define pr_fmt(fmt) KBUILD_MODNAME ":%s: " fmt, __func__ - -#include "qdma_descq.h" - -#include -#include - -#include "qdma_device.h" -#include "qdma_intr.h" -#include "qdma_regs.h" -#include "qdma_thread.h" -#include "qdma_context.h" -#include "qdma_st_c2h.h" -#include "qdma_access_common.h" -#include "thread.h" -#include "qdma_ul_ext.h" -#include "version.h" -#ifdef ERR_DEBUG -#include "qdma_nl.h" -#endif - -struct q_state_name q_state_list[] = { - {Q_STATE_DISABLED, "disabled"}, - {Q_STATE_ENABLED, "cfg'ed"}, - {Q_STATE_ONLINE, "online"} -}; - -/* - * dma transfer requests - */ -#ifdef DEBUG -static void sgl_dump(struct qdma_sw_sg *sgl, unsigned int sgcnt) -{ - struct qdma_sw_sg *sg = sgl; - int i; - - pr_info("sgl 0x%p, sgcntt %u.\n", sgl, sgcnt); - - for (i = 0; i < sgcnt; i++, sg++) - pr_info("%d, 0x%p, pg 0x%p,%u+%u, dma 0x%llx.\n", - i, sg, sg->pg, sg->offset, sg->len, sg->dma_addr); -} -#endif - -u64 rdtsc_gettime(void) -{ - unsigned int low, high; - - asm volatile("rdtscp" : "=a" (low), "=d" (high)); - return low | ((u64)high) << 32; -} - -int qdma_sgl_find_offset(struct qdma_request *req, struct qdma_sw_sg **sg_p, - unsigned int *sg_offset) -{ - struct qdma_sgt_req_cb *cb = qdma_req_cb_get(req); - struct qdma_sw_sg *sg = req->sgl; - unsigned int sgcnt = req->sgcnt; - unsigned int offset = cb->offset; - unsigned int len = 0; - int i; - - if (req->count == 0) { - *sg_p = sg; - *sg_offset = 0; - return 0; - } - - - for (i = 0; i < sgcnt; i++, sg++) { - len += sg->len; - - if (len == offset) { - *sg_p = sg + 1; - *sg_offset = 0; - ++i; - break; - } else if (len > offset) { - *sg_p = sg; - *sg_offset = sg->len - (len - offset); - break; - } - } - - if (i < sgcnt) - return i; - - return -EINVAL; -} - -void qdma_update_request(void *q_hndl, struct qdma_request *req, - unsigned int num_desc, - unsigned int data_cnt, - unsigned int sg_offset, - void *sg) -{ - struct qdma_descq *descq = (struct qdma_descq *)q_hndl; - struct qdma_sgt_req_cb *cb = qdma_req_cb_get(req); - - cb->desc_nr += num_desc; - cb->offset += data_cnt; - cb->sg_offset = sg_offset; - cb->sg = sg; - if (cb->offset >= req->count) { - qdma_work_queue_del(descq, cb); - list_add_tail(&cb->list, &descq->pend_list); - } -} - -static int descq_mm_n_h2c_cmpl_status(struct qdma_descq *descq); - -static int descq_poll_mm_n_h2c_cmpl_status(struct qdma_descq *descq) -{ - enum qdma_drv_mode drv_mode = descq->xdev->conf.qdma_drv_mode; - - if ((drv_mode == POLL_MODE) || (drv_mode == AUTO_MODE)) { - descq->proc_req_running = 1; - return descq_mm_n_h2c_cmpl_status(descq); - } else - return 0; -} - -static inline unsigned int incr_pidx(unsigned int pidx, unsigned int incr_val, - unsigned int ring_sz) -{ - pidx += incr_val; - if (pidx >= ring_sz) - pidx -= ring_sz; - - return pidx; -} - -static inline int qdma_pidx_update(struct qdma_descq *descq, - unsigned char force) -{ - int ret = 0; - unsigned int desc_avail_max = descq->conf.rngsz - 1; - - /* interrupt for last update came, now submit descs that are setup */ - if (force) /* re-arm interrupt with pidx update */ - goto update; - /* q is not very busy, go ahead and submit */ - if (descq->avail > (desc_avail_max - descq->conf.pidx_acc)) - goto update; - - /* accumulating descs to be submitted */ - if (descq->desc_pend < descq->conf.pidx_acc) - goto exit_update; - -update: - ret = queue_pidx_update(descq->xdev, descq->conf.qidx, - descq->conf.q_type, &descq->pidx_info); - if (ret < 0) { - pr_err("%s: Failed to update pidx\n", - descq->conf.name); - return -EINVAL; - } - - descq->desc_pend = 0; - -exit_update: - return ret; -} - -static ssize_t descq_mm_proc_request(struct qdma_descq *descq) -{ - int rv = 0; - unsigned int desc_written = 0; - unsigned int rngsz = descq->conf.rngsz; - unsigned int pidx; - u64 ep_addr = 0; - struct qdma_mm_desc *desc; - struct qdma_queue_conf *qconf = &descq->conf; - unsigned char is_ul_ext = (qconf->desc_bypass && - qconf->fp_bypass_desc_fill) ? 1 : 0; - u32 aperture = qconf->aperture_size ? - qconf->aperture_size : QDMA_DESC_BLEN_MAX; - u8 keyhole_en = qconf->aperture_size ? 1 : 0; - u64 ep_addr_max = 0; - - lock_descq(descq); - /* process completion of submitted requests */ - if (descq->q_stop_wait) { - descq_mm_n_h2c_cmpl_status(descq); - unlock_descq(descq); - return 0; - } - if (unlikely(descq->q_state != Q_STATE_ONLINE)) { - unlock_descq(descq); - return 0; - } - - if (descq->proc_req_running) { - unlock_descq(descq); - return 0; - } - - pidx = descq->pidx; - desc = (struct qdma_mm_desc *)descq->desc + pidx; - - descq_poll_mm_n_h2c_cmpl_status(descq); - - while (!list_empty(&descq->work_list)) { - struct qdma_sgt_req_cb *cb = list_first_entry(&descq->work_list, - struct qdma_sgt_req_cb, list); - struct qdma_request *req = (struct qdma_request *)cb; - struct qdma_sw_sg *sg = req->sgl; - unsigned int sg_offset = 0; - unsigned int sg_max = req->sgcnt; - struct qdma_mm_desc *desc_start = NULL; - struct qdma_mm_desc *desc_end = NULL; - unsigned int desc_max = descq->avail; - unsigned int data_cnt = 0; - unsigned int desc_cnt = 0; - unsigned int len = 0; - int i = 0; - int rv; - - ep_addr_max = req->ep_addr + aperture - 1; - - /** - * When keyhole feature is enabled, the ep_addr - * cannot ever exceed the aperture size. - * The offset calculation is implemented below. - */ - if (!keyhole_en) - ep_addr = req->ep_addr + cb->offset; - else - ep_addr = req->ep_addr + (cb->offset & (aperture - 1)); - - if (!desc_max) { - descq_poll_mm_n_h2c_cmpl_status(descq); - desc_max = descq->avail; - } - - if (!desc_max) - break; - - if (is_ul_ext) { - int desc_consumed = - qconf->fp_bypass_desc_fill(descq, - QDMA_Q_MODE_MM, - (qconf->q_type == Q_C2H) ? - QDMA_Q_DIR_C2H : - QDMA_Q_DIR_H2C, - req); - if (desc_consumed > 0) - desc_cnt += desc_consumed; - goto update_pidx; - } - rv = qdma_sgl_find_offset(req, &sg, &sg_offset); - if (rv < 0) { - pr_info("descq %s, req 0x%p, OOR %u/%u, %d/%u.\n", - descq->conf.name, req, cb->offset, - req->count, rv, sg_max); - qdma_update_request(descq, req, 0, 0, 0, NULL); - continue; - } - i = rv; - pr_debug("%s, req 0x%p, offset %u/%u -> sg %d, 0x%p,%u.\n", - descq->conf.name, req, cb->offset, req->count, - i, sg, sg_offset); - - desc_start = desc; - for (; i < sg_max && desc_cnt < desc_max; i++, sg++) { - unsigned int tlen = sg->len; - dma_addr_t src_addr = sg->dma_addr; - unsigned int pg_off = sg->offset; - - pr_debug("desc %u/%u, sgl %d, len %u,%u, offset %u.\n", - desc_cnt, desc_max, i, len, tlen, sg_offset); - - desc->flag_len = 0; - if (sg_offset) { - tlen -= sg_offset; - src_addr += sg_offset; - pg_off += sg_offset; - sg_offset = 0; - } - - do { - unsigned int len = min_t(unsigned int, tlen, - aperture); - - if (keyhole_en) { - if (ep_addr > ep_addr_max) - ep_addr = req->ep_addr; - - if (ep_addr + len > ep_addr_max) - len = ep_addr_max - ep_addr + 1; - } - - desc_end = desc; - sg_offset += len; - - desc->rsvd1 = 0UL; - desc->rsvd0 = 0U; - - if (descq->conf.q_type == Q_C2H) { - desc->src_addr = ep_addr; - desc->dst_addr = src_addr; - } else { - desc->dst_addr = ep_addr; - desc->src_addr = src_addr; - } - - desc->flag_len = len; - desc->flag_len |= (1 << S_DESC_F_DV); - ep_addr += len; - data_cnt += len; - src_addr += len; - tlen -= len; - pg_off += len; - - if (++pidx == rngsz) { - pidx = 0; - desc = - (struct qdma_mm_desc *)descq->desc; - } else { - desc++; - } - - desc_cnt++; - if (desc_cnt == desc_max) - break; - } while (tlen); - if (!tlen) - sg_offset = 0; - } - if (i == sg_max) { - sg = NULL; - sg_offset = 0; - } - - if (!desc_end || !desc_start) { - pr_info("descq %s, %u, pidx 0x%x, desc 0x%p ~ 0x%p.\n", - descq->conf.name, descq->qidx_hw, pidx, - desc_start, desc_end); - break; - } - - /* set eop */ - desc_end->flag_len |= (1 << S_DESC_F_EOP); - /* set sop */ - desc_start->flag_len |= (1 << S_DESC_F_SOP); - qdma_update_request(descq, req, desc_cnt, data_cnt, sg_offset, - sg); - descq->pidx = pidx; - descq->avail -= desc_cnt; -update_pidx: - - desc_written += desc_cnt; - - pr_debug("descq %s, +%u,%u, avail %u, ep_addr 0x%llx + 0x%x(%u).\n", - descq->conf.name, desc_cnt, pidx, descq->avail, - req->ep_addr, data_cnt, data_cnt); - - } - - if (desc_written) { - descq->pend_list_empty = 0; - descq->pidx_info.pidx = descq->pidx; - rv = queue_pidx_update(descq->xdev, descq->conf.qidx, - descq->conf.q_type, &descq->pidx_info); - if (unlikely(rv < 0)) { - pr_err("%s: Failed to update pidx\n", - descq->conf.name); - unlock_descq(descq); - return -EINVAL; - } - descq_poll_mm_n_h2c_cmpl_status(descq); - } - - descq->proc_req_running = 0; - unlock_descq(descq); - - if (desc_written && descq->cmplthp) - qdma_kthread_wakeup(descq->cmplthp); - - return 0; -} -/** - * This function is called directly while sending packet or as interrupt - * service when any pending request or pending descriptor is present. - */ -static ssize_t descq_proc_st_h2c_request_qep(struct qdma_descq *descq) -{ - int ret = 0; - struct qdma_request *req; - unsigned int desc_written = 0; - unsigned int desc_cnt = 0; - - /* exit as packet have been queued and can be processes as part of who - * ever holding the lock or during interrupt service - */ - if (!(spin_trylock_bh(&(descq)->lock))) - return 0; - - /* process completion of submitted requests */ - if (unlikely(descq->q_stop_wait)) { - descq_mm_n_h2c_cmpl_status(descq); - unlock_descq(descq); - return 0; - } - - if (unlikely(descq->q_state != Q_STATE_ONLINE)) { - unlock_descq(descq); - return 0; - } - -setup_desc: - while (qdma_work_queue_len(descq) && descq->avail) { - req = qdma_work_queue_first_entry(descq); - desc_cnt = descq->conf.fp_bypass_desc_fill(descq, - QDMA_Q_MODE_ST, QDMA_Q_DIR_H2C, req); - - if (unlikely(desc_cnt == 0)) - break; - - desc_written += desc_cnt; - - if (desc_written >= descq->conf.pidx_acc) - break; - } - - if (unlikely(!desc_written)) { - /* packet queued while holding lock and no interrupt pending */ - if (unlikely(qdma_work_queue_len(descq) && - descq->avail == descq->conf.rngsz - 1)) { - unlock_descq(descq); - descq_proc_st_h2c_request_qep(descq); - return 0; - } - unlock_descq(descq); - return 0; - } - - descq->desc_pend += desc_written; - descq->pidx_info.pidx = descq->pidx; - - ret = qdma_pidx_update(descq, 0); - if (unlikely(ret < 0)) { - pr_err("%s: Failed to update pidx\n", - descq->conf.name); - unlock_descq(descq); - return -EINVAL; - } - - if (descq->work_req_pend && (desc_written >= descq->conf.pidx_acc)) { - desc_written = 0; - goto setup_desc; - } - - unlock_descq(descq); - - return ret; -} - - -static ssize_t descq_proc_st_h2c_request(struct qdma_descq *descq) -{ - int ret = 0; - struct qdma_h2c_desc *desc; - u8 *tx_time_pkt_offset = NULL; - unsigned int rngsz = descq->conf.rngsz; - unsigned int pidx; - unsigned int desc_written = 0; - struct qdma_queue_conf *qconf = &descq->conf; - unsigned char is_ul_ext = (qconf->desc_bypass && - qconf->fp_bypass_desc_fill) ? 1 : 0; - struct qdma_dev *qdev = NULL; - - lock_descq(descq); - /* process completion of submitted requests */ - if (descq->q_stop_wait) { - descq_mm_n_h2c_cmpl_status(descq); - unlock_descq(descq); - return 0; - } - if (unlikely(descq->q_state != Q_STATE_ONLINE)) { - unlock_descq(descq); - return 0; - } - - if (descq->proc_req_running) { - unlock_descq(descq); - return 0; - } - - qdev = xdev_2_qdev(descq->xdev); - /* service completion first */ - descq_poll_mm_n_h2c_cmpl_status(descq); - - pidx = descq->pidx; - desc = (struct qdma_h2c_desc *)descq->desc + pidx; - while (!list_empty(&descq->work_list)) { - struct qdma_sgt_req_cb *cb = list_first_entry(&descq->work_list, - struct qdma_sgt_req_cb, list); - struct qdma_request *req = (struct qdma_request *)cb; - struct qdma_sw_sg *sg = req->sgl; - unsigned int sg_offset = 0; - unsigned int sg_max = req->sgcnt; - unsigned int desc_max = descq->avail; - unsigned int data_cnt = 0; - unsigned int desc_cnt = 0; - unsigned int pktsz = req->ep_addr ? - min_t(unsigned int, req->ep_addr, PAGE_SIZE) : - PAGE_SIZE; - int i = 0; - int rv; - - if (!desc_max) { - descq_poll_mm_n_h2c_cmpl_status(descq); - desc_max = descq->avail; - } - - if (!desc_max) - break; - -#ifdef DEBUG - pr_info("%s, req %u.\n", descq->conf.name, req->count); - sgl_dump(req->sgl, sg_max); -#endif - if (is_ul_ext) { - int desc_consumed = - qconf->fp_bypass_desc_fill(descq, - QDMA_Q_MODE_ST, - QDMA_Q_DIR_H2C, - req); - if (desc_consumed > 0) - desc_cnt += desc_consumed; - goto update_pidx; - } - - rv = qdma_sgl_find_offset(req, &sg, - &sg_offset); - - if (rv < 0) { - pr_err("descq %s, req 0x%p, OOR %u/%u, %d/%u.\n", - descq->conf.name, req, cb->offset, - req->count, rv, sg_max); - qdma_update_request(descq, req, 0, 0, 0, NULL); - continue; - } - i = rv; - pr_debug("%s, req 0x%p, offset %u/%u -> sg %d, 0x%p,%u.\n", - descq->conf.name, req, cb->offset, req->count, - i, sg, sg_offset); - desc->flags = 0; - desc->cdh_flags = 0; - - for (; i < sg_max && desc_cnt < desc_max; i++, sg++) { - unsigned int tlen = sg->len; - dma_addr_t src_addr = sg->dma_addr; - - if (sg_offset) { - tlen -= sg_offset; - src_addr += sg_offset; - sg_offset = 0; - } - - do { /* to support zero byte transfer */ - unsigned int len = min_t(unsigned int, tlen, - pktsz); - - sg_offset += len; - desc->src_addr = src_addr; - desc->len = len; - desc->pld_len = len; - desc->cdh_flags |= S_H2C_DESC_F_ZERO_CDH; - data_cnt += len; - src_addr += len; - tlen -= len; - tx_time_pkt_offset = - (u8 *)(page_address(sg->pg) + - sg->offset); - - /* Setting SOP/EOP for the dummy bypass case */ - if (descq->conf.desc_bypass) { - if (i == 0) - desc->flags |= S_H2C_DESC_F_SOP; - - if ((i == sg_max - 1)) - desc->flags |= S_H2C_DESC_F_EOP; - } - -#if 0 - pr_info("desc %d, pidx 0x%x, data_cnt %u, cb off %u:\n", - i, pidx, data_cnt, cb->offset); - print_hex_dump(KERN_INFO, "desc", - DUMP_PREFIX_OFFSET, 16, 1, - (void *)desc, 16, false); -#endif - - if (++pidx == rngsz) { - pidx = 0; - desc = - (struct qdma_h2c_desc *)descq->desc; - } else { - desc++; - desc->flags = 0; - desc->cdh_flags = 0; - } - - desc_cnt++; - if (desc_cnt == desc_max) - break; - } while (tlen); - if (!tlen) - sg_offset = 0; - - } - if (i == sg_max) { - sg = NULL; - sg_offset = 0; - } - qdma_update_request(descq, req, desc_cnt, data_cnt, sg_offset, - sg); - descq->pidx = pidx; - descq->avail -= desc_cnt; -update_pidx: - if (!desc_cnt) - break; - desc_written += desc_cnt; - - pr_debug("descq %s, +%u,%u, avail %u, 0x%x(%u), cb off %u.\n", - descq->conf.name, desc_cnt, pidx, descq->avail, - data_cnt, data_cnt, cb->offset); - - } - - if (desc_written) { - descq->pend_list_empty = 0; - descq->pidx_info.pidx = descq->pidx; - if (descq->conf.ping_pong_en) { - if (tx_time_pkt_offset != NULL) { - u64 tx_time = rdtsc_gettime(); - - qdev->c2h_descq[qconf->qidx].ping_pong_tx_time = - tx_time; - memcpy(tx_time_pkt_offset, &tx_time, - sizeof(tx_time)); - } else - pr_err("Err: Tx Time Offset is NULL\n"); - } - - - ret = queue_pidx_update(descq->xdev, descq->conf.qidx, - descq->conf.q_type, &descq->pidx_info); - if (ret < 0) { - pr_err("%s: Failed to update pidx\n", - descq->conf.name); - unlock_descq(descq); - return -EINVAL; - } - descq_poll_mm_n_h2c_cmpl_status(descq); - } - - descq->proc_req_running = 0; - - if (desc_written && descq->cmplthp) - qdma_kthread_wakeup(descq->cmplthp); - - unlock_descq(descq); - - return 0; -} - -/* - * descriptor Queue - */ -static inline int get_desc_size(struct qdma_descq *descq) -{ - if (descq->conf.desc_bypass && (descq->conf.sw_desc_sz == DESC_SZ_64B)) - return DESC_SZ_64B_BYTES; - if (!descq->conf.st) - return (int)sizeof(struct qdma_mm_desc); - - if (descq->conf.q_type == Q_C2H) - return (int)sizeof(struct qdma_c2h_desc); - - return (int)sizeof(struct qdma_h2c_desc); -} - -static inline int get_desc_cmpl_status_size(struct qdma_descq *descq) -{ - return (int)sizeof(struct qdma_desc_cmpl_status); -} - -static inline void desc_ring_free(struct xlnx_dma_dev *xdev, int ring_sz, - int desc_sz, int cs_sz, u8 *desc, dma_addr_t desc_bus) -{ - unsigned int len = ring_sz * desc_sz + cs_sz; - - pr_debug("free %u(0x%x)=%d*%u+%d, 0x%p, bus 0x%llx.\n", - len, len, desc_sz, ring_sz, cs_sz, desc, desc_bus); - - dma_free_coherent(&xdev->conf.pdev->dev, - ((size_t)ring_sz * desc_sz + cs_sz), - desc, desc_bus); -} - -static void *desc_ring_alloc(struct xlnx_dma_dev *xdev, int ring_sz, - int desc_sz, int cs_sz, dma_addr_t *bus, u8 **cs_pp) -{ - unsigned int len = ring_sz * desc_sz + cs_sz; - u8 *p = dma_alloc_coherent(&xdev->conf.pdev->dev, len, bus, GFP_KERNEL); - - if (!p) { - pr_err("%s, OOM, sz ring %d, desc %d, cmpl status sz %d.\n", - xdev->conf.name, ring_sz, desc_sz, cs_sz); - return NULL; - } - - *cs_pp = p + ring_sz * desc_sz; - memset(p, 0, len); - - pr_debug("alloc %u(0x%x)=%d*%u+%d, 0x%p, bus 0x%llx, cmpl status 0x%p.\n", - len, len, desc_sz, ring_sz, cs_sz, p, *bus, *cs_pp); - - return p; -} - -static void desc_alloc_irq(struct qdma_descq *descq) -{ - struct xlnx_dma_dev *xdev = descq->xdev; - unsigned long flags; - int i, idx = 0, min = -1; - - if (!xdev->num_vecs) - return; - - /** Pick the MSI-X vector that currently has the fewest queues - * on PF0, vector#0 is dedicated for Error interrupts and - * vector #1 is dedicated for User interrupts - * For all other PFs, vector#0 is dedicated for User interrupts - */ - - idx = xdev->dvec_start_idx; - if (xdev->conf.qdma_drv_mode == DIRECT_INTR_MODE) { - for (i = xdev->dvec_start_idx; i < xdev->num_vecs; i++) { - struct intr_info_t *intr_info_list = - &xdev->dev_intr_info_list[i]; - - spin_lock_irqsave(&intr_info_list->vec_q_list, - flags); - if (!intr_info_list->intr_list_cnt) { - spin_unlock_irqrestore( - &intr_info_list->vec_q_list, - flags); - idx = i; - break; - } - if (min < 0) - min = intr_info_list->intr_list_cnt; - if (intr_info_list->intr_list_cnt < min) { - min = intr_info_list->intr_list_cnt; - idx = i; - } - - spin_unlock_irqrestore(&intr_info_list->vec_q_list, - flags); - } - } - descq->intr_id = idx; - pr_debug("descq->intr_id = %d allocated to qidx = %d\n", - descq->intr_id, descq->conf.qidx); -} - -/* - * writeback handling - */ -static int descq_mm_n_h2c_cmpl_status(struct qdma_descq *descq) -{ - int rv = 0; - unsigned int cidx, cidx_hw; - unsigned int cr; - - pr_debug("descq 0x%p, %s, pidx %u, cidx %u.\n", - descq, descq->conf.name, descq->pidx, descq->cidx); - - if (descq->pidx == descq->cidx) { /* queue empty? */ - pr_debug("descq %s empty, return.\n", descq->conf.name); - return 0; - } - - cidx = descq->cidx; -#ifdef __READ_ONCE_DEFINED__ - cidx_hw = READ_ONCE(((struct qdma_desc_cmpl_status *) - descq->desc_cmpl_status)->cidx); -#else - cidx_hw = ((struct qdma_desc_cmpl_status *) - descq->desc_cmpl_status)->cidx; - dma_rmb(); -#endif - - if (cidx_hw == cidx) /* no new writeback? */ - return 0; - - /* completion credits */ - cr = (cidx_hw < cidx) ? (descq->conf.rngsz - cidx) + cidx_hw : - cidx_hw - cidx; - - pr_debug("%s descq %s, cidx 0x%x -> 0x%x, avail 0x%x + 0x%x.\n", - __func__, descq->conf.name, cidx, - cidx_hw, descq->avail, cr); - - descq->cidx = cidx_hw; - descq->avail += cr; - descq->credit += cr; - - incr_cmpl_desc_cnt(descq, cr); - - /* completes requests */ - pr_debug("%s %s, 0x%p, credit %u + %u.\n", - __func__, descq->conf.name, descq, cr, descq->credit); - - cr = descq->credit; - - while (!list_empty(&descq->pend_list)) { - struct qdma_sgt_req_cb *cb = list_first_entry(&descq->pend_list, - struct qdma_sgt_req_cb, list); - - pr_debug("%s, 0x%p, cb 0x%p, desc_nr %u, credit %u.\n", - descq->conf.name, descq, cb, cb->desc_nr, cr); - - if (cr >= cb->desc_nr) { - pr_debug("%s, cb 0x%p done, credit %u > %u.\n", - descq->conf.name, cb, cr, cb->desc_nr); - cr -= cb->desc_nr; - qdma_sgt_req_done(descq, cb, 0); - } else { - pr_debug("%s, cb 0x%p not done, credit %u < %u.\n", - descq->conf.name, cb, cr, cb->desc_nr); - cb->desc_nr -= cr; - cr = 0; - } - - if (!cr) - break; - } - - descq->credit = cr; - pr_debug("%s, 0x%p, credit %u.\n", - descq->conf.name, descq, descq->credit); - - rv = qdma_pidx_update(descq, 1); - if (unlikely(rv < 0)) - pr_err("%s: Failed to update pidx\n", descq->conf.name); - - return 0; -} - -/* ************** public function definitions ******************************* */ - -void qdma_descq_init(struct qdma_descq *descq, struct xlnx_dma_dev *xdev, - int idx_hw, int idx_sw) -{ - struct qdma_dev *qdev = xdev_2_qdev(xdev); - - memset(descq, 0, sizeof(struct qdma_descq)); - - spin_lock_init(&descq->lock); - spin_lock_init(&descq->work_list_lock); - INIT_LIST_HEAD(&descq->work_list); - INIT_LIST_HEAD(&descq->pend_list); - qdma_waitq_init(&descq->pend_list_wq); - INIT_LIST_HEAD(&descq->intr_list); - INIT_LIST_HEAD(&descq->legacy_intr_q_list); - INIT_WORK(&descq->work, intr_work); - descq->xdev = xdev; - descq->channel = 0; - descq->qidx_hw = qdev->qbase + idx_hw; - descq->conf.qidx = idx_sw; -} - -int qdma_q_desc_get(void *q_hndl, const unsigned int desc_cnt, - struct qdma_q_desc_list **desc_list) -{ - struct qdma_descq *descq = (struct qdma_descq *)q_hndl; - - if (unlikely(desc_cnt >= descq->conf.rngsz)) { - pr_err("Number of descriptors required > ring size"); - return -EINVAL; /* not possible to give so many desc */ - } - - /* - * it is very unlikely that below condition hits in MM or ST H2C as - * one packet is submitted at once. But It is ibserved that HW is not - * giving writeback and sometimes its corresponding interrupt. For this - * reason a polling logic is introduced as below - **/ - if (descq->avail < desc_cnt) - descq_mm_n_h2c_cmpl_status(descq); - - if (unlikely(descq->avail < desc_cnt)) { - pr_err("No entries available to read"); - return -EBUSY; /* curently not available */ - } - - *desc_list = descq->desc_list + descq->pidx; - descq->pidx = incr_pidx(descq->pidx, - desc_cnt, - descq->conf.rngsz); - descq->avail -= desc_cnt; - return 0; -} - -int qdma_q_init_pointers(void *q_hndl) -{ - struct qdma_descq *descq = (struct qdma_descq *)q_hndl; - int rv; - - if ((descq->conf.st && (descq->conf.q_type == Q_C2H)) || - (!descq->conf.st && (descq->conf.q_type == Q_CMPT))) { - if (descq->conf.init_pidx_dis) { - /* use qdma_q_init_pointers - *for updating the pidx and cidx later - */ - descq->cmpt_cidx_info.wrb_cidx = 0; - rv = queue_cmpt_cidx_update(descq->xdev, - descq->conf.qidx, - &descq->cmpt_cidx_info); - if (unlikely(rv < 0)) { - pr_err("%s: Failed to update cmpt cidx\n", - descq->conf.name); - return -EINVAL; - } - - if (descq->conf.q_type == Q_CMPT) - return 0; - - descq->pidx_info.pidx = descq->conf.rngsz - 1; - rv = queue_pidx_update(descq->xdev, descq->conf.qidx, - descq->conf.q_type, &descq->pidx_info); - if (unlikely(rv < 0)) { - pr_err("%s: Failed to update pidx\n", - descq->conf.name); - return -EINVAL; - } - } else { - pr_err("pidx disable is active"); - return -EINVAL; - } - } else { - pr_err("Invalid mode"); - return -EINVAL; - } - - return 0; -} - -int qdma_queue_update_pointers(unsigned long dev_hndl, unsigned long qhndl) -{ - struct xlnx_dma_dev *xdev = (struct xlnx_dma_dev *)dev_hndl; - struct qdma_descq *descq = qdma_device_get_descq_by_id(xdev, qhndl, - NULL, 0, 0); - int ret = 0; - - if (!descq) { - pr_err("%s descq is null\n", __func__); - return -EINVAL; - } - - if (descq->conf.st && (descq->conf.q_type == Q_C2H)) { - lock_descq(descq); - if (descq->q_state == Q_STATE_ONLINE) { - ret = queue_cmpt_cidx_update(descq->xdev, - descq->conf.qidx, - &descq->cmpt_cidx_info); - if (ret < 0) { - pr_err("%s: Failed to update cmpt cidx\n", - descq->conf.name); - - ret = -EBUSY; - goto func_exit; - } - ret = queue_pidx_update(descq->xdev, - descq->conf.qidx, - descq->conf.q_type, - &descq->pidx_info); - if (ret < 0) { - pr_err("%s: Failed to update pidx\n", - descq->conf.name); - ret = -EBUSY; - goto func_exit; - } - /* - * Memory barrier in update pointers - */ - wmb(); - } else { - pr_debug("Pointer update for offline queue for %s", - descq->conf.name); - ret = -ENODEV; - } - } else { - pr_err("Pointer update for invalid queue for %s", - descq->conf.name); - ret = -EINVAL; - } - -func_exit: - unlock_descq(descq); - return ret; - -} - -int qdma_descq_alloc_resource(struct qdma_descq *descq) -{ - struct xlnx_dma_dev *xdev = descq->xdev; - struct qdma_queue_conf *qconf = &descq->conf; - unsigned char is_ul_ext = (qconf->desc_bypass && - qconf->fp_bypass_desc_fill) ? 1 : 0; - int rv; -#ifdef TEST_64B_DESC_BYPASS_FEATURE - int i = 0; - u8 *desc_bypass; - u8 bypass_data[DESC_SZ_64B_BYTES]; -#endif - /* descriptor ring */ - if (descq->conf.q_type != Q_CMPT) { - descq->desc = desc_ring_alloc(xdev, descq->conf.rngsz, - get_desc_size(descq), - get_desc_cmpl_status_size(descq), - &descq->desc_bus, &descq->desc_cmpl_status); - if (!descq->desc) { - pr_err("dev %s, descq %s, sz %u, desc ring OOM.\n", - xdev->conf.name, descq->conf.name, - descq->conf.rngsz); - goto err_out; - } - } - - if (descq->conf.st && (descq->conf.q_type == Q_C2H)) { - struct qdma_flq *flq = (struct qdma_flq *)descq->flq; - - flq->desc = (struct qdma_c2h_desc *)descq->desc; - flq->size = descq->conf.rngsz; - flq->buf_pg_shift = fls(descq->conf.c2h_bufsz) - 1; - flq->buf_pg_mask = (1 << flq->buf_pg_shift) - 1; - - flq->desc_buf_size = get_next_powof2(descq->conf.c2h_bufsz); - flq->desc_pg_shift = fls(flq->desc_buf_size) - 1; - - /* These code changes are to accomodate buf_sz - * of less than 4096 - */ - - if (flq->desc_pg_shift < PAGE_SHIFT) - flq->desc_pg_order = 0; - else - flq->desc_pg_order = flq->desc_pg_shift - PAGE_SHIFT; - - flq->max_pg_offset = (PAGE_SIZE << flq->desc_pg_order); - - pr_debug("%s: buf_pg_shift = %d, buf_pg_mask = %d, desc_buf_size = %d, desc_pg_shift = %d, flq->desc_pg_order = %d, flq->max_pg_offset = %d", - descq->conf.name, - flq->buf_pg_shift, - flq->buf_pg_mask, - flq->desc_buf_size, - flq->desc_pg_shift, - flq->desc_pg_order, - flq->max_pg_offset); - - - /* freelist / rx buffers */ - rv = descq_flq_alloc_resource(descq); - if (rv < 0) { - pr_err("%s: resource allocation failed", - __func__); - goto err_out; - } - } else if (is_ul_ext) { - int i; - unsigned int desc_sz = get_desc_size(descq); - - descq->desc_list = kcalloc(descq->conf.rngsz, - sizeof(struct qdma_q_desc_list), - GFP_KERNEL); - if (!descq->desc_list) { - pr_err("desc_list allocation failed.OOM"); - goto err_out; - } - for (i = 0; i < descq->conf.rngsz; i++) { - int next = (i == (descq->conf.rngsz - 1)) ? 0 : (i + 1); - - descq->desc_list[i].desc = descq->desc + (i * desc_sz); - descq->desc_list[i].next = &descq->desc_list[next]; - } - } - - if ((descq->conf.st && (descq->conf.q_type == Q_C2H)) || - (!descq->conf.st && (descq->conf.q_type == Q_CMPT))) { - - descq->color = 1; - - /* writeback ring */ - descq->desc_cmpt = desc_ring_alloc(xdev, - descq->conf.rngsz_cmpt, - descq->cmpt_entry_len, - sizeof(struct - qdma_c2h_cmpt_cmpl_status), - &descq->desc_cmpt_bus, - &descq->desc_cmpt_cmpl_status); - if (!descq->desc_cmpt) { - pr_warn("dev %s, descq %s, sz %u, cmpt ring OOM.\n", - xdev->conf.name, descq->conf.name, - descq->conf.rngsz_cmpt); - goto err_out; - } - descq->desc_cmpt_cur = descq->desc_cmpt; - - } - - pr_debug("%s: %u/%u, rng %u,%u, desc 0x%p, cmpl status 0x%p.\n", - descq->conf.name, descq->conf.qidx, descq->qidx_hw, - descq->conf.rngsz, descq->conf.rngsz_cmpt, descq->desc, - descq->desc_cmpt); - - /* interrupt vectors */ - desc_alloc_irq(descq); - - /* Fill in the descriptors with some hard coded value for testing */ -#ifdef TEST_64B_DESC_BYPASS_FEATURE - desc_bypass = descq->desc; - if (descq->conf.st && (descq->conf.q_type == Q_H2C)) { - if (descq->conf.desc_bypass && - (descq->conf.sw_desc_sz == DESC_SZ_64B)) { - for (i = 0; i < descq->conf.rngsz; i++) { - memset(bypass_data, i+1, DESC_SZ_64B_BYTES); - memcpy(&desc_bypass[i*DESC_SZ_64B_BYTES], - bypass_data, DESC_SZ_64B_BYTES); - } - } - } -#endif - return 0; - -err_out: - qdma_descq_free_resource(descq); - pr_err("Out of Memory"); - return -ENOMEM; -} - -void qdma_descq_free_resource(struct qdma_descq *descq) -{ - if (!descq) - return; - - if (descq->desc) { - - int desc_sz = get_desc_size(descq); - int cs_sz = get_desc_cmpl_status_size(descq); - - pr_debug("%s: desc 0x%p, cmpt 0x%p.\n", - descq->conf.name, descq->desc, descq->desc_cmpt); - - if (descq->conf.st && (descq->conf.q_type == Q_C2H)) { - descq_flq_free_resource(descq); - descq_flq_free_page_resource(descq); - } else - kfree(descq->desc_list); - - desc_ring_free(descq->xdev, descq->conf.rngsz, desc_sz, cs_sz, - descq->desc, descq->desc_bus); - descq->desc_cmpl_status = NULL; - descq->desc = NULL; - descq->desc_bus = 0UL; - } - - if (descq->desc_cmpt) { - desc_ring_free(descq->xdev, descq->conf.rngsz_cmpt, - descq->cmpt_entry_len, - sizeof(struct qdma_c2h_cmpt_cmpl_status), - descq->desc_cmpt, descq->desc_cmpt_bus); - - descq->desc_cmpt_cmpl_status = NULL; - descq->desc_cmpt = NULL; - descq->desc_cmpt_bus = 0UL; - } -} - -void qdma_descq_config(struct qdma_descq *descq, struct qdma_queue_conf *qconf, - int reconfig) -{ - if (!reconfig) { - int len; - - memcpy(&descq->conf, qconf, sizeof(struct qdma_queue_conf)); - /* descq->conf.st = qconf->st; - * descq->conf.c2h = qconf->c2h; - */ - - /* qdma[vf]<255>-MM/ST-H2C/C2H-Q[2048] */ -#ifdef __QDMA_VF__ - len = snprintf(descq->conf.name, QDMA_QUEUE_NAME_MAXLEN, - "qdmavf"); -#else - len = snprintf(descq->conf.name, QDMA_QUEUE_NAME_MAXLEN, - "qdma"); -#endif - len += snprintf(descq->conf.name + len, - QDMA_QUEUE_NAME_MAXLEN - len, - "%05x-%s-%u", - descq->xdev->conf.bdf, descq->conf.st ? "ST" : "MM", - descq->conf.qidx); - descq->conf.name[len] = '\0'; - - descq->conf.st = qconf->st; - descq->conf.q_type = qconf->q_type; - - } else { - descq->conf.desc_rng_sz_idx = qconf->desc_rng_sz_idx; - descq->conf.cmpl_rng_sz_idx = qconf->cmpl_rng_sz_idx; - descq->conf.c2h_buf_sz_idx = qconf->c2h_buf_sz_idx; - - descq->conf.irq_en = (descq->xdev->conf.qdma_drv_mode != - POLL_MODE) ? 1 : 0; - descq->conf.cmpl_en_intr = descq->conf.irq_en; - descq->conf.wb_status_en = qconf->wb_status_en; - descq->conf.cmpl_status_acc_en = qconf->cmpl_status_acc_en; - descq->conf.cmpl_status_pend_chk = qconf->cmpl_status_pend_chk; - descq->conf.cmpl_stat_en = qconf->cmpl_stat_en; - descq->conf.cmpl_trig_mode = qconf->cmpl_trig_mode; - descq->conf.cmpl_timer_idx = qconf->cmpl_timer_idx; - descq->conf.fetch_credit = qconf->fetch_credit; - descq->conf.cmpl_cnt_th_idx = qconf->cmpl_cnt_th_idx; - /* Below check is applicable only for Versal family. */ - if (descq->xdev->version_info.ip_type == QDMA_VERSAL_HARD_IP) - descq->channel = qconf->mm_channel; - - descq->conf.desc_bypass = qconf->desc_bypass; - descq->conf.pfetch_bypass = qconf->pfetch_bypass; - descq->conf.pfetch_en = qconf->pfetch_en; - descq->conf.cmpl_udd_en = qconf->cmpl_udd_en; - descq->conf.cmpl_desc_sz = qconf->cmpl_desc_sz; - descq->conf.sw_desc_sz = qconf->sw_desc_sz; - descq->conf.cmpl_ovf_chk_dis = qconf->cmpl_ovf_chk_dis; - descq->conf.adaptive_rx = qconf->adaptive_rx; - descq->conf.ping_pong_en = qconf->ping_pong_en; - descq->conf.aperture_size = qconf->aperture_size; - descq->conf.pidx_acc = qconf->pidx_acc; - } -} - -int qdma_descq_config_complete(struct qdma_descq *descq) -{ - struct global_csr_conf *csr_info = &descq->xdev->csr_info; - struct qdma_queue_conf *qconf = &descq->conf; - struct xlnx_dma_dev *xdev = descq->xdev; - - qconf->rngsz = csr_info->ring_sz[qconf->desc_rng_sz_idx] - 1; - - /* <= 2018.2 IP - * make the cmpl ring size bigger if possible to avoid run out of - * cmpl entry while desc. ring still have free entries - */ - if ((qconf->st && (qconf->q_type == Q_C2H)) || - (!qconf->st && (qconf->q_type == Q_CMPT))) { - int i; - unsigned int v = csr_info->ring_sz[qconf->cmpl_rng_sz_idx]; - int best_fit_idx = -1; - - for (i = 0; i < QDMA_GLOBAL_CSR_ARRAY_SZ; i++) { - if (csr_info->ring_sz[i] > v) { - if (best_fit_idx < 0) - best_fit_idx = i; - else if ((best_fit_idx >= 0) && - (csr_info->ring_sz[i] < - csr_info->ring_sz[best_fit_idx])) - best_fit_idx = i; - } - } - - if (best_fit_idx >= 0) - qconf->cmpl_rng_sz_idx = best_fit_idx; - - qconf->rngsz_cmpt = csr_info->ring_sz[qconf->cmpl_rng_sz_idx] - - 1; - qconf->c2h_bufsz = csr_info->c2h_buf_sz[qconf->c2h_buf_sz_idx]; - descq->cmpt_cidx_info.irq_en = qconf->cmpl_en_intr; - descq->cmpt_cidx_info.trig_mode = qconf->cmpl_trig_mode; - descq->cmpt_cidx_info.timer_idx = qconf->cmpl_timer_idx; - descq->cmpt_cidx_info.counter_idx = qconf->cmpl_cnt_th_idx; - descq->cmpt_cidx_info.wrb_en = qconf->cmpl_stat_en; - } - if (qconf->st && (qconf->q_type == Q_C2H)) - descq->pidx_info.irq_en = 0; - else - descq->pidx_info.irq_en = descq->conf.irq_en; - - /* we can never use the full ring because then cidx would equal pidx - * and thus the ring would be interpreted as empty. Thus max number of - * usable entries is ring_size - 1 - */ - descq->avail = descq->conf.rngsz - 1; - descq->pend_list_empty = 1; - - descq->pidx = 0; - descq->cidx = 0; - descq->cidx_cmpt = 0; - descq->pidx_cmpt = 0; - descq->credit = 0; - descq->work_req_pend = 0; - - /* ST C2H only */ - if ((qconf->st && (qconf->q_type == Q_C2H)) || - (!qconf->st && (qconf->q_type == Q_CMPT))) { - int i, hi_idx, low_idx; - - descq->cmpt_entry_len = 8 << qconf->cmpl_desc_sz; - - pr_debug("%s: cmpl sz %u(%d), udd_en %d.\n", - descq->conf.name, descq->cmpt_entry_len, - descq->conf.cmpl_desc_sz, descq->conf.cmpl_udd_en); - descq->c2h_pend_pkt_moving_avg = - csr_info->c2h_cnt_th[descq->conf.cmpl_cnt_th_idx]; - for (i = 0; i < QDMA_GLOBAL_CSR_ARRAY_SZ; i++) { - if (descq->conf.cmpl_cnt_th_idx == - descq->xdev->sorted_c2h_cntr_idx[i]) { - descq->sorted_c2h_cntr_idx = i; - break; - } - } - hi_idx = descq->sorted_c2h_cntr_idx + 1; - low_idx = descq->sorted_c2h_cntr_idx - 1; - - if (descq->sorted_c2h_cntr_idx == - (QDMA_GLOBAL_CSR_ARRAY_SZ - 1)) - hi_idx = descq->sorted_c2h_cntr_idx; - - i = xdev->sorted_c2h_cntr_idx[hi_idx]; - - descq->c2h_pend_pkt_avg_thr_hi = - (descq->c2h_pend_pkt_moving_avg + - csr_info->c2h_cnt_th[i]); - if (descq->sorted_c2h_cntr_idx == 0) - low_idx = 0; - - i = xdev->sorted_c2h_cntr_idx[low_idx]; - - descq->c2h_pend_pkt_avg_thr_lo = - (descq->c2h_pend_pkt_moving_avg + - csr_info->c2h_cnt_th[i]); - descq->c2h_pend_pkt_avg_thr_hi >>= 1; - descq->c2h_pend_pkt_avg_thr_lo >>= 1; - pr_debug("q%u: sorted idx = %u %u %u", descq->conf.qidx, - descq->sorted_c2h_cntr_idx, - descq->c2h_pend_pkt_avg_thr_lo, - descq->c2h_pend_pkt_avg_thr_hi); - } - - return 0; -} - -int qdma_descq_prog_hw(struct qdma_descq *descq) -{ - int rv = qdma_descq_context_setup(descq); - - if (rv < 0) { - pr_warn("%s failed to program contexts", descq->conf.name); - return rv; - } - - /* update pidx/cidx */ - if ((descq->conf.st && (descq->conf.q_type == Q_C2H)) || - (!descq->conf.st && (descq->conf.q_type == Q_CMPT))) { - if (!descq->conf.init_pidx_dis) { - /* use qdma_q_init_pointers - * for updating the pidx and cidx later - */ - descq->cmpt_cidx_info.wrb_cidx = 0; - rv = queue_cmpt_cidx_update(descq->xdev, - descq->conf.qidx, - &descq->cmpt_cidx_info); - if (unlikely(rv < 0)) { - pr_err("%s: Failed to update cmpt cidx\n", - descq->conf.name); - return -EINVAL; - } - - if (descq->conf.q_type == Q_CMPT) - return rv; - - descq->pidx_info.pidx = descq->conf.rngsz - 1; - rv = queue_pidx_update(descq->xdev, descq->conf.qidx, - descq->conf.q_type, &descq->pidx_info); - if (unlikely(rv < 0)) { - pr_err("%s: Failed to update pidx\n", - descq->conf.name); - return -EINVAL; - } - } - } - - return rv; -} - -int qdma_descq_service_cmpl_update(struct qdma_descq *descq, int budget, - bool c2h_upd_cmpl) -{ - int rv = 0; - - if (descq->conf.st && (descq->conf.q_type == Q_C2H)) { - lock_descq(descq); - if (descq->q_state == Q_STATE_ONLINE) { - rv = descq_process_completion_st_c2h(descq, budget, - c2h_upd_cmpl); - if (rv && (rv != -ENODATA)) - pr_err("Error detected in %s", - descq->conf.name); - } else { - pr_debug("Invalid q state of %s ", descq->conf.name); - rv = -EINVAL; - } - unlock_descq(descq); - } else if ((descq->xdev->conf.qdma_drv_mode == POLL_MODE) || - (descq->xdev->conf.qdma_drv_mode == AUTO_MODE)) { - lock_descq(descq); - if (!descq->proc_req_running) { - unlock_descq(descq); - qdma_descq_proc_sgt_request(descq); - } else { - pr_err("Processing previous request\n"); - unlock_descq(descq); - } - } else { - lock_descq(descq); - descq_mm_n_h2c_cmpl_status(descq); - if (qdma_work_queue_len(descq) || descq->desc_pend) { - unlock_descq(descq); - rv = qdma_descq_proc_sgt_request(descq); - return rv; - } - unlock_descq(descq); - } - - return rv; -} - -ssize_t qdma_descq_proc_sgt_request(struct qdma_descq *descq) -{ - if (!descq->conf.st) /* MM H2C/C2H */ - return descq_mm_proc_request(descq); - else if (descq->conf.st && (descq->conf.q_type == Q_H2C)) {/* ST H2C */ - if (descq->conf.fp_bypass_desc_fill && - descq->conf.desc_bypass && - descq->xdev->conf.qdma_drv_mode == DIRECT_INTR_MODE) - return descq_proc_st_h2c_request_qep(descq); - return descq_proc_st_h2c_request(descq); - } else /* ST C2H - should not happen - handled separately */ - return -EINVAL; -} - -void incr_cmpl_desc_cnt(struct qdma_descq *descq, unsigned int cnt) -{ - descq->total_cmpl_descs += cnt; - switch ((descq->conf.st << 1) | descq->conf.q_type) { - case 0: - descq->xdev->total_mm_h2c_pkts += cnt; - break; - case 1: - descq->xdev->total_mm_c2h_pkts += cnt; - break; - case 2: - descq->xdev->total_st_h2c_pkts += cnt; - break; - case 3: - descq->xdev->total_st_c2h_pkts += cnt; - break; - default: - break; - } -} - -void qdma_sgt_req_done(struct qdma_descq *descq, struct qdma_sgt_req_cb *cb, - int error) -{ - struct qdma_request *req = (struct qdma_request *)cb; - - if (unlikely(error)) - pr_err("req 0x%p, cb 0x%p, fp_done 0x%p done, err %d.\n", - req, cb, req->fp_done, error); - - list_del(&cb->list); - if (cb->unmap_needed) { - sgl_unmap(descq->xdev->conf.pdev, req->sgl, req->sgcnt, - (descq->conf.q_type == Q_C2H) ? - DMA_FROM_DEVICE : DMA_TO_DEVICE); - cb->unmap_needed = 0; - } - if (req->fp_done) { - if ((cb->offset != req->count) && - !(descq->conf.st && - (descq->conf.q_type == Q_C2H))) { - pr_info("req 0x%p not completed %u != %u.\n", - req, cb->offset, req->count); - error = -EINVAL; - } - cb->status = error; - cb->done = 1; - req->fp_done(req, cb->offset, error); - } else { - pr_debug("req 0x%p, cb 0x%p, wake up.\n", req, cb); - cb->status = error; - cb->done = 1; - qdma_waitq_wakeup(&cb->wq); - } - - if (!descq->conf.fp_descq_c2h_packet) { - if (descq->conf.st && (descq->conf.q_type == Q_C2H)) - descq->pend_list_empty = (descq->avail == 0); - else - descq->pend_list_empty = (descq->avail == - (descq->conf.rngsz - 1)); - - if (descq->q_stop_wait && descq->pend_list_empty) - qdma_waitq_wakeup(&descq->pend_list_wq); - } else - descq->pend_list_empty = 1; -} - -int qdma_descq_dump_desc(struct qdma_descq *descq, int start, - int end, char *buf, int buflen) -{ - struct qdma_flq *flq = (struct qdma_flq *)descq->flq; - int desc_sz = get_desc_size(descq); - u8 *p = descq->desc + start * desc_sz; - struct qdma_sw_sg *fl = (descq->conf.st && - (descq->conf.q_type == Q_C2H)) ? - flq->sdesc + start : NULL; - int i = start; - int len = strlen(buf); - - if (!descq->desc) - return 0; - - for (; i < end && i < descq->conf.rngsz; i++, p += desc_sz) { - len += snprintf(buf + len, buflen - len, - "%d: 0x%p ", i, p); - hex_dump_to_buffer(p, desc_sz, - (desc_sz < DESC_SZ_16B_BYTES) ? 16 : 32, - 4, buf + len, buflen - len, 0); - len = strlen(buf); - if (desc_sz > DESC_SZ_32B_BYTES) { - len += snprintf(buf + len, buflen - len, " "); - hex_dump_to_buffer(p + DESC_SZ_32B_BYTES, desc_sz, - 32, 4, buf + len, buflen - len, 0); - len = strlen(buf); - } - if (fl) { - len += snprintf(buf + len, buflen - len, - " fl pg 0x%p, 0x%llx.\n", - fl->pg, fl->dma_addr); - fl++; - } else - buf[len++] = '\n'; - } - - p = descq->desc_cmpl_status; - - dma_rmb(); - - len += snprintf(buf + len, buflen - len, "CMPL STATUS: 0x%p ", p); - hex_dump_to_buffer(p, get_desc_cmpl_status_size(descq), 16, 4, - buf + len, buflen - len, 0); - len = strlen(buf); - buf[len++] = '\n'; - - if (descq->conf.st && (descq->conf.q_type == Q_C2H)) { - p = page_address(fl->pg); - len += snprintf(buf + len, buflen - len, "data 0: 0x%p ", p); - hex_dump_to_buffer(p, descq->cmpt_entry_len, - (descq->cmpt_entry_len < DESC_SZ_16B_BYTES) ? 16 : 32, - 4, buf + len, - buflen - len, 0); - len = strlen(buf); - if (descq->cmpt_entry_len > DESC_SZ_32B_BYTES) { - len += snprintf(buf + len, buflen - len, " "); - hex_dump_to_buffer(p + DESC_SZ_32B_BYTES, - descq->cmpt_entry_len, 32, 4, - buf + len, buflen - len, 0); - len = strlen(buf); - } - buf[len++] = '\n'; - } - - return len; -} - -int qdma_descq_dump_cmpt(struct qdma_descq *descq, int start, - int end, char *buf, int buflen) -{ - uint8_t *cmpt = descq->desc_cmpt; - u8 *p; - int i = start; - int len = strlen(buf); - int stride = descq->cmpt_entry_len; - - if (!descq->desc_cmpt) - return 0; - - for (cmpt += (start * stride); - i < end && i < descq->conf.rngsz_cmpt; i++, - cmpt += stride) { - len += snprintf(buf + len, buflen - len, - "%d: 0x%p ", i, cmpt); - hex_dump_to_buffer(cmpt, descq->cmpt_entry_len, - 32, 4, buf + len, buflen - len, 0); - len = strlen(buf); - if (descq->cmpt_entry_len > DESC_SZ_32B_BYTES) { - len += snprintf(buf + len, buflen - len, - " "); - hex_dump_to_buffer(cmpt + DESC_SZ_32B_BYTES, - descq->cmpt_entry_len, - 32, 4, buf + len, buflen - len, 0); - len = strlen(buf); - } - buf[len++] = '\n'; - } - - len += snprintf(buf + len, buflen - len, - "CMPL STATUS: 0x%p ", - descq->desc_cmpt_cmpl_status); - - p = descq->desc_cmpt_cmpl_status; - dma_rmb(); - hex_dump_to_buffer(p, sizeof(struct qdma_c2h_cmpt_cmpl_status), - 16, 4, buf + len, buflen - len, 0); - len = strlen(buf); - buf[len++] = '\n'; - - return len; -} - -int qdma_descq_dump_state(struct qdma_descq *descq, char *buf, int buflen) -{ - char *cur = buf; - char *const end = buf + buflen; - - if (!buf || !buflen) { - pr_warn("incorrect arguments buf=%p buflen=%d", buf, buflen); - return 0; - } - - if (descq->conf.q_type != Q_CMPT) - cur += snprintf(cur, end - cur, "%s %s ", - descq->conf.name, - (descq->conf.q_type == Q_C2H) ? "C2H" : "H2C"); - else - cur += snprintf(cur, end - cur, "%s %s ", - descq->conf.name, "CMPT"); - if (cur >= end) - goto handle_truncation; - - if (descq->err) - cur += snprintf(cur, end - cur, "ERR\n"); - else - cur += snprintf(cur, end - cur, "%s\n", - q_state_list[descq->q_state].name); - - if (cur >= end) - goto handle_truncation; - - return cur - buf; - -handle_truncation: - *buf = '\0'; - return cur - buf; -} - -int qdma_descq_dump(struct qdma_descq *descq, char *buf, int buflen, int detail) -{ - char *cur = buf; - char *const end = buf + buflen; - - if (!buf || !buflen) { - pr_info("%s:%s 0x%x/0x%x, desc sz %u/%u, pidx %u, cidx %u\n", - descq->conf.name, descq->err ? "ERR" : "", - descq->conf.qidx, descq->qidx_hw, descq->conf.rngsz, - descq->avail, descq->pidx, descq->cidx); - return 0; - } - - cur += qdma_descq_dump_state(descq, cur, end - cur); - if (cur >= end) - goto handle_truncation; - - if (descq->q_state == Q_STATE_DISABLED) - return cur - buf; - - cur += snprintf(cur, end - cur, - "\thw_ID %u, thp %s, desc 0x%p/0x%llx, %u\n", - descq->qidx_hw, - descq->cmplthp ? descq->cmplthp->name : "?", - descq->desc, descq->desc_bus, descq->conf.rngsz); - if (cur >= end) - goto handle_truncation; - - if (descq->conf.st && (descq->conf.q_type == Q_C2H)) { - cur += snprintf(cur, end - cur, - "\tcmpt desc 0x%p/0x%llx, %u\n", - descq->desc_cmpt, descq->desc_cmpt_bus, - descq->conf.rngsz_cmpt); - if (cur >= end) - goto handle_truncation; - } - - if (!detail) - return cur - buf; - - if (descq->desc_cmpl_status) { - u8 *cs = descq->desc_cmpl_status; - - cur += snprintf(cur, end - cur, "\n\tcmpl status: 0x%p, ", cs); - if (cur >= end) - goto handle_truncation; - - dma_rmb(); -#if KERNEL_VERSION(4, 0, 0) <= LINUX_VERSION_CODE - cur += hex_dump_to_buffer(cs, - sizeof(struct qdma_desc_cmpl_status), - 16, 4, cur, end - cur, 0); -#else - hex_dump_to_buffer(cs, sizeof(struct qdma_desc_cmpl_status), - 16, 4, cur, end - cur, 0); - cur += strlen(cur); -#endif - if (cur >= end) - goto handle_truncation; - - cur += snprintf(cur, end - cur, "\n"); - if (cur >= end) - goto handle_truncation; - } - if (descq->desc_cmpt_cmpl_status) { - u8 *cs = descq->desc_cmpt_cmpl_status; - - cur += snprintf(cur, end - cur, "\tCMPT CMPL STATUS: 0x%p, ", - cs); - if (cur >= end) - goto handle_truncation; - - dma_rmb(); -#if KERNEL_VERSION(4, 0, 0) <= LINUX_VERSION_CODE - cur += hex_dump_to_buffer(cs, - sizeof(struct qdma_c2h_cmpt_cmpl_status), - 16, 4, cur, end - cur, 0); -#else - hex_dump_to_buffer(cs, sizeof(struct qdma_c2h_cmpt_cmpl_status), - 16, 4, cur, end - cur, 0); - cur += strlen(cur); -#endif - if (cur >= end) - goto handle_truncation; - - cur += snprintf(cur, end - cur, "\n"); - if (cur >= end) - goto handle_truncation; - } - - return cur - buf; - -handle_truncation: - *buf = '\0'; - return cur - buf; -} - -int qdma_queue_avail_desc(unsigned long dev_hndl, unsigned long id) -{ - struct qdma_descq *descq = qdma_device_get_descq_by_id( - (struct xlnx_dma_dev *)dev_hndl, - id, NULL, 0, 1); - int avail; - - if (!descq) { - pr_err("Invalid qid: %ld", id); - return -EINVAL; - } - - lock_descq(descq); - avail = descq->avail; - unlock_descq(descq); - - return avail; -} - -#ifdef ERR_DEBUG -int qdma_queue_set_err_induction(unsigned long dev_hndl, unsigned long id, - u32 err, char *buf, int buflen) -{ - struct qdma_descq *descq = qdma_device_get_descq_by_id( - (struct xlnx_dma_dev *)dev_hndl, - id, buf, buflen, 1); - unsigned int err_en = (err >> 31); - unsigned int err_no = (err & 0x7FFFFFFF); - - if (!descq) { - pr_err("Invalid qid: %ld", id); - return -EINVAL; - } - - if (err_no < sb_mi_h2c0_dat) { - descq->induce_err &= ~(1 << err_no); - descq->induce_err |= (err_en << err_no); - } else { - descq->ecc_err &= ~(1 << (err_no - sb_mi_h2c0_dat)); - descq->ecc_err |= (err_en << (err_no - sb_mi_h2c0_dat)); - } - pr_info("Errs enabled = [QDMA]: 0x%08x 0x%08x\n [ECC]: 0x%08x 0x%08x", - (u32)(descq->induce_err >> 32), - (u32)(descq->induce_err & 0xFFFFFFFF), - (u32)(descq->ecc_err >> 32), - (u32)(descq->ecc_err & 0xFFFFFFFF)); - - return 0; -} -#endif - -int qdma_queue_packet_write(unsigned long dev_hndl, unsigned long id, - struct qdma_request *req) -{ - struct xlnx_dma_dev *xdev = (struct xlnx_dma_dev *)dev_hndl; - struct qdma_descq *descq; - struct qdma_sgt_req_cb *cb; - int rv; - - /** make sure that the dev_hndl passed is Valid */ - if (unlikely(!xdev)) { - pr_err("dev_hndl is NULL"); - return -EINVAL; - } - - if (unlikely(xdev_check_hndl(__func__, - xdev->conf.pdev, dev_hndl) < 0)) { - pr_err("Invalid dev_hndl passed"); - return -EINVAL; - } - - if (unlikely(!req)) { - pr_err("req is NULL"); - return -EINVAL; - } - - cb = qdma_req_cb_get(req); - - descq = qdma_device_get_descq_by_id(xdev, id, NULL, 0, 0); - if (unlikely(!descq)) { - pr_err("Invalid qid: %ld", id); - return -EINVAL; - } - - if (unlikely(!descq->conf.st || (descq->conf.q_type == Q_C2H))) { - pr_err("%s: st %d, type %d.\n", - descq->conf.name, descq->conf.st, descq->conf.q_type); - return -EINVAL; - } - - memset(cb, 0, QDMA_REQ_OPAQUE_SIZE); - qdma_waitq_init(&cb->wq); - qdma_work_queue_add(descq, cb); - - if (!req->dma_mapped) { - rv = sgl_map(descq->xdev->conf.pdev, req->sgl, req->sgcnt, - DMA_TO_DEVICE); - if (rv < 0) { - pr_err("%s map sgl %u failed, %u.\n", - descq->conf.name, req->sgcnt, req->count); - goto unmap_sgl; - } - cb->unmap_needed = 1; - } - - if (!req->check_qstate_disabled) { - lock_descq(descq); - if (descq->q_state != Q_STATE_ONLINE) { - unlock_descq(descq); - pr_err("%s descq %s NOT online.\n", - descq->xdev->conf.name, descq->conf.name); - rv = -EINVAL; - goto unmap_sgl; - } - unlock_descq(descq); - } - - qdma_descq_proc_sgt_request(descq); - - - pr_debug("%s: cb 0x%p submitted for bytes %u.\n", - descq->conf.name, cb, req->count); - - return req->count; - -unmap_sgl: - if (cb->unmap_needed) - sgl_unmap(descq->xdev->conf.pdev, req->sgl, req->sgcnt, - DMA_TO_DEVICE); - return rv; -} - -int qdma_descq_get_cmpt_udd(unsigned long dev_hndl, unsigned long id, - char *buf, int buflen) -{ - uint8_t *cmpt; - uint8_t i = 0; - int len = 0; - int print_len = 0; - struct xlnx_dma_dev *xdev = (struct xlnx_dma_dev *)dev_hndl; - struct qdma_descq *descq = NULL; - struct qdma_c2h_cmpt_cmpl_status *cs; - - if (!buf || !buflen || !xdev) { - pr_err("Invalid bud:%p, buflen:%d", buf, buflen); - return -EINVAL; - } - - - descq = qdma_device_get_descq_by_id(xdev, id, buf, buflen, 1); - - if (!descq) { - pr_err("Invalid qid: %ld", id); - return -EINVAL; - } - - cs = (struct qdma_c2h_cmpt_cmpl_status *) - descq->desc_cmpt_cmpl_status; - - cmpt = descq->desc_cmpt + ((cs->pidx - 1) * descq->cmpt_entry_len); - - /* - * Ignoring the first 4 bits of the completion entry as they represent - * the error and color bits. - * TODO: May need to change the masking logic and move that in thegtest, - * as error and color bit positions may change in the future releases. - */ - for (i = 0; i < descq->cmpt_entry_len; i++) { - if (buf && buflen) { - if ((xdev->version_info.ip_type == QDMA_VERSAL_HARD_IP) - && xdev->version_info.device_type == - QDMA_DEVICE_VERSAL_CPM4) { - if (i <= 1) - continue; - else if (i == 2) - print_len = snprintf(buf + len, buflen, - "%02x", - (0xF0 & cmpt[i])); - else - print_len = snprintf(buf + len, buflen, - "%02x", - cmpt[i]); - } else { - if (i == 0) - print_len = snprintf(buf + len, buflen, - "%02x", - (cmpt[i] & 0xF0)); - else - print_len = snprintf(buf + len, buflen, - "%02x", - cmpt[i]); - } - - } - buflen -= print_len; - len += print_len; - } - buf[len] = '\0'; - - return 0; -} - -static int qdma_descq_read_cmpt(struct qdma_descq *descq, - u32 num_entries, u8 *cmpt_data) -{ - uint8_t *cmpt; - int i = 0; - int stride = descq->cmpt_entry_len; - u8 *temp = cmpt_data; - - if (!descq->desc_cmpt) - return 0; - - lock_descq(descq); - cmpt = descq->desc_cmpt + (descq->cidx_cmpt * stride); - for (i = 0; i < num_entries; - i++, cmpt += stride, cmpt_data += stride) { - memcpy(cmpt_data, cmpt, stride); - } - *(temp) = (*(temp) & 0xF0); - unlock_descq(descq); - - return i; -} - -int qdma_descq_read_cmpt_data(unsigned long dev_hndl, unsigned long id, - u32 *num_entries, u8 **cmpt_entries, - char *buf, int buflen) -{ - struct qdma_descq *descq = qdma_device_get_descq_by_id( - (struct xlnx_dma_dev *)dev_hndl, - id, buf, buflen, 1); - struct qdma_c2h_cmpt_cmpl_status *cs = NULL; - unsigned int pidx_cmpt = 0; - unsigned int cidx_cmpt = 0; - int rv = 0; - u32 pend = 0; - - if (!descq) { - pr_err("Invalid qid, qid = %ld", id); - return -EINVAL; - } - - if (!buf || !buflen) { - pr_err("Invalid buf:%p, buflen:%d", buf, buflen); - return -EINVAL; - } - - if (descq->conf.st) { - pr_err("Not supported for ST mode"); - rv = -EINVAL; - return rv; - } - - lock_descq(descq); - cs = (struct qdma_c2h_cmpt_cmpl_status *) - descq->desc_cmpt_cmpl_status; - cidx_cmpt = descq->cidx_cmpt; - pidx_cmpt = cs->pidx; - unlock_descq(descq); - pend = ring_idx_delta(pidx_cmpt, - cidx_cmpt, - descq->conf.rngsz_cmpt); - pr_debug("ringsz %d, pend = %d, cs->pidx = %d cs->cidx = %d, descq->cidx_cmpt = %d, descq->pidx_cmpt = %d", - descq->conf.rngsz_cmpt, pend, cs->pidx, cs->cidx, - cidx_cmpt, - pidx_cmpt); - *num_entries = min(pend, descq->conf.rngsz_cmpt); - - if (!pend) { - int l = 0; - - pr_debug("No pending cmpt entries"); - /* SW work around where next interrupt could be missed when - * there are no entries as of now - */ - if (descq->xdev->conf.qdma_drv_mode != POLL_MODE) { - lock_descq(descq); - descq->cmpt_cidx_info.wrb_cidx = cidx_cmpt; - unlock_descq(descq); - rv = queue_cmpt_cidx_update(descq->xdev, - descq->conf.qidx, - &descq->cmpt_cidx_info); - if (unlikely(rv < 0)) { - pr_err("%s: Failed to update cmpt cidx\n", - descq->conf.name); - return -EINVAL; - } - - } - - l = strlen(buf); - - l += snprintf(buf + l, buflen, - "%s no pending entries in cmpt ring\n", - descq->conf.name); - buf[l] = '\0'; - *num_entries = 0; - return 0; - } - - if (*num_entries > 0) { - /** Note: cmpt_entries will be freed by caller in nl.c - * do not free it here - */ - *cmpt_entries = kzalloc((*num_entries * descq->cmpt_entry_len), - GFP_KERNEL); - if (!*cmpt_entries) { - int l = snprintf(buf, buflen, "OOM for cmpt_entries\n"); - - buf[l] = '\0'; - *num_entries = 0; - return 0; - } - - qdma_descq_read_cmpt(descq, *num_entries, *cmpt_entries); - lock_descq(descq); - descq->cidx_cmpt += *num_entries; - descq->cmpt_cidx_info.wrb_cidx = descq->cidx_cmpt; - unlock_descq(descq); - rv = queue_cmpt_cidx_update(descq->xdev, - descq->conf.qidx, - &descq->cmpt_cidx_info); - if (unlikely(rv < 0)) { - pr_err("%s: Failed to update cmpt cidx\n", - descq->conf.name); - return -EINVAL; - } - } - - return rv; -} diff --git a/QDMA/linux-kernel/driver/libqdma/qdma_descq.h b/QDMA/linux-kernel/driver/libqdma/qdma_descq.h deleted file mode 100755 index bb1ba3611..000000000 --- a/QDMA/linux-kernel/driver/libqdma/qdma_descq.h +++ /dev/null @@ -1,613 +0,0 @@ -/* - * This file is part of the Xilinx DMA IP Core driver for Linux - * - * Copyright (c) 2017-2022, Xilinx, Inc. All rights reserved. - * Copyright (c) 2022, Advanced Micro Devices, Inc. All rights reserved. - * - * This source code is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * The full GNU General Public License is included in this distribution in - * the file called "COPYING". - */ - -#ifndef __QDMA_DESCQ_H__ -#define __QDMA_DESCQ_H__ -/** - * @file - * @brief This file contains the declarations for qdma descq processing - * - */ -#include -#include -#include "qdma_compat.h" -#include "libqdma_export.h" -#include "qdma_regs.h" -#ifdef ERR_DEBUG -#include "qdma_nl.h" -#endif -#include "qdma_ul_ext.h" - -/** - * struct q_state_name - Structure to hold the q state and name - * - * A queue can be in one of these states - * - */ -struct q_state_name { - /** @q_state : Current state of the queue. */ - enum q_state_t q_state; - /** @state : Q state Name */ - char name[20]; -}; - -extern struct q_state_name q_state_list[]; - -#define QDMA_FLQ_SIZE 124 - -/** - * @struct - qdma_descq - * @brief qdma software descriptor book keeping fields - */ -struct qdma_descq { - /** qdma queue configuration */ - struct qdma_queue_conf conf; - /** lock to protect access to software descriptor */ - spinlock_t lock; - /** pointer to dma device */ - struct xlnx_dma_dev *xdev; - /** number of channels */ - u8 channel; - /** flag to indicate error on the Q, in halted state */ - u8 err:1; - /** color bit for the queue */ - u8 color:1; - /** cpu attached */ - u8 cpu_assigned:1; - /** state of the proc req */ - u8 proc_req_running; - /* rx_time in CPU timestamp of ping_pong pkt for - * measuring H2C-C2H loopback latency - */ - u64 ping_pong_rx_time; - /* tx_time in CPU timestamp of ping_pong pkt for - * measuring H2C-C2H loopback latency - */ - u64 ping_pong_tx_time; - /** Indicate q state */ - enum q_state_t q_state; - /** hw qidx associated for this queue */ - unsigned int qidx_hw; - /** cpu attached to intr_work */ - unsigned int intr_work_cpu; - /** @q_hndl: Q handle */ - unsigned long q_hndl; - /** queue handler */ - struct work_struct work; - /** interrupt list */ - struct list_head intr_list; - /** leagcy interrupt list */ - struct list_head legacy_intr_q_list; - /** interrupt id associated for this queue */ - int intr_id; - /** work list for the queue */ - struct list_head work_list; - /** current req count */ - unsigned int work_req_pend; - /* lock to synchonize work queue access*/ - spinlock_t work_list_lock; - /** write back therad list */ - struct qdma_kthread *cmplthp; - /** completion status thread list for the queue */ - struct list_head cmplthp_list; - /** pending qork thread list */ - struct list_head pend_list; - /** wait queue for pending list clear */ - qdma_wait_queue pend_list_wq; - /** pending list empty count */ - unsigned int pend_list_empty; - /* flag to indicate wwaiting for transfers to complete before q stop*/ - unsigned int q_stop_wait; - /** availed count */ - unsigned int avail; - /** current req count */ - unsigned int pend_req_desc; - /** current producer index */ - unsigned int pidx; - /** current consumer index */ - unsigned int cidx; - /** number of descrtors yet to be processed*/ - unsigned int credit; - /** desctor to be processed*/ - u8 *desc; - /** desctor dma address*/ - dma_addr_t desc_bus; - /** desctor writeback*/ - u8 *desc_cmpl_status; - - /* ST C2H */ - /** programming order of the data in ST c2h mode*/ - unsigned char fl_pg_order; - /** cmpt entry length*/ - unsigned char cmpt_entry_len; - /** 2 bits reserved*/ - unsigned char rsvd[2]; - /** qdma free list q*/ - unsigned char flq[QDMA_FLQ_SIZE]; - /**total # of udd outstanding */ - unsigned int udd_cnt; - /** packet count/number of packets to be processed*/ - unsigned int pkt_cnt; - /** packet data length */ - unsigned int pkt_dlen; - /** pidx of the completion entry */ - unsigned int pidx_cmpt; - /** completion cidx */ - unsigned int cidx_cmpt; - /** number of packets processed in q */ - unsigned long long total_cmpl_descs; - /** descriptor writeback, data type depends on the cmpt_entry_len */ - void *desc_cmpt_cur; - /* descriptor list to be provided for ul extenstion call */ - struct qdma_q_desc_list *desc_list; - /** pointer to completion entry */ - u8 *desc_cmpt; - /** descriptor dma bus address*/ - dma_addr_t desc_cmpt_bus; - /** descriptor writeback dma bus address*/ - u8 *desc_cmpt_cmpl_status; - /** @desc_pend: pending desc to be updated processed by hw */ - unsigned char desc_pend; - /** pidx info to be written to PIDX regiser*/ - struct qdma_q_pidx_reg_info pidx_info; - /** cmpt cidx info to be written to CMPT CIDX regiser*/ - struct qdma_q_cmpt_cidx_reg_info cmpt_cidx_info; - /** @c2h_pend_pkt_moving_avg: average rate of packets received */ - unsigned int c2h_pend_pkt_moving_avg; - /** @c2h_pend_pkt_avg_thr_hi: higher average threshold */ - unsigned int c2h_pend_pkt_avg_thr_hi; - /** @c2h_pend_pkt_avg_thr_lo: lower average threshold */ - unsigned int c2h_pend_pkt_avg_thr_lo; - /** @sorted_c2h_cntr_idx: sorted c2h counter index */ - unsigned char sorted_c2h_cntr_idx; - /** @c2h_cntr_monitor_cnt: c2h counter stagnant monitor count */ - unsigned char c2h_cntr_monitor_cnt; -#ifdef ERR_DEBUG - /** flag to indicate error inducing */ - u64 induce_err; - u64 ecc_err; -#endif -#ifdef DEBUGFS - /** debugfs queue index root */ - struct dentry *dbgfs_qidx_root; - /** debugfs queue root */ - struct dentry *dbgfs_queue_root; - /** debugfs cmpt queue root */ - struct dentry *dbgfs_cmpt_queue_root; -#endif -}; -#ifdef DEBUG_THREADS -#define lock_descq(descq) \ - do { \ - pr_debug("locking descq %s ...\n", (descq)->conf.name); \ - spin_lock_bh(&(descq)->lock); \ - } while (0) - -#define unlock_descq(descq) \ - do { \ - pr_debug("unlock descq %s ...\n", (descq)->conf.name); \ - spin_unlock_bh(&(descq)->lock); \ - } while (0) -#else -/** macro to lock descq */ -#define lock_descq(descq) spin_lock_bh(&(descq)->lock) -/** macro to un lock descq */ -#define unlock_descq(descq) spin_unlock_bh(&(descq)->lock) -#endif - -static inline unsigned int ring_idx_delta(unsigned int new, unsigned int old, - unsigned int rngsz) -{ - return new >= old ? (new - old) : new + (rngsz - old); -} - -static inline unsigned int ring_idx_incr(unsigned int idx, unsigned int cnt, - unsigned int rngsz) -{ - idx += cnt; - return idx >= rngsz ? idx - rngsz : idx; -} - -static inline unsigned int ring_idx_decr(unsigned int idx, unsigned int cnt, - unsigned int rngsz) -{ - return idx >= cnt ? idx - cnt : rngsz - (cnt - idx); -} - -/*****************************************************************************/ -/** - * qdma_descq_init() - initialize the sw descq entry - * - * @param[in] descq: pointer to qdma_descq - * @param[in] xdev: pointer to xdev - * @param[in] idx_hw: hw queue index - * @param[in] idx_sw: sw queue index - * - * @return none - *****************************************************************************/ -void qdma_descq_init(struct qdma_descq *descq, struct xlnx_dma_dev *xdev, - int idx_hw, int idx_sw); - -/*****************************************************************************/ -/** - * qdma_descq_config() - configure the sw descq entry - * - * @param[in] descq: pointer to qdma_descq - * @param[in] qconf: queue configuration - * @param[in] reconfig: flag to indicate whether to refig the sw descq - * - * @return none - *****************************************************************************/ -void qdma_descq_config(struct qdma_descq *descq, struct qdma_queue_conf *qconf, - int reconfig); - -/*****************************************************************************/ -/** - * qdma_descq_config_complete() - initialize the descq with default values - * - * @param[in] descq: pointer to qdma_descq - * - * @return 0: success - * @return <0: failure - *****************************************************************************/ -int qdma_descq_config_complete(struct qdma_descq *descq); - -/*****************************************************************************/ -/** - * qdma_descq_alloc_resource() - allocate the resources for a request - * - * @param[in] descq: pointer to qdma_descq - * - * @return 0: success - * @return <0: failure - *****************************************************************************/ -int qdma_descq_alloc_resource(struct qdma_descq *descq); - -/*****************************************************************************/ -/** - * qdma_descq_free_resource() - free up the resources assigned to a request - * - * @param[in] descq: pointer to qdma_descq - * - * @return none - *****************************************************************************/ -void qdma_descq_free_resource(struct qdma_descq *descq); - -/*****************************************************************************/ -/** - * qdma_descq_prog_hw() - program the hw descriptors - * - * @param[in] descq: pointer to qdma_descq - * - * @return 0: success - * @return <0: failure - *****************************************************************************/ -int qdma_descq_prog_hw(struct qdma_descq *descq); - -/*****************************************************************************/ -/** - * qdma_descq_context_cleanup() - clean up the queue context - * - * @param[in] descq: pointer to qdma_descq - * - * @return 0: success - * @return <0: failure - *****************************************************************************/ -int qdma_descq_context_cleanup(struct qdma_descq *descq); - -/*****************************************************************************/ -/** - * qdma_descq_service_cmpl_update() - process completion data for the request - * - * @param[in] descq: pointer to qdma_descq - * @param[in] budget: number of descriptors to process - * @param[in] c2h_upd_cmpl: C2H only: if update completion needed - * - * @return 0 - success, < 0 for failure - *****************************************************************************/ -int qdma_descq_service_cmpl_update(struct qdma_descq *descq, int budget, - bool c2h_upd_cmpl); - -/*****************************************************************************/ -/** - * qdma_descq_dump() - dump the queue sw desciptor data - * - * @param[in] descq: pointer to qdma_descq - * @param[in] detail: indicate whether full details or abstact details - * @param[in] buflen: length of the input buffer - * @param[out] buf: message buffer - * - * @return 0: success - * @return <0: failure - *****************************************************************************/ -int qdma_descq_dump(struct qdma_descq *descq, - char *buf, int buflen, int detail); - -/*****************************************************************************/ -/** - * qdma_descq_dump_desc() - dump the queue hw descriptors - * - * @param[in] descq: pointer to qdma_descq - * @param[in] start: start descriptor index - * @param[in] end: end descriptor index - * @param[in] buflen: length of the input buffer - * @param[out] buf: message buffer - * - * @return 0: success - * @return <0: failure - *****************************************************************************/ -int qdma_descq_dump_desc(struct qdma_descq *descq, int start, int end, - char *buf, int buflen); - -/*****************************************************************************/ -/** - * qdma_descq_dump_state() - dump the queue desciptor state - * - * @param[in] descq: pointer to qdma_descq - * @param[in] buflen: length of the input buffer - * @param[out] buf: message buffer - * - * @return 0: success - * @return <0: failure - *****************************************************************************/ -int qdma_descq_dump_state(struct qdma_descq *descq, char *buf, int buflen); - -/*****************************************************************************/ -/** - * intr_cidx_update() - update the interrupt cidx - * - * @param[in] descq: pointer to qdma_descq - * @param[in] sw_cidx: sw cidx - * @param[in] ring_index: ring index - * - *****************************************************************************/ -void intr_cidx_update(struct qdma_descq *descq, unsigned int sw_cidx, - int ring_index); - -/*****************************************************************************/ -/** - * incr_cmpl_desc_cnt() - update the interrupt cidx - * - * @param[in] descq: pointer to qdma_descq - * - *****************************************************************************/ -void incr_cmpl_desc_cnt(struct qdma_descq *descq, unsigned int cnt); - -/** - * @struct - qdma_sgt_req_cb - * @brief qdma_sgt_req_cb fits in qdma_request.opaque - */ -struct qdma_sgt_req_cb { - /** qdma read/write request list*/ - struct list_head list; - /** request wait queue */ - qdma_wait_queue wq; - /** number of descriptors to proccess*/ - unsigned int desc_nr; - /** offset in the page*/ - unsigned int offset; - /** offset in the scatter gather list*/ - unsigned int sg_offset; - /** next sg to be processed */ - void *sg; - /** scatter gather ebtry index*/ - unsigned int sg_idx; - /** number of data byte not yet proccessed*/ - unsigned int left; - /** status of the request*/ - int status; - /** indicates whether request processing is done or not*/ - u8 done; - /** indicates whether to unmap the kernel pages*/ - u8 unmap_needed:1; -}; - -/** macro to get the request call back data */ -#define qdma_req_cb_get(req) (struct qdma_sgt_req_cb *)((req)->opaque) - -/*****************************************************************************/ -/** - * qdma_descq_proc_sgt_request() - handler to process the qdma - * read/write request - * - * @param[in] descq: pointer to qdma_descq - * @param[in] cb: scatter gather list call back data - * - * @return size of the request - *****************************************************************************/ -ssize_t qdma_descq_proc_sgt_request(struct qdma_descq *descq); - -/*****************************************************************************/ -/** - * qdma_sgt_req_done() - handler to track the progress of the request - * - * @param[in] descq: pointer to qdma_descq - * @param[in] cb: scatter gather list call back data - * @param[out] error: indicates the error status - * - * @return none - *****************************************************************************/ -void qdma_sgt_req_done(struct qdma_descq *descq, struct qdma_sgt_req_cb *cb, - int error); - -/*****************************************************************************/ -/** - * sgl_map() - handler to map the scatter gather list to kernel pages - * - * @param[in] pdev: pointer to struct pci_dev - * @param[in] sgl: scatter gather list - * @param[in] sgcnt: number of entries in scatter gather list - * @param[in] dir: direction of the request - * - * @return none - *****************************************************************************/ -int sgl_map(struct pci_dev *pdev, struct qdma_sw_sg *sgl, unsigned int sgcnt, - enum dma_data_direction dir); - -/*****************************************************************************/ -/** - * sgl_unmap() - handler to unmap the scatter gather list and free - * the kernel pages - * - * @param[in] pdev: pointer to struct pci_dev - * @param[in] sg: scatter gather list - * @param[in] sgcnt: number of entries in scatter gather list - * @param[in] dir: direction of the request - * - * @return none - *****************************************************************************/ -void sgl_unmap(struct pci_dev *pdev, struct qdma_sw_sg *sg, unsigned int sgcnt, - enum dma_data_direction dir); - -/*****************************************************************************/ -/** - * descq_flq_free_resource() - handler to free the pages for the request - * - * @param[in] descq: pointer to qdma_descq - * - * @return none - *****************************************************************************/ -void descq_flq_free_resource(struct qdma_descq *descq); - -/*****************************************************************************/ -/** - * descq_flq_free_page_resource() - handler to free the pages for the request - * - * @param[in] descq: pointer to qdma_descq - * - * @return none - *****************************************************************************/ -void descq_flq_free_page_resource(struct qdma_descq *descq); -int rcv_udd_only(struct qdma_descq *descq, struct qdma_ul_cmpt_info *cmpl); -int parse_cmpl_entry(struct qdma_descq *descq, struct qdma_ul_cmpt_info *cmpl); -void cmpt_next(struct qdma_descq *descq); - -/* CIDX/PIDX update macros */ -#ifndef __QDMA_VF__ -#define queue_pidx_update(xdev, qid, is_c2h, pidx_info) \ - (xdev->hw.qdma_queue_pidx_update(xdev, QDMA_DEV_PF, qid, is_c2h,\ - pidx_info)) -#else -#define queue_pidx_update(xdev, qid, is_c2h, pidx_info) \ - (xdev->hw.qdma_queue_pidx_update(xdev, QDMA_DEV_VF, qid, is_c2h, \ - pidx_info)) -#endif - -#ifndef __QDMA_VF__ -#define queue_cmpt_cidx_update(xdev, qid, cmpt_cidx_info) \ - (xdev->hw.qdma_queue_cmpt_cidx_update(xdev, QDMA_DEV_PF, qid, \ - cmpt_cidx_info)) -#else -#define queue_cmpt_cidx_update(xdev, qid, cmpt_cidx_info) \ - (xdev->hw.qdma_queue_cmpt_cidx_update(xdev, QDMA_DEV_VF, qid, \ - cmpt_cidx_info)) -#endif - -#ifndef __QDMA_VF__ -#define queue_cmpt_cidx_read(xdev, qid, cmpt_cidx_info) \ - (xdev->hw.qdma_queue_cmpt_cidx_read(xdev, QDMA_DEV_PF, qid, \ - cmpt_cidx_info)) -#else -#define queue_cmpt_cidx_read(xdev, qid, cmpt_cidx_info) \ - (xdev->hw.qdma_queue_cmpt_cidx_read(xdev, QDMA_DEV_VF, qid, \ - cmpt_cidx_info)) -#endif - -#ifndef __QDMA_VF__ -#define queue_intr_cidx_update(xdev, qid, intr_cidx_info) \ - (xdev->hw.qdma_queue_intr_cidx_update(xdev, QDMA_DEV_PF, qid, \ - intr_cidx_info)) -#else -#define queue_intr_cidx_update(xdev, qid, intr_cidx_info) \ - (xdev->hw.qdma_queue_intr_cidx_update(xdev, QDMA_DEV_VF, qid, \ - intr_cidx_info)) -#endif - -u64 rdtsc_gettime(void); -static inline unsigned int get_next_powof2(unsigned int value) -{ - unsigned int num_bits, mask, f_value; - - num_bits = fls(value) - 1; - mask = (1 << num_bits) - 1; - f_value = ((value + mask) >> num_bits) << num_bits; - - return f_value; -} - -//#define QDMA_SPIN_LOCK_GRANULAR - -static inline void qdma_work_queue_add(struct qdma_descq *descq, - struct qdma_sgt_req_cb *cb) -{ -#ifdef QDMA_SPIN_LOCK_GRANULAR - spin_lock_bh(&descq->work_list_lock); - list_add_tail(&cb->list, &descq->work_list); - descq->work_req_pend++; - spin_unlock_bh(&descq->work_list_lock); -#else - list_add_tail(&cb->list, &descq->work_list); - descq->work_req_pend++; -#endif -} - -static inline void qdma_work_queue_del(struct qdma_descq *descq, - struct qdma_sgt_req_cb *cb) -{ -#ifdef QDMA_SPIN_LOCK_GRANULAR - spin_lock_bh(&descq->work_list_lock); - list_del(&cb->list); - descq->work_req_pend--; - spin_unlock_bh(&descq->work_list_lock); -#else - list_del(&cb->list); - descq->work_req_pend--; -#endif -} - -static inline int qdma_work_queue_len(struct qdma_descq *descq) -{ - int count = 0; - -#ifdef QDMA_SPIN_LOCK_GRANULAR - spin_lock_bh(&descq->work_list_lock); - count = descq->work_req_pend; - spin_unlock_bh(&descq->work_list_lock); -#else - count = descq->work_req_pend; -#endif - return count; -} - -static inline struct qdma_request *qdma_work_queue_first_entry( - struct qdma_descq *descq) -{ - struct qdma_request *req; -#ifdef QDMA_SPIN_LOCK_GRANULAR - spin_lock_bh(&descq->work_list_lock); - req = (struct qdma_request *) list_first_entry(&descq->work_list, - struct qdma_sgt_req_cb, list); - spin_unlock_bh(&descq->work_list_lock); -#else - req = (struct qdma_request *) list_first_entry(&descq->work_list, - struct qdma_sgt_req_cb, list); -#endif - return req; -} -#endif /* ifndef __QDMA_DESCQ_H__ */ diff --git a/QDMA/linux-kernel/driver/libqdma/qdma_device.c b/QDMA/linux-kernel/driver/libqdma/qdma_device.c deleted file mode 100755 index fcf80581d..000000000 --- a/QDMA/linux-kernel/driver/libqdma/qdma_device.c +++ /dev/null @@ -1,635 +0,0 @@ -/* - * This file is part of the Xilinx DMA IP Core driver for Linux - * - * Copyright (c) 2017-2022, Xilinx, Inc. All rights reserved. - * Copyright (c) 2022, Advanced Micro Devices, Inc. All rights reserved. - * - * This source code is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * The full GNU General Public License is included in this distribution in - * the file called "COPYING". - */ - -#define pr_fmt(fmt) KBUILD_MODNAME ":%s: " fmt, __func__ - -#include -#include -#include -#include "qdma_device.h" -#include "qdma_context.h" -#include "qdma_descq.h" -#include "qdma_intr.h" -#include "qdma_regs.h" -#include "qdma_mbox.h" -#include "qdma_access_common.h" -#include "qdma_resource_mgmt.h" - -#ifdef __QDMA_VF__ -static int device_set_qrange(struct xlnx_dma_dev *xdev) -{ - struct qdma_dev *qdev = xdev_2_qdev(xdev); - struct mbox_msg *m; - int rv = 0; - - if (!qdev) { - pr_err("dev %s, qdev null.\n", - dev_name(&xdev->conf.pdev->dev)); - return -EINVAL; - } - - m = qdma_mbox_msg_alloc(); - if (!m) - return -ENOMEM; - - qdma_mbox_compose_vf_fmap_prog(xdev->func_id, qdev->qmax, - (int)qdev->qbase, - m->raw); - rv = qdma_mbox_msg_send(xdev, m, 1, QDMA_MBOX_MSG_TIMEOUT_MS); - if (rv < 0) { - if (rv != -ENODEV) - pr_info("%s set q range (fmap) failed %d.\n", - xdev->conf.name, rv); - goto err_out; - } - - rv = qdma_mbox_vf_response_status(m->raw); - if (rv < 0) { - pr_err("mbox_vf_response_status failed, err = %d", rv); - rv = -EINVAL; - } - pr_debug("%s, func id %u/%u, Q 0x%x + 0x%x.\n", - xdev->conf.name, xdev->func_id, xdev->func_id_parent, - qdev->qbase, qdev->qmax); - - if (!rv) - qdev->init_qrange = 1; - -err_out: - qdma_mbox_msg_free(m); - return rv; -} - -int device_set_qconf(struct xlnx_dma_dev *xdev, int *qmax, int *qbase) -{ - struct mbox_msg *m; - int rv = 0; - - m = qdma_mbox_msg_alloc(); - if (!m) - return -ENOMEM; - - qdma_mbox_compose_vf_qreq(xdev->func_id, - (uint16_t)*qmax & 0xFFFF, *qbase, m->raw); - rv = qdma_mbox_msg_send(xdev, m, 1, QDMA_MBOX_MSG_TIMEOUT_MS); - if (rv < 0) { - pr_info("%s set q range (qconf) failed %d.\n", - xdev->conf.name, rv); - goto err_out; - } - - rv = qdma_mbox_vf_qinfo_get(m->raw, qbase, (uint16_t *)qmax); - if (rv < 0) { - pr_err("mbox_vf_qinfo_get failed, err = %d", rv); - rv = -EINVAL; - } -err_out: - qdma_mbox_msg_free(m); - return rv; -} -#else -static int device_set_qrange(struct xlnx_dma_dev *xdev) -{ - struct qdma_dev *qdev = xdev_2_qdev(xdev); - struct qdma_fmap_cfg fmap; - int rv = 0; - - memset(&fmap, 0, sizeof(struct qdma_fmap_cfg)); - - if (!qdev) { - pr_err("dev %s, qdev null.\n", - dev_name(&xdev->conf.pdev->dev)); - return -EINVAL; - } - - fmap.qmax = qdev->qmax; - fmap.qbase = qdev->qbase; - - rv = xdev->hw.qdma_fmap_conf(xdev, xdev->func_id, &fmap, - QDMA_HW_ACCESS_WRITE); - if (rv < 0) { - pr_err("FMAP write failed, err %d\n", rv); - return xdev->hw.qdma_get_error_code(rv); - } - - qdev->init_qrange = 1; - - pr_debug("%s, func id %u, Q 0x%x + 0x%x.\n", - xdev->conf.name, xdev->func_id, qdev->qbase, qdev->qmax); - - return rv; -} -#endif /* ifndef __QDMA_VF__ */ - -int qdma_device_interrupt_setup(struct xlnx_dma_dev *xdev) -{ - int rv = 0; - - if ((xdev->conf.qdma_drv_mode == INDIRECT_INTR_MODE) || - (xdev->conf.qdma_drv_mode == AUTO_MODE)) { - rv = intr_ring_setup(xdev); - if (rv) { - pr_err("Failed to setup intr ring, err %d", rv); - return -EINVAL; - } - - if (xdev->intr_coal_list != NULL) { - rv = qdma_intr_context_setup(xdev); - if (rv) - return rv; - } else { - pr_info("dev %s intr vec[%d] >= queues[%d], No aggregation\n", - dev_name(&xdev->conf.pdev->dev), - (xdev->num_vecs - xdev->dvec_start_idx), - xdev->conf.qsets_max); - pr_warn("Changing the system mode to direct interrupt mode"); - xdev->conf.qdma_drv_mode = DIRECT_INTR_MODE; - } - } - - -#ifndef __QDMA_VF__ - if (((xdev->conf.qdma_drv_mode != POLL_MODE) && - (xdev->conf.qdma_drv_mode != LEGACY_INTR_MODE)) && - xdev->conf.master_pf) { - rv = qdma_err_intr_setup(xdev); - if (rv < 0) { - pr_err("Failed to setup err intr, err %d", rv); - return -EINVAL; - } - - rv = xdev->hw.qdma_hw_error_enable(xdev, - xdev->hw.qdma_max_errors); - if (rv < 0) { - pr_err("Failed to enable error interrupt, err = %d", - rv); - return -EINVAL; - } - - rv = xdev->hw.qdma_hw_error_intr_rearm(xdev); - if (rv < 0) { - pr_err("Failed to rearm error interrupt with error = %d", - rv); - return -EINVAL; - } - } -#endif - return rv; -} - -void qdma_device_interrupt_cleanup(struct xlnx_dma_dev *xdev) -{ - if (xdev->intr_coal_list) - intr_ring_teardown(xdev); -} - -int qdma_device_prep_q_resource(struct xlnx_dma_dev *xdev) -{ - struct qdma_dev *qdev = xdev_2_qdev(xdev); - int rv = 0; - - if (qdev->init_qrange) - goto done; - - rv = qdma_csr_read(xdev, &xdev->csr_info); - if (rv < 0) - goto done; - - rv = device_set_qrange(xdev); - if (rv < 0) - goto done; -done: - return rv; -} - -int qdma_device_init(struct xlnx_dma_dev *xdev) -{ - int i = 0; - struct qdma_fmap_cfg fmap; - -#ifndef __QDMA_VF__ - int rv = 0; -#endif - int qmax = xdev->conf.qsets_max; - struct qdma_descq *descq; - struct qdma_dev *qdev; - - memset(&fmap, 0, sizeof(struct qdma_fmap_cfg)); - - qdev = kzalloc(sizeof(struct qdma_dev), GFP_KERNEL); - - if (!qdev) { - pr_err("dev %s qmax %d OOM.\n", - dev_name(&xdev->conf.pdev->dev), qmax); - intr_teardown(xdev); - return -ENOMEM; - } - - spin_lock_init(&qdev->lock); - xdev->dev_priv = (void *)qdev; -#ifndef __QDMA_VF__ - if (xdev->conf.master_pf) { - rv = xdev->hw.qdma_init_ctxt_memory(xdev); - if (rv < 0) { - pr_err("init ctxt write failed, err %d\n", rv); - return xdev->hw.qdma_get_error_code(rv); - } - } -#endif - - qdev->h2c_descq = kmalloc(sizeof(struct qdma_descq) * qmax, GFP_KERNEL); - qdev->c2h_descq = kmalloc(sizeof(struct qdma_descq) * qmax, GFP_KERNEL); - qdev->cmpt_descq = kmalloc(sizeof(struct qdma_descq) * qmax, - GFP_KERNEL); - - qdev->qmax = qmax; - qdev->init_qrange = 0; - - qdev->qbase = xdev->conf.qsets_base; - - for (i = 0, descq = qdev->h2c_descq; i < qdev->qmax; i++, descq++) - qdma_descq_init(descq, xdev, i, i); - for (i = 0, descq = qdev->c2h_descq; i < qdev->qmax; i++, descq++) - qdma_descq_init(descq, xdev, i, i); - for (i = 0, descq = qdev->cmpt_descq; i < qdev->qmax; i++, descq++) - qdma_descq_init(descq, xdev, i, i); -#ifndef __QDMA_VF__ - xdev->hw.qdma_set_default_global_csr(xdev); - for (i = 0; i < xdev->dev_cap.mm_channel_max; i++) { - xdev->hw.qdma_mm_channel_conf(xdev, i, 1, 1); - xdev->hw.qdma_mm_channel_conf(xdev, i, 0, 1); - } -#endif - return 0; -} - -#define QDMA_BUF_LEN 256 -void qdma_device_cleanup(struct xlnx_dma_dev *xdev) -{ - int i; - struct qdma_dev *qdev = xdev_2_qdev(xdev); - struct qdma_descq *descq; - char buf[QDMA_BUF_LEN]; - - if (!qdev) { - pr_info("dev %s, qdev null.\n", - dev_name(&xdev->conf.pdev->dev)); - return; - } - - for (i = 0, descq = qdev->h2c_descq; i < qdev->qmax; i++, descq++) { - if (descq->q_state == Q_STATE_ONLINE) - qdma_queue_stop((unsigned long int)xdev, - i, buf, QDMA_BUF_LEN); - } - - for (i = 0, descq = qdev->c2h_descq; i < qdev->qmax; i++, descq++) { - if (descq->q_state == Q_STATE_ONLINE) - qdma_queue_stop((unsigned long int)xdev, - i + qdev->qmax, buf, QDMA_BUF_LEN); - } - - for (i = 0, descq = qdev->h2c_descq; i < qdev->qmax; i++, descq++) { - if (descq->q_state == Q_STATE_ENABLED) - qdma_queue_remove((unsigned long int)xdev, - i, buf, QDMA_BUF_LEN); - } - - for (i = 0, descq = qdev->c2h_descq; i < qdev->qmax; i++, descq++) { - if (descq->q_state == Q_STATE_ENABLED) - qdma_queue_remove((unsigned long int)xdev, - i + qdev->qmax, buf, QDMA_BUF_LEN); - } - - kfree(qdev->h2c_descq); - kfree(qdev->c2h_descq); - kfree(qdev->cmpt_descq); - xdev->dev_priv = NULL; - kfree(qdev); -} - -long qdma_device_get_id_from_descq(struct xlnx_dma_dev *xdev, - struct qdma_descq *descq) -{ - struct qdma_dev *qdev; - unsigned long idx; - unsigned long idx_max; - struct qdma_descq *_descq; - - if (!xdev) { - pr_info("xdev NULL.\n"); - return -EINVAL; - } - - qdev = xdev_2_qdev(xdev); - - if (!qdev) { - pr_err("dev %s, qdev null.\n", - dev_name(&xdev->conf.pdev->dev)); - return -EINVAL; - } - if (descq->conf.q_type == Q_H2C) { - _descq = qdev->h2c_descq; - idx = 0; - } else if (descq->conf.q_type == Q_C2H) { - _descq = qdev->c2h_descq; - idx = qdev->qmax; - } else { - _descq = qdev->cmpt_descq; - idx = 2 * qdev->qmax; - } - - idx_max = (idx + (2 * qdev->qmax)); - for (; idx < idx_max; idx++, _descq++) - if (_descq == descq) - return idx; - - return -EINVAL; - -} - -struct qdma_descq *qdma_device_get_descq_by_id(struct xlnx_dma_dev *xdev, - unsigned long idx, char *buf, int buflen, int init) -{ - struct qdma_dev *qdev; - struct qdma_descq *descq; - - if (!xdev) { - pr_info("xdev NULL.\n"); - return NULL; - } - - qdev = xdev_2_qdev(xdev); - - if (!qdev) { - pr_err("dev %s, qdev null.\n", - dev_name(&xdev->conf.pdev->dev)); - return NULL; - } - - if (idx >= qdev->qmax) { - idx -= qdev->qmax; - if (idx >= qdev->qmax) { - idx -= qdev->qmax; - if (idx >= qdev->qmax) { - pr_info("%s, q idx too big 0x%lx > 0x%x.\n", - xdev->conf.name, idx, qdev->qmax); - if (buf && buflen) - snprintf(buf, buflen, - "%s, q idx too big 0x%lx > 0x%x.\n", - xdev->conf.name, idx, qdev->qmax); - return NULL; - } - descq = qdev->cmpt_descq + idx; - } else { - descq = qdev->c2h_descq + idx; - } - } else { - descq = qdev->h2c_descq + idx; - } - - if (init) { - lock_descq(descq); - if (descq->q_state == Q_STATE_DISABLED) { - pr_info("%s, idx 0x%lx, q 0x%p state invalid.\n", - xdev->conf.name, idx, descq); - if (buf && buflen) - snprintf(buf, buflen, - "%s, idx 0x%lx, q 0x%p state invalid.\n", - xdev->conf.name, idx, descq); - unlock_descq(descq); - return NULL; - } - unlock_descq(descq); - } - - return descq; -} - -#ifdef DEBUGFS -struct qdma_descq *qdma_device_get_pair_descq_by_id(struct xlnx_dma_dev *xdev, - unsigned long idx, char *buf, int buflen, int init) -{ - struct qdma_dev *qdev; - struct qdma_descq *pair_descq; - - if (!xdev) { - pr_info("xdev NULL.\n"); - return NULL; - } - - qdev = xdev_2_qdev(xdev); - - if (!qdev) { - pr_err("dev %s, qdev null.\n", - dev_name(&xdev->conf.pdev->dev)); - return NULL; - } - - if (idx >= qdev->qmax) { - idx -= qdev->qmax; - if (idx >= qdev->qmax) { - pr_debug("%s, q idx too big 0x%lx > 0x%x.\n", - xdev->conf.name, idx, qdev->qmax); - if (buf && buflen) - snprintf(buf, buflen, - "%s, q idx too big 0x%lx > 0x%x.\n", - xdev->conf.name, idx, qdev->qmax); - return NULL; - } - pair_descq = qdev->h2c_descq + idx; - } else { - pair_descq = qdev->c2h_descq + idx; - } - - if (init) { - lock_descq(pair_descq); - if (pair_descq->q_state == Q_STATE_DISABLED) { - pr_debug("%s, idx 0x%lx, q 0x%p state invalid.\n", - xdev->conf.name, idx, pair_descq); - if (buf && buflen) - snprintf(buf, buflen, - "%s, idx 0x%lx, q 0x%p state invalid.\n", - xdev->conf.name, idx, pair_descq); - unlock_descq(pair_descq); - return NULL; - } - unlock_descq(pair_descq); - } - - return pair_descq; -} -#endif - -struct qdma_descq *qdma_device_get_descq_by_hw_qid(struct xlnx_dma_dev *xdev, - unsigned long qidx_hw, u8 c2h) -{ - struct qdma_dev *qdev; - struct qdma_descq *descq; - unsigned long qidx_sw = 0; - - if (!xdev) { - pr_info("xdev NULL.\n"); - return NULL; - } - - qdev = xdev_2_qdev(xdev); - - if (!qdev) { - pr_err("dev %s, qdev null.\n", - dev_name(&xdev->conf.pdev->dev)); - return NULL; - } - - qidx_sw = qidx_hw - qdev->qbase; - if (c2h) - descq = &qdev->c2h_descq[qidx_sw]; - else - descq = &qdev->h2c_descq[qidx_sw]; - - return descq; -} - - -void qdma_pf_trigger_vf_reset(unsigned long dev_hndl) -{ - struct xlnx_dma_dev *xdev = (struct xlnx_dma_dev *)dev_hndl; - unsigned int sleep_timeout = 0; - struct mbox_msg *m = NULL; - struct qdma_vf_info *vf = NULL; - int i = 0, rv = 0; - u8 vf_count_online = 0, no_bye_count = 0; - uint32_t active_queue_count = 0; - - if (!xdev) { - pr_err("xdev NULL\n"); - return; - } - - if (!xdev->vf_count) { - pr_debug("VF count is zero\n"); - return; - } - - vf_count_online = xdev->vf_count_online; - vf = (struct qdma_vf_info *)xdev->vf_info; - - xdev->reset_state = RESET_STATE_PF_WAIT_FOR_BYES; - for (i = 0; i < vf_count_online; i++) { - active_queue_count = qdma_get_device_active_queue_count( - xdev->dma_device_index, - vf[i].func_id, QDMA_DEV_Q_TYPE_H2C); - active_queue_count += qdma_get_device_active_queue_count( - xdev->dma_device_index, - vf[i].func_id, QDMA_DEV_Q_TYPE_C2H); - sleep_timeout = QDMA_MBOX_MSG_TIMEOUT_MS + - (200 * active_queue_count); - - pr_info("VF reset in progress. Wait for 0x%x ms\n", - sleep_timeout); - - m = qdma_mbox_msg_alloc(); - if (!m) { - pr_err("Memory allocation for mbox message failed\n"); - return; - } - - pr_debug("xdev->func_id=%d, vf[i].func_id=%d, i = %d", - xdev->func_id, vf[i].func_id, i); - qdma_mbox_compose_vf_reset_message(m->raw, xdev->func_id, - vf[i].func_id); - rv = qdma_mbox_msg_send(xdev, m, 1, QDMA_MBOX_MSG_TIMEOUT_MS); - if (rv == 0) { - qdma_waitq_wait_event_timeout(xdev->wq, - (xdev->vf_count_online == - (vf_count_online - i - 1)), - msecs_to_jiffies(sleep_timeout)); - } - if (xdev->vf_count_online != - (vf_count_online - i - 1)) { - xdev->vf_count_online--; - no_bye_count++; - pr_warn("BYE not recv from func=%d, online_count=%d\n", - vf[i].func_id, xdev->vf_count_online); - } - } - - xdev->reset_state = RESET_STATE_IDLE; - pr_debug("no_bye_count=%d\n", no_bye_count); - -} - -void qdma_pf_trigger_vf_offline(unsigned long dev_hndl) -{ - struct xlnx_dma_dev *xdev = (struct xlnx_dma_dev *)dev_hndl; - struct mbox_msg *m = NULL; - struct qdma_vf_info *vf = NULL; - int i = 0, rv = 0; - unsigned int sleep_timeout = 0; - u8 vf_count_online = 0; - uint32_t active_queue_count = 0; - - if (!xdev) { - pr_err("xdev NULL\n"); - return; - } - - if (!xdev->vf_count) { - pr_debug("VF count is zero\n"); - return; - } - - vf_count_online = xdev->vf_count_online; - vf = (struct qdma_vf_info *)xdev->vf_info; - - for (i = 0; i < vf_count_online; i++) { - active_queue_count = qdma_get_device_active_queue_count( - xdev->dma_device_index, - vf[i].func_id, QDMA_DEV_Q_TYPE_H2C); - active_queue_count += qdma_get_device_active_queue_count( - xdev->dma_device_index, - vf[i].func_id, QDMA_DEV_Q_TYPE_C2H); - sleep_timeout = QDMA_MBOX_MSG_TIMEOUT_MS + - (200 * active_queue_count); - - pr_info("VF offline in progress. Wait for 0x%x ms\n", - sleep_timeout); - m = qdma_mbox_msg_alloc(); - if (!m) { - pr_err("Memory allocation for mbox message failed\n"); - return; - } - pr_info("xdev->func_id=%d, vf[i].func_id=%d, i = %d", - xdev->func_id, vf[i].func_id, i); - qdma_mbox_compose_pf_offline(m->raw, xdev->func_id, - vf[i].func_id); - rv = qdma_mbox_msg_send(xdev, m, 1, QDMA_MBOX_MSG_TIMEOUT_MS); - - if (!rv) { - qdma_waitq_wait_event_timeout(xdev->wq, - vf[i].func_id == QDMA_FUNC_ID_INVALID, - msecs_to_jiffies(sleep_timeout)); - } - - if (vf[i].func_id != QDMA_FUNC_ID_INVALID) - pr_warn("BYE not recv from func=%d, online_count=%d\n", - vf[i].func_id, xdev->vf_count_online); - } - pr_debug("xdev->vf_count_online=%d\n", xdev->vf_count_online); -} diff --git a/QDMA/linux-kernel/driver/libqdma/qdma_device.h b/QDMA/linux-kernel/driver/libqdma/qdma_device.h deleted file mode 100755 index c86046745..000000000 --- a/QDMA/linux-kernel/driver/libqdma/qdma_device.h +++ /dev/null @@ -1,266 +0,0 @@ -/* - * This file is part of the Xilinx DMA IP Core driver for Linux - * - * Copyright (c) 2017-2022, Xilinx, Inc. All rights reserved. - * Copyright (c) 2022, Advanced Micro Devices, Inc. All rights reserved. - * - * This source code is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * The full GNU General Public License is included in this distribution in - * the file called "COPYING". - */ - -#ifndef LIBQDMA_QDMA_DEVICE_H_ -#define LIBQDMA_QDMA_DEVICE_H_ -/** - * @file - * @brief This file contains the declarations for QDMA device - * - */ -#include -#include "libqdma_export.h" -#include "qdma_access_common.h" - -/** - * forward declaration for qdma descriptor - */ -struct qdma_descq; -/** - * forward declaration for xlnx_dma_dev - */ -struct xlnx_dma_dev; - -/** - * @struct - qdma_dev - * @brief qdma device per function - */ -struct qdma_dev { - /** flag indicates whether the fmap programming is completed or not */ - u8 init_qrange:1; - /** filler */ - u8 filler[3]; - /** max number of queues per function */ - unsigned short qmax; - /** queue start number for this function */ - unsigned short qbase; - /** qdma_dev lock */ - spinlock_t lock; - /** h2c descq list */ - struct qdma_descq *h2c_descq; - /** c2h descq list */ - struct qdma_descq *c2h_descq; - /** cmpt descq list */ - struct qdma_descq *cmpt_descq; -}; - -/** - * macro to convert the given xdev to qdev - */ -#define xdev_2_qdev(xdev) (struct qdma_dev *)((xdev)->dev_priv) - -/*****************************************************************************/ -/** - * qdma_device_init() - initializes the qdma device - * - * @param[in] xdev: pointer to xdev - * - * @return 0: success - * @return -1: failure - *****************************************************************************/ -int qdma_device_init(struct xlnx_dma_dev *xdev); - -/*****************************************************************************/ -/** - * qdma_device_cleanup() - clean up the qdma device - * - * @param[in] xdev: pointer to xdev - * - * @return none - *****************************************************************************/ -void qdma_device_cleanup(struct xlnx_dma_dev *xdev); - -/*****************************************************************************/ -/** - * qdma_device_get_descq_by_id() - get the qhndl for descq - * - * @param[in] xdev: pointer to xdev - * @param[in] descq: pointer to the descq - * - * @return qhndl for descq on success - * @return <0 on failure - *****************************************************************************/ -long qdma_device_get_id_from_descq(struct xlnx_dma_dev *xdev, - struct qdma_descq *descq); -/*****************************************************************************/ -/** - * qdma_device_get_descq_by_id() - get the descq using the qid - * - * @param[in] xdev: pointer to xdev - * @param[in] idx: sw qidx - * @param[in] init: indicates whether to initialize the device or not - * @param[in] buflen: length of the input buffer - * @param[out] buf: message buffer - * - * @return pointer to descq on success - * @return NULL on failure - *****************************************************************************/ -struct qdma_descq *qdma_device_get_descq_by_id(struct xlnx_dma_dev *xdev, - unsigned long idx, char *buf, int buflen, int init); - -#ifdef DEBUGFS -/*****************************************************************************/ -/** - * qdma_device_get_pair_descq_by_id() - get the descq using the qid - * - * @param[in] xdev: pointer to xdev - * @param[in] idx: sw qidx - * @param[in] init: indicates whether to initialize the device or not - * @param[in] buflen: length of the input buffer - * @param[out] buf: message buffer - * - * @return pointer to descq on success - * @return NULL on failure - *****************************************************************************/ -struct qdma_descq *qdma_device_get_pair_descq_by_id(struct xlnx_dma_dev *xdev, - unsigned long idx, char *buf, int buflen, int init); -#endif - -/*****************************************************************************/ -/** - * qdma_device_get_descq_by_hw_qid() - get the descq using the hw qid - * - * @param[in] xdev: pointer to xdev - * @param[in] qidx_hw: hw qidx - * @param[in] c2h: indicates whether hw qidx belongs to c2h or h2c - * - * @return pointer to descq on success - * @return NULL on failure - *****************************************************************************/ -struct qdma_descq *qdma_device_get_descq_by_hw_qid(struct xlnx_dma_dev *xdev, - unsigned long qidx_hw, u8 c2h); - -/*****************************************************************************/ -/** - * qdma_device_prep_q_resource() - Prepare queue resources - * - * @param[in] xdev: pointer to xdev - * - * @return 0: success - * @return <0: failure - *****************************************************************************/ -int qdma_device_prep_q_resource(struct xlnx_dma_dev *xdev); - -/*****************************************************************************/ -/** - * qdma_device_interrupt_setup() - Setup device itnerrupts - * - * @param[in] xdev: pointer to xdev - * - * @return 0: success - * @return <0: failure - *****************************************************************************/ -int qdma_device_interrupt_setup(struct xlnx_dma_dev *xdev); - -/*****************************************************************************/ -/** - * qdma_device_interrupt_cleanup() - Celanup device interrupts - * - * @param[in] xdev: pointer to xdev - * - * @return 0: success - * @return <0: failure - *****************************************************************************/ -void qdma_device_interrupt_cleanup(struct xlnx_dma_dev *xdev); - -#ifdef __QDMA_VF__ -/*****************************************************************************/ -/** - * device_set_qconf() - set device conf - * - * @param[in] xdev: pointer to xdev - * @param[in] qmax: maximum request qsize for VF instance - * @param[in] qbase: queue base - * - * @return 0: success - * @return < 0: failure - *****************************************************************************/ -int device_set_qconf(struct xlnx_dma_dev *xdev, int *qmax, int *qbase); - -#endif - - -enum csr_type { - QDMA_CSR_TYPE_NONE, - QDMA_CSR_TYPE_RNGSZ, /** all global csr ring size settings */ - QDMA_CSR_TYPE_BUFSZ, /** all global csr buffer size settings */ - QDMA_CSR_TYPE_TIMER_CNT, /** all global csr timer count settings */ - QDMA_CSR_TYPE_CNT_TH, /** all global csr counter thresh settings */ - - QDMA_CSR_TYPE_MAX -}; - -/*****************************************************************************/ -/** - * qdma_csr_read() - Read specific global csr registers - * - * @param[in] xdev: pointer to xdev - * @param[out] csr: csr value - * - * @return 0: success - * @return <0: failure - *****************************************************************************/ -int qdma_csr_read(struct xlnx_dma_dev *xdev, struct global_csr_conf *csr); - -/*****************************************************************************/ -/** - * qdma_set_ring_sizes() - Wrapper function to set the ring sizes values - * - * @param[in] xdev: pointer to xdev - * @param[in] index: Index from where the values needs to written - * @param[in] count: number of entries to be written - * @param[in] glbl_rng_sz: pointer to array of global ring sizes - * - * @return 0 on success - * @return <0 on failure - *****************************************************************************/ -int qdma_set_ring_sizes(struct xlnx_dma_dev *xdev, u8 index, - u8 count, u32 *glbl_rng_sz); - -/*****************************************************************************/ -/** - * qdma_set_ring_sizes() - Wrapper function to set the ring sizes values - * - * @param[in] xdev: pointer to xdev - * @param[in] index: Index from where the values needs to written - * @param[in] count: number of entries to be written - * @param[out] glbl_rng_sz: pointer to array of global ring sizes - * - * @return 0 on success - * @return <0 on failure - *****************************************************************************/ -int qdma_get_ring_sizes(struct xlnx_dma_dev *xdev, u8 index, - u8 count, u32 *glbl_rng_sz); - - -/*****************************************************************************/ -/** - * qdma_pf_trigger_vf_reset() - Function to trigger FLR of all the VFs on PF - * - * @param[in] dev_hndl: Handle of the xdev - *****************************************************************************/ -void qdma_pf_trigger_vf_reset(unsigned long dev_hndl); - -/** - * qdma_pf_trigger_vf_offline() - Function to trigger offline of all the VFs - * - * @param[in] dev_hndl: Handle of the xdev - *****************************************************************************/ -void qdma_pf_trigger_vf_offline(unsigned long dev_hndl); -#endif /* LIBQDMA_QDMA_DEVICE_H_ */ diff --git a/QDMA/linux-kernel/driver/libqdma/qdma_intr.c b/QDMA/linux-kernel/driver/libqdma/qdma_intr.c deleted file mode 100755 index 1a90a42f0..000000000 --- a/QDMA/linux-kernel/driver/libqdma/qdma_intr.c +++ /dev/null @@ -1,1024 +0,0 @@ -/* - * This file is part of the Xilinx DMA IP Core driver for Linux - * - * Copyright (c) 2017-2022, Xilinx, Inc. All rights reserved. - * Copyright (c) 2022, Advanced Micro Devices, Inc. All rights reserved. - * - * This source code is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * The full GNU General Public License is included in this distribution in - * the file called "COPYING". - */ - -#define pr_fmt(fmt) KBUILD_MODNAME ":%s: " fmt, __func__ - -#include -#include "qdma_descq.h" -#include "qdma_device.h" -#include "qdma_regs.h" -#include "thread.h" -#include "version.h" -#include "qdma_mbox_protocol.h" -#include "qdma_intr.h" -#ifdef DUMP_ON_ERROR_INTERRUPT -#include "qdma_reg_dump.h" -#endif -#include "qdma_access_common.h" - -#ifndef __QDMA_VF__ -static LIST_HEAD(legacy_intr_q_list); -static spinlock_t legacy_intr_lock; -static spinlock_t legacy_q_add_lock; -static unsigned long legacy_intr_flags = IRQF_SHARED; -#endif - - -#ifndef __QDMA_VF__ -#ifdef DUMP_ON_ERROR_INTERRUPT -#define REG_BANNER_LEN (81 * 5) -static int dump_qdma_regs(struct xlnx_dma_dev *xdev) -{ - int len = 0, dis_len = 0; - int rv; - char *buf = NULL, *tbuff = NULL; - int buflen; - char temp_buf[512]; - - if (!xdev) { - pr_err("Invalid device\n"); - return -EINVAL; - } - - rv = qdma_reg_dump_buf_len((void *)xdev, - xdev->version_info.ip_type, &buflen); - if (rv < 0) { - pr_err("Failed to get reg dump buffer length\n"); - return rv; - } - buflen += REG_BANNER_LEN; - - /** allocate memory */ - tbuff = (char *) kzalloc(buflen, GFP_KERNEL); - if (!tbuff) - return -ENOMEM; - - buf = tbuff; - rv = qdma_dump_config_regs(xdev, buf + len, buflen - len); - if (rv < 0) { - pr_warn("Failed to dump Config Bar register values\n"); - goto free_buf; - } - len += rv; - - *data = buf; - *data_len = buflen; - - buf[++len] = '\0'; - memset(temp_buf, '\0', 512); - for (dis_len = 0; dis_len < len; dis_len += 512) { - memcpy(temp_buf, buf, 512); - pr_info("\n%s", temp_buf); - memset(temp_buf, '\0', 512); - buf += 512; - } - -free_buf: - kfree(tbuf); - return 0; -} -#endif -#endif - -#ifndef MBOX_INTERRUPT_DISABLE -static irqreturn_t mbox_intr_handler(int irq_index, int irq, void *dev_id) -{ - struct xlnx_dma_dev *xdev = dev_id; - struct qdma_mbox *mbox = &xdev->mbox; - - pr_debug("Mailbox IRQ fired on Funtion#%d: index=%d, vector=%d\n", - xdev->func_id, irq_index, irq); - - queue_work(mbox->workq, &mbox->rx_work); - - return IRQ_HANDLED; -} -#endif - -#ifndef USER_INTERRUPT_DISABLE -static irqreturn_t user_intr_handler(int irq_index, int irq, void *dev_id) -{ - struct xlnx_dma_dev *xdev = dev_id; - - pr_debug("User IRQ fired on Funtion#%d: index=%d, vector=%d\n", - xdev->func_id, irq_index, irq); - - if (xdev->conf.fp_user_isr_handler) { -#ifndef __XRT__ - xdev->conf.fp_user_isr_handler((unsigned long)xdev, - xdev->conf.uld); -#else - xdev->conf.fp_user_isr_handler((unsigned long)xdev, - irq_index, xdev->conf.uld); -#endif - } - - return IRQ_HANDLED; -} -#endif - -#ifndef __QDMA_VF__ -static irqreturn_t error_intr_handler(int irq_index, int irq, void *dev_id) -{ - struct xlnx_dma_dev *xdev = dev_id; - - pr_info("Error IRQ fired on Funtion#%d: index=%d, vector=%d\n", - xdev->func_id, irq_index, irq); - - xdev->hw.qdma_hw_error_process(xdev); - - xdev->hw.qdma_hw_error_intr_rearm(xdev); -#ifdef DUMP_ON_ERROR_INTERRUPT - dump_qdma_regs(xdev); -#endif - return IRQ_HANDLED; -} -#endif - -static void data_intr_aggregate(struct xlnx_dma_dev *xdev, int vidx, int irq, - u64 timestamp) -{ - struct qdma_descq *descq = NULL; - u32 counter = 0; - struct intr_coal_conf *coal_entry = - (xdev->intr_coal_list + vidx - xdev->dvec_start_idx); - union qdma_intr_ring *ring_entry; - struct qdma_intr_cidx_reg_info *intr_cidx_info; - uint8_t color = 0; - uint8_t intr_type = 0; - uint32_t qid = 0; - uint32_t num_entries_processed = 0; - - - if (!coal_entry) { - pr_err("Failed to locate the coalescing entry for vector = %d\n", - vidx); - return; - } - intr_cidx_info = &coal_entry->intr_cidx_info; - pr_debug("INTR_COAL: msix[%d].vector=%d, msix[%d].entry=%d, rngsize=%d, cidx = %d\n", - vidx, xdev->msix[vidx].vector, - vidx, - xdev->msix[vidx].entry, - coal_entry->intr_rng_num_entries, - intr_cidx_info->sw_cidx); - - pr_debug("vidx = %d, dvec_start_idx = %d\n", vidx, - xdev->dvec_start_idx); - - if ((xdev->msix[vidx].entry) != coal_entry->vec_id) { - pr_err("msix[%d].entry[%d] != vec_id[%d]\n", - vidx, xdev->msix[vidx].entry, - coal_entry->vec_id); - - return; - } - - counter = intr_cidx_info->sw_cidx; - ring_entry = (coal_entry->intr_ring_base + counter); - if (!ring_entry) { - pr_err("Failed to locate the ring entry for vector = %d\n", - vidx); - return; - } - - do { - if ((xdev->version_info.ip_type == QDMA_VERSAL_HARD_IP) && - (xdev->version_info.device_type == - QDMA_DEVICE_VERSAL_CPM4)) { - color = ring_entry->ring_cpm.coal_color; - intr_type = ring_entry->ring_cpm.intr_type; - qid = ring_entry->ring_cpm.qid; - } else { - color = ring_entry->ring_generic.coal_color; - intr_type = ring_entry->ring_generic.intr_type; - qid = ring_entry->ring_generic.qid; - } - - if (color != coal_entry->color) - break; - pr_debug("IRQ[%d]: IVE[%d], Qid = %d, e_color = %d, c_color = %d, intr_type = %d\n", - irq, vidx, qid, coal_entry->color, - color, intr_type); - - descq = qdma_device_get_descq_by_hw_qid(xdev, qid, - intr_type); - if (!descq) { - pr_err("IRQ[%d]: IVE[%d], Qid = %d: desc not found\n", - irq, vidx, qid); - return; - } - xdev->prev_descq = descq; - pr_debug("IRQ[%d]: IVE[%d], Qid = %d, e_color = %d, c_color = %d, intr_type = %d\n", - irq, vidx, qid, coal_entry->color, - color, intr_type); - - if (descq->conf.ping_pong_en && - descq->conf.q_type == Q_C2H && descq->conf.st) - descq->ping_pong_rx_time = timestamp; - - if (descq->conf.fp_descq_isr_top) { - descq->conf.fp_descq_isr_top(descq->q_hndl, - descq->conf.quld); - } else { - if (descq->cpu_assigned) - schedule_work_on(descq->intr_work_cpu, - &descq->work); - else - schedule_work(&descq->work); - } - - if (++intr_cidx_info->sw_cidx == - coal_entry->intr_rng_num_entries) { - counter = 0; - xdev->intr_coal_list->color = - (xdev->intr_coal_list->color) ? 0 : 1; - intr_cidx_info->sw_cidx = 0; - } else - counter++; - num_entries_processed++; - ring_entry = (coal_entry->intr_ring_base + counter); - } while (1); - - if (descq) { - queue_intr_cidx_update(descq->xdev, - descq->conf.qidx, &coal_entry->intr_cidx_info); - } else if (num_entries_processed == 0) { - pr_debug("No entries processed\n"); - descq = xdev->prev_descq; - if (descq) { - pr_debug("Doing stale update\n"); - queue_intr_cidx_update(descq->xdev, - descq->conf.qidx, &coal_entry->intr_cidx_info); - } - } - -} - -static void data_intr_direct(struct xlnx_dma_dev *xdev, int vidx, int irq, - u64 timestamp) -{ - struct qdma_descq *descq; - unsigned long flags; - struct list_head *descq_list = - &xdev->dev_intr_info_list[vidx].intr_list; - struct list_head *entry, *tmp; - - spin_lock_irqsave(&xdev->dev_intr_info_list[vidx].vec_q_list, - flags); - list_for_each_safe(entry, tmp, descq_list) { - descq = container_of(entry, struct qdma_descq, intr_list); - - if (descq->conf.ping_pong_en && - descq->conf.q_type == Q_C2H && descq->conf.st) - descq->ping_pong_rx_time = timestamp; - - if (descq->conf.fp_descq_isr_top) { - descq->conf.fp_descq_isr_top(descq->q_hndl, - descq->conf.quld); - } else { - if (descq->cpu_assigned) - schedule_work_on(descq->intr_work_cpu, - &descq->work); - else - schedule_work(&descq->work); - } - } - spin_unlock_irqrestore(&xdev->dev_intr_info_list[vidx].vec_q_list, - flags); -} - -static irqreturn_t data_intr_handler(int vector_index, int irq, void *dev_id) -{ - struct xlnx_dma_dev *xdev = dev_id; - u64 timestamp; - - pr_debug("%s: Data IRQ fired on Funtion#%05x: index=%d, vector=%d\n", - xdev->mod_name, xdev->func_id, vector_index, irq); - timestamp = rdtsc_gettime(); - - if ((xdev->conf.qdma_drv_mode == INDIRECT_INTR_MODE) || - (xdev->conf.qdma_drv_mode == AUTO_MODE)) - data_intr_aggregate(xdev, vector_index, irq, timestamp); - else - data_intr_direct(xdev, vector_index, irq, timestamp); - - return IRQ_HANDLED; -} - -static inline void intr_ring_free(struct xlnx_dma_dev *xdev, int ring_sz, - int intr_desc_sz, u8 *intr_desc, dma_addr_t desc_bus) -{ - unsigned int len = ring_sz * intr_desc_sz; - - pr_debug("free %u(0x%x)=%d*%u, 0x%p, bus 0x%llx.\n", - len, len, intr_desc_sz, ring_sz, intr_desc, desc_bus); - - dma_free_coherent(&xdev->conf.pdev->dev, (size_t)ring_sz * intr_desc_sz, - intr_desc, desc_bus); -} - -static void *intr_ring_alloc(struct xlnx_dma_dev *xdev, int ring_sz, - int intr_desc_sz, dma_addr_t *bus) -{ - unsigned int len = ring_sz * intr_desc_sz; - u8 *p = dma_alloc_coherent(&xdev->conf.pdev->dev, len, bus, GFP_KERNEL); - - if (!p) { - pr_err("%s, OOM, sz ring %d, intr_desc %d.\n", - xdev->conf.name, ring_sz, intr_desc_sz); - return NULL; - } - - memset(p, 0, len); - - pr_debug("alloc %u(0x%x)=%d*%u, bus 0x%llx .\n", - len, len, intr_desc_sz, ring_sz, *bus); - - return p; -} - -#ifdef __QDMA_VF__ -static void intr_context_invalidate(struct xlnx_dma_dev *xdev) -{ - int i = 0; - struct mbox_msg *m; - int rv = 0; - struct mbox_msg_intr_ctxt ictxt; - struct intr_coal_conf *ring_entry; - - m = qdma_mbox_msg_alloc(); - if (!m) - return; - memset(&ictxt, 0, sizeof(struct mbox_msg_intr_ctxt)); - ictxt.num_rings = QDMA_NUM_DATA_VEC_FOR_INTR_CXT; - - for (i = 0; i < QDMA_NUM_DATA_VEC_FOR_INTR_CXT; i++) { - ictxt.ring_index_list[i] = - get_intr_ring_index(xdev, xdev->dvec_start_idx + i); - } - qdma_mbox_compose_vf_intr_ctxt_invalidate(xdev->func_id, - &ictxt, m->raw); - rv = qdma_mbox_msg_send(xdev, m, 1, QDMA_MBOX_MSG_TIMEOUT_MS); - if (rv < 0) { - pr_err("%s invalidate interrupt context failed %d.\n", - xdev->conf.name, rv); - } - - qdma_mbox_msg_free(m); - - for (i = 0; i < QDMA_NUM_DATA_VEC_FOR_INTR_CXT; i++) { - ring_entry = (xdev->intr_coal_list + i); - if (ring_entry) { - intr_ring_free(xdev, - ring_entry->intr_rng_num_entries, - sizeof(union qdma_intr_ring), - (u8 *)ring_entry->intr_ring_base, - ring_entry->intr_ring_bus); - } - } - -} -#else -static void intr_context_invalidate(struct xlnx_dma_dev *xdev) -{ - int i = 0; - unsigned int ring_index = 0; - struct intr_coal_conf *ring_entry; - int rv = 0; - - while (i < QDMA_NUM_DATA_VEC_FOR_INTR_CXT) { - ring_index = get_intr_ring_index(xdev, - (i + xdev->dvec_start_idx)); - rv = xdev->hw.qdma_indirect_intr_ctx_conf(xdev, ring_index, - NULL, QDMA_HW_ACCESS_INVALIDATE); - if (rv < 0) { - pr_err("Intr ctxt invalidate failed, err = %d", - rv); - return; - } - ring_entry = (xdev->intr_coal_list + i); - if (ring_entry) { - intr_ring_free(xdev, - ring_entry->intr_rng_num_entries, - sizeof(union qdma_intr_ring), - (u8 *)ring_entry->intr_ring_base, - ring_entry->intr_ring_bus); - } - i++; - } - -} -#endif - -void intr_ring_teardown(struct xlnx_dma_dev *xdev) -{ - intr_context_invalidate(xdev); - kfree(xdev->intr_coal_list); -} - -static void data_vector_handler(int irq, struct xlnx_dma_dev *xdev) -{ - int i; - - for (i = 0; i < xdev->num_vecs; i++) { - if (xdev->msix[i].vector == irq) { - xdev->dev_intr_info_list[i].intr_vec_map.intr_handler(i, - irq, (void *)xdev); - break; - } - } -} - -static irqreturn_t irq_bottom(int irq, void *dev_id) -{ - struct xlnx_dma_dev *xdev = dev_id; - - data_vector_handler(irq, xdev); - - return IRQ_HANDLED; -} - -static irqreturn_t irq_top(int irq, void *dev_id) -{ - struct xlnx_dma_dev *xdev = dev_id; - - if (xdev->conf.fp_q_isr_top_dev) { - xdev->conf.fp_q_isr_top_dev((unsigned long)xdev, - xdev->conf.uld); - } - - return IRQ_WAKE_THREAD; -} - - -void intr_teardown(struct xlnx_dma_dev *xdev) -{ - int i = xdev->num_vecs; - - while (--i >= 0) - free_irq(xdev->msix[i].vector, xdev); - - if (xdev->num_vecs) - pci_disable_msix(xdev->conf.pdev); - - kfree(xdev->msix); - kfree(xdev->dev_intr_info_list); -} - - -static int intr_vector_setup(struct xlnx_dma_dev *xdev, int idx, - enum intr_type_list type, f_intr_handler handler) -{ - int rv; - - if (type == INTR_TYPE_ERROR) - snprintf(xdev->dev_intr_info_list[idx].msix_name, - QDMA_DEV_NAME_MAXLEN + 16, "%s-error", - xdev->conf.name); - - if (type == INTR_TYPE_USER) -#ifndef USER_INTERRUPT_DISABLE - snprintf(xdev->dev_intr_info_list[idx].msix_name, - QDMA_DEV_NAME_MAXLEN + 16, "%s-user", xdev->conf.name); -#else - return -EINVAL; -#endif - if (type == INTR_TYPE_DATA) - snprintf(xdev->dev_intr_info_list[idx].msix_name, - QDMA_DEV_NAME_MAXLEN + 16, "%s-data", xdev->conf.name); - if (type == INTR_TYPE_MBOX) -#ifndef MBOX_INTERRUPT_DISABLE - snprintf(xdev->dev_intr_info_list[idx].msix_name, - QDMA_DEV_NAME_MAXLEN + 16, "%s-mbox", xdev->conf.name); -#else - return -EINVAL; -#endif - - xdev->dev_intr_info_list[idx].intr_vec_map.intr_type = type; - xdev->dev_intr_info_list[idx].intr_vec_map.intr_vec_index = idx; - xdev->dev_intr_info_list[idx].intr_vec_map.intr_handler = handler; - - if ((type == INTR_TYPE_DATA) || (type == INTR_TYPE_MBOX)) { - rv = request_irq(xdev->msix[idx].vector, irq_bottom, 0, - xdev->dev_intr_info_list[idx].msix_name, xdev); - } else - rv = request_threaded_irq(xdev->msix[idx].vector, irq_top, - irq_bottom, 0, - xdev->dev_intr_info_list[idx].msix_name, - xdev); - - pr_debug("%s requesting IRQ vector #%d: vec %d, type %d, %s.\n", - xdev->conf.name, idx, xdev->msix[idx].vector, - type, xdev->dev_intr_info_list[idx].msix_name); - - if (rv) { - pr_err("%s requesting IRQ vector #%d: vec %d failed %d.\n", - xdev->conf.name, idx, xdev->msix[idx].vector, rv); - return rv; - } - - return 0; -} -#ifdef __PCI_MSI_VEC_COUNT__ - -#define msix_table_size(flags) ((flags & PCI_MSIX_FLAGS_QSIZE) + 1) - -static int pci_msix_vec_count(struct pci_dev *dev) -{ - u16 control; - - if (!dev->msix_cap) - return 0; - - pci_read_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, &control); - return msix_table_size(control); -} -#endif - -int intr_setup(struct xlnx_dma_dev *xdev) -{ - int rv = 0; - int i = 0; - int num_vecs = 0; - int num_vecs_req = 0; -#ifndef USER_INTERRUPT_DISABLE - int intr_count = 0; -#endif - - if ((xdev->conf.qdma_drv_mode == POLL_MODE) || - (xdev->conf.qdma_drv_mode == LEGACY_INTR_MODE)) { - goto exit; - } - num_vecs = pci_msix_vec_count(xdev->conf.pdev); - pr_debug("dev %s, xdev->num_vecs = %d\n", - dev_name(&xdev->conf.pdev->dev), xdev->num_vecs); - - if (num_vecs == 0) { - pr_warn("MSI-X not supported, running in polled mode\n"); - return 0; - } - - if (xdev->conf.data_msix_qvec_max == 0) { - pr_err("At least 1 data vector is required. input invalid: data_masix_qvec_max(%u)", - xdev->conf.data_msix_qvec_max); - return -EINVAL; - } - - xdev->num_vecs = min_t(int, num_vecs, xdev->conf.msix_qvec_max); - if (xdev->num_vecs < xdev->conf.msix_qvec_max) - pr_info("current device supports only (%u) msix vectors per function. ignoring input for (%u) vectors", - xdev->num_vecs, - xdev->conf.msix_qvec_max); - - /** Make sure the total supported vectors = - * (user vectors + data vectors + 1 error vectors - * + 1 mailbox vectors) - * find the requested vectors and check the available vectors - * can satisfy the request - */ - num_vecs_req = xdev->conf.user_msix_qvec_max + - xdev->conf.data_msix_qvec_max; - - /** Dedicate 1 vector for error interrupts */ - if (xdev->conf.master_pf) - num_vecs_req++; - -#ifndef MBOX_INTERRUPT_DISABLE - /** Dedicate 1 vector for mailbox interrupts */ - if (qdma_mbox_is_irq_availabe(xdev)) - num_vecs_req++; -#endif - - if (num_vecs_req > xdev->num_vecs) { - pr_warn("Available vectors(%u) is less than Requested vectors(%u) [u:%u|d:%u]\n", - xdev->num_vecs, - num_vecs_req, - xdev->conf.user_msix_qvec_max, - xdev->conf.data_msix_qvec_max); - return -EINVAL; - } - - xdev->msix = kzalloc((sizeof(struct msix_entry) * xdev->num_vecs), - GFP_KERNEL); - if (!xdev->msix) { - pr_err("dev %s xdev->msix OOM.\n", - dev_name(&xdev->conf.pdev->dev)); - rv = -ENOMEM; - goto exit; - } - - xdev->dev_intr_info_list = - kzalloc((sizeof(struct intr_info_t) * xdev->num_vecs), - GFP_KERNEL); - if (!xdev->dev_intr_info_list) { - pr_err("dev %s xdev->dev_intr_info_list OOM.\n", - dev_name(&xdev->conf.pdev->dev)); - rv = -ENOMEM; - goto free_msix; - } - - for (i = 0; i < xdev->num_vecs; i++) { - xdev->msix[i].entry = i; - INIT_LIST_HEAD(&xdev->dev_intr_info_list[i].intr_list); - spin_lock_init(&xdev->dev_intr_info_list[i].vec_q_list); - } - -#if KERNEL_VERSION(4, 12, 0) <= LINUX_VERSION_CODE - rv = pci_enable_msix_exact(xdev->conf.pdev, xdev->msix, xdev->num_vecs); -#else - rv = pci_enable_msix(xdev->conf.pdev, xdev->msix, xdev->num_vecs); -#endif - if (rv < 0) { - pr_err("Error enabling MSI-X (%d)\n", rv); - goto free_intr_info; - } - - /** On master PF0, vector#2 is dedicated for Error interrupts and - * vector #1 is dedicated for User interrupts - * For all other PFs and VFs, vector#0 is dedicated for User interrupts - * The remaining vectors are for Data interrupts - */ - i = 0; /* This is mandatory, do not delete */ - -#ifndef MBOX_INTERRUPT_DISABLE - if (qdma_mbox_is_irq_availabe(xdev)) { - /* Mail box interrupt */ - rv = intr_vector_setup(xdev, i, INTR_TYPE_MBOX, - mbox_intr_handler); - if (rv) - goto cleanup_irq; - i++; - } -#endif - -#ifndef USER_INTERRUPT_DISABLE - for (intr_count = 0; - intr_count < xdev->conf.user_msix_qvec_max; - intr_count++) { - /* user interrupt */ - rv = intr_vector_setup(xdev, i, INTR_TYPE_USER, - user_intr_handler); - if (rv) - goto cleanup_irq; - i++; - } -#endif - -#ifndef __QDMA_VF__ - /* global error interrupt */ - if (xdev->conf.master_pf) { - rv = intr_vector_setup(xdev, i, INTR_TYPE_ERROR, - error_intr_handler); - if (rv) - goto cleanup_irq; - i++; - } -#endif - - /* data interrupt */ - xdev->dvec_start_idx = i; - for (; i < xdev->num_vecs; i++) { - rv = intr_vector_setup(xdev, i, INTR_TYPE_DATA, - data_intr_handler); - if (rv) - goto cleanup_irq; - } - - xdev->flags |= XDEV_FLAG_IRQ; - return rv; - -cleanup_irq: - while (--i >= 0) - free_irq(xdev->msix[i].vector, xdev); - - pci_disable_msix(xdev->conf.pdev); - xdev->num_vecs = 0; -free_intr_info: - kfree(xdev->dev_intr_info_list); -free_msix: - kfree(xdev->msix); -exit: - return rv; -} - - - -#ifndef __QDMA_VF__ -static irqreturn_t irq_legacy(int irq, void *irq_data) -{ - struct list_head *entry, *tmp; - struct xlnx_dma_dev *xdev = (struct xlnx_dma_dev *)irq_data; - irqreturn_t ret = IRQ_NONE; - - if (!xdev) { - pr_err("Invalid Xdev"); - goto irq_return; - } - - spin_lock_irqsave(&legacy_intr_lock, legacy_intr_flags); - if (!xdev->hw.qdma_is_legacy_intr_pend(xdev)) { - - list_for_each_safe(entry, tmp, &legacy_intr_q_list) { - struct qdma_descq *descq = - container_of(entry, - struct qdma_descq, - legacy_intr_q_list); - - qdma_descq_service_cmpl_update(descq, 0, 1); - } - xdev->hw.qdma_clear_pend_legacy_intr(xdev); - xdev->hw.qdma_legacy_intr_conf(xdev, ENABLE); - ret = IRQ_HANDLED; - } - spin_unlock_irqrestore(&legacy_intr_lock, legacy_intr_flags); - -irq_return: - return ret; -} - -void intr_legacy_clear(struct qdma_descq *descq) -{ - - if (!descq) { - pr_err("Invalid descq received"); - return; - } - list_del(&descq->legacy_intr_q_list); - - if (list_empty(&legacy_intr_q_list)) { - - pr_info("un-registering legacy interrupt from qdma%05x\n", - descq->xdev->conf.bdf); - - descq->xdev->hw.qdma_legacy_intr_conf(descq->xdev, DISABLE); - - free_irq(descq->xdev->conf.pdev->irq, descq->xdev); - } -} - -int intr_legacy_setup(struct qdma_descq *descq) -{ - int req_irq = 0; - int rv = 0; - - if (!descq) { - pr_err("Invalid descq received"); - return -EINVAL; - } - - spin_lock(&legacy_q_add_lock); - req_irq = list_empty(&legacy_intr_q_list); - rv = req_irq ? 0 : 1; - - if (req_irq != 0) { - spin_lock_init(&legacy_intr_lock); - pr_debug("registering legacy interrupt for irq-%d from qdma%05x\n", - descq->xdev->conf.pdev->irq, descq->xdev->conf.bdf); - - if (descq->xdev->hw.qdma_legacy_intr_conf(descq->xdev, - DISABLE)) { - spin_unlock(&legacy_q_add_lock); - return -EINVAL; - } - - rv = request_threaded_irq(descq->xdev->conf.pdev->irq, irq_top, - irq_legacy, legacy_intr_flags, - "qdma legacy intr", - descq->xdev); - - if (rv < 0) - goto exit_intr_setup; - else { - list_add_tail(&descq->legacy_intr_q_list, - &legacy_intr_q_list); - rv = 0; - } - if (descq->xdev->hw.qdma_legacy_intr_conf(descq->xdev, - ENABLE)) { - spin_unlock(&legacy_q_add_lock); - return -EINVAL; - } - } else - list_add_tail(&descq->legacy_intr_q_list, - &legacy_intr_q_list); - -exit_intr_setup: - spin_unlock(&legacy_q_add_lock); - return rv; -} -#endif - -int intr_ring_setup(struct xlnx_dma_dev *xdev) -{ - int num_entries = 0; - int counter = 0; - struct intr_coal_conf *intr_coal_list; - struct intr_coal_conf *intr_coal_list_entry; - - if ((xdev->conf.qdma_drv_mode != INDIRECT_INTR_MODE) && - (xdev->conf.qdma_drv_mode != AUTO_MODE)) { - pr_debug("skipping interrupt aggregation: driver is loaded in %s mode\n", - mode_name_list[xdev->conf.qdma_drv_mode].name); - xdev->intr_coal_list = NULL; - return 0; - } - - /** For master_pf, vec1 and vec2 is used for - * error and user interrupts - * for other pfs, vec0 is used for user interrupts - */ - if (xdev->num_vecs != 0) { - pr_debug("dev %s num_vectors[%d] < num_queues [%d]\n", - dev_name(&xdev->conf.pdev->dev), - xdev->num_vecs, - xdev->conf.qsets_max); - pr_debug("Enabling Interrupt aggregation\n"); - - /** obtain the number of queue entries - * in each inr_ring based on ring size - */ - num_entries = ((xdev->conf.intr_rngsz + 1) * 512); - - pr_debug("%s interrupt coalescing ring with %d entries\n", - dev_name(&xdev->conf.pdev->dev), num_entries); - /** - * Initially assuming that each vector has the same size of the - * ring, In practical it is possible to have different ring - * size of different vectors (?) - */ - intr_coal_list = kzalloc( - sizeof(struct intr_coal_conf) * - QDMA_NUM_DATA_VEC_FOR_INTR_CXT, - GFP_KERNEL); - if (!intr_coal_list) { - pr_err("dev %s num_vecs %d OOM.\n", - dev_name(&xdev->conf.pdev->dev), - QDMA_NUM_DATA_VEC_FOR_INTR_CXT); - return -ENOMEM; - } - - for (counter = 0; - counter < QDMA_NUM_DATA_VEC_FOR_INTR_CXT; - counter++) { - intr_coal_list_entry = (intr_coal_list + counter); - intr_coal_list_entry->intr_rng_num_entries = - num_entries; - intr_coal_list_entry->intr_ring_base = intr_ring_alloc( - xdev, num_entries, - sizeof(union qdma_intr_ring), - &intr_coal_list_entry->intr_ring_bus); - if (!intr_coal_list_entry->intr_ring_base) { - pr_err("dev %s, sz %u, intr_desc ring OOM.\n", - xdev->conf.name, - intr_coal_list_entry->intr_rng_num_entries); - goto err_out; - } - - intr_coal_list_entry->vec_id = - xdev->msix[counter + xdev->dvec_start_idx].entry; - intr_coal_list_entry->intr_cidx_info.sw_cidx = 0; - intr_coal_list_entry->color = 1; - intr_coal_list_entry->intr_cidx_info.rng_idx = - get_intr_ring_index(xdev, - intr_coal_list_entry->vec_id); - pr_debug("ring_number = %d, vector_index = %d, ring_size = %d, ring_base = 0x%08x", - counter, intr_coal_list_entry->vec_id, - intr_coal_list_entry->intr_rng_num_entries, - (unsigned int)intr_coal_list_entry->intr_ring_bus); - } - - pr_debug("dev %s interrupt coalescing ring setup successful\n", - dev_name(&xdev->conf.pdev->dev)); - - xdev->intr_coal_list = intr_coal_list; - } else { - pr_info("dev %s intr vec[%d] >= queues[%d], No aggregation\n", - dev_name(&xdev->conf.pdev->dev), - (xdev->num_vecs - xdev->dvec_start_idx), - xdev->conf.qsets_max); - - xdev->intr_coal_list = NULL; - /* Fallback from indirect interrupt mode */ - xdev->conf.qdma_drv_mode = POLL_MODE; - } - return 0; - -err_out: - while (--counter >= 0) { - intr_coal_list_entry = (intr_coal_list + counter); - intr_ring_free(xdev, intr_coal_list_entry->intr_rng_num_entries, - sizeof(union qdma_intr_ring), - (u8 *)intr_coal_list_entry->intr_ring_base, - intr_coal_list_entry->intr_ring_bus); - } - kfree(intr_coal_list); - return -ENOMEM; -} - -void intr_work(struct work_struct *work) -{ - struct qdma_descq *descq; - - descq = container_of(work, struct qdma_descq, work); - qdma_descq_service_cmpl_update(descq, 0, 1); -} - -/** - * qdma_queue_service - service the queue - * in the case of irq handler is registered by the user, the user should - * call qdma_queue_service() in its interrupt handler to service the queue - * @dev_hndl: hndl retured from qdma_device_open() - * @qhndl: hndl retured from qdma_queue_add() - */ -int qdma_queue_service(unsigned long dev_hndl, unsigned long id, int budget, - bool c2h_upd_cmpl) -{ - struct xlnx_dma_dev *xdev = (struct xlnx_dma_dev *)dev_hndl; - struct qdma_descq *descq; - - /** make sure that the dev_hndl passed is Valid */ - if (!xdev) { - pr_err("dev_hndl is NULL"); - return -EINVAL; - } - - if (xdev_check_hndl(__func__, xdev->conf.pdev, dev_hndl) < 0) { - pr_err("Invalid dev_hndl passed"); - return -EINVAL; - } - - descq = qdma_device_get_descq_by_id(xdev, id, NULL, 0, 0); - if (descq) - return qdma_descq_service_cmpl_update(descq, - budget, c2h_upd_cmpl); - - return -EINVAL; -} - -static u8 get_intr_vec_index(struct xlnx_dma_dev *xdev, u8 intr_type) -{ - int i = 0; - - for (i = 0; i < xdev->num_vecs; i++) { - if (xdev->dev_intr_info_list[i].intr_vec_map.intr_type == - intr_type) { - struct intr_info_t *dev_intr_info_list = - &xdev->dev_intr_info_list[i]; - return dev_intr_info_list->intr_vec_map.intr_vec_index; - } - } - return 0; -} - -int qdma_err_intr_setup(struct xlnx_dma_dev *xdev) -{ - int rv = 0; - u8 err_intr_index = 0; - - err_intr_index = get_intr_vec_index(xdev, INTR_TYPE_ERROR); - - rv = xdev->hw.qdma_hw_error_intr_setup(xdev, xdev->func_id, - err_intr_index); - if (rv < 0) { - pr_err("Failed to setup error interrupt, err = %d", rv); - return -EINVAL; - } - - return 0; -} - -int get_intr_ring_index(struct xlnx_dma_dev *xdev, u32 vector_index) -{ - int ring_index = 0; - - ring_index = (vector_index - xdev->dvec_start_idx) + - (xdev->func_id * QDMA_NUM_DATA_VEC_FOR_INTR_CXT); - pr_debug("func_id = %d, vector_index = %d, ring_index = %d\n", - xdev->func_id, vector_index, ring_index); - - return ring_index; -} - -void intr_legacy_init(void) -{ -#ifndef __QDMA_VF__ - spin_lock_init(&legacy_q_add_lock); -#endif -} diff --git a/QDMA/linux-kernel/driver/libqdma/qdma_intr.h b/QDMA/linux-kernel/driver/libqdma/qdma_intr.h deleted file mode 100755 index c26174e5a..000000000 --- a/QDMA/linux-kernel/driver/libqdma/qdma_intr.h +++ /dev/null @@ -1,259 +0,0 @@ -/* - * This file is part of the Xilinx DMA IP Core driver for Linux - * - * Copyright (c) 2017-2022, Xilinx, Inc. All rights reserved. - * Copyright (c) 2022, Advanced Micro Devices, Inc. All rights reserved. - * - * This source code is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * The full GNU General Public License is included in this distribution in - * the file called "COPYING". - */ - -#ifndef LIBQDMA_QDMA_INTR_H_ -#define LIBQDMA_QDMA_INTR_H_ -/** - * @file - * @brief This file contains the declarations for qdma dev interrupt handlers - * - */ -#include -#include -#include "qdma_descq.h" -/** - * forward declaration for xlnx_dma_dev - */ -struct xlnx_dma_dev; - -/** - * @struct - qdma_intr_ring_cpm - * @brief Interrupt ring entry definition for 2018.2 CPM release - */ -struct qdma_intr_ring_cpm { - /** producer index. This is from Interrupt source. - * Cumulative pointer of total interrupt Aggregation - * Ring entry written - */ - __be64 pidx:16; - /** consumer index. This is from Interrupt source. - * Cumulative consumed pointer - */ - __be64 cidx:16; - /** source color. This is from Interrupt source. - * This bit inverts every time pidx wraps around - * and this field gets copied to color field of descriptor. - */ - __be64 s_color:1; - /** This is from Interrupt source. - * Interrupt state, 0: CMPT_INT_ISR; 1: CMPT_INT_TRIG; 2: CMPT_INT_ARMED - */ - __be64 intr_satus:2; - /** error. This is from interrupt source - * {C2h_err[1:0], h2c_err[1:0]} - */ - __be64 error:4; - /** 11 reserved bits*/ - __be64 rsvd:11; - /** Is the interrupt raised due to error ? - * 1: error interrupt; 0: non-error interrupt - */ - __be64 error_int:1; - /** interrupt type, 0: H2C; 1: C2H*/ - __be64 intr_type:1; - /** This is from Interrupt source. Queue ID*/ - __be64 qid:11; - /** The color bit of the Interrupt Aggregation Ring. - * This bit inverts every time pidx wraps around on the - * Interrupt Aggregation Ring. - */ - __be64 coal_color:1; -}; - -/** - * @struct - qdma_intr_ring_generic - * @brief Interrupt ring entry definition - */ -struct qdma_intr_ring_generic { - /** producer index. This is from Interrupt source. - * Cumulative pointer of total interrupt Aggregation - * Ring entry written - */ - __be64 pidx:16; - /** consumer index. This is from Interrupt source. - * Cumulative consumed pointer - */ - __be64 cidx:16; - /** source color. This is from Interrupt source. - * This bit inverts every time pidx wraps around - * and this field gets copied to color field of descriptor. - */ - __be64 s_color:1; - /** This is from Interrupt source. - * Interrupt state, 0: CMPT_INT_ISR; 1: CMPT_INT_TRIG; 2: CMPT_INT_ARMED - */ - __be64 intr_satus:2; - /** error. This is from interrupt source - * {C2h_err[1:0], h2c_err[1:0]} - */ - __be64 error:2; - /** 1 reserved bits*/ - __be64 rsvd:1; - /** interrupt type, 0: H2C; 1: C2H*/ - __be64 intr_type:1; - /** This is from Interrupt source. Queue ID*/ - __be64 qid:24; - /** The color bit of the Interrupt Aggregation Ring. - * This bit inverts every time pidx wraps around on the - * Interrupt Aggregation Ring. - */ - __be64 coal_color:1; -}; - -union qdma_intr_ring { - struct qdma_intr_ring_cpm ring_cpm; - struct qdma_intr_ring_generic ring_generic; -}; - - -/*****************************************************************************/ -/** - * intr_teardown() - un register the interrupts for the device - * - * @param[in] xdev: pointer to xdev - * - * @return none - *****************************************************************************/ -void intr_teardown(struct xlnx_dma_dev *xdev); - -/*****************************************************************************/ -/** - * intr_setup() - register the interrupts for the device - * - * @param[in] xdev: pointer to xdev - * - * @return 0: success - * @return <0: failure - *****************************************************************************/ -int intr_setup(struct xlnx_dma_dev *xdev); - -/*****************************************************************************/ -/** - * intr_ring_teardown() - delete the interrupt ring - * - * @param[in] xdev: pointer to xdev - * - * @return none - *****************************************************************************/ -void intr_ring_teardown(struct xlnx_dma_dev *xdev); - -/*****************************************************************************/ -/** - * intr_context_setup() - set up the interrupt context - * - * @param[in] xdev: pointer to xdev - * - * @return 0: success - * @return <0: failure - *****************************************************************************/ -int intr_context_setup(struct xlnx_dma_dev *xdev); - -/*****************************************************************************/ -/** - * intr_ring_setup() - create the interrupt ring - * - * @param[in] xdev: pointer to xdev - * - * @return 0: success - * @return <0: failure - *****************************************************************************/ -int intr_ring_setup(struct xlnx_dma_dev *xdev); - -/*****************************************************************************/ -/** - * intr_legacy_setup() - setup the legacy interrupt handler - * - * @param[in] descq: descq on which the interrupt needs to be setup - * - * @return 0: success - * @return <0: failure - *****************************************************************************/ -int intr_legacy_setup(struct qdma_descq *descq); - -/*****************************************************************************/ -/** - * intr_legacy_clear() - clear the legacy interrupt handler - * - * @param[in] descq: descq on which the interrupt needs to be cleared - * - * @return 0: success - * @return <0: failure - *****************************************************************************/ -void intr_legacy_clear(struct qdma_descq *descq); - - -/*****************************************************************************/ -/** - * intr_work() - attach the top half for the interrupt - * - * @param[in] work: pointer to struct work_struct - * - * @return none - *****************************************************************************/ -void intr_work(struct work_struct *work); - -/*****************************************************************************/ -/** - * qdma_err_intr_setup() - set up the error interrupt - * - * @param[in] xdev: pointer to xdev - * - * @return none - *****************************************************************************/ -int qdma_err_intr_setup(struct xlnx_dma_dev *xdev); - -/*****************************************************************************/ -/** - * qdma_enable_hw_err() - enable the hw errors - * - * @param[in] xdev: pointer to xdev - * @param[in] hw_err_type: hw error type - * - * @return none - *****************************************************************************/ -void qdma_enable_hw_err(struct xlnx_dma_dev *xdev, u8 hw_err_type); - -/*****************************************************************************/ -/** - * get_intr_ring_index() - get the interrupt ring index based on vector index - * - * @param[in] xdev: pointer to xdev - * @param[in] vector_index: vector index - * - * @return 0: success - * @return <0: failure - *****************************************************************************/ -int get_intr_ring_index(struct xlnx_dma_dev *xdev, u32 vector_index); - -#ifndef __QDMA_VF__ -#ifdef ERR_DEBUG -/*****************************************************************************/ -/** - * err_stat_handler() - error interrupt handler - * - * @param[in] xdev: pointer to xdev - * - * @return none - *****************************************************************************/ -void err_stat_handler(struct xlnx_dma_dev *xdev); -#endif -#endif - -#endif /* LIBQDMA_QDMA_DEVICE_H_ */ - diff --git a/QDMA/linux-kernel/driver/libqdma/qdma_license.h b/QDMA/linux-kernel/driver/libqdma/qdma_license.h deleted file mode 100755 index 31750730d..000000000 --- a/QDMA/linux-kernel/driver/libqdma/qdma_license.h +++ /dev/null @@ -1,22 +0,0 @@ -#ifndef LIBQDMA_QDMA_LICENSE_H_ -#define LIBQDMA_QDMA_LICENSE_H_ -/* - * This file is part of the Xilinx DMA IP Core driver for Linux - * - * Copyright (c) 2017-2022, Xilinx, Inc. All rights reserved. - * Copyright (c) 2022, Advanced Micro Devices, Inc. All rights reserved. - * - * This source code is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * The full GNU General Public License is included in this distribution in - * the file called "COPYING". - */ - -#endif /* LIBQDMA_QDMA_LICENSE_H_ */ diff --git a/QDMA/linux-kernel/driver/libqdma/qdma_mbox.c b/QDMA/linux-kernel/driver/libqdma/qdma_mbox.c deleted file mode 100755 index 0161d04d5..000000000 --- a/QDMA/linux-kernel/driver/libqdma/qdma_mbox.c +++ /dev/null @@ -1,594 +0,0 @@ -/* - * This file is part of the Xilinx DMA IP Core driver for Linux - * - * Copyright (c) 2017-2022, Xilinx, Inc. All rights reserved. - * Copyright (c) 2022, Advanced Micro Devices, Inc. All rights reserved. - * - * This source code is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * The full GNU General Public License is included in this distribution in - * the file called "COPYING". - */ - -#define pr_fmt(fmt) KBUILD_MODNAME ":%s: " fmt, __func__ - -#include -#include -#include -#include -#include -#include -#include -#include - -#include "qdma_compat.h" -#include "xdev.h" -#include "qdma_device.h" -#include "qdma_regs.h" -#include "qdma_context.h" -#include "qdma_intr.h" -#include "qdma_mbox.h" - -#define MBOX_TIMER_INTERVAL (1) - -#ifdef __QDMA_VF__ -#define QDMA_DEV QDMA_DEV_VF -#else -#define QDMA_DEV QDMA_DEV_PF -#endif - -static int mbox_hw_send(struct qdma_mbox *mbox, struct mbox_msg *m) -{ - struct xlnx_dma_dev *xdev = mbox->xdev; - int rv; - - spin_lock_bh(&mbox->hw_tx_lock); - rv = qdma_mbox_send(xdev, QDMA_DEV, m->raw); - spin_unlock_bh(&mbox->hw_tx_lock); - - return rv; -} - -static int mbox_hw_rcv(struct qdma_mbox *mbox, struct mbox_msg *m) -{ - struct xlnx_dma_dev *xdev = mbox->xdev; - int rv; - - spin_lock_bh(&mbox->hw_rx_lock); - memset(m->raw, 0, MBOX_MSG_REG_MAX * - sizeof(uint32_t)); - rv = qdma_mbox_rcv(xdev, QDMA_DEV, m->raw); - spin_unlock_bh(&mbox->hw_rx_lock); - return rv; -} - -/* - * mbox tx message processing - */ -static void mbox_msg_destroy(struct kref *kref) -{ - struct mbox_msg *m = container_of(kref, struct mbox_msg, refcnt); -#ifdef RHEL_RELEASE_VERSION -#if RHEL_RELEASE_VERSION(8, 1) <= RHEL_RELEASE_CODE - vfree(m); -#else - kfree(m); -#endif -#else - kfree(m); -#endif -} - -void __qdma_mbox_msg_free(const char *f, struct mbox_msg *m) -{ - kref_put(&m->refcnt, mbox_msg_destroy); -} - -struct mbox_msg *qdma_mbox_msg_alloc(void) -{ -#ifdef RHEL_RELEASE_VERSION -#if RHEL_RELEASE_VERSION(8, 1) <= RHEL_RELEASE_CODE - struct mbox_msg *m = vmalloc(sizeof(struct mbox_msg)); -#else - struct mbox_msg *m = kzalloc(sizeof(struct mbox_msg), GFP_KERNEL); -#endif -#else - struct mbox_msg *m = kzalloc(sizeof(struct mbox_msg), GFP_KERNEL); -#endif - if (!m) - return NULL; - memset(m, 0, sizeof(struct mbox_msg)); - kref_init(&m->refcnt); - qdma_waitq_init(&m->waitq); - - return m; -} - -int qdma_mbox_msg_send(struct xlnx_dma_dev *xdev, struct mbox_msg *m, - bool wait_resp, unsigned int timeout_ms) -{ - struct qdma_mbox *mbox = &xdev->mbox; - - m->resp_op_matched = 0; - m->wait_resp = wait_resp ? 1 : 0; - m->retry_cnt = (timeout_ms / 1000) + 1; - -#if defined(__QDMA_VF__) - if (xdev->reset_state == RESET_STATE_INVALID) - return -EINVAL; -#endif - /* queue up to ensure order */ - spin_lock_bh(&mbox->list_lock); - list_add_tail(&m->list, &mbox->tx_todo_list); - spin_unlock_bh(&mbox->list_lock); - - /* kick start the tx */ - queue_work(mbox->workq, &mbox->tx_work); - - if (!wait_resp) - return 0; - - qdma_waitq_wait_event_timeout(m->waitq, m->resp_op_matched, - msecs_to_jiffies(timeout_ms)); - - if (!m->resp_op_matched) { - /* delete from mbox list */ - spin_lock_bh(&mbox->list_lock); - list_del(&m->list); - spin_unlock_bh(&mbox->list_lock); - - pr_err("%s mbox timed out. timeout %u ms.\n", - xdev->conf.name, timeout_ms); - - return -EPIPE; - } - - return 0; -} - -/* - * mbox rx message processing - */ -#ifdef __QDMA_VF__ - -static int mbox_rcv_one_msg(struct qdma_mbox *mbox) -{ - struct mbox_msg *m_rcv = &mbox->rx; - struct mbox_msg *m_snd = NULL, *tmp1 = NULL, *tmp2 = NULL; - struct mbox_msg *m_resp = NULL; - int rv = 0; - - if (mbox->xdev->func_id == mbox->xdev->func_id_parent) { - mbox->xdev->func_id = qdma_mbox_vf_func_id_get(m_rcv->raw, - QDMA_DEV); - mbox->xdev->func_id_parent = qdma_mbox_vf_parent_func_id_get( - m_rcv->raw); - } - spin_lock_bh(&mbox->list_lock); - /* check if the sent request expired */ - if (!list_empty(&mbox->rx_pend_list)) { - list_for_each_entry_safe(tmp1, tmp2, &mbox->rx_pend_list, - list) { - if (qdma_mbox_is_msg_response(tmp1->raw, m_rcv->raw)) { - m_snd = tmp1; - m_snd->resp_op_matched = 1; - break; - } - } - } - spin_unlock_bh(&mbox->list_lock); - - if (list_empty(&mbox->rx_pend_list)) { - m_resp = qdma_mbox_msg_alloc(); - if (!m_resp) { - pr_err("Failed to allocate mbox msg\n"); - return -ENOMEM; - } - rv = qdma_mbox_vf_rcv_msg_handler(m_rcv->raw, m_resp->raw); - if (rv == QDMA_MBOX_VF_RESET) { - qdma_mbox_msg_send(mbox->xdev, m_resp, 0, - QDMA_MBOX_MSG_TIMEOUT_MS); - mbox->xdev->reset_state = RESET_STATE_RECV_PF_RESET_REQ; - queue_work(mbox->xdev->workq, - &(mbox->xdev->reset_work)); - } else if (rv == QDMA_MBOX_PF_RESET_DONE) { - mbox->xdev->reset_state = - RESET_STATE_RECV_PF_RESET_DONE; - qdma_waitq_wakeup(&mbox->xdev->wq); - qdma_mbox_msg_send(mbox->xdev, m_resp, 0, - QDMA_MBOX_MSG_TIMEOUT_MS); - - - } else if (rv == QDMA_MBOX_PF_BYE) { - qdma_mbox_msg_send(mbox->xdev, m_resp, 0, - QDMA_MBOX_MSG_TIMEOUT_MS); - mbox->xdev->reset_state = - RESET_STATE_RECV_PF_OFFLINE_REQ; - queue_work(mbox->xdev->workq, - &(mbox->xdev->reset_work)); - } else { - pr_err("func_id=0x%x parent=0x%x", mbox->xdev->func_id, - mbox->xdev->func_id_parent); - } - - } - - if (m_snd) { - /* a matching request is found */ - spin_lock_bh(&mbox->list_lock); - list_del(&m_snd->list); - memcpy(m_snd->raw, m_rcv->raw, MBOX_MSG_REG_MAX * - sizeof(uint32_t)); - /* wake up anyone waiting on the response */ - qdma_waitq_wakeup(&m_snd->waitq); - spin_unlock_bh(&mbox->list_lock); - } - - return 0; -} - -#else -static int mbox_rcv_one_msg(struct qdma_mbox *mbox) -{ - struct mbox_msg *m = &mbox->rx; - struct mbox_msg *m_resp = qdma_mbox_msg_alloc(); - struct mbox_msg *m_snd = NULL, *tmp1 = NULL, *tmp2 = NULL; - int rv; - - if (!m_resp) - return -ENOMEM; - - rv = qdma_mbox_pf_rcv_msg_handler(mbox->xdev, - mbox->xdev->dma_device_index, - mbox->xdev->func_id, - m->raw, m_resp->raw); - - if (rv == QDMA_MBOX_VF_OFFLINE || - rv == QDMA_MBOX_VF_RESET_BYE) { -#ifdef CONFIG_PCI_IOV - uint16_t vf_func_id = qdma_mbox_vf_func_id_get(m->raw, - QDMA_DEV); - - xdev_sriov_vf_offline(mbox->xdev, vf_func_id); -#endif - if (rv == QDMA_MBOX_VF_RESET_BYE) - qdma_mbox_msg_send(mbox->xdev, m_resp, 0, - QDMA_MBOX_MSG_TIMEOUT_MS); - else - qdma_mbox_msg_free(m_resp); - } else if (rv == QDMA_MBOX_VF_ONLINE) { -#ifdef CONFIG_PCI_IOV - uint16_t vf_func_id = qdma_mbox_vf_func_id_get(m->raw, - QDMA_DEV); - - xdev_sriov_vf_online(mbox->xdev, vf_func_id); -#endif - qdma_mbox_msg_send(mbox->xdev, m_resp, 0, - QDMA_MBOX_MSG_TIMEOUT_MS); - } else if (rv == QDMA_MBOX_VF_RESET || - rv == QDMA_MBOX_PF_RESET_DONE || - rv == QDMA_MBOX_PF_BYE) { - spin_lock_bh(&mbox->list_lock); - if (!list_empty(&mbox->rx_pend_list)) { - list_for_each_entry_safe(tmp1, tmp2, - &mbox->rx_pend_list, - list) { - if (qdma_mbox_is_msg_response(tmp1->raw, - m->raw)) { - m_snd = tmp1; - m_snd->resp_op_matched = 1; - break; - } - } - } - if (m_snd) { - list_del(&m_snd->list); - memcpy(m_snd->raw, m->raw, MBOX_MSG_REG_MAX * - sizeof(uint32_t)); - qdma_waitq_wakeup(&m_snd->waitq); - qdma_mbox_msg_free(m_snd); - } - qdma_mbox_msg_free(m_resp); - spin_unlock_bh(&mbox->list_lock); - } else - qdma_mbox_msg_send(mbox->xdev, m_resp, 0, - QDMA_MBOX_MSG_TIMEOUT_MS); - - return 0; -} -#endif - -static inline void mbox_timer_stop(struct qdma_mbox *mbox) -{ - del_timer(&mbox->timer); -} - -static inline void mbox_timer_start(struct qdma_mbox *mbox) -{ - struct timer_list *timer = &mbox->timer; - - qdma_timer_start(timer, MBOX_TIMER_INTERVAL); -} - -/* - * tx & rx workqueue handler - */ -static void mbox_tx_work(struct work_struct *work) -{ - struct qdma_mbox *mbox = container_of(work, struct qdma_mbox, tx_work); - - while (1) { - struct mbox_msg *m = NULL; - - spin_lock_bh(&mbox->list_lock); - if (list_empty(&mbox->tx_todo_list)) { - spin_unlock_bh(&mbox->list_lock); - break; - } - - m = list_first_entry(&mbox->tx_todo_list, - struct mbox_msg, list); - - spin_unlock_bh(&mbox->list_lock); - - if (mbox_hw_send(mbox, m) == 0) { - mbox->send_busy = 0; - spin_lock_bh(&mbox->list_lock); - /* Msg tx successful, remove from list */ - list_del(&m->list); - spin_unlock_bh(&mbox->list_lock); - - /* response needed */ - if (m->wait_resp) { - spin_lock_bh(&mbox->list_lock); - list_add_tail(&m->list, &mbox->rx_pend_list); - spin_unlock_bh(&mbox->list_lock); - } else - qdma_mbox_msg_free(m); - } else { - if (!xlnx_dma_device_flag_check(mbox->xdev, - XDEV_FLAG_OFFLINE)) { - if (!m->wait_resp) { - m->retry_cnt--; - if (!m->retry_cnt) { - spin_lock_bh(&mbox->list_lock); - list_del(&m->list); - spin_unlock_bh( - &mbox->list_lock); - qdma_mbox_msg_free(m); - break; - } - } - mbox->send_busy = 1; - mbox_timer_start(mbox); - } else - qdma_mbox_msg_free(m); - break; - } - } -} - -static void mbox_rx_work(struct work_struct *work) -{ - struct qdma_mbox *mbox = container_of(work, struct qdma_mbox, rx_work); - struct xlnx_dma_dev *xdev = mbox->xdev; - struct mbox_msg *m = &mbox->rx; - int rv; - int mbox_stop = 0; - - rv = mbox_hw_rcv(mbox, m); - while (rv == 0) { - if (unlikely(xlnx_dma_device_flag_check(xdev, - XDEV_FLAG_OFFLINE))) - break; - else if (mbox_rcv_one_msg(mbox) == -EINVAL) - break; - rv = mbox_hw_rcv(mbox, m); - } - - if (rv == -QDMA_ERR_MBOX_ALL_ZERO_MSG) { -#ifdef __QDMA_VF__ - if (xdev->reset_state == RESET_STATE_IDLE) { - mbox_stop = 1; - pr_info("func_id=0x%x parent=0x%x %s: rcv'ed all zeros msg, disable mbox processing.\n", - xdev->func_id, xdev->func_id_parent, - xdev->conf.name); - } -#else - mbox_stop = 1; - pr_info("PF func_id=0x%x %s: rcv'ed all zero mbox msg, disable mbox processing.\n", - xdev->func_id, xdev->conf.name); -#endif - - } else if (xlnx_dma_device_flag_check(xdev, XDEV_FLAG_OFFLINE)) - mbox_stop = 1; - - if (mbox->rx_poll) { - - if (mbox_stop == 1) - mbox_timer_stop(mbox); - else - mbox_timer_start(mbox); - } else { - if (mbox_stop != 0) - qdma_mbox_disable_interrupts(xdev, QDMA_DEV); - } -} - -/* - * non-interrupt mode: use timer for periodic checking of new messages - */ -#if KERNEL_VERSION(4, 15, 0) <= LINUX_VERSION_CODE -static void mbox_timer_handler(struct timer_list *t) -#else -static void mbox_timer_handler(unsigned long arg) -#endif -{ -#if KERNEL_VERSION(4, 15, 0) <= LINUX_VERSION_CODE - struct qdma_mbox *mbox = from_timer(mbox, t, timer); -#else - struct qdma_mbox *mbox = (struct qdma_mbox *)arg; -#endif - if (mbox->rx_poll) - queue_work(mbox->workq, &mbox->rx_work); - if (mbox->send_busy) - queue_work(mbox->workq, &mbox->tx_work); -} - -bool qdma_mbox_is_irq_availabe(struct xlnx_dma_dev *xdev) -{ - /*MBOX is available in all QDMA Soft Devices for vivado release > - * 2019.1 - */ - if (((xdev->version_info.device_type == QDMA_DEVICE_SOFT) && - (xdev->version_info.vivado_release >= QDMA_VIVADO_2019_1))) - return true; - /*MBOX is available in all Versal Hard IP from CPM5 onwards */ - if ((xdev->version_info.ip_type == QDMA_VERSAL_HARD_IP) && - (xdev->version_info.device_type == QDMA_DEVICE_VERSAL_CPM5)) - return true; - - return false; -} - -/* - * mailbox initialization and cleanup - */ -void qdma_mbox_stop(struct xlnx_dma_dev *xdev) -{ - struct qdma_mbox *mbox = &xdev->mbox; - uint8_t retry_count = 100; - int rv = 0; - -#ifndef __QDMA_VF__ - if (!xdev->dev_cap.mailbox_en) - return; -#endif - do { - spin_lock_bh(&mbox->list_lock); - if (list_empty(&mbox->tx_todo_list)) - break; - spin_unlock_bh(&mbox->list_lock); - mdelay(10); /* sleep 10ms for msgs to be sent or freed */ - } while (1); - spin_unlock_bh(&mbox->list_lock); - - do { - rv = qdma_mbox_out_status(xdev, QDMA_DEV); - if (!rv) - break; - retry_count--; - mdelay(10); - } while (retry_count != 0); - mbox_timer_stop(&xdev->mbox); - pr_debug("func_id=%d retry_count=%d\n", xdev->func_id, retry_count); - if (qdma_mbox_is_irq_availabe(xdev)) { - if (!xdev->mbox.rx_poll) - qdma_mbox_disable_interrupts(xdev, QDMA_DEV); - } -} - -void qdma_mbox_start(struct xlnx_dma_dev *xdev) -{ - -#ifndef __QDMA_VF__ - if (!xdev->dev_cap.mailbox_en) - return; -#endif - if (xdev->mbox.rx_poll) - mbox_timer_start(&xdev->mbox); - else - qdma_mbox_enable_interrupts(xdev, QDMA_DEV); -} - -void qdma_mbox_poll_start(struct xlnx_dma_dev *xdev) -{ - -#ifndef __QDMA_VF__ - if (!xdev->dev_cap.mailbox_en) - return; -#endif - xdev->mbox.rx_poll = 1; - qdma_mbox_disable_interrupts(xdev, QDMA_DEV); - mbox_timer_start(&xdev->mbox); -} - -void qdma_mbox_cleanup(struct xlnx_dma_dev *xdev) -{ - struct qdma_mbox *mbox = &xdev->mbox; - - if (mbox->workq) { - mbox_timer_stop(mbox); - if (!xdev->mbox.rx_poll) - qdma_mbox_disable_interrupts(xdev, QDMA_DEV); - flush_workqueue(mbox->workq); - destroy_workqueue(mbox->workq); - } -} - -int qdma_mbox_init(struct xlnx_dma_dev *xdev) -{ - struct qdma_mbox *mbox = &xdev->mbox; - struct timer_list *timer = &mbox->timer; -#ifndef __QDMA_VF__ - int i; -#endif - struct mbox_msg m; - char name[80]; - int rv; - - mbox->xdev = xdev; - - spin_lock_init(&mbox->lock); - spin_lock_init(&mbox->list_lock); - spin_lock_init(&mbox->hw_rx_lock); - spin_lock_init(&mbox->hw_tx_lock); - - INIT_LIST_HEAD(&mbox->tx_todo_list); - INIT_LIST_HEAD(&mbox->rx_pend_list); - INIT_WORK(&mbox->tx_work, mbox_tx_work); - INIT_WORK(&mbox->rx_work, mbox_rx_work); - - snprintf(name, 80, "%s_mbox_wq", xdev->conf.name); - mbox->workq = create_singlethread_workqueue(name); - - if (!mbox->workq) { - pr_info("%s OOM, mbox workqueue.\n", xdev->conf.name); - goto cleanup; - } - - - /* read & discard whatever in the incoming message buffer */ -#ifndef __QDMA_VF__ - for (i = 0; i < 256; i++) - rv = mbox_hw_rcv(mbox, &m); -#else - rv = mbox_hw_rcv(mbox, &m); -#endif - /* ack any received messages in the Q */ - qdma_mbox_hw_init(xdev, QDMA_DEV); - if (qdma_mbox_is_irq_availabe(xdev)) { - if ((xdev->conf.qdma_drv_mode != POLL_MODE) && - (xdev->conf.qdma_drv_mode != LEGACY_INTR_MODE)) { - mbox->rx_poll = 0; - qdma_mbox_enable_interrupts(xdev, QDMA_DEV); - } else - mbox->rx_poll = 1; - } else - mbox->rx_poll = 1; - - qdma_timer_setup(timer, mbox_timer_handler, mbox); - - return 0; - -cleanup: - qdma_mbox_cleanup(xdev); - return -ENOMEM; -} diff --git a/QDMA/linux-kernel/driver/libqdma/qdma_mbox.h b/QDMA/linux-kernel/driver/libqdma/qdma_mbox.h deleted file mode 100755 index e027edaa0..000000000 --- a/QDMA/linux-kernel/driver/libqdma/qdma_mbox.h +++ /dev/null @@ -1,163 +0,0 @@ -/* - * This file is part of the Xilinx DMA IP Core driver for Linux - * - * Copyright (c) 2017-2022, Xilinx, Inc. All rights reserved. - * Copyright (c) 2022, Advanced Micro Devices, Inc. All rights reserved. - * - * This source code is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * The full GNU General Public License is included in this distribution in - * the file called "COPYING". - */ - -#ifndef __QDMA_MBOX_H__ -#define __QDMA_MBOX_H__ - -#include "qdma_compat.h" -#include "qdma_device.h" -#include "qdma_access_common.h" -#include "qdma_mbox_protocol.h" - -/** - * @file - * @brief This file contains the declarations for qdma mailbox apis - * - */ - -/** - * mailbox messages - * - * NOTE: make sure the total message length is <= 128 bytes: - * mbox_msg_hdr: 4 bytes - * body: <= (128 - hdr) bytes - * - */ - -struct mbox_msg { - struct work_struct work; /** workqueue item */ - struct list_head list; /** message list */ - qdma_wait_queue waitq; - struct kref refcnt; - u8 wait_resp; - u8 resp_op_matched; - u16 retry_cnt; - - u32 raw[MBOX_MSG_REG_MAX]; -}; - -/** - * forward declaration of xlnx_dma_dev - */ -struct xlnx_dma_dev; -/** - * @struct - qdma_mbox book keeping - * @brief mailbox book keeping structure - */ -struct qdma_mbox { - /** common lock */ - spinlock_t lock; - /** tx lock */ - spinlock_t hw_tx_lock; - /** rx lock */ - spinlock_t hw_rx_lock; - /** work queue */ - struct workqueue_struct *workq; - /** pointer to device data */ - struct xlnx_dma_dev *xdev; - /** tx work_struct to pass data to tx work queue */ - struct work_struct tx_work; - /** rx work_struct to pass data to rx work queue */ - struct work_struct rx_work; - /** mbox rx message */ - struct mbox_msg rx; - /** list lock */ - spinlock_t list_lock; - /** list of messages waiting to be sent */ - struct list_head tx_todo_list; - /** list of messages waiting for response */ - struct list_head rx_pend_list; - /* flag to monitor tx is busy */ - uint8_t send_busy; - /* flag for rx polling mode */ - uint8_t rx_poll; - - /** timer list */ - struct timer_list timer; - -}; - -#define QDMA_MBOX_MSG_TIMEOUT_MS 10000 /* 10 sec*/ -/*****************************************************************************/ -/** - * qdma_mbox_init() - initialize qdma mailbox - * - * @param xdev: pointer to xlnx_dma_dev - * - * @return 0: success - * @return <0: failure - *****************************************************************************/ -int qdma_mbox_init(struct xlnx_dma_dev *xdev); - -/*****************************************************************************/ -/** - * qdma_mbox_cleanup() - cleanup resources of qdma mailbox - * qdma_mbox_stop() - stop mailbox processing - * qdma_mbox_start() - start mailbox processing - * qdma_mbox_poll_start() - start mailbox processing in poll mode - * - * @param xdev: pointer to xlnx_dma_dev - * - * @return none - *****************************************************************************/ -void qdma_mbox_cleanup(struct xlnx_dma_dev *xdev); -void qdma_mbox_stop(struct xlnx_dma_dev *xdev); -void qdma_mbox_start(struct xlnx_dma_dev *xdev); -void qdma_mbox_poll_start(struct xlnx_dma_dev *xdev); -bool qdma_mbox_is_irq_availabe(struct xlnx_dma_dev *xdev); - - -/*****************************************************************************/ -/** - * qdma_mbox_msg_send() - handler to send a mailbox message - * - * @param xdev: pointer to xlnx_dma_dev - * @param m: mailbox message - * - * @return 0: success - * @return <0: failure - *****************************************************************************/ -int qdma_mbox_msg_send(struct xlnx_dma_dev *xdev, struct mbox_msg *m, - bool wait_resp, unsigned int timeout_ms); - - -/*****************************************************************************/ -/** - * qdma_mbox_msg_alloc() - allocate a mailbox message - * - * @param xdev: pointer to xlnx_dma_dev - * - * @return 0: success - * @return NULL: failure - *****************************************************************************/ -struct mbox_msg *qdma_mbox_msg_alloc(void); - -/*****************************************************************************/ -/** - * __qdma_mbox_msg_free() - free the mailbox message - * - * @param f: function name - * @param m: mailbox message - * - * @return none - *****************************************************************************/ -void __qdma_mbox_msg_free(const char *f, struct mbox_msg *m); -#define qdma_mbox_msg_free(m) __qdma_mbox_msg_free(__func__, m) - -#endif /* #ifndef __QDMA_MBOX_H__ */ diff --git a/QDMA/linux-kernel/driver/libqdma/qdma_platform.c b/QDMA/linux-kernel/driver/libqdma/qdma_platform.c deleted file mode 100755 index d008d92ad..000000000 --- a/QDMA/linux-kernel/driver/libqdma/qdma_platform.c +++ /dev/null @@ -1,145 +0,0 @@ -/* - * This file is part of the Xilinx DMA IP Core driver for Linux - * - * Copyright (c) 2017-2022, Xilinx, Inc. All rights reserved. - * Copyright (c) 2022, Advanced Micro Devices, Inc. All rights reserved. - * - * This source code is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * The full GNU General Public License is included in this distribution in - * the file called "COPYING". - */ -#include "qdma_platform.h" -#include "qdma_regs.h" -#include "qdma_access_errors.h" -#include -#include - -static struct err_code_map error_code_map_list[] = { - {QDMA_SUCCESS, 0}, - {QDMA_ERR_INV_PARAM, EINVAL}, - {QDMA_ERR_NO_MEM, ENOMEM}, - {QDMA_ERR_HWACC_BUSY_TIMEOUT, EBUSY}, - {QDMA_ERR_HWACC_INV_CONFIG_BAR, EINVAL}, - {QDMA_ERR_HWACC_NO_PEND_LEGCY_INTR, EINVAL}, - {QDMA_ERR_HWACC_BAR_NOT_FOUND, EINVAL}, - {QDMA_ERR_HWACC_FEATURE_NOT_SUPPORTED, EINVAL}, - {QDMA_ERR_RM_RES_EXISTS, EPERM}, - {QDMA_ERR_RM_RES_NOT_EXISTS, EINVAL}, - {QDMA_ERR_RM_DEV_EXISTS, EPERM}, - {QDMA_ERR_RM_DEV_NOT_EXISTS, EINVAL}, - {QDMA_ERR_RM_NO_QUEUES_LEFT, EPERM}, - {QDMA_ERR_RM_QMAX_CONF_REJECTED, EPERM}, - {QDMA_ERR_MBOX_FMAP_WR_FAILED, EIO}, - {QDMA_ERR_MBOX_NUM_QUEUES, EINVAL}, - {QDMA_ERR_MBOX_INV_QID, EINVAL}, - {QDMA_ERR_MBOX_INV_RINGSZ, EINVAL}, - {QDMA_ERR_MBOX_INV_BUFSZ, EINVAL}, - {QDMA_ERR_MBOX_INV_CNTR_TH, EINVAL}, - {QDMA_ERR_MBOX_INV_TMR_TH, EINVAL}, - {QDMA_ERR_MBOX_INV_MSG, EINVAL}, - {QDMA_ERR_MBOX_SEND_BUSY, EBUSY}, - {QDMA_ERR_MBOX_NO_MSG_IN, EINVAL}, - {QDMA_ERR_MBOX_REG_READ_FAILED, EIO}, - {QDMA_ERR_MBOX_ALL_ZERO_MSG, EINVAL}, -}; - -/** - * mutex used for resource management APIs - */ -static DEFINE_MUTEX(res_mutex); - -void *qdma_calloc(uint32_t num_blocks, uint32_t size) -{ - return kzalloc((num_blocks * (size_t)size), GFP_KERNEL); -} - -void qdma_memfree(void *memptr) -{ - kfree(memptr); -} - -void qdma_udelay(u32 delay_us) -{ - udelay(delay_us); -} - -int qdma_reg_access_lock(void *dev_hndl) -{ - struct xlnx_dma_dev *xdev = (struct xlnx_dma_dev *)dev_hndl; - - spin_lock(&xdev->hw_prg_lock); - - return 0; -} - -int qdma_reg_access_release(void *dev_hndl) -{ - struct xlnx_dma_dev *xdev = (struct xlnx_dma_dev *)dev_hndl; - - spin_unlock(&xdev->hw_prg_lock); - - return 0; -} - -u32 qdma_reg_read(void *dev_hndl, u32 reg_offst) -{ - struct xlnx_dma_dev *xdev = (struct xlnx_dma_dev *)dev_hndl; - - return readl(xdev->regs + reg_offst); -} - -void qdma_reg_write(void *dev_hndl, u32 reg_offst, u32 val) -{ - struct xlnx_dma_dev *xdev = (struct xlnx_dma_dev *)dev_hndl; - - writel(val, xdev->regs + reg_offst); -} - -void qdma_resource_lock_take(void) -{ - mutex_lock(&res_mutex); -} - -void qdma_resource_lock_give(void) -{ - mutex_unlock(&res_mutex); -} - -void qdma_get_hw_access(void *dev_hndl, struct qdma_hw_access **hw) -{ - struct xlnx_dma_dev *xdev = (struct xlnx_dma_dev *)dev_hndl; - *hw = &xdev->hw; -} - -void qdma_strncpy(char *dest, const char *src, size_t n) -{ - strncpy(dest, src, n); -} - - -int qdma_get_err_code(int acc_err_code) -{ - acc_err_code *= -1; - return -(error_code_map_list[acc_err_code].err_code); -} - -int qdma_io_wmb(void) -{ - /* - * TODO: Write memory barrier(wmb) calls are happening differently - * for DPDK and Linux drivers. DPDK driver is calling wmb() before - * pidx/cmpt_cidx updates, where as linux driver calls wmb() after - * pidx/cmpt_cidx updates. As linux driver performance numbers - * are good with current changes, so keeping this function - * as place holder for furure changes related to memory barriers. - */ - return 0; -} diff --git a/QDMA/linux-kernel/driver/libqdma/qdma_platform_env.h b/QDMA/linux-kernel/driver/libqdma/qdma_platform_env.h deleted file mode 100755 index 6649bfc76..000000000 --- a/QDMA/linux-kernel/driver/libqdma/qdma_platform_env.h +++ /dev/null @@ -1,33 +0,0 @@ -/* - * This file is part of the Xilinx DMA IP Core driver for Linux - * - * Copyright (c) 2017-2022, Xilinx, Inc. All rights reserved. - * Copyright (c) 2022, Advanced Micro Devices, Inc. All rights reserved. - * - * This source code is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * The full GNU General Public License is included in this distribution in - * the file called "COPYING". - */ -#ifndef LIBQDMA_QDMA_PLATFORM_ENV_H_ -#define LIBQDMA_QDMA_PLATFORM_ENV_H_ - -#include -#include - -#define QDMA_SNPRINTF_S(arg1, arg2, arg3, ...) \ - snprintf(arg1, arg3, ##__VA_ARGS__) - -#define qdma_log_info(x_, ...) pr_info(x_, ##__VA_ARGS__) -#define qdma_log_warning(x_, ...) pr_warn(x_, ##__VA_ARGS__) -#define qdma_log_error(x_, ...) pr_err(x_, ##__VA_ARGS__) -#define qdma_log_debug(x_, ...) pr_debug(x_, ##__VA_ARGS__) - -#endif /* LIBQDMA_QDMA_PLATFORM_ENV_H_ */ diff --git a/QDMA/linux-kernel/driver/libqdma/qdma_regs.c b/QDMA/linux-kernel/driver/libqdma/qdma_regs.c deleted file mode 100755 index 920176cfd..000000000 --- a/QDMA/linux-kernel/driver/libqdma/qdma_regs.c +++ /dev/null @@ -1,610 +0,0 @@ -/* - * This file is part of the Xilinx DMA IP Core driver for Linux - * - * Copyright (c) 2017-2022, Xilinx, Inc. All rights reserved. - * Copyright (c) 2022, Advanced Micro Devices, Inc. All rights reserved. - * - * This source code is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * The full GNU General Public License is included in this distribution in - * the file called "COPYING". - */ - -#define pr_fmt(fmt) KBUILD_MODNAME ":%s: " fmt, __func__ - -#include "qdma_regs.h" - -#include -#include -#include -#include -#include - -#include "xdev.h" -#include "qdma_device.h" -#include "qdma_descq.h" -#include "qdma_st_c2h.h" -#include "qdma_access_common.h" -#include "qdma_resource_mgmt.h" - -int qdma_set_ring_sizes(struct xlnx_dma_dev *xdev, u8 index, - u8 count, u32 *glbl_rng_sz) -{ - int i = 0; - - if (!xdev || !glbl_rng_sz) - return -EINVAL; - - /* Adding 1 for the wrap around descriptor and status descriptor */ - for (i = index; i < (index + count); i++) - *(glbl_rng_sz + i) += 1; - - if (xdev->hw.qdma_global_csr_conf(xdev, index, count, glbl_rng_sz, - QDMA_CSR_RING_SZ, QDMA_HW_ACCESS_WRITE)) - return -EINVAL; - - return 0; -} - -int qdma_get_ring_sizes(struct xlnx_dma_dev *xdev, u8 index, - u8 count, u32 *glbl_rng_sz) -{ - int i = 0; - - if (!xdev || !glbl_rng_sz) - return -EINVAL; - - if (xdev->hw.qdma_global_csr_conf(xdev, index, count, glbl_rng_sz, - QDMA_CSR_RING_SZ, QDMA_HW_ACCESS_READ)) - return -EINVAL; - - /* Subtracting 1 for the wrap around descriptor and status descriptor */ - for (i = index; i < (index + count); i++) - *(glbl_rng_sz + i) -= 1; - - return 0; -} - -/*****************************************************************************/ -/** - * qdma_device_read_config_register() - read dma config. register - * - * @param[in] dev_hndl: dev_hndl returned from qdma_device_open() - * @param[in] reg_addr: register address - * @param[out] value: pointer to hold the read value - * - * Return: 0 for success and <0 for error - *****************************************************************************/ -int qdma_device_read_config_register(unsigned long dev_hndl, - unsigned int reg_addr, u32 *value) -{ - struct xlnx_dma_dev *xdev = (struct xlnx_dma_dev *)dev_hndl; - - if (!xdev) { - pr_err("dev_hndl is NULL"); - return -EINVAL; - } - - if (xdev_check_hndl(__func__, xdev->conf.pdev, dev_hndl) < 0) { - pr_err("Invalid dev_hndl passed"); - return -EINVAL; - } - - *value = readl(xdev->regs + reg_addr); - - return 0; -} - -/*****************************************************************************/ -/** - * qdma_device_write_config_register() - write dma config. register - * - * @param[in] dev_hndl: dev_hndl returned from qdma_device_open() - * @param[in] reg_addr: register address - * @param[in] value: register value to be writen - * - * Return: 0 for success and <0 for error - *****************************************************************************/ -int qdma_device_write_config_register(unsigned long dev_hndl, - unsigned int reg_addr, unsigned int val) -{ - struct xlnx_dma_dev *xdev = (struct xlnx_dma_dev *)dev_hndl; - - if (!xdev) { - pr_err("dev_hndl is NULL"); - return -EINVAL; - } - - if (xdev_check_hndl(__func__, xdev->conf.pdev, dev_hndl) < 0) { - pr_err("Invalid dev_hndl passed"); - return -EINVAL; - } - - pr_debug("%s reg 0x%x, w 0x%08x.\n", xdev->conf.name, reg_addr, val); - writel(val, xdev->regs + reg_addr); - - return 0; -} - - -#ifdef __QDMA_VF__ -#include "qdma_mbox.h" - -int qdma_csr_read(struct xlnx_dma_dev *xdev, struct global_csr_conf *csr) -{ - struct mbox_msg *m = qdma_mbox_msg_alloc(); - int rv, i; - struct qdma_csr_info csr_info; - - if (!m) - return -ENOMEM; - - memset(&csr_info, 0, sizeof(csr_info)); - - qdma_mbox_compose_csr_read(xdev->func_id, m->raw); - rv = qdma_mbox_msg_send(xdev, m, 1, QDMA_MBOX_MSG_TIMEOUT_MS); - if (rv < 0) - goto free_msg; - - rv = qdma_mbox_vf_csr_get(m->raw, &csr_info); - if (!rv) { - for (i = 0; i < QDMA_GLOBAL_CSR_ARRAY_SZ; i++) { - csr->ring_sz[i] = (uint32_t)csr_info.ringsz[i]; - csr->c2h_buf_sz[i] = (uint32_t)csr_info.bufsz[i]; - csr->c2h_timer_cnt[i] = (uint32_t)csr_info.timer_cnt[i]; - csr->c2h_cnt_th[i] = (uint32_t)csr_info.cnt_thres[i]; - } - csr->wb_intvl = csr_info.wb_intvl; - } else { - pr_err("csr info read failed, rv = %d", rv); - rv = -EINVAL; - } - - -free_msg: - qdma_mbox_msg_free(m); - return rv; -} - -#ifdef QDMA_CSR_REG_UPDATE -int qdma_global_csr_set(unsigned long dev_hndl, u8 index, u8 count, - struct global_csr_conf *csr) -{ - struct xlnx_dma_dev *xdev = (struct xlnx_dma_dev *)dev_hndl; - - if (xdev_check_hndl(__func__, xdev->conf.pdev, dev_hndl) < 0) - return -EINVAL; - - pr_info("VF %d setting csr NOT allowed.\n", xdev->func_id); - return -EINVAL; -} -#endif -#else /* ifdef __QDMA_VF__ */ - -static void qdma_sort_c2h_cntr_th_values(struct xlnx_dma_dev *xdev) -{ - uint8_t i, idx = 0, j = 0; - uint8_t c2h_cntr_val = xdev->csr_info.c2h_cnt_th[0]; - uint8_t least_max = 0; - int ref_idx = -1; - -get_next_idx: - for (i = 0; i < QDMA_GLOBAL_CSR_ARRAY_SZ; i++) { - if ((ref_idx >= 0) && (ref_idx == i)) - continue; - if (xdev->csr_info.c2h_cnt_th[i] < least_max) - continue; - c2h_cntr_val = xdev->csr_info.c2h_cnt_th[i]; - idx = i; - break; - } - for (; i < QDMA_GLOBAL_CSR_ARRAY_SZ; i++) { - if ((ref_idx >= 0) && (ref_idx == i)) - continue; - if (xdev->csr_info.c2h_cnt_th[i] < least_max) - continue; - if (c2h_cntr_val >= xdev->csr_info.c2h_cnt_th[i]) { - c2h_cntr_val = xdev->csr_info.c2h_cnt_th[i]; - idx = i; - } - } - xdev->sorted_c2h_cntr_idx[j] = idx; - ref_idx = idx; - j++; - idx = j; - least_max = c2h_cntr_val; - if (j < QDMA_GLOBAL_CSR_ARRAY_SZ) - goto get_next_idx; -} - -int qdma_csr_read(struct xlnx_dma_dev *xdev, struct global_csr_conf *csr) -{ - int rv = 0; - - rv = xdev->hw.qdma_global_csr_conf(xdev, 0, - QDMA_GLOBAL_CSR_ARRAY_SZ, csr->ring_sz, - QDMA_CSR_RING_SZ, QDMA_HW_ACCESS_READ); - if (unlikely(rv < 0)) { - pr_err("Failed to read global ring sizes, err = %d", rv); - return xdev->hw.qdma_get_error_code(rv); - } - - rv = xdev->hw.qdma_global_writeback_interval_conf(xdev, - &csr->wb_intvl, - QDMA_HW_ACCESS_READ); - if (unlikely(rv < 0)) { - if (rv != -QDMA_ERR_HWACC_FEATURE_NOT_SUPPORTED) { - pr_err("Failed to read write back interval, err = %d", - rv); - return xdev->hw.qdma_get_error_code(rv); - } - pr_warn("Hardware Feature not supported"); - } - - rv = xdev->hw.qdma_global_csr_conf(xdev, 0, - QDMA_GLOBAL_CSR_ARRAY_SZ, csr->c2h_buf_sz, - QDMA_CSR_BUF_SZ, QDMA_HW_ACCESS_READ); - if (unlikely(rv < 0)) { - if (rv != -QDMA_ERR_HWACC_FEATURE_NOT_SUPPORTED) { - pr_err("Failed to read global buffer sizes, err = %d", - rv); - return xdev->hw.qdma_get_error_code(rv); - } - pr_warn("Hardware Feature not supported"); - } - - rv = xdev->hw.qdma_global_csr_conf(xdev, 0, - QDMA_GLOBAL_CSR_ARRAY_SZ, csr->c2h_timer_cnt, - QDMA_CSR_TIMER_CNT, QDMA_HW_ACCESS_READ); - if (unlikely(rv < 0)) { - if (rv != -QDMA_ERR_HWACC_FEATURE_NOT_SUPPORTED) { - pr_err("Failed to read global timer count, err = %d", - rv); - return xdev->hw.qdma_get_error_code(rv); - } - pr_warn("Hardware Feature not supported"); - } - - rv = xdev->hw.qdma_global_csr_conf(xdev, 0, - QDMA_GLOBAL_CSR_ARRAY_SZ, csr->c2h_cnt_th, - QDMA_CSR_CNT_TH, QDMA_HW_ACCESS_READ); - if (unlikely(rv < 0)) { - if (rv != -QDMA_ERR_HWACC_FEATURE_NOT_SUPPORTED) { - pr_err("Failed to read global counter threshold, err = %d", - rv); - return xdev->hw.qdma_get_error_code(rv); - } - pr_warn("Hardware Feature not supported"); - } - qdma_sort_c2h_cntr_th_values(xdev); - return 0; -} - -#ifdef QDMA_CSR_REG_UPDATE -int qdma_global_csr_set(unsigned long dev_hndl, u8 index, u8 count, - struct global_csr_conf *csr) -{ - int rv = 0; - struct xlnx_dma_dev *xdev = (struct xlnx_dma_dev *)dev_hndl; - - if (xdev_check_hndl(__func__, xdev->conf.pdev, dev_hndl) < 0) - return -EINVAL; - - /** If qdma_get_active_queue_count() > 0, - * cannot modify global CSR. - */ - if (qdma_get_active_queue_count(xdev->dma_device_index)) { - pr_err("xdev %s, FMAP prog done, cannot modify global CSR\n", - xdev->mod_name); - return -EINVAL; - } - if (xdev->hw.qdma_global_writeback_interval_conf(xdev, csr->wb_intvl, - QDMA_HW_ACCESS_WRITE)) - return -EINVAL; - if (xdev->hw.qdma_global_csr_conf(xdev, index, count, csr->ring_sz, - QDMA_CSR_RING_SZ, QDMA_HW_ACCESS_WRITE)) - return -EINVAL; - if (xdev->hw.qdma_global_csr_conf(xdev, index, count, - csr->c2h_timer_cnt, - QDMA_CSR_TIMER_CNT, QDMA_HW_ACCESS_WRITE)) - return -EINVAL; - if (xdev->hw.qdma_global_csr_conf(xdev, index, count, csr->c2h_cnt_th, - QDMA_CSR_CNT_TH, QDMA_HW_ACCESS_WRITE)) - return -EINVAL; - if (xdev->hw.qdma_global_csr_conf(xdev, index, count, csr->c2h_buf_sz, - QDMA_CSR_BUF_SZ, QDMA_HW_ACCESS_WRITE)) - return -EINVAL; - - rv = qdma_csr_read(xdev, &xdev->csr_info); - if (unlikely(rv < 0)) - return rv; - - return 0; -} -#endif -#endif - -int qdma_global_csr_get(unsigned long dev_hndl, u8 index, u8 count, - struct global_csr_conf *csr) -{ - struct xlnx_dma_dev *xdev = (struct xlnx_dma_dev *)dev_hndl; - int i = 0; - - if (!xdev) { - pr_err("dev_hndl is NULL"); - return -EINVAL; - } - - if (xdev_check_hndl(__func__, xdev->conf.pdev, dev_hndl) < 0) { - pr_err("Invalid dev_hndl passed"); - return -EINVAL; - } - - if ((index + count) > QDMA_GLOBAL_CSR_ARRAY_SZ) { - pr_err("%s: Invalid index=%u and count=%u > %d", - __func__, index, count, - QDMA_GLOBAL_CSR_ARRAY_SZ); - return -EINVAL; - } - - /** If qdma_get_active_queue_count() > 0, - * read the stored xdev csr values. - */ - if (qdma_get_active_queue_count(xdev->dma_device_index)) - memcpy(csr, &xdev->csr_info, sizeof(struct global_csr_conf)); - else - qdma_csr_read(xdev, csr); - - /** Subtracting 1 for the wrap around descriptor and status descriptor - * This same logic is present in qdma_get/set_ring_sizes() API - * In case of any changes to this number, make sure to update in - * all these places - */ - for (i = index; i < (index + count); i++) - csr->ring_sz[i]--; - - return 0; -} - -int qdma_device_flr_quirk_set(struct pci_dev *pdev, unsigned long dev_hndl) -{ - struct xlnx_dma_dev *xdev = (struct xlnx_dma_dev *)dev_hndl; - int rv; - - if (!dev_hndl) { - pr_err("Invalid dev_hndl passed"); - return -EINVAL; - } - - if (xdev_check_hndl(__func__, pdev, dev_hndl) < 0) { - pr_err("Invalid dev_hndl passed"); - return -EINVAL; - } - - if (xdev->conf.pdev != pdev) { - pr_err("Invalid pdev passed: pci_dev(0x%lx) != pdev(0x%lx)\n", - (unsigned long)xdev->conf.pdev, (unsigned long)pdev); - return -EINVAL; - } - - if (!xdev->dev_cap.flr_present) { - pr_info("FLR not present, therefore skipping FLR reset\n"); - return 0; - } - - if (!dev_hndl || xdev_check_hndl(__func__, pdev, dev_hndl) < 0) - return -EINVAL; - -#ifndef __QDMA_VF__ - rv = xdev->hw.qdma_initiate_flr(xdev, 0); -#else - rv = xdev->hw.qdma_initiate_flr(xdev, 1); -#endif - if (rv) - return -EINVAL; - - return 0; -} - -int qdma_device_flr_quirk_check(struct pci_dev *pdev, unsigned long dev_hndl) -{ - struct xlnx_dma_dev *xdev = (struct xlnx_dma_dev *)dev_hndl; - int rv; - uint8_t flr_done = 0; - - if (!dev_hndl) { - pr_err("Invalid dev_hndl passed"); - return -EINVAL; - } - - if (xdev_check_hndl(__func__, pdev, dev_hndl) < 0) { - pr_err("Invalid dev_hndl passed"); - return -EINVAL; - } - - if (xdev->conf.pdev != pdev) { - pr_err("Invalid pdev passed: pci_dev(0x%lx) != pdev(0x%lx)\n", - (unsigned long)xdev->conf.pdev, (unsigned long)pdev); - return -EINVAL; - } - - if (!xdev->dev_cap.flr_present) { - pr_info("FLR not present, therefore skipping FLR reset status\n"); - return 0; - } - -#ifndef __QDMA_VF__ - rv = xdev->hw.qdma_is_flr_done(xdev, 0, &flr_done); -#else - rv = xdev->hw.qdma_is_flr_done(xdev, 1, &flr_done); -#endif - if (rv) - return -EINVAL; - - if (!flr_done) - pr_info("%s, flr status stuck\n", xdev->conf.name); - - return 0; -} - -int qdma_device_version_info(unsigned long dev_hndl, - struct qdma_version_info *version_info) -{ - int rv = 0; - struct qdma_hw_version_info info; - struct xlnx_dma_dev *xdev = (struct xlnx_dma_dev *)dev_hndl; - - if (!xdev) { - pr_err("dev_hndl is NULL"); - return -EINVAL; - } - - if (!version_info) { - pr_err("version_info is NULL"); - return -EINVAL; - } - - if (xdev_check_hndl(__func__, xdev->conf.pdev, dev_hndl) < 0) { - pr_err("Invalid dev_hndl passed"); - return -EINVAL; - } - - memset(&info, 0, sizeof(info)); -#ifndef __QDMA_VF__ - rv = xdev->hw.qdma_get_version(xdev, QDMA_DEV_PF, &info); -#else - rv = xdev->hw.qdma_get_version(xdev, QDMA_DEV_VF, &info); -#endif - if (rv < 0) { - pr_err("failed to get version with error = %d", rv); - return xdev->hw.qdma_get_error_code(rv); - } - - strncpy(version_info->ip_str, info.qdma_ip_type_str, - sizeof(version_info->ip_str) - 1); - strncpy(version_info->rtl_version_str, info.qdma_rtl_version_str, - sizeof(version_info->rtl_version_str) - 1); - strncpy(version_info->vivado_release_str, - info.qdma_vivado_release_id_str, - sizeof(version_info->vivado_release_str) - 1); - strncpy(version_info->device_type_str, - info.qdma_device_type_str, - sizeof(version_info->device_type_str) - 1); - return 0; -} - -#ifndef __QDMA_VF__ -void qdma_device_attributes_get(struct xlnx_dma_dev *xdev) -{ - struct qdma_dev_attributes dev_info; - - memset(&dev_info, 0, sizeof(dev_info)); - - xdev->hw.qdma_get_device_attributes(xdev, &xdev->dev_cap); - - pr_info("%s: num_pfs:%d, num_qs:%d, flr_present:%d, st_en:%d, mm_en:%d, mm_cmpt_en:%d, mailbox_en:%d, mm_channel_max:%d, qid2vec_ctx:%d, cmpt_ovf_chk_dis:%d, mailbox_intr:%d, sw_desc_64b:%d, cmpt_desc_64b:%d, dynamic_bar:%d, legacy_intr:%d, cmpt_trig_count_timer:%d", - xdev->conf.name, - xdev->dev_cap.num_pfs, - xdev->dev_cap.num_qs, - xdev->dev_cap.flr_present, - xdev->dev_cap.st_en, - xdev->dev_cap.mm_en, - xdev->dev_cap.mm_cmpt_en, - xdev->dev_cap.mailbox_en, - xdev->dev_cap.mm_channel_max, - xdev->dev_cap.qid2vec_ctx, - xdev->dev_cap.cmpt_ovf_chk_dis, - xdev->dev_cap.mailbox_intr, - xdev->dev_cap.sw_desc_64b, - xdev->dev_cap.cmpt_desc_64b, - xdev->dev_cap.dynamic_bar, - xdev->dev_cap.legacy_intr, - xdev->dev_cap.cmpt_trig_count_timer); -} -#endif - -int qdma_queue_cmpl_ctrl(unsigned long dev_hndl, unsigned long id, - struct qdma_cmpl_ctrl *cctrl, bool set) -{ - int rv = 0; - struct xlnx_dma_dev *xdev = (struct xlnx_dma_dev *)dev_hndl; - struct qdma_descq *descq; - - /** make sure that the dev_hndl passed is Valid */ - if (!xdev) { - pr_err("dev_hndl is NULL"); - return -EINVAL; - } - - if (xdev_check_hndl(__func__, xdev->conf.pdev, dev_hndl) < 0) { - pr_err("Invalid dev_hndl passed"); - return -EINVAL; - } - - descq = qdma_device_get_descq_by_id(xdev, id, NULL, 0, 1); - if (!descq) { - pr_err("Invalid qid: %ld", id); - return -EINVAL; - } - - if (set) { - lock_descq(descq); - - descq->cmpt_cidx_info.trig_mode = - descq->conf.cmpl_trig_mode = - cctrl->trigger_mode; - descq->cmpt_cidx_info.timer_idx = - descq->conf.cmpl_timer_idx = cctrl->timer_idx; - descq->cmpt_cidx_info.counter_idx = - descq->conf.cmpl_cnt_th_idx = cctrl->cnt_th_idx; - descq->cmpt_cidx_info.irq_en = - descq->conf.cmpl_en_intr = cctrl->cmpl_en_intr; - descq->cmpt_cidx_info.wrb_en = - descq->conf.cmpl_stat_en = cctrl->en_stat_desc; - - descq->cmpt_cidx_info.wrb_cidx = descq->cidx_cmpt; - rv = queue_cmpt_cidx_update(descq->xdev, - descq->conf.qidx, &descq->cmpt_cidx_info); - if (unlikely(rv < 0)) { - pr_err("%s: Failed to update cmpt cidx\n", - descq->conf.name); - unlock_descq(descq); - return rv; - } - - unlock_descq(descq); - - } else { - lock_descq(descq); - /* read the setting */ - rv = queue_cmpt_cidx_read(descq->xdev, - descq->conf.qidx, &descq->cmpt_cidx_info); - if (unlikely(rv < 0)) { - pr_err("%s: Failed to read cmpt cidx\n", - descq->conf.name); - unlock_descq(descq); - return rv; - } - - cctrl->trigger_mode = descq->conf.cmpl_trig_mode = - descq->cmpt_cidx_info.trig_mode; - cctrl->timer_idx = descq->conf.cmpl_timer_idx = - descq->cmpt_cidx_info.timer_idx; - cctrl->cnt_th_idx = descq->conf.cmpl_cnt_th_idx = - descq->cmpt_cidx_info.counter_idx; - cctrl->en_stat_desc = descq->conf.cmpl_stat_en = - descq->cmpt_cidx_info.wrb_en; - cctrl->cmpl_en_intr = descq->conf.cmpl_en_intr = - descq->cmpt_cidx_info.irq_en; - unlock_descq(descq); - } - - return 0; -} diff --git a/QDMA/linux-kernel/driver/libqdma/qdma_regs.h b/QDMA/linux-kernel/driver/libqdma/qdma_regs.h deleted file mode 100755 index 4e1d1bb10..000000000 --- a/QDMA/linux-kernel/driver/libqdma/qdma_regs.h +++ /dev/null @@ -1,185 +0,0 @@ -/* - * This file is part of the Xilinx DMA IP Core driver for Linux - * - * Copyright (c) 2017-2022, Xilinx, Inc. All rights reserved. - * Copyright (c) 2022, Advanced Micro Devices, Inc. All rights reserved. - * - * This source code is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * The full GNU General Public License is included in this distribution in - * the file called "COPYING". - */ - -#ifndef __QDMA_REGS_H__ -#define __QDMA_REGS_H__ - -#include -#include "xdev.h" - -#define QDMA_REG_SZ_IN_BYTES 4 - -#define DESC_SZ_64B 3 -#define DESC_SZ_8B_BYTES 8 -#define DESC_SZ_16B_BYTES 16 -#define DESC_SZ_32B_BYTES 32 -#define DESC_SZ_64B_BYTES 64 - -#ifndef __QDMA_VF__ - -/* - * monitor - */ -#define QDMA_REG_C2H_STAT_AXIS_PKG_CMP 0xA94 - -#endif /* ifndef __QDMA_VF__ */ - -/* - * descriptor & writeback status - */ -/** - * @struct - qdma_mm_desc - * @brief memory mapped descriptor format - */ -struct qdma_mm_desc { - /** source address */ - __be64 src_addr; - /** flags */ - __be32 flag_len; - /** reserved 32 bits */ - __be32 rsvd0; - /** destination address */ - __be64 dst_addr; - /** reserved 64 bits */ - __be64 rsvd1; -}; - -#define S_DESC_F_DV 28 -#define S_DESC_F_SOP 29 -#define S_DESC_F_EOP 30 - - -#define S_H2C_DESC_F_SOP 1 -#define S_H2C_DESC_F_EOP 2 - - -#define S_H2C_DESC_NUM_GL 0 -#define M_H2C_DESC_NUM_GL 0x7U -#define V_H2C_DESC_NUM_GL(x) ((x) << S_H2C_DESC_NUM_GL) - -#define S_H2C_DESC_NUM_CDH 3 -#define M_H2C_DESC_NUM_CDH 0xFU -#define V_H2C_DESC_NUM_CDH(x) ((x) << S_H2C_DESC_NUM_CDH) - -#define S_H2C_DESC_F_ZERO_CDH 13 -#define S_H2C_DESC_F_EOT 14 -#define S_H2C_DESC_F_REQ_CMPL_STATUS 15 - -/* FIXME pld_len and flags members are part of custom descriptor format needed - * by example design for ST loopback and desc bypass - */ -/** - * @struct - qdma_h2c_desc - * @brief memory mapped descriptor format - */ -struct qdma_h2c_desc { - __be16 cdh_flags; /**< cdh flags */ - __be16 pld_len; /**< current packet length */ - __be16 len; /**< total packet length */ - __be16 flags; /**< descriptor flags */ - __be64 src_addr; /**< source address */ -}; - -/** - * @struct - qdma_c2h_desc - * @brief qdma c2h descriptor - */ -struct qdma_c2h_desc { - __be64 dst_addr; /**< destination address */ -}; - -/** - * @struct - qdma_desc_cmpl_status - * @brief qdma writeback descriptor - */ -struct qdma_desc_cmpl_status { - __be16 pidx; /**< producer index */ - __be16 cidx; /**< consumer index */ - __be32 rsvd; /**< reserved 32 bits */ -}; - -#define S_C2H_CMPT_ENTRY_F_FORMAT 0 -#define F_C2H_CMPT_ENTRY_F_FORMAT (1 << S_C2H_CMPT_ENTRY_F_FORMAT) -#define DFORMAT0_CMPL_MASK 0xF /* udd starts at bit 4 */ -#define DFORMAT1_CMPL_MASK 0xFFFFF /* udd starts at bit 20 */ - - -#define S_C2H_CMPT_ENTRY_F_COLOR 1 -#define F_C2H_CMPT_ENTRY_F_COLOR (1 << S_C2H_CMPT_ENTRY_F_COLOR) - -#define S_C2H_CMPT_ENTRY_F_ERR 2 -#define F_C2H_CMPT_ENTRY_F_ERR (1 << S_C2H_CMPT_ENTRY_F_ERR) - -#define S_C2H_CMPT_ENTRY_F_DESC_USED 3 -#define F_C2H_CMPT_ENTRY_F_DESC_USED (1 << S_C2H_CMPT_ENTRY_F_DESC_USED) - -#define S_C2H_CMPT_ENTRY_LENGTH 4 -#define M_C2H_CMPT_ENTRY_LENGTH 0xFFFFU -#define L_C2H_CMPT_ENTRY_LENGTH 16 -#define V_C2H_CMPT_ENTRY_LENGTH(x) \ - (((x) & M_C2H_CMPT_ENTRY_LENGTH) << S_C2H_CMPT_ENTRY_LENGTH) - -#define S_C2H_CMPT_ENTRY_F_EOT 20 -#define F_C2H_CMPT_ENTRY_F_EOT (1 << S_C2H_CMPT_ENTRY_F_EOT) - -#define S_C2H_CMPT_ENTRY_F_USET_INTR 21 - -#define S_C2H_CMPT_USER_DEFINED 22 -#define V_C2H_CMPT_USER_DEFINED(x) ((x) << S_C2H_CMPT_USER_DEFINED) - -#define M_C2H_CMPT_ENTRY_DMA_INFO 0xFFFFFF -#define L_C2H_CMPT_ENTRY_DMA_INFO 3 /* 20 bits */ -/** - * @struct - qdma_c2h_cmpt_cmpl_status - * @brief qdma completion data descriptor - */ -struct qdma_c2h_cmpt_cmpl_status { - __be16 pidx; /**< producer index */ - __be16 cidx; /**< consumer index */ - __be32 color_isr_status; /**< isr color and status */ -}; -#define S_C2H_CMPT_F_COLOR 0 - -#define S_C2H_CMPT_INT_STATE 1 -#define M_C2H_CMPT_INT_STATE 0x3U - -/* - * HW API - */ - -#include "xdev.h" - -#define __read_reg(xdev, reg_addr) (readl(xdev->regs + reg_addr)) -#ifdef DEBUG__ -#define __write_reg(xdev, reg_addr, val) \ - do { \ - pr_debug("%s, reg 0x%x, val 0x%x.\n", \ - xdev->conf.name, reg_addr, (u32)val); \ - writel(val, xdev->regs + reg_addr); \ - } while (0) -#else -#define __write_reg(xdev, reg_addr, val) (writel(val, xdev->regs + reg_addr)) -#endif /* #ifdef DEBUG__ */ - -#ifndef __QDMA_VF__ -void qdma_device_attributes_get(struct xlnx_dma_dev *xdev); - -#endif /* #ifndef __QDMA_VF__ */ - -#endif diff --git a/QDMA/linux-kernel/driver/libqdma/qdma_sriov.c b/QDMA/linux-kernel/driver/libqdma/qdma_sriov.c deleted file mode 100755 index 4911bf811..000000000 --- a/QDMA/linux-kernel/driver/libqdma/qdma_sriov.c +++ /dev/null @@ -1,279 +0,0 @@ -/* - * This file is part of the Xilinx DMA IP Core driver for Linux - * - * Copyright (c) 2017-2022, Xilinx, Inc. All rights reserved. - * Copyright (c) 2022, Advanced Micro Devices, Inc. All rights reserved. - * - * This source code is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * The full GNU General Public License is included in this distribution in - * the file called "COPYING". - */ - -#define pr_fmt(fmt) KBUILD_MODNAME ":%s: " fmt, __func__ - -#include -#include -#include - -#include "xdev.h" -#include "qdma_mbox.h" -#include - -#ifdef __QDMA_VF__ -int xdev_sriov_vf_offline(struct xlnx_dma_dev *xdev, u16 func_id) -{ - int rv; - struct mbox_msg *m = qdma_mbox_msg_alloc(); - - if (!m) - return -ENOMEM; - - qdma_mbox_compose_vf_offline(xdev->func_id, m->raw); - /** For sending BYE message, retry to send multiple - * times before giving up by giving non-zero timeout value - */ - rv = qdma_mbox_msg_send(xdev, m, 0, QDMA_MBOX_MSG_TIMEOUT_MS); - if (rv < 0) - pr_info("%s, send bye failed %d.\n", xdev->conf.name, rv); - - return rv; -} - -int xdev_sriov_vf_reset_offline(struct xlnx_dma_dev *xdev) -{ - int rv; - struct mbox_msg *m = qdma_mbox_msg_alloc(); - - if (!m) - return -ENOMEM; - - qdma_mbox_compose_vf_reset_offline(xdev->func_id, m->raw); - - rv = qdma_mbox_msg_send(xdev, m, 1, QDMA_MBOX_MSG_TIMEOUT_MS); - if (rv < 0) - pr_err("%s, send reset bye failed %d.\n", xdev->conf.name, rv); - - qdma_mbox_msg_free(m); - return rv; -} -int xdev_sriov_vf_online(struct xlnx_dma_dev *xdev, u16 func_id) -{ - int rv; - int qbase = -1; - struct mbox_msg *m = qdma_mbox_msg_alloc(); - - if (!m) - return -ENOMEM; - - qmda_mbox_compose_vf_online(xdev->func_id, 0, &qbase, m->raw); - - rv = qdma_mbox_msg_send(xdev, m, 1, QDMA_MBOX_MSG_TIMEOUT_MS); - if (rv < 0) { - pr_err("%s, send hello failed %d.\n", xdev->conf.name, rv); - qdma_mbox_msg_free(m); - return rv; - } - - rv = qdma_mbox_vf_dev_info_get(m->raw, &xdev->dev_cap, - &xdev->dma_device_index); - if (rv < 0) { - pr_info("%s, failed to get dev info %d.\n", - xdev->conf.name, rv); - rv = -EINVAL; - } else { - pr_info("%s: num_pfs:%d, num_qs:%d, flr_present:%d, st_en:%d, mm_en:%d, mm_cmpt_en:%d, mailbox_en:%d, mm_channel_max:%d, qid2vec_ctx:%d, cmpt_ovf_chk_dis:%d, mailbox_intr:%d, sw_desc_64b:%d, cmpt_desc_64b:%d, dynamic_bar:%d, legacy_intr:%d, cmpt_trig_count_timer:%d", - xdev->conf.name, - xdev->dev_cap.num_pfs, - xdev->dev_cap.num_qs, - xdev->dev_cap.flr_present, - xdev->dev_cap.st_en, - xdev->dev_cap.mm_en, - xdev->dev_cap.mm_cmpt_en, - xdev->dev_cap.mailbox_en, - xdev->dev_cap.mm_channel_max, - xdev->dev_cap.qid2vec_ctx, - xdev->dev_cap.cmpt_ovf_chk_dis, - xdev->dev_cap.mailbox_intr, - xdev->dev_cap.sw_desc_64b, - xdev->dev_cap.cmpt_desc_64b, - xdev->dev_cap.dynamic_bar, - xdev->dev_cap.legacy_intr, - xdev->dev_cap.cmpt_trig_count_timer); - } - - qdma_mbox_msg_free(m); - return rv; -} - -#elif defined(CONFIG_PCI_IOV) - -void xdev_sriov_disable(struct xlnx_dma_dev *xdev) -{ - struct pci_dev *pdev = xdev->conf.pdev; - unsigned int sleep_timeout = (50 * xdev->vf_count); /* 50ms per vf */ - - if (!xdev->vf_count) - return; - - pci_disable_sriov(pdev); - - qdma_waitq_wait_event_timeout(xdev->wq, (xdev->vf_count == 0), - msecs_to_jiffies(sleep_timeout)); - - qdma_mbox_stop(xdev); - kfree(xdev->vf_info); - xdev->vf_info = NULL; - xdev->vf_count = 0; - -} - -int xdev_sriov_enable(struct xlnx_dma_dev *xdev, int num_vfs) -{ - struct pci_dev *pdev = xdev->conf.pdev; - int current_vfs = pci_num_vf(pdev); - struct qdma_vf_info *vf; - int i; - int rv; - - if (current_vfs) { - dev_err(&pdev->dev, "%d VFs already enabled!n", current_vfs); - return current_vfs; - } - - vf = kmalloc(num_vfs * (sizeof(struct qdma_vf_info)), GFP_KERNEL); - if (!vf) { - pr_info("%s failed to allocate memory for VFs, %d * %ld.\n", - xdev->conf.name, num_vfs, sizeof(struct qdma_vf_info)); - return -ENOMEM; - } - - for (i = 0; i < num_vfs; i++) - vf[i].func_id = QDMA_FUNC_ID_INVALID; - - qdma_waitq_init(&xdev->wq); - xdev->vf_count = num_vfs; - xdev->vf_info = vf; - - pr_debug("%s: req %d, current %d, assigned %d.\n", - xdev->conf.name, num_vfs, current_vfs, pci_vfs_assigned(pdev)); - - qdma_mbox_start(xdev); - - rv = pci_enable_sriov(pdev, num_vfs); - if (rv) { - pr_info("%s, enable sriov %d failed %d.\n", - xdev->conf.name, num_vfs, rv); - xdev_sriov_disable(xdev); - return 0; - } - - pr_debug("%s: done, req %d, current %d, assigned %d.\n", - xdev->conf.name, num_vfs, pci_num_vf(pdev), - pci_vfs_assigned(pdev)); - - return num_vfs; -} - -int qdma_device_sriov_config(struct pci_dev *pdev, unsigned long dev_hndl, - int num_vfs) -{ - struct xlnx_dma_dev *xdev = (struct xlnx_dma_dev *)dev_hndl; - int rv; - - if (!dev_hndl) - return -EINVAL; - - rv = xdev_check_hndl(__func__, pdev, dev_hndl); - if (rv < 0) - return rv; - - /* if zero disable sriov */ - if (!num_vfs) { - xdev_sriov_disable(xdev); - return 0; - } - - if (!xdev->dev_cap.mailbox_en) { - dev_err(&pdev->dev, "Mailbox not enabled in this device"); - return -EPERM; - } - - rv = xdev_sriov_enable(xdev, num_vfs); - if (rv < 0) - return rv; - - return xdev->vf_count; -} - -void xdev_sriov_vf_offline(struct xlnx_dma_dev *xdev, u16 func_id) -{ - struct qdma_vf_info *vf = (struct qdma_vf_info *)xdev->vf_info; - int i; - - xdev->vf_count_online--; - for (i = 0; i < xdev->vf_count; i++, vf++) { - if (vf->func_id == func_id) { - /** func_id cannot be marked invalid in the PF FLR flow. - * This is because, after PF comes back up - * it should have valid func_id list to be able to - * send out the RESET_DONE msg - */ - if (xdev->reset_state == RESET_STATE_IDLE) - vf->func_id = QDMA_FUNC_ID_INVALID; - vf->qbase = 0; - vf->qmax = 0; - } - } - - qdma_waitq_wakeup(&xdev->wq); -} - -int xdev_sriov_vf_online(struct xlnx_dma_dev *xdev, u16 func_id) -{ - struct qdma_vf_info *vf = (struct qdma_vf_info *)xdev->vf_info; - int i; - - xdev->vf_count_online++; - - if (xdev->reset_state == RESET_STATE_IDLE) { - for (i = 0; i < xdev->vf_count; i++, vf++) { - if (vf->func_id == QDMA_FUNC_ID_INVALID) { - vf->func_id = func_id; - return 0; - } - } - pr_info("%s, func 0x%x, NO free slot.\n", xdev->conf.name, - func_id); - qdma_waitq_wakeup(&xdev->wq); - return -EINVAL; - } else - return 0; -} - -int xdev_sriov_vf_fmap(struct xlnx_dma_dev *xdev, u16 func_id, - unsigned short qbase, unsigned short qmax) -{ - struct qdma_vf_info *vf = (struct qdma_vf_info *)xdev->vf_info; - int i; - - for (i = 0; i < xdev->vf_count; i++, vf++) { - if (vf->func_id == func_id) { - vf->qbase = qbase; - vf->qmax = qmax; - return 0; - } - } - - pr_info("%s, func 0x%x, NO match.\n", xdev->conf.name, func_id); - return -EINVAL; -} - -#endif /* if defined(CONFIG_PCI_IOV) && !defined(__QDMA_VF__) */ diff --git a/QDMA/linux-kernel/driver/libqdma/qdma_st_c2h.c b/QDMA/linux-kernel/driver/libqdma/qdma_st_c2h.c deleted file mode 100755 index 80a8d7397..000000000 --- a/QDMA/linux-kernel/driver/libqdma/qdma_st_c2h.c +++ /dev/null @@ -1,1286 +0,0 @@ -/* - * This file is part of the Xilinx DMA IP Core driver for Linux - * - * Copyright (c) 2017-2022, Xilinx, Inc. All rights reserved. - * Copyright (c) 2022, Advanced Micro Devices, Inc. All rights reserved. - * - * This source code is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * The full GNU General Public License is included in this distribution in - * the file called "COPYING". - */ - -#define pr_fmt(fmt) KBUILD_MODNAME ":%s: " fmt, __func__ - -#include "qdma_descq.h" - -#include -#include -#include - -#include "qdma_device.h" -#include "qdma_intr.h" -#include "qdma_regs.h" -#include "qdma_thread.h" -#include "qdma_context.h" -#include "thread.h" -#include "qdma_compat.h" -#include "qdma_st_c2h.h" -#include "qdma_access_common.h" -#include "qdma_ul_ext.h" -#include "version.h" - -/* - * ST C2H descq (i.e., freelist) RX buffers - */ - -static inline void flq_free_one(struct qdma_sw_sg *sdesc, - struct qdma_c2h_desc *desc) -{ - if (sdesc) { - if (sdesc->dma_addr) { - desc->dst_addr = 0UL; - sdesc->dma_addr = 0UL; - } - - if (sdesc->pg) { - sdesc->pg = NULL; - sdesc->offset = 0; - } - } else - pr_err("%s: sdesc is NULL", __func__); - -} - -static inline int flq_fill_one(struct qdma_descq *descq, - struct qdma_sw_sg *sdesc, - struct qdma_c2h_desc *desc) -{ - struct qdma_flq *flq = (struct qdma_flq *)descq->flq; - struct qdma_sw_pg_sg *pg_sdesc; - unsigned int pg_idx = 0; - unsigned int buf_sz; - - if (!flq) { - pr_err("%s: flq is NULL", __func__); - return -EINVAL; - } - - if (flq->num_pages == 0) { - pr_err("%s: flq->num_pages is NULL", __func__); - return -EINVAL; - } - - buf_sz = flq->desc_buf_size; - pg_idx = (flq->alloc_idx & flq->num_pgs_mask); - - if (pg_idx >= flq->num_pages) { - pr_err("%s: pg_idx %d is Invalid", - __func__, - pg_idx); - return -EINVAL; - } - - pg_sdesc = flq->pg_sdesc + pg_idx; - if (!pg_sdesc || !pg_sdesc->pg_base) { - pr_err("%s: pg_sdesc is NULL", __func__); - return -EINVAL; - } - - if (pg_sdesc->pg_offset + buf_sz > flq->max_pg_offset) { - pr_err("%s: memory full, alloc_idx %u, recycle_idx = %u offset = %u, pg_idx = %u", - __func__, - flq->alloc_idx, - flq->recycle_idx, - pg_sdesc->pg_offset, - pg_idx); - return -ENOMEM; - } - - - sdesc->pg = pg_sdesc->pg_base; - sdesc->offset = pg_sdesc->pg_offset; - sdesc->dma_addr = pg_sdesc->pg_dma_base_addr + pg_sdesc->pg_offset; - sdesc->len = descq->conf.c2h_bufsz; - desc->dst_addr = sdesc->dma_addr; -#if KERNEL_VERSION(4, 6, 0) < LINUX_VERSION_CODE - page_ref_inc(pg_sdesc->pg_base); -#else - atomic_inc(&(pg_sdesc->pg_base->_count)); -#endif - pg_sdesc->pg_offset += buf_sz; - - if ((pg_sdesc->pg_offset + buf_sz) > flq->max_pg_offset) - flq->alloc_idx++; - - return 0; -} - -static inline void flq_unmap_page_one(struct qdma_sw_pg_sg *pg_sdesc, - struct device *dev, - unsigned char pg_order) -{ - if (pg_sdesc && pg_sdesc->pg_dma_base_addr) { - dma_unmap_page(dev, pg_sdesc->pg_dma_base_addr, - PAGE_SIZE << pg_order, - DMA_FROM_DEVICE); - pg_sdesc->pg_dma_base_addr = 0UL; - } -} - -static inline void flq_free_page_one(struct qdma_sw_pg_sg *pg_sdesc, - struct device *dev, - unsigned char pg_order, - unsigned int pg_shift) -{ - unsigned int page_count = 0; - unsigned int i = 0; - - if (pg_sdesc && pg_sdesc->pg_base) { - /* +1 for dma_unmap*/ - page_count = (pg_sdesc->pg_offset >> pg_shift) + 1; - - flq_unmap_page_one(pg_sdesc, dev, pg_order); - - for (i = 0; i < page_count; i++) - put_page(pg_sdesc->pg_base); - - pg_sdesc->pg_base = NULL; - pg_sdesc->pg_dma_base_addr = 0UL; - } -} - -void descq_flq_free_page_resource(struct qdma_descq *descq) -{ - struct xlnx_dma_dev *xdev = descq->xdev; - struct device *dev = &xdev->conf.pdev->dev; - struct qdma_flq *flq = (struct qdma_flq *)descq->flq; - struct qdma_sw_pg_sg *pg_sdesc = flq->pg_sdesc; - unsigned char pg_order = flq->desc_pg_order; - int i; - - for (i = 0; i < flq->num_pages; i++, pg_sdesc++) - flq_free_page_one(pg_sdesc, dev, - pg_order, flq->desc_pg_shift); - - kfree(flq->pg_sdesc); - flq->pg_sdesc = NULL; - - memset(flq, 0, sizeof(struct qdma_flq)); -} - -void descq_flq_free_resource(struct qdma_descq *descq) -{ - struct qdma_flq *flq = (struct qdma_flq *)descq->flq; - struct qdma_sw_sg *sdesc = flq->sdesc; - struct qdma_c2h_desc *desc = flq->desc; - int i; - - /* It can never be null beyond this */ - if (!sdesc) { - pr_err("%s: sdesc is Invalid", - __func__); - return; - } - - for (i = 0; i < flq->size; i++, sdesc++, desc++) - flq_free_one(sdesc, desc); - - kfree(flq->sdesc); - flq->sdesc = NULL; - flq->sdesc_info = NULL; - -} - - -static inline int flq_fill_page_one(struct qdma_sw_pg_sg *pg_sdesc, - struct device *dev, - int node, unsigned char pg_order, gfp_t gfp) -{ - struct page *pg; - dma_addr_t mapping; - - pg = alloc_pages_node(node, __GFP_COMP | gfp, pg_order); - if (unlikely(!pg)) { - pr_err("%s: failed to allocate the pages, order %d.\n", - __func__, - pg_order); - return -ENOMEM; - } - - mapping = dma_map_page(dev, pg, 0, (PAGE_SIZE << pg_order), - DMA_FROM_DEVICE); - if (unlikely(dma_mapping_error(dev, mapping))) { - dev_err(dev, "page 0x%p mapping error 0x%llx.\n", - pg, (unsigned long long)mapping); - __free_pages(pg, pg_order); - return -EINVAL; - } - - pg_sdesc->pg_base = pg; - pg_sdesc->pg_dma_base_addr = mapping; - pg_sdesc->pg_offset = 0; - return 0; -} - -int descq_flq_alloc_resource(struct qdma_descq *descq) -{ - struct xlnx_dma_dev *xdev = descq->xdev; - struct qdma_flq *flq = (struct qdma_flq *)descq->flq; - struct device *dev = &xdev->conf.pdev->dev; - int node = dev_to_node(dev); - struct qdma_sw_pg_sg *pg_sdesc = NULL; - struct qdma_sw_sg *sdesc, *prev = NULL; - struct qdma_sdesc_info *sinfo, *sprev = NULL; - struct qdma_c2h_desc *desc = flq->desc; - int i; - int rv = 0; - /* find the most significant bit number */ - unsigned int div_bits = 0; - - div_bits = flq->desc_pg_shift; - flq->num_bufs_per_pg = - (flq->max_pg_offset >> div_bits); - - if (flq->num_bufs_per_pg == 0) { - pr_err("%s: conf_c2h_bufsz = %d, flq_c2h_buf_size = %d, flq->max_pg_offset = %d, flq->num_bufs_per_pg = %d, flq->desc_pg_order = %d, div_bits = %d", - __func__, - descq->conf.c2h_bufsz, - flq->desc_buf_size, - flq->max_pg_offset, - flq->num_bufs_per_pg, - flq->desc_pg_order, - div_bits); - return -EINVAL; - } - - flq->num_pages = (flq->size / flq->num_bufs_per_pg) + - ((flq->size % flq->num_bufs_per_pg) == 0 ? 0 : 1); - flq->num_pages = get_next_powof2(flq->num_pages); - /* without this, alloc_idx and recycle_idx - * will toeing each other creating a mess - */ - if (flq->num_pages < flq->size) - flq->num_pages = (flq->num_pages << 1); - flq->num_pgs_mask = (flq->num_pages - 1); - - pr_debug("%s: conf_c2h_bufsz = %d, flq_c2h_buf_size = %d, num_bufs_per_pg = %d, num_pages = %d, flq->size = %d", - __func__, - descq->conf.c2h_bufsz, - flq->desc_buf_size, - flq->num_bufs_per_pg, - flq->num_pages, - flq->size); - - pg_sdesc = kzalloc_node(flq->num_pages * - (sizeof(struct qdma_sw_pg_sg)), - GFP_KERNEL, node); - - if (!pg_sdesc) { - pr_err("%s: OOM, sz %d * %ld.\n", - __func__, - flq->num_pages, - (sizeof(struct qdma_sw_pg_sg))); - return -ENOMEM; - } - flq->pg_sdesc = pg_sdesc; - - for (pg_sdesc = flq->pg_sdesc, i = 0; - i < flq->num_pages; i++, pg_sdesc++) { - rv = flq_fill_page_one(pg_sdesc, dev, node, - flq->desc_pg_order, GFP_KERNEL); - if (rv < 0) { - descq_flq_free_page_resource(descq); - return rv; - } - } - - sdesc = kzalloc_node(flq->size * (sizeof(struct qdma_sw_sg) + - sizeof(struct qdma_sdesc_info)), - GFP_KERNEL, node); - if (!sdesc) { - pr_err("%s: OOM, sz %d * %ld.\n", - __func__, - flq->size, - ((sizeof(struct qdma_sw_sg) + - sizeof(struct qdma_sdesc_info)))); - descq_flq_free_page_resource(descq); - return -ENOMEM; - } - - flq->sdesc = sdesc; - flq->sdesc_info = sinfo = (struct qdma_sdesc_info *)(sdesc + flq->size); - flq->alloc_idx = 0; - - /* make the flq to be a linked list ring */ - for (i = 0; i < flq->size; i++, prev = sdesc, sdesc++, - sprev = sinfo, sinfo++) { - if (prev) - prev->next = sdesc; - if (sprev) - sprev->next = sinfo; - } - - /* last entry's next points to the first entry */ - prev->next = flq->sdesc; - sprev->next = flq->sdesc_info; - - for (sdesc = flq->sdesc, i = 0; i < flq->size; i++, sdesc++, desc++) { - rv = flq_fill_one(descq, sdesc, desc); - if (rv < 0) { - descq_flq_free_resource(descq); - descq_flq_free_page_resource(descq); - return rv; - } - } - - return 0; -} - -static inline int flq_refill_pages(struct qdma_descq *descq, - int count, bool recycle, gfp_t gfp) -{ - struct xlnx_dma_dev *xdev = descq->xdev; - struct device *dev = &xdev->conf.pdev->dev; - int node = dev_to_node(dev); - struct qdma_flq *flq = (struct qdma_flq *)descq->flq; - unsigned int n_recycle_index = flq->recycle_idx; - /* find the most significant bit number */ - unsigned int div_bits = flq->desc_pg_shift; - struct qdma_sw_pg_sg *pg_sdesc = flq->pg_sdesc; - unsigned int free_bufs_in_pg; - unsigned int i = 0, j = 0; - int rv; - - for (i = 0; i < count; ) { - pg_sdesc = flq->pg_sdesc + - (n_recycle_index & flq->num_pgs_mask); - - if (!pg_sdesc) { - pr_err("pg_sdesc is NULL"); - return -EINVAL; - } - - free_bufs_in_pg = (pg_sdesc->pg_offset >> div_bits); - free_bufs_in_pg = - min_t(unsigned int, free_bufs_in_pg, count - i); - for (j = 0; j < free_bufs_in_pg; j++) { - pg_sdesc->pg_offset -= flq->desc_buf_size; - if (!recycle && !descq->conf.fp_descq_c2h_packet) - put_page(pg_sdesc->pg_base); - } - i += free_bufs_in_pg; - BUG_ON(i > count); - if (!pg_sdesc->pg_offset) - n_recycle_index++; - } - - if (recycle) - flq->recycle_idx = n_recycle_index; - else { - while (1) { - pg_sdesc = flq->pg_sdesc + - (flq->recycle_idx & flq->num_pgs_mask); - - if (!pg_sdesc) { - pr_err("pg_sdesc is NULL"); - return -EINVAL; - } - - /** Stop the allocation when the pg_offset of - * the page is not 0 and - * recycle index is less than the alloc index - */ - if (pg_sdesc->pg_offset || - flq->recycle_idx == flq->alloc_idx) - break; - - flq_unmap_page_one(pg_sdesc, dev, flq->desc_pg_order); - put_page(pg_sdesc->pg_base); - rv = flq_fill_page_one(pg_sdesc, - dev, node, flq->desc_pg_order, gfp); - if (rv < 0) - break; - - flq->recycle_idx++; - } - } - - return 0; -} - -static int qdma_flq_refill(struct qdma_descq *descq, int idx, int count, - int recycle, gfp_t gfp) -{ - struct qdma_flq *flq = (struct qdma_flq *)descq->flq; - struct qdma_sw_sg *sdesc = flq->sdesc + idx; - struct qdma_c2h_desc *desc = flq->desc + idx; - struct qdma_sdesc_info *sinfo = flq->sdesc_info + idx; - int i; - int rv; - - if (!recycle) { - rv = flq_refill_pages(descq, count, recycle, gfp); - if (unlikely(rv < 0)) { - pr_err("%s: flq_refill_pages failed rv %d error", - descq->conf.name, rv); - } - } - - for (i = 0; i < count; i++, idx++, sdesc++, desc++, sinfo++) { - if (idx == flq->size) { - idx = 0; - sdesc = flq->sdesc; - desc = flq->desc; - sinfo = flq->sdesc_info; - } - - if (recycle) { - sdesc->len = descq->conf.c2h_bufsz; - } else { - flq_free_one(sdesc, desc); - rv = flq_fill_one(descq, sdesc, desc); - if (unlikely(rv < 0)) { - pr_err("%s: rv %d error", - descq->conf.name, rv); - if (rv == -ENOMEM) - flq->alloc_fail++; - else - flq->mapping_err++; - - break; - } - } - sinfo->fbits = 0; - descq->avail++; - } - - if (list_empty(&descq->work_list) && - list_empty(&descq->pend_list)) { - descq->pend_list_empty = 1; - if (descq->q_stop_wait) - qdma_waitq_wakeup(&descq->pend_list_wq); - } - - return i; -} - -/* - * - */ -int descq_st_c2h_read(struct qdma_descq *descq, struct qdma_request *req, - bool update_pidx, bool refill) -{ - struct qdma_sgt_req_cb *cb = qdma_req_cb_get(req); - struct qdma_flq *flq = (struct qdma_flq *)descq->flq; - unsigned int pidx = flq->pidx_pend; - struct qdma_sw_sg *fsg = flq->sdesc + pidx; - struct qdma_sw_sg *tsg = req->sgl; - unsigned int fsgcnt = ring_idx_delta(descq->pidx, pidx, flq->size); - unsigned int tsgoff = cb->sg_offset; - unsigned int foff = 0; - int i = 0, j = 0; - int rv = 0; - unsigned int copied = 0; - - if (!fsgcnt) - return 0; - - if (cb->sg_idx) { - for (; tsg && j < cb->sg_idx; j++) - tsg = tsg->next; - - if (!tsg) { - pr_err("tsg error, index %u/%u.\n", - cb->sg_idx, req->sgcnt); - return -EINVAL; - } - } - - while ((i < fsgcnt) && tsg) { - unsigned int flen = fsg->len; - unsigned char *faddr = page_address(fsg->pg) + fsg->offset; - - foff = 0; - - while (flen && tsg) { - unsigned int toff = tsg->offset + tsgoff; - unsigned int copy = min_t(unsigned int, flen, - tsg->len - tsgoff); - u64 *pkt_tx_time = - (u64 *)(page_address(fsg->pg) + fsg->offset); - - if (!req->no_memcpy) { - memcpy(page_address(tsg->pg) + toff, - faddr, copy); - flush_dcache_page(tsg->pg); - } - if (descq->conf.ping_pong_en && - *pkt_tx_time == descq->ping_pong_tx_time) { - u64 latency; - - pr_debug("pkt tx_time=%llu\n", *pkt_tx_time); - - latency = descq->ping_pong_rx_time - - *pkt_tx_time; - - // calculate minimum latency - if (descq->xdev->ping_pong_lat_min > latency - || descq->xdev->ping_pong_lat_min == 0) { - pr_info("ping_pong_lat_min=%llu curr=%llu\n", - descq->xdev->ping_pong_lat_min, - latency); - descq->xdev->ping_pong_lat_min = - latency; - } - - // calculate max latency - if (descq->xdev->ping_pong_lat_max < latency - || descq->xdev->ping_pong_lat_max == 0) { - pr_info("ping_pong_lat_max=%llu curr=%llu\n", - descq->xdev->ping_pong_lat_max, - latency); - descq->xdev->ping_pong_lat_max = - latency; - } - - // sum of latencies for avg - descq->xdev->ping_pong_lat_total += latency; - } else if (descq->conf.ping_pong_en && - *pkt_tx_time != descq->ping_pong_tx_time) { - pr_err("Error: pkt tx=%llu descq->tx_time=%llu %p\n", - *pkt_tx_time, - descq->ping_pong_tx_time, - descq); - } - - - faddr += copy; - flen -= copy; - foff += copy; - tsgoff += copy; - copied += copy; - - if (tsgoff == tsg->len) { - tsg = tsg->next; - tsgoff = 0; - j++; - } - } - - if (foff == fsg->len) { - pidx = ring_idx_incr(pidx, 1, descq->conf.rngsz); - i++; - foff = 0; - fsg = fsg->next; - } - } - - incr_cmpl_desc_cnt(descq, i); - - if (refill && i) - qdma_flq_refill(descq, flq->pidx_pend, i, 1, GFP_ATOMIC); - - flq->pidx_pend = ring_idx_incr(flq->pidx_pend, i, flq->size); - if (foff) { - fsg->offset += foff; - fsg->len -= foff; - } - - if (i && update_pidx) { - i = ring_idx_decr(flq->pidx_pend, 1, flq->size); - descq->pidx_info.pidx = i; - rv = queue_pidx_update(descq->xdev, descq->conf.qidx, - descq->conf.q_type, &descq->pidx_info); - if (unlikely(rv < 0)) { - pr_err("%s: Failed to update pidx\n", - descq->conf.name); - return -EINVAL; - } - } - - cb->sg_idx = j; - cb->sg_offset = tsgoff; - cb->left -= copied; - - flq->pkt_dlen -= copied; - - return copied; -} - -static int qdma_c2h_packets_proc_dflt(struct qdma_descq *descq) -{ - struct qdma_sgt_req_cb *cb = NULL, *tmp = NULL; - - list_for_each_entry_safe(cb, tmp, &descq->pend_list, list) { - int rv; - - /* check for zero length dma */ - if (!cb->left) { - pr_debug("%s, cb 0x%p pending, zero len.\n", - descq->conf.name, cb); - - qdma_sgt_req_done(descq, cb, 0); - return 0; - } - - rv = descq_st_c2h_read(descq, (struct qdma_request *)cb, 0, 0); - if (rv < 0) { - pr_info("req 0x%p, error %d.\n", cb, rv); - qdma_sgt_req_done(descq, cb, rv); - continue; - } - - if (!cb->left) - qdma_sgt_req_done(descq, cb, 0); - else - break; /* no more data available */ - } - - return 0; -} - -void cmpt_next(struct qdma_descq *descq) -{ - u8 *desc_cmpt_cur = (u8 *)descq->desc_cmpt_cur + descq->cmpt_entry_len; - - descq->desc_cmpt_cur = desc_cmpt_cur; - if (unlikely(++descq->cidx_cmpt == descq->conf.rngsz_cmpt)) { - descq->cidx_cmpt = 0; - descq->color ^= 1; - descq->desc_cmpt_cur = descq->desc_cmpt; - } -} - -static inline bool is_new_cmpl_entry(struct qdma_descq *descq, - struct qdma_ul_cmpt_info *cmpl) -{ - return cmpl->f.color == descq->color; -} - -int parse_cmpl_entry(struct qdma_descq *descq, struct qdma_ul_cmpt_info *cmpl) -{ - __be64 *cmpt = (__be64 *)descq->desc_cmpt_cur; - - dma_rmb(); - -#if 0 - print_hex_dump(KERN_INFO, "cmpl entry ", DUMP_PREFIX_OFFSET, - 16, 1, (void *)cmpt, descq->cmpt_entry_len, - false); -#endif - - cmpl->entry = cmpt; - cmpl->f.format = (cmpt[0] & F_C2H_CMPT_ENTRY_F_FORMAT) ? 1 : 0; - cmpl->f.color = (cmpt[0] & F_C2H_CMPT_ENTRY_F_COLOR) ? 1 : 0; - cmpl->f.err = (cmpt[0] & F_C2H_CMPT_ENTRY_F_ERR) ? 1 : 0; - cmpl->f.eot = (cmpt[0] & F_C2H_CMPT_ENTRY_F_EOT) ? 1 : 0; - cmpl->f.desc_used = (cmpt[0] & F_C2H_CMPT_ENTRY_F_DESC_USED) ? 1 : 0; - if (!cmpl->f.format && cmpl->f.desc_used) { - cmpl->len = (cmpt[0] >> S_C2H_CMPT_ENTRY_LENGTH) & - M_C2H_CMPT_ENTRY_LENGTH; - /* zero length transfer allowed */ - } else - cmpl->len = 0; - - return 0; -} - -static int get_fl_nr(unsigned int len, - unsigned int c2h_bufsz, - unsigned int pg_shift, unsigned int pg_mask, - unsigned int *last_len) -{ - unsigned int l_len = len; - int l_fl_nr = 1; - - if ((len & (len-1)) == 0) { - /* pr_info("Len is ^2"); */ - l_fl_nr = len ? ((len + pg_mask) >> pg_shift) : 1; - l_len = (len & pg_mask); - if (l_len == 0) - l_len = c2h_bufsz; - } else { - /* pr_info("Len is non ^2"); */ - if (len) { - if (len <= c2h_bufsz) - l_fl_nr = 1; - else { - l_fl_nr = 0; - while (l_len >= c2h_bufsz) { - l_fl_nr++; - l_len -= c2h_bufsz; - } - - if (l_len) - l_fl_nr++; - else - l_len = c2h_bufsz; - } - } - - } - - *last_len = l_len; - return l_fl_nr; -} - -static int rcv_pkt(struct qdma_descq *descq, struct qdma_ul_cmpt_info *cmpl, - unsigned int len) -{ - unsigned int pidx = cmpl->pidx; - struct qdma_flq *flq = (struct qdma_flq *)descq->flq; - unsigned int pg_shift = flq->desc_pg_shift; - unsigned int pg_mask = (1 << pg_shift) - 1; - unsigned int rngsz = descq->conf.rngsz; - /* zero length still uses one descriptor */ - unsigned int l_len = 0; - int fl_nr = get_fl_nr(len, - descq->conf.c2h_bufsz, - pg_shift, pg_mask, &l_len); - unsigned int last = ring_idx_incr(cmpl->pidx, fl_nr - 1, rngsz); - unsigned int next = ring_idx_incr(last, 1, rngsz); - struct qdma_sw_sg *sdesc = flq->sdesc + last; - unsigned int cidx_next = ring_idx_incr(descq->cidx_cmpt, 1, - descq->conf.rngsz_cmpt); - - if (!len) - sdesc->len = 0; - else - sdesc->len = l_len; - - if (descq->avail < fl_nr) - return -EBUSY; - - descq->avail -= fl_nr; - - - if (descq->conf.fp_descq_c2h_packet) { - int rv = descq->conf.fp_descq_c2h_packet(descq->q_hndl, - descq->conf.quld, len, fl_nr, flq->sdesc + pidx, - descq->conf.cmpl_udd_en ? - (unsigned char *)cmpl->entry : NULL); - - if (rv < 0) - return rv; - flq->pidx_pend = next; - } else { - int i; - struct qdma_sdesc_info *sinfo = flq->sdesc_info + pidx; - - for (i = 0; i < fl_nr; i++, sinfo = sinfo->next) { - WARN_ON(sinfo->f.valid); - sinfo->f.valid = 1; - sinfo->cidx = cidx_next; - } - - flq->sdesc_info[pidx].f.sop = 1; - flq->sdesc_info[last].f.eop = 1; - - flq->pkt_dlen += len; - if (descq->conf.cmpl_udd_en) - flq->udd_cnt++; - } - cmpl->pidx = next; - - return 0; -} - -int rcv_udd_only(struct qdma_descq *descq, struct qdma_ul_cmpt_info *cmpl) -{ -#ifdef XMP_DISABLE_ST_C2H_CMPL - __be64 cmpt_entry = cmpl->entry[0]; -#endif - struct qdma_flq *flq = (struct qdma_flq *)descq->flq; - - pr_debug("%s, rcv udd.\n", descq->conf.name); -#if 0 - print_hex_dump(KERN_INFO, "cmpl entry: ", DUMP_PREFIX_OFFSET, - 16, 1, (void *)cmpl->entry, descq->cmpt_entry_len, - false); -#endif - - /* udd only: no descriptor used */ - if (descq->conf.fp_descq_c2h_packet) { - return descq->conf.fp_descq_c2h_packet(descq->q_hndl, - descq->conf.quld, 0, 0, NULL, - (unsigned char *)cmpl->entry); - } -#ifdef XMP_DISABLE_ST_C2H_CMPL - if ((cmpt_entry & (1 << 20)) > 0) { - __be16 pkt_cnt = (cmpt_entry >> 32) & 0xFFFF; - __be16 pkt_len = (cmpt_entry >> 48) & 0xFFFF; - int i; - - pr_info("pkt %u * %u.\n", pkt_len, pkt_cnt); - for (i = 0; i < pkt_cnt; i++) { - int rv = rcv_pkt(descq, cmpl, pkt_len); - - if (rv < 0) - break; - } - } -#endif - flq->udd_cnt++; - - return 0; -} - -static void descq_adjust_c2h_cntr_avgs(struct qdma_descq *descq) -{ - int i; - struct xlnx_dma_dev *xdev = descq->xdev; - struct global_csr_conf *csr_info = &xdev->csr_info; - uint8_t latecy_optimized = descq->conf.latency_optimize; - - descq->c2h_pend_pkt_moving_avg = - csr_info->c2h_cnt_th[descq->cmpt_cidx_info.counter_idx]; - - if (descq->sorted_c2h_cntr_idx == (QDMA_GLOBAL_CSR_ARRAY_SZ - 1)) - i = xdev->sorted_c2h_cntr_idx[descq->sorted_c2h_cntr_idx]; - else - i = xdev->sorted_c2h_cntr_idx[descq->sorted_c2h_cntr_idx + 1]; - - if (latecy_optimized) - descq->c2h_pend_pkt_avg_thr_hi = (csr_info->c2h_cnt_th[i] + - csr_info->c2h_cnt_th[i]); - else - descq->c2h_pend_pkt_avg_thr_hi = - (descq->c2h_pend_pkt_moving_avg + - csr_info->c2h_cnt_th[i]); - - if (descq->sorted_c2h_cntr_idx > 0) - i = xdev->sorted_c2h_cntr_idx[descq->sorted_c2h_cntr_idx - 1]; - else - i = xdev->sorted_c2h_cntr_idx[descq->sorted_c2h_cntr_idx]; - if (latecy_optimized) - descq->c2h_pend_pkt_avg_thr_lo = (csr_info->c2h_cnt_th[i] + - csr_info->c2h_cnt_th[i]); - else - descq->c2h_pend_pkt_avg_thr_lo = - (descq->c2h_pend_pkt_moving_avg + - csr_info->c2h_cnt_th[i]); - - descq->c2h_pend_pkt_avg_thr_hi >>= 1; - descq->c2h_pend_pkt_avg_thr_lo >>= 1; - pr_debug("q%u: c2h_cntr_idx = %u %u %u", descq->conf.qidx, - descq->cmpt_cidx_info.counter_idx, - descq->c2h_pend_pkt_avg_thr_lo, - descq->c2h_pend_pkt_avg_thr_hi); -} - -static void descq_incr_c2h_cntr_th(struct qdma_descq *descq) -{ - unsigned char i, c2h_cntr_idx; - unsigned char c2h_cntr_val_new; - unsigned char c2h_cntr_val_curr; - - if (descq->sorted_c2h_cntr_idx == - (QDMA_GLOBAL_CSR_ARRAY_SZ - 1)) - return; - descq->c2h_cntr_monitor_cnt = 0; - i = descq->sorted_c2h_cntr_idx; - c2h_cntr_idx = descq->xdev->sorted_c2h_cntr_idx[i]; - c2h_cntr_val_curr = descq->xdev->csr_info.c2h_cnt_th[c2h_cntr_idx]; - i++; - c2h_cntr_idx = descq->xdev->sorted_c2h_cntr_idx[i]; - c2h_cntr_val_new = descq->xdev->csr_info.c2h_cnt_th[c2h_cntr_idx]; - - if ((c2h_cntr_val_new >= descq->c2h_pend_pkt_moving_avg) && - (c2h_cntr_val_new - descq->c2h_pend_pkt_moving_avg) >= - (descq->c2h_pend_pkt_moving_avg - c2h_cntr_val_curr)) - return; /* choosing the closest */ - /* do not allow c2h c2ntr value go beyond half of cmpt rng sz*/ - if (c2h_cntr_val_new < (descq->conf.rngsz >> 1)) { - descq->cmpt_cidx_info.counter_idx = c2h_cntr_idx; - descq->sorted_c2h_cntr_idx = i; - descq_adjust_c2h_cntr_avgs(descq); - } -} - -static void descq_decr_c2h_cntr_th(struct qdma_descq *descq, - unsigned int budget) -{ - unsigned char i, c2h_cntr_idx; - unsigned char c2h_cntr_val_new; - unsigned char c2h_cntr_val_curr; - - if (!descq->sorted_c2h_cntr_idx) - return; - descq->c2h_cntr_monitor_cnt = 0; - i = descq->sorted_c2h_cntr_idx; - c2h_cntr_idx = descq->xdev->sorted_c2h_cntr_idx[i]; - c2h_cntr_val_curr = descq->xdev->csr_info.c2h_cnt_th[c2h_cntr_idx]; - i--; - c2h_cntr_idx = descq->xdev->sorted_c2h_cntr_idx[i]; - - c2h_cntr_val_new = descq->xdev->csr_info.c2h_cnt_th[c2h_cntr_idx]; - - if ((c2h_cntr_val_new <= descq->c2h_pend_pkt_moving_avg) && - (descq->c2h_pend_pkt_moving_avg - c2h_cntr_val_new) >= - (c2h_cntr_val_curr - descq->c2h_pend_pkt_moving_avg)) - return; /* choosing the closest */ - - /* for better performance we do not allow c2h_cnt - * val below budget unless latency optimized - * '-2' is SW work around for HW bug - */ - if (!descq->conf.latency_optimize && - (c2h_cntr_val_new < (budget - 2))) - return; - - descq->cmpt_cidx_info.counter_idx = c2h_cntr_idx; - - descq->sorted_c2h_cntr_idx = i; - descq_adjust_c2h_cntr_avgs(descq); -} - - -#define MAX_C2H_CNTR_STAGNANT_CNT 16 - -static void descq_adjust_c2h_cntr_th(struct qdma_descq *descq, - unsigned int pend, unsigned int budget) -{ - descq->c2h_pend_pkt_moving_avg += pend; - descq->c2h_pend_pkt_moving_avg >>= 1; /* average */ - /* if avg > hi_th, increase the counter - * if avg < lo_th, decrease the counter - */ - if (descq->c2h_pend_pkt_avg_thr_hi <= descq->c2h_pend_pkt_moving_avg) - descq_incr_c2h_cntr_th(descq); - else if (descq->c2h_pend_pkt_avg_thr_lo >= - descq->c2h_pend_pkt_moving_avg) - descq_decr_c2h_cntr_th(descq, budget); - else { - descq->c2h_cntr_monitor_cnt++; - if (descq->c2h_cntr_monitor_cnt == MAX_C2H_CNTR_STAGNANT_CNT) { - /* go down on counter value to see if we actually are - * increasing latency by setting - * higher counter threshold - */ - descq_decr_c2h_cntr_th(descq, budget); - descq->c2h_cntr_monitor_cnt = 0; - } else - return; - } -} - -static int descq_cmpl_err_check(struct qdma_descq *descq, - struct qdma_ul_cmpt_info *cmpl) -{ - /* - * format = 1 does not have length field, so the driver cannot - * figure out how many descriptor is used - */ - if (unlikely(cmpl->f.format)) { - pr_err("%s: ERR cmpl. entry %u format=1.\n", - descq->conf.name, descq->cidx_cmpt); - goto err_out; - } - - if (unlikely(!cmpl->f.desc_used && !descq->conf.cmpl_udd_en)) { - pr_warn("%s, ERR cmpl entry %u, desc_used 0, udd_en 0.\n", - descq->conf.name, descq->cidx_cmpt); - goto err_out; - } - - if (unlikely(cmpl->f.err)) { - pr_warn("%s, ERR cmpl entry %u error set\n", - descq->conf.name, descq->cidx_cmpt); - goto err_out; - } - - return 0; -err_out: - descq->err = 1; - print_hex_dump(KERN_INFO, "cmpl entry: ", DUMP_PREFIX_OFFSET, - 16, 1, (void *)cmpl, descq->cmpt_entry_len, - false); - return -EINVAL; - -} - -int descq_process_completion_st_c2h(struct qdma_descq *descq, int budget, - bool upd_cmpl) -{ - struct xlnx_dma_dev *xdev = descq->xdev; - struct qdma_c2h_cmpt_cmpl_status *cs = - (struct qdma_c2h_cmpt_cmpl_status *) - descq->desc_cmpt_cmpl_status; - struct qdma_queue_conf *qconf = &descq->conf; - unsigned int rngsz_cmpt = qconf->rngsz_cmpt; - unsigned int pidx = descq->pidx; - unsigned int cidx_cmpt = descq->cidx_cmpt; - unsigned int pidx_cmpt = cs->pidx; - struct qdma_flq *flq = (struct qdma_flq *)descq->flq; - unsigned int pidx_pend = flq->pidx_pend; - bool uld_handler = descq->conf.fp_descq_c2h_packet ? true : false; - unsigned char is_ul_ext = (qconf->desc_bypass && - qconf->fp_proc_ul_cmpt_entry) ? 1 : 0; - int pend, ret = 0; - int proc_cnt = 0; - int rv = 0; - int read_weight = budget; - - /* once an error happens, stop processing of the Q */ - if (descq->err) { - pr_err("%s: err.\n", descq->conf.name); - return -EINVAL; - } - - dma_rmb(); - pend = ring_idx_delta(pidx_cmpt, cidx_cmpt, rngsz_cmpt); - if (!pend) { - /* SW work around where next interrupt could be missed when - * there are no entries as of now - */ - if (descq->xdev->conf.qdma_drv_mode != POLL_MODE) { - rv = queue_cmpt_cidx_update(descq->xdev, - descq->conf.qidx, - &descq->cmpt_cidx_info); - if (unlikely(rv < 0)) { - pr_err("%s: Failed to update cmpt cidx\n", - descq->conf.name); - return -EINVAL; - } - } - return -ENODATA; - } - -#if 0 - print_hex_dump(KERN_INFO, "cmpl status: ", DUMP_PREFIX_OFFSET, - 16, 1, (void *)cs, sizeof(*cs), - false); - pr_info("cmpl status: pidx 0x%x, cidx %x, color %d, int_state 0x%x.\n", - cs->pidx, cs->cidx, cs->color_isr_status & 0x1, - (cs->color_isr_status >> 1) & 0x3); -#endif - - flq->pkt_cnt = pend; - - if (!budget || budget > pend) - budget = pend; - - while (likely(proc_cnt < budget)) { - struct qdma_ul_cmpt_info cmpl; - int rv; - - memset(&cmpl, 0, sizeof(struct qdma_ul_cmpt_info)); - if (is_ul_ext) - rv = qconf->fp_proc_ul_cmpt_entry(descq->desc_cmpt_cur, - &cmpl); - else - rv = parse_cmpl_entry(descq, &cmpl); - /* completion entry error, q is halted */ - if (rv < 0) - return rv; - rv = descq_cmpl_err_check(descq, &cmpl); - if (rv < 0) - return rv; - - if (!is_new_cmpl_entry(descq, &cmpl)) - break; - - cmpl.pidx = pidx; - - if (cmpl.f.desc_used) { - rv = rcv_pkt(descq, &cmpl, cmpl.len); - } else if (descq->conf.cmpl_udd_en) { - /* udd only: no descriptor used */ - rv = rcv_udd_only(descq, &cmpl); - } - - if (rv < 0) /* cannot process now, stop */ - break; - - pidx = cmpl.pidx; - - cmpt_next(descq); - proc_cnt++; - } - - flq->pkt_cnt -= proc_cnt; - - if ((xdev->conf.intr_moderation) && - (descq->cmpt_cidx_info.trig_mode == - TRIG_MODE_COMBO)) { - pend = ring_idx_delta(cs->pidx, descq->cidx_cmpt, rngsz_cmpt); - flq->pkt_cnt = pend; - - /* we dont need interrupt if packets available for next read */ - if (read_weight && (flq->pkt_cnt > read_weight)) - descq->cmpt_cidx_info.irq_en = 0; - else - descq->cmpt_cidx_info.irq_en = 1; - - /* if we use just then at right value of c2h_cntr - * the average goes down as there - * will not be many pend packet. - */ - if (descq->conf.adaptive_rx) - descq_adjust_c2h_cntr_th(descq, pend + proc_cnt, - read_weight); - } - - if (proc_cnt) { - descq->pidx_cmpt = pidx_cmpt; - descq->pidx = pidx; - descq->cmpt_cidx_info.wrb_cidx = descq->cidx_cmpt; - if (!descq->conf.fp_descq_c2h_packet) { - rv = queue_cmpt_cidx_update(descq->xdev, - descq->conf.qidx, &descq->cmpt_cidx_info); - if (unlikely(rv < 0)) { - pr_err("%s: Failed to update cmpt cidx\n", - descq->conf.name); - return -EINVAL; - } - qdma_c2h_packets_proc_dflt(descq); - } - - flq->pkt_cnt = ring_idx_delta(cs->pidx, descq->cidx_cmpt, - rngsz_cmpt); - - /* some descq entries have been consumed */ - if (flq->pidx_pend != pidx_pend) { - pend = ring_idx_delta(flq->pidx_pend, pidx_pend, - flq->size); - qdma_flq_refill(descq, pidx_pend, pend, - uld_handler ? 0 : 1, GFP_ATOMIC); - - if (upd_cmpl && !descq->q_stop_wait) { - pend = ring_idx_decr(flq->pidx_pend, 1, - flq->size); - descq->pidx_info.pidx = pend; - if (!descq->conf.fp_descq_c2h_packet) { - ret = queue_pidx_update(descq->xdev, - descq->conf.qidx, - descq->conf.q_type, - &descq->pidx_info); - if (unlikely(ret < 0)) { - pr_err("%s: Failed to update pidx\n", - descq->conf.name); - return -EINVAL; - } - } - } - } - } - - return 0; -} - -int qdma_queue_c2h_peek(unsigned long dev_hndl, unsigned long id, - unsigned int *udd_cnt, unsigned int *pkt_cnt, - unsigned int *data_len) -{ - struct xlnx_dma_dev *xdev = (struct xlnx_dma_dev *)dev_hndl; - struct qdma_descq *descq; - struct qdma_flq *flq; - - /** make sure that the dev_hndl passed is Valid */ - if (!xdev) { - pr_err("dev_hndl is NULL"); - return -EINVAL; - } - - if (xdev_check_hndl(__func__, xdev->conf.pdev, dev_hndl) < 0) { - pr_err("Invalid dev_hndl passed"); - return -EINVAL; - } - - descq = qdma_device_get_descq_by_id(xdev, id, NULL, 0, 0); - if (!descq) { - pr_err("Invalid qid(%ld)", id); - return -EINVAL; - } - - flq = (struct qdma_flq *)descq->flq; - *udd_cnt = flq->udd_cnt; - *pkt_cnt = flq->pkt_cnt; - *data_len = flq->pkt_dlen; - - return 0; -} - -int qdma_queue_packet_read(unsigned long dev_hndl, unsigned long id, - struct qdma_request *req, struct qdma_cmpl_ctrl *cctrl) -{ - struct xlnx_dma_dev *xdev = (struct xlnx_dma_dev *)dev_hndl; - struct qdma_descq *descq; - struct qdma_sgt_req_cb *cb = NULL; - int rv = 0; - - /** make sure that the dev_hndl passed is Valid */ - if (!xdev) { - pr_err("dev_hndl is NULL"); - return -EINVAL; - } - - if (xdev_check_hndl(__func__, xdev->conf.pdev, dev_hndl) < 0) { - pr_err("Invalid dev_hndl passed"); - return -EINVAL; - } - - if (!req) { - pr_err("req is NULL"); - return -EINVAL; - } - cb = qdma_req_cb_get(req); - - descq = qdma_device_get_descq_by_id(xdev, id, NULL, 0, 1); - if (!descq) { - pr_err("Invalid qid(%ld)", id); - return -EINVAL; - } - - if (!descq->conf.st || (descq->conf.q_type != Q_C2H)) { - pr_info("%s: st %d, type %d.\n", - descq->conf.name, descq->conf.st, descq->conf.q_type); - return -EINVAL; - } - - if (cctrl) { - lock_descq(descq); - - descq->cmpt_cidx_info.trig_mode = - descq->conf.cmpl_trig_mode = cctrl->trigger_mode; - descq->cmpt_cidx_info.timer_idx = - descq->conf.cmpl_timer_idx = cctrl->timer_idx; - descq->cmpt_cidx_info.counter_idx = - descq->conf.cmpl_cnt_th_idx = cctrl->cnt_th_idx; - descq->cmpt_cidx_info.irq_en = - descq->conf.cmpl_en_intr = cctrl->cmpl_en_intr; - descq->cmpt_cidx_info.wrb_en = - descq->conf.cmpl_stat_en = cctrl->en_stat_desc; - - descq->cmpt_cidx_info.wrb_cidx = descq->cidx_cmpt; - - rv = queue_cmpt_cidx_update(descq->xdev, - descq->conf.qidx, &descq->cmpt_cidx_info); - if (unlikely(rv < 0)) { - pr_err("%s: Failed to update cmpt cidx\n", - descq->conf.name); - unlock_descq(descq); - return -EINVAL; - } - - unlock_descq(descq); - } - - memset(cb, 0, QDMA_REQ_OPAQUE_SIZE); - - qdma_waitq_init(&cb->wq); - - lock_descq(descq); - descq_st_c2h_read(descq, req, 1, 1); - unlock_descq(descq); - - return req->count - cb->left; -} diff --git a/QDMA/linux-kernel/driver/libqdma/qdma_st_c2h.h b/QDMA/linux-kernel/driver/libqdma/qdma_st_c2h.h deleted file mode 100755 index 1d6971f02..000000000 --- a/QDMA/linux-kernel/driver/libqdma/qdma_st_c2h.h +++ /dev/null @@ -1,227 +0,0 @@ -/* - * This file is part of the Xilinx DMA IP Core driver for Linux - * - * Copyright (c) 2017-2022, Xilinx, Inc. All rights reserved. - * Copyright (c) 2022, Advanced Micro Devices, Inc. All rights reserved. - * - * This source code is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * The full GNU General Public License is included in this distribution in - * the file called "COPYING". - */ - -#ifndef __QDMA_ST_C2H_H__ -#define __QDMA_ST_C2H_H__ -/** - * @file - * @brief This file contains the declarations for qdma st c2h processing - * - */ -#include -#include -#include "qdma_descq.h" -#ifdef ERR_DEBUG -#include "qdma_nl.h" -#endif - -/** - * @struct - qdma_sdesc_info - * @brief qdma descriptor information - */ -struct qdma_sdesc_info { - /** pointer to next descriptor */ - struct qdma_sdesc_info *next; - /** - * @union - desciptor flags - */ - union { - /** 8 flag bits */ - u8 fbits; - /** - * @struct - flags - * @brief desciptor flags - */ - struct flags { - /** is descriptor valid */ - u8 valid:1; - /** start of the packet */ - u8 sop:1; - /** end of the packet */ - u8 eop:1; - /** filler for 5 bits */ - u8 filler:5; - } f; - }; - /** reserved 3 bits */ - u8 rsvd[3]; - /** consumer index */ - unsigned int cidx; -}; - -/** - * struct qdma_sw_pg_sg - qdma page scatter gather request - * - */ -struct qdma_sw_pg_sg { - /** @pg_base: pointer to current page */ - struct page *pg_base; - /** @pg_dma_base_addr: dma address of the allocated page */ - dma_addr_t pg_dma_base_addr; - /** @pg_offset: page offset for all pages */ - unsigned int pg_offset; -}; - -/** - * @struct - qdma_flq - * @brief qdma free list q page allocation book keeping - */ -struct qdma_flq { - /** RO: size of the decriptor */ - unsigned int size; - /** RO: c2h buffer size */ - unsigned int desc_buf_size; - /** RO: number of pages */ - unsigned int num_pages; - /** RO: Mask for number of pages */ - unsigned int num_pgs_mask; - /** RO: number of buffers per page */ - unsigned int num_bufs_per_pg; - /** RO: number of currently allocated page index */ - unsigned int alloc_idx; - /** RO: number of currently recycled page index */ - unsigned int recycle_idx; - /** RO: max page offset */ - unsigned int max_pg_offset; - /** RO: page order */ - unsigned int buf_pg_mask; - /** RO: desc page order */ - unsigned char desc_pg_order; - /** RO: desc page shift */ - unsigned char desc_pg_shift; - /** RO: page shift */ - unsigned char buf_pg_shift; - /** RO: pointer to qdma c2h decriptor */ - struct qdma_c2h_desc *desc; - - /** RW: total # of udd outstanding */ - unsigned int udd_cnt; - /** RW: total # of packet outstanding */ - unsigned int pkt_cnt; - /** RW: total # of pkt payload length outstanding */ - unsigned int pkt_dlen; - /** RW: # of available Rx buffers */ - unsigned int avail; - /** RW: # of times buffer allocation failed */ - unsigned long alloc_fail; - /** RW: # of RX Buffer DMA Mapping failures */ - unsigned long mapping_err; - /** RW: consumer index */ - unsigned int cidx; - /** RW: producer index */ - unsigned int pidx; - /** RW: pending pidxes */ - unsigned int pidx_pend; - /** RW: Page list */ - struct qdma_sw_pg_sg *pg_sdesc; - /** RW: sw scatter gather list */ - struct qdma_sw_sg *sdesc; - /** RW: sw descriptor info */ - struct qdma_sdesc_info *sdesc_info; -}; - -/*****************************************************************************/ -/** - * qdma_descq_rxq_read() - read from the rx queue - * - * @param[in] descq: pointer to qdma_descq - * @param[in] req: queue request - * - * @return 0: success - * @return <0: failure - *****************************************************************************/ -int qdma_descq_rxq_read(struct qdma_descq *descq, struct qdma_request *req); - -/** - * qdma_descq_dump_cmpt() - dump the completion queue descriptors - * - * @param[in] descq: pointer to qdma_descq - * @param[in] start: start completion descriptor index - * @param[in] end: end completion descriptor index - * @param[in] buflen: length of the input buffer - * @param[out] buf: message buffer - * - * @return 0: success - * @return <0: failure - *****************************************************************************/ -int qdma_descq_dump_cmpt(struct qdma_descq *descq, int start, int end, - char *buf, int buflen); - -/*****************************************************************************/ -/** - * incr_cmpl_desc_cnt() - update the interrupt cidx - * - * @param[in] descq: pointer to qdma_descq - * @param[in] cnt: increment value - * - *****************************************************************************/ -void incr_cmpl_desc_cnt(struct qdma_descq *descq, unsigned int cnt); - -/*****************************************************************************/ -/** - * descq_flq_free_resource() - handler to free the pages for the request - * - * @param[in] descq: pointer to qdma_descq - * - * @return none - *****************************************************************************/ -void descq_flq_free_resource(struct qdma_descq *descq); - -/*****************************************************************************/ -/** - * descq_flq_alloc_resource() - handler to allocate the pages for the request - * - * @param[in] descq: pointer to qdma_descq - * - * @return 0: success - * @return <0: failure - *****************************************************************************/ -int descq_flq_alloc_resource(struct qdma_descq *descq); - -/*****************************************************************************/ -/** - * descq_process_completion_st_c2h() - handler to process the st c2h - * completion request - * - * @param[in] descq: pointer to qdma_descq - * @param[in] budget: number of descriptors to process - * @param[in] upd_cmpl: if update completion required - * - * @return 0: success - * @return <0: failure - *****************************************************************************/ -int descq_process_completion_st_c2h(struct qdma_descq *descq, int budget, - bool upd_cmpl); - -/*****************************************************************************/ -/** - * descq_st_c2h_read() - handler to process the st c2h read request - * - * @param[in] descq: pointer to qdma_descq - * @param[in] req: pointer to read request - * @param[in] update_pidx: flag to update the request - * @param[in] refill: flag to indicate whether to refill the flq - * - * @return 0: success - * @return <0: failure - *****************************************************************************/ -int descq_st_c2h_read(struct qdma_descq *descq, struct qdma_request *req, - bool update_pidx, bool refill); - -#endif /* ifndef __QDMA_ST_C2H_H__ */ diff --git a/QDMA/linux-kernel/driver/libqdma/qdma_thread.c b/QDMA/linux-kernel/driver/libqdma/qdma_thread.c deleted file mode 100755 index cf96fd208..000000000 --- a/QDMA/linux-kernel/driver/libqdma/qdma_thread.c +++ /dev/null @@ -1,236 +0,0 @@ -/* - * This file is part of the Xilinx DMA IP Core driver for Linux - * - * Copyright (c) 2017-2022, Xilinx, Inc. All rights reserved. - * Copyright (c) 2022, Advanced Micro Devices, Inc. All rights reserved. - * - * This source code is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * The full GNU General Public License is included in this distribution in - * the file called "COPYING". - */ - -#define pr_fmt(fmt) KBUILD_MODNAME ":%s: " fmt, __func__ - -#include "qdma_thread.h" - -#include - -#include "qdma_descq.h" -#include "thread.h" -#include "xdev.h" - -/* ********************* global variables *********************************** */ - -static unsigned int thread_cnt; -/** completion status threads */ -static struct qdma_kthread *cs_threads; - -static spinlock_t qcnt_lock; -static unsigned int cpu_count; -static unsigned int *per_cpu_qcnt; - -/* ********************* static function declarations *********************** */ - -static int qdma_thread_cmpl_status_pend(struct list_head *work_item); -static int qdma_thread_cmpl_status_proc(struct list_head *work_item); - -/* ********************* static function definitions ************************ */ -static int qdma_thread_cmpl_status_pend(struct list_head *work_item) -{ - struct qdma_descq *descq = list_entry(work_item, struct qdma_descq, - cmplthp_list); - int pend = 0; - - lock_descq(descq); - pend = !list_empty(&descq->pend_list) || !list_empty(&descq->work_list); - unlock_descq(descq); - - return pend; -} - -static int qdma_thread_cmpl_status_proc(struct list_head *work_item) -{ - struct qdma_descq *descq; - - descq = list_entry(work_item, struct qdma_descq, cmplthp_list); - qdma_descq_service_cmpl_update(descq, 0, 1); - return 0; -} - -/* ********************* public function definitions ************************ */ - -void qdma_thread_remove_work(struct qdma_descq *descq) -{ - struct qdma_kthread *cmpl_thread; - int cpu_idx = cpu_count; - - - lock_descq(descq); - cmpl_thread = descq->cmplthp; - descq->cmplthp = NULL; - - if (descq->cpu_assigned) { - descq->cpu_assigned = 0; - cpu_idx = descq->intr_work_cpu; - } - - pr_debug("%s removing from thread %s, %u.\n", - descq->conf.name, cmpl_thread ? cmpl_thread->name : "?", - cpu_idx); - - unlock_descq(descq); - - if (cpu_idx < cpu_count) { - spin_lock(&qcnt_lock); - per_cpu_qcnt[cpu_idx]--; - spin_unlock(&qcnt_lock); - } - - if (cmpl_thread) { - lock_thread(cmpl_thread); - list_del(&descq->cmplthp_list); - cmpl_thread->work_cnt--; - unlock_thread(cmpl_thread); - } -} - -void qdma_thread_add_work(struct qdma_descq *descq) -{ - struct qdma_kthread *thp = cs_threads; - unsigned int v = 0; - int i, idx = thread_cnt; - - if (descq->xdev->conf.qdma_drv_mode != POLL_MODE) { - spin_lock(&qcnt_lock); - idx = cpu_count - 1; - v = per_cpu_qcnt[idx]; - for (i = idx - 1; i >= 0 && v; i--) { - if (per_cpu_qcnt[i] < v) { - idx = i; - v = per_cpu_qcnt[i]; - } - } - - per_cpu_qcnt[idx]++; - spin_unlock(&qcnt_lock); - - lock_descq(descq); - descq->cpu_assigned = 1; - descq->intr_work_cpu = idx; - unlock_descq(descq); - - pr_debug("%s 0x%p assigned to cpu %u.\n", - descq->conf.name, descq, idx); - - return; - } - - /* Polled mode only */ - for (i = 0; i < thread_cnt; i++, thp++) { - lock_thread(thp); - if (idx == thread_cnt) { - v = thp->work_cnt; - idx = i; - } else if (!thp->work_cnt) { - idx = i; - unlock_thread(thp); - break; - } else if (thp->work_cnt < v) - idx = i; - unlock_thread(thp); - } - - thp = cs_threads + idx; - lock_thread(thp); - list_add_tail(&descq->cmplthp_list, &thp->work_list); - descq->intr_work_cpu = idx; - thp->work_cnt++; - unlock_thread(thp); - - pr_debug("%s 0x%p assigned to cmpl status thread %s,%u.\n", - descq->conf.name, descq, thp->name, thp->work_cnt); - - lock_descq(descq); - descq->cmplthp = thp; - unlock_descq(descq); -} - -int qdma_threads_create(unsigned int num_threads) -{ - struct qdma_kthread *thp; - int i; - int rv; - - if (thread_cnt) { - pr_warn("threads already created!"); - return 0; - } - spin_lock_init(&qcnt_lock); - - cpu_count = num_online_cpus(); - per_cpu_qcnt = kzalloc(cpu_count * sizeof(unsigned int), GFP_KERNEL); - if (!per_cpu_qcnt) - return -ENOMEM; - - thread_cnt = (num_threads == 0) ? cpu_count : num_threads; - - cs_threads = kzalloc(thread_cnt * sizeof(struct qdma_kthread), - GFP_KERNEL); - if (!cs_threads) - return -ENOMEM; - - /* N dma writeback monitoring threads */ - thp = cs_threads; - for (i = 0; i < thread_cnt; i++, thp++) { - thp->cpu = i; - thp->kth_timeout = 0; - rv = qdma_kthread_start(thp, "qdma_cmpl_status_th", i); - if (rv < 0) - goto cleanup_threads; - thp->fproc = qdma_thread_cmpl_status_proc; - thp->fpending = qdma_thread_cmpl_status_pend; - } - - return 0; - -cleanup_threads: - kfree(cs_threads); - cs_threads = NULL; - thread_cnt = 0; - - return rv; -} - -void qdma_threads_destroy(void) -{ - int i; - struct qdma_kthread *thp; - - if (per_cpu_qcnt) { - spin_lock(&qcnt_lock); - kfree(per_cpu_qcnt); - per_cpu_qcnt = NULL; - spin_unlock(&qcnt_lock); - } - - if (!thread_cnt) - return; - - /* N dma writeback monitoring threads */ - thp = cs_threads; - for (i = 0; i < thread_cnt; i++, thp++) - if (thp->fproc) - qdma_kthread_stop(thp); - - kfree(cs_threads); - cs_threads = NULL; - thread_cnt = 0; -} diff --git a/QDMA/linux-kernel/driver/libqdma/qdma_thread.h b/QDMA/linux-kernel/driver/libqdma/qdma_thread.h deleted file mode 100755 index 48b268041..000000000 --- a/QDMA/linux-kernel/driver/libqdma/qdma_thread.h +++ /dev/null @@ -1,76 +0,0 @@ -/* - * This file is part of the Xilinx DMA IP Core driver for Linux - * - * Copyright (c) 2017-2022, Xilinx, Inc. All rights reserved. - * Copyright (c) 2022, Advanced Micro Devices, Inc. All rights reserved. - * - * This source code is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * The full GNU General Public License is included in this distribution in - * the file called "COPYING". - */ - -#ifndef LIBQDMA_QDMA_THREAD_H_ -#define LIBQDMA_QDMA_THREAD_H_ -/** - * @file - * @brief This file contains the declarations for qdma thread handlers - * - */ - -/** qdma_descq forward declaration */ -struct qdma_descq; - -/*****************************************************************************/ -/** - * qdma_threads_create() - create qdma threads - * This functions creates two threads for each cpu in the system or number of - * number of thread requested by param num_threads and assigns the - * thread handlers - * 1: queue processing thread - * 2: queue completion handler thread - * - * @param[in] num_threads - number of threads to be created - * - * @return 0: success - * @return <0: failure - *****************************************************************************/ -int qdma_threads_create(unsigned int num_threads); - -/*****************************************************************************/ -/** - * qdma_threads_destroy() - destroy all the qdma threads created - * during system initialization - * - * @return none - *****************************************************************************/ -void qdma_threads_destroy(void); - -/*****************************************************************************/ -/** - * qdma_thread_remove_work() - handler to remove the attached work thread - * - * @param[in] descq: pointer to qdma_descq - * - * @return none - *****************************************************************************/ -void qdma_thread_remove_work(struct qdma_descq *descq); - -/*****************************************************************************/ -/** - * qdma_thread_add_work() - handler to add a work thread - * - * @param[in] descq: pointer to qdma_descq - * - * @return none - *****************************************************************************/ -void qdma_thread_add_work(struct qdma_descq *descq); - -#endif /* LIBQDMA_QDMA_THREAD_H_ */ diff --git a/QDMA/linux-kernel/driver/libqdma/qdma_ul_ext.h b/QDMA/linux-kernel/driver/libqdma/qdma_ul_ext.h deleted file mode 100755 index ae6993861..000000000 --- a/QDMA/linux-kernel/driver/libqdma/qdma_ul_ext.h +++ /dev/null @@ -1,99 +0,0 @@ -#ifndef QDMA_UL_EXT_H__ -#define QDMA_UL_EXT_H__ -/* - * This file is part of the Xilinx DMA IP Core driver for Linux - * - * Copyright (c) 2017-2022, Xilinx, Inc. All rights reserved. - * Copyright (c) 2022, Advanced Micro Devices, Inc. All rights reserved. - * - * This source code is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * The full GNU General Public License is included in this distribution in - * the file called "COPYING". - */ - -/** - * @file - * @brief This file provides the interface definitions for bypass extension - * modules to be plugged in - */ - -#include "libqdma_export.h" - -/** - * struct qdma_q_desc_list - descriptor list - */ -struct qdma_q_desc_list { - /** @desc: pointer to the descriptor */ - void *desc; - /** @next: pointer to the next list element */ - struct qdma_q_desc_list *next; -}; - -/*****************************************************************************/ -/** - * qdma_sgl_find_offset() - find the sgl offset for the request under process - * - * @req: request under process - * @sg_p: pointer to the entry in the sgl list - * @sg_offset: offset in the entry of sgl list - * - * Return: 0: success; <0: on any error - * - *****************************************************************************/ -int qdma_sgl_find_offset(struct qdma_request *req, struct qdma_sw_sg **sg_p, - unsigned int *sg_offset); - -/*****************************************************************************/ -/** - * qdma_update_request() - update the request current processed info - * - * @q_hndl: handle to the q with which bypass module can request descriptors - * @req: request under process - * @num_desc: number of descriptors consumed consumed in the process - * @data_cnt: amount of data processed in the request - * @sg_offset: offset in the @sg - * @sg: next sg to be serviced - * - *****************************************************************************/ -void qdma_update_request(void *q_hndl, struct qdma_request *req, - unsigned int num_desc, - unsigned int data_cnt, - unsigned int sg_offset, - void *sg); - -/*****************************************************************************/ -/** - * qdma_q_desc_get() - request @desc_cnt number of descriptors for the q - * specified by @q_hndl - * - * @q_hndl: handle to the q with which bypass module can request descriptors - * @desc_cnt: number of descriptors required - * @desc_list: list of descriptors to be provided for this request - * - * Return: 0: success; <0: if number of requested descriptors not available - * - *****************************************************************************/ -int qdma_q_desc_get(void *q_hndl, const unsigned int desc_cnt, - struct qdma_q_desc_list **desc_list); - -/*****************************************************************************/ -/** - * qdma_q_init_pointers() - update the pidx/cidx pointers of the q specified - * by @q_hndl - * - * @q_hndl: handle to the q with which bypass module can request descriptors - * - * Return: 0: success; <0: on failure - * - *****************************************************************************/ -int qdma_q_init_pointers(void *q_hndl); - -#endif /* QDMA_UL_EXT_H__ */ diff --git a/QDMA/linux-kernel/driver/libqdma/thread.c b/QDMA/linux-kernel/driver/libqdma/thread.c deleted file mode 100755 index d0c09091c..000000000 --- a/QDMA/linux-kernel/driver/libqdma/thread.c +++ /dev/null @@ -1,194 +0,0 @@ -/* - * This file is part of the Xilinx DMA IP Core driver for Linux - * - * Copyright (c) 2017-2022, Xilinx, Inc. All rights reserved. - * Copyright (c) 2022, Advanced Micro Devices, Inc. All rights reserved. - * - * This source code is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * The full GNU General Public License is included in this distribution in - * the file called "COPYING". - */ - -#define pr_fmt(fmt) KBUILD_MODNAME ":%s: " fmt, __func__ - -#include "thread.h" - -#include - -/* - * kernel thread function wrappers - */ -int qdma_kthread_dump(struct qdma_kthread *thp, char *buf, int buflen, - int detail) -{ - int len = 0; - - if (!buf || !buflen) - return 0; - - lock_thread(thp); - len += snprintf(buf, buflen, "%s, cpu %u, work %u.\n", - thp->name, thp->cpu, thp->work_cnt); - - if (detail) - ; - - unlock_thread(thp); - - buf[len] = '\0'; - return len; -} - -static inline int xthread_work_pending(struct qdma_kthread *thp) -{ - struct list_head *work_item, *next; - - /* any work items assigned to this thread? */ - if (list_empty(&thp->work_list)) - return 0; - - - /* any work item has pending work to do? */ - list_for_each_safe(work_item, next, &thp->work_list) { - if (thp->fpending && thp->fpending(work_item)) - return 1; - - } - return 0; -} - -static inline void xthread_reschedule(struct qdma_kthread *thp) -{ - if (thp->kth_timeout) { - pr_debug_thread("%s rescheduling for %u seconds", - thp->name, thp->kth_timeout); - qdma_waitq_wait_event_timeout( - thp->waitq, thp->schedule, - msecs_to_jiffies(thp->kth_timeout)); - } else { - pr_debug_thread("%s rescheduling", thp->name); - qdma_waitq_wait_event(thp->waitq, thp->schedule); - } -} - -static int xthread_main(void *data) -{ - struct qdma_kthread *thp = (struct qdma_kthread *)data; - - pr_debug_thread("%s UP.\n", thp->name); - - disallow_signal(SIGPIPE); - - if (thp->finit) - thp->finit(thp); - - - while (!kthread_should_stop()) { - - struct list_head *work_item, *next; - - pr_debug_thread("%s interruptible\n", thp->name); - - /* any work to do? */ - lock_thread(thp); - if (!xthread_work_pending(thp)) { - unlock_thread(thp); - xthread_reschedule(thp); - lock_thread(thp); - } - thp->schedule = 0; - - if (thp->work_cnt) { - pr_debug_thread("%s processing %u work items\n", - thp->name, thp->work_cnt); - /* do work */ - list_for_each_safe(work_item, next, &thp->work_list) { - thp->fproc(work_item); - } - } - unlock_thread(thp); - schedule(); - } - - pr_debug_thread("%s, work done.\n", thp->name); - - - if (thp->fdone) - thp->fdone(thp); - - pr_debug_thread("%s, exit.\n", thp->name); - return 0; -} - -int qdma_kthread_start(struct qdma_kthread *thp, char *name, int id) -{ - int len; - - if (thp->task) { - pr_warn("kthread %s task already running?\n", thp->name); - return -EINVAL; - } - -#ifdef __QDMA_VF__ - len = snprintf(thp->name, sizeof(thp->name), "%s_vf_%d", name, id); - if (len < 0) - return -EINVAL; -#else - len = snprintf(thp->name, sizeof(thp->name), "%s%d", name, id); - if (len < 0) - return -EINVAL; -#endif - thp->id = id; - - spin_lock_init(&thp->lock); - INIT_LIST_HEAD(&thp->work_list); - qdma_waitq_init(&thp->waitq); - - thp->task = kthread_create_on_node(xthread_main, (void *)thp, - cpu_to_node(thp->cpu), "%s", thp->name); - if (IS_ERR(thp->task)) { - pr_err("kthread %s, create task failed: 0x%lx\n", - thp->name, (unsigned long)IS_ERR(thp->task)); - thp->task = NULL; - return -EFAULT; - } - - kthread_bind(thp->task, thp->cpu); - - pr_debug_thread("kthread 0x%p, %s, cpu %u, task 0x%p.\n", - thp, thp->name, thp->cpu, thp->task); - - wake_up_process(thp->task); - return 0; -} - -int qdma_kthread_stop(struct qdma_kthread *thp) -{ - int rv; - - if (!thp->task) { - pr_debug_thread("kthread %s, already stopped.\n", thp->name); - return 0; - } - - thp->schedule = 1; - rv = kthread_stop(thp->task); - if (rv < 0) { - pr_warn("kthread %s, stop err %d.\n", thp->name, rv); - return rv; - } - - pr_debug_thread("kthread %s, 0x%p, stopped.\n", thp->name, thp->task); - thp->task = NULL; - - return 0; -} - diff --git a/QDMA/linux-kernel/driver/libqdma/thread.h b/QDMA/linux-kernel/driver/libqdma/thread.h deleted file mode 100755 index 56346ce60..000000000 --- a/QDMA/linux-kernel/driver/libqdma/thread.h +++ /dev/null @@ -1,146 +0,0 @@ -/* - * This file is part of the Xilinx DMA IP Core driver for Linux - * - * Copyright (c) 2017-2022, Xilinx, Inc. All rights reserved. - * Copyright (c) 2022, Advanced Micro Devices, Inc. All rights reserved. - * - * This source code is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * The full GNU General Public License is included in this distribution in - * the file called "COPYING". - */ - -#ifndef __XDMA_KTHREAD_H__ -#define __XDMA_KTHREAD_H__ -/** - * @file - * @brief This file contains the declarations for qdma kernel threads - * - */ -#include -#include -#include -#include -#include -#include "qdma_compat.h" - -/** - * @struct - qdma_kthread - * @brief qdma thread book keeping parameters - */ -struct qdma_kthread { - /** thread lock*/ - spinlock_t lock; - /** name of the thread */ - char name[26]; - /** cpu number for which the thread associated with */ - unsigned short cpu; - /** thread id */ - unsigned short id; - /** thread sleep timeout value */ - unsigned int kth_timeout; - /** flags for thread */ - unsigned long flag; - /** thread wait queue */ - qdma_wait_queue waitq; - /* flag to indicate scheduling of thread */ - unsigned int schedule; - /** kernel task structure associated with thread*/ - struct task_struct *task; - /** thread work list count */ - unsigned int work_cnt; - /** thread work list count */ - struct list_head work_list; - /** thread initialization handler */ - int (*finit)(struct qdma_kthread *thp); - /** thread pending handler */ - int (*fpending)(struct list_head *work_item); - /** thread peocessing handler */ - int (*fproc)(struct list_head *work_item); - /** thread done handler */ - int (*fdone)(struct qdma_kthread *thp); -}; - -/*****************************************************************************/ -/** - * qdma_kthread_dump() - handler to dump the thread information - * - * @param[in] thp: pointer to qdma_kthread - * @param[in] detail: flag to indicate whether details required or not - * @param[in] buflen: length of the input buffer - * @param[out] buf: message buffer - * - * @return length of the buffer - *****************************************************************************/ -int qdma_kthread_dump(struct qdma_kthread *thp, char *buf, int buflen, - int detail); - -#ifdef DEBUG_THREADS -#define lock_thread(thp) \ - do { \ - pr_debug("locking thp %s ...\n", (thp)->name); \ - spin_lock(&(thp)->lock); \ - } while (0) - -#define unlock_thread(thp) \ - do { \ - pr_debug("unlock thp %s ...\n", (thp)->name); \ - spin_unlock(&(thp)->lock); \ - } while (0) - -#define qdma_kthread_wakeup(thp) \ - do { \ - pr_debug("signaling thp %s ...\n", (thp)->name); \ - thp->schedule = 1; \ - qdma_waitq_wakeup(&thp->waitq); \ - } while (0) - -#define pr_debug_thread(fmt, ...) pr_debug(fmt, __VA_ARGS__) - -#else -/** lock thread macro */ -#define lock_thread(thp) spin_lock(&(thp)->lock) -/** un lock thread macro */ -#define unlock_thread(thp) spin_unlock(&(thp)->lock) -/** macro to wake up the qdma k thread */ -#define qdma_kthread_wakeup(thp) \ - do { \ - thp->schedule = 1; \ - qdma_waitq_wakeup(&thp->waitq); \ - } while (0) -/** pr_debug_thread */ -#define pr_debug_thread(fmt, ...) -#endif - -/*****************************************************************************/ -/** - * qdma_kthread_start() - handler to start the kernel thread - * - * @param[in] thp: pointer to qdma_kthread - * @param[in] name: name for the thread - * @param[in] id: thread id - * - * @return 0: success - * @return <0: failure - *****************************************************************************/ -int qdma_kthread_start(struct qdma_kthread *thp, char *name, int id); - -/*****************************************************************************/ -/** - * qdma_kthread_stop() - handler to stop the kernel thread - * - * @param[in] thp: pointer to qdma_kthread - * - * @return 0: success - * @return <0: failure - *****************************************************************************/ -int qdma_kthread_stop(struct qdma_kthread *thp); - -#endif /* #ifndef __XDMA_KTHREAD_H__ */ diff --git a/QDMA/linux-kernel/driver/libqdma/version.h b/QDMA/linux-kernel/driver/libqdma/version.h deleted file mode 100755 index 5b6e3324a..000000000 --- a/QDMA/linux-kernel/driver/libqdma/version.h +++ /dev/null @@ -1,40 +0,0 @@ -/* - * This file is part of the Xilinx DMA IP Core driver for Linux - * - * Copyright (c) 2017-2022, Xilinx, Inc. All rights reserved. - * Copyright (c) 2022, Advanced Micro Devices, Inc. All rights reserved. - * - * This source code is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * The full GNU General Public License is included in this distribution in - * the file called "COPYING". - */ - -#ifndef __LIBQDMA_VERSION_H__ -#define __LIBQDMA_VERSION_H__ - -#define LIBQDMA_MODULE_NAME "libqdma" -#define LIBQDMA_MODULE_DESC "Xilinx QDMA Library" - -#define LIBQDMA_VERSION_MAJOR 2023 -#define LIBQDMA_VERSION_MINOR 2 -#define LIBQDMA_VERSION_PATCH 0 - -#define LIBQDMA_VERSION_STR \ - __stringify(LIBQDMA_VERSION_MAJOR) "." \ - __stringify(LIBQDMA_VERSION_MINOR) "." \ - __stringify(LIBQDMA_VERSION_PATCH) - -#define LIBQDMA_VERSION \ - ((LIBQDMA_VERSION_MAJOR)*10000 + \ - (LIBQDMA_VERSION_MINOR)*1000 + \ - LIBQDMA_VERSION_PATCH) - -#endif /* ifndef __LIBQDMA_VERSION_H__ */ diff --git a/QDMA/linux-kernel/driver/libqdma/xdev.c b/QDMA/linux-kernel/driver/libqdma/xdev.c deleted file mode 100755 index 19880a515..000000000 --- a/QDMA/linux-kernel/driver/libqdma/xdev.c +++ /dev/null @@ -1,1535 +0,0 @@ -/* - * This file is part of the Xilinx DMA IP Core driver for Linux - * - * Copyright (c) 2017-2022, Xilinx, Inc. All rights reserved. - * Copyright (c) 2022, Advanced Micro Devices, Inc. All rights reserved. - * - * This source code is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * The full GNU General Public License is included in this distribution in - * the file called "COPYING". - */ - -/** - * @file - * @brief This file contains the declarations for QDMA PCIe device - * - */ -#define pr_fmt(fmt) KBUILD_MODNAME ":%s: " fmt, __func__ - -#include -#include -#include -#include -#include -#include -#include -#include - -#include "qdma_regs.h" -#include "xdev.h" -#include "qdma_mbox.h" -#include "qdma_intr.h" -#include "qdma_resource_mgmt.h" -#include "qdma_access_common.h" -#ifdef DEBUGFS -#include "qdma_debugfs_dev.h" -#endif -#ifdef __XRT__ -#include "qdma_access_errors.h" -#endif - -#ifdef __LIST_NEXT_ENTRY__ -#define list_next_entry(pos, member) \ - list_entry((pos)->member.next, typeof(*(pos)), member) -#endif - -#ifndef __QDMA_VF__ -#ifndef QDMA_QBASE -#define QDMA_QBASE 0 -#endif -#ifndef QDMA_TOTAL_Q -/** - * CPM5 supports 4095 Qs & all other designs supports 2048 Qs. - * Though the number here is given as 2K Qs, - * actual qmax is extracted from dev cap. - */ -#define QDMA_TOTAL_Q 2048 -#endif -#endif - -/** - * qdma device management - * maintains a list of the qdma devices - */ -static LIST_HEAD(xdev_list); - -/** - * mutex defined for qdma device management - */ -static DEFINE_MUTEX(xdev_mutex); - -#ifndef list_last_entry -#define list_last_entry(ptr, type, member) \ - list_entry((ptr)->prev, type, member) -#endif - -struct qdma_resource_lock { - struct list_head node; - struct mutex lock; -}; - -/*****************************************************************************/ -/** - * pci_dma_mask_set() - check the pci capability of the dma device - * - * @param[in] pdev: pointer to struct pci_dev - * - * - * @return 0: on success - * @return <0: on failure - *****************************************************************************/ -static int pci_dma_mask_set(struct pci_dev *pdev) -{ - /** 64-bit addressing capability for XDMA? */ - - if (!dma_set_mask(&pdev->dev, DMA_BIT_MASK(64))) { - /** use 64-bit DMA for descriptors */ - dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)); - /** use 64-bit DMA, 32-bit for consistent */ - } else if (!dma_set_mask(&pdev->dev, DMA_BIT_MASK(32))) { - dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)); - /** use 32-bit DMA */ - dev_info(&pdev->dev, "Using a 32-bit DMA mask.\n"); - } else { - /** use 32-bit DMA */ - dev_info(&pdev->dev, "No suitable DMA possible.\n"); - return -EINVAL; - } - - return 0; -} - -#if KERNEL_VERSION(3, 5, 0) <= LINUX_VERSION_CODE -static void pci_enable_relaxed_ordering(struct pci_dev *pdev) -{ - pcie_capability_set_word(pdev, PCI_EXP_DEVCTL, PCI_EXP_DEVCTL_RELAX_EN); -} - -static void pci_disable_relaxed_ordering(struct pci_dev *pdev) -{ - pcie_capability_clear_word(pdev, PCI_EXP_DEVCTL, - PCI_EXP_DEVCTL_RELAX_EN); -} - -static void pci_enable_extended_tag(struct pci_dev *pdev) -{ - pcie_capability_set_word(pdev, PCI_EXP_DEVCTL, PCI_EXP_DEVCTL_EXT_TAG); -} - -static void pci_disable_extended_tag(struct pci_dev *pdev) -{ - pcie_capability_clear_word(pdev, PCI_EXP_DEVCTL, - PCI_EXP_DEVCTL_EXT_TAG); -} - -#else -static void pci_enable_relaxed_ordering(struct pci_dev *pdev) -{ - u16 v; - int pos; - - pos = pci_pcie_cap(pdev); - if (pos > 0) { - pci_read_config_word(pdev, pos + PCI_EXP_DEVCTL, &v); - v |= PCI_EXP_DEVCTL_RELAX_EN; - pci_write_config_word(pdev, pos + PCI_EXP_DEVCTL, v); - } -} - -static void pci_disable_relaxed_ordering(struct pci_dev *pdev) -{ - u16 v; - int pos; - - pos = pci_pcie_cap(pdev); - if (pos > 0) { - pci_read_config_word(pdev, pos + PCI_EXP_DEVCTL, &v); - v &= ~(PCI_EXP_DEVCTL_RELAX_EN); - pci_write_config_word(pdev, pos + PCI_EXP_DEVCTL, v); - } -} - -static void pci_enable_extended_tag(struct pci_dev *pdev) -{ - u16 v; - int pos; - - pos = pci_pcie_cap(pdev); - if (pos > 0) { - pci_read_config_word(pdev, pos + PCI_EXP_DEVCTL, &v); - v |= PCI_EXP_DEVCTL_EXT_TAG; - pci_write_config_word(pdev, pos + PCI_EXP_DEVCTL, v); - } -} - -static void pci_disable_extended_tag(struct pci_dev *pdev) -{ - u16 v; - int pos; - - pos = pci_pcie_cap(pdev); - if (pos > 0) { - pci_read_config_word(pdev, pos + PCI_EXP_DEVCTL, &v); - v &= ~(PCI_EXP_DEVCTL_EXT_TAG); - pci_write_config_word(pdev, pos + PCI_EXP_DEVCTL, v); - } -} -#endif - - -#if defined(__QDMA_VF__) -static void xdev_reset_work(struct work_struct *work) -{ - struct xlnx_dma_dev *xdev = container_of(work, struct xlnx_dma_dev, - reset_work); - struct pci_dev *pdev = xdev->conf.pdev; - int rv = 0; - - if (xdev->reset_state == RESET_STATE_RECV_PF_RESET_REQ) { - - qdma_device_offline(pdev, (unsigned long)xdev, XDEV_FLR_ACTIVE); - pci_disable_extended_tag(pdev); - pci_disable_relaxed_ordering(pdev); - pci_release_regions(pdev); - pci_disable_device(pdev); - -#ifndef __XRT__ - rv = pci_request_regions(pdev, "qdma-vf"); - if (rv) { - pr_err("cannot obtain PCI resources\n"); - return; - } -#endif - - rv = pci_enable_device(pdev); - if (rv) { - pr_err("cannot enable PCI device\n"); -#ifndef __XRT__ - pci_release_regions(pdev); -#endif - return; - } - - /* enable relaxed ordering */ - pci_enable_relaxed_ordering(pdev); - - /* enable extended tag */ - pci_enable_extended_tag(pdev); - - /* enable bus master capability */ - pci_set_master(pdev); - - pci_dma_mask_set(pdev); - - pcie_set_readrq(pdev, 512); - - qdma_device_online(pdev, (unsigned long)xdev, XDEV_FLR_ACTIVE); - - if (xdev->reset_state == RESET_STATE_RECV_PF_RESET_DONE) - xdev->reset_state = RESET_STATE_IDLE; - } else if (xdev->reset_state == RESET_STATE_RECV_PF_OFFLINE_REQ) { - qdma_device_offline(pdev, (unsigned long)xdev, - XDEV_FLR_INACTIVE); - } -} -#endif - -/*****************************************************************************/ -/** - * xdev_list_first() - handler to return the first xdev entry from the list - * - * @return pointer to first xlnx_dma_dev on success - * @return NULL on failure - *****************************************************************************/ -struct xlnx_dma_dev *xdev_list_first(void) -{ - struct xlnx_dma_dev *xdev; - - mutex_lock(&xdev_mutex); - xdev = list_first_entry(&xdev_list, struct xlnx_dma_dev, list_head); - mutex_unlock(&xdev_mutex); - - return xdev; -} - -/*****************************************************************************/ -/** - * xdev_list_next() - handler to return the next xdev entry from the list - * - * @param[in] xdev: pointer to current xdev - * - * @return pointer to next xlnx_dma_dev on success - * @return NULL on failure - *****************************************************************************/ -struct xlnx_dma_dev *xdev_list_next(struct xlnx_dma_dev *xdev) -{ - struct xlnx_dma_dev *next; - - mutex_lock(&xdev_mutex); - next = list_next_entry(xdev, list_head); - mutex_unlock(&xdev_mutex); - - return next; -} - -/*****************************************************************************/ -/** - * xdev_list_dump() - list the dma device details - * - * @param[in] buflen: length of the input buffer - * @param[out] buf: message buffer - * - * @return pointer to next xlnx_dma_dev on success - * @return NULL on failure - *****************************************************************************/ -int xdev_list_dump(char *buf, int buflen) -{ - struct xlnx_dma_dev *xdev, *tmp; - int len = 0; - - mutex_lock(&xdev_mutex); - list_for_each_entry_safe(xdev, tmp, &xdev_list, list_head) { - len += snprintf(buf + len, buflen - len, - "qdma%05x\t%02x:%02x.%02x\n", - xdev->conf.bdf, xdev->conf.pdev->bus->number, - PCI_SLOT(xdev->conf.pdev->devfn), - PCI_FUNC(xdev->conf.pdev->devfn)); - if (len >= buflen) - break; - } - mutex_unlock(&xdev_mutex); - - buf[len] = '\0'; - return len; -} - -/*****************************************************************************/ -/** - * xdev_list_add() - add a new node to the xdma device lsit - * - * @param[in] xdev: pointer to current xdev - * - * @return none - *****************************************************************************/ -static inline void xdev_list_add(struct xlnx_dma_dev *xdev) -{ - u32 bdf = 0; - struct xlnx_dma_dev *_xdev, *tmp; - u32 last_bus = 0; - u32 last_dev = 0; - - mutex_lock(&xdev_mutex); - bdf = ((xdev->conf.pdev->bus->number << PCI_SHIFT_BUS) | - (PCI_SLOT(xdev->conf.pdev->devfn) << PCI_SHIFT_DEV) | - PCI_FUNC(xdev->conf.pdev->devfn)); - xdev->conf.bdf = bdf; - list_add_tail(&xdev->list_head, &xdev_list); - - /* - * Iterate through the list of devices. Increment cfg_done, to - * get the mulitplier for initial configuration of queues. A - * '0' indicates queue is already configured. < 0, indicates - * config done using sysfs entry - */ - - list_for_each_entry_safe(_xdev, tmp, &xdev_list, list_head) { - - /*are we dealing with a different card?*/ -#ifdef __QDMA_VF__ - /** for VF check only bus number, as dev number can change - * in a single card - */ - if (last_bus != _xdev->conf.pdev->bus->number) -#else - if ((last_bus != _xdev->conf.pdev->bus->number) || - (last_dev != PCI_SLOT(_xdev->conf.pdev->devfn))) -#endif - xdev->conf.idx = 0; - xdev->conf.idx++; - last_bus = _xdev->conf.pdev->bus->number; - last_dev = PCI_SLOT(xdev->conf.pdev->devfn); - } - mutex_unlock(&xdev_mutex); -} - - -#undef list_last_entry -/*****************************************************************************/ -/** - * xdev_list_add() - remove a node from the xdma device lsit - * - * @param[in] xdev: pointer to current xdev - * - * @return none - *****************************************************************************/ -static inline void xdev_list_remove(struct xlnx_dma_dev *xdev) -{ - mutex_lock(&xdev_mutex); - list_del(&xdev->list_head); - mutex_unlock(&xdev_mutex); -} - -/*****************************************************************************/ -/** - * xdev_find_by_pdev() - find the xdev using struct pci_dev - * - * @param[in] pdev: pointer to struct pci_dev - * - * @return pointer to xlnx_dma_dev on success - * @return NULL on failure - *****************************************************************************/ -struct xlnx_dma_dev *xdev_find_by_pdev(struct pci_dev *pdev) -{ - struct xlnx_dma_dev *xdev, *tmp; - - mutex_lock(&xdev_mutex); - list_for_each_entry_safe(xdev, tmp, &xdev_list, list_head) { - if (xdev->conf.pdev == pdev) { - mutex_unlock(&xdev_mutex); - return xdev; - } - } - mutex_unlock(&xdev_mutex); - return NULL; -} - -/*****************************************************************************/ -/** - * xdev_find_by_idx() - find the xdev using the index value - * - * @param[in] idx: index value in the xdev list - * - * @return pointer to xlnx_dma_dev on success - * @return NULL on failure - *****************************************************************************/ -struct xlnx_dma_dev *xdev_find_by_idx(int idx) -{ - struct xlnx_dma_dev *xdev, *tmp; - - mutex_lock(&xdev_mutex); - list_for_each_entry_safe(xdev, tmp, &xdev_list, list_head) { - if (xdev->conf.bdf == idx) { - mutex_unlock(&xdev_mutex); - return xdev; - } - } - mutex_unlock(&xdev_mutex); - return NULL; -} - -/*****************************************************************************/ -/** - * xdev_check_hndl() - helper function to validate the device handle - * - * @param[in] pdev: pointer to struct pci_dev - * @param[in] hndl: device handle - * - * @return 0: success - * @return <0: on failure - *****************************************************************************/ -int xdev_check_hndl(const char *fname, struct pci_dev *pdev, unsigned long hndl) -{ - struct xlnx_dma_dev *xdev = (struct xlnx_dma_dev *)hndl; - - if (!pdev) - return -EINVAL; - - if (xdev->magic != QDMA_MAGIC_DEVICE) { - pr_err("%s xdev->magic %ld != %ld\n", - fname, xdev->magic, QDMA_MAGIC_DEVICE); - return -EINVAL; - } - - if (xdev->conf.pdev != pdev) { - pr_err("pci_dev(0x%lx) != pdev(0x%lx)\n", - (unsigned long)xdev->conf.pdev, - (unsigned long)pdev); - return -EINVAL; - } - - return 0; -} - -/********************************************************************** - * PCI-level Functions - **********************************************************************/ - -/*****************************************************************************/ -/** - * xdev_unmap_bars() - Unmap the BAR regions that had been mapped - * earlier using map_bars() - * - * @param[in] xdev: pointer to current xdev - * @param[in] pdev: pointer to struct pci_dev - * - * @return none - *****************************************************************************/ -static void xdev_unmap_bars(struct xlnx_dma_dev *xdev, struct pci_dev *pdev) -{ - if (xdev->regs) { - /* unmap BAR */ - pci_iounmap(pdev, xdev->regs); - /* mark as unmapped */ - xdev->regs = NULL; - } -} - -/*****************************************************************************/ -/** - * xdev_map_bars() - map device regions into kernel virtual address space - * earlier using map_bars() - * - * @param[in] xdev: pointer to current xdev - * @param[in] pdev: pointer to struct pci_dev - * - * Map the device memory regions into kernel virtual address space after - * verifying their sizes respect the minimum sizes needed - * - * @return length of the bar on success - * @return 0 on failure - *****************************************************************************/ -static int xdev_map_bars(struct xlnx_dma_dev *xdev, struct pci_dev *pdev) -{ - int map_len; - - map_len = pci_resource_len(pdev, (int)xdev->conf.bar_num_config); - if (map_len > QDMA_MAX_BAR_LEN_MAPPED) - map_len = QDMA_MAX_BAR_LEN_MAPPED; - - xdev->regs = pci_iomap(pdev, xdev->conf.bar_num_config, map_len); - if (!xdev->regs || - map_len < QDMA_MIN_BAR_LEN_MAPPED) { - pr_err("%s unable to map config bar %d.\n", xdev->conf.name, - xdev->conf.bar_num_config); - return -EINVAL; - } - - return 0; -} - -/*****************************************************************************/ -/** - * xdev_identify_bars() - identifies the AXI Master Lite bar - * and AXI Bridge Master bar - * - * @param[in] xdev: pointer to current xdev - * @param[in] pdev: pointer to struct pci_dev\ - * - * @return 0 on success, -ve on failure - *****************************************************************************/ -static int xdev_identify_bars(struct xlnx_dma_dev *xdev, struct pci_dev *pdev) -{ - int bar_idx = 0; - int rv = 0; - u8 num_bars_present = 0; - int bar_id_list[QDMA_BAR_NUM]; - int bar_id_idx = 0; - - /* Find out the number of bars present in the design */ - for (bar_idx = 0; bar_idx < QDMA_BAR_NUM; bar_idx++) { - int map_len = 0; - - map_len = pci_resource_len(pdev, bar_idx); - if (!map_len) - continue; - - bar_id_list[bar_id_idx] = bar_idx; - bar_id_idx++; - num_bars_present++; - } - - if (num_bars_present > 1) { - - /* AXI Master Lite BAR IDENTIFICATION */ - if ((xdev->version_info.ip_type == QDMA_VERSAL_HARD_IP) && - (xdev->version_info.device_type == - QDMA_DEVICE_VERSAL_CPM4)) - xdev->conf.bar_num_user = DEFAULT_USER_BAR; - else { -#ifndef __QDMA_VF__ - rv = xdev->hw.qdma_get_user_bar(xdev, 0, - xdev->func_id, - (uint8_t *)&xdev->conf.bar_num_user); -#else - rv = xdev->hw.qdma_get_user_bar(xdev, 1, - xdev->func_id_parent, - (uint8_t *)&xdev->conf.bar_num_user); -#endif - } - - if (rv < 0) { - pr_err("get AXI Master Lite bar failed with error = %d", - rv); -#ifdef __XRT__ - /** This change is for XRT application, - * when there is no user BAR in desin - */ - rv = QDMA_ERR_HWACC_BAR_NOT_FOUND; -#else - return xdev->hw.qdma_get_error_code(rv); -#endif - } - - pr_info("AXI Master Lite BAR %d.\n", - xdev->conf.bar_num_user); - - /* AXI Bridge Master BAR IDENTIFICATION */ - if (num_bars_present > 2) { - for (bar_idx = 0; bar_idx < num_bars_present; - bar_idx++) { - if ((bar_id_list[bar_idx] != - xdev->conf.bar_num_user) && - (bar_id_list[bar_idx] != - xdev->conf.bar_num_config)) { - xdev->conf.bar_num_bypass = - bar_id_list[bar_idx]; - pr_info("AXI Bridge Master BAR %d.\n", - xdev->conf.bar_num_bypass); - break; - } - } - } - } - return rv; -} - -/*****************************************************************************/ -/** - * xdev_alloc() - allocate the dma device - * - * @param[in] conf: qdma device configuration - * - * - * @return pointer to dma device - * @return NULL on failure - *****************************************************************************/ -static struct xlnx_dma_dev *xdev_alloc(struct qdma_dev_conf *conf) -{ - struct xlnx_dma_dev *xdev; - - /* allocate zeroed device book keeping structure */ - xdev = kzalloc(sizeof(struct xlnx_dma_dev), GFP_KERNEL); - if (!xdev) - return NULL; - - spin_lock_init(&xdev->hw_prg_lock); - spin_lock_init(&xdev->lock); - - /* create a driver to device reference */ - memcpy(&xdev->conf, conf, sizeof(*conf)); - - xdev->magic = QDMA_MAGIC_DEVICE; - - /* !! FIXME default to enabled for everything */ - xdev->dev_cap.flr_present = 1; - xdev->dev_cap.st_en = 1; - xdev->dev_cap.mm_en = 1; - xdev->dev_cap.mm_channel_max = 1; - - return xdev; -} - -#ifndef __QDMA_VF__ -static void qdma_err_mon(struct work_struct *work) -{ - struct delayed_work *dwork = container_of(work, - struct delayed_work, work); - struct xlnx_dma_dev *xdev = container_of(dwork, - struct xlnx_dma_dev, err_mon); - - if (!xdev) { - pr_err("Invalid xdev"); - return; - } - spin_lock(&xdev->err_lock); - - if (xdev->err_mon_cancel == 0) { - xdev->hw.qdma_hw_error_process(xdev); - schedule_delayed_work(dwork, msecs_to_jiffies(1000));/* 1 sec */ - } - spin_unlock(&xdev->err_lock); -} -#endif - - - -/*****************************************************************************/ -/** - * qdma_device_offline() - set the dma device in offline mode - * - * @param[in] pdev: pointer to struct pci_dev - * @param[in] dev_hndl: device handle - * @param[in] reset: 0/1 function level reset active or not - * - * @return 0: on success - * @return <0: on failure - *****************************************************************************/ -int qdma_device_offline(struct pci_dev *pdev, unsigned long dev_hndl, - int reset) -{ - struct xlnx_dma_dev *xdev = (struct xlnx_dma_dev *)dev_hndl; - - if (!xdev) { - pr_err("dev_hndl is NULL"); - return -EINVAL; - } - - if (xdev_check_hndl(__func__, pdev, dev_hndl) < 0) { - pr_err("Invalid dev_hndl passed"); - return -EINVAL; - } - - if (xdev->conf.pdev != pdev) { - pr_err("Invalid pdev passed: pci_dev(0x%lx) != pdev(0x%lx)\n", - (unsigned long)xdev->conf.pdev, (unsigned long)pdev); - return -EINVAL; - } - - if (xlnx_dma_device_flag_check(xdev, XDEV_FLAG_OFFLINE)) { -#ifdef __QDMA_VF__ - if (xdev->workq != NULL) { - pr_debug("destroy workq\n"); - destroy_workqueue(xdev->workq); - xdev->workq = NULL; - } -#endif - return 0; - } - -#ifdef __QDMA_VF__ - if (xdev->reset_state == RESET_STATE_PF_OFFLINE_REQ_PROCESSING) { - int retry_cnt = 10; - - while (!xlnx_dma_device_flag_check(xdev, XDEV_FLAG_OFFLINE)) { - mdelay(100); - if (retry_cnt == 0) - break; - retry_cnt--; - } - if (xdev->workq != NULL) { - destroy_workqueue(xdev->workq); - xdev->workq = NULL; - } - return 0; - } -#endif - /* Canceling the error poll thread which was started - * in the poll mode - */ -#ifndef __QDMA_VF__ - if ((xdev->conf.master_pf) && - (xdev->conf.qdma_drv_mode == POLL_MODE)) { - pr_debug("Cancelling delayed work"); - spin_lock(&xdev->err_lock); - xdev->err_mon_cancel = 1; - cancel_delayed_work_sync(&xdev->err_mon); - spin_unlock(&xdev->err_lock); - } -#endif - - qdma_device_cleanup(xdev); - qdma_device_interrupt_cleanup(xdev); - qdma_mbox_stop(xdev); - intr_teardown(xdev); - xdev->flags &= ~(XDEV_FLAG_IRQ); - - /* - * When the FLR is done to parent PF , it's associated VFs - * and it's resources are no more active. The - * interrupt state of the VF goes bad. That's why switching - * from mbox's interrupt mode to poll mode - */ - qdma_mbox_poll_start(xdev); -#ifdef __QDMA_VF__ - if (reset) { - if (xdev->reset_state == RESET_STATE_RECV_PF_RESET_REQ) { - - xdev_sriov_vf_reset_offline(xdev); - - /** Wait for the PF to send the PF Reset Done*/ - qdma_waitq_wait_event_timeout(xdev->wq, - (xdev->reset_state == - RESET_STATE_RECV_PF_RESET_DONE), - 10 * QDMA_MBOX_MSG_TIMEOUT_MS); - - if (xdev->reset_state != RESET_STATE_RECV_PF_RESET_DONE) - xdev->reset_state = RESET_STATE_INVALID; - } else - xdev_sriov_vf_offline(xdev, 0); - - } else { - if (xdev->reset_state == RESET_STATE_RECV_PF_OFFLINE_REQ) { - xdev_sriov_vf_offline(xdev, 0); - xdev->reset_state = - RESET_STATE_PF_OFFLINE_REQ_PROCESSING; - } else { - xdev_sriov_vf_offline(xdev, 0); - destroy_workqueue(xdev->workq); - xdev->workq = NULL; - } - } - qdma_mbox_stop(xdev); -#elif defined(CONFIG_PCI_IOV) - if (!reset) { - qdma_pf_trigger_vf_offline((unsigned long)xdev); - xdev_sriov_disable(xdev); - } else if (xdev->vf_count_online != 0) { - qdma_pf_trigger_vf_reset((unsigned long)xdev); - qdma_mbox_stop(xdev); - } - -#endif - - if (reset) { - /* Free the allocated resources if FLR process running*/ - if (xdev->conf.fp_flr_free_resource) - xdev->conf.fp_flr_free_resource((unsigned long)xdev); - } - - if (xdev->conf.qdma_drv_mode != POLL_MODE) - xdev->mbox.rx_poll = 0; - - xdev_flag_set(xdev, XDEV_FLAG_OFFLINE); - if (xdev->dev_cap.mailbox_en) - qdma_mbox_cleanup(xdev); - - return 0; -} - -/*****************************************************************************/ -/** - * qdma_device_online() - set the dma device in online mode - * - * @param[in] pdev: pointer to struct pci_dev - * @param[in] dev_hndl: device handle - * @param[in] reset: 0/1 function level reset active or not - * - * @return 0: on success - * @return <0: on failure - *****************************************************************************/ -int qdma_device_online(struct pci_dev *pdev, unsigned long dev_hndl, int reset) -{ - struct xlnx_dma_dev *xdev = (struct xlnx_dma_dev *)dev_hndl; - int rv; -#if !defined(__QDMA_VF__) - struct qdma_vf_info *vf; -#endif - if (!xdev) { - pr_err("Invalid device handle received"); - return -EINVAL; - } - - - if (xdev_check_hndl(__func__, pdev, dev_hndl) < 0) { - pr_err("Invalid device"); - return -EINVAL; - } - - if (xdev->conf.pdev != pdev) { - pr_err("pci_dev(0x%lx) != pdev(0x%lx)\n", - (unsigned long)xdev->conf.pdev, (unsigned long)pdev); - } - -#if defined(__QDMA_VF__) - pr_info("reset_state = %d", xdev->reset_state); - if (reset && xdev->reset_state == RESET_STATE_INVALID) { - pr_info("returning"); - return -EINVAL; - } -#endif - - if (xdev->conf.qdma_drv_mode != POLL_MODE && - xdev->conf.qdma_drv_mode != LEGACY_INTR_MODE) { - - if ((xdev->flags & XDEV_FLAG_IRQ) == 0x0) { - rv = intr_setup(xdev); - if (rv) { - pr_err("Failed to setup interrupts, err %d", - rv); - return -EINVAL; - } - } - xdev->flags |= XDEV_FLAG_IRQ; - } - -#ifndef __QDMA_VF__ - if (xdev->dev_cap.mailbox_en) - qdma_mbox_init(xdev); -#else - qdma_mbox_init(xdev); - if (!reset) { - qdma_waitq_init(&xdev->wq); - INIT_WORK(&xdev->reset_work, xdev_reset_work); - xdev->workq = create_singlethread_workqueue("Reset Work Queue"); - } -#endif - rv = qdma_device_init(xdev); - if (rv < 0) { - pr_warn("qdma_init failed %d.\n", rv); - return rv; - } - xdev_flag_clear(xdev, XDEV_FLAG_OFFLINE); -#ifdef __QDMA_VF__ - qdma_mbox_start(xdev); - /* PF mbox will start when vf > 0 */ - rv = xdev_sriov_vf_online(xdev, 0); - if (rv < 0) - return rv; -#endif - rv = qdma_device_interrupt_setup(xdev); - if (rv < 0) { - pr_err("Failed to setup device interrupts"); - return rv; - } - - /* Starting a error poll thread in Poll mode */ -#ifndef __QDMA_VF__ - if ((xdev->conf.master_pf) && - (xdev->conf.qdma_drv_mode == POLL_MODE)) { - - rv = xdev->hw.qdma_hw_error_enable(xdev, - xdev->hw.qdma_max_errors); - if (rv < 0) { - pr_err("Failed to enable error interrupts"); - return -EINVAL; - } - - spin_lock_init(&xdev->err_lock); - xdev->err_mon_cancel = 0; - INIT_DELAYED_WORK(&xdev->err_mon, qdma_err_mon); - schedule_delayed_work(&xdev->err_mon, - msecs_to_jiffies(1000)); - } - - /** - * Send the RESET_DONE message to VF - */ - if (reset && xdev->vf_count != 0) { - int i = 0; - - vf = (struct qdma_vf_info *)xdev->vf_info; - - if (!vf) { - pr_err("Invalid vf handle received"); - return -EINVAL; - } - - qdma_mbox_start(xdev); - for (i = 0; i < xdev->vf_count; i++) { - struct mbox_msg *m = NULL; - u8 vf_count_online = xdev->vf_count_online; - - m = qdma_mbox_msg_alloc(); - if (!m) { - pr_err("Failed to allocate mbox msg\n"); - return -ENOMEM; - } - qdma_mbox_compose_pf_reset_done_message(m->raw, - xdev->func_id, vf[i].func_id); - qdma_mbox_msg_send(xdev, m, 1, - QDMA_MBOX_MSG_TIMEOUT_MS); - - qdma_waitq_wait_event_timeout(xdev->wq, - (xdev->vf_count_online == - (vf_count_online + 1)), - QDMA_MBOX_MSG_TIMEOUT_MS); - } - } - -#endif - - return 0; -} - -/*****************************************************************************/ -/** - * qdma_device_open() - open the dma device - * - * @param[in] mod_name: name of the dma device - * @param[in] conf: device configuration - * @param[in] dev_hndl: device handle - * - * - * @return 0: on success - * @return <0: on failure - *****************************************************************************/ -int qdma_device_open(const char *mod_name, struct qdma_dev_conf *conf, - unsigned long *dev_hndl) -{ - struct pci_dev *pdev = NULL; - struct xlnx_dma_dev *xdev = NULL; - int rv = 0; -#ifndef __QDMA_VF__ - int qbase = QDMA_QBASE; - int qmax = QDMA_TOTAL_Q; -#endif - - *dev_hndl = 0UL; - - if (!mod_name) { - pr_err("%s: mod_name is NULL.\n", __func__); - return -EINVAL; - } - - if (!conf) { - pr_err("%s: queue_conf is NULL.\n", mod_name); - return -EINVAL; - } - - if (conf->qdma_drv_mode > LEGACY_INTR_MODE) { - pr_err("%s: driver mode passed in Invalid.\n", mod_name); - return -EINVAL; - } - - pdev = conf->pdev; - - if (!pdev) { - pr_err("%s: pci device NULL.\n", mod_name); - return -EINVAL; - } - pr_info("%s, %02x:%02x.%02x, pdev 0x%p, 0x%x:0x%x.\n", - mod_name, pdev->bus->number, PCI_SLOT(pdev->devfn), - PCI_FUNC(pdev->devfn), pdev, pdev->vendor, pdev->device); - - xdev = xdev_find_by_pdev(pdev); - if (xdev) { - pr_warn("%s, device %s already attached!\n", - mod_name, dev_name(&pdev->dev)); - return -EINVAL; - } - -#ifndef __XRT__ - rv = pci_request_regions(pdev, mod_name); - if (rv) { - /* Just info, some other driver may have claimed the device. */ - dev_info(&pdev->dev, "cannot obtain PCI resources\n"); - return rv; - } -#endif - - rv = pci_enable_device(pdev); - if (rv) { - dev_err(&pdev->dev, "cannot enable PCI device\n"); - goto release_regions; - } - - /* enable relaxed ordering */ - pci_enable_relaxed_ordering(pdev); - - /* enable extended tag */ - pci_enable_extended_tag(pdev); - - /* enable bus master capability */ - pci_set_master(pdev); - - rv = pci_dma_mask_set(pdev); - if (rv) { - pr_err("Failed to set the dma mask"); - goto disable_device; - } - - if (pcie_get_readrq(pdev) < 512) - pcie_set_readrq(pdev, 512); - - /* allocate zeroed device book keeping structure */ - xdev = xdev_alloc(conf); - if (!xdev) { - pr_err("Failed to allocate xdev"); - goto disable_device; - } - - strncpy(xdev->mod_name, mod_name, QDMA_DEV_NAME_MAXLEN - 1); - - xdev_flag_set(xdev, XDEV_FLAG_OFFLINE); - xdev_list_add(xdev); - - rv = snprintf(xdev->conf.name, QDMA_DEV_NAME_MAXLEN, - "qdma%05x-p%s", - xdev->conf.bdf, dev_name(&xdev->conf.pdev->dev)); - xdev->conf.name[rv] = '\0'; - - /* Mapping bars */ - rv = xdev_map_bars(xdev, pdev); - if (rv) { - pr_err("Failed to map the bars"); - goto unmap_bars; - } - - /* Get HW access */ -#ifndef __QDMA_VF__ - rv = qdma_hw_access_init(xdev, 0, &xdev->hw); - if (rv != QDMA_SUCCESS) { - rv = -EINVAL; - goto unmap_bars; - } - - rv = xdev->hw.qdma_get_version(xdev, 0, &xdev->version_info); - if (rv != QDMA_SUCCESS) { - rv = xdev->hw.qdma_get_error_code(rv); - pr_err("Failed to get the HW Version"); - goto unmap_bars; - } - - /* get the device attributes */ - qdma_device_attributes_get(xdev); - qmax = xdev->dev_cap.num_qs; - if (pdev->bus->parent) - rv = qdma_master_resource_create(pdev->bus->number, - pci_bus_max_busnr(pdev->bus->parent), qbase, - qmax, &xdev->dma_device_index); - else - rv = qdma_master_resource_create(pdev->bus->number, - pdev->bus->number, qbase, - qmax, &xdev->dma_device_index); - - if (rv == -QDMA_ERR_NO_MEM) { - pr_err("master_resource_create failed, err = %d", rv); - rv = -ENOMEM; - goto unmap_bars; - } -#else - rv = qdma_hw_access_init(xdev, 1, &xdev->hw); - if (rv != QDMA_SUCCESS) - goto unmap_bars; - rv = xdev->hw.qdma_get_version(xdev, 1, &xdev->version_info); - if (rv != QDMA_SUCCESS) - goto unmap_bars; -#endif - - pr_info("Vivado version = %s\n", - xdev->version_info.qdma_vivado_release_id_str); - -#ifndef __QDMA_VF__ - rv = xdev->hw.qdma_get_function_number(xdev, &xdev->func_id); - if (rv < 0) { - pr_err("get function number failed, err = %d", rv); - rv = -EINVAL; - goto unmap_bars; - } - - rv = qdma_dev_qinfo_get(xdev->dma_device_index, xdev->func_id, - &xdev->conf.qsets_base, - &xdev->conf.qsets_max); - if (rv < 0) { - rv = qdma_dev_entry_create(xdev->dma_device_index, - xdev->func_id); - if (rv < 0) { - pr_err("Failed to create device entry, err = %d", rv); - rv = -ENODEV; - goto unmap_bars; - } - } - - rv = qdma_dev_update(xdev->dma_device_index, xdev->func_id, - xdev->conf.qsets_max, &xdev->conf.qsets_base); - if (rv < 0) { - pr_err("qdma_dev_update function call failed, err = %d\n", rv); - rv = xdev->hw.qdma_get_error_code(rv); - goto unmap_bars; - } - - if (!xdev->dev_cap.mm_en && !xdev->dev_cap.st_en) { - pr_err("None of the modes ( ST or MM) are enabled\n"); - rv = -EINVAL; - goto unmap_bars; - } -#endif - -#ifdef __QDMA_VF__ - if ((conf->qdma_drv_mode != POLL_MODE) && - (xdev->version_info.ip_type == QDMA_VERSAL_HARD_IP) && - (xdev->version_info.device_type == QDMA_DEVICE_VERSAL_CPM4)) { - pr_warn("VF is not supported in %s mode\n", - mode_name_list[conf->qdma_drv_mode].name); - pr_info("Switching VF to poll mode\n"); - xdev->conf.qdma_drv_mode = POLL_MODE; - } -#endif - - if ((conf->qdma_drv_mode == LEGACY_INTR_MODE) && - (!xdev->dev_cap.legacy_intr)) { - dev_err(&pdev->dev, "Legacy mode interrupts are not supported\n"); - goto unmap_bars; - } - - rv = qdma_device_online(pdev, (unsigned long)xdev, XDEV_FLR_INACTIVE); - if (rv < 0) { - pr_warn("Failed to set the dma device online, err = %d", rv); - goto cleanup_qdma; - } - - rv = xdev_identify_bars(xdev, pdev); - if (rv < 0) { - pr_err("Failed to identify bars, err %d", rv); - goto unmap_bars; - } - - memcpy(conf, &xdev->conf, sizeof(*conf)); - - pr_info("%s, %05x, pdev 0x%p, xdev 0x%p, ch %u, q %u, vf %u.\n", - dev_name(&pdev->dev), xdev->conf.bdf, pdev, xdev, - xdev->dev_cap.mm_channel_max, conf->qsets_max, conf->vf_max); - -#ifdef DEBUGFS - /** time to clean debugfs */ - dbgfs_dev_init(xdev); -#endif - - *dev_hndl = (unsigned long)xdev; - - return rv; - -cleanup_qdma: - qdma_device_offline(pdev, (unsigned long)xdev, XDEV_FLR_INACTIVE); - -unmap_bars: - xdev_unmap_bars(xdev, pdev); - xdev_list_remove(xdev); - kfree(xdev); - -disable_device: - pci_disable_extended_tag(pdev); - pci_disable_relaxed_ordering(pdev); - pci_disable_device(pdev); - -release_regions: -#ifndef __XRT__ - pci_release_regions(pdev); -#endif - - return rv; -} - -/*****************************************************************************/ -/** - * qdma_device_close() - close the dma device - * - * @param[in] pdev: pointer to struct pci_dev - * @param[in] dev_hndl: device handle - * - * @return 0: on success - * @return <0: on failure - *****************************************************************************/ -int qdma_device_close(struct pci_dev *pdev, unsigned long dev_hndl) -{ - struct xlnx_dma_dev *xdev = (struct xlnx_dma_dev *)dev_hndl; - - if (!dev_hndl) { - pr_err("dev_hndl is NULL"); - return -EINVAL; - } - - if (xdev_check_hndl(__func__, pdev, dev_hndl) < 0) { - pr_err("Invalid dev_hndl passed"); - return -EINVAL; - } - - if (xdev->conf.pdev != pdev) { - pr_err("Invalid pdev passed: pci_dev(0x%lx) != pdev(0x%lx)\n", - (unsigned long)xdev->conf.pdev, (unsigned long)pdev); - return -EINVAL; - } - - qdma_device_offline(pdev, dev_hndl, XDEV_FLR_INACTIVE); - -#ifdef DEBUGFS - /** time to clean debugfs */ - dbgfs_dev_exit(xdev); -#endif -#ifndef __QDMA_VF__ - qdma_dev_entry_destroy(xdev->dma_device_index, xdev->func_id); - qdma_master_resource_destroy(xdev->dma_device_index); -#endif - - xdev_unmap_bars(xdev, pdev); - - pci_disable_relaxed_ordering(pdev); - pci_disable_extended_tag(pdev); -#ifndef __XRT__ - pci_release_regions(pdev); -#endif - pci_disable_device(pdev); - - xdev_list_remove(xdev); - - kfree(xdev); - - return 0; -} - -/*****************************************************************************/ -/** - * qdma_device_get_config() - get the device configuration - * - * @param[in] dev_hndl: device handle - * @param[out] conf: dma device configuration - * @param[out] buf, buflen: - * error message buffer, can be NULL/0 (i.e., optional) - * - * - * @return none - *****************************************************************************/ -int qdma_device_get_config(unsigned long dev_hndl, struct qdma_dev_conf *conf, - char *buf, int buflen) -{ - struct xlnx_dma_dev *xdev = (struct xlnx_dma_dev *)dev_hndl; - - /** make sure that the dev_hndl passed is Valid */ - if (!xdev) { - pr_err("dev_hndl is NULL"); - if (buf && buflen) - snprintf(buf, buflen, "dev_hndl is NULL"); - return -EINVAL; - } - - if (xdev_check_hndl(__func__, xdev->conf.pdev, dev_hndl) < 0) { - pr_err("Invalid dev_hndl passed"); - if (buf && buflen) - snprintf(buf, buflen, "Invalid dev_hndl passed"); - return -EINVAL; - } - - memcpy(conf, &xdev->conf, sizeof(*conf)); - - if (buf && buflen) - snprintf(buf, buflen, - "Device %s configuration is stored in conf param", - xdev->conf.name); - - return 0; -} - -int qdma_device_clear_stats(unsigned long dev_hndl) -{ - struct xlnx_dma_dev *xdev = (struct xlnx_dma_dev *) dev_hndl; - - /** make sure that the dev_hndl passed is Valid */ - if (!xdev) { - pr_err("dev_hndl is NULL"); - return -EINVAL; - } - - if (xdev_check_hndl(__func__, xdev->conf.pdev, dev_hndl) < 0) { - pr_err("Invalid dev_hndl passed"); - return -EINVAL; - } - - xdev->total_mm_h2c_pkts = 0; - xdev->total_mm_c2h_pkts = 0; - xdev->total_st_h2c_pkts = 0; - xdev->total_st_c2h_pkts = 0; - xdev->ping_pong_lat_max = 0; - xdev->ping_pong_lat_min = 0; - xdev->ping_pong_lat_total = 0; - - return 0; -} - -int qdma_device_get_mmh2c_pkts(unsigned long dev_hndl, - unsigned long long *mmh2c_pkts) -{ - struct xlnx_dma_dev *xdev = (struct xlnx_dma_dev *) dev_hndl; - - /** make sure that the dev_hndl passed is Valid */ - if (!xdev) { - pr_err("dev_hndl is NULL"); - return -EINVAL; - } - - if (xdev_check_hndl(__func__, xdev->conf.pdev, dev_hndl) < 0) { - pr_err("Invalid dev_hndl passed"); - return -EINVAL; - } - - *mmh2c_pkts = xdev->total_mm_h2c_pkts; - - return 0; -} - -int qdma_device_get_mmc2h_pkts(unsigned long dev_hndl, - unsigned long long *mmc2h_pkts) -{ - struct xlnx_dma_dev *xdev = (struct xlnx_dma_dev *) dev_hndl; - - /** make sure that the dev_hndl passed is Valid */ - if (!xdev) { - pr_err("dev_hndl is NULL"); - return -EINVAL; - } - - if (xdev_check_hndl(__func__, xdev->conf.pdev, dev_hndl) < 0) { - pr_err("Invalid dev_hndl passed"); - return -EINVAL; - } - - *mmc2h_pkts = xdev->total_mm_c2h_pkts; - - return 0; -} - -int qdma_device_get_sth2c_pkts(unsigned long dev_hndl, - unsigned long long *sth2c_pkts) -{ - struct xlnx_dma_dev *xdev = (struct xlnx_dma_dev *) dev_hndl; - - /** make sure that the dev_hndl passed is Valid */ - if (!xdev) { - pr_err("dev_hndl is NULL"); - return -EINVAL; - } - - if (xdev_check_hndl(__func__, xdev->conf.pdev, dev_hndl) < 0) { - pr_err("Invalid dev_hndl passed"); - return -EINVAL; - } - - *sth2c_pkts = xdev->total_st_h2c_pkts; - - return 0; -} - -int qdma_device_get_stc2h_pkts(unsigned long dev_hndl, - unsigned long long *stc2h_pkts) -{ - struct xlnx_dma_dev *xdev = (struct xlnx_dma_dev *) dev_hndl; - - /** make sure that the dev_hndl passed is Valid */ - if (!xdev) { - pr_err("dev_hndl is NULL"); - return -EINVAL; - } - - if (xdev_check_hndl(__func__, xdev->conf.pdev, dev_hndl) < 0) { - pr_err("Invalid dev_hndl passed"); - return -EINVAL; - } - - *stc2h_pkts = xdev->total_st_c2h_pkts; - - return 0; -} - -int qdma_device_get_ping_pong_min_lat(unsigned long dev_hndl, - unsigned long long *min_lat) -{ - struct xlnx_dma_dev *xdev = (struct xlnx_dma_dev *) dev_hndl; - - /** make sure that the dev_hndl passed is Valid */ - if (!xdev) { - pr_err("dev_hndl is NULL"); - return -EINVAL; - } - - if (!min_lat) { - pr_err("Min Lat is NULL\n"); - return -EINVAL; - } - if (xdev_check_hndl(__func__, xdev->conf.pdev, dev_hndl) < 0) { - pr_err("Invalid dev_hndl passed"); - return -EINVAL; - } - - *min_lat = xdev->ping_pong_lat_min; - - return 0; -} - -int qdma_device_get_ping_pong_max_lat(unsigned long dev_hndl, - unsigned long long *max_lat) -{ - struct xlnx_dma_dev *xdev = (struct xlnx_dma_dev *) dev_hndl; - - /** make sure that the dev_hndl passed is Valid */ - if (!xdev) { - pr_err("dev_hndl is NULL"); - return -EINVAL; - } - - if (!max_lat) { - pr_err("Max Lat is NULL\n"); - return -EINVAL; - } - if (xdev_check_hndl(__func__, xdev->conf.pdev, dev_hndl) < 0) { - pr_err("Invalid dev_hndl passed"); - return -EINVAL; - } - - *max_lat = xdev->ping_pong_lat_max; - - return 0; -} - -int qdma_device_get_ping_pong_tot_lat(unsigned long dev_hndl, - unsigned long long *lat_total) -{ - struct xlnx_dma_dev *xdev = (struct xlnx_dma_dev *) dev_hndl; - - /** make sure that the dev_hndl passed is Valid */ - if (!xdev) { - pr_err("dev_hndl is NULL"); - return -EINVAL; - } - - if (!lat_total) { - pr_err("Total Lat is NULL\n"); - return -EINVAL; - } - if (xdev_check_hndl(__func__, xdev->conf.pdev, dev_hndl) < 0) { - pr_err("Invalid dev_hndl passed"); - return -EINVAL; - } - - *lat_total = xdev->ping_pong_lat_total; - - return 0; -} -/*****************************************************************************/ -/** - * qdma_device_set_config() - set the device configuration - * - * @param[in] dev_hndl: device handle - * @param[in] conf: dma device configuration to set - * - * @return 0 on success ,<0 on failure - *****************************************************************************/ -int qdma_device_set_config(unsigned long dev_hndl, struct qdma_dev_conf *conf) -{ - struct xlnx_dma_dev *xdev = (struct xlnx_dma_dev *)dev_hndl; - - /** make sure that the dev_hndl passed is Valid */ - if (!xdev) { - pr_err("dev_hndl is NULL"); - return -EINVAL; - } - - if (!conf) { - pr_err("conf is NULL"); - return -EINVAL; - } - - if (xdev_check_hndl(__func__, xdev->conf.pdev, dev_hndl) < 0) - return -EINVAL; - - memcpy(&xdev->conf, conf, sizeof(*conf)); - - return 0; -} - diff --git a/QDMA/linux-kernel/driver/libqdma/xdev.h b/QDMA/linux-kernel/driver/libqdma/xdev.h deleted file mode 100755 index 47c26b43c..000000000 --- a/QDMA/linux-kernel/driver/libqdma/xdev.h +++ /dev/null @@ -1,610 +0,0 @@ -/* - * This file is part of the Xilinx DMA IP Core driver for Linux - * - * Copyright (c) 2017-2022, Xilinx, Inc. All rights reserved. - * Copyright (c) 2022, Advanced Micro Devices, Inc. All rights reserved. - * - * This source code is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * The full GNU General Public License is included in this distribution in - * the file called "COPYING". - */ - -#ifndef __XDEV_H__ -#define __XDEV_H__ -/** - * @file - * @brief This file contains the declarations for QDMA PCIe device - * - */ -#include -#include -#include -#include - -#include "libqdma_export.h" -#include "qdma_mbox.h" -#include "qdma_access_errors.h" -#ifdef DEBUGFS -#include "qdma_debugfs.h" - -extern struct dentry *qdma_debugfs_root; -#endif - -#define DEFAULT_USER_BAR 2 - -/** - * QDMA bars - */ -#define QDMA_BAR_NUM 6 -/** - * QDMA config bar size - 64MB - */ -#define QDMA_MAX_BAR_LEN_MAPPED 0x4000000 -/** - * Min QDMA config bar size - 16K - */ -#define QDMA_MIN_BAR_LEN_MAPPED 0x4000 - -/* - *module_param_array: - *config_bar= - * - *config_bar= - * - * - * - */ -#define BUS_NUM_MASK 0xFFFF0000 -#define BUS_NUM_SHIFT 16 - -#define PF_DEV_0_MASK 0x0000F000 -#define PF_DEV_0_SHIFT 12 -#define PF_DEV_1_MASK 0x00000F00 -#define PF_DEV_1_SHIFT 8 -#define PF_DEV_2_MASK 0x000000F0 -#define PF_DEV_2_SHIFT 4 -#define PF_DEV_3_MASK 0x0000000F -#define PF_DEV_3_SHIFT 0 - -#define VF_PF_IDENTIFIER_MASK 0xF -#define VF_PF_IDENTIFIER_SHIFT 8 - -#define QDMA_MAGIC_DEVICE 0xEEEEEEEEUL - -enum qdma_pf_devices { - PF_DEVICE_0 = 0, - PF_DEVICE_1, - PF_DEVICE_2, - PF_DEVICE_3 -}; - -/** - * number of bits to describe the DMA transfer descriptor - */ -#define QDMA_DESC_BLEN_BITS 28 -/** - * maximum size of a single DMA transfer descriptor - */ -#define QDMA_DESC_BLEN_MAX ((1 << (QDMA_DESC_BLEN_BITS)) - 1) - -/** - * obtain the 32 most significant (high) bits of a 32-bit or 64-bit address - */ -#define PCI_DMA_H(addr) ((addr >> 16) >> 16) -/** - * obtain the 32 least significant (low) bits of a 32-bit or 64-bit address - */ -#define PCI_DMA_L(addr) (addr & 0xffffffffUL) - -/** - * Xiling DMA device forward declaration - */ -struct xlnx_dma_dev; - -/* XDMA PCIe device specific book-keeping */ -/** - * Flag for device offline - */ -#define XDEV_FLAG_OFFLINE 0x1 -/** - * Flag for IRQ - */ -#define XDEV_FLAG_IRQ 0x2 -/** - * Maximum number of interrupts supported per device - */ -#define XDEV_NUM_IRQ_MAX 8 - -/** - * Macro to indicate FLR flow is active - */ -#define XDEV_FLR_ACTIVE 1 -/** - * Macro to indicate FLR flow is not active - */ -#define XDEV_FLR_INACTIVE 0 -/** - * interrupt call back function handlers - */ -typedef irqreturn_t (*f_intr_handler)(int irq_index, int irq, void *dev_id); - -/** - * @struct - intr_coal_conf - * @brief interrut coalescing configuration - */ -struct intr_coal_conf { - /**< interrupt vector index */ - u16 vec_id; - /**< number of entries in interrupt ring per vector */ - u16 intr_rng_num_entries; - /**< interrupt ring base address */ - dma_addr_t intr_ring_bus; - union qdma_intr_ring *intr_ring_base; - /**< color value indicates the valid entry in the interrupt ring */ - u8 color; - /**< Interrupt cidx info to be written to INTR CIDX register */ - struct qdma_intr_cidx_reg_info intr_cidx_info; -}; - -/** - * Macros for Hardware Version info - */ -#define RTL1_VERSION 0 -#define RTL2_VERSION 1 -#define VIVADO_RELEASE_2018_3 0 -#define VIVADO_RELEASE_2018_2 1 - -/** - * intr_type_list - interrupt types - */ -enum intr_type_list { - INTR_TYPE_ERROR, /**< error interrupt */ - INTR_TYPE_USER, /**< user interrupt */ - INTR_TYPE_DATA, /**< data interrupt */ - INTR_TYPE_MBOX, /**< mail box interrupt */ - INTR_TYPE_MAX /**< max interrupt */ -}; - -/** - * reset_state - Keep track of state during FLR - */ -enum reset_state_t { - RESET_STATE_IDLE, - RESET_STATE_RECV_PF_RESET_REQ, - RESET_STATE_PF_WAIT_FOR_BYES, - RESET_STATE_RECV_PF_RESET_DONE, - RESET_STATE_RECV_PF_OFFLINE_REQ, - RESET_STATE_PF_OFFLINE_REQ_PROCESSING, - RESET_STATE_INVALID, -}; - - -/** - * @struct - intr_vec_map_type - * @brief interrupt vector map details - */ -struct intr_vec_map_type { - enum intr_type_list intr_type; /**< interrupt type */ - int intr_vec_index; /**< interrupt vector index */ - f_intr_handler intr_handler; /**< interrupt handler */ -}; - -/**< Interrupt info for MSI-X interrupt vectors per device */ -struct intr_info_t { - /**< msix_entry list for all vectors */ - char msix_name[QDMA_DEV_NAME_MAXLEN + 16]; - /**< queue list for each interrupt */ - struct list_head intr_list; - /**< number of queues assigned for each interrupt */ - int intr_list_cnt; - /**< interrupt vector map */ - struct intr_vec_map_type intr_vec_map; - /**< interrupt lock per vector */ - spinlock_t vec_q_list; -}; - -/** - * @struct - xlnx_dma_dev - * @brief Xilinx DMA device details - */ -struct xlnx_dma_dev { - unsigned long magic; /* structure ID for sanity checks */ - /**< Xilinx DMA device name */ - char mod_name[QDMA_DEV_NAME_MAXLEN]; - /**< Board id this device belongs to*/ - u32 dma_device_index; - /**< Keeping track of last updated descq - * Used only in case of auto and intr aggr driver mode - * This is required because HW might prematurely raise interrupt - * without actual new entries in the aggr ring and we need to - * provide some update to the sw_cidx of aggr ring so that - * interrupt gets triggered again - */ - struct qdma_descq *prev_descq; - /**< DMA device configuration */ - struct qdma_dev_conf conf; - /**< csr info */ - struct global_csr_conf csr_info; - /**< sorted c2h counter indexes */ - uint8_t sorted_c2h_cntr_idx[QDMA_GLOBAL_CSR_ARRAY_SZ]; - /**< DMA device list */ - struct list_head list_head; - /**< DMA device lock to protects concurrent access */ - spinlock_t lock; - /**< DMA device hardware program lock */ - spinlock_t hw_prg_lock; - /**< device flags */ - unsigned int flags; - /**< device capabilities */ - struct qdma_dev_attributes dev_cap; - /**< sriov info */ - void *vf_info; - /**< number of virtual functions */ - u16 vf_count; - /**< number of online virtual functions */ - u8 vf_count_online; -#ifdef __QDMA_VF__ - /** work queue */ - struct workqueue_struct *workq; - /** work_struct to pass work to reset thread */ - struct work_struct reset_work; -#endif - /** Reset state */ - enum reset_state_t reset_state; - /**< wait q for vf offline */ - qdma_wait_queue wq; - /**< function id */ - u16 func_id; -#ifdef __QDMA_VF__ - /**< parent function id, valid only for virtual function */ - u16 func_id_parent; -#else - /**< number of physical functions */ - u8 pf_count; -#endif - /**< PCIe config. bar */ - void __iomem *regs; - /**< number of MSI-X interrupt vectors per device */ - int num_vecs; - /**< msix_entry list for all MSIx vectors associated for device */ - struct msix_entry *msix; - /**< interrupt info list for all MSIx vectors associated for device */ - struct intr_info_t *dev_intr_info_list; - /**< data vector start index */ - int dvec_start_idx; - /**< DMA private device to hold the qdma que details */ - void *dev_priv; - /**< list of interrupt coalescing configuration for each vector */ - struct intr_coal_conf *intr_coal_list; - /**< legacy interrupt vector */ - int vector_legacy; - /**< error lock */ - spinlock_t err_lock; - /**< flag to indicate the error minitor status */ - u8 err_mon_cancel; - /**< error minitor work handler */ - struct delayed_work err_mon; -#ifdef DEBUGFS - /** debugfs device root */ - struct dentry *dbgfs_dev_root; - /** debugfs queue root */ - struct dentry *dbgfs_queues_root; - /** debugfs intr ring root */ - struct dentry *dbgfs_intr_root; - /* lock for creating qidx directory */ - spinlock_t qidx_lock; -#endif - - /** number of packets processed in pf */ - struct qdma_mbox mbox; - unsigned long long total_mm_h2c_pkts; - unsigned long long total_mm_c2h_pkts; - unsigned long long total_st_h2c_pkts; - unsigned long long total_st_c2h_pkts; - /** max ping_pong latency */ - u64 ping_pong_lat_max; - /** min ping_pong latency */ - u64 ping_pong_lat_min; - /** avg ping_pong latency */ - u64 ping_pong_lat_total; - /**< for upper layer calling function */ - unsigned int dev_ulf_extra[0]; - - /* qdma_hw_access structure */ - struct qdma_hw_access hw; - /* qdma_hw_version_info structure */ - struct qdma_hw_version_info version_info; -}; - -struct qdma_vf_info { - unsigned short func_id; - unsigned short qbase; - unsigned short qmax; - unsigned short filler; -}; - -/*****************************************************************************/ -/** - * xlnx_dma_device_flag_check() - helper function to check the flag status - * - * @param[in] xdev: pointer to xilinx dma device - * @param[in] f: flag value - * - * - * @return 1 if the flag is on - * @return 0 if the flag is off - *****************************************************************************/ -static inline int xlnx_dma_device_flag_check(struct xlnx_dma_dev *xdev, - unsigned int f) -{ - unsigned long flags; - - spin_lock_irqsave(&xdev->lock, flags); - if (xdev->flags & f) { - spin_unlock_irqrestore(&xdev->lock, flags); - return 1; - } - spin_unlock_irqrestore(&xdev->lock, flags); - return 0; -} - -/*****************************************************************************/ -/** - * xlnx_dma_device_flag_test_n_set() - helper function to test n set the flag - * - * @param[in] xdev: pointer to xilinx dma device - * @param[in] f: flag value - * - * - * @return 1 if the flag is already enabled - * @return 0 if the flag is off - *****************************************************************************/ -static inline int xlnx_dma_device_flag_test_n_set(struct xlnx_dma_dev *xdev, - unsigned int f) -{ - unsigned long flags; - int rv = 0; - - spin_lock_irqsave(&xdev->lock, flags); - if (xdev->flags & f) - rv = 1; - else - xdev->flags |= f; - spin_unlock_irqrestore(&xdev->lock, flags); - return rv; -} - -/*****************************************************************************/ -/** - * xdev_flag_set() - helper function to set the device flag - * - * @param[in] xdev: pointer to xilinx dma device - * @param[in] f: flag value - * - * - * @return none - *****************************************************************************/ -static inline void xdev_flag_set(struct xlnx_dma_dev *xdev, unsigned int f) -{ - unsigned long flags; - - spin_lock_irqsave(&xdev->lock, flags); - xdev->flags |= f; - spin_unlock_irqrestore(&xdev->lock, flags); -} - -/*****************************************************************************/ -/** - * xlnx_dma_device_flag_test_n_set() - helper function to clear the device flag - * - * @param[in] xdev: pointer to xilinx dma device - * @param[in] f: flag value - * - * @return none - *****************************************************************************/ -static inline void xdev_flag_clear(struct xlnx_dma_dev *xdev, unsigned int f) -{ - unsigned long flags; - - spin_lock_irqsave(&xdev->lock, flags); - xdev->flags &= ~f; - spin_unlock_irqrestore(&xdev->lock, flags); -} - -/*****************************************************************************/ -/** - * xdev_find_by_pdev() - find the xdev using struct pci_dev - * - * @param[in] pdev: pointer to struct pci_dev - * - * @return pointer to xlnx_dma_dev on success - * @return NULL on failure - *****************************************************************************/ -struct xlnx_dma_dev *xdev_find_by_pdev(struct pci_dev *pdev); - -/*****************************************************************************/ -/** - * xdev_find_by_idx() - find the xdev using the index value - * - * @param[in] idx: index value in the xdev list - * - * @return pointer to xlnx_dma_dev on success - * @return NULL on failure - *****************************************************************************/ -struct xlnx_dma_dev *xdev_find_by_idx(int idx); - -/*****************************************************************************/ -/** - * xdev_list_first() - handler to return the first xdev entry from the list - * - * @return pointer to first xlnx_dma_dev on success - * @return NULL on failure - *****************************************************************************/ -struct xlnx_dma_dev *xdev_list_first(void); - -/*****************************************************************************/ -/** - * xdev_list_next() - handler to return the next xdev entry from the list - * - * @param[in] xdev: pointer to current xdev - * - * @return pointer to next xlnx_dma_dev on success - * @return NULL on failure - *****************************************************************************/ -struct xlnx_dma_dev *xdev_list_next(struct xlnx_dma_dev *xdev); - -/*****************************************************************************/ -/** - * xdev_list_dump() - list the dma device details - * - * @param[in] buflen: length of the input buffer - * @param[out] buf: message buffer - * - * @return pointer to next xlnx_dma_dev on success - * @return NULL on failure - *****************************************************************************/ -int xdev_list_dump(char *buf, int buflen); - -/*****************************************************************************/ -/** - * xdev_check_hndl() - helper function to validate the device handle - * - * @param[in] fname: device name - * @param[in] pdev: pointer to struct pci_dev - * @param[in] hndl: device handle - * - * @return 0: success - * @return EINVAL: on failure - *****************************************************************************/ -int xdev_check_hndl(const char *fname, - struct pci_dev *pdev, unsigned long hndl); - - -#ifdef __QDMA_VF__ -/*****************************************************************************/ -/** - * xdev_sriov_vf_offline() - API to set the virtual function to offline mode - * - * @param[in] xdev: pointer to xdev - * @param[in] func_id: function identifier - * - * @return 0: success - * @return -1: on failure - *****************************************************************************/ -int xdev_sriov_vf_offline(struct xlnx_dma_dev *xdev, u16 func_id); - -/*****************************************************************************/ -/** - * xdev_sriov_vf_reset_offline() - API to set the virtual function to - * offline mode in FLR flow initiated by PF - * - * @param[in] xdev: pointer to xdev - * - * @return 0: success - * @return -1: on failure - *****************************************************************************/ -int xdev_sriov_vf_reset_offline(struct xlnx_dma_dev *xdev); - -/*****************************************************************************/ -/** - * xdev_sriov_vf_online() - API to set the virtual function to online mode - * - * @param[in] xdev: pointer to xdev - * @param[in] func_id: function identifier - * - * @return 0: success - * @return -1: on failure - *****************************************************************************/ -int xdev_sriov_vf_online(struct xlnx_dma_dev *xdev, u16 func_id); -#elif defined(CONFIG_PCI_IOV) -/* SR-IOV */ -/*****************************************************************************/ -/** - * xdev_sriov_vf_online() - API to disable the virtual function - * - * @param[in] xdev: pointer to xdev - * - * @return none - *****************************************************************************/ -void xdev_sriov_disable(struct xlnx_dma_dev *xdev); - -/*****************************************************************************/ -/** - * xdev_sriov_vf_online() - API to enable the virtual function - * - * @param[in] xdev: pointer to xdev - * @param[in] func_id: function identifier - * - * @return number of vfs enabled on success - * @return -1: on failure - *****************************************************************************/ -int xdev_sriov_enable(struct xlnx_dma_dev *xdev, int num_vfs); - -/*****************************************************************************/ -/** - * xdev_sriov_vf_offline() - API to set the virtual function to offline mode - * - * @param[in] xdev: pointer to xdev - * @param[in] func_id: function identifier - * - * @return none - *****************************************************************************/ -void xdev_sriov_vf_offline(struct xlnx_dma_dev *xdev, u16 func_id); - -/*****************************************************************************/ -/** - * xdev_sriov_vf_offline() - API to set the virtual function to offline mode - * - * @param[in] xdev: pointer to xdev - * @param[in] func_id: function identifier - * - * @return 0: success - * @return -1: on failure - *****************************************************************************/ -int xdev_sriov_vf_online(struct xlnx_dma_dev *xdev, u16 func_id); - -/*****************************************************************************/ -/** - * xdev_sriov_vf_offline() - API to configure the fmap for virtual function - * - * @param[in] xdev: pointer to xdev - * @param[in] func_id: function identifier - * @param[in] qbase: queue start - * @param[in] qmax: queue max - * - * @return 0: success - * @return -1: on failure - *****************************************************************************/ -int xdev_sriov_vf_fmap(struct xlnx_dma_dev *xdev, u16 func_id, - unsigned short qbase, unsigned short qmax); - -#define xdev_sriov_vf_reset_offline(xdev) -#else -/** dummy declaration for xdev_sriov_disable() - * When virtual function is not enabled - */ -#define xdev_sriov_disable(xdev) -/** dummy declaration for xdev_sriov_enable() - * When virtual function is not enabled - */ -#define xdev_sriov_enable(xdev, num_vfs) -/** dummy declaration for xdev_sriov_vf_offline() - * When virtual function is not enabled - */ -#define xdev_sriov_vf_offline(xdev, func_id) -/** dummy declaration for xdev_sriov_vf_online() - * When virtual function is not enabled - */ -#define xdev_sriov_vf_online(xdev, func_id) -#define xdev_sriov_vf_reset_offline(xdev) -#endif - -#endif /* XDMA_LIB_H */ diff --git a/QDMA/linux-kernel/driver/make_rules/common_flags.mk b/QDMA/linux-kernel/driver/make_rules/common_flags.mk deleted file mode 100755 index 69bebdedf..000000000 --- a/QDMA/linux-kernel/driver/make_rules/common_flags.mk +++ /dev/null @@ -1,28 +0,0 @@ -#/* -# * This file is part of the Xilinx DMA IP Core driver for Linux -# * -# * Copyright (c) 2017-2022, Xilinx, Inc. All rights reserved. -# * Copyright (c) 2022-2023, Advanced Micro Devices, Inc. All rights reserved. -# * -# * This source code is free software; you can redistribute it and/or modify it -# * under the terms and conditions of the GNU General Public License, -# * version 2, as published by the Free Software Foundation. -# * -# * This program is distributed in the hope that it will be useful, but WITHOUT -# * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -# * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for -# * more details. -# * -# * The full GNU General Public License is included in this distribution in -# * the file called "COPYING". -# */ - -#Build flags common to xdma/qdma - -ifeq ($(VF),1) - EXTRA_FLAGS += -D__QDMA_VF__ - PFVF_TYPE = -vf -else - PFVF_TYPE = -pf -endif - diff --git a/QDMA/linux-kernel/driver/make_rules/distro_check.mk b/QDMA/linux-kernel/driver/make_rules/distro_check.mk deleted file mode 100755 index 4689147d5..000000000 --- a/QDMA/linux-kernel/driver/make_rules/distro_check.mk +++ /dev/null @@ -1,132 +0,0 @@ -#/* -# * This file is part of the Xilinx DMA IP Core driver for Linux -# * -# * Copyright (c) 2017-2022, Xilinx, Inc. All rights reserved. -# * Copyright (c) 2022-2023, Advanced Micro Devices, Inc. All rights reserved. -# * -# * This source code is free software; you can redistribute it and/or modify it -# * under the terms and conditions of the GNU General Public License, -# * version 2, as published by the Free Software Foundation. -# * -# * This program is distributed in the hope that it will be useful, but WITHOUT -# * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -# * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for -# * more details. -# * -# * The full GNU General Public License is included in this distribution in -# * the file called "COPYING". -# */ - -# -# distro. checks -# uses the same variables calculated from kernel_check.mk -# - -distro := -dmajor := -dminor := - -# kernel.org rc kernels -#ifneq ($(shell echo $(kextraversion) | $(grep) -c 'git'),0) -# distro := GIT -# dmajor := -# dminor := -#endif # kernel.org - -ifneq ($(shell $(grep) -c 'RHEL' $(VERSION_H)),0) - distro := RHEL -# distro_vmajor := $(shell $(grep) 'RHEL_MAJOR' $(VERSION_H) | cut -d' ' -f3) -# distro_vminor := $(shell $(grep) 'RHEL_MINOR' $(VERSION_H) | cut -d' ' -f3) - dmajor := $(word 3, $(shell $(grep) 'RHEL_MAJOR' $(VERSION_H))) - dminor := $(word 3, $(shell $(grep) 'RHEL_MINOR' $(VERSION_H))) - ifeq ($(dmajor),) - ifeq ($(dminor),) - $(error ERROR! RHEL distro version NOT specified, check version.h.) - endif - endif - ifeq ($(shell [ $(dmajor) -lt 5 ] && echo 1),1) - $(error ERROR! Unsupported RHEL version $(dmajor).$(dminor).) - endif - ifeq ($(dmajor),5) - ifeq ($(shell [ $(dmajor) -lt 4 ] && echo 1),1) - $(error ERROR! Unsupported RHEL version $(dmajor).$(dminor).) - endif - endif -endif # RHEL - -# SLES does not provide any release macros like RHEL. So we are -# setting Makefile flags for SLES releases based on the version -# and patchlevel obtained from /etc/SuSE-release file -ifneq ($(wildcard /etc/SuSE-release),) - distro := SLES - dmajor := $(shell cat /etc/SuSE-release | grep VERSION | awk '{print $$3}') - dminor := $(shell cat /etc/SuSE-release | grep PATCHLEVEL | awk '{print $$3}') -endif - -$(info "distro=$(distro), dmajor=$(dmajor) dminor=$(dminor) ") - -# assume this is kernel.org kernels -ifeq ($(distro),) - ifeq ($(kseries),2.6) - ifeq ($(shell [ $(ksublevel) -ge 32 ] && echo 1),1) - distro := GIT - else - $(error kernel version $(kbaseversion)$(kextraversion) NOT supported.) - $( kernel.org Requires >= 2.6.32.) - endif - endif - - ifeq ($(kversion),3) - ifeq ($(shell [ $(kpatchlevel) -ge 1 ] && echo 1),1) - distro := GIT - else - $(error kernel version $(kbaseversion)$(kextraversion) NOT supported.) - $( kernel.org Requires >= 3.1.) - endif - endif - - ifeq ($(kversion),4) - distro := GIT - endif - - ifeq ($(kversion),5) - distro := GIT - endif - - ifeq ($(kversion),6) - distro := GIT - endif -endif # assume kernel.org kernels - -ifeq ($(distro),) - $(error kernel version $(kbaseversion)$(kextraversion) NOT supported.) - $( kernel.org Requires >= 2.6.35.) -endif - -FLAGS += -D$(distro)$(dmajor)SP$(dminor) -FLAGS += -D$(distro)$(dmajor) -# special case for SLES 11 -ifeq ($(distro),SLES) - ifeq ($(dmajor),11) - ifeq ($(shell test $(dminor) -ge 1; echo $$?),0) - FLAGS += -DSLES_RELEASE_11_1 - endif - ifeq ($(shell test $(dminor) -ge 2; echo $$?),0) - FLAGS += -DSLES_RELEASE_11_2 - endif - ifeq ($(shell test $(dminor) -ge 3; echo $$?),0) - FLAGS += -DSLES_RELEASE_11_3 - endif - ifeq ($(shell test $(dminor) -ge 4; echo $$?),0) - FLAGS += -DSLES_RELEASE_11_4 - endif - else - FLAGS += -D$(distro)_RELEASE_$(dmajor)_$(dminor) - endif -endif - -$(info $(kbaseversion)$(kextraversion): $(distro),$(dmajor),$(dminor), $(FLAGS)) - -export distro -export dmajor -export dminor diff --git a/QDMA/linux-kernel/driver/make_rules/kernel_check.mk b/QDMA/linux-kernel/driver/make_rules/kernel_check.mk deleted file mode 100755 index ab2b36982..000000000 --- a/QDMA/linux-kernel/driver/make_rules/kernel_check.mk +++ /dev/null @@ -1,351 +0,0 @@ -#/* -# * This file is part of the Xilinx DMA IP Core driver for Linux -# * -# * Copyright (c) 2017-2022, Xilinx, Inc. All rights reserved. -# * Copyright (c) 2022-2023, Advanced Micro Devices, Inc. All rights reserved. -# * -# * This source code is free software; you can redistribute it and/or modify it -# * under the terms and conditions of the GNU General Public License, -# * version 2, as published by the Free Software Foundation. -# * -# * This program is distributed in the hope that it will be useful, but WITHOUT -# * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -# * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for -# * more details. -# * -# * The full GNU General Public License is included in this distribution in -# * the file called "COPYING". -# */ - -# Kernel directories. -KERNELRELEASE := $(shell uname -r) - -# If KSRC= is specified on the command line, KOBJ= must -# also be specified. This is to avoid mixups if the kernel object path -# differs from the source path. A shortcut (KSRC=KOBJ) is to use KDIR. -ifeq ($(KDIR),) - ifeq ($(KSRC),) - ifneq ($(KOBJ),) - $(warning When using KOBJ=, the KSRC= must also be defined.) - $(warning Use KDIR= when KSRC and KOBJ are the same.) - $(error ERROR: kernel source path not specified) - endif - else - ifeq ($(KOBJ),) - $(warning When using KSRC=, the KOBJ= must also be defined.) - $(warning Use KDIR= when KSRC and KOBJ are the same.) - $(error ERROR: KOBJ path not specified) - endif - endif -else - override KSRC := $(KDIR) - override KOBJ := $(KDIR) -endif - -# Only if KSRC/KOBJ were not defined on the command line. -KSRC ?= $(wildcard /lib/modules/$(KERNELRELEASE)/source) -KOBJ ?= $(wildcard /lib/modules/$(KERNELRELEASE)/build) -KINC = $(KSRC)/include - -#$(warning KDIR: $(KDIR).) - -ifeq ($(KSRC),) - KSRC = $(KOBJ) -endif - -# Define kernel files. -VERSION_H := $(KOBJ)/include/linux/version.h -AUTOCONF_H := $(KOBJ)/include/generated/autoconf.h -UTSRELEASE_H := $(KOBJ)/include/generated/utsrelease.h - -ifeq ($(wildcard $(VERSION_H)),) - VERSION_H := $(KOBJ)/include/generated/uapi/linux/version.h -endif -ifeq ($(wildcard $(AUTOCONF_H)),) - AUTOCONF_H := $(KOBJ)/include/linux/autoconf.h -endif -ifeq ($(wildcard $(UTSRELEASE_H)),) - UTSRELEASE_H := $(KOBJ)/include/linux/utsrelease.h -endif -#ifeq ($(wildcard $(UTSRELEASE_H)),) -# $(error NO utsrelease) -#endif - -# Define architecture and target(for RPM). -ARCH := $(shell uname -m) -target := $(ARCH) -override ARCH := $(shell echo $(ARCH) | sed 's/i.86/i386/') -ifeq ($(USER_ARCH),) - - ifeq ($(ARCH),ppc64le) - ifeq ($(wildcard $(KOBJ)/arch/$(ARCH)),) - override ARCH := powerpc - endif - endif - - ifeq ($(ARCH),ppc64) - # Check if the kernel wants ppc64 or powerpc. - ifeq ($(wildcard $(KOBJ)/arch/$(ARCH)),) - override ARCH := powerpc - endif - endif -else - # Honor the value of ARCH if specified by user. - override ARCH := $(USER_ARCH) -endif - -# Functions. -define path_check -$(if $(wildcard $(1)),$(1),) -endef -define reverse_sort -$(shell echo -e `echo "$(strip $(1))" |\ - sed 's/[[:space:]]/\\\n/g'` | sort -r) -endef -define version_code -$(shell let x=`sed '/^\#define[[:space:]]*LINUX_VERSION_CODE/!d;\ - s/.*LINUX_VERSION_CODE[[:space:]]*//' < $(1)\ - 2>/dev/null`;\ - let a="$$x >> 16";\ - let x="$$x - ($$a << 16)";\ - let b="$$x >> 8";\ - let x="$$x - ($$b << 8)";\ - echo "$$a $$b $$x") -endef - -# Checks for kernel source and object directories. -ifeq ($(call path_check,$(KSRC)),) - $(warning Be sure the kernel source is properly installed or \ - try specifying the kernel source tree using 'make KSRC=') - $(error ERROR: missing kernel source) -endif -ifeq ($(call path_check,$(KOBJ)),) - $(warning Try specifying the kernel build tree using 'make KOBJ='.) - $(error ERROR: missing kernel build) -endif - -# Check kernel source and build directories are somewhat likely to be correct. -ifneq ($(notdir $(wildcard $(KSRC)/Makefile)),Makefile) - $(warning There seems to be a problem with the kernel \ - source [$(KSRC)] directory.) - $(error ERROR: missing kernel Makefile) -endif -ifneq ($(notdir $(wildcard $(KOBJ)/Makefile)),Makefile) - $(warning There seems to be a problem with the kernel \ - build [$(KOBJ)] directory.) - $(error ERROR: missing kernel Makefile) -endif - -# Get kernel version code info. -KERNELVERSION := $(strip $(call version_code,$(VERSION_H))) -ifneq ($(words $(KERNELVERSION)), 3) - $(error ERROR: unexpected kernel version \ - '$(shell echo $(KERNELVERSION) | sed 's/[[:space:]]/./g')') -endif - -# Define kernel version details. -kversion := $(word 1, $(KERNELVERSION)) -kpatchlevel := $(word 2, $(KERNELVERSION)) -ksublevel := $(word 3, $(KERNELVERSION)) - -# The kernel base version, excluding the EXTRAVERSION string. -kbaseversion := $(kversion).$(kpatchlevel).$(ksublevel) - -# The kernel series version. -kseries := $(kversion).$(kpatchlevel) - -# Fix for variation of Module.symvers naming (thanks 2.6.17!). -# I need to know the file name of the module symver generated by the kernel -# during an external module build (MODPOST). Also used for kernels that don't -# automatically generate the module symver file during MODPOST (2.6.0-2.6.17?). -ifeq ($(shell $(grep) -c '^modulesymfile[[:space:]]*:\?=' \ - $(KSRC)/scripts/Makefile.modpost),1) - modulesymfile := $(shell $(grep) '^modulesymfile[[:space:]]*:\?=' \ - $(KSRC)/scripts/Makefile.modpost) - kernelsymfile := $(shell $(grep) '^kernelsymfile[[:space:]]*:\?=' \ - $(KSRC)/scripts/Makefile.modpost) -else - ifeq ($(shell $(grep) -c '^symverfile[[:space:]]*:\?=' \ - $(KSRC)/scripts/Makefile.modpost),1) - symverfile := $(shell $(grep) '^symverfile[[:space:]]*:\?=' \ - $(KSRC)/scripts/Makefile.modpost) - kernelsymfile := $(subst symverfile,kernelsymfile,$(symverfile)) - endif -endif -modulesymfile ?= $(symverfile) -ifeq ($(modulesymfile),) - $(warning The parsing of $(KSRC)/scripts/Makefile.modpost \ - is not making sense.) - $(error ERROR cannot determine module symvers file) -endif - -# Gnu make (3.80) bug #1516, $(eval ...) inside conditionals causes errors. -# This is fixed in v3.81 and some v3.80 (RHEL4/5) but not on SLES10. -# Workaround: include a separate makefile that does the eval. -ifeq ($(shell echo '$(modulesymfile)' | $(grep) -c '^[[:alnum:]_]\+[[:space:]]*:\?=[[:space:]]*.\+'),1) - $(shell echo '$$(eval $$(modulesymfile))' > eval.mak) - include eval.mak -else - modulesymfile = -endif -ifeq ($(shell echo '$(kernelsymfile)' | $(grep) -c '^[[:alnum:]_]\+[[:space:]]*:\?=[[:space:]]*.\+'),1) - $(shell echo '$$(eval $$(kernelsymfile))' > eval.mak) - include eval.mak -else - kernelsymfile = -endif -modulesymfile := $(notdir $(modulesymfile)) -kernelsymfile := $(notdir $(kernelsymfile)) -$(shell [ -f eval.mak ] && /bin/rm -f eval.mak) - -ifneq ($(words $(modulesymfile)),1) - $(warning The parsing of $(KSRC)/scripts/Makefile.modpost \ - is not making sense.) - $(warning You can try passing 'modulesymfile=Module.symvers' or \ - similar to make.) - $(error ERROR cannot determine module symvers file) -endif - - -# Check for configured kernel. -ifeq ($(wildcard $(AUTOCONF_H)),) - $(warning The kernel is not properly configured, try running \ - 'make menuconfig' on your kernel.) - $(error ERROR: kernel missing autoconf.h) -endif -# Check for built kernel. -ifeq ($(wildcard $(VERSION_H)),) - $(warning The kernel has not been compiled. Try building your kernel \ - before building this driver.) - $(error ERROR: kernel missing version.h) -endif - -# Check that kernel supports modules. -ifneq ($(shell $(grep) -c '^\#define[[:space:]]\+CONFIG_MODULES[[:space:]]\+1' $(AUTOCONF_H)),1) - $(warning The kernel has not been configured for module support.) - $(warning Try configuring the kernel to allow external modules and \ - recompile.) - $(error ERROR: kernel CONFIG_MODULES not defined) -endif - -# Get kernel UTS_RELEASE info. -ifneq ($(wildcard $(UTSRELEASE_H)),) - ifneq ($(shell $(grep) -c '^\#define[[:space:]]\+UTS_RELEASE' \ - $(UTSRELEASE_H)),0) - utsrelease := $(UTSRELEASE_H) - endif -else - ifneq ($(wildcard $(KOBJ)/include/linux/version.h),) - ifneq ($(shell $(grep) -c '^\#define[[:space:]]\+UTS_RELEASE' \ - $(KOBJ)/include/linux/version.h),0) - utsrelease := $(KOBJ)/include/linux/version.h - endif - endif -endif -ifeq ($(utsrelease),) - $(error ERROR: cannot locate kernel UTS_RELEASE) -endif -# Getting the UTS_RELEASE on RHEL3 had problems due to the multiple defines -# within the file. I can run this file through the C pre-processor and get -# the actual UTS_RELEASE definition. This has only been tested on gcc, other -# compilers may not work. -utsrelease := $(strip $(shell $(CC) -E -dM -I $(KSRC)/include $(utsrelease) \ - 2>/dev/null| sed '/^\#define[[:space:]]*UTS_RELEASE/!d;\ - s/^\#define UTS_RELEASE[[:space:]]*"//;\ - s/"//g')) - -# The kernel local version string if defined in config. -klocalversion := $(shell sed '/^CONFIG_LOCALVERSION=/!d;\ - s/^CONFIG_LOCALVERSION="//;s/"//g'\ - 2>/dev/null < $(KOBJ)/.config) -# The complete kernel EXTRAVERSION string. -kextraversion := $(subst $(kbaseversion),,$(utsrelease)) -# The full kernel version should be the same as uts_release. -kernelversion := $(utsrelease) - -# The kernel EXTRAVERSION creates a unique problem, especially since -# kernel versioning extended into the EXTRAVERSION and distributions -# add strings such as smp, largesmp, xen, etc or when additional minor -# version numbers are appended. -# Some code that we supply is dependent on the kernel version and -# parts of the EXTRAVERSION, but not dependent on some of the additional -# flags. This requires that I have a list of kernel version strings that -# could map to the source version we require. For example, if the -# kernel version is 2.6.9-67.ELsmp, we only care about the "2.6.9-67" -# part, therefore, I need to split the EXTRAVERSION accordingly. -# Another problem is when a user builds their own kernel, say 2.6.21.4 -# and adds an additional string to EXTRAVERSION. The EXTRAVERSION is -# now ".4-custom" and I have to parse this with hopes of extracting -# only the ".4" part, resulting in the needed "2.6.21.4" version. -# Adding a BUGFIX version (int) field would be very helpfull! - -# EXTRAVERSION as defined only in the Makefile. -extraversion1 := $(strip $(shell sed '/^EXTRAVERSION/!d;\ - s/^EXTRAVERSION[[:space:]]*=//;s/"//g'\ - < $(KSRC)/Makefile 2>/dev/null)) -# SLES9 likes to put make code in their EXTRAVERSION define. Let the -# variables expand out to nothing, because the code will cause problems. -extraversion1 := $(shell echo $(extraversion1)) -# EXTRAVERSION without local version. -extraversion2 := $(strip $(subst $(klocalversion),,$(kextraversion))) -# EXTRAVERSION with only the kernel .version (hopefully). -extraversion3 := $(strip $(shell echo $(kextraversion) |\ - sed 's/\(^\.[0-9]*\).*/\1/')) -# EXTRAVERSION without the Redhat EL tag. -extraversion4 := $(strip $(shell echo $(kextraversion) |\ - sed 's/\.EL.*//i')) -# EXTRAVERSION with the Redhat EL tag, but nothing else after. -extraversion5 := $(strip $(shell echo $(kextraversion) |\ - sed 's/\(\.EL\).*/\1/i')) -# EXTRAVERSION with the Redhat EL tag, including a number (el5). -extraversion6 := $(strip $(shell echo $(kextraversion) |\ - sed 's/\(\.EL[[:digit:]]*\).*/\1/i')) -# EXTRAVERSION without the Redhat hotfix/update kernel version number. -extraversion7 := $(strip $(shell echo $(kextraversion) |\ - sed 's/\(.*\-[[:digit:]]*\)\..*\(\.EL\).*/\1\2/i')) -# EXTRAVERSION without the Redhat hotfix/update kernel version number with Redhat EL tag, including the number (el5). -extraversion8 := $(strip $(shell echo $(kextraversion) |\ - sed 's/\(.*\-[[:digit:]]*\)\..*\(\.EL[[:digit:]]\).*/\1\2/i')) -# EXTRAVERSION with only the RHEL distro version -extraversion9 := $(strip $(shell echo $(kextraversion) |\ - sed 's/\(.*\-[[:digit:]]*\)\..*\.EL[[:digit:]].*/\1/i')) - -# All known EXTRAVERSION strings, duplicates removed. -extraversions := $(strip $(sort $(kextraversion) \ - $(extraversion1) \ - $(extraversion2) \ - $(extraversion3) \ - $(extraversion4) \ - $(extraversion5) \ - $(extraversion6) \ - $(extraversion7) \ - $(extraversion8) \ - $(extraversion9))) - -# List of all possible kernel version names for target kernel. -all_kernels := $(sort $(kbaseversion) \ - $(foreach a,$(extraversions),$(kbaseversion)$(a))) - -# A reverse ordered list. This is used primarily to search source code -# directory names to match the target kernel version. -kversions := $(call reverse_sort, $(all_kernels)) - -# Special cases for 2.4 series kernels. -ifeq ($(kseries),2.4) - $(error ERROR: 2.4 kernel NOT supported.) -endif -# Note: Define only FLAGS here. These will convert to CFLAGS in the sub-make. -# If the environment variable FLAGS is defined with make, things will break, -# use CFLAGS instead. -# General compiler flags. -# Kernel version 3.3+ moved include/asm to include/generated, which breaks -# outbox kernel drivers. Fix to include the new generated without code change. -ifeq ($(kversion),3) - ifeq ($(shell [ $(kpatchlevel) -gt 2 ] && echo 1),1) - override CARCH := $(ARCH) - ifeq ($(CARCH),x86_64) - override CARCH := x86 - endif - FLAGS += -I$(KSRC)/arch/$(CARCH)/include/generated - endif -endif diff --git a/QDMA/linux-kernel/driver/src/Makefile b/QDMA/linux-kernel/driver/src/Makefile deleted file mode 100755 index 1b5b9bd07..000000000 --- a/QDMA/linux-kernel/driver/src/Makefile +++ /dev/null @@ -1,147 +0,0 @@ -#/* -# * This file is part of the Xilinx DMA IP Core driver for Linux -# * -# * Copyright (c) 2017-2022, Xilinx, Inc. All rights reserved. -# * Copyright (c) 2022-2023, Advanced Micro Devices, Inc. All rights reserved. -# * -# * This source code is free software; you can redistribute it and/or modify it -# * under the terms and conditions of the GNU General Public License, -# * version 2, as published by the Free Software Foundation. -# * -# * This program is distributed in the hope that it will be useful, but WITHOUT -# * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -# * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for -# * more details. -# * -# * The full GNU General Public License is included in this distribution in -# * the file called "COPYING". -# */ - -SHELL = /bin/bash - -export topdir -export bin_dir - -# The top-level makefile defines required variables and flags. -ifneq ($(shell [[ $(MAKELEVEL) -ge 1 ]] && echo 1),1) - $(error Please use the top-level Makefile to build this driver) -endif - -ifneq ($(wildcard /etc/lsb-release),) - ifneq ($(shell $(grep) "Ubuntu" /etc/lsb-release),) - FLAGS += -DUBUNTU_VERSION_CODE - endif -endif - -include $(srcdir)/../make_rules/common_flags.mk - -$(info srcdir = $(srcdir).) -$(info KSRC = $(KSRC).) -$(info VF = $(VF).) -$(info CROSS_COMPILE_FLAG = $(CROSS_COMPILE_FLAG).) -$(info ARCH = $(ARCH).) - - -MOD_NAME := qdma$(PFVF_TYPE) - -EXTRA_CFLAGS += -DLINUX -D__KERNEL__ -DMODULE -O2 -pipe -Wall -Werror -EXTRA_CFLAGS += $(FLAGS) $(CPPFLAGS) $(EXTRA_FLAGS) -EXTRA_CFLAGS += -I$(srcdir)/../include -EXTRA_CFLAGS += -I$(KSRC)/../include -EXTRA_CFLAGS += -I$(srcdir)/../libqdma/qdma_access/qdma_soft_access -EXTRA_CFLAGS += -I$(srcdir)/../libqdma/qdma_access/eqdma_soft_access -EXTRA_CFLAGS += -I$(srcdir)/../libqdma/qdma_access/eqdma_cpm5_access -EXTRA_CFLAGS += -I$(srcdir)/../libqdma/qdma_access/qdma_cpm4_access -EXTRA_CFLAGS += -I. - -# linux >= 3.13 genl_ops become part of the genl_family. And although -# genl_register_family_with_ops() is still retained until kernel 4.10, -# its prototype changed from a extern function to a define. -# -ifneq ($(shell $(grep) -c 'int genl_register_family_with_ops' $(KINC)/net/genetlink.h),0) - ccflags-y += -D__GENL_REG_FAMILY_OPS_FUNC__ -endif - -# linux <= 3.13 pci_msix_vec_count is not defined. -# -ifeq ($(shell $(grep) -c 'int pci_msix_vec_count' $(KINC)/linux/pci.h),0) - ccflags-y += -D__PCI_MSI_VEC_COUNT__ -endif - -# linux < 3.13 list_next_entry is not defined. -# -ifeq ($(shell $(grep) -c 'list_next_entry' $(KINC)/linux/list.h),0) - ccflags-y += -D__LIST_NEXT_ENTRY__ -endif - -# linux < 3.18.13 READ_ONCE is not defined. -# -ifneq ($(shell $(grep) -c 'READ_ONCE' $(KINC)/linux/compiler.h),0) - ccflags-y += -D__READ_ONCE_DEFINED__ -endif - -$(info EXTRA_FLAGS = $(EXTRA_FLAGS).) -$(info ccflags-y = $(ccflags-y).) -#EXTRA_CFLAGS += -DDEBUG - -#For Kernel Images > 4.9.199 with CONFIG_STACK_VALIDATION=y and GCC version > 8 compiler throws spurious warnings -#related to sibling calls and frame pointer save/setup. To supress these warnings -#enable the OBJECT_FILES_NON_STANDARD option below -#If in case, the flag name changes in future linux kernel releases, please refer -#https://github.com/torvalds/linux/blob/master/tools/objtool/Documentation/stack-validation.txt -#to get the correct flag name -#OBJECT_FILES_NON_STANDARD := y - -ifneq ($(modulesymfile),) - override symverfile = symverfile="$(topdir)/$(modulesymfile) \ - -o $(drvdir)/$(modulesymfile)" -else - override symverfile = -endif - -DRV_OBJS := nl.o cdev.o qdma_mod.o - -LIBQDMA_OBJS := libqdma/qdma_mbox.o libqdma/qdma_intr.o libqdma/qdma_st_c2h.o \ - libqdma/qdma_thread.o libqdma/libqdma_export.o libqdma/qdma_context.o \ - libqdma/qdma_sriov.o libqdma/qdma_platform.o libqdma/qdma_descq.o libqdma/qdma_regs.o \ - libqdma/qdma_debugfs.o libqdma/qdma_debugfs_dev.o libqdma/qdma_debugfs_queue.o \ - libqdma/libqdma_config.o libqdma/qdma_device.o libqdma/xdev.o libqdma/thread.o - -QDMA_ACCESS_OBJS := libqdma/qdma_access/qdma_mbox_protocol.o libqdma/qdma_access/qdma_list.o \ - libqdma/qdma_access/qdma_access_common.o libqdma/qdma_access/qdma_resource_mgmt.o \ - libqdma/qdma_access/qdma_cpm4_access/qdma_cpm4_access.o \ - libqdma/qdma_access/qdma_cpm4_access/qdma_cpm4_reg_dump.o \ - libqdma/qdma_access/qdma_soft_access/qdma_soft_access.o \ - libqdma/qdma_access/eqdma_soft_access/eqdma_soft_access.o \ - libqdma/qdma_access/eqdma_soft_access/eqdma_soft_reg_dump.o \ - libqdma/qdma_access/eqdma_cpm5_access/eqdma_cpm5_access.o \ - libqdma/qdma_access/eqdma_cpm5_access/eqdma_cpm5_reg_dump.o - - - -obj-m += $(MOD_NAME).o -$(MOD_NAME)-objs += $(DRV_OBJS) -$(MOD_NAME)-objs += $(LIBQDMA_OBJS) -$(MOD_NAME)-objs += $(QDMA_ACCESS_OBJS) - -ifeq ($(ARCH),aarch64) - ARCH=arm64 -endif - -.PHONY: bin -bin: - @mkdir -p -m 755 $(bin_dir) - @rm -f $(MOD_NAME).ko $(bin_dir)/$(MOD_NAME).ko -ifeq ($(CROSS_COMPILE_FLAG),) - @$(MAKE) symverfile=$(symverfile) KBUILD_EXTRA_SYMBOLS=$(extra_symb) -C $(KOBJ) M=$(shell pwd) modules -else - @$(MAKE) symverfile=$(symverfile) KBUILD_EXTRA_SYMBOLS=$(extra_symb) -C $(KOBJ) CROSS_COMPILE=$(CROSS_COMPILE_FLAG) SUBDIRS=$(shell pwd) modules -endif - @cp $(MOD_NAME).ko $(bin_dir) - -.PHONY: clean -clean: - @-/bin/rm -rf *.ko* ?odule* .tmp_versions *.mod.* *.o *.o.* .*.o.* .*.cmd - @-/bin/rm -rf */*.o */*.o.* */.*.o.* */.*.cmd - @-/bin/rm -rf $(bin_dir)/*.ko - @-/bin/rm -f $(srcdir)/drv/libqdma diff --git a/QDMA/linux-kernel/driver/src/cdev.c b/QDMA/linux-kernel/driver/src/cdev.c deleted file mode 100755 index bd7d68128..000000000 --- a/QDMA/linux-kernel/driver/src/cdev.c +++ /dev/null @@ -1,819 +0,0 @@ -/* - * This file is part of the Xilinx DMA IP Core driver for Linux - * - * Copyright (c) 2017-2022, Xilinx, Inc. All rights reserved. - * Copyright (c) 2022-2023, Advanced Micro Devices, Inc. All rights reserved. - * - * This source code is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * The full GNU General Public License is included in this distribution in - * the file called "COPYING". - */ - -#define pr_fmt(fmt) KBUILD_MODNAME ":%s: " fmt, __func__ - -#include "cdev.h" - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#if KERNEL_VERSION(3, 16, 0) <= LINUX_VERSION_CODE -#include -#endif - -#include "qdma_mod.h" -#include "libqdma/xdev.h" - -/* - * @struct - xlnx_phy_dev - * @brief xilinx board device data members - */ -struct xlnx_phy_dev { - struct list_head list_head; /**< board list */ - unsigned int major; /**< major number per board */ - unsigned int device_bus; /**< PCIe device bus number per board */ - unsigned int dma_device_index; -}; - -static LIST_HEAD(xlnx_phy_dev_list); -static DEFINE_MUTEX(xlnx_phy_dev_mutex); - -struct cdev_async_io { - ssize_t res2; - unsigned long req_count; - unsigned long cmpl_count; - unsigned long err_cnt; - struct qdma_io_cb *qiocb; - struct qdma_request **reqv; - struct kiocb *iocb; - struct work_struct wrk_itm; -}; - -enum qdma_cdev_ioctl_cmd { - QDMA_CDEV_IOCTL_NO_MEMCPY, - QDMA_CDEV_IOCTL_CMDS -}; - -static struct class *qdma_class; -static struct kmem_cache *cdev_cache; - -static ssize_t cdev_gen_read_write(struct file *file, char __user *buf, - size_t count, loff_t *pos, bool write); -static void unmap_user_buf(struct qdma_io_cb *iocb, bool write); -static inline void iocb_release(struct qdma_io_cb *iocb); - -static inline void xlnx_phy_dev_list_remove(struct xlnx_phy_dev *phy_dev) -{ - if (!phy_dev) - return; - - mutex_lock(&xlnx_phy_dev_mutex); - list_del(&phy_dev->list_head); - mutex_unlock(&xlnx_phy_dev_mutex); -} - -static inline void xlnx_phy_dev_list_add(struct xlnx_phy_dev *phy_dev) -{ - if (!phy_dev) - return; - - mutex_lock(&xlnx_phy_dev_mutex); - list_add_tail(&phy_dev->list_head, &xlnx_phy_dev_list); - mutex_unlock(&xlnx_phy_dev_mutex); -} - -static int qdma_req_completed(struct qdma_request *req, - unsigned int bytes_done, int err) -{ - struct qdma_io_cb *qiocb = container_of(req, - struct qdma_io_cb, - req); - struct cdev_async_io *caio = NULL; - bool free_caio = false; - ssize_t res, res2; - - - if (qiocb) { - caio = (struct cdev_async_io *)qiocb->private; - } else { - pr_err("Invalid Data structure. Probable memory corruption"); - return -EINVAL; - } - - if (!caio) { - pr_err("Invalid Data structure. Probable memory corruption"); - return -EINVAL; - } - - unmap_user_buf(qiocb, req->write); - iocb_release(qiocb); - caio->res2 |= (err < 0) ? err : 0; - if (caio->res2) - caio->err_cnt++; - caio->cmpl_count++; - if (caio->cmpl_count == caio->req_count) { - res = caio->cmpl_count - caio->err_cnt; - res2 = caio->res2; -#ifdef RHEL_RELEASE_VERSION -#if RHEL_RELEASE_VERSION(9, 0) < RHEL_RELEASE_CODE - caio->iocb->ki_complete(caio->iocb, res); -#elif RHEL_RELEASE_VERSION(8, 0) < RHEL_RELEASE_CODE - caio->iocb->ki_complete(caio->iocb, res, res2); -#else - aio_complete(caio->iocb, res, res2); -#endif -#else -#if KERNEL_VERSION(5, 16, 0) <= LINUX_VERSION_CODE - caio->iocb->ki_complete(caio->iocb, res); -#elif KERNEL_VERSION(4, 1, 0) <= LINUX_VERSION_CODE - caio->iocb->ki_complete(caio->iocb, res, res2); -#else - aio_complete(caio->iocb, res, res2); -#endif -#endif - kfree(caio->qiocb); - free_caio = true; - } - if (free_caio) - kmem_cache_free(cdev_cache, caio); - - return 0; -} - -/* - * character device file operations - */ -static int cdev_gen_open(struct inode *inode, struct file *file) -{ - struct qdma_cdev *xcdev = container_of(inode->i_cdev, struct qdma_cdev, - cdev); - file->private_data = xcdev; - - if (xcdev->fp_open_extra) - return xcdev->fp_open_extra(xcdev); - - return 0; -} - -static int cdev_gen_close(struct inode *inode, struct file *file) -{ - struct qdma_cdev *xcdev = (struct qdma_cdev *)file->private_data; - - if (xcdev && xcdev->fp_close_extra) - return xcdev->fp_close_extra(xcdev); - - return 0; -} - -static loff_t cdev_gen_llseek(struct file *file, loff_t off, int whence) -{ - struct qdma_cdev *xcdev = (struct qdma_cdev *)file->private_data; - - loff_t newpos = 0; - - switch (whence) { - case 0: /* SEEK_SET */ - newpos = off; - break; - case 1: /* SEEK_CUR */ - newpos = file->f_pos + off; - break; - case 2: /* SEEK_END, @TODO should work from end of address space */ - newpos = UINT_MAX + off; - break; - default: /* can't happen */ - return -EINVAL; - } - if (newpos < 0) - return -EINVAL; - file->f_pos = newpos; - - pr_debug("%s: pos=%lld\n", xcdev->name, (signed long long)newpos); - - return newpos; -} - -static long cdev_gen_ioctl(struct file *file, unsigned int cmd, - unsigned long arg) -{ - struct qdma_cdev *xcdev = (struct qdma_cdev *)file->private_data; - - switch (cmd) { - case QDMA_CDEV_IOCTL_NO_MEMCPY: - get_user(xcdev->no_memcpy, (unsigned char *)arg); - return 0; - default: - break; - } - if (xcdev->fp_ioctl_extra) - return xcdev->fp_ioctl_extra(xcdev, cmd, arg); - - pr_err("%s ioctl NOT supported.\n", xcdev->name); - return -EINVAL; -} - -/* - * cdev r/w - */ -static inline void iocb_release(struct qdma_io_cb *iocb) -{ - if (iocb->pages) - iocb->pages = NULL; - kfree(iocb->sgl); - iocb->sgl = NULL; - iocb->buf = NULL; -} - -static void unmap_user_buf(struct qdma_io_cb *iocb, bool write) -{ - int i; - - if (!iocb->pages || !iocb->pages_nr) - return; - - for (i = 0; i < iocb->pages_nr; i++) { - if (iocb->pages[i]) { - if (!write) - set_page_dirty(iocb->pages[i]); - put_page(iocb->pages[i]); - } else - break; - } - - if (i != iocb->pages_nr) - pr_err("sgl pages %d/%u.\n", i, iocb->pages_nr); - - iocb->pages_nr = 0; -} - -static int map_user_buf_to_sgl(struct qdma_io_cb *iocb, bool write) -{ - unsigned long len = iocb->len; - char *buf = iocb->buf; - struct qdma_sw_sg *sg; - unsigned int pg_off = offset_in_page(buf); - unsigned int pages_nr = (len + pg_off + PAGE_SIZE - 1) >> PAGE_SHIFT; - int i; - int rv; - - if (len == 0) - pages_nr = 1; - if (pages_nr == 0) - return -EINVAL; - - iocb->pages_nr = 0; - sg = kmalloc(pages_nr * (sizeof(struct qdma_sw_sg) + - sizeof(struct page *)), GFP_KERNEL); - if (!sg) { - pr_err("sgl allocation failed for %u pages", pages_nr); - return -ENOMEM; - } - memset(sg, 0, pages_nr * (sizeof(struct qdma_sw_sg) + - sizeof(struct page *))); - iocb->sgl = sg; - - iocb->pages = (struct page **)(sg + pages_nr); - rv = get_user_pages_fast((unsigned long)buf, pages_nr, 1/* write */, - iocb->pages); - /* No pages were pinned */ - if (rv < 0) { - pr_err("unable to pin down %u user pages, %d.\n", - pages_nr, rv); - goto err_out; - } - /* Less pages pinned than wanted */ - if (rv != pages_nr) { - pr_err("unable to pin down all %u user pages, %d.\n", - pages_nr, rv); - iocb->pages_nr = rv; - rv = -EFAULT; - goto err_out; - } - - for (i = 1; i < pages_nr; i++) { - if (iocb->pages[i - 1] == iocb->pages[i]) { - pr_err("duplicate pages, %d, %d.\n", - i - 1, i); - iocb->pages_nr = pages_nr; - rv = -EFAULT; - goto err_out; - } - } - - sg = iocb->sgl; - for (i = 0; i < pages_nr; i++, sg++) { - unsigned int offset = offset_in_page(buf); - unsigned int nbytes = min_t(unsigned int, PAGE_SIZE - offset, - len); - struct page *pg = iocb->pages[i]; - - flush_dcache_page(pg); - - sg->next = sg + 1; - sg->pg = pg; - sg->offset = offset; - sg->len = nbytes; - sg->dma_addr = 0UL; - - buf += nbytes; - len -= nbytes; - } - - iocb->sgl[pages_nr - 1].next = NULL; - iocb->pages_nr = pages_nr; - return 0; - -err_out: - unmap_user_buf(iocb, write); - iocb_release(iocb); - - return rv; -} - -static ssize_t cdev_gen_read_write(struct file *file, char __user *buf, - size_t count, loff_t *pos, bool write) -{ - struct qdma_cdev *xcdev = (struct qdma_cdev *)file->private_data; - struct qdma_io_cb iocb; - struct qdma_request *req = &iocb.req; - ssize_t res = 0; - int rv; - unsigned long qhndl; - - if (!xcdev) { - pr_err("file 0x%p, xcdev NULL, 0x%p,%llu, pos %llu, W %d.\n", - file, buf, (u64)count, (u64)*pos, write); - return -EINVAL; - } - - if (!xcdev->fp_rw) { - pr_err("file 0x%p, %s, NO rw, 0x%p,%llu, pos %llu, W %d.\n", - file, xcdev->name, buf, (u64)count, (u64)*pos, write); - return -EINVAL; - } - - qhndl = write ? xcdev->h2c_qhndl : xcdev->c2h_qhndl; - - pr_debug("%s, priv 0x%lx: buf 0x%p,%llu, pos %llu, W %d.\n", - xcdev->name, qhndl, buf, (u64)count, (u64)*pos, - write); - - memset(&iocb, 0, sizeof(struct qdma_io_cb)); - iocb.buf = buf; - iocb.len = count; - rv = map_user_buf_to_sgl(&iocb, write); - if (rv < 0) - return rv; - - req->sgcnt = iocb.pages_nr; - req->sgl = iocb.sgl; - req->write = write ? 1 : 0; - req->dma_mapped = 0; - req->udd_len = 0; - req->ep_addr = (u64)*pos; - req->count = count; - req->timeout_ms = 10 * 1000; /* 10 seconds */ - req->fp_done = NULL; /* blocking */ - req->h2c_eot = 1; /* set to 1 for STM tests */ - - res = xcdev->fp_rw(xcdev->xcb->xpdev->dev_hndl, qhndl, req); - - unmap_user_buf(&iocb, write); - iocb_release(&iocb); - - return res; -} - -static ssize_t cdev_gen_write(struct file *file, const char __user *buf, - size_t count, loff_t *pos) -{ - return cdev_gen_read_write(file, (char *)buf, count, pos, 1); -} - -static ssize_t cdev_gen_read(struct file *file, char __user *buf, - size_t count, loff_t *pos) -{ - return cdev_gen_read_write(file, (char *)buf, count, pos, 0); -} - -static ssize_t cdev_aio_write(struct kiocb *iocb, const struct iovec *io, - unsigned long count, loff_t pos) -{ - struct qdma_cdev *xcdev = - (struct qdma_cdev *)iocb->ki_filp->private_data; - struct cdev_async_io *caio; - int rv = 0; - unsigned long i; - unsigned long qhndl; - - if (!xcdev) { - pr_err("file 0x%p, xcdev NULL, %llu, pos %llu, W %d.\n", - iocb->ki_filp, (u64)count, (u64)pos, 1); - return -EINVAL; - } - - if (!xcdev->fp_rw) { - pr_err("No Read write handler assigned\n"); - return -EINVAL; - } - - caio = kmem_cache_alloc(cdev_cache, GFP_KERNEL); - if (!caio) { - pr_err("Failed to allocate caio"); - return -ENOMEM; - } - memset(caio, 0, sizeof(struct cdev_async_io)); - caio->qiocb = kzalloc(count * (sizeof(struct qdma_io_cb) + - sizeof(struct qdma_request *)), GFP_KERNEL); - if (!caio->qiocb) { - pr_err("failed to allocate qiocb"); - return -ENOMEM; - } - - caio->reqv = (struct qdma_request **)(caio->qiocb + count); - for (i = 0; i < count; i++) { - caio->qiocb[i].private = caio; - caio->reqv[i] = &(caio->qiocb[i].req); - caio->qiocb[i].buf = io[i].iov_base; - caio->qiocb[i].len = io[i].iov_len; - rv = map_user_buf_to_sgl(&(caio->qiocb[i]), true); - if (rv < 0) - break; - - caio->reqv[i]->write = 1; - caio->reqv[i]->sgcnt = caio->qiocb[i].pages_nr; - caio->reqv[i]->sgl = caio->qiocb[i].sgl; - caio->reqv[i]->dma_mapped = false; - caio->reqv[i]->udd_len = 0; - caio->reqv[i]->ep_addr = (u64)pos; - pos += io[i].iov_len; - caio->reqv[i]->no_memcpy = xcdev->no_memcpy ? 1 : 0; - caio->reqv[i]->count = io->iov_len; - caio->reqv[i]->timeout_ms = 10 * 1000; /* 10 seconds */ - caio->reqv[i]->fp_done = qdma_req_completed; - - } - if (i > 0) { - iocb->private = caio; - caio->iocb = iocb; - caio->req_count = i; - qhndl = xcdev->h2c_qhndl; - rv = xcdev->fp_aiorw(xcdev->xcb->xpdev->dev_hndl, qhndl, - caio->req_count, caio->reqv); - if (rv >= 0) - rv = -EIOCBQUEUED; - } else { - pr_err("failed with %d for %lu reqs", rv, caio->req_count); - kfree(caio->qiocb); - kmem_cache_free(cdev_cache, caio); - } - - return rv; -} - -static ssize_t cdev_aio_read(struct kiocb *iocb, const struct iovec *io, - unsigned long count, loff_t pos) -{ - struct qdma_cdev *xcdev = - (struct qdma_cdev *)iocb->ki_filp->private_data; - struct cdev_async_io *caio; - int rv = 0; - unsigned long i; - unsigned long qhndl; - - if (!xcdev) { - pr_err("file 0x%p, xcdev NULL, %llu, pos %llu, W %d.\n", - iocb->ki_filp, (u64)count, (u64)pos, 1); - return -EINVAL; - } - - if (!xcdev->fp_rw) { - pr_err("No Read write handler assigned\n"); - return -EINVAL; - } - - caio = kmem_cache_alloc(cdev_cache, GFP_KERNEL); - if (!caio) { - pr_err("failed to allocate qiocb"); - return -ENOMEM; - } - memset(caio, 0, sizeof(struct cdev_async_io)); - caio->qiocb = kzalloc(count * (sizeof(struct qdma_io_cb) + - sizeof(struct qdma_request *)), GFP_KERNEL); - if (!caio->qiocb) { - pr_err("failed to allocate qiocb"); - return -ENOMEM; - } - - caio->reqv = (struct qdma_request **)(caio->qiocb + count); - for (i = 0; i < count; i++) { - caio->qiocb[i].private = caio; - caio->reqv[i] = &(caio->qiocb[i].req); - caio->qiocb[i].buf = io[i].iov_base; - caio->qiocb[i].len = io[i].iov_len; - rv = map_user_buf_to_sgl(&(caio->qiocb[i]), false); - if (rv < 0) - break; - - caio->reqv[i]->write = 0; - caio->reqv[i]->sgcnt = caio->qiocb[i].pages_nr; - caio->reqv[i]->sgl = caio->qiocb[i].sgl; - caio->reqv[i]->dma_mapped = false; - caio->reqv[i]->udd_len = 0; - caio->reqv[i]->ep_addr = (u64)pos; - pos += io[i].iov_len; - caio->reqv[i]->no_memcpy = xcdev->no_memcpy ? 1 : 0; - caio->reqv[i]->count = io->iov_len; - caio->reqv[i]->timeout_ms = 10 * 1000; /* 10 seconds */ - caio->reqv[i]->fp_done = qdma_req_completed; - } - if (i > 0) { - iocb->private = caio; - caio->iocb = iocb; - caio->req_count = i; - qhndl = xcdev->c2h_qhndl; - rv = xcdev->fp_aiorw(xcdev->xcb->xpdev->dev_hndl, qhndl, - caio->req_count, caio->reqv); - if (rv >= 0) - rv = -EIOCBQUEUED; - } else { - pr_err("failed with %d for %lu reqs", rv, caio->req_count); - kfree(caio->qiocb); - kmem_cache_free(cdev_cache, caio); - } - - return rv; -} - -#if KERNEL_VERSION(3, 16, 0) <= LINUX_VERSION_CODE -static ssize_t cdev_write_iter(struct kiocb *iocb, struct iov_iter *io) -{ - return cdev_aio_write(iocb, io->iov, io->nr_segs, iocb->ki_pos); -} - -static ssize_t cdev_read_iter(struct kiocb *iocb, struct iov_iter *io) -{ - return cdev_aio_read(iocb, io->iov, io->nr_segs, iocb->ki_pos); -} -#endif - -static const struct file_operations cdev_gen_fops = { - .owner = THIS_MODULE, - .open = cdev_gen_open, - .release = cdev_gen_close, - .write = cdev_gen_write, -#if KERNEL_VERSION(3, 16, 0) <= LINUX_VERSION_CODE - .write_iter = cdev_write_iter, -#else - .aio_write = cdev_aio_write, -#endif - .read = cdev_gen_read, -#if KERNEL_VERSION(3, 16, 0) <= LINUX_VERSION_CODE - .read_iter = cdev_read_iter, -#else - .aio_read = cdev_aio_read, -#endif - .unlocked_ioctl = cdev_gen_ioctl, - .llseek = cdev_gen_llseek, -}; - -/* - * xcb: per pci device character device control info. - * xcdev: per queue character device - */ -void qdma_cdev_destroy(struct qdma_cdev *xcdev) -{ - - if (!xcdev) { - pr_err("xcdev is NULL.\n"); - return; - } - pr_debug("destroying cdev %p", xcdev); - - if (xcdev->sys_device) - device_destroy(qdma_class, xcdev->cdevno); - - cdev_del(&xcdev->cdev); - - kfree(xcdev); -} - -int qdma_cdev_create(struct qdma_cdev_cb *xcb, struct pci_dev *pdev, - struct qdma_queue_conf *qconf, unsigned int minor, - unsigned long qhndl, struct qdma_cdev **xcdev_pp, - char *ebuf, int ebuflen) -{ - struct qdma_cdev *xcdev; - int rv; - unsigned long *priv_data; - - xcdev = kzalloc(sizeof(struct qdma_cdev) + strlen(qconf->name) + 1, - GFP_KERNEL); - if (!xcdev) { - pr_err("%s failed to allocate cdev %lu.\n", - qconf->name, sizeof(struct qdma_cdev)); - if (ebuf && ebuflen) { - rv = snprintf(ebuf, ebuflen, - "%s failed to allocate cdev %lu.\n", - qconf->name, sizeof(struct qdma_cdev)); - ebuf[rv] = '\0'; - - } - return -ENOMEM; - } - - xcdev->cdev.owner = THIS_MODULE; - xcdev->xcb = xcb; - priv_data = (qconf->q_type == Q_C2H) ? - &xcdev->c2h_qhndl : &xcdev->h2c_qhndl; - *priv_data = qhndl; - xcdev->dir_init = (1 << qconf->q_type); - strcpy(xcdev->name, qconf->name); - - xcdev->minor = minor; - if (xcdev->minor >= xcb->cdev_minor_cnt) { - pr_err("%s: no char dev. left.\n", qconf->name); - if (ebuf && ebuflen) { - rv = snprintf(ebuf, ebuflen, "%s cdev no cdev left.\n", - qconf->name); - ebuf[rv] = '\0'; - } - rv = -ENOSPC; - goto err_out; - } - xcdev->cdevno = MKDEV(xcb->cdev_major, xcdev->minor); - - cdev_init(&xcdev->cdev, &cdev_gen_fops); - - /* bring character device live */ - rv = cdev_add(&xcdev->cdev, xcdev->cdevno, 1); - if (rv < 0) { - pr_err("cdev_add failed %d, %s.\n", rv, xcdev->name); - if (ebuf && ebuflen) { - int l = snprintf(ebuf, ebuflen, - "%s cdev add failed %d.\n", - qconf->name, rv); - ebuf[l] = '\0'; - } - goto err_out; - } - - /* create device on our class */ - if (qdma_class) { - xcdev->sys_device = device_create(qdma_class, &(pdev->dev), - xcdev->cdevno, NULL, "%s", xcdev->name); - if (IS_ERR(xcdev->sys_device)) { - rv = PTR_ERR(xcdev->sys_device); - pr_err("%s device_create failed %d.\n", - xcdev->name, rv); - if (ebuf && ebuflen) { - int l = snprintf(ebuf, ebuflen, - "%s device_create failed %d.\n", - qconf->name, rv); - ebuf[l] = '\0'; - } - goto del_cdev; - } - } - - xcdev->fp_rw = qdma_request_submit; - xcdev->fp_aiorw = qdma_batch_request_submit; - - *xcdev_pp = xcdev; - return 0; - -del_cdev: - cdev_del(&xcdev->cdev); - -err_out: - kfree(xcdev); - return rv; -} - -/* - * per device initialization & cleanup - */ -void qdma_cdev_device_cleanup(struct qdma_cdev_cb *xcb) -{ - if (!xcb->cdev_major) - return; - - xcb->cdev_major = 0; -} - -int qdma_cdev_device_init(struct qdma_cdev_cb *xcb) -{ - dev_t dev; - int rv; - struct xlnx_phy_dev *phy_dev, *tmp, *new_phy_dev; - struct xlnx_dma_dev *xdev = NULL; - - spin_lock_init(&xcb->lock); - - xcb->cdev_minor_cnt = QDMA_MINOR_MAX; - - if (xcb->cdev_major) { - pr_warn("major %d already exist.\n", xcb->cdev_major); - return -EINVAL; - } - - /* Check if same bus id device is added in global list - * If found then assign same major number - */ - mutex_lock(&xlnx_phy_dev_mutex); - xdev = (struct xlnx_dma_dev *)xcb->xpdev->dev_hndl; - list_for_each_entry_safe(phy_dev, tmp, &xlnx_phy_dev_list, list_head) { - if (phy_dev->device_bus == xcb->xpdev->pdev->bus->number && - phy_dev->dma_device_index == xdev->dma_device_index) { - xcb->cdev_major = phy_dev->major; - mutex_unlock(&xlnx_phy_dev_mutex); - return 0; - } - } - mutex_unlock(&xlnx_phy_dev_mutex); - - /* allocate a dynamically allocated char device node */ - rv = alloc_chrdev_region(&dev, 0, xcb->cdev_minor_cnt, - QDMA_CDEV_CLASS_NAME); - if (rv) { - pr_err("unable to allocate cdev region %d.\n", rv); - return rv; - } - xcb->cdev_major = MAJOR(dev); - - new_phy_dev = kzalloc(sizeof(struct xlnx_phy_dev), GFP_KERNEL); - if (!new_phy_dev) { - pr_err("unable to allocate xlnx_dev.\n"); - return -ENOMEM; - } - - new_phy_dev->major = xcb->cdev_major; - new_phy_dev->device_bus = xcb->xpdev->pdev->bus->number; - new_phy_dev->dma_device_index = xdev->dma_device_index; - xlnx_phy_dev_list_add(new_phy_dev); - - return 0; -} - -/* - * driver-wide Initialization & cleanup - */ - -int qdma_cdev_init(void) -{ - qdma_class = class_create(THIS_MODULE, QDMA_CDEV_CLASS_NAME); - if (IS_ERR(qdma_class)) { - pr_err("%s: failed to create class 0x%lx.", - QDMA_CDEV_CLASS_NAME, (unsigned long)qdma_class); - qdma_class = NULL; - return -ENODEV; - } - /* using kmem_cache_create to enable sequential cleanup */ - cdev_cache = kmem_cache_create("cdev_cache", - sizeof(struct cdev_async_io), - 0, - SLAB_HWCACHE_ALIGN, - NULL); - if (!cdev_cache) { - pr_err("failed to allocate cdev_cache\n"); - return -ENOMEM; - } - - return 0; -} - -void qdma_cdev_cleanup(void) -{ - struct xlnx_phy_dev *phy_dev, *tmp; - - list_for_each_entry_safe(phy_dev, tmp, &xlnx_phy_dev_list, list_head) { - unregister_chrdev_region(MKDEV(phy_dev->major, 0), - QDMA_MINOR_MAX); - xlnx_phy_dev_list_remove(phy_dev); - kfree(phy_dev); - } - - kmem_cache_destroy(cdev_cache); - if (qdma_class) - class_destroy(qdma_class); - -} diff --git a/QDMA/linux-kernel/driver/src/cdev.h b/QDMA/linux-kernel/driver/src/cdev.h deleted file mode 100755 index 371e52801..000000000 --- a/QDMA/linux-kernel/driver/src/cdev.h +++ /dev/null @@ -1,183 +0,0 @@ -/* - * This file is part of the Xilinx DMA IP Core driver for Linux - * - * Copyright (c) 2017-2022, Xilinx, Inc. All rights reserved. - * Copyright (c) 2022-2023, Advanced Micro Devices, Inc. All rights reserved. - * - * This source code is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * The full GNU General Public License is included in this distribution in - * the file called "COPYING". - */ - -#ifndef __QDMA_CDEV_H__ -#define __QDMA_CDEV_H__ -/** - * @file - * @brief This file contains the declarations for qdma pcie kernel module - * - */ -#include -#include "version.h" -#include - -#include "libqdma/libqdma_export.h" -#include - -/** QDMA character device class name */ -#define QDMA_CDEV_CLASS_NAME DRV_MODULE_NAME -/** QDMA character device max minor number to support 4k queues */ -#define QDMA_MINOR_MAX (4096) - -/* per pci device control */ -/** - * @struct - qdma_cdev_cb - * @brief QDMA character device call back data - */ -struct qdma_cdev_cb { - /** pointer to xilinx pcie device */ - struct xlnx_pci_dev *xpdev; - /** character device lock */ - spinlock_t lock; - /** character device major number */ - int cdev_major; - /** character device minor number count */ - int cdev_minor_cnt; -}; - -/** - * @struct - qdma_cdev - * @brief QDMA character device book keeping parameters - */ -struct qdma_cdev { - /** lsit of qdma character devices */ - struct list_head list_head; - /** minor number */ - int minor; - /** character device number */ - dev_t cdevno; - /** pointer to qdma character device call back data */ - struct qdma_cdev_cb *xcb; - /** pointer to kernel device(struct device) */ - struct device *sys_device; - /** pointer to kernel cdev(struct cdev) */ - struct cdev cdev; - /** c2h queue handle */ - unsigned long c2h_qhndl; - /** hec queue handle */ - unsigned long h2c_qhndl; - /** direction */ - unsigned short dir_init; - /* flag to indicate if memcpy is required */ - unsigned char no_memcpy; - /** call back function for open a device */ - int (*fp_open_extra)(struct qdma_cdev *xcdev); - /** call back function for close a device */ - int (*fp_close_extra)(struct qdma_cdev *xcdev); - /** call back function to handle ioctl message */ - long (*fp_ioctl_extra)(struct qdma_cdev *xcdev, unsigned int cmd, - unsigned long arg); - /** call back function to handle read write request*/ - ssize_t (*fp_rw)(unsigned long dev_hndl, unsigned long qhndl, - struct qdma_request *req); - ssize_t (*fp_aiorw)(unsigned long dev_hndl, unsigned long qhndl, - unsigned long count, struct qdma_request **reqv); - /** name of the character device*/ - char name[0]; -}; - -/** - * @struct - qdma_io_cb - * @brief QDMA character device io call back book keeping parameters - */ -struct qdma_io_cb { - void *private; - /** user buffer */ - void __user *buf; - /** length of the user buffer */ - size_t len; - /** page number */ - unsigned int pages_nr; - /** scatter gather list */ - struct qdma_sw_sg *sgl; - /** pages allocated to accommodate the scatter gather list */ - struct page **pages; - /** qdma request */ - struct qdma_request req; -}; - -/*****************************************************************************/ -/** - * qdma_cdev_destroy() - handler to destroy the character device - * - * @param[in] xcdev: pointer to character device - * - * @return none - *****************************************************************************/ -void qdma_cdev_destroy(struct qdma_cdev *xcdev); - -/*****************************************************************************/ -/** - * qdma_cdev_create() - handler to create a character device - * - * @param[in] xcb: pointer to qdma character device call back data - * @param[in] pdev: pointer to struct pci_dev - * @param[in] qconf: queue configurations - * @param[in] minor: character device minor number - * @param[in] ebuflen: buffer length - * @param[in] qhndl: queue handle - * @param[out] xcdev_pp: pointer to struct qdma_cdev - * @param[out] ebuf: - * error message buffer, can be NULL/0 (i.e., optional) - * - * @return 0: success - * @return <0: failure - *****************************************************************************/ -int qdma_cdev_create(struct qdma_cdev_cb *xcb, struct pci_dev *pdev, - struct qdma_queue_conf *qconf, unsigned int minor, - unsigned long qhndl, struct qdma_cdev **xcdev_pp, - char *ebuf, int ebuflen); - -/*****************************************************************************/ -/** - * qdma_cdev_device_cleanup() - handler to clean up a character device - * - * @param[in] xcb: pointer to qdma character device call back data - * - * @return none - *****************************************************************************/ -void qdma_cdev_device_cleanup(struct qdma_cdev_cb *xcb); - -/*****************************************************************************/ -/** - * qdma_cdev_device_init() - handler to initialize a character device - * - * @param[in] xcb: pointer to qdma character device call back data - * - * @return 0: success - * @return <0: failure - *****************************************************************************/ -int qdma_cdev_device_init(struct qdma_cdev_cb *xcb); - -/*****************************************************************************/ -/** - * qdma_cdev_cleanup() - character device cleanup handler - * - *****************************************************************************/ -void qdma_cdev_cleanup(void); - -/*****************************************************************************/ -/** - * qdma_cdev_init() - character device initialization handler - * - *****************************************************************************/ -int qdma_cdev_init(void); - -#endif /* ifndef __QDMA_CDEV_H__ */ diff --git a/QDMA/linux-kernel/driver/src/nl.c b/QDMA/linux-kernel/driver/src/nl.c deleted file mode 100755 index 5a3da367c..000000000 --- a/QDMA/linux-kernel/driver/src/nl.c +++ /dev/null @@ -1,2902 +0,0 @@ -/* - * This file is part of the Xilinx DMA IP Core driver for Linux - * - * Copyright (c) 2017-2022, Xilinx, Inc. All rights reserved. - * Copyright (c) 2022-2023, Advanced Micro Devices, Inc. All rights reserved. - * - * This source code is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * The full GNU General Public License is included in this distribution in - * the file called "COPYING". - */ - -#define pr_fmt(fmt) KBUILD_MODNAME ":%s: " fmt, __func__ - -#include -#include -#include -#include - -#include "libqdma/libqdma_export.h" -#include "qdma_mod.h" -#include "qdma_nl.h" -#include "nl.h" -#include "version.h" - -#define QDMA_C2H_DEFAULT_BUF_SZ (4096) -#define DUMP_LINE_SZ (81) -#define QDMA_Q_DUMP_MAX_QUEUES (100) -#define QDMA_Q_DUMP_LINE_SZ (25 * 1024) -#define QDMA_Q_LIST_LINE_SZ (200) - -static int xnl_dev_list(struct sk_buff *skb2, struct genl_info *info); - -#ifdef RHEL_RELEASE_VERSION -#if RHEL_RELEASE_VERSION(8, 3) > RHEL_RELEASE_CODE -static struct nla_policy xnl_policy[XNL_ATTR_MAX] = { - [XNL_ATTR_GENMSG] = { .type = NLA_NUL_STRING }, - - [XNL_ATTR_DRV_INFO] = { .type = NLA_NUL_STRING }, - - [XNL_ATTR_DEV_IDX] = { .type = NLA_U32 }, - [XNL_ATTR_PCI_BUS] = { .type = NLA_U32 }, - [XNL_ATTR_PCI_DEV] = { .type = NLA_U32 }, - [XNL_ATTR_PCI_FUNC] = { .type = NLA_U32 }, - [XNL_ATTR_DEV_CFG_BAR] = { .type = NLA_U32 }, - [XNL_ATTR_DEV_USR_BAR] = { .type = NLA_U32 }, - [XNL_ATTR_DEV_QSET_MAX] = { .type = NLA_U32 }, - [XNL_ATTR_DEV_QSET_QBASE] = { .type = NLA_U32 }, - - [XNL_ATTR_VERSION_INFO] = { .type = NLA_NUL_STRING }, - [XNL_ATTR_DEVICE_TYPE] = { .type = NLA_NUL_STRING }, - [XNL_ATTR_IP_TYPE] = { .type = NLA_NUL_STRING }, - [XNL_ATTR_DEV_NUMQS] = { .type = NLA_U32 }, - [XNL_ATTR_DEV_NUM_PFS] = { .type = NLA_U32 }, - [XNL_ATTR_DEV_MM_CHANNEL_MAX] = { .type = NLA_U32 }, - [XNL_ATTR_DEV_MAILBOX_ENABLE] = { .type = NLA_U32 }, - [XNL_ATTR_DEV_FLR_PRESENT] = { .type = NLA_U32 }, - [XNL_ATTR_DEV_ST_ENABLE] = { .type = NLA_U32 }, - [XNL_ATTR_DEV_MM_ENABLE] = { .type = NLA_U32 }, - [XNL_ATTR_DEV_MM_CMPT_ENABLE] = { .type = NLA_U32 }, - - [XNL_ATTR_REG_BAR_NUM] = { .type = NLA_U32 }, - [XNL_ATTR_REG_ADDR] = { .type = NLA_U32 }, - [XNL_ATTR_REG_VAL] = { .type = NLA_U32 }, - - [XNL_ATTR_QIDX] = { .type = NLA_U32 }, - [XNL_ATTR_NUM_Q] = { .type = NLA_U32 }, - [XNL_ATTR_QFLAG] = { .type = NLA_U32 }, - [XNL_ATTR_CMPT_DESC_SIZE] = { .type = NLA_U32 }, - [XNL_ATTR_SW_DESC_SIZE] = { .type = NLA_U32 }, - [XNL_ATTR_QRNGSZ_IDX] = { .type = NLA_U32 }, - [XNL_ATTR_C2H_BUFSZ_IDX] = { .type = NLA_U32 }, - [XNL_ATTR_CMPT_TIMER_IDX] = { .type = NLA_U32 }, - [XNL_ATTR_CMPT_CNTR_IDX] = { .type = NLA_U32 }, - [XNL_ATTR_MM_CHANNEL] = { .type = NLA_U32 }, - [XNL_ATTR_CMPT_TRIG_MODE] = { .type = NLA_U32 }, - [XNL_ATTR_CMPT_ENTRIES_CNT] = { .type = NLA_U32 }, - [XNL_ATTR_RANGE_START] = { .type = NLA_U32 }, - [XNL_ATTR_RANGE_END] = { .type = NLA_U32 }, - - [XNL_ATTR_INTR_VECTOR_IDX] = { .type = NLA_U32 }, - [XNL_ATTR_PIPE_GL_MAX] = { .type = NLA_U32 }, - [XNL_ATTR_PIPE_FLOW_ID] = { .type = NLA_U32 }, - [XNL_ATTR_PIPE_SLR_ID] = { .type = NLA_U32 }, - [XNL_ATTR_PIPE_TDEST] = { .type = NLA_U32 }, - - [XNL_ATTR_DEV_STM_BAR] = { .type = NLA_U32 }, - [XNL_ATTR_Q_STATE] = { .type = NLA_U32 }, - [XNL_ATTR_ERROR] = { .type = NLA_U32 }, - [XNL_ATTR_PING_PONG_EN] = { .type = NLA_U32 }, - [XNL_ATTR_DEV] = { .type = NLA_BINARY, - .len = QDMA_DEV_ATTR_STRUCT_SIZE, }, - [XNL_ATTR_GLOBAL_CSR] = { .type = NLA_BINARY, - .len = QDMA_DEV_GLOBAL_CSR_STRUCT_SIZE, }, -#ifdef ERR_DEBUG - [XNL_ATTR_QPARAM_ERR_INFO] = { .type = NLA_U32 }, -#endif -}; -#endif -#else -#if ((KERNEL_VERSION(5, 2, 0) > LINUX_VERSION_CODE) || (LINUX_VERSION_CODE > \ - KERNEL_VERSION(5, 9, 0))) -static struct nla_policy xnl_policy[XNL_ATTR_MAX] = { - [XNL_ATTR_GENMSG] = { .type = NLA_NUL_STRING }, - - [XNL_ATTR_DRV_INFO] = { .type = NLA_NUL_STRING }, - - [XNL_ATTR_DEV_IDX] = { .type = NLA_U32 }, - [XNL_ATTR_PCI_BUS] = { .type = NLA_U32 }, - [XNL_ATTR_PCI_DEV] = { .type = NLA_U32 }, - [XNL_ATTR_PCI_FUNC] = { .type = NLA_U32 }, - [XNL_ATTR_DEV_CFG_BAR] = { .type = NLA_U32 }, - [XNL_ATTR_DEV_USR_BAR] = { .type = NLA_U32 }, - [XNL_ATTR_DEV_QSET_MAX] = { .type = NLA_U32 }, - [XNL_ATTR_DEV_QSET_QBASE] = { .type = NLA_U32 }, - - [XNL_ATTR_VERSION_INFO] = { .type = NLA_NUL_STRING }, - [XNL_ATTR_DEVICE_TYPE] = { .type = NLA_NUL_STRING }, - [XNL_ATTR_IP_TYPE] = { .type = NLA_NUL_STRING }, - [XNL_ATTR_DEV_NUMQS] = { .type = NLA_U32 }, - [XNL_ATTR_DEV_NUM_PFS] = { .type = NLA_U32 }, - [XNL_ATTR_DEV_MM_CHANNEL_MAX] = { .type = NLA_U32 }, - [XNL_ATTR_DEV_MAILBOX_ENABLE] = { .type = NLA_U32 }, - [XNL_ATTR_DEV_FLR_PRESENT] = { .type = NLA_U32 }, - [XNL_ATTR_DEV_ST_ENABLE] = { .type = NLA_U32 }, - [XNL_ATTR_DEV_MM_ENABLE] = { .type = NLA_U32 }, - [XNL_ATTR_DEV_MM_CMPT_ENABLE] = { .type = NLA_U32 }, - - [XNL_ATTR_REG_BAR_NUM] = { .type = NLA_U32 }, - [XNL_ATTR_REG_ADDR] = { .type = NLA_U32 }, - [XNL_ATTR_REG_VAL] = { .type = NLA_U32 }, - - [XNL_ATTR_CSR_INDEX] = { .type = NLA_U32 }, - [XNL_ATTR_CSR_COUNT] = { .type = NLA_U32 }, - - [XNL_ATTR_QIDX] = { .type = NLA_U32 }, - [XNL_ATTR_NUM_Q] = { .type = NLA_U32 }, - [XNL_ATTR_QFLAG] = { .type = NLA_U32 }, - [XNL_ATTR_CMPT_DESC_SIZE] = { .type = NLA_U32 }, - [XNL_ATTR_SW_DESC_SIZE] = { .type = NLA_U32 }, - [XNL_ATTR_QRNGSZ_IDX] = { .type = NLA_U32 }, - [XNL_ATTR_C2H_BUFSZ_IDX] = { .type = NLA_U32 }, - [XNL_ATTR_CMPT_TIMER_IDX] = { .type = NLA_U32 }, - [XNL_ATTR_CMPT_CNTR_IDX] = { .type = NLA_U32 }, - [XNL_ATTR_MM_CHANNEL] = { .type = NLA_U32 }, - [XNL_ATTR_CMPT_TRIG_MODE] = { .type = NLA_U32 }, - [XNL_ATTR_CMPT_ENTRIES_CNT] = { .type = NLA_U32 }, - [XNL_ATTR_RANGE_START] = { .type = NLA_U32 }, - [XNL_ATTR_RANGE_END] = { .type = NLA_U32 }, - - [XNL_ATTR_INTR_VECTOR_IDX] = { .type = NLA_U32 }, - [XNL_ATTR_INTR_VECTOR_START_IDX] = { .type = NLA_U32 }, - [XNL_ATTR_INTR_VECTOR_END_IDX] = { .type = NLA_U32 }, - [XNL_ATTR_RSP_BUF_LEN] = { .type = NLA_U32 }, - [XNL_ATTR_PIPE_GL_MAX] = { .type = NLA_U32 }, - [XNL_ATTR_PIPE_FLOW_ID] = { .type = NLA_U32 }, - [XNL_ATTR_PIPE_SLR_ID] = { .type = NLA_U32 }, - [XNL_ATTR_PIPE_TDEST] = { .type = NLA_U32 }, - - [XNL_ATTR_DEV_STM_BAR] = { .type = NLA_U32 }, - [XNL_ATTR_Q_STATE] = { .type = NLA_U32 }, - [XNL_ATTR_ERROR] = { .type = NLA_U32 }, - [XNL_ATTR_PING_PONG_EN] = { .type = NLA_U32 }, - [XNL_ATTR_APERTURE_SZ] = { .type = NLA_U32 }, - [XNL_ATTR_DEV_STAT_PING_PONG_LATMIN1] = { .type = NLA_U32 }, - [XNL_ATTR_DEV_STAT_PING_PONG_LATMIN2] = { .type = NLA_U32 }, - [XNL_ATTR_DEV_STAT_PING_PONG_LATMAX1] = { .type = NLA_U32 }, - [XNL_ATTR_DEV_STAT_PING_PONG_LATMAX2] = { .type = NLA_U32 }, - [XNL_ATTR_DEV_STAT_PING_PONG_LATAVG1] = { .type = NLA_U32 }, - [XNL_ATTR_DEV_STAT_PING_PONG_LATAVG2] = { .type = NLA_U32 }, - [XNL_ATTR_DEV] = { .type = NLA_BINARY, - .len = QDMA_DEV_ATTR_STRUCT_SIZE, }, - [XNL_ATTR_GLOBAL_CSR] = { .type = NLA_BINARY, - .len = QDMA_DEV_GLOBAL_CSR_STRUCT_SIZE, }, -#ifdef ERR_DEBUG - [XNL_ATTR_QPARAM_ERR_INFO] = { .type = NLA_U32 }, -#endif -}; -#endif -#endif - -static int xnl_respond_buffer_cmpt(struct genl_info *info, char *buf, - int buflen, int error, long int cmpt_entries); - -static int xnl_dev_info(struct sk_buff *, struct genl_info *); -static int xnl_dev_version_capabilities(struct sk_buff *skb2, - struct genl_info *info); -static int xnl_dev_stat(struct sk_buff *, struct genl_info *); -static int xnl_dev_stat_clear(struct sk_buff *, struct genl_info *); -static int xnl_q_list(struct sk_buff *, struct genl_info *); -static int xnl_q_add(struct sk_buff *, struct genl_info *); -static int xnl_q_start(struct sk_buff *, struct genl_info *); -static int xnl_q_stop(struct sk_buff *, struct genl_info *); -static int xnl_q_del(struct sk_buff *, struct genl_info *); -static int xnl_q_dump(struct sk_buff *, struct genl_info *); -static int xnl_q_dump_desc(struct sk_buff *, struct genl_info *); -static int xnl_q_dump_cmpt(struct sk_buff *, struct genl_info *); -static int xnl_config_reg_dump(struct sk_buff *, struct genl_info *); -static int xnl_q_read_pkt(struct sk_buff *, struct genl_info *); -static int xnl_q_read_udd(struct sk_buff *, struct genl_info *); -static int xnl_q_cmpt_read(struct sk_buff *, struct genl_info *); -static int xnl_intr_ring_dump(struct sk_buff *, struct genl_info *); -static int xnl_register_read(struct sk_buff *, struct genl_info *); -static int xnl_register_write(struct sk_buff *, struct genl_info *); -static int xnl_get_global_csr(struct sk_buff *skb2, struct genl_info *info); -static int xnl_get_queue_state(struct sk_buff *, struct genl_info *); -static int xnl_config_reg_info_dump(struct sk_buff *, struct genl_info *); - -#ifdef TANDEM_BOOT_SUPPORTED -static int xnl_en_st(struct sk_buff *skb2, struct genl_info *info); -#endif - -#ifdef ERR_DEBUG -static int xnl_err_induce(struct sk_buff *skb2, struct genl_info *info); -#endif - -#ifdef RHEL_RELEASE_VERSION -#if RHEL_RELEASE_VERSION(8, 3) > RHEL_RELEASE_CODE -#define GENL_OPS_POLICY -#endif -#else -#if ((KERNEL_VERSION(5, 2, 0) > LINUX_VERSION_CODE) || (LINUX_VERSION_CODE > \ - KERNEL_VERSION(5, 9, 0))) -#define GENL_OPS_POLICY -#endif -#endif - -#ifdef GENL_OPS_POLICY -static struct genl_ops xnl_ops[] = { - { - .cmd = XNL_CMD_DEV_LIST, - .policy = xnl_policy, - .doit = xnl_dev_list, - }, - { - .cmd = XNL_CMD_DEV_CAP, - .policy = xnl_policy, - .doit = xnl_dev_version_capabilities, - }, - { - .cmd = XNL_CMD_DEV_INFO, - .policy = xnl_policy, - .doit = xnl_dev_info, - }, - { - .cmd = XNL_CMD_DEV_STAT, - .policy = xnl_policy, - .doit = xnl_dev_stat, - }, - { - .cmd = XNL_CMD_DEV_STAT_CLEAR, - .policy = xnl_policy, - .doit = xnl_dev_stat_clear, - }, - { - .cmd = XNL_CMD_Q_LIST, - .policy = xnl_policy, - .doit = xnl_q_list, - }, - { - .cmd = XNL_CMD_Q_ADD, - .policy = xnl_policy, - .doit = xnl_q_add, - }, - { - .cmd = XNL_CMD_Q_START, - .policy = xnl_policy, - .doit = xnl_q_start, - }, - { - .cmd = XNL_CMD_Q_STOP, - .policy = xnl_policy, - .doit = xnl_q_stop, - }, - { - .cmd = XNL_CMD_Q_DEL, - .policy = xnl_policy, - .doit = xnl_q_del, - }, - { - .cmd = XNL_CMD_Q_DUMP, - .policy = xnl_policy, - .doit = xnl_q_dump, - }, - { - .cmd = XNL_CMD_Q_DESC, - .policy = xnl_policy, - .doit = xnl_q_dump_desc, - }, - { - .cmd = XNL_CMD_REG_DUMP, - .policy = xnl_policy, - .doit = xnl_config_reg_dump, - }, - { - .cmd = XNL_CMD_REG_INFO_READ, - .policy = xnl_policy, - .doit = xnl_config_reg_info_dump, - }, - { - .cmd = XNL_CMD_Q_CMPT, - .policy = xnl_policy, - .doit = xnl_q_dump_cmpt, - }, - { - .cmd = XNL_CMD_Q_UDD, - .policy = xnl_policy, - .doit = xnl_q_read_udd, - }, - { - .cmd = XNL_CMD_Q_RX_PKT, - .policy = xnl_policy, - .doit = xnl_q_read_pkt, - }, - { - .cmd = XNL_CMD_Q_CMPT_READ, - .policy = xnl_policy, - .doit = xnl_q_cmpt_read, - }, - { - .cmd = XNL_CMD_INTR_RING_DUMP, - .policy = xnl_policy, - .doit = xnl_intr_ring_dump, - }, - { - .cmd = XNL_CMD_REG_RD, - .policy = xnl_policy, - .doit = xnl_register_read, - }, - { - .cmd = XNL_CMD_REG_WRT, - .policy = xnl_policy, - .doit = xnl_register_write, - }, - { - .cmd = XNL_CMD_GLOBAL_CSR, - .policy = xnl_policy, - .doit = xnl_get_global_csr, - }, - { - .cmd = XNL_CMD_GET_Q_STATE, - .policy = xnl_policy, - .doit = xnl_get_queue_state, - }, - -#ifdef TANDEM_BOOT_SUPPORTED - { - .cmd = XNL_CMD_EN_ST, - .policy = xnl_policy, - .doit = xnl_en_st, - }, -#endif - -#ifdef ERR_DEBUG - { - .cmd = XNL_CMD_Q_ERR_INDUCE, - .policy = xnl_policy, - .doit = xnl_err_induce, - } -#endif -}; -#else -static struct genl_ops xnl_ops[] = { - { - .cmd = XNL_CMD_DEV_LIST, - .doit = xnl_dev_list, - }, - { - .cmd = XNL_CMD_DEV_CAP, - .doit = xnl_dev_version_capabilities, - }, - { - .cmd = XNL_CMD_DEV_INFO, - .doit = xnl_dev_info, - }, - { - .cmd = XNL_CMD_DEV_STAT, - .doit = xnl_dev_stat, - }, - { - .cmd = XNL_CMD_DEV_STAT_CLEAR, - .doit = xnl_dev_stat_clear, - }, - { - .cmd = XNL_CMD_Q_LIST, - .doit = xnl_q_list, - }, - { - .cmd = XNL_CMD_Q_ADD, - .doit = xnl_q_add, - }, - { - .cmd = XNL_CMD_Q_START, - .doit = xnl_q_start, - }, - { - .cmd = XNL_CMD_Q_STOP, - .doit = xnl_q_stop, - }, - { - .cmd = XNL_CMD_Q_DEL, - .doit = xnl_q_del, - }, - { - .cmd = XNL_CMD_Q_DUMP, - .doit = xnl_q_dump, - }, - { - .cmd = XNL_CMD_Q_DESC, - .doit = xnl_q_dump_desc, - }, - { - .cmd = XNL_CMD_REG_DUMP, - .doit = xnl_config_reg_dump, - }, - { - .cmd = XNL_CMD_REG_INFO_READ, - .doit = xnl_config_reg_info_dump, - }, - { - .cmd = XNL_CMD_Q_CMPT, - .doit = xnl_q_dump_cmpt, - }, - { - .cmd = XNL_CMD_Q_UDD, - .doit = xnl_q_read_udd, - }, - { - .cmd = XNL_CMD_Q_RX_PKT, - .doit = xnl_q_read_pkt, - }, - { - .cmd = XNL_CMD_Q_CMPT_READ, - .doit = xnl_q_cmpt_read, - }, - { - .cmd = XNL_CMD_INTR_RING_DUMP, - .doit = xnl_intr_ring_dump, - }, - { - .cmd = XNL_CMD_REG_RD, - .doit = xnl_register_read, - }, - { - .cmd = XNL_CMD_REG_WRT, - .doit = xnl_register_write, - }, - { - .cmd = XNL_CMD_GLOBAL_CSR, - .doit = xnl_get_global_csr, - }, - { - .cmd = XNL_CMD_GET_Q_STATE, - .doit = xnl_get_queue_state, - }, - -#ifdef TANDEM_BOOT_SUPPORTED - { - .cmd = XNL_CMD_EN_ST, - .doit = xnl_en_st, - }, -#endif - -#ifdef ERR_DEBUG - { - .cmd = XNL_CMD_Q_ERR_INDUCE, - .doit = xnl_err_induce, - } -#endif -}; -#endif - -static struct genl_family xnl_family = { -#ifdef GENL_ID_GENERATE - .id = GENL_ID_GENERATE, -#endif - .hdrsize = 0, -#ifdef __QDMA_VF__ - .name = XNL_NAME_VF, -#else - .name = XNL_NAME_PF, -#endif -#ifndef __GENL_REG_FAMILY_OPS_FUNC__ - .ops = xnl_ops, - .n_ops = ARRAY_SIZE(xnl_ops), -#endif - .maxattr = XNL_ATTR_MAX - 1, -}; - -static struct sk_buff *xnl_msg_alloc(enum xnl_op_t op, int min_sz, - void **hdr, struct genl_info *info) -{ - struct sk_buff *skb; - void *p; - unsigned long sz = min_sz < NLMSG_GOODSIZE ? NLMSG_GOODSIZE : min_sz; - - skb = genlmsg_new(sz, GFP_KERNEL); - if (!skb) { - pr_err("failed to allocate skb %lu.\n", sz); - return NULL; - } - - p = genlmsg_put(skb, 0, info->snd_seq + 1, &xnl_family, 0, op); - if (!p) { - pr_err("skb too small.\n"); - nlmsg_free(skb); - return NULL; - } - - *hdr = p; - return skb; -} - -static inline int xnl_msg_add_attr_str(struct sk_buff *skb, - enum xnl_attr_t type, char *s) -{ - int rv; - - rv = nla_put_string(skb, type, s); - if (rv != 0) { - pr_err("nla_put_string return %d.\n", rv); - return -EINVAL; - } - return 0; -} - -static inline int xnl_msg_add_attr_data(struct sk_buff *skb, - enum xnl_attr_t type, void *s, unsigned int len) -{ - int rv; - - rv = nla_put(skb, type, len, s); - if (rv != 0) { - pr_err("nla_put return %d.\n", rv); - return -EINVAL; - } - return 0; -} - - -static inline int xnl_msg_add_attr_uint(struct sk_buff *skb, - enum xnl_attr_t type, u32 v) -{ - int rv; - - rv = nla_put_u32(skb, type, v); - if (rv != 0) { - pr_err("nla add dev_idx failed %d.\n", rv); - return -EINVAL; - } - return 0; -} - -static inline int xnl_msg_send(struct sk_buff *skb_tx, void *hdr, - struct genl_info *info) -{ - int rv; - - genlmsg_end(skb_tx, hdr); - - rv = genlmsg_unicast(genl_info_net(info), skb_tx, info->snd_portid); - if (rv) - pr_err("send portid %d failed %d.\n", info->snd_portid, rv); - - return 0; -} - -#ifdef DEBUG -static int xnl_dump_attrs(struct genl_info *info) -{ - int i; - - pr_info("snd_seq 0x%x, portid 0x%x.\n", - info->snd_seq, info->snd_portid); -#if 0 - print_hex_dump_bytes("nlhdr", DUMP_PREFIX_OFFSET, info->nlhdr, - sizeof(struct nlmsghdr)); - pr_info("\n"); { - print_hex_dump_bytes("genlhdr", DUMP_PREFIX_OFFSET, info->genlhdr, - sizeof(struct genlmsghdr)); - pr_info("\n"); -#endif - - pr_info("nlhdr: len %u, type %u, flags 0x%x, seq 0x%x, pid %u.\n", - info->nlhdr->nlmsg_len, - info->nlhdr->nlmsg_type, - info->nlhdr->nlmsg_flags, - info->nlhdr->nlmsg_seq, - info->nlhdr->nlmsg_pid); - pr_info("genlhdr: cmd 0x%x %s, version %u, reserved 0x%x.\n", - info->genlhdr->cmd, xnl_op_str[info->genlhdr->cmd], - info->genlhdr->version, - info->genlhdr->reserved); - - for (i = 0; i < XNL_ATTR_MAX; i++) { - struct nlattr *na = info->attrs[i]; - - if (na) { -#if ((KERNEL_VERSION(5, 2, 0) > LINUX_VERSION_CODE) || (LINUX_VERSION_CODE > \ - KERNEL_VERSION(5, 9, 0))) - if (xnl_policy[i].type == NLA_NUL_STRING) { -#else - if (1) { -#endif - - char *s = (char *)nla_data(na); - - if (s) - pr_info("attr %d, %s, str %s.\n", - i, xnl_attr_str[i], s); - else - pr_info("attr %d, %s, str NULL.\n", - i, xnl_attr_str[i]); - - } else { - u32 v = nla_get_u32(na); - - pr_info("attr %s, u32 0x%x.\n", - xnl_attr_str[i], v); - } - } - } - - return 0; -} -#else -#define xnl_dump_attrs(info) -#endif - -static int xnl_respond_buffer_cmpt(struct genl_info *info, char *buf, - int buflen, int error, long int cmpt_entries) -{ - struct sk_buff *skb; - void *hdr; - int rv; - - skb = xnl_msg_alloc(info->genlhdr->cmd, buflen, &hdr, info); - if (!skb) - return -ENOMEM; - - rv = xnl_msg_add_attr_str(skb, XNL_ATTR_GENMSG, buf); - if (rv != 0) { - pr_err("xnl_msg_add_attr_str() failed: %d", rv); - nlmsg_free(skb); - return rv; - } - - rv = xnl_msg_add_attr_uint(skb, XNL_ATTR_ERROR, error); - if (rv != 0) { - pr_err("xnl_msg_add_attr_str() failed: %d", rv); - nlmsg_free(skb); - return rv; - } - - rv = xnl_msg_add_attr_uint(skb, XNL_ATTR_CMPT_ENTRIES_CNT, - cmpt_entries); - if (rv != 0) { - pr_err("xnl_msg_add_attr_str() failed: %d", rv); - nlmsg_free(skb); - return rv; - } - - rv = xnl_msg_send(skb, hdr, info); - - return rv; -} - -int xnl_respond_buffer(struct genl_info *info, char *buf, int buflen, int error) -{ - struct sk_buff *skb; - void *hdr; - int rv; - - skb = xnl_msg_alloc(info->genlhdr->cmd, buflen, &hdr, info); - if (!skb) - return -ENOMEM; - - rv = xnl_msg_add_attr_str(skb, XNL_ATTR_GENMSG, buf); - if (rv != 0) { - pr_err("xnl_msg_add_attr_str() failed: %d", rv); - nlmsg_free(skb); - return rv; - } - - rv = xnl_msg_add_attr_uint(skb, XNL_ATTR_ERROR, error); - if (rv != 0) { - pr_err("xnl_msg_add_attr_str() failed: %d", rv); - nlmsg_free(skb); - return rv; - } - - rv = xnl_msg_send(skb, hdr, info); - - return rv; -} - -static int xnl_respond_data(struct genl_info *info, void *buf, int buflen) -{ - struct sk_buff *skb; - void *hdr; - int rv; - - skb = xnl_msg_alloc(info->genlhdr->cmd, buflen, &hdr, info); - if (!skb) - return -ENOMEM; - - rv = xnl_msg_add_attr_data(skb, XNL_ATTR_GLOBAL_CSR, buf, buflen); - if (rv != 0) { - pr_err("xnl_msg_add_attr_data() failed: %d", rv); - return rv; - } - - rv = xnl_msg_send(skb, hdr, info); - return rv; -} - -static char *xnl_mem_alloc(int l, struct genl_info *info) -{ - char ebuf[XNL_ERR_BUFLEN]; - char *buf = kmalloc(l, GFP_KERNEL); - int rv; - - if (buf) { - memset(buf, 0, l); - return buf; - } - - pr_err("xnl OOM %d.\n", l); - - rv = snprintf(ebuf, XNL_ERR_BUFLEN, "ERR! xnl OOM %d.\n", l); - - xnl_respond_buffer(info, ebuf, XNL_ERR_BUFLEN, rv); - - return NULL; -} - -static struct xlnx_pci_dev *xnl_rcv_check_xpdev(struct genl_info *info) -{ - u32 idx; - struct xlnx_pci_dev *xpdev; - char err[XNL_ERR_BUFLEN]; - int rv = 0; - - if (info == NULL) - return NULL; - - if (!info->attrs[XNL_ATTR_DEV_IDX]) { - snprintf(err, sizeof(err), - "command %s missing attribute XNL_ATTR_DEV_IDX", - xnl_op_str[info->genlhdr->cmd]); - rv = -EINVAL; - goto respond_error; - } - - idx = nla_get_u32(info->attrs[XNL_ATTR_DEV_IDX]); - - xpdev = xpdev_find_by_idx(idx, err, sizeof(err)); - if (!xpdev) { - rv = -EINVAL; - /* err buffer populated by xpdev_find_by_idx*/ - goto respond_error; - } - - return xpdev; - -respond_error: - xnl_respond_buffer(info, err, strlen(err), rv); - return NULL; -} - -static int qconf_get(struct qdma_queue_conf *qconf, struct genl_info *info, - char *err, int errlen, unsigned char *is_qp) -{ - u32 f = 0; - - if (!qconf || !info) - return -EINVAL; - - if (!info->attrs[XNL_ATTR_QFLAG]) { - snprintf(err, errlen, "Missing attribute 'XNL_ATTR_QFLAG'\n"); - goto respond_error; - } - f = nla_get_u32(info->attrs[XNL_ATTR_QFLAG]); - if ((f & XNL_F_QMODE_ST) && (f & XNL_F_QMODE_MM)) { - snprintf(err, errlen, "ERR! Both ST and MM mode set.\n"); - goto respond_error; - } else if (!(f & XNL_F_QMODE_ST) && !(f & XNL_F_QMODE_MM)) { - /* default to MM */ - f |= XNL_F_QMODE_MM; - } - - if (!(f & XNL_F_QDIR_H2C) && - !(f & XNL_F_QDIR_C2H) && !(f & XNL_F_Q_CMPL)) { - /* default to H2C */ - f |= XNL_F_QDIR_H2C; - } - - memset(qconf, 0, sizeof(*qconf)); - qconf->st = (f & XNL_F_QMODE_ST) ? 1 : 0; - - if (f & XNL_F_QDIR_H2C) - qconf->q_type = Q_H2C; - else if (f & XNL_F_QDIR_C2H) - qconf->q_type = Q_C2H; - else - qconf->q_type = Q_CMPT; - - *is_qp = ((f & XNL_F_QDIR_BOTH) == XNL_F_QDIR_BOTH) ? 1 : 0; - - if (!info->attrs[XNL_ATTR_QIDX]) { - snprintf(err, errlen, "Missing attribute 'XNL_ATTR_QIDX'"); - goto respond_error; - } - qconf->qidx = nla_get_u32(info->attrs[XNL_ATTR_QIDX]); - if (qconf->qidx == XNL_QIDX_INVALID) - qconf->qidx = QDMA_QUEUE_IDX_INVALID; - - return 0; - -respond_error: - - xnl_respond_buffer(info, err, strlen(err), 0); - return -EINVAL; -} - -static struct xlnx_qdata *xnl_rcv_check_qidx(struct genl_info *info, - struct xlnx_pci_dev *xpdev, - struct qdma_queue_conf *qconf, char *buf, - int buflen) -{ - char ebuf[XNL_ERR_BUFLEN]; - struct xlnx_qdata *qdata = xpdev_queue_get(xpdev, qconf->qidx, - qconf->q_type, 1, ebuf, XNL_ERR_BUFLEN); - - if (!qdata) { - snprintf(ebuf, - XNL_ERR_BUFLEN, - "ERR! qidx %u invalid.\n", - qconf->qidx); - xnl_respond_buffer(info, ebuf, XNL_ERR_BUFLEN, 0); - } - - return qdata; -} - -static int xnl_chk_attr(enum xnl_attr_t xnl_attr, struct genl_info *info, - unsigned short qidx, char *buf, int buflen) -{ - int rv = 0; - - if (!info->attrs[xnl_attr]) { - if (buf) { - rv += snprintf(buf, buflen, - "Missing attribute %s for qidx = %u\n", - xnl_attr_str[xnl_attr], - qidx); - } - rv = -1; - } - - return rv; -} - -static void xnl_extract_extra_config_attr(struct genl_info *info, - struct qdma_queue_conf *qconf) -{ - u32 f = nla_get_u32(info->attrs[XNL_ATTR_QFLAG]); - - qconf->desc_bypass = (f & XNL_F_DESC_BYPASS_EN) ? 1 : 0; - qconf->pfetch_bypass = (f & XNL_F_PFETCH_BYPASS_EN) ? 1 : 0; - qconf->pfetch_en = (f & XNL_F_PFETCH_EN) ? 1 : 0; - qconf->wb_status_en = (f & XNL_F_CMPL_STATUS_EN) ? 1 : 0; - qconf->cmpl_status_acc_en = (f & XNL_F_CMPL_STATUS_ACC_EN) ? 1 : 0; - qconf->cmpl_status_pend_chk = (f & XNL_F_CMPL_STATUS_PEND_CHK) ? 1 : 0; - qconf->fetch_credit = (f & XNL_F_FETCH_CREDIT) ? 1 : 0; - qconf->cmpl_stat_en = (f & XNL_F_CMPL_STATUS_DESC_EN) ? 1 : 0; - qconf->cmpl_en_intr = (f & XNL_F_C2H_CMPL_INTR_EN) ? 1 : 0; - qconf->cmpl_udd_en = (f & XNL_F_CMPL_UDD_EN) ? 1 : 0; - qconf->cmpl_ovf_chk_dis = (f & XNL_F_CMPT_OVF_CHK_DIS) ? 1 : 0; - - if (qconf->q_type == Q_CMPT) - qconf->cmpl_udd_en = 1; - - if (xnl_chk_attr(XNL_ATTR_QRNGSZ_IDX, info, qconf->qidx, NULL, 0) == 0) - qconf->desc_rng_sz_idx = qconf->cmpl_rng_sz_idx = - nla_get_u32(info->attrs[XNL_ATTR_QRNGSZ_IDX]); - if (xnl_chk_attr(XNL_ATTR_C2H_BUFSZ_IDX, info, - qconf->qidx, NULL, 0) == 0) - qconf->c2h_buf_sz_idx = - nla_get_u32(info->attrs[XNL_ATTR_C2H_BUFSZ_IDX]); - if (xnl_chk_attr(XNL_ATTR_CMPT_TIMER_IDX, info, - qconf->qidx, NULL, 0) == 0) - qconf->cmpl_timer_idx = - nla_get_u32(info->attrs[XNL_ATTR_CMPT_TIMER_IDX]); - if (xnl_chk_attr(XNL_ATTR_CMPT_CNTR_IDX, info, - qconf->qidx, NULL, 0) == 0) - qconf->cmpl_cnt_th_idx = - nla_get_u32(info->attrs[XNL_ATTR_CMPT_CNTR_IDX]); - if (xnl_chk_attr(XNL_ATTR_MM_CHANNEL, info, qconf->qidx, NULL, 0) == 0) - qconf->mm_channel = - nla_get_u32(info->attrs[XNL_ATTR_MM_CHANNEL]); - if (xnl_chk_attr(XNL_ATTR_CMPT_DESC_SIZE, - info, qconf->qidx, NULL, 0) == 0) - qconf->cmpl_desc_sz = - nla_get_u32(info->attrs[XNL_ATTR_CMPT_DESC_SIZE]); - if (xnl_chk_attr(XNL_ATTR_SW_DESC_SIZE, - info, qconf->qidx, NULL, 0) == 0) - qconf->sw_desc_sz = - nla_get_u32(info->attrs[XNL_ATTR_SW_DESC_SIZE]); - if (xnl_chk_attr(XNL_ATTR_PING_PONG_EN, - info, qconf->qidx, NULL, 0) == 0) - qconf->ping_pong_en = 1; - if (xnl_chk_attr(XNL_ATTR_APERTURE_SZ, - info, qconf->qidx, NULL, 0) == 0) - qconf->aperture_size = - nla_get_u32(info->attrs[XNL_ATTR_APERTURE_SZ]); - if (xnl_chk_attr(XNL_ATTR_CMPT_TRIG_MODE, info, - qconf->qidx, NULL, 0) == 0) - qconf->cmpl_trig_mode = - nla_get_u32(info->attrs[XNL_ATTR_CMPT_TRIG_MODE]); - else - qconf->cmpl_trig_mode = 1; -} - -static int xnl_dev_list(struct sk_buff *skb2, struct genl_info *info) -{ - char *buf; - int rv; - - if (info == NULL) - return -EINVAL; - - xnl_dump_attrs(info); - - buf = xnl_mem_alloc(XNL_RESP_BUFLEN_MAX, info); - if (!buf) - return -ENOMEM; - - rv = xpdev_list_dump(buf, XNL_RESP_BUFLEN_MAX); - if (rv < 0) { - pr_err("xpdev_list_dump() failed: %d", rv); - goto free_msg_buff; - } - - rv = xnl_respond_buffer(info, buf, strlen(buf), rv); - -free_msg_buff: - kfree(buf); - return rv; -} - -static int xnl_dev_info(struct sk_buff *skb2, struct genl_info *info) -{ - struct sk_buff *skb; - void *hdr; - struct xlnx_pci_dev *xpdev; - struct pci_dev *pdev; - struct qdma_dev_conf conf; - int rv; - - if (info == NULL) - return -EINVAL; - - xnl_dump_attrs(info); - - xpdev = xnl_rcv_check_xpdev(info); - if (!xpdev) - return -EINVAL; - pdev = xpdev->pdev; - - rv = qdma_device_get_config(xpdev->dev_hndl, &conf, NULL, 0); - if (rv < 0) - return rv; - - skb = xnl_msg_alloc(XNL_CMD_DEV_INFO, 0, &hdr, info); - if (!skb) - return -ENOMEM; - - rv = xnl_msg_add_attr_uint(skb, XNL_ATTR_PCI_BUS, - pdev->bus->number); - if (rv < 0) { - pr_err("xnl_msg_add_attr_uint() failed: %d", rv); - goto free_skb; - } - rv = xnl_msg_add_attr_uint(skb, XNL_ATTR_PCI_DEV, - PCI_SLOT(pdev->devfn)); - if (rv < 0) { - pr_err("xnl_msg_add_attr_uint() failed: %d", rv); - goto free_skb; - } - rv = xnl_msg_add_attr_uint(skb, XNL_ATTR_PCI_FUNC, - PCI_FUNC(pdev->devfn)); - if (rv < 0) { - pr_err("xnl_msg_add_attr_uint() failed: %d", rv); - goto free_skb; - } - rv = xnl_msg_add_attr_uint(skb, XNL_ATTR_DEV_CFG_BAR, - conf.bar_num_config); - if (rv < 0) { - pr_err("xnl_msg_add_attr_uint() failed: %d", rv); - goto free_skb; - } - rv = xnl_msg_add_attr_uint(skb, XNL_ATTR_DEV_USR_BAR, - conf.bar_num_user); - if (rv < 0) { - pr_err("xnl_msg_add_attr_uint() failed: %d", rv); - goto free_skb; - } - rv = xnl_msg_add_attr_uint(skb, XNL_ATTR_DEV_QSET_MAX, conf.qsets_max); - if (rv < 0) { - pr_err("xnl_msg_add_attr_uint() failed: %d", rv); - goto free_skb; - } - rv = xnl_msg_add_attr_uint(skb, XNL_ATTR_DEV_QSET_QBASE, - conf.qsets_base); - if (rv < 0) { - pr_err("xnl_msg_add_attr_uint() failed: %d", rv); - goto free_skb; - } - - rv = xnl_msg_send(skb, hdr, info); - - return rv; - -free_skb: - nlmsg_free(skb); - return rv; -} - -static int xnl_dev_version_capabilities(struct sk_buff *skb2, - struct genl_info *info) -{ - struct sk_buff *skb; - void *hdr; - struct xlnx_pci_dev *xpdev; - struct qdma_version_info ver_info; - struct qdma_dev_attributes dev_attr; - char buf[XNL_RESP_BUFLEN_MIN]; - int buflen = XNL_RESP_BUFLEN_MIN; - int rv = 0; - - if (info == NULL) - return -EINVAL; - - xnl_dump_attrs(info); - - xpdev = xnl_rcv_check_xpdev(info); - if (!xpdev) - return -EINVAL; - - skb = xnl_msg_alloc(XNL_CMD_DEV_CAP, 0, &hdr, info); - if (!skb) - return -ENOMEM; - - rv = qdma_device_version_info(xpdev->dev_hndl, &ver_info); - if (rv < 0) { - pr_err("qdma_device_version_info() failed: %d", rv); - goto free_skb; - } - - rv = qdma_device_capabilities_info(xpdev->dev_hndl, &dev_attr); - if (rv < 0) { - pr_err("qdma_device_capabilities_info() failed: %d", rv); - goto free_skb; - } - - rv = snprintf(buf + rv, buflen, - "=============Hardware Version============\n\n"); - rv += snprintf(buf + rv, buflen - rv, - "RTL Version : %s\n", ver_info.rtl_version_str); - rv += snprintf(buf + rv, - buflen - rv, - "Vivado ReleaseID : %s\n", - ver_info.vivado_release_str); - rv += snprintf(buf + rv, - buflen - rv, - "QDMA Device Type : %s\n", - ver_info.device_type_str); - - rv += snprintf(buf + rv, - buflen - rv, - "QDMA IP Type : %s\n", - ver_info.ip_str); - - rv += snprintf(buf + rv, - buflen - rv, - "============Software Version============\n\n"); - rv += snprintf(buf + rv, - buflen - rv, - "qdma driver version : %s\n\n", - DRV_MODULE_VERSION); - - rv = xnl_msg_add_attr_str(skb, XNL_ATTR_VERSION_INFO, buf); - if (rv != 0) { - pr_err("xnl_msg_add_attr_str() failed: %d", rv); - goto free_skb; - } - - rv = xnl_msg_add_attr_str(skb, XNL_ATTR_DEVICE_TYPE, - ver_info.device_type_str); - if (rv != 0) { - pr_err("xnl_msg_add_attr_str() failed: %d", rv); - goto free_skb; - } - - rv = xnl_msg_add_attr_str(skb, XNL_ATTR_IP_TYPE, ver_info.ip_str); - if (rv != 0) { - pr_err("xnl_msg_add_attr_str() failed: %d", rv); - goto free_skb; - } - - rv = xnl_msg_add_attr_uint(skb, XNL_ATTR_DEV_MM_ENABLE, dev_attr.mm_en); - if (rv < 0) { - pr_err("xnl_msg_add_attr_uint() failed: %d", rv); - goto free_skb; - } - - rv = xnl_msg_add_attr_uint(skb, XNL_ATTR_DEV_ST_ENABLE, dev_attr.st_en); - if (rv < 0) { - pr_err("xnl_msg_add_attr_uint() failed: %d", rv); - goto free_skb; - } - - rv = xnl_msg_add_attr_uint(skb, XNL_ATTR_DEV_MM_CMPT_ENABLE, - dev_attr.mm_cmpt_en); - if (rv < 0) { - pr_err("xnl_msg_add_attr_uint() failed: %d", rv); - goto free_skb; - } - - rv = xnl_msg_add_attr_uint(skb, XNL_ATTR_DEV_NUMQS, - dev_attr.num_qs); - if (rv < 0) { - pr_err("xnl_msg_add_attr_uint() failed: %d", rv); - goto free_skb; - } - - rv = xnl_msg_add_attr_uint(skb, XNL_ATTR_DEV_NUM_PFS, dev_attr.num_pfs); - if (rv < 0) { - pr_err("xnl_msg_add_attr_uint() failed: %d", rv); - goto free_skb; - } - - rv = xnl_msg_add_attr_uint(skb, XNL_ATTR_DEV_MM_CHANNEL_MAX, - dev_attr.mm_channel_max); - if (rv < 0) { - pr_err("xnl_msg_add_attr_uint() failed: %d", rv); - goto free_skb; - } - - rv = xnl_msg_add_attr_uint(skb, XNL_ATTR_DEV_MAILBOX_ENABLE, - dev_attr.mailbox_en); - if (rv < 0) { - pr_err("xnl_msg_add_attr_uint() failed: %d", rv); - goto free_skb; - } - - rv = xnl_msg_add_attr_uint(skb, XNL_ATTR_DEV_FLR_PRESENT, - dev_attr.flr_present); - if (rv < 0) { - pr_err("xnl_msg_add_attr_uint() failed: %d", rv); - goto free_skb; - } - - rv = xnl_msg_add_attr_uint(skb, XNL_ATTR_DEBUG_EN, - dev_attr.debug_mode); - if (rv < 0) { - pr_err("xnl_msg_add_attr_uint() failed: %d", rv); - goto free_skb; - } - - rv = xnl_msg_add_attr_uint(skb, XNL_ATTR_DESC_ENGINE_MODE, - dev_attr.desc_eng_mode); - if (rv < 0) { - pr_err("xnl_msg_add_attr_uint() failed: %d", rv); - goto free_skb; - } - - rv = xnl_msg_add_attr_data(skb, XNL_ATTR_DEV, - (void *)&dev_attr, sizeof(struct qdma_dev_attributes)); - if (rv != 0) { - pr_err("xnl_msg_add_attr_data() failed: %d", rv); - return rv; - } - - rv = xnl_msg_send(skb, hdr, info); - return rv; - -free_skb: - nlmsg_free(skb); - return rv; -} - -static int xnl_dev_stat(struct sk_buff *skb2, struct genl_info *info) -{ - struct sk_buff *skb; - void *hdr; - struct xlnx_pci_dev *xpdev; - int rv; - unsigned long long mmh2c_pkts = 0; - unsigned long long mmc2h_pkts = 0; - unsigned long long sth2c_pkts = 0; - unsigned long long stc2h_pkts = 0; - unsigned long long min_ping_pong_lat = 0; - unsigned long long max_ping_pong_lat = 0; - unsigned long long total_ping_pong_lat = 0; - unsigned long long avg_ping_pong_lat = 0; - unsigned int pkts; - - if (info == NULL) - return -EINVAL; - - xnl_dump_attrs(info); - - xpdev = xnl_rcv_check_xpdev(info); - if (!xpdev) - return -EINVAL; - - skb = xnl_msg_alloc(XNL_CMD_DEV_STAT, 0, &hdr, info); - if (!skb) - return -ENOMEM; - - qdma_device_get_mmh2c_pkts(xpdev->dev_hndl, &mmh2c_pkts); - qdma_device_get_mmc2h_pkts(xpdev->dev_hndl, &mmc2h_pkts); - qdma_device_get_sth2c_pkts(xpdev->dev_hndl, &sth2c_pkts); - qdma_device_get_stc2h_pkts(xpdev->dev_hndl, &stc2h_pkts); - qdma_device_get_ping_pong_min_lat(xpdev->dev_hndl, - &min_ping_pong_lat); - qdma_device_get_ping_pong_max_lat(xpdev->dev_hndl, - &max_ping_pong_lat); - qdma_device_get_ping_pong_tot_lat(xpdev->dev_hndl, - &total_ping_pong_lat); - - pkts = mmh2c_pkts; - rv = xnl_msg_add_attr_uint(skb, XNL_ATTR_DEV_STAT_MMH2C_PKTS1, pkts); - if (rv < 0) { - pr_err("xnl_msg_add_attr_uint() failed: %d", rv); - return rv; - } - pkts = (mmh2c_pkts >> 32); - rv = xnl_msg_add_attr_uint(skb, XNL_ATTR_DEV_STAT_MMH2C_PKTS2, pkts); - if (rv < 0) { - pr_err("xnl_msg_add_attr_uint() failed: %d", rv); - return rv; - } - pkts = mmc2h_pkts; - rv = xnl_msg_add_attr_uint(skb, XNL_ATTR_DEV_STAT_MMC2H_PKTS1, pkts); - if (rv < 0) { - pr_err("xnl_msg_add_attr_uint() failed: %d", rv); - return rv; - } - pkts = (mmc2h_pkts >> 32); - rv = xnl_msg_add_attr_uint(skb, XNL_ATTR_DEV_STAT_MMC2H_PKTS2, pkts); - if (rv < 0) { - pr_err("xnl_msg_add_attr_uint() failed: %d", rv); - return rv; - } - pkts = sth2c_pkts; - rv = xnl_msg_add_attr_uint(skb, XNL_ATTR_DEV_STAT_STH2C_PKTS1, pkts); - if (rv < 0) { - pr_err("xnl_msg_add_attr_uint() failed: %d", rv); - return rv; - } - pkts = (sth2c_pkts >> 32); - rv = xnl_msg_add_attr_uint(skb, XNL_ATTR_DEV_STAT_STH2C_PKTS2, pkts); - if (rv < 0) { - pr_err("xnl_msg_add_attr_uint() failed: %d", rv); - return rv; - } - pkts = stc2h_pkts; - rv = xnl_msg_add_attr_uint(skb, XNL_ATTR_DEV_STAT_STC2H_PKTS1, pkts); - if (rv < 0) { - pr_err("xnl_msg_add_attr_uint() failed: %d", rv); - return rv; - } - pkts = (stc2h_pkts >> 32); - rv = xnl_msg_add_attr_uint(skb, XNL_ATTR_DEV_STAT_STC2H_PKTS2, pkts); - if (rv < 0) { - pr_err("xnl_msg_add_attr_uint() failed: %d", rv); - return rv; - } - pkts = min_ping_pong_lat; - rv = xnl_msg_add_attr_uint(skb, - XNL_ATTR_DEV_STAT_PING_PONG_LATMIN1, pkts); - if (rv < 0) { - pr_err("xnl_msg_add_attr_uint() failed: %d", rv); - return rv; - } - pkts = (min_ping_pong_lat >> 32); - rv = xnl_msg_add_attr_uint(skb, - XNL_ATTR_DEV_STAT_PING_PONG_LATMIN2, pkts); - if (rv < 0) { - pr_err("xnl_msg_add_attr_uint() failed: %d", rv); - return rv; - } - pkts = min_ping_pong_lat; - rv = xnl_msg_add_attr_uint(skb, - XNL_ATTR_DEV_STAT_PING_PONG_LATMIN1, pkts); - if (rv < 0) { - pr_err("xnl_msg_add_attr_uint() failed: %d", rv); - return rv; - } - pkts = (min_ping_pong_lat >> 32); - rv = xnl_msg_add_attr_uint(skb, - XNL_ATTR_DEV_STAT_PING_PONG_LATMIN2, pkts); - if (rv < 0) { - pr_err("xnl_msg_add_attr_uint() failed: %d", rv); - return rv; - } - pkts = max_ping_pong_lat; - rv = xnl_msg_add_attr_uint(skb, - XNL_ATTR_DEV_STAT_PING_PONG_LATMAX1, pkts); - if (rv < 0) { - pr_err("xnl_msg_add_attr_uint() failed: %d", rv); - return rv; - } - pkts = (max_ping_pong_lat >> 32); - rv = xnl_msg_add_attr_uint(skb, - XNL_ATTR_DEV_STAT_PING_PONG_LATMAX2, pkts); - if (rv < 0) { - pr_err("xnl_msg_add_attr_uint() failed: %d", rv); - return rv; - } - - if (stc2h_pkts != 0) - avg_ping_pong_lat = total_ping_pong_lat / stc2h_pkts; - else - pr_err("No C2H packets to calculate avg\n"); - - pkts = avg_ping_pong_lat; - rv = xnl_msg_add_attr_uint(skb, - XNL_ATTR_DEV_STAT_PING_PONG_LATAVG1, pkts); - if (rv < 0) { - pr_err("xnl_msg_add_attr_uint() failed: %d", rv); - return rv; - } - pkts = (avg_ping_pong_lat >> 32); - rv = xnl_msg_add_attr_uint(skb, - XNL_ATTR_DEV_STAT_PING_PONG_LATAVG2, pkts); - if (rv < 0) { - pr_err("xnl_msg_add_attr_uint() failed: %d", rv); - return rv; - } - rv = xnl_msg_send(skb, hdr, info); - - return rv; -} - -static int xnl_dev_stat_clear(struct sk_buff *skb2, struct genl_info *info) -{ - struct xlnx_pci_dev *xpdev; - int rv; - char *buf; - - if (info == NULL) - return -EINVAL; - - xnl_dump_attrs(info); - - xpdev = xnl_rcv_check_xpdev(info); - if (!xpdev) - return -EINVAL; - buf = xnl_mem_alloc(XNL_RESP_BUFLEN_MIN, info); - if (!buf) - return -ENOMEM; - - qdma_device_clear_stats(xpdev->dev_hndl); - - buf[0] = '\0'; - - rv = xnl_respond_buffer(info, buf, XNL_RESP_BUFLEN_MAX, 0); - - kfree(buf); - return rv; -} - - - -static int xnl_get_queue_state(struct sk_buff *skb2, struct genl_info *info) -{ - struct xlnx_pci_dev *xpdev; - struct qdma_queue_conf qconf; - char buf[XNL_RESP_BUFLEN_MIN]; - struct xlnx_qdata *qdata; - int rv = 0; - unsigned char is_qp; - unsigned int q_flags; - struct sk_buff *skb; - void *hdr; - struct qdma_q_state qstate; - - if (info == NULL) - return 0; - - xnl_dump_attrs(info); - - skb = xnl_msg_alloc(XNL_CMD_DEV_STAT, 0, &hdr, info); - if (!skb) - return -ENOMEM; - - - xpdev = xnl_rcv_check_xpdev(info); - if (!xpdev) { - nlmsg_free(skb); - return -EINVAL; - } - - rv = qconf_get(&qconf, info, buf, XNL_RESP_BUFLEN_MIN, &is_qp); - if (rv < 0) { - nlmsg_free(skb); - return -EINVAL; - } - if (is_qp) - return -EINVAL; - - qdata = xnl_rcv_check_qidx(info, xpdev, &qconf, buf, - XNL_RESP_BUFLEN_MIN); - if (!qdata) { - nlmsg_free(skb); - return -EINVAL; - } - - rv = qdma_get_queue_state(xpdev->dev_hndl, qdata->qhndl, &qstate, - buf, XNL_RESP_BUFLEN_MIN); - if (rv < 0) { - xnl_respond_buffer(info, buf, XNL_RESP_BUFLEN_MAX, rv); - nlmsg_free(skb); - pr_err("qdma_get_queue_state() failed: %d", rv); - return rv; - } - - q_flags = 0; - - if (qstate.st) - q_flags |= XNL_F_QMODE_ST; - else - q_flags |= XNL_F_QMODE_MM; - - - if (qstate.q_type == Q_C2H) - q_flags |= XNL_F_QDIR_C2H; - else if (qstate.q_type == Q_H2C) - q_flags |= XNL_F_QDIR_H2C; - else - q_flags |= XNL_F_Q_CMPL; - - rv = xnl_msg_add_attr_uint(skb, XNL_ATTR_QFLAG, q_flags); - if (rv < 0) { - nlmsg_free(skb); - pr_err("xnl_msg_add_attr_uint() failed: %d", rv); - return rv; - } - - rv = xnl_msg_add_attr_uint(skb, XNL_ATTR_QIDX, qstate.qidx); - if (rv < 0) { - nlmsg_free(skb); - pr_err("xnl_msg_add_attr_uint() failed: %d", rv); - return rv; - } - - rv = xnl_msg_add_attr_uint(skb, XNL_ATTR_Q_STATE, qstate.qstate); - if (rv < 0) { - nlmsg_free(skb); - pr_err("xnl_msg_add_attr_uint() failed: %d", rv); - return rv; - } - - - rv = xnl_msg_send(skb, hdr, info); - - return rv; - -} - -static int xnl_q_list(struct sk_buff *skb2, struct genl_info *info) -{ - struct xlnx_pci_dev *xpdev; - char *buf; - int rv = 0; - char ebuf[XNL_RESP_BUFLEN_MIN]; - struct qdma_queue_conf qconf; - unsigned char is_qp; - uint32_t qmax = 0; - uint32_t buflen = 0, max_buflen = 0; - struct qdma_queue_count q_count; - unsigned int qidx, num_q; - struct xlnx_qdata *qdata; - - if (info == NULL) - return -EINVAL; - - xnl_dump_attrs(info); - - xpdev = xnl_rcv_check_xpdev(info); - if (!xpdev) - return -EINVAL; - - buf = xnl_mem_alloc(XNL_RESP_BUFLEN_MIN, info); - if (!buf) - return -ENOMEM; - buflen = XNL_RESP_BUFLEN_MIN; - rv = qconf_get(&qconf, info, ebuf, XNL_RESP_BUFLEN_MIN, &is_qp); - if (rv < 0) - return rv; - - qidx = qconf.qidx; - num_q = nla_get_u32(info->attrs[XNL_ATTR_NUM_Q]); - - rv = qdma_get_queue_count(xpdev->dev_hndl, &q_count, buf, buflen); - if (rv < 0) { - rv += snprintf(buf, XNL_RESP_BUFLEN_MIN, - "Failed to get queue count\n"); - goto send_rsp; - } - - qmax = q_count.h2c_qcnt + q_count.c2h_qcnt; - if (!qmax) { - rv += snprintf(buf, 8, "Zero Qs\n\n"); - goto send_rsp; - } - - qdata = xnl_rcv_check_qidx(info, xpdev, &qconf, buf, buflen); - if (!qdata) - goto send_rsp; - - num_q = nla_get_u32(info->attrs[XNL_ATTR_NUM_Q]); - - if (num_q > QDMA_Q_DUMP_MAX_QUEUES) { - pr_err("Can not dump more than %d queues\n", - QDMA_Q_DUMP_MAX_QUEUES); - rv += snprintf(buf, 40, "Can not dump more than %d queues\n", - QDMA_Q_DUMP_MAX_QUEUES); - goto send_rsp; - } - - kfree(buf); - max_buflen = (num_q * 2 * QDMA_Q_LIST_LINE_SZ); - buf = xnl_mem_alloc(max_buflen, info); - if (!buf) - return -ENOMEM; - - buflen = max_buflen; - rv = qdma_queue_list(xpdev->dev_hndl, qidx, num_q, buf, buflen); - if (rv < 0) { - pr_err("qdma_queue_list() failed: %d", rv); - goto send_rsp; - } - -send_rsp: - rv = xnl_respond_buffer(info, buf, max_buflen, rv); - kfree(buf); - return rv; -} - -static int xnl_q_add(struct sk_buff *skb2, struct genl_info *info) -{ - struct xlnx_pci_dev *xpdev = NULL; - struct qdma_queue_conf qconf; - char *buf, *cur, *end; - int rv = 0; - int rv2 = 0; - unsigned char is_qp; - unsigned int num_q; - unsigned int i; - unsigned short qidx; - unsigned char dir; - int buf_len = XNL_RESP_BUFLEN_MAX; - - if (info == NULL) - return -EINVAL; - - xnl_dump_attrs(info); - - xpdev = xnl_rcv_check_xpdev(info); - if (!xpdev) - return -EINVAL; - - if (info->attrs[XNL_ATTR_RSP_BUF_LEN]) - buf_len = nla_get_u32(info->attrs[XNL_ATTR_RSP_BUF_LEN]); - - buf = xnl_mem_alloc(buf_len, info); - if (!buf) - return -ENOMEM; - cur = buf; - end = buf + buf_len; - - if (unlikely(!qdma_get_qmax(xpdev->dev_hndl))) { - pr_info("0 sized Qs\n"); - rv += snprintf(cur, end - cur, "Zero Qs\n"); - goto send_resp; - } - rv = qconf_get(&qconf, info, cur, end - cur, &is_qp); - if (rv < 0) - goto free_buf; - - qidx = qconf.qidx; - - rv = xnl_chk_attr(XNL_ATTR_NUM_Q, info, qidx, cur, end - cur); - if (rv < 0) - goto send_resp; - num_q = nla_get_u32(info->attrs[XNL_ATTR_NUM_Q]); - - if (qconf.q_type > Q_CMPT) { - pr_err("Invalid q type received"); - rv += snprintf(cur, end - cur, "Invalid q type received"); - goto send_resp; - } - - dir = qconf.q_type; - for (i = 0; i < num_q; i++) { - if (qconf.q_type != Q_CMPT) - qconf.q_type = dir; -add_q: - if (qidx != QDMA_QUEUE_IDX_INVALID) - qconf.qidx = qidx + i; - rv = xpdev_queue_add(xpdev, &qconf, cur, end - cur); - if (rv < 0) { - pr_err("xpdev_queue_add() failed: %d\n", rv); - goto send_resp; - } - cur = buf + strlen(buf); - if (qconf.q_type != Q_CMPT) { - if (is_qp && (dir == qconf.q_type)) { - qconf.q_type = (~qconf.q_type) & 0x1; - goto add_q; - } - } - } -/* Suppress Q additions prints if num_q's greater than 2048. - * And print only consolidated Q's added, to overcome attr failure. - * TODO: This is a workaround. Need to comeup with proper fix. - */ - if (num_q > 2048) { - memset(buf, 0, strlen(buf) + 1); - snprintf(buf, 25, "Added %u Queues.\n", i); - } else { - cur += snprintf(cur, end - cur, "Added %u Queues.\n", i); - } - -send_resp: - rv2 = xnl_respond_buffer(info, buf, strlen(buf), rv); -free_buf: - kfree(buf); - return rv < 0 ? rv : rv2; -} - -static int xnl_q_buf_idx_get(struct xlnx_pci_dev *xpdev) -{ - struct global_csr_conf csr; - int i, rv; - - memset(&csr, 0, sizeof(struct global_csr_conf)); - rv = qdma_global_csr_get(xpdev->dev_hndl, 0, - QDMA_GLOBAL_CSR_ARRAY_SZ, - &csr); - if (rv < 0) - return 0; - - for (i = 0; i < QDMA_GLOBAL_CSR_ARRAY_SZ; i++) { - if (csr.c2h_buf_sz[i] == QDMA_C2H_DEFAULT_BUF_SZ) - return i; - } - - return 0; -} - -static int xnl_q_start(struct sk_buff *skb2, struct genl_info *info) -{ - struct xlnx_pci_dev *xpdev; - struct qdma_queue_conf qconf; - struct qdma_queue_conf qconf_old; - char buf[XNL_RESP_BUFLEN_MIN]; - struct xlnx_qdata *qdata; - int rv = 0; - unsigned char is_qp; - unsigned short num_q; - unsigned int i; - unsigned short qidx; - unsigned char dir; - unsigned char is_bufsz_idx = 1; - - if (info == NULL) - return 0; - - xnl_dump_attrs(info); - - xpdev = xnl_rcv_check_xpdev(info); - if (!xpdev) - return 0; - - if (unlikely(!qdma_get_qmax(xpdev->dev_hndl))) { - rv += snprintf(buf, 8, "Zero Qs\n"); - goto send_resp; - } - rv = qconf_get(&qconf, info, buf, XNL_RESP_BUFLEN_MIN, &is_qp); - if (rv < 0) - goto send_resp; - - qidx = qconf.qidx; - - rv = xnl_chk_attr(XNL_ATTR_NUM_Q, info, qidx, buf, XNL_RESP_BUFLEN_MIN); - if (rv < 0) - goto send_resp; - num_q = nla_get_u32(info->attrs[XNL_ATTR_NUM_Q]); - - xnl_extract_extra_config_attr(info, &qconf); - - if (qconf.st && (qconf.q_type == Q_CMPT)) { - rv += snprintf(buf, 40, "MM CMPL is valid only for MM Mode"); - goto send_resp; - } - - if (qconf.q_type > Q_CMPT) { - pr_err("Invalid q type received"); - rv += snprintf(buf, 40, "Invalid q type received"); - goto send_resp; - } - - if (!info->attrs[XNL_ATTR_C2H_BUFSZ_IDX]) - is_bufsz_idx = 0; - - if (!info->attrs[XNL_ATTR_MM_CHANNEL]) - qconf.mm_channel = 0; - - dir = qconf.q_type; - for (i = qidx; i < (qidx + num_q); i++) { - if (qconf.q_type != Q_CMPT) - qconf.q_type = dir; -reconfig: - qconf.qidx = i; - qdata = xnl_rcv_check_qidx(info, xpdev, &qconf, buf, - XNL_RESP_BUFLEN_MIN); - if (!qdata) - goto send_resp; - rv = qdma_queue_get_config(xpdev->dev_hndl, qdata->qhndl, - &qconf_old, buf, XNL_RESP_BUFLEN_MIN); - if (rv < 0) - goto send_resp; - - if (qconf.q_type != Q_CMPT) { - if (qconf_old.st && qconf_old.q_type && !is_bufsz_idx) - qconf.c2h_buf_sz_idx = xnl_q_buf_idx_get(xpdev); - } - rv = qdma_queue_config(xpdev->dev_hndl, qdata->qhndl, - &qconf, buf, XNL_RESP_BUFLEN_MIN); - if (rv < 0) { - pr_err("qdma_queue_config failed: %d", rv); - goto send_resp; - } - if (qconf.q_type != Q_CMPT) { - if (is_qp && (dir == qconf.q_type)) { - qconf.q_type = (~qconf.q_type) & 0x1; - goto reconfig; - } - } - } - - rv = xpdev_nl_queue_start(xpdev, info, is_qp, qconf.q_type, - qidx, num_q); - if (rv < 0) { - snprintf(buf, XNL_RESP_BUFLEN_MIN, "qdma%05x OOM.\n", - xpdev->idx); - goto send_resp; - } - - return 0; - -send_resp: - rv = xnl_respond_buffer(info, buf, XNL_RESP_BUFLEN_MIN, rv); - - return rv; -} - -static int xnl_q_stop(struct sk_buff *skb2, struct genl_info *info) -{ - struct xlnx_pci_dev *xpdev; - struct qdma_queue_conf qconf; - char buf[XNL_RESP_BUFLEN_MIN]; - struct xlnx_qdata *qdata; - int rv = 0, rv2 = 0; - unsigned char is_qp; - unsigned short num_q; - unsigned int i; - unsigned short qidx; - unsigned char dir; - - if (info == NULL) - return 0; - - xnl_dump_attrs(info); - - xpdev = xnl_rcv_check_xpdev(info); - if (!xpdev) - return 0; - - if (unlikely(!qdma_get_qmax(xpdev->dev_hndl))) { - rv += snprintf(buf, 8, "Zero Qs\n"); - goto send_resp; - } - rv = qconf_get(&qconf, info, buf, XNL_RESP_BUFLEN_MIN, &is_qp); - if (rv < 0) - goto send_resp; - - if (!info->attrs[XNL_ATTR_NUM_Q]) { - pr_warn("Missing attribute 'XNL_ATTR_NUM_Q'"); - return -1; - } - - if (qconf.q_type > Q_CMPT) { - pr_err("Invalid q type received"); - rv += snprintf(buf, 40, "Invalid q type received"); - goto send_resp; - } - - num_q = nla_get_u32(info->attrs[XNL_ATTR_NUM_Q]); - - qidx = qconf.qidx; - dir = qconf.q_type; - for (i = qidx; i < (qidx + num_q); i++) { - if (qconf.q_type != Q_CMPT) - qconf.q_type = dir; -stop_q: - qconf.qidx = i; - qdata = xnl_rcv_check_qidx(info, xpdev, &qconf, buf, - XNL_RESP_BUFLEN_MIN); - if (!qdata) - goto send_resp; - rv = qdma_queue_stop(xpdev->dev_hndl, qdata->qhndl, - buf, XNL_RESP_BUFLEN_MIN); - if (rv < 0) { - pr_err("qdma_queue_stop() failed: %d", rv); - goto send_resp; - } - if (qconf.q_type != Q_CMPT) { - if (is_qp && (dir == qconf.q_type)) { - qconf.q_type = (~qconf.q_type) & 0x1; - goto stop_q; - } - } - } - rv2 = snprintf(buf + rv, XNL_RESP_BUFLEN_MIN - rv, - "Stopped Queues %u -> %u.\n", qidx, i - 1); -send_resp: - rv = xnl_respond_buffer(info, buf, XNL_RESP_BUFLEN_MIN, rv); - return rv; -} - -static int xnl_q_del(struct sk_buff *skb2, struct genl_info *info) -{ - struct xlnx_pci_dev *xpdev; - struct qdma_queue_conf qconf; - char buf[XNL_RESP_BUFLEN_MIN]; - int rv = 0, rv2 = 0; - unsigned char is_qp; - unsigned short num_q; - unsigned int i; - unsigned short qidx; - unsigned char dir; - - if (info == NULL) - return 0; - - xnl_dump_attrs(info); - - xpdev = xnl_rcv_check_xpdev(info); - if (!xpdev) - return 0; - - if (unlikely(!qdma_get_qmax(xpdev->dev_hndl))) { - rv += snprintf(buf, 8, "Zero Qs\n"); - goto send_resp; - } - rv = qconf_get(&qconf, info, buf, XNL_RESP_BUFLEN_MIN, &is_qp); - if (rv < 0) - goto send_resp; - - if (qconf.q_type > Q_CMPT) { - pr_err("Invalid q type received"); - rv += snprintf(buf, 40, "Invalid q type received"); - goto send_resp; - } - - if (!info->attrs[XNL_ATTR_NUM_Q]) { - pr_warn("Missing attribute 'XNL_ATTR_NUM_Q'"); - return -1; - } - num_q = nla_get_u32(info->attrs[XNL_ATTR_NUM_Q]); - - qidx = qconf.qidx; - - dir = qconf.q_type; - for (i = qidx; i < (qidx + num_q); i++) { - if (qconf.q_type != Q_CMPT) - qconf.q_type = dir; -del_q: - qconf.qidx = i; - rv = xpdev_queue_delete(xpdev, qconf.qidx, qconf.q_type, - buf, XNL_RESP_BUFLEN_MIN); - if (rv < 0) { - pr_err("xpdev_queue_delete() failed: %d", rv); - goto send_resp; - } - if (qconf.q_type != Q_CMPT) { - if (is_qp && (dir == qconf.q_type)) { - qconf.q_type = (~qconf.q_type) & 0x1; - goto del_q; - } - } - } - rv2 = snprintf(buf + rv, XNL_RESP_BUFLEN_MIN - rv, - "Deleted Queues %u -> %u.\n", qidx, i - 1); -send_resp: - rv = xnl_respond_buffer(info, buf, XNL_RESP_BUFLEN_MIN, rv); - return rv; -} - -static int xnl_config_reg_dump(struct sk_buff *skb2, struct genl_info *info) -{ - struct xlnx_pci_dev *xpdev; - char *buf; - int buf_len = XNL_RESP_BUFLEN_MAX; - int rv = 0; - - if (info == NULL) - return 0; - - xnl_dump_attrs(info); - - xpdev = xnl_rcv_check_xpdev(info); - if (!xpdev) - return 0; - - if (info->attrs[XNL_ATTR_RSP_BUF_LEN]) - buf_len = nla_get_u32(info->attrs[XNL_ATTR_RSP_BUF_LEN]); - buf = xnl_mem_alloc(buf_len, info); - if (!buf) - return -ENOMEM; - - qdma_config_reg_dump(xpdev->dev_hndl, buf, buf_len); - - rv = xnl_respond_buffer(info, buf, buf_len, rv); - - kfree(buf); - return rv; -} - -static int xnl_config_reg_info_dump - (struct sk_buff *skb2, struct genl_info *info) -{ - struct xlnx_pci_dev *xpdev; - char *buf; - int buf_len = XNL_RESP_BUFLEN_MAX; - int rv = 0; - uint32_t reg_addr = 0; - uint32_t num_regs = 0; - - if (info == NULL) - return 0; - - xnl_dump_attrs(info); - - xpdev = xnl_rcv_check_xpdev(info); - if (!xpdev) - return 0; - - if (info->attrs[XNL_ATTR_RSP_BUF_LEN]) - buf_len = nla_get_u32(info->attrs[XNL_ATTR_RSP_BUF_LEN]); - - if (info->attrs[XNL_ATTR_REG_ADDR]) - reg_addr = nla_get_u32(info->attrs[XNL_ATTR_REG_ADDR]); - - if (info->attrs[XNL_ATTR_NUM_REGS]) - num_regs = nla_get_u32(info->attrs[XNL_ATTR_NUM_REGS]); - - buf = xnl_mem_alloc(buf_len, info); - if (!buf) - return -ENOMEM; - - qdma_config_reg_info_dump(xpdev->dev_hndl, - reg_addr, num_regs, buf, buf_len); - - rv = xnl_respond_buffer(info, buf, buf_len, rv); - - kfree(buf); - return rv; -} - - -static int xnl_q_dump(struct sk_buff *skb2, struct genl_info *info) -{ - struct xlnx_pci_dev *xpdev; - struct qdma_queue_conf qconf; - struct xlnx_qdata *qdata; - char *buf; - char ebuf[XNL_RESP_BUFLEN_MIN]; - int rv; - unsigned char is_qp; - unsigned int num_q; - unsigned int i; - unsigned short qidx; - unsigned char dir; - int buf_len = XNL_RESP_BUFLEN_MAX; - unsigned int buf_idx = 0; - char banner[DUMP_LINE_SZ]; - - if (info == NULL) - return 0; - - xnl_dump_attrs(info); - xpdev = xnl_rcv_check_xpdev(info); - if (!xpdev) - return 0; - - rv = qconf_get(&qconf, info, ebuf, XNL_RESP_BUFLEN_MIN, &is_qp); - if (rv < 0) - return rv; - - if (info->attrs[XNL_ATTR_RSP_BUF_LEN]) - buf_len = nla_get_u32(info->attrs[XNL_ATTR_RSP_BUF_LEN]); - - buf = xnl_mem_alloc(buf_len, info); - if (!buf) - return -ENOMEM; - - if (qconf.q_type > Q_CMPT) { - pr_err("Invalid q type received"); - rv += snprintf(buf, 40, "Invalid q type received"); - goto send_resp; - } - - if (!info->attrs[XNL_ATTR_NUM_Q]) { - pr_warn("Missing attribute 'XNL_ATTR_NUM_Q'"); - kfree(buf); - return -1; - } - num_q = nla_get_u32(info->attrs[XNL_ATTR_NUM_Q]); - - if (num_q > QDMA_Q_DUMP_MAX_QUEUES) { - pr_err("Can not dump more than %d queues\n", - QDMA_Q_DUMP_MAX_QUEUES); - rv += snprintf(buf, 40, "Can not dump more than %d queues\n", - QDMA_Q_DUMP_MAX_QUEUES); - goto send_resp; - } - kfree(buf); - buf_len = (num_q * QDMA_Q_DUMP_LINE_SZ); - buf = xnl_mem_alloc(buf_len, info); - if (!buf) - return -ENOMEM; - - qidx = qconf.qidx; - dir = qconf.q_type; - - for (i = 0; i < DUMP_LINE_SZ - 5; i++) - snprintf(banner + i, DUMP_LINE_SZ - 5, "*"); - - for (i = qidx; i < (qidx + num_q); i++) { - if (qconf.q_type != Q_CMPT) - qconf.q_type = dir; - -dump_q: - qconf.qidx = i; - qdata = xnl_rcv_check_qidx(info, xpdev, &qconf, buf + buf_idx, - buf_len - buf_idx); - if (!qdata) - goto send_resp; - - buf_idx += snprintf(buf + buf_idx, - DUMP_LINE_SZ, "\n%s", banner); - - buf_idx += snprintf(buf + buf_idx, buf_len - buf_idx, -#ifndef __QDMA_VF__ - "\n%40s qdma%05x %s QID# %u\n", -#else - "\n%40s qdmavf%05x %s QID# %u\n", -#endif - "Context Dump for", - xpdev->idx, - q_type_list[qconf.q_type].name, - qconf.qidx); - - buf_idx += snprintf(buf + buf_idx, - buf_len - buf_idx, "\n%s\n", banner); - - rv = qdma_queue_dump(xpdev->dev_hndl, qdata->qhndl, - buf + buf_idx, - buf_len - buf_idx); - buf_idx = strlen(buf); - if (rv < 0) { - pr_err("qdma_queue_dump() failed: %d", rv); - goto send_resp; - } - if (qconf.q_type != Q_CMPT) { - if (is_qp && (dir == qconf.q_type)) { - qconf.q_type = (~qconf.q_type) & 0x1; - goto dump_q; - } - } - } - rv = snprintf(buf + buf_idx, buf_len - buf_idx, - "Dumped Queues %u -> %u.\n", qidx, i - 1); - buf_idx += rv; -send_resp: - rv = xnl_respond_buffer(info, buf, buf_len, rv); - kfree(buf); - return rv; -} - -static int xnl_q_dump_desc(struct sk_buff *skb2, struct genl_info *info) -{ - struct xlnx_pci_dev *xpdev; - struct qdma_queue_conf qconf; - struct xlnx_qdata *qdata; - u32 v1; - u32 v2; - char *buf; - char ebuf[XNL_RESP_BUFLEN_MIN]; - int rv; - unsigned char is_qp; - unsigned int num_q; - unsigned int i; - unsigned short qidx; - unsigned char dir; - int buf_len = XNL_RESP_BUFLEN_MAX; - unsigned int buf_idx = 0; - - if (info == NULL) - return 0; - - xnl_dump_attrs(info); - - v1 = nla_get_u32(info->attrs[XNL_ATTR_RANGE_START]); - v2 = nla_get_u32(info->attrs[XNL_ATTR_RANGE_END]); - - xpdev = xnl_rcv_check_xpdev(info); - if (!xpdev) - return 0; - - if (unlikely(!qdma_get_qmax(xpdev->dev_hndl))) - return 0; - rv = qconf_get(&qconf, info, ebuf, XNL_RESP_BUFLEN_MIN, &is_qp); - if (rv < 0) - return rv; - - if (info->attrs[XNL_ATTR_RSP_BUF_LEN]) - buf_len = nla_get_u32(info->attrs[XNL_ATTR_RSP_BUF_LEN]); - - buf = xnl_mem_alloc(buf_len, info); - if (!buf) { - rv = snprintf(ebuf, XNL_RESP_BUFLEN_MIN, - "%s OOM %d.\n", - __func__, buf_len); - xnl_respond_buffer(info, ebuf, XNL_RESP_BUFLEN_MIN, rv); - return -ENOMEM; - } - - if (!info->attrs[XNL_ATTR_NUM_Q]) { - pr_warn("Missing attribute 'XNL_ATTR_NUM_Q'"); - return -1; - } - num_q = nla_get_u32(info->attrs[XNL_ATTR_NUM_Q]); - - - if (qconf.q_type > Q_CMPT) { - pr_err("Invalid q type received"); - rv += snprintf(buf, 40, "Invalid q type received"); - goto send_resp; - } - - qidx = qconf.qidx; - dir = qconf.q_type; - for (i = qidx; i < (qidx + num_q); i++) { - qconf.q_type = dir; -dump_q: - qconf.qidx = i; - qdata = xnl_rcv_check_qidx(info, xpdev, &qconf, buf + buf_idx, - buf_len - buf_idx); - if (!qdata) - goto send_resp; - rv = qdma_queue_dump_desc(xpdev->dev_hndl, - qdata->qhndl, v1, v2, - buf + buf_idx, buf_len - buf_idx); - buf_idx = strlen(buf); - - if (rv < 0) { - pr_err("qdma_queue_dump_desc() failed: %d", rv); - goto send_resp; - } - if (is_qp && (dir == qconf.q_type)) { - qconf.q_type = (~qconf.q_type) & 0x1; - goto dump_q; - } - } - - rv = snprintf(buf + buf_idx, buf_len - buf_idx, - "Dumped descs of queues %u -> %u.\n", - qidx, i - 1); -send_resp: - rv = xnl_respond_buffer(info, buf, buf_len, rv); - - kfree(buf); - return rv; -} - -static int xnl_q_dump_cmpt(struct sk_buff *skb2, struct genl_info *info) -{ - struct xlnx_pci_dev *xpdev; - struct qdma_queue_conf qconf; - struct xlnx_qdata *qdata; - u32 v1; - u32 v2; - char *buf; - char ebuf[XNL_RESP_BUFLEN_MIN]; - int rv; - unsigned char is_qp; - unsigned int num_q; - unsigned int i; - unsigned short qidx; - unsigned char dir; - int buf_len = XNL_RESP_BUFLEN_MAX; - unsigned int buf_idx = 0; - - if (info == NULL) - return 0; - - xnl_dump_attrs(info); - - v1 = nla_get_u32(info->attrs[XNL_ATTR_RANGE_START]); - v2 = nla_get_u32(info->attrs[XNL_ATTR_RANGE_END]); - - xpdev = xnl_rcv_check_xpdev(info); - if (!xpdev) - return 0; - - if (unlikely(!qdma_get_qmax(xpdev->dev_hndl))) - return 0; - - rv = qconf_get(&qconf, info, ebuf, XNL_RESP_BUFLEN_MIN, &is_qp); - if (rv < 0) - return rv; - - if (info->attrs[XNL_ATTR_RSP_BUF_LEN]) - buf_len = nla_get_u32(info->attrs[XNL_ATTR_RSP_BUF_LEN]); - - buf = xnl_mem_alloc(buf_len, info); - if (!buf) { - rv = snprintf(ebuf, XNL_RESP_BUFLEN_MIN, - "%s OOM %d.\n", - __func__, buf_len); - xnl_respond_buffer(info, ebuf, XNL_RESP_BUFLEN_MIN, rv); - return -ENOMEM; - } - - if (!info->attrs[XNL_ATTR_NUM_Q]) { - pr_warn("Missing attribute 'XNL_ATTR_NUM_Q'"); - return -1; - } - num_q = nla_get_u32(info->attrs[XNL_ATTR_NUM_Q]); - - - if (qconf.q_type > Q_CMPT) { - pr_err("Invalid q type received"); - rv += snprintf(buf, 40, "Invalid q type received"); - goto send_resp; - } - - qidx = qconf.qidx; - - dir = qconf.q_type; - for (i = qidx; i < (qidx + num_q); i++) { - if (qconf.q_type != Q_CMPT) - qconf.q_type = dir; -dump_q: - qconf.qidx = i; - qdata = xnl_rcv_check_qidx(info, xpdev, &qconf, buf + buf_idx, - buf_len - buf_idx); - if (!qdata) - goto send_resp; - rv = qdma_queue_dump_cmpt(xpdev->dev_hndl, - qdata->qhndl, v1, v2, - buf + buf_idx, buf_len - buf_idx); - buf_idx = strlen(buf); - if (rv < 0) { - pr_err("qdma_queue_dump_cmpt() failed: %d", rv); - goto send_resp; - } - if (qconf.q_type != Q_CMPT) { - if (is_qp && (dir == qconf.q_type)) { - qconf.q_type = (~qconf.q_type) & 0x1; - goto dump_q; - } - } - } - rv = snprintf(buf + buf_idx, buf_len - buf_idx, - "Dumped descs of queues %u -> %u.\n", - qidx, i - 1); - buf_idx += rv; -send_resp: - rv = xnl_respond_buffer(info, buf, buf_len, rv); - - kfree(buf); - return rv; -} - -static int xnl_q_read_udd(struct sk_buff *skb2, struct genl_info *info) -{ - int rv = 0; - struct qdma_queue_conf qconf; - char *buf; - unsigned char is_qp; - struct xlnx_pci_dev *xpdev; - struct xlnx_qdata *qdata; - int buf_len = XNL_RESP_BUFLEN_MAX; - - if (info == NULL) - return -EINVAL; - - xnl_dump_attrs(info); - - buf = xnl_mem_alloc(XNL_RESP_BUFLEN_MAX, info); - if (!buf) - return -ENOMEM; - - xpdev = xnl_rcv_check_xpdev(info); - if (!xpdev) { - kfree(buf); - return -EINVAL; - } - - rv = qconf_get(&qconf, info, buf, XNL_RESP_BUFLEN_MAX, &is_qp); - if (rv < 0) - goto send_resp; - - qdata = xnl_rcv_check_qidx(info, xpdev, &qconf, buf, - XNL_RESP_BUFLEN_MAX); - if (!qdata) - goto send_resp; - - rv = qdma_descq_get_cmpt_udd(xpdev->dev_hndl, qdata->qhndl, buf, - XNL_RESP_BUFLEN_MAX); - if (rv < 0) - goto send_resp; - -send_resp: - rv = xnl_respond_buffer(info, buf, buf_len, rv); - - kfree(buf); - return rv; -} - -static int xnl_q_cmpt_read(struct sk_buff *skb2, struct genl_info *info) -{ - int rv = 0, err = 0; - struct qdma_queue_conf qconf; - char *buf = NULL; - unsigned char is_qp = 0; - struct xlnx_pci_dev *xpdev = NULL; - struct xlnx_qdata *qdata = NULL; - int buf_len = XNL_RESP_BUFLEN_MAX; - u32 num_entries = 0; - u8 *cmpt_entries = NULL, *cmpt_entry_list = NULL; - u32 cmpt_entry_len = 0; - u32 count = 0, diff_len = 0; - struct qdma_queue_conf qconf_attr; - - if (info == NULL) - return -EINVAL; - - xnl_dump_attrs(info); - - xpdev = xnl_rcv_check_xpdev(info); - if (!xpdev) - return -EINVAL; - - if (info->attrs[XNL_ATTR_RSP_BUF_LEN]) - buf_len = nla_get_u32(info->attrs[XNL_ATTR_RSP_BUF_LEN]); - - buf = xnl_mem_alloc(buf_len, info); - if (!buf) - return -ENOMEM; - - rv = qconf_get(&qconf, info, buf, buf_len, &is_qp); - if (rv < 0) - goto send_resp; - - qconf.q_type = Q_CMPT; - qdata = xnl_rcv_check_qidx(info, xpdev, &qconf, buf, buf_len); - if (!qdata) - goto send_resp; - - rv = qdma_queue_get_config(xpdev->dev_hndl, qdata->qhndl, - &qconf_attr, buf, buf_len); - if (rv < 0) - goto send_resp; - - rv = qdma_descq_read_cmpt_data(xpdev->dev_hndl, - qdata->qhndl, - &num_entries, - &cmpt_entries, - buf, - buf_len); - if (rv < 0) - goto free_cmpt; - - if (num_entries != 0) { - memset(buf, '\0', buf_len); - cmpt_entry_list = cmpt_entries; - cmpt_entry_len = 8 << qconf_attr.cmpl_desc_sz; - for (count = 0; count < num_entries; count++) { - hex_dump_to_buffer(cmpt_entry_list, cmpt_entry_len, - 32, 4, buf + diff_len, - buf_len - diff_len, 0); - diff_len = strlen(buf); - if (cmpt_entry_len > 32) { - diff_len += snprintf(buf + diff_len, - buf_len - diff_len, - " "); - hex_dump_to_buffer(cmpt_entry_list + 32, - cmpt_entry_len, - 32, 4, buf + diff_len, - buf_len - diff_len, 0); - diff_len = strlen(buf); - } - buf[diff_len++] = '\n'; - cmpt_entry_list += cmpt_entry_len; - } - } - -free_cmpt: - kfree(cmpt_entries); -send_resp: - err = rv; - rv = xnl_respond_buffer_cmpt(info, buf, buf_len, - err, num_entries); - kfree(buf); - return rv; -} - - -#ifdef ERR_DEBUG -static int xnl_err_induce(struct sk_buff *skb2, struct genl_info *info) -{ - struct xlnx_pci_dev *xpdev; - struct qdma_queue_conf qconf; - struct xlnx_qdata *qdata; - char *buf; - char ebuf[XNL_RESP_BUFLEN_MIN]; - unsigned char is_qp; - int rv; - u32 err; - - if (info == NULL) - return 0; - - xnl_dump_attrs(info); - - xpdev = xnl_rcv_check_xpdev(info); - if (!xpdev) - return 0; - rv = qconf_get(&qconf, info, ebuf, XNL_RESP_BUFLEN_MIN, &is_qp); - if (rv < 0) - return rv; - - buf = xnl_mem_alloc(XNL_RESP_BUFLEN_MAX, info); - if (!buf) { - rv = snprintf(ebuf, XNL_RESP_BUFLEN_MIN, "%s OOM %d.\n", - __func__, XNL_RESP_BUFLEN_MAX); - xnl_respond_buffer(info, ebuf, XNL_RESP_BUFLEN_MIN, rv); - return -ENOMEM; - } - - qdata = xnl_rcv_check_qidx(info, xpdev, &qconf, buf, - XNL_RESP_BUFLEN_MIN); - if (!qdata) - goto send_resp; - err = nla_get_u32(info->attrs[XNL_ATTR_QPARAM_ERR_INFO]); - - if (qdma_queue_set_err_induction(xpdev->dev_hndl, qdata->qhndl, err, - buf, XNL_RESP_BUFLEN_MAX)) { - rv += snprintf(buf + rv, XNL_RESP_BUFLEN_MAX, - "Failed to set induce err\n"); - goto send_resp; - } - rv += snprintf(buf + rv, XNL_RESP_BUFLEN_MAX, - "queue error induced\n"); - -send_resp: - rv = xnl_respond_buffer(info, buf, XNL_RESP_BUFLEN_MAX, rv); - - kfree(buf); - return rv; -} -#endif - -static int xnl_q_read_pkt(struct sk_buff *skb2, struct genl_info *info) -{ -#if 0 - struct xlnx_pci_dev *xpdev; - struct qdma_queue_conf qconf; - struct xlnx_qdata *qdata; - char *buf; - char ebuf[XNL_RESP_BUFLEN_MIN]; - int rv; - unsigned char is_qp; - unsigned int num_q; - unsigned int i; - unsigned short qidx; - int buf_len = XNL_RESP_BUFLEN_MAX; - - if (info == NULL) - return 0; - - xnl_dump_attrs(info); - - xpdev = xnl_rcv_check_xpdev(info); - if (!xpdev) - return 0; - - rv = qconf_get(&qconf, info, ebuf, XNL_RESP_BUFLEN_MIN, &is_qp); - if (rv < 0) - return rv; - - if (info->attrs[XNL_ATTR_RSP_BUF_LEN]) - buf_len = nla_get_u32(info->attrs[XNL_ATTR_RSP_BUF_LEN]); - - buf = xnl_mem_alloc(buf_len, info); - if (!buf) { - rv = snprintf(ebuf, XNL_RESP_BUFLEN_MIN, - "%s OOM %d.\n", - __func__, buf_len); - xnl_respond_buffer(info, ebuf, XNL_RESP_BUFLEN_MIN, rv); - return -ENOMEM; - } - - if (!info->attrs[XNL_ATTR_NUM_Q]) { - pr_warn("Missing attribute 'XNL_ATTR_NUM_Q'"); - return -1; - } - num_q = nla_get_u32(info->attrs[XNL_ATTR_NUM_Q]); - - qidx = qconf.qidx; - for (i = qidx; i < (qidx + num_q); i++) { - qconf.q_type = 1; - qconf.qidx = i; - qdata = xnl_rcv_check_qidx(info, xpdev, &qconf, buf, - buf_len); - if (!qdata) - goto send_resp; - rv = qdma_queue_dump_rx_packet(xpdev->dev_hndl, qdata->qhndl, - buf, buf_len); - if (rv < 0) { - pr_err("qdma_queue_dump_rx_packet) failed: %d", rv); - goto send_resp; - } - } -send_resp: - rv = xnl_respond_buffer(info, buf, buf_len, rv); - - kfree(buf); - return rv; -#endif - pr_info("NOT supported.\n"); - return -EINVAL; -} - -static int xnl_intr_ring_dump(struct sk_buff *skb2, struct genl_info *info) -{ - struct xlnx_pci_dev *xpdev; - char *buf; - unsigned int vector_idx = 0; - int start_idx = 0, end_idx = 0; - int rv = 0; - int buf_len = XNL_RESP_BUFLEN_MAX; - - if (info == NULL) - return 0; - - xnl_dump_attrs(info); - - xpdev = xnl_rcv_check_xpdev(info); - if (!xpdev) - return 0; - - if (!info->attrs[XNL_ATTR_INTR_VECTOR_IDX]) { - pr_warn("Missing attribute 'XNL_ATTR_INTR_VECTOR_IDX'"); - return -1; - } - vector_idx = nla_get_u32(info->attrs[XNL_ATTR_INTR_VECTOR_IDX]); - start_idx = nla_get_u32(info->attrs[XNL_ATTR_INTR_VECTOR_START_IDX]); - end_idx = nla_get_u32(info->attrs[XNL_ATTR_INTR_VECTOR_END_IDX]); - - if (info->attrs[XNL_ATTR_RSP_BUF_LEN]) - buf_len = nla_get_u32(info->attrs[XNL_ATTR_RSP_BUF_LEN]); - - buf = xnl_mem_alloc(buf_len, info); - if (!buf) - return -ENOMEM; - - if (xpdev->idx == 0) { - if (vector_idx == 0) { - rv += snprintf(buf + rv, buf_len, - "vector_idx %u is for error interrupt\n", - vector_idx); - goto send_resp; - } else if (vector_idx == 1) { - rv += snprintf(buf + rv, buf_len, - "vector_idx %u is for user interrupt\n", - vector_idx); - goto send_resp; - } - } else { - if (vector_idx == 0) { - rv += snprintf(buf + rv, buf_len, - "vector_idx %u is for user interrupt\n", - vector_idx); - goto send_resp; - } - } - - rv = qdma_intr_ring_dump(xpdev->dev_hndl, - vector_idx, start_idx, - end_idx, buf, buf_len); - if (rv < 0) { - pr_err("qdma_intr_ring_dump() failed: %d", rv); - goto send_resp; - } - -send_resp: - rv = xnl_respond_buffer(info, buf, buf_len, rv); - - kfree(buf); - return rv; -} - -static int xnl_register_read(struct sk_buff *skb2, struct genl_info *info) -{ - struct sk_buff *skb; - void *hdr; - struct xlnx_pci_dev *xpdev; - struct qdma_dev_conf conf; - char buf[XNL_RESP_BUFLEN_MIN]; - unsigned int bar_num = 0, reg_addr = 0; - uint32_t reg_val = 0; - int rv = 0, err = 0; - - if (info == NULL) - return 0; - - xnl_dump_attrs(info); - - xpdev = xnl_rcv_check_xpdev(info); - if (!xpdev) - return 0; - - rv = qdma_device_get_config(xpdev->dev_hndl, &conf, NULL, 0); - if (rv < 0) - return rv; - - skb = xnl_msg_alloc(XNL_CMD_REG_RD, 0, &hdr, info); - if (!skb) - return -ENOMEM; - - if (!info->attrs[XNL_ATTR_REG_BAR_NUM]) { - pr_warn("Missing attribute 'XNL_ATTR_REG_BAR_NUM'"); - return -EINVAL; - } - - if (!info->attrs[XNL_ATTR_REG_ADDR]) { - pr_warn("Missing attribute 'XNL_ATTR_REG_ADDR'"); - return -EINVAL; - } - - bar_num = nla_get_u32(info->attrs[XNL_ATTR_REG_BAR_NUM]); - reg_addr = nla_get_u32(info->attrs[XNL_ATTR_REG_ADDR]); - - if (bar_num == conf.bar_num_config) { - rv = qdma_device_read_config_register(xpdev->dev_hndl, - reg_addr, ®_val); - if (rv < 0) { - pr_err("Config bar register read failed with error = %d\n", - rv); - return rv; - } - } else if (bar_num == conf.bar_num_user) { - rv = qdma_device_read_user_register(xpdev, reg_addr, ®_val); - if (rv < 0) { - pr_err("AXI Master Lite bar register read failed with error = %d\n", - rv); - return rv; - } - } else if (bar_num == conf.bar_num_bypass) { - rv = qdma_device_read_bypass_register(xpdev, - reg_addr, ®_val); - if (rv < 0) { - pr_err("AXI Bridge Master bar register read failed with error = %d\n", - rv); - return rv; - } - } else { - rv += snprintf(buf + rv, XNL_RESP_BUFLEN_MIN, - "Invalid bar number\n"); - goto send_resp; - } - - err = xnl_msg_add_attr_uint(skb, XNL_ATTR_REG_VAL, reg_val); - if (err < 0) { - pr_err("xnl_msg_add_attr_uint() failed: %d", rv); - return err; - } - - err = xnl_msg_send(skb, hdr, info); - return err; - -send_resp: - rv = xnl_respond_buffer(info, buf, XNL_RESP_BUFLEN_MIN, err); - nlmsg_free(skb); - return rv; -} - -static int xnl_register_write(struct sk_buff *skb2, struct genl_info *info) -{ - struct xlnx_pci_dev *xpdev; - struct qdma_dev_conf conf; - char buf[XNL_RESP_BUFLEN_MIN]; - unsigned int bar_num = 0, reg_addr = 0; - uint32_t reg_val = 0; - int rv = 0; - - if (info == NULL) - return 0; - - xnl_dump_attrs(info); - - xpdev = xnl_rcv_check_xpdev(info); - if (!xpdev) - return 0; - - rv = qdma_device_get_config(xpdev->dev_hndl, &conf, NULL, 0); - if (rv < 0) - return rv; - - if (!info->attrs[XNL_ATTR_REG_BAR_NUM]) { - pr_warn("Missing attribute 'XNL_ATTR_REG_BAR_NUM'"); - return -EINVAL; - } - - if (!info->attrs[XNL_ATTR_REG_ADDR]) { - pr_warn("Missing attribute 'XNL_ATTR_REG_ADDR'"); - return -EINVAL; - } - - if (!info->attrs[XNL_ATTR_REG_VAL]) { - pr_warn("Missing attribute 'XNL_ATTR_REG_VAL'"); - return -EINVAL; - } - - bar_num = nla_get_u32(info->attrs[XNL_ATTR_REG_BAR_NUM]); - reg_addr = nla_get_u32(info->attrs[XNL_ATTR_REG_ADDR]); - reg_val = nla_get_u32(info->attrs[XNL_ATTR_REG_VAL]); - - if (bar_num == conf.bar_num_config) { - rv = qdma_device_write_config_register(xpdev->dev_hndl, - reg_addr, reg_val); - if (rv < 0) { - pr_err("Config bar register write failed with error = %d\n", - rv); - return rv; - } - } else if (bar_num == conf.bar_num_user) { - rv = qdma_device_write_user_register(xpdev, reg_addr, reg_val); - if (rv < 0) { - pr_err("AXI Master Lite bar register write failed with error = %d\n", - rv); - return rv; - } - - } else if (bar_num == conf.bar_num_bypass) { - rv = qdma_device_write_bypass_register(xpdev, - reg_addr, reg_val); - if (rv < 0) { - pr_err("AXI Bridge Master bar register write failed with error = %d\n", - rv); - return rv; - } - } else { - rv += snprintf(buf + rv, XNL_RESP_BUFLEN_MIN, - "Invalid bar number\n"); - goto send_resp; - } - - -send_resp: - rv = xnl_respond_buffer(info, buf, XNL_RESP_BUFLEN_MIN, rv); - return rv; -} - -static int xnl_get_global_csr(struct sk_buff *skb2, struct genl_info *info) -{ - struct global_csr_conf *csr; - struct xlnx_pci_dev *xpdev; - int rv; - u8 index = 0, count = 0; - - if (info == NULL) - return -EINVAL; - - xnl_dump_attrs(info); - - xpdev = xnl_rcv_check_xpdev(info); - if (!xpdev) - return 0; - - csr = kmalloc(sizeof(struct global_csr_conf), GFP_KERNEL); - if (!csr) - return -ENOMEM; - - if (!info->attrs[XNL_ATTR_CSR_INDEX]) { - pr_warn("Missing attribute 'XNL_ATTR_CSR_INDEX'"); - kfree(csr); - return -EINVAL; - } - - if (!info->attrs[XNL_ATTR_CSR_COUNT]) { - pr_warn("Missing attribute 'XNL_ATTR_CSR_COUNT'"); - kfree(csr); - return -EINVAL; - } - - index = nla_get_u32(info->attrs[XNL_ATTR_CSR_INDEX]); - count = nla_get_u32(info->attrs[XNL_ATTR_CSR_COUNT]); - - rv = qdma_global_csr_get(xpdev->dev_hndl, index, count, csr); - if (rv < 0) { - pr_err("qdma_global_csr_get() failed: %d", rv); - goto free_msg_buff; - } - - rv = xnl_respond_data(info, - (void *)csr, sizeof(struct global_csr_conf)); - -free_msg_buff: - kfree(csr); - return rv; -} - -#ifdef TANDEM_BOOT_SUPPORTED -static int xnl_en_st(struct sk_buff *skb2, struct genl_info *info) -{ - struct xlnx_pci_dev *xpdev; - int rv; - char *buf; - - if (info == NULL) - return -EINVAL; - - xnl_dump_attrs(info); - - xpdev = xnl_rcv_check_xpdev(info); - if (!xpdev) - return -EINVAL; - buf = xnl_mem_alloc(XNL_RESP_BUFLEN_MIN, info); - if (!buf) - return -ENOMEM; - - qdma_init_st_ctxt(xpdev->dev_hndl, buf, XNL_RESP_BUFLEN_MAX); - rv = xnl_respond_buffer(info, buf, XNL_RESP_BUFLEN_MAX, 0); - - kfree(buf); - return rv; -} -#endif - -int xlnx_nl_init(void) -{ - int rv; -#ifdef __GENL_REG_FAMILY_OPS_FUNC__ - rv = genl_register_family_with_ops(&xnl_family, - xnl_ops, ARRAY_SIZE(xnl_ops)); -#else - rv = genl_register_family(&xnl_family); -#endif - if (rv) - pr_err("genl_register_family failed %d.\n", rv); - - return rv; -} - -void xlnx_nl_exit(void) -{ - int rv; - - rv = genl_unregister_family(&xnl_family); - if (rv) - pr_err("genl_unregister_family failed %d.\n", rv); -} diff --git a/QDMA/linux-kernel/driver/src/nl.h b/QDMA/linux-kernel/driver/src/nl.h deleted file mode 100755 index e1d402455..000000000 --- a/QDMA/linux-kernel/driver/src/nl.h +++ /dev/null @@ -1,49 +0,0 @@ -/* - * This file is part of the Xilinx DMA IP Core driver for Linux - * - * Copyright (c) 2017-2022, Xilinx, Inc. All rights reserved. - * Copyright (c) 2022-2023, Advanced Micro Devices, Inc. All rights reserved. - * - * This source code is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * The full GNU General Public License is included in this distribution in - * the file called "COPYING". - */ - -#ifndef __QDMA_DRV_NL_H__ -#define __QDMA_DRV_NL_H__ -/** - * @file - * @brief This file contains the declarations for qdma netlink helper - * funnctions kernel module - * - */ -#define pr_fmt(fmt) KBUILD_MODNAME ":%s: " fmt, __func__ - -#include - -/*****************************************************************************/ -/** - * xnl_respond_buffer() - send a netlink string message - * - * @param[in] nl_info: pointer to netlink genl_info - * @param[in] buf: string buffer - * @param[in] buflen: length of the string buffer - * - * @return 0: success - * @return <0: failure - *****************************************************************************/ -int xnl_respond_buffer(struct genl_info *info, char *buf, int buflen, - int error); - -int xlnx_nl_init(void); -void xlnx_nl_exit(void); - -#endif /* ifndef __QDMA_DRV_NL_H__ */ diff --git a/QDMA/linux-kernel/driver/src/pci_ids.h b/QDMA/linux-kernel/driver/src/pci_ids.h deleted file mode 100755 index 61a3da1eb..000000000 --- a/QDMA/linux-kernel/driver/src/pci_ids.h +++ /dev/null @@ -1,477 +0,0 @@ -/* - * This file is part of the Xilinx DMA IP Core driver for Linux - * - * Copyright (c) 2017-2022, Xilinx, Inc. All rights reserved. - * Copyright (c) 2022-2023, Advanced Micro Devices, Inc. All rights reserved. - * - * This source code is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * The full GNU General Public License is included in this distribution in - * the file called "COPYING". - */ - -#ifndef __XDMA_PCI_ID_H__ -#define __XDMA_PCI_ID_H__ -/** - * @file - * @brief This file contains the list of pcie devices supported for qdma driver - * - */ - -/** - * list of pcie devices supported for qdma driver - */ -static const struct pci_device_id pci_ids[] = { - -#ifdef __QDMA_VF__ - /** Gen 1 VF */ - /** PCIe lane width x1 */ - { PCI_DEVICE(0x10ee, 0xa011), }, /** VF on PF 0 */ - { PCI_DEVICE(0x10ee, 0xa111), }, /** VF on PF 1 */ - { PCI_DEVICE(0x10ee, 0xa211), }, /** VF on PF 2 */ - { PCI_DEVICE(0x10ee, 0xa311), }, /** VF on PF 3 */ - /** PCIe lane width x2 */ - { PCI_DEVICE(0x10ee, 0xa012), }, /** VF on PF 0 */ - { PCI_DEVICE(0x10ee, 0xa112), }, /** VF on PF 1 */ - { PCI_DEVICE(0x10ee, 0xa212), }, /** VF on PF 2 */ - { PCI_DEVICE(0x10ee, 0xa312), }, /** VF on PF 3 */ - /** PCIe lane width x4 */ - { PCI_DEVICE(0x10ee, 0xa014), }, /** VF on PF 0 */ - { PCI_DEVICE(0x10ee, 0xa114), }, /** VF on PF 1 */ - { PCI_DEVICE(0x10ee, 0xa214), }, /** VF on PF 2 */ - { PCI_DEVICE(0x10ee, 0xa314), }, /** VF on PF 3 */ - /** PCIe lane width x8 */ - { PCI_DEVICE(0x10ee, 0xa018), }, /** VF on PF 0 */ - { PCI_DEVICE(0x10ee, 0xa118), }, /** VF on PF 1 */ - { PCI_DEVICE(0x10ee, 0xa218), }, /** VF on PF 2 */ - { PCI_DEVICE(0x10ee, 0xa318), }, /** VF on PF 3 */ - /** PCIe lane width x16 */ - { PCI_DEVICE(0x10ee, 0xa01f), }, /** VF on PF 0 */ - { PCI_DEVICE(0x10ee, 0xa11f), }, /** VF on PF 1 */ - { PCI_DEVICE(0x10ee, 0xa21f), }, /** VF on PF 2 */ - { PCI_DEVICE(0x10ee, 0xa31f), }, /** VF on PF 3 */ - - /** Gen 2 VF */ - /** PCIe lane width x1 */ - { PCI_DEVICE(0x10ee, 0xa021), }, /** VF on PF 0 */ - { PCI_DEVICE(0x10ee, 0xa121), }, /** VF on PF 1 */ - { PCI_DEVICE(0x10ee, 0xa221), }, /** VF on PF 2 */ - { PCI_DEVICE(0x10ee, 0xa321), }, /** VF on PF 3 */ - /** PCIe lane width x2 */ - { PCI_DEVICE(0x10ee, 0xa022), }, /** VF on PF 0 */ - { PCI_DEVICE(0x10ee, 0xa122), }, /** VF on PF 1 */ - { PCI_DEVICE(0x10ee, 0xa222), }, /** VF on PF 2 */ - { PCI_DEVICE(0x10ee, 0xa322), }, /** VF on PF 3 */ - /** PCIe lane width x4 */ - { PCI_DEVICE(0x10ee, 0xa024), }, /** VF on PF 0 */ - { PCI_DEVICE(0x10ee, 0xa124), }, /** VF on PF 1 */ - { PCI_DEVICE(0x10ee, 0xa224), }, /** VF on PF 2 */ - { PCI_DEVICE(0x10ee, 0xa324), }, /** VF on PF 3 */ - /** PCIe lane width x8 */ - { PCI_DEVICE(0x10ee, 0xa028), }, /** VF on PF 0 */ - { PCI_DEVICE(0x10ee, 0xa128), }, /** VF on PF 1 */ - { PCI_DEVICE(0x10ee, 0xa228), }, /** VF on PF 2 */ - { PCI_DEVICE(0x10ee, 0xa328), }, /** VF on PF 3 */ - /** PCIe lane width x16 */ - { PCI_DEVICE(0x10ee, 0xa02f), }, /** VF on PF 0 */ - { PCI_DEVICE(0x10ee, 0xa12f), }, /** VF on PF 1 */ - { PCI_DEVICE(0x10ee, 0xa22f), }, /** VF on PF 2 */ - { PCI_DEVICE(0x10ee, 0xa32f), }, /** VF on PF 3 */ - - /** Gen 3 VF */ - /** PCIe lane width x1 */ - { PCI_DEVICE(0x10ee, 0xa031), }, /** VF on PF 0 */ - { PCI_DEVICE(0x10ee, 0xa131), }, /** VF on PF 1 */ - { PCI_DEVICE(0x10ee, 0xa231), }, /** VF on PF 2 */ - { PCI_DEVICE(0x10ee, 0xa331), }, /** VF on PF 3 */ - /** PCIe lane width x2 */ - { PCI_DEVICE(0x10ee, 0xa032), }, /** VF on PF 0 */ - { PCI_DEVICE(0x10ee, 0xa132), }, /** VF on PF 1 */ - { PCI_DEVICE(0x10ee, 0xa232), }, /** VF on PF 2 */ - { PCI_DEVICE(0x10ee, 0xa332), }, /** VF on PF 3 */ - /** PCIe lane width x4 */ - { PCI_DEVICE(0x10ee, 0xa034), }, /** VF on PF 0 */ - { PCI_DEVICE(0x10ee, 0xa134), }, /** VF on PF 1 */ - { PCI_DEVICE(0x10ee, 0xa234), }, /** VF on PF 2 */ - { PCI_DEVICE(0x10ee, 0xa334), }, /** VF on PF 3 */ - /** PCIe lane width x8 */ - { PCI_DEVICE(0x10ee, 0xa038), }, /** VF on PF 0 */ - { PCI_DEVICE(0x10ee, 0xa138), }, /** VF on PF 1 */ - { PCI_DEVICE(0x10ee, 0xa238), }, /** VF on PF 2 */ - { PCI_DEVICE(0x10ee, 0xa338), }, /** VF on PF 3 */ - /** PCIe lane width x16 */ - { PCI_DEVICE(0x10ee, 0xa03f), }, /** VF on PF 0 */ - { PCI_DEVICE(0x10ee, 0xa13f), }, /** VF on PF 1 */ - { PCI_DEVICE(0x10ee, 0xa23f), }, /** VF on PF 2 */ - { PCI_DEVICE(0x10ee, 0xa33f), }, /** VF on PF 3 */ - - /** Gen 4 VF */ - /** PCIe lane width x1 */ - { PCI_DEVICE(0x10ee, 0xa041), }, /** VF on PF 0 */ - { PCI_DEVICE(0x10ee, 0xa141), }, /** VF on PF 1 */ - { PCI_DEVICE(0x10ee, 0xa241), }, /** VF on PF 2 */ - { PCI_DEVICE(0x10ee, 0xa341), }, /** VF on PF 3 */ - /** PCIe lane width x2 */ - { PCI_DEVICE(0x10ee, 0xa042), }, /** VF on PF 0 */ - { PCI_DEVICE(0x10ee, 0xa142), }, /** VF on PF 1 */ - { PCI_DEVICE(0x10ee, 0xa242), }, /** VF on PF 2 */ - { PCI_DEVICE(0x10ee, 0xa342), }, /** VF on PF 3 */ - /** PCIe lane width x4 */ - { PCI_DEVICE(0x10ee, 0xa044), }, /** VF on PF 0 */ - { PCI_DEVICE(0x10ee, 0xa144), }, /** VF on PF 1 */ - { PCI_DEVICE(0x10ee, 0xa244), }, /** VF on PF 2 */ - { PCI_DEVICE(0x10ee, 0xa344), }, /** VF on PF 3 */ - { PCI_DEVICE(0x10ee, 0xa444), }, /** VF on PF 4 */ - { PCI_DEVICE(0x10ee, 0xa544), }, /** VF on PF 5 */ - { PCI_DEVICE(0x10ee, 0xa644), }, /** VF on PF 6 */ - { PCI_DEVICE(0x10ee, 0xa744), }, /** VF on PF 7 */ - /** PCIe lane width x8 */ - { PCI_DEVICE(0x10ee, 0xa048), }, /** VF on PF 0 */ - { PCI_DEVICE(0x10ee, 0xa148), }, /** VF on PF 1 */ - { PCI_DEVICE(0x10ee, 0xa248), }, /** VF on PF 2 */ - { PCI_DEVICE(0x10ee, 0xa348), }, /** VF on PF 3 */ - - /** Gen 1 VF */ - /** PCIe lane width x1 */ - { PCI_DEVICE(0x10ee, 0xc011), }, /** VF on PF 0 */ - { PCI_DEVICE(0x10ee, 0xc111), }, /** VF on PF 1 */ - { PCI_DEVICE(0x10ee, 0xc211), }, /** VF on PF 2 */ - { PCI_DEVICE(0x10ee, 0xc311), }, /** VF on PF 3 */ - /** PCIe lane width x2 */ - { PCI_DEVICE(0x10ee, 0xc012), }, /** VF on PF 0 */ - { PCI_DEVICE(0x10ee, 0xc112), }, /** VF on PF 1 */ - { PCI_DEVICE(0x10ee, 0xc212), }, /** VF on PF 2 */ - { PCI_DEVICE(0x10ee, 0xc312), }, /** VF on PF 3 */ - /** PCIe lane width x4 */ - { PCI_DEVICE(0x10ee, 0xc014), }, /** VF on PF 0 */ - { PCI_DEVICE(0x10ee, 0xc114), }, /** VF on PF 1 */ - { PCI_DEVICE(0x10ee, 0xc214), }, /** VF on PF 2 */ - { PCI_DEVICE(0x10ee, 0xc314), }, /** VF on PF 3 */ - /** PCIe lane width x8 */ - { PCI_DEVICE(0x10ee, 0xc018), }, /** VF on PF 0 */ - { PCI_DEVICE(0x10ee, 0xc118), }, /** VF on PF 1 */ - { PCI_DEVICE(0x10ee, 0xc218), }, /** VF on PF 2 */ - { PCI_DEVICE(0x10ee, 0xc318), }, /** VF on PF 3 */ - /** PCIe lane width x16 */ - { PCI_DEVICE(0x10ee, 0xc01f), }, /** VF on PF 0 */ - { PCI_DEVICE(0x10ee, 0xc11f), }, /** VF on PF 1 */ - { PCI_DEVICE(0x10ee, 0xc21f), }, /** VF on PF 2 */ - { PCI_DEVICE(0x10ee, 0xc31f), }, /** VF on PF 3 */ - - /** Gen 2 VF */ - /** PCIe lane width x1 */ - { PCI_DEVICE(0x10ee, 0xc021), }, /** VF on PF 0 */ - { PCI_DEVICE(0x10ee, 0xc121), }, /** VF on PF 1 */ - { PCI_DEVICE(0x10ee, 0xc221), }, /** VF on PF 2 */ - { PCI_DEVICE(0x10ee, 0xc321), }, /** VF on PF 3 */ - /** PCIe lane width x2 */ - { PCI_DEVICE(0x10ee, 0xc022), }, /** VF on PF 0 */ - { PCI_DEVICE(0x10ee, 0xc122), }, /** VF on PF 1 */ - { PCI_DEVICE(0x10ee, 0xc222), }, /** VF on PF 2 */ - { PCI_DEVICE(0x10ee, 0xc322), }, /** VF on PF 3 */ - /** PCIe lane width x4 */ - { PCI_DEVICE(0x10ee, 0xc024), }, /** VF on PF 0 */ - { PCI_DEVICE(0x10ee, 0xc124), }, /** VF on PF 1 */ - { PCI_DEVICE(0x10ee, 0xc224), }, /** VF on PF 2 */ - { PCI_DEVICE(0x10ee, 0xc324), }, /** VF on PF 3 */ - /** PCIe lane width x8 */ - { PCI_DEVICE(0x10ee, 0xc028), }, /** VF on PF 0 */ - { PCI_DEVICE(0x10ee, 0xc128), }, /** VF on PF 1 */ - { PCI_DEVICE(0x10ee, 0xc228), }, /** VF on PF 2 */ - { PCI_DEVICE(0x10ee, 0xc328), }, /** VF on PF 3 */ - /** PCIe lane width x16 */ - { PCI_DEVICE(0x10ee, 0xc02f), }, /** VF on PF 0 */ - { PCI_DEVICE(0x10ee, 0xc12f), }, /** VF on PF 1 */ - { PCI_DEVICE(0x10ee, 0xc22f), }, /** VF on PF 2 */ - { PCI_DEVICE(0x10ee, 0xc32f), }, /** VF on PF 3 */ - - /** Gen 3 VF */ - /** PCIe lane width x1 */ - { PCI_DEVICE(0x10ee, 0xc031), }, /** VF on PF 0 */ - { PCI_DEVICE(0x10ee, 0xc131), }, /** VF on PF 1 */ - { PCI_DEVICE(0x10ee, 0xc231), }, /** VF on PF 2 */ - { PCI_DEVICE(0x10ee, 0xc331), }, /** VF on PF 3 */ - /** PCIe lane width x2 */ - { PCI_DEVICE(0x10ee, 0xc032), }, /** VF on PF 0 */ - { PCI_DEVICE(0x10ee, 0xc132), }, /** VF on PF 1 */ - { PCI_DEVICE(0x10ee, 0xc232), }, /** VF on PF 2 */ - { PCI_DEVICE(0x10ee, 0xc332), }, /** VF on PF 3 */ - /** PCIe lane width x4 */ - { PCI_DEVICE(0x10ee, 0xc034), }, /** VF on PF 0 */ - { PCI_DEVICE(0x10ee, 0xc134), }, /** VF on PF 1 */ - { PCI_DEVICE(0x10ee, 0xc234), }, /** VF on PF 2 */ - { PCI_DEVICE(0x10ee, 0xc334), }, /** VF on PF 3 */ - /** PCIe lane width x8 */ - { PCI_DEVICE(0x10ee, 0xc038), }, /** VF on PF 0 */ - { PCI_DEVICE(0x10ee, 0xc138), }, /** VF on PF 1 */ - { PCI_DEVICE(0x10ee, 0xc238), }, /** VF on PF 2 */ - { PCI_DEVICE(0x10ee, 0xc338), }, /** VF on PF 3 */ - /** PCIe lane width x16 */ - { PCI_DEVICE(0x10ee, 0xc03f), }, /** VF on PF 0 */ - { PCI_DEVICE(0x10ee, 0xc13f), }, /** VF on PF 1 */ - { PCI_DEVICE(0x10ee, 0xc23f), }, /** VF on PF 2 */ - { PCI_DEVICE(0x10ee, 0xc33f), }, /** VF on PF 3 */ - - /** Gen 4 VF */ - /** PCIe lane width x1 */ - { PCI_DEVICE(0x10ee, 0xc041), }, /** VF on PF 0 */ - { PCI_DEVICE(0x10ee, 0xc141), }, /** VF on PF 1 */ - { PCI_DEVICE(0x10ee, 0xc241), }, /** VF on PF 2 */ - { PCI_DEVICE(0x10ee, 0xc341), }, /** VF on PF 3 */ - /** PCIe lane width x2 */ - { PCI_DEVICE(0x10ee, 0xc042), }, /** VF on PF 0 */ - { PCI_DEVICE(0x10ee, 0xc142), }, /** VF on PF 1 */ - { PCI_DEVICE(0x10ee, 0xc242), }, /** VF on PF 2 */ - { PCI_DEVICE(0x10ee, 0xc342), }, /** VF on PF 3 */ - /** PCIe lane width x4 */ - { PCI_DEVICE(0x10ee, 0xc044), }, /** VF on PF 0 */ - { PCI_DEVICE(0x10ee, 0xc144), }, /** VF on PF 1 */ - { PCI_DEVICE(0x10ee, 0xc244), }, /** VF on PF 2 */ - { PCI_DEVICE(0x10ee, 0xc344), }, /** VF on PF 3 */ - { PCI_DEVICE(0x10ee, 0xc444), }, /** VF on PF 4 */ - { PCI_DEVICE(0x10ee, 0xc544), }, /** VF on PF 5 */ - { PCI_DEVICE(0x10ee, 0xc644), }, /** VF on PF 6 */ - { PCI_DEVICE(0x10ee, 0xc744), }, /** VF on PF 7 */ - /** PCIe lane width x8 */ - { PCI_DEVICE(0x10ee, 0xc048), }, /** VF on PF 0 */ - { PCI_DEVICE(0x10ee, 0xc148), }, /** VF on PF 1 */ - { PCI_DEVICE(0x10ee, 0xc248), }, /** VF on PF 2 */ - { PCI_DEVICE(0x10ee, 0xc348), }, /** VF on PF 3 */ - - /** Gen 5 VF */ - /** PCIe lane width x8 */ - { PCI_DEVICE(0x10ee, 0xc058), }, /** VF on PF 0 */ - { PCI_DEVICE(0x10ee, 0xc158), }, /** VF on PF 1 */ - { PCI_DEVICE(0x10ee, 0xc258), }, /** VF on PF 2 */ - { PCI_DEVICE(0x10ee, 0xc358), }, /** VF on PF 3 */ -#else - /** Gen 1 PF */ - /** PCIe lane width x1 */ - { PCI_DEVICE(0x10ee, 0x9011), }, /** PF 0 */ - { PCI_DEVICE(0x10ee, 0x9111), }, /** PF 1 */ - { PCI_DEVICE(0x10ee, 0x9211), }, /** PF 2 */ - { PCI_DEVICE(0x10ee, 0x9311), }, /** PF 3 */ - /** PCIe lane width x2 */ - { PCI_DEVICE(0x10ee, 0x9012), }, /** PF 0 */ - { PCI_DEVICE(0x10ee, 0x9112), }, /** PF 1 */ - { PCI_DEVICE(0x10ee, 0x9212), }, /** PF 2 */ - { PCI_DEVICE(0x10ee, 0x9312), }, /** PF 3 */ - /** PCIe lane width x4 */ - { PCI_DEVICE(0x10ee, 0x9014), }, /** PF 0 */ - { PCI_DEVICE(0x10ee, 0x9114), }, /** PF 1 */ - { PCI_DEVICE(0x10ee, 0x9214), }, /** PF 2 */ - { PCI_DEVICE(0x10ee, 0x9314), }, /** PF 3 */ - /** PCIe lane width x8 */ - { PCI_DEVICE(0x10ee, 0x9018), }, /** PF 0 */ - { PCI_DEVICE(0x10ee, 0x9118), }, /** PF 1 */ - { PCI_DEVICE(0x10ee, 0x9218), }, /** PF 2 */ - { PCI_DEVICE(0x10ee, 0x9318), }, /** PF 3 */ - /** PCIe lane width x16 */ - { PCI_DEVICE(0x10ee, 0x901f), }, /** PF 0 */ - { PCI_DEVICE(0x10ee, 0x911f), }, /** PF 1 */ - { PCI_DEVICE(0x10ee, 0x921f), }, /** PF 2 */ - { PCI_DEVICE(0x10ee, 0x931f), }, /** PF 3 */ - - /** Gen 2 PF */ - /** PCIe lane width x1 */ - { PCI_DEVICE(0x10ee, 0x9021), }, /** PF 0 */ - { PCI_DEVICE(0x10ee, 0x9121), }, /** PF 1 */ - { PCI_DEVICE(0x10ee, 0x9221), }, /** PF 2 */ - { PCI_DEVICE(0x10ee, 0x9321), }, /** PF 3 */ - /** PCIe lane width x2 */ - { PCI_DEVICE(0x10ee, 0x9022), }, /** PF 0 */ - { PCI_DEVICE(0x10ee, 0x9122), }, /** PF 1 */ - { PCI_DEVICE(0x10ee, 0x9222), }, /** PF 2 */ - { PCI_DEVICE(0x10ee, 0x9322), }, /** PF 3 */ - /** PCIe lane width x4 */ - { PCI_DEVICE(0x10ee, 0x9024), }, /** PF 0 */ - { PCI_DEVICE(0x10ee, 0x9124), }, /** PF 1 */ - { PCI_DEVICE(0x10ee, 0x9224), }, /** PF 2 */ - { PCI_DEVICE(0x10ee, 0x9324), }, /** PF 3 */ - /** PCIe lane width x8 */ - { PCI_DEVICE(0x10ee, 0x9028), }, /** PF 0 */ - { PCI_DEVICE(0x10ee, 0x9128), }, /** PF 1 */ - { PCI_DEVICE(0x10ee, 0x9228), }, /** PF 2 */ - { PCI_DEVICE(0x10ee, 0x9328), }, /** PF 3 */ - /** PCIe lane width x16 */ - { PCI_DEVICE(0x10ee, 0x902f), }, /** PF 0 */ - { PCI_DEVICE(0x10ee, 0x912f), }, /** PF 1 */ - { PCI_DEVICE(0x10ee, 0x922f), }, /** PF 2 */ - { PCI_DEVICE(0x10ee, 0x932f), }, /** PF 3 */ - - /** Gen 3 PF */ - /** PCIe lane width x1 */ - { PCI_DEVICE(0x10ee, 0x9031), }, /** PF 0 */ - { PCI_DEVICE(0x10ee, 0x9131), }, /** PF 1 */ - { PCI_DEVICE(0x10ee, 0x9231), }, /** PF 2 */ - { PCI_DEVICE(0x10ee, 0x9331), }, /** PF 3 */ - /** PCIe lane width x2 */ - { PCI_DEVICE(0x10ee, 0x9032), }, /** PF 0 */ - { PCI_DEVICE(0x10ee, 0x9132), }, /** PF 1 */ - { PCI_DEVICE(0x10ee, 0x9232), }, /** PF 2 */ - { PCI_DEVICE(0x10ee, 0x9332), }, /** PF 3 */ - /** PCIe lane width x4 */ - { PCI_DEVICE(0x10ee, 0x9034), }, /** PF 0 */ - { PCI_DEVICE(0x10ee, 0x9134), }, /** PF 1 */ - { PCI_DEVICE(0x10ee, 0x9234), }, /** PF 2 */ - { PCI_DEVICE(0x10ee, 0x9334), }, /** PF 3 */ - /** PCIe lane width x8 */ - { PCI_DEVICE(0x10ee, 0x9038), }, /** PF 0 */ - { PCI_DEVICE(0x10ee, 0x9138), }, /** PF 1 */ - { PCI_DEVICE(0x10ee, 0x9238), }, /** PF 2 */ - { PCI_DEVICE(0x10ee, 0x9338), }, /** PF 3 */ - /** PCIe lane width x16 */ - { PCI_DEVICE(0x10ee, 0x903f), }, /** PF 0 */ - { PCI_DEVICE(0x10ee, 0x913f), }, /** PF 1 */ - { PCI_DEVICE(0x10ee, 0x923f), }, /** PF 2 */ - { PCI_DEVICE(0x10ee, 0x933f), }, /** PF 3 */ - /* { PCI_DEVICE(0x10ee, 0x6a9f), }, */ /** PF 0 */ - { PCI_DEVICE(0x10ee, 0x6aa0), }, /** PF 1 */ - - /** Gen 4 PF */ - /** PCIe lane width x1 */ - { PCI_DEVICE(0x10ee, 0x9041), }, /** PF 0 */ - { PCI_DEVICE(0x10ee, 0x9141), }, /** PF 1 */ - { PCI_DEVICE(0x10ee, 0x9241), }, /** PF 2 */ - { PCI_DEVICE(0x10ee, 0x9341), }, /** PF 3 */ - /** PCIe lane width x2 */ - { PCI_DEVICE(0x10ee, 0x9042), }, /** PF 0 */ - { PCI_DEVICE(0x10ee, 0x9142), }, /** PF 1 */ - { PCI_DEVICE(0x10ee, 0x9242), }, /** PF 2 */ - { PCI_DEVICE(0x10ee, 0x9342), }, /** PF 3 */ - /** PCIe lane width x4 */ - { PCI_DEVICE(0x10ee, 0x9044), }, /** PF 0 */ - { PCI_DEVICE(0x10ee, 0x9144), }, /** PF 1 */ - { PCI_DEVICE(0x10ee, 0x9244), }, /** PF 2 */ - { PCI_DEVICE(0x10ee, 0x9344), }, /** PF 3 */ - /** PCIe lane width x8 */ - { PCI_DEVICE(0x10ee, 0x9048), }, /** PF 0 */ - { PCI_DEVICE(0x10ee, 0x9148), }, /** PF 1 */ - { PCI_DEVICE(0x10ee, 0x9248), }, /** PF 2 */ - { PCI_DEVICE(0x10ee, 0x9348), }, /** PF 3 */ - - /** Gen 1 PF */ - /** PCIe lane width x1 */ - { PCI_DEVICE(0x10ee, 0xb011), }, /** PF 0 */ - { PCI_DEVICE(0x10ee, 0xb111), }, /** PF 1 */ - { PCI_DEVICE(0x10ee, 0xb211), }, /** PF 2 */ - { PCI_DEVICE(0x10ee, 0xb311), }, /** PF 3 */ - /** PCIe lane width x2 */ - { PCI_DEVICE(0x10ee, 0xb012), }, /** PF 0 */ - { PCI_DEVICE(0x10ee, 0xb112), }, /** PF 1 */ - { PCI_DEVICE(0x10ee, 0xb212), }, /** PF 2 */ - { PCI_DEVICE(0x10ee, 0xb312), }, /** PF 3 */ - /** PCIe lane width x4 */ - { PCI_DEVICE(0x10ee, 0xb014), }, /** PF 0 */ - { PCI_DEVICE(0x10ee, 0xb114), }, /** PF 1 */ - { PCI_DEVICE(0x10ee, 0xb214), }, /** PF 2 */ - { PCI_DEVICE(0x10ee, 0xb314), }, /** PF 3 */ - /** PCIe lane width x8 */ - { PCI_DEVICE(0x10ee, 0xb018), }, /** PF 0 */ - { PCI_DEVICE(0x10ee, 0xb118), }, /** PF 1 */ - { PCI_DEVICE(0x10ee, 0xb218), }, /** PF 2 */ - { PCI_DEVICE(0x10ee, 0xb318), }, /** PF 3 */ - /** PCIe lane width x16 */ - { PCI_DEVICE(0x10ee, 0xb01f), }, /** PF 0 */ - { PCI_DEVICE(0x10ee, 0xb11f), }, /** PF 1 */ - { PCI_DEVICE(0x10ee, 0xb21f), }, /** PF 2 */ - { PCI_DEVICE(0x10ee, 0xb31f), }, /** PF 3 */ - - /** Gen 2 PF */ - /** PCIe lane width x1 */ - { PCI_DEVICE(0x10ee, 0xb021), }, /** PF 0 */ - { PCI_DEVICE(0x10ee, 0xb121), }, /** PF 1 */ - { PCI_DEVICE(0x10ee, 0xb221), }, /** PF 2 */ - { PCI_DEVICE(0x10ee, 0xb321), }, /** PF 3 */ - /** PCIe lane width x2 */ - { PCI_DEVICE(0x10ee, 0xb022), }, /** PF 0 */ - { PCI_DEVICE(0x10ee, 0xb122), }, /** PF 1 */ - { PCI_DEVICE(0x10ee, 0xb222), }, /** PF 2 */ - { PCI_DEVICE(0x10ee, 0xb322), }, /** PF 3 */ - /** PCIe lane width x4 */ - { PCI_DEVICE(0x10ee, 0xb024), }, /** PF 0 */ - { PCI_DEVICE(0x10ee, 0xb124), }, /** PF 1 */ - { PCI_DEVICE(0x10ee, 0xb224), }, /** PF 2 */ - { PCI_DEVICE(0x10ee, 0xb324), }, /** PF 3 */ - /** PCIe lane width x8 */ - { PCI_DEVICE(0x10ee, 0xb028), }, /** PF 0 */ - { PCI_DEVICE(0x10ee, 0xb128), }, /** PF 1 */ - { PCI_DEVICE(0x10ee, 0xb228), }, /** PF 2 */ - { PCI_DEVICE(0x10ee, 0xb328), }, /** PF 3 */ - /** PCIe lane width x16 */ - { PCI_DEVICE(0x10ee, 0xb02f), }, /** PF 0 */ - { PCI_DEVICE(0x10ee, 0xb12f), }, /** PF 1 */ - { PCI_DEVICE(0x10ee, 0xb22f), }, /** PF 2 */ - { PCI_DEVICE(0x10ee, 0xb32f), }, /** PF 3 */ - - /** Gen 3 PF */ - /** PCIe lane width x1 */ - { PCI_DEVICE(0x10ee, 0xb031), }, /** PF 0 */ - { PCI_DEVICE(0x10ee, 0xb131), }, /** PF 1 */ - { PCI_DEVICE(0x10ee, 0xb231), }, /** PF 2 */ - { PCI_DEVICE(0x10ee, 0xb331), }, /** PF 3 */ - /** PCIe lane width x2 */ - { PCI_DEVICE(0x10ee, 0xb032), }, /** PF 0 */ - { PCI_DEVICE(0x10ee, 0xb132), }, /** PF 1 */ - { PCI_DEVICE(0x10ee, 0xb232), }, /** PF 2 */ - { PCI_DEVICE(0x10ee, 0xb332), }, /** PF 3 */ - /** PCIe lane width x4 */ - { PCI_DEVICE(0x10ee, 0xb034), }, /** PF 0 */ - { PCI_DEVICE(0x10ee, 0xb134), }, /** PF 1 */ - { PCI_DEVICE(0x10ee, 0xb234), }, /** PF 2 */ - { PCI_DEVICE(0x10ee, 0xb334), }, /** PF 3 */ - /** PCIe lane width x8 */ - { PCI_DEVICE(0x10ee, 0xb038), }, /** PF 0 */ - { PCI_DEVICE(0x10ee, 0xb138), }, /** PF 1 */ - { PCI_DEVICE(0x10ee, 0xb238), }, /** PF 2 */ - { PCI_DEVICE(0x10ee, 0xb338), }, /** PF 3 */ - /** PCIe lane width x16 */ - { PCI_DEVICE(0x10ee, 0xb03f), }, /** PF 0 */ - { PCI_DEVICE(0x10ee, 0xb13f), }, /** PF 1 */ - { PCI_DEVICE(0x10ee, 0xb23f), }, /** PF 2 */ - { PCI_DEVICE(0x10ee, 0xb33f), }, /** PF 3 */ - - /** Gen 4 PF */ - /** PCIe lane width x1 */ - { PCI_DEVICE(0x10ee, 0xb041), }, /** PF 0 */ - { PCI_DEVICE(0x10ee, 0xb141), }, /** PF 1 */ - { PCI_DEVICE(0x10ee, 0xb241), }, /** PF 2 */ - { PCI_DEVICE(0x10ee, 0xb341), }, /** PF 3 */ - /** PCIe lane width x2 */ - { PCI_DEVICE(0x10ee, 0xb042), }, /** PF 0 */ - { PCI_DEVICE(0x10ee, 0xb142), }, /** PF 1 */ - { PCI_DEVICE(0x10ee, 0xb242), }, /** PF 2 */ - { PCI_DEVICE(0x10ee, 0xb342), }, /** PF 3 */ - /** PCIe lane width x4 */ - { PCI_DEVICE(0x10ee, 0xb044), }, /** PF 0 */ - { PCI_DEVICE(0x10ee, 0xb144), }, /** PF 1 */ - { PCI_DEVICE(0x10ee, 0xb244), }, /** PF 2 */ - { PCI_DEVICE(0x10ee, 0xb344), }, /** PF 3 */ - /** PCIe lane width x8 */ - { PCI_DEVICE(0x10ee, 0xb048), }, /** PF 0 */ - { PCI_DEVICE(0x10ee, 0xb148), }, /** PF 1 */ - { PCI_DEVICE(0x10ee, 0xb248), }, /** PF 2 */ - { PCI_DEVICE(0x10ee, 0xb348), }, /** PF 3 */ - - /** Gen 5 PF */ - /** PCIe lane width x8 */ - { PCI_DEVICE(0x10ee, 0xb058), }, /** PF 0 */ - { PCI_DEVICE(0x10ee, 0xb158), }, /** PF 1 */ - { PCI_DEVICE(0x10ee, 0xb258), }, /** PF 2 */ - { PCI_DEVICE(0x10ee, 0xb358), }, /** PF 3 */ -#endif - - {0,} -}; - -/** module device table */ -MODULE_DEVICE_TABLE(pci, pci_ids); - -#endif /* ifndef __XDMA_PCI_ID_H__ */ diff --git a/QDMA/linux-kernel/driver/src/qdma_mod.c b/QDMA/linux-kernel/driver/src/qdma_mod.c deleted file mode 100755 index 11791f978..000000000 --- a/QDMA/linux-kernel/driver/src/qdma_mod.c +++ /dev/null @@ -1,1927 +0,0 @@ -/* - * This file is part of the Xilinx DMA IP Core driver for Linux - * - * Copyright (c) 2017-2022, Xilinx, Inc. All rights reserved. - * Copyright (c) 2022-2023, Advanced Micro Devices, Inc. All rights reserved. - * - * This source code is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * The full GNU General Public License is included in this distribution in - * the file called "COPYING". - */ - -#define pr_fmt(fmt) KBUILD_MODNAME ":%s: " fmt, __func__ - -#include "qdma_mod.h" - -#include -#include -#include -#include -#include -#include -#include -#include - -#include "nl.h" -#include "libqdma/xdev.h" - -/* include early, to verify it depends only on the headers above */ -#include "version.h" - -#define QDMA_DEFAULT_TOTAL_Q 2048 - -static char version[] = - DRV_MODULE_DESC " v" DRV_MODULE_VERSION "\n"; - -MODULE_AUTHOR("Xilinx, Inc."); -MODULE_DESCRIPTION(DRV_MODULE_DESC); -MODULE_VERSION(DRV_MODULE_VERSION); -MODULE_LICENSE("Dual BSD/GPL"); - -static char mode[500] = {0}; -module_param_string(mode, mode, sizeof(mode), 0); -MODULE_PARM_DESC(mode, "Load the driver in different modes, dflt is auto mode, format is \"::\" and multiple comma separated entries can be specified"); - -static char config_bar[500] = {0}; -module_param_string(config_bar, config_bar, sizeof(config_bar), 0); -MODULE_PARM_DESC(config_bar, "specify the config bar number, dflt is 0, format is \"::\" and multiple comma separated entries can be specified"); - -static char master_pf[500] = {0}; -module_param_string(master_pf, master_pf, sizeof(master_pf), 0); -MODULE_PARM_DESC(master_pf, "specify the master_pf, dflt is 0, format is \":\" and multiple comma separated entries can be specified"); - -static unsigned int num_threads; -module_param(num_threads, uint, 0644); -MODULE_PARM_DESC(num_threads, -"Number of threads to be created each for request and writeback processing"); - - -#include "pci_ids.h" - -/* - * xpdev helper functions - */ -static LIST_HEAD(xpdev_list); -static DEFINE_MUTEX(xpdev_mutex); - -static int xpdev_qdata_realloc(struct xlnx_pci_dev *xpdev, unsigned int qmax); - -static int xpdev_map_bar(struct xlnx_pci_dev *xpdev, - void __iomem **regs, u8 bar_num); -static void xpdev_unmap_bar(struct xlnx_pci_dev *xpdev, void __iomem **regs); - -#ifdef __QDMA_VF__ -void qdma_flr_resource_free(unsigned long dev_hndl); -#endif - -/*****************************************************************************/ -/** - * funcname() - handler to show the intr_rngsz configuration value - * - * @dev : PCIe device handle - * @attr: intr_rngsz configuration value - * @buf : buffer to hold the configured value - * - * Handler function to show the intr_rngsz - * - * @note none - * - * Return: Returns length of the buffer on success, <0 on failure - * - *****************************************************************************/ -static ssize_t show_intr_rngsz(struct device *dev, - struct device_attribute *attr, char *buf) -{ - struct xlnx_pci_dev *xpdev; - int len; - unsigned int rngsz = 0; - - xpdev = (struct xlnx_pci_dev *)dev_get_drvdata(dev); - if (!xpdev) - return -EINVAL; - - rngsz = qdma_get_intr_rngsz(xpdev->dev_hndl); - len = scnprintf(buf, PAGE_SIZE, "%u\n", rngsz); - if (len <= 0) - pr_err("copying rngsz to buffer failed with err: %d\n", len); - - return len; -} - -/*****************************************************************************/ -/** - * funcname() - handler to set the intr_rngsz configuration value - * - * @dev : PCIe device handle - * @attr: intr_rngsz configuration value - * @buf : buffer to hold the configured value - * @count : the number of bytes of data in the buffer - * - * Handler function to set the intr_rngsz - * - * @note none - * - * Return: Returns length of the buffer on success, <0 on failure - * - *****************************************************************************/ -static ssize_t set_intr_rngsz(struct device *dev, - struct device_attribute *attr, const char *buf, size_t count) -{ - struct xlnx_pci_dev *xpdev; - unsigned int rngsz = 0; - int err = 0; - - xpdev = (struct xlnx_pci_dev *)dev_get_drvdata(dev); - if (!xpdev) - return -EINVAL; - - err = kstrtouint(buf, 0, &rngsz); - if (err < 0) { - pr_err("failed to set interrupt ring size\n"); - return err; - } - - - err = qdma_set_intr_rngsz(xpdev->dev_hndl, (u32)rngsz); - return err ? err : count; -} - -/*****************************************************************************/ -/** - * funcname() - handler to show the qmax configuration value - * - * @dev : PCIe device handle - * @attr: qmax configuration value - * @buf : buffer to hold the configured value - * - * Handler function to show the qmax - * - * @note none - * - * Return: Returns length of the buffer on success, <0 on failure - * - *****************************************************************************/ -static ssize_t show_qmax(struct device *dev, - struct device_attribute *attr, char *buf) -{ - struct xlnx_pci_dev *xpdev; - int len; - unsigned int qmax = 0; - - xpdev = (struct xlnx_pci_dev *)dev_get_drvdata(dev); - if (!xpdev) - return -EINVAL; - - qmax = qdma_get_qmax(xpdev->dev_hndl); - len = scnprintf(buf, PAGE_SIZE, "%u\n", qmax); - if (len <= 0) - pr_err("copying qmax to buf failed with err: %d\n", len); - - return len; -} - -#ifndef __QDMA_VF__ -static ssize_t set_qmax(struct device *dev, - struct device_attribute *attr, const char *buf, size_t count) -{ - struct xlnx_pci_dev *xpdev; - unsigned int qmax = 0; - int err = 0; - - xpdev = (struct xlnx_pci_dev *)dev_get_drvdata(dev); - if (!xpdev) - return -EINVAL; - err = kstrtouint(buf, 0, &qmax); - if (err < 0) { - pr_err("failed to set qmax to %d\n", qmax); - return err; - } - err = qdma_set_qmax(xpdev->dev_hndl, -1, qmax); - - if (!err) - xpdev_qdata_realloc(xpdev, qmax); - - return err ? err : count; -} - -/*****************************************************************************/ -/** - * funcname() - handler to show the cmpl_status_acc configuration value - * - * @dev : PCIe device handle - * @attr: cmpl_status_acc configuration value - * @buf : buffer to hold the configured value - * - * Handler function to show the cmpl_status_acc - * - * @note none - * - * Return: Returns length of the buffer on success, <0 on failure - * - *****************************************************************************/ -static ssize_t show_cmpl_status_acc(struct device *dev, - struct device_attribute *attr, char *buf) -{ - struct xlnx_pci_dev *xpdev; - int len; - unsigned int cmpl_status_acc = 0; - - xpdev = (struct xlnx_pci_dev *)dev_get_drvdata(dev); - if (!xpdev) - return -EINVAL; - - cmpl_status_acc = qdma_get_wb_intvl(xpdev->dev_hndl); - len = scnprintf(buf, PAGE_SIZE, - "%u\n", cmpl_status_acc); - if (len <= 0) - pr_err("copying cmpl status acc value to buf failed with err: %d\n", - len); - - return len; -} - -/*****************************************************************************/ -/** - * funcname() - handler to set the cmpl_status_acc configuration value - * - * @dev : PCIe device handle - * @attr: cmpl_status_acc configuration value - * @buf : buffer to hold the configured value - * @count : the number of bytes of data in the buffer - * - * Handler function to set the cmpl_status_acc - * - * @note none - * - * Return: Returns length of the buffer on success, <0 on failure - * - *****************************************************************************/ -static ssize_t set_cmpl_status_acc(struct device *dev, - struct device_attribute *attr, const char *buf, size_t count) -{ -#ifdef QDMA_CSR_REG_UPDATE - struct pci_dev *pdev = to_pci_dev(dev); - struct xlnx_pci_dev *xpdev; - unsigned int cmpl_status_acc = 0; - int err = 0; - - if (!pdev) - return -EINVAL; - - xpdev = (struct xlnx_pci_dev *)dev_get_drvdata(dev); - if (!xpdev) - return -EINVAL; - - err = kstrtoint(buf, 0, &cmpl_status_acc); - if (err < 0) { - pr_err("failed to set cmpl status accumulator to %d\n", - cmpl_status_acc); - return err; - } - - err = qdma_set_cmpl_status_acc(xpdev->dev_hndl, cmpl_status_acc); - return err ? err : count; -#else - pr_warn("QDMA CSR completion status accumulation update is not allowed\n"); - return -EPERM; -#endif -} - -/*****************************************************************************/ -/** - * funcname() - handler to show the buf_sz configuration value - * - * @dev : PCIe device handle - * @attr: buf_sz configuration value - * @buf : buffer to hold the configured value - * - * Handler function to show the buf_sz - * - * @note none - * - * Return: Returns length of the buffer on success, <0 on failure - * - *****************************************************************************/ - -static ssize_t show_c2h_buf_sz(struct device *dev, - struct device_attribute *attr, char *buf) -{ - struct xlnx_pci_dev *xpdev; - int len = 0; - int i; - unsigned int c2h_buf_sz[QDMA_GLOBAL_CSR_ARRAY_SZ] = {0}; - - xpdev = (struct xlnx_pci_dev *)dev_get_drvdata(dev); - if (!xpdev) - return -EINVAL; - - qdma_get_buf_sz(xpdev->dev_hndl, c2h_buf_sz); - - len += scnprintf(buf + len, PAGE_SIZE - len, "%u", c2h_buf_sz[0]); - for (i = 1; i < QDMA_GLOBAL_CSR_ARRAY_SZ; i++) - len += scnprintf(buf + len, - PAGE_SIZE - len, " %u", c2h_buf_sz[i]); - len += scnprintf(buf + len, PAGE_SIZE - len, "%s", "\n\0"); - - return len; -} - -/*****************************************************************************/ -/** - * funcname() - handler to set the buf_sz configuration value - * - * @dev : PCIe device handle - * @attr: buf_sz configuration value - * @buf : buffer to hold the configured value - * @count : the number of bytes of data in the buffer - * - * Handler function to set the buf_sz - * - * @note none - * - * Return: Returns length of the buffer on success, <0 on failure - * - *****************************************************************************/ - -static ssize_t set_c2h_buf_sz(struct device *dev, - struct device_attribute *attr, const char *buf, size_t count) -{ -#ifdef QDMA_CSR_REG_UPDATE - struct pci_dev *pdev = to_pci_dev(dev); - struct xlnx_pci_dev *xpdev; - int err = 0; - char *s = (char *)buf, *p = NULL; - const char *tc = " "; /* token character here is a "space" */ - unsigned int c2h_buf_sz[QDMA_GLOBAL_CSR_ARRAY_SZ] = {0}; - int i = 0; - - if (!pdev) - return -EINVAL; - - xpdev = (struct xlnx_pci_dev *)dev_get_drvdata(dev); - if (!xpdev) - return -EINVAL; - - /* First read the values in to the register - * This helps to restore the values of entries if - * user configures lesser than 16 values - */ - qdma_get_buf_sz(xpdev->dev_hndl, c2h_buf_sz); - - while (((p = strsep(&s, tc)) != NULL) && - (i < QDMA_GLOBAL_CSR_ARRAY_SZ)) { - if (*p == 0) - continue; - - err = kstrtoint(p, 0, &c2h_buf_sz[i]); - if (err < 0) - goto input_err; - - i++; - } - - if (p) { - /* - * check if the number of entries are more than 16 ! - * if yes, ignore the extra values - */ - pr_warn("Found more than 16 buffer size entries. Ignoring extra entries\n"); - } - - err = qdma_set_buf_sz(xpdev->dev_hndl, c2h_buf_sz); - -input_err: - return err ? err : count; -#else - pr_warn("QDMA CSR C2H buffer size update is not allowed\n"); - return -EPERM; -#endif -} - -/*****************************************************************************/ -/** - * funcname() - handler to show the ring_sz configuration value - * - * @dev : PCIe device handle - * @attr: ring_sz configuration value - * @buf : buffer to hold the configured value - * - * Handler function to show the ring_sz - * - * @note none - * - * Return: Returns length of the buffer on success, <0 on failure - * - *****************************************************************************/ - -static ssize_t show_glbl_rng_sz(struct device *dev, - struct device_attribute *attr, char *buf) -{ - struct xlnx_pci_dev *xpdev; - struct xlnx_dma_dev *xdev = NULL; - int len = 0; - int i; - unsigned int glbl_ring_sz[QDMA_GLOBAL_CSR_ARRAY_SZ] = {0}; - - xpdev = (struct xlnx_pci_dev *)dev_get_drvdata(dev); - if (!xpdev) - return -EINVAL; - - xdev = (struct xlnx_dma_dev *)(xpdev->dev_hndl); - qdma_get_ring_sizes(xdev, 0, QDMA_GLOBAL_CSR_ARRAY_SZ, glbl_ring_sz); - len += scnprintf(buf + len, PAGE_SIZE - len, "%u", glbl_ring_sz[0]); - for (i = 1; i < QDMA_GLOBAL_CSR_ARRAY_SZ; i++) - len += scnprintf(buf + len, - PAGE_SIZE - len, - " %u", glbl_ring_sz[i]); - len += scnprintf(buf + len, PAGE_SIZE - len, "%s", "\n\0"); - - return len; -} - -/*****************************************************************************/ -/** - * funcname() - handler to set the glbl_ring_sz configuration value - * - * @dev : PCIe device handle - * @attr: buf_sz configuration value - * @buf : buffer to hold the configured value - * @count : the number of bytes of data in the buffer - * - * Handler function to set the glbl_ring_sz - * - * @note none - * - * Return: Returns length of the buffer on success, <0 on failure - * - *****************************************************************************/ - -static ssize_t set_glbl_rng_sz(struct device *dev, - struct device_attribute *attr, const char *buf, size_t count) -{ -#ifdef QDMA_CSR_REG_UPDATE - struct pci_dev *pdev = to_pci_dev(dev); - struct xlnx_pci_dev *xpdev; - int err = 0; - char *s = (char *)buf, *p = NULL; - const char *tc = " "; /* token character here is a "space" */ - unsigned int glbl_ring_sz[QDMA_GLOBAL_CSR_ARRAY_SZ] = {0}; - int i = 0; - - if (!pdev) - return -EINVAL; - - xpdev = (struct xlnx_pci_dev *)dev_get_drvdata(dev); - if (!xpdev) - return -EINVAL; - - /* First read the values in to the register - * This helps to restore the values of entries if - * user configures lesser than 16 values - */ - qdma_get_glbl_rng_sz(xpdev->dev_hndl, glbl_ring_sz); - - while (((p = strsep(&s, tc)) != NULL) && - (i < QDMA_GLOBAL_CSR_ARRAY_SZ)) { - if (*p == 0) - continue; - - err = kstrtoint(p, 0, &glbl_ring_sz[i]); - if (err < 0) - goto input_err; - - i++; - } - - if (p) { - /* - * check if the number of entries are more than 16 ! - * if yes, ignore the extra values - */ - pr_warn("Found more than 16 ring size entries. Ignoring extra entries"); - } - - err = qdma_set_glbl_rng_sz(xpdev->dev_hndl, glbl_ring_sz); - -input_err: - return err ? err : count; -#else - pr_warn("QDMA CSR global ring size update is not allowed\n"); - return -EPERM; -#endif -} - -/*****************************************************************************/ -/** - * funcname() - handler to show global csr c2h_timer_cnt configuration value - * - * @dev : PCIe device handle - * @attr: c2h_timer_cnt configuration value - * @buf : buffer to hold the configured value - * - * Handler function to show the global csr c2h_timer_cnt - * - * @note none - * - * Return: Returns length of the buffer on success, <0 on failure - * - *****************************************************************************/ -static ssize_t show_c2h_timer_cnt(struct device *dev, - struct device_attribute *attr, char *buf) -{ - struct xlnx_pci_dev *xpdev; - int len = 0; - int i; - unsigned int c2h_timer_cnt[QDMA_GLOBAL_CSR_ARRAY_SZ] = {0}; - - xpdev = (struct xlnx_pci_dev *)dev_get_drvdata(dev); - if (!xpdev) - return -EINVAL; - - qdma_get_timer_cnt(xpdev->dev_hndl, c2h_timer_cnt); - - len += scnprintf(buf + len, PAGE_SIZE - len, "%u", c2h_timer_cnt[0]); - for (i = 1; i < QDMA_GLOBAL_CSR_ARRAY_SZ; i++) - len += scnprintf(buf + len, - PAGE_SIZE - len, - " %u", c2h_timer_cnt[i]); - len += scnprintf(buf + len, PAGE_SIZE - len, "%s", "\n\0"); - - return len; -} - -/*****************************************************************************/ -/** - * set_c2h_timer_cnt() - handler to set global csr c2h_timer_cnt config - * - * @dev : PCIe device handle - * @attr: c2h_timer_cnt configuration value - * @buf : buffer containing new configuration - * @count : the number of bytes of data in the buffer - * - * Handler function to set the global csr c2h_timer_cnt - * - * @note none - * - * Return: Returns length of the buffer on success, <0 on failure - * - *****************************************************************************/ -static ssize_t set_c2h_timer_cnt(struct device *dev, - struct device_attribute *attr, const char *buf, size_t count) -{ -#ifdef QDMA_CSR_REG_UPDATE - struct pci_dev *pdev = to_pci_dev(dev); - struct xlnx_pci_dev *xpdev; - int err = 0; - char *s = (char *)buf, *p = NULL; - const char *tc = " "; /* token character here is a "space" */ - unsigned int c2h_timer_cnt[QDMA_GLOBAL_CSR_ARRAY_SZ] = {0}; - int i = 0; - - if (!pdev) - return -EINVAL; - - xpdev = (struct xlnx_pci_dev *)dev_get_drvdata(dev); - if (!xpdev) - return -EINVAL; - - /* First read the values in to the register - * This helps to restore the values of entries if - * user configures lesser than 16 values - */ - qdma_get_timer_cnt(xpdev->dev_hndl, c2h_timer_cnt); - - while (((p = strsep(&s, tc)) != NULL) && - (i < QDMA_GLOBAL_CSR_ARRAY_SZ)) { - if (*p == 0) - continue; - - err = kstrtoint(p, 0, &c2h_timer_cnt[i]); - if (err < 0) - goto input_err; - - if (c2h_timer_cnt[i] > 255) { - pr_warn("timer cnt at index %d is %d - out of range [0-255]\n", - i, c2h_timer_cnt[i]); - err = -EINVAL; - goto input_err; - } - i++; - } - - if (p) { - /* - * check if the number of entries are more than 16 ! - * if yes, ignore the extra values - */ - pr_warn("Found more than 16 timer entries. Ignoring extra entries\n"); - } - err = qdma_set_timer_cnt(xpdev->dev_hndl, c2h_timer_cnt); - -input_err: - return err ? err : count; -#else - pr_warn("QDMA CSR C2H timer counter update is not allowed\n"); - return -EPERM; -#endif -} - -/*****************************************************************************/ -/** - * funcname() - handler to show global csr c2h_cnt_th_ configuration value - * - * @dev : PCIe device handle - * @attr: c2h_cnt_th configuration value - * @buf : buffer to hold the configured value - * - * Handler function to show the global csr c2h_cnt_th - * - * @note none - * - * Return: Returns length of the buffer on success, <0 on failure - * - *****************************************************************************/ -static ssize_t show_c2h_cnt_th(struct device *dev, - struct device_attribute *attr, char *buf) -{ - struct xlnx_pci_dev *xpdev; - int len = 0; - int i; - unsigned int c2h_cnt_th[QDMA_GLOBAL_CSR_ARRAY_SZ] = {0}; - - xpdev = (struct xlnx_pci_dev *)dev_get_drvdata(dev); - if (!xpdev) - return -EINVAL; - - qdma_get_cnt_thresh(xpdev->dev_hndl, c2h_cnt_th); - - len += scnprintf(buf + len, - PAGE_SIZE - len, "%u", c2h_cnt_th[0]); - for (i = 1; i < QDMA_GLOBAL_CSR_ARRAY_SZ; i++) - len += scnprintf(buf + len, - PAGE_SIZE - len, " %u", c2h_cnt_th[i]); - len += scnprintf(buf + len, - PAGE_SIZE - len, "%s", "\n\0"); - - return len; -} - -/*****************************************************************************/ -/** - * set_c2h_cnt_th() - handler to set global csr c2h_cnt_th configuration - * - * @dev : PCIe device handle - * @attr: c2h_cnt_th configuration value - * @buf : buffer containing new configuration - * @count : the number of bytes of data in the buffer - * - * Handler function to set the global csr c2h_cnt_th - * - * @note none - * - * Return: Returns length of the buffer on success, <0 on failure - * - *****************************************************************************/ -static ssize_t set_c2h_cnt_th(struct device *dev, - struct device_attribute *attr, const char *buf, size_t count) -{ -#ifdef QDMA_CSR_REG_UPDATE - struct pci_dev *pdev = to_pci_dev(dev); - struct xlnx_pci_dev *xpdev; - int err = 0; - char *s = (char *)buf, *p = NULL; - const char *tc = " "; /* token character here is a "space" */ - unsigned int c2h_cnt_th[QDMA_GLOBAL_CSR_ARRAY_SZ] = {0}; - int i = 0; - - if (!pdev) - return -EINVAL; - - xpdev = (struct xlnx_pci_dev *)dev_get_drvdata(dev); - if (!xpdev) - return -EINVAL; - - /* First read the values in to the register - * This helps to restore the values of entries if - * user configures lesser than 16 values - */ - qdma_get_cnt_thresh(xpdev->dev_hndl, c2h_cnt_th); - - while (((p = strsep(&s, tc)) != NULL) && - (i < QDMA_GLOBAL_CSR_ARRAY_SZ)) { - if (*p == 0) - continue; - - err = kstrtoint(p, 0, &c2h_cnt_th[i]); - if (err < 0) - goto input_err; - - if (c2h_cnt_th[i] > 255) { - pr_warn("counter threshold at index %d is %d - out of range [0-255]\n", - i, c2h_cnt_th[i]); - err = -EINVAL; - goto input_err; - } - i++; - } - - if (p) { - /* - * check if the number of entries are more than 16 ! - * if yes, ignore the extra values - */ - pr_warn("Found more than 16 counter entries. Ignoring extra entries\n"); - } - err = qdma_set_cnt_thresh(xpdev->dev_hndl, c2h_cnt_th); - -input_err: - return err ? err : count; -#else - pr_warn("QDMA CSR C2H counter threshold update is not allowed\n"); - return -EPERM; -#endif -} -#else /** For VF #ifdef __QDMA_VF__ */ -/*****************************************************************************/ -/** - * funcname() - handler to set the qmax configuration value - * - * @dev : PCIe device handle - * @attr: qmax configuration value - * @buf : buffer to hold the configured value - * - * Handler function to set the qmax - * - * @note none - * - * Return: Returns length of the buffer on success, <0 on failure - * - *****************************************************************************/ - -static ssize_t set_qmax(struct device *dev, - struct device_attribute *attr, const char *buf, size_t count) -{ - struct xlnx_pci_dev *_xpdev; - unsigned int qmax = 0; - int err = 0; - - _xpdev = (struct xlnx_pci_dev *)dev_get_drvdata(dev); - if (!_xpdev) - return -EINVAL; - - err = kstrtouint(buf, 0, &qmax); - if (err < 0) { - pr_err("Failed to set qmax\n"); - return err; - } - - err = qdma_vf_qconf(_xpdev->dev_hndl, qmax); - if (err < 0) - return err; - - if (!err) { - pr_debug("Succesfully reconfigured qdmavf%05x\n", _xpdev->idx); - xpdev_qdata_realloc(_xpdev, qmax); - } - - return err ? err : count; -} -#endif - -static DEVICE_ATTR(qmax, S_IWUSR | S_IRUGO, show_qmax, set_qmax); -static DEVICE_ATTR(intr_rngsz, S_IWUSR | S_IRUGO, - show_intr_rngsz, set_intr_rngsz); -#ifndef __QDMA_VF__ -static DEVICE_ATTR(buf_sz, S_IWUSR | S_IRUGO, - show_c2h_buf_sz, set_c2h_buf_sz); -static DEVICE_ATTR(glbl_rng_sz, S_IWUSR | S_IRUGO, - show_glbl_rng_sz, set_glbl_rng_sz); -static DEVICE_ATTR(c2h_timer_cnt, S_IWUSR | S_IRUGO, - show_c2h_timer_cnt, set_c2h_timer_cnt); -static DEVICE_ATTR(c2h_cnt_th, S_IWUSR | S_IRUGO, - show_c2h_cnt_th, set_c2h_cnt_th); -static DEVICE_ATTR(cmpl_status_acc, S_IWUSR | S_IRUGO, - show_cmpl_status_acc, set_cmpl_status_acc); -#endif - -static struct attribute *pci_device_attrs[] = { - &dev_attr_qmax.attr, - &dev_attr_intr_rngsz.attr, - NULL, -}; - -static struct attribute *pci_master_device_attrs[] = { - &dev_attr_qmax.attr, - &dev_attr_intr_rngsz.attr, -#ifndef __QDMA_VF__ - &dev_attr_buf_sz.attr, - &dev_attr_glbl_rng_sz.attr, - &dev_attr_c2h_timer_cnt.attr, - &dev_attr_c2h_cnt_th.attr, - &dev_attr_cmpl_status_acc.attr, -#endif - NULL, -}; - -static struct attribute_group pci_device_attr_group = { - .name = "qdma", - .attrs = pci_device_attrs, - -}; - -static struct attribute_group pci_master_device_attr_group = { - .name = "qdma", - .attrs = pci_master_device_attrs, - -}; - -static inline void xpdev_list_remove(struct xlnx_pci_dev *xpdev) -{ - mutex_lock(&xpdev_mutex); - list_del(&xpdev->list_head); - mutex_unlock(&xpdev_mutex); -} - -static inline void xpdev_list_add(struct xlnx_pci_dev *xpdev) -{ - mutex_lock(&xpdev_mutex); - list_add_tail(&xpdev->list_head, &xpdev_list); - mutex_unlock(&xpdev_mutex); -} - -int xpdev_list_dump(char *buf, int buflen) -{ - struct xlnx_pci_dev *xpdev, *tmp; - char *cur = buf; - char *const end = buf + buflen; - int base_end = 0; - int qmax_val = 0; - - if (!buf || !buflen) - return -EINVAL; - - mutex_lock(&xpdev_mutex); - list_for_each_entry_safe(xpdev, tmp, &xpdev_list, list_head) { - struct pci_dev *pdev; - struct qdma_dev_conf conf; - int rv; - - rv = qdma_device_get_config(xpdev->dev_hndl, &conf, NULL, 0); - if (rv < 0) { - cur += snprintf(cur, cur - end, - "ERR! unable to get device config for idx %05x\n", - xpdev->idx); - if (cur >= end) - goto handle_truncation; - break; - } - - pdev = conf.pdev; - - base_end = (int)(conf.qsets_base + conf.qsets_max - 1); - if (base_end < 0) - base_end = 0; - qmax_val = conf.qsets_max; - - if (qmax_val) { - cur += snprintf(cur, end - cur, -#ifdef __QDMA_VF__ - "qdmavf%05x\t%s\tmax QP: %d, %d~%d\n", -#else - "qdma%05x\t%s\tmax QP: %d, %d~%d\n", -#endif - xpdev->idx, dev_name(&pdev->dev), - qmax_val, conf.qsets_base, - base_end); - } else { - cur += snprintf(cur, end - cur, -#ifdef __QDMA_VF__ - "qdmavf%05x\t%s\tmax QP: 0, -~-\n", -#else - "qdma%05x\t%s\tmax QP: 0, -~-\n", -#endif - xpdev->idx, dev_name(&pdev->dev)); - } - if (cur >= end) - goto handle_truncation; - } - mutex_unlock(&xpdev_mutex); - - return cur - buf; - -handle_truncation: - mutex_unlock(&xpdev_mutex); - pr_warn("ERR! str truncated. req=%lu, avail=%u", cur - buf, buflen); - *buf = '\0'; - return cur - buf; -} - -/** - * Function to find the first PF device available in the card - */ -static bool is_first_pfdev(u8 bus_number) -{ - struct xlnx_pci_dev *_xpdev, *tmp; - - mutex_lock(&xpdev_mutex); - if (list_empty(&xpdev_list)) { - mutex_unlock(&xpdev_mutex); - return 1; - } - - list_for_each_entry_safe(_xpdev, tmp, &xpdev_list, list_head) { - struct pci_dev *pdev = _xpdev->pdev; - /** find first bus and device are matching */ - if (pdev->bus->number == bus_number) { - mutex_unlock(&xpdev_mutex); - /** if func matches, it returns 1, else 0*/ - return 0; - } - } - mutex_unlock(&xpdev_mutex); - - return 1; -} -/*****************************************************************************/ -/** - * extract_mod_param() - extract the device mode and config bar per function - * - * @param[in] pdev: pcie device - * @param[in] qdma_drv_mod_param_type: mod param type - * - * @return device mode - *****************************************************************************/ -static u8 extract_mod_param(struct pci_dev *pdev, - enum qdma_drv_mod_param_type param_type) -{ - char p[600]; - char *ptr, *mod; - - u8 dev_fn = PCI_FUNC(pdev->devfn); -#ifdef __QDMA_VF__ - u16 device_id = pdev->device; -#endif - - - /* Fetch param specified in the module parameter */ - ptr = p; - if (param_type == DRV_MODE) { - if (mode[0] == '\0') - return 0; - strncpy(p, mode, sizeof(p) - 1); - } else if (param_type == CONFIG_BAR) { - if (config_bar[0] == '\0') - return 0; - strncpy(p, config_bar, sizeof(p) - 1); - } else if (param_type == MASTER_PF) { - if (master_pf[0] == '\0') - return is_first_pfdev(pdev->bus->number); - strncpy(p, master_pf, sizeof(p) - 1); - } else { - pr_err("Invalid module param type received\n"); - return -EINVAL; - } - - while ((mod = strsep(&ptr, ","))) { - unsigned int bus_num, func_num, param = 0; - int fields; - - if (!strlen(mod)) - continue; - - if (param_type == MASTER_PF) { - fields = sscanf(mod, "%x:%x", &bus_num, ¶m); - - if (fields != 2) { - pr_warn("invalid mode string \"%s\"\n", mod); - continue; - } - - if ((bus_num == pdev->bus->number) && - (dev_fn == param)) - return 1; - } else { - fields = sscanf(mod, "%x:%x:%x", - &bus_num, &func_num, ¶m); - - if (fields != 3) { - pr_warn("invalid mode string \"%s\"\n", mod); - continue; - } - -#ifndef __QDMA_VF__ - if ((bus_num == pdev->bus->number) && - (func_num == dev_fn)) - return param; -#else - if ((bus_num == pdev->bus->number) && - (((device_id >> VF_PF_IDENTIFIER_SHIFT) & - VF_PF_IDENTIFIER_MASK) == func_num)) - return param; -#endif - } - } - - return 0; -} - -struct xlnx_pci_dev *xpdev_find_by_idx(unsigned int idx, char *buf, int buflen) -{ - struct xlnx_pci_dev *xpdev, *tmp; - - mutex_lock(&xpdev_mutex); - list_for_each_entry_safe(xpdev, tmp, &xpdev_list, list_head) { - if (xpdev->idx == idx) { - mutex_unlock(&xpdev_mutex); - return xpdev; - } - } - mutex_unlock(&xpdev_mutex); - - if (buf && buflen) - snprintf(buf, buflen, "NO device found at index %05x!\n", idx); - - return NULL; -} - -struct xlnx_qdata *xpdev_queue_get(struct xlnx_pci_dev *xpdev, - unsigned int qidx, u8 q_type, bool check_qhndl, - char *ebuf, int ebuflen) -{ - struct xlnx_qdata *qdata; - - if (qidx >= xpdev->qmax) { - pr_debug("qdma%05x QID %u too big, %05x.\n", - xpdev->idx, qidx, xpdev->qmax); - if (ebuf && ebuflen) { - snprintf(ebuf, ebuflen, "QID %u too big, %u.\n", - qidx, xpdev->qmax); - } - return NULL; - } - - qdata = xpdev->qdata + qidx; - if (q_type == Q_C2H) - qdata += xpdev->qmax; - if (q_type == Q_CMPT) - qdata += (2 * xpdev->qmax); - - if (check_qhndl && (!qdata->qhndl && !qdata->xcdev)) { - pr_debug("qdma%05x QID %u NOT configured.\n", xpdev->idx, qidx); - if (ebuf && ebuflen) { - snprintf(ebuf, ebuflen, - "QID %u NOT configured.\n", qidx); - } - - return NULL; - } - - return qdata; -} - -int xpdev_queue_delete(struct xlnx_pci_dev *xpdev, unsigned int qidx, u8 q_type, - char *ebuf, int ebuflen) -{ - struct xlnx_qdata *qdata = xpdev_queue_get(xpdev, qidx, q_type, 1, ebuf, - ebuflen); - int rv = 0; - - if (!qdata) - return -EINVAL; - - if (q_type != Q_CMPT) { - if (!qdata->xcdev) - return -EINVAL; - } - - if (qdata->qhndl != QDMA_QUEUE_IDX_INVALID) - rv = qdma_queue_remove(xpdev->dev_hndl, qdata->qhndl, - ebuf, ebuflen); - else - pr_err("qidx %u/%u, type %d, qhndl invalid.\n", - qidx, xpdev->qmax, q_type); - if (rv < 0) - goto exit; - - if (q_type != Q_CMPT) { - spin_lock(&xpdev->cdev_lock); - qdata->xcdev->dir_init &= ~(1 << (q_type ? 1 : 0)); - spin_unlock(&xpdev->cdev_lock); - - if (!qdata->xcdev->dir_init) - qdma_cdev_destroy(qdata->xcdev); - } - - memset(qdata, 0, sizeof(*qdata)); -exit: - return rv; -} - -#if KERNEL_VERSION(3, 16, 0) <= LINUX_VERSION_CODE -static void xpdev_queue_delete_all(struct xlnx_pci_dev *xpdev) -{ - int i; - - for (i = 0; i < xpdev->qmax; i++) { - xpdev_queue_delete(xpdev, i, 0, NULL, 0); - xpdev_queue_delete(xpdev, i, 1, NULL, 0); - } -} -#endif - -int xpdev_queue_add(struct xlnx_pci_dev *xpdev, struct qdma_queue_conf *qconf, - char *ebuf, int ebuflen) -{ - struct xlnx_qdata *qdata; - struct qdma_cdev *xcdev = NULL; - struct xlnx_qdata *qdata_tmp; - struct qdma_dev_conf dev_config; - u8 dir; - unsigned long qhndl; - int rv; - - rv = qdma_queue_add(xpdev->dev_hndl, qconf, &qhndl, ebuf, ebuflen); - if (rv < 0) - return rv; - - pr_debug("qdma%05x idx %u, st %d, q_type %s, added, qhndl 0x%lx.\n", - xpdev->idx, qconf->qidx, qconf->st, - q_type_list[qconf->q_type].name, qhndl); - - qdata = xpdev_queue_get(xpdev, qconf->qidx, qconf->q_type, 0, ebuf, - ebuflen); - if (!qdata) { - pr_err("q added 0x%lx, get failed, idx 0x%x.\n", - qhndl, qconf->qidx); - return rv; - } - - if (qconf->q_type != Q_CMPT) { - dir = (qconf->q_type == Q_C2H) ? 0 : 1; - spin_lock(&xpdev->cdev_lock); - qdata_tmp = xpdev_queue_get(xpdev, qconf->qidx, - dir, 0, NULL, 0); - if (qdata_tmp) { - /* only 1 cdev per queue pair */ - if (qdata_tmp->xcdev) { - unsigned long *priv_data; - - qdata->qhndl = qhndl; - qdata->xcdev = qdata_tmp->xcdev; - priv_data = (qconf->q_type == Q_C2H) ? - &qdata->xcdev->c2h_qhndl : - &qdata->xcdev->h2c_qhndl; - *priv_data = qhndl; - qdata->xcdev->dir_init |= (1 << qconf->q_type); - - spin_unlock(&xpdev->cdev_lock); - return 0; - } - } - spin_unlock(&xpdev->cdev_lock); - } - - rv = qdma_device_get_config(xpdev->dev_hndl, &dev_config, NULL, 0); - if (rv < 0) { - pr_err("Failed to get conf for qdma device '%05x'\n", - xpdev->idx); - return rv; - } - - /* always create the cdev - * Give HW QID as minor number with qsets_base calculation - */ - if (qconf->q_type != Q_CMPT) { - rv = qdma_cdev_create(&xpdev->cdev_cb, xpdev->pdev, qconf, - (dev_config.qsets_base + qconf->qidx), - qhndl, &xcdev, ebuf, ebuflen); - - qdata->xcdev = xcdev; - } - - qdata->qhndl = qhndl; - - return rv; -} - -static void nl_work_handler_q_start(struct work_struct *work) -{ - struct xlnx_nl_work *nl_work = container_of(work, struct xlnx_nl_work, - work); - struct xlnx_pci_dev *xpdev = nl_work->xpdev; - struct xlnx_nl_work_q_ctrl *qctrl = &nl_work->qctrl; - unsigned int qidx = qctrl->qidx; - u8 is_qp = qctrl->is_qp; - u8 q_type = qctrl->q_type; - int i; - char *ebuf = nl_work->buf; - int rv = 0; - - for (i = 0; i < qctrl->qcnt; i++, qidx++) { - struct xlnx_qdata *qdata; - -q_start: - qdata = xpdev_queue_get(xpdev, qidx, q_type, 1, ebuf, - nl_work->buflen); - if (!qdata) { - pr_err("%s, idx %u, q_type %s, get failed.\n", - dev_name(&xpdev->pdev->dev), qidx, - q_type_list[q_type].name); - snprintf(ebuf, nl_work->buflen, - "Q idx %u, q_type %s, get failed.\n", - qidx, q_type_list[q_type].name); - goto send_resp; - } - - rv = qdma_queue_start(xpdev->dev_hndl, qdata->qhndl, ebuf, - nl_work->buflen); - if (rv < 0) { - pr_err("%s, idx %u, q_type %s, start failed %d.\n", - dev_name(&xpdev->pdev->dev), qidx, - q_type_list[q_type].name, rv); - snprintf(ebuf, nl_work->buflen, - "Q idx %u, q_type %s, start failed %d.\n", - qidx, q_type_list[q_type].name, rv); - goto send_resp; - } - if (qctrl->q_type != Q_CMPT) { - if (is_qp && q_type == qctrl->q_type) { - q_type = !qctrl->q_type; - goto q_start; - } - - q_type = qctrl->q_type; - } - } - - snprintf(ebuf, nl_work->buflen, - "%u Queues started, idx %u ~ %u.\n", - qctrl->qcnt, qctrl->qidx, qidx - 1); - -send_resp: - nl_work->q_start_handled = 1; - nl_work->ret = rv; - wake_up_interruptible(&nl_work->wq); -} - -static struct xlnx_nl_work *xpdev_nl_work_alloc(struct xlnx_pci_dev *xpdev) -{ - struct xlnx_nl_work *nl_work; - - /* allocate work struct */ - nl_work = kzalloc(sizeof(*nl_work), GFP_ATOMIC); - if (!nl_work) { - pr_err("qdma%05x %s: OOM.\n", - xpdev->idx, dev_name(&xpdev->pdev->dev)); - return NULL; - } - - nl_work->xpdev = xpdev; - - return nl_work; -} - -int xpdev_nl_queue_start(struct xlnx_pci_dev *xpdev, void *nl_info, u8 is_qp, - u8 q_type, unsigned short qidx, unsigned short qcnt) -{ - struct xlnx_nl_work *nl_work = xpdev_nl_work_alloc(xpdev); - struct xlnx_nl_work_q_ctrl *qctrl; - char ebuf[XNL_EBUFLEN]; - int rv = 0; - - if (!nl_work) - return -ENOMEM; - - qctrl = &nl_work->qctrl; - qctrl->is_qp = is_qp; - qctrl->q_type = q_type; - qctrl->qidx = qidx; - qctrl->qcnt = qcnt; - - INIT_WORK(&nl_work->work, nl_work_handler_q_start); - init_waitqueue_head(&nl_work->wq); - nl_work->q_start_handled = 0; - nl_work->buf = ebuf; - nl_work->buflen = XNL_EBUFLEN; - queue_work(xpdev->nl_task_wq, &nl_work->work); - wait_event_interruptible(nl_work->wq, nl_work->q_start_handled); - rv = nl_work->ret; - kfree(nl_work); - xnl_respond_buffer(nl_info, ebuf, strlen(ebuf), rv); - - return rv; -} - -static void xpdev_free(struct xlnx_pci_dev *p) -{ - xpdev_list_remove(p); - - if (p->nl_task_wq) - destroy_workqueue(p->nl_task_wq); - - kfree(p->qdata); - kfree(p); -} - -static int xpdev_qdata_realloc(struct xlnx_pci_dev *xpdev, unsigned int qmax) -{ - if (!xpdev) - return -EINVAL; - - kfree(xpdev->qdata); - xpdev->qdata = NULL; - - if (!qmax) - return 0; - xpdev->qdata = kzalloc(qmax * 3 * sizeof(struct xlnx_qdata), - GFP_KERNEL); - if (!xpdev->qdata) { - pr_err("OMM, xpdev->qdata, sz %u.\n", qmax); - return -ENOMEM; - } - xpdev->qmax = qmax; - - return 0; -} - -static struct xlnx_pci_dev *xpdev_alloc(struct pci_dev *pdev, unsigned int qmax) -{ - int sz = sizeof(struct xlnx_pci_dev); - struct xlnx_pci_dev *xpdev = kzalloc(sz, GFP_KERNEL); - char name[80]; - - if (!xpdev) { - xpdev = vmalloc(sz); - if (xpdev) - memset(xpdev, 0, sz); - } - - if (!xpdev) { - pr_err("OMM, qmax %u, sz %u.\n", qmax, sz); - return NULL; - } - spin_lock_init(&xpdev->cdev_lock); - xpdev->pdev = pdev; - xpdev->qmax = qmax; - xpdev->idx = 0xFF; - if (qmax && (xpdev_qdata_realloc(xpdev, qmax) < 0)) - goto free_xpdev; - - snprintf(name, 80, "qdma_%s_nl_wq", dev_name(&pdev->dev)); - xpdev->nl_task_wq = create_singlethread_workqueue(name); - if (!xpdev->nl_task_wq) { - pr_err("%s failed to allocate nl_task_wq.\n", - dev_name(&pdev->dev)); - goto free_xpdev; - } - - xpdev_list_add(xpdev); - return xpdev; - -free_xpdev: - xpdev_free(xpdev); - return NULL; -} - -static int xpdev_map_bar(struct xlnx_pci_dev *xpdev, - void __iomem **regs, u8 bar_num) -{ - int map_len; - - /* map the AXI Master Lite bar */ - map_len = pci_resource_len(xpdev->pdev, (int)bar_num); - if (map_len > QDMA_MAX_BAR_LEN_MAPPED) - map_len = QDMA_MAX_BAR_LEN_MAPPED; - - *regs = pci_iomap(xpdev->pdev, bar_num, map_len); - if (!(*regs)) { - pr_err("unable to map bar %d.\n", bar_num); - return -ENOMEM; - } - - return 0; -} - -static void xpdev_unmap_bar(struct xlnx_pci_dev *xpdev, void __iomem **regs) -{ - /* unmap BAR */ - if (*regs) { - pci_iounmap(xpdev->pdev, *regs); - /* mark as unmapped */ - *regs = NULL; - } -} - -int qdma_device_read_user_register(struct xlnx_pci_dev *xpdev, - u32 reg_addr, u32 *value) -{ - struct xlnx_dma_dev *xdev = NULL; - int rv = 0; - - if (!xpdev) - return -EINVAL; - - xdev = (struct xlnx_dma_dev *)(xpdev->dev_hndl); - - if (xdev->conf.bar_num_user < 0) { - pr_err("AXI Master Lite bar is not present\n"); - return -EINVAL; - } - - /* map the AXI Master Lite bar */ - rv = xpdev_map_bar(xpdev, &xpdev->user_bar_regs, - xdev->conf.bar_num_user); - if (rv < 0) - return rv; - - *value = readl(xpdev->user_bar_regs + reg_addr); - - /* unmap the AXI Master Lite bar after accessing it */ - xpdev_unmap_bar(xpdev, &xpdev->user_bar_regs); - - return 0; -} - -int qdma_device_write_user_register(struct xlnx_pci_dev *xpdev, - u32 reg_addr, u32 value) -{ - struct xlnx_dma_dev *xdev = NULL; - int rv = 0; - - if (!xpdev) - return -EINVAL; - - xdev = (struct xlnx_dma_dev *)(xpdev->dev_hndl); - - if (xdev->conf.bar_num_user < 0) { - pr_err("AXI Master Lite bar is not present\n"); - return -EINVAL; - } - - /* map the AXI Master Lite bar */ - rv = xpdev_map_bar(xpdev, &xpdev->user_bar_regs, - xdev->conf.bar_num_user); - if (rv < 0) - return rv; - - - writel(value, xpdev->user_bar_regs + reg_addr); - - /* unmap the AXI Master Lite bar after accessing it */ - xpdev_unmap_bar(xpdev, &xpdev->user_bar_regs); - - return 0; -} - -int qdma_device_read_bypass_register(struct xlnx_pci_dev *xpdev, - u32 reg_addr, u32 *value) -{ - struct xlnx_dma_dev *xdev = NULL; - int rv = 0; - - if (!xpdev) - return -EINVAL; - - xdev = (struct xlnx_dma_dev *)(xpdev->dev_hndl); - - if (xdev->conf.bar_num_bypass < 0) { - pr_err("AXI Bridge Master bar is not present\n"); - return -EINVAL; - } - - /* map the AXI Bridge Master bar */ - rv = xpdev_map_bar(xpdev, &xpdev->bypass_bar_regs, - xdev->conf.bar_num_bypass); - if (rv < 0) - return rv; - - *value = readl(xpdev->bypass_bar_regs + reg_addr); - - /* unmap the AXI Bridge Master bar after accessing it */ - xpdev_unmap_bar(xpdev, &xpdev->bypass_bar_regs); - - return 0; -} - -int qdma_device_write_bypass_register(struct xlnx_pci_dev *xpdev, - u32 reg_addr, u32 value) -{ - struct xlnx_dma_dev *xdev = NULL; - int rv = 0; - - if (!xpdev) - return -EINVAL; - - xdev = (struct xlnx_dma_dev *)(xpdev->dev_hndl); - - if (xdev->conf.bar_num_bypass < 0) { - pr_err("AXI Bridge Master bar is not present\n"); - return -EINVAL; - } - - /* map the AXI Bridge Master bar */ - rv = xpdev_map_bar(xpdev, &xpdev->bypass_bar_regs, - xdev->conf.bar_num_bypass); - if (rv < 0) - return rv; - - writel(value, xpdev->bypass_bar_regs + reg_addr); - - /* unmap the AXI Bridge Master bar after accessing it */ - xpdev_unmap_bar(xpdev, &xpdev->bypass_bar_regs); - - return 0; -} - -static int probe_one(struct pci_dev *pdev, const struct pci_device_id *id) -{ - struct qdma_dev_conf conf; - struct xlnx_pci_dev *xpdev = NULL; - unsigned long dev_hndl; - int rv; -#ifdef __x86_64__ - pr_info("%s: func 0x%x, p/v %d/%d,0x%p.\n", - dev_name(&pdev->dev), PCI_FUNC(pdev->devfn), - pdev->is_physfn, pdev->is_virtfn, pdev->physfn); -#endif - memset(&conf, 0, sizeof(conf)); - - conf.qdma_drv_mode = (enum qdma_drv_mode)extract_mod_param(pdev, - DRV_MODE); - conf.vf_max = 0; /* enable via sysfs */ - -#ifndef __QDMA_VF__ - conf.master_pf = extract_mod_param(pdev, MASTER_PF); - if (conf.master_pf) - pr_info("Configuring '%02x:%02x:%x' as master pf\n", - pdev->bus->number, - PCI_SLOT(pdev->devfn), - PCI_FUNC(pdev->devfn)); - -#endif /* #ifdef __QDMA_VF__ */ - pr_info("Driver is loaded in %s(%d) mode\n", - mode_name_list[conf.qdma_drv_mode].name, - conf.qdma_drv_mode); - - if (conf.qdma_drv_mode == LEGACY_INTR_MODE) - intr_legacy_init(); - - conf.intr_rngsz = QDMA_INTR_COAL_RING_SIZE; - conf.pdev = pdev; - - /* initialize all the bar numbers with -1 */ - conf.bar_num_config = -1; - conf.bar_num_user = -1; - conf.bar_num_bypass = -1; - - conf.bar_num_config = extract_mod_param(pdev, CONFIG_BAR); - conf.qsets_max = 0; - conf.qsets_base = -1; - conf.msix_qvec_max = 32; - conf.user_msix_qvec_max = 1; -#ifdef __QDMA_VF__ - conf.fp_flr_free_resource = qdma_flr_resource_free; -#endif - if (conf.master_pf) - conf.data_msix_qvec_max = 5; - else - conf.data_msix_qvec_max = 6; - - rv = qdma_device_open(DRV_MODULE_NAME, &conf, &dev_hndl); - if (rv < 0) - return rv; - - xpdev = xpdev_alloc(pdev, conf.qsets_max); - if (!xpdev) { - rv = -EINVAL; - goto close_device; - } - - xpdev->dev_hndl = dev_hndl; - xpdev->idx = conf.bdf; - - xpdev->cdev_cb.xpdev = xpdev; - rv = qdma_cdev_device_init(&xpdev->cdev_cb); - if (rv < 0) - goto close_device; - - /* Create the files for attributes in sysfs */ - if (conf.master_pf) { - rv = sysfs_create_group(&pdev->dev.kobj, - &pci_master_device_attr_group); - if (rv < 0) - goto close_device; - } else { - rv = sysfs_create_group(&pdev->dev.kobj, - &pci_device_attr_group); - if (rv < 0) - goto close_device; - } - - dev_set_drvdata(&pdev->dev, xpdev); - - return 0; - -close_device: - qdma_device_close(pdev, dev_hndl); - - if (xpdev) - xpdev_free(xpdev); - - return rv; -} - -static void xpdev_device_cleanup(struct xlnx_pci_dev *xpdev) -{ - struct xlnx_qdata *qdata = xpdev->qdata; - struct xlnx_qdata *qmax = qdata + (xpdev->qmax * 2); /* h2c and c2h */ - - for (; qdata != qmax; qdata++) { - if (qdata->xcdev) { - /* if either h2c(1) or c2h(2) bit set, but not both */ - if (qdata->xcdev->dir_init == 1 || - qdata->xcdev->dir_init == 2) { - qdma_cdev_destroy(qdata->xcdev); - } else { /* both bits are set so remove one */ - spin_lock(&xpdev->cdev_lock); - qdata->xcdev->dir_init >>= 1; - spin_unlock(&xpdev->cdev_lock); - } - } - memset(qdata, 0, sizeof(*qdata)); - } -} - -static void remove_one(struct pci_dev *pdev) -{ - struct xlnx_dma_dev *xdev = NULL; - struct xlnx_pci_dev *xpdev = dev_get_drvdata(&pdev->dev); - - if (!xpdev) { - pr_info("%s NOT attached.\n", dev_name(&pdev->dev)); - return; - } - - xdev = (struct xlnx_dma_dev *)(xpdev->dev_hndl); - - pr_info("%s pdev 0x%p, xdev 0x%p, hndl 0x%lx, qdma%05x.\n", - dev_name(&pdev->dev), pdev, xpdev, xpdev->dev_hndl, xpdev->idx); - - if (xdev->conf.master_pf) - sysfs_remove_group(&pdev->dev.kobj, - &pci_master_device_attr_group); - else - sysfs_remove_group(&pdev->dev.kobj, &pci_device_attr_group); - - qdma_cdev_device_cleanup(&xpdev->cdev_cb); - - xpdev_device_cleanup(xpdev); - - qdma_device_close(pdev, xpdev->dev_hndl); - - xpdev_free(xpdev); - - dev_set_drvdata(&pdev->dev, NULL); -} - -#if defined(CONFIG_PCI_IOV) && !defined(__QDMA_VF__) -static int sriov_config(struct pci_dev *pdev, int num_vfs) -{ - struct xlnx_pci_dev *xpdev = dev_get_drvdata(&pdev->dev); - int total_vfs = pci_sriov_get_totalvfs(pdev); - - if (!xpdev) { - pr_info("%s NOT attached.\n", dev_name(&pdev->dev)); - return -EINVAL; - } - - pr_debug("%s pdev 0x%p, xdev 0x%p, hndl 0x%lx, qdma%05x.\n", - dev_name(&pdev->dev), pdev, xpdev, xpdev->dev_hndl, xpdev->idx); - - if (num_vfs > total_vfs) { - pr_info("%s, clamp down # of VFs %d -> %d.\n", - dev_name(&pdev->dev), num_vfs, total_vfs); - num_vfs = total_vfs; - } - - return qdma_device_sriov_config(pdev, xpdev->dev_hndl, num_vfs); -} -#endif - -static pci_ers_result_t qdma_error_detected(struct pci_dev *pdev, - pci_channel_state_t state) -{ - struct xlnx_pci_dev *xpdev = dev_get_drvdata(&pdev->dev); - - switch (state) { - case pci_channel_io_normal: - return PCI_ERS_RESULT_CAN_RECOVER; - case pci_channel_io_frozen: - pr_warn("dev 0x%p,0x%p, frozen state error, reset controller\n", - pdev, xpdev); - pci_disable_device(pdev); - return PCI_ERS_RESULT_NEED_RESET; - case pci_channel_io_perm_failure: - pr_warn("dev 0x%p,0x%p, failure state error, req. disconnect\n", - pdev, xpdev); - return PCI_ERS_RESULT_DISCONNECT; - } - return PCI_ERS_RESULT_NEED_RESET; -} - -static pci_ers_result_t qdma_slot_reset(struct pci_dev *pdev) -{ - struct xlnx_pci_dev *xpdev = dev_get_drvdata(&pdev->dev); - - if (!xpdev) { - pr_info("%s NOT attached.\n", dev_name(&pdev->dev)); - return PCI_ERS_RESULT_DISCONNECT; - } - - pr_info("0x%p restart after slot reset\n", xpdev); - if (pci_enable_device_mem(pdev)) { - pr_info("0x%p failed to renable after slot reset\n", xpdev); - return PCI_ERS_RESULT_DISCONNECT; - } - - pci_set_master(pdev); - pci_restore_state(pdev); - pci_save_state(pdev); - - return PCI_ERS_RESULT_RECOVERED; -} - -static void qdma_error_resume(struct pci_dev *pdev) -{ - struct xlnx_pci_dev *xpdev = dev_get_drvdata(&pdev->dev); - - if (!xpdev) { - pr_info("%s NOT attached.\n", dev_name(&pdev->dev)); - return; - } - - pr_info("dev 0x%p,0x%p.\n", pdev, xpdev); -#ifdef RHEL_RELEASE_VERSION -#if RHEL_RELEASE_VERSION(8, 3) > RHEL_RELEASE_CODE - pci_cleanup_aer_uncorrect_error_status(pdev); -#else - pci_aer_clear_nonfatal_status(pdev); -#endif -#else -#if KERNEL_VERSION(5, 7, 0) <= LINUX_VERSION_CODE - pci_aer_clear_nonfatal_status(pdev); -#else - pci_cleanup_aer_uncorrect_error_status(pdev); -#endif -#endif -} - - -#ifdef __QDMA_VF__ -void qdma_flr_resource_free(unsigned long dev_hndl) -{ - struct xlnx_dma_dev *xdev = (struct xlnx_dma_dev *)(dev_hndl); - struct xlnx_pci_dev *xpdev = dev_get_drvdata(&xdev->conf.pdev->dev); - - xpdev_device_cleanup(xpdev); - xdev->conf.qsets_max = 0; - xdev->conf.qsets_base = -1; -} -#endif - -#if KERNEL_VERSION(4, 13, 0) <= LINUX_VERSION_CODE -static void qdma_reset_prepare(struct pci_dev *pdev) -{ - struct xlnx_pci_dev *xpdev = dev_get_drvdata(&pdev->dev); - struct xlnx_dma_dev *xdev = NULL; - - xdev = (struct xlnx_dma_dev *)(xpdev->dev_hndl); - pr_info("%s pdev 0x%p, xdev 0x%p, hndl 0x%lx, qdma%05x.\n", - dev_name(&pdev->dev), pdev, xpdev, xpdev->dev_hndl, xpdev->idx); - - qdma_device_offline(pdev, xpdev->dev_hndl, XDEV_FLR_ACTIVE); - - /* FLR setting is required for Versal Hard IP */ - if ((xdev->version_info.ip_type == QDMA_VERSAL_HARD_IP) && - (xdev->version_info.device_type == - QDMA_DEVICE_VERSAL_CPM4)) - qdma_device_flr_quirk_set(pdev, xpdev->dev_hndl); - xpdev_queue_delete_all(xpdev); - xpdev_device_cleanup(xpdev); - xdev->conf.qsets_max = 0; - xdev->conf.qsets_base = -1; - - if ((xdev->version_info.ip_type == QDMA_VERSAL_HARD_IP) && - (xdev->version_info.device_type == - QDMA_DEVICE_VERSAL_CPM4)) - qdma_device_flr_quirk_check(pdev, xpdev->dev_hndl); -} - -static void qdma_reset_done(struct pci_dev *pdev) -{ - struct xlnx_pci_dev *xpdev = dev_get_drvdata(&pdev->dev); - - pr_info("%s pdev 0x%p, xdev 0x%p, hndl 0x%lx, qdma%05x.\n", - dev_name(&pdev->dev), pdev, xpdev, xpdev->dev_hndl, xpdev->idx); - qdma_device_online(pdev, xpdev->dev_hndl, XDEV_FLR_ACTIVE); -} - -#elif KERNEL_VERSION(3, 16, 0) <= LINUX_VERSION_CODE -static void qdma_reset_notify(struct pci_dev *pdev, bool prepare) -{ - struct xlnx_pci_dev *xpdev = dev_get_drvdata(&pdev->dev); - struct xlnx_dma_dev *xdev = NULL; - - xdev = (struct xlnx_dma_dev *)(xpdev->dev_hndl); - - pr_info("%s prepare %d, pdev 0x%p, xdev 0x%p, hndl 0x%lx, qdma%05x.\n", - dev_name(&pdev->dev), prepare, pdev, xpdev, xpdev->dev_hndl, - xpdev->idx); - - if (prepare) { - qdma_device_offline(pdev, xpdev->dev_hndl, XDEV_FLR_ACTIVE); - /* FLR setting is not required for 2018.3 IP */ - if ((xdev->version_info.ip_type == QDMA_VERSAL_HARD_IP) && - (xdev->version_info.device_type == - QDMA_DEVICE_VERSAL_CPM4)) - qdma_device_flr_quirk_set(pdev, xpdev->dev_hndl); - xpdev_queue_delete_all(xpdev); - xpdev_device_cleanup(xpdev); - xdev->conf.qsets_max = 0; - xdev->conf.qsets_base = -1; - - if ((xdev->version_info.ip_type == QDMA_VERSAL_HARD_IP) && - (xdev->version_info.device_type == - QDMA_DEVICE_VERSAL_CPM4)) - qdma_device_flr_quirk_check(pdev, xpdev->dev_hndl); - } else - qdma_device_online(pdev, xpdev->dev_hndl, XDEV_FLR_ACTIVE); -} -#endif -static const struct pci_error_handlers qdma_err_handler = { - .error_detected = qdma_error_detected, - .slot_reset = qdma_slot_reset, - .resume = qdma_error_resume, -#if KERNEL_VERSION(4, 13, 0) <= LINUX_VERSION_CODE - .reset_prepare = qdma_reset_prepare, - .reset_done = qdma_reset_done, -#elif KERNEL_VERSION(3, 16, 0) <= LINUX_VERSION_CODE - .reset_notify = qdma_reset_notify, -#endif -}; - -static struct pci_driver pci_driver = { - .name = DRV_MODULE_NAME, - .id_table = pci_ids, - .probe = probe_one, - .remove = remove_one, -/* .shutdown = shutdown_one, */ -#if defined(CONFIG_PCI_IOV) && !defined(__QDMA_VF__) - .sriov_configure = sriov_config, -#endif - .err_handler = &qdma_err_handler, -}; - -static int __init qdma_mod_init(void) -{ - int rv; - - pr_info("%s", version); - - rv = libqdma_init(num_threads, NULL); - if (rv < 0) - return rv; - - rv = xlnx_nl_init(); - if (rv < 0) - return rv; - - rv = qdma_cdev_init(); - if (rv < 0) - return rv; - - return pci_register_driver(&pci_driver); -} - -static void __exit qdma_mod_exit(void) -{ - /* unregister this driver from the PCI bus driver */ - pci_unregister_driver(&pci_driver); - - xlnx_nl_exit(); - - qdma_cdev_cleanup(); - - libqdma_exit(); -} - -module_init(qdma_mod_init); -module_exit(qdma_mod_exit); diff --git a/QDMA/linux-kernel/driver/src/qdma_mod.h b/QDMA/linux-kernel/driver/src/qdma_mod.h deleted file mode 100755 index 3cd04a511..000000000 --- a/QDMA/linux-kernel/driver/src/qdma_mod.h +++ /dev/null @@ -1,238 +0,0 @@ -/* - * This file is part of the Xilinx DMA IP Core driver for Linux - * - * Copyright (c) 2017-2022, Xilinx, Inc. All rights reserved. - * Copyright (c) 2022-2023, Advanced Micro Devices, Inc. All rights reserved. - * - * This source code is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * The full GNU General Public License is included in this distribution in - * the file called "COPYING". - */ - -#ifndef __QDMA_MODULE_H__ -#define __QDMA_MODULE_H__ -/** - * @file - * @brief This file contains the declarations for qdma pcie kernel module - * - */ -#include -#include -#include -#include - -#include "libqdma/libqdma_export.h" -#include "cdev.h" - - -/** - * enum qdma_drv_mod_param_type - Indicate the module parameter type - * - * QDMA PF/VF drivers takes module parameters mode and config bar is the same - * format, This enum is unsed to identify the parameter type - * - */ -enum qdma_drv_mod_param_type { - /** @DRV_MODE : Driver mode mod param */ - DRV_MODE, - /** @CONFIG_BAR : Config Bar mod param */ - CONFIG_BAR, - /** @MASTER_PF : Master PF mod param */ - MASTER_PF, -}; - -/** - * @struct - xlnx_qdata - * @brief queue data variables send while read/write request - */ -struct xlnx_qdata { - unsigned long qhndl; /**< Queue handle */ - struct qdma_cdev *xcdev; /**< qdma character device details */ -}; - -#define XNL_EBUFLEN 256 -struct xlnx_nl_work_q_ctrl { - unsigned short qidx; - unsigned short qcnt; - u8 is_qp:1; - u8 q_type:2; -}; - -struct xlnx_nl_work { - struct work_struct work; - struct xlnx_pci_dev *xpdev; - wait_queue_head_t wq; - unsigned int q_start_handled; - unsigned int buflen; - char *buf; - struct xlnx_nl_work_q_ctrl qctrl; - int ret; -}; - -/** - * @struct - xlnx_pci_dev - * @brief xilinx pcie device data members - */ -struct xlnx_pci_dev { - struct list_head list_head; /**< device list */ - struct pci_dev *pdev; /**< pointer to struct pci_dev */ - unsigned long dev_hndl; /**< device handle*/ - struct workqueue_struct *nl_task_wq; /**< netlink request work queue */ - struct qdma_cdev_cb cdev_cb; /**< character device call back data*/ - spinlock_t cdev_lock; /**< character device lock*/ - unsigned int qmax; /**< max number of queues for device*/ - unsigned int idx; /**< device index*/ - void __iomem *user_bar_regs; /**< PCIe AXI Master Lite bar */ - void __iomem *bypass_bar_regs; /**< PCIe AXI Bridge Master bar*/ - struct xlnx_qdata *qdata; /**< queue data*/ -}; - -/*****************************************************************************/ -/** - * xpdev_list_dump() - list the qdma devices - * - * @param[in] buflen: buffer length - * @param[out] buf: - * error message buffer, can be NULL/0 (i.e., optional) - * - * @return 0: success - * @return <0: failure - *****************************************************************************/ -int xpdev_list_dump(char *buf, int buflen); - -/*****************************************************************************/ -/** - * xpdev_find_by_idx() - qdma pcie kernel module api to - * find the qdma device by index - * - * @param[in] idx: qdma device index - * @param[in] buflen: buffer length - * @param[out] buf: - * error message buffer, can be NULL/0 (i.e., optional) - * - * @return 0: pointer to xlnx_pci_dev - * @return NULL: failure - *****************************************************************************/ -struct xlnx_pci_dev *xpdev_find_by_idx(unsigned int idx, char *buf, - int buflen); - -/*****************************************************************************/ -/** - * xpdev_queue_get() - qdma pcie kernel module api to get a queue information - * - * @param[in] xpdev: pointer to xlnx_pci_dev - * @param[in] qidx: queue index - * @param[in] c2h: flag to indicate the queue direction (c2h/h2c) - * @param[in] check_qhndl: flag for validating the data - * @param[in] ebuflen: buffer length - * @param[out] ebuf: - * error message buffer, can be NULL/0 (i.e., optional) - * - * @return 0: queue information - * @return NULL: failure - *****************************************************************************/ -struct xlnx_qdata *xpdev_queue_get(struct xlnx_pci_dev *xpdev, - unsigned int qidx, u8 q_type, bool check_qhndl, - char *ebuf, int ebuflen); - -/*****************************************************************************/ -/** - * xpdev_queue_add() - qdma pcie kernel module api to add a queue - * - * @param[in] xpdev: pointer to xlnx_pci_dev - * @param[in] qconf: queue configuration - * @param[in] ebuflen: buffer length - * @param[out] ebuf: - * error message buffer, can be NULL/0 (i.e., optional) - * - * @return 0: success - * @return <0: failure - *****************************************************************************/ -int xpdev_queue_add(struct xlnx_pci_dev *xpdev, struct qdma_queue_conf *qconf, - char *ebuf, int ebuflen); - -/*****************************************************************************/ -/** - * xpdev_queue_delete() - qdma pcie kernel module api to delete a queue - * - * @param[in] xpdev: pointer to xlnx_pci_dev - * @param[in] qidx: queue index - * @param[in] c2h: flag to indicate the queue direction (c2h/h2c) - * @param[in] ebuflen: buffer length - * @param[out] ebuf: - * error message buffer, can be NULL/0 (i.e., optional) - * - * @return 0: success - * @return <0: failure - *****************************************************************************/ -int xpdev_queue_delete(struct xlnx_pci_dev *xpdev, unsigned int qidx, - u8 q_type, char *ebuf, int ebuflen); - -int xpdev_nl_queue_start(struct xlnx_pci_dev *xpdev, void *nl_info, u8 is_qp, - u8 q_type, unsigned short qidx, unsigned short qcnt); - -/*****************************************************************************/ -/** - * qdma_device_read_user_register() - read AXI Master Lite bar register - * - * @param[in] xpdev: pointer to xlnx_pci_dev - * @param[in] reg_addr: register address - * @param[out] value: pointer to hold the register value - * - * @return 0: success - * @return <0: failure - *****************************************************************************/ -int qdma_device_read_user_register(struct xlnx_pci_dev *xpdev, - u32 reg_addr, u32 *value); - -/*****************************************************************************/ -/** - * qdma_device_write_user_register() - write AXI Master Lite bar register - * - * @param[in] xpdev: pointer to xlnx_pci_dev - * @param[in] reg_addr: register address - * @param[in] value: register value to be written - * - * @return 0: success - * @return <0: failure - *****************************************************************************/ -int qdma_device_write_user_register(struct xlnx_pci_dev *xpdev, - u32 reg_addr, u32 value); - -/*****************************************************************************/ -/** - * qdma_device_read_bypass_register() - read AXI Bridge Master bar register - * - * @param[in] xpdev: pointer to xlnx_pci_dev - * @param[in] reg_addr: register address - * @param[out] value: pointer to hold the register value - * - * @return 0: success - * @return <0: failure - *****************************************************************************/ -int qdma_device_read_bypass_register(struct xlnx_pci_dev *xpdev, - u32 reg_addr, u32 *value); - -/*****************************************************************************/ -/** - * qdma_device_write_bypass_register() - write AXI Bridge Master bar register - * - * @param[in] xpdev: pointer to xlnx_pci_dev - * @param[in] reg_addr: register address - * @param[in] value: register value to be written - * - * @return 0: success - * @return <0: failure - *****************************************************************************/ -int qdma_device_write_bypass_register(struct xlnx_pci_dev *xpdev, - u32 reg_addr, u32 value); - -#endif /* ifndef __QDMA_MODULE_H__ */ diff --git a/QDMA/linux-kernel/driver/src/version.h b/QDMA/linux-kernel/driver/src/version.h deleted file mode 100755 index 572742884..000000000 --- a/QDMA/linux-kernel/driver/src/version.h +++ /dev/null @@ -1,47 +0,0 @@ -/* - * This file is part of the Xilinx DMA IP Core driver for Linux - * - * Copyright (c) 2017-2022, Xilinx, Inc. All rights reserved. - * Copyright (c) 2022-2023, Advanced Micro Devices, Inc. All rights reserved. - * - * This source code is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * The full GNU General Public License is included in this distribution in - * the file called "COPYING". - */ - -#ifndef __QDMA_VERSION_H__ -#define __QDMA_VERSION_H__ - -#include "libqdma/version.h" - -#ifdef __QDMA_VF__ -#define DRV_MODULE_NAME "qdma-vf" -#define DRV_MODULE_DESC "Xilinx QDMA VF Reference Driver" -#else -#define DRV_MODULE_NAME "qdma-pf" -#define DRV_MODULE_DESC "Xilinx QDMA PF Reference Driver" -#endif /* #ifdef __QDMA_VF__ */ -#define DRV_MODULE_RELDATE "Sept 2023" - -#define DRV_MOD_MAJOR 2023 -#define DRV_MOD_MINOR 2 -#define DRV_MOD_PATCHLEVEL 0 - -#define DRV_MODULE_VERSION \ - __stringify(DRV_MOD_MAJOR) "." \ - __stringify(DRV_MOD_MINOR) "." \ - __stringify(DRV_MOD_PATCHLEVEL) "." \ - __stringify(LIBQDMA_VERSION_PATCH) "." \ - -#define DRV_MOD_VERSION_NUMBER \ - ((DRV_MOD_MAJOR)*10000 + (DRV_MOD_MINOR)*1000 + DRV_MOD_PATCHLEVEL) - -#endif /* ifndef __QDMA_VERSION_H__ */ diff --git a/QDMA/linux-kernel/license.txt b/QDMA/linux-kernel/license.txt deleted file mode 100755 index 8eac7fb43..000000000 --- a/QDMA/linux-kernel/license.txt +++ /dev/null @@ -1,14 +0,0 @@ -/* - * This source code is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * The full GNU General Public License is included in this distribution in - * the file called "COPYING". - */ - diff --git a/QDMA/linux-kernel/scripts/datafile_16bit_pattern.bin b/QDMA/linux-kernel/scripts/datafile_16bit_pattern.bin deleted file mode 100755 index 1b50cdd57bcc0fb5c0e6ae027560cd03062b5434..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 262144 zcmWL6g96~X0szt4Ox-l;+O}=mwr$JW8_dPIGq0nw0X zL^LLv5KW0@M027A(UNFIv?kgRZHab7d!hr;k?2HpCb|$^iEc!9q6g8F=tcA<`Vf7I ze#C!7e_{YJkQhV^CWa70iDATWVgxag7)6XG#t>tPam09H0x^-8L`){85L1b1#B^c? zF_V}@%qHd#bBTGxd}0BykXS@4CYBIOiDkrcVg<31SVgQR)(~rnb;NpN1F@0VL~JIu z5L=0D#CBo_v6I+E>?ZaQdx?F-e&PUekT^sfCXNtCiDSfZ;skM$I7OT$&JbsbbHsV# z0&$VJL|i7W5Lbz7#C75Zag(@3+$Qc2cZqw%ec}P}ka$EqCY}&aiD$%f;sx=NctyM> z-Vkqzcf@<*1M!jgM0_T`5MPOJ#CPHc@ss#P{3iYoe~EttL6Rgz(j-H&BuDb3K#HV9 z%A`W7q(r^wUf8S*T7jyz9Z zATN@a$jjsv@+x_ayiVRAZ<4pj+vFYcE_sixv1P!9x5-DkIGLKpbAojsKQhcswh>A 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zxN2N2t{&HjYsR(W+Hsw@Zd@;}A2)~_#*N~}ag(@d+$?S$w}@NDt>V^ko49S9Gh$qIA;>q!pcxpT?o*vJLXU4PQ+3}osZagoZA1{a(#*5;`@sfCHyewWG zuZUO1tK!x1ns{xzE?ysRh&RTY;?41vcx${Z-X8CWcgDNo-SM7yZ@e$wA0LPh#)sm= z@sapwd@Md5pNLP!r{dG`nfPpcE+=s_-cGDz8>F*Z^pOc+wqh(E@k;?MDy_-p(v{vQ8`f5yM! z-|?ULZ~QMNVlt*;I%Z-v=3+h;VlkFtIR>#3tFactSdWd^jIG#?ofyS#?8SZ@#5fM) ID30U*0ZEV@;{X5v diff --git a/QDMA/linux-kernel/scripts/license-for-datafile_16bit_pattern.txt b/QDMA/linux-kernel/scripts/license-for-datafile_16bit_pattern.txt deleted file mode 100755 index 15469adbf..000000000 --- a/QDMA/linux-kernel/scripts/license-for-datafile_16bit_pattern.txt +++ /dev/null @@ -1,19 +0,0 @@ -/* - * THIS BINARY FILE IS GENERATED FROM XILINX TOOLS AND IS AVAILABLE EXCLUSIVELY IN BINARY FORMAT. - * - * Copyright © 2022 Xilinx, Inc. - * - * Redistribution and use in binary form only, without modification, is permitted provided that the following conditions are met: - * - * Redistributions must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. - * The name of Xilinx, Inc. may not be used to endorse or promote products redistributed with this software without specific prior written permission. - * THIS SOFTWARE IS PROVIDED BY XILINX, INC. "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, - * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL XILINX, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR - * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - */ \ No newline at end of file diff --git a/QDMA/linux-kernel/scripts/qdma_generate_conf_file.sh b/QDMA/linux-kernel/scripts/qdma_generate_conf_file.sh deleted file mode 100755 index c66cb1ad2..000000000 --- a/QDMA/linux-kernel/scripts/qdma_generate_conf_file.sh +++ /dev/null @@ -1,121 +0,0 @@ -#/* -# * This file is part of the Xilinx DMA IP Core driver for Linux -# * -# * Copyright (c) 2017-2022, Xilinx, Inc. All rights reserved. -# * Copyright (c) 2022-2023, Advanced Micro Devices, Inc. All rights reserved. -# * -# * This source code is free software; you can redistribute it and/or modify it -# * under the terms and conditions of the GNU General Public License, -# * version 2, as published by the Free Software Foundation. -# * -# * This program is distributed in the hope that it will be useful, but WITHOUT -# * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -# * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for -# * more details. -# * -# * The full GNU General Public License is included in this distribution in -# * the file called "COPYING". -# */ - - -#!/bin/bash -# -# Simple script to generate conf file for module params. -# - - -function print_help() { - echo "" - echo "Usage : $0 " - echo "Ex : $0 0x06 4 0 0 0" - echo " : PF Bus Number" - echo "" - echo " : Number of PFs supported, Default - 4" - echo "" - echo " : Mode, Default - 0 (Auto)" - echo "" - echo " : Config Bar number, Default - 0" - echo "" - echo " : Master PF, Default - 0" - echo "" - echo "" - echo "" - exit 1 -} - -if [ $# -lt 1 ]; then - echo "Invalid arguements." - print_help - exit; -fi; - -bus_num=$1 -num_pfs=4 -mode=0 -config_bar=0 -master_pf=0 - -if [ ! -z $2 ]; then - num_pfs=$2 -fi - -if [ ! -z $3 ]; then - mode=$3 -fi - -if [ ! -z $4 ]; then - config_bar=$4 -fi - -if [ ! -z $5 ]; then - master_pf=$5 -fi - -generate_conf() -{ - conf_file="qdma.conf" - echo -n "options qdma-pf mode=" > conf_file - for ((j = 0; j < ${num_pfs}; j++)) - do - echo -n "${bus_num}:${j}:${mode}" >> conf_file - if [ $j != $((${num_pfs} - 1)) ]; then - echo -n "," >> conf_file - fi - done - echo -e "" >> conf_file - echo -n "options qdma-pf config_bar=" >> conf_file - for ((j = 0; j < ${num_pfs}; j++)) - do - echo -n "${bus_num}:${j}:${config_bar}" >> conf_file - if [ $j != $((${num_pfs} - 1)) ]; then - echo -n "," >> conf_file - fi - done - echo -e "" >> conf_file - echo -n "options qdma-pf master_pf=${bus_num}:${master_pf}" >> conf_file - - echo -e "" >> conf_file - echo -n "options qdma-vf mode=" >> conf_file - for ((j = 0; j < ${num_pfs}; j++)) - do - echo -n "${bus_num}:${j}:${mode}" >> conf_file - if [ $j != $((${num_pfs} - 1)) ]; then - echo -n "," >> conf_file - fi - done - echo -e "" >> conf_file - echo -n "options qdma-vf config_bar=" >> conf_file - for ((j = 0; j < ${num_pfs}; j++)) - do - echo -n "${bus_num}:${j}:${config_bar}" >> conf_file - if [ $j != $((${num_pfs} - 1)) ]; then - echo -n "," >> conf_file - fi - done - - rm -rf /etc/modprobe.d/qdma.conf - cp conf_file /etc/modprobe.d/qdma.conf - rm -rf conf_file -} - -generate_conf diff --git a/QDMA/linux-kernel/scripts/qdma_run_test_mm_vf.sh b/QDMA/linux-kernel/scripts/qdma_run_test_mm_vf.sh deleted file mode 100755 index 1692277c4..000000000 --- a/QDMA/linux-kernel/scripts/qdma_run_test_mm_vf.sh +++ /dev/null @@ -1,162 +0,0 @@ -#/* -# * This file is part of the Xilinx DMA IP Core driver for Linux -# * -# * Copyright (c) 2017-2022, Xilinx, Inc. All rights reserved. -# * Copyright (c) 2022-2023, Advanced Micro Devices, Inc. All rights reserved. -# * -# * This source code is free software; you can redistribute it and/or modify it -# * under the terms and conditions of the GNU General Public License, -# * version 2, as published by the Free Software Foundation. -# * -# * This program is distributed in the hope that it will be useful, but WITHOUT -# * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -# * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for -# * more details. -# * -# * The full GNU General Public License is included in this distribution in -# * the file called "COPYING". -# */ - - -#!/bin/bash -# -# Simple run script to test QDMA in VF AXI-MM mode. -# -# VF AXI-MM Transfer -# - H2C operation is performed to send data to BRAM on the FPGA. -# - C2H operation is performed to reads data from BRAM. -# - C2H data is stored in a local file 'out_mm0_$qid', which will be compared to original file for correctness. - -################################################ -# User Configurable Parameters -################################################ -iteration=$1 # [Optional] Iterations -size=$2 # [Optional] Size per payload packet - -################################################ -# Hard Coded Parameters -################################################ -q_per_vf=1 -vf=00080 -size_max=4096 -host_adr_high=0 -infile='./datafile_16bit_pattern.bin' - - -################################################ -# Input check -################################################ -if [ "$1" == "-h" ]; then - echo "Example: qdma_run_test_st_vf.sh [iteration] [size(in byte)]" - echo "Example: qdma_run_test_st_vf.sh This will run VF MM test in random mode" - exit -fi - -if [ -z $2 ] || [ $# -eq 0 ] ; then - echo "Run VF MM test in random mode" - sleep 3 -fi - -if [ -z $iteration ]; then - iteration=1 -fi - -if [ ! -z $size ]; then - f_size=1 -else - f_size=0 -fi - -################################################# -# Helper Functions -################################################ - -function randomize_tx_params() { - #random host address - if [ $host_adr_high -ne 0 ]; then - hst_adr1=$RANDOM - hst_adr1=$((hst_adr1 % host_adr_high)) - else - hst_adr1=0 - fi - - # byte size - size=$RANDOM - if [ $size -eq 0 ]; then - size=$(($RANDOM % 64 + 1)) ## for random number between 1 and 64 - else - size=$((size % $size_max)) - fi - - # Correct if size is odd - even=$((size%2)) - if [ $even -eq 1 ];then - size=$((size+1)) - fi -} - - -function queue_start() { - echo "---- Queue Start $2 ----" - dma-ctl qdma$1 q add idx $2 mode $3 dir bi - dma-ctl qdma$1 q start idx $2 dir bi -} - -function cleanup_queue() { - echo "---- Queue Clean up $2 ----" - dma-ctl qdma$1 q stop idx $2 dir bi - dma-ctl qdma$1 q del idx $2 dir bi -} - -vfs=`dma-ctl dev list | grep qdmavf | cut -d' ' -f1`; - -echo "**** AXI-MM Start ****" -for vfsdev in $vfs;do - vf="${vfsdev#*f}" - q_per_vf="$(dma-ctl dev list |grep qdmavf$vf | cut -d ' ' -f 3 | cut -d ',' -f 1 | xargs)" - - for ((i=0; i< $q_per_vf; i++)) do - # Setup for Queues - qid=$i - dev_mm_c2h="/dev/qdmavf$vf-MM-$qid" - dev_mm_h2c="/dev/qdmavf$vf-MM-$qid" - loop=1 - - out_mm="out_mm0_"$qid - # Open the Queue for AXI-MM streaming interface. - queue_start vf$vf $qid mm - - while [ "$loop" -le $iteration ] - do - # Determine if DMA is targeted @ random host address - if [ $f_size -eq 1 ]; then - hst_adr1=0 - else - randomize_tx_params - fi - - # H2C transfer - dma-to-device -d $dev_mm_h2c -f $infile -s $size -o $hst_adr1 - - # C2H transfer - dma-from-device -d $dev_mm_c2h -f $out_mm -s $size -o $hst_adr1 - - # Compare file for correctness - cmp $out_mm $infile -n $size - - if [ $? -eq 1 ]; then - echo "#### Test ERROR. Queue $qid data did not match ####" - exit 1 - else - echo "**** Test pass. Queue $qid" - fi - - wait - - ((loop++)) - done - # Close the Queues - cleanup_queue vf$vf $qid - done -done -echo "**** AXI-MM completed ****" diff --git a/QDMA/linux-kernel/scripts/qdma_run_test_pf.sh b/QDMA/linux-kernel/scripts/qdma_run_test_pf.sh deleted file mode 100755 index f49bead3d..000000000 --- a/QDMA/linux-kernel/scripts/qdma_run_test_pf.sh +++ /dev/null @@ -1,508 +0,0 @@ -#/* -# * This file is part of the Xilinx DMA IP Core driver for Linux -# * -# * Copyright (c) 2017-2022, Xilinx, Inc. All rights reserved. -# * Copyright (c) 2022-2023, Advanced Micro Devices, Inc. All rights reserved. -# * -# * This source code is free software; you can redistribute it and/or modify it -# * under the terms and conditions of the GNU General Public License, -# * version 2, as published by the Free Software Foundation. -# * -# * This program is distributed in the hope that it will be useful, but WITHOUT -# * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -# * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for -# * more details. -# * -# * The full GNU General Public License is included in this distribution in -# * the file called "COPYING". -# */ - - -#!/bin/bash -# -# Simple run script to test QDMA in AXI-MM and AXI-St mode. -# -# AXI-MM Transfer -# First H2C operation is performed for 1KBytes, this will write 1Kbytes of data to BRAM on card side. -# Then C2H operation is performed for 1KBytes. DMA reads data from BRAM and will transfer -# to local file 'out_mm0_0', which will be compared to original file for correctness. -# -# AXI-ST H2C Transfer -# for H2C Streaming transfer data needs to be a per-defined data. 16 bit incremental data. -# Data file is provided with the script. -# H2C operation is performed, Data is read from Host memory and send to Card side. There is a data checker -# on the card side which will check the data for correctness and will log the result in a register. -# Script then read the register to check for results. -# -# -# AXI-ST C2H Transfer -# For C2H operation there is a data generator on the Card side which needs to be setup to generate data. -# Qid, transfer length and number of paket are written before C2H transfer. Then -# C2H transfer is started by writing to register. C2H operation is completed and the data is written to 'out_st0_0" -# file which then is compared to a per-defined data file. The data generator will only generate pre-defined -# data, so data comparison will need to be done with 'datafile_16bit_pattern.bin' file only. -# -# - - -function print_help() { - echo "" - echo "Usage : $0 " - echo "Ex : $0 06000 0 4 1 1 1 1" - echo " : PF Bus device function in bbddf format ex:06000" - echo "" - echo " : qid start" - echo "" - echo " : number of queue from qid_start" - echo " Default - 04 " - echo "" - echo " : Enable desc bypass" - echo " Default - 0 " - echo "" - echo " : Enable prefetch" - echo " Default - 0 " - echo "" - echo " : Enable prefetch bypass" - echo " Default - 0 " - echo "" - echo " : Apply Function Level Reset" - echo " Default - 0 " - echo "" - echo "" - echo "" - exit 1 -} - -if [ $# -lt 2 ]; then - echo "Invalid arguements." - print_help - exit; -fi; - -pf=$1 -qid_start=$2 -num_qs=4 -desc_byp=0 -pftch=0 -pftch_byp=0 -flr_on=0 - -if [ ! -z $3 ]; then - num_qs=$3 -fi - -if [ ! -z $4 ]; then #if arg4 is there byp enable - desc_byp=$4 -fi - -if [ ! -z $5 ]; then #if arg5 is there pfetch enable - pftch=$5 -fi - -if [ ! -z $6 ]; then #if arg6 is there pfetch byp enable - pftch_byp=$6 -fi -if [ ! -z $6 ]; then #if arg7 is there FLR enable - flr_on=$7 -fi - -echo "$pf $qid_start $num_qs $desc_byp $pftch $pftch_byp" -size=1024 -num_pkt=1 #number of packets not more then 64 -infile='./datafile_16bit_pattern.bin' -declare -a bypass_mode_lst=(NO_BYPASS_MODE DESC_BYPASS_MODE CACHE_BYPASS_MODE SIMPLE_BYPASS_MODE) - - -function get_dev () { - pf_list="$(dma-ctl dev list | grep qdma | grep -v qdmavf)" - echo "$pf_list" - while read -r line; do - IFS=$'\t ,~' read -r -a array <<< "$line" - qdmabdf=${array[0]} - bdf_array+=("${qdmabdf#*a}") - full_bdf_array+=("${array[1]}") - num_queue_per_pf+=("${array[4]}") - qbase_array+=("${array[5]}") - done <<< "$pf_list" - -} - -function set_flr() { - echo "Applying function level reset" - for pf_bdf in ${bdf_array[@]}; do - pci_bus=${pf_bdf:0:2} - pci_device=${pf_bdf:2:2} - pci_func=${pf_bdf:4:1} - echo "echo 1 > /sys/bus/pci/devices/0000\:${pci_bus}\:${pci_device}.${pci_func}/reset" - echo 1 > /sys/bus/pci/devices/0000\:${pci_bus}\:${pci_device}.${pci_func}/reset - done -} - -function set_bypass_mode() { - dev=$1 - mode=$2 - dir=$3 - bypass=$4 - local reg_val=0x00; - - if [ $mode == mm ]; then - case $dir in - h2c) - if [ $bypass == DESC_BYPASS_MODE ]; then - echo "setting DESC_BYPASS_MODE for ${mode}-$dir" - reg_val=0x1; - else - reg_val=0x0; - fi - - ;; - c2h) - if [ $bypass == DESC_BYPASS_MODE ]; then - echo "setting DESC_BYPASS_MODE for ${mode}-$dir" - reg_val=0x2; - else - reg_val=0x0; - fi - - ;; - bi) - if [ $bypass == DESC_BYPASS_MODE ]; then - echo "setting DESC_BYPASS_MODE for ${mode}-$dir" - reg_val=0x3; - else - reg_val=0x0; - fi - ;; - esac - else - case $dir in - h2c) - case $bypass in - CACHE_BYPASS_MODE) - echo "setting CACHE_BYPASS_MODE for ${mode}-$dir" - reg_val=0x1; - ;; - SIMPLE_BYPASS_MODE) - echo "setting SIMPLE_BYPASS_MODE for ${mode}-$dir" - reg_val=0x1; - ;; - *) - echo "setting NO_BYPASS_MODE for ${mode}-$dir" - reg_val=0x00; - ;; - esac - ;; - c2h) - case $bypass in - CACHE_BYPASS_MODE) - echo "setting CACHE_BYPASS_MODE for ${mode}-$dir" - reg_val=0x2; - ;; - SIMPLE_BYPASS_MODE) - echo "setting SIMPLE_BYPASS_MODE for ${mode}-$dir" - reg_val=0x4; - ;; - *) - echo "setting NO_BYPASS_MODE for ${mode}-$dir" - reg_val=0x00; - ;; - esac - ;; - bi) - case $bypass in - CACHE_BYPASS_MODE) - echo "setting CACHE_BYPASS_MODE for ${mode}-$dir" - reg_val=0x3; - ;; - SIMPLE_BYPASS_MODE) - echo "setting SIMPLE_BYPASS_MODE for ${mode}-$dir" - reg_val=0x5; - ;; - *) - echo "setting NO_BYPASS_MODE for ${mode}-$dir" - reg_val=0x00; - ;; - esac - ;; - esac - fi - dma-ctl qdma$dev reg write bar 2 0x90 $reg_val -} - -function get_bypass_mode() { - byp_mode=0 - if [ $1 == mm ]; then - if [ $desc_byp -eq 1 ]; then - byp_mode=1 - fi - else - if [ $desc_byp -eq 1 ] && [ $pftch_byp -eq 0 ]; then - byp_mode=2 - elif [ $desc_byp -eq 1 ] && [ $pftch_byp -eq 1 ]; then - byp_mode=3 - fi - fi - echo $byp_mode -} - -function queue_start() { - echo "setting up qdma$1-$3-$2" - dma-ctl qdma$1 q add idx $2 mode $3 dir $4 >> ./run_pf.log 2>&1 - if [ $? -ne 0 ]; then - echo "q add failed for qdma$1-$3-$2" - return - fi - bypass_mode=$(get_bypass_mode $3 $4) - set_bypass_mode $1 $3 $4 ${bypass_mode_lst[${bypass_mode}]} - if [ $3 == mm -o $4 == h2c ]; then - if [ $desc_byp -eq 1 ]; then - dma-ctl qdma$1 q start idx $2 dir $4 desc_bypass_en >> ./run_pf.log 2>&1 - else - dma-ctl qdma$1 q start idx $2 dir $4 >> ./run_pf.log 2>&1 - fi - else - if [ $desc_byp -eq 1 ] && [ $pftch -eq 0 ]; then - if [ $pftch_byp -eq 0 ]; then - dma-ctl qdma$1 q start idx $2 dir $4 desc_bypass_en >> ./run_pf.log 2>&1 - else - dma-ctl qdma$1 q start idx $2 dir $4 desc_bypass_en pfetch_bypass_en >> ./run_pf.log 2>&1 - fi - elif [ $desc_byp -eq 1 ] && [ $pftch -eq 1 ]; then - if [ $pftch_byp -eq 0 ]; then - dma-ctl qdma$1 q start idx $2 dir $4 desc_bypass_en pfetch_en >> ./run_pf.log 2>&1 - else - dma-ctl qdma$1 q start idx $2 dir $4 desc_bypass_en pfetch_en pfetch_bypass_en >> ./run_pf.log 2>&1 - fi - elif [ $desc_byp -eq 0 ] && [ $pftch -eq 1 ] ; then # - if [ $pftch_byp -eq 0 ]; then - dma-ctl qdma$1 q start idx $2 dir $4 pfetch_en >> ./run_pf.log 2>&1 - else - echo "Invalid case of bypass mode" >> ./run_pf.log 2>&1 - dma-ctl qdma$1 q del idx $2 dir bi >> ./run_pf.log 2>&1 - return 1 - fi - else - if [ $pftch_byp -eq 0 ]; then - dma-ctl qdma$1 q start idx $2 dir $4>> ./run_pf.log 2>&1 - else - echo "Invalid case of bypass mode" >> ./run_pf.log 2>&1 - dma-ctl qdma$1 q del idx $2 dir bi >> ./run_pf.log 2>&1 - return 1 - fi - fi - fi - if [ $? -ne 0 ]; then - echo "q start failed for qdma$1-$3-$2-$4" - dma-ctl qdma$1 q del idx $2 dir bi >> ./run_pf.log 2>&1 - return $? - fi - - - return 0 -} - -function cleanup_queue() { - echo "cleaning up qdma$1-$3-$2" - dma-ctl qdma$1 q stop idx $2 dir $4 >> ./run_pf.log 2>&1 - dma-ctl qdma$1 q del idx $2 dir $4 >> ./run_pf.log 2>&1 - -} - - -# Find AXI Master Lite bar -function get_user_bar () { - local pf_bdf=$1 - tmp=`dma-ctl qdma$pf_bdf reg read bar 0 0x10C | grep "0x10c" | cut -d '=' -f2 | cut -d 'x' -f2 | cut -d '.' -f1` - bar_ext=$(printf '%x\n' "$(( 0x$tmp & 0x00000f ))") - - if [ $bar_ext -eq 2 ]; then - usr_bar=1 - elif [ $bar_ext -eq 4 ];then - usr_bar=2 - fi -} - - -function run_mm_h2c_c2h () { - for pf_bdf in ${bdf_array[@]}; do - echo "***********************************************" 2>&1 | tee -a ./run_pf.log - echo "AXI-MM for Func $pf_bdf Start" 2>&1 | tee -a ./run_pf.log - get_user_bar $pf_bdf - for ((i=$qid_start; i < (($qid_start + $num_qs)); i++)); do - # Setup for Queues - qid=$i - dev_mm_c2h="/dev/qdma$pf_bdf-MM-$qid" - dev_mm_h2c="/dev/qdma$pf_bdf-MM-$qid" - - out_mm="/tmp/out_mm"$pf_bdf"_"$qid - # Open the Queue for AXI-MM streaming interface. - queue_start $pf_bdf $qid mm bi - if [ $? -ne 0 ]; then - echo "q setup for qdma$pf_bdf-MM-$qid failed" - continue - fi - echo "setup for qdma$pf_bdf-MM-$qid done" - # H2C transfer - dma-to-device -d $dev_mm_h2c -f $infile -s $size >> ./run_pf.log 2>&1 - - # C2H transfer - dma-from-device -d $dev_mm_c2h -f $out_mm -s $size >> ./run_pf.log 2>&1 - - # Compare file for correctness - cmp $out_mm $infile -n $size - if [ $? -eq 1 ]; then - echo "#### Test ERROR. Queue $qid data did not match ####" - dma-ctl qdma$pf_bdf q dump idx $qid >> ./run_pf.log 2>&1 - dma-ctl qdma$pf_bdf reg dump >> ./run_pf.log 2>&1 - else - echo "**** Test pass. Queue $qid" - fi - # Close the Queues - cleanup_queue $pf_bdf $qid st bi - echo "-----------------------------------------------" - done - echo "AXI-MM for Func $pf_bdf End" 2>&1 | tee -a ./run_pf.log - echo "***********************************************" 2>&1 | tee -a ./run_pf.log - done -} - - - -function run_st_h2c () { - - # AXI-ST H2C transfer - for pf_bdf in "${bdf_array[@]}"; do - echo "***********************************************" 2>&1 | tee -a ./run_pf.log - echo "AXI-ST H2C for Func $pf_bdf Start" 2>&1 | tee -a ./run_pf.log - get_user_bar $pf_bdf - for ((i=$qid_start; i < (($qid_start + $num_qs)); i++)); do - # Setup for Queues - qid=$i - queue_start $pf_bdf $qid st h2c # open the Queue for AXI-ST streaming interface. - - dev_st_h2c="/dev/qdma$pf_bdf-ST-$qid" - - # Clear H2C match from previous runs. this register is in card side. - # MAtch clear register is on offset 0x0C - dma-ctl qdma$pf_bdf reg write bar $usr_bar 0x0C 0x1 >> ./run_pf.log 2>&1 # clear h2c Match register. - - # do H2C Transfer - dma-to-device -d $dev_st_h2c -f $infile -s $size >> ./run_pf.log 2>&1 - - if [ $? -ne 0 ]; then - echo "#### ERROR Test failed. Transfer failed ####" - cleanup_queue $pf_bdf $qid st h2c - continue - fi - # check for H2C data match. MAtch register is in offset 0x10. - pass=`dma-ctl qdma$pf_bdf reg read bar $usr_bar 0x10 | grep "0x10" | cut -d '=' -f2 | cut -d 'x' -f2 | cut -d '.' -f1` - # convert hex to bin - code=`echo $pass | tr 'a-z' 'A-Z'` - val=`echo "obase=2; ibase=16; $code" | bc` - check=1 - if [ $(($val & $check)) -eq 1 ];then - echo "*** Test passed for Queue $qid" - else - echo "#### ERROR Test failed. pattern did not match ####" - dma-ctl qdma$pf_bdf q dump idx $qid >> ./run_pf.log 2>&1 - dma-ctl qdma$pf_bdf reg dump >> ./run_pf.log 2>&1 - fi - cleanup_queue $pf_bdf $qid st h2c - echo "-----------------------------------------------" - done - echo "AXI-ST H2C for Func $pf_bdf End" 2>&1 | tee -a ./run_pf.log - echo "***********************************************" 2>&1 | tee -a ./run_pf.log - done - -} - -function run_st_c2h () { - local pf=0 - - for pf_bdf in "${bdf_array[@]}"; do - - echo "***********************************************" 2>&1 | tee -a ./run_pf.log - echo "AXI-ST C2H for Func $pf_bdf Start" 2>&1 | tee -a ./run_pf.log - - get_user_bar $pf_bdf - - for ((i=$qid_start; i < (($qid_start + $num_qs)); i++)); do - # Setup for Queues - qid=$i - out_st="/tmp/out_st"$pf_bdf"_"$qid - - # Each PF is assigned with 32 Queues. PF0 has queue 0 to 31, PF1 has 32 to 63 - # Write QID in offset 0x00 - hw_qid=$(($qid + ${qbase_array[$pf]} )) - dma-ctl qdma$pf_bdf reg write bar $usr_bar 0x0 $hw_qid >> ./run_pf.log 2>&1 - - # open the Queue for AXI-ST streaming interface. - queue_start $pf_bdf $qid st c2h - - dev_st_c2h="/dev/qdma$pf_bdf-ST-$qid" - let "tsize= $size*$num_pkt" # if more packets are requested. - - # Write transfer size to offset 0x04 - dma-ctl qdma$pf_bdf reg write bar $usr_bar 0x4 $size >> ./run_pf.log 2>&1 - - # Write number of packets to offset 0x20 - dma-ctl qdma$pf_bdf reg write bar $usr_bar 0x20 $num_pkt >> ./run_pf.log 2>&1 - - # Write to offset 0x80 bit [1] to trigger C2H data generator. - dma-ctl qdma$pf_bdf reg write bar $usr_bar 0x08 2 >> ./run_pf.log 2>&1 - - # do C2H transfer - dma-from-device -d $dev_st_c2h -f $out_st -s $tsize >> ./run_pf.log 2>&1 - if [ $? -ne 0 ]; then - echo "#### ERROR Test failed. Transfer failed ####" - cleanup_queue $pf_bdf $qid st c2h - continue - fi - - cmp $out_st $infile -n $tsize - if [ $? -ne 0 ]; then - echo "#### Test ERROR. Queue $2 data did not match ####" - dma-ctl qdma$pf_bdf q dump idx $qid dir c2h >> ./run_pf.log 2>&1 - dma-ctl qdma$pf_bdf reg dump >> ./run_pf.log 2>&1 - else - echo "**** Test pass. Queue $qid" - fi - # Close the Queues - dma-ctl qdma$pf_bdf reg write bar $usr_bar 0x08 0x22 >> ./run_pf.log 2>&1 - var=`dma-ctl qdma$pf_bdf reg read bar $usr_bar 0x18 | sed 's/.*= //' | sed 's/.*x//' | cut -d. -f1` - j=0 - while [ "$j" -lt "2" ] - do - j=$[$j+1] - if [ $var -eq "1" ] - then - break - else - sleep 1 - fi - done - cleanup_queue $pf_bdf $qid st c2h - echo "-----------------------------------------------" - done - pf=$((pf+1)); - echo "AXI-ST C2H for Func $pf_bdf End" 2>&1 | tee -a ./run_pf.log - echo "***********************************************" 2>&1 | tee -a ./run_pf.log - done -} - - -echo "###############################################################" > "run_pf.log" -echo "QDMA Test on All PFs Starts" >> "run_pf.log" -echo "###############################################################" >> "run_pf.log" - -get_dev -if [ $flr_on -ne 0 ]; then - set_flr -fi -run_mm_h2c_c2h -run_st_h2c -run_st_c2h - -exit 0 - - diff --git a/QDMA/linux-kernel/scripts/qdma_run_test_st_vf.sh b/QDMA/linux-kernel/scripts/qdma_run_test_st_vf.sh deleted file mode 100755 index 754a40842..000000000 --- a/QDMA/linux-kernel/scripts/qdma_run_test_st_vf.sh +++ /dev/null @@ -1,229 +0,0 @@ -#/* -# * This file is part of the Xilinx DMA IP Core driver for Linux -# * -# * Copyright (c) 2017-2022, Xilinx, Inc. All rights reserved. -# * Copyright (c) 2022-2023, Advanced Micro Devices, Inc. All rights reserved. -# * -# * This source code is free software; you can redistribute it and/or modify it -# * under the terms and conditions of the GNU General Public License, -# * version 2, as published by the Free Software Foundation. -# * -# * This program is distributed in the hope that it will be useful, but WITHOUT -# * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -# * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for -# * more details. -# * -# * The full GNU General Public License is included in this distribution in -# * the file called "COPYING". -# */ - - -#!/bin/bash -# Simple run script to test QDMA in VF AXI-ST mode. -# -# VF AXI-ST Transfer -# - H2C operation is performed to send data to BRAM on the FPGA. -# - C2H operation is performed to reads data from BRAM. -# - C2H data is stored in a local file 'out_st_$qid', which will be compared to original file for correctness. - - -################################################ -# User Configurable Parameters -################################################ - -iteration=$1 # [Optional] iterations of C2H tests -size=$2 # [Optional] Size per payload packet -num_pkt=$3 # [Optional] number of payload packet - -################################################ -# Hard Coded Parameters -################################################ -usr_bar=2 # For VF, DMA BAR is bar 0. AXI Master Lite(User BAR) is bar 2. -vf=00080 -size_max=4096 -host_adr_high=0 -infile='./datafile_16bit_pattern.bin' -logfile="loopback$1_$2.log" - -################################################ -# Input check -################################################ -if [ -z $iteration ]; then - iteration=1 -fi - -if [ ! -z $size ]; then - f_size=1 -else - f_size=0 -fi - -if [ -z $num_pkt ]; then - num_pkt=1 -fi - -################################################# -# Helper Functions -################################################ -function randomize_tx_params() { - #random host address - if [ $host_adr_high -ne 0 ]; then - hst_adr1=$RANDOM - hst_adr1=$((hst_adr1 % host_adr_high)) - else - hst_adr1=0 - fi - - # byte size - size=$RANDOM - if [ $size -eq 0 ]; then - size=$(($RANDOM % 64 + 1)) ## for random number between 1 and 64 - else - size=$((size % $size_max)) - fi - - # Correct if size is odd - even=$((size%2)) - if [ $even -eq 1 ];then - size=$((size+1)) - fi -} - -function queue_start() { - echo "---- Queue Start $2 ----" - dma-ctl qdma$1 q add idx $2 dir h2c mode $3 - dma-ctl qdma$1 q start idx $2 dir h2c - dma-ctl qdma$1 q add idx $2 dir c2h mode $3 - dma-ctl qdma$1 q start idx $2 dir c2h -} - -function cleanup_queue() { - echo "---- Queue Clean up $2 ----" - dma-ctl qdma$1 q stop idx $2 dir h2c - dma-ctl qdma$1 q del idx $2 dir h2c - dma-ctl qdma$1 q stop idx $2 dir c2h - dma-ctl qdma$1 q del idx $2 dir c2h -} - -# Get a list of available devices -vfs="$(dma-ctl dev list | grep qdmavf | cut -d ' ' -f1)" -echo "############################# AXI-ST Start #################################" - -for vfsdev in $vfs; do - - vf="${vfsdev#*f}" - q_per_vf="$(dma-ctl dev list |grep qdmavf$vf | cut -d ' ' -f 3 | cut -d ',' -f 1 | xargs)" - hw_qbase="$(dma-ctl dev list |grep qdmavf$vf|cut -d',' -f 2 | cut -d '~' -f 1|xargs)" - - for ((i=0; i<$q_per_vf; i++)) do - - # Setup for Queues - qid=$i - hw_qid=$((qid+hw_qbase)) - dev_st_c2h="/dev/qdmavf$vf-ST-$qid" - dev_st_h2c="/dev/qdmavf$vf-ST-$qid" - out="out_st_$qid" - loop=1 - - # Open the Queue for AXI-ST streaming interface. - queue_start vf$vf $qid st > /dev/null - - while [ "$loop" -le $iteration ] - do - # Determine if DMA is targeted @ random host address - if [ $f_size -eq 1 ]; then - hst_adr1=0 - else - randomize_tx_params - fi - - # if more packets are requested. - let "tsize= $size*$num_pkt" - - echo "" - echo "########################################################################################" - echo "############# H2C ST LOOP $loop : dev=$dev_st_h2c qid=$qid hw_qid=$hw_qid" - echo "############# transfer_size=$tsize pkt_size=$size pkt_count=$num_pkt hst_adr=$hst_adr1" - echo "########################################################################################" - - #clear match bit before each H2C ST transfer - dma-ctl qdmavf$vf reg write bar $usr_bar 0x0c 0x01 - - # H2C transfer - dma-to-device -d $dev_st_h2c -f $infile -s $tsize -o $hst_adr1 & - re=$? - - wait - - # Check match bit and QID - hwqid_match=$(dma-ctl qdmavf$vf reg read bar $usr_bar 0x10 | grep "0x10" | cut -d '=' -f2 | cut -d 'x' -f2 | cut -d '.' -f1) - code=`echo $hwqid_match | tr 'a-z' 'A-Z'` - val=`echo "obase=2; ibase=16; $code" | bc` - if [ $(($val & 0x1)) -ne 1 ];then - echo "### ERROR: QID MATCH is $hwqid_match "$hw_qid_hex"1" - re=-1 - fi - - if [ $re == 0 ]; then - echo "######################################################" - echo "############## VF H2C ST PASS QID $qid ################" - echo "######################################################" - else - echo "#### ERROR: VF H2C ST FAIL" - fi - - echo "" - echo "########################################################################################" - echo "############# C2H ST LOOP $loop : dev=$dev_st_c2h qid=$qid hw_qid=$hw_qid" - echo "############# transfer_size=$tsize pkt_size=$size pkt_count=$num_pkt hst_adr=$hst_adr1" - echo "########################################################################################" - - dma-ctl qdmavf$vf reg write bar $usr_bar 0x0 $hw_qid # for Queue 0 - dma-ctl qdmavf$vf reg write bar $usr_bar 0x4 $size - dma-ctl qdmavf$vf reg write bar $usr_bar 0x20 $num_pkt #number of packets - dma-ctl qdmavf$vf reg write bar $usr_bar 0x08 2 # Must set C2H start before starting transfer - - dma-from-device -d $dev_st_c2h -f $out -o $hst_adr1 -s $tsize & - - wait - - #Check if files is there. - if [ ! -f $out ]; then - echo " #### ERROR: Queue $qid output file does not exists ####" - echo " #### ERROR: Queue $qid output file does not exists ####" >> $logfile - cleanup_queue vf$vf $qid st - exit -1 - fi - - # check files size - filesize=$(stat -c%s "$out") - if [ $filesize -gt $tsize ]; then - echo "#### ERROR: Queue $qid output file size does not match, filesize= $filesize ####" - echo "#### ERROR: Queue $qid output file size does not match, filesize= $filesize ####" >> $logfile - cleanup_queue vf$vf $qid st - exit -1 - fi - - #compare file - cmp $out $infile -n $tsize - if [ $? -eq 1 ]; then - echo "#### Test ERROR. Queue $qid data did not match ####" - echo "#### Test ERROR. Queue $qid data did not match ####" >> $logfile - dma-ctl qdmavf$vf q dump idx $qid mode st dir c2h - dma-ctl qdmavf$vf reg dump - cleanup_queue vf$vf $qid st - exit -1 - else - echo "######################################################" - echo "############## VF C2H ST PASS QID $qid ################" - echo "######################################################" - fi - wait - ((loop++)) - done - cleanup_queue vf$vf $qid st > /dev/null - done -done -echo "########################## AXI-ST completed ###################################" -exit 0 - diff --git a/QDMA/linux-kernel/scripts/qdma_vf_auto_tst.sh b/QDMA/linux-kernel/scripts/qdma_vf_auto_tst.sh deleted file mode 100755 index 4d7fed150..000000000 --- a/QDMA/linux-kernel/scripts/qdma_vf_auto_tst.sh +++ /dev/null @@ -1,102 +0,0 @@ -#/* -# * This file is part of the Xilinx DMA IP Core driver for Linux -# * -# * Copyright (c) 2017-2022, Xilinx, Inc. All rights reserved. -# * Copyright (c) 2022-2023, Advanced Micro Devices, Inc. All rights reserved. -# * -# * This source code is free software; you can redistribute it and/or modify it -# * under the terms and conditions of the GNU General Public License, -# * version 2, as published by the Free Software Foundation. -# * -# * This program is distributed in the hope that it will be useful, but WITHOUT -# * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -# * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for -# * more details. -# * -# * The full GNU General Public License is included in this distribution in -# * the file called "COPYING". -# */ - - -#!/bin/bash -# -# Simple script to automate the VF regression testing using gtest framework -# -# This script will insert the module, configure the qmax_vfs, and instantiate -# vfs on each PF one at a time. After instantiating the VFs, it will trigger -# qdma_test regression test suite for VF only. -# -# Inputs: -# MODULE_TOP_DIR= Top directory for qdma linux module -# GTEST_TOP_DIR= Top directory for gtest regression test suite -# MASTER_PF_PCI_BDF= BDF For master PF. - -MODULE_DIR=$1 -GTEST_DIR=$2 -qdma_mod=$MODULE_DIR/build/qdma.ko -qdma_mod_vf=$MODULE_DIR/build/qdma_vf.ko -gtest_bin=$GTEST_DIR/build/src/qdma_test -#busdev="0000:05:00" -master_pf=0000:$3 -busdev=${master_pf%.*} -mod_param_arr=("mode=1" "mode=2" "mode=3") -vfs_cnt=(64 60 60 68) -qmax_vfs=1024 - -RED='\033[0;31m' -NC='\033[0m' - -prep_test_env () { - rmmod qdma - rmmod qdma_vf - sleep 2 - insmod $qdma_mod $1 - insmod $qdma_mod_vf - sleep 2 - if [ ! -f /sys/bus/pci/devices/$master_pf/qdma/qmax_vfs ];then - echo -e "${RED} Aborting, no /sys/bus/pci/devices/$master_pf/qdma/qmax_vfs found.${NC}" - exit -4 - fi - echo $qmax_vfs > /sys/bus/pci/devices/$master_pf/qdma/qmax_vfs - echo $3 > /sys/bus/pci/devices/$busdev.$2/sriov_numvfs - ret=$? - echo - echo "**********************************" - echo "******Doing QDMA VF Tests *******" - echo "**********************************" - echo - echo PF=$2, VF=$3, qmax_vfs=$qmax_vfs - echo module_param=$1 - echo - dma-ctl dev list - - return $ret -} - -if [ $# -lt 3 ];then - echo -e "${RED}Aborting. Invalid usgae. Try $0 . ${NC}" - exit -1 -fi - -if [ ! -f $qdma_mod ] || [ ! -f $qdma_mod_vf ];then - echo -e "${RED}Aborting. Missing qdma drivers at $MODULE_DIR${NC}" - exit -2 -fi - -if [ ! -f $gtest_bin ];then - echo -e "${RED}Aborting. Missing qdma_test at $GTEST_DIR${NC}" - exit -3 -fi - -for fn in `seq 0 3`;do - for params in "${mod_param_arr[@]}";do - prep_test_env "$params" $fn ${vfs_cnt[$fn]} - ret=$? - if [ $ret -ne 0 ];then - echo -e "${RED}FAILED VF tests, Aborting${NC}" - exit -1 - fi - sleep 3 - $gtest_bin --gtest_filter="*VF*" - done -done diff --git a/QDMA/windows/QDMA.sln b/QDMA/windows/QDMA.sln deleted file mode 100644 index 0ad42df70..000000000 --- a/QDMA/windows/QDMA.sln +++ /dev/null @@ -1,69 +0,0 @@ - -Microsoft Visual Studio Solution File, Format Version 12.00 -# Visual Studio 15 -VisualStudioVersion = 15.0.27130.2010 -MinimumVisualStudioVersion = 10.0.40219.1 -Project("{2150E333-8FDC-42A3-9474-1A3956D46DE8}") = "utilities", "utilities", "{94F05E27-A247-49D0-87D9-9EA67085F512}" -EndProject -Project("{2150E333-8FDC-42A3-9474-1A3956D46DE8}") = "drivers", "drivers", "{AE056764-B26E-440F-A803-22D4287DC633}" -EndProject -Project("{2150E333-8FDC-42A3-9474-1A3956D46DE8}") = "docs", "docs", "{63917B3A-5853-4882-BB78-1A4367A87B62}" - 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{B446331B-DD9E-40DD-958A-8D7A1AACA454}.Debug|x64.ActiveCfg = Debug|x64 - {B446331B-DD9E-40DD-958A-8D7A1AACA454}.Debug|x64.Build.0 = Debug|x64 - {B446331B-DD9E-40DD-958A-8D7A1AACA454}.Debug|x64.Deploy.0 = Debug|x64 - {B446331B-DD9E-40DD-958A-8D7A1AACA454}.Release|x64.ActiveCfg = Release|x64 - {B446331B-DD9E-40DD-958A-8D7A1AACA454}.Release|x64.Build.0 = Release|x64 - {B446331B-DD9E-40DD-958A-8D7A1AACA454}.Release|x64.Deploy.0 = Release|x64 - {4898E717-0B00-487F-9F88-C95D61116871}.Debug|x64.ActiveCfg = Debug|x64 - {4898E717-0B00-487F-9F88-C95D61116871}.Debug|x64.Build.0 = Debug|x64 - {4898E717-0B00-487F-9F88-C95D61116871}.Release|x64.ActiveCfg = Release|x64 - {4898E717-0B00-487F-9F88-C95D61116871}.Release|x64.Build.0 = Release|x64 - {F7C376CA-92F6-4484-B737-8670222CE79F}.Debug|x64.ActiveCfg = Debug|x64 - {F7C376CA-92F6-4484-B737-8670222CE79F}.Debug|x64.Build.0 = Debug|x64 - {F7C376CA-92F6-4484-B737-8670222CE79F}.Release|x64.ActiveCfg = Release|x64 - {F7C376CA-92F6-4484-B737-8670222CE79F}.Release|x64.Build.0 = Release|x64 - {620A4D4D-5D14-41BA-909B-011FF03A25FD}.Debug|x64.ActiveCfg = Debug|x64 - {620A4D4D-5D14-41BA-909B-011FF03A25FD}.Debug|x64.Build.0 = Debug|x64 - {620A4D4D-5D14-41BA-909B-011FF03A25FD}.Release|x64.ActiveCfg = Release|x64 - {620A4D4D-5D14-41BA-909B-011FF03A25FD}.Release|x64.Build.0 = Release|x64 - {359143E6-933A-49CC-806C-C5376E1809A4}.Debug|x64.ActiveCfg = Debug|x64 - {359143E6-933A-49CC-806C-C5376E1809A4}.Debug|x64.Build.0 = Debug|x64 - {359143E6-933A-49CC-806C-C5376E1809A4}.Debug|x64.Deploy.0 = Debug|x64 - {359143E6-933A-49CC-806C-C5376E1809A4}.Release|x64.ActiveCfg = Release|x64 - {359143E6-933A-49CC-806C-C5376E1809A4}.Release|x64.Build.0 = Release|x64 - {359143E6-933A-49CC-806C-C5376E1809A4}.Release|x64.Deploy.0 = Release|x64 - EndGlobalSection - GlobalSection(SolutionProperties) = preSolution - HideSolutionNode = FALSE - EndGlobalSection - GlobalSection(NestedProjects) = preSolution - {B446331B-DD9E-40DD-958A-8D7A1AACA454} = {AE056764-B26E-440F-A803-22D4287DC633} - {4898E717-0B00-487F-9F88-C95D61116871} = {94F05E27-A247-49D0-87D9-9EA67085F512} - {F7C376CA-92F6-4484-B737-8670222CE79F} = {94F05E27-A247-49D0-87D9-9EA67085F512} - {620A4D4D-5D14-41BA-909B-011FF03A25FD} = {94F05E27-A247-49D0-87D9-9EA67085F512} - {359143E6-933A-49CC-806C-C5376E1809A4} = {AE056764-B26E-440F-A803-22D4287DC633} - EndGlobalSection - GlobalSection(ExtensibilityGlobals) = postSolution - SolutionGuid = {C455ECA0-8379-4737-AE1C-A9D89747A2E2} - EndGlobalSection -EndGlobal diff --git a/QDMA/windows/README.md b/QDMA/windows/README.md deleted file mode 100644 index 414fde44f..000000000 --- a/QDMA/windows/README.md +++ /dev/null @@ -1,266 +0,0 @@ -# Xilinx QDMA Driver (Windows) - -This project contains the driver and user-space software for the Xilinx PCIe Multi-Queue DMA Subsystem IP. - -_____________________________________________________________________________ -Contents - -1. Directory Structure -2. Dependencies -3. Building from Source - 3.1 From Visual Studio - 3.2 From Command Line -4. Driver Installation -5. Test Utilities - 5.1 dma-arw - 5.2 dma-rw - 5.3 dma-ctl -6. Known Issues -7. References -_____________________________________________________________________________ - - -1. Directory Structure: - - / - |__ build/ - Generated directory containing build output binaries. - |__ apps/ - Contains application source code which demonstrates the usage of QDMA driver. - | |__ dma-arw/ - Asynchrnous Read/Write PCIe BARs of QDMA IP or perform tx/rx DMA transfers. - | |__ dma-rw/ - Synchronous Read/Write PCIe BARs of QDMA IP or perform tx/rx DMA transfers. - | |__ dma-ctl/ - DMA queues control and configuration for DMA transfers. - |__ docs/ - QDMA documentation - |__ sys/ - Contains the QDMA driver source code. - |__ README.md - This file. - |__ QDMA.sln - Visual Studio Solution. - -2. Dependencies - - * Windows 10 target machine - * Windows 10 development machine - * Windows Driver Development Kit 10.0.17134.0 (or later) - * Visual Studio 2017 - -3. Building from Source - - 3.1 From Visual Studio - ---------------------- - - The Windows driver and sample applications can be built using Visual Studio. - 1. Open the *QDMA.sln* solution. - 2. Select the appropriate *Build Configuration* (Debug/Release) from the menu bar. - 2. Click *Build* from the menu bar. - 3. Click *Build Solution*. - - This driver project settings currently support 64bit Windows 10 OS. - In order to target a different Windows OS, go to the driver project *Properties->Driver Settings->General* and change *Target OS Version* to the desired OS. - - Also *Release* and *Debug* build configurations exist and are configurable via the *Configuration Manager*. - - The compiled build products can then be found in the *build/x64/`CONFIG`/* folder. This folder contains three folders: - - *bin/* contains sample and test applications - - *libqdma/* contains libqdma static library - - *sys/* contains the driver - - 3.2 From Command Line - --------------------- - - 1. Open *Developer Command Prompt for VS2017* - 2. Change directory to the project root directory - 3. Run the following command: - - msbuild /t:clean /t:build QDMA.sln - - 4. The build should run and display the following - - Build succeeded. - 0 Warning(s) - 0 Error(s) - - Time Elapsed 00:01:05.55 - - For more information on building Windows drivers visit the [MSDN website][ref4]. - -4. Driver Installation - - The easiest way to install the driver is via Windows' *Device Manager* - (_Control Panel->System->Device Manager_). - - _**Note**: The driver does not provide a certified signature and uses a test signature instead. - Please be aware that, depending on your target operating system, you may need to enable test-signed drivers in your windows boot configuration - in order to enable installation of this driver. See [MSDN website][ref5] for further information._ - - 1. Open the *Device Manager* - 2. Initially the device will be displayed as a *PCI Serial Port* or *PCI Memory Controller*. - 3. Right-Click on the device and select *Update Driver Software* and - select the folder of the built QDMA driver (typically *build/x64/`CONFIG`/sys/QDMA/* (where `CONFIG` is *Debug* or *Release*). - 4. If prompted about unverified driver publisher, select *Install this driver software anyway*. - 5. *Xilinx Drivers -> Xilinx PCIe Multi-Queue DMA* should now be visible in the *Device Manager* - -5. Test Utilities - - The Xilinx dma-arw and dma-rw are test utilities can perform the following functions - - AXI-MM - - H2C/C2H AXI-MM transfer. - - AXI-ST-H2C - - Enables the user to perform AXI-ST H2C transfers and checks data for correctness. - - AXI-ST-C2H - - Enables the user to perform AXI-ST C2H transfers and checks data for correctness. - - register access - - read a register space - - write to a register space - 5.1 dma-arw - ----------- - e.g. - 1. Get the dma-arw help - > dma-arw -h - dma-arw usage: - dma-arw -v : prints the version information - - dma-arw qdma mode <0 | 1> [OPTIONS] [DATA] - - - qdma : unique qdma device name ( is BBDDF where BB -> PCI Bus No, DD -> PCI Dev No, F -> PCI Fun No) - - mode : 0 : this mode uses ReadFile and WriteFile async implementation - : 1 : this mode uses ReadFileEx and WriteFileEx async implementation - - DEVNODE : One of: queue_mm_ | queue_st_* - where the * is a numeric wildcard (0 - 511for queue). - - ADDR : The target offset address of the read/write operation. - Applicable only for control, user, queue_mm device nodes. - Can be in hex or decimal. - - OPTIONS : - -a set alignment requirement for host-side buffer (default: PAGE_SIZE) - -b open file as binary - -f use contents of file as input or write output into file. - -l length of data to read/write (default: 4 bytes or whole file if '-f' flag is used) - - DATA : Space separated bytes (big endian) in decimal or hex, - e.g.: 17 34 51 68 - or: 0x11 0x22 0x33 0x44 - 2. Read/Write four bytes from AXI-MM at zeroth offset on queue zero of PF 0 - > dma-arw qdma17000 mode 0 queue_mm_0 read 0 -l 4 - > dma-arw qdma17000 mode 0 queue_mm_0 write 0 0xA 0xB 0XC 0xD - > dma-arw qdma17000 mode 1 queue_mm_0 read 0 -l 4 - > dma-arw qdma17000 mode 1 queue_mm_0 write 0 0xA 0xB 0XC 0xD - - 3. Read four bytes from AXI-ST-H2C on queue zero - > dma-arw qdma17000 mode 0 queue_st_0 read -l 4 - > dma-arw qdma17000 mode 1 queue_st_0 read -l 4 - - 4. Write four bytes to AXI-ST-C2H on queue zero - > dma-arw qdma17000 mode 0 queue_st_0 write -l 4 - > dma-arw qdma17000 mode 1 queue_st_0 write -l 4 - - 5. Read/Write four bytes from control register space at zeroth offset - > dma-arw qdma17000 mode 0 control read 0 -l 4 - > dma-arw qdma17000 mode 0 control write 0 0xA 0xB 0XC 0xD - > dma-arw qdma17000 mode 1 control read 0 -l 4 - > dma-arw qdma17000 mode 1 control write 0 0xA 0xB 0XC 0xD - - 5.2 dma-rw - ----------- - e.g. - 1. Get the dma-rw help - > dma-rw -h - dma-rw usage: - dma-rw -v : prints the version information - - dma-rw qdma [OPTIONS] [DATA] - - - qdma : unique qdma device name ( is BBDDF where BB -> PCI Bus No, DD -> PCI Dev No, F -> PCI Fun No) - - DEVNODE : One of: control | user | queue_mm_ | queue_st_* - where the * is a numeric wildcard (0 - 511for queue). - - ADDR : The target offset address of the read/write operation. - Applicable only for control, user, queue_mm device nodes. - Can be in hex or decimal. - - OPTIONS : - -a set alignment requirement for host-side buffer (default: PAGE_SIZE) - -b open file as binary - -f use contents of file as input or write output into file. - -l length of data to read/write (default: 4 bytes or whole file if '-f' flag is used) - - DATA : Space separated bytes (big endian) in decimal or hex, - e.g.: 17 34 51 68 - or: 0x11 0x22 0x33 0x44 - 2. Read/Write four bytes from AXI-MM at zeroth offset on queue zero of PF 0 - > dma-rw qdma17000 queue_mm_0 read 0 -l 4 - > dma-rw qdma17000 queue_mm_0 write 0 0xA 0xB 0XC 0xD - - 3. Read four bytes from AXI-ST-H2C on queue zero - > dma-rw qdma17000 queue_st_0 read -l 4 - - 4. Write four bytes to AXI-ST-C2H on queue zero - > dma-rw qdma17000 queue_st_0 write -l 4 - - 5. Read/Write four bytes from control register space at zeroth offset - > dma-rw qdma17000 control read 0 -l 4 - > dma-rw qdma17000 control write 0 0xA 0xB 0XC 0xD - - 5.3 dma-ctl - ------------ - The Xilinx dma-ctl is a helper utility can perform the following functions for a given PF - - Add/Start/Stop/Delete/State queues - - can add and start a queue - - can stop and delete a queue - - can retrieve and show the state of a queue - - Dump the CSR registers Information - - List all the CSR registers and its values - - Provide the HW and SW capabilities Information - - e.g.: - 1. Get the dma-ctl help - > dma-ctl -h - usage: dma-ctl [dev | qdma] [operation] - dma-ctl -h - Prints this help - dma-ctl -v - Prints the version information - - dev [operation] : system wide FPGA operations - list : list all qdma functions - - qdma [operation] : per QDMA FPGA operations - : N is BBDDF where BB -> PCI Bus No, DD -> PCI Dev No, F -> PCI Fun No - csr - dump : Dump QDMA CSR Information - - devinfo : lists the Hardware and Software version and capabilities - - queue - add mode qid [en_mm_cmpl] idx_h2c_ringsz <0:15> idx_c2h_ringsz <0:15> - [idx_c2h_timer <0:15>] [idx_c2h_th <0:15>] [idx_c2h_bufsz <0:15>] [cmptsz <0|1|2|3>] - add a queue - [trigmode ] [sw_desc_sz <3>] [desc_bypass_en] [pfch_en] [pfch_bypass_en] - [cmpl_ovf_dis] - start qid - start a single queue - stop qid - stop a single queue - delete qid - delete a queue - state qid - print the state of the queue - dump qid dir desc - dump desc ring entries to - dump qid cmpt - dump completion ring entries to - dump qid ctx dir - dump context information of - cmpt_read qid - Read the completion data - intring dump vector - interrupt ring dump for vector number - for intrrupt entries : --- - reg dump - register dump - - 2. Get the qdma devices list - > dma-ctl dev list - qdma17000 0000:17:00:0 maxQP: 512, 0~511 - qdma17001 0000:17:00:1 maxQP: 512, 512~1023 - qdma17002 0000:17:00:2 maxQP: 512, 1024~1535 - qdma17003 0000:17:00:3 maxQP: 512, 1536~2047 - - -6. Known Issues - - * Driver installation gives warning due to test signature. - * Driver is not fully tuned to achieve maximum IP performance - -7. References - - [ref1]: https://www.xilinx.com/products/intellectual-property/pcie-dma.html - [ref2]: https://www.xilinx.com/support/documentation/ip_documentation/qdma/v3_0/pg302-qdma.pdf - [ref3]: https://developer.microsoft.com/en-us/windows/hardware/windows-driver-kit - [ref4]: https://msdn.microsoft.com/en-us/windows/hardware/drivers/develop/building-a-driver - [ref5]: https://msdn.microsoft.com/en-us/windows/hardware/drivers/install/the-testsigning-boot-configuration-option \ No newline at end of file diff --git a/QDMA/windows/RELEASE b/QDMA/windows/RELEASE deleted file mode 100644 index 936e10d19..000000000 --- a/QDMA/windows/RELEASE +++ /dev/null @@ -1,76 +0,0 @@ -Release: 2020.2 -================ - -This release is validated on QDMA4.0 2020.2 based example design and -QDMA3.1 2019.2 patch based example design. - -QDMA Windows driver is supported in poll mode by default - -SUPPORTED FEATURES: -=================== -2019.1 Features ---------------- -- Support for AXI4 Memory Mapped(MM) and AXI4 Streaming(ST) Interfaces -- Supports only Physical Functions(PFs) -- 2048 queues Sets (512 queues for each PF) - - 2048 H2C(host-to-card) Descriptor rings - - 2048 C2H (card-to-host) Descriptor rings - - 2048 Completion rings -- Interrupts - - Up to 8 MSI-X vectors per Function - - Interrupt Aggregation with single ring per PF -- Driver can be loaded in - - Poll mode - - direct interrupt mode - - interrupt aggregation mode -- Queues are managed by synchronous/Asynchronous IO from single application. -- Driver configuration through qdma.inf file -- Zero Packet size Write/Read support for ST mode -- Descriptor bypass(8,16,32 descriptor sizes) support -- Descriptor Prefetch - -2019.2 Features ---------------- -- Support disabling overflow check in completion ring -- Support 64B descriptor format in bypass mode -- Support for Completion queue descriptors of 64 bytes size -- Legacy Interrupt Support -- Support HW Error reporting -- Support Completions in Streaming mode -- Support flexible BAR mapping for QDMA configuration register space -- Version for SW and HW -- ST H2C to C2H loopback support -- Enhancements to user application utilities - -2020.1 Updates ---------------- -- QDMA driver and libqdma as a separate project -- Configurable queue distribution between physical functions -- User application utility names changed as dma-ctl, dma-arw, dma-rw -- New set of commands added to dma-ctl application -- Support QDMA4.0 context and register changes -- Common driver to support QDMA3.1 and QDMA4.0 designs -- Updated and validated the example design with marker changes for QDMA4.0 and without marker changes for QDMA3.1 -- Support multiple bus numbers on single card - -2020.2 Updates --------------- -- Support larger MM & ST packet transfer support -- Added support for detailed register dump -- Added support for post processing HW error messages -- Added support for Debug mode and Internal only mode - - -KNOWN ISSUES: -============= -- Driver installation gives warning due to test signature. -- In interrupt mode, Sometimes completions are not received when C2H PIDX updates are held for 64 descriptors -- On QDMA4.0 2020.2 design, User logic fails to generate C2H streaming packets when multiple threads try - to generate packets on multiple active queues. - -DRIVER LIMITATIONS: -=================== -- SRIOV is not supported -- Big endian systems are not supported -- Driver is not fully tuned to achieve maximum IP performance -- For optimal QDMA streaming performance, packet buffers of the descriptor ring should be aligned to at least 256 bytes. diff --git a/QDMA/windows/apps/common/include/device_file.hpp b/QDMA/windows/apps/common/include/device_file.hpp deleted file mode 100644 index a1394bb95..000000000 --- a/QDMA/windows/apps/common/include/device_file.hpp +++ /dev/null @@ -1,293 +0,0 @@ -/* - * Copyright (C) 2020 Xilinx, Inc - * - * Licensed under the Apache License, Version 2.0 (the "License"). You may - * not use this file except in compliance with the License. You may obtain - * a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - */ - -#pragma once - -#include -#include -#include -#include - -#include -#include -#include -#include - -#define DEV_NAME_MAX_SZ 12 - -struct device_details { - UINT8 bus_no; - UINT8 dev_no; - UINT8 fun_no; - std::string device_name; - std::string device_path; -}; - -#pragma warning( disable : 4505) -static bool get_device(std::vector dev_details, const char *dev_name, device_details &dev_info) { - bool is_dev_found = false; - - for (auto i = 0; i < (int)dev_details.size(); i++) { - if (dev_details[i].device_name == dev_name) { - is_dev_found = true; - dev_info = dev_details[i]; - break; - } - } - return is_dev_found; -} - -static std::vector get_device_details(GUID guid) { - auto device_info = SetupDiGetClassDevs((LPGUID)&guid, NULL, NULL, DIGCF_PRESENT | DIGCF_DEVICEINTERFACE); - if (device_info == INVALID_HANDLE_VALUE) { - throw std::runtime_error("GetDevices INVALID_HANDLE_VALUE"); - } - - SP_DEVINFO_DATA dev_info_data; - dev_info_data.cbSize = sizeof(SP_DEVINFO_DATA); - - SP_DEVICE_INTERFACE_DATA device_interface = { 0 }; - device_interface.cbSize = sizeof(SP_DEVICE_INTERFACE_DATA); - - - std::vector dev_details; - device_details info; - - /* enumerate through devices */ - for (unsigned index = 0; - SetupDiEnumDeviceInterfaces(device_info, NULL, &guid, index, &device_interface); - ++index) { - - unsigned char *bus_no = NULL; - unsigned char *dev_addr = NULL; - DWORD lsize = 0; - - /* get required buffer size */ - unsigned long detailLength = 0; - if (!SetupDiGetDeviceInterfaceDetail(device_info, &device_interface, NULL, 0, &detailLength, NULL) && GetLastError() != ERROR_INSUFFICIENT_BUFFER) { - throw std::runtime_error("SetupDiGetDeviceInterfaceDetail - get length failed"); - } - - /* allocate space for device interface detail */ - auto dev_detail = reinterpret_cast(new char[detailLength]); - dev_detail->cbSize = sizeof(SP_DEVICE_INTERFACE_DETAIL_DATA); - - /* get device interface detail */ - if (!SetupDiGetDeviceInterfaceDetail(device_info, &device_interface, dev_detail, detailLength, NULL, &dev_info_data)) { - delete[] dev_detail; - throw std::runtime_error("SetupDiGetDeviceInterfaceDetail - get detail failed"); - } - - /* get the required size for PCIe BUS NUMBER Parameter */ - if (!SetupDiGetDeviceRegistryProperty(device_info, &dev_info_data, SPDRP_BUSNUMBER, NULL, (PBYTE)bus_no, 0, &lsize) && GetLastError() != ERROR_INSUFFICIENT_BUFFER) { - delete[] dev_detail; - throw std::runtime_error("SetupDiGetDeviceRegistryProperty - get length failed"); - } - - /* Retrieve the PCIe bus number */ - bus_no = (unsigned char*)malloc(lsize); - if (!SetupDiGetDeviceRegistryProperty(device_info, &dev_info_data, SPDRP_BUSNUMBER, NULL, (PBYTE)bus_no, lsize, NULL)) { - delete[] dev_detail; - free(bus_no); - throw std::runtime_error("SetupDiGetDeviceRegistryProperty - get Registry failed"); - } - - /* get the required size for PCIe Device Address Parameter */ - if (!SetupDiGetDeviceRegistryProperty(device_info, &dev_info_data, SPDRP_ADDRESS, NULL, (PBYTE)dev_addr, 0, &lsize) && GetLastError() != ERROR_INSUFFICIENT_BUFFER) { - delete[] dev_detail; - free(bus_no); - throw std::runtime_error("SetupDiGetDeviceRegistryProperty - get length failed"); - } - - /* Retrieve the PCIe Device Address */ - dev_addr = (unsigned char*)malloc(lsize); - if (!SetupDiGetDeviceRegistryProperty(device_info, &dev_info_data, SPDRP_ADDRESS, NULL, (PBYTE)dev_addr, lsize, NULL)) { - delete[] dev_detail; - free(bus_no); - free(dev_addr); - throw std::runtime_error("SetupDiGetDeviceRegistryProperty - get Registry failed"); - } - - /* Prepare BDF format (0xBBDDF) */ - UINT8 dev_no = (*dev_addr & 0xF8) >> 3; - UINT8 fun_no = (*dev_addr & 0x7); - UINT32 bdf = 0x0; - bdf = bdf | (*bus_no << 12); - bdf = bdf | (dev_no << 4); - bdf = bdf | (fun_no); - - /* Prepare the PCIe devices identifier strings */ - std::ostringstream outs; - outs << "qdma"; - outs.setf (std::ios::hex, std::ios::basefield); - outs.width(5); outs.fill('0'); - outs << bdf; - - /* Fill the details in info structure */ - info.bus_no = *bus_no; - info.dev_no = dev_no; - info.fun_no = fun_no; - info.device_name = outs.str(); - info.device_path = dev_detail->DevicePath; - - /* Append it to the return vector */ - dev_details.emplace_back(info); - - free(bus_no); - free(dev_addr); - delete[] dev_detail; - } - - SetupDiDestroyDeviceInfoList(device_info); - - return dev_details; -} - - -inline static std::string get_last_win_err_msg() { - char tmp[256]; - FormatMessageA(FORMAT_MESSAGE_FROM_SYSTEM, NULL, GetLastError(), - MAKELANGID(LANG_NEUTRAL, SUBLANG_DEFAULT), tmp, 256, NULL); - - return{ tmp, 256 }; -} - -struct device_file { - HANDLE h; - device_file(); - device_file(const std::string& path, DWORD accessFlags); - ~device_file(); - - device_file(const device_file& rhs) = delete; - device_file& operator=(const device_file& rhs) = delete; - - device_file(device_file && rhs); - - device_file& operator=(device_file&& rhs); - - void open(const std::string& path, DWORD accessFlags, DWORD fattribs = FILE_ATTRIBUTE_NORMAL); - - void close(); - - template - void write(long address, const T value); - - template - T read(long address); - - void seek(long device_offset); - size_t write(void* buffer, size_t size); - size_t read(void* buffer, size_t size); - - size_t ioctl(int code, void* inData = nullptr, DWORD inSize = 0, void* outData = nullptr, - DWORD outSize = 0); -}; - -inline device_file::device_file() : h(INVALID_HANDLE_VALUE) {}; - -inline void device_file::open(const std::string& path, DWORD accessFlags, DWORD fattribs) { - h = CreateFile(path.c_str(), accessFlags, 0, NULL, OPEN_EXISTING, - fattribs, NULL); - if (h == INVALID_HANDLE_VALUE) { - throw std::runtime_error("CreateFile control failed: " + get_last_win_err_msg()); - } -} - -inline void device_file::close() { - if (h != INVALID_HANDLE_VALUE) { - CloseHandle(h); - } -} - -inline device_file::device_file(const std::string& path, DWORD accessFlags) : h(INVALID_HANDLE_VALUE) { - open(path, accessFlags); -} - -inline device_file::~device_file() { - close(); -} - -#if 0 -inline device_file::device_file(device_file && rhs) - : h(INVALID_HANDLE_VALUE) { - *this = std::move(rhs); -} - -inline device_file& device_file::operator=(device_file&& rhs) { - if (this != &rhs) { - h = rhs.h; - rhs.h = INVALID_HANDLE_VALUE; - } - return *this; -}; -#endif - -inline void device_file::seek(long device_offset) { - if (INVALID_SET_FILE_POINTER == SetFilePointer(h, device_offset, NULL, FILE_BEGIN)) { - throw std::runtime_error("SetFilePointer failed: " + get_last_win_err_msg()); - } -} - -inline size_t device_file::write(void* buffer, size_t size) { - unsigned long num_bytes_written; - if (!WriteFile(h, buffer, (DWORD)size, &num_bytes_written, NULL)) { - throw std::runtime_error("Failed to write to device! " + get_last_win_err_msg()); - } - - return num_bytes_written; -} - -template -inline void device_file::write(long addr, T t) { - seek(addr); - unsigned long num_bytes_written; - if (!WriteFile(h, &t, sizeof(T), &num_bytes_written, NULL)) { - throw std::runtime_error("Failed to write to device! " + get_last_win_err_msg()); - } else if (num_bytes_written != sizeof(T)) { - throw std::runtime_error("Failed to write all bytes!"); - } -} - -inline size_t device_file::read(void* buffer, size_t size) { - unsigned long num_bytes_read; - if (!ReadFile(h, buffer, (DWORD)size, &num_bytes_read, NULL)) { - throw std::runtime_error("Failed to read from device! " + get_last_win_err_msg()); - } - return num_bytes_read; -} - -template -inline T device_file::read(long addr) { - seek(addr); - T buffer; - unsigned long num_bytes_read; - if (!ReadFile(h, &buffer, sizeof(T), &num_bytes_read, NULL)) { - throw std::runtime_error("Failed to read from device! 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bytes_transfered; - if (qdev->xfer_size >= bytes_transfered) { - qdev->xfer_done = true; - ReleaseSemaphore(qdev->sem_xfer_done, 1, NULL); - } - - return; -} - -BOOL WINAPI xfer_completion(PVOID arg) -{ - UNREFERENCED_PARAMETER(arg); - bool ret; - constexpr unsigned int wait_size = 50; - LPOVERLAPPED_ENTRY wait_ov_entry = (LPOVERLAPPED_ENTRY)malloc(wait_size * sizeof(OVERLAPPED)); - ULONG no_entries_cmpltd = 0; - ULONG wait_time = COMPL_WAIT_TIME; /* In msec */ - ULONG total_bytes_xfered = 0; - qdma_device *qdev = (qdma_device *)arg; - - - try { - qdev->thread_run = true; - while (true) { - ret = GetQueuedCompletionStatusEx( - qdev->cmplt_io_handle, &wait_ov_entry[0], - wait_size, &no_entries_cmpltd, - wait_time, FALSE); - - if (ret == true) { - qdev->rxd_size = 0; - for (ULONG index = 0; index < no_entries_cmpltd; index++) { - total_bytes_xfered += wait_ov_entry[index].dwNumberOfBytesTransferred; - qdev->rxd_size += wait_ov_entry[index].dwNumberOfBytesTransferred; - } - if (total_bytes_xfered >= qdev->xfer_size) { - qdev->xfer_done = true; - ReleaseSemaphore(qdev->sem_xfer_done, 1, NULL); - } - } - if (qdev->thread_exit == true) - break; - } - free(wait_ov_entry); - } - catch (const std::exception& e) { - free(wait_ov_entry); - std::cout << "Error: " << e.what() << '\n'; - } - - return true; -} - -void qdma_device::async_env_init(void) -{ - sem_xfer_done = CreateSemaphore(NULL, 0, 1, NULL); - if (sem_xfer_done == NULL) { - throw std::runtime_error("CreateSemaphore error: " + get_last_win_err_msg()); - } - - if (cmd.mode == FILE_NORMAL_MODE) { - cmplt_io_handle = CreateIoCompletionPort(queue_.h, NULL, 1, 0); - if (NULL == cmplt_io_handle) { - throw std::runtime_error("FAILED TO CREATE COMPLETION HANDLE : " + get_last_win_err_msg()); - } - - thread_run = false; - thread_exit = false; - xfer_done = false; - - cmplt_th_handle = - CreateThread(NULL, - 10 * 1024 * 1024, // stack size - (LPTHREAD_START_ROUTINE)xfer_completion, - (void *)this, - 0, - NULL); - - if (NULL == cmplt_th_handle) { - CloseHandle(sem_xfer_done); - throw std::runtime_error("Error CreateThread Failed : " + get_last_win_err_msg()); - } - - while (thread_run == false); - } -} - -void qdma_device::async_env_exit(void) -{ - if (cmd.mode == FILE_NORMAL_MODE) { - thread_exit = true; - Sleep(2 * COMPL_WAIT_TIME); - WaitForSingleObject(cmplt_th_handle, INFINITE); - CloseHandle(cmplt_th_handle); - } - CloseHandle(sem_xfer_done); -} - -void qdma_device::poll_completion(void) -{ - int timeout = 0; - - while (WAIT_OBJECT_0 != WaitForSingleObject(sem_xfer_done, 1)) { - timeout++; - SleepEx(9, TRUE); - if (timeout > MAX_TIMEOUT_PERIOD) - break; - } - - if (cmd.mode == FILE_NORMAL_MODE) { - thread_exit = true; - Sleep(2 * COMPL_WAIT_TIME); - } -} - -int qdma_device::qdma_read(void) -{ - bool ret; - OVERLAPPED overlapped; - - cmd.data = allocate_buffer(cmd.size, cmd.alignment); - if (!cmd.data) { - throw std::runtime_error("Error allocating memory" + get_last_win_err_msg()); - } - - switch (cmd.node) { - case devnode_sel::queue_mm: - qopen(cmd.qid, true); - xfer_size = cmd.size; - memset(&overlapped, 0, sizeof(overlapped)); - overlapped.OffsetHigh = 0x0; - overlapped.Offset = (DWORD)cmd.addr; - - if (cmd.mode == FILE_NORMAL_MODE) { - ret = ReadFile(queue_.h, cmd.data, xfer_size, NULL, &overlapped); - } - else { - overlapped.hEvent = this; - ret = ReadFileEx(queue_.h, cmd.data, xfer_size, &overlapped, CompletionRoutine); - } - - if (ret == false) { - auto error = GetLastError(); - if (error != ERROR_IO_PENDING) - throw std::runtime_error("Failed to read from device! " + get_last_win_err_msg()); - } - - /* no-op...just waiting for async completion */ - poll_completion(); - - if (xfer_done) { - printf("Asynchronous Read completed : \n"); - printf("------------------------------\n"); - if (TRUE == cmd.binary) - print_bytes_binary(cmd.data, cmd.size); - else - print_bytes(cmd.addr, cmd.data, cmd.size); - } - else { - printf("Failed to Read : Async Timeout Occurred\n"); - } - qclose(); - break; - - case devnode_sel::queue_st: - { - DWORD packet_size; - DWORD packet_cnt; - DWORD remain_size = cmd.size; - DWORD buf_idx = 0; - bool pkt_generate = true; - bool last_pkt_generate = true; - - qopen(cmd.qid, false); - - do { - if (remain_size >= ST_C2H_MAX_PACK_SIZE_CHUNK) { - packet_cnt = remain_size / ST_C2H_MAX_PACK_SIZE_CHUNK; - packet_size = ST_C2H_MAX_PACK_SIZE_CHUNK; - } - else { - if (last_pkt_generate) { - pkt_generate = true; - last_pkt_generate = false; - } - packet_cnt = 1; - packet_size = remain_size; - } - - if (cmd.size == 0x0) { - cout << "Initiating Zero Byte Read\n"; - } - - if (pkt_generate) { - dgen.reset_pkt_ctrl(); - dgen.configure_c2h(cmd.qid + qbase, packet_size, packet_cnt); - dgen.generate_packets(); - pkt_generate = false; - } - - xfer_size = packet_size * packet_cnt; - xfer_done = false; - - memset(&overlapped, 0, sizeof(overlapped)); - overlapped.OffsetHigh = 0x0; - overlapped.Offset = (DWORD)cmd.addr; - - //printf("buf_idx : %d, len : %d\n", buf_idx, xfer_size); - - if (cmd.mode == FILE_NORMAL_MODE) { - ret = ReadFile(queue_.h, &cmd.data[buf_idx], xfer_size, NULL, &overlapped); - } - else { - overlapped.hEvent = this; - ret = ReadFileEx(queue_.h, &cmd.data[buf_idx], xfer_size, &overlapped, CompletionRoutine); - } - - if (ret == false) { - auto error = GetLastError(); - if (error != ERROR_IO_PENDING) - throw std::runtime_error("Failed to read from device! " + get_last_win_err_msg()); - } - - poll_completion(); - if (!xfer_done) - break; - buf_idx = buf_idx + rxd_size; - remain_size = remain_size - rxd_size; - - if (cmd.size == 0x0) { - cout << "ZERO Byte Read Successful\n"; - } - } while (remain_size); - - if (xfer_done) { - printf("Asynchronous Read completed : \n"); - printf("------------------------------\n"); - if (TRUE == cmd.binary) - print_bytes_binary(cmd.data, cmd.size); - else - print_bytes(cmd.addr, cmd.data, cmd.size); - } - else { - printf("Failed to Read : Async Timeout Occurred\n"); - } - qclose(); - } - - break; - - default: - return 1; - } - - if (cmd.data) _aligned_free(cmd.data); - return 0; -} - -int qdma_device::qdma_write(void ) -{ - bool ret; - OVERLAPPED overlapped; - - switch (cmd.node) { - case devnode_sel::queue_mm: - qopen(cmd.qid, true); - - if (cmd.data == nullptr && false == cmd.file.empty()) { - read_file_option(); - } - - xfer_size = cmd.size; - memset(&overlapped, 0, sizeof(overlapped)); - overlapped.OffsetHigh = 0x0; - overlapped.Offset = (DWORD)cmd.addr; - - if (cmd.mode == FILE_NORMAL_MODE) { - ret = WriteFile(queue_.h, cmd.data, xfer_size, NULL, &overlapped); - } - else { - overlapped.hEvent = this; - ret = WriteFileEx(queue_.h, cmd.data, xfer_size, &overlapped, CompletionRoutine); - } - - if (ret == false) { - auto error = GetLastError(); - if (error != ERROR_IO_PENDING) - throw std::runtime_error("Failed to write to device! " + get_last_win_err_msg()); - } - - poll_completion(); - - if (!xfer_done) { - printf("Failed to Write : Async Timeout Occurred\n"); - } - else { - printf("Asynchronous Write completed : \n"); - printf("------------------------------\n"); - } - - qclose(); - - break; - - case devnode_sel::queue_st: - { - qopen(cmd.qid, false); - aligned_vector wr_buffer(cmd.size); - iota(wr_buffer.begin(), wr_buffer.end(), static_cast(0)); /* 0, 1, 2, 3, 4 ... */ - dgen.reset_h2c(); - - if (cmd.size == 0x0) - cout <<"Initiating Zero Byte Write\n"; - - xfer_size = cmd.size; - memset(&overlapped, 0, sizeof(overlapped)); - overlapped.OffsetHigh = 0x0; - overlapped.Offset = (DWORD)cmd.addr; - - if (cmd.mode == FILE_NORMAL_MODE) { - ret = WriteFile(queue_.h, wr_buffer.data(), xfer_size, NULL, &overlapped); - } - else { - overlapped.hEvent = this; - ret = WriteFileEx(queue_.h, wr_buffer.data(), xfer_size, &overlapped, CompletionRoutine); - } - - if (ret == false) { - auto error = GetLastError(); - if (error != ERROR_IO_PENDING) - throw std::runtime_error("Failed to write to device! " + get_last_win_err_msg()); - } - - poll_completion(); - - if (xfer_done) { - printf("Asynchronous Write completed : \n"); - printf("------------------------------\n"); - if (true == dgen.check_h2c(cmd.qid + qbase)) - cout << "Data generator returned SUCCESS for received data" << endl; - else - throw std::runtime_error("Data generator reported error for received data!"); - - if (cmd.size == 0x0) - cout << "ZERO Byte Write Successful\n"; - } - else { - printf("Failed to Write : Async Timeout Occurred\n"); - } - - qclose(); - break; - } - default: - return 1; - } - - if (cmd.data) _aligned_free(cmd.data); - return 0; -} - -static int is_printable(char c) -{ - /* anything below ASCII code 32 is non-printing, 127 is DELETE */ - if (c < 32 || c == 127) { - return FALSE; - } - return TRUE; -} - -static void print_bytes_binary(BYTE* data, size_t length) -{ - FILE* output = stdout; - - if (false == cmd.file.empty()) { - fopen_s(&output, cmd.file.data(), "wb"); - } - - fwrite(data, sizeof(BYTE), length, output); - - if (false == cmd.file.empty()) { - fclose(output); - } -} - -static void print_bytes(size_t addr, BYTE* data, size_t length) -{ - FILE* output = stdout; - - if (false == cmd.file.empty()) { - fopen_s(&output, cmd.file.data(), "wb"); - } - - /* formatted output */ - for (int row = 0; row < (int)(length / 16 + ((length % 16) ? 1 : 0)); - row++) { - - /* Print address */ - fprintf(output, "0x%04zX: ", addr + row * 16); - - /* Print bytes */ - int column; - for (column = 0; column < (int)min(16, length - (row * 16)); - column++) { - fprintf(output, "%02x ", data[(row * 16) + column]); - } - for (; column < 16; column++) { - fprintf(output, " "); - } - - /* Print gutter */ - fprintf(output, " "); - - /* Print characters */ - for (column = 0; column < (int)min(16, length - (row * 16)); - column++) { - fprintf(output, "%c", is_printable(data[(row * 16) + column]) ? - (data[(row * 16) + column]) : '.'); - } - for (; column < 16; column++) { - fprintf(output, " "); - } - fprintf(output, "\n"); - } - - if (false == cmd.file.empty()) { - fclose(output); - } -} - -static int read_file_option(void) -{ - FILE* inputFile; - if (fopen_s(&inputFile, cmd.file.data(), "rb") != 0) { - fprintf(stderr, "Could not open file <%s>\n", cmd.file.data()); - return 1; - } - - /* determine file size */ - if (cmd.size == 0) { - fseek(inputFile, 0, SEEK_END); - fpos_t fpos; - fgetpos(inputFile, &fpos); - fseek(inputFile, 0, SEEK_SET); - cmd.size = (DWORD)fpos; - } - - cmd.data = allocate_buffer(cmd.size, cmd.alignment); - if (!cmd.data) { - fprintf(stderr, "Error allocating %ld bytes of memory, error code: %ld\n", cmd.size, GetLastError()); - return 1; - } - cmd.size = (DWORD)fread(cmd.data, 1, cmd.size, inputFile); - - fclose(inputFile); - return 0; -} - -static void help(void) -{ - cout << "dma-arw usage:\n"; - cout << "dma-arw -v : prints the version information\n\n"; - cout << "dma-arw qdma mode <0 | 1> [OPTIONS] [DATA]\n\n"; - cout << "- qdma : unique qdma device name ( is BBDDF where BB -> PCI Bus No, DD -> PCI Dev No, F -> PCI Fun No)\n"; - cout << "- mode : 0 : this mode uses ReadFile and WriteFile async implementation\n"; - cout << " : 1 : this mode uses ReadFileEx and WriteFileEx async implementation\n"; - cout << "- DEVNODE : One of: queue_mm_ | queue_st_*\n"; - cout << " where the * is a numeric wildcard (0 - N) for queue.\n"; - cout << "- ADDR : The target offset address of the read/write operation.\n"; - cout << " Applicable only for control, user, queue_mm device nodes.\n"; - cout << " Can be in hex or decimal.\n"; - cout << "- OPTIONS : \n"; - cout << " -a set alignment requirement for host-side buffer (default: PAGE_SIZE)\n"; - cout << " -b open file as binary\n"; - cout << " -f use contents of file as input or write output into file.\n"; - cout << " -l length of data to read/write (default: 4 bytes or whole file if '-f' flag is used)\n"; - cout << "- DATA : Space separated bytes (big endian) in decimal or hex, \n"; - cout << " e.g.: 17 34 51 68\n"; - cout << " or: 0x11 0x22 0x33 0x44\n"; -} - -static void init_cmd(void) -{ - cmd.addr = 0x0; - cmd.alignment = 0; - cmd.binary = false; - cmd.node = devnode_sel::none; - cmd.op = op_sel::none; - cmd.bus_no = 0; - cmd.dev_no = 0; - cmd.fun_no = 0; - cmd.dev_name[0] = '\0'; - cmd.qid = 0; - cmd.size = 4; - cmd.data = nullptr; -} - -static BYTE* allocate_buffer(size_t size, size_t alignment) -{ - if (size == 0) { - size = 4; - } - - if (alignment == 0) { - SYSTEM_INFO sys_info; - GetSystemInfo(&sys_info); - alignment = sys_info.dwPageSize; - } - - return (BYTE*)_aligned_malloc(size, alignment); -} - -int parse_command_line(const int argc, char* argv[]) -{ - /* - * qdma_rw pf

[OPTIONS] [DATA] - * 0 1 2 3 4 5 6... n... - */ - auto argidx = 1; - - if (argc < 2) { - return 1; - } - - if ((strcmp(argv[argidx], "-v") == 0) || (strcmp(argv[argidx], "-V") == 0)) { - printf("%s version %s\n", PROGNAME, VERSION); - printf("%s\n", COPYRIGHT); - exit(0); - } - - init_cmd(); - - if (argc < 5) { - return 1; - } - - if (strncmp(argv[argidx], "qdma", 4)) { - return 1; - } - - strncpy_s(cmd.dev_name, DEV_NAME_MAX_SZ, argv[argidx], _TRUNCATE); - ++argidx; - - if (strncmp(argv[argidx], "mode", 4)) { - return 1; - } - ++argidx; - - cmd.mode = std::stoul(argv[argidx]); - ++argidx; - - if (std::regex_match(argv[argidx], std::regex("queue_mm_[0-9]+"))) { - string qid_str{ argv[argidx] }; - auto it = std::find(qid_str.begin(), qid_str.end(), '_'); - it = it+4; - cout << *it << endl; - cmd.qid = std::stoul(string{ it, qid_str.end() }); - cmd.node = devnode_sel::queue_mm; - } - else if (std::regex_match(argv[argidx], std::regex("queue_st_[0-9]+"))) { - string qid_str{ argv[argidx] }; - auto it = std::find(qid_str.begin(), qid_str.end(), '_'); - it = it + 4; - cmd.qid = std::stoul(string{ it, qid_str.end() }); - cmd.node = devnode_sel::queue_st; - } - else { - return 1; - } - ++argidx; - - if (strcmp(argv[argidx], "read") == 0) { - cmd.op = op_sel::read; - } - else if (strcmp(argv[argidx], "write") == 0) { - cmd.op = op_sel::write; - } - else - return 1; - ++argidx; - - if (cmd.node == devnode_sel::queue_mm) { - cmd.addr = strtoul(argv[argidx], NULL, 0); - ++argidx; - } - else if (cmd.node == devnode_sel::queue_st) { - if (argv[argidx][0] != '-') { - printf("\nErr: ST mode doesn't need the target address option\n\n"); - return 1; - } - } - - while ((argidx < argc) && ((argv[argidx][0] == '-') || (argv[argidx][0] == '/'))) { - switch (argv[argidx][1]) { - case 'l': - argidx++; - cmd.size = strtoul(argv[argidx], NULL, 0); - argidx++; - break; - case 'f': - argidx++; - cmd.file = _strdup(argv[argidx]); - argidx++; - break; - case 'a': - argidx++; - cmd.alignment = strtoul(argv[argidx], NULL, 0); - argidx++; - break; - case 'b': - cmd.binary = TRUE; - argidx++; - break; - case '?': - case 'h': - default: - return 1; - } - } - - if (argidx != argc) { - if (cmd.op == op_sel::write && - cmd.node != devnode_sel::queue_st) { - cmd.size = argc - argidx; - cmd.data = allocate_buffer(cmd.size, cmd.alignment); - if (cmd.data == nullptr) { - cout << "Could not allocate memory for data" << endl; - exit(1); - } - - for (int byteidx = 0; argidx < argc; argidx++, byteidx++) { - cmd.data[byteidx] = (char)strtoul(argv[argidx], NULL, 0); - } - } - else - return 0; - } - - return 0; -} - -int __cdecl main(const int argc, char* argv[]) -{ - try { - if (parse_command_line(argc, argv)) { - help(); - if (cmd.data) _aligned_free(cmd.data); - exit(1); - } - - auto dev_details = get_device_details(GUID_DEVINTERFACE_QDMA); - if (!dev_details.size()) { - std::cerr << "No QDMA Devices found!" << std::endl; - return 1; - } - - device_details dev_info; - auto res = get_device(dev_details, cmd.dev_name, dev_info); - if (res == false) { - printf("Device name is not valid\n"); - if (cmd.data) _aligned_free(cmd.data); - return 1; - } - - cmd.bus_no = dev_info.bus_no; - cmd.dev_no = dev_info.dev_no; - cmd.fun_no = dev_info.fun_no; - qdma_device qdev(dev_info.device_path.c_str()); - - if (cmd.qid >= qdev.get_qmax()) { - if (cmd.data) _aligned_free(cmd.data); - cout << "Invalid qid provided." << endl; - return 1; - } - - if (cmd.op == op_sel::read) { - qdev.qdma_read(); - } - else if (cmd.op == op_sel::write) { - qdev.qdma_write(); - } - } - catch (const std::exception& e) { - if (cmd.data) _aligned_free(cmd.data); - cout << "Error: " << e.what() << '\n'; - } -} diff --git a/QDMA/windows/apps/dma-arw/dma_arw.hpp b/QDMA/windows/apps/dma-arw/dma_arw.hpp deleted file mode 100644 index fd2ea68de..000000000 --- a/QDMA/windows/apps/dma-arw/dma_arw.hpp +++ /dev/null @@ -1,315 +0,0 @@ -/* - * Copyright (C) 2020 Xilinx, Inc - * - * Licensed under the Apache License, Version 2.0 (the "License"). You may - * not use this file except in compliance with the License. You may obtain - * a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - */ - -#include -#include -#include -#include -#include -#include -#include - -#include "device_file.hpp" -#include "qdma_driver_api.h" - -#pragma comment(lib, "setupapi.lib") - -using std::uint32_t; -using std::string; -using std::runtime_error; -using std::cout; -using namespace std; - -#define ST_C2H_MAX_PACK_SIZE_CHUNK 4096 -#define COMPL_WAIT_TIME 100 /* Milli Seconds */ -#define MAX_TIMEOUT_PERIOD 1000 /* Milli Seconds */ -#define FILE_NORMAL_MODE 0 -#define FILE_EX_MODE 1 - -/* ----- common functions ----- */ -static constexpr uint32_t bit(uint64_t n) { - return (1ull << n); -} - -static constexpr bool is_bit_set(uint64_t x, uint64_t n) { - return (x & bit(n)) == bit(n); -} - -static constexpr uint64_t create_mask(uint64_t n, uint64_t l) { - return ((1ull << l) - 1ull) << n; -} - -static constexpr uint32_t get_bits(uint32_t value, uint32_t bit_index, uint32_t len) { - return ((value & create_mask(bit_index, len)) >> bit_index); -} -/* ----- ----- */ - -enum class devnode_sel { - queue_mm, - queue_st, - none -}; - -enum class op_sel { - read, - write, - interrupt, - none -}; - -struct cli_cmd { - op_sel op; - UINT8 bus_no; - UINT8 dev_no; - UINT8 fun_no; - char dev_name[DEV_NAME_MAX_SZ]; - devnode_sel node; - BYTE *data; - LONG addr; - ULONG qid; - int mode; - DWORD size; - string file; - size_t alignment; - BOOL binary; -}; - -template -struct aligned_allocator { - - typedef T value_type; - - aligned_allocator() noexcept {} - - template - aligned_allocator(const aligned_allocator&) noexcept {} - - template - bool operator==(const aligned_allocator&) const noexcept - { - return true; - } - template - bool operator!=(const aligned_allocator&) const noexcept - { - return false; - } - - T* allocate(const std::size_t num) { - if (num == 0) { - return nullptr; - } - - void* const ptr = _aligned_malloc(num * sizeof(T), Alignment); - if (ptr == nullptr) { - throw std::bad_alloc(); - } - return static_cast(ptr); - } - void deallocate(T* const p, std::size_t) { - if (p) { - _aligned_free(p); - } - } - - template - struct rebind { - typedef aligned_allocator other; - }; -}; - -template -using aligned_vector = std::vector>; - -template -void fill_pattern(Iter begin, Iter end) { - std::iota(begin, end, 0); // 0, 1, 2, 3, 4 ... -} - -class data_generator { -public: - using value_type = uint16_t; - - explicit data_generator(const std::string& dev_path) - { - user_bar.open(dev_path + "\\user", GENERIC_WRITE | GENERIC_READ); - } - - ~data_generator() - { - user_bar.close(); - } - - bool check_h2c(const uint32_t qid) - { - const auto match_reg = user_bar.read(0x10); - const auto match_qid = get_bits(match_reg, 4, 28); /* bits 4-31 = qid */ - return (match_qid == qid) && is_bit_set(match_reg, 0); /* bit 0 = match */ - } - - void reset_h2c() - { - user_bar.write(0xC, 0x1); - } - - void reset_pkt_ctrl() - { - user_bar.write(0x8, 0x0); - } - - void set_queue(const uint32_t qid) - { - user_bar.write(0x0, qid); - } - - void configure_c2h(const uint32_t qid, const uint32_t packet_size, const uint32_t num_packets) - { - //printf("DGEN : PKT SIZE : %d, PKT CNT : %d\n", packet_size, num_packets); - set_queue(qid); - user_bar.write(0x4, packet_size); - user_bar.write(0x20, num_packets); - } - - void generate_packets() - { - user_bar.write(0x8, 0x2); - } - - BOOL read(void *buff, LONG addr, DWORD size) - { - if (INVALID_SET_FILE_POINTER == SetFilePointer(user_bar.h, static_cast(addr), nullptr, FILE_BEGIN)) { - return FALSE; - } - - return ReadFile(user_bar.h, buff, size, &size, NULL); - } - - BOOL write(void *buff, LONG addr, DWORD size) - { - if (INVALID_SET_FILE_POINTER == SetFilePointer(user_bar.h, static_cast(addr), nullptr, FILE_BEGIN)) { - return FALSE; - } - - return WriteFile(user_bar.h, buff, size, &size, NULL); - } - - BOOL generate_user_interrupt(UINT32 fun_id) - { - UINT32 val = 0x0; - - val = 0x00; - user_bar.write(0x98, val); - - user_bar.write(0x9C, val); - - val = 0x0; - val = fun_id << 12; - val |= 0x1; - if (fun_id == 0) - val |= (1u << 4); - user_bar.write(0x94, val); - - return TRUE; - } - -private: - device_file user_bar; -}; - -class qdma_device { -public: - HANDLE cmplt_th_handle; - HANDLE cmplt_io_handle; - bool thread_run = false; - bool thread_exit = false; - bool xfer_done = false; - HANDLE sem_xfer_done; - ULONG xfer_size; - ULONG rxd_size; - - void async_env_init(void); - void async_env_exit(void); - void poll_completion(void); - - explicit qdma_device(const char* device_path) : dgen(device_path) - { - using namespace std::string_literals; - dev_path = device_path; - control_bar_.open(dev_path + "\\control"s, GENERIC_READ | GENERIC_WRITE); - mgmt.open(dev_path + "\\mgmt"s, GENERIC_READ | GENERIC_WRITE); - get_qstats(); - } - - ~qdma_device() - { - control_bar_.close(); - mgmt.close(); - } - - void get_qstats(void) - { - struct qstat_out qstats_info = { 0 }; - try { - mgmt.ioctl(IOCTL_QDMA_GET_QSTATS, NULL, 0, &qstats_info, sizeof(qstats_info)); - qbase = qstats_info.qbase; - qmax = qstats_info.qmax; - } - catch (const std::exception& e) { - cout << "IOCTL Failed for qstats " << e.what() << '\n'; - } - } - - unsigned int get_qmax() - { - return qmax; - } - - int qopen(ULONG qid, bool is_mm) - { - DWORD f_attribs = (FILE_ATTRIBUTE_NORMAL | FILE_FLAG_OVERLAPPED | FILE_FLAG_NO_BUFFERING); - if (true == is_mm) - queue_.open(dev_path + "\\queue_"s + to_string(qid), GENERIC_READ | GENERIC_WRITE, f_attribs); - else - queue_.open(dev_path + "\\st_"s + to_string(qid), GENERIC_READ | GENERIC_WRITE, f_attribs); - - async_env_init(); - return 0; - } - - void qclose(void) - { - async_env_exit(); - queue_.close(); - } - - int qdma_read(); - int qdma_write(); - int qdma_interrupt(void); - -private: - const char* dev_path; - device_file control_bar_; - data_generator dgen; - device_file queue_; - device_file mgmt; - unsigned int qbase; - unsigned int qmax; -}; - -static BYTE* allocate_buffer(size_t size, size_t alignment); -static void print_bytes(size_t addr, BYTE* data, size_t length); -static int read_file_option(void); -static void print_bytes_binary(BYTE* data, size_t length); \ No newline at end of file diff --git a/QDMA/windows/apps/dma-arw/dma_arw.vcxproj b/QDMA/windows/apps/dma-arw/dma_arw.vcxproj deleted file mode 100644 index c2a6e3d4d..000000000 --- a/QDMA/windows/apps/dma-arw/dma_arw.vcxproj +++ /dev/null @@ -1,146 +0,0 @@ - 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- - - - {4FC737F1-C7A5-4376-A066-2A32D752A2FF} - cpp;c;cc;cxx;def;odl;idl;hpj;bat;asm;asmx - - - {93995380-89BD-4b04-88EB-625FBE52EBFB} - h;hpp;hxx;hm;inl;inc;xsd - - - {67DA6AB6-F800-4c08-8B7A-83BB121AAD01} - rc;ico;cur;bmp;dlg;rc2;rct;bin;rgs;gif;jpg;jpeg;jpe;resx;tiff;tif;png;wav;mfcribbon-ms - - - - - Header Files - - - Header Files - - - - - Source Files - - - \ No newline at end of file diff --git a/QDMA/windows/apps/dma-arw/dma_arw.vcxproj.user b/QDMA/windows/apps/dma-arw/dma_arw.vcxproj.user deleted file mode 100644 index be2507870..000000000 --- a/QDMA/windows/apps/dma-arw/dma_arw.vcxproj.user +++ /dev/null @@ -1,4 +0,0 @@ - - - - \ No newline at end of file diff --git a/QDMA/windows/apps/dma-arw/version.h b/QDMA/windows/apps/dma-arw/version.h deleted file mode 100644 index 63e122ef8..000000000 --- a/QDMA/windows/apps/dma-arw/version.h +++ /dev/null @@ -1,26 +0,0 @@ -/* - * Copyright (C) 2020 Xilinx, Inc - * - * Licensed under the Apache License, Version 2.0 (the "License"). You may - * not use this file except in compliance with the License. You may obtain - * a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - */ - -#pragma once - -#ifndef __QDMARW_VERSION_H -#define __QDMARW_VERSION_H - -#define PROGNAME "dma-arw" -#define VERSION "2020.2.0" -#define COPYRIGHT "Copyright (c) 2020 Xilinx Inc." - -#endif /*__QDMARW_VERSION_H*/ diff --git a/QDMA/windows/apps/dma-ctl/dmactl.cpp b/QDMA/windows/apps/dma-ctl/dmactl.cpp deleted file mode 100644 index 002486780..000000000 --- a/QDMA/windows/apps/dma-ctl/dmactl.cpp +++ /dev/null @@ -1,1440 +0,0 @@ -/* - * Copyright (C) 2020 Xilinx, Inc - * - * Licensed under the Apache License, Version 2.0 (the "License"). You may - * not use this file except in compliance with the License. You may obtain - * a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - */ - -#include -#include -#include -#include - -#include "device_file.hpp" -#include "qdma_driver_api.h" -#include "version.h" - -#define MAX_VALID_GLBL_IDX 15 -#define MAX_VALID_CMPT_SZ 3 -#define MAX_VALID_INTR_RING_VEC 8 -#define MAX_VALID_BAR_NUM 5 -#define MAX_CMPT_DESC_SZ 64 -#define MAX_INTR_RING_ENTRY_SZ 32 -#define MAX_DUMP_BUFF_SZ 64 * 1024 -#define MAX_REG_INFO_SZ 1024 - -#pragma comment(lib, "setupapi.lib") - -using std::uint32_t; -using std::string; -using std::runtime_error; -using std::cout; -using namespace std; - -const char *desc_engine_mode[] = { - "Internal and Bypass mode", - "Bypass only mode" - "Inernal only mode", -}; - - -static void help(void); - -static bool open_device(const char *dev_name, device_file& device) -{ - device_details dev_info; - - if (dev_name == NULL) { - cout << "Null Parameter provided for dev_name\n"; - return false; - } - - auto dev_details = get_device_details(GUID_DEVINTERFACE_QDMA); - - if (!dev_details.size()) { - cout << "No QDMA Devices found\n"; - return false; - } - - auto res = get_device(dev_details, dev_name, dev_info); - if (res == false) { - printf("Device name requested to open is not valid\n"); - return false; - } - - const auto& dev_path = dev_info.device_path; - device.open(dev_path + "\\mgmt", GENERIC_READ | GENERIC_WRITE); - - return true; -} - -bool sort_fun(device_details d1, device_details d2) -{ - UINT32 bdf_1 = 0x0, bdf_2 = 0x0; - - bdf_1 = (d1.bus_no << 12) | (d1.dev_no << 4) | d1.fun_no; - bdf_2 = (d2.bus_no << 12) | (d2.dev_no << 4) | d2.fun_no; - return (bdf_1 < bdf_2); -} - -static int get_qrange(const char *dev_name, unsigned int& qmax, unsigned int& qbase) -{ - try { - device_file device; - - auto ret = open_device(dev_name, device); - if (ret == false) - return 1; - - struct qstat_out qstats_info = { 0 }; - device.ioctl(IOCTL_QDMA_GET_QSTATS, NULL, 0, &qstats_info, sizeof(qstats_info)); - qmax = qstats_info.qmax; - qbase = qstats_info.qbase; - } - catch (const std::exception& e) { - cout << "Failed to get qmax from ioctl : " << e.what() << '\n'; - } - - return 0; -} - -static int handle_dev_cmds(const int argc, char* argv[]) -{ - auto i = 0; - - if (0 == argc) { - return 1; - } - - while (i < argc) { - if (strcmp(argv[i], "list") == 0) { - auto device_details = get_device_details(GUID_DEVINTERFACE_QDMA); - UINT32 prev_bus = 0x000000; - - if (!device_details.size()) { - printf("\nNo QDMA Devices present in the system\n\n"); - break; - } - - std::sort(device_details.begin(), device_details.end(), sort_fun); - - for (auto idx = 0; idx < (int)device_details.size(); idx++) { - unsigned int qmax = 0, qbase = 0; - int ret = get_qrange(device_details[idx].device_name.c_str(), qmax, qbase); - if (ret) - return 1; - - auto bus_no = device_details[idx].bus_no; - auto dev_no = device_details[idx].dev_no; - auto fun_no = device_details[idx].fun_no; - auto end_q = qbase + qmax - 1; - - if (prev_bus != bus_no) { - printf("\n"); - prev_bus = bus_no; - } - - printf("%s\t0000:%02X:%02X:%01X\tmaxQP: %d, %d~%d\n", device_details[idx].device_name.c_str(), bus_no, dev_no, fun_no, qmax, qbase, end_q); - } - printf("\n"); - } - else { - cout << "Unknown command " << argv[i] << endl; - return 1; - } - ++i; - } - - return 0; -} -static int handle_csr_cmds(const char *dev_name, const int argc, char* argv[]) -{ - auto i = 0; - device_file device; - - auto ret = open_device(dev_name, device); - if (ret == false) - return 0; - - while (i < argc) { - if (strcmp(argv[i], "dump") == 0) { - ioctl_cmd cmd = {}; - DWORD ioctl_code = IOCTL_QDMA_CSR_DUMP; - - cmd.csr.out = (struct csr_conf_out *)new struct csr_conf_out; - - try { - device.ioctl(ioctl_code, NULL, 0, cmd.csr.out, sizeof(struct csr_conf_out)); - printf("Global CSR :\n"); - - printf("Index Ring size Timer count Threshold count Buffer size\n"); - for (auto ind = 0; ind < QDMA_CSR_SZ; ++ind) - printf("%-10d%-20u%-20u%-20u%-20u\n", - ind, - cmd.csr.out->ring_sz[ind], - cmd.csr.out->c2h_timer_cnt[ind], - cmd.csr.out->c2h_th_cnt[ind], - cmd.csr.out->c2h_buff_sz[ind]); - - delete cmd.csr.out; - } - catch (const std::exception& e) { - delete cmd.csr.out; - cout << "Failed to dump CSR from ioctl : " << e.what() << '\n'; - } - } - else { - return 1; - } - - ++i; - } - - return 0; -} - -static int handle_devinfo(const char *dev_name) -{ - device_file device; - - auto ret = open_device(dev_name, device); - if (ret == false) - return 0; - - ioctl_cmd cmd = {}; - DWORD ioctl_code = IOCTL_QDMA_DEVINFO; - - cmd.dev_info.out = (struct device_info_out *)new struct device_info_out; - - try { - device.ioctl(ioctl_code, NULL, 0, cmd.dev_info.out, sizeof(struct device_info_out)); - - printf("=============Hardware Version=================\n"); - printf("%-35s : %s\n", "RTL Version", cmd.dev_info.out->ver_info.qdma_rtl_version_str); - printf("%-35s : %s\n", "Vivado ReleaseID", cmd.dev_info.out->ver_info.qdma_vivado_release_id_str); - printf("%-35s : %s\n", "Device Type", cmd.dev_info.out->ver_info.qdma_device_type_str); - if (strstr(cmd.dev_info.out->ver_info.qdma_device_type_str, "Versal IP") != NULL) - printf("%-35s : %s\n", "Versal IP Type", cmd.dev_info.out->ver_info.qdma_versal_ip_type_str); - printf("\n"); - - printf("=============Software Version=================\n"); - printf("%-35s : %s\n", "qdma driver version", cmd.dev_info.out->ver_info.qdma_sw_version); - printf("\n"); - - printf("=============Hardware Capabilities============\n"); - - printf("%-35s : %d\n", "Number of PFs supported", cmd.dev_info.out->num_pfs); - printf("%-35s : %d\n", "Total number of queues supported", cmd.dev_info.out->num_qs); - printf("%-35s : %d\n", "MM channels", cmd.dev_info.out->num_mm_channels); - printf("%-35s : %s\n", "FLR Present", cmd.dev_info.out->flr_present ? "yes" : "no"); - printf("%-35s : %s\n", "ST enabled", cmd.dev_info.out->st_en ? "yes" : "no"); - printf("%-35s : %s\n", "MM enabled", cmd.dev_info.out->mm_en ? "yes" : "no"); - printf("%-35s : %s\n", "Mailbox enabled", cmd.dev_info.out->mailbox_en ? "yes" : "no"); - printf("%-35s : %s\n", "MM completion enabled", cmd.dev_info.out->mm_cmpl_en ? "yes" : "no"); - printf("%-35s : %s\n", "Debug Mode enabled", cmd.dev_info.out->debug_mode ? "yes" : "no"); - if (cmd.dev_info.out->desc_eng_mode < sizeof(desc_engine_mode) / sizeof(desc_engine_mode[0])) { - printf("%-35s : %s\n", "Desc Engine Mode", desc_engine_mode[cmd.dev_info.out->desc_eng_mode]); - } - else { - printf("%-35s : %s\n", "Desc Engine Mode", "Invalid"); - } - - printf("\n"); - - delete cmd.dev_info.out; - } - catch (const std::exception& e) { - delete cmd.dev_info.out; - cout << "Failed to get devinfo from ioctl : " << e.what() << '\n'; - } - return 0; -} - -static int handle_qmax(const char *dev_name, const int argc, char* argv[]) -{ - ioctl_cmd cmd = {}; - DWORD ioctl_code = IOCTL_QDMA_SET_QMAX; - - if (argc > 1) { - cout << "Only one argument is required" << endl; - return 1; - } - - cmd.qmax_info.in.qmax = (unsigned short)strtoul(argv[0], NULL, 0); - - try { - device_file device; - - auto ret = open_device(dev_name, device); - if (ret == false) - return 0; - - device.ioctl(ioctl_code, &cmd.qmax_info.in, sizeof(cmd.qmax_info.in), NULL, 0); - cout << "Set qmax successfull" << endl; - } - catch (const std::exception& e) { - cout << "Failed to set qmax.\n" << e.what() << '\n'; - } - - return 0; -} - -static int handle_qstats(const char *dev_name) -{ - ioctl_cmd cmd = {}; - DWORD ioctl_code = IOCTL_QDMA_GET_QSTATS; - cmd.qstats_info.out = new struct qstat_out; - - try { - device_file device; - - auto ret = open_device(dev_name, device); - if (ret == false) - return 0; - - device.ioctl(ioctl_code, NULL, 0, cmd.qstats_info.out, sizeof(struct qstat_out)); - - printf("Device : %s\n", dev_name); - printf("Maximum queues : %u\n", cmd.qstats_info.out->qmax); - printf("Active H2C queues : %u\n", cmd.qstats_info.out->active_h2c_queues); - printf("Active C2H queues : %u\n", cmd.qstats_info.out->active_c2h_queues); - printf("Active CMPT queues : %u\n", cmd.qstats_info.out->active_cmpt_queues); - } - catch (const std::exception& e) { - cout << "Failed to set qmax.\n" << e.what() << '\n'; - } - - return 0; -} - -static int handle_add_queue(const char *dev_name, const int argc, char* argv[]) -{ - auto i = 0; - ioctl_cmd cmd = {}; - DWORD ioctl_code = IOCTL_QDMA_QUEUE_ADD; - bool mode, qid, h2c_ring_sz, c2h_ring_sz, c2h_timer, c2h_th, c2h_buff_sz; - bool cmplsz, trigmode; - mode = qid = h2c_ring_sz = c2h_ring_sz = c2h_timer = c2h_th = c2h_buff_sz = false; - cmplsz = trigmode = false; - - while (i < argc) { - if (strcmp(argv[i], "mode") == 0) { - ++i; - - if (strcmp(argv[i], "mm") == 0) { - cmd.q_conf.in.is_st = 0; - } - else if (strcmp(argv[i], "st") == 0) { - cmd.q_conf.in.is_st = 1; - } - else { - cout << "Unknown command " << argv[i] << endl; - return 1; - } - mode = true; - } - else if (strcmp(argv[i], "qid") == 0) { - ++i; - cmd.q_conf.in.qid = (unsigned short)strtoul(argv[i], NULL, 0); - cout << "Adding queue ::" << cmd.q_conf.in.qid << endl; - qid = true; - } - else if (strcmp(argv[i], "en_mm_cmpl") == 0) { - cmd.q_conf.in.en_mm_cmpl = true; - } - else if (strcmp(argv[i], "idx_h2c_ringsz") == 0) { - ++i; - cmd.q_conf.in.h2c_ring_sz_index = (unsigned char)strtoul(argv[i], NULL, 0); - if (MAX_VALID_GLBL_IDX < cmd.q_conf.in.h2c_ring_sz_index) { - cout << "Invalid h2c ring size index : " << argv[i] << endl; - return 1; - } - h2c_ring_sz = true; - } - else if (strcmp(argv[i], "idx_c2h_ringsz") == 0) { - ++i; - cmd.q_conf.in.c2h_ring_sz_index = (unsigned char)strtoul(argv[i], NULL, 0); - if (MAX_VALID_GLBL_IDX < cmd.q_conf.in.c2h_ring_sz_index) { - cout << "Invalid c2h ring size index : " << argv[i] << endl; - return 1; - } - c2h_ring_sz = true; - } - else if (strcmp(argv[i], "idx_c2h_timer") == 0) { - ++i; - cmd.q_conf.in.c2h_timer_cnt_index = (unsigned char)strtoul(argv[i], NULL, 0); - if (MAX_VALID_GLBL_IDX < cmd.q_conf.in.c2h_timer_cnt_index) { - cout << "Invalid c2h timer index : " << argv[i] << endl; - return 1; - } - c2h_timer = true; - } - else if (strcmp(argv[i], "idx_c2h_th") == 0) { - ++i; - cmd.q_conf.in.c2h_th_cnt_index = (unsigned char)strtoul(argv[i], NULL, 0); - if (MAX_VALID_GLBL_IDX < cmd.q_conf.in.c2h_th_cnt_index) { - cout << "Invalid c2h threshold index : " << argv[i] << endl; - return 1; - } - c2h_th = true; - } - else if (strcmp(argv[i], "idx_c2h_bufsz") == 0) { - ++i; - cmd.q_conf.in.c2h_buff_sz_index = (unsigned char)strtoul(argv[i], NULL, 0); - if (MAX_VALID_GLBL_IDX < cmd.q_conf.in.c2h_buff_sz_index) { - cout << "Invalid c2h buffer size index : " << argv[i] << endl; - return 1; - } - c2h_buff_sz = true; - } - else if (strcmp(argv[i], "cmptsz") == 0) { - ++i; - unsigned char compl_sz = (unsigned char)strtoul(argv[i], NULL, 0); - if (compl_sz == 0) - cmd.q_conf.in.compl_sz = CMPT_DESC_SZ_8B; - else if (compl_sz == 1) - cmd.q_conf.in.compl_sz = CMPT_DESC_SZ_16B; - else if (compl_sz == 2) - cmd.q_conf.in.compl_sz = CMPT_DESC_SZ_32B; - else if (compl_sz == 3) - cmd.q_conf.in.compl_sz = CMPT_DESC_SZ_64B; - else { - cout << "Invalid c2h completion size : " << argv[i] << endl; - return 1; - } - cmplsz = true; - } - else if (strcmp(argv[i], "trigmode") == 0) { - ++i; - - if (strcmp(argv[i], "every") == 0) { - cmd.q_conf.in.trig_mode = TRIG_MODE_EVERY; - } - else if (strcmp(argv[i], "usr_cnt") == 0) { - cmd.q_conf.in.trig_mode = TRIG_MODE_USER_COUNT; - } - else if (strcmp(argv[i], "usr") == 0) { - cmd.q_conf.in.trig_mode = TRIG_MODE_USER; - } - else if (strcmp(argv[i], "usr_tmr") == 0) { - cmd.q_conf.in.trig_mode = TRIG_MODE_USER_TIMER; - } - else if (strcmp(argv[i], "usr_tmr_cnt") == 0) { - cmd.q_conf.in.trig_mode = TRIG_MODE_USER_TIMER_COUNT; - } - else { - cout << "Invalid trigger mode : " << argv[i] << endl; - return 1; - } - - trigmode = true; - } - else if (strcmp(argv[i], "sw_desc_sz") == 0) { - ++i; - cmd.q_conf.in.sw_desc_sz = (unsigned char)strtoul(argv[i], NULL, 0); - if (cmd.q_conf.in.sw_desc_sz != 3) { - cout << "sw_desc_sz must be 3\n"; - cout << "Only 64B descriptor(3) can be configured in bypass mode\n"; - return 1; - } - } - else if (strcmp(argv[i], "desc_bypass_en") == 0) { - cmd.q_conf.in.desc_bypass_en = true; - } - else if (strcmp(argv[i], "pfch_en") == 0) { - cmd.q_conf.in.pfch_en = true; - } - else if (strcmp(argv[i], "pfch_bypass_en") == 0) { - cmd.q_conf.in.pfch_bypass_en = true; - } - else if (strcmp(argv[i], "cmpl_ovf_dis") == 0) { - cmd.q_conf.in.cmpl_ovf_dis = true; - } - else { - cout << "Unknown command " << argv[i] << endl; - return 1; - } - - ++i; - } - - if (!mode || !qid || !h2c_ring_sz || !c2h_ring_sz) { - cout << "Insufficient options provided\n"; - return 1; - } - - if (!cmd.q_conf.in.is_st && - (c2h_buff_sz || cmd.q_conf.in.pfch_en - || cmd.q_conf.in.pfch_bypass_en)) { - cout << "Invalid arguments for MM mode\n"; - return 1; - } - - if ((!cmd.q_conf.in.desc_bypass_en) && (cmd.q_conf.in.sw_desc_sz == 3)) { - cout << "Invalid Parameter Combination : "; - cout << "desc_bypass_en : " << cmd.q_conf.in.desc_bypass_en << ", sw_desc_sz : " << cmd.q_conf.in.sw_desc_sz << endl; - cout << "64 Byte Descriptor supported only when descriptor bypass is enabled\n"; - } - - try { - device_file device; - - auto ret = open_device(dev_name, device); - if (ret == false) - return 0; - - device.ioctl(ioctl_code, &cmd.q_conf.in, sizeof(cmd.q_conf.in), NULL, 0); - cout << "Added Queue " << cmd.q_conf.in.qid << " Successfully\n"; - } - catch (const std::exception& e) { - cout << "Failed to add queue.\n" << e.what() << '\n'; - } - - return 0; -} - -static int handle_start_queue(const char *dev_name, const int argc, char* argv[]) -{ - auto i = 0; - ioctl_cmd cmd = {}; - DWORD ioctl_code = IOCTL_QDMA_QUEUE_START; - - while (i < argc) { - if (strcmp(argv[i], "qid") == 0) { - ++i; - cmd.q_conf.in.qid = (unsigned short)strtoul(argv[i], NULL, 0); - cout << "Starting queue :: " << cmd.q_conf.in.qid << endl; - } - else { - cout << "Unknown command " << argv[i] << endl; - return 1; - } - - ++i; - } - - try { - device_file device; - - auto ret = open_device(dev_name, device); - if (ret == false) - return 0; - - device.ioctl(ioctl_code, &cmd.q_conf.in, sizeof(cmd.q_conf.in), NULL, 0); - cout << "Started Queue " << cmd.q_conf.in.qid << " Successfully\n"; - } - catch (const std::exception& e) { - cout << "Failed to start queue.\n" << e.what() << '\n'; - } - - return 0; -} - -static int handle_stop_queue(const char *dev_name, const int argc, char* argv[]) -{ - auto i = 0; - ioctl_cmd cmd = {}; - DWORD ioctl_code = IOCTL_QDMA_QUEUE_STOP; - - while (i < argc) { - if (strcmp(argv[i], "qid") == 0) { - ++i; - cmd.q_conf.in.qid = (unsigned short)strtoul(argv[i], NULL, 0); - cout << "Stopping queue : " << cmd.q_conf.in.qid << endl; - } - else { - cout << "Unknown command " << argv[i] << endl; - return 1; - } - - ++i; - } - - try { - device_file device; - - auto ret = open_device(dev_name, device); - if (ret == false) - return 0; - - device.ioctl(ioctl_code, &cmd.q_conf.in, sizeof(cmd.q_conf.in), NULL, 0); - cout << "Stopped Queue " << cmd.q_conf.in.qid << " Successfully\n"; - } - catch (const std::exception& e) { - cout << "Failed to stop queue.\n" << e.what() << '\n'; - } - - return 0; -} - -static int handle_delete_queue(const char *dev_name, const int argc, char* argv[]) -{ - auto i = 0; - ioctl_cmd cmd = {}; - DWORD ioctl_code = IOCTL_QDMA_QUEUE_DELETE; - - while (i < argc) { - if (strcmp(argv[i], "qid") == 0) { - ++i; - cmd.q_conf.in.qid = (unsigned short)strtoul(argv[i], NULL, 0); - cout << "Deleting queue :: " << cmd.q_conf.in.qid << endl; - } - else { - cout << "Unknown command " << argv[i] << endl; - return 1; - } - - ++i; - } - - try { - device_file device; - - auto ret = open_device(dev_name, device); - if (ret == false) - return 0; - - device.ioctl(ioctl_code, &cmd.q_conf.in, sizeof(cmd.q_conf.in), NULL, 0); - cout << "Deleted Queue " << cmd.q_conf.in.qid << " Successfully\n"; - } - catch (const std::exception& e) { - cout << "Failed to delete queue.\n" << e.what() << '\n'; - } - - return 0; -} - -static int handle_queue_state(const char *dev_name, const int argc, char* argv[]) -{ - auto i = 0; - ioctl_cmd cmd = {}; - DWORD ioctl_code = IOCTL_QDMA_QUEUE_DUMP_STATE; - - if (i == argc) { - cout << "insufficient argument\n"; - return 1; - } - - while (i < argc) { - if (strcmp(argv[i], "qid") == 0) { - ++i; - cmd.q_state.in.qid = static_cast(strtoul(argv[i], NULL, 0)); - } - else { - cout << "Unknown command " << argv[i] << endl; - return 1; - } - - ++i; - } - - try { - device_file device; - auto ret = open_device(dev_name, device); - if (ret == false) - return 0; - - cmd.q_state.out = (struct queue_state_out *)new struct queue_state_out; - - if (device.ioctl(ioctl_code, &cmd.q_state.in, sizeof(cmd.q_state.in), - cmd.q_state.out, sizeof(struct queue_state_out))) { - printf("%5s%20s\n", "QID", "STATE"); - printf("%5s%20s\n", "---", "-----"); - printf("%5u%20s\n", cmd.q_state.in.qid, cmd.q_state.out->state); - } - delete cmd.q_state.out; - } - catch (const std::exception& e) { - delete cmd.q_state.out; - cout << "Failed to get queue state.\n" << e.what() << '\n'; - } - - return 0; -} -static int handle_queue_dump(const char *dev_name, const int argc, char* argv[]) -{ - auto i = 0; - bool qid_valid = false, dir_valid = false, desc_valid = false, cmpt_valid = false; - bool type_valid = false; - bool ctx_valid = false; - unsigned short qid = 0; - enum queue_direction dir = QUEUE_DIR_H2C; - enum ring_type type = ring_type::RING_TYPE_H2C; - ioctl_cmd cmd = {}; - DWORD ioctl_code = 0; - - if (i == argc) { - cout << "insufficient argument\n"; - return 1; - } - - while (i < argc) { - if (strcmp(argv[i], "qid") == 0) { - if (argv[i + 1] == NULL) { - cout << "Insufficient options provided\n"; - cout << "qid option needs as an argument : \n"; - return 1; - } - - ++i; - qid = static_cast(strtoul(argv[i], NULL, 0)); - qid_valid = true; - } - else if (strcmp(argv[i], "dir") == 0) { - if (argv[i + 1] == NULL) { - cout << "Insufficient options provided\n"; - cout << "dir option needs as an argument : h2c/c2h\n"; - return 1; - } - - ++i; - if (strcmp(argv[i], "h2c") == 0) { - dir = QUEUE_DIR_H2C; - } - else if (strcmp(argv[i], "c2h") == 0) { - dir = QUEUE_DIR_C2H; - } - else { - cout << "Invalid direction : " << argv[i] << endl; - return 1; - } - dir_valid = true; - } - else if (strcmp(argv[i], "type") == 0) { - if (argv[i + 1] == NULL) { - cout << "Insufficient options provided\n"; - cout << "type option needs as an argument : h2c/c2h/cmpt\n"; - return 1; - } - - ++i; - if (strcmp(argv[i], "h2c") == 0) { - type = ring_type::RING_TYPE_H2C; - } - else if (strcmp(argv[i], "c2h") == 0) { - type = ring_type::RING_TYPE_C2H; - } - else if (strcmp(argv[i], "cmpt") == 0) { - type = ring_type::RING_TYPE_CMPT; - } - else { - cout << "Invalid ring type : " << argv[i] << endl; - return 1; - } - type_valid = true; - } - else if (strcmp(argv[i], "desc") == 0) { - if ((argv[i + 1] == NULL) || (argv[i + 2] == NULL)) { - cout << "Insufficient options provided\n"; - cout << "desc option needs two arguments : and \n"; - return 1; - } - - ioctl_code = IOCTL_QDMA_QUEUE_DUMP_DESC; - cmd.desc_info.in.desc_type = RING_DESC; - - ++i; - cmd.desc_info.in.desc_start = strtoul(argv[i], NULL, 0); - - ++i; - cmd.desc_info.in.desc_end = strtoul(argv[i], NULL, 0); - - if (cmd.desc_info.in.desc_end < cmd.desc_info.in.desc_start) { - cout << "Insufficient range : "; - cout << cmd.desc_info.in.desc_start << "~" << cmd.desc_info.in.desc_end << endl; - return 1; - } - - desc_valid = true; - } - else if (strcmp(argv[i], "cmpt") == 0) { - if ((argv[i + 1] == NULL) || (argv[i + 2] == NULL)) { - cout << "Insufficient options provided\n"; - cout << "desc option needs two arguments : and \n"; - return 1; - } - - ioctl_code = IOCTL_QDMA_QUEUE_DUMP_DESC; - cmd.desc_info.in.desc_type = CMPT_DESC; - - ++i; - cmd.desc_info.in.desc_start = strtoul(argv[i], NULL, 0); - - ++i; - cmd.desc_info.in.desc_end = strtoul(argv[i], NULL, 0); - - if (cmd.desc_info.in.desc_end < cmd.desc_info.in.desc_start) { - cout << "Insufficient range : "; - cout << cmd.desc_info.in.desc_start << "~" << cmd.desc_info.in.desc_end << endl; - return 1; - } - - cmpt_valid = true; - } - else if (strcmp(argv[i], "ctx") == 0) { - ioctl_code = IOCTL_QDMA_QUEUE_DUMP_CTX; - ctx_valid = true; - } - else { - cout << "Unknown command " << argv[i] << endl; - return 1; - } - - ++i; - } - - if (!qid_valid || (!dir_valid && !cmpt_valid && !type_valid) || - (!desc_valid && !cmpt_valid && !ctx_valid) || - (type_valid ^ ctx_valid)) { - cout << "Insufficient options provided\n"; - return 1; - } - - try { - device_file device; - auto ret = open_device(dev_name, device); - if (ret == false) - return 0; - - unsigned int size; - unsigned int out_size; - - if (ctx_valid) { - cmd.ctx_info.in.qid = qid; - cmd.ctx_info.in.type = type; - /* Allocate memory for the maximum possible context size */ - size = MAX_DUMP_BUFF_SZ; - - out_size = sizeof(struct ctx_dump_info_out) + size; - cmd.ctx_info.out = (struct ctx_dump_info_out *)new char[out_size]; - cmd.ctx_info.out->ret_sz = 0; - - device.ioctl(ioctl_code, &cmd.ctx_info.in, sizeof(cmd.ctx_info.in), - cmd.ctx_info.out, out_size); - - if (!cmd.ctx_info.out->ret_sz) { - printf("Failed to dump the queue context\n"); - } - else { - char *addr = (char *)&cmd.ctx_info.out->pbuffer[0]; - for (i = 0; ((i < (int)cmd.ctx_info.out->ret_sz) && (addr[i] != '\0')); i++) { - printf("%c", addr[i]); - } - } - delete[] cmd.ctx_info.out; - } - else { - cmd.desc_info.in.qid = qid; - cmd.desc_info.in.dir = dir; - /* Allocate memory for the maximum possible combination of desc size */ - size = (cmd.desc_info.in.desc_end - cmd.desc_info.in.desc_start + 1) * 64; - - out_size = sizeof(struct desc_dump_info_out) + size; - cmd.desc_info.out = (struct desc_dump_info_out *)new unsigned char[out_size]; - cmd.desc_info.out->desc_sz = 0; - cmd.desc_info.out->data_sz = 0; - - device.ioctl(ioctl_code, &cmd.desc_info.in, sizeof(cmd.desc_info.in), - cmd.desc_info.out, out_size); - - if (!&cmd.desc_info.out->desc_sz || !cmd.desc_info.out->data_sz) { - printf("Failed to dump the queue descriptors\n"); - } - else { - auto desc_index = cmd.desc_info.in.desc_start; - auto desc_cnt = cmd.desc_info.out->data_sz / cmd.desc_info.out->desc_sz; - auto n = cmd.desc_info.out->desc_sz / 4; - UINT32 *addr = (UINT32 *)&cmd.desc_info.out->pbuffer[0]; - - for (i = 0; i < (int)desc_cnt; i++) { - printf("%5d : ", desc_index++); - for (UINT16 j = 0; j < n; j++) { - printf("%08X ", addr[(i * n) + j]); - } - printf("\n"); - } - } - - - delete[] cmd.desc_info.out; - } - } - catch (const std::exception& e) { - if (ctx_valid) - delete[] cmd.ctx_info.out; - else - delete[] cmd.desc_info.out; - - cout << "Failed to dump queue descriptors.\n" << e.what() << '\n'; - } - - return 0; - -} - -static int handle_queue_cmpt_read(const char *dev_name, const int argc, char* argv[]) -{ - auto i = 0; - bool qid_valid = false; - ioctl_cmd cmd = {}; - DWORD ioctl_code = 0x0; - - if (i == argc) { - cout << "insufficient argument\n"; - return 1; - } - - while (i < argc) { - if (strcmp(argv[i], "qid") == 0) { - if (argv[i + 1] == NULL) { - cout << "Insufficient options provided\n"; - cout << "qid option needs as an argument : \n"; - return 1; - } - - ++i; - cmd.cmpt_info.in.qid = static_cast(strtoul(argv[i], NULL, 0)); - qid_valid = true; - } - else { - cout << "Unknown command " << argv[i] << endl; - return 1; - } - - ++i; - } - - if (!qid_valid) { - cout << "Insufficient options provided: qid option is must to execute cmpt_read command\n"; - return 1; - } - - try { - device_file device; - auto ret = open_device(dev_name, device); - if (ret == false) - return 0; - - unsigned int size = 10 * MAX_CMPT_DESC_SZ; - ioctl_code = IOCTL_QDMA_QUEUE_CMPT_READ; - - unsigned int out_size = sizeof(struct cmpt_data_info_out) + size; - cmd.cmpt_info.out = (struct cmpt_data_info_out *)new unsigned char[out_size]; - bool is_data_avail = false; - UINT32 cmpt_data_idx = 0; - do { - cmd.cmpt_info.out->ret_len = 0; - cmd.cmpt_info.out->cmpt_desc_sz = 0; - - memset(&cmd.cmpt_info.out->pbuffer[0], 0xDEADBEEF, size); - - device.ioctl(ioctl_code, &cmd.cmpt_info.in, sizeof(cmd.cmpt_info.in), - cmd.cmpt_info.out, out_size); - - if (!cmd.cmpt_info.out->cmpt_desc_sz || !cmd.cmpt_info.out->ret_len) { - if (is_data_avail == false) - printf("Completion Data not available\n"); - } - else { - is_data_avail = true; - auto n = cmd.cmpt_info.out->cmpt_desc_sz / 4; - auto desc_cnt = cmd.cmpt_info.out->ret_len / cmd.cmpt_info.out->cmpt_desc_sz; - UINT32 *addr = (UINT32 *)&cmd.cmpt_info.out->pbuffer[0]; - for (i = 0; i < (int)desc_cnt; i++) { - printf("%5d : ", cmpt_data_idx++); - for (auto j = 0U; j < n; j++) { - printf("%08X ", addr[(i * n) + j]); - } - printf("\n"); - } - } - } while (cmd.cmpt_info.out->ret_len); - - delete[] cmd.cmpt_info.out; - } - catch (const std::exception& e) { - delete[] cmd.cmpt_info.out; - cout << "Failed to execute cmpt_read command.\n" << e.what() << '\n'; - } - - return 0; -} - -static int handle_queue_listall(const char *dev_name) -{ - ioctl_cmd cmd = {}; - DWORD ioctl_code = IOCTL_QDMA_QUEUE_DUMP_STATE; - - try { - device_file device; - unsigned int qmax = 0, qbase = 0; - bool ret = open_device(dev_name, device); - if (ret == false) - return 0; - - ret = get_qrange(dev_name, qmax, qbase); - if (ret) - return 1; - - cmd.q_state.out = (struct queue_state_out *)new struct queue_state_out; - - printf("%5s%20s\n", "QID", "STATE"); - printf("%5s%20s\n", "---", "-----"); - for (unsigned short i = 0; i < qmax; i++) { - memset(cmd.q_state.out, 0, sizeof(struct queue_state_out)); - - cmd.q_state.in.qid = i; - - if (device.ioctl(ioctl_code, &cmd.q_state.in, sizeof(cmd.q_state.in), - cmd.q_state.out, sizeof(struct queue_state_out))) { - printf("%5u%20s\n", cmd.q_state.in.qid, cmd.q_state.out->state); - } - } - delete cmd.q_state.out; - } - catch (const std::exception& e) { - delete cmd.q_state.out; - cout << "Failed to get queue state.\n" << e.what() << '\n'; - } - - return 0; -} - -static int handle_intring_dump(const char *dev_name, const int argc, char* argv[]) -{ - auto i = 0; - bool vector_valid = false; - bool index_valid = false; - ioctl_cmd cmd = {}; - DWORD ioctl_code = 0x0; - - if (i == argc) { - cout << "insufficient argument\n"; - return 1; - } - - while (i < argc) { - if (strcmp(argv[i], "vector") == 0) { - if ((argv[i + 1] == NULL) || (argv[i + 2] == NULL) || (argv[i + 3] == NULL)) { - cout << "Insufficient options provided\n"; - cout << "vector option needs as three arguments : \n"; - return 1; - } - - ++i; - cmd.int_ring_info.in.vec_id = strtoul(argv[i], NULL, 0); - if (MAX_VALID_INTR_RING_VEC < cmd.int_ring_info.in.vec_id) { - cout << "Invalid intr vector id : " << argv[i] << endl; - break; - } - vector_valid = true; - - ++i; - cmd.int_ring_info.in.start_idx = strtoul(argv[i], NULL, 0); - ++i; - cmd.int_ring_info.in.end_idx = strtoul(argv[i], NULL, 0); - if (cmd.int_ring_info.in.start_idx > cmd.int_ring_info.in.end_idx) { - cout << "Start index must be less than or equal to end index" << endl; - break; - } - index_valid = true; - } - else { - cout << "Unknown command " << argv[i] << endl; - return 1; - } - ++i; - } - - if (!vector_valid || !index_valid) { - cout << "Insufficient options provided\n"; - return 1; - } - - try { - device_file device; - auto ret = open_device(dev_name, device); - if (ret == false) - return 0; - - unsigned int size = - (cmd.int_ring_info.in.end_idx - cmd.int_ring_info.in.start_idx + 1) * MAX_INTR_RING_ENTRY_SZ; - - unsigned int out_size = sizeof (struct intring_info_out) + size; - - cmd.int_ring_info.out = (struct intring_info_out *)new unsigned char[out_size]; - - cmd.int_ring_info.out->ret_len = 0; - cmd.int_ring_info.out->ring_entry_sz = 0; - - ioctl_code = IOCTL_QDMA_INTRING_DUMP; - - device.ioctl(ioctl_code, &cmd.int_ring_info.in, sizeof(cmd.int_ring_info.in), - cmd.int_ring_info.out, out_size); - - if (!cmd.int_ring_info.out->ring_entry_sz || !cmd.int_ring_info.out->ret_len) { - printf("Failed to dump the intr ring\n"); - } - else { - auto start_idx = cmd.int_ring_info.in.start_idx; - auto ring_entry_cnt = cmd.int_ring_info.out->ret_len / cmd.int_ring_info.out->ring_entry_sz; - auto n = cmd.int_ring_info.out->ring_entry_sz / 4; - UINT32 *addr = (UINT32 *)&cmd.int_ring_info.out->pbuffer[0]; - for (i = 0; i < (int)ring_entry_cnt; i++) { - printf("%5d : ", start_idx++); - for (UINT16 j = 0; j < n; j++) { - printf("%08X ", addr[(i * n) + j]); - } - printf("\n"); - } - } - delete[] cmd.int_ring_info.out; - } - catch (const std::exception& e) { - delete[] cmd.int_ring_info.out; - cout << "Failed to execute intring dump command.\n" << e.what() << '\n'; - } - - return 0; -} - -static int handle_reg_dump(const char *dev_name, const int argc, char* argv[]) -{ - UNREFERENCED_PARAMETER(argc); - UNREFERENCED_PARAMETER(argv); - - ioctl_cmd cmd = {}; - DWORD ioctl_code = 0x0; - - try { - device_file device; - auto ret = open_device(dev_name, device); - if (ret == false) - return 0; - - unsigned int size = MAX_DUMP_BUFF_SZ; - - unsigned int out_size = sizeof(struct regdump_info_out) + size; - cmd.reg_dump_info.out = (struct regdump_info_out *)new char[out_size]; - cmd.reg_dump_info.out->ret_len = 0; - - ioctl_code = IOCTL_QDMA_REG_DUMP; - - device.ioctl(ioctl_code, NULL, 0, cmd.reg_dump_info.out, out_size); - - if (!cmd.reg_dump_info.out->ret_len) { - printf("Failed to dump the registers\n"); - } - else { - char *addr = (char *)&cmd.reg_dump_info.out->pbuffer[0]; - for (auto i = 0; ((i < (int)cmd.reg_dump_info.out->ret_len) && (addr[i] != '\0')); i++) { - printf("%c", addr[i]); - } - } - delete[] cmd.reg_dump_info.out; - } - catch (const std::exception& e) { - delete[] cmd.reg_dump_info.out; - cout << "Failed to execute reg dump command.\n" << e.what() << '\n'; - } - - return 0; -} - - -static int handle_reg_info(const char* dev_name, const int argc, char* argv[]) -{ - UNREFERENCED_PARAMETER(dev_name); - UNREFERENCED_PARAMETER(argc); - UNREFERENCED_PARAMETER(argv); - auto i = 0; - bool bar_valid = false; - ioctl_cmd cmd = {}; - DWORD ioctl_code = 0x0; - - if (i == argc) { - cout << "insufficient arguments\n"; - return 1; - } - - while (i < argc) { - if (strcmp(argv[i], "bar") == 0) { - if ((argv[i + 1] == NULL) || (argv[i + 2] == NULL)) { - cout << "Insufficient options provided\n"; - cout << "bar option needs atleast two arguments :
[num_regs ]\n"; - return 1; - } - - ++i; - cmd.reg_info.in.bar_no = strtoul(argv[i], NULL, 0); - if ((MAX_VALID_BAR_NUM < cmd.reg_info.in.bar_no) && - ((cmd.reg_info.in.bar_no % 2) != 0)) { - cout << "Invalid BAR number provided : " << argv[i] << endl; - break; - } - cmd.reg_info.in.bar_no = cmd.reg_info.in.bar_no / 2; - bar_valid = true; - - ++i; - cmd.reg_info.in.address = strtoul(argv[i], NULL, 0); - - ++i; - if ((argv[i] != NULL) && (strcmp(argv[i], "num_regs")) == 0) { - cmd.reg_info.in.reg_cnt = strtoul(argv[i + 1], NULL, 0); - ++i; - } - else { - cmd.reg_info.in.reg_cnt = 1; - } - } - else { - cout << "Unknown command " << argv[i] << endl; - return 1; - } - ++i; - } - - if (!bar_valid) { - return 1; - } - - try { - device_file device; - auto ret = open_device(dev_name, device); - if (ret == false) - return 0; - - unsigned int size = (cmd.reg_info.in.reg_cnt * MAX_REG_INFO_SZ); - unsigned int out_size = sizeof(struct reg_info_out) + size; - cmd.reg_info.out = (struct reg_info_out *)new char[out_size]; - cmd.reg_info.out->ret_len = 0; - - ioctl_code = IOCTL_QDMA_REG_INFO; - - device.ioctl(ioctl_code, &cmd.reg_info.in, sizeof(cmd.reg_info.in), - cmd.reg_info.out, out_size); - - if (!cmd.reg_info.out->ret_len) { - printf("Failed to dump the registers\n"); - } - else { - char* data = (char*)&cmd.reg_info.out->pbuffer[0]; - for (i = 0; ((i < (int)cmd.reg_info.out->ret_len) && - (data[i] != '\0')); i++) { - printf("%c", data[i]); - } - } - delete[] cmd.reg_info.out; - } - catch (const std::exception& e) { - delete[] cmd.reg_info.out; - cout << "Failed to execute reg info command.\n" << e.what() << '\n'; - } - - return 0; -} - -static int handle_queue_cmds(const char *dev_name, const int argc, char* argv[]) -{ - auto i = 0; - - while (i < argc) { - if (strcmp(argv[i], "add") == 0) { - ++i; - return handle_add_queue(dev_name, argc - i, argv + i); - } - else if (strcmp(argv[i], "start") == 0) { - ++i; - return handle_start_queue(dev_name, argc - i, argv + i); - } - else if (strcmp(argv[i], "stop") == 0) { - ++i; - return handle_stop_queue(dev_name, argc - i, argv + i); - } - else if (strcmp(argv[i], "delete") == 0) { - ++i; - return handle_delete_queue(dev_name, argc - i, argv + i); - } - else if (strcmp(argv[i], "state") == 0) { - ++i; - return handle_queue_state(dev_name, argc - i, argv + i); - } - else if (strcmp(argv[i], "dump") == 0) { - ++i; - return handle_queue_dump(dev_name, argc - i, argv + i); - } - else if (strcmp(argv[i], "cmpt_read") == 0) { - ++i; - return handle_queue_cmpt_read(dev_name, argc - i, argv + i); - } - else if (strcmp(argv[i], "listall") == 0) { - ++i; - return handle_queue_listall(dev_name); - } - else { - cout << "Unknown command " << argv[i] << endl; - return 1; - } - } - - return 0; -} - -static int handle_intring_cmds(const char *dev_name, const int argc, char* argv[]) -{ - auto i = 0; - - while (i < argc) { - if (strcmp(argv[i], "dump") == 0) { - ++i; - return handle_intring_dump(dev_name, argc - i, argv + i); - } - else { - cout << "Unknown command " << argv[i] << endl; - return 1; - } - } - return 0; -} - -static int handle_reg_cmds(const char *dev_name, const int argc, char* argv[]) -{ - auto i = 0; - - while (i < argc) { - if (strcmp(argv[i], "dump") == 0) { - ++i; - return handle_reg_dump(dev_name, argc - i, argv + i); - } - else if (strcmp(argv[i], "info") == 0) { - ++i; - return handle_reg_info(dev_name, argc - i, argv + i); - } - else { - cout << "Unknown command " << argv[i] << endl; - return 1; - } - } - return 0; -} - -static int process_cli(const int argc, char* argv[]) -{ - auto i = 1; - char dev_name[DEV_NAME_MAX_SZ]; - - if (strcmp(argv[1], "dev") == 0) { - ++i; - return handle_dev_cmds(argc - i, argv + i); - } - else if (strncmp(argv[1], "qdma", 4) == 0) { - strncpy_s(dev_name, DEV_NAME_MAX_SZ, argv[1], _TRUNCATE); - ++i; - } - else if ((strcmp(argv[1], "-h") == 0) || (strcmp(argv[1], "/?") == 0)) { - help(); - return 0; - } - else if ((strcmp(argv[1], "-v") == 0) || (strcmp(argv[1], "-V") == 0)) { - printf("%s version %s\n", PROGNAME, VERSION); - printf("%s\n", COPYRIGHT); - return 0; - } - - if (strcmp(argv[i], "csr") == 0) { - ++i; - return handle_csr_cmds(dev_name, argc - i, argv + i); - } - else if (strcmp(argv[i], "devinfo") == 0) { - ++i; - return handle_devinfo(dev_name); - } - else if (strcmp(argv[i], "qmax") == 0) { - ++i; - return handle_qmax(dev_name, argc - i, argv + i); - } - else if (strcmp(argv[i], "qstats") == 0) { - ++i; - return handle_qstats(dev_name); - } - else if (strcmp(argv[i], "queue") == 0) { - ++i; - return handle_queue_cmds(dev_name, argc - i, argv + i); - } - else if (strcmp(argv[i], "intring") == 0) { - ++i; - return handle_intring_cmds(dev_name, argc - i, argv + i); - } - else if (strcmp(argv[i], "reg") == 0) { - ++i; - return handle_reg_cmds(dev_name, argc - i, argv + i); - } - else { - cout << "Unknown command " << argv[i] << endl; - return 1; - } -} - -static void help(void) -{ - cout << "usage: dma-ctl [dev | qdma] [operation]\n"; - cout << " dma-ctl -h - Prints this help\n"; - cout << " dma-ctl -v - Prints the version information\n"; - cout << "\n"; - cout << "dev [operation]\t: system wide FPGA operations\n"; - cout << " list\t: list all qdma functions\n"; - cout << "\n"; - cout << "qdma [operation]\t: per QDMA FPGA operations\n"; - cout << " \t\t: N is BBDDF where BB -> PCI Bus No, DD -> PCI Dev No, F -> PCI Fun No\n"; - cout << " csr \n"; - cout << " dump\t: Dump QDMA CSR Information\n"; - cout << " \n"; - cout << " devinfo\t: lists the Hardware and Software version and capabilities\n"; - cout << " qmax \t: Assign maximum number of queues for a device\n"; - cout << " qstats\t: Dump number of available and free queues\n"; - cout << " \n"; - cout << " queue \n"; - cout << " add mode qid [en_mm_cmpl] idx_h2c_ringsz <0:15> idx_c2h_ringsz <0:15>\n"; - cout << " [idx_c2h_timer <0:15>] [idx_c2h_th <0:15>] [idx_c2h_bufsz <0:15>] [cmptsz <0|1|2|3>] - add a queue\n"; - cout << " [trigmode ] [sw_desc_sz <3>] [desc_bypass_en] [pfch_en] [pfch_bypass_en]\n"; - cout << " [cmpl_ovf_dis]\n"; - cout << " start qid - start a single queue\n" ; - cout << " stop qid - stop a single queue\n"; - cout << " delete qid - delete a queue\n"; - cout << " state qid - print the state of the queue\n"; - cout << " dump qid dir desc - dump desc ring entries to \n"; - cout << " dump qid cmpt - dump completion ring entries to \n"; - cout << " dump qid ctx type - dump context information of \n"; - cout << " cmpt_read qid - Read the completion data\n"; - cout << " intring dump vector - interrupt ring dump for vector number \n"; - cout << " for intrrupt entries : --- \n"; - cout << " reg dump - register dump\n"; - cout << " reg info bar addr [num_regs ] - dump detailed fields information of a register\n"; -} - -int __cdecl main(const int argc, char* argv[]) -{ - try { - if (argc > 1) { - /* Pasre command line options */ - if (process_cli(argc, argv)) { - help(); - } - } - else { - help(); - } - } - catch (const std::exception& e) { - cout << "Error: " << e.what() << '\n'; - } -} diff --git a/QDMA/windows/apps/dma-ctl/dmactl.vcxproj b/QDMA/windows/apps/dma-ctl/dmactl.vcxproj deleted file mode 100644 index 7941c377b..000000000 --- a/QDMA/windows/apps/dma-ctl/dmactl.vcxproj +++ /dev/null @@ -1,146 +0,0 @@ - - - - - Debug - Win32 - - - Release - Win32 - - - Debug - x64 - - - Release - x64 - - - - - - - - - - - {620A4D4D-5D14-41BA-909B-011FF03A25FD} - {504102d4-2172-473c-8adf-cd96e308f257} - v4.5 - 12.0 - Debug - Win32 - qdma_rw - $(LatestTargetPlatformVersion) - dma-ctl - - - - Windows10 - true - WindowsApplicationForDrivers10.0 - Application - Universal - NotSet - false - - - Windows10 - false - WindowsApplicationForDrivers10.0 - Application - Universal - NotSet - false - - - Windows10 - true - WindowsApplicationForDrivers10.0 - Application - Universal - NotSet - false - - - Windows10 - false - WindowsApplicationForDrivers10.0 - Application - Universal - NotSet - false - - - - - - - - - - $(SolutionDir)build\$(Platform)\$(ConfigurationName)\bin\ - $(SolutionDir).tmp\$(Platform)\$(ConfigurationName)\$(ProjectName)\ - $(VC_LibraryPath_x64);$(WindowsSDK_LibraryPath_x64);$(NETFXKitsDir)Lib\um\x64 - false - - - $(SolutionDir)build\$(Platform)\$(ConfigurationName)\bin\ - $(SolutionDir).tmp\$(Platform)\$(ConfigurationName)\$(ProjectName)\ - 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- - - - {4FC737F1-C7A5-4376-A066-2A32D752A2FF} - cpp;c;cc;cxx;def;odl;idl;hpj;bat;asm;asmx - - - {93995380-89BD-4b04-88EB-625FBE52EBFB} - h;hpp;hxx;hm;inl;inc;xsd - - - {67DA6AB6-F800-4c08-8B7A-83BB121AAD01} - rc;ico;cur;bmp;dlg;rc2;rct;bin;rgs;gif;jpg;jpeg;jpe;resx;tiff;tif;png;wav;mfcribbon-ms - - - - - Header Files - - - Header Files - - - - - Source Files - - - \ No newline at end of file diff --git a/QDMA/windows/apps/dma-ctl/dmactl.vcxproj.user b/QDMA/windows/apps/dma-ctl/dmactl.vcxproj.user deleted file mode 100644 index be2507870..000000000 --- a/QDMA/windows/apps/dma-ctl/dmactl.vcxproj.user +++ /dev/null @@ -1,4 +0,0 @@ - - - - \ No newline at end of file diff --git a/QDMA/windows/apps/dma-ctl/version.h b/QDMA/windows/apps/dma-ctl/version.h deleted file mode 100644 index 3fc5eb80e..000000000 --- a/QDMA/windows/apps/dma-ctl/version.h +++ /dev/null @@ -1,26 +0,0 @@ -/* - * Copyright (C) 2020 Xilinx, Inc - * - * Licensed under the Apache License, Version 2.0 (the "License"). You may - * not use this file except in compliance with the License. You may obtain - * a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 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zxN2N2t{&HjYsR(W+Hsw@Zd@;}A2)~_#*N~}ag(@d+$?S$w}@NDt>V^ko49S9Gh$qIA;>q!pcxpT?o*vJLXU4PQ+3}osZagoZA1{a(#*5;`@sfCHyewWG zuZUO1tK!x1ns{xzE?ysRh&RTY;?41vcx${Z-X8CWcgDNo-SM7yZ@e$wA0LPh#)sm= z@sapwd@Md5pNLP!r{dG`nfPpcE+=s_-cGDz8>F*Z^pOc+wqh(E@k;?MDy_-p(v{vQ8`f5yM! z-|?ULZ~QMNVlt*;I%Z-v=3+h;VlkFtIR>#3tFactSdWd^jIG#?ofyS#?8SZ@#5fM) ID30U*0ZEV@;{X5v diff --git a/QDMA/windows/apps/dma-rw/datafile4K.bin b/QDMA/windows/apps/dma-rw/datafile4K.bin deleted file mode 100644 index df437f42c808d41dec5d543d60ce94c8cb8a044a..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 4096 zcmZQzWMXDvWn<^yMC+6cQE@6%&_`l#-T_m6KOcR8m$^Ra4i{)Y8_`)zddH zG%_|ZH8Z!cw6eCbwX=6{baHlab#wRd^z!!c_45x13RUz zF>}`JIdkXDU$Ah|;w4L$Enl&6)#^2C*R9{Mant54TeofBv2)k%J$v`(cmd.addr), nullptr, FILE_BEGIN)) { - throw runtime_error("SetFilePointer failed: " + std::to_string(GetLastError())); - } - if (!ReadFile(control_bar_.h, cmd.data, cmd.size, &cmd.size, NULL)) { - throw std::runtime_error("Failed to read from device! " + get_last_win_err_msg()); - } - print_bytes(cmd.addr, cmd.data, cmd.size); - break; - - case devnode_sel::user: - if (false == dgen.read(cmd.data, cmd.addr, cmd.size)) { - throw std::runtime_error("Failed to read from device! " + get_last_win_err_msg()); - } - print_bytes(cmd.addr, cmd.data, cmd.size); - break; - - case devnode_sel::queue_mm: - qopen(cmd.qid, true); - - if (INVALID_SET_FILE_POINTER == SetFilePointer(queue_.h, static_cast(cmd.addr), nullptr, FILE_BEGIN)) { - throw runtime_error("SetFilePointer failed: " + std::to_string(GetLastError())); - } - if (!ReadFile(queue_.h, cmd.data, cmd.size, &cmd.size, NULL)) { - throw std::runtime_error("Failed to read from device! " + get_last_win_err_msg()); - } - - if (TRUE == cmd.binary) - print_bytes_binary(cmd.data, cmd.size); - else - print_bytes(cmd.addr, cmd.data, cmd.size); - - qclose(); - - break; - - case devnode_sel::queue_st: - { - DWORD packet_size; - DWORD packet_cnt; - DWORD remain_size = cmd.size; - DWORD rxd_size = 0; - DWORD buf_idx = 0; - bool pkt_generate = true; - bool last_pkt_generate = true; - - qopen(cmd.qid, false); - do { - if (remain_size >= ST_C2H_MAX_PACK_SIZE_CHUNK) { - packet_cnt = remain_size / ST_C2H_MAX_PACK_SIZE_CHUNK; - packet_size = ST_C2H_MAX_PACK_SIZE_CHUNK; - } - else { - if (last_pkt_generate) { - pkt_generate = true; - last_pkt_generate = false; - } - packet_cnt = 1; - packet_size = remain_size; - } - - if (cmd.size == 0x0) { - cout << "Initiating Zero Byte Read\n"; - } - - if (pkt_generate) { - dgen.reset_pkt_ctrl(); - dgen.configure_c2h(cmd.qid + qbase, packet_size, packet_cnt); - dgen.generate_packets(); - pkt_generate = false; - } - - if (!ReadFile(queue_.h, &cmd.data[buf_idx], (packet_size * packet_cnt), &rxd_size, NULL)) { - throw std::runtime_error("Failed to read from device! " + get_last_win_err_msg()); - } - - buf_idx = buf_idx + rxd_size; - remain_size = remain_size - rxd_size; - - if (cmd.size == 0x0) { - cout << "ZERO Byte Read Successful\n"; - } - } while (remain_size); - qclose(); - - if (TRUE == cmd.binary) - print_bytes_binary(cmd.data, cmd.size); - else - print_bytes(cmd.addr, cmd.data, cmd.size); - } - - break; - - default: - return 1; - } - - if (cmd.data) _aligned_free(cmd.data); - return 0; -} - -int qdma_device::qdma_write(void ) -{ - switch (cmd.node) { - case devnode_sel::control: - if (INVALID_SET_FILE_POINTER == SetFilePointer(control_bar_.h, static_cast(cmd.addr), nullptr, FILE_BEGIN)) { - throw runtime_error("SetFilePointer failed: " + std::to_string(GetLastError())); - } - if (!WriteFile(control_bar_.h, cmd.data, cmd.size, &cmd.size, NULL)) { - throw std::runtime_error("Failed to read from device! " + get_last_win_err_msg()); - } - break; - - case devnode_sel::user: - if (false == dgen.write(cmd.data, cmd.addr, cmd.size)) { - throw std::runtime_error("Failed to read from device! " + get_last_win_err_msg()); - } - break; - - case devnode_sel::queue_mm: - qopen(cmd.qid, true); - - if (cmd.data == nullptr && false == cmd.file.empty()) { - read_file_option(); - } - - if (INVALID_SET_FILE_POINTER == SetFilePointer(queue_.h, static_cast(cmd.addr), nullptr, FILE_BEGIN)) { - throw runtime_error("SetFilePointer failed: " + std::to_string(GetLastError())); - } - if (!WriteFile(queue_.h, cmd.data, cmd.size, &cmd.size, NULL)) { - throw std::runtime_error("Failed to write to device! " + get_last_win_err_msg()); - } - - qclose(); - - break; - - case devnode_sel::queue_st: - { - qopen(cmd.qid, false); - aligned_vector wr_buffer(cmd.size); - iota(wr_buffer.begin(), wr_buffer.end(), static_cast(0)); /* 0, 1, 2, 3, 4 ... */ - dgen.reset_h2c(); - - if (cmd.size == 0x0) { - cout <<"Initiating Zero Byte Write\n"; - } - - if (!WriteFile(queue_.h, wr_buffer.data(), cmd.size, &cmd.size, NULL)) { - throw std::runtime_error("Failed to write to device! " + get_last_win_err_msg()); - } - - if (true == dgen.check_h2c(cmd.qid + qbase)) - cout << "Data generator returned SUCCESS for received data" << endl; - else - throw std::runtime_error("Data generator reported error for received data!"); - - if (cmd.size == 0x0) { - cout << "ZERO Byte Write Successful\n"; - } - - qclose(); - break; - } - default: - return 1; - } - - if (cmd.data) _aligned_free(cmd.data); - return 0; -} - -int qdma_device::qdma_interrupt(void) -{ - switch (cmd.node) { - case devnode_sel::user: - if (false == dgen.generate_user_interrupt(cmd.fun_no)) { - throw std::runtime_error("Failed to generate user interrupt from device! " + get_last_win_err_msg()); - } - break; - - default: - throw std::runtime_error("Can not generate user interrupt for wrong target! " + get_last_win_err_msg()); - } - - return 0; -} - -static int is_printable(char c) -{ - /* anything below ASCII code 32 is non-printing, 127 is DELETE */ - if (c < 32 || c == 127) { - return FALSE; - } - return TRUE; -} - -static void print_bytes_binary(BYTE* data, size_t length) -{ - FILE* output = stdout; - - if (false == cmd.file.empty()) { - fopen_s(&output, cmd.file.data(), "wb"); - } - - fwrite(data, sizeof(BYTE), length, output); - - if (false == cmd.file.empty()) { - fclose(output); - } -} - -static void print_bytes(size_t addr, BYTE* data, size_t length) -{ - FILE* output = stdout; - - if (false == cmd.file.empty()) { - fopen_s(&output, cmd.file.data(), "wb"); - } - - /* formatted output */ - for (int row = 0; row < (int)(length / 16 + ((length % 16) ? 1 : 0)); - row++) { - - /* Print address */ - fprintf(output, "0x%04zX: ", addr + row * 16); - - /* Print bytes */ - int column; - for (column = 0; column < (int)min(16, length - (row * 16)); - column++) { - fprintf(output, "%02x ", data[(row * 16) + column]); - } - for (; column < 16; column++) { - fprintf(output, " "); - } - - /* Print gutter */ - fprintf(output, " "); - - /* Print characters */ - for (column = 0; column < (int)min(16, length - (row * 16)); - column++) { - fprintf(output, "%c", is_printable(data[(row * 16) + column]) ? - (data[(row * 16) + column]) : '.'); - } - for (; column < 16; column++) { - fprintf(output, " "); - } - fprintf(output, "\n"); - } - - if (false == cmd.file.empty()) { - fclose(output); - } -} - -static int read_file_option(void) -{ - FILE* inputFile; - if (fopen_s(&inputFile, cmd.file.data(), "rb") != 0) { - fprintf(stderr, "Could not open file <%s>\n", cmd.file.data()); - return 1; - } - - /* determine file size */ - if (cmd.size == 0) { - fseek(inputFile, 0, SEEK_END); - fpos_t fpos; - fgetpos(inputFile, &fpos); - fseek(inputFile, 0, SEEK_SET); - cmd.size = (DWORD)fpos; - } - - cmd.data = allocate_buffer(cmd.size, cmd.alignment); - if (!cmd.data) { - fprintf(stderr, "Error allocating %ld bytes of memory, error code: %ld\n", cmd.size, GetLastError()); - return 1; - } - cmd.size = (DWORD)fread(cmd.data, 1, cmd.size, inputFile); - - fclose(inputFile); - return 0; -} - -static void help(void) -{ - cout << "dma-rw usage:\n"; - cout << "dma-rw -v : prints the version information\n\n"; - cout << "dma-rw qdma [OPTIONS] [DATA]\n\n"; - cout << "- qdma : unique qdma device name ( is BBDDF where BB -> PCI Bus No, DD -> PCI Dev No, F -> PCI Fun No)\n"; - cout << "- DEVNODE : One of: control | user | queue_mm_ | queue_st_*\n"; - cout << " where the * is a numeric wildcard (0 - N) for queue.\n"; - cout << "- ADDR : The target offset address of the read/write operation.\n"; - cout << " Applicable only for control, user, queue_mm device nodes.\n"; - cout << " Can be in hex or decimal.\n"; - cout << "- OPTIONS : \n"; - cout << " -a set alignment requirement for host-side buffer (default: PAGE_SIZE)\n"; - cout << " -b open file as binary\n"; - cout << " -f use contents of file as input or write output into file.\n"; - cout << " -l length of data to read/write (default: 4 bytes or whole file if '-f' flag is used)\n"; - cout << "- DATA : Space separated bytes (big endian) in decimal or hex, \n"; - cout << " e.g.: 17 34 51 68\n"; - cout << " or: 0x11 0x22 0x33 0x44\n"; -} - -static void init_cmd(void) -{ - cmd.addr = 0x0; - cmd.alignment = 0; - cmd.binary = false; - cmd.node = devnode_sel::none; - cmd.op = op_sel::none; - cmd.bus_no = 0; - cmd.dev_no = 0; - cmd.fun_no = 0; - cmd.dev_name[0] = '\0'; - cmd.qid = 0; - cmd.size = 4; - cmd.data = nullptr; -} - -static BYTE* allocate_buffer(size_t size, size_t alignment) -{ - if (size == 0) { - size = 4; - } - - if (alignment == 0) { - SYSTEM_INFO sys_info; - GetSystemInfo(&sys_info); - alignment = sys_info.dwPageSize; - } - - return (BYTE*)_aligned_malloc(size, alignment); -} - -int parse_command_line(const int argc, char* argv[]) -{ - /* - * dma-rw pf

[OPTIONS] [DATA] - * 0 1 2 3 4 5 6... n... - */ - auto argidx = 1; - - if (argc < 2) { - return 1; - } - - if ((strcmp(argv[argidx], "-v") == 0) || (strcmp(argv[argidx], "-V") == 0)) { - printf("%s version %s\n", PROGNAME, VERSION); - printf("%s\n", COPYRIGHT); - exit(0); - } - - init_cmd(); - - if (argc < 5) { - return 1; - } - - if (strncmp(argv[argidx], "qdma", 4)) { - return 1; - } - - strncpy_s(cmd.dev_name, DEV_NAME_MAX_SZ, argv[argidx], _TRUNCATE); - ++argidx; - - if (strcmp(argv[argidx], "control") == 0) { - cmd.node = devnode_sel::control; - } - else if (strcmp(argv[argidx], "user") == 0) { - cmd.node = devnode_sel::user; - - if (strcmp(argv[argidx + 1], "interrupt") == 0) { - cmd.op = op_sel::interrupt; - return 0; - } - } - else if (std::regex_match(argv[argidx], std::regex("queue_mm_[0-9]+"))) { - string qid_str{ argv[argidx] }; - auto it = std::find(qid_str.begin(), qid_str.end(), '_'); - it = it+4; - cout << *it << endl; - cmd.qid = std::stoul(string{ it, qid_str.end() }); - cmd.node = devnode_sel::queue_mm; - } - else if (std::regex_match(argv[argidx], std::regex("queue_st_[0-9]+"))) { - string qid_str{ argv[argidx] }; - auto it = std::find(qid_str.begin(), qid_str.end(), '_'); - it = it + 4; - cmd.qid = std::stoul(string{ it, qid_str.end() }); - cmd.node = devnode_sel::queue_st; - } - else { - return 1; - } - ++argidx; - - if (strcmp(argv[argidx], "read") == 0) { - cmd.op = op_sel::read; - } - else if (strcmp(argv[argidx], "write") == 0) { - cmd.op = op_sel::write; - } - else - return 1; - ++argidx; - - if (cmd.node == devnode_sel::queue_mm || cmd.node == devnode_sel::control || cmd.node == devnode_sel::user) { - cmd.addr = strtoul(argv[argidx], NULL, 0); - ++argidx; - } - else if (cmd.node == devnode_sel::queue_st) { - if (argv[argidx][0] != '-') { - return 1; - } - } - - while ((argidx < argc) && ((argv[argidx][0] == '-') || (argv[argidx][0] == '/'))) { - switch (argv[argidx][1]) { - case 'l': - argidx++; - cmd.size = strtoul(argv[argidx], NULL, 0); - argidx++; - break; - case 'f': - argidx++; - cmd.file = _strdup(argv[argidx]); - argidx++; - break; - case 'a': - argidx++; - cmd.alignment = strtoul(argv[argidx], NULL, 0); - argidx++; - break; - case 'b': - cmd.binary = TRUE; - argidx++; - break; - case '?': - case 'h': - default: - return 1; - } - } - - if (argidx != argc) { - if (cmd.op == op_sel::write && - cmd.node != devnode_sel::queue_st) { - cmd.size = argc - argidx; - cmd.data = allocate_buffer(cmd.size, cmd.alignment); - if (cmd.data == nullptr) { - cout << "Could not allocate memory for data" << endl; - exit(1); - } - - for (int byteidx = 0; argidx < argc; argidx++, byteidx++) { - cmd.data[byteidx] = (char)strtoul(argv[argidx], NULL, 0); - } - } - else - return 0; - } - - return 0; -} - -int __cdecl main(const int argc, char* argv[]) -{ - try { - if (parse_command_line(argc, argv)) { - help(); - if (cmd.data) _aligned_free(cmd.data); - exit(1); - } - - auto dev_details = get_device_details(GUID_DEVINTERFACE_QDMA); - cout << "Found " << dev_details.size() << " QDMA devices\n"; - - device_details dev_info; - auto res = get_device(dev_details, cmd.dev_name, dev_info); - if (res == false) { - printf("Device name is not valid\n"); - if (cmd.data) _aligned_free(cmd.data); - return 1; - } - - cmd.bus_no = dev_info.bus_no; - cmd.dev_no = dev_info.dev_no; - cmd.fun_no = dev_info.fun_no; - qdma_device qdev(dev_info.device_path.c_str()); - - if (cmd.qid >= qdev.get_qmax()) { - if (cmd.data) _aligned_free(cmd.data); - cout << "Invalid qid provided." << endl; - return 1; - } - - if (cmd.op == op_sel::read) { - qdev.qdma_read(); - } - else if (cmd.op == op_sel::write) { - qdev.qdma_write(); - } - else if (cmd.op == op_sel::interrupt) { - qdev.qdma_interrupt(); - } - } - catch (const std::exception& e) { - if (cmd.data) _aligned_free(cmd.data); - cout << "Error: " << e.what() << '\n'; - } -} diff --git a/QDMA/windows/apps/dma-rw/dma_rw.hpp b/QDMA/windows/apps/dma-rw/dma_rw.hpp deleted file mode 100644 index 49185d616..000000000 --- a/QDMA/windows/apps/dma-rw/dma_rw.hpp +++ /dev/null @@ -1,296 +0,0 @@ -/* - * Copyright (C) 2020 Xilinx, Inc - * - * Licensed under the Apache License, Version 2.0 (the "License"). You may - * not use this file except in compliance with the License. You may obtain - * a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - */ - -#include -#include -#include -#include -#include -#include -#include - -#include "device_file.hpp" -#include "qdma_driver_api.h" - -#pragma comment(lib, "setupapi.lib") - -using std::uint32_t; -using std::string; -using std::runtime_error; -using std::cout; -using namespace std; - -#define ST_C2H_MAX_PACK_SIZE_CHUNK 4096 - -/* ----- common functions ----- */ -static constexpr uint32_t bit(uint64_t n) { - return (1ull << n); -} - -static constexpr bool is_bit_set(uint64_t x, uint64_t n) { - return (x & bit(n)) == bit(n); -} - -static constexpr uint64_t create_mask(uint64_t n, uint64_t l) { - return ((1ull << l) - 1ull) << n; -} - -static constexpr uint32_t get_bits(uint32_t value, uint32_t bit_index, uint32_t len) { - return ((value & create_mask(bit_index, len)) >> bit_index); -} -/* ----- ----- */ - -enum class devnode_sel { - control, - user, - queue_mm, - queue_st, - none -}; - -enum class op_sel { - read, - write, - interrupt, - none -}; - -struct cli_cmd { - op_sel op; - UINT8 bus_no; - UINT8 dev_no; - UINT8 fun_no; - char dev_name[DEV_NAME_MAX_SZ]; - devnode_sel node; - BYTE *data; - LONG addr; - ULONG qid; - DWORD size; - string file; - size_t alignment; - BOOL binary; -}; - -template -struct aligned_allocator { - - typedef T value_type; - - aligned_allocator() noexcept {} - - template - aligned_allocator(const aligned_allocator&) noexcept {} - - template - bool operator==(const aligned_allocator&) const noexcept - { - return true; - } - template - bool operator!=(const aligned_allocator&) const noexcept - { - return false; - } - - T* allocate(const std::size_t num) { - if (num == 0) { - return nullptr; - } - - void* const ptr = _aligned_malloc(num * sizeof(T), Alignment); - if (ptr == nullptr) { - throw std::bad_alloc(); - } - return static_cast(ptr); - } - void deallocate(T* const p, std::size_t) { - if (p) { - _aligned_free(p); - } - } - - template - struct rebind { - typedef aligned_allocator other; - }; -}; - -template -using aligned_vector = std::vector>; - -template -void fill_pattern(Iter begin, Iter end) { - std::iota(begin, end, 0); // 0, 1, 2, 3, 4 ... -} - -class data_generator { -public: - using value_type = uint16_t; - - explicit data_generator(const std::string& dev_path) - { - user_bar.open(dev_path + "\\user", GENERIC_WRITE | GENERIC_READ); - } - - ~data_generator() - { - user_bar.close(); - } - - bool check_h2c(const uint32_t qid) - { - const auto match_reg = user_bar.read(0x10); - const auto match_qid = get_bits(match_reg, 4, 28); /* bits 4-31 = qid */ - return (match_qid == qid) && is_bit_set(match_reg, 0); /* bit 0 = match */ - } - - void reset_h2c() - { - user_bar.write(0xC, 0x1); - } - - void reset_pkt_ctrl() - { - user_bar.write(0x8, 0x0); - } - - void set_queue(const uint32_t qid) - { - user_bar.write(0x0, qid); - } - - void configure_c2h(const uint32_t qid, const uint32_t packet_size, const uint32_t num_packets) - { - printf("DGEN : PKT SIZE : %d, PKT CNT : %d\n", packet_size, num_packets); - set_queue(qid); - user_bar.write(0x4, packet_size); - user_bar.write(0x20, num_packets); - } - - void generate_packets() - { - user_bar.write(0x8, 0x2); - } - - BOOL read(void *buff, LONG addr, DWORD size) - { - if (INVALID_SET_FILE_POINTER == SetFilePointer(user_bar.h, static_cast(addr), nullptr, FILE_BEGIN)) { - return FALSE; - } - - return ReadFile(user_bar.h, buff, size, &size, NULL); - } - - BOOL write(void *buff, LONG addr, DWORD size) - { - if (INVALID_SET_FILE_POINTER == SetFilePointer(user_bar.h, static_cast(addr), nullptr, FILE_BEGIN)) { - return FALSE; - } - - return WriteFile(user_bar.h, buff, size, &size, NULL); - } - - BOOL generate_user_interrupt(UINT32 fun_id) - { - UINT32 val = 0x0; - - val = 0x00; - user_bar.write(0x98, val); - - user_bar.write(0x9C, val); - - val = 0x0; - val = fun_id << 12; - val |= 0x1; - if (fun_id == 0) - val |= (1u << 4); - user_bar.write(0x94, val); - - return TRUE; - } - -private: - device_file user_bar; -}; - -class qdma_device { -public: - explicit qdma_device(const char* device_path) : dgen(device_path) - { - using namespace std::string_literals; - dev_path = device_path; - control_bar_.open(dev_path + "\\control"s, GENERIC_READ | GENERIC_WRITE); - mgmt.open(dev_path + "\\mgmt"s, GENERIC_READ | GENERIC_WRITE); - get_qstats(); - } - - ~qdma_device() - { - control_bar_.close(); - mgmt.close(); - } - - void get_qstats(void) - { - struct qstat_out qstats_info = { 0 }; - try { - mgmt.ioctl(IOCTL_QDMA_GET_QSTATS, NULL, 0, &qstats_info, sizeof(qstats_info)); - qbase = qstats_info.qbase; - qmax = qstats_info.qmax; - } - catch (const std::exception& e) { - cout << "IOCTL Failed for qstats " << e.what() << '\n'; - } - } - - unsigned int get_qmax() - { - return qmax; - } - - int qopen(ULONG qid, bool is_mm) - { - if (true == is_mm) - queue_.open(dev_path + "\\queue_"s + to_string(qid), GENERIC_READ | GENERIC_WRITE); - else - queue_.open(dev_path + "\\st_"s + to_string(qid), GENERIC_READ | GENERIC_WRITE); - - return 0; - } - - void qclose(void) - { - queue_.close(); - } - - int qdma_read(); - int qdma_write(); - int qdma_interrupt(void); - -private: - const char* dev_path; - device_file control_bar_; - data_generator dgen; - device_file queue_; - device_file mgmt; - unsigned int qbase; - unsigned int qmax; -}; - -static BYTE* allocate_buffer(size_t size, size_t alignment); -static void print_bytes(size_t addr, BYTE* data, size_t length); -static int read_file_option(void); -static void print_bytes_binary(BYTE* data, size_t length); \ No newline at end of file diff --git a/QDMA/windows/apps/dma-rw/dma_rw.vcxproj b/QDMA/windows/apps/dma-rw/dma_rw.vcxproj deleted file mode 100644 index 79419dac3..000000000 --- a/QDMA/windows/apps/dma-rw/dma_rw.vcxproj +++ /dev/null @@ -1,146 +0,0 @@ - - - - - Debug - Win32 - - - Release - Win32 - - - Debug - x64 - - - Release - x64 - - - - - - - - - - - {F7C376CA-92F6-4484-B737-8670222CE79F} - {504102d4-2172-473c-8adf-cd96e308f257} - v4.5 - 12.0 - Debug - Win32 - qdma_rw - $(LatestTargetPlatformVersion) - dma-rw - - - - Windows10 - true - WindowsApplicationForDrivers10.0 - Application - Universal - NotSet - false - - - Windows10 - false - WindowsApplicationForDrivers10.0 - Application - Universal - NotSet - false - - - Windows10 - true - WindowsApplicationForDrivers10.0 - Application - Universal - NotSet - false - - - Windows10 - false - WindowsApplicationForDrivers10.0 - Application - Universal - NotSet - false - - - - - - - - - - $(SolutionDir)build\$(Platform)\$(ConfigurationName)\bin\ - $(SolutionDir).tmp\$(Platform)\$(ConfigurationName)\$(ProjectName)\ - $(VC_LibraryPath_x64);$(WindowsSDK_LibraryPath_x64);$(NETFXKitsDir)Lib\um\x64 - false - - - $(SolutionDir)build\$(Platform)\$(ConfigurationName)\bin\ - $(SolutionDir).tmp\$(Platform)\$(ConfigurationName)\$(ProjectName)\ - false - - - $(SolutionDir)build\$(Platform)\$(ConfigurationName)\bin\ - $(SolutionDir).tmp\$(Platform)\$(ConfigurationName)\$(ProjectName)\ - false - - - $(SolutionDir).tmp\$(Platform)\$(ConfigurationName)\$(ProjectName)\ - $(SolutionDir)build\$(Platform)\$(ConfigurationName)\bin\ - false - - - - _DEBUG;WINAPI_FAMILY=WINAPI_FAMILY_DESKTOP_APP;WINAPI_PARTITION_DESKTOP=1;WINAPI_PARTITION_SYSTEM=1;WINAPI_PARTITION_APP=1;WINAPI_PARTITION_PC_APP=1;%(PreprocessorDefinitions) - MultiThreadedDebugDLL - $(SolutionDir)\apps\common\include;$(SolutionDir)\sys\drv\include;$(SolutionDir)\sys\libqdma\include;%(AdditionalIncludeDirectories) - - - %(AdditionalDependencies);onecoreuap.lib - - - - - WINAPI_FAMILY=WINAPI_FAMILY_DESKTOP_APP;WINAPI_PARTITION_DESKTOP=1;WINAPI_PARTITION_SYSTEM=1;WINAPI_PARTITION_APP=1;WINAPI_PARTITION_PC_APP=1;%(PreprocessorDefinitions) - $(SolutionDir)\sys\libqdma\include;$(SolutionDir)\sys\drv\include;$(SolutionDir)\apps\common\include;%(AdditionalIncludeDirectories) - - - %(AdditionalDependencies);onecoreuap.lib - - - - - _WIN64;_AMD64_;AMD64;%(PreprocessorDefinitions) - MultiThreadedDebug - $(SolutionDir)\sys\drv\include;$(SolutionDir)\sys\libqdma\include;$(SolutionDir)\apps\common\include;%(AdditionalIncludeDirectories) - - - kernel32.lib;user32.lib;gdi32.lib;winspool.lib;comdlg32.lib;advapi32.lib;shell32.lib;ole32.lib;oleaut32.lib;uuid.lib;odbc32.lib;odbccp32.lib;%(AdditionalDependencies) - - - - - - WINAPI_FAMILY=WINAPI_FAMILY_DESKTOP_APP;WINAPI_PARTITION_DESKTOP=1;WINAPI_PARTITION_SYSTEM=1;WINAPI_PARTITION_APP=1;WINAPI_PARTITION_PC_APP=1;%(PreprocessorDefinitions) - $(SolutionDir)\apps\common\include;$(SolutionDir)\sys\drv\include;$(SolutionDir)\sys\libqdma\include;%(AdditionalIncludeDirectories) - - - %(AdditionalDependencies);onecoreuap.lib - - - - - - \ No newline at end of file diff --git a/QDMA/windows/apps/dma-rw/dma_rw.vcxproj.filters b/QDMA/windows/apps/dma-rw/dma_rw.vcxproj.filters deleted file mode 100644 index 090c753cb..000000000 --- a/QDMA/windows/apps/dma-rw/dma_rw.vcxproj.filters +++ /dev/null @@ -1,30 +0,0 @@ - - - - - {4FC737F1-C7A5-4376-A066-2A32D752A2FF} - cpp;c;cc;cxx;def;odl;idl;hpj;bat;asm;asmx - - - {93995380-89BD-4b04-88EB-625FBE52EBFB} - h;hpp;hxx;hm;inl;inc;xsd - - - {67DA6AB6-F800-4c08-8B7A-83BB121AAD01} - rc;ico;cur;bmp;dlg;rc2;rct;bin;rgs;gif;jpg;jpeg;jpe;resx;tiff;tif;png;wav;mfcribbon-ms - - - - - Header Files - - - Header Files - - - - - Source Files - - - \ No newline at end of file diff --git a/QDMA/windows/apps/dma-rw/dma_rw.vcxproj.user b/QDMA/windows/apps/dma-rw/dma_rw.vcxproj.user deleted file mode 100644 index be2507870..000000000 --- a/QDMA/windows/apps/dma-rw/dma_rw.vcxproj.user +++ /dev/null @@ -1,4 +0,0 @@ - - - - \ No newline at end of file diff --git a/QDMA/windows/apps/dma-rw/version.h b/QDMA/windows/apps/dma-rw/version.h deleted file mode 100644 index adae31641..000000000 --- a/QDMA/windows/apps/dma-rw/version.h +++ /dev/null @@ -1,26 +0,0 @@ -/* - * Copyright (C) 2020 Xilinx, Inc - * - * Licensed under the Apache License, Version 2.0 (the "License"). You may - * not use this file except in compliance with the License. You may obtain - * a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - */ - -#pragma once - -#ifndef __QDMARW_VERSION_H -#define __QDMARW_VERSION_H - -#define PROGNAME "dma-rw" -#define VERSION "2020.2.0" -#define COPYRIGHT "Copyright (c) 2020 Xilinx Inc." - -#endif /*__QDMARW_VERSION_H*/ diff --git a/QDMA/windows/sys/drv/include/qdma_driver_api.h b/QDMA/windows/sys/drv/include/qdma_driver_api.h deleted file mode 100644 index e4d12cf0b..000000000 --- a/QDMA/windows/sys/drv/include/qdma_driver_api.h +++ /dev/null @@ -1,434 +0,0 @@ -/* - * Copyright (C) 2020 Xilinx, Inc - * - * Licensed under the Apache License, Version 2.0 (the "License"). You may - * not use this file except in compliance with the License. You may obtain - * a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - */ - -#ifndef QDMA_DRIVER_API_H_ -#define QDMA_DRIVER_API_H_ - -#ifdef __cplusplus -extern "C" { -#endif - -#include -#include - -/** - * Define an Interface Guid so that app can find the device and talk to it. - */ -#include - -typedef int BOOL; - -#ifdef DEFINE_GUID -DEFINE_GUID (GUID_DEVINTERFACE_QDMA, - 0x80f90fa8,0x0cea,0x43c5,0x81,0xce,0x4b,0xf9,0x4a,0xa1,0x4c,0x72); -/** {80f90fa8-0cea-43c5-81ce-4bf94aa14c72} */ -#endif - -/** Interface File Names exposed by driver */ -#define QDMA_FILE_USER L"\\user" -#define QDMA_FILE_CONTROL L"\\control" -#define QDMA_FILE_BYPASS L"\\bypass" -#define QDMA_FILE_DMA_QUEUE L"\\queue_" -#define QDMA_FILE_DMA_ST_QUEUE L"\\st_" -#define QDMA_FILE_DMA_MGMT L"\\mgmt" - -#define QDMA_CSR_SZ 16U -#define QDMA_MAX_UDD_DATA_LEN 64U -#define QDMA_VERSION_INFO_LENGTH 32U - -/** Queue Direction */ -enum queue_direction { - QUEUE_DIR_H2C = 0, - QUEUE_DIR_C2H -}; - -/** Descriptor Type */ -enum descriptor_type { - RING_DESC = 0, - CMPT_DESC -}; - -/** Completion descriptor size */ -enum cmpt_desc_sz { - CMPT_DESC_SZ_8B = 0, - CMPT_DESC_SZ_16B, - CMPT_DESC_SZ_32B, - CMPT_DESC_SZ_64B, - CMPT_DESC_SZ_MAX -}; - -/** Trigger mode (to be used for ST Queues) */ -enum trig_mode { - TRIG_MODE_DISABLE = 0, - TRIG_MODE_EVERY, - TRIG_MODE_USER_COUNT, - TRIG_MODE_USER, - TRIG_MODE_USER_TIMER, - TRIG_MODE_USER_TIMER_COUNT, - TRIG_MODE_MAX -}; - -enum ring_type { - RING_TYPE_H2C = 0, - RING_TYPE_C2H, - RING_TYPE_CMPT -}; - -/** Device IOCTL Commands */ -enum commands { - CMD_CSR_DUMP, - CMD_DEVINFO, - CMD_QUEUE_ADD, - CMD_QUEUE_START, - CMD_QUEUE_STOP, - CMD_QUEUE_DELETE, - CMD_QUEUE_DUMP_STATE, - CMD_QUEUE_READ_UDD, - CMD_QUEUE_DUMP_DESC, - CMD_QUEUE_DUMP_CTX, - CMD_QUEUE_CMPT_READ, - CMD_INTRING_DUMP, - CMD_REG_DUMP, - CMD_QUEUE_NO_COPY, - CMD_SET_QMAX, - CMD_GET_QSTATS, - CMD_REG_INFO, - CMD_OP_MAX -}; - -/** Structure which holds the CSR registers information - * IOCTL Command : - * IOCTL_QDMA_CSR_DUMP - */ -struct csr_conf_out{ - UINT32 ring_sz[QDMA_CSR_SZ]; - UINT32 c2h_timer_cnt[QDMA_CSR_SZ]; - UINT32 c2h_th_cnt[QDMA_CSR_SZ]; - UINT32 c2h_buff_sz[QDMA_CSR_SZ]; - UINT32 wb_interval; -}; - -/** Structure which holds the Queue configuration parameters - * Valid IOCTL Commands: - * IOCTL_QDMA_QUEUE_ADD - * IOCTL_QDMA_QUEUE_START - * IOCTL_QDMA_QUEUE_STOP - * IOCTL_QDMA_QUEUE_DELETE - */ -struct queue_conf_in { - UINT16 qid; - BOOL is_st; - UINT8 h2c_ring_sz_index; - UINT8 c2h_ring_sz_index; - UINT8 c2h_buff_sz_index; - UINT8 c2h_th_cnt_index; - UINT8 c2h_timer_cnt_index; - enum cmpt_desc_sz compl_sz; - enum trig_mode trig_mode; - UINT8 sw_desc_sz; - BOOL desc_bypass_en; - BOOL pfch_en; - BOOL pfch_bypass_en; - BOOL cmpl_ovf_dis; - BOOL en_mm_cmpl; -}; - -/** Structure to be passed as input parameter for - * IOCTL Command : - * IOCTL_QDMA_QUEUE_DUMP_STATE - */ -struct queue_state_in { - UINT16 qid; -}; - -/** Structure to be passed as output parameter for - * IOCTL Command : - * IOCTL_QDMA_QUEUE_DUMP_STATE - */ -struct queue_state_out { - char state[20]; -}; - -/** Structure to be passed as output parameter for - * IOCTL Command : - * IOCTL_QDMA_DEVINFO -*/ -struct device_info_out { - struct version_info { - char qdma_rtl_version_str[QDMA_VERSION_INFO_LENGTH]; - char qdma_vivado_release_id_str[QDMA_VERSION_INFO_LENGTH]; - char qdma_device_type_str[QDMA_VERSION_INFO_LENGTH]; - char qdma_versal_ip_type_str[QDMA_VERSION_INFO_LENGTH]; - char qdma_sw_version[QDMA_VERSION_INFO_LENGTH]; - }ver_info; - UINT32 num_pfs; - UINT32 num_qs; - BOOL flr_present; - BOOL st_en; - BOOL mm_en; - BOOL mm_cmpl_en; - BOOL mailbox_en; - BOOL debug_mode; - UINT8 desc_eng_mode; - UINT32 num_mm_channels; -}; - -/** Structure to be passed as input parameter for - * IOCTL Command : - * IOCTL_QDMA_QUEUE_READ_UDD -*/ -struct cmpt_udd_info_in { - UINT16 qid; -}; - -/** Structure to be passed as output parameter for - * IOCTL Command : - * IOCTL_QDMA_QUEUE_READ_UDD -*/ -struct cmpt_udd_info_out { - UINT64 length; - UINT8 buffer[QDMA_MAX_UDD_DATA_LEN]; -}; - -/** Structure to be passed as input parameter for - * IOCTL Command : - * IOCTL_QDMA_QUEUE_DUMP_DESC -*/ -struct desc_dump_info_in { - UINT16 qid; - enum queue_direction dir; - enum descriptor_type desc_type; - UINT32 desc_start; - UINT32 desc_end; -}; - -/** Structure to be passed as output parameter for - * IOCTL Command : - * IOCTL_QDMA_QUEUE_DUMP_DESC -*/ -struct desc_dump_info_out { - size_t desc_sz; - size_t data_sz; - UINT8 pbuffer[1]; -}; - -/** Structure to be passed as input parameter for - * IOCTL Command : - * IOCTL_QDMA_QUEUE_DUMP_CTX -*/ -struct ctx_dump_info_in { - UINT16 qid; - enum ring_type type; -}; - -/** Structure to be passed as output parameter for - * IOCTL Command : - * IOCTL_QDMA_QUEUE_DUMP_CTX -*/ -struct ctx_dump_info_out { - size_t ret_sz; - char pbuffer[1]; -}; - -/** Structure to be passed as input parameter for - * IOCTL Command : - * IOCTL_QDMA_QUEUE_CMPT_READ -*/ -struct cmpt_data_info_in { - UINT16 qid; -}; - -/** Structure to be passed as output parameter for - * IOCTL Command : - * IOCTL_QDMA_QUEUE_CMPT_READ -*/ -struct cmpt_data_info_out { - size_t ret_len; - size_t cmpt_desc_sz; - UINT8 pbuffer[1]; -}; - -/** Structure to be passed as input parameter for - * IOCTL Command : - * IOCTL_QDMA_INTRING_DUMP - */ -struct intring_info_in { - UINT32 vec_id; - UINT32 start_idx; - UINT32 end_idx; -}; - -/** Structure to be passed as input parameter for - * IOCTL Command : - * IOCTL_QDMA_SET_QMAX - */ -struct qmax_in { - UINT32 qmax; -}; - -/** Structure to be passed as output parameter for - * IOCTL Command : - * IOCTL_QDMA_INTRING_DUMP - */ -struct intring_info_out { - size_t ret_len; - size_t ring_entry_sz; - UINT8 pbuffer[1]; -}; - -/** Structure to be passed as output parameter for - * IOCTL Command : - * IOCTL_QDMA_REG_DUMP - */ -struct regdump_info_out { - size_t ret_len; - char pbuffer[1]; -}; - -/** Structure to be passed as output parameter for - * IOCTL Command : - * IOCTL_QDMA_GET_QSTATS - */ -struct qstat_out { - UINT32 qbase; - UINT32 qmax; - UINT32 active_h2c_queues; - UINT32 active_c2h_queues; - UINT32 active_cmpt_queues; -}; - -/** Structure to be passed as input parameter for - * IOCTL Command : - * IOCTL_QDMA_REG_INFO - */ -struct reg_info_in { - UINT32 bar_no; - UINT32 address; - UINT32 reg_cnt; -}; - -/** Structure to be passed as output parameter for - * IOCTL Command : - * IOCTL_QDMA_REG_INFO - */ -struct reg_info_out { - size_t ret_len; - char pbuffer[1]; -}; - -struct csr_conf_data { - struct csr_conf_out *out; -}; - -struct queue_conf { - struct queue_conf_in in; -}; - -struct queue_active_state { - struct queue_state_in in; - struct queue_state_out *out; -}; - -struct device_info { - struct device_info_out *out; -}; - -struct cmpt_udd_info { - struct cmpt_udd_info_in in; - struct cmpt_udd_info_out *out; -}; - -struct desc_dump_info { - struct desc_dump_info_in in; - struct desc_dump_info_out *out; -}; - -struct ctx_dump_info { - struct ctx_dump_info_in in; - struct ctx_dump_info_out *out; -}; - -struct cmpt_data_info { - struct cmpt_data_info_in in; - struct cmpt_data_info_out *out; -}; - -struct intring_info { - struct intring_info_in in; - struct intring_info_out *out; -}; - -struct regdump_info { - struct regdump_info_out *out; -}; - -struct qmax_info { - struct qmax_in in; -}; - -struct qstats_info { - struct qstat_out *out; -}; - -struct reg_info { - struct reg_info_in in; - struct reg_info_out* out; -}; - -/** Union that consolidates parameters for all ioctl commands */ -union ioctl_cmd { - struct csr_conf_data csr; - struct queue_conf q_conf; - struct queue_active_state q_state; - struct device_info dev_info; - struct cmpt_udd_info udd_info; - struct desc_dump_info desc_info; - struct ctx_dump_info ctx_info; - struct cmpt_data_info cmpt_info; - struct intring_info int_ring_info; - struct regdump_info reg_dump_info; - struct qmax_info qmax_info; - struct qstats_info qstats_info; - struct reg_info reg_info; -}; - -#define QDMA_IOCTL(index) CTL_CODE(FILE_DEVICE_UNKNOWN, index, METHOD_BUFFERED, FILE_ANY_ACCESS) - -#define IOCTL_QDMA_CSR_DUMP QDMA_IOCTL(CMD_CSR_DUMP) -#define IOCTL_QDMA_DEVINFO QDMA_IOCTL(CMD_DEVINFO) -#define IOCTL_QDMA_QUEUE_ADD QDMA_IOCTL(CMD_QUEUE_ADD) -#define IOCTL_QDMA_QUEUE_START QDMA_IOCTL(CMD_QUEUE_START) -#define IOCTL_QDMA_QUEUE_STOP QDMA_IOCTL(CMD_QUEUE_STOP) -#define IOCTL_QDMA_QUEUE_DELETE QDMA_IOCTL(CMD_QUEUE_DELETE) -#define IOCTL_QDMA_QUEUE_DUMP_STATE QDMA_IOCTL(CMD_QUEUE_DUMP_STATE) -#define IOCTL_QDMA_QUEUE_READ_UDD QDMA_IOCTL(CMD_QUEUE_READ_UDD) -#define IOCTL_QDMA_QUEUE_DUMP_DESC QDMA_IOCTL(CMD_QUEUE_DUMP_DESC) -#define IOCTL_QDMA_QUEUE_DUMP_CTX QDMA_IOCTL(CMD_QUEUE_DUMP_CTX) -#define IOCTL_QDMA_QUEUE_CMPT_READ QDMA_IOCTL(CMD_QUEUE_CMPT_READ) -#define IOCTL_QDMA_INTRING_DUMP QDMA_IOCTL(CMD_INTRING_DUMP) -#define IOCTL_QDMA_REG_DUMP QDMA_IOCTL(CMD_REG_DUMP) -#define IOCTL_QDMA_QUEUE_NO_COPY QDMA_IOCTL(CMD_QUEUE_NO_COPY) -#define IOCTL_QDMA_SET_QMAX QDMA_IOCTL(CMD_SET_QMAX) -#define IOCTL_QDMA_GET_QSTATS QDMA_IOCTL(CMD_GET_QSTATS) -#define IOCTL_QDMA_REG_INFO QDMA_IOCTL(CMD_REG_INFO) - -#include - -#ifdef __cplusplus -} -#endif - -#endif /* QDMA_DRIVER_API_H_ */ diff --git a/QDMA/windows/sys/drv/qdma.inf b/QDMA/windows/sys/drv/qdma.inf deleted file mode 100644 index a7b5ac11a..000000000 --- a/QDMA/windows/sys/drv/qdma.inf +++ /dev/null @@ -1,325 +0,0 @@ -; -; Copyright (C) 2020 Xilinx, Inc -; -; Licensed under the Apache License, Version 2.0 (the "License"). You may -; not use this file except in compliance with the License. You may obtain -; a copy of the License at -; -; http://www.apache.org/licenses/LICENSE-2.0 -; -; Unless required by applicable law or agreed to in writing, software -; distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -; WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -; License for the specific language governing permissions and limitations -; under the License. - -; -; QDMA.inf -; - -[Version] -Signature = "$WINDOWS NT$" -Class = %ClassName% -ClassGuid = {a3a4c1ce-5a80-452c-9b51-a98edd3378d1} -Provider = %ManufacturerName% -CatalogFile = QDMA.cat -DriverVer = 10/15/2020, 2020.2.0.0 ;Format : year.quarter_no.drv_ver.libqdma_ver -DriverPackageType = PlugAndPlay - -[DestinationDirs] -DefaultDestDir = 12 -QDMA_Device_CoInstaller_CopyFiles = 11 - -; ================= Class section ============================================= - -[ClassInstall32] -Addreg=SampleClassReg - -[SampleClassReg] -HKR,,,0,%ClassName% -HKR,,Icon,,-5 - -[SourceDisksNames] -1 = %DiskName%,,,"" - -[SourceDisksFiles] -QDMA.sys = 1,, -WdfCoInstaller$KMDFCOINSTALLERVERSION$.dll=1 ; make sure the number matches with SourceDisksNames - -; ================= Install Section =========================================== - -[Manufacturer] -%ManufacturerName%=Standard,NT$ARCH$ - -[Standard.NT$ARCH$] -; DisplayName Section DeviceId -; ----------- ------- -------- -; GEN 1 -; PCIe lane width x1 -%QDMA.DeviceDesc%= QDMA_Device, PCI\VEN_10ee&DEV_9011 ; PF 0 -%QDMA.DeviceDesc%= QDMA_Device, PCI\VEN_10ee&DEV_9111 ; PF 1 -%QDMA.DeviceDesc%= QDMA_Device, PCI\VEN_10ee&DEV_9211 ; PF 2 -%QDMA.DeviceDesc%= QDMA_Device, PCI\VEN_10ee&DEV_9311 ; PF 3 -; PCIe lane width x2 -%QDMA.DeviceDesc%= QDMA_Device, PCI\VEN_10ee&DEV_9012 ; PF 0 -%QDMA.DeviceDesc%= QDMA_Device, PCI\VEN_10ee&DEV_9112 ; PF 1 -%QDMA.DeviceDesc%= QDMA_Device, PCI\VEN_10ee&DEV_9212 ; PF 2 -%QDMA.DeviceDesc%= QDMA_Device, PCI\VEN_10ee&DEV_9312 ; PF 3 -; PCIe lane width x4 -%QDMA.DeviceDesc%= QDMA_Device, PCI\VEN_10ee&DEV_9014 ; PF 0 -%QDMA.DeviceDesc%= QDMA_Device, PCI\VEN_10ee&DEV_9114 ; PF 1 -%QDMA.DeviceDesc%= QDMA_Device, PCI\VEN_10ee&DEV_9214 ; PF 2 -%QDMA.DeviceDesc%= QDMA_Device, PCI\VEN_10ee&DEV_9314 ; PF 3 -; PCIe lane width x8 -%QDMA.DeviceDesc%= QDMA_Device, PCI\VEN_10ee&DEV_9018 ; PF 0 -%QDMA.DeviceDesc%= QDMA_Device, PCI\VEN_10ee&DEV_9118 ; PF 1 -%QDMA.DeviceDesc%= QDMA_Device, PCI\VEN_10ee&DEV_9218 ; PF 2 -%QDMA.DeviceDesc%= QDMA_Device, PCI\VEN_10ee&DEV_9318 ; PF 3 -; PCIe lane width x16 -%QDMA.DeviceDesc%= QDMA_Device, PCI\VEN_10ee&DEV_901f ; PF 0 -%QDMA.DeviceDesc%= QDMA_Device, PCI\VEN_10ee&DEV_911f ; PF 1 -%QDMA.DeviceDesc%= QDMA_Device, PCI\VEN_10ee&DEV_921f ; PF 2 -%QDMA.DeviceDesc%= QDMA_Device, PCI\VEN_10ee&DEV_931f ; PF 3 - -; GEN 2 -; PCIe lane width x1 -%QDMA.DeviceDesc%= QDMA_Device, PCI\VEN_10ee&DEV_9021 ; PF 0 -%QDMA.DeviceDesc%= QDMA_Device, PCI\VEN_10ee&DEV_9121 ; PF 1 -%QDMA.DeviceDesc%= QDMA_Device, PCI\VEN_10ee&DEV_9221 ; PF 2 -%QDMA.DeviceDesc%= QDMA_Device, PCI\VEN_10ee&DEV_9321 ; PF 3 -; PCIe lane width x2 -%QDMA.DeviceDesc%= QDMA_Device, PCI\VEN_10ee&DEV_9022 ; PF 0 -%QDMA.DeviceDesc%= QDMA_Device, PCI\VEN_10ee&DEV_9122 ; PF 1 -%QDMA.DeviceDesc%= QDMA_Device, PCI\VEN_10ee&DEV_9222 ; PF 2 -%QDMA.DeviceDesc%= QDMA_Device, PCI\VEN_10ee&DEV_9322 ; PF 3 -; PCIe lane width x4 -%QDMA.DeviceDesc%= QDMA_Device, PCI\VEN_10ee&DEV_9024 ; PF 0 -%QDMA.DeviceDesc%= QDMA_Device, PCI\VEN_10ee&DEV_9124 ; PF 1 -%QDMA.DeviceDesc%= QDMA_Device, PCI\VEN_10ee&DEV_9224 ; PF 2 -%QDMA.DeviceDesc%= QDMA_Device, PCI\VEN_10ee&DEV_9324 ; PF 3 -; PCIe lane width x8 -%QDMA.DeviceDesc%= QDMA_Device, PCI\VEN_10ee&DEV_9028 ; PF 0 -%QDMA.DeviceDesc%= QDMA_Device, PCI\VEN_10ee&DEV_9128 ; PF 1 -%QDMA.DeviceDesc%= QDMA_Device, PCI\VEN_10ee&DEV_9228 ; PF 2 -%QDMA.DeviceDesc%= QDMA_Device, PCI\VEN_10ee&DEV_9328 ; PF 3 -; PCIe lane width x16 -%QDMA.DeviceDesc%= QDMA_Device, PCI\VEN_10ee&DEV_902f ; PF 0 -%QDMA.DeviceDesc%= QDMA_Device, PCI\VEN_10ee&DEV_912f ; PF 1 -%QDMA.DeviceDesc%= QDMA_Device, PCI\VEN_10ee&DEV_922f ; PF 2 -%QDMA.DeviceDesc%= QDMA_Device, PCI\VEN_10ee&DEV_932f ; PF 3 - -; GEN 3 -; PCIe lane width x1 -%QDMA.DeviceDesc%= QDMA_Device, PCI\VEN_10ee&DEV_9031 ; PF 0 -%QDMA.DeviceDesc%= QDMA_Device, PCI\VEN_10ee&DEV_9131 ; PF 1 -%QDMA.DeviceDesc%= QDMA_Device, PCI\VEN_10ee&DEV_9231 ; PF 2 -%QDMA.DeviceDesc%= QDMA_Device, PCI\VEN_10ee&DEV_9331 ; PF 3 -; PCIe lane width x2 -%QDMA.DeviceDesc%= QDMA_Device, PCI\VEN_10ee&DEV_9032 ; PF 0 -%QDMA.DeviceDesc%= QDMA_Device, PCI\VEN_10ee&DEV_9132 ; PF 1 -%QDMA.DeviceDesc%= QDMA_Device, PCI\VEN_10ee&DEV_9232 ; PF 2 -%QDMA.DeviceDesc%= QDMA_Device, PCI\VEN_10ee&DEV_9332 ; PF 3 -; PCIe lane width x4 -%QDMA.DeviceDesc%= QDMA_Device, PCI\VEN_10ee&DEV_9034 ; PF 0 -%QDMA.DeviceDesc%= QDMA_Device, PCI\VEN_10ee&DEV_9134 ; PF 1 -%QDMA.DeviceDesc%= QDMA_Device, PCI\VEN_10ee&DEV_9234 ; PF 2 -%QDMA.DeviceDesc%= QDMA_Device, PCI\VEN_10ee&DEV_9334 ; PF 3 -; PCIe lane width x8 -%QDMA.DeviceDesc%= QDMA_Device, PCI\VEN_10ee&DEV_9038 ; PF 0 -%QDMA.DeviceDesc%= QDMA_Device, PCI\VEN_10ee&DEV_9138 ; PF 1 -%QDMA.DeviceDesc%= QDMA_Device, PCI\VEN_10ee&DEV_9238 ; PF 2 -%QDMA.DeviceDesc%= QDMA_Device, PCI\VEN_10ee&DEV_9338 ; PF 3 -; PCIe lane width x16 -%QDMA.DeviceDesc%= QDMA_Device, PCI\VEN_10ee&DEV_903f ; PF 0 -%QDMA.DeviceDesc%= QDMA_Device, PCI\VEN_10ee&DEV_913f ; PF 1 -%QDMA.DeviceDesc%= QDMA_Device, PCI\VEN_10ee&DEV_923f ; PF 2 -%QDMA.DeviceDesc%= QDMA_Device, PCI\VEN_10ee&DEV_933f ; PF 3 - -; GEN 4 -; PCIe lane width x1 -%QDMA.DeviceDesc%= QDMA_Device, PCI\VEN_10ee&DEV_9041 ; PF 0 -%QDMA.DeviceDesc%= QDMA_Device, PCI\VEN_10ee&DEV_9141 ; PF 1 -%QDMA.DeviceDesc%= QDMA_Device, PCI\VEN_10ee&DEV_9241 ; PF 2 -%QDMA.DeviceDesc%= QDMA_Device, PCI\VEN_10ee&DEV_9341 ; PF 3 -; PCIe lane width x2 -%QDMA.DeviceDesc%= QDMA_Device, PCI\VEN_10ee&DEV_9042 ; PF 0 -%QDMA.DeviceDesc%= QDMA_Device, PCI\VEN_10ee&DEV_9142 ; PF 1 -%QDMA.DeviceDesc%= QDMA_Device, PCI\VEN_10ee&DEV_9242 ; PF 2 -%QDMA.DeviceDesc%= QDMA_Device, PCI\VEN_10ee&DEV_9342 ; PF 3 -; PCIe lane width x4 -%QDMA.DeviceDesc%= QDMA_Device, PCI\VEN_10ee&DEV_9044 ; PF 0 -%QDMA.DeviceDesc%= QDMA_Device, PCI\VEN_10ee&DEV_9144 ; PF 1 -%QDMA.DeviceDesc%= QDMA_Device, PCI\VEN_10ee&DEV_9244 ; PF 2 -%QDMA.DeviceDesc%= QDMA_Device, PCI\VEN_10ee&DEV_9344 ; PF 3 -; PCIe lane width x8 -%QDMA.DeviceDesc%= QDMA_Device, PCI\VEN_10ee&DEV_9048 ; PF 0 -%QDMA.DeviceDesc%= QDMA_Device, PCI\VEN_10ee&DEV_9148 ; PF 1 -%QDMA.DeviceDesc%= QDMA_Device, PCI\VEN_10ee&DEV_9248 ; PF 2 -%QDMA.DeviceDesc%= QDMA_Device, PCI\VEN_10ee&DEV_9348 ; PF 3 - -; Versal -; GEN 1 -; PCIe lane width x1 -%QDMA.DeviceDesc%= QDMA_Device, PCI\VEN_10ee&DEV_b011 ; PF 0 -%QDMA.DeviceDesc%= QDMA_Device, PCI\VEN_10ee&DEV_b111 ; PF 1 -%QDMA.DeviceDesc%= QDMA_Device, PCI\VEN_10ee&DEV_b211 ; PF 2 -%QDMA.DeviceDesc%= QDMA_Device, PCI\VEN_10ee&DEV_b311 ; PF 3 -; PCIe lane width x2 -%QDMA.DeviceDesc%= QDMA_Device, PCI\VEN_10ee&DEV_b012 ; PF 0 -%QDMA.DeviceDesc%= QDMA_Device, PCI\VEN_10ee&DEV_b112 ; PF 1 -%QDMA.DeviceDesc%= QDMA_Device, PCI\VEN_10ee&DEV_b212 ; PF 2 -%QDMA.DeviceDesc%= QDMA_Device, PCI\VEN_10ee&DEV_b312 ; PF 3 -; PCIe lane width x4 -%QDMA.DeviceDesc%= QDMA_Device, PCI\VEN_10ee&DEV_b014 ; PF 0 -%QDMA.DeviceDesc%= QDMA_Device, PCI\VEN_10ee&DEV_b114 ; PF 1 -%QDMA.DeviceDesc%= QDMA_Device, PCI\VEN_10ee&DEV_b214 ; PF 2 -%QDMA.DeviceDesc%= QDMA_Device, PCI\VEN_10ee&DEV_b314 ; PF 3 -; PCIe lane width x8 -%QDMA.DeviceDesc%= QDMA_Device, PCI\VEN_10ee&DEV_b018 ; PF 0 -%QDMA.DeviceDesc%= QDMA_Device, PCI\VEN_10ee&DEV_b118 ; PF 1 -%QDMA.DeviceDesc%= QDMA_Device, PCI\VEN_10ee&DEV_b218 ; PF 2 -%QDMA.DeviceDesc%= QDMA_Device, PCI\VEN_10ee&DEV_b318 ; PF 3 -; PCIe lane width x16 -%QDMA.DeviceDesc%= QDMA_Device, PCI\VEN_10ee&DEV_b01f ; PF 0 -%QDMA.DeviceDesc%= QDMA_Device, PCI\VEN_10ee&DEV_b11f ; PF 1 -%QDMA.DeviceDesc%= QDMA_Device, PCI\VEN_10ee&DEV_b21f ; PF 2 -%QDMA.DeviceDesc%= QDMA_Device, PCI\VEN_10ee&DEV_b31f ; PF 3 - -; GEN 2 -; PCIe lane width x1 -%QDMA.DeviceDesc%= QDMA_Device, PCI\VEN_10ee&DEV_b021 ; PF 0 -%QDMA.DeviceDesc%= QDMA_Device, PCI\VEN_10ee&DEV_b121 ; PF 1 -%QDMA.DeviceDesc%= QDMA_Device, PCI\VEN_10ee&DEV_b221 ; PF 2 -%QDMA.DeviceDesc%= QDMA_Device, PCI\VEN_10ee&DEV_b321 ; PF 3 -; PCIe lane width x2 -%QDMA.DeviceDesc%= QDMA_Device, PCI\VEN_10ee&DEV_b022 ; PF 0 -%QDMA.DeviceDesc%= QDMA_Device, PCI\VEN_10ee&DEV_b122 ; PF 1 -%QDMA.DeviceDesc%= QDMA_Device, PCI\VEN_10ee&DEV_b222 ; PF 2 -%QDMA.DeviceDesc%= QDMA_Device, PCI\VEN_10ee&DEV_b322 ; PF 3 -; PCIe lane width x4 -%QDMA.DeviceDesc%= QDMA_Device, PCI\VEN_10ee&DEV_b024 ; PF 0 -%QDMA.DeviceDesc%= QDMA_Device, PCI\VEN_10ee&DEV_b124 ; PF 1 -%QDMA.DeviceDesc%= QDMA_Device, PCI\VEN_10ee&DEV_b224 ; PF 2 -%QDMA.DeviceDesc%= QDMA_Device, PCI\VEN_10ee&DEV_b324 ; PF 3 -; PCIe lane width x8 -%QDMA.DeviceDesc%= QDMA_Device, PCI\VEN_10ee&DEV_b028 ; PF 0 -%QDMA.DeviceDesc%= QDMA_Device, PCI\VEN_10ee&DEV_b128 ; PF 1 -%QDMA.DeviceDesc%= QDMA_Device, PCI\VEN_10ee&DEV_b228 ; PF 2 -%QDMA.DeviceDesc%= QDMA_Device, PCI\VEN_10ee&DEV_b328 ; PF 3 -; PCIe lane width x16 -%QDMA.DeviceDesc%= QDMA_Device, PCI\VEN_10ee&DEV_b02f ; PF 0 -%QDMA.DeviceDesc%= QDMA_Device, PCI\VEN_10ee&DEV_b12f ; PF 1 -%QDMA.DeviceDesc%= QDMA_Device, PCI\VEN_10ee&DEV_b22f ; PF 2 -%QDMA.DeviceDesc%= QDMA_Device, PCI\VEN_10ee&DEV_b32f ; PF 3 - -; GEN 3 -; PCIe lane width x1 -%QDMA.DeviceDesc%= QDMA_Device, PCI\VEN_10ee&DEV_b031 ; PF 0 -%QDMA.DeviceDesc%= QDMA_Device, PCI\VEN_10ee&DEV_b131 ; PF 1 -%QDMA.DeviceDesc%= QDMA_Device, PCI\VEN_10ee&DEV_b231 ; PF 2 -%QDMA.DeviceDesc%= QDMA_Device, PCI\VEN_10ee&DEV_b331 ; PF 3 -; PCIe lane width x2 -%QDMA.DeviceDesc%= QDMA_Device, PCI\VEN_10ee&DEV_b032 ; PF 0 -%QDMA.DeviceDesc%= QDMA_Device, PCI\VEN_10ee&DEV_b132 ; PF 1 -%QDMA.DeviceDesc%= QDMA_Device, PCI\VEN_10ee&DEV_b232 ; PF 2 -%QDMA.DeviceDesc%= QDMA_Device, PCI\VEN_10ee&DEV_b332 ; PF 3 -; PCIe lane width x4 -%QDMA.DeviceDesc%= QDMA_Device, PCI\VEN_10ee&DEV_b034 ; PF 0 -%QDMA.DeviceDesc%= QDMA_Device, PCI\VEN_10ee&DEV_b134 ; PF 1 -%QDMA.DeviceDesc%= QDMA_Device, PCI\VEN_10ee&DEV_b234 ; PF 2 -%QDMA.DeviceDesc%= QDMA_Device, PCI\VEN_10ee&DEV_b334 ; PF 3 -; PCIe lane width x8 -%QDMA.DeviceDesc%= QDMA_Device, PCI\VEN_10ee&DEV_b038 ; PF 0 -%QDMA.DeviceDesc%= QDMA_Device, PCI\VEN_10ee&DEV_b138 ; PF 1 -%QDMA.DeviceDesc%= QDMA_Device, PCI\VEN_10ee&DEV_b238 ; PF 2 -%QDMA.DeviceDesc%= QDMA_Device, PCI\VEN_10ee&DEV_b338 ; PF 3 -; PCIe lane width x16 -%QDMA.DeviceDesc%= QDMA_Device, PCI\VEN_10ee&DEV_b03f ; PF 0 -%QDMA.DeviceDesc%= QDMA_Device, PCI\VEN_10ee&DEV_b13f ; PF 1 -%QDMA.DeviceDesc%= QDMA_Device, PCI\VEN_10ee&DEV_b23f ; PF 2 -%QDMA.DeviceDesc%= QDMA_Device, PCI\VEN_10ee&DEV_b33f ; PF 3 - -; GEN 4 -; PCIe lane width x1 -%QDMA.DeviceDesc%= QDMA_Device, PCI\VEN_10ee&DEV_b041 ; PF 0 -%QDMA.DeviceDesc%= QDMA_Device, PCI\VEN_10ee&DEV_b141 ; PF 1 -%QDMA.DeviceDesc%= QDMA_Device, PCI\VEN_10ee&DEV_b241 ; PF 2 -%QDMA.DeviceDesc%= QDMA_Device, PCI\VEN_10ee&DEV_b341 ; PF 3 -; PCIe lane width x2 -%QDMA.DeviceDesc%= QDMA_Device, PCI\VEN_10ee&DEV_b042 ; PF 0 -%QDMA.DeviceDesc%= QDMA_Device, PCI\VEN_10ee&DEV_b142 ; PF 1 -%QDMA.DeviceDesc%= QDMA_Device, PCI\VEN_10ee&DEV_b242 ; PF 2 -%QDMA.DeviceDesc%= QDMA_Device, PCI\VEN_10ee&DEV_b342 ; PF 3 -; PCIe lane width x4 -%QDMA.DeviceDesc%= QDMA_Device, PCI\VEN_10ee&DEV_b044 ; PF 0 -%QDMA.DeviceDesc%= QDMA_Device, PCI\VEN_10ee&DEV_b144 ; PF 1 -%QDMA.DeviceDesc%= QDMA_Device, PCI\VEN_10ee&DEV_b244 ; PF 2 -%QDMA.DeviceDesc%= QDMA_Device, PCI\VEN_10ee&DEV_b344 ; PF 3 -; PCIe lane width x8 -%QDMA.DeviceDesc%= QDMA_Device, PCI\VEN_10ee&DEV_b048 ; PF 0 -%QDMA.DeviceDesc%= QDMA_Device, PCI\VEN_10ee&DEV_b148 ; PF 1 -%QDMA.DeviceDesc%= QDMA_Device, PCI\VEN_10ee&DEV_b248 ; PF 2 -%QDMA.DeviceDesc%= QDMA_Device, PCI\VEN_10ee&DEV_b348 ; PF 3 - -[QDMA_Device.NT] -CopyFiles=Drivers_Dir - -; MSI/MSI-X support -[QDMA_Device.NT.HW] -AddReg = QDMA_Device.EnableMSI - -[QDMA_Device.EnableMSI] -HKR,"Interrupt Management",,0x00000010 -HKR,"Interrupt Management\MessageSignaledInterruptProperties",,0x00000010 -HKR,"Interrupt Management\MessageSignaledInterruptProperties",MSISupported,0x00010001,1 -HKR,"Interrupt Management\MessageSignaledInterruptProperties",MessageNumberLimit,0x00010001,32 - -[Drivers_Dir] -QDMA.sys - -; ================= Service installation ====================================== - -[QDMA_Device.NT.Services] -AddService = QDMA,%SPSVCINST_ASSOCSERVICE%, QDMA_Service_Inst - -; ================= QDMA driver install sections ============================== - -[QDMA_Service_Inst] -DisplayName = %QDMA.SVCDESC% -ServiceType = 1 ; SERVICE_KERNEL_DRIVER -StartType = 3 ; SERVICE_DEMAND_START -ErrorControl = 1 ; SERVICE_ERROR_NORMAL -ServiceBinary = %12%\QDMA.sys -AddReg = QDMA_Device_Inst.NT.Services.AddReg - -[QDMA_Device_Inst.NT.Services.AddReg] -; Driver operation mode. -HKR,Parameters,"DRIVER_MODE",0x00010001,0 ;set to 0 - hardware polling, 1 - Direct Interrupt, 2 - Indirect Interrupt (default is 0 - polling) -; Config BAR Index -HKR,Parameters,"CONFIG_BAR",0x00010001,0 ;set to either 0, 1 or 2 (default is 0) - -; ================= QDMA_Device Coinstaller installation ====================== - -[QDMA_Device.NT.CoInstallers] -AddReg=QDMA_Device_CoInstaller_AddReg -CopyFiles=QDMA_Device_CoInstaller_CopyFiles - -[QDMA_Device_CoInstaller_AddReg] -HKR,,CoInstallers32,0x00010000, "WdfCoInstaller$KMDFCOINSTALLERVERSION$.dll,WdfCoInstaller" - -[QDMA_Device_CoInstaller_CopyFiles] -WdfCoInstaller$KMDFCOINSTALLERVERSION$.dll - -[QDMA_Device.NT.Wdf] -KmdfService = QDMA, QDMA_wdfsect - -[QDMA_wdfsect] -KmdfLibraryVersion = $KMDFVERSION$ - -[Strings] -SPSVCINST_ASSOCSERVICE = 0x00000002 -ManufacturerName = "Xilinx" -ClassName = "Xilinx Drivers" -DiskName = "QDMA Installation Disk" -QDMA.DeviceDesc = "Xilinx PCIe Multi-Queue DMA" -QDMA.SVCDESC = "QDMA Service" diff --git a/QDMA/windows/sys/drv/qdma_generic.vcxproj b/QDMA/windows/sys/drv/qdma_generic.vcxproj deleted file mode 100644 index 69b3ede6b..000000000 --- a/QDMA/windows/sys/drv/qdma_generic.vcxproj +++ /dev/null @@ -1,213 +0,0 @@ - - - - - Debug - Win32 - - - Release - Win32 - - - Debug - x64 - - - Release - x64 - - - - {B446331B-DD9E-40DD-958A-8D7A1AACA454} - {497e31cb-056b-4f31-abb8-447fd55ee5a5} - - - 12.0 - Debug - Win32 - MDMA - QDMA Reference Driver - - - - Windows10 - true - WindowsKernelModeDriver10.0 - Driver - KMDF - Desktop - true - 1 - false - - - Windows10 - false - WindowsKernelModeDriver10.0 - Driver - KMDF - Desktop - true - 1 - false - - - Windows10 - true - WindowsKernelModeDriver10.0 - Driver - KMDF - Desktop - true - 1 - false - - - Windows10 - false - WindowsKernelModeDriver10.0 - Driver - KMDF - Desktop - true - 1 - false - - - - - - - - - - - DbgengKernelDebugger - $(SolutionDir)build\$(Platform)\$(ConfigurationName)\sys\ - $(SolutionDir).tmp\$(Platform)\$(ConfigurationName)\$(ProjectName)\ - QDMA - - - DbgengKernelDebugger - $(SolutionDir)build\$(Platform)\$(ConfigurationName)\sys\ - $(SolutionDir).tmp\$(Platform)\$(ConfigurationName)\$(ProjectName)\ - QDMA - - - DbgengKernelDebugger - $(SolutionDir)build\$(Platform)\$(ConfigurationName)\sys\ - QDMA - $(SolutionDir).tmp\$(Platform)\$(ConfigurationName)\$(ProjectName)\ - - - DbgengKernelDebugger - $(SolutionDir)build\$(Platform)\$(ConfigurationName)\sys\ - $(SolutionDir).tmp\$(Platform)\$(ConfigurationName)\$(ProjectName)\ - QDMA - - - - true - false - include\trace.h - true - CompileAsCpp - false - $(ProjectDir)\..\libqdma\include;$(ProjectDir)\include;%(AdditionalIncludeDirectories) - qdma - stdcpp17 - false - - - - - - - false - false - include\trace.h - true - CompileAsCpp - false - $(ProjectDir)\..\libqdma\include;$(ProjectDir)\include;%(AdditionalIncludeDirectories) - qdma - stdcpp17 - - - - - - - - - true - false - source\trace.h - true - CompileAsCpp - false - $(ProjectDir)\..\libqdma\include;$(ProjectDir)\include;$(ProjectDir)\source;%(AdditionalIncludeDirectories) - true - qdma - stdcpp17 - false - $(ExternalCompilerOptions) %(AdditionalOptions) - - - - - - - false - false - source\trace.h - true - CompileAsCpp - false - $(ProjectDir)\..\libqdma\include;$(ProjectDir)\include;$(ProjectDir)\source;%(AdditionalIncludeDirectories) - qdma - stdcpp17 - $(ExternalCompilerOptions) %(AdditionalOptions) - - - - - - - - - - - - - - - - - - - - - {359143e6-933a-49cc-806c-c5376e1809a4} - - - - - - - - - - - - - - - - - - - - - \ No newline at end of file diff --git a/QDMA/windows/sys/drv/qdma_generic.vcxproj.filters b/QDMA/windows/sys/drv/qdma_generic.vcxproj.filters deleted file mode 100644 index ce750f2bd..000000000 --- a/QDMA/windows/sys/drv/qdma_generic.vcxproj.filters +++ /dev/null @@ -1,73 +0,0 @@ - - - - - {4FC737F1-C7A5-4376-A066-2A32D752A2FF} - cpp;c;cc;cxx;def;odl;idl;hpj;bat;asm;asmx - - - {93995380-89BD-4b04-88EB-625FBE52EBFB} - h;hpp;hxx;hm;inl;inc;xsd - - - {67DA6AB6-F800-4c08-8B7A-83BB121AAD01} - rc;ico;cur;bmp;dlg;rc2;rct;bin;rgs;gif;jpg;jpeg;jpe;resx;tiff;tif;png;wav;mfcribbon-ms - - - {8E41214B-6785-4CFE-B992-037D68949A14} - inf;inv;inx;mof;mc; - - - - - Driver Files - - - - - Resource Files - - - - - Resource Files - - - - - Header Files - - - Header Files - - - Header Files - - - Header Files - - - Header Files - - - Header Files - - - Header Files - - - Header Files - - - - - Source Files - - - Source Files - - - Source Files - - - \ No newline at end of file diff --git a/QDMA/windows/sys/drv/qdma_generic.vcxproj.user b/QDMA/windows/sys/drv/qdma_generic.vcxproj.user deleted file mode 100644 index a667f8f86..000000000 --- a/QDMA/windows/sys/drv/qdma_generic.vcxproj.user +++ /dev/null @@ -1,36 +0,0 @@ - - - - False - None - - - C:\Program Files (x86)\Windows Kits\10\Testing\Tests\Utilities\DefaultDriverPackageInstallationTask.dll - XIRIPDSLAB20 - XIRIPDSLAB20 - - Microsoft.DriverKit.DefaultDriverPackageInstallationClass.PerformDefaultDriverPackageInstallation - - True - False - True - - 133563 - FvOn - DbgengRemoteDebugger - - - - - - - - - - - - - - - - \ No newline at end of file diff --git a/QDMA/windows/sys/drv/resource/Resource.aps b/QDMA/windows/sys/drv/resource/Resource.aps deleted file mode 100644 index 0c3530ff98bfca8f73aa146fefa36be5a3b9ad6d..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 2984 zcmb_eOOM-B6#h&D>HrlZgiysQEnTz{3HEgQnhna>9>!`Cha{6`BuiE%@yw*kW0Xge zB37)B*z!YIuw`HI3s{#Q01K9g@SW>8vEz0M5{a&Teb4)xd%k-CAj`2>goD$>?|XjT z;yA<;?DM@?XiNIm_2mSAYyr-m*AMz9!D#HYdcnLk=mg%yX!tZ}PsZN7+v^VIxgA~C zy{1(v_|~ZVjI24`*xm7*$~`}l@rB2iW&d>A>v@NE!BTp>@ytITjwfEf({FjR?w~WA zjlB|;dDUP%oQ~Q-e$)nD(y64sFO-`)*8bj5D>pD&3L5!yFe<-LsrhBQS@)}U%{{7` zw%;fek8Bva0fxAyn{KI8C|gVNE?qY8Zjzx~ue!yRJn8Sn>9ymM9f^zf_kqYMhDN`X zM_QxiH|%Q7am&6_K5${+Luig=`n7tY?wGipGwvVu&qJND zI%TtXWHClXy~X;*S9e~ydUv%d{J?iiUeea*Tmkg$b{uKpgHuuwt)KHnqKpDnfKNH?%cP7e+$xJQmn zJN`c8x(=&;s!_newro8KrGE*LxmY#X^E8xnI zdPj^WpkH}v08EvQii-7&&lWXhaiAg{oAp*-$99eB zQ`54G2jR>tx;2}5Rm+EVv4Tf3Uw8H^I-f~d(>EJ8K{VY|*Kg3%utA1cL+4a3hz5*_ zndUBR^68+=9aF>+_m$1{2!rFj9LKVc-zXneIxhcdchK%lJ3;nl1VA^h5z=twjk<(` zy&l6?5u9^5%k{-#d+l!w59U`S!Uk&WsRpB}a^}Egq`r#xfOGl%ocaB4NR2q;8NI(y zb8v%XfNgH~*zZ?{r%~U8oh7(&w(2bDlT-F1@RQ=vnP;7QK;9>Of_-_7vL<=@#3I3^ z=k!VXGf)SWcSP)%gFe&mJ!V8fz}6Tx5H*N^-_Y z{CUD$Sgr7Mw&=UYZfQ|Eic~5W?r6bV_5v#^=gEMv_V|wPyRFQRnIE)GT#is5h-Px< z6I++v`CgL#XM!hv&yqXHU$nQ@lfHw<-Qk>u*F5RF!#?$V#L(6}=`%~tn{N_4>GMW# l^~Kx&4OazAufB7cOqjJe{s|)1FO^ASrr_nAGOxqSe*oA5{w4qb diff --git a/QDMA/windows/sys/drv/resource/Resource.rc b/QDMA/windows/sys/drv/resource/Resource.rc deleted file mode 100644 index eee2360e5ee55d9476640e2054304c0d95020e92..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 2038 zcmb7_ZEq4$5QXQniT~kd`$dgiOg|c9LQ7R*kqU^CG-;NXA_)cL#o9lwK4&fqtff}7 z*}Zq~ojLc+nVH>RKTGz^9@`@ejKNN9YBRgFxs7aSUv0_S6IP!x9@z`OgMDFl%ssIm z_MDw6v)%?}i*|-h&j#!+c=oYeG4C^<1HQ|R=T`B6hc0Dq3DcKW;=1uG#b>K@ z3jUlNmpqznmKLm>kiXdcjhd5DURHkB$(RfA0|Rj<)=tJ^+0kuBz?&yJ_+)c>X%JU}7AwJ)+nzOE&93x%iyg%t&RV*$F8NF`9e||H9K%junqaS}6s<*mDZTO9t@l|@U=r<$4#(E z?PC2@G+pYyPfQuBMHUz2DB|Wy2wi=V>@XK!eSs#byZL=lI1c7f#DNK(Qo+ z|4P8_1UqH0MlQ!*BZu~p`M~c(qO8#$0R-u$YSX_aew8b{jn@nh$KDp)It({`Msp{k3>e~A% JT`LhQ|2LLRJre)` diff --git a/QDMA/windows/sys/drv/source/device.cpp b/QDMA/windows/sys/drv/source/device.cpp deleted file mode 100644 index fd900c064..000000000 --- a/QDMA/windows/sys/drv/source/device.cpp +++ /dev/null @@ -1,248 +0,0 @@ -/* - * Copyright (C) 2020 Xilinx, Inc - * - * Licensed under the Apache License, Version 2.0 (the "License"). You may - * not use this file except in compliance with the License. You may obtain - * a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - */ - -#define INITGUID - -#include "qdma_driver_api.h" -#include "io_queue.h" -#include "device.h" - -#include "trace.h" - -#ifdef ENABLE_WPP_TRACING -#include "device.tmh" -#endif - -#ifdef ALLOC_PRAGMA -#pragma alloc_text (PAGE, qdma_create_device) -#pragma alloc_text (PAGE, qdma_evt_device_prepare_hardware) -#pragma alloc_text (PAGE, qdma_evt_device_release_hardware) -#endif - -using namespace xlnx; - -_Use_decl_annotations_ -NTSTATUS -qdma_create_device( - _Inout_ PWDFDEVICE_INIT wdf_device_init -) -{ - PAGED_CODE(); - - WdfDeviceInitSetIoType(wdf_device_init, WdfDeviceIoDirect); - - /* Set call-backs for any of the functions we are interested in. If no call-back is set, the - * framework will take the default action by itself. - */ - WDF_PNPPOWER_EVENT_CALLBACKS pnp_power_callbacks; - WDF_PNPPOWER_EVENT_CALLBACKS_INIT(&pnp_power_callbacks); - pnp_power_callbacks.EvtDevicePrepareHardware = qdma_evt_device_prepare_hardware; - pnp_power_callbacks.EvtDeviceReleaseHardware = qdma_evt_device_release_hardware; - WdfDeviceInitSetPnpPowerEventCallbacks(wdf_device_init, &pnp_power_callbacks); - - WDF_OBJECT_ATTRIBUTES device_attributes; - WDF_OBJECT_ATTRIBUTES_INIT_CONTEXT_TYPE(&device_attributes, device_context); - - /* Register file object call-backs */ - WDF_FILEOBJECT_CONFIG file_config; - WDF_FILEOBJECT_CONFIG_INIT(&file_config, - qdma_evt_device_file_create, - qdma_evt_device_file_close, - qdma_evt_device_file_cleanup); - WDF_OBJECT_ATTRIBUTES file_attribs; - WDF_OBJECT_ATTRIBUTES_INIT(&file_attribs); - file_attribs.SynchronizationScope = WdfSynchronizationScopeNone; - WDF_OBJECT_ATTRIBUTES_SET_CONTEXT_TYPE(&file_attribs, file_context); - WdfDeviceInitSetFileObjectConfig(wdf_device_init, &file_config, &file_attribs); - - WDFDEVICE device; - auto status = WdfDeviceCreate(&wdf_device_init, &device_attributes, &device); - if (!NT_SUCCESS(status)) { - TraceError(TRACE_DEVICE, "WdfDeviceCreate failed! %!STATUS!", status); - return status; - } - - /* Create a device interface to user-space */ - status = WdfDeviceCreateDeviceInterface(device, &GUID_DEVINTERFACE_QDMA, nullptr); - if (!NT_SUCCESS(status)) { - TraceError(TRACE_DEVICE, "WdfDeviceCreateDeviceInterface failed! %!STATUS!", status); - return status; - } - - /* Initialize the I/O Package and any Queues */ - status = qdma_io_queue_initialize(device); - if (!NT_SUCCESS(status)) { - TraceError(TRACE_DEVICE, "qdma_io_queue_initialize() failed! %!STATUS!", status); - return status; - } - - return status; -} - -static NTSTATUS read_reg_params( - xlnx::queue_op_mode &op_mode, - UINT8 &config_bar) -{ - WDFKEY key; - DECLARE_CONST_UNICODE_STRING(value_drv_mode, L"DRIVER_MODE"); - DECLARE_CONST_UNICODE_STRING(value_config_bar, L"CONFIG_BAR"); - op_mode = xlnx::queue_op_mode::POLL_MODE; - WDFDRIVER driver = WdfGetDriver(); - - NTSTATUS status = WdfDriverOpenParametersRegistryKey(driver, - STANDARD_RIGHTS_ALL, - WDF_NO_OBJECT_ATTRIBUTES, - &key); - if (!NT_SUCCESS(status)) { - TraceError(TRACE_DEVICE, "WdfDriverOpenParametersRegistryKey failed: %!STATUS!", status); - goto ErrExit; - } - - ULONG DRV_MODE; - status = WdfRegistryQueryULong(key, &value_drv_mode, &DRV_MODE); - if (!NT_SUCCESS(status)) { - TraceError(TRACE_DEVICE, "WdfRegistryQueryULong failed: %!STATUS!", status); - goto ErrExit; - } - - if (DRV_MODE > INTR_COAL_MODE) { - TraceError(TRACE_DEVICE, "Invalid parameter DRIVER_MODE - [%lu]", DRV_MODE); - status = STATUS_INVALID_PARAMETER; - goto ErrExit; - } - - op_mode = (xlnx::queue_op_mode)DRV_MODE; - - ULONG CONFIG_BAR; - status = WdfRegistryQueryULong(key, &value_config_bar, &CONFIG_BAR); - if (!NT_SUCCESS(status)) { - TraceError(TRACE_DEVICE, "WdfRegistryQueryULong failed: %!STATUS!", status); - goto ErrExit; - } - - if (CONFIG_BAR > 2ul) { - TraceError(TRACE_DEVICE, "Invalid parameter CONFIG_BAR - [%lu]", CONFIG_BAR); - status = STATUS_INVALID_PARAMETER; - goto ErrExit; - } - - config_bar = (UINT8)CONFIG_BAR; - - TraceVerbose(TRACE_DEVICE, "Parameter DRV_MODE - [%lu] CONFIG_BAR - [%lu]", op_mode, CONFIG_BAR); - -ErrExit: - WdfRegistryClose(key); - return status; -} - -//_Use_decl_annotations_ -static void -qdma_user_isr_handler( - ULONG event_id, - void *user_data) -{ - UNREFERENCED_PARAMETER(event_id); - UNREFERENCED_PARAMETER(user_data); - TraceInfo(TRACE_DEVICE, "In %s", __func__); -} - -//_Use_decl_annotations_ -static void -qdma_user_interrupt_enable( - ULONG event_id, - void *user_data) -{ - UNREFERENCED_PARAMETER(event_id); - UNREFERENCED_PARAMETER(user_data); - TraceInfo(TRACE_DEVICE, "In %s", __func__); -} - -//_Use_decl_annotations_ -static void -qdma_user_interrupt_disable( - ULONG event_id, - void *user_data) -{ - UNREFERENCED_PARAMETER(event_id); - UNREFERENCED_PARAMETER(user_data); - TraceInfo(TRACE_DEVICE, "In %s", __func__); -} - -NTSTATUS qdma_evt_device_prepare_hardware( - const WDFDEVICE device, - const WDFCMRESLIST resources, - const WDFCMRESLIST resources_translated) -{ - PAGED_CODE(); - - qdma_drv_config drv_conf = {}; - device_context *ctx = get_device_context(device); - - ctx->qdma = qdma_interface::create_qdma_device(); - if (ctx->qdma == nullptr) { - TraceError(TRACE_DEVICE, "qdma device memory allocation failed"); - return STATUS_INSUFFICIENT_RESOURCES; - } - - - NTSTATUS status = read_reg_params(ctx->config.op_mode, ctx->config.config_bar); - if (!NT_SUCCESS(status)) { - TraceError(TRACE_DEVICE, "failed to read registry params %!STATUS!", status); - return status; - } - - drv_conf.operation_mode = ctx->config.op_mode; - drv_conf.cfg_bar = ctx->config.config_bar; - drv_conf.qsets_max = QDMA_MAX_QUEUES_PER_PF; - drv_conf.user_msix_max = QDMA_MAX_USER_INTR; - drv_conf.data_msix_max = QDMA_MAX_DATA_INTR; - drv_conf.user_data = (void*)device; - drv_conf.user_isr_handler = qdma_user_isr_handler; - drv_conf.user_interrupt_enable_handler = qdma_user_interrupt_enable; - drv_conf.user_interrupt_disable_handler = qdma_user_interrupt_disable; - - status = ctx->qdma->init(drv_conf); - if (!NT_SUCCESS(status)) { - TraceError(TRACE_DEVICE, "qdma.init() failed! %!STATUS!", status); - return status; - } - - status = ctx->qdma->open(device, resources, resources_translated); - if (!NT_SUCCESS(status)) { - TraceError(TRACE_DEVICE, "qdma.open() failed! %!STATUS!", status); - return status; - } - - return STATUS_SUCCESS; -} - -NTSTATUS qdma_evt_device_release_hardware( - const WDFDEVICE device, - WDFCMRESLIST resources_translated) -{ - PAGED_CODE(); - - UNREFERENCED_PARAMETER(resources_translated); - - device_context* ctx = get_device_context(device); - if (ctx) { - ctx->qdma->close(); - qdma_interface::remove_qdma_device(ctx->qdma); - ctx->qdma = nullptr; - } - - return STATUS_SUCCESS; -} \ No newline at end of file diff --git a/QDMA/windows/sys/drv/source/device.h b/QDMA/windows/sys/drv/source/device.h deleted file mode 100644 index 7bce0ad08..000000000 --- a/QDMA/windows/sys/drv/source/device.h +++ /dev/null @@ -1,65 +0,0 @@ -/* - * Copyright (C) 2020 Xilinx, Inc - * - * Licensed under the Apache License, Version 2.0 (the "License"). You may - * not use this file except in compliance with the License. You may obtain - * a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - */ - -#pragma once - -#include "windows_common.h" -#include "qdma_exports.h" - -EXTERN_C_START - -#define QDMA_MAX_QUEUES_PER_PF 512 -#define QDMA_MAX_USER_INTR 1 -#define QDMA_MAX_DATA_INTR 7 - -struct device_context { - struct { - xlnx::queue_op_mode op_mode; - UINT8 config_bar; - }config; - - xlnx::qdma_interface *qdma; -}; -WDF_DECLARE_CONTEXT_TYPE_WITH_NAME(device_context, get_device_context) - -_IRQL_requires_same_ -_IRQL_requires_max_(PASSIVE_LEVEL) -NTSTATUS -qdma_create_device( - _Inout_ PWDFDEVICE_INIT device_init -); - -enum class file_target { - USER, - CONTROL, - BYPASS, - DMA_QUEUE, - ST_QUEUE, - MGMT, - UNKNOWN = 255, -}; - -struct file_context { - file_target target; - UINT16 qid; - bool no_copy; -}; -WDF_DECLARE_CONTEXT_TYPE_WITH_NAME(file_context, get_file_context) - -EVT_WDF_DEVICE_PREPARE_HARDWARE qdma_evt_device_prepare_hardware; -EVT_WDF_DEVICE_RELEASE_HARDWARE qdma_evt_device_release_hardware; - -EXTERN_C_END diff --git a/QDMA/windows/sys/drv/source/driver.cpp b/QDMA/windows/sys/drv/source/driver.cpp deleted file mode 100644 index 09c0502b3..000000000 --- a/QDMA/windows/sys/drv/source/driver.cpp +++ /dev/null @@ -1,98 +0,0 @@ -/* - * Copyright (C) 2020 Xilinx, Inc - * - * Licensed under the Apache License, Version 2.0 (the "License"). You may - * not use this file except in compliance with the License. You may obtain - * a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - */ - -#include "driver.h" -#include "device.h" - -#include "trace.h" - -#ifdef ENABLE_WPP_TRACING -#include "driver.tmh" -#endif - -#ifdef ALLOC_PRAGMA -#pragma alloc_text (INIT, DriverEntry) -#pragma alloc_text (PAGE, qdma_evt_device_add) -#pragma alloc_text (PAGE, qdma_evt_driver_context_cleanup) -#endif - -using namespace xlnx; - -_Use_decl_annotations_ -NTSTATUS -DriverEntry( - _In_ PDRIVER_OBJECT driver_object, - _In_ PUNICODE_STRING registry_path -) -{ - /** Initialize WPP Tracing */ - WPP_INIT_TRACING(driver_object, registry_path); - - TraceInfo(TRACE_DRIVER, "Xilinx PCIe Multi-Queue DMA Driver - Built %s,%s", - __DATE__, __TIME__); - - /** Register a cleanup callback to call WPP_CLEANUP during driver unload */ - WDF_OBJECT_ATTRIBUTES attributes; - WDF_OBJECT_ATTRIBUTES_INIT(&attributes); - attributes.EvtCleanupCallback = qdma_evt_driver_context_cleanup; - - WDF_DRIVER_CONFIG config; - WDF_DRIVER_CONFIG_INIT(&config, qdma_evt_device_add); - - NTSTATUS status = WdfDriverCreate(driver_object, registry_path, &attributes, &config, WDF_NO_HANDLE); - - if (!NT_SUCCESS(status)) { - TraceError(TRACE_DRIVER, "WdfDriverCreate failed %!STATUS!", status); - WPP_CLEANUP(driver_object); - return status; - } - - TraceVerbose(TRACE_DRIVER, "%!FUNC! Exit"); - - return status; -} - -_Use_decl_annotations_ -NTSTATUS -qdma_evt_device_add( - _In_ WDFDRIVER driver, - _Inout_ PWDFDEVICE_INIT device_init -) -{ - UNREFERENCED_PARAMETER(driver); - - PAGED_CODE(); - return qdma_create_device(device_init); -} - -_Use_decl_annotations_ -VOID -qdma_evt_driver_context_cleanup( - _In_ WDFOBJECT driver_object -) -{ - // EvtCleanupCallback for WDFDEVICE objects is always called at PASSIVE_LEVEL - _IRQL_limited_to_(PASSIVE_LEVEL); - PAGED_CODE(); - -#ifndef ENABLE_WPP_TRACING - UNREFERENCED_PARAMETER(driver_object); -#endif - - TraceVerbose(TRACE_DRIVER, "%!FUNC! Entry"); - /** Stop WPP Tracing */ - WPP_CLEANUP(WdfDriverWdmGetDriverObject(static_cast(driver_object))); -} diff --git a/QDMA/windows/sys/drv/source/driver.h b/QDMA/windows/sys/drv/source/driver.h deleted file mode 100644 index 929ff6180..000000000 --- a/QDMA/windows/sys/drv/source/driver.h +++ /dev/null @@ -1,32 +0,0 @@ -/* - * Copyright (C) 2020 Xilinx, Inc - * - * Licensed under the Apache License, Version 2.0 (the "License"). You may - * not use this file except in compliance with the License. You may obtain - * a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - */ - -#pragma once - -#include "windows_common.h" - -EXTERN_C_START - -/** - * WDFDRIVER Events - */ - -DRIVER_INITIALIZE DriverEntry; -EVT_WDF_DRIVER_DEVICE_ADD qdma_evt_device_add; -EVT_WDF_OBJECT_CONTEXT_CLEANUP qdma_evt_driver_context_cleanup; - - -EXTERN_C_END diff --git a/QDMA/windows/sys/drv/source/io_queue.cpp b/QDMA/windows/sys/drv/source/io_queue.cpp deleted file mode 100644 index 964b4e185..000000000 --- a/QDMA/windows/sys/drv/source/io_queue.cpp +++ /dev/null @@ -1,1441 +0,0 @@ -/* - * Copyright (C) 2020 Xilinx, Inc - * - * Licensed under the Apache License, Version 2.0 (the "License"). You may - * not use this file except in compliance with the License. You may obtain - * a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - */ - -#include "qdma_driver_api.h" -#include "device.h" -#include "io_queue.h" - -#include "trace.h" - -#ifdef ENABLE_WPP_TRACING -#include "io_queue.tmh" -#endif - -// remove some false positive static analysis errors related to trace messages -//#ifndef WPP_TRACING -//#define WPP_(x) (void) -//#endif - -#ifdef ALLOC_PRAGMA -#pragma alloc_text (PAGE, qdma_io_queue_initialize) -#endif - -using namespace xlnx; - -void drv_st_tx_zcmp_cb(void *priv, NTSTATUS status); -void drv_st_tx_cmp_cb(void *priv, NTSTATUS status); -void drv_mm_cmp_cb(void *priv, NTSTATUS status); -void drv_st_rx_cmp_cb(const st_c2h_pkt_fragment *rx_pkts, size_t num_pkts, void *priv, NTSTATUS status); -void drv_st_process_udd_only_pkts(UINT16 qid, void *udd_addr, void *priv); - -/* ----------------- static function definitions ----------------- */ -const static struct device_file_details { - file_target target; - const wchar_t* name; -} file_name_LUT[] = { - { file_target::USER, QDMA_FILE_USER }, - { file_target::CONTROL, QDMA_FILE_CONTROL }, - { file_target::BYPASS, QDMA_FILE_BYPASS }, - { file_target::DMA_QUEUE, QDMA_FILE_DMA_QUEUE }, - { file_target::ST_QUEUE, QDMA_FILE_DMA_ST_QUEUE }, - { file_target::MGMT, QDMA_FILE_DMA_MGMT}, -}; - -/* convert from filename to device node */ -static file_target parse_file_name( - const PUNICODE_STRING file_name) -{ - for (UINT i = 0; i < sizeof(file_name_LUT) / sizeof(file_name_LUT[0]); ++i) { - if (!wcscmp(file_name->Buffer, file_name_LUT[i].name)) { - return file_name_LUT[i].target; - } - if (wcsstr(file_name->Buffer, file_name_LUT[i].name) - && file_name->Length > wcslen(file_name_LUT[i].name)) { - return file_name_LUT[i].target; - } - } - TraceError(TRACE_DEVICE, "device file name does not match one of known types!"); - return file_target::UNKNOWN; -} - -static UINT16 extract_index_token( - const PUNICODE_STRING file_name) -{ - ULONG index = 0; - UNICODE_STRING token_uni; - RtlInitUnicodeString(&token_uni, wcsstr(file_name->Buffer, L"_") + 1); - auto status = RtlUnicodeStringToInteger(&token_uni, 10, &index); - if (!NT_SUCCESS(status)) { - TraceError(TRACE_DEVICE, "RtlUnicodeStringToInteger failed! %!STATUS!", status); - return UINT16_MAX; - } - return (UINT16)index; -} - -static void io_read_bar( - qdma_interface *qdma_dev, - qdma_bar_type bar_type, - const WDFREQUEST request, - const size_t length) -{ - WDF_REQUEST_PARAMETERS params; - WDF_REQUEST_PARAMETERS_INIT(¶ms); - WdfRequestGetParameters(request, ¶ms); - const auto offset = static_cast(params.Parameters.Read.DeviceOffset); - - /* get handle to the IO request memory which will hold the read data */ - WDFMEMORY request_mem; - auto status = WdfRequestRetrieveOutputMemory(request, &request_mem); - if (!NT_SUCCESS(status)) { - TraceError(TRACE_IO, "WdfRequestRetrieveOutputMemory failed: %!STATUS!", status); - goto ErrExit; - } - - /* get pointer to buffer */ - const auto req_buffer = WdfMemoryGetBuffer(request_mem, nullptr); - - status = qdma_dev->read_bar(bar_type, offset, req_buffer, length); - if (!NT_SUCCESS(status)) { - TraceError(TRACE_IO, "Reading PCIe BAR failed: %!STATUS!", status); - goto ErrExit; - } - - WdfRequestCompleteWithInformation(request, status, length); - return; - -ErrExit: - WdfRequestComplete(request, status); -} - -static void io_write_bar( - qdma_interface *qdma_dev, - qdma_bar_type bar_type, - const WDFREQUEST request, - const size_t length) -{ - WDF_REQUEST_PARAMETERS params; - WDF_REQUEST_PARAMETERS_INIT(¶ms); - WdfRequestGetParameters(request, ¶ms); - const auto offset = static_cast(params.Parameters.Write.DeviceOffset); - - /* get handle to the IO request memory which will hold the read data */ - WDFMEMORY request_mem; - - auto status = WdfRequestRetrieveInputMemory(request, &request_mem); - if (!NT_SUCCESS(status)) { - TraceError(TRACE_IO, "WdfRequestRetrieveOutputMemory failed: %!STATUS!", status); - goto ErrExit; - } - - /* get pointer to buffer */ - const auto req_buffer = WdfMemoryGetBuffer(request_mem, nullptr); - - status = qdma_dev->write_bar(bar_type, offset, req_buffer, length); - if (!NT_SUCCESS(status)) { - TraceError(TRACE_IO, "Writing PCIe BAR failed: %!STATUS!", status); - goto ErrExit; - } - - WdfRequestCompleteWithInformation(request, status, length); - return; - -ErrExit: - WdfRequestComplete(request, status); -} - -static BOOLEAN program_mm_dma_cb( - const WDFDMATRANSACTION transaction, - WDFDEVICE device, - WDFCONTEXT context, - const WDF_DMA_DIRECTION direction, - const PSCATTER_GATHER_LIST sg_list) -{ - auto dev_ctx = get_device_context(device); - DMA_TXN_CONTEXT *dma_ctx = (DMA_TXN_CONTEXT *)context; - const auto request = WdfDmaTransactionGetRequest(transaction); - WDF_REQUEST_PARAMETERS params; - WDF_REQUEST_PARAMETERS_INIT(¶ms); - WdfRequestGetParameters(request, ¶ms); - - const auto device_offset = (direction == WdfDmaDirectionWriteToDevice) ? - params.Parameters.Write.DeviceOffset : - params.Parameters.Read.DeviceOffset; - - auto status = dev_ctx->qdma->qdma_enqueue_mm_request(dma_ctx->qid, direction, sg_list, device_offset, drv_mm_cmp_cb, transaction); - if (!NT_SUCCESS(status)) { - dma_ctx->txn_len = 0; - /** Complete the DMA transaction */ - drv_mm_cmp_cb(transaction, status); - TraceError(TRACE_IO, "qdma_enqueue_mm_request() failed! %!STATUS!", status);; - return false; - } - - TraceVerbose(TRACE_IO, "qdma_enqueue_mm_request(): txd len : %lld", dma_ctx->txn_len); - - return true; -} - -static BOOLEAN program_st_tx_dma_cb( - WDFDMATRANSACTION transaction, - WDFDEVICE device, - const WDFCONTEXT context, - const WDF_DMA_DIRECTION direction, - const PSCATTER_GATHER_LIST sg_list) -{ - UNREFERENCED_PARAMETER(direction); - - auto dev_ctx = get_device_context(device); - DMA_TXN_CONTEXT *dma_ctx = (DMA_TXN_CONTEXT *)context; - - auto status = dev_ctx->qdma->qdma_enqueue_st_tx_request(dma_ctx->qid, sg_list, drv_st_tx_cmp_cb, transaction); - if (!NT_SUCCESS(status)) { - TraceError(TRACE_IO, "qdma_enqueue_st_tx_request() failed! %!STATUS!", status); - drv_st_tx_cmp_cb(transaction, status); - return false; - } - - TraceVerbose(TRACE_IO, "qdma_enqueue_st_tx_request(): txd len : %lld", dma_ctx->txn_len); - - return true; -} - - -static void io_mm_dma( - qdma_interface *qdma_dev, - UINT16 qid, - WDFREQUEST request, - const size_t length, - const WDF_DMA_DIRECTION direction) -{ - WDF_OBJECT_ATTRIBUTES attributes; - WDFDMATRANSACTION dma_transaction; - - WDF_OBJECT_ATTRIBUTES_INIT_CONTEXT_TYPE(&attributes, DMA_TXN_CONTEXT); - auto status = WdfDmaTransactionCreate(qdma_dev->dma_enabler, &attributes, &dma_transaction); - if (!NT_SUCCESS(status)) { - TraceError(TRACE_IO, "WdfDmaTransactionCreate() failed: %!STATUS!", status); - return; - } - - auto dma_ctx = get_dma_txn_context(dma_transaction); - dma_ctx->qid = qid; - dma_ctx->txn_len = length; - - /* initialize a DMA transaction from the request */ - status = WdfDmaTransactionInitializeUsingRequest(dma_transaction, - request, - program_mm_dma_cb, - direction); - if (!NT_SUCCESS(status)) { - TraceError(TRACE_IO, "WdfDmaTransactionInitializeUsingRequest failed: %!STATUS!", status); - goto ErrExit; - } - - status = WdfDmaTransactionExecute(dma_transaction, dma_ctx); - if (!NT_SUCCESS(status)) { - TraceError(TRACE_IO, "WdfDmaTransactionExecute failed: %!STATUS!", status); - goto ErrExit; - } - - TraceVerbose(TRACE_IO, "DMA transfer triggered on queue %d, direction : %d", qid, direction); - return; - -ErrExit: - WdfObjectDelete(dma_transaction); - WdfRequestComplete(request, status); - TraceError(TRACE_IO, "DMA transfer initiation failed, Request 0x%p: %!STATUS!", request, status); - -} - -static void io_st_read_dma( - qdma_interface *qdma_dev, - UINT16 qid, - WDFREQUEST request, - const size_t length) -{ - WDF_OBJECT_ATTRIBUTES attributes; - DMA_TXN_CONTEXT *dma_context = nullptr; - WDF_OBJECT_ATTRIBUTES_INIT_CONTEXT_TYPE(&attributes, DMA_TXN_CONTEXT); - - NTSTATUS status = WdfObjectAllocateContext(request, &attributes, (PVOID *)&dma_context); - dma_context->qid = qid; - dma_context->txn_len = length; - - status = qdma_dev->qdma_enqueue_st_rx_request(qid, length, drv_st_rx_cmp_cb, (void *)request); - if (!NT_SUCCESS(status)) { - WdfRequestComplete(request, status); - TraceError(TRACE_IO, "DMA transfer initiation failed: %!STATUS!", status); - } - - TraceVerbose(TRACE_IO, "DMA transfer triggered on queue %d", qid); -} - -static void io_st_zero_write_dma( - qdma_interface *qdma_dev, - UINT16 qid, - WDFREQUEST request, - const size_t length, - const WDF_DMA_DIRECTION direction) -{ - UNREFERENCED_PARAMETER(length); - UNREFERENCED_PARAMETER(direction); - - ST_DMA_ZERO_TX_PRIV *priv; - /** construct one element sg_list */ - constexpr size_t sg_list_len = sizeof(SCATTER_GATHER_LIST) + sizeof(SCATTER_GATHER_ELEMENT); - PSCATTER_GATHER_LIST sg_list; - - sg_list = (PSCATTER_GATHER_LIST)ExAllocatePoolWithTag(NonPagedPoolNx, sg_list_len, IO_QUEUE_TAG); - if (sg_list == NULL) { - TraceVerbose(TRACE_IO, "sg_list: Mem alloc failed\n"); - return; - } - - RtlZeroMemory(sg_list, sg_list_len); - - sg_list->NumberOfElements = 1; - sg_list->Elements[0].Address.QuadPart = NULL; - sg_list->Elements[0].Length = 0x0; - - priv = (ST_DMA_ZERO_TX_PRIV*)ExAllocatePoolWithTag(NonPagedPoolNx, sizeof(ST_DMA_ZERO_TX_PRIV), IO_QUEUE_TAG); - if (priv == NULL) { - ExFreePoolWithTag(sg_list, IO_QUEUE_TAG); - TraceVerbose(TRACE_IO, "priv: Mem alloc failed\n"); - return; - } - - /** Store the context info in priv data */ - priv->request = request; - priv->sg_list = sg_list; - - /* For Zero byte transfer, pass the ST_DMA_ZERO_TX_PRIV in WDFDMATRANSACTION parameter that contains, - locally constructed single element sglist parameter & WDFREQUEST for the function qdma_enqueue_st_request */ - auto status = qdma_dev->qdma_enqueue_st_tx_request(qid, sg_list, drv_st_tx_zcmp_cb, static_cast(priv)); - if (!NT_SUCCESS(status)) { - TraceError(TRACE_IO, "DMA transfer initiation failed! %!STATUS!", status); - drv_st_tx_zcmp_cb(priv, status); - return; - } - - TraceVerbose(TRACE_IO, "DMA transfer triggered on queue %d for zero length", qid); - return; -} - -static void io_st_write_dma( - qdma_interface *qdma_dev, - UINT16 qid, - WDFREQUEST request, - const size_t length, - const WDF_DMA_DIRECTION direction) -{ - WDF_OBJECT_ATTRIBUTES attributes; - WDFDMATRANSACTION dma_transaction; - - WDF_OBJECT_ATTRIBUTES_INIT_CONTEXT_TYPE(&attributes, DMA_TXN_CONTEXT); - auto status = WdfDmaTransactionCreate(qdma_dev->dma_enabler, &attributes, &dma_transaction); - if (!NT_SUCCESS(status)) { - TraceError(TRACE_IO, "WdfDmaTransactionCreate() failed: %!STATUS!", status); - WdfRequestComplete(request, status); - return; - } - - auto dma_ctx = get_dma_txn_context(dma_transaction); - if (!dma_ctx) { - goto ErrExit; - } - - dma_ctx->qid = qid; - dma_ctx->txn_len = length; - - /* initialize a DMA transaction from the request */ - status = WdfDmaTransactionInitializeUsingRequest(dma_transaction, - request, - program_st_tx_dma_cb, - direction); - if (!NT_SUCCESS(status)) { - TraceError(TRACE_IO, "WdfDmaTransactionInitializeUsingRequest failed: %!STATUS!", status); - goto ErrExit; - } - - status = WdfDmaTransactionExecute(dma_transaction, dma_ctx); - if (!NT_SUCCESS(status)) { - TraceError(TRACE_IO, "WdfDmaTransactionExecute failed: %!STATUS!", status); - goto ErrExit; - } - - TraceVerbose(TRACE_IO, "DMA transfer triggered on queue %d", qid); - return; - -ErrExit: - WdfObjectDelete(dma_transaction); - WdfRequestComplete(request, status); - TraceError(TRACE_IO, "DMA transfer initiation failed! for Request : %p, %!STATUS!", request, status); -} - -/* ----- CB Processing Functions ----- */ -void drv_st_rx_cmp_cb(const st_c2h_pkt_fragment *rx_pkts, size_t num_pkts, void *priv, NTSTATUS status) -{ - WDFREQUEST request = (WDFREQUEST)priv; - size_t offset = 0; - auto dma_ctx = get_dma_txn_context(request); - auto file_ctx = get_file_context(WdfRequestGetFileObject(request)); - - if (nullptr == file_ctx) { - status = STATUS_UNSUCCESSFUL; - goto ErrExit; - } - - if ((NT_SUCCESS(status))) { - if (dma_ctx->txn_len != (size_t)0) { - WDFMEMORY output_mem; - status = WdfRequestRetrieveOutputMemory(request, &output_mem); - if (!NT_SUCCESS(status)) { - TraceError(TRACE_IO, "WdfRequestRetrieveOutputMemory failed: %!STATUS!", status); - WdfRequestCompleteWithInformation(request, status, (size_t)0); - return; - } - - for (size_t i = 0; i < num_pkts; i++) { - st_c2h_pkt_fragment packet = rx_pkts[i]; - -#ifdef DBG - if (packet.udd_data != nullptr) { - UINT8 len = 0; - constexpr unsigned short MAX_UDD_STR_LEN = (QDMA_MAX_UDD_DATA_LEN * 3) + 1; - char imm_data_str[MAX_UDD_STR_LEN]; - UINT32 udd_len; - UINT8 udd_buffer[QDMA_MAX_UDD_DATA_LEN]; - WDFQUEUE io_queue = WdfRequestGetIoQueue(request); - if (io_queue) { - auto dev_ctx = get_device_context(WdfIoQueueGetDevice(io_queue)); - status = dev_ctx->qdma->qdma_retrieve_st_udd_data(dma_ctx->qid, packet.udd_data, udd_buffer, &udd_len); - - for (auto iter = 0UL; iter < udd_len; iter++) { - RtlStringCchPrintfA((imm_data_str + len), (MAX_UDD_STR_LEN - len), "%02X ", udd_buffer[iter]); - len = len + 3; /* 3 characters are getting utilized for each byte */ - } - TraceVerbose(TRACE_IO, "Immediate data Len : %d, Data: %s", udd_len, imm_data_str); - } - } -#endif - if ((packet.data) && (packet.length) && - (packet.pkt_type != st_c2h_pkt_type::ST_C2H_UDD_ONLY_PKT)) { - - if ((offset + packet.length) >= dma_ctx->txn_len) { - if (false == file_ctx->no_copy) - WdfMemoryCopyFromBuffer(output_mem, offset, packet.data, (dma_ctx->txn_len - offset)); - offset += (dma_ctx->txn_len - offset); - break; - } - else { - if (false == file_ctx->no_copy) - WdfMemoryCopyFromBuffer(output_mem, offset, packet.data, packet.length); - offset += packet.length; - } - } - } - } - - WdfRequestCompleteWithInformation(request, STATUS_SUCCESS, offset); - return; - } - -ErrExit: - WdfRequestCompleteWithInformation(request, status, (size_t)0); - - TraceVerbose(TRACE_IO, "ST C2H Request completed with %!STATUS!", status); -} - -static void dma_complete_transaction(WDFDMATRANSACTION dma_transaction, NTSTATUS status) -{ - NTSTATUS ret; - WDFREQUEST request = NULL; - BOOLEAN transaction_complete = false; - auto dma_ctx = get_dma_txn_context(dma_transaction); - size_t length = dma_ctx->txn_len; - UINT16 qid = dma_ctx->qid; - - request = WdfDmaTransactionGetRequest(dma_transaction); - if (!request) - /** Dont return from here, Need to delete the dma_transaction object */ - TraceError(TRACE_IO, "Callback triggered, No request pending on queue %d", qid); - - if ((NT_SUCCESS(status))) - transaction_complete = WdfDmaTransactionDmaCompleted(dma_transaction, &ret); - else - transaction_complete = WdfDmaTransactionDmaCompletedFinal(dma_transaction, length, &ret); - - if (transaction_complete) { - NT_ASSERT(status != STATUS_MORE_PROCESSING_REQUIRED); - WdfObjectDelete(dma_transaction); - } - else { - TraceError(TRACE_IO, "Err: DMA transaction not completed on queue %d, ret : %X", qid, ret); - } - - if (request) { - WdfRequestCompleteWithInformation(request, status, length); - TraceVerbose(TRACE_IO, "DMA transfer completed on queue %d, Len : %lld", qid, length); - } -} - -void drv_mm_cmp_cb(void *priv, NTSTATUS status) -{ - if (priv == nullptr) { - TraceError(TRACE_IO, "WDFDMATRANSACTION is NULL, Not possible to proceed"); - return; - } - - dma_complete_transaction(static_cast(priv), status); -} - -void drv_st_tx_cmp_cb(void *priv, NTSTATUS status) -{ - if (priv == nullptr) { - TraceError(TRACE_IO, "WDFDMATRANSACTION is NULL, Not possible to proceed"); - return; - } - - dma_complete_transaction(static_cast(priv), status); -} - -void drv_st_tx_zcmp_cb(void *priv, NTSTATUS status) -{ - if (priv == nullptr) { - TraceError(TRACE_IO, "WDFREQUEST is NULL, Not possible to proceed"); - return; - } - - ST_DMA_ZERO_TX_PRIV *priv_ctx = (ST_DMA_ZERO_TX_PRIV *)priv; - - WdfRequestCompleteWithInformation(static_cast(priv_ctx->request), status, 0); - - ExFreePoolWithTag(priv_ctx->sg_list, IO_QUEUE_TAG); - ExFreePoolWithTag(priv_ctx, IO_QUEUE_TAG); - - TraceInfo(TRACE_IO, "DMA Transfer completed for Zero length"); -} - -void drv_st_process_udd_only_pkts(UINT16 qid, void *udd_addr, void *priv) -{ - TraceVerbose(TRACE_IO, "UDD Only Call back function called, qid : %d, " - "udd_addr : %p, priv : %p\n", qid, udd_addr, priv); - -#ifdef DBG - if ((udd_addr == nullptr) || (priv == nullptr)) - return; - - UINT8 len = 0; - constexpr unsigned short MAX_UDD_STR_LEN = (QDMA_MAX_UDD_DATA_LEN * 3) + 1; - char imm_data_str[MAX_UDD_STR_LEN]; - UINT32 udd_len; - UINT8 udd_buffer[QDMA_MAX_UDD_DATA_LEN]; - qdma_interface *qdma_dev = (qdma_interface *)priv; - - NTSTATUS status = qdma_dev->qdma_retrieve_st_udd_data(qid, udd_addr, udd_buffer, &udd_len); - - if (NT_SUCCESS(status)) { - for (auto iter = 0UL; iter < udd_len; iter++) { - RtlStringCchPrintfA((imm_data_str + len), (MAX_UDD_STR_LEN - len), "%02X ", udd_buffer[iter]); - len = len + 3; /* 3 characters are getting utilized for each byte */ - } - - TraceInfo(TRACE_IO, "Immediate data Len : %d, Data: %s", udd_len, imm_data_str); - } -#endif -} - -NTSTATUS qdma_io_queue_initialize( - const WDFDEVICE device) -{ - PAGED_CODE(); - - TraceVerbose(TRACE_IO, "Initializing main entry IO queue"); - - /* Configure a default queue so that requests that are not configure-fowarded using - * WdfDeviceConfigureRequestDispatching to goto other queues get dispatched here. - */ - WDF_IO_QUEUE_CONFIG queue_config; - WDF_IO_QUEUE_CONFIG_INIT_DEFAULT_QUEUE(&queue_config, WdfIoQueueDispatchParallel); - queue_config.AllowZeroLengthRequests = true; - queue_config.EvtIoDeviceControl = qdma_evt_ioctl; - queue_config.EvtIoStop = qdma_evt_io_stop; - queue_config.EvtIoRead = qdma_evt_io_read; - queue_config.EvtIoWrite = qdma_evt_io_write; - - WDFQUEUE queue; - auto status = WdfIoQueueCreate(device, &queue_config, WDF_NO_OBJECT_ATTRIBUTES, &queue); - if (!NT_SUCCESS(status)) { - TraceError(TRACE_IO, "WdfIoQueueCreate failed %!STATUS!", status); - return status; - } - - return status; -} - -static NTSTATUS retrive_ioctl( - WDFREQUEST request, - PVOID ibuf, - size_t ibuf_len, - PVOID *obuf = nullptr, - size_t obuf_len = 0 -) -{ - PVOID in_buff = nullptr; - PVOID out_buff = nullptr; - size_t buff_len; - NTSTATUS status; - - if (ibuf != nullptr) { - status = WdfRequestRetrieveInputBuffer(request, ibuf_len, &in_buff, &buff_len); - if (!NT_SUCCESS(status)) { - TraceError(TRACE_IO, "WdfRequestRetrieveInputBuffer failed: %!STATUS!", status); - return status; - } - - if (ibuf_len != buff_len) { - TraceError(TRACE_IO, "input buffer length mismatch: %lld != %lld", ibuf_len, buff_len); - return STATUS_UNSUCCESSFUL; - } - - RtlCopyMemory(ibuf, in_buff, buff_len); - } - - if (obuf != nullptr) { - status = WdfRequestRetrieveOutputBuffer(request, obuf_len, &out_buff, &buff_len); - if (!NT_SUCCESS(status)) { - TraceError(TRACE_IO, "WdfRequestRetrieveOutputBuffer failed: %!STATUS!", status); - return STATUS_UNSUCCESSFUL; - } - - if (obuf_len != buff_len) { - TraceError(TRACE_IO, "output buffer length mismatch: %lld != %lld", obuf_len, buff_len); - return STATUS_UNSUCCESSFUL; - } - - *obuf = out_buff; - } - - return STATUS_SUCCESS; -} - -static NTSTATUS validate_ioctl_cmd( - ULONG io_control_code, - ioctl_cmd& cmd -) -{ - NTSTATUS status = STATUS_SUCCESS; - - switch (io_control_code) { - case IOCTL_QDMA_QUEUE_ADD: - if (cmd.q_conf.in.h2c_ring_sz_index >= QDMA_CSR_SZ) { - status = STATUS_INVALID_PARAMETER; - goto Exit; - } - if (cmd.q_conf.in.c2h_ring_sz_index >= QDMA_CSR_SZ) { - status = STATUS_INVALID_PARAMETER; - goto Exit; - } - if (cmd.q_conf.in.c2h_buff_sz_index >= QDMA_CSR_SZ) { - status = STATUS_INVALID_PARAMETER; - goto Exit; - } - if (cmd.q_conf.in.c2h_th_cnt_index >= QDMA_CSR_SZ) { - status = STATUS_INVALID_PARAMETER; - goto Exit; - } - if (cmd.q_conf.in.c2h_timer_cnt_index >= QDMA_CSR_SZ) { - status = STATUS_INVALID_PARAMETER; - goto Exit; - } - if (cmd.q_conf.in.compl_sz >= CMPT_DESC_SZ_MAX) { - status = STATUS_INVALID_PARAMETER; - goto Exit; - } - if (cmd.q_conf.in.trig_mode >= TRIG_MODE_MAX) { - status = STATUS_INVALID_PARAMETER; - goto Exit; - } - break; - case IOCTL_QDMA_QUEUE_DUMP_DESC: - if (cmd.desc_info.in.dir > queue_direction::QUEUE_DIR_C2H) { - status = STATUS_INVALID_PARAMETER; - goto Exit; - } - if (cmd.desc_info.in.desc_type > descriptor_type::CMPT_DESC) { - status = STATUS_INVALID_PARAMETER; - goto Exit; - } - break; - case IOCTL_QDMA_QUEUE_DUMP_CTX: - if (cmd.ctx_info.in.type > ring_type::RING_TYPE_CMPT) { - status = STATUS_INVALID_PARAMETER; - goto Exit; - } - break; - default: - /* default validation is success */ - break; - } - -Exit: - return status; -} - -void qdma_evt_ioctl( - WDFQUEUE queue, - WDFREQUEST request, - size_t output_buffer_length, - size_t input_buffer_length, - ULONG io_control_code) -{ - NTSTATUS status; - auto dev_ctx = get_device_context(WdfIoQueueGetDevice(queue)); - auto file_ctx = get_file_context(WdfRequestGetFileObject(request)); - auto qdma_dev = dev_ctx->qdma; - union ioctl_cmd cmd; - enum queue_state qstate; - - TraceVerbose(TRACE_IO, "Queue 0x%p, Request 0x%p OutputBufferLength %llu InputBufferLength %llu IoControlCode 0x%X", - queue, request, output_buffer_length, input_buffer_length, io_control_code); - - if (file_target::MGMT != file_ctx->target && file_target::ST_QUEUE != file_ctx->target) { - TraceError(TRACE_IO, "File target not supported"); - WdfRequestComplete(request, STATUS_UNSUCCESSFUL); - return; - } - - if (false == qdma_dev->qdma_is_device_online()) { - TraceError(TRACE_DEVICE, "QDMA Device is offline."); - WdfRequestComplete(request, STATUS_DEVICE_OFF_LINE); - return; - } - - RtlZeroMemory(&cmd, sizeof(cmd)); - switch (io_control_code) { - case IOCTL_QDMA_CSR_DUMP : - { - qdma_glbl_csr_conf conf = {}; - - status = retrive_ioctl(request, nullptr, 0, - (PVOID *)&cmd.csr.out, output_buffer_length); - if (!NT_SUCCESS(status)) - goto Exit; - - TraceVerbose(TRACE_IO, "IOCTL_QDMA_CSR_DUMP"); - status = qdma_dev->qdma_read_csr_conf(&conf); - if (!NT_SUCCESS(status)) - goto Exit; - - RtlCopyMemory(cmd.csr.out, &conf, sizeof(conf)); - - WdfRequestCompleteWithInformation(request, status, sizeof(qdma_glbl_csr_conf)); - break; - } - case IOCTL_QDMA_DEVINFO : - { - qdma_version_info version_info = {}; - - status = retrive_ioctl(request, nullptr, 0, - (PVOID *)&cmd.dev_info.out, output_buffer_length); - if (!NT_SUCCESS(status)) - goto Exit; - - TraceVerbose(TRACE_IO, "IOCTL_QDMA_DEVINFO"); - status = qdma_dev->qdma_device_version_info(version_info); - if (!NT_SUCCESS(status)) - goto Exit; - - device_info_out::version_info *ver_info = &cmd.dev_info.out->ver_info; - - RtlStringCchCopyNA(ver_info->qdma_rtl_version_str, - sizeof(ver_info->qdma_rtl_version_str), - version_info.qdma_rtl_version_str, - QDMA_VERSION_INFO_LENGTH); - - RtlStringCchCopyNA(ver_info->qdma_vivado_release_id_str, - sizeof(ver_info->qdma_vivado_release_id_str), - version_info.qdma_vivado_release_id_str, - QDMA_VERSION_INFO_LENGTH); - - RtlStringCchCopyNA(ver_info->qdma_device_type_str, - sizeof(ver_info->qdma_device_type_str), - version_info.qdma_device_type_str, - QDMA_VERSION_INFO_LENGTH); - - RtlStringCchCopyNA(ver_info->qdma_versal_ip_type_str, - sizeof(ver_info->qdma_versal_ip_type_str), - version_info.qdma_versal_ip_type_str, - QDMA_VERSION_INFO_LENGTH); - - RtlStringCchCopyNA(ver_info->qdma_sw_version, - sizeof(ver_info->qdma_sw_version), - version_info.qdma_sw_version_str, - QDMA_VERSION_INFO_LENGTH); - - qdma_device_attributes_info dev_attr = {}; - status = qdma_dev->qdma_get_dev_capabilities_info(dev_attr); - if (status != STATUS_SUCCESS) - goto Exit; - - cmd.dev_info.out->num_pfs = dev_attr.num_pfs; - cmd.dev_info.out->num_qs = dev_attr.num_qs; - cmd.dev_info.out->flr_present = dev_attr.flr_present; - cmd.dev_info.out->st_en = dev_attr.st_en; - cmd.dev_info.out->mm_en = dev_attr.mm_en; - cmd.dev_info.out->mm_cmpl_en = dev_attr.mm_cmpl_en; - cmd.dev_info.out->mailbox_en = dev_attr.mailbox_en; - cmd.dev_info.out->num_mm_channels = dev_attr.num_mm_channels; - cmd.dev_info.out->debug_mode = dev_attr.debug_mode; - cmd.dev_info.out->desc_eng_mode = dev_attr.desc_eng_mode; - - WdfRequestCompleteWithInformation(request, status, sizeof(device_info_out)); - - break; - } - case IOCTL_QDMA_QUEUE_ADD : - { - queue_config q_conf = {}; - - status = retrive_ioctl(request, - &cmd.q_conf.in, sizeof(cmd.q_conf.in)); - if (!NT_SUCCESS(status)) - goto Exit; - - status = validate_ioctl_cmd(io_control_code, cmd); - if (!NT_SUCCESS(status)) - goto Exit; - - q_conf.h2c_ring_sz_index = cmd.q_conf.in.h2c_ring_sz_index; - q_conf.c2h_ring_sz_index = cmd.q_conf.in.c2h_ring_sz_index; - q_conf.c2h_buff_sz_index = cmd.q_conf.in.c2h_buff_sz_index; - q_conf.c2h_th_cnt_index = cmd.q_conf.in.c2h_th_cnt_index; - q_conf.c2h_timer_cnt_index = cmd.q_conf.in.c2h_timer_cnt_index; - q_conf.is_st = cmd.q_conf.in.is_st; - - if (cmd.q_conf.in.trig_mode == trig_mode::TRIG_MODE_EVERY) - q_conf.trig_mode = qdma_trig_mode::QDMA_TRIG_MODE_EVERY; - else if (cmd.q_conf.in.trig_mode == trig_mode::TRIG_MODE_USER_COUNT) - q_conf.trig_mode = qdma_trig_mode::QDMA_TRIG_MODE_USER_COUNT; - else if (cmd.q_conf.in.trig_mode == trig_mode::TRIG_MODE_USER) - q_conf.trig_mode = qdma_trig_mode::QDMA_TRIG_MODE_USER; - else if (cmd.q_conf.in.trig_mode == trig_mode::TRIG_MODE_USER_TIMER) - q_conf.trig_mode = qdma_trig_mode::QDMA_TRIG_MODE_USER_TIMER; - else if (cmd.q_conf.in.trig_mode == trig_mode::TRIG_MODE_USER_TIMER_COUNT) - q_conf.trig_mode = qdma_trig_mode::QDMA_TRIG_MODE_USER_TIMER_COUNT; - else - q_conf.trig_mode = qdma_trig_mode::QDMA_TRIG_MODE_DISABLE; - - if (cmd.q_conf.in.compl_sz == cmpt_desc_sz::CMPT_DESC_SZ_8B) - q_conf.cmpt_sz = qdma_desc_sz::QDMA_DESC_SZ_8B; - else if (cmd.q_conf.in.compl_sz == cmpt_desc_sz::CMPT_DESC_SZ_16B) - q_conf.cmpt_sz = qdma_desc_sz::QDMA_DESC_SZ_16B; - else if (cmd.q_conf.in.compl_sz == cmpt_desc_sz::CMPT_DESC_SZ_32B) - q_conf.cmpt_sz = qdma_desc_sz::QDMA_DESC_SZ_32B; - else if (cmd.q_conf.in.compl_sz == cmpt_desc_sz::CMPT_DESC_SZ_64B) - q_conf.cmpt_sz = qdma_desc_sz::QDMA_DESC_SZ_64B; - - q_conf.desc_bypass_en = cmd.q_conf.in.desc_bypass_en; - q_conf.pfch_bypass_en = cmd.q_conf.in.pfch_bypass_en; - q_conf.pfch_en = cmd.q_conf.in.pfch_en; - q_conf.cmpl_ovf_dis = cmd.q_conf.in.cmpl_ovf_dis; - q_conf.sw_desc_sz = cmd.q_conf.in.sw_desc_sz; - q_conf.en_mm_cmpl = cmd.q_conf.in.en_mm_cmpl; - - if (q_conf.is_st) - q_conf.proc_st_udd_cb = drv_st_process_udd_only_pkts; - else - q_conf.proc_st_udd_cb = nullptr; - - TraceVerbose(TRACE_IO, "IOCTL_QDMA_QUEUE_ADD : %u", cmd.q_conf.in.qid); - - status = qdma_dev->qdma_add_queue(cmd.q_conf.in.qid, q_conf); - WdfRequestComplete(request, status); - break; - } - case IOCTL_QDMA_QUEUE_START : - { - status = retrive_ioctl(request, - &cmd.q_conf.in, sizeof(cmd.q_conf.in)); - if (!NT_SUCCESS(status)) - goto Exit; - - TraceVerbose(TRACE_IO, "IOCTL_QDMA_QUEUE_START : %u", - cmd.q_conf.in.qid); - status = qdma_dev->qdma_start_queue(cmd.q_conf.in.qid); - WdfRequestComplete(request, status); - break; - } - case IOCTL_QDMA_QUEUE_STOP : - { - status = retrive_ioctl(request, - &cmd.q_conf.in, sizeof(cmd.q_conf.in)); - if (!NT_SUCCESS(status)) - goto Exit; - - TraceVerbose(TRACE_IO, "IOCTL_QDMA_QUEUE_STOP : %u", cmd.q_conf.in.qid); - status = qdma_dev->qdma_stop_queue(cmd.q_conf.in.qid); - WdfRequestComplete(request, status); - break; - } - case IOCTL_QDMA_QUEUE_DELETE : - { - status = retrive_ioctl(request, - &cmd.q_conf.in, sizeof(cmd.q_conf.in)); - if (!NT_SUCCESS(status)) - goto Exit; - - TraceVerbose(TRACE_IO, "IOCTL_QDMA_QUEUE_DELETE : %u", cmd.q_conf.in.qid); - status = qdma_dev->qdma_remove_queue(cmd.q_conf.in.qid); - WdfRequestComplete(request, status); - break; - } - case IOCTL_QDMA_QUEUE_DUMP_STATE : - { - status = retrive_ioctl(request, - &cmd.q_state.in, sizeof(cmd.q_state.in), - (PVOID *)&cmd.q_state.out, output_buffer_length); - if (!NT_SUCCESS(status)) - goto Exit; - - status = validate_ioctl_cmd(io_control_code, cmd); - if (!NT_SUCCESS(status)) - goto Exit; - - if (cmd.q_state.out == nullptr) { - TraceError(TRACE_IO, "NULL Buffer for IOCTL_QDMA_QUEUE_DUMP_STATE"); - status = STATUS_INVALID_PARAMETER; - goto Exit; - } - - TraceVerbose(TRACE_IO, "IOCTL_QDMA_QUEUE_DUMP_STATE : %d", cmd.q_state.in.qid); - status = qdma_dev->qdma_get_queues_state(cmd.q_state.in.qid, &qstate, - cmd.q_state.out->state, sizeof(cmd.q_state.out->state)); - - if (!NT_SUCCESS(status)) - goto Exit; - - WdfRequestCompleteWithInformation(request, status, sizeof(queue_state_out)); - break; - } - case IOCTL_QDMA_QUEUE_READ_UDD : - { - status = retrive_ioctl(request, - &cmd.udd_info.in, sizeof(cmd.udd_info.in), - (PVOID *)&cmd.udd_info.out, output_buffer_length); - - if (!NT_SUCCESS(status)) - goto Exit; - - if (cmd.udd_info.out == nullptr) { - TraceError(TRACE_IO, "NULL Buffer for IOCTL_QDMA_QUEUE_DUMP_STATE"); - status = STATUS_INVALID_PARAMETER; - goto Exit; - } - - TraceVerbose(TRACE_IO, "IOCTL_QDMA_QUEUE_READ_UDD : %d", cmd.udd_info.in.qid); - - status = qdma_dev->qdma_retrieve_last_st_udd_data(cmd.udd_info.in.qid, - &cmd.udd_info.out->buffer[0], (UINT32 *)&cmd.udd_info.out->length); - - if (!NT_SUCCESS(status)) - goto Exit; - - WdfRequestCompleteWithInformation(request, status, sizeof(cmpt_udd_info_out)); - - break; - } - case IOCTL_QDMA_QUEUE_DUMP_DESC : - { - status = retrive_ioctl(request, - &cmd.desc_info.in, sizeof(cmd.desc_info.in), - (PVOID *)&cmd.desc_info.out, output_buffer_length); - if (!NT_SUCCESS(status)) - goto Exit; - - status = validate_ioctl_cmd(io_control_code, cmd); - if (!NT_SUCCESS(status)) - goto Exit; - - if (cmd.desc_info.out == nullptr) { - TraceError(TRACE_IO, "NULL Buffer for CMD_QUEUE_DUMP_DESC"); - status = STATUS_INVALID_PARAMETER; - goto Exit; - } - - qdma_desc_info desc_info; - - desc_info.qid = cmd.desc_info.in.qid; - desc_info.dir = (cmd.desc_info.in.dir == QUEUE_DIR_H2C) ? - qdma_queue_dir::QDMA_QUEUE_DIR_H2C : qdma_queue_dir::QDMA_QUEUE_DIR_C2H; - desc_info.desc_type = (cmd.desc_info.in.desc_type == RING_DESC) ? - qdma_desc_type::RING_DESCRIPTOR : qdma_desc_type::CMPT_DESCRIPTOR; - desc_info.desc_start = cmd.desc_info.in.desc_start; - desc_info.desc_end = cmd.desc_info.in.desc_end; - desc_info.buffer_sz = (UINT32)output_buffer_length - sizeof(struct desc_dump_info_out); - - desc_info.pbuffer = &cmd.desc_info.out->pbuffer[0]; - desc_info.desc_sz = 0; /* updated by qdma api desc_dump */ - desc_info.data_sz = 0; /* updated by qdma api desc_dump */ - - TraceVerbose(TRACE_IO, "IOCTL_QDMA_QUEUE_DUMP_DESC : %d", desc_info.qid); - - status = qdma_dev->qdma_queue_desc_dump(&desc_info); - if (!NT_SUCCESS(status)) { - TraceError(TRACE_IO, "qdma_dev->qdma_queue_desc_dump failed : Err : %X", status); - goto Exit; - } - - cmd.desc_info.out->desc_sz = desc_info.desc_sz; - cmd.desc_info.out->data_sz = desc_info.data_sz; - - WdfRequestCompleteWithInformation(request, status, - sizeof(desc_dump_info_out) + desc_info.data_sz); - - break; - } - case IOCTL_QDMA_QUEUE_DUMP_CTX : - { - status = retrive_ioctl(request, - &cmd.ctx_info.in, sizeof(cmd.ctx_info.in), - (PVOID *)&cmd.ctx_info.out, output_buffer_length); - if (!NT_SUCCESS(status)) - goto Exit; - - status = validate_ioctl_cmd(io_control_code, cmd); - if (!NT_SUCCESS(status)) - goto Exit; - - if (cmd.ctx_info.out == nullptr) { - TraceError(TRACE_IO, "NULL Buffer for CMD_QUEUE_DUMP_CTX"); - status = STATUS_INVALID_PARAMETER; - goto Exit; - } - - qdma_ctx_info ctx_info; - - ctx_info.qid = cmd.ctx_info.in.qid; - - if (cmd.ctx_info.in.type == ring_type::RING_TYPE_H2C) - ctx_info.ring_type = qdma_q_type::QDMA_Q_TYPE_H2C; - else if (cmd.ctx_info.in.type == ring_type::RING_TYPE_C2H) - ctx_info.ring_type = qdma_q_type::QDMA_Q_TYPE_C2H; - else if (cmd.ctx_info.in.type == ring_type::RING_TYPE_CMPT) - ctx_info.ring_type = qdma_q_type::QDMA_Q_TYPE_CMPT; - - ctx_info.buffer_sz = output_buffer_length - sizeof(struct ctx_dump_info_out); - ctx_info.pbuffer = &cmd.ctx_info.out->pbuffer[0]; - ctx_info.ret_sz = 0; - - TraceVerbose(TRACE_IO, "IOCTL_QDMA_QUEUE_DUMP_CTX : %d", ctx_info.qid); - /* Read context data */ - status = qdma_dev->qdma_queue_dump_context(&ctx_info); - if (!NT_SUCCESS(status)) { - TraceError(TRACE_IO, "qdma_dev->qdma_queue_dump_context failed, qid : %d : Err : %X", ctx_info.qid, status); - goto Exit; - } - - cmd.ctx_info.out->ret_sz = ctx_info.ret_sz; - - WdfRequestCompleteWithInformation(request, status, - sizeof(ctx_dump_info_out) + ctx_info.ret_sz); - break; - } - case IOCTL_QDMA_QUEUE_CMPT_READ : - { - status = retrive_ioctl(request, - &cmd.cmpt_info.in, sizeof(cmd.cmpt_info.in), - (PVOID *)&cmd.cmpt_info.out, output_buffer_length); - if (!NT_SUCCESS(status)) - goto Exit; - - if (cmd.cmpt_info.out == nullptr) { - TraceError(TRACE_IO, "NULL Buffer for CMD_QUEUE_CMPT_READ"); - status = STATUS_INVALID_PARAMETER; - goto Exit; - } - - qdma_cmpt_info cmpt_info; - - cmpt_info.qid = cmd.cmpt_info.in.qid; - cmpt_info.buffer_len = (UINT32)output_buffer_length - sizeof(struct cmpt_data_info_out); - - cmpt_info.pbuffer = &cmd.cmpt_info.out->pbuffer[0]; - cmpt_info.ret_len = 0; - cmpt_info.cmpt_desc_sz = 0; - - TraceVerbose(TRACE_IO, "IOCTL_QDMA_QUEUE_CMPT_READ : %d", cmpt_info.qid); - /* Read MM completion data */ - status = qdma_dev->qdma_read_mm_cmpt_data(&cmpt_info); - if (!NT_SUCCESS(status)) { - TraceError(TRACE_IO, "qdma_dev->qdma_read_mm_cmpt_data failed : Err : %X", status); - goto Exit; - } - - cmd.cmpt_info.out->ret_len = cmpt_info.ret_len; - cmd.cmpt_info.out->cmpt_desc_sz = cmpt_info.cmpt_desc_sz; - - WdfRequestCompleteWithInformation(request, status, - sizeof(cmpt_data_info_out) + cmpt_info.ret_len); - break; - } - case IOCTL_QDMA_INTRING_DUMP : - { - status = retrive_ioctl(request, - &cmd.int_ring_info.in, sizeof(cmd.int_ring_info.in), - (PVOID *)&cmd.int_ring_info.out, output_buffer_length); - if (!NT_SUCCESS(status)) - goto Exit; - - if (cmd.int_ring_info.out == nullptr) { - TraceError(TRACE_IO, "NULL Buffer for IOCTL_QDMA_INTRING_DUMP"); - status = STATUS_INVALID_PARAMETER; - goto Exit; - } - - qdma_intr_ring_info intring_info; - intring_info.vec_id = cmd.int_ring_info.in.vec_id; - intring_info.start_idx = cmd.int_ring_info.in.start_idx; - intring_info.end_idx = cmd.int_ring_info.in.end_idx; - intring_info.buffer_len = output_buffer_length - sizeof(struct intring_info_out); - - intring_info.ret_len = 0; - intring_info.ring_entry_sz = 0; - intring_info.pbuffer = &cmd.int_ring_info.out->pbuffer[0]; - - TraceVerbose(TRACE_IO, "IOCTL_QDMA_INTRING_DUMP : %d", intring_info.vec_id); - status = qdma_dev->qdma_intring_dump(&intring_info); - if (!NT_SUCCESS(status)) { - TraceError(TRACE_IO, "qdma_dev->qdma_intring_dump failed : Err : %X", status); - goto Exit; - } - - cmd.int_ring_info.out->ret_len = intring_info.ret_len; - cmd.int_ring_info.out->ring_entry_sz = intring_info.ring_entry_sz; - - WdfRequestCompleteWithInformation(request, status, - sizeof(intring_info_out) + intring_info.ret_len); - break; - } - case IOCTL_QDMA_REG_DUMP : - { - status = retrive_ioctl(request, nullptr, 0, - (PVOID *)&cmd.reg_dump_info.out, output_buffer_length); - if (!NT_SUCCESS(status)) - goto Exit; - - if (cmd.reg_dump_info.out == nullptr) { - TraceError(TRACE_IO, "NULL Buffer for CMD_REG_DUMP"); - status = STATUS_INVALID_PARAMETER; - goto Exit; - } - - qdma_reg_dump_info regdump_info; - - regdump_info.buffer_len = output_buffer_length - sizeof(struct regdump_info_out); - - regdump_info.ret_len = 0; - regdump_info.pbuffer = &cmd.reg_dump_info.out->pbuffer[0]; - - TraceVerbose(TRACE_IO, "IOCTL_QDMA_REG_DUMP"); - status = qdma_dev->qdma_regdump(®dump_info); - if (!NT_SUCCESS(status)) { - TraceError(TRACE_IO, "qdma_dev->qdma_regdump failed : Err : %X", status); - goto Exit; - } - - cmd.reg_dump_info.out->ret_len = regdump_info.ret_len; - - WdfRequestCompleteWithInformation(request, status, - sizeof(regdump_info_out) + regdump_info.ret_len); - break; - } - case IOCTL_QDMA_QUEUE_NO_COPY : - { - TraceInfo(TRACE_IO, "No Copy Set for QID : %u", file_ctx->qid); - file_ctx->no_copy = true; - WdfRequestComplete(request, STATUS_SUCCESS); - break; - } - case IOCTL_QDMA_SET_QMAX: - { - status = retrive_ioctl(request, &cmd.qmax_info.in, sizeof(cmd.qmax_info.in)); - if (!NT_SUCCESS(status)) - goto Exit; - - status = qdma_dev->qdma_set_qmax(cmd.qmax_info.in.qmax); - WdfRequestComplete(request, status); - break; - } - case IOCTL_QDMA_GET_QSTATS : - { - status = retrive_ioctl(request, nullptr, 0, - (PVOID *)&cmd.qstats_info.out, sizeof(struct qstat_out)); - if (!NT_SUCCESS(status)) - goto Exit; - - if (cmd.qstats_info.out == nullptr) { - TraceError(TRACE_IO, "nullptr Buffer for IOCTL_QDMA_GET_QSTATS"); - status = STATUS_INVALID_PARAMETER; - goto Exit; - } - - qdma_qstat_info qstats = { 0 }; - status = qdma_dev->qdma_get_qstats_info(qstats); - if (!NT_SUCCESS(status)) { - TraceError(TRACE_IO, "qdma_dev->qdma_get_qstats_info() failed : Err : %X", status); - goto Exit; - } - - cmd.qstats_info.out->qbase = qstats.qbase; - cmd.qstats_info.out->qmax = qstats.qmax; - cmd.qstats_info.out->active_h2c_queues = qstats.active_h2c_queues; - cmd.qstats_info.out->active_c2h_queues = qstats.active_c2h_queues; - cmd.qstats_info.out->active_cmpt_queues = qstats.active_cmpt_queues; - WdfRequestCompleteWithInformation(request, status, sizeof(struct qstat_out)); - break; - } - case IOCTL_QDMA_REG_INFO: - { - status = retrive_ioctl(request, &cmd.reg_info.in, sizeof(cmd.reg_info.in), - (PVOID*)&cmd.reg_info.out, output_buffer_length); - if (!NT_SUCCESS(status)) - goto Exit; - - if (cmd.reg_info.out == nullptr) { - TraceError(TRACE_IO, "nullptr Buffer for IOCTL_QDMA_REG_INFO"); - status = STATUS_INVALID_PARAMETER; - goto Exit; - } - - struct qdma_reg_info reg_info = { 0 }; - reg_info.bar_no = cmd.reg_info.in.bar_no; - reg_info.address = cmd.reg_info.in.address; - reg_info.reg_cnt = cmd.reg_info.in.reg_cnt; - reg_info.buf_len = output_buffer_length - sizeof(struct reg_info_out);; - reg_info.ret_len = 0; - reg_info.pbuffer = cmd.reg_info.out->pbuffer; - - status = qdma_dev->qdma_get_reg_info(®_info); - if (!NT_SUCCESS(status)) { - TraceError(TRACE_IO, "qdma_dev->qdma_get_reg_info() failed : Err : %X", status); - goto Exit; - } - - cmd.reg_info.out->ret_len = reg_info.ret_len; - - WdfRequestCompleteWithInformation(request, status, - sizeof(reg_info_out) + reg_info.ret_len); - break; - } - default: - TraceInfo(TRACE_IO, "UNKNOWN IOCTL CALLED"); - WdfRequestComplete(request, STATUS_UNSUCCESSFUL); - break; - } - - return; - -Exit: - WdfRequestComplete(request, status); -} - -void qdma_evt_io_stop( - WDFQUEUE queue, - WDFREQUEST request, - ULONG action_flags) -{ - TraceInfo(TRACE_IO, "Queue 0x%p, Request 0x%p ActionFlags %d", queue, request, action_flags); - - return; -} - -void qdma_evt_io_read( - const WDFQUEUE io_queue, - const WDFREQUEST request, - size_t length) -{ - auto status = STATUS_SUCCESS; - - auto dev_ctx = get_device_context(WdfIoQueueGetDevice(io_queue)); - auto file_ctx = get_file_context(WdfRequestGetFileObject(request)); - NT_ASSERT(dev_ctx != nullptr); - NT_ASSERT(file_ctx != nullptr); - - /* For Non ST mode, return success for zero length reads */ - if ((file_ctx->target != file_target::ST_QUEUE) && (length == 0)) { - WdfRequestComplete(request, STATUS_SUCCESS); - return; - } - - switch (file_ctx->target) { - case file_target::USER: - TraceVerbose(TRACE_IO, "AXI Master Lite BAR reading %llu bytes", length); - io_read_bar(dev_ctx->qdma, qdma_bar_type::USER_BAR, request, length); - break; - case file_target::CONTROL: - TraceVerbose(TRACE_IO, "control BAR reading %llu bytes", length); - io_read_bar(dev_ctx->qdma, qdma_bar_type::CONFIG_BAR, request, length); - break; - case file_target::BYPASS: - TraceVerbose(TRACE_IO, "AXI Bridge Master BAR reading %llu bytes", length); - io_read_bar(dev_ctx->qdma, qdma_bar_type::BYPASS_BAR, request, length); - break; - case file_target::DMA_QUEUE: - TraceVerbose(TRACE_IO, "queue_%u reading %llu bytes", file_ctx->qid, length); - io_mm_dma(dev_ctx->qdma, file_ctx->qid, request, length, - WdfDmaDirectionReadFromDevice); - break; - case file_target::ST_QUEUE: - TraceVerbose(TRACE_IO, "queue_%u reading %llu bytes", file_ctx->qid, length); - io_st_read_dma(dev_ctx->qdma, file_ctx->qid, request, length); - break; - default: - TraceError(TRACE_IO, "Unknown file target!"); - status = STATUS_INVALID_PARAMETER; - } - - if (!NT_SUCCESS(status)) { - WdfRequestComplete(request, status); - } -} - -void qdma_evt_io_write( - const WDFQUEUE io_queue, - const WDFREQUEST request, - size_t length) -{ - - auto status = STATUS_SUCCESS; - - auto dev_ctx = get_device_context(WdfIoQueueGetDevice(io_queue)); - auto file_ctx = get_file_context(WdfRequestGetFileObject(request)); - - NT_ASSERT(dev_ctx != nullptr); - NT_ASSERT(file_ctx != nullptr); - - /* For Non ST mode, return success for zero length writes */ - if ((file_ctx->target != file_target::ST_QUEUE) && (length == 0)) { - WdfRequestComplete(request, STATUS_SUCCESS); - return; - } - - switch (file_ctx->target) { - case file_target::USER: - TraceVerbose(TRACE_IO, "AXI Master Lite BAR writing %llu bytes", length); - io_write_bar(dev_ctx->qdma, qdma_bar_type::USER_BAR, request, length); - break; - case file_target::CONTROL: - TraceVerbose(TRACE_IO, "control BAR writing %llu bytes", length); - io_write_bar(dev_ctx->qdma, qdma_bar_type::CONFIG_BAR, request, length); - break; - case file_target::BYPASS: - TraceVerbose(TRACE_IO, "AXI Bridge Master BAR writing %llu bytes", length); - io_write_bar(dev_ctx->qdma, qdma_bar_type::BYPASS_BAR, request, length); - break; - case file_target::DMA_QUEUE: - TraceVerbose(TRACE_IO, "queue_%u writing %llu bytes", file_ctx->qid, length); - io_mm_dma(dev_ctx->qdma, file_ctx->qid, request, length, WdfDmaDirectionWriteToDevice); - break; - case file_target::ST_QUEUE: - TraceVerbose(TRACE_IO, "queue_%u writing %llu bytes", file_ctx->qid, length); - if (length == 0) { - io_st_zero_write_dma(dev_ctx->qdma, file_ctx->qid, request, length, WdfDmaDirectionWriteToDevice); - } - else { - io_st_write_dma(dev_ctx->qdma, file_ctx->qid, request, length, WdfDmaDirectionWriteToDevice); - } - break; - default: - TraceError(TRACE_IO, "Unknown file target!"); - status = STATUS_INVALID_PARAMETER; - } - - if (!NT_SUCCESS(status)) { - WdfRequestComplete(request, status); - } -} - -void qdma_evt_device_file_create( - const WDFDEVICE wdf_device, - const WDFREQUEST request, - const WDFFILEOBJECT wdf_file) -{ - auto status = STATUS_SUCCESS; - - auto file_name = WdfFileObjectGetFileName(wdf_file); - auto dev_ctx = get_device_context(wdf_device); - - /* no filename given? */ - NT_ASSERT(file_name != nullptr); - if (file_name->Buffer == nullptr) { - TraceError(TRACE_DEVICE, "no device file name given!"); - status = STATUS_INVALID_PARAMETER; - goto ErrExit; - } - - auto ctx = get_file_context(wdf_file); - NT_ASSERT(ctx != nullptr); - - ctx->target = parse_file_name(file_name); - if (ctx->target == file_target::UNKNOWN) { - TraceError(TRACE_DEVICE, "device file %wZ is not supported!", file_name); - status = STATUS_INVALID_PARAMETER; - goto ErrExit; - } - else if (ctx->target == file_target::DMA_QUEUE) { - ctx->qid = extract_index_token(file_name); - status = dev_ctx->qdma->qdma_is_queue_in_range(ctx->qid); - if (STATUS_SUCCESS != status) { - goto ErrExit; - } - TraceVerbose(TRACE_DEVICE, "MM qid=%u", ctx->qid); - } - else if (ctx->target == file_target::ST_QUEUE) { - /* get the qid number */ - ctx->qid = extract_index_token(file_name); - ctx->no_copy = false; - status = dev_ctx->qdma->qdma_is_queue_in_range(ctx->qid); - if (STATUS_SUCCESS != status) { - goto ErrExit; - } - TraceVerbose(TRACE_DEVICE, "ST qid=%u", ctx->qid); - } - - if (false == dev_ctx->qdma->qdma_is_device_online()) { - TraceError(TRACE_DEVICE, "QDMA Device is offline."); - status = STATUS_DEVICE_OFF_LINE; - } - - TraceVerbose(TRACE_DEVICE, "Opening file %wZ", file_name); - -ErrExit: - WdfRequestComplete(request, status); -} - -void qdma_evt_device_file_close( - const WDFFILEOBJECT wdf_file) -{ - PUNICODE_STRING file_name = WdfFileObjectGetFileName(wdf_file); - TraceVerbose(TRACE_DEVICE, "Closing file %wZ", file_name); -} - -void qdma_evt_device_file_cleanup( - const WDFFILEOBJECT wdf_file) -{ - PUNICODE_STRING file_name = WdfFileObjectGetFileName(wdf_file); - TraceVerbose(TRACE_DEVICE, "Cleanup %wZ", file_name); -} diff --git a/QDMA/windows/sys/drv/source/io_queue.h b/QDMA/windows/sys/drv/source/io_queue.h deleted file mode 100644 index 49617e59f..000000000 --- a/QDMA/windows/sys/drv/source/io_queue.h +++ /dev/null @@ -1,52 +0,0 @@ -/* - * Copyright (C) 2020 Xilinx, Inc - * - * Licensed under the Apache License, Version 2.0 (the "License"). You may - * not use this file except in compliance with the License. You may obtain - * a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - */ - -#pragma once - -#include "windows_common.h" -#include "qdma_exports.h" - -EXTERN_C_START - -using namespace xlnx; - -static constexpr ULONG IO_QUEUE_TAG = 'UQOI'; - -NTSTATUS qdma_io_queue_initialize(WDFDEVICE wdf_device); - -struct DMA_TXN_CONTEXT { - UINT16 qid; - size_t txn_len; -}; - -WDF_DECLARE_CONTEXT_TYPE_WITH_NAME(DMA_TXN_CONTEXT, get_dma_txn_context) - - -struct ST_DMA_ZERO_TX_PRIV { - WDFREQUEST request; - PVOID sg_list; -}; - -EVT_WDF_IO_QUEUE_IO_DEVICE_CONTROL qdma_evt_ioctl; -EVT_WDF_IO_QUEUE_IO_STOP qdma_evt_io_stop; -EVT_WDF_IO_QUEUE_IO_READ qdma_evt_io_read; -EVT_WDF_IO_QUEUE_IO_WRITE qdma_evt_io_write; - -EVT_WDF_DEVICE_FILE_CREATE qdma_evt_device_file_create; -EVT_WDF_FILE_CLOSE qdma_evt_device_file_close; -EVT_WDF_FILE_CLEANUP qdma_evt_device_file_cleanup; - -EXTERN_C_END diff --git a/QDMA/windows/sys/drv/source/trace.h b/QDMA/windows/sys/drv/source/trace.h deleted file mode 100644 index f999760ea..000000000 --- a/QDMA/windows/sys/drv/source/trace.h +++ /dev/null @@ -1,89 +0,0 @@ -/* - * Copyright (C) 2020 Xilinx, Inc - * - * Licensed under the Apache License, Version 2.0 (the "License"). You may - * not use this file except in compliance with the License. You may obtain - * a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - */ - -#pragma once - -#if defined(DBG) || defined(ENABLE_WPP) -#define ENABLE_WPP_TRACING -#endif - -/** - * Define the tracing flags. - * - * Tracing GUID - 0bed1f17-aa40-5163-c038-33715b81ae49 - * Trace Name : 'Xilinx-QDMA-Debug' - */ -#define WPP_CONTROL_GUIDS \ - WPP_DEFINE_CONTROL_GUID( \ - QDMATraceGuid, (0bed1f17, aa40, 5163, c038, 33715b81ae49), \ - \ - WPP_DEFINE_BIT(TRACE_PCIE) \ - WPP_DEFINE_BIT(TRACE_INTR) \ - WPP_DEFINE_BIT(TRACE_THREAD) \ - WPP_DEFINE_BIT(TRACE_QDMA) \ - WPP_DEFINE_BIT(TRACE_DBG) \ - WPP_DEFINE_BIT(TRACE_QDMA_ACCESS) \ - WPP_DEFINE_BIT(TRACE_DRIVER) \ - WPP_DEFINE_BIT(TRACE_DEVICE) \ - WPP_DEFINE_BIT(TRACE_IO) \ - ) - -/* WPP_LEVEL_FLAGS_LOGGER and WPP_LEVEL_FLAGS_ENABLED support trace functions - with LEVEL and FLAGS static parameters (in that order) prior to any dynamic - parameters (such as MSG) -*/ -#define WPP_LEVEL_FLAGS_LOGGER(level, flags) \ - WPP_LEVEL_LOGGER(flags) - -#define WPP_LEVEL_FLAGS_ENABLED(level, flags) \ - (WPP_LEVEL_ENABLED(flags) && WPP_CONTROL(WPP_BIT_ ## flags).Level >= level) - -/* Optimize WPP tracing call site conditional checks - - NOTE: This is only safe if we ensure no WPP tracing functions are called - before WPP_INIT_TRACING() or after WPP_CLEANUP(). -*/ -#define WPP_CHECK_INIT - - -// -// This comment block is scanned by the trace preprocessor to define our -// Trace functions. -// -// begin_wpp config -// FUNC TraceVerbose{LEVEL=TRACE_LEVEL_VERBOSE}(FLAGS, MSG, ...); -// FUNC TraceInfo{LEVEL=TRACE_LEVEL_INFORMATION}(FLAGS, MSG, ...); -// FUNC TraceWarning{LEVEL=TRACE_LEVEL_WARNING}(FLAGS, MSG, ...); -// FUNC TraceError{LEVEL=TRACE_LEVEL_ERROR}(FLAGS, MSG, ...); -// FUNC TraceEvents(LEVEL, FLAGS, MSG, ...); -// end_wpp -// - -/** WPP tracing is disabled by default in release configuration. - * so stub out definitions and functions - * - * To Enable WPP Tracing, Enable Run WPP Tracing in settings and - * define MACRO "ENABLE_WPP" - */ -#ifndef ENABLE_WPP_TRACING -#define WPP_INIT_TRACING(driver_object, registry_path) -#define WPP_CLEANUP(driver_object) -#define TraceVerbose(flags, ...) (__VA_ARGS__) -#define TraceInfo(flags, ...) (__VA_ARGS__) -#define TraceWarning(flags, ...) (__VA_ARGS__) -#define TraceError(flags, ...) (__VA_ARGS__) -#define TraceEvents(flags, ...) (__VA_ARGS__) -#endif diff --git a/QDMA/windows/sys/drv/source/windows_common.h b/QDMA/windows/sys/drv/source/windows_common.h deleted file mode 100644 index 834f00788..000000000 --- a/QDMA/windows/sys/drv/source/windows_common.h +++ /dev/null @@ -1,29 +0,0 @@ -/* - * Copyright (C) 2020 Xilinx, Inc - * - * Licensed under the Apache License, Version 2.0 (the "License"). You may - * not use this file except in compliance with the License. You may obtain - * a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - */ - -#pragma once - -#ifndef STRICT -#define STRICT -#endif - -#include -#include -#include -#include -#include -#include - diff --git a/QDMA/windows/sys/libqdma/include/qdma_exports.h b/QDMA/windows/sys/libqdma/include/qdma_exports.h deleted file mode 100644 index ab597a519..000000000 --- a/QDMA/windows/sys/libqdma/include/qdma_exports.h +++ /dev/null @@ -1,940 +0,0 @@ -/* - * Copyright (C) 2020 Xilinx, Inc - * - * Licensed under the Apache License, Version 2.0 (the "License"). You may - * not use this file except in compliance with the License. You may obtain - * a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - */ - -#pragma once - -#include - -/** - * @file - * @brief This file contains the declarations for libqdma interface structures - * - */ - -/* Xilinx namespace */ -namespace xlnx { - -class qdma_interface; -struct st_c2h_pkt_fragment; - -/** - * enum qdma_q_type: Q type - */ -enum qdma_q_type { - /** @QDMA_Q_TYPE_H2C: H2C Q */ - QDMA_Q_TYPE_H2C, - /** @QDMA_Q_TYPE_C2H: C2H Q */ - QDMA_Q_TYPE_C2H, - /** @QDMA_Q_TYPE_CMPT: CMPT Q */ - QDMA_Q_TYPE_CMPT, - /** @QDMA_Q_TYPE_MAX: Total Q types */ - QDMA_Q_TYPE_MAX -}; - -/** queue_state - State of the QDMA queue */ -enum queue_state { - /** Queue is available to configure */ - QUEUE_AVAILABLE, - /** Queue is added with resources */ - QUEUE_ADDED, - /** Queue is programmed and started */ - QUEUE_STARTED, - /** Queue critical operation is in progress */ - QUEUE_BUSY, - /** Invalid Queue State */ - QUEUE_INVALID_STATE -}; - -/** Streaming card to host packet type */ -enum class st_c2h_pkt_type { - /** C2H DATA Packet MACRO */ - ST_C2H_DATA_PKT, - /** C2H USER DEFINED DATA Packet MACRO */ - ST_C2H_UDD_ONLY_PKT, -}; - -/** qdma_queue_dir - QDMA Queue Direction */ -enum class qdma_queue_dir { - /** Queue H2C Direction */ - QDMA_QUEUE_DIR_H2C = 0, - /** Queue C2H Direction */ - QDMA_QUEUE_DIR_C2H -}; - -/** RING DESCRIPTOR TYPE */ -enum class qdma_desc_type { - /* Descriptor of type descriptor ring */ - RING_DESCRIPTOR = 0, - /* Descriptor of type completion ring */ - CMPT_DESCRIPTOR -}; - -/** DESCRIPTOR SIZE IN BYTES */ -enum class qdma_desc_sz { - /* Descriptor size of 8 bytes */ - QDMA_DESC_SZ_8B = 0, - /* Descriptor size of 16 bytes */ - QDMA_DESC_SZ_16B, - /* Descriptor size of 32 bytes */ - QDMA_DESC_SZ_32B, - /* Descriptor size of 64 bytes */ - QDMA_DESC_SZ_64B, - /* Descriptor size of invalid size */ - QDMA_DESC_SZ_MAX -}; - -/** Completion status trigger mode */ -enum class qdma_trig_mode { - /* Trigger disabled */ - QDMA_TRIG_MODE_DISABLE = 0, - /* Trigger on every update */ - QDMA_TRIG_MODE_EVERY, - /* Trigger on user count */ - QDMA_TRIG_MODE_USER_COUNT, - /* Trigger on user event */ - QDMA_TRIG_MODE_USER, - /* Trigger on user timer */ - QDMA_TRIG_MODE_USER_TIMER, - /* Trigger on user timer and count */ - QDMA_TRIG_MODE_USER_TIMER_COUNT, - /* Trigger invalid */ - QDMA_TRIG_MODE_MAX -}; - -/** queue_op_mode - QDMA Operation Mode */ -enum queue_op_mode { - /** Poll Mode */ - POLL_MODE = 0, - /** Direct Interrupt Mode */ - INTR_MODE, - /** Indirect Interrupt Mode(Aggregation) */ - INTR_COAL_MODE -}; - -/** qdma_bar_type - QDMA PCIe BAR Types */ -enum class qdma_bar_type { - /** QDMA Configuration BAR - * (Contains all QDMA configuration Registers) - */ - CONFIG_BAR, - /** QDMA AXI Master Lite BAR - * (Contains User Logic Registers) - */ - USER_BAR, - /** QDMA AXI Bridge Master BAR - * (Contains Bypass Registers to bypass QDMA) - */ - BYPASS_BAR -}; - -/** Specifies No of CSR Global Registers avalable */ -static constexpr size_t QDMA_GLBL_CSR_REG_CNT = 16; - -/** qdma_glbl_csr_conf - Provides the available CSR - * connfiguration registers - */ -struct qdma_glbl_csr_conf { - /** Ring Size CSR Registers */ - UINT32 ring_sz[QDMA_GLBL_CSR_REG_CNT]; - /** C2H Timer Count CSR Registers */ - UINT32 c2h_timer_cnt[QDMA_GLBL_CSR_REG_CNT]; - /** C2H Threshold CSR Registers */ - UINT32 c2h_th_cnt[QDMA_GLBL_CSR_REG_CNT]; - /** C2H Buffer size CSR Registers */ - UINT32 c2h_buff_sz[QDMA_GLBL_CSR_REG_CNT]; - /** Writeback interval timeout register */ - UINT32 wb_interval; -}; - -/** - * dma_completion_cb() - DMA Request completion callback function type - * - * @param[in] priv: Driver provided private member - * @param[in] status: DMA Request completion status - * - * @return void - */ -using dma_completion_cb = void(*)(void *priv, NTSTATUS status); - -/** - * st_rx_completion_cb() - Streaming C2H DMA Request completion callback function type - * - * @param[in] rx_frags: List of packet fragments - * @param[in] num_pkts: entries in rx_frags - * @param[in] priv: Driver provided private member - * @param[in] status: DMA Request completion status - * - * @return void - */ -using st_rx_completion_cb = void(*)(const st_c2h_pkt_fragment *rx_frags, size_t num_pkts, void *priv, NTSTATUS status); - -/** - * proc_st_udd_only_cb() - User defined data received callback function type - * - * @param[in] qid: Queue number - * @param[in] udd_addr: UDD pointer - * @param[in] priv: Driver provided private member - * - * @return void - */ -using proc_st_udd_only_cb = void(*)(UINT16 qid, void *udd_addr, void *priv); - -/** - * fp_user_isr_handler() - User defined user ISR handler - * - * @param[in] event_id: Event identifier - * @param[in] user_data: Driver provided user data - * - * @return void - */ -using fp_user_isr_handler = void(*)(ULONG event_id, void *user_data); - -/** - * fp_user_interrupt_enable_handler() - User defined user ISR handler - * - * @param[in] event_id: Event identifier - * @param[in] user_data: Driver provided user data - * - * @return void - */ -using fp_user_interrupt_enable_handler = void(*)(ULONG event_id, void *user_data); - -/** - * fp_user_interrupt_disable_handler() - User defined user ISR handler - * - * @param[in] event_id: Event identifier - * @param[in] user_data: Driver provided user data - * - * @return void - */ -using fp_user_interrupt_disable_handler = void(*)(ULONG event_id, void *user_data); - -/** dev_config - qdma device configuration - * needed to initialize the device - */ -struct qdma_drv_config { - /* Queue operation mode */ - queue_op_mode operation_mode; - - /* Config BAR index */ - UINT8 cfg_bar; - - /* Maximum queues for the device */ - UINT32 qsets_max; - - /* Maximum user MSIx vector to use */ - UINT16 user_msix_max; - - /* Maximum data MSIx vector to use */ - UINT16 data_msix_max; - - /* User data for user interrupt callback functions */ - void *user_data; - - /* User ISR handler */ - fp_user_isr_handler user_isr_handler; - - /* User interrupt enable handler */ - fp_user_interrupt_enable_handler user_interrupt_enable_handler; - - /* User interrupt disable handler */ - fp_user_interrupt_disable_handler user_interrupt_disable_handler; -}; - -/** queue_config - qdma queue configuration - * needed to add a queue - */ -struct queue_config { - /** queue is ST or MM */ - bool is_st; - /** H2C ring size index */ - UINT8 h2c_ring_sz_index; - /** C2H ring size index */ - UINT8 c2h_ring_sz_index; - /** C2H buffer size index */ - UINT8 c2h_buff_sz_index; - /** C2H threshold index */ - UINT8 c2h_th_cnt_index; - /** C2H timer count index */ - UINT8 c2h_timer_cnt_index; - /** completion ring size */ - qdma_desc_sz cmpt_sz; - /** trigger mode (valid for ST C2H) */ - qdma_trig_mode trig_mode; - /** Software descriptor size */ - UINT8 sw_desc_sz; - /** descriptor bypass enabled or not */ - bool desc_bypass_en; - /** prefetch enabled or not */ - bool pfch_en; - /** prefetch bypass enabled or not */ - bool pfch_bypass_en; - /** Completion overflow disabled or not */ - bool cmpl_ovf_dis; - /** MM completion enabled or not */ - bool en_mm_cmpl; - /** ST UDD data only call back function */ - proc_st_udd_only_cb proc_st_udd_cb; -}; - -/** st_c2h_pkt_fragment - C2H Packet Details */ -struct st_c2h_pkt_fragment { - /** C2H Data Fragment Address */ - void *data = nullptr; - /** User Defined Data Address */ - void *udd_data = nullptr; - /** Length of the C2H data Fragment */ - size_t length = 0; - /** Indicates Start of packet */ - UINT32 sop : 1; - /** Indicates End of packet */ - UINT32 eop : 1; - /** Indicates Packet Type (ST_C2H_DATA_PKT or ST_C2H_UDD_ONLY_PKT) */ - st_c2h_pkt_type pkt_type : 1; - /** Reserved Field */ - UINT32 reserved : 29; -}; - -/** qdma_device_attributes_info - Device Attributes/Features */ -struct qdma_device_attributes_info { - /** No of Physical functions supported */ - UINT8 num_pfs; - /** No of queues supported */ - UINT16 num_qs; - /** Function Level Reset Status */ - bool flr_present; - /** Streaming Feature enabled */ - bool st_en; - /** Memory Mapped Feature enabled */ - bool mm_en; - /** MM Completion Feature enabled */ - bool mm_cmpl_en; - /** Mailbox Feature enabled */ - bool mailbox_en; - /** Debug mode is enabled/disabled for IP */ - bool debug_mode; - /** Descriptor Engine mode: - * Internal only/Bypass only/Internal & Bypass - */ - UINT8 desc_eng_mode; - /** Number of MM channels supported */ - UINT16 num_mm_channels; -}; - -#define DEVICE_VERSION_INFO_STR_LENGTH 32 -/** qdma_version_info - QDMA HW and SW version information */ -struct qdma_version_info { - /** Version string */ - char qdma_rtl_version_str[DEVICE_VERSION_INFO_STR_LENGTH]; - /** Release string */ - char qdma_vivado_release_id_str[DEVICE_VERSION_INFO_STR_LENGTH]; - /** Qdma device type string*/ - char qdma_device_type_str[DEVICE_VERSION_INFO_STR_LENGTH]; - /** Versal IP state string*/ - char qdma_versal_ip_type_str[DEVICE_VERSION_INFO_STR_LENGTH]; - /** QDMA SW Version string*/ - char qdma_sw_version_str[DEVICE_VERSION_INFO_STR_LENGTH]; -}; - -/** qdma_desc_info - Structure contains required members to - * retrieve descriptor information - * - * The QDMA queue descriptor information will be copied into - * pbuffer for the requested qid, - * dir, desc_type from - * desc_start to desc_end into - * pbuffer. - * - * Caller must allocate memory for pbuffer and - * the size must be specified in buff_sz - * - * The driver specifies the actual length of data copied - * into pbuffer in data_sz field - * along with descriptor size in desc_sz. - * - */ -struct qdma_desc_info { - /** QID */ - UINT16 qid; - /** Q Direction (H2C, C2H) */ - qdma_queue_dir dir; - /** Descriptor Type (Ring Descriptor, Completion Descriptor) */ - qdma_desc_type desc_type; - /** Descriptor Start Index */ - UINT32 desc_start; - /** Descriptor End Index */ - UINT32 desc_end; - /** Data Buffer available size */ - size_t buffer_sz; - /** Data Buffer */ - UINT8 *pbuffer; - /** Size of the descriptor */ - size_t desc_sz; - /** Size of the data returned */ - size_t data_sz; -}; - -/** qdma_cmpt_info - Structure contains required members to - * retrieve completion ring information - * - * The QDMA MM completion ring data will be copied into - * pbuffer for the requested qid - * - * Caller must allocate memory for pbuffer and - * the size must be specified in buf_len - * - * The driver specifies the actual length of data copied - * into pbuffer in ret_len field - * along with completion descriptor size in cmpt_desc_sz. - * - */ -struct qdma_cmpt_info { - /** QID */ - UINT16 qid; - /** Data Buffer available size */ - size_t buffer_len; - /** Returned Data size */ - size_t ret_len; - /** Completion Descriptor size */ - size_t cmpt_desc_sz; - /** Buffer to hold Completion Descriptors */ - UINT8 *pbuffer; -}; - -/** qdma_ctx_info - Structure contains required members to - * retrieve QDMA queue context information - * - * The queue context information will be copied into - * pbuffer for the requested qid - * in the requested dir - * - * Caller must allocate memory for pbuffer and - * the size must be specified in buff_sz - * - * The driver specifies the actual length of data copied - * into pbuffer in ret_sz field. - */ -struct qdma_ctx_info { - /** QID */ - UINT16 qid; - /** Ring Type (H2C, C2H, CMPT) */ - enum qdma_q_type ring_type; - /** Data Buffer available size */ - size_t buffer_sz; - /** Returned Data size */ - size_t ret_sz; - /** Buffer to hold context information */ - char *pbuffer; -}; - -/** qdma_intr_ring_info - Structure contains required members to - * retrieve Interrupt ring information. - * - * The interrupt ring information will be copied into - * pbuffer from start_idx to - * end_idx for the requested vec_id - * - * Caller must allocate memory for pbuffer and - * the size must be specified in buf_len - * - * The driver specifies the actual length of data copied - * into pbuffer in ret_len field. - * - * The driver specifies the size of the ring entry in ring_entry_sz - */ -struct qdma_intr_ring_info { - /** Interrupt Vector ID */ - UINT32 vec_id; - /** Interrupt ring start index */ - UINT32 start_idx; - /** Interrupt ring end index */ - UINT32 end_idx; - /** Data Buffer available size */ - size_t buffer_len; - /** Returned Data size */ - size_t ret_len; - /** Size of the interrupt ring entry */ - size_t ring_entry_sz; - /** Buffer to hold interrupt ring information */ - unsigned char *pbuffer; -}; - -/** qdma_reg_dump_info - Structure contains required members to - * retrieve register dump information - * - * All the QDMA registers and its contents will be copied into - * pbuffer - * - * Caller must allocate memory for pbuffer and - * the size must be specified in buf_len - * - * The driver specifies the actual length of data copied - * into pbuffer in ret_len field. - */ -struct qdma_reg_dump_info { - /** Data Buffer available size */ - size_t buffer_len; - /** Returned Data size */ - size_t ret_len; - /** Buffer to hold regsiter dump information */ - char *pbuffer; -}; - -/** qdma_queue_stats - Structure contains required members to - * retrieve queue stats information - * - * All the queue statistics for this function is copied. - */ -struct qdma_qstat_info { - /** Queue base for this device */ - UINT32 qbase; - /** Maximum allocated queues for this device */ - UINT32 qmax; - /** Active host to card queues for this device */ - UINT32 active_h2c_queues; - /** Active card to host queues for this device */ - UINT32 active_c2h_queues; - /** Active completion queues for this device */ - UINT32 active_cmpt_queues; -}; - -/** qdma_reg_info - Structure contains required members to - * retrieve requested qdma registers information - */ -struct qdma_reg_info { - /** PCIe bar number */ - UINT32 bar_no; - /** Register address offset */ - UINT32 address; - /** number of registers to retrieve */ - UINT32 reg_cnt; - /** Length of the buffer pointed by pbuffer */ - size_t buf_len; - /** Length of the data present in pbuffer */ - size_t ret_len; - /** output buffer to copy the register info */ - char *pbuffer; -}; - -/** - * qdma_interface - libqdma interface class - * - * This class defines the interfaces that can be used while using - * the libqdma library. - */ -class qdma_interface { -public: - /** Handle to WDF DMA Enabler object to enable and start DMA operations */ - WDFDMAENABLER dma_enabler = nullptr; - - /*****************************************************************************/ - /** - * init() - Initializes the qdma device with operation mode and - * config bar number to use - * - * @param[in] conf: Device operation configuration - * - * @return STATUS_SUCCESS for success else error - *****************************************************************************/ - virtual NTSTATUS init(qdma_drv_config conf) = 0; - - /*****************************************************************************/ - /** - * open() - Prepares the qdma_device with all necessary information - * like allocating memory for resources, BAR mappings, - * Initializes the hardware structure, Initializes queues etc., - * - * @param[in] device: WDF Device - * @param[in] resources: Handle to WDF Framework raw - * HW resources list - * @param[in] resources_translated: Handle to WDF Framework translated - * HW resources list - * - * @return STATUS_SUCCESS for success else error - *****************************************************************************/ - virtual NTSTATUS open(WDFDEVICE device, WDFCMRESLIST resources, WDFCMRESLIST resources_translated) = 0; - - /*****************************************************************************/ - /** - * close() - Closes the QDMA device by freeing memory for resources, - * unmapping BARs, De-initializes the hardware structure, - * De-initializes queues etc., - * - * @return void - *****************************************************************************/ - virtual void close(void) = 0; - - /*****************************************************************************/ - /** - * qdma_is_device_online() - Checks if qdma device is ready for operations. - * - * @return true when device is online state. - * false when device is offline state. - *****************************************************************************/ - virtual bool qdma_is_device_online(void) = 0; - - /*****************************************************************************/ - /** - * read_bar() - Performs PCIe read operation on specified BAR number at - * requested offset of requested size - * - * @param[in] bar_type: BAR Type - * @param[in] offset: address offset to read the data from - * @param[out] data: data buffer to store the read data - * @param[in] size: size of the requested read operation(in bytes) - * - * @return STATUS_SUCCESS for success else error - *****************************************************************************/ - virtual NTSTATUS read_bar(qdma_bar_type bar_type, size_t offset, void* data, size_t size) = 0; - - /*****************************************************************************/ - /** - * write_bar() - Performs PCIe write operation on specified BAR number at - * requested offset of requested size - * - * @param[in] bar_type: BAR Type - * @param[in] offset: address offset to write the data to - * @param[in] data: data buffer contains the data bytes to write - * @param[in] size: size of the requested write operation(in bytes) - * - * @return STATUS_SUCCESS for success else error - *****************************************************************************/ - virtual NTSTATUS write_bar(qdma_bar_type bar_type, size_t offset, void* data, size_t size) = 0; - - /*****************************************************************************/ - /** - * write_bar() - Performs PCIe write operation on specified BAR number at - * requested offset of requested size - * - * @param[in] bar_type: BAR Type - * @param[out] bar_base: BAR base mapped address - * @param[out] bar_lenght: Bar length(in bytes) - * - * @return STATUS_SUCCESS for success else error - *****************************************************************************/ - virtual NTSTATUS get_bar_info(qdma_bar_type bar_type, PVOID &bar_base, size_t &bar_length) = 0; - - /*****************************************************************************/ - /** - * qdma_get_queues_state() - Retrieves the state of the specified queue - * - * @param[in] qid: queue id relative to this QDMA device - * @param[out] qstate: state of the queue specified as enumeration - * @param[out] state: state of the queue specified as character string - * @param[in] sz: size of the state character array - * - * @return STATUS_SUCCESS for success else error - *****************************************************************************/ - virtual NTSTATUS qdma_get_queues_state(UINT16 qid, enum queue_state *qstate, char *state, size_t sz) = 0; - - /*****************************************************************************/ - /** - * qdma_add_queue() - Configures the specified queue addition process with - * provided configuration - * - * @param[in] qid: queue id relative to this QDMA device - * @param[in] conf: configuration parameters for qid - * - * @return STATUS_SUCCESS for success else error - *****************************************************************************/ - virtual NTSTATUS qdma_add_queue(UINT16 qid, queue_config& conf) = 0; - - /*****************************************************************************/ - /** - * qdma_start_queue() - Starts the configured queue(qid) and the queue will be - * in operational state - * - * @param[in] qid: queue id relative to this QDMA device - * - * @return STATUS_SUCCESS for success else error - *****************************************************************************/ - virtual NTSTATUS qdma_start_queue(UINT16 qid) = 0; - - /*****************************************************************************/ - /** - * qdma_stop_queue() - Stops the queue(qid) and the queue will be - * in non operational state - * - * @param[in] qid: queue id relative to this QDMA device - * - * @return STATUS_SUCCESS for success else error - *****************************************************************************/ - virtual NTSTATUS qdma_stop_queue(UINT16 qid) = 0; - - /*****************************************************************************/ - /** - * qdma_remove_queue() - Removes the queue(qid) configuration and - * puts in available state for re-use - * - * @param[in] qid: queue id relative to this QDMA device - * - * @return STATUS_SUCCESS for success else error - *****************************************************************************/ - virtual NTSTATUS qdma_remove_queue(UINT16 qid) = 0; - - /*****************************************************************************/ - /** - * qdma_is_queue_in_range() - Validate qid of a queue for this device - * - * @param[in] qid: queue id relative to this QDMA device - * - * @return STATUS_SUCCESS for success else error - *****************************************************************************/ - virtual NTSTATUS qdma_is_queue_in_range(UINT16 qid) = 0; - - /*****************************************************************************/ - /** - * qdma_enqueue_mm_request() - enqueues an MM request into specified queue - * - * @param[in] qid: queue id relative to this QDMA device - * @param[in] direction: DMA direction (read or write) - * @param[in] sg_list: scatter-gather list of data buffers - * @param[in] device_offset: Device address to write/from read - * @param[in] compl_cb: completion call back function - * @param[in] priv: private data that gets passed to - * compl_cb function - * - * @return STATUS_SUCCESS for success else error - *****************************************************************************/ - virtual NTSTATUS qdma_enqueue_mm_request(UINT16 qid, WDF_DMA_DIRECTION direction, PSCATTER_GATHER_LIST sg_list, LONGLONG device_offset, dma_completion_cb compl_cb, VOID *priv) = 0; - - /*****************************************************************************/ - /** - * qdma_enqueue_st_tx_request() - enqueues an ST write request into specified queue - * - * @param[in] qid: queue id relative to this QDMA device - * @param[in] sg_list: scatter-gather list of data buffers - * @param[in,out] compl_cb: completion call back function - * to indicate write operation is completed - * @param[in,out] priv: private data that gets passed to - * compl_cb function - * - * @return STATUS_SUCCESS for success else error - *****************************************************************************/ - virtual NTSTATUS qdma_enqueue_st_tx_request(UINT16 qid, PSCATTER_GATHER_LIST sg_list, dma_completion_cb compl_cb, VOID *priv) = 0; - - /*****************************************************************************/ - /** - * qdma_enqueue_st_rx_request() - enqueues an ST read request into specified queue - * - * @param[in] qid: queue id relative to this QDMA device - * @param[in] length: desired data length to be received - * @param[in,out] compl_cb: completion call back function - * once data is available - * @param[in,out] priv: private data that gets passed to - * compl_cb function - * - * @return STATUS_SUCCESS for success else error - *****************************************************************************/ - virtual NTSTATUS qdma_enqueue_st_rx_request(UINT16 qid, size_t length, st_rx_completion_cb compl_cb, VOID *priv) = 0; - - /*****************************************************************************/ - /** - * qdma_retrieve_st_udd_data() - Retrieves the User Defined Data(side band data) - * from ST C2H descriptors - * - * @param[in] qid: queue id relative to this QDMA device - * @param[in] addr: UDD address in descriptor - * @param[out] buf: buffer to store user defined data - * @param[out] len: specifies the length of UDD in bytes - * - * @return STATUS_SUCCESS for success else error - *****************************************************************************/ - virtual NTSTATUS qdma_retrieve_st_udd_data(UINT16 qid, void *addr, UINT8 *buf, UINT32 *len) = 0; - - /*****************************************************************************/ - /** - * qdma_retrieve_last_st_udd_data() - Retrieves the User Defined Data - * (side band data) from ST C2H descriptors - * that can be consumed in driver - * - * @param[in] qid: queue id relative to this QDMA device - * @param[out] buf: buffer to store user defined data - * @param[out] len: specifies the length of UDD in bytes - * - * @return STATUS_SUCCESS for success else error - *****************************************************************************/ - virtual NTSTATUS qdma_retrieve_last_st_udd_data(UINT16 qid, UINT8 *buf, UINT32 *len) = 0; - - /*****************************************************************************/ - /** - * qdma_queue_desc_dump() - Retrieves the descriptors data into desc_info - * - * @param[in,out] desc_info: pointer to qdma_desc_info - * - * @return STATUS_SUCCESS for success else error - *****************************************************************************/ - virtual NTSTATUS qdma_queue_desc_dump(qdma_desc_info *desc_info) = 0; - - /*****************************************************************************/ - /** - * qdma_read_mm_cmpt_data() - Retrieves the User Defined Data(side band data) - * from MM write back ring (if HW support available) - * - * @param[in,out] cmpt_info: user defined data(completion) information - * - * @return STATUS_SUCCESS for success else error - *****************************************************************************/ - virtual NTSTATUS qdma_read_mm_cmpt_data(qdma_cmpt_info *cmpt_info) = 0; - - /*****************************************************************************/ - /** - * qdma_queue_dump_context() - Dumps the queue context information of given - * direction - * - * @param[in,out] ctx_info: context information structure - * - * @return STATUS_SUCCESS for success else error - *****************************************************************************/ - virtual NTSTATUS qdma_queue_dump_context(qdma_ctx_info *ctx_info) = 0; - - /*****************************************************************************/ - /** - * qdma_intring_dump() - Dumps the interrupt ring context information of given - * vector ID from start index to end index - * - * @param[in,out] intring_info: interrupt ring context information - * - * @return STATUS_SUCCESS for success else error - *****************************************************************************/ - virtual NTSTATUS qdma_intring_dump(qdma_intr_ring_info *intring_info) = 0; - - /*****************************************************************************/ - /** - * qdma_regdump() - Dumps all the QDMA registers to given buffer - * - * @param[in,out] regdump_info: Register dump information - * - * @return STATUS_SUCCESS for success else error - *****************************************************************************/ - virtual NTSTATUS qdma_regdump(qdma_reg_dump_info *regdump_info) = 0; - - /*****************************************************************************/ - /** - * qdma_read_csr_conf() - Retrieves the CSR registers information - * - * @param[out] conf: CSR registers information - * - * @return STATUS_SUCCESS for success else error - *****************************************************************************/ - virtual NTSTATUS qdma_read_csr_conf(qdma_glbl_csr_conf *conf) = 0; - - /*****************************************************************************/ - /** - * qdma_get_dev_capabilities_info() - Retrieves the HW device features info - * - * @param[out] dev_attr: HW device attributes - * - * @return STATUS_SUCCESS for success else error - *****************************************************************************/ - virtual NTSTATUS qdma_get_dev_capabilities_info(qdma_device_attributes_info &dev_attr) = 0; - - /*****************************************************************************/ - /** - * qdma_device_version_info() - Retrieves the QDMA HW and SW versions - * in character array format - * - * @param[out] version_info: HW & SW versions information in character - * array format - * - * @return STATUS_SUCCESS for success else error - *****************************************************************************/ - virtual NTSTATUS qdma_device_version_info(qdma_version_info &version_info) = 0; - - /*****************************************************************************/ - /** - * qdma_set_qmax() - Set maximum queues number for this QDMA function. - * - * @param[in] qmax: Maximum number of queues for this function. - * - * @return STATUS_SUCCESS for success else error - *****************************************************************************/ - virtual NTSTATUS qdma_set_qmax(UINT32 qmax) = 0; - - /*****************************************************************************/ - /** - * qdma_get_qstats_info() - Retrieves the QDMA statistics for queue resources - * - * @param[out] qstats: Total queues for function with occupied H2C, C2H and - * CMPT queues count. - * - * @return STATUS_SUCCESS for success else error - *****************************************************************************/ - virtual NTSTATUS qdma_get_qstats_info(qdma_qstat_info &qstats) = 0; - - /*****************************************************************************/ - /** - * qdma_get_reg_info() - Retrieves the requested QDMA registers information - * - * @param[out] reg_info: Register information (Address, Len, etc.,) - * - * @return STATUS_SUCCESS for success else error - *****************************************************************************/ - virtual NTSTATUS qdma_get_reg_info(qdma_reg_info* reg_info) = 0; - - /*****************************************************************************/ - /** - * create_qdma_device() - Allocates an instance for qdma device - * - * @return Address of qdma_interface class or NULL in case of error - *****************************************************************************/ - static qdma_interface* create_qdma_device(void); - - /*****************************************************************************/ - /** - * remove_qdma_device() - frees the allocated instance for qdma_device - * - * @param[in] qdma_dev: address of the qdma_device instance - * - * @return void - *****************************************************************************/ - static void remove_qdma_device(qdma_interface *qdma_dev); - - /// @cond - /*****************************************************************************/ - /** - * new - Overloaded new operator to allocate the memory - * - * @param[in] num_bytes: number of bytes of memory to allocate - * - * @return void * - *****************************************************************************/ - _IRQL_requires_max_(PASSIVE_LEVEL) - void *operator new(_In_ size_t num_bytes); - - /*****************************************************************************/ - /** - * delete - Overloaded delete operator to free the memory - * - * @param[in] addr: address of the memory - * - * @return void - *****************************************************************************/ - _IRQL_requires_max_(PASSIVE_LEVEL) - void operator delete(_In_ void *addr); - - /*****************************************************************************/ - /** - * ~qdma_interface() - destructor - * - * @return void - *****************************************************************************/ - virtual ~qdma_interface() {} - /// @endcond -}; - -} -#include diff --git a/QDMA/windows/sys/libqdma/include/xversion.hpp b/QDMA/windows/sys/libqdma/include/xversion.hpp deleted file mode 100644 index 86f8f8aeb..000000000 --- a/QDMA/windows/sys/libqdma/include/xversion.hpp +++ /dev/null @@ -1,75 +0,0 @@ -/* - * Copyright (C) 2020 Xilinx, Inc - * - * Licensed under the Apache License, Version 2.0 (the "License"). You may - * not use this file except in compliance with the License. You may obtain - * a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - */ - -#pragma once - -/** Product Version (common.ver resources compatible) ***********************/ - -#undef VER_PRODUCTMAJORVERSION -#define VER_PRODUCTMAJORVERSION (2020) -#undef VER_PRODUCTMINORVERSION -#define VER_PRODUCTMINORVERSION (2) -#undef VER_PRODUCTREVISION -#define VER_PRODUCTREVISION (0) -#undef VER_PRODUCTBUILD -#define VER_PRODUCTBUILD (0) - -/** Company Details *********************************************************/ - -#undef VER_COMPANYNAME_STR -#define VER_COMPANYNAME_STR "Xilinx, Inc." - -/** Copyright Details *******************************************************/ - -#undef VER_LEGALCOPYRIGHT_YEARS -#define VER_LEGALCOPYRIGHT_YEARS "2019-2020" -#undef VER_LEGALCOPYRIGHT_STR_WITH_YEARS -#define VER_LEGALCOPYRIGHT_STR_WITH_YEARS \ - "Copyright 2019-2020 Xilinx, Inc." -#undef VER_LEGALCOPYRIGHT_STR -#if defined(RC_INVOKED) -#define VER_LEGALCOPYRIGHT_STR \ - "\251 Copyright Xilinx, Inc. All rights reserved." -#else -#define VER_LEGALCOPYRIGHT_STR \ - "(c) Copyright Xilinx, Inc. All rights reserved." -#endif - -/** Product Details *********************************************************/ - -#undef VER_PRODUCTNAME_STR -#define VER_PRODUCTNAME_STR \ - "Xilinx PCIe Multi-Queue-DMA Reference Driver" - -// Version number (in format needed for version resources) -#undef VER_PRODUCTVERSION -#define VER_PRODUCTVERSION 2020,2,0,0 - -// Version number string -#undef VER_PRODUCTVERSION_STR -#define VER_PRODUCTVERSION_STR "2020.2.0.0" - -/** File Details ************************************************************/ - -// Default file version to be the same as product version -#define VER_FILEVERSION VER_PRODUCTVERSION -#define VER_FILEVERSION_STR VER_PRODUCTVERSION_STR - -// Default to language-independent software -#define VER_LANGNEUTRAL - -// Don't append a build machine tag to the file version string -#undef __BUILDMACHINE__ diff --git a/QDMA/windows/sys/libqdma/libqdma.vcxproj b/QDMA/windows/sys/libqdma/libqdma.vcxproj deleted file mode 100644 index f059ff241..000000000 --- a/QDMA/windows/sys/libqdma/libqdma.vcxproj +++ /dev/null @@ -1,229 +0,0 @@ - - - - - Debug - Win32 - - - Release - Win32 - - - Debug - x64 - - - Release - x64 - - - - {359143E6-933A-49CC-806C-C5376E1809A4} - {497e31cb-056b-4f31-abb8-447fd55ee5a5} - - - 12.0 - Debug - Win32 - MDMA - libqdma - $(LatestTargetPlatformVersion) - - - - Windows10 - true - WindowsKernelModeDriver10.0 - Driver - KMDF - Desktop - true - 1 - false - - - Windows10 - false - WindowsKernelModeDriver10.0 - Driver - KMDF - Desktop - true - 1 - false - - - Windows10 - true - WindowsKernelModeDriver10.0 - StaticLibrary - KMDF - Desktop - true - 1 - false - - - Windows10 - false - WindowsKernelModeDriver10.0 - StaticLibrary - KMDF - Desktop - true - 1 - false - - - - - - - - - - - DbgengKernelDebugger - $(SolutionDir)build\$(Platform)\$(ConfigurationName)\sys\ - $(SolutionDir).tmp\$(Platform)\$(ConfigurationName)\$(ProjectName)\ - QDMA - - - DbgengKernelDebugger - $(SolutionDir)build\$(Platform)\$(ConfigurationName)\sys\ - $(SolutionDir).tmp\$(Platform)\$(ConfigurationName)\$(ProjectName)\ - QDMA - - - DbgengKernelDebugger - $(SolutionDir)build\$(Platform)\$(ConfigurationName)\libqdma\ - QDMA - $(SolutionDir).tmp\$(Platform)\$(ConfigurationName)\$(ProjectName)\ - .lib - - - DbgengKernelDebugger - $(SolutionDir)build\$(Platform)\$(ConfigurationName)\libqdma\ - $(SolutionDir).tmp\$(Platform)\$(ConfigurationName)\$(ProjectName)\ - QDMA - .lib - - - - true - false - include\trace.h - true - CompileAsCpp - false - $(ProjectDir)\..\libqdma\include;$(ProjectDir)\include;%(AdditionalIncludeDirectories) - qdma - stdcpp17 - false - - - - - - - false - false - include\trace.h - true - CompileAsCpp - false - $(ProjectDir)\..\libqdma\include;$(ProjectDir)\include;%(AdditionalIncludeDirectories) - qdma - stdcpp17 - - - - - - - - - true - false - source\trace.h - true - CompileAsCpp - false - $(ProjectDir)\include\;$(ProjectDir)\source\;$(ProjectDir)\source\qdma_access\;$(ProjectDir)\source\qdma_access\eqdma_soft_access;$(ProjectDir)\source\qdma_access\qdma_soft_access;$(ProjectDir)\source\qdma_access\qdma_s80_hard_access;%(AdditionalIncludeDirectories) - true - qdma - stdcpp17 - false - $(ExternalCompilerOptions) %(AdditionalOptions) - - - - - - - false - false - source\trace.h - true - CompileAsCpp - false - $(ProjectDir)\include\;$(ProjectDir)\source\;$(ProjectDir)\source\qdma_access\;$(ProjectDir)\source\qdma_access\eqdma_soft_access;$(ProjectDir)\source\qdma_access\qdma_soft_access;$(ProjectDir)\source\qdma_access\qdma_s80_hard_access;%(AdditionalIncludeDirectories) - qdma - stdcpp17 - $(ExternalCompilerOptions) %(AdditionalOptions) - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - \ No newline at end of file diff --git a/QDMA/windows/sys/libqdma/libqdma.vcxproj.filters b/QDMA/windows/sys/libqdma/libqdma.vcxproj.filters deleted file mode 100644 index ac01025ef..000000000 --- a/QDMA/windows/sys/libqdma/libqdma.vcxproj.filters +++ /dev/null @@ -1,129 +0,0 @@ - - - - - {e1da9a0a-858f-49d8-bf70-e04880baf8b3} - - - {6c2a1f5c-8444-46b2-95e9-8c53ee5ab032} - - - - - Header Files - - - Header Files - - - Header Files - - - Header Files - - - Header Files - - - Header Files - - - Header Files - - - Header Files - - - Header Files - - - Header Files - - - Header Files - - - Header Files - - - Header Files - - - Header Files - - - Header Files - - - Header Files - - - Header Files - - - Header Files - - - Header Files - - - Header Files - - - Header Files - - - Header Files - - - Header Files - - - Header Files - - - Header Files - - - - - Source Files - - - Source Files - - - Source Files - - - Source Files - - - Source Files - - - Source Files - - - Source Files - - - Source Files - - - Source Files - - - Source Files - - - Source Files - - - Source Files - - - Source Files - - - \ No newline at end of file diff --git a/QDMA/windows/sys/libqdma/libqdma.vcxproj.user b/QDMA/windows/sys/libqdma/libqdma.vcxproj.user deleted file mode 100644 index a667f8f86..000000000 --- a/QDMA/windows/sys/libqdma/libqdma.vcxproj.user +++ /dev/null @@ -1,36 +0,0 @@ - - - - False - None - - - C:\Program Files (x86)\Windows Kits\10\Testing\Tests\Utilities\DefaultDriverPackageInstallationTask.dll - XIRIPDSLAB20 - XIRIPDSLAB20 - - Microsoft.DriverKit.DefaultDriverPackageInstallationClass.PerformDefaultDriverPackageInstallation - - True - False - True - - 133563 - FvOn - DbgengRemoteDebugger - - - - - - - - - - - - - - - - \ No newline at end of file diff --git a/QDMA/windows/sys/libqdma/source/interrupts.cpp b/QDMA/windows/sys/libqdma/source/interrupts.cpp deleted file mode 100644 index 581c8c46b..000000000 --- a/QDMA/windows/sys/libqdma/source/interrupts.cpp +++ /dev/null @@ -1,947 +0,0 @@ -/* - * Copyright (C) 2020 Xilinx, Inc - * - * Licensed under the Apache License, Version 2.0 (the "License"). You may - * not use this file except in compliance with the License. You may obtain - * a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - */ - -#include "qdma.h" -#include "interrupts.hpp" -#include "trace.h" - -#ifdef ENABLE_WPP_TRACING -#include "interrupts.tmh" -#endif - -using namespace xlnx; - -/* ------- Interrupt Queue ------- */ -NTSTATUS intr_queue::create( - WDFDMAENABLER& dma_enabler) -{ - auto buffer_size = size * sizeof(intr_entry); - - /* Align to page size */ - if (buffer_size % PAGE_SIZE) { - buffer_size = ((buffer_size / PAGE_SIZE) + 1) * PAGE_SIZE; - } - - TraceVerbose(TRACE_INTR, "%s: Intr Queue : %d, Buffer size : %llu, Ring size : %llu", - qdma->dev_conf.name, idx_abs, buffer_size, size); - - capacity = buffer_size / sizeof(intr_entry); - npages = buffer_size / PAGE_SIZE; - color = 1; - - TraceVerbose(TRACE_INTR, "Intr Queue : %d, Page size : %llu, Capacity : %llu", - idx_abs, npages, capacity); - - auto status = WdfCommonBufferCreate(dma_enabler, - buffer_size, - WDF_NO_OBJECT_ATTRIBUTES, - &buffer); - if (!NT_SUCCESS(status)) { - TraceError(TRACE_INTR, "%s: Interrupt WdfCommonBufferCreate failed for " - "intr queue : %d, : %!STATUS!", qdma->dev_conf.name, idx_abs, status); - return status; - } - - buffer_va = static_cast(WdfCommonBufferGetAlignedVirtualAddress(buffer)); - - clear_contents(); - - return status; -} - -void intr_queue::clear_contents(void) -{ - auto buffer_size = size * sizeof(intr_entry); - RtlZeroMemory(buffer_va, buffer_size); - sw_index = 0; - intr_cidx_info.rng_idx = 0; - intr_cidx_info.sw_cidx = 0; -} - -void intr_queue::advance_sw_index(void) -{ - ++sw_index; - - if (sw_index == capacity) { - sw_index = 0; - /* Flip the color */ - color = color ? 0 : 1; - } -} - -PFORCEINLINE void intr_queue::update_csr_cidx( - queue_pair *q, - UINT32 new_cidx) -{ - TraceVerbose(TRACE_INTR, "%s: Intr queue_%u updating c2h pidx to %u", qdma->dev_conf.name, idx, new_cidx); - intr_cidx_info.rng_idx = (UINT8)idx_abs; - intr_cidx_info.sw_cidx = (UINT16)new_cidx; - - qdma->hw.qdma_queue_intr_cidx_update(qdma, false /* is_vf */, q->idx, &intr_cidx_info); -} - -NTSTATUS intr_queue::intring_dump(qdma_intr_ring_info *intring_info) -{ - size_t len; - size_t buf_idx; - size_t ring_entry_sz; - UINT8 *ring_buff_addr; - UINT8 *buf = intring_info->pbuffer; - size_t buf_len = intring_info->buffer_len; - - if ((intring_info->start_idx >= size) || - (intring_info->end_idx >= size)) { - TraceError(TRACE_INTR, "%s: Intr Ring index Range is incorrect : start : %d, end : %d, RING SIZE : %d", - qdma->dev_conf.name, intring_info->start_idx, intring_info->end_idx, size); - return STATUS_ACCESS_VIOLATION; - } - - ring_entry_sz = sizeof(intr_entry); - intring_info->ring_entry_sz = ring_entry_sz; - if (intring_info->start_idx <= intring_info->end_idx) { - len = ((size_t)intring_info->end_idx - (size_t)intring_info->start_idx + 1) * ring_entry_sz; - len = min(len, buf_len); - buf_idx = intring_info->start_idx * ring_entry_sz; - ring_buff_addr = &((UINT8 *)buffer_va)[buf_idx]; - RtlCopyMemory(buf, ring_buff_addr, len); - intring_info->ret_len = len; - } - else { - len = (size - intring_info->start_idx) * ring_entry_sz; - len = min(len, buf_len); - buf_idx = intring_info->start_idx * ring_entry_sz; - ring_buff_addr = &((UINT8 *)buffer_va)[buf_idx]; - RtlCopyMemory(buf, ring_buff_addr, len); - intring_info->ret_len = len; - - size_t remain_len = ((size_t)intring_info->end_idx + 1) * ring_entry_sz; - len = min(remain_len, (buf_len - len)); - ring_buff_addr = &((UINT8 *)buffer_va)[0]; - RtlCopyMemory(&buf[intring_info->ret_len], ring_buff_addr, len); - intring_info->ret_len += len; - } - - return STATUS_SUCCESS; -} - -/* --------------*/ - -inline static size_t get_msix_mask_offset( - UINT32 vector) -{ - return (qdma_trq_cmc_msix_table + (((size_t)vector + 1) * qdma_msix_vectors_mask_step)); -}; - -void qdma_device::mask_msi_entry( - UINT32 vector) -{ - /* MSIx mask value - * [bit 0 ] - 0 : Unmask, 1 : Mask - * [bit 1-31] - Reserved - */ - UINT32 mask_val = 1u; - qdma_conf_reg_write(get_msix_mask_offset(vector), mask_val); -} - -void qdma_device::unmask_msi_entry( - UINT32 vector) -{ - /* MSIx mask value - * [bit 0 ] - 0 : Unmask, 1 : Mask - * [bit 1-31] - Reserved - */ - UINT32 mask_val = 0u; - qdma_conf_reg_write(get_msix_mask_offset(vector), mask_val); -} - -BOOLEAN EvtErrorInterruptIsr( - WDFINTERRUPT interrupt, - ULONG MessageID) -{ - UNREFERENCED_PARAMETER(interrupt); - UNREFERENCED_PARAMETER(MessageID); - - return WdfInterruptQueueDpcForIsr(interrupt); -} - -VOID EvtErrorInterruptDpc( - WDFINTERRUPT interrupt, - WDFOBJECT device) -{ - UNREFERENCED_PARAMETER(device); - UNREFERENCED_PARAMETER(interrupt); - - TraceError(TRACE_INTR, "Error IRQ Fired on Master PF"); - - auto irq_ctx = get_qdma_irq_context(interrupt); - if (nullptr == irq_ctx) { - TraceError(TRACE_INTR, "Err: null irq_ctx in EvtErrorInterruptDpc"); - return; - } - - auto qdma_dev = irq_ctx->qdma_dev; - qdma_dev->hw.qdma_hw_error_process(qdma_dev); - qdma_dev->hw.qdma_hw_error_intr_rearm(qdma_dev); - - return; -} - -NTSTATUS EvtUserInterruptEnable( - WDFINTERRUPT interrupt, - WDFDEVICE device) -{ - UNREFERENCED_PARAMETER(device); - auto irq_ctx = get_qdma_irq_context(interrupt); - if (irq_ctx->qdma_dev->drv_conf.user_interrupt_enable_handler) { - irq_ctx->qdma_dev->drv_conf.user_interrupt_enable_handler(irq_ctx->vector_id, - irq_ctx->qdma_dev->drv_conf.user_data); - } - - TraceVerbose(TRACE_INTR, "%s: --> %s", irq_ctx->qdma_dev->dev_conf.name, __func__); - return STATUS_SUCCESS; -} - -NTSTATUS EvtUserInterruptDisable( - WDFINTERRUPT interrupt, - WDFDEVICE device) -{ - UNREFERENCED_PARAMETER(device); - auto irq_ctx = get_qdma_irq_context(interrupt); - if (irq_ctx->qdma_dev->drv_conf.user_interrupt_disable_handler) { - irq_ctx->qdma_dev->drv_conf.user_interrupt_disable_handler(irq_ctx->vector_id, - irq_ctx->qdma_dev->drv_conf.user_data); - } - - TraceVerbose(TRACE_INTR, "%s: %s <--", irq_ctx->qdma_dev->dev_conf.name, __func__); - return STATUS_SUCCESS; -} - -BOOLEAN EvtUserInterruptIsr( - WDFINTERRUPT interrupt, - ULONG MessageID) -{ - UNREFERENCED_PARAMETER(interrupt); - UNREFERENCED_PARAMETER(MessageID); - - TraceVerbose(TRACE_INTR, "User Interrupt ISR CALLED %lu SUCCESSFull", MessageID); - - return WdfInterruptQueueDpcForIsr(interrupt); -} - -VOID EvtUserInterruptDpc( - WDFINTERRUPT interrupt, - WDFOBJECT device) -{ - UNREFERENCED_PARAMETER(device); - auto irq_ctx = get_qdma_irq_context(interrupt); - - TraceVerbose(TRACE_INTR, "%s: User Interrupt DPC for vector : %u", irq_ctx->qdma_dev->dev_conf.name, irq_ctx->vector_id); - - if (irq_ctx->qdma_dev->drv_conf.user_isr_handler) { - irq_ctx->qdma_dev->drv_conf.user_isr_handler(irq_ctx->vector_id, - irq_ctx->qdma_dev->drv_conf.user_data); - } - - return; -} - -BOOLEAN EvtDataInterruptIsr( - WDFINTERRUPT interrupt, - ULONG MessageID) -{ - UNREFERENCED_PARAMETER(MessageID); - auto irq_ctx = get_qdma_irq_context(interrupt); - auto qdma_dev = irq_ctx->qdma_dev; - - if ((irq_ctx->intr_type == interrupt_type::LEGACY) && - (qdma_dev->hw.qdma_legacy_intr_conf != nullptr)) { - TraceVerbose(TRACE_INTR, "LEGACY INTERRUPT RECEIVED"); - auto ret = qdma_dev->hw.qdma_is_legacy_intr_pend(qdma_dev); - if (ret < 0) { - /* No interrupt pending, Hence returning from ISR */ - return false; - } - - qdma_dev->hw.qdma_clear_pend_legacy_intr(qdma_dev); - } - - irq_ctx->interrupt_handler(irq_ctx); - - if ((irq_ctx->intr_type == interrupt_type::LEGACY) && - (qdma_dev->hw.qdma_legacy_intr_conf != nullptr)) { - qdma_dev->hw.qdma_legacy_intr_conf(qdma_dev, ENABLE); - TraceVerbose(TRACE_INTR, "LEGACY INTERRUPT RE-ENABLED"); - } - - return true; -} - -BOOLEAN schedule_dpc(queue_pair* q, UINT8 is_c2h, CCHAR active_processors) -{ - BOOLEAN status = FALSE; - poll_operation_entry* poll_entry = nullptr; - PRKDPC dpc = nullptr; - PVOID arg1 = nullptr; - - poll_entry = (is_c2h) ? q->c2h_q.poll_entry : q->h2c_q.poll_entry; - if (poll_entry) { - dpc = &poll_entry->thread->dpc; - arg1 = poll_entry->thread; - - KeSetTargetProcessorDpc(dpc, (CCHAR)(q->idx % active_processors)); - status = KeInsertQueueDpc(dpc, arg1, NULL); - } - - return status; -} - -void cpm_handle_indirect_interrupt( - PQDMA_IRQ_CONTEXT irq_ctx) -{ - queue_pair *q = nullptr; - UINT8 is_c2h = 0; - CCHAR active_processors = (CCHAR)KeQueryActiveProcessorCount(NULL); - - auto intr_queue = irq_ctx->intr_q; - if (nullptr == intr_queue) { - TraceError(TRACE_INTR, "%s: Invalid vector %lu was called in coal mode", - irq_ctx->qdma_dev->dev_conf.name, irq_ctx->vector_id); - return; - } - - const auto ring_va = static_cast(intr_queue->buffer_va); - - TraceVerbose(TRACE_INTR, "%s: CPM Coal queue SW Index : %u", - irq_ctx->qdma_dev->dev_conf.name, intr_queue->sw_index); - TraceVerbose(TRACE_INTR, "%s: CPM Intr PIDX : %u, Intr CIDX : %u", - irq_ctx->qdma_dev->dev_conf.name, ring_va[intr_queue->sw_index].desc_pidx, - ring_va[intr_queue->sw_index].desc_cidx); - - while (ring_va[intr_queue->sw_index].color == intr_queue->color) { - q = irq_ctx->qdma_dev->qdma_get_queue_pair_by_hwid(ring_va[intr_queue->sw_index].qid); - if (nullptr == q) { - TraceError(TRACE_INTR, "%s: Queue not found hw qid : %u Intr qid : %u", - irq_ctx->qdma_dev->dev_conf.name, - ring_va[intr_queue->sw_index].qid, - intr_queue->idx); - intr_queue->advance_sw_index(); - continue; - } - - is_c2h = ring_va[intr_queue->sw_index].intr_type; - - schedule_dpc(q, is_c2h, active_processors); - - intr_queue->advance_sw_index(); - - TraceVerbose(TRACE_INTR, "%s: CPM QUEUE ID : %u, is_c2h : %d", - irq_ctx->qdma_dev->dev_conf.name, - ring_va[intr_queue->sw_index].qid, is_c2h); - } - - if (q) { - intr_queue->update_csr_cidx(q, intr_queue->sw_index); - } -} - -void handle_indirect_interrupt( - PQDMA_IRQ_CONTEXT irq_ctx) -{ - queue_pair *q = nullptr; - UINT8 is_c2h = 0; - CCHAR active_processors = (CCHAR)KeQueryActiveProcessorCount(NULL); - - auto intr_queue = irq_ctx->intr_q; - if (nullptr == intr_queue) { - TraceError(TRACE_INTR, "%s: Invalid vector %lu was called in coal mode", - irq_ctx->qdma_dev->dev_conf.name, irq_ctx->vector_id); - return; - } - - const auto ring_va = static_cast(intr_queue->buffer_va); - - TraceVerbose(TRACE_INTR, "%s: Coal queue SW Index : %u", - irq_ctx->qdma_dev->dev_conf.name, intr_queue->sw_index); - TraceVerbose(TRACE_INTR, "%s: Intr PIDX : %u, Intr CIDX : %u", - irq_ctx->qdma_dev->dev_conf.name, - ring_va[intr_queue->sw_index].desc_pidx, - ring_va[intr_queue->sw_index].desc_cidx); - - while (ring_va[intr_queue->sw_index].color == intr_queue->color) { - q = irq_ctx->qdma_dev->qdma_get_queue_pair_by_hwid(ring_va[intr_queue->sw_index].qid); - if (nullptr == q) { - TraceError(TRACE_INTR, "%s: Queue not found hw qid : %u Intr qid : %u", - irq_ctx->qdma_dev->dev_conf.name, - ring_va[intr_queue->sw_index].qid, intr_queue->idx); - intr_queue->advance_sw_index(); - continue; - } - - is_c2h = ring_va[intr_queue->sw_index].intr_type; - - schedule_dpc(q, is_c2h, active_processors); - - intr_queue->advance_sw_index(); - - TraceVerbose(TRACE_INTR, "%s: QUEUE ID : %u, is_c2h : %d", - irq_ctx->qdma_dev->dev_conf.name, ring_va[intr_queue->sw_index].qid, is_c2h); - } - - if (q) { - intr_queue->update_csr_cidx(q, intr_queue->sw_index); - } -} - -void handle_direct_interrupt( - PQDMA_IRQ_CONTEXT irq_ctx) -{ - CCHAR active_processors = (CCHAR)KeQueryActiveProcessorCount(NULL); - PLIST_ENTRY entry; - PLIST_ENTRY temp; - - LIST_FOR_EACH_ENTRY_SAFE(&irq_ctx->queue_list_head, temp, entry) { - queue_pair *queue = CONTAINING_RECORD(entry, queue_pair, list_entry); - - TraceVerbose(TRACE_INTR, "%s: SERVICING QUEUE : %u IN DIRECT INTERRUPT", - irq_ctx->qdma_dev->dev_conf.name, queue->idx); - schedule_dpc(queue, 0 /* H2C */, active_processors); - schedule_dpc(queue, 1 /* C2H */, active_processors); - - } -} - -int qdma_device::setup_legacy_vector(queue_pair& q) -{ - int ret = 0; - int status = 0; - int legacy_vec = 0; - - WdfInterruptAcquireLock(irq_mgr.irq[legacy_vec]); - - auto irq_ctx = get_qdma_irq_context(irq_mgr.irq[legacy_vec]); - if (false == IS_LIST_EMPTY(&irq_ctx->queue_list_head)) { - TraceError(TRACE_INTR, "%s: Only One queue is supported " - "in legacy interrupt mode", dev_conf.name); - status = -(STATUS_UNSUCCESSFUL); - goto ErrExit; - } - - if (hw.qdma_legacy_intr_conf == nullptr) { - TraceError(TRACE_INTR, "%s: legacy interrupt mode " - "not supported", dev_conf.name); - status = -(STATUS_UNSUCCESSFUL); - goto ErrExit; - } - - ret = hw.qdma_legacy_intr_conf(this, DISABLE); - if (ret < 0) { - TraceError(TRACE_INTR, "%s: qdma_disable_legacy_interrupt " - "failed, ret : %d", dev_conf.name, ret); - status = hw.qdma_get_error_code(ret); - goto ErrExit; - } - - LIST_ADD_TAIL(&irq_ctx->queue_list_head, &q.list_entry); - - ret = hw.qdma_legacy_intr_conf(this, ENABLE); - if (ret < 0) { - TraceError(TRACE_INTR, "%s: qdma_enable_legacy_interrupt " - "failed, ret : %d", dev_conf.name, ret); - status = hw.qdma_get_error_code(ret); - goto ErrExit; - } - - TraceVerbose(TRACE_INTR, "%s: Vector Allocated [0] for legacy interrupt mode", - dev_conf.name); - - WdfInterruptReleaseLock(irq_mgr.irq[legacy_vec]); - - return legacy_vec; - -ErrExit: - WdfInterruptReleaseLock(irq_mgr.irq[legacy_vec]); - return status; -} - -/* Allocate MSIx Vector position */ -UINT32 qdma_device::alloc_msix_vector_position(queue_pair& q) -{ - UINT32 weight; - UINT32 vector; - - WdfSpinLockAcquire(irq_mgr.lock); - - vector = irq_mgr.data_vector_id_start; - weight = irq_mgr.irq_weight[vector]; - - for (UINT32 i = irq_mgr.data_vector_id_start + 1; i <= irq_mgr.data_vector_id_end; ++i) { - if (irq_mgr.irq_weight[i] < weight) { - weight = irq_mgr.irq_weight[i]; - vector = i; - } - } - - ++irq_mgr.irq_weight[vector]; - - WdfSpinLockRelease(irq_mgr.lock); - - if (drv_conf.operation_mode == queue_op_mode::INTR_MODE) { - WdfInterruptAcquireLock(irq_mgr.irq[vector]); - - auto irq_ctx = get_qdma_irq_context(irq_mgr.irq[vector]); - LIST_ADD_TAIL(&irq_ctx->queue_list_head, &queue_pairs[q.idx].list_entry); - - WdfInterruptReleaseLock(irq_mgr.irq[vector]); - } - else if (drv_conf.operation_mode == queue_op_mode::INTR_COAL_MODE) { - /* For indirect interrupt, return absolute interrupt queue index */ - auto irq_ctx = get_qdma_irq_context(irq_mgr.irq[vector]); - vector = irq_ctx->intr_q->idx_abs; - } - - TraceVerbose(TRACE_INTR, "%s: Vector Allocated [%u]. Weight : %u", - dev_conf.name, vector, irq_mgr.irq_weight[vector]); - - return vector; -} - -/* Free MSIX vector position */ -void qdma_device::free_msix_vector_position( - queue_pair& q, - UINT32 vector) -{ - auto RELATIVE_INTR_QID = [](auto q) { return q % (UINT32)qdma_max_msix_vectors_per_pf; }; - if (drv_conf.operation_mode == queue_op_mode::INTR_COAL_MODE) - vector = RELATIVE_INTR_QID(vector); - else if (drv_conf.operation_mode == queue_op_mode::INTR_MODE) { - WdfInterruptAcquireLock(irq_mgr.irq[vector]); - auto irq_ctx = get_qdma_irq_context(irq_mgr.irq[vector]); - PLIST_ENTRY entry; - LIST_FOR_EACH_ENTRY(&irq_ctx->queue_list_head, entry) { - queue_pair *queue = CONTAINING_RECORD(entry, queue_pair, list_entry); - if (queue->idx == q.idx) { - LIST_DEL_NODE(entry); - break; - } - } - WdfInterruptReleaseLock(irq_mgr.irq[vector]); - } - - WdfSpinLockAcquire(irq_mgr.lock); - - --irq_mgr.irq_weight[vector]; - - TraceVerbose(TRACE_INTR, "%s: Vector Released. New weight : %u", - dev_conf.name, irq_mgr.irq_weight[vector]); - WdfSpinLockRelease(irq_mgr.lock); -} - -int qdma_device::assign_interrupt_vector(queue_pair& q) -{ - UINT32 vec; - - if (irq_mgr.intr_type == interrupt_type::MSIX) - vec = alloc_msix_vector_position(q); - else { - vec = setup_legacy_vector(q); - } - return vec; -} - -void qdma_device::free_interrupt_vector(queue_pair& q, UINT32 vec_id) -{ - if (irq_mgr.intr_type == interrupt_type::MSIX) - free_msix_vector_position(q, vec_id); - else - clear_legacy_vector(q, vec_id); -} - -/* Clear legacy vector and disable interrupts */ -void qdma_device::clear_legacy_vector( - queue_pair& q, - UINT32 vector) -{ - UNREFERENCED_PARAMETER(q); - - WdfInterruptAcquireLock(irq_mgr.irq[vector]); - - auto irq_ctx = get_qdma_irq_context(irq_mgr.irq[vector]); - auto queue_item = irq_ctx->queue_list_head; - - if (hw.qdma_legacy_intr_conf != nullptr) { - hw.qdma_legacy_intr_conf(this, DISABLE); - } - - INIT_LIST_HEAD(&irq_ctx->queue_list_head); - WdfInterruptReleaseLock(irq_mgr.irq[vector]); -} - -NTSTATUS qdma_device::configure_irq( - PQDMA_IRQ_CONTEXT irq_context, - ULONG vec) -{ - irq_context->vector_id = vec; - irq_context->qdma_dev = this; - - if ((vec >= irq_mgr.data_vector_id_start) && (vec <= irq_mgr.data_vector_id_end)) { - /* Data interrupts */ - irq_mgr.irq_weight[vec] = 0u; - - if (drv_conf.operation_mode == queue_op_mode::INTR_COAL_MODE) { /* Indirect interrupt */ - irq_context->intr_q = &irq_mgr.intr_q[vec]; - irq_mgr.intr_q[vec].vector = vec; - irq_context->is_coal = true; - if (hw_version_info.ip_type == QDMA_VERSAL_HARD_IP) { - irq_context->interrupt_handler = &cpm_handle_indirect_interrupt; - } - else { - irq_context->interrupt_handler = &handle_indirect_interrupt; - } - } - else { /* Direct interrupt */ - INIT_LIST_HEAD(&irq_context->queue_list_head); - - irq_context->is_coal = false; - irq_context->interrupt_handler = &handle_direct_interrupt; - } - irq_context->intr_type = irq_mgr.intr_type; - } - - return STATUS_SUCCESS; -} - -NTSTATUS qdma_device::arrange_msix_vector_types(void) -{ - ULONG vector = 0; - ULONG req_vec; - ULONG num_msix_vectors = pcie.get_num_msix_vectors(); - - if (num_msix_vectors == 0ul) { - TraceError(TRACE_INTR, "%s: Not enough MSIx vectors : [%u]", - dev_conf.name, num_msix_vectors); - return STATUS_UNSUCCESSFUL; - } - - /** Reserve one vector for Error Interrupt which reports out - * the QDMA internal HW errors to the user - * - * Master PF will own this option and hence other PFs dont need - * to reserve vector for error interrupt - */ - if (dev_conf.is_master_pf) { /* Master PF */ - TraceInfo(TRACE_INTR, "%s: Setting Error Interrupt by Master PF", - dev_conf.name); - irq_mgr.err_vector_id = vector; - ++vector; - /** Error interrupt consumes 1 vector from data interrupt vectors */ - drv_conf.data_msix_max = drv_conf.data_msix_max - 1; - } - - req_vec = vector + drv_conf.data_msix_max + drv_conf.user_msix_max; - - if (num_msix_vectors < req_vec) { - TraceError(TRACE_INTR, "%s: Not enough MSIx vectors : [%u]. Requested : [%u]\n", - dev_conf.name, num_msix_vectors, req_vec); - return STATUS_UNSUCCESSFUL; - } - - irq_mgr.user_vector_id_start = vector; - irq_mgr.user_vector_id_end = vector + drv_conf.user_msix_max - 1 ; - vector += drv_conf.user_msix_max; - - irq_mgr.data_vector_id_start = vector; - - if (drv_conf.operation_mode == queue_op_mode::INTR_COAL_MODE) - irq_mgr.data_vector_id_end = irq_mgr.data_vector_id_start + IND_INTR_MAX_DATA_VECTORS - 1; - else - irq_mgr.data_vector_id_end = vector + drv_conf.data_msix_max - 1; - - TraceVerbose(TRACE_INTR, "%s: Function: %0X, Err vec : %lu, User vec : [%u : %u] Data vec : [%u : %u]", - dev_conf.name, dev_conf.dev_sbdf.sbdf.fun_no, irq_mgr.err_vector_id, - irq_mgr.user_vector_id_start, irq_mgr.user_vector_id_end, - irq_mgr.data_vector_id_start, irq_mgr.data_vector_id_end); - - return STATUS_SUCCESS; -} - -NTSTATUS qdma_device::setup_msix_interrupt( - WDFCMRESLIST resources, - const WDFCMRESLIST resources_translated) -{ - NTSTATUS status; - - /* Setup interrupts */ - PCM_PARTIAL_RESOURCE_DESCRIPTOR resource; - PCM_PARTIAL_RESOURCE_DESCRIPTOR resource_translated; - - ULONG numResources = WdfCmResourceListGetCount(resources_translated); - TraceVerbose(TRACE_INTR, "%s: Total number of resource : %lu", - dev_conf.name, numResources); - - status = arrange_msix_vector_types(); - if (!NT_SUCCESS(status)) { - TraceError(TRACE_INTR, "%s: Failed to arrange MSIx vectors", dev_conf.name); - return status; - } - - for (UINT i = 0, vec = 0; i < numResources && vec < pcie.get_num_msix_vectors(); i++) { - - resource = WdfCmResourceListGetDescriptor(resources, i); - resource_translated = WdfCmResourceListGetDescriptor(resources_translated, i); - if (resource_translated->Type != CmResourceTypeInterrupt) { - continue; - } - - WDF_INTERRUPT_CONFIG config; - - if ((irq_mgr.err_vector_id == vec) && (dev_conf.is_master_pf)) { - WDF_INTERRUPT_CONFIG_INIT(&config, EvtErrorInterruptIsr, EvtErrorInterruptDpc); - config.EvtInterruptEnable = nullptr; - config.EvtInterruptDisable = nullptr; - TraceVerbose(TRACE_INTR, "%s: [%u] - Error interrupt configuration", - dev_conf.name, vec); - } - else if ((vec >= irq_mgr.user_vector_id_start) && (vec <= irq_mgr.user_vector_id_end)) { - WDF_INTERRUPT_CONFIG_INIT(&config, EvtUserInterruptIsr, EvtUserInterruptDpc); - config.EvtInterruptEnable = EvtUserInterruptEnable; - config.EvtInterruptDisable = EvtUserInterruptDisable; - TraceVerbose(TRACE_INTR, "%s: [%u] - User interrupt configuration", - dev_conf.name, vec); - } - else if ((vec >= irq_mgr.data_vector_id_start) && (vec <= irq_mgr.data_vector_id_end)) { /* Data interrupts */ - WDF_INTERRUPT_CONFIG_INIT(&config, EvtDataInterruptIsr, nullptr); - config.EvtInterruptEnable = nullptr; - config.EvtInterruptDisable = nullptr; - TraceVerbose(TRACE_INTR, "%s: [%u] - Data interrupt configuration", dev_conf.name, vec); - } - else { - TraceVerbose(TRACE_INTR, "%s: [%u] - No configuration", dev_conf.name, vec); - continue; - } - - config.InterruptRaw = resource; - config.InterruptTranslated = resource_translated; - config.AutomaticSerialization = TRUE; - - WDF_OBJECT_ATTRIBUTES attribs; - WDF_OBJECT_ATTRIBUTES_INIT(&attribs); - WDF_OBJECT_ATTRIBUTES_INIT_CONTEXT_TYPE(&attribs, QDMA_IRQ_CONTEXT); - - status = WdfInterruptCreate(wdf_dev, &config, &attribs, &irq_mgr.irq[vec]); - if (!NT_SUCCESS(status)) { - TraceError(TRACE_INTR, "WdfInterruptCreate failed: %!STATUS!", status); - return status; - } - - /* FIXME: 2018.2 Bitstream Issue?? Unmasking of the MSIX vectors not happening. So doing it manually */ - if (hw_version_info.ip_type == QDMA_VERSAL_HARD_IP) { - unmask_msi_entry(vec); - } - - auto irq_context = get_qdma_irq_context(irq_mgr.irq[vec]); - status = configure_irq(irq_context, vec); - if (!NT_SUCCESS(status)) { - TraceError(TRACE_INTR, "%s: WdfInterruptCreate failed: %!STATUS!", - dev_conf.name, status); - return status; - } - - if ((irq_mgr.err_vector_id == vec) && (dev_conf.is_master_pf)) { - int ret = hw.qdma_hw_error_intr_setup((void *)this, - (uint16_t)dev_conf.dev_sbdf.sbdf.fun_no, (uint8_t)irq_mgr.err_vector_id); - if (ret < 0) { - TraceError(TRACE_INTR, "%s: qdma_error_interrupt_setup() failed with error %d", - dev_conf.name, ret); - return hw.qdma_get_error_code(ret); - } - - ret = hw.qdma_hw_error_enable((void *)this, hw.qdma_max_errors); - if (ret < 0) { - TraceError(TRACE_INTR, "%s: qdma_error_enable() failed with error %d", - dev_conf.name, ret); - return hw.qdma_get_error_code(ret); - } - - ret = hw.qdma_hw_error_intr_rearm((void *)this); - if (ret < 0) { - TraceError(TRACE_INTR, "%s: qdma_error_interrupt_rearm() failed with error %d", - dev_conf.name, ret); - return hw.qdma_get_error_code(ret); - } - } - - ++vec; - - TraceInfo(TRACE_INTR, "%s: INTERRUPT REGISTERED FOR VECTOR ID: : %d WEIGHT : %d", - dev_conf.name, irq_context->vector_id, irq_context->weight); - } - - return STATUS_SUCCESS; -} - -NTSTATUS qdma_device::setup_legacy_interrupt( - WDFCMRESLIST resources, - const WDFCMRESLIST resources_translated) -{ - NTSTATUS status; - - /* Setup interrupts */ - PCM_PARTIAL_RESOURCE_DESCRIPTOR resource; - PCM_PARTIAL_RESOURCE_DESCRIPTOR resource_translated; - - ULONG numResources = WdfCmResourceListGetCount(resources_translated); - TraceVerbose(TRACE_INTR, "%s: Total number of resource : %lu", - dev_conf.name, numResources); - - - for (UINT i = 0, vec = 0; i < numResources; i++) { - - resource = WdfCmResourceListGetDescriptor(resources, i); - resource_translated = WdfCmResourceListGetDescriptor(resources_translated, i); - if (resource_translated->Type != CmResourceTypeInterrupt) { - continue; - } - - WDF_INTERRUPT_CONFIG config; - - /* Initializing the interrupt config with Data ISR and DPC handlers */ - WDF_INTERRUPT_CONFIG_INIT(&config, EvtDataInterruptIsr, nullptr); - - config.InterruptRaw = resource; - config.InterruptTranslated = resource_translated; - config.EvtInterruptEnable = nullptr; - config.EvtInterruptDisable = nullptr; - config.AutomaticSerialization = TRUE; - - WDF_OBJECT_ATTRIBUTES attribs; - WDF_OBJECT_ATTRIBUTES_INIT(&attribs); - WDF_OBJECT_ATTRIBUTES_INIT_CONTEXT_TYPE(&attribs, QDMA_IRQ_CONTEXT); - - status = WdfInterruptCreate(wdf_dev, &config, &attribs, &irq_mgr.irq[vec]); - if (!NT_SUCCESS(status)) { - TraceError(TRACE_INTR, "%s: WdfInterruptCreate failed: %!STATUS!", - dev_conf.name, status); - return status; - } - - auto irq_context = get_qdma_irq_context(irq_mgr.irq[vec]); - status = configure_irq(irq_context, vec); - if (!NT_SUCCESS(status)) { - TraceError(TRACE_INTR, "%s: WdfInterruptCreate failed: %!STATUS!", - dev_conf.name, status); - return status; - } - - ++vec; - - TraceInfo(TRACE_INTR, "%s: LEGACY INTERRUPT REGISTERED FOR VECTOR ID: : %d WEIGHT : %d", - dev_conf.name, irq_context->vector_id, irq_context->weight); - - /* Only One Vector for Legacy interrupt */ - break; - } - - return STATUS_SUCCESS; -} - -NTSTATUS qdma_device::intr_setup( - WDFCMRESLIST resources, - const WDFCMRESLIST resources_translated) -{ - UINT32 i; - NTSTATUS status = STATUS_SUCCESS; - PCM_PARTIAL_RESOURCE_DESCRIPTOR resource_desc; - ULONG numResources = WdfCmResourceListGetCount(resources_translated); - - /* Initialize IRQ spin lock */ - WDF_OBJECT_ATTRIBUTES attr; - WDF_OBJECT_ATTRIBUTES_INIT(&attr); - attr.ParentObject = wdf_dev; - - status = WdfSpinLockCreate(&attr, &irq_mgr.lock); - if (!NT_SUCCESS(status)) { - TraceError(TRACE_INTR, "%s: WdfSpinLockCreate failed: %!STATUS!", - dev_conf.name, status); - return status; - } - - irq_mgr.intr_type = interrupt_type::NONE; - for (i = 0; i < numResources; i++) { - resource_desc = WdfCmResourceListGetDescriptor(resources_translated, i); - if (resource_desc->Type != CmResourceTypeInterrupt) { - TraceVerbose(TRACE_INTR, "Non Interrupt Resource : %d", resource_desc->Type); - continue; - } - - if (resource_desc->Flags & CM_RESOURCE_INTERRUPT_MESSAGE) { - irq_mgr.intr_type = interrupt_type::MSIX; - - TraceVerbose(TRACE_INTR, - "Message Interrupt level 0x%0x, Vector 0x%0x, MessageCount %u\n" - , resource_desc->u.MessageInterrupt.Translated.Level - , resource_desc->u.MessageInterrupt.Translated.Vector - , resource_desc->u.MessageInterrupt.Raw.MessageCount - ); - } - else { - irq_mgr.intr_type = interrupt_type::LEGACY; - - TraceVerbose(TRACE_INTR, - "Legacy Interrupt level: 0x%0x, Vector: 0x%0x\n" - , resource_desc->u.Interrupt.Level - , resource_desc->u.Interrupt.Vector - ); - } - break; - } - - if (irq_mgr.intr_type == interrupt_type::LEGACY) { - status = setup_legacy_interrupt(resources, resources_translated); - if (!NT_SUCCESS(status)) { - TraceError(TRACE_INTR, "%s: setup_legacy_interrupt() failed: %!STATUS!", - dev_conf.name, status); - } - } - else if (irq_mgr.intr_type == interrupt_type::MSIX) { - status = setup_msix_interrupt(resources, resources_translated); - if (!NT_SUCCESS(status)) { - TraceError(TRACE_INTR, "%s: setup_msix_interrupt() failed: %!STATUS!", - dev_conf.name, status); - } - } - else { - TraceError(TRACE_INTR, "%s: Invalid Interrupt Type : %d " - "(valid are legacy and msix)", dev_conf.name, (int)irq_mgr.intr_type); - return STATUS_UNSUCCESSFUL; - } - - return status; -} - -void qdma_device::intr_teardown(void) -{ - if ((irq_mgr.intr_type == interrupt_type::LEGACY) && - (hw.qdma_legacy_intr_conf != nullptr)) - hw.qdma_legacy_intr_conf((void *)this, DISABLE); - else { - /* FIXME: 2018.2 Bitstream issue?? Mask the msix vectors */ - if (hw_version_info.ip_type == QDMA_VERSAL_HARD_IP) { - for (auto i = 0u; i < pcie.get_num_msix_vectors(); ++i) { - mask_msi_entry(i); - } - } - } -} diff --git a/QDMA/windows/sys/libqdma/source/interrupts.hpp b/QDMA/windows/sys/libqdma/source/interrupts.hpp deleted file mode 100644 index 934443023..000000000 --- a/QDMA/windows/sys/libqdma/source/interrupts.hpp +++ /dev/null @@ -1,107 +0,0 @@ -/* - * Copyright (C) 2020 Xilinx, Inc - * - * Licensed under the Apache License, Version 2.0 (the "License"). You may - * not use this file except in compliance with the License. You may obtain - * a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - */ - -#pragma once - -#include "qdma_platform_env.h" -#include "qdma_config.h" -#include "qdma_reg_ext.h" - -namespace xlnx { -/* Forward declaration */ -class qdma_device; -struct queue_pair; - -#define VECTOR_TYPE_ERROR 0 -#define VECTOR_TYPE_USER 1 -#define VECTOR_TYPE_DATA_START 2 - -#define IND_INTR_MAX_DATA_VECTORS QDMA_NUM_DATA_VEC_FOR_INTR_CXT - -enum class interrupt_type { - NONE, - LEGACY, - MSIX -}; - -struct intr_queue { - static constexpr size_t size = 512; - size_t capacity = size; - size_t npages = 1; - - UINT16 idx = 0; /* queue index - relative to this PF */ - UINT16 idx_abs = 0; /* queue index - abolute across all PF */ - - UINT8 color = 1; - ULONG vector = 0; - - qdma_intr_cidx_reg_info intr_cidx_info; - qdma_device* qdma = nullptr; - WDFCOMMONBUFFER buffer = nullptr; - void *buffer_va = nullptr; - - volatile UINT32 sw_index = 0; /* Driver CIDX */ - - NTSTATUS create(WDFDMAENABLER& dma_enabler); - void clear_contents(void); - - void advance_sw_index(void); - PFORCEINLINE void update_csr_cidx(queue_pair *q, UINT32 new_cidx); - NTSTATUS intring_dump(qdma_intr_ring_info *intring_info); -}; - -typedef struct QDMA_IRQ_CONTEXT { - bool is_coal; - interrupt_type intr_type = interrupt_type::NONE; - ULONG vector_id; - UINT32 weight; - - /* For user interrupt handling */ - void *user_data; - - /* For Error interrupt handling */ - qdma_device *qdma_dev = nullptr; - - /* For direct interrupt handling */ - LIST_ENTRY queue_list_head; - - /* For indirect interrupt handling */ - intr_queue *intr_q = nullptr; - - /* Interrupt handler function */ - void (*interrupt_handler)(QDMA_IRQ_CONTEXT *); - -}*PQDMA_IRQ_CONTEXT; - -WDF_DECLARE_CONTEXT_TYPE_WITH_NAME(QDMA_IRQ_CONTEXT, get_qdma_irq_context); - -struct interrupt_manager { - interrupt_type intr_type = interrupt_type::NONE; - ULONG err_vector_id = 0; - ULONG user_vector_id_start = 0; - ULONG user_vector_id_end = 0; - ULONG data_vector_id_end = 0; - ULONG data_vector_id_start = 0; - - WDFSPINLOCK lock = nullptr; - UINT32 irq_weight[qdma_max_msix_vectors_per_pf]; - WDFINTERRUPT irq[qdma_max_msix_vectors_per_pf]; - intr_queue intr_q[qdma_max_msix_vectors_per_pf]; -}; - -} /* namespace xlnx */ - - diff --git a/QDMA/windows/sys/libqdma/source/qdma.cpp b/QDMA/windows/sys/libqdma/source/qdma.cpp deleted file mode 100644 index 645542f06..000000000 --- a/QDMA/windows/sys/libqdma/source/qdma.cpp +++ /dev/null @@ -1,4235 +0,0 @@ -/* - * Copyright (C) 2020 Xilinx, Inc - * - * Licensed under the Apache License, Version 2.0 (the "License"). You may - * not use this file except in compliance with the License. You may obtain - * a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - */ - -#include "qdma.h" -#include "interrupts.hpp" -#include "qdma_platform.h" -#include "trace.h" - -#ifdef ENABLE_WPP_TRACING -#include "qdma.tmh" -#endif - -using namespace xlnx; - -/* Below are per driver global variables */ -static LIST_ENTRY qdma_dev_list_head; -static WDFWAITLOCK qdma_list_lock; -static volatile LONG qdma_active_pf_count = 0; - -static struct drv_mode_name mode_name_list[] = { - { POLL_MODE, "poll"}, - { INTR_MODE, "direct interrupt"}, - { INTR_COAL_MODE, "indirect interrupt"}, -}; - -NTSTATUS qdma_device::list_add_qdma_device_and_set_gbl_csr(void) -{ - if ((LONG)1 == InterlockedIncrement(&qdma_active_pf_count)) { - TraceVerbose(TRACE_QDMA, "%s: ** Initializing global device list and wait lock **", dev_conf.name); - - /* First device in the list, Initialize the list head */ - INIT_LIST_HEAD(&qdma_dev_list_head); - - WDF_OBJECT_ATTRIBUTES attr; - WDF_OBJECT_ATTRIBUTES_INIT(&attr); - attr.ParentObject = WDFDRIVER(); - - NTSTATUS status = WdfWaitLockCreate(&attr, &qdma_list_lock); - if (!(NT_SUCCESS(status))) { - TraceError(TRACE_QDMA, "%s: Failed to create qdma list wait lock %!STATUS!", dev_conf.name, status); - qdma_list_lock = nullptr; - return status; - } - } - else { - /* To avoid race, Wait for some time - * if list head and wait lock initialization already in progress. - */ - LARGE_INTEGER wait_time; - wait_time.QuadPart = WDF_REL_TIMEOUT_IN_US(100); - KeDelayExecutionThread(KernelMode, FALSE, &wait_time); - - if (nullptr == qdma_list_lock) { - TraceError(TRACE_QDMA, "%s: qdma list wait lock not initialized", dev_conf.name); - return STATUS_UNSUCCESSFUL; - } - } - - TraceVerbose(TRACE_QDMA, "%s: ++ Active pf count : %u ++", dev_conf.name, qdma_active_pf_count); - - WdfWaitLockAcquire(qdma_list_lock, NULL); - - dev_conf.is_master_pf = is_first_qdma_pf_device(); - if (true == dev_conf.is_master_pf) { - TraceInfo(TRACE_QDMA, "Configuring '%04X:%02X:%02X.%x' as master pf\n", - dev_conf.dev_sbdf.sbdf.seg_no, dev_conf.dev_sbdf.sbdf.bus_no, - dev_conf.dev_sbdf.sbdf.dev_no, dev_conf.dev_sbdf.sbdf.fun_no); - - TraceVerbose(TRACE_QDMA, "%s: Setting Global CSR", dev_conf.name); - - int ret = hw.qdma_set_default_global_csr(this); - if (ret < 0) { - TraceError(TRACE_QDMA, "%s: Failed to set global CSR Configuration, ret : %d", dev_conf.name, ret); - WdfWaitLockRelease(qdma_list_lock); - return hw.qdma_get_error_code(ret); - } - } - - LIST_ADD_TAIL(&qdma_dev_list_head, &list_entry); - - WdfWaitLockRelease(qdma_list_lock); - - return STATUS_SUCCESS; -} - -bool qdma_device::is_first_qdma_pf_device(void) -{ - PLIST_ENTRY entry, temp; - - LIST_FOR_EACH_ENTRY_SAFE(&qdma_dev_list_head, temp, entry) { - qdma_device *qdma_dev = CONTAINING_RECORD(entry, qdma_device, list_entry); - if (qdma_dev->dev_conf.dev_sbdf.sbdf.bus_no == dev_conf.dev_sbdf.sbdf.bus_no) { - return false; - } - } - - return true; -} - -void qdma_device::list_remove_qdma_device(void) -{ - if (nullptr == list_entry.Flink && nullptr == list_entry.Blink) - return; - - WdfWaitLockAcquire(qdma_list_lock, nullptr); - LIST_DEL_NODE(&list_entry); - WdfWaitLockRelease(qdma_list_lock); - auto cnt = InterlockedDecrement(&qdma_active_pf_count); - TraceVerbose(TRACE_QDMA, "%s: -- Active pf count : %u --", dev_conf.name, cnt); -} - -/* --------------------------- debug prints of structs --------------------------- */ - -#ifdef ENABLE_WPP_TRACING - -static void dump(const mm_descriptor& desc) -{ - TraceVerbose( - TRACE_DBG, - "descriptor={valid=%u, sop=%u, eop=%u, length=%u, addr=0x%llX," - "dest_addr=0x%llX }", - desc.valid, desc.sop, desc.eop, desc.length, desc.addr, - desc.dest_addr); -} - -static void dump(const h2c_descriptor& desc) -{ - TraceVerbose( - TRACE_DBG, - "descriptor={sop=%u, eop=%u, length=%u, addr=0x%llX}", - desc.sop, desc.eop, desc.length, desc.addr); -} - -static void dump(const char* dir, const qdma_descq_hw_ctxt& ctxt) -{ - TraceVerbose( - TRACE_QDMA, - "%s_hw_desc_ctxt={cidx=%u, credit_use=%u, desc_pending=%u, " - "idle_stop=%u evt_pending=%u fetch_pending=%u}", - dir, ctxt.cidx, ctxt.crd_use, ctxt.dsc_pend, ctxt.idl_stp_b, - ctxt.evt_pnd, ctxt.fetch_pnd); -} - -static void dump(const char* dir, const qdma_descq_sw_ctxt& ctxt) -{ - TraceVerbose(TRACE_QDMA, - "%s_sw_desc_ctxt={pidx=%u irq_arm=%u, funid=%u, qen=%u, " - "frcd_en=%u, wbi_chk=%u, wbi_intvl_en=%u at=%u, fetch_max=%u, " - "rngsz_idx=%u, desc_sz=%u, bypass=%u, mm_ch=%u wb_en=%u" - "irq_en=%u, portid=%u, irq_no_last=%u, err=%u, err_wb=%u, " - "irq_req=%u, mrkr_dis=%u is_mm=%u, ring_bs_addr=%llX, " - "vec=%u, int_aggr=%u}", - dir, ctxt.pidx, ctxt.irq_arm, ctxt.fnc_id, ctxt.qen, - ctxt.frcd_en, ctxt.wbi_chk, ctxt.wbi_intvl_en, ctxt.at, - ctxt.fetch_max, ctxt.rngsz_idx, ctxt.desc_sz, ctxt.bypass, - ctxt.mm_chn, ctxt.wbk_en, ctxt.irq_en, ctxt.port_id, - ctxt.irq_no_last, ctxt.err, ctxt.err_wb_sent, ctxt.irq_req, - ctxt.mrkr_dis, ctxt.is_mm, ctxt.ring_bs_addr, - ctxt.vec, ctxt.intr_aggr); -} - -static void dump(const qdma_descq_prefetch_ctxt& ctxt) -{ - TraceVerbose( - TRACE_DBG, - "c2h_prefetch_ctxt={bypass=%u, buffer_size_idx=%u, " - "sw_credit=%u, valid=%u}", - ctxt.bypass, ctxt.bufsz_idx, ctxt.sw_crdt, ctxt.valid); -} - -static void dump(const qdma_descq_credit_ctxt& ctxt) -{ - TraceVerbose( - TRACE_DBG, - "c2h_credit_ctxt={credits=%u}", - ctxt.credit); -} - -static void dump(const qdma_descq_cmpt_ctxt& ctxt) -{ - TraceVerbose( - TRACE_DBG, - "c2h_cmpt_ctxt={en_stat_desc=%u, en_int=%u, trig_mode=%u, " - "funid=%u, cntr_idx=%u, tmr_idx=%u, int_st=%u, color=%u, " - "ringsz_idx=%u, bs_addr=%llX, desc_sz=%u, pidx=%u, cidx=%u, " - "valid=%u, err=%u, usr_trig_pnd=%u, tmr_runing=%u, fupd=%u, " - "ovf_chk_dis=%u, at=%u, vec=%u, int_aggr=%u}", - ctxt.en_stat_desc, ctxt.en_int, ctxt.trig_mode, ctxt.fnc_id, - ctxt.counter_idx, ctxt.timer_idx, ctxt.in_st, ctxt.color, ctxt.ringsz_idx, - ctxt.bs_addr, ctxt.desc_sz, ctxt.pidx, ctxt.cidx, ctxt.valid, - ctxt.err, ctxt.user_trig_pend, ctxt.timer_running, ctxt.full_upd, - ctxt.ovf_chk_dis, ctxt.at, ctxt.vec, ctxt.int_aggr); -} - -static void dump(const qdma_qid2vec& ctxt) { - TraceVerbose( - TRACE_DBG, - "qid2vec_ctxt={c2h_coal_en=%u, c2h_vec=%u, h2c_coal_en=%u, " - "h2c_vec=%u}", - ctxt.c2h_en_coal, ctxt.c2h_vector, ctxt.h2c_en_coal, ctxt.h2c_vector); -} - -static void dump(qdma_device *qdma_dev, const queue_type q_type, const UINT16 qid) -{ - TraceVerbose(TRACE_DBG, "------------ QUEUE_%u CONTEXT DUMPS ------------", qid); - qdma_descq_sw_ctxt sw_ctxt = { 0 }; - qdma_dev->hw.qdma_sw_ctx_conf((void *)qdma_dev, false, qid, &sw_ctxt, QDMA_HW_ACCESS_READ); - dump("H2C", sw_ctxt); - qdma_dev->hw.qdma_sw_ctx_conf((void *)qdma_dev, true, qid, &sw_ctxt, QDMA_HW_ACCESS_READ); - dump("C2H", sw_ctxt); - - qdma_descq_hw_ctxt hw_ctxt = { 0 }; - qdma_dev->hw.qdma_hw_ctx_conf((void *)qdma_dev, false, qid, &hw_ctxt, QDMA_HW_ACCESS_READ); - dump("H2C", hw_ctxt); - qdma_dev->hw.qdma_hw_ctx_conf((void *)qdma_dev, true, qid, &hw_ctxt, QDMA_HW_ACCESS_READ); - dump("C2H", hw_ctxt); - - if (qdma_dev->hw.qdma_qid2vec_conf) { - qdma_qid2vec qid2vec_ctxt = { 0 }; - qdma_dev->hw.qdma_qid2vec_conf((void *)qdma_dev, false, qid, &qid2vec_ctxt, QDMA_HW_ACCESS_READ); - dump(qid2vec_ctxt); - qdma_dev->hw.qdma_qid2vec_conf((void *)qdma_dev, true, qid, &qid2vec_ctxt, QDMA_HW_ACCESS_READ); - dump(qid2vec_ctxt); - } - - if (q_type == queue_type::STREAMING) { - qdma_descq_cmpt_ctxt cmpt_ctxt = { 0 }; - qdma_dev->hw.qdma_cmpt_ctx_conf((void *)qdma_dev, qid, &cmpt_ctxt, QDMA_HW_ACCESS_READ); - dump(cmpt_ctxt); - - qdma_descq_prefetch_ctxt pfch_ctxt = { 0 }; - qdma_dev->hw.qdma_pfetch_ctx_conf((void *)qdma_dev, qid, &pfch_ctxt, QDMA_HW_ACCESS_READ); - dump(pfch_ctxt); - - qdma_descq_credit_ctxt credit_ctxt = { 0 }; - qdma_dev->hw.qdma_credit_ctx_conf((void *)qdma_dev, true, qid, &credit_ctxt, QDMA_HW_ACCESS_READ); - dump(credit_ctxt); - } - TraceVerbose(TRACE_DBG, "------------ ------------"); -} - -static void dump(const c2h_wb_status& status) -{ - TraceVerbose( - TRACE_DBG, - "c2h_wb_status={pidx=%u, cidx=%u, color=%u, irq_state=%u}", - status.pidx, status.cidx, status.color, status.irq_state); -} - -static void dump(int index, const c2h_wb_header_8B& status) -{ - TraceVerbose( - TRACE_DBG, - "c2h_cmpt_ring[%u]={length=%u, color=%u, desc_error=%u, " - "user_defined_0=0x%llx}", - index, status.length, status.color, status.desc_error, - status.user_defined_0); -} -#else -#define dump(...) (__VA_ARGS__) -#endif - -static size_t get_descriptor_size(qdma_desc_sz desc_sz) -{ - size_t size_in_bytes = 0; - - size_in_bytes = static_cast(1) << (3 + static_cast(desc_sz)); - - return size_in_bytes; -} - -//======================= private member function implemenations ================================== - -_IRQL_requires_max_(PASSIVE_LEVEL) -void *qdma_interface::operator new(_In_ size_t num_bytes) -{ - VERIFY_IS_IRQL_PASSIVE_LEVEL(); - - void *mem = qdma_calloc(1, (uint32_t)num_bytes); - if (mem) - RtlZeroMemory(mem, num_bytes); - - return mem; -} - -_IRQL_requires_max_(PASSIVE_LEVEL) -void qdma_interface::operator delete(_In_ void *addr) -{ - VERIFY_IS_IRQL_PASSIVE_LEVEL(); - if (addr != nullptr) { - qdma_memfree(addr); - } -} - -qdma_interface* qdma_interface::create_qdma_device(void) -{ - qdma_interface *dev_interface = nullptr; - - dev_interface = new xlnx::qdma_device; - if (dev_interface == nullptr) - TraceError(TRACE_QDMA, "qdma_interface allocation Failed"); - else - TraceVerbose(TRACE_QDMA, "qdma_interface allocation Success : %d", sizeof(xlnx::qdma_device)); - - return dev_interface; -} - -void qdma_interface::remove_qdma_device(qdma_interface *qdma_dev) -{ - delete qdma_dev; -} - -NTSTATUS qdma_device::init_qdma_global() -{ - NTSTATUS status; - int ret; - - status = qdma_read_csr_conf(&csr_conf); - if (!NT_SUCCESS(status)) { - TraceError(TRACE_QDMA, "%s: Failed to read CSR Configuration", dev_conf.name); - return status; - } - - ret = hw.qdma_hw_error_enable((void *)this, hw.qdma_max_errors); - if (ret < 0) { - TraceInfo(TRACE_QDMA, "%s: Failed to enable qdma errors, ret : %d", dev_conf.name, ret); - return hw.qdma_get_error_code(ret); - } - - return STATUS_SUCCESS; -} - -NTSTATUS qdma_device::init_func() -{ - int ret; - struct qdma_fmap_cfg config = { 0 }; - - UINT8 h2c = 0, c2h = 1; - for (UINT8 i = 0; i < dev_conf.dev_info.mm_channel_max; i++) { - ret = hw.qdma_mm_channel_conf((void *)this, i, h2c, TRUE); - if (ret < 0) { - TraceError(TRACE_QDMA, "%s: Failed to configure H2C MM channel %d, ret : %d", - dev_conf.name, i, ret); - return hw.qdma_get_error_code(ret); - } - - ret = hw.qdma_mm_channel_conf((void *)this, i, c2h, TRUE); - if (ret < 0) { - TraceError(TRACE_QDMA, "%s: Failed to configure C2H MM channel %d, ret : %d", - dev_conf.name, i, ret); - return hw.qdma_get_error_code(ret); - } - } - - config.qbase = static_cast(qbase); - config.qmax = static_cast(drv_conf.qsets_max); - - ret = hw.qdma_fmap_conf((void *)this, - dev_conf.dev_sbdf.sbdf.fun_no, - &config, - QDMA_HW_ACCESS_WRITE); - if (ret < 0) { - TraceError(TRACE_QDMA, "%s: Failed FMAP Programming for PF %d, ret: %d", - dev_conf.name, dev_conf.dev_sbdf.sbdf.fun_no, ret); - return hw.qdma_get_error_code(ret); - } - - return STATUS_SUCCESS; -} - -void qdma_device::destroy_func(void) -{ - struct qdma_fmap_cfg config = {}; - config.qbase = 0; - config.qmax = 0; - - if (hw.qdma_fmap_conf) { - hw.qdma_fmap_conf((void *)this, - dev_conf.dev_sbdf.sbdf.fun_no, - &config, - QDMA_HW_ACCESS_WRITE); - } -} - - -NTSTATUS qdma_device::assign_bar_types() -{ - UINT8 user_bar_id = 0; - int ret = hw.qdma_get_user_bar((void *)this, - false, - dev_conf.dev_sbdf.sbdf.fun_no, - &user_bar_id); - if (ret < 0) { - TraceError(TRACE_QDMA, "%s: Failed to get AXI Master Lite BAR, ret : %d", dev_conf.name, ret); - return hw.qdma_get_error_code(ret); - } - user_bar_id = user_bar_id / 2; - - NTSTATUS status = pcie.assign_bar_types(user_bar_id); - if (!NT_SUCCESS(status)) { - TraceError(TRACE_QDMA, "%s: pcie assign_bar_types() failed: %!STATUS!", dev_conf.name, status); - return status; - } - - return STATUS_SUCCESS; -} - -NTSTATUS qdma_device::init_dma_queues() -{ - NTSTATUS status = STATUS_SUCCESS; - - if (drv_conf.qsets_max == 0) - return STATUS_SUCCESS; - - queue_pairs = (queue_pair *)qdma_calloc(drv_conf.qsets_max, sizeof(queue_pair)); - if (nullptr == queue_pairs) { - TraceError(TRACE_QDMA, "%s: Failed to allocate queue_pair memory", dev_conf.name); - return STATUS_INSUFFICIENT_RESOURCES; - } - - for (UINT16 qid = 0; qid < drv_conf.qsets_max; qid++) { - auto& q = queue_pairs[qid]; - q.idx = qid; - q.idx_abs = qid + static_cast(qbase); - q.qdma = this; - q.state = queue_state::QUEUE_AVAILABLE; - - if (drv_conf.operation_mode != queue_op_mode::POLL_MODE) - q.h2c_q.lib_config.irq_en = q.c2h_q.lib_config.irq_en = true; - else - q.h2c_q.lib_config.irq_en = q.c2h_q.lib_config.irq_en = false; - - /* clear all context fields for this queue */ - status = clear_contexts(q); - if (!NT_SUCCESS(status)) { - TraceError(TRACE_QDMA, "%s: queue_pair::clear_contexts() failed for queue %d! %!STATUS!", dev_conf.name, q.idx_abs, status); - destroy_dma_queues(); - return status; - } - } - - TraceVerbose(TRACE_QDMA, "%s: All queue contexts are cleared", dev_conf.name); - - return STATUS_SUCCESS; -} - -void qdma_device::destroy_dma_queues(void) -{ - if (nullptr != queue_pairs) { - qdma_memfree(queue_pairs); - queue_pairs = nullptr; - } -} - -NTSTATUS qdma_device::init_interrupt_queues() -{ - NTSTATUS status = STATUS_SUCCESS; - int ret; - qdma_indirect_intr_ctxt intr_ctx = { 0 }; - - /* Initialize interrupt queues */ - for (auto vec = irq_mgr.data_vector_id_start; vec <= irq_mgr.data_vector_id_end; ++vec) { - auto& intr_q = irq_mgr.intr_q[vec]; - intr_q.idx = (UINT16)vec; - intr_q.idx_abs = (UINT16)(vec + (dev_conf.dev_sbdf.sbdf.fun_no * qdma_max_msix_vectors_per_pf)); - intr_q.qdma = this; - - status = intr_q.create(dma_enabler); - if (!NT_SUCCESS(status)) { - TraceError(TRACE_QDMA, "%s: intr_queue::create_resources() failed! %!STATUS!", dev_conf.name, status); - return status; - } - - /* Any failures onwards does not need cleanup. Common buffer created by q.create() - * is freed when dma_enabler object is deleted. - */ - - /* clear context for this queue */ - ret = hw.qdma_indirect_intr_ctx_conf((void *)this, - intr_q.idx_abs, - NULL, - QDMA_HW_ACCESS_CLEAR); - if (ret < 0) { - TraceError(TRACE_QDMA, "%s: Failed to clear interrupt context \ - for intr queue %d, ret : %d", dev_conf.name, intr_q.idx_abs, ret); - return hw.qdma_get_error_code(ret); - } - - /* set the interrupt context for this queue */ - intr_ctx.valid = true; - intr_ctx.vec = (UINT16)intr_q.vector; - intr_ctx.color = intr_q.color; - intr_ctx.func_id = dev_conf.dev_sbdf.sbdf.fun_no; - intr_ctx.page_size = (UINT8)(intr_q.npages - 1); - intr_ctx.baddr_4k = WdfCommonBufferGetAlignedLogicalAddress(intr_q.buffer).QuadPart; - - TraceVerbose(TRACE_DBG, "%s: SETTING intr_ctxt={ \ - BaseAddr=%llX, color=%u, page_sz=%u, vector=%u }", - dev_conf.name, intr_ctx.baddr_4k, intr_ctx.color, intr_ctx.page_size, intr_ctx.vec); - - ret = hw.qdma_indirect_intr_ctx_conf((void *)this, - intr_q.idx_abs, - &intr_ctx, - QDMA_HW_ACCESS_WRITE); - if (ret < 0) { - TraceError(TRACE_QDMA, "%s: Failed to program interrupt \ - ring for intr queue %d, ret: %d", dev_conf.name, intr_q.idx_abs, ret); - return hw.qdma_get_error_code(ret); - } - } - - return status; -} - -NTSTATUS qdma_device::init_os_resources( - WDFCMRESLIST resources, - const WDFCMRESLIST resources_translated) -{ - WDF_OBJECT_ATTRIBUTES attr; - WDF_OBJECT_ATTRIBUTES_INIT(&attr); - attr.ParentObject = wdf_dev; - - WdfDeviceSetAlignmentRequirement(wdf_dev, FILE_64_BYTE_ALIGNMENT); - WDF_DMA_ENABLER_CONFIG dma_enabler_config; - WDF_DMA_ENABLER_CONFIG_INIT(&dma_enabler_config, - WdfDmaProfileScatterGather64Duplex, - 1024 * 1024 * 1024); /* TODO: Magic */ - NTSTATUS status = WdfDmaEnablerCreate(wdf_dev, - &dma_enabler_config, - &attr, - &dma_enabler); - if (!NT_SUCCESS(status)) { - TraceError(TRACE_QDMA, "%s: WdfDmaEnablerCreate() failed: %!STATUS!", dev_conf.name, status); - return status; - } - - if ((dev_conf.is_master_pf) && - (drv_conf.operation_mode == queue_op_mode::POLL_MODE)) { - int ret = hw.qdma_hw_error_enable(this, hw.qdma_max_errors); - if (ret < 0) { - TraceError(TRACE_QDMA, "%s: qdma_error_enable() failed, ret : %d", dev_conf.name, ret); - return hw.qdma_get_error_code(ret); - } - - /* Create a thread for polling errors */ - status = th_mgr.create_err_poll_thread(this); - if (!NT_SUCCESS(status)) { - TraceError(TRACE_QDMA, "%s: create_err_poll_thread() failed: %!STATUS!", dev_conf.name, status); - return status; - } - } - - status = th_mgr.create_sys_threads(drv_conf.operation_mode); - if (!NT_SUCCESS(status)) { - TraceError(TRACE_QDMA, "%s: create_sys_threads() failed: %!STATUS!", dev_conf.name, status); - goto ErrExit; - } - - /* INTERRUPT HANDLING */ - if (drv_conf.operation_mode != queue_op_mode::POLL_MODE) { - /* Get MSIx vector count */ - status = pcie.find_num_msix_vectors(wdf_dev); - if (!NT_SUCCESS(status)) { - TraceError(TRACE_QDMA, "%s: pcie.get_num_msix_vectors() failed! %!STATUS!", dev_conf.name, status); - goto ErrExit; - } - - status = intr_setup(resources, resources_translated); - if (!NT_SUCCESS(status)) { - TraceError(TRACE_QDMA, "%s: intr_setup() failed: %!STATUS!", dev_conf.name, status); - goto ErrExit; - } - } - - return status; - -ErrExit: - destroy_os_resources(); - return status; -} - -void qdma_device::destroy_os_resources(void) -{ - /* dma_enabler will be free by wdf_dev cleanup */ - - if (drv_conf.operation_mode == queue_op_mode::POLL_MODE) { - if (dev_conf.is_master_pf) - th_mgr.terminate_err_poll_thread(); - } - else { - intr_teardown(); - } - - th_mgr.terminate_sys_threads(); -} - -NTSTATUS qdma_device::init_resource_manager() -{ - NTSTATUS status = STATUS_SUCCESS; - - if (qdma_resource_lock_init()) { - TraceError(TRACE_QDMA, "%s: Resource lock creation failed!", dev_conf.name); - return STATUS_UNSUCCESSFUL; - } - - int ret = qdma_master_resource_create(dev_conf.dev_sbdf.sbdf.bus_no, - dev_conf.dev_sbdf.sbdf.bus_no, - QDMA_QBASE, - QDMA_TOTAL_Q, - &dma_dev_index); - if (ret < 0 && ret != -QDMA_ERR_RM_RES_EXISTS) { - TraceError(TRACE_QDMA, "%s: qdma_master_resource_create() failed!, ret : %d", dev_conf.name, ret); - return hw.qdma_get_error_code(ret); - } - - TraceVerbose(TRACE_QDMA, "%s: Device Index : %u Bus start : %u Bus End : %u", - dev_conf.name, dma_dev_index, dev_conf.dev_sbdf.sbdf.bus_no, dev_conf.dev_sbdf.sbdf.bus_no); - - ret = qdma_dev_entry_create(dma_dev_index, dev_conf.dev_sbdf.sbdf.fun_no); - if (ret < 0) { - TraceError(TRACE_QDMA, "%s: qdma_dev_entry_create() failed for function : %u, ret : %d", - dev_conf.name, dev_conf.dev_sbdf.sbdf.fun_no, ret); - status = hw.qdma_get_error_code(ret); - goto ErrExit; - } - - ret = qdma_dev_update(dma_dev_index, dev_conf.dev_sbdf.sbdf.fun_no, drv_conf.qsets_max, &qbase); - if (ret < 0) { - TraceError(TRACE_QDMA, "%s: qdma_dev_update() failed for function : %u, ret : %d", - dev_conf.name, dev_conf.dev_sbdf.sbdf.fun_no, ret); - status = hw.qdma_get_error_code(ret); - goto ErrExit; - } - - TraceVerbose(TRACE_QDMA, "%s: QDMA Function : %u, qbase : %u, qmax : %u", - dev_conf.name, dev_conf.dev_sbdf.sbdf.fun_no, qbase, drv_conf.qsets_max); - - return status; - -ErrExit: - destroy_resource_manager(); - return status; -} - - -void qdma_device::destroy_resource_manager(void) -{ - qdma_dev_entry_destroy(dma_dev_index, dev_conf.dev_sbdf.sbdf.fun_no); - qdma_master_resource_destroy(dma_dev_index); -} - -void qdma_device::inc_queue_pair_count(bool is_cmpt_valid) -{ - qdma_dev_increment_active_queue(dma_dev_index, - dev_conf.dev_sbdf.sbdf.fun_no, - QDMA_DEV_Q_TYPE_H2C); - - qdma_dev_increment_active_queue(dma_dev_index, - dev_conf.dev_sbdf.sbdf.fun_no, - QDMA_DEV_Q_TYPE_C2H); - - if (true == is_cmpt_valid) { - qdma_dev_increment_active_queue(dma_dev_index, - dev_conf.dev_sbdf.sbdf.fun_no, - QDMA_DEV_Q_TYPE_CMPT); - } -} - -void qdma_device::dec_queue_pair_count(bool is_cmpt_valid) -{ - qdma_dev_decrement_active_queue(dma_dev_index, - dev_conf.dev_sbdf.sbdf.fun_no, - QDMA_DEV_Q_TYPE_H2C); - - qdma_dev_decrement_active_queue(dma_dev_index, - dev_conf.dev_sbdf.sbdf.fun_no, - QDMA_DEV_Q_TYPE_C2H); - - if (true == is_cmpt_valid) { - qdma_dev_decrement_active_queue(dma_dev_index, - dev_conf.dev_sbdf.sbdf.fun_no, - QDMA_DEV_Q_TYPE_CMPT); - } -} - - -/* ----- received packet fragment functions ----- */ -NTSTATUS st_c2h_pkt_frag_queue::create(UINT32 entries) -{ - max_q_size = entries; - - frags = static_cast(qdma_calloc(entries, - sizeof(st_c2h_pkt_fragment))); - if (nullptr == frags) { - TraceError(TRACE_QDMA, "Failed to allocate memory for rcvd pkts"); - return STATUS_INSUFFICIENT_RESOURCES; - } - - pidx = cidx = 0; - avail_byte_cnt = 0; - avail_frag_cnt = 0; - - return STATUS_SUCCESS; -} - -void st_c2h_pkt_frag_queue::destroy(void) -{ - if(avail_frag_cnt != 0) - TraceError(TRACE_QDMA, "Error: Still there are packets to process in" - " received_pkts : count : %d", avail_frag_cnt); - - if (frags != nullptr) { - qdma_memfree(frags); - frags = nullptr; - } -} - -PFORCEINLINE bool st_c2h_pkt_frag_queue::is_queue_full(void) -{ - if (((pidx + 1) % max_q_size) == cidx) { - return true; - } - return false; -} - -PFORCEINLINE bool st_c2h_pkt_frag_queue::is_queue_empty(void) -{ - if (cidx == pidx) { - return true; - } - return false; -} - -inline LONG st_c2h_pkt_frag_queue::get_avail_frag_cnt(void) -{ - return avail_frag_cnt; -} - -inline size_t st_c2h_pkt_frag_queue::get_avail_byte_cnt(void) -{ - return avail_byte_cnt; -} - -NTSTATUS st_c2h_pkt_frag_queue::add(st_c2h_pkt_fragment &elem) -{ - if(is_queue_full() == true) - return STATUS_DESTINATION_ELEMENT_FULL; - - frags[pidx] = elem; - - pidx++; - if (pidx >= max_q_size) - pidx = 0; - - avail_byte_cnt += elem.length; - ++avail_frag_cnt; - - return STATUS_SUCCESS; -} - -NTSTATUS st_c2h_pkt_frag_queue::consume(st_c2h_pkt_fragment &elem) -{ - if (is_queue_empty() == true) - return STATUS_SOURCE_ELEMENT_EMPTY; - - elem = frags[cidx]; - - cidx++; - if (cidx >= max_q_size) - cidx = 0; - - avail_byte_cnt -= elem.length; - --avail_frag_cnt; - - return STATUS_SUCCESS; -} -/* ----- -----*/ - -PFORCEINLINE void ring_buffer::advance_idx(volatile UINT32& idx) -{ - NT_ASSERT(idx < capacity); - - /* This condition is to ensure that idx update should happen only once - (either roll back to 0 or increment by 1) - */ - if ((idx + 1) == capacity) - idx = 0; - else - idx++; -} - -PFORCEINLINE void ring_buffer::advance_idx( - volatile UINT32& idx, - const UINT32 num) -{ - if ((idx + num) < capacity) - idx = idx + num; - else - idx = num - (capacity - idx); -} - -NTSTATUS ring_buffer::create( - WDFDMAENABLER& dma_enabler, - UINT32 num_entries, - size_t desc_sz_bytes) -{ - const size_t buffer_sz = num_entries * desc_sz_bytes; - - /** Descriptor Capacity of the ring (does not include write back status entry) - total ring size = capacity + 1; - - descriptor ring uses (capacity - 1) entries for queue full condition - */ - capacity = num_entries - 1; - hw_index = sw_index = 0u; - stats.tot_desc_accepted = stats.tot_desc_processed = 0; - - TraceVerbose(TRACE_QDMA, "Allocate DMA buffer size : %llu ring depth : %llu, capacity : %llu", - buffer_sz, num_entries, capacity); - - auto status = WdfCommonBufferCreate(dma_enabler, - buffer_sz, - WDF_NO_OBJECT_ATTRIBUTES, - &buffer); - - if (!NT_SUCCESS(status)) { - TraceError(TRACE_QDMA, "WdfCommonBufferCreate failed: %!STATUS!", status); - return status; - } - - buffer_va = WdfCommonBufferGetAlignedVirtualAddress(buffer); - RtlZeroMemory(buffer_va, buffer_sz); - - wb_status = WDF_PTR_ADD_OFFSET_TYPE(buffer_va, - capacity * desc_sz_bytes, - wb_status_base *); - - wb_status->cidx = wb_status->pidx = 0; - return status; -} - -void ring_buffer::destroy(void) -{ - capacity = 0; - buffer_va = nullptr; - wb_status = nullptr; - sw_index = 0; - hw_index = 0; - stats.tot_desc_accepted = 0; - stats.tot_desc_processed = 0; - if (buffer) { - TraceVerbose(TRACE_QDMA, "Deleting buffer object"); - WdfObjectDelete(buffer); - buffer = nullptr; - } -} - -PFORCEINLINE UINT32 ring_buffer::idx_delta(UINT32 start_idx, UINT32 end_idx) -{ - NT_ASSERT(start_idx < capacity); - NT_ASSERT(end_idx < capacity); - - if (start_idx <= end_idx) - return end_idx - start_idx; - else - return capacity - start_idx + end_idx; -} - -void *ring_buffer::get_va(void) -{ - return buffer_va; -} - -UINT32 ring_buffer::get_capacity(void) -{ - return capacity; -} - -UINT32 ring_buffer::get_num_free_entries(void) -{ - /* As hw_index is proper 32-bit aligned address, - reading and writing gets done in single cycle - and hence not using any synchronization for performance - */ - UINT32 wb_index = hw_index; - - if (wb_index > sw_index) - return ((wb_index - sw_index) - 1); - else - return (capacity - 1 - (sw_index - wb_index)); -} - -NTSTATUS h2c_queue::create( - qdma_device *qdma, - queue_config& q_conf) -{ - user_conf = q_conf; - - INIT_LIST_HEAD(&req_list_head); - - if ((user_conf.desc_bypass_en) && - (user_conf.sw_desc_sz == static_cast(qdma_desc_sz::QDMA_DESC_SZ_64B))) { - lib_config.desc_sz = qdma_desc_sz::QDMA_DESC_SZ_64B; - } - else { - lib_config.desc_sz = user_conf.is_st ? qdma_desc_sz::QDMA_DESC_SZ_16B : qdma_desc_sz::QDMA_DESC_SZ_32B; - } - - size_t desc_sz_bytes = get_descriptor_size(lib_config.desc_sz); - lib_config.ring_sz = qdma->csr_conf.ring_sz[user_conf.h2c_ring_sz_index]; - - auto status = desc_ring.create(qdma->dma_enabler, - lib_config.ring_sz, - desc_sz_bytes); - if (!NT_SUCCESS(status)) { - TraceError(TRACE_QDMA, "%s: desc_ring.create failed: %!STATUS!", - qdma->dev_conf.name, status); - return status; - } - - init_csr_h2c_pidx_info(); - - /** Create and initialize MM/ST_H2C request tracker of - * descriptor ring size, This is shadow ring and hence the - * size is exact descriptor ring size - */ - status = req_tracker.create(lib_config.ring_sz); - if (!NT_SUCCESS(status)) { - TraceError(TRACE_QDMA, "%s: init_dma_req_tracker() failed: %!STATUS!", - qdma->dev_conf.name, status); - goto ErrExit; - } - - status = WdfSpinLockCreate(WDF_NO_OBJECT_ATTRIBUTES, &lock); - if (!NT_SUCCESS(status)) { - TraceError(TRACE_QDMA, "%s: WdfSpinLockCreate() failed: %!STATUS!", - qdma->dev_conf.name, status); - goto ErrExit; - } - -#ifdef TEST_64B_DESC_BYPASS_FEATURE - if (user_conf.is_st && user_conf.desc_bypass_en && user_conf.sw_desc_sz == 3) { - TraceVerbose(TRACE_QDMA, "%s: Initializing the descriptors with " - "preloaded data to test TEST_64B_DESC_BYPASS_FEATURE", qdma->dev_conf.name); - - for (UINT32 desc_idx = 0; desc_idx < lib_config.ring_sz; desc_idx++) { - UINT8 *desc = - WDF_PTR_ADD_OFFSET_TYPE(desc_ring.buffer_va, - (desc_sz_bytes * desc_idx), - UINT8 *); - RtlFillMemory(desc, desc_sz_bytes, desc_idx + 1); - } - } -#endif - return status; - -ErrExit: - destroy(); - return status; -} - -void h2c_queue::destroy(void) -{ - desc_ring.destroy(); - req_tracker.destroy(); - if (nullptr != lock) { - WdfObjectDelete(lock); - lock = nullptr; - } -} - -void h2c_queue::init_csr_h2c_pidx_info(void) -{ - csr_pidx_info.irq_en = lib_config.irq_en; - csr_pidx_info.pidx = 0u; -} - -NTSTATUS c2h_queue::create( - qdma_device *qdma, - queue_config& q_conf) -{ - user_conf = q_conf; - - INIT_LIST_HEAD(&req_list_head); - - if ((user_conf.desc_bypass_en) && - (user_conf.sw_desc_sz == static_cast(qdma_desc_sz::QDMA_DESC_SZ_64B))) { - lib_config.desc_sz = qdma_desc_sz::QDMA_DESC_SZ_64B; - } - else { - lib_config.desc_sz = user_conf.is_st ? qdma_desc_sz::QDMA_DESC_SZ_8B : qdma_desc_sz::QDMA_DESC_SZ_32B; - } - - size_t desc_sz_bytes = get_descriptor_size(lib_config.desc_sz); - lib_config.ring_sz = qdma->csr_conf.ring_sz[user_conf.c2h_ring_sz_index]; - - INT32 cmpt_ring_idx = - get_cmpt_ring_index(&qdma->csr_conf.ring_sz[0], - user_conf.c2h_ring_sz_index); - - /** If cmpt_ring_idx is found, that is cmpt_ring index */ - if (cmpt_ring_idx >= 0) - lib_config.cmpt_ring_id = cmpt_ring_idx; - /** Else, cmpt_ring index is same as descriptor ring index */ - else - lib_config.cmpt_ring_id = user_conf.c2h_ring_sz_index; - - lib_config.cmpt_ring_sz = qdma->csr_conf.ring_sz[lib_config.cmpt_ring_id]; - - NTSTATUS status = desc_ring.create(qdma->dma_enabler, lib_config.ring_sz, desc_sz_bytes); - if (!NT_SUCCESS(status)) { - TraceError(TRACE_QDMA, "%s: desc_ring.create failed: %!STATUS!", qdma->dev_conf.name, status); - return status; - } - - status = WdfSpinLockCreate(WDF_NO_OBJECT_ATTRIBUTES, &lock); - if (!NT_SUCCESS(status)) { - TraceError(TRACE_INTR, "%s: WdfSpinLockCreate failed: %!STATUS!", qdma->dev_conf.name, status); - goto ErrExit; - } - - if (user_conf.is_st) { - /** Create and initialize ST C2H dma request tracker of - * descriptor ring size to allow minimum of desc_ring entry requests - * when each request occupies a single desc_ring entry - */ - status = st_c2h_req_tracker.create(lib_config.ring_sz); - if (!NT_SUCCESS(status)) { - TraceError(TRACE_QDMA, "%s: Failed to init() ST C2H req tracker failed: %!STATUS!", - qdma->dev_conf.name, status); - goto ErrExit; - } - } - else { - /** Create and initialize MM/ST_H2C request tracker of - * descriptor ring size, This is shadow ring and hence the - * size is exact descriptor ring size - */ - status = req_tracker.create(lib_config.ring_sz); - if (!NT_SUCCESS(status)) { - TraceError(TRACE_QDMA, "%s: Failed to init() MM C2H req tracker failed: %!STATUS!", - qdma->dev_conf.name, status); - goto ErrExit; - } - } - - init_csr_c2h_pidx_info(); - is_cmpt_valid = false; - if ((user_conf.is_st) || - (!user_conf.is_st && user_conf.en_mm_cmpl && qdma->dev_conf.dev_info.mm_cmpt_en)) { - /* Completion ring resources */ - is_cmpt_valid = true; - size_t cmpt_sz_bytes = get_descriptor_size(user_conf.cmpt_sz); - - status = cmpt_ring.create(qdma->dma_enabler, lib_config.cmpt_ring_sz, cmpt_sz_bytes); - if (!NT_SUCCESS(status)) { - TraceError(TRACE_QDMA, "%s: desc_ring.create failed: %!STATUS!", - qdma->dev_conf.name, status); - goto ErrExit; - } - - init_csr_cmpt_cidx_info(); - - /* Identify completion offset */ - qdma_hw_version_info hw_version_info = { }; - qdma->qdma_get_hw_version_info(hw_version_info); - if (hw_version_info.ip_type == QDMA_VERSAL_HARD_IP) { - /* UDD starts from index 2 for Versal Hard IP */ - cmpt_offset = 2; - } - else { - cmpt_offset = 0; - } - } - - if (!user_conf.is_st) - return status; - - lib_config.data_buf_size = qdma->csr_conf.c2h_buff_sz[user_conf.c2h_buff_sz_index]; - const auto c2h_desc_ring = static_cast(desc_ring.get_va()); - - auto desc_ring_capacity = desc_ring.get_capacity(); - pkt_buffer = static_cast(qdma_calloc(desc_ring_capacity, - sizeof(st_c2h_pkt_buffer))); - - if (nullptr == pkt_buffer) { - TraceError(TRACE_QDMA, "%s: rx_buffers qdma_calloc failed: %!STATUS!", - qdma->dev_conf.name, status); - status = STATUS_INSUFFICIENT_RESOURCES; - goto ErrExit; - } - - bool rx_contiguous_alloc; - PVOID buff_va = nullptr; - PHYSICAL_ADDRESS buff_dma; - - /* Try allocating contigous DMA common buffer */ - status = pkt_buffer[0].create(qdma->dma_enabler, - (desc_ring_capacity * lib_config.data_buf_size)); - if (!NT_SUCCESS(status)) { - rx_contiguous_alloc = false; - no_allocated_rx_common_buffs = desc_ring_capacity; - buff_dma.QuadPart = 0; - } - else { - rx_contiguous_alloc = true; - no_allocated_rx_common_buffs = 1; - buff_va = pkt_buffer[0].get_va(); - buff_dma.QuadPart = pkt_buffer[0].get_dma_addr().QuadPart; - } - - for (UINT32 i = 0; i < desc_ring_capacity; ++i) { - if (true == rx_contiguous_alloc) { - /* Split the contiguous buffer */ - pkt_buffer[i].fill_rx_buff(buff_va, buff_dma); - - buff_va = (PVOID)((UINT8 *)buff_va + lib_config.data_buf_size); - buff_dma.QuadPart = buff_dma.QuadPart + lib_config.data_buf_size; - } - else { - /* Allocate DMA buffers for Rx Ring */ - status = pkt_buffer[i].create(qdma->dma_enabler, lib_config.data_buf_size); - if (!NT_SUCCESS(status)) { - no_allocated_rx_common_buffs = i - 1; - goto ErrExit; - } - } - - /* Fill DMA Address for QDMA Rx Descriptor Ring */ - c2h_desc_ring[i].addr = pkt_buffer[i].get_dma_addr().QuadPart; - } - - status = pkt_frag_queue.create(lib_config.cmpt_ring_sz); - if (!NT_SUCCESS(status)) { - TraceError(TRACE_QDMA, "%s: received pkts init failed: %!STATUS!", qdma->dev_conf.name, status); - goto ErrExit; - } - - pkt_frag_list = static_cast(qdma_calloc(desc_ring_capacity, - sizeof(st_c2h_pkt_fragment))); - if (nullptr == pkt_frag_list) { - TraceError(TRACE_QDMA, "%s: rx_buffers qdma_calloc failed: %!STATUS!", qdma->dev_conf.name, status); - status = STATUS_INSUFFICIENT_RESOURCES; - goto ErrExit; - } - - return status; -ErrExit: - destroy(); - return status; -} - -void c2h_queue::destroy(void) -{ - desc_ring.destroy(); - - if (lock) { - WdfObjectDelete(lock); - lock = nullptr; - } - - cmpt_ring.destroy(); - is_cmpt_valid = false; - - if (user_conf.is_st) { - if (pkt_buffer) { - TraceVerbose(TRACE_QDMA, "Deleting ST Rx buffer objects"); - - for (UINT32 i = 0u; i < no_allocated_rx_common_buffs; ++i) { - pkt_buffer[i].destroy(); - } - no_allocated_rx_common_buffs = 0; - - qdma_memfree(pkt_buffer); - pkt_buffer = nullptr; - } - - st_c2h_req_tracker.destroy(); - pkt_frag_queue.destroy(); - - if (nullptr != pkt_frag_list) { - qdma_memfree(pkt_frag_list); - pkt_frag_list = nullptr; - } - } - else { - req_tracker.destroy(); - } -} - -INT32 c2h_queue::get_cmpt_ring_index(UINT32* csr_ring_sz_table, UINT32 desc_ring_idx) -{ - UINT32 csr_idx; - - /** Completion Ring size deduction */ - int best_fit_idx = -1; - for (csr_idx = 0; csr_idx < QDMA_GLOBAL_CSR_ARRAY_SZ; csr_idx++) { - /** Check for ring size larger than descriptor ring size (lib_config.ring_sz) */ - if (csr_ring_sz_table[csr_idx] > csr_ring_sz_table[desc_ring_idx]) { - - /** best_fit_index is the index where its size is - * next higher than descriptor ring size - * (should be in one of the CSR ring size registers) - */ - if (best_fit_idx < 0) - best_fit_idx = csr_idx; - else if ((best_fit_idx >= 0) && - (csr_ring_sz_table[csr_idx] < - csr_ring_sz_table[best_fit_idx])) - best_fit_idx = csr_idx; - } - } - - return best_fit_idx; -} - -void c2h_queue::init_csr_c2h_pidx_info(void) -{ - csr_pidx_info.irq_en = lib_config.irq_en; - csr_pidx_info.pidx = 0u; -} - -void c2h_queue::init_csr_cmpt_cidx_info(void) -{ - csr_cmpt_cidx_info.counter_idx = user_conf.c2h_th_cnt_index; - csr_cmpt_cidx_info.irq_en = lib_config.irq_en; - csr_cmpt_cidx_info.timer_idx = user_conf.c2h_timer_cnt_index; - csr_cmpt_cidx_info.trig_mode = static_cast(user_conf.trig_mode); - csr_cmpt_cidx_info.wrb_en = true; - csr_cmpt_cidx_info.wrb_cidx = 0u; -} - -NTSTATUS dma_req_tracker::create(UINT32 entries) -{ - requests = static_cast(qdma_calloc(entries, sizeof(req_ctx))); - if (nullptr == requests) { - return STATUS_INSUFFICIENT_RESOURCES; - } - - return STATUS_SUCCESS; -} - -void dma_req_tracker::destroy() -{ - if (nullptr != requests) { - qdma_memfree(requests); - requests = nullptr; - } -} - -NTSTATUS st_c2h_dma_req_tracker::create(UINT32 entries) -{ - requests = static_cast(qdma_calloc(entries, sizeof(st_c2h_req))); - if (nullptr == requests) { - return STATUS_INSUFFICIENT_RESOURCES; - } - - NTSTATUS status = WdfSpinLockCreate(WDF_NO_OBJECT_ATTRIBUTES, &lock); - if (!NT_SUCCESS(status)) { - TraceError(TRACE_INTR, "WdfSpinLockCreate failed: %!STATUS!", status); - qdma_memfree(requests); - return status; - } - - capacity = entries; - pidx = cidx = 0u; - - return STATUS_SUCCESS; -} - -void st_c2h_dma_req_tracker::destroy(void) -{ - if (nullptr != requests) { - qdma_memfree(requests); - requests = nullptr; - } - - if (nullptr != lock) { - WdfObjectDelete(lock); - lock = nullptr; - } -} - -NTSTATUS st_c2h_dma_req_tracker::st_push_dma_req(st_c2h_req& req) -{ - WdfSpinLockAcquire(lock); - if (((pidx + 1) % capacity) == cidx) { - WdfSpinLockRelease(lock); - return STATUS_DESTINATION_ELEMENT_FULL; - } - - requests[pidx].len = req.len; - requests[pidx].priv = req.priv; - requests[pidx].st_compl_cb = req.st_compl_cb; - - pidx = (pidx + 1) % capacity; - - WdfSpinLockRelease(lock); - - return STATUS_SUCCESS; -} - -NTSTATUS st_c2h_dma_req_tracker::st_peek_dma_req(st_c2h_req& req) -{ - WdfSpinLockAcquire(lock); - if (pidx == cidx) { - WdfSpinLockRelease(lock); - return STATUS_SOURCE_ELEMENT_EMPTY; - } - WdfSpinLockRelease(lock); - - /* Released the spin above, this call st_peek_dma_req is - designed to use for sequential execution and hence - is not thread safe - */ - - req.len = requests[cidx].len; - req.priv = requests[cidx].priv; - req.st_compl_cb = requests[cidx].st_compl_cb; - - return STATUS_SUCCESS; -} - -NTSTATUS st_c2h_dma_req_tracker::st_pop_dma_req(void) -{ - WdfSpinLockAcquire(lock); - if (pidx == cidx) { - WdfSpinLockRelease(lock); - return STATUS_SOURCE_ELEMENT_EMPTY; - } - WdfSpinLockRelease(lock); - - /* Released the spin above, this call st_peek_dma_req is - designed to use for sequential execution and hence - is not thread safe - */ - requests[cidx].len = 0; - requests[cidx].priv = nullptr; - requests[cidx].st_compl_cb = nullptr; - - cidx = (cidx + 1) % capacity; - return STATUS_SUCCESS; -} - -inline NTSTATUS st_c2h_pkt_buffer::create( - WDFDMAENABLER dma_enabler, - size_t size) -{ - WDF_COMMON_BUFFER_CONFIG common_buff_config; - WDF_COMMON_BUFFER_CONFIG_INIT(&common_buff_config, FILE_64_BYTE_ALIGNMENT); - - NTSTATUS status = WdfCommonBufferCreateWithConfig(dma_enabler, - size, - &common_buff_config, - WDF_NO_OBJECT_ATTRIBUTES, - &rx_buff_common); - - if (!NT_SUCCESS(status)) { - TraceError(TRACE_QDMA, "WdfCommonBufferCreate failed %!STATUS!", status); - return status; - } - - rx_buff_va = WdfCommonBufferGetAlignedVirtualAddress(rx_buff_common); - rx_buff_dma = WdfCommonBufferGetAlignedLogicalAddress(rx_buff_common); - - RtlZeroMemory(rx_buff_va, size); - - return status; -} - -inline void st_c2h_pkt_buffer::destroy(void) -{ - WdfObjectDelete(rx_buff_common); -} - -inline void st_c2h_pkt_buffer::fill_rx_buff(PVOID buff_va, PHYSICAL_ADDRESS buff_dma) -{ - rx_buff_va = buff_va; - rx_buff_dma = buff_dma; -} - -inline PHYSICAL_ADDRESS st_c2h_pkt_buffer::get_dma_addr(void) -{ - return rx_buff_dma; -} - -inline PVOID st_c2h_pkt_buffer::get_va(void) -{ - return rx_buff_va; -} - -NTSTATUS queue_pair::create( - queue_config& conf) -{ - NTSTATUS status; - - type = conf.is_st ? queue_type::STREAMING : queue_type::MEMORY_MAPPED; - - RtlStringCchPrintfA(name, ARRAYSIZE(name), "%s-%s-%d", - qdma->dev_conf.name, ((conf.is_st) ? "ST" : "MM"), idx); - - /* h2c common buffer */ - status = h2c_q.create(qdma, conf); - if (!NT_SUCCESS(status)) { - TraceError(TRACE_QDMA, "%s h2c_q.create failed: %!STATUS!", this->name, status); - return status; - } - - /* c2h common buffer */ - status = c2h_q.create(qdma, conf); - if (!NT_SUCCESS(status)) { - TraceError(TRACE_QDMA, "%s c2h_q.create failed: %!STATUS!", this->name, status); - h2c_q.destroy(); - return status; - } - - return status; -} - -void queue_pair::destroy(void) -{ - h2c_q.destroy(); - c2h_q.destroy(); -} - -void queue_pair::init_csr(void) -{ - if (c2h_q.is_cmpt_valid == true) { - update_sw_index_with_csr_h2c_pidx(0); - update_sw_index_with_csr_wb(0); - update_sw_index_with_csr_c2h_pidx(static_cast(c2h_q.desc_ring.capacity - 1)); - } - else { - update_sw_index_with_csr_h2c_pidx(0); - update_sw_index_with_csr_c2h_pidx(0); - } -} - -PFORCEINLINE void queue_pair::update_sw_index_with_csr_h2c_pidx(UINT32 new_pidx) -{ - TraceVerbose(TRACE_QDMA, "%s-H2C updating h2c pidx to %u", this->name, new_pidx); - - MemoryBarrier(); - h2c_q.desc_ring.sw_index = new_pidx; - h2c_q.csr_pidx_info.pidx = (UINT16)new_pidx; - qdma->hw.qdma_queue_pidx_update(qdma, false /* is_vf */, - idx, false /* is_c2h */, - &h2c_q.csr_pidx_info); -} - -PFORCEINLINE void queue_pair::update_sw_index_with_csr_c2h_pidx(UINT32 new_pidx) -{ - TraceVerbose(TRACE_QDMA, "%s-C2H updating c2h pidx to %u", this->name, new_pidx); - - MemoryBarrier(); - c2h_q.desc_ring.sw_index = new_pidx; - c2h_q.csr_pidx_info.pidx = (UINT16)new_pidx; - qdma->hw.qdma_queue_pidx_update(qdma, false /* is_vf */, - idx, true /* is_c2h */, - &c2h_q.csr_pidx_info); -} - -PFORCEINLINE void queue_pair::update_sw_index_with_csr_wb(UINT32 new_cidx) -{ - TraceVerbose(TRACE_QDMA, "%s-C2H updating wb cidx to %u", this->name, new_cidx); - - c2h_q.cmpt_ring.sw_index = new_cidx; - c2h_q.csr_cmpt_cidx_info.wrb_cidx = (UINT16)new_cidx; - qdma->hw.qdma_queue_cmpt_cidx_update(qdma, false, idx, - &c2h_q.csr_cmpt_cidx_info); -} - -service_status queue_pair::process_mm_request(dma_request* request, size_t* xfer_len) -{ - bool poll; - ring_buffer *desc_ring; - dma_req_tracker *tracker; - ULONG no_of_sub_elem = 0; - UINT32 credits = 0; - ULONG sg_index; - WDF_DMA_DIRECTION direction; - PSCATTER_GATHER_LIST sg_list; - LONGLONG device_offset; - dma_completion_cb compl_cb; - VOID *priv; - poll_operation_entry *poll_entry; - char *dir_name; - service_status status = service_status::SERVICE_CONTINUE; - - /** Validate the parameters */ - if ((request == nullptr) || (xfer_len == NULL)) - return service_status::SERVICE_ERROR; - - /** Read the request parameters */ - direction = request->direction; - sg_list = request->sg_list; - device_offset = (request->device_offset + request->offset_idx); - compl_cb = request->compl_cb; - priv = request->priv; - - if (direction == WdfDmaDirectionWriteToDevice) { - desc_ring = &h2c_q.desc_ring; - tracker = &h2c_q.req_tracker; - poll = !h2c_q.lib_config.irq_en; - poll_entry = h2c_q.poll_entry; - dir_name = (char *)"H2C"; - } - else { - desc_ring = &c2h_q.desc_ring; - tracker = &c2h_q.req_tracker; - poll = !c2h_q.lib_config.irq_en; - poll_entry = c2h_q.poll_entry; - dir_name = (char *)"C2H"; - } - - credits = desc_ring->get_num_free_entries(); - if (credits == 0) { - TraceError(TRACE_QDMA, "%s-%s: No space [%u] in sg dma list", - this->name, dir_name, credits); - return status; - } - - UINT32 ring_idx = desc_ring->sw_index; - bool is_credit_avail = true; - size_t dmaed_len = 0; - - TraceVerbose(TRACE_QDMA, "%s-%s enqueueing %u sg list at ring_index=%u FreeDesc : %u", - this->name, dir_name, (sg_list->NumberOfElements - request->sg_index), ring_idx, credits); - - const auto desc = static_cast(desc_ring->get_va()); - - for (sg_index = request->sg_index; - ((sg_index < sg_list->NumberOfElements) && (is_credit_avail)); sg_index++) { - - size_t len = 0; - size_t remain_len = sg_list->Elements[sg_index].Length; - size_t frag_len = mm_max_desc_data_len; - - if (sg_list->Elements[sg_index].Length > mm_max_desc_data_len) { - UINT32 frag_cnt = (UINT32)(sg_list->Elements[sg_index].Length / sg_frag_len); - if (sg_list->Elements[sg_index].Length % sg_frag_len) - frag_cnt++; - - if (frag_cnt > credits) { - TraceInfo(TRACE_QDMA, "%s-%s Sufficient credts are not available to fit sg element, " - "frag_cnt : %d, credits : %d\n", this->name, dir_name, frag_cnt, credits); - - break; - } - - frag_len = sg_frag_len; - TraceInfo(TRACE_QDMA, "%s-%s sg_list len > mm_max_desc_data_len(%lld > %lld), " - "splitting at idx: %d", this->name, dir_name, sg_list->Elements[sg_index].Length, - mm_max_desc_data_len, sg_index); - } - - while (remain_len != 0) { - size_t part_len = min(remain_len, frag_len); - - desc[ring_idx].length = part_len; - desc[ring_idx].valid = true; - desc[ring_idx].sop = (sg_index == 0); - desc[ring_idx].eop = (sg_index == (sg_list->NumberOfElements - 1)) && (remain_len == part_len); - - if (direction == WdfDmaDirectionWriteToDevice) { - desc[ring_idx].addr = sg_list->Elements[sg_index].Address.QuadPart + len; - desc[ring_idx].dest_addr = device_offset; - } - else { - desc[ring_idx].addr = device_offset; - desc[ring_idx].dest_addr = sg_list->Elements[sg_index].Address.QuadPart + len; - } - - len = len + part_len; - remain_len = remain_len - part_len; - - device_offset += part_len; - dump(desc[ring_idx]); - - tracker->requests[ring_idx].compl_cb = nullptr; - /** Set Call back function if EOP is SET */ - if (desc[ring_idx].eop == true) { - tracker->requests[ring_idx].compl_cb = (dma_completion_cb)compl_cb; - tracker->requests[ring_idx].priv = priv; - desc[ring_idx].eop = true; - } - - desc_ring->advance_idx(ring_idx); - - no_of_sub_elem++; - /** Descriptor ring boundary checking */ - credits--; - if (credits == 0) { - is_credit_avail = false; - break; - } - } - /** Discard the main element count in sg_list->NumberOfElements */ - no_of_sub_elem--; - dmaed_len += len; - } - - if (sg_index != request->sg_index) { - request->sg_index = sg_index; - request->offset_idx = device_offset - request->device_offset; - - /** When sg_index reaches the end, request forward done */ - if (request->sg_index >= sg_list->NumberOfElements) - status = service_status::SERVICE_FINISHED; - - UINT32 accepted_desc = desc_ring->idx_delta(desc_ring->sw_index, ring_idx); - desc_ring->stats.tot_desc_accepted += accepted_desc; - - *xfer_len = dmaed_len; - - TraceVerbose(TRACE_QDMA, "%s-%s +++ Request added at : %u +++", - this->name, dir_name, (ring_idx - 1)); - TraceVerbose(TRACE_QDMA, "%s-%s MM Accepted Desc : %d", - this->name, dir_name, accepted_desc); - -#ifdef STRESS_TEST - KeStallExecutionProcessor(2); -#endif - - if (direction == WdfDmaDirectionWriteToDevice) { - update_sw_index_with_csr_h2c_pidx(ring_idx); - TraceVerbose(TRACE_QDMA, "%s-%s csr[%u].h2c_dsc_pidx=%u", - this->name, dir_name, idx_abs, ring_idx); - } - else { - update_sw_index_with_csr_c2h_pidx(ring_idx); - TraceVerbose(TRACE_QDMA, "%s-%s csr[%u].c2h_dsc_pidx=%u", - this->name, dir_name, idx_abs, ring_idx); - } - - if (poll) - wakeup_thread(poll_entry->thread); - } - - return status; -} - -service_status queue_pair::process_st_h2c_request(dma_request* request, size_t* xfer_len) -{ - bool poll; - ring_buffer *desc_ring; - dma_req_tracker *tracker; - poll_operation_entry *poll_entry; - ULONG NumberOfElements; - ULONG no_of_sub_elem = 0; - UINT32 credits; - PSCATTER_GATHER_LIST sg_list; - dma_completion_cb compl_cb; - VOID *priv; - ULONG sg_index; - service_status status = service_status::SERVICE_CONTINUE; - - /** Validate the parameters */ - if ((request == nullptr) || (xfer_len == NULL)) - return service_status::SERVICE_ERROR; - - /** ST C2H has different execution flow */ - if (request->direction != WdfDmaDirectionWriteToDevice) - return service_status::SERVICE_ERROR; - - /** Read the request parameters */ - sg_list = request->sg_list; - compl_cb = request->compl_cb; - priv = request->priv; - - desc_ring = &h2c_q.desc_ring; - tracker = &h2c_q.req_tracker; - poll = !h2c_q.lib_config.irq_en; - poll_entry = h2c_q.poll_entry; - NumberOfElements = sg_list->NumberOfElements; - - credits = desc_ring->get_num_free_entries(); - if (credits == 0) { - TraceError(TRACE_QDMA, "%s-H2C: No space [%u] in sg dma list", this->name, credits); - return status; - } - - UINT32 pidx = desc_ring->sw_index; - const auto desc = static_cast(desc_ring->get_va()); - bool is_credit_avail = true; - size_t dmaed_len = 0; - - TraceVerbose(TRACE_QDMA, "%s-H2C enqueueing %u sg list at ring_index=%u FreeDesc : %u", - this->name, (NumberOfElements - request->sg_index), pidx, credits); - - for (sg_index = request->sg_index; ((sg_index < NumberOfElements) && (is_credit_avail)); sg_index++) { - size_t len = 0; - size_t remain_len = sg_list->Elements[sg_index].Length; - size_t frag_len = st_max_desc_data_len; - - /* If the SG element length is more than ST supported len, - * then Fragment the SG element into sub SG elements */ - if (sg_list->Elements[sg_index].Length > st_max_desc_data_len) { - UINT32 frag_cnt = (UINT32)(sg_list->Elements[sg_index].Length / sg_frag_len); - if (sg_list->Elements[sg_index].Length % sg_frag_len) - frag_cnt++; - - if (frag_cnt > credits) { - TraceInfo(TRACE_QDMA, "%s-H2C: Sufficient credits are not available to fit sg element, " - "frag_cnt : %d, credits : %d\n", this->name, frag_cnt, credits); - - break; - } - - frag_len = sg_frag_len; - TraceInfo(TRACE_QDMA, "%s-H2C sg_list len > st_max_desc_data_len(%lld > %lld), " - "splitting at idx: %d", this->name, sg_list->Elements[sg_index].Length, - st_max_desc_data_len, sg_index); - } - - /** do while loop is to support ST Zero length packet transfers */ - do { - size_t part_len = min(remain_len, frag_len); - - desc[pidx].addr = sg_list->Elements[sg_index].Address.QuadPart + len; - desc[pidx].length = (UINT16)part_len; - desc[pidx].pld_len = (UINT16)part_len; - desc[pidx].sop = (sg_index == 0); - desc[pidx].eop = (sg_index == (NumberOfElements - 1) && (remain_len == part_len)); - - len = len + part_len; - remain_len = remain_len - part_len; - - dump(desc[pidx]); - - tracker->requests[pidx].compl_cb = nullptr; - /** Set Call back function if EOP is SET */ - if (desc[pidx].eop == true) { - tracker->requests[pidx].compl_cb = (dma_completion_cb)compl_cb; - tracker->requests[pidx].priv = priv; - } - - desc_ring->advance_idx(pidx); - - no_of_sub_elem++; - /** Descriptor ring boundary checking */ - credits--; - if (credits == 0) { - is_credit_avail = false; - break; - } - } while (remain_len != 0); - /** Discard the main element count in sg_list->NumberOfElements */ - no_of_sub_elem--; - dmaed_len += len; - } - - if (sg_index != request->sg_index) { - request->sg_index = sg_index; - - /** When sg_index reaches the end, request forward done */ - if (request->sg_index >= sg_list->NumberOfElements) - status = service_status::SERVICE_FINISHED; - - UINT32 accepted_desc = desc_ring->idx_delta(desc_ring->sw_index, pidx); - desc_ring->stats.tot_desc_accepted += accepted_desc; - - *xfer_len = dmaed_len; - - TraceVerbose(TRACE_QDMA, "%s-H2C +++ Request added at : %u +++", this->name, (pidx - 1)); - TraceVerbose(TRACE_QDMA, "%s-H2C ST Accepted Desc : %d", this->name, accepted_desc); - - update_sw_index_with_csr_h2c_pidx(pidx); - TraceVerbose(TRACE_QDMA, "%s-H2C csr[%u].h2c_dsc_pidx=%u", this->name, idx_abs, pidx); - - if (poll) - wakeup_thread(poll_entry->thread); - - } - return status; -} - -service_status queue_pair::service_mm_st_h2c_completions(ring_buffer *desc_ring, - dma_req_tracker *tracker, UINT32 budget, UINT32 &proc_desc_cnt) -{ - UINT32 old_cidx = desc_ring->hw_index; - UINT32 new_cidx = desc_ring->wb_status->cidx; - UINT32 index; - - /** Complete requests covered by the descriptors in the interval - * [old_cidx, new_cidx] */ - for (index = old_cidx; - ((index != new_cidx) && (budget > 0)); - desc_ring->advance_idx(index), budget--) { - req_ctx &completed_req = tracker->requests[index]; - - if (completed_req.compl_cb != nullptr) { - TraceVerbose(TRACE_QDMA, "%s: --- COMPLETING REQ AT : %u ---", this->name, index); - completed_req.compl_cb(completed_req.priv, STATUS_SUCCESS); - completed_req.compl_cb = nullptr; - completed_req.priv = nullptr; - } - } - - proc_desc_cnt = desc_ring->idx_delta(old_cidx, index); - desc_ring->stats.tot_desc_processed += proc_desc_cnt; - - /* Update stored copy of the ring's consumer index */ - desc_ring->hw_index = index; - - if (index != new_cidx || desc_ring->sw_index != new_cidx) { - /** Ran out of completion budget or still have pending requests. - * In interrupt mode while ISR is running, driver might miss the - * new interrupts. So, check if any pending jobs are for ring to - * continue polling service. - */ - return service_status::SERVICE_CONTINUE; - } - else { - return service_status::SERVICE_FINISHED; - } -} - -NTSTATUS queue_pair::check_cmpt_error(c2h_wb_header_8B *cmpt_data) -{ - NTSTATUS status = STATUS_SUCCESS; - - if (cmpt_data->data_frmt) { - /** - * format = 1 does not have length field, so the driver cannot - * figure out how many descriptor is used - */ - status = STATUS_UNSUCCESSFUL; - } - - if (cmpt_data->desc_error) { - /** - * descriptor has error - */ - status = STATUS_UNSUCCESSFUL; - } - - return status; -} - -PFORCEINLINE void queue_pair::update_c2h_pidx_in_batch(UINT32 processed_desc_cnt) -{ - TraceVerbose(TRACE_QDMA, "%s: Completed desc count qid[%u] : %ld", - this->name, idx_abs, processed_desc_cnt); - if (processed_desc_cnt) { - UINT32 new_pidx = c2h_q.desc_ring.sw_index; - c2h_q.desc_ring.advance_idx(new_pidx, processed_desc_cnt); - update_sw_index_with_csr_c2h_pidx(new_pidx); - } -} - -service_status queue_pair::st_service_c2h_queue(UINT32 budget) -{ - NTSTATUS status; - service_status ret = service_status::SERVICE_FINISHED; - ring_buffer *cmpt_ring = &c2h_q.cmpt_ring; - const auto wb_status = reinterpret_cast(cmpt_ring->wb_status); - auto current_pidx = wb_status->pidx; - auto prev_pidx = c2h_q.cmpt_ring.sw_index; - - /* Process WB ring */ - if (prev_pidx != current_pidx) { - TraceVerbose(TRACE_QDMA, "%s: Completion ring sw index : %u hw pidx : %u", this->name, prev_pidx, current_pidx); - dump(*const_cast(wb_status)); - - c2h_wb_header_8B *c2h_cmpt_ring_va; - UINT32 wb_desc_shift = (3 + static_cast(c2h_q.user_conf.cmpt_sz)); - const auto c2h_cmpt_ring_base_va = static_cast(c2h_q.cmpt_ring.get_va()); - - for (; prev_pidx != current_pidx; c2h_q.cmpt_ring.advance_idx(prev_pidx)) { - c2h_cmpt_ring_va = (c2h_wb_header_8B *)((UINT8 *)c2h_cmpt_ring_base_va + ((UINT64)prev_pidx << wb_desc_shift)); - - dump(prev_pidx, *c2h_cmpt_ring_va); - - /** Check completion descriptor for any errors */ - status = check_cmpt_error(c2h_cmpt_ring_va); - if (!NT_SUCCESS(status)) { - TraceError(TRACE_QDMA, "%s: check_cmpt_error returned error", this->name); - return service_status::SERVICE_ERROR; - } - - if (c2h_cmpt_ring_va->desc_used) { - /* Consume the used packet */ - status = process_st_c2h_data_pkt((void *)c2h_cmpt_ring_va, c2h_cmpt_ring_va->length); - if (!NT_SUCCESS(status)) { - TraceError(TRACE_QDMA, "%s: process_st_c2h_data_pkt() failed: %!STATUS!", this->name, status); - break; - } - } - else { - /* If user provides a call back function during queue addition, - * callback function will be called and user can process the UDD data, - * else, data will be discarded - * - * This is UDD_ONLY packets, i.e, data is not associated with this completion - * Data associated UDD packets will be given as part of read requests - */ - if (c2h_q.user_conf.proc_st_udd_cb) - c2h_q.user_conf.proc_st_udd_cb(idx, (void *)c2h_cmpt_ring_va, (void *)qdma); - } - } - - update_sw_index_with_csr_wb(prev_pidx); - } - - /* Process pending ST DMA Requests */ - UINT32 processed_dma_requests = 0; - st_c2h_req req = { 0 }; - UINT32 processed_desc_cnt = 0; - constexpr UINT8 pidx_update_interval = 16; - - /** For ST C2H Queues, budget acts as Upper cut-off for - * the dma requests from user that are pending for completion */ - while (processed_dma_requests < budget) { - status = c2h_q.st_c2h_req_tracker.st_peek_dma_req(req); - if (!NT_SUCCESS(status)) { - /* No more pending requests, Update PIDX and break the loop */ - update_c2h_pidx_in_batch(processed_desc_cnt); - LONG pkt_cnt = c2h_q.pkt_frag_queue.get_avail_frag_cnt(); - if (pkt_cnt) { - TraceVerbose(TRACE_QDMA, "%s: No pending requests. Available Packets : %Iu", this->name, pkt_cnt); - ret = service_status::SERVICE_CONTINUE; - } - break; - } - - if (req.len <= c2h_q.pkt_frag_queue.get_avail_byte_cnt()) { - UINT32 n = 0; - /* For Zero length packets */ - if (req.len == 0) { - status = c2h_q.pkt_frag_queue.consume(c2h_q.pkt_frag_list[n]); - if (!NT_SUCCESS(status)) { - break; - } - n++; - } - else { - size_t length; - for (n = 0u, length = 0u; ((n < c2h_q.desc_ring.get_capacity()) && - (length < req.len)); ++n) { - status = c2h_q.pkt_frag_queue.consume(c2h_q.pkt_frag_list[n]); - if (!NT_SUCCESS(status)) { - break; - } - length += c2h_q.pkt_frag_list[n].length; - } - } - - if (req.st_compl_cb != nullptr) { - req.st_compl_cb(c2h_q.pkt_frag_list, n, req.priv, status); - req.st_compl_cb = nullptr; - } - - c2h_q.st_c2h_req_tracker.st_pop_dma_req(); - ++processed_dma_requests; - processed_desc_cnt += n; - c2h_q.desc_ring.stats.tot_desc_processed += n; - - if (processed_desc_cnt >= pidx_update_interval) { - /* Return ST Buffers to desc ring */ - update_c2h_pidx_in_batch(processed_desc_cnt); - processed_desc_cnt = 0; - } - } - else { - TraceInfo(TRACE_QDMA, "%s: req_len : %lld, rxd_len:%lld", - this->name, req.len, c2h_q.pkt_frag_queue.get_avail_byte_cnt()); - update_c2h_pidx_in_batch(processed_desc_cnt); - ret = service_status::SERVICE_CONTINUE; - break; - } - } - - TraceVerbose(TRACE_QDMA, "%s: Completed Request count : %ld", - this->name, processed_dma_requests); - return ret; -} - -void process_queue_req(queue_pair* queue, WDFSPINLOCK lock, PLIST_ENTRY req_list_head) -{ - PLIST_ENTRY entry; - PLIST_ENTRY temp; - service_status status; - UINT32 req_service_cnt = 0; - size_t xfer_len = 0; - - if ((queue == nullptr) || (lock == nullptr) || (req_list_head == nullptr)) { - TraceError(TRACE_QDMA, "Invalid Parameters : queue : %p, " - "lock : %p, req_list_head : %p", queue, lock, req_list_head); - return; - } - - if (queue->state != queue_state::QUEUE_STARTED) { - TraceError(TRACE_QDMA, "%s invalid state, q_state: %d", - queue->name, queue->state); - return; - } - - /** Come out of the loop only - * "when the list is empty" or - * "when there is no room in descriptor ring (!SERVICE_FINISHED)" or - * "when max request service reached" - */ - LIST_FOR_EACH_ENTRY_SAFE(req_list_head, temp, entry) { - dma_request* request = LIST_GET_ENTRY(entry, dma_request, list_entry); - if (queue->type == queue_type::STREAMING) { - status = queue->process_st_h2c_request(request, &xfer_len); - } - else { - status = queue->process_mm_request(request, &xfer_len); - } - switch (status) { - case service_status::SERVICE_CONTINUE: - /** Exit the loop as there is no room in descriptor ring */ - req_service_cnt = max_req_service_cnt; - TraceVerbose(TRACE_QDMA, "%s-%s: Request Split", queue->name, - ((request->direction == WdfDmaDirectionReadFromDevice) ? "C2H" : "H2C")); - break; - - case service_status::SERVICE_FINISHED: - req_service_cnt++; - WdfSpinLockAcquire(lock); - LIST_DEL_NODE(entry); - WdfSpinLockRelease(lock); - qdma_memfree(request); - break; - - case service_status::SERVICE_ERROR: - /** Remove the request from the list, - * Can be NULL pointer or ST C2H packet */ - WdfSpinLockAcquire(lock); - LIST_DEL_NODE(entry); - WdfSpinLockRelease(lock); - - if (request) { - TraceError(TRACE_QDMA, "%s-%s: queue->process_XXX_request() SERVICE_ERROR", - ((request->direction == WdfDmaDirectionReadFromDevice) ? "C2H" : "H2C"), - queue->name); - qdma_memfree(request); - } - break; - default: - TraceError(TRACE_QDMA, "%s-%s: queue->process_XXX_request() " - "invalid return value (0x%X)", queue->name, - ((request->direction == WdfDmaDirectionReadFromDevice)? "C2H" : "H2C"), - static_cast(status)); - break; - } - - if (req_service_cnt >= max_req_service_cnt) { - TraceInfo(TRACE_QDMA, "%s: Max Requests serviced (%d)", queue->name, req_service_cnt); - break; - } - } -} - -void process_mm_h2c_req(void* arg) -{ - queue_pair* queue = static_cast(arg); - - process_queue_req(queue, queue->h2c_q.lock, &queue->h2c_q.req_list_head); -} - -void process_mm_c2h_req(void* arg) -{ - queue_pair* queue = static_cast(arg); - - process_queue_req(queue, queue->c2h_q.lock, &queue->c2h_q.req_list_head); -} - -void service_h2c_mm_queue(void* arg) -{ - queue_pair *queue = static_cast(arg); - UINT32 budget = mm_h2c_completion_weight; - ring_buffer *desc_ring = &queue->h2c_q.desc_ring; - dma_req_tracker *tracker = &queue->h2c_q.req_tracker; - UINT32 proc_desc_cnt = 0; - - service_status status = - queue->service_mm_st_h2c_completions(desc_ring, tracker, budget, proc_desc_cnt); - switch (status) { - case service_status::SERVICE_CONTINUE: - if (proc_desc_cnt != 0) { - TraceVerbose(TRACE_QDMA, "%s: MM H2C [%u] Flag request, " - "proc_desc_cnt:%d", queue->name, queue->idx_abs, proc_desc_cnt); - wakeup_thread(queue->h2c_q.req_proc_entry->thread); - } - wakeup_thread(queue->h2c_q.poll_entry->thread); - break; - case service_status::SERVICE_ERROR: - TraceError(TRACE_QDMA, "%s: MM H2C [%u] service error", queue->name, queue->idx_abs); - break; - case service_status::SERVICE_FINISHED: - wakeup_thread(queue->h2c_q.req_proc_entry->thread); - TraceVerbose(TRACE_QDMA, "%s: ervice_h2c_mm_queue [%u] Completed", queue->name, queue->idx_abs); - default: - break; - } -} - -void service_c2h_mm_queue(void *arg) -{ - queue_pair *queue = static_cast(arg); - UINT32 budget = mm_c2h_completion_weight; - ring_buffer* desc_ring = &queue->c2h_q.desc_ring; - dma_req_tracker* tracker = &queue->c2h_q.req_tracker; - UINT32 proc_desc_cnt = 0; - - service_status status = - queue->service_mm_st_h2c_completions(desc_ring, tracker, budget, proc_desc_cnt); - switch (status) { - case service_status::SERVICE_CONTINUE: - if (proc_desc_cnt != 0) { - TraceVerbose(TRACE_QDMA, "%s: MM C2H [%u] Flag request, " - "proc_desc_cnt:%d", queue->name, queue->idx_abs, proc_desc_cnt); - wakeup_thread(queue->c2h_q.req_proc_entry->thread); - } - wakeup_thread(queue->c2h_q.poll_entry->thread); - break; - case service_status::SERVICE_ERROR: - TraceError(TRACE_QDMA, "%s: MM C2H [%u] service error", queue->name, queue->idx_abs); - break; - case service_status::SERVICE_FINISHED: - wakeup_thread(queue->c2h_q.req_proc_entry->thread); - TraceVerbose(TRACE_QDMA, "%s: service_c2h_mm_queue [%u] Completed", queue->name, queue->idx_abs); - default: - break; - } -} - -void process_st_h2c_req(void* arg) -{ - queue_pair* queue = static_cast(arg); - - process_queue_req(queue, queue->h2c_q.lock, &queue->h2c_q.req_list_head); -} - -void service_h2c_st_queue(void *arg) -{ - queue_pair *queue = static_cast(arg); - UINT32 budget = st_h2c_completion_weight; - ring_buffer* desc_ring = &queue->h2c_q.desc_ring; - dma_req_tracker* tracker = &queue->h2c_q.req_tracker; - UINT32 proc_desc_cnt = 0; - - service_status status = - queue->service_mm_st_h2c_completions(desc_ring, tracker, budget, proc_desc_cnt); - switch (status) { - case service_status::SERVICE_CONTINUE: - if (proc_desc_cnt != 0) { - TraceVerbose(TRACE_QDMA, "%s: ST H2C [%u] Flag request, " - "proc_desc_cnt:%d", queue->name, queue->idx_abs, proc_desc_cnt); - wakeup_thread(queue->h2c_q.req_proc_entry->thread); - } - wakeup_thread(queue->h2c_q.poll_entry->thread); - break; - case service_status::SERVICE_ERROR: - TraceError(TRACE_QDMA, "%s: ST H2C [%u] service error", queue->name, queue->idx_abs); - break; - case service_status::SERVICE_FINISHED: - wakeup_thread(queue->h2c_q.req_proc_entry->thread); - TraceVerbose(TRACE_QDMA, "%s: service_h2c_st_queue [%u] Completed", queue->name, queue->idx_abs); - default: - break; - } -} - -void service_c2h_st_queue(void *arg) -{ - queue_pair *queue = static_cast(arg); - UINT32 budget = st_c2h_completion_weight; - service_status status = queue->st_service_c2h_queue(budget); - - switch (status) { - case service_status::SERVICE_CONTINUE: - wakeup_thread(queue->c2h_q.poll_entry->thread); - break; - case service_status::SERVICE_ERROR: - TraceError(TRACE_QDMA, "%s: ST C2H [%u] service error", queue->name, queue->idx_abs); - break; - case service_status::SERVICE_FINISHED: - TraceVerbose(TRACE_QDMA, "%s: service_c2h_st_queue [%u] Completed", queue->name, queue->idx_abs); - default: - break; - } -} - -NTSTATUS queue_pair::enqueue_dma_request(dma_request *request) -{ - WDFSPINLOCK lock; - PLIST_ENTRY req_list_head; - dma_request* req_entry; - poll_operation_entry* req_proc_entry; - char *dir_name; - - if (request == nullptr) - return STATUS_INVALID_PARAMETER; - - /** This function Only Support MM H2C, MM C2H and ST C2H. - * Rule out the unsupported case - */ - if ((request->is_st == true) && - (request->direction != WdfDmaDirectionWriteToDevice)) { - return STATUS_NOT_SUPPORTED; - } - - if (request->direction == WdfDmaDirectionWriteToDevice) { - lock = h2c_q.lock; - req_list_head = &h2c_q.req_list_head; - req_proc_entry = h2c_q.req_proc_entry; - dir_name = (char *)"H2C"; - } - else { - lock = c2h_q.lock; - req_list_head = &c2h_q.req_list_head; - req_proc_entry = c2h_q.req_proc_entry; - dir_name = (char*)"C2H"; - } - - req_entry = static_cast(qdma_calloc(1, sizeof(dma_request))); - if (req_entry == nullptr) { - TraceError(TRACE_QDMA, "%s: req_entry allocation failed", this->name); - return STATUS_NO_MEMORY; - } - - /** Copy the request details */ - RtlCopyMemory(req_entry, request, sizeof(dma_request)); - - TraceVerbose(TRACE_QDMA, "%s-%s Req Added, Abs Queue: %d, Entry : %p", - this->name, dir_name, idx_abs, - static_cast(&req_entry->list_entry)); - - /** Add to the request linked list head */ - WdfSpinLockAcquire(lock); - LIST_ADD_TAIL(req_list_head, &req_entry->list_entry); - WdfSpinLockRelease(lock); - - /** Wake up the thread to forward the request to DMA engine */ - wakeup_thread(req_proc_entry->thread); - - return STATUS_SUCCESS; -} - -NTSTATUS queue_pair::enqueue_dma_request( - size_t length, - st_rx_completion_cb compl_cb, - void *priv) -{ - bool poll = !c2h_q.lib_config.irq_en; - st_c2h_req req; - req.len = length; - req.priv = priv; - req.st_compl_cb = compl_cb; - - NTSTATUS status = c2h_q.st_c2h_req_tracker.st_push_dma_req(req); - if (!NT_SUCCESS(status)) { - TraceError(TRACE_QDMA, "%s: Failed to add ST C2H request %!STATUS!", this->name, status); - return status; - } - - if (poll) { - wakeup_thread(c2h_q.poll_entry->thread); - } - - return status; -} - -NTSTATUS queue_pair::process_st_c2h_data_pkt( - void *udd_ptr, - const UINT32 length) -{ - st_c2h_pkt_fragment elem; - UINT32 data_buff_sz = c2h_q.lib_config.data_buf_size; - UINT32 remain_len = length; - auto num_descriptors = (length + data_buff_sz - 1) / data_buff_sz; - auto& c2h_hw_idx = c2h_q.desc_ring.hw_index; - NTSTATUS status = STATUS_SUCCESS; - - /* For Zero Length Packet */ - if (length == 0) { - num_descriptors = 1; - } - - for (UINT32 i = 0; i < num_descriptors; ++i) { - elem.pkt_type = st_c2h_pkt_type::ST_C2H_DATA_PKT; - elem.data = c2h_q.pkt_buffer[c2h_hw_idx].get_va(); - elem.length = min(remain_len, data_buff_sz); - remain_len -= data_buff_sz; - - if (i == (UINT32)0) { - elem.udd_data = udd_ptr; - elem.sop = 1; - elem.eop = 0; - } - else { - elem.udd_data = nullptr; - elem.sop = elem.eop = 0 ; - } - - elem.eop = (i == num_descriptors - 1) ? 1 : 0; - - status = c2h_q.pkt_frag_queue.add(elem); - if (!NT_SUCCESS(status)) { - TraceError(TRACE_QDMA, "%s: add fragment failed: %!STATUS!", this->name, status); - return status; - } - - c2h_q.desc_ring.advance_idx(c2h_hw_idx); - } - - return status; -} - -void queue_pair::cancel_mm_st_h2c_pending_requests( - ring_buffer *desc_ring, - dma_req_tracker *tracker, - WDFSPINLOCK lock) -{ - /** From hw_index to sw_index [all pending requests in queue], - * cancel all the requests for given descriptor ring */ - - /* Acquire spin lock for rundown protection */ - WdfSpinLockAcquire(lock); - for (UINT32 index = desc_ring->hw_index; - index != desc_ring->sw_index; desc_ring->advance_idx(index)) { - if (tracker->requests[index].compl_cb != nullptr) { - dma_completion_cb compl_cb = tracker->requests[index].compl_cb; - compl_cb(tracker->requests[index].priv, STATUS_CANCELLED); - tracker->requests[index].compl_cb = nullptr; - tracker->requests[index].priv = nullptr; - } - } - WdfSpinLockRelease(lock); -} - -void queue_pair::flush_queue(void) -{ - /* Cancel all the pending requests */ - cancel_mm_st_h2c_pending_requests(&h2c_q.desc_ring, &h2c_q.req_tracker, h2c_q.lock); - if (type == queue_type::MEMORY_MAPPED) { - cancel_mm_st_h2c_pending_requests(&c2h_q.desc_ring, &c2h_q.req_tracker, c2h_q.lock); - } - else { - /** Cancelling ST C2H pending requests */ - st_c2h_req req; - while (NT_SUCCESS(c2h_q.st_c2h_req_tracker.st_peek_dma_req(req))) { - if (req.st_compl_cb != nullptr) { - req.st_compl_cb(nullptr, 0, req.priv, STATUS_CANCELLED); - req.st_compl_cb = nullptr; - } - c2h_q.st_c2h_req_tracker.st_pop_dma_req(); - } - } -} - -NTSTATUS queue_pair::read_st_udd_data(void *addr, UINT8 *buf, UINT32 *len) -{ - UINT32 udd_len = (UINT32)get_descriptor_size(c2h_q.user_conf.cmpt_sz); - UINT8 *cmpt = (UINT8 *)addr; - UINT8 loc = 0; - UINT32 index = c2h_q.cmpt_offset; - - if ((nullptr == addr) || (nullptr == buf) || (nullptr == len)) - return STATUS_INVALID_PARAMETER; - - for (loc = 0; index < udd_len; loc++, index++) { - if (loc == 0) { - buf[loc] = cmpt[index] & 0xF0; - } - else { - buf[loc] = cmpt[index]; - } - } - - *len = loc; - - TraceVerbose(TRACE_QDMA, "%s: UDD Len : %u", this->name, loc); - - return STATUS_SUCCESS; -} - -void * queue_pair::get_last_udd_addr(void) -{ - UINT8 *udd_addr = nullptr; - UINT32 udd_len = (UINT32)get_descriptor_size(c2h_q.user_conf.cmpt_sz); - const auto c2h_cmpt_ring_va = static_cast(c2h_q.cmpt_ring.get_va()); - - volatile wb_status_base *wb_status = c2h_q.cmpt_ring.wb_status; - UINT16 latest_pidx = wb_status->pidx; - - if (latest_pidx == 0) - latest_pidx = (UINT16)(c2h_q.cmpt_ring.get_capacity() - 1); - else - latest_pidx = latest_pidx - 1; - - udd_addr = (UINT8 *)c2h_cmpt_ring_va + ((UINT64)latest_pidx * udd_len); - - return udd_addr; -} - -NTSTATUS queue_pair::desc_dump(qdma_desc_info *desc_info) -{ - size_t desc_sz; - size_t desc_len; - size_t len; - size_t buf_idx; - ring_buffer *desc_ring; - UINT8 *desc_buff_addr; - UINT8 *buf = desc_info->pbuffer; - size_t buff_sz = desc_info->buffer_sz; - WDFSPINLOCK lock; - - - if (desc_info->desc_type == qdma_desc_type::CMPT_DESCRIPTOR) { - if (c2h_q.is_cmpt_valid == true) { - desc_ring = &c2h_q.cmpt_ring; - desc_sz = (size_t)c2h_q.user_conf.cmpt_sz; - lock = c2h_q.lock; - } - else { - TraceError(TRACE_QDMA, "%s: MM CMPT is not valid, HW MM CMPT EN : %d, SW MM CMPT EN : %d\n", - this->name, qdma->dev_conf.dev_info.mm_cmpt_en, c2h_q.user_conf.en_mm_cmpl); - return STATUS_NOT_SUPPORTED; - } - } - else { - if (desc_info->dir == qdma_queue_dir::QDMA_QUEUE_DIR_H2C) { - desc_ring = &h2c_q.desc_ring; - desc_sz = static_cast(h2c_q.lib_config.desc_sz); - lock = h2c_q.lock; - } - else { - desc_ring = &c2h_q.desc_ring; - desc_sz = static_cast(c2h_q.lib_config.desc_sz); - lock = c2h_q.lock; - } - } - - if ((desc_info->desc_start > desc_ring->get_capacity()) || - (desc_info->desc_end > desc_ring->get_capacity())) { - TraceError(TRACE_QDMA, "%s: Descriptor Range is incorrect : start : %d, end : %d, RING SIZE : %d", - this->name, desc_info->desc_start, desc_info->desc_end, desc_ring->get_capacity()); - return STATUS_ACCESS_VIOLATION; - } - - desc_len = (static_cast(1) << (3 + desc_sz)); - - desc_info->desc_sz = desc_len; - - /** This lock is to prevent queue stop/delete operations when descriptor - * data is captured. There is no guarantee that the descriptor data - * won't change (Ex: completion entries are filled by HW). - * - * This will grab instantaneous information present in the descriptors - */ - WdfSpinLockAcquire(lock); - if (desc_info->desc_start <= desc_info->desc_end) { - len = ((size_t)desc_info->desc_end - (size_t)desc_info->desc_start + 1) * desc_len; - if (buff_sz < len) { - WdfSpinLockRelease(lock); - return STATUS_BUFFER_TOO_SMALL; - } - - buf_idx = desc_info->desc_start * desc_len; - desc_buff_addr = &((UINT8 *)desc_ring->get_va())[buf_idx]; - RtlCopyMemory(buf, desc_buff_addr, len); - desc_info->data_sz = len; - } - else { - len = ((size_t)desc_ring->get_capacity() - (size_t)desc_info->desc_start + 1) * desc_len; - if (buff_sz < len) { - WdfSpinLockRelease(lock); - return STATUS_BUFFER_TOO_SMALL; - } - - buf_idx = desc_info->desc_start * desc_len; - desc_buff_addr = &((UINT8 *)desc_ring->get_va())[buf_idx]; - RtlCopyMemory(buf, desc_buff_addr, len); - desc_info->data_sz = len; - - size_t remain_len = ((size_t)desc_info->desc_end + 1) * desc_len; - if ((buff_sz - len) < remain_len) { - WdfSpinLockRelease(lock); - return STATUS_BUFFER_TOO_SMALL; - } - - desc_buff_addr = &((UINT8 *)desc_ring->get_va())[0]; - RtlCopyMemory(&buf[desc_info->data_sz], desc_buff_addr, len); - desc_info->data_sz += len; - } - WdfSpinLockRelease(lock); - - return STATUS_SUCCESS; -} - -NTSTATUS queue_pair::read_mm_cmpt_data(qdma_cmpt_info *cmpt_info) -{ - if (type != queue_type::MEMORY_MAPPED) { - TraceError(TRACE_QDMA, "%s: read_mm_cmpt_data supported only for MM queues", this->name); - return STATUS_NOT_SUPPORTED; - } - - if (!c2h_q.is_cmpt_valid) { - TraceError(TRACE_QDMA, "%s: MM Completion is not enabled, " - "HW En Status : %d, SW En Status : %d", this->name, - qdma->dev_conf.dev_info.mm_cmpt_en, c2h_q.user_conf.en_mm_cmpl); - - return STATUS_NOT_CAPABLE; - } - - WdfSpinLockAcquire(c2h_q.lock); - const auto wb_status = reinterpret_cast(c2h_q.cmpt_ring.wb_status); - auto prev_pidx = c2h_q.cmpt_ring.sw_index; - auto current_pidx = wb_status->pidx; - - if (prev_pidx == current_pidx) { - TraceError(TRACE_QDMA, "%s: No Completion data available : " - "Prev PIDX : %d, Pres PIDX : %d", this->name, prev_pidx, current_pidx); - WdfSpinLockRelease(c2h_q.lock); - return STATUS_SOURCE_ELEMENT_EMPTY; - } - - UINT8 *dest_buff = cmpt_info->pbuffer; - size_t index = 0; - const UINT8 *src_buff = static_cast(c2h_q.cmpt_ring.get_va()); - size_t desc_sz = get_descriptor_size(c2h_q.user_conf.cmpt_sz);; - - for (; prev_pidx != current_pidx; c2h_q.cmpt_ring.advance_idx(prev_pidx)) { - - if ((index >= cmpt_info->buffer_len) || ((index + desc_sz) > cmpt_info->buffer_len)) { - break; - } - - memcpy_s(&dest_buff[index], (cmpt_info->buffer_len - index), &src_buff[prev_pidx * desc_sz], desc_sz); - /** The first 4 bits are example design specific and - * which contains Err, color, two user logic bits. - * - * Its the user design choice on the format of the completion data and - * This part of the code is to demonstrate the MM CMPT functionality - */ - dest_buff[index] = dest_buff[index] & 0xF0; - index = index + desc_sz; - } - - cmpt_info->ret_len = index; - cmpt_info->cmpt_desc_sz = desc_sz; - - update_sw_index_with_csr_wb(prev_pidx); - - WdfSpinLockRelease(c2h_q.lock); - - return STATUS_SUCCESS; -} - -//======================= indirect programming ==================================================== - -NTSTATUS qdma_device::clear_queue_contexts(bool is_c2h, UINT16 qid, qdma_hw_access_type context_op) const -{ - const bool irq_enable = (drv_conf.operation_mode == queue_op_mode::POLL_MODE) ? false : true; - int ret = hw.qdma_sw_ctx_conf((void *)this, is_c2h, qid, nullptr, context_op); - if (ret < 0) - return hw.qdma_get_error_code(ret); - - ret = hw.qdma_hw_ctx_conf((void *)this, is_c2h, qid, nullptr, context_op); - if (ret < 0) - return hw.qdma_get_error_code(ret); - - ret = hw.qdma_credit_ctx_conf((void *)this, is_c2h, qid, nullptr, context_op); - if (ret < 0) - return hw.qdma_get_error_code(ret); - - if ((nullptr != hw.qdma_qid2vec_conf) && irq_enable) { - /** Versal Hard IP supports explicit qid2vec context programming. - * For other versions, vector Id is accommodated in software context. - */ - ret = hw.qdma_qid2vec_conf((void *)this, is_c2h, qid, nullptr, context_op); - if (ret < 0) { - return hw.qdma_get_error_code(ret); - } - } - - return STATUS_SUCCESS; -} - -NTSTATUS qdma_device::clear_cmpt_contexts(UINT16 qid, qdma_hw_access_type context_op) const -{ - int ret = hw.qdma_cmpt_ctx_conf((void *)this, qid, nullptr, context_op); - if (ret < 0) - return hw.qdma_get_error_code(ret); - - return STATUS_SUCCESS; -} - -NTSTATUS qdma_device::clear_pfetch_contexts(UINT16 qid, qdma_hw_access_type context_op) const -{ - int ret = hw.qdma_pfetch_ctx_conf((void *)this, qid, nullptr, context_op); - if (ret < 0) - return hw.qdma_get_error_code(ret); - - return STATUS_SUCCESS; -} - - -NTSTATUS qdma_device::clear_contexts(queue_pair& q, bool invalidate) const -{ - auto idx_abs = q.idx_abs; - qdma_hw_access_type context_op = (invalidate == true) ? QDMA_HW_ACCESS_INVALIDATE : QDMA_HW_ACCESS_CLEAR; - - /* Clear/Invalidate H2C contexts */ - NTSTATUS status = clear_queue_contexts(false, idx_abs, context_op); - if (!NT_SUCCESS(status)) { - return status; - } - - /* Clear/Invalidate C2H contexts */ - status = clear_queue_contexts(true, idx_abs, context_op); - if (!NT_SUCCESS(status)) { - return status; - } - - /** - * clear Completion context when completion ring is valid for the queue - */ - if(q.c2h_q.is_cmpt_valid == true) { - status = clear_cmpt_contexts(idx_abs, context_op); - if (!NT_SUCCESS(status)) { - return status; - } - } - - /** - * Clear Prefetch context if queue is added in streaming mode - */ - if (q.c2h_q.user_conf.is_st) { - status = clear_pfetch_contexts(idx_abs, context_op); - if (!NT_SUCCESS(status)) { - return status; - } - } - - return STATUS_SUCCESS; -} - -NTSTATUS qdma_device::set_h2c_ctx( - queue_pair& q) -{ - int ret; - - TraceVerbose(TRACE_QDMA, "%s setting h2c contexts...", q.name); - - const bool irq_enable = (drv_conf.operation_mode == queue_op_mode::POLL_MODE) ? false : true; - - if (irq_enable) - TraceVerbose(TRACE_QDMA, "%s Programming with IRQ", q.name); - - qdma_descq_sw_ctxt sw_ctx = {}; - - sw_ctx.pidx = 0; - sw_ctx.qen = true; - sw_ctx.frcd_en = false; - sw_ctx.wbi_chk = true; - sw_ctx.wbi_intvl_en = true; - sw_ctx.fnc_id = dev_conf.dev_sbdf.sbdf.fun_no; - sw_ctx.rngsz_idx = q.h2c_q.user_conf.h2c_ring_sz_index; - sw_ctx.bypass = q.h2c_q.user_conf.desc_bypass_en; - sw_ctx.mm_chn = 0; - sw_ctx.wbk_en = true; - sw_ctx.irq_en = irq_enable; - sw_ctx.is_mm = q.type == queue_type::MEMORY_MAPPED ? 1 : 0; - sw_ctx.desc_sz = (UINT8)q.h2c_q.lib_config.desc_sz; - sw_ctx.at = 0; - sw_ctx.ring_bs_addr = WdfCommonBufferGetAlignedLogicalAddress(q.h2c_q.desc_ring.buffer).QuadPart; - - if (irq_enable) { - sw_ctx.vec = (UINT16)q.h2c_q.lib_config.vector_id; - sw_ctx.intr_aggr = (drv_conf.operation_mode == queue_op_mode::INTR_COAL_MODE) ? true : false; - } - - ret = hw.qdma_sw_ctx_conf((void *)this, false, q.idx_abs, &sw_ctx, QDMA_HW_ACCESS_WRITE); - if (ret < 0) { - TraceError(TRACE_QDMA, "%s Failed to program H2C Software context! ret : %d", q.name, ret); - return hw.qdma_get_error_code(ret); - } - - if ((nullptr != hw.qdma_qid2vec_conf) && irq_enable) { - /** Versal Hard IP supports explicit qid2vec context programming. - * For other versions, vector Id is accommodated in software context. - */ - qdma_qid2vec intr_ctx = {}; - intr_ctx.h2c_vector = (UINT8)q.h2c_q.lib_config.vector_id; - intr_ctx.h2c_en_coal = (drv_conf.operation_mode == queue_op_mode::INTR_COAL_MODE) ? true : false; - - ret = hw.qdma_qid2vec_conf((void *)this, false, q.idx_abs, &intr_ctx, QDMA_HW_ACCESS_WRITE); - if (ret < 0) { - TraceError(TRACE_QDMA, "%s Failed to program qid2vec context! ret : %d", q.name, ret); - clear_queue_contexts(false, q.idx_abs, QDMA_HW_ACCESS_CLEAR); - return hw.qdma_get_error_code(ret); - } - } - - return STATUS_SUCCESS; -} - -NTSTATUS qdma_device::set_c2h_ctx( - queue_pair& q) -{ - int ret; - NTSTATUS status = STATUS_SUCCESS; - - TraceVerbose(TRACE_QDMA, "%s setting c2h contexts...", q.name); - - const bool irq_enable = (drv_conf.operation_mode == queue_op_mode::POLL_MODE) ? false : true; - - if (irq_enable) - TraceVerbose(TRACE_QDMA, "%s Programming with IRQ", q.name); - - qdma_descq_sw_ctxt sw_ctx = {}; - - sw_ctx.pidx = 0; - sw_ctx.qen = true; - sw_ctx.frcd_en = false; - sw_ctx.wbi_chk = true; - sw_ctx.wbi_intvl_en = false; - sw_ctx.fnc_id = dev_conf.dev_sbdf.sbdf.fun_no; - sw_ctx.rngsz_idx = q.c2h_q.user_conf.c2h_ring_sz_index; - sw_ctx.bypass = q.c2h_q.user_conf.desc_bypass_en; - sw_ctx.wbk_en = true; - sw_ctx.irq_en = irq_enable; - sw_ctx.is_mm = q.type == queue_type::MEMORY_MAPPED ? 1 : 0; - sw_ctx.desc_sz = (UINT8)q.c2h_q.lib_config.desc_sz; - sw_ctx.at = 0; - sw_ctx.ring_bs_addr = WdfCommonBufferGetAlignedLogicalAddress(q.c2h_q.desc_ring.buffer).QuadPart; - - if (q.type == queue_type::STREAMING) { - sw_ctx.frcd_en = true; - } - - if (irq_enable) { - sw_ctx.vec = (UINT16)q.c2h_q.lib_config.vector_id; - sw_ctx.intr_aggr = (drv_conf.operation_mode == queue_op_mode::INTR_COAL_MODE) ? true : false; - } - - ret = hw.qdma_sw_ctx_conf((void *)this, true, q.idx_abs, &sw_ctx, QDMA_HW_ACCESS_WRITE); - if (ret < 0) { - TraceError(TRACE_QDMA, "%s Failed to program C2H Software context! ret : %d", q.name, ret); - return hw.qdma_get_error_code(ret); - } - - if ((nullptr != hw.qdma_qid2vec_conf) && irq_enable) { - /** Versal Hard IP supports explicit qid2vec context programming. - * For other versions, vector Id is accommodated in software context. - */ - qdma_qid2vec intr_ctx = {}; - intr_ctx.c2h_vector = (UINT8)q.c2h_q.lib_config.vector_id; - intr_ctx.c2h_en_coal = (drv_conf.operation_mode == queue_op_mode::INTR_COAL_MODE) ? true : false; - - ret = hw.qdma_qid2vec_conf((void *)this, true, q.idx_abs, &intr_ctx, QDMA_HW_ACCESS_WRITE); - if (ret < 0) { - TraceError(TRACE_QDMA, "%s Failed to program qid2vec context!, ret : %d", q.name, ret); - status = hw.qdma_get_error_code(ret); - goto ErrExit; - } - } - - /* CMPT context programming */ - if (q.c2h_q.is_cmpt_valid == true) { - qdma_descq_cmpt_ctxt cmp_ctx = {}; - cmp_ctx.en_stat_desc = true; - cmp_ctx.en_int = irq_enable; - cmp_ctx.trig_mode = (uint8_t)q.c2h_q.user_conf.trig_mode; - cmp_ctx.fnc_id = dev_conf.dev_sbdf.sbdf.fun_no; - cmp_ctx.counter_idx = q.c2h_q.user_conf.c2h_th_cnt_index; - cmp_ctx.timer_idx = q.c2h_q.user_conf.c2h_timer_cnt_index; - cmp_ctx.ringsz_idx = (UINT8)q.c2h_q.lib_config.cmpt_ring_id; - cmp_ctx.ovf_chk_dis = q.c2h_q.user_conf.cmpl_ovf_dis; - cmp_ctx.color = 1; - cmp_ctx.pidx = 0; - cmp_ctx.valid = true; - cmp_ctx.full_upd = false; - cmp_ctx.desc_sz = (uint8_t)q.c2h_q.user_conf.cmpt_sz; - cmp_ctx.bs_addr = WdfCommonBufferGetAlignedLogicalAddress(q.c2h_q.cmpt_ring.buffer).QuadPart; - - if (irq_enable) { - cmp_ctx.vec = (UINT16)q.c2h_q.lib_config.vector_id; - cmp_ctx.int_aggr = (drv_conf.operation_mode == queue_op_mode::INTR_COAL_MODE) ? true : false; - } - - ret = hw.qdma_cmpt_ctx_conf((void *)this, q.idx_abs, &cmp_ctx, QDMA_HW_ACCESS_WRITE); - if (ret < 0) { - TraceError(TRACE_QDMA, "%s Failed to program completion context! ret : %d", q.name, ret); - status = hw.qdma_get_error_code(ret); - goto ErrExit; - } - } - - /* Pre-fetch context programming */ - if (q.type == queue_type::STREAMING) { - qdma_descq_prefetch_ctxt pf_ctx = {}; - pf_ctx.bufsz_idx = q.c2h_q.user_conf.c2h_buff_sz_index; - pf_ctx.valid = true; - pf_ctx.pfch_en = q.c2h_q.user_conf.pfch_en; - pf_ctx.bypass = q.c2h_q.user_conf.pfch_bypass_en; - - ret = hw.qdma_pfetch_ctx_conf((void *)this, q.idx_abs, &pf_ctx, QDMA_HW_ACCESS_WRITE); - if (ret < 0) { - TraceError(TRACE_QDMA, "%s Failed to program prefetch context!, ret : %d", q.name, ret); - status = hw.qdma_get_error_code(ret); - goto ErrExit; - } - } - - return STATUS_SUCCESS; - -ErrExit: - clear_queue_contexts(true, q.idx_abs, QDMA_HW_ACCESS_CLEAR); - - if (q.c2h_q.is_cmpt_valid == true) { - clear_cmpt_contexts(q.idx_abs, QDMA_HW_ACCESS_CLEAR); - } - - if (q.type == queue_type::STREAMING) { - clear_pfetch_contexts(q.idx_abs, QDMA_HW_ACCESS_CLEAR); - } - - return status; -} - -NTSTATUS qdma_device::queue_program( - queue_pair& q) -{ - TraceVerbose(TRACE_QDMA, "%s programming...", q.name); - - auto status = set_h2c_ctx(q); - if (!NT_SUCCESS(status)) { - return status; - } - - status = set_c2h_ctx(q); - if (!NT_SUCCESS(status)) { - /* Clear H2C queue contexts */ - clear_queue_contexts(false, q.idx_abs, QDMA_HW_ACCESS_CLEAR); - return status; - } - - return status; -} - -/* ---------- public qdma member function implemenations ---------- */ - -NTSTATUS qdma_device::init(qdma_drv_config conf) -{ - NTSTATUS status; - - TraceInfo(TRACE_QDMA, "Xilinx QDMA PF Reference Driver v%u.%u.%u", - qdma_version.major, qdma_version.minor, qdma_version.patch); - - InterlockedExchange(&qdma_device_state, device_state::DEVICE_INIT); - - drv_conf = conf; - status = WdfSpinLockCreate(WDF_NO_OBJECT_ATTRIBUTES, ®ister_access_lock); - if (!NT_SUCCESS(status)) { - TraceError(TRACE_QDMA, "Register access lock creation failed!"); - return status; - } - - return STATUS_SUCCESS; -} - -ULONG qdma_device::qdma_conf_reg_read(size_t offset) -{ - return pcie.conf_reg_read(offset); -} - -void qdma_device::qdma_conf_reg_write(size_t offset, ULONG data) -{ - pcie.conf_reg_write(offset, data); -} - -NTSTATUS qdma_device::read_bar( - qdma_bar_type bar_type, - size_t offset, - void* data, - size_t size) -{ - return pcie.read_bar(bar_type, offset, data, size); -} - -NTSTATUS qdma_device::write_bar( - qdma_bar_type bar_type, - size_t offset, - void* data, - size_t size) -{ - return pcie.write_bar(bar_type, offset, data, size); -} - -NTSTATUS qdma_device::get_bar_info( - qdma_bar_type bar_type, - PVOID &bar_base, - size_t &bar_length) -{ - return pcie.get_bar_info(bar_type, bar_base, bar_length); -} - -NTSTATUS qdma_device::qdma_is_queue_in_range(UINT16 qid) -{ - if (qid >= drv_conf.qsets_max) { - TraceError(TRACE_QDMA, "%s: Provided qid : %u is more than allocated : %u", dev_conf.name, qid, drv_conf.qsets_max); - return STATUS_INVALID_PARAMETER; - } - - return STATUS_SUCCESS; -} - -_IRQL_requires_(PASSIVE_LEVEL) -NTSTATUS qdma_device::qdma_get_queues_state( - _In_ UINT16 qid, - _Out_ enum queue_state *qstate, - _Out_writes_(str_maxlen) CHAR *str, - _In_ size_t str_maxlen) -{ - NTSTATUS status = STATUS_SUCCESS; - - if (qid >= drv_conf.qsets_max) { - TraceError(TRACE_QDMA, "%s: Invalid Qid %d provided", dev_conf.name, qid); - return STATUS_INVALID_PARAMETER; - } - if (qstate == NULL) { - TraceError(TRACE_QDMA, "%s: qstate is NULL", dev_conf.name); - return STATUS_INVALID_PARAMETER; - } - - switch (queue_pairs[qid].state) { - case queue_state::QUEUE_ADDED: - *qstate = queue_state::QUEUE_ADDED; - if (str != NULL) - status = RtlStringCchCopyA(str, str_maxlen, "QUEUE ADDED"); - break; - case queue_state::QUEUE_STARTED: - *qstate = queue_state::QUEUE_STARTED; - if (str != NULL) - status = RtlStringCchCopyA(str, str_maxlen, "QUEUE ACTIVE"); - break; - case queue_state::QUEUE_AVAILABLE: - *qstate = queue_state::QUEUE_AVAILABLE; - if (str != NULL) - status = RtlStringCchCopyA(str, str_maxlen, "QUEUE IS AVAILABLE"); - break; - case queue_state::QUEUE_BUSY: - *qstate = queue_state::QUEUE_BUSY; - if (str != NULL) - status = RtlStringCchCopyA(str, str_maxlen, "QUEUE BUSY"); - break; - default: - NT_ASSERT(FALSE); - *qstate = queue_state::QUEUE_INVALID_STATE; - if (str != NULL) - status = RtlStringCchCopyA(str, str_maxlen, ""); - break; - } - - return status; -} - -NTSTATUS qdma_device::qdma_set_qmax(UINT32 queue_max) -{ - INT32 queue_base = -1; - NTSTATUS status = STATUS_SUCCESS; - - LONG state = InterlockedCompareExchange(&qdma_device_state, - device_state::DEVICE_OFFLINE, - device_state::DEVICE_ONLINE); - if (state == device_state::DEVICE_OFFLINE) { - TraceError(TRACE_QDMA, "%s: Device OFFLINE, Can't proceed.", dev_conf.name); - return STATUS_UNSUCCESSFUL; - } - - UINT32 active_queues = qdma_get_active_queue_count(dma_dev_index); - if (active_queues) { - TraceError(TRACE_QDMA, "%s: Not possible to update qmax, %u queues are active", - dev_conf.name, active_queues); - status = STATUS_INVALID_PARAMETER; - goto ErrExit; - } - - int rv = qdma_dev_update(dma_dev_index, dev_conf.dev_sbdf.sbdf.fun_no, queue_max, &queue_base); - if (rv < 0) { - TraceError(TRACE_QDMA, "%s: qdma_dev_update() Failed! %d", dev_conf.name, rv); - status = hw.qdma_get_error_code(rv); - goto ErrExit; - } - - rv = qdma_dev_qinfo_get(dma_dev_index, dev_conf.dev_sbdf.sbdf.fun_no, &queue_base, &queue_max); - if (rv < 0) { - TraceError(TRACE_QDMA, "%s: qdma_dev_qinfo_get() Failed! %d", dev_conf.name, rv); - status = hw.qdma_get_error_code(rv); - goto ErrExit; - } - - TraceInfo(TRACE_QDMA, "%s: qmax updated. Old qmax : %u, New qmax : %u, " - "Old qbase : %d, New qbase : %d", - dev_conf.name, drv_conf.qsets_max, queue_max, qbase, queue_base); - - drv_conf.qsets_max = queue_max; - qbase = queue_base; - - if (queue_pairs) { - qdma_memfree(queue_pairs); - queue_pairs = nullptr; - } - - status = init_dma_queues(); - if (!NT_SUCCESS(status)) { - TraceError(TRACE_QDMA, "%s: init_dma_queues() failed! %!STATUS!", dev_conf.name, status); - drv_conf.qsets_max = 0u; - qbase = -1; - } - - status = init_func(); - if (!NT_SUCCESS(status)) { - TraceError(TRACE_QDMA, "%s: init_func() failed! %!STATUS!", dev_conf.name, status); - return status; - } - -ErrExit: - InterlockedExchange(&qdma_device_state, device_state::DEVICE_ONLINE); - return status; -} - -NTSTATUS qdma_device::validate_qconfig(queue_config& conf) -{ - /** check if the requested mode is enabled? - * the request modes are read from the HW. - * before serving any request, first check if the - * HW has the capability or not, else return error - */ - - if ((conf.is_st && !dev_conf.dev_info.st_en) || - (!conf.is_st && !dev_conf.dev_info.mm_en)) { - TraceError(TRACE_QDMA, "%s: %s mode is not enabled in device", - dev_conf.name, (conf.is_st ? "ST" : "MM")); - return STATUS_INVALID_PARAMETER; - } - - - if ((hw_version_info.ip_type == EQDMA_SOFT_IP) && - (hw_version_info.vivado_release >= QDMA_VIVADO_2020_2)) { - - if (dev_conf.dev_info.desc_eng_mode == QDMA_DESC_ENG_BYPASS_ONLY) { - TraceError(TRACE_QDMA, "Bypass only mode design is not supported"); - return STATUS_NOT_SUPPORTED; - } - - if ((conf.desc_bypass_en == true) && - (dev_conf.dev_info.desc_eng_mode == QDMA_DESC_ENG_INTERNAL_ONLY)) { - TraceError(TRACE_QDMA, - "Queue config in bypass " - "mode not supported on internal only mode design"); - return STATUS_NOT_SUPPORTED; - } - } - - - if ((conf.h2c_ring_sz_index >= QDMA_GLBL_CSR_REG_CNT) || - (conf.c2h_ring_sz_index >= QDMA_GLBL_CSR_REG_CNT) || - (conf.c2h_buff_sz_index >= QDMA_GLBL_CSR_REG_CNT) || - (conf.c2h_th_cnt_index >= QDMA_GLBL_CSR_REG_CNT) || - (conf.c2h_timer_cnt_index >= QDMA_GLBL_CSR_REG_CNT)) { - TraceError(TRACE_QDMA, "%s: One or more invalid global CSR indexes provided", dev_conf.name); - return STATUS_INVALID_PARAMETER; - } - - if (conf.cmpt_sz >= qdma_desc_sz::QDMA_DESC_SZ_MAX) { - TraceError(TRACE_QDMA, "%s: Invalid completion descriptor size provided", dev_conf.name); - return STATUS_INVALID_PARAMETER; - } - - if (conf.trig_mode >= qdma_trig_mode::QDMA_TRIG_MODE_MAX) { - TraceError(TRACE_QDMA, "%s: Invalid Trigger mode provided", dev_conf.name); - return STATUS_INVALID_PARAMETER; - } - - if ((conf.en_mm_cmpl) && (!dev_conf.dev_info.mm_cmpt_en)) { - TraceError(TRACE_QDMA, "%s: MM Completion not supported in HW", dev_conf.name); - return STATUS_NOT_SUPPORTED; - } - - if ((conf.cmpl_ovf_dis) && (!dev_conf.dev_info.cmpt_ovf_chk_dis)) { - TraceError(TRACE_QDMA, "%s: Completion overflow disable option not supported in HW", dev_conf.name); - return STATUS_NOT_SUPPORTED; - } - - if (hw_version_info.ip_type == QDMA_VERSAL_HARD_IP) { - /** 64B Descriptors not supportd for the versal hard IP (i.e., s80 device) */ - if ((conf.sw_desc_sz == static_cast(qdma_desc_sz::QDMA_DESC_SZ_64B)) || - (conf.cmpt_sz == qdma_desc_sz::QDMA_DESC_SZ_64B)) { - TraceError(TRACE_QDMA, "%s: 64B Descriptor not supported for Versal Hard IP(S80)", dev_conf.name); - return STATUS_NOT_SUPPORTED; - } - - if ((conf.trig_mode == qdma_trig_mode::QDMA_TRIG_MODE_USER_TIMER_COUNT) || - (conf.trig_mode == qdma_trig_mode::QDMA_TRIG_MODE_USER_COUNT)) { - TraceError(TRACE_QDMA, "%s: Counter, Timer+Counter modes are not supported for Versal Hard IP(S80)", dev_conf.name); - return STATUS_NOT_SUPPORTED; - } - } - - return STATUS_SUCCESS; -} - -NTSTATUS qdma_device::qdma_add_queue(UINT16 qid, queue_config& conf) -{ - if (qid >= drv_conf.qsets_max) { - TraceError(TRACE_QDMA, "%s: Invalid Qid %d provided", dev_conf.name, qid); - return STATUS_INVALID_PARAMETER; - } - - NTSTATUS status = validate_qconfig(conf); - if (!NT_SUCCESS(status)) - return status; - - auto& q = queue_pairs[qid]; - - auto old_state = InterlockedCompareExchange(&q.state, - queue_state::QUEUE_BUSY, - queue_state::QUEUE_AVAILABLE); - if (old_state != queue_state::QUEUE_AVAILABLE) { - TraceError(TRACE_QDMA, "%s : Queue %u is not available, q_state %d!", dev_conf.name, qid, q.state); - return STATUS_UNSUCCESSFUL; - } - - TraceVerbose(TRACE_QDMA, "%s: Adding the queue : %u", dev_conf.name, qid); - - status = q.create(conf); - if (!NT_SUCCESS(status)) { - TraceError(TRACE_QDMA, "%s: Failed to allocate resource for queue %u, status: %!STATUS!", dev_conf.name, qid, status); - goto ErrExit; - } - - /* Increament resource manager active queue count */ - inc_queue_pair_count(q.c2h_q.is_cmpt_valid); - - InterlockedExchange(&q.state, queue_state::QUEUE_ADDED); - - TraceInfo(TRACE_QDMA, "%s: queue added : %s", dev_conf.name, q.name); - - return status; - -ErrExit: - InterlockedExchange(&q.state, queue_state::QUEUE_AVAILABLE); - return status; -} - -NTSTATUS qdma_device::qdma_start_queue(UINT16 qid) -{ - if (qid >= drv_conf.qsets_max) { - TraceError(TRACE_QDMA, "%s: Invalid Qid %d provided", dev_conf.name, qid); - return STATUS_INVALID_PARAMETER; - } - - auto& q = queue_pairs[qid]; - - auto old_state = InterlockedCompareExchange(&q.state, - queue_state::QUEUE_BUSY, - queue_state::QUEUE_ADDED); - if (old_state != queue_state::QUEUE_ADDED) { - TraceError(TRACE_QDMA, "%s invalid state, q_state %d", q.name, q.state); - return STATUS_UNSUCCESSFUL; - } - - TraceVerbose(TRACE_QDMA, "%s: Starting the queue : %u", dev_conf.name, qid); - - bool is_intr_vec_allocated = false; - NTSTATUS status = STATUS_SUCCESS; - - if (drv_conf.operation_mode != queue_op_mode::POLL_MODE) { - auto vec = assign_interrupt_vector(q); - if (vec < 0) { - TraceError(TRACE_QDMA, "%s Failed to assign interrupt vector", q.name); - status = STATUS_UNSUCCESSFUL; - goto ErrExit; - } - - q.h2c_q.lib_config.vector_id = q.c2h_q.lib_config.vector_id = vec; - is_intr_vec_allocated = true; - - TraceInfo(TRACE_QDMA, "%s Allocated vector Id : %u", q.name, q.c2h_q.lib_config.vector_id); - } - - /* H2C request process function registration */ - poll_op req_op; - bool is_st = q.h2c_q.user_conf.is_st; - req_op.fn = is_st ? process_st_h2c_req : process_mm_h2c_req; - req_op.arg = &queue_pairs[qid]; - - q.h2c_q.req_proc_entry = th_mgr.register_poll_function(req_op); - if (nullptr == q.h2c_q.req_proc_entry) { - TraceError(TRACE_QDMA, "%s Failed to register H2C request process method", q.name); - status = STATUS_UNSUCCESSFUL; - goto ErrExit; - } - - /* C2H request process function registration */ - is_st = q.c2h_q.user_conf.is_st; - if (is_st == false) { - req_op.fn = process_mm_c2h_req; - - q.c2h_q.req_proc_entry = th_mgr.register_poll_function(req_op); - if (nullptr == q.c2h_q.req_proc_entry) { - TraceError(TRACE_QDMA, "%s Failed to register C2H request process method", q.name); - status = STATUS_UNSUCCESSFUL; - goto ErrExit; - } - } - - /* H2C Poll function registration */ - poll_op compl_op; - is_st = q.h2c_q.user_conf.is_st; - compl_op.fn = is_st ? service_h2c_st_queue : service_h2c_mm_queue; - compl_op.arg = &queue_pairs[qid]; - - q.h2c_q.poll_entry = th_mgr.register_poll_function(compl_op); - if (nullptr == q.h2c_q.poll_entry) { - TraceError(TRACE_QDMA, "%s Failed to register H2C Completion poll method", q.name); - status = STATUS_UNSUCCESSFUL; - goto ErrExit; - } - - /* C2H Poll function registration */ - is_st = q.c2h_q.user_conf.is_st; - compl_op.fn = is_st ? service_c2h_st_queue : service_c2h_mm_queue; - - q.c2h_q.poll_entry = th_mgr.register_poll_function(compl_op); - if (nullptr == q.c2h_q.poll_entry) { - TraceError(TRACE_QDMA, "%s Failed to register C2H Completion poll method", q.name); - status = STATUS_UNSUCCESSFUL; - goto ErrExit; - } - - status = queue_program(q); - if (!NT_SUCCESS(status)) { - TraceError(TRACE_QDMA, "%s failed to program contexts, status : %!STATUS!", q.name, status); - goto ErrExit; - } - - dump(this, q.type, q.idx_abs); - - q.init_csr(); - - InterlockedExchange(&q.state, queue_state::QUEUE_STARTED); - - TraceInfo(TRACE_QDMA, "%s: queue started : %s", dev_conf.name, q.name); - - return status; - -ErrExit: - if (nullptr != q.h2c_q.poll_entry) { - th_mgr.unregister_poll_function(q.h2c_q.req_proc_entry); - q.h2c_q.req_proc_entry = nullptr; - } - - if (q.c2h_q.req_proc_entry) { - if (q.type == queue_type::MEMORY_MAPPED) { - th_mgr.unregister_poll_function(q.c2h_q.req_proc_entry); - q.c2h_q.req_proc_entry = nullptr; - } - } - - if (nullptr != q.h2c_q.poll_entry) { - th_mgr.unregister_poll_function(q.h2c_q.poll_entry); - q.h2c_q.poll_entry = nullptr; - } - - if (nullptr != q.c2h_q.poll_entry) { - th_mgr.unregister_poll_function(q.c2h_q.poll_entry); - q.c2h_q.poll_entry = nullptr; - } - - if (is_intr_vec_allocated) - free_interrupt_vector(q, q.c2h_q.lib_config.vector_id); - - InterlockedExchange(&q.state, queue_state::QUEUE_ADDED); - return status; -} - -NTSTATUS qdma_device::qdma_stop_queue(UINT16 qid) -{ - if (qid >= drv_conf.qsets_max) { - TraceError(TRACE_QDMA, "%s: Invalid Qid %d provided", dev_conf.name, qid); - return STATUS_INVALID_PARAMETER; - } - - NTSTATUS status = STATUS_SUCCESS; - - auto& q = queue_pairs[qid]; - - TraceVerbose(TRACE_QDMA, "%s: Stopping the queue : %u", dev_conf.name, qid); - - /* Stop further traffic on the queue */ - auto old_state = InterlockedCompareExchange(&q.state, - queue_state::QUEUE_BUSY, - queue_state::QUEUE_STARTED); - if (old_state != queue_state::QUEUE_STARTED) { - TraceError(TRACE_QDMA, "%s invalid state, q_state %d", q.name, q.state); - return STATUS_UNSUCCESSFUL; - } - - /* Wait till incoming traffic stops & let HW finish any pending jobs */ - LARGE_INTEGER wait_time; - wait_time.QuadPart = WDF_REL_TIMEOUT_IN_MS(2); - /** Re-adjust the system tick for better resolution - * - * As the system tick in windows can go up to 15.625 msec - * the delay is varying between 1 msec to 15 msec - */ - ExSetTimerResolution((ULONG)(2 * WDF_TIMEOUT_TO_MS), TRUE); - - KeDelayExecutionThread(KernelMode, FALSE, &wait_time); - - /** Revert back the system tick to default */ - ExSetTimerResolution(0, FALSE); - - th_mgr.unregister_poll_function(q.h2c_q.poll_entry); - th_mgr.unregister_poll_function(q.c2h_q.poll_entry); - - th_mgr.unregister_poll_function(q.h2c_q.req_proc_entry); - if (q.type == queue_type::MEMORY_MAPPED) - th_mgr.unregister_poll_function(q.c2h_q.req_proc_entry); - - q.h2c_q.poll_entry = nullptr; - q.c2h_q.poll_entry = nullptr; - - if (drv_conf.operation_mode != queue_op_mode::POLL_MODE) - free_interrupt_vector(q, q.c2h_q.lib_config.vector_id); - - /* Drain any pending requests */ - q.flush_queue(); - - /* Invalidate the contexts */ - status = clear_contexts(q, true); - if (!NT_SUCCESS(status)) { - TraceError(TRACE_QDMA, "%s Failed to invalidate the context", q.name); - /* Continue further even in error scenario */ - } - - InterlockedExchange(&q.state, queue_state::QUEUE_ADDED); - - TraceInfo(TRACE_QDMA, "%s: queue stopped : %s", dev_conf.name, q.name); - - return STATUS_SUCCESS; -} - -NTSTATUS qdma_device::qdma_remove_queue(UINT16 qid) -{ - if (qid >= drv_conf.qsets_max) { - TraceError(TRACE_QDMA, "%s: Invalid Qid %d provided", dev_conf.name, qid); - return STATUS_INVALID_PARAMETER; - } - - auto& q = queue_pairs[qid]; - - TraceVerbose(TRACE_QDMA, "%s: Removing the queue : %u", dev_conf.name, qid); - - auto old_state = InterlockedCompareExchange(&q.state, - queue_state::QUEUE_BUSY, - queue_state::QUEUE_ADDED); - if (old_state != queue_state::QUEUE_ADDED) { - TraceError(TRACE_QDMA, "%s invalid state, q_state %d", q.name, q.state); - return STATUS_UNSUCCESSFUL; - } - - /* Clear queue context */ - NTSTATUS status = clear_contexts(q); - if (!NT_SUCCESS(status)) { - TraceError(TRACE_QDMA, "%s Failed to clear the context", q.name); - /* Continue further even in error scenario */ - } - - auto is_cmpt_valid = q.c2h_q.is_cmpt_valid; - - q.destroy(); - - /* Decreament resource manager active queue count */ - dec_queue_pair_count(is_cmpt_valid); - - InterlockedExchange(&q.state, queue_state::QUEUE_AVAILABLE); - - TraceInfo(TRACE_QDMA, "%s: queue removed : %s", dev_conf.name, q.name); - - return STATUS_SUCCESS; -} - -NTSTATUS qdma_device::qdma_enqueue_mm_request( - UINT16 qid, - WDF_DMA_DIRECTION direction, - PSCATTER_GATHER_LIST sg_list, - LONGLONG device_offset, - dma_completion_cb compl_cb, - VOID *priv) -{ - if ((qid >= drv_conf.qsets_max) || (compl_cb == nullptr) || - (sg_list == nullptr)) { - TraceError(TRACE_QDMA, "%s : Incorrect Parameters, qid : %d, " - "compl_cb : %p, sg_list : %p", dev_conf.name, qid, compl_cb, sg_list); - return STATUS_INVALID_PARAMETER; - } - - auto& q = queue_pairs[qid]; - - if (q.state != queue_state::QUEUE_STARTED) { - TraceError(TRACE_QDMA, "%s invalid state, q_state %d", q.name, q.state); - return STATUS_INVALID_DEVICE_STATE; - } - - if (q.type != queue_type::MEMORY_MAPPED) { - TraceError(TRACE_QDMA, "%s is not configured in MM mode!", q.name); - return STATUS_ACCESS_VIOLATION; - } - - TraceVerbose(TRACE_QDMA, "%s enqueue request", q.name); - - dma_request request; - - request.is_st = false; - request.direction = direction; - request.sg_list = sg_list; - request.device_offset = device_offset; - request.compl_cb = compl_cb; - request.priv = priv; - request.sg_index = 0; - request.offset_idx = 0; - - NTSTATUS status = q.enqueue_dma_request(&request); - if (!NT_SUCCESS(status)) { - TraceError(TRACE_QDMA, "%s Failed to enqueue the MM request, Status : %!STATUS!", q.name, status); - return status; - } - - return status; -} - -NTSTATUS qdma_device::qdma_enqueue_st_tx_request( - UINT16 qid, - PSCATTER_GATHER_LIST sg_list, - dma_completion_cb compl_cb, - VOID *priv) -{ - if ((qid >= drv_conf.qsets_max) || (compl_cb == nullptr) || - (sg_list == nullptr)) { - TraceError(TRACE_QDMA, "%s : Incorrect Parameters, qid : %d, " - "compl_cb : %p, sg_list : %p", dev_conf.name, qid, compl_cb, sg_list); - return STATUS_INVALID_PARAMETER; - } - - auto& q = queue_pairs[qid]; - - if (q.state != queue_state::QUEUE_STARTED) { - TraceError(TRACE_QDMA, "%s invalid state, q_state %d", q.name, q.state); - return STATUS_INVALID_DEVICE_STATE; - } - - if (q.type != queue_type::STREAMING) { - TraceError(TRACE_QDMA, "Queue %d is not configured in ST mode!", qid); - return STATUS_ACCESS_VIOLATION; - } - - TraceVerbose(TRACE_QDMA, "%s TX enqueue request", q.name); - - dma_request request; - - request.is_st = true; - request.direction = WdfDmaDirectionWriteToDevice; - request.sg_list = sg_list; - request.compl_cb = compl_cb; - request.priv = priv; - request.sg_index = 0; - request.offset_idx = 0; - - NTSTATUS status = q.enqueue_dma_request(&request); - if (!NT_SUCCESS(status)) { - TraceError(TRACE_QDMA, "%s Failed to enqueue the ST TX request, Status : %!STATUS!", q.name, status); - return status; - } - - return STATUS_SUCCESS; -} - -NTSTATUS qdma_device::qdma_enqueue_st_rx_request( - UINT16 qid, - size_t length, - st_rx_completion_cb compl_cb, - VOID *priv) -{ - if ((qid >= drv_conf.qsets_max) || (compl_cb == nullptr)) { - TraceError(TRACE_QDMA, "%s: Incorrect Parameters, qid : %d, compl_cb : %p len : %Iu", - dev_conf.name, qid, compl_cb, length); - return STATUS_INVALID_PARAMETER; - } - - auto& q = queue_pairs[qid]; - - if (q.state != queue_state::QUEUE_STARTED) { - TraceError(TRACE_QDMA, "%s invalid state, q_state %d", q.name, q.state); - return STATUS_INVALID_DEVICE_STATE; - } - - if (q.type != queue_type::STREAMING) { - TraceError(TRACE_QDMA, "Queue %d is not configured in ST mode!", qid); - return STATUS_ACCESS_VIOLATION; - } - - TraceVerbose(TRACE_QDMA, "%s RX enqueue request", q.name); - - NTSTATUS status = q.enqueue_dma_request(length, compl_cb, priv); - if (!NT_SUCCESS(status)) { - TraceError(TRACE_QDMA, "%s Failed to enqueue the ST RX request, Status : %!STATUS!", q.name, status); - } - - return status; -} - -NTSTATUS qdma_device::qdma_retrieve_st_udd_data(UINT16 qid, void *addr, UINT8 *buf, UINT32 *len) -{ - if (qid >= drv_conf.qsets_max) { - TraceError(TRACE_QDMA, "%s: Invalid Qid %d provided", dev_conf.name, qid); - return STATUS_INVALID_PARAMETER; - } - - if ((addr == nullptr) || (buf == nullptr) || (len == nullptr)) - return STATUS_INVALID_PARAMETER; - - auto& q = queue_pairs[qid]; - - if (q.state != queue_state::QUEUE_STARTED) { - TraceError(TRACE_QDMA, "%s invalid state, q_state %d", q.name, q.state); - return STATUS_INVALID_DEVICE_STATE; - } - - if (q.type != queue_type::STREAMING) { - TraceError(TRACE_QDMA, "Queue %d is not configured in ST mode!", qid); - return STATUS_ACCESS_VIOLATION; - } - - TraceVerbose(TRACE_QDMA, "%s Retrieving UDD data", q.name); - - return q.read_st_udd_data(addr, buf, len); -} - -NTSTATUS qdma_device::qdma_retrieve_last_st_udd_data(UINT16 qid, UINT8 *buf, UINT32 *len) -{ - if (qid >= drv_conf.qsets_max) { - TraceError(TRACE_QDMA, "%s: Invalid Qid %d provided", dev_conf.name, qid); - return STATUS_INVALID_PARAMETER; - } - - if ((buf == nullptr) || (len == nullptr)) - return STATUS_INVALID_PARAMETER; - - auto& q = queue_pairs[qid]; - - if (q.state != queue_state::QUEUE_STARTED) { - TraceError(TRACE_QDMA, "%s invalid state, q_state %d", q.name, q.state); - return STATUS_INVALID_DEVICE_STATE; - } - - if (q.type != queue_type::STREAMING) { - TraceError(TRACE_QDMA, "Queue %d is not configured in ST mode!", qid); - return STATUS_ACCESS_VIOLATION; - } - - TraceVerbose(TRACE_QDMA, "%s Reading latest UDD data", q.name); - - void *udd_addr = q.get_last_udd_addr(); - - return q.read_st_udd_data(udd_addr, buf, len); -} - -NTSTATUS qdma_device::qdma_queue_desc_dump(qdma_desc_info *desc_info) -{ - if (desc_info->qid >= drv_conf.qsets_max) { - TraceError(TRACE_QDMA, "%s: Invalid Qid %d provided", dev_conf.name, desc_info->qid); - return STATUS_INVALID_PARAMETER; - } - - if ((desc_info == nullptr) || (desc_info->pbuffer == nullptr) || (desc_info->buffer_sz == 0)) - return STATUS_INVALID_PARAMETER; - - auto& q = queue_pairs[desc_info->qid]; - - auto old_state = InterlockedCompareExchange(&q.state, - queue_state::QUEUE_BUSY, - queue_state::QUEUE_ADDED); - if (old_state == queue_state::QUEUE_AVAILABLE) { - TraceError(TRACE_QDMA, "Queue %u is not added or started to get dump", desc_info->qid); - return STATUS_UNSUCCESSFUL; - } - - TraceVerbose(TRACE_QDMA, "%s descripor data dump", q.name); - - NTSTATUS status = q.desc_dump(desc_info); - - InterlockedExchange(&q.state, old_state); - - return status; -} - -NTSTATUS qdma_device::qdma_read_mm_cmpt_data(qdma_cmpt_info *cmpt_info) -{ - if (cmpt_info->qid >= drv_conf.qsets_max) { - TraceError(TRACE_QDMA, "%s: Invalid Qid %d provided", dev_conf.name, cmpt_info->qid); - return STATUS_INVALID_PARAMETER; - } - - if ((cmpt_info == nullptr) || (cmpt_info->pbuffer == nullptr) || (cmpt_info->buffer_len == 0)) - return STATUS_INVALID_PARAMETER; - - auto& q = queue_pairs[cmpt_info->qid]; - - if (q.state != queue_state::QUEUE_STARTED) { - TraceError(TRACE_QDMA, "%s invalid state, q_state %d", q.name, q.state); - return STATUS_INVALID_DEVICE_STATE; - } - - if (q.type != queue_type::MEMORY_MAPPED) { - TraceError(TRACE_QDMA, "Queue %d is not configured in MM mode!", cmpt_info->qid); - return STATUS_ACCESS_VIOLATION; - } - - TraceVerbose(TRACE_QDMA, "%s Read MM completion data", q.name); - - return q.read_mm_cmpt_data(cmpt_info); -} - -NTSTATUS qdma_device::qdma_queue_context_read(UINT16 qid, enum qdma_dev_q_type ctx_type, struct qdma_descq_context *ctxt) -{ - if ((qid >= drv_conf.qsets_max) || - (ctx_type >= qdma_dev_q_type::QDMA_DEV_Q_TYPE_MAX) || - (ctxt == nullptr)) { - TraceError(TRACE_QDMA, "%s: Incorrect Parameters, qid : %d, ctx_type : %d, ctxt : %p", - dev_conf.name, qid, ctx_type, ctxt); - return STATUS_INVALID_PARAMETER; - } - - auto& q = queue_pairs[qid]; - - if (q.state != queue_state::QUEUE_STARTED) { - TraceError(TRACE_QDMA, "%s invalid state, q_state %d", q.name, q.state); - return STATUS_INVALID_DEVICE_STATE; - } - - uint8_t is_c2h = (ctx_type == qdma_dev_q_type::QDMA_DEV_Q_TYPE_C2H) ? true : false; - uint16_t hw_qid = q.idx_abs; - int ret; - bool dump = false; - - if (ctx_type != qdma_dev_q_type::QDMA_DEV_Q_TYPE_CMPT) { - ret = hw.qdma_sw_ctx_conf(this, is_c2h, hw_qid, &ctxt->sw_ctxt, QDMA_HW_ACCESS_READ); - if (ret < 0) { - TraceError(TRACE_QDMA, "%s Failed to read SW context, ret : %d", q.name, ret); - return hw.qdma_get_error_code(ret); - } - - ret = hw.qdma_hw_ctx_conf(this, is_c2h, hw_qid, &ctxt->hw_ctxt, QDMA_HW_ACCESS_READ); - if (ret < 0) { - TraceError(TRACE_QDMA, "%s Failed to read HW context, ret : %d", q.name, ret); - return hw.qdma_get_error_code(ret); - } - - ret = hw.qdma_credit_ctx_conf(this, is_c2h, hw_qid, &ctxt->cr_ctxt, QDMA_HW_ACCESS_READ); - if (ret < 0) { - TraceError(TRACE_QDMA, "%s Failed to read credit context, ret : %d", q.name, ret); - return hw.qdma_get_error_code(ret); - } - - if ((q.type == queue_type::STREAMING) && (is_c2h)) { - ret = hw.qdma_pfetch_ctx_conf(this, hw_qid, &ctxt->pfetch_ctxt, QDMA_HW_ACCESS_READ); - if (ret < 0) { - TraceError(TRACE_QDMA, "%s Failed to read pre-fetch context, ret : %d", q.name, ret); - return hw.qdma_get_error_code(ret); - } - } - - dump = true; - } - - if (((q.type == queue_type::STREAMING) && (is_c2h)) || - ((q.type == queue_type::MEMORY_MAPPED) && (ctx_type == qdma_dev_q_type::QDMA_DEV_Q_TYPE_CMPT) && - (dev_conf.dev_info.mm_cmpt_en) && (q.c2h_q.user_conf.en_mm_cmpl))) { - - ret = hw.qdma_cmpt_ctx_conf(this, hw_qid, &ctxt->cmpt_ctxt, QDMA_HW_ACCESS_READ); - if (ret < 0) { - TraceError(TRACE_QDMA, "%s Failed to read completion " - "context, ret : %d", q.name, ret); - return hw.qdma_get_error_code(ret); - } - dump = true; - } - - if (!dump) - return STATUS_UNSUCCESSFUL; - - return STATUS_SUCCESS; -} - -NTSTATUS qdma_device::qdma_intr_context_read(UINT8 ring_idx_abs, struct qdma_indirect_intr_ctxt *ctxt) -{ - int ret; - - if (drv_conf.operation_mode != queue_op_mode::INTR_COAL_MODE) - return STATUS_ACCESS_VIOLATION; - - ret = hw.qdma_indirect_intr_ctx_conf(this, ring_idx_abs, ctxt, QDMA_HW_ACCESS_READ); - if (ret < 0) { - TraceError(TRACE_QDMA, "%s : Failed to read interrupt context for ring index %d!, ret : %d", - dev_conf.name, ring_idx_abs, ret); - return hw.qdma_get_error_code(ret); - } - - return STATUS_SUCCESS; -} - -NTSTATUS qdma_device::qdma_queue_dump_context(qdma_ctx_info *ctx_info) -{ - if (ctx_info->qid >= drv_conf.qsets_max) { - TraceError(TRACE_QDMA, "%s: Invalid Qid %d provided", dev_conf.name, ctx_info->qid); - return STATUS_INVALID_PARAMETER; - } - - if ((ctx_info == nullptr) || - (ctx_info->ring_type >= qdma_q_type::QDMA_Q_TYPE_MAX) || - (ctx_info->pbuffer == nullptr) || (ctx_info->buffer_sz == 0)) - return STATUS_INVALID_PARAMETER; - - queue_pair &q = queue_pairs[ctx_info->qid]; - - if (q.state != queue_state::QUEUE_STARTED) { - TraceError(TRACE_QDMA, "%s invalid state, q_state %d", q.name, q.state); - return STATUS_INVALID_DEVICE_STATE; - } - - uint8_t st = (q.type == queue_type::STREAMING) ? 1 : 0; - size_t len = 0; - NTSTATUS status; - bool dump = false; - - if (ctx_info->ring_type != qdma_q_type::QDMA_Q_TYPE_CMPT) { - dump = true; - } - else if ((q.type == queue_type::MEMORY_MAPPED) && - (ctx_info->ring_type == qdma_q_type::QDMA_Q_TYPE_CMPT) && - (dev_conf.dev_info.mm_cmpt_en) && (q.c2h_q.user_conf.en_mm_cmpl)) { - dump = true; - } - - if (!dump) - return STATUS_UNSUCCESSFUL; - - int ctx_len = hw.qdma_read_dump_queue_context(this, q.idx_abs, - st, (qdma_dev_q_type)ctx_info->ring_type, - ctx_info->pbuffer, (uint32_t)ctx_info->buffer_sz); - if (ctx_len < 0) { - TraceError(TRACE_QDMA, "%s hw.qdma_dump_queue_context failed : %d", q.name, ctx_len); - return hw.qdma_get_error_code(ctx_len); - } - - len = len + ctx_len; - - if (drv_conf.operation_mode == queue_op_mode::INTR_COAL_MODE) { - if (ctx_info->buffer_sz < len) { - TraceError(TRACE_QDMA, "%s Insufficient Buffer Length, " - "buffer has %lld bytes, needs %lld bytes", q.name, ctx_info->buffer_sz, len); - return STATUS_BUFFER_TOO_SMALL; - } - - UINT8 ring_index = 0; - if (ctx_info->ring_type == qdma_q_type::QDMA_Q_TYPE_H2C) - ring_index = (UINT8)q.h2c_q.lib_config.vector_id; - else if (ctx_info->ring_type != qdma_q_type::QDMA_Q_TYPE_MAX) - ring_index = (UINT8)q.c2h_q.lib_config.vector_id; - - struct qdma_indirect_intr_ctxt intr_ctxt; - status = qdma_intr_context_read(ring_index, &intr_ctxt); - if (!NT_SUCCESS(status)) - return status; - - int intr_len = hw.qdma_dump_intr_context(this, &intr_ctxt, ring_index, - &ctx_info->pbuffer[len], (uint32_t)(ctx_info->buffer_sz - len)); - if (intr_len < 0) { - TraceError(TRACE_QDMA, "%s : hw.qdma_dump_intr_context returned error : %d", dev_conf.name, intr_len); - return hw.qdma_get_error_code(intr_len); - } - - len = len + intr_len; - } - - ctx_info->ret_sz = len; - - return STATUS_SUCCESS; -} - -NTSTATUS qdma_device::qdma_intring_dump(qdma_intr_ring_info *intring_info) -{ - if (drv_conf.operation_mode != queue_op_mode::INTR_COAL_MODE) { - TraceError(TRACE_QDMA, "Interrupt ring is valid only in Aggregation Mode"); - return STATUS_INVALID_DEVICE_REQUEST; - } - - if ((intring_info == nullptr) || - (intring_info->pbuffer == nullptr) || (intring_info->buffer_len == 0)) { - TraceError(TRACE_QDMA, "Invalid Parameters"); - return STATUS_INVALID_PARAMETER; - } - - if ((intring_info->vec_id < irq_mgr.data_vector_id_start) || - (intring_info->vec_id >= irq_mgr.data_vector_id_end)) { - TraceError(TRACE_QDMA, "Invalid Vector ID : %d, Valid range : %u ~ %u", - intring_info->vec_id, irq_mgr.data_vector_id_start, irq_mgr.data_vector_id_end); - return STATUS_INVALID_PARAMETER; - } - - if (drv_conf.operation_mode != queue_op_mode::INTR_COAL_MODE) { - TraceError(TRACE_QDMA, "%s is not configured in Interrupt Aggregation mode", dev_conf.name); - return STATUS_INVALID_DEVICE_REQUEST; - } - - NTSTATUS status = irq_mgr.intr_q[intring_info->vec_id].intring_dump(intring_info); - - return status; -} - -NTSTATUS qdma_device::qdma_regdump(qdma_reg_dump_info *regdump_info) -{ - bool is_vf = false; - - if ((regdump_info == nullptr) || (regdump_info->pbuffer == nullptr) || (regdump_info->buffer_len == 0)) - return STATUS_INVALID_PARAMETER; - - int len = hw.qdma_dump_config_regs(this, is_vf, regdump_info->pbuffer, (uint32_t)regdump_info->buffer_len); - if (len < 0) { - TraceError(TRACE_QDMA, " %s : hw.qdma_dump_config_regs failed with err : %d", dev_conf.name, len); - return hw.qdma_get_error_code(len); - } - - regdump_info->ret_len = len; - return STATUS_SUCCESS; -} - -NTSTATUS qdma_device::qdma_get_qstats_info(qdma_qstat_info &qstats) -{ - INT32 queue_base = -1; /* qdma_dev_qinfo_get() requires qbase to be int pointer */ - - qdma_dev_qinfo_get(dma_dev_index, dev_conf.dev_sbdf.sbdf.fun_no, &queue_base, &qstats.qmax); - qstats.qbase = queue_base; - qstats.active_h2c_queues = - qdma_get_device_active_queue_count(dma_dev_index, dev_conf.dev_sbdf.sbdf.fun_no, QDMA_DEV_Q_TYPE_H2C); - qstats.active_c2h_queues = - qdma_get_device_active_queue_count(dma_dev_index, dev_conf.dev_sbdf.sbdf.fun_no, QDMA_DEV_Q_TYPE_C2H); - qstats.active_cmpt_queues = - qdma_get_device_active_queue_count(dma_dev_index, dev_conf.dev_sbdf.sbdf.fun_no, QDMA_DEV_Q_TYPE_CMPT); - - return STATUS_SUCCESS; -} - -NTSTATUS qdma_device::qdma_get_reg_info(qdma_reg_info* reg_info) -{ - int len = 0; - - if (reg_info == nullptr) - return STATUS_INVALID_PARAMETER; - - if (!hw.qdma_dump_reg_info) - return STATUS_NOT_SUPPORTED; - - len = hw.qdma_dump_reg_info(this, - reg_info->address, reg_info->reg_cnt, - reg_info->pbuffer, (int)reg_info->buf_len); - - if (len < 0) { - TraceError(TRACE_QDMA, "hw.qdma_dump_reg_info Failed with error : %d", len); - return STATUS_UNSUCCESSFUL; - } - - if (len == 0) { - TraceError(TRACE_QDMA, "Register %d is not present in the design", reg_info->address); - return STATUS_INVALID_PARAMETER; - } - - reg_info->ret_len = len; - - return STATUS_SUCCESS; -} - -NTSTATUS qdma_device::open(const WDFDEVICE device, WDFCMRESLIST resources, - const WDFCMRESLIST resources_translated) -{ - NTSTATUS status = STATUS_SUCCESS; - int ret = 0; - - wdf_dev = device; - - status = pcie.get_bdf(wdf_dev, dev_conf.dev_sbdf.val); - if (!NT_SUCCESS(status)) { - TraceError(TRACE_QDMA, "pcie.get_bdf failed! %!STATUS!", status); - return status; - } - - RtlStringCchPrintfA(dev_conf.name, - ARRAYSIZE(dev_conf.name), "qdma%02X%02X%x", - dev_conf.dev_sbdf.sbdf.bus_no, - dev_conf.dev_sbdf.sbdf.dev_no, - dev_conf.dev_sbdf.sbdf.fun_no); - - TraceInfo(TRACE_QDMA, "%04X:%02X:%02X.%X: func : %X, p/v 1/0", - dev_conf.dev_sbdf.sbdf.seg_no, dev_conf.dev_sbdf.sbdf.bus_no, - dev_conf.dev_sbdf.sbdf.dev_no, dev_conf.dev_sbdf.sbdf.fun_no, - dev_conf.dev_sbdf.sbdf.fun_no); - - status = pcie.map(resources_translated); - if (!NT_SUCCESS(status)) { - TraceError(TRACE_QDMA, "%s : pcie.map failed! %!STATUS!", dev_conf.name, status); - return status; - } - - status = pcie.assign_config_bar(drv_conf.cfg_bar); - if (!NT_SUCCESS(status)) { - TraceError(TRACE_QDMA, "%s: Failed to assign config BAR", dev_conf.name); - return status; - } - - ret = qdma_hw_access_init((void*)this, 0, &hw); - if (ret < 0) { - TraceError(TRACE_QDMA, "%s: Failed to initialize hw access", dev_conf.name); - return STATUS_UNSUCCESSFUL; - } - - /** Change device state to offline after acquiring the HW callbacks */ - InterlockedExchange(&qdma_device_state, device_state::DEVICE_OFFLINE); - - ret = hw.qdma_get_version((void *)this, QDMA_DEV_PF, &hw_version_info); - if (ret < 0) { - TraceError(TRACE_QDMA, "%s: qdma_get_version failed!, ret : %d", dev_conf.name, ret); - status = hw.qdma_get_error_code(ret); - goto ErrExit; - } - - status = assign_bar_types(); - if (!NT_SUCCESS(status)) { - TraceError(TRACE_QDMA, "%s : assign_bar_types failed! %!STATUS!", dev_conf.name, status); - goto ErrExit; - } - - ret = hw.qdma_get_device_attributes((void *)this, &dev_conf.dev_info); - if (ret < 0) { - TraceError(TRACE_QDMA, "%s: qdma_get_device_attributes failed!, ret : %d", dev_conf.name, ret); - status = hw.qdma_get_error_code(ret); - goto ErrExit; - } - - TraceInfo(TRACE_QDMA, "qdma_get_device_attributes: %s: num_pfs:%d, num_qs:%d, flr_present:%d, st_en:%d, " - "mm_en:%d, mm_cmpt_en:%d, mailbox_en:%d, mm_channel_max:%d, qid2vec_ctx:%d, ", - dev_conf.name, - dev_conf.dev_info.num_pfs, - dev_conf.dev_info.num_qs, - dev_conf.dev_info.flr_present, - dev_conf.dev_info.st_en, - dev_conf.dev_info.mm_en, - dev_conf.dev_info.mm_cmpt_en, - dev_conf.dev_info.mailbox_en, - dev_conf.dev_info.mm_channel_max, - dev_conf.dev_info.qid2vec_ctx); - - TraceInfo(TRACE_QDMA, "cmpt_ovf_chk_dis:%d, mailbox_intr:%d, sw_desc_64b:%d, cmpt_desc_64b:%d, " - "dynamic_bar:%d, legacy_intr:%d, cmpt_trig_count_timer:%d", - dev_conf.dev_info.cmpt_ovf_chk_dis, - dev_conf.dev_info.mailbox_intr, - dev_conf.dev_info.sw_desc_64b, - dev_conf.dev_info.cmpt_desc_64b, - dev_conf.dev_info.dynamic_bar, - dev_conf.dev_info.legacy_intr, - dev_conf.dev_info.cmpt_trig_count_timer); - - if ((dev_conf.dev_info.st_en == 0) && - (dev_conf.dev_info.mm_en == 0)) { - TraceError(TRACE_QDMA, "%s: None of the modes ( ST or MM) are enabled", dev_conf.name); - status = STATUS_INVALID_HW_PROFILE; - goto ErrExit; - } - - status = list_add_qdma_device_and_set_gbl_csr(); - if (!NT_SUCCESS(status)) { - TraceError(TRACE_QDMA, "%s: list_add_qdma_device_and_set_gbl_csr failed! %!STATUS!", dev_conf.name, status); - goto ErrExit; - } - - TraceInfo(TRACE_QDMA, "Driver is loaded in %s(%d) mode", - mode_name_list[drv_conf.operation_mode].name, drv_conf.operation_mode); - - status = init_resource_manager(); - if (!NT_SUCCESS(status)) { - TraceError(TRACE_QDMA, "%s: init_resource_manager failed! %!STATUS!", dev_conf.name, status); - goto ErrExit; - } - - status = init_os_resources(resources, resources_translated); - if (!NT_SUCCESS(status)) { - TraceError(TRACE_QDMA, "%s: init_os_resources() failed! %!STATUS!", dev_conf.name, status); - goto ErrExit; - } - - status = init_qdma_global(); - if (!NT_SUCCESS(status)) { - TraceError(TRACE_QDMA, "%s: init_qdma_global() failed! %!STATUS!", dev_conf.name, status); - goto ErrExit; - } - - status = init_func(); - if (!NT_SUCCESS(status)) { - TraceError(TRACE_QDMA, "%s: init_func() failed! %!STATUS!", dev_conf.name, status); - goto ErrExit; - } - - status = init_dma_queues(); - if (!NT_SUCCESS(status)) { - TraceError(TRACE_QDMA, "%s: init_dma_queues() failed! %!STATUS!", dev_conf.name, status); - goto ErrExit; - } - - if (drv_conf.operation_mode == queue_op_mode::INTR_COAL_MODE) { - status = init_interrupt_queues(); - if (!NT_SUCCESS(status)) { - TraceError(TRACE_QDMA, "%s: init_interrupt_queues() failed! %!STATUS!", dev_conf.name, status); - goto ErrExit; - } - } - - InterlockedExchange(&qdma_device_state, device_state::DEVICE_ONLINE); - - TraceInfo(TRACE_QDMA, "%s, %05x, qdma_device %p, ch %u, q %u.", - dev_conf.name, dev_conf.dev_sbdf.val, this, - dev_conf.dev_info.mm_channel_max, drv_conf.qsets_max); - - return status; - -ErrExit: - close(); - return status; -} - -void qdma_device::close() -{ - /** Make sure to not perform multiple cleanups on same device */ - if (qdma_device_state != device_state::DEVICE_INIT) { - - TraceInfo(TRACE_QDMA, "%04X:%02X:%02X.%X qdma_device 0x%p, %s.\n", - dev_conf.dev_sbdf.sbdf.seg_no, dev_conf.dev_sbdf.sbdf.bus_no, - dev_conf.dev_sbdf.sbdf.dev_no, dev_conf.dev_sbdf.sbdf.fun_no, - this, dev_conf.name); - - destroy_dma_queues(); - - destroy_func(); - - destroy_os_resources(); - - destroy_resource_manager(); - - list_remove_qdma_device(); - - pcie.unmap(); - - if (nullptr != register_access_lock) { - WdfObjectDelete(register_access_lock); - register_access_lock = nullptr; - } - InterlockedExchange(&qdma_device_state, device_state::DEVICE_INIT); - } -} - -bool qdma_device::qdma_is_device_online(void) -{ - if (qdma_device_state == device_state::DEVICE_ONLINE) - return true; - - return false; -} - -NTSTATUS qdma_device::qdma_read_csr_conf(qdma_glbl_csr_conf *conf) -{ - int ret; - - ret = hw.qdma_global_csr_conf((void *)this, 0, QDMA_GLOBAL_CSR_ARRAY_SZ, - conf->ring_sz, QDMA_CSR_RING_SZ, QDMA_HW_ACCESS_READ); - if (ret < 0) { - TraceError(TRACE_QDMA, "%s: Failed to read CSR global ring size, ret : %d", dev_conf.name, ret); - return hw.qdma_get_error_code(ret); - } - - ret = hw.qdma_global_csr_conf((void *)this, 0, QDMA_GLOBAL_CSR_ARRAY_SZ, - conf->c2h_timer_cnt, QDMA_CSR_TIMER_CNT, QDMA_HW_ACCESS_READ); - if ((ret < 0) && (ret != -QDMA_ERR_HWACC_FEATURE_NOT_SUPPORTED)) { - TraceError(TRACE_QDMA, "%s: Failed to read CSR global timer count, ret : %d", dev_conf.name, ret); - return hw.qdma_get_error_code(ret); - } - - ret = hw.qdma_global_csr_conf((void *)this, 0, QDMA_GLOBAL_CSR_ARRAY_SZ, - conf->c2h_th_cnt, QDMA_CSR_CNT_TH, QDMA_HW_ACCESS_READ); - if ((ret < 0) && (ret != -QDMA_ERR_HWACC_FEATURE_NOT_SUPPORTED)) { - TraceError(TRACE_QDMA, "%s: Failed to read CSR global counter threshold, ret : %d", dev_conf.name, ret); - return hw.qdma_get_error_code(ret); - } - - ret = hw.qdma_global_csr_conf((void *)this, 0, QDMA_GLOBAL_CSR_ARRAY_SZ, - conf->c2h_buff_sz, QDMA_CSR_BUF_SZ, QDMA_HW_ACCESS_READ); - if ((ret < 0) && (ret != -QDMA_ERR_HWACC_FEATURE_NOT_SUPPORTED)) { - TraceError(TRACE_QDMA, "%s: Failed to read CSR global buffer size, ret : %d", dev_conf.name, ret); - return hw.qdma_get_error_code(ret); - } - - ret = hw.qdma_global_writeback_interval_conf((void *)this, - (qdma_wrb_interval *)&conf->wb_interval, QDMA_HW_ACCESS_READ); - if ((ret < 0) && (ret != -QDMA_ERR_HWACC_FEATURE_NOT_SUPPORTED)) { - TraceError(TRACE_QDMA, "%s: Failed to read CSR global write back interval, ret : %d", dev_conf.name, ret); - return hw.qdma_get_error_code(ret); - } - - return STATUS_SUCCESS; -} - -NTSTATUS qdma_device::qdma_get_dev_capabilities_info(qdma_device_attributes_info &dev_attr) -{ - int ret; - struct qdma_dev_attributes dev_info; - - ret = hw.qdma_get_device_attributes((void *)this, &dev_info); - if (ret < 0) { - TraceError(TRACE_QDMA, "%s: qdma_get_device_attributes Failed, ret : %d", dev_conf.name, ret); - return hw.qdma_get_error_code(ret); - } - - dev_attr.num_pfs = dev_info.num_pfs; - dev_attr.num_qs = dev_info.num_qs; - dev_attr.flr_present = dev_info.flr_present; - dev_attr.st_en = dev_info.st_en; - dev_attr.mm_en = dev_info.mm_en; - dev_attr.mm_cmpl_en = dev_info.mm_cmpt_en; - dev_attr.mailbox_en = dev_info.mailbox_en; - dev_attr.num_mm_channels = dev_info.mm_channel_max; - dev_attr.debug_mode = dev_info.debug_mode; - dev_attr.desc_eng_mode = dev_info.desc_eng_mode; - - return STATUS_SUCCESS; -} -void qdma_device::qdma_get_hw_version_info( - qdma_hw_version_info &version_info) -{ - version_info = hw_version_info; -} - -_IRQL_requires_(PASSIVE_LEVEL) -NTSTATUS qdma_device::qdma_device_version_info( - qdma_version_info &version_info) -{ - NTSTATUS status; - struct qdma_hw_version_info info; - - int ret = hw.qdma_get_version((void *)this, QDMA_DEV_PF, &info); - if (ret < 0) { - TraceError(TRACE_QDMA, "%s: qdma_get_version failed!, ret : %d", dev_conf.name, ret); - return hw.qdma_get_error_code(ret); - } - - status = RtlStringCchCopyNA(version_info.qdma_rtl_version_str, - ARRAYSIZE(version_info.qdma_rtl_version_str), - info.qdma_rtl_version_str, - ARRAYSIZE(info.qdma_rtl_version_str)); - if (!NT_SUCCESS(status)) { - return status; - } - - status = RtlStringCchCopyNA(version_info.qdma_vivado_release_id_str, - ARRAYSIZE(version_info.qdma_vivado_release_id_str), - info.qdma_vivado_release_id_str, - ARRAYSIZE(info.qdma_vivado_release_id_str)); - if (!NT_SUCCESS(status)) { - return status; - } - - status = RtlStringCchCopyNA(version_info.qdma_device_type_str, - ARRAYSIZE(version_info.qdma_device_type_str), - info.qdma_device_type_str, - ARRAYSIZE(info.qdma_device_type_str)); - if (!NT_SUCCESS(status)) { - return status; - } - - status = RtlStringCchCopyNA(version_info.qdma_versal_ip_type_str, - ARRAYSIZE(version_info.qdma_versal_ip_type_str), - info.qdma_ip_type_str, - ARRAYSIZE(info.qdma_ip_type_str)); - if (!NT_SUCCESS(status)) { - return status; - } - - status = RtlStringCchPrintfA(version_info.qdma_sw_version_str, - ARRAYSIZE(version_info.qdma_sw_version_str), - "%d.%d.%d", qdma_version.major, - qdma_version.minor, qdma_version.patch); - - return status; -} - -queue_pair *qdma_device::qdma_get_queue_pair_by_hwid(UINT16 qid_abs) -{ - if (qid_abs >= (qbase + drv_conf.qsets_max)) { - TraceError(TRACE_QDMA, "%s: Invalid Qid %d provided", dev_conf.name, qid_abs); - return nullptr; - } - - UINT16 qid_rel = qid_abs - static_cast(qbase); - TraceVerbose(TRACE_QDMA, "%s: Absolute qid : %u Relative qid : %u", dev_conf.name, qid_abs, qid_rel); - return &queue_pairs[qid_rel]; -} \ No newline at end of file diff --git a/QDMA/windows/sys/libqdma/source/qdma.h b/QDMA/windows/sys/libqdma/source/qdma.h deleted file mode 100644 index 4949f6a54..000000000 --- a/QDMA/windows/sys/libqdma/source/qdma.h +++ /dev/null @@ -1,616 +0,0 @@ -/* - * Copyright (C) 2020 Xilinx, Inc - * - * Licensed under the Apache License, Version 2.0 (the "License"). You may - * not use this file except in compliance with the License. You may obtain - * a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - */ - -#pragma once - -/** - * @file - * @brief This file contains the declarations for libqdma interfaces - * - */ - -#include "qdma_platform_env.h" -#include "xversion.hpp" -#include "xpcie.hpp" -#include "qdma_reg_ext.h" -#include "qdma_config.h" -#include "thread.h" -#include "qdma_exports.h" -#include "qdma_access_common.h" -#include "qdma_resource_mgmt.h" -#include "interrupts.hpp" -#include "qdma_platform.h" - -/* Xilinx namespace */ -namespace xlnx { - -#pragma pack(1) -struct version { - UINT8 patch; - UINT8 minor; - UINT16 major; - - constexpr version(const UINT16 major_, const UINT8 minor_, const UINT8 patch_) - : patch(patch_), minor(minor_), major(major_) {} - - constexpr UINT32 hash() const { - return UINT32((major << 16) + (minor << 8) + patch); - } - - constexpr bool operator==(const version& other) const { - return hash() == other.hash(); - } - - constexpr bool operator!=(const version& other) const { - return !(*this == other); - } -}; -#pragma pack() - -/* ensure that version is evaluated at compile time */ -static_assert(version(65535, 0, 0).major == 65535 && - version(0, 255, 0).minor == 255 && - version(0, 0, 255).patch == 255, "incorrect bits in version"); -static_assert(sizeof(version) == sizeof(UINT32), "size of version struct is not 32bits"); - -static_assert(version(0x1234, 0x56, 0x78).hash() == 0x12345678, "error in version hash function"); - -static_assert(version(1, 2, 3) == version(1, 2, 3), "error in version equality comparison"); -static_assert(version(1, 2, 3) != version(1, 2, 0), "error in version equality comparison"); -static_assert(version(1, 2, 3) != version(1, 0, 3), "error in version equality comparison"); -static_assert(version(1, 2, 3) != version(0, 2, 3), "error in version equality comparison"); - - - -/** libqdma version number */ -static constexpr version qdma_version = version(VER_PRODUCTMAJORVERSION, VER_PRODUCTMINORVERSION, VER_PRODUCTREVISION); - -static constexpr size_t sg_frag_len = 61440; /** 15 * 4K Fragment size */ -static constexpr size_t st_max_desc_data_len = 65535; -static constexpr size_t mm_max_desc_data_len = 65535; - -static constexpr unsigned int mm_h2c_completion_weight = 2048; -static constexpr unsigned int mm_c2h_completion_weight = 2048; -static constexpr unsigned int st_h2c_completion_weight = 2048; -static constexpr unsigned int st_c2h_completion_weight = 2048; - -static constexpr unsigned int max_req_service_cnt = 10; - -/** - * Structure to hold the driver name and mode - */ -struct drv_mode_name { - /** Mode of the function */ - queue_op_mode mode; - /** Driver Name */ - char name[20]; -}; - -class qdma_device; -struct queue_pair; - -#define IS_LIST_EMPTY(list_head) \ - IsListEmpty(list_head) - -#define INIT_LIST_HEAD(list_head) \ - InitializeListHead(list_head) - -#define LIST_ADD_HEAD(list_head, entry) \ - InsertHeadList(list_head, entry) - -#define LIST_ADD_TAIL(list_head, entry) \ - InsertTailList(list_head, entry) - -#define LIST_DEL_NODE(entry) \ - RemoveEntryList(entry) - -#define LIST_FOR_EACH_ENTRY(list_head, entry) \ - for ((entry)= (list_head)->Flink; (entry) != (list_head); (entry) = (entry)->Flink) - -#define LIST_FOR_EACH_ENTRY_SAFE(list_head, n, entry) \ - for ((entry) = (list_head)->Flink, (n) = (entry)->Flink; (entry) != (list_head); (entry) = (n), (n) = (entry)->Flink) - -#define LIST_GET_ENTRY(entry, type, member) \ - CONTAINING_RECORD(entry, type, member) - -/** queue_type - QDMA queue type */ -enum class queue_type { - /** Memory mapped queue type */ - MEMORY_MAPPED, - /** Streaming queue type */ - STREAMING, - /** Invalid queue type */ - NONE -}; - -/** device_state - State of the QDMA device */ -enum device_state { - /** Device is in Init State */ - DEVICE_INIT, - /** Device is offline */ - DEVICE_OFFLINE, - /** Device is online */ - DEVICE_ONLINE, -}; - -/** - * Maxinum length of the QDMA device name - */ -#define QDMA_DEV_NAME_MAXLEN 32 - - /** - * QDMA_QUEUE_NAME_MAXLEN - Maximum queue name length - */ -#define QDMA_QUEUE_NAME_MAXLEN 32 - - /** - * qdma_dev_conf - defines the per-device qdma property. - */ -struct qdma_dev_conf { - /** PCIe Segment-Bus-Device-Function of QDMA device */ - union pci_sbdf dev_sbdf; - /** Indicates whether this QDMA device is master */ - UINT32 is_master_pf : 1; - /** Reserved Field, not being used */ - UINT32 reserved02 : 31; - /** The name of the QDMA device, in 'qdma' format */ - char name[QDMA_DEV_NAME_MAXLEN]; - /** Attributes of the QDMA device specifies the supported features */ - struct qdma_dev_attributes dev_info; -}; - -/** - * st_c2h_pkt_frag_queue - Structure to manage streamed - * c2h packet fragments. - */ -struct st_c2h_pkt_frag_queue { - st_c2h_pkt_fragment *frags = nullptr; - UINT32 avail_frag_cnt = 0; - size_t avail_byte_cnt = 0; - /** Maximum size of the queue, - * (max_q_size - 1) packets will fit in this queue - */ - UINT32 max_q_size; - UINT32 pidx; - UINT32 cidx; - - NTSTATUS create(UINT32 entries); - void destroy(void); - NTSTATUS add(st_c2h_pkt_fragment &elem); - NTSTATUS consume(st_c2h_pkt_fragment &elem); - PFORCEINLINE bool is_queue_full(void); - PFORCEINLINE bool is_queue_empty(void); - inline LONG get_avail_frag_cnt(void); - inline size_t get_avail_byte_cnt(void); -}; - -struct ring_buffer { - UINT32 capacity; /* NOT including status write-back */ - - WDFCOMMONBUFFER buffer = nullptr; - void *buffer_va = nullptr; - volatile wb_status_base* wb_status = nullptr; - - volatile UINT32 sw_index = 0; /* usage: e.g. [1] pidx for MM C2H, MM H2C, ST H2C. [2] cidx for ST WB */ - volatile UINT32 hw_index = 0; /* usage: e.g. [1] cidx for MM C2H, MM H2C, ST H2C. [2] pidx for ST WB */ - - struct { - UINT32 tot_desc_accepted; - UINT32 tot_desc_processed; - }stats; - - PFORCEINLINE void advance_idx(volatile UINT32& idx); - PFORCEINLINE void advance_idx(volatile UINT32& idx, UINT32 num); - PFORCEINLINE UINT32 idx_delta(UINT32 start_idx, UINT32 end_idx); - - NTSTATUS create(WDFDMAENABLER& dma_enabler, UINT32 num_entries, size_t desc_sz_in_bytes); - void destroy(void); - UINT32 get_num_free_entries(void); - void *get_va(void); - UINT32 get_capacity(void); -}; - -/** libqdma_queue_config -- This structure holds - * the QDMA configuration parameters which are - * deduced from the user requested while adding the queue - */ -struct libqdma_queue_config { - /** Flag indicates the interrupt enabled or not */ - bool irq_en; - /** Holds the vector id (MSIX/Legacy) assigned for the queue */ - UINT32 vector_id; - /** Holds the descriptor size of the ring */ - qdma_desc_sz desc_sz; - /** Holds the size of the descriptor ring (i.e., no of entries) */ - UINT32 ring_sz; - /** Holds the size of the completion ring (i.e., no of entries) */ - UINT32 cmpt_ring_sz; - /** Holds the index of the completion ring (one of the Global CSR register index) */ - UINT32 cmpt_ring_id; - /** Holds the size of the single data buffer (Valid for ST C2H only) */ - UINT32 data_buf_size; -}; - -/** req_ctx -- Stores the request completion parameters */ -struct req_ctx { - /** User supplied private data */ - void *priv; - /** Completion callback routine */ - dma_completion_cb compl_cb; -}; - -/** dma_req_tracker -- This is a shadow ring tracker for - * MM and ST H2C transfers. This structure holds the data - * required for making request completions - * - * This shadow ring tracker is used to avoid the - * use of synchronization primitives for the performance - * cost - */ -struct dma_req_tracker { - /** Holds the completion parameters for user requests */ - req_ctx *requests = nullptr; - - /** Allocates and initializes the request tracker */ - NTSTATUS create(UINT32 entries); - /** Frees the memory allocated for request tracker */ - void destroy(); -}; - -/** st_c2h_req -- Stores the ST C2H request completion parameters */ -struct st_c2h_req { - /** Length of the packet requested */ - size_t len; - /** User supplied private data */ - void *priv; - /** Completion callback routine */ - st_rx_completion_cb st_compl_cb; -}; - -/** st_c2h_dma_req_tracker -- This structure holds the user requests - * for ST C2H direction. This tracker has the same size as descriptor - * ring (i.e., no of entries) - */ -struct st_c2h_dma_req_tracker { - st_c2h_req *requests = nullptr; - - /* This lock is to ensure enqueueing/adding - ST C2H requests properly to request tracker and - dequeueing/popping the requests during completions - */ - WDFSPINLOCK lock = nullptr; - - /** The size of this request tracker (no of entries) - * This tracker is a bounded queue with max capacity specified - * during initialization by the caller. - */ - UINT32 capacity; - UINT32 pidx; - UINT32 cidx; - - NTSTATUS create(UINT32 entries); - void destroy(void); - - NTSTATUS st_push_dma_req(st_c2h_req& req); - NTSTATUS st_peek_dma_req(st_c2h_req& req); - NTSTATUS st_pop_dma_req(void); -}; - -struct st_c2h_pkt_buffer { - WDFCOMMONBUFFER rx_buff_common; - PVOID rx_buff_va; - PHYSICAL_ADDRESS rx_buff_dma; - - NTSTATUS create(WDFDMAENABLER dma_enabler, size_t size); - void destroy(void); - void fill_rx_buff(PVOID buff_va, PHYSICAL_ADDRESS buff_dma); - PHYSICAL_ADDRESS get_dma_addr(void); - PVOID get_va(void); -}; - -struct dma_request { - /** Linked list entry to form request queue */ - LIST_ENTRY list_entry; - /** DMA Mode (ST/MM) */ - bool is_st; - /** Direction of DMA */ - WDF_DMA_DIRECTION direction; - /** SG list of request */ - PSCATTER_GATHER_LIST sg_list; - /** Completion callback handler */ - dma_completion_cb compl_cb; - /** Private data to pass during completion callback */ - VOID *priv; - /** The device address to/from DMA - * (Only Valid for MM transfers) */ - LONGLONG device_offset; - /** Holds the next index to resume - * request transfer for split request */ - UINT32 sg_index; - /** Holds the next device offset to resume - * request transfer for split request - * (Only valid for MM transfers ) */ - LONGLONG offset_idx; -}; - -struct h2c_queue { - queue_config user_conf; - libqdma_queue_config lib_config; - - ring_buffer desc_ring; - dma_req_tracker req_tracker; - - /** This forms a chain of h2c requests */ - LIST_ENTRY req_list_head; - - /* This lock is to ensure enqueueing/adding - the requests to the descriptor ring properly - - During completions this lock is not needed and - request tracker design will make sure proper execution - */ - WDFSPINLOCK lock = nullptr; - poll_operation_entry *req_proc_entry; - poll_operation_entry *poll_entry; - qdma_q_pidx_reg_info csr_pidx_info; - - NTSTATUS create(qdma_device *qdma, queue_config& conf); - void destroy(void); - void init_csr_h2c_pidx_info(void); -}; - -struct c2h_queue { - queue_config user_conf; - libqdma_queue_config lib_config; - - ring_buffer desc_ring; - dma_req_tracker req_tracker; - - /** This forms a chain of c2h requests */ - LIST_ENTRY req_list_head; - - /* This lock is to ensure MM enqueueing/adding - the requests to the descriptor ring properly - - For completions of MM requests: lock is not needed - request tracker design takes care - */ - WDFSPINLOCK lock = nullptr; - poll_operation_entry *req_proc_entry; - poll_operation_entry *poll_entry; - qdma_q_pidx_reg_info csr_pidx_info; - qdma_q_cmpt_cidx_reg_info csr_cmpt_cidx_info; - bool is_cmpt_valid = false; - UINT32 cmpt_offset = 0; - ring_buffer cmpt_ring; - - /* Only for streaming */ - st_c2h_dma_req_tracker st_c2h_req_tracker; - UINT32 no_allocated_rx_common_buffs = 0; - st_c2h_pkt_buffer *pkt_buffer = nullptr; - st_c2h_pkt_fragment *pkt_frag_list = nullptr; - st_c2h_pkt_frag_queue pkt_frag_queue; - - NTSTATUS create(qdma_device *qdma, queue_config& conf); - void destroy(void); - INT32 get_cmpt_ring_index(UINT32* csr_ring_sz_table, UINT32 desc_ring_index); - void init_csr_c2h_pidx_info(void); - void init_csr_cmpt_cidx_info(void); -}; - -enum class service_status { - SERVICE_CONTINUE, - SERVICE_FINISHED, - SERVICE_ERROR, -}; - -struct queue_pair { - LIST_ENTRY list_entry; - qdma_device *qdma = nullptr; - - queue_type type; - char name[QDMA_QUEUE_NAME_MAXLEN]; - volatile LONG state; - - UINT16 idx = 0; /* queue index - relative to this PF */ - UINT16 idx_abs = 0; /* queue index - absolute across all PF */ - - h2c_queue h2c_q; - c2h_queue c2h_q; - - /** Initialization and De-Initialization functions */ - NTSTATUS create(queue_config& conf); - void destroy(void); - void init_csr(void); - - /** CSR update functions */ - PFORCEINLINE void update_sw_index_with_csr_wb(UINT32 new_cidx); - PFORCEINLINE void update_sw_index_with_csr_h2c_pidx(UINT32 new_pidx); - PFORCEINLINE void update_sw_index_with_csr_c2h_pidx(UINT32 new_pidx); - - /** Transfer initiate functions */ - NTSTATUS enqueue_dma_request(dma_request *request); - NTSTATUS enqueue_dma_request(size_t length, st_rx_completion_cb compl_cb, void *priv); - - /** Transfer processing functions */ - service_status process_mm_request(dma_request* request, size_t* xfer_len); - service_status process_st_h2c_request(dma_request* request, size_t* xfer_len); - NTSTATUS process_st_c2h_data_pkt(void* udd_ptr, const UINT32 length); - - /** Transfer completion functions */ - service_status service_mm_st_h2c_completions(ring_buffer *desc_ring, dma_req_tracker *tracker, UINT32 budget, UINT32& proc_desc_cnt); - service_status st_service_c2h_queue(UINT32 budget); - - PFORCEINLINE void update_c2h_pidx_in_batch(UINT32 processed_desc_cnt); - NTSTATUS check_cmpt_error(c2h_wb_header_8B *cmpt_data); - - /** User-Defined Data(Side band data) funtions */ - NTSTATUS read_st_udd_data(void *addr, UINT8 *buf, UINT32 *len); - void * get_last_udd_addr(void); - - /** Reads MM Completion ring (UDD) data, - * This is independent ring and not related to data packets */ - NTSTATUS read_mm_cmpt_data(qdma_cmpt_info *cmpt_info); - - /** Cleanup related functions */ - void flush_queue(void); - void cancel_mm_st_h2c_pending_requests(ring_buffer* desc_ring, dma_req_tracker* tracker, WDFSPINLOCK lock); - - /** Debug Functions */ - NTSTATUS desc_dump(qdma_desc_info *desc_info); -}; - -/** - * qdma_device - Master class for QDMA device - * - * This class defines the interface structures/unions/classes - * and interface functions that can be used while using - * the libqdma library - */ -class qdma_device : public qdma_interface { -public: - /** Spinlock to serialize all the HW registers */ - WDFSPINLOCK register_access_lock = nullptr; - /** Structure that provides set of call back functions to access hardware */ - qdma_hw_access hw; - /** Structure that provides QDMA device properties */ - qdma_dev_conf dev_conf; - /** Structure that contains QDMA global CSR registers information */ - qdma_glbl_csr_conf csr_conf; - /** Structure that contains QDMA driver configuration */ - qdma_drv_config drv_conf; - - /** DMA Initialization/Teardown APIs */ - NTSTATUS init(qdma_drv_config conf); - NTSTATUS open(WDFDEVICE device, WDFCMRESLIST resources, WDFCMRESLIST resources_translated); - void close(void); - bool qdma_is_device_online(void); - - /** PCIe BAR Read and Write APIs */ - NTSTATUS read_bar(qdma_bar_type bar_type, size_t offset, void* data, size_t size); - NTSTATUS write_bar(qdma_bar_type bar_type, size_t offset, void* data, size_t size); - ULONG qdma_conf_reg_read(size_t offset); - void qdma_conf_reg_write(size_t offset, ULONG data); - NTSTATUS get_bar_info(qdma_bar_type bar_type, PVOID &bar_base, size_t &bar_length); - - /** Queue Configuration APIs (Add, Start Stop, Delete, state) */ - NTSTATUS qdma_add_queue(UINT16 qid, queue_config& conf); - NTSTATUS qdma_start_queue(UINT16 qid); - NTSTATUS qdma_stop_queue(UINT16 qid); - NTSTATUS qdma_remove_queue(UINT16 qid); - NTSTATUS qdma_is_queue_in_range(UINT16 qid); - NTSTATUS qdma_get_queues_state(UINT16 qid, enum queue_state *qstate, CHAR *str, size_t str_maxlen); - NTSTATUS qdma_set_qmax(UINT32 queue_max); - - /** DMA transfer APIs (From Device and To Device) */ - NTSTATUS qdma_enqueue_mm_request(UINT16 qid, WDF_DMA_DIRECTION direction, PSCATTER_GATHER_LIST sg_list, LONGLONG device_offset, dma_completion_cb compl_cb, VOID *priv); - NTSTATUS qdma_enqueue_st_tx_request(UINT16 qid, PSCATTER_GATHER_LIST sg_list, dma_completion_cb compl_cb, VOID *priv); - NTSTATUS qdma_enqueue_st_rx_request(UINT16 qid, size_t length, st_rx_completion_cb compl_cb, VOID *priv); - - /** DMA Completion ring APIs */ - NTSTATUS qdma_retrieve_st_udd_data(UINT16 qid, void *addr, UINT8 *buf, UINT32 *len); - NTSTATUS qdma_retrieve_last_st_udd_data(UINT16 qid, UINT8 *buf, UINT32 *len); - NTSTATUS qdma_read_mm_cmpt_data(qdma_cmpt_info *cmpt_info); - - /** DMA Configuration Read APIs */ - NTSTATUS qdma_read_csr_conf(qdma_glbl_csr_conf *conf); - NTSTATUS qdma_get_dev_capabilities_info(qdma_device_attributes_info &dev_attr); - NTSTATUS qdma_queue_context_read(UINT16 qid, enum qdma_dev_q_type ctx_type, struct qdma_descq_context *ctxt); - - /** DMA Configuration dump APIs */ - NTSTATUS qdma_queue_desc_dump(qdma_desc_info *desc_info); - NTSTATUS qdma_queue_dump_context(qdma_ctx_info *ctx_info); - NTSTATUS qdma_intring_dump(qdma_intr_ring_info *intring_info); - NTSTATUS qdma_regdump(qdma_reg_dump_info *regdump_info); - NTSTATUS qdma_get_qstats_info(qdma_qstat_info &qstats); - NTSTATUS qdma_get_reg_info(qdma_reg_info *reg_info); - - /** DMA Versioning APIs */ - NTSTATUS qdma_device_version_info(qdma_version_info &version_info); - void qdma_get_hw_version_info(qdma_hw_version_info &version_info); - - /** Misc APIs */ - queue_pair *qdma_get_queue_pair_by_hwid(UINT16 qid_abs); -private: - LIST_ENTRY list_entry; - /** Identifier returned by resource manager */ - UINT32 dma_dev_index = 0; - /** Start/base queue number for this device */ - INT32 qbase = -1; - /** Device state */ - volatile LONG qdma_device_state; - - xpcie_device pcie; - WDFDEVICE wdf_dev = nullptr; - qdma_hw_version_info hw_version_info; - queue_pair *queue_pairs = nullptr; - interrupt_manager irq_mgr; - thread_manager th_mgr; - - NTSTATUS validate_qconfig(queue_config& conf); - - /* QDMA Device(s) list helper functions */ - NTSTATUS list_add_qdma_device_and_set_gbl_csr(void); - bool is_first_qdma_pf_device(void); - void list_remove_qdma_device(void); - - /* Context programming */ - NTSTATUS clear_queue_contexts(bool is_c2h, UINT16 qid, qdma_hw_access_type context_op) const; - NTSTATUS clear_cmpt_contexts(UINT16 qid, qdma_hw_access_type context_op) const; - NTSTATUS clear_pfetch_contexts(UINT16 qid, qdma_hw_access_type context_op) const; - NTSTATUS clear_contexts(queue_pair& q, bool invalidate = false) const; - NTSTATUS queue_program(queue_pair& q); - NTSTATUS set_h2c_ctx(queue_pair& q); - NTSTATUS set_c2h_ctx(queue_pair& q); - - NTSTATUS init_qdma_global(); - NTSTATUS init_func(); - NTSTATUS assign_bar_types(); - NTSTATUS init_dma_queues(); - NTSTATUS init_interrupt_queues(); - NTSTATUS init_os_resources(WDFCMRESLIST resources, const WDFCMRESLIST resources_translated); - NTSTATUS init_resource_manager(); - void inc_queue_pair_count(bool is_cmpt_valid); - void dec_queue_pair_count(bool is_cmpt_valid); - - void destroy_dma_queues(void); - void destroy_os_resources(void); - void destroy_func(void); - void destroy_resource_manager(void); - - NTSTATUS configure_irq(PQDMA_IRQ_CONTEXT irq_context, ULONG vec); - NTSTATUS intr_setup(WDFCMRESLIST resources, const WDFCMRESLIST resources_translated); - void intr_teardown(void); - NTSTATUS setup_legacy_interrupt(WDFCMRESLIST resources, const WDFCMRESLIST resources_translated); - int setup_legacy_vector(queue_pair& q); - void clear_legacy_vector(queue_pair& q, UINT32 vector); - NTSTATUS arrange_msix_vector_types(void); - NTSTATUS setup_msix_interrupt(WDFCMRESLIST resources, const WDFCMRESLIST resources_translated); - UINT32 alloc_msix_vector_position(queue_pair& q); - int assign_interrupt_vector(queue_pair& q); - void free_interrupt_vector(queue_pair& q, UINT32 vec_id); - void free_msix_vector_position(queue_pair& q, UINT32 vector); - void mask_msi_entry(UINT32 vector); - void unmask_msi_entry(UINT32 vector); - NTSTATUS qdma_intr_context_read(UINT8 ring_idx_abs, struct qdma_indirect_intr_ctxt *ctxt); -}; - -typedef struct devices_list { - qdma_device *qdma_dev; - devices_list *next; -}devices_list, *pdevices_list; - -} /* namespace xlnx */ diff --git a/QDMA/windows/sys/libqdma/source/qdma_access/eqdma_soft_access/eqdma_soft_access.c b/QDMA/windows/sys/libqdma/source/qdma_access/eqdma_soft_access/eqdma_soft_access.c deleted file mode 100644 index 90c6bba90..000000000 --- a/QDMA/windows/sys/libqdma/source/qdma_access/eqdma_soft_access/eqdma_soft_access.c +++ /dev/null @@ -1,5868 +0,0 @@ -/* - * Copyright (C) 2020 Xilinx, Inc - * - * Licensed under the Apache License, Version 2.0 (the "License"). You may - * not use this file except in compliance with the License. You may obtain - * a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - */ - -#include "eqdma_soft_access.h" -#include "eqdma_soft_reg.h" -#include "qdma_reg_dump.h" - -#ifdef ENABLE_WPP_TRACING -#include "eqdma_soft_access.tmh" -#endif - -/** EQDMA Context array size */ -#define EQDMA_SW_CONTEXT_NUM_WORDS 8 -#define EQDMA_HW_CONTEXT_NUM_WORDS 2 -#define EQDMA_PFETCH_CONTEXT_NUM_WORDS 2 -#define EQDMA_CR_CONTEXT_NUM_WORDS 1 -#define EQDMA_CMPT_CONTEXT_NUM_WORDS 6 -#define EQDMA_IND_INTR_CONTEXT_NUM_WORDS 4 - -#define EQDMA_VF_USER_BAR_ID 2 - -#define EQDMA_REG_GROUP_1_START_ADDR 0x000 -#define EQDMA_REG_GROUP_2_START_ADDR 0x804 -#define EQDMA_REG_GROUP_3_START_ADDR 0xB00 -#define EQDMA_REG_GROUP_4_START_ADDR 0x5014 - -#define EQDMA_TOTAL_LEAF_ERROR_AGGREGATORS 9 -#define EQDMA_GLBL_TRQ_ERR_ALL_MASK 0XB3 -#define EQDMA_GLBL_DSC_ERR_ALL_MASK 0X1F9037E -#define EQDMA_C2H_ERR_ALL_MASK 0X3F6DF -#define EQDMA_C2H_FATAL_ERR_ALL_MASK 0X1FDF1B -#define EQDMA_H2C_ERR_ALL_MASK 0X3F -#define EQDMA_SBE_ERR_ALL_MASK 0XFFFFFFFF -#define EQDMA_DBE_ERR_ALL_MASK 0XFFFFFFFF - -/* H2C Throttle settings */ -#define EQDMA_H2C_THROT_DATA_THRESH 0x5000 -#define EQDMA_THROT_EN_DATA 1 -#define EQDMA_THROT_EN_REQ 0 -#define EQDMA_H2C_THROT_REQ_THRESH 0xC0 - - -/** Auxillary Bitmasks for fields spanning multiple words */ -#define EQDMA_SW_CTXT_PASID_GET_H_MASK GENMASK(21, 12) -#define EQDMA_SW_CTXT_PASID_GET_L_MASK GENMASK(11, 0) -#define EQDMA_SW_CTXT_VIRTIO_DSC_BASE_GET_H_MASK GENMASK_ULL(63, 53) -#define EQDMA_SW_CTXT_VIRTIO_DSC_BASE_GET_M_MASK GENMASK_ULL(52, 21) -#define EQDMA_SW_CTXT_VIRTIO_DSC_BASE_GET_L_MASK GENMASK_ULL(20, 0) -#define EQDMA_CMPL_CTXT_PASID_GET_H_MASK GENMASK(21, 9) -#define EQDMA_CMPL_CTXT_PASID_GET_L_MASK GENMASK(8, 0) -#define EQDMA_INTR_CTXT_PASID_GET_H_MASK GENMASK(21, 9) -#define EQDMA_INTR_CTXT_PASID_GET_L_MASK GENMASK(8, 0) - - -#define EQDMA_OFFSET_GLBL2_PF_BARLITE_EXT 0x10C - -#define QDMA_OFFSET_GLBL2_PF_BARLITE_INT 0x104 -#define QDMA_GLBL2_PF3_BAR_MAP_MASK GENMASK(23, 18) -#define QDMA_GLBL2_PF2_BAR_MAP_MASK GENMASK(17, 12) -#define QDMA_GLBL2_PF1_BAR_MAP_MASK GENMASK(11, 6) -#define QDMA_GLBL2_PF0_BAR_MAP_MASK GENMASK(5, 0) - -#define EQDMA_GLBL2_DBG_MODE_EN_MASK BIT(4) -#define EQDMA_GLBL2_DESC_ENG_MODE_MASK GENMASK(3, 2) -#define EQDMA_GLBL2_FLR_PRESENT_MASK BIT(1) -#define EQDMA_GLBL2_MAILBOX_EN_MASK BIT(0) - -static void eqdma_hw_st_h2c_err_process(void *dev_hndl); -static void eqdma_hw_st_c2h_err_process(void *dev_hndl); -static void eqdma_hw_desc_err_process(void *dev_hndl); -static void eqdma_hw_trq_err_process(void *dev_hndl); -static void eqdma_hw_ram_sbe_err_process(void *dev_hndl); -static void eqdma_hw_ram_dbe_err_process(void *dev_hndl); - -static struct eqdma_hw_err_info eqdma_err_info[EQDMA_ERRS_ALL] = { - /* Descriptor errors */ - { - EQDMA_DSC_ERR_POISON, - "Poison error", - EQDMA_GLBL_DSC_ERR_MSK_ADDR, - EQDMA_GLBL_DSC_ERR_STS_ADDR, - GLBL_DSC_ERR_STS_POISON_MASK, - GLBL_ERR_STAT_ERR_DSC_MASK, - &eqdma_hw_desc_err_process - }, - { - EQDMA_DSC_ERR_UR_CA, - "Unsupported request or completer aborted error", - EQDMA_GLBL_DSC_ERR_MSK_ADDR, - EQDMA_GLBL_DSC_ERR_STS_ADDR, - GLBL_DSC_ERR_STS_UR_CA_MASK, - GLBL_ERR_STAT_ERR_DSC_MASK, - &eqdma_hw_desc_err_process - }, - { - EQDMA_DSC_ERR_BCNT, - "Unexpected Byte count in completion error", - EQDMA_GLBL_DSC_ERR_MSK_ADDR, - EQDMA_GLBL_DSC_ERR_STS_ADDR, - GLBL_DSC_ERR_STS_BCNT_MASK, - GLBL_ERR_STAT_ERR_DSC_MASK, - &eqdma_hw_desc_err_process - }, - { - EQDMA_DSC_ERR_PARAM, - "Parameter mismatch error", - EQDMA_GLBL_DSC_ERR_MSK_ADDR, - EQDMA_GLBL_DSC_ERR_STS_ADDR, - GLBL_DSC_ERR_STS_PARAM_MASK, - GLBL_ERR_STAT_ERR_DSC_MASK, - &eqdma_hw_desc_err_process - }, - { - EQDMA_DSC_ERR_ADDR, - "Address mismatch error", - EQDMA_GLBL_DSC_ERR_MSK_ADDR, - EQDMA_GLBL_DSC_ERR_STS_ADDR, - GLBL_DSC_ERR_STS_ADDR_MASK, - GLBL_ERR_STAT_ERR_DSC_MASK, - &eqdma_hw_desc_err_process - }, - { - EQDMA_DSC_ERR_TAG, - "Unexpected tag error", - EQDMA_GLBL_DSC_ERR_MSK_ADDR, - EQDMA_GLBL_DSC_ERR_STS_ADDR, - GLBL_DSC_ERR_STS_TAG_MASK, - GLBL_ERR_STAT_ERR_DSC_MASK, - &eqdma_hw_desc_err_process - }, - { - EQDMA_DSC_ERR_FLR, - "FLR error", - EQDMA_GLBL_DSC_ERR_MSK_ADDR, - EQDMA_GLBL_DSC_ERR_STS_ADDR, - GLBL_DSC_ERR_STS_FLR_MASK, - GLBL_ERR_STAT_ERR_DSC_MASK, - &eqdma_hw_desc_err_process - }, - { - EQDMA_DSC_ERR_TIMEOUT, - "Timed out error", - EQDMA_GLBL_DSC_ERR_MSK_ADDR, - EQDMA_GLBL_DSC_ERR_STS_ADDR, - GLBL_DSC_ERR_STS_TIMEOUT_MASK, - GLBL_ERR_STAT_ERR_DSC_MASK, - &eqdma_hw_desc_err_process - }, - { - EQDMA_DSC_ERR_DAT_POISON, - "Poison data error", - EQDMA_GLBL_DSC_ERR_MSK_ADDR, - EQDMA_GLBL_DSC_ERR_STS_ADDR, - GLBL_DSC_ERR_STS_DAT_POISON_MASK, - GLBL_ERR_STAT_ERR_DSC_MASK, - &eqdma_hw_desc_err_process - }, - { - EQDMA_DSC_ERR_FLR_CANCEL, - "Descriptor fetch cancelled due to FLR error", - EQDMA_GLBL_DSC_ERR_MSK_ADDR, - EQDMA_GLBL_DSC_ERR_STS_ADDR, - GLBL_DSC_ERR_STS_FLR_CANCEL_MASK, - GLBL_ERR_STAT_ERR_DSC_MASK, - &eqdma_hw_desc_err_process - }, - { - EQDMA_DSC_ERR_DMA, - "DMA engine error", - EQDMA_GLBL_DSC_ERR_MSK_ADDR, - EQDMA_GLBL_DSC_ERR_STS_ADDR, - GLBL_DSC_ERR_STS_DMA_MASK, - GLBL_ERR_STAT_ERR_DSC_MASK, - &eqdma_hw_desc_err_process - }, - { - EQDMA_DSC_ERR_DSC, - "Invalid PIDX update error", - EQDMA_GLBL_DSC_ERR_MSK_ADDR, - EQDMA_GLBL_DSC_ERR_STS_ADDR, - GLBL_DSC_ERR_STS_DSC_MASK, - GLBL_ERR_STAT_ERR_DSC_MASK, - &eqdma_hw_desc_err_process - }, - { - EQDMA_DSC_ERR_RQ_CANCEL, - "Descriptor fetch cancelled due to disable register status error", - EQDMA_GLBL_DSC_ERR_MSK_ADDR, - EQDMA_GLBL_DSC_ERR_STS_ADDR, - GLBL_DSC_ERR_STS_RQ_CANCEL_MASK, - GLBL_ERR_STAT_ERR_DSC_MASK, - &eqdma_hw_desc_err_process - }, - { - EQDMA_DSC_ERR_DBE, - "UNC_ERR_RAM_DBE error", - EQDMA_GLBL_DSC_ERR_MSK_ADDR, - EQDMA_GLBL_DSC_ERR_STS_ADDR, - GLBL_DSC_ERR_STS_DBE_MASK, - GLBL_ERR_STAT_ERR_DSC_MASK, - &eqdma_hw_desc_err_process - }, - { - EQDMA_DSC_ERR_SBE, - "UNC_ERR_RAM_SBE error", - EQDMA_GLBL_DSC_ERR_MSK_ADDR, - EQDMA_GLBL_DSC_ERR_STS_ADDR, - GLBL_DSC_ERR_STS_SBE_MASK, - GLBL_ERR_STAT_ERR_DSC_MASK, - &eqdma_hw_desc_err_process - }, - { - EQDMA_DSC_ERR_ALL, - "All Descriptor errors", - EQDMA_GLBL_DSC_ERR_MSK_ADDR, - EQDMA_GLBL_DSC_ERR_STS_ADDR, - EQDMA_GLBL_DSC_ERR_ALL_MASK, - GLBL_ERR_STAT_ERR_DSC_MASK, - &eqdma_hw_desc_err_process - }, - - /* TRQ errors */ - { - EQDMA_TRQ_ERR_CSR_UNMAPPED, - "Access targeted unmapped register space via CSR pathway error", - EQDMA_GLBL_TRQ_ERR_MSK_ADDR, - EQDMA_GLBL_TRQ_ERR_STS_ADDR, - GLBL_TRQ_ERR_STS_CSR_UNMAPPED_MASK, - GLBL_ERR_STAT_ERR_TRQ_MASK, - &eqdma_hw_trq_err_process - }, - { - EQDMA_TRQ_ERR_VF_ACCESS, - "VF attempted to access Global register space or Function map", - EQDMA_GLBL_TRQ_ERR_MSK_ADDR, - EQDMA_GLBL_TRQ_ERR_STS_ADDR, - GLBL_TRQ_ERR_STS_VF_ACCESS_ERR_MASK, - GLBL_ERR_STAT_ERR_TRQ_MASK, - &eqdma_hw_trq_err_process - }, - { - EQDMA_TRQ_ERR_TCP_CSR_TIMEOUT, - "Timeout on request to dma internal csr register", - EQDMA_GLBL_TRQ_ERR_MSK_ADDR, - EQDMA_GLBL_TRQ_ERR_STS_ADDR, - GLBL_TRQ_ERR_STS_TCP_CSR_TIMEOUT_MASK, - GLBL_ERR_STAT_ERR_TRQ_MASK, - &eqdma_hw_trq_err_process - }, - { - EQDMA_TRQ_ERR_QSPC_UNMAPPED, - "Access targeted unmapped register via queue space pathway", - EQDMA_GLBL_TRQ_ERR_MSK_ADDR, - EQDMA_GLBL_TRQ_ERR_STS_ADDR, - GLBL_TRQ_ERR_STS_QSPC_UNMAPPED_MASK, - GLBL_ERR_STAT_ERR_TRQ_MASK, - &eqdma_hw_trq_err_process - }, - { - EQDMA_TRQ_ERR_QID_RANGE, - "Qid range error", - EQDMA_GLBL_TRQ_ERR_MSK_ADDR, - EQDMA_GLBL_TRQ_ERR_STS_ADDR, - GLBL_TRQ_ERR_STS_QID_RANGE_MASK, - GLBL_ERR_STAT_ERR_TRQ_MASK, - &eqdma_hw_trq_err_process - }, - { - EQDMA_TRQ_ERR_TCP_QSPC_TIMEOUT, - "Timeout on request to dma internal queue space register", - EQDMA_GLBL_TRQ_ERR_MSK_ADDR, - EQDMA_GLBL_TRQ_ERR_STS_ADDR, - GLBL_TRQ_ERR_STS_TCP_QSPC_TIMEOUT_MASK, - GLBL_ERR_STAT_ERR_TRQ_MASK, - &eqdma_hw_trq_err_process - }, - { - EQDMA_TRQ_ERR_ALL, - "All TRQ errors", - EQDMA_GLBL_TRQ_ERR_MSK_ADDR, - EQDMA_GLBL_TRQ_ERR_STS_ADDR, - EQDMA_GLBL_TRQ_ERR_ALL_MASK, - GLBL_ERR_STAT_ERR_TRQ_MASK, - &eqdma_hw_trq_err_process - }, - - /* C2H Errors*/ - { - EQDMA_ST_C2H_ERR_MTY_MISMATCH, - "MTY mismatch error", - EQDMA_C2H_ERR_MASK_ADDR, - EQDMA_C2H_ERR_STAT_ADDR, - C2H_ERR_STAT_MTY_MISMATCH_MASK, - GLBL_ERR_STAT_ERR_C2H_ST_MASK, - &eqdma_hw_st_c2h_err_process - }, - { - EQDMA_ST_C2H_ERR_LEN_MISMATCH, - "Packet length mismatch error", - EQDMA_C2H_ERR_MASK_ADDR, - EQDMA_C2H_ERR_STAT_ADDR, - C2H_ERR_STAT_LEN_MISMATCH_MASK, - GLBL_ERR_STAT_ERR_C2H_ST_MASK, - &eqdma_hw_st_c2h_err_process - }, - { - EQDMA_ST_C2H_ERR_SH_CMPT_DSC, - "A Shared CMPT queue has encountered a descriptor error", - EQDMA_C2H_ERR_MASK_ADDR, - EQDMA_C2H_ERR_STAT_ADDR, - C2H_ERR_STAT_SH_CMPT_DSC_ERR_MASK, - GLBL_ERR_STAT_ERR_C2H_ST_MASK, - &eqdma_hw_st_c2h_err_process - }, - { - EQDMA_ST_C2H_ERR_QID_MISMATCH, - "Qid mismatch error", - EQDMA_C2H_ERR_MASK_ADDR, - EQDMA_C2H_ERR_STAT_ADDR, - C2H_ERR_STAT_QID_MISMATCH_MASK, - GLBL_ERR_STAT_ERR_C2H_ST_MASK, - &eqdma_hw_st_c2h_err_process - }, - { - EQDMA_ST_C2H_ERR_DESC_RSP_ERR, - "Descriptor error bit set", - EQDMA_C2H_ERR_MASK_ADDR, - EQDMA_C2H_ERR_STAT_ADDR, - C2H_ERR_STAT_DESC_RSP_ERR_MASK, - GLBL_ERR_STAT_ERR_C2H_ST_MASK, - &eqdma_hw_st_c2h_err_process - }, - { - EQDMA_ST_C2H_ERR_ENG_WPL_DATA_PAR_ERR, - "Data parity error", - EQDMA_C2H_ERR_MASK_ADDR, - EQDMA_C2H_ERR_STAT_ADDR, - C2H_ERR_STAT_ENG_WPL_DATA_PAR_ERR_MASK, - GLBL_ERR_STAT_ERR_C2H_ST_MASK, - &eqdma_hw_st_c2h_err_process - }, - { - EQDMA_ST_C2H_ERR_MSI_INT_FAIL, - "MSI got a fail response error", - EQDMA_C2H_ERR_MASK_ADDR, - EQDMA_C2H_ERR_STAT_ADDR, - C2H_ERR_STAT_MSI_INT_FAIL_MASK, - GLBL_ERR_STAT_ERR_C2H_ST_MASK, - &eqdma_hw_st_c2h_err_process - }, - { - EQDMA_ST_C2H_ERR_ERR_DESC_CNT, - "Descriptor count error", - EQDMA_C2H_ERR_MASK_ADDR, - EQDMA_C2H_ERR_STAT_ADDR, - C2H_ERR_STAT_ERR_DESC_CNT_MASK, - GLBL_ERR_STAT_ERR_C2H_ST_MASK, - &eqdma_hw_st_c2h_err_process - }, - { - EQDMA_ST_C2H_ERR_PORTID_CTXT_MISMATCH, - "Port id in packet and pfetch ctxt mismatch error", - EQDMA_C2H_ERR_MASK_ADDR, - EQDMA_C2H_ERR_STAT_ADDR, - C2H_ERR_STAT_PORT_ID_CTXT_MISMATCH_MASK, - GLBL_ERR_STAT_ERR_C2H_ST_MASK, - &eqdma_hw_st_c2h_err_process - }, - { - EQDMA_ST_C2H_ERR_CMPT_INV_Q_ERR, - "Writeback on invalid queue error", - EQDMA_C2H_ERR_MASK_ADDR, - EQDMA_C2H_ERR_STAT_ADDR, - C2H_ERR_STAT_WRB_INV_Q_ERR_MASK, - GLBL_ERR_STAT_ERR_C2H_ST_MASK, - &eqdma_hw_st_c2h_err_process - }, - { - EQDMA_ST_C2H_ERR_CMPT_QFULL_ERR, - "Completion queue gets full error", - EQDMA_C2H_ERR_MASK_ADDR, - EQDMA_C2H_ERR_STAT_ADDR, - C2H_ERR_STAT_WRB_QFULL_ERR_MASK, - GLBL_ERR_STAT_ERR_C2H_ST_MASK, - &eqdma_hw_st_c2h_err_process - }, - { - EQDMA_ST_C2H_ERR_CMPT_CIDX_ERR, - "Bad CIDX update by the software error", - EQDMA_C2H_ERR_MASK_ADDR, - EQDMA_C2H_ERR_STAT_ADDR, - C2H_ERR_STAT_WRB_CIDX_ERR_MASK, - GLBL_ERR_STAT_ERR_C2H_ST_MASK, - &eqdma_hw_st_c2h_err_process - }, - { - EQDMA_ST_C2H_ERR_CMPT_PRTY_ERR, - "C2H completion Parity error", - EQDMA_C2H_ERR_MASK_ADDR, - EQDMA_C2H_ERR_STAT_ADDR, - C2H_ERR_STAT_WRB_PRTY_ERR_MASK, - GLBL_ERR_STAT_ERR_C2H_ST_MASK, - &eqdma_hw_st_c2h_err_process - }, - { - EQDMA_ST_C2H_ERR_AVL_RING_DSC, - "Available ring fetch returns descriptor with error", - EQDMA_C2H_ERR_MASK_ADDR, - EQDMA_C2H_ERR_STAT_ADDR, - C2H_ERR_STAT_AVL_RING_DSC_ERR_MASK, - GLBL_ERR_STAT_ERR_C2H_ST_MASK, - &eqdma_hw_st_c2h_err_process - }, - { - EQDMA_ST_C2H_ERR_HDR_ECC_UNC, - "multi-bit ecc error on c2h packet header", - EQDMA_C2H_ERR_MASK_ADDR, - EQDMA_C2H_ERR_STAT_ADDR, - C2H_ERR_STAT_HDR_ECC_UNC_ERR_MASK, - GLBL_ERR_STAT_ERR_C2H_ST_MASK, - &eqdma_hw_st_c2h_err_process - }, - { - EQDMA_ST_C2H_ERR_HDR_ECC_COR, - "single-bit ecc error on c2h packet header", - EQDMA_C2H_ERR_MASK_ADDR, - EQDMA_C2H_ERR_STAT_ADDR, - C2H_ERR_STAT_HDR_ECC_COR_ERR_MASK, - GLBL_ERR_STAT_ERR_C2H_ST_MASK, - &eqdma_hw_st_c2h_err_process - }, - { - EQDMA_ST_C2H_ERR_ALL, - "All C2h errors", - EQDMA_C2H_ERR_MASK_ADDR, - EQDMA_C2H_ERR_STAT_ADDR, - EQDMA_C2H_ERR_ALL_MASK, - GLBL_ERR_STAT_ERR_C2H_ST_MASK, - &eqdma_hw_st_c2h_err_process - }, - - /* C2H fatal errors */ - { - EQDMA_ST_FATAL_ERR_MTY_MISMATCH, - "Fatal MTY mismatch error", - EQDMA_C2H_FATAL_ERR_MASK_ADDR, - EQDMA_C2H_FATAL_ERR_STAT_ADDR, - C2H_FATAL_ERR_STAT_MTY_MISMATCH_MASK, - GLBL_ERR_STAT_ERR_C2H_ST_MASK, - &eqdma_hw_st_c2h_err_process - }, - { - EQDMA_ST_FATAL_ERR_LEN_MISMATCH, - "Fatal Len mismatch error", - EQDMA_C2H_FATAL_ERR_MASK_ADDR, - EQDMA_C2H_FATAL_ERR_STAT_ADDR, - C2H_FATAL_ERR_STAT_LEN_MISMATCH_MASK, - GLBL_ERR_STAT_ERR_C2H_ST_MASK, - &eqdma_hw_st_c2h_err_process - }, - { - EQDMA_ST_FATAL_ERR_QID_MISMATCH, - "Fatal Qid mismatch error", - EQDMA_C2H_FATAL_ERR_MASK_ADDR, - EQDMA_C2H_FATAL_ERR_STAT_ADDR, - C2H_FATAL_ERR_STAT_QID_MISMATCH_MASK, - GLBL_ERR_STAT_ERR_C2H_ST_MASK, - &eqdma_hw_st_c2h_err_process - }, - { - EQDMA_ST_FATAL_ERR_TIMER_FIFO_RAM_RDBE, - "RAM double bit fatal error", - EQDMA_C2H_FATAL_ERR_MASK_ADDR, - EQDMA_C2H_FATAL_ERR_STAT_ADDR, - C2H_FATAL_ERR_STAT_TIMER_FIFO_RAM_RDBE_MASK, - GLBL_ERR_STAT_ERR_C2H_ST_MASK, - &eqdma_hw_st_c2h_err_process - }, - { - EQDMA_ST_FATAL_ERR_PFCH_II_RAM_RDBE, - "RAM double bit fatal error", - EQDMA_C2H_FATAL_ERR_MASK_ADDR, - EQDMA_C2H_FATAL_ERR_STAT_ADDR, - C2H_FATAL_ERR_STAT_PFCH_LL_RAM_RDBE_MASK, - GLBL_ERR_STAT_ERR_C2H_ST_MASK, - &eqdma_hw_st_c2h_err_process - }, - { - EQDMA_ST_FATAL_ERR_CMPT_CTXT_RAM_RDBE, - "RAM double bit fatal error", - EQDMA_C2H_FATAL_ERR_MASK_ADDR, - EQDMA_C2H_FATAL_ERR_STAT_ADDR, - C2H_FATAL_ERR_STAT_WRB_CTXT_RAM_RDBE_MASK, - GLBL_ERR_STAT_ERR_C2H_ST_MASK, - &eqdma_hw_st_c2h_err_process - }, - { - EQDMA_ST_FATAL_ERR_PFCH_CTXT_RAM_RDBE, - "RAM double bit fatal error", - EQDMA_C2H_FATAL_ERR_MASK_ADDR, - EQDMA_C2H_FATAL_ERR_STAT_ADDR, - C2H_FATAL_ERR_STAT_PFCH_CTXT_RAM_RDBE_MASK, - GLBL_ERR_STAT_ERR_C2H_ST_MASK, - &eqdma_hw_st_c2h_err_process - }, - { - EQDMA_ST_FATAL_ERR_DESC_REQ_FIFO_RAM_RDBE, - "RAM double bit fatal error", - EQDMA_C2H_FATAL_ERR_MASK_ADDR, - EQDMA_C2H_FATAL_ERR_STAT_ADDR, - C2H_FATAL_ERR_STAT_DESC_REQ_FIFO_RAM_RDBE_MASK, - GLBL_ERR_STAT_ERR_C2H_ST_MASK, - &eqdma_hw_st_c2h_err_process - }, - { - EQDMA_ST_FATAL_ERR_INT_CTXT_RAM_RDBE, - "RAM double bit fatal error", - EQDMA_C2H_FATAL_ERR_MASK_ADDR, - EQDMA_C2H_FATAL_ERR_STAT_ADDR, - C2H_FATAL_ERR_STAT_INT_CTXT_RAM_RDBE_MASK, - GLBL_ERR_STAT_ERR_C2H_ST_MASK, - &eqdma_hw_st_c2h_err_process - }, - { - EQDMA_ST_FATAL_ERR_CMPT_COAL_DATA_RAM_RDBE, - "RAM double bit fatal error", - EQDMA_C2H_FATAL_ERR_MASK_ADDR, - EQDMA_C2H_FATAL_ERR_STAT_ADDR, - C2H_FATAL_ERR_STAT_WRB_COAL_DATA_RAM_RDBE_MASK, - GLBL_ERR_STAT_ERR_C2H_ST_MASK, - &eqdma_hw_st_c2h_err_process - }, - { - EQDMA_ST_FATAL_ERR_CMPT_FIFO_RAM_RDBE, - "RAM double bit fatal error", - EQDMA_C2H_FATAL_ERR_MASK_ADDR, - EQDMA_C2H_FATAL_ERR_STAT_ADDR, - C2H_FATAL_ERR_STAT_CMPT_FIFO_RAM_RDBE_MASK, - GLBL_ERR_STAT_ERR_C2H_ST_MASK, - &eqdma_hw_st_c2h_err_process - }, - { - EQDMA_ST_FATAL_ERR_QID_FIFO_RAM_RDBE, - "RAM double bit fatal error", - EQDMA_C2H_FATAL_ERR_MASK_ADDR, - EQDMA_C2H_FATAL_ERR_STAT_ADDR, - C2H_FATAL_ERR_STAT_QID_FIFO_RAM_RDBE_MASK, - GLBL_ERR_STAT_ERR_C2H_ST_MASK, - &eqdma_hw_st_c2h_err_process - }, - { - EQDMA_ST_FATAL_ERR_PAYLOAD_FIFO_RAM_RDBE, - "RAM double bit fatal error", - EQDMA_C2H_FATAL_ERR_MASK_ADDR, - EQDMA_C2H_FATAL_ERR_STAT_ADDR, - C2H_FATAL_ERR_STAT_PLD_FIFO_RAM_RDBE_MASK, - GLBL_ERR_STAT_ERR_C2H_ST_MASK, - &eqdma_hw_st_c2h_err_process - }, - { - EQDMA_ST_FATAL_ERR_WPL_DATA_PAR, - "RAM double bit fatal error", - EQDMA_C2H_FATAL_ERR_MASK_ADDR, - EQDMA_C2H_FATAL_ERR_STAT_ADDR, - C2H_FATAL_ERR_STAT_WPL_DATA_PAR_ERR_MASK, - GLBL_ERR_STAT_ERR_C2H_ST_MASK, - &eqdma_hw_st_c2h_err_process - }, - { - EQDMA_ST_FATAL_ERR_AVL_RING_FIFO_RAM_RDBE, - "RAM double bit fatal error", - EQDMA_C2H_FATAL_ERR_MASK_ADDR, - EQDMA_C2H_FATAL_ERR_STAT_ADDR, - C2H_FATAL_ERR_STAT_AVL_RING_FIFO_RAM_RDBE_MASK, - GLBL_ERR_STAT_ERR_C2H_ST_MASK, - &eqdma_hw_st_c2h_err_process - }, - { - EQDMA_ST_FATAL_ERR_HDR_ECC_UNC, - "RAM double bit fatal error", - EQDMA_C2H_FATAL_ERR_MASK_ADDR, - EQDMA_C2H_FATAL_ERR_STAT_ADDR, - C2H_FATAL_ERR_STAT_HDR_ECC_UNC_ERR_MASK, - GLBL_ERR_STAT_ERR_C2H_ST_MASK, - &eqdma_hw_st_c2h_err_process - }, - { - EQDMA_ST_FATAL_ERR_ALL, - "All fatal errors", - EQDMA_C2H_FATAL_ERR_MASK_ADDR, - EQDMA_C2H_FATAL_ERR_STAT_ADDR, - EQDMA_C2H_FATAL_ERR_ALL_MASK, - GLBL_ERR_STAT_ERR_C2H_ST_MASK, - &eqdma_hw_st_c2h_err_process - }, - - /* H2C St errors */ - { - EQDMA_ST_H2C_ERR_ZERO_LEN_DESC, - "Zero length descriptor error", - EQDMA_H2C_ERR_MASK_ADDR, - EQDMA_H2C_ERR_STAT_ADDR, - H2C_ERR_STAT_ZERO_LEN_DS_MASK, - GLBL_ERR_STAT_ERR_H2C_ST_MASK, - &eqdma_hw_st_h2c_err_process - }, - { - EQDMA_ST_H2C_ERR_SDI_MRKR_REQ_MOP, - "A non-EOP descriptor received", - EQDMA_H2C_ERR_MASK_ADDR, - EQDMA_H2C_ERR_STAT_ADDR, - H2C_ERR_STAT_SDI_MRKR_REQ_MOP_ERR_MASK, - GLBL_ERR_STAT_ERR_H2C_ST_MASK, - &eqdma_hw_st_h2c_err_process - }, - { - EQDMA_ST_H2C_ERR_NO_DMA_DSC, - "No DMA descriptor received error", - EQDMA_H2C_ERR_MASK_ADDR, - EQDMA_H2C_ERR_STAT_ADDR, - H2C_ERR_STAT_NO_DMA_DS_MASK, - GLBL_ERR_STAT_ERR_H2C_ST_MASK, - &eqdma_hw_st_h2c_err_process - }, - { - EQDMA_ST_H2C_ERR_SBE, - "Single bit error detected on H2C-ST data error", - EQDMA_H2C_ERR_MASK_ADDR, - EQDMA_H2C_ERR_STAT_ADDR, - H2C_ERR_STAT_SBE_MASK, - GLBL_ERR_STAT_ERR_H2C_ST_MASK, - &eqdma_hw_st_h2c_err_process - }, - { - EQDMA_ST_H2C_ERR_DBE, - "Double bit error detected on H2C-ST data error", - EQDMA_H2C_ERR_MASK_ADDR, - EQDMA_H2C_ERR_STAT_ADDR, - H2C_ERR_STAT_DBE_MASK, - GLBL_ERR_STAT_ERR_H2C_ST_MASK, - &eqdma_hw_st_h2c_err_process - }, - { - EQDMA_ST_H2C_ERR_PAR, - "Internal data parity error", - EQDMA_H2C_ERR_MASK_ADDR, - EQDMA_H2C_ERR_STAT_ADDR, - H2C_ERR_STAT_PAR_ERR_MASK, - GLBL_ERR_STAT_ERR_H2C_ST_MASK, - &eqdma_hw_st_h2c_err_process - }, - { - EQDMA_ST_H2C_ERR_ALL, - "All H2C errors", - EQDMA_H2C_ERR_MASK_ADDR, - EQDMA_H2C_ERR_STAT_ADDR, - EQDMA_H2C_ERR_ALL_MASK, - GLBL_ERR_STAT_ERR_H2C_ST_MASK, - &eqdma_hw_st_h2c_err_process - }, - - /* SBE errors */ - { - EQDMA_SBE_1_ERR_RC_RRQ_EVEN_RAM, - "RC RRQ Even RAM single bit ECC error.", - EQDMA_RAM_SBE_MSK_1_A_ADDR, - EQDMA_RAM_SBE_STS_1_A_ADDR, - RAM_SBE_STS_1_A_RC_RRQ_EVEN_RAM_MASK, - GLBL_ERR_STAT_ERR_RAM_SBE_MASK, - &eqdma_hw_ram_sbe_err_process - }, - { - EQDMA_SBE_1_ERR_TAG_ODD_RAM, - "Tag Odd Ram single bit ECC error.", - EQDMA_RAM_SBE_MSK_1_A_ADDR, - EQDMA_RAM_SBE_STS_1_A_ADDR, - RAM_SBE_STS_1_A_TAG_ODD_RAM_MASK, - GLBL_ERR_STAT_ERR_RAM_SBE_MASK, - &eqdma_hw_ram_sbe_err_process - }, - { - EQDMA_SBE_1_ERR_TAG_EVEN_RAM, - "Tag Even Ram single bit ECC error.", - EQDMA_RAM_SBE_MSK_1_A_ADDR, - EQDMA_RAM_SBE_STS_1_A_ADDR, - RAM_SBE_STS_1_A_TAG_EVEN_RAM_MASK, - GLBL_ERR_STAT_ERR_RAM_SBE_MASK, - &eqdma_hw_ram_sbe_err_process - }, - { - EQDMA_SBE_1_ERR_PFCH_CTXT_CAM_RAM_0, - "Pfch Ctxt CAM RAM 0 single bit ECC error.", - EQDMA_RAM_SBE_MSK_1_A_ADDR, - EQDMA_RAM_SBE_STS_1_A_ADDR, - RAM_SBE_STS_1_A_PFCH_CTXT_CAM_RAM_0_MASK, - GLBL_ERR_STAT_ERR_RAM_SBE_MASK, - &eqdma_hw_ram_sbe_err_process - }, - { - EQDMA_SBE_1_ERR_PFCH_CTXT_CAM_RAM_1, - "Pfch Ctxt CAM RAM 1 single bit ECC error.", - EQDMA_RAM_SBE_MSK_1_A_ADDR, - EQDMA_RAM_SBE_STS_1_A_ADDR, - RAM_SBE_STS_1_A_PFCH_CTXT_CAM_RAM_1_MASK, - GLBL_ERR_STAT_ERR_RAM_SBE_MASK, - &eqdma_hw_ram_sbe_err_process - }, - { - EQDMA_SBE_1_ERR_ALL, - "All SBE Errors.", - EQDMA_RAM_SBE_MSK_1_A_ADDR, - EQDMA_RAM_SBE_STS_1_A_ADDR, - EQDMA_SBE_ERR_ALL_MASK, - GLBL_ERR_STAT_ERR_RAM_SBE_MASK, - &eqdma_hw_ram_sbe_err_process - }, - { - EQDMA_SBE_ERR_MI_H2C0_DAT, - "H2C MM data buffer single bit ECC error", - EQDMA_RAM_SBE_MSK_A_ADDR, - EQDMA_RAM_SBE_STS_A_ADDR, - RAM_SBE_STS_A_MI_H2C0_DAT_MASK, - GLBL_ERR_STAT_ERR_RAM_SBE_MASK, - &eqdma_hw_ram_sbe_err_process - }, - { - EQDMA_SBE_ERR_MI_H2C1_DAT, - "H2C MM data buffer single bit ECC error", - EQDMA_RAM_SBE_MSK_A_ADDR, - EQDMA_RAM_SBE_STS_A_ADDR, - RAM_SBE_STS_A_MI_H2C1_DAT_MASK, - GLBL_ERR_STAT_ERR_RAM_SBE_MASK, - &eqdma_hw_ram_sbe_err_process - }, - { - EQDMA_SBE_ERR_MI_H2C2_DAT, - "H2C MM data buffer single bit ECC error", - EQDMA_RAM_SBE_MSK_A_ADDR, - EQDMA_RAM_SBE_STS_A_ADDR, - RAM_SBE_STS_A_MI_H2C2_DAT_MASK, - GLBL_ERR_STAT_ERR_RAM_SBE_MASK, - &eqdma_hw_ram_sbe_err_process - }, - { - EQDMA_SBE_ERR_MI_H2C3_DAT, - "H2C MM data buffer single bit ECC error", - EQDMA_RAM_SBE_MSK_A_ADDR, - EQDMA_RAM_SBE_STS_A_ADDR, - RAM_SBE_STS_A_MI_H2C3_DAT_MASK, - GLBL_ERR_STAT_ERR_RAM_SBE_MASK, - &eqdma_hw_ram_sbe_err_process - }, - { - EQDMA_SBE_ERR_MI_C2H0_DAT, - "C2H MM data buffer single bit ECC error", - EQDMA_RAM_SBE_MSK_A_ADDR, - EQDMA_RAM_SBE_STS_A_ADDR, - RAM_SBE_STS_A_MI_C2H0_DAT_MASK, - GLBL_ERR_STAT_ERR_RAM_SBE_MASK, - &eqdma_hw_ram_sbe_err_process - }, - { - EQDMA_SBE_ERR_MI_C2H1_DAT, - "C2H MM data buffer single bit ECC error", - EQDMA_RAM_SBE_MSK_A_ADDR, - EQDMA_RAM_SBE_STS_A_ADDR, - RAM_SBE_STS_A_MI_C2H1_DAT_MASK, - GLBL_ERR_STAT_ERR_RAM_SBE_MASK, - &eqdma_hw_ram_sbe_err_process - }, -{ - EQDMA_SBE_ERR_MI_C2H2_DAT, - "C2H MM data buffer single bit ECC error", - EQDMA_RAM_SBE_MSK_A_ADDR, - EQDMA_RAM_SBE_STS_A_ADDR, - RAM_SBE_STS_A_MI_C2H2_DAT_MASK, - GLBL_ERR_STAT_ERR_RAM_SBE_MASK, - &eqdma_hw_ram_sbe_err_process - }, - { - EQDMA_SBE_ERR_MI_C2H3_DAT, - "C2H MM data buffer single bit ECC error", - EQDMA_RAM_SBE_MSK_A_ADDR, - EQDMA_RAM_SBE_STS_A_ADDR, - RAM_SBE_STS_A_MI_C2H3_DAT_MASK, - GLBL_ERR_STAT_ERR_RAM_SBE_MASK, - &eqdma_hw_ram_sbe_err_process - }, - { - EQDMA_SBE_ERR_H2C_RD_BRG_DAT, - "Bridge master read single bit ECC error", - EQDMA_RAM_SBE_MSK_A_ADDR, - EQDMA_RAM_SBE_STS_A_ADDR, - RAM_SBE_STS_A_H2C_RD_BRG_DAT_MASK, - GLBL_ERR_STAT_ERR_RAM_SBE_MASK, - &eqdma_hw_ram_sbe_err_process - }, - { - EQDMA_SBE_ERR_H2C_WR_BRG_DAT, - "Bridge master write single bit ECC error", - EQDMA_RAM_SBE_MSK_A_ADDR, - EQDMA_RAM_SBE_STS_A_ADDR, - RAM_SBE_STS_A_H2C_WR_BRG_DAT_MASK, - GLBL_ERR_STAT_ERR_RAM_SBE_MASK, - &eqdma_hw_ram_sbe_err_process - }, - { - EQDMA_SBE_ERR_C2H_RD_BRG_DAT, - "Bridge slave read data buffer single bit ECC error", - EQDMA_RAM_SBE_MSK_A_ADDR, - EQDMA_RAM_SBE_STS_A_ADDR, - RAM_SBE_STS_A_C2H_RD_BRG_DAT_MASK, - GLBL_ERR_STAT_ERR_RAM_SBE_MASK, - &eqdma_hw_ram_sbe_err_process - }, - { - EQDMA_SBE_ERR_C2H_WR_BRG_DAT, - "Bridge slave write data buffer single bit ECC error", - EQDMA_RAM_SBE_MSK_A_ADDR, - EQDMA_RAM_SBE_STS_A_ADDR, - RAM_SBE_STS_A_C2H_WR_BRG_DAT_MASK, - GLBL_ERR_STAT_ERR_RAM_SBE_MASK, - &eqdma_hw_ram_sbe_err_process - }, - { - EQDMA_SBE_ERR_FUNC_MAP, - "Function map RAM single bit ECC error", - EQDMA_RAM_SBE_MSK_A_ADDR, - EQDMA_RAM_SBE_STS_A_ADDR, - RAM_SBE_STS_A_FUNC_MAP_MASK, - GLBL_ERR_STAT_ERR_RAM_SBE_MASK, - &eqdma_hw_ram_sbe_err_process - }, - { - EQDMA_SBE_ERR_DSC_HW_CTXT, - "Descriptor engine hardware context RAM single bit ECC error", - EQDMA_RAM_SBE_MSK_A_ADDR, - EQDMA_RAM_SBE_STS_A_ADDR, - RAM_SBE_STS_A_DSC_HW_CTXT_MASK, - GLBL_ERR_STAT_ERR_RAM_SBE_MASK, - &eqdma_hw_ram_sbe_err_process - }, - { - EQDMA_SBE_ERR_DSC_CRD_RCV, - "Descriptor engine receive credit context RAM single bit ECC error", - EQDMA_RAM_SBE_MSK_A_ADDR, - EQDMA_RAM_SBE_STS_A_ADDR, - RAM_SBE_STS_A_DSC_CRD_RCV_MASK, - GLBL_ERR_STAT_ERR_RAM_SBE_MASK, - &eqdma_hw_ram_sbe_err_process - }, - { - EQDMA_SBE_ERR_DSC_SW_CTXT, - "Descriptor engine software context RAM single bit ECC error", - EQDMA_RAM_SBE_MSK_A_ADDR, - EQDMA_RAM_SBE_STS_A_ADDR, - RAM_SBE_STS_A_DSC_SW_CTXT_MASK, - GLBL_ERR_STAT_ERR_RAM_SBE_MASK, - &eqdma_hw_ram_sbe_err_process - }, - { - EQDMA_SBE_ERR_DSC_CPLI, - "Descriptor engine fetch completion information RAM single bit ECC error", - EQDMA_RAM_SBE_MSK_A_ADDR, - EQDMA_RAM_SBE_STS_A_ADDR, - RAM_SBE_STS_A_DSC_CPLI_MASK, - GLBL_ERR_STAT_ERR_RAM_SBE_MASK, - &eqdma_hw_ram_sbe_err_process - }, - { - EQDMA_SBE_ERR_DSC_CPLD, - "Descriptor engine fetch completion data RAM single bit ECC error", - EQDMA_RAM_SBE_MSK_A_ADDR, - EQDMA_RAM_SBE_STS_A_ADDR, - RAM_SBE_STS_A_DSC_CPLD_MASK, - GLBL_ERR_STAT_ERR_RAM_SBE_MASK, - &eqdma_hw_ram_sbe_err_process - }, - { - EQDMA_SBE_ERR_MI_TL_SLV_FIFO_RAM, - "TL Slavle FIFO RAM single bit ECC error", - EQDMA_RAM_SBE_MSK_A_ADDR, - EQDMA_RAM_SBE_STS_A_ADDR, - RAM_SBE_STS_A_MI_TL_SLV_FIFO_RAM_MASK, - GLBL_ERR_STAT_ERR_RAM_SBE_MASK, - &eqdma_hw_ram_sbe_err_process - }, - { - EQDMA_SBE_ERR_TIMER_FIFO_RAM, - "Timer fifo RAM single bit ECC error", - EQDMA_RAM_SBE_MSK_A_ADDR, - EQDMA_RAM_SBE_STS_A_ADDR, - RAM_SBE_STS_A_TIMER_FIFO_RAM_MASK, - GLBL_ERR_STAT_ERR_RAM_SBE_MASK, - &eqdma_hw_ram_sbe_err_process - }, - { - EQDMA_SBE_ERR_QID_FIFO_RAM, - "C2H ST QID FIFO RAM single bit ECC error", - EQDMA_RAM_SBE_MSK_A_ADDR, - EQDMA_RAM_SBE_STS_A_ADDR, - RAM_SBE_STS_A_QID_FIFO_RAM_MASK, - GLBL_ERR_STAT_ERR_RAM_SBE_MASK, - &eqdma_hw_ram_sbe_err_process - }, - { - EQDMA_SBE_ERR_WRB_COAL_DATA_RAM, - "Writeback Coalescing RAM single bit ECC error", - EQDMA_RAM_SBE_MSK_A_ADDR, - EQDMA_RAM_SBE_STS_A_ADDR, - RAM_SBE_STS_A_WRB_COAL_DATA_RAM_MASK, - GLBL_ERR_STAT_ERR_RAM_SBE_MASK, - &eqdma_hw_ram_sbe_err_process - }, - { - EQDMA_SBE_ERR_INT_CTXT_RAM, - "Interrupt context RAM single bit ECC error", - EQDMA_RAM_SBE_MSK_A_ADDR, - EQDMA_RAM_SBE_STS_A_ADDR, - RAM_SBE_STS_A_INT_CTXT_RAM_MASK, - GLBL_ERR_STAT_ERR_RAM_SBE_MASK, - &eqdma_hw_ram_sbe_err_process - }, - { - EQDMA_SBE_ERR_DESC_REQ_FIFO_RAM, - "C2H ST descriptor request RAM single bit ECC error", - EQDMA_RAM_SBE_MSK_A_ADDR, - EQDMA_RAM_SBE_STS_A_ADDR, - RAM_SBE_STS_A_DESC_REQ_FIFO_RAM_MASK, - GLBL_ERR_STAT_ERR_RAM_SBE_MASK, - &eqdma_hw_ram_sbe_err_process - }, - { - EQDMA_SBE_ERR_PFCH_CTXT_RAM, - "C2H ST prefetch RAM single bit ECC error", - EQDMA_RAM_SBE_MSK_A_ADDR, - EQDMA_RAM_SBE_STS_A_ADDR, - RAM_SBE_STS_A_PFCH_CTXT_RAM_MASK, - GLBL_ERR_STAT_ERR_RAM_SBE_MASK, - &eqdma_hw_ram_sbe_err_process - }, - { - EQDMA_SBE_ERR_WRB_CTXT_RAM, - "C2H ST completion context RAM single bit ECC error", - EQDMA_RAM_SBE_MSK_A_ADDR, - EQDMA_RAM_SBE_STS_A_ADDR, - RAM_SBE_STS_A_WRB_CTXT_RAM_MASK, - GLBL_ERR_STAT_ERR_RAM_SBE_MASK, - &eqdma_hw_ram_sbe_err_process - }, - { - EQDMA_SBE_ERR_PFCH_LL_RAM, - "C2H ST prefetch list RAM single bit ECC error", - EQDMA_RAM_SBE_MSK_A_ADDR, - EQDMA_RAM_SBE_STS_A_ADDR, - RAM_SBE_STS_A_PFCH_LL_RAM_MASK, - GLBL_ERR_STAT_ERR_RAM_SBE_MASK, - &eqdma_hw_ram_sbe_err_process - }, - { - EQDMA_SBE_ERR_PEND_FIFO_RAM, - "Pend FIFO RAM single bit ECC error", - EQDMA_RAM_SBE_MSK_A_ADDR, - EQDMA_RAM_SBE_STS_A_ADDR, - RAM_SBE_STS_A_PEND_FIFO_RAM_MASK, - GLBL_ERR_STAT_ERR_RAM_SBE_MASK, - &eqdma_hw_ram_sbe_err_process - }, - { - EQDMA_SBE_ERR_RC_RRQ_ODD_RAM, - "RC RRQ Odd RAM single bit ECC error.", - EQDMA_RAM_SBE_MSK_A_ADDR, - EQDMA_RAM_SBE_STS_A_ADDR, - RAM_SBE_STS_A_RC_RRQ_ODD_RAM_MASK, - GLBL_ERR_STAT_ERR_RAM_SBE_MASK, - &eqdma_hw_ram_sbe_err_process - }, - { - EQDMA_SBE_ERR_ALL, - "All SBE errors", - EQDMA_RAM_SBE_MSK_A_ADDR, - EQDMA_RAM_SBE_STS_A_ADDR, - EQDMA_SBE_ERR_ALL_MASK, - GLBL_ERR_STAT_ERR_RAM_SBE_MASK, - &eqdma_hw_ram_sbe_err_process - }, - - - /* DBE errors */ - { - EQDMA_DBE_1_ERR_RC_RRQ_EVEN_RAM, - "RC RRQ Odd RAM double bit ECC error.", - EQDMA_RAM_DBE_MSK_1_A_ADDR, - EQDMA_RAM_DBE_STS_1_A_ADDR, - RAM_DBE_STS_1_A_RC_RRQ_EVEN_RAM_MASK, - GLBL_ERR_STAT_ERR_RAM_DBE_MASK, - &eqdma_hw_ram_dbe_err_process - }, - { - EQDMA_DBE_1_ERR_TAG_ODD_RAM, - "Tag Odd Ram double bit ECC error.", - EQDMA_RAM_DBE_MSK_1_A_ADDR, - EQDMA_RAM_DBE_STS_1_A_ADDR, - RAM_DBE_STS_1_A_TAG_ODD_RAM_MASK, - GLBL_ERR_STAT_ERR_RAM_DBE_MASK, - &eqdma_hw_ram_dbe_err_process - }, - { - EQDMA_DBE_1_ERR_TAG_EVEN_RAM, - "Tag Even Ram double bit ECC error.", - EQDMA_RAM_DBE_MSK_1_A_ADDR, - EQDMA_RAM_DBE_STS_1_A_ADDR, - RAM_DBE_STS_1_A_TAG_EVEN_RAM_MASK, - GLBL_ERR_STAT_ERR_RAM_DBE_MASK, - &eqdma_hw_ram_dbe_err_process - }, - { - EQDMA_DBE_1_ERR_PFCH_CTXT_CAM_RAM_0, - "Pfch Ctxt CAM RAM 0 double bit ECC error.", - EQDMA_RAM_DBE_MSK_1_A_ADDR, - EQDMA_RAM_DBE_STS_1_A_ADDR, - RAM_DBE_STS_1_A_PFCH_CTXT_CAM_RAM_0_MASK, - GLBL_ERR_STAT_ERR_RAM_DBE_MASK, - &eqdma_hw_ram_dbe_err_process - }, - { - EQDMA_DBE_1_ERR_PFCH_CTXT_CAM_RAM_1, - "Pfch Ctxt CAM RAM double bit ECC error.", - EQDMA_RAM_DBE_MSK_1_A_ADDR, - EQDMA_RAM_DBE_STS_1_A_ADDR, - RAM_DBE_STS_1_A_PFCH_CTXT_CAM_RAM_0_MASK, - GLBL_ERR_STAT_ERR_RAM_DBE_MASK, - &eqdma_hw_ram_dbe_err_process - }, - { - EQDMA_DBE_1_ERR_ALL, - "All DBE errors", - EQDMA_RAM_DBE_MSK_1_A_ADDR, - EQDMA_RAM_DBE_STS_1_A_ADDR, - EQDMA_DBE_ERR_ALL_MASK, - GLBL_ERR_STAT_ERR_RAM_DBE_MASK, - &eqdma_hw_ram_dbe_err_process - }, - { - EQDMA_DBE_ERR_MI_H2C0_DAT, - "H2C MM data buffer double bit ECC error", - EQDMA_RAM_DBE_MSK_A_ADDR, - EQDMA_RAM_DBE_STS_A_ADDR, - RAM_DBE_STS_A_MI_H2C0_DAT_MASK, - GLBL_ERR_STAT_ERR_RAM_DBE_MASK, - &eqdma_hw_ram_dbe_err_process - }, - { - EQDMA_DBE_ERR_MI_H2C1_DAT, - "H2C MM data buffer double bit ECC error", - EQDMA_RAM_DBE_MSK_A_ADDR, - EQDMA_RAM_DBE_STS_A_ADDR, - RAM_DBE_STS_A_MI_H2C1_DAT_MASK, - GLBL_ERR_STAT_ERR_RAM_DBE_MASK, - &eqdma_hw_ram_dbe_err_process - }, - { - EQDMA_DBE_ERR_MI_H2C2_DAT, - "H2C MM data buffer double bit ECC error", - EQDMA_RAM_DBE_MSK_A_ADDR, - EQDMA_RAM_DBE_STS_A_ADDR, - RAM_DBE_STS_A_MI_H2C2_DAT_MASK, - GLBL_ERR_STAT_ERR_RAM_DBE_MASK, - &eqdma_hw_ram_dbe_err_process - }, - { - EQDMA_DBE_ERR_MI_H2C3_DAT, - "H2C MM data buffer double bit ECC error", - EQDMA_RAM_DBE_MSK_A_ADDR, - EQDMA_RAM_DBE_STS_A_ADDR, - RAM_DBE_STS_A_MI_H2C3_DAT_MASK, - GLBL_ERR_STAT_ERR_RAM_DBE_MASK, - &eqdma_hw_ram_dbe_err_process - }, - { - EQDMA_DBE_ERR_MI_C2H0_DAT, - "C2H MM data buffer double bit ECC error", - EQDMA_RAM_DBE_MSK_A_ADDR, - EQDMA_RAM_DBE_STS_A_ADDR, - RAM_DBE_STS_A_MI_C2H0_DAT_MASK, - GLBL_ERR_STAT_ERR_RAM_DBE_MASK, - &eqdma_hw_ram_dbe_err_process - }, - { - EQDMA_DBE_ERR_MI_C2H1_DAT, - "C2H MM data buffer double bit ECC error", - EQDMA_RAM_DBE_MSK_A_ADDR, - EQDMA_RAM_DBE_STS_A_ADDR, - RAM_DBE_STS_A_MI_C2H1_DAT_MASK, - GLBL_ERR_STAT_ERR_RAM_DBE_MASK, - &eqdma_hw_ram_dbe_err_process - }, - { - EQDMA_DBE_ERR_MI_C2H2_DAT, - "C2H MM data buffer double bit ECC error", - EQDMA_RAM_DBE_MSK_A_ADDR, - EQDMA_RAM_DBE_STS_A_ADDR, - RAM_DBE_STS_A_MI_C2H2_DAT_MASK, - GLBL_ERR_STAT_ERR_RAM_DBE_MASK, - &eqdma_hw_ram_dbe_err_process - }, - { - EQDMA_DBE_ERR_MI_C2H3_DAT, - "C2H MM data buffer double bit ECC error", - EQDMA_RAM_DBE_MSK_A_ADDR, - EQDMA_RAM_DBE_STS_A_ADDR, - RAM_DBE_STS_A_MI_C2H3_DAT_MASK, - GLBL_ERR_STAT_ERR_RAM_DBE_MASK, - &eqdma_hw_ram_dbe_err_process - }, - { - EQDMA_DBE_ERR_H2C_RD_BRG_DAT, - "Bridge master read double bit ECC error", - EQDMA_RAM_DBE_MSK_A_ADDR, - EQDMA_RAM_DBE_STS_A_ADDR, - RAM_DBE_STS_A_H2C_RD_BRG_DAT_MASK, - GLBL_ERR_STAT_ERR_RAM_DBE_MASK, - &eqdma_hw_ram_dbe_err_process - }, - { - EQDMA_DBE_ERR_H2C_WR_BRG_DAT, - "Bridge master write double bit ECC error", - EQDMA_RAM_DBE_MSK_A_ADDR, - EQDMA_RAM_DBE_STS_A_ADDR, - RAM_DBE_STS_A_H2C_WR_BRG_DAT_MASK, - GLBL_ERR_STAT_ERR_RAM_DBE_MASK, - &eqdma_hw_ram_dbe_err_process - }, - { - EQDMA_DBE_ERR_C2H_RD_BRG_DAT, - "Bridge slave read data buffer double bit ECC error", - EQDMA_RAM_DBE_MSK_A_ADDR, - EQDMA_RAM_DBE_STS_A_ADDR, - RAM_DBE_STS_A_C2H_RD_BRG_DAT_MASK, - GLBL_ERR_STAT_ERR_RAM_DBE_MASK, - &eqdma_hw_ram_dbe_err_process - }, - { - EQDMA_DBE_ERR_C2H_WR_BRG_DAT, - "Bridge slave write data buffer double bit ECC error", - EQDMA_RAM_DBE_MSK_A_ADDR, - EQDMA_RAM_DBE_STS_A_ADDR, - RAM_DBE_STS_A_C2H_WR_BRG_DAT_MASK, - GLBL_ERR_STAT_ERR_RAM_DBE_MASK, - &eqdma_hw_ram_dbe_err_process - }, - { - EQDMA_DBE_ERR_FUNC_MAP, - "Function map RAM double bit ECC error", - EQDMA_RAM_DBE_MSK_A_ADDR, - EQDMA_RAM_DBE_STS_A_ADDR, - RAM_DBE_STS_A_FUNC_MAP_MASK, - GLBL_ERR_STAT_ERR_RAM_DBE_MASK, - &eqdma_hw_ram_dbe_err_process - }, - { - EQDMA_DBE_ERR_DSC_HW_CTXT, - "Descriptor engine hardware context RAM double bit ECC error", - EQDMA_RAM_DBE_MSK_A_ADDR, - EQDMA_RAM_DBE_STS_A_ADDR, - RAM_DBE_STS_A_DSC_HW_CTXT_MASK, - GLBL_ERR_STAT_ERR_RAM_DBE_MASK, - &eqdma_hw_ram_dbe_err_process - }, - { - EQDMA_DBE_ERR_DSC_CRD_RCV, - "Descriptor engine receive credit context RAM double bit ECC error", - EQDMA_RAM_DBE_MSK_A_ADDR, - EQDMA_RAM_DBE_STS_A_ADDR, - RAM_DBE_STS_A_DSC_CRD_RCV_MASK, - GLBL_ERR_STAT_ERR_RAM_DBE_MASK, - &eqdma_hw_ram_dbe_err_process - }, - { - EQDMA_DBE_ERR_DSC_SW_CTXT, - "Descriptor engine software context RAM double bit ECC error", - EQDMA_RAM_DBE_MSK_A_ADDR, - EQDMA_RAM_DBE_STS_A_ADDR, - RAM_DBE_STS_A_DSC_SW_CTXT_MASK, - GLBL_ERR_STAT_ERR_RAM_DBE_MASK, - &eqdma_hw_ram_dbe_err_process - }, - { - EQDMA_DBE_ERR_DSC_CPLI, - "Descriptor engine fetch completion information RAM double bit ECC error", - EQDMA_RAM_DBE_MSK_A_ADDR, - EQDMA_RAM_DBE_STS_A_ADDR, - RAM_DBE_STS_A_DSC_CPLI_MASK, - GLBL_ERR_STAT_ERR_RAM_DBE_MASK, - &eqdma_hw_ram_dbe_err_process - }, - { - EQDMA_DBE_ERR_DSC_CPLD, - "Descriptor engine fetch completion data RAM double bit ECC error", - EQDMA_RAM_DBE_MSK_A_ADDR, - EQDMA_RAM_DBE_STS_A_ADDR, - RAM_DBE_STS_A_DSC_CPLD_MASK, - GLBL_ERR_STAT_ERR_RAM_DBE_MASK, - &eqdma_hw_ram_dbe_err_process - }, - { - EQDMA_DBE_ERR_MI_TL_SLV_FIFO_RAM, - "TL Slave FIFO RAM double bit ECC error", - EQDMA_RAM_DBE_MSK_A_ADDR, - EQDMA_RAM_DBE_STS_A_ADDR, - RAM_DBE_STS_A_MI_TL_SLV_FIFO_RAM_MASK, - GLBL_ERR_STAT_ERR_RAM_DBE_MASK, - &eqdma_hw_ram_dbe_err_process - }, - { - EQDMA_DBE_ERR_TIMER_FIFO_RAM, - "Timer fifo RAM double bit ECC error", - EQDMA_RAM_DBE_MSK_A_ADDR, - EQDMA_RAM_DBE_STS_A_ADDR, - RAM_DBE_STS_A_TIMER_FIFO_RAM_MASK, - GLBL_ERR_STAT_ERR_RAM_DBE_MASK, - &eqdma_hw_ram_dbe_err_process - }, - { - EQDMA_DBE_ERR_QID_FIFO_RAM, - "C2H ST QID FIFO RAM double bit ECC error", - EQDMA_RAM_DBE_MSK_A_ADDR, - EQDMA_RAM_DBE_STS_A_ADDR, - RAM_DBE_STS_A_QID_FIFO_RAM_MASK, - GLBL_ERR_STAT_ERR_RAM_DBE_MASK, - &eqdma_hw_ram_dbe_err_process - }, - { - EQDMA_DBE_ERR_WRB_COAL_DATA_RAM, - "Writeback Coalescing RAM double bit ECC error", - EQDMA_RAM_DBE_MSK_A_ADDR, - EQDMA_RAM_DBE_STS_A_ADDR, - RAM_DBE_STS_A_WRB_COAL_DATA_RAM_MASK, - GLBL_ERR_STAT_ERR_RAM_DBE_MASK, - &eqdma_hw_ram_dbe_err_process - }, - { - EQDMA_DBE_ERR_INT_CTXT_RAM, - "Interrupt context RAM double bit ECC error", - EQDMA_RAM_DBE_MSK_A_ADDR, - EQDMA_RAM_DBE_STS_A_ADDR, - RAM_DBE_STS_A_INT_CTXT_RAM_MASK, - GLBL_ERR_STAT_ERR_RAM_DBE_MASK, - &eqdma_hw_ram_dbe_err_process - }, - { - EQDMA_DBE_ERR_DESC_REQ_FIFO_RAM, - "C2H ST descriptor request RAM double bit ECC error", - EQDMA_RAM_DBE_MSK_A_ADDR, - EQDMA_RAM_DBE_STS_A_ADDR, - RAM_DBE_STS_A_DESC_REQ_FIFO_RAM_MASK, - GLBL_ERR_STAT_ERR_RAM_DBE_MASK, - &eqdma_hw_ram_dbe_err_process - }, - { - EQDMA_DBE_ERR_PFCH_CTXT_RAM, - "C2H ST prefetch RAM double bit ECC error", - EQDMA_RAM_DBE_MSK_A_ADDR, - EQDMA_RAM_DBE_STS_A_ADDR, - RAM_DBE_STS_A_PFCH_CTXT_RAM_MASK, - GLBL_ERR_STAT_ERR_RAM_DBE_MASK, - &eqdma_hw_ram_dbe_err_process - }, - { - EQDMA_DBE_ERR_WRB_CTXT_RAM, - "C2H ST completion context RAM double bit ECC error", - EQDMA_RAM_DBE_MSK_A_ADDR, - EQDMA_RAM_DBE_STS_A_ADDR, - RAM_DBE_STS_A_WRB_CTXT_RAM_MASK, - GLBL_ERR_STAT_ERR_RAM_DBE_MASK, - &eqdma_hw_ram_dbe_err_process - }, - { - EQDMA_DBE_ERR_PFCH_LL_RAM, - "C2H ST prefetch list RAM double bit ECC error", - EQDMA_RAM_DBE_MSK_A_ADDR, - EQDMA_RAM_DBE_STS_A_ADDR, - RAM_DBE_STS_A_PFCH_LL_RAM_MASK, - GLBL_ERR_STAT_ERR_RAM_DBE_MASK, - &eqdma_hw_ram_dbe_err_process - }, - { - EQDMA_DBE_ERR_PEND_FIFO_RAM, - "Pend FIFO RAM double bit ECC error", - EQDMA_RAM_DBE_MSK_A_ADDR, - EQDMA_RAM_DBE_STS_A_ADDR, - RAM_DBE_STS_A_PEND_FIFO_RAM_MASK, - GLBL_ERR_STAT_ERR_RAM_DBE_MASK, - &eqdma_hw_ram_dbe_err_process - }, - { - EQDMA_DBE_ERR_RC_RRQ_ODD_RAM, - "RC RRQ Odd RAM double bit ECC error.", - EQDMA_RAM_DBE_MSK_A_ADDR, - EQDMA_RAM_DBE_STS_A_ADDR, - RAM_DBE_STS_A_RC_RRQ_ODD_RAM_MASK, - GLBL_ERR_STAT_ERR_RAM_DBE_MASK, - &eqdma_hw_ram_dbe_err_process - }, - { - EQDMA_DBE_ERR_ALL, - "All DBE errors", - EQDMA_RAM_DBE_MSK_A_ADDR, - EQDMA_RAM_DBE_STS_A_ADDR, - EQDMA_DBE_ERR_ALL_MASK, - GLBL_ERR_STAT_ERR_RAM_DBE_MASK, - &eqdma_hw_ram_dbe_err_process - } -}; - -static int32_t all_eqdma_hw_errs[EQDMA_TOTAL_LEAF_ERROR_AGGREGATORS] = { - - EQDMA_DSC_ERR_ALL, - EQDMA_TRQ_ERR_ALL, - EQDMA_ST_C2H_ERR_ALL, - EQDMA_ST_FATAL_ERR_ALL, - EQDMA_ST_H2C_ERR_ALL, - EQDMA_SBE_1_ERR_ALL, - EQDMA_SBE_ERR_ALL, - EQDMA_DBE_1_ERR_ALL, - EQDMA_DBE_ERR_ALL -}; - -static struct qctx_entry eqdma_sw_ctxt_entries[] = { - {"PIDX", 0}, - {"IRQ Arm", 0}, - {"Function Id", 0}, - {"Queue Enable", 0}, - {"Fetch Credit Enable", 0}, - {"Write back/Intr Check", 0}, - {"Write back/Intr Interval", 0}, - {"Address Translation", 0}, - {"Fetch Max", 0}, - {"Ring Size", 0}, - {"Descriptor Size", 0}, - {"Bypass Enable", 0}, - {"MM Channel", 0}, - {"Writeback Enable", 0}, - {"Interrupt Enable", 0}, - {"Port Id", 0}, - {"Interrupt No Last", 0}, - {"Error", 0}, - {"Writeback Error Sent", 0}, - {"IRQ Request", 0}, - {"Marker Disable", 0}, - {"Is Memory Mapped", 0}, - {"Descriptor Ring Base Addr (Low)", 0}, - {"Descriptor Ring Base Addr (High)", 0}, - {"Interrupt Vector/Ring Index", 0}, - {"Interrupt Aggregation", 0}, - {"Disable Interrupt with VF", 0}, - {"Pack descriptor output interface", 0}, - {"Irq Bypass", 0}, -}; - -static struct qctx_entry eqdma_hw_ctxt_entries[] = { - {"CIDX", 0}, - {"Credits Consumed", 0}, - {"Descriptors Pending", 0}, - {"Queue Invalid No Desc Pending", 0}, - {"Eviction Pending", 0}, - {"Fetch Pending", 0}, -}; - -static struct qctx_entry eqdma_credit_ctxt_entries[] = { - {"Credit", 0}, -}; - -static struct qctx_entry eqdma_cmpt_ctxt_entries[] = { - {"Enable Status Desc Update", 0}, - {"Enable Interrupt", 0}, - {"Trigger Mode", 0}, - {"Function Id", 0}, - {"Counter Index", 0}, - {"Timer Index", 0}, - {"Interrupt State", 0}, - {"Color", 0}, - {"Ring Size", 0}, - {"Base Addr High (L)[37:6]", 0}, - {"Base Addr High(H)[63:38]", 0}, - {"Descriptor Size", 0}, - {"PIDX", 0}, - {"CIDX", 0}, - {"Valid", 0}, - {"Error", 0}, - {"Trigger Pending", 0}, - {"Timer Running", 0}, - {"Full Update", 0}, - {"Over Flow Check Disable", 0}, - {"Address Translation", 0}, - {"Interrupt Vector/Ring Index", 0}, - {"Interrupt Aggregation", 0}, - {"Disable Insterrupt with VF", 0}, - {"c2h Direction", 0}, - {"Base Addr Low[5:2]", 0}, - {"Shared Completion Queue", 0}, -}; - -static struct qctx_entry eqdma_c2h_pftch_ctxt_entries[] = { - {"Bypass", 0}, - {"Buffer Size Index", 0}, - {"Port Id", 0}, - {"Variable Descriptor", 0}, - {"Number of descriptors prefetched", 0}, - {"Error", 0}, - {"Prefetch Enable", 0}, - {"In Prefetch", 0}, - {"Software Credit", 0}, - {"Valid", 0}, -}; - -static struct qctx_entry eqdma_ind_intr_ctxt_entries[] = { - {"valid", 0}, - {"vec", 0}, - {"int_st", 0}, - {"color", 0}, - {"baddr_4k (Low)", 0}, - {"baddr_4k (High)", 0}, - {"page_size", 0}, - {"pidx", 0}, - {"at", 0}, - {"Function Id", 0}, -}; - -static int eqdma_indirect_reg_invalidate(void *dev_hndl, - enum ind_ctxt_cmd_sel sel, uint16_t hw_qid); -static int eqdma_indirect_reg_clear(void *dev_hndl, - enum ind_ctxt_cmd_sel sel, uint16_t hw_qid); -static int eqdma_indirect_reg_read(void *dev_hndl, enum ind_ctxt_cmd_sel sel, - uint16_t hw_qid, uint32_t cnt, uint32_t *data); -static int eqdma_indirect_reg_write(void *dev_hndl, enum ind_ctxt_cmd_sel sel, - uint16_t hw_qid, uint32_t *data, uint16_t cnt); - -uint32_t eqdma_get_config_num_regs(void) -{ - return eqdma_config_num_regs_get(); -} - -struct xreg_info *eqdma_get_config_regs(void) -{ - return eqdma_config_regs_get(); -} - -uint32_t eqdma_reg_dump_buf_len(void) -{ - uint32_t length = (eqdma_config_num_regs_get() + 1) - * REG_DUMP_SIZE_PER_LINE; - return length; -} - -int eqdma_context_buf_len(uint8_t st, - enum qdma_dev_q_type q_type, uint32_t *buflen) -{ - int len = 0; - - if (q_type == QDMA_DEV_Q_TYPE_CMPT) { - len += (((sizeof(eqdma_cmpt_ctxt_entries) / - sizeof(eqdma_cmpt_ctxt_entries[0])) + 1) * - REG_DUMP_SIZE_PER_LINE); - } else { - len += (((sizeof(eqdma_sw_ctxt_entries) / - sizeof(eqdma_sw_ctxt_entries[0])) + 1) * - REG_DUMP_SIZE_PER_LINE); - - len += (((sizeof(eqdma_hw_ctxt_entries) / - sizeof(eqdma_hw_ctxt_entries[0])) + 1) * - REG_DUMP_SIZE_PER_LINE); - - len += (((sizeof(eqdma_credit_ctxt_entries) / - sizeof(eqdma_credit_ctxt_entries[0])) + 1) * - REG_DUMP_SIZE_PER_LINE); - - if (st && (q_type == QDMA_DEV_Q_TYPE_C2H)) { - len += (((sizeof(eqdma_cmpt_ctxt_entries) / - sizeof(eqdma_cmpt_ctxt_entries[0])) + 1) * - REG_DUMP_SIZE_PER_LINE); - - len += (((sizeof(eqdma_c2h_pftch_ctxt_entries) / - sizeof(eqdma_c2h_pftch_ctxt_entries[0])) + 1) * - REG_DUMP_SIZE_PER_LINE); - } - } - - *buflen = len; - return 0; -} - -static uint32_t eqdma_intr_context_buf_len(void) -{ - uint32_t len = 0; - - len += (((sizeof(eqdma_ind_intr_ctxt_entries) / - sizeof(eqdma_ind_intr_ctxt_entries[0])) + 1) * - REG_DUMP_SIZE_PER_LINE); - return len; -} - -/* - * eqdma_indirect_reg_invalidate() - helper function to invalidate indirect - * context registers. - * - * return -QDMA_ERR_HWACC_BUSY_TIMEOUT if register - * value didn't match, QDMA_SUCCESS other wise - */ -static int eqdma_indirect_reg_invalidate(void *dev_hndl, - enum ind_ctxt_cmd_sel sel, uint16_t hw_qid) -{ - union qdma_ind_ctxt_cmd cmd; - - qdma_reg_access_lock(dev_hndl); - - /* set command register */ - cmd.word = 0; - cmd.bits.qid = hw_qid; - cmd.bits.op = QDMA_CTXT_CMD_INV; - cmd.bits.sel = sel; - qdma_reg_write(dev_hndl, EQDMA_IND_CTXT_CMD_ADDR, cmd.word); - - /* check if the operation went through well */ - if (hw_monitor_reg(dev_hndl, EQDMA_IND_CTXT_CMD_ADDR, - IND_CTXT_CMD_BUSY_MASK, 0, - QDMA_REG_POLL_DFLT_INTERVAL_US, - QDMA_REG_POLL_DFLT_TIMEOUT_US)) { - qdma_reg_access_release(dev_hndl); - qdma_log_error("%s: hw_monitor_reg failed with err:%d\n", - __func__, - -QDMA_ERR_HWACC_BUSY_TIMEOUT); - return -QDMA_ERR_HWACC_BUSY_TIMEOUT; - } - - qdma_reg_access_release(dev_hndl); - - return QDMA_SUCCESS; -} - -/* - * eqdma_indirect_reg_clear() - helper function to clear indirect - * context registers. - * - * return -QDMA_ERR_HWACC_BUSY_TIMEOUT if register - * value didn't match, QDMA_SUCCESS other wise - */ -static int eqdma_indirect_reg_clear(void *dev_hndl, - enum ind_ctxt_cmd_sel sel, uint16_t hw_qid) -{ - union qdma_ind_ctxt_cmd cmd; - - qdma_reg_access_lock(dev_hndl); - - /* set command register */ - cmd.word = 0; - cmd.bits.qid = hw_qid; - cmd.bits.op = QDMA_CTXT_CMD_CLR; - cmd.bits.sel = sel; - qdma_reg_write(dev_hndl, EQDMA_IND_CTXT_CMD_ADDR, cmd.word); - - /* check if the operation went through well */ - if (hw_monitor_reg(dev_hndl, EQDMA_IND_CTXT_CMD_ADDR, - IND_CTXT_CMD_BUSY_MASK, 0, - QDMA_REG_POLL_DFLT_INTERVAL_US, - QDMA_REG_POLL_DFLT_TIMEOUT_US)) { - qdma_reg_access_release(dev_hndl); - qdma_log_error("%s: hw_monitor_reg failed with err:%d\n", - __func__, - -QDMA_ERR_HWACC_BUSY_TIMEOUT); - return -QDMA_ERR_HWACC_BUSY_TIMEOUT; - } - - qdma_reg_access_release(dev_hndl); - - return QDMA_SUCCESS; -} - -/* - * eqdma_indirect_reg_read() - helper function to read indirect - * context registers. - * - * return -QDMA_ERR_HWACC_BUSY_TIMEOUT if register - * value didn't match, QDMA_SUCCESS other wise - */ -static int eqdma_indirect_reg_read(void *dev_hndl, enum ind_ctxt_cmd_sel sel, - uint16_t hw_qid, uint32_t cnt, uint32_t *data) -{ - uint32_t index = 0, reg_addr = EQDMA_IND_CTXT_DATA_ADDR; - union qdma_ind_ctxt_cmd cmd; - - qdma_reg_access_lock(dev_hndl); - - /* set command register */ - cmd.word = 0; - cmd.bits.qid = hw_qid; - cmd.bits.op = QDMA_CTXT_CMD_RD; - cmd.bits.sel = sel; - - qdma_reg_write(dev_hndl, EQDMA_IND_CTXT_CMD_ADDR, cmd.word); - - /* check if the operation went through well */ - if (hw_monitor_reg(dev_hndl, EQDMA_IND_CTXT_CMD_ADDR, - IND_CTXT_CMD_BUSY_MASK, 0, - QDMA_REG_POLL_DFLT_INTERVAL_US, - QDMA_REG_POLL_DFLT_TIMEOUT_US)) { - qdma_reg_access_release(dev_hndl); - qdma_log_error("%s: hw_monitor_reg failed with err:%d\n", - __func__, - -QDMA_ERR_HWACC_BUSY_TIMEOUT); - return -QDMA_ERR_HWACC_BUSY_TIMEOUT; - } - - for (index = 0; index < cnt; index++, reg_addr += sizeof(uint32_t)) - data[index] = qdma_reg_read(dev_hndl, reg_addr); - - qdma_reg_access_release(dev_hndl); - - return QDMA_SUCCESS; -} - -/* - * eqdma_indirect_reg_write() - helper function to write indirect - * context registers. - * - * return -QDMA_ERR_HWACC_BUSY_TIMEOUT if register - * value didn't match, QDMA_SUCCESS other wise - */ -static int eqdma_indirect_reg_write(void *dev_hndl, enum ind_ctxt_cmd_sel sel, - uint16_t hw_qid, uint32_t *data, uint16_t cnt) -{ - uint32_t index, reg_addr; - struct qdma_indirect_ctxt_regs regs; - uint32_t *wr_data = (uint32_t *)®s; - - qdma_reg_access_lock(dev_hndl); - - /* write the context data */ - for (index = 0; index < QDMA_IND_CTXT_DATA_NUM_REGS; index++) { - if (index < cnt) - regs.qdma_ind_ctxt_data[index] = data[index]; - else - regs.qdma_ind_ctxt_data[index] = 0; - regs.qdma_ind_ctxt_mask[index] = 0xFFFFFFFF; - } - - regs.cmd.word = 0; - regs.cmd.bits.qid = hw_qid; - regs.cmd.bits.op = QDMA_CTXT_CMD_WR; - regs.cmd.bits.sel = sel; - reg_addr = EQDMA_IND_CTXT_DATA_ADDR; - - for (index = 0; index < ((2 * QDMA_IND_CTXT_DATA_NUM_REGS) + 1); - index++, reg_addr += sizeof(uint32_t)) - qdma_reg_write(dev_hndl, reg_addr, wr_data[index]); - - /* check if the operation went through well */ - if (hw_monitor_reg(dev_hndl, EQDMA_IND_CTXT_CMD_ADDR, - IND_CTXT_CMD_BUSY_MASK, 0, - QDMA_REG_POLL_DFLT_INTERVAL_US, - QDMA_REG_POLL_DFLT_TIMEOUT_US)) { - qdma_reg_access_release(dev_hndl); - qdma_log_error("%s: hw_monitor_reg failed with err:%d\n", - __func__, - -QDMA_ERR_HWACC_BUSY_TIMEOUT); - return -QDMA_ERR_HWACC_BUSY_TIMEOUT; - } - - qdma_reg_access_release(dev_hndl); - - return QDMA_SUCCESS; -} - -/* - * eqdma_fill_sw_ctxt() - Helper function to fill sw context into structure - * - */ -static void eqdma_fill_sw_ctxt(struct qdma_descq_sw_ctxt *sw_ctxt) -{ - int i = 0; - - eqdma_sw_ctxt_entries[i++].value = sw_ctxt->pidx; - eqdma_sw_ctxt_entries[i++].value = sw_ctxt->irq_arm; - eqdma_sw_ctxt_entries[i++].value = sw_ctxt->fnc_id; - eqdma_sw_ctxt_entries[i++].value = sw_ctxt->qen; - eqdma_sw_ctxt_entries[i++].value = sw_ctxt->frcd_en; - eqdma_sw_ctxt_entries[i++].value = sw_ctxt->wbi_chk; - eqdma_sw_ctxt_entries[i++].value = sw_ctxt->wbi_intvl_en; - eqdma_sw_ctxt_entries[i++].value = sw_ctxt->at; - eqdma_sw_ctxt_entries[i++].value = sw_ctxt->fetch_max; - eqdma_sw_ctxt_entries[i++].value = sw_ctxt->rngsz_idx; - eqdma_sw_ctxt_entries[i++].value = sw_ctxt->desc_sz; - eqdma_sw_ctxt_entries[i++].value = sw_ctxt->bypass; - eqdma_sw_ctxt_entries[i++].value = sw_ctxt->mm_chn; - eqdma_sw_ctxt_entries[i++].value = sw_ctxt->wbk_en; - eqdma_sw_ctxt_entries[i++].value = sw_ctxt->irq_en; - eqdma_sw_ctxt_entries[i++].value = sw_ctxt->port_id; - eqdma_sw_ctxt_entries[i++].value = sw_ctxt->irq_no_last; - eqdma_sw_ctxt_entries[i++].value = sw_ctxt->err; - eqdma_sw_ctxt_entries[i++].value = sw_ctxt->err_wb_sent; - eqdma_sw_ctxt_entries[i++].value = sw_ctxt->irq_req; - eqdma_sw_ctxt_entries[i++].value = sw_ctxt->mrkr_dis; - eqdma_sw_ctxt_entries[i++].value = sw_ctxt->is_mm; - eqdma_sw_ctxt_entries[i++].value = sw_ctxt->ring_bs_addr & 0xFFFFFFFF; - eqdma_sw_ctxt_entries[i++].value = - (sw_ctxt->ring_bs_addr >> 32) & 0xFFFFFFFF; - eqdma_sw_ctxt_entries[i++].value = sw_ctxt->vec; - eqdma_sw_ctxt_entries[i++].value = sw_ctxt->intr_aggr; - eqdma_sw_ctxt_entries[i++].value = sw_ctxt->dis_intr_on_vf; - eqdma_sw_ctxt_entries[i++].value = sw_ctxt->pack_byp_out; - eqdma_sw_ctxt_entries[i++].value = sw_ctxt->irq_byp; - -} - -/* - * eqdma_fill_cmpt_ctxt() - Helper function to fill completion context - * into structure - * - */ -static void eqdma_fill_cmpt_ctxt(struct qdma_descq_cmpt_ctxt *cmpt_ctxt) -{ - int i = 0; - - eqdma_cmpt_ctxt_entries[i++].value = cmpt_ctxt->en_stat_desc; - eqdma_cmpt_ctxt_entries[i++].value = cmpt_ctxt->en_int; - eqdma_cmpt_ctxt_entries[i++].value = cmpt_ctxt->trig_mode; - eqdma_cmpt_ctxt_entries[i++].value = cmpt_ctxt->fnc_id; - eqdma_cmpt_ctxt_entries[i++].value = cmpt_ctxt->counter_idx; - eqdma_cmpt_ctxt_entries[i++].value = cmpt_ctxt->timer_idx; - eqdma_cmpt_ctxt_entries[i++].value = cmpt_ctxt->in_st; - eqdma_cmpt_ctxt_entries[i++].value = cmpt_ctxt->color; - eqdma_cmpt_ctxt_entries[i++].value = cmpt_ctxt->ringsz_idx; - eqdma_cmpt_ctxt_entries[i++].value = (uint32_t)FIELD_GET( - EQDMA_COMPL_CTXT_BADDR_HIGH_L_MASK, - cmpt_ctxt->bs_addr); - eqdma_cmpt_ctxt_entries[i++].value = (uint32_t)FIELD_GET( - EQDMA_COMPL_CTXT_BADDR_HIGH_H_MASK, - cmpt_ctxt->bs_addr); - eqdma_cmpt_ctxt_entries[i++].value = cmpt_ctxt->desc_sz; - eqdma_cmpt_ctxt_entries[i++].value = cmpt_ctxt->pidx; - eqdma_cmpt_ctxt_entries[i++].value = cmpt_ctxt->cidx; - eqdma_cmpt_ctxt_entries[i++].value = cmpt_ctxt->valid; - eqdma_cmpt_ctxt_entries[i++].value = cmpt_ctxt->err; - eqdma_cmpt_ctxt_entries[i++].value = cmpt_ctxt->user_trig_pend; - eqdma_cmpt_ctxt_entries[i++].value = cmpt_ctxt->timer_running; - eqdma_cmpt_ctxt_entries[i++].value = cmpt_ctxt->full_upd; - eqdma_cmpt_ctxt_entries[i++].value = cmpt_ctxt->ovf_chk_dis; - eqdma_cmpt_ctxt_entries[i++].value = cmpt_ctxt->at; - eqdma_cmpt_ctxt_entries[i++].value = cmpt_ctxt->vec; - eqdma_cmpt_ctxt_entries[i++].value = cmpt_ctxt->int_aggr; - eqdma_cmpt_ctxt_entries[i++].value = cmpt_ctxt->dis_intr_on_vf; - eqdma_cmpt_ctxt_entries[i++].value = cmpt_ctxt->dir_c2h; - eqdma_cmpt_ctxt_entries[i++].value = (uint32_t)FIELD_GET( - EQDMA_COMPL_CTXT_BADDR_LOW_MASK, - cmpt_ctxt->bs_addr); - eqdma_cmpt_ctxt_entries[i++].value = cmpt_ctxt->sh_cmpt; -} - -/* - * eqdma_fill_hw_ctxt() - Helper function to fill HW context into structure - * - */ -static void eqdma_fill_hw_ctxt(struct qdma_descq_hw_ctxt *hw_ctxt) -{ - int i = 0; - - eqdma_hw_ctxt_entries[i++].value = hw_ctxt->cidx; - eqdma_hw_ctxt_entries[i++].value = hw_ctxt->crd_use; - eqdma_hw_ctxt_entries[i++].value = hw_ctxt->dsc_pend; - eqdma_hw_ctxt_entries[i++].value = hw_ctxt->idl_stp_b; - eqdma_hw_ctxt_entries[i++].value = hw_ctxt->evt_pnd; - eqdma_hw_ctxt_entries[i++].value = hw_ctxt->fetch_pnd; -} - -/* - * eqdma_fill_credit_ctxt() - Helper function to fill Credit context - * into structure - * - */ -static void eqdma_fill_credit_ctxt(struct qdma_descq_credit_ctxt *cr_ctxt) -{ - eqdma_credit_ctxt_entries[0].value = cr_ctxt->credit; -} - -/* - * eqdma_fill_pfetch_ctxt() - Helper function to fill Prefetch context - * into structure - * - */ -static void eqdma_fill_pfetch_ctxt(struct qdma_descq_prefetch_ctxt - *pfetch_ctxt) -{ - int i = 0; - - eqdma_c2h_pftch_ctxt_entries[i++].value = pfetch_ctxt->bypass; - eqdma_c2h_pftch_ctxt_entries[i++].value = pfetch_ctxt->bufsz_idx; - eqdma_c2h_pftch_ctxt_entries[i++].value = pfetch_ctxt->port_id; - eqdma_c2h_pftch_ctxt_entries[i++].value = pfetch_ctxt->var_desc; - eqdma_c2h_pftch_ctxt_entries[i++].value = pfetch_ctxt->num_pftch; - eqdma_c2h_pftch_ctxt_entries[i++].value = pfetch_ctxt->err; - eqdma_c2h_pftch_ctxt_entries[i++].value = pfetch_ctxt->pfch_en; - eqdma_c2h_pftch_ctxt_entries[i++].value = pfetch_ctxt->pfch; - eqdma_c2h_pftch_ctxt_entries[i++].value = pfetch_ctxt->sw_crdt; - eqdma_c2h_pftch_ctxt_entries[i++].value = pfetch_ctxt->valid; -} - -/* - * eqdma_fill_intr_ctxt() - Helper function to fill interrupt context - * into structure - * - */ -static void eqdma_fill_intr_ctxt(struct qdma_indirect_intr_ctxt *intr_ctxt) -{ - int i = 0; - - eqdma_ind_intr_ctxt_entries[i++].value = intr_ctxt->valid; - eqdma_ind_intr_ctxt_entries[i++].value = intr_ctxt->vec; - eqdma_ind_intr_ctxt_entries[i++].value = intr_ctxt->int_st; - eqdma_ind_intr_ctxt_entries[i++].value = intr_ctxt->color; - eqdma_ind_intr_ctxt_entries[i++].value = - intr_ctxt->baddr_4k & 0xFFFFFFFF; - eqdma_ind_intr_ctxt_entries[i++].value = - (intr_ctxt->baddr_4k >> 32) & 0xFFFFFFFF; - eqdma_ind_intr_ctxt_entries[i++].value = intr_ctxt->page_size; - eqdma_ind_intr_ctxt_entries[i++].value = intr_ctxt->pidx; - eqdma_ind_intr_ctxt_entries[i++].value = intr_ctxt->at; - eqdma_ind_intr_ctxt_entries[i++].value = intr_ctxt->func_id; -} - -/*****************************************************************************/ -/** - * eqdma_set_default_global_csr() - function to set the global CSR register to - * default values. The value can be modified later by using the set/get csr - * functions - * - * @dev_hndl: device handle - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -int eqdma_set_default_global_csr(void *dev_hndl) -{ - /* Default values */ - uint32_t cfg_val = 0, reg_val = 0; - uint32_t rng_sz[QDMA_NUM_RING_SIZES] = {2049, 65, 129, 193, 257, 385, - 513, 769, 1025, 1537, 3073, 4097, 6145, 8193, 12289, 16385}; - uint32_t tmr_cnt[QDMA_NUM_C2H_TIMERS] = {1, 2, 4, 5, 8, 10, 15, 20, 25, - 30, 50, 75, 100, 125, 150, 200}; - uint32_t cnt_th[QDMA_NUM_C2H_COUNTERS] = {2, 4, 8, 16, 24, 32, 48, 64, - 80, 96, 112, 128, 144, 160, 176, 192}; - uint32_t buf_sz[QDMA_NUM_C2H_BUFFER_SIZES] = {4096, 256, 512, 1024, - 2048, 3968, 4096, 4096, 4096, 4096, 4096, 4096, 4096, 8192, - 9018, 16384}; - struct qdma_dev_attributes dev_cap; - - if (!dev_hndl) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", __func__, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - eqdma_get_device_attributes(dev_hndl, &dev_cap); - - /* Configuring CSR registers */ - /* Global ring sizes */ - qdma_write_csr_values(dev_hndl, EQDMA_GLBL_RNG_SZ_1_ADDR, 0, - QDMA_NUM_RING_SIZES, rng_sz); - - if (dev_cap.st_en || dev_cap.mm_cmpt_en) { - /* Counter thresholds */ - qdma_write_csr_values(dev_hndl, EQDMA_C2H_CNT_TH_ADDR, 0, - QDMA_NUM_C2H_COUNTERS, cnt_th); - - /* Timer Counters */ - qdma_write_csr_values(dev_hndl, EQDMA_C2H_TIMER_CNT_ADDR, 0, - QDMA_NUM_C2H_TIMERS, tmr_cnt); - - - /* Writeback Interval */ - reg_val = - FIELD_SET(GLBL_DSC_CFG_MAXFETCH_MASK, - DEFAULT_MAX_DSC_FETCH) | - FIELD_SET(GLBL_DSC_CFG_WB_ACC_INT_MASK, - DEFAULT_WRB_INT); - qdma_reg_write(dev_hndl, EQDMA_GLBL_DSC_CFG_ADDR, reg_val); - } - - if (dev_cap.st_en) { - /* Buffer Sizes */ - qdma_write_csr_values(dev_hndl, EQDMA_C2H_BUF_SZ_ADDR, 0, - QDMA_NUM_C2H_BUFFER_SIZES, buf_sz); - - /* Prefetch Configuration */ - - cfg_val = qdma_reg_read(dev_hndl, - EQDMA_C2H_PFCH_CACHE_DEPTH_ADDR); - - reg_val = - FIELD_SET(C2H_PFCH_CFG_FL_TH_MASK, - DEFAULT_PFCH_STOP_THRESH); - qdma_reg_write(dev_hndl, EQDMA_C2H_PFCH_CFG_ADDR, reg_val); - - reg_val = FIELD_SET(C2H_PFCH_CFG_1_QCNT_MASK, (cfg_val >> 1)) | - FIELD_SET(C2H_PFCH_CFG_1_EVT_QCNT_TH_MASK, - ((cfg_val >> 1) - 2)); - qdma_reg_write(dev_hndl, EQDMA_C2H_PFCH_CFG_1_ADDR, reg_val); - - reg_val = FIELD_SET(C2H_PFCH_CFG_2_NUM_MASK, - DEFAULT_PFCH_NUM_ENTRIES_PER_Q); - - qdma_reg_write(dev_hndl, EQDMA_C2H_PFCH_CFG_2_ADDR, reg_val); - - /* C2H interrupt timer tick */ - qdma_reg_write(dev_hndl, EQDMA_C2H_INT_TIMER_TICK_ADDR, - DEFAULT_C2H_INTR_TIMER_TICK); - - /* C2h Completion Coalesce Configuration */ - cfg_val = qdma_reg_read(dev_hndl, - EQDMA_C2H_WRB_COAL_BUF_DEPTH_ADDR); - reg_val = - FIELD_SET(C2H_WRB_COAL_CFG_TICK_CNT_MASK, - DEFAULT_CMPT_COAL_TIMER_CNT) | - FIELD_SET(C2H_WRB_COAL_CFG_TICK_VAL_MASK, - DEFAULT_CMPT_COAL_TIMER_TICK) | - FIELD_SET(C2H_WRB_COAL_CFG_MAX_BUF_SZ_MASK, cfg_val); - qdma_reg_write(dev_hndl, EQDMA_C2H_WRB_COAL_CFG_ADDR, reg_val); - - /* H2C throttle Configuration*/ - - reg_val = - FIELD_SET(H2C_REQ_THROT_PCIE_DATA_THRESH_MASK, - EQDMA_H2C_THROT_DATA_THRESH) | - FIELD_SET(H2C_REQ_THROT_PCIE_EN_DATA_MASK, - EQDMA_THROT_EN_DATA) | - FIELD_SET(H2C_REQ_THROT_PCIE_MASK, - EQDMA_H2C_THROT_REQ_THRESH) | - FIELD_SET(H2C_REQ_THROT_PCIE_EN_REQ_MASK, - EQDMA_THROT_EN_REQ); - qdma_reg_write(dev_hndl, EQDMA_H2C_REQ_THROT_PCIE_ADDR, - reg_val); - } - - return QDMA_SUCCESS; -} - -/* - * dump_eqdma_context() - Helper function to dump queue context into string - * - * return len - length of the string copied into buffer - */ -static int dump_eqdma_context(struct qdma_descq_context *queue_context, - uint8_t st, enum qdma_dev_q_type q_type, - char *buf, int buf_sz) -{ - int i = 0; - int n; - int len = 0; - int rv; - char banner[DEBGFS_LINE_SZ]; - - if (queue_context == NULL) { - qdma_log_error("%s: queue_context is NULL, err:%d\n", - __func__, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - if (q_type == QDMA_DEV_Q_TYPE_CMPT) { - eqdma_fill_cmpt_ctxt(&queue_context->cmpt_ctxt); - } else if (q_type == QDMA_DEV_Q_TYPE_H2C) { - eqdma_fill_sw_ctxt(&queue_context->sw_ctxt); - eqdma_fill_hw_ctxt(&queue_context->hw_ctxt); - eqdma_fill_credit_ctxt(&queue_context->cr_ctxt); - } else if (q_type == QDMA_DEV_Q_TYPE_C2H) { - eqdma_fill_sw_ctxt(&queue_context->sw_ctxt); - eqdma_fill_hw_ctxt(&queue_context->hw_ctxt); - eqdma_fill_credit_ctxt(&queue_context->cr_ctxt); - if (st) { - eqdma_fill_pfetch_ctxt(&queue_context->pfetch_ctxt); - eqdma_fill_cmpt_ctxt(&queue_context->cmpt_ctxt); - } - } - - if (q_type != QDMA_DEV_Q_TYPE_CMPT) { - for (i = 0; i < DEBGFS_LINE_SZ - 5; i++) { - rv = QDMA_SNPRINTF_S(banner + i, - (DEBGFS_LINE_SZ - i), - sizeof("-"), "-"); - if ((rv < 0) || (rv > (int)sizeof("-"))) { - qdma_log_error( - "%d:%s QDMA_SNPRINTF_S() failed, err:%d\n", - __LINE__, __func__, - rv); - goto INSUF_BUF_EXIT; - } - } - - /* SW context dump */ - n = sizeof(eqdma_sw_ctxt_entries) / - sizeof((eqdma_sw_ctxt_entries)[0]); - for (i = 0; i < n; i++) { - if ((len >= buf_sz) || - ((len + DEBGFS_LINE_SZ) >= buf_sz)) - goto INSUF_BUF_EXIT; - - if (i == 0) { - if ((len + (3 * DEBGFS_LINE_SZ)) >= buf_sz) - goto INSUF_BUF_EXIT; - rv = QDMA_SNPRINTF_S(buf + len, (buf_sz - len), - DEBGFS_LINE_SZ, "\n%s", banner); - if ((rv < 0) || (rv > DEBGFS_LINE_SZ)) { - qdma_log_error( - "%d:%s QDMA_SNPRINTF_S() failed, err:%d\n", - __LINE__, __func__, - rv); - goto INSUF_BUF_EXIT; - } - len += rv; - - rv = QDMA_SNPRINTF_S(buf + len, (buf_sz - len), - DEBGFS_LINE_SZ, "\n%40s", "SW Context"); - if ((rv < 0) || (rv > DEBGFS_LINE_SZ)) { - qdma_log_error( - "%d:%s QDMA_SNPRINTF_S() failed, err:%d\n", - __LINE__, __func__, - rv); - goto INSUF_BUF_EXIT; - } - len += rv; - - rv = QDMA_SNPRINTF_S(buf + len, (buf_sz - len), - DEBGFS_LINE_SZ, "\n%s\n", banner); - if ((rv < 0) || (rv > DEBGFS_LINE_SZ)) { - qdma_log_error( - "%d:%s QDMA_SNPRINTF_S() failed, err:%d\n", - __LINE__, __func__, - rv); - goto INSUF_BUF_EXIT; - } - len += rv; - } - - rv = QDMA_SNPRINTF_S(buf + len, (buf_sz - len), - DEBGFS_LINE_SZ, - "%-47s %#-10x %u\n", - eqdma_sw_ctxt_entries[i].name, - eqdma_sw_ctxt_entries[i].value, - eqdma_sw_ctxt_entries[i].value); - if ((rv < 0) || (rv > DEBGFS_LINE_SZ)) { - qdma_log_error( - "%d:%s QDMA_SNPRINTF_S() failed, err:%d\n", - __LINE__, __func__, - rv); - goto INSUF_BUF_EXIT; - } - len += rv; - } - - /* HW context dump */ - n = sizeof(eqdma_hw_ctxt_entries) / - sizeof((eqdma_hw_ctxt_entries)[0]); - for (i = 0; i < n; i++) { - if ((len >= buf_sz) || - ((len + DEBGFS_LINE_SZ) >= buf_sz)) - goto INSUF_BUF_EXIT; - - if (i == 0) { - if ((len + (3 * DEBGFS_LINE_SZ)) >= buf_sz) - goto INSUF_BUF_EXIT; - - rv = QDMA_SNPRINTF_S(buf + len, (buf_sz - len), - DEBGFS_LINE_SZ, "\n%s", banner); - if ((rv < 0) || (rv > DEBGFS_LINE_SZ)) { - qdma_log_error( - "%d:%s QDMA_SNPRINTF_S() failed, err:%d\n", - __LINE__, __func__, - rv); - goto INSUF_BUF_EXIT; - } - len += rv; - - rv = QDMA_SNPRINTF_S(buf + len, (buf_sz - len), - DEBGFS_LINE_SZ, "\n%40s", "HW Context"); - if ((rv < 0) || (rv > DEBGFS_LINE_SZ)) { - qdma_log_error( - "%d:%s QDMA_SNPRINTF_S() failed, err:%d\n", - __LINE__, __func__, - rv); - goto INSUF_BUF_EXIT; - } - len += rv; - - rv = QDMA_SNPRINTF_S(buf + len, (buf_sz - len), - DEBGFS_LINE_SZ, "\n%s\n", banner); - if ((rv < 0) || (rv > DEBGFS_LINE_SZ)) { - qdma_log_error( - "%d:%s QDMA_SNPRINTF_S() failed, err:%d\n", - __LINE__, __func__, - rv); - goto INSUF_BUF_EXIT; - } - len += rv; - } - - rv = QDMA_SNPRINTF_S(buf + len, (buf_sz - len), - DEBGFS_LINE_SZ, - "%-47s %#-10x %u\n", - eqdma_hw_ctxt_entries[i].name, - eqdma_hw_ctxt_entries[i].value, - eqdma_hw_ctxt_entries[i].value); - if ((rv < 0) || (rv > DEBGFS_LINE_SZ)) { - qdma_log_error( - "%d:%s QDMA_SNPRINTF_S() failed, err:%d\n", - __LINE__, __func__, - rv); - goto INSUF_BUF_EXIT; - } - len += rv; - } - - /* Credit context dump */ - n = sizeof(eqdma_credit_ctxt_entries) / - sizeof((eqdma_credit_ctxt_entries)[0]); - for (i = 0; i < n; i++) { - if ((len >= buf_sz) || - ((len + DEBGFS_LINE_SZ) >= buf_sz)) - goto INSUF_BUF_EXIT; - - if (i == 0) { - if ((len + (3 * DEBGFS_LINE_SZ)) >= buf_sz) - goto INSUF_BUF_EXIT; - - rv = QDMA_SNPRINTF_S(buf + len, (buf_sz - len), - DEBGFS_LINE_SZ, "\n%s", banner); - if ((rv < 0) || (rv > DEBGFS_LINE_SZ)) { - qdma_log_error( - "%d:%s QDMA_SNPRINTF_S() failed, err:%d\n", - __LINE__, __func__, - rv); - goto INSUF_BUF_EXIT; - } - len += rv; - - rv = QDMA_SNPRINTF_S(buf + len, (buf_sz - len), - DEBGFS_LINE_SZ, "\n%40s", - "Credit Context"); - if ((rv < 0) || (rv > DEBGFS_LINE_SZ)) { - qdma_log_error( - "%d:%s QDMA_SNPRINTF_S() failed, err:%d\n", - __LINE__, __func__, - rv); - goto INSUF_BUF_EXIT; - } - len += rv; - - rv = QDMA_SNPRINTF_S(buf + len, (buf_sz - len), - DEBGFS_LINE_SZ, "\n%s\n", banner); - if ((rv < 0) || (rv > DEBGFS_LINE_SZ)) { - qdma_log_error( - "%d:%s QDMA_SNPRINTF_S() failed, err:%d\n", - __LINE__, __func__, - rv); - goto INSUF_BUF_EXIT; - } - len += rv; - } - - rv = QDMA_SNPRINTF_S(buf + len, (buf_sz - len), - DEBGFS_LINE_SZ, - "%-47s %#-10x %u\n", - eqdma_credit_ctxt_entries[i].name, - eqdma_credit_ctxt_entries[i].value, - eqdma_credit_ctxt_entries[i].value); - if ((rv < 0) || (rv > DEBGFS_LINE_SZ)) { - qdma_log_error( - "%d:%s QDMA_SNPRINTF_S() failed, err:%d\n", - __LINE__, __func__, - rv); - goto INSUF_BUF_EXIT; - } - len += rv; - } - } - - if ((q_type == QDMA_DEV_Q_TYPE_CMPT) || - (st && q_type == QDMA_DEV_Q_TYPE_C2H)) { - /* Completion context dump */ - n = sizeof(eqdma_cmpt_ctxt_entries) / - sizeof((eqdma_cmpt_ctxt_entries)[0]); - for (i = 0; i < n; i++) { - if ((len >= buf_sz) || - ((len + DEBGFS_LINE_SZ) >= buf_sz)) - goto INSUF_BUF_EXIT; - - if (i == 0) { - if ((len + (3 * DEBGFS_LINE_SZ)) >= buf_sz) - goto INSUF_BUF_EXIT; - - rv = QDMA_SNPRINTF_S(buf + len, (buf_sz - len), - DEBGFS_LINE_SZ, "\n%s", banner); - if ((rv < 0) || (rv > DEBGFS_LINE_SZ)) { - qdma_log_error( - "%d:%s QDMA_SNPRINTF_S() failed, err:%d\n", - __LINE__, __func__, - rv); - goto INSUF_BUF_EXIT; - } - len += rv; - - rv = QDMA_SNPRINTF_S(buf + len, (buf_sz - len), - DEBGFS_LINE_SZ, "\n%40s", - "Completion Context"); - if ((rv < 0) || (rv > DEBGFS_LINE_SZ)) { - qdma_log_error( - "%d:%s QDMA_SNPRINTF_S() failed, err:%d\n", - __LINE__, __func__, - rv); - goto INSUF_BUF_EXIT; - } - len += rv; - - rv = QDMA_SNPRINTF_S(buf + len, (buf_sz - len), - DEBGFS_LINE_SZ, "\n%s\n", banner); - if ((rv < 0) || (rv > DEBGFS_LINE_SZ)) { - qdma_log_error( - "%d:%s QDMA_SNPRINTF_S() failed, err:%d\n", - __LINE__, __func__, - rv); - goto INSUF_BUF_EXIT; - } - len += rv; - } - - rv = QDMA_SNPRINTF_S(buf + len, (buf_sz - len), - DEBGFS_LINE_SZ, - "%-47s %#-10x %u\n", - eqdma_cmpt_ctxt_entries[i].name, - eqdma_cmpt_ctxt_entries[i].value, - eqdma_cmpt_ctxt_entries[i].value); - if ((rv < 0) || (rv > DEBGFS_LINE_SZ)) { - qdma_log_error( - "%d:%s QDMA_SNPRINTF_S() failed, err:%d\n", - __LINE__, __func__, - rv); - goto INSUF_BUF_EXIT; - } - len += rv; - } - } - - if (st && q_type == QDMA_DEV_Q_TYPE_C2H) { - /* Prefetch context dump */ - n = sizeof(eqdma_c2h_pftch_ctxt_entries) / - sizeof(eqdma_c2h_pftch_ctxt_entries[0]); - for (i = 0; i < n; i++) { - if ((len >= buf_sz) || - ((len + DEBGFS_LINE_SZ) >= buf_sz)) - goto INSUF_BUF_EXIT; - - if (i == 0) { - if ((len + (3 * DEBGFS_LINE_SZ)) >= buf_sz) - goto INSUF_BUF_EXIT; - - rv = QDMA_SNPRINTF_S(buf + len, (buf_sz - len), - DEBGFS_LINE_SZ, "\n%s", banner); - if ((rv < 0) || (rv > DEBGFS_LINE_SZ)) { - qdma_log_error( - "%d:%s QDMA_SNPRINTF_S() failed, err:%d\n", - __LINE__, __func__, - rv); - goto INSUF_BUF_EXIT; - } - len += rv; - - rv = QDMA_SNPRINTF_S(buf + len, (buf_sz - len), - DEBGFS_LINE_SZ, "\n%40s", - "Prefetch Context"); - if ((rv < 0) || (rv > DEBGFS_LINE_SZ)) { - qdma_log_error( - "%d:%s QDMA_SNPRINTF_S() failed, err:%d\n", - __LINE__, __func__, - rv); - goto INSUF_BUF_EXIT; - } - len += rv; - - rv = QDMA_SNPRINTF_S(buf + len, (buf_sz - len), - DEBGFS_LINE_SZ, "\n%s\n", banner); - if ((rv < 0) || (rv > DEBGFS_LINE_SZ)) { - qdma_log_error( - "%d:%s QDMA_SNPRINTF_S() failed, err:%d\n", - __LINE__, __func__, - rv); - goto INSUF_BUF_EXIT; - } - len += rv; - } - - rv = QDMA_SNPRINTF_S(buf + len, (buf_sz - len), - DEBGFS_LINE_SZ, - "%-47s %#-10x %u\n", - eqdma_c2h_pftch_ctxt_entries[i].name, - eqdma_c2h_pftch_ctxt_entries[i].value, - eqdma_c2h_pftch_ctxt_entries[i].value); - if ((rv < 0) || (rv > DEBGFS_LINE_SZ)) { - qdma_log_error( - "%d:%s QDMA_SNPRINTF_S() failed, err:%d\n", - __LINE__, __func__, - rv); - goto INSUF_BUF_EXIT; - } - len += rv; - } - } - - return len; - -INSUF_BUF_EXIT: - if (buf_sz > DEBGFS_LINE_SZ) { - rv = QDMA_SNPRINTF_S((buf + buf_sz - DEBGFS_LINE_SZ), - buf_sz, DEBGFS_LINE_SZ, - "\n\nInsufficient buffer size, partial context dump\n"); - if ((rv < 0) || (rv > DEBGFS_LINE_SZ)) { - qdma_log_error( - "%d:%s QDMA_SNPRINTF_S() failed, err:%d\n", - __LINE__, __func__, - rv); - } - } - - qdma_log_error("%s: Insufficient buffer size, err:%d\n", - __func__, -QDMA_ERR_NO_MEM); - - return -QDMA_ERR_NO_MEM; -} - -/* - * dump_eqdma_intr_context() - Helper function to dump interrupt context into - * string - * - * return len - length of the string copied into buffer - */ -static int dump_eqdma_intr_context(struct qdma_indirect_intr_ctxt *intr_ctx, - int ring_index, - char *buf, int buf_sz) -{ - int i = 0; - int n; - int len = 0; - int rv; - char banner[DEBGFS_LINE_SZ]; - - eqdma_fill_intr_ctxt(intr_ctx); - - for (i = 0; i < DEBGFS_LINE_SZ - 5; i++) { - rv = QDMA_SNPRINTF_S(banner + i, - (DEBGFS_LINE_SZ - i), - sizeof("-"), "-"); - if ((rv < 0) || (rv > (int)sizeof("-"))) { - qdma_log_error( - "%d:%s QDMA_SNPRINTF_S() failed, err:%d\n", - __LINE__, __func__, - rv); - goto INSUF_BUF_EXIT; - } - } - - /* Interrupt context dump */ - n = sizeof(eqdma_ind_intr_ctxt_entries) / - sizeof((eqdma_ind_intr_ctxt_entries)[0]); - for (i = 0; i < n; i++) { - if ((len >= buf_sz) || ((len + DEBGFS_LINE_SZ) >= buf_sz)) - goto INSUF_BUF_EXIT; - - if (i == 0) { - if ((len + (3 * DEBGFS_LINE_SZ)) >= buf_sz) - goto INSUF_BUF_EXIT; - - rv = QDMA_SNPRINTF_S(buf + len, (buf_sz - len), - DEBGFS_LINE_SZ, "\n%s", banner); - if ((rv < 0) || (rv > DEBGFS_LINE_SZ)) { - qdma_log_error( - "%d:%s QDMA_SNPRINTF_S() failed, err:%d\n", - __LINE__, __func__, - rv); - goto INSUF_BUF_EXIT; - } - len += rv; - - rv = QDMA_SNPRINTF_S(buf + len, (buf_sz - len), - DEBGFS_LINE_SZ, "\n%50s %d", - "Interrupt Context for ring#", ring_index); - if ((rv < 0) || (rv > DEBGFS_LINE_SZ)) { - qdma_log_error( - "%d:%s QDMA_SNPRINTF_S() failed, err:%d\n", - __LINE__, __func__, - rv); - goto INSUF_BUF_EXIT; - } - len += rv; - - rv = QDMA_SNPRINTF_S(buf + len, (buf_sz - len), - DEBGFS_LINE_SZ, "\n%s\n", banner); - if ((rv < 0) || (rv > DEBGFS_LINE_SZ)) { - qdma_log_error( - "%d:%s QDMA_SNPRINTF_S() failed, err:%d\n", - __LINE__, __func__, - rv); - goto INSUF_BUF_EXIT; - } - len += rv; - } - - rv = QDMA_SNPRINTF_S(buf + len, (buf_sz - len), DEBGFS_LINE_SZ, - "%-47s %#-10x %u\n", - eqdma_ind_intr_ctxt_entries[i].name, - eqdma_ind_intr_ctxt_entries[i].value, - eqdma_ind_intr_ctxt_entries[i].value); - if ((rv < 0) || (rv > DEBGFS_LINE_SZ)) { - qdma_log_error( - "%d:%s QDMA_SNPRINTF_S() failed, err:%d\n", - __LINE__, __func__, - rv); - goto INSUF_BUF_EXIT; - } - len += rv; - } - - return len; - -INSUF_BUF_EXIT: - if (buf_sz > DEBGFS_LINE_SZ) { - rv = QDMA_SNPRINTF_S((buf + buf_sz - DEBGFS_LINE_SZ), - buf_sz, DEBGFS_LINE_SZ, - "\n\nInsufficient buffer size, partial context dump\n"); - if ((rv < 0) || (rv > DEBGFS_LINE_SZ)) { - qdma_log_error( - "%d:%s QDMA_SNPRINTF_S() failed, err:%d\n", - __LINE__, __func__, - rv); - } - } - - qdma_log_error("%s: Insufficient buffer size, err:%d\n", - __func__, -QDMA_ERR_NO_MEM); - - return -QDMA_ERR_NO_MEM; -} - -/*****************************************************************************/ -/** - * eqdma_get_version() - Function to get the eqdma version - * - * @dev_hndl: device handle - * @is_vf: Whether PF or VF - * @version_info: pointer to hold the version info - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -int eqdma_get_version(void *dev_hndl, uint8_t is_vf, - struct qdma_hw_version_info *version_info) -{ - uint32_t reg_val = 0; - uint32_t reg_addr = (is_vf) ? EQDMA_OFFSET_VF_VERSION : - EQDMA_GLBL2_MISC_CAP_ADDR; - - if (!dev_hndl) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - reg_val = qdma_reg_read(dev_hndl, reg_addr); - - qdma_fetch_version_details(is_vf, reg_val, version_info); - - return QDMA_SUCCESS; -} - -/*****************************************************************************/ -/** - * eqdma_sw_context_write() - create sw context and program it - * - * @dev_hndl: device handle - * @c2h: is c2h queue - * @hw_qid: hardware qid of the queue - * @ctxt: pointer to the SW context data strucutre - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -static int eqdma_sw_context_write(void *dev_hndl, uint8_t c2h, - uint16_t hw_qid, - const struct qdma_descq_sw_ctxt *ctxt) -{ - uint32_t sw_ctxt[EQDMA_SW_CONTEXT_NUM_WORDS] = {0}; - uint16_t num_words_count = 0; - uint32_t pasid_l, pasid_h; - uint32_t virtio_desc_base_l, virtio_desc_base_m, virtio_desc_base_h; - enum ind_ctxt_cmd_sel sel = c2h ? - QDMA_CTXT_SEL_SW_C2H : QDMA_CTXT_SEL_SW_H2C; - - /* Input args check */ - if (!dev_hndl || !ctxt) { - qdma_log_error("%s: dev_handle=%p sw_ctxt=%p NULL, err:%d\n", - __func__, dev_hndl, ctxt, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - pasid_l = - FIELD_GET(EQDMA_SW_CTXT_PASID_GET_L_MASK, ctxt->pasid); - pasid_h = - FIELD_GET(EQDMA_SW_CTXT_PASID_GET_H_MASK, ctxt->pasid); - - virtio_desc_base_l = (uint32_t)FIELD_GET( - EQDMA_SW_CTXT_VIRTIO_DSC_BASE_GET_L_MASK, - ctxt->virtio_dsc_base); - virtio_desc_base_m = (uint32_t)FIELD_GET( - EQDMA_SW_CTXT_VIRTIO_DSC_BASE_GET_M_MASK, - ctxt->virtio_dsc_base); - virtio_desc_base_h = (uint32_t)FIELD_GET( - EQDMA_SW_CTXT_VIRTIO_DSC_BASE_GET_H_MASK, - ctxt->virtio_dsc_base); - - sw_ctxt[num_words_count++] = - FIELD_SET(SW_IND_CTXT_DATA_W0_PIDX_MASK, ctxt->pidx) | - FIELD_SET(SW_IND_CTXT_DATA_W0_IRQ_ARM_MASK, ctxt->irq_arm) | - FIELD_SET(SW_IND_CTXT_DATA_W0_FNC_MASK, ctxt->fnc_id); - - qdma_log_debug("%s: pidx=%x, irq_arm=%x, fnc_id=%x\n", - __func__, ctxt->pidx, ctxt->irq_arm, ctxt->fnc_id); - - sw_ctxt[num_words_count++] = - FIELD_SET(SW_IND_CTXT_DATA_W1_QEN_MASK, ctxt->qen) | - FIELD_SET(SW_IND_CTXT_DATA_W1_FCRD_EN_MASK, ctxt->frcd_en) | - FIELD_SET(SW_IND_CTXT_DATA_W1_WBI_CHK_MASK, ctxt->wbi_chk) | - FIELD_SET(SW_IND_CTXT_DATA_W1_WBI_INTVL_EN_MASK, - ctxt->wbi_intvl_en) | - FIELD_SET(SW_IND_CTXT_DATA_W1_AT_MASK, ctxt->at) | - FIELD_SET(SW_IND_CTXT_DATA_W1_FETCH_MAX_MASK, ctxt->fetch_max) | - FIELD_SET(SW_IND_CTXT_DATA_W1_RNG_SZ_MASK, ctxt->rngsz_idx) | - FIELD_SET(SW_IND_CTXT_DATA_W1_DSC_SZ_MASK, ctxt->desc_sz) | - FIELD_SET(SW_IND_CTXT_DATA_W1_BYPASS_MASK, ctxt->bypass) | - FIELD_SET(SW_IND_CTXT_DATA_W1_MM_CHN_MASK, ctxt->mm_chn) | - FIELD_SET(SW_IND_CTXT_DATA_W1_WBK_EN_MASK, ctxt->wbk_en) | - FIELD_SET(SW_IND_CTXT_DATA_W1_IRQ_EN_MASK, ctxt->irq_en) | - FIELD_SET(SW_IND_CTXT_DATA_W1_PORT_ID_MASK, ctxt->port_id) | - FIELD_SET(SW_IND_CTXT_DATA_W1_IRQ_NO_LAST_MASK, - ctxt->irq_no_last) | - FIELD_SET(SW_IND_CTXT_DATA_W1_ERR_MASK, ctxt->err) | - FIELD_SET(SW_IND_CTXT_DATA_W1_ERR_WB_SENT_MASK, - ctxt->err_wb_sent) | - FIELD_SET(SW_IND_CTXT_DATA_W1_IRQ_REQ_MASK, ctxt->irq_req) | - FIELD_SET(SW_IND_CTXT_DATA_W1_MRKR_DIS_MASK, ctxt->mrkr_dis) | - FIELD_SET(SW_IND_CTXT_DATA_W1_IS_MM_MASK, ctxt->is_mm); - - qdma_log_debug("%s: qen=%x, frcd_en=%x, wbi_chk=%x, wbi_intvl_en=%x\n", - __func__, ctxt->qen, ctxt->frcd_en, ctxt->wbi_chk, - ctxt->wbi_intvl_en); - - qdma_log_debug("%s: at=%x, fetch_max=%x, rngsz_idx=%x, desc_sz=%x\n", - __func__, ctxt->at, ctxt->fetch_max, ctxt->rngsz_idx, - ctxt->desc_sz); - - qdma_log_debug("%s: bypass=%x, mm_chn=%x, wbk_en=%x, irq_en=%x\n", - __func__, ctxt->bypass, ctxt->mm_chn, ctxt->wbk_en, - ctxt->irq_en); - - qdma_log_debug("%s: port_id=%x, irq_no_last=%x,err=%x", - __func__, ctxt->port_id, ctxt->irq_no_last, ctxt->err); - qdma_log_debug(", err_wb_sent=%x\n", ctxt->err_wb_sent); - - qdma_log_debug("%s: irq_req=%x, mrkr_dis=%x, is_mm=%x\n", - __func__, ctxt->irq_req, ctxt->mrkr_dis, ctxt->is_mm); - - sw_ctxt[num_words_count++] = ctxt->ring_bs_addr & 0xffffffff; - sw_ctxt[num_words_count++] = (ctxt->ring_bs_addr >> 32) & 0xffffffff; - - sw_ctxt[num_words_count++] = - FIELD_SET(SW_IND_CTXT_DATA_W4_VEC_MASK, ctxt->vec) | - FIELD_SET(SW_IND_CTXT_DATA_W4_INT_AGGR_MASK, ctxt->intr_aggr) | - FIELD_SET(SW_IND_CTXT_DATA_W4_DIS_INTR_ON_VF_MASK, - ctxt->dis_intr_on_vf) | - FIELD_SET(SW_IND_CTXT_DATA_W4_VIRTIO_EN_MASK, - ctxt->virtio_en) | - FIELD_SET(SW_IND_CTXT_DATA_W4_PACK_BYP_OUT_MASK, - ctxt->pack_byp_out) | - FIELD_SET(SW_IND_CTXT_DATA_W4_IRQ_BYP_MASK, ctxt->irq_byp) | - FIELD_SET(SW_IND_CTXT_DATA_W4_HOST_ID_MASK, ctxt->host_id) | - FIELD_SET(SW_IND_CTXT_DATA_W4_PASID_L_MASK, pasid_l); - - sw_ctxt[num_words_count++] = - FIELD_SET(SW_IND_CTXT_DATA_W5_PASID_H_MASK, pasid_h) | - FIELD_SET(SW_IND_CTXT_DATA_W5_PASID_EN_MASK, ctxt->pasid_en) | - FIELD_SET(SW_IND_CTXT_DATA_W5_VIRTIO_DSC_BASE_L_MASK, - virtio_desc_base_l); - - sw_ctxt[num_words_count++] = - FIELD_SET(SW_IND_CTXT_DATA_W6_VIRTIO_DSC_BASE_M_MASK, - virtio_desc_base_m); - - sw_ctxt[num_words_count++] = - FIELD_SET(SW_IND_CTXT_DATA_W7_VIRTIO_DSC_BASE_H_MASK, - virtio_desc_base_h); - - - qdma_log_debug("%s: vec=%x, intr_aggr=%x\n", - __func__, ctxt->vec, ctxt->intr_aggr); - - return eqdma_indirect_reg_write(dev_hndl, sel, hw_qid, - sw_ctxt, num_words_count); -} - -/*****************************************************************************/ -/** - * eqdma_sw_context_read() - read sw context - * - * @dev_hndl: device handle - * @c2h: is c2h queue - * @hw_qid: hardware qid of the queue - * @ctxt: pointer to the output context data - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -static int eqdma_sw_context_read(void *dev_hndl, uint8_t c2h, - uint16_t hw_qid, - struct qdma_descq_sw_ctxt *ctxt) -{ - int rv = QDMA_SUCCESS; - uint32_t sw_ctxt[EQDMA_SW_CONTEXT_NUM_WORDS] = {0}; - uint32_t pasid_l, pasid_h; - uint32_t virtio_desc_base_l, virtio_desc_base_m, virtio_desc_base_h; - enum ind_ctxt_cmd_sel sel = c2h ? - QDMA_CTXT_SEL_SW_C2H : QDMA_CTXT_SEL_SW_H2C; - - if (!dev_hndl || !ctxt) { - qdma_log_error("%s: dev_handle=%p sw_ctxt=%p NULL, err:%d\n", - __func__, dev_hndl, ctxt, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - rv = eqdma_indirect_reg_read(dev_hndl, sel, hw_qid, - EQDMA_SW_CONTEXT_NUM_WORDS, sw_ctxt); - if (rv < 0) - return rv; - - ctxt->pidx = FIELD_GET(SW_IND_CTXT_DATA_W0_PIDX_MASK, sw_ctxt[0]); - ctxt->irq_arm = - (uint8_t)(FIELD_GET(SW_IND_CTXT_DATA_W0_IRQ_ARM_MASK, - sw_ctxt[0])); - ctxt->fnc_id = - (uint8_t)(FIELD_GET(SW_IND_CTXT_DATA_W0_FNC_MASK, - sw_ctxt[0])); - - qdma_log_debug("%s: pidx=%x, irq_arm=%x, fnc_id=%x", - __func__, ctxt->pidx, ctxt->irq_arm, ctxt->fnc_id); - - ctxt->qen = FIELD_GET(SW_IND_CTXT_DATA_W1_QEN_MASK, sw_ctxt[1]); - ctxt->frcd_en = FIELD_GET(SW_IND_CTXT_DATA_W1_FCRD_EN_MASK, sw_ctxt[1]); - ctxt->wbi_chk = FIELD_GET(SW_IND_CTXT_DATA_W1_WBI_CHK_MASK, sw_ctxt[1]); - ctxt->wbi_intvl_en = - FIELD_GET(SW_IND_CTXT_DATA_W1_WBI_INTVL_EN_MASK, sw_ctxt[1]); - ctxt->at = FIELD_GET(SW_IND_CTXT_DATA_W1_AT_MASK, sw_ctxt[1]); - ctxt->fetch_max = - (uint8_t)FIELD_GET(SW_IND_CTXT_DATA_W1_FETCH_MAX_MASK, - sw_ctxt[1]); - ctxt->rngsz_idx = - (uint8_t)(FIELD_GET(SW_IND_CTXT_DATA_W1_RNG_SZ_MASK, - sw_ctxt[1])); - ctxt->desc_sz = - (uint8_t)(FIELD_GET(SW_IND_CTXT_DATA_W1_DSC_SZ_MASK, - sw_ctxt[1])); - ctxt->bypass = - (uint8_t)(FIELD_GET(SW_IND_CTXT_DATA_W1_BYPASS_MASK, - sw_ctxt[1])); - ctxt->mm_chn = - (uint8_t)(FIELD_GET(SW_IND_CTXT_DATA_W1_MM_CHN_MASK, - sw_ctxt[1])); - ctxt->wbk_en = - (uint8_t)(FIELD_GET(SW_IND_CTXT_DATA_W1_WBK_EN_MASK, - sw_ctxt[1])); - ctxt->irq_en = - (uint8_t)(FIELD_GET(SW_IND_CTXT_DATA_W1_IRQ_EN_MASK, - sw_ctxt[1])); - ctxt->port_id = - (uint8_t)(FIELD_GET(SW_IND_CTXT_DATA_W1_PORT_ID_MASK, - sw_ctxt[1])); - ctxt->irq_no_last = - (uint8_t)(FIELD_GET(SW_IND_CTXT_DATA_W1_IRQ_NO_LAST_MASK, - sw_ctxt[1])); - ctxt->err = - (uint8_t)(FIELD_GET(SW_IND_CTXT_DATA_W1_ERR_MASK, sw_ctxt[1])); - ctxt->err_wb_sent = - (uint8_t)(FIELD_GET(SW_IND_CTXT_DATA_W1_ERR_WB_SENT_MASK, - sw_ctxt[1])); - ctxt->irq_req = - (uint8_t)(FIELD_GET(SW_IND_CTXT_DATA_W1_IRQ_REQ_MASK, - sw_ctxt[1])); - ctxt->mrkr_dis = - (uint8_t)(FIELD_GET(SW_IND_CTXT_DATA_W1_MRKR_DIS_MASK, - sw_ctxt[1])); - ctxt->is_mm = - (uint8_t)(FIELD_GET(SW_IND_CTXT_DATA_W1_IS_MM_MASK, - sw_ctxt[1])); - - qdma_log_debug("%s: qen=%x, frcd_en=%x, wbi_chk=%x, wbi_intvl_en=%x\n", - __func__, ctxt->qen, ctxt->frcd_en, ctxt->wbi_chk, - ctxt->wbi_intvl_en); - qdma_log_debug("%s: at=%x, fetch_max=%x, rngsz_idx=%x, desc_sz=%x\n", - __func__, ctxt->at, ctxt->fetch_max, ctxt->rngsz_idx, - ctxt->desc_sz); - qdma_log_debug("%s: bypass=%x, mm_chn=%x, wbk_en=%x, irq_en=%x\n", - __func__, ctxt->bypass, ctxt->mm_chn, ctxt->wbk_en, - ctxt->irq_en); - qdma_log_debug("%s: port_id=%x, irq_no_last=%x,", - __func__, ctxt->port_id, ctxt->irq_no_last); - qdma_log_debug(" err=%x, err_wb_sent=%x\n", - ctxt->err, ctxt->err_wb_sent); - qdma_log_debug("%s: irq_req=%x, mrkr_dis=%x, is_mm=%x\n", - __func__, ctxt->irq_req, ctxt->mrkr_dis, ctxt->is_mm); - - ctxt->ring_bs_addr = ((uint64_t)sw_ctxt[3] << 32) | (sw_ctxt[2]); - - ctxt->vec = FIELD_GET(SW_IND_CTXT_DATA_W4_VEC_MASK, sw_ctxt[4]); - ctxt->intr_aggr = (uint8_t)(FIELD_GET(SW_IND_CTXT_DATA_W4_INT_AGGR_MASK, - sw_ctxt[4])); - ctxt->dis_intr_on_vf = - (uint8_t)(FIELD_GET(SW_IND_CTXT_DATA_W4_DIS_INTR_ON_VF_MASK, - sw_ctxt[4])); - ctxt->virtio_en = - (uint8_t)(FIELD_GET(SW_IND_CTXT_DATA_W4_VIRTIO_EN_MASK, - sw_ctxt[4])); - ctxt->pack_byp_out = - (uint8_t)(FIELD_GET(SW_IND_CTXT_DATA_W4_PACK_BYP_OUT_MASK, - sw_ctxt[4])); - ctxt->irq_byp = - (uint8_t)(FIELD_GET(SW_IND_CTXT_DATA_W4_IRQ_BYP_MASK, - sw_ctxt[4])); - ctxt->host_id = - (uint8_t)(FIELD_GET(SW_IND_CTXT_DATA_W4_HOST_ID_MASK, - sw_ctxt[4])); - pasid_l = FIELD_GET(SW_IND_CTXT_DATA_W4_PASID_L_MASK, sw_ctxt[4]); - - pasid_h = FIELD_GET(SW_IND_CTXT_DATA_W5_PASID_H_MASK, sw_ctxt[5]); - ctxt->pasid_en = (uint8_t)FIELD_GET(SW_IND_CTXT_DATA_W5_PASID_EN_MASK, - sw_ctxt[5]); - virtio_desc_base_l = - FIELD_GET(SW_IND_CTXT_DATA_W5_VIRTIO_DSC_BASE_L_MASK, - sw_ctxt[5]); - virtio_desc_base_m = - FIELD_GET(SW_IND_CTXT_DATA_W6_VIRTIO_DSC_BASE_M_MASK, - sw_ctxt[6]); - - virtio_desc_base_h = - FIELD_GET(SW_IND_CTXT_DATA_W7_VIRTIO_DSC_BASE_H_MASK, - sw_ctxt[6]); - - ctxt->pasid = - FIELD_SET(EQDMA_SW_CTXT_PASID_GET_L_MASK, pasid_l) | - FIELD_SET(EQDMA_SW_CTXT_PASID_GET_H_MASK, pasid_h); - - ctxt->virtio_dsc_base = - FIELD_SET(EQDMA_SW_CTXT_VIRTIO_DSC_BASE_GET_L_MASK, - (uint64_t)virtio_desc_base_l) | - FIELD_SET(EQDMA_SW_CTXT_VIRTIO_DSC_BASE_GET_M_MASK, - (uint64_t)virtio_desc_base_m) | - FIELD_SET(EQDMA_SW_CTXT_VIRTIO_DSC_BASE_GET_H_MASK, - (uint64_t)virtio_desc_base_h); - - qdma_log_debug("%s: vec=%x, intr_aggr=%x\n", - __func__, ctxt->vec, ctxt->intr_aggr); - - return QDMA_SUCCESS; -} - -/*****************************************************************************/ -/** - * eqdma_sw_context_clear() - clear sw context - * - * @dev_hndl: device handle - * @c2h: is c2h queue - * @hw_qid: hardware qid of the queue - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -static int eqdma_sw_context_clear(void *dev_hndl, uint8_t c2h, - uint16_t hw_qid) -{ - enum ind_ctxt_cmd_sel sel = c2h ? - QDMA_CTXT_SEL_SW_C2H : QDMA_CTXT_SEL_SW_H2C; - - if (!dev_hndl) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", __func__, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - return eqdma_indirect_reg_clear(dev_hndl, sel, hw_qid); -} - -/*****************************************************************************/ -/** - * eqdma_sw_context_invalidate() - invalidate sw context - * - * @dev_hndl: device handle - * @c2h: is c2h queue - * @hw_qid: hardware qid of the queue - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -static int eqdma_sw_context_invalidate(void *dev_hndl, uint8_t c2h, - uint16_t hw_qid) -{ - enum ind_ctxt_cmd_sel sel = c2h ? - QDMA_CTXT_SEL_SW_C2H : QDMA_CTXT_SEL_SW_H2C; - - if (!dev_hndl) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", __func__, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - return eqdma_indirect_reg_invalidate(dev_hndl, sel, hw_qid); -} - -/*****************************************************************************/ -/** - * eqdma_sw_ctx_conf() - configure SW context - * - * @dev_hndl: device handle - * @c2h: is c2h queue - * @hw_qid: hardware qid of the queue - * @ctxt: pointer to the context data - * @access_type HW access type (qdma_hw_access_type enum) value - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -int eqdma_sw_ctx_conf(void *dev_hndl, uint8_t c2h, uint16_t hw_qid, - struct qdma_descq_sw_ctxt *ctxt, - enum qdma_hw_access_type access_type) -{ - int rv = QDMA_SUCCESS; - - switch (access_type) { - case QDMA_HW_ACCESS_READ: - rv = eqdma_sw_context_read(dev_hndl, c2h, hw_qid, ctxt); - break; - case QDMA_HW_ACCESS_WRITE: - rv = eqdma_sw_context_write(dev_hndl, c2h, hw_qid, ctxt); - break; - case QDMA_HW_ACCESS_CLEAR: - rv = eqdma_sw_context_clear(dev_hndl, c2h, hw_qid); - break; - case QDMA_HW_ACCESS_INVALIDATE: - rv = eqdma_sw_context_invalidate(dev_hndl, c2h, hw_qid); - break; - default: - qdma_log_error("%s: access_type(%d) invalid, err:%d\n", - __func__, - access_type, - -QDMA_ERR_INV_PARAM); - rv = -QDMA_ERR_INV_PARAM; - break; - } - - return rv; -} - -/*****************************************************************************/ -/** - * eqdma_pfetch_context_write() - create prefetch context and program it - * - * @dev_hndl: device handle - * @hw_qid: hardware qid of the queue - * @ctxt: pointer to the prefetch context data strucutre - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -static int eqdma_pfetch_context_write(void *dev_hndl, uint16_t hw_qid, - const struct qdma_descq_prefetch_ctxt *ctxt) -{ - uint32_t pfetch_ctxt[EQDMA_PFETCH_CONTEXT_NUM_WORDS] = {0}; - enum ind_ctxt_cmd_sel sel = QDMA_CTXT_SEL_PFTCH; - uint32_t sw_crdt_l, sw_crdt_h; - uint16_t num_words_count = 0; - - if (!dev_hndl || !ctxt) { - qdma_log_error("%s: dev_handle or pfetch ctxt NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - sw_crdt_l = - FIELD_GET(QDMA_PFTCH_CTXT_SW_CRDT_GET_L_MASK, ctxt->sw_crdt); - sw_crdt_h = - FIELD_GET(QDMA_PFTCH_CTXT_SW_CRDT_GET_H_MASK, ctxt->sw_crdt); - - qdma_log_debug("%s: sw_crdt_l=%u, sw_crdt_h=%u, hw_qid=%hu\n", - __func__, sw_crdt_l, sw_crdt_h, hw_qid); - - pfetch_ctxt[num_words_count++] = - FIELD_SET(PREFETCH_CTXT_DATA_W0_BYPASS_MASK, ctxt->bypass) | - FIELD_SET(PREFETCH_CTXT_DATA_W0_BUF_SZ_IDX_MASK, - ctxt->bufsz_idx) | - FIELD_SET(PREFETCH_CTXT_DATA_W0_PORT_ID_MASK, ctxt->port_id) | - FIELD_SET(PREFETCH_CTXT_DATA_W0_NUM_PFCH_MASK, - ctxt->num_pftch) | - FIELD_SET(PREFETCH_CTXT_DATA_W0_VAR_DESC_MASK, - ctxt->var_desc) | - FIELD_SET(PREFETCH_CTXT_DATA_W0_ERR_MASK, ctxt->err) | - FIELD_SET(PREFETCH_CTXT_DATA_W0_PFCH_EN_MASK, ctxt->pfch_en) | - FIELD_SET(PREFETCH_CTXT_DATA_W0_PFCH_MASK, ctxt->pfch) | - FIELD_SET(PREFETCH_CTXT_DATA_W0_SW_CRDT_L_MASK, sw_crdt_l); - - qdma_log_debug("%s: bypass=%x, bufsz_idx=%x, port_id=%x\n", - __func__, ctxt->bypass, ctxt->bufsz_idx, ctxt->port_id); - qdma_log_debug("%s: err=%x, pfch_en=%x, pfch=%x, ctxt->valid=%x\n", - __func__, ctxt->err, ctxt->pfch_en, ctxt->pfch, - ctxt->valid); - - pfetch_ctxt[num_words_count++] = - FIELD_SET(PREFETCH_CTXT_DATA_W1_SW_CRDT_H_MASK, sw_crdt_h) | - FIELD_SET(PREFETCH_CTXT_DATA_W1_VALID_MASK, ctxt->valid); - - return eqdma_indirect_reg_write(dev_hndl, sel, hw_qid, - pfetch_ctxt, num_words_count); -} - -/*****************************************************************************/ -/** - * eqdma_pfetch_context_read() - read prefetch context - * - * @dev_hndl: device handle - * @hw_qid: hardware qid of the queue - * @ctxt: pointer to the output context data - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -static int eqdma_pfetch_context_read(void *dev_hndl, uint16_t hw_qid, - struct qdma_descq_prefetch_ctxt *ctxt) -{ - int rv = QDMA_SUCCESS; - uint32_t pfetch_ctxt[EQDMA_PFETCH_CONTEXT_NUM_WORDS] = {0}; - enum ind_ctxt_cmd_sel sel = QDMA_CTXT_SEL_PFTCH; - uint32_t sw_crdt_l, sw_crdt_h; - - if (!dev_hndl || !ctxt) { - qdma_log_error("%s: dev_handle or pfetch ctxt NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - rv = eqdma_indirect_reg_read(dev_hndl, sel, hw_qid, - EQDMA_PFETCH_CONTEXT_NUM_WORDS, pfetch_ctxt); - if (rv < 0) - return rv; - - ctxt->bypass = - FIELD_GET(PREFETCH_CTXT_DATA_W0_BYPASS_MASK, pfetch_ctxt[0]); - ctxt->bufsz_idx = - FIELD_GET(PREFETCH_CTXT_DATA_W0_BUF_SZ_IDX_MASK, - pfetch_ctxt[0]); - ctxt->num_pftch = (uint16_t) FIELD_GET( - PREFETCH_CTXT_DATA_W0_NUM_PFCH_MASK, pfetch_ctxt[0]); - ctxt->port_id = - FIELD_GET(PREFETCH_CTXT_DATA_W0_PORT_ID_MASK, pfetch_ctxt[0]); - ctxt->var_desc = (uint8_t) - FIELD_GET(PREFETCH_CTXT_DATA_W0_VAR_DESC_MASK, - pfetch_ctxt[0]); - ctxt->err = - (uint8_t)(FIELD_GET(PREFETCH_CTXT_DATA_W0_ERR_MASK, - pfetch_ctxt[0])); - ctxt->pfch_en = - (uint8_t)(FIELD_GET(PREFETCH_CTXT_DATA_W0_PFCH_EN_MASK, - pfetch_ctxt[0])); - ctxt->pfch = - (uint8_t)(FIELD_GET(PREFETCH_CTXT_DATA_W0_PFCH_MASK, - pfetch_ctxt[0])); - sw_crdt_l = - FIELD_GET(PREFETCH_CTXT_DATA_W0_SW_CRDT_L_MASK, pfetch_ctxt[0]); - - sw_crdt_h = - FIELD_GET(PREFETCH_CTXT_DATA_W1_SW_CRDT_H_MASK, pfetch_ctxt[1]); - ctxt->valid = - (uint8_t)(FIELD_GET(PREFETCH_CTXT_DATA_W1_VALID_MASK, - pfetch_ctxt[1])); - - ctxt->sw_crdt = - FIELD_SET(QDMA_PFTCH_CTXT_SW_CRDT_GET_L_MASK, sw_crdt_l) | - FIELD_SET(QDMA_PFTCH_CTXT_SW_CRDT_GET_H_MASK, sw_crdt_h); - - qdma_log_debug("%s: sw_crdt_l=%u, sw_crdt_h=%u, hw_qid=%hu\n", - __func__, sw_crdt_l, sw_crdt_h, hw_qid); - qdma_log_debug("%s: bypass=%x, bufsz_idx=%x, port_id=%x\n", - __func__, ctxt->bypass, ctxt->bufsz_idx, ctxt->port_id); - qdma_log_debug("%s: err=%x, pfch_en=%x, pfch=%x, ctxt->valid=%x\n", - __func__, ctxt->err, ctxt->pfch_en, ctxt->pfch, - ctxt->valid); - - return QDMA_SUCCESS; -} - -/*****************************************************************************/ -/** - * eqdma_pfetch_context_clear() - clear prefetch context - * - * @dev_hndl: device handle - * @hw_qid: hardware qid of the queue - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -static int eqdma_pfetch_context_clear(void *dev_hndl, uint16_t hw_qid) -{ - enum ind_ctxt_cmd_sel sel = QDMA_CTXT_SEL_PFTCH; - - if (!dev_hndl) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", __func__, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - return eqdma_indirect_reg_clear(dev_hndl, sel, hw_qid); -} - -/*****************************************************************************/ -/** - * eqdma_pfetch_context_invalidate() - invalidate prefetch context - * - * @dev_hndl: device handle - * @hw_qid: hardware qid of the queue - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -static int eqdma_pfetch_context_invalidate(void *dev_hndl, uint16_t hw_qid) -{ - enum ind_ctxt_cmd_sel sel = QDMA_CTXT_SEL_PFTCH; - - if (!dev_hndl) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", __func__, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - return eqdma_indirect_reg_invalidate(dev_hndl, sel, hw_qid); -} - -/*****************************************************************************/ -/** - * eqdma_pfetch_ctx_conf() - configure prefetch context - * - * @dev_hndl: device handle - * @hw_qid: hardware qid of the queue - * @ctxt: pointer to context data - * @access_type HW access type (qdma_hw_access_type enum) value - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -int eqdma_pfetch_ctx_conf(void *dev_hndl, uint16_t hw_qid, - struct qdma_descq_prefetch_ctxt *ctxt, - enum qdma_hw_access_type access_type) -{ - int rv = QDMA_SUCCESS; - - switch (access_type) { - case QDMA_HW_ACCESS_READ: - rv = eqdma_pfetch_context_read(dev_hndl, hw_qid, ctxt); - break; - case QDMA_HW_ACCESS_WRITE: - rv = eqdma_pfetch_context_write(dev_hndl, hw_qid, ctxt); - break; - case QDMA_HW_ACCESS_CLEAR: - rv = eqdma_pfetch_context_clear(dev_hndl, hw_qid); - break; - case QDMA_HW_ACCESS_INVALIDATE: - rv = eqdma_pfetch_context_invalidate(dev_hndl, hw_qid); - break; - default: - qdma_log_error("%s: access_type(%d) invalid, err:%d\n", - __func__, - access_type, - -QDMA_ERR_INV_PARAM); - rv = -QDMA_ERR_INV_PARAM; - break; - } - - return rv; -} - -/*****************************************************************************/ -/** - * eqdma_cmpt_context_write() - create completion context and program it - * - * @dev_hndl: device handle - * @hw_qid: hardware qid of the queue - * @ctxt: pointer to the cmpt context data strucutre - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -static int eqdma_cmpt_context_write(void *dev_hndl, uint16_t hw_qid, - const struct qdma_descq_cmpt_ctxt *ctxt) -{ - uint32_t cmpt_ctxt[EQDMA_CMPT_CONTEXT_NUM_WORDS] = {0}; - uint16_t num_words_count = 0; - uint32_t baddr4_high_l, baddr4_high_h, - baddr4_low, pidx_l, pidx_h, pasid_l, pasid_h; - enum ind_ctxt_cmd_sel sel = QDMA_CTXT_SEL_CMPT; - - /* Input args check */ - if (!dev_hndl || !ctxt) { - qdma_log_error("%s: dev_handle or cmpt ctxt NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - if (ctxt->trig_mode > QDMA_CMPT_UPDATE_TRIG_MODE_TMR_CNTR) { - qdma_log_error("%s: trig_mode(%d) > (%d) is invalid, err:%d\n", - __func__, - ctxt->trig_mode, - QDMA_CMPT_UPDATE_TRIG_MODE_TMR_CNTR, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - baddr4_high_l = (uint32_t)FIELD_GET(EQDMA_COMPL_CTXT_BADDR_HIGH_L_MASK, - ctxt->bs_addr); - baddr4_high_h = (uint32_t)FIELD_GET(EQDMA_COMPL_CTXT_BADDR_HIGH_H_MASK, - ctxt->bs_addr); - baddr4_low = (uint32_t)FIELD_GET(EQDMA_COMPL_CTXT_BADDR_LOW_MASK, - ctxt->bs_addr); - - pidx_l = FIELD_GET(QDMA_COMPL_CTXT_PIDX_GET_L_MASK, ctxt->pidx); - pidx_h = FIELD_GET(QDMA_COMPL_CTXT_PIDX_GET_H_MASK, ctxt->pidx); - - pasid_l = - FIELD_GET(EQDMA_CMPL_CTXT_PASID_GET_L_MASK, ctxt->pasid); - pasid_h = - FIELD_GET(EQDMA_CMPL_CTXT_PASID_GET_H_MASK, ctxt->pasid); - - cmpt_ctxt[num_words_count++] = - FIELD_SET(CMPL_CTXT_DATA_W0_EN_STAT_DESC_MASK, - ctxt->en_stat_desc) | - FIELD_SET(CMPL_CTXT_DATA_W0_EN_INT_MASK, ctxt->en_int) | - FIELD_SET(CMPL_CTXT_DATA_W0_TRIG_MODE_MASK, ctxt->trig_mode) | - FIELD_SET(CMPL_CTXT_DATA_W0_FNC_ID_MASK, ctxt->fnc_id) | - FIELD_SET(CMPL_CTXT_DATA_W0_CNTER_IX_MASK, - ctxt->counter_idx) | - FIELD_SET(CMPL_CTXT_DATA_W0_TIMER_IX_MASK, ctxt->timer_idx) | - FIELD_SET(CMPL_CTXT_DATA_W0_INT_ST_MASK, ctxt->in_st) | - FIELD_SET(CMPL_CTXT_DATA_W0_COLOR_MASK, ctxt->color) | - FIELD_SET(CMPL_CTXT_DATA_W0_QSIZE_IX_MASK, ctxt->ringsz_idx); - - cmpt_ctxt[num_words_count++] = - FIELD_SET(CMPL_CTXT_DATA_W1_BADDR4_HIGH_L_MASK, baddr4_high_l); - - cmpt_ctxt[num_words_count++] = - FIELD_SET(CMPL_CTXT_DATA_W2_BADDR4_HIGH_H_MASK, baddr4_high_h) | - FIELD_SET(CMPL_CTXT_DATA_W2_DESC_SIZE_MASK, ctxt->desc_sz) | - FIELD_SET(CMPL_CTXT_DATA_W2_PIDX_L_MASK, pidx_l); - - cmpt_ctxt[num_words_count++] = - FIELD_SET(CMPL_CTXT_DATA_W3_PIDX_H_MASK, pidx_h) | - FIELD_SET(CMPL_CTXT_DATA_W3_CIDX_MASK, ctxt->cidx) | - FIELD_SET(CMPL_CTXT_DATA_W3_VALID_MASK, ctxt->valid) | - FIELD_SET(CMPL_CTXT_DATA_W3_ERR_MASK, ctxt->err) | - FIELD_SET(CMPL_CTXT_DATA_W3_USER_TRIG_PEND_MASK, - ctxt->user_trig_pend); - - cmpt_ctxt[num_words_count++] = - FIELD_SET(CMPL_CTXT_DATA_W4_TIMER_RUNNING_MASK, - ctxt->timer_running) | - FIELD_SET(CMPL_CTXT_DATA_W4_FULL_UPD_MASK, ctxt->full_upd) | - FIELD_SET(CMPL_CTXT_DATA_W4_OVF_CHK_DIS_MASK, - ctxt->ovf_chk_dis) | - FIELD_SET(CMPL_CTXT_DATA_W4_AT_MASK, ctxt->at) | - FIELD_SET(CMPL_CTXT_DATA_W4_VEC_MASK, ctxt->vec) | - FIELD_SET(CMPL_CTXT_DATA_W4_INT_AGGR_MASK, ctxt->int_aggr) | - FIELD_SET(CMPL_CTXT_DATA_W4_DIS_INTR_ON_VF_MASK, - ctxt->dis_intr_on_vf) | - FIELD_SET(CMPL_CTXT_DATA_W4_VIO_MASK, ctxt->vio) | - FIELD_SET(CMPL_CTXT_DATA_W4_DIR_C2H_MASK, ctxt->dir_c2h) | - FIELD_SET(CMPL_CTXT_DATA_W4_HOST_ID_MASK, ctxt->host_id) | - FIELD_SET(CMPL_CTXT_DATA_W4_PASID_L_MASK, pasid_l); - - cmpt_ctxt[num_words_count++] = - FIELD_SET(CMPL_CTXT_DATA_W5_PASID_H_MASK, pasid_h) | - FIELD_SET(CMPL_CTXT_DATA_W5_PASID_EN_MASK, - ctxt->pasid_en) | - FIELD_SET(CMPL_CTXT_DATA_W5_BADDR4_LOW_MASK, - baddr4_low) | - FIELD_SET(CMPL_CTXT_DATA_W5_VIO_EOP_MASK, ctxt->vio_eop) | - FIELD_SET(CMPL_CTXT_DATA_W5_SH_CMPT_MASK, ctxt->sh_cmpt); - - return eqdma_indirect_reg_write(dev_hndl, sel, hw_qid, - cmpt_ctxt, num_words_count); -} - -/*****************************************************************************/ -/** - * eqdma_cmpt_context_read() - read completion context - * - * @dev_hndl: device handle - * @hw_qid: hardware qid of the queue - * @ctxt: pointer to the context data - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -static int eqdma_cmpt_context_read(void *dev_hndl, uint16_t hw_qid, - struct qdma_descq_cmpt_ctxt *ctxt) -{ - int rv = QDMA_SUCCESS; - uint32_t cmpt_ctxt[EQDMA_CMPT_CONTEXT_NUM_WORDS] = {0}; - enum ind_ctxt_cmd_sel sel = QDMA_CTXT_SEL_CMPT; - uint32_t baddr4_high_l, baddr4_high_h, baddr4_low, - pidx_l, pidx_h, pasid_l, pasid_h; - - if (!dev_hndl || !ctxt) { - qdma_log_error("%s: dev_handle or cmpt ctxt NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - rv = eqdma_indirect_reg_read(dev_hndl, sel, hw_qid, - EQDMA_CMPT_CONTEXT_NUM_WORDS, cmpt_ctxt); - if (rv < 0) - return rv; - - ctxt->en_stat_desc = - FIELD_GET(CMPL_CTXT_DATA_W0_EN_STAT_DESC_MASK, cmpt_ctxt[0]); - ctxt->en_int = FIELD_GET(CMPL_CTXT_DATA_W0_EN_INT_MASK, cmpt_ctxt[0]); - ctxt->trig_mode = - FIELD_GET(CMPL_CTXT_DATA_W0_TRIG_MODE_MASK, cmpt_ctxt[0]); - ctxt->fnc_id = - (uint8_t)(FIELD_GET(CMPL_CTXT_DATA_W0_FNC_ID_MASK, - cmpt_ctxt[0])); - ctxt->counter_idx = - (uint8_t)(FIELD_GET(CMPL_CTXT_DATA_W0_CNTER_IX_MASK, - cmpt_ctxt[0])); - ctxt->timer_idx = - (uint8_t)(FIELD_GET(CMPL_CTXT_DATA_W0_TIMER_IX_MASK, - cmpt_ctxt[0])); - ctxt->in_st = - (uint8_t)(FIELD_GET(CMPL_CTXT_DATA_W0_INT_ST_MASK, - cmpt_ctxt[0])); - ctxt->color = - (uint8_t)(FIELD_GET(CMPL_CTXT_DATA_W0_COLOR_MASK, - cmpt_ctxt[0])); - ctxt->ringsz_idx = - (uint8_t)(FIELD_GET(CMPL_CTXT_DATA_W0_QSIZE_IX_MASK, - cmpt_ctxt[0])); - - baddr4_high_l = FIELD_GET(CMPL_CTXT_DATA_W1_BADDR4_HIGH_L_MASK, - cmpt_ctxt[1]); - - baddr4_high_h = FIELD_GET(CMPL_CTXT_DATA_W2_BADDR4_HIGH_H_MASK, - cmpt_ctxt[2]); - ctxt->desc_sz = - (uint8_t)(FIELD_GET(CMPL_CTXT_DATA_W2_DESC_SIZE_MASK, - cmpt_ctxt[2])); - pidx_l = FIELD_GET(CMPL_CTXT_DATA_W2_PIDX_L_MASK, cmpt_ctxt[2]); - - pidx_h = FIELD_GET(CMPL_CTXT_DATA_W3_PIDX_H_MASK, cmpt_ctxt[3]); - ctxt->cidx = - (uint16_t)(FIELD_GET(CMPL_CTXT_DATA_W3_CIDX_MASK, - cmpt_ctxt[3])); - ctxt->valid = - (uint8_t)(FIELD_GET(CMPL_CTXT_DATA_W3_VALID_MASK, - cmpt_ctxt[3])); - ctxt->err = - (uint8_t)(FIELD_GET(CMPL_CTXT_DATA_W3_ERR_MASK, - cmpt_ctxt[3])); - ctxt->user_trig_pend = (uint8_t) - (FIELD_GET(CMPL_CTXT_DATA_W3_USER_TRIG_PEND_MASK, - cmpt_ctxt[3])); - - ctxt->timer_running = - FIELD_GET(CMPL_CTXT_DATA_W4_TIMER_RUNNING_MASK, cmpt_ctxt[4]); - ctxt->full_upd = - FIELD_GET(CMPL_CTXT_DATA_W4_FULL_UPD_MASK, cmpt_ctxt[4]); - ctxt->ovf_chk_dis = - FIELD_GET(CMPL_CTXT_DATA_W4_OVF_CHK_DIS_MASK, cmpt_ctxt[4]); - ctxt->at = FIELD_GET(CMPL_CTXT_DATA_W4_AT_MASK, cmpt_ctxt[4]); - ctxt->vec = FIELD_GET(CMPL_CTXT_DATA_W4_VEC_MASK, cmpt_ctxt[4]); - ctxt->int_aggr = (uint8_t) - (FIELD_GET(CMPL_CTXT_DATA_W4_INT_AGGR_MASK, cmpt_ctxt[4])); - ctxt->dis_intr_on_vf = (uint8_t) - FIELD_GET(CMPL_CTXT_DATA_W4_DIS_INTR_ON_VF_MASK, - cmpt_ctxt[4]); - ctxt->vio = (uint8_t)FIELD_GET(CMPL_CTXT_DATA_W4_VIO_MASK, - cmpt_ctxt[4]); - ctxt->dir_c2h = (uint8_t)FIELD_GET(CMPL_CTXT_DATA_W4_DIR_C2H_MASK, - cmpt_ctxt[4]); - ctxt->host_id = (uint8_t)FIELD_GET(CMPL_CTXT_DATA_W4_HOST_ID_MASK, - cmpt_ctxt[4]); - pasid_l = FIELD_GET(CMPL_CTXT_DATA_W4_PASID_L_MASK, cmpt_ctxt[4]); - - pasid_h = (uint32_t)FIELD_GET(CMPL_CTXT_DATA_W5_PASID_H_MASK, - cmpt_ctxt[5]); - ctxt->pasid_en = (uint8_t)FIELD_GET(CMPL_CTXT_DATA_W5_PASID_EN_MASK, - cmpt_ctxt[5]); - baddr4_low = (uint8_t)FIELD_GET( - CMPL_CTXT_DATA_W5_BADDR4_LOW_MASK, cmpt_ctxt[5]); - ctxt->vio_eop = (uint8_t)FIELD_GET(CMPL_CTXT_DATA_W5_VIO_EOP_MASK, - cmpt_ctxt[5]); - ctxt->sh_cmpt = (uint8_t)FIELD_GET(CMPL_CTXT_DATA_W5_SH_CMPT_MASK, - cmpt_ctxt[5]); - - ctxt->bs_addr = - FIELD_SET(EQDMA_COMPL_CTXT_BADDR_HIGH_L_MASK, - (uint64_t)baddr4_high_l) | - FIELD_SET(EQDMA_COMPL_CTXT_BADDR_HIGH_H_MASK, - (uint64_t)baddr4_high_h) | - FIELD_SET(EQDMA_COMPL_CTXT_BADDR_LOW_MASK, - (uint64_t)baddr4_low); - - ctxt->pasid = - FIELD_SET(EQDMA_CMPL_CTXT_PASID_GET_L_MASK, pasid_l) | - FIELD_SET(EQDMA_CMPL_CTXT_PASID_GET_H_MASK, - (uint64_t)pasid_h); - - ctxt->pidx = - FIELD_SET(QDMA_COMPL_CTXT_PIDX_GET_L_MASK, pidx_l) | - FIELD_SET(QDMA_COMPL_CTXT_PIDX_GET_H_MASK, pidx_h); - - return QDMA_SUCCESS; -} - -/*****************************************************************************/ -/** - * eqdma_cmpt_context_clear() - clear completion context - * - * @dev_hndl: device handle - * @hw_qid: hardware qid of the queue - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -static int eqdma_cmpt_context_clear(void *dev_hndl, uint16_t hw_qid) -{ - enum ind_ctxt_cmd_sel sel = QDMA_CTXT_SEL_CMPT; - - if (!dev_hndl) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", __func__, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - return eqdma_indirect_reg_clear(dev_hndl, sel, hw_qid); -} - -/*****************************************************************************/ -/** - * eqdma_cmpt_context_invalidate() - invalidate completion context - * - * @dev_hndl: device handle - * @hw_qid: hardware qid of the queue - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -static int eqdma_cmpt_context_invalidate(void *dev_hndl, uint16_t hw_qid) -{ - enum ind_ctxt_cmd_sel sel = QDMA_CTXT_SEL_CMPT; - - if (!dev_hndl) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", __func__, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - return eqdma_indirect_reg_invalidate(dev_hndl, sel, hw_qid); -} - -/*****************************************************************************/ -/** - * eqdma_cmpt_ctx_conf() - configure completion context - * - * @dev_hndl: device handle - * @hw_qid: hardware qid of the queue - * @ctxt: pointer to context data - * @access_type HW access type (qdma_hw_access_type enum) value - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -int eqdma_cmpt_ctx_conf(void *dev_hndl, uint16_t hw_qid, - struct qdma_descq_cmpt_ctxt *ctxt, - enum qdma_hw_access_type access_type) -{ - int rv = QDMA_SUCCESS; - - switch (access_type) { - case QDMA_HW_ACCESS_READ: - rv = eqdma_cmpt_context_read(dev_hndl, hw_qid, ctxt); - break; - case QDMA_HW_ACCESS_WRITE: - rv = eqdma_cmpt_context_write(dev_hndl, hw_qid, ctxt); - break; - case QDMA_HW_ACCESS_CLEAR: - rv = eqdma_cmpt_context_clear(dev_hndl, hw_qid); - break; - case QDMA_HW_ACCESS_INVALIDATE: - rv = eqdma_cmpt_context_invalidate(dev_hndl, hw_qid); - break; - default: - qdma_log_error("%s: access_type(%d) invalid, err:%d\n", - __func__, - access_type, - -QDMA_ERR_INV_PARAM); - rv = -QDMA_ERR_INV_PARAM; - break; - } - - return rv; -} - -/*****************************************************************************/ -/** - * eqdma_hw_context_read() - read hardware context - * - * @dev_hndl: device handle - * @c2h: is c2h queue - * @hw_qid: hardware qid of the queue - * @ctxt: pointer to the output context data - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -static int eqdma_hw_context_read(void *dev_hndl, uint8_t c2h, - uint16_t hw_qid, struct qdma_descq_hw_ctxt *ctxt) -{ - int rv = QDMA_SUCCESS; - uint32_t hw_ctxt[EQDMA_HW_CONTEXT_NUM_WORDS] = {0}; - enum ind_ctxt_cmd_sel sel = c2h ? QDMA_CTXT_SEL_HW_C2H : - QDMA_CTXT_SEL_HW_H2C; - - if (!dev_hndl || !ctxt) { - qdma_log_error("%s: dev_handle or hw_ctxt NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - rv = eqdma_indirect_reg_read(dev_hndl, sel, hw_qid, - EQDMA_HW_CONTEXT_NUM_WORDS, hw_ctxt); - if (rv < 0) - return rv; - - ctxt->cidx = FIELD_GET(HW_IND_CTXT_DATA_W0_CIDX_MASK, hw_ctxt[0]); - ctxt->crd_use = - (uint16_t)(FIELD_GET(HW_IND_CTXT_DATA_W0_CRD_USE_MASK, - hw_ctxt[0])); - - ctxt->dsc_pend = - (uint8_t)(FIELD_GET(HW_IND_CTXT_DATA_W1_DSC_PND_MASK, - hw_ctxt[1])); - ctxt->idl_stp_b = - (uint8_t)(FIELD_GET(HW_IND_CTXT_DATA_W1_IDL_STP_B_MASK, - hw_ctxt[1])); - ctxt->evt_pnd = - (uint8_t)(FIELD_GET(HW_IND_CTXT_DATA_W1_EVT_PND_MASK, - hw_ctxt[1])); - ctxt->fetch_pnd = (uint8_t) - (FIELD_GET(HW_IND_CTXT_DATA_W1_DSC_PND_MASK, hw_ctxt[1])); - - qdma_log_debug("%s: cidx=%hu, crd_use=%hu, dsc_pend=%x\n", - __func__, ctxt->cidx, ctxt->crd_use, ctxt->dsc_pend); - qdma_log_debug("%s: idl_stp_b=%x, evt_pnd=%x, fetch_pnd=%x\n", - __func__, ctxt->idl_stp_b, ctxt->evt_pnd, - ctxt->fetch_pnd); - - return QDMA_SUCCESS; -} - -/*****************************************************************************/ -/** - * eqdma_hw_context_clear() - clear hardware context - * - * @dev_hndl: device handle - * @c2h: is c2h queue - * @hw_qid: hardware qid of the queue - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -static int eqdma_hw_context_clear(void *dev_hndl, uint8_t c2h, - uint16_t hw_qid) -{ - enum ind_ctxt_cmd_sel sel = c2h ? QDMA_CTXT_SEL_HW_C2H : - QDMA_CTXT_SEL_HW_H2C; - - if (!dev_hndl) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", __func__, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - return eqdma_indirect_reg_clear(dev_hndl, sel, hw_qid); -} - -/*****************************************************************************/ -/** - * eqdma_hw_context_invalidate() - invalidate hardware context - * - * @dev_hndl: device handle - * @c2h: is c2h queue - * @hw_qid: hardware qid of the queue - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -static int eqdma_hw_context_invalidate(void *dev_hndl, uint8_t c2h, - uint16_t hw_qid) -{ - enum ind_ctxt_cmd_sel sel = c2h ? QDMA_CTXT_SEL_HW_C2H : - QDMA_CTXT_SEL_HW_H2C; - - if (!dev_hndl) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", __func__, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - return eqdma_indirect_reg_invalidate(dev_hndl, sel, hw_qid); -} - -/*****************************************************************************/ -/** - * eqdma_hw_ctx_conf() - configure HW context - * - * @dev_hndl: device handle - * @c2h: is c2h queue - * @hw_qid: hardware qid of the queue - * @ctxt: pointer to context data - * @access_type HW access type (qdma_hw_access_type enum) value - * QDMA_HW_ACCESS_WRITE Not supported - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -int eqdma_hw_ctx_conf(void *dev_hndl, uint8_t c2h, uint16_t hw_qid, - struct qdma_descq_hw_ctxt *ctxt, - enum qdma_hw_access_type access_type) -{ - int rv = QDMA_SUCCESS; - - /** ctxt requires only H2C-0 or C2H-1 - * return error for any other values - */ - if (c2h > 1) { - qdma_log_error("%s: c2h(%d) invalid, err:%d\n", - __func__, - c2h, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - switch (access_type) { - case QDMA_HW_ACCESS_READ: - rv = eqdma_hw_context_read(dev_hndl, c2h, hw_qid, ctxt); - break; - case QDMA_HW_ACCESS_CLEAR: - rv = eqdma_hw_context_clear(dev_hndl, c2h, hw_qid); - break; - case QDMA_HW_ACCESS_INVALIDATE: - rv = eqdma_hw_context_invalidate(dev_hndl, c2h, hw_qid); - break; - case QDMA_HW_ACCESS_WRITE: - default: - qdma_log_error("%s: access_type=%d is invalid, err:%d\n", - __func__, access_type, - -QDMA_ERR_INV_PARAM); - rv = -QDMA_ERR_INV_PARAM; - break; - } - - return rv; -} - -/*****************************************************************************/ -/** - * eqdma_credit_context_read() - read credit context - * - * @dev_hndl: device handle - * @c2h: is c2h queue - * @hw_qid: hardware qid of the queue - * @ctxt: pointer to the context data - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -static int eqdma_credit_context_read(void *dev_hndl, uint8_t c2h, - uint16_t hw_qid, - struct qdma_descq_credit_ctxt *ctxt) -{ - int rv = QDMA_SUCCESS; - uint32_t cr_ctxt[EQDMA_CR_CONTEXT_NUM_WORDS] = {0}; - enum ind_ctxt_cmd_sel sel = c2h ? QDMA_CTXT_SEL_CR_C2H : - QDMA_CTXT_SEL_CR_H2C; - - if (!dev_hndl || !ctxt) { - qdma_log_error("%s: dev_hndl=%p credit_ctxt=%p, err:%d\n", - __func__, dev_hndl, ctxt, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - rv = eqdma_indirect_reg_read(dev_hndl, sel, hw_qid, - EQDMA_CR_CONTEXT_NUM_WORDS, cr_ctxt); - if (rv < 0) - return rv; - - ctxt->credit = FIELD_GET(CRED_CTXT_DATA_W0_CREDT_MASK, cr_ctxt[0]); - - qdma_log_debug("%s: credit=%u\n", __func__, ctxt->credit); - - return QDMA_SUCCESS; -} - -/*****************************************************************************/ -/** - * eqdma_credit_context_clear() - clear credit context - * - * @dev_hndl: device handle - * @c2h: is c2h queue - * @hw_qid: hardware qid of the queue - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -static int eqdma_credit_context_clear(void *dev_hndl, uint8_t c2h, - uint16_t hw_qid) -{ - enum ind_ctxt_cmd_sel sel = c2h ? QDMA_CTXT_SEL_CR_C2H : - QDMA_CTXT_SEL_CR_H2C; - - if (!dev_hndl) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", __func__, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - return eqdma_indirect_reg_clear(dev_hndl, sel, hw_qid); -} - -/*****************************************************************************/ -/** - * eqdma_credit_context_invalidate() - invalidate credit context - * - * @dev_hndl: device handle - * @c2h: is c2h queue - * @hw_qid: hardware qid of the queue - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -static int eqdma_credit_context_invalidate(void *dev_hndl, uint8_t c2h, - uint16_t hw_qid) -{ - enum ind_ctxt_cmd_sel sel = c2h ? QDMA_CTXT_SEL_CR_C2H : - QDMA_CTXT_SEL_CR_H2C; - - if (!dev_hndl) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", __func__, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - return eqdma_indirect_reg_invalidate(dev_hndl, sel, hw_qid); -} - -/*****************************************************************************/ -/** - * eqdma_credit_ctx_conf() - configure credit context - * - * @dev_hndl: device handle - * @c2h: is c2h queue - * @hw_qid: hardware qid of the queue - * @ctxt: pointer to the context data - * @access_type HW access type (qdma_hw_access_type enum) value - * QDMA_HW_ACCESS_WRITE Not supported - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -int eqdma_credit_ctx_conf(void *dev_hndl, uint8_t c2h, - uint16_t hw_qid, struct qdma_descq_credit_ctxt *ctxt, - enum qdma_hw_access_type access_type) -{ - int rv = QDMA_SUCCESS; - - /** ctxt requires only H2C-0 or C2H-1 - * return error for any other values - */ - if (c2h > 1) { - qdma_log_error("%s: c2h(%d) invalid, err:%d\n", - __func__, - c2h, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - switch (access_type) { - case QDMA_HW_ACCESS_READ: - rv = eqdma_credit_context_read(dev_hndl, c2h, hw_qid, ctxt); - break; - case QDMA_HW_ACCESS_CLEAR: - rv = eqdma_credit_context_clear(dev_hndl, c2h, hw_qid); - break; - case QDMA_HW_ACCESS_INVALIDATE: - rv = eqdma_credit_context_invalidate(dev_hndl, c2h, hw_qid); - break; - case QDMA_HW_ACCESS_WRITE: - default: - qdma_log_error("%s: Invalid access type=%d, err:%d\n", - __func__, access_type, - -QDMA_ERR_INV_PARAM); - rv = -QDMA_ERR_INV_PARAM; - break; - } - - return rv; -} - - -/*****************************************************************************/ -/** - * eqdma_indirect_intr_context_write() - create indirect interrupt context - * and program it - * - * @dev_hndl: device handle - * @ring_index: indirect interrupt ring index - * @ctxt: pointer to the interrupt context data strucutre - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -static int eqdma_indirect_intr_context_write(void *dev_hndl, - uint16_t ring_index, const struct qdma_indirect_intr_ctxt *ctxt) -{ - uint32_t intr_ctxt[EQDMA_IND_INTR_CONTEXT_NUM_WORDS] = {0}; - enum ind_ctxt_cmd_sel sel = QDMA_CTXT_SEL_INT_COAL; - uint32_t baddr_l, baddr_m, baddr_h, pasid_l, pasid_h; - uint16_t num_words_count = 0; - - if (!dev_hndl || !ctxt) { - qdma_log_error("%s: dev_hndl=%p intr_ctxt=%p, err:%d\n", - __func__, dev_hndl, ctxt, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - baddr_l = (uint32_t)FIELD_GET(QDMA_INTR_CTXT_BADDR_GET_L_MASK, - ctxt->baddr_4k); - baddr_m = (uint32_t)FIELD_GET(QDMA_INTR_CTXT_BADDR_GET_M_MASK, - ctxt->baddr_4k); - baddr_h = (uint32_t)FIELD_GET(QDMA_INTR_CTXT_BADDR_GET_H_MASK, - ctxt->baddr_4k); - - pasid_l = - FIELD_GET(EQDMA_INTR_CTXT_PASID_GET_L_MASK, ctxt->pasid); - pasid_h = - FIELD_GET(EQDMA_INTR_CTXT_PASID_GET_H_MASK, ctxt->pasid); - - intr_ctxt[num_words_count++] = - FIELD_SET(INTR_CTXT_DATA_W0_VALID_MASK, ctxt->valid) | - FIELD_SET(INTR_CTXT_DATA_W0_VEC_MASK, ctxt->vec) | - FIELD_SET(INTR_CTXT_DATA_W0_INT_ST_MASK, ctxt->int_st) | - FIELD_SET(INTR_CTXT_DATA_W0_COLOR_MASK, ctxt->color) | - FIELD_SET(INTR_CTXT_DATA_W0_BADDR_4K_L_MASK, baddr_l); - - intr_ctxt[num_words_count++] = - FIELD_SET(INTR_CTXT_DATA_W1_BADDR_4K_M_MASK, baddr_m); - - intr_ctxt[num_words_count++] = - FIELD_SET(INTR_CTXT_DATA_W2_BADDR_4K_H_MASK, baddr_h) | - FIELD_SET(INTR_CTXT_DATA_W2_PAGE_SIZE_MASK, ctxt->page_size) | - FIELD_SET(INTR_CTXT_DATA_W2_PIDX_MASK, ctxt->pidx) | - FIELD_SET(INTR_CTXT_DATA_W2_AT_MASK, ctxt->at) | - FIELD_SET(INTR_CTXT_DATA_W2_HOST_ID_MASK, ctxt->host_id) | - FIELD_SET(INTR_CTXT_DATA_W2_PASID_L_MASK, pasid_l); - - intr_ctxt[num_words_count++] = - FIELD_SET(INTR_CTXT_DATA_W3_PASID_H_MASK, pasid_h) | - FIELD_SET(INTR_CTXT_DATA_W3_PASID_EN_MASK, ctxt->pasid_en) | - FIELD_SET(INTR_CTXT_DATA_W3_FUNC_MASK, ctxt->func_id); - - return eqdma_indirect_reg_write(dev_hndl, sel, ring_index, - intr_ctxt, num_words_count); -} - -/*****************************************************************************/ -/** - * eqdma_indirect_intr_context_read() - read indirect interrupt context - * - * @dev_hndl: device handle - * @ring_index: indirect interrupt ring index - * @ctxt: pointer to the output context data - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -static int eqdma_indirect_intr_context_read(void *dev_hndl, - uint16_t ring_index, struct qdma_indirect_intr_ctxt *ctxt) -{ - int rv = QDMA_SUCCESS; - uint32_t intr_ctxt[EQDMA_IND_INTR_CONTEXT_NUM_WORDS] = {0}; - enum ind_ctxt_cmd_sel sel = QDMA_CTXT_SEL_INT_COAL; - uint64_t baddr_l, baddr_m, baddr_h, pasid_l, pasid_h; - - if (!dev_hndl || !ctxt) { - qdma_log_error("%s: dev_hndl=%p intr_ctxt=%p, err:%d\n", - __func__, dev_hndl, ctxt, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - rv = eqdma_indirect_reg_read(dev_hndl, sel, ring_index, - EQDMA_IND_INTR_CONTEXT_NUM_WORDS, intr_ctxt); - if (rv < 0) - return rv; - - ctxt->valid = FIELD_GET(INTR_CTXT_DATA_W0_VALID_MASK, intr_ctxt[0]); - ctxt->vec = FIELD_GET(INTR_CTXT_DATA_W0_VEC_MASK, intr_ctxt[0]); - ctxt->int_st = - (uint8_t)(FIELD_GET(INTR_CTXT_DATA_W0_INT_ST_MASK, - intr_ctxt[0])); - ctxt->color = - (uint8_t)(FIELD_GET(INTR_CTXT_DATA_W0_COLOR_MASK, - intr_ctxt[0])); - baddr_l = FIELD_GET(INTR_CTXT_DATA_W0_BADDR_4K_L_MASK, intr_ctxt[0]); - - baddr_m = FIELD_GET(INTR_CTXT_DATA_W1_BADDR_4K_M_MASK, intr_ctxt[1]); - - baddr_h = FIELD_GET(INTR_CTXT_DATA_W2_BADDR_4K_H_MASK, intr_ctxt[2]); - ctxt->page_size = - FIELD_GET(INTR_CTXT_DATA_W2_PAGE_SIZE_MASK, intr_ctxt[2]); - ctxt->pidx = - (uint16_t)(FIELD_GET(INTR_CTXT_DATA_W2_PIDX_MASK, - intr_ctxt[2])); - ctxt->at = - (uint8_t)(FIELD_GET(INTR_CTXT_DATA_W2_AT_MASK, intr_ctxt[2])); - ctxt->host_id = (uint8_t)(FIELD_GET(INTR_CTXT_DATA_W2_HOST_ID_MASK, - intr_ctxt[2])); - pasid_l = (uint8_t)(FIELD_GET(INTR_CTXT_DATA_W2_PASID_L_MASK, - intr_ctxt[2])); - - pasid_h = FIELD_GET(INTR_CTXT_DATA_W3_PASID_H_MASK, intr_ctxt[3]); - ctxt->pasid_en = (uint8_t)FIELD_GET(INTR_CTXT_DATA_W3_PASID_EN_MASK, - intr_ctxt[3]); - - ctxt->func_id = (uint16_t)FIELD_GET(INTR_CTXT_DATA_W3_FUNC_MASK, - intr_ctxt[3]); - - ctxt->baddr_4k = - FIELD_SET(QDMA_INTR_CTXT_BADDR_GET_L_MASK, baddr_l) | - FIELD_SET(QDMA_INTR_CTXT_BADDR_GET_M_MASK, baddr_m) | - FIELD_SET(QDMA_INTR_CTXT_BADDR_GET_H_MASK, baddr_h); - - ctxt->pasid = - FIELD_SET(EQDMA_INTR_CTXT_PASID_GET_L_MASK, pasid_l) | - FIELD_SET(EQDMA_INTR_CTXT_PASID_GET_H_MASK, pasid_h); - - return QDMA_SUCCESS; -} - -/*****************************************************************************/ -/** - * eqdma_indirect_intr_context_clear() - clear indirect interrupt context - * - * @dev_hndl: device handle - * @ring_index: indirect interrupt ring index - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -static int eqdma_indirect_intr_context_clear(void *dev_hndl, - uint16_t ring_index) -{ - enum ind_ctxt_cmd_sel sel = QDMA_CTXT_SEL_INT_COAL; - - if (!dev_hndl) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", __func__, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - return eqdma_indirect_reg_clear(dev_hndl, sel, ring_index); -} - -/*****************************************************************************/ -/** - * eqdma_indirect_intr_context_invalidate() - invalidate indirect interrupt - * context - * - * @dev_hndl: device handle - * @ring_index: indirect interrupt ring index - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -static int eqdma_indirect_intr_context_invalidate(void *dev_hndl, - uint16_t ring_index) -{ - enum ind_ctxt_cmd_sel sel = QDMA_CTXT_SEL_INT_COAL; - - if (!dev_hndl) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", __func__, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - return eqdma_indirect_reg_invalidate(dev_hndl, sel, ring_index); -} - -/*****************************************************************************/ -/** - * eqdma_indirect_intr_ctx_conf() - configure indirect interrupt context - * - * @dev_hndl: device handle - * @ring_index: indirect interrupt ring index - * @ctxt: pointer to context data - * @access_type HW access type (qdma_hw_access_type enum) value - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -int eqdma_indirect_intr_ctx_conf(void *dev_hndl, uint16_t ring_index, - struct qdma_indirect_intr_ctxt *ctxt, - enum qdma_hw_access_type access_type) -{ - int rv = QDMA_SUCCESS; - - switch (access_type) { - case QDMA_HW_ACCESS_READ: - rv = eqdma_indirect_intr_context_read(dev_hndl, ring_index, - ctxt); - break; - case QDMA_HW_ACCESS_WRITE: - rv = eqdma_indirect_intr_context_write(dev_hndl, ring_index, - ctxt); - break; - case QDMA_HW_ACCESS_CLEAR: - rv = eqdma_indirect_intr_context_clear(dev_hndl, - ring_index); - break; - case QDMA_HW_ACCESS_INVALIDATE: - rv = eqdma_indirect_intr_context_invalidate(dev_hndl, - ring_index); - break; - default: - qdma_log_error("%s: access_type=%d is invalid, err:%d\n", - __func__, access_type, - -QDMA_ERR_INV_PARAM); - rv = -QDMA_ERR_INV_PARAM; - break; - } - - return rv; -} - -/*****************************************************************************/ -/** - * eqdma_dump_config_regs() - Function to get qdma config register dump in a - * buffer - * - * @dev_hndl: device handle - * @is_vf: Whether PF or VF - * @buf : pointer to buffer to be filled - * @buflen : Length of the buffer - * - * Return: Length up-till the buffer is filled -success and < 0 - failure - *****************************************************************************/ -int eqdma_dump_config_regs(void *dev_hndl, uint8_t is_vf, - char *buf, uint32_t buflen) -{ - uint32_t i = 0, j = 0; - struct xreg_info *reg_info; - uint32_t num_regs = eqdma_config_num_regs_get(); - uint32_t len = 0, val = 0; - int rv = QDMA_SUCCESS; - char name[DEBGFS_GEN_NAME_SZ] = ""; - struct qdma_dev_attributes dev_cap; - - if (!dev_hndl) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - if (buflen < eqdma_reg_dump_buf_len()) { - qdma_log_error("%s: Buffer too small, err:%d\n", - __func__, -QDMA_ERR_NO_MEM); - return -QDMA_ERR_NO_MEM; - } - - if (is_vf) { - qdma_log_error("%s: Wrong API used for VF, err:%d\n", - __func__, - -QDMA_ERR_HWACC_FEATURE_NOT_SUPPORTED); - return -QDMA_ERR_HWACC_FEATURE_NOT_SUPPORTED; - } - - eqdma_get_device_attributes(dev_hndl, &dev_cap); - - reg_info = eqdma_config_regs_get(); - - for (i = 0; i < num_regs; i++) { - if ((GET_CAPABILITY_MASK(dev_cap.mm_en, dev_cap.st_en, - dev_cap.mm_cmpt_en, dev_cap.mailbox_en) - & reg_info[i].mode) == 0) - continue; - - /* If Debug Mode not enabled and the current register - * is debug register, skip reading it. - */ - if (dev_cap.debug_mode == 0 && - reg_info[i].is_debug_reg == 1) - continue; - - for (j = 0; j < reg_info[i].repeat; j++) { - rv = QDMA_SNPRINTF_S(name, DEBGFS_GEN_NAME_SZ, - DEBGFS_GEN_NAME_SZ, - "%s", reg_info[i].name); - if ((rv < 0) || (rv > DEBGFS_GEN_NAME_SZ)) { - qdma_log_error( - "%d:%s QDMA_SNPRINTF_S() failed, err:%d\n", - __LINE__, __func__, - rv); - return -QDMA_ERR_NO_MEM; - } - val = qdma_reg_read(dev_hndl, - (reg_info[i].addr + (j * 4))); - rv = dump_reg(buf + len, buflen - len, - (reg_info[i].addr + (j * 4)), - name, val); - if (rv < 0) { - qdma_log_error( - "%s Buff too small, err:%d\n", - __func__, - -QDMA_ERR_NO_MEM); - return -QDMA_ERR_NO_MEM; - } - len += rv; - } - } - - return len; -} - -/*****************************************************************************/ -/** - * qdma_dump_cpm_queue_context() - Function to get qdma queue context dump - * in a buffer - * - * @dev_hndl: device handle - * @st: Queue Mode(ST or MM) - * @q_type: Queue type(H2C/C2H/CMPT) - * @context: Queue Context - * @buf : pointer to buffer to be filled - * @buflen : Length of the buffer - * - * Return: Length up-till the buffer is filled -success and < 0 - failure - *****************************************************************************/ -int eqdma_dump_queue_context(void *dev_hndl, - uint8_t st, - enum qdma_dev_q_type q_type, - struct qdma_descq_context *ctxt_data, - char *buf, uint32_t buflen) -{ - int rv = 0; - uint32_t req_buflen = 0; - - if (!dev_hndl) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - - return -QDMA_ERR_INV_PARAM; - } - - if (!ctxt_data) { - qdma_log_error("%s: ctxt_data is NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - - return -QDMA_ERR_INV_PARAM; - } - - if (!buf) { - qdma_log_error("%s: buf is NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - - return -QDMA_ERR_INV_PARAM; - } - - if (q_type >= QDMA_DEV_Q_TYPE_MAX) { - qdma_log_error("%s: invalid q_type, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - - return -QDMA_ERR_INV_PARAM; - } - - rv = eqdma_context_buf_len(st, q_type, &req_buflen); - if (rv != QDMA_SUCCESS) - return rv; - - if (buflen < req_buflen) { - qdma_log_error("%s: Too small buffer(%d), reqd(%d), err:%d\n", - __func__, buflen, req_buflen, -QDMA_ERR_NO_MEM); - return -QDMA_ERR_NO_MEM; - } - - rv = dump_eqdma_context(ctxt_data, st, q_type, - buf, buflen); - - return rv; -} - -/*****************************************************************************/ -/** - * eqdma_dump_intr_context() - Function to get qdma interrupt context dump - * in a buffer - * - * @dev_hndl: device handle - * @intr_ctx: Interrupt Context - * @ring_index: Ring index - * @buf : pointer to buffer to be filled - * @buflen : Length of the buffer - * - * Return: Length up-till the buffer is filled -success and < 0 - failure - *****************************************************************************/ -int eqdma_dump_intr_context(void *dev_hndl, - struct qdma_indirect_intr_ctxt *intr_ctx, - int ring_index, - char *buf, uint32_t buflen) -{ - int rv = 0; - uint32_t req_buflen = 0; - - if (!dev_hndl) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - - return -QDMA_ERR_INV_PARAM; - } - if (!intr_ctx) { - qdma_log_error("%s: intr_ctx is NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - if (!buf) { - qdma_log_error("%s: buf is NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - req_buflen = eqdma_intr_context_buf_len(); - if (buflen < req_buflen) { - qdma_log_error("%s: Too small buffer(%d), reqd(%d), err:%d\n", - __func__, buflen, req_buflen, -QDMA_ERR_NO_MEM); - return -QDMA_ERR_NO_MEM; - } - - rv = dump_eqdma_intr_context(intr_ctx, ring_index, buf, buflen); - - return rv; -} - -/*****************************************************************************/ -/** - * eqdma_read_dump_queue_context() - Function to read and dump the queue - * context in a buffer - * - * @dev_hndl: device handle - * @hw_qid: queue id - * @st: Queue Mode(ST or MM) - * @q_type: Queue type(H2C/C2H/CMPT) - * @buf : pointer to buffer to be filled - * @buflen : Length of the buffer - * - * Return: Length up-till the buffer is filled -success and < 0 - failure - *****************************************************************************/ -int eqdma_read_dump_queue_context(void *dev_hndl, - uint16_t qid_hw, - uint8_t st, - enum qdma_dev_q_type q_type, - char *buf, uint32_t buflen) -{ - int rv = QDMA_SUCCESS; - uint32_t req_buflen = 0; - struct qdma_descq_context context; - - if (!dev_hndl) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - - return -QDMA_ERR_INV_PARAM; - } - - if (!buf) { - qdma_log_error("%s: buf is NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - - return -QDMA_ERR_INV_PARAM; - } - - if (q_type >= QDMA_DEV_Q_TYPE_MAX) { - qdma_log_error("%s: Not supported for q_type, err = %d\n", - __func__, -QDMA_ERR_INV_PARAM); - - return -QDMA_ERR_INV_PARAM; - } - - rv = eqdma_context_buf_len(st, q_type, &req_buflen); - if (rv != QDMA_SUCCESS) - return rv; - - if (buflen < req_buflen) { - qdma_log_error("%s: Too small buffer(%d), reqd(%d), err:%d\n", - __func__, buflen, req_buflen, -QDMA_ERR_NO_MEM); - return -QDMA_ERR_NO_MEM; - } - - qdma_memset(&context, 0, sizeof(struct qdma_descq_context)); - - if (q_type != QDMA_DEV_Q_TYPE_CMPT) { - rv = eqdma_sw_ctx_conf(dev_hndl, (uint8_t)q_type, qid_hw, - &(context.sw_ctxt), QDMA_HW_ACCESS_READ); - if (rv < 0) { - qdma_log_error( - "%s: Failed to read sw context, err = %d", - __func__, rv); - return rv; - } - - rv = eqdma_hw_ctx_conf(dev_hndl, (uint8_t)q_type, qid_hw, - &(context.hw_ctxt), QDMA_HW_ACCESS_READ); - if (rv < 0) { - qdma_log_error( - "%s: Failed to read hw context, err = %d", - __func__, rv); - return rv; - } - - rv = eqdma_credit_ctx_conf(dev_hndl, (uint8_t)q_type, - qid_hw, &(context.cr_ctxt), - QDMA_HW_ACCESS_READ); - if (rv < 0) { - qdma_log_error( - "%s: Failed to read credit context, err = %d", - __func__, rv); - return rv; - } - - if (st && (q_type == QDMA_DEV_Q_TYPE_C2H)) { - rv = eqdma_pfetch_ctx_conf(dev_hndl, - qid_hw, - &(context.pfetch_ctxt), - QDMA_HW_ACCESS_READ); - if (rv < 0) { - qdma_log_error( - "%s: Failed to read pftech context, err = %d", - __func__, rv); - return rv; - } - } - } - - if ((st && (q_type == QDMA_DEV_Q_TYPE_C2H)) || - (!st && (q_type == QDMA_DEV_Q_TYPE_CMPT))) { - rv = eqdma_cmpt_ctx_conf(dev_hndl, qid_hw, - &(context.cmpt_ctxt), - QDMA_HW_ACCESS_READ); - if (rv < 0) { - qdma_log_error( - "%s: Failed to read cmpt context, err = %d", - __func__, rv); - return rv; - } - } - - - rv = dump_eqdma_context(&context, st, q_type, - buf, buflen); - - return rv; -} - -/*****************************************************************************/ -/** - * eqdma_get_user_bar() - Function to get the AXI Master Lite(user bar) number - * - * @dev_hndl: device handle - * @is_vf: Whether PF or VF - * @func_id: function id of the PF - * @user_bar: pointer to hold the AXI Master Lite bar number - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -int eqdma_get_user_bar(void *dev_hndl, uint8_t is_vf, - uint8_t func_id, uint8_t *user_bar) -{ - uint8_t bar_found = 0; - uint8_t bar_idx = 0; - uint32_t user_bar_id = 0; - uint32_t reg_addr = (is_vf) ? EQDMA_OFFSET_VF_USER_BAR : - EQDMA_OFFSET_GLBL2_PF_BARLITE_EXT; - - if (!dev_hndl) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - if (!user_bar) { - qdma_log_error("%s: AXI Master Lite bar is NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - user_bar_id = qdma_reg_read(dev_hndl, reg_addr); - user_bar_id = (user_bar_id >> (6 * func_id)) & 0x3F; - - for (bar_idx = 0; bar_idx < QDMA_BAR_NUM; bar_idx++) { - if (user_bar_id & (1 << bar_idx)) { - *user_bar = bar_idx; - bar_found = 1; - break; - } - } - if (bar_found == 0) { - *user_bar = 0; - qdma_log_error("%s: Bar not found, err:%d\n", - __func__, - -QDMA_ERR_HWACC_BAR_NOT_FOUND); - return -QDMA_ERR_HWACC_BAR_NOT_FOUND; - } - - return QDMA_SUCCESS; -} - -/*****************************************************************************/ -/** - * eqdma_hw_ram_sbe_err_process() - Function to dump SBE error debug information - * - * @dev_hndl: device handle - * @buf: Bufffer for the debug info to be dumped in - * @buflen: Length of the buffer - * - * Return: void - *****************************************************************************/ -static void eqdma_hw_ram_sbe_err_process(void *dev_hndl) -{ - eqdma_dump_reg_info(dev_hndl, EQDMA_RAM_SBE_STS_A_ADDR, - 1, NULL, 0); - eqdma_dump_reg_info(dev_hndl, EQDMA_RAM_SBE_STS_1_A_ADDR, - 1, NULL, 0); -} - -/*****************************************************************************/ -/** - * eqdma_hw_ram_dbe_err_process() - Function to dump DBE error debug information - * - * @dev_hndl: device handle - * @buf: Bufffer for the debug info to be dumped in - * @buflen: Length of the buffer - * - * Return: void - *****************************************************************************/ -static void eqdma_hw_ram_dbe_err_process(void *dev_hndl) -{ - eqdma_dump_reg_info(dev_hndl, EQDMA_RAM_DBE_STS_A_ADDR, - 1, NULL, 0); - eqdma_dump_reg_info(dev_hndl, EQDMA_RAM_DBE_STS_1_A_ADDR, - 1, NULL, 0); -} - -/*****************************************************************************/ -/** - * eqdma_hw_desc_err_process() - Function to dump Descriptor Error information - * - * @dev_hndl: device handle - * @buf: Bufffer for the debug info to be dumped in - * @buflen: Length of the buffer - * - * Return: void - *****************************************************************************/ -static void eqdma_hw_desc_err_process(void *dev_hndl) -{ - int i = 0; - uint32_t desc_err_reg_list[] = { - EQDMA_GLBL_DSC_ERR_STS_ADDR, - EQDMA_GLBL_DSC_ERR_LOG0_ADDR, - EQDMA_GLBL_DSC_ERR_LOG1_ADDR, - EQDMA_GLBL_DSC_DBG_DAT0_ADDR, - EQDMA_GLBL_DSC_DBG_DAT1_ADDR, - EQDMA_GLBL_DSC_ERR_LOG2_ADDR - }; - int desc_err_num_regs = sizeof(desc_err_reg_list)/sizeof(uint32_t); - - for (i = 0; i < desc_err_num_regs; i++) { - eqdma_dump_reg_info(dev_hndl, desc_err_reg_list[i], - 1, NULL, 0); - } -} - -/*****************************************************************************/ -/** - * eqdma_hw_trq_err_process() - Function to dump Target Access Error information - * - * @dev_hndl: device handle - * @buf: Bufffer for the debug info to be dumped in - * @buflen: Length of the buffer - * - * Return: void - *****************************************************************************/ -static void eqdma_hw_trq_err_process(void *dev_hndl) -{ - int i = 0; - uint32_t trq_err_reg_list[] = { - EQDMA_GLBL_TRQ_ERR_STS_ADDR, - EQDMA_GLBL_TRQ_ERR_LOG_ADDR - }; - int trq_err_reg_num_regs = sizeof(trq_err_reg_list)/sizeof(uint32_t); - - for (i = 0; i < trq_err_reg_num_regs; i++) { - eqdma_dump_reg_info(dev_hndl, trq_err_reg_list[i], - 1, NULL, 0); - } -} - -/*****************************************************************************/ -/** - * eqdma_hw_st_h2c_err_process() - Function to dump MM H2C Error information - * - * @dev_hndl: device handle - * @buf: Bufffer for the debug info to be dumped in - * @buflen: Length of the buffer - * - * Return: void - *****************************************************************************/ -static void eqdma_hw_st_h2c_err_process(void *dev_hndl) -{ - int i = 0; - uint32_t st_h2c_err_reg_list[] = { - EQDMA_H2C_ERR_STAT_ADDR, - EQDMA_H2C_FIRST_ERR_QID_ADDR, - EQDMA_H2C_DBG_REG0_ADDR, - EQDMA_H2C_DBG_REG1_ADDR, - EQDMA_H2C_DBG_REG2_ADDR, - EQDMA_H2C_DBG_REG3_ADDR, - EQDMA_H2C_DBG_REG4_ADDR - }; - int st_h2c_err_num_regs = sizeof(st_h2c_err_reg_list)/sizeof(uint32_t); - - for (i = 0; i < st_h2c_err_num_regs; i++) { - eqdma_dump_reg_info(dev_hndl, st_h2c_err_reg_list[i], - 1, NULL, 0); - } -} - - -/*****************************************************************************/ -/** - * eqdma_hw_st_c2h_err_process() - Function to dump MM H2C Error information - * - * @dev_hndl: device handle - * @buf: Bufffer for the debug info to be dumped in - * @buflen: Length of the buffer - * - * Return: void - *****************************************************************************/ -static void eqdma_hw_st_c2h_err_process(void *dev_hndl) -{ - int i = 0; - uint32_t st_c2h_err_reg_list[] = { - EQDMA_C2H_ERR_STAT_ADDR, - EQDMA_C2H_FATAL_ERR_STAT_ADDR, - EQDMA_C2H_FIRST_ERR_QID_ADDR, - EQDMA_C2H_STAT_S_AXIS_C2H_ACCEPTED_ADDR, - EQDMA_C2H_STAT_S_AXIS_WRB_ACCEPTED_ADDR, - EQDMA_C2H_STAT_DESC_RSP_PKT_ACCEPTED_ADDR, - EQDMA_C2H_STAT_AXIS_PKG_CMP_ADDR, - EQDMA_C2H_STAT_DBG_DMA_ENG_0_ADDR, - EQDMA_C2H_STAT_DBG_DMA_ENG_1_ADDR, - EQDMA_C2H_STAT_DBG_DMA_ENG_2_ADDR, - EQDMA_C2H_STAT_DBG_DMA_ENG_3_ADDR, - EQDMA_C2H_STAT_DESC_RSP_DROP_ACCEPTED_ADDR, - EQDMA_C2H_STAT_DESC_RSP_ERR_ACCEPTED_ADDR - }; - int st_c2h_err_num_regs = sizeof(st_c2h_err_reg_list)/sizeof(uint32_t); - - for (i = 0; i < st_c2h_err_num_regs; i++) { - eqdma_dump_reg_info(dev_hndl, st_c2h_err_reg_list[i], - 1, NULL, 0); - } -} - - - -/*****************************************************************************/ -/** - * eqdma_hw_get_error_name() - Function to get the error in string format - * - * @err_idx: error index - * - * Return: string - success and NULL on failure - *****************************************************************************/ -const char *eqdma_hw_get_error_name(uint32_t err_idx) -{ - if (err_idx >= EQDMA_ERRS_ALL) { - qdma_log_error("%s: err_idx=%d is invalid, returning NULL\n", - __func__, (enum eqdma_error_idx)err_idx); - return NULL; - } - - return eqdma_err_info[(enum eqdma_error_idx)err_idx].err_name; -} - -/*****************************************************************************/ -/** - * eqdma_hw_error_process() - Function to find the error that got - * triggered and call the handler qdma_hw_error_handler of that - * particular error. - * - * @dev_hndl: device handle - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -int eqdma_hw_error_process(void *dev_hndl) -{ - uint32_t glbl_err_stat = 0, err_stat = 0; - uint32_t bit = 0, i = 0; - int32_t idx = 0; - struct qdma_dev_attributes dev_cap; - uint32_t hw_err_position[EQDMA_TOTAL_LEAF_ERROR_AGGREGATORS] = { - EQDMA_DSC_ERR_POISON, - EQDMA_TRQ_ERR_CSR_UNMAPPED, - EQDMA_ST_C2H_ERR_MTY_MISMATCH, - EQDMA_ST_FATAL_ERR_MTY_MISMATCH, - EQDMA_ST_H2C_ERR_ZERO_LEN_DESC, - EQDMA_SBE_1_ERR_RC_RRQ_EVEN_RAM, - EQDMA_SBE_ERR_MI_H2C0_DAT, - EQDMA_DBE_1_ERR_RC_RRQ_EVEN_RAM, - EQDMA_DBE_ERR_MI_H2C0_DAT - }; - - if (!dev_hndl) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - - eqdma_get_device_attributes(dev_hndl, &dev_cap); - - glbl_err_stat = qdma_reg_read(dev_hndl, EQDMA_GLBL_ERR_STAT_ADDR); - - if (!glbl_err_stat) - return QDMA_HW_ERR_NOT_DETECTED; - - - qdma_log_info("%s: Global Err Reg(0x%x) = 0x%x\n", - __func__, EQDMA_GLBL_ERR_STAT_ADDR, - glbl_err_stat); - - for (i = 0; i < EQDMA_TOTAL_LEAF_ERROR_AGGREGATORS; i++) { - bit = hw_err_position[i]; - - if ((!dev_cap.st_en) && (bit == EQDMA_ST_C2H_ERR_MTY_MISMATCH || - bit == EQDMA_ST_FATAL_ERR_MTY_MISMATCH || - bit == EQDMA_ST_H2C_ERR_ZERO_LEN_DESC)) - continue; - - err_stat = qdma_reg_read(dev_hndl, - eqdma_err_info[bit].stat_reg_addr); - if (err_stat) { - qdma_log_info("addr = 0x%08x val = 0x%08x", - eqdma_err_info[bit].stat_reg_addr, - err_stat); - - eqdma_err_info[bit].eqdma_hw_err_process( - dev_hndl); - for (idx = bit; idx < all_eqdma_hw_errs[i]; idx++) { - /* call the platform specific handler */ - if (err_stat & - eqdma_err_info[idx].leaf_err_mask) - qdma_log_error("%s detected %s\n", - __func__, - eqdma_hw_get_error_name(idx)); - } - qdma_reg_write(dev_hndl, - eqdma_err_info[bit].stat_reg_addr, - err_stat); - } - - } - - /* Write 1 to the global status register to clear the bits */ - qdma_reg_write(dev_hndl, EQDMA_GLBL_ERR_STAT_ADDR, glbl_err_stat); - - return QDMA_SUCCESS; -} - -/*****************************************************************************/ -/** - * qdma_hw_error_enable() - Function to enable all or a specific error - * - * @dev_hndl: device handle - * @err_idx: error index - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -int eqdma_hw_error_enable(void *dev_hndl, uint32_t err_idx) -{ - uint32_t idx = 0, i = 0; - uint32_t reg_val = 0; - struct qdma_dev_attributes dev_cap; - - if (!dev_hndl) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - if (err_idx > EQDMA_ERRS_ALL) { - qdma_log_error("%s: err_idx=%d is invalid, err:%d\n", - __func__, (enum eqdma_error_idx)err_idx, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - eqdma_get_device_attributes(dev_hndl, &dev_cap); - - if (err_idx == EQDMA_ERRS_ALL) { - for (i = 0; i < EQDMA_TOTAL_LEAF_ERROR_AGGREGATORS; i++) { - - idx = all_eqdma_hw_errs[i]; - - /* Don't access streaming registers in - * MM only bitstreams - */ - if (!dev_cap.st_en) { - if (idx == EQDMA_ST_C2H_ERR_ALL || - idx == EQDMA_ST_FATAL_ERR_ALL || - idx == EQDMA_ST_H2C_ERR_ALL) - continue; - } - - reg_val = eqdma_err_info[idx].leaf_err_mask; - qdma_reg_write(dev_hndl, - eqdma_err_info[idx].mask_reg_addr, reg_val); - - reg_val = qdma_reg_read(dev_hndl, - EQDMA_GLBL_ERR_MASK_ADDR); - reg_val |= FIELD_SET( - eqdma_err_info[idx].global_err_mask, 1); - qdma_reg_write(dev_hndl, EQDMA_GLBL_ERR_MASK_ADDR, - reg_val); - } - - } else { - /* Don't access streaming registers in MM only bitstreams - * QDMA_C2H_ERR_MTY_MISMATCH to QDMA_H2C_ERR_ALL are all - * ST errors - */ - if (!dev_cap.st_en) { - if (err_idx >= EQDMA_ST_C2H_ERR_MTY_MISMATCH && - err_idx <= EQDMA_ST_H2C_ERR_ALL) - return QDMA_SUCCESS; - } - - reg_val = qdma_reg_read(dev_hndl, - eqdma_err_info[err_idx].mask_reg_addr); - reg_val |= FIELD_SET(eqdma_err_info[err_idx].leaf_err_mask, 1); - qdma_reg_write(dev_hndl, - eqdma_err_info[err_idx].mask_reg_addr, reg_val); - - reg_val = qdma_reg_read(dev_hndl, EQDMA_GLBL_ERR_MASK_ADDR); - reg_val |= - FIELD_SET(eqdma_err_info[err_idx].global_err_mask, 1); - qdma_reg_write(dev_hndl, EQDMA_GLBL_ERR_MASK_ADDR, reg_val); - } - - return QDMA_SUCCESS; -} - -/*****************************************************************************/ -/** - * eqdma_get_device_attributes() - Function to get the qdma device - * attributes - * - * @dev_hndl: device handle - * @dev_info: pointer to hold the device info - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -int eqdma_get_device_attributes(void *dev_hndl, - struct qdma_dev_attributes *dev_info) -{ - uint8_t count = 0; - uint32_t reg_val = 0; - - if (!dev_hndl) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - if (!dev_info) { - qdma_log_error("%s: dev_info is NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - /* number of PFs */ - reg_val = qdma_reg_read(dev_hndl, QDMA_OFFSET_GLBL2_PF_BARLITE_INT); - if (FIELD_GET(QDMA_GLBL2_PF0_BAR_MAP_MASK, reg_val)) - count++; - if (FIELD_GET(QDMA_GLBL2_PF1_BAR_MAP_MASK, reg_val)) - count++; - if (FIELD_GET(QDMA_GLBL2_PF2_BAR_MAP_MASK, reg_val)) - count++; - if (FIELD_GET(QDMA_GLBL2_PF3_BAR_MAP_MASK, reg_val)) - count++; - dev_info->num_pfs = count; - - /* Number of Qs */ - reg_val = qdma_reg_read(dev_hndl, EQDMA_GLBL2_CHANNEL_CAP_ADDR); - dev_info->num_qs = - FIELD_GET(GLBL2_CHANNEL_CAP_MULTIQ_MAX_MASK, reg_val); - - /* FLR present */ - reg_val = qdma_reg_read(dev_hndl, EQDMA_GLBL2_MISC_CAP_ADDR); - dev_info->mailbox_en = FIELD_GET(EQDMA_GLBL2_MAILBOX_EN_MASK, - reg_val); - dev_info->flr_present = FIELD_GET(EQDMA_GLBL2_FLR_PRESENT_MASK, - reg_val); - dev_info->mm_cmpt_en = 0; - dev_info->debug_mode = FIELD_GET(EQDMA_GLBL2_DBG_MODE_EN_MASK, - reg_val); - dev_info->desc_eng_mode = FIELD_GET(EQDMA_GLBL2_DESC_ENG_MODE_MASK, - reg_val); - - /* ST/MM enabled? */ - reg_val = qdma_reg_read(dev_hndl, EQDMA_GLBL2_CHANNEL_MDMA_ADDR); - dev_info->st_en = (FIELD_GET(GLBL2_CHANNEL_MDMA_C2H_ST_MASK, reg_val) - && FIELD_GET(GLBL2_CHANNEL_MDMA_H2C_ST_MASK, reg_val)) ? 1 : 0; - dev_info->mm_en = (FIELD_GET(GLBL2_CHANNEL_MDMA_C2H_ENG_MASK, reg_val) - && FIELD_GET(GLBL2_CHANNEL_MDMA_H2C_ENG_MASK, reg_val)) ? 1 : 0; - - /* num of mm channels */ - /* TODO : Register not yet defined for this. Hard coding it to 1.*/ - dev_info->mm_channel_max = 1; - - dev_info->qid2vec_ctx = 0; - dev_info->cmpt_ovf_chk_dis = 1; - dev_info->mailbox_intr = 1; - dev_info->sw_desc_64b = 1; - dev_info->cmpt_desc_64b = 1; - dev_info->dynamic_bar = 1; - dev_info->legacy_intr = 1; - dev_info->cmpt_trig_count_timer = 1; - - return QDMA_SUCCESS; -} - -/*****************************************************************************/ -/** - * eqdma_init_ctxt_memory() - function to initialize the context memory - * - * @dev_hndl: device handle - * - * Return: returns the platform specific error code - *****************************************************************************/ -int eqdma_init_ctxt_memory(void *dev_hndl) -{ -#ifdef ENABLE_INIT_CTXT_MEMORY - uint32_t data[QDMA_REG_IND_CTXT_REG_COUNT]; - uint16_t i = 0; - struct qdma_dev_attributes dev_info; - - if (!dev_hndl) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - qdma_memset(data, 0, sizeof(uint32_t) * QDMA_REG_IND_CTXT_REG_COUNT); - eqdma_get_device_attributes(dev_hndl, &dev_info); - - for (; i < dev_info.num_qs; i++) { - int sel = QDMA_CTXT_SEL_SW_C2H; - int rv; - - for (; sel <= QDMA_CTXT_SEL_PFTCH; sel++) { - /** if the st mode(h2c/c2h) not enabled - * in the design, then skip the PFTCH - * and CMPT context setup - */ - if ((dev_info.st_en == 0) && - ((sel == QDMA_CTXT_SEL_PFTCH) || - (sel == QDMA_CTXT_SEL_CMPT))) { - qdma_log_debug("%s: ST context is skipped:", - __func__); - qdma_log_debug("sel = %d\n", sel); - continue; - } - - rv = eqdma_indirect_reg_clear(dev_hndl, - (enum ind_ctxt_cmd_sel)sel, i); - if (rv < 0) - return rv; - } - } - - /* fmap */ - for (i = 0; i < dev_info.num_pfs; i++) - eqdma_indirect_reg_clear(dev_hndl, - QDMA_CTXT_SEL_FMAP, i); - -#else - if (!dev_hndl) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } -#endif - return QDMA_SUCCESS; - -} - - -static int get_reg_entry(uint32_t reg_addr, int *reg_entry) -{ - uint32_t i = 0; - struct xreg_info *reg_info; - uint32_t num_regs = eqdma_config_num_regs_get(); - - reg_info = eqdma_config_regs_get(); - - for (i = 0; (i < num_regs - 1); i++) { - if (reg_info[i].addr == reg_addr) { - *reg_entry = i; - break; - } - } - - if (i >= num_regs - 1) { - qdma_log_error("%s: 0x%08x is missing register list, err:%d\n", - __func__, - reg_addr, - -QDMA_ERR_INV_PARAM); - *reg_entry = -1; - return -QDMA_ERR_INV_PARAM; - } - - return 0; -} - -/*****************************************************************************/ -/** - * eqdma_dump_config_reg_list() - Dump the registers - * - * @dev_hndl: device handle - * @total_regs : Max registers to read - * @reg_list : array of reg addr and reg values - * @buf : pointer to buffer to be filled - * @buflen : Length of the buffer - * - * Return: returns the platform specific error code - *****************************************************************************/ -int eqdma_dump_config_reg_list(void *dev_hndl, uint32_t total_regs, - struct qdma_reg_data *reg_list, char *buf, uint32_t buflen) -{ - uint32_t j = 0, len = 0; - uint32_t reg_count = 0; - int reg_data_entry; - int rv = 0; - char name[DEBGFS_GEN_NAME_SZ] = ""; - struct xreg_info *reg_info = eqdma_config_regs_get(); - struct qdma_dev_attributes dev_cap; - - if (!dev_hndl) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - if (!buf) { - qdma_log_error("%s: buf is NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - eqdma_get_device_attributes(dev_hndl, &dev_cap); - - for (reg_count = 0; - (reg_count < total_regs);) { - - /* If Debug Mode not enabled and the current register - * is debug register, skip reading it. - */ - if (dev_cap.debug_mode == 0 && - reg_info[reg_count].is_debug_reg == 1) - continue; - - rv = get_reg_entry(reg_list[reg_count].reg_addr, - ®_data_entry); - if (rv < 0) { - qdma_log_error("%s: register missing in list, err:%d\n", - __func__, - -QDMA_ERR_INV_PARAM); - return rv; - } - - for (j = 0; j < reg_info[reg_data_entry].repeat; j++) { - rv = QDMA_SNPRINTF_S(name, DEBGFS_GEN_NAME_SZ, - DEBGFS_GEN_NAME_SZ, - "%s_%d", - reg_info[reg_data_entry].name, j); - if ((rv < 0) || (rv > DEBGFS_GEN_NAME_SZ)) { - qdma_log_error( - "%d:%s snprintf failed, err:%d\n", - __LINE__, __func__, - rv); - return -QDMA_ERR_NO_MEM; - } - rv = dump_reg(buf + len, buflen - len, - (reg_info[reg_data_entry].addr + (j * 4)), - name, - reg_list[reg_count + j].reg_val); - if (rv < 0) { - qdma_log_error( - "%s Buff too small, err:%d\n", - __func__, - -QDMA_ERR_NO_MEM); - return -QDMA_ERR_NO_MEM; - } - len += rv; - } - reg_count += j; - } - - return len; - -} - - -/*****************************************************************************/ -/** - * qdma_read_reg_list() - read the register values - * - * @dev_hndl: device handle - * @is_vf: Whether PF or VF - * @total_regs : Max registers to read - * @reg_list : array of reg addr and reg values - * - * Return: returns the platform specific error code - *****************************************************************************/ -int eqdma_read_reg_list(void *dev_hndl, uint8_t is_vf, - uint16_t reg_rd_group, - uint16_t *total_regs, - struct qdma_reg_data *reg_list) -{ - uint16_t reg_count = 0, i = 0, j = 0; - struct xreg_info *reg_info; - uint32_t num_regs = eqdma_config_num_regs_get(); - struct xreg_info *eqdma_config_regs = eqdma_config_regs_get(); - struct qdma_dev_attributes dev_cap; - uint32_t reg_start_addr = 0; - int reg_index = 0; - int rv = 0; - - if (!is_vf) { - qdma_log_error("%s: not supported for PF, err:%d\n", - __func__, - -QDMA_ERR_HWACC_FEATURE_NOT_SUPPORTED); - return -QDMA_ERR_HWACC_FEATURE_NOT_SUPPORTED; - } - - if (!dev_hndl) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - if (!reg_list) { - qdma_log_error("%s: reg_list is NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - eqdma_get_device_attributes(dev_hndl, &dev_cap); - - switch (reg_rd_group) { - case QDMA_REG_READ_GROUP_1: - reg_start_addr = EQDMA_REG_GROUP_1_START_ADDR; - break; - case QDMA_REG_READ_GROUP_2: - reg_start_addr = EQDMA_REG_GROUP_2_START_ADDR; - break; - case QDMA_REG_READ_GROUP_3: - reg_start_addr = EQDMA_REG_GROUP_3_START_ADDR; - break; - case QDMA_REG_READ_GROUP_4: - reg_start_addr = EQDMA_REG_GROUP_4_START_ADDR; - break; - default: - qdma_log_error("%s: Invalid slot received\n", - __func__); - return -QDMA_ERR_INV_PARAM; - } - - rv = get_reg_entry(reg_start_addr, ®_index); - if (rv < 0) { - qdma_log_error("%s: register missing in list, err:%d\n", - __func__, - -QDMA_ERR_INV_PARAM); - return rv; - } - reg_info = &eqdma_config_regs[reg_index]; - - for (i = 0, reg_count = 0; - ((i < num_regs - 1 - reg_index) && - (reg_count < QDMA_MAX_REGISTER_DUMP)); i++) { - - if (((GET_CAPABILITY_MASK(dev_cap.mm_en, dev_cap.st_en, - dev_cap.mm_cmpt_en, dev_cap.mailbox_en) - & reg_info[i].mode) == 0) || - (reg_info[i].read_type == QDMA_REG_READ_PF_ONLY)) - continue; - - /* If Debug Mode not enabled and the current register - * is debug register, skip reading it. - */ - if (dev_cap.debug_mode == 0 && - reg_info[i].is_debug_reg == 1) - continue; - - for (j = 0; j < reg_info[i].repeat && - (reg_count < QDMA_MAX_REGISTER_DUMP); - j++) { - reg_list[reg_count].reg_addr = - (reg_info[i].addr + (j * 4)); - reg_list[reg_count].reg_val = - qdma_reg_read(dev_hndl, - reg_list[reg_count].reg_addr); - reg_count++; - } - } - - *total_regs = reg_count; - return rv; -} - -/*****************************************************************************/ -/** - * eqdma_write_global_ring_sizes() - function to set the global ring size array - * - * @dev_hndl: device handle - * @index: Index from where the values needs to written - * @count: number of entries to be written - * @glbl_rng_sz: pointer to the array having the values to write - * - * (index + count) shall not be more than 16 - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -static int eqdma_write_global_ring_sizes(void *dev_hndl, uint8_t index, - uint8_t count, const uint32_t *glbl_rng_sz) -{ - if (!dev_hndl || !glbl_rng_sz || !count) { - qdma_log_error("%s: dev_hndl=%p glbl_rng_sz=%p, err:%d\n", - __func__, dev_hndl, glbl_rng_sz, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - if ((index + count) > QDMA_NUM_RING_SIZES) { - qdma_log_error("%s: index=%u count=%u > %d, err:%d\n", - __func__, index, count, - QDMA_NUM_RING_SIZES, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - qdma_write_csr_values(dev_hndl, EQDMA_GLBL_RNG_SZ_1_ADDR, index, count, - glbl_rng_sz); - - return QDMA_SUCCESS; -} - -/*****************************************************************************/ -/** - * eqdma_read_global_ring_sizes() - function to get the global rng_sz array - * - * @dev_hndl: device handle - * @index: Index from where the values needs to read - * @count: number of entries to be read - * @glbl_rng_sz: pointer to array to hold the values read - * - * (index + count) shall not be more than 16 - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -static int eqdma_read_global_ring_sizes(void *dev_hndl, uint8_t index, - uint8_t count, uint32_t *glbl_rng_sz) -{ - if (!dev_hndl || !glbl_rng_sz || !count) { - qdma_log_error("%s: dev_hndl=%p glbl_rng_sz=%p, err:%d\n", - __func__, dev_hndl, glbl_rng_sz, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - if ((index + count) > QDMA_NUM_RING_SIZES) { - qdma_log_error("%s: index=%u count=%u > %d, err:%d\n", - __func__, index, count, - QDMA_NUM_C2H_BUFFER_SIZES, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - qdma_read_csr_values(dev_hndl, EQDMA_GLBL_RNG_SZ_1_ADDR, index, count, - glbl_rng_sz); - - return QDMA_SUCCESS; -} - -/*****************************************************************************/ -/** - * eqdma_write_global_timer_count() - function to set the timer values - * - * @dev_hndl: device handle - * @glbl_tmr_cnt: pointer to the array having the values to write - * @index: Index from where the values needs to written - * @count: number of entries to be written - * - * (index + count) shall not be more than 16 - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -static int eqdma_write_global_timer_count(void *dev_hndl, uint8_t index, - uint8_t count, const uint32_t *glbl_tmr_cnt) -{ - struct qdma_dev_attributes dev_cap; - - if (!dev_hndl || !glbl_tmr_cnt || !count) { - qdma_log_error("%s: dev_hndl=%p glbl_tmr_cnt=%p, err:%d\n", - __func__, dev_hndl, glbl_tmr_cnt, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - if ((index + count) > QDMA_NUM_C2H_TIMERS) { - qdma_log_error("%s: index=%u count=%u > %d, err:%d\n", - __func__, index, count, - QDMA_NUM_C2H_TIMERS, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - eqdma_get_device_attributes(dev_hndl, &dev_cap); - - if (dev_cap.st_en || dev_cap.mm_cmpt_en) - qdma_write_csr_values(dev_hndl, EQDMA_C2H_TIMER_CNT_ADDR, - index, count, glbl_tmr_cnt); - else { - qdma_log_error("%s: ST or MM cmpt not supported, err:%d\n", - __func__, - -QDMA_ERR_HWACC_FEATURE_NOT_SUPPORTED); - return -QDMA_ERR_HWACC_FEATURE_NOT_SUPPORTED; - } - - return QDMA_SUCCESS; -} - -/*****************************************************************************/ -/** - * eqdma_read_global_timer_count() - function to get the timer values - * - * @dev_hndl: device handle - * @index: Index from where the values needs to read - * @count: number of entries to be read - * @glbl_tmr_cnt: pointer to array to hold the values read - * - * (index + count) shall not be more than 16 - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -static int eqdma_read_global_timer_count(void *dev_hndl, uint8_t index, - uint8_t count, uint32_t *glbl_tmr_cnt) -{ - struct qdma_dev_attributes dev_cap; - - if (!dev_hndl || !glbl_tmr_cnt || !count) { - qdma_log_error("%s: dev_hndl=%p glbl_tmr_cnt=%p, err:%d\n", - __func__, dev_hndl, glbl_tmr_cnt, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - if ((index + count) > QDMA_NUM_C2H_TIMERS) { - qdma_log_error("%s: index=%u count=%u > %d, err:%d\n", - __func__, index, count, - QDMA_NUM_C2H_TIMERS, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - eqdma_get_device_attributes(dev_hndl, &dev_cap); - - if (dev_cap.st_en || dev_cap.mm_cmpt_en) - qdma_read_csr_values(dev_hndl, - EQDMA_C2H_TIMER_CNT_ADDR, index, - count, glbl_tmr_cnt); - else { - qdma_log_error("%s: ST or MM cmpt not supported, err:%d\n", - __func__, - -QDMA_ERR_HWACC_FEATURE_NOT_SUPPORTED); - return -QDMA_ERR_HWACC_FEATURE_NOT_SUPPORTED; - } - - return QDMA_SUCCESS; -} - -/*****************************************************************************/ -/** - * eqdma_write_global_counter_threshold() - function to set the counter - * threshold values - * - * @dev_hndl: device handle - * @index: Index from where the values needs to written - * @count: number of entries to be written - * @glbl_cnt_th: pointer to the array having the values to write - * - * (index + count) shall not be more than 16 - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -static int eqdma_write_global_counter_threshold(void *dev_hndl, uint8_t index, - uint8_t count, const uint32_t *glbl_cnt_th) -{ - struct qdma_dev_attributes dev_cap; - - if (!dev_hndl || !glbl_cnt_th || !count) { - qdma_log_error("%s: dev_hndl=%p glbl_cnt_th=%p, err:%d\n", - __func__, dev_hndl, glbl_cnt_th, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - if ((index + count) > QDMA_NUM_C2H_COUNTERS) { - qdma_log_error("%s: index=%u count=%u > %d, err:%d\n", - __func__, index, count, - QDMA_NUM_C2H_BUFFER_SIZES, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - eqdma_get_device_attributes(dev_hndl, &dev_cap); - - if (dev_cap.st_en || dev_cap.mm_cmpt_en) - qdma_write_csr_values(dev_hndl, EQDMA_C2H_CNT_TH_ADDR, index, - count, glbl_cnt_th); - else { - qdma_log_error("%s: ST or MM cmpt not supported, err:%d\n", - __func__, - -QDMA_ERR_HWACC_FEATURE_NOT_SUPPORTED); - return -QDMA_ERR_HWACC_FEATURE_NOT_SUPPORTED; - } - - return QDMA_SUCCESS; -} - -/*****************************************************************************/ -/** - * eqdma_read_global_counter_threshold() - function to get the counter threshold - * values - * - * @dev_hndl: device handle - * @index: Index from where the values needs to read - * @count: number of entries to be read - * @glbl_cnt_th: pointer to array to hold the values read - * - * (index + count) shall not be more than 16 - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -static int eqdma_read_global_counter_threshold(void *dev_hndl, uint8_t index, - uint8_t count, uint32_t *glbl_cnt_th) -{ - struct qdma_dev_attributes dev_cap; - - if (!dev_hndl || !glbl_cnt_th || !count) { - qdma_log_error("%s: dev_hndl=%p glbl_cnt_th=%p, err:%d\n", - __func__, dev_hndl, glbl_cnt_th, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - if ((index + count) > QDMA_NUM_C2H_COUNTERS) { - qdma_log_error("%s: index=%u count=%u > %d, err:%d\n", - __func__, index, count, - QDMA_NUM_C2H_COUNTERS, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - eqdma_get_device_attributes(dev_hndl, &dev_cap); - - if (dev_cap.st_en || dev_cap.mm_cmpt_en) - qdma_read_csr_values(dev_hndl, EQDMA_C2H_CNT_TH_ADDR, index, - count, glbl_cnt_th); - else { - qdma_log_error("%s: ST or MM cmpt not supported, err:%d\n", - __func__, -QDMA_ERR_HWACC_FEATURE_NOT_SUPPORTED); - return -QDMA_ERR_HWACC_FEATURE_NOT_SUPPORTED; - } - - return QDMA_SUCCESS; -} - -/*****************************************************************************/ -/** - * eqdma_write_global_buffer_sizes() - function to set the buffer sizes - * - * @dev_hndl: device handle - * @index: Index from where the values needs to written - * @count: number of entries to be written - * @glbl_buf_sz: pointer to the array having the values to write - * - * (index + count) shall not be more than 16 - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -static int eqdma_write_global_buffer_sizes(void *dev_hndl, uint8_t index, - uint8_t count, const uint32_t *glbl_buf_sz) -{ - struct qdma_dev_attributes dev_cap; - - if (!dev_hndl || !glbl_buf_sz || !count) { - qdma_log_error("%s: dev_hndl=%p glbl_buf_sz=%p, err:%d\n", - __func__, dev_hndl, glbl_buf_sz, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - if ((index + count) > QDMA_NUM_C2H_BUFFER_SIZES) { - qdma_log_error("%s: index=%u count=%u > %d, err:%d\n", - __func__, index, count, - QDMA_NUM_C2H_BUFFER_SIZES, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - eqdma_get_device_attributes(dev_hndl, &dev_cap); - - if (dev_cap.st_en) - qdma_write_csr_values(dev_hndl, EQDMA_C2H_BUF_SZ_ADDR, index, - count, glbl_buf_sz); - else { - qdma_log_error("%s: ST not supported, err:%d\n", - __func__, - -QDMA_ERR_HWACC_FEATURE_NOT_SUPPORTED); - return -QDMA_ERR_HWACC_FEATURE_NOT_SUPPORTED; - } - - return QDMA_SUCCESS; -} - -/*****************************************************************************/ -/** - * eqdma_read_global_buffer_sizes() - function to get the buffer sizes - * - * @dev_hndl: device handle - * @index: Index from where the values needs to read - * @count: number of entries to be read - * @glbl_buf_sz: pointer to array to hold the values read - * - * (index + count) shall not be more than 16 - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -static int eqdma_read_global_buffer_sizes(void *dev_hndl, uint8_t index, - uint8_t count, uint32_t *glbl_buf_sz) -{ - struct qdma_dev_attributes dev_cap; - - if (!dev_hndl || !glbl_buf_sz || !count) { - qdma_log_error("%s: dev_hndl=%p glbl_buf_sz=%p, err:%d\n", - __func__, dev_hndl, glbl_buf_sz, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - if ((index + count) > QDMA_NUM_C2H_BUFFER_SIZES) { - qdma_log_error("%s: index=%u count=%u > %d, err:%d\n", - __func__, index, count, - QDMA_NUM_C2H_BUFFER_SIZES, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - eqdma_get_device_attributes(dev_hndl, &dev_cap); - - if (dev_cap.st_en) - qdma_read_csr_values(dev_hndl, EQDMA_C2H_BUF_SZ_ADDR, index, - count, glbl_buf_sz); - else { - qdma_log_error("%s: ST is not supported, err:%d\n", - __func__, - -QDMA_ERR_HWACC_FEATURE_NOT_SUPPORTED); - return -QDMA_ERR_HWACC_FEATURE_NOT_SUPPORTED; - } - - return QDMA_SUCCESS; -} - -/*****************************************************************************/ -/** - * eqdma_global_csr_conf() - function to configure global csr - * - * @dev_hndl: device handle - * @index: Index from where the values needs to read - * @count: number of entries to be read - * @csr_val: uint32_t pointer to csr value - * @csr_type: Type of the CSR (qdma_global_csr_type enum) to configure - * @access_type HW access type (qdma_hw_access_type enum) value - * QDMA_HW_ACCESS_CLEAR - Not supported - * QDMA_HW_ACCESS_INVALIDATE - Not supported - * - * (index + count) shall not be more than 16 - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -int eqdma_global_csr_conf(void *dev_hndl, uint8_t index, uint8_t count, - uint32_t *csr_val, - enum qdma_global_csr_type csr_type, - enum qdma_hw_access_type access_type) -{ - int rv = QDMA_SUCCESS; - - switch (csr_type) { - case QDMA_CSR_RING_SZ: - switch (access_type) { - case QDMA_HW_ACCESS_READ: - rv = eqdma_read_global_ring_sizes( - dev_hndl, - index, - count, - csr_val); - break; - case QDMA_HW_ACCESS_WRITE: - rv = eqdma_write_global_ring_sizes( - dev_hndl, - index, - count, - csr_val); - break; - default: - qdma_log_error("%s: access_type(%d) invalid, err:%d\n", - __func__, - access_type, - -QDMA_ERR_INV_PARAM); - rv = -QDMA_ERR_INV_PARAM; - break; - } - break; - case QDMA_CSR_TIMER_CNT: - switch (access_type) { - case QDMA_HW_ACCESS_READ: - rv = eqdma_read_global_timer_count( - dev_hndl, - index, - count, - csr_val); - break; - case QDMA_HW_ACCESS_WRITE: - rv = eqdma_write_global_timer_count( - dev_hndl, - index, - count, - csr_val); - break; - default: - qdma_log_error("%s: access_type(%d) invalid, err:%d\n", - __func__, - access_type, - -QDMA_ERR_INV_PARAM); - rv = -QDMA_ERR_INV_PARAM; - break; - } - break; - case QDMA_CSR_CNT_TH: - switch (access_type) { - case QDMA_HW_ACCESS_READ: - rv = - eqdma_read_global_counter_threshold( - dev_hndl, - index, - count, - csr_val); - break; - case QDMA_HW_ACCESS_WRITE: - rv = - eqdma_write_global_counter_threshold( - dev_hndl, - index, - count, - csr_val); - break; - default: - qdma_log_error("%s: access_type(%d) invalid, err:%d\n", - __func__, - access_type, - -QDMA_ERR_INV_PARAM); - rv = -QDMA_ERR_INV_PARAM; - break; - } - break; - case QDMA_CSR_BUF_SZ: - switch (access_type) { - case QDMA_HW_ACCESS_READ: - rv = - eqdma_read_global_buffer_sizes(dev_hndl, - index, - count, - csr_val); - break; - case QDMA_HW_ACCESS_WRITE: - rv = - eqdma_write_global_buffer_sizes(dev_hndl, - index, - count, - csr_val); - break; - default: - qdma_log_error("%s: access_type(%d) invalid, err:%d\n", - __func__, - access_type, - -QDMA_ERR_INV_PARAM); - rv = -QDMA_ERR_INV_PARAM; - break; - } - break; - default: - qdma_log_error("%s: csr_type(%d) invalid, err:%d\n", - __func__, - csr_type, - -QDMA_ERR_INV_PARAM); - rv = -QDMA_ERR_INV_PARAM; - break; - } - - return rv; -} - -/*****************************************************************************/ -/** - * eqdma_global_writeback_interval_write() - function to set the writeback - * interval - * - * @dev_hndl device handle - * @wb_int: Writeback Interval - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -static int eqdma_global_writeback_interval_write(void *dev_hndl, - enum qdma_wrb_interval wb_int) -{ - uint32_t reg_val; - struct qdma_dev_attributes dev_cap; - - if (!dev_hndl) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", __func__, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - if (wb_int >= QDMA_NUM_WRB_INTERVALS) { - qdma_log_error("%s: wb_int=%d is invalid, err:%d\n", - __func__, wb_int, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - eqdma_get_device_attributes(dev_hndl, &dev_cap); - - if (dev_cap.st_en || dev_cap.mm_cmpt_en) { - reg_val = qdma_reg_read(dev_hndl, EQDMA_GLBL_DSC_CFG_ADDR); - reg_val |= FIELD_SET(GLBL_DSC_CFG_WB_ACC_INT_MASK, wb_int); - qdma_reg_write(dev_hndl, EQDMA_GLBL_DSC_CFG_ADDR, reg_val); - } else { - qdma_log_error("%s: ST or MM cmpt not supported, err:%d\n", - __func__, -QDMA_ERR_HWACC_FEATURE_NOT_SUPPORTED); - return -QDMA_ERR_HWACC_FEATURE_NOT_SUPPORTED; - } - - return QDMA_SUCCESS; -} - -/*****************************************************************************/ -/** - * eqdma_global_writeback_interval_read() - function to get the writeback - * interval - * - * @dev_hndl: device handle - * @wb_int: pointer to the data to hold Writeback Interval - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -static int eqdma_global_writeback_interval_read(void *dev_hndl, - enum qdma_wrb_interval *wb_int) -{ - uint32_t reg_val; - struct qdma_dev_attributes dev_cap; - - if (!dev_hndl) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", __func__, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - if (!wb_int) { - qdma_log_error("%s: wb_int is NULL, err:%d\n", __func__, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - eqdma_get_device_attributes(dev_hndl, &dev_cap); - - if (dev_cap.st_en || dev_cap.mm_cmpt_en) { - reg_val = qdma_reg_read(dev_hndl, EQDMA_GLBL_DSC_CFG_ADDR); - *wb_int = (enum qdma_wrb_interval)FIELD_GET( - GLBL_DSC_CFG_WB_ACC_INT_MASK, reg_val); - } else { - qdma_log_error("%s: ST or MM cmpt not supported, err:%d\n", - __func__, -QDMA_ERR_HWACC_FEATURE_NOT_SUPPORTED); - return -QDMA_ERR_HWACC_FEATURE_NOT_SUPPORTED; - } - - return QDMA_SUCCESS; -} - -/*****************************************************************************/ -/** - * eqdma_global_writeback_interval_conf() - function to configure - * the writeback interval - * - * @dev_hndl: device handle - * @wb_int: pointer to the data to hold Writeback Interval - * @access_type HW access type (qdma_hw_access_type enum) value - * QDMA_HW_ACCESS_CLEAR - Not supported - * QDMA_HW_ACCESS_INVALIDATE - Not supported - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -int eqdma_global_writeback_interval_conf(void *dev_hndl, - enum qdma_wrb_interval *wb_int, - enum qdma_hw_access_type access_type) -{ - int rv = QDMA_SUCCESS; - - switch (access_type) { - case QDMA_HW_ACCESS_READ: - rv = eqdma_global_writeback_interval_read(dev_hndl, wb_int); - break; - case QDMA_HW_ACCESS_WRITE: - rv = eqdma_global_writeback_interval_write(dev_hndl, *wb_int); - break; - case QDMA_HW_ACCESS_CLEAR: - case QDMA_HW_ACCESS_INVALIDATE: - default: - qdma_log_error("%s: access_type(%d) invalid, err:%d\n", - __func__, - access_type, - -QDMA_ERR_INV_PARAM); - rv = -QDMA_ERR_INV_PARAM; - break; - } - - return rv; -} - - -/*****************************************************************************/ -/** - * eqdma_mm_channel_conf() - Function to enable/disable the MM channel - * - * @dev_hndl: device handle - * @channel: MM channel number - * @is_c2h: Queue direction. Set 1 for C2H and 0 for H2C - * @enable: Enable or disable MM channel - * - * Presently, we have only 1 MM channel - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -int eqdma_mm_channel_conf(void *dev_hndl, uint8_t channel, uint8_t is_c2h, - uint8_t enable) -{ - uint32_t reg_addr = (is_c2h) ? EQDMA_C2H_MM_CTL_ADDR : - EQDMA_H2C_MM_CTL_ADDR; - struct qdma_dev_attributes dev_cap; - - if (!dev_hndl) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - eqdma_get_device_attributes(dev_hndl, &dev_cap); - - if (dev_cap.mm_en) - qdma_reg_write(dev_hndl, - reg_addr + (channel * QDMA_MM_CONTROL_STEP), - enable); - - - return QDMA_SUCCESS; -} - -int eqdma_dump_reg_info(void *dev_hndl, uint32_t reg_addr, - uint32_t num_regs, char *buf, uint32_t buflen) -{ - uint32_t total_num_regs = eqdma_config_num_regs_get(); - struct xreg_info *config_regs = eqdma_config_regs_get(); - struct qdma_dev_attributes dev_cap; - const char *bitfield_name; - uint32_t i = 0, num_regs_idx = 0, k = 0, j = 0, - bitfield = 0, lsb = 0, msb = 31; - int rv = 0; - uint32_t reg_val; - uint32_t data_len = 0; - - if (!dev_hndl) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - eqdma_get_device_attributes(dev_hndl, &dev_cap); - - for (i = 0; i < total_num_regs; i++) { - if (reg_addr == config_regs[i].addr) { - j = i; - break; - } - } - - if (i == total_num_regs) { - qdma_log_error("%s: Register not found err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - if (buf) - QDMA_SNPRINTF_S(buf, buflen, - DEBGFS_LINE_SZ, - "Register not found 0x%x\n", reg_addr); - - return -QDMA_ERR_INV_PARAM; - } - - num_regs_idx = (j + num_regs < total_num_regs) ? - (j + num_regs) : total_num_regs; - - for (; j < num_regs_idx ; j++) { - reg_val = qdma_reg_read(dev_hndl, - config_regs[j].addr); - - if (buf) { - rv = QDMA_SNPRINTF_S(buf, buflen, - DEBGFS_LINE_SZ, - "\n%-40s 0x%-7x %-#10x %-10d\n", - config_regs[j].name, - config_regs[j].addr, - reg_val, reg_val); - if ((rv < 0) || (rv > DEBGFS_LINE_SZ)) { - qdma_log_error( - "%s: Insufficient buffer, err:%d\n", - __func__, -QDMA_ERR_NO_MEM); - return -QDMA_ERR_NO_MEM; - } - buf += rv; - data_len += rv; - buflen -= rv; - } else - qdma_log_info("%-40s 0x%-7x %-#10x %-10d\n", - config_regs[j].name, - config_regs[j].addr, - reg_val, reg_val); - - - for (k = 0; - k < config_regs[j].num_bitfields; k++) { - /* If Debug Mode not enabled and the current register - * is debug register, skip reading it. - */ - if (dev_cap.debug_mode == 0 && - config_regs[j].is_debug_reg == 1) - continue; - - bitfield = - config_regs[j].bitfields[k].field_mask; - bitfield_name = - config_regs[i].bitfields[k].field_name; - lsb = 0; - msb = 31; - - while (!(BIT(lsb) & bitfield)) - lsb++; - - while (!(BIT(msb) & bitfield)) - msb--; - - if (msb != lsb) { - if (buf) { - rv = QDMA_SNPRINTF_S(buf, buflen, - DEBGFS_LINE_SZ, - "%-40s [%2u,%2u] %#-10x\n", - bitfield_name, - msb, lsb, - (reg_val & bitfield) >> - lsb); - if ((rv < 0) || (rv > DEBGFS_LINE_SZ)) { - qdma_log_error( - "%s: Insufficient buffer, err:%d\n", - __func__, - -QDMA_ERR_NO_MEM); - return -QDMA_ERR_NO_MEM; - } - buf += rv; - data_len += rv; - buflen -= rv; - } else - qdma_log_info( - "%-40s [%2u,%2u] %#-10x\n", - bitfield_name, - msb, lsb, - (reg_val & bitfield) >> lsb); - - - } else { - if (buf) { - rv = QDMA_SNPRINTF_S(buf, buflen, - DEBGFS_LINE_SZ, - "%-40s [%5u] %#-10x\n", - bitfield_name, - lsb, - (reg_val & bitfield) >> - lsb); - if ((rv < 0) || (rv > DEBGFS_LINE_SZ)) { - qdma_log_error( - "%s: Insufficient buffer, err:%d\n", - __func__, - -QDMA_ERR_NO_MEM); - return -QDMA_ERR_NO_MEM; - } - buf += rv; - data_len += rv; - buflen -= rv; - } else - qdma_log_info( - "%-40s [%5u] %#-10x\n", - bitfield_name, - lsb, - (reg_val & bitfield) >> lsb); - - } - } - } - - return data_len; -} - diff --git a/QDMA/windows/sys/libqdma/source/qdma_access/eqdma_soft_access/eqdma_soft_access.h b/QDMA/windows/sys/libqdma/source/qdma_access/eqdma_soft_access/eqdma_soft_access.h deleted file mode 100644 index 4f37f2459..000000000 --- a/QDMA/windows/sys/libqdma/source/qdma_access/eqdma_soft_access/eqdma_soft_access.h +++ /dev/null @@ -1,306 +0,0 @@ -/* - * Copyright (C) 2020 Xilinx, Inc - * - * Licensed under the Apache License, Version 2.0 (the "License"). You may - * not use this file except in compliance with the License. You may obtain - * a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - */ - -#ifndef __EQDMA_SOFT_ACCESS_H_ -#define __EQDMA_SOFT_ACCESS_H_ - -#ifdef __cplusplus -extern "C" { -#endif - -#include "qdma_platform.h" - -/** - * enum qdma_error_idx - qdma errors - */ -enum eqdma_error_idx { - /* Descriptor errors */ - EQDMA_DSC_ERR_POISON, - EQDMA_DSC_ERR_UR_CA, - EQDMA_DSC_ERR_BCNT, - EQDMA_DSC_ERR_PARAM, - EQDMA_DSC_ERR_ADDR, - EQDMA_DSC_ERR_TAG, - EQDMA_DSC_ERR_FLR, - EQDMA_DSC_ERR_TIMEOUT, - EQDMA_DSC_ERR_DAT_POISON, - EQDMA_DSC_ERR_FLR_CANCEL, - EQDMA_DSC_ERR_DMA, - EQDMA_DSC_ERR_DSC, - EQDMA_DSC_ERR_RQ_CANCEL, - EQDMA_DSC_ERR_DBE, - EQDMA_DSC_ERR_SBE, - EQDMA_DSC_ERR_ALL, - - /* TRQ Errors */ - EQDMA_TRQ_ERR_CSR_UNMAPPED, - EQDMA_TRQ_ERR_VF_ACCESS, - EQDMA_TRQ_ERR_TCP_CSR_TIMEOUT, - EQDMA_TRQ_ERR_QSPC_UNMAPPED, - EQDMA_TRQ_ERR_QID_RANGE, - EQDMA_TRQ_ERR_TCP_QSPC_TIMEOUT, - EQDMA_TRQ_ERR_ALL, - - /* C2H Errors */ - EQDMA_ST_C2H_ERR_MTY_MISMATCH, - EQDMA_ST_C2H_ERR_LEN_MISMATCH, - EQDMA_ST_C2H_ERR_SH_CMPT_DSC, - EQDMA_ST_C2H_ERR_QID_MISMATCH, - EQDMA_ST_C2H_ERR_DESC_RSP_ERR, - EQDMA_ST_C2H_ERR_ENG_WPL_DATA_PAR_ERR, - EQDMA_ST_C2H_ERR_MSI_INT_FAIL, - EQDMA_ST_C2H_ERR_ERR_DESC_CNT, - EQDMA_ST_C2H_ERR_PORTID_CTXT_MISMATCH, - EQDMA_ST_C2H_ERR_CMPT_INV_Q_ERR, - EQDMA_ST_C2H_ERR_CMPT_QFULL_ERR, - EQDMA_ST_C2H_ERR_CMPT_CIDX_ERR, - EQDMA_ST_C2H_ERR_CMPT_PRTY_ERR, - EQDMA_ST_C2H_ERR_AVL_RING_DSC, - EQDMA_ST_C2H_ERR_HDR_ECC_UNC, - EQDMA_ST_C2H_ERR_HDR_ECC_COR, - EQDMA_ST_C2H_ERR_ALL, - - /* Fatal Errors */ - EQDMA_ST_FATAL_ERR_MTY_MISMATCH, - EQDMA_ST_FATAL_ERR_LEN_MISMATCH, - EQDMA_ST_FATAL_ERR_QID_MISMATCH, - EQDMA_ST_FATAL_ERR_TIMER_FIFO_RAM_RDBE, - EQDMA_ST_FATAL_ERR_PFCH_II_RAM_RDBE, - EQDMA_ST_FATAL_ERR_CMPT_CTXT_RAM_RDBE, - EQDMA_ST_FATAL_ERR_PFCH_CTXT_RAM_RDBE, - EQDMA_ST_FATAL_ERR_DESC_REQ_FIFO_RAM_RDBE, - EQDMA_ST_FATAL_ERR_INT_CTXT_RAM_RDBE, - EQDMA_ST_FATAL_ERR_CMPT_COAL_DATA_RAM_RDBE, - EQDMA_ST_FATAL_ERR_CMPT_FIFO_RAM_RDBE, - EQDMA_ST_FATAL_ERR_QID_FIFO_RAM_RDBE, - EQDMA_ST_FATAL_ERR_PAYLOAD_FIFO_RAM_RDBE, - EQDMA_ST_FATAL_ERR_WPL_DATA_PAR, - EQDMA_ST_FATAL_ERR_AVL_RING_FIFO_RAM_RDBE, - EQDMA_ST_FATAL_ERR_HDR_ECC_UNC, - EQDMA_ST_FATAL_ERR_ALL, - - /* H2C Errors */ - EQDMA_ST_H2C_ERR_ZERO_LEN_DESC, - EQDMA_ST_H2C_ERR_SDI_MRKR_REQ_MOP, - EQDMA_ST_H2C_ERR_NO_DMA_DSC, - EQDMA_ST_H2C_ERR_SBE, - EQDMA_ST_H2C_ERR_DBE, - EQDMA_ST_H2C_ERR_PAR, - EQDMA_ST_H2C_ERR_ALL, - - /* Single bit errors */ - EQDMA_SBE_1_ERR_RC_RRQ_EVEN_RAM, - EQDMA_SBE_1_ERR_TAG_ODD_RAM, - EQDMA_SBE_1_ERR_TAG_EVEN_RAM, - EQDMA_SBE_1_ERR_PFCH_CTXT_CAM_RAM_0, - EQDMA_SBE_1_ERR_PFCH_CTXT_CAM_RAM_1, - EQDMA_SBE_1_ERR_ALL, - - /* Single bit errors */ - EQDMA_SBE_ERR_MI_H2C0_DAT, - EQDMA_SBE_ERR_MI_H2C1_DAT, - EQDMA_SBE_ERR_MI_H2C2_DAT, - EQDMA_SBE_ERR_MI_H2C3_DAT, - EQDMA_SBE_ERR_MI_C2H0_DAT, - EQDMA_SBE_ERR_MI_C2H1_DAT, - EQDMA_SBE_ERR_MI_C2H2_DAT, - EQDMA_SBE_ERR_MI_C2H3_DAT, - EQDMA_SBE_ERR_H2C_RD_BRG_DAT, - EQDMA_SBE_ERR_H2C_WR_BRG_DAT, - EQDMA_SBE_ERR_C2H_RD_BRG_DAT, - EQDMA_SBE_ERR_C2H_WR_BRG_DAT, - EQDMA_SBE_ERR_FUNC_MAP, - EQDMA_SBE_ERR_DSC_HW_CTXT, - EQDMA_SBE_ERR_DSC_CRD_RCV, - EQDMA_SBE_ERR_DSC_SW_CTXT, - EQDMA_SBE_ERR_DSC_CPLI, - EQDMA_SBE_ERR_DSC_CPLD, - EQDMA_SBE_ERR_MI_TL_SLV_FIFO_RAM, - EQDMA_SBE_ERR_TIMER_FIFO_RAM, - EQDMA_SBE_ERR_QID_FIFO_RAM, - EQDMA_SBE_ERR_WRB_COAL_DATA_RAM, - EQDMA_SBE_ERR_INT_CTXT_RAM, - EQDMA_SBE_ERR_DESC_REQ_FIFO_RAM, - EQDMA_SBE_ERR_PFCH_CTXT_RAM, - EQDMA_SBE_ERR_WRB_CTXT_RAM, - EQDMA_SBE_ERR_PFCH_LL_RAM, - EQDMA_SBE_ERR_PEND_FIFO_RAM, - EQDMA_SBE_ERR_RC_RRQ_ODD_RAM, - EQDMA_SBE_ERR_ALL, - - /* Double bit Errors */ - EQDMA_DBE_1_ERR_RC_RRQ_EVEN_RAM, - EQDMA_DBE_1_ERR_TAG_ODD_RAM, - EQDMA_DBE_1_ERR_TAG_EVEN_RAM, - EQDMA_DBE_1_ERR_PFCH_CTXT_CAM_RAM_0, - EQDMA_DBE_1_ERR_PFCH_CTXT_CAM_RAM_1, - EQDMA_DBE_1_ERR_ALL, - - /* Double bit Errors */ - EQDMA_DBE_ERR_MI_H2C0_DAT, - EQDMA_DBE_ERR_MI_H2C1_DAT, - EQDMA_DBE_ERR_MI_H2C2_DAT, - EQDMA_DBE_ERR_MI_H2C3_DAT, - EQDMA_DBE_ERR_MI_C2H0_DAT, - EQDMA_DBE_ERR_MI_C2H1_DAT, - EQDMA_DBE_ERR_MI_C2H2_DAT, - EQDMA_DBE_ERR_MI_C2H3_DAT, - EQDMA_DBE_ERR_H2C_RD_BRG_DAT, - EQDMA_DBE_ERR_H2C_WR_BRG_DAT, - EQDMA_DBE_ERR_C2H_RD_BRG_DAT, - EQDMA_DBE_ERR_C2H_WR_BRG_DAT, - EQDMA_DBE_ERR_FUNC_MAP, - EQDMA_DBE_ERR_DSC_HW_CTXT, - EQDMA_DBE_ERR_DSC_CRD_RCV, - EQDMA_DBE_ERR_DSC_SW_CTXT, - EQDMA_DBE_ERR_DSC_CPLI, - EQDMA_DBE_ERR_DSC_CPLD, - EQDMA_DBE_ERR_MI_TL_SLV_FIFO_RAM, - EQDMA_DBE_ERR_TIMER_FIFO_RAM, - EQDMA_DBE_ERR_QID_FIFO_RAM, - EQDMA_DBE_ERR_WRB_COAL_DATA_RAM, - EQDMA_DBE_ERR_INT_CTXT_RAM, - EQDMA_DBE_ERR_DESC_REQ_FIFO_RAM, - EQDMA_DBE_ERR_PFCH_CTXT_RAM, - EQDMA_DBE_ERR_WRB_CTXT_RAM, - EQDMA_DBE_ERR_PFCH_LL_RAM, - EQDMA_DBE_ERR_PEND_FIFO_RAM, - EQDMA_DBE_ERR_RC_RRQ_ODD_RAM, - EQDMA_DBE_ERR_ALL, - - EQDMA_ERRS_ALL -}; - -struct eqdma_hw_err_info { - enum eqdma_error_idx idx; - const char *err_name; - uint32_t mask_reg_addr; - uint32_t stat_reg_addr; - uint32_t leaf_err_mask; - uint32_t global_err_mask; - void (*eqdma_hw_err_process)(void *dev_hndl); -}; - -#define EQDMA_OFFSET_VF_VERSION 0x5014 -#define EQDMA_OFFSET_VF_USER_BAR 0x5018 - -#define EQDMA_OFFSET_MBOX_BASE_PF 0x22400 -#define EQDMA_OFFSET_MBOX_BASE_VF 0x5000 - -#define EQDMA_COMPL_CTXT_BADDR_HIGH_H_MASK GENMASK_ULL(63, 38) -#define EQDMA_COMPL_CTXT_BADDR_HIGH_L_MASK GENMASK_ULL(37, 6) -#define EQDMA_COMPL_CTXT_BADDR_LOW_MASK GENMASK_ULL(5, 2) - -int eqdma_init_ctxt_memory(void *dev_hndl); - -int eqdma_get_version(void *dev_hndl, uint8_t is_vf, - struct qdma_hw_version_info *version_info); - -int eqdma_sw_ctx_conf(void *dev_hndl, uint8_t c2h, uint16_t hw_qid, - struct qdma_descq_sw_ctxt *ctxt, - enum qdma_hw_access_type access_type); - -int eqdma_hw_ctx_conf(void *dev_hndl, uint8_t c2h, uint16_t hw_qid, - struct qdma_descq_hw_ctxt *ctxt, - enum qdma_hw_access_type access_type); - -int eqdma_credit_ctx_conf(void *dev_hndl, uint8_t c2h, - uint16_t hw_qid, struct qdma_descq_credit_ctxt *ctxt, - enum qdma_hw_access_type access_type); - -int eqdma_pfetch_ctx_conf(void *dev_hndl, uint16_t hw_qid, - struct qdma_descq_prefetch_ctxt *ctxt, - enum qdma_hw_access_type access_type); - -int eqdma_cmpt_ctx_conf(void *dev_hndl, uint16_t hw_qid, - struct qdma_descq_cmpt_ctxt *ctxt, - enum qdma_hw_access_type access_type); - -int eqdma_indirect_intr_ctx_conf(void *dev_hndl, uint16_t ring_index, - struct qdma_indirect_intr_ctxt *ctxt, - enum qdma_hw_access_type access_type); - -int eqdma_dump_config_regs(void *dev_hndl, uint8_t is_vf, - char *buf, uint32_t buflen); - -int eqdma_dump_intr_context(void *dev_hndl, - struct qdma_indirect_intr_ctxt *intr_ctx, - int ring_index, - char *buf, uint32_t buflen); - -int eqdma_dump_queue_context(void *dev_hndl, - uint8_t st, - enum qdma_dev_q_type q_type, - struct qdma_descq_context *ctxt_data, - char *buf, uint32_t buflen); - -uint32_t eqdma_reg_dump_buf_len(void); - -int eqdma_context_buf_len(uint8_t st, - enum qdma_dev_q_type q_type, uint32_t *buflen); - -int eqdma_hw_error_process(void *dev_hndl); -const char *eqdma_hw_get_error_name(uint32_t err_idx); -int eqdma_hw_error_enable(void *dev_hndl, uint32_t err_idx); - -int eqdma_read_dump_queue_context(void *dev_hndl, - uint16_t qid_hw, - uint8_t st, - enum qdma_dev_q_type q_type, - char *buf, uint32_t buflen); - -int eqdma_get_device_attributes(void *dev_hndl, - struct qdma_dev_attributes *dev_info); - -int eqdma_get_user_bar(void *dev_hndl, uint8_t is_vf, - uint8_t func_id, uint8_t *user_bar); - -int eqdma_dump_config_reg_list(void *dev_hndl, - uint32_t total_regs, - struct qdma_reg_data *reg_list, - char *buf, uint32_t buflen); - -int eqdma_read_reg_list(void *dev_hndl, uint8_t is_vf, - uint16_t reg_rd_group, - uint16_t *total_regs, - struct qdma_reg_data *reg_list); - -int eqdma_set_default_global_csr(void *dev_hndl); - -int eqdma_global_csr_conf(void *dev_hndl, uint8_t index, uint8_t count, - uint32_t *csr_val, - enum qdma_global_csr_type csr_type, - enum qdma_hw_access_type access_type); - -int eqdma_global_writeback_interval_conf(void *dev_hndl, - enum qdma_wrb_interval *wb_int, - enum qdma_hw_access_type access_type); - -int eqdma_mm_channel_conf(void *dev_hndl, uint8_t channel, uint8_t is_c2h, - uint8_t enable); - -int eqdma_dump_reg_info(void *dev_hndl, uint32_t reg_addr, - uint32_t num_regs, char *buf, uint32_t buflen); - -uint32_t eqdma_get_config_num_regs(void); - -struct xreg_info *eqdma_get_config_regs(void); - -#ifdef __cplusplus -} -#endif - -#endif /* __EQDMA_SOFT_ACCESS_H_ */ diff --git a/QDMA/windows/sys/libqdma/source/qdma_access/eqdma_soft_access/eqdma_soft_reg.h b/QDMA/windows/sys/libqdma/source/qdma_access/eqdma_soft_access/eqdma_soft_reg.h deleted file mode 100644 index eac97ed6f..000000000 --- a/QDMA/windows/sys/libqdma/source/qdma_access/eqdma_soft_access/eqdma_soft_reg.h +++ /dev/null @@ -1,1226 +0,0 @@ -/* - * Copyright (C) 2020 Xilinx, Inc - * - * Licensed under the Apache License, Version 2.0 (the "License"). You may - * not use this file except in compliance with the License. You may obtain - * a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - */ - -#ifndef __EQDMA_SOFT_REG_H -#define __EQDMA_SOFT_REG_H - - -#ifdef __cplusplus -extern "C" { -#endif - -#include "qdma_platform.h" - -#ifdef CHAR_BIT -#undef CHAR_BIT -#endif -#define CHAR_BIT 8 - -#ifdef BIT -#undef BIT -#endif -#define BIT(n) (1u << (n)) - -#ifdef BITS_PER_BYTE -#undef BITS_PER_BYTE -#endif -#define BITS_PER_BYTE CHAR_BIT - -#ifdef BITS_PER_LONG -#undef BITS_PER_LONG -#endif -#define BITS_PER_LONG (sizeof(uint32_t) * BITS_PER_BYTE) - -#ifdef BITS_PER_LONG_LONG -#undef BITS_PER_LONG_LONG -#endif -#define BITS_PER_LONG_LONG (sizeof(uint64_t) * BITS_PER_BYTE) - -#ifdef GENMASK -#undef GENMASK -#endif -#define GENMASK(h, l) \ - ((0xFFFFFFFF << (l)) & (0xFFFFFFFF >> (BITS_PER_LONG - 1 - (h)))) - -#ifdef GENMASK_ULL -#undef GENMASK_ULL -#endif -#define GENMASK_ULL(h, l) \ - ((0xFFFFFFFFFFFFFFFF << (l)) & \ - (0xFFFFFFFFFFFFFFFF >> (BITS_PER_LONG_LONG - 1 - (h)))) - -#define DEBGFS_LINE_SZ (81) - -#ifdef ARRAY_SIZE -#undef ARRAY_SIZE -#endif -#define ARRAY_SIZE(arr) (sizeof(arr) / \ - sizeof(arr[0])) - - -uint32_t eqdma_config_num_regs_get(void); -struct xreg_info *eqdma_config_regs_get(void); -#define EQDMA_CFG_BLK_IDENTIFIER_ADDR 0x00 -#define CFG_BLK_IDENTIFIER_MASK GENMASK(31, 20) -#define CFG_BLK_IDENTIFIER_1_MASK GENMASK(19, 16) -#define CFG_BLK_IDENTIFIER_RSVD_1_MASK GENMASK(15, 8) -#define CFG_BLK_IDENTIFIER_VERSION_MASK GENMASK(7, 0) -#define EQDMA_CFG_BLK_PCIE_MAX_PLD_SIZE_ADDR 0x08 -#define CFG_BLK_PCIE_MAX_PLD_SIZE_RSVD_1_MASK GENMASK(31, 7) -#define CFG_BLK_PCIE_MAX_PLD_SIZE_PROG_MASK GENMASK(6, 4) -#define CFG_BLK_PCIE_MAX_PLD_SIZE_RSVD_2_MASK BIT(3) -#define CFG_BLK_PCIE_MAX_PLD_SIZE_ISSUED_MASK GENMASK(2, 0) -#define EQDMA_CFG_BLK_PCIE_MAX_READ_REQ_SIZE_ADDR 0x0C -#define CFG_BLK_PCIE_MAX_READ_REQ_SIZE_RSVD_1_MASK GENMASK(31, 7) -#define CFG_BLK_PCIE_MAX_READ_REQ_SIZE_PROG_MASK GENMASK(6, 4) -#define CFG_BLK_PCIE_MAX_READ_REQ_SIZE_RSVD_2_MASK BIT(3) -#define CFG_BLK_PCIE_MAX_READ_REQ_SIZE_ISSUED_MASK GENMASK(2, 0) -#define EQDMA_CFG_BLK_SYSTEM_ID_ADDR 0x10 -#define CFG_BLK_SYSTEM_ID_RSVD_1_MASK GENMASK(31, 17) -#define CFG_BLK_SYSTEM_ID_INST_TYPE_MASK BIT(16) -#define CFG_BLK_SYSTEM_ID_MASK GENMASK(15, 0) -#define EQDMA_CFG_BLK_MSIX_ENABLE_ADDR 0x014 -#define CFG_BLK_MSIX_ENABLE_MASK GENMASK(31, 0) -#define EQDMA_CFG_PCIE_DATA_WIDTH_ADDR 0x18 -#define CFG_PCIE_DATA_WIDTH_RSVD_1_MASK GENMASK(31, 3) -#define CFG_PCIE_DATA_WIDTH_DATAPATH_MASK GENMASK(2, 0) -#define EQDMA_CFG_PCIE_CTL_ADDR 0x1C -#define CFG_PCIE_CTL_RSVD_1_MASK GENMASK(31, 18) -#define CFG_PCIE_CTL_MGMT_AXIL_CTRL_MASK GENMASK(17, 16) -#define CFG_PCIE_CTL_RSVD_2_MASK GENMASK(15, 2) -#define CFG_PCIE_CTL_RRQ_DISABLE_MASK BIT(1) -#define CFG_PCIE_CTL_RELAXED_ORDERING_MASK BIT(0) -#define EQDMA_CFG_BLK_MSI_ENABLE_ADDR 0x20 -#define CFG_BLK_MSI_ENABLE_MASK GENMASK(31, 0) -#define EQDMA_CFG_AXI_USER_MAX_PLD_SIZE_ADDR 0x40 -#define CFG_AXI_USER_MAX_PLD_SIZE_RSVD_1_MASK GENMASK(31, 7) -#define CFG_AXI_USER_MAX_PLD_SIZE_ISSUED_MASK GENMASK(6, 4) -#define CFG_AXI_USER_MAX_PLD_SIZE_RSVD_2_MASK BIT(3) -#define CFG_AXI_USER_MAX_PLD_SIZE_PROG_MASK GENMASK(2, 0) -#define EQDMA_CFG_AXI_USER_MAX_READ_REQ_SIZE_ADDR 0x44 -#define CFG_AXI_USER_MAX_READ_REQ_SIZE_RSVD_1_MASK GENMASK(31, 7) -#define CFG_AXI_USER_MAX_READ_REQ_SIZE_USISSUED_MASK GENMASK(6, 4) -#define CFG_AXI_USER_MAX_READ_REQ_SIZE_RSVD_2_MASK BIT(3) -#define CFG_AXI_USER_MAX_READ_REQ_SIZE_USPROG_MASK GENMASK(2, 0) -#define EQDMA_CFG_BLK_MISC_CTL_ADDR 0x4C -#define CFG_BLK_MISC_CTL_RSVD_1_MASK GENMASK(31, 24) -#define CFG_BLK_MISC_CTL_10B_TAG_EN_MASK BIT(23) -#define CFG_BLK_MISC_CTL_RSVD_2_MASK BIT(22) -#define CFG_BLK_MISC_CTL_AXI_WBK_MASK BIT(21) -#define CFG_BLK_MISC_CTL_AXI_DSC_MASK BIT(20) -#define CFG_BLK_MISC_CTL_NUM_TAG_MASK GENMASK(19, 8) -#define CFG_BLK_MISC_CTL_RSVD_3_MASK GENMASK(7, 5) -#define CFG_BLK_MISC_CTL_RQ_METERING_MULTIPLIER_MASK GENMASK(4, 0) -#define EQDMA_CFG_PL_CRED_CTL_ADDR 0x68 -#define CFG_PL_CRED_CTL_RSVD_1_MASK GENMASK(31, 5) -#define CFG_PL_CRED_CTL_SLAVE_CRD_RLS_MASK BIT(4) -#define CFG_PL_CRED_CTL_RSVD_2_MASK GENMASK(3, 1) -#define CFG_PL_CRED_CTL_MASTER_CRD_RST_MASK BIT(0) -#define EQDMA_CFG_BLK_SCRATCH_ADDR 0x80 -#define CFG_BLK_SCRATCH_MASK GENMASK(31, 0) -#define EQDMA_CFG_GIC_ADDR 0xA0 -#define CFG_GIC_RSVD_1_MASK GENMASK(31, 1) -#define CFG_GIC_GIC_IRQ_MASK BIT(0) -#define EQDMA_RAM_SBE_MSK_1_A_ADDR 0xE0 -#define RAM_SBE_MSK_1_A_MASK GENMASK(31, 0) -#define EQDMA_RAM_SBE_STS_1_A_ADDR 0xE4 -#define RAM_SBE_STS_1_A_RSVD_MASK GENMASK(31, 5) -#define RAM_SBE_STS_1_A_PFCH_CTXT_CAM_RAM_1_MASK BIT(4) -#define RAM_SBE_STS_1_A_PFCH_CTXT_CAM_RAM_0_MASK BIT(3) -#define RAM_SBE_STS_1_A_TAG_EVEN_RAM_MASK BIT(2) -#define RAM_SBE_STS_1_A_TAG_ODD_RAM_MASK BIT(1) -#define RAM_SBE_STS_1_A_RC_RRQ_EVEN_RAM_MASK BIT(0) -#define EQDMA_RAM_DBE_MSK_1_A_ADDR 0xE8 -#define RAM_DBE_MSK_1_A_MASK GENMASK(31, 0) -#define EQDMA_RAM_DBE_STS_1_A_ADDR 0xEC -#define RAM_DBE_STS_1_A_RSVD_MASK GENMASK(31, 5) -#define RAM_DBE_STS_1_A_PFCH_CTXT_CAM_RAM_1_MASK BIT(4) -#define RAM_DBE_STS_1_A_PFCH_CTXT_CAM_RAM_0_MASK BIT(3) -#define RAM_DBE_STS_1_A_TAG_EVEN_RAM_MASK BIT(2) -#define RAM_DBE_STS_1_A_TAG_ODD_RAM_MASK BIT(1) -#define RAM_DBE_STS_1_A_RC_RRQ_EVEN_RAM_MASK BIT(0) -#define EQDMA_RAM_SBE_MSK_A_ADDR 0xF0 -#define RAM_SBE_MSK_A_MASK GENMASK(31, 0) -#define EQDMA_RAM_SBE_STS_A_ADDR 0xF4 -#define RAM_SBE_STS_A_RC_RRQ_ODD_RAM_MASK BIT(31) -#define RAM_SBE_STS_A_PEND_FIFO_RAM_MASK BIT(30) -#define RAM_SBE_STS_A_PFCH_LL_RAM_MASK BIT(29) -#define RAM_SBE_STS_A_WRB_CTXT_RAM_MASK BIT(28) -#define RAM_SBE_STS_A_PFCH_CTXT_RAM_MASK BIT(27) -#define RAM_SBE_STS_A_DESC_REQ_FIFO_RAM_MASK BIT(26) -#define RAM_SBE_STS_A_INT_CTXT_RAM_MASK BIT(25) -#define RAM_SBE_STS_A_WRB_COAL_DATA_RAM_MASK BIT(24) -#define RAM_SBE_STS_A_QID_FIFO_RAM_MASK BIT(23) -#define RAM_SBE_STS_A_TIMER_FIFO_RAM_MASK GENMASK(22, 19) -#define RAM_SBE_STS_A_MI_TL_SLV_FIFO_RAM_MASK BIT(18) -#define RAM_SBE_STS_A_DSC_CPLD_MASK BIT(17) -#define RAM_SBE_STS_A_DSC_CPLI_MASK BIT(16) -#define RAM_SBE_STS_A_DSC_SW_CTXT_MASK BIT(15) -#define RAM_SBE_STS_A_DSC_CRD_RCV_MASK BIT(14) -#define RAM_SBE_STS_A_DSC_HW_CTXT_MASK BIT(13) -#define RAM_SBE_STS_A_FUNC_MAP_MASK BIT(12) -#define RAM_SBE_STS_A_C2H_WR_BRG_DAT_MASK BIT(11) -#define RAM_SBE_STS_A_C2H_RD_BRG_DAT_MASK BIT(10) -#define RAM_SBE_STS_A_H2C_WR_BRG_DAT_MASK BIT(9) -#define RAM_SBE_STS_A_H2C_RD_BRG_DAT_MASK BIT(8) -#define RAM_SBE_STS_A_MI_C2H3_DAT_MASK BIT(7) -#define RAM_SBE_STS_A_MI_C2H2_DAT_MASK BIT(6) -#define RAM_SBE_STS_A_MI_C2H1_DAT_MASK BIT(5) -#define RAM_SBE_STS_A_MI_C2H0_DAT_MASK BIT(4) -#define RAM_SBE_STS_A_MI_H2C3_DAT_MASK BIT(3) -#define RAM_SBE_STS_A_MI_H2C2_DAT_MASK BIT(2) -#define RAM_SBE_STS_A_MI_H2C1_DAT_MASK BIT(1) -#define RAM_SBE_STS_A_MI_H2C0_DAT_MASK BIT(0) -#define EQDMA_RAM_DBE_MSK_A_ADDR 0xF8 -#define RAM_DBE_MSK_A_MASK GENMASK(31, 0) -#define EQDMA_RAM_DBE_STS_A_ADDR 0xFC -#define RAM_DBE_STS_A_RC_RRQ_ODD_RAM_MASK BIT(31) -#define RAM_DBE_STS_A_PEND_FIFO_RAM_MASK BIT(30) -#define RAM_DBE_STS_A_PFCH_LL_RAM_MASK BIT(29) -#define RAM_DBE_STS_A_WRB_CTXT_RAM_MASK BIT(28) -#define RAM_DBE_STS_A_PFCH_CTXT_RAM_MASK BIT(27) -#define RAM_DBE_STS_A_DESC_REQ_FIFO_RAM_MASK BIT(26) -#define RAM_DBE_STS_A_INT_CTXT_RAM_MASK BIT(25) -#define RAM_DBE_STS_A_WRB_COAL_DATA_RAM_MASK BIT(24) -#define RAM_DBE_STS_A_QID_FIFO_RAM_MASK BIT(23) -#define RAM_DBE_STS_A_TIMER_FIFO_RAM_MASK GENMASK(22, 19) -#define RAM_DBE_STS_A_MI_TL_SLV_FIFO_RAM_MASK BIT(18) -#define RAM_DBE_STS_A_DSC_CPLD_MASK BIT(17) -#define RAM_DBE_STS_A_DSC_CPLI_MASK BIT(16) -#define RAM_DBE_STS_A_DSC_SW_CTXT_MASK BIT(15) -#define RAM_DBE_STS_A_DSC_CRD_RCV_MASK BIT(14) -#define RAM_DBE_STS_A_DSC_HW_CTXT_MASK BIT(13) -#define RAM_DBE_STS_A_FUNC_MAP_MASK BIT(12) -#define RAM_DBE_STS_A_C2H_WR_BRG_DAT_MASK BIT(11) -#define RAM_DBE_STS_A_C2H_RD_BRG_DAT_MASK BIT(10) -#define RAM_DBE_STS_A_H2C_WR_BRG_DAT_MASK BIT(9) -#define RAM_DBE_STS_A_H2C_RD_BRG_DAT_MASK BIT(8) -#define RAM_DBE_STS_A_MI_C2H3_DAT_MASK BIT(7) -#define RAM_DBE_STS_A_MI_C2H2_DAT_MASK BIT(6) -#define RAM_DBE_STS_A_MI_C2H1_DAT_MASK BIT(5) -#define RAM_DBE_STS_A_MI_C2H0_DAT_MASK BIT(4) -#define RAM_DBE_STS_A_MI_H2C3_DAT_MASK BIT(3) -#define RAM_DBE_STS_A_MI_H2C2_DAT_MASK BIT(2) -#define RAM_DBE_STS_A_MI_H2C1_DAT_MASK BIT(1) -#define RAM_DBE_STS_A_MI_H2C0_DAT_MASK BIT(0) -#define EQDMA_GLBL2_IDENTIFIER_ADDR 0x100 -#define GLBL2_IDENTIFIER_MASK GENMASK(31, 8) -#define GLBL2_IDENTIFIER_VERSION_MASK GENMASK(7, 0) -#define EQDMA_GLBL2_CHANNEL_INST_ADDR 0x114 -#define GLBL2_CHANNEL_INST_RSVD_1_MASK GENMASK(31, 18) -#define GLBL2_CHANNEL_INST_C2H_ST_MASK BIT(17) -#define GLBL2_CHANNEL_INST_H2C_ST_MASK BIT(16) -#define GLBL2_CHANNEL_INST_RSVD_2_MASK GENMASK(15, 12) -#define GLBL2_CHANNEL_INST_C2H_ENG_MASK GENMASK(11, 8) -#define GLBL2_CHANNEL_INST_RSVD_3_MASK GENMASK(7, 4) -#define GLBL2_CHANNEL_INST_H2C_ENG_MASK GENMASK(3, 0) -#define EQDMA_GLBL2_CHANNEL_MDMA_ADDR 0x118 -#define GLBL2_CHANNEL_MDMA_RSVD_1_MASK GENMASK(31, 18) -#define GLBL2_CHANNEL_MDMA_C2H_ST_MASK BIT(17) -#define GLBL2_CHANNEL_MDMA_H2C_ST_MASK BIT(16) -#define GLBL2_CHANNEL_MDMA_RSVD_2_MASK GENMASK(15, 12) -#define GLBL2_CHANNEL_MDMA_C2H_ENG_MASK GENMASK(11, 8) -#define GLBL2_CHANNEL_MDMA_RSVD_3_MASK GENMASK(7, 4) -#define GLBL2_CHANNEL_MDMA_H2C_ENG_MASK GENMASK(3, 0) -#define EQDMA_GLBL2_CHANNEL_STRM_ADDR 0x11C -#define GLBL2_CHANNEL_STRM_RSVD_1_MASK GENMASK(31, 18) -#define GLBL2_CHANNEL_STRM_C2H_ST_MASK BIT(17) -#define GLBL2_CHANNEL_STRM_H2C_ST_MASK BIT(16) -#define GLBL2_CHANNEL_STRM_RSVD_2_MASK GENMASK(15, 12) -#define GLBL2_CHANNEL_STRM_C2H_ENG_MASK GENMASK(11, 8) -#define GLBL2_CHANNEL_STRM_RSVD_3_MASK GENMASK(7, 4) -#define GLBL2_CHANNEL_STRM_H2C_ENG_MASK GENMASK(3, 0) -#define EQDMA_GLBL2_CHANNEL_CAP_ADDR 0x120 -#define GLBL2_CHANNEL_CAP_RSVD_1_MASK GENMASK(31, 12) -#define GLBL2_CHANNEL_CAP_MULTIQ_MAX_MASK GENMASK(11, 0) -#define EQDMA_GLBL2_CHANNEL_PASID_CAP_ADDR 0x128 -#define GLBL2_CHANNEL_PASID_CAP_RSVD_1_MASK GENMASK(31, 2) -#define GLBL2_CHANNEL_PASID_CAP_BRIDGEEN_MASK BIT(1) -#define GLBL2_CHANNEL_PASID_CAP_DMAEN_MASK BIT(0) -#define EQDMA_GLBL2_SYSTEM_ID_ADDR 0x130 -#define GLBL2_SYSTEM_ID_RSVD_1_MASK GENMASK(31, 16) -#define GLBL2_SYSTEM_ID_MASK GENMASK(15, 0) -#define EQDMA_GLBL2_MISC_CAP_ADDR 0x134 -#define GLBL2_MISC_CAP_MASK GENMASK(31, 0) -#define EQDMA_GLBL2_DBG_PCIE_RQ0_ADDR 0x1B8 -#define GLBL2_PCIE_RQ0_NPH_AVL_MASK GENMASK(31, 20) -#define GLBL2_PCIE_RQ0_RCB_AVL_MASK GENMASK(19, 9) -#define GLBL2_PCIE_RQ0_SLV_RD_CREDS_MASK GENMASK(8, 2) -#define GLBL2_PCIE_RQ0_TAG_EP_MASK GENMASK(1, 0) -#define EQDMA_GLBL2_DBG_PCIE_RQ1_ADDR 0x1BC -#define GLBL2_PCIE_RQ1_RSVD_1_MASK GENMASK(31, 21) -#define GLBL2_PCIE_RQ1_TAG_FL_MASK GENMASK(20, 19) -#define GLBL2_PCIE_RQ1_WTLP_HEADER_FIFO_FL_MASK BIT(18) -#define GLBL2_PCIE_RQ1_WTLP_HEADER_FIFO_EP_MASK BIT(17) -#define GLBL2_PCIE_RQ1_RQ_FIFO_EP_MASK BIT(16) -#define GLBL2_PCIE_RQ1_RQ_FIFO_FL_MASK BIT(15) -#define GLBL2_PCIE_RQ1_TLPSM_MASK GENMASK(14, 12) -#define GLBL2_PCIE_RQ1_TLPSM512_MASK GENMASK(11, 9) -#define GLBL2_PCIE_RQ1_RREQ_RCB_OK_MASK BIT(8) -#define GLBL2_PCIE_RQ1_RREQ0_SLV_MASK BIT(7) -#define GLBL2_PCIE_RQ1_RREQ0_VLD_MASK BIT(6) -#define GLBL2_PCIE_RQ1_RREQ0_RDY_MASK BIT(5) -#define GLBL2_PCIE_RQ1_RREQ1_SLV_MASK BIT(4) -#define GLBL2_PCIE_RQ1_RREQ1_VLD_MASK BIT(3) -#define GLBL2_PCIE_RQ1_RREQ1_RDY_MASK BIT(2) -#define GLBL2_PCIE_RQ1_WTLP_REQ_MASK BIT(1) -#define GLBL2_PCIE_RQ1_WTLP_STRADDLE_MASK BIT(0) -#define EQDMA_GLBL2_DBG_AXIMM_WR0_ADDR 0x1C0 -#define GLBL2_AXIMM_WR0_RSVD_1_MASK GENMASK(31, 27) -#define GLBL2_AXIMM_WR0_WR_REQ_MASK BIT(26) -#define GLBL2_AXIMM_WR0_WR_CHN_MASK GENMASK(25, 23) -#define GLBL2_AXIMM_WR0_WTLP_DATA_FIFO_EP_MASK BIT(22) -#define GLBL2_AXIMM_WR0_WPL_FIFO_EP_MASK BIT(21) -#define GLBL2_AXIMM_WR0_BRSP_CLAIM_CHN_MASK GENMASK(20, 18) -#define GLBL2_AXIMM_WR0_WRREQ_CNT_MASK GENMASK(17, 12) -#define GLBL2_AXIMM_WR0_BID_MASK GENMASK(11, 9) -#define GLBL2_AXIMM_WR0_BVALID_MASK BIT(8) -#define GLBL2_AXIMM_WR0_BREADY_MASK BIT(7) -#define GLBL2_AXIMM_WR0_WVALID_MASK BIT(6) -#define GLBL2_AXIMM_WR0_WREADY_MASK BIT(5) -#define GLBL2_AXIMM_WR0_AWID_MASK GENMASK(4, 2) -#define GLBL2_AXIMM_WR0_AWVALID_MASK BIT(1) -#define GLBL2_AXIMM_WR0_AWREADY_MASK BIT(0) -#define EQDMA_GLBL2_DBG_AXIMM_WR1_ADDR 0x1C4 -#define GLBL2_AXIMM_WR1_RSVD_1_MASK GENMASK(31, 30) -#define GLBL2_AXIMM_WR1_BRSP_CNT4_MASK GENMASK(29, 24) -#define GLBL2_AXIMM_WR1_BRSP_CNT3_MASK GENMASK(23, 18) -#define GLBL2_AXIMM_WR1_BRSP_CNT2_MASK GENMASK(17, 12) -#define GLBL2_AXIMM_WR1_BRSP_CNT1_MASK GENMASK(11, 6) -#define GLBL2_AXIMM_WR1_BRSP_CNT0_MASK GENMASK(5, 0) -#define EQDMA_GLBL2_DBG_AXIMM_RD0_ADDR 0x1C8 -#define GLBL2_AXIMM_RD0_RSVD_1_MASK GENMASK(31, 23) -#define GLBL2_AXIMM_RD0_PND_CNT_MASK GENMASK(22, 17) -#define GLBL2_AXIMM_RD0_RD_REQ_MASK BIT(16) -#define GLBL2_AXIMM_RD0_RD_CHNL_MASK GENMASK(15, 13) -#define GLBL2_AXIMM_RD0_RRSP_CLAIM_CHNL_MASK GENMASK(12, 10) -#define GLBL2_AXIMM_RD0_RID_MASK GENMASK(9, 7) -#define GLBL2_AXIMM_RD0_RVALID_MASK BIT(6) -#define GLBL2_AXIMM_RD0_RREADY_MASK BIT(5) -#define GLBL2_AXIMM_RD0_ARID_MASK GENMASK(4, 2) -#define GLBL2_AXIMM_RD0_ARVALID_MASK BIT(1) -#define GLBL2_AXIMM_RD0_ARREADY_MASK BIT(0) -#define EQDMA_GLBL2_DBG_AXIMM_RD1_ADDR 0x1CC -#define GLBL2_AXIMM_RD1_RSVD_1_MASK GENMASK(31, 30) -#define GLBL2_AXIMM_RD1_RRSP_CNT4_MASK GENMASK(29, 24) -#define GLBL2_AXIMM_RD1_RRSP_CNT3_MASK GENMASK(23, 18) -#define GLBL2_AXIMM_RD1_RRSP_CNT2_MASK GENMASK(17, 12) -#define GLBL2_AXIMM_RD1_RRSP_CNT1_MASK GENMASK(11, 6) -#define GLBL2_AXIMM_RD1_RRSP_CNT0_MASK GENMASK(5, 0) -#define EQDMA_GLBL2_DBG_FAB0_ADDR 0x1D0 -#define GLBL2_FAB0_H2C_INB_CONV_IN_VLD_MASK BIT(31) -#define GLBL2_FAB0_H2C_INB_CONV_IN_RDY_MASK BIT(30) -#define GLBL2_FAB0_H2C_SEG_IN_VLD_MASK BIT(29) -#define GLBL2_FAB0_H2C_SEG_IN_RDY_MASK BIT(28) -#define GLBL2_FAB0_H2C_SEG_OUT_VLD_MASK GENMASK(27, 24) -#define GLBL2_FAB0_H2C_SEG_OUT_RDY_MASK BIT(23) -#define GLBL2_FAB0_H2C_MST_CRDT_STAT_MASK GENMASK(22, 16) -#define GLBL2_FAB0_C2H_SLV_AFIFO_FULL_MASK BIT(15) -#define GLBL2_FAB0_C2H_SLV_AFIFO_EMPTY_MASK BIT(14) -#define GLBL2_FAB0_C2H_DESEG_SEG_VLD_MASK GENMASK(13, 10) -#define GLBL2_FAB0_C2H_DESEG_SEG_RDY_MASK BIT(9) -#define GLBL2_FAB0_C2H_DESEG_OUT_VLD_MASK BIT(8) -#define GLBL2_FAB0_C2H_DESEG_OUT_RDY_MASK BIT(7) -#define GLBL2_FAB0_C2H_INB_DECONV_OUT_VLD_MASK BIT(6) -#define GLBL2_FAB0_C2H_INB_DECONV_OUT_RDY_MASK BIT(5) -#define GLBL2_FAB0_C2H_DSC_CRDT_AFIFO_FULL_MASK BIT(4) -#define GLBL2_FAB0_C2H_DSC_CRDT_AFIFO_EMPTY_MASK BIT(3) -#define GLBL2_FAB0_IRQ_IN_AFIFO_FULL_MASK BIT(2) -#define GLBL2_FAB0_IRQ_IN_AFIFO_EMPTY_MASK BIT(1) -#define GLBL2_FAB0_IMM_CRD_AFIFO_EMPTY_MASK BIT(0) -#define EQDMA_GLBL2_DBG_FAB1_ADDR 0x1D4 -#define GLBL2_FAB1_BYP_OUT_CRDT_STAT_MASK GENMASK(31, 25) -#define GLBL2_FAB1_TM_DSC_STS_CRDT_STAT_MASK GENMASK(24, 18) -#define GLBL2_FAB1_C2H_CMN_AFIFO_FULL_MASK BIT(17) -#define GLBL2_FAB1_C2H_CMN_AFIFO_EMPTY_MASK BIT(16) -#define GLBL2_FAB1_RSVD_1_MASK GENMASK(15, 13) -#define GLBL2_FAB1_C2H_BYP_IN_AFIFO_FULL_MASK BIT(12) -#define GLBL2_FAB1_RSVD_2_MASK GENMASK(11, 9) -#define GLBL2_FAB1_C2H_BYP_IN_AFIFO_EMPTY_MASK BIT(8) -#define GLBL2_FAB1_RSVD_3_MASK GENMASK(7, 5) -#define GLBL2_FAB1_H2C_BYP_IN_AFIFO_FULL_MASK BIT(4) -#define GLBL2_FAB1_RSVD_4_MASK GENMASK(3, 1) -#define GLBL2_FAB1_H2C_BYP_IN_AFIFO_EMPTY_MASK BIT(0) -#define EQDMA_GLBL2_DBG_MATCH_SEL_ADDR 0x1F4 -#define GLBL2_MATCH_SEL_RSV_MASK GENMASK(31, 18) -#define GLBL2_MATCH_SEL_CSR_SEL_MASK GENMASK(17, 13) -#define GLBL2_MATCH_SEL_CSR_EN_MASK BIT(12) -#define GLBL2_MATCH_SEL_ROTATE1_MASK GENMASK(11, 10) -#define GLBL2_MATCH_SEL_ROTATE0_MASK GENMASK(9, 8) -#define GLBL2_MATCH_SEL_SEL_MASK GENMASK(7, 0) -#define EQDMA_GLBL2_DBG_MATCH_MSK_ADDR 0x1F8 -#define GLBL2_MATCH_MSK_MASK GENMASK(31, 0) -#define EQDMA_GLBL2_DBG_MATCH_PAT_ADDR 0x1FC -#define GLBL2_MATCH_PAT_PATTERN_MASK GENMASK(31, 0) -#define EQDMA_GLBL_RNG_SZ_1_ADDR 0x204 -#define GLBL_RNG_SZ_1_RSVD_1_MASK GENMASK(31, 16) -#define GLBL_RNG_SZ_1_RING_SIZE_MASK GENMASK(15, 0) -#define EQDMA_GLBL_RNG_SZ_2_ADDR 0x208 -#define GLBL_RNG_SZ_2_RSVD_1_MASK GENMASK(31, 16) -#define GLBL_RNG_SZ_2_RING_SIZE_MASK GENMASK(15, 0) -#define EQDMA_GLBL_RNG_SZ_3_ADDR 0x20C -#define GLBL_RNG_SZ_3_RSVD_1_MASK GENMASK(31, 16) -#define GLBL_RNG_SZ_3_RING_SIZE_MASK GENMASK(15, 0) -#define EQDMA_GLBL_RNG_SZ_4_ADDR 0x210 -#define GLBL_RNG_SZ_4_RSVD_1_MASK GENMASK(31, 16) -#define GLBL_RNG_SZ_4_RING_SIZE_MASK GENMASK(15, 0) -#define EQDMA_GLBL_RNG_SZ_5_ADDR 0x214 -#define GLBL_RNG_SZ_5_RSVD_1_MASK GENMASK(31, 16) -#define GLBL_RNG_SZ_5_RING_SIZE_MASK GENMASK(15, 0) -#define EQDMA_GLBL_RNG_SZ_6_ADDR 0x218 -#define GLBL_RNG_SZ_6_RSVD_1_MASK GENMASK(31, 16) -#define GLBL_RNG_SZ_6_RING_SIZE_MASK GENMASK(15, 0) -#define EQDMA_GLBL_RNG_SZ_7_ADDR 0x21C -#define GLBL_RNG_SZ_7_RSVD_1_MASK GENMASK(31, 16) -#define GLBL_RNG_SZ_7_RING_SIZE_MASK GENMASK(15, 0) -#define EQDMA_GLBL_RNG_SZ_8_ADDR 0x220 -#define GLBL_RNG_SZ_8_RSVD_1_MASK GENMASK(31, 16) -#define GLBL_RNG_SZ_8_RING_SIZE_MASK GENMASK(15, 0) -#define EQDMA_GLBL_RNG_SZ_9_ADDR 0x224 -#define GLBL_RNG_SZ_9_RSVD_1_MASK GENMASK(31, 16) -#define GLBL_RNG_SZ_9_RING_SIZE_MASK GENMASK(15, 0) -#define EQDMA_GLBL_RNG_SZ_A_ADDR 0x228 -#define GLBL_RNG_SZ_A_RSVD_1_MASK GENMASK(31, 16) -#define GLBL_RNG_SZ_A_RING_SIZE_MASK GENMASK(15, 0) -#define EQDMA_GLBL_RNG_SZ_B_ADDR 0x22C -#define GLBL_RNG_SZ_B_RSVD_1_MASK GENMASK(31, 16) -#define GLBL_RNG_SZ_B_RING_SIZE_MASK GENMASK(15, 0) -#define EQDMA_GLBL_RNG_SZ_C_ADDR 0x230 -#define GLBL_RNG_SZ_C_RSVD_1_MASK GENMASK(31, 16) -#define GLBL_RNG_SZ_C_RING_SIZE_MASK GENMASK(15, 0) -#define EQDMA_GLBL_RNG_SZ_D_ADDR 0x234 -#define GLBL_RNG_SZ_D_RSVD_1_MASK GENMASK(31, 16) -#define GLBL_RNG_SZ_D_RING_SIZE_MASK GENMASK(15, 0) -#define EQDMA_GLBL_RNG_SZ_E_ADDR 0x238 -#define GLBL_RNG_SZ_E_RSVD_1_MASK GENMASK(31, 16) -#define GLBL_RNG_SZ_E_RING_SIZE_MASK GENMASK(15, 0) -#define EQDMA_GLBL_RNG_SZ_F_ADDR 0x23C -#define GLBL_RNG_SZ_F_RSVD_1_MASK GENMASK(31, 16) -#define GLBL_RNG_SZ_F_RING_SIZE_MASK GENMASK(15, 0) -#define EQDMA_GLBL_RNG_SZ_10_ADDR 0x240 -#define GLBL_RNG_SZ_10_RSVD_1_MASK GENMASK(31, 16) -#define GLBL_RNG_SZ_10_RING_SIZE_MASK GENMASK(15, 0) -#define EQDMA_GLBL_ERR_STAT_ADDR 0x248 -#define GLBL_ERR_STAT_RSVD_1_MASK GENMASK(31, 18) -#define GLBL_ERR_STAT_ERR_FAB_MASK BIT(17) -#define GLBL_ERR_STAT_ERR_H2C_ST_MASK BIT(16) -#define GLBL_ERR_STAT_ERR_BDG_MASK BIT(15) -#define GLBL_ERR_STAT_IND_CTXT_CMD_ERR_MASK GENMASK(14, 9) -#define GLBL_ERR_STAT_ERR_C2H_ST_MASK BIT(8) -#define GLBL_ERR_STAT_ERR_C2H_MM_1_MASK BIT(7) -#define GLBL_ERR_STAT_ERR_C2H_MM_0_MASK BIT(6) -#define GLBL_ERR_STAT_ERR_H2C_MM_1_MASK BIT(5) -#define GLBL_ERR_STAT_ERR_H2C_MM_0_MASK BIT(4) -#define GLBL_ERR_STAT_ERR_TRQ_MASK BIT(3) -#define GLBL_ERR_STAT_ERR_DSC_MASK BIT(2) -#define GLBL_ERR_STAT_ERR_RAM_DBE_MASK BIT(1) -#define GLBL_ERR_STAT_ERR_RAM_SBE_MASK BIT(0) -#define EQDMA_GLBL_ERR_MASK_ADDR 0x24C -#define GLBL_ERR_MASK GENMASK(31, 0) -#define EQDMA_GLBL_DSC_CFG_ADDR 0x250 -#define GLBL_DSC_CFG_RSVD_1_MASK GENMASK(31, 10) -#define GLBL_DSC_CFG_UNC_OVR_COR_MASK BIT(9) -#define GLBL_DSC_CFG_CTXT_FER_DIS_MASK BIT(8) -#define GLBL_DSC_CFG_RSVD_2_MASK GENMASK(7, 6) -#define GLBL_DSC_CFG_MAXFETCH_MASK GENMASK(5, 3) -#define GLBL_DSC_CFG_WB_ACC_INT_MASK GENMASK(2, 0) -#define EQDMA_GLBL_DSC_ERR_STS_ADDR 0x254 -#define GLBL_DSC_ERR_STS_RSVD_1_MASK GENMASK(31, 26) -#define GLBL_DSC_ERR_STS_PORT_ID_MASK BIT(25) -#define GLBL_DSC_ERR_STS_SBE_MASK BIT(24) -#define GLBL_DSC_ERR_STS_DBE_MASK BIT(23) -#define GLBL_DSC_ERR_STS_RQ_CANCEL_MASK BIT(22) -#define GLBL_DSC_ERR_STS_DSC_MASK BIT(21) -#define GLBL_DSC_ERR_STS_DMA_MASK BIT(20) -#define GLBL_DSC_ERR_STS_FLR_CANCEL_MASK BIT(19) -#define GLBL_DSC_ERR_STS_RSVD_2_MASK GENMASK(18, 17) -#define GLBL_DSC_ERR_STS_DAT_POISON_MASK BIT(16) -#define GLBL_DSC_ERR_STS_TIMEOUT_MASK BIT(9) -#define GLBL_DSC_ERR_STS_FLR_MASK BIT(8) -#define GLBL_DSC_ERR_STS_TAG_MASK BIT(6) -#define GLBL_DSC_ERR_STS_ADDR_MASK BIT(5) -#define GLBL_DSC_ERR_STS_PARAM_MASK BIT(4) -#define GLBL_DSC_ERR_STS_BCNT_MASK BIT(3) -#define GLBL_DSC_ERR_STS_UR_CA_MASK BIT(2) -#define GLBL_DSC_ERR_STS_POISON_MASK BIT(1) -#define EQDMA_GLBL_DSC_ERR_MSK_ADDR 0x258 -#define GLBL_DSC_ERR_MSK_MASK GENMASK(31, 0) -#define EQDMA_GLBL_DSC_ERR_LOG0_ADDR 0x25C -#define GLBL_DSC_ERR_LOG0_VALID_MASK BIT(31) -#define GLBL_DSC_ERR_LOG0_SEL_MASK BIT(30) -#define GLBL_DSC_ERR_LOG0_RSVD_1_MASK GENMASK(29, 13) -#define GLBL_DSC_ERR_LOG0_QID_MASK GENMASK(12, 0) -#define EQDMA_GLBL_DSC_ERR_LOG1_ADDR 0x260 -#define GLBL_DSC_ERR_LOG1_RSVD_1_MASK GENMASK(31, 28) -#define GLBL_DSC_ERR_LOG1_CIDX_MASK GENMASK(27, 12) -#define GLBL_DSC_ERR_LOG1_RSVD_2_MASK GENMASK(11, 9) -#define GLBL_DSC_ERR_LOG1_SUB_TYPE_MASK GENMASK(8, 5) -#define GLBL_DSC_ERR_LOG1_ERR_TYPE_MASK GENMASK(4, 0) -#define EQDMA_GLBL_TRQ_ERR_STS_ADDR 0x264 -#define GLBL_TRQ_ERR_STS_RSVD_1_MASK GENMASK(31, 8) -#define GLBL_TRQ_ERR_STS_TCP_QSPC_TIMEOUT_MASK BIT(7) -#define GLBL_TRQ_ERR_STS_RSVD_2_MASK BIT(6) -#define GLBL_TRQ_ERR_STS_QID_RANGE_MASK BIT(5) -#define GLBL_TRQ_ERR_STS_QSPC_UNMAPPED_MASK BIT(4) -#define GLBL_TRQ_ERR_STS_TCP_CSR_TIMEOUT_MASK BIT(3) -#define GLBL_TRQ_ERR_STS_RSVD_3_MASK BIT(2) -#define GLBL_TRQ_ERR_STS_VF_ACCESS_ERR_MASK BIT(1) -#define GLBL_TRQ_ERR_STS_CSR_UNMAPPED_MASK BIT(0) -#define EQDMA_GLBL_TRQ_ERR_MSK_ADDR 0x268 -#define GLBL_TRQ_ERR_MSK_MASK GENMASK(31, 0) -#define EQDMA_GLBL_TRQ_ERR_LOG_ADDR 0x26C -#define GLBL_TRQ_ERR_LOG_SRC_MASK BIT(31) -#define GLBL_TRQ_ERR_LOG_TARGET_MASK GENMASK(30, 27) -#define GLBL_TRQ_ERR_LOG_FUNC_MASK GENMASK(26, 17) -#define GLBL_TRQ_ERR_LOG_ADDRESS_MASK GENMASK(16, 0) -#define EQDMA_GLBL_DSC_DBG_DAT0_ADDR 0x270 -#define GLBL_DSC_DAT0_RSVD_1_MASK GENMASK(31, 30) -#define GLBL_DSC_DAT0_CTXT_ARB_DIR_MASK BIT(29) -#define GLBL_DSC_DAT0_CTXT_ARB_QID_MASK GENMASK(28, 17) -#define GLBL_DSC_DAT0_CTXT_ARB_REQ_MASK GENMASK(16, 12) -#define GLBL_DSC_DAT0_IRQ_FIFO_FL_MASK BIT(11) -#define GLBL_DSC_DAT0_TMSTALL_MASK BIT(10) -#define GLBL_DSC_DAT0_RRQ_STALL_MASK GENMASK(9, 8) -#define GLBL_DSC_DAT0_RCP_FIFO_SPC_STALL_MASK GENMASK(7, 6) -#define GLBL_DSC_DAT0_RRQ_FIFO_SPC_STALL_MASK GENMASK(5, 4) -#define GLBL_DSC_DAT0_FAB_MRKR_RSP_STALL_MASK GENMASK(3, 2) -#define GLBL_DSC_DAT0_DSC_OUT_STALL_MASK GENMASK(1, 0) -#define EQDMA_GLBL_DSC_DBG_DAT1_ADDR 0x274 -#define GLBL_DSC_DAT1_RSVD_1_MASK GENMASK(31, 28) -#define GLBL_DSC_DAT1_EVT_SPC_C2H_MASK GENMASK(27, 22) -#define GLBL_DSC_DAT1_EVT_SP_H2C_MASK GENMASK(21, 16) -#define GLBL_DSC_DAT1_DSC_SPC_C2H_MASK GENMASK(15, 8) -#define GLBL_DSC_DAT1_DSC_SPC_H2C_MASK GENMASK(7, 0) -#define EQDMA_GLBL_DSC_DBG_CTL_ADDR 0x278 -#define GLBL_DSC_CTL_RSVD_1_MASK GENMASK(31, 3) -#define GLBL_DSC_CTL_SELECT_MASK GENMASK(2, 0) -#define EQDMA_GLBL_DSC_ERR_LOG2_ADDR 0x27c -#define GLBL_DSC_ERR_LOG2_OLD_PIDX_MASK GENMASK(31, 16) -#define GLBL_DSC_ERR_LOG2_NEW_PIDX_MASK GENMASK(15, 0) -#define EQDMA_GLBL_GLBL_INTERRUPT_CFG_ADDR 0x2c4 -#define GLBL_GLBL_INTERRUPT_CFG_RSVD_1_MASK GENMASK(31, 2) -#define GLBL_GLBL_INTERRUPT_CFG_LGCY_INTR_PENDING_MASK BIT(1) -#define GLBL_GLBL_INTERRUPT_CFG_EN_LGCY_INTR_MASK BIT(0) -#define EQDMA_GLBL_VCH_HOST_PROFILE_ADDR 0x2c8 -#define GLBL_VCH_HOST_PROFILE_RSVD_1_MASK GENMASK(31, 28) -#define GLBL_VCH_HOST_PROFILE_2C_MM_MASK GENMASK(27, 24) -#define GLBL_VCH_HOST_PROFILE_2C_ST_MASK GENMASK(23, 20) -#define GLBL_VCH_HOST_PROFILE_VCH_DSC_MASK GENMASK(19, 16) -#define GLBL_VCH_HOST_PROFILE_VCH_INT_MSG_MASK GENMASK(15, 12) -#define GLBL_VCH_HOST_PROFILE_VCH_INT_AGGR_MASK GENMASK(11, 8) -#define GLBL_VCH_HOST_PROFILE_VCH_CMPT_MASK GENMASK(7, 4) -#define GLBL_VCH_HOST_PROFILE_VCH_C2H_PLD_MASK GENMASK(3, 0) -#define EQDMA_GLBL_BRIDGE_HOST_PROFILE_ADDR 0x308 -#define GLBL_BRIDGE_HOST_PROFILE_RSVD_1_MASK GENMASK(31, 4) -#define GLBL_BRIDGE_HOST_PROFILE_BDGID_MASK GENMASK(3, 0) -#define EQDMA_AXIMM_IRQ_DEST_ADDR_ADDR 0x30c -#define AXIMM_IRQ_DEST_ADDR_ADDR_MASK GENMASK(31, 0) -#define EQDMA_FAB_ERR_LOG_ADDR 0x314 -#define FAB_ERR_LOG_RSVD_1_MASK GENMASK(31, 7) -#define FAB_ERR_LOG_SRC_MASK GENMASK(6, 0) -#define EQDMA_GLBL_REQ_ERR_STS_ADDR 0x318 -#define GLBL_REQ_ERR_STS_RSVD_1_MASK GENMASK(31, 11) -#define GLBL_REQ_ERR_STS_RC_DISCONTINUE_MASK BIT(10) -#define GLBL_REQ_ERR_STS_RC_PRTY_MASK BIT(9) -#define GLBL_REQ_ERR_STS_RC_FLR_MASK BIT(8) -#define GLBL_REQ_ERR_STS_RC_TIMEOUT_MASK BIT(7) -#define GLBL_REQ_ERR_STS_RC_INV_BCNT_MASK BIT(6) -#define GLBL_REQ_ERR_STS_RC_INV_TAG_MASK BIT(5) -#define GLBL_REQ_ERR_STS_RC_START_ADDR_MISMCH_MASK BIT(4) -#define GLBL_REQ_ERR_STS_RC_RID_TC_ATTR_MISMCH_MASK BIT(3) -#define GLBL_REQ_ERR_STS_RC_NO_DATA_MASK BIT(2) -#define GLBL_REQ_ERR_STS_RC_UR_CA_CRS_MASK BIT(1) -#define GLBL_REQ_ERR_STS_RC_POISONED_MASK BIT(0) -#define EQDMA_GLBL_REQ_ERR_MSK_ADDR 0x31C -#define GLBL_REQ_ERR_MSK_MASK GENMASK(31, 0) -#define EQDMA_IND_CTXT_DATA_ADDR 0x804 -#define IND_CTXT_DATA_DATA_MASK GENMASK(31, 0) -#define EQDMA_IND_CTXT_MASK_ADDR 0x824 -#define IND_CTXT_MASK GENMASK(31, 0) -#define EQDMA_IND_CTXT_CMD_ADDR 0x844 -#define IND_CTXT_CMD_RSVD_1_MASK GENMASK(31, 20) -#define IND_CTXT_CMD_QID_MASK GENMASK(19, 7) -#define IND_CTXT_CMD_OP_MASK GENMASK(6, 5) -#define IND_CTXT_CMD_SEL_MASK GENMASK(4, 1) -#define IND_CTXT_CMD_BUSY_MASK BIT(0) -#define EQDMA_C2H_TIMER_CNT_ADDR 0xA00 -#define C2H_TIMER_CNT_RSVD_1_MASK GENMASK(31, 16) -#define C2H_TIMER_CNT_MASK GENMASK(15, 0) -#define EQDMA_C2H_CNT_TH_ADDR 0xA40 -#define C2H_CNT_TH_RSVD_1_MASK GENMASK(31, 16) -#define C2H_CNT_TH_THESHOLD_CNT_MASK GENMASK(15, 0) -#define EQDMA_C2H_STAT_S_AXIS_C2H_ACCEPTED_ADDR 0xA88 -#define C2H_STAT_S_AXIS_C2H_ACCEPTED_MASK GENMASK(31, 0) -#define EQDMA_C2H_STAT_S_AXIS_WRB_ACCEPTED_ADDR 0xA8C -#define C2H_STAT_S_AXIS_WRB_ACCEPTED_MASK GENMASK(31, 0) -#define EQDMA_C2H_STAT_DESC_RSP_PKT_ACCEPTED_ADDR 0xA90 -#define C2H_STAT_DESC_RSP_PKT_ACCEPTED_D_MASK GENMASK(31, 0) -#define EQDMA_C2H_STAT_AXIS_PKG_CMP_ADDR 0xA94 -#define C2H_STAT_AXIS_PKG_CMP_MASK GENMASK(31, 0) -#define EQDMA_C2H_STAT_DESC_RSP_ACCEPTED_ADDR 0xA98 -#define C2H_STAT_DESC_RSP_ACCEPTED_D_MASK GENMASK(31, 0) -#define EQDMA_C2H_STAT_DESC_RSP_CMP_ADDR 0xA9C -#define C2H_STAT_DESC_RSP_CMP_D_MASK GENMASK(31, 0) -#define EQDMA_C2H_STAT_WRQ_OUT_ADDR 0xAA0 -#define C2H_STAT_WRQ_OUT_MASK GENMASK(31, 0) -#define EQDMA_C2H_STAT_WPL_REN_ACCEPTED_ADDR 0xAA4 -#define C2H_STAT_WPL_REN_ACCEPTED_MASK GENMASK(31, 0) -#define EQDMA_C2H_STAT_TOTAL_WRQ_LEN_ADDR 0xAA8 -#define C2H_STAT_TOTAL_WRQ_LEN_MASK GENMASK(31, 0) -#define EQDMA_C2H_STAT_TOTAL_WPL_LEN_ADDR 0xAAC -#define C2H_STAT_TOTAL_WPL_LEN_MASK GENMASK(31, 0) -#define EQDMA_C2H_BUF_SZ_ADDR 0xAB0 -#define C2H_BUF_SZ_IZE_MASK GENMASK(31, 0) -#define EQDMA_C2H_ERR_STAT_ADDR 0xAF0 -#define C2H_ERR_STAT_RSVD_1_MASK GENMASK(31, 21) -#define C2H_ERR_STAT_WRB_PORT_ID_ERR_MASK BIT(20) -#define C2H_ERR_STAT_HDR_PAR_ERR_MASK BIT(19) -#define C2H_ERR_STAT_HDR_ECC_COR_ERR_MASK BIT(18) -#define C2H_ERR_STAT_HDR_ECC_UNC_ERR_MASK BIT(17) -#define C2H_ERR_STAT_AVL_RING_DSC_ERR_MASK BIT(16) -#define C2H_ERR_STAT_WRB_PRTY_ERR_MASK BIT(15) -#define C2H_ERR_STAT_WRB_CIDX_ERR_MASK BIT(14) -#define C2H_ERR_STAT_WRB_QFULL_ERR_MASK BIT(13) -#define C2H_ERR_STAT_WRB_INV_Q_ERR_MASK BIT(12) -#define C2H_ERR_STAT_RSVD_2_MASK BIT(11) -#define C2H_ERR_STAT_PORT_ID_CTXT_MISMATCH_MASK BIT(10) -#define C2H_ERR_STAT_ERR_DESC_CNT_MASK BIT(9) -#define C2H_ERR_STAT_RSVD_3_MASK BIT(8) -#define C2H_ERR_STAT_MSI_INT_FAIL_MASK BIT(7) -#define C2H_ERR_STAT_ENG_WPL_DATA_PAR_ERR_MASK BIT(6) -#define C2H_ERR_STAT_RSVD_4_MASK BIT(5) -#define C2H_ERR_STAT_DESC_RSP_ERR_MASK BIT(4) -#define C2H_ERR_STAT_QID_MISMATCH_MASK BIT(3) -#define C2H_ERR_STAT_SH_CMPT_DSC_ERR_MASK BIT(2) -#define C2H_ERR_STAT_LEN_MISMATCH_MASK BIT(1) -#define C2H_ERR_STAT_MTY_MISMATCH_MASK BIT(0) -#define EQDMA_C2H_ERR_MASK_ADDR 0xAF4 -#define C2H_ERR_EN_MASK GENMASK(31, 0) -#define EQDMA_C2H_FATAL_ERR_STAT_ADDR 0xAF8 -#define C2H_FATAL_ERR_STAT_RSVD_1_MASK GENMASK(31, 21) -#define C2H_FATAL_ERR_STAT_HDR_ECC_UNC_ERR_MASK BIT(20) -#define C2H_FATAL_ERR_STAT_AVL_RING_FIFO_RAM_RDBE_MASK BIT(19) -#define C2H_FATAL_ERR_STAT_WPL_DATA_PAR_ERR_MASK BIT(18) -#define C2H_FATAL_ERR_STAT_PLD_FIFO_RAM_RDBE_MASK BIT(17) -#define C2H_FATAL_ERR_STAT_QID_FIFO_RAM_RDBE_MASK BIT(16) -#define C2H_FATAL_ERR_STAT_CMPT_FIFO_RAM_RDBE_MASK BIT(15) -#define C2H_FATAL_ERR_STAT_WRB_COAL_DATA_RAM_RDBE_MASK BIT(14) -#define C2H_FATAL_ERR_STAT_RESERVED2_MASK BIT(13) -#define C2H_FATAL_ERR_STAT_INT_CTXT_RAM_RDBE_MASK BIT(12) -#define C2H_FATAL_ERR_STAT_DESC_REQ_FIFO_RAM_RDBE_MASK BIT(11) -#define C2H_FATAL_ERR_STAT_PFCH_CTXT_RAM_RDBE_MASK BIT(10) -#define C2H_FATAL_ERR_STAT_WRB_CTXT_RAM_RDBE_MASK BIT(9) -#define C2H_FATAL_ERR_STAT_PFCH_LL_RAM_RDBE_MASK BIT(8) -#define C2H_FATAL_ERR_STAT_TIMER_FIFO_RAM_RDBE_MASK GENMASK(7, 4) -#define C2H_FATAL_ERR_STAT_QID_MISMATCH_MASK BIT(3) -#define C2H_FATAL_ERR_STAT_RESERVED1_MASK BIT(2) -#define C2H_FATAL_ERR_STAT_LEN_MISMATCH_MASK BIT(1) -#define C2H_FATAL_ERR_STAT_MTY_MISMATCH_MASK BIT(0) -#define EQDMA_C2H_FATAL_ERR_MASK_ADDR 0xAFC -#define C2H_FATAL_ERR_C2HEN_MASK GENMASK(31, 0) -#define EQDMA_C2H_FATAL_ERR_ENABLE_ADDR 0xB00 -#define C2H_FATAL_ERR_ENABLE_RSVD_1_MASK GENMASK(31, 2) -#define C2H_FATAL_ERR_ENABLE_WPL_PAR_INV_MASK BIT(1) -#define C2H_FATAL_ERR_ENABLE_WRQ_DIS_MASK BIT(0) -#define EQDMA_GLBL_ERR_INT_ADDR 0xB04 -#define GLBL_ERR_INT_RSVD_1_MASK GENMASK(31, 30) -#define GLBL_ERR_INT_HOST_ID_MASK GENMASK(29, 26) -#define GLBL_ERR_INT_DIS_INTR_ON_VF_MASK BIT(25) -#define GLBL_ERR_INT_ARM_MASK BIT(24) -#define GLBL_ERR_INT_EN_COAL_MASK BIT(23) -#define GLBL_ERR_INT_VEC_MASK GENMASK(22, 12) -#define GLBL_ERR_INT_FUNC_MASK GENMASK(11, 0) -#define EQDMA_C2H_PFCH_CFG_ADDR 0xB08 -#define C2H_PFCH_CFG_EVTFL_TH_MASK GENMASK(31, 16) -#define C2H_PFCH_CFG_FL_TH_MASK GENMASK(15, 0) -#define EQDMA_C2H_PFCH_CFG_1_ADDR 0xA80 -#define C2H_PFCH_CFG_1_EVT_QCNT_TH_MASK GENMASK(31, 16) -#define C2H_PFCH_CFG_1_QCNT_MASK GENMASK(15, 0) -#define EQDMA_C2H_PFCH_CFG_2_ADDR 0xA84 -#define C2H_PFCH_CFG_2_FENCE_MASK BIT(31) -#define C2H_PFCH_CFG_2_RSVD_MASK GENMASK(30, 29) -#define C2H_PFCH_CFG_2_VAR_DESC_NO_DROP_MASK BIT(28) -#define C2H_PFCH_CFG_2_LL_SZ_TH_MASK GENMASK(27, 12) -#define C2H_PFCH_CFG_2_VAR_DESC_NUM_MASK GENMASK(11, 6) -#define C2H_PFCH_CFG_2_NUM_MASK GENMASK(5, 0) -#define EQDMA_C2H_INT_TIMER_TICK_ADDR 0xB0C -#define C2H_INT_TIMER_TICK_MASK GENMASK(31, 0) -#define EQDMA_C2H_STAT_DESC_RSP_DROP_ACCEPTED_ADDR 0xB10 -#define C2H_STAT_DESC_RSP_DROP_ACCEPTED_D_MASK GENMASK(31, 0) -#define EQDMA_C2H_STAT_DESC_RSP_ERR_ACCEPTED_ADDR 0xB14 -#define C2H_STAT_DESC_RSP_ERR_ACCEPTED_D_MASK GENMASK(31, 0) -#define EQDMA_C2H_STAT_DESC_REQ_ADDR 0xB18 -#define C2H_STAT_DESC_REQ_MASK GENMASK(31, 0) -#define EQDMA_C2H_STAT_DBG_DMA_ENG_0_ADDR 0xB1C -#define C2H_STAT_DMA_ENG_0_S_AXIS_C2H_TVALID_MASK BIT(31) -#define C2H_STAT_DMA_ENG_0_S_AXIS_C2H_TREADY_MASK BIT(30) -#define C2H_STAT_DMA_ENG_0_S_AXIS_WRB_TVALID_MASK GENMASK(29, 27) -#define C2H_STAT_DMA_ENG_0_S_AXIS_WRB_TREADY_MASK GENMASK(26, 24) -#define C2H_STAT_DMA_ENG_0_PLD_FIFO_IN_RDY_MASK BIT(23) -#define C2H_STAT_DMA_ENG_0_QID_FIFO_IN_RDY_MASK BIT(22) -#define C2H_STAT_DMA_ENG_0_ARB_FIFO_OUT_VLD_MASK BIT(21) -#define C2H_STAT_DMA_ENG_0_ARB_FIFO_OUT_QID_MASK GENMASK(20, 9) -#define C2H_STAT_DMA_ENG_0_WRB_FIFO_IN_RDY_MASK BIT(8) -#define C2H_STAT_DMA_ENG_0_WRB_FIFO_OUT_CNT_MASK GENMASK(7, 5) -#define C2H_STAT_DMA_ENG_0_WRB_SM_CS_MASK BIT(4) -#define C2H_STAT_DMA_ENG_0_MAIN_SM_CS_MASK GENMASK(3, 0) -#define EQDMA_C2H_STAT_DBG_DMA_ENG_1_ADDR 0xB20 -#define C2H_STAT_DMA_ENG_1_RSVD_1_MASK GENMASK(31, 29) -#define C2H_STAT_DMA_ENG_1_QID_FIFO_OUT_CNT_MASK GENMASK(28, 18) -#define C2H_STAT_DMA_ENG_1_PLD_FIFO_OUT_CNT_MASK GENMASK(17, 7) -#define C2H_STAT_DMA_ENG_1_PLD_ST_FIFO_CNT_MASK GENMASK(6, 0) -#define EQDMA_C2H_STAT_DBG_DMA_ENG_2_ADDR 0xB24 -#define C2H_STAT_DMA_ENG_2_RSVD_1_MASK GENMASK(31, 29) -#define C2H_STAT_DMA_ENG_2_QID_FIFO_OUT_CNT_MASK GENMASK(28, 18) -#define C2H_STAT_DMA_ENG_2_PLD_FIFO_OUT_CNT_MASK GENMASK(17, 7) -#define C2H_STAT_DMA_ENG_2_PLD_ST_FIFO_CNT_MASK GENMASK(6, 0) -#define EQDMA_C2H_STAT_DBG_DMA_ENG_3_ADDR 0xB28 -#define C2H_STAT_DMA_ENG_3_RSVD_1_MASK GENMASK(31, 24) -#define C2H_STAT_DMA_ENG_3_WRQ_FIFO_OUT_CNT_MASK GENMASK(23, 19) -#define C2H_STAT_DMA_ENG_3_QID_FIFO_OUT_VLD_MASK BIT(18) -#define C2H_STAT_DMA_ENG_3_PLD_FIFO_OUT_VLD_MASK BIT(17) -#define C2H_STAT_DMA_ENG_3_PLD_ST_FIFO_OUT_VLD_MASK BIT(16) -#define C2H_STAT_DMA_ENG_3_PLD_ST_FIFO_OUT_DATA_EOP_MASK BIT(15) -#define C2H_STAT_DMA_ENG_3_PLD_ST_FIFO_OUT_DATA_AVL_IDX_ENABLE_MASK BIT(14) -#define C2H_STAT_DMA_ENG_3_PLD_ST_FIFO_OUT_DATA_DROP_MASK BIT(13) -#define C2H_STAT_DMA_ENG_3_PLD_ST_FIFO_OUT_DATA_ERR_MASK BIT(12) -#define C2H_STAT_DMA_ENG_3_DESC_CNT_FIFO_IN_RDY_MASK BIT(11) -#define C2H_STAT_DMA_ENG_3_DESC_RSP_FIFO_IN_RDY_MASK BIT(10) -#define C2H_STAT_DMA_ENG_3_PLD_PKT_ID_LARGER_0_MASK BIT(9) -#define C2H_STAT_DMA_ENG_3_WRQ_VLD_MASK BIT(8) -#define C2H_STAT_DMA_ENG_3_WRQ_RDY_MASK BIT(7) -#define C2H_STAT_DMA_ENG_3_WRQ_FIFO_OUT_RDY_MASK BIT(6) -#define C2H_STAT_DMA_ENG_3_WRQ_PACKET_OUT_DATA_DROP_MASK BIT(5) -#define C2H_STAT_DMA_ENG_3_WRQ_PACKET_OUT_DATA_ERR_MASK BIT(4) -#define C2H_STAT_DMA_ENG_3_WRQ_PACKET_OUT_DATA_MARKER_MASK BIT(3) -#define C2H_STAT_DMA_ENG_3_WRQ_PACKET_PRE_EOR_MASK BIT(2) -#define C2H_STAT_DMA_ENG_3_WCP_FIFO_IN_RDY_MASK BIT(1) -#define C2H_STAT_DMA_ENG_3_PLD_ST_FIFO_IN_RDY_MASK BIT(0) -#define EQDMA_C2H_DBG_PFCH_ERR_CTXT_ADDR 0xB2C -#define C2H_PFCH_ERR_CTXT_RSVD_1_MASK GENMASK(31, 14) -#define C2H_PFCH_ERR_CTXT_ERR_STAT_MASK BIT(13) -#define C2H_PFCH_ERR_CTXT_CMD_WR_MASK BIT(12) -#define C2H_PFCH_ERR_CTXT_QID_MASK GENMASK(11, 1) -#define C2H_PFCH_ERR_CTXT_DONE_MASK BIT(0) -#define EQDMA_C2H_FIRST_ERR_QID_ADDR 0xB30 -#define C2H_FIRST_ERR_QID_RSVD_1_MASK GENMASK(31, 21) -#define C2H_FIRST_ERR_QID_ERR_TYPE_MASK GENMASK(20, 16) -#define C2H_FIRST_ERR_QID_RSVD_MASK GENMASK(15, 13) -#define C2H_FIRST_ERR_QID_QID_MASK GENMASK(12, 0) -#define EQDMA_STAT_NUM_WRB_IN_ADDR 0xB34 -#define STAT_NUM_WRB_IN_RSVD_1_MASK GENMASK(31, 16) -#define STAT_NUM_WRB_IN_WRB_CNT_MASK GENMASK(15, 0) -#define EQDMA_STAT_NUM_WRB_OUT_ADDR 0xB38 -#define STAT_NUM_WRB_OUT_RSVD_1_MASK GENMASK(31, 16) -#define STAT_NUM_WRB_OUT_WRB_CNT_MASK GENMASK(15, 0) -#define EQDMA_STAT_NUM_WRB_DRP_ADDR 0xB3C -#define STAT_NUM_WRB_DRP_RSVD_1_MASK GENMASK(31, 16) -#define STAT_NUM_WRB_DRP_WRB_CNT_MASK GENMASK(15, 0) -#define EQDMA_STAT_NUM_STAT_DESC_OUT_ADDR 0xB40 -#define STAT_NUM_STAT_DESC_OUT_RSVD_1_MASK GENMASK(31, 16) -#define STAT_NUM_STAT_DESC_OUT_CNT_MASK GENMASK(15, 0) -#define EQDMA_STAT_NUM_DSC_CRDT_SENT_ADDR 0xB44 -#define STAT_NUM_DSC_CRDT_SENT_RSVD_1_MASK GENMASK(31, 16) -#define STAT_NUM_DSC_CRDT_SENT_CNT_MASK GENMASK(15, 0) -#define EQDMA_STAT_NUM_FCH_DSC_RCVD_ADDR 0xB48 -#define STAT_NUM_FCH_DSC_RCVD_RSVD_1_MASK GENMASK(31, 16) -#define STAT_NUM_FCH_DSC_RCVD_DSC_CNT_MASK GENMASK(15, 0) -#define EQDMA_STAT_NUM_BYP_DSC_RCVD_ADDR 0xB4C -#define STAT_NUM_BYP_DSC_RCVD_RSVD_1_MASK GENMASK(31, 11) -#define STAT_NUM_BYP_DSC_RCVD_DSC_CNT_MASK GENMASK(10, 0) -#define EQDMA_C2H_WRB_COAL_CFG_ADDR 0xB50 -#define C2H_WRB_COAL_CFG_MAX_BUF_SZ_MASK GENMASK(31, 26) -#define C2H_WRB_COAL_CFG_TICK_VAL_MASK GENMASK(25, 14) -#define C2H_WRB_COAL_CFG_TICK_CNT_MASK GENMASK(13, 2) -#define C2H_WRB_COAL_CFG_SET_GLB_FLUSH_MASK BIT(1) -#define C2H_WRB_COAL_CFG_DONE_GLB_FLUSH_MASK BIT(0) -#define EQDMA_C2H_INTR_H2C_REQ_ADDR 0xB54 -#define C2H_INTR_H2C_REQ_RSVD_1_MASK GENMASK(31, 18) -#define C2H_INTR_H2C_REQ_CNT_MASK GENMASK(17, 0) -#define EQDMA_C2H_INTR_C2H_MM_REQ_ADDR 0xB58 -#define C2H_INTR_C2H_MM_REQ_RSVD_1_MASK GENMASK(31, 18) -#define C2H_INTR_C2H_MM_REQ_CNT_MASK GENMASK(17, 0) -#define EQDMA_C2H_INTR_ERR_INT_REQ_ADDR 0xB5C -#define C2H_INTR_ERR_INT_REQ_RSVD_1_MASK GENMASK(31, 18) -#define C2H_INTR_ERR_INT_REQ_CNT_MASK GENMASK(17, 0) -#define EQDMA_C2H_INTR_C2H_ST_REQ_ADDR 0xB60 -#define C2H_INTR_C2H_ST_REQ_RSVD_1_MASK GENMASK(31, 18) -#define C2H_INTR_C2H_ST_REQ_CNT_MASK GENMASK(17, 0) -#define EQDMA_C2H_INTR_H2C_ERR_C2H_MM_MSIX_ACK_ADDR 0xB64 -#define C2H_INTR_H2C_ERR_C2H_MM_MSIX_ACK_RSVD_1_MASK GENMASK(31, 18) -#define C2H_INTR_H2C_ERR_C2H_MM_MSIX_ACK_CNT_MASK GENMASK(17, 0) -#define EQDMA_C2H_INTR_H2C_ERR_C2H_MM_MSIX_FAIL_ADDR 0xB68 -#define C2H_INTR_H2C_ERR_C2H_MM_MSIX_FAIL_RSVD_1_MASK GENMASK(31, 18) -#define C2H_INTR_H2C_ERR_C2H_MM_MSIX_FAIL_CNT_MASK GENMASK(17, 0) -#define EQDMA_C2H_INTR_H2C_ERR_C2H_MM_MSIX_NO_MSIX_ADDR 0xB6C -#define C2H_INTR_H2C_ERR_C2H_MM_MSIX_NO_MSIX_RSVD_1_MASK GENMASK(31, 18) -#define C2H_INTR_H2C_ERR_C2H_MM_MSIX_NO_MSIX_CNT_MASK GENMASK(17, 0) -#define EQDMA_C2H_INTR_H2C_ERR_C2H_MM_CTXT_INVAL_ADDR 0xB70 -#define C2H_INTR_H2C_ERR_C2H_MM_CTXT_INVAL_RSVD_1_MASK GENMASK(31, 18) -#define C2H_INTR_H2C_ERR_C2H_MM_CTXT_INVAL_CNT_MASK GENMASK(17, 0) -#define EQDMA_C2H_INTR_C2H_ST_MSIX_ACK_ADDR 0xB74 -#define C2H_INTR_C2H_ST_MSIX_ACK_RSVD_1_MASK GENMASK(31, 18) -#define C2H_INTR_C2H_ST_MSIX_ACK_CNT_MASK GENMASK(17, 0) -#define EQDMA_C2H_INTR_C2H_ST_MSIX_FAIL_ADDR 0xB78 -#define C2H_INTR_C2H_ST_MSIX_FAIL_RSVD_1_MASK GENMASK(31, 18) -#define C2H_INTR_C2H_ST_MSIX_FAIL_CNT_MASK GENMASK(17, 0) -#define EQDMA_C2H_INTR_C2H_ST_NO_MSIX_ADDR 0xB7C -#define C2H_INTR_C2H_ST_NO_MSIX_RSVD_1_MASK GENMASK(31, 18) -#define C2H_INTR_C2H_ST_NO_MSIX_CNT_MASK GENMASK(17, 0) -#define EQDMA_C2H_INTR_C2H_ST_CTXT_INVAL_ADDR 0xB80 -#define C2H_INTR_C2H_ST_CTXT_INVAL_RSVD_1_MASK GENMASK(31, 18) -#define C2H_INTR_C2H_ST_CTXT_INVAL_CNT_MASK GENMASK(17, 0) -#define EQDMA_C2H_STAT_WR_CMP_ADDR 0xB84 -#define C2H_STAT_WR_CMP_RSVD_1_MASK GENMASK(31, 18) -#define C2H_STAT_WR_CMP_CNT_MASK GENMASK(17, 0) -#define EQDMA_C2H_STAT_DBG_DMA_ENG_4_ADDR 0xB88 -#define C2H_STAT_DMA_ENG_4_RSVD_1_MASK GENMASK(31, 24) -#define C2H_STAT_DMA_ENG_4_WRQ_FIFO_OUT_CNT_MASK GENMASK(23, 19) -#define C2H_STAT_DMA_ENG_4_QID_FIFO_OUT_VLD_MASK BIT(18) -#define C2H_STAT_DMA_ENG_4_PLD_FIFO_OUT_VLD_MASK BIT(17) -#define C2H_STAT_DMA_ENG_4_PLD_ST_FIFO_OUT_VLD_MASK BIT(16) -#define C2H_STAT_DMA_ENG_4_PLD_ST_FIFO_OUT_DATA_EOP_MASK BIT(15) -#define C2H_STAT_DMA_ENG_4_PLD_ST_FIFO_OUT_DATA_AVL_IDX_ENABLE_MASK BIT(14) -#define C2H_STAT_DMA_ENG_4_PLD_ST_FIFO_OUT_DATA_DROP_MASK BIT(13) -#define C2H_STAT_DMA_ENG_4_PLD_ST_FIFO_OUT_DATA_ERR_MASK BIT(12) -#define C2H_STAT_DMA_ENG_4_DESC_CNT_FIFO_IN_RDY_MASK BIT(11) -#define C2H_STAT_DMA_ENG_4_DESC_RSP_FIFO_IN_RDY_MASK BIT(10) -#define C2H_STAT_DMA_ENG_4_PLD_PKT_ID_LARGER_0_MASK BIT(9) -#define C2H_STAT_DMA_ENG_4_WRQ_VLD_MASK BIT(8) -#define C2H_STAT_DMA_ENG_4_WRQ_RDY_MASK BIT(7) -#define C2H_STAT_DMA_ENG_4_WRQ_FIFO_OUT_RDY_MASK BIT(6) -#define C2H_STAT_DMA_ENG_4_WRQ_PACKET_OUT_DATA_DROP_MASK BIT(5) -#define C2H_STAT_DMA_ENG_4_WRQ_PACKET_OUT_DATA_ERR_MASK BIT(4) -#define C2H_STAT_DMA_ENG_4_WRQ_PACKET_OUT_DATA_MARKER_MASK BIT(3) -#define C2H_STAT_DMA_ENG_4_WRQ_PACKET_PRE_EOR_MASK BIT(2) -#define C2H_STAT_DMA_ENG_4_WCP_FIFO_IN_RDY_MASK BIT(1) -#define C2H_STAT_DMA_ENG_4_PLD_ST_FIFO_IN_RDY_MASK BIT(0) -#define EQDMA_C2H_STAT_DBG_DMA_ENG_5_ADDR 0xB8C -#define C2H_STAT_DMA_ENG_5_RSVD_1_MASK GENMASK(31, 30) -#define C2H_STAT_DMA_ENG_5_WRB_SM_VIRT_CH_MASK BIT(29) -#define C2H_STAT_DMA_ENG_5_WRB_FIFO_IN_REQ_MASK GENMASK(28, 24) -#define C2H_STAT_DMA_ENG_5_ARB_FIFO_OUT_CNT_MASK GENMASK(23, 22) -#define C2H_STAT_DMA_ENG_5_ARB_FIFO_OUT_DATA_LEN_MASK GENMASK(21, 6) -#define C2H_STAT_DMA_ENG_5_ARB_FIFO_OUT_DATA_VIRT_CH_MASK BIT(5) -#define C2H_STAT_DMA_ENG_5_ARB_FIFO_OUT_DATA_VAR_DESC_MASK BIT(4) -#define C2H_STAT_DMA_ENG_5_ARB_FIFO_OUT_DATA_DROP_REQ_MASK BIT(3) -#define C2H_STAT_DMA_ENG_5_ARB_FIFO_OUT_DATA_NUM_BUF_OV_MASK BIT(2) -#define C2H_STAT_DMA_ENG_5_ARB_FIFO_OUT_DATA_MARKER_MASK BIT(1) -#define C2H_STAT_DMA_ENG_5_ARB_FIFO_OUT_DATA_HAS_CMPT_MASK BIT(0) -#define EQDMA_C2H_DBG_PFCH_QID_ADDR 0xB90 -#define C2H_PFCH_QID_RSVD_1_MASK GENMASK(31, 16) -#define C2H_PFCH_QID_ERR_CTXT_MASK BIT(15) -#define C2H_PFCH_QID_TARGET_MASK GENMASK(14, 12) -#define C2H_PFCH_QID_QID_OR_TAG_MASK GENMASK(11, 0) -#define EQDMA_C2H_DBG_PFCH_ADDR 0xB94 -#define C2H_PFCH_DATA_MASK GENMASK(31, 0) -#define EQDMA_C2H_INT_DBG_ADDR 0xB98 -#define C2H_INT_RSVD_1_MASK GENMASK(31, 8) -#define C2H_INT_INT_COAL_SM_MASK GENMASK(7, 4) -#define C2H_INT_INT_SM_MASK GENMASK(3, 0) -#define EQDMA_C2H_STAT_IMM_ACCEPTED_ADDR 0xB9C -#define C2H_STAT_IMM_ACCEPTED_RSVD_1_MASK GENMASK(31, 18) -#define C2H_STAT_IMM_ACCEPTED_CNT_MASK GENMASK(17, 0) -#define EQDMA_C2H_STAT_MARKER_ACCEPTED_ADDR 0xBA0 -#define C2H_STAT_MARKER_ACCEPTED_RSVD_1_MASK GENMASK(31, 18) -#define C2H_STAT_MARKER_ACCEPTED_CNT_MASK GENMASK(17, 0) -#define EQDMA_C2H_STAT_DISABLE_CMP_ACCEPTED_ADDR 0xBA4 -#define C2H_STAT_DISABLE_CMP_ACCEPTED_RSVD_1_MASK GENMASK(31, 18) -#define C2H_STAT_DISABLE_CMP_ACCEPTED_CNT_MASK GENMASK(17, 0) -#define EQDMA_C2H_PLD_FIFO_CRDT_CNT_ADDR 0xBA8 -#define C2H_PLD_FIFO_CRDT_CNT_RSVD_1_MASK GENMASK(31, 18) -#define C2H_PLD_FIFO_CRDT_CNT_CNT_MASK GENMASK(17, 0) -#define EQDMA_C2H_INTR_DYN_REQ_ADDR 0xBAC -#define C2H_INTR_DYN_REQ_RSVD_1_MASK GENMASK(31, 18) -#define C2H_INTR_DYN_REQ_CNT_MASK GENMASK(17, 0) -#define EQDMA_C2H_INTR_DYN_MISC_ADDR 0xBB0 -#define C2H_INTR_DYN_MISC_RSVD_1_MASK GENMASK(31, 18) -#define C2H_INTR_DYN_MISC_CNT_MASK GENMASK(17, 0) -#define EQDMA_C2H_DROP_LEN_MISMATCH_ADDR 0xBB4 -#define C2H_DROP_LEN_MISMATCH_RSVD_1_MASK GENMASK(31, 18) -#define C2H_DROP_LEN_MISMATCH_CNT_MASK GENMASK(17, 0) -#define EQDMA_C2H_DROP_DESC_RSP_LEN_ADDR 0xBB8 -#define C2H_DROP_DESC_RSP_LEN_RSVD_1_MASK GENMASK(31, 18) -#define C2H_DROP_DESC_RSP_LEN_CNT_MASK GENMASK(17, 0) -#define EQDMA_C2H_DROP_QID_FIFO_LEN_ADDR 0xBBC -#define C2H_DROP_QID_FIFO_LEN_RSVD_1_MASK GENMASK(31, 18) -#define C2H_DROP_QID_FIFO_LEN_CNT_MASK GENMASK(17, 0) -#define EQDMA_C2H_DROP_PLD_CNT_ADDR 0xBC0 -#define C2H_DROP_PLD_CNT_RSVD_1_MASK GENMASK(31, 18) -#define C2H_DROP_PLD_CNT_CNT_MASK GENMASK(17, 0) -#define EQDMA_C2H_CMPT_FORMAT_0_ADDR 0xBC4 -#define C2H_CMPT_FORMAT_0_DESC_ERR_LOC_MASK GENMASK(31, 16) -#define C2H_CMPT_FORMAT_0_COLOR_LOC_MASK GENMASK(15, 0) -#define EQDMA_C2H_CMPT_FORMAT_1_ADDR 0xBC8 -#define C2H_CMPT_FORMAT_1_DESC_ERR_LOC_MASK GENMASK(31, 16) -#define C2H_CMPT_FORMAT_1_COLOR_LOC_MASK GENMASK(15, 0) -#define EQDMA_C2H_CMPT_FORMAT_2_ADDR 0xBCC -#define C2H_CMPT_FORMAT_2_DESC_ERR_LOC_MASK GENMASK(31, 16) -#define C2H_CMPT_FORMAT_2_COLOR_LOC_MASK GENMASK(15, 0) -#define EQDMA_C2H_CMPT_FORMAT_3_ADDR 0xBD0 -#define C2H_CMPT_FORMAT_3_DESC_ERR_LOC_MASK GENMASK(31, 16) -#define C2H_CMPT_FORMAT_3_COLOR_LOC_MASK GENMASK(15, 0) -#define EQDMA_C2H_CMPT_FORMAT_4_ADDR 0xBD4 -#define C2H_CMPT_FORMAT_4_DESC_ERR_LOC_MASK GENMASK(31, 16) -#define C2H_CMPT_FORMAT_4_COLOR_LOC_MASK GENMASK(15, 0) -#define EQDMA_C2H_CMPT_FORMAT_5_ADDR 0xBD8 -#define C2H_CMPT_FORMAT_5_DESC_ERR_LOC_MASK GENMASK(31, 16) -#define C2H_CMPT_FORMAT_5_COLOR_LOC_MASK GENMASK(15, 0) -#define EQDMA_C2H_CMPT_FORMAT_6_ADDR 0xBDC -#define C2H_CMPT_FORMAT_6_DESC_ERR_LOC_MASK GENMASK(31, 16) -#define C2H_CMPT_FORMAT_6_COLOR_LOC_MASK GENMASK(15, 0) -#define EQDMA_C2H_PFCH_CACHE_DEPTH_ADDR 0xBE0 -#define C2H_PFCH_CACHE_DEPTH_MAX_STBUF_MASK GENMASK(23, 16) -#define C2H_PFCH_CACHE_DEPTH_MASK GENMASK(7, 0) -#define EQDMA_C2H_WRB_COAL_BUF_DEPTH_ADDR 0xBE4 -#define C2H_WRB_COAL_BUF_DEPTH_RSVD_1_MASK GENMASK(31, 8) -#define C2H_WRB_COAL_BUF_DEPTH_BUFFER_MASK GENMASK(7, 0) -#define EQDMA_C2H_PFCH_CRDT_ADDR 0xBE8 -#define C2H_PFCH_CRDT_RSVD_1_MASK GENMASK(31, 1) -#define C2H_PFCH_CRDT_RSVD_2_MASK BIT(0) -#define EQDMA_C2H_STAT_HAS_CMPT_ACCEPTED_ADDR 0xBEC -#define C2H_STAT_HAS_CMPT_ACCEPTED_RSVD_1_MASK GENMASK(31, 18) -#define C2H_STAT_HAS_CMPT_ACCEPTED_CNT_MASK GENMASK(17, 0) -#define EQDMA_C2H_STAT_HAS_PLD_ACCEPTED_ADDR 0xBF0 -#define C2H_STAT_HAS_PLD_ACCEPTED_RSVD_1_MASK GENMASK(31, 18) -#define C2H_STAT_HAS_PLD_ACCEPTED_CNT_MASK GENMASK(17, 0) -#define EQDMA_C2H_PLD_PKT_ID_ADDR 0xBF4 -#define C2H_PLD_PKT_ID_CMPT_WAIT_MASK GENMASK(31, 16) -#define C2H_PLD_PKT_ID_DATA_MASK GENMASK(15, 0) -#define EQDMA_C2H_PLD_PKT_ID_1_ADDR 0xBF8 -#define C2H_PLD_PKT_ID_1_CMPT_WAIT_MASK GENMASK(31, 16) -#define C2H_PLD_PKT_ID_1_DATA_MASK GENMASK(15, 0) -#define EQDMA_C2H_DROP_PLD_CNT_1_ADDR 0xBFC -#define C2H_DROP_PLD_CNT_1_RSVD_1_MASK GENMASK(31, 18) -#define C2H_DROP_PLD_CNT_1_CNT_MASK GENMASK(17, 0) -#define EQDMA_H2C_ERR_STAT_ADDR 0xE00 -#define H2C_ERR_STAT_RSVD_1_MASK GENMASK(31, 6) -#define H2C_ERR_STAT_PAR_ERR_MASK BIT(5) -#define H2C_ERR_STAT_SBE_MASK BIT(4) -#define H2C_ERR_STAT_DBE_MASK BIT(3) -#define H2C_ERR_STAT_NO_DMA_DS_MASK BIT(2) -#define H2C_ERR_STAT_SDI_MRKR_REQ_MOP_ERR_MASK BIT(1) -#define H2C_ERR_STAT_ZERO_LEN_DS_MASK BIT(0) -#define EQDMA_H2C_ERR_MASK_ADDR 0xE04 -#define H2C_ERR_EN_MASK GENMASK(31, 0) -#define EQDMA_H2C_FIRST_ERR_QID_ADDR 0xE08 -#define H2C_FIRST_ERR_QID_RSVD_1_MASK GENMASK(31, 20) -#define H2C_FIRST_ERR_QID_ERR_TYPE_MASK GENMASK(19, 16) -#define H2C_FIRST_ERR_QID_RSVD_2_MASK GENMASK(15, 13) -#define H2C_FIRST_ERR_QID_QID_MASK GENMASK(12, 0) -#define EQDMA_H2C_DBG_REG0_ADDR 0xE0C -#define H2C_REG0_NUM_DSC_RCVD_MASK GENMASK(31, 16) -#define H2C_REG0_NUM_WRB_SENT_MASK GENMASK(15, 0) -#define EQDMA_H2C_DBG_REG1_ADDR 0xE10 -#define H2C_REG1_NUM_REQ_SENT_MASK GENMASK(31, 16) -#define H2C_REG1_NUM_CMP_SENT_MASK GENMASK(15, 0) -#define EQDMA_H2C_DBG_REG2_ADDR 0xE14 -#define H2C_REG2_RSVD_1_MASK GENMASK(31, 16) -#define H2C_REG2_NUM_ERR_DSC_RCVD_MASK GENMASK(15, 0) -#define EQDMA_H2C_DBG_REG3_ADDR 0xE18 -#define H2C_REG3_RSVD_1_MASK BIT(31) -#define H2C_REG3_DSCO_FIFO_EMPTY_MASK BIT(30) -#define H2C_REG3_DSCO_FIFO_FULL_MASK BIT(29) -#define H2C_REG3_CUR_RC_STATE_MASK GENMASK(28, 26) -#define H2C_REG3_RDREQ_LINES_MASK GENMASK(25, 16) -#define H2C_REG3_RDATA_LINES_AVAIL_MASK GENMASK(15, 6) -#define H2C_REG3_PEND_FIFO_EMPTY_MASK BIT(5) -#define H2C_REG3_PEND_FIFO_FULL_MASK BIT(4) -#define H2C_REG3_CUR_RQ_STATE_MASK GENMASK(3, 2) -#define H2C_REG3_DSCI_FIFO_FULL_MASK BIT(1) -#define H2C_REG3_DSCI_FIFO_EMPTY_MASK BIT(0) -#define EQDMA_H2C_DBG_REG4_ADDR 0xE1C -#define H2C_REG4_RDREQ_ADDR_MASK GENMASK(31, 0) -#define EQDMA_H2C_FATAL_ERR_EN_ADDR 0xE20 -#define H2C_FATAL_ERR_EN_RSVD_1_MASK GENMASK(31, 1) -#define H2C_FATAL_ERR_EN_H2C_MASK BIT(0) -#define EQDMA_H2C_REQ_THROT_PCIE_ADDR 0xE24 -#define H2C_REQ_THROT_PCIE_EN_REQ_MASK BIT(31) -#define H2C_REQ_THROT_PCIE_MASK GENMASK(30, 19) -#define H2C_REQ_THROT_PCIE_EN_DATA_MASK BIT(18) -#define H2C_REQ_THROT_PCIE_DATA_THRESH_MASK GENMASK(17, 0) -#define EQDMA_H2C_ALN_DBG_REG0_ADDR 0xE28 -#define H2C_ALN_REG0_NUM_PKT_SENT_MASK GENMASK(15, 0) -#define EQDMA_H2C_REQ_THROT_AXIMM_ADDR 0xE2C -#define H2C_REQ_THROT_AXIMM_EN_REQ_MASK BIT(31) -#define H2C_REQ_THROT_AXIMM_MASK GENMASK(30, 19) -#define H2C_REQ_THROT_AXIMM_EN_DATA_MASK BIT(18) -#define H2C_REQ_THROT_AXIMM_DATA_THRESH_MASK GENMASK(17, 0) -#define EQDMA_C2H_MM_CTL_ADDR 0x1004 -#define C2H_MM_CTL_RESERVED1_MASK GENMASK(31, 9) -#define C2H_MM_CTL_ERRC_EN_MASK BIT(8) -#define C2H_MM_CTL_RESERVED0_MASK GENMASK(7, 1) -#define C2H_MM_CTL_RUN_MASK BIT(0) -#define EQDMA_C2H_MM_STATUS_ADDR 0x1040 -#define C2H_MM_STATUS_RSVD_1_MASK GENMASK(31, 1) -#define C2H_MM_STATUS_RUN_MASK BIT(0) -#define EQDMA_C2H_MM_CMPL_DESC_CNT_ADDR 0x1048 -#define C2H_MM_CMPL_DESC_CNT_C2H_CO_MASK GENMASK(31, 0) -#define EQDMA_C2H_MM_ERR_CODE_ENABLE_MASK_ADDR 0x1054 -#define C2H_MM_ERR_CODE_ENABLE_RESERVED1_MASK BIT(31) -#define C2H_MM_ERR_CODE_ENABLE_WR_UC_RAM_MASK BIT(30) -#define C2H_MM_ERR_CODE_ENABLE_WR_UR_MASK BIT(29) -#define C2H_MM_ERR_CODE_ENABLE_WR_FLR_MASK BIT(28) -#define C2H_MM_ERR_CODE_ENABLE_RESERVED0_MASK GENMASK(27, 2) -#define C2H_MM_ERR_CODE_ENABLE_RD_SLV_ERR_MASK BIT(1) -#define C2H_MM_ERR_CODE_ENABLE_WR_SLV_ERR_MASK BIT(0) -#define EQDMA_C2H_MM_ERR_CODE_ADDR 0x1058 -#define C2H_MM_ERR_CODE_RESERVED1_MASK GENMASK(31, 28) -#define C2H_MM_ERR_CODE_CIDX_MASK GENMASK(27, 12) -#define C2H_MM_ERR_CODE_RESERVED0_MASK GENMASK(11, 10) -#define C2H_MM_ERR_CODE_SUB_TYPE_MASK GENMASK(9, 5) -#define C2H_MM_ERR_CODE_MASK GENMASK(4, 0) -#define EQDMA_C2H_MM_ERR_INFO_ADDR 0x105C -#define C2H_MM_ERR_INFO_VALID_MASK BIT(31) -#define C2H_MM_ERR_INFO_SEL_MASK BIT(30) -#define C2H_MM_ERR_INFO_RSVD_1_MASK GENMASK(29, 24) -#define C2H_MM_ERR_INFO_QID_MASK GENMASK(23, 0) -#define EQDMA_C2H_MM_PERF_MON_CTL_ADDR 0x10C0 -#define C2H_MM_PERF_MON_CTL_RSVD_1_MASK GENMASK(31, 4) -#define C2H_MM_PERF_MON_CTL_IMM_START_MASK BIT(3) -#define C2H_MM_PERF_MON_CTL_RUN_START_MASK BIT(2) -#define C2H_MM_PERF_MON_CTL_IMM_CLEAR_MASK BIT(1) -#define C2H_MM_PERF_MON_CTL_RUN_CLEAR_MASK BIT(0) -#define EQDMA_C2H_MM_PERF_MON_CYCLE_CNT0_ADDR 0x10C4 -#define C2H_MM_PERF_MON_CYCLE_CNT0_CYC_CNT_MASK GENMASK(31, 0) -#define EQDMA_C2H_MM_PERF_MON_CYCLE_CNT1_ADDR 0x10C8 -#define C2H_MM_PERF_MON_CYCLE_CNT1_RSVD_1_MASK GENMASK(31, 10) -#define C2H_MM_PERF_MON_CYCLE_CNT1_CYC_CNT_MASK GENMASK(9, 0) -#define EQDMA_C2H_MM_PERF_MON_DATA_CNT0_ADDR 0x10CC -#define C2H_MM_PERF_MON_DATA_CNT0_DCNT_MASK GENMASK(31, 0) -#define EQDMA_C2H_MM_PERF_MON_DATA_CNT1_ADDR 0x10D0 -#define C2H_MM_PERF_MON_DATA_CNT1_RSVD_1_MASK GENMASK(31, 10) -#define C2H_MM_PERF_MON_DATA_CNT1_DCNT_MASK GENMASK(9, 0) -#define EQDMA_C2H_MM_DBG_ADDR 0x10E8 -#define C2H_MM_RSVD_1_MASK GENMASK(31, 24) -#define C2H_MM_RRQ_ENTRIES_MASK GENMASK(23, 17) -#define C2H_MM_DAT_FIFO_SPC_MASK GENMASK(16, 7) -#define C2H_MM_RD_STALL_MASK BIT(6) -#define C2H_MM_RRQ_FIFO_FI_MASK BIT(5) -#define C2H_MM_WR_STALL_MASK BIT(4) -#define C2H_MM_WRQ_FIFO_FI_MASK BIT(3) -#define C2H_MM_WBK_STALL_MASK BIT(2) -#define C2H_MM_DSC_FIFO_EP_MASK BIT(1) -#define C2H_MM_DSC_FIFO_FL_MASK BIT(0) -#define EQDMA_H2C_MM_CTL_ADDR 0x1204 -#define H2C_MM_CTL_RESERVED1_MASK GENMASK(31, 9) -#define H2C_MM_CTL_ERRC_EN_MASK BIT(8) -#define H2C_MM_CTL_RESERVED0_MASK GENMASK(7, 1) -#define H2C_MM_CTL_RUN_MASK BIT(0) -#define EQDMA_H2C_MM_STATUS_ADDR 0x1240 -#define H2C_MM_STATUS_RSVD_1_MASK GENMASK(31, 1) -#define H2C_MM_STATUS_RUN_MASK BIT(0) -#define EQDMA_H2C_MM_CMPL_DESC_CNT_ADDR 0x1248 -#define H2C_MM_CMPL_DESC_CNT_H2C_CO_MASK GENMASK(31, 0) -#define EQDMA_H2C_MM_ERR_CODE_ENABLE_MASK_ADDR 0x1254 -#define H2C_MM_ERR_CODE_ENABLE_RESERVED5_MASK GENMASK(31, 30) -#define H2C_MM_ERR_CODE_ENABLE_WR_SLV_ERR_MASK BIT(29) -#define H2C_MM_ERR_CODE_ENABLE_WR_DEC_ERR_MASK BIT(28) -#define H2C_MM_ERR_CODE_ENABLE_RESERVED4_MASK GENMASK(27, 23) -#define H2C_MM_ERR_CODE_ENABLE_RD_RQ_DIS_ERR_MASK BIT(22) -#define H2C_MM_ERR_CODE_ENABLE_RESERVED3_MASK GENMASK(21, 17) -#define H2C_MM_ERR_CODE_ENABLE_RD_DAT_POISON_ERR_MASK BIT(16) -#define H2C_MM_ERR_CODE_ENABLE_RESERVED2_MASK GENMASK(15, 9) -#define H2C_MM_ERR_CODE_ENABLE_RD_FLR_ERR_MASK BIT(8) -#define H2C_MM_ERR_CODE_ENABLE_RESERVED1_MASK GENMASK(7, 6) -#define H2C_MM_ERR_CODE_ENABLE_RD_HDR_ADR_ERR_MASK BIT(5) -#define H2C_MM_ERR_CODE_ENABLE_RD_HDR_PARA_MASK BIT(4) -#define H2C_MM_ERR_CODE_ENABLE_RD_HDR_BYTE_ERR_MASK BIT(3) -#define H2C_MM_ERR_CODE_ENABLE_RD_UR_CA_MASK BIT(2) -#define H2C_MM_ERR_CODE_ENABLE_RD_HRD_POISON_ERR_MASK BIT(1) -#define H2C_MM_ERR_CODE_ENABLE_RESERVED0_MASK BIT(0) -#define EQDMA_H2C_MM_ERR_CODE_ADDR 0x1258 -#define H2C_MM_ERR_CODE_RSVD_1_MASK GENMASK(31, 28) -#define H2C_MM_ERR_CODE_CIDX_MASK GENMASK(27, 12) -#define H2C_MM_ERR_CODE_RESERVED0_MASK GENMASK(11, 10) -#define H2C_MM_ERR_CODE_SUB_TYPE_MASK GENMASK(9, 5) -#define H2C_MM_ERR_CODE_MASK GENMASK(4, 0) -#define EQDMA_H2C_MM_ERR_INFO_ADDR 0x125C -#define H2C_MM_ERR_INFO_VALID_MASK BIT(31) -#define H2C_MM_ERR_INFO_SEL_MASK BIT(30) -#define H2C_MM_ERR_INFO_RSVD_1_MASK GENMASK(29, 24) -#define H2C_MM_ERR_INFO_QID_MASK GENMASK(23, 0) -#define EQDMA_H2C_MM_PERF_MON_CTL_ADDR 0x12C0 -#define H2C_MM_PERF_MON_CTL_RSVD_1_MASK GENMASK(31, 4) -#define H2C_MM_PERF_MON_CTL_IMM_START_MASK BIT(3) -#define H2C_MM_PERF_MON_CTL_RUN_START_MASK BIT(2) -#define H2C_MM_PERF_MON_CTL_IMM_CLEAR_MASK BIT(1) -#define H2C_MM_PERF_MON_CTL_RUN_CLEAR_MASK BIT(0) -#define EQDMA_H2C_MM_PERF_MON_CYCLE_CNT0_ADDR 0x12C4 -#define H2C_MM_PERF_MON_CYCLE_CNT0_CYC_CNT_MASK GENMASK(31, 0) -#define EQDMA_H2C_MM_PERF_MON_CYCLE_CNT1_ADDR 0x12C8 -#define H2C_MM_PERF_MON_CYCLE_CNT1_RSVD_1_MASK GENMASK(31, 10) -#define H2C_MM_PERF_MON_CYCLE_CNT1_CYC_CNT_MASK GENMASK(9, 0) -#define EQDMA_H2C_MM_PERF_MON_DATA_CNT0_ADDR 0x12CC -#define H2C_MM_PERF_MON_DATA_CNT0_DCNT_MASK GENMASK(31, 0) -#define EQDMA_H2C_MM_PERF_MON_DATA_CNT1_ADDR 0x12D0 -#define H2C_MM_PERF_MON_DATA_CNT1_RSVD_1_MASK GENMASK(31, 10) -#define H2C_MM_PERF_MON_DATA_CNT1_DCNT_MASK GENMASK(9, 0) -#define EQDMA_H2C_MM_DBG_ADDR 0x12E8 -#define H2C_MM_RSVD_1_MASK GENMASK(31, 24) -#define H2C_MM_RRQ_ENTRIES_MASK GENMASK(23, 17) -#define H2C_MM_DAT_FIFO_SPC_MASK GENMASK(16, 7) -#define H2C_MM_RD_STALL_MASK BIT(6) -#define H2C_MM_RRQ_FIFO_FI_MASK BIT(5) -#define H2C_MM_WR_STALL_MASK BIT(4) -#define H2C_MM_WRQ_FIFO_FI_MASK BIT(3) -#define H2C_MM_WBK_STALL_MASK BIT(2) -#define H2C_MM_DSC_FIFO_EP_MASK BIT(1) -#define H2C_MM_DSC_FIFO_FL_MASK BIT(0) -#define EQDMA_C2H_CRDT_COAL_CFG_1_ADDR 0x1400 -#define C2H_CRDT_COAL_CFG_1_RSVD_1_MASK GENMASK(31, 18) -#define C2H_CRDT_COAL_CFG_1_PLD_FIFO_TH_MASK GENMASK(17, 10) -#define C2H_CRDT_COAL_CFG_1_TIMER_TH_MASK GENMASK(9, 0) -#define EQDMA_C2H_CRDT_COAL_CFG_2_ADDR 0x1404 -#define C2H_CRDT_COAL_CFG_2_RSVD_1_MASK GENMASK(31, 24) -#define C2H_CRDT_COAL_CFG_2_FIFO_TH_MASK GENMASK(23, 16) -#define C2H_CRDT_COAL_CFG_2_RESERVED1_MASK GENMASK(15, 11) -#define C2H_CRDT_COAL_CFG_2_NT_TH_MASK GENMASK(10, 0) -#define EQDMA_C2H_PFCH_BYP_QID_ADDR 0x1408 -#define C2H_PFCH_BYP_QID_RSVD_1_MASK GENMASK(31, 12) -#define C2H_PFCH_BYP_QID_MASK GENMASK(11, 0) -#define EQDMA_C2H_PFCH_BYP_TAG_ADDR 0x140C -#define C2H_PFCH_BYP_TAG_RSVD_1_MASK GENMASK(31, 20) -#define C2H_PFCH_BYP_TAG_BYP_QID_MASK GENMASK(19, 8) -#define C2H_PFCH_BYP_TAG_RSVD_2_MASK BIT(7) -#define C2H_PFCH_BYP_TAG_MASK GENMASK(6, 0) -#define EQDMA_C2H_WATER_MARK_ADDR 0x1500 -#define C2H_WATER_MARK_HIGH_WM_MASK GENMASK(31, 16) -#define C2H_WATER_MARK_LOW_WM_MASK GENMASK(15, 0) -#define SW_IND_CTXT_DATA_W7_VIRTIO_DSC_BASE_H_MASK GENMASK(10, 0) -#define SW_IND_CTXT_DATA_W6_VIRTIO_DSC_BASE_M_MASK GENMASK(31, 0) -#define SW_IND_CTXT_DATA_W5_VIRTIO_DSC_BASE_L_MASK GENMASK(31, 11) -#define SW_IND_CTXT_DATA_W5_PASID_EN_MASK BIT(10) -#define SW_IND_CTXT_DATA_W5_PASID_H_MASK GENMASK(9, 0) -#define SW_IND_CTXT_DATA_W4_PASID_L_MASK GENMASK(31, 20) -#define SW_IND_CTXT_DATA_W4_HOST_ID_MASK GENMASK(19, 16) -#define SW_IND_CTXT_DATA_W4_IRQ_BYP_MASK BIT(15) -#define SW_IND_CTXT_DATA_W4_PACK_BYP_OUT_MASK BIT(14) -#define SW_IND_CTXT_DATA_W4_VIRTIO_EN_MASK BIT(13) -#define SW_IND_CTXT_DATA_W4_DIS_INTR_ON_VF_MASK BIT(12) -#define SW_IND_CTXT_DATA_W4_INT_AGGR_MASK BIT(11) -#define SW_IND_CTXT_DATA_W4_VEC_MASK GENMASK(10, 0) -#define SW_IND_CTXT_DATA_W3_DSC_BASE_H_MASK GENMASK(31, 0) -#define SW_IND_CTXT_DATA_W2_DSC_BASE_L_MASK GENMASK(31, 0) -#define SW_IND_CTXT_DATA_W1_IS_MM_MASK BIT(31) -#define SW_IND_CTXT_DATA_W1_MRKR_DIS_MASK BIT(30) -#define SW_IND_CTXT_DATA_W1_IRQ_REQ_MASK BIT(29) -#define SW_IND_CTXT_DATA_W1_ERR_WB_SENT_MASK BIT(28) -#define SW_IND_CTXT_DATA_W1_ERR_MASK GENMASK(27, 26) -#define SW_IND_CTXT_DATA_W1_IRQ_NO_LAST_MASK BIT(25) -#define SW_IND_CTXT_DATA_W1_PORT_ID_MASK GENMASK(24, 22) -#define SW_IND_CTXT_DATA_W1_IRQ_EN_MASK BIT(21) -#define SW_IND_CTXT_DATA_W1_WBK_EN_MASK BIT(20) -#define SW_IND_CTXT_DATA_W1_MM_CHN_MASK BIT(19) -#define SW_IND_CTXT_DATA_W1_BYPASS_MASK BIT(18) -#define SW_IND_CTXT_DATA_W1_DSC_SZ_MASK GENMASK(17, 16) -#define SW_IND_CTXT_DATA_W1_RNG_SZ_MASK GENMASK(15, 12) -#define SW_IND_CTXT_DATA_W1_RSVD_1_MASK GENMASK(11, 9) -#define SW_IND_CTXT_DATA_W1_FETCH_MAX_MASK GENMASK(8, 5) -#define SW_IND_CTXT_DATA_W1_AT_MASK BIT(4) -#define SW_IND_CTXT_DATA_W1_WBI_INTVL_EN_MASK BIT(3) -#define SW_IND_CTXT_DATA_W1_WBI_CHK_MASK BIT(2) -#define SW_IND_CTXT_DATA_W1_FCRD_EN_MASK BIT(1) -#define SW_IND_CTXT_DATA_W1_QEN_MASK BIT(0) -#define SW_IND_CTXT_DATA_W0_RSV_MASK GENMASK(31, 29) -#define SW_IND_CTXT_DATA_W0_FNC_MASK GENMASK(28, 17) -#define SW_IND_CTXT_DATA_W0_IRQ_ARM_MASK BIT(16) -#define SW_IND_CTXT_DATA_W0_PIDX_MASK GENMASK(15, 0) -#define HW_IND_CTXT_DATA_W1_RSVD_1_MASK BIT(15) -#define HW_IND_CTXT_DATA_W1_FETCH_PND_MASK GENMASK(14, 11) -#define HW_IND_CTXT_DATA_W1_EVT_PND_MASK BIT(10) -#define HW_IND_CTXT_DATA_W1_IDL_STP_B_MASK BIT(9) -#define HW_IND_CTXT_DATA_W1_DSC_PND_MASK BIT(8) -#define HW_IND_CTXT_DATA_W1_RSVD_2_MASK GENMASK(7, 0) -#define HW_IND_CTXT_DATA_W0_CRD_USE_MASK GENMASK(31, 16) -#define HW_IND_CTXT_DATA_W0_CIDX_MASK GENMASK(15, 0) -#define CRED_CTXT_DATA_W0_RSVD_1_MASK GENMASK(31, 16) -#define CRED_CTXT_DATA_W0_CREDT_MASK GENMASK(15, 0) -#define PREFETCH_CTXT_DATA_W1_VALID_MASK BIT(13) -#define PREFETCH_CTXT_DATA_W1_SW_CRDT_H_MASK GENMASK(12, 0) -#define PREFETCH_CTXT_DATA_W0_SW_CRDT_L_MASK GENMASK(31, 29) -#define PREFETCH_CTXT_DATA_W0_PFCH_MASK BIT(28) -#define PREFETCH_CTXT_DATA_W0_PFCH_EN_MASK BIT(27) -#define PREFETCH_CTXT_DATA_W0_ERR_MASK BIT(26) -#define PREFETCH_CTXT_DATA_W0_RSVD_MASK GENMASK(25, 22) -#define PREFETCH_CTXT_DATA_W0_PFCH_NEED_MASK GENMASK(21, 16) -#define PREFETCH_CTXT_DATA_W0_NUM_PFCH_MASK GENMASK(15, 10) -#define PREFETCH_CTXT_DATA_W0_VIRTIO_MASK BIT(9) -#define PREFETCH_CTXT_DATA_W0_VAR_DESC_MASK BIT(8) -#define PREFETCH_CTXT_DATA_W0_PORT_ID_MASK GENMASK(7, 5) -#define PREFETCH_CTXT_DATA_W0_BUF_SZ_IDX_MASK GENMASK(4, 1) -#define PREFETCH_CTXT_DATA_W0_BYPASS_MASK BIT(0) -#define CMPL_CTXT_DATA_W6_RSVD_1_H_MASK GENMASK(7, 0) -#define CMPL_CTXT_DATA_W5_RSVD_1_L_MASK GENMASK(31, 23) -#define CMPL_CTXT_DATA_W5_PORT_ID_MASK GENMASK(22, 20) -#define CMPL_CTXT_DATA_W5_SH_CMPT_MASK BIT(19) -#define CMPL_CTXT_DATA_W5_VIO_EOP_MASK BIT(18) -#define CMPL_CTXT_DATA_W5_BADDR4_LOW_MASK GENMASK(17, 14) -#define CMPL_CTXT_DATA_W5_PASID_EN_MASK BIT(13) -#define CMPL_CTXT_DATA_W5_PASID_H_MASK GENMASK(12, 0) -#define CMPL_CTXT_DATA_W4_PASID_L_MASK GENMASK(31, 23) -#define CMPL_CTXT_DATA_W4_HOST_ID_MASK GENMASK(22, 19) -#define CMPL_CTXT_DATA_W4_DIR_C2H_MASK BIT(18) -#define CMPL_CTXT_DATA_W4_VIO_MASK BIT(17) -#define CMPL_CTXT_DATA_W4_DIS_INTR_ON_VF_MASK BIT(16) -#define CMPL_CTXT_DATA_W4_INT_AGGR_MASK BIT(15) -#define CMPL_CTXT_DATA_W4_VEC_MASK GENMASK(14, 4) -#define CMPL_CTXT_DATA_W4_AT_MASK BIT(3) -#define CMPL_CTXT_DATA_W4_OVF_CHK_DIS_MASK BIT(2) -#define CMPL_CTXT_DATA_W4_FULL_UPD_MASK BIT(1) -#define CMPL_CTXT_DATA_W4_TIMER_RUNNING_MASK BIT(0) -#define CMPL_CTXT_DATA_W3_USER_TRIG_PEND_MASK BIT(31) -#define CMPL_CTXT_DATA_W3_ERR_MASK GENMASK(30, 29) -#define CMPL_CTXT_DATA_W3_VALID_MASK BIT(28) -#define CMPL_CTXT_DATA_W3_CIDX_MASK GENMASK(27, 12) -#define CMPL_CTXT_DATA_W3_PIDX_H_MASK GENMASK(11, 0) -#define CMPL_CTXT_DATA_W2_PIDX_L_MASK GENMASK(31, 28) -#define CMPL_CTXT_DATA_W2_DESC_SIZE_MASK GENMASK(27, 26) -#define CMPL_CTXT_DATA_W2_BADDR4_HIGH_H_MASK GENMASK(25, 0) -#define CMPL_CTXT_DATA_W1_BADDR4_HIGH_L_MASK GENMASK(31, 0) -#define CMPL_CTXT_DATA_W0_QSIZE_IX_MASK GENMASK(31, 28) -#define CMPL_CTXT_DATA_W0_COLOR_MASK BIT(27) -#define CMPL_CTXT_DATA_W0_INT_ST_MASK GENMASK(26, 25) -#define CMPL_CTXT_DATA_W0_TIMER_IX_MASK GENMASK(24, 21) -#define CMPL_CTXT_DATA_W0_CNTER_IX_MASK GENMASK(20, 17) -#define CMPL_CTXT_DATA_W0_FNC_ID_MASK GENMASK(16, 5) -#define CMPL_CTXT_DATA_W0_TRIG_MODE_MASK GENMASK(4, 2) -#define CMPL_CTXT_DATA_W0_EN_INT_MASK BIT(1) -#define CMPL_CTXT_DATA_W0_EN_STAT_DESC_MASK BIT(0) -#define INTR_CTXT_DATA_W3_FUNC_MASK GENMASK(29, 18) -#define INTR_CTXT_DATA_W3_RSVD_MASK GENMASK(17, 14) -#define INTR_CTXT_DATA_W3_PASID_EN_MASK BIT(13) -#define INTR_CTXT_DATA_W3_PASID_H_MASK GENMASK(12, 0) -#define INTR_CTXT_DATA_W2_PASID_L_MASK GENMASK(31, 23) -#define INTR_CTXT_DATA_W2_HOST_ID_MASK GENMASK(22, 19) -#define INTR_CTXT_DATA_W2_AT_MASK BIT(18) -#define INTR_CTXT_DATA_W2_PIDX_MASK GENMASK(17, 6) -#define INTR_CTXT_DATA_W2_PAGE_SIZE_MASK GENMASK(5, 3) -#define INTR_CTXT_DATA_W2_BADDR_4K_H_MASK GENMASK(2, 0) -#define INTR_CTXT_DATA_W1_BADDR_4K_M_MASK GENMASK(31, 0) -#define INTR_CTXT_DATA_W0_BADDR_4K_L_MASK GENMASK(31, 15) -#define INTR_CTXT_DATA_W0_COLOR_MASK BIT(14) -#define INTR_CTXT_DATA_W0_INT_ST_MASK BIT(13) -#define INTR_CTXT_DATA_W0_RSVD1_MASK BIT(12) -#define INTR_CTXT_DATA_W0_VEC_MASK GENMASK(11, 1) -#define INTR_CTXT_DATA_W0_VALID_MASK BIT(0) - -#ifdef __cplusplus -} -#endif - -#endif - diff --git a/QDMA/windows/sys/libqdma/source/qdma_access/eqdma_soft_access/eqdma_soft_reg_dump.c b/QDMA/windows/sys/libqdma/source/qdma_access/eqdma_soft_access/eqdma_soft_reg_dump.c deleted file mode 100644 index 8d3c0880d..000000000 --- a/QDMA/windows/sys/libqdma/source/qdma_access/eqdma_soft_access/eqdma_soft_reg_dump.c +++ /dev/null @@ -1,3938 +0,0 @@ -/* - * Copyright (C) 2020 Xilinx, Inc - * - * Licensed under the Apache License, Version 2.0 (the "License"). You may - * not use this file except in compliance with the License. You may obtain - * a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - */ - - -#include "eqdma_soft_reg.h" -#include "qdma_reg_dump.h" - -#ifdef ENABLE_WPP_TRACING -#include "eqdma_soft_reg_dump.tmh" -#endif - - -static struct regfield_info - cfg_blk_identifier_field_info[] = { - {"CFG_BLK_IDENTIFIER", - CFG_BLK_IDENTIFIER_MASK}, - {"CFG_BLK_IDENTIFIER_1", - CFG_BLK_IDENTIFIER_1_MASK}, - {"CFG_BLK_IDENTIFIER_RSVD_1", - CFG_BLK_IDENTIFIER_RSVD_1_MASK}, - {"CFG_BLK_IDENTIFIER_VERSION", - CFG_BLK_IDENTIFIER_VERSION_MASK}, -}; - - -static struct regfield_info - cfg_blk_pcie_max_pld_size_field_info[] = { - {"CFG_BLK_PCIE_MAX_PLD_SIZE_RSVD_1", - CFG_BLK_PCIE_MAX_PLD_SIZE_RSVD_1_MASK}, - {"CFG_BLK_PCIE_MAX_PLD_SIZE_PROG", - CFG_BLK_PCIE_MAX_PLD_SIZE_PROG_MASK}, - {"CFG_BLK_PCIE_MAX_PLD_SIZE_RSVD_2", - CFG_BLK_PCIE_MAX_PLD_SIZE_RSVD_2_MASK}, - {"CFG_BLK_PCIE_MAX_PLD_SIZE_ISSUED", - CFG_BLK_PCIE_MAX_PLD_SIZE_ISSUED_MASK}, -}; - - -static struct regfield_info - cfg_blk_pcie_max_read_req_size_field_info[] = { - {"CFG_BLK_PCIE_MAX_READ_REQ_SIZE_RSVD_1", - CFG_BLK_PCIE_MAX_READ_REQ_SIZE_RSVD_1_MASK}, - {"CFG_BLK_PCIE_MAX_READ_REQ_SIZE_PROG", - CFG_BLK_PCIE_MAX_READ_REQ_SIZE_PROG_MASK}, - {"CFG_BLK_PCIE_MAX_READ_REQ_SIZE_RSVD_2", - CFG_BLK_PCIE_MAX_READ_REQ_SIZE_RSVD_2_MASK}, - {"CFG_BLK_PCIE_MAX_READ_REQ_SIZE_ISSUED", - CFG_BLK_PCIE_MAX_READ_REQ_SIZE_ISSUED_MASK}, -}; - - -static struct regfield_info - cfg_blk_system_id_field_info[] = { - {"CFG_BLK_SYSTEM_ID_RSVD_1", - CFG_BLK_SYSTEM_ID_RSVD_1_MASK}, - {"CFG_BLK_SYSTEM_ID_INST_TYPE", - CFG_BLK_SYSTEM_ID_INST_TYPE_MASK}, - {"CFG_BLK_SYSTEM_ID", - CFG_BLK_SYSTEM_ID_MASK}, -}; - - -static struct regfield_info - cfg_blk_msix_enable_field_info[] = { - {"CFG_BLK_MSIX_ENABLE", - CFG_BLK_MSIX_ENABLE_MASK}, -}; - - -static struct regfield_info - cfg_pcie_data_width_field_info[] = { - {"CFG_PCIE_DATA_WIDTH_RSVD_1", - CFG_PCIE_DATA_WIDTH_RSVD_1_MASK}, - {"CFG_PCIE_DATA_WIDTH_DATAPATH", - CFG_PCIE_DATA_WIDTH_DATAPATH_MASK}, -}; - - -static struct regfield_info - cfg_pcie_ctl_field_info[] = { - {"CFG_PCIE_CTL_RSVD_1", - CFG_PCIE_CTL_RSVD_1_MASK}, - {"CFG_PCIE_CTL_MGMT_AXIL_CTRL", - CFG_PCIE_CTL_MGMT_AXIL_CTRL_MASK}, - {"CFG_PCIE_CTL_RSVD_2", - CFG_PCIE_CTL_RSVD_2_MASK}, - {"CFG_PCIE_CTL_RRQ_DISABLE", - CFG_PCIE_CTL_RRQ_DISABLE_MASK}, - {"CFG_PCIE_CTL_RELAXED_ORDERING", - CFG_PCIE_CTL_RELAXED_ORDERING_MASK}, -}; - - -static struct regfield_info - cfg_blk_msi_enable_field_info[] = { - {"CFG_BLK_MSI_ENABLE", - CFG_BLK_MSI_ENABLE_MASK}, -}; - - -static struct regfield_info - cfg_axi_user_max_pld_size_field_info[] = { - {"CFG_AXI_USER_MAX_PLD_SIZE_RSVD_1", - CFG_AXI_USER_MAX_PLD_SIZE_RSVD_1_MASK}, - {"CFG_AXI_USER_MAX_PLD_SIZE_ISSUED", - CFG_AXI_USER_MAX_PLD_SIZE_ISSUED_MASK}, - {"CFG_AXI_USER_MAX_PLD_SIZE_RSVD_2", - CFG_AXI_USER_MAX_PLD_SIZE_RSVD_2_MASK}, - {"CFG_AXI_USER_MAX_PLD_SIZE_PROG", - CFG_AXI_USER_MAX_PLD_SIZE_PROG_MASK}, -}; - - -static struct regfield_info - cfg_axi_user_max_read_req_size_field_info[] = { - {"CFG_AXI_USER_MAX_READ_REQ_SIZE_RSVD_1", - CFG_AXI_USER_MAX_READ_REQ_SIZE_RSVD_1_MASK}, - {"CFG_AXI_USER_MAX_READ_REQ_SIZE_USISSUED", - CFG_AXI_USER_MAX_READ_REQ_SIZE_USISSUED_MASK}, - {"CFG_AXI_USER_MAX_READ_REQ_SIZE_RSVD_2", - CFG_AXI_USER_MAX_READ_REQ_SIZE_RSVD_2_MASK}, - {"CFG_AXI_USER_MAX_READ_REQ_SIZE_USPROG", - CFG_AXI_USER_MAX_READ_REQ_SIZE_USPROG_MASK}, -}; - - -static struct regfield_info - cfg_blk_misc_ctl_field_info[] = { - {"CFG_BLK_MISC_CTL_RSVD_1", - CFG_BLK_MISC_CTL_RSVD_1_MASK}, - {"CFG_BLK_MISC_CTL_10B_TAG_EN", - CFG_BLK_MISC_CTL_10B_TAG_EN_MASK}, - {"CFG_BLK_MISC_CTL_RSVD_2", - CFG_BLK_MISC_CTL_RSVD_2_MASK}, - {"CFG_BLK_MISC_CTL_AXI_WBK", - CFG_BLK_MISC_CTL_AXI_WBK_MASK}, - {"CFG_BLK_MISC_CTL_AXI_DSC", - CFG_BLK_MISC_CTL_AXI_DSC_MASK}, - {"CFG_BLK_MISC_CTL_NUM_TAG", - CFG_BLK_MISC_CTL_NUM_TAG_MASK}, - {"CFG_BLK_MISC_CTL_RSVD_3", - CFG_BLK_MISC_CTL_RSVD_3_MASK}, - {"CFG_BLK_MISC_CTL_RQ_METERING_MULTIPLIER", - CFG_BLK_MISC_CTL_RQ_METERING_MULTIPLIER_MASK}, -}; - - -static struct regfield_info - cfg_pl_cred_ctl_field_info[] = { - {"CFG_PL_CRED_CTL_RSVD_1", - CFG_PL_CRED_CTL_RSVD_1_MASK}, - {"CFG_PL_CRED_CTL_SLAVE_CRD_RLS", - CFG_PL_CRED_CTL_SLAVE_CRD_RLS_MASK}, - {"CFG_PL_CRED_CTL_RSVD_2", - CFG_PL_CRED_CTL_RSVD_2_MASK}, - {"CFG_PL_CRED_CTL_MASTER_CRD_RST", - CFG_PL_CRED_CTL_MASTER_CRD_RST_MASK}, -}; - - -static struct regfield_info - cfg_blk_scratch_field_info[] = { - {"CFG_BLK_SCRATCH", - CFG_BLK_SCRATCH_MASK}, -}; - - -static struct regfield_info - cfg_gic_field_info[] = { - {"CFG_GIC_RSVD_1", - CFG_GIC_RSVD_1_MASK}, - {"CFG_GIC_GIC_IRQ", - CFG_GIC_GIC_IRQ_MASK}, -}; - - -static struct regfield_info - ram_sbe_msk_1_a_field_info[] = { - {"RAM_SBE_MSK_1_A", - RAM_SBE_MSK_1_A_MASK}, -}; - - -static struct regfield_info - ram_sbe_sts_1_a_field_info[] = { - {"RAM_SBE_STS_1_A_RSVD", - RAM_SBE_STS_1_A_RSVD_MASK}, - {"RAM_SBE_STS_1_A_PFCH_CTXT_CAM_RAM_1", - RAM_SBE_STS_1_A_PFCH_CTXT_CAM_RAM_1_MASK}, - {"RAM_SBE_STS_1_A_PFCH_CTXT_CAM_RAM_0", - RAM_SBE_STS_1_A_PFCH_CTXT_CAM_RAM_0_MASK}, - {"RAM_SBE_STS_1_A_TAG_EVEN_RAM", - RAM_SBE_STS_1_A_TAG_EVEN_RAM_MASK}, - {"RAM_SBE_STS_1_A_TAG_ODD_RAM", - RAM_SBE_STS_1_A_TAG_ODD_RAM_MASK}, - {"RAM_SBE_STS_1_A_RC_RRQ_EVEN_RAM", - RAM_SBE_STS_1_A_RC_RRQ_EVEN_RAM_MASK}, -}; - - -static struct regfield_info - ram_dbe_msk_1_a_field_info[] = { - {"RAM_DBE_MSK_1_A", - RAM_DBE_MSK_1_A_MASK}, -}; - - -static struct regfield_info - ram_dbe_sts_1_a_field_info[] = { - {"RAM_DBE_STS_1_A_RSVD", - RAM_DBE_STS_1_A_RSVD_MASK}, - {"RAM_DBE_STS_1_A_PFCH_CTXT_CAM_RAM_1", - RAM_DBE_STS_1_A_PFCH_CTXT_CAM_RAM_1_MASK}, - {"RAM_DBE_STS_1_A_PFCH_CTXT_CAM_RAM_0", - RAM_DBE_STS_1_A_PFCH_CTXT_CAM_RAM_0_MASK}, - {"RAM_DBE_STS_1_A_TAG_EVEN_RAM", - RAM_DBE_STS_1_A_TAG_EVEN_RAM_MASK}, - {"RAM_DBE_STS_1_A_TAG_ODD_RAM", - RAM_DBE_STS_1_A_TAG_ODD_RAM_MASK}, - {"RAM_DBE_STS_1_A_RC_RRQ_EVEN_RAM", - RAM_DBE_STS_1_A_RC_RRQ_EVEN_RAM_MASK}, -}; - - -static struct regfield_info - ram_sbe_msk_a_field_info[] = { - {"RAM_SBE_MSK_A", - RAM_SBE_MSK_A_MASK}, -}; - - -static struct regfield_info - ram_sbe_sts_a_field_info[] = { - {"RAM_SBE_STS_A_RC_RRQ_ODD_RAM", - RAM_SBE_STS_A_RC_RRQ_ODD_RAM_MASK}, - {"RAM_SBE_STS_A_PEND_FIFO_RAM", - RAM_SBE_STS_A_PEND_FIFO_RAM_MASK}, - {"RAM_SBE_STS_A_PFCH_LL_RAM", - RAM_SBE_STS_A_PFCH_LL_RAM_MASK}, - {"RAM_SBE_STS_A_WRB_CTXT_RAM", - RAM_SBE_STS_A_WRB_CTXT_RAM_MASK}, - {"RAM_SBE_STS_A_PFCH_CTXT_RAM", - RAM_SBE_STS_A_PFCH_CTXT_RAM_MASK}, - {"RAM_SBE_STS_A_DESC_REQ_FIFO_RAM", - RAM_SBE_STS_A_DESC_REQ_FIFO_RAM_MASK}, - {"RAM_SBE_STS_A_INT_CTXT_RAM", - RAM_SBE_STS_A_INT_CTXT_RAM_MASK}, - {"RAM_SBE_STS_A_WRB_COAL_DATA_RAM", - RAM_SBE_STS_A_WRB_COAL_DATA_RAM_MASK}, - {"RAM_SBE_STS_A_QID_FIFO_RAM", - RAM_SBE_STS_A_QID_FIFO_RAM_MASK}, - {"RAM_SBE_STS_A_TIMER_FIFO_RAM", - RAM_SBE_STS_A_TIMER_FIFO_RAM_MASK}, - {"RAM_SBE_STS_A_MI_TL_SLV_FIFO_RAM", - RAM_SBE_STS_A_MI_TL_SLV_FIFO_RAM_MASK}, - {"RAM_SBE_STS_A_DSC_CPLD", - RAM_SBE_STS_A_DSC_CPLD_MASK}, - {"RAM_SBE_STS_A_DSC_CPLI", - RAM_SBE_STS_A_DSC_CPLI_MASK}, - {"RAM_SBE_STS_A_DSC_SW_CTXT", - RAM_SBE_STS_A_DSC_SW_CTXT_MASK}, - {"RAM_SBE_STS_A_DSC_CRD_RCV", - RAM_SBE_STS_A_DSC_CRD_RCV_MASK}, - {"RAM_SBE_STS_A_DSC_HW_CTXT", - RAM_SBE_STS_A_DSC_HW_CTXT_MASK}, - {"RAM_SBE_STS_A_FUNC_MAP", - RAM_SBE_STS_A_FUNC_MAP_MASK}, - {"RAM_SBE_STS_A_C2H_WR_BRG_DAT", - RAM_SBE_STS_A_C2H_WR_BRG_DAT_MASK}, - {"RAM_SBE_STS_A_C2H_RD_BRG_DAT", - RAM_SBE_STS_A_C2H_RD_BRG_DAT_MASK}, - {"RAM_SBE_STS_A_H2C_WR_BRG_DAT", - RAM_SBE_STS_A_H2C_WR_BRG_DAT_MASK}, - {"RAM_SBE_STS_A_H2C_RD_BRG_DAT", - RAM_SBE_STS_A_H2C_RD_BRG_DAT_MASK}, - {"RAM_SBE_STS_A_MI_C2H3_DAT", - RAM_SBE_STS_A_MI_C2H3_DAT_MASK}, - {"RAM_SBE_STS_A_MI_C2H2_DAT", - RAM_SBE_STS_A_MI_C2H2_DAT_MASK}, - {"RAM_SBE_STS_A_MI_C2H1_DAT", - RAM_SBE_STS_A_MI_C2H1_DAT_MASK}, - {"RAM_SBE_STS_A_MI_C2H0_DAT", - RAM_SBE_STS_A_MI_C2H0_DAT_MASK}, - {"RAM_SBE_STS_A_MI_H2C3_DAT", - RAM_SBE_STS_A_MI_H2C3_DAT_MASK}, - {"RAM_SBE_STS_A_MI_H2C2_DAT", - RAM_SBE_STS_A_MI_H2C2_DAT_MASK}, - {"RAM_SBE_STS_A_MI_H2C1_DAT", - RAM_SBE_STS_A_MI_H2C1_DAT_MASK}, - {"RAM_SBE_STS_A_MI_H2C0_DAT", - RAM_SBE_STS_A_MI_H2C0_DAT_MASK}, -}; - - -static struct regfield_info - ram_dbe_msk_a_field_info[] = { - {"RAM_DBE_MSK_A", - RAM_DBE_MSK_A_MASK}, -}; - - -static struct regfield_info - ram_dbe_sts_a_field_info[] = { - {"RAM_DBE_STS_A_RC_RRQ_ODD_RAM", - RAM_DBE_STS_A_RC_RRQ_ODD_RAM_MASK}, - {"RAM_DBE_STS_A_PEND_FIFO_RAM", - RAM_DBE_STS_A_PEND_FIFO_RAM_MASK}, - {"RAM_DBE_STS_A_PFCH_LL_RAM", - RAM_DBE_STS_A_PFCH_LL_RAM_MASK}, - {"RAM_DBE_STS_A_WRB_CTXT_RAM", - RAM_DBE_STS_A_WRB_CTXT_RAM_MASK}, - {"RAM_DBE_STS_A_PFCH_CTXT_RAM", - RAM_DBE_STS_A_PFCH_CTXT_RAM_MASK}, - {"RAM_DBE_STS_A_DESC_REQ_FIFO_RAM", - RAM_DBE_STS_A_DESC_REQ_FIFO_RAM_MASK}, - {"RAM_DBE_STS_A_INT_CTXT_RAM", - RAM_DBE_STS_A_INT_CTXT_RAM_MASK}, - {"RAM_DBE_STS_A_WRB_COAL_DATA_RAM", - RAM_DBE_STS_A_WRB_COAL_DATA_RAM_MASK}, - {"RAM_DBE_STS_A_QID_FIFO_RAM", - RAM_DBE_STS_A_QID_FIFO_RAM_MASK}, - {"RAM_DBE_STS_A_TIMER_FIFO_RAM", - RAM_DBE_STS_A_TIMER_FIFO_RAM_MASK}, - {"RAM_DBE_STS_A_MI_TL_SLV_FIFO_RAM", - RAM_DBE_STS_A_MI_TL_SLV_FIFO_RAM_MASK}, - {"RAM_DBE_STS_A_DSC_CPLD", - RAM_DBE_STS_A_DSC_CPLD_MASK}, - {"RAM_DBE_STS_A_DSC_CPLI", - RAM_DBE_STS_A_DSC_CPLI_MASK}, - {"RAM_DBE_STS_A_DSC_SW_CTXT", - RAM_DBE_STS_A_DSC_SW_CTXT_MASK}, - {"RAM_DBE_STS_A_DSC_CRD_RCV", - RAM_DBE_STS_A_DSC_CRD_RCV_MASK}, - {"RAM_DBE_STS_A_DSC_HW_CTXT", - RAM_DBE_STS_A_DSC_HW_CTXT_MASK}, - {"RAM_DBE_STS_A_FUNC_MAP", - RAM_DBE_STS_A_FUNC_MAP_MASK}, - {"RAM_DBE_STS_A_C2H_WR_BRG_DAT", - RAM_DBE_STS_A_C2H_WR_BRG_DAT_MASK}, - {"RAM_DBE_STS_A_C2H_RD_BRG_DAT", - RAM_DBE_STS_A_C2H_RD_BRG_DAT_MASK}, - {"RAM_DBE_STS_A_H2C_WR_BRG_DAT", - RAM_DBE_STS_A_H2C_WR_BRG_DAT_MASK}, - {"RAM_DBE_STS_A_H2C_RD_BRG_DAT", - RAM_DBE_STS_A_H2C_RD_BRG_DAT_MASK}, - {"RAM_DBE_STS_A_MI_C2H3_DAT", - RAM_DBE_STS_A_MI_C2H3_DAT_MASK}, - {"RAM_DBE_STS_A_MI_C2H2_DAT", - RAM_DBE_STS_A_MI_C2H2_DAT_MASK}, - {"RAM_DBE_STS_A_MI_C2H1_DAT", - RAM_DBE_STS_A_MI_C2H1_DAT_MASK}, - {"RAM_DBE_STS_A_MI_C2H0_DAT", - RAM_DBE_STS_A_MI_C2H0_DAT_MASK}, - {"RAM_DBE_STS_A_MI_H2C3_DAT", - RAM_DBE_STS_A_MI_H2C3_DAT_MASK}, - {"RAM_DBE_STS_A_MI_H2C2_DAT", - RAM_DBE_STS_A_MI_H2C2_DAT_MASK}, - {"RAM_DBE_STS_A_MI_H2C1_DAT", - RAM_DBE_STS_A_MI_H2C1_DAT_MASK}, - {"RAM_DBE_STS_A_MI_H2C0_DAT", - RAM_DBE_STS_A_MI_H2C0_DAT_MASK}, -}; - - -static struct regfield_info - glbl2_identifier_field_info[] = { - {"GLBL2_IDENTIFIER", - GLBL2_IDENTIFIER_MASK}, - {"GLBL2_IDENTIFIER_VERSION", - GLBL2_IDENTIFIER_VERSION_MASK}, -}; - - -static struct regfield_info - glbl2_channel_inst_field_info[] = { - {"GLBL2_CHANNEL_INST_RSVD_1", - GLBL2_CHANNEL_INST_RSVD_1_MASK}, - {"GLBL2_CHANNEL_INST_C2H_ST", - GLBL2_CHANNEL_INST_C2H_ST_MASK}, - {"GLBL2_CHANNEL_INST_H2C_ST", - GLBL2_CHANNEL_INST_H2C_ST_MASK}, - {"GLBL2_CHANNEL_INST_RSVD_2", - GLBL2_CHANNEL_INST_RSVD_2_MASK}, - {"GLBL2_CHANNEL_INST_C2H_ENG", - GLBL2_CHANNEL_INST_C2H_ENG_MASK}, - {"GLBL2_CHANNEL_INST_RSVD_3", - GLBL2_CHANNEL_INST_RSVD_3_MASK}, - {"GLBL2_CHANNEL_INST_H2C_ENG", - GLBL2_CHANNEL_INST_H2C_ENG_MASK}, -}; - - -static struct regfield_info - glbl2_channel_mdma_field_info[] = { - {"GLBL2_CHANNEL_MDMA_RSVD_1", - GLBL2_CHANNEL_MDMA_RSVD_1_MASK}, - {"GLBL2_CHANNEL_MDMA_C2H_ST", - GLBL2_CHANNEL_MDMA_C2H_ST_MASK}, - {"GLBL2_CHANNEL_MDMA_H2C_ST", - GLBL2_CHANNEL_MDMA_H2C_ST_MASK}, - {"GLBL2_CHANNEL_MDMA_RSVD_2", - GLBL2_CHANNEL_MDMA_RSVD_2_MASK}, - {"GLBL2_CHANNEL_MDMA_C2H_ENG", - GLBL2_CHANNEL_MDMA_C2H_ENG_MASK}, - {"GLBL2_CHANNEL_MDMA_RSVD_3", - GLBL2_CHANNEL_MDMA_RSVD_3_MASK}, - {"GLBL2_CHANNEL_MDMA_H2C_ENG", - GLBL2_CHANNEL_MDMA_H2C_ENG_MASK}, -}; - - -static struct regfield_info - glbl2_channel_strm_field_info[] = { - {"GLBL2_CHANNEL_STRM_RSVD_1", - GLBL2_CHANNEL_STRM_RSVD_1_MASK}, - {"GLBL2_CHANNEL_STRM_C2H_ST", - GLBL2_CHANNEL_STRM_C2H_ST_MASK}, - {"GLBL2_CHANNEL_STRM_H2C_ST", - GLBL2_CHANNEL_STRM_H2C_ST_MASK}, - {"GLBL2_CHANNEL_STRM_RSVD_2", - GLBL2_CHANNEL_STRM_RSVD_2_MASK}, - {"GLBL2_CHANNEL_STRM_C2H_ENG", - GLBL2_CHANNEL_STRM_C2H_ENG_MASK}, - {"GLBL2_CHANNEL_STRM_RSVD_3", - GLBL2_CHANNEL_STRM_RSVD_3_MASK}, - {"GLBL2_CHANNEL_STRM_H2C_ENG", - GLBL2_CHANNEL_STRM_H2C_ENG_MASK}, -}; - - -static struct regfield_info - glbl2_channel_cap_field_info[] = { - {"GLBL2_CHANNEL_CAP_RSVD_1", - GLBL2_CHANNEL_CAP_RSVD_1_MASK}, - {"GLBL2_CHANNEL_CAP_MULTIQ_MAX", - GLBL2_CHANNEL_CAP_MULTIQ_MAX_MASK}, -}; - - -static struct regfield_info - glbl2_channel_pasid_cap_field_info[] = { - {"GLBL2_CHANNEL_PASID_CAP_RSVD_1", - GLBL2_CHANNEL_PASID_CAP_RSVD_1_MASK}, - {"GLBL2_CHANNEL_PASID_CAP_BRIDGEEN", - GLBL2_CHANNEL_PASID_CAP_BRIDGEEN_MASK}, - {"GLBL2_CHANNEL_PASID_CAP_DMAEN", - GLBL2_CHANNEL_PASID_CAP_DMAEN_MASK}, -}; - - -static struct regfield_info - glbl2_system_id_field_info[] = { - {"GLBL2_SYSTEM_ID_RSVD_1", - GLBL2_SYSTEM_ID_RSVD_1_MASK}, - {"GLBL2_SYSTEM_ID", - GLBL2_SYSTEM_ID_MASK}, -}; - - -static struct regfield_info - glbl2_misc_cap_field_info[] = { - {"GLBL2_MISC_CAP", - GLBL2_MISC_CAP_MASK}, -}; - - -static struct regfield_info - glbl2_dbg_pcie_rq0_field_info[] = { - {"GLBL2_PCIE_RQ0_NPH_AVL", - GLBL2_PCIE_RQ0_NPH_AVL_MASK}, - {"GLBL2_PCIE_RQ0_RCB_AVL", - GLBL2_PCIE_RQ0_RCB_AVL_MASK}, - {"GLBL2_PCIE_RQ0_SLV_RD_CREDS", - GLBL2_PCIE_RQ0_SLV_RD_CREDS_MASK}, - {"GLBL2_PCIE_RQ0_TAG_EP", - GLBL2_PCIE_RQ0_TAG_EP_MASK}, -}; - - -static struct regfield_info - glbl2_dbg_pcie_rq1_field_info[] = { - {"GLBL2_PCIE_RQ1_RSVD_1", - GLBL2_PCIE_RQ1_RSVD_1_MASK}, - {"GLBL2_PCIE_RQ1_TAG_FL", - GLBL2_PCIE_RQ1_TAG_FL_MASK}, - {"GLBL2_PCIE_RQ1_WTLP_HEADER_FIFO_FL", - GLBL2_PCIE_RQ1_WTLP_HEADER_FIFO_FL_MASK}, - {"GLBL2_PCIE_RQ1_WTLP_HEADER_FIFO_EP", - GLBL2_PCIE_RQ1_WTLP_HEADER_FIFO_EP_MASK}, - {"GLBL2_PCIE_RQ1_RQ_FIFO_EP", - GLBL2_PCIE_RQ1_RQ_FIFO_EP_MASK}, - {"GLBL2_PCIE_RQ1_RQ_FIFO_FL", - GLBL2_PCIE_RQ1_RQ_FIFO_FL_MASK}, - {"GLBL2_PCIE_RQ1_TLPSM", - GLBL2_PCIE_RQ1_TLPSM_MASK}, - {"GLBL2_PCIE_RQ1_TLPSM512", - GLBL2_PCIE_RQ1_TLPSM512_MASK}, - {"GLBL2_PCIE_RQ1_RREQ_RCB_OK", - GLBL2_PCIE_RQ1_RREQ_RCB_OK_MASK}, - {"GLBL2_PCIE_RQ1_RREQ0_SLV", - GLBL2_PCIE_RQ1_RREQ0_SLV_MASK}, - {"GLBL2_PCIE_RQ1_RREQ0_VLD", - GLBL2_PCIE_RQ1_RREQ0_VLD_MASK}, - {"GLBL2_PCIE_RQ1_RREQ0_RDY", - GLBL2_PCIE_RQ1_RREQ0_RDY_MASK}, - {"GLBL2_PCIE_RQ1_RREQ1_SLV", - GLBL2_PCIE_RQ1_RREQ1_SLV_MASK}, - {"GLBL2_PCIE_RQ1_RREQ1_VLD", - GLBL2_PCIE_RQ1_RREQ1_VLD_MASK}, - {"GLBL2_PCIE_RQ1_RREQ1_RDY", - GLBL2_PCIE_RQ1_RREQ1_RDY_MASK}, - {"GLBL2_PCIE_RQ1_WTLP_REQ", - GLBL2_PCIE_RQ1_WTLP_REQ_MASK}, - {"GLBL2_PCIE_RQ1_WTLP_STRADDLE", - GLBL2_PCIE_RQ1_WTLP_STRADDLE_MASK}, -}; - - -static struct regfield_info - glbl2_dbg_aximm_wr0_field_info[] = { - {"GLBL2_AXIMM_WR0_RSVD_1", - GLBL2_AXIMM_WR0_RSVD_1_MASK}, - {"GLBL2_AXIMM_WR0_WR_REQ", - GLBL2_AXIMM_WR0_WR_REQ_MASK}, - {"GLBL2_AXIMM_WR0_WR_CHN", - GLBL2_AXIMM_WR0_WR_CHN_MASK}, - {"GLBL2_AXIMM_WR0_WTLP_DATA_FIFO_EP", - GLBL2_AXIMM_WR0_WTLP_DATA_FIFO_EP_MASK}, - {"GLBL2_AXIMM_WR0_WPL_FIFO_EP", - GLBL2_AXIMM_WR0_WPL_FIFO_EP_MASK}, - {"GLBL2_AXIMM_WR0_BRSP_CLAIM_CHN", - GLBL2_AXIMM_WR0_BRSP_CLAIM_CHN_MASK}, - {"GLBL2_AXIMM_WR0_WRREQ_CNT", - GLBL2_AXIMM_WR0_WRREQ_CNT_MASK}, - {"GLBL2_AXIMM_WR0_BID", - GLBL2_AXIMM_WR0_BID_MASK}, - {"GLBL2_AXIMM_WR0_BVALID", - GLBL2_AXIMM_WR0_BVALID_MASK}, - {"GLBL2_AXIMM_WR0_BREADY", - GLBL2_AXIMM_WR0_BREADY_MASK}, - {"GLBL2_AXIMM_WR0_WVALID", - GLBL2_AXIMM_WR0_WVALID_MASK}, - {"GLBL2_AXIMM_WR0_WREADY", - GLBL2_AXIMM_WR0_WREADY_MASK}, - {"GLBL2_AXIMM_WR0_AWID", - GLBL2_AXIMM_WR0_AWID_MASK}, - {"GLBL2_AXIMM_WR0_AWVALID", - GLBL2_AXIMM_WR0_AWVALID_MASK}, - {"GLBL2_AXIMM_WR0_AWREADY", - GLBL2_AXIMM_WR0_AWREADY_MASK}, -}; - - -static struct regfield_info - glbl2_dbg_aximm_wr1_field_info[] = { - {"GLBL2_AXIMM_WR1_RSVD_1", - GLBL2_AXIMM_WR1_RSVD_1_MASK}, - {"GLBL2_AXIMM_WR1_BRSP_CNT4", - GLBL2_AXIMM_WR1_BRSP_CNT4_MASK}, - {"GLBL2_AXIMM_WR1_BRSP_CNT3", - GLBL2_AXIMM_WR1_BRSP_CNT3_MASK}, - {"GLBL2_AXIMM_WR1_BRSP_CNT2", - GLBL2_AXIMM_WR1_BRSP_CNT2_MASK}, - {"GLBL2_AXIMM_WR1_BRSP_CNT1", - GLBL2_AXIMM_WR1_BRSP_CNT1_MASK}, - {"GLBL2_AXIMM_WR1_BRSP_CNT0", - GLBL2_AXIMM_WR1_BRSP_CNT0_MASK}, -}; - - -static struct regfield_info - glbl2_dbg_aximm_rd0_field_info[] = { - {"GLBL2_AXIMM_RD0_RSVD_1", - GLBL2_AXIMM_RD0_RSVD_1_MASK}, - {"GLBL2_AXIMM_RD0_PND_CNT", - GLBL2_AXIMM_RD0_PND_CNT_MASK}, - {"GLBL2_AXIMM_RD0_RD_REQ", - GLBL2_AXIMM_RD0_RD_REQ_MASK}, - {"GLBL2_AXIMM_RD0_RD_CHNL", - GLBL2_AXIMM_RD0_RD_CHNL_MASK}, - {"GLBL2_AXIMM_RD0_RRSP_CLAIM_CHNL", - GLBL2_AXIMM_RD0_RRSP_CLAIM_CHNL_MASK}, - {"GLBL2_AXIMM_RD0_RID", - GLBL2_AXIMM_RD0_RID_MASK}, - {"GLBL2_AXIMM_RD0_RVALID", - GLBL2_AXIMM_RD0_RVALID_MASK}, - {"GLBL2_AXIMM_RD0_RREADY", - GLBL2_AXIMM_RD0_RREADY_MASK}, - {"GLBL2_AXIMM_RD0_ARID", - GLBL2_AXIMM_RD0_ARID_MASK}, - {"GLBL2_AXIMM_RD0_ARVALID", - GLBL2_AXIMM_RD0_ARVALID_MASK}, - {"GLBL2_AXIMM_RD0_ARREADY", - GLBL2_AXIMM_RD0_ARREADY_MASK}, -}; - - -static struct regfield_info - glbl2_dbg_aximm_rd1_field_info[] = { - {"GLBL2_AXIMM_RD1_RSVD_1", - GLBL2_AXIMM_RD1_RSVD_1_MASK}, - {"GLBL2_AXIMM_RD1_RRSP_CNT4", - GLBL2_AXIMM_RD1_RRSP_CNT4_MASK}, - {"GLBL2_AXIMM_RD1_RRSP_CNT3", - GLBL2_AXIMM_RD1_RRSP_CNT3_MASK}, - {"GLBL2_AXIMM_RD1_RRSP_CNT2", - GLBL2_AXIMM_RD1_RRSP_CNT2_MASK}, - {"GLBL2_AXIMM_RD1_RRSP_CNT1", - GLBL2_AXIMM_RD1_RRSP_CNT1_MASK}, - {"GLBL2_AXIMM_RD1_RRSP_CNT0", - GLBL2_AXIMM_RD1_RRSP_CNT0_MASK}, -}; - - -static struct regfield_info - glbl2_dbg_fab0_field_info[] = { - {"GLBL2_FAB0_H2C_INB_CONV_IN_VLD", - GLBL2_FAB0_H2C_INB_CONV_IN_VLD_MASK}, - {"GLBL2_FAB0_H2C_INB_CONV_IN_RDY", - GLBL2_FAB0_H2C_INB_CONV_IN_RDY_MASK}, - {"GLBL2_FAB0_H2C_SEG_IN_VLD", - GLBL2_FAB0_H2C_SEG_IN_VLD_MASK}, - {"GLBL2_FAB0_H2C_SEG_IN_RDY", - GLBL2_FAB0_H2C_SEG_IN_RDY_MASK}, - {"GLBL2_FAB0_H2C_SEG_OUT_VLD", - GLBL2_FAB0_H2C_SEG_OUT_VLD_MASK}, - {"GLBL2_FAB0_H2C_SEG_OUT_RDY", - GLBL2_FAB0_H2C_SEG_OUT_RDY_MASK}, - {"GLBL2_FAB0_H2C_MST_CRDT_STAT", - GLBL2_FAB0_H2C_MST_CRDT_STAT_MASK}, - {"GLBL2_FAB0_C2H_SLV_AFIFO_FULL", - GLBL2_FAB0_C2H_SLV_AFIFO_FULL_MASK}, - {"GLBL2_FAB0_C2H_SLV_AFIFO_EMPTY", - GLBL2_FAB0_C2H_SLV_AFIFO_EMPTY_MASK}, - {"GLBL2_FAB0_C2H_DESEG_SEG_VLD", - GLBL2_FAB0_C2H_DESEG_SEG_VLD_MASK}, - {"GLBL2_FAB0_C2H_DESEG_SEG_RDY", - GLBL2_FAB0_C2H_DESEG_SEG_RDY_MASK}, - {"GLBL2_FAB0_C2H_DESEG_OUT_VLD", - GLBL2_FAB0_C2H_DESEG_OUT_VLD_MASK}, - {"GLBL2_FAB0_C2H_DESEG_OUT_RDY", - GLBL2_FAB0_C2H_DESEG_OUT_RDY_MASK}, - {"GLBL2_FAB0_C2H_INB_DECONV_OUT_VLD", - GLBL2_FAB0_C2H_INB_DECONV_OUT_VLD_MASK}, - {"GLBL2_FAB0_C2H_INB_DECONV_OUT_RDY", - GLBL2_FAB0_C2H_INB_DECONV_OUT_RDY_MASK}, - {"GLBL2_FAB0_C2H_DSC_CRDT_AFIFO_FULL", - GLBL2_FAB0_C2H_DSC_CRDT_AFIFO_FULL_MASK}, - {"GLBL2_FAB0_C2H_DSC_CRDT_AFIFO_EMPTY", - GLBL2_FAB0_C2H_DSC_CRDT_AFIFO_EMPTY_MASK}, - {"GLBL2_FAB0_IRQ_IN_AFIFO_FULL", - GLBL2_FAB0_IRQ_IN_AFIFO_FULL_MASK}, - {"GLBL2_FAB0_IRQ_IN_AFIFO_EMPTY", - GLBL2_FAB0_IRQ_IN_AFIFO_EMPTY_MASK}, - {"GLBL2_FAB0_IMM_CRD_AFIFO_EMPTY", - GLBL2_FAB0_IMM_CRD_AFIFO_EMPTY_MASK}, -}; - - -static struct regfield_info - glbl2_dbg_fab1_field_info[] = { - {"GLBL2_FAB1_BYP_OUT_CRDT_STAT", - GLBL2_FAB1_BYP_OUT_CRDT_STAT_MASK}, - {"GLBL2_FAB1_TM_DSC_STS_CRDT_STAT", - GLBL2_FAB1_TM_DSC_STS_CRDT_STAT_MASK}, - {"GLBL2_FAB1_C2H_CMN_AFIFO_FULL", - GLBL2_FAB1_C2H_CMN_AFIFO_FULL_MASK}, - {"GLBL2_FAB1_C2H_CMN_AFIFO_EMPTY", - GLBL2_FAB1_C2H_CMN_AFIFO_EMPTY_MASK}, - {"GLBL2_FAB1_RSVD_1", - GLBL2_FAB1_RSVD_1_MASK}, - {"GLBL2_FAB1_C2H_BYP_IN_AFIFO_FULL", - GLBL2_FAB1_C2H_BYP_IN_AFIFO_FULL_MASK}, - {"GLBL2_FAB1_RSVD_2", - GLBL2_FAB1_RSVD_2_MASK}, - {"GLBL2_FAB1_C2H_BYP_IN_AFIFO_EMPTY", - GLBL2_FAB1_C2H_BYP_IN_AFIFO_EMPTY_MASK}, - {"GLBL2_FAB1_RSVD_3", - GLBL2_FAB1_RSVD_3_MASK}, - {"GLBL2_FAB1_H2C_BYP_IN_AFIFO_FULL", - GLBL2_FAB1_H2C_BYP_IN_AFIFO_FULL_MASK}, - {"GLBL2_FAB1_RSVD_4", - GLBL2_FAB1_RSVD_4_MASK}, - {"GLBL2_FAB1_H2C_BYP_IN_AFIFO_EMPTY", - GLBL2_FAB1_H2C_BYP_IN_AFIFO_EMPTY_MASK}, -}; - - -static struct regfield_info - glbl2_dbg_match_sel_field_info[] = { - {"GLBL2_MATCH_SEL_RSV", - GLBL2_MATCH_SEL_RSV_MASK}, - {"GLBL2_MATCH_SEL_CSR_SEL", - GLBL2_MATCH_SEL_CSR_SEL_MASK}, - {"GLBL2_MATCH_SEL_CSR_EN", - GLBL2_MATCH_SEL_CSR_EN_MASK}, - {"GLBL2_MATCH_SEL_ROTATE1", - GLBL2_MATCH_SEL_ROTATE1_MASK}, - {"GLBL2_MATCH_SEL_ROTATE0", - GLBL2_MATCH_SEL_ROTATE0_MASK}, - {"GLBL2_MATCH_SEL_SEL", - GLBL2_MATCH_SEL_SEL_MASK}, -}; - - -static struct regfield_info - glbl2_dbg_match_msk_field_info[] = { - {"GLBL2_MATCH_MSK", - GLBL2_MATCH_MSK_MASK}, -}; - - -static struct regfield_info - glbl2_dbg_match_pat_field_info[] = { - {"GLBL2_MATCH_PAT_PATTERN", - GLBL2_MATCH_PAT_PATTERN_MASK}, -}; - - -static struct regfield_info - glbl_rng_sz_1_field_info[] = { - {"GLBL_RNG_SZ_1_RSVD_1", - GLBL_RNG_SZ_1_RSVD_1_MASK}, - {"GLBL_RNG_SZ_1_RING_SIZE", - GLBL_RNG_SZ_1_RING_SIZE_MASK}, -}; - - -static struct regfield_info - glbl_rng_sz_2_field_info[] = { - {"GLBL_RNG_SZ_2_RSVD_1", - GLBL_RNG_SZ_2_RSVD_1_MASK}, - {"GLBL_RNG_SZ_2_RING_SIZE", - GLBL_RNG_SZ_2_RING_SIZE_MASK}, -}; - - -static struct regfield_info - glbl_rng_sz_3_field_info[] = { - {"GLBL_RNG_SZ_3_RSVD_1", - GLBL_RNG_SZ_3_RSVD_1_MASK}, - {"GLBL_RNG_SZ_3_RING_SIZE", - GLBL_RNG_SZ_3_RING_SIZE_MASK}, -}; - - -static struct regfield_info - glbl_rng_sz_4_field_info[] = { - {"GLBL_RNG_SZ_4_RSVD_1", - GLBL_RNG_SZ_4_RSVD_1_MASK}, - {"GLBL_RNG_SZ_4_RING_SIZE", - GLBL_RNG_SZ_4_RING_SIZE_MASK}, -}; - - -static struct regfield_info - glbl_rng_sz_5_field_info[] = { - {"GLBL_RNG_SZ_5_RSVD_1", - GLBL_RNG_SZ_5_RSVD_1_MASK}, - {"GLBL_RNG_SZ_5_RING_SIZE", - GLBL_RNG_SZ_5_RING_SIZE_MASK}, -}; - - -static struct regfield_info - glbl_rng_sz_6_field_info[] = { - {"GLBL_RNG_SZ_6_RSVD_1", - GLBL_RNG_SZ_6_RSVD_1_MASK}, - {"GLBL_RNG_SZ_6_RING_SIZE", - GLBL_RNG_SZ_6_RING_SIZE_MASK}, -}; - - -static struct regfield_info - glbl_rng_sz_7_field_info[] = { - {"GLBL_RNG_SZ_7_RSVD_1", - GLBL_RNG_SZ_7_RSVD_1_MASK}, - {"GLBL_RNG_SZ_7_RING_SIZE", - GLBL_RNG_SZ_7_RING_SIZE_MASK}, -}; - - -static struct regfield_info - glbl_rng_sz_8_field_info[] = { - {"GLBL_RNG_SZ_8_RSVD_1", - GLBL_RNG_SZ_8_RSVD_1_MASK}, - {"GLBL_RNG_SZ_8_RING_SIZE", - GLBL_RNG_SZ_8_RING_SIZE_MASK}, -}; - - -static struct regfield_info - glbl_rng_sz_9_field_info[] = { - {"GLBL_RNG_SZ_9_RSVD_1", - GLBL_RNG_SZ_9_RSVD_1_MASK}, - {"GLBL_RNG_SZ_9_RING_SIZE", - GLBL_RNG_SZ_9_RING_SIZE_MASK}, -}; - - -static struct regfield_info - glbl_rng_sz_a_field_info[] = { - {"GLBL_RNG_SZ_A_RSVD_1", - GLBL_RNG_SZ_A_RSVD_1_MASK}, - {"GLBL_RNG_SZ_A_RING_SIZE", - GLBL_RNG_SZ_A_RING_SIZE_MASK}, -}; - - -static struct regfield_info - glbl_rng_sz_b_field_info[] = { - {"GLBL_RNG_SZ_B_RSVD_1", - GLBL_RNG_SZ_B_RSVD_1_MASK}, - {"GLBL_RNG_SZ_B_RING_SIZE", - GLBL_RNG_SZ_B_RING_SIZE_MASK}, -}; - - -static struct regfield_info - glbl_rng_sz_c_field_info[] = { - {"GLBL_RNG_SZ_C_RSVD_1", - GLBL_RNG_SZ_C_RSVD_1_MASK}, - {"GLBL_RNG_SZ_C_RING_SIZE", - GLBL_RNG_SZ_C_RING_SIZE_MASK}, -}; - - -static struct regfield_info - glbl_rng_sz_d_field_info[] = { - {"GLBL_RNG_SZ_D_RSVD_1", - GLBL_RNG_SZ_D_RSVD_1_MASK}, - {"GLBL_RNG_SZ_D_RING_SIZE", - GLBL_RNG_SZ_D_RING_SIZE_MASK}, -}; - - -static struct regfield_info - glbl_rng_sz_e_field_info[] = { - {"GLBL_RNG_SZ_E_RSVD_1", - GLBL_RNG_SZ_E_RSVD_1_MASK}, - {"GLBL_RNG_SZ_E_RING_SIZE", - GLBL_RNG_SZ_E_RING_SIZE_MASK}, -}; - - -static struct regfield_info - glbl_rng_sz_f_field_info[] = { - {"GLBL_RNG_SZ_F_RSVD_1", - GLBL_RNG_SZ_F_RSVD_1_MASK}, - {"GLBL_RNG_SZ_F_RING_SIZE", - GLBL_RNG_SZ_F_RING_SIZE_MASK}, -}; - - -static struct regfield_info - glbl_rng_sz_10_field_info[] = { - {"GLBL_RNG_SZ_10_RSVD_1", - GLBL_RNG_SZ_10_RSVD_1_MASK}, - {"GLBL_RNG_SZ_10_RING_SIZE", - GLBL_RNG_SZ_10_RING_SIZE_MASK}, -}; - - -static struct regfield_info - glbl_err_stat_field_info[] = { - {"GLBL_ERR_STAT_RSVD_1", - GLBL_ERR_STAT_RSVD_1_MASK}, - {"GLBL_ERR_STAT_ERR_FAB", - GLBL_ERR_STAT_ERR_FAB_MASK}, - {"GLBL_ERR_STAT_ERR_H2C_ST", - GLBL_ERR_STAT_ERR_H2C_ST_MASK}, - {"GLBL_ERR_STAT_ERR_BDG", - GLBL_ERR_STAT_ERR_BDG_MASK}, - {"GLBL_ERR_STAT_IND_CTXT_CMD_ERR", - GLBL_ERR_STAT_IND_CTXT_CMD_ERR_MASK}, - {"GLBL_ERR_STAT_ERR_C2H_ST", - GLBL_ERR_STAT_ERR_C2H_ST_MASK}, - {"GLBL_ERR_STAT_ERR_C2H_MM_1", - GLBL_ERR_STAT_ERR_C2H_MM_1_MASK}, - {"GLBL_ERR_STAT_ERR_C2H_MM_0", - GLBL_ERR_STAT_ERR_C2H_MM_0_MASK}, - {"GLBL_ERR_STAT_ERR_H2C_MM_1", - GLBL_ERR_STAT_ERR_H2C_MM_1_MASK}, - {"GLBL_ERR_STAT_ERR_H2C_MM_0", - GLBL_ERR_STAT_ERR_H2C_MM_0_MASK}, - {"GLBL_ERR_STAT_ERR_TRQ", - GLBL_ERR_STAT_ERR_TRQ_MASK}, - {"GLBL_ERR_STAT_ERR_DSC", - GLBL_ERR_STAT_ERR_DSC_MASK}, - {"GLBL_ERR_STAT_ERR_RAM_DBE", - GLBL_ERR_STAT_ERR_RAM_DBE_MASK}, - {"GLBL_ERR_STAT_ERR_RAM_SBE", - GLBL_ERR_STAT_ERR_RAM_SBE_MASK}, -}; - - -static struct regfield_info - glbl_err_mask_field_info[] = { - {"GLBL_ERR", - GLBL_ERR_MASK}, -}; - - -static struct regfield_info - glbl_dsc_cfg_field_info[] = { - {"GLBL_DSC_CFG_RSVD_1", - GLBL_DSC_CFG_RSVD_1_MASK}, - {"GLBL_DSC_CFG_UNC_OVR_COR", - GLBL_DSC_CFG_UNC_OVR_COR_MASK}, - {"GLBL_DSC_CFG_CTXT_FER_DIS", - GLBL_DSC_CFG_CTXT_FER_DIS_MASK}, - {"GLBL_DSC_CFG_RSVD_2", - GLBL_DSC_CFG_RSVD_2_MASK}, - {"GLBL_DSC_CFG_MAXFETCH", - GLBL_DSC_CFG_MAXFETCH_MASK}, - {"GLBL_DSC_CFG_WB_ACC_INT", - GLBL_DSC_CFG_WB_ACC_INT_MASK}, -}; - - -static struct regfield_info - glbl_dsc_err_sts_field_info[] = { - {"GLBL_DSC_ERR_STS_RSVD_1", - GLBL_DSC_ERR_STS_RSVD_1_MASK}, - {"GLBL_DSC_ERR_STS_PORT_ID", - GLBL_DSC_ERR_STS_PORT_ID_MASK}, - {"GLBL_DSC_ERR_STS_SBE", - GLBL_DSC_ERR_STS_SBE_MASK}, - {"GLBL_DSC_ERR_STS_DBE", - GLBL_DSC_ERR_STS_DBE_MASK}, - {"GLBL_DSC_ERR_STS_RQ_CANCEL", - GLBL_DSC_ERR_STS_RQ_CANCEL_MASK}, - {"GLBL_DSC_ERR_STS_DSC", - GLBL_DSC_ERR_STS_DSC_MASK}, - {"GLBL_DSC_ERR_STS_DMA", - GLBL_DSC_ERR_STS_DMA_MASK}, - {"GLBL_DSC_ERR_STS_FLR_CANCEL", - GLBL_DSC_ERR_STS_FLR_CANCEL_MASK}, - {"GLBL_DSC_ERR_STS_RSVD_2", - GLBL_DSC_ERR_STS_RSVD_2_MASK}, - {"GLBL_DSC_ERR_STS_DAT_POISON", - GLBL_DSC_ERR_STS_DAT_POISON_MASK}, - {"GLBL_DSC_ERR_STS_TIMEOUT", - GLBL_DSC_ERR_STS_TIMEOUT_MASK}, - {"GLBL_DSC_ERR_STS_FLR", - GLBL_DSC_ERR_STS_FLR_MASK}, - {"GLBL_DSC_ERR_STS_TAG", - GLBL_DSC_ERR_STS_TAG_MASK}, - {"GLBL_DSC_ERR_STS_ADDR", - GLBL_DSC_ERR_STS_ADDR_MASK}, - {"GLBL_DSC_ERR_STS_PARAM", - GLBL_DSC_ERR_STS_PARAM_MASK}, - {"GLBL_DSC_ERR_STS_BCNT", - GLBL_DSC_ERR_STS_BCNT_MASK}, - {"GLBL_DSC_ERR_STS_UR_CA", - GLBL_DSC_ERR_STS_UR_CA_MASK}, - {"GLBL_DSC_ERR_STS_POISON", - GLBL_DSC_ERR_STS_POISON_MASK}, -}; - - -static struct regfield_info - glbl_dsc_err_msk_field_info[] = { - {"GLBL_DSC_ERR_MSK", - GLBL_DSC_ERR_MSK_MASK}, -}; - - -static struct regfield_info - glbl_dsc_err_log0_field_info[] = { - {"GLBL_DSC_ERR_LOG0_VALID", - GLBL_DSC_ERR_LOG0_VALID_MASK}, - {"GLBL_DSC_ERR_LOG0_SEL", - GLBL_DSC_ERR_LOG0_SEL_MASK}, - {"GLBL_DSC_ERR_LOG0_RSVD_1", - GLBL_DSC_ERR_LOG0_RSVD_1_MASK}, - {"GLBL_DSC_ERR_LOG0_QID", - GLBL_DSC_ERR_LOG0_QID_MASK}, -}; - - -static struct regfield_info - glbl_dsc_err_log1_field_info[] = { - {"GLBL_DSC_ERR_LOG1_RSVD_1", - GLBL_DSC_ERR_LOG1_RSVD_1_MASK}, - {"GLBL_DSC_ERR_LOG1_CIDX", - GLBL_DSC_ERR_LOG1_CIDX_MASK}, - {"GLBL_DSC_ERR_LOG1_RSVD_2", - GLBL_DSC_ERR_LOG1_RSVD_2_MASK}, - {"GLBL_DSC_ERR_LOG1_SUB_TYPE", - GLBL_DSC_ERR_LOG1_SUB_TYPE_MASK}, - {"GLBL_DSC_ERR_LOG1_ERR_TYPE", - GLBL_DSC_ERR_LOG1_ERR_TYPE_MASK}, -}; - - -static struct regfield_info - glbl_trq_err_sts_field_info[] = { - {"GLBL_TRQ_ERR_STS_RSVD_1", - GLBL_TRQ_ERR_STS_RSVD_1_MASK}, - {"GLBL_TRQ_ERR_STS_TCP_QSPC_TIMEOUT", - GLBL_TRQ_ERR_STS_TCP_QSPC_TIMEOUT_MASK}, - {"GLBL_TRQ_ERR_STS_RSVD_2", - GLBL_TRQ_ERR_STS_RSVD_2_MASK}, - {"GLBL_TRQ_ERR_STS_QID_RANGE", - GLBL_TRQ_ERR_STS_QID_RANGE_MASK}, - {"GLBL_TRQ_ERR_STS_QSPC_UNMAPPED", - GLBL_TRQ_ERR_STS_QSPC_UNMAPPED_MASK}, - {"GLBL_TRQ_ERR_STS_TCP_CSR_TIMEOUT", - GLBL_TRQ_ERR_STS_TCP_CSR_TIMEOUT_MASK}, - {"GLBL_TRQ_ERR_STS_RSVD_3", - GLBL_TRQ_ERR_STS_RSVD_3_MASK}, - {"GLBL_TRQ_ERR_STS_VF_ACCESS_ERR", - GLBL_TRQ_ERR_STS_VF_ACCESS_ERR_MASK}, - {"GLBL_TRQ_ERR_STS_CSR_UNMAPPED", - GLBL_TRQ_ERR_STS_CSR_UNMAPPED_MASK}, -}; - - -static struct regfield_info - glbl_trq_err_msk_field_info[] = { - {"GLBL_TRQ_ERR_MSK", - GLBL_TRQ_ERR_MSK_MASK}, -}; - - -static struct regfield_info - glbl_trq_err_log_field_info[] = { - {"GLBL_TRQ_ERR_LOG_SRC", - GLBL_TRQ_ERR_LOG_SRC_MASK}, - {"GLBL_TRQ_ERR_LOG_TARGET", - GLBL_TRQ_ERR_LOG_TARGET_MASK}, - {"GLBL_TRQ_ERR_LOG_FUNC", - GLBL_TRQ_ERR_LOG_FUNC_MASK}, - {"GLBL_TRQ_ERR_LOG_ADDRESS", - GLBL_TRQ_ERR_LOG_ADDRESS_MASK}, -}; - - -static struct regfield_info - glbl_dsc_dbg_dat0_field_info[] = { - {"GLBL_DSC_DAT0_RSVD_1", - GLBL_DSC_DAT0_RSVD_1_MASK}, - {"GLBL_DSC_DAT0_CTXT_ARB_DIR", - GLBL_DSC_DAT0_CTXT_ARB_DIR_MASK}, - {"GLBL_DSC_DAT0_CTXT_ARB_QID", - GLBL_DSC_DAT0_CTXT_ARB_QID_MASK}, - {"GLBL_DSC_DAT0_CTXT_ARB_REQ", - GLBL_DSC_DAT0_CTXT_ARB_REQ_MASK}, - {"GLBL_DSC_DAT0_IRQ_FIFO_FL", - GLBL_DSC_DAT0_IRQ_FIFO_FL_MASK}, - {"GLBL_DSC_DAT0_TMSTALL", - GLBL_DSC_DAT0_TMSTALL_MASK}, - {"GLBL_DSC_DAT0_RRQ_STALL", - GLBL_DSC_DAT0_RRQ_STALL_MASK}, - {"GLBL_DSC_DAT0_RCP_FIFO_SPC_STALL", - GLBL_DSC_DAT0_RCP_FIFO_SPC_STALL_MASK}, - {"GLBL_DSC_DAT0_RRQ_FIFO_SPC_STALL", - GLBL_DSC_DAT0_RRQ_FIFO_SPC_STALL_MASK}, - {"GLBL_DSC_DAT0_FAB_MRKR_RSP_STALL", - GLBL_DSC_DAT0_FAB_MRKR_RSP_STALL_MASK}, - {"GLBL_DSC_DAT0_DSC_OUT_STALL", - GLBL_DSC_DAT0_DSC_OUT_STALL_MASK}, -}; - - -static struct regfield_info - glbl_dsc_dbg_dat1_field_info[] = { - {"GLBL_DSC_DAT1_RSVD_1", - GLBL_DSC_DAT1_RSVD_1_MASK}, - {"GLBL_DSC_DAT1_EVT_SPC_C2H", - GLBL_DSC_DAT1_EVT_SPC_C2H_MASK}, - {"GLBL_DSC_DAT1_EVT_SP_H2C", - GLBL_DSC_DAT1_EVT_SP_H2C_MASK}, - {"GLBL_DSC_DAT1_DSC_SPC_C2H", - GLBL_DSC_DAT1_DSC_SPC_C2H_MASK}, - {"GLBL_DSC_DAT1_DSC_SPC_H2C", - GLBL_DSC_DAT1_DSC_SPC_H2C_MASK}, -}; - - -static struct regfield_info - glbl_dsc_dbg_ctl_field_info[] = { - {"GLBL_DSC_CTL_RSVD_1", - GLBL_DSC_CTL_RSVD_1_MASK}, - {"GLBL_DSC_CTL_SELECT", - GLBL_DSC_CTL_SELECT_MASK}, -}; - - -static struct regfield_info - glbl_dsc_err_log2_field_info[] = { - {"GLBL_DSC_ERR_LOG2_OLD_PIDX", - GLBL_DSC_ERR_LOG2_OLD_PIDX_MASK}, - {"GLBL_DSC_ERR_LOG2_NEW_PIDX", - GLBL_DSC_ERR_LOG2_NEW_PIDX_MASK}, -}; - - -static struct regfield_info - glbl_glbl_interrupt_cfg_field_info[] = { - {"GLBL_GLBL_INTERRUPT_CFG_RSVD_1", - GLBL_GLBL_INTERRUPT_CFG_RSVD_1_MASK}, - {"GLBL_GLBL_INTERRUPT_CFG_LGCY_INTR_PENDING", - GLBL_GLBL_INTERRUPT_CFG_LGCY_INTR_PENDING_MASK}, - {"GLBL_GLBL_INTERRUPT_CFG_EN_LGCY_INTR", - GLBL_GLBL_INTERRUPT_CFG_EN_LGCY_INTR_MASK}, -}; - - -static struct regfield_info - glbl_vch_host_profile_field_info[] = { - {"GLBL_VCH_HOST_PROFILE_RSVD_1", - GLBL_VCH_HOST_PROFILE_RSVD_1_MASK}, - {"GLBL_VCH_HOST_PROFILE_2C_MM", - GLBL_VCH_HOST_PROFILE_2C_MM_MASK}, - {"GLBL_VCH_HOST_PROFILE_2C_ST", - GLBL_VCH_HOST_PROFILE_2C_ST_MASK}, - {"GLBL_VCH_HOST_PROFILE_VCH_DSC", - GLBL_VCH_HOST_PROFILE_VCH_DSC_MASK}, - {"GLBL_VCH_HOST_PROFILE_VCH_INT_MSG", - GLBL_VCH_HOST_PROFILE_VCH_INT_MSG_MASK}, - {"GLBL_VCH_HOST_PROFILE_VCH_INT_AGGR", - GLBL_VCH_HOST_PROFILE_VCH_INT_AGGR_MASK}, - {"GLBL_VCH_HOST_PROFILE_VCH_CMPT", - GLBL_VCH_HOST_PROFILE_VCH_CMPT_MASK}, - {"GLBL_VCH_HOST_PROFILE_VCH_C2H_PLD", - GLBL_VCH_HOST_PROFILE_VCH_C2H_PLD_MASK}, -}; - - -static struct regfield_info - glbl_bridge_host_profile_field_info[] = { - {"GLBL_BRIDGE_HOST_PROFILE_RSVD_1", - GLBL_BRIDGE_HOST_PROFILE_RSVD_1_MASK}, - {"GLBL_BRIDGE_HOST_PROFILE_BDGID", - GLBL_BRIDGE_HOST_PROFILE_BDGID_MASK}, -}; - - -static struct regfield_info - aximm_irq_dest_addr_field_info[] = { - {"AXIMM_IRQ_DEST_ADDR_ADDR", - AXIMM_IRQ_DEST_ADDR_ADDR_MASK}, -}; - - -static struct regfield_info - fab_err_log_field_info[] = { - {"FAB_ERR_LOG_RSVD_1", - FAB_ERR_LOG_RSVD_1_MASK}, - {"FAB_ERR_LOG_SRC", - FAB_ERR_LOG_SRC_MASK}, -}; - - -static struct regfield_info - glbl_req_err_sts_field_info[] = { - {"GLBL_REQ_ERR_STS_RSVD_1", - GLBL_REQ_ERR_STS_RSVD_1_MASK}, - {"GLBL_REQ_ERR_STS_RC_DISCONTINUE", - GLBL_REQ_ERR_STS_RC_DISCONTINUE_MASK}, - {"GLBL_REQ_ERR_STS_RC_PRTY", - GLBL_REQ_ERR_STS_RC_PRTY_MASK}, - {"GLBL_REQ_ERR_STS_RC_FLR", - GLBL_REQ_ERR_STS_RC_FLR_MASK}, - {"GLBL_REQ_ERR_STS_RC_TIMEOUT", - GLBL_REQ_ERR_STS_RC_TIMEOUT_MASK}, - {"GLBL_REQ_ERR_STS_RC_INV_BCNT", - GLBL_REQ_ERR_STS_RC_INV_BCNT_MASK}, - {"GLBL_REQ_ERR_STS_RC_INV_TAG", - GLBL_REQ_ERR_STS_RC_INV_TAG_MASK}, - {"GLBL_REQ_ERR_STS_RC_START_ADDR_MISMCH", - GLBL_REQ_ERR_STS_RC_START_ADDR_MISMCH_MASK}, - {"GLBL_REQ_ERR_STS_RC_RID_TC_ATTR_MISMCH", - GLBL_REQ_ERR_STS_RC_RID_TC_ATTR_MISMCH_MASK}, - {"GLBL_REQ_ERR_STS_RC_NO_DATA", - GLBL_REQ_ERR_STS_RC_NO_DATA_MASK}, - {"GLBL_REQ_ERR_STS_RC_UR_CA_CRS", - GLBL_REQ_ERR_STS_RC_UR_CA_CRS_MASK}, - {"GLBL_REQ_ERR_STS_RC_POISONED", - GLBL_REQ_ERR_STS_RC_POISONED_MASK}, -}; - - -static struct regfield_info - glbl_req_err_msk_field_info[] = { - {"GLBL_REQ_ERR_MSK", - GLBL_REQ_ERR_MSK_MASK}, -}; - - -static struct regfield_info - ind_ctxt_data_field_info[] = { - {"IND_CTXT_DATA_DATA", - IND_CTXT_DATA_DATA_MASK}, -}; - - -static struct regfield_info - ind_ctxt_mask_field_info[] = { - {"IND_CTXT", - IND_CTXT_MASK}, -}; - - -static struct regfield_info - ind_ctxt_cmd_field_info[] = { - {"IND_CTXT_CMD_RSVD_1", - IND_CTXT_CMD_RSVD_1_MASK}, - {"IND_CTXT_CMD_QID", - IND_CTXT_CMD_QID_MASK}, - {"IND_CTXT_CMD_OP", - IND_CTXT_CMD_OP_MASK}, - {"IND_CTXT_CMD_SEL", - IND_CTXT_CMD_SEL_MASK}, - {"IND_CTXT_CMD_BUSY", - IND_CTXT_CMD_BUSY_MASK}, -}; - - -static struct regfield_info - c2h_timer_cnt_field_info[] = { - {"C2H_TIMER_CNT_RSVD_1", - C2H_TIMER_CNT_RSVD_1_MASK}, - {"C2H_TIMER_CNT", - C2H_TIMER_CNT_MASK}, -}; - - -static struct regfield_info - c2h_cnt_th_field_info[] = { - {"C2H_CNT_TH_RSVD_1", - C2H_CNT_TH_RSVD_1_MASK}, - {"C2H_CNT_TH_THESHOLD_CNT", - C2H_CNT_TH_THESHOLD_CNT_MASK}, -}; - - -static struct regfield_info - c2h_stat_s_axis_c2h_accepted_field_info[] = { - {"C2H_STAT_S_AXIS_C2H_ACCEPTED", - C2H_STAT_S_AXIS_C2H_ACCEPTED_MASK}, -}; - - -static struct regfield_info - c2h_stat_s_axis_wrb_accepted_field_info[] = { - {"C2H_STAT_S_AXIS_WRB_ACCEPTED", - C2H_STAT_S_AXIS_WRB_ACCEPTED_MASK}, -}; - - -static struct regfield_info - c2h_stat_desc_rsp_pkt_accepted_field_info[] = { - {"C2H_STAT_DESC_RSP_PKT_ACCEPTED_D", - C2H_STAT_DESC_RSP_PKT_ACCEPTED_D_MASK}, -}; - - -static struct regfield_info - c2h_stat_axis_pkg_cmp_field_info[] = { - {"C2H_STAT_AXIS_PKG_CMP", - C2H_STAT_AXIS_PKG_CMP_MASK}, -}; - - -static struct regfield_info - c2h_stat_desc_rsp_accepted_field_info[] = { - {"C2H_STAT_DESC_RSP_ACCEPTED_D", - C2H_STAT_DESC_RSP_ACCEPTED_D_MASK}, -}; - - -static struct regfield_info - c2h_stat_desc_rsp_cmp_field_info[] = { - {"C2H_STAT_DESC_RSP_CMP_D", - C2H_STAT_DESC_RSP_CMP_D_MASK}, -}; - - -static struct regfield_info - c2h_stat_wrq_out_field_info[] = { - {"C2H_STAT_WRQ_OUT", - C2H_STAT_WRQ_OUT_MASK}, -}; - - -static struct regfield_info - c2h_stat_wpl_ren_accepted_field_info[] = { - {"C2H_STAT_WPL_REN_ACCEPTED", - C2H_STAT_WPL_REN_ACCEPTED_MASK}, -}; - - -static struct regfield_info - c2h_stat_total_wrq_len_field_info[] = { - {"C2H_STAT_TOTAL_WRQ_LEN", - C2H_STAT_TOTAL_WRQ_LEN_MASK}, -}; - - -static struct regfield_info - c2h_stat_total_wpl_len_field_info[] = { - {"C2H_STAT_TOTAL_WPL_LEN", - C2H_STAT_TOTAL_WPL_LEN_MASK}, -}; - - -static struct regfield_info - c2h_buf_sz_field_info[] = { - {"C2H_BUF_SZ_IZE", - C2H_BUF_SZ_IZE_MASK}, -}; - - -static struct regfield_info - c2h_err_stat_field_info[] = { - {"C2H_ERR_STAT_RSVD_1", - C2H_ERR_STAT_RSVD_1_MASK}, - {"C2H_ERR_STAT_WRB_PORT_ID_ERR", - C2H_ERR_STAT_WRB_PORT_ID_ERR_MASK}, - {"C2H_ERR_STAT_HDR_PAR_ERR", - C2H_ERR_STAT_HDR_PAR_ERR_MASK}, - {"C2H_ERR_STAT_HDR_ECC_COR_ERR", - C2H_ERR_STAT_HDR_ECC_COR_ERR_MASK}, - {"C2H_ERR_STAT_HDR_ECC_UNC_ERR", - C2H_ERR_STAT_HDR_ECC_UNC_ERR_MASK}, - {"C2H_ERR_STAT_AVL_RING_DSC_ERR", - C2H_ERR_STAT_AVL_RING_DSC_ERR_MASK}, - {"C2H_ERR_STAT_WRB_PRTY_ERR", - C2H_ERR_STAT_WRB_PRTY_ERR_MASK}, - {"C2H_ERR_STAT_WRB_CIDX_ERR", - C2H_ERR_STAT_WRB_CIDX_ERR_MASK}, - {"C2H_ERR_STAT_WRB_QFULL_ERR", - C2H_ERR_STAT_WRB_QFULL_ERR_MASK}, - {"C2H_ERR_STAT_WRB_INV_Q_ERR", - C2H_ERR_STAT_WRB_INV_Q_ERR_MASK}, - {"C2H_ERR_STAT_RSVD_2", - C2H_ERR_STAT_RSVD_2_MASK}, - {"C2H_ERR_STAT_PORT_ID_CTXT_MISMATCH", - C2H_ERR_STAT_PORT_ID_CTXT_MISMATCH_MASK}, - {"C2H_ERR_STAT_ERR_DESC_CNT", - C2H_ERR_STAT_ERR_DESC_CNT_MASK}, - {"C2H_ERR_STAT_RSVD_3", - C2H_ERR_STAT_RSVD_3_MASK}, - {"C2H_ERR_STAT_MSI_INT_FAIL", - C2H_ERR_STAT_MSI_INT_FAIL_MASK}, - {"C2H_ERR_STAT_ENG_WPL_DATA_PAR_ERR", - C2H_ERR_STAT_ENG_WPL_DATA_PAR_ERR_MASK}, - {"C2H_ERR_STAT_RSVD_4", - C2H_ERR_STAT_RSVD_4_MASK}, - {"C2H_ERR_STAT_DESC_RSP_ERR", - C2H_ERR_STAT_DESC_RSP_ERR_MASK}, - {"C2H_ERR_STAT_QID_MISMATCH", - C2H_ERR_STAT_QID_MISMATCH_MASK}, - {"C2H_ERR_STAT_SH_CMPT_DSC_ERR", - C2H_ERR_STAT_SH_CMPT_DSC_ERR_MASK}, - {"C2H_ERR_STAT_LEN_MISMATCH", - C2H_ERR_STAT_LEN_MISMATCH_MASK}, - {"C2H_ERR_STAT_MTY_MISMATCH", - C2H_ERR_STAT_MTY_MISMATCH_MASK}, -}; - - -static struct regfield_info - c2h_err_mask_field_info[] = { - {"C2H_ERR_EN", - C2H_ERR_EN_MASK}, -}; - - -static struct regfield_info - c2h_fatal_err_stat_field_info[] = { - {"C2H_FATAL_ERR_STAT_RSVD_1", - C2H_FATAL_ERR_STAT_RSVD_1_MASK}, - {"C2H_FATAL_ERR_STAT_HDR_ECC_UNC_ERR", - C2H_FATAL_ERR_STAT_HDR_ECC_UNC_ERR_MASK}, - {"C2H_FATAL_ERR_STAT_AVL_RING_FIFO_RAM_RDBE", - C2H_FATAL_ERR_STAT_AVL_RING_FIFO_RAM_RDBE_MASK}, - {"C2H_FATAL_ERR_STAT_WPL_DATA_PAR_ERR", - C2H_FATAL_ERR_STAT_WPL_DATA_PAR_ERR_MASK}, - {"C2H_FATAL_ERR_STAT_PLD_FIFO_RAM_RDBE", - C2H_FATAL_ERR_STAT_PLD_FIFO_RAM_RDBE_MASK}, - {"C2H_FATAL_ERR_STAT_QID_FIFO_RAM_RDBE", - C2H_FATAL_ERR_STAT_QID_FIFO_RAM_RDBE_MASK}, - {"C2H_FATAL_ERR_STAT_CMPT_FIFO_RAM_RDBE", - C2H_FATAL_ERR_STAT_CMPT_FIFO_RAM_RDBE_MASK}, - {"C2H_FATAL_ERR_STAT_WRB_COAL_DATA_RAM_RDBE", - C2H_FATAL_ERR_STAT_WRB_COAL_DATA_RAM_RDBE_MASK}, - {"C2H_FATAL_ERR_STAT_RESERVED2", - C2H_FATAL_ERR_STAT_RESERVED2_MASK}, - {"C2H_FATAL_ERR_STAT_INT_CTXT_RAM_RDBE", - C2H_FATAL_ERR_STAT_INT_CTXT_RAM_RDBE_MASK}, - {"C2H_FATAL_ERR_STAT_DESC_REQ_FIFO_RAM_RDBE", - C2H_FATAL_ERR_STAT_DESC_REQ_FIFO_RAM_RDBE_MASK}, - {"C2H_FATAL_ERR_STAT_PFCH_CTXT_RAM_RDBE", - C2H_FATAL_ERR_STAT_PFCH_CTXT_RAM_RDBE_MASK}, - {"C2H_FATAL_ERR_STAT_WRB_CTXT_RAM_RDBE", - C2H_FATAL_ERR_STAT_WRB_CTXT_RAM_RDBE_MASK}, - {"C2H_FATAL_ERR_STAT_PFCH_LL_RAM_RDBE", - C2H_FATAL_ERR_STAT_PFCH_LL_RAM_RDBE_MASK}, - {"C2H_FATAL_ERR_STAT_TIMER_FIFO_RAM_RDBE", - C2H_FATAL_ERR_STAT_TIMER_FIFO_RAM_RDBE_MASK}, - {"C2H_FATAL_ERR_STAT_QID_MISMATCH", - C2H_FATAL_ERR_STAT_QID_MISMATCH_MASK}, - {"C2H_FATAL_ERR_STAT_RESERVED1", - C2H_FATAL_ERR_STAT_RESERVED1_MASK}, - {"C2H_FATAL_ERR_STAT_LEN_MISMATCH", - C2H_FATAL_ERR_STAT_LEN_MISMATCH_MASK}, - {"C2H_FATAL_ERR_STAT_MTY_MISMATCH", - C2H_FATAL_ERR_STAT_MTY_MISMATCH_MASK}, -}; - - -static struct regfield_info - c2h_fatal_err_mask_field_info[] = { - {"C2H_FATAL_ERR_C2HEN", - C2H_FATAL_ERR_C2HEN_MASK}, -}; - - -static struct regfield_info - c2h_fatal_err_enable_field_info[] = { - {"C2H_FATAL_ERR_ENABLE_RSVD_1", - C2H_FATAL_ERR_ENABLE_RSVD_1_MASK}, - {"C2H_FATAL_ERR_ENABLE_WPL_PAR_INV", - C2H_FATAL_ERR_ENABLE_WPL_PAR_INV_MASK}, - {"C2H_FATAL_ERR_ENABLE_WRQ_DIS", - C2H_FATAL_ERR_ENABLE_WRQ_DIS_MASK}, -}; - - -static struct regfield_info - glbl_err_int_field_info[] = { - {"GLBL_ERR_INT_RSVD_1", - GLBL_ERR_INT_RSVD_1_MASK}, - {"GLBL_ERR_INT_HOST_ID", - GLBL_ERR_INT_HOST_ID_MASK}, - {"GLBL_ERR_INT_DIS_INTR_ON_VF", - GLBL_ERR_INT_DIS_INTR_ON_VF_MASK}, - {"GLBL_ERR_INT_ARM", - GLBL_ERR_INT_ARM_MASK}, - {"GLBL_ERR_INT_EN_COAL", - GLBL_ERR_INT_EN_COAL_MASK}, - {"GLBL_ERR_INT_VEC", - GLBL_ERR_INT_VEC_MASK}, - {"GLBL_ERR_INT_FUNC", - GLBL_ERR_INT_FUNC_MASK}, -}; - - -static struct regfield_info - c2h_pfch_cfg_field_info[] = { - {"C2H_PFCH_CFG_EVTFL_TH", - C2H_PFCH_CFG_EVTFL_TH_MASK}, - {"C2H_PFCH_CFG_FL_TH", - C2H_PFCH_CFG_FL_TH_MASK}, -}; - - -static struct regfield_info - c2h_pfch_cfg_1_field_info[] = { - {"C2H_PFCH_CFG_1_EVT_QCNT_TH", - C2H_PFCH_CFG_1_EVT_QCNT_TH_MASK}, - {"C2H_PFCH_CFG_1_QCNT", - C2H_PFCH_CFG_1_QCNT_MASK}, -}; - - -static struct regfield_info - c2h_pfch_cfg_2_field_info[] = { - {"C2H_PFCH_CFG_2_FENCE", - C2H_PFCH_CFG_2_FENCE_MASK}, - {"C2H_PFCH_CFG_2_RSVD", - C2H_PFCH_CFG_2_RSVD_MASK}, - {"C2H_PFCH_CFG_2_VAR_DESC_NO_DROP", - C2H_PFCH_CFG_2_VAR_DESC_NO_DROP_MASK}, - {"C2H_PFCH_CFG_2_LL_SZ_TH", - C2H_PFCH_CFG_2_LL_SZ_TH_MASK}, - {"C2H_PFCH_CFG_2_VAR_DESC_NUM", - C2H_PFCH_CFG_2_VAR_DESC_NUM_MASK}, - {"C2H_PFCH_CFG_2_NUM", - C2H_PFCH_CFG_2_NUM_MASK}, -}; - - -static struct regfield_info - c2h_int_timer_tick_field_info[] = { - {"C2H_INT_TIMER_TICK", - C2H_INT_TIMER_TICK_MASK}, -}; - - -static struct regfield_info - c2h_stat_desc_rsp_drop_accepted_field_info[] = { - {"C2H_STAT_DESC_RSP_DROP_ACCEPTED_D", - C2H_STAT_DESC_RSP_DROP_ACCEPTED_D_MASK}, -}; - - -static struct regfield_info - c2h_stat_desc_rsp_err_accepted_field_info[] = { - {"C2H_STAT_DESC_RSP_ERR_ACCEPTED_D", - C2H_STAT_DESC_RSP_ERR_ACCEPTED_D_MASK}, -}; - - -static struct regfield_info - c2h_stat_desc_req_field_info[] = { - {"C2H_STAT_DESC_REQ", - C2H_STAT_DESC_REQ_MASK}, -}; - - -static struct regfield_info - c2h_stat_dbg_dma_eng_0_field_info[] = { - {"C2H_STAT_DMA_ENG_0_S_AXIS_C2H_TVALID", - C2H_STAT_DMA_ENG_0_S_AXIS_C2H_TVALID_MASK}, - {"C2H_STAT_DMA_ENG_0_S_AXIS_C2H_TREADY", - C2H_STAT_DMA_ENG_0_S_AXIS_C2H_TREADY_MASK}, - {"C2H_STAT_DMA_ENG_0_S_AXIS_WRB_TVALID", - C2H_STAT_DMA_ENG_0_S_AXIS_WRB_TVALID_MASK}, - {"C2H_STAT_DMA_ENG_0_S_AXIS_WRB_TREADY", - C2H_STAT_DMA_ENG_0_S_AXIS_WRB_TREADY_MASK}, - {"C2H_STAT_DMA_ENG_0_PLD_FIFO_IN_RDY", - C2H_STAT_DMA_ENG_0_PLD_FIFO_IN_RDY_MASK}, - {"C2H_STAT_DMA_ENG_0_QID_FIFO_IN_RDY", - C2H_STAT_DMA_ENG_0_QID_FIFO_IN_RDY_MASK}, - {"C2H_STAT_DMA_ENG_0_ARB_FIFO_OUT_VLD", - C2H_STAT_DMA_ENG_0_ARB_FIFO_OUT_VLD_MASK}, - {"C2H_STAT_DMA_ENG_0_ARB_FIFO_OUT_QID", - C2H_STAT_DMA_ENG_0_ARB_FIFO_OUT_QID_MASK}, - {"C2H_STAT_DMA_ENG_0_WRB_FIFO_IN_RDY", - C2H_STAT_DMA_ENG_0_WRB_FIFO_IN_RDY_MASK}, - {"C2H_STAT_DMA_ENG_0_WRB_FIFO_OUT_CNT", - C2H_STAT_DMA_ENG_0_WRB_FIFO_OUT_CNT_MASK}, - {"C2H_STAT_DMA_ENG_0_WRB_SM_CS", - C2H_STAT_DMA_ENG_0_WRB_SM_CS_MASK}, - {"C2H_STAT_DMA_ENG_0_MAIN_SM_CS", - C2H_STAT_DMA_ENG_0_MAIN_SM_CS_MASK}, -}; - - -static struct regfield_info - c2h_stat_dbg_dma_eng_1_field_info[] = { - {"C2H_STAT_DMA_ENG_1_RSVD_1", - C2H_STAT_DMA_ENG_1_RSVD_1_MASK}, - {"C2H_STAT_DMA_ENG_1_QID_FIFO_OUT_CNT", - C2H_STAT_DMA_ENG_1_QID_FIFO_OUT_CNT_MASK}, - {"C2H_STAT_DMA_ENG_1_PLD_FIFO_OUT_CNT", - C2H_STAT_DMA_ENG_1_PLD_FIFO_OUT_CNT_MASK}, - {"C2H_STAT_DMA_ENG_1_PLD_ST_FIFO_CNT", - C2H_STAT_DMA_ENG_1_PLD_ST_FIFO_CNT_MASK}, -}; - - -static struct regfield_info - c2h_stat_dbg_dma_eng_2_field_info[] = { - {"C2H_STAT_DMA_ENG_2_RSVD_1", - C2H_STAT_DMA_ENG_2_RSVD_1_MASK}, - {"C2H_STAT_DMA_ENG_2_QID_FIFO_OUT_CNT", - C2H_STAT_DMA_ENG_2_QID_FIFO_OUT_CNT_MASK}, - {"C2H_STAT_DMA_ENG_2_PLD_FIFO_OUT_CNT", - C2H_STAT_DMA_ENG_2_PLD_FIFO_OUT_CNT_MASK}, - {"C2H_STAT_DMA_ENG_2_PLD_ST_FIFO_CNT", - C2H_STAT_DMA_ENG_2_PLD_ST_FIFO_CNT_MASK}, -}; - - -static struct regfield_info - c2h_stat_dbg_dma_eng_3_field_info[] = { - {"C2H_STAT_DMA_ENG_3_RSVD_1", - C2H_STAT_DMA_ENG_3_RSVD_1_MASK}, - {"C2H_STAT_DMA_ENG_3_WRQ_FIFO_OUT_CNT", - C2H_STAT_DMA_ENG_3_WRQ_FIFO_OUT_CNT_MASK}, - {"C2H_STAT_DMA_ENG_3_QID_FIFO_OUT_VLD", - C2H_STAT_DMA_ENG_3_QID_FIFO_OUT_VLD_MASK}, - {"C2H_STAT_DMA_ENG_3_PLD_FIFO_OUT_VLD", - C2H_STAT_DMA_ENG_3_PLD_FIFO_OUT_VLD_MASK}, - {"C2H_STAT_DMA_ENG_3_PLD_ST_FIFO_OUT_VLD", - C2H_STAT_DMA_ENG_3_PLD_ST_FIFO_OUT_VLD_MASK}, - {"C2H_STAT_DMA_ENG_3_PLD_ST_FIFO_OUT_DATA_EOP", - C2H_STAT_DMA_ENG_3_PLD_ST_FIFO_OUT_DATA_EOP_MASK}, - {"C2H_STAT_DMA_ENG_3_PLD_ST_FIFO_OUT_DATA_AVL_IDX_ENABLE", - C2H_STAT_DMA_ENG_3_PLD_ST_FIFO_OUT_DATA_AVL_IDX_ENABLE_MASK}, - {"C2H_STAT_DMA_ENG_3_PLD_ST_FIFO_OUT_DATA_DROP", - C2H_STAT_DMA_ENG_3_PLD_ST_FIFO_OUT_DATA_DROP_MASK}, - {"C2H_STAT_DMA_ENG_3_PLD_ST_FIFO_OUT_DATA_ERR", - C2H_STAT_DMA_ENG_3_PLD_ST_FIFO_OUT_DATA_ERR_MASK}, - {"C2H_STAT_DMA_ENG_3_DESC_CNT_FIFO_IN_RDY", - C2H_STAT_DMA_ENG_3_DESC_CNT_FIFO_IN_RDY_MASK}, - {"C2H_STAT_DMA_ENG_3_DESC_RSP_FIFO_IN_RDY", - C2H_STAT_DMA_ENG_3_DESC_RSP_FIFO_IN_RDY_MASK}, - {"C2H_STAT_DMA_ENG_3_PLD_PKT_ID_LARGER_0", - C2H_STAT_DMA_ENG_3_PLD_PKT_ID_LARGER_0_MASK}, - {"C2H_STAT_DMA_ENG_3_WRQ_VLD", - C2H_STAT_DMA_ENG_3_WRQ_VLD_MASK}, - {"C2H_STAT_DMA_ENG_3_WRQ_RDY", - C2H_STAT_DMA_ENG_3_WRQ_RDY_MASK}, - {"C2H_STAT_DMA_ENG_3_WRQ_FIFO_OUT_RDY", - C2H_STAT_DMA_ENG_3_WRQ_FIFO_OUT_RDY_MASK}, - {"C2H_STAT_DMA_ENG_3_WRQ_PACKET_OUT_DATA_DROP", - C2H_STAT_DMA_ENG_3_WRQ_PACKET_OUT_DATA_DROP_MASK}, - {"C2H_STAT_DMA_ENG_3_WRQ_PACKET_OUT_DATA_ERR", - C2H_STAT_DMA_ENG_3_WRQ_PACKET_OUT_DATA_ERR_MASK}, - {"C2H_STAT_DMA_ENG_3_WRQ_PACKET_OUT_DATA_MARKER", - C2H_STAT_DMA_ENG_3_WRQ_PACKET_OUT_DATA_MARKER_MASK}, - {"C2H_STAT_DMA_ENG_3_WRQ_PACKET_PRE_EOR", - C2H_STAT_DMA_ENG_3_WRQ_PACKET_PRE_EOR_MASK}, - {"C2H_STAT_DMA_ENG_3_WCP_FIFO_IN_RDY", - C2H_STAT_DMA_ENG_3_WCP_FIFO_IN_RDY_MASK}, - {"C2H_STAT_DMA_ENG_3_PLD_ST_FIFO_IN_RDY", - C2H_STAT_DMA_ENG_3_PLD_ST_FIFO_IN_RDY_MASK}, -}; - - -static struct regfield_info - c2h_dbg_pfch_err_ctxt_field_info[] = { - {"C2H_PFCH_ERR_CTXT_RSVD_1", - C2H_PFCH_ERR_CTXT_RSVD_1_MASK}, - {"C2H_PFCH_ERR_CTXT_ERR_STAT", - C2H_PFCH_ERR_CTXT_ERR_STAT_MASK}, - {"C2H_PFCH_ERR_CTXT_CMD_WR", - C2H_PFCH_ERR_CTXT_CMD_WR_MASK}, - {"C2H_PFCH_ERR_CTXT_QID", - C2H_PFCH_ERR_CTXT_QID_MASK}, - {"C2H_PFCH_ERR_CTXT_DONE", - C2H_PFCH_ERR_CTXT_DONE_MASK}, -}; - - -static struct regfield_info - c2h_first_err_qid_field_info[] = { - {"C2H_FIRST_ERR_QID_RSVD_1", - C2H_FIRST_ERR_QID_RSVD_1_MASK}, - {"C2H_FIRST_ERR_QID_ERR_TYPE", - C2H_FIRST_ERR_QID_ERR_TYPE_MASK}, - {"C2H_FIRST_ERR_QID_RSVD", - C2H_FIRST_ERR_QID_RSVD_MASK}, - {"C2H_FIRST_ERR_QID_QID", - C2H_FIRST_ERR_QID_QID_MASK}, -}; - - -static struct regfield_info - stat_num_wrb_in_field_info[] = { - {"STAT_NUM_WRB_IN_RSVD_1", - STAT_NUM_WRB_IN_RSVD_1_MASK}, - {"STAT_NUM_WRB_IN_WRB_CNT", - STAT_NUM_WRB_IN_WRB_CNT_MASK}, -}; - - -static struct regfield_info - stat_num_wrb_out_field_info[] = { - {"STAT_NUM_WRB_OUT_RSVD_1", - STAT_NUM_WRB_OUT_RSVD_1_MASK}, - {"STAT_NUM_WRB_OUT_WRB_CNT", - STAT_NUM_WRB_OUT_WRB_CNT_MASK}, -}; - - -static struct regfield_info - stat_num_wrb_drp_field_info[] = { - {"STAT_NUM_WRB_DRP_RSVD_1", - STAT_NUM_WRB_DRP_RSVD_1_MASK}, - {"STAT_NUM_WRB_DRP_WRB_CNT", - STAT_NUM_WRB_DRP_WRB_CNT_MASK}, -}; - - -static struct regfield_info - stat_num_stat_desc_out_field_info[] = { - {"STAT_NUM_STAT_DESC_OUT_RSVD_1", - STAT_NUM_STAT_DESC_OUT_RSVD_1_MASK}, - {"STAT_NUM_STAT_DESC_OUT_CNT", - STAT_NUM_STAT_DESC_OUT_CNT_MASK}, -}; - - -static struct regfield_info - stat_num_dsc_crdt_sent_field_info[] = { - {"STAT_NUM_DSC_CRDT_SENT_RSVD_1", - STAT_NUM_DSC_CRDT_SENT_RSVD_1_MASK}, - {"STAT_NUM_DSC_CRDT_SENT_CNT", - STAT_NUM_DSC_CRDT_SENT_CNT_MASK}, -}; - - -static struct regfield_info - stat_num_fch_dsc_rcvd_field_info[] = { - {"STAT_NUM_FCH_DSC_RCVD_RSVD_1", - STAT_NUM_FCH_DSC_RCVD_RSVD_1_MASK}, - {"STAT_NUM_FCH_DSC_RCVD_DSC_CNT", - STAT_NUM_FCH_DSC_RCVD_DSC_CNT_MASK}, -}; - - -static struct regfield_info - stat_num_byp_dsc_rcvd_field_info[] = { - {"STAT_NUM_BYP_DSC_RCVD_RSVD_1", - STAT_NUM_BYP_DSC_RCVD_RSVD_1_MASK}, - {"STAT_NUM_BYP_DSC_RCVD_DSC_CNT", - STAT_NUM_BYP_DSC_RCVD_DSC_CNT_MASK}, -}; - - -static struct regfield_info - c2h_wrb_coal_cfg_field_info[] = { - {"C2H_WRB_COAL_CFG_MAX_BUF_SZ", - C2H_WRB_COAL_CFG_MAX_BUF_SZ_MASK}, - {"C2H_WRB_COAL_CFG_TICK_VAL", - C2H_WRB_COAL_CFG_TICK_VAL_MASK}, - {"C2H_WRB_COAL_CFG_TICK_CNT", - C2H_WRB_COAL_CFG_TICK_CNT_MASK}, - {"C2H_WRB_COAL_CFG_SET_GLB_FLUSH", - C2H_WRB_COAL_CFG_SET_GLB_FLUSH_MASK}, - {"C2H_WRB_COAL_CFG_DONE_GLB_FLUSH", - C2H_WRB_COAL_CFG_DONE_GLB_FLUSH_MASK}, -}; - - -static struct regfield_info - c2h_intr_h2c_req_field_info[] = { - {"C2H_INTR_H2C_REQ_RSVD_1", - C2H_INTR_H2C_REQ_RSVD_1_MASK}, - {"C2H_INTR_H2C_REQ_CNT", - C2H_INTR_H2C_REQ_CNT_MASK}, -}; - - -static struct regfield_info - c2h_intr_c2h_mm_req_field_info[] = { - {"C2H_INTR_C2H_MM_REQ_RSVD_1", - C2H_INTR_C2H_MM_REQ_RSVD_1_MASK}, - {"C2H_INTR_C2H_MM_REQ_CNT", - C2H_INTR_C2H_MM_REQ_CNT_MASK}, -}; - - -static struct regfield_info - c2h_intr_err_int_req_field_info[] = { - {"C2H_INTR_ERR_INT_REQ_RSVD_1", - C2H_INTR_ERR_INT_REQ_RSVD_1_MASK}, - {"C2H_INTR_ERR_INT_REQ_CNT", - C2H_INTR_ERR_INT_REQ_CNT_MASK}, -}; - - -static struct regfield_info - c2h_intr_c2h_st_req_field_info[] = { - {"C2H_INTR_C2H_ST_REQ_RSVD_1", - C2H_INTR_C2H_ST_REQ_RSVD_1_MASK}, - {"C2H_INTR_C2H_ST_REQ_CNT", - C2H_INTR_C2H_ST_REQ_CNT_MASK}, -}; - - -static struct regfield_info - c2h_intr_h2c_err_c2h_mm_msix_ack_field_info[] = { - {"C2H_INTR_H2C_ERR_C2H_MM_MSIX_ACK_RSVD_1", - C2H_INTR_H2C_ERR_C2H_MM_MSIX_ACK_RSVD_1_MASK}, - {"C2H_INTR_H2C_ERR_C2H_MM_MSIX_ACK_CNT", - C2H_INTR_H2C_ERR_C2H_MM_MSIX_ACK_CNT_MASK}, -}; - - -static struct regfield_info - c2h_intr_h2c_err_c2h_mm_msix_fail_field_info[] = { - {"C2H_INTR_H2C_ERR_C2H_MM_MSIX_FAIL_RSVD_1", - C2H_INTR_H2C_ERR_C2H_MM_MSIX_FAIL_RSVD_1_MASK}, - {"C2H_INTR_H2C_ERR_C2H_MM_MSIX_FAIL_CNT", - C2H_INTR_H2C_ERR_C2H_MM_MSIX_FAIL_CNT_MASK}, -}; - - -static struct regfield_info - c2h_intr_h2c_err_c2h_mm_msix_no_msix_field_info[] = { - {"C2H_INTR_H2C_ERR_C2H_MM_MSIX_NO_MSIX_RSVD_1", - C2H_INTR_H2C_ERR_C2H_MM_MSIX_NO_MSIX_RSVD_1_MASK}, - {"C2H_INTR_H2C_ERR_C2H_MM_MSIX_NO_MSIX_CNT", - C2H_INTR_H2C_ERR_C2H_MM_MSIX_NO_MSIX_CNT_MASK}, -}; - - -static struct regfield_info - c2h_intr_h2c_err_c2h_mm_ctxt_inval_field_info[] = { - {"C2H_INTR_H2C_ERR_C2H_MM_CTXT_INVAL_RSVD_1", - C2H_INTR_H2C_ERR_C2H_MM_CTXT_INVAL_RSVD_1_MASK}, - {"C2H_INTR_H2C_ERR_C2H_MM_CTXT_INVAL_CNT", - C2H_INTR_H2C_ERR_C2H_MM_CTXT_INVAL_CNT_MASK}, -}; - - -static struct regfield_info - c2h_intr_c2h_st_msix_ack_field_info[] = { - {"C2H_INTR_C2H_ST_MSIX_ACK_RSVD_1", - C2H_INTR_C2H_ST_MSIX_ACK_RSVD_1_MASK}, - {"C2H_INTR_C2H_ST_MSIX_ACK_CNT", - C2H_INTR_C2H_ST_MSIX_ACK_CNT_MASK}, -}; - - -static struct regfield_info - c2h_intr_c2h_st_msix_fail_field_info[] = { - {"C2H_INTR_C2H_ST_MSIX_FAIL_RSVD_1", - C2H_INTR_C2H_ST_MSIX_FAIL_RSVD_1_MASK}, - {"C2H_INTR_C2H_ST_MSIX_FAIL_CNT", - C2H_INTR_C2H_ST_MSIX_FAIL_CNT_MASK}, -}; - - -static struct regfield_info - c2h_intr_c2h_st_no_msix_field_info[] = { - {"C2H_INTR_C2H_ST_NO_MSIX_RSVD_1", - C2H_INTR_C2H_ST_NO_MSIX_RSVD_1_MASK}, - {"C2H_INTR_C2H_ST_NO_MSIX_CNT", - C2H_INTR_C2H_ST_NO_MSIX_CNT_MASK}, -}; - - -static struct regfield_info - c2h_intr_c2h_st_ctxt_inval_field_info[] = { - {"C2H_INTR_C2H_ST_CTXT_INVAL_RSVD_1", - C2H_INTR_C2H_ST_CTXT_INVAL_RSVD_1_MASK}, - {"C2H_INTR_C2H_ST_CTXT_INVAL_CNT", - C2H_INTR_C2H_ST_CTXT_INVAL_CNT_MASK}, -}; - - -static struct regfield_info - c2h_stat_wr_cmp_field_info[] = { - {"C2H_STAT_WR_CMP_RSVD_1", - C2H_STAT_WR_CMP_RSVD_1_MASK}, - {"C2H_STAT_WR_CMP_CNT", - C2H_STAT_WR_CMP_CNT_MASK}, -}; - - -static struct regfield_info - c2h_stat_dbg_dma_eng_4_field_info[] = { - {"C2H_STAT_DMA_ENG_4_RSVD_1", - C2H_STAT_DMA_ENG_4_RSVD_1_MASK}, - {"C2H_STAT_DMA_ENG_4_WRQ_FIFO_OUT_CNT", - C2H_STAT_DMA_ENG_4_WRQ_FIFO_OUT_CNT_MASK}, - {"C2H_STAT_DMA_ENG_4_QID_FIFO_OUT_VLD", - C2H_STAT_DMA_ENG_4_QID_FIFO_OUT_VLD_MASK}, - {"C2H_STAT_DMA_ENG_4_PLD_FIFO_OUT_VLD", - C2H_STAT_DMA_ENG_4_PLD_FIFO_OUT_VLD_MASK}, - {"C2H_STAT_DMA_ENG_4_PLD_ST_FIFO_OUT_VLD", - C2H_STAT_DMA_ENG_4_PLD_ST_FIFO_OUT_VLD_MASK}, - {"C2H_STAT_DMA_ENG_4_PLD_ST_FIFO_OUT_DATA_EOP", - C2H_STAT_DMA_ENG_4_PLD_ST_FIFO_OUT_DATA_EOP_MASK}, - {"C2H_STAT_DMA_ENG_4_PLD_ST_FIFO_OUT_DATA_AVL_IDX_ENABLE", - C2H_STAT_DMA_ENG_4_PLD_ST_FIFO_OUT_DATA_AVL_IDX_ENABLE_MASK}, - {"C2H_STAT_DMA_ENG_4_PLD_ST_FIFO_OUT_DATA_DROP", - C2H_STAT_DMA_ENG_4_PLD_ST_FIFO_OUT_DATA_DROP_MASK}, - {"C2H_STAT_DMA_ENG_4_PLD_ST_FIFO_OUT_DATA_ERR", - C2H_STAT_DMA_ENG_4_PLD_ST_FIFO_OUT_DATA_ERR_MASK}, - {"C2H_STAT_DMA_ENG_4_DESC_CNT_FIFO_IN_RDY", - C2H_STAT_DMA_ENG_4_DESC_CNT_FIFO_IN_RDY_MASK}, - {"C2H_STAT_DMA_ENG_4_DESC_RSP_FIFO_IN_RDY", - C2H_STAT_DMA_ENG_4_DESC_RSP_FIFO_IN_RDY_MASK}, - {"C2H_STAT_DMA_ENG_4_PLD_PKT_ID_LARGER_0", - C2H_STAT_DMA_ENG_4_PLD_PKT_ID_LARGER_0_MASK}, - {"C2H_STAT_DMA_ENG_4_WRQ_VLD", - C2H_STAT_DMA_ENG_4_WRQ_VLD_MASK}, - {"C2H_STAT_DMA_ENG_4_WRQ_RDY", - C2H_STAT_DMA_ENG_4_WRQ_RDY_MASK}, - {"C2H_STAT_DMA_ENG_4_WRQ_FIFO_OUT_RDY", - C2H_STAT_DMA_ENG_4_WRQ_FIFO_OUT_RDY_MASK}, - {"C2H_STAT_DMA_ENG_4_WRQ_PACKET_OUT_DATA_DROP", - C2H_STAT_DMA_ENG_4_WRQ_PACKET_OUT_DATA_DROP_MASK}, - {"C2H_STAT_DMA_ENG_4_WRQ_PACKET_OUT_DATA_ERR", - C2H_STAT_DMA_ENG_4_WRQ_PACKET_OUT_DATA_ERR_MASK}, - {"C2H_STAT_DMA_ENG_4_WRQ_PACKET_OUT_DATA_MARKER", - C2H_STAT_DMA_ENG_4_WRQ_PACKET_OUT_DATA_MARKER_MASK}, - {"C2H_STAT_DMA_ENG_4_WRQ_PACKET_PRE_EOR", - C2H_STAT_DMA_ENG_4_WRQ_PACKET_PRE_EOR_MASK}, - {"C2H_STAT_DMA_ENG_4_WCP_FIFO_IN_RDY", - C2H_STAT_DMA_ENG_4_WCP_FIFO_IN_RDY_MASK}, - {"C2H_STAT_DMA_ENG_4_PLD_ST_FIFO_IN_RDY", - C2H_STAT_DMA_ENG_4_PLD_ST_FIFO_IN_RDY_MASK}, -}; - - -static struct regfield_info - c2h_stat_dbg_dma_eng_5_field_info[] = { - {"C2H_STAT_DMA_ENG_5_RSVD_1", - C2H_STAT_DMA_ENG_5_RSVD_1_MASK}, - {"C2H_STAT_DMA_ENG_5_WRB_SM_VIRT_CH", - C2H_STAT_DMA_ENG_5_WRB_SM_VIRT_CH_MASK}, - {"C2H_STAT_DMA_ENG_5_WRB_FIFO_IN_REQ", - C2H_STAT_DMA_ENG_5_WRB_FIFO_IN_REQ_MASK}, - {"C2H_STAT_DMA_ENG_5_ARB_FIFO_OUT_CNT", - C2H_STAT_DMA_ENG_5_ARB_FIFO_OUT_CNT_MASK}, - {"C2H_STAT_DMA_ENG_5_ARB_FIFO_OUT_DATA_LEN", - C2H_STAT_DMA_ENG_5_ARB_FIFO_OUT_DATA_LEN_MASK}, - {"C2H_STAT_DMA_ENG_5_ARB_FIFO_OUT_DATA_VIRT_CH", - C2H_STAT_DMA_ENG_5_ARB_FIFO_OUT_DATA_VIRT_CH_MASK}, - {"C2H_STAT_DMA_ENG_5_ARB_FIFO_OUT_DATA_VAR_DESC", - C2H_STAT_DMA_ENG_5_ARB_FIFO_OUT_DATA_VAR_DESC_MASK}, - {"C2H_STAT_DMA_ENG_5_ARB_FIFO_OUT_DATA_DROP_REQ", - C2H_STAT_DMA_ENG_5_ARB_FIFO_OUT_DATA_DROP_REQ_MASK}, - {"C2H_STAT_DMA_ENG_5_ARB_FIFO_OUT_DATA_NUM_BUF_OV", - C2H_STAT_DMA_ENG_5_ARB_FIFO_OUT_DATA_NUM_BUF_OV_MASK}, - {"C2H_STAT_DMA_ENG_5_ARB_FIFO_OUT_DATA_MARKER", - C2H_STAT_DMA_ENG_5_ARB_FIFO_OUT_DATA_MARKER_MASK}, - {"C2H_STAT_DMA_ENG_5_ARB_FIFO_OUT_DATA_HAS_CMPT", - C2H_STAT_DMA_ENG_5_ARB_FIFO_OUT_DATA_HAS_CMPT_MASK}, -}; - - -static struct regfield_info - c2h_dbg_pfch_qid_field_info[] = { - {"C2H_PFCH_QID_RSVD_1", - C2H_PFCH_QID_RSVD_1_MASK}, - {"C2H_PFCH_QID_ERR_CTXT", - C2H_PFCH_QID_ERR_CTXT_MASK}, - {"C2H_PFCH_QID_TARGET", - C2H_PFCH_QID_TARGET_MASK}, - {"C2H_PFCH_QID_QID_OR_TAG", - C2H_PFCH_QID_QID_OR_TAG_MASK}, -}; - - -static struct regfield_info - c2h_dbg_pfch_field_info[] = { - {"C2H_PFCH_DATA", - C2H_PFCH_DATA_MASK}, -}; - - -static struct regfield_info - c2h_int_dbg_field_info[] = { - {"C2H_INT_RSVD_1", - C2H_INT_RSVD_1_MASK}, - {"C2H_INT_INT_COAL_SM", - C2H_INT_INT_COAL_SM_MASK}, - {"C2H_INT_INT_SM", - C2H_INT_INT_SM_MASK}, -}; - - -static struct regfield_info - c2h_stat_imm_accepted_field_info[] = { - {"C2H_STAT_IMM_ACCEPTED_RSVD_1", - C2H_STAT_IMM_ACCEPTED_RSVD_1_MASK}, - {"C2H_STAT_IMM_ACCEPTED_CNT", - C2H_STAT_IMM_ACCEPTED_CNT_MASK}, -}; - - -static struct regfield_info - c2h_stat_marker_accepted_field_info[] = { - {"C2H_STAT_MARKER_ACCEPTED_RSVD_1", - C2H_STAT_MARKER_ACCEPTED_RSVD_1_MASK}, - {"C2H_STAT_MARKER_ACCEPTED_CNT", - C2H_STAT_MARKER_ACCEPTED_CNT_MASK}, -}; - - -static struct regfield_info - c2h_stat_disable_cmp_accepted_field_info[] = { - {"C2H_STAT_DISABLE_CMP_ACCEPTED_RSVD_1", - C2H_STAT_DISABLE_CMP_ACCEPTED_RSVD_1_MASK}, - {"C2H_STAT_DISABLE_CMP_ACCEPTED_CNT", - C2H_STAT_DISABLE_CMP_ACCEPTED_CNT_MASK}, -}; - - -static struct regfield_info - c2h_pld_fifo_crdt_cnt_field_info[] = { - {"C2H_PLD_FIFO_CRDT_CNT_RSVD_1", - C2H_PLD_FIFO_CRDT_CNT_RSVD_1_MASK}, - {"C2H_PLD_FIFO_CRDT_CNT_CNT", - C2H_PLD_FIFO_CRDT_CNT_CNT_MASK}, -}; - - -static struct regfield_info - c2h_intr_dyn_req_field_info[] = { - {"C2H_INTR_DYN_REQ_RSVD_1", - C2H_INTR_DYN_REQ_RSVD_1_MASK}, - {"C2H_INTR_DYN_REQ_CNT", - C2H_INTR_DYN_REQ_CNT_MASK}, -}; - - -static struct regfield_info - c2h_intr_dyn_misc_field_info[] = { - {"C2H_INTR_DYN_MISC_RSVD_1", - C2H_INTR_DYN_MISC_RSVD_1_MASK}, - {"C2H_INTR_DYN_MISC_CNT", - C2H_INTR_DYN_MISC_CNT_MASK}, -}; - - -static struct regfield_info - c2h_drop_len_mismatch_field_info[] = { - {"C2H_DROP_LEN_MISMATCH_RSVD_1", - C2H_DROP_LEN_MISMATCH_RSVD_1_MASK}, - {"C2H_DROP_LEN_MISMATCH_CNT", - C2H_DROP_LEN_MISMATCH_CNT_MASK}, -}; - - -static struct regfield_info - c2h_drop_desc_rsp_len_field_info[] = { - {"C2H_DROP_DESC_RSP_LEN_RSVD_1", - C2H_DROP_DESC_RSP_LEN_RSVD_1_MASK}, - {"C2H_DROP_DESC_RSP_LEN_CNT", - C2H_DROP_DESC_RSP_LEN_CNT_MASK}, -}; - - -static struct regfield_info - c2h_drop_qid_fifo_len_field_info[] = { - {"C2H_DROP_QID_FIFO_LEN_RSVD_1", - C2H_DROP_QID_FIFO_LEN_RSVD_1_MASK}, - {"C2H_DROP_QID_FIFO_LEN_CNT", - C2H_DROP_QID_FIFO_LEN_CNT_MASK}, -}; - - -static struct regfield_info - c2h_drop_pld_cnt_field_info[] = { - {"C2H_DROP_PLD_CNT_RSVD_1", - C2H_DROP_PLD_CNT_RSVD_1_MASK}, - {"C2H_DROP_PLD_CNT_CNT", - C2H_DROP_PLD_CNT_CNT_MASK}, -}; - - -static struct regfield_info - c2h_cmpt_format_0_field_info[] = { - {"C2H_CMPT_FORMAT_0_DESC_ERR_LOC", - C2H_CMPT_FORMAT_0_DESC_ERR_LOC_MASK}, - {"C2H_CMPT_FORMAT_0_COLOR_LOC", - C2H_CMPT_FORMAT_0_COLOR_LOC_MASK}, -}; - - -static struct regfield_info - c2h_cmpt_format_1_field_info[] = { - {"C2H_CMPT_FORMAT_1_DESC_ERR_LOC", - C2H_CMPT_FORMAT_1_DESC_ERR_LOC_MASK}, - {"C2H_CMPT_FORMAT_1_COLOR_LOC", - C2H_CMPT_FORMAT_1_COLOR_LOC_MASK}, -}; - - -static struct regfield_info - c2h_cmpt_format_2_field_info[] = { - {"C2H_CMPT_FORMAT_2_DESC_ERR_LOC", - C2H_CMPT_FORMAT_2_DESC_ERR_LOC_MASK}, - {"C2H_CMPT_FORMAT_2_COLOR_LOC", - C2H_CMPT_FORMAT_2_COLOR_LOC_MASK}, -}; - - -static struct regfield_info - c2h_cmpt_format_3_field_info[] = { - {"C2H_CMPT_FORMAT_3_DESC_ERR_LOC", - C2H_CMPT_FORMAT_3_DESC_ERR_LOC_MASK}, - {"C2H_CMPT_FORMAT_3_COLOR_LOC", - C2H_CMPT_FORMAT_3_COLOR_LOC_MASK}, -}; - - -static struct regfield_info - c2h_cmpt_format_4_field_info[] = { - {"C2H_CMPT_FORMAT_4_DESC_ERR_LOC", - C2H_CMPT_FORMAT_4_DESC_ERR_LOC_MASK}, - {"C2H_CMPT_FORMAT_4_COLOR_LOC", - C2H_CMPT_FORMAT_4_COLOR_LOC_MASK}, -}; - - -static struct regfield_info - c2h_cmpt_format_5_field_info[] = { - {"C2H_CMPT_FORMAT_5_DESC_ERR_LOC", - C2H_CMPT_FORMAT_5_DESC_ERR_LOC_MASK}, - {"C2H_CMPT_FORMAT_5_COLOR_LOC", - C2H_CMPT_FORMAT_5_COLOR_LOC_MASK}, -}; - - -static struct regfield_info - c2h_cmpt_format_6_field_info[] = { - {"C2H_CMPT_FORMAT_6_DESC_ERR_LOC", - C2H_CMPT_FORMAT_6_DESC_ERR_LOC_MASK}, - {"C2H_CMPT_FORMAT_6_COLOR_LOC", - C2H_CMPT_FORMAT_6_COLOR_LOC_MASK}, -}; - - -static struct regfield_info - c2h_pfch_cache_depth_field_info[] = { - {"C2H_PFCH_CACHE_DEPTH_MAX_STBUF", - C2H_PFCH_CACHE_DEPTH_MAX_STBUF_MASK}, - {"C2H_PFCH_CACHE_DEPTH", - C2H_PFCH_CACHE_DEPTH_MASK}, -}; - - -static struct regfield_info - c2h_wrb_coal_buf_depth_field_info[] = { - {"C2H_WRB_COAL_BUF_DEPTH_RSVD_1", - C2H_WRB_COAL_BUF_DEPTH_RSVD_1_MASK}, - {"C2H_WRB_COAL_BUF_DEPTH_BUFFER", - C2H_WRB_COAL_BUF_DEPTH_BUFFER_MASK}, -}; - - -static struct regfield_info - c2h_pfch_crdt_field_info[] = { - {"C2H_PFCH_CRDT_RSVD_1", - C2H_PFCH_CRDT_RSVD_1_MASK}, - {"C2H_PFCH_CRDT_RSVD_2", - C2H_PFCH_CRDT_RSVD_2_MASK}, -}; - - -static struct regfield_info - c2h_stat_has_cmpt_accepted_field_info[] = { - {"C2H_STAT_HAS_CMPT_ACCEPTED_RSVD_1", - C2H_STAT_HAS_CMPT_ACCEPTED_RSVD_1_MASK}, - {"C2H_STAT_HAS_CMPT_ACCEPTED_CNT", - C2H_STAT_HAS_CMPT_ACCEPTED_CNT_MASK}, -}; - - -static struct regfield_info - c2h_stat_has_pld_accepted_field_info[] = { - {"C2H_STAT_HAS_PLD_ACCEPTED_RSVD_1", - C2H_STAT_HAS_PLD_ACCEPTED_RSVD_1_MASK}, - {"C2H_STAT_HAS_PLD_ACCEPTED_CNT", - C2H_STAT_HAS_PLD_ACCEPTED_CNT_MASK}, -}; - - -static struct regfield_info - c2h_pld_pkt_id_field_info[] = { - {"C2H_PLD_PKT_ID_CMPT_WAIT", - C2H_PLD_PKT_ID_CMPT_WAIT_MASK}, - {"C2H_PLD_PKT_ID_DATA", - C2H_PLD_PKT_ID_DATA_MASK}, -}; - - -static struct regfield_info - c2h_pld_pkt_id_1_field_info[] = { - {"C2H_PLD_PKT_ID_1_CMPT_WAIT", - C2H_PLD_PKT_ID_1_CMPT_WAIT_MASK}, - {"C2H_PLD_PKT_ID_1_DATA", - C2H_PLD_PKT_ID_1_DATA_MASK}, -}; - - -static struct regfield_info - c2h_drop_pld_cnt_1_field_info[] = { - {"C2H_DROP_PLD_CNT_1_RSVD_1", - C2H_DROP_PLD_CNT_1_RSVD_1_MASK}, - {"C2H_DROP_PLD_CNT_1_CNT", - C2H_DROP_PLD_CNT_1_CNT_MASK}, -}; - - -static struct regfield_info - h2c_err_stat_field_info[] = { - {"H2C_ERR_STAT_RSVD_1", - H2C_ERR_STAT_RSVD_1_MASK}, - {"H2C_ERR_STAT_PAR_ERR", - H2C_ERR_STAT_PAR_ERR_MASK}, - {"H2C_ERR_STAT_SBE", - H2C_ERR_STAT_SBE_MASK}, - {"H2C_ERR_STAT_DBE", - H2C_ERR_STAT_DBE_MASK}, - {"H2C_ERR_STAT_NO_DMA_DS", - H2C_ERR_STAT_NO_DMA_DS_MASK}, - {"H2C_ERR_STAT_SDI_MRKR_REQ_MOP_ERR", - H2C_ERR_STAT_SDI_MRKR_REQ_MOP_ERR_MASK}, - {"H2C_ERR_STAT_ZERO_LEN_DS", - H2C_ERR_STAT_ZERO_LEN_DS_MASK}, -}; - - -static struct regfield_info - h2c_err_mask_field_info[] = { - {"H2C_ERR_EN", - H2C_ERR_EN_MASK}, -}; - - -static struct regfield_info - h2c_first_err_qid_field_info[] = { - {"H2C_FIRST_ERR_QID_RSVD_1", - H2C_FIRST_ERR_QID_RSVD_1_MASK}, - {"H2C_FIRST_ERR_QID_ERR_TYPE", - H2C_FIRST_ERR_QID_ERR_TYPE_MASK}, - {"H2C_FIRST_ERR_QID_RSVD_2", - H2C_FIRST_ERR_QID_RSVD_2_MASK}, - {"H2C_FIRST_ERR_QID_QID", - H2C_FIRST_ERR_QID_QID_MASK}, -}; - - -static struct regfield_info - h2c_dbg_reg0_field_info[] = { - {"H2C_REG0_NUM_DSC_RCVD", - H2C_REG0_NUM_DSC_RCVD_MASK}, - {"H2C_REG0_NUM_WRB_SENT", - H2C_REG0_NUM_WRB_SENT_MASK}, -}; - - -static struct regfield_info - h2c_dbg_reg1_field_info[] = { - {"H2C_REG1_NUM_REQ_SENT", - H2C_REG1_NUM_REQ_SENT_MASK}, - {"H2C_REG1_NUM_CMP_SENT", - H2C_REG1_NUM_CMP_SENT_MASK}, -}; - - -static struct regfield_info - h2c_dbg_reg2_field_info[] = { - {"H2C_REG2_RSVD_1", - H2C_REG2_RSVD_1_MASK}, - {"H2C_REG2_NUM_ERR_DSC_RCVD", - H2C_REG2_NUM_ERR_DSC_RCVD_MASK}, -}; - - -static struct regfield_info - h2c_dbg_reg3_field_info[] = { - {"H2C_REG3_RSVD_1", - H2C_REG3_RSVD_1_MASK}, - {"H2C_REG3_DSCO_FIFO_EMPTY", - H2C_REG3_DSCO_FIFO_EMPTY_MASK}, - {"H2C_REG3_DSCO_FIFO_FULL", - H2C_REG3_DSCO_FIFO_FULL_MASK}, - {"H2C_REG3_CUR_RC_STATE", - H2C_REG3_CUR_RC_STATE_MASK}, - {"H2C_REG3_RDREQ_LINES", - H2C_REG3_RDREQ_LINES_MASK}, - {"H2C_REG3_RDATA_LINES_AVAIL", - H2C_REG3_RDATA_LINES_AVAIL_MASK}, - {"H2C_REG3_PEND_FIFO_EMPTY", - H2C_REG3_PEND_FIFO_EMPTY_MASK}, - {"H2C_REG3_PEND_FIFO_FULL", - H2C_REG3_PEND_FIFO_FULL_MASK}, - {"H2C_REG3_CUR_RQ_STATE", - H2C_REG3_CUR_RQ_STATE_MASK}, - {"H2C_REG3_DSCI_FIFO_FULL", - H2C_REG3_DSCI_FIFO_FULL_MASK}, - {"H2C_REG3_DSCI_FIFO_EMPTY", - H2C_REG3_DSCI_FIFO_EMPTY_MASK}, -}; - - -static struct regfield_info - h2c_dbg_reg4_field_info[] = { - {"H2C_REG4_RDREQ_ADDR", - H2C_REG4_RDREQ_ADDR_MASK}, -}; - - -static struct regfield_info - h2c_fatal_err_en_field_info[] = { - {"H2C_FATAL_ERR_EN_RSVD_1", - H2C_FATAL_ERR_EN_RSVD_1_MASK}, - {"H2C_FATAL_ERR_EN_H2C", - H2C_FATAL_ERR_EN_H2C_MASK}, -}; - - -static struct regfield_info - h2c_req_throt_pcie_field_info[] = { - {"H2C_REQ_THROT_PCIE_EN_REQ", - H2C_REQ_THROT_PCIE_EN_REQ_MASK}, - {"H2C_REQ_THROT_PCIE", - H2C_REQ_THROT_PCIE_MASK}, - {"H2C_REQ_THROT_PCIE_EN_DATA", - H2C_REQ_THROT_PCIE_EN_DATA_MASK}, - {"H2C_REQ_THROT_PCIE_DATA_THRESH", - H2C_REQ_THROT_PCIE_DATA_THRESH_MASK}, -}; - - -static struct regfield_info - h2c_aln_dbg_reg0_field_info[] = { - {"H2C_ALN_REG0_NUM_PKT_SENT", - H2C_ALN_REG0_NUM_PKT_SENT_MASK}, -}; - - -static struct regfield_info - h2c_req_throt_aximm_field_info[] = { - {"H2C_REQ_THROT_AXIMM_EN_REQ", - H2C_REQ_THROT_AXIMM_EN_REQ_MASK}, - {"H2C_REQ_THROT_AXIMM", - H2C_REQ_THROT_AXIMM_MASK}, - {"H2C_REQ_THROT_AXIMM_EN_DATA", - H2C_REQ_THROT_AXIMM_EN_DATA_MASK}, - {"H2C_REQ_THROT_AXIMM_DATA_THRESH", - H2C_REQ_THROT_AXIMM_DATA_THRESH_MASK}, -}; - - -static struct regfield_info - c2h_mm_ctl_field_info[] = { - {"C2H_MM_CTL_RESERVED1", - C2H_MM_CTL_RESERVED1_MASK}, - {"C2H_MM_CTL_ERRC_EN", - C2H_MM_CTL_ERRC_EN_MASK}, - {"C2H_MM_CTL_RESERVED0", - C2H_MM_CTL_RESERVED0_MASK}, - {"C2H_MM_CTL_RUN", - C2H_MM_CTL_RUN_MASK}, -}; - - -static struct regfield_info - c2h_mm_status_field_info[] = { - {"C2H_MM_STATUS_RSVD_1", - C2H_MM_STATUS_RSVD_1_MASK}, - {"C2H_MM_STATUS_RUN", - C2H_MM_STATUS_RUN_MASK}, -}; - - -static struct regfield_info - c2h_mm_cmpl_desc_cnt_field_info[] = { - {"C2H_MM_CMPL_DESC_CNT_C2H_CO", - C2H_MM_CMPL_DESC_CNT_C2H_CO_MASK}, -}; - - -static struct regfield_info - c2h_mm_err_code_enable_mask_field_info[] = { - {"C2H_MM_ERR_CODE_ENABLE_RESERVED1", - C2H_MM_ERR_CODE_ENABLE_RESERVED1_MASK}, - {"C2H_MM_ERR_CODE_ENABLE_WR_UC_RAM", - C2H_MM_ERR_CODE_ENABLE_WR_UC_RAM_MASK}, - {"C2H_MM_ERR_CODE_ENABLE_WR_UR", - C2H_MM_ERR_CODE_ENABLE_WR_UR_MASK}, - {"C2H_MM_ERR_CODE_ENABLE_WR_FLR", - C2H_MM_ERR_CODE_ENABLE_WR_FLR_MASK}, - {"C2H_MM_ERR_CODE_ENABLE_RESERVED0", - C2H_MM_ERR_CODE_ENABLE_RESERVED0_MASK}, - {"C2H_MM_ERR_CODE_ENABLE_RD_SLV_ERR", - C2H_MM_ERR_CODE_ENABLE_RD_SLV_ERR_MASK}, - {"C2H_MM_ERR_CODE_ENABLE_WR_SLV_ERR", - C2H_MM_ERR_CODE_ENABLE_WR_SLV_ERR_MASK}, -}; - - -static struct regfield_info - c2h_mm_err_code_field_info[] = { - {"C2H_MM_ERR_CODE_RESERVED1", - C2H_MM_ERR_CODE_RESERVED1_MASK}, - {"C2H_MM_ERR_CODE_CIDX", - C2H_MM_ERR_CODE_CIDX_MASK}, - {"C2H_MM_ERR_CODE_RESERVED0", - C2H_MM_ERR_CODE_RESERVED0_MASK}, - {"C2H_MM_ERR_CODE_SUB_TYPE", - C2H_MM_ERR_CODE_SUB_TYPE_MASK}, - {"C2H_MM_ERR_CODE", - C2H_MM_ERR_CODE_MASK}, -}; - - -static struct regfield_info - c2h_mm_err_info_field_info[] = { - {"C2H_MM_ERR_INFO_VALID", - C2H_MM_ERR_INFO_VALID_MASK}, - {"C2H_MM_ERR_INFO_SEL", - C2H_MM_ERR_INFO_SEL_MASK}, - {"C2H_MM_ERR_INFO_RSVD_1", - C2H_MM_ERR_INFO_RSVD_1_MASK}, - {"C2H_MM_ERR_INFO_QID", - C2H_MM_ERR_INFO_QID_MASK}, -}; - - -static struct regfield_info - c2h_mm_perf_mon_ctl_field_info[] = { - {"C2H_MM_PERF_MON_CTL_RSVD_1", - C2H_MM_PERF_MON_CTL_RSVD_1_MASK}, - {"C2H_MM_PERF_MON_CTL_IMM_START", - C2H_MM_PERF_MON_CTL_IMM_START_MASK}, - {"C2H_MM_PERF_MON_CTL_RUN_START", - C2H_MM_PERF_MON_CTL_RUN_START_MASK}, - {"C2H_MM_PERF_MON_CTL_IMM_CLEAR", - C2H_MM_PERF_MON_CTL_IMM_CLEAR_MASK}, - {"C2H_MM_PERF_MON_CTL_RUN_CLEAR", - C2H_MM_PERF_MON_CTL_RUN_CLEAR_MASK}, -}; - - -static struct regfield_info - c2h_mm_perf_mon_cycle_cnt0_field_info[] = { - {"C2H_MM_PERF_MON_CYCLE_CNT0_CYC_CNT", - C2H_MM_PERF_MON_CYCLE_CNT0_CYC_CNT_MASK}, -}; - - -static struct regfield_info - c2h_mm_perf_mon_cycle_cnt1_field_info[] = { - {"C2H_MM_PERF_MON_CYCLE_CNT1_RSVD_1", - C2H_MM_PERF_MON_CYCLE_CNT1_RSVD_1_MASK}, - {"C2H_MM_PERF_MON_CYCLE_CNT1_CYC_CNT", - C2H_MM_PERF_MON_CYCLE_CNT1_CYC_CNT_MASK}, -}; - - -static struct regfield_info - c2h_mm_perf_mon_data_cnt0_field_info[] = { - {"C2H_MM_PERF_MON_DATA_CNT0_DCNT", - C2H_MM_PERF_MON_DATA_CNT0_DCNT_MASK}, -}; - - -static struct regfield_info - c2h_mm_perf_mon_data_cnt1_field_info[] = { - {"C2H_MM_PERF_MON_DATA_CNT1_RSVD_1", - C2H_MM_PERF_MON_DATA_CNT1_RSVD_1_MASK}, - {"C2H_MM_PERF_MON_DATA_CNT1_DCNT", - C2H_MM_PERF_MON_DATA_CNT1_DCNT_MASK}, -}; - - -static struct regfield_info - c2h_mm_dbg_field_info[] = { - {"C2H_MM_RSVD_1", - C2H_MM_RSVD_1_MASK}, - {"C2H_MM_RRQ_ENTRIES", - C2H_MM_RRQ_ENTRIES_MASK}, - {"C2H_MM_DAT_FIFO_SPC", - C2H_MM_DAT_FIFO_SPC_MASK}, - {"C2H_MM_RD_STALL", - C2H_MM_RD_STALL_MASK}, - {"C2H_MM_RRQ_FIFO_FI", - C2H_MM_RRQ_FIFO_FI_MASK}, - {"C2H_MM_WR_STALL", - C2H_MM_WR_STALL_MASK}, - {"C2H_MM_WRQ_FIFO_FI", - C2H_MM_WRQ_FIFO_FI_MASK}, - {"C2H_MM_WBK_STALL", - C2H_MM_WBK_STALL_MASK}, - {"C2H_MM_DSC_FIFO_EP", - C2H_MM_DSC_FIFO_EP_MASK}, - {"C2H_MM_DSC_FIFO_FL", - C2H_MM_DSC_FIFO_FL_MASK}, -}; - - -static struct regfield_info - h2c_mm_ctl_field_info[] = { - {"H2C_MM_CTL_RESERVED1", - H2C_MM_CTL_RESERVED1_MASK}, - {"H2C_MM_CTL_ERRC_EN", - H2C_MM_CTL_ERRC_EN_MASK}, - {"H2C_MM_CTL_RESERVED0", - H2C_MM_CTL_RESERVED0_MASK}, - {"H2C_MM_CTL_RUN", - H2C_MM_CTL_RUN_MASK}, -}; - - -static struct regfield_info - h2c_mm_status_field_info[] = { - {"H2C_MM_STATUS_RSVD_1", - H2C_MM_STATUS_RSVD_1_MASK}, - {"H2C_MM_STATUS_RUN", - H2C_MM_STATUS_RUN_MASK}, -}; - - -static struct regfield_info - h2c_mm_cmpl_desc_cnt_field_info[] = { - {"H2C_MM_CMPL_DESC_CNT_H2C_CO", - H2C_MM_CMPL_DESC_CNT_H2C_CO_MASK}, -}; - - -static struct regfield_info - h2c_mm_err_code_enable_mask_field_info[] = { - {"H2C_MM_ERR_CODE_ENABLE_RESERVED5", - H2C_MM_ERR_CODE_ENABLE_RESERVED5_MASK}, - {"H2C_MM_ERR_CODE_ENABLE_WR_SLV_ERR", - H2C_MM_ERR_CODE_ENABLE_WR_SLV_ERR_MASK}, - {"H2C_MM_ERR_CODE_ENABLE_WR_DEC_ERR", - H2C_MM_ERR_CODE_ENABLE_WR_DEC_ERR_MASK}, - {"H2C_MM_ERR_CODE_ENABLE_RESERVED4", - H2C_MM_ERR_CODE_ENABLE_RESERVED4_MASK}, - {"H2C_MM_ERR_CODE_ENABLE_RD_RQ_DIS_ERR", - H2C_MM_ERR_CODE_ENABLE_RD_RQ_DIS_ERR_MASK}, - {"H2C_MM_ERR_CODE_ENABLE_RESERVED3", - H2C_MM_ERR_CODE_ENABLE_RESERVED3_MASK}, - {"H2C_MM_ERR_CODE_ENABLE_RD_DAT_POISON_ERR", - H2C_MM_ERR_CODE_ENABLE_RD_DAT_POISON_ERR_MASK}, - {"H2C_MM_ERR_CODE_ENABLE_RESERVED2", - H2C_MM_ERR_CODE_ENABLE_RESERVED2_MASK}, - {"H2C_MM_ERR_CODE_ENABLE_RD_FLR_ERR", - H2C_MM_ERR_CODE_ENABLE_RD_FLR_ERR_MASK}, - {"H2C_MM_ERR_CODE_ENABLE_RESERVED1", - H2C_MM_ERR_CODE_ENABLE_RESERVED1_MASK}, - {"H2C_MM_ERR_CODE_ENABLE_RD_HDR_ADR_ERR", - H2C_MM_ERR_CODE_ENABLE_RD_HDR_ADR_ERR_MASK}, - {"H2C_MM_ERR_CODE_ENABLE_RD_HDR_PARA", - H2C_MM_ERR_CODE_ENABLE_RD_HDR_PARA_MASK}, - {"H2C_MM_ERR_CODE_ENABLE_RD_HDR_BYTE_ERR", - H2C_MM_ERR_CODE_ENABLE_RD_HDR_BYTE_ERR_MASK}, - {"H2C_MM_ERR_CODE_ENABLE_RD_UR_CA", - H2C_MM_ERR_CODE_ENABLE_RD_UR_CA_MASK}, - {"H2C_MM_ERR_CODE_ENABLE_RD_HRD_POISON_ERR", - H2C_MM_ERR_CODE_ENABLE_RD_HRD_POISON_ERR_MASK}, - {"H2C_MM_ERR_CODE_ENABLE_RESERVED0", - H2C_MM_ERR_CODE_ENABLE_RESERVED0_MASK}, -}; - - -static struct regfield_info - h2c_mm_err_code_field_info[] = { - {"H2C_MM_ERR_CODE_RSVD_1", - H2C_MM_ERR_CODE_RSVD_1_MASK}, - {"H2C_MM_ERR_CODE_CIDX", - H2C_MM_ERR_CODE_CIDX_MASK}, - {"H2C_MM_ERR_CODE_RESERVED0", - H2C_MM_ERR_CODE_RESERVED0_MASK}, - {"H2C_MM_ERR_CODE_SUB_TYPE", - H2C_MM_ERR_CODE_SUB_TYPE_MASK}, - {"H2C_MM_ERR_CODE", - H2C_MM_ERR_CODE_MASK}, -}; - - -static struct regfield_info - h2c_mm_err_info_field_info[] = { - {"H2C_MM_ERR_INFO_VALID", - H2C_MM_ERR_INFO_VALID_MASK}, - {"H2C_MM_ERR_INFO_SEL", - H2C_MM_ERR_INFO_SEL_MASK}, - {"H2C_MM_ERR_INFO_RSVD_1", - H2C_MM_ERR_INFO_RSVD_1_MASK}, - {"H2C_MM_ERR_INFO_QID", - H2C_MM_ERR_INFO_QID_MASK}, -}; - - -static struct regfield_info - h2c_mm_perf_mon_ctl_field_info[] = { - {"H2C_MM_PERF_MON_CTL_RSVD_1", - H2C_MM_PERF_MON_CTL_RSVD_1_MASK}, - {"H2C_MM_PERF_MON_CTL_IMM_START", - H2C_MM_PERF_MON_CTL_IMM_START_MASK}, - {"H2C_MM_PERF_MON_CTL_RUN_START", - H2C_MM_PERF_MON_CTL_RUN_START_MASK}, - {"H2C_MM_PERF_MON_CTL_IMM_CLEAR", - H2C_MM_PERF_MON_CTL_IMM_CLEAR_MASK}, - {"H2C_MM_PERF_MON_CTL_RUN_CLEAR", - H2C_MM_PERF_MON_CTL_RUN_CLEAR_MASK}, -}; - - -static struct regfield_info - h2c_mm_perf_mon_cycle_cnt0_field_info[] = { - {"H2C_MM_PERF_MON_CYCLE_CNT0_CYC_CNT", - H2C_MM_PERF_MON_CYCLE_CNT0_CYC_CNT_MASK}, -}; - - -static struct regfield_info - h2c_mm_perf_mon_cycle_cnt1_field_info[] = { - {"H2C_MM_PERF_MON_CYCLE_CNT1_RSVD_1", - H2C_MM_PERF_MON_CYCLE_CNT1_RSVD_1_MASK}, - {"H2C_MM_PERF_MON_CYCLE_CNT1_CYC_CNT", - H2C_MM_PERF_MON_CYCLE_CNT1_CYC_CNT_MASK}, -}; - - -static struct regfield_info - h2c_mm_perf_mon_data_cnt0_field_info[] = { - {"H2C_MM_PERF_MON_DATA_CNT0_DCNT", - H2C_MM_PERF_MON_DATA_CNT0_DCNT_MASK}, -}; - - -static struct regfield_info - h2c_mm_perf_mon_data_cnt1_field_info[] = { - {"H2C_MM_PERF_MON_DATA_CNT1_RSVD_1", - H2C_MM_PERF_MON_DATA_CNT1_RSVD_1_MASK}, - {"H2C_MM_PERF_MON_DATA_CNT1_DCNT", - H2C_MM_PERF_MON_DATA_CNT1_DCNT_MASK}, -}; - - -static struct regfield_info - h2c_mm_dbg_field_info[] = { - {"H2C_MM_RSVD_1", - H2C_MM_RSVD_1_MASK}, - {"H2C_MM_RRQ_ENTRIES", - H2C_MM_RRQ_ENTRIES_MASK}, - {"H2C_MM_DAT_FIFO_SPC", - H2C_MM_DAT_FIFO_SPC_MASK}, - {"H2C_MM_RD_STALL", - H2C_MM_RD_STALL_MASK}, - {"H2C_MM_RRQ_FIFO_FI", - H2C_MM_RRQ_FIFO_FI_MASK}, - {"H2C_MM_WR_STALL", - H2C_MM_WR_STALL_MASK}, - {"H2C_MM_WRQ_FIFO_FI", - H2C_MM_WRQ_FIFO_FI_MASK}, - {"H2C_MM_WBK_STALL", - H2C_MM_WBK_STALL_MASK}, - {"H2C_MM_DSC_FIFO_EP", - H2C_MM_DSC_FIFO_EP_MASK}, - {"H2C_MM_DSC_FIFO_FL", - H2C_MM_DSC_FIFO_FL_MASK}, -}; - - -static struct regfield_info - c2h_crdt_coal_cfg_1_field_info[] = { - {"C2H_CRDT_COAL_CFG_1_RSVD_1", - C2H_CRDT_COAL_CFG_1_RSVD_1_MASK}, - {"C2H_CRDT_COAL_CFG_1_PLD_FIFO_TH", - C2H_CRDT_COAL_CFG_1_PLD_FIFO_TH_MASK}, - {"C2H_CRDT_COAL_CFG_1_TIMER_TH", - C2H_CRDT_COAL_CFG_1_TIMER_TH_MASK}, -}; - - -static struct regfield_info - c2h_crdt_coal_cfg_2_field_info[] = { - {"C2H_CRDT_COAL_CFG_2_RSVD_1", - C2H_CRDT_COAL_CFG_2_RSVD_1_MASK}, - {"C2H_CRDT_COAL_CFG_2_FIFO_TH", - C2H_CRDT_COAL_CFG_2_FIFO_TH_MASK}, - {"C2H_CRDT_COAL_CFG_2_RESERVED1", - C2H_CRDT_COAL_CFG_2_RESERVED1_MASK}, - {"C2H_CRDT_COAL_CFG_2_NT_TH", - C2H_CRDT_COAL_CFG_2_NT_TH_MASK}, -}; - - -static struct regfield_info - c2h_pfch_byp_qid_field_info[] = { - {"C2H_PFCH_BYP_QID_RSVD_1", - C2H_PFCH_BYP_QID_RSVD_1_MASK}, - {"C2H_PFCH_BYP_QID", - C2H_PFCH_BYP_QID_MASK}, -}; - - -static struct regfield_info - c2h_pfch_byp_tag_field_info[] = { - {"C2H_PFCH_BYP_TAG_RSVD_1", - C2H_PFCH_BYP_TAG_RSVD_1_MASK}, - {"C2H_PFCH_BYP_TAG_BYP_QID", - C2H_PFCH_BYP_TAG_BYP_QID_MASK}, - {"C2H_PFCH_BYP_TAG_RSVD_2", - C2H_PFCH_BYP_TAG_RSVD_2_MASK}, - {"C2H_PFCH_BYP_TAG", - C2H_PFCH_BYP_TAG_MASK}, -}; - - -static struct regfield_info - c2h_water_mark_field_info[] = { - {"C2H_WATER_MARK_HIGH_WM", - C2H_WATER_MARK_HIGH_WM_MASK}, - {"C2H_WATER_MARK_LOW_WM", - C2H_WATER_MARK_LOW_WM_MASK}, -}; - -static struct xreg_info eqdma_config_regs[] = { -{"CFG_BLK_IDENTIFIER", 0x00, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(cfg_blk_identifier_field_info), - cfg_blk_identifier_field_info -}, -{"CFG_BLK_PCIE_MAX_PLD_SIZE", 0x08, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(cfg_blk_pcie_max_pld_size_field_info), - cfg_blk_pcie_max_pld_size_field_info -}, -{"CFG_BLK_PCIE_MAX_READ_REQ_SIZE", 0x0c, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(cfg_blk_pcie_max_read_req_size_field_info), - cfg_blk_pcie_max_read_req_size_field_info -}, -{"CFG_BLK_SYSTEM_ID", 0x10, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(cfg_blk_system_id_field_info), - cfg_blk_system_id_field_info -}, -{"CFG_BLK_MSIX_ENABLE", 0x014, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(cfg_blk_msix_enable_field_info), - cfg_blk_msix_enable_field_info -}, -{"CFG_PCIE_DATA_WIDTH", 0x18, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(cfg_pcie_data_width_field_info), - cfg_pcie_data_width_field_info -}, -{"CFG_PCIE_CTL", 0x1c, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(cfg_pcie_ctl_field_info), - cfg_pcie_ctl_field_info -}, -{"CFG_BLK_MSI_ENABLE", 0x20, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(cfg_blk_msi_enable_field_info), - cfg_blk_msi_enable_field_info -}, -{"CFG_AXI_USER_MAX_PLD_SIZE", 0x40, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(cfg_axi_user_max_pld_size_field_info), - cfg_axi_user_max_pld_size_field_info -}, -{"CFG_AXI_USER_MAX_READ_REQ_SIZE", 0x44, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(cfg_axi_user_max_read_req_size_field_info), - cfg_axi_user_max_read_req_size_field_info -}, -{"CFG_BLK_MISC_CTL", 0x4c, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(cfg_blk_misc_ctl_field_info), - cfg_blk_misc_ctl_field_info -}, -{"CFG_PL_CRED_CTL", 0x68, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(cfg_pl_cred_ctl_field_info), - cfg_pl_cred_ctl_field_info -}, -{"CFG_BLK_SCRATCH", 0x80, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(cfg_blk_scratch_field_info), - cfg_blk_scratch_field_info -}, -{"CFG_GIC", 0xa0, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(cfg_gic_field_info), - cfg_gic_field_info -}, -{"RAM_SBE_MSK_1_A", 0xe0, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(ram_sbe_msk_1_a_field_info), - ram_sbe_msk_1_a_field_info -}, -{"RAM_SBE_STS_1_A", 0xe4, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(ram_sbe_sts_1_a_field_info), - ram_sbe_sts_1_a_field_info -}, -{"RAM_DBE_MSK_1_A", 0xe8, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(ram_dbe_msk_1_a_field_info), - ram_dbe_msk_1_a_field_info -}, -{"RAM_DBE_STS_1_A", 0xec, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(ram_dbe_sts_1_a_field_info), - ram_dbe_sts_1_a_field_info -}, -{"RAM_SBE_MSK_A", 0xf0, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(ram_sbe_msk_a_field_info), - ram_sbe_msk_a_field_info -}, -{"RAM_SBE_STS_A", 0xf4, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(ram_sbe_sts_a_field_info), - ram_sbe_sts_a_field_info -}, -{"RAM_DBE_MSK_A", 0xf8, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(ram_dbe_msk_a_field_info), - ram_dbe_msk_a_field_info -}, -{"RAM_DBE_STS_A", 0xfc, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(ram_dbe_sts_a_field_info), - ram_dbe_sts_a_field_info -}, -{"GLBL2_IDENTIFIER", 0x100, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(glbl2_identifier_field_info), - glbl2_identifier_field_info -}, -{"GLBL2_CHANNEL_INST", 0x114, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(glbl2_channel_inst_field_info), - glbl2_channel_inst_field_info -}, -{"GLBL2_CHANNEL_MDMA", 0x118, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(glbl2_channel_mdma_field_info), - glbl2_channel_mdma_field_info -}, -{"GLBL2_CHANNEL_STRM", 0x11c, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(glbl2_channel_strm_field_info), - glbl2_channel_strm_field_info -}, -{"GLBL2_CHANNEL_CAP", 0x120, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(glbl2_channel_cap_field_info), - glbl2_channel_cap_field_info -}, -{"GLBL2_CHANNEL_PASID_CAP", 0x128, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(glbl2_channel_pasid_cap_field_info), - glbl2_channel_pasid_cap_field_info -}, -{"GLBL2_SYSTEM_ID", 0x130, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(glbl2_system_id_field_info), - glbl2_system_id_field_info -}, -{"GLBL2_MISC_CAP", 0x134, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(glbl2_misc_cap_field_info), - glbl2_misc_cap_field_info -}, -{"GLBL2_DBG_PCIE_RQ0", 0x1b8, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(glbl2_dbg_pcie_rq0_field_info), - glbl2_dbg_pcie_rq0_field_info -}, -{"GLBL2_DBG_PCIE_RQ1", 0x1bc, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(glbl2_dbg_pcie_rq1_field_info), - glbl2_dbg_pcie_rq1_field_info -}, -{"GLBL2_DBG_AXIMM_WR0", 0x1c0, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(glbl2_dbg_aximm_wr0_field_info), - glbl2_dbg_aximm_wr0_field_info -}, -{"GLBL2_DBG_AXIMM_WR1", 0x1c4, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(glbl2_dbg_aximm_wr1_field_info), - glbl2_dbg_aximm_wr1_field_info -}, -{"GLBL2_DBG_AXIMM_RD0", 0x1c8, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(glbl2_dbg_aximm_rd0_field_info), - glbl2_dbg_aximm_rd0_field_info -}, -{"GLBL2_DBG_AXIMM_RD1", 0x1cc, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(glbl2_dbg_aximm_rd1_field_info), - glbl2_dbg_aximm_rd1_field_info -}, -{"GLBL2_DBG_FAB0", 0x1d0, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(glbl2_dbg_fab0_field_info), - glbl2_dbg_fab0_field_info -}, -{"GLBL2_DBG_FAB1", 0x1d4, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(glbl2_dbg_fab1_field_info), - glbl2_dbg_fab1_field_info -}, -{"GLBL2_DBG_MATCH_SEL", 0x1f4, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(glbl2_dbg_match_sel_field_info), - glbl2_dbg_match_sel_field_info -}, -{"GLBL2_DBG_MATCH_MSK", 0x1f8, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(glbl2_dbg_match_msk_field_info), - glbl2_dbg_match_msk_field_info -}, -{"GLBL2_DBG_MATCH_PAT", 0x1fc, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(glbl2_dbg_match_pat_field_info), - glbl2_dbg_match_pat_field_info -}, -{"GLBL_RNG_SZ_1", 0x204, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(glbl_rng_sz_1_field_info), - glbl_rng_sz_1_field_info -}, -{"GLBL_RNG_SZ_2", 0x208, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(glbl_rng_sz_2_field_info), - glbl_rng_sz_2_field_info -}, -{"GLBL_RNG_SZ_3", 0x20c, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(glbl_rng_sz_3_field_info), - glbl_rng_sz_3_field_info -}, -{"GLBL_RNG_SZ_4", 0x210, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(glbl_rng_sz_4_field_info), - glbl_rng_sz_4_field_info -}, -{"GLBL_RNG_SZ_5", 0x214, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(glbl_rng_sz_5_field_info), - glbl_rng_sz_5_field_info -}, -{"GLBL_RNG_SZ_6", 0x218, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(glbl_rng_sz_6_field_info), - glbl_rng_sz_6_field_info -}, -{"GLBL_RNG_SZ_7", 0x21c, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(glbl_rng_sz_7_field_info), - glbl_rng_sz_7_field_info -}, -{"GLBL_RNG_SZ_8", 0x220, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(glbl_rng_sz_8_field_info), - glbl_rng_sz_8_field_info -}, -{"GLBL_RNG_SZ_9", 0x224, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(glbl_rng_sz_9_field_info), - glbl_rng_sz_9_field_info -}, -{"GLBL_RNG_SZ_A", 0x228, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(glbl_rng_sz_a_field_info), - glbl_rng_sz_a_field_info -}, -{"GLBL_RNG_SZ_B", 0x22c, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(glbl_rng_sz_b_field_info), - glbl_rng_sz_b_field_info -}, -{"GLBL_RNG_SZ_C", 0x230, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(glbl_rng_sz_c_field_info), - glbl_rng_sz_c_field_info -}, -{"GLBL_RNG_SZ_D", 0x234, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(glbl_rng_sz_d_field_info), - glbl_rng_sz_d_field_info -}, -{"GLBL_RNG_SZ_E", 0x238, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(glbl_rng_sz_e_field_info), - glbl_rng_sz_e_field_info -}, -{"GLBL_RNG_SZ_F", 0x23c, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(glbl_rng_sz_f_field_info), - glbl_rng_sz_f_field_info -}, -{"GLBL_RNG_SZ_10", 0x240, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(glbl_rng_sz_10_field_info), - glbl_rng_sz_10_field_info -}, -{"GLBL_ERR_STAT", 0x248, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(glbl_err_stat_field_info), - glbl_err_stat_field_info -}, -{"GLBL_ERR_MASK", 0x24c, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(glbl_err_mask_field_info), - glbl_err_mask_field_info -}, -{"GLBL_DSC_CFG", 0x250, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(glbl_dsc_cfg_field_info), - glbl_dsc_cfg_field_info -}, -{"GLBL_DSC_ERR_STS", 0x254, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(glbl_dsc_err_sts_field_info), - glbl_dsc_err_sts_field_info -}, -{"GLBL_DSC_ERR_MSK", 0x258, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(glbl_dsc_err_msk_field_info), - glbl_dsc_err_msk_field_info -}, -{"GLBL_DSC_ERR_LOG0", 0x25c, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(glbl_dsc_err_log0_field_info), - glbl_dsc_err_log0_field_info -}, -{"GLBL_DSC_ERR_LOG1", 0x260, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(glbl_dsc_err_log1_field_info), - glbl_dsc_err_log1_field_info -}, -{"GLBL_TRQ_ERR_STS", 0x264, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(glbl_trq_err_sts_field_info), - glbl_trq_err_sts_field_info -}, -{"GLBL_TRQ_ERR_MSK", 0x268, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(glbl_trq_err_msk_field_info), - glbl_trq_err_msk_field_info -}, -{"GLBL_TRQ_ERR_LOG", 0x26c, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(glbl_trq_err_log_field_info), - glbl_trq_err_log_field_info -}, -{"GLBL_DSC_DBG_DAT0", 0x270, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(glbl_dsc_dbg_dat0_field_info), - glbl_dsc_dbg_dat0_field_info -}, -{"GLBL_DSC_DBG_DAT1", 0x274, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(glbl_dsc_dbg_dat1_field_info), - glbl_dsc_dbg_dat1_field_info -}, -{"GLBL_DSC_DBG_CTL", 0x278, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(glbl_dsc_dbg_ctl_field_info), - glbl_dsc_dbg_ctl_field_info -}, -{"GLBL_DSC_ERR_LOG2", 0x27c, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(glbl_dsc_err_log2_field_info), - glbl_dsc_err_log2_field_info -}, -{"GLBL_GLBL_INTERRUPT_CFG", 0x2c4, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(glbl_glbl_interrupt_cfg_field_info), - glbl_glbl_interrupt_cfg_field_info -}, -{"GLBL_VCH_HOST_PROFILE", 0x2c8, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(glbl_vch_host_profile_field_info), - glbl_vch_host_profile_field_info -}, -{"GLBL_BRIDGE_HOST_PROFILE", 0x308, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(glbl_bridge_host_profile_field_info), - glbl_bridge_host_profile_field_info -}, -{"AXIMM_IRQ_DEST_ADDR", 0x30c, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(aximm_irq_dest_addr_field_info), - aximm_irq_dest_addr_field_info -}, -{"FAB_ERR_LOG", 0x314, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(fab_err_log_field_info), - fab_err_log_field_info -}, -{"GLBL_REQ_ERR_STS", 0x318, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(glbl_req_err_sts_field_info), - glbl_req_err_sts_field_info -}, -{"GLBL_REQ_ERR_MSK", 0x31c, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(glbl_req_err_msk_field_info), - glbl_req_err_msk_field_info -}, -{"IND_CTXT_DATA", 0x804, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(ind_ctxt_data_field_info), - ind_ctxt_data_field_info -}, -{"IND_CTXT_MASK", 0x824, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(ind_ctxt_mask_field_info), - ind_ctxt_mask_field_info -}, -{"IND_CTXT_CMD", 0x844, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(ind_ctxt_cmd_field_info), - ind_ctxt_cmd_field_info -}, -{"C2H_TIMER_CNT", 0xa00, - 1, 0, 0, 0, - 0, QDMA_COMPLETION_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_timer_cnt_field_info), - c2h_timer_cnt_field_info -}, -{"C2H_CNT_TH", 0xa40, - 1, 0, 0, 0, - 0, QDMA_COMPLETION_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_cnt_th_field_info), - c2h_cnt_th_field_info -}, -{"C2H_STAT_S_AXIS_C2H_ACCEPTED", 0xa88, - 1, 0, 0, 0, - 1, QDMA_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(c2h_stat_s_axis_c2h_accepted_field_info), - c2h_stat_s_axis_c2h_accepted_field_info -}, -{"C2H_STAT_S_AXIS_WRB_ACCEPTED", 0xa8c, - 1, 0, 0, 0, - 1, QDMA_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(c2h_stat_s_axis_wrb_accepted_field_info), - c2h_stat_s_axis_wrb_accepted_field_info -}, -{"C2H_STAT_DESC_RSP_PKT_ACCEPTED", 0xa90, - 1, 0, 0, 0, - 1, QDMA_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(c2h_stat_desc_rsp_pkt_accepted_field_info), - c2h_stat_desc_rsp_pkt_accepted_field_info -}, -{"C2H_STAT_AXIS_PKG_CMP", 0xa94, - 1, 0, 0, 0, - 1, QDMA_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(c2h_stat_axis_pkg_cmp_field_info), - c2h_stat_axis_pkg_cmp_field_info -}, -{"C2H_STAT_DESC_RSP_ACCEPTED", 0xa98, - 1, 0, 0, 0, - 1, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_stat_desc_rsp_accepted_field_info), - c2h_stat_desc_rsp_accepted_field_info -}, -{"C2H_STAT_DESC_RSP_CMP", 0xa9c, - 1, 0, 0, 0, - 1, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_stat_desc_rsp_cmp_field_info), - c2h_stat_desc_rsp_cmp_field_info -}, -{"C2H_STAT_WRQ_OUT", 0xaa0, - 1, 0, 0, 0, - 1, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_stat_wrq_out_field_info), - c2h_stat_wrq_out_field_info -}, -{"C2H_STAT_WPL_REN_ACCEPTED", 0xaa4, - 1, 0, 0, 0, - 1, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_stat_wpl_ren_accepted_field_info), - c2h_stat_wpl_ren_accepted_field_info -}, -{"C2H_STAT_TOTAL_WRQ_LEN", 0xaa8, - 1, 0, 0, 0, - 1, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_stat_total_wrq_len_field_info), - c2h_stat_total_wrq_len_field_info -}, -{"C2H_STAT_TOTAL_WPL_LEN", 0xaac, - 1, 0, 0, 0, - 1, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_stat_total_wpl_len_field_info), - c2h_stat_total_wpl_len_field_info -}, -{"C2H_BUF_SZ", 0xab0, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_buf_sz_field_info), - c2h_buf_sz_field_info -}, -{"C2H_ERR_STAT", 0xaf0, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(c2h_err_stat_field_info), - c2h_err_stat_field_info -}, -{"C2H_ERR_MASK", 0xaf4, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(c2h_err_mask_field_info), - c2h_err_mask_field_info -}, -{"C2H_FATAL_ERR_STAT", 0xaf8, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(c2h_fatal_err_stat_field_info), - c2h_fatal_err_stat_field_info -}, -{"C2H_FATAL_ERR_MASK", 0xafc, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(c2h_fatal_err_mask_field_info), - c2h_fatal_err_mask_field_info -}, -{"C2H_FATAL_ERR_ENABLE", 0xb00, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(c2h_fatal_err_enable_field_info), - c2h_fatal_err_enable_field_info -}, -{"GLBL_ERR_INT", 0xb04, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(glbl_err_int_field_info), - glbl_err_int_field_info -}, -{"C2H_PFCH_CFG", 0xb08, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_pfch_cfg_field_info), - c2h_pfch_cfg_field_info -}, -{"C2H_PFCH_CFG_1", 0xa80, - 1, 0, 0, 0, - 0, QDMA_COMPLETION_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_pfch_cfg_1_field_info), - c2h_pfch_cfg_1_field_info -}, -{"C2H_PFCH_CFG_2", 0xa84, - 1, 0, 0, 0, - 0, QDMA_COMPLETION_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_pfch_cfg_2_field_info), - c2h_pfch_cfg_2_field_info -}, -{"C2H_INT_TIMER_TICK", 0xb0c, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_int_timer_tick_field_info), - c2h_int_timer_tick_field_info -}, -{"C2H_STAT_DESC_RSP_DROP_ACCEPTED", 0xb10, - 1, 0, 0, 0, - 1, QDMA_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(c2h_stat_desc_rsp_drop_accepted_field_info), - c2h_stat_desc_rsp_drop_accepted_field_info -}, -{"C2H_STAT_DESC_RSP_ERR_ACCEPTED", 0xb14, - 1, 0, 0, 0, - 1, QDMA_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(c2h_stat_desc_rsp_err_accepted_field_info), - c2h_stat_desc_rsp_err_accepted_field_info -}, -{"C2H_STAT_DESC_REQ", 0xb18, - 1, 0, 0, 0, - 1, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_stat_desc_req_field_info), - c2h_stat_desc_req_field_info -}, -{"C2H_STAT_DBG_DMA_ENG_0", 0xb1c, - 1, 0, 0, 0, - 1, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_stat_dbg_dma_eng_0_field_info), - c2h_stat_dbg_dma_eng_0_field_info -}, -{"C2H_STAT_DBG_DMA_ENG_1", 0xb20, - 1, 0, 0, 0, - 1, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_stat_dbg_dma_eng_1_field_info), - c2h_stat_dbg_dma_eng_1_field_info -}, -{"C2H_STAT_DBG_DMA_ENG_2", 0xb24, - 1, 0, 0, 0, - 1, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_stat_dbg_dma_eng_2_field_info), - c2h_stat_dbg_dma_eng_2_field_info -}, -{"C2H_STAT_DBG_DMA_ENG_3", 0xb28, - 1, 0, 0, 0, - 1, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_stat_dbg_dma_eng_3_field_info), - c2h_stat_dbg_dma_eng_3_field_info -}, -{"C2H_DBG_PFCH_ERR_CTXT", 0xb2c, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_dbg_pfch_err_ctxt_field_info), - c2h_dbg_pfch_err_ctxt_field_info -}, -{"C2H_FIRST_ERR_QID", 0xb30, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(c2h_first_err_qid_field_info), - c2h_first_err_qid_field_info -}, -{"STAT_NUM_WRB_IN", 0xb34, - 1, 0, 0, 0, - 1, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(stat_num_wrb_in_field_info), - stat_num_wrb_in_field_info -}, -{"STAT_NUM_WRB_OUT", 0xb38, - 1, 0, 0, 0, - 1, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(stat_num_wrb_out_field_info), - stat_num_wrb_out_field_info -}, -{"STAT_NUM_WRB_DRP", 0xb3c, - 1, 0, 0, 0, - 1, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(stat_num_wrb_drp_field_info), - stat_num_wrb_drp_field_info -}, -{"STAT_NUM_STAT_DESC_OUT", 0xb40, - 1, 0, 0, 0, - 1, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(stat_num_stat_desc_out_field_info), - stat_num_stat_desc_out_field_info -}, -{"STAT_NUM_DSC_CRDT_SENT", 0xb44, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(stat_num_dsc_crdt_sent_field_info), - stat_num_dsc_crdt_sent_field_info -}, -{"STAT_NUM_FCH_DSC_RCVD", 0xb48, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(stat_num_fch_dsc_rcvd_field_info), - stat_num_fch_dsc_rcvd_field_info -}, -{"STAT_NUM_BYP_DSC_RCVD", 0xb4c, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(stat_num_byp_dsc_rcvd_field_info), - stat_num_byp_dsc_rcvd_field_info -}, -{"C2H_WRB_COAL_CFG", 0xb50, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_wrb_coal_cfg_field_info), - c2h_wrb_coal_cfg_field_info -}, -{"C2H_INTR_H2C_REQ", 0xb54, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(c2h_intr_h2c_req_field_info), - c2h_intr_h2c_req_field_info -}, -{"C2H_INTR_C2H_MM_REQ", 0xb58, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(c2h_intr_c2h_mm_req_field_info), - c2h_intr_c2h_mm_req_field_info -}, -{"C2H_INTR_ERR_INT_REQ", 0xb5c, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(c2h_intr_err_int_req_field_info), - c2h_intr_err_int_req_field_info -}, -{"C2H_INTR_C2H_ST_REQ", 0xb60, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(c2h_intr_c2h_st_req_field_info), - c2h_intr_c2h_st_req_field_info -}, -{"C2H_INTR_H2C_ERR_C2H_MM_MSIX_ACK", 0xb64, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_intr_h2c_err_c2h_mm_msix_ack_field_info), - c2h_intr_h2c_err_c2h_mm_msix_ack_field_info -}, -{"C2H_INTR_H2C_ERR_C2H_MM_MSIX_FAIL", 0xb68, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_intr_h2c_err_c2h_mm_msix_fail_field_info), - c2h_intr_h2c_err_c2h_mm_msix_fail_field_info -}, -{"C2H_INTR_H2C_ERR_C2H_MM_MSIX_NO_MSIX", 0xb6c, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_intr_h2c_err_c2h_mm_msix_no_msix_field_info), - c2h_intr_h2c_err_c2h_mm_msix_no_msix_field_info -}, -{"C2H_INTR_H2C_ERR_C2H_MM_CTXT_INVAL", 0xb70, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_intr_h2c_err_c2h_mm_ctxt_inval_field_info), - c2h_intr_h2c_err_c2h_mm_ctxt_inval_field_info -}, -{"C2H_INTR_C2H_ST_MSIX_ACK", 0xb74, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(c2h_intr_c2h_st_msix_ack_field_info), - c2h_intr_c2h_st_msix_ack_field_info -}, -{"C2H_INTR_C2H_ST_MSIX_FAIL", 0xb78, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(c2h_intr_c2h_st_msix_fail_field_info), - c2h_intr_c2h_st_msix_fail_field_info -}, -{"C2H_INTR_C2H_ST_NO_MSIX", 0xb7c, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_intr_c2h_st_no_msix_field_info), - c2h_intr_c2h_st_no_msix_field_info -}, -{"C2H_INTR_C2H_ST_CTXT_INVAL", 0xb80, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_intr_c2h_st_ctxt_inval_field_info), - c2h_intr_c2h_st_ctxt_inval_field_info -}, -{"C2H_STAT_WR_CMP", 0xb84, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_stat_wr_cmp_field_info), - c2h_stat_wr_cmp_field_info -}, -{"C2H_STAT_DBG_DMA_ENG_4", 0xb88, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_stat_dbg_dma_eng_4_field_info), - c2h_stat_dbg_dma_eng_4_field_info -}, -{"C2H_STAT_DBG_DMA_ENG_5", 0xb8c, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_stat_dbg_dma_eng_5_field_info), - c2h_stat_dbg_dma_eng_5_field_info -}, -{"C2H_DBG_PFCH_QID", 0xb90, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_dbg_pfch_qid_field_info), - c2h_dbg_pfch_qid_field_info -}, -{"C2H_DBG_PFCH", 0xb94, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_dbg_pfch_field_info), - c2h_dbg_pfch_field_info -}, -{"C2H_INT_DBG", 0xb98, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_int_dbg_field_info), - c2h_int_dbg_field_info -}, -{"C2H_STAT_IMM_ACCEPTED", 0xb9c, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_stat_imm_accepted_field_info), - c2h_stat_imm_accepted_field_info -}, -{"C2H_STAT_MARKER_ACCEPTED", 0xba0, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_stat_marker_accepted_field_info), - c2h_stat_marker_accepted_field_info -}, -{"C2H_STAT_DISABLE_CMP_ACCEPTED", 0xba4, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_stat_disable_cmp_accepted_field_info), - c2h_stat_disable_cmp_accepted_field_info -}, -{"C2H_PLD_FIFO_CRDT_CNT", 0xba8, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_pld_fifo_crdt_cnt_field_info), - c2h_pld_fifo_crdt_cnt_field_info -}, -{"C2H_INTR_DYN_REQ", 0xbac, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_intr_dyn_req_field_info), - c2h_intr_dyn_req_field_info -}, -{"C2H_INTR_DYN_MISC", 0xbb0, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_intr_dyn_misc_field_info), - c2h_intr_dyn_misc_field_info -}, -{"C2H_DROP_LEN_MISMATCH", 0xbb4, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_drop_len_mismatch_field_info), - c2h_drop_len_mismatch_field_info -}, -{"C2H_DROP_DESC_RSP_LEN", 0xbb8, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_drop_desc_rsp_len_field_info), - c2h_drop_desc_rsp_len_field_info -}, -{"C2H_DROP_QID_FIFO_LEN", 0xbbc, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_drop_qid_fifo_len_field_info), - c2h_drop_qid_fifo_len_field_info -}, -{"C2H_DROP_PLD_CNT", 0xbc0, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_drop_pld_cnt_field_info), - c2h_drop_pld_cnt_field_info -}, -{"C2H_CMPT_FORMAT_0", 0xbc4, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_cmpt_format_0_field_info), - c2h_cmpt_format_0_field_info -}, -{"C2H_CMPT_FORMAT_1", 0xbc8, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_cmpt_format_1_field_info), - c2h_cmpt_format_1_field_info -}, -{"C2H_CMPT_FORMAT_2", 0xbcc, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_cmpt_format_2_field_info), - c2h_cmpt_format_2_field_info -}, -{"C2H_CMPT_FORMAT_3", 0xbd0, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_cmpt_format_3_field_info), - c2h_cmpt_format_3_field_info -}, -{"C2H_CMPT_FORMAT_4", 0xbd4, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_cmpt_format_4_field_info), - c2h_cmpt_format_4_field_info -}, -{"C2H_CMPT_FORMAT_5", 0xbd8, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_cmpt_format_5_field_info), - c2h_cmpt_format_5_field_info -}, -{"C2H_CMPT_FORMAT_6", 0xbdc, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_cmpt_format_6_field_info), - c2h_cmpt_format_6_field_info -}, -{"C2H_PFCH_CACHE_DEPTH", 0xbe0, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_pfch_cache_depth_field_info), - c2h_pfch_cache_depth_field_info -}, -{"C2H_WRB_COAL_BUF_DEPTH", 0xbe4, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_wrb_coal_buf_depth_field_info), - c2h_wrb_coal_buf_depth_field_info -}, -{"C2H_PFCH_CRDT", 0xbe8, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_pfch_crdt_field_info), - c2h_pfch_crdt_field_info -}, -{"C2H_STAT_HAS_CMPT_ACCEPTED", 0xbec, - 1, 0, 0, 0, - 1, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_stat_has_cmpt_accepted_field_info), - c2h_stat_has_cmpt_accepted_field_info -}, -{"C2H_STAT_HAS_PLD_ACCEPTED", 0xbf0, - 1, 0, 0, 0, - 1, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_stat_has_pld_accepted_field_info), - c2h_stat_has_pld_accepted_field_info -}, -{"C2H_PLD_PKT_ID", 0xbf4, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_pld_pkt_id_field_info), - c2h_pld_pkt_id_field_info -}, -{"C2H_PLD_PKT_ID_1", 0xbf8, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_pld_pkt_id_1_field_info), - c2h_pld_pkt_id_1_field_info -}, -{"C2H_DROP_PLD_CNT_1", 0xbfc, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_drop_pld_cnt_1_field_info), - c2h_drop_pld_cnt_1_field_info -}, -{"H2C_ERR_STAT", 0xe00, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(h2c_err_stat_field_info), - h2c_err_stat_field_info -}, -{"H2C_ERR_MASK", 0xe04, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(h2c_err_mask_field_info), - h2c_err_mask_field_info -}, -{"H2C_FIRST_ERR_QID", 0xe08, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(h2c_first_err_qid_field_info), - h2c_first_err_qid_field_info -}, -{"H2C_DBG_REG0", 0xe0c, - 1, 0, 0, 0, - 1, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(h2c_dbg_reg0_field_info), - h2c_dbg_reg0_field_info -}, -{"H2C_DBG_REG1", 0xe10, - 1, 0, 0, 0, - 1, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(h2c_dbg_reg1_field_info), - h2c_dbg_reg1_field_info -}, -{"H2C_DBG_REG2", 0xe14, - 1, 0, 0, 0, - 1, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(h2c_dbg_reg2_field_info), - h2c_dbg_reg2_field_info -}, -{"H2C_DBG_REG3", 0xe18, - 1, 0, 0, 0, - 1, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(h2c_dbg_reg3_field_info), - h2c_dbg_reg3_field_info -}, -{"H2C_DBG_REG4", 0xe1c, - 1, 0, 0, 0, - 1, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(h2c_dbg_reg4_field_info), - h2c_dbg_reg4_field_info -}, -{"H2C_FATAL_ERR_EN", 0xe20, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(h2c_fatal_err_en_field_info), - h2c_fatal_err_en_field_info -}, -{"H2C_REQ_THROT_PCIE", 0xe24, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(h2c_req_throt_pcie_field_info), - h2c_req_throt_pcie_field_info -}, -{"H2C_ALN_DBG_REG0", 0xe28, - 1, 0, 0, 0, - 1, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(h2c_aln_dbg_reg0_field_info), - h2c_aln_dbg_reg0_field_info -}, -{"H2C_REQ_THROT_AXIMM", 0xe2c, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(h2c_req_throt_aximm_field_info), - h2c_req_throt_aximm_field_info -}, -{"C2H_MM_CTL", 0x1004, - 1, 0, 0, 0, - 0, QDMA_MM_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_mm_ctl_field_info), - c2h_mm_ctl_field_info -}, -{"C2H_MM_STATUS", 0x1040, - 1, 0, 0, 0, - 0, QDMA_MM_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_mm_status_field_info), - c2h_mm_status_field_info -}, -{"C2H_MM_CMPL_DESC_CNT", 0x1048, - 1, 0, 0, 0, - 0, QDMA_MM_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_mm_cmpl_desc_cnt_field_info), - c2h_mm_cmpl_desc_cnt_field_info -}, -{"C2H_MM_ERR_CODE_ENABLE_MASK", 0x1054, - 1, 0, 0, 0, - 0, QDMA_MM_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_mm_err_code_enable_mask_field_info), - c2h_mm_err_code_enable_mask_field_info -}, -{"C2H_MM_ERR_CODE", 0x1058, - 1, 0, 0, 0, - 0, QDMA_MM_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_mm_err_code_field_info), - c2h_mm_err_code_field_info -}, -{"C2H_MM_ERR_INFO", 0x105c, - 1, 0, 0, 0, - 0, QDMA_MM_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_mm_err_info_field_info), - c2h_mm_err_info_field_info -}, -{"C2H_MM_PERF_MON_CTL", 0x10c0, - 1, 0, 0, 0, - 0, QDMA_MM_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_mm_perf_mon_ctl_field_info), - c2h_mm_perf_mon_ctl_field_info -}, -{"C2H_MM_PERF_MON_CYCLE_CNT0", 0x10c4, - 1, 0, 0, 0, - 0, QDMA_MM_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_mm_perf_mon_cycle_cnt0_field_info), - c2h_mm_perf_mon_cycle_cnt0_field_info -}, -{"C2H_MM_PERF_MON_CYCLE_CNT1", 0x10c8, - 1, 0, 0, 0, - 0, QDMA_MM_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_mm_perf_mon_cycle_cnt1_field_info), - c2h_mm_perf_mon_cycle_cnt1_field_info -}, -{"C2H_MM_PERF_MON_DATA_CNT0", 0x10cc, - 1, 0, 0, 0, - 0, QDMA_MM_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_mm_perf_mon_data_cnt0_field_info), - c2h_mm_perf_mon_data_cnt0_field_info -}, -{"C2H_MM_PERF_MON_DATA_CNT1", 0x10d0, - 1, 0, 0, 0, - 0, QDMA_MM_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_mm_perf_mon_data_cnt1_field_info), - c2h_mm_perf_mon_data_cnt1_field_info -}, -{"C2H_MM_DBG", 0x10e8, - 1, 0, 0, 0, - 0, QDMA_MM_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_mm_dbg_field_info), - c2h_mm_dbg_field_info -}, -{"H2C_MM_CTL", 0x1204, - 1, 0, 0, 0, - 0, QDMA_MM_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(h2c_mm_ctl_field_info), - h2c_mm_ctl_field_info -}, -{"H2C_MM_STATUS", 0x1240, - 1, 0, 0, 0, - 0, QDMA_MM_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(h2c_mm_status_field_info), - h2c_mm_status_field_info -}, -{"H2C_MM_CMPL_DESC_CNT", 0x1248, - 1, 0, 0, 0, - 0, QDMA_MM_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(h2c_mm_cmpl_desc_cnt_field_info), - h2c_mm_cmpl_desc_cnt_field_info -}, -{"H2C_MM_ERR_CODE_ENABLE_MASK", 0x1254, - 1, 0, 0, 0, - 0, QDMA_MM_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(h2c_mm_err_code_enable_mask_field_info), - h2c_mm_err_code_enable_mask_field_info -}, -{"H2C_MM_ERR_CODE", 0x1258, - 1, 0, 0, 0, - 0, QDMA_MM_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(h2c_mm_err_code_field_info), - h2c_mm_err_code_field_info -}, -{"H2C_MM_ERR_INFO", 0x125c, - 1, 0, 0, 0, - 0, QDMA_MM_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(h2c_mm_err_info_field_info), - h2c_mm_err_info_field_info -}, -{"H2C_MM_PERF_MON_CTL", 0x12c0, - 1, 0, 0, 0, - 0, QDMA_MM_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(h2c_mm_perf_mon_ctl_field_info), - h2c_mm_perf_mon_ctl_field_info -}, -{"H2C_MM_PERF_MON_CYCLE_CNT0", 0x12c4, - 1, 0, 0, 0, - 0, QDMA_MM_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(h2c_mm_perf_mon_cycle_cnt0_field_info), - h2c_mm_perf_mon_cycle_cnt0_field_info -}, -{"H2C_MM_PERF_MON_CYCLE_CNT1", 0x12c8, - 1, 0, 0, 0, - 0, QDMA_MM_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(h2c_mm_perf_mon_cycle_cnt1_field_info), - h2c_mm_perf_mon_cycle_cnt1_field_info -}, -{"H2C_MM_PERF_MON_DATA_CNT0", 0x12cc, - 1, 0, 0, 0, - 0, QDMA_MM_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(h2c_mm_perf_mon_data_cnt0_field_info), - h2c_mm_perf_mon_data_cnt0_field_info -}, -{"H2C_MM_PERF_MON_DATA_CNT1", 0x12d0, - 1, 0, 0, 0, - 0, QDMA_MM_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(h2c_mm_perf_mon_data_cnt1_field_info), - h2c_mm_perf_mon_data_cnt1_field_info -}, -{"H2C_MM_DBG", 0x12e8, - 1, 0, 0, 0, - 0, QDMA_MM_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(h2c_mm_dbg_field_info), - h2c_mm_dbg_field_info -}, -{"C2H_CRDT_COAL_CFG_1", 0x1400, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_crdt_coal_cfg_1_field_info), - c2h_crdt_coal_cfg_1_field_info -}, -{"C2H_CRDT_COAL_CFG_2", 0x1404, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_crdt_coal_cfg_2_field_info), - c2h_crdt_coal_cfg_2_field_info -}, -{"C2H_PFCH_BYP_QID", 0x1408, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_pfch_byp_qid_field_info), - c2h_pfch_byp_qid_field_info -}, -{"C2H_PFCH_BYP_TAG", 0x140c, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_pfch_byp_tag_field_info), - c2h_pfch_byp_tag_field_info -}, -{"C2H_WATER_MARK", 0x1500, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_water_mark_field_info), - c2h_water_mark_field_info -}, - -}; - -uint32_t eqdma_config_num_regs_get(void) -{ - return (sizeof(eqdma_config_regs)/ - sizeof(eqdma_config_regs[0])); -} - -struct xreg_info *eqdma_config_regs_get(void) -{ - return eqdma_config_regs; -} - diff --git a/QDMA/windows/sys/libqdma/source/qdma_access/qdma_access_common.c b/QDMA/windows/sys/libqdma/source/qdma_access/qdma_access_common.c deleted file mode 100644 index 1419c6367..000000000 --- a/QDMA/windows/sys/libqdma/source/qdma_access/qdma_access_common.c +++ /dev/null @@ -1,1284 +0,0 @@ -/* - * Copyright (C) 2020 Xilinx, Inc - * - * Licensed under the Apache License, Version 2.0 (the "License"). You may - * not use this file except in compliance with the License. You may obtain - * a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - */ - -#include "qdma_access_common.h" -#include "qdma_platform.h" -#include "qdma_soft_reg.h" -#include "qdma_soft_access.h" -#include "qdma_s80_hard_access.h" -#include "eqdma_soft_access.h" -#include "qdma_reg_dump.h" - -#ifdef ENABLE_WPP_TRACING -#include "qdma_access_common.tmh" -#endif - -/* qdma version info */ -#define RTL_BASE_VERSION 2 -#define RTL_PATCH_VERSION 3 - -/** - * enum qdma_ip - To hold ip type - */ -enum qdma_ip { - QDMA_OR_VERSAL_IP, - EQDMA_IP -}; - - -/* - * hw_monitor_reg() - polling a register repeatly until - * (the register value & mask) == val or time is up - * - * return -QDMA_BUSY_IIMEOUT_ERR if register value didn't match, 0 other wise - */ -int hw_monitor_reg(void *dev_hndl, uint32_t reg, uint32_t mask, - uint32_t val, uint32_t interval_us, uint32_t timeout_us) -{ - int count; - uint32_t v; - - if (!interval_us) - interval_us = QDMA_REG_POLL_DFLT_INTERVAL_US; - if (!timeout_us) - timeout_us = QDMA_REG_POLL_DFLT_TIMEOUT_US; - - count = timeout_us / interval_us; - - do { - v = qdma_reg_read(dev_hndl, reg); - if ((v & mask) == val) - return QDMA_SUCCESS; - qdma_udelay(interval_us); - } while (--count); - - v = qdma_reg_read(dev_hndl, reg); - if ((v & mask) == val) - return QDMA_SUCCESS; - - qdma_log_error("%s: Reg read=%u Expected=%u, err:%d\n", - __func__, v, val, - -QDMA_ERR_HWACC_BUSY_TIMEOUT); - return -QDMA_ERR_HWACC_BUSY_TIMEOUT; -} - -/*****************************************************************************/ -/** - * qdma_get_rtl_version() - Function to get the rtl_version in - * string format - * - * @rtl_version: Vivado release ID - * - * Return: string - success and NULL on failure - *****************************************************************************/ -static const char *qdma_get_rtl_version(enum qdma_rtl_version rtl_version) -{ - switch (rtl_version) { - case QDMA_RTL_PATCH: - return "RTL Patch"; - case QDMA_RTL_BASE: - return "RTL Base"; - default: - qdma_log_error("%s: invalid rtl_version(%d), err:%d\n", - __func__, rtl_version, -QDMA_ERR_INV_PARAM); - return NULL; - } -} - -/*****************************************************************************/ -/** - * qdma_get_ip_type() - Function to get the ip type in string format - * - * @ip_type: IP Type - * - * Return: string - success and NULL on failure - *****************************************************************************/ -static const char *qdma_get_ip_type(enum qdma_ip_type ip_type) -{ - switch (ip_type) { - case QDMA_VERSAL_HARD_IP: - return "Versal Hard IP"; - case QDMA_VERSAL_SOFT_IP: - return "Versal Soft IP"; - case QDMA_SOFT_IP: - return "QDMA Soft IP"; - case EQDMA_SOFT_IP: - return "EQDMA Soft IP"; - default: - qdma_log_error("%s: invalid ip type(%d), err:%d\n", - __func__, ip_type, -QDMA_ERR_INV_PARAM); - return NULL; - } -} - -/*****************************************************************************/ -/** - * qdma_get_device_type() - Function to get the device type in - * string format - * - * @device_type: Device Type - * - * Return: string - success and NULL on failure - *****************************************************************************/ -static const char *qdma_get_device_type(enum qdma_device_type device_type) -{ - switch (device_type) { - case QDMA_DEVICE_SOFT: - return "Soft IP"; - case QDMA_DEVICE_VERSAL: - return "Versal S80 Hard IP"; - default: - qdma_log_error("%s: invalid device type(%d), err:%d\n", - __func__, device_type, -QDMA_ERR_INV_PARAM); - return NULL; - } -} - -/*****************************************************************************/ -/** - * qdma_get_vivado_release_id() - Function to get the vivado release id in - * string format - * - * @vivado_release_id: Vivado release ID - * - * Return: string - success and NULL on failure - *****************************************************************************/ -static const char *qdma_get_vivado_release_id( - enum qdma_vivado_release_id vivado_release_id) -{ - switch (vivado_release_id) { - case QDMA_VIVADO_2018_3: - return "vivado 2018.3"; - case QDMA_VIVADO_2019_1: - return "vivado 2019.1"; - case QDMA_VIVADO_2019_2: - return "vivado 2019.2"; - case QDMA_VIVADO_2020_1: - return "vivado 2020.1"; - case QDMA_VIVADO_2020_2: - return "vivado 2020.2"; - default: - qdma_log_error("%s: invalid vivado_release_id(%d), err:%d\n", - __func__, - vivado_release_id, - -QDMA_ERR_INV_PARAM); - return NULL; - } -} - - -void qdma_write_csr_values(void *dev_hndl, uint32_t reg_offst, - uint32_t idx, uint32_t cnt, const uint32_t *values) -{ - uint32_t index, reg_addr; - - for (index = idx; index < (idx + cnt); index++) { - reg_addr = reg_offst + (index * sizeof(uint32_t)); - qdma_reg_write(dev_hndl, reg_addr, values[index - idx]); - } -} - -void qdma_read_csr_values(void *dev_hndl, uint32_t reg_offst, - uint32_t idx, uint32_t cnt, uint32_t *values) -{ - uint32_t index, reg_addr; - - reg_addr = reg_offst + (idx * sizeof(uint32_t)); - for (index = 0; index < cnt; index++) { - values[index] = qdma_reg_read(dev_hndl, reg_addr + - (index * sizeof(uint32_t))); - } -} - -void qdma_fetch_version_details(uint8_t is_vf, uint32_t version_reg_val, - struct qdma_hw_version_info *version_info) -{ - uint32_t rtl_version, vivado_release_id, ip_type, device_type; - const char *version_str; - - if (!is_vf) { - rtl_version = FIELD_GET(QDMA_GLBL2_RTL_VERSION_MASK, - version_reg_val); - vivado_release_id = - FIELD_GET(QDMA_GLBL2_VIVADO_RELEASE_MASK, - version_reg_val); - device_type = FIELD_GET(QDMA_GLBL2_DEVICE_ID_MASK, - version_reg_val); - ip_type = FIELD_GET(QDMA_GLBL2_VERSAL_IP_MASK, - version_reg_val); - } else { - rtl_version = - FIELD_GET(QDMA_GLBL2_VF_RTL_VERSION_MASK, - version_reg_val); - vivado_release_id = - FIELD_GET(QDMA_GLBL2_VF_VIVADO_RELEASE_MASK, - version_reg_val); - device_type = FIELD_GET(QDMA_GLBL2_VF_DEVICE_ID_MASK, - version_reg_val); - ip_type = - FIELD_GET(QDMA_GLBL2_VF_VERSAL_IP_MASK, - version_reg_val); - } - - switch (rtl_version) { - case 0: - version_info->rtl_version = QDMA_RTL_BASE; - break; - case 1: - version_info->rtl_version = QDMA_RTL_PATCH; - break; - default: - version_info->rtl_version = QDMA_RTL_NONE; - break; - } - - version_str = qdma_get_rtl_version(version_info->rtl_version); - if (version_str != NULL) - qdma_strncpy(version_info->qdma_rtl_version_str, - version_str, - QDMA_HW_VERSION_STRING_LEN); - - switch (device_type) { - case 0: - version_info->device_type = QDMA_DEVICE_SOFT; - break; - case 1: - version_info->device_type = QDMA_DEVICE_VERSAL; - break; - default: - version_info->device_type = QDMA_DEVICE_NONE; - break; - } - - version_str = qdma_get_device_type(version_info->device_type); - if (version_str != NULL) - qdma_strncpy(version_info->qdma_device_type_str, - version_str, - QDMA_HW_VERSION_STRING_LEN); - - - if (version_info->device_type == QDMA_DEVICE_SOFT) { - switch (ip_type) { - case 0: - version_info->ip_type = QDMA_SOFT_IP; - break; - case 1: - version_info->ip_type = EQDMA_SOFT_IP; - break; - default: - version_info->ip_type = QDMA_NONE_IP; - } - } else { - switch (ip_type) { - case 0: - version_info->ip_type = QDMA_VERSAL_HARD_IP; - break; - case 1: - version_info->ip_type = QDMA_VERSAL_SOFT_IP; - break; - default: - version_info->ip_type = QDMA_NONE_IP; - } - } - - version_str = qdma_get_ip_type(version_info->ip_type); - if (version_str != NULL) - qdma_strncpy(version_info->qdma_ip_type_str, - version_str, - QDMA_HW_VERSION_STRING_LEN); - - if (version_info->ip_type == QDMA_SOFT_IP) { - switch (vivado_release_id) { - case 0: - version_info->vivado_release = QDMA_VIVADO_2018_3; - break; - case 1: - version_info->vivado_release = QDMA_VIVADO_2019_1; - break; - case 2: - version_info->vivado_release = QDMA_VIVADO_2019_2; - break; - default: - version_info->vivado_release = QDMA_VIVADO_NONE; - break; - } - } else if (version_info->ip_type == EQDMA_SOFT_IP) { - switch (vivado_release_id) { - case 0: - version_info->vivado_release = QDMA_VIVADO_2020_1; - break; - case 1: - version_info->vivado_release = QDMA_VIVADO_2020_2; - break; - default: - version_info->vivado_release = QDMA_VIVADO_NONE; - break; - } - } else { /* Versal case */ - switch (vivado_release_id) { - case 0: - version_info->vivado_release = QDMA_VIVADO_2019_2; - break; - default: - version_info->vivado_release = QDMA_VIVADO_NONE; - break; - } - } - - version_str = qdma_get_vivado_release_id( - version_info->vivado_release); - if (version_str != NULL) - qdma_strncpy(version_info->qdma_vivado_release_id_str, - version_str, - QDMA_HW_VERSION_STRING_LEN); -} - - -/* - * dump_reg() - Helper function to dump register value into string - * - * return len - length of the string copied into buffer - */ -int dump_reg(char *buf, int buf_sz, uint32_t raddr, - const char *rname, uint32_t rval) -{ - /* length of the line should be minimum 80 chars. - * If below print pattern is changed, check for - * new buffer size requirement - */ - if (buf_sz < DEBGFS_LINE_SZ) { - qdma_log_error("%s: buf_sz(%d) < expected(%d): err: %d\n", - __func__, - buf_sz, DEBGFS_LINE_SZ, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - return QDMA_SNPRINTF_S(buf, buf_sz, DEBGFS_LINE_SZ, - "[%#7x] %-47s %#-10x %u\n", - raddr, rname, rval, rval); - -} - -void qdma_memset(void *to, uint8_t val, uint32_t size) -{ - uint32_t i; - uint8_t *_to = (uint8_t *)to; - - for (i = 0; i < size; i++) - _to[i] = val; -} - -/*****************************************************************************/ -/** - * qdma_queue_cmpt_cidx_read() - function to read the CMPT CIDX register - * - * @dev_hndl: device handle - * @is_vf: Whether PF or VF - * @qid: Queue id relative to the PF/VF calling this API - * @reg_info: pointer to array to hold the values read - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -static int qdma_queue_cmpt_cidx_read(void *dev_hndl, uint8_t is_vf, - uint16_t qid, struct qdma_q_cmpt_cidx_reg_info *reg_info) -{ - uint32_t reg_val = 0; - uint32_t reg_addr = (is_vf) ? QDMA_OFFSET_VF_DMAP_SEL_CMPT_CIDX : - QDMA_OFFSET_DMAP_SEL_CMPT_CIDX; - - if (!dev_hndl) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - if (!reg_info) { - qdma_log_error("%s: reg_info is NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - - reg_addr += qid * QDMA_CMPT_CIDX_STEP; - - reg_val = qdma_reg_read(dev_hndl, reg_addr); - - reg_info->wrb_cidx = - FIELD_GET(QDMA_DMAP_SEL_CMPT_WRB_CIDX_MASK, reg_val); - reg_info->counter_idx = - (uint8_t)(FIELD_GET(QDMA_DMAP_SEL_CMPT_CNT_THRESH_MASK, - reg_val)); - reg_info->wrb_en = - (uint8_t)(FIELD_GET(QDMA_DMAP_SEL_CMPT_STS_DESC_EN_MASK, - reg_val)); - reg_info->irq_en = - (uint8_t)(FIELD_GET(QDMA_DMAP_SEL_CMPT_IRQ_EN_MASK, reg_val)); - reg_info->timer_idx = - (uint8_t)(FIELD_GET(QDMA_DMAP_SEL_CMPT_TMR_CNT_MASK, reg_val)); - reg_info->trig_mode = - (uint8_t)(FIELD_GET(QDMA_DMAP_SEL_CMPT_TRG_MODE_MASK, reg_val)); - - return QDMA_SUCCESS; -} - - -/*****************************************************************************/ -/** - * qdma_initiate_flr() - function to initiate Function Level Reset - * - * @dev_hndl: device handle - * @is_vf: Whether PF or VF - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -static int qdma_initiate_flr(void *dev_hndl, uint8_t is_vf) -{ - uint32_t reg_addr = (is_vf) ? QDMA_OFFSET_VF_REG_FLR_STATUS : - QDMA_OFFSET_PF_REG_FLR_STATUS; - - if (!dev_hndl) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - qdma_reg_write(dev_hndl, reg_addr, 1); - - return QDMA_SUCCESS; -} - -/*****************************************************************************/ -/** - * qdma_is_flr_done() - function to check whether the FLR is done or not - * - * @dev_hndl: device handle - * @is_vf: Whether PF or VF - * @done: if FLR process completed , done is 1 else 0. - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -static int qdma_is_flr_done(void *dev_hndl, uint8_t is_vf, uint8_t *done) -{ - int rv; - uint32_t reg_addr = (is_vf) ? QDMA_OFFSET_VF_REG_FLR_STATUS : - QDMA_OFFSET_PF_REG_FLR_STATUS; - - if (!dev_hndl) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - if (!done) { - qdma_log_error("%s: done is NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - /* wait for it to become zero */ - rv = hw_monitor_reg(dev_hndl, reg_addr, QDMA_FLR_STATUS_MASK, - 0, 5 * QDMA_REG_POLL_DFLT_INTERVAL_US, - QDMA_REG_POLL_DFLT_TIMEOUT_US); - if (rv < 0) - *done = 0; - else - *done = 1; - - return QDMA_SUCCESS; -} - -/*****************************************************************************/ -/** - * qdma_is_config_bar() - function for the config bar verification - * - * @dev_hndl: device handle - * @is_vf: Whether PF or VF - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -static int qdma_is_config_bar(void *dev_hndl, uint8_t is_vf, enum qdma_ip *ip) -{ - uint32_t reg_val = 0; - uint32_t reg_addr = (is_vf) ? QDMA_OFFSET_VF_VERSION : - QDMA_OFFSET_CONFIG_BLOCK_ID; - - if (!dev_hndl) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - reg_val = qdma_reg_read(dev_hndl, reg_addr); - - /** TODO: Version register for VFs is 0x5014 for EQDMA and - * 0x1014 for QDMA/Versal. First time reading 0x5014 for - * all the device and based on the upper 16 bits value - * (i.e. 0x1fd3), finding out whether its EQDMA or QDMA/Versal - * for EQDMA VFs. - * Need to modify this logic once the hardware team - * comes up with a common register for VFs - */ - if (is_vf) { - if (FIELD_GET(QDMA_GLBL2_VF_UNIQUE_ID_MASK, reg_val) - != QDMA_MAGIC_NUMBER) { - /* Its either QDMA or Versal */ - *ip = EQDMA_IP; - reg_addr = EQDMA_OFFSET_VF_VERSION; - reg_val = qdma_reg_read(dev_hndl, reg_addr); - } else { - *ip = QDMA_OR_VERSAL_IP; - return QDMA_SUCCESS; - } - } - - if (FIELD_GET(QDMA_CONFIG_BLOCK_ID_MASK, reg_val) - != QDMA_MAGIC_NUMBER) { - qdma_log_error("%s: Invalid config bar, err:%d\n", - __func__, - -QDMA_ERR_HWACC_INV_CONFIG_BAR); - return -QDMA_ERR_HWACC_INV_CONFIG_BAR; - } - - return QDMA_SUCCESS; -} - -int qdma_acc_reg_dump_buf_len(void *dev_hndl, - enum qdma_ip_type ip_type, int *buflen) -{ - uint32_t len = 0; - int rv = 0; - - *buflen = 0; - - if (!dev_hndl) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - - return -QDMA_ERR_INV_PARAM; - } - - switch (ip_type) { - case QDMA_SOFT_IP: - len = qdma_soft_reg_dump_buf_len(); - break; - case QDMA_VERSAL_HARD_IP: - len = qdma_s80_hard_reg_dump_buf_len(); - break; - case EQDMA_SOFT_IP: - len = eqdma_reg_dump_buf_len(); - break; - default: - qdma_log_error("%s: Invalid version number, err = %d", - __func__, -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - *buflen = (int)len; - return rv; -} - -int qdma_acc_reg_info_len(void *dev_hndl, - enum qdma_ip_type ip_type, int *buflen, int *num_regs) -{ - uint32_t len = 0; - int rv = 0; - - if (!dev_hndl) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - - return -QDMA_ERR_INV_PARAM; - } - - if (!buflen) { - qdma_log_error("%s: buflen is NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - - return -QDMA_ERR_INV_PARAM; - } - - if (!num_regs) { - qdma_log_error("%s: num_regs is NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - - return -QDMA_ERR_INV_PARAM; - } - - *buflen = 0; - - switch (ip_type) { - case QDMA_SOFT_IP: - len = 0; - *num_regs = 0; - break; - case QDMA_VERSAL_HARD_IP: - len = qdma_s80_hard_reg_dump_buf_len(); - *num_regs = (int)((len / REG_DUMP_SIZE_PER_LINE) - 1); - break; - case EQDMA_SOFT_IP: - len = eqdma_reg_dump_buf_len(); - *num_regs = (int)((len / REG_DUMP_SIZE_PER_LINE) - 1); - break; - default: - qdma_log_error("%s: Invalid version number, err = %d", - __func__, -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - *buflen = (int)len; - return rv; -} - -int qdma_acc_context_buf_len(void *dev_hndl, - enum qdma_ip_type ip_type, uint8_t st, - enum qdma_dev_q_type q_type, uint32_t *buflen) -{ - int rv = 0; - - *buflen = 0; - if (!dev_hndl) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - - return -QDMA_ERR_INV_PARAM; - } - - switch (ip_type) { - case QDMA_SOFT_IP: - rv = qdma_soft_context_buf_len(st, q_type, buflen); - break; - case QDMA_VERSAL_HARD_IP: - rv = qdma_s80_hard_context_buf_len(st, q_type, buflen); - break; - case EQDMA_SOFT_IP: - rv = eqdma_context_buf_len(st, q_type, buflen); - break; - default: - qdma_log_error("%s: Invalid version number, err = %d", - __func__, -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - return rv; -} - -int qdma_acc_get_num_config_regs(void *dev_hndl, - enum qdma_ip_type ip_type, uint32_t *num_regs) -{ - int rv = 0; - - *num_regs = 0; - if (!dev_hndl) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - - return -QDMA_ERR_INV_PARAM; - } - - switch (ip_type) { - case QDMA_SOFT_IP: - rv = qdma_get_config_num_regs(); - break; - case QDMA_VERSAL_HARD_IP: - rv = qdma_s80_hard_get_config_num_regs(); - break; - case EQDMA_SOFT_IP: - rv = eqdma_get_config_num_regs(); - break; - default: - qdma_log_error("%s: Invalid version number, err = %d", - __func__, -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - *num_regs = rv; - - return 0; -} - -/*****************************************************************************/ -/** - * qdma_acc_get_config_regs() - Function to get qdma config registers. - * - * @dev_hndl: device handle - * @is_vf: Whether PF or VF - * @ip_type: QDMA IP Type - * @reg_data: pointer to register data to be filled - * - * Return: Length up-till the buffer is filled -success and < 0 - failure - *****************************************************************************/ -int qdma_acc_get_config_regs(void *dev_hndl, uint8_t is_vf, - enum qdma_ip_type ip_type, - uint32_t *reg_data) -{ - struct xreg_info *reg_info; - uint32_t count = 0; - uint32_t num_regs; - int rv = 0; - - if (!dev_hndl) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - if (is_vf) { - qdma_log_error("%s: Get Config regs not valid for VF, err:%d\n", - __func__, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - if (reg_data == NULL) { - qdma_log_error("%s: reg_data is NULL, err:%d\n", - __func__, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - switch (ip_type) { - case QDMA_SOFT_IP: - num_regs = qdma_get_config_num_regs(); - reg_info = qdma_get_config_regs(); - break; - case QDMA_VERSAL_HARD_IP: - num_regs = qdma_s80_hard_get_config_num_regs(); - reg_info = qdma_s80_hard_get_config_regs(); - break; - case EQDMA_SOFT_IP: - num_regs = eqdma_get_config_num_regs(); - reg_info = eqdma_get_config_regs(); - break; - default: - qdma_log_error("%s: Invalid version number, err = %d", - __func__, -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - for (count = 0; count < num_regs - 1; count++) { - reg_data[count] = qdma_reg_read(dev_hndl, - reg_info[count].addr); - } - - return rv; -} - - -/*****************************************************************************/ -/** - * qdma_acc_dump_config_regs() - Function to get qdma config register dump in a - * buffer - * - * @dev_hndl: device handle - * @is_vf: Whether PF or VF - * @ip_type: QDMA IP Type - * @buf : pointer to buffer to be filled - * @buflen : Length of the buffer - * - * Return: Length up-till the buffer is filled -success and < 0 - failure - *****************************************************************************/ -int qdma_acc_dump_config_regs(void *dev_hndl, uint8_t is_vf, - enum qdma_ip_type ip_type, - char *buf, uint32_t buflen) -{ - int rv = 0; - - switch (ip_type) { - case QDMA_SOFT_IP: - rv = qdma_soft_dump_config_regs(dev_hndl, is_vf, - buf, buflen); - break; - case QDMA_VERSAL_HARD_IP: - rv = qdma_s80_hard_dump_config_regs(dev_hndl, is_vf, - buf, buflen); - break; - case EQDMA_SOFT_IP: - rv = eqdma_dump_config_regs(dev_hndl, is_vf, - buf, buflen); - break; - default: - qdma_log_error("%s: Invalid version number, err = %d", - __func__, -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - return rv; -} - -/*****************************************************************************/ -/** - * qdma_acc_dump_reg_info() - Function to dump fileds in - * a specified register. - * - * @dev_hndl: device handle - * @ip_type: QDMA IP Type - * @buf : pointer to buffer to be filled - * @buflen : Length of the buffer - * - * Return: Length up-till the buffer is filled -success and < 0 - failure - *****************************************************************************/ -int qdma_acc_dump_reg_info(void *dev_hndl, - enum qdma_ip_type ip_type, uint32_t reg_addr, - uint32_t num_regs, char *buf, uint32_t buflen) -{ - int rv = 0; - - if (!dev_hndl) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - if (!buf || !buflen) { - qdma_log_error("%s: Invalid input buffer, err = %d", - __func__, -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - switch (ip_type) { - case QDMA_SOFT_IP: - QDMA_SNPRINTF_S(buf, buflen, DEBGFS_LINE_SZ, - "QDMA reg field info not supported for QDMA_SOFT_IP\n"); - break; - case QDMA_VERSAL_HARD_IP: - rv = qdma_s80_hard_dump_reg_info(dev_hndl, reg_addr, - num_regs, buf, buflen); - break; - case EQDMA_SOFT_IP: - rv = eqdma_dump_reg_info(dev_hndl, reg_addr, - num_regs, buf, buflen); - break; - default: - qdma_log_error("%s: Invalid version number, err = %d", - __func__, -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - return rv; -} - -/*****************************************************************************/ -/** - * qdma_acc_dump_queue_context() - Function to get qdma queue context dump in a - * buffer - * - * @dev_hndl: device handle - * @ip_type: QDMA IP Type - * @st: Queue Mode (ST or MM) - * @q_type: Queue Type - * @ctxt_data: Context Data - * @buf : pointer to buffer to be filled - * @buflen : Length of the buffer - * - * Return: Length up-till the buffer is filled -success and < 0 - failure - *****************************************************************************/ -int qdma_acc_dump_queue_context(void *dev_hndl, - enum qdma_ip_type ip_type, - uint8_t st, - enum qdma_dev_q_type q_type, - struct qdma_descq_context *ctxt_data, - char *buf, uint32_t buflen) -{ - int rv = 0; - - switch (ip_type) { - case QDMA_SOFT_IP: - rv = qdma_soft_dump_queue_context(dev_hndl, - st, q_type, ctxt_data, buf, buflen); - break; - case QDMA_VERSAL_HARD_IP: - rv = qdma_s80_hard_dump_queue_context(dev_hndl, - st, q_type, ctxt_data, buf, buflen); - break; - case EQDMA_SOFT_IP: - rv = eqdma_dump_queue_context(dev_hndl, - st, q_type, ctxt_data, buf, buflen); - break; - default: - qdma_log_error("%s: Invalid version number, err = %d", - __func__, -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - return rv; -} - -/*****************************************************************************/ -/** - * qdma_acc_read_dump_queue_context() - Function to read and dump the queue - * context in the user-provided buffer. This API is valid only for PF and - * should not be used for VFs. For VF's use qdma_dump_queue_context() API - * after reading the context through mailbox. - * - * @dev_hndl: device handle - * @ip_type: QDMA IP type - * @hw_qid: queue id - * @st: Queue Mode(ST or MM) - * @q_type: Queue type(H2C/C2H/CMPT)* - * @buf : pointer to buffer to be filled - * @buflen : Length of the buffer - * - * Return: Length up-till the buffer is filled -success and < 0 - failure - *****************************************************************************/ -int qdma_acc_read_dump_queue_context(void *dev_hndl, - enum qdma_ip_type ip_type, - uint16_t qid_hw, - uint8_t st, - enum qdma_dev_q_type q_type, - char *buf, uint32_t buflen) -{ - int rv = QDMA_SUCCESS; - - switch (ip_type) { - case QDMA_SOFT_IP: - rv = qdma_soft_read_dump_queue_context(dev_hndl, - qid_hw, st, q_type, buf, buflen); - break; - case QDMA_VERSAL_HARD_IP: - rv = qdma_s80_hard_read_dump_queue_context(dev_hndl, - qid_hw, st, q_type, buf, buflen); - break; - case EQDMA_SOFT_IP: - rv = eqdma_read_dump_queue_context(dev_hndl, - qid_hw, st, q_type, buf, buflen); - break; - default: - qdma_log_error("%s: Invalid version number, err = %d", - __func__, -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - return rv; -} - -/*****************************************************************************/ -/** - * qdma_acc_dump_config_reg_list() - Dump the registers - * - * @dev_hndl: device handle - * @ip_type: QDMA ip type - * @num_regs : Max registers to read - * @reg_list : array of reg addr and reg values - * @buf : pointer to buffer to be filled - * @buflen : Length of the buffer - * - * Return: returns the platform specific error code - *****************************************************************************/ -int qdma_acc_dump_config_reg_list(void *dev_hndl, - enum qdma_ip_type ip_type, - uint32_t num_regs, - struct qdma_reg_data *reg_list, - char *buf, uint32_t buflen) -{ - int rv = 0; - - switch (ip_type) { - case QDMA_SOFT_IP: - rv = qdma_soft_dump_config_reg_list(dev_hndl, - num_regs, - reg_list, buf, buflen); - break; - case QDMA_VERSAL_HARD_IP: - rv = qdma_s80_hard_dump_config_reg_list(dev_hndl, - num_regs, - reg_list, buf, buflen); - break; - case EQDMA_SOFT_IP: - rv = eqdma_dump_config_reg_list(dev_hndl, - num_regs, - reg_list, buf, buflen); - break; - default: - qdma_log_error("%s: Invalid version number, err = %d", - __func__, -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - return rv; -} - - -/*****************************************************************************/ -/** - * qdma_get_function_number() - Function to get the function number - * - * @dev_hndl: device handle - * @func_id: pointer to hold the function id - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -static int qdma_get_function_number(void *dev_hndl, uint8_t *func_id) -{ - if (!dev_hndl || !func_id) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - *func_id = (uint8_t)qdma_reg_read(dev_hndl, - QDMA_OFFSET_GLBL2_CHANNEL_FUNC_RET); - - return QDMA_SUCCESS; -} - - -/*****************************************************************************/ -/** - * qdma_hw_error_intr_setup() - Function to set up the qdma error - * interrupt - * - * @dev_hndl: device handle - * @func_id: Function id - * @err_intr_index: Interrupt vector - * @rearm: rearm or not - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -static int qdma_hw_error_intr_setup(void *dev_hndl, uint16_t func_id, - uint8_t err_intr_index) -{ - uint32_t reg_val = 0; - - if (!dev_hndl) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - reg_val = - FIELD_SET(QDMA_GLBL_ERR_FUNC_MASK, func_id) | - FIELD_SET(QDMA_GLBL_ERR_VEC_MASK, err_intr_index); - - qdma_reg_write(dev_hndl, QDMA_OFFSET_GLBL_ERR_INT, reg_val); - - return QDMA_SUCCESS; -} - -/*****************************************************************************/ -/** - * qdma_hw_error_intr_rearm() - Function to re-arm the error interrupt - * - * @dev_hndl: device handle - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -static int qdma_hw_error_intr_rearm(void *dev_hndl) -{ - uint32_t reg_val = 0; - - if (!dev_hndl) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - reg_val = qdma_reg_read(dev_hndl, QDMA_OFFSET_GLBL_ERR_INT); - reg_val |= FIELD_SET(QDMA_GLBL_ERR_ARM_MASK, 1); - - qdma_reg_write(dev_hndl, QDMA_OFFSET_GLBL_ERR_INT, reg_val); - - return QDMA_SUCCESS; -} - -/*****************************************************************************/ -/** - * qdma_get_error_code() - function to get the qdma access mapped - * error code - * - * @acc_err_code: qdma access error code - * - * Return: returns the platform specific error code - *****************************************************************************/ -int qdma_get_error_code(int acc_err_code) -{ - return qdma_get_err_code(acc_err_code); -} - -int qdma_hw_access_init(void *dev_hndl, uint8_t is_vf, - struct qdma_hw_access *hw_access) -{ - int rv = QDMA_SUCCESS; - enum qdma_ip ip = EQDMA_IP; - - struct qdma_hw_version_info version_info; - - if (!dev_hndl) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - if (!hw_access) { - qdma_log_error("%s: hw_access is NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - rv = qdma_is_config_bar(dev_hndl, is_vf, &ip); - if (rv != QDMA_SUCCESS) { - qdma_log_error("%s: config bar passed is INVALID, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - return rv; - } - - qdma_memset(hw_access, 0, sizeof(struct qdma_hw_access)); - - if (ip == EQDMA_IP) - hw_access->qdma_get_version = &eqdma_get_version; - else - hw_access->qdma_get_version = &qdma_get_version; - hw_access->qdma_init_ctxt_memory = &qdma_init_ctxt_memory; - hw_access->qdma_fmap_conf = &qdma_fmap_conf; - hw_access->qdma_sw_ctx_conf = &qdma_sw_ctx_conf; - hw_access->qdma_pfetch_ctx_conf = &qdma_pfetch_ctx_conf; - hw_access->qdma_cmpt_ctx_conf = &qdma_cmpt_ctx_conf; - hw_access->qdma_hw_ctx_conf = &qdma_hw_ctx_conf; - hw_access->qdma_credit_ctx_conf = &qdma_credit_ctx_conf; - hw_access->qdma_indirect_intr_ctx_conf = &qdma_indirect_intr_ctx_conf; - hw_access->qdma_set_default_global_csr = &qdma_set_default_global_csr; - hw_access->qdma_global_csr_conf = &qdma_global_csr_conf; - hw_access->qdma_global_writeback_interval_conf = - &qdma_global_writeback_interval_conf; - hw_access->qdma_queue_pidx_update = &qdma_queue_pidx_update; - hw_access->qdma_queue_cmpt_cidx_read = &qdma_queue_cmpt_cidx_read; - hw_access->qdma_queue_cmpt_cidx_update = &qdma_queue_cmpt_cidx_update; - hw_access->qdma_queue_intr_cidx_update = &qdma_queue_intr_cidx_update; - hw_access->qdma_mm_channel_conf = &qdma_mm_channel_conf; - hw_access->qdma_get_user_bar = &qdma_get_user_bar; - hw_access->qdma_get_function_number = &qdma_get_function_number; - hw_access->qdma_get_device_attributes = &qdma_get_device_attributes; - hw_access->qdma_hw_error_intr_setup = &qdma_hw_error_intr_setup; - hw_access->qdma_hw_error_intr_rearm = &qdma_hw_error_intr_rearm; - hw_access->qdma_hw_error_enable = &qdma_hw_error_enable; - hw_access->qdma_hw_get_error_name = &qdma_hw_get_error_name; - hw_access->qdma_hw_error_process = &qdma_hw_error_process; - hw_access->qdma_dump_config_regs = &qdma_soft_dump_config_regs; - hw_access->qdma_dump_queue_context = &qdma_soft_dump_queue_context; - hw_access->qdma_read_dump_queue_context = - &qdma_soft_read_dump_queue_context; - hw_access->qdma_dump_intr_context = &qdma_dump_intr_context; - hw_access->qdma_is_legacy_intr_pend = &qdma_is_legacy_intr_pend; - hw_access->qdma_clear_pend_legacy_intr = &qdma_clear_pend_legacy_intr; - hw_access->qdma_legacy_intr_conf = &qdma_legacy_intr_conf; - hw_access->qdma_initiate_flr = &qdma_initiate_flr; - hw_access->qdma_is_flr_done = &qdma_is_flr_done; - hw_access->qdma_get_error_code = &qdma_get_error_code; - hw_access->qdma_read_reg_list = &qdma_read_reg_list; - hw_access->qdma_dump_config_reg_list = - &qdma_soft_dump_config_reg_list; - hw_access->qdma_dump_reg_info = &qdma_dump_reg_info; - hw_access->mbox_base_pf = QDMA_OFFSET_MBOX_BASE_PF; - hw_access->mbox_base_vf = QDMA_OFFSET_MBOX_BASE_VF; - hw_access->qdma_max_errors = QDMA_ERRS_ALL; - - rv = hw_access->qdma_get_version(dev_hndl, is_vf, &version_info); - if (rv != QDMA_SUCCESS) - return rv; - - qdma_log_info("Device Type: %s\n", - qdma_get_device_type(version_info.device_type)); - - qdma_log_info("IP Type: %s\n", - qdma_get_ip_type(version_info.ip_type)); - - qdma_log_info("Vivado Release: %s\n", - qdma_get_vivado_release_id(version_info.vivado_release)); - - if (version_info.ip_type == QDMA_VERSAL_HARD_IP) { - hw_access->qdma_init_ctxt_memory = - &qdma_s80_hard_init_ctxt_memory; - hw_access->qdma_qid2vec_conf = &qdma_s80_hard_qid2vec_conf; - hw_access->qdma_fmap_conf = &qdma_s80_hard_fmap_conf; - hw_access->qdma_sw_ctx_conf = &qdma_s80_hard_sw_ctx_conf; - hw_access->qdma_pfetch_ctx_conf = - &qdma_s80_hard_pfetch_ctx_conf; - hw_access->qdma_cmpt_ctx_conf = &qdma_s80_hard_cmpt_ctx_conf; - hw_access->qdma_hw_ctx_conf = &qdma_s80_hard_hw_ctx_conf; - hw_access->qdma_credit_ctx_conf = - &qdma_s80_hard_credit_ctx_conf; - hw_access->qdma_indirect_intr_ctx_conf = - &qdma_s80_hard_indirect_intr_ctx_conf; - hw_access->qdma_set_default_global_csr = - &qdma_s80_hard_set_default_global_csr; - hw_access->qdma_queue_pidx_update = - &qdma_s80_hard_queue_pidx_update; - hw_access->qdma_queue_cmpt_cidx_update = - &qdma_s80_hard_queue_cmpt_cidx_update; - hw_access->qdma_queue_intr_cidx_update = - &qdma_s80_hard_queue_intr_cidx_update; - hw_access->qdma_get_user_bar = &qdma_cmp_get_user_bar; - hw_access->qdma_get_device_attributes = - &qdma_s80_hard_get_device_attributes; - hw_access->qdma_dump_config_regs = - &qdma_s80_hard_dump_config_regs; - hw_access->qdma_dump_intr_context = - &qdma_s80_hard_dump_intr_context; - hw_access->qdma_hw_error_enable = - &qdma_s80_hard_hw_error_enable; - hw_access->qdma_hw_error_process = - &qdma_s80_hard_hw_error_process; - hw_access->qdma_hw_get_error_name = - &qdma_s80_hard_hw_get_error_name; - hw_access->qdma_legacy_intr_conf = NULL; - hw_access->qdma_read_reg_list = &qdma_s80_hard_read_reg_list; - hw_access->qdma_dump_config_reg_list = - &qdma_s80_hard_dump_config_reg_list; - hw_access->qdma_dump_queue_context = - &qdma_s80_hard_dump_queue_context; - hw_access->qdma_read_dump_queue_context = - &qdma_s80_hard_read_dump_queue_context; - hw_access->qdma_dump_reg_info = &qdma_s80_hard_dump_reg_info; - hw_access->qdma_max_errors = QDMA_S80_HARD_ERRS_ALL; - } - - if (version_info.ip_type == EQDMA_SOFT_IP) { - hw_access->qdma_init_ctxt_memory = &eqdma_init_ctxt_memory; - hw_access->qdma_sw_ctx_conf = &eqdma_sw_ctx_conf; - hw_access->qdma_pfetch_ctx_conf = &eqdma_pfetch_ctx_conf; - hw_access->qdma_cmpt_ctx_conf = &eqdma_cmpt_ctx_conf; - hw_access->qdma_indirect_intr_ctx_conf = - &eqdma_indirect_intr_ctx_conf; - hw_access->qdma_dump_config_regs = &eqdma_dump_config_regs; - hw_access->qdma_dump_intr_context = &eqdma_dump_intr_context; - hw_access->qdma_hw_error_enable = &eqdma_hw_error_enable; - hw_access->qdma_hw_error_process = &eqdma_hw_error_process; - hw_access->qdma_hw_get_error_name = &eqdma_hw_get_error_name; - hw_access->qdma_hw_ctx_conf = &eqdma_hw_ctx_conf; - hw_access->qdma_credit_ctx_conf = &eqdma_credit_ctx_conf; - hw_access->qdma_set_default_global_csr = - &eqdma_set_default_global_csr; - hw_access->qdma_get_device_attributes = - &eqdma_get_device_attributes; - hw_access->qdma_get_user_bar = &eqdma_get_user_bar; - hw_access->qdma_read_reg_list = &eqdma_read_reg_list; - hw_access->qdma_dump_config_reg_list = - &eqdma_dump_config_reg_list; - hw_access->qdma_dump_queue_context = - &eqdma_dump_queue_context; - hw_access->qdma_read_dump_queue_context = - &eqdma_read_dump_queue_context; - hw_access->qdma_dump_reg_info = &eqdma_dump_reg_info; - /* All CSR and Queue space register belongs to Window 0. - * Mailbox and MSIX register belongs to Window 1 - * Therefore, Mailbox offsets are different for EQDMA - * Mailbox offset for PF : 128K + original address - * Mailbox offset for VF : 16K + original address - */ - hw_access->mbox_base_pf = EQDMA_OFFSET_MBOX_BASE_PF; - hw_access->mbox_base_vf = EQDMA_OFFSET_MBOX_BASE_VF; - hw_access->qdma_max_errors = EQDMA_ERRS_ALL; - } - - return QDMA_SUCCESS; -} diff --git a/QDMA/windows/sys/libqdma/source/qdma_access/qdma_access_common.h b/QDMA/windows/sys/libqdma/source/qdma_access/qdma_access_common.h deleted file mode 100644 index d2dbf4ae2..000000000 --- a/QDMA/windows/sys/libqdma/source/qdma_access/qdma_access_common.h +++ /dev/null @@ -1,902 +0,0 @@ -/* - * Copyright (C) 2020 Xilinx, Inc - * - * Licensed under the Apache License, Version 2.0 (the "License"). You may - * not use this file except in compliance with the License. You may obtain - * a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - */ - -#ifndef __QDMA_ACCESS_COMMON_H_ -#define __QDMA_ACCESS_COMMON_H_ - -#ifdef __cplusplus -extern "C" { -#endif - -#include "qdma_access_export.h" -#include "qdma_access_errors.h" - -/* QDMA HW version string array length */ -#define QDMA_HW_VERSION_STRING_LEN 32 - -#define ENABLE_INIT_CTXT_MEMORY 1 - -#ifdef GCC_COMPILER -static inline uint32_t get_trailing_zeros(uint64_t x) -{ - uint32_t rv = - __builtin_ffsll(x) - 1; - return rv; -} -#else -static inline uint32_t get_trailing_zeros(uint64_t value) -{ - uint32_t pos = 0; - - if ((value & 0xffffffff) == 0) { - pos += 32; - value >>= 32; - } - if ((value & 0xffff) == 0) { - pos += 16; - value >>= 16; - } - if ((value & 0xff) == 0) { - pos += 8; - value >>= 8; - } - if ((value & 0xf) == 0) { - pos += 4; - value >>= 4; - } - if ((value & 0x3) == 0) { - pos += 2; - value >>= 2; - } - if ((value & 0x1) == 0) - pos += 1; - - return pos; -} -#endif - -#define FIELD_SHIFT(mask) get_trailing_zeros(mask) -#define FIELD_SET(mask, val) ((val << FIELD_SHIFT(mask)) & mask) -#define FIELD_GET(mask, reg) ((reg & mask) >> FIELD_SHIFT(mask)) - - -/* CSR Default values */ -#define DEFAULT_MAX_DSC_FETCH 6 -#define DEFAULT_WRB_INT QDMA_WRB_INTERVAL_128 -#define DEFAULT_PFCH_STOP_THRESH 256 -#define DEFAULT_PFCH_NUM_ENTRIES_PER_Q 8 -#define DEFAULT_PFCH_MAX_Q_CNT 16 -#define DEFAULT_C2H_INTR_TIMER_TICK 25 -#define DEFAULT_CMPT_COAL_TIMER_CNT 5 -#define DEFAULT_CMPT_COAL_TIMER_TICK 25 -#define DEFAULT_CMPT_COAL_MAX_BUF_SZ 32 - -#define QDMA_BAR_NUM 6 - -/** Maximum data vectors to be used for each function - * TODO: Please note that for 2018.2 only one vector would be used - * per pf and only one ring would be created for this vector - * It is also assumed that all functions have the same number of data vectors - * and currently different number of vectors per PF is not supported - */ -#define QDMA_NUM_DATA_VEC_FOR_INTR_CXT 1 - -enum ind_ctxt_cmd_op { - QDMA_CTXT_CMD_CLR, - QDMA_CTXT_CMD_WR, - QDMA_CTXT_CMD_RD, - QDMA_CTXT_CMD_INV -}; - -enum ind_ctxt_cmd_sel { - QDMA_CTXT_SEL_SW_C2H, - QDMA_CTXT_SEL_SW_H2C, - QDMA_CTXT_SEL_HW_C2H, - QDMA_CTXT_SEL_HW_H2C, - QDMA_CTXT_SEL_CR_C2H, - QDMA_CTXT_SEL_CR_H2C, - QDMA_CTXT_SEL_CMPT, - QDMA_CTXT_SEL_PFTCH, - QDMA_CTXT_SEL_INT_COAL, - QDMA_CTXT_SEL_PASID_RAM_LOW, - QDMA_CTXT_SEL_PASID_RAM_HIGH, - QDMA_CTXT_SEL_TIMER, - QDMA_CTXT_SEL_FMAP, -}; - -/* polling a register */ -#define QDMA_REG_POLL_DFLT_INTERVAL_US 10 /* 10us per poll */ -#define QDMA_REG_POLL_DFLT_TIMEOUT_US (500*1000) /* 500ms */ - -/** Constants */ -#define QDMA_NUM_RING_SIZES 16 -#define QDMA_NUM_C2H_TIMERS 16 -#define QDMA_NUM_C2H_BUFFER_SIZES 16 -#define QDMA_NUM_C2H_COUNTERS 16 -#define QDMA_MM_CONTROL_RUN 0x1 -#define QDMA_MM_CONTROL_STEP 0x100 -#define QDMA_MAGIC_NUMBER 0x1fd3 -#define QDMA_PIDX_STEP 0x10 -#define QDMA_CMPT_CIDX_STEP 0x10 -#define QDMA_INT_CIDX_STEP 0x10 - - -/** QDMA_IND_REG_SEL_PFTCH */ -#define QDMA_PFTCH_CTXT_SW_CRDT_GET_H_MASK GENMASK(15, 3) -#define QDMA_PFTCH_CTXT_SW_CRDT_GET_L_MASK GENMASK(2, 0) - -/** QDMA_IND_REG_SEL_CMPT */ -#define QDMA_COMPL_CTXT_BADDR_GET_H_MASK GENMASK_ULL(63, 38) -#define QDMA_COMPL_CTXT_BADDR_GET_L_MASK GENMASK_ULL(37, 12) -#define QDMA_COMPL_CTXT_PIDX_GET_H_MASK GENMASK(15, 4) -#define QDMA_COMPL_CTXT_PIDX_GET_L_MASK GENMASK(3, 0) - -#define QDMA_INTR_CTXT_BADDR_GET_H_MASK GENMASK_ULL(63, 61) -#define QDMA_INTR_CTXT_BADDR_GET_M_MASK GENMASK_ULL(60, 29) -#define QDMA_INTR_CTXT_BADDR_GET_L_MASK GENMASK_ULL(28, 12) - -#define QDMA_GLBL2_MM_CMPT_EN_MASK BIT(2) -#define QDMA_GLBL2_FLR_PRESENT_MASK BIT(1) -#define QDMA_GLBL2_MAILBOX_EN_MASK BIT(0) - -#define QDMA_REG_IND_CTXT_REG_COUNT 8 - -/* ------------------------ indirect register context fields -----------*/ -union qdma_ind_ctxt_cmd { - uint32_t word; - struct { - uint32_t busy:1; - uint32_t sel:4; - uint32_t op:2; - uint32_t qid:11; - uint32_t rsvd:14; - } bits; -}; - -#define QDMA_IND_CTXT_DATA_NUM_REGS 8 - -/** - * struct qdma_indirect_ctxt_regs - Inirect Context programming registers - */ -struct qdma_indirect_ctxt_regs { - uint32_t qdma_ind_ctxt_data[QDMA_IND_CTXT_DATA_NUM_REGS]; - uint32_t qdma_ind_ctxt_mask[QDMA_IND_CTXT_DATA_NUM_REGS]; - union qdma_ind_ctxt_cmd cmd; -}; - -/** - * struct qdma_fmap_cfg - fmap config data structure - */ -struct qdma_fmap_cfg { - - /** @qbase - queue base for the function */ - uint16_t qbase; - /** @qmax - maximum queues in the function */ - uint16_t qmax; -}; - -/** - * struct qdma_qid2vec - qid to vector mapping data structure - */ -struct qdma_qid2vec { - - /** @c2h_vector - For direct interrupt, it is the interrupt - * vector index of msix table; - * for indirect interrupt, it is the ring index - */ - uint8_t c2h_vector; - /** @c2h_en_coal - C2H Interrupt aggregation enable */ - uint8_t c2h_en_coal; - /** @h2c_vector - For direct interrupt, it is the interrupt - * vector index of msix table; - * for indirect interrupt, it is the ring index - */ - uint8_t h2c_vector; - /** @h2c_en_coal - H2C Interrupt aggregation enable */ - uint8_t h2c_en_coal; -}; - -/** - * struct qdma_descq_sw_ctxt - descq SW context config data structure - */ -struct qdma_descq_sw_ctxt { - - /** @ring_bs_addr - ring base address */ - uint64_t ring_bs_addr; - /** @vec - vector number */ - uint16_t vec; - /** @pidx - initial producer index */ - uint16_t pidx; - /** @irq_arm - Interrupt Arm */ - uint8_t irq_arm; - /** @fnc_id - Function ID */ - uint8_t fnc_id; - /** @qen - Indicates that the queue is enabled */ - uint8_t qen; - /** @frcd_en -Enable fetch credit */ - uint8_t frcd_en; - /** @wbi_chk -Writeback/Interrupt after pending check */ - uint8_t wbi_chk; - /** @wbi_intvl_en -Write back/Interrupt interval */ - uint8_t wbi_intvl_en; - /** @at - Address tanslation */ - uint8_t at; - /** @fetch_max - Maximum number of descriptor fetches outstanding */ - uint8_t fetch_max; - /** @rngsz_idx - Descriptor ring size index */ - uint8_t rngsz_idx; - /** @desc_sz -Descriptor fetch size */ - uint8_t desc_sz; - /** @bypass - bypass enable */ - uint8_t bypass; - /** @mm_chn - MM channel */ - uint8_t mm_chn; - /** @wbk_en -Writeback enable */ - uint8_t wbk_en; - /** @irq_en -Interrupt enable */ - uint8_t irq_en; - /** @port_id -Port_id */ - uint8_t port_id; - /** @irq_no_last - No interrupt was sent */ - uint8_t irq_no_last; - /** @err - Error status */ - uint8_t err; - /** @err_wb_sent -writeback/interrupt was sent for an error */ - uint8_t err_wb_sent; - /** @irq_req - Interrupt due to error waiting to be sent */ - uint8_t irq_req; - /** @mrkr_dis - Marker disable */ - uint8_t mrkr_dis; - /** @is_mm - MM mode */ - uint8_t is_mm; - /** @intr_aggr - interrupt aggregation enable */ - uint8_t intr_aggr; - /** @pasid_en - PASID Enable */ - uint8_t pasid_en; - /** @dis_intr_on_vf - Disbale interrupt with VF */ - uint8_t dis_intr_on_vf; - /** @virtio_en - Queue is in Virtio Mode */ - uint8_t virtio_en; - /** @pack_byp_out - descs on desc output interface can be packed */ - uint8_t pack_byp_out; - /** @irq_byp - IRQ Bypass mode */ - uint8_t irq_byp; - /** @host_id - Host ID */ - uint8_t host_id; - /** @pasid - PASID */ - uint32_t pasid; - /** @virtio_dsc_base - Virtio Desc Base Address */ - uint64_t virtio_dsc_base; -}; - -/** - * struct qdma_descq_hw_ctxt - descq hw context config data structure - */ -struct qdma_descq_hw_ctxt { - /** @cidx - consumer index */ - uint16_t cidx; - /** @crd_use - credits consumed */ - uint16_t crd_use; - /** @dsc_pend - descriptors pending */ - uint8_t dsc_pend; - /** @idl_stp_b -Queue invalid and no descriptors pending */ - uint8_t idl_stp_b; - /** @evt_pnd - Event pending */ - uint8_t evt_pnd; - /** @fetch_pnd -Descriptor fetch pending */ - uint8_t fetch_pnd; -}; - -/** - * struct qdma_descq_credit_ctxt - descq credit context config data structure - */ -struct qdma_descq_credit_ctxt { - - /** @credit -Fetch credits received. */ - uint32_t credit; -}; - -/** - * struct qdma_descq_prefetch_ctxt - descq pfetch context config data structure - */ -struct qdma_descq_prefetch_ctxt { - /** @sw_crdt -Software credit */ - uint16_t sw_crdt; - /** @bypass - bypass enable */ - uint8_t bypass; - /** @bufsz_idx - c2h buffer size index */ - uint8_t bufsz_idx; - /** @port_id - port ID */ - uint8_t port_id; - /** @var_desc - Variable Descriptor */ - uint8_t var_desc; - /** @num_pftch - Number of descs prefetched */ - uint16_t num_pftch; - /** @err -Error detected on this queue */ - uint8_t err; - /** @pfch_en - Enable prefetch */ - uint8_t pfch_en; - /** @pfch - Queue is in prefetch */ - uint8_t pfch; - /** @valid - context is valid */ - uint8_t valid; -}; - -/** - * struct qdma_descq_cmpt_ctxt - descq completion context config data structure - */ -struct qdma_descq_cmpt_ctxt { - /** @bs_addr - completion ring base address */ - uint64_t bs_addr; - /** @vec - Interrupt Vector */ - uint16_t vec; - /** @pidx_l - producer index low */ - uint16_t pidx; - /** @cidx - consumer index */ - uint16_t cidx; - /** @en_stat_desc - Enable Completion Status writes */ - uint8_t en_stat_desc; - /** @en_int - Enable Completion interrupts */ - uint8_t en_int; - /** @trig_mode - Interrupt and Completion Status Write Trigger Mode */ - uint8_t trig_mode; - /** @fnc_id - Function ID */ - uint8_t fnc_id; - /** @counter_idx - Index to counter register */ - uint8_t counter_idx; - /** @timer_idx - Index to timer register */ - uint8_t timer_idx; - /** @in_st - Interrupt State */ - uint8_t in_st; - /** @color - initial color bit to be used on Completion */ - uint8_t color; - /** @ringsz_idx - Completion ring size index to ring size registers */ - uint8_t ringsz_idx; - /** @desc_sz -descriptor size */ - uint8_t desc_sz; - /** @valid - context valid */ - uint8_t valid; - /** @err - error status */ - uint8_t err; - /** - * @user_trig_pend - user logic initiated interrupt is - * pending to be generate - */ - uint8_t user_trig_pend; - /** @timer_running - timer is running on this queue */ - uint8_t timer_running; - /** @full_upd - Full update */ - uint8_t full_upd; - /** @ovf_chk_dis - Completion Ring Overflow Check Disable */ - uint8_t ovf_chk_dis; - /** @at -Address Translation */ - uint8_t at; - /** @int_aggr -Interrupt Aggregation */ - uint8_t int_aggr; - /** @dis_intr_on_vf - Disbale interrupt with VF */ - uint8_t dis_intr_on_vf; - /** @vio - queue is in VirtIO mode */ - uint8_t vio; - /** @dir_c2h - DMA direction is C2H */ - uint8_t dir_c2h; - /** @host_id - Host ID */ - uint8_t host_id; - /** @pasid - PASID */ - uint32_t pasid; - /** @pasid_en - PASID Enable */ - uint8_t pasid_en; - /** @vio_eop - Virtio End-of-packet */ - uint8_t vio_eop; - /** @sh_cmpt - Shared Completion Queue */ - uint8_t sh_cmpt; -}; - -/** - * struct qdma_indirect_intr_ctxt - indirect interrupt context config data - * structure - */ -struct qdma_indirect_intr_ctxt { - /** @baddr_4k -Base address of Interrupt Aggregation Ring */ - uint64_t baddr_4k; - /** @vec - Interrupt vector index in msix table */ - uint16_t vec; - /** @pidx - Producer Index */ - uint16_t pidx; - /** @valid - context valid */ - uint8_t valid; - /** @int_st -Interrupt State */ - uint8_t int_st; - /** @color - Color bit */ - uint8_t color; - /** @page_size - Interrupt Aggregation Ring size */ - uint8_t page_size; - /** @at - Address translation */ - uint8_t at; - /** @host_id - Host ID */ - uint8_t host_id; - /** @pasid - PASID */ - uint32_t pasid; - /** @pasid_en - PASID Enable */ - uint8_t pasid_en; - /** @func_id - Function ID */ - uint16_t func_id; -}; - -struct qdma_hw_version_info { - /** @rtl_version - RTL Version */ - enum qdma_rtl_version rtl_version; - /** @vivado_release - Vivado Release id */ - enum qdma_vivado_release_id vivado_release; - /** @versal_ip_state - Versal IP state */ - enum qdma_ip_type ip_type; - /** @device_type - Device Type */ - enum qdma_device_type device_type; - /** @qdma_rtl_version_str - RTL Version string*/ - char qdma_rtl_version_str[QDMA_HW_VERSION_STRING_LEN]; - /** @qdma_vivado_release_id_str - Vivado Release id string*/ - char qdma_vivado_release_id_str[QDMA_HW_VERSION_STRING_LEN]; - /** @qdma_device_type_str - Qdma device type string*/ - char qdma_device_type_str[QDMA_HW_VERSION_STRING_LEN]; - /** @qdma_versal_ip_state_str - Versal IP state string*/ - char qdma_ip_type_str[QDMA_HW_VERSION_STRING_LEN]; -}; - -#define CTXT_ENTRY_NAME_SZ 64 -struct qctx_entry { - char name[CTXT_ENTRY_NAME_SZ]; - uint32_t value; -}; - -/** - * @struct - qdma_descq_context - * @brief queue context information - */ -struct qdma_descq_context { - struct qdma_qid2vec qid2vec; - struct qdma_fmap_cfg fmap; - struct qdma_descq_sw_ctxt sw_ctxt; - struct qdma_descq_hw_ctxt hw_ctxt; - struct qdma_descq_credit_ctxt cr_ctxt; - struct qdma_descq_prefetch_ctxt pfetch_ctxt; - struct qdma_descq_cmpt_ctxt cmpt_ctxt; -}; - -/** - * struct qdma_q_pidx_reg_info - Software PIDX register fields - */ -struct qdma_q_pidx_reg_info { - /** @pidx - Producer Index */ - uint16_t pidx; - /** @irq_en - Interrupt enable */ - uint8_t irq_en; -}; - -/** - * struct qdma_q_intr_cidx_reg_info - Interrupt Ring CIDX register fields - */ -struct qdma_intr_cidx_reg_info { - /** @sw_cidx - Software Consumer Index */ - uint16_t sw_cidx; - /** @rng_idx - Ring Index of the Interrupt Aggregation ring */ - uint8_t rng_idx; -}; - -/** - * struct qdma_q_cmpt_cidx_reg_info - CMPT CIDX register fields - */ -struct qdma_q_cmpt_cidx_reg_info { - /** @wrb_cidx - CMPT Consumer Index */ - uint16_t wrb_cidx; - /** @counter_idx - Counter Threshold Index */ - uint8_t counter_idx; - /** @timer_idx - Timer Count Index */ - uint8_t timer_idx; - /** @trig_mode - Trigger mode */ - uint8_t trig_mode; - /** @wrb_en - Enable status descriptor for CMPT */ - uint8_t wrb_en; - /** @irq_en - Enable Interrupt for CMPT */ - uint8_t irq_en; -}; - - -/** - * struct qdma_csr_info - Global CSR info data structure - */ -struct qdma_csr_info { - /** @ringsz: ring size values */ - uint16_t ringsz[QDMA_GLOBAL_CSR_ARRAY_SZ]; - /** @bufsz: buffer size values */ - uint16_t bufsz[QDMA_GLOBAL_CSR_ARRAY_SZ]; - /** @timer_cnt: timer threshold values */ - uint8_t timer_cnt[QDMA_GLOBAL_CSR_ARRAY_SZ]; - /** @cnt_thres: counter threshold values */ - uint8_t cnt_thres[QDMA_GLOBAL_CSR_ARRAY_SZ]; - /** @wb_intvl: writeback interval */ - uint8_t wb_intvl; -}; - -#define QDMA_MAX_REGISTER_DUMP 14 - -/** - * struct qdma_reg_data - Structure to - * hold address value and pair - */ -struct qdma_reg_data { - /** @reg_addr: register address */ - uint32_t reg_addr; - /** @reg_val: register value */ - uint32_t reg_val; -}; - -/** - * enum qdma_hw_access_type - To hold hw access type - */ -enum qdma_hw_access_type { - QDMA_HW_ACCESS_READ, - QDMA_HW_ACCESS_WRITE, - QDMA_HW_ACCESS_CLEAR, - QDMA_HW_ACCESS_INVALIDATE, - QDMA_HW_ACCESS_MAX -}; - -/** - * enum qdma_global_csr_type - To hold global csr type - */ -enum qdma_global_csr_type { - QDMA_CSR_RING_SZ, - QDMA_CSR_TIMER_CNT, - QDMA_CSR_CNT_TH, - QDMA_CSR_BUF_SZ, - QDMA_CSR_MAX -}; - -/** - * enum status_type - To hold enable/disable status type - */ -enum status_type { - DISABLE = 0, - ENABLE = 1, -}; - -/** - * enum qdma_reg_read_type - Indicates reg read type - */ -enum qdma_reg_read_type { - /** @QDMA_REG_READ_PF_ONLY: Read the register for PFs only */ - QDMA_REG_READ_PF_ONLY, - /** @QDMA_REG_READ_VF_ONLY: Read the register for VFs only */ - QDMA_REG_READ_VF_ONLY, - /** @QDMA_REG_READ_PF_VF: Read the register for both PF and VF */ - QDMA_REG_READ_PF_VF, - /** @QDMA_REG_READ_MAX: Reg read enum max */ - QDMA_REG_READ_MAX -}; - -/** - * enum qdma_reg_read_groups - Indicates reg read groups - */ -enum qdma_reg_read_groups { - /** @QDMA_REG_READ_GROUP_1: Read the register from 0x000 to 0x288 */ - QDMA_REG_READ_GROUP_1, - /** @QDMA_REG_READ_GROUP_2: Read the register from 0x400 to 0xAFC */ - QDMA_REG_READ_GROUP_2, - /** @QDMA_REG_READ_GROUP_3: Read the register from 0xB00 to 0xE28 */ - QDMA_REG_READ_GROUP_3, - /** @QDMA_REG_READ_GROUP_4: Read the register Mailbox Registers */ - QDMA_REG_READ_GROUP_4, - /** @QDMA_REG_READ_GROUP_MAX: Reg read max groups */ - QDMA_REG_READ_GROUP_MAX -}; - -void qdma_write_csr_values(void *dev_hndl, uint32_t reg_offst, - uint32_t idx, uint32_t cnt, const uint32_t *values); - -void qdma_read_csr_values(void *dev_hndl, uint32_t reg_offst, - uint32_t idx, uint32_t cnt, uint32_t *values); - -int dump_reg(char *buf, int buf_sz, uint32_t raddr, - const char *rname, uint32_t rval); - -int hw_monitor_reg(void *dev_hndl, uint32_t reg, uint32_t mask, - uint32_t val, uint32_t interval_us, - uint32_t timeout_us); - -void qdma_memset(void *to, uint8_t val, uint32_t size); - -int qdma_acc_reg_dump_buf_len(void *dev_hndl, - enum qdma_ip_type ip_type, int *buflen); - -int qdma_acc_reg_info_len(void *dev_hndl, - enum qdma_ip_type ip_type, int *buflen, int *num_regs); - -int qdma_acc_context_buf_len(void *dev_hndl, - enum qdma_ip_type ip_type, uint8_t st, - enum qdma_dev_q_type q_type, uint32_t *buflen); - -int qdma_acc_get_num_config_regs(void *dev_hndl, - enum qdma_ip_type ip_type, uint32_t *num_regs); - -/* - * struct qdma_hw_access - Structure to hold HW access function pointers - */ -struct qdma_hw_access { - int (*qdma_set_default_global_csr)(void *dev_hndl); - int (*qdma_global_csr_conf)(void *dev_hndl, uint8_t index, - uint8_t count, uint32_t *csr_val, - enum qdma_global_csr_type csr_type, - enum qdma_hw_access_type access_type); - int (*qdma_global_writeback_interval_conf)(void *dev_hndl, - enum qdma_wrb_interval *wb_int, - enum qdma_hw_access_type access_type); - int (*qdma_init_ctxt_memory)(void *dev_hndl); - int (*qdma_qid2vec_conf)(void *dev_hndl, uint8_t c2h, uint16_t hw_qid, - struct qdma_qid2vec *ctxt, - enum qdma_hw_access_type access_type); - int (*qdma_fmap_conf)(void *dev_hndl, uint16_t func_id, - struct qdma_fmap_cfg *config, - enum qdma_hw_access_type access_type); - int (*qdma_sw_ctx_conf)(void *dev_hndl, uint8_t c2h, uint16_t hw_qid, - struct qdma_descq_sw_ctxt *ctxt, - enum qdma_hw_access_type access_type); - int (*qdma_pfetch_ctx_conf)(void *dev_hndl, uint16_t hw_qid, - struct qdma_descq_prefetch_ctxt *ctxt, - enum qdma_hw_access_type access_type); - int (*qdma_cmpt_ctx_conf)(void *dev_hndl, uint16_t hw_qid, - struct qdma_descq_cmpt_ctxt *ctxt, - enum qdma_hw_access_type access_type); - int (*qdma_hw_ctx_conf)(void *dev_hndl, uint8_t c2h, uint16_t hw_qid, - struct qdma_descq_hw_ctxt *ctxt, - enum qdma_hw_access_type access_type); - int (*qdma_credit_ctx_conf)(void *dev_hndl, uint8_t c2h, - uint16_t hw_qid, - struct qdma_descq_credit_ctxt *ctxt, - enum qdma_hw_access_type access_type); - int (*qdma_indirect_intr_ctx_conf)(void *dev_hndl, uint16_t ring_index, - struct qdma_indirect_intr_ctxt *ctxt, - enum qdma_hw_access_type access_type); - int (*qdma_queue_pidx_update)(void *dev_hndl, uint8_t is_vf, - uint16_t qid, - uint8_t is_c2h, - const struct qdma_q_pidx_reg_info *reg_info); - int (*qdma_queue_cmpt_cidx_read)(void *dev_hndl, uint8_t is_vf, - uint16_t qid, - struct qdma_q_cmpt_cidx_reg_info *reg_info); - int (*qdma_queue_cmpt_cidx_update)(void *dev_hndl, uint8_t is_vf, - uint16_t qid, - const struct qdma_q_cmpt_cidx_reg_info *reg_info); - int (*qdma_queue_intr_cidx_update)(void *dev_hndl, uint8_t is_vf, - uint16_t qid, - const struct qdma_intr_cidx_reg_info *reg_info); - int (*qdma_mm_channel_conf)(void *dev_hndl, uint8_t channel, - uint8_t is_c2h, uint8_t enable); - int (*qdma_get_user_bar)(void *dev_hndl, uint8_t is_vf, - uint8_t func_id, uint8_t *user_bar); - int (*qdma_get_function_number)(void *dev_hndl, uint8_t *func_id); - int (*qdma_get_version)(void *dev_hndl, uint8_t is_vf, - struct qdma_hw_version_info *version_info); - int (*qdma_get_device_attributes)(void *dev_hndl, - struct qdma_dev_attributes *dev_info); - int (*qdma_hw_error_intr_setup)(void *dev_hndl, uint16_t func_id, - uint8_t err_intr_index); - int (*qdma_hw_error_intr_rearm)(void *dev_hndl); - int (*qdma_hw_error_enable)(void *dev_hndl, - uint32_t err_idx); - const char *(*qdma_hw_get_error_name)(uint32_t err_idx); - int (*qdma_hw_error_process)(void *dev_hndl); - int (*qdma_dump_config_regs)(void *dev_hndl, uint8_t is_vf, char *buf, - uint32_t buflen); - int (*qdma_dump_reg_info)(void *dev_hndl, uint32_t reg_addr, - uint32_t num_regs, - char *buf, - uint32_t buflen); - int (*qdma_dump_queue_context)(void *dev_hndl, - uint8_t st, - enum qdma_dev_q_type q_type, - struct qdma_descq_context *ctxt_data, - char *buf, uint32_t buflen); - int (*qdma_read_dump_queue_context)(void *dev_hndl, - uint16_t qid_hw, - uint8_t st, - enum qdma_dev_q_type q_type, - char *buf, uint32_t buflen); - int (*qdma_dump_intr_context)(void *dev_hndl, - struct qdma_indirect_intr_ctxt *intr_ctx, - int ring_index, - char *buf, uint32_t buflen); - int (*qdma_is_legacy_intr_pend)(void *dev_hndl); - int (*qdma_clear_pend_legacy_intr)(void *dev_hndl); - int (*qdma_legacy_intr_conf)(void *dev_hndl, enum status_type enable); - int (*qdma_initiate_flr)(void *dev_hndl, uint8_t is_vf); - int (*qdma_is_flr_done)(void *dev_hndl, uint8_t is_vf, uint8_t *done); - int (*qdma_get_error_code)(int acc_err_code); - int (*qdma_read_reg_list)(void *dev_hndl, uint8_t is_vf, - uint16_t reg_rd_group, - uint16_t *total_regs, - struct qdma_reg_data *reg_list); - int (*qdma_dump_config_reg_list)(void *dev_hndl, - uint32_t num_regs, - struct qdma_reg_data *reg_list, - char *buf, uint32_t buflen); - uint32_t mbox_base_pf; - uint32_t mbox_base_vf; - uint32_t qdma_max_errors; -}; - -/*****************************************************************************/ -/** - * qdma_hw_access_init() - Function to get the QDMA hardware - * access function pointers - * This function should be called once per device from - * device_open()/probe(). Caller shall allocate memory for - * qdma_hw_access structure and store pointer to it in their - * per device structure. Config BAR validation will be done - * inside this function - * - * @dev_hndl: device handle - * @is_vf: Whether PF or VF - * @hw_access: qdma_hw_access structure pointer. - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -int qdma_hw_access_init(void *dev_hndl, uint8_t is_vf, - struct qdma_hw_access *hw_access); - -/*****************************************************************************/ -/** - * qdma_acc_dump_config_regs() - Function to get qdma config registers - * - * @dev_hndl: device handle - * @is_vf: Whether PF or VF - * @ip_type: QDMA IP Type - * @reg_data: pointer to register data to be filled - * - * Return: Length up-till the buffer is filled -success and < 0 - failure - *****************************************************************************/ -int qdma_acc_get_config_regs(void *dev_hndl, uint8_t is_vf, - enum qdma_ip_type ip_type, - uint32_t *reg_data); - -/*****************************************************************************/ -/** - * qdma_acc_dump_config_regs() - Function to get qdma config register dump in a - * buffer - * - * @dev_hndl: device handle - * @is_vf: Whether PF or VF - * @ip_type: QDMA IP Type - * @buf : pointer to buffer to be filled - * @buflen : Length of the buffer - * - * Return: Length up-till the buffer is filled -success and < 0 - failure - *****************************************************************************/ -int qdma_acc_dump_config_regs(void *dev_hndl, uint8_t is_vf, - enum qdma_ip_type ip_type, - char *buf, uint32_t buflen); - -/*****************************************************************************/ -/** - * qdma_acc_dump_reg_info() - Function to get qdma reg info in a buffer - * - * @dev_hndl: device handle - * @ip_type: QDMA IP Type - * @reg_addr: Register Address - * @num_regs: Number of Registers - * @buf : pointer to buffer to be filled - * @buflen : Length of the buffer - * - * Return: Length up-till the buffer is filled -success and < 0 - failure - *****************************************************************************/ -int qdma_acc_dump_reg_info(void *dev_hndl, - enum qdma_ip_type ip_type, uint32_t reg_addr, - uint32_t num_regs, char *buf, uint32_t buflen); - -/*****************************************************************************/ -/** - * qdma_acc_dump_queue_context() - Function to dump qdma queue context data in a - * buffer where context information is already available in 'ctxt_data' - * structure pointer buffer - * - * @dev_hndl: device handle - * @ip_type: QDMA IP Type - * @st: ST or MM - * @q_type: Queue Type - * @ctxt_data: Context Data - * @buf : pointer to buffer to be filled - * @buflen : Length of the buffer - * - * Return: Length up-till the buffer is filled -success and < 0 - failure - *****************************************************************************/ -int qdma_acc_dump_queue_context(void *dev_hndl, - enum qdma_ip_type ip_type, - uint8_t st, - enum qdma_dev_q_type q_type, - struct qdma_descq_context *ctxt_data, - char *buf, uint32_t buflen); - -/*****************************************************************************/ -/** - * qdma_acc_read_dump_queue_context() - Function to read and dump the queue - * context in a buffer - * - * @dev_hndl: device handle - * @ip_type: QDMA IP Type - * @qid_hw: queue id - * @st: ST or MM - * @q_type: Queue Type - * @buf : pointer to buffer to be filled - * @buflen : Length of the buffer - * - * Return: Length up-till the buffer is filled -success and < 0 - failure - *****************************************************************************/ -int qdma_acc_read_dump_queue_context(void *dev_hndl, - enum qdma_ip_type ip_type, - uint16_t qid_hw, - uint8_t st, - enum qdma_dev_q_type q_type, - char *buf, uint32_t buflen); - - -/*****************************************************************************/ -/** - * qdma_acc_dump_config_reg_list() - Dump the registers - * - * @dev_hndl: device handle - * @ip_type: QDMA IP Type - * @total_regs : Max registers to read - * @reg_list : array of reg addr and reg values - * @buf : pointer to buffer to be filled - * @buflen : Length of the buffer - * - * Return: returns the platform specific error code - *****************************************************************************/ -int qdma_acc_dump_config_reg_list(void *dev_hndl, - enum qdma_ip_type ip_type, - uint32_t num_regs, - struct qdma_reg_data *reg_list, - char *buf, uint32_t buflen); - -/*****************************************************************************/ -/** - * qdma_get_error_code() - function to get the qdma access mapped - * error code - * - * @acc_err_code: qdma access error code - * - * Return: returns the platform specific error code - *****************************************************************************/ -int qdma_get_error_code(int acc_err_code); - -/*****************************************************************************/ -/** - * qdma_fetch_version_details() - Function to fetch the version details from the - * version register value - * - * @is_vf : Whether PF or VF - * @version_reg_val : Value of the version register - * @version_info : Pointer to store the version details. - * - * Return: Nothing - *****************************************************************************/ -void qdma_fetch_version_details(uint8_t is_vf, uint32_t version_reg_val, - struct qdma_hw_version_info *version_info); - - -#ifdef __cplusplus -} -#endif - -#endif /* QDMA_ACCESS_COMMON_H_ */ diff --git a/QDMA/windows/sys/libqdma/source/qdma_access/qdma_access_errors.h b/QDMA/windows/sys/libqdma/source/qdma_access/qdma_access_errors.h deleted file mode 100644 index f260bdb75..000000000 --- a/QDMA/windows/sys/libqdma/source/qdma_access/qdma_access_errors.h +++ /dev/null @@ -1,72 +0,0 @@ -/* - * Copyright (C) 2020 Xilinx, Inc - * - * Licensed under the Apache License, Version 2.0 (the "License"). You may - * not use this file except in compliance with the License. You may obtain - * a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - */ - -#ifndef __QDMA_ACCESS_ERRORS_H_ -#define __QDMA_ACCESS_ERRORS_H_ - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * DOC: QDMA common library error codes definitions - * - * Header file *qdma_access_errors.h* defines error codes for common library - */ - -struct err_code_map { - int acc_err_code; - int err_code; -}; - -#define QDMA_HW_ERR_NOT_DETECTED 1 - -enum qdma_access_error_codes { - QDMA_SUCCESS = 0, - QDMA_ERR_INV_PARAM, - QDMA_ERR_NO_MEM, - QDMA_ERR_HWACC_BUSY_TIMEOUT, - QDMA_ERR_HWACC_INV_CONFIG_BAR, - QDMA_ERR_HWACC_NO_PEND_LEGCY_INTR, - QDMA_ERR_HWACC_BAR_NOT_FOUND, - QDMA_ERR_HWACC_FEATURE_NOT_SUPPORTED, /* 7 */ - - QDMA_ERR_RM_RES_EXISTS, /* 8 */ - QDMA_ERR_RM_RES_NOT_EXISTS, - QDMA_ERR_RM_DEV_EXISTS, - QDMA_ERR_RM_DEV_NOT_EXISTS, - QDMA_ERR_RM_NO_QUEUES_LEFT, - QDMA_ERR_RM_QMAX_CONF_REJECTED, /* 13 */ - - QDMA_ERR_MBOX_FMAP_WR_FAILED, /* 14 */ - QDMA_ERR_MBOX_NUM_QUEUES, - QDMA_ERR_MBOX_INV_QID, - QDMA_ERR_MBOX_INV_RINGSZ, - QDMA_ERR_MBOX_INV_BUFSZ, - QDMA_ERR_MBOX_INV_CNTR_TH, - QDMA_ERR_MBOX_INV_TMR_TH, - QDMA_ERR_MBOX_INV_MSG, - QDMA_ERR_MBOX_SEND_BUSY, - QDMA_ERR_MBOX_NO_MSG_IN, - QDMA_ERR_MBOX_REG_READ_FAILED, - QDMA_ERR_MBOX_ALL_ZERO_MSG, /* 25 */ -}; - -#ifdef __cplusplus -} -#endif - -#endif /* __QDMA_ACCESS_ERRORS_H_ */ diff --git a/QDMA/windows/sys/libqdma/source/qdma_access/qdma_access_export.h b/QDMA/windows/sys/libqdma/source/qdma_access/qdma_access_export.h deleted file mode 100644 index 736af8733..000000000 --- a/QDMA/windows/sys/libqdma/source/qdma_access/qdma_access_export.h +++ /dev/null @@ -1,255 +0,0 @@ -/* - * Copyright (C) 2020 Xilinx, Inc - * - * Licensed under the Apache License, Version 2.0 (the "License"). You may - * not use this file except in compliance with the License. You may obtain - * a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - */ - -#ifndef __QDMA_ACCESS_EXPORT_H_ -#define __QDMA_ACCESS_EXPORT_H_ - -#ifdef __cplusplus -extern "C" { -#endif - -#include "qdma_platform_env.h" - -/** QDMA Global CSR array size */ -#define QDMA_GLOBAL_CSR_ARRAY_SZ 16 - -/** - * struct qdma_dev_attributes - QDMA device attributes - */ -struct qdma_dev_attributes { - /** @num_pfs - Num of PFs*/ - uint8_t num_pfs; - /** @num_qs - Num of Queues */ - uint16_t num_qs; - /** @flr_present - FLR resent or not? */ - uint8_t flr_present:1; - /** @st_en - ST mode supported or not? */ - uint8_t st_en:1; - /** @mm_en - MM mode supported or not? */ - uint8_t mm_en:1; - /** @mm_cmpt_en - MM with Completions supported or not? */ - uint8_t mm_cmpt_en:1; - /** @mailbox_en - Mailbox supported or not? */ - uint8_t mailbox_en:1; - /** @debug_mode - Debug mode is enabled/disabled for IP */ - uint8_t debug_mode:1; - /** @desc_eng_mode - Descriptor Engine mode: - * Internal only/Bypass only/Internal & Bypass - */ - uint8_t desc_eng_mode:2; - /** @mm_channel_max - Num of MM channels */ - uint8_t mm_channel_max; - - /** Below are the list of HW features which are populated by qdma_access - * based on RTL version - */ - /** @qid2vec_ctx - To indicate support of qid2vec context */ - uint8_t qid2vec_ctx:1; - /** @cmpt_ovf_chk_dis - To indicate support of overflow check - * disable in CMPT ring - */ - uint8_t cmpt_ovf_chk_dis:1; - /** @mailbox_intr - To indicate support of mailbox interrupt */ - uint8_t mailbox_intr:1; - /** @sw_desc_64b - To indicate support of 64 bytes C2H/H2C - * descriptor format - */ - uint8_t sw_desc_64b:1; - /** @cmpt_desc_64b - To indicate support of 64 bytes CMPT - * descriptor format - */ - uint8_t cmpt_desc_64b:1; - /** @dynamic_bar - To indicate support of dynamic bar detection */ - uint8_t dynamic_bar:1; - /** @legacy_intr - To indicate support of legacy interrupt */ - uint8_t legacy_intr:1; - /** @cmpt_trig_count_timer - To indicate support of counter + timer - * trigger mode - */ - uint8_t cmpt_trig_count_timer:1; -}; - -/** qdma_dev_attributes structure size */ -#define QDMA_DEV_ATTR_STRUCT_SIZE (sizeof(struct qdma_dev_attributes)) - -/** global_csr_conf structure size */ -#define QDMA_DEV_GLOBAL_CSR_STRUCT_SIZE (sizeof(struct global_csr_conf)) - -/** - * enum qdma_dev_type - To hold qdma device type - */ -enum qdma_dev_type { - QDMA_DEV_PF, - QDMA_DEV_VF -}; - -/** - * enum qdma_dev_q_type: Q type - */ -enum qdma_dev_q_type { - /** @QDMA_DEV_Q_TYPE_H2C: H2C Q */ - QDMA_DEV_Q_TYPE_H2C, - /** @QDMA_DEV_Q_TYPE_C2H: C2H Q */ - QDMA_DEV_Q_TYPE_C2H, - /** @QDMA_DEV_Q_TYPE_CMPT: CMPT Q */ - QDMA_DEV_Q_TYPE_CMPT, - /** @QDMA_DEV_Q_TYPE_MAX: Total Q types */ - QDMA_DEV_Q_TYPE_MAX -}; - -/** - * @enum qdma_desc_size - QDMA queue descriptor size - */ -enum qdma_desc_size { - /** @QDMA_DESC_SIZE_8B - 8 byte descriptor */ - QDMA_DESC_SIZE_8B, - /** @QDMA_DESC_SIZE_16B - 16 byte descriptor */ - QDMA_DESC_SIZE_16B, - /** @QDMA_DESC_SIZE_32B - 32 byte descriptor */ - QDMA_DESC_SIZE_32B, - /** @QDMA_DESC_SIZE_64B - 64 byte descriptor */ - QDMA_DESC_SIZE_64B -}; - -/** - * @enum qdma_cmpt_update_trig_mode - Interrupt and Completion status write - * trigger mode - */ -enum qdma_cmpt_update_trig_mode { - /** @QDMA_CMPT_UPDATE_TRIG_MODE_DIS - disabled */ - QDMA_CMPT_UPDATE_TRIG_MODE_DIS, - /** @QDMA_CMPT_UPDATE_TRIG_MODE_EVERY - every */ - QDMA_CMPT_UPDATE_TRIG_MODE_EVERY, - /** @QDMA_CMPT_UPDATE_TRIG_MODE_USR_CNT - user counter */ - QDMA_CMPT_UPDATE_TRIG_MODE_USR_CNT, - /** @QDMA_CMPT_UPDATE_TRIG_MODE_USR - user */ - QDMA_CMPT_UPDATE_TRIG_MODE_USR, - /** @QDMA_CMPT_UPDATE_TRIG_MODE_USR_TMR - user timer */ - QDMA_CMPT_UPDATE_TRIG_MODE_USR_TMR, - /** @QDMA_CMPT_UPDATE_TRIG_MODE_TMR_CNTR - timer + counter combo */ - QDMA_CMPT_UPDATE_TRIG_MODE_TMR_CNTR -}; - - -/** - * @enum qdma_indirect_intr_ring_size - Indirect interrupt ring size - */ -enum qdma_indirect_intr_ring_size { - /** @QDMA_INDIRECT_INTR_RING_SIZE_4KB - Accommodates 512 entries */ - QDMA_INDIRECT_INTR_RING_SIZE_4KB, - /** @QDMA_INDIRECT_INTR_RING_SIZE_8KB - Accommodates 1024 entries */ - QDMA_INDIRECT_INTR_RING_SIZE_8KB, - /** @QDMA_INDIRECT_INTR_RING_SIZE_12KB - Accommodates 1536 entries */ - QDMA_INDIRECT_INTR_RING_SIZE_12KB, - /** @QDMA_INDIRECT_INTR_RING_SIZE_16KB - Accommodates 2048 entries */ - QDMA_INDIRECT_INTR_RING_SIZE_16KB, - /** @QDMA_INDIRECT_INTR_RING_SIZE_20KB - Accommodates 2560 entries */ - QDMA_INDIRECT_INTR_RING_SIZE_20KB, - /** @QDMA_INDIRECT_INTR_RING_SIZE_24KB - Accommodates 3072 entries */ - QDMA_INDIRECT_INTR_RING_SIZE_24KB, - /** @QDMA_INDIRECT_INTR_RING_SIZE_28KB - Accommodates 3584 entries */ - QDMA_INDIRECT_INTR_RING_SIZE_28KB, - /** @QDMA_INDIRECT_INTR_RING_SIZE_32KB - Accommodates 4096 entries */ - QDMA_INDIRECT_INTR_RING_SIZE_32KB -}; - -/** - * @enum qdma_wrb_interval - writeback update interval - */ -enum qdma_wrb_interval { - /** @QDMA_WRB_INTERVAL_4 - writeback update interval of 4 */ - QDMA_WRB_INTERVAL_4, - /** @QDMA_WRB_INTERVAL_8 - writeback update interval of 8 */ - QDMA_WRB_INTERVAL_8, - /** @QDMA_WRB_INTERVAL_16 - writeback update interval of 16 */ - QDMA_WRB_INTERVAL_16, - /** @QDMA_WRB_INTERVAL_32 - writeback update interval of 32 */ - QDMA_WRB_INTERVAL_32, - /** @QDMA_WRB_INTERVAL_64 - writeback update interval of 64 */ - QDMA_WRB_INTERVAL_64, - /** @QDMA_WRB_INTERVAL_128 - writeback update interval of 128 */ - QDMA_WRB_INTERVAL_128, - /** @QDMA_WRB_INTERVAL_256 - writeback update interval of 256 */ - QDMA_WRB_INTERVAL_256, - /** @QDMA_WRB_INTERVAL_512 - writeback update interval of 512 */ - QDMA_WRB_INTERVAL_512, - /** @QDMA_NUM_WRB_INTERVALS - total number of writeback intervals */ - QDMA_NUM_WRB_INTERVALS -}; - -enum qdma_rtl_version { - /** @QDMA_RTL_BASE - RTL Base */ - QDMA_RTL_BASE, - /** @QDMA_RTL_PATCH - RTL Patch */ - QDMA_RTL_PATCH, - /** @QDMA_RTL_NONE - Not a valid RTL version */ - QDMA_RTL_NONE, -}; - -enum qdma_vivado_release_id { - /** @QDMA_VIVADO_2018_3 - Vivado version 2018.3 */ - QDMA_VIVADO_2018_3, - /** @QDMA_VIVADO_2019_1 - Vivado version 2019.1 */ - QDMA_VIVADO_2019_1, - /** @QDMA_VIVADO_2019_2 - Vivado version 2019.2 */ - QDMA_VIVADO_2019_2, - /** @QDMA_VIVADO_2020_1 - Vivado version 2020.1 */ - QDMA_VIVADO_2020_1, - /** @QDMA_VIVADO_2020_2 - Vivado version 2020.2 */ - QDMA_VIVADO_2020_2, - /** @QDMA_VIVADO_NONE - Not a valid Vivado version*/ - QDMA_VIVADO_NONE -}; - -enum qdma_ip_type { - /** @QDMA_VERSAL_HARD_IP - Hard IP */ - QDMA_VERSAL_HARD_IP, - /** @QDMA_VERSAL_SOFT_IP - Soft IP */ - QDMA_VERSAL_SOFT_IP, - /** @QDMA_SOFT_IP - Hard IP */ - QDMA_SOFT_IP, - /** @EQDMA_SOFT_IP - Soft IP */ - EQDMA_SOFT_IP, - /** @QDMA_VERSAL_NONE - Not versal device */ - QDMA_NONE_IP -}; - - -enum qdma_device_type { - /** @QDMA_DEVICE_SOFT - UltraScale+ IP's */ - QDMA_DEVICE_SOFT, - /** @QDMA_DEVICE_VERSAL -VERSAL IP */ - QDMA_DEVICE_VERSAL, - /** @QDMA_DEVICE_NONE - Not a valid device */ - QDMA_DEVICE_NONE -}; - -enum qdma_desc_eng_mode { - /** @QDMA_DESC_ENG_INTERNAL_BYPASS - Internal and Bypass mode */ - QDMA_DESC_ENG_INTERNAL_BYPASS, - /** @QDMA_DESC_ENG_BYPASS_ONLY - Only Bypass mode */ - QDMA_DESC_ENG_BYPASS_ONLY, - /** @QDMA_DESC_ENG_INTERNAL_ONLY - Only Internal mode */ - QDMA_DESC_ENG_INTERNAL_ONLY, - /** @QDMA_DESC_ENG_MODE_MAX - Max of desc engine modes */ - QDMA_DESC_ENG_MODE_MAX -}; - -#ifdef __cplusplus -} -#endif - -#endif /* __QDMA_ACCESS_EXPORT_H_ */ diff --git a/QDMA/windows/sys/libqdma/source/qdma_access/qdma_access_version.h b/QDMA/windows/sys/libqdma/source/qdma_access/qdma_access_version.h deleted file mode 100644 index 9b6d4422c..000000000 --- a/QDMA/windows/sys/libqdma/source/qdma_access/qdma_access_version.h +++ /dev/null @@ -1,36 +0,0 @@ -/* - * Copyright (C) 2020 Xilinx, Inc - * - * Licensed under the Apache License, Version 2.0 (the "License"). You may - * not use this file except in compliance with the License. You may obtain - * a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - */ - -#ifndef __QDMA_ACCESS_VERSION_H_ -#define __QDMA_ACCESS_VERSION_H_ - - -#define QDMA_VERSION_MAJOR 2020 -#define QDMA_VERSION_MINOR 2 -#define QDMA_VERSION_PATCH 0 - -#define QDMA_VERSION_STR \ - __stringify(QDMA_VERSION_MAJOR) "." \ - __stringify(QDMA_VERSION_MINOR) "." \ - __stringify(QDMA_VERSION_PATCH) - -#define QDMA_VERSION \ - ((QDMA_VERSION_MAJOR)*1000 + \ - (QDMA_VERSION_MINOR)*100 + \ - QDMA_VERSION_PATCH) - - -#endif /* __QDMA_ACCESS_VERSION_H_ */ diff --git a/QDMA/windows/sys/libqdma/source/qdma_access/qdma_list.c b/QDMA/windows/sys/libqdma/source/qdma_access/qdma_list.c deleted file mode 100644 index 46691a882..000000000 --- a/QDMA/windows/sys/libqdma/source/qdma_access/qdma_list.c +++ /dev/null @@ -1,61 +0,0 @@ -/* - * Copyright (C) 2020 Xilinx, Inc - * - * Licensed under the Apache License, Version 2.0 (the "License"). You may - * not use this file except in compliance with the License. You may obtain - * a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - */ - -#include "qdma_list.h" - -void qdma_list_init_head(struct qdma_list_head *head) -{ - if (head) - head->prev = head->next = head; -} - -void qdma_list_add_tail(struct qdma_list_head *node, - struct qdma_list_head *head) -{ - head->prev->next = node; - node->next = head; - node->prev = head->prev; - head->prev = node; -} - -void qdma_list_insert_before(struct qdma_list_head *new_node, - struct qdma_list_head *node) -{ - node->prev->next = new_node; - new_node->prev = node->prev; - new_node->next = node; - node->prev = new_node; -} - -void qdma_list_insert_after(struct qdma_list_head *new_node, - struct qdma_list_head *node) -{ - new_node->prev = node; - new_node->next = node->next; - node->next->prev = new_node; - node->next = new_node; -} - - -void qdma_list_del(struct qdma_list_head *node) -{ - if (node) { - if (node->prev) - node->prev->next = node->next; - if (node->next) - node->next->prev = node->prev; - } -} diff --git a/QDMA/windows/sys/libqdma/source/qdma_access/qdma_list.h b/QDMA/windows/sys/libqdma/source/qdma_access/qdma_list.h deleted file mode 100644 index f6a59c89c..000000000 --- a/QDMA/windows/sys/libqdma/source/qdma_access/qdma_list.h +++ /dev/null @@ -1,125 +0,0 @@ -/* - * Copyright (C) 2020 Xilinx, Inc - * - * Licensed under the Apache License, Version 2.0 (the "License"). You may - * not use this file except in compliance with the License. You may obtain - * a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - */ - -#ifndef __QDMA_LIST_H_ -#define __QDMA_LIST_H_ - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * DOC: QDMA common library provided list implementation definitions - * - * Header file *qdma_list.h* defines APIs for creating and managing list. - */ - -/** - * struct qdma_list_head - data type for creating a list node - */ -struct qdma_list_head { - struct qdma_list_head *prev; - struct qdma_list_head *next; - void *priv; -}; - -#define QDMA_LIST_HEAD_INIT(name) { &(name), &(name), NULL } - -#define QDMA_LIST_HEAD(name) \ - struct qdma_list_head name = QDMA_LIST_HEAD_INIT(name) - -#define QDMA_LIST_GET_DATA(node) (node->priv) -#define QDMA_LIST_SET_DATA(node, data) ((node)->priv = data) - - -#define qdma_list_for_each_safe(pos, n, head) \ - for (pos = (head)->next, n = pos->next; pos != (head); \ - pos = n, n = pos->next) - - -#define qdma_list_is_last_entry(entry, head) ((entry)->next == (head)) - -#define qdma_list_is_empty(head) ((head)->next == (head)) - -/*****************************************************************************/ -/** - * qdma_list_init_head(): Init the list head - * - * @head: head of the list - * - * Return: None - *****************************************************************************/ -void qdma_list_init_head(struct qdma_list_head *head); - -/*****************************************************************************/ -/** - * qdma_list_add_tail(): add the given @node at the end of the list with @head - * - * @node: new entry which has to be added at the end of the list with @head - * @head: head of the list - * - * This API needs to be called with holding the lock to the list - * - * Return: None - *****************************************************************************/ -void qdma_list_add_tail(struct qdma_list_head *node, - struct qdma_list_head *head); - -/*****************************************************************************/ -/** - * qdma_list_insert_before(): add the given @node at the before a @node - * - * @new_node: new entry which has to be added before @node - * @node: reference node in the list - * - * This API needs to be called with holding the lock to the list - * - * Return: None - *****************************************************************************/ -void qdma_list_insert_before(struct qdma_list_head *new_node, - struct qdma_list_head *node); - -/*****************************************************************************/ -/** - * qdma_list_insert_after(): add the given @node at the after a @node - * - * @new_node: new entry which has to be added after @node - * @node: reference node in the list - * - * This API needs to be called with holding the lock to the list - * - * Return: None - *****************************************************************************/ -void qdma_list_insert_after(struct qdma_list_head *new_node, - struct qdma_list_head *node); - -/*****************************************************************************/ -/** - * qdma_list_del(): delete an node from the list - * - * @node: node in a list - * - * This API needs to be called with holding the lock to the list - * - * Return: None - *****************************************************************************/ -void qdma_list_del(struct qdma_list_head *node); - -#ifdef __cplusplus -} -#endif - -#endif /* __QDMA_LIST_H_ */ diff --git a/QDMA/windows/sys/libqdma/source/qdma_access/qdma_platform.h b/QDMA/windows/sys/libqdma/source/qdma_access/qdma_platform.h deleted file mode 100644 index cd7d64d8a..000000000 --- a/QDMA/windows/sys/libqdma/source/qdma_access/qdma_platform.h +++ /dev/null @@ -1,168 +0,0 @@ -/* - * Copyright (C) 2020 Xilinx, Inc - * - * Licensed under the Apache License, Version 2.0 (the "License"). You may - * not use this file except in compliance with the License. You may obtain - * a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - */ - -#ifndef __QDMA_PLATFORM_H_ -#define __QDMA_PLATFORM_H_ - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * DOC: QDMA platform specific interface definitions - * - * Header file *qdma_platform_env.h* defines function signatures that are - * required to be implemented by platform specific drivers. - */ - -#include "qdma_access_common.h" - -/*****************************************************************************/ -/** - * qdma_calloc(): allocate memory and initialize with 0 - * - * @num_blocks: number of blocks of contiguous memory of @size - * @size: size of each chunk of memory - * - * Return: pointer to the memory block created on success and NULL on failure - *****************************************************************************/ -void *qdma_calloc(uint32_t num_blocks, uint32_t size); - -/*****************************************************************************/ -/** - * qdma_memfree(): free the memory - * - * @memptr: pointer to the memory block - * - * Return: None - *****************************************************************************/ -void qdma_memfree(void *memptr); - -/*****************************************************************************/ -/** - * qdma_resource_lock_init() - Init lock to access resource management APIs - * - * @return None - *****************************************************************************/ -int qdma_resource_lock_init(void); - -/*****************************************************************************/ -/** - * qdma_resource_lock_take() - take lock to access resource management APIs - * - * @return None - *****************************************************************************/ -void qdma_resource_lock_take(void); - -/*****************************************************************************/ -/** - * qdma_resource_lock_give() - release lock after accessing resource management - * APIs - * - * @return None - *****************************************************************************/ -void qdma_resource_lock_give(void); - -/*****************************************************************************/ -/** - * qdma_reg_write() - Register write API. - * - * @dev_hndl: device handle - * @reg_offst: QDMA Config bar register offset to write - * @val: value to be written - * - * Return: Nothing - *****************************************************************************/ -void qdma_reg_write(void *dev_hndl, uint32_t reg_offst, uint32_t val); - -/*****************************************************************************/ -/** - * qdma_reg_read() - Register read API. - * - * @dev_hndl: device handle - * @reg_offst: QDMA Config bar register offset to be read - * - * Return: Value read - *****************************************************************************/ -uint32_t qdma_reg_read(void *dev_hndl, uint32_t reg_offst); - -/*****************************************************************************/ -/** - * qdma_reg_access_lock() - Lock function for Register access - * - * @dev_hndl: device handle - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -int qdma_reg_access_lock(void *dev_hndl); - -/*****************************************************************************/ -/** - * qdma_reg_access_release() - Release function for Register access - * - * @dev_hndl: device handle - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -int qdma_reg_access_release(void *dev_hndl); - -/*****************************************************************************/ -/** - * qdma_udelay() - delay function to be used in the common library - * - * @delay_usec: delay in microseconds - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -void qdma_udelay(uint32_t delay_usec); - -/*****************************************************************************/ -/** - * qdma_get_hw_access() - function to get the qdma_hw_access - * - * @dev_hndl: device handle - * @dev_cap: pointer to hold qdma_hw_access structure - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -void qdma_get_hw_access(void *dev_hndl, struct qdma_hw_access **hw); - -/*****************************************************************************/ -/** - * qdma_strncpy(): copy n size string from source to destination buffer - * - * @memptr: pointer to the memory block - * - * Return: None - *****************************************************************************/ -void qdma_strncpy(char *dest, const char *src, size_t n); - - -/*****************************************************************************/ -/** - * qdma_get_err_code() - function to get the qdma access mapped error code - * - * @acc_err_code: qdma access error code - * - * Return: returns the platform specific error code - *****************************************************************************/ -int qdma_get_err_code(int acc_err_code); - -#ifdef __cplusplus -} -#endif - -#endif /* __QDMA_PLATFORM_H_ */ diff --git a/QDMA/windows/sys/libqdma/source/qdma_access/qdma_reg_dump.h b/QDMA/windows/sys/libqdma/source/qdma_access/qdma_reg_dump.h deleted file mode 100644 index 6ad7f70ab..000000000 --- a/QDMA/windows/sys/libqdma/source/qdma_access/qdma_reg_dump.h +++ /dev/null @@ -1,82 +0,0 @@ -/* - * Copyright (C) 2020 Xilinx, Inc - * - * Licensed under the Apache License, Version 2.0 (the "License"). You may - * not use this file except in compliance with the License. You may obtain - * a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - */ - -#ifndef __QDMA_REG_DUMP_H__ -#define __QDMA_REG_DUMP_H__ - -#ifdef __cplusplus -extern "C" { -#endif - -#include "qdma_platform_env.h" -#include "qdma_access_common.h" - -#define DEBUGFS_DEV_INFO_SZ (300) - -#define QDMA_REG_NAME_LENGTH 64 -#define DEBUGFS_INTR_CNTX_SZ (2048 * 2) -#define DBGFS_ERR_BUFLEN (64) -#define DEBGFS_LINE_SZ (81) -#define DEBGFS_GEN_NAME_SZ (40) -#define REG_DUMP_SIZE_PER_LINE (256) - -#define MAX_QDMA_CFG_REGS (200) - -#define QDMA_MM_EN_SHIFT 0 -#define QDMA_CMPT_EN_SHIFT 1 -#define QDMA_ST_EN_SHIFT 2 -#define QDMA_MAILBOX_EN_SHIFT 3 - -#define QDMA_MM_MODE (1 << QDMA_MM_EN_SHIFT) -#define QDMA_COMPLETION_MODE (1 << QDMA_CMPT_EN_SHIFT) -#define QDMA_ST_MODE (1 << QDMA_ST_EN_SHIFT) -#define QDMA_MAILBOX (1 << QDMA_MAILBOX_EN_SHIFT) - - -#define QDMA_MM_ST_MODE \ - (QDMA_MM_MODE | QDMA_COMPLETION_MODE | QDMA_ST_MODE) - -#define GET_CAPABILITY_MASK(mm_en, st_en, mm_cmpt_en, mailbox_en) \ - ((mm_en << QDMA_MM_EN_SHIFT) | \ - ((mm_cmpt_en | st_en) << QDMA_CMPT_EN_SHIFT) | \ - (st_en << QDMA_ST_EN_SHIFT) | \ - (mailbox_en << QDMA_MAILBOX_EN_SHIFT)) - - -struct regfield_info { - const char *field_name; - uint32_t field_mask; -}; - -struct xreg_info { - const char *name; - uint32_t addr; - uint32_t repeat; - uint32_t step; - uint8_t shift; - uint8_t len; - uint8_t is_debug_reg; - uint8_t mode; - uint8_t read_type; - uint8_t num_bitfields; - struct regfield_info *bitfields; -}; - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/QDMA/windows/sys/libqdma/source/qdma_access/qdma_resource_mgmt.c b/QDMA/windows/sys/libqdma/source/qdma_access/qdma_resource_mgmt.c deleted file mode 100644 index 3cb7967d4..000000000 --- a/QDMA/windows/sys/libqdma/source/qdma_access/qdma_resource_mgmt.c +++ /dev/null @@ -1,794 +0,0 @@ -/* - * Copyright (C) 2020 Xilinx, Inc - * - * Licensed under the Apache License, Version 2.0 (the "License"). You may - * not use this file except in compliance with the License. You may obtain - * a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - */ - -#include "qdma_resource_mgmt.h" -#include "qdma_platform.h" -#include "qdma_list.h" -#include "qdma_access_errors.h" - -#ifdef ENABLE_WPP_TRACING -#include "qdma_resource_mgmt.tmh" -#endif - -struct qdma_resource_entry { - int qbase; - uint32_t total_q; - struct qdma_list_head node; -}; - -/** per function entry */ -struct qdma_dev_entry { - uint16_t func_id; - uint32_t active_h2c_qcnt; - uint32_t active_c2h_qcnt; - uint32_t active_cmpt_qcnt; - struct qdma_resource_entry entry; -}; - -/** for hodling the qconf_entry structure */ -struct qdma_resource_master { - /** DMA device index this resource belongs to */ - uint32_t dma_device_index; - /** starting pci bus number this resource belongs to */ - uint32_t pci_bus_start; - /** ending pci bus number this resource belongs to */ - uint32_t pci_bus_end; - /** total queue this resource manager handles */ - uint32_t total_q; - /** queue base from which this resource manger handles */ - int qbase; - /** for attaching to master resource list */ - struct qdma_list_head node; - /** for holding device entries */ - struct qdma_list_head dev_list; - /** for holding free resource list */ - struct qdma_list_head free_list; - /** active queue count per resource*/ - uint32_t active_qcnt; -}; - -static QDMA_LIST_HEAD(master_resource_list); - -static struct qdma_resource_master *qdma_find_master_resource_entry( - uint32_t bus_start, uint32_t bus_end) -{ - struct qdma_list_head *entry, *tmp; - - qdma_resource_lock_take(); - qdma_list_for_each_safe(entry, tmp, &master_resource_list) { - struct qdma_resource_master *q_resource = - (struct qdma_resource_master *) - QDMA_LIST_GET_DATA(entry); - - if (q_resource->pci_bus_start == bus_start && - q_resource->pci_bus_end == bus_end) { - qdma_resource_lock_give(); - return q_resource; - } - } - qdma_resource_lock_give(); - - return NULL; -} - -static struct qdma_resource_master *qdma_get_master_resource_entry( - uint32_t dma_device_index) -{ - struct qdma_list_head *entry, *tmp; - - qdma_resource_lock_take(); - qdma_list_for_each_safe(entry, tmp, &master_resource_list) { - struct qdma_resource_master *q_resource = - (struct qdma_resource_master *) - QDMA_LIST_GET_DATA(entry); - - if (q_resource->dma_device_index == dma_device_index) { - qdma_resource_lock_give(); - return q_resource; - } - } - qdma_resource_lock_give(); - - return NULL; -} - -static struct qdma_dev_entry *qdma_get_dev_entry(uint32_t dma_device_index, - uint16_t func_id) -{ - struct qdma_list_head *entry, *tmp; - struct qdma_resource_master *q_resource = - qdma_get_master_resource_entry(dma_device_index); - - if (!q_resource) - return NULL; - - qdma_resource_lock_take(); - qdma_list_for_each_safe(entry, tmp, &q_resource->dev_list) { - struct qdma_dev_entry *dev_entry = (struct qdma_dev_entry *) - QDMA_LIST_GET_DATA(entry); - - if (dev_entry->func_id == func_id) { - qdma_resource_lock_give(); - return dev_entry; - } - } - qdma_resource_lock_give(); - - return NULL; -} - -static struct qdma_resource_entry *qdma_free_entry_create(int q_base, - uint32_t total_q) -{ - struct qdma_resource_entry *entry = (struct qdma_resource_entry *) - qdma_calloc(1, sizeof(struct qdma_resource_master)); - if (entry == NULL) - return NULL; - - entry->total_q = total_q; - entry->qbase = q_base; - - return entry; -} - -static void qdma_submit_to_free_list(struct qdma_dev_entry *dev_entry, - struct qdma_list_head *head) -{ - struct qdma_resource_entry *streach_node = NULL; - struct qdma_list_head *entry, *tmp; - /* create a new node to be added to empty free list */ - struct qdma_resource_entry *new_node = NULL; - - if (!dev_entry->entry.total_q) - return; - - if (qdma_list_is_empty(head)) { - new_node = qdma_free_entry_create(dev_entry->entry.qbase, - dev_entry->entry.total_q); - if (new_node == NULL) - return; - QDMA_LIST_SET_DATA(&new_node->node, new_node); - qdma_list_add_tail(&new_node->node, head); - /* reset device entry q resource params */ - dev_entry->entry.qbase = -1; - dev_entry->entry.total_q = 0; - } else { - qdma_list_for_each_safe(entry, tmp, head) { - struct qdma_resource_entry *node = - (struct qdma_resource_entry *) - QDMA_LIST_GET_DATA(entry); - - /* insert the free slot at appropriate place */ - if ((node->qbase > dev_entry->entry.qbase) || - qdma_list_is_last_entry(entry, head)) { - new_node = qdma_free_entry_create( - dev_entry->entry.qbase, - dev_entry->entry.total_q); - if (new_node == NULL) - return; - QDMA_LIST_SET_DATA(&new_node->node, new_node); - if (node->qbase > dev_entry->entry.qbase) - qdma_list_insert_before(&new_node->node, - &node->node); - else - qdma_list_add_tail(&new_node->node, - head); - /* reset device entry q resource params */ - dev_entry->entry.qbase = -1; - dev_entry->entry.total_q = 0; - break; - } - } - } - - /* de-fragment (merge contiguous resource chunks) if possible */ - qdma_list_for_each_safe(entry, tmp, head) { - struct qdma_resource_entry *node = - (struct qdma_resource_entry *)QDMA_LIST_GET_DATA(entry); - - if (!streach_node) - streach_node = node; - else { - if ((streach_node->qbase + streach_node->total_q) == - (uint32_t)node->qbase) { - streach_node->total_q += node->total_q; - qdma_list_del(&node->node); - qdma_memfree(node); - } else - streach_node = node; - } - } -} - -/** - * qdma_resource_entry() - return the best free list entry node that can - * accommodate the new request - */ -static struct qdma_resource_entry *qdma_get_resource_node(uint32_t qmax, - int qbase, - struct qdma_list_head *free_list_head) -{ - struct qdma_list_head *entry, *tmp; - struct qdma_resource_entry *best_fit_node = NULL; - - /* try to honor requested qbase */ - if (qbase >= 0) { - qdma_list_for_each_safe(entry, tmp, free_list_head) { - struct qdma_resource_entry *node = - (struct qdma_resource_entry *)QDMA_LIST_GET_DATA(entry); - - if ((qbase >= node->qbase) && - (node->qbase + node->total_q) >= - (qbase + qmax)) { - best_fit_node = node; - goto fragment_free_list; - } - } - } - best_fit_node = NULL; - - /* find a best node to accommodate q resource request */ - qdma_list_for_each_safe(entry, tmp, free_list_head) { - struct qdma_resource_entry *node = - (struct qdma_resource_entry *)QDMA_LIST_GET_DATA(entry); - - if (node->total_q >= qmax) { - if (!best_fit_node || (best_fit_node->total_q >= - node->total_q)) { - best_fit_node = node; - qbase = best_fit_node->qbase; - } - } - } - -fragment_free_list: - if (!best_fit_node) - return NULL; - - if ((qbase == best_fit_node->qbase) && - (qmax == best_fit_node->total_q)) - return best_fit_node; - - /* split free resource node accordingly */ - if ((qbase == best_fit_node->qbase) && - (qmax != best_fit_node->total_q)) { - /* - * create an extra node to hold the extra queues from this node - */ - struct qdma_resource_entry *new_entry = NULL; - int lqbase = best_fit_node->qbase + qmax; - uint32_t lqmax = best_fit_node->total_q - qmax; - - new_entry = qdma_free_entry_create(lqbase, lqmax); - if (new_entry == NULL) - return NULL; - QDMA_LIST_SET_DATA(&new_entry->node, new_entry); - qdma_list_insert_after(&new_entry->node, - &best_fit_node->node); - best_fit_node->total_q -= lqmax; - } else if ((qbase > best_fit_node->qbase) && - ((qbase + qmax) == (best_fit_node->qbase + - best_fit_node->total_q))) { - /* - * create an extra node to hold the extra queues from this node - */ - struct qdma_resource_entry *new_entry = NULL; - int lqbase = best_fit_node->qbase; - uint32_t lqmax = qbase - best_fit_node->qbase; - - new_entry = qdma_free_entry_create(lqbase, lqmax); - if (new_entry == NULL) - return NULL; - QDMA_LIST_SET_DATA(&new_entry->node, new_entry); - qdma_list_insert_before(&new_entry->node, - &best_fit_node->node); - best_fit_node->total_q = qmax; - best_fit_node->qbase = qbase; - } else { - /* - * create two extra node to hold the extra queues from this node - */ - struct qdma_resource_entry *new_entry = NULL; - int lqbase = best_fit_node->qbase; - uint32_t lqmax = qbase - best_fit_node->qbase; - - new_entry = qdma_free_entry_create(lqbase, lqmax); - if (new_entry == NULL) - return NULL; - QDMA_LIST_SET_DATA(&new_entry->node, new_entry); - qdma_list_insert_before(&new_entry->node, - &best_fit_node->node); - - best_fit_node->qbase = qbase; - best_fit_node->total_q -= lqmax; - - lqbase = best_fit_node->qbase + qmax; - lqmax = best_fit_node->total_q - qmax; - - new_entry = qdma_free_entry_create(lqbase, lqmax); - if (new_entry == NULL) - return NULL; - QDMA_LIST_SET_DATA(&new_entry->node, new_entry); - qdma_list_insert_after(&new_entry->node, - &best_fit_node->node); - best_fit_node->total_q = qmax; - } - - return best_fit_node; -} - -static int qdma_request_q_resource(struct qdma_dev_entry *dev_entry, - uint32_t new_qmax, int new_qbase, - struct qdma_list_head *free_list_head) -{ - uint32_t qmax = dev_entry->entry.total_q; - int qbase = dev_entry->entry.qbase; - struct qdma_resource_entry *free_entry_node = NULL; - int rv = QDMA_SUCCESS; - - /* submit already allocated queues back to free list before requesting - * new resource - */ - qdma_submit_to_free_list(dev_entry, free_list_head); - - if (!new_qmax) - return 0; - /* check if the request can be accomodated */ - free_entry_node = qdma_get_resource_node(new_qmax, new_qbase, - free_list_head); - if (free_entry_node == NULL) { - /* request cannot be accommodated. Restore the dev_entry */ - free_entry_node = qdma_get_resource_node(qmax, qbase, - free_list_head); - rv = -QDMA_ERR_RM_NO_QUEUES_LEFT; - qdma_log_error("%s: Not enough queues, err:%d\n", __func__, - -QDMA_ERR_RM_NO_QUEUES_LEFT); - if (free_entry_node == NULL) { - dev_entry->entry.qbase = -1; - dev_entry->entry.total_q = 0; - - return rv; - } - } - - dev_entry->entry.qbase = free_entry_node->qbase; - dev_entry->entry.total_q = free_entry_node->total_q; - - qdma_list_del(&free_entry_node->node); - qdma_memfree(free_entry_node); - - return rv; -} - -int qdma_master_resource_create(uint32_t bus_start, uint32_t bus_end, - int q_base, uint32_t total_q, uint32_t *dma_device_index) -{ - struct qdma_resource_master *q_resource; - struct qdma_resource_entry *free_entry; - static int index; - - q_resource = qdma_find_master_resource_entry(bus_start, bus_end); - if (q_resource) { - *dma_device_index = q_resource->dma_device_index; - qdma_log_debug("%s: Resource already created", __func__); - qdma_log_debug("for this device(%d)\n", - q_resource->dma_device_index); - return -QDMA_ERR_RM_RES_EXISTS; - } - - *dma_device_index = index; - - q_resource = (struct qdma_resource_master *)qdma_calloc(1, - sizeof(struct qdma_resource_master)); - if (!q_resource) { - qdma_log_error("%s: no memory for q_resource, err:%d\n", - __func__, - -QDMA_ERR_NO_MEM); - return -QDMA_ERR_NO_MEM; - } - - free_entry = (struct qdma_resource_entry *) - qdma_calloc(1, sizeof(struct qdma_resource_entry)); - if (!free_entry) { - qdma_memfree(q_resource); - qdma_log_error("%s: no memory for free_entry, err:%d\n", - __func__, - -QDMA_ERR_NO_MEM); - return -QDMA_ERR_NO_MEM; - } - - qdma_resource_lock_take(); - q_resource->dma_device_index = index; - q_resource->pci_bus_start = bus_start; - q_resource->pci_bus_end = bus_end; - q_resource->total_q = total_q; - q_resource->qbase = q_base; - qdma_list_init_head(&q_resource->dev_list); - qdma_list_init_head(&q_resource->free_list); - QDMA_LIST_SET_DATA(&q_resource->node, q_resource); - QDMA_LIST_SET_DATA(&q_resource->free_list, q_resource); - qdma_list_add_tail(&q_resource->node, &master_resource_list); - - - free_entry->total_q = total_q; - free_entry->qbase = q_base; - QDMA_LIST_SET_DATA(&free_entry->node, free_entry); - qdma_list_add_tail(&free_entry->node, &q_resource->free_list); - qdma_resource_lock_give(); - - qdma_log_debug("%s: New master resource created at %d", - __func__, index); - ++index; - - return QDMA_SUCCESS; -} - -void qdma_master_resource_destroy(uint32_t dma_device_index) -{ - struct qdma_resource_master *q_resource = - qdma_get_master_resource_entry(dma_device_index); - struct qdma_list_head *entry, *tmp; - - if (!q_resource) - return; - qdma_resource_lock_take(); - if (!qdma_list_is_empty(&q_resource->dev_list)) { - qdma_resource_lock_give(); - return; - } - qdma_list_for_each_safe(entry, tmp, &q_resource->free_list) { - struct qdma_resource_entry *free_entry = - (struct qdma_resource_entry *) - QDMA_LIST_GET_DATA(entry); - - qdma_list_del(&free_entry->node); - qdma_memfree(free_entry); - } - qdma_list_del(&q_resource->node); - qdma_memfree(q_resource); - qdma_resource_lock_give(); -} - - -int qdma_dev_entry_create(uint32_t dma_device_index, uint16_t func_id) -{ - struct qdma_resource_master *q_resource = - qdma_get_master_resource_entry(dma_device_index); - struct qdma_dev_entry *dev_entry; - - if (!q_resource) { - qdma_log_error("%s: Queue resource not found, err: %d\n", - __func__, - -QDMA_ERR_RM_RES_NOT_EXISTS); - return -QDMA_ERR_RM_RES_NOT_EXISTS; - } - - dev_entry = qdma_get_dev_entry(dma_device_index, func_id); - if (!dev_entry) { - qdma_resource_lock_take(); - dev_entry = (struct qdma_dev_entry *) - qdma_calloc(1, sizeof(struct qdma_dev_entry)); - if (dev_entry == NULL) { - qdma_resource_lock_give(); - qdma_log_error("%s: Insufficient memory, err:%d\n", - __func__, - -QDMA_ERR_NO_MEM); - return -QDMA_ERR_NO_MEM; - } - dev_entry->func_id = func_id; - dev_entry->entry.qbase = -1; - dev_entry->entry.total_q = 0; - QDMA_LIST_SET_DATA(&dev_entry->entry.node, dev_entry); - qdma_list_add_tail(&dev_entry->entry.node, - &q_resource->dev_list); - qdma_resource_lock_give(); - qdma_log_info("%s: Created the dev entry successfully\n", - __func__); - } else { - qdma_log_error("%s: Dev entry already created, err = %d\n", - __func__, - -QDMA_ERR_RM_DEV_EXISTS); - return -QDMA_ERR_RM_DEV_EXISTS; - } - - return QDMA_SUCCESS; -} - -void qdma_dev_entry_destroy(uint32_t dma_device_index, uint16_t func_id) -{ - struct qdma_resource_master *q_resource = - qdma_get_master_resource_entry(dma_device_index); - struct qdma_dev_entry *dev_entry; - - if (!q_resource) { - qdma_log_error("%s: Queue resource not found.\n", __func__); - return; - } - - dev_entry = qdma_get_dev_entry(dma_device_index, func_id); - if (!dev_entry) { - qdma_log_error("%s: Dev entry not found\n", __func__); - return; - } - qdma_resource_lock_take(); - qdma_submit_to_free_list(dev_entry, &q_resource->free_list); - - qdma_list_del(&dev_entry->entry.node); - qdma_memfree(dev_entry); - qdma_resource_lock_give(); -} - -int qdma_dev_update(uint32_t dma_device_index, uint16_t func_id, - uint32_t qmax, int *qbase) -{ - struct qdma_resource_master *q_resource = - qdma_get_master_resource_entry(dma_device_index); - struct qdma_dev_entry *dev_entry; - int rv; - - if (!q_resource) { - qdma_log_error("%s: Queue resource not found, err: %d\n", - __func__, -QDMA_ERR_RM_RES_NOT_EXISTS); - return -QDMA_ERR_RM_RES_NOT_EXISTS; - } - - dev_entry = qdma_get_dev_entry(dma_device_index, func_id); - - if (!dev_entry) { - qdma_log_error("%s: Dev Entry not found, err: %d\n", - __func__, - -QDMA_ERR_RM_DEV_NOT_EXISTS); - return -QDMA_ERR_RM_DEV_NOT_EXISTS; - } - - qdma_resource_lock_take(); - - /* if any active queue on device, no more new qmax - * configuration allowed - */ - if (dev_entry->active_h2c_qcnt || - dev_entry->active_c2h_qcnt || - dev_entry->active_cmpt_qcnt) { - qdma_resource_lock_give(); - qdma_log_error("%s: Qs active. Config blocked, err: %d\n", - __func__, -QDMA_ERR_RM_QMAX_CONF_REJECTED); - return -QDMA_ERR_RM_QMAX_CONF_REJECTED; - } - - rv = qdma_request_q_resource(dev_entry, qmax, *qbase, - &q_resource->free_list); - - *qbase = dev_entry->entry.qbase; - qdma_resource_lock_give(); - - - return rv; -} - -int qdma_dev_qinfo_get(uint32_t dma_device_index, uint16_t func_id, - int *qbase, uint32_t *qmax) -{ - struct qdma_resource_master *q_resource = - qdma_get_master_resource_entry(dma_device_index); - struct qdma_dev_entry *dev_entry; - - if (!q_resource) { - qdma_log_error("%s: Queue resource not found, err: %d\n", - __func__, -QDMA_ERR_RM_RES_NOT_EXISTS); - return -QDMA_ERR_RM_RES_NOT_EXISTS; - } - - dev_entry = qdma_get_dev_entry(dma_device_index, func_id); - - if (!dev_entry) { - qdma_log_debug("%s: Dev Entry not created yet\n", __func__); - return -QDMA_ERR_RM_DEV_NOT_EXISTS; - } - - qdma_resource_lock_take(); - *qbase = dev_entry->entry.qbase; - *qmax = dev_entry->entry.total_q; - qdma_resource_lock_give(); - - return QDMA_SUCCESS; -} - -enum qdma_dev_q_range qdma_dev_is_queue_in_range(uint32_t dma_device_index, - uint16_t func_id, - uint32_t qid_hw) -{ - struct qdma_resource_master *q_resource = - qdma_get_master_resource_entry(dma_device_index); - struct qdma_dev_entry *dev_entry; - uint32_t qmax; - - if (!q_resource) { - qdma_log_error("%s: Queue resource not found, err: %d\n", - __func__, -QDMA_ERR_RM_RES_NOT_EXISTS); - return QDMA_DEV_Q_OUT_OF_RANGE; - } - - dev_entry = qdma_get_dev_entry(dma_device_index, func_id); - - if (!dev_entry) { - qdma_log_error("%s: Dev entry not found, err: %d\n", - __func__, -QDMA_ERR_RM_DEV_NOT_EXISTS); - return QDMA_DEV_Q_OUT_OF_RANGE; - } - - qdma_resource_lock_take(); - qmax = dev_entry->entry.qbase + dev_entry->entry.total_q; - if (dev_entry->entry.total_q && (qid_hw < qmax) && - ((int)qid_hw >= dev_entry->entry.qbase)) { - qdma_resource_lock_give(); - return QDMA_DEV_Q_IN_RANGE; - } - qdma_resource_lock_give(); - - return QDMA_DEV_Q_OUT_OF_RANGE; -} - -int qdma_dev_increment_active_queue(uint32_t dma_device_index, uint16_t func_id, - enum qdma_dev_q_type q_type) -{ - struct qdma_resource_master *q_resource = - qdma_get_master_resource_entry(dma_device_index); - struct qdma_dev_entry *dev_entry; - int rv = QDMA_SUCCESS; - uint32_t *active_qcnt = NULL; - - if (!q_resource) { - qdma_log_error("%s: Queue resource not found, err: %d\n", - __func__, -QDMA_ERR_RM_RES_NOT_EXISTS); - return -QDMA_ERR_RM_RES_NOT_EXISTS; - } - - dev_entry = qdma_get_dev_entry(dma_device_index, func_id); - - if (!dev_entry) { - qdma_log_error("%s: Dev Entry not found, err: %d\n", - __func__, - -QDMA_ERR_RM_DEV_NOT_EXISTS); - return -QDMA_ERR_RM_DEV_NOT_EXISTS; - } - - qdma_resource_lock_take(); - switch (q_type) { - case QDMA_DEV_Q_TYPE_H2C: - active_qcnt = &dev_entry->active_h2c_qcnt; - break; - case QDMA_DEV_Q_TYPE_C2H: - active_qcnt = &dev_entry->active_c2h_qcnt; - break; - case QDMA_DEV_Q_TYPE_CMPT: - active_qcnt = &dev_entry->active_cmpt_qcnt; - break; - default: - rv = -QDMA_ERR_RM_DEV_NOT_EXISTS; - } - - if (active_qcnt && (dev_entry->entry.total_q < ((*active_qcnt) + 1))) { - qdma_resource_lock_give(); - return -QDMA_ERR_RM_NO_QUEUES_LEFT; - } - - if (active_qcnt) { - *active_qcnt = (*active_qcnt) + 1; - q_resource->active_qcnt++; - } - qdma_resource_lock_give(); - - return rv; -} - - -int qdma_dev_decrement_active_queue(uint32_t dma_device_index, uint16_t func_id, - enum qdma_dev_q_type q_type) -{ - struct qdma_resource_master *q_resource = - qdma_get_master_resource_entry(dma_device_index); - struct qdma_dev_entry *dev_entry; - int rv = QDMA_SUCCESS; - - if (!q_resource) { - qdma_log_error("%s: Queue resource not found, err: %d\n", - __func__, - -QDMA_ERR_RM_RES_NOT_EXISTS); - return -QDMA_ERR_RM_RES_NOT_EXISTS; - } - - dev_entry = qdma_get_dev_entry(dma_device_index, func_id); - - if (!dev_entry) { - qdma_log_error("%s: Dev entry not found, err: %d\n", - __func__, -QDMA_ERR_RM_DEV_NOT_EXISTS); - return -QDMA_ERR_RM_DEV_NOT_EXISTS; - } - - qdma_resource_lock_take(); - switch (q_type) { - case QDMA_DEV_Q_TYPE_H2C: - if (dev_entry->active_h2c_qcnt) - dev_entry->active_h2c_qcnt--; - break; - case QDMA_DEV_Q_TYPE_C2H: - if (dev_entry->active_c2h_qcnt) - dev_entry->active_c2h_qcnt--; - break; - case QDMA_DEV_Q_TYPE_CMPT: - if (dev_entry->active_cmpt_qcnt) - dev_entry->active_cmpt_qcnt--; - break; - default: - rv = -QDMA_ERR_RM_DEV_NOT_EXISTS; - } - q_resource->active_qcnt--; - qdma_resource_lock_give(); - - return rv; -} - -uint32_t qdma_get_active_queue_count(uint32_t dma_device_index) -{ - struct qdma_resource_master *q_resource = - qdma_get_master_resource_entry(dma_device_index); - uint32_t q_cnt; - - if (!q_resource) - return QDMA_SUCCESS; - - qdma_resource_lock_take(); - q_cnt = q_resource->active_qcnt; - qdma_resource_lock_give(); - - return q_cnt; -} - -int qdma_get_device_active_queue_count(uint32_t dma_device_index, - uint16_t func_id, - enum qdma_dev_q_type q_type) -{ - struct qdma_resource_master *q_resource = - qdma_get_master_resource_entry(dma_device_index); - struct qdma_dev_entry *dev_entry; - uint32_t dev_active_qcnt = 0; - - if (!q_resource) - return -QDMA_ERR_RM_RES_NOT_EXISTS; - - dev_entry = qdma_get_dev_entry(dma_device_index, func_id); - - if (!dev_entry) - return -QDMA_ERR_RM_DEV_NOT_EXISTS; - - qdma_resource_lock_take(); - switch (q_type) { - case QDMA_DEV_Q_TYPE_H2C: - dev_active_qcnt = dev_entry->active_h2c_qcnt; - break; - case QDMA_DEV_Q_TYPE_C2H: - dev_active_qcnt = dev_entry->active_c2h_qcnt; - break; - case QDMA_DEV_Q_TYPE_CMPT: - dev_active_qcnt = dev_entry->active_cmpt_qcnt; - break; - default: - dev_active_qcnt = 0; - } - qdma_resource_lock_give(); - - return dev_active_qcnt; -} diff --git a/QDMA/windows/sys/libqdma/source/qdma_access/qdma_resource_mgmt.h b/QDMA/windows/sys/libqdma/source/qdma_access/qdma_resource_mgmt.h deleted file mode 100644 index 436a77f9a..000000000 --- a/QDMA/windows/sys/libqdma/source/qdma_access/qdma_resource_mgmt.h +++ /dev/null @@ -1,213 +0,0 @@ -/* - * Copyright (C) 2020 Xilinx, Inc - * - * Licensed under the Apache License, Version 2.0 (the "License"). You may - * not use this file except in compliance with the License. You may obtain - * a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - */ - -#ifndef __QDMA_RESOURCE_MGMT_H_ -#define __QDMA_RESOURCE_MGMT_H_ - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * DOC: QDMA resource management interface definitions - * - * Header file *qdma_resource_mgmt.h* defines data structures and function - * signatures exported for QDMA queue management. - */ - -#include "qdma_platform_env.h" -#include "qdma_access_export.h" - -/** - * enum qdma_dev_q_range: Q ranage check - */ -enum qdma_dev_q_range { - /** @QDMA_DEV_Q_IN_RANGE: Q belongs to dev */ - QDMA_DEV_Q_IN_RANGE, - /** @QDMA_DEV_Q_OUT_OF_RANGE: Q does not belong to dev */ - QDMA_DEV_Q_OUT_OF_RANGE, - /** @QDMA_DEV_Q_RANGE_MAX: total Q validity states */ - QDMA_DEV_Q_RANGE_MAX -}; - -/*****************************************************************************/ -/** - * qdma_master_resource_create(): create the master q resource - * - * @bus_start: Bus number of the device i.e. pdev->bus->number - * @bus_end: Ending bus number i.e. the subordinate bus number of the - * parent bridge - * @q_base: base from which this master resource needs to be created - * @total_q: total queues in this master resource - * @dma_device_index: DMA device identifier assigned by resource manager to - * track the number of devices - * - * A master resource per driver per board is created to manage the queues - * allocated to this driver. - * - * Return: 0 : success and < 0: failure - *****************************************************************************/ -int qdma_master_resource_create(uint32_t bus_start, uint32_t bus_end, - int q_base, uint32_t total_q, uint32_t *dma_device_index); - -/*****************************************************************************/ -/** - * qdma_master_resource_destroy(): destroy the master q resource - * - * @dma_device_index: DMA device identifier this master resource belongs to - * - * Return: None - *****************************************************************************/ -void qdma_master_resource_destroy(uint32_t dma_device_index); - -/*****************************************************************************/ -/** - * qdma_dev_entry_create(): create a device entry for @func_id - * - * @dma_device_index: DMA device identifier that this device belongs to - * @func_id: device identification id - * - * A device entry is to be created on every function probe. - * - * Return: 0 : success and < 0: failure - *****************************************************************************/ -int qdma_dev_entry_create(uint32_t dma_device_index, uint16_t func_id); - -/*****************************************************************************/ -/** - * qdma_dev_entry_destroy(): destroy device entry for @func_id - * - * @dma_device_index: DMA device identifier that this device belongs to - * @func_id: device identification id - * - * Return: None - *****************************************************************************/ -void qdma_dev_entry_destroy(uint32_t dma_device_index, uint16_t func_id); - -/*****************************************************************************/ -/** - * qdma_dev_update(): update qmax for the device - * - * @dma_device_index: DMA device identifier that this device belongs to - * @func_id: device identification id - * @dev_type: device type - * @qmax: qmax for this device - * @qbase: output qbase for this device - * - * This API is to be called for update request of qmax of any function. - * - * Return: 0 : success and < 0: failure - *****************************************************************************/ -int qdma_dev_update(uint32_t dma_device_index, uint16_t func_id, - uint32_t qmax, int *qbase); - -/*****************************************************************************/ -/** - * qdma_dev_qinfo_get(): get device info - * - * @dma_device_index: DMA device identifier that this device belongs to - * @func_id: device identification id - * @dev_type: device type - * @qmax: output qmax for this device - * @qbase: output qbase for this device - * - * This API can be used get the qbase and qmax for any function - * - * Return: 0 : success and < 0: failure - *****************************************************************************/ -int qdma_dev_qinfo_get(uint32_t dma_device_index, uint16_t func_id, - int *qbase, uint32_t *qmax); - -/*****************************************************************************/ -/** - * qdma_dev_is_queue_in_range(): check if queue belongs to this device - * - * @dma_device_index: DMA device identifier that this device belongs to - * @func_id: device identification id - * @qid_hw: hardware queue id - * - * This API checks if the queue ID is in valid range for function specified - * - * Return: @QDMA_DEV_Q_IN_RANGE : valid and - * @QDMA_DEV_Q_OUT_OF_RANGE: invalid - *****************************************************************************/ -enum qdma_dev_q_range qdma_dev_is_queue_in_range(uint32_t dma_device_index, - uint16_t func_id, - uint32_t qid_hw); - -/*****************************************************************************/ -/** - * qdma_dev_increment_active_queue(): increment active queue count - * - * @dma_device_index: DMA device identifier that this device belongs to - * @func_id: device identification id - * @q_type: Queue type i.e. C2H or H2C or CMPT - * - * This API is used to increment the active queue count of this function - * - * Return: 0 : success and < 0: failure - *****************************************************************************/ -int qdma_dev_increment_active_queue(uint32_t dma_device_index, uint16_t func_id, - enum qdma_dev_q_type q_type); - -/*****************************************************************************/ -/** - * qdma_dev_decrement_active_queue(): increment active queue count - * - * @dma_device_index: DMA device identifier that this device belongs to - * @func_id: device identification id - * @q_type: Queue type i.e. C2H or H2C or CMPT - * - * This API is used to increment the active queue count of this function - * - * Return: 0 : success and < 0: failure - *****************************************************************************/ -int qdma_dev_decrement_active_queue(uint32_t dma_device_index, uint16_t func_id, - enum qdma_dev_q_type q_type); - -/*****************************************************************************/ -/** - * qdma_is_active_queue(): check if any queue is active - * - * @dma_device_index: DMA device identifier that this resource belongs to - * - * This API is used to check if any active queue is present. - * - * Return: active queue count - *****************************************************************************/ -uint32_t qdma_get_active_queue_count(uint32_t dma_device_index); - -/*****************************************************************************/ -/** - * qdma_get_device_active_queue_count(): get device active queue count - * - * @dma_device_index: DMA device identifier that this device belongs to - * @func_id: device identification id - * @q_type: Queue type i.e. C2H or H2C or CMPT - * - * This API is used to get the active queue count of this function - * - * Return: 0 : success and < 0: failure - *****************************************************************************/ -int qdma_get_device_active_queue_count(uint32_t dma_device_index, - uint16_t func_id, - enum qdma_dev_q_type q_type); - -#ifdef __cplusplus -} -#endif - -#endif /* __QDMA_RESOURCE_MGMT_H_ */ diff --git a/QDMA/windows/sys/libqdma/source/qdma_access/qdma_s80_hard_access/qdma_s80_hard_access.c b/QDMA/windows/sys/libqdma/source/qdma_access/qdma_s80_hard_access/qdma_s80_hard_access.c deleted file mode 100644 index 65dd310c2..000000000 --- a/QDMA/windows/sys/libqdma/source/qdma_access/qdma_s80_hard_access/qdma_s80_hard_access.c +++ /dev/null @@ -1,5894 +0,0 @@ -/* - * Copyright (C) 2020 Xilinx, Inc - * - * Licensed under the Apache License, Version 2.0 (the "License"). You may - * not use this file except in compliance with the License. You may obtain - * a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - */ - -#include "qdma_s80_hard_access.h" -#include "qdma_s80_hard_reg.h" -#include "qdma_reg_dump.h" - -#ifdef ENABLE_WPP_TRACING -#include "qdma_s80_hard_access.tmh" -#endif - -/** QDMA S80 Hard Context array size */ -#define QDMA_S80_HARD_SW_CONTEXT_NUM_WORDS 4 -#define QDMA_S80_HARD_CMPT_CONTEXT_NUM_WORDS 4 -#define QDMA_S80_HARD_QID2VEC_CONTEXT_NUM_WORDS 1 -#define QDMA_S80_HARD_HW_CONTEXT_NUM_WORDS 2 -#define QDMA_S80_HARD_CR_CONTEXT_NUM_WORDS 1 -#define QDMA_S80_HARD_IND_INTR_CONTEXT_NUM_WORDS 3 -#define QDMA_S80_HARD_PFETCH_CONTEXT_NUM_WORDS 2 - -#define QDMA_S80_HARD_VF_USER_BAR_ID 2 - -#define QDMA_S80_REG_GROUP_1_START_ADDR 0x000 -#define QDMA_S80_REG_GROUP_2_START_ADDR 0x400 -#define QDMA_S80_REG_GROUP_3_START_ADDR 0xB00 -#define QDMA_S80_REG_GROUP_4_START_ADDR 0x1014 - -#define QDMA_S80_HARD_REG_TRQ_SEL_FMAP_STEP 4 - -#define QDMA_S80_HARD_IND_CTXT_DATA_NUM_REGS 4 - -#define QDMA_S80_HARD_TOTAL_LEAF_ERROR_AGGREGATORS 7 -#define QDMA_S80_HARD_GLBL_TRQ_ERR_ALL_MASK 0XB3 -#define QDMA_S80_HARD_GLBL_DSC_ERR_ALL_MASK 0X1F9037E -#define QDMA_S80_HARD_C2H_ERR_ALL_MASK 0X3F6DF -#define QDMA_S80_HARD_C2H_FATAL_ERR_ALL_MASK 0X1FDF1B -#define QDMA_S80_HARD_H2C_ERR_ALL_MASK 0X3F -#define QDMA_S80_HARD_SBE_ERR_ALL_MASK 0XFFFFFFFF -#define QDMA_S80_HARD_DBE_ERR_ALL_MASK 0XFFFFFFFF - -#define QDMA_S80_HARD_OFFSET_DMAP_SEL_INT_CIDX 0x6400 -#define QDMA_S80_HARD_OFFSET_DMAP_SEL_H2C_DSC_PIDX 0x6404 -#define QDMA_S80_HARD_OFFSET_DMAP_SEL_C2H_DSC_PIDX 0x6408 -#define QDMA_S80_HARD_OFFSET_DMAP_SEL_CMPT_CIDX 0x640C - -#define QDMA_S80_HARD_OFFSET_VF_DMAP_SEL_INT_CIDX 0x3000 -#define QDMA_S80_HARD_OFFSET_VF_DMAP_SEL_H2C_DSC_PIDX 0x3004 -#define QDMA_S80_HARD_OFFSET_VF_DMAP_SEL_C2H_DSC_PIDX 0x3008 -#define QDMA_S80_HARD_OFFSET_VF_DMAP_SEL_CMPT_CIDX 0x300C - -#define QDMA_S80_HARD_DMA_SEL_INT_SW_CIDX_MASK GENMASK(15, 0) -#define QDMA_S80_HARD_DMA_SEL_INT_RING_IDX_MASK GENMASK(23, 16) -#define QDMA_S80_HARD_DMA_SEL_DESC_PIDX_MASK GENMASK(15, 0) -#define QDMA_S80_HARD_DMA_SEL_IRQ_EN_MASK BIT(16) -#define QDMA_S80_HARD_DMAP_SEL_CMPT_IRQ_EN_MASK BIT(28) -#define QDMA_S80_HARD_DMAP_SEL_CMPT_STS_DESC_EN_MASK BIT(27) -#define QDMA_S80_HARD_DMAP_SEL_CMPT_TRG_MODE_MASK GENMASK(26, 24) -#define QDMA_S80_HARD_DMAP_SEL_CMPT_TMR_CNT_MASK GENMASK(23, 20) -#define QDMA_S80_HARD_DMAP_SEL_CMPT_CNT_THRESH_MASK GENMASK(19, 16) -#define QDMA_S80_HARD_DMAP_SEL_CMPT_WRB_CIDX_MASK GENMASK(15, 0) -#define QDMA_S80_HARD_INTR_CTXT_BADDR_GET_H_MASK GENMASK_ULL(63, 35) -#define QDMA_S80_HARD_INTR_CTXT_BADDR_GET_L_MASK GENMASK_ULL(34, 12) -#define QDMA_S80_HARD_COMPL_CTXT_BADDR_GET_H_MASK GENMASK_ULL(63, 42) -#define QDMA_S80_HARD_COMPL_CTXT_BADDR_GET_M_MASK GENMASK_ULL(41, 10) -#define QDMA_S80_HARD_COMPL_CTXT_BADDR_GET_L_MASK GENMASK_ULL(9, 6) -#define QDMA_S80_HARD_COMPL_CTXT_PIDX_GET_H_MASK GENMASK(15, 8) -#define QDMA_S80_HARD_COMPL_CTXT_PIDX_GET_L_MASK GENMASK(7, 0) -#define QDMA_S80_HARD_QID2VEC_H2C_VECTOR GENMASK(16, 9) -#define QDMA_S80_HARD_QID2VEC_H2C_COAL_EN BIT(17) - -static void qdma_s80_hard_hw_st_h2c_err_process(void *dev_hndl); -static void qdma_s80_hard_hw_st_c2h_err_process(void *dev_hndl); -static void qdma_s80_hard_hw_desc_err_process(void *dev_hndl); -static void qdma_s80_hard_hw_trq_err_process(void *dev_hndl); -static void qdma_s80_hard_hw_ram_sbe_err_process(void *dev_hndl); -static void qdma_s80_hard_hw_ram_dbe_err_process(void *dev_hndl); - -static struct qdma_s80_hard_hw_err_info - qdma_s80_hard_err_info[QDMA_S80_HARD_ERRS_ALL] = { - /* Descriptor errors */ - { - QDMA_S80_HARD_DSC_ERR_POISON, - "Poison error", - QDMA_S80_HARD_GLBL_DSC_ERR_MSK_ADDR, - QDMA_S80_HARD_GLBL_DSC_ERR_STS_ADDR, - GLBL_DSC_ERR_STS_POISON_MASK, - GLBL_ERR_STAT_ERR_DSC_MASK, - &qdma_s80_hard_hw_desc_err_process - }, - { - QDMA_S80_HARD_DSC_ERR_UR_CA, - "Unsupported request or completer aborted error", - QDMA_S80_HARD_GLBL_DSC_ERR_MSK_ADDR, - QDMA_S80_HARD_GLBL_DSC_ERR_STS_ADDR, - GLBL_DSC_ERR_STS_UR_CA_MASK, - GLBL_ERR_STAT_ERR_DSC_MASK, - &qdma_s80_hard_hw_desc_err_process - }, - { - QDMA_S80_HARD_DSC_ERR_PARAM, - "Parameter mismatch error", - QDMA_S80_HARD_GLBL_DSC_ERR_MSK_ADDR, - QDMA_S80_HARD_GLBL_DSC_ERR_STS_ADDR, - GLBL_DSC_ERR_STS_PARAM_MASK, - GLBL_ERR_STAT_ERR_DSC_MASK, - &qdma_s80_hard_hw_desc_err_process - }, - { - QDMA_S80_HARD_DSC_ERR_ADDR, - "Address mismatch error", - QDMA_S80_HARD_GLBL_DSC_ERR_MSK_ADDR, - QDMA_S80_HARD_GLBL_DSC_ERR_STS_ADDR, - GLBL_DSC_ERR_STS_ADDR_MASK, - GLBL_ERR_STAT_ERR_DSC_MASK, - &qdma_s80_hard_hw_desc_err_process - }, - { - QDMA_S80_HARD_DSC_ERR_TAG, - "Unexpected tag error", - QDMA_S80_HARD_GLBL_DSC_ERR_MSK_ADDR, - QDMA_S80_HARD_GLBL_DSC_ERR_STS_ADDR, - GLBL_DSC_ERR_STS_TAG_MASK, - GLBL_ERR_STAT_ERR_DSC_MASK, - &qdma_s80_hard_hw_desc_err_process - }, - { - QDMA_S80_HARD_DSC_ERR_FLR, - "FLR error", - QDMA_S80_HARD_GLBL_DSC_ERR_MSK_ADDR, - QDMA_S80_HARD_GLBL_DSC_ERR_STS_ADDR, - GLBL_DSC_ERR_STS_FLR_MASK, - GLBL_ERR_STAT_ERR_DSC_MASK, - &qdma_s80_hard_hw_desc_err_process - }, - { - QDMA_S80_HARD_DSC_ERR_TIMEOUT, - "Timed out error", - QDMA_S80_HARD_GLBL_DSC_ERR_MSK_ADDR, - QDMA_S80_HARD_GLBL_DSC_ERR_STS_ADDR, - GLBL_DSC_ERR_STS_TIMEOUT_MASK, - GLBL_ERR_STAT_ERR_DSC_MASK, - &qdma_s80_hard_hw_desc_err_process - }, - { - QDMA_S80_HARD_DSC_ERR_DAT_POISON, - "Poison data error", - QDMA_S80_HARD_GLBL_DSC_ERR_MSK_ADDR, - QDMA_S80_HARD_GLBL_DSC_ERR_STS_ADDR, - GLBL_DSC_ERR_STS_DAT_POISON_MASK, - GLBL_ERR_STAT_ERR_DSC_MASK, - &qdma_s80_hard_hw_desc_err_process - }, - { - QDMA_S80_HARD_DSC_ERR_FLR_CANCEL, - "Descriptor fetch cancelled due to FLR error", - QDMA_S80_HARD_GLBL_DSC_ERR_MSK_ADDR, - QDMA_S80_HARD_GLBL_DSC_ERR_STS_ADDR, - GLBL_DSC_ERR_STS_FLR_CANCEL_MASK, - GLBL_ERR_STAT_ERR_DSC_MASK, - &qdma_s80_hard_hw_desc_err_process - }, - { - QDMA_S80_HARD_DSC_ERR_DMA, - "DMA engine error", - QDMA_S80_HARD_GLBL_DSC_ERR_MSK_ADDR, - QDMA_S80_HARD_GLBL_DSC_ERR_STS_ADDR, - GLBL_DSC_ERR_STS_DMA_MASK, - GLBL_ERR_STAT_ERR_DSC_MASK, - &qdma_s80_hard_hw_desc_err_process - }, - { - QDMA_S80_HARD_DSC_ERR_DSC, - "Invalid PIDX update error", - QDMA_S80_HARD_GLBL_DSC_ERR_MSK_ADDR, - QDMA_S80_HARD_GLBL_DSC_ERR_STS_ADDR, - GLBL_DSC_ERR_STS_DSC_MASK, - GLBL_ERR_STAT_ERR_DSC_MASK, - &qdma_s80_hard_hw_desc_err_process - }, - { - QDMA_S80_HARD_DSC_ERR_RQ_CANCEL, - "Descriptor fetch cancelled due to disable register status error", - QDMA_S80_HARD_GLBL_DSC_ERR_MSK_ADDR, - QDMA_S80_HARD_GLBL_DSC_ERR_STS_ADDR, - GLBL_DSC_ERR_STS_RQ_CANCEL_MASK, - GLBL_ERR_STAT_ERR_DSC_MASK, - &qdma_s80_hard_hw_desc_err_process - }, - { - QDMA_S80_HARD_DSC_ERR_DBE, - "UNC_ERR_RAM_DBE error", - QDMA_S80_HARD_GLBL_DSC_ERR_MSK_ADDR, - QDMA_S80_HARD_GLBL_DSC_ERR_STS_ADDR, - GLBL_DSC_ERR_STS_DBE_MASK, - GLBL_ERR_STAT_ERR_DSC_MASK, - &qdma_s80_hard_hw_desc_err_process - }, - { - QDMA_S80_HARD_DSC_ERR_SBE, - "UNC_ERR_RAM_SBE error", - QDMA_S80_HARD_GLBL_DSC_ERR_MSK_ADDR, - QDMA_S80_HARD_GLBL_DSC_ERR_STS_ADDR, - GLBL_DSC_ERR_STS_SBE_MASK, - GLBL_ERR_STAT_ERR_DSC_MASK, - &qdma_s80_hard_hw_desc_err_process - }, - { - QDMA_S80_HARD_DSC_ERR_ALL, - "All Descriptor errors", - QDMA_S80_HARD_GLBL_DSC_ERR_MSK_ADDR, - QDMA_S80_HARD_GLBL_DSC_ERR_STS_ADDR, - QDMA_S80_HARD_DBE_ERR_ALL_MASK, - GLBL_ERR_STAT_ERR_DSC_MASK, - &qdma_s80_hard_hw_desc_err_process - }, - - /* TRQ errors */ - { - QDMA_S80_HARD_TRQ_ERR_UNMAPPED, - "Access targeted unmapped register space via CSR pathway error", - QDMA_S80_HARD_GLBL_TRQ_ERR_MSK_ADDR, - QDMA_S80_HARD_GLBL_TRQ_ERR_STS_ADDR, - GLBL_TRQ_ERR_STS_UNMAPPED_MASK, - GLBL_ERR_STAT_ERR_TRQ_MASK, - &qdma_s80_hard_hw_trq_err_process - }, - { - QDMA_S80_HARD_TRQ_ERR_QID_RANGE, - "Qid range error", - QDMA_S80_HARD_GLBL_TRQ_ERR_MSK_ADDR, - QDMA_S80_HARD_GLBL_TRQ_ERR_STS_ADDR, - GLBL_TRQ_ERR_STS_QID_RANGE_MASK, - GLBL_ERR_STAT_ERR_TRQ_MASK, - &qdma_s80_hard_hw_trq_err_process - }, - { - QDMA_S80_HARD_TRQ_ERR_VF_ACCESS_ERR, - "VF attempted to access Global register space or Function map", - QDMA_S80_HARD_GLBL_TRQ_ERR_MSK_ADDR, - QDMA_S80_HARD_GLBL_TRQ_ERR_STS_ADDR, - GLBL_TRQ_ERR_STS_VF_ACCESS_ERR_MASK, - GLBL_ERR_STAT_ERR_TRQ_MASK, - &qdma_s80_hard_hw_trq_err_process - }, - { - QDMA_S80_HARD_TRQ_ERR_TCP_TIMEOUT, - "Timeout on request to dma internal csr register", - QDMA_S80_HARD_GLBL_TRQ_ERR_MSK_ADDR, - QDMA_S80_HARD_GLBL_TRQ_ERR_STS_ADDR, - GLBL_TRQ_ERR_STS_TCP_TIMEOUT_MASK, - GLBL_ERR_STAT_ERR_TRQ_MASK, - &qdma_s80_hard_hw_trq_err_process - }, - { - QDMA_S80_HARD_TRQ_ERR_ALL, - "All TRQ errors", - QDMA_S80_HARD_GLBL_TRQ_ERR_MSK_ADDR, - QDMA_S80_HARD_GLBL_TRQ_ERR_STS_ADDR, - QDMA_S80_HARD_GLBL_TRQ_ERR_ALL_MASK, - GLBL_ERR_STAT_ERR_TRQ_MASK, - &qdma_s80_hard_hw_trq_err_process - }, - - /* C2H Errors*/ - { - QDMA_S80_HARD_ST_C2H_ERR_MTY_MISMATCH, - "MTY mismatch error", - QDMA_S80_HARD_C2H_ERR_MASK_ADDR, - QDMA_S80_HARD_C2H_ERR_STAT_ADDR, - C2H_ERR_STAT_MTY_MISMATCH_MASK, - GLBL_ERR_STAT_ERR_C2H_ST_MASK, - &qdma_s80_hard_hw_st_c2h_err_process - }, - { - QDMA_S80_HARD_ST_C2H_ERR_LEN_MISMATCH, - "Packet length mismatch error", - QDMA_S80_HARD_C2H_ERR_MASK_ADDR, - QDMA_S80_HARD_C2H_ERR_STAT_ADDR, - C2H_ERR_STAT_LEN_MISMATCH_MASK, - GLBL_ERR_STAT_ERR_C2H_ST_MASK, - &qdma_s80_hard_hw_st_c2h_err_process - }, - { - QDMA_S80_HARD_ST_C2H_ERR_QID_MISMATCH, - "Qid mismatch error", - QDMA_S80_HARD_C2H_ERR_MASK_ADDR, - QDMA_S80_HARD_C2H_ERR_STAT_ADDR, - C2H_ERR_STAT_QID_MISMATCH_MASK, - GLBL_ERR_STAT_ERR_C2H_ST_MASK, - &qdma_s80_hard_hw_st_c2h_err_process - }, - { - QDMA_S80_HARD_ST_C2H_ERR_DESC_RSP_ERR, - "Descriptor error bit set", - QDMA_S80_HARD_C2H_ERR_MASK_ADDR, - QDMA_S80_HARD_C2H_ERR_STAT_ADDR, - C2H_ERR_STAT_DESC_RSP_ERR_MASK, - GLBL_ERR_STAT_ERR_C2H_ST_MASK, - &qdma_s80_hard_hw_st_c2h_err_process - }, - { - QDMA_S80_HARD_ST_C2H_ERR_ENG_WPL_DATA_PAR_ERR, - "Data parity error", - QDMA_S80_HARD_C2H_ERR_MASK_ADDR, - QDMA_S80_HARD_C2H_ERR_STAT_ADDR, - C2H_ERR_STAT_ENG_WPL_DATA_PAR_ERR_MASK, - GLBL_ERR_STAT_ERR_C2H_ST_MASK, - &qdma_s80_hard_hw_st_c2h_err_process - }, - { - QDMA_S80_HARD_ST_C2H_ERR_MSI_INT_FAIL, - "MSI got a fail response error", - QDMA_S80_HARD_C2H_ERR_MASK_ADDR, - QDMA_S80_HARD_C2H_ERR_STAT_ADDR, - C2H_ERR_STAT_MSI_INT_FAIL_MASK, - GLBL_ERR_STAT_ERR_C2H_ST_MASK, - &qdma_s80_hard_hw_st_c2h_err_process - }, - { - QDMA_S80_HARD_ST_C2H_ERR_ERR_DESC_CNT, - "Descriptor count error", - QDMA_S80_HARD_C2H_ERR_MASK_ADDR, - QDMA_S80_HARD_C2H_ERR_STAT_ADDR, - C2H_ERR_STAT_ERR_DESC_CNT_MASK, - GLBL_ERR_STAT_ERR_C2H_ST_MASK, - &qdma_s80_hard_hw_st_c2h_err_process - }, - { - QDMA_S80_HARD_ST_C2H_ERR_PORTID_CTXT_MISMATCH, - "Port id in packet and pfetch ctxt mismatch error", - QDMA_S80_HARD_C2H_ERR_MASK_ADDR, - QDMA_S80_HARD_C2H_ERR_STAT_ADDR, - C2H_ERR_STAT_PORT_ID_CTXT_MISMATCH_MASK, - GLBL_ERR_STAT_ERR_C2H_ST_MASK, - &qdma_s80_hard_hw_st_c2h_err_process - }, - { - QDMA_S80_HARD_ST_C2H_ERR_PORTID_BYP_IN_MISMATCH, - "Port id in packet and bypass in mismatch error", - QDMA_S80_HARD_C2H_ERR_MASK_ADDR, - QDMA_S80_HARD_C2H_ERR_STAT_ADDR, - C2H_ERR_STAT_PORT_ID_CTXT_MISMATCH_MASK, - GLBL_ERR_STAT_ERR_C2H_ST_MASK, - &qdma_s80_hard_hw_st_c2h_err_process - }, - { - QDMA_S80_HARD_ST_C2H_ERR_WRB_INV_Q_ERR, - "Writeback on invalid queue error", - QDMA_S80_HARD_C2H_ERR_MASK_ADDR, - QDMA_S80_HARD_C2H_ERR_STAT_ADDR, - C2H_ERR_STAT_WRB_INV_Q_ERR_MASK, - GLBL_ERR_STAT_ERR_C2H_ST_MASK, - &qdma_s80_hard_hw_st_c2h_err_process - }, - { - QDMA_S80_HARD_ST_C2H_ERR_WRB_QFULL_ERR, - "Completion queue gets full error", - QDMA_S80_HARD_C2H_ERR_MASK_ADDR, - QDMA_S80_HARD_C2H_ERR_STAT_ADDR, - C2H_ERR_STAT_WRB_QFULL_ERR_MASK, - GLBL_ERR_STAT_ERR_C2H_ST_MASK, - &qdma_s80_hard_hw_st_c2h_err_process - }, - { - QDMA_S80_HARD_ST_C2H_ERR_WRB_CIDX_ERR, - "Bad CIDX update by the software error", - QDMA_S80_HARD_C2H_ERR_MASK_ADDR, - QDMA_S80_HARD_C2H_ERR_STAT_ADDR, - C2H_ERR_STAT_WRB_CIDX_ERR_MASK, - GLBL_ERR_STAT_ERR_C2H_ST_MASK, - &qdma_s80_hard_hw_st_c2h_err_process - }, - { - QDMA_S80_HARD_ST_C2H_ERR_WRB_PRTY_ERR, - "C2H completion Parity error", - QDMA_S80_HARD_C2H_ERR_MASK_ADDR, - QDMA_S80_HARD_C2H_ERR_STAT_ADDR, - C2H_ERR_STAT_WRB_PRTY_ERR_MASK, - GLBL_ERR_STAT_ERR_C2H_ST_MASK, - &qdma_s80_hard_hw_st_c2h_err_process - }, - { - QDMA_S80_HARD_ST_C2H_ERR_ALL, - "All C2h errors", - QDMA_S80_HARD_C2H_ERR_MASK_ADDR, - QDMA_S80_HARD_C2H_ERR_STAT_ADDR, - QDMA_S80_HARD_C2H_ERR_ALL_MASK, - GLBL_ERR_STAT_ERR_C2H_ST_MASK, - &qdma_s80_hard_hw_st_c2h_err_process - }, - - /* C2H fatal errors */ - { - QDMA_S80_HARD_ST_FATAL_ERR_MTY_MISMATCH, - "Fatal MTY mismatch error", - QDMA_S80_HARD_C2H_FATAL_ERR_MASK_ADDR, - QDMA_S80_HARD_C2H_FATAL_ERR_STAT_ADDR, - C2H_FATAL_ERR_STAT_MTY_MISMATCH_MASK, - GLBL_ERR_STAT_ERR_C2H_ST_MASK, - &qdma_s80_hard_hw_st_c2h_err_process - }, - { - QDMA_S80_HARD_ST_FATAL_ERR_LEN_MISMATCH, - "Fatal Len mismatch error", - QDMA_S80_HARD_C2H_FATAL_ERR_MASK_ADDR, - QDMA_S80_HARD_C2H_FATAL_ERR_STAT_ADDR, - C2H_FATAL_ERR_STAT_LEN_MISMATCH_MASK, - GLBL_ERR_STAT_ERR_C2H_ST_MASK, - &qdma_s80_hard_hw_st_c2h_err_process - }, - { - QDMA_S80_HARD_ST_FATAL_ERR_QID_MISMATCH, - "Fatal Qid mismatch error", - QDMA_S80_HARD_C2H_FATAL_ERR_MASK_ADDR, - QDMA_S80_HARD_C2H_FATAL_ERR_STAT_ADDR, - C2H_FATAL_ERR_STAT_QID_MISMATCH_MASK, - GLBL_ERR_STAT_ERR_C2H_ST_MASK, - &qdma_s80_hard_hw_st_c2h_err_process - }, - { - QDMA_S80_HARD_ST_FATAL_ERR_TIMER_FIFO_RAM_RDBE, - "RAM double bit fatal error", - QDMA_S80_HARD_C2H_FATAL_ERR_MASK_ADDR, - QDMA_S80_HARD_C2H_FATAL_ERR_STAT_ADDR, - C2H_FATAL_ERR_STAT_TIMER_FIFO_RAM_RDBE_MASK, - GLBL_ERR_STAT_ERR_C2H_ST_MASK, - &qdma_s80_hard_hw_st_c2h_err_process - }, - { - QDMA_S80_HARD_ST_FATAL_ERR_PFCH_II_RAM_RDBE, - "RAM double bit fatal error", - QDMA_S80_HARD_C2H_FATAL_ERR_MASK_ADDR, - QDMA_S80_HARD_C2H_FATAL_ERR_STAT_ADDR, - C2H_FATAL_ERR_STAT_PFCH_LL_RAM_RDBE_MASK, - GLBL_ERR_STAT_ERR_C2H_ST_MASK, - &qdma_s80_hard_hw_st_c2h_err_process - }, - { - QDMA_S80_HARD_ST_FATAL_ERR_WRB_CTXT_RAM_RDBE, - "RAM double bit fatal error", - QDMA_S80_HARD_C2H_FATAL_ERR_MASK_ADDR, - QDMA_S80_HARD_C2H_FATAL_ERR_STAT_ADDR, - C2H_FATAL_ERR_STAT_WRB_CTXT_RAM_RDBE_MASK, - GLBL_ERR_STAT_ERR_C2H_ST_MASK, - &qdma_s80_hard_hw_st_c2h_err_process - }, - { - QDMA_S80_HARD_ST_FATAL_ERR_PFCH_CTXT_RAM_RDBE, - "RAM double bit fatal error", - QDMA_S80_HARD_C2H_FATAL_ERR_MASK_ADDR, - QDMA_S80_HARD_C2H_FATAL_ERR_STAT_ADDR, - C2H_FATAL_ERR_STAT_PFCH_CTXT_RAM_RDBE_MASK, - GLBL_ERR_STAT_ERR_C2H_ST_MASK, - &qdma_s80_hard_hw_st_c2h_err_process - }, - { - QDMA_S80_HARD_ST_FATAL_ERR_DESC_REQ_FIFO_RAM_RDBE, - "RAM double bit fatal error", - QDMA_S80_HARD_C2H_FATAL_ERR_MASK_ADDR, - QDMA_S80_HARD_C2H_FATAL_ERR_STAT_ADDR, - C2H_FATAL_ERR_STAT_DESC_REQ_FIFO_RAM_RDBE_MASK, - GLBL_ERR_STAT_ERR_C2H_ST_MASK, - &qdma_s80_hard_hw_st_c2h_err_process - }, - { - QDMA_S80_HARD_ST_FATAL_ERR_INT_CTXT_RAM_RDBE, - "RAM double bit fatal error", - QDMA_S80_HARD_C2H_FATAL_ERR_MASK_ADDR, - QDMA_S80_HARD_C2H_FATAL_ERR_STAT_ADDR, - C2H_FATAL_ERR_STAT_INT_CTXT_RAM_RDBE_MASK, - GLBL_ERR_STAT_ERR_C2H_ST_MASK, - &qdma_s80_hard_hw_st_c2h_err_process - }, - { - QDMA_S80_HARD_ST_FATAL_ERR_INT_QID2VEC_RAM_RDBE, - "RAM double bit fatal error", - QDMA_S80_HARD_C2H_FATAL_ERR_MASK_ADDR, - QDMA_S80_HARD_C2H_FATAL_ERR_STAT_ADDR, - C2H_FATAL_ERR_STAT_INT_QID2VEC_RAM_RDBE_MASK, - GLBL_ERR_STAT_ERR_C2H_ST_MASK, - &qdma_s80_hard_hw_st_c2h_err_process - }, - { - QDMA_S80_HARD_ST_FATAL_ERR_WRB_COAL_DATA_RAM_RDBE, - "RAM double bit fatal error", - QDMA_S80_HARD_C2H_FATAL_ERR_MASK_ADDR, - QDMA_S80_HARD_C2H_FATAL_ERR_STAT_ADDR, - C2H_FATAL_ERR_STAT_WRB_COAL_DATA_RAM_RDBE_MASK, - GLBL_ERR_STAT_ERR_C2H_ST_MASK, - &qdma_s80_hard_hw_st_c2h_err_process - }, - { - QDMA_S80_HARD_ST_FATAL_ERR_TUSER_FIFO_RAM_RDBE, - "RAM double bit fatal error", - QDMA_S80_HARD_C2H_FATAL_ERR_MASK_ADDR, - QDMA_S80_HARD_C2H_FATAL_ERR_STAT_ADDR, - C2H_FATAL_ERR_STAT_TUSER_FIFO_RAM_RDBE_MASK, - GLBL_ERR_STAT_ERR_C2H_ST_MASK, - &qdma_s80_hard_hw_st_c2h_err_process - }, - { - QDMA_S80_HARD_ST_FATAL_ERR_QID_FIFO_RAM_RDBE, - "RAM double bit fatal error", - QDMA_S80_HARD_C2H_FATAL_ERR_MASK_ADDR, - QDMA_S80_HARD_C2H_FATAL_ERR_STAT_ADDR, - C2H_FATAL_ERR_STAT_QID_FIFO_RAM_RDBE_MASK, - GLBL_ERR_STAT_ERR_C2H_ST_MASK, - &qdma_s80_hard_hw_st_c2h_err_process - }, - { - QDMA_S80_HARD_ST_FATAL_ERR_PAYLOAD_FIFO_RAM_RDBE, - "RAM double bit fatal error", - QDMA_S80_HARD_C2H_FATAL_ERR_MASK_ADDR, - QDMA_S80_HARD_C2H_FATAL_ERR_STAT_ADDR, - C2H_FATAL_ERR_STAT_PLD_FIFO_RAM_RDBE_MASK, - GLBL_ERR_STAT_ERR_C2H_ST_MASK, - &qdma_s80_hard_hw_st_c2h_err_process - }, - { - QDMA_S80_HARD_ST_FATAL_ERR_WPL_DATA_PAR_ERR, - "RAM double bit fatal error", - QDMA_S80_HARD_C2H_FATAL_ERR_MASK_ADDR, - QDMA_S80_HARD_C2H_FATAL_ERR_STAT_ADDR, - C2H_FATAL_ERR_STAT_WPL_DATA_PAR_ERR_MASK, - GLBL_ERR_STAT_ERR_C2H_ST_MASK, - &qdma_s80_hard_hw_st_c2h_err_process - }, - { - QDMA_S80_HARD_ST_FATAL_ERR_ALL, - "All fatal errors", - QDMA_S80_HARD_C2H_FATAL_ERR_MASK_ADDR, - QDMA_S80_HARD_C2H_FATAL_ERR_STAT_ADDR, - QDMA_S80_HARD_C2H_FATAL_ERR_ALL_MASK, - GLBL_ERR_STAT_ERR_C2H_ST_MASK, - &qdma_s80_hard_hw_st_c2h_err_process - }, - - /* H2C St errors */ - { - QDMA_S80_HARD_ST_H2C_ERR_ZERO_LEN_DESC_ERR, - "Zero length descriptor error", - QDMA_S80_HARD_H2C_ERR_MASK_ADDR, - QDMA_S80_HARD_H2C_ERR_STAT_ADDR, - H2C_ERR_STAT_ZERO_LEN_DS_MASK, - GLBL_ERR_STAT_ERR_H2C_ST_MASK, - &qdma_s80_hard_hw_st_h2c_err_process - }, - { - QDMA_S80_HARD_ST_H2C_ERR_SDI_MRKR_REQ_MOP_ERR, - "A non-EOP descriptor received", - QDMA_S80_HARD_H2C_ERR_MASK_ADDR, - QDMA_S80_HARD_H2C_ERR_STAT_ADDR, - H2C_ERR_STAT_SDI_MRKR_REQ_MOP_ERR_MASK, - GLBL_ERR_STAT_ERR_H2C_ST_MASK, - &qdma_s80_hard_hw_st_h2c_err_process - }, - { - QDMA_S80_HARD_ST_H2C_ERR_NO_DMA_DSC, - "No DMA descriptor received error", - QDMA_S80_HARD_H2C_ERR_MASK_ADDR, - QDMA_S80_HARD_H2C_ERR_STAT_ADDR, - H2C_ERR_STAT_NO_DMA_DS_MASK, - GLBL_ERR_STAT_ERR_H2C_ST_MASK, - &qdma_s80_hard_hw_st_h2c_err_process - }, - { - QDMA_S80_HARD_ST_H2C_ERR_DBE, - "Double bit error detected on H2C-ST data error", - QDMA_S80_HARD_H2C_ERR_MASK_ADDR, - QDMA_S80_HARD_H2C_ERR_STAT_ADDR, - H2C_ERR_STAT_DBE_MASK, - GLBL_ERR_STAT_ERR_H2C_ST_MASK, - &qdma_s80_hard_hw_st_h2c_err_process - }, - { - QDMA_S80_HARD_ST_H2C_ERR_SBE, - "Single bit error detected on H2C-ST data error", - QDMA_S80_HARD_H2C_ERR_MASK_ADDR, - QDMA_S80_HARD_H2C_ERR_STAT_ADDR, - H2C_ERR_STAT_SBE_MASK, - GLBL_ERR_STAT_ERR_H2C_ST_MASK, - &qdma_s80_hard_hw_st_h2c_err_process - }, - { - QDMA_S80_HARD_ST_H2C_ERR_ALL, - "All H2C errors", - QDMA_S80_HARD_H2C_ERR_MASK_ADDR, - QDMA_S80_HARD_H2C_ERR_STAT_ADDR, - QDMA_S80_HARD_H2C_ERR_ALL_MASK, - GLBL_ERR_STAT_ERR_H2C_ST_MASK, - &qdma_s80_hard_hw_st_h2c_err_process - }, - - /* SBE errors */ - { - QDMA_S80_HARD_SBE_ERR_MI_H2C0_DAT, - "H2C MM data buffer single bit ECC error", - QDMA_S80_HARD_RAM_SBE_MSK_A_ADDR, - QDMA_S80_HARD_RAM_SBE_STS_A_ADDR, - RAM_SBE_STS_A_MI_H2C0_DAT_MASK, - GLBL_ERR_STAT_ERR_RAM_SBE_MASK, - &qdma_s80_hard_hw_ram_sbe_err_process - }, - { - QDMA_S80_HARD_SBE_ERR_MI_C2H0_DAT, - "C2H MM data buffer single bit ECC error", - QDMA_S80_HARD_RAM_SBE_MSK_A_ADDR, - QDMA_S80_HARD_RAM_SBE_STS_A_ADDR, - RAM_SBE_STS_A_MI_C2H0_DAT_MASK, - GLBL_ERR_STAT_ERR_RAM_SBE_MASK, - &qdma_s80_hard_hw_ram_sbe_err_process - }, - { - QDMA_S80_HARD_SBE_ERR_H2C_RD_BRG_DAT, - "Bridge master read single bit ECC error", - QDMA_S80_HARD_RAM_SBE_MSK_A_ADDR, - QDMA_S80_HARD_RAM_SBE_STS_A_ADDR, - RAM_SBE_STS_A_H2C_RD_BRG_DAT_MASK, - GLBL_ERR_STAT_ERR_RAM_SBE_MASK, - &qdma_s80_hard_hw_ram_sbe_err_process - }, - { - QDMA_S80_HARD_SBE_ERR_H2C_WR_BRG_DAT, - "Bridge master write single bit ECC error", - QDMA_S80_HARD_RAM_SBE_MSK_A_ADDR, - QDMA_S80_HARD_RAM_SBE_STS_A_ADDR, - RAM_SBE_STS_A_H2C_WR_BRG_DAT_MASK, - GLBL_ERR_STAT_ERR_RAM_SBE_MASK, - &qdma_s80_hard_hw_ram_sbe_err_process - }, - { - QDMA_S80_HARD_SBE_ERR_C2H_RD_BRG_DAT, - "Bridge slave read data buffer single bit ECC error", - QDMA_S80_HARD_RAM_SBE_MSK_A_ADDR, - QDMA_S80_HARD_RAM_SBE_STS_A_ADDR, - RAM_SBE_STS_A_C2H_RD_BRG_DAT_MASK, - GLBL_ERR_STAT_ERR_RAM_SBE_MASK, - &qdma_s80_hard_hw_ram_sbe_err_process - }, - { - QDMA_S80_HARD_SBE_ERR_C2H_WR_BRG_DAT, - "Bridge slave write data buffer single bit ECC error", - QDMA_S80_HARD_RAM_SBE_MSK_A_ADDR, - QDMA_S80_HARD_RAM_SBE_STS_A_ADDR, - RAM_SBE_STS_A_C2H_WR_BRG_DAT_MASK, - GLBL_ERR_STAT_ERR_RAM_SBE_MASK, - &qdma_s80_hard_hw_ram_sbe_err_process - }, - { - QDMA_S80_HARD_SBE_ERR_FUNC_MAP, - "Function map RAM single bit ECC error", - QDMA_S80_HARD_RAM_SBE_MSK_A_ADDR, - QDMA_S80_HARD_RAM_SBE_STS_A_ADDR, - RAM_SBE_STS_A_FUNC_MAP_MASK, - GLBL_ERR_STAT_ERR_RAM_SBE_MASK, - &qdma_s80_hard_hw_ram_sbe_err_process - }, - { - QDMA_S80_HARD_SBE_ERR_DSC_HW_CTXT, - "Descriptor engine hardware context RAM single bit ECC error", - QDMA_S80_HARD_RAM_SBE_MSK_A_ADDR, - QDMA_S80_HARD_RAM_SBE_STS_A_ADDR, - RAM_SBE_STS_A_DSC_HW_CTXT_MASK, - GLBL_ERR_STAT_ERR_RAM_SBE_MASK, - &qdma_s80_hard_hw_ram_sbe_err_process - }, - { - QDMA_S80_HARD_SBE_ERR_DSC_CRD_RCV, - "Descriptor engine receive credit context RAM single bit ECC error", - QDMA_S80_HARD_RAM_SBE_MSK_A_ADDR, - QDMA_S80_HARD_RAM_SBE_STS_A_ADDR, - RAM_SBE_STS_A_DSC_CRD_RCV_MASK, - GLBL_ERR_STAT_ERR_RAM_SBE_MASK, - &qdma_s80_hard_hw_ram_sbe_err_process - }, - { - QDMA_S80_HARD_SBE_ERR_DSC_SW_CTXT, - "Descriptor engine software context RAM single bit ECC error", - QDMA_S80_HARD_RAM_SBE_MSK_A_ADDR, - QDMA_S80_HARD_RAM_SBE_STS_A_ADDR, - RAM_SBE_STS_A_DSC_SW_CTXT_MASK, - GLBL_ERR_STAT_ERR_RAM_SBE_MASK, - &qdma_s80_hard_hw_ram_sbe_err_process - }, - { - QDMA_S80_HARD_SBE_ERR_DSC_CPLI, - "Descriptor engine fetch completion information RAM single bit ECC error", - QDMA_S80_HARD_RAM_SBE_MSK_A_ADDR, - QDMA_S80_HARD_RAM_SBE_STS_A_ADDR, - RAM_SBE_STS_A_DSC_CPLI_MASK, - GLBL_ERR_STAT_ERR_RAM_SBE_MASK, - &qdma_s80_hard_hw_ram_sbe_err_process - }, - { - QDMA_S80_HARD_SBE_ERR_DSC_CPLD, - "Descriptor engine fetch completion data RAM single bit ECC error", - QDMA_S80_HARD_RAM_SBE_MSK_A_ADDR, - QDMA_S80_HARD_RAM_SBE_STS_A_ADDR, - RAM_SBE_STS_A_DSC_CPLD_MASK, - GLBL_ERR_STAT_ERR_RAM_SBE_MASK, - &qdma_s80_hard_hw_ram_sbe_err_process - }, - { - QDMA_S80_HARD_SBE_ERR_PASID_CTXT_RAM, - "Pasid ctxt FIFO RAM single bit ECC error", - QDMA_S80_HARD_RAM_SBE_MSK_A_ADDR, - QDMA_S80_HARD_RAM_SBE_STS_A_ADDR, - RAM_SBE_STS_A_PASID_CTXT_RAM_MASK, - GLBL_ERR_STAT_ERR_RAM_SBE_MASK, - &qdma_s80_hard_hw_ram_sbe_err_process - }, - { - QDMA_S80_HARD_SBE_ERR_TIMER_FIFO_RAM, - "Timer fifo RAM single bit ECC error", - QDMA_S80_HARD_RAM_SBE_MSK_A_ADDR, - QDMA_S80_HARD_RAM_SBE_STS_A_ADDR, - RAM_SBE_STS_A_TIMER_FIFO_RAM_MASK, - GLBL_ERR_STAT_ERR_RAM_SBE_MASK, - &qdma_s80_hard_hw_ram_sbe_err_process - }, - { - QDMA_S80_HARD_SBE_ERR_PAYLOAD_FIFO_RAM, - "C2H ST payload FIFO RAM single bit ECC error", - QDMA_S80_HARD_RAM_SBE_MSK_A_ADDR, - QDMA_S80_HARD_RAM_SBE_STS_A_ADDR, - RAM_SBE_STS_A_PLD_FIFO_RAM_MASK, - GLBL_ERR_STAT_ERR_RAM_SBE_MASK, - &qdma_s80_hard_hw_ram_sbe_err_process - }, - { - QDMA_S80_HARD_SBE_ERR_QID_FIFO_RAM, - "C2H ST QID FIFO RAM single bit ECC error", - QDMA_S80_HARD_RAM_SBE_MSK_A_ADDR, - QDMA_S80_HARD_RAM_SBE_STS_A_ADDR, - RAM_SBE_STS_A_QID_FIFO_RAM_MASK, - GLBL_ERR_STAT_ERR_RAM_SBE_MASK, - &qdma_s80_hard_hw_ram_sbe_err_process - }, - { - QDMA_S80_HARD_SBE_ERR_TUSER_FIFO_RAM, - "C2H ST TUSER FIFO RAM single bit ECC error", - QDMA_S80_HARD_RAM_SBE_MSK_A_ADDR, - QDMA_S80_HARD_RAM_SBE_STS_A_ADDR, - RAM_SBE_STS_A_TUSER_FIFO_RAM_MASK, - GLBL_ERR_STAT_ERR_RAM_SBE_MASK, - &qdma_s80_hard_hw_ram_sbe_err_process - }, - { - QDMA_S80_HARD_SBE_ERR_WRB_COAL_DATA_RAM, - "Writeback Coalescing RAM single bit ECC error", - QDMA_S80_HARD_RAM_SBE_MSK_A_ADDR, - QDMA_S80_HARD_RAM_SBE_STS_A_ADDR, - RAM_SBE_STS_A_WRB_COAL_DATA_RAM_MASK, - GLBL_ERR_STAT_ERR_RAM_SBE_MASK, - &qdma_s80_hard_hw_ram_sbe_err_process - }, - { - QDMA_S80_HARD_SBE_ERR_INT_QID2VEC_RAM, - "Interrupt QID2VEC RAM single bit ECC error", - QDMA_S80_HARD_RAM_SBE_MSK_A_ADDR, - QDMA_S80_HARD_RAM_SBE_STS_A_ADDR, - RAM_SBE_STS_A_INT_QID2VEC_RAM_MASK, - GLBL_ERR_STAT_ERR_RAM_SBE_MASK, - &qdma_s80_hard_hw_ram_sbe_err_process - }, - { - QDMA_S80_HARD_SBE_ERR_INT_CTXT_RAM, - "Interrupt context RAM single bit ECC error", - QDMA_S80_HARD_RAM_SBE_MSK_A_ADDR, - QDMA_S80_HARD_RAM_SBE_STS_A_ADDR, - RAM_SBE_STS_A_INT_CTXT_RAM_MASK, - GLBL_ERR_STAT_ERR_RAM_SBE_MASK, - &qdma_s80_hard_hw_ram_sbe_err_process - }, - { - QDMA_S80_HARD_SBE_ERR_DESC_REQ_FIFO_RAM, - "C2H ST descriptor request RAM single bit ECC error", - QDMA_S80_HARD_RAM_SBE_MSK_A_ADDR, - QDMA_S80_HARD_RAM_SBE_STS_A_ADDR, - RAM_SBE_STS_A_DESC_REQ_FIFO_RAM_MASK, - GLBL_ERR_STAT_ERR_RAM_SBE_MASK, - &qdma_s80_hard_hw_ram_sbe_err_process - }, - { - QDMA_S80_HARD_SBE_ERR_PFCH_CTXT_RAM, - "C2H ST prefetch RAM single bit ECC error", - QDMA_S80_HARD_RAM_SBE_MSK_A_ADDR, - QDMA_S80_HARD_RAM_SBE_STS_A_ADDR, - RAM_SBE_STS_A_PFCH_CTXT_RAM_MASK, - GLBL_ERR_STAT_ERR_RAM_SBE_MASK, - &qdma_s80_hard_hw_ram_sbe_err_process - }, - { - QDMA_S80_HARD_SBE_ERR_WRB_CTXT_RAM, - "C2H ST completion context RAM single bit ECC error", - QDMA_S80_HARD_RAM_SBE_MSK_A_ADDR, - QDMA_S80_HARD_RAM_SBE_STS_A_ADDR, - RAM_SBE_STS_A_WRB_CTXT_RAM_MASK, - GLBL_ERR_STAT_ERR_RAM_SBE_MASK, - &qdma_s80_hard_hw_ram_sbe_err_process - }, - { - QDMA_S80_HARD_SBE_ERR_PFCH_LL_RAM, - "C2H ST prefetch list RAM single bit ECC error", - QDMA_S80_HARD_RAM_SBE_MSK_A_ADDR, - QDMA_S80_HARD_RAM_SBE_STS_A_ADDR, - RAM_SBE_STS_A_PFCH_LL_RAM_MASK, - GLBL_ERR_STAT_ERR_RAM_SBE_MASK, - &qdma_s80_hard_hw_ram_sbe_err_process - }, - { - QDMA_S80_HARD_SBE_ERR_ALL, - "All SBE errors", - QDMA_S80_HARD_RAM_SBE_MSK_A_ADDR, - QDMA_S80_HARD_RAM_SBE_STS_A_ADDR, - QDMA_S80_HARD_SBE_ERR_ALL_MASK, - GLBL_ERR_STAT_ERR_RAM_SBE_MASK, - &qdma_s80_hard_hw_ram_sbe_err_process - }, - - - /* DBE errors */ - { - QDMA_S80_HARD_DBE_ERR_MI_H2C0_DAT, - "H2C MM data buffer single bit ECC error", - QDMA_S80_HARD_RAM_DBE_MSK_A_ADDR, - QDMA_S80_HARD_RAM_DBE_STS_A_ADDR, - RAM_DBE_STS_A_MI_H2C0_DAT_MASK, - GLBL_ERR_STAT_ERR_RAM_DBE_MASK, - &qdma_s80_hard_hw_ram_dbe_err_process - }, - { - QDMA_S80_HARD_DBE_ERR_MI_C2H0_DAT, - "C2H MM data buffer single bit ECC error", - QDMA_S80_HARD_RAM_DBE_MSK_A_ADDR, - QDMA_S80_HARD_RAM_DBE_STS_A_ADDR, - RAM_DBE_STS_A_MI_C2H0_DAT_MASK, - GLBL_ERR_STAT_ERR_RAM_DBE_MASK, - &qdma_s80_hard_hw_ram_dbe_err_process - }, - { - QDMA_S80_HARD_DBE_ERR_H2C_RD_BRG_DAT, - "Bridge master read single bit ECC error", - QDMA_S80_HARD_RAM_DBE_MSK_A_ADDR, - QDMA_S80_HARD_RAM_DBE_STS_A_ADDR, - RAM_DBE_STS_A_H2C_RD_BRG_DAT_MASK, - GLBL_ERR_STAT_ERR_RAM_DBE_MASK, - &qdma_s80_hard_hw_ram_dbe_err_process - }, - { - QDMA_S80_HARD_DBE_ERR_H2C_WR_BRG_DAT, - "Bridge master write single bit ECC error", - QDMA_S80_HARD_RAM_DBE_MSK_A_ADDR, - QDMA_S80_HARD_RAM_DBE_STS_A_ADDR, - RAM_DBE_STS_A_H2C_WR_BRG_DAT_MASK, - GLBL_ERR_STAT_ERR_RAM_DBE_MASK, - &qdma_s80_hard_hw_ram_dbe_err_process - }, - { - QDMA_S80_HARD_DBE_ERR_C2H_RD_BRG_DAT, - "Bridge slave read data buffer single bit ECC error", - QDMA_S80_HARD_RAM_DBE_MSK_A_ADDR, - QDMA_S80_HARD_RAM_DBE_STS_A_ADDR, - RAM_DBE_STS_A_C2H_RD_BRG_DAT_MASK, - GLBL_ERR_STAT_ERR_RAM_DBE_MASK, - &qdma_s80_hard_hw_ram_dbe_err_process - }, - { - QDMA_S80_HARD_DBE_ERR_C2H_WR_BRG_DAT, - "Bridge slave write data buffer single bit ECC error", - QDMA_S80_HARD_RAM_DBE_MSK_A_ADDR, - QDMA_S80_HARD_RAM_DBE_STS_A_ADDR, - RAM_DBE_STS_A_C2H_WR_BRG_DAT_MASK, - GLBL_ERR_STAT_ERR_RAM_DBE_MASK, - &qdma_s80_hard_hw_ram_dbe_err_process - }, - { - QDMA_S80_HARD_DBE_ERR_FUNC_MAP, - "Function map RAM single bit ECC error", - QDMA_S80_HARD_RAM_DBE_MSK_A_ADDR, - QDMA_S80_HARD_RAM_DBE_STS_A_ADDR, - RAM_DBE_STS_A_FUNC_MAP_MASK, - GLBL_ERR_STAT_ERR_RAM_DBE_MASK, - &qdma_s80_hard_hw_ram_dbe_err_process - }, - { - QDMA_S80_HARD_DBE_ERR_DSC_HW_CTXT, - "Descriptor engine hardware context RAM single bit ECC error", - QDMA_S80_HARD_RAM_DBE_MSK_A_ADDR, - QDMA_S80_HARD_RAM_DBE_STS_A_ADDR, - RAM_DBE_STS_A_DSC_HW_CTXT_MASK, - GLBL_ERR_STAT_ERR_RAM_DBE_MASK, - &qdma_s80_hard_hw_ram_dbe_err_process - }, - { - QDMA_S80_HARD_DBE_ERR_DSC_CRD_RCV, - "Descriptor engine receive credit context RAM single bit ECC error", - QDMA_S80_HARD_RAM_DBE_MSK_A_ADDR, - QDMA_S80_HARD_RAM_DBE_STS_A_ADDR, - RAM_DBE_STS_A_DSC_CRD_RCV_MASK, - GLBL_ERR_STAT_ERR_RAM_DBE_MASK, - &qdma_s80_hard_hw_ram_dbe_err_process - }, - { - QDMA_S80_HARD_DBE_ERR_DSC_SW_CTXT, - "Descriptor engine software context RAM single bit ECC error", - QDMA_S80_HARD_RAM_DBE_MSK_A_ADDR, - QDMA_S80_HARD_RAM_DBE_STS_A_ADDR, - RAM_DBE_STS_A_DSC_SW_CTXT_MASK, - GLBL_ERR_STAT_ERR_RAM_DBE_MASK, - &qdma_s80_hard_hw_ram_dbe_err_process - }, - { - QDMA_S80_HARD_DBE_ERR_DSC_CPLI, - "Descriptor engine fetch completion information RAM single bit ECC error", - QDMA_S80_HARD_RAM_DBE_MSK_A_ADDR, - QDMA_S80_HARD_RAM_DBE_STS_A_ADDR, - RAM_DBE_STS_A_DSC_CPLI_MASK, - GLBL_ERR_STAT_ERR_RAM_DBE_MASK, - &qdma_s80_hard_hw_ram_dbe_err_process - }, - { - QDMA_S80_HARD_DBE_ERR_DSC_CPLD, - "Descriptor engine fetch completion data RAM single bit ECC error", - QDMA_S80_HARD_RAM_DBE_MSK_A_ADDR, - QDMA_S80_HARD_RAM_DBE_STS_A_ADDR, - RAM_DBE_STS_A_DSC_CPLD_MASK, - GLBL_ERR_STAT_ERR_RAM_DBE_MASK, - &qdma_s80_hard_hw_ram_dbe_err_process - }, - { - QDMA_S80_HARD_DBE_ERR_PASID_CTXT_RAM, - "PASID CTXT RAM single bit ECC error", - QDMA_S80_HARD_RAM_DBE_MSK_A_ADDR, - QDMA_S80_HARD_RAM_DBE_STS_A_ADDR, - RAM_DBE_STS_A_PASID_CTXT_RAM_MASK, - GLBL_ERR_STAT_ERR_RAM_DBE_MASK, - &qdma_s80_hard_hw_ram_dbe_err_process - }, - { - QDMA_S80_HARD_DBE_ERR_TIMER_FIFO_RAM, - "Timer fifo RAM single bit ECC error", - QDMA_S80_HARD_RAM_DBE_MSK_A_ADDR, - QDMA_S80_HARD_RAM_DBE_STS_A_ADDR, - RAM_DBE_STS_A_TIMER_FIFO_RAM_MASK, - GLBL_ERR_STAT_ERR_RAM_DBE_MASK, - &qdma_s80_hard_hw_ram_dbe_err_process - }, - { - QDMA_S80_HARD_DBE_ERR_PAYLOAD_FIFO_RAM, - "Payload fifo RAM single bit ECC error", - QDMA_S80_HARD_RAM_DBE_MSK_A_ADDR, - QDMA_S80_HARD_RAM_DBE_STS_A_ADDR, - RAM_DBE_STS_A_PLD_FIFO_RAM_MASK, - GLBL_ERR_STAT_ERR_RAM_DBE_MASK, - &qdma_s80_hard_hw_ram_dbe_err_process - }, - { - QDMA_S80_HARD_DBE_ERR_QID_FIFO_RAM, - "C2H ST QID FIFO RAM single bit ECC error", - QDMA_S80_HARD_RAM_DBE_MSK_A_ADDR, - QDMA_S80_HARD_RAM_DBE_STS_A_ADDR, - RAM_DBE_STS_A_QID_FIFO_RAM_MASK, - GLBL_ERR_STAT_ERR_RAM_DBE_MASK, - &qdma_s80_hard_hw_ram_dbe_err_process - }, - { - QDMA_S80_HARD_DBE_ERR_WRB_COAL_DATA_RAM, - "Writeback Coalescing RAM single bit ECC error", - QDMA_S80_HARD_RAM_DBE_MSK_A_ADDR, - QDMA_S80_HARD_RAM_DBE_STS_A_ADDR, - RAM_DBE_STS_A_WRB_COAL_DATA_RAM_MASK, - GLBL_ERR_STAT_ERR_RAM_DBE_MASK, - &qdma_s80_hard_hw_ram_dbe_err_process - }, - { - QDMA_S80_HARD_DBE_ERR_INT_QID2VEC_RAM, - "QID2VEC RAM single bit ECC error", - QDMA_S80_HARD_RAM_DBE_MSK_A_ADDR, - QDMA_S80_HARD_RAM_DBE_STS_A_ADDR, - RAM_DBE_STS_A_INT_QID2VEC_RAM_MASK, - GLBL_ERR_STAT_ERR_RAM_DBE_MASK, - &qdma_s80_hard_hw_ram_dbe_err_process - }, - { - QDMA_S80_HARD_DBE_ERR_INT_CTXT_RAM, - "Interrupt context RAM single bit ECC error", - QDMA_S80_HARD_RAM_DBE_MSK_A_ADDR, - QDMA_S80_HARD_RAM_DBE_STS_A_ADDR, - RAM_DBE_STS_A_INT_CTXT_RAM_MASK, - GLBL_ERR_STAT_ERR_RAM_DBE_MASK, - &qdma_s80_hard_hw_ram_dbe_err_process - }, - { - QDMA_S80_HARD_DBE_ERR_DESC_REQ_FIFO_RAM, - "C2H ST descriptor request RAM single bit ECC error", - QDMA_S80_HARD_RAM_DBE_MSK_A_ADDR, - QDMA_S80_HARD_RAM_DBE_STS_A_ADDR, - RAM_DBE_STS_A_DESC_REQ_FIFO_RAM_MASK, - GLBL_ERR_STAT_ERR_RAM_DBE_MASK, - &qdma_s80_hard_hw_ram_dbe_err_process - }, - { - QDMA_S80_HARD_DBE_ERR_PFCH_CTXT_RAM, - "C2H ST prefetch RAM single bit ECC error", - QDMA_S80_HARD_RAM_DBE_MSK_A_ADDR, - QDMA_S80_HARD_RAM_DBE_STS_A_ADDR, - RAM_DBE_STS_A_PFCH_CTXT_RAM_MASK, - GLBL_ERR_STAT_ERR_RAM_DBE_MASK, - &qdma_s80_hard_hw_ram_dbe_err_process - }, - { - QDMA_S80_HARD_DBE_ERR_WRB_CTXT_RAM, - "C2H ST completion context RAM single bit ECC error", - QDMA_S80_HARD_RAM_DBE_MSK_A_ADDR, - QDMA_S80_HARD_RAM_DBE_STS_A_ADDR, - RAM_DBE_STS_A_WRB_CTXT_RAM_MASK, - GLBL_ERR_STAT_ERR_RAM_DBE_MASK, - &qdma_s80_hard_hw_ram_dbe_err_process - }, - { - QDMA_S80_HARD_DBE_ERR_PFCH_LL_RAM, - "C2H ST prefetch list RAM single bit ECC error", - QDMA_S80_HARD_RAM_DBE_MSK_A_ADDR, - QDMA_S80_HARD_RAM_DBE_STS_A_ADDR, - RAM_DBE_STS_A_PFCH_LL_RAM_MASK, - GLBL_ERR_STAT_ERR_RAM_DBE_MASK, - &qdma_s80_hard_hw_ram_dbe_err_process - }, - { - QDMA_S80_HARD_DBE_ERR_ALL, - "All DBE errors", - QDMA_S80_HARD_RAM_DBE_MSK_A_ADDR, - QDMA_S80_HARD_RAM_DBE_STS_A_ADDR, - QDMA_S80_HARD_DBE_ERR_ALL_MASK, - GLBL_ERR_STAT_ERR_RAM_DBE_MASK, - &qdma_s80_hard_hw_ram_dbe_err_process - } -}; - -static int32_t all_qdma_s80_hard_hw_errs[ - QDMA_S80_HARD_TOTAL_LEAF_ERROR_AGGREGATORS] = { - - QDMA_S80_HARD_DSC_ERR_ALL, - QDMA_S80_HARD_TRQ_ERR_ALL, - QDMA_S80_HARD_ST_C2H_ERR_ALL, - QDMA_S80_HARD_ST_FATAL_ERR_ALL, - QDMA_S80_HARD_ST_H2C_ERR_ALL, - QDMA_S80_HARD_SBE_ERR_ALL, - QDMA_S80_HARD_DBE_ERR_ALL -}; - - - -union qdma_s80_hard_ind_ctxt_cmd { - uint32_t word; - struct { - uint32_t busy:1; - uint32_t sel:4; - uint32_t op:2; - uint32_t qid:11; - uint32_t rsvd:14; - } bits; -}; - -struct qdma_s80_hard_indirect_ctxt_regs { - uint32_t qdma_ind_ctxt_data[QDMA_S80_HARD_IND_CTXT_DATA_NUM_REGS]; - uint32_t qdma_ind_ctxt_mask[QDMA_S80_HARD_IND_CTXT_DATA_NUM_REGS]; - union qdma_s80_hard_ind_ctxt_cmd cmd; -}; - -static struct qctx_entry qdma_s80_hard_sw_ctxt_entries[] = { - {"PIDX", 0}, - {"IRQ Arm", 0}, - {"Queue Enable", 0}, - {"Fetch Credit Enable", 0}, - {"Write back/Intr Check", 0}, - {"Write back/Intr Interval", 0}, - {"Function Id", 0}, - {"Ring Size", 0}, - {"Descriptor Size", 0}, - {"Bypass Enable", 0}, - {"MM Channel", 0}, - {"Writeback Enable", 0}, - {"Interrupt Enable", 0}, - {"Port Id", 0}, - {"Interrupt No Last", 0}, - {"Error", 0}, - {"Writeback Error Sent", 0}, - {"IRQ Request", 0}, - {"Marker Disable", 0}, - {"Is Memory Mapped", 0}, - {"Descriptor Ring Base Addr (Low)", 0}, - {"Descriptor Ring Base Addr (High)", 0}, -}; - -static struct qctx_entry qdma_s80_hard_hw_ctxt_entries[] = { - {"CIDX", 0}, - {"Credits Consumed", 0}, - {"Descriptors Pending", 0}, - {"Queue Invalid No Desc Pending", 0}, - {"Eviction Pending", 0}, - {"Fetch Pending", 0}, -}; - -static struct qctx_entry qdma_s80_hard_credit_ctxt_entries[] = { - {"Credit", 0}, -}; - -static struct qctx_entry qdma_s80_hard_cmpt_ctxt_entries[] = { - {"Enable Status Desc Update", 0}, - {"Enable Interrupt", 0}, - {"Trigger Mode", 0}, - {"Function Id", 0}, - {"Counter Index", 0}, - {"Timer Index", 0}, - {"Interrupt State", 0}, - {"Color", 0}, - {"Ring Size", 0}, - {"Base Address (Low)", 0}, - {"Base Address (High)", 0}, - {"Descriptor Size", 0}, - {"PIDX", 0}, - {"CIDX", 0}, - {"Valid", 0}, - {"Error", 0}, - {"Trigger Pending", 0}, - {"Timer Running", 0}, - {"Full Update", 0}, -}; - -static struct qctx_entry qdma_s80_hard_c2h_pftch_ctxt_entries[] = { - {"Bypass", 0}, - {"Buffer Size Index", 0}, - {"Port Id", 0}, - {"Error", 0}, - {"Prefetch Enable", 0}, - {"In Prefetch", 0}, - {"Software Credit", 0}, - {"Valid", 0}, -}; - -static struct qctx_entry qdma_s80_hard_qid2vec_ctxt_entries[] = { - {"c2h_vector", 0}, - {"c2h_en_coal", 0}, - {"h2c_vector", 0}, - {"h2c_en_coal", 0}, -}; - -static struct qctx_entry qdma_s80_hard_ind_intr_ctxt_entries[] = { - {"valid", 0}, - {"vec", 0}, - {"int_st", 0}, - {"color", 0}, - {"baddr_4k (Low)", 0}, - {"baddr_4k (High)", 0}, - {"page_size", 0}, - {"pidx", 0}, -}; - -static int qdma_s80_hard_indirect_reg_invalidate(void *dev_hndl, - enum ind_ctxt_cmd_sel sel, uint16_t hw_qid); -static int qdma_s80_hard_indirect_reg_clear(void *dev_hndl, - enum ind_ctxt_cmd_sel sel, uint16_t hw_qid); -static int qdma_s80_hard_indirect_reg_read(void *dev_hndl, - enum ind_ctxt_cmd_sel sel, - uint16_t hw_qid, uint32_t cnt, uint32_t *data); -static int qdma_s80_hard_indirect_reg_write(void *dev_hndl, - enum ind_ctxt_cmd_sel sel, - uint16_t hw_qid, uint32_t *data, uint16_t cnt); - -uint32_t qdma_s80_hard_get_config_num_regs(void) -{ - return qdma_s80_hard_config_num_regs_get(); -} - -struct xreg_info *qdma_s80_hard_get_config_regs(void) -{ - return qdma_s80_hard_config_regs_get(); -} - -uint32_t qdma_s80_hard_reg_dump_buf_len(void) -{ - uint32_t length = (qdma_s80_hard_config_num_regs_get() + 1) - * REG_DUMP_SIZE_PER_LINE; - return length; -} - -int qdma_s80_hard_context_buf_len(uint8_t st, - enum qdma_dev_q_type q_type, uint32_t *req_buflen) -{ - uint32_t len = 0; - int rv = 0; - - if (q_type == QDMA_DEV_Q_TYPE_CMPT) { - len += (((sizeof(qdma_s80_hard_cmpt_ctxt_entries) / - sizeof(qdma_s80_hard_cmpt_ctxt_entries[0])) + 1) * - REG_DUMP_SIZE_PER_LINE); - } else { - len += (((sizeof(qdma_s80_hard_sw_ctxt_entries) / - sizeof(qdma_s80_hard_sw_ctxt_entries[0])) + 1) * - REG_DUMP_SIZE_PER_LINE); - - len += (((sizeof(qdma_s80_hard_hw_ctxt_entries) / - sizeof(qdma_s80_hard_hw_ctxt_entries[0])) + 1) * - REG_DUMP_SIZE_PER_LINE); - - len += (((sizeof(qdma_s80_hard_credit_ctxt_entries) / - sizeof(qdma_s80_hard_credit_ctxt_entries[0])) + 1) * - REG_DUMP_SIZE_PER_LINE); - - if (st && (q_type == QDMA_DEV_Q_TYPE_C2H)) { - len += (((sizeof(qdma_s80_hard_cmpt_ctxt_entries) / - sizeof(qdma_s80_hard_cmpt_ctxt_entries[0])) + 1) * - REG_DUMP_SIZE_PER_LINE); - - len += (((sizeof(qdma_s80_hard_c2h_pftch_ctxt_entries) / - sizeof(qdma_s80_hard_c2h_pftch_ctxt_entries[0])) + 1) * - REG_DUMP_SIZE_PER_LINE); - } - } - - *req_buflen = len; - return rv; -} - -static uint32_t qdma_s80_hard_intr_context_buf_len(void) -{ - uint32_t len = 0; - - len += (((sizeof(qdma_s80_hard_ind_intr_ctxt_entries) / - sizeof(qdma_s80_hard_ind_intr_ctxt_entries[0])) + 1) * - REG_DUMP_SIZE_PER_LINE); - return len; -} - -/* - * qdma_acc_fill_sw_ctxt() - Helper function to fill sw context into structure - * - */ -static void qdma_s80_hard_fill_sw_ctxt(struct qdma_descq_sw_ctxt *sw_ctxt) -{ - qdma_s80_hard_sw_ctxt_entries[0].value = sw_ctxt->pidx; - qdma_s80_hard_sw_ctxt_entries[1].value = sw_ctxt->irq_arm; - qdma_s80_hard_sw_ctxt_entries[2].value = sw_ctxt->qen; - qdma_s80_hard_sw_ctxt_entries[3].value = sw_ctxt->frcd_en; - qdma_s80_hard_sw_ctxt_entries[4].value = sw_ctxt->wbi_chk; - qdma_s80_hard_sw_ctxt_entries[5].value = sw_ctxt->wbi_intvl_en; - qdma_s80_hard_sw_ctxt_entries[6].value = sw_ctxt->fnc_id; - qdma_s80_hard_sw_ctxt_entries[7].value = sw_ctxt->rngsz_idx; - qdma_s80_hard_sw_ctxt_entries[8].value = sw_ctxt->desc_sz; - qdma_s80_hard_sw_ctxt_entries[9].value = sw_ctxt->bypass; - qdma_s80_hard_sw_ctxt_entries[10].value = sw_ctxt->mm_chn; - qdma_s80_hard_sw_ctxt_entries[11].value = sw_ctxt->wbk_en; - qdma_s80_hard_sw_ctxt_entries[12].value = sw_ctxt->irq_en; - qdma_s80_hard_sw_ctxt_entries[13].value = sw_ctxt->port_id; - qdma_s80_hard_sw_ctxt_entries[14].value = sw_ctxt->irq_no_last; - qdma_s80_hard_sw_ctxt_entries[15].value = sw_ctxt->err; - qdma_s80_hard_sw_ctxt_entries[16].value = sw_ctxt->err_wb_sent; - qdma_s80_hard_sw_ctxt_entries[17].value = sw_ctxt->irq_req; - qdma_s80_hard_sw_ctxt_entries[18].value = sw_ctxt->mrkr_dis; - qdma_s80_hard_sw_ctxt_entries[19].value = sw_ctxt->is_mm; - qdma_s80_hard_sw_ctxt_entries[20].value = - sw_ctxt->ring_bs_addr & 0xFFFFFFFF; - qdma_s80_hard_sw_ctxt_entries[21].value = - (sw_ctxt->ring_bs_addr >> 32) & 0xFFFFFFFF; -} - -/* - * qdma_acc_fill_cmpt_ctxt() - Helper function to fill completion context - * into structure - * - */ -static void qdma_s80_hard_fill_cmpt_ctxt(struct qdma_descq_cmpt_ctxt *cmpt_ctxt) -{ - qdma_s80_hard_cmpt_ctxt_entries[0].value = cmpt_ctxt->en_stat_desc; - qdma_s80_hard_cmpt_ctxt_entries[1].value = cmpt_ctxt->en_int; - qdma_s80_hard_cmpt_ctxt_entries[2].value = cmpt_ctxt->trig_mode; - qdma_s80_hard_cmpt_ctxt_entries[3].value = cmpt_ctxt->fnc_id; - qdma_s80_hard_cmpt_ctxt_entries[4].value = cmpt_ctxt->counter_idx; - qdma_s80_hard_cmpt_ctxt_entries[5].value = cmpt_ctxt->timer_idx; - qdma_s80_hard_cmpt_ctxt_entries[6].value = cmpt_ctxt->in_st; - qdma_s80_hard_cmpt_ctxt_entries[7].value = cmpt_ctxt->color; - qdma_s80_hard_cmpt_ctxt_entries[8].value = cmpt_ctxt->ringsz_idx; - qdma_s80_hard_cmpt_ctxt_entries[9].value = - cmpt_ctxt->bs_addr & 0xFFFFFFFF; - qdma_s80_hard_cmpt_ctxt_entries[10].value = - (cmpt_ctxt->bs_addr >> 32) & 0xFFFFFFFF; - qdma_s80_hard_cmpt_ctxt_entries[11].value = cmpt_ctxt->desc_sz; - qdma_s80_hard_cmpt_ctxt_entries[12].value = cmpt_ctxt->pidx; - qdma_s80_hard_cmpt_ctxt_entries[13].value = cmpt_ctxt->cidx; - qdma_s80_hard_cmpt_ctxt_entries[14].value = cmpt_ctxt->valid; - qdma_s80_hard_cmpt_ctxt_entries[15].value = cmpt_ctxt->err; - qdma_s80_hard_cmpt_ctxt_entries[16].value = cmpt_ctxt->user_trig_pend; - qdma_s80_hard_cmpt_ctxt_entries[17].value = cmpt_ctxt->timer_running; - qdma_s80_hard_cmpt_ctxt_entries[18].value = cmpt_ctxt->full_upd; - -} - -/* - * qdma_acc_fill_hw_ctxt() - Helper function to fill HW context into structure - * - */ -static void qdma_s80_hard_fill_hw_ctxt(struct qdma_descq_hw_ctxt *hw_ctxt) -{ - qdma_s80_hard_hw_ctxt_entries[0].value = hw_ctxt->cidx; - qdma_s80_hard_hw_ctxt_entries[1].value = hw_ctxt->crd_use; - qdma_s80_hard_hw_ctxt_entries[2].value = hw_ctxt->dsc_pend; - qdma_s80_hard_hw_ctxt_entries[3].value = hw_ctxt->idl_stp_b; - qdma_s80_hard_hw_ctxt_entries[4].value = hw_ctxt->evt_pnd; - qdma_s80_hard_hw_ctxt_entries[5].value = hw_ctxt->fetch_pnd; -} - -/* - * qdma_acc_fill_credit_ctxt() - Helper function to fill Credit context - * into structure - * - */ -static void qdma_s80_hard_fill_credit_ctxt( - struct qdma_descq_credit_ctxt *cr_ctxt) -{ - qdma_s80_hard_credit_ctxt_entries[0].value = cr_ctxt->credit; -} - -/* - * qdma_acc_fill_pfetch_ctxt() - Helper function to fill Prefetch context - * into structure - * - */ -static void qdma_s80_hard_fill_pfetch_ctxt( - struct qdma_descq_prefetch_ctxt *pfetch_ctxt) -{ - qdma_s80_hard_c2h_pftch_ctxt_entries[0].value = pfetch_ctxt->bypass; - qdma_s80_hard_c2h_pftch_ctxt_entries[1].value = pfetch_ctxt->bufsz_idx; - qdma_s80_hard_c2h_pftch_ctxt_entries[2].value = pfetch_ctxt->port_id; - qdma_s80_hard_c2h_pftch_ctxt_entries[3].value = pfetch_ctxt->err; - qdma_s80_hard_c2h_pftch_ctxt_entries[4].value = pfetch_ctxt->pfch_en; - qdma_s80_hard_c2h_pftch_ctxt_entries[5].value = pfetch_ctxt->pfch; - qdma_s80_hard_c2h_pftch_ctxt_entries[6].value = pfetch_ctxt->sw_crdt; - qdma_s80_hard_c2h_pftch_ctxt_entries[7].value = pfetch_ctxt->valid; -} - -static void qdma_s80_hard_fill_qid2vec_ctxt(struct qdma_qid2vec *qid2vec_ctxt) -{ - qdma_s80_hard_qid2vec_ctxt_entries[0].value = qid2vec_ctxt->c2h_vector; - qdma_s80_hard_qid2vec_ctxt_entries[1].value = qid2vec_ctxt->c2h_en_coal; - qdma_s80_hard_qid2vec_ctxt_entries[2].value = qid2vec_ctxt->h2c_vector; - qdma_s80_hard_qid2vec_ctxt_entries[3].value = qid2vec_ctxt->h2c_en_coal; -} - -static void qdma_s80_hard_fill_intr_ctxt( - struct qdma_indirect_intr_ctxt *intr_ctxt) -{ - qdma_s80_hard_ind_intr_ctxt_entries[0].value = intr_ctxt->valid; - qdma_s80_hard_ind_intr_ctxt_entries[1].value = intr_ctxt->vec; - qdma_s80_hard_ind_intr_ctxt_entries[2].value = intr_ctxt->int_st; - qdma_s80_hard_ind_intr_ctxt_entries[3].value = intr_ctxt->color; - qdma_s80_hard_ind_intr_ctxt_entries[4].value = - intr_ctxt->baddr_4k & 0xFFFFFFFF; - qdma_s80_hard_ind_intr_ctxt_entries[5].value = - (intr_ctxt->baddr_4k >> 32) & 0xFFFFFFFF; - qdma_s80_hard_ind_intr_ctxt_entries[6].value = intr_ctxt->page_size; - qdma_s80_hard_ind_intr_ctxt_entries[7].value = intr_ctxt->pidx; -} - -/* - * dump_s80_hard_context() - Helper function to dump queue context into string - * - * return len - length of the string copied into buffer - */ -static int dump_s80_hard_context(struct qdma_descq_context *queue_context, - uint8_t st, enum qdma_dev_q_type q_type, - char *buf, int buf_sz) -{ - int i = 0; - int n; - int len = 0; - int rv; - char banner[DEBGFS_LINE_SZ]; - - if (queue_context == NULL) { - qdma_log_error("%s: queue_context is NULL, err:%d\n", - __func__, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - if (q_type >= QDMA_DEV_Q_TYPE_CMPT) { - qdma_log_error("%s: Invalid queue type(%d), err:%d\n", - __func__, - q_type, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - qdma_s80_hard_fill_sw_ctxt(&queue_context->sw_ctxt); - qdma_s80_hard_fill_hw_ctxt(&queue_context->hw_ctxt); - qdma_s80_hard_fill_credit_ctxt(&queue_context->cr_ctxt); - qdma_s80_hard_fill_qid2vec_ctxt(&queue_context->qid2vec); - if (st && (q_type == QDMA_DEV_Q_TYPE_C2H)) { - qdma_s80_hard_fill_pfetch_ctxt(&queue_context->pfetch_ctxt); - qdma_s80_hard_fill_cmpt_ctxt(&queue_context->cmpt_ctxt); - } - - if (q_type != QDMA_DEV_Q_TYPE_CMPT) { - for (i = 0; i < DEBGFS_LINE_SZ - 5; i++) { - rv = QDMA_SNPRINTF_S(banner + i, - (DEBGFS_LINE_SZ - i), - sizeof("-"), "-"); - if ((rv < 0) || (rv > (int)sizeof("-"))) { - qdma_log_error( - "%d:%s QDMA_SNPRINTF_S() failed, err:%d\n", - __LINE__, __func__, - rv); - goto INSUF_BUF_EXIT; - } - } - - /* SW context dump */ - n = sizeof(qdma_s80_hard_sw_ctxt_entries) / - sizeof((qdma_s80_hard_sw_ctxt_entries)[0]); - for (i = 0; i < n; i++) { - if ((len >= buf_sz) || - ((len + DEBGFS_LINE_SZ) >= buf_sz)) - goto INSUF_BUF_EXIT; - - if (i == 0) { - if ((len + (3 * DEBGFS_LINE_SZ)) >= buf_sz) - goto INSUF_BUF_EXIT; - rv = QDMA_SNPRINTF_S(buf + len, (buf_sz - len), - DEBGFS_LINE_SZ, "\n%s", banner); - if ((rv < 0) || (rv > DEBGFS_LINE_SZ)) { - qdma_log_error( - "%d:%s QDMA_SNPRINTF_S() failed, err:%d\n", - __LINE__, __func__, - rv); - goto INSUF_BUF_EXIT; - } - len += rv; - - rv = QDMA_SNPRINTF_S(buf + len, (buf_sz - len), - DEBGFS_LINE_SZ, "\n%40s", "SW Context"); - if ((rv < 0) || (rv > DEBGFS_LINE_SZ)) { - qdma_log_error( - "%d:%s QDMA_SNPRINTF_S() failed, err:%d\n", - __LINE__, __func__, - rv); - goto INSUF_BUF_EXIT; - } - len += rv; - - rv = QDMA_SNPRINTF_S(buf + len, (buf_sz - len), - DEBGFS_LINE_SZ, "\n%s\n", banner); - if ((rv < 0) || (rv > DEBGFS_LINE_SZ)) { - qdma_log_error( - "%d:%s QDMA_SNPRINTF_S() failed, err:%d\n", - __LINE__, __func__, - rv); - goto INSUF_BUF_EXIT; - } - len += rv; - } - - rv = QDMA_SNPRINTF_S(buf + len, (buf_sz - len), - DEBGFS_LINE_SZ, - "%-47s %#-10x %u\n", - qdma_s80_hard_sw_ctxt_entries[i].name, - qdma_s80_hard_sw_ctxt_entries[i].value, - qdma_s80_hard_sw_ctxt_entries[i].value); - if ((rv < 0) || (rv > DEBGFS_LINE_SZ)) { - qdma_log_error( - "%d:%s QDMA_SNPRINTF_S() failed, err:%d\n", - __LINE__, __func__, - rv); - goto INSUF_BUF_EXIT; - } - len += rv; - } - - /* HW context dump */ - n = sizeof(qdma_s80_hard_hw_ctxt_entries) / - sizeof((qdma_s80_hard_hw_ctxt_entries)[0]); - for (i = 0; i < n; i++) { - if ((len >= buf_sz) || - ((len + DEBGFS_LINE_SZ) >= buf_sz)) - goto INSUF_BUF_EXIT; - - if (i == 0) { - if ((len + (3 * DEBGFS_LINE_SZ)) >= buf_sz) - goto INSUF_BUF_EXIT; - - rv = QDMA_SNPRINTF_S(buf + len, (buf_sz - len), - DEBGFS_LINE_SZ, "\n%s", banner); - if ((rv < 0) || (rv > DEBGFS_LINE_SZ)) { - qdma_log_error( - "%d:%s QDMA_SNPRINTF_S() failed, err:%d\n", - __LINE__, __func__, - rv); - goto INSUF_BUF_EXIT; - } - len += rv; - - rv = QDMA_SNPRINTF_S(buf + len, (buf_sz - len), - DEBGFS_LINE_SZ, "\n%40s", "HW Context"); - if ((rv < 0) || (rv > DEBGFS_LINE_SZ)) { - qdma_log_error( - "%d:%s QDMA_SNPRINTF_S() failed, err:%d\n", - __LINE__, __func__, - rv); - goto INSUF_BUF_EXIT; - } - len += rv; - - rv = QDMA_SNPRINTF_S(buf + len, (buf_sz - len), - DEBGFS_LINE_SZ, "\n%s\n", banner); - if ((rv < 0) || (rv > DEBGFS_LINE_SZ)) { - qdma_log_error( - "%d:%s QDMA_SNPRINTF_S() failed, err:%d\n", - __LINE__, __func__, - rv); - goto INSUF_BUF_EXIT; - } - len += rv; - } - - rv = QDMA_SNPRINTF_S(buf + len, (buf_sz - len), - DEBGFS_LINE_SZ, - "%-47s %#-10x %u\n", - qdma_s80_hard_hw_ctxt_entries[i].name, - qdma_s80_hard_hw_ctxt_entries[i].value, - qdma_s80_hard_hw_ctxt_entries[i].value); - if ((rv < 0) || (rv > DEBGFS_LINE_SZ)) { - qdma_log_error( - "%d:%s QDMA_SNPRINTF_S() failed, err:%d\n", - __LINE__, __func__, - rv); - goto INSUF_BUF_EXIT; - } - len += rv; - } - - /* Credit context dump */ - n = sizeof(qdma_s80_hard_credit_ctxt_entries) / - sizeof((qdma_s80_hard_credit_ctxt_entries)[0]); - for (i = 0; i < n; i++) { - if ((len >= buf_sz) || - ((len + DEBGFS_LINE_SZ) >= buf_sz)) - goto INSUF_BUF_EXIT; - - if (i == 0) { - if ((len + (3 * DEBGFS_LINE_SZ)) >= buf_sz) - goto INSUF_BUF_EXIT; - - rv = QDMA_SNPRINTF_S(buf + len, (buf_sz - len), - DEBGFS_LINE_SZ, "\n%s", banner); - if ((rv < 0) || (rv > DEBGFS_LINE_SZ)) { - qdma_log_error( - "%d:%s QDMA_SNPRINTF_S() failed, err:%d\n", - __LINE__, __func__, - rv); - goto INSUF_BUF_EXIT; - } - len += rv; - - rv = QDMA_SNPRINTF_S(buf + len, (buf_sz - len), - DEBGFS_LINE_SZ, "\n%40s", - "Credit Context"); - if ((rv < 0) || (rv > DEBGFS_LINE_SZ)) { - qdma_log_error( - "%d:%s QDMA_SNPRINTF_S() failed, err:%d\n", - __LINE__, __func__, - rv); - goto INSUF_BUF_EXIT; - } - len += rv; - - rv = QDMA_SNPRINTF_S(buf + len, (buf_sz - len), - DEBGFS_LINE_SZ, "\n%s\n", banner); - if ((rv < 0) || (rv > DEBGFS_LINE_SZ)) { - qdma_log_error( - "%d:%s QDMA_SNPRINTF_S() failed, err:%d\n", - __LINE__, __func__, - rv); - goto INSUF_BUF_EXIT; - } - len += rv; - } - - rv = QDMA_SNPRINTF_S(buf + len, (buf_sz - len), - DEBGFS_LINE_SZ, - "%-47s %#-10x %u\n", - qdma_s80_hard_credit_ctxt_entries[i].name, - qdma_s80_hard_credit_ctxt_entries[i].value, - qdma_s80_hard_credit_ctxt_entries[i].value); - if ((rv < 0) || (rv > DEBGFS_LINE_SZ)) { - qdma_log_error( - "%d:%s QDMA_SNPRINTF_S() failed, err:%d\n", - __LINE__, __func__, - rv); - goto INSUF_BUF_EXIT; - } - len += rv; - } - } - - /* SW context dump */ - n = sizeof(qdma_s80_hard_qid2vec_ctxt_entries) / - sizeof((qdma_s80_hard_qid2vec_ctxt_entries)[0]); - for (i = 0; i < n; i++) { - if ((len >= buf_sz) || - ((len + DEBGFS_LINE_SZ) >= buf_sz)) - goto INSUF_BUF_EXIT; - - if (i == 0) { - if ((len + (3 * DEBGFS_LINE_SZ)) >= buf_sz) - goto INSUF_BUF_EXIT; - rv = QDMA_SNPRINTF_S(buf + len, (buf_sz - len), - DEBGFS_LINE_SZ, "\n%s", banner); - if ((rv < 0) || (rv > DEBGFS_LINE_SZ)) { - qdma_log_error( - "%d:%s QDMA_SNPRINTF_S() failed, err:%d\n", - __LINE__, __func__, - rv); - goto INSUF_BUF_EXIT; - } - len += rv; - - rv = QDMA_SNPRINTF_S(buf + len, (buf_sz - len), - DEBGFS_LINE_SZ, "\n%40s", - "QID2VEC Context"); - if ((rv < 0) || (rv > DEBGFS_LINE_SZ)) { - qdma_log_error( - "%d:%s QDMA_SNPRINTF_S() failed, err:%d\n", - __LINE__, __func__, - rv); - goto INSUF_BUF_EXIT; - } - len += rv; - - rv = QDMA_SNPRINTF_S(buf + len, (buf_sz - len), - DEBGFS_LINE_SZ, "\n%s\n", banner); - if ((rv < 0) || (rv > DEBGFS_LINE_SZ)) { - qdma_log_error( - "%d:%s QDMA_SNPRINTF_S() failed, err:%d\n", - __LINE__, __func__, - rv); - goto INSUF_BUF_EXIT; - } - len += rv; - } - - rv = QDMA_SNPRINTF_S(buf + len, (buf_sz - len), DEBGFS_LINE_SZ, - "%-47s %#-10x %u\n", - qdma_s80_hard_qid2vec_ctxt_entries[i].name, - qdma_s80_hard_qid2vec_ctxt_entries[i].value, - qdma_s80_hard_qid2vec_ctxt_entries[i].value); - if ((rv < 0) || (rv > DEBGFS_LINE_SZ)) { - qdma_log_error( - "%d:%s QDMA_SNPRINTF_S() failed, err:%d\n", - __LINE__, __func__, - rv); - goto INSUF_BUF_EXIT; - } - len += rv; - } - - - if ((q_type == QDMA_DEV_Q_TYPE_CMPT) || - (st && q_type == QDMA_DEV_Q_TYPE_C2H)) { - /* Completion context dump */ - n = sizeof(qdma_s80_hard_cmpt_ctxt_entries) / - sizeof((qdma_s80_hard_cmpt_ctxt_entries)[0]); - for (i = 0; i < n; i++) { - if ((len >= buf_sz) || - ((len + DEBGFS_LINE_SZ) >= buf_sz)) - goto INSUF_BUF_EXIT; - - if (i == 0) { - if ((len + (3 * DEBGFS_LINE_SZ)) >= buf_sz) - goto INSUF_BUF_EXIT; - - rv = QDMA_SNPRINTF_S(buf + len, (buf_sz - len), - DEBGFS_LINE_SZ, "\n%s", banner); - if ((rv < 0) || (rv > DEBGFS_LINE_SZ)) { - qdma_log_error( - "%d:%s QDMA_SNPRINTF_S() failed, err:%d\n", - __LINE__, __func__, - rv); - goto INSUF_BUF_EXIT; - } - len += rv; - - rv = QDMA_SNPRINTF_S(buf + len, (buf_sz - len), - DEBGFS_LINE_SZ, "\n%40s", - "Completion Context"); - if ((rv < 0) || (rv > DEBGFS_LINE_SZ)) { - qdma_log_error( - "%d:%s QDMA_SNPRINTF_S() failed, err:%d\n", - __LINE__, __func__, - rv); - goto INSUF_BUF_EXIT; - } - len += rv; - - rv = QDMA_SNPRINTF_S(buf + len, (buf_sz - len), - DEBGFS_LINE_SZ, "\n%s\n", banner); - if ((rv < 0) || (rv > DEBGFS_LINE_SZ)) { - qdma_log_error( - "%d:%s QDMA_SNPRINTF_S() failed, err:%d\n", - __LINE__, __func__, - rv); - goto INSUF_BUF_EXIT; - } - len += rv; - } - - rv = QDMA_SNPRINTF_S(buf + len, (buf_sz - len), - DEBGFS_LINE_SZ, - "%-47s %#-10x %u\n", - qdma_s80_hard_cmpt_ctxt_entries[i].name, - qdma_s80_hard_cmpt_ctxt_entries[i].value, - qdma_s80_hard_cmpt_ctxt_entries[i].value); - if ((rv < 0) || (rv > DEBGFS_LINE_SZ)) { - qdma_log_error( - "%d:%s QDMA_SNPRINTF_S() failed, err:%d\n", - __LINE__, __func__, - rv); - goto INSUF_BUF_EXIT; - } - len += rv; - } - } - - if (st && q_type == QDMA_DEV_Q_TYPE_C2H) { - /* Prefetch context dump */ - n = sizeof(qdma_s80_hard_c2h_pftch_ctxt_entries) / - sizeof(qdma_s80_hard_c2h_pftch_ctxt_entries[0]); - for (i = 0; i < n; i++) { - if ((len >= buf_sz) || - ((len + DEBGFS_LINE_SZ) >= buf_sz)) - goto INSUF_BUF_EXIT; - - if (i == 0) { - if ((len + (3 * DEBGFS_LINE_SZ)) >= buf_sz) - goto INSUF_BUF_EXIT; - - rv = QDMA_SNPRINTF_S(buf + len, (buf_sz - len), - DEBGFS_LINE_SZ, "\n%s", banner); - if ((rv < 0) || (rv > DEBGFS_LINE_SZ)) { - qdma_log_error( - "%d:%s QDMA_SNPRINTF_S() failed, err:%d\n", - __LINE__, __func__, - rv); - goto INSUF_BUF_EXIT; - } - len += rv; - - rv = QDMA_SNPRINTF_S(buf + len, (buf_sz - len), - DEBGFS_LINE_SZ, "\n%40s", - "Prefetch Context"); - if ((rv < 0) || (rv > DEBGFS_LINE_SZ)) { - qdma_log_error( - "%d:%s QDMA_SNPRINTF_S() failed, err:%d\n", - __LINE__, __func__, - rv); - goto INSUF_BUF_EXIT; - } - len += rv; - - rv = QDMA_SNPRINTF_S(buf + len, (buf_sz - len), - DEBGFS_LINE_SZ, "\n%s\n", banner); - if ((rv < 0) || (rv > DEBGFS_LINE_SZ)) { - qdma_log_error( - "%d:%s QDMA_SNPRINTF_S() failed, err:%d\n", - __LINE__, __func__, - rv); - goto INSUF_BUF_EXIT; - } - len += rv; - } - - rv = QDMA_SNPRINTF_S(buf + len, (buf_sz - len), - DEBGFS_LINE_SZ, - "%-47s %#-10x %u\n", - qdma_s80_hard_c2h_pftch_ctxt_entries[i].name, - qdma_s80_hard_c2h_pftch_ctxt_entries[i].value, - qdma_s80_hard_c2h_pftch_ctxt_entries[i].value); - if ((rv < 0) || (rv > DEBGFS_LINE_SZ)) { - qdma_log_error( - "%d:%s QDMA_SNPRINTF_S() failed, err:%d\n", - __LINE__, __func__, - rv); - goto INSUF_BUF_EXIT; - } - len += rv; - } - } - - return len; - -INSUF_BUF_EXIT: - if (buf_sz > DEBGFS_LINE_SZ) { - rv = QDMA_SNPRINTF_S((buf + buf_sz - DEBGFS_LINE_SZ), - buf_sz, DEBGFS_LINE_SZ, - "\n\nInsufficient buffer size, partial context dump\n"); - if ((rv < 0) || (rv > DEBGFS_LINE_SZ)) { - qdma_log_error( - "%d:%s QDMA_SNPRINTF_S() failed, err:%d\n", - __LINE__, __func__, - rv); - } - } - - qdma_log_error("%s: Insufficient buffer size, err:%d\n", - __func__, -QDMA_ERR_NO_MEM); - - return -QDMA_ERR_NO_MEM; -} - -static int dump_s80_hard_intr_context(struct qdma_indirect_intr_ctxt *intr_ctx, - int ring_index, - char *buf, int buf_sz) -{ - int i = 0; - int n; - int len = 0; - int rv; - char banner[DEBGFS_LINE_SZ]; - - qdma_s80_hard_fill_intr_ctxt(intr_ctx); - - for (i = 0; i < DEBGFS_LINE_SZ - 5; i++) { - rv = QDMA_SNPRINTF_S(banner + i, - (DEBGFS_LINE_SZ - i), - sizeof("-"), "-"); - if ((rv < 0) || (rv > (int)sizeof("-"))) { - qdma_log_error( - "%d:%s QDMA_SNPRINTF_S() failed, err:%d\n", - __LINE__, __func__, - rv); - goto INSUF_BUF_EXIT; - } - } - - /* Interrupt context dump */ - n = sizeof(qdma_s80_hard_ind_intr_ctxt_entries) / - sizeof((qdma_s80_hard_ind_intr_ctxt_entries)[0]); - for (i = 0; i < n; i++) { - if ((len >= buf_sz) || ((len + DEBGFS_LINE_SZ) >= buf_sz)) - goto INSUF_BUF_EXIT; - - if (i == 0) { - if ((len + (3 * DEBGFS_LINE_SZ)) >= buf_sz) - goto INSUF_BUF_EXIT; - - rv = QDMA_SNPRINTF_S(buf + len, (buf_sz - len), - DEBGFS_LINE_SZ, "\n%s", banner); - if ((rv < 0) || (rv > DEBGFS_LINE_SZ)) { - qdma_log_error( - "%d:%s QDMA_SNPRINTF_S() failed, err:%d\n", - __LINE__, __func__, - rv); - goto INSUF_BUF_EXIT; - } - len += rv; - - rv = QDMA_SNPRINTF_S(buf + len, (buf_sz - len), - DEBGFS_LINE_SZ, "\n%50s %d", - "Interrupt Context for ring#", ring_index); - if ((rv < 0) || (rv > DEBGFS_LINE_SZ)) { - qdma_log_error( - "%d:%s QDMA_SNPRINTF_S() failed, err:%d\n", - __LINE__, __func__, - rv); - goto INSUF_BUF_EXIT; - } - len += rv; - - rv = QDMA_SNPRINTF_S(buf + len, (buf_sz - len), - DEBGFS_LINE_SZ, "\n%s\n", banner); - if ((rv < 0) || (rv > DEBGFS_LINE_SZ)) { - qdma_log_error( - "%d:%s QDMA_SNPRINTF_S() failed, err:%d\n", - __LINE__, __func__, - rv); - goto INSUF_BUF_EXIT; - } - len += rv; - } - - rv = QDMA_SNPRINTF_S(buf + len, (buf_sz - len), DEBGFS_LINE_SZ, - "%-47s %#-10x %u\n", - qdma_s80_hard_ind_intr_ctxt_entries[i].name, - qdma_s80_hard_ind_intr_ctxt_entries[i].value, - qdma_s80_hard_ind_intr_ctxt_entries[i].value); - if ((rv < 0) || (rv > DEBGFS_LINE_SZ)) { - qdma_log_error( - "%d:%s QDMA_SNPRINTF_S() failed, err:%d\n", - __LINE__, __func__, - rv); - goto INSUF_BUF_EXIT; - } - len += rv; - } - - return len; - -INSUF_BUF_EXIT: - if (buf_sz > DEBGFS_LINE_SZ) { - rv = QDMA_SNPRINTF_S((buf + buf_sz - DEBGFS_LINE_SZ), - buf_sz, DEBGFS_LINE_SZ, - "\n\nInsufficient buffer size, partial intr context dump\n"); - if ((rv < 0) || (rv > DEBGFS_LINE_SZ)) { - qdma_log_error( - "%d:%s QDMA_SNPRINTF_S() failed, err:%d\n", - __LINE__, __func__, - rv); - } - } - - qdma_log_error("%s: Insufficient buffer size, err:%d\n", - __func__, -QDMA_ERR_NO_MEM); - - return -QDMA_ERR_NO_MEM; -} - -/* - * qdma_s80_hard_indirect_reg_invalidate() - helper function to invalidate - * indirect context registers. - * - * return -QDMA_ERR_HWACC_BUSY_TIMEOUT if register - * value didn't match, QDMA_SUCCESS other wise - */ -static int qdma_s80_hard_indirect_reg_invalidate(void *dev_hndl, - enum ind_ctxt_cmd_sel sel, uint16_t hw_qid) -{ - union qdma_s80_hard_ind_ctxt_cmd cmd; - - qdma_reg_access_lock(dev_hndl); - - /* set command register */ - cmd.word = 0; - cmd.bits.qid = hw_qid; - cmd.bits.op = QDMA_CTXT_CMD_INV; - cmd.bits.sel = sel; - qdma_reg_write(dev_hndl, QDMA_S80_HARD_IND_CTXT_CMD_ADDR, cmd.word); - - /* check if the operation went through well */ - if (hw_monitor_reg(dev_hndl, QDMA_S80_HARD_IND_CTXT_CMD_ADDR, - IND_CTXT_CMD_BUSY_MASK, 0, - QDMA_REG_POLL_DFLT_INTERVAL_US, - QDMA_REG_POLL_DFLT_TIMEOUT_US)) { - qdma_reg_access_release(dev_hndl); - qdma_log_error("%s: hw_monitor_reg failed, err:%d\n", - __func__, - -QDMA_ERR_HWACC_BUSY_TIMEOUT); - return -QDMA_ERR_HWACC_BUSY_TIMEOUT; - } - - qdma_reg_access_release(dev_hndl); - - return QDMA_SUCCESS; -} - -/* - * qdma_s80_hard_indirect_reg_clear() - helper function to clear indirect - * context registers. - * - * return -QDMA_ERR_HWACC_BUSY_TIMEOUT if register - * value didn't match, QDMA_SUCCESS other wise - */ -static int qdma_s80_hard_indirect_reg_clear(void *dev_hndl, - enum ind_ctxt_cmd_sel sel, uint16_t hw_qid) -{ - union qdma_s80_hard_ind_ctxt_cmd cmd; - - qdma_reg_access_lock(dev_hndl); - - /* set command register */ - cmd.word = 0; - cmd.bits.qid = hw_qid; - cmd.bits.op = QDMA_CTXT_CMD_CLR; - cmd.bits.sel = sel; - - qdma_reg_write(dev_hndl, QDMA_S80_HARD_IND_CTXT_CMD_ADDR, cmd.word); - - /* check if the operation went through well */ - if (hw_monitor_reg(dev_hndl, QDMA_S80_HARD_IND_CTXT_CMD_ADDR, - IND_CTXT_CMD_BUSY_MASK, 0, - QDMA_REG_POLL_DFLT_INTERVAL_US, - QDMA_REG_POLL_DFLT_TIMEOUT_US)) { - qdma_reg_access_release(dev_hndl); - qdma_log_error("%s: hw_monitor_reg failed, err:%d\n", - __func__, - -QDMA_ERR_HWACC_BUSY_TIMEOUT); - return -QDMA_ERR_HWACC_BUSY_TIMEOUT; - } - - qdma_reg_access_release(dev_hndl); - - return QDMA_SUCCESS; -} - -/* - * qdma_s80_hard_indirect_reg_read() - helper function to read indirect - * context registers. - * - * return -QDMA_ERR_HWACC_BUSY_TIMEOUT if register - * value didn't match, QDMA_SUCCESS other wise - */ -static int qdma_s80_hard_indirect_reg_read(void *dev_hndl, - enum ind_ctxt_cmd_sel sel, - uint16_t hw_qid, uint32_t cnt, uint32_t *data) -{ - uint32_t index = 0, reg_addr = QDMA_S80_HARD_IND_CTXT_DATA_3_ADDR; - union qdma_s80_hard_ind_ctxt_cmd cmd; - - qdma_reg_access_lock(dev_hndl); - - /* set command register */ - cmd.word = 0; - cmd.bits.qid = hw_qid; - cmd.bits.op = QDMA_CTXT_CMD_RD; - cmd.bits.sel = sel; - qdma_reg_write(dev_hndl, QDMA_S80_HARD_IND_CTXT_CMD_ADDR, cmd.word); - - /* check if the operation went through well */ - if (hw_monitor_reg(dev_hndl, QDMA_S80_HARD_IND_CTXT_CMD_ADDR, - IND_CTXT_CMD_BUSY_MASK, 0, - QDMA_REG_POLL_DFLT_INTERVAL_US, - QDMA_REG_POLL_DFLT_TIMEOUT_US)) { - qdma_reg_access_release(dev_hndl); - qdma_log_error("%s: hw_monitor_reg failed, err:%d\n", - __func__, - -QDMA_ERR_HWACC_BUSY_TIMEOUT); - return -QDMA_ERR_HWACC_BUSY_TIMEOUT; - } - - for (index = 0; index < cnt; index++, reg_addr += sizeof(uint32_t)) - data[index] = qdma_reg_read(dev_hndl, reg_addr); - - qdma_reg_access_release(dev_hndl); - - return QDMA_SUCCESS; -} - -/* - * qdma_s80_hard_indirect_reg_write() - helper function to write indirect - * context registers. - * - * return -QDMA_ERR_HWACC_BUSY_TIMEOUT if register - * value didn't match, QDMA_SUCCESS other wise - */ -static int qdma_s80_hard_indirect_reg_write(void *dev_hndl, - enum ind_ctxt_cmd_sel sel, - uint16_t hw_qid, uint32_t *data, uint16_t cnt) -{ - uint32_t index, reg_addr; - struct qdma_s80_hard_indirect_ctxt_regs regs; - uint32_t *wr_data = (uint32_t *)®s; - - qdma_reg_access_lock(dev_hndl); - - /* write the context data */ - for (index = 0; index < QDMA_S80_HARD_IND_CTXT_DATA_NUM_REGS; - index++) { - if (index < cnt) - regs.qdma_ind_ctxt_data[index] = data[index]; - else - regs.qdma_ind_ctxt_data[index] = 0; - regs.qdma_ind_ctxt_mask[index] = 0xFFFFFFFF; - } - - regs.cmd.word = 0; - regs.cmd.bits.qid = hw_qid; - regs.cmd.bits.op = QDMA_CTXT_CMD_WR; - regs.cmd.bits.sel = sel; - reg_addr = QDMA_S80_HARD_IND_CTXT_DATA_3_ADDR; - - for (index = 0; - index < ((2 * QDMA_S80_HARD_IND_CTXT_DATA_NUM_REGS) + 1); - index++, reg_addr += sizeof(uint32_t)) - qdma_reg_write(dev_hndl, reg_addr, wr_data[index]); - - /* check if the operation went through well */ - if (hw_monitor_reg(dev_hndl, QDMA_S80_HARD_IND_CTXT_CMD_ADDR, - IND_CTXT_CMD_BUSY_MASK, 0, - QDMA_REG_POLL_DFLT_INTERVAL_US, - QDMA_REG_POLL_DFLT_TIMEOUT_US)) { - qdma_reg_access_release(dev_hndl); - qdma_log_error("%s: hw_monitor_reg failed, err:%d\n", - __func__, - -QDMA_ERR_HWACC_BUSY_TIMEOUT); - return -QDMA_ERR_HWACC_BUSY_TIMEOUT; - } - - qdma_reg_access_release(dev_hndl); - - return QDMA_SUCCESS; -} - -/*****************************************************************************/ -/** - * qdma_s80_hard_qid2vec_write() - create qid2vec context and program it - * - * @dev_hndl: device handle - * @c2h: is c2h queue - * @hw_qid: hardware qid of the queue - * @ctxt: pointer to the context data - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -static int qdma_s80_hard_qid2vec_write(void *dev_hndl, uint8_t c2h, - uint16_t hw_qid, struct qdma_qid2vec *ctxt) -{ - uint32_t qid2vec = 0; - enum ind_ctxt_cmd_sel sel = QDMA_CTXT_SEL_FMAP; - int rv = 0; - - if (!dev_hndl || !ctxt) { - qdma_log_error("%s: dev_hndl=%p qid2vec=%p, err:%d\n", - __func__, dev_hndl, ctxt, -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - rv = qdma_s80_hard_indirect_reg_read(dev_hndl, sel, hw_qid, - 1, &qid2vec); - if (rv < 0) - return rv; - if (c2h) { - qid2vec = qid2vec & (QDMA_S80_HARD_QID2VEC_H2C_VECTOR | - QDMA_S80_HARD_QID2VEC_H2C_COAL_EN); - qid2vec |= FIELD_SET(C2H_QID2VEC_MAP_C2H_VECTOR_MASK, - ctxt->c2h_vector) | - FIELD_SET(C2H_QID2VEC_MAP_C2H_EN_COAL_MASK, - ctxt->c2h_en_coal); - } else { - qid2vec = qid2vec & (C2H_QID2VEC_MAP_C2H_VECTOR_MASK | - C2H_QID2VEC_MAP_C2H_EN_COAL_MASK); - qid2vec |= - FIELD_SET(QDMA_S80_HARD_QID2VEC_H2C_VECTOR, - ctxt->h2c_vector) | - FIELD_SET(QDMA_S80_HARD_QID2VEC_H2C_COAL_EN, - ctxt->h2c_en_coal); - } - - return qdma_s80_hard_indirect_reg_write(dev_hndl, sel, hw_qid, - &qid2vec, QDMA_S80_HARD_QID2VEC_CONTEXT_NUM_WORDS); - -} - -/*****************************************************************************/ -/** - * qdma_s80_hard_qid2vec_read() - read qid2vec context - * - * @dev_hndl: device handle - * @c2h: is c2h queue - * @hw_qid: hardware qid of the queue - * @ctxt: pointer to the context data - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -static int qdma_s80_hard_qid2vec_read(void *dev_hndl, uint8_t c2h, - uint16_t hw_qid, struct qdma_qid2vec *ctxt) -{ - int rv = 0; - uint32_t qid2vec[QDMA_S80_HARD_QID2VEC_CONTEXT_NUM_WORDS] = {0}; - enum ind_ctxt_cmd_sel sel = QDMA_CTXT_SEL_FMAP; - - if (!dev_hndl || !ctxt) { - qdma_log_error("%s: dev_hndl=%p qid2vec=%p, err:%d\n", - __func__, dev_hndl, ctxt, -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - rv = qdma_s80_hard_indirect_reg_read(dev_hndl, sel, hw_qid, - QDMA_S80_HARD_QID2VEC_CONTEXT_NUM_WORDS, qid2vec); - if (rv < 0) - return rv; - - if (c2h) { - ctxt->c2h_vector = FIELD_GET(C2H_QID2VEC_MAP_C2H_VECTOR_MASK, - qid2vec[0]); - ctxt->c2h_en_coal = - (uint8_t)(FIELD_GET(C2H_QID2VEC_MAP_C2H_EN_COAL_MASK, - qid2vec[0])); - } else { - ctxt->h2c_vector = - (uint8_t)(FIELD_GET(QDMA_S80_HARD_QID2VEC_H2C_VECTOR, - qid2vec[0])); - ctxt->h2c_en_coal = - (uint8_t)(FIELD_GET(QDMA_S80_HARD_QID2VEC_H2C_COAL_EN, - qid2vec[0])); - } - - return QDMA_SUCCESS; -} - -/*****************************************************************************/ -/** - * qdma_s80_hard_qid2vec_clear() - clear qid2vec context - * - * @dev_hndl: device handle - * @hw_qid: hardware qid of the queue - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -static int qdma_s80_hard_qid2vec_clear(void *dev_hndl, uint16_t hw_qid) -{ - enum ind_ctxt_cmd_sel sel = QDMA_CTXT_SEL_FMAP; - - if (!dev_hndl) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - return qdma_s80_hard_indirect_reg_clear(dev_hndl, sel, hw_qid); -} - -/*****************************************************************************/ -/** - * qdma_s80_hard_qid2vec_invalidate() - invalidate qid2vec context - * - * @dev_hndl: device handle - * @hw_qid: hardware qid of the queue - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -static int qdma_s80_hard_qid2vec_invalidate(void *dev_hndl, uint16_t hw_qid) -{ - enum ind_ctxt_cmd_sel sel = QDMA_CTXT_SEL_FMAP; - - if (!dev_hndl) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - return qdma_s80_hard_indirect_reg_invalidate(dev_hndl, sel, hw_qid); -} - -/*****************************************************************************/ -/** - * qdma_s80_hard_qid2vec_conf() - configure qid2vector context - * - * @dev_hndl: device handle - * @c2h: is c2h queue - * @hw_qid: hardware qid of the queue - * @ctxt: pointer to the context data - * @access_type HW access type (qdma_hw_access_type enum) value - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -int qdma_s80_hard_qid2vec_conf(void *dev_hndl, uint8_t c2h, uint16_t hw_qid, - struct qdma_qid2vec *ctxt, - enum qdma_hw_access_type access_type) -{ - int ret_val = 0; - - switch (access_type) { - case QDMA_HW_ACCESS_READ: - ret_val = qdma_s80_hard_qid2vec_read(dev_hndl, c2h, - hw_qid, ctxt); - break; - case QDMA_HW_ACCESS_WRITE: - ret_val = qdma_s80_hard_qid2vec_write(dev_hndl, c2h, - hw_qid, ctxt); - break; - case QDMA_HW_ACCESS_CLEAR: - ret_val = qdma_s80_hard_qid2vec_clear(dev_hndl, hw_qid); - break; - case QDMA_HW_ACCESS_INVALIDATE: - ret_val = qdma_s80_hard_qid2vec_invalidate(dev_hndl, hw_qid); - break; - default: - qdma_log_error("%s: access_type=%d is invalid, err:%d\n", - __func__, access_type, - -QDMA_ERR_INV_PARAM); - ret_val = -QDMA_ERR_INV_PARAM; - break; - } - - return ret_val; -} - -/*****************************************************************************/ -/** - * qdma_s80_hard_fmap_write() - create fmap context and program it - * - * @dev_hndl: device handle - * @func_id: function id of the device - * @config: pointer to the fmap data strucutre - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -static int qdma_s80_hard_fmap_write(void *dev_hndl, uint16_t func_id, - const struct qdma_fmap_cfg *config) -{ - uint32_t fmap = 0; - - if (!dev_hndl || !config) { - qdma_log_error("%s: dev_handle or config is NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - fmap = FIELD_SET(TRQ_SEL_FMAP_0_QID_BASE_MASK, config->qbase) | - FIELD_SET(TRQ_SEL_FMAP_0_QID_MAX_MASK, - config->qmax); - - qdma_reg_write(dev_hndl, QDMA_S80_HARD_TRQ_SEL_FMAP_0_ADDR + - func_id * QDMA_S80_HARD_REG_TRQ_SEL_FMAP_STEP, - fmap); - return QDMA_SUCCESS; -} - -/*****************************************************************************/ -/** - * qdma_s80_hard_fmap_read() - read fmap context - * - * @dev_hndl: device handle - * @func_id: function id of the device - * @config: pointer to the output fmap data - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -static int qdma_s80_hard_fmap_read(void *dev_hndl, uint16_t func_id, - struct qdma_fmap_cfg *config) -{ - uint32_t fmap = 0; - - if (!dev_hndl || !config) { - qdma_log_error("%s: dev_handle=%p fmap=%p NULL, err:%d\n", - __func__, dev_hndl, config, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - fmap = qdma_reg_read(dev_hndl, QDMA_S80_HARD_TRQ_SEL_FMAP_0_ADDR + - func_id * QDMA_S80_HARD_REG_TRQ_SEL_FMAP_STEP); - - config->qbase = FIELD_GET(TRQ_SEL_FMAP_0_QID_BASE_MASK, fmap); - config->qmax = - (uint16_t)(FIELD_GET(TRQ_SEL_FMAP_0_QID_MAX_MASK, - fmap)); - - return QDMA_SUCCESS; -} - -/*****************************************************************************/ -/** - * qdma_s80_hard_fmap_clear() - clear fmap context - * - * @dev_hndl: device handle - * @func_id: function id of the device - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -static int qdma_s80_hard_fmap_clear(void *dev_hndl, uint16_t func_id) -{ - uint32_t fmap = 0; - - if (!dev_hndl) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - qdma_reg_write(dev_hndl, QDMA_S80_HARD_TRQ_SEL_FMAP_0_ADDR + - func_id * QDMA_S80_HARD_REG_TRQ_SEL_FMAP_STEP, - fmap); - - return QDMA_SUCCESS; -} - -/*****************************************************************************/ -/** - * qdma_s80_hard_fmap_conf() - configure fmap context - * - * @dev_hndl: device handle - * @func_id: function id of the device - * @config: pointer to the fmap data - * @access_type HW access type (qdma_hw_access_type enum) value - * QDMA_HW_ACCESS_INVALIDATE unsupported - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -int qdma_s80_hard_fmap_conf(void *dev_hndl, uint16_t func_id, - struct qdma_fmap_cfg *config, - enum qdma_hw_access_type access_type) -{ - int ret_val = 0; - - switch (access_type) { - case QDMA_HW_ACCESS_READ: - ret_val = qdma_s80_hard_fmap_read(dev_hndl, func_id, config); - break; - case QDMA_HW_ACCESS_WRITE: - ret_val = qdma_s80_hard_fmap_write(dev_hndl, func_id, config); - break; - case QDMA_HW_ACCESS_CLEAR: - ret_val = qdma_s80_hard_fmap_clear(dev_hndl, func_id); - break; - case QDMA_HW_ACCESS_INVALIDATE: - default: - qdma_log_error("%s: access_type=%d is invalid, err:%d\n", - __func__, access_type, - -QDMA_ERR_INV_PARAM); - ret_val = -QDMA_ERR_INV_PARAM; - break; - } - - return ret_val; -} - -/*****************************************************************************/ -/** - * qdma_s80_hard_sw_context_write() - create sw context and program it - * - * @dev_hndl: device handle - * @c2h: is c2h queue - * @hw_qid: hardware qid of the queue - * @ctxt: pointer to the SW context data strucutre - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -static int qdma_s80_hard_sw_context_write(void *dev_hndl, uint8_t c2h, - uint16_t hw_qid, - const struct qdma_descq_sw_ctxt *ctxt) -{ - uint32_t sw_ctxt[QDMA_S80_HARD_SW_CONTEXT_NUM_WORDS] = {0}; - uint16_t num_words_count = 0; - enum ind_ctxt_cmd_sel sel = c2h ? - QDMA_CTXT_SEL_SW_C2H : QDMA_CTXT_SEL_SW_H2C; - - /* Input args check */ - if (!dev_hndl || !ctxt) { - qdma_log_error("%s: dev_hndl or ctxt is NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - if ((ctxt->desc_sz > QDMA_DESC_SIZE_64B) || - (ctxt->rngsz_idx >= QDMA_NUM_RING_SIZES)) { - qdma_log_error("%s: Invalid desc_sz(%d)/rngidx(%d), err:%d\n", - __func__, - ctxt->desc_sz, - ctxt->rngsz_idx, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - sw_ctxt[num_words_count++] = - FIELD_SET(SW_IND_CTXT_DATA_W0_PIDX_MASK, ctxt->pidx) | - FIELD_SET(SW_IND_CTXT_DATA_W0_IRQ_ARM_MASK, ctxt->irq_arm); - - sw_ctxt[num_words_count++] = - FIELD_SET(SW_IND_CTXT_DATA_W1_QEN_MASK, ctxt->qen) | - FIELD_SET(SW_IND_CTXT_DATA_W1_FCRD_EN_MASK, ctxt->frcd_en) | - FIELD_SET(SW_IND_CTXT_DATA_W1_WBI_CHK_MASK, ctxt->wbi_chk) | - FIELD_SET(SW_IND_CTXT_DATA_W1_WBI_INTVL_EN_MASK, - ctxt->wbi_intvl_en) | - FIELD_SET(SW_IND_CTXT_DATA_W1_FNC_ID_MASK, ctxt->fnc_id) | - FIELD_SET(SW_IND_CTXT_DATA_W1_RNG_SZ_MASK, ctxt->rngsz_idx) | - FIELD_SET(SW_IND_CTXT_DATA_W1_DSC_SZ_MASK, ctxt->desc_sz) | - FIELD_SET(SW_IND_CTXT_DATA_W1_BYPASS_MASK, ctxt->bypass) | - FIELD_SET(SW_IND_CTXT_DATA_W1_MM_CHN_MASK, ctxt->mm_chn) | - FIELD_SET(SW_IND_CTXT_DATA_W1_WBK_EN_MASK, ctxt->wbk_en) | - FIELD_SET(SW_IND_CTXT_DATA_W1_IRQ_EN_MASK, ctxt->irq_en) | - FIELD_SET(SW_IND_CTXT_DATA_W1_PORT_ID_MASK, ctxt->port_id) | - FIELD_SET(SW_IND_CTXT_DATA_W1_IRQ_NO_LAST_MASK, - ctxt->irq_no_last) | - FIELD_SET(SW_IND_CTXT_DATA_W1_ERR_MASK, ctxt->err) | - FIELD_SET(SW_IND_CTXT_DATA_W1_ERR_WB_SENT_MASK, - ctxt->err_wb_sent) | - FIELD_SET(SW_IND_CTXT_DATA_W1_IRQ_REQ_MASK, ctxt->irq_req) | - FIELD_SET(SW_IND_CTXT_DATA_W1_MRKR_DIS_MASK, ctxt->mrkr_dis) | - FIELD_SET(SW_IND_CTXT_DATA_W1_IS_MM_MASK, ctxt->is_mm); - - sw_ctxt[num_words_count++] = ctxt->ring_bs_addr & 0xffffffff; - sw_ctxt[num_words_count++] = (ctxt->ring_bs_addr >> 32) & 0xffffffff; - - return qdma_s80_hard_indirect_reg_write(dev_hndl, sel, hw_qid, - sw_ctxt, num_words_count); -} - -/*****************************************************************************/ -/** - * qdma_s80_hard_sw_context_read() - read sw context - * - * @dev_hndl: device handle - * @c2h: is c2h queue - * @hw_qid: hardware qid of the queue - * @ctxt: pointer to the output context data - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -static int qdma_s80_hard_sw_context_read(void *dev_hndl, uint8_t c2h, - uint16_t hw_qid, - struct qdma_descq_sw_ctxt *ctxt) -{ - int rv = 0; - uint32_t sw_ctxt[QDMA_S80_HARD_SW_CONTEXT_NUM_WORDS] = {0}; - enum ind_ctxt_cmd_sel sel = c2h ? - QDMA_CTXT_SEL_SW_C2H : QDMA_CTXT_SEL_SW_H2C; - struct qdma_qid2vec qid2vec_ctxt = {0}; - - if (!dev_hndl || !ctxt) { - qdma_log_error("%s: dev_hndl=%p sw_ctxt=%p, err:%d\n", - __func__, dev_hndl, ctxt, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - rv = qdma_s80_hard_indirect_reg_read(dev_hndl, sel, hw_qid, - QDMA_S80_HARD_SW_CONTEXT_NUM_WORDS, sw_ctxt); - if (rv < 0) - return rv; - - ctxt->pidx = FIELD_GET(SW_IND_CTXT_DATA_W0_PIDX_MASK, sw_ctxt[0]); - ctxt->irq_arm = - (uint8_t)(FIELD_GET(SW_IND_CTXT_DATA_W0_IRQ_ARM_MASK, - sw_ctxt[0])); - - ctxt->qen = FIELD_GET(SW_IND_CTXT_DATA_W1_QEN_MASK, sw_ctxt[1]); - ctxt->frcd_en = FIELD_GET(SW_IND_CTXT_DATA_W1_FCRD_EN_MASK, - sw_ctxt[1]); - ctxt->wbi_chk = FIELD_GET(SW_IND_CTXT_DATA_W1_WBI_CHK_MASK, - sw_ctxt[1]); - ctxt->wbi_intvl_en = - FIELD_GET(SW_IND_CTXT_DATA_W1_WBI_INTVL_EN_MASK, - sw_ctxt[1]); - ctxt->fnc_id = - (uint8_t)(FIELD_GET(SW_IND_CTXT_DATA_W1_FNC_ID_MASK, - sw_ctxt[1])); - ctxt->rngsz_idx = - (uint8_t)(FIELD_GET(SW_IND_CTXT_DATA_W1_RNG_SZ_MASK, - sw_ctxt[1])); - ctxt->desc_sz = - (uint8_t)(FIELD_GET(SW_IND_CTXT_DATA_W1_DSC_SZ_MASK, - sw_ctxt[1])); - ctxt->bypass = - (uint8_t)(FIELD_GET(SW_IND_CTXT_DATA_W1_BYPASS_MASK, - sw_ctxt[1])); - ctxt->mm_chn = - (uint8_t)(FIELD_GET(SW_IND_CTXT_DATA_W1_MM_CHN_MASK, - sw_ctxt[1])); - ctxt->wbk_en = - (uint8_t)(FIELD_GET(SW_IND_CTXT_DATA_W1_WBK_EN_MASK, - sw_ctxt[1])); - ctxt->irq_en = - (uint8_t)(FIELD_GET(SW_IND_CTXT_DATA_W1_IRQ_EN_MASK, - sw_ctxt[1])); - ctxt->port_id = - (uint8_t)(FIELD_GET(SW_IND_CTXT_DATA_W1_PORT_ID_MASK, - sw_ctxt[1])); - ctxt->irq_no_last = - (uint8_t)(FIELD_GET(SW_IND_CTXT_DATA_W1_IRQ_NO_LAST_MASK, - sw_ctxt[1])); - ctxt->err = - (uint8_t)(FIELD_GET(SW_IND_CTXT_DATA_W1_ERR_MASK, sw_ctxt[1])); - ctxt->err_wb_sent = - (uint8_t)(FIELD_GET(SW_IND_CTXT_DATA_W1_ERR_WB_SENT_MASK, - sw_ctxt[1])); - ctxt->irq_req = - (uint8_t)(FIELD_GET(SW_IND_CTXT_DATA_W1_IRQ_REQ_MASK, - sw_ctxt[1])); - ctxt->mrkr_dis = - (uint8_t)(FIELD_GET(SW_IND_CTXT_DATA_W1_MRKR_DIS_MASK, - sw_ctxt[1])); - ctxt->is_mm = - (uint8_t)(FIELD_GET(SW_IND_CTXT_DATA_W1_IS_MM_MASK, - sw_ctxt[1])); - - ctxt->ring_bs_addr = ((uint64_t)sw_ctxt[3] << 32) | (sw_ctxt[2]); - - /** Read the QID2VEC Context Data */ - rv = qdma_s80_hard_qid2vec_read(dev_hndl, c2h, hw_qid, &qid2vec_ctxt); - if (rv < 0) - return rv; - - if (c2h) { - ctxt->vec = qid2vec_ctxt.c2h_vector; - ctxt->intr_aggr = qid2vec_ctxt.c2h_en_coal; - } else { - ctxt->vec = qid2vec_ctxt.h2c_vector; - ctxt->intr_aggr = qid2vec_ctxt.h2c_en_coal; - } - - - return QDMA_SUCCESS; -} - -/*****************************************************************************/ -/** - * qdma_s80_hard_sw_context_clear() - clear sw context - * - * @dev_hndl: device handle - * @c2h: is c2h queue - * @hw_qid: hardware qid of the queue - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -static int qdma_s80_hard_sw_context_clear(void *dev_hndl, uint8_t c2h, - uint16_t hw_qid) -{ - enum ind_ctxt_cmd_sel sel = c2h ? - QDMA_CTXT_SEL_SW_C2H : QDMA_CTXT_SEL_SW_H2C; - - if (!dev_hndl) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - return qdma_s80_hard_indirect_reg_clear(dev_hndl, sel, hw_qid); -} - -/*****************************************************************************/ -/** - * qdma_s80_hard_sw_context_invalidate() - invalidate sw context - * - * @dev_hndl: device handle - * @c2h: is c2h queue - * @hw_qid: hardware qid of the queue - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -static int qdma_s80_hard_sw_context_invalidate(void *dev_hndl, uint8_t c2h, - uint16_t hw_qid) -{ - enum ind_ctxt_cmd_sel sel = c2h ? - QDMA_CTXT_SEL_SW_C2H : QDMA_CTXT_SEL_SW_H2C; - - if (!dev_hndl) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - return qdma_s80_hard_indirect_reg_invalidate(dev_hndl, sel, hw_qid); -} - -/*****************************************************************************/ -/** - * qdma_s80_hard_sw_ctx_conf() - configure SW context - * - * @dev_hndl: device handle - * @c2h: is c2h queue - * @hw_qid: hardware qid of the queue - * @ctxt: pointer to the context data - * @access_type HW access type (qdma_hw_access_type enum) value - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -int qdma_s80_hard_sw_ctx_conf(void *dev_hndl, uint8_t c2h, uint16_t hw_qid, - struct qdma_descq_sw_ctxt *ctxt, - enum qdma_hw_access_type access_type) -{ - int ret_val = 0; - - switch (access_type) { - case QDMA_HW_ACCESS_READ: - ret_val = qdma_s80_hard_sw_context_read(dev_hndl, c2h, hw_qid, - ctxt); - break; - case QDMA_HW_ACCESS_WRITE: - ret_val = qdma_s80_hard_sw_context_write(dev_hndl, c2h, hw_qid, - ctxt); - break; - case QDMA_HW_ACCESS_CLEAR: - ret_val = qdma_s80_hard_sw_context_clear(dev_hndl, c2h, hw_qid); - break; - case QDMA_HW_ACCESS_INVALIDATE: - ret_val = qdma_s80_hard_sw_context_invalidate(dev_hndl, - c2h, hw_qid); - break; - default: - qdma_log_error("%s: access_type=%d is invalid, err:%d\n", - __func__, access_type, - -QDMA_ERR_INV_PARAM); - ret_val = -QDMA_ERR_INV_PARAM; - break; - } - return ret_val; -} - -/*****************************************************************************/ -/** - * qdma_s80_hard_pfetch_context_write() - create prefetch context and program it - * - * @dev_hndl: device handle - * @hw_qid: hardware qid of the queue - * @ctxt: pointer to the prefetch context data strucutre - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -static int qdma_s80_hard_pfetch_context_write(void *dev_hndl, uint16_t hw_qid, - const struct qdma_descq_prefetch_ctxt *ctxt) -{ - uint32_t pfetch_ctxt[QDMA_S80_HARD_PFETCH_CONTEXT_NUM_WORDS] = {0}; - enum ind_ctxt_cmd_sel sel = QDMA_CTXT_SEL_PFTCH; - uint32_t sw_crdt_l, sw_crdt_h; - uint16_t num_words_count = 0; - - if (!dev_hndl || !ctxt) { - qdma_log_error("%s: dev_hndl=%p pfetch_ctxt=%p, err:%d\n", - __func__, dev_hndl, ctxt, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - sw_crdt_l = - FIELD_GET(QDMA_PFTCH_CTXT_SW_CRDT_GET_L_MASK, ctxt->sw_crdt); - sw_crdt_h = - FIELD_GET(QDMA_PFTCH_CTXT_SW_CRDT_GET_H_MASK, ctxt->sw_crdt); - - pfetch_ctxt[num_words_count++] = - FIELD_SET(PREFETCH_CTXT_DATA_W0_BYPASS_MASK, ctxt->bypass) | - FIELD_SET(PREFETCH_CTXT_DATA_W0_BUF_SIZE_IDX_MASK, - ctxt->bufsz_idx) | - FIELD_SET(PREFETCH_CTXT_DATA_W0_PORT_ID_MASK, ctxt->port_id) | - FIELD_SET(PREFETCH_CTXT_DATA_W0_ERR_MASK, ctxt->err) | - FIELD_SET(PREFETCH_CTXT_DATA_W0_PFCH_EN_MASK, ctxt->pfch_en) | - FIELD_SET(PREFETCH_CTXT_DATA_W0_PFCH_MASK, ctxt->pfch) | - FIELD_SET(PREFETCH_CTXT_DATA_W0_SW_CRDT_L_MASK, sw_crdt_l); - - pfetch_ctxt[num_words_count++] = - FIELD_SET(PREFETCH_CTXT_DATA_W1_SW_CRDT_H_MASK, sw_crdt_h) | - FIELD_SET(PREFETCH_CTXT_DATA_W1_VALID_MASK, ctxt->valid); - - return qdma_s80_hard_indirect_reg_write(dev_hndl, sel, hw_qid, - pfetch_ctxt, num_words_count); -} - -/*****************************************************************************/ -/** - * qdma_s80_hard_pfetch_context_read() - read prefetch context - * - * @dev_hndl: device handle - * @hw_qid: hardware qid of the queue - * @ctxt: pointer to the output context data - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -static int qdma_s80_hard_pfetch_context_read(void *dev_hndl, uint16_t hw_qid, - struct qdma_descq_prefetch_ctxt *ctxt) -{ - int rv = 0; - uint32_t pfetch_ctxt[QDMA_S80_HARD_PFETCH_CONTEXT_NUM_WORDS] = {0}; - enum ind_ctxt_cmd_sel sel = QDMA_CTXT_SEL_PFTCH; - uint32_t sw_crdt_l, sw_crdt_h; - - if (!dev_hndl || !ctxt) { - qdma_log_error("%s: dev_hndl=%p pfetch_ctxt=%p, err:%d\n", - __func__, dev_hndl, ctxt, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - rv = qdma_s80_hard_indirect_reg_read(dev_hndl, sel, hw_qid, - QDMA_S80_HARD_PFETCH_CONTEXT_NUM_WORDS, pfetch_ctxt); - if (rv < 0) - return rv; - - ctxt->bypass = - (uint8_t)(FIELD_GET(PREFETCH_CTXT_DATA_W0_BYPASS_MASK, - pfetch_ctxt[0])); - ctxt->bufsz_idx = - (uint8_t)(FIELD_GET(PREFETCH_CTXT_DATA_W0_BUF_SIZE_IDX_MASK, - pfetch_ctxt[0])); - ctxt->port_id = - (uint8_t)(FIELD_GET(PREFETCH_CTXT_DATA_W0_PORT_ID_MASK, - pfetch_ctxt[0])); - ctxt->err = - (uint8_t)(FIELD_GET(PREFETCH_CTXT_DATA_W0_ERR_MASK, - pfetch_ctxt[0])); - ctxt->pfch_en = - (uint8_t)(FIELD_GET(PREFETCH_CTXT_DATA_W0_PFCH_EN_MASK, - pfetch_ctxt[0])); - ctxt->pfch = - (uint8_t)(FIELD_GET(PREFETCH_CTXT_DATA_W0_PFCH_MASK, - pfetch_ctxt[0])); - sw_crdt_l = - (uint32_t)FIELD_GET(PREFETCH_CTXT_DATA_W0_SW_CRDT_L_MASK, - pfetch_ctxt[0]); - - sw_crdt_h = - (uint32_t)FIELD_GET(PREFETCH_CTXT_DATA_W1_SW_CRDT_H_MASK, - pfetch_ctxt[1]); - ctxt->valid = - (uint8_t)(FIELD_GET(PREFETCH_CTXT_DATA_W1_VALID_MASK, - pfetch_ctxt[1])); - - ctxt->sw_crdt = - (uint16_t)(FIELD_SET(QDMA_PFTCH_CTXT_SW_CRDT_GET_L_MASK, - sw_crdt_l) | - FIELD_SET(QDMA_PFTCH_CTXT_SW_CRDT_GET_H_MASK, sw_crdt_h)); - - return QDMA_SUCCESS; -} - -/*****************************************************************************/ -/** - * qdma_s80_hard_pfetch_context_clear() - clear prefetch context - * - * @dev_hndl: device handle - * @hw_qid: hardware qid of the queue - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -static int qdma_s80_hard_pfetch_context_clear(void *dev_hndl, uint16_t hw_qid) -{ - enum ind_ctxt_cmd_sel sel = QDMA_CTXT_SEL_PFTCH; - - if (!dev_hndl) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - return qdma_s80_hard_indirect_reg_clear(dev_hndl, sel, hw_qid); -} - -/*****************************************************************************/ -/** - * qdma_s80_hard_pfetch_context_invalidate() - invalidate prefetch context - * - * @dev_hndl: device handle - * @hw_qid: hardware qid of the queue - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -static int qdma_s80_hard_pfetch_context_invalidate(void *dev_hndl, - uint16_t hw_qid) -{ - enum ind_ctxt_cmd_sel sel = QDMA_CTXT_SEL_PFTCH; - - if (!dev_hndl) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - return qdma_s80_hard_indirect_reg_invalidate(dev_hndl, sel, hw_qid); -} - -/*****************************************************************************/ -/** - * qdma_s80_hard_pfetch_ctx_conf() - configure prefetch context - * - * @dev_hndl: device handle - * @hw_qid: hardware qid of the queue - * @ctxt: pointer to context data - * @access_type HW access type (qdma_hw_access_type enum) value - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -int qdma_s80_hard_pfetch_ctx_conf(void *dev_hndl, uint16_t hw_qid, - struct qdma_descq_prefetch_ctxt *ctxt, - enum qdma_hw_access_type access_type) -{ - int ret_val = 0; - - switch (access_type) { - case QDMA_HW_ACCESS_READ: - ret_val = qdma_s80_hard_pfetch_context_read(dev_hndl, - hw_qid, ctxt); - break; - case QDMA_HW_ACCESS_WRITE: - ret_val = qdma_s80_hard_pfetch_context_write(dev_hndl, - hw_qid, ctxt); - break; - case QDMA_HW_ACCESS_CLEAR: - ret_val = qdma_s80_hard_pfetch_context_clear(dev_hndl, hw_qid); - break; - case QDMA_HW_ACCESS_INVALIDATE: - ret_val = qdma_s80_hard_pfetch_context_invalidate(dev_hndl, - hw_qid); - break; - default: - qdma_log_error("%s: access_type=%d is invalid, err:%d\n", - __func__, access_type, - -QDMA_ERR_INV_PARAM); - ret_val = -QDMA_ERR_INV_PARAM; - break; - } - - return ret_val; -} - -/*****************************************************************************/ -/** - * qdma_s80_hard_cmpt_context_write() - create completion context and program it - * - * @dev_hndl: device handle - * @hw_qid: hardware qid of the queue - * @ctxt: pointer to the cmpt context data strucutre - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -static int qdma_s80_hard_cmpt_context_write(void *dev_hndl, uint16_t hw_qid, - const struct qdma_descq_cmpt_ctxt *ctxt) -{ - uint32_t cmpt_ctxt[QDMA_S80_HARD_CMPT_CONTEXT_NUM_WORDS] = {0}; - uint16_t num_words_count = 0; - uint32_t baddr_l, baddr_h, baddr_m, pidx_l, pidx_h; - enum ind_ctxt_cmd_sel sel = QDMA_CTXT_SEL_CMPT; - - /* Input args check */ - if (!dev_hndl || !ctxt) { - qdma_log_error("%s: dev_hndl=%p cmpt_ctxt=%p, err:%d\n", - __func__, dev_hndl, ctxt, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - if ((ctxt->desc_sz > QDMA_DESC_SIZE_32B) || - (ctxt->ringsz_idx >= QDMA_NUM_RING_SIZES) || - (ctxt->counter_idx >= QDMA_NUM_C2H_COUNTERS) || - (ctxt->timer_idx >= QDMA_NUM_C2H_TIMERS) || - (ctxt->trig_mode > QDMA_CMPT_UPDATE_TRIG_MODE_TMR_CNTR)) { - qdma_log_error - ("%s Inv dsz(%d)/ridx(%d)/cntr(%d)/tmr(%d)/tm(%d), err:%d\n", - __func__, - ctxt->desc_sz, - ctxt->ringsz_idx, - ctxt->counter_idx, - ctxt->timer_idx, - ctxt->trig_mode, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - baddr_l = - (uint32_t)FIELD_GET(QDMA_S80_HARD_COMPL_CTXT_BADDR_GET_L_MASK, - ctxt->bs_addr); - baddr_m = - (uint32_t)FIELD_GET(QDMA_S80_HARD_COMPL_CTXT_BADDR_GET_M_MASK, - ctxt->bs_addr); - baddr_h = - (uint32_t)FIELD_GET(QDMA_S80_HARD_COMPL_CTXT_BADDR_GET_H_MASK, - ctxt->bs_addr); - - pidx_l = FIELD_GET(QDMA_S80_HARD_COMPL_CTXT_PIDX_GET_L_MASK, - ctxt->pidx); - pidx_h = FIELD_GET(QDMA_S80_HARD_COMPL_CTXT_PIDX_GET_H_MASK, - ctxt->pidx); - - cmpt_ctxt[num_words_count++] = - FIELD_SET(CMPL_CTXT_DATA_W0_EN_STAT_DESC_MASK, - ctxt->en_stat_desc) | - FIELD_SET(CMPL_CTXT_DATA_W0_EN_INT_MASK, ctxt->en_int) | - FIELD_SET(CMPL_CTXT_DATA_W0_TRIG_MODE_MASK, ctxt->trig_mode) | - FIELD_SET(CMPL_CTXT_DATA_W0_FNC_ID_MASK, ctxt->fnc_id) | - FIELD_SET(CMPL_CTXT_DATA_W0_CNTER_IDX_MASK, - ctxt->counter_idx) | - FIELD_SET(CMPL_CTXT_DATA_W0_TIMER_IDX_MASK, - ctxt->timer_idx) | - FIELD_SET(CMPL_CTXT_DATA_W0_INT_ST_MASK, - ctxt->in_st) | - FIELD_SET(CMPL_CTXT_DATA_W0_COLOR_MASK, - ctxt->color) | - FIELD_SET(CMPL_CTXT_DATA_W0_QSIZE_IDX_MASK, - ctxt->ringsz_idx) | - FIELD_SET(CMPL_CTXT_DATA_W0_BADDR_64_L_MASK, - baddr_l); - - cmpt_ctxt[num_words_count++] = - FIELD_SET(CMPL_CTXT_DATA_W1_BADDR_64_M_MASK, - baddr_m); - - cmpt_ctxt[num_words_count++] = - FIELD_SET(CMPL_CTXT_DATA_W2_BADDR_64_H_MASK, - baddr_h) | - FIELD_SET(CMPL_CTXT_DATA_W2_DESC_SIZE_MASK, - ctxt->desc_sz) | - FIELD_SET(CMPL_CTXT_DATA_W2_PIDX_L_MASK, - pidx_l); - - cmpt_ctxt[num_words_count++] = - FIELD_SET(CMPL_CTXT_DATA_W3_PIDX_H_MASK, - pidx_h) | - FIELD_SET(CMPL_CTXT_DATA_W3_CIDX_MASK, ctxt->cidx) | - FIELD_SET(CMPL_CTXT_DATA_W3_VALID_MASK, ctxt->valid) | - FIELD_SET(CMPL_CTXT_DATA_W3_ERR_MASK, ctxt->err) | - FIELD_SET(CMPL_CTXT_DATA_W3_USER_TRIG_PEND_MASK, - ctxt->user_trig_pend) | - FIELD_SET(CMPL_CTXT_DATA_W3_TIMER_RUNNING_MASK, - ctxt->timer_running) | - FIELD_SET(CMPL_CTXT_DATA_W3_FULL_UPD_MASK, - ctxt->full_upd); - - return qdma_s80_hard_indirect_reg_write(dev_hndl, sel, hw_qid, - cmpt_ctxt, num_words_count); - -} - -/*****************************************************************************/ -/** - * qdma_s80_hard_cmpt_context_read() - read completion context - * - * @dev_hndl: device handle - * @hw_qid: hardware qid of the queue - * @ctxt: pointer to the context data - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -static int qdma_s80_hard_cmpt_context_read(void *dev_hndl, uint16_t hw_qid, - struct qdma_descq_cmpt_ctxt *ctxt) -{ - int rv = 0; - uint32_t cmpt_ctxt[QDMA_S80_HARD_CMPT_CONTEXT_NUM_WORDS] = {0}; - enum ind_ctxt_cmd_sel sel = QDMA_CTXT_SEL_CMPT; - uint32_t baddr_l, baddr_h, baddr_m, - pidx_l, pidx_h; - - if (!dev_hndl || !ctxt) { - qdma_log_error("%s: dev_hndl=%p cmpt_ctxt=%p, err:%d\n", - __func__, dev_hndl, ctxt, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - rv = qdma_s80_hard_indirect_reg_read(dev_hndl, sel, hw_qid, - QDMA_S80_HARD_CMPT_CONTEXT_NUM_WORDS, cmpt_ctxt); - if (rv < 0) - return rv; - - ctxt->en_stat_desc = - FIELD_GET(CMPL_CTXT_DATA_W0_EN_STAT_DESC_MASK, cmpt_ctxt[0]); - ctxt->en_int = FIELD_GET(CMPL_CTXT_DATA_W0_EN_INT_MASK, - cmpt_ctxt[0]); - ctxt->trig_mode = - FIELD_GET(CMPL_CTXT_DATA_W0_TRIG_MODE_MASK, cmpt_ctxt[0]); - ctxt->fnc_id = - (uint8_t)(FIELD_GET(CMPL_CTXT_DATA_W0_FNC_ID_MASK, - cmpt_ctxt[0])); - ctxt->counter_idx = - (uint8_t)(FIELD_GET( - CMPL_CTXT_DATA_W0_CNTER_IDX_MASK, - cmpt_ctxt[0])); - ctxt->timer_idx = - (uint8_t)(FIELD_GET(CMPL_CTXT_DATA_W0_TIMER_IDX_MASK, - cmpt_ctxt[0])); - ctxt->in_st = - (uint8_t)(FIELD_GET(CMPL_CTXT_DATA_W0_INT_ST_MASK, - cmpt_ctxt[0])); - ctxt->color = - (uint8_t)(FIELD_GET(CMPL_CTXT_DATA_W0_COLOR_MASK, - cmpt_ctxt[0])); - ctxt->ringsz_idx = - (uint8_t)(FIELD_GET(CMPL_CTXT_DATA_W0_QSIZE_IDX_MASK, - cmpt_ctxt[0])); - - baddr_l = - FIELD_GET(CMPL_CTXT_DATA_W0_BADDR_64_L_MASK, - cmpt_ctxt[0]); - baddr_m = - FIELD_GET(CMPL_CTXT_DATA_W1_BADDR_64_M_MASK, - cmpt_ctxt[1]); - baddr_h = - FIELD_GET(CMPL_CTXT_DATA_W2_BADDR_64_H_MASK, - cmpt_ctxt[2]); - - ctxt->desc_sz = - (uint8_t)(FIELD_GET(CMPL_CTXT_DATA_W2_DESC_SIZE_MASK, - cmpt_ctxt[2])); - pidx_l = FIELD_GET(CMPL_CTXT_DATA_W2_PIDX_L_MASK, - cmpt_ctxt[2]); - - pidx_h = FIELD_GET(CMPL_CTXT_DATA_W3_PIDX_H_MASK, - cmpt_ctxt[3]); - ctxt->cidx = - (uint16_t)(FIELD_GET(CMPL_CTXT_DATA_W3_CIDX_MASK, - cmpt_ctxt[3])); - ctxt->valid = - (uint8_t)(FIELD_GET(CMPL_CTXT_DATA_W3_VALID_MASK, - cmpt_ctxt[3])); - ctxt->err = - (uint8_t)(FIELD_GET(CMPL_CTXT_DATA_W3_ERR_MASK, - cmpt_ctxt[3])); - ctxt->user_trig_pend = - (uint8_t)(FIELD_GET( - CMPL_CTXT_DATA_W3_USER_TRIG_PEND_MASK, cmpt_ctxt[3])); - - ctxt->timer_running = - (uint8_t)(FIELD_GET(CMPL_CTXT_DATA_W3_TIMER_RUNNING_MASK, - cmpt_ctxt[3])); - ctxt->full_upd = - (uint8_t)(FIELD_GET(CMPL_CTXT_DATA_W3_FULL_UPD_MASK, - cmpt_ctxt[3])); - - ctxt->bs_addr = - FIELD_SET(QDMA_S80_HARD_COMPL_CTXT_BADDR_GET_L_MASK, - (uint64_t)baddr_l) | - FIELD_SET(QDMA_S80_HARD_COMPL_CTXT_BADDR_GET_M_MASK, - (uint64_t)baddr_m) | - FIELD_SET(QDMA_S80_HARD_COMPL_CTXT_BADDR_GET_H_MASK, - (uint64_t)baddr_h); - - ctxt->pidx = - (uint16_t)(FIELD_SET(QDMA_S80_HARD_COMPL_CTXT_PIDX_GET_L_MASK, - pidx_l) | - FIELD_SET(QDMA_S80_HARD_COMPL_CTXT_PIDX_GET_H_MASK, - pidx_h)); - - return QDMA_SUCCESS; -} - -/*****************************************************************************/ -/** - * qdma_s80_hard_cmpt_context_clear() - clear completion context - * - * @dev_hndl: device handle - * @hw_qid: hardware qid of the queue - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -static int qdma_s80_hard_cmpt_context_clear(void *dev_hndl, uint16_t hw_qid) -{ - enum ind_ctxt_cmd_sel sel = QDMA_CTXT_SEL_CMPT; - - if (!dev_hndl) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - return qdma_s80_hard_indirect_reg_clear(dev_hndl, sel, hw_qid); -} - -/*****************************************************************************/ -/** - * qdma_s80_hard_cmpt_context_invalidate() - invalidate completion context - * - * @dev_hndl: device handle - * @hw_qid: hardware qid of the queue - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -static int qdma_s80_hard_cmpt_context_invalidate(void *dev_hndl, - uint16_t hw_qid) -{ - enum ind_ctxt_cmd_sel sel = QDMA_CTXT_SEL_CMPT; - - if (!dev_hndl) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - return qdma_s80_hard_indirect_reg_invalidate(dev_hndl, sel, hw_qid); -} - -/*****************************************************************************/ -/** - * qdma_s80_hard_cmpt_ctx_conf() - configure completion context - * - * @dev_hndl: device handle - * @hw_qid: hardware qid of the queue - * @ctxt: pointer to context data - * @access_type HW access type (qdma_hw_access_type enum) value - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -int qdma_s80_hard_cmpt_ctx_conf(void *dev_hndl, uint16_t hw_qid, - struct qdma_descq_cmpt_ctxt *ctxt, - enum qdma_hw_access_type access_type) -{ - int ret_val = 0; - - if (!dev_hndl) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - switch (access_type) { - case QDMA_HW_ACCESS_READ: - ret_val = qdma_s80_hard_cmpt_context_read(dev_hndl, - hw_qid, ctxt); - break; - case QDMA_HW_ACCESS_WRITE: - ret_val = qdma_s80_hard_cmpt_context_write(dev_hndl, - hw_qid, ctxt); - break; - case QDMA_HW_ACCESS_CLEAR: - ret_val = qdma_s80_hard_cmpt_context_clear(dev_hndl, hw_qid); - break; - case QDMA_HW_ACCESS_INVALIDATE: - ret_val = qdma_s80_hard_cmpt_context_invalidate(dev_hndl, - hw_qid); - break; - default: - qdma_log_error("%s: access_type=%d is invalid, err:%d\n", - __func__, access_type, - -QDMA_ERR_INV_PARAM); - ret_val = -QDMA_ERR_INV_PARAM; - break; - } - - return ret_val; -} - -/*****************************************************************************/ -/** - * qdma_s80_hard_hw_context_read() - read hardware context - * - * @dev_hndl: device handle - * @c2h: is c2h queue - * @hw_qid: hardware qid of the queue - * @ctxt: pointer to the output context data - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -static int qdma_s80_hard_hw_context_read(void *dev_hndl, uint8_t c2h, - uint16_t hw_qid, struct qdma_descq_hw_ctxt *ctxt) -{ - int rv = 0; - uint32_t hw_ctxt[QDMA_S80_HARD_HW_CONTEXT_NUM_WORDS] = {0}; - enum ind_ctxt_cmd_sel sel = c2h ? QDMA_CTXT_SEL_HW_C2H : - QDMA_CTXT_SEL_HW_H2C; - - if (!dev_hndl || !ctxt) { - qdma_log_error("%s: dev_hndl=%p hw_ctxt=%p, err:%d\n", - __func__, dev_hndl, ctxt, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - rv = qdma_s80_hard_indirect_reg_read(dev_hndl, sel, hw_qid, - QDMA_S80_HARD_HW_CONTEXT_NUM_WORDS, hw_ctxt); - if (rv < 0) - return rv; - - ctxt->cidx = FIELD_GET(HW_IND_CTXT_DATA_W0_CIDX_MASK, hw_ctxt[0]); - ctxt->crd_use = - (uint16_t)(FIELD_GET(HW_IND_CTXT_DATA_W0_CRD_USE_MASK, - hw_ctxt[0])); - - ctxt->dsc_pend = - (uint8_t)(FIELD_GET(HW_IND_CTXT_DATA_W1_DSC_PND_MASK, - hw_ctxt[1])); - ctxt->idl_stp_b = - (uint8_t)(FIELD_GET(HW_IND_CTXT_DATA_W1_IDL_STP_B_MASK, - hw_ctxt[1])); - ctxt->fetch_pnd = - (uint8_t)(FIELD_GET(HW_IND_CTXT_DATA_W1_FETCH_PND_MASK, - hw_ctxt[1])); - - return QDMA_SUCCESS; -} - -/*****************************************************************************/ -/** - * qdma_s80_hard_hw_context_clear() - clear hardware context - * - * @dev_hndl: device handle - * @c2h: is c2h queue - * @hw_qid: hardware qid of the queue - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -static int qdma_s80_hard_hw_context_clear(void *dev_hndl, uint8_t c2h, - uint16_t hw_qid) -{ - enum ind_ctxt_cmd_sel sel = c2h ? QDMA_CTXT_SEL_HW_C2H : - QDMA_CTXT_SEL_HW_H2C; - - if (!dev_hndl) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - return qdma_s80_hard_indirect_reg_clear(dev_hndl, sel, hw_qid); -} - -/*****************************************************************************/ -/** - * qdma_s80_hard_hw_context_invalidate() - invalidate hardware context - * - * @dev_hndl: device handle - * @c2h: is c2h queue - * @hw_qid: hardware qid of the queue - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -static int qdma_s80_hard_hw_context_invalidate(void *dev_hndl, uint8_t c2h, - uint16_t hw_qid) -{ - enum ind_ctxt_cmd_sel sel = c2h ? QDMA_CTXT_SEL_HW_C2H : - QDMA_CTXT_SEL_HW_H2C; - - if (!dev_hndl) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - return qdma_s80_hard_indirect_reg_invalidate(dev_hndl, sel, hw_qid); -} - -/*****************************************************************************/ -/** - * qdma_s80_hard_hw_ctx_conf() - configure HW context - * - * @dev_hndl: device handle - * @c2h: is c2h queue - * @hw_qid: hardware qid of the queue - * @ctxt: pointer to context data - * @access_type HW access type (qdma_hw_access_type enum) value - * QDMA_HW_ACCESS_WRITE unsupported - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -int qdma_s80_hard_hw_ctx_conf(void *dev_hndl, uint8_t c2h, uint16_t hw_qid, - struct qdma_descq_hw_ctxt *ctxt, - enum qdma_hw_access_type access_type) -{ - int ret_val = 0; - - switch (access_type) { - case QDMA_HW_ACCESS_READ: - ret_val = qdma_s80_hard_hw_context_read(dev_hndl, c2h, hw_qid, - ctxt); - break; - case QDMA_HW_ACCESS_CLEAR: - ret_val = qdma_s80_hard_hw_context_clear(dev_hndl, c2h, hw_qid); - break; - case QDMA_HW_ACCESS_INVALIDATE: - ret_val = qdma_s80_hard_hw_context_invalidate(dev_hndl, c2h, - hw_qid); - break; - case QDMA_HW_ACCESS_WRITE: - default: - qdma_log_error("%s: access_type=%d is invalid, err:%d\n", - __func__, access_type, - -QDMA_ERR_INV_PARAM); - ret_val = -QDMA_ERR_INV_PARAM; - break; - } - - - return ret_val; -} - -/*****************************************************************************/ -/** - * qdma_s80_hard_indirect_intr_context_write() - create indirect - * interrupt context and program it - * - * @dev_hndl: device handle - * @ring_index: indirect interrupt ring index - * @ctxt: pointer to the interrupt context data strucutre - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -static int qdma_s80_hard_indirect_intr_context_write(void *dev_hndl, - uint16_t ring_index, const struct qdma_indirect_intr_ctxt *ctxt) -{ - uint32_t intr_ctxt[QDMA_S80_HARD_IND_INTR_CONTEXT_NUM_WORDS] = {0}; - enum ind_ctxt_cmd_sel sel = QDMA_CTXT_SEL_INT_COAL; - uint16_t num_words_count = 0; - uint32_t baddr_l, baddr_h; - - if (!dev_hndl || !ctxt) { - qdma_log_error("%s: dev_hndl=%p intr_ctxt=%p, err:%d\n", - __func__, dev_hndl, ctxt, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - if (ctxt->page_size > QDMA_INDIRECT_INTR_RING_SIZE_32KB) { - qdma_log_error("%s: ctxt->page_size=%u is too big, err:%d\n", - __func__, ctxt->page_size, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - baddr_l = - (uint32_t)FIELD_GET(QDMA_S80_HARD_INTR_CTXT_BADDR_GET_L_MASK, - ctxt->baddr_4k); - baddr_h = - (uint32_t)FIELD_GET(QDMA_S80_HARD_INTR_CTXT_BADDR_GET_H_MASK, - ctxt->baddr_4k); - - intr_ctxt[num_words_count++] = - FIELD_SET(INTR_CTXT_DATA_W0_VALID_MASK, ctxt->valid) | - FIELD_SET(INTR_CTXT_DATA_W0_VEC_MASK, ctxt->vec) | - FIELD_SET(INTR_CTXT_DATA_W0_INT_ST_MASK, - ctxt->int_st) | - FIELD_SET(INTR_CTXT_DATA_W0_COLOR_MASK, ctxt->color) | - FIELD_SET(INTR_CTXT_DATA_W0_BADDR_4K_L_MASK, baddr_l); - - intr_ctxt[num_words_count++] = - FIELD_SET(INTR_CTXT_DATA_W1_BADDR_4K_H_MASK, baddr_h) | - FIELD_SET(INTR_CTXT_DATA_W1_PAGE_SIZE_MASK, - ctxt->page_size); - - intr_ctxt[num_words_count++] = - FIELD_SET(INTR_CTXT_DATA_W2_PIDX_MASK, ctxt->pidx); - - return qdma_s80_hard_indirect_reg_write(dev_hndl, sel, ring_index, - intr_ctxt, num_words_count); -} - -/*****************************************************************************/ -/** - * qdma_indirect_intr_context_read() - read indirect interrupt context - * - * @dev_hndl: device handle - * @ring_index: indirect interrupt ring index - * @ctxt: pointer to the output context data - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -static int qdma_s80_hard_indirect_intr_context_read(void *dev_hndl, - uint16_t ring_index, struct qdma_indirect_intr_ctxt *ctxt) -{ - int rv = 0; - uint32_t intr_ctxt[QDMA_S80_HARD_IND_INTR_CONTEXT_NUM_WORDS] = {0}; - enum ind_ctxt_cmd_sel sel = QDMA_CTXT_SEL_INT_COAL; - uint64_t baddr_l, baddr_h; - - if (!dev_hndl || !ctxt) { - qdma_log_error("%s: dev_hndl=%p intr_ctxt=%p, err:%d\n", - __func__, dev_hndl, ctxt, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - rv = qdma_s80_hard_indirect_reg_read(dev_hndl, sel, ring_index, - QDMA_S80_HARD_IND_INTR_CONTEXT_NUM_WORDS, intr_ctxt); - if (rv < 0) - return rv; - - ctxt->valid = FIELD_GET(INTR_CTXT_DATA_W0_VALID_MASK, intr_ctxt[0]); - ctxt->vec = FIELD_GET(INTR_CTXT_DATA_W0_VEC_MASK, - intr_ctxt[0]); - ctxt->int_st = FIELD_GET(INTR_CTXT_DATA_W0_INT_ST_MASK, - intr_ctxt[0]); - ctxt->color = - (uint8_t)(FIELD_GET(INTR_CTXT_DATA_W0_COLOR_MASK, - intr_ctxt[0])); - baddr_l = FIELD_GET(INTR_CTXT_DATA_W0_BADDR_4K_L_MASK, - intr_ctxt[0]); - - baddr_h = FIELD_GET(INTR_CTXT_DATA_W1_BADDR_4K_H_MASK, - intr_ctxt[1]); - ctxt->page_size = - (uint8_t)(FIELD_GET(INTR_CTXT_DATA_W1_PAGE_SIZE_MASK, - intr_ctxt[1])); - ctxt->pidx = FIELD_GET(INTR_CTXT_DATA_W2_PIDX_MASK, - intr_ctxt[2]); - - ctxt->baddr_4k = - FIELD_SET(QDMA_S80_HARD_INTR_CTXT_BADDR_GET_L_MASK, baddr_l) | - FIELD_SET(QDMA_S80_HARD_INTR_CTXT_BADDR_GET_H_MASK, baddr_h); - - return QDMA_SUCCESS; -} - -/*****************************************************************************/ -/** - * qdma_s80_hard_indirect_intr_context_clear() - clear indirect - * interrupt context - * - * @dev_hndl: device handle - * @ring_index: indirect interrupt ring index - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -static int qdma_s80_hard_indirect_intr_context_clear(void *dev_hndl, - uint16_t ring_index) -{ - enum ind_ctxt_cmd_sel sel = QDMA_CTXT_SEL_INT_COAL; - - if (!dev_hndl) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - return qdma_s80_hard_indirect_reg_clear(dev_hndl, sel, ring_index); -} - -/*****************************************************************************/ -/** - * qdma_s80_hard_indirect_intr_context_invalidate() - invalidate - * indirect interrupt context - * - * @dev_hndl: device handle - * @ring_index: indirect interrupt ring index - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -static int qdma_s80_hard_indirect_intr_context_invalidate(void *dev_hndl, - uint16_t ring_index) -{ - enum ind_ctxt_cmd_sel sel = QDMA_CTXT_SEL_INT_COAL; - - if (!dev_hndl) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - return qdma_s80_hard_indirect_reg_invalidate(dev_hndl, sel, ring_index); -} - -/*****************************************************************************/ -/** - * qdma_s80_hard_indirect_intr_ctx_conf() - configure indirect interrupt context - * - * @dev_hndl: device handle - * @ring_index: indirect interrupt ring index - * @ctxt: pointer to context data - * @access_type HW access type (qdma_hw_access_type enum) value - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -int qdma_s80_hard_indirect_intr_ctx_conf(void *dev_hndl, uint16_t ring_index, - struct qdma_indirect_intr_ctxt *ctxt, - enum qdma_hw_access_type access_type) -{ - int ret_val = 0; - - switch (access_type) { - case QDMA_HW_ACCESS_READ: - ret_val = qdma_s80_hard_indirect_intr_context_read(dev_hndl, - ring_index, - ctxt); - break; - case QDMA_HW_ACCESS_WRITE: - ret_val = qdma_s80_hard_indirect_intr_context_write(dev_hndl, - ring_index, - ctxt); - break; - case QDMA_HW_ACCESS_CLEAR: - ret_val = qdma_s80_hard_indirect_intr_context_clear(dev_hndl, - ring_index); - break; - case QDMA_HW_ACCESS_INVALIDATE: - ret_val = qdma_s80_hard_indirect_intr_context_invalidate( - dev_hndl, ring_index); - break; - default: - qdma_log_error("%s: access_type=%d is invalid, err:%d\n", - __func__, access_type, - -QDMA_ERR_INV_PARAM); - ret_val = -QDMA_ERR_INV_PARAM; - break; - } - - return ret_val; -} - -/*****************************************************************************/ -/** - * qdma_s80_hard_set_default_global_csr() - function to set the global - * CSR register to default values. The value can be modified later by using - * the set/get csr functions - * - * @dev_hndl: device handle - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -int qdma_s80_hard_set_default_global_csr(void *dev_hndl) -{ - /* Default values */ - uint32_t reg_val = 0; - uint32_t rng_sz[QDMA_NUM_RING_SIZES] = {2049, 65, 129, 193, 257, - 385, 513, 769, 1025, 1537, 3073, 4097, 6145, - 8193, 12289, 16385}; - uint32_t tmr_cnt[QDMA_NUM_C2H_TIMERS] = {1, 2, 4, 5, 8, 10, 15, 20, 25, - 30, 50, 75, 100, 125, 150, 200}; - uint32_t cnt_th[QDMA_NUM_C2H_COUNTERS] = {2, 4, 8, 16, 24, - 32, 48, 64, 80, 96, 112, 128, 144, - 160, 176, 192}; - uint32_t buf_sz[QDMA_NUM_C2H_BUFFER_SIZES] = {4096, 256, 512, 1024, - 2048, 3968, 4096, 4096, 4096, 4096, 4096, 4096, - 4096, 8192, 9018, 16384}; - struct qdma_dev_attributes dev_cap; - - if (!dev_hndl) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - qdma_s80_hard_get_device_attributes(dev_hndl, &dev_cap); - - /* Configuring CSR registers */ - /* Global ring sizes */ - qdma_write_csr_values(dev_hndl, QDMA_S80_HARD_GLBL_RNG_SZ_1_ADDR, 0, - QDMA_NUM_RING_SIZES, rng_sz); - - if (dev_cap.st_en || dev_cap.mm_cmpt_en) { - /* Counter thresholds */ - qdma_write_csr_values(dev_hndl, - QDMA_S80_HARD_C2H_CNT_TH_1_ADDR, 0, - QDMA_NUM_C2H_COUNTERS, cnt_th); - - /* Timer Counters */ - qdma_write_csr_values(dev_hndl, - QDMA_S80_HARD_C2H_TIMER_CNT_1_ADDR, 0, - QDMA_NUM_C2H_TIMERS, tmr_cnt); - - - /* Writeback Interval */ - reg_val = - FIELD_SET(GLBL_DSC_CFG_MAXFETCH_MASK, - DEFAULT_MAX_DSC_FETCH) | - FIELD_SET(GLBL_DSC_CFG_WB_ACC_INT_MASK, - DEFAULT_WRB_INT); - qdma_reg_write(dev_hndl, - QDMA_S80_HARD_GLBL_DSC_CFG_ADDR, reg_val); - } - - if (dev_cap.st_en) { - /* Buffer Sizes */ - qdma_write_csr_values(dev_hndl, - QDMA_S80_HARD_C2H_BUF_SZ_0_ADDR, 0, - QDMA_NUM_C2H_BUFFER_SIZES, buf_sz); - - /* Prefetch Configuration */ - reg_val = - FIELD_SET(C2H_PFCH_CFG_FL_TH_MASK, - DEFAULT_PFCH_STOP_THRESH) | - FIELD_SET(C2H_PFCH_CFG_NUM_MASK, - DEFAULT_PFCH_NUM_ENTRIES_PER_Q) | - FIELD_SET(C2H_PFCH_CFG_QCNT_MASK, - DEFAULT_PFCH_MAX_Q_CNT) | - FIELD_SET(C2H_PFCH_CFG_EVT_QCNT_TH_MASK, - DEFAULT_C2H_INTR_TIMER_TICK); - qdma_reg_write(dev_hndl, - QDMA_S80_HARD_C2H_PFCH_CFG_ADDR, reg_val); - - /* C2H interrupt timer tick */ - qdma_reg_write(dev_hndl, QDMA_S80_HARD_C2H_INT_TIMER_TICK_ADDR, - DEFAULT_C2H_INTR_TIMER_TICK); - - /* C2h Completion Coalesce Configuration */ - reg_val = - FIELD_SET(C2H_WRB_COAL_CFG_TICK_CNT_MASK, - DEFAULT_CMPT_COAL_TIMER_CNT) | - FIELD_SET(C2H_WRB_COAL_CFG_TICK_VAL_MASK, - DEFAULT_CMPT_COAL_TIMER_TICK) | - FIELD_SET(C2H_WRB_COAL_CFG_MAX_BUF_SZ_MASK, - DEFAULT_CMPT_COAL_MAX_BUF_SZ); - qdma_reg_write(dev_hndl, - QDMA_S80_HARD_C2H_WRB_COAL_CFG_ADDR, reg_val); - -#if 0 - /* H2C throttle Configuration*/ - reg_val = - FIELD_SET(QDMA_H2C_DATA_THRESH_MASK, - DEFAULT_H2C_THROT_DATA_THRESH) | - FIELD_SET(QDMA_H2C_REQ_THROT_EN_DATA_MASK, - DEFAULT_THROT_EN_DATA); - qdma_reg_write(dev_hndl, QDMA_OFFSET_H2C_REQ_THROT, reg_val); -#endif - } - - return QDMA_SUCCESS; -} - -/*****************************************************************************/ -/** - * qdma_s80_hard_queue_pidx_update() - function to update the desc PIDX - * - * @dev_hndl: device handle - * @is_vf: Whether PF or VF - * @qid: Queue id relative to the PF/VF calling this API - * @is_c2h: Queue direction. Set 1 for C2H and 0 for H2C - * @reg_info: data needed for the PIDX register update - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -int qdma_s80_hard_queue_pidx_update(void *dev_hndl, uint8_t is_vf, uint16_t qid, - uint8_t is_c2h, const struct qdma_q_pidx_reg_info *reg_info) -{ - uint32_t reg_addr = 0; - uint32_t reg_val = 0; - - if (!dev_hndl) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - if (!reg_info) { - qdma_log_error("%s: reg_info is NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - if (!is_vf) { - reg_addr = (is_c2h) ? - QDMA_S80_HARD_OFFSET_DMAP_SEL_C2H_DSC_PIDX : - QDMA_S80_HARD_OFFSET_DMAP_SEL_H2C_DSC_PIDX; - } else { - reg_addr = (is_c2h) ? - QDMA_S80_HARD_OFFSET_VF_DMAP_SEL_C2H_DSC_PIDX : - QDMA_S80_HARD_OFFSET_VF_DMAP_SEL_H2C_DSC_PIDX; - } - - reg_addr += (qid * QDMA_PIDX_STEP); - - reg_val = FIELD_SET(QDMA_S80_HARD_DMA_SEL_DESC_PIDX_MASK, - reg_info->pidx) | - FIELD_SET(QDMA_S80_HARD_DMA_SEL_IRQ_EN_MASK, - reg_info->irq_en); - - qdma_reg_write(dev_hndl, reg_addr, reg_val); - - return QDMA_SUCCESS; -} - -/*****************************************************************************/ -/** - * qdma_s80_hard_queue_cmpt_cidx_update() - function to update the CMPT - * CIDX update - * - * @dev_hndl: device handle - * @is_vf: Whether PF or VF - * @qid: Queue id relative to the PF/VF calling this API - * @reg_info: data needed for the CIDX register update - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -int qdma_s80_hard_queue_cmpt_cidx_update(void *dev_hndl, uint8_t is_vf, - uint16_t qid, const struct qdma_q_cmpt_cidx_reg_info *reg_info) -{ - uint32_t reg_addr = (is_vf) ? - QDMA_S80_HARD_OFFSET_VF_DMAP_SEL_CMPT_CIDX : - QDMA_S80_HARD_OFFSET_DMAP_SEL_CMPT_CIDX; - uint32_t reg_val = 0; - - if (!dev_hndl) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - if (!reg_info) { - qdma_log_error("%s: reg_info is NULL, err:%d\n", - __func__, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - reg_addr += (qid * QDMA_CMPT_CIDX_STEP); - - reg_val = - FIELD_SET(QDMA_S80_HARD_DMAP_SEL_CMPT_WRB_CIDX_MASK, - reg_info->wrb_cidx) | - FIELD_SET(QDMA_S80_HARD_DMAP_SEL_CMPT_CNT_THRESH_MASK, - reg_info->counter_idx) | - FIELD_SET(QDMA_S80_HARD_DMAP_SEL_CMPT_TMR_CNT_MASK, - reg_info->timer_idx) | - FIELD_SET(QDMA_S80_HARD_DMAP_SEL_CMPT_TRG_MODE_MASK, - reg_info->trig_mode) | - FIELD_SET(QDMA_S80_HARD_DMAP_SEL_CMPT_STS_DESC_EN_MASK, - reg_info->wrb_en) | - FIELD_SET(QDMA_S80_HARD_DMAP_SEL_CMPT_IRQ_EN_MASK, - reg_info->irq_en); - - qdma_reg_write(dev_hndl, reg_addr, reg_val); - - return QDMA_SUCCESS; -} - -/*****************************************************************************/ -/** - * qdma_s80_hard_queue_intr_cidx_update() - function to update the - * CMPT CIDX update - * - * @dev_hndl: device handle - * @is_vf: Whether PF or VF - * @qid: Queue id relative to the PF/VF calling this API - * @reg_info: data needed for the CIDX register update - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -int qdma_s80_hard_queue_intr_cidx_update(void *dev_hndl, uint8_t is_vf, - uint16_t qid, const struct qdma_intr_cidx_reg_info *reg_info) -{ - uint32_t reg_addr = (is_vf) ? - QDMA_S80_HARD_OFFSET_VF_DMAP_SEL_INT_CIDX : - QDMA_S80_HARD_OFFSET_DMAP_SEL_INT_CIDX; - uint32_t reg_val = 0; - - if (!dev_hndl) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - if (!reg_info) { - qdma_log_error("%s: reg_info is NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - reg_addr += qid * QDMA_INT_CIDX_STEP; - - reg_val = - FIELD_SET(QDMA_S80_HARD_DMA_SEL_INT_SW_CIDX_MASK, - reg_info->sw_cidx) | - FIELD_SET(QDMA_S80_HARD_DMA_SEL_INT_RING_IDX_MASK, - reg_info->rng_idx); - - qdma_reg_write(dev_hndl, reg_addr, reg_val); - - return QDMA_SUCCESS; -} - -/*****************************************************************************/ -/** - * qdma_cmp_get_user_bar() - Function to get the - * AXI Master Lite(user bar) number - * @dev_hndl: device handle - * @is_vf: Whether PF or VF - * @func_id: function id of the PF - * @user_bar: pointer to hold the AXI Master Lite(user bar) number - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -int qdma_cmp_get_user_bar(void *dev_hndl, uint8_t is_vf, - uint8_t func_id, uint8_t *user_bar) -{ - uint8_t bar_found = 0; - uint8_t bar_idx = 0; - uint32_t user_bar_id = 0; - uint32_t reg_addr = 0; - - if (!dev_hndl) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - if (!user_bar) { - qdma_log_error("%s: user_bar is NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - reg_addr = (is_vf) ? QDMA_S80_HARD_GLBL2_PF_VF_BARLITE_EXT_ADDR : - QDMA_S80_HARD_GLBL2_PF_BARLITE_EXT_ADDR; - - if (!is_vf) { - user_bar_id = qdma_reg_read(dev_hndl, reg_addr); - user_bar_id = (user_bar_id >> (6 * func_id)) & 0x3F; - } else { - *user_bar = QDMA_S80_HARD_VF_USER_BAR_ID; - return QDMA_SUCCESS; - } - - for (bar_idx = 0; bar_idx < QDMA_BAR_NUM; bar_idx++) { - if (user_bar_id & (1 << bar_idx)) { - *user_bar = bar_idx; - bar_found = 1; - break; - } - } - if (bar_found == 0) { - *user_bar = 0; - qdma_log_error("%s: Bar not found, err:%d\n", - __func__, - -QDMA_ERR_HWACC_BAR_NOT_FOUND); - return -QDMA_ERR_HWACC_BAR_NOT_FOUND; - } - - return QDMA_SUCCESS; -} - -/*****************************************************************************/ -/** - * qdma_s80_hard_hw_ram_sbe_err_process() -Function to dump SBE err debug info - * - * @dev_hndl: device handle - * @buf: Bufffer for the debug info to be dumped in - * @buflen: Length of the buffer - * - * Return: void - *****************************************************************************/ -static void qdma_s80_hard_hw_ram_sbe_err_process(void *dev_hndl) -{ - qdma_s80_hard_dump_reg_info(dev_hndl, QDMA_S80_HARD_RAM_SBE_STS_A_ADDR, - 1, NULL, 0); -} - -/*****************************************************************************/ -/** - * qdma_s80_hard_hw_ram_dbe_err_process() -Function to dump DBE err debug info - * - * @dev_hndl: device handle - * @buf: Bufffer for the debug info to be dumped in - * @buflen: Length of the buffer - * - * Return: void - *****************************************************************************/ -static void qdma_s80_hard_hw_ram_dbe_err_process(void *dev_hndl) -{ - qdma_s80_hard_dump_reg_info(dev_hndl, QDMA_S80_HARD_RAM_DBE_STS_A_ADDR, - 1, NULL, 0); -} - -/*****************************************************************************/ -/** - * qdma_s80_hard_hw_desc_err_process() -Function to dump Descriptor Error info - * - * @dev_hndl: device handle - * @buf: Bufffer for the debug info to be dumped in - * @buflen: Length of the buffer - * - * Return: void - *****************************************************************************/ -static void qdma_s80_hard_hw_desc_err_process(void *dev_hndl) -{ - int i = 0; - uint32_t desc_err_reg_list[] = { - QDMA_S80_HARD_GLBL_DSC_ERR_STS_ADDR, - QDMA_S80_HARD_GLBL_DSC_ERR_LOG0_ADDR, - QDMA_S80_HARD_GLBL_DSC_ERR_LOG1_ADDR, - QDMA_S80_HARD_GLBL_DSC_DBG_DAT0_ADDR, - QDMA_S80_HARD_GLBL_DSC_DBG_DAT1_ADDR - }; - int desc_err_num_regs = sizeof(desc_err_reg_list)/sizeof(uint32_t); - - for (i = 0; i < desc_err_num_regs; i++) { - qdma_s80_hard_dump_reg_info(dev_hndl, - desc_err_reg_list[i], - 1, NULL, 0); - } -} - -/*****************************************************************************/ -/** - * qdma_s80_hard_hw_trq_err_process() -Function to dump Target Access Err info - * - * @dev_hndl: device handle - * @buf: Bufffer for the debug info to be dumped in - * @buflen: Length of the buffer - * - * Return: void - *****************************************************************************/ -static void qdma_s80_hard_hw_trq_err_process(void *dev_hndl) -{ - int i = 0; - uint32_t trq_err_reg_list[] = { - QDMA_S80_HARD_GLBL_TRQ_ERR_STS_ADDR, - QDMA_S80_HARD_GLBL_TRQ_ERR_LOG_ADDR - }; - int trq_err_reg_num_regs = sizeof(trq_err_reg_list)/sizeof(uint32_t); - - for (i = 0; i < trq_err_reg_num_regs; i++) { - qdma_s80_hard_dump_reg_info(dev_hndl, trq_err_reg_list[i], - 1, NULL, 0); - } - - -} - -/*****************************************************************************/ -/** - * qdma_s80_hard_hw_st_h2c_err_process() - Function to dump MM H2C Error info - * - * @dev_hndl: device handle - * @buf: Bufffer for the debug info to be dumped in - * @buflen: Length of the buffer - * - * Return: void - *****************************************************************************/ -static void qdma_s80_hard_hw_st_h2c_err_process(void *dev_hndl) -{ - int i = 0; - uint32_t st_h2c_err_reg_list[] = { - QDMA_S80_HARD_H2C_ERR_STAT_ADDR, - QDMA_S80_HARD_H2C_FIRST_ERR_QID_ADDR, - QDMA_S80_HARD_H2C_DBG_REG0_ADDR, - QDMA_S80_HARD_H2C_DBG_REG1_ADDR, - QDMA_S80_HARD_H2C_DBG_REG2_ADDR, - QDMA_S80_HARD_H2C_DBG_REG3_ADDR, - QDMA_S80_HARD_H2C_DBG_REG4_ADDR - }; - int st_h2c_err_num_regs = sizeof(st_h2c_err_reg_list)/sizeof(uint32_t); - - for (i = 0; i < st_h2c_err_num_regs; i++) { - qdma_s80_hard_dump_reg_info(dev_hndl, - st_h2c_err_reg_list[i], - 1, NULL, 0); - } -} - - -/*****************************************************************************/ -/** - * qdma_s80_hard_hw_st_c2h_err_process() - Function to dump MM H2C Error info - * - * @dev_hndl: device handle - * @buf: Bufffer for the debug info to be dumped in - * @buflen: Length of the buffer - * - * Return: void - *****************************************************************************/ -static void qdma_s80_hard_hw_st_c2h_err_process(void *dev_hndl) -{ - int i = 0; - uint32_t st_c2h_err_reg_list[] = { - QDMA_S80_HARD_C2H_ERR_STAT_ADDR, - QDMA_S80_HARD_C2H_FATAL_ERR_STAT_ADDR, - QDMA_S80_HARD_C2H_FIRST_ERR_QID_ADDR, - QDMA_S80_HARD_C2H_STAT_S_AXIS_C2H_ACCEPTED_ADDR, - QDMA_S80_HARD_C2H_STAT_S_AXIS_WRB_ACCEPTED_ADDR, - QDMA_S80_HARD_C2H_STAT_DESC_RSP_PKT_ACCEPTED_ADDR, - QDMA_S80_HARD_C2H_STAT_AXIS_PKG_CMP_ADDR, - QDMA_S80_HARD_C2H_STAT_DBG_DMA_ENG_0_ADDR, - QDMA_S80_HARD_C2H_STAT_DBG_DMA_ENG_1_ADDR, - QDMA_S80_HARD_C2H_STAT_DBG_DMA_ENG_2_ADDR, - QDMA_S80_HARD_C2H_STAT_DBG_DMA_ENG_3_ADDR, - QDMA_S80_HARD_C2H_STAT_DESC_RSP_DROP_ACCEPTED_ADDR, - QDMA_S80_HARD_C2H_STAT_DESC_RSP_ERR_ACCEPTED_ADDR - }; - int st_c2h_err_num_regs = sizeof(st_c2h_err_reg_list)/sizeof(uint32_t); - - for (i = 0; i < st_c2h_err_num_regs; i++) { - qdma_s80_hard_dump_reg_info(dev_hndl, - st_c2h_err_reg_list[i], - 1, NULL, 0); - } -} - - - -/*****************************************************************************/ -/** - * qdma_s80_hard_hw_get_error_name() - Function to get the error in str format - * - * @err_idx: error index - * - * Return: string - success and NULL on failure - *****************************************************************************/ -const char *qdma_s80_hard_hw_get_error_name(uint32_t err_idx) -{ - if (err_idx >= QDMA_S80_HARD_ERRS_ALL) { - qdma_log_error("%s: err_idx=%d is invalid, returning NULL\n", - __func__, - (enum qdma_s80_hard_error_idx)err_idx); - return NULL; - } - - return qdma_s80_hard_err_info[ - (enum qdma_s80_hard_error_idx)err_idx].err_name; -} - -/*****************************************************************************/ -/** - * qdma_s80_hard_hw_error_process() - Function to find the error that got - * triggered and call the handler qdma_hw_error_handler of that - * particular error. - * - * @dev_hndl: device handle - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -int qdma_s80_hard_hw_error_process(void *dev_hndl) -{ - uint32_t glbl_err_stat = 0, err_stat = 0; - uint32_t i = 0, j = 0; - int32_t idx = 0; - struct qdma_dev_attributes dev_cap; - uint32_t hw_err_position[QDMA_S80_HARD_TOTAL_LEAF_ERROR_AGGREGATORS] = { - QDMA_S80_HARD_DSC_ERR_POISON, - QDMA_S80_HARD_TRQ_ERR_UNMAPPED, - QDMA_S80_HARD_ST_C2H_ERR_MTY_MISMATCH, - QDMA_S80_HARD_ST_FATAL_ERR_MTY_MISMATCH, - QDMA_S80_HARD_ST_H2C_ERR_ZERO_LEN_DESC_ERR, - QDMA_S80_HARD_SBE_ERR_MI_H2C0_DAT, - QDMA_S80_HARD_DBE_ERR_MI_H2C0_DAT - }; - - if (!dev_hndl) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - - qdma_s80_hard_get_device_attributes(dev_hndl, &dev_cap); - - glbl_err_stat = qdma_reg_read(dev_hndl, - QDMA_S80_HARD_GLBL_ERR_STAT_ADDR); - if (!glbl_err_stat) - return QDMA_HW_ERR_NOT_DETECTED; - - qdma_log_info("%s: Global Err Reg(0x%x) = 0x%x\n", - __func__, QDMA_S80_HARD_GLBL_ERR_STAT_ADDR, - glbl_err_stat); - - for (i = 0; i < QDMA_S80_HARD_TOTAL_LEAF_ERROR_AGGREGATORS; i++) { - j = hw_err_position[i]; - - if ((!dev_cap.st_en) && - (j == QDMA_S80_HARD_ST_C2H_ERR_MTY_MISMATCH || - j == QDMA_S80_HARD_ST_FATAL_ERR_MTY_MISMATCH || - j == QDMA_S80_HARD_ST_H2C_ERR_ZERO_LEN_DESC_ERR)) - continue; - - err_stat = qdma_reg_read(dev_hndl, - qdma_s80_hard_err_info[j].stat_reg_addr); - if (err_stat) { - qdma_log_info("addr = 0x%08x val = 0x%08x", - qdma_s80_hard_err_info[j].stat_reg_addr, - err_stat); - - qdma_s80_hard_err_info[j].qdma_s80_hard_hw_err_process( - dev_hndl); - for (idx = j; - idx < all_qdma_s80_hard_hw_errs[i]; - idx++) { - /* call the platform specific handler */ - if (err_stat & - qdma_s80_hard_err_info[idx].leaf_err_mask) - qdma_log_error("%s detected %s\n", - __func__, - qdma_s80_hard_hw_get_error_name( - idx)); - } - qdma_reg_write(dev_hndl, - qdma_s80_hard_err_info[j].stat_reg_addr, - err_stat); - } - - } - - /* Write 1 to the global status register to clear the bits */ - qdma_reg_write(dev_hndl, - QDMA_S80_HARD_GLBL_ERR_STAT_ADDR, glbl_err_stat); - - return QDMA_SUCCESS; -} - -/*****************************************************************************/ -/** - * qdma_hw_error_enable() - Function to enable all or a specific error - * - * @dev_hndl: device handle - * @err_idx: error index - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -int qdma_s80_hard_hw_error_enable(void *dev_hndl, uint32_t err_idx) -{ - uint32_t idx = 0, i = 0; - uint32_t reg_val = 0; - struct qdma_dev_attributes dev_cap; - - if (!dev_hndl) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - if (err_idx > QDMA_S80_HARD_ERRS_ALL) { - qdma_log_error("%s: err_idx=%d is invalid, err:%d\n", - __func__, (enum qdma_s80_hard_error_idx)err_idx, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - qdma_s80_hard_get_device_attributes(dev_hndl, &dev_cap); - - if (err_idx == QDMA_S80_HARD_ERRS_ALL) { - for (i = 0; - i < QDMA_S80_HARD_TOTAL_LEAF_ERROR_AGGREGATORS; - i++) { - - idx = all_qdma_s80_hard_hw_errs[i]; - - /* Don't access streaming registers in - * MM only bitstreams - */ - if (!dev_cap.st_en) { - if (idx == QDMA_S80_HARD_ST_C2H_ERR_ALL || - idx == QDMA_S80_HARD_ST_FATAL_ERR_ALL || - idx == QDMA_S80_HARD_ST_H2C_ERR_ALL) - continue; - } - - reg_val = qdma_s80_hard_err_info[idx].leaf_err_mask; - qdma_reg_write(dev_hndl, - qdma_s80_hard_err_info[idx].mask_reg_addr, - reg_val); - - reg_val = qdma_reg_read(dev_hndl, - QDMA_S80_HARD_GLBL_ERR_MASK_ADDR); - reg_val |= FIELD_SET( - qdma_s80_hard_err_info[idx].global_err_mask, 1); - qdma_reg_write(dev_hndl, - QDMA_S80_HARD_GLBL_ERR_MASK_ADDR, - reg_val); - } - - } else { - /* Don't access streaming registers in MM only bitstreams - * QDMA_C2H_ERR_MTY_MISMATCH to QDMA_H2C_ERR_ALL are all - * ST errors - */ - if (!dev_cap.st_en) { - if (err_idx >= QDMA_S80_HARD_ST_C2H_ERR_MTY_MISMATCH && - err_idx <= QDMA_S80_HARD_ST_H2C_ERR_ALL) - return QDMA_SUCCESS; - } - - reg_val = qdma_reg_read(dev_hndl, - qdma_s80_hard_err_info[err_idx].mask_reg_addr); - reg_val |= - FIELD_SET(qdma_s80_hard_err_info[err_idx].leaf_err_mask, - 1); - qdma_reg_write(dev_hndl, - qdma_s80_hard_err_info[err_idx].mask_reg_addr, - reg_val); - - reg_val = qdma_reg_read(dev_hndl, - QDMA_S80_HARD_GLBL_ERR_MASK_ADDR); - reg_val |= - FIELD_SET( - qdma_s80_hard_err_info[err_idx].global_err_mask, - 1); - qdma_reg_write(dev_hndl, - QDMA_S80_HARD_GLBL_ERR_MASK_ADDR, reg_val); - } - - return QDMA_SUCCESS; -} - -/*****************************************************************************/ -/** - * qdma_s80_hard_get_device_attributes() - Function to get the qdma - * device attributes - * - * @dev_hndl: device handle - * @dev_info: pointer to hold the device info - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -int qdma_s80_hard_get_device_attributes(void *dev_hndl, - struct qdma_dev_attributes *dev_info) -{ - uint8_t count = 0; - uint32_t reg_val = 0; - - if (!dev_hndl) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - if (!dev_info) { - qdma_log_error("%s: dev_info is NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - /* number of PFs */ - reg_val = qdma_reg_read(dev_hndl, - QDMA_S80_HARD_GLBL2_PF_BARLITE_INT_ADDR); - if (FIELD_GET(GLBL2_PF_BARLITE_INT_PF0_BAR_MAP_MASK, reg_val)) - count++; - if (FIELD_GET(GLBL2_PF_BARLITE_INT_PF1_BAR_MAP_MASK, reg_val)) - count++; - if (FIELD_GET(GLBL2_PF_BARLITE_INT_PF2_BAR_MAP_MASK, reg_val)) - count++; - if (FIELD_GET(GLBL2_PF_BARLITE_INT_PF3_BAR_MAP_MASK, reg_val)) - count++; - dev_info->num_pfs = count; - - /* Number of Qs */ - reg_val = qdma_reg_read(dev_hndl, QDMA_S80_HARD_GLBL2_CHANNEL_CAP_ADDR); - dev_info->num_qs = (FIELD_GET(GLBL2_CHANNEL_CAP_MULTIQ_MAX_MASK, - reg_val)); - - /* FLR present */ - reg_val = qdma_reg_read(dev_hndl, QDMA_S80_HARD_GLBL2_MISC_CAP_ADDR); - dev_info->mailbox_en = FIELD_GET(QDMA_GLBL2_MAILBOX_EN_MASK, reg_val); - dev_info->flr_present = FIELD_GET(QDMA_GLBL2_FLR_PRESENT_MASK, reg_val); - dev_info->mm_cmpt_en = 0; - - /* ST/MM enabled? */ - reg_val = qdma_reg_read(dev_hndl, - QDMA_S80_HARD_GLBL2_CHANNEL_MDMA_ADDR); - dev_info->mm_en = (FIELD_GET(GLBL2_CHANNEL_MDMA_C2H_ENG_MASK, reg_val) - && FIELD_GET(GLBL2_CHANNEL_MDMA_H2C_ENG_MASK, reg_val)) ? 1 : 0; - dev_info->st_en = (FIELD_GET(GLBL2_CHANNEL_MDMA_C2H_ST_MASK, reg_val) - && FIELD_GET(GLBL2_CHANNEL_MDMA_H2C_ST_MASK, - reg_val)) ? 1 : 0; - - /* num of mm channels for Versal Hard is 2 */ - dev_info->mm_channel_max = 2; - - dev_info->debug_mode = 0; - dev_info->desc_eng_mode = 0; - dev_info->qid2vec_ctx = 1; - dev_info->cmpt_ovf_chk_dis = 0; - dev_info->mailbox_intr = 0; - dev_info->sw_desc_64b = 0; - dev_info->cmpt_desc_64b = 0; - dev_info->dynamic_bar = 0; - dev_info->legacy_intr = 0; - dev_info->cmpt_trig_count_timer = 0; - - return QDMA_SUCCESS; -} - - -/*****************************************************************************/ -/** - * qdma_s80_hard_credit_context_read() - read credit context - * - * @dev_hndl: device handle - * @c2h : is c2h queue - * @hw_qid : hardware qid of the queue - * @ctxt : pointer to the context data - * - * Return : 0 - success and < 0 - failure - *****************************************************************************/ -static int qdma_s80_hard_credit_context_read(void *dev_hndl, uint8_t c2h, - uint16_t hw_qid, - struct qdma_descq_credit_ctxt *ctxt) -{ - int rv = QDMA_SUCCESS; - uint32_t cr_ctxt[QDMA_S80_HARD_CR_CONTEXT_NUM_WORDS] = {0}; - enum ind_ctxt_cmd_sel sel = c2h ? QDMA_CTXT_SEL_CR_C2H : - QDMA_CTXT_SEL_CR_H2C; - - if (!dev_hndl || !ctxt) { - qdma_log_error("%s: dev_hndl=%p credit_ctxt=%p, err:%d\n", - __func__, dev_hndl, ctxt, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - rv = qdma_s80_hard_indirect_reg_read(dev_hndl, sel, hw_qid, - QDMA_S80_HARD_CR_CONTEXT_NUM_WORDS, cr_ctxt); - if (rv < 0) - return rv; - - ctxt->credit = FIELD_GET(CRED_CTXT_DATA_W0_CREDT_MASK, - cr_ctxt[0]); - - qdma_log_debug("%s: credit=%u\n", __func__, ctxt->credit); - - return QDMA_SUCCESS; -} - -/*****************************************************************************/ -/** - * qdma_s80_hard_credit_context_clear() - clear credit context - * - * @dev_hndl: device handle - * @c2h : is c2h queue - * @hw_qid : hardware qid of the queue - * - * Return : 0 - success and < 0 - failure - *****************************************************************************/ -static int qdma_s80_hard_credit_context_clear(void *dev_hndl, uint8_t c2h, - uint16_t hw_qid) -{ - enum ind_ctxt_cmd_sel sel = c2h ? QDMA_CTXT_SEL_CR_C2H : - QDMA_CTXT_SEL_CR_H2C; - - if (!dev_hndl) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", __func__, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - return qdma_s80_hard_indirect_reg_clear(dev_hndl, sel, hw_qid); -} - -/*****************************************************************************/ -/** - * qdma_s80_hard_credit_context_invalidate() - invalidate credit context - * - * @dev_hndl: device handle - * @c2h : is c2h queue - * @hw_qid : hardware qid of the queue - * - * Return : 0 - success and < 0 - failure - *****************************************************************************/ -static int qdma_s80_hard_credit_context_invalidate(void *dev_hndl, uint8_t c2h, - uint16_t hw_qid) -{ - enum ind_ctxt_cmd_sel sel = c2h ? QDMA_CTXT_SEL_CR_C2H : - QDMA_CTXT_SEL_CR_H2C; - - if (!dev_hndl) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", __func__, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - return qdma_s80_hard_indirect_reg_invalidate(dev_hndl, sel, hw_qid); -} - -/*****************************************************************************/ -/** - * qdma_s80_hard_credit_ctx_conf() - configure credit context - * - * @dev_hndl : device handle - * @c2h : is c2h queue - * @hw_qid : hardware qid of the queue - * @ctxt : pointer to the context data - * @access_type : HW access type (qdma_hw_access_type enum) value - * QDMA_HW_ACCESS_WRITE Not supported - * - * Return : 0 - success and < 0 - failure - *****************************************************************************/ -int qdma_s80_hard_credit_ctx_conf(void *dev_hndl, uint8_t c2h, uint16_t hw_qid, - struct qdma_descq_credit_ctxt *ctxt, - enum qdma_hw_access_type access_type) -{ - int rv = QDMA_SUCCESS; - - switch (access_type) { - case QDMA_HW_ACCESS_READ: - rv = qdma_s80_hard_credit_context_read(dev_hndl, c2h, - hw_qid, ctxt); - break; - case QDMA_HW_ACCESS_CLEAR: - rv = qdma_s80_hard_credit_context_clear(dev_hndl, c2h, hw_qid); - break; - case QDMA_HW_ACCESS_INVALIDATE: - rv = qdma_s80_hard_credit_context_invalidate(dev_hndl, c2h, - hw_qid); - break; - case QDMA_HW_ACCESS_WRITE: - default: - qdma_log_error("%s: Invalid access type=%d, err:%d\n", - __func__, access_type, - -QDMA_ERR_INV_PARAM); - rv = -QDMA_ERR_INV_PARAM; - break; - } - - return rv; -} - - -/*****************************************************************************/ -/** - * qdma_s80_hard_dump_config_regs() - Function to get qdma config register - * dump in a buffer - * - * @dev_hndl: device handle - * @is_vf: Whether PF or VF - * @buf : pointer to buffer to be filled - * @buflen : Length of the buffer - * - * Return: Length up-till the buffer is filled -success and < 0 - failure - *****************************************************************************/ -int qdma_s80_hard_dump_config_regs(void *dev_hndl, uint8_t is_vf, - char *buf, uint32_t buflen) -{ - uint32_t i = 0, j = 0; - struct xreg_info *reg_info; - uint32_t num_regs = qdma_s80_hard_config_num_regs_get(); - uint32_t len = 0, val = 0; - int rv = QDMA_SUCCESS; - char name[DEBGFS_GEN_NAME_SZ] = ""; - struct qdma_dev_attributes dev_cap; - - if (!dev_hndl) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - if (buflen < qdma_s80_hard_reg_dump_buf_len()) { - qdma_log_error("%s: Buffer too small, err:%d\n", __func__, - -QDMA_ERR_NO_MEM); - return -QDMA_ERR_NO_MEM; - } - - if (is_vf) { - qdma_log_error("%s: Wrong API used for VF, err:%d\n", - __func__, - -QDMA_ERR_HWACC_FEATURE_NOT_SUPPORTED); - return -QDMA_ERR_HWACC_FEATURE_NOT_SUPPORTED; - } - - qdma_s80_hard_get_device_attributes(dev_hndl, &dev_cap); - - reg_info = qdma_s80_hard_config_regs_get(); - - for (i = 0; i < num_regs; i++) { - if ((GET_CAPABILITY_MASK(dev_cap.mm_en, dev_cap.st_en, - dev_cap.mm_cmpt_en, dev_cap.mailbox_en) - & reg_info[i].mode) == 0) - continue; - - for (j = 0; j < reg_info[i].repeat; j++) { - rv = QDMA_SNPRINTF_S(name, DEBGFS_GEN_NAME_SZ, - DEBGFS_GEN_NAME_SZ, - "%s_%d", reg_info[i].name, j); - if ((rv < 0) || (rv > DEBGFS_GEN_NAME_SZ)) { - qdma_log_error( - "%d:%s QDMA_SNPRINTF_S() failed, err:%d\n", - __LINE__, __func__, - rv); - return -QDMA_ERR_NO_MEM; - } - - val = qdma_reg_read(dev_hndl, - (reg_info[i].addr + (j * 4))); - rv = dump_reg(buf + len, buflen - len, - (reg_info[i].addr + (j * 4)), - name, val); - if (rv < 0) { - qdma_log_error( - "%s Buff too small, err:%d\n", - __func__, - -QDMA_ERR_NO_MEM); - return -QDMA_ERR_NO_MEM; - } - len += rv; - } - } - - return len; -} - -/*****************************************************************************/ -/** - * qdma_dump_s80_hard_queue_context() - Function to get qdma queue context dump - * in a buffer - * - * @dev_hndl: device handle - * @hw_qid: queue id - * @buf : pointer to buffer to be filled - * @buflen : Length of the buffer - * - * Return: Length up-till the buffer is filled -success and < 0 - failure - *****************************************************************************/ -int qdma_s80_hard_dump_queue_context(void *dev_hndl, - uint8_t st, - enum qdma_dev_q_type q_type, - struct qdma_descq_context *ctxt_data, - char *buf, uint32_t buflen) -{ - int rv = 0; - uint32_t req_buflen = 0; - - if (!dev_hndl) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - - return -QDMA_ERR_INV_PARAM; - } - - if (!ctxt_data) { - qdma_log_error("%s: ctxt_data is NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - - return -QDMA_ERR_INV_PARAM; - } - - if (!buf) { - qdma_log_error("%s: buf is NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - - return -QDMA_ERR_INV_PARAM; - } - if (q_type >= QDMA_DEV_Q_TYPE_MAX) { - qdma_log_error("%s: invalid q_type, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - - return -QDMA_ERR_INV_PARAM; - } - - rv = qdma_s80_hard_context_buf_len(st, q_type, &req_buflen); - if (rv != QDMA_SUCCESS) - return rv; - - if (buflen < req_buflen) { - qdma_log_error("%s: Too small buffer(%d), reqd(%d), err:%d\n", - __func__, buflen, req_buflen, -QDMA_ERR_NO_MEM); - return -QDMA_ERR_NO_MEM; - } - - rv = dump_s80_hard_context(ctxt_data, st, q_type, - buf, buflen); - - return rv; -} - -/*****************************************************************************/ -/** - * qdma_dump_s80_hard_intr_context() - Function to get qdma interrupt - * context dump in a buffer - * - * @dev_hndl: device handle - * @hw_qid: queue id - * @buf : pointer to buffer to be filled - * @buflen : Length of the buffer - * - * Return: Length up-till the buffer is filled -success and < 0 - failure - *****************************************************************************/ -int qdma_s80_hard_dump_intr_context(void *dev_hndl, - struct qdma_indirect_intr_ctxt *intr_ctx, - int ring_index, - char *buf, uint32_t buflen) -{ - int rv = 0; - uint32_t req_buflen = 0; - - if (!dev_hndl) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - - return -QDMA_ERR_INV_PARAM; - } - - if (!intr_ctx) { - qdma_log_error("%s: intr_ctx is NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - - return -QDMA_ERR_INV_PARAM; - } - - if (!buf) { - qdma_log_error("%s: buf is NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - req_buflen = qdma_s80_hard_intr_context_buf_len(); - if (buflen < req_buflen) { - qdma_log_error("%s: Too small buffer(%d), reqd(%d), err:%d\n", - __func__, buflen, req_buflen, -QDMA_ERR_NO_MEM); - return -QDMA_ERR_NO_MEM; - } - - rv = dump_s80_hard_intr_context(intr_ctx, ring_index, buf, buflen); - - return rv; -} - -/*****************************************************************************/ -/** - * qdma_s80_hard_read_dump_queue_context() - Function to read and dump the queue - * context in a buffer - * - * @dev_hndl: device handle - * @hw_qid: queue id - * @st: Queue Mode(ST or MM) - * @q_type: Queue type(H2C/C2H/CMPT) - * @buf : pointer to buffer to be filled - * @buflen : Length of the buffer - * - * Return: Length up-till the buffer is filled -success and < 0 - failure - *****************************************************************************/ -int qdma_s80_hard_read_dump_queue_context(void *dev_hndl, - uint16_t qid_hw, - uint8_t st, - enum qdma_dev_q_type q_type, - char *buf, uint32_t buflen) -{ - int rv = QDMA_SUCCESS; - uint32_t req_buflen = 0; - struct qdma_descq_context context; - - if (!dev_hndl) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - - return -QDMA_ERR_INV_PARAM; - } - - if (!buf) { - qdma_log_error("%s: buf is NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - - return -QDMA_ERR_INV_PARAM; - } - - if (q_type >= QDMA_DEV_Q_TYPE_CMPT) { - qdma_log_error("%s: Not supported for q_type, err = %d\n", - __func__, -QDMA_ERR_INV_PARAM); - - return -QDMA_ERR_INV_PARAM; - } - - rv = qdma_s80_hard_context_buf_len(st, q_type, &req_buflen); - - if (rv != QDMA_SUCCESS) - return rv; - - if (buflen < req_buflen) { - qdma_log_error("%s: Too small buffer(%d), reqd(%d), err:%d\n", - __func__, buflen, req_buflen, -QDMA_ERR_NO_MEM); - return -QDMA_ERR_NO_MEM; - } - - qdma_memset(&context, 0, sizeof(struct qdma_descq_context)); - - if (q_type != QDMA_DEV_Q_TYPE_CMPT) { - rv = qdma_s80_hard_sw_ctx_conf(dev_hndl, (uint8_t)q_type, - qid_hw, &(context.sw_ctxt), - QDMA_HW_ACCESS_READ); - if (rv < 0) { - qdma_log_error( - "%s: Failed to read sw context, err = %d", - __func__, rv); - return rv; - } - - rv = qdma_s80_hard_hw_ctx_conf(dev_hndl, (uint8_t)q_type, - qid_hw, &(context.hw_ctxt), - QDMA_HW_ACCESS_READ); - if (rv < 0) { - qdma_log_error( - "%s: Failed to read hw context, err = %d", - __func__, rv); - return rv; - } - - rv = qdma_s80_hard_qid2vec_conf(dev_hndl, (uint8_t)q_type, - qid_hw, &(context.qid2vec), - QDMA_HW_ACCESS_READ); - if (rv < 0) { - qdma_log_error( - "%s: Failed to read qid2vec context, err = %d", - __func__, rv); - return rv; - } - - rv = qdma_s80_hard_credit_ctx_conf(dev_hndl, (uint8_t)q_type, - qid_hw, &(context.cr_ctxt), - QDMA_HW_ACCESS_READ); - if (rv < 0) { - qdma_log_error( - "%s: Failed to read credit context, err = %d", - __func__, rv); - return rv; - } - - if (st && (q_type == QDMA_DEV_Q_TYPE_C2H)) { - rv = qdma_s80_hard_pfetch_ctx_conf(dev_hndl, - qid_hw, - &(context.pfetch_ctxt), - QDMA_HW_ACCESS_READ); - if (rv < 0) { - qdma_log_error( - "%s: Failed to read pftech context, err = %d", - __func__, rv); - return rv; - } - } - } - - if ((st && (q_type == QDMA_DEV_Q_TYPE_C2H)) || - (!st && (q_type == QDMA_DEV_Q_TYPE_CMPT))) { - rv = qdma_s80_hard_cmpt_ctx_conf(dev_hndl, qid_hw, - &(context.cmpt_ctxt), - QDMA_HW_ACCESS_READ); - if (rv < 0) { - qdma_log_error( - "%s: Failed to read cmpt context, err = %d", - __func__, rv); - return rv; - } - } - - - - rv = dump_s80_hard_context(&context, st, q_type, - buf, buflen); - - return rv; -} - -/*****************************************************************************/ -/** - * qdma_s80_hard_init_ctxt_memory() - Initialize the context for all queues - * - * @dev_hndl : device handle - * - * Return : 0 - success and < 0 - failure - *****************************************************************************/ - -int qdma_s80_hard_init_ctxt_memory(void *dev_hndl) -{ -#ifdef ENABLE_INIT_CTXT_MEMORY - uint32_t data[QDMA_REG_IND_CTXT_REG_COUNT]; - uint16_t i = 0; - struct qdma_dev_attributes dev_info; - - if (!dev_hndl) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - qdma_memset(data, 0, sizeof(uint32_t) * QDMA_REG_IND_CTXT_REG_COUNT); - qdma_s80_hard_get_device_attributes(dev_hndl, &dev_info); - qdma_log_info("%s: clearing the context for all qs", - __func__); - for (; i < dev_info.num_qs; i++) { - int sel = QDMA_CTXT_SEL_SW_C2H; - int rv; - - for (; sel <= QDMA_CTXT_SEL_PFTCH; sel++) { - /** if the st mode(h2c/c2h) not enabled - * in the design, then skip the PFTCH - * and CMPT context setup - */ - if ((dev_info.st_en == 0) && - (sel == QDMA_CTXT_SEL_PFTCH || - sel == QDMA_CTXT_SEL_CMPT)) { - qdma_log_debug("%s: ST context is skipped:", - __func__); - qdma_log_debug(" sel = %d", sel); - continue; - } - - rv = qdma_s80_hard_indirect_reg_clear(dev_hndl, - (enum ind_ctxt_cmd_sel)sel, i); - if (rv < 0) - return rv; - } - } - - /* fmap */ - for (i = 0; i < dev_info.num_pfs; i++) - qdma_s80_hard_fmap_clear(dev_hndl, i); -#else - if (!dev_hndl) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } -#endif - return 0; -} - -static int get_reg_entry(uint32_t reg_addr, int *reg_entry) -{ - uint32_t i = 0; - struct xreg_info *reg_info; - uint32_t num_regs = qdma_s80_hard_config_num_regs_get(); - - reg_info = qdma_s80_hard_config_regs_get(); - - for (i = 0; (i < num_regs - 1); i++) { - if (reg_info[i].addr == reg_addr) { - *reg_entry = i; - break; - } - } - - if (i >= num_regs - 1) { - qdma_log_error("%s: 0x%08x is missing register list, err:%d\n", - __func__, - reg_addr, - -QDMA_ERR_INV_PARAM); - *reg_entry = -1; - return -QDMA_ERR_INV_PARAM; - } - - return 0; -} - -/*****************************************************************************/ -/** - * qdma_s80_hard_dump_config_reg_list() - Dump the registers - * - * @dev_hndl: device handle - * @total_regs : Max registers to read - * @reg_list : array of reg addr and reg values - * @buf : pointer to buffer to be filled - * @buflen : Length of the buffer - * - * Return: returns the platform specific error code - *****************************************************************************/ -int qdma_s80_hard_dump_config_reg_list(void *dev_hndl, uint32_t total_regs, - struct qdma_reg_data *reg_list, char *buf, uint32_t buflen) -{ - uint32_t j = 0, len = 0; - uint32_t reg_count = 0; - int reg_data_entry; - int rv = 0; - char name[DEBGFS_GEN_NAME_SZ] = ""; - struct xreg_info *reg_info = qdma_s80_hard_config_regs_get(); - - if (!dev_hndl) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - if (!buf) { - qdma_log_error("%s: buf is NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - for (reg_count = 0; - (reg_count < total_regs);) { - - rv = get_reg_entry(reg_list[reg_count].reg_addr, - ®_data_entry); - if (rv < 0) { - qdma_log_error("%s: register missing in list, err:%d\n", - __func__, - -QDMA_ERR_INV_PARAM); - return rv; - } - - for (j = 0; j < reg_info[reg_data_entry].repeat; j++) { - rv = QDMA_SNPRINTF_S(name, DEBGFS_GEN_NAME_SZ, - DEBGFS_GEN_NAME_SZ, - "%s_%d", - reg_info[reg_data_entry].name, j); - if ((rv < 0) || (rv > DEBGFS_GEN_NAME_SZ)) { - qdma_log_error( - "%d:%s snprintf failed, err:%d\n", - __LINE__, __func__, - rv); - return -QDMA_ERR_NO_MEM; - } - rv = dump_reg(buf + len, buflen - len, - (reg_info[reg_data_entry].addr + (j * 4)), - name, - reg_list[reg_count + j].reg_val); - if (rv < 0) { - qdma_log_error( - "%s Buff too small, err:%d\n", - __func__, - -QDMA_ERR_NO_MEM); - return -QDMA_ERR_NO_MEM; - } - len += rv; - } - reg_count += j; - } - - return len; - -} - - -/*****************************************************************************/ -/** - * qdma_read_reg_list() - read the register values - * - * @dev_hndl: device handle - * @is_vf: Whether PF or VF - * @total_regs : Max registers to read - * @reg_list : array of reg addr and reg values - * - * Return: returns the platform specific error code - *****************************************************************************/ -int qdma_s80_hard_read_reg_list(void *dev_hndl, uint8_t is_vf, - uint16_t reg_rd_slot, - uint16_t *total_regs, - struct qdma_reg_data *reg_list) -{ - uint16_t reg_count = 0, i = 0, j = 0; - uint32_t num_regs = qdma_s80_hard_config_num_regs_get(); - struct xreg_info *reg_info = qdma_s80_hard_config_regs_get(); - struct qdma_dev_attributes dev_cap; - uint32_t reg_start_addr = 0; - int reg_index = 0; - int rv = 0; - - if (!is_vf) { - qdma_log_error("%s: not supported for PF, err:%d\n", - __func__, - -QDMA_ERR_HWACC_FEATURE_NOT_SUPPORTED); - return -QDMA_ERR_HWACC_FEATURE_NOT_SUPPORTED; - } - - if (!dev_hndl) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - if (!reg_list) { - qdma_log_error("%s: reg_list is NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - qdma_s80_hard_get_device_attributes(dev_hndl, &dev_cap); - - switch (reg_rd_slot) { - case QDMA_REG_READ_GROUP_1: - reg_start_addr = QDMA_S80_REG_GROUP_1_START_ADDR; - break; - case QDMA_REG_READ_GROUP_2: - reg_start_addr = QDMA_S80_REG_GROUP_2_START_ADDR; - break; - case QDMA_REG_READ_GROUP_3: - reg_start_addr = QDMA_S80_REG_GROUP_3_START_ADDR; - break; - case QDMA_REG_READ_GROUP_4: - reg_start_addr = QDMA_S80_REG_GROUP_4_START_ADDR; - break; - default: - qdma_log_error("%s: Invalid slot received\n", - __func__); - return -QDMA_ERR_INV_PARAM; - } - - rv = get_reg_entry(reg_start_addr, ®_index); - if (rv < 0) { - qdma_log_error("%s: register missing in list, err:%d\n", - __func__, - -QDMA_ERR_INV_PARAM); - return rv; - } - - for (i = 0, reg_count = 0; - ((i < num_regs - 1 - reg_index) && - (reg_count < QDMA_MAX_REGISTER_DUMP)); i++) { - - if (((GET_CAPABILITY_MASK(dev_cap.mm_en, dev_cap.st_en, - dev_cap.mm_cmpt_en, dev_cap.mailbox_en) - & reg_info[i].mode) == 0) || - (reg_info[i].read_type == QDMA_REG_READ_PF_ONLY)) - continue; - - for (j = 0; j < reg_info[i].repeat && - (reg_count < QDMA_MAX_REGISTER_DUMP); - j++) { - reg_list[reg_count].reg_addr = - (reg_info[i].addr + (j * 4)); - reg_list[reg_count].reg_val = - qdma_reg_read(dev_hndl, - reg_list[reg_count].reg_addr); - reg_count++; - } - } - - *total_regs = reg_count; - return rv; -} - -/*****************************************************************************/ -/** - * qdma_s80_hard_write_global_ring_sizes() - set the global ring size array - * - * @dev_hndl: device handle - * @index: Index from where the values needs to written - * @count: number of entries to be written - * @glbl_rng_sz: pointer to the array having the values to write - * - * (index + count) shall not be more than 16 - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -static int qdma_s80_hard_write_global_ring_sizes(void *dev_hndl, uint8_t index, - uint8_t count, const uint32_t *glbl_rng_sz) -{ - if (!dev_hndl || !glbl_rng_sz || !count) { - qdma_log_error("%s: dev_hndl=%p glbl_rng_sz=%p, err:%d\n", - __func__, dev_hndl, glbl_rng_sz, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - if ((index + count) > QDMA_NUM_RING_SIZES) { - qdma_log_error("%s: index=%u count=%u > %d, err:%d\n", - __func__, index, count, - QDMA_NUM_RING_SIZES, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - qdma_write_csr_values(dev_hndl, - QDMA_S80_HARD_GLBL_RNG_SZ_1_ADDR, index, count, - glbl_rng_sz); - - return QDMA_SUCCESS; -} - -/*****************************************************************************/ -/** - * qdma_s80_hard_read_global_ring_sizes() - function to get the - * global rng_sz array - * - * @dev_hndl: device handle - * @index: Index from where the values needs to read - * @count: number of entries to be read - * @glbl_rng_sz: pointer to array to hold the values read - * - * (index + count) shall not be more than 16 - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -static int qdma_s80_hard_read_global_ring_sizes(void *dev_hndl, uint8_t index, - uint8_t count, uint32_t *glbl_rng_sz) -{ - if (!dev_hndl || !glbl_rng_sz || !count) { - qdma_log_error("%s: dev_hndl=%p glbl_rng_sz=%p, err:%d\n", - __func__, dev_hndl, glbl_rng_sz, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - if ((index + count) > QDMA_NUM_RING_SIZES) { - qdma_log_error("%s: index=%u count=%u > %d, err:%d\n", - __func__, index, count, - QDMA_NUM_C2H_BUFFER_SIZES, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - qdma_read_csr_values(dev_hndl, - QDMA_S80_HARD_GLBL_RNG_SZ_1_ADDR, index, count, - glbl_rng_sz); - - return QDMA_SUCCESS; -} - -/*****************************************************************************/ -/** - * qdma_s80_hard_write_global_timer_count() - function to set the timer values - * - * @dev_hndl: device handle - * @glbl_tmr_cnt: pointer to the array having the values to write - * @index: Index from where the values needs to written - * @count: number of entries to be written - * - * (index + count) shall not be more than 16 - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -static int qdma_s80_hard_write_global_timer_count(void *dev_hndl, uint8_t index, - uint8_t count, const uint32_t *glbl_tmr_cnt) -{ - struct qdma_dev_attributes dev_cap; - - if (!dev_hndl || !glbl_tmr_cnt || !count) { - qdma_log_error("%s: dev_hndl=%p glbl_tmr_cnt=%p, err:%d\n", - __func__, dev_hndl, glbl_tmr_cnt, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - if ((index + count) > QDMA_NUM_C2H_TIMERS) { - qdma_log_error("%s: index=%u count=%u > %d, err:%d\n", - __func__, index, count, - QDMA_NUM_C2H_TIMERS, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - qdma_s80_hard_get_device_attributes(dev_hndl, &dev_cap); - - if (dev_cap.st_en || dev_cap.mm_cmpt_en) - qdma_write_csr_values(dev_hndl, - QDMA_S80_HARD_C2H_TIMER_CNT_1_ADDR, - index, count, glbl_tmr_cnt); - else { - qdma_log_error("%s: ST or MM cmpt not supported, err:%d\n", - __func__, - -QDMA_ERR_HWACC_FEATURE_NOT_SUPPORTED); - return -QDMA_ERR_HWACC_FEATURE_NOT_SUPPORTED; - } - - return QDMA_SUCCESS; -} - -/*****************************************************************************/ -/** - * qdma_s80_hard_read_global_timer_count() - function to get the timer values - * - * @dev_hndl: device handle - * @index: Index from where the values needs to read - * @count: number of entries to be read - * @glbl_tmr_cnt: pointer to array to hold the values read - * - * (index + count) shall not be more than 16 - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -static int qdma_s80_hard_read_global_timer_count(void *dev_hndl, uint8_t index, - uint8_t count, uint32_t *glbl_tmr_cnt) -{ - struct qdma_dev_attributes dev_cap; - - if (!dev_hndl || !glbl_tmr_cnt || !count) { - qdma_log_error("%s: dev_hndl=%p glbl_tmr_cnt=%p, err:%d\n", - __func__, dev_hndl, glbl_tmr_cnt, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - if ((index + count) > QDMA_NUM_C2H_TIMERS) { - qdma_log_error("%s: index=%u count=%u > %d, err:%d\n", - __func__, index, count, - QDMA_NUM_C2H_TIMERS, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - qdma_s80_hard_get_device_attributes(dev_hndl, &dev_cap); - - if (dev_cap.st_en || dev_cap.mm_cmpt_en) - qdma_read_csr_values(dev_hndl, - QDMA_S80_HARD_C2H_TIMER_CNT_1_ADDR, index, - count, glbl_tmr_cnt); - else { - qdma_log_error("%s: ST or MM cmpt not supported, err:%d\n", - __func__, - -QDMA_ERR_HWACC_FEATURE_NOT_SUPPORTED); - return -QDMA_ERR_HWACC_FEATURE_NOT_SUPPORTED; - } - - return QDMA_SUCCESS; -} - -/*****************************************************************************/ -/** - * qdma_s80_hard_write_global_counter_threshold() - function to set the counter - * threshold values - * - * @dev_hndl: device handle - * @index: Index from where the values needs to written - * @count: number of entries to be written - * @glbl_cnt_th: pointer to the array having the values to write - * - * (index + count) shall not be more than 16 - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -static int qdma_s80_hard_write_global_counter_threshold(void *dev_hndl, - uint8_t index, - uint8_t count, const uint32_t *glbl_cnt_th) -{ - struct qdma_dev_attributes dev_cap; - - if (!dev_hndl || !glbl_cnt_th || !count) { - qdma_log_error("%s: dev_hndl=%p glbl_cnt_th=%p, err:%d\n", - __func__, dev_hndl, glbl_cnt_th, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - if ((index + count) > QDMA_NUM_C2H_COUNTERS) { - qdma_log_error("%s: index=%u count=%u > %d, err:%d\n", - __func__, index, count, - QDMA_NUM_C2H_BUFFER_SIZES, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - qdma_s80_hard_get_device_attributes(dev_hndl, &dev_cap); - - if (dev_cap.st_en || dev_cap.mm_cmpt_en) - qdma_write_csr_values(dev_hndl, - QDMA_S80_HARD_C2H_CNT_TH_1_ADDR, index, - count, glbl_cnt_th); - else { - qdma_log_error("%s: ST or MM cmpt not supported, err:%d\n", - __func__, - -QDMA_ERR_HWACC_FEATURE_NOT_SUPPORTED); - return -QDMA_ERR_HWACC_FEATURE_NOT_SUPPORTED; - } - - return QDMA_SUCCESS; -} - -/*****************************************************************************/ -/** - * qdma_s80_hard_read_global_counter_threshold() - get the counter - * threshold values - * - * @dev_hndl: device handle - * @index: Index from where the values needs to read - * @count: number of entries to be read - * @glbl_cnt_th: pointer to array to hold the values read - * - * (index + count) shall not be more than 16 - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -static int qdma_s80_hard_read_global_counter_threshold(void *dev_hndl, - uint8_t index, - uint8_t count, uint32_t *glbl_cnt_th) -{ - struct qdma_dev_attributes dev_cap; - - if (!dev_hndl || !glbl_cnt_th || !count) { - qdma_log_error("%s: dev_hndl=%p glbl_cnt_th=%p, err:%d\n", - __func__, dev_hndl, glbl_cnt_th, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - if ((index + count) > QDMA_NUM_C2H_COUNTERS) { - qdma_log_error("%s: index=%u count=%u > %d, err:%d\n", - __func__, index, count, - QDMA_NUM_C2H_COUNTERS, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - qdma_s80_hard_get_device_attributes(dev_hndl, &dev_cap); - - if (dev_cap.st_en || dev_cap.mm_cmpt_en) - qdma_read_csr_values(dev_hndl, - QDMA_S80_HARD_C2H_CNT_TH_1_ADDR, index, - count, glbl_cnt_th); - else { - qdma_log_error("%s: ST or MM cmpt not supported, err:%d\n", - __func__, -QDMA_ERR_HWACC_FEATURE_NOT_SUPPORTED); - return -QDMA_ERR_HWACC_FEATURE_NOT_SUPPORTED; - } - - return QDMA_SUCCESS; -} - -/*****************************************************************************/ -/** - * qdma_s80_hard_write_global_buffer_sizes() - function to set the buffer sizes - * - * @dev_hndl: device handle - * @index: Index from where the values needs to written - * @count: number of entries to be written - * @glbl_buf_sz: pointer to the array having the values to write - * - * (index + count) shall not be more than 16 - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -static int qdma_s80_hard_write_global_buffer_sizes(void *dev_hndl, - uint8_t index, - uint8_t count, const uint32_t *glbl_buf_sz) -{ - struct qdma_dev_attributes dev_cap; - - if (!dev_hndl || !glbl_buf_sz || !count) { - qdma_log_error("%s: dev_hndl=%p glbl_buf_sz=%p, err:%d\n", - __func__, dev_hndl, glbl_buf_sz, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - if ((index + count) > QDMA_NUM_C2H_BUFFER_SIZES) { - qdma_log_error("%s: index=%u count=%u > %d, err:%d\n", - __func__, index, count, - QDMA_NUM_C2H_BUFFER_SIZES, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - qdma_s80_hard_get_device_attributes(dev_hndl, &dev_cap); - - if (dev_cap.st_en) - qdma_write_csr_values(dev_hndl, - QDMA_S80_HARD_C2H_BUF_SZ_0_ADDR, index, - count, glbl_buf_sz); - else { - qdma_log_error("%s: ST not supported, err:%d\n", - __func__, - -QDMA_ERR_HWACC_FEATURE_NOT_SUPPORTED); - return -QDMA_ERR_HWACC_FEATURE_NOT_SUPPORTED; - } - - return QDMA_SUCCESS; -} - -/*****************************************************************************/ -/** - * qdma_s80_hard_read_global_buffer_sizes() - function to get the buffer sizes - * - * @dev_hndl: device handle - * @index: Index from where the values needs to read - * @count: number of entries to be read - * @glbl_buf_sz: pointer to array to hold the values read - * - * (index + count) shall not be more than 16 - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -static int qdma_s80_hard_read_global_buffer_sizes(void *dev_hndl, uint8_t index, - uint8_t count, uint32_t *glbl_buf_sz) -{ - struct qdma_dev_attributes dev_cap; - - if (!dev_hndl || !glbl_buf_sz || !count) { - qdma_log_error("%s: dev_hndl=%p glbl_buf_sz=%p, err:%d\n", - __func__, dev_hndl, glbl_buf_sz, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - if ((index + count) > QDMA_NUM_C2H_BUFFER_SIZES) { - qdma_log_error("%s: index=%u count=%u > %d, err:%d\n", - __func__, index, count, - QDMA_NUM_C2H_BUFFER_SIZES, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - qdma_s80_hard_get_device_attributes(dev_hndl, &dev_cap); - - if (dev_cap.st_en) - qdma_read_csr_values(dev_hndl, - QDMA_S80_HARD_C2H_BUF_SZ_0_ADDR, index, - count, glbl_buf_sz); - else { - qdma_log_error("%s: ST is not supported, err:%d\n", - __func__, - -QDMA_ERR_HWACC_FEATURE_NOT_SUPPORTED); - return -QDMA_ERR_HWACC_FEATURE_NOT_SUPPORTED; - } - - return QDMA_SUCCESS; -} - -/*****************************************************************************/ -/** - * qdma_s80_hard_global_csr_conf() - function to configure global csr - * - * @dev_hndl: device handle - * @index: Index from where the values needs to read - * @count: number of entries to be read - * @csr_val: uint32_t pointer to csr value - * @csr_type: Type of the CSR (qdma_global_csr_type enum) to configure - * @access_type HW access type (qdma_hw_access_type enum) value - * QDMA_HW_ACCESS_CLEAR - Not supported - * QDMA_HW_ACCESS_INVALIDATE - Not supported - * - * (index + count) shall not be more than 16 - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -int qdma_s80_hard_global_csr_conf(void *dev_hndl, uint8_t index, uint8_t count, - uint32_t *csr_val, - enum qdma_global_csr_type csr_type, - enum qdma_hw_access_type access_type) -{ - int rv = QDMA_SUCCESS; - - switch (csr_type) { - case QDMA_CSR_RING_SZ: - switch (access_type) { - case QDMA_HW_ACCESS_READ: - rv = qdma_s80_hard_read_global_ring_sizes( - dev_hndl, - index, - count, - csr_val); - break; - case QDMA_HW_ACCESS_WRITE: - rv = qdma_s80_hard_write_global_ring_sizes( - dev_hndl, - index, - count, - csr_val); - break; - default: - qdma_log_error("%s: access_type(%d) invalid, err:%d\n", - __func__, - access_type, - -QDMA_ERR_INV_PARAM); - rv = -QDMA_ERR_INV_PARAM; - break; - } - break; - case QDMA_CSR_TIMER_CNT: - switch (access_type) { - case QDMA_HW_ACCESS_READ: - rv = qdma_s80_hard_read_global_timer_count( - dev_hndl, - index, - count, - csr_val); - break; - case QDMA_HW_ACCESS_WRITE: - rv = qdma_s80_hard_write_global_timer_count( - dev_hndl, - index, - count, - csr_val); - break; - default: - qdma_log_error("%s: access_type(%d) invalid, err:%d\n", - __func__, - access_type, - -QDMA_ERR_INV_PARAM); - rv = -QDMA_ERR_INV_PARAM; - break; - } - break; - case QDMA_CSR_CNT_TH: - switch (access_type) { - case QDMA_HW_ACCESS_READ: - rv = - qdma_s80_hard_read_global_counter_threshold( - dev_hndl, - index, - count, - csr_val); - break; - case QDMA_HW_ACCESS_WRITE: - rv = - qdma_s80_hard_write_global_counter_threshold( - dev_hndl, - index, - count, - csr_val); - break; - default: - qdma_log_error("%s: access_type(%d) invalid, err:%d\n", - __func__, - access_type, - -QDMA_ERR_INV_PARAM); - rv = -QDMA_ERR_INV_PARAM; - break; - } - break; - case QDMA_CSR_BUF_SZ: - switch (access_type) { - case QDMA_HW_ACCESS_READ: - rv = - qdma_s80_hard_read_global_buffer_sizes(dev_hndl, - index, - count, - csr_val); - break; - case QDMA_HW_ACCESS_WRITE: - rv = - qdma_s80_hard_write_global_buffer_sizes(dev_hndl, - index, - count, - csr_val); - break; - default: - qdma_log_error("%s: access_type(%d) invalid, err:%d\n", - __func__, - access_type, - -QDMA_ERR_INV_PARAM); - rv = -QDMA_ERR_INV_PARAM; - break; - } - break; - default: - qdma_log_error("%s: csr_type(%d) invalid, err:%d\n", - __func__, - csr_type, - -QDMA_ERR_INV_PARAM); - rv = -QDMA_ERR_INV_PARAM; - break; - } - - return rv; -} - -/*****************************************************************************/ -/** - * qdma_s80_hard_global_writeback_interval_write() - function to set the - * writeback interval - * - * @dev_hndl device handle - * @wb_int: Writeback Interval - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -static int qdma_s80_hard_global_writeback_interval_write(void *dev_hndl, - enum qdma_wrb_interval wb_int) -{ - uint32_t reg_val; - struct qdma_dev_attributes dev_cap; - - if (!dev_hndl) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", __func__, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - if (wb_int >= QDMA_NUM_WRB_INTERVALS) { - qdma_log_error("%s: wb_int=%d is invalid, err:%d\n", - __func__, wb_int, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - qdma_s80_hard_get_device_attributes(dev_hndl, &dev_cap); - - if (dev_cap.st_en || dev_cap.mm_cmpt_en) { - reg_val = qdma_reg_read(dev_hndl, - QDMA_S80_HARD_GLBL_DSC_CFG_ADDR); - reg_val |= FIELD_SET(GLBL_DSC_CFG_WB_ACC_INT_MASK, wb_int); - - qdma_reg_write(dev_hndl, - QDMA_S80_HARD_GLBL_DSC_CFG_ADDR, reg_val); - } else { - qdma_log_error("%s: ST or MM cmpt not supported, err:%d\n", - __func__, -QDMA_ERR_HWACC_FEATURE_NOT_SUPPORTED); - return -QDMA_ERR_HWACC_FEATURE_NOT_SUPPORTED; - } - - return QDMA_SUCCESS; -} - -/*****************************************************************************/ -/** - * qdma_s80_hard_global_writeback_interval_read() - function to get the - * writeback interval - * - * @dev_hndl: device handle - * @wb_int: pointer to the data to hold Writeback Interval - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -static int qdma_s80_hard_global_writeback_interval_read(void *dev_hndl, - enum qdma_wrb_interval *wb_int) -{ - uint32_t reg_val; - struct qdma_dev_attributes dev_cap; - - if (!dev_hndl) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", __func__, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - if (!wb_int) { - qdma_log_error("%s: wb_int is NULL, err:%d\n", __func__, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - qdma_s80_hard_get_device_attributes(dev_hndl, &dev_cap); - - if (dev_cap.st_en || dev_cap.mm_cmpt_en) { - reg_val = qdma_reg_read(dev_hndl, - QDMA_S80_HARD_GLBL_DSC_CFG_ADDR); - *wb_int = (enum qdma_wrb_interval)FIELD_GET( - GLBL_DSC_CFG_WB_ACC_INT_MASK, reg_val); - } else { - qdma_log_error("%s: ST or MM cmpt not supported, err:%d\n", - __func__, -QDMA_ERR_HWACC_FEATURE_NOT_SUPPORTED); - return -QDMA_ERR_HWACC_FEATURE_NOT_SUPPORTED; - } - - return QDMA_SUCCESS; -} - -/*****************************************************************************/ -/** - * qdma_s80_hard_global_writeback_interval_conf() - function to configure - * the writeback interval - * - * @dev_hndl: device handle - * @wb_int: pointer to the data to hold Writeback Interval - * @access_type HW access type (qdma_hw_access_type enum) value - * QDMA_HW_ACCESS_CLEAR - Not supported - * QDMA_HW_ACCESS_INVALIDATE - Not supported - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -int qdma_s80_hard_global_writeback_interval_conf(void *dev_hndl, - enum qdma_wrb_interval *wb_int, - enum qdma_hw_access_type access_type) -{ - int rv = QDMA_SUCCESS; - - switch (access_type) { - case QDMA_HW_ACCESS_READ: - rv = - qdma_s80_hard_global_writeback_interval_read(dev_hndl, wb_int); - break; - case QDMA_HW_ACCESS_WRITE: - rv = - qdma_s80_hard_global_writeback_interval_write(dev_hndl, - *wb_int); - break; - case QDMA_HW_ACCESS_CLEAR: - case QDMA_HW_ACCESS_INVALIDATE: - default: - qdma_log_error("%s: access_type(%d) invalid, err:%d\n", - __func__, - access_type, - -QDMA_ERR_INV_PARAM); - rv = -QDMA_ERR_INV_PARAM; - break; - } - - return rv; -} - - -/*****************************************************************************/ -/** - * qdma_s80_hard_mm_channel_conf() - Function to enable/disable the MM channel - * - * @dev_hndl: device handle - * @channel: MM channel number - * @is_c2h: Queue direction. Set 1 for C2H and 0 for H2C - * @enable: Enable or disable MM channel - * - * Presently, we have only 1 MM channel - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -int qdma_s80_hard_mm_channel_conf(void *dev_hndl, uint8_t channel, - uint8_t is_c2h, - uint8_t enable) -{ - uint32_t reg_addr = (is_c2h) ? QDMA_S80_HARD_C2H_CHANNEL_CTL_ADDR : - QDMA_S80_HARD_H2C_CHANNEL_CTL_ADDR; - struct qdma_dev_attributes dev_cap; - - if (!dev_hndl) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - qdma_s80_hard_get_device_attributes(dev_hndl, &dev_cap); - - if (dev_cap.mm_en) { - qdma_reg_write(dev_hndl, - reg_addr + (channel * QDMA_MM_CONTROL_STEP), - enable); - } - - return QDMA_SUCCESS; -} - -int qdma_s80_hard_dump_reg_info(void *dev_hndl, uint32_t reg_addr, - uint32_t num_regs, char *buf, uint32_t buflen) -{ - uint32_t total_num_regs = qdma_s80_hard_config_num_regs_get(); - struct xreg_info *config_regs = qdma_s80_hard_config_regs_get(); - const char *bitfield_name; - uint32_t i = 0, num_regs_idx = 0, k = 0, j = 0, - bitfield = 0, lsb = 0, msb = 31; - int rv = 0; - uint32_t reg_val; - uint32_t data_len = 0; - - if (!dev_hndl) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - for (i = 0; i < total_num_regs; i++) { - if (reg_addr == config_regs[i].addr) { - j = i; - break; - } - } - - if (i == total_num_regs) { - qdma_log_error("%s: Register not found err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - if (buf) - QDMA_SNPRINTF_S(buf, buflen, - DEBGFS_LINE_SZ, - "Register not found 0x%x\n", reg_addr); - return -QDMA_ERR_INV_PARAM; - } - - num_regs_idx = (j + num_regs < total_num_regs) ? - (j + num_regs) : total_num_regs; - - for (; j < num_regs_idx ; j++) { - reg_val = qdma_reg_read(dev_hndl, - config_regs[j].addr); - - if (buf) { - rv = QDMA_SNPRINTF_S(buf, buflen, - DEBGFS_LINE_SZ, - "\n%-40s 0x%-7x %-#10x %-10d\n", - config_regs[j].name, - config_regs[j].addr, - reg_val, reg_val); - if ((rv < 0) || (rv > DEBGFS_LINE_SZ)) { - qdma_log_error( - "%s: Insufficient buffer, err:%d\n", - __func__, -QDMA_ERR_NO_MEM); - return -QDMA_ERR_NO_MEM; - } - buf += rv; - data_len += rv; - buflen -= rv; - } else - qdma_log_info("%-40s 0x%-7x %-#10x %-10d\n", - config_regs[j].name, - config_regs[j].addr, - reg_val, reg_val); - - - for (k = 0; - k < config_regs[j].num_bitfields; k++) { - - bitfield = - config_regs[j].bitfields[k].field_mask; - bitfield_name = - config_regs[i].bitfields[k].field_name; - lsb = 0; - msb = 31; - - while (!(BIT(lsb) & bitfield)) - lsb++; - - while (!(BIT(msb) & bitfield)) - msb--; - - if (msb != lsb) { - if (buf) { - rv = QDMA_SNPRINTF_S(buf, buflen, - DEBGFS_LINE_SZ, - "%-40s [%2u,%2u] %#-10x\n", - bitfield_name, - msb, lsb, - (reg_val & bitfield) >> - lsb); - if ((rv < 0) || (rv > DEBGFS_LINE_SZ)) { - qdma_log_error( - "%s: Insufficient buffer, err:%d\n", - __func__, - -QDMA_ERR_NO_MEM); - return -QDMA_ERR_NO_MEM; - } - buf += rv; - data_len += rv; - buflen -= rv; - } else - qdma_log_info( - "%-40s [%2u,%2u] %#-10x\n", - bitfield_name, - msb, lsb, - (reg_val & bitfield) >> lsb); - - - } else { - if (buf) { - rv = QDMA_SNPRINTF_S(buf, buflen, - DEBGFS_LINE_SZ, - "%-40s [%5u] %#-10x\n", - bitfield_name, - lsb, - (reg_val & bitfield) >> - lsb); - if ((rv < 0) || (rv > DEBGFS_LINE_SZ)) { - qdma_log_error( - "%s: Insufficient buffer, err:%d\n", - __func__, - -QDMA_ERR_NO_MEM); - return -QDMA_ERR_NO_MEM; - } - buf += rv; - data_len += rv; - buflen -= rv; - } else - qdma_log_info( - "%-40s [%5u] %#-10x\n", - bitfield_name, - lsb, - (reg_val & bitfield) >> lsb); - - } - } - } - - return data_len; - -} diff --git a/QDMA/windows/sys/libqdma/source/qdma_access/qdma_s80_hard_access/qdma_s80_hard_access.h b/QDMA/windows/sys/libqdma/source/qdma_access/qdma_s80_hard_access/qdma_s80_hard_access.h deleted file mode 100644 index 8ae6d601c..000000000 --- a/QDMA/windows/sys/libqdma/source/qdma_access/qdma_s80_hard_access/qdma_s80_hard_access.h +++ /dev/null @@ -1,278 +0,0 @@ -/* - * Copyright (C) 2020 Xilinx, Inc - * - * Licensed under the Apache License, Version 2.0 (the "License"). You may - * not use this file except in compliance with the License. You may obtain - * a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - */ - -#ifndef __QDMA_S80_HARD_ACCESS_H_ -#define __QDMA_S80_HARD_ACCESS_H_ - -#ifdef __cplusplus -extern "C" { -#endif - -#include "qdma_platform.h" - -/** - * enum qdma_error_idx - qdma errors - */ -enum qdma_s80_hard_error_idx { - /* Descriptor errors */ - QDMA_S80_HARD_DSC_ERR_POISON, - QDMA_S80_HARD_DSC_ERR_UR_CA, - QDMA_S80_HARD_DSC_ERR_PARAM, - QDMA_S80_HARD_DSC_ERR_ADDR, - QDMA_S80_HARD_DSC_ERR_TAG, - QDMA_S80_HARD_DSC_ERR_FLR, - QDMA_S80_HARD_DSC_ERR_TIMEOUT, - QDMA_S80_HARD_DSC_ERR_DAT_POISON, - QDMA_S80_HARD_DSC_ERR_FLR_CANCEL, - QDMA_S80_HARD_DSC_ERR_DMA, - QDMA_S80_HARD_DSC_ERR_DSC, - QDMA_S80_HARD_DSC_ERR_RQ_CANCEL, - QDMA_S80_HARD_DSC_ERR_DBE, - QDMA_S80_HARD_DSC_ERR_SBE, - QDMA_S80_HARD_DSC_ERR_ALL, - - /* TRQ Errors */ - QDMA_S80_HARD_TRQ_ERR_UNMAPPED, - QDMA_S80_HARD_TRQ_ERR_QID_RANGE, - QDMA_S80_HARD_TRQ_ERR_VF_ACCESS_ERR, - QDMA_S80_HARD_TRQ_ERR_TCP_TIMEOUT, - QDMA_S80_HARD_TRQ_ERR_ALL, - - /* C2H Errors */ - QDMA_S80_HARD_ST_C2H_ERR_MTY_MISMATCH, - QDMA_S80_HARD_ST_C2H_ERR_LEN_MISMATCH, - QDMA_S80_HARD_ST_C2H_ERR_QID_MISMATCH, - QDMA_S80_HARD_ST_C2H_ERR_DESC_RSP_ERR, - QDMA_S80_HARD_ST_C2H_ERR_ENG_WPL_DATA_PAR_ERR, - QDMA_S80_HARD_ST_C2H_ERR_MSI_INT_FAIL, - QDMA_S80_HARD_ST_C2H_ERR_ERR_DESC_CNT, - QDMA_S80_HARD_ST_C2H_ERR_PORTID_CTXT_MISMATCH, - QDMA_S80_HARD_ST_C2H_ERR_PORTID_BYP_IN_MISMATCH, - QDMA_S80_HARD_ST_C2H_ERR_WRB_INV_Q_ERR, - QDMA_S80_HARD_ST_C2H_ERR_WRB_QFULL_ERR, - QDMA_S80_HARD_ST_C2H_ERR_WRB_CIDX_ERR, - QDMA_S80_HARD_ST_C2H_ERR_WRB_PRTY_ERR, - QDMA_S80_HARD_ST_C2H_ERR_ALL, - - /* Fatal Errors */ - QDMA_S80_HARD_ST_FATAL_ERR_MTY_MISMATCH, - QDMA_S80_HARD_ST_FATAL_ERR_LEN_MISMATCH, - QDMA_S80_HARD_ST_FATAL_ERR_QID_MISMATCH, - QDMA_S80_HARD_ST_FATAL_ERR_TIMER_FIFO_RAM_RDBE, - QDMA_S80_HARD_ST_FATAL_ERR_PFCH_II_RAM_RDBE, - QDMA_S80_HARD_ST_FATAL_ERR_WRB_CTXT_RAM_RDBE, - QDMA_S80_HARD_ST_FATAL_ERR_PFCH_CTXT_RAM_RDBE, - QDMA_S80_HARD_ST_FATAL_ERR_DESC_REQ_FIFO_RAM_RDBE, - QDMA_S80_HARD_ST_FATAL_ERR_INT_CTXT_RAM_RDBE, - QDMA_S80_HARD_ST_FATAL_ERR_INT_QID2VEC_RAM_RDBE, - QDMA_S80_HARD_ST_FATAL_ERR_WRB_COAL_DATA_RAM_RDBE, - QDMA_S80_HARD_ST_FATAL_ERR_TUSER_FIFO_RAM_RDBE, - QDMA_S80_HARD_ST_FATAL_ERR_QID_FIFO_RAM_RDBE, - QDMA_S80_HARD_ST_FATAL_ERR_PAYLOAD_FIFO_RAM_RDBE, - QDMA_S80_HARD_ST_FATAL_ERR_WPL_DATA_PAR_ERR, - QDMA_S80_HARD_ST_FATAL_ERR_ALL, - - /* H2C Errors */ - QDMA_S80_HARD_ST_H2C_ERR_ZERO_LEN_DESC_ERR, - QDMA_S80_HARD_ST_H2C_ERR_SDI_MRKR_REQ_MOP_ERR, - QDMA_S80_HARD_ST_H2C_ERR_NO_DMA_DSC, - QDMA_S80_HARD_ST_H2C_ERR_DBE, - QDMA_S80_HARD_ST_H2C_ERR_SBE, - QDMA_S80_HARD_ST_H2C_ERR_ALL, - - /* Single bit errors */ - QDMA_S80_HARD_SBE_ERR_MI_H2C0_DAT, - QDMA_S80_HARD_SBE_ERR_MI_C2H0_DAT, - QDMA_S80_HARD_SBE_ERR_H2C_RD_BRG_DAT, - QDMA_S80_HARD_SBE_ERR_H2C_WR_BRG_DAT, - QDMA_S80_HARD_SBE_ERR_C2H_RD_BRG_DAT, - QDMA_S80_HARD_SBE_ERR_C2H_WR_BRG_DAT, - QDMA_S80_HARD_SBE_ERR_FUNC_MAP, - QDMA_S80_HARD_SBE_ERR_DSC_HW_CTXT, - QDMA_S80_HARD_SBE_ERR_DSC_CRD_RCV, - QDMA_S80_HARD_SBE_ERR_DSC_SW_CTXT, - QDMA_S80_HARD_SBE_ERR_DSC_CPLI, - QDMA_S80_HARD_SBE_ERR_DSC_CPLD, - QDMA_S80_HARD_SBE_ERR_PASID_CTXT_RAM, - QDMA_S80_HARD_SBE_ERR_TIMER_FIFO_RAM, - QDMA_S80_HARD_SBE_ERR_PAYLOAD_FIFO_RAM, - QDMA_S80_HARD_SBE_ERR_QID_FIFO_RAM, - QDMA_S80_HARD_SBE_ERR_TUSER_FIFO_RAM, - QDMA_S80_HARD_SBE_ERR_WRB_COAL_DATA_RAM, - QDMA_S80_HARD_SBE_ERR_INT_QID2VEC_RAM, - QDMA_S80_HARD_SBE_ERR_INT_CTXT_RAM, - QDMA_S80_HARD_SBE_ERR_DESC_REQ_FIFO_RAM, - QDMA_S80_HARD_SBE_ERR_PFCH_CTXT_RAM, - QDMA_S80_HARD_SBE_ERR_WRB_CTXT_RAM, - QDMA_S80_HARD_SBE_ERR_PFCH_LL_RAM, - QDMA_S80_HARD_SBE_ERR_ALL, - - /* Double bit Errors */ - QDMA_S80_HARD_DBE_ERR_MI_H2C0_DAT, - QDMA_S80_HARD_DBE_ERR_MI_C2H0_DAT, - QDMA_S80_HARD_DBE_ERR_H2C_RD_BRG_DAT, - QDMA_S80_HARD_DBE_ERR_H2C_WR_BRG_DAT, - QDMA_S80_HARD_DBE_ERR_C2H_RD_BRG_DAT, - QDMA_S80_HARD_DBE_ERR_C2H_WR_BRG_DAT, - QDMA_S80_HARD_DBE_ERR_FUNC_MAP, - QDMA_S80_HARD_DBE_ERR_DSC_HW_CTXT, - QDMA_S80_HARD_DBE_ERR_DSC_CRD_RCV, - QDMA_S80_HARD_DBE_ERR_DSC_SW_CTXT, - QDMA_S80_HARD_DBE_ERR_DSC_CPLI, - QDMA_S80_HARD_DBE_ERR_DSC_CPLD, - QDMA_S80_HARD_DBE_ERR_PASID_CTXT_RAM, - QDMA_S80_HARD_DBE_ERR_TIMER_FIFO_RAM, - QDMA_S80_HARD_DBE_ERR_PAYLOAD_FIFO_RAM, - QDMA_S80_HARD_DBE_ERR_QID_FIFO_RAM, - QDMA_S80_HARD_DBE_ERR_WRB_COAL_DATA_RAM, - QDMA_S80_HARD_DBE_ERR_INT_QID2VEC_RAM, - QDMA_S80_HARD_DBE_ERR_INT_CTXT_RAM, - QDMA_S80_HARD_DBE_ERR_DESC_REQ_FIFO_RAM, - QDMA_S80_HARD_DBE_ERR_PFCH_CTXT_RAM, - QDMA_S80_HARD_DBE_ERR_WRB_CTXT_RAM, - QDMA_S80_HARD_DBE_ERR_PFCH_LL_RAM, - QDMA_S80_HARD_DBE_ERR_ALL, - - QDMA_S80_HARD_ERRS_ALL -}; - -struct qdma_s80_hard_hw_err_info { - enum qdma_s80_hard_error_idx idx; - const char *err_name; - uint32_t mask_reg_addr; - uint32_t stat_reg_addr; - uint32_t leaf_err_mask; - uint32_t global_err_mask; - void (*qdma_s80_hard_hw_err_process)(void *dev_hndl); -}; - - -int qdma_s80_hard_init_ctxt_memory(void *dev_hndl); - -int qdma_s80_hard_qid2vec_conf(void *dev_hndl, uint8_t c2h, uint16_t hw_qid, - struct qdma_qid2vec *ctxt, - enum qdma_hw_access_type access_type); - -int qdma_s80_hard_fmap_conf(void *dev_hndl, uint16_t func_id, - struct qdma_fmap_cfg *config, - enum qdma_hw_access_type access_type); - -int qdma_s80_hard_sw_ctx_conf(void *dev_hndl, uint8_t c2h, uint16_t hw_qid, - struct qdma_descq_sw_ctxt *ctxt, - enum qdma_hw_access_type access_type); - -int qdma_s80_hard_pfetch_ctx_conf(void *dev_hndl, uint16_t hw_qid, - struct qdma_descq_prefetch_ctxt *ctxt, - enum qdma_hw_access_type access_type); - -int qdma_s80_hard_cmpt_ctx_conf(void *dev_hndl, uint16_t hw_qid, - struct qdma_descq_cmpt_ctxt *ctxt, - enum qdma_hw_access_type access_type); - -int qdma_s80_hard_hw_ctx_conf(void *dev_hndl, uint8_t c2h, uint16_t hw_qid, - struct qdma_descq_hw_ctxt *ctxt, - enum qdma_hw_access_type access_type); - -int qdma_s80_hard_credit_ctx_conf(void *dev_hndl, uint8_t c2h, uint16_t hw_qid, - struct qdma_descq_credit_ctxt *ctxt, - enum qdma_hw_access_type access_type); - -int qdma_s80_hard_indirect_intr_ctx_conf(void *dev_hndl, uint16_t ring_index, - struct qdma_indirect_intr_ctxt *ctxt, - enum qdma_hw_access_type access_type); - -int qdma_s80_hard_set_default_global_csr(void *dev_hndl); - -int qdma_s80_hard_queue_pidx_update(void *dev_hndl, uint8_t is_vf, uint16_t qid, - uint8_t is_c2h, const struct qdma_q_pidx_reg_info *reg_info); - -int qdma_s80_hard_queue_cmpt_cidx_update(void *dev_hndl, uint8_t is_vf, - uint16_t qid, const struct qdma_q_cmpt_cidx_reg_info *reg_info); - -int qdma_s80_hard_queue_intr_cidx_update(void *dev_hndl, uint8_t is_vf, - uint16_t qid, const struct qdma_intr_cidx_reg_info *reg_info); - -int qdma_cmp_get_user_bar(void *dev_hndl, uint8_t is_vf, - uint8_t func_id, uint8_t *user_bar); - -int qdma_s80_hard_get_device_attributes(void *dev_hndl, - struct qdma_dev_attributes *dev_info); - -uint32_t qdma_s80_hard_reg_dump_buf_len(void); - -int qdma_s80_hard_context_buf_len(uint8_t st, - enum qdma_dev_q_type q_type, uint32_t *req_buflen); - -int qdma_s80_hard_dump_config_regs(void *dev_hndl, uint8_t is_vf, - char *buf, uint32_t buflen); - -int qdma_s80_hard_hw_error_process(void *dev_hndl); -const char *qdma_s80_hard_hw_get_error_name(uint32_t err_idx); -int qdma_s80_hard_hw_error_enable(void *dev_hndl, uint32_t err_idx); - -int qdma_s80_hard_dump_queue_context(void *dev_hndl, - uint8_t st, - enum qdma_dev_q_type q_type, - struct qdma_descq_context *ctxt_data, - char *buf, uint32_t buflen); - -int qdma_s80_hard_dump_intr_context(void *dev_hndl, - struct qdma_indirect_intr_ctxt *intr_ctx, - int ring_index, - char *buf, uint32_t buflen); - -int qdma_s80_hard_read_dump_queue_context(void *dev_hndl, - uint16_t qid_hw, - uint8_t st, - enum qdma_dev_q_type q_type, - char *buf, uint32_t buflen); - -int qdma_s80_hard_dump_config_reg_list(void *dev_hndl, - uint32_t total_regs, - struct qdma_reg_data *reg_list, - char *buf, uint32_t buflen); - -int qdma_s80_hard_read_reg_list(void *dev_hndl, uint8_t is_vf, - uint16_t reg_rd_slot, - uint16_t *total_regs, - struct qdma_reg_data *reg_list); - -int qdma_s80_hard_global_csr_conf(void *dev_hndl, uint8_t index, - uint8_t count, - uint32_t *csr_val, - enum qdma_global_csr_type csr_type, - enum qdma_hw_access_type access_type); - -int qdma_s80_hard_global_writeback_interval_conf(void *dev_hndl, - enum qdma_wrb_interval *wb_int, - enum qdma_hw_access_type access_type); - -int qdma_s80_hard_mm_channel_conf(void *dev_hndl, uint8_t channel, - uint8_t is_c2h, - uint8_t enable); - -int qdma_s80_hard_dump_reg_info(void *dev_hndl, uint32_t reg_addr, - uint32_t num_regs, char *buf, uint32_t buflen); - -uint32_t qdma_s80_hard_get_config_num_regs(void); - -struct xreg_info *qdma_s80_hard_get_config_regs(void); - -#ifdef __cplusplus -} -#endif - -#endif /* __QDMA_S80_HARD_ACCESS_H_ */ diff --git a/QDMA/windows/sys/libqdma/source/qdma_access/qdma_s80_hard_access/qdma_s80_hard_reg.h b/QDMA/windows/sys/libqdma/source/qdma_access/qdma_s80_hard_access/qdma_s80_hard_reg.h deleted file mode 100644 index 3e2a5355b..000000000 --- a/QDMA/windows/sys/libqdma/source/qdma_access/qdma_s80_hard_access/qdma_s80_hard_reg.h +++ /dev/null @@ -1,2045 +0,0 @@ -/* - * Copyright (C) 2020 Xilinx, Inc - * - * Licensed under the Apache License, Version 2.0 (the "License"). You may - * not use this file except in compliance with the License. You may obtain - * a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - */ - -#ifndef __QDMA_S80_HARD_REG_H -#define __QDMA_S80_HARD_REG_H - - -#ifdef __cplusplus -extern "C" { -#endif - -#include "qdma_platform.h" - -#ifdef CHAR_BIT -#undef CHAR_BIT -#endif -#define CHAR_BIT 8 - -#ifdef BIT -#undef BIT -#endif -#define BIT(n) (1u << (n)) - -#ifdef BITS_PER_BYTE -#undef BITS_PER_BYTE -#endif -#define BITS_PER_BYTE CHAR_BIT - -#ifdef BITS_PER_LONG -#undef BITS_PER_LONG -#endif -#define BITS_PER_LONG (sizeof(uint32_t) * BITS_PER_BYTE) - -#ifdef BITS_PER_LONG_LONG -#undef BITS_PER_LONG_LONG -#endif -#define BITS_PER_LONG_LONG (sizeof(uint64_t) * BITS_PER_BYTE) - -#ifdef GENMASK -#undef GENMASK -#endif -#define GENMASK(h, l) \ - ((0xFFFFFFFF << (l)) & (0xFFFFFFFF >> (BITS_PER_LONG - 1 - (h)))) - -#ifdef GENMASK_ULL -#undef GENMASK_ULL -#endif -#define GENMASK_ULL(h, l) \ - ((0xFFFFFFFFFFFFFFFF << (l)) & \ - (0xFFFFFFFFFFFFFFFF >> (BITS_PER_LONG_LONG - 1 - (h)))) - -#define DEBGFS_LINE_SZ (81) - -#ifdef ARRAY_SIZE -#undef ARRAY_SIZE -#endif -#define ARRAY_SIZE(arr) (sizeof(arr) / \ - sizeof(arr[0])) - - -uint32_t qdma_s80_hard_config_num_regs_get(void); -struct xreg_info *qdma_s80_hard_config_regs_get(void); -#define QDMA_S80_HARD_CFG_BLK_IDENTIFIER_ADDR 0x00 -#define CFG_BLK_IDENTIFIER_MASK GENMASK(31, 20) -#define CFG_BLK_IDENTIFIER_1_MASK GENMASK(19, 16) -#define CFG_BLK_IDENTIFIER_RSVD_1_MASK GENMASK(15, 8) -#define CFG_BLK_IDENTIFIER_VERSION_MASK GENMASK(7, 0) -#define QDMA_S80_HARD_CFG_BLK_BUSDEV_ADDR 0x04 -#define CFG_BLK_BUSDEV_BDF_MASK GENMASK(15, 0) -#define QDMA_S80_HARD_CFG_BLK_PCIE_MAX_PLD_SIZE_ADDR 0x08 -#define CFG_BLK_PCIE_MAX_PLD_SIZE_MASK GENMASK(2, 0) -#define QDMA_S80_HARD_CFG_BLK_PCIE_MAX_READ_REQ_SIZE_ADDR 0x0C -#define CFG_BLK_PCIE_MAX_READ_REQ_SIZE_MASK GENMASK(2, 0) -#define QDMA_S80_HARD_CFG_BLK_SYSTEM_ID_ADDR 0x10 -#define CFG_BLK_SYSTEM_ID_MASK GENMASK(15, 0) -#define QDMA_S80_HARD_CFG_BLK_MSI_ENABLE_ADDR 0x014 -#define CFG_BLK_MSI_ENABLE_3_MASK BIT(17) -#define CFG_BLK_MSI_ENABLE_MSIX3_MASK BIT(16) -#define CFG_BLK_MSI_ENABLE_2_MASK BIT(13) -#define CFG_BLK_MSI_ENABLE_MSIX2_MASK BIT(12) -#define CFG_BLK_MSI_ENABLE_1_MASK BIT(9) -#define CFG_BLK_MSI_ENABLE_MSIX1_MASK BIT(8) -#define CFG_BLK_MSI_ENABLE_0_MASK BIT(1) -#define CFG_BLK_MSI_ENABLE_MSIX0_MASK BIT(0) -#define QDMA_S80_HARD_CFG_PCIE_DATA_WIDTH_ADDR 0x18 -#define CFG_PCIE_DATA_WIDTH_DATAPATH_MASK GENMASK(2, 0) -#define QDMA_S80_HARD_CFG_PCIE_CTL_ADDR 0x1C -#define CFG_PCIE_CTL_RRQ_DISABLE_MASK BIT(1) -#define CFG_PCIE_CTL_RELAXED_ORDERING_MASK BIT(0) -#define QDMA_S80_HARD_CFG_AXI_USER_MAX_PLD_SIZE_ADDR 0x40 -#define CFG_AXI_USER_MAX_PLD_SIZE_ISSUED_MASK GENMASK(6, 4) -#define CFG_AXI_USER_MAX_PLD_SIZE_PROG_MASK GENMASK(2, 0) -#define QDMA_S80_HARD_CFG_AXI_USER_MAX_READ_REQ_SIZE_ADDR 0x44 -#define CFG_AXI_USER_MAX_READ_REQ_SIZE_USISSUED_MASK GENMASK(6, 4) -#define CFG_AXI_USER_MAX_READ_REQ_SIZE_USPROG_MASK GENMASK(2, 0) -#define QDMA_S80_HARD_CFG_BLK_MISC_CTL_ADDR 0x4C -#define CFG_BLK_MISC_CTL_NUM_TAG_MASK GENMASK(19, 8) -#define CFG_BLK_MISC_CTL_RQ_METERING_MULTIPLIER_MASK GENMASK(4, 0) -#define QDMA_S80_HARD_CFG_BLK_SCRATCH_0_ADDR 0x80 -#define CFG_BLK_SCRATCH_0_MASK GENMASK(31, 0) -#define QDMA_S80_HARD_CFG_BLK_SCRATCH_1_ADDR 0x84 -#define CFG_BLK_SCRATCH_1_MASK GENMASK(31, 0) -#define QDMA_S80_HARD_CFG_BLK_SCRATCH_2_ADDR 0x88 -#define CFG_BLK_SCRATCH_2_MASK GENMASK(31, 0) -#define QDMA_S80_HARD_CFG_BLK_SCRATCH_3_ADDR 0x8C -#define CFG_BLK_SCRATCH_3_MASK GENMASK(31, 0) -#define QDMA_S80_HARD_CFG_BLK_SCRATCH_4_ADDR 0x90 -#define CFG_BLK_SCRATCH_4_MASK GENMASK(31, 0) -#define QDMA_S80_HARD_CFG_BLK_SCRATCH_5_ADDR 0x94 -#define CFG_BLK_SCRATCH_5_MASK GENMASK(31, 0) -#define QDMA_S80_HARD_CFG_BLK_SCRATCH_6_ADDR 0x98 -#define CFG_BLK_SCRATCH_6_MASK GENMASK(31, 0) -#define QDMA_S80_HARD_CFG_BLK_SCRATCH_7_ADDR 0x9C -#define CFG_BLK_SCRATCH_7_MASK GENMASK(31, 0) -#define QDMA_S80_HARD_RAM_SBE_MSK_A_ADDR 0xF0 -#define RAM_SBE_MSK_A_MASK GENMASK(31, 0) -#define QDMA_S80_HARD_RAM_SBE_STS_A_ADDR 0xF4 -#define RAM_SBE_STS_A_RSVD_1_MASK BIT(31) -#define RAM_SBE_STS_A_PFCH_LL_RAM_MASK BIT(30) -#define RAM_SBE_STS_A_WRB_CTXT_RAM_MASK BIT(29) -#define RAM_SBE_STS_A_PFCH_CTXT_RAM_MASK BIT(28) -#define RAM_SBE_STS_A_DESC_REQ_FIFO_RAM_MASK BIT(27) -#define RAM_SBE_STS_A_INT_CTXT_RAM_MASK BIT(26) -#define RAM_SBE_STS_A_INT_QID2VEC_RAM_MASK BIT(25) -#define RAM_SBE_STS_A_WRB_COAL_DATA_RAM_MASK BIT(24) -#define RAM_SBE_STS_A_TUSER_FIFO_RAM_MASK BIT(23) -#define RAM_SBE_STS_A_QID_FIFO_RAM_MASK BIT(22) -#define RAM_SBE_STS_A_PLD_FIFO_RAM_MASK BIT(21) -#define RAM_SBE_STS_A_TIMER_FIFO_RAM_MASK BIT(20) -#define RAM_SBE_STS_A_PASID_CTXT_RAM_MASK BIT(19) -#define RAM_SBE_STS_A_DSC_CPLD_MASK BIT(18) -#define RAM_SBE_STS_A_DSC_CPLI_MASK BIT(17) -#define RAM_SBE_STS_A_DSC_SW_CTXT_MASK BIT(16) -#define RAM_SBE_STS_A_DSC_CRD_RCV_MASK BIT(15) -#define RAM_SBE_STS_A_DSC_HW_CTXT_MASK BIT(14) -#define RAM_SBE_STS_A_FUNC_MAP_MASK BIT(13) -#define RAM_SBE_STS_A_C2H_WR_BRG_DAT_MASK BIT(12) -#define RAM_SBE_STS_A_C2H_RD_BRG_DAT_MASK BIT(11) -#define RAM_SBE_STS_A_H2C_WR_BRG_DAT_MASK BIT(10) -#define RAM_SBE_STS_A_H2C_RD_BRG_DAT_MASK BIT(9) -#define RAM_SBE_STS_A_RSVD_2_MASK GENMASK(8, 5) -#define RAM_SBE_STS_A_MI_C2H0_DAT_MASK BIT(4) -#define RAM_SBE_STS_A_RSVD_3_MASK GENMASK(3, 1) -#define RAM_SBE_STS_A_MI_H2C0_DAT_MASK BIT(0) -#define QDMA_S80_HARD_RAM_DBE_MSK_A_ADDR 0xF8 -#define RAM_DBE_MSK_A_MASK GENMASK(31, 0) -#define QDMA_S80_HARD_RAM_DBE_STS_A_ADDR 0xFC -#define RAM_DBE_STS_A_RSVD_1_MASK BIT(31) -#define RAM_DBE_STS_A_PFCH_LL_RAM_MASK BIT(30) -#define RAM_DBE_STS_A_WRB_CTXT_RAM_MASK BIT(29) -#define RAM_DBE_STS_A_PFCH_CTXT_RAM_MASK BIT(28) -#define RAM_DBE_STS_A_DESC_REQ_FIFO_RAM_MASK BIT(27) -#define RAM_DBE_STS_A_INT_CTXT_RAM_MASK BIT(26) -#define RAM_DBE_STS_A_INT_QID2VEC_RAM_MASK BIT(25) -#define RAM_DBE_STS_A_WRB_COAL_DATA_RAM_MASK BIT(24) -#define RAM_DBE_STS_A_TUSER_FIFO_RAM_MASK BIT(23) -#define RAM_DBE_STS_A_QID_FIFO_RAM_MASK BIT(22) -#define RAM_DBE_STS_A_PLD_FIFO_RAM_MASK BIT(21) -#define RAM_DBE_STS_A_TIMER_FIFO_RAM_MASK BIT(20) -#define RAM_DBE_STS_A_PASID_CTXT_RAM_MASK BIT(19) -#define RAM_DBE_STS_A_DSC_CPLD_MASK BIT(18) -#define RAM_DBE_STS_A_DSC_CPLI_MASK BIT(17) -#define RAM_DBE_STS_A_DSC_SW_CTXT_MASK BIT(16) -#define RAM_DBE_STS_A_DSC_CRD_RCV_MASK BIT(15) -#define RAM_DBE_STS_A_DSC_HW_CTXT_MASK BIT(14) -#define RAM_DBE_STS_A_FUNC_MAP_MASK BIT(13) -#define RAM_DBE_STS_A_C2H_WR_BRG_DAT_MASK BIT(12) -#define RAM_DBE_STS_A_C2H_RD_BRG_DAT_MASK BIT(11) -#define RAM_DBE_STS_A_H2C_WR_BRG_DAT_MASK BIT(10) -#define RAM_DBE_STS_A_H2C_RD_BRG_DAT_MASK BIT(9) -#define RAM_DBE_STS_A_RSVD_2_MASK GENMASK(8, 5) -#define RAM_DBE_STS_A_MI_C2H0_DAT_MASK BIT(4) -#define RAM_DBE_STS_A_RSVD_3_MASK GENMASK(3, 1) -#define RAM_DBE_STS_A_MI_H2C0_DAT_MASK BIT(0) -#define QDMA_S80_HARD_GLBL2_IDENTIFIER_ADDR 0x100 -#define GLBL2_IDENTIFIER_MASK GENMASK(31, 8) -#define GLBL2_IDENTIFIER_VERSION_MASK GENMASK(7, 0) -#define QDMA_S80_HARD_GLBL2_PF_BARLITE_INT_ADDR 0x104 -#define GLBL2_PF_BARLITE_INT_PF3_BAR_MAP_MASK GENMASK(23, 18) -#define GLBL2_PF_BARLITE_INT_PF2_BAR_MAP_MASK GENMASK(17, 12) -#define GLBL2_PF_BARLITE_INT_PF1_BAR_MAP_MASK GENMASK(11, 6) -#define GLBL2_PF_BARLITE_INT_PF0_BAR_MAP_MASK GENMASK(5, 0) -#define QDMA_S80_HARD_GLBL2_PF_VF_BARLITE_INT_ADDR 0x108 -#define GLBL2_PF_VF_BARLITE_INT_PF3_MAP_MASK GENMASK(23, 18) -#define GLBL2_PF_VF_BARLITE_INT_PF2_MAP_MASK GENMASK(17, 12) -#define GLBL2_PF_VF_BARLITE_INT_PF1_MAP_MASK GENMASK(11, 6) -#define GLBL2_PF_VF_BARLITE_INT_PF0_MAP_MASK GENMASK(5, 0) -#define QDMA_S80_HARD_GLBL2_PF_BARLITE_EXT_ADDR 0x10C -#define GLBL2_PF_BARLITE_EXT_PF3_BAR_MAP_MASK GENMASK(23, 18) -#define GLBL2_PF_BARLITE_EXT_PF2_BAR_MAP_MASK GENMASK(17, 12) -#define GLBL2_PF_BARLITE_EXT_PF1_BAR_MAP_MASK GENMASK(11, 6) -#define GLBL2_PF_BARLITE_EXT_PF0_BAR_MAP_MASK GENMASK(5, 0) -#define QDMA_S80_HARD_GLBL2_PF_VF_BARLITE_EXT_ADDR 0x110 -#define GLBL2_PF_VF_BARLITE_EXT_PF3_MAP_MASK GENMASK(23, 18) -#define GLBL2_PF_VF_BARLITE_EXT_PF2_MAP_MASK GENMASK(17, 12) -#define GLBL2_PF_VF_BARLITE_EXT_PF1_MAP_MASK GENMASK(11, 6) -#define GLBL2_PF_VF_BARLITE_EXT_PF0_MAP_MASK GENMASK(5, 0) -#define QDMA_S80_HARD_GLBL2_CHANNEL_INST_ADDR 0x114 -#define GLBL2_CHANNEL_INST_RSVD_1_MASK GENMASK(31, 18) -#define GLBL2_CHANNEL_INST_C2H_ST_MASK BIT(17) -#define GLBL2_CHANNEL_INST_H2C_ST_MASK BIT(16) -#define GLBL2_CHANNEL_INST_RSVD_2_MASK GENMASK(15, 9) -#define GLBL2_CHANNEL_INST_C2H_ENG_MASK BIT(8) -#define GLBL2_CHANNEL_INST_RSVD_3_MASK GENMASK(7, 1) -#define GLBL2_CHANNEL_INST_H2C_ENG_MASK BIT(0) -#define QDMA_S80_HARD_GLBL2_CHANNEL_MDMA_ADDR 0x118 -#define GLBL2_CHANNEL_MDMA_RSVD_1_MASK GENMASK(31, 18) -#define GLBL2_CHANNEL_MDMA_C2H_ST_MASK BIT(17) -#define GLBL2_CHANNEL_MDMA_H2C_ST_MASK BIT(16) -#define GLBL2_CHANNEL_MDMA_RSVD_2_MASK GENMASK(15, 9) -#define GLBL2_CHANNEL_MDMA_C2H_ENG_MASK BIT(8) -#define GLBL2_CHANNEL_MDMA_RSVD_3_MASK GENMASK(7, 1) -#define GLBL2_CHANNEL_MDMA_H2C_ENG_MASK BIT(0) -#define QDMA_S80_HARD_GLBL2_CHANNEL_STRM_ADDR 0x11C -#define GLBL2_CHANNEL_STRM_RSVD_1_MASK GENMASK(31, 18) -#define GLBL2_CHANNEL_STRM_C2H_ST_MASK BIT(17) -#define GLBL2_CHANNEL_STRM_H2C_ST_MASK BIT(16) -#define GLBL2_CHANNEL_STRM_RSVD_2_MASK GENMASK(15, 9) -#define GLBL2_CHANNEL_STRM_C2H_ENG_MASK BIT(8) -#define GLBL2_CHANNEL_STRM_RSVD_3_MASK GENMASK(7, 1) -#define GLBL2_CHANNEL_STRM_H2C_ENG_MASK BIT(0) -#define QDMA_S80_HARD_GLBL2_CHANNEL_CAP_ADDR 0x120 -#define GLBL2_CHANNEL_CAP_RSVD_1_MASK GENMASK(31, 12) -#define GLBL2_CHANNEL_CAP_MULTIQ_MAX_MASK GENMASK(11, 0) -#define QDMA_S80_HARD_GLBL2_CHANNEL_PASID_CAP_ADDR 0x128 -#define GLBL2_CHANNEL_PASID_CAP_RSVD_1_MASK GENMASK(31, 16) -#define GLBL2_CHANNEL_PASID_CAP_BRIDGEOFFSET_MASK GENMASK(15, 4) -#define GLBL2_CHANNEL_PASID_CAP_RSVD_2_MASK GENMASK(3, 2) -#define GLBL2_CHANNEL_PASID_CAP_BRIDGEEN_MASK BIT(1) -#define GLBL2_CHANNEL_PASID_CAP_DMAEN_MASK BIT(0) -#define QDMA_S80_HARD_GLBL2_CHANNEL_FUNC_RET_ADDR 0x12C -#define GLBL2_CHANNEL_FUNC_RET_RSVD_1_MASK GENMASK(31, 8) -#define GLBL2_CHANNEL_FUNC_RET_FUNC_MASK GENMASK(7, 0) -#define QDMA_S80_HARD_GLBL2_SYSTEM_ID_ADDR 0x130 -#define GLBL2_SYSTEM_ID_RSVD_1_MASK GENMASK(31, 16) -#define GLBL2_SYSTEM_ID_MASK GENMASK(15, 0) -#define QDMA_S80_HARD_GLBL2_MISC_CAP_ADDR 0x134 -#define GLBL2_MISC_CAP_RSVD_1_MASK GENMASK(31, 0) -#define QDMA_S80_HARD_GLBL2_DBG_PCIE_RQ0_ADDR 0x1B8 -#define GLBL2_PCIE_RQ0_NPH_AVL_MASK GENMASK(31, 20) -#define GLBL2_PCIE_RQ0_RCB_AVL_MASK GENMASK(19, 10) -#define GLBL2_PCIE_RQ0_SLV_RD_CREDS_MASK GENMASK(9, 4) -#define GLBL2_PCIE_RQ0_TAG_EP_MASK GENMASK(3, 2) -#define GLBL2_PCIE_RQ0_TAG_FL_MASK GENMASK(1, 0) -#define QDMA_S80_HARD_GLBL2_DBG_PCIE_RQ1_ADDR 0x1BC -#define GLBL2_PCIE_RQ1_RSVD_1_MASK GENMASK(31, 17) -#define GLBL2_PCIE_RQ1_WTLP_REQ_MASK BIT(16) -#define GLBL2_PCIE_RQ1_WTLP_HEADER_FIFO_FL_MASK BIT(15) -#define GLBL2_PCIE_RQ1_WTLP_HEADER_FIFO_EP_MASK BIT(14) -#define GLBL2_PCIE_RQ1_RQ_FIFO_EP_MASK BIT(13) -#define GLBL2_PCIE_RQ1_RQ_FIFO_FL_MASK BIT(12) -#define GLBL2_PCIE_RQ1_TLPSM_MASK GENMASK(11, 9) -#define GLBL2_PCIE_RQ1_TLPSM512_MASK GENMASK(8, 6) -#define GLBL2_PCIE_RQ1_RREQ0_RCB_OK_MASK BIT(5) -#define GLBL2_PCIE_RQ1_RREQ0_SLV_MASK BIT(4) -#define GLBL2_PCIE_RQ1_RREQ0_VLD_MASK BIT(3) -#define GLBL2_PCIE_RQ1_RREQ1_RCB_OK_MASK BIT(2) -#define GLBL2_PCIE_RQ1_RREQ1_SLV_MASK BIT(1) -#define GLBL2_PCIE_RQ1_RREQ1_VLD_MASK BIT(0) -#define QDMA_S80_HARD_GLBL2_DBG_AXIMM_WR0_ADDR 0x1C0 -#define GLBL2_AXIMM_WR0_RSVD_1_MASK GENMASK(31, 27) -#define GLBL2_AXIMM_WR0_WR_REQ_MASK BIT(26) -#define GLBL2_AXIMM_WR0_WR_CHN_MASK GENMASK(25, 23) -#define GLBL2_AXIMM_WR0_WTLP_DATA_FIFO_EP_MASK BIT(22) -#define GLBL2_AXIMM_WR0_WPL_FIFO_EP_MASK BIT(21) -#define GLBL2_AXIMM_WR0_BRSP_CLAIM_CHN_MASK GENMASK(20, 18) -#define GLBL2_AXIMM_WR0_WRREQ_CNT_MASK GENMASK(17, 12) -#define GLBL2_AXIMM_WR0_BID_MASK GENMASK(11, 9) -#define GLBL2_AXIMM_WR0_BVALID_MASK BIT(8) -#define GLBL2_AXIMM_WR0_BREADY_MASK BIT(7) -#define GLBL2_AXIMM_WR0_WVALID_MASK BIT(6) -#define GLBL2_AXIMM_WR0_WREADY_MASK BIT(5) -#define GLBL2_AXIMM_WR0_AWID_MASK GENMASK(4, 2) -#define GLBL2_AXIMM_WR0_AWVALID_MASK BIT(1) -#define GLBL2_AXIMM_WR0_AWREADY_MASK BIT(0) -#define QDMA_S80_HARD_GLBL2_DBG_AXIMM_WR1_ADDR 0x1C4 -#define GLBL2_AXIMM_WR1_RSVD_1_MASK GENMASK(31, 30) -#define GLBL2_AXIMM_WR1_BRSP_CNT4_MASK GENMASK(29, 24) -#define GLBL2_AXIMM_WR1_BRSP_CNT3_MASK GENMASK(23, 18) -#define GLBL2_AXIMM_WR1_BRSP_CNT2_MASK GENMASK(17, 12) -#define GLBL2_AXIMM_WR1_BRSP_CNT1_MASK GENMASK(11, 6) -#define GLBL2_AXIMM_WR1_BRSP_CNT0_MASK GENMASK(5, 0) -#define QDMA_S80_HARD_GLBL2_DBG_AXIMM_RD0_ADDR 0x1C8 -#define GLBL2_AXIMM_RD0_RSVD_1_MASK GENMASK(31, 23) -#define GLBL2_AXIMM_RD0_PND_CNT_MASK GENMASK(22, 17) -#define GLBL2_AXIMM_RD0_RD_CHNL_MASK GENMASK(16, 14) -#define GLBL2_AXIMM_RD0_RD_REQ_MASK BIT(13) -#define GLBL2_AXIMM_RD0_RRSP_CLAIM_CHNL_MASK GENMASK(12, 10) -#define GLBL2_AXIMM_RD0_RID_MASK GENMASK(9, 7) -#define GLBL2_AXIMM_RD0_RVALID_MASK BIT(6) -#define GLBL2_AXIMM_RD0_RREADY_MASK BIT(5) -#define GLBL2_AXIMM_RD0_ARID_MASK GENMASK(4, 2) -#define GLBL2_AXIMM_RD0_ARVALID_MASK BIT(1) -#define GLBL2_AXIMM_RD0_ARREADY_MASK BIT(0) -#define QDMA_S80_HARD_GLBL2_DBG_AXIMM_RD1_ADDR 0x1CC -#define GLBL2_AXIMM_RD1_RSVD_1_MASK GENMASK(31, 30) -#define GLBL2_AXIMM_RD1_RRSP_CNT4_MASK GENMASK(29, 24) -#define GLBL2_AXIMM_RD1_RRSP_CNT3_MASK GENMASK(23, 18) -#define GLBL2_AXIMM_RD1_RRSP_CNT2_MASK GENMASK(17, 12) -#define GLBL2_AXIMM_RD1_RRSP_CNT1_MASK GENMASK(11, 6) -#define GLBL2_AXIMM_RD1_RRSP_CNT0_MASK GENMASK(5, 0) -#define QDMA_S80_HARD_GLBL_RNG_SZ_1_ADDR 0x204 -#define GLBL_RNG_SZ_1_RSVD_1_MASK GENMASK(31, 16) -#define GLBL_RNG_SZ_1_RING_SIZE_MASK GENMASK(15, 0) -#define QDMA_S80_HARD_GLBL_RNG_SZ_2_ADDR 0x208 -#define GLBL_RNG_SZ_2_RSVD_1_MASK GENMASK(31, 16) -#define GLBL_RNG_SZ_2_RING_SIZE_MASK GENMASK(15, 0) -#define QDMA_S80_HARD_GLBL_RNG_SZ_3_ADDR 0x20C -#define GLBL_RNG_SZ_3_RSVD_1_MASK GENMASK(31, 16) -#define GLBL_RNG_SZ_3_RING_SIZE_MASK GENMASK(15, 0) -#define QDMA_S80_HARD_GLBL_RNG_SZ_4_ADDR 0x210 -#define GLBL_RNG_SZ_4_RSVD_1_MASK GENMASK(31, 16) -#define GLBL_RNG_SZ_4_RING_SIZE_MASK GENMASK(15, 0) -#define QDMA_S80_HARD_GLBL_RNG_SZ_5_ADDR 0x214 -#define GLBL_RNG_SZ_5_RSVD_1_MASK GENMASK(31, 16) -#define GLBL_RNG_SZ_5_RING_SIZE_MASK GENMASK(15, 0) -#define QDMA_S80_HARD_GLBL_RNG_SZ_6_ADDR 0x218 -#define GLBL_RNG_SZ_6_RSVD_1_MASK GENMASK(31, 16) -#define GLBL_RNG_SZ_6_RING_SIZE_MASK GENMASK(15, 0) -#define QDMA_S80_HARD_GLBL_RNG_SZ_7_ADDR 0x21C -#define GLBL_RNG_SZ_7_RSVD_1_MASK GENMASK(31, 16) -#define GLBL_RNG_SZ_7_RING_SIZE_MASK GENMASK(15, 0) -#define QDMA_S80_HARD_GLBL_RNG_SZ_8_ADDR 0x220 -#define GLBL_RNG_SZ_8_RSVD_1_MASK GENMASK(31, 16) -#define GLBL_RNG_SZ_8_RING_SIZE_MASK GENMASK(15, 0) -#define QDMA_S80_HARD_GLBL_RNG_SZ_9_ADDR 0x224 -#define GLBL_RNG_SZ_9_RSVD_1_MASK GENMASK(31, 16) -#define GLBL_RNG_SZ_9_RING_SIZE_MASK GENMASK(15, 0) -#define QDMA_S80_HARD_GLBL_RNG_SZ_A_ADDR 0x228 -#define GLBL_RNG_SZ_A_RSVD_1_MASK GENMASK(31, 16) -#define GLBL_RNG_SZ_A_RING_SIZE_MASK GENMASK(15, 0) -#define QDMA_S80_HARD_GLBL_RNG_SZ_B_ADDR 0x22C -#define GLBL_RNG_SZ_B_RSVD_1_MASK GENMASK(31, 16) -#define GLBL_RNG_SZ_B_RING_SIZE_MASK GENMASK(15, 0) -#define QDMA_S80_HARD_GLBL_RNG_SZ_C_ADDR 0x230 -#define GLBL_RNG_SZ_C_RSVD_1_MASK GENMASK(31, 16) -#define GLBL_RNG_SZ_C_RING_SIZE_MASK GENMASK(15, 0) -#define QDMA_S80_HARD_GLBL_RNG_SZ_D_ADDR 0x234 -#define GLBL_RNG_SZ_D_RSVD_1_MASK GENMASK(31, 16) -#define GLBL_RNG_SZ_D_RING_SIZE_MASK GENMASK(15, 0) -#define QDMA_S80_HARD_GLBL_RNG_SZ_E_ADDR 0x238 -#define GLBL_RNG_SZ_E_RSVD_1_MASK GENMASK(31, 16) -#define GLBL_RNG_SZ_E_RING_SIZE_MASK GENMASK(15, 0) -#define QDMA_S80_HARD_GLBL_RNG_SZ_F_ADDR 0x23C -#define GLBL_RNG_SZ_F_RSVD_1_MASK GENMASK(31, 16) -#define GLBL_RNG_SZ_F_RING_SIZE_MASK GENMASK(15, 0) -#define QDMA_S80_HARD_GLBL_RNG_SZ_10_ADDR 0x240 -#define GLBL_RNG_SZ_10_RSVD_1_MASK GENMASK(31, 16) -#define GLBL_RNG_SZ_10_RING_SIZE_MASK GENMASK(15, 0) -#define QDMA_S80_HARD_GLBL_ERR_STAT_ADDR 0x248 -#define GLBL_ERR_STAT_RSVD_1_MASK GENMASK(31, 12) -#define GLBL_ERR_STAT_ERR_H2C_ST_MASK BIT(11) -#define GLBL_ERR_STAT_ERR_BDG_MASK BIT(10) -#define GLBL_ERR_STAT_IND_CTXT_CMD_ERR_MASK BIT(9) -#define GLBL_ERR_STAT_ERR_C2H_ST_MASK BIT(8) -#define GLBL_ERR_STAT_ERR_C2H_MM_1_MASK BIT(7) -#define GLBL_ERR_STAT_ERR_C2H_MM_0_MASK BIT(6) -#define GLBL_ERR_STAT_ERR_H2C_MM_1_MASK BIT(5) -#define GLBL_ERR_STAT_ERR_H2C_MM_0_MASK BIT(4) -#define GLBL_ERR_STAT_ERR_TRQ_MASK BIT(3) -#define GLBL_ERR_STAT_ERR_DSC_MASK BIT(2) -#define GLBL_ERR_STAT_ERR_RAM_DBE_MASK BIT(1) -#define GLBL_ERR_STAT_ERR_RAM_SBE_MASK BIT(0) -#define QDMA_S80_HARD_GLBL_ERR_MASK_ADDR 0x24C -#define GLBL_ERR_RSVD_1_MASK GENMASK(31, 9) -#define GLBL_ERR_MASK GENMASK(8, 0) -#define QDMA_S80_HARD_GLBL_DSC_CFG_ADDR 0x250 -#define GLBL_DSC_CFG_RSVD_1_MASK GENMASK(31, 10) -#define GLBL_DSC_CFG_UNC_OVR_COR_MASK BIT(9) -#define GLBL_DSC_CFG_CTXT_FER_DIS_MASK BIT(8) -#define GLBL_DSC_CFG_RSVD_2_MASK GENMASK(7, 6) -#define GLBL_DSC_CFG_MAXFETCH_MASK GENMASK(5, 3) -#define GLBL_DSC_CFG_WB_ACC_INT_MASK GENMASK(2, 0) -#define QDMA_S80_HARD_GLBL_DSC_ERR_STS_ADDR 0x254 -#define GLBL_DSC_ERR_STS_RSVD_1_MASK GENMASK(31, 25) -#define GLBL_DSC_ERR_STS_SBE_MASK BIT(24) -#define GLBL_DSC_ERR_STS_DBE_MASK BIT(23) -#define GLBL_DSC_ERR_STS_RQ_CANCEL_MASK BIT(22) -#define GLBL_DSC_ERR_STS_DSC_MASK BIT(21) -#define GLBL_DSC_ERR_STS_DMA_MASK BIT(20) -#define GLBL_DSC_ERR_STS_FLR_CANCEL_MASK BIT(19) -#define GLBL_DSC_ERR_STS_RSVD_2_MASK GENMASK(18, 17) -#define GLBL_DSC_ERR_STS_DAT_POISON_MASK BIT(16) -#define GLBL_DSC_ERR_STS_TIMEOUT_MASK BIT(9) -#define GLBL_DSC_ERR_STS_FLR_MASK BIT(5) -#define GLBL_DSC_ERR_STS_TAG_MASK BIT(4) -#define GLBL_DSC_ERR_STS_ADDR_MASK BIT(3) -#define GLBL_DSC_ERR_STS_PARAM_MASK BIT(2) -#define GLBL_DSC_ERR_STS_UR_CA_MASK BIT(1) -#define GLBL_DSC_ERR_STS_POISON_MASK BIT(0) -#define QDMA_S80_HARD_GLBL_DSC_ERR_MSK_ADDR 0x258 -#define GLBL_DSC_ERR_MSK_MASK GENMASK(8, 0) -#define QDMA_S80_HARD_GLBL_DSC_ERR_LOG0_ADDR 0x25C -#define GLBL_DSC_ERR_LOG0_VALID_MASK BIT(31) -#define GLBL_DSC_ERR_LOG0_RSVD_1_MASK GENMASK(30, 29) -#define GLBL_DSC_ERR_LOG0_QID_MASK GENMASK(28, 17) -#define GLBL_DSC_ERR_LOG0_SEL_MASK BIT(16) -#define GLBL_DSC_ERR_LOG0_CIDX_MASK GENMASK(15, 0) -#define QDMA_S80_HARD_GLBL_DSC_ERR_LOG1_ADDR 0x260 -#define GLBL_DSC_ERR_LOG1_RSVD_1_MASK GENMASK(31, 9) -#define GLBL_DSC_ERR_LOG1_SUB_TYPE_MASK GENMASK(8, 5) -#define GLBL_DSC_ERR_LOG1_ERR_TYPE_MASK GENMASK(4, 0) -#define QDMA_S80_HARD_GLBL_TRQ_ERR_STS_ADDR 0x264 -#define GLBL_TRQ_ERR_STS_RSVD_1_MASK GENMASK(31, 4) -#define GLBL_TRQ_ERR_STS_TCP_TIMEOUT_MASK BIT(3) -#define GLBL_TRQ_ERR_STS_VF_ACCESS_ERR_MASK BIT(2) -#define GLBL_TRQ_ERR_STS_QID_RANGE_MASK BIT(1) -#define GLBL_TRQ_ERR_STS_UNMAPPED_MASK BIT(0) -#define QDMA_S80_HARD_GLBL_TRQ_ERR_MSK_ADDR 0x268 -#define GLBL_TRQ_ERR_MSK_MASK GENMASK(31, 0) -#define QDMA_S80_HARD_GLBL_TRQ_ERR_LOG_ADDR 0x26C -#define GLBL_TRQ_ERR_LOG_RSVD_1_MASK GENMASK(31, 28) -#define GLBL_TRQ_ERR_LOG_TARGET_MASK GENMASK(27, 24) -#define GLBL_TRQ_ERR_LOG_FUNC_MASK GENMASK(23, 16) -#define GLBL_TRQ_ERR_LOG_ADDRESS_MASK GENMASK(15, 0) -#define QDMA_S80_HARD_GLBL_DSC_DBG_DAT0_ADDR 0x270 -#define GLBL_DSC_DAT0_RSVD_1_MASK GENMASK(31, 30) -#define GLBL_DSC_DAT0_CTXT_ARB_DIR_MASK BIT(29) -#define GLBL_DSC_DAT0_CTXT_ARB_QID_MASK GENMASK(28, 17) -#define GLBL_DSC_DAT0_CTXT_ARB_REQ_MASK GENMASK(16, 12) -#define GLBL_DSC_DAT0_IRQ_FIFO_FL_MASK BIT(11) -#define GLBL_DSC_DAT0_TMSTALL_MASK BIT(10) -#define GLBL_DSC_DAT0_RRQ_STALL_MASK GENMASK(9, 8) -#define GLBL_DSC_DAT0_RCP_FIFO_SPC_STALL_MASK GENMASK(7, 6) -#define GLBL_DSC_DAT0_RRQ_FIFO_SPC_STALL_MASK GENMASK(5, 4) -#define GLBL_DSC_DAT0_FAB_MRKR_RSP_STALL_MASK GENMASK(3, 2) -#define GLBL_DSC_DAT0_DSC_OUT_STALL_MASK GENMASK(1, 0) -#define QDMA_S80_HARD_GLBL_DSC_DBG_DAT1_ADDR 0x274 -#define GLBL_DSC_DAT1_RSVD_1_MASK GENMASK(31, 28) -#define GLBL_DSC_DAT1_EVT_SPC_C2H_MASK GENMASK(27, 22) -#define GLBL_DSC_DAT1_EVT_SP_H2C_MASK GENMASK(21, 16) -#define GLBL_DSC_DAT1_DSC_SPC_C2H_MASK GENMASK(15, 8) -#define GLBL_DSC_DAT1_DSC_SPC_H2C_MASK GENMASK(7, 0) -#define QDMA_S80_HARD_TRQ_SEL_FMAP_0_ADDR 0x400 -#define TRQ_SEL_FMAP_0_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_0_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_0_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_S80_HARD_TRQ_SEL_FMAP_1_ADDR 0x404 -#define TRQ_SEL_FMAP_1_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_1_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_1_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_S80_HARD_TRQ_SEL_FMAP_2_ADDR 0x408 -#define TRQ_SEL_FMAP_2_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_2_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_2_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_S80_HARD_TRQ_SEL_FMAP_3_ADDR 0x40C -#define TRQ_SEL_FMAP_3_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_3_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_3_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_S80_HARD_TRQ_SEL_FMAP_4_ADDR 0x410 -#define TRQ_SEL_FMAP_4_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_4_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_4_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_S80_HARD_TRQ_SEL_FMAP_5_ADDR 0x414 -#define TRQ_SEL_FMAP_5_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_5_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_5_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_S80_HARD_TRQ_SEL_FMAP_6_ADDR 0x418 -#define TRQ_SEL_FMAP_6_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_6_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_6_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_S80_HARD_TRQ_SEL_FMAP_7_ADDR 0x41C -#define TRQ_SEL_FMAP_7_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_7_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_7_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_S80_HARD_TRQ_SEL_FMAP_8_ADDR 0x420 -#define TRQ_SEL_FMAP_8_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_8_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_8_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_S80_HARD_TRQ_SEL_FMAP_9_ADDR 0x424 -#define TRQ_SEL_FMAP_9_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_9_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_9_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_S80_HARD_TRQ_SEL_FMAP_A_ADDR 0x428 -#define TRQ_SEL_FMAP_A_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_A_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_A_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_S80_HARD_TRQ_SEL_FMAP_B_ADDR 0x42C -#define TRQ_SEL_FMAP_B_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_B_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_B_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_S80_HARD_TRQ_SEL_FMAP_D_ADDR 0x430 -#define TRQ_SEL_FMAP_D_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_D_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_D_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_S80_HARD_TRQ_SEL_FMAP_E_ADDR 0x434 -#define TRQ_SEL_FMAP_E_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_E_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_E_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_S80_HARD_TRQ_SEL_FMAP_F_ADDR 0x438 -#define TRQ_SEL_FMAP_F_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_F_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_F_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_S80_HARD_TRQ_SEL_FMAP_10_ADDR 0x43C -#define TRQ_SEL_FMAP_10_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_10_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_10_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_S80_HARD_TRQ_SEL_FMAP_11_ADDR 0x440 -#define TRQ_SEL_FMAP_11_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_11_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_11_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_S80_HARD_TRQ_SEL_FMAP_12_ADDR 0x444 -#define TRQ_SEL_FMAP_12_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_12_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_12_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_S80_HARD_TRQ_SEL_FMAP_13_ADDR 0x448 -#define TRQ_SEL_FMAP_13_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_13_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_13_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_S80_HARD_TRQ_SEL_FMAP_14_ADDR 0x44C -#define TRQ_SEL_FMAP_14_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_14_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_14_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_S80_HARD_TRQ_SEL_FMAP_15_ADDR 0x450 -#define TRQ_SEL_FMAP_15_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_15_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_15_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_S80_HARD_TRQ_SEL_FMAP_16_ADDR 0x454 -#define TRQ_SEL_FMAP_16_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_16_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_16_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_S80_HARD_TRQ_SEL_FMAP_17_ADDR 0x458 -#define TRQ_SEL_FMAP_17_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_17_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_17_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_S80_HARD_TRQ_SEL_FMAP_18_ADDR 0x45C -#define TRQ_SEL_FMAP_18_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_18_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_18_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_S80_HARD_TRQ_SEL_FMAP_19_ADDR 0x460 -#define TRQ_SEL_FMAP_19_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_19_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_19_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_S80_HARD_TRQ_SEL_FMAP_1A_ADDR 0x464 -#define TRQ_SEL_FMAP_1A_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_1A_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_1A_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_S80_HARD_TRQ_SEL_FMAP_1B_ADDR 0x468 -#define TRQ_SEL_FMAP_1B_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_1B_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_1B_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_S80_HARD_TRQ_SEL_FMAP_1C_ADDR 0x46C -#define TRQ_SEL_FMAP_1C_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_1C_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_1C_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_S80_HARD_TRQ_SEL_FMAP_1D_ADDR 0x470 -#define TRQ_SEL_FMAP_1D_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_1D_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_1D_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_S80_HARD_TRQ_SEL_FMAP_1E_ADDR 0x474 -#define TRQ_SEL_FMAP_1E_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_1E_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_1E_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_S80_HARD_TRQ_SEL_FMAP_1F_ADDR 0x478 -#define TRQ_SEL_FMAP_1F_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_1F_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_1F_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_S80_HARD_TRQ_SEL_FMAP_20_ADDR 0x47C -#define TRQ_SEL_FMAP_20_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_20_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_20_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_S80_HARD_TRQ_SEL_FMAP_21_ADDR 0x480 -#define TRQ_SEL_FMAP_21_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_21_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_21_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_S80_HARD_TRQ_SEL_FMAP_22_ADDR 0x484 -#define TRQ_SEL_FMAP_22_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_22_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_22_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_S80_HARD_TRQ_SEL_FMAP_23_ADDR 0x488 -#define TRQ_SEL_FMAP_23_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_23_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_23_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_S80_HARD_TRQ_SEL_FMAP_24_ADDR 0x48C -#define TRQ_SEL_FMAP_24_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_24_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_24_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_S80_HARD_TRQ_SEL_FMAP_25_ADDR 0x490 -#define TRQ_SEL_FMAP_25_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_25_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_25_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_S80_HARD_TRQ_SEL_FMAP_26_ADDR 0x494 -#define TRQ_SEL_FMAP_26_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_26_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_26_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_S80_HARD_TRQ_SEL_FMAP_27_ADDR 0x498 -#define TRQ_SEL_FMAP_27_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_27_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_27_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_S80_HARD_TRQ_SEL_FMAP_28_ADDR 0x49C -#define TRQ_SEL_FMAP_28_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_28_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_28_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_S80_HARD_TRQ_SEL_FMAP_29_ADDR 0x4A0 -#define TRQ_SEL_FMAP_29_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_29_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_29_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_S80_HARD_TRQ_SEL_FMAP_2A_ADDR 0x4A4 -#define TRQ_SEL_FMAP_2A_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_2A_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_2A_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_S80_HARD_TRQ_SEL_FMAP_2B_ADDR 0x4A8 -#define TRQ_SEL_FMAP_2B_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_2B_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_2B_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_S80_HARD_TRQ_SEL_FMAP_2C_ADDR 0x4AC -#define TRQ_SEL_FMAP_2C_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_2C_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_2C_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_S80_HARD_TRQ_SEL_FMAP_2D_ADDR 0x4B0 -#define TRQ_SEL_FMAP_2D_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_2D_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_2D_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_S80_HARD_TRQ_SEL_FMAP_2E_ADDR 0x4B4 -#define TRQ_SEL_FMAP_2E_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_2E_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_2E_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_S80_HARD_TRQ_SEL_FMAP_2F_ADDR 0x4B8 -#define TRQ_SEL_FMAP_2F_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_2F_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_2F_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_S80_HARD_TRQ_SEL_FMAP_30_ADDR 0x4BC -#define TRQ_SEL_FMAP_30_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_30_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_30_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_S80_HARD_TRQ_SEL_FMAP_31_ADDR 0x4D0 -#define TRQ_SEL_FMAP_31_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_31_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_31_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_S80_HARD_TRQ_SEL_FMAP_32_ADDR 0x4D4 -#define TRQ_SEL_FMAP_32_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_32_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_32_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_S80_HARD_TRQ_SEL_FMAP_33_ADDR 0x4D8 -#define TRQ_SEL_FMAP_33_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_33_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_33_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_S80_HARD_TRQ_SEL_FMAP_34_ADDR 0x4DC -#define TRQ_SEL_FMAP_34_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_34_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_34_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_S80_HARD_TRQ_SEL_FMAP_35_ADDR 0x4E0 -#define TRQ_SEL_FMAP_35_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_35_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_35_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_S80_HARD_TRQ_SEL_FMAP_36_ADDR 0x4E4 -#define TRQ_SEL_FMAP_36_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_36_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_36_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_S80_HARD_TRQ_SEL_FMAP_37_ADDR 0x4E8 -#define TRQ_SEL_FMAP_37_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_37_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_37_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_S80_HARD_TRQ_SEL_FMAP_38_ADDR 0x4EC -#define TRQ_SEL_FMAP_38_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_38_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_38_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_S80_HARD_TRQ_SEL_FMAP_39_ADDR 0x4F0 -#define TRQ_SEL_FMAP_39_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_39_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_39_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_S80_HARD_TRQ_SEL_FMAP_3A_ADDR 0x4F4 -#define TRQ_SEL_FMAP_3A_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_3A_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_3A_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_S80_HARD_TRQ_SEL_FMAP_3B_ADDR 0x4F8 -#define TRQ_SEL_FMAP_3B_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_3B_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_3B_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_S80_HARD_TRQ_SEL_FMAP_3C_ADDR 0x4FC -#define TRQ_SEL_FMAP_3C_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_3C_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_3C_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_S80_HARD_TRQ_SEL_FMAP_3D_ADDR 0x500 -#define TRQ_SEL_FMAP_3D_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_3D_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_3D_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_S80_HARD_TRQ_SEL_FMAP_3E_ADDR 0x504 -#define TRQ_SEL_FMAP_3E_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_3E_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_3E_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_S80_HARD_TRQ_SEL_FMAP_3F_ADDR 0x508 -#define TRQ_SEL_FMAP_3F_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_3F_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_3F_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_S80_HARD_TRQ_SEL_FMAP_40_ADDR 0x50C -#define TRQ_SEL_FMAP_40_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_40_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_40_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_S80_HARD_TRQ_SEL_FMAP_41_ADDR 0x510 -#define TRQ_SEL_FMAP_41_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_41_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_41_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_S80_HARD_TRQ_SEL_FMAP_42_ADDR 0x514 -#define TRQ_SEL_FMAP_42_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_42_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_42_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_S80_HARD_TRQ_SEL_FMAP_43_ADDR 0x518 -#define TRQ_SEL_FMAP_43_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_43_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_43_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_S80_HARD_TRQ_SEL_FMAP_44_ADDR 0x51C -#define TRQ_SEL_FMAP_44_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_44_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_44_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_S80_HARD_TRQ_SEL_FMAP_45_ADDR 0x520 -#define TRQ_SEL_FMAP_45_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_45_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_45_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_S80_HARD_TRQ_SEL_FMAP_46_ADDR 0x524 -#define TRQ_SEL_FMAP_46_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_46_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_46_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_S80_HARD_TRQ_SEL_FMAP_47_ADDR 0x528 -#define TRQ_SEL_FMAP_47_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_47_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_47_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_S80_HARD_TRQ_SEL_FMAP_48_ADDR 0x52C -#define TRQ_SEL_FMAP_48_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_48_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_48_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_S80_HARD_TRQ_SEL_FMAP_49_ADDR 0x530 -#define TRQ_SEL_FMAP_49_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_49_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_49_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_S80_HARD_TRQ_SEL_FMAP_4A_ADDR 0x534 -#define TRQ_SEL_FMAP_4A_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_4A_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_4A_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_S80_HARD_TRQ_SEL_FMAP_4B_ADDR 0x538 -#define TRQ_SEL_FMAP_4B_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_4B_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_4B_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_S80_HARD_TRQ_SEL_FMAP_4C_ADDR 0x53C -#define TRQ_SEL_FMAP_4C_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_4C_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_4C_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_S80_HARD_TRQ_SEL_FMAP_4D_ADDR 0x540 -#define TRQ_SEL_FMAP_4D_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_4D_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_4D_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_S80_HARD_TRQ_SEL_FMAP_4E_ADDR 0x544 -#define TRQ_SEL_FMAP_4E_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_4E_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_4E_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_S80_HARD_TRQ_SEL_FMAP_4F_ADDR 0x548 -#define TRQ_SEL_FMAP_4F_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_4F_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_4F_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_S80_HARD_TRQ_SEL_FMAP_50_ADDR 0x54C -#define TRQ_SEL_FMAP_50_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_50_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_50_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_S80_HARD_TRQ_SEL_FMAP_51_ADDR 0x550 -#define TRQ_SEL_FMAP_51_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_51_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_51_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_S80_HARD_TRQ_SEL_FMAP_52_ADDR 0x554 -#define TRQ_SEL_FMAP_52_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_52_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_52_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_S80_HARD_TRQ_SEL_FMAP_53_ADDR 0x558 -#define TRQ_SEL_FMAP_53_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_53_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_53_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_S80_HARD_TRQ_SEL_FMAP_54_ADDR 0x55C -#define TRQ_SEL_FMAP_54_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_54_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_54_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_S80_HARD_TRQ_SEL_FMAP_55_ADDR 0x560 -#define TRQ_SEL_FMAP_55_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_55_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_55_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_S80_HARD_TRQ_SEL_FMAP_56_ADDR 0x564 -#define TRQ_SEL_FMAP_56_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_56_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_56_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_S80_HARD_TRQ_SEL_FMAP_57_ADDR 0x568 -#define TRQ_SEL_FMAP_57_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_57_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_57_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_S80_HARD_TRQ_SEL_FMAP_58_ADDR 0x56C -#define TRQ_SEL_FMAP_58_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_58_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_58_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_S80_HARD_TRQ_SEL_FMAP_59_ADDR 0x570 -#define TRQ_SEL_FMAP_59_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_59_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_59_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_S80_HARD_TRQ_SEL_FMAP_5A_ADDR 0x574 -#define TRQ_SEL_FMAP_5A_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_5A_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_5A_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_S80_HARD_TRQ_SEL_FMAP_5B_ADDR 0x578 -#define TRQ_SEL_FMAP_5B_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_5B_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_5B_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_S80_HARD_TRQ_SEL_FMAP_5C_ADDR 0x57C -#define TRQ_SEL_FMAP_5C_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_5C_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_5C_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_S80_HARD_TRQ_SEL_FMAP_5D_ADDR 0x580 -#define TRQ_SEL_FMAP_5D_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_5D_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_5D_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_S80_HARD_TRQ_SEL_FMAP_5E_ADDR 0x584 -#define TRQ_SEL_FMAP_5E_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_5E_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_5E_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_S80_HARD_TRQ_SEL_FMAP_5F_ADDR 0x588 -#define TRQ_SEL_FMAP_5F_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_5F_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_5F_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_S80_HARD_TRQ_SEL_FMAP_60_ADDR 0x58C -#define TRQ_SEL_FMAP_60_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_60_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_60_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_S80_HARD_TRQ_SEL_FMAP_61_ADDR 0x590 -#define TRQ_SEL_FMAP_61_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_61_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_61_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_S80_HARD_TRQ_SEL_FMAP_62_ADDR 0x594 -#define TRQ_SEL_FMAP_62_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_62_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_62_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_S80_HARD_TRQ_SEL_FMAP_63_ADDR 0x598 -#define TRQ_SEL_FMAP_63_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_63_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_63_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_S80_HARD_TRQ_SEL_FMAP_64_ADDR 0x59C -#define TRQ_SEL_FMAP_64_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_64_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_64_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_S80_HARD_TRQ_SEL_FMAP_65_ADDR 0x5A0 -#define TRQ_SEL_FMAP_65_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_65_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_65_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_S80_HARD_TRQ_SEL_FMAP_66_ADDR 0x5A4 -#define TRQ_SEL_FMAP_66_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_66_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_66_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_S80_HARD_TRQ_SEL_FMAP_67_ADDR 0x5A8 -#define TRQ_SEL_FMAP_67_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_67_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_67_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_S80_HARD_TRQ_SEL_FMAP_68_ADDR 0x5AC -#define TRQ_SEL_FMAP_68_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_68_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_68_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_S80_HARD_TRQ_SEL_FMAP_69_ADDR 0x5B0 -#define TRQ_SEL_FMAP_69_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_69_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_69_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_S80_HARD_TRQ_SEL_FMAP_6A_ADDR 0x5B4 -#define TRQ_SEL_FMAP_6A_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_6A_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_6A_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_S80_HARD_TRQ_SEL_FMAP_6B_ADDR 0x5B8 -#define TRQ_SEL_FMAP_6B_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_6B_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_6B_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_S80_HARD_TRQ_SEL_FMAP_6C_ADDR 0x5BC -#define TRQ_SEL_FMAP_6C_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_6C_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_6C_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_S80_HARD_TRQ_SEL_FMAP_6D_ADDR 0x5C0 -#define TRQ_SEL_FMAP_6D_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_6D_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_6D_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_S80_HARD_TRQ_SEL_FMAP_6E_ADDR 0x5C4 -#define TRQ_SEL_FMAP_6E_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_6E_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_6E_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_S80_HARD_TRQ_SEL_FMAP_6F_ADDR 0x5C8 -#define TRQ_SEL_FMAP_6F_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_6F_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_6F_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_S80_HARD_TRQ_SEL_FMAP_70_ADDR 0x5CC -#define TRQ_SEL_FMAP_70_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_70_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_70_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_S80_HARD_TRQ_SEL_FMAP_71_ADDR 0x5D0 -#define TRQ_SEL_FMAP_71_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_71_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_71_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_S80_HARD_TRQ_SEL_FMAP_72_ADDR 0x5D4 -#define TRQ_SEL_FMAP_72_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_72_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_72_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_S80_HARD_TRQ_SEL_FMAP_73_ADDR 0x5D8 -#define TRQ_SEL_FMAP_73_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_73_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_73_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_S80_HARD_TRQ_SEL_FMAP_74_ADDR 0x5DC -#define TRQ_SEL_FMAP_74_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_74_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_74_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_S80_HARD_TRQ_SEL_FMAP_75_ADDR 0x5E0 -#define TRQ_SEL_FMAP_75_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_75_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_75_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_S80_HARD_TRQ_SEL_FMAP_76_ADDR 0x5E4 -#define TRQ_SEL_FMAP_76_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_76_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_76_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_S80_HARD_TRQ_SEL_FMAP_77_ADDR 0x5E8 -#define TRQ_SEL_FMAP_77_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_77_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_77_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_S80_HARD_TRQ_SEL_FMAP_78_ADDR 0x5EC -#define TRQ_SEL_FMAP_78_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_78_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_78_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_S80_HARD_TRQ_SEL_FMAP_79_ADDR 0x5F0 -#define TRQ_SEL_FMAP_79_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_79_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_79_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_S80_HARD_TRQ_SEL_FMAP_7A_ADDR 0x5F4 -#define TRQ_SEL_FMAP_7A_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_7A_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_7A_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_S80_HARD_TRQ_SEL_FMAP_7B_ADDR 0x5F8 -#define TRQ_SEL_FMAP_7B_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_7B_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_7B_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_S80_HARD_TRQ_SEL_FMAP_7C_ADDR 0x5FC -#define TRQ_SEL_FMAP_7C_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_7C_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_7C_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_S80_HARD_TRQ_SEL_FMAP_7D_ADDR 0x600 -#define TRQ_SEL_FMAP_7D_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_7D_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_7D_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_S80_HARD_TRQ_SEL_FMAP_7E_ADDR 0x604 -#define TRQ_SEL_FMAP_7E_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_7E_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_7E_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_S80_HARD_TRQ_SEL_FMAP_7F_ADDR 0x608 -#define TRQ_SEL_FMAP_7F_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_7F_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_7F_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_S80_HARD_TRQ_SEL_FMAP_80_ADDR 0x60C -#define TRQ_SEL_FMAP_80_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_80_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_80_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_S80_HARD_TRQ_SEL_FMAP_81_ADDR 0x610 -#define TRQ_SEL_FMAP_81_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_81_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_81_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_S80_HARD_TRQ_SEL_FMAP_82_ADDR 0x614 -#define TRQ_SEL_FMAP_82_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_82_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_82_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_S80_HARD_TRQ_SEL_FMAP_83_ADDR 0x618 -#define TRQ_SEL_FMAP_83_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_83_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_83_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_S80_HARD_TRQ_SEL_FMAP_84_ADDR 0x61C -#define TRQ_SEL_FMAP_84_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_84_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_84_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_S80_HARD_TRQ_SEL_FMAP_85_ADDR 0x620 -#define TRQ_SEL_FMAP_85_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_85_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_85_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_S80_HARD_TRQ_SEL_FMAP_86_ADDR 0x624 -#define TRQ_SEL_FMAP_86_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_86_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_86_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_S80_HARD_TRQ_SEL_FMAP_87_ADDR 0x628 -#define TRQ_SEL_FMAP_87_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_87_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_87_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_S80_HARD_TRQ_SEL_FMAP_88_ADDR 0x62C -#define TRQ_SEL_FMAP_88_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_88_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_88_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_S80_HARD_TRQ_SEL_FMAP_89_ADDR 0x630 -#define TRQ_SEL_FMAP_89_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_89_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_89_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_S80_HARD_TRQ_SEL_FMAP_8A_ADDR 0x634 -#define TRQ_SEL_FMAP_8A_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_8A_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_8A_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_S80_HARD_TRQ_SEL_FMAP_8B_ADDR 0x638 -#define TRQ_SEL_FMAP_8B_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_8B_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_8B_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_S80_HARD_TRQ_SEL_FMAP_8C_ADDR 0x63C -#define TRQ_SEL_FMAP_8C_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_8C_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_8C_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_S80_HARD_TRQ_SEL_FMAP_8D_ADDR 0x640 -#define TRQ_SEL_FMAP_8D_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_8D_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_8D_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_S80_HARD_TRQ_SEL_FMAP_8E_ADDR 0x644 -#define TRQ_SEL_FMAP_8E_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_8E_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_8E_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_S80_HARD_TRQ_SEL_FMAP_8F_ADDR 0x648 -#define TRQ_SEL_FMAP_8F_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_8F_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_8F_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_S80_HARD_TRQ_SEL_FMAP_90_ADDR 0x64C -#define TRQ_SEL_FMAP_90_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_90_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_90_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_S80_HARD_TRQ_SEL_FMAP_91_ADDR 0x650 -#define TRQ_SEL_FMAP_91_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_91_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_91_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_S80_HARD_TRQ_SEL_FMAP_92_ADDR 0x654 -#define TRQ_SEL_FMAP_92_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_92_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_92_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_S80_HARD_TRQ_SEL_FMAP_93_ADDR 0x658 -#define TRQ_SEL_FMAP_93_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_93_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_93_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_S80_HARD_TRQ_SEL_FMAP_94_ADDR 0x65C -#define TRQ_SEL_FMAP_94_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_94_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_94_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_S80_HARD_TRQ_SEL_FMAP_95_ADDR 0x660 -#define TRQ_SEL_FMAP_95_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_95_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_95_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_S80_HARD_TRQ_SEL_FMAP_96_ADDR 0x664 -#define TRQ_SEL_FMAP_96_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_96_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_96_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_S80_HARD_TRQ_SEL_FMAP_97_ADDR 0x668 -#define TRQ_SEL_FMAP_97_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_97_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_97_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_S80_HARD_TRQ_SEL_FMAP_98_ADDR 0x66C -#define TRQ_SEL_FMAP_98_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_98_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_98_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_S80_HARD_TRQ_SEL_FMAP_99_ADDR 0x670 -#define TRQ_SEL_FMAP_99_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_99_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_99_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_S80_HARD_TRQ_SEL_FMAP_9A_ADDR 0x674 -#define TRQ_SEL_FMAP_9A_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_9A_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_9A_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_S80_HARD_TRQ_SEL_FMAP_9B_ADDR 0x678 -#define TRQ_SEL_FMAP_9B_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_9B_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_9B_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_S80_HARD_TRQ_SEL_FMAP_9C_ADDR 0x67C -#define TRQ_SEL_FMAP_9C_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_9C_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_9C_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_S80_HARD_TRQ_SEL_FMAP_9D_ADDR 0x680 -#define TRQ_SEL_FMAP_9D_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_9D_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_9D_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_S80_HARD_TRQ_SEL_FMAP_9E_ADDR 0x684 -#define TRQ_SEL_FMAP_9E_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_9E_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_9E_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_S80_HARD_TRQ_SEL_FMAP_9F_ADDR 0x688 -#define TRQ_SEL_FMAP_9F_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_9F_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_9F_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_S80_HARD_TRQ_SEL_FMAP_A0_ADDR 0x68C -#define TRQ_SEL_FMAP_A0_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_A0_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_A0_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_S80_HARD_TRQ_SEL_FMAP_A1_ADDR 0x690 -#define TRQ_SEL_FMAP_A1_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_A1_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_A1_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_S80_HARD_TRQ_SEL_FMAP_A2_ADDR 0x694 -#define TRQ_SEL_FMAP_A2_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_A2_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_A2_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_S80_HARD_TRQ_SEL_FMAP_A3_ADDR 0x698 -#define TRQ_SEL_FMAP_A3_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_A3_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_A3_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_S80_HARD_TRQ_SEL_FMAP_A4_ADDR 0x69C -#define TRQ_SEL_FMAP_A4_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_A4_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_A4_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_S80_HARD_TRQ_SEL_FMAP_A5_ADDR 0x6A0 -#define TRQ_SEL_FMAP_A5_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_A5_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_A5_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_S80_HARD_TRQ_SEL_FMAP_A6_ADDR 0x6A4 -#define TRQ_SEL_FMAP_A6_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_A6_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_A6_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_S80_HARD_TRQ_SEL_FMAP_A7_ADDR 0x6A8 -#define TRQ_SEL_FMAP_A7_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_A7_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_A7_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_S80_HARD_TRQ_SEL_FMAP_A8_ADDR 0x6AC -#define TRQ_SEL_FMAP_A8_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_A8_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_A8_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_S80_HARD_TRQ_SEL_FMAP_A9_ADDR 0x6B0 -#define TRQ_SEL_FMAP_A9_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_A9_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_A9_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_S80_HARD_TRQ_SEL_FMAP_AA_ADDR 0x6B4 -#define TRQ_SEL_FMAP_AA_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_AA_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_AA_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_S80_HARD_TRQ_SEL_FMAP_AB_ADDR 0x6B8 -#define TRQ_SEL_FMAP_AB_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_AB_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_AB_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_S80_HARD_TRQ_SEL_FMAP_AC_ADDR 0x6BC -#define TRQ_SEL_FMAP_AC_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_AC_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_AC_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_S80_HARD_TRQ_SEL_FMAP_AD_ADDR 0x6D0 -#define TRQ_SEL_FMAP_AD_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_AD_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_AD_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_S80_HARD_TRQ_SEL_FMAP_AE_ADDR 0x6D4 -#define TRQ_SEL_FMAP_AE_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_AE_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_AE_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_S80_HARD_TRQ_SEL_FMAP_AF_ADDR 0x6D8 -#define TRQ_SEL_FMAP_AF_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_AF_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_AF_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_S80_HARD_TRQ_SEL_FMAP_B0_ADDR 0x6DC -#define TRQ_SEL_FMAP_B0_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_B0_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_B0_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_S80_HARD_TRQ_SEL_FMAP_B1_ADDR 0x6E0 -#define TRQ_SEL_FMAP_B1_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_B1_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_B1_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_S80_HARD_TRQ_SEL_FMAP_B2_ADDR 0x6E4 -#define TRQ_SEL_FMAP_B2_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_B2_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_B2_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_S80_HARD_TRQ_SEL_FMAP_B3_ADDR 0x6E8 -#define TRQ_SEL_FMAP_B3_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_B3_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_B3_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_S80_HARD_TRQ_SEL_FMAP_B4_ADDR 0x6EC -#define TRQ_SEL_FMAP_B4_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_B4_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_B4_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_S80_HARD_TRQ_SEL_FMAP_B5_ADDR 0x6F0 -#define TRQ_SEL_FMAP_B5_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_B5_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_B5_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_S80_HARD_TRQ_SEL_FMAP_B6_ADDR 0x6F4 -#define TRQ_SEL_FMAP_B6_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_B6_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_B6_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_S80_HARD_TRQ_SEL_FMAP_B7_ADDR 0x6F8 -#define TRQ_SEL_FMAP_B7_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_B7_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_B7_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_S80_HARD_TRQ_SEL_FMAP_B8_ADDR 0x6FC -#define TRQ_SEL_FMAP_B8_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_B8_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_B8_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_S80_HARD_TRQ_SEL_FMAP_B9_ADDR 0x700 -#define TRQ_SEL_FMAP_B9_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_B9_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_B9_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_S80_HARD_TRQ_SEL_FMAP_BA_ADDR 0x704 -#define TRQ_SEL_FMAP_BA_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_BA_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_BA_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_S80_HARD_TRQ_SEL_FMAP_BB_ADDR 0x708 -#define TRQ_SEL_FMAP_BB_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_BB_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_BB_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_S80_HARD_TRQ_SEL_FMAP_BC_ADDR 0x70C -#define TRQ_SEL_FMAP_BC_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_BC_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_BC_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_S80_HARD_TRQ_SEL_FMAP_BD_ADDR 0x710 -#define TRQ_SEL_FMAP_BD_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_BD_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_BD_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_S80_HARD_TRQ_SEL_FMAP_BE_ADDR 0x714 -#define TRQ_SEL_FMAP_BE_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_BE_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_BE_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_S80_HARD_TRQ_SEL_FMAP_BF_ADDR 0x718 -#define TRQ_SEL_FMAP_BF_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_BF_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_BF_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_S80_HARD_TRQ_SEL_FMAP_C0_ADDR 0x71C -#define TRQ_SEL_FMAP_C0_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_C0_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_C0_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_S80_HARD_TRQ_SEL_FMAP_C1_ADDR 0x720 -#define TRQ_SEL_FMAP_C1_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_C1_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_C1_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_S80_HARD_TRQ_SEL_FMAP_C2_ADDR 0x734 -#define TRQ_SEL_FMAP_C2_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_C2_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_C2_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_S80_HARD_TRQ_SEL_FMAP_C3_ADDR 0x748 -#define TRQ_SEL_FMAP_C3_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_C3_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_C3_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_S80_HARD_TRQ_SEL_FMAP_C4_ADDR 0x74C -#define TRQ_SEL_FMAP_C4_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_C4_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_C4_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_S80_HARD_TRQ_SEL_FMAP_C5_ADDR 0x750 -#define TRQ_SEL_FMAP_C5_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_C5_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_C5_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_S80_HARD_TRQ_SEL_FMAP_C6_ADDR 0x754 -#define TRQ_SEL_FMAP_C6_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_C6_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_C6_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_S80_HARD_TRQ_SEL_FMAP_C7_ADDR 0x758 -#define TRQ_SEL_FMAP_C7_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_C7_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_C7_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_S80_HARD_TRQ_SEL_FMAP_C8_ADDR 0x75C -#define TRQ_SEL_FMAP_C8_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_C8_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_C8_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_S80_HARD_TRQ_SEL_FMAP_C9_ADDR 0x760 -#define TRQ_SEL_FMAP_C9_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_C9_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_C9_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_S80_HARD_TRQ_SEL_FMAP_CA_ADDR 0x764 -#define TRQ_SEL_FMAP_CA_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_CA_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_CA_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_S80_HARD_TRQ_SEL_FMAP_CB_ADDR 0x768 -#define TRQ_SEL_FMAP_CB_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_CB_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_CB_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_S80_HARD_TRQ_SEL_FMAP_CC_ADDR 0x76C -#define TRQ_SEL_FMAP_CC_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_CC_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_CC_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_S80_HARD_TRQ_SEL_FMAP_CD_ADDR 0x770 -#define TRQ_SEL_FMAP_CD_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_CD_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_CD_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_S80_HARD_TRQ_SEL_FMAP_CE_ADDR 0x774 -#define TRQ_SEL_FMAP_CE_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_CE_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_CE_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_S80_HARD_TRQ_SEL_FMAP_CF_ADDR 0x778 -#define TRQ_SEL_FMAP_CF_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_CF_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_CF_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_S80_HARD_TRQ_SEL_FMAP_D0_ADDR 0x77C -#define TRQ_SEL_FMAP_D0_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_D0_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_D0_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_S80_HARD_TRQ_SEL_FMAP_D1_ADDR 0x780 -#define TRQ_SEL_FMAP_D1_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_D1_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_D1_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_S80_HARD_TRQ_SEL_FMAP_D2_ADDR 0x784 -#define TRQ_SEL_FMAP_D2_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_D2_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_D2_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_S80_HARD_TRQ_SEL_FMAP_D3_ADDR 0x788 -#define TRQ_SEL_FMAP_D3_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_D3_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_D3_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_S80_HARD_TRQ_SEL_FMAP_D4_ADDR 0x78C -#define TRQ_SEL_FMAP_D4_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_D4_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_D4_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_S80_HARD_TRQ_SEL_FMAP_D5_ADDR 0x790 -#define TRQ_SEL_FMAP_D5_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_D5_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_D5_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_S80_HARD_TRQ_SEL_FMAP_D6_ADDR 0x794 -#define TRQ_SEL_FMAP_D6_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_D6_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_D6_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_S80_HARD_TRQ_SEL_FMAP_D7_ADDR 0x798 -#define TRQ_SEL_FMAP_D7_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_D7_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_D7_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_S80_HARD_TRQ_SEL_FMAP_D8_ADDR 0x79C -#define TRQ_SEL_FMAP_D8_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_D8_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_D8_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_S80_HARD_TRQ_SEL_FMAP_D9_ADDR 0x7A0 -#define TRQ_SEL_FMAP_D9_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_D9_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_D9_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_S80_HARD_TRQ_SEL_FMAP_DA_ADDR 0x7A4 -#define TRQ_SEL_FMAP_DA_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_DA_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_DA_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_S80_HARD_TRQ_SEL_FMAP_DB_ADDR 0x7A8 -#define TRQ_SEL_FMAP_DB_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_DB_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_DB_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_S80_HARD_TRQ_SEL_FMAP_DC_ADDR 0x7AC -#define TRQ_SEL_FMAP_DC_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_DC_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_DC_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_S80_HARD_TRQ_SEL_FMAP_DD_ADDR 0x7B0 -#define TRQ_SEL_FMAP_DD_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_DD_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_DD_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_S80_HARD_TRQ_SEL_FMAP_DE_ADDR 0x7B4 -#define TRQ_SEL_FMAP_DE_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_DE_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_DE_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_S80_HARD_TRQ_SEL_FMAP_DF_ADDR 0x7B8 -#define TRQ_SEL_FMAP_DF_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_DF_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_DF_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_S80_HARD_TRQ_SEL_FMAP_E0_ADDR 0x7BC -#define TRQ_SEL_FMAP_E0_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_E0_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_E0_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_S80_HARD_TRQ_SEL_FMAP_E1_ADDR 0x7C0 -#define TRQ_SEL_FMAP_E1_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_E1_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_E1_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_S80_HARD_TRQ_SEL_FMAP_E2_ADDR 0x7C4 -#define TRQ_SEL_FMAP_E2_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_E2_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_E2_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_S80_HARD_TRQ_SEL_FMAP_E3_ADDR 0x7C8 -#define TRQ_SEL_FMAP_E3_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_E3_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_E3_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_S80_HARD_TRQ_SEL_FMAP_E4_ADDR 0x7CC -#define TRQ_SEL_FMAP_E4_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_E4_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_E4_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_S80_HARD_TRQ_SEL_FMAP_E5_ADDR 0x7D0 -#define TRQ_SEL_FMAP_E5_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_E5_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_E5_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_S80_HARD_TRQ_SEL_FMAP_E6_ADDR 0x7D4 -#define TRQ_SEL_FMAP_E6_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_E6_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_E6_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_S80_HARD_TRQ_SEL_FMAP_E7_ADDR 0x7D8 -#define TRQ_SEL_FMAP_E7_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_E7_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_E7_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_S80_HARD_TRQ_SEL_FMAP_E8_ADDR 0x7DC -#define TRQ_SEL_FMAP_E8_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_E8_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_E8_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_S80_HARD_TRQ_SEL_FMAP_E9_ADDR 0x7E0 -#define TRQ_SEL_FMAP_E9_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_E9_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_E9_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_S80_HARD_TRQ_SEL_FMAP_EA_ADDR 0x7E4 -#define TRQ_SEL_FMAP_EA_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_EA_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_EA_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_S80_HARD_TRQ_SEL_FMAP_EB_ADDR 0x7E8 -#define TRQ_SEL_FMAP_EB_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_EB_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_EB_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_S80_HARD_TRQ_SEL_FMAP_EC_ADDR 0x7EC -#define TRQ_SEL_FMAP_EC_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_EC_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_EC_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_S80_HARD_TRQ_SEL_FMAP_ED_ADDR 0x7F0 -#define TRQ_SEL_FMAP_ED_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_ED_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_ED_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_S80_HARD_TRQ_SEL_FMAP_EE_ADDR 0x7F4 -#define TRQ_SEL_FMAP_EE_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_EE_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_EE_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_S80_HARD_TRQ_SEL_FMAP_EF_ADDR 0x7F8 -#define TRQ_SEL_FMAP_EF_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_EF_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_EF_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_S80_HARD_TRQ_SEL_FMAP_F0_ADDR 0x7FC -#define TRQ_SEL_FMAP_F0_RSVD_1_MASK GENMASK(31, 23) -#define TRQ_SEL_FMAP_F0_QID_MAX_MASK GENMASK(22, 11) -#define TRQ_SEL_FMAP_F0_QID_BASE_MASK GENMASK(10, 0) -#define QDMA_S80_HARD_IND_CTXT_DATA_3_ADDR 0x804 -#define IND_CTXT_DATA_3_DATA_MASK GENMASK(31, 0) -#define QDMA_S80_HARD_IND_CTXT_DATA_2_ADDR 0x808 -#define IND_CTXT_DATA_2_DATA_MASK GENMASK(31, 0) -#define QDMA_S80_HARD_IND_CTXT_DATA_1_ADDR 0x80C -#define IND_CTXT_DATA_1_DATA_MASK GENMASK(31, 0) -#define QDMA_S80_HARD_IND_CTXT_DATA_0_ADDR 0x810 -#define IND_CTXT_DATA_0_DATA_MASK GENMASK(31, 0) -#define QDMA_S80_HARD_IND_CTXT3_ADDR 0x814 -#define IND_CTXT3_MASK GENMASK(31, 0) -#define QDMA_S80_HARD_IND_CTXT2_ADDR 0x818 -#define IND_CTXT2_MASK GENMASK(31, 0) -#define QDMA_S80_HARD_IND_CTXT1_ADDR 0x81C -#define IND_CTXT1_MASK GENMASK(31, 0) -#define QDMA_S80_HARD_IND_CTXT0_ADDR 0x820 -#define IND_CTXT0_MASK GENMASK(31, 0) -#define QDMA_S80_HARD_IND_CTXT_CMD_ADDR 0x824 -#define IND_CTXT_CMD_RSVD_1_MASK GENMASK(31, 18) -#define IND_CTXT_CMD_QID_MASK GENMASK(17, 7) -#define IND_CTXT_CMD_OP_MASK GENMASK(6, 5) -#define IND_CTXT_CMD_SET_MASK GENMASK(4, 1) -#define IND_CTXT_CMD_BUSY_MASK BIT(0) -#define QDMA_S80_HARD_C2H_TIMER_CNT_1_ADDR 0xA00 -#define C2H_TIMER_CNT_1_RSVD_1_MASK GENMASK(31, 8) -#define C2H_TIMER_CNT_1_MASK GENMASK(7, 0) -#define QDMA_S80_HARD_C2H_TIMER_CNT_2_ADDR 0xA04 -#define C2H_TIMER_CNT_2_RSVD_1_MASK GENMASK(31, 8) -#define C2H_TIMER_CNT_2_MASK GENMASK(7, 0) -#define QDMA_S80_HARD_C2H_TIMER_CNT_3_ADDR 0xA08 -#define C2H_TIMER_CNT_3_RSVD_1_MASK GENMASK(31, 8) -#define C2H_TIMER_CNT_3_MASK GENMASK(7, 0) -#define QDMA_S80_HARD_C2H_TIMER_CNT_4_ADDR 0xA0C -#define C2H_TIMER_CNT_4_RSVD_1_MASK GENMASK(31, 8) -#define C2H_TIMER_CNT_4_MASK GENMASK(7, 0) -#define QDMA_S80_HARD_C2H_TIMER_CNT_5_ADDR 0xA10 -#define C2H_TIMER_CNT_5_RSVD_1_MASK GENMASK(31, 8) -#define C2H_TIMER_CNT_5_MASK GENMASK(7, 0) -#define QDMA_S80_HARD_C2H_TIMER_CNT_6_ADDR 0xA14 -#define C2H_TIMER_CNT_6_RSVD_1_MASK GENMASK(31, 8) -#define C2H_TIMER_CNT_6_MASK GENMASK(7, 0) -#define QDMA_S80_HARD_C2H_TIMER_CNT_7_ADDR 0xA18 -#define C2H_TIMER_CNT_7_RSVD_1_MASK GENMASK(31, 8) -#define C2H_TIMER_CNT_7_MASK GENMASK(7, 0) -#define QDMA_S80_HARD_C2H_TIMER_CNT_8_ADDR 0xA1C -#define C2H_TIMER_CNT_8_RSVD_1_MASK GENMASK(31, 8) -#define C2H_TIMER_CNT_8_MASK GENMASK(7, 0) -#define QDMA_S80_HARD_C2H_TIMER_CNT_9_ADDR 0xA20 -#define C2H_TIMER_CNT_9_RSVD_1_MASK GENMASK(31, 8) -#define C2H_TIMER_CNT_9_MASK GENMASK(7, 0) -#define QDMA_S80_HARD_C2H_TIMER_CNT_A_ADDR 0xA24 -#define C2H_TIMER_CNT_A_RSVD_1_MASK GENMASK(31, 8) -#define C2H_TIMER_CNT_A_MASK GENMASK(7, 0) -#define QDMA_S80_HARD_C2H_TIMER_CNT_B_ADDR 0xA28 -#define C2H_TIMER_CNT_B_RSVD_1_MASK GENMASK(31, 8) -#define C2H_TIMER_CNT_B_MASK GENMASK(7, 0) -#define QDMA_S80_HARD_C2H_TIMER_CNT_C_ADDR 0xA2C -#define C2H_TIMER_CNT_C_RSVD_1_MASK GENMASK(31, 8) -#define C2H_TIMER_CNT_C_MASK GENMASK(7, 0) -#define QDMA_S80_HARD_C2H_TIMER_CNT_D_ADDR 0xA30 -#define C2H_TIMER_CNT_D_RSVD_1_MASK GENMASK(31, 8) -#define C2H_TIMER_CNT_D_MASK GENMASK(7, 0) -#define QDMA_S80_HARD_C2H_TIMER_CNT_E_ADDR 0xA34 -#define C2H_TIMER_CNT_E_RSVD_1_MASK GENMASK(31, 8) -#define C2H_TIMER_CNT_E_MASK GENMASK(7, 0) -#define QDMA_S80_HARD_C2H_TIMER_CNT_F_ADDR 0xA38 -#define C2H_TIMER_CNT_F_RSVD_1_MASK GENMASK(31, 8) -#define C2H_TIMER_CNT_F_MASK GENMASK(7, 0) -#define QDMA_S80_HARD_C2H_TIMER_CNT_10_ADDR 0xA3C -#define C2H_TIMER_CNT_10_RSVD_1_MASK GENMASK(31, 8) -#define C2H_TIMER_CNT_10_MASK GENMASK(7, 0) -#define QDMA_S80_HARD_C2H_CNT_TH_1_ADDR 0xA40 -#define C2H_CNT_TH_1_RSVD_1_MASK GENMASK(31, 8) -#define C2H_CNT_TH_1_THESHOLD_CNT_MASK GENMASK(7, 0) -#define QDMA_S80_HARD_C2H_CNT_TH_2_ADDR 0xA44 -#define C2H_CNT_TH_2_RSVD_1_MASK GENMASK(31, 8) -#define C2H_CNT_TH_2_THESHOLD_CNT_MASK GENMASK(7, 0) -#define QDMA_S80_HARD_C2H_CNT_TH_3_ADDR 0xA48 -#define C2H_CNT_TH_3_RSVD_1_MASK GENMASK(31, 8) -#define C2H_CNT_TH_3_THESHOLD_CNT_MASK GENMASK(7, 0) -#define QDMA_S80_HARD_C2H_CNT_TH_4_ADDR 0xA4C -#define C2H_CNT_TH_4_RSVD_1_MASK GENMASK(31, 8) -#define C2H_CNT_TH_4_THESHOLD_CNT_MASK GENMASK(7, 0) -#define QDMA_S80_HARD_C2H_CNT_TH_5_ADDR 0xA50 -#define C2H_CNT_TH_5_RSVD_1_MASK GENMASK(31, 8) -#define C2H_CNT_TH_5_THESHOLD_CNT_MASK GENMASK(7, 0) -#define QDMA_S80_HARD_C2H_CNT_TH_6_ADDR 0xA54 -#define C2H_CNT_TH_6_RSVD_1_MASK GENMASK(31, 8) -#define C2H_CNT_TH_6_THESHOLD_CNT_MASK GENMASK(7, 0) -#define QDMA_S80_HARD_C2H_CNT_TH_7_ADDR 0xA58 -#define C2H_CNT_TH_7_RSVD_1_MASK GENMASK(31, 8) -#define C2H_CNT_TH_7_THESHOLD_CNT_MASK GENMASK(7, 0) -#define QDMA_S80_HARD_C2H_CNT_TH_8_ADDR 0xA5C -#define C2H_CNT_TH_8_RSVD_1_MASK GENMASK(31, 8) -#define C2H_CNT_TH_8_THESHOLD_CNT_MASK GENMASK(7, 0) -#define QDMA_S80_HARD_C2H_CNT_TH_9_ADDR 0xA60 -#define C2H_CNT_TH_9_RSVD_1_MASK GENMASK(31, 8) -#define C2H_CNT_TH_9_THESHOLD_CNT_MASK GENMASK(7, 0) -#define QDMA_S80_HARD_C2H_CNT_TH_A_ADDR 0xA64 -#define C2H_CNT_TH_A_RSVD_1_MASK GENMASK(31, 8) -#define C2H_CNT_TH_A_THESHOLD_CNT_MASK GENMASK(7, 0) -#define QDMA_S80_HARD_C2H_CNT_TH_B_ADDR 0xA68 -#define C2H_CNT_TH_B_RSVD_1_MASK GENMASK(31, 8) -#define C2H_CNT_TH_B_THESHOLD_CNT_MASK GENMASK(7, 0) -#define QDMA_S80_HARD_C2H_CNT_TH_C_ADDR 0xA6C -#define C2H_CNT_TH_C_RSVD_1_MASK GENMASK(31, 8) -#define C2H_CNT_TH_C_THESHOLD_CNT_MASK GENMASK(7, 0) -#define QDMA_S80_HARD_C2H_CNT_TH_D_ADDR 0xA70 -#define C2H_CNT_TH_D_RSVD_1_MASK GENMASK(31, 8) -#define C2H_CNT_TH_D_THESHOLD_CNT_MASK GENMASK(7, 0) -#define QDMA_S80_HARD_C2H_CNT_TH_E_ADDR 0xA74 -#define C2H_CNT_TH_E_RSVD_1_MASK GENMASK(31, 8) -#define C2H_CNT_TH_E_THESHOLD_CNT_MASK GENMASK(7, 0) -#define QDMA_S80_HARD_C2H_CNT_TH_F_ADDR 0xA78 -#define C2H_CNT_TH_F_RSVD_1_MASK GENMASK(31, 8) -#define C2H_CNT_TH_F_THESHOLD_CNT_MASK GENMASK(7, 0) -#define QDMA_S80_HARD_C2H_CNT_TH_10_ADDR 0xA7C -#define C2H_CNT_TH_10_RSVD_1_MASK GENMASK(31, 8) -#define C2H_CNT_TH_10_THESHOLD_CNT_MASK GENMASK(7, 0) -#define QDMA_S80_HARD_C2H_QID2VEC_MAP_QID_ADDR 0xA80 -#define C2H_QID2VEC_MAP_QID_RSVD_1_MASK GENMASK(31, 11) -#define C2H_QID2VEC_MAP_QID_QID_MASK GENMASK(10, 0) -#define QDMA_S80_HARD_C2H_QID2VEC_MAP_ADDR 0xA84 -#define C2H_QID2VEC_MAP_RSVD_1_MASK GENMASK(31, 19) -#define C2H_QID2VEC_MAP_H2C_EN_COAL_MASK BIT(18) -#define C2H_QID2VEC_MAP_H2C_VECTOR_MASK GENMASK(17, 9) -#define C2H_QID2VEC_MAP_C2H_EN_COAL_MASK BIT(8) -#define C2H_QID2VEC_MAP_C2H_VECTOR_MASK GENMASK(7, 0) -#define QDMA_S80_HARD_C2H_STAT_S_AXIS_C2H_ACCEPTED_ADDR 0xA88 -#define C2H_STAT_S_AXIS_C2H_ACCEPTED_MASK GENMASK(31, 0) -#define QDMA_S80_HARD_C2H_STAT_S_AXIS_WRB_ACCEPTED_ADDR 0xA8C -#define C2H_STAT_S_AXIS_WRB_ACCEPTED_MASK GENMASK(31, 0) -#define QDMA_S80_HARD_C2H_STAT_DESC_RSP_PKT_ACCEPTED_ADDR 0xA90 -#define C2H_STAT_DESC_RSP_PKT_ACCEPTED_D_MASK GENMASK(31, 0) -#define QDMA_S80_HARD_C2H_STAT_AXIS_PKG_CMP_ADDR 0xA94 -#define C2H_STAT_AXIS_PKG_CMP_MASK GENMASK(31, 0) -#define QDMA_S80_HARD_C2H_STAT_DESC_RSP_ACCEPTED_ADDR 0xA98 -#define C2H_STAT_DESC_RSP_ACCEPTED_D_MASK GENMASK(31, 0) -#define QDMA_S80_HARD_C2H_STAT_DESC_RSP_CMP_ADDR 0xA9C -#define C2H_STAT_DESC_RSP_CMP_D_MASK GENMASK(31, 0) -#define QDMA_S80_HARD_C2H_STAT_WRQ_OUT_ADDR 0xAA0 -#define C2H_STAT_WRQ_OUT_MASK GENMASK(31, 0) -#define QDMA_S80_HARD_C2H_STAT_WPL_REN_ACCEPTED_ADDR 0xAA4 -#define C2H_STAT_WPL_REN_ACCEPTED_MASK GENMASK(31, 0) -#define QDMA_S80_HARD_C2H_STAT_TOTAL_WRQ_LEN_ADDR 0xAA8 -#define C2H_STAT_TOTAL_WRQ_LEN_MASK GENMASK(31, 0) -#define QDMA_S80_HARD_C2H_STAT_TOTAL_WPL_LEN_ADDR 0xAAC -#define C2H_STAT_TOTAL_WPL_LEN_MASK GENMASK(31, 0) -#define QDMA_S80_HARD_C2H_BUF_SZ_0_ADDR 0xAB0 -#define C2H_BUF_SZ_0_SIZE_MASK GENMASK(31, 0) -#define QDMA_S80_HARD_C2H_BUF_SZ_1_ADDR 0xAB4 -#define C2H_BUF_SZ_1_SIZE_MASK GENMASK(31, 0) -#define QDMA_S80_HARD_C2H_BUF_SZ_2_ADDR 0xAB8 -#define C2H_BUF_SZ_2_SIZE_MASK GENMASK(31, 0) -#define QDMA_S80_HARD_C2H_BUF_SZ_3_ADDR 0xABC -#define C2H_BUF_SZ_3_SIZE_MASK GENMASK(31, 0) -#define QDMA_S80_HARD_C2H_BUF_SZ_4_ADDR 0xAC0 -#define C2H_BUF_SZ_4_SIZE_MASK GENMASK(31, 0) -#define QDMA_S80_HARD_C2H_BUF_SZ_5_ADDR 0xAC4 -#define C2H_BUF_SZ_5_SIZE_MASK GENMASK(31, 0) -#define QDMA_S80_HARD_C2H_BUF_SZ_7_ADDR 0XAC8 -#define C2H_BUF_SZ_7_SIZE_MASK GENMASK(31, 0) -#define QDMA_S80_HARD_C2H_BUF_SZ_8_ADDR 0XACC -#define C2H_BUF_SZ_8_SIZE_MASK GENMASK(31, 0) -#define QDMA_S80_HARD_C2H_BUF_SZ_9_ADDR 0xAD0 -#define C2H_BUF_SZ_9_SIZE_MASK GENMASK(31, 0) -#define QDMA_S80_HARD_C2H_BUF_SZ_10_ADDR 0xAD4 -#define C2H_BUF_SZ_10_SIZE_MASK GENMASK(31, 0) -#define QDMA_S80_HARD_C2H_BUF_SZ_11_ADDR 0xAD8 -#define C2H_BUF_SZ_11_SIZE_MASK GENMASK(31, 0) -#define QDMA_S80_HARD_C2H_BUF_SZ_12_ADDR 0xAE0 -#define C2H_BUF_SZ_12_SIZE_MASK GENMASK(31, 0) -#define QDMA_S80_HARD_C2H_BUF_SZ_13_ADDR 0xAE4 -#define C2H_BUF_SZ_13_SIZE_MASK GENMASK(31, 0) -#define QDMA_S80_HARD_C2H_BUF_SZ_14_ADDR 0xAE8 -#define C2H_BUF_SZ_14_SIZE_MASK GENMASK(31, 0) -#define QDMA_S80_HARD_C2H_BUF_SZ_15_ADDR 0XAEC -#define C2H_BUF_SZ_15_SIZE_MASK GENMASK(31, 0) -#define QDMA_S80_HARD_C2H_ERR_STAT_ADDR 0xAF0 -#define C2H_ERR_STAT_RSVD_1_MASK GENMASK(31, 16) -#define C2H_ERR_STAT_WRB_PRTY_ERR_MASK BIT(15) -#define C2H_ERR_STAT_WRB_CIDX_ERR_MASK BIT(14) -#define C2H_ERR_STAT_WRB_QFULL_ERR_MASK BIT(13) -#define C2H_ERR_STAT_WRB_INV_Q_ERR_MASK BIT(12) -#define C2H_ERR_STAT_PORT_ID_BYP_IN_MISMATCH_MASK BIT(11) -#define C2H_ERR_STAT_PORT_ID_CTXT_MISMATCH_MASK BIT(10) -#define C2H_ERR_STAT_ERR_DESC_CNT_MASK BIT(9) -#define C2H_ERR_STAT_RSVD_2_MASK BIT(8) -#define C2H_ERR_STAT_MSI_INT_FAIL_MASK BIT(7) -#define C2H_ERR_STAT_ENG_WPL_DATA_PAR_ERR_MASK BIT(6) -#define C2H_ERR_STAT_RSVD_3_MASK BIT(5) -#define C2H_ERR_STAT_DESC_RSP_ERR_MASK BIT(4) -#define C2H_ERR_STAT_QID_MISMATCH_MASK BIT(3) -#define C2H_ERR_STAT_RSVD_4_MASK BIT(2) -#define C2H_ERR_STAT_LEN_MISMATCH_MASK BIT(1) -#define C2H_ERR_STAT_MTY_MISMATCH_MASK BIT(0) -#define QDMA_S80_HARD_C2H_ERR_MASK_ADDR 0xAF4 -#define C2H_ERR_EN_MASK GENMASK(31, 0) -#define QDMA_S80_HARD_C2H_FATAL_ERR_STAT_ADDR 0xAF8 -#define C2H_FATAL_ERR_STAT_RSVD_1_MASK GENMASK(31, 19) -#define C2H_FATAL_ERR_STAT_WPL_DATA_PAR_ERR_MASK BIT(18) -#define C2H_FATAL_ERR_STAT_PLD_FIFO_RAM_RDBE_MASK BIT(17) -#define C2H_FATAL_ERR_STAT_QID_FIFO_RAM_RDBE_MASK BIT(16) -#define C2H_FATAL_ERR_STAT_TUSER_FIFO_RAM_RDBE_MASK BIT(15) -#define C2H_FATAL_ERR_STAT_WRB_COAL_DATA_RAM_RDBE_MASK BIT(14) -#define C2H_FATAL_ERR_STAT_INT_QID2VEC_RAM_RDBE_MASK BIT(13) -#define C2H_FATAL_ERR_STAT_INT_CTXT_RAM_RDBE_MASK BIT(12) -#define C2H_FATAL_ERR_STAT_DESC_REQ_FIFO_RAM_RDBE_MASK BIT(11) -#define C2H_FATAL_ERR_STAT_PFCH_CTXT_RAM_RDBE_MASK BIT(10) -#define C2H_FATAL_ERR_STAT_WRB_CTXT_RAM_RDBE_MASK BIT(9) -#define C2H_FATAL_ERR_STAT_PFCH_LL_RAM_RDBE_MASK BIT(8) -#define C2H_FATAL_ERR_STAT_TIMER_FIFO_RAM_RDBE_MASK GENMASK(7, 4) -#define C2H_FATAL_ERR_STAT_QID_MISMATCH_MASK BIT(3) -#define C2H_FATAL_ERR_STAT_RSVD_2_MASK BIT(2) -#define C2H_FATAL_ERR_STAT_LEN_MISMATCH_MASK BIT(1) -#define C2H_FATAL_ERR_STAT_MTY_MISMATCH_MASK BIT(0) -#define QDMA_S80_HARD_C2H_FATAL_ERR_MASK_ADDR 0xAFC -#define C2H_FATAL_ERR_C2HEN_MASK GENMASK(31, 0) -#define QDMA_S80_HARD_C2H_FATAL_ERR_ENABLE_ADDR 0xB00 -#define C2H_FATAL_ERR_ENABLE_RSVD_1_MASK GENMASK(31, 2) -#define C2H_FATAL_ERR_ENABLE_WPL_PAR_INV_MASK BIT(1) -#define C2H_FATAL_ERR_ENABLE_WRQ_DIS_MASK BIT(0) -#define QDMA_S80_HARD_GLBL_ERR_INT_ADDR 0xB04 -#define GLBL_ERR_INT_RSVD_1_MASK GENMASK(31, 18) -#define GLBL_ERR_INT_ARM_MASK BIT(17) -#define GLBL_ERR_INT_EN_COAL_MASK BIT(16) -#define GLBL_ERR_INT_VEC_MASK GENMASK(15, 8) -#define GLBL_ERR_INT_FUNC_MASK GENMASK(7, 0) -#define QDMA_S80_HARD_C2H_PFCH_CFG_ADDR 0xB08 -#define C2H_PFCH_CFG_EVT_QCNT_TH_MASK GENMASK(31, 25) -#define C2H_PFCH_CFG_QCNT_MASK GENMASK(24, 16) -#define C2H_PFCH_CFG_NUM_MASK GENMASK(15, 8) -#define C2H_PFCH_CFG_FL_TH_MASK GENMASK(7, 0) -#define QDMA_S80_HARD_C2H_INT_TIMER_TICK_ADDR 0xB0C -#define C2H_INT_TIMER_TICK_MASK GENMASK(31, 0) -#define QDMA_S80_HARD_C2H_STAT_DESC_RSP_DROP_ACCEPTED_ADDR 0xB10 -#define C2H_STAT_DESC_RSP_DROP_ACCEPTED_D_MASK GENMASK(31, 0) -#define QDMA_S80_HARD_C2H_STAT_DESC_RSP_ERR_ACCEPTED_ADDR 0xB14 -#define C2H_STAT_DESC_RSP_ERR_ACCEPTED_D_MASK GENMASK(31, 0) -#define QDMA_S80_HARD_C2H_STAT_DESC_REQ_ADDR 0xB18 -#define C2H_STAT_DESC_REQ_MASK GENMASK(31, 0) -#define QDMA_S80_HARD_C2H_STAT_DBG_DMA_ENG_0_ADDR 0xB1C -#define C2H_STAT_DMA_ENG_0_RSVD_1_MASK BIT(31) -#define C2H_STAT_DMA_ENG_0_WRB_FIFO_OUT_CNT_MASK GENMASK(30, 28) -#define C2H_STAT_DMA_ENG_0_QID_FIFO_OUT_CNT_MASK GENMASK(27, 18) -#define C2H_STAT_DMA_ENG_0_PLD_FIFO_OUT_CNT_MASK GENMASK(17, 8) -#define C2H_STAT_DMA_ENG_0_WRQ_FIFO_OUT_CNT_MASK GENMASK(7, 5) -#define C2H_STAT_DMA_ENG_0_WRB_SM_CS_MASK BIT(4) -#define C2H_STAT_DMA_ENG_0_MAIN_SM_CS_MASK GENMASK(3, 0) -#define QDMA_S80_HARD_C2H_STAT_DBG_DMA_ENG_1_ADDR 0xB20 -#define C2H_STAT_DMA_ENG_1_RSVD_1_MASK BIT(31) -#define C2H_STAT_DMA_ENG_1_DESC_RSP_LAST_MASK BIT(30) -#define C2H_STAT_DMA_ENG_1_PLD_FIFO_IN_CNT_MASK GENMASK(29, 20) -#define C2H_STAT_DMA_ENG_1_PLD_FIFO_OUTPUT_CNT_MASK GENMASK(19, 10) -#define C2H_STAT_DMA_ENG_1_QID_FIFO_IN_CNT_MASK GENMASK(9, 0) -#define QDMA_S80_HARD_C2H_STAT_DBG_DMA_ENG_2_ADDR 0xB24 -#define C2H_STAT_DMA_ENG_2_RSVD_1_MASK GENMASK(31, 30) -#define C2H_STAT_DMA_ENG_2_WRB_FIFO_IN_CNT_MASK GENMASK(29, 20) -#define C2H_STAT_DMA_ENG_2_WRB_FIFO_OUTPUT_CNT_MASK GENMASK(19, 10) -#define C2H_STAT_DMA_ENG_2_QID_FIFO_OUTPUT_CNT_MASK GENMASK(9, 0) -#define QDMA_S80_HARD_C2H_STAT_DBG_DMA_ENG_3_ADDR 0xB28 -#define C2H_STAT_DMA_ENG_3_RSVD_1_MASK GENMASK(31, 30) -#define C2H_STAT_DMA_ENG_3_ADDR_4K_SPLIT_CNT_MASK GENMASK(29, 20) -#define C2H_STAT_DMA_ENG_3_WRQ_FIFO_IN_CNT_MASK GENMASK(19, 10) -#define C2H_STAT_DMA_ENG_3_WRQ_FIFO_OUTPUT_CNT_MASK GENMASK(9, 0) -#define QDMA_S80_HARD_C2H_DBG_PFCH_ERR_CTXT_ADDR 0xB2C -#define C2H_PFCH_ERR_CTXT_RSVD_1_MASK GENMASK(31, 14) -#define C2H_PFCH_ERR_CTXT_ERR_STAT_MASK BIT(13) -#define C2H_PFCH_ERR_CTXT_CMD_WR_MASK BIT(12) -#define C2H_PFCH_ERR_CTXT_QID_MASK GENMASK(11, 1) -#define C2H_PFCH_ERR_CTXT_DONE_MASK BIT(0) -#define QDMA_S80_HARD_C2H_FIRST_ERR_QID_ADDR 0xB30 -#define C2H_FIRST_ERR_QID_RSVD_1_MASK GENMASK(31, 21) -#define C2H_FIRST_ERR_QID_ERR_STAT_MASK GENMASK(20, 16) -#define C2H_FIRST_ERR_QID_CMD_WR_MASK GENMASK(15, 12) -#define C2H_FIRST_ERR_QID_QID_MASK GENMASK(11, 0) -#define QDMA_S80_HARD_STAT_NUM_WRB_IN_ADDR 0xB34 -#define STAT_NUM_WRB_IN_RSVD_1_MASK GENMASK(31, 16) -#define STAT_NUM_WRB_IN_WRB_CNT_MASK GENMASK(15, 0) -#define QDMA_S80_HARD_STAT_NUM_WRB_OUT_ADDR 0xB38 -#define STAT_NUM_WRB_OUT_RSVD_1_MASK GENMASK(31, 16) -#define STAT_NUM_WRB_OUT_WRB_CNT_MASK GENMASK(15, 0) -#define QDMA_S80_HARD_STAT_NUM_WRB_DRP_ADDR 0xB3C -#define STAT_NUM_WRB_DRP_RSVD_1_MASK GENMASK(31, 16) -#define STAT_NUM_WRB_DRP_WRB_CNT_MASK GENMASK(15, 0) -#define QDMA_S80_HARD_STAT_NUM_STAT_DESC_OUT_ADDR 0xB40 -#define STAT_NUM_STAT_DESC_OUT_RSVD_1_MASK GENMASK(31, 16) -#define STAT_NUM_STAT_DESC_OUT_CNT_MASK GENMASK(15, 0) -#define QDMA_S80_HARD_STAT_NUM_DSC_CRDT_SENT_ADDR 0xB44 -#define STAT_NUM_DSC_CRDT_SENT_RSVD_1_MASK GENMASK(31, 16) -#define STAT_NUM_DSC_CRDT_SENT_CNT_MASK GENMASK(15, 0) -#define QDMA_S80_HARD_STAT_NUM_FCH_DSC_RCVD_ADDR 0xB48 -#define STAT_NUM_FCH_DSC_RCVD_RSVD_1_MASK GENMASK(31, 16) -#define STAT_NUM_FCH_DSC_RCVD_DSC_CNT_MASK GENMASK(15, 0) -#define QDMA_S80_HARD_STAT_NUM_BYP_DSC_RCVD_ADDR 0xB4C -#define STAT_NUM_BYP_DSC_RCVD_RSVD_1_MASK GENMASK(31, 11) -#define STAT_NUM_BYP_DSC_RCVD_DSC_CNT_MASK GENMASK(10, 0) -#define QDMA_S80_HARD_C2H_WRB_COAL_CFG_ADDR 0xB50 -#define C2H_WRB_COAL_CFG_MAX_BUF_SZ_MASK GENMASK(31, 26) -#define C2H_WRB_COAL_CFG_TICK_VAL_MASK GENMASK(25, 14) -#define C2H_WRB_COAL_CFG_TICK_CNT_MASK GENMASK(13, 2) -#define C2H_WRB_COAL_CFG_SET_GLB_FLUSH_MASK BIT(1) -#define C2H_WRB_COAL_CFG_DONE_GLB_FLUSH_MASK BIT(0) -#define QDMA_S80_HARD_C2H_INTR_H2C_REQ_ADDR 0xB54 -#define C2H_INTR_H2C_REQ_RSVD_1_MASK GENMASK(31, 18) -#define C2H_INTR_H2C_REQ_CNT_MASK GENMASK(17, 0) -#define QDMA_S80_HARD_C2H_INTR_C2H_MM_REQ_ADDR 0xB58 -#define C2H_INTR_C2H_MM_REQ_RSVD_1_MASK GENMASK(31, 18) -#define C2H_INTR_C2H_MM_REQ_CNT_MASK GENMASK(17, 0) -#define QDMA_S80_HARD_C2H_INTR_ERR_INT_REQ_ADDR 0xB5C -#define C2H_INTR_ERR_INT_REQ_RSVD_1_MASK GENMASK(31, 18) -#define C2H_INTR_ERR_INT_REQ_CNT_MASK GENMASK(17, 0) -#define QDMA_S80_HARD_C2H_INTR_C2H_ST_REQ_ADDR 0xB60 -#define C2H_INTR_C2H_ST_REQ_RSVD_1_MASK GENMASK(31, 18) -#define C2H_INTR_C2H_ST_REQ_CNT_MASK GENMASK(17, 0) -#define QDMA_S80_HARD_C2H_INTR_H2C_ERR_C2H_MM_MSIX_ACK_ADDR 0xB64 -#define C2H_INTR_H2C_ERR_C2H_MM_MSIX_ACK_RSVD_1_MASK GENMASK(31, 18) -#define C2H_INTR_H2C_ERR_C2H_MM_MSIX_ACK_CNT_MASK GENMASK(17, 0) -#define QDMA_S80_HARD_C2H_INTR_H2C_ERR_C2H_MM_MSIX_FAIL_ADDR 0xB68 -#define C2H_INTR_H2C_ERR_C2H_MM_MSIX_FAIL_RSVD_1_MASK GENMASK(31, 18) -#define C2H_INTR_H2C_ERR_C2H_MM_MSIX_FAIL_CNT_MASK GENMASK(17, 0) -#define QDMA_S80_HARD_C2H_INTR_H2C_ERR_C2H_MM_MSIX_NO_MSIX_ADDR 0xB6C -#define C2H_INTR_H2C_ERR_C2H_MM_MSIX_NO_MSIX_RSVD_1_MASK GENMASK(31, 18) -#define C2H_INTR_H2C_ERR_C2H_MM_MSIX_NO_MSIX_CNT_MASK GENMASK(17, 0) -#define QDMA_S80_HARD_C2H_INTR_H2C_ERR_C2H_MM_CTXT_INVAL_ADDR 0xB70 -#define C2H_INTR_H2C_ERR_C2H_MM_CTXT_INVAL_RSVD_1_MASK GENMASK(31, 18) -#define C2H_INTR_H2C_ERR_C2H_MM_CTXT_INVAL_CNT_MASK GENMASK(17, 0) -#define QDMA_S80_HARD_C2H_INTR_C2H_ST_MSIX_ACK_ADDR 0xB74 -#define C2H_INTR_C2H_ST_MSIX_ACK_RSVD_1_MASK GENMASK(31, 18) -#define C2H_INTR_C2H_ST_MSIX_ACK_CNT_MASK GENMASK(17, 0) -#define QDMA_S80_HARD_C2H_INTR_C2H_ST_MSIX_FAIL_ADDR 0xB78 -#define C2H_INTR_C2H_ST_MSIX_FAIL_RSVD_1_MASK GENMASK(31, 18) -#define C2H_INTR_C2H_ST_MSIX_FAIL_CNT_MASK GENMASK(17, 0) -#define QDMA_S80_HARD_C2H_INTR_C2H_ST_NO_MSIX_ADDR 0xB7C -#define C2H_INTR_C2H_ST_NO_MSIX_RSVD_1_MASK GENMASK(31, 18) -#define C2H_INTR_C2H_ST_NO_MSIX_CNT_MASK GENMASK(17, 0) -#define QDMA_S80_HARD_C2H_INTR_C2H_ST_CTXT_INVAL_ADDR 0xB80 -#define C2H_INTR_C2H_ST_CTXT_INVAL_RSVD_1_MASK GENMASK(31, 18) -#define C2H_INTR_C2H_ST_CTXT_INVAL_CNT_MASK GENMASK(17, 0) -#define QDMA_S80_HARD_C2H_STAT_WR_CMP_ADDR 0xB84 -#define C2H_STAT_WR_CMP_RSVD_1_MASK GENMASK(31, 18) -#define C2H_STAT_WR_CMP_CNT_MASK GENMASK(17, 0) -#define QDMA_S80_HARD_C2H_STAT_DBG_DMA_ENG_4_ADDR 0xB88 -#define C2H_STAT_DMA_ENG_4_TUSER_FIFO_OUT_VLD_MASK BIT(31) -#define C2H_STAT_DMA_ENG_4_WRB_FIFO_IN_RDY_MASK BIT(30) -#define C2H_STAT_DMA_ENG_4_TUSER_FIFO_IN_CNT_MASK GENMASK(29, 20) -#define C2H_STAT_DMA_ENG_4_TUSER_FIFO_OUTPUT_CNT_MASK GENMASK(19, 10) -#define C2H_STAT_DMA_ENG_4_TUSER_FIFO_OUT_CNT_MASK GENMASK(9, 0) -#define QDMA_S80_HARD_C2H_STAT_DBG_DMA_ENG_5_ADDR 0xB8C -#define C2H_STAT_DMA_ENG_5_RSVD_1_MASK GENMASK(31, 25) -#define C2H_STAT_DMA_ENG_5_TUSER_COMB_OUT_VLD_MASK BIT(24) -#define C2H_STAT_DMA_ENG_5_TUSER_FIFO_IN_RDY_MASK BIT(23) -#define C2H_STAT_DMA_ENG_5_TUSER_COMB_IN_CNT_MASK GENMASK(22, 13) -#define C2H_STAT_DMA_ENG_5_TUSE_COMB_OUTPUT_CNT_MASK GENMASK(12, 3) -#define C2H_STAT_DMA_ENG_5_TUSER_COMB_CNT_MASK GENMASK(2, 0) -#define QDMA_S80_HARD_C2H_DBG_PFCH_QID_ADDR 0xB90 -#define C2H_PFCH_QID_RSVD_1_MASK GENMASK(31, 15) -#define C2H_PFCH_QID_ERR_CTXT_MASK BIT(14) -#define C2H_PFCH_QID_TARGET_MASK GENMASK(13, 11) -#define C2H_PFCH_QID_QID_OR_TAG_MASK GENMASK(10, 0) -#define QDMA_S80_HARD_C2H_DBG_PFCH_ADDR 0xB94 -#define C2H_PFCH_DATA_MASK GENMASK(31, 0) -#define QDMA_S80_HARD_C2H_INT_DBG_ADDR 0xB98 -#define C2H_INT_RSVD_1_MASK GENMASK(31, 8) -#define C2H_INT_INT_COAL_SM_MASK GENMASK(7, 4) -#define C2H_INT_INT_SM_MASK GENMASK(3, 0) -#define QDMA_S80_HARD_C2H_STAT_IMM_ACCEPTED_ADDR 0xB9C -#define C2H_STAT_IMM_ACCEPTED_RSVD_1_MASK GENMASK(31, 18) -#define C2H_STAT_IMM_ACCEPTED_CNT_MASK GENMASK(17, 0) -#define QDMA_S80_HARD_C2H_STAT_MARKER_ACCEPTED_ADDR 0xBA0 -#define C2H_STAT_MARKER_ACCEPTED_RSVD_1_MASK GENMASK(31, 18) -#define C2H_STAT_MARKER_ACCEPTED_CNT_MASK GENMASK(17, 0) -#define QDMA_S80_HARD_C2H_STAT_DISABLE_CMP_ACCEPTED_ADDR 0xBA4 -#define C2H_STAT_DISABLE_CMP_ACCEPTED_RSVD_1_MASK GENMASK(31, 18) -#define C2H_STAT_DISABLE_CMP_ACCEPTED_CNT_MASK GENMASK(17, 0) -#define QDMA_S80_HARD_C2H_PLD_FIFO_CRDT_CNT_ADDR 0xBA8 -#define C2H_PLD_FIFO_CRDT_CNT_RSVD_1_MASK GENMASK(31, 18) -#define C2H_PLD_FIFO_CRDT_CNT_CNT_MASK GENMASK(17, 0) -#define QDMA_S80_HARD_H2C_ERR_STAT_ADDR 0xE00 -#define H2C_ERR_STAT_RSVD_1_MASK GENMASK(31, 5) -#define H2C_ERR_STAT_SBE_MASK BIT(4) -#define H2C_ERR_STAT_DBE_MASK BIT(3) -#define H2C_ERR_STAT_NO_DMA_DS_MASK BIT(2) -#define H2C_ERR_STAT_SDI_MRKR_REQ_MOP_ERR_MASK BIT(1) -#define H2C_ERR_STAT_ZERO_LEN_DS_MASK BIT(0) -#define QDMA_S80_HARD_H2C_ERR_MASK_ADDR 0xE04 -#define H2C_ERR_EN_MASK GENMASK(31, 0) -#define QDMA_S80_HARD_H2C_FIRST_ERR_QID_ADDR 0xE08 -#define H2C_FIRST_ERR_QID_RSVD_1_MASK GENMASK(31, 20) -#define H2C_FIRST_ERR_QID_ERR_TYPE_MASK GENMASK(19, 16) -#define H2C_FIRST_ERR_QID_RSVD_2_MASK GENMASK(15, 12) -#define H2C_FIRST_ERR_QID_QID_MASK GENMASK(11, 0) -#define QDMA_S80_HARD_H2C_DBG_REG0_ADDR 0xE0C -#define H2C_REG0_NUM_DSC_RCVD_MASK GENMASK(31, 16) -#define H2C_REG0_NUM_WRB_SENT_MASK GENMASK(15, 0) -#define QDMA_S80_HARD_H2C_DBG_REG1_ADDR 0xE10 -#define H2C_REG1_NUM_REQ_SENT_MASK GENMASK(31, 16) -#define H2C_REG1_NUM_CMP_SENT_MASK GENMASK(15, 0) -#define QDMA_S80_HARD_H2C_DBG_REG2_ADDR 0xE14 -#define H2C_REG2_RSVD_1_MASK GENMASK(31, 16) -#define H2C_REG2_NUM_ERR_DSC_RCVD_MASK GENMASK(15, 0) -#define QDMA_S80_HARD_H2C_DBG_REG3_ADDR 0xE18 -#define H2C_REG3_MASK BIT(31) -#define H2C_REG3_DSCO_FIFO_EMPTY_MASK BIT(30) -#define H2C_REG3_DSCO_FIFO_FULL_MASK BIT(29) -#define H2C_REG3_CUR_RC_STATE_MASK GENMASK(28, 26) -#define H2C_REG3_RDREQ_LINES_MASK GENMASK(25, 16) -#define H2C_REG3_RDATA_LINES_AVAIL_MASK GENMASK(15, 6) -#define H2C_REG3_PEND_FIFO_EMPTY_MASK BIT(5) -#define H2C_REG3_PEND_FIFO_FULL_MASK BIT(4) -#define H2C_REG3_CUR_RQ_STATE_MASK GENMASK(3, 2) -#define H2C_REG3_DSCI_FIFO_FULL_MASK BIT(1) -#define H2C_REG3_DSCI_FIFO_EMPTY_MASK BIT(0) -#define QDMA_S80_HARD_H2C_DBG_REG4_ADDR 0xE1C -#define H2C_REG4_RDREQ_ADDR_MASK GENMASK(31, 0) -#define QDMA_S80_HARD_H2C_FATAL_ERR_EN_ADDR 0xE20 -#define H2C_FATAL_ERR_EN_RSVD_1_MASK GENMASK(31, 1) -#define H2C_FATAL_ERR_EN_H2C_MASK BIT(0) -#define QDMA_S80_HARD_C2H_CHANNEL_CTL_ADDR 0x1004 -#define C2H_CHANNEL_CTL_RSVD_1_MASK GENMASK(31, 1) -#define C2H_CHANNEL_CTL_RUN_MASK BIT(0) -#define QDMA_S80_HARD_C2H_CHANNEL_CTL_1_ADDR 0x1008 -#define C2H_CHANNEL_CTL_1_RUN_MASK GENMASK(31, 1) -#define C2H_CHANNEL_CTL_1_RUN_1_MASK BIT(0) -#define QDMA_S80_HARD_C2H_MM_STATUS_ADDR 0x1040 -#define C2H_MM_STATUS_RSVD_1_MASK GENMASK(31, 1) -#define C2H_MM_STATUS_RUN_MASK BIT(0) -#define QDMA_S80_HARD_C2H_CHANNEL_CMPL_DESC_CNT_ADDR 0x1048 -#define C2H_CHANNEL_CMPL_DESC_CNT_C2H_CO_MASK GENMASK(31, 0) -#define QDMA_S80_HARD_C2H_MM_ERR_CODE_ENABLE_MASK_ADDR 0x1054 -#define C2H_MM_ERR_CODE_ENABLE_RSVD_1_MASK BIT(31) -#define C2H_MM_ERR_CODE_ENABLE_WR_UC_RAM_MASK BIT(30) -#define C2H_MM_ERR_CODE_ENABLE_WR_UR_MASK BIT(29) -#define C2H_MM_ERR_CODE_ENABLE_WR_FLR_MASK BIT(28) -#define C2H_MM_ERR_CODE_ENABLE_RSVD_2_MASK GENMASK(27, 2) -#define C2H_MM_ERR_CODE_ENABLE_RD_SLV_ERR_MASK BIT(1) -#define C2H_MM_ERR_CODE_ENABLE_WR_SLV_ERR_MASK BIT(0) -#define QDMA_S80_HARD_C2H_MM_ERR_CODE_ADDR 0x1058 -#define C2H_MM_ERR_CODE_RSVD_1_MASK GENMASK(31, 18) -#define C2H_MM_ERR_CODE_VALID_MASK BIT(17) -#define C2H_MM_ERR_CODE_RDWR_MASK BIT(16) -#define C2H_MM_ERR_CODE_MASK GENMASK(4, 0) -#define QDMA_S80_HARD_C2H_MM_ERR_INFO_ADDR 0x105C -#define C2H_MM_ERR_INFO_RSVD_1_MASK GENMASK(31, 29) -#define C2H_MM_ERR_INFO_QID_MASK GENMASK(28, 17) -#define C2H_MM_ERR_INFO_DIR_MASK BIT(16) -#define C2H_MM_ERR_INFO_CIDX_MASK GENMASK(15, 0) -#define QDMA_S80_HARD_C2H_MM_PERF_MON_CTL_ADDR 0x10C0 -#define C2H_MM_PERF_MON_CTL_RSVD_1_MASK GENMASK(31, 4) -#define C2H_MM_PERF_MON_CTL_IMM_START_MASK BIT(3) -#define C2H_MM_PERF_MON_CTL_RUN_START_MASK BIT(2) -#define C2H_MM_PERF_MON_CTL_IMM_CLEAR_MASK BIT(1) -#define C2H_MM_PERF_MON_CTL_RUN_CLEAR_MASK BIT(0) -#define QDMA_S80_HARD_C2H_MM_PERF_MON_CYCLE_CNT0_ADDR 0x10C4 -#define C2H_MM_PERF_MON_CYCLE_CNT0_CYC_CNT_MASK GENMASK(31, 0) -#define QDMA_S80_HARD_C2H_MM_PERF_MON_CYCLE_CNT1_ADDR 0x10C8 -#define C2H_MM_PERF_MON_CYCLE_CNT1_RSVD_1_MASK GENMASK(31, 10) -#define C2H_MM_PERF_MON_CYCLE_CNT1_CYC_CNT_MASK GENMASK(9, 0) -#define QDMA_S80_HARD_C2H_MM_PERF_MON_DATA_CNT0_ADDR 0x10CC -#define C2H_MM_PERF_MON_DATA_CNT0_DCNT_MASK GENMASK(31, 0) -#define QDMA_S80_HARD_C2H_MM_PERF_MON_DATA_CNT1_ADDR 0x10D0 -#define C2H_MM_PERF_MON_DATA_CNT1_RSVD_1_MASK GENMASK(31, 10) -#define C2H_MM_PERF_MON_DATA_CNT1_DCNT_MASK GENMASK(9, 0) -#define QDMA_S80_HARD_C2H_MM_DBG_ADDR 0x10E8 -#define C2H_MM_RSVD_1_MASK GENMASK(31, 24) -#define C2H_MM_RRQ_ENTRIES_MASK GENMASK(23, 17) -#define C2H_MM_DAT_FIFO_SPC_MASK GENMASK(16, 7) -#define C2H_MM_RD_STALL_MASK BIT(6) -#define C2H_MM_RRQ_FIFO_FI_MASK BIT(5) -#define C2H_MM_WR_STALL_MASK BIT(4) -#define C2H_MM_WRQ_FIFO_FI_MASK BIT(3) -#define C2H_MM_WBK_STALL_MASK BIT(2) -#define C2H_MM_DSC_FIFO_EP_MASK BIT(1) -#define C2H_MM_DSC_FIFO_FL_MASK BIT(0) -#define QDMA_S80_HARD_H2C_CHANNEL_CTL_ADDR 0x1204 -#define H2C_CHANNEL_CTL_RSVD_1_MASK GENMASK(31, 1) -#define H2C_CHANNEL_CTL_RUN_MASK BIT(0) -#define QDMA_S80_HARD_H2C_CHANNEL_CTL_1_ADDR 0x1208 -#define H2C_CHANNEL_CTL_1_RUN_MASK BIT(0) -#define QDMA_S80_HARD_H2C_CHANNEL_CTL_2_ADDR 0x120C -#define H2C_CHANNEL_CTL_2_RUN_MASK BIT(0) -#define QDMA_S80_HARD_H2C_MM_STATUS_ADDR 0x1240 -#define H2C_MM_STATUS_RSVD_1_MASK GENMASK(31, 1) -#define H2C_MM_STATUS_RUN_MASK BIT(0) -#define QDMA_S80_HARD_H2C_CHANNEL_CMPL_DESC_CNT_ADDR 0x1248 -#define H2C_CHANNEL_CMPL_DESC_CNT_H2C_CO_MASK GENMASK(31, 0) -#define QDMA_S80_HARD_H2C_MM_ERR_CODE_ENABLE_MASK_ADDR 0x1254 -#define H2C_MM_ERR_CODE_ENABLE_RSVD_1_MASK GENMASK(31, 30) -#define H2C_MM_ERR_CODE_ENABLE_WR_SLV_ERR_MASK BIT(29) -#define H2C_MM_ERR_CODE_ENABLE_WR_DEC_ERR_MASK BIT(28) -#define H2C_MM_ERR_CODE_ENABLE_RSVD_2_MASK GENMASK(27, 23) -#define H2C_MM_ERR_CODE_ENABLE_RD_RQ_DIS_ERR_MASK BIT(22) -#define H2C_MM_ERR_CODE_ENABLE_RSVD_3_MASK GENMASK(21, 17) -#define H2C_MM_ERR_CODE_ENABLE_RD_DAT_POISON_ERR_MASK BIT(16) -#define H2C_MM_ERR_CODE_ENABLE_RSVD_4_MASK GENMASK(15, 9) -#define H2C_MM_ERR_CODE_ENABLE_RD_FLR_ERR_MASK BIT(8) -#define H2C_MM_ERR_CODE_ENABLE_RSVD_5_MASK GENMASK(7, 6) -#define H2C_MM_ERR_CODE_ENABLE_RD_HDR_ADR_ERR_MASK BIT(5) -#define H2C_MM_ERR_CODE_ENABLE_RD_HDR_PARA_MASK BIT(4) -#define H2C_MM_ERR_CODE_ENABLE_RD_HDR_BYTE_ERR_MASK BIT(3) -#define H2C_MM_ERR_CODE_ENABLE_RD_UR_CA_MASK BIT(2) -#define H2C_MM_ERR_CODE_ENABLE_RD_HRD_POISON_ERR_MASK BIT(1) -#define H2C_MM_ERR_CODE_ENABLE_RSVD_6_MASK BIT(0) -#define QDMA_S80_HARD_H2C_MM_ERR_CODE_ADDR 0x1258 -#define H2C_MM_ERR_CODE_RSVD_1_MASK GENMASK(31, 18) -#define H2C_MM_ERR_CODE_VALID_MASK BIT(17) -#define H2C_MM_ERR_CODE_RDWR_MASK BIT(16) -#define H2C_MM_ERR_CODE_MASK GENMASK(4, 0) -#define QDMA_S80_HARD_H2C_MM_ERR_INFO_ADDR 0x125C -#define H2C_MM_ERR_INFO_RSVD_1_MASK GENMASK(31, 29) -#define H2C_MM_ERR_INFO_QID_MASK GENMASK(28, 17) -#define H2C_MM_ERR_INFO_DIR_MASK BIT(16) -#define H2C_MM_ERR_INFO_CIDX_MASK GENMASK(15, 0) -#define QDMA_S80_HARD_H2C_MM_PERF_MON_CTL_ADDR 0x12C0 -#define H2C_MM_PERF_MON_CTL_RSVD_1_MASK GENMASK(31, 4) -#define H2C_MM_PERF_MON_CTL_IMM_START_MASK BIT(3) -#define H2C_MM_PERF_MON_CTL_RUN_START_MASK BIT(2) -#define H2C_MM_PERF_MON_CTL_IMM_CLEAR_MASK BIT(1) -#define H2C_MM_PERF_MON_CTL_RUN_CLEAR_MASK BIT(0) -#define QDMA_S80_HARD_H2C_MM_PERF_MON_CYCLE_CNT0_ADDR 0x12C4 -#define H2C_MM_PERF_MON_CYCLE_CNT0_CYC_CNT_MASK GENMASK(31, 0) -#define QDMA_S80_HARD_H2C_MM_PERF_MON_CYCLE_CNT1_ADDR 0x12C8 -#define H2C_MM_PERF_MON_CYCLE_CNT1_RSVD_1_MASK GENMASK(31, 10) -#define H2C_MM_PERF_MON_CYCLE_CNT1_CYC_CNT_MASK GENMASK(9, 0) -#define QDMA_S80_HARD_H2C_MM_PERF_MON_DATA_CNT0_ADDR 0x12CC -#define H2C_MM_PERF_MON_DATA_CNT0_DCNT_MASK GENMASK(31, 0) -#define QDMA_S80_HARD_H2C_MM_PERF_MON_DATA_CNT1_ADDR 0x12D0 -#define H2C_MM_PERF_MON_DATA_CNT1_RSVD_1_MASK GENMASK(31, 10) -#define H2C_MM_PERF_MON_DATA_CNT1_DCNT_MASK GENMASK(9, 0) -#define QDMA_S80_HARD_H2C_MM_DBG_ADDR 0x12E8 -#define H2C_MM_RSVD_1_MASK GENMASK(31, 24) -#define H2C_MM_RRQ_ENTRIES_MASK GENMASK(23, 17) -#define H2C_MM_DAT_FIFO_SPC_MASK GENMASK(16, 7) -#define H2C_MM_RD_STALL_MASK BIT(6) -#define H2C_MM_RRQ_FIFO_FI_MASK BIT(5) -#define H2C_MM_WR_STALL_MASK BIT(4) -#define H2C_MM_WRQ_FIFO_FI_MASK BIT(3) -#define H2C_MM_WBK_STALL_MASK BIT(2) -#define H2C_MM_DSC_FIFO_EP_MASK BIT(1) -#define H2C_MM_DSC_FIFO_FL_MASK BIT(0) -#define QDMA_S80_HARD_FUNC_STATUS_REG_ADDR 0x2400 -#define FUNC_STATUS_REG_RSVD_1_MASK GENMASK(31, 12) -#define FUNC_STATUS_REG_CUR_SRC_FN_MASK GENMASK(11, 4) -#define FUNC_STATUS_REG_ACK_MASK BIT(2) -#define FUNC_STATUS_REG_O_MSG_MASK BIT(1) -#define FUNC_STATUS_REG_I_MSG_MASK BIT(0) -#define QDMA_S80_HARD_FUNC_CMD_REG_ADDR 0x2404 -#define FUNC_CMD_REG_RSVD_1_MASK GENMASK(31, 3) -#define FUNC_CMD_REG_RSVD_2_MASK BIT(2) -#define FUNC_CMD_REG_MSG_RCV_MASK BIT(1) -#define FUNC_CMD_REG_MSG_SENT_MASK BIT(0) -#define QDMA_S80_HARD_FUNC_INTERRUPT_VECTOR_REG_ADDR 0x2408 -#define FUNC_INTERRUPT_VECTOR_REG_RSVD_1_MASK GENMASK(31, 5) -#define FUNC_INTERRUPT_VECTOR_REG_IN_MASK GENMASK(4, 0) -#define QDMA_S80_HARD_TARGET_FUNC_REG_ADDR 0x240C -#define TARGET_FUNC_REG_RSVD_1_MASK GENMASK(31, 8) -#define TARGET_FUNC_REG_N_ID_MASK GENMASK(7, 0) -#define QDMA_S80_HARD_FUNC_INTERRUPT_CTL_REG_ADDR 0x2410 -#define FUNC_INTERRUPT_CTL_REG_RSVD_1_MASK GENMASK(31, 1) -#define FUNC_INTERRUPT_CTL_REG_INT_EN_MASK BIT(0) -#define SW_IND_CTXT_DATA_W3_DSC_BASE_H_MASK GENMASK(31, 0) -#define SW_IND_CTXT_DATA_W2_DSC_BASE_L_MASK GENMASK(31, 0) -#define SW_IND_CTXT_DATA_W1_IS_MM_MASK BIT(31) -#define SW_IND_CTXT_DATA_W1_MRKR_DIS_MASK BIT(30) -#define SW_IND_CTXT_DATA_W1_IRQ_REQ_MASK BIT(29) -#define SW_IND_CTXT_DATA_W1_ERR_WB_SENT_MASK BIT(28) -#define SW_IND_CTXT_DATA_W1_ERR_MASK GENMASK(27, 26) -#define SW_IND_CTXT_DATA_W1_IRQ_NO_LAST_MASK BIT(25) -#define SW_IND_CTXT_DATA_W1_PORT_ID_MASK GENMASK(24, 22) -#define SW_IND_CTXT_DATA_W1_IRQ_EN_MASK BIT(21) -#define SW_IND_CTXT_DATA_W1_WBK_EN_MASK BIT(20) -#define SW_IND_CTXT_DATA_W1_MM_CHN_MASK BIT(19) -#define SW_IND_CTXT_DATA_W1_BYPASS_MASK BIT(18) -#define SW_IND_CTXT_DATA_W1_DSC_SZ_MASK GENMASK(17, 16) -#define SW_IND_CTXT_DATA_W1_RNG_SZ_MASK GENMASK(15, 12) -#define SW_IND_CTXT_DATA_W1_FNC_ID_MASK GENMASK(11, 4) -#define SW_IND_CTXT_DATA_W1_WBI_INTVL_EN_MASK BIT(3) -#define SW_IND_CTXT_DATA_W1_WBI_CHK_MASK BIT(2) -#define SW_IND_CTXT_DATA_W1_FCRD_EN_MASK BIT(1) -#define SW_IND_CTXT_DATA_W1_QEN_MASK BIT(0) -#define SW_IND_CTXT_DATA_W0_RSV_MASK GENMASK(31, 17) -#define SW_IND_CTXT_DATA_W0_IRQ_ARM_MASK BIT(16) -#define SW_IND_CTXT_DATA_W0_PIDX_MASK GENMASK(15, 0) -#define HW_IND_CTXT_DATA_W1_RSVD_MASK GENMASK(15, 11) -#define HW_IND_CTXT_DATA_W1_FETCH_PND_MASK BIT(10) -#define HW_IND_CTXT_DATA_W1_IDL_STP_B_MASK BIT(9) -#define HW_IND_CTXT_DATA_W1_DSC_PND_MASK BIT(8) -#define HW_IND_CTXT_DATA_W1_RSVD_1_MASK GENMASK(7, 0) -#define HW_IND_CTXT_DATA_W0_CRD_USE_MASK GENMASK(31, 16) -#define HW_IND_CTXT_DATA_W0_CIDX_MASK GENMASK(15, 0) -#define CRED_CTXT_DATA_W0_RSVD_1_MASK GENMASK(31, 16) -#define CRED_CTXT_DATA_W0_CREDT_MASK GENMASK(15, 0) -#define PREFETCH_CTXT_DATA_W1_VALID_MASK BIT(13) -#define PREFETCH_CTXT_DATA_W1_SW_CRDT_H_MASK GENMASK(12, 0) -#define PREFETCH_CTXT_DATA_W0_SW_CRDT_L_MASK GENMASK(31, 29) -#define PREFETCH_CTXT_DATA_W0_PFCH_MASK BIT(28) -#define PREFETCH_CTXT_DATA_W0_PFCH_EN_MASK BIT(27) -#define PREFETCH_CTXT_DATA_W0_ERR_MASK BIT(26) -#define PREFETCH_CTXT_DATA_W0_RSVD_MASK GENMASK(25, 8) -#define PREFETCH_CTXT_DATA_W0_PORT_ID_MASK GENMASK(7, 5) -#define PREFETCH_CTXT_DATA_W0_BUF_SIZE_IDX_MASK GENMASK(4, 1) -#define PREFETCH_CTXT_DATA_W0_BYPASS_MASK BIT(0) -#define CMPL_CTXT_DATA_W3_RSVD_MASK GENMASK(31, 30) -#define CMPL_CTXT_DATA_W3_FULL_UPD_MASK BIT(29) -#define CMPL_CTXT_DATA_W3_TIMER_RUNNING_MASK BIT(28) -#define CMPL_CTXT_DATA_W3_USER_TRIG_PEND_MASK BIT(27) -#define CMPL_CTXT_DATA_W3_ERR_MASK GENMASK(26, 25) -#define CMPL_CTXT_DATA_W3_VALID_MASK BIT(24) -#define CMPL_CTXT_DATA_W3_CIDX_MASK GENMASK(23, 8) -#define CMPL_CTXT_DATA_W3_PIDX_H_MASK GENMASK(7, 0) -#define CMPL_CTXT_DATA_W2_PIDX_L_MASK GENMASK(31, 24) -#define CMPL_CTXT_DATA_W2_DESC_SIZE_MASK GENMASK(23, 22) -#define CMPL_CTXT_DATA_W2_BADDR_64_H_MASK GENMASK(21, 0) -#define CMPL_CTXT_DATA_W1_BADDR_64_M_MASK GENMASK(31, 0) -#define CMPL_CTXT_DATA_W0_BADDR_64_L_MASK GENMASK(31, 28) -#define CMPL_CTXT_DATA_W0_QSIZE_IDX_MASK GENMASK(27, 24) -#define CMPL_CTXT_DATA_W0_COLOR_MASK BIT(23) -#define CMPL_CTXT_DATA_W0_INT_ST_MASK GENMASK(22, 21) -#define CMPL_CTXT_DATA_W0_TIMER_IDX_MASK GENMASK(20, 17) -#define CMPL_CTXT_DATA_W0_CNTER_IDX_MASK GENMASK(16, 13) -#define CMPL_CTXT_DATA_W0_FNC_ID_MASK GENMASK(12, 5) -#define CMPL_CTXT_DATA_W0_TRIG_MODE_MASK GENMASK(4, 2) -#define CMPL_CTXT_DATA_W0_EN_INT_MASK BIT(1) -#define CMPL_CTXT_DATA_W0_EN_STAT_DESC_MASK BIT(0) -#define INTR_CTXT_DATA_W2_PIDX_MASK GENMASK(11, 0) -#define INTR_CTXT_DATA_W1_PAGE_SIZE_MASK GENMASK(31, 29) -#define INTR_CTXT_DATA_W1_BADDR_4K_H_MASK GENMASK(28, 0) -#define INTR_CTXT_DATA_W0_BADDR_4K_L_MASK GENMASK(31, 9) -#define INTR_CTXT_DATA_W0_COLOR_MASK BIT(8) -#define INTR_CTXT_DATA_W0_INT_ST_MASK BIT(7) -#define INTR_CTXT_DATA_W0_RSVD_MASK BIT(6) -#define INTR_CTXT_DATA_W0_VEC_MASK GENMASK(5, 1) -#define INTR_CTXT_DATA_W0_VALID_MASK BIT(0) - -#ifdef __cplusplus -} -#endif - -#endif - diff --git a/QDMA/windows/sys/libqdma/source/qdma_access/qdma_s80_hard_access/qdma_s80_hard_reg_dump.c b/QDMA/windows/sys/libqdma/source/qdma_access/qdma_s80_hard_access/qdma_s80_hard_reg_dump.c deleted file mode 100644 index 1f367326d..000000000 --- a/QDMA/windows/sys/libqdma/source/qdma_access/qdma_s80_hard_access/qdma_s80_hard_reg_dump.c +++ /dev/null @@ -1,8013 +0,0 @@ -/* - * Copyright (C) 2020 Xilinx, Inc - * - * Licensed under the Apache License, Version 2.0 (the "License"). You may - * not use this file except in compliance with the License. You may obtain - * a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - */ - - -#include "qdma_s80_hard_reg.h" -#include "qdma_reg_dump.h" - -#ifdef ENABLE_WPP_TRACING -#include "qdma_s80_hard_reg_dump.tmh" -#endif - - -static struct regfield_info - cfg_blk_identifier_field_info[] = { - {"CFG_BLK_IDENTIFIER", - CFG_BLK_IDENTIFIER_MASK}, - {"CFG_BLK_IDENTIFIER_1", - CFG_BLK_IDENTIFIER_1_MASK}, - {"CFG_BLK_IDENTIFIER_RSVD_1", - CFG_BLK_IDENTIFIER_RSVD_1_MASK}, - {"CFG_BLK_IDENTIFIER_VERSION", - CFG_BLK_IDENTIFIER_VERSION_MASK}, -}; - - -static struct regfield_info - cfg_blk_busdev_field_info[] = { - {"CFG_BLK_BUSDEV_BDF", - CFG_BLK_BUSDEV_BDF_MASK}, -}; - - -static struct regfield_info - cfg_blk_pcie_max_pld_size_field_info[] = { - {"CFG_BLK_PCIE_MAX_PLD_SIZE", - CFG_BLK_PCIE_MAX_PLD_SIZE_MASK}, -}; - - -static struct regfield_info - cfg_blk_pcie_max_read_req_size_field_info[] = { - {"CFG_BLK_PCIE_MAX_READ_REQ_SIZE", - CFG_BLK_PCIE_MAX_READ_REQ_SIZE_MASK}, -}; - - -static struct regfield_info - cfg_blk_system_id_field_info[] = { - {"CFG_BLK_SYSTEM_ID", - CFG_BLK_SYSTEM_ID_MASK}, -}; - - -static struct regfield_info - cfg_blk_msi_enable_field_info[] = { - {"CFG_BLK_MSI_ENABLE_3", - CFG_BLK_MSI_ENABLE_3_MASK}, - {"CFG_BLK_MSI_ENABLE_MSIX3", - CFG_BLK_MSI_ENABLE_MSIX3_MASK}, - {"CFG_BLK_MSI_ENABLE_2", - CFG_BLK_MSI_ENABLE_2_MASK}, - {"CFG_BLK_MSI_ENABLE_MSIX2", - CFG_BLK_MSI_ENABLE_MSIX2_MASK}, - {"CFG_BLK_MSI_ENABLE_1", - CFG_BLK_MSI_ENABLE_1_MASK}, - {"CFG_BLK_MSI_ENABLE_MSIX1", - CFG_BLK_MSI_ENABLE_MSIX1_MASK}, - {"CFG_BLK_MSI_ENABLE_0", - CFG_BLK_MSI_ENABLE_0_MASK}, - {"CFG_BLK_MSI_ENABLE_MSIX0", - CFG_BLK_MSI_ENABLE_MSIX0_MASK}, -}; - - -static struct regfield_info - cfg_pcie_data_width_field_info[] = { - {"CFG_PCIE_DATA_WIDTH_DATAPATH", - CFG_PCIE_DATA_WIDTH_DATAPATH_MASK}, -}; - - -static struct regfield_info - cfg_pcie_ctl_field_info[] = { - {"CFG_PCIE_CTL_RRQ_DISABLE", - CFG_PCIE_CTL_RRQ_DISABLE_MASK}, - {"CFG_PCIE_CTL_RELAXED_ORDERING", - CFG_PCIE_CTL_RELAXED_ORDERING_MASK}, -}; - - -static struct regfield_info - cfg_axi_user_max_pld_size_field_info[] = { - {"CFG_AXI_USER_MAX_PLD_SIZE_ISSUED", - CFG_AXI_USER_MAX_PLD_SIZE_ISSUED_MASK}, - {"CFG_AXI_USER_MAX_PLD_SIZE_PROG", - CFG_AXI_USER_MAX_PLD_SIZE_PROG_MASK}, -}; - - -static struct regfield_info - cfg_axi_user_max_read_req_size_field_info[] = { - {"CFG_AXI_USER_MAX_READ_REQ_SIZE_USISSUED", - CFG_AXI_USER_MAX_READ_REQ_SIZE_USISSUED_MASK}, - {"CFG_AXI_USER_MAX_READ_REQ_SIZE_USPROG", - CFG_AXI_USER_MAX_READ_REQ_SIZE_USPROG_MASK}, -}; - - -static struct regfield_info - cfg_blk_misc_ctl_field_info[] = { - {"CFG_BLK_MISC_CTL_NUM_TAG", - CFG_BLK_MISC_CTL_NUM_TAG_MASK}, - {"CFG_BLK_MISC_CTL_RQ_METERING_MULTIPLIER", - CFG_BLK_MISC_CTL_RQ_METERING_MULTIPLIER_MASK}, -}; - - -static struct regfield_info - cfg_blk_scratch_0_field_info[] = { - {"CFG_BLK_SCRATCH_0", - CFG_BLK_SCRATCH_0_MASK}, -}; - - -static struct regfield_info - cfg_blk_scratch_1_field_info[] = { - {"CFG_BLK_SCRATCH_1", - CFG_BLK_SCRATCH_1_MASK}, -}; - - -static struct regfield_info - cfg_blk_scratch_2_field_info[] = { - {"CFG_BLK_SCRATCH_2", - CFG_BLK_SCRATCH_2_MASK}, -}; - - -static struct regfield_info - cfg_blk_scratch_3_field_info[] = { - {"CFG_BLK_SCRATCH_3", - CFG_BLK_SCRATCH_3_MASK}, -}; - - -static struct regfield_info - cfg_blk_scratch_4_field_info[] = { - {"CFG_BLK_SCRATCH_4", - CFG_BLK_SCRATCH_4_MASK}, -}; - - -static struct regfield_info - cfg_blk_scratch_5_field_info[] = { - {"CFG_BLK_SCRATCH_5", - CFG_BLK_SCRATCH_5_MASK}, -}; - - -static struct regfield_info - cfg_blk_scratch_6_field_info[] = { - {"CFG_BLK_SCRATCH_6", - CFG_BLK_SCRATCH_6_MASK}, -}; - - -static struct regfield_info - cfg_blk_scratch_7_field_info[] = { - {"CFG_BLK_SCRATCH_7", - CFG_BLK_SCRATCH_7_MASK}, -}; - - -static struct regfield_info - ram_sbe_msk_a_field_info[] = { - {"RAM_SBE_MSK_A", - RAM_SBE_MSK_A_MASK}, -}; - - -static struct regfield_info - ram_sbe_sts_a_field_info[] = { - {"RAM_SBE_STS_A_RSVD_1", - RAM_SBE_STS_A_RSVD_1_MASK}, - {"RAM_SBE_STS_A_PFCH_LL_RAM", - RAM_SBE_STS_A_PFCH_LL_RAM_MASK}, - {"RAM_SBE_STS_A_WRB_CTXT_RAM", - RAM_SBE_STS_A_WRB_CTXT_RAM_MASK}, - {"RAM_SBE_STS_A_PFCH_CTXT_RAM", - RAM_SBE_STS_A_PFCH_CTXT_RAM_MASK}, - {"RAM_SBE_STS_A_DESC_REQ_FIFO_RAM", - RAM_SBE_STS_A_DESC_REQ_FIFO_RAM_MASK}, - {"RAM_SBE_STS_A_INT_CTXT_RAM", - RAM_SBE_STS_A_INT_CTXT_RAM_MASK}, - {"RAM_SBE_STS_A_INT_QID2VEC_RAM", - RAM_SBE_STS_A_INT_QID2VEC_RAM_MASK}, - {"RAM_SBE_STS_A_WRB_COAL_DATA_RAM", - RAM_SBE_STS_A_WRB_COAL_DATA_RAM_MASK}, - {"RAM_SBE_STS_A_TUSER_FIFO_RAM", - RAM_SBE_STS_A_TUSER_FIFO_RAM_MASK}, - {"RAM_SBE_STS_A_QID_FIFO_RAM", - RAM_SBE_STS_A_QID_FIFO_RAM_MASK}, - {"RAM_SBE_STS_A_PLD_FIFO_RAM", - RAM_SBE_STS_A_PLD_FIFO_RAM_MASK}, - {"RAM_SBE_STS_A_TIMER_FIFO_RAM", - RAM_SBE_STS_A_TIMER_FIFO_RAM_MASK}, - {"RAM_SBE_STS_A_PASID_CTXT_RAM", - RAM_SBE_STS_A_PASID_CTXT_RAM_MASK}, - {"RAM_SBE_STS_A_DSC_CPLD", - RAM_SBE_STS_A_DSC_CPLD_MASK}, - {"RAM_SBE_STS_A_DSC_CPLI", - RAM_SBE_STS_A_DSC_CPLI_MASK}, - {"RAM_SBE_STS_A_DSC_SW_CTXT", - RAM_SBE_STS_A_DSC_SW_CTXT_MASK}, - {"RAM_SBE_STS_A_DSC_CRD_RCV", - RAM_SBE_STS_A_DSC_CRD_RCV_MASK}, - {"RAM_SBE_STS_A_DSC_HW_CTXT", - RAM_SBE_STS_A_DSC_HW_CTXT_MASK}, - {"RAM_SBE_STS_A_FUNC_MAP", - RAM_SBE_STS_A_FUNC_MAP_MASK}, - {"RAM_SBE_STS_A_C2H_WR_BRG_DAT", - RAM_SBE_STS_A_C2H_WR_BRG_DAT_MASK}, - {"RAM_SBE_STS_A_C2H_RD_BRG_DAT", - RAM_SBE_STS_A_C2H_RD_BRG_DAT_MASK}, - {"RAM_SBE_STS_A_H2C_WR_BRG_DAT", - RAM_SBE_STS_A_H2C_WR_BRG_DAT_MASK}, - {"RAM_SBE_STS_A_H2C_RD_BRG_DAT", - RAM_SBE_STS_A_H2C_RD_BRG_DAT_MASK}, - {"RAM_SBE_STS_A_RSVD_2", - RAM_SBE_STS_A_RSVD_2_MASK}, - {"RAM_SBE_STS_A_MI_C2H0_DAT", - RAM_SBE_STS_A_MI_C2H0_DAT_MASK}, - {"RAM_SBE_STS_A_RSVD_3", - RAM_SBE_STS_A_RSVD_3_MASK}, - {"RAM_SBE_STS_A_MI_H2C0_DAT", - RAM_SBE_STS_A_MI_H2C0_DAT_MASK}, -}; - - -static struct regfield_info - ram_dbe_msk_a_field_info[] = { - {"RAM_DBE_MSK_A", - RAM_DBE_MSK_A_MASK}, -}; - - -static struct regfield_info - ram_dbe_sts_a_field_info[] = { - {"RAM_DBE_STS_A_RSVD_1", - RAM_DBE_STS_A_RSVD_1_MASK}, - {"RAM_DBE_STS_A_PFCH_LL_RAM", - RAM_DBE_STS_A_PFCH_LL_RAM_MASK}, - {"RAM_DBE_STS_A_WRB_CTXT_RAM", - RAM_DBE_STS_A_WRB_CTXT_RAM_MASK}, - {"RAM_DBE_STS_A_PFCH_CTXT_RAM", - RAM_DBE_STS_A_PFCH_CTXT_RAM_MASK}, - {"RAM_DBE_STS_A_DESC_REQ_FIFO_RAM", - RAM_DBE_STS_A_DESC_REQ_FIFO_RAM_MASK}, - {"RAM_DBE_STS_A_INT_CTXT_RAM", - RAM_DBE_STS_A_INT_CTXT_RAM_MASK}, - {"RAM_DBE_STS_A_INT_QID2VEC_RAM", - RAM_DBE_STS_A_INT_QID2VEC_RAM_MASK}, - {"RAM_DBE_STS_A_WRB_COAL_DATA_RAM", - RAM_DBE_STS_A_WRB_COAL_DATA_RAM_MASK}, - {"RAM_DBE_STS_A_TUSER_FIFO_RAM", - RAM_DBE_STS_A_TUSER_FIFO_RAM_MASK}, - {"RAM_DBE_STS_A_QID_FIFO_RAM", - RAM_DBE_STS_A_QID_FIFO_RAM_MASK}, - {"RAM_DBE_STS_A_PLD_FIFO_RAM", - RAM_DBE_STS_A_PLD_FIFO_RAM_MASK}, - {"RAM_DBE_STS_A_TIMER_FIFO_RAM", - RAM_DBE_STS_A_TIMER_FIFO_RAM_MASK}, - {"RAM_DBE_STS_A_PASID_CTXT_RAM", - RAM_DBE_STS_A_PASID_CTXT_RAM_MASK}, - {"RAM_DBE_STS_A_DSC_CPLD", - RAM_DBE_STS_A_DSC_CPLD_MASK}, - {"RAM_DBE_STS_A_DSC_CPLI", - RAM_DBE_STS_A_DSC_CPLI_MASK}, - {"RAM_DBE_STS_A_DSC_SW_CTXT", - RAM_DBE_STS_A_DSC_SW_CTXT_MASK}, - {"RAM_DBE_STS_A_DSC_CRD_RCV", - RAM_DBE_STS_A_DSC_CRD_RCV_MASK}, - {"RAM_DBE_STS_A_DSC_HW_CTXT", - RAM_DBE_STS_A_DSC_HW_CTXT_MASK}, - {"RAM_DBE_STS_A_FUNC_MAP", - RAM_DBE_STS_A_FUNC_MAP_MASK}, - {"RAM_DBE_STS_A_C2H_WR_BRG_DAT", - RAM_DBE_STS_A_C2H_WR_BRG_DAT_MASK}, - {"RAM_DBE_STS_A_C2H_RD_BRG_DAT", - RAM_DBE_STS_A_C2H_RD_BRG_DAT_MASK}, - {"RAM_DBE_STS_A_H2C_WR_BRG_DAT", - RAM_DBE_STS_A_H2C_WR_BRG_DAT_MASK}, - {"RAM_DBE_STS_A_H2C_RD_BRG_DAT", - RAM_DBE_STS_A_H2C_RD_BRG_DAT_MASK}, - {"RAM_DBE_STS_A_RSVD_2", - RAM_DBE_STS_A_RSVD_2_MASK}, - {"RAM_DBE_STS_A_MI_C2H0_DAT", - RAM_DBE_STS_A_MI_C2H0_DAT_MASK}, - {"RAM_DBE_STS_A_RSVD_3", - RAM_DBE_STS_A_RSVD_3_MASK}, - {"RAM_DBE_STS_A_MI_H2C0_DAT", - RAM_DBE_STS_A_MI_H2C0_DAT_MASK}, -}; - - -static struct regfield_info - glbl2_identifier_field_info[] = { - {"GLBL2_IDENTIFIER", - GLBL2_IDENTIFIER_MASK}, - {"GLBL2_IDENTIFIER_VERSION", - GLBL2_IDENTIFIER_VERSION_MASK}, -}; - - -static struct regfield_info - glbl2_pf_barlite_int_field_info[] = { - {"GLBL2_PF_BARLITE_INT_PF3_BAR_MAP", - GLBL2_PF_BARLITE_INT_PF3_BAR_MAP_MASK}, - {"GLBL2_PF_BARLITE_INT_PF2_BAR_MAP", - GLBL2_PF_BARLITE_INT_PF2_BAR_MAP_MASK}, - {"GLBL2_PF_BARLITE_INT_PF1_BAR_MAP", - GLBL2_PF_BARLITE_INT_PF1_BAR_MAP_MASK}, - {"GLBL2_PF_BARLITE_INT_PF0_BAR_MAP", - GLBL2_PF_BARLITE_INT_PF0_BAR_MAP_MASK}, -}; - - -static struct regfield_info - glbl2_pf_vf_barlite_int_field_info[] = { - {"GLBL2_PF_VF_BARLITE_INT_PF3_MAP", - GLBL2_PF_VF_BARLITE_INT_PF3_MAP_MASK}, - {"GLBL2_PF_VF_BARLITE_INT_PF2_MAP", - GLBL2_PF_VF_BARLITE_INT_PF2_MAP_MASK}, - {"GLBL2_PF_VF_BARLITE_INT_PF1_MAP", - GLBL2_PF_VF_BARLITE_INT_PF1_MAP_MASK}, - {"GLBL2_PF_VF_BARLITE_INT_PF0_MAP", - GLBL2_PF_VF_BARLITE_INT_PF0_MAP_MASK}, -}; - - -static struct regfield_info - glbl2_pf_barlite_ext_field_info[] = { - {"GLBL2_PF_BARLITE_EXT_PF3_BAR_MAP", - GLBL2_PF_BARLITE_EXT_PF3_BAR_MAP_MASK}, - {"GLBL2_PF_BARLITE_EXT_PF2_BAR_MAP", - GLBL2_PF_BARLITE_EXT_PF2_BAR_MAP_MASK}, - {"GLBL2_PF_BARLITE_EXT_PF1_BAR_MAP", - GLBL2_PF_BARLITE_EXT_PF1_BAR_MAP_MASK}, - {"GLBL2_PF_BARLITE_EXT_PF0_BAR_MAP", - GLBL2_PF_BARLITE_EXT_PF0_BAR_MAP_MASK}, -}; - - -static struct regfield_info - glbl2_pf_vf_barlite_ext_field_info[] = { - {"GLBL2_PF_VF_BARLITE_EXT_PF3_MAP", - GLBL2_PF_VF_BARLITE_EXT_PF3_MAP_MASK}, - {"GLBL2_PF_VF_BARLITE_EXT_PF2_MAP", - GLBL2_PF_VF_BARLITE_EXT_PF2_MAP_MASK}, - {"GLBL2_PF_VF_BARLITE_EXT_PF1_MAP", - GLBL2_PF_VF_BARLITE_EXT_PF1_MAP_MASK}, - {"GLBL2_PF_VF_BARLITE_EXT_PF0_MAP", - GLBL2_PF_VF_BARLITE_EXT_PF0_MAP_MASK}, -}; - - -static struct regfield_info - glbl2_channel_inst_field_info[] = { - {"GLBL2_CHANNEL_INST_RSVD_1", - GLBL2_CHANNEL_INST_RSVD_1_MASK}, - {"GLBL2_CHANNEL_INST_C2H_ST", - GLBL2_CHANNEL_INST_C2H_ST_MASK}, - {"GLBL2_CHANNEL_INST_H2C_ST", - GLBL2_CHANNEL_INST_H2C_ST_MASK}, - {"GLBL2_CHANNEL_INST_RSVD_2", - GLBL2_CHANNEL_INST_RSVD_2_MASK}, - {"GLBL2_CHANNEL_INST_C2H_ENG", - GLBL2_CHANNEL_INST_C2H_ENG_MASK}, - {"GLBL2_CHANNEL_INST_RSVD_3", - GLBL2_CHANNEL_INST_RSVD_3_MASK}, - {"GLBL2_CHANNEL_INST_H2C_ENG", - GLBL2_CHANNEL_INST_H2C_ENG_MASK}, -}; - - -static struct regfield_info - glbl2_channel_mdma_field_info[] = { - {"GLBL2_CHANNEL_MDMA_RSVD_1", - GLBL2_CHANNEL_MDMA_RSVD_1_MASK}, - {"GLBL2_CHANNEL_MDMA_C2H_ST", - GLBL2_CHANNEL_MDMA_C2H_ST_MASK}, - {"GLBL2_CHANNEL_MDMA_H2C_ST", - GLBL2_CHANNEL_MDMA_H2C_ST_MASK}, - {"GLBL2_CHANNEL_MDMA_RSVD_2", - GLBL2_CHANNEL_MDMA_RSVD_2_MASK}, - {"GLBL2_CHANNEL_MDMA_C2H_ENG", - GLBL2_CHANNEL_MDMA_C2H_ENG_MASK}, - {"GLBL2_CHANNEL_MDMA_RSVD_3", - GLBL2_CHANNEL_MDMA_RSVD_3_MASK}, - {"GLBL2_CHANNEL_MDMA_H2C_ENG", - GLBL2_CHANNEL_MDMA_H2C_ENG_MASK}, -}; - - -static struct regfield_info - glbl2_channel_strm_field_info[] = { - {"GLBL2_CHANNEL_STRM_RSVD_1", - GLBL2_CHANNEL_STRM_RSVD_1_MASK}, - {"GLBL2_CHANNEL_STRM_C2H_ST", - GLBL2_CHANNEL_STRM_C2H_ST_MASK}, - {"GLBL2_CHANNEL_STRM_H2C_ST", - GLBL2_CHANNEL_STRM_H2C_ST_MASK}, - {"GLBL2_CHANNEL_STRM_RSVD_2", - GLBL2_CHANNEL_STRM_RSVD_2_MASK}, - {"GLBL2_CHANNEL_STRM_C2H_ENG", - GLBL2_CHANNEL_STRM_C2H_ENG_MASK}, - {"GLBL2_CHANNEL_STRM_RSVD_3", - GLBL2_CHANNEL_STRM_RSVD_3_MASK}, - {"GLBL2_CHANNEL_STRM_H2C_ENG", - GLBL2_CHANNEL_STRM_H2C_ENG_MASK}, -}; - - -static struct regfield_info - glbl2_channel_cap_field_info[] = { - {"GLBL2_CHANNEL_CAP_RSVD_1", - GLBL2_CHANNEL_CAP_RSVD_1_MASK}, - {"GLBL2_CHANNEL_CAP_MULTIQ_MAX", - GLBL2_CHANNEL_CAP_MULTIQ_MAX_MASK}, -}; - - -static struct regfield_info - glbl2_channel_pasid_cap_field_info[] = { - {"GLBL2_CHANNEL_PASID_CAP_RSVD_1", - GLBL2_CHANNEL_PASID_CAP_RSVD_1_MASK}, - {"GLBL2_CHANNEL_PASID_CAP_BRIDGEOFFSET", - GLBL2_CHANNEL_PASID_CAP_BRIDGEOFFSET_MASK}, - {"GLBL2_CHANNEL_PASID_CAP_RSVD_2", - GLBL2_CHANNEL_PASID_CAP_RSVD_2_MASK}, - {"GLBL2_CHANNEL_PASID_CAP_BRIDGEEN", - GLBL2_CHANNEL_PASID_CAP_BRIDGEEN_MASK}, - {"GLBL2_CHANNEL_PASID_CAP_DMAEN", - GLBL2_CHANNEL_PASID_CAP_DMAEN_MASK}, -}; - - -static struct regfield_info - glbl2_channel_func_ret_field_info[] = { - {"GLBL2_CHANNEL_FUNC_RET_RSVD_1", - GLBL2_CHANNEL_FUNC_RET_RSVD_1_MASK}, - {"GLBL2_CHANNEL_FUNC_RET_FUNC", - GLBL2_CHANNEL_FUNC_RET_FUNC_MASK}, -}; - - -static struct regfield_info - glbl2_system_id_field_info[] = { - {"GLBL2_SYSTEM_ID_RSVD_1", - GLBL2_SYSTEM_ID_RSVD_1_MASK}, - {"GLBL2_SYSTEM_ID", - GLBL2_SYSTEM_ID_MASK}, -}; - - -static struct regfield_info - glbl2_misc_cap_field_info[] = { - {"GLBL2_MISC_CAP_RSVD_1", - GLBL2_MISC_CAP_RSVD_1_MASK}, -}; - - -static struct regfield_info - glbl2_dbg_pcie_rq0_field_info[] = { - {"GLBL2_PCIE_RQ0_NPH_AVL", - GLBL2_PCIE_RQ0_NPH_AVL_MASK}, - {"GLBL2_PCIE_RQ0_RCB_AVL", - GLBL2_PCIE_RQ0_RCB_AVL_MASK}, - {"GLBL2_PCIE_RQ0_SLV_RD_CREDS", - GLBL2_PCIE_RQ0_SLV_RD_CREDS_MASK}, - {"GLBL2_PCIE_RQ0_TAG_EP", - GLBL2_PCIE_RQ0_TAG_EP_MASK}, - {"GLBL2_PCIE_RQ0_TAG_FL", - GLBL2_PCIE_RQ0_TAG_FL_MASK}, -}; - - -static struct regfield_info - glbl2_dbg_pcie_rq1_field_info[] = { - {"GLBL2_PCIE_RQ1_RSVD_1", - GLBL2_PCIE_RQ1_RSVD_1_MASK}, - {"GLBL2_PCIE_RQ1_WTLP_REQ", - GLBL2_PCIE_RQ1_WTLP_REQ_MASK}, - {"GLBL2_PCIE_RQ1_WTLP_HEADER_FIFO_FL", - GLBL2_PCIE_RQ1_WTLP_HEADER_FIFO_FL_MASK}, - {"GLBL2_PCIE_RQ1_WTLP_HEADER_FIFO_EP", - GLBL2_PCIE_RQ1_WTLP_HEADER_FIFO_EP_MASK}, - {"GLBL2_PCIE_RQ1_RQ_FIFO_EP", - GLBL2_PCIE_RQ1_RQ_FIFO_EP_MASK}, - {"GLBL2_PCIE_RQ1_RQ_FIFO_FL", - GLBL2_PCIE_RQ1_RQ_FIFO_FL_MASK}, - {"GLBL2_PCIE_RQ1_TLPSM", - GLBL2_PCIE_RQ1_TLPSM_MASK}, - {"GLBL2_PCIE_RQ1_TLPSM512", - GLBL2_PCIE_RQ1_TLPSM512_MASK}, - {"GLBL2_PCIE_RQ1_RREQ0_RCB_OK", - GLBL2_PCIE_RQ1_RREQ0_RCB_OK_MASK}, - {"GLBL2_PCIE_RQ1_RREQ0_SLV", - GLBL2_PCIE_RQ1_RREQ0_SLV_MASK}, - {"GLBL2_PCIE_RQ1_RREQ0_VLD", - GLBL2_PCIE_RQ1_RREQ0_VLD_MASK}, - {"GLBL2_PCIE_RQ1_RREQ1_RCB_OK", - GLBL2_PCIE_RQ1_RREQ1_RCB_OK_MASK}, - {"GLBL2_PCIE_RQ1_RREQ1_SLV", - GLBL2_PCIE_RQ1_RREQ1_SLV_MASK}, - {"GLBL2_PCIE_RQ1_RREQ1_VLD", - GLBL2_PCIE_RQ1_RREQ1_VLD_MASK}, -}; - - -static struct regfield_info - glbl2_dbg_aximm_wr0_field_info[] = { - {"GLBL2_AXIMM_WR0_RSVD_1", - GLBL2_AXIMM_WR0_RSVD_1_MASK}, - {"GLBL2_AXIMM_WR0_WR_REQ", - GLBL2_AXIMM_WR0_WR_REQ_MASK}, - {"GLBL2_AXIMM_WR0_WR_CHN", - GLBL2_AXIMM_WR0_WR_CHN_MASK}, - {"GLBL2_AXIMM_WR0_WTLP_DATA_FIFO_EP", - GLBL2_AXIMM_WR0_WTLP_DATA_FIFO_EP_MASK}, - {"GLBL2_AXIMM_WR0_WPL_FIFO_EP", - GLBL2_AXIMM_WR0_WPL_FIFO_EP_MASK}, - {"GLBL2_AXIMM_WR0_BRSP_CLAIM_CHN", - GLBL2_AXIMM_WR0_BRSP_CLAIM_CHN_MASK}, - {"GLBL2_AXIMM_WR0_WRREQ_CNT", - GLBL2_AXIMM_WR0_WRREQ_CNT_MASK}, - {"GLBL2_AXIMM_WR0_BID", - GLBL2_AXIMM_WR0_BID_MASK}, - {"GLBL2_AXIMM_WR0_BVALID", - GLBL2_AXIMM_WR0_BVALID_MASK}, - {"GLBL2_AXIMM_WR0_BREADY", - GLBL2_AXIMM_WR0_BREADY_MASK}, - {"GLBL2_AXIMM_WR0_WVALID", - GLBL2_AXIMM_WR0_WVALID_MASK}, - {"GLBL2_AXIMM_WR0_WREADY", - GLBL2_AXIMM_WR0_WREADY_MASK}, - {"GLBL2_AXIMM_WR0_AWID", - GLBL2_AXIMM_WR0_AWID_MASK}, - {"GLBL2_AXIMM_WR0_AWVALID", - GLBL2_AXIMM_WR0_AWVALID_MASK}, - {"GLBL2_AXIMM_WR0_AWREADY", - GLBL2_AXIMM_WR0_AWREADY_MASK}, -}; - - -static struct regfield_info - glbl2_dbg_aximm_wr1_field_info[] = { - {"GLBL2_AXIMM_WR1_RSVD_1", - GLBL2_AXIMM_WR1_RSVD_1_MASK}, - {"GLBL2_AXIMM_WR1_BRSP_CNT4", - GLBL2_AXIMM_WR1_BRSP_CNT4_MASK}, - {"GLBL2_AXIMM_WR1_BRSP_CNT3", - GLBL2_AXIMM_WR1_BRSP_CNT3_MASK}, - {"GLBL2_AXIMM_WR1_BRSP_CNT2", - GLBL2_AXIMM_WR1_BRSP_CNT2_MASK}, - {"GLBL2_AXIMM_WR1_BRSP_CNT1", - GLBL2_AXIMM_WR1_BRSP_CNT1_MASK}, - {"GLBL2_AXIMM_WR1_BRSP_CNT0", - GLBL2_AXIMM_WR1_BRSP_CNT0_MASK}, -}; - - -static struct regfield_info - glbl2_dbg_aximm_rd0_field_info[] = { - {"GLBL2_AXIMM_RD0_RSVD_1", - GLBL2_AXIMM_RD0_RSVD_1_MASK}, - {"GLBL2_AXIMM_RD0_PND_CNT", - GLBL2_AXIMM_RD0_PND_CNT_MASK}, - {"GLBL2_AXIMM_RD0_RD_CHNL", - GLBL2_AXIMM_RD0_RD_CHNL_MASK}, - {"GLBL2_AXIMM_RD0_RD_REQ", - GLBL2_AXIMM_RD0_RD_REQ_MASK}, - {"GLBL2_AXIMM_RD0_RRSP_CLAIM_CHNL", - GLBL2_AXIMM_RD0_RRSP_CLAIM_CHNL_MASK}, - {"GLBL2_AXIMM_RD0_RID", - GLBL2_AXIMM_RD0_RID_MASK}, - {"GLBL2_AXIMM_RD0_RVALID", - GLBL2_AXIMM_RD0_RVALID_MASK}, - {"GLBL2_AXIMM_RD0_RREADY", - GLBL2_AXIMM_RD0_RREADY_MASK}, - {"GLBL2_AXIMM_RD0_ARID", - GLBL2_AXIMM_RD0_ARID_MASK}, - {"GLBL2_AXIMM_RD0_ARVALID", - GLBL2_AXIMM_RD0_ARVALID_MASK}, - {"GLBL2_AXIMM_RD0_ARREADY", - GLBL2_AXIMM_RD0_ARREADY_MASK}, -}; - - -static struct regfield_info - glbl2_dbg_aximm_rd1_field_info[] = { - {"GLBL2_AXIMM_RD1_RSVD_1", - GLBL2_AXIMM_RD1_RSVD_1_MASK}, - {"GLBL2_AXIMM_RD1_RRSP_CNT4", - GLBL2_AXIMM_RD1_RRSP_CNT4_MASK}, - {"GLBL2_AXIMM_RD1_RRSP_CNT3", - GLBL2_AXIMM_RD1_RRSP_CNT3_MASK}, - {"GLBL2_AXIMM_RD1_RRSP_CNT2", - GLBL2_AXIMM_RD1_RRSP_CNT2_MASK}, - {"GLBL2_AXIMM_RD1_RRSP_CNT1", - GLBL2_AXIMM_RD1_RRSP_CNT1_MASK}, - {"GLBL2_AXIMM_RD1_RRSP_CNT0", - GLBL2_AXIMM_RD1_RRSP_CNT0_MASK}, -}; - - -static struct regfield_info - glbl_rng_sz_1_field_info[] = { - {"GLBL_RNG_SZ_1_RSVD_1", - GLBL_RNG_SZ_1_RSVD_1_MASK}, - {"GLBL_RNG_SZ_1_RING_SIZE", - GLBL_RNG_SZ_1_RING_SIZE_MASK}, -}; - - -static struct regfield_info - glbl_rng_sz_2_field_info[] = { - {"GLBL_RNG_SZ_2_RSVD_1", - GLBL_RNG_SZ_2_RSVD_1_MASK}, - {"GLBL_RNG_SZ_2_RING_SIZE", - GLBL_RNG_SZ_2_RING_SIZE_MASK}, -}; - - -static struct regfield_info - glbl_rng_sz_3_field_info[] = { - {"GLBL_RNG_SZ_3_RSVD_1", - GLBL_RNG_SZ_3_RSVD_1_MASK}, - {"GLBL_RNG_SZ_3_RING_SIZE", - GLBL_RNG_SZ_3_RING_SIZE_MASK}, -}; - - -static struct regfield_info - glbl_rng_sz_4_field_info[] = { - {"GLBL_RNG_SZ_4_RSVD_1", - GLBL_RNG_SZ_4_RSVD_1_MASK}, - {"GLBL_RNG_SZ_4_RING_SIZE", - GLBL_RNG_SZ_4_RING_SIZE_MASK}, -}; - - -static struct regfield_info - glbl_rng_sz_5_field_info[] = { - {"GLBL_RNG_SZ_5_RSVD_1", - GLBL_RNG_SZ_5_RSVD_1_MASK}, - {"GLBL_RNG_SZ_5_RING_SIZE", - GLBL_RNG_SZ_5_RING_SIZE_MASK}, -}; - - -static struct regfield_info - glbl_rng_sz_6_field_info[] = { - {"GLBL_RNG_SZ_6_RSVD_1", - GLBL_RNG_SZ_6_RSVD_1_MASK}, - {"GLBL_RNG_SZ_6_RING_SIZE", - GLBL_RNG_SZ_6_RING_SIZE_MASK}, -}; - - -static struct regfield_info - glbl_rng_sz_7_field_info[] = { - {"GLBL_RNG_SZ_7_RSVD_1", - GLBL_RNG_SZ_7_RSVD_1_MASK}, - {"GLBL_RNG_SZ_7_RING_SIZE", - GLBL_RNG_SZ_7_RING_SIZE_MASK}, -}; - - -static struct regfield_info - glbl_rng_sz_8_field_info[] = { - {"GLBL_RNG_SZ_8_RSVD_1", - GLBL_RNG_SZ_8_RSVD_1_MASK}, - {"GLBL_RNG_SZ_8_RING_SIZE", - GLBL_RNG_SZ_8_RING_SIZE_MASK}, -}; - - -static struct regfield_info - glbl_rng_sz_9_field_info[] = { - {"GLBL_RNG_SZ_9_RSVD_1", - GLBL_RNG_SZ_9_RSVD_1_MASK}, - {"GLBL_RNG_SZ_9_RING_SIZE", - GLBL_RNG_SZ_9_RING_SIZE_MASK}, -}; - - -static struct regfield_info - glbl_rng_sz_a_field_info[] = { - {"GLBL_RNG_SZ_A_RSVD_1", - GLBL_RNG_SZ_A_RSVD_1_MASK}, - {"GLBL_RNG_SZ_A_RING_SIZE", - GLBL_RNG_SZ_A_RING_SIZE_MASK}, -}; - - -static struct regfield_info - glbl_rng_sz_b_field_info[] = { - {"GLBL_RNG_SZ_B_RSVD_1", - GLBL_RNG_SZ_B_RSVD_1_MASK}, - {"GLBL_RNG_SZ_B_RING_SIZE", - GLBL_RNG_SZ_B_RING_SIZE_MASK}, -}; - - -static struct regfield_info - glbl_rng_sz_c_field_info[] = { - {"GLBL_RNG_SZ_C_RSVD_1", - GLBL_RNG_SZ_C_RSVD_1_MASK}, - {"GLBL_RNG_SZ_C_RING_SIZE", - GLBL_RNG_SZ_C_RING_SIZE_MASK}, -}; - - -static struct regfield_info - glbl_rng_sz_d_field_info[] = { - {"GLBL_RNG_SZ_D_RSVD_1", - GLBL_RNG_SZ_D_RSVD_1_MASK}, - {"GLBL_RNG_SZ_D_RING_SIZE", - GLBL_RNG_SZ_D_RING_SIZE_MASK}, -}; - - -static struct regfield_info - glbl_rng_sz_e_field_info[] = { - {"GLBL_RNG_SZ_E_RSVD_1", - GLBL_RNG_SZ_E_RSVD_1_MASK}, - {"GLBL_RNG_SZ_E_RING_SIZE", - GLBL_RNG_SZ_E_RING_SIZE_MASK}, -}; - - -static struct regfield_info - glbl_rng_sz_f_field_info[] = { - {"GLBL_RNG_SZ_F_RSVD_1", - GLBL_RNG_SZ_F_RSVD_1_MASK}, - {"GLBL_RNG_SZ_F_RING_SIZE", - GLBL_RNG_SZ_F_RING_SIZE_MASK}, -}; - - -static struct regfield_info - glbl_rng_sz_10_field_info[] = { - {"GLBL_RNG_SZ_10_RSVD_1", - GLBL_RNG_SZ_10_RSVD_1_MASK}, - {"GLBL_RNG_SZ_10_RING_SIZE", - GLBL_RNG_SZ_10_RING_SIZE_MASK}, -}; - - -static struct regfield_info - glbl_err_stat_field_info[] = { - {"GLBL_ERR_STAT_RSVD_1", - GLBL_ERR_STAT_RSVD_1_MASK}, - {"GLBL_ERR_STAT_ERR_H2C_ST", - GLBL_ERR_STAT_ERR_H2C_ST_MASK}, - {"GLBL_ERR_STAT_ERR_BDG", - GLBL_ERR_STAT_ERR_BDG_MASK}, - {"GLBL_ERR_STAT_IND_CTXT_CMD_ERR", - GLBL_ERR_STAT_IND_CTXT_CMD_ERR_MASK}, - {"GLBL_ERR_STAT_ERR_C2H_ST", - GLBL_ERR_STAT_ERR_C2H_ST_MASK}, - {"GLBL_ERR_STAT_ERR_C2H_MM_1", - GLBL_ERR_STAT_ERR_C2H_MM_1_MASK}, - {"GLBL_ERR_STAT_ERR_C2H_MM_0", - GLBL_ERR_STAT_ERR_C2H_MM_0_MASK}, - {"GLBL_ERR_STAT_ERR_H2C_MM_1", - GLBL_ERR_STAT_ERR_H2C_MM_1_MASK}, - {"GLBL_ERR_STAT_ERR_H2C_MM_0", - GLBL_ERR_STAT_ERR_H2C_MM_0_MASK}, - {"GLBL_ERR_STAT_ERR_TRQ", - GLBL_ERR_STAT_ERR_TRQ_MASK}, - {"GLBL_ERR_STAT_ERR_DSC", - GLBL_ERR_STAT_ERR_DSC_MASK}, - {"GLBL_ERR_STAT_ERR_RAM_DBE", - GLBL_ERR_STAT_ERR_RAM_DBE_MASK}, - {"GLBL_ERR_STAT_ERR_RAM_SBE", - GLBL_ERR_STAT_ERR_RAM_SBE_MASK}, -}; - - -static struct regfield_info - glbl_err_mask_field_info[] = { - {"GLBL_ERR_RSVD_1", - GLBL_ERR_RSVD_1_MASK}, - {"GLBL_ERR", - GLBL_ERR_MASK}, -}; - - -static struct regfield_info - glbl_dsc_cfg_field_info[] = { - {"GLBL_DSC_CFG_RSVD_1", - GLBL_DSC_CFG_RSVD_1_MASK}, - {"GLBL_DSC_CFG_UNC_OVR_COR", - GLBL_DSC_CFG_UNC_OVR_COR_MASK}, - {"GLBL_DSC_CFG_CTXT_FER_DIS", - GLBL_DSC_CFG_CTXT_FER_DIS_MASK}, - {"GLBL_DSC_CFG_RSVD_2", - GLBL_DSC_CFG_RSVD_2_MASK}, - {"GLBL_DSC_CFG_MAXFETCH", - GLBL_DSC_CFG_MAXFETCH_MASK}, - {"GLBL_DSC_CFG_WB_ACC_INT", - GLBL_DSC_CFG_WB_ACC_INT_MASK}, -}; - - -static struct regfield_info - glbl_dsc_err_sts_field_info[] = { - {"GLBL_DSC_ERR_STS_RSVD_1", - GLBL_DSC_ERR_STS_RSVD_1_MASK}, - {"GLBL_DSC_ERR_STS_SBE", - GLBL_DSC_ERR_STS_SBE_MASK}, - {"GLBL_DSC_ERR_STS_DBE", - GLBL_DSC_ERR_STS_DBE_MASK}, - {"GLBL_DSC_ERR_STS_RQ_CANCEL", - GLBL_DSC_ERR_STS_RQ_CANCEL_MASK}, - {"GLBL_DSC_ERR_STS_DSC", - GLBL_DSC_ERR_STS_DSC_MASK}, - {"GLBL_DSC_ERR_STS_DMA", - GLBL_DSC_ERR_STS_DMA_MASK}, - {"GLBL_DSC_ERR_STS_FLR_CANCEL", - GLBL_DSC_ERR_STS_FLR_CANCEL_MASK}, - {"GLBL_DSC_ERR_STS_RSVD_2", - GLBL_DSC_ERR_STS_RSVD_2_MASK}, - {"GLBL_DSC_ERR_STS_DAT_POISON", - GLBL_DSC_ERR_STS_DAT_POISON_MASK}, - {"GLBL_DSC_ERR_STS_TIMEOUT", - GLBL_DSC_ERR_STS_TIMEOUT_MASK}, - {"GLBL_DSC_ERR_STS_FLR", - GLBL_DSC_ERR_STS_FLR_MASK}, - {"GLBL_DSC_ERR_STS_TAG", - GLBL_DSC_ERR_STS_TAG_MASK}, - {"GLBL_DSC_ERR_STS_ADDR", - GLBL_DSC_ERR_STS_ADDR_MASK}, - {"GLBL_DSC_ERR_STS_PARAM", - GLBL_DSC_ERR_STS_PARAM_MASK}, - {"GLBL_DSC_ERR_STS_UR_CA", - GLBL_DSC_ERR_STS_UR_CA_MASK}, - {"GLBL_DSC_ERR_STS_POISON", - GLBL_DSC_ERR_STS_POISON_MASK}, -}; - - -static struct regfield_info - glbl_dsc_err_msk_field_info[] = { - {"GLBL_DSC_ERR_MSK", - GLBL_DSC_ERR_MSK_MASK}, -}; - - -static struct regfield_info - glbl_dsc_err_log0_field_info[] = { - {"GLBL_DSC_ERR_LOG0_VALID", - GLBL_DSC_ERR_LOG0_VALID_MASK}, - {"GLBL_DSC_ERR_LOG0_RSVD_1", - GLBL_DSC_ERR_LOG0_RSVD_1_MASK}, - {"GLBL_DSC_ERR_LOG0_QID", - GLBL_DSC_ERR_LOG0_QID_MASK}, - {"GLBL_DSC_ERR_LOG0_SEL", - GLBL_DSC_ERR_LOG0_SEL_MASK}, - {"GLBL_DSC_ERR_LOG0_CIDX", - GLBL_DSC_ERR_LOG0_CIDX_MASK}, -}; - - -static struct regfield_info - glbl_dsc_err_log1_field_info[] = { - {"GLBL_DSC_ERR_LOG1_RSVD_1", - GLBL_DSC_ERR_LOG1_RSVD_1_MASK}, - {"GLBL_DSC_ERR_LOG1_SUB_TYPE", - GLBL_DSC_ERR_LOG1_SUB_TYPE_MASK}, - {"GLBL_DSC_ERR_LOG1_ERR_TYPE", - GLBL_DSC_ERR_LOG1_ERR_TYPE_MASK}, -}; - - -static struct regfield_info - glbl_trq_err_sts_field_info[] = { - {"GLBL_TRQ_ERR_STS_RSVD_1", - GLBL_TRQ_ERR_STS_RSVD_1_MASK}, - {"GLBL_TRQ_ERR_STS_TCP_TIMEOUT", - GLBL_TRQ_ERR_STS_TCP_TIMEOUT_MASK}, - {"GLBL_TRQ_ERR_STS_VF_ACCESS_ERR", - GLBL_TRQ_ERR_STS_VF_ACCESS_ERR_MASK}, - {"GLBL_TRQ_ERR_STS_QID_RANGE", - GLBL_TRQ_ERR_STS_QID_RANGE_MASK}, - {"GLBL_TRQ_ERR_STS_UNMAPPED", - GLBL_TRQ_ERR_STS_UNMAPPED_MASK}, -}; - - -static struct regfield_info - glbl_trq_err_msk_field_info[] = { - {"GLBL_TRQ_ERR_MSK", - GLBL_TRQ_ERR_MSK_MASK}, -}; - - -static struct regfield_info - glbl_trq_err_log_field_info[] = { - {"GLBL_TRQ_ERR_LOG_RSVD_1", - GLBL_TRQ_ERR_LOG_RSVD_1_MASK}, - {"GLBL_TRQ_ERR_LOG_TARGET", - GLBL_TRQ_ERR_LOG_TARGET_MASK}, - {"GLBL_TRQ_ERR_LOG_FUNC", - GLBL_TRQ_ERR_LOG_FUNC_MASK}, - {"GLBL_TRQ_ERR_LOG_ADDRESS", - GLBL_TRQ_ERR_LOG_ADDRESS_MASK}, -}; - - -static struct regfield_info - glbl_dsc_dbg_dat0_field_info[] = { - {"GLBL_DSC_DAT0_RSVD_1", - GLBL_DSC_DAT0_RSVD_1_MASK}, - {"GLBL_DSC_DAT0_CTXT_ARB_DIR", - GLBL_DSC_DAT0_CTXT_ARB_DIR_MASK}, - {"GLBL_DSC_DAT0_CTXT_ARB_QID", - GLBL_DSC_DAT0_CTXT_ARB_QID_MASK}, - {"GLBL_DSC_DAT0_CTXT_ARB_REQ", - GLBL_DSC_DAT0_CTXT_ARB_REQ_MASK}, - {"GLBL_DSC_DAT0_IRQ_FIFO_FL", - GLBL_DSC_DAT0_IRQ_FIFO_FL_MASK}, - {"GLBL_DSC_DAT0_TMSTALL", - GLBL_DSC_DAT0_TMSTALL_MASK}, - {"GLBL_DSC_DAT0_RRQ_STALL", - GLBL_DSC_DAT0_RRQ_STALL_MASK}, - {"GLBL_DSC_DAT0_RCP_FIFO_SPC_STALL", - GLBL_DSC_DAT0_RCP_FIFO_SPC_STALL_MASK}, - {"GLBL_DSC_DAT0_RRQ_FIFO_SPC_STALL", - GLBL_DSC_DAT0_RRQ_FIFO_SPC_STALL_MASK}, - {"GLBL_DSC_DAT0_FAB_MRKR_RSP_STALL", - GLBL_DSC_DAT0_FAB_MRKR_RSP_STALL_MASK}, - {"GLBL_DSC_DAT0_DSC_OUT_STALL", - GLBL_DSC_DAT0_DSC_OUT_STALL_MASK}, -}; - - -static struct regfield_info - glbl_dsc_dbg_dat1_field_info[] = { - {"GLBL_DSC_DAT1_RSVD_1", - GLBL_DSC_DAT1_RSVD_1_MASK}, - {"GLBL_DSC_DAT1_EVT_SPC_C2H", - GLBL_DSC_DAT1_EVT_SPC_C2H_MASK}, - {"GLBL_DSC_DAT1_EVT_SP_H2C", - GLBL_DSC_DAT1_EVT_SP_H2C_MASK}, - {"GLBL_DSC_DAT1_DSC_SPC_C2H", - GLBL_DSC_DAT1_DSC_SPC_C2H_MASK}, - {"GLBL_DSC_DAT1_DSC_SPC_H2C", - GLBL_DSC_DAT1_DSC_SPC_H2C_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_0_field_info[] = { - {"TRQ_SEL_FMAP_0_RSVD_1", - TRQ_SEL_FMAP_0_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_0_QID_MAX", - TRQ_SEL_FMAP_0_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_0_QID_BASE", - TRQ_SEL_FMAP_0_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_1_field_info[] = { - {"TRQ_SEL_FMAP_1_RSVD_1", - TRQ_SEL_FMAP_1_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_1_QID_MAX", - TRQ_SEL_FMAP_1_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_1_QID_BASE", - TRQ_SEL_FMAP_1_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_2_field_info[] = { - {"TRQ_SEL_FMAP_2_RSVD_1", - TRQ_SEL_FMAP_2_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_2_QID_MAX", - TRQ_SEL_FMAP_2_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_2_QID_BASE", - TRQ_SEL_FMAP_2_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_3_field_info[] = { - {"TRQ_SEL_FMAP_3_RSVD_1", - TRQ_SEL_FMAP_3_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_3_QID_MAX", - TRQ_SEL_FMAP_3_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_3_QID_BASE", - TRQ_SEL_FMAP_3_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_4_field_info[] = { - {"TRQ_SEL_FMAP_4_RSVD_1", - TRQ_SEL_FMAP_4_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_4_QID_MAX", - TRQ_SEL_FMAP_4_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_4_QID_BASE", - TRQ_SEL_FMAP_4_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_5_field_info[] = { - {"TRQ_SEL_FMAP_5_RSVD_1", - TRQ_SEL_FMAP_5_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_5_QID_MAX", - TRQ_SEL_FMAP_5_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_5_QID_BASE", - TRQ_SEL_FMAP_5_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_6_field_info[] = { - {"TRQ_SEL_FMAP_6_RSVD_1", - TRQ_SEL_FMAP_6_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_6_QID_MAX", - TRQ_SEL_FMAP_6_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_6_QID_BASE", - TRQ_SEL_FMAP_6_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_7_field_info[] = { - {"TRQ_SEL_FMAP_7_RSVD_1", - TRQ_SEL_FMAP_7_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_7_QID_MAX", - TRQ_SEL_FMAP_7_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_7_QID_BASE", - TRQ_SEL_FMAP_7_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_8_field_info[] = { - {"TRQ_SEL_FMAP_8_RSVD_1", - TRQ_SEL_FMAP_8_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_8_QID_MAX", - TRQ_SEL_FMAP_8_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_8_QID_BASE", - TRQ_SEL_FMAP_8_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_9_field_info[] = { - {"TRQ_SEL_FMAP_9_RSVD_1", - TRQ_SEL_FMAP_9_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_9_QID_MAX", - TRQ_SEL_FMAP_9_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_9_QID_BASE", - TRQ_SEL_FMAP_9_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_a_field_info[] = { - {"TRQ_SEL_FMAP_A_RSVD_1", - TRQ_SEL_FMAP_A_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_A_QID_MAX", - TRQ_SEL_FMAP_A_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_A_QID_BASE", - TRQ_SEL_FMAP_A_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_b_field_info[] = { - {"TRQ_SEL_FMAP_B_RSVD_1", - TRQ_SEL_FMAP_B_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_B_QID_MAX", - TRQ_SEL_FMAP_B_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_B_QID_BASE", - TRQ_SEL_FMAP_B_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_d_field_info[] = { - {"TRQ_SEL_FMAP_D_RSVD_1", - TRQ_SEL_FMAP_D_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_D_QID_MAX", - TRQ_SEL_FMAP_D_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_D_QID_BASE", - TRQ_SEL_FMAP_D_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_e_field_info[] = { - {"TRQ_SEL_FMAP_E_RSVD_1", - TRQ_SEL_FMAP_E_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_E_QID_MAX", - TRQ_SEL_FMAP_E_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_E_QID_BASE", - TRQ_SEL_FMAP_E_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_f_field_info[] = { - {"TRQ_SEL_FMAP_F_RSVD_1", - TRQ_SEL_FMAP_F_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_F_QID_MAX", - TRQ_SEL_FMAP_F_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_F_QID_BASE", - TRQ_SEL_FMAP_F_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_10_field_info[] = { - {"TRQ_SEL_FMAP_10_RSVD_1", - TRQ_SEL_FMAP_10_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_10_QID_MAX", - TRQ_SEL_FMAP_10_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_10_QID_BASE", - TRQ_SEL_FMAP_10_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_11_field_info[] = { - {"TRQ_SEL_FMAP_11_RSVD_1", - TRQ_SEL_FMAP_11_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_11_QID_MAX", - TRQ_SEL_FMAP_11_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_11_QID_BASE", - TRQ_SEL_FMAP_11_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_12_field_info[] = { - {"TRQ_SEL_FMAP_12_RSVD_1", - TRQ_SEL_FMAP_12_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_12_QID_MAX", - TRQ_SEL_FMAP_12_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_12_QID_BASE", - TRQ_SEL_FMAP_12_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_13_field_info[] = { - {"TRQ_SEL_FMAP_13_RSVD_1", - TRQ_SEL_FMAP_13_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_13_QID_MAX", - TRQ_SEL_FMAP_13_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_13_QID_BASE", - TRQ_SEL_FMAP_13_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_14_field_info[] = { - {"TRQ_SEL_FMAP_14_RSVD_1", - TRQ_SEL_FMAP_14_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_14_QID_MAX", - TRQ_SEL_FMAP_14_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_14_QID_BASE", - TRQ_SEL_FMAP_14_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_15_field_info[] = { - {"TRQ_SEL_FMAP_15_RSVD_1", - TRQ_SEL_FMAP_15_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_15_QID_MAX", - TRQ_SEL_FMAP_15_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_15_QID_BASE", - TRQ_SEL_FMAP_15_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_16_field_info[] = { - {"TRQ_SEL_FMAP_16_RSVD_1", - TRQ_SEL_FMAP_16_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_16_QID_MAX", - TRQ_SEL_FMAP_16_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_16_QID_BASE", - TRQ_SEL_FMAP_16_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_17_field_info[] = { - {"TRQ_SEL_FMAP_17_RSVD_1", - TRQ_SEL_FMAP_17_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_17_QID_MAX", - TRQ_SEL_FMAP_17_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_17_QID_BASE", - TRQ_SEL_FMAP_17_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_18_field_info[] = { - {"TRQ_SEL_FMAP_18_RSVD_1", - TRQ_SEL_FMAP_18_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_18_QID_MAX", - TRQ_SEL_FMAP_18_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_18_QID_BASE", - TRQ_SEL_FMAP_18_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_19_field_info[] = { - {"TRQ_SEL_FMAP_19_RSVD_1", - TRQ_SEL_FMAP_19_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_19_QID_MAX", - TRQ_SEL_FMAP_19_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_19_QID_BASE", - TRQ_SEL_FMAP_19_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_1a_field_info[] = { - {"TRQ_SEL_FMAP_1A_RSVD_1", - TRQ_SEL_FMAP_1A_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_1A_QID_MAX", - TRQ_SEL_FMAP_1A_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_1A_QID_BASE", - TRQ_SEL_FMAP_1A_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_1b_field_info[] = { - {"TRQ_SEL_FMAP_1B_RSVD_1", - TRQ_SEL_FMAP_1B_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_1B_QID_MAX", - TRQ_SEL_FMAP_1B_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_1B_QID_BASE", - TRQ_SEL_FMAP_1B_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_1c_field_info[] = { - {"TRQ_SEL_FMAP_1C_RSVD_1", - TRQ_SEL_FMAP_1C_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_1C_QID_MAX", - TRQ_SEL_FMAP_1C_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_1C_QID_BASE", - TRQ_SEL_FMAP_1C_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_1d_field_info[] = { - {"TRQ_SEL_FMAP_1D_RSVD_1", - TRQ_SEL_FMAP_1D_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_1D_QID_MAX", - TRQ_SEL_FMAP_1D_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_1D_QID_BASE", - TRQ_SEL_FMAP_1D_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_1e_field_info[] = { - {"TRQ_SEL_FMAP_1E_RSVD_1", - TRQ_SEL_FMAP_1E_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_1E_QID_MAX", - TRQ_SEL_FMAP_1E_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_1E_QID_BASE", - TRQ_SEL_FMAP_1E_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_1f_field_info[] = { - {"TRQ_SEL_FMAP_1F_RSVD_1", - TRQ_SEL_FMAP_1F_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_1F_QID_MAX", - TRQ_SEL_FMAP_1F_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_1F_QID_BASE", - TRQ_SEL_FMAP_1F_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_20_field_info[] = { - {"TRQ_SEL_FMAP_20_RSVD_1", - TRQ_SEL_FMAP_20_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_20_QID_MAX", - TRQ_SEL_FMAP_20_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_20_QID_BASE", - TRQ_SEL_FMAP_20_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_21_field_info[] = { - {"TRQ_SEL_FMAP_21_RSVD_1", - TRQ_SEL_FMAP_21_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_21_QID_MAX", - TRQ_SEL_FMAP_21_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_21_QID_BASE", - TRQ_SEL_FMAP_21_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_22_field_info[] = { - {"TRQ_SEL_FMAP_22_RSVD_1", - TRQ_SEL_FMAP_22_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_22_QID_MAX", - TRQ_SEL_FMAP_22_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_22_QID_BASE", - TRQ_SEL_FMAP_22_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_23_field_info[] = { - {"TRQ_SEL_FMAP_23_RSVD_1", - TRQ_SEL_FMAP_23_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_23_QID_MAX", - TRQ_SEL_FMAP_23_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_23_QID_BASE", - TRQ_SEL_FMAP_23_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_24_field_info[] = { - {"TRQ_SEL_FMAP_24_RSVD_1", - TRQ_SEL_FMAP_24_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_24_QID_MAX", - TRQ_SEL_FMAP_24_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_24_QID_BASE", - TRQ_SEL_FMAP_24_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_25_field_info[] = { - {"TRQ_SEL_FMAP_25_RSVD_1", - TRQ_SEL_FMAP_25_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_25_QID_MAX", - TRQ_SEL_FMAP_25_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_25_QID_BASE", - TRQ_SEL_FMAP_25_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_26_field_info[] = { - {"TRQ_SEL_FMAP_26_RSVD_1", - TRQ_SEL_FMAP_26_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_26_QID_MAX", - TRQ_SEL_FMAP_26_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_26_QID_BASE", - TRQ_SEL_FMAP_26_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_27_field_info[] = { - {"TRQ_SEL_FMAP_27_RSVD_1", - TRQ_SEL_FMAP_27_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_27_QID_MAX", - TRQ_SEL_FMAP_27_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_27_QID_BASE", - TRQ_SEL_FMAP_27_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_28_field_info[] = { - {"TRQ_SEL_FMAP_28_RSVD_1", - TRQ_SEL_FMAP_28_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_28_QID_MAX", - TRQ_SEL_FMAP_28_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_28_QID_BASE", - TRQ_SEL_FMAP_28_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_29_field_info[] = { - {"TRQ_SEL_FMAP_29_RSVD_1", - TRQ_SEL_FMAP_29_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_29_QID_MAX", - TRQ_SEL_FMAP_29_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_29_QID_BASE", - TRQ_SEL_FMAP_29_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_2a_field_info[] = { - {"TRQ_SEL_FMAP_2A_RSVD_1", - TRQ_SEL_FMAP_2A_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_2A_QID_MAX", - TRQ_SEL_FMAP_2A_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_2A_QID_BASE", - TRQ_SEL_FMAP_2A_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_2b_field_info[] = { - {"TRQ_SEL_FMAP_2B_RSVD_1", - TRQ_SEL_FMAP_2B_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_2B_QID_MAX", - TRQ_SEL_FMAP_2B_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_2B_QID_BASE", - TRQ_SEL_FMAP_2B_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_2c_field_info[] = { - {"TRQ_SEL_FMAP_2C_RSVD_1", - TRQ_SEL_FMAP_2C_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_2C_QID_MAX", - TRQ_SEL_FMAP_2C_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_2C_QID_BASE", - TRQ_SEL_FMAP_2C_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_2d_field_info[] = { - {"TRQ_SEL_FMAP_2D_RSVD_1", - TRQ_SEL_FMAP_2D_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_2D_QID_MAX", - TRQ_SEL_FMAP_2D_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_2D_QID_BASE", - TRQ_SEL_FMAP_2D_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_2e_field_info[] = { - {"TRQ_SEL_FMAP_2E_RSVD_1", - TRQ_SEL_FMAP_2E_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_2E_QID_MAX", - TRQ_SEL_FMAP_2E_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_2E_QID_BASE", - TRQ_SEL_FMAP_2E_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_2f_field_info[] = { - {"TRQ_SEL_FMAP_2F_RSVD_1", - TRQ_SEL_FMAP_2F_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_2F_QID_MAX", - TRQ_SEL_FMAP_2F_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_2F_QID_BASE", - TRQ_SEL_FMAP_2F_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_30_field_info[] = { - {"TRQ_SEL_FMAP_30_RSVD_1", - TRQ_SEL_FMAP_30_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_30_QID_MAX", - TRQ_SEL_FMAP_30_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_30_QID_BASE", - TRQ_SEL_FMAP_30_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_31_field_info[] = { - {"TRQ_SEL_FMAP_31_RSVD_1", - TRQ_SEL_FMAP_31_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_31_QID_MAX", - TRQ_SEL_FMAP_31_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_31_QID_BASE", - TRQ_SEL_FMAP_31_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_32_field_info[] = { - {"TRQ_SEL_FMAP_32_RSVD_1", - TRQ_SEL_FMAP_32_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_32_QID_MAX", - TRQ_SEL_FMAP_32_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_32_QID_BASE", - TRQ_SEL_FMAP_32_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_33_field_info[] = { - {"TRQ_SEL_FMAP_33_RSVD_1", - TRQ_SEL_FMAP_33_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_33_QID_MAX", - TRQ_SEL_FMAP_33_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_33_QID_BASE", - TRQ_SEL_FMAP_33_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_34_field_info[] = { - {"TRQ_SEL_FMAP_34_RSVD_1", - TRQ_SEL_FMAP_34_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_34_QID_MAX", - TRQ_SEL_FMAP_34_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_34_QID_BASE", - TRQ_SEL_FMAP_34_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_35_field_info[] = { - {"TRQ_SEL_FMAP_35_RSVD_1", - TRQ_SEL_FMAP_35_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_35_QID_MAX", - TRQ_SEL_FMAP_35_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_35_QID_BASE", - TRQ_SEL_FMAP_35_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_36_field_info[] = { - {"TRQ_SEL_FMAP_36_RSVD_1", - TRQ_SEL_FMAP_36_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_36_QID_MAX", - TRQ_SEL_FMAP_36_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_36_QID_BASE", - TRQ_SEL_FMAP_36_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_37_field_info[] = { - {"TRQ_SEL_FMAP_37_RSVD_1", - TRQ_SEL_FMAP_37_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_37_QID_MAX", - TRQ_SEL_FMAP_37_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_37_QID_BASE", - TRQ_SEL_FMAP_37_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_38_field_info[] = { - {"TRQ_SEL_FMAP_38_RSVD_1", - TRQ_SEL_FMAP_38_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_38_QID_MAX", - TRQ_SEL_FMAP_38_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_38_QID_BASE", - TRQ_SEL_FMAP_38_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_39_field_info[] = { - {"TRQ_SEL_FMAP_39_RSVD_1", - TRQ_SEL_FMAP_39_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_39_QID_MAX", - TRQ_SEL_FMAP_39_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_39_QID_BASE", - TRQ_SEL_FMAP_39_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_3a_field_info[] = { - {"TRQ_SEL_FMAP_3A_RSVD_1", - TRQ_SEL_FMAP_3A_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_3A_QID_MAX", - TRQ_SEL_FMAP_3A_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_3A_QID_BASE", - TRQ_SEL_FMAP_3A_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_3b_field_info[] = { - {"TRQ_SEL_FMAP_3B_RSVD_1", - TRQ_SEL_FMAP_3B_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_3B_QID_MAX", - TRQ_SEL_FMAP_3B_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_3B_QID_BASE", - TRQ_SEL_FMAP_3B_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_3c_field_info[] = { - {"TRQ_SEL_FMAP_3C_RSVD_1", - TRQ_SEL_FMAP_3C_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_3C_QID_MAX", - TRQ_SEL_FMAP_3C_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_3C_QID_BASE", - TRQ_SEL_FMAP_3C_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_3d_field_info[] = { - {"TRQ_SEL_FMAP_3D_RSVD_1", - TRQ_SEL_FMAP_3D_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_3D_QID_MAX", - TRQ_SEL_FMAP_3D_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_3D_QID_BASE", - TRQ_SEL_FMAP_3D_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_3e_field_info[] = { - {"TRQ_SEL_FMAP_3E_RSVD_1", - TRQ_SEL_FMAP_3E_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_3E_QID_MAX", - TRQ_SEL_FMAP_3E_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_3E_QID_BASE", - TRQ_SEL_FMAP_3E_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_3f_field_info[] = { - {"TRQ_SEL_FMAP_3F_RSVD_1", - TRQ_SEL_FMAP_3F_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_3F_QID_MAX", - TRQ_SEL_FMAP_3F_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_3F_QID_BASE", - TRQ_SEL_FMAP_3F_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_40_field_info[] = { - {"TRQ_SEL_FMAP_40_RSVD_1", - TRQ_SEL_FMAP_40_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_40_QID_MAX", - TRQ_SEL_FMAP_40_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_40_QID_BASE", - TRQ_SEL_FMAP_40_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_41_field_info[] = { - {"TRQ_SEL_FMAP_41_RSVD_1", - TRQ_SEL_FMAP_41_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_41_QID_MAX", - TRQ_SEL_FMAP_41_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_41_QID_BASE", - TRQ_SEL_FMAP_41_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_42_field_info[] = { - {"TRQ_SEL_FMAP_42_RSVD_1", - TRQ_SEL_FMAP_42_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_42_QID_MAX", - TRQ_SEL_FMAP_42_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_42_QID_BASE", - TRQ_SEL_FMAP_42_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_43_field_info[] = { - {"TRQ_SEL_FMAP_43_RSVD_1", - TRQ_SEL_FMAP_43_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_43_QID_MAX", - TRQ_SEL_FMAP_43_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_43_QID_BASE", - TRQ_SEL_FMAP_43_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_44_field_info[] = { - {"TRQ_SEL_FMAP_44_RSVD_1", - TRQ_SEL_FMAP_44_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_44_QID_MAX", - TRQ_SEL_FMAP_44_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_44_QID_BASE", - TRQ_SEL_FMAP_44_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_45_field_info[] = { - {"TRQ_SEL_FMAP_45_RSVD_1", - TRQ_SEL_FMAP_45_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_45_QID_MAX", - TRQ_SEL_FMAP_45_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_45_QID_BASE", - TRQ_SEL_FMAP_45_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_46_field_info[] = { - {"TRQ_SEL_FMAP_46_RSVD_1", - TRQ_SEL_FMAP_46_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_46_QID_MAX", - TRQ_SEL_FMAP_46_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_46_QID_BASE", - TRQ_SEL_FMAP_46_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_47_field_info[] = { - {"TRQ_SEL_FMAP_47_RSVD_1", - TRQ_SEL_FMAP_47_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_47_QID_MAX", - TRQ_SEL_FMAP_47_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_47_QID_BASE", - TRQ_SEL_FMAP_47_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_48_field_info[] = { - {"TRQ_SEL_FMAP_48_RSVD_1", - TRQ_SEL_FMAP_48_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_48_QID_MAX", - TRQ_SEL_FMAP_48_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_48_QID_BASE", - TRQ_SEL_FMAP_48_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_49_field_info[] = { - {"TRQ_SEL_FMAP_49_RSVD_1", - TRQ_SEL_FMAP_49_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_49_QID_MAX", - TRQ_SEL_FMAP_49_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_49_QID_BASE", - TRQ_SEL_FMAP_49_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_4a_field_info[] = { - {"TRQ_SEL_FMAP_4A_RSVD_1", - TRQ_SEL_FMAP_4A_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_4A_QID_MAX", - TRQ_SEL_FMAP_4A_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_4A_QID_BASE", - TRQ_SEL_FMAP_4A_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_4b_field_info[] = { - {"TRQ_SEL_FMAP_4B_RSVD_1", - TRQ_SEL_FMAP_4B_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_4B_QID_MAX", - TRQ_SEL_FMAP_4B_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_4B_QID_BASE", - TRQ_SEL_FMAP_4B_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_4c_field_info[] = { - {"TRQ_SEL_FMAP_4C_RSVD_1", - TRQ_SEL_FMAP_4C_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_4C_QID_MAX", - TRQ_SEL_FMAP_4C_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_4C_QID_BASE", - TRQ_SEL_FMAP_4C_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_4d_field_info[] = { - {"TRQ_SEL_FMAP_4D_RSVD_1", - TRQ_SEL_FMAP_4D_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_4D_QID_MAX", - TRQ_SEL_FMAP_4D_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_4D_QID_BASE", - TRQ_SEL_FMAP_4D_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_4e_field_info[] = { - {"TRQ_SEL_FMAP_4E_RSVD_1", - TRQ_SEL_FMAP_4E_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_4E_QID_MAX", - TRQ_SEL_FMAP_4E_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_4E_QID_BASE", - TRQ_SEL_FMAP_4E_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_4f_field_info[] = { - {"TRQ_SEL_FMAP_4F_RSVD_1", - TRQ_SEL_FMAP_4F_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_4F_QID_MAX", - TRQ_SEL_FMAP_4F_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_4F_QID_BASE", - TRQ_SEL_FMAP_4F_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_50_field_info[] = { - {"TRQ_SEL_FMAP_50_RSVD_1", - TRQ_SEL_FMAP_50_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_50_QID_MAX", - TRQ_SEL_FMAP_50_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_50_QID_BASE", - TRQ_SEL_FMAP_50_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_51_field_info[] = { - {"TRQ_SEL_FMAP_51_RSVD_1", - TRQ_SEL_FMAP_51_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_51_QID_MAX", - TRQ_SEL_FMAP_51_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_51_QID_BASE", - TRQ_SEL_FMAP_51_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_52_field_info[] = { - {"TRQ_SEL_FMAP_52_RSVD_1", - TRQ_SEL_FMAP_52_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_52_QID_MAX", - TRQ_SEL_FMAP_52_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_52_QID_BASE", - TRQ_SEL_FMAP_52_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_53_field_info[] = { - {"TRQ_SEL_FMAP_53_RSVD_1", - TRQ_SEL_FMAP_53_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_53_QID_MAX", - TRQ_SEL_FMAP_53_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_53_QID_BASE", - TRQ_SEL_FMAP_53_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_54_field_info[] = { - {"TRQ_SEL_FMAP_54_RSVD_1", - TRQ_SEL_FMAP_54_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_54_QID_MAX", - TRQ_SEL_FMAP_54_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_54_QID_BASE", - TRQ_SEL_FMAP_54_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_55_field_info[] = { - {"TRQ_SEL_FMAP_55_RSVD_1", - TRQ_SEL_FMAP_55_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_55_QID_MAX", - TRQ_SEL_FMAP_55_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_55_QID_BASE", - TRQ_SEL_FMAP_55_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_56_field_info[] = { - {"TRQ_SEL_FMAP_56_RSVD_1", - TRQ_SEL_FMAP_56_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_56_QID_MAX", - TRQ_SEL_FMAP_56_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_56_QID_BASE", - TRQ_SEL_FMAP_56_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_57_field_info[] = { - {"TRQ_SEL_FMAP_57_RSVD_1", - TRQ_SEL_FMAP_57_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_57_QID_MAX", - TRQ_SEL_FMAP_57_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_57_QID_BASE", - TRQ_SEL_FMAP_57_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_58_field_info[] = { - {"TRQ_SEL_FMAP_58_RSVD_1", - TRQ_SEL_FMAP_58_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_58_QID_MAX", - TRQ_SEL_FMAP_58_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_58_QID_BASE", - TRQ_SEL_FMAP_58_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_59_field_info[] = { - {"TRQ_SEL_FMAP_59_RSVD_1", - TRQ_SEL_FMAP_59_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_59_QID_MAX", - TRQ_SEL_FMAP_59_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_59_QID_BASE", - TRQ_SEL_FMAP_59_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_5a_field_info[] = { - {"TRQ_SEL_FMAP_5A_RSVD_1", - TRQ_SEL_FMAP_5A_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_5A_QID_MAX", - TRQ_SEL_FMAP_5A_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_5A_QID_BASE", - TRQ_SEL_FMAP_5A_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_5b_field_info[] = { - {"TRQ_SEL_FMAP_5B_RSVD_1", - TRQ_SEL_FMAP_5B_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_5B_QID_MAX", - TRQ_SEL_FMAP_5B_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_5B_QID_BASE", - TRQ_SEL_FMAP_5B_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_5c_field_info[] = { - {"TRQ_SEL_FMAP_5C_RSVD_1", - TRQ_SEL_FMAP_5C_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_5C_QID_MAX", - TRQ_SEL_FMAP_5C_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_5C_QID_BASE", - TRQ_SEL_FMAP_5C_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_5d_field_info[] = { - {"TRQ_SEL_FMAP_5D_RSVD_1", - TRQ_SEL_FMAP_5D_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_5D_QID_MAX", - TRQ_SEL_FMAP_5D_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_5D_QID_BASE", - TRQ_SEL_FMAP_5D_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_5e_field_info[] = { - {"TRQ_SEL_FMAP_5E_RSVD_1", - TRQ_SEL_FMAP_5E_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_5E_QID_MAX", - TRQ_SEL_FMAP_5E_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_5E_QID_BASE", - TRQ_SEL_FMAP_5E_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_5f_field_info[] = { - {"TRQ_SEL_FMAP_5F_RSVD_1", - TRQ_SEL_FMAP_5F_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_5F_QID_MAX", - TRQ_SEL_FMAP_5F_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_5F_QID_BASE", - TRQ_SEL_FMAP_5F_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_60_field_info[] = { - {"TRQ_SEL_FMAP_60_RSVD_1", - TRQ_SEL_FMAP_60_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_60_QID_MAX", - TRQ_SEL_FMAP_60_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_60_QID_BASE", - TRQ_SEL_FMAP_60_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_61_field_info[] = { - {"TRQ_SEL_FMAP_61_RSVD_1", - TRQ_SEL_FMAP_61_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_61_QID_MAX", - TRQ_SEL_FMAP_61_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_61_QID_BASE", - TRQ_SEL_FMAP_61_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_62_field_info[] = { - {"TRQ_SEL_FMAP_62_RSVD_1", - TRQ_SEL_FMAP_62_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_62_QID_MAX", - TRQ_SEL_FMAP_62_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_62_QID_BASE", - TRQ_SEL_FMAP_62_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_63_field_info[] = { - {"TRQ_SEL_FMAP_63_RSVD_1", - TRQ_SEL_FMAP_63_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_63_QID_MAX", - TRQ_SEL_FMAP_63_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_63_QID_BASE", - TRQ_SEL_FMAP_63_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_64_field_info[] = { - {"TRQ_SEL_FMAP_64_RSVD_1", - TRQ_SEL_FMAP_64_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_64_QID_MAX", - TRQ_SEL_FMAP_64_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_64_QID_BASE", - TRQ_SEL_FMAP_64_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_65_field_info[] = { - {"TRQ_SEL_FMAP_65_RSVD_1", - TRQ_SEL_FMAP_65_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_65_QID_MAX", - TRQ_SEL_FMAP_65_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_65_QID_BASE", - TRQ_SEL_FMAP_65_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_66_field_info[] = { - {"TRQ_SEL_FMAP_66_RSVD_1", - TRQ_SEL_FMAP_66_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_66_QID_MAX", - TRQ_SEL_FMAP_66_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_66_QID_BASE", - TRQ_SEL_FMAP_66_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_67_field_info[] = { - {"TRQ_SEL_FMAP_67_RSVD_1", - TRQ_SEL_FMAP_67_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_67_QID_MAX", - TRQ_SEL_FMAP_67_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_67_QID_BASE", - TRQ_SEL_FMAP_67_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_68_field_info[] = { - {"TRQ_SEL_FMAP_68_RSVD_1", - TRQ_SEL_FMAP_68_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_68_QID_MAX", - TRQ_SEL_FMAP_68_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_68_QID_BASE", - TRQ_SEL_FMAP_68_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_69_field_info[] = { - {"TRQ_SEL_FMAP_69_RSVD_1", - TRQ_SEL_FMAP_69_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_69_QID_MAX", - TRQ_SEL_FMAP_69_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_69_QID_BASE", - TRQ_SEL_FMAP_69_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_6a_field_info[] = { - {"TRQ_SEL_FMAP_6A_RSVD_1", - TRQ_SEL_FMAP_6A_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_6A_QID_MAX", - TRQ_SEL_FMAP_6A_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_6A_QID_BASE", - TRQ_SEL_FMAP_6A_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_6b_field_info[] = { - {"TRQ_SEL_FMAP_6B_RSVD_1", - TRQ_SEL_FMAP_6B_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_6B_QID_MAX", - TRQ_SEL_FMAP_6B_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_6B_QID_BASE", - TRQ_SEL_FMAP_6B_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_6c_field_info[] = { - {"TRQ_SEL_FMAP_6C_RSVD_1", - TRQ_SEL_FMAP_6C_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_6C_QID_MAX", - TRQ_SEL_FMAP_6C_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_6C_QID_BASE", - TRQ_SEL_FMAP_6C_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_6d_field_info[] = { - {"TRQ_SEL_FMAP_6D_RSVD_1", - TRQ_SEL_FMAP_6D_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_6D_QID_MAX", - TRQ_SEL_FMAP_6D_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_6D_QID_BASE", - TRQ_SEL_FMAP_6D_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_6e_field_info[] = { - {"TRQ_SEL_FMAP_6E_RSVD_1", - TRQ_SEL_FMAP_6E_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_6E_QID_MAX", - TRQ_SEL_FMAP_6E_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_6E_QID_BASE", - TRQ_SEL_FMAP_6E_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_6f_field_info[] = { - {"TRQ_SEL_FMAP_6F_RSVD_1", - TRQ_SEL_FMAP_6F_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_6F_QID_MAX", - TRQ_SEL_FMAP_6F_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_6F_QID_BASE", - TRQ_SEL_FMAP_6F_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_70_field_info[] = { - {"TRQ_SEL_FMAP_70_RSVD_1", - TRQ_SEL_FMAP_70_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_70_QID_MAX", - TRQ_SEL_FMAP_70_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_70_QID_BASE", - TRQ_SEL_FMAP_70_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_71_field_info[] = { - {"TRQ_SEL_FMAP_71_RSVD_1", - TRQ_SEL_FMAP_71_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_71_QID_MAX", - TRQ_SEL_FMAP_71_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_71_QID_BASE", - TRQ_SEL_FMAP_71_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_72_field_info[] = { - {"TRQ_SEL_FMAP_72_RSVD_1", - TRQ_SEL_FMAP_72_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_72_QID_MAX", - TRQ_SEL_FMAP_72_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_72_QID_BASE", - TRQ_SEL_FMAP_72_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_73_field_info[] = { - {"TRQ_SEL_FMAP_73_RSVD_1", - TRQ_SEL_FMAP_73_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_73_QID_MAX", - TRQ_SEL_FMAP_73_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_73_QID_BASE", - TRQ_SEL_FMAP_73_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_74_field_info[] = { - {"TRQ_SEL_FMAP_74_RSVD_1", - TRQ_SEL_FMAP_74_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_74_QID_MAX", - TRQ_SEL_FMAP_74_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_74_QID_BASE", - TRQ_SEL_FMAP_74_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_75_field_info[] = { - {"TRQ_SEL_FMAP_75_RSVD_1", - TRQ_SEL_FMAP_75_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_75_QID_MAX", - TRQ_SEL_FMAP_75_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_75_QID_BASE", - TRQ_SEL_FMAP_75_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_76_field_info[] = { - {"TRQ_SEL_FMAP_76_RSVD_1", - TRQ_SEL_FMAP_76_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_76_QID_MAX", - TRQ_SEL_FMAP_76_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_76_QID_BASE", - TRQ_SEL_FMAP_76_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_77_field_info[] = { - {"TRQ_SEL_FMAP_77_RSVD_1", - TRQ_SEL_FMAP_77_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_77_QID_MAX", - TRQ_SEL_FMAP_77_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_77_QID_BASE", - TRQ_SEL_FMAP_77_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_78_field_info[] = { - {"TRQ_SEL_FMAP_78_RSVD_1", - TRQ_SEL_FMAP_78_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_78_QID_MAX", - TRQ_SEL_FMAP_78_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_78_QID_BASE", - TRQ_SEL_FMAP_78_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_79_field_info[] = { - {"TRQ_SEL_FMAP_79_RSVD_1", - TRQ_SEL_FMAP_79_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_79_QID_MAX", - TRQ_SEL_FMAP_79_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_79_QID_BASE", - TRQ_SEL_FMAP_79_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_7a_field_info[] = { - {"TRQ_SEL_FMAP_7A_RSVD_1", - TRQ_SEL_FMAP_7A_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_7A_QID_MAX", - TRQ_SEL_FMAP_7A_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_7A_QID_BASE", - TRQ_SEL_FMAP_7A_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_7b_field_info[] = { - {"TRQ_SEL_FMAP_7B_RSVD_1", - TRQ_SEL_FMAP_7B_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_7B_QID_MAX", - TRQ_SEL_FMAP_7B_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_7B_QID_BASE", - TRQ_SEL_FMAP_7B_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_7c_field_info[] = { - {"TRQ_SEL_FMAP_7C_RSVD_1", - TRQ_SEL_FMAP_7C_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_7C_QID_MAX", - TRQ_SEL_FMAP_7C_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_7C_QID_BASE", - TRQ_SEL_FMAP_7C_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_7d_field_info[] = { - {"TRQ_SEL_FMAP_7D_RSVD_1", - TRQ_SEL_FMAP_7D_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_7D_QID_MAX", - TRQ_SEL_FMAP_7D_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_7D_QID_BASE", - TRQ_SEL_FMAP_7D_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_7e_field_info[] = { - {"TRQ_SEL_FMAP_7E_RSVD_1", - TRQ_SEL_FMAP_7E_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_7E_QID_MAX", - TRQ_SEL_FMAP_7E_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_7E_QID_BASE", - TRQ_SEL_FMAP_7E_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_7f_field_info[] = { - {"TRQ_SEL_FMAP_7F_RSVD_1", - TRQ_SEL_FMAP_7F_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_7F_QID_MAX", - TRQ_SEL_FMAP_7F_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_7F_QID_BASE", - TRQ_SEL_FMAP_7F_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_80_field_info[] = { - {"TRQ_SEL_FMAP_80_RSVD_1", - TRQ_SEL_FMAP_80_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_80_QID_MAX", - TRQ_SEL_FMAP_80_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_80_QID_BASE", - TRQ_SEL_FMAP_80_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_81_field_info[] = { - {"TRQ_SEL_FMAP_81_RSVD_1", - TRQ_SEL_FMAP_81_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_81_QID_MAX", - TRQ_SEL_FMAP_81_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_81_QID_BASE", - TRQ_SEL_FMAP_81_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_82_field_info[] = { - {"TRQ_SEL_FMAP_82_RSVD_1", - TRQ_SEL_FMAP_82_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_82_QID_MAX", - TRQ_SEL_FMAP_82_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_82_QID_BASE", - TRQ_SEL_FMAP_82_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_83_field_info[] = { - {"TRQ_SEL_FMAP_83_RSVD_1", - TRQ_SEL_FMAP_83_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_83_QID_MAX", - TRQ_SEL_FMAP_83_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_83_QID_BASE", - TRQ_SEL_FMAP_83_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_84_field_info[] = { - {"TRQ_SEL_FMAP_84_RSVD_1", - TRQ_SEL_FMAP_84_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_84_QID_MAX", - TRQ_SEL_FMAP_84_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_84_QID_BASE", - TRQ_SEL_FMAP_84_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_85_field_info[] = { - {"TRQ_SEL_FMAP_85_RSVD_1", - TRQ_SEL_FMAP_85_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_85_QID_MAX", - TRQ_SEL_FMAP_85_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_85_QID_BASE", - TRQ_SEL_FMAP_85_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_86_field_info[] = { - {"TRQ_SEL_FMAP_86_RSVD_1", - TRQ_SEL_FMAP_86_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_86_QID_MAX", - TRQ_SEL_FMAP_86_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_86_QID_BASE", - TRQ_SEL_FMAP_86_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_87_field_info[] = { - {"TRQ_SEL_FMAP_87_RSVD_1", - TRQ_SEL_FMAP_87_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_87_QID_MAX", - TRQ_SEL_FMAP_87_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_87_QID_BASE", - TRQ_SEL_FMAP_87_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_88_field_info[] = { - {"TRQ_SEL_FMAP_88_RSVD_1", - TRQ_SEL_FMAP_88_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_88_QID_MAX", - TRQ_SEL_FMAP_88_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_88_QID_BASE", - TRQ_SEL_FMAP_88_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_89_field_info[] = { - {"TRQ_SEL_FMAP_89_RSVD_1", - TRQ_SEL_FMAP_89_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_89_QID_MAX", - TRQ_SEL_FMAP_89_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_89_QID_BASE", - TRQ_SEL_FMAP_89_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_8a_field_info[] = { - {"TRQ_SEL_FMAP_8A_RSVD_1", - TRQ_SEL_FMAP_8A_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_8A_QID_MAX", - TRQ_SEL_FMAP_8A_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_8A_QID_BASE", - TRQ_SEL_FMAP_8A_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_8b_field_info[] = { - {"TRQ_SEL_FMAP_8B_RSVD_1", - TRQ_SEL_FMAP_8B_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_8B_QID_MAX", - TRQ_SEL_FMAP_8B_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_8B_QID_BASE", - TRQ_SEL_FMAP_8B_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_8c_field_info[] = { - {"TRQ_SEL_FMAP_8C_RSVD_1", - TRQ_SEL_FMAP_8C_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_8C_QID_MAX", - TRQ_SEL_FMAP_8C_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_8C_QID_BASE", - TRQ_SEL_FMAP_8C_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_8d_field_info[] = { - {"TRQ_SEL_FMAP_8D_RSVD_1", - TRQ_SEL_FMAP_8D_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_8D_QID_MAX", - TRQ_SEL_FMAP_8D_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_8D_QID_BASE", - TRQ_SEL_FMAP_8D_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_8e_field_info[] = { - {"TRQ_SEL_FMAP_8E_RSVD_1", - TRQ_SEL_FMAP_8E_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_8E_QID_MAX", - TRQ_SEL_FMAP_8E_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_8E_QID_BASE", - TRQ_SEL_FMAP_8E_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_8f_field_info[] = { - {"TRQ_SEL_FMAP_8F_RSVD_1", - TRQ_SEL_FMAP_8F_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_8F_QID_MAX", - TRQ_SEL_FMAP_8F_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_8F_QID_BASE", - TRQ_SEL_FMAP_8F_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_90_field_info[] = { - {"TRQ_SEL_FMAP_90_RSVD_1", - TRQ_SEL_FMAP_90_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_90_QID_MAX", - TRQ_SEL_FMAP_90_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_90_QID_BASE", - TRQ_SEL_FMAP_90_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_91_field_info[] = { - {"TRQ_SEL_FMAP_91_RSVD_1", - TRQ_SEL_FMAP_91_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_91_QID_MAX", - TRQ_SEL_FMAP_91_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_91_QID_BASE", - TRQ_SEL_FMAP_91_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_92_field_info[] = { - {"TRQ_SEL_FMAP_92_RSVD_1", - TRQ_SEL_FMAP_92_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_92_QID_MAX", - TRQ_SEL_FMAP_92_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_92_QID_BASE", - TRQ_SEL_FMAP_92_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_93_field_info[] = { - {"TRQ_SEL_FMAP_93_RSVD_1", - TRQ_SEL_FMAP_93_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_93_QID_MAX", - TRQ_SEL_FMAP_93_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_93_QID_BASE", - TRQ_SEL_FMAP_93_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_94_field_info[] = { - {"TRQ_SEL_FMAP_94_RSVD_1", - TRQ_SEL_FMAP_94_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_94_QID_MAX", - TRQ_SEL_FMAP_94_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_94_QID_BASE", - TRQ_SEL_FMAP_94_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_95_field_info[] = { - {"TRQ_SEL_FMAP_95_RSVD_1", - TRQ_SEL_FMAP_95_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_95_QID_MAX", - TRQ_SEL_FMAP_95_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_95_QID_BASE", - TRQ_SEL_FMAP_95_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_96_field_info[] = { - {"TRQ_SEL_FMAP_96_RSVD_1", - TRQ_SEL_FMAP_96_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_96_QID_MAX", - TRQ_SEL_FMAP_96_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_96_QID_BASE", - TRQ_SEL_FMAP_96_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_97_field_info[] = { - {"TRQ_SEL_FMAP_97_RSVD_1", - TRQ_SEL_FMAP_97_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_97_QID_MAX", - TRQ_SEL_FMAP_97_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_97_QID_BASE", - TRQ_SEL_FMAP_97_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_98_field_info[] = { - {"TRQ_SEL_FMAP_98_RSVD_1", - TRQ_SEL_FMAP_98_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_98_QID_MAX", - TRQ_SEL_FMAP_98_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_98_QID_BASE", - TRQ_SEL_FMAP_98_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_99_field_info[] = { - {"TRQ_SEL_FMAP_99_RSVD_1", - TRQ_SEL_FMAP_99_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_99_QID_MAX", - TRQ_SEL_FMAP_99_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_99_QID_BASE", - TRQ_SEL_FMAP_99_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_9a_field_info[] = { - {"TRQ_SEL_FMAP_9A_RSVD_1", - TRQ_SEL_FMAP_9A_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_9A_QID_MAX", - TRQ_SEL_FMAP_9A_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_9A_QID_BASE", - TRQ_SEL_FMAP_9A_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_9b_field_info[] = { - {"TRQ_SEL_FMAP_9B_RSVD_1", - TRQ_SEL_FMAP_9B_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_9B_QID_MAX", - TRQ_SEL_FMAP_9B_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_9B_QID_BASE", - TRQ_SEL_FMAP_9B_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_9c_field_info[] = { - {"TRQ_SEL_FMAP_9C_RSVD_1", - TRQ_SEL_FMAP_9C_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_9C_QID_MAX", - TRQ_SEL_FMAP_9C_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_9C_QID_BASE", - TRQ_SEL_FMAP_9C_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_9d_field_info[] = { - {"TRQ_SEL_FMAP_9D_RSVD_1", - TRQ_SEL_FMAP_9D_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_9D_QID_MAX", - TRQ_SEL_FMAP_9D_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_9D_QID_BASE", - TRQ_SEL_FMAP_9D_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_9e_field_info[] = { - {"TRQ_SEL_FMAP_9E_RSVD_1", - TRQ_SEL_FMAP_9E_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_9E_QID_MAX", - TRQ_SEL_FMAP_9E_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_9E_QID_BASE", - TRQ_SEL_FMAP_9E_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_9f_field_info[] = { - {"TRQ_SEL_FMAP_9F_RSVD_1", - TRQ_SEL_FMAP_9F_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_9F_QID_MAX", - TRQ_SEL_FMAP_9F_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_9F_QID_BASE", - TRQ_SEL_FMAP_9F_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_a0_field_info[] = { - {"TRQ_SEL_FMAP_A0_RSVD_1", - TRQ_SEL_FMAP_A0_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_A0_QID_MAX", - TRQ_SEL_FMAP_A0_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_A0_QID_BASE", - TRQ_SEL_FMAP_A0_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_a1_field_info[] = { - {"TRQ_SEL_FMAP_A1_RSVD_1", - TRQ_SEL_FMAP_A1_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_A1_QID_MAX", - TRQ_SEL_FMAP_A1_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_A1_QID_BASE", - TRQ_SEL_FMAP_A1_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_a2_field_info[] = { - {"TRQ_SEL_FMAP_A2_RSVD_1", - TRQ_SEL_FMAP_A2_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_A2_QID_MAX", - TRQ_SEL_FMAP_A2_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_A2_QID_BASE", - TRQ_SEL_FMAP_A2_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_a3_field_info[] = { - {"TRQ_SEL_FMAP_A3_RSVD_1", - TRQ_SEL_FMAP_A3_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_A3_QID_MAX", - TRQ_SEL_FMAP_A3_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_A3_QID_BASE", - TRQ_SEL_FMAP_A3_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_a4_field_info[] = { - {"TRQ_SEL_FMAP_A4_RSVD_1", - TRQ_SEL_FMAP_A4_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_A4_QID_MAX", - TRQ_SEL_FMAP_A4_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_A4_QID_BASE", - TRQ_SEL_FMAP_A4_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_a5_field_info[] = { - {"TRQ_SEL_FMAP_A5_RSVD_1", - TRQ_SEL_FMAP_A5_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_A5_QID_MAX", - TRQ_SEL_FMAP_A5_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_A5_QID_BASE", - TRQ_SEL_FMAP_A5_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_a6_field_info[] = { - {"TRQ_SEL_FMAP_A6_RSVD_1", - TRQ_SEL_FMAP_A6_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_A6_QID_MAX", - TRQ_SEL_FMAP_A6_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_A6_QID_BASE", - TRQ_SEL_FMAP_A6_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_a7_field_info[] = { - {"TRQ_SEL_FMAP_A7_RSVD_1", - TRQ_SEL_FMAP_A7_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_A7_QID_MAX", - TRQ_SEL_FMAP_A7_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_A7_QID_BASE", - TRQ_SEL_FMAP_A7_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_a8_field_info[] = { - {"TRQ_SEL_FMAP_A8_RSVD_1", - TRQ_SEL_FMAP_A8_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_A8_QID_MAX", - TRQ_SEL_FMAP_A8_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_A8_QID_BASE", - TRQ_SEL_FMAP_A8_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_a9_field_info[] = { - {"TRQ_SEL_FMAP_A9_RSVD_1", - TRQ_SEL_FMAP_A9_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_A9_QID_MAX", - TRQ_SEL_FMAP_A9_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_A9_QID_BASE", - TRQ_SEL_FMAP_A9_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_aa_field_info[] = { - {"TRQ_SEL_FMAP_AA_RSVD_1", - TRQ_SEL_FMAP_AA_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_AA_QID_MAX", - TRQ_SEL_FMAP_AA_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_AA_QID_BASE", - TRQ_SEL_FMAP_AA_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_ab_field_info[] = { - {"TRQ_SEL_FMAP_AB_RSVD_1", - TRQ_SEL_FMAP_AB_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_AB_QID_MAX", - TRQ_SEL_FMAP_AB_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_AB_QID_BASE", - TRQ_SEL_FMAP_AB_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_ac_field_info[] = { - {"TRQ_SEL_FMAP_AC_RSVD_1", - TRQ_SEL_FMAP_AC_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_AC_QID_MAX", - TRQ_SEL_FMAP_AC_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_AC_QID_BASE", - TRQ_SEL_FMAP_AC_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_ad_field_info[] = { - {"TRQ_SEL_FMAP_AD_RSVD_1", - TRQ_SEL_FMAP_AD_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_AD_QID_MAX", - TRQ_SEL_FMAP_AD_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_AD_QID_BASE", - TRQ_SEL_FMAP_AD_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_ae_field_info[] = { - {"TRQ_SEL_FMAP_AE_RSVD_1", - TRQ_SEL_FMAP_AE_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_AE_QID_MAX", - TRQ_SEL_FMAP_AE_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_AE_QID_BASE", - TRQ_SEL_FMAP_AE_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_af_field_info[] = { - {"TRQ_SEL_FMAP_AF_RSVD_1", - TRQ_SEL_FMAP_AF_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_AF_QID_MAX", - TRQ_SEL_FMAP_AF_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_AF_QID_BASE", - TRQ_SEL_FMAP_AF_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_b0_field_info[] = { - {"TRQ_SEL_FMAP_B0_RSVD_1", - TRQ_SEL_FMAP_B0_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_B0_QID_MAX", - TRQ_SEL_FMAP_B0_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_B0_QID_BASE", - TRQ_SEL_FMAP_B0_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_b1_field_info[] = { - {"TRQ_SEL_FMAP_B1_RSVD_1", - TRQ_SEL_FMAP_B1_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_B1_QID_MAX", - TRQ_SEL_FMAP_B1_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_B1_QID_BASE", - TRQ_SEL_FMAP_B1_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_b2_field_info[] = { - {"TRQ_SEL_FMAP_B2_RSVD_1", - TRQ_SEL_FMAP_B2_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_B2_QID_MAX", - TRQ_SEL_FMAP_B2_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_B2_QID_BASE", - TRQ_SEL_FMAP_B2_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_b3_field_info[] = { - {"TRQ_SEL_FMAP_B3_RSVD_1", - TRQ_SEL_FMAP_B3_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_B3_QID_MAX", - TRQ_SEL_FMAP_B3_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_B3_QID_BASE", - TRQ_SEL_FMAP_B3_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_b4_field_info[] = { - {"TRQ_SEL_FMAP_B4_RSVD_1", - TRQ_SEL_FMAP_B4_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_B4_QID_MAX", - TRQ_SEL_FMAP_B4_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_B4_QID_BASE", - TRQ_SEL_FMAP_B4_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_b5_field_info[] = { - {"TRQ_SEL_FMAP_B5_RSVD_1", - TRQ_SEL_FMAP_B5_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_B5_QID_MAX", - TRQ_SEL_FMAP_B5_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_B5_QID_BASE", - TRQ_SEL_FMAP_B5_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_b6_field_info[] = { - {"TRQ_SEL_FMAP_B6_RSVD_1", - TRQ_SEL_FMAP_B6_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_B6_QID_MAX", - TRQ_SEL_FMAP_B6_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_B6_QID_BASE", - TRQ_SEL_FMAP_B6_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_b7_field_info[] = { - {"TRQ_SEL_FMAP_B7_RSVD_1", - TRQ_SEL_FMAP_B7_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_B7_QID_MAX", - TRQ_SEL_FMAP_B7_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_B7_QID_BASE", - TRQ_SEL_FMAP_B7_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_b8_field_info[] = { - {"TRQ_SEL_FMAP_B8_RSVD_1", - TRQ_SEL_FMAP_B8_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_B8_QID_MAX", - TRQ_SEL_FMAP_B8_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_B8_QID_BASE", - TRQ_SEL_FMAP_B8_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_b9_field_info[] = { - {"TRQ_SEL_FMAP_B9_RSVD_1", - TRQ_SEL_FMAP_B9_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_B9_QID_MAX", - TRQ_SEL_FMAP_B9_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_B9_QID_BASE", - TRQ_SEL_FMAP_B9_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_ba_field_info[] = { - {"TRQ_SEL_FMAP_BA_RSVD_1", - TRQ_SEL_FMAP_BA_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_BA_QID_MAX", - TRQ_SEL_FMAP_BA_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_BA_QID_BASE", - TRQ_SEL_FMAP_BA_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_bb_field_info[] = { - {"TRQ_SEL_FMAP_BB_RSVD_1", - TRQ_SEL_FMAP_BB_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_BB_QID_MAX", - TRQ_SEL_FMAP_BB_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_BB_QID_BASE", - TRQ_SEL_FMAP_BB_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_bc_field_info[] = { - {"TRQ_SEL_FMAP_BC_RSVD_1", - TRQ_SEL_FMAP_BC_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_BC_QID_MAX", - TRQ_SEL_FMAP_BC_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_BC_QID_BASE", - TRQ_SEL_FMAP_BC_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_bd_field_info[] = { - {"TRQ_SEL_FMAP_BD_RSVD_1", - TRQ_SEL_FMAP_BD_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_BD_QID_MAX", - TRQ_SEL_FMAP_BD_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_BD_QID_BASE", - TRQ_SEL_FMAP_BD_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_be_field_info[] = { - {"TRQ_SEL_FMAP_BE_RSVD_1", - TRQ_SEL_FMAP_BE_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_BE_QID_MAX", - TRQ_SEL_FMAP_BE_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_BE_QID_BASE", - TRQ_SEL_FMAP_BE_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_bf_field_info[] = { - {"TRQ_SEL_FMAP_BF_RSVD_1", - TRQ_SEL_FMAP_BF_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_BF_QID_MAX", - TRQ_SEL_FMAP_BF_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_BF_QID_BASE", - TRQ_SEL_FMAP_BF_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_c0_field_info[] = { - {"TRQ_SEL_FMAP_C0_RSVD_1", - TRQ_SEL_FMAP_C0_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_C0_QID_MAX", - TRQ_SEL_FMAP_C0_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_C0_QID_BASE", - TRQ_SEL_FMAP_C0_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_c1_field_info[] = { - {"TRQ_SEL_FMAP_C1_RSVD_1", - TRQ_SEL_FMAP_C1_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_C1_QID_MAX", - TRQ_SEL_FMAP_C1_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_C1_QID_BASE", - TRQ_SEL_FMAP_C1_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_c2_field_info[] = { - {"TRQ_SEL_FMAP_C2_RSVD_1", - TRQ_SEL_FMAP_C2_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_C2_QID_MAX", - TRQ_SEL_FMAP_C2_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_C2_QID_BASE", - TRQ_SEL_FMAP_C2_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_c3_field_info[] = { - {"TRQ_SEL_FMAP_C3_RSVD_1", - TRQ_SEL_FMAP_C3_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_C3_QID_MAX", - TRQ_SEL_FMAP_C3_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_C3_QID_BASE", - TRQ_SEL_FMAP_C3_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_c4_field_info[] = { - {"TRQ_SEL_FMAP_C4_RSVD_1", - TRQ_SEL_FMAP_C4_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_C4_QID_MAX", - TRQ_SEL_FMAP_C4_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_C4_QID_BASE", - TRQ_SEL_FMAP_C4_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_c5_field_info[] = { - {"TRQ_SEL_FMAP_C5_RSVD_1", - TRQ_SEL_FMAP_C5_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_C5_QID_MAX", - TRQ_SEL_FMAP_C5_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_C5_QID_BASE", - TRQ_SEL_FMAP_C5_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_c6_field_info[] = { - {"TRQ_SEL_FMAP_C6_RSVD_1", - TRQ_SEL_FMAP_C6_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_C6_QID_MAX", - TRQ_SEL_FMAP_C6_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_C6_QID_BASE", - TRQ_SEL_FMAP_C6_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_c7_field_info[] = { - {"TRQ_SEL_FMAP_C7_RSVD_1", - TRQ_SEL_FMAP_C7_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_C7_QID_MAX", - TRQ_SEL_FMAP_C7_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_C7_QID_BASE", - TRQ_SEL_FMAP_C7_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_c8_field_info[] = { - {"TRQ_SEL_FMAP_C8_RSVD_1", - TRQ_SEL_FMAP_C8_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_C8_QID_MAX", - TRQ_SEL_FMAP_C8_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_C8_QID_BASE", - TRQ_SEL_FMAP_C8_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_c9_field_info[] = { - {"TRQ_SEL_FMAP_C9_RSVD_1", - TRQ_SEL_FMAP_C9_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_C9_QID_MAX", - TRQ_SEL_FMAP_C9_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_C9_QID_BASE", - TRQ_SEL_FMAP_C9_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_ca_field_info[] = { - {"TRQ_SEL_FMAP_CA_RSVD_1", - TRQ_SEL_FMAP_CA_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_CA_QID_MAX", - TRQ_SEL_FMAP_CA_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_CA_QID_BASE", - TRQ_SEL_FMAP_CA_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_cb_field_info[] = { - {"TRQ_SEL_FMAP_CB_RSVD_1", - TRQ_SEL_FMAP_CB_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_CB_QID_MAX", - TRQ_SEL_FMAP_CB_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_CB_QID_BASE", - TRQ_SEL_FMAP_CB_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_cc_field_info[] = { - {"TRQ_SEL_FMAP_CC_RSVD_1", - TRQ_SEL_FMAP_CC_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_CC_QID_MAX", - TRQ_SEL_FMAP_CC_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_CC_QID_BASE", - TRQ_SEL_FMAP_CC_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_cd_field_info[] = { - {"TRQ_SEL_FMAP_CD_RSVD_1", - TRQ_SEL_FMAP_CD_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_CD_QID_MAX", - TRQ_SEL_FMAP_CD_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_CD_QID_BASE", - TRQ_SEL_FMAP_CD_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_ce_field_info[] = { - {"TRQ_SEL_FMAP_CE_RSVD_1", - TRQ_SEL_FMAP_CE_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_CE_QID_MAX", - TRQ_SEL_FMAP_CE_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_CE_QID_BASE", - TRQ_SEL_FMAP_CE_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_cf_field_info[] = { - {"TRQ_SEL_FMAP_CF_RSVD_1", - TRQ_SEL_FMAP_CF_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_CF_QID_MAX", - TRQ_SEL_FMAP_CF_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_CF_QID_BASE", - TRQ_SEL_FMAP_CF_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_d0_field_info[] = { - {"TRQ_SEL_FMAP_D0_RSVD_1", - TRQ_SEL_FMAP_D0_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_D0_QID_MAX", - TRQ_SEL_FMAP_D0_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_D0_QID_BASE", - TRQ_SEL_FMAP_D0_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_d1_field_info[] = { - {"TRQ_SEL_FMAP_D1_RSVD_1", - TRQ_SEL_FMAP_D1_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_D1_QID_MAX", - TRQ_SEL_FMAP_D1_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_D1_QID_BASE", - TRQ_SEL_FMAP_D1_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_d2_field_info[] = { - {"TRQ_SEL_FMAP_D2_RSVD_1", - TRQ_SEL_FMAP_D2_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_D2_QID_MAX", - TRQ_SEL_FMAP_D2_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_D2_QID_BASE", - TRQ_SEL_FMAP_D2_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_d3_field_info[] = { - {"TRQ_SEL_FMAP_D3_RSVD_1", - TRQ_SEL_FMAP_D3_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_D3_QID_MAX", - TRQ_SEL_FMAP_D3_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_D3_QID_BASE", - TRQ_SEL_FMAP_D3_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_d4_field_info[] = { - {"TRQ_SEL_FMAP_D4_RSVD_1", - TRQ_SEL_FMAP_D4_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_D4_QID_MAX", - TRQ_SEL_FMAP_D4_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_D4_QID_BASE", - TRQ_SEL_FMAP_D4_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_d5_field_info[] = { - {"TRQ_SEL_FMAP_D5_RSVD_1", - TRQ_SEL_FMAP_D5_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_D5_QID_MAX", - TRQ_SEL_FMAP_D5_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_D5_QID_BASE", - TRQ_SEL_FMAP_D5_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_d6_field_info[] = { - {"TRQ_SEL_FMAP_D6_RSVD_1", - TRQ_SEL_FMAP_D6_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_D6_QID_MAX", - TRQ_SEL_FMAP_D6_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_D6_QID_BASE", - TRQ_SEL_FMAP_D6_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_d7_field_info[] = { - {"TRQ_SEL_FMAP_D7_RSVD_1", - TRQ_SEL_FMAP_D7_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_D7_QID_MAX", - TRQ_SEL_FMAP_D7_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_D7_QID_BASE", - TRQ_SEL_FMAP_D7_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_d8_field_info[] = { - {"TRQ_SEL_FMAP_D8_RSVD_1", - TRQ_SEL_FMAP_D8_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_D8_QID_MAX", - TRQ_SEL_FMAP_D8_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_D8_QID_BASE", - TRQ_SEL_FMAP_D8_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_d9_field_info[] = { - {"TRQ_SEL_FMAP_D9_RSVD_1", - TRQ_SEL_FMAP_D9_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_D9_QID_MAX", - TRQ_SEL_FMAP_D9_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_D9_QID_BASE", - TRQ_SEL_FMAP_D9_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_da_field_info[] = { - {"TRQ_SEL_FMAP_DA_RSVD_1", - TRQ_SEL_FMAP_DA_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_DA_QID_MAX", - TRQ_SEL_FMAP_DA_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_DA_QID_BASE", - TRQ_SEL_FMAP_DA_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_db_field_info[] = { - {"TRQ_SEL_FMAP_DB_RSVD_1", - TRQ_SEL_FMAP_DB_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_DB_QID_MAX", - TRQ_SEL_FMAP_DB_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_DB_QID_BASE", - TRQ_SEL_FMAP_DB_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_dc_field_info[] = { - {"TRQ_SEL_FMAP_DC_RSVD_1", - TRQ_SEL_FMAP_DC_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_DC_QID_MAX", - TRQ_SEL_FMAP_DC_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_DC_QID_BASE", - TRQ_SEL_FMAP_DC_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_dd_field_info[] = { - {"TRQ_SEL_FMAP_DD_RSVD_1", - TRQ_SEL_FMAP_DD_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_DD_QID_MAX", - TRQ_SEL_FMAP_DD_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_DD_QID_BASE", - TRQ_SEL_FMAP_DD_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_de_field_info[] = { - {"TRQ_SEL_FMAP_DE_RSVD_1", - TRQ_SEL_FMAP_DE_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_DE_QID_MAX", - TRQ_SEL_FMAP_DE_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_DE_QID_BASE", - TRQ_SEL_FMAP_DE_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_df_field_info[] = { - {"TRQ_SEL_FMAP_DF_RSVD_1", - TRQ_SEL_FMAP_DF_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_DF_QID_MAX", - TRQ_SEL_FMAP_DF_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_DF_QID_BASE", - TRQ_SEL_FMAP_DF_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_e0_field_info[] = { - {"TRQ_SEL_FMAP_E0_RSVD_1", - TRQ_SEL_FMAP_E0_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_E0_QID_MAX", - TRQ_SEL_FMAP_E0_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_E0_QID_BASE", - TRQ_SEL_FMAP_E0_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_e1_field_info[] = { - {"TRQ_SEL_FMAP_E1_RSVD_1", - TRQ_SEL_FMAP_E1_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_E1_QID_MAX", - TRQ_SEL_FMAP_E1_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_E1_QID_BASE", - TRQ_SEL_FMAP_E1_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_e2_field_info[] = { - {"TRQ_SEL_FMAP_E2_RSVD_1", - TRQ_SEL_FMAP_E2_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_E2_QID_MAX", - TRQ_SEL_FMAP_E2_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_E2_QID_BASE", - TRQ_SEL_FMAP_E2_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_e3_field_info[] = { - {"TRQ_SEL_FMAP_E3_RSVD_1", - TRQ_SEL_FMAP_E3_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_E3_QID_MAX", - TRQ_SEL_FMAP_E3_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_E3_QID_BASE", - TRQ_SEL_FMAP_E3_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_e4_field_info[] = { - {"TRQ_SEL_FMAP_E4_RSVD_1", - TRQ_SEL_FMAP_E4_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_E4_QID_MAX", - TRQ_SEL_FMAP_E4_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_E4_QID_BASE", - TRQ_SEL_FMAP_E4_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_e5_field_info[] = { - {"TRQ_SEL_FMAP_E5_RSVD_1", - TRQ_SEL_FMAP_E5_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_E5_QID_MAX", - TRQ_SEL_FMAP_E5_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_E5_QID_BASE", - TRQ_SEL_FMAP_E5_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_e6_field_info[] = { - {"TRQ_SEL_FMAP_E6_RSVD_1", - TRQ_SEL_FMAP_E6_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_E6_QID_MAX", - TRQ_SEL_FMAP_E6_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_E6_QID_BASE", - TRQ_SEL_FMAP_E6_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_e7_field_info[] = { - {"TRQ_SEL_FMAP_E7_RSVD_1", - TRQ_SEL_FMAP_E7_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_E7_QID_MAX", - TRQ_SEL_FMAP_E7_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_E7_QID_BASE", - TRQ_SEL_FMAP_E7_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_e8_field_info[] = { - {"TRQ_SEL_FMAP_E8_RSVD_1", - TRQ_SEL_FMAP_E8_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_E8_QID_MAX", - TRQ_SEL_FMAP_E8_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_E8_QID_BASE", - TRQ_SEL_FMAP_E8_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_e9_field_info[] = { - {"TRQ_SEL_FMAP_E9_RSVD_1", - TRQ_SEL_FMAP_E9_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_E9_QID_MAX", - TRQ_SEL_FMAP_E9_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_E9_QID_BASE", - TRQ_SEL_FMAP_E9_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_ea_field_info[] = { - {"TRQ_SEL_FMAP_EA_RSVD_1", - TRQ_SEL_FMAP_EA_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_EA_QID_MAX", - TRQ_SEL_FMAP_EA_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_EA_QID_BASE", - TRQ_SEL_FMAP_EA_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_eb_field_info[] = { - {"TRQ_SEL_FMAP_EB_RSVD_1", - TRQ_SEL_FMAP_EB_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_EB_QID_MAX", - TRQ_SEL_FMAP_EB_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_EB_QID_BASE", - TRQ_SEL_FMAP_EB_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_ec_field_info[] = { - {"TRQ_SEL_FMAP_EC_RSVD_1", - TRQ_SEL_FMAP_EC_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_EC_QID_MAX", - TRQ_SEL_FMAP_EC_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_EC_QID_BASE", - TRQ_SEL_FMAP_EC_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_ed_field_info[] = { - {"TRQ_SEL_FMAP_ED_RSVD_1", - TRQ_SEL_FMAP_ED_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_ED_QID_MAX", - TRQ_SEL_FMAP_ED_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_ED_QID_BASE", - TRQ_SEL_FMAP_ED_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_ee_field_info[] = { - {"TRQ_SEL_FMAP_EE_RSVD_1", - TRQ_SEL_FMAP_EE_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_EE_QID_MAX", - TRQ_SEL_FMAP_EE_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_EE_QID_BASE", - TRQ_SEL_FMAP_EE_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_ef_field_info[] = { - {"TRQ_SEL_FMAP_EF_RSVD_1", - TRQ_SEL_FMAP_EF_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_EF_QID_MAX", - TRQ_SEL_FMAP_EF_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_EF_QID_BASE", - TRQ_SEL_FMAP_EF_QID_BASE_MASK}, -}; - - -static struct regfield_info - trq_sel_fmap_f0_field_info[] = { - {"TRQ_SEL_FMAP_F0_RSVD_1", - TRQ_SEL_FMAP_F0_RSVD_1_MASK}, - {"TRQ_SEL_FMAP_F0_QID_MAX", - TRQ_SEL_FMAP_F0_QID_MAX_MASK}, - {"TRQ_SEL_FMAP_F0_QID_BASE", - TRQ_SEL_FMAP_F0_QID_BASE_MASK}, -}; - - -static struct regfield_info - ind_ctxt_data_3_field_info[] = { - {"IND_CTXT_DATA_3_DATA", - IND_CTXT_DATA_3_DATA_MASK}, -}; - - -static struct regfield_info - ind_ctxt_data_2_field_info[] = { - {"IND_CTXT_DATA_2_DATA", - IND_CTXT_DATA_2_DATA_MASK}, -}; - - -static struct regfield_info - ind_ctxt_data_1_field_info[] = { - {"IND_CTXT_DATA_1_DATA", - IND_CTXT_DATA_1_DATA_MASK}, -}; - - -static struct regfield_info - ind_ctxt_data_0_field_info[] = { - {"IND_CTXT_DATA_0_DATA", - IND_CTXT_DATA_0_DATA_MASK}, -}; - - -static struct regfield_info - ind_ctxt3_field_info[] = { - {"IND_CTXT3", - IND_CTXT3_MASK}, -}; - - -static struct regfield_info - ind_ctxt2_field_info[] = { - {"IND_CTXT2", - IND_CTXT2_MASK}, -}; - - -static struct regfield_info - ind_ctxt1_field_info[] = { - {"IND_CTXT1", - IND_CTXT1_MASK}, -}; - - -static struct regfield_info - ind_ctxt0_field_info[] = { - {"IND_CTXT0", - IND_CTXT0_MASK}, -}; - - -static struct regfield_info - ind_ctxt_cmd_field_info[] = { - {"IND_CTXT_CMD_RSVD_1", - IND_CTXT_CMD_RSVD_1_MASK}, - {"IND_CTXT_CMD_QID", - IND_CTXT_CMD_QID_MASK}, - {"IND_CTXT_CMD_OP", - IND_CTXT_CMD_OP_MASK}, - {"IND_CTXT_CMD_SET", - IND_CTXT_CMD_SET_MASK}, - {"IND_CTXT_CMD_BUSY", - IND_CTXT_CMD_BUSY_MASK}, -}; - - -static struct regfield_info - c2h_timer_cnt_1_field_info[] = { - {"C2H_TIMER_CNT_1_RSVD_1", - C2H_TIMER_CNT_1_RSVD_1_MASK}, - {"C2H_TIMER_CNT_1", - C2H_TIMER_CNT_1_MASK}, -}; - - -static struct regfield_info - c2h_timer_cnt_2_field_info[] = { - {"C2H_TIMER_CNT_2_RSVD_1", - C2H_TIMER_CNT_2_RSVD_1_MASK}, - {"C2H_TIMER_CNT_2", - C2H_TIMER_CNT_2_MASK}, -}; - - -static struct regfield_info - c2h_timer_cnt_3_field_info[] = { - {"C2H_TIMER_CNT_3_RSVD_1", - C2H_TIMER_CNT_3_RSVD_1_MASK}, - {"C2H_TIMER_CNT_3", - C2H_TIMER_CNT_3_MASK}, -}; - - -static struct regfield_info - c2h_timer_cnt_4_field_info[] = { - {"C2H_TIMER_CNT_4_RSVD_1", - C2H_TIMER_CNT_4_RSVD_1_MASK}, - {"C2H_TIMER_CNT_4", - C2H_TIMER_CNT_4_MASK}, -}; - - -static struct regfield_info - c2h_timer_cnt_5_field_info[] = { - {"C2H_TIMER_CNT_5_RSVD_1", - C2H_TIMER_CNT_5_RSVD_1_MASK}, - {"C2H_TIMER_CNT_5", - C2H_TIMER_CNT_5_MASK}, -}; - - -static struct regfield_info - c2h_timer_cnt_6_field_info[] = { - {"C2H_TIMER_CNT_6_RSVD_1", - C2H_TIMER_CNT_6_RSVD_1_MASK}, - {"C2H_TIMER_CNT_6", - C2H_TIMER_CNT_6_MASK}, -}; - - -static struct regfield_info - c2h_timer_cnt_7_field_info[] = { - {"C2H_TIMER_CNT_7_RSVD_1", - C2H_TIMER_CNT_7_RSVD_1_MASK}, - {"C2H_TIMER_CNT_7", - C2H_TIMER_CNT_7_MASK}, -}; - - -static struct regfield_info - c2h_timer_cnt_8_field_info[] = { - {"C2H_TIMER_CNT_8_RSVD_1", - C2H_TIMER_CNT_8_RSVD_1_MASK}, - {"C2H_TIMER_CNT_8", - C2H_TIMER_CNT_8_MASK}, -}; - - -static struct regfield_info - c2h_timer_cnt_9_field_info[] = { - {"C2H_TIMER_CNT_9_RSVD_1", - C2H_TIMER_CNT_9_RSVD_1_MASK}, - {"C2H_TIMER_CNT_9", - C2H_TIMER_CNT_9_MASK}, -}; - - -static struct regfield_info - c2h_timer_cnt_a_field_info[] = { - {"C2H_TIMER_CNT_A_RSVD_1", - C2H_TIMER_CNT_A_RSVD_1_MASK}, - {"C2H_TIMER_CNT_A", - C2H_TIMER_CNT_A_MASK}, -}; - - -static struct regfield_info - c2h_timer_cnt_b_field_info[] = { - {"C2H_TIMER_CNT_B_RSVD_1", - C2H_TIMER_CNT_B_RSVD_1_MASK}, - {"C2H_TIMER_CNT_B", - C2H_TIMER_CNT_B_MASK}, -}; - - -static struct regfield_info - c2h_timer_cnt_c_field_info[] = { - {"C2H_TIMER_CNT_C_RSVD_1", - C2H_TIMER_CNT_C_RSVD_1_MASK}, - {"C2H_TIMER_CNT_C", - C2H_TIMER_CNT_C_MASK}, -}; - - -static struct regfield_info - c2h_timer_cnt_d_field_info[] = { - {"C2H_TIMER_CNT_D_RSVD_1", - C2H_TIMER_CNT_D_RSVD_1_MASK}, - {"C2H_TIMER_CNT_D", - C2H_TIMER_CNT_D_MASK}, -}; - - -static struct regfield_info - c2h_timer_cnt_e_field_info[] = { - {"C2H_TIMER_CNT_E_RSVD_1", - C2H_TIMER_CNT_E_RSVD_1_MASK}, - {"C2H_TIMER_CNT_E", - C2H_TIMER_CNT_E_MASK}, -}; - - -static struct regfield_info - c2h_timer_cnt_f_field_info[] = { - {"C2H_TIMER_CNT_F_RSVD_1", - C2H_TIMER_CNT_F_RSVD_1_MASK}, - {"C2H_TIMER_CNT_F", - C2H_TIMER_CNT_F_MASK}, -}; - - -static struct regfield_info - c2h_timer_cnt_10_field_info[] = { - {"C2H_TIMER_CNT_10_RSVD_1", - C2H_TIMER_CNT_10_RSVD_1_MASK}, - {"C2H_TIMER_CNT_10", - C2H_TIMER_CNT_10_MASK}, -}; - - -static struct regfield_info - c2h_cnt_th_1_field_info[] = { - {"C2H_CNT_TH_1_RSVD_1", - C2H_CNT_TH_1_RSVD_1_MASK}, - {"C2H_CNT_TH_1_THESHOLD_CNT", - C2H_CNT_TH_1_THESHOLD_CNT_MASK}, -}; - - -static struct regfield_info - c2h_cnt_th_2_field_info[] = { - {"C2H_CNT_TH_2_RSVD_1", - C2H_CNT_TH_2_RSVD_1_MASK}, - {"C2H_CNT_TH_2_THESHOLD_CNT", - C2H_CNT_TH_2_THESHOLD_CNT_MASK}, -}; - - -static struct regfield_info - c2h_cnt_th_3_field_info[] = { - {"C2H_CNT_TH_3_RSVD_1", - C2H_CNT_TH_3_RSVD_1_MASK}, - {"C2H_CNT_TH_3_THESHOLD_CNT", - C2H_CNT_TH_3_THESHOLD_CNT_MASK}, -}; - - -static struct regfield_info - c2h_cnt_th_4_field_info[] = { - {"C2H_CNT_TH_4_RSVD_1", - C2H_CNT_TH_4_RSVD_1_MASK}, - {"C2H_CNT_TH_4_THESHOLD_CNT", - C2H_CNT_TH_4_THESHOLD_CNT_MASK}, -}; - - -static struct regfield_info - c2h_cnt_th_5_field_info[] = { - {"C2H_CNT_TH_5_RSVD_1", - C2H_CNT_TH_5_RSVD_1_MASK}, - {"C2H_CNT_TH_5_THESHOLD_CNT", - C2H_CNT_TH_5_THESHOLD_CNT_MASK}, -}; - - -static struct regfield_info - c2h_cnt_th_6_field_info[] = { - {"C2H_CNT_TH_6_RSVD_1", - C2H_CNT_TH_6_RSVD_1_MASK}, - {"C2H_CNT_TH_6_THESHOLD_CNT", - C2H_CNT_TH_6_THESHOLD_CNT_MASK}, -}; - - -static struct regfield_info - c2h_cnt_th_7_field_info[] = { - {"C2H_CNT_TH_7_RSVD_1", - C2H_CNT_TH_7_RSVD_1_MASK}, - {"C2H_CNT_TH_7_THESHOLD_CNT", - C2H_CNT_TH_7_THESHOLD_CNT_MASK}, -}; - - -static struct regfield_info - c2h_cnt_th_8_field_info[] = { - {"C2H_CNT_TH_8_RSVD_1", - C2H_CNT_TH_8_RSVD_1_MASK}, - {"C2H_CNT_TH_8_THESHOLD_CNT", - C2H_CNT_TH_8_THESHOLD_CNT_MASK}, -}; - - -static struct regfield_info - c2h_cnt_th_9_field_info[] = { - {"C2H_CNT_TH_9_RSVD_1", - C2H_CNT_TH_9_RSVD_1_MASK}, - {"C2H_CNT_TH_9_THESHOLD_CNT", - C2H_CNT_TH_9_THESHOLD_CNT_MASK}, -}; - - -static struct regfield_info - c2h_cnt_th_a_field_info[] = { - {"C2H_CNT_TH_A_RSVD_1", - C2H_CNT_TH_A_RSVD_1_MASK}, - {"C2H_CNT_TH_A_THESHOLD_CNT", - C2H_CNT_TH_A_THESHOLD_CNT_MASK}, -}; - - -static struct regfield_info - c2h_cnt_th_b_field_info[] = { - {"C2H_CNT_TH_B_RSVD_1", - C2H_CNT_TH_B_RSVD_1_MASK}, - {"C2H_CNT_TH_B_THESHOLD_CNT", - C2H_CNT_TH_B_THESHOLD_CNT_MASK}, -}; - - -static struct regfield_info - c2h_cnt_th_c_field_info[] = { - {"C2H_CNT_TH_C_RSVD_1", - C2H_CNT_TH_C_RSVD_1_MASK}, - {"C2H_CNT_TH_C_THESHOLD_CNT", - C2H_CNT_TH_C_THESHOLD_CNT_MASK}, -}; - - -static struct regfield_info - c2h_cnt_th_d_field_info[] = { - {"C2H_CNT_TH_D_RSVD_1", - C2H_CNT_TH_D_RSVD_1_MASK}, - {"C2H_CNT_TH_D_THESHOLD_CNT", - C2H_CNT_TH_D_THESHOLD_CNT_MASK}, -}; - - -static struct regfield_info - c2h_cnt_th_e_field_info[] = { - {"C2H_CNT_TH_E_RSVD_1", - C2H_CNT_TH_E_RSVD_1_MASK}, - {"C2H_CNT_TH_E_THESHOLD_CNT", - C2H_CNT_TH_E_THESHOLD_CNT_MASK}, -}; - - -static struct regfield_info - c2h_cnt_th_f_field_info[] = { - {"C2H_CNT_TH_F_RSVD_1", - C2H_CNT_TH_F_RSVD_1_MASK}, - {"C2H_CNT_TH_F_THESHOLD_CNT", - C2H_CNT_TH_F_THESHOLD_CNT_MASK}, -}; - - -static struct regfield_info - c2h_cnt_th_10_field_info[] = { - {"C2H_CNT_TH_10_RSVD_1", - C2H_CNT_TH_10_RSVD_1_MASK}, - {"C2H_CNT_TH_10_THESHOLD_CNT", - C2H_CNT_TH_10_THESHOLD_CNT_MASK}, -}; - - -static struct regfield_info - c2h_qid2vec_map_qid_field_info[] = { - {"C2H_QID2VEC_MAP_QID_RSVD_1", - C2H_QID2VEC_MAP_QID_RSVD_1_MASK}, - {"C2H_QID2VEC_MAP_QID_QID", - C2H_QID2VEC_MAP_QID_QID_MASK}, -}; - - -static struct regfield_info - c2h_qid2vec_map_field_info[] = { - {"C2H_QID2VEC_MAP_RSVD_1", - C2H_QID2VEC_MAP_RSVD_1_MASK}, - {"C2H_QID2VEC_MAP_H2C_EN_COAL", - C2H_QID2VEC_MAP_H2C_EN_COAL_MASK}, - {"C2H_QID2VEC_MAP_H2C_VECTOR", - C2H_QID2VEC_MAP_H2C_VECTOR_MASK}, - {"C2H_QID2VEC_MAP_C2H_EN_COAL", - C2H_QID2VEC_MAP_C2H_EN_COAL_MASK}, - {"C2H_QID2VEC_MAP_C2H_VECTOR", - C2H_QID2VEC_MAP_C2H_VECTOR_MASK}, -}; - - -static struct regfield_info - c2h_stat_s_axis_c2h_accepted_field_info[] = { - {"C2H_STAT_S_AXIS_C2H_ACCEPTED", - C2H_STAT_S_AXIS_C2H_ACCEPTED_MASK}, -}; - - -static struct regfield_info - c2h_stat_s_axis_wrb_accepted_field_info[] = { - {"C2H_STAT_S_AXIS_WRB_ACCEPTED", - C2H_STAT_S_AXIS_WRB_ACCEPTED_MASK}, -}; - - -static struct regfield_info - c2h_stat_desc_rsp_pkt_accepted_field_info[] = { - {"C2H_STAT_DESC_RSP_PKT_ACCEPTED_D", - C2H_STAT_DESC_RSP_PKT_ACCEPTED_D_MASK}, -}; - - -static struct regfield_info - c2h_stat_axis_pkg_cmp_field_info[] = { - {"C2H_STAT_AXIS_PKG_CMP", - C2H_STAT_AXIS_PKG_CMP_MASK}, -}; - - -static struct regfield_info - c2h_stat_desc_rsp_accepted_field_info[] = { - {"C2H_STAT_DESC_RSP_ACCEPTED_D", - C2H_STAT_DESC_RSP_ACCEPTED_D_MASK}, -}; - - -static struct regfield_info - c2h_stat_desc_rsp_cmp_field_info[] = { - {"C2H_STAT_DESC_RSP_CMP_D", - C2H_STAT_DESC_RSP_CMP_D_MASK}, -}; - - -static struct regfield_info - c2h_stat_wrq_out_field_info[] = { - {"C2H_STAT_WRQ_OUT", - C2H_STAT_WRQ_OUT_MASK}, -}; - - -static struct regfield_info - c2h_stat_wpl_ren_accepted_field_info[] = { - {"C2H_STAT_WPL_REN_ACCEPTED", - C2H_STAT_WPL_REN_ACCEPTED_MASK}, -}; - - -static struct regfield_info - c2h_stat_total_wrq_len_field_info[] = { - {"C2H_STAT_TOTAL_WRQ_LEN", - C2H_STAT_TOTAL_WRQ_LEN_MASK}, -}; - - -static struct regfield_info - c2h_stat_total_wpl_len_field_info[] = { - {"C2H_STAT_TOTAL_WPL_LEN", - C2H_STAT_TOTAL_WPL_LEN_MASK}, -}; - - -static struct regfield_info - c2h_buf_sz_0_field_info[] = { - {"C2H_BUF_SZ_0_SIZE", - C2H_BUF_SZ_0_SIZE_MASK}, -}; - - -static struct regfield_info - c2h_buf_sz_1_field_info[] = { - {"C2H_BUF_SZ_1_SIZE", - C2H_BUF_SZ_1_SIZE_MASK}, -}; - - -static struct regfield_info - c2h_buf_sz_2_field_info[] = { - {"C2H_BUF_SZ_2_SIZE", - C2H_BUF_SZ_2_SIZE_MASK}, -}; - - -static struct regfield_info - c2h_buf_sz_3_field_info[] = { - {"C2H_BUF_SZ_3_SIZE", - C2H_BUF_SZ_3_SIZE_MASK}, -}; - - -static struct regfield_info - c2h_buf_sz_4_field_info[] = { - {"C2H_BUF_SZ_4_SIZE", - C2H_BUF_SZ_4_SIZE_MASK}, -}; - - -static struct regfield_info - c2h_buf_sz_5_field_info[] = { - {"C2H_BUF_SZ_5_SIZE", - C2H_BUF_SZ_5_SIZE_MASK}, -}; - - -static struct regfield_info - c2h_buf_sz_7_field_info[] = { - {"C2H_BUF_SZ_7_SIZE", - C2H_BUF_SZ_7_SIZE_MASK}, -}; - - -static struct regfield_info - c2h_buf_sz_8_field_info[] = { - {"C2H_BUF_SZ_8_SIZE", - C2H_BUF_SZ_8_SIZE_MASK}, -}; - - -static struct regfield_info - c2h_buf_sz_9_field_info[] = { - {"C2H_BUF_SZ_9_SIZE", - C2H_BUF_SZ_9_SIZE_MASK}, -}; - - -static struct regfield_info - c2h_buf_sz_10_field_info[] = { - {"C2H_BUF_SZ_10_SIZE", - C2H_BUF_SZ_10_SIZE_MASK}, -}; - - -static struct regfield_info - c2h_buf_sz_11_field_info[] = { - {"C2H_BUF_SZ_11_SIZE", - C2H_BUF_SZ_11_SIZE_MASK}, -}; - - -static struct regfield_info - c2h_buf_sz_12_field_info[] = { - {"C2H_BUF_SZ_12_SIZE", - C2H_BUF_SZ_12_SIZE_MASK}, -}; - - -static struct regfield_info - c2h_buf_sz_13_field_info[] = { - {"C2H_BUF_SZ_13_SIZE", - C2H_BUF_SZ_13_SIZE_MASK}, -}; - - -static struct regfield_info - c2h_buf_sz_14_field_info[] = { - {"C2H_BUF_SZ_14_SIZE", - C2H_BUF_SZ_14_SIZE_MASK}, -}; - - -static struct regfield_info - c2h_buf_sz_15_field_info[] = { - {"C2H_BUF_SZ_15_SIZE", - C2H_BUF_SZ_15_SIZE_MASK}, -}; - - -static struct regfield_info - c2h_err_stat_field_info[] = { - {"C2H_ERR_STAT_RSVD_1", - C2H_ERR_STAT_RSVD_1_MASK}, - {"C2H_ERR_STAT_WRB_PRTY_ERR", - C2H_ERR_STAT_WRB_PRTY_ERR_MASK}, - {"C2H_ERR_STAT_WRB_CIDX_ERR", - C2H_ERR_STAT_WRB_CIDX_ERR_MASK}, - {"C2H_ERR_STAT_WRB_QFULL_ERR", - C2H_ERR_STAT_WRB_QFULL_ERR_MASK}, - {"C2H_ERR_STAT_WRB_INV_Q_ERR", - C2H_ERR_STAT_WRB_INV_Q_ERR_MASK}, - {"C2H_ERR_STAT_PORT_ID_BYP_IN_MISMATCH", - C2H_ERR_STAT_PORT_ID_BYP_IN_MISMATCH_MASK}, - {"C2H_ERR_STAT_PORT_ID_CTXT_MISMATCH", - C2H_ERR_STAT_PORT_ID_CTXT_MISMATCH_MASK}, - {"C2H_ERR_STAT_ERR_DESC_CNT", - C2H_ERR_STAT_ERR_DESC_CNT_MASK}, - {"C2H_ERR_STAT_RSVD_2", - C2H_ERR_STAT_RSVD_2_MASK}, - {"C2H_ERR_STAT_MSI_INT_FAIL", - C2H_ERR_STAT_MSI_INT_FAIL_MASK}, - {"C2H_ERR_STAT_ENG_WPL_DATA_PAR_ERR", - C2H_ERR_STAT_ENG_WPL_DATA_PAR_ERR_MASK}, - {"C2H_ERR_STAT_RSVD_3", - C2H_ERR_STAT_RSVD_3_MASK}, - {"C2H_ERR_STAT_DESC_RSP_ERR", - C2H_ERR_STAT_DESC_RSP_ERR_MASK}, - {"C2H_ERR_STAT_QID_MISMATCH", - C2H_ERR_STAT_QID_MISMATCH_MASK}, - {"C2H_ERR_STAT_RSVD_4", - C2H_ERR_STAT_RSVD_4_MASK}, - {"C2H_ERR_STAT_LEN_MISMATCH", - C2H_ERR_STAT_LEN_MISMATCH_MASK}, - {"C2H_ERR_STAT_MTY_MISMATCH", - C2H_ERR_STAT_MTY_MISMATCH_MASK}, -}; - - -static struct regfield_info - c2h_err_mask_field_info[] = { - {"C2H_ERR_EN", - C2H_ERR_EN_MASK}, -}; - - -static struct regfield_info - c2h_fatal_err_stat_field_info[] = { - {"C2H_FATAL_ERR_STAT_RSVD_1", - C2H_FATAL_ERR_STAT_RSVD_1_MASK}, - {"C2H_FATAL_ERR_STAT_WPL_DATA_PAR_ERR", - C2H_FATAL_ERR_STAT_WPL_DATA_PAR_ERR_MASK}, - {"C2H_FATAL_ERR_STAT_PLD_FIFO_RAM_RDBE", - C2H_FATAL_ERR_STAT_PLD_FIFO_RAM_RDBE_MASK}, - {"C2H_FATAL_ERR_STAT_QID_FIFO_RAM_RDBE", - C2H_FATAL_ERR_STAT_QID_FIFO_RAM_RDBE_MASK}, - {"C2H_FATAL_ERR_STAT_TUSER_FIFO_RAM_RDBE", - C2H_FATAL_ERR_STAT_TUSER_FIFO_RAM_RDBE_MASK}, - {"C2H_FATAL_ERR_STAT_WRB_COAL_DATA_RAM_RDBE", - C2H_FATAL_ERR_STAT_WRB_COAL_DATA_RAM_RDBE_MASK}, - {"C2H_FATAL_ERR_STAT_INT_QID2VEC_RAM_RDBE", - C2H_FATAL_ERR_STAT_INT_QID2VEC_RAM_RDBE_MASK}, - {"C2H_FATAL_ERR_STAT_INT_CTXT_RAM_RDBE", - C2H_FATAL_ERR_STAT_INT_CTXT_RAM_RDBE_MASK}, - {"C2H_FATAL_ERR_STAT_DESC_REQ_FIFO_RAM_RDBE", - C2H_FATAL_ERR_STAT_DESC_REQ_FIFO_RAM_RDBE_MASK}, - {"C2H_FATAL_ERR_STAT_PFCH_CTXT_RAM_RDBE", - C2H_FATAL_ERR_STAT_PFCH_CTXT_RAM_RDBE_MASK}, - {"C2H_FATAL_ERR_STAT_WRB_CTXT_RAM_RDBE", - C2H_FATAL_ERR_STAT_WRB_CTXT_RAM_RDBE_MASK}, - {"C2H_FATAL_ERR_STAT_PFCH_LL_RAM_RDBE", - C2H_FATAL_ERR_STAT_PFCH_LL_RAM_RDBE_MASK}, - {"C2H_FATAL_ERR_STAT_TIMER_FIFO_RAM_RDBE", - C2H_FATAL_ERR_STAT_TIMER_FIFO_RAM_RDBE_MASK}, - {"C2H_FATAL_ERR_STAT_QID_MISMATCH", - C2H_FATAL_ERR_STAT_QID_MISMATCH_MASK}, - {"C2H_FATAL_ERR_STAT_RSVD_2", - C2H_FATAL_ERR_STAT_RSVD_2_MASK}, - {"C2H_FATAL_ERR_STAT_LEN_MISMATCH", - C2H_FATAL_ERR_STAT_LEN_MISMATCH_MASK}, - {"C2H_FATAL_ERR_STAT_MTY_MISMATCH", - C2H_FATAL_ERR_STAT_MTY_MISMATCH_MASK}, -}; - - -static struct regfield_info - c2h_fatal_err_mask_field_info[] = { - {"C2H_FATAL_ERR_C2HEN", - C2H_FATAL_ERR_C2HEN_MASK}, -}; - - -static struct regfield_info - c2h_fatal_err_enable_field_info[] = { - {"C2H_FATAL_ERR_ENABLE_RSVD_1", - C2H_FATAL_ERR_ENABLE_RSVD_1_MASK}, - {"C2H_FATAL_ERR_ENABLE_WPL_PAR_INV", - C2H_FATAL_ERR_ENABLE_WPL_PAR_INV_MASK}, - {"C2H_FATAL_ERR_ENABLE_WRQ_DIS", - C2H_FATAL_ERR_ENABLE_WRQ_DIS_MASK}, -}; - - -static struct regfield_info - glbl_err_int_field_info[] = { - {"GLBL_ERR_INT_RSVD_1", - GLBL_ERR_INT_RSVD_1_MASK}, - {"GLBL_ERR_INT_ARM", - GLBL_ERR_INT_ARM_MASK}, - {"GLBL_ERR_INT_EN_COAL", - GLBL_ERR_INT_EN_COAL_MASK}, - {"GLBL_ERR_INT_VEC", - GLBL_ERR_INT_VEC_MASK}, - {"GLBL_ERR_INT_FUNC", - GLBL_ERR_INT_FUNC_MASK}, -}; - - -static struct regfield_info - c2h_pfch_cfg_field_info[] = { - {"C2H_PFCH_CFG_EVT_QCNT_TH", - C2H_PFCH_CFG_EVT_QCNT_TH_MASK}, - {"C2H_PFCH_CFG_QCNT", - C2H_PFCH_CFG_QCNT_MASK}, - {"C2H_PFCH_CFG_NUM", - C2H_PFCH_CFG_NUM_MASK}, - {"C2H_PFCH_CFG_FL_TH", - C2H_PFCH_CFG_FL_TH_MASK}, -}; - - -static struct regfield_info - c2h_int_timer_tick_field_info[] = { - {"C2H_INT_TIMER_TICK", - C2H_INT_TIMER_TICK_MASK}, -}; - - -static struct regfield_info - c2h_stat_desc_rsp_drop_accepted_field_info[] = { - {"C2H_STAT_DESC_RSP_DROP_ACCEPTED_D", - C2H_STAT_DESC_RSP_DROP_ACCEPTED_D_MASK}, -}; - - -static struct regfield_info - c2h_stat_desc_rsp_err_accepted_field_info[] = { - {"C2H_STAT_DESC_RSP_ERR_ACCEPTED_D", - C2H_STAT_DESC_RSP_ERR_ACCEPTED_D_MASK}, -}; - - -static struct regfield_info - c2h_stat_desc_req_field_info[] = { - {"C2H_STAT_DESC_REQ", - C2H_STAT_DESC_REQ_MASK}, -}; - - -static struct regfield_info - c2h_stat_dbg_dma_eng_0_field_info[] = { - {"C2H_STAT_DMA_ENG_0_RSVD_1", - C2H_STAT_DMA_ENG_0_RSVD_1_MASK}, - {"C2H_STAT_DMA_ENG_0_WRB_FIFO_OUT_CNT", - C2H_STAT_DMA_ENG_0_WRB_FIFO_OUT_CNT_MASK}, - {"C2H_STAT_DMA_ENG_0_QID_FIFO_OUT_CNT", - C2H_STAT_DMA_ENG_0_QID_FIFO_OUT_CNT_MASK}, - {"C2H_STAT_DMA_ENG_0_PLD_FIFO_OUT_CNT", - C2H_STAT_DMA_ENG_0_PLD_FIFO_OUT_CNT_MASK}, - {"C2H_STAT_DMA_ENG_0_WRQ_FIFO_OUT_CNT", - C2H_STAT_DMA_ENG_0_WRQ_FIFO_OUT_CNT_MASK}, - {"C2H_STAT_DMA_ENG_0_WRB_SM_CS", - C2H_STAT_DMA_ENG_0_WRB_SM_CS_MASK}, - {"C2H_STAT_DMA_ENG_0_MAIN_SM_CS", - C2H_STAT_DMA_ENG_0_MAIN_SM_CS_MASK}, -}; - - -static struct regfield_info - c2h_stat_dbg_dma_eng_1_field_info[] = { - {"C2H_STAT_DMA_ENG_1_RSVD_1", - C2H_STAT_DMA_ENG_1_RSVD_1_MASK}, - {"C2H_STAT_DMA_ENG_1_DESC_RSP_LAST", - C2H_STAT_DMA_ENG_1_DESC_RSP_LAST_MASK}, - {"C2H_STAT_DMA_ENG_1_PLD_FIFO_IN_CNT", - C2H_STAT_DMA_ENG_1_PLD_FIFO_IN_CNT_MASK}, - {"C2H_STAT_DMA_ENG_1_PLD_FIFO_OUTPUT_CNT", - C2H_STAT_DMA_ENG_1_PLD_FIFO_OUTPUT_CNT_MASK}, - {"C2H_STAT_DMA_ENG_1_QID_FIFO_IN_CNT", - C2H_STAT_DMA_ENG_1_QID_FIFO_IN_CNT_MASK}, -}; - - -static struct regfield_info - c2h_stat_dbg_dma_eng_2_field_info[] = { - {"C2H_STAT_DMA_ENG_2_RSVD_1", - C2H_STAT_DMA_ENG_2_RSVD_1_MASK}, - {"C2H_STAT_DMA_ENG_2_WRB_FIFO_IN_CNT", - C2H_STAT_DMA_ENG_2_WRB_FIFO_IN_CNT_MASK}, - {"C2H_STAT_DMA_ENG_2_WRB_FIFO_OUTPUT_CNT", - C2H_STAT_DMA_ENG_2_WRB_FIFO_OUTPUT_CNT_MASK}, - {"C2H_STAT_DMA_ENG_2_QID_FIFO_OUTPUT_CNT", - C2H_STAT_DMA_ENG_2_QID_FIFO_OUTPUT_CNT_MASK}, -}; - - -static struct regfield_info - c2h_stat_dbg_dma_eng_3_field_info[] = { - {"C2H_STAT_DMA_ENG_3_RSVD_1", - C2H_STAT_DMA_ENG_3_RSVD_1_MASK}, - {"C2H_STAT_DMA_ENG_3_ADDR_4K_SPLIT_CNT", - C2H_STAT_DMA_ENG_3_ADDR_4K_SPLIT_CNT_MASK}, - {"C2H_STAT_DMA_ENG_3_WRQ_FIFO_IN_CNT", - C2H_STAT_DMA_ENG_3_WRQ_FIFO_IN_CNT_MASK}, - {"C2H_STAT_DMA_ENG_3_WRQ_FIFO_OUTPUT_CNT", - C2H_STAT_DMA_ENG_3_WRQ_FIFO_OUTPUT_CNT_MASK}, -}; - - -static struct regfield_info - c2h_dbg_pfch_err_ctxt_field_info[] = { - {"C2H_PFCH_ERR_CTXT_RSVD_1", - C2H_PFCH_ERR_CTXT_RSVD_1_MASK}, - {"C2H_PFCH_ERR_CTXT_ERR_STAT", - C2H_PFCH_ERR_CTXT_ERR_STAT_MASK}, - {"C2H_PFCH_ERR_CTXT_CMD_WR", - C2H_PFCH_ERR_CTXT_CMD_WR_MASK}, - {"C2H_PFCH_ERR_CTXT_QID", - C2H_PFCH_ERR_CTXT_QID_MASK}, - {"C2H_PFCH_ERR_CTXT_DONE", - C2H_PFCH_ERR_CTXT_DONE_MASK}, -}; - - -static struct regfield_info - c2h_first_err_qid_field_info[] = { - {"C2H_FIRST_ERR_QID_RSVD_1", - C2H_FIRST_ERR_QID_RSVD_1_MASK}, - {"C2H_FIRST_ERR_QID_ERR_STAT", - C2H_FIRST_ERR_QID_ERR_STAT_MASK}, - {"C2H_FIRST_ERR_QID_CMD_WR", - C2H_FIRST_ERR_QID_CMD_WR_MASK}, - {"C2H_FIRST_ERR_QID_QID", - C2H_FIRST_ERR_QID_QID_MASK}, -}; - - -static struct regfield_info - stat_num_wrb_in_field_info[] = { - {"STAT_NUM_WRB_IN_RSVD_1", - STAT_NUM_WRB_IN_RSVD_1_MASK}, - {"STAT_NUM_WRB_IN_WRB_CNT", - STAT_NUM_WRB_IN_WRB_CNT_MASK}, -}; - - -static struct regfield_info - stat_num_wrb_out_field_info[] = { - {"STAT_NUM_WRB_OUT_RSVD_1", - STAT_NUM_WRB_OUT_RSVD_1_MASK}, - {"STAT_NUM_WRB_OUT_WRB_CNT", - STAT_NUM_WRB_OUT_WRB_CNT_MASK}, -}; - - -static struct regfield_info - stat_num_wrb_drp_field_info[] = { - {"STAT_NUM_WRB_DRP_RSVD_1", - STAT_NUM_WRB_DRP_RSVD_1_MASK}, - {"STAT_NUM_WRB_DRP_WRB_CNT", - STAT_NUM_WRB_DRP_WRB_CNT_MASK}, -}; - - -static struct regfield_info - stat_num_stat_desc_out_field_info[] = { - {"STAT_NUM_STAT_DESC_OUT_RSVD_1", - STAT_NUM_STAT_DESC_OUT_RSVD_1_MASK}, - {"STAT_NUM_STAT_DESC_OUT_CNT", - STAT_NUM_STAT_DESC_OUT_CNT_MASK}, -}; - - -static struct regfield_info - stat_num_dsc_crdt_sent_field_info[] = { - {"STAT_NUM_DSC_CRDT_SENT_RSVD_1", - STAT_NUM_DSC_CRDT_SENT_RSVD_1_MASK}, - {"STAT_NUM_DSC_CRDT_SENT_CNT", - STAT_NUM_DSC_CRDT_SENT_CNT_MASK}, -}; - - -static struct regfield_info - stat_num_fch_dsc_rcvd_field_info[] = { - {"STAT_NUM_FCH_DSC_RCVD_RSVD_1", - STAT_NUM_FCH_DSC_RCVD_RSVD_1_MASK}, - {"STAT_NUM_FCH_DSC_RCVD_DSC_CNT", - STAT_NUM_FCH_DSC_RCVD_DSC_CNT_MASK}, -}; - - -static struct regfield_info - stat_num_byp_dsc_rcvd_field_info[] = { - {"STAT_NUM_BYP_DSC_RCVD_RSVD_1", - STAT_NUM_BYP_DSC_RCVD_RSVD_1_MASK}, - {"STAT_NUM_BYP_DSC_RCVD_DSC_CNT", - STAT_NUM_BYP_DSC_RCVD_DSC_CNT_MASK}, -}; - - -static struct regfield_info - c2h_wrb_coal_cfg_field_info[] = { - {"C2H_WRB_COAL_CFG_MAX_BUF_SZ", - C2H_WRB_COAL_CFG_MAX_BUF_SZ_MASK}, - {"C2H_WRB_COAL_CFG_TICK_VAL", - C2H_WRB_COAL_CFG_TICK_VAL_MASK}, - {"C2H_WRB_COAL_CFG_TICK_CNT", - C2H_WRB_COAL_CFG_TICK_CNT_MASK}, - {"C2H_WRB_COAL_CFG_SET_GLB_FLUSH", - C2H_WRB_COAL_CFG_SET_GLB_FLUSH_MASK}, - {"C2H_WRB_COAL_CFG_DONE_GLB_FLUSH", - C2H_WRB_COAL_CFG_DONE_GLB_FLUSH_MASK}, -}; - - -static struct regfield_info - c2h_intr_h2c_req_field_info[] = { - {"C2H_INTR_H2C_REQ_RSVD_1", - C2H_INTR_H2C_REQ_RSVD_1_MASK}, - {"C2H_INTR_H2C_REQ_CNT", - C2H_INTR_H2C_REQ_CNT_MASK}, -}; - - -static struct regfield_info - c2h_intr_c2h_mm_req_field_info[] = { - {"C2H_INTR_C2H_MM_REQ_RSVD_1", - C2H_INTR_C2H_MM_REQ_RSVD_1_MASK}, - {"C2H_INTR_C2H_MM_REQ_CNT", - C2H_INTR_C2H_MM_REQ_CNT_MASK}, -}; - - -static struct regfield_info - c2h_intr_err_int_req_field_info[] = { - {"C2H_INTR_ERR_INT_REQ_RSVD_1", - C2H_INTR_ERR_INT_REQ_RSVD_1_MASK}, - {"C2H_INTR_ERR_INT_REQ_CNT", - C2H_INTR_ERR_INT_REQ_CNT_MASK}, -}; - - -static struct regfield_info - c2h_intr_c2h_st_req_field_info[] = { - {"C2H_INTR_C2H_ST_REQ_RSVD_1", - C2H_INTR_C2H_ST_REQ_RSVD_1_MASK}, - {"C2H_INTR_C2H_ST_REQ_CNT", - C2H_INTR_C2H_ST_REQ_CNT_MASK}, -}; - - -static struct regfield_info - c2h_intr_h2c_err_c2h_mm_msix_ack_field_info[] = { - {"C2H_INTR_H2C_ERR_C2H_MM_MSIX_ACK_RSVD_1", - C2H_INTR_H2C_ERR_C2H_MM_MSIX_ACK_RSVD_1_MASK}, - {"C2H_INTR_H2C_ERR_C2H_MM_MSIX_ACK_CNT", - C2H_INTR_H2C_ERR_C2H_MM_MSIX_ACK_CNT_MASK}, -}; - - -static struct regfield_info - c2h_intr_h2c_err_c2h_mm_msix_fail_field_info[] = { - {"C2H_INTR_H2C_ERR_C2H_MM_MSIX_FAIL_RSVD_1", - C2H_INTR_H2C_ERR_C2H_MM_MSIX_FAIL_RSVD_1_MASK}, - {"C2H_INTR_H2C_ERR_C2H_MM_MSIX_FAIL_CNT", - C2H_INTR_H2C_ERR_C2H_MM_MSIX_FAIL_CNT_MASK}, -}; - - -static struct regfield_info - c2h_intr_h2c_err_c2h_mm_msix_no_msix_field_info[] = { - {"C2H_INTR_H2C_ERR_C2H_MM_MSIX_NO_MSIX_RSVD_1", - C2H_INTR_H2C_ERR_C2H_MM_MSIX_NO_MSIX_RSVD_1_MASK}, - {"C2H_INTR_H2C_ERR_C2H_MM_MSIX_NO_MSIX_CNT", - C2H_INTR_H2C_ERR_C2H_MM_MSIX_NO_MSIX_CNT_MASK}, -}; - - -static struct regfield_info - c2h_intr_h2c_err_c2h_mm_ctxt_inval_field_info[] = { - {"C2H_INTR_H2C_ERR_C2H_MM_CTXT_INVAL_RSVD_1", - C2H_INTR_H2C_ERR_C2H_MM_CTXT_INVAL_RSVD_1_MASK}, - {"C2H_INTR_H2C_ERR_C2H_MM_CTXT_INVAL_CNT", - C2H_INTR_H2C_ERR_C2H_MM_CTXT_INVAL_CNT_MASK}, -}; - - -static struct regfield_info - c2h_intr_c2h_st_msix_ack_field_info[] = { - {"C2H_INTR_C2H_ST_MSIX_ACK_RSVD_1", - C2H_INTR_C2H_ST_MSIX_ACK_RSVD_1_MASK}, - {"C2H_INTR_C2H_ST_MSIX_ACK_CNT", - C2H_INTR_C2H_ST_MSIX_ACK_CNT_MASK}, -}; - - -static struct regfield_info - c2h_intr_c2h_st_msix_fail_field_info[] = { - {"C2H_INTR_C2H_ST_MSIX_FAIL_RSVD_1", - C2H_INTR_C2H_ST_MSIX_FAIL_RSVD_1_MASK}, - {"C2H_INTR_C2H_ST_MSIX_FAIL_CNT", - C2H_INTR_C2H_ST_MSIX_FAIL_CNT_MASK}, -}; - - -static struct regfield_info - c2h_intr_c2h_st_no_msix_field_info[] = { - {"C2H_INTR_C2H_ST_NO_MSIX_RSVD_1", - C2H_INTR_C2H_ST_NO_MSIX_RSVD_1_MASK}, - {"C2H_INTR_C2H_ST_NO_MSIX_CNT", - C2H_INTR_C2H_ST_NO_MSIX_CNT_MASK}, -}; - - -static struct regfield_info - c2h_intr_c2h_st_ctxt_inval_field_info[] = { - {"C2H_INTR_C2H_ST_CTXT_INVAL_RSVD_1", - C2H_INTR_C2H_ST_CTXT_INVAL_RSVD_1_MASK}, - {"C2H_INTR_C2H_ST_CTXT_INVAL_CNT", - C2H_INTR_C2H_ST_CTXT_INVAL_CNT_MASK}, -}; - - -static struct regfield_info - c2h_stat_wr_cmp_field_info[] = { - {"C2H_STAT_WR_CMP_RSVD_1", - C2H_STAT_WR_CMP_RSVD_1_MASK}, - {"C2H_STAT_WR_CMP_CNT", - C2H_STAT_WR_CMP_CNT_MASK}, -}; - - -static struct regfield_info - c2h_stat_dbg_dma_eng_4_field_info[] = { - {"C2H_STAT_DMA_ENG_4_TUSER_FIFO_OUT_VLD", - C2H_STAT_DMA_ENG_4_TUSER_FIFO_OUT_VLD_MASK}, - {"C2H_STAT_DMA_ENG_4_WRB_FIFO_IN_RDY", - C2H_STAT_DMA_ENG_4_WRB_FIFO_IN_RDY_MASK}, - {"C2H_STAT_DMA_ENG_4_TUSER_FIFO_IN_CNT", - C2H_STAT_DMA_ENG_4_TUSER_FIFO_IN_CNT_MASK}, - {"C2H_STAT_DMA_ENG_4_TUSER_FIFO_OUTPUT_CNT", - C2H_STAT_DMA_ENG_4_TUSER_FIFO_OUTPUT_CNT_MASK}, - {"C2H_STAT_DMA_ENG_4_TUSER_FIFO_OUT_CNT", - C2H_STAT_DMA_ENG_4_TUSER_FIFO_OUT_CNT_MASK}, -}; - - -static struct regfield_info - c2h_stat_dbg_dma_eng_5_field_info[] = { - {"C2H_STAT_DMA_ENG_5_RSVD_1", - C2H_STAT_DMA_ENG_5_RSVD_1_MASK}, - {"C2H_STAT_DMA_ENG_5_TUSER_COMB_OUT_VLD", - C2H_STAT_DMA_ENG_5_TUSER_COMB_OUT_VLD_MASK}, - {"C2H_STAT_DMA_ENG_5_TUSER_FIFO_IN_RDY", - C2H_STAT_DMA_ENG_5_TUSER_FIFO_IN_RDY_MASK}, - {"C2H_STAT_DMA_ENG_5_TUSER_COMB_IN_CNT", - C2H_STAT_DMA_ENG_5_TUSER_COMB_IN_CNT_MASK}, - {"C2H_STAT_DMA_ENG_5_TUSE_COMB_OUTPUT_CNT", - C2H_STAT_DMA_ENG_5_TUSE_COMB_OUTPUT_CNT_MASK}, - {"C2H_STAT_DMA_ENG_5_TUSER_COMB_CNT", - C2H_STAT_DMA_ENG_5_TUSER_COMB_CNT_MASK}, -}; - - -static struct regfield_info - c2h_dbg_pfch_qid_field_info[] = { - {"C2H_PFCH_QID_RSVD_1", - C2H_PFCH_QID_RSVD_1_MASK}, - {"C2H_PFCH_QID_ERR_CTXT", - C2H_PFCH_QID_ERR_CTXT_MASK}, - {"C2H_PFCH_QID_TARGET", - C2H_PFCH_QID_TARGET_MASK}, - {"C2H_PFCH_QID_QID_OR_TAG", - C2H_PFCH_QID_QID_OR_TAG_MASK}, -}; - - -static struct regfield_info - c2h_dbg_pfch_field_info[] = { - {"C2H_PFCH_DATA", - C2H_PFCH_DATA_MASK}, -}; - - -static struct regfield_info - c2h_int_dbg_field_info[] = { - {"C2H_INT_RSVD_1", - C2H_INT_RSVD_1_MASK}, - {"C2H_INT_INT_COAL_SM", - C2H_INT_INT_COAL_SM_MASK}, - {"C2H_INT_INT_SM", - C2H_INT_INT_SM_MASK}, -}; - - -static struct regfield_info - c2h_stat_imm_accepted_field_info[] = { - {"C2H_STAT_IMM_ACCEPTED_RSVD_1", - C2H_STAT_IMM_ACCEPTED_RSVD_1_MASK}, - {"C2H_STAT_IMM_ACCEPTED_CNT", - C2H_STAT_IMM_ACCEPTED_CNT_MASK}, -}; - - -static struct regfield_info - c2h_stat_marker_accepted_field_info[] = { - {"C2H_STAT_MARKER_ACCEPTED_RSVD_1", - C2H_STAT_MARKER_ACCEPTED_RSVD_1_MASK}, - {"C2H_STAT_MARKER_ACCEPTED_CNT", - C2H_STAT_MARKER_ACCEPTED_CNT_MASK}, -}; - - -static struct regfield_info - c2h_stat_disable_cmp_accepted_field_info[] = { - {"C2H_STAT_DISABLE_CMP_ACCEPTED_RSVD_1", - C2H_STAT_DISABLE_CMP_ACCEPTED_RSVD_1_MASK}, - {"C2H_STAT_DISABLE_CMP_ACCEPTED_CNT", - C2H_STAT_DISABLE_CMP_ACCEPTED_CNT_MASK}, -}; - - -static struct regfield_info - c2h_pld_fifo_crdt_cnt_field_info[] = { - {"C2H_PLD_FIFO_CRDT_CNT_RSVD_1", - C2H_PLD_FIFO_CRDT_CNT_RSVD_1_MASK}, - {"C2H_PLD_FIFO_CRDT_CNT_CNT", - C2H_PLD_FIFO_CRDT_CNT_CNT_MASK}, -}; - - -static struct regfield_info - h2c_err_stat_field_info[] = { - {"H2C_ERR_STAT_RSVD_1", - H2C_ERR_STAT_RSVD_1_MASK}, - {"H2C_ERR_STAT_SBE", - H2C_ERR_STAT_SBE_MASK}, - {"H2C_ERR_STAT_DBE", - H2C_ERR_STAT_DBE_MASK}, - {"H2C_ERR_STAT_NO_DMA_DS", - H2C_ERR_STAT_NO_DMA_DS_MASK}, - {"H2C_ERR_STAT_SDI_MRKR_REQ_MOP_ERR", - H2C_ERR_STAT_SDI_MRKR_REQ_MOP_ERR_MASK}, - {"H2C_ERR_STAT_ZERO_LEN_DS", - H2C_ERR_STAT_ZERO_LEN_DS_MASK}, -}; - - -static struct regfield_info - h2c_err_mask_field_info[] = { - {"H2C_ERR_EN", - H2C_ERR_EN_MASK}, -}; - - -static struct regfield_info - h2c_first_err_qid_field_info[] = { - {"H2C_FIRST_ERR_QID_RSVD_1", - H2C_FIRST_ERR_QID_RSVD_1_MASK}, - {"H2C_FIRST_ERR_QID_ERR_TYPE", - H2C_FIRST_ERR_QID_ERR_TYPE_MASK}, - {"H2C_FIRST_ERR_QID_RSVD_2", - H2C_FIRST_ERR_QID_RSVD_2_MASK}, - {"H2C_FIRST_ERR_QID_QID", - H2C_FIRST_ERR_QID_QID_MASK}, -}; - - -static struct regfield_info - h2c_dbg_reg0_field_info[] = { - {"H2C_REG0_NUM_DSC_RCVD", - H2C_REG0_NUM_DSC_RCVD_MASK}, - {"H2C_REG0_NUM_WRB_SENT", - H2C_REG0_NUM_WRB_SENT_MASK}, -}; - - -static struct regfield_info - h2c_dbg_reg1_field_info[] = { - {"H2C_REG1_NUM_REQ_SENT", - H2C_REG1_NUM_REQ_SENT_MASK}, - {"H2C_REG1_NUM_CMP_SENT", - H2C_REG1_NUM_CMP_SENT_MASK}, -}; - - -static struct regfield_info - h2c_dbg_reg2_field_info[] = { - {"H2C_REG2_RSVD_1", - H2C_REG2_RSVD_1_MASK}, - {"H2C_REG2_NUM_ERR_DSC_RCVD", - H2C_REG2_NUM_ERR_DSC_RCVD_MASK}, -}; - - -static struct regfield_info - h2c_dbg_reg3_field_info[] = { - {"H2C_REG3", - H2C_REG3_MASK}, - {"H2C_REG3_DSCO_FIFO_EMPTY", - H2C_REG3_DSCO_FIFO_EMPTY_MASK}, - {"H2C_REG3_DSCO_FIFO_FULL", - H2C_REG3_DSCO_FIFO_FULL_MASK}, - {"H2C_REG3_CUR_RC_STATE", - H2C_REG3_CUR_RC_STATE_MASK}, - {"H2C_REG3_RDREQ_LINES", - H2C_REG3_RDREQ_LINES_MASK}, - {"H2C_REG3_RDATA_LINES_AVAIL", - H2C_REG3_RDATA_LINES_AVAIL_MASK}, - {"H2C_REG3_PEND_FIFO_EMPTY", - H2C_REG3_PEND_FIFO_EMPTY_MASK}, - {"H2C_REG3_PEND_FIFO_FULL", - H2C_REG3_PEND_FIFO_FULL_MASK}, - {"H2C_REG3_CUR_RQ_STATE", - H2C_REG3_CUR_RQ_STATE_MASK}, - {"H2C_REG3_DSCI_FIFO_FULL", - H2C_REG3_DSCI_FIFO_FULL_MASK}, - {"H2C_REG3_DSCI_FIFO_EMPTY", - H2C_REG3_DSCI_FIFO_EMPTY_MASK}, -}; - - -static struct regfield_info - h2c_dbg_reg4_field_info[] = { - {"H2C_REG4_RDREQ_ADDR", - H2C_REG4_RDREQ_ADDR_MASK}, -}; - - -static struct regfield_info - h2c_fatal_err_en_field_info[] = { - {"H2C_FATAL_ERR_EN_RSVD_1", - H2C_FATAL_ERR_EN_RSVD_1_MASK}, - {"H2C_FATAL_ERR_EN_H2C", - H2C_FATAL_ERR_EN_H2C_MASK}, -}; - - -static struct regfield_info - c2h_channel_ctl_field_info[] = { - {"C2H_CHANNEL_CTL_RSVD_1", - C2H_CHANNEL_CTL_RSVD_1_MASK}, - {"C2H_CHANNEL_CTL_RUN", - C2H_CHANNEL_CTL_RUN_MASK}, -}; - - -static struct regfield_info - c2h_channel_ctl_1_field_info[] = { - {"C2H_CHANNEL_CTL_1_RUN", - C2H_CHANNEL_CTL_1_RUN_MASK}, - {"C2H_CHANNEL_CTL_1_RUN_1", - C2H_CHANNEL_CTL_1_RUN_1_MASK}, -}; - - -static struct regfield_info - c2h_mm_status_field_info[] = { - {"C2H_MM_STATUS_RSVD_1", - C2H_MM_STATUS_RSVD_1_MASK}, - {"C2H_MM_STATUS_RUN", - C2H_MM_STATUS_RUN_MASK}, -}; - - -static struct regfield_info - c2h_channel_cmpl_desc_cnt_field_info[] = { - {"C2H_CHANNEL_CMPL_DESC_CNT_C2H_CO", - C2H_CHANNEL_CMPL_DESC_CNT_C2H_CO_MASK}, -}; - - -static struct regfield_info - c2h_mm_err_code_enable_mask_field_info[] = { - {"C2H_MM_ERR_CODE_ENABLE_RSVD_1", - C2H_MM_ERR_CODE_ENABLE_RSVD_1_MASK}, - {"C2H_MM_ERR_CODE_ENABLE_WR_UC_RAM", - C2H_MM_ERR_CODE_ENABLE_WR_UC_RAM_MASK}, - {"C2H_MM_ERR_CODE_ENABLE_WR_UR", - C2H_MM_ERR_CODE_ENABLE_WR_UR_MASK}, - {"C2H_MM_ERR_CODE_ENABLE_WR_FLR", - C2H_MM_ERR_CODE_ENABLE_WR_FLR_MASK}, - {"C2H_MM_ERR_CODE_ENABLE_RSVD_2", - C2H_MM_ERR_CODE_ENABLE_RSVD_2_MASK}, - {"C2H_MM_ERR_CODE_ENABLE_RD_SLV_ERR", - C2H_MM_ERR_CODE_ENABLE_RD_SLV_ERR_MASK}, - {"C2H_MM_ERR_CODE_ENABLE_WR_SLV_ERR", - C2H_MM_ERR_CODE_ENABLE_WR_SLV_ERR_MASK}, -}; - - -static struct regfield_info - c2h_mm_err_code_field_info[] = { - {"C2H_MM_ERR_CODE_RSVD_1", - C2H_MM_ERR_CODE_RSVD_1_MASK}, - {"C2H_MM_ERR_CODE_VALID", - C2H_MM_ERR_CODE_VALID_MASK}, - {"C2H_MM_ERR_CODE_RDWR", - C2H_MM_ERR_CODE_RDWR_MASK}, - {"C2H_MM_ERR_CODE", - C2H_MM_ERR_CODE_MASK}, -}; - - -static struct regfield_info - c2h_mm_err_info_field_info[] = { - {"C2H_MM_ERR_INFO_RSVD_1", - C2H_MM_ERR_INFO_RSVD_1_MASK}, - {"C2H_MM_ERR_INFO_QID", - C2H_MM_ERR_INFO_QID_MASK}, - {"C2H_MM_ERR_INFO_DIR", - C2H_MM_ERR_INFO_DIR_MASK}, - {"C2H_MM_ERR_INFO_CIDX", - C2H_MM_ERR_INFO_CIDX_MASK}, -}; - - -static struct regfield_info - c2h_mm_perf_mon_ctl_field_info[] = { - {"C2H_MM_PERF_MON_CTL_RSVD_1", - C2H_MM_PERF_MON_CTL_RSVD_1_MASK}, - {"C2H_MM_PERF_MON_CTL_IMM_START", - C2H_MM_PERF_MON_CTL_IMM_START_MASK}, - {"C2H_MM_PERF_MON_CTL_RUN_START", - C2H_MM_PERF_MON_CTL_RUN_START_MASK}, - {"C2H_MM_PERF_MON_CTL_IMM_CLEAR", - C2H_MM_PERF_MON_CTL_IMM_CLEAR_MASK}, - {"C2H_MM_PERF_MON_CTL_RUN_CLEAR", - C2H_MM_PERF_MON_CTL_RUN_CLEAR_MASK}, -}; - - -static struct regfield_info - c2h_mm_perf_mon_cycle_cnt0_field_info[] = { - {"C2H_MM_PERF_MON_CYCLE_CNT0_CYC_CNT", - C2H_MM_PERF_MON_CYCLE_CNT0_CYC_CNT_MASK}, -}; - - -static struct regfield_info - c2h_mm_perf_mon_cycle_cnt1_field_info[] = { - {"C2H_MM_PERF_MON_CYCLE_CNT1_RSVD_1", - C2H_MM_PERF_MON_CYCLE_CNT1_RSVD_1_MASK}, - {"C2H_MM_PERF_MON_CYCLE_CNT1_CYC_CNT", - C2H_MM_PERF_MON_CYCLE_CNT1_CYC_CNT_MASK}, -}; - - -static struct regfield_info - c2h_mm_perf_mon_data_cnt0_field_info[] = { - {"C2H_MM_PERF_MON_DATA_CNT0_DCNT", - C2H_MM_PERF_MON_DATA_CNT0_DCNT_MASK}, -}; - - -static struct regfield_info - c2h_mm_perf_mon_data_cnt1_field_info[] = { - {"C2H_MM_PERF_MON_DATA_CNT1_RSVD_1", - C2H_MM_PERF_MON_DATA_CNT1_RSVD_1_MASK}, - {"C2H_MM_PERF_MON_DATA_CNT1_DCNT", - C2H_MM_PERF_MON_DATA_CNT1_DCNT_MASK}, -}; - - -static struct regfield_info - c2h_mm_dbg_field_info[] = { - {"C2H_MM_RSVD_1", - C2H_MM_RSVD_1_MASK}, - {"C2H_MM_RRQ_ENTRIES", - C2H_MM_RRQ_ENTRIES_MASK}, - {"C2H_MM_DAT_FIFO_SPC", - C2H_MM_DAT_FIFO_SPC_MASK}, - {"C2H_MM_RD_STALL", - C2H_MM_RD_STALL_MASK}, - {"C2H_MM_RRQ_FIFO_FI", - C2H_MM_RRQ_FIFO_FI_MASK}, - {"C2H_MM_WR_STALL", - C2H_MM_WR_STALL_MASK}, - {"C2H_MM_WRQ_FIFO_FI", - C2H_MM_WRQ_FIFO_FI_MASK}, - {"C2H_MM_WBK_STALL", - C2H_MM_WBK_STALL_MASK}, - {"C2H_MM_DSC_FIFO_EP", - C2H_MM_DSC_FIFO_EP_MASK}, - {"C2H_MM_DSC_FIFO_FL", - C2H_MM_DSC_FIFO_FL_MASK}, -}; - - -static struct regfield_info - h2c_channel_ctl_field_info[] = { - {"H2C_CHANNEL_CTL_RSVD_1", - H2C_CHANNEL_CTL_RSVD_1_MASK}, - {"H2C_CHANNEL_CTL_RUN", - H2C_CHANNEL_CTL_RUN_MASK}, -}; - - -static struct regfield_info - h2c_channel_ctl_1_field_info[] = { - {"H2C_CHANNEL_CTL_1_RUN", - H2C_CHANNEL_CTL_1_RUN_MASK}, -}; - - -static struct regfield_info - h2c_channel_ctl_2_field_info[] = { - {"H2C_CHANNEL_CTL_2_RUN", - H2C_CHANNEL_CTL_2_RUN_MASK}, -}; - - -static struct regfield_info - h2c_mm_status_field_info[] = { - {"H2C_MM_STATUS_RSVD_1", - H2C_MM_STATUS_RSVD_1_MASK}, - {"H2C_MM_STATUS_RUN", - H2C_MM_STATUS_RUN_MASK}, -}; - - -static struct regfield_info - h2c_channel_cmpl_desc_cnt_field_info[] = { - {"H2C_CHANNEL_CMPL_DESC_CNT_H2C_CO", - H2C_CHANNEL_CMPL_DESC_CNT_H2C_CO_MASK}, -}; - - -static struct regfield_info - h2c_mm_err_code_enable_mask_field_info[] = { - {"H2C_MM_ERR_CODE_ENABLE_RSVD_1", - H2C_MM_ERR_CODE_ENABLE_RSVD_1_MASK}, - {"H2C_MM_ERR_CODE_ENABLE_WR_SLV_ERR", - H2C_MM_ERR_CODE_ENABLE_WR_SLV_ERR_MASK}, - {"H2C_MM_ERR_CODE_ENABLE_WR_DEC_ERR", - H2C_MM_ERR_CODE_ENABLE_WR_DEC_ERR_MASK}, - {"H2C_MM_ERR_CODE_ENABLE_RSVD_2", - H2C_MM_ERR_CODE_ENABLE_RSVD_2_MASK}, - {"H2C_MM_ERR_CODE_ENABLE_RD_RQ_DIS_ERR", - H2C_MM_ERR_CODE_ENABLE_RD_RQ_DIS_ERR_MASK}, - {"H2C_MM_ERR_CODE_ENABLE_RSVD_3", - H2C_MM_ERR_CODE_ENABLE_RSVD_3_MASK}, - {"H2C_MM_ERR_CODE_ENABLE_RD_DAT_POISON_ERR", - H2C_MM_ERR_CODE_ENABLE_RD_DAT_POISON_ERR_MASK}, - {"H2C_MM_ERR_CODE_ENABLE_RSVD_4", - H2C_MM_ERR_CODE_ENABLE_RSVD_4_MASK}, - {"H2C_MM_ERR_CODE_ENABLE_RD_FLR_ERR", - H2C_MM_ERR_CODE_ENABLE_RD_FLR_ERR_MASK}, - {"H2C_MM_ERR_CODE_ENABLE_RSVD_5", - H2C_MM_ERR_CODE_ENABLE_RSVD_5_MASK}, - {"H2C_MM_ERR_CODE_ENABLE_RD_HDR_ADR_ERR", - H2C_MM_ERR_CODE_ENABLE_RD_HDR_ADR_ERR_MASK}, - {"H2C_MM_ERR_CODE_ENABLE_RD_HDR_PARA", - H2C_MM_ERR_CODE_ENABLE_RD_HDR_PARA_MASK}, - {"H2C_MM_ERR_CODE_ENABLE_RD_HDR_BYTE_ERR", - H2C_MM_ERR_CODE_ENABLE_RD_HDR_BYTE_ERR_MASK}, - {"H2C_MM_ERR_CODE_ENABLE_RD_UR_CA", - H2C_MM_ERR_CODE_ENABLE_RD_UR_CA_MASK}, - {"H2C_MM_ERR_CODE_ENABLE_RD_HRD_POISON_ERR", - H2C_MM_ERR_CODE_ENABLE_RD_HRD_POISON_ERR_MASK}, - {"H2C_MM_ERR_CODE_ENABLE_RSVD_6", - H2C_MM_ERR_CODE_ENABLE_RSVD_6_MASK}, -}; - - -static struct regfield_info - h2c_mm_err_code_field_info[] = { - {"H2C_MM_ERR_CODE_RSVD_1", - H2C_MM_ERR_CODE_RSVD_1_MASK}, - {"H2C_MM_ERR_CODE_VALID", - H2C_MM_ERR_CODE_VALID_MASK}, - {"H2C_MM_ERR_CODE_RDWR", - H2C_MM_ERR_CODE_RDWR_MASK}, - {"H2C_MM_ERR_CODE", - H2C_MM_ERR_CODE_MASK}, -}; - - -static struct regfield_info - h2c_mm_err_info_field_info[] = { - {"H2C_MM_ERR_INFO_RSVD_1", - H2C_MM_ERR_INFO_RSVD_1_MASK}, - {"H2C_MM_ERR_INFO_QID", - H2C_MM_ERR_INFO_QID_MASK}, - {"H2C_MM_ERR_INFO_DIR", - H2C_MM_ERR_INFO_DIR_MASK}, - {"H2C_MM_ERR_INFO_CIDX", - H2C_MM_ERR_INFO_CIDX_MASK}, -}; - - -static struct regfield_info - h2c_mm_perf_mon_ctl_field_info[] = { - {"H2C_MM_PERF_MON_CTL_RSVD_1", - H2C_MM_PERF_MON_CTL_RSVD_1_MASK}, - {"H2C_MM_PERF_MON_CTL_IMM_START", - H2C_MM_PERF_MON_CTL_IMM_START_MASK}, - {"H2C_MM_PERF_MON_CTL_RUN_START", - H2C_MM_PERF_MON_CTL_RUN_START_MASK}, - {"H2C_MM_PERF_MON_CTL_IMM_CLEAR", - H2C_MM_PERF_MON_CTL_IMM_CLEAR_MASK}, - {"H2C_MM_PERF_MON_CTL_RUN_CLEAR", - H2C_MM_PERF_MON_CTL_RUN_CLEAR_MASK}, -}; - - -static struct regfield_info - h2c_mm_perf_mon_cycle_cnt0_field_info[] = { - {"H2C_MM_PERF_MON_CYCLE_CNT0_CYC_CNT", - H2C_MM_PERF_MON_CYCLE_CNT0_CYC_CNT_MASK}, -}; - - -static struct regfield_info - h2c_mm_perf_mon_cycle_cnt1_field_info[] = { - {"H2C_MM_PERF_MON_CYCLE_CNT1_RSVD_1", - H2C_MM_PERF_MON_CYCLE_CNT1_RSVD_1_MASK}, - {"H2C_MM_PERF_MON_CYCLE_CNT1_CYC_CNT", - H2C_MM_PERF_MON_CYCLE_CNT1_CYC_CNT_MASK}, -}; - - -static struct regfield_info - h2c_mm_perf_mon_data_cnt0_field_info[] = { - {"H2C_MM_PERF_MON_DATA_CNT0_DCNT", - H2C_MM_PERF_MON_DATA_CNT0_DCNT_MASK}, -}; - - -static struct regfield_info - h2c_mm_perf_mon_data_cnt1_field_info[] = { - {"H2C_MM_PERF_MON_DATA_CNT1_RSVD_1", - H2C_MM_PERF_MON_DATA_CNT1_RSVD_1_MASK}, - {"H2C_MM_PERF_MON_DATA_CNT1_DCNT", - H2C_MM_PERF_MON_DATA_CNT1_DCNT_MASK}, -}; - - -static struct regfield_info - h2c_mm_dbg_field_info[] = { - {"H2C_MM_RSVD_1", - H2C_MM_RSVD_1_MASK}, - {"H2C_MM_RRQ_ENTRIES", - H2C_MM_RRQ_ENTRIES_MASK}, - {"H2C_MM_DAT_FIFO_SPC", - H2C_MM_DAT_FIFO_SPC_MASK}, - {"H2C_MM_RD_STALL", - H2C_MM_RD_STALL_MASK}, - {"H2C_MM_RRQ_FIFO_FI", - H2C_MM_RRQ_FIFO_FI_MASK}, - {"H2C_MM_WR_STALL", - H2C_MM_WR_STALL_MASK}, - {"H2C_MM_WRQ_FIFO_FI", - H2C_MM_WRQ_FIFO_FI_MASK}, - {"H2C_MM_WBK_STALL", - H2C_MM_WBK_STALL_MASK}, - {"H2C_MM_DSC_FIFO_EP", - H2C_MM_DSC_FIFO_EP_MASK}, - {"H2C_MM_DSC_FIFO_FL", - H2C_MM_DSC_FIFO_FL_MASK}, -}; - - -static struct regfield_info - func_status_reg_field_info[] = { - {"FUNC_STATUS_REG_RSVD_1", - FUNC_STATUS_REG_RSVD_1_MASK}, - {"FUNC_STATUS_REG_CUR_SRC_FN", - FUNC_STATUS_REG_CUR_SRC_FN_MASK}, - {"FUNC_STATUS_REG_ACK", - FUNC_STATUS_REG_ACK_MASK}, - {"FUNC_STATUS_REG_O_MSG", - FUNC_STATUS_REG_O_MSG_MASK}, - {"FUNC_STATUS_REG_I_MSG", - FUNC_STATUS_REG_I_MSG_MASK}, -}; - - -static struct regfield_info - func_cmd_reg_field_info[] = { - {"FUNC_CMD_REG_RSVD_1", - FUNC_CMD_REG_RSVD_1_MASK}, - {"FUNC_CMD_REG_RSVD_2", - FUNC_CMD_REG_RSVD_2_MASK}, - {"FUNC_CMD_REG_MSG_RCV", - FUNC_CMD_REG_MSG_RCV_MASK}, - {"FUNC_CMD_REG_MSG_SENT", - FUNC_CMD_REG_MSG_SENT_MASK}, -}; - - -static struct regfield_info - func_interrupt_vector_reg_field_info[] = { - {"FUNC_INTERRUPT_VECTOR_REG_RSVD_1", - FUNC_INTERRUPT_VECTOR_REG_RSVD_1_MASK}, - {"FUNC_INTERRUPT_VECTOR_REG_IN", - FUNC_INTERRUPT_VECTOR_REG_IN_MASK}, -}; - - -static struct regfield_info - target_func_reg_field_info[] = { - {"TARGET_FUNC_REG_RSVD_1", - TARGET_FUNC_REG_RSVD_1_MASK}, - {"TARGET_FUNC_REG_N_ID", - TARGET_FUNC_REG_N_ID_MASK}, -}; - - -static struct regfield_info - func_interrupt_ctl_reg_field_info[] = { - {"FUNC_INTERRUPT_CTL_REG_RSVD_1", - FUNC_INTERRUPT_CTL_REG_RSVD_1_MASK}, - {"FUNC_INTERRUPT_CTL_REG_INT_EN", - FUNC_INTERRUPT_CTL_REG_INT_EN_MASK}, -}; - -static struct xreg_info qdma_s80_hard_config_regs[] = { -{"CFG_BLK_IDENTIFIER", 0x00, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(cfg_blk_identifier_field_info), - cfg_blk_identifier_field_info -}, -{"CFG_BLK_BUSDEV", 0x04, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(cfg_blk_busdev_field_info), - cfg_blk_busdev_field_info -}, -{"CFG_BLK_PCIE_MAX_PLD_SIZE", 0x08, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(cfg_blk_pcie_max_pld_size_field_info), - cfg_blk_pcie_max_pld_size_field_info -}, -{"CFG_BLK_PCIE_MAX_READ_REQ_SIZE", 0x0c, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(cfg_blk_pcie_max_read_req_size_field_info), - cfg_blk_pcie_max_read_req_size_field_info -}, -{"CFG_BLK_SYSTEM_ID", 0x10, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(cfg_blk_system_id_field_info), - cfg_blk_system_id_field_info -}, -{"CFG_BLK_MSI_ENABLE", 0x014, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(cfg_blk_msi_enable_field_info), - cfg_blk_msi_enable_field_info -}, -{"CFG_PCIE_DATA_WIDTH", 0x18, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(cfg_pcie_data_width_field_info), - cfg_pcie_data_width_field_info -}, -{"CFG_PCIE_CTL", 0x1c, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(cfg_pcie_ctl_field_info), - cfg_pcie_ctl_field_info -}, -{"CFG_AXI_USER_MAX_PLD_SIZE", 0x40, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(cfg_axi_user_max_pld_size_field_info), - cfg_axi_user_max_pld_size_field_info -}, -{"CFG_AXI_USER_MAX_READ_REQ_SIZE", 0x44, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(cfg_axi_user_max_read_req_size_field_info), - cfg_axi_user_max_read_req_size_field_info -}, -{"CFG_BLK_MISC_CTL", 0x4c, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(cfg_blk_misc_ctl_field_info), - cfg_blk_misc_ctl_field_info -}, -{"CFG_BLK_SCRATCH_0", 0x80, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(cfg_blk_scratch_0_field_info), - cfg_blk_scratch_0_field_info -}, -{"CFG_BLK_SCRATCH_1", 0x84, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(cfg_blk_scratch_1_field_info), - cfg_blk_scratch_1_field_info -}, -{"CFG_BLK_SCRATCH_2", 0x88, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(cfg_blk_scratch_2_field_info), - cfg_blk_scratch_2_field_info -}, -{"CFG_BLK_SCRATCH_3", 0x8c, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(cfg_blk_scratch_3_field_info), - cfg_blk_scratch_3_field_info -}, -{"CFG_BLK_SCRATCH_4", 0x90, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(cfg_blk_scratch_4_field_info), - cfg_blk_scratch_4_field_info -}, -{"CFG_BLK_SCRATCH_5", 0x94, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(cfg_blk_scratch_5_field_info), - cfg_blk_scratch_5_field_info -}, -{"CFG_BLK_SCRATCH_6", 0x98, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(cfg_blk_scratch_6_field_info), - cfg_blk_scratch_6_field_info -}, -{"CFG_BLK_SCRATCH_7", 0x9c, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(cfg_blk_scratch_7_field_info), - cfg_blk_scratch_7_field_info -}, -{"RAM_SBE_MSK_A", 0xf0, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(ram_sbe_msk_a_field_info), - ram_sbe_msk_a_field_info -}, -{"RAM_SBE_STS_A", 0xf4, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(ram_sbe_sts_a_field_info), - ram_sbe_sts_a_field_info -}, -{"RAM_DBE_MSK_A", 0xf8, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(ram_dbe_msk_a_field_info), - ram_dbe_msk_a_field_info -}, -{"RAM_DBE_STS_A", 0xfc, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(ram_dbe_sts_a_field_info), - ram_dbe_sts_a_field_info -}, -{"GLBL2_IDENTIFIER", 0x100, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(glbl2_identifier_field_info), - glbl2_identifier_field_info -}, -{"GLBL2_PF_BARLITE_INT", 0x104, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(glbl2_pf_barlite_int_field_info), - glbl2_pf_barlite_int_field_info -}, -{"GLBL2_PF_VF_BARLITE_INT", 0x108, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(glbl2_pf_vf_barlite_int_field_info), - glbl2_pf_vf_barlite_int_field_info -}, -{"GLBL2_PF_BARLITE_EXT", 0x10c, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(glbl2_pf_barlite_ext_field_info), - glbl2_pf_barlite_ext_field_info -}, -{"GLBL2_PF_VF_BARLITE_EXT", 0x110, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(glbl2_pf_vf_barlite_ext_field_info), - glbl2_pf_vf_barlite_ext_field_info -}, -{"GLBL2_CHANNEL_INST", 0x114, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(glbl2_channel_inst_field_info), - glbl2_channel_inst_field_info -}, -{"GLBL2_CHANNEL_MDMA", 0x118, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(glbl2_channel_mdma_field_info), - glbl2_channel_mdma_field_info -}, -{"GLBL2_CHANNEL_STRM", 0x11c, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(glbl2_channel_strm_field_info), - glbl2_channel_strm_field_info -}, -{"GLBL2_CHANNEL_CAP", 0x120, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(glbl2_channel_cap_field_info), - glbl2_channel_cap_field_info -}, -{"GLBL2_CHANNEL_PASID_CAP", 0x128, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(glbl2_channel_pasid_cap_field_info), - glbl2_channel_pasid_cap_field_info -}, -{"GLBL2_CHANNEL_FUNC_RET", 0x12c, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(glbl2_channel_func_ret_field_info), - glbl2_channel_func_ret_field_info -}, -{"GLBL2_SYSTEM_ID", 0x130, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(glbl2_system_id_field_info), - glbl2_system_id_field_info -}, -{"GLBL2_MISC_CAP", 0x134, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(glbl2_misc_cap_field_info), - glbl2_misc_cap_field_info -}, -{"GLBL2_DBG_PCIE_RQ0", 0x1b8, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(glbl2_dbg_pcie_rq0_field_info), - glbl2_dbg_pcie_rq0_field_info -}, -{"GLBL2_DBG_PCIE_RQ1", 0x1bc, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(glbl2_dbg_pcie_rq1_field_info), - glbl2_dbg_pcie_rq1_field_info -}, -{"GLBL2_DBG_AXIMM_WR0", 0x1c0, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(glbl2_dbg_aximm_wr0_field_info), - glbl2_dbg_aximm_wr0_field_info -}, -{"GLBL2_DBG_AXIMM_WR1", 0x1c4, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(glbl2_dbg_aximm_wr1_field_info), - glbl2_dbg_aximm_wr1_field_info -}, -{"GLBL2_DBG_AXIMM_RD0", 0x1c8, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(glbl2_dbg_aximm_rd0_field_info), - glbl2_dbg_aximm_rd0_field_info -}, -{"GLBL2_DBG_AXIMM_RD1", 0x1cc, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(glbl2_dbg_aximm_rd1_field_info), - glbl2_dbg_aximm_rd1_field_info -}, -{"GLBL_RNG_SZ_1", 0x204, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(glbl_rng_sz_1_field_info), - glbl_rng_sz_1_field_info -}, -{"GLBL_RNG_SZ_2", 0x208, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(glbl_rng_sz_2_field_info), - glbl_rng_sz_2_field_info -}, -{"GLBL_RNG_SZ_3", 0x20c, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(glbl_rng_sz_3_field_info), - glbl_rng_sz_3_field_info -}, -{"GLBL_RNG_SZ_4", 0x210, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(glbl_rng_sz_4_field_info), - glbl_rng_sz_4_field_info -}, -{"GLBL_RNG_SZ_5", 0x214, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(glbl_rng_sz_5_field_info), - glbl_rng_sz_5_field_info -}, -{"GLBL_RNG_SZ_6", 0x218, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(glbl_rng_sz_6_field_info), - glbl_rng_sz_6_field_info -}, -{"GLBL_RNG_SZ_7", 0x21c, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(glbl_rng_sz_7_field_info), - glbl_rng_sz_7_field_info -}, -{"GLBL_RNG_SZ_8", 0x220, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(glbl_rng_sz_8_field_info), - glbl_rng_sz_8_field_info -}, -{"GLBL_RNG_SZ_9", 0x224, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(glbl_rng_sz_9_field_info), - glbl_rng_sz_9_field_info -}, -{"GLBL_RNG_SZ_A", 0x228, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(glbl_rng_sz_a_field_info), - glbl_rng_sz_a_field_info -}, -{"GLBL_RNG_SZ_B", 0x22c, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(glbl_rng_sz_b_field_info), - glbl_rng_sz_b_field_info -}, -{"GLBL_RNG_SZ_C", 0x230, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(glbl_rng_sz_c_field_info), - glbl_rng_sz_c_field_info -}, -{"GLBL_RNG_SZ_D", 0x234, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(glbl_rng_sz_d_field_info), - glbl_rng_sz_d_field_info -}, -{"GLBL_RNG_SZ_E", 0x238, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(glbl_rng_sz_e_field_info), - glbl_rng_sz_e_field_info -}, -{"GLBL_RNG_SZ_F", 0x23c, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(glbl_rng_sz_f_field_info), - glbl_rng_sz_f_field_info -}, -{"GLBL_RNG_SZ_10", 0x240, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(glbl_rng_sz_10_field_info), - glbl_rng_sz_10_field_info -}, -{"GLBL_ERR_STAT", 0x248, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(glbl_err_stat_field_info), - glbl_err_stat_field_info -}, -{"GLBL_ERR_MASK", 0x24c, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(glbl_err_mask_field_info), - glbl_err_mask_field_info -}, -{"GLBL_DSC_CFG", 0x250, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(glbl_dsc_cfg_field_info), - glbl_dsc_cfg_field_info -}, -{"GLBL_DSC_ERR_STS", 0x254, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(glbl_dsc_err_sts_field_info), - glbl_dsc_err_sts_field_info -}, -{"GLBL_DSC_ERR_MSK", 0x258, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(glbl_dsc_err_msk_field_info), - glbl_dsc_err_msk_field_info -}, -{"GLBL_DSC_ERR_LOG0", 0x25c, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(glbl_dsc_err_log0_field_info), - glbl_dsc_err_log0_field_info -}, -{"GLBL_DSC_ERR_LOG1", 0x260, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(glbl_dsc_err_log1_field_info), - glbl_dsc_err_log1_field_info -}, -{"GLBL_TRQ_ERR_STS", 0x264, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(glbl_trq_err_sts_field_info), - glbl_trq_err_sts_field_info -}, -{"GLBL_TRQ_ERR_MSK", 0x268, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(glbl_trq_err_msk_field_info), - glbl_trq_err_msk_field_info -}, -{"GLBL_TRQ_ERR_LOG", 0x26c, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(glbl_trq_err_log_field_info), - glbl_trq_err_log_field_info -}, -{"GLBL_DSC_DBG_DAT0", 0x270, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(glbl_dsc_dbg_dat0_field_info), - glbl_dsc_dbg_dat0_field_info -}, -{"GLBL_DSC_DBG_DAT1", 0x274, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(glbl_dsc_dbg_dat1_field_info), - glbl_dsc_dbg_dat1_field_info -}, -{"TRQ_SEL_FMAP_0", 0x400, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_0_field_info), - trq_sel_fmap_0_field_info -}, -{"TRQ_SEL_FMAP_1", 0x404, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_1_field_info), - trq_sel_fmap_1_field_info -}, -{"TRQ_SEL_FMAP_2", 0x408, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_2_field_info), - trq_sel_fmap_2_field_info -}, -{"TRQ_SEL_FMAP_3", 0x40c, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_3_field_info), - trq_sel_fmap_3_field_info -}, -{"TRQ_SEL_FMAP_4", 0x410, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_4_field_info), - trq_sel_fmap_4_field_info -}, -{"TRQ_SEL_FMAP_5", 0x414, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_5_field_info), - trq_sel_fmap_5_field_info -}, -{"TRQ_SEL_FMAP_6", 0x418, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_6_field_info), - trq_sel_fmap_6_field_info -}, -{"TRQ_SEL_FMAP_7", 0x41c, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_7_field_info), - trq_sel_fmap_7_field_info -}, -{"TRQ_SEL_FMAP_8", 0x420, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_8_field_info), - trq_sel_fmap_8_field_info -}, -{"TRQ_SEL_FMAP_9", 0x424, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_9_field_info), - trq_sel_fmap_9_field_info -}, -{"TRQ_SEL_FMAP_A", 0x428, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_a_field_info), - trq_sel_fmap_a_field_info -}, -{"TRQ_SEL_FMAP_B", 0x42c, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_b_field_info), - trq_sel_fmap_b_field_info -}, -{"TRQ_SEL_FMAP_D", 0x430, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_d_field_info), - trq_sel_fmap_d_field_info -}, -{"TRQ_SEL_FMAP_E", 0x434, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_e_field_info), - trq_sel_fmap_e_field_info -}, -{"TRQ_SEL_FMAP_F", 0x438, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_f_field_info), - trq_sel_fmap_f_field_info -}, -{"TRQ_SEL_FMAP_10", 0x43c, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_10_field_info), - trq_sel_fmap_10_field_info -}, -{"TRQ_SEL_FMAP_11", 0x440, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_11_field_info), - trq_sel_fmap_11_field_info -}, -{"TRQ_SEL_FMAP_12", 0x444, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_12_field_info), - trq_sel_fmap_12_field_info -}, -{"TRQ_SEL_FMAP_13", 0x448, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_13_field_info), - trq_sel_fmap_13_field_info -}, -{"TRQ_SEL_FMAP_14", 0x44c, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_14_field_info), - trq_sel_fmap_14_field_info -}, -{"TRQ_SEL_FMAP_15", 0x450, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_15_field_info), - trq_sel_fmap_15_field_info -}, -{"TRQ_SEL_FMAP_16", 0x454, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_16_field_info), - trq_sel_fmap_16_field_info -}, -{"TRQ_SEL_FMAP_17", 0x458, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_17_field_info), - trq_sel_fmap_17_field_info -}, -{"TRQ_SEL_FMAP_18", 0x45c, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_18_field_info), - trq_sel_fmap_18_field_info -}, -{"TRQ_SEL_FMAP_19", 0x460, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_19_field_info), - trq_sel_fmap_19_field_info -}, -{"TRQ_SEL_FMAP_1A", 0x464, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_1a_field_info), - trq_sel_fmap_1a_field_info -}, -{"TRQ_SEL_FMAP_1B", 0x468, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_1b_field_info), - trq_sel_fmap_1b_field_info -}, -{"TRQ_SEL_FMAP_1C", 0x46c, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_1c_field_info), - trq_sel_fmap_1c_field_info -}, -{"TRQ_SEL_FMAP_1D", 0x470, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_1d_field_info), - trq_sel_fmap_1d_field_info -}, -{"TRQ_SEL_FMAP_1E", 0x474, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_1e_field_info), - trq_sel_fmap_1e_field_info -}, -{"TRQ_SEL_FMAP_1F", 0x478, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_1f_field_info), - trq_sel_fmap_1f_field_info -}, -{"TRQ_SEL_FMAP_20", 0x47c, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_20_field_info), - trq_sel_fmap_20_field_info -}, -{"TRQ_SEL_FMAP_21", 0x480, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_21_field_info), - trq_sel_fmap_21_field_info -}, -{"TRQ_SEL_FMAP_22", 0x484, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_22_field_info), - trq_sel_fmap_22_field_info -}, -{"TRQ_SEL_FMAP_23", 0x488, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_23_field_info), - trq_sel_fmap_23_field_info -}, -{"TRQ_SEL_FMAP_24", 0x48c, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_24_field_info), - trq_sel_fmap_24_field_info -}, -{"TRQ_SEL_FMAP_25", 0x490, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_25_field_info), - trq_sel_fmap_25_field_info -}, -{"TRQ_SEL_FMAP_26", 0x494, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_26_field_info), - trq_sel_fmap_26_field_info -}, -{"TRQ_SEL_FMAP_27", 0x498, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_27_field_info), - trq_sel_fmap_27_field_info -}, -{"TRQ_SEL_FMAP_28", 0x49c, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_28_field_info), - trq_sel_fmap_28_field_info -}, -{"TRQ_SEL_FMAP_29", 0x4a0, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_29_field_info), - trq_sel_fmap_29_field_info -}, -{"TRQ_SEL_FMAP_2A", 0x4a4, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_2a_field_info), - trq_sel_fmap_2a_field_info -}, -{"TRQ_SEL_FMAP_2B", 0x4a8, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_2b_field_info), - trq_sel_fmap_2b_field_info -}, -{"TRQ_SEL_FMAP_2C", 0x4ac, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_2c_field_info), - trq_sel_fmap_2c_field_info -}, -{"TRQ_SEL_FMAP_2D", 0x4b0, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_2d_field_info), - trq_sel_fmap_2d_field_info -}, -{"TRQ_SEL_FMAP_2E", 0x4b4, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_2e_field_info), - trq_sel_fmap_2e_field_info -}, -{"TRQ_SEL_FMAP_2F", 0x4b8, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_2f_field_info), - trq_sel_fmap_2f_field_info -}, -{"TRQ_SEL_FMAP_30", 0x4bc, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_30_field_info), - trq_sel_fmap_30_field_info -}, -{"TRQ_SEL_FMAP_31", 0x4d0, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_31_field_info), - trq_sel_fmap_31_field_info -}, -{"TRQ_SEL_FMAP_32", 0x4d4, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_32_field_info), - trq_sel_fmap_32_field_info -}, -{"TRQ_SEL_FMAP_33", 0x4d8, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_33_field_info), - trq_sel_fmap_33_field_info -}, -{"TRQ_SEL_FMAP_34", 0x4dc, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_34_field_info), - trq_sel_fmap_34_field_info -}, -{"TRQ_SEL_FMAP_35", 0x4e0, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_35_field_info), - trq_sel_fmap_35_field_info -}, -{"TRQ_SEL_FMAP_36", 0x4e4, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_36_field_info), - trq_sel_fmap_36_field_info -}, -{"TRQ_SEL_FMAP_37", 0x4e8, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_37_field_info), - trq_sel_fmap_37_field_info -}, -{"TRQ_SEL_FMAP_38", 0x4ec, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_38_field_info), - trq_sel_fmap_38_field_info -}, -{"TRQ_SEL_FMAP_39", 0x4f0, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_39_field_info), - trq_sel_fmap_39_field_info -}, -{"TRQ_SEL_FMAP_3A", 0x4f4, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_3a_field_info), - trq_sel_fmap_3a_field_info -}, -{"TRQ_SEL_FMAP_3B", 0x4f8, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_3b_field_info), - trq_sel_fmap_3b_field_info -}, -{"TRQ_SEL_FMAP_3C", 0x4fc, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_3c_field_info), - trq_sel_fmap_3c_field_info -}, -{"TRQ_SEL_FMAP_3D", 0x500, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_3d_field_info), - trq_sel_fmap_3d_field_info -}, -{"TRQ_SEL_FMAP_3E", 0x504, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_3e_field_info), - trq_sel_fmap_3e_field_info -}, -{"TRQ_SEL_FMAP_3F", 0x508, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_3f_field_info), - trq_sel_fmap_3f_field_info -}, -{"TRQ_SEL_FMAP_40", 0x50c, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_40_field_info), - trq_sel_fmap_40_field_info -}, -{"TRQ_SEL_FMAP_41", 0x510, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_41_field_info), - trq_sel_fmap_41_field_info -}, -{"TRQ_SEL_FMAP_42", 0x514, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_42_field_info), - trq_sel_fmap_42_field_info -}, -{"TRQ_SEL_FMAP_43", 0x518, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_43_field_info), - trq_sel_fmap_43_field_info -}, -{"TRQ_SEL_FMAP_44", 0x51c, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_44_field_info), - trq_sel_fmap_44_field_info -}, -{"TRQ_SEL_FMAP_45", 0x520, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_45_field_info), - trq_sel_fmap_45_field_info -}, -{"TRQ_SEL_FMAP_46", 0x524, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_46_field_info), - trq_sel_fmap_46_field_info -}, -{"TRQ_SEL_FMAP_47", 0x528, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_47_field_info), - trq_sel_fmap_47_field_info -}, -{"TRQ_SEL_FMAP_48", 0x52c, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_48_field_info), - trq_sel_fmap_48_field_info -}, -{"TRQ_SEL_FMAP_49", 0x530, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_49_field_info), - trq_sel_fmap_49_field_info -}, -{"TRQ_SEL_FMAP_4A", 0x534, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_4a_field_info), - trq_sel_fmap_4a_field_info -}, -{"TRQ_SEL_FMAP_4B", 0x538, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_4b_field_info), - trq_sel_fmap_4b_field_info -}, -{"TRQ_SEL_FMAP_4C", 0x53c, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_4c_field_info), - trq_sel_fmap_4c_field_info -}, -{"TRQ_SEL_FMAP_4D", 0x540, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_4d_field_info), - trq_sel_fmap_4d_field_info -}, -{"TRQ_SEL_FMAP_4E", 0x544, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_4e_field_info), - trq_sel_fmap_4e_field_info -}, -{"TRQ_SEL_FMAP_4F", 0x548, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_4f_field_info), - trq_sel_fmap_4f_field_info -}, -{"TRQ_SEL_FMAP_50", 0x54c, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_50_field_info), - trq_sel_fmap_50_field_info -}, -{"TRQ_SEL_FMAP_51", 0x550, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_51_field_info), - trq_sel_fmap_51_field_info -}, -{"TRQ_SEL_FMAP_52", 0x554, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_52_field_info), - trq_sel_fmap_52_field_info -}, -{"TRQ_SEL_FMAP_53", 0x558, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_53_field_info), - trq_sel_fmap_53_field_info -}, -{"TRQ_SEL_FMAP_54", 0x55c, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_54_field_info), - trq_sel_fmap_54_field_info -}, -{"TRQ_SEL_FMAP_55", 0x560, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_55_field_info), - trq_sel_fmap_55_field_info -}, -{"TRQ_SEL_FMAP_56", 0x564, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_56_field_info), - trq_sel_fmap_56_field_info -}, -{"TRQ_SEL_FMAP_57", 0x568, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_57_field_info), - trq_sel_fmap_57_field_info -}, -{"TRQ_SEL_FMAP_58", 0x56c, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_58_field_info), - trq_sel_fmap_58_field_info -}, -{"TRQ_SEL_FMAP_59", 0x570, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_59_field_info), - trq_sel_fmap_59_field_info -}, -{"TRQ_SEL_FMAP_5A", 0x574, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_5a_field_info), - trq_sel_fmap_5a_field_info -}, -{"TRQ_SEL_FMAP_5B", 0x578, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_5b_field_info), - trq_sel_fmap_5b_field_info -}, -{"TRQ_SEL_FMAP_5C", 0x57c, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_5c_field_info), - trq_sel_fmap_5c_field_info -}, -{"TRQ_SEL_FMAP_5D", 0x580, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_5d_field_info), - trq_sel_fmap_5d_field_info -}, -{"TRQ_SEL_FMAP_5E", 0x584, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_5e_field_info), - trq_sel_fmap_5e_field_info -}, -{"TRQ_SEL_FMAP_5F", 0x588, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_5f_field_info), - trq_sel_fmap_5f_field_info -}, -{"TRQ_SEL_FMAP_60", 0x58c, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_60_field_info), - trq_sel_fmap_60_field_info -}, -{"TRQ_SEL_FMAP_61", 0x590, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_61_field_info), - trq_sel_fmap_61_field_info -}, -{"TRQ_SEL_FMAP_62", 0x594, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_62_field_info), - trq_sel_fmap_62_field_info -}, -{"TRQ_SEL_FMAP_63", 0x598, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_63_field_info), - trq_sel_fmap_63_field_info -}, -{"TRQ_SEL_FMAP_64", 0x59c, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_64_field_info), - trq_sel_fmap_64_field_info -}, -{"TRQ_SEL_FMAP_65", 0x5a0, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_65_field_info), - trq_sel_fmap_65_field_info -}, -{"TRQ_SEL_FMAP_66", 0x5a4, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_66_field_info), - trq_sel_fmap_66_field_info -}, -{"TRQ_SEL_FMAP_67", 0x5a8, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_67_field_info), - trq_sel_fmap_67_field_info -}, -{"TRQ_SEL_FMAP_68", 0x5ac, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_68_field_info), - trq_sel_fmap_68_field_info -}, -{"TRQ_SEL_FMAP_69", 0x5b0, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_69_field_info), - trq_sel_fmap_69_field_info -}, -{"TRQ_SEL_FMAP_6A", 0x5b4, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_6a_field_info), - trq_sel_fmap_6a_field_info -}, -{"TRQ_SEL_FMAP_6B", 0x5b8, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_6b_field_info), - trq_sel_fmap_6b_field_info -}, -{"TRQ_SEL_FMAP_6C", 0x5bc, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_6c_field_info), - trq_sel_fmap_6c_field_info -}, -{"TRQ_SEL_FMAP_6D", 0x5c0, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_6d_field_info), - trq_sel_fmap_6d_field_info -}, -{"TRQ_SEL_FMAP_6E", 0x5c4, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_6e_field_info), - trq_sel_fmap_6e_field_info -}, -{"TRQ_SEL_FMAP_6F", 0x5c8, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_6f_field_info), - trq_sel_fmap_6f_field_info -}, -{"TRQ_SEL_FMAP_70", 0x5cc, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_70_field_info), - trq_sel_fmap_70_field_info -}, -{"TRQ_SEL_FMAP_71", 0x5d0, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_71_field_info), - trq_sel_fmap_71_field_info -}, -{"TRQ_SEL_FMAP_72", 0x5d4, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_72_field_info), - trq_sel_fmap_72_field_info -}, -{"TRQ_SEL_FMAP_73", 0x5d8, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_73_field_info), - trq_sel_fmap_73_field_info -}, -{"TRQ_SEL_FMAP_74", 0x5dc, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_74_field_info), - trq_sel_fmap_74_field_info -}, -{"TRQ_SEL_FMAP_75", 0x5e0, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_75_field_info), - trq_sel_fmap_75_field_info -}, -{"TRQ_SEL_FMAP_76", 0x5e4, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_76_field_info), - trq_sel_fmap_76_field_info -}, -{"TRQ_SEL_FMAP_77", 0x5e8, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_77_field_info), - trq_sel_fmap_77_field_info -}, -{"TRQ_SEL_FMAP_78", 0x5ec, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_78_field_info), - trq_sel_fmap_78_field_info -}, -{"TRQ_SEL_FMAP_79", 0x5f0, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_79_field_info), - trq_sel_fmap_79_field_info -}, -{"TRQ_SEL_FMAP_7A", 0x5f4, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_7a_field_info), - trq_sel_fmap_7a_field_info -}, -{"TRQ_SEL_FMAP_7B", 0x5f8, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_7b_field_info), - trq_sel_fmap_7b_field_info -}, -{"TRQ_SEL_FMAP_7C", 0x5fc, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_7c_field_info), - trq_sel_fmap_7c_field_info -}, -{"TRQ_SEL_FMAP_7D", 0x600, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_7d_field_info), - trq_sel_fmap_7d_field_info -}, -{"TRQ_SEL_FMAP_7E", 0x604, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_7e_field_info), - trq_sel_fmap_7e_field_info -}, -{"TRQ_SEL_FMAP_7F", 0x608, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_7f_field_info), - trq_sel_fmap_7f_field_info -}, -{"TRQ_SEL_FMAP_80", 0x60c, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_80_field_info), - trq_sel_fmap_80_field_info -}, -{"TRQ_SEL_FMAP_81", 0x610, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_81_field_info), - trq_sel_fmap_81_field_info -}, -{"TRQ_SEL_FMAP_82", 0x614, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_82_field_info), - trq_sel_fmap_82_field_info -}, -{"TRQ_SEL_FMAP_83", 0x618, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_83_field_info), - trq_sel_fmap_83_field_info -}, -{"TRQ_SEL_FMAP_84", 0x61c, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_84_field_info), - trq_sel_fmap_84_field_info -}, -{"TRQ_SEL_FMAP_85", 0x620, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_85_field_info), - trq_sel_fmap_85_field_info -}, -{"TRQ_SEL_FMAP_86", 0x624, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_86_field_info), - trq_sel_fmap_86_field_info -}, -{"TRQ_SEL_FMAP_87", 0x628, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_87_field_info), - trq_sel_fmap_87_field_info -}, -{"TRQ_SEL_FMAP_88", 0x62c, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_88_field_info), - trq_sel_fmap_88_field_info -}, -{"TRQ_SEL_FMAP_89", 0x630, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_89_field_info), - trq_sel_fmap_89_field_info -}, -{"TRQ_SEL_FMAP_8A", 0x634, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_8a_field_info), - trq_sel_fmap_8a_field_info -}, -{"TRQ_SEL_FMAP_8B", 0x638, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_8b_field_info), - trq_sel_fmap_8b_field_info -}, -{"TRQ_SEL_FMAP_8C", 0x63c, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_8c_field_info), - trq_sel_fmap_8c_field_info -}, -{"TRQ_SEL_FMAP_8D", 0x640, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_8d_field_info), - trq_sel_fmap_8d_field_info -}, -{"TRQ_SEL_FMAP_8E", 0x644, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_8e_field_info), - trq_sel_fmap_8e_field_info -}, -{"TRQ_SEL_FMAP_8F", 0x648, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_8f_field_info), - trq_sel_fmap_8f_field_info -}, -{"TRQ_SEL_FMAP_90", 0x64c, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_90_field_info), - trq_sel_fmap_90_field_info -}, -{"TRQ_SEL_FMAP_91", 0x650, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_91_field_info), - trq_sel_fmap_91_field_info -}, -{"TRQ_SEL_FMAP_92", 0x654, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_92_field_info), - trq_sel_fmap_92_field_info -}, -{"TRQ_SEL_FMAP_93", 0x658, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_93_field_info), - trq_sel_fmap_93_field_info -}, -{"TRQ_SEL_FMAP_94", 0x65c, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_94_field_info), - trq_sel_fmap_94_field_info -}, -{"TRQ_SEL_FMAP_95", 0x660, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_95_field_info), - trq_sel_fmap_95_field_info -}, -{"TRQ_SEL_FMAP_96", 0x664, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_96_field_info), - trq_sel_fmap_96_field_info -}, -{"TRQ_SEL_FMAP_97", 0x668, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_97_field_info), - trq_sel_fmap_97_field_info -}, -{"TRQ_SEL_FMAP_98", 0x66c, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_98_field_info), - trq_sel_fmap_98_field_info -}, -{"TRQ_SEL_FMAP_99", 0x670, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_99_field_info), - trq_sel_fmap_99_field_info -}, -{"TRQ_SEL_FMAP_9A", 0x674, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_9a_field_info), - trq_sel_fmap_9a_field_info -}, -{"TRQ_SEL_FMAP_9B", 0x678, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_9b_field_info), - trq_sel_fmap_9b_field_info -}, -{"TRQ_SEL_FMAP_9C", 0x67c, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_9c_field_info), - trq_sel_fmap_9c_field_info -}, -{"TRQ_SEL_FMAP_9D", 0x680, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_9d_field_info), - trq_sel_fmap_9d_field_info -}, -{"TRQ_SEL_FMAP_9E", 0x684, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_9e_field_info), - trq_sel_fmap_9e_field_info -}, -{"TRQ_SEL_FMAP_9F", 0x688, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_9f_field_info), - trq_sel_fmap_9f_field_info -}, -{"TRQ_SEL_FMAP_A0", 0x68c, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_a0_field_info), - trq_sel_fmap_a0_field_info -}, -{"TRQ_SEL_FMAP_A1", 0x690, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_a1_field_info), - trq_sel_fmap_a1_field_info -}, -{"TRQ_SEL_FMAP_A2", 0x694, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_a2_field_info), - trq_sel_fmap_a2_field_info -}, -{"TRQ_SEL_FMAP_A3", 0x698, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_a3_field_info), - trq_sel_fmap_a3_field_info -}, -{"TRQ_SEL_FMAP_A4", 0x69c, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_a4_field_info), - trq_sel_fmap_a4_field_info -}, -{"TRQ_SEL_FMAP_A5", 0x6a0, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_a5_field_info), - trq_sel_fmap_a5_field_info -}, -{"TRQ_SEL_FMAP_A6", 0x6a4, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_a6_field_info), - trq_sel_fmap_a6_field_info -}, -{"TRQ_SEL_FMAP_A7", 0x6a8, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_a7_field_info), - trq_sel_fmap_a7_field_info -}, -{"TRQ_SEL_FMAP_A8", 0x6ac, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_a8_field_info), - trq_sel_fmap_a8_field_info -}, -{"TRQ_SEL_FMAP_A9", 0x6b0, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_a9_field_info), - trq_sel_fmap_a9_field_info -}, -{"TRQ_SEL_FMAP_AA", 0x6b4, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_aa_field_info), - trq_sel_fmap_aa_field_info -}, -{"TRQ_SEL_FMAP_AB", 0x6b8, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_ab_field_info), - trq_sel_fmap_ab_field_info -}, -{"TRQ_SEL_FMAP_AC", 0x6bc, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_ac_field_info), - trq_sel_fmap_ac_field_info -}, -{"TRQ_SEL_FMAP_AD", 0x6d0, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_ad_field_info), - trq_sel_fmap_ad_field_info -}, -{"TRQ_SEL_FMAP_AE", 0x6d4, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_ae_field_info), - trq_sel_fmap_ae_field_info -}, -{"TRQ_SEL_FMAP_AF", 0x6d8, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_af_field_info), - trq_sel_fmap_af_field_info -}, -{"TRQ_SEL_FMAP_B0", 0x6dc, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_b0_field_info), - trq_sel_fmap_b0_field_info -}, -{"TRQ_SEL_FMAP_B1", 0x6e0, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_b1_field_info), - trq_sel_fmap_b1_field_info -}, -{"TRQ_SEL_FMAP_B2", 0x6e4, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_b2_field_info), - trq_sel_fmap_b2_field_info -}, -{"TRQ_SEL_FMAP_B3", 0x6e8, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_b3_field_info), - trq_sel_fmap_b3_field_info -}, -{"TRQ_SEL_FMAP_B4", 0x6ec, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_b4_field_info), - trq_sel_fmap_b4_field_info -}, -{"TRQ_SEL_FMAP_B5", 0x6f0, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_b5_field_info), - trq_sel_fmap_b5_field_info -}, -{"TRQ_SEL_FMAP_B6", 0x6f4, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_b6_field_info), - trq_sel_fmap_b6_field_info -}, -{"TRQ_SEL_FMAP_B7", 0x6f8, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_b7_field_info), - trq_sel_fmap_b7_field_info -}, -{"TRQ_SEL_FMAP_B8", 0x6fc, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_b8_field_info), - trq_sel_fmap_b8_field_info -}, -{"TRQ_SEL_FMAP_B9", 0x700, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_b9_field_info), - trq_sel_fmap_b9_field_info -}, -{"TRQ_SEL_FMAP_BA", 0x704, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_ba_field_info), - trq_sel_fmap_ba_field_info -}, -{"TRQ_SEL_FMAP_BB", 0x708, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_bb_field_info), - trq_sel_fmap_bb_field_info -}, -{"TRQ_SEL_FMAP_BC", 0x70c, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_bc_field_info), - trq_sel_fmap_bc_field_info -}, -{"TRQ_SEL_FMAP_BD", 0x710, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_bd_field_info), - trq_sel_fmap_bd_field_info -}, -{"TRQ_SEL_FMAP_BE", 0x714, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_be_field_info), - trq_sel_fmap_be_field_info -}, -{"TRQ_SEL_FMAP_BF", 0x718, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_bf_field_info), - trq_sel_fmap_bf_field_info -}, -{"TRQ_SEL_FMAP_C0", 0x71c, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_c0_field_info), - trq_sel_fmap_c0_field_info -}, -{"TRQ_SEL_FMAP_C1", 0x720, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_c1_field_info), - trq_sel_fmap_c1_field_info -}, -{"TRQ_SEL_FMAP_C2", 0x734, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_c2_field_info), - trq_sel_fmap_c2_field_info -}, -{"TRQ_SEL_FMAP_C3", 0x748, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_c3_field_info), - trq_sel_fmap_c3_field_info -}, -{"TRQ_SEL_FMAP_C4", 0x74c, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_c4_field_info), - trq_sel_fmap_c4_field_info -}, -{"TRQ_SEL_FMAP_C5", 0x750, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_c5_field_info), - trq_sel_fmap_c5_field_info -}, -{"TRQ_SEL_FMAP_C6", 0x754, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_c6_field_info), - trq_sel_fmap_c6_field_info -}, -{"TRQ_SEL_FMAP_C7", 0x758, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_c7_field_info), - trq_sel_fmap_c7_field_info -}, -{"TRQ_SEL_FMAP_C8", 0x75c, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_c8_field_info), - trq_sel_fmap_c8_field_info -}, -{"TRQ_SEL_FMAP_C9", 0x760, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_c9_field_info), - trq_sel_fmap_c9_field_info -}, -{"TRQ_SEL_FMAP_CA", 0x764, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_ca_field_info), - trq_sel_fmap_ca_field_info -}, -{"TRQ_SEL_FMAP_CB", 0x768, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_cb_field_info), - trq_sel_fmap_cb_field_info -}, -{"TRQ_SEL_FMAP_CC", 0x76c, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_cc_field_info), - trq_sel_fmap_cc_field_info -}, -{"TRQ_SEL_FMAP_CD", 0x770, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_cd_field_info), - trq_sel_fmap_cd_field_info -}, -{"TRQ_SEL_FMAP_CE", 0x774, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_ce_field_info), - trq_sel_fmap_ce_field_info -}, -{"TRQ_SEL_FMAP_CF", 0x778, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_cf_field_info), - trq_sel_fmap_cf_field_info -}, -{"TRQ_SEL_FMAP_D0", 0x77c, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_d0_field_info), - trq_sel_fmap_d0_field_info -}, -{"TRQ_SEL_FMAP_D1", 0x780, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_d1_field_info), - trq_sel_fmap_d1_field_info -}, -{"TRQ_SEL_FMAP_D2", 0x784, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_d2_field_info), - trq_sel_fmap_d2_field_info -}, -{"TRQ_SEL_FMAP_D3", 0x788, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_d3_field_info), - trq_sel_fmap_d3_field_info -}, -{"TRQ_SEL_FMAP_D4", 0x78c, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_d4_field_info), - trq_sel_fmap_d4_field_info -}, -{"TRQ_SEL_FMAP_D5", 0x790, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_d5_field_info), - trq_sel_fmap_d5_field_info -}, -{"TRQ_SEL_FMAP_D6", 0x794, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_d6_field_info), - trq_sel_fmap_d6_field_info -}, -{"TRQ_SEL_FMAP_D7", 0x798, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_d7_field_info), - trq_sel_fmap_d7_field_info -}, -{"TRQ_SEL_FMAP_D8", 0x79c, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_d8_field_info), - trq_sel_fmap_d8_field_info -}, -{"TRQ_SEL_FMAP_D9", 0x7a0, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_d9_field_info), - trq_sel_fmap_d9_field_info -}, -{"TRQ_SEL_FMAP_DA", 0x7a4, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_da_field_info), - trq_sel_fmap_da_field_info -}, -{"TRQ_SEL_FMAP_DB", 0x7a8, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_db_field_info), - trq_sel_fmap_db_field_info -}, -{"TRQ_SEL_FMAP_DC", 0x7ac, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_dc_field_info), - trq_sel_fmap_dc_field_info -}, -{"TRQ_SEL_FMAP_DD", 0x7b0, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_dd_field_info), - trq_sel_fmap_dd_field_info -}, -{"TRQ_SEL_FMAP_DE", 0x7b4, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_de_field_info), - trq_sel_fmap_de_field_info -}, -{"TRQ_SEL_FMAP_DF", 0x7b8, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_df_field_info), - trq_sel_fmap_df_field_info -}, -{"TRQ_SEL_FMAP_E0", 0x7bc, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_e0_field_info), - trq_sel_fmap_e0_field_info -}, -{"TRQ_SEL_FMAP_E1", 0x7c0, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_e1_field_info), - trq_sel_fmap_e1_field_info -}, -{"TRQ_SEL_FMAP_E2", 0x7c4, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_e2_field_info), - trq_sel_fmap_e2_field_info -}, -{"TRQ_SEL_FMAP_E3", 0x7c8, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_e3_field_info), - trq_sel_fmap_e3_field_info -}, -{"TRQ_SEL_FMAP_E4", 0x7cc, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_e4_field_info), - trq_sel_fmap_e4_field_info -}, -{"TRQ_SEL_FMAP_E5", 0x7d0, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_e5_field_info), - trq_sel_fmap_e5_field_info -}, -{"TRQ_SEL_FMAP_E6", 0x7d4, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_e6_field_info), - trq_sel_fmap_e6_field_info -}, -{"TRQ_SEL_FMAP_E7", 0x7d8, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_e7_field_info), - trq_sel_fmap_e7_field_info -}, -{"TRQ_SEL_FMAP_E8", 0x7dc, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_e8_field_info), - trq_sel_fmap_e8_field_info -}, -{"TRQ_SEL_FMAP_E9", 0x7e0, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_e9_field_info), - trq_sel_fmap_e9_field_info -}, -{"TRQ_SEL_FMAP_EA", 0x7e4, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_ea_field_info), - trq_sel_fmap_ea_field_info -}, -{"TRQ_SEL_FMAP_EB", 0x7e8, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_eb_field_info), - trq_sel_fmap_eb_field_info -}, -{"TRQ_SEL_FMAP_EC", 0x7ec, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_ec_field_info), - trq_sel_fmap_ec_field_info -}, -{"TRQ_SEL_FMAP_ED", 0x7f0, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_ed_field_info), - trq_sel_fmap_ed_field_info -}, -{"TRQ_SEL_FMAP_EE", 0x7f4, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_ee_field_info), - trq_sel_fmap_ee_field_info -}, -{"TRQ_SEL_FMAP_EF", 0x7f8, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_ef_field_info), - trq_sel_fmap_ef_field_info -}, -{"TRQ_SEL_FMAP_F0", 0x7fc, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(trq_sel_fmap_f0_field_info), - trq_sel_fmap_f0_field_info -}, -{"IND_CTXT_DATA_3", 0x804, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(ind_ctxt_data_3_field_info), - ind_ctxt_data_3_field_info -}, -{"IND_CTXT_DATA_2", 0x808, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(ind_ctxt_data_2_field_info), - ind_ctxt_data_2_field_info -}, -{"IND_CTXT_DATA_1", 0x80c, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(ind_ctxt_data_1_field_info), - ind_ctxt_data_1_field_info -}, -{"IND_CTXT_DATA_0", 0x810, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(ind_ctxt_data_0_field_info), - ind_ctxt_data_0_field_info -}, -{"IND_CTXT3", 0x814, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(ind_ctxt3_field_info), - ind_ctxt3_field_info -}, -{"IND_CTXT2", 0x818, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(ind_ctxt2_field_info), - ind_ctxt2_field_info -}, -{"IND_CTXT1", 0x81c, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(ind_ctxt1_field_info), - ind_ctxt1_field_info -}, -{"IND_CTXT0", 0x820, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(ind_ctxt0_field_info), - ind_ctxt0_field_info -}, -{"IND_CTXT_CMD", 0x824, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(ind_ctxt_cmd_field_info), - ind_ctxt_cmd_field_info -}, -{"C2H_TIMER_CNT_1", 0xa00, - 1, 0, 0, 0, - 0, QDMA_COMPLETION_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_timer_cnt_1_field_info), - c2h_timer_cnt_1_field_info -}, -{"C2H_TIMER_CNT_2", 0xa04, - 1, 0, 0, 0, - 0, QDMA_COMPLETION_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_timer_cnt_2_field_info), - c2h_timer_cnt_2_field_info -}, -{"C2H_TIMER_CNT_3", 0xa08, - 1, 0, 0, 0, - 0, QDMA_COMPLETION_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_timer_cnt_3_field_info), - c2h_timer_cnt_3_field_info -}, -{"C2H_TIMER_CNT_4", 0xa0c, - 1, 0, 0, 0, - 0, QDMA_COMPLETION_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_timer_cnt_4_field_info), - c2h_timer_cnt_4_field_info -}, -{"C2H_TIMER_CNT_5", 0xa10, - 1, 0, 0, 0, - 0, QDMA_COMPLETION_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_timer_cnt_5_field_info), - c2h_timer_cnt_5_field_info -}, -{"C2H_TIMER_CNT_6", 0xa14, - 1, 0, 0, 0, - 0, QDMA_COMPLETION_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_timer_cnt_6_field_info), - c2h_timer_cnt_6_field_info -}, -{"C2H_TIMER_CNT_7", 0xa18, - 1, 0, 0, 0, - 0, QDMA_COMPLETION_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_timer_cnt_7_field_info), - c2h_timer_cnt_7_field_info -}, -{"C2H_TIMER_CNT_8", 0xa1c, - 1, 0, 0, 0, - 0, QDMA_COMPLETION_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_timer_cnt_8_field_info), - c2h_timer_cnt_8_field_info -}, -{"C2H_TIMER_CNT_9", 0xa20, - 1, 0, 0, 0, - 0, QDMA_COMPLETION_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_timer_cnt_9_field_info), - c2h_timer_cnt_9_field_info -}, -{"C2H_TIMER_CNT_A", 0xa24, - 1, 0, 0, 0, - 0, QDMA_COMPLETION_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_timer_cnt_a_field_info), - c2h_timer_cnt_a_field_info -}, -{"C2H_TIMER_CNT_B", 0xa28, - 1, 0, 0, 0, - 0, QDMA_COMPLETION_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_timer_cnt_b_field_info), - c2h_timer_cnt_b_field_info -}, -{"C2H_TIMER_CNT_C", 0xa2c, - 1, 0, 0, 0, - 0, QDMA_COMPLETION_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_timer_cnt_c_field_info), - c2h_timer_cnt_c_field_info -}, -{"C2H_TIMER_CNT_D", 0xa30, - 1, 0, 0, 0, - 0, QDMA_COMPLETION_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_timer_cnt_d_field_info), - c2h_timer_cnt_d_field_info -}, -{"C2H_TIMER_CNT_E", 0xa34, - 1, 0, 0, 0, - 0, QDMA_COMPLETION_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_timer_cnt_e_field_info), - c2h_timer_cnt_e_field_info -}, -{"C2H_TIMER_CNT_F", 0xa38, - 1, 0, 0, 0, - 0, QDMA_COMPLETION_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_timer_cnt_f_field_info), - c2h_timer_cnt_f_field_info -}, -{"C2H_TIMER_CNT_10", 0xa3c, - 1, 0, 0, 0, - 0, QDMA_COMPLETION_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_timer_cnt_10_field_info), - c2h_timer_cnt_10_field_info -}, -{"C2H_CNT_TH_1", 0xa40, - 1, 0, 0, 0, - 0, QDMA_COMPLETION_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_cnt_th_1_field_info), - c2h_cnt_th_1_field_info -}, -{"C2H_CNT_TH_2", 0xa44, - 1, 0, 0, 0, - 0, QDMA_COMPLETION_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_cnt_th_2_field_info), - c2h_cnt_th_2_field_info -}, -{"C2H_CNT_TH_3", 0xa48, - 1, 0, 0, 0, - 0, QDMA_COMPLETION_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_cnt_th_3_field_info), - c2h_cnt_th_3_field_info -}, -{"C2H_CNT_TH_4", 0xa4c, - 1, 0, 0, 0, - 0, QDMA_COMPLETION_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_cnt_th_4_field_info), - c2h_cnt_th_4_field_info -}, -{"C2H_CNT_TH_5", 0xa50, - 1, 0, 0, 0, - 0, QDMA_COMPLETION_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_cnt_th_5_field_info), - c2h_cnt_th_5_field_info -}, -{"C2H_CNT_TH_6", 0xa54, - 1, 0, 0, 0, - 0, QDMA_COMPLETION_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_cnt_th_6_field_info), - c2h_cnt_th_6_field_info -}, -{"C2H_CNT_TH_7", 0xa58, - 1, 0, 0, 0, - 0, QDMA_COMPLETION_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_cnt_th_7_field_info), - c2h_cnt_th_7_field_info -}, -{"C2H_CNT_TH_8", 0xa5c, - 1, 0, 0, 0, - 0, QDMA_COMPLETION_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_cnt_th_8_field_info), - c2h_cnt_th_8_field_info -}, -{"C2H_CNT_TH_9", 0xa60, - 1, 0, 0, 0, - 0, QDMA_COMPLETION_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_cnt_th_9_field_info), - c2h_cnt_th_9_field_info -}, -{"C2H_CNT_TH_A", 0xa64, - 1, 0, 0, 0, - 0, QDMA_COMPLETION_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_cnt_th_a_field_info), - c2h_cnt_th_a_field_info -}, -{"C2H_CNT_TH_B", 0xa68, - 1, 0, 0, 0, - 0, QDMA_COMPLETION_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_cnt_th_b_field_info), - c2h_cnt_th_b_field_info -}, -{"C2H_CNT_TH_C", 0xa6c, - 1, 0, 0, 0, - 0, QDMA_COMPLETION_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_cnt_th_c_field_info), - c2h_cnt_th_c_field_info -}, -{"C2H_CNT_TH_D", 0xa70, - 1, 0, 0, 0, - 0, QDMA_COMPLETION_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_cnt_th_d_field_info), - c2h_cnt_th_d_field_info -}, -{"C2H_CNT_TH_E", 0xa74, - 1, 0, 0, 0, - 0, QDMA_COMPLETION_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_cnt_th_e_field_info), - c2h_cnt_th_e_field_info -}, -{"C2H_CNT_TH_F", 0xa78, - 1, 0, 0, 0, - 0, QDMA_COMPLETION_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_cnt_th_f_field_info), - c2h_cnt_th_f_field_info -}, -{"C2H_CNT_TH_10", 0xa7c, - 1, 0, 0, 0, - 0, QDMA_COMPLETION_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_cnt_th_10_field_info), - c2h_cnt_th_10_field_info -}, -{"C2H_QID2VEC_MAP_QID", 0xa80, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_qid2vec_map_qid_field_info), - c2h_qid2vec_map_qid_field_info -}, -{"C2H_QID2VEC_MAP", 0xa84, - 1, 0, 0, 0, - 0, QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_qid2vec_map_field_info), - c2h_qid2vec_map_field_info -}, -{"C2H_STAT_S_AXIS_C2H_ACCEPTED", 0xa88, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(c2h_stat_s_axis_c2h_accepted_field_info), - c2h_stat_s_axis_c2h_accepted_field_info -}, -{"C2H_STAT_S_AXIS_WRB_ACCEPTED", 0xa8c, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(c2h_stat_s_axis_wrb_accepted_field_info), - c2h_stat_s_axis_wrb_accepted_field_info -}, -{"C2H_STAT_DESC_RSP_PKT_ACCEPTED", 0xa90, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(c2h_stat_desc_rsp_pkt_accepted_field_info), - c2h_stat_desc_rsp_pkt_accepted_field_info -}, -{"C2H_STAT_AXIS_PKG_CMP", 0xa94, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(c2h_stat_axis_pkg_cmp_field_info), - c2h_stat_axis_pkg_cmp_field_info -}, -{"C2H_STAT_DESC_RSP_ACCEPTED", 0xa98, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_stat_desc_rsp_accepted_field_info), - c2h_stat_desc_rsp_accepted_field_info -}, -{"C2H_STAT_DESC_RSP_CMP", 0xa9c, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_stat_desc_rsp_cmp_field_info), - c2h_stat_desc_rsp_cmp_field_info -}, -{"C2H_STAT_WRQ_OUT", 0xaa0, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_stat_wrq_out_field_info), - c2h_stat_wrq_out_field_info -}, -{"C2H_STAT_WPL_REN_ACCEPTED", 0xaa4, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_stat_wpl_ren_accepted_field_info), - c2h_stat_wpl_ren_accepted_field_info -}, -{"C2H_STAT_TOTAL_WRQ_LEN", 0xaa8, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_stat_total_wrq_len_field_info), - c2h_stat_total_wrq_len_field_info -}, -{"C2H_STAT_TOTAL_WPL_LEN", 0xaac, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_stat_total_wpl_len_field_info), - c2h_stat_total_wpl_len_field_info -}, -{"C2H_BUF_SZ_0", 0xab0, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_buf_sz_0_field_info), - c2h_buf_sz_0_field_info -}, -{"C2H_BUF_SZ_1", 0xab4, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_buf_sz_1_field_info), - c2h_buf_sz_1_field_info -}, -{"C2H_BUF_SZ_2", 0xab8, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_buf_sz_2_field_info), - c2h_buf_sz_2_field_info -}, -{"C2H_BUF_SZ_3", 0xabc, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_buf_sz_3_field_info), - c2h_buf_sz_3_field_info -}, -{"C2H_BUF_SZ_4", 0xac0, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_buf_sz_4_field_info), - c2h_buf_sz_4_field_info -}, -{"C2H_BUF_SZ_5", 0xac4, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_buf_sz_5_field_info), - c2h_buf_sz_5_field_info -}, -{"C2H_BUF_SZ_7", 0xac8, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_buf_sz_7_field_info), - c2h_buf_sz_7_field_info -}, -{"C2H_BUF_SZ_8", 0xacc, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_buf_sz_8_field_info), - c2h_buf_sz_8_field_info -}, -{"C2H_BUF_SZ_9", 0xad0, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_buf_sz_9_field_info), - c2h_buf_sz_9_field_info -}, -{"C2H_BUF_SZ_10", 0xad4, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_buf_sz_10_field_info), - c2h_buf_sz_10_field_info -}, -{"C2H_BUF_SZ_11", 0xad8, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_buf_sz_11_field_info), - c2h_buf_sz_11_field_info -}, -{"C2H_BUF_SZ_12", 0xae0, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_buf_sz_12_field_info), - c2h_buf_sz_12_field_info -}, -{"C2H_BUF_SZ_13", 0xae4, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_buf_sz_13_field_info), - c2h_buf_sz_13_field_info -}, -{"C2H_BUF_SZ_14", 0xae8, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_buf_sz_14_field_info), - c2h_buf_sz_14_field_info -}, -{"C2H_BUF_SZ_15", 0xaec, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_buf_sz_15_field_info), - c2h_buf_sz_15_field_info -}, -{"C2H_ERR_STAT", 0xaf0, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(c2h_err_stat_field_info), - c2h_err_stat_field_info -}, -{"C2H_ERR_MASK", 0xaf4, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(c2h_err_mask_field_info), - c2h_err_mask_field_info -}, -{"C2H_FATAL_ERR_STAT", 0xaf8, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(c2h_fatal_err_stat_field_info), - c2h_fatal_err_stat_field_info -}, -{"C2H_FATAL_ERR_MASK", 0xafc, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(c2h_fatal_err_mask_field_info), - c2h_fatal_err_mask_field_info -}, -{"C2H_FATAL_ERR_ENABLE", 0xb00, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(c2h_fatal_err_enable_field_info), - c2h_fatal_err_enable_field_info -}, -{"GLBL_ERR_INT", 0xb04, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(glbl_err_int_field_info), - glbl_err_int_field_info -}, -{"C2H_PFCH_CFG", 0xb08, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_pfch_cfg_field_info), - c2h_pfch_cfg_field_info -}, -{"C2H_INT_TIMER_TICK", 0xb0c, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_int_timer_tick_field_info), - c2h_int_timer_tick_field_info -}, -{"C2H_STAT_DESC_RSP_DROP_ACCEPTED", 0xb10, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(c2h_stat_desc_rsp_drop_accepted_field_info), - c2h_stat_desc_rsp_drop_accepted_field_info -}, -{"C2H_STAT_DESC_RSP_ERR_ACCEPTED", 0xb14, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(c2h_stat_desc_rsp_err_accepted_field_info), - c2h_stat_desc_rsp_err_accepted_field_info -}, -{"C2H_STAT_DESC_REQ", 0xb18, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_stat_desc_req_field_info), - c2h_stat_desc_req_field_info -}, -{"C2H_STAT_DBG_DMA_ENG_0", 0xb1c, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_stat_dbg_dma_eng_0_field_info), - c2h_stat_dbg_dma_eng_0_field_info -}, -{"C2H_STAT_DBG_DMA_ENG_1", 0xb20, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_stat_dbg_dma_eng_1_field_info), - c2h_stat_dbg_dma_eng_1_field_info -}, -{"C2H_STAT_DBG_DMA_ENG_2", 0xb24, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_stat_dbg_dma_eng_2_field_info), - c2h_stat_dbg_dma_eng_2_field_info -}, -{"C2H_STAT_DBG_DMA_ENG_3", 0xb28, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_stat_dbg_dma_eng_3_field_info), - c2h_stat_dbg_dma_eng_3_field_info -}, -{"C2H_DBG_PFCH_ERR_CTXT", 0xb2c, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_dbg_pfch_err_ctxt_field_info), - c2h_dbg_pfch_err_ctxt_field_info -}, -{"C2H_FIRST_ERR_QID", 0xb30, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(c2h_first_err_qid_field_info), - c2h_first_err_qid_field_info -}, -{"STAT_NUM_WRB_IN", 0xb34, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(stat_num_wrb_in_field_info), - stat_num_wrb_in_field_info -}, -{"STAT_NUM_WRB_OUT", 0xb38, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(stat_num_wrb_out_field_info), - stat_num_wrb_out_field_info -}, -{"STAT_NUM_WRB_DRP", 0xb3c, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(stat_num_wrb_drp_field_info), - stat_num_wrb_drp_field_info -}, -{"STAT_NUM_STAT_DESC_OUT", 0xb40, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(stat_num_stat_desc_out_field_info), - stat_num_stat_desc_out_field_info -}, -{"STAT_NUM_DSC_CRDT_SENT", 0xb44, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(stat_num_dsc_crdt_sent_field_info), - stat_num_dsc_crdt_sent_field_info -}, -{"STAT_NUM_FCH_DSC_RCVD", 0xb48, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(stat_num_fch_dsc_rcvd_field_info), - stat_num_fch_dsc_rcvd_field_info -}, -{"STAT_NUM_BYP_DSC_RCVD", 0xb4c, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(stat_num_byp_dsc_rcvd_field_info), - stat_num_byp_dsc_rcvd_field_info -}, -{"C2H_WRB_COAL_CFG", 0xb50, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_wrb_coal_cfg_field_info), - c2h_wrb_coal_cfg_field_info -}, -{"C2H_INTR_H2C_REQ", 0xb54, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(c2h_intr_h2c_req_field_info), - c2h_intr_h2c_req_field_info -}, -{"C2H_INTR_C2H_MM_REQ", 0xb58, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(c2h_intr_c2h_mm_req_field_info), - c2h_intr_c2h_mm_req_field_info -}, -{"C2H_INTR_ERR_INT_REQ", 0xb5c, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(c2h_intr_err_int_req_field_info), - c2h_intr_err_int_req_field_info -}, -{"C2H_INTR_C2H_ST_REQ", 0xb60, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(c2h_intr_c2h_st_req_field_info), - c2h_intr_c2h_st_req_field_info -}, -{"C2H_INTR_H2C_ERR_C2H_MM_MSIX_ACK", 0xb64, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_intr_h2c_err_c2h_mm_msix_ack_field_info), - c2h_intr_h2c_err_c2h_mm_msix_ack_field_info -}, -{"C2H_INTR_H2C_ERR_C2H_MM_MSIX_FAIL", 0xb68, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_intr_h2c_err_c2h_mm_msix_fail_field_info), - c2h_intr_h2c_err_c2h_mm_msix_fail_field_info -}, -{"C2H_INTR_H2C_ERR_C2H_MM_MSIX_NO_MSIX", 0xb6c, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_intr_h2c_err_c2h_mm_msix_no_msix_field_info), - c2h_intr_h2c_err_c2h_mm_msix_no_msix_field_info -}, -{"C2H_INTR_H2C_ERR_C2H_MM_CTXT_INVAL", 0xb70, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_intr_h2c_err_c2h_mm_ctxt_inval_field_info), - c2h_intr_h2c_err_c2h_mm_ctxt_inval_field_info -}, -{"C2H_INTR_C2H_ST_MSIX_ACK", 0xb74, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(c2h_intr_c2h_st_msix_ack_field_info), - c2h_intr_c2h_st_msix_ack_field_info -}, -{"C2H_INTR_C2H_ST_MSIX_FAIL", 0xb78, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(c2h_intr_c2h_st_msix_fail_field_info), - c2h_intr_c2h_st_msix_fail_field_info -}, -{"C2H_INTR_C2H_ST_NO_MSIX", 0xb7c, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_intr_c2h_st_no_msix_field_info), - c2h_intr_c2h_st_no_msix_field_info -}, -{"C2H_INTR_C2H_ST_CTXT_INVAL", 0xb80, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_intr_c2h_st_ctxt_inval_field_info), - c2h_intr_c2h_st_ctxt_inval_field_info -}, -{"C2H_STAT_WR_CMP", 0xb84, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_stat_wr_cmp_field_info), - c2h_stat_wr_cmp_field_info -}, -{"C2H_STAT_DBG_DMA_ENG_4", 0xb88, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_stat_dbg_dma_eng_4_field_info), - c2h_stat_dbg_dma_eng_4_field_info -}, -{"C2H_STAT_DBG_DMA_ENG_5", 0xb8c, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_stat_dbg_dma_eng_5_field_info), - c2h_stat_dbg_dma_eng_5_field_info -}, -{"C2H_DBG_PFCH_QID", 0xb90, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_dbg_pfch_qid_field_info), - c2h_dbg_pfch_qid_field_info -}, -{"C2H_DBG_PFCH", 0xb94, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_dbg_pfch_field_info), - c2h_dbg_pfch_field_info -}, -{"C2H_INT_DBG", 0xb98, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_int_dbg_field_info), - c2h_int_dbg_field_info -}, -{"C2H_STAT_IMM_ACCEPTED", 0xb9c, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_stat_imm_accepted_field_info), - c2h_stat_imm_accepted_field_info -}, -{"C2H_STAT_MARKER_ACCEPTED", 0xba0, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_stat_marker_accepted_field_info), - c2h_stat_marker_accepted_field_info -}, -{"C2H_STAT_DISABLE_CMP_ACCEPTED", 0xba4, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_stat_disable_cmp_accepted_field_info), - c2h_stat_disable_cmp_accepted_field_info -}, -{"C2H_PLD_FIFO_CRDT_CNT", 0xba8, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_pld_fifo_crdt_cnt_field_info), - c2h_pld_fifo_crdt_cnt_field_info -}, -{"H2C_ERR_STAT", 0xe00, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(h2c_err_stat_field_info), - h2c_err_stat_field_info -}, -{"H2C_ERR_MASK", 0xe04, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(h2c_err_mask_field_info), - h2c_err_mask_field_info -}, -{"H2C_FIRST_ERR_QID", 0xe08, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(h2c_first_err_qid_field_info), - h2c_first_err_qid_field_info -}, -{"H2C_DBG_REG0", 0xe0c, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(h2c_dbg_reg0_field_info), - h2c_dbg_reg0_field_info -}, -{"H2C_DBG_REG1", 0xe10, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(h2c_dbg_reg1_field_info), - h2c_dbg_reg1_field_info -}, -{"H2C_DBG_REG2", 0xe14, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(h2c_dbg_reg2_field_info), - h2c_dbg_reg2_field_info -}, -{"H2C_DBG_REG3", 0xe18, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(h2c_dbg_reg3_field_info), - h2c_dbg_reg3_field_info -}, -{"H2C_DBG_REG4", 0xe1c, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(h2c_dbg_reg4_field_info), - h2c_dbg_reg4_field_info -}, -{"H2C_FATAL_ERR_EN", 0xe20, - 1, 0, 0, 0, - 0, QDMA_ST_MODE, QDMA_REG_READ_PF_VF, - ARRAY_SIZE(h2c_fatal_err_en_field_info), - h2c_fatal_err_en_field_info -}, -{"C2H_CHANNEL_CTL", 0x1004, - 1, 0, 0, 0, - 0, QDMA_MM_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_channel_ctl_field_info), - c2h_channel_ctl_field_info -}, -{"C2H_CHANNEL_CTL_1", 0x1008, - 1, 0, 0, 0, - 0, QDMA_MM_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_channel_ctl_1_field_info), - c2h_channel_ctl_1_field_info -}, -{"C2H_MM_STATUS", 0x1040, - 1, 0, 0, 0, - 0, QDMA_MM_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_mm_status_field_info), - c2h_mm_status_field_info -}, -{"C2H_CHANNEL_CMPL_DESC_CNT", 0x1048, - 1, 0, 0, 0, - 0, QDMA_MM_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_channel_cmpl_desc_cnt_field_info), - c2h_channel_cmpl_desc_cnt_field_info -}, -{"C2H_MM_ERR_CODE_ENABLE_MASK", 0x1054, - 1, 0, 0, 0, - 0, QDMA_MM_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_mm_err_code_enable_mask_field_info), - c2h_mm_err_code_enable_mask_field_info -}, -{"C2H_MM_ERR_CODE", 0x1058, - 1, 0, 0, 0, - 0, QDMA_MM_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_mm_err_code_field_info), - c2h_mm_err_code_field_info -}, -{"C2H_MM_ERR_INFO", 0x105c, - 1, 0, 0, 0, - 0, QDMA_MM_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_mm_err_info_field_info), - c2h_mm_err_info_field_info -}, -{"C2H_MM_PERF_MON_CTL", 0x10c0, - 1, 0, 0, 0, - 0, QDMA_MM_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_mm_perf_mon_ctl_field_info), - c2h_mm_perf_mon_ctl_field_info -}, -{"C2H_MM_PERF_MON_CYCLE_CNT0", 0x10c4, - 1, 0, 0, 0, - 0, QDMA_MM_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_mm_perf_mon_cycle_cnt0_field_info), - c2h_mm_perf_mon_cycle_cnt0_field_info -}, -{"C2H_MM_PERF_MON_CYCLE_CNT1", 0x10c8, - 1, 0, 0, 0, - 0, QDMA_MM_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_mm_perf_mon_cycle_cnt1_field_info), - c2h_mm_perf_mon_cycle_cnt1_field_info -}, -{"C2H_MM_PERF_MON_DATA_CNT0", 0x10cc, - 1, 0, 0, 0, - 0, QDMA_MM_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_mm_perf_mon_data_cnt0_field_info), - c2h_mm_perf_mon_data_cnt0_field_info -}, -{"C2H_MM_PERF_MON_DATA_CNT1", 0x10d0, - 1, 0, 0, 0, - 0, QDMA_MM_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_mm_perf_mon_data_cnt1_field_info), - c2h_mm_perf_mon_data_cnt1_field_info -}, -{"C2H_MM_DBG", 0x10e8, - 1, 0, 0, 0, - 0, QDMA_MM_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(c2h_mm_dbg_field_info), - c2h_mm_dbg_field_info -}, -{"H2C_CHANNEL_CTL", 0x1204, - 1, 0, 0, 0, - 0, QDMA_MM_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(h2c_channel_ctl_field_info), - h2c_channel_ctl_field_info -}, -{"H2C_CHANNEL_CTL_1", 0x1208, - 1, 0, 0, 0, - 0, QDMA_MM_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(h2c_channel_ctl_1_field_info), - h2c_channel_ctl_1_field_info -}, -{"H2C_CHANNEL_CTL_2", 0x120c, - 1, 0, 0, 0, - 0, QDMA_MM_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(h2c_channel_ctl_2_field_info), - h2c_channel_ctl_2_field_info -}, -{"H2C_MM_STATUS", 0x1240, - 1, 0, 0, 0, - 0, QDMA_MM_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(h2c_mm_status_field_info), - h2c_mm_status_field_info -}, -{"H2C_CHANNEL_CMPL_DESC_CNT", 0x1248, - 1, 0, 0, 0, - 0, QDMA_MM_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(h2c_channel_cmpl_desc_cnt_field_info), - h2c_channel_cmpl_desc_cnt_field_info -}, -{"H2C_MM_ERR_CODE_ENABLE_MASK", 0x1254, - 1, 0, 0, 0, - 0, QDMA_MM_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(h2c_mm_err_code_enable_mask_field_info), - h2c_mm_err_code_enable_mask_field_info -}, -{"H2C_MM_ERR_CODE", 0x1258, - 1, 0, 0, 0, - 0, QDMA_MM_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(h2c_mm_err_code_field_info), - h2c_mm_err_code_field_info -}, -{"H2C_MM_ERR_INFO", 0x125c, - 1, 0, 0, 0, - 0, QDMA_MM_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(h2c_mm_err_info_field_info), - h2c_mm_err_info_field_info -}, -{"H2C_MM_PERF_MON_CTL", 0x12c0, - 1, 0, 0, 0, - 0, QDMA_MM_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(h2c_mm_perf_mon_ctl_field_info), - h2c_mm_perf_mon_ctl_field_info -}, -{"H2C_MM_PERF_MON_CYCLE_CNT0", 0x12c4, - 1, 0, 0, 0, - 0, QDMA_MM_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(h2c_mm_perf_mon_cycle_cnt0_field_info), - h2c_mm_perf_mon_cycle_cnt0_field_info -}, -{"H2C_MM_PERF_MON_CYCLE_CNT1", 0x12c8, - 1, 0, 0, 0, - 0, QDMA_MM_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(h2c_mm_perf_mon_cycle_cnt1_field_info), - h2c_mm_perf_mon_cycle_cnt1_field_info -}, -{"H2C_MM_PERF_MON_DATA_CNT0", 0x12cc, - 1, 0, 0, 0, - 0, QDMA_MM_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(h2c_mm_perf_mon_data_cnt0_field_info), - h2c_mm_perf_mon_data_cnt0_field_info -}, -{"H2C_MM_PERF_MON_DATA_CNT1", 0x12d0, - 1, 0, 0, 0, - 0, QDMA_MM_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(h2c_mm_perf_mon_data_cnt1_field_info), - h2c_mm_perf_mon_data_cnt1_field_info -}, -{"H2C_MM_DBG", 0x12e8, - 1, 0, 0, 0, - 0, QDMA_MM_MODE, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(h2c_mm_dbg_field_info), - h2c_mm_dbg_field_info -}, -{"FUNC_STATUS_REG", 0x2400, - 1, 0, 0, 0, - 0, QDMA_MAILBOX, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(func_status_reg_field_info), - func_status_reg_field_info -}, -{"FUNC_CMD_REG", 0x2404, - 1, 0, 0, 0, - 0, QDMA_MAILBOX, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(func_cmd_reg_field_info), - func_cmd_reg_field_info -}, -{"FUNC_INTERRUPT_VECTOR_REG", 0x2408, - 1, 0, 0, 0, - 0, QDMA_MAILBOX, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(func_interrupt_vector_reg_field_info), - func_interrupt_vector_reg_field_info -}, -{"TARGET_FUNC_REG", 0x240c, - 1, 0, 0, 0, - 0, QDMA_MAILBOX, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(target_func_reg_field_info), - target_func_reg_field_info -}, -{"FUNC_INTERRUPT_CTL_REG", 0x2410, - 1, 0, 0, 0, - 0, QDMA_MAILBOX, QDMA_REG_READ_PF_ONLY, - ARRAY_SIZE(func_interrupt_ctl_reg_field_info), - func_interrupt_ctl_reg_field_info -}, - -}; - -uint32_t qdma_s80_hard_config_num_regs_get(void) -{ - return (sizeof(qdma_s80_hard_config_regs)/ - sizeof(qdma_s80_hard_config_regs[0])); -} - -struct xreg_info *qdma_s80_hard_config_regs_get(void) -{ - return qdma_s80_hard_config_regs; -} - diff --git a/QDMA/windows/sys/libqdma/source/qdma_access/qdma_soft_access/qdma_soft_access.c b/QDMA/windows/sys/libqdma/source/qdma_access/qdma_soft_access/qdma_soft_access.c deleted file mode 100644 index 01b389e3a..000000000 --- a/QDMA/windows/sys/libqdma/source/qdma_access/qdma_soft_access/qdma_soft_access.c +++ /dev/null @@ -1,6151 +0,0 @@ -/* - * Copyright (C) 2020 Xilinx, Inc - * - * Licensed under the Apache License, Version 2.0 (the "License"). You may - * not use this file except in compliance with the License. You may obtain - * a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - */ - - -#include "qdma_soft_access.h" -#include "qdma_soft_reg.h" -#include "qdma_reg_dump.h" - - -#ifdef ENABLE_WPP_TRACING -#include "qdma_soft_access.tmh" -#endif - -/** QDMA Context array size */ -#define QDMA_FMAP_NUM_WORDS 2 -#define QDMA_SW_CONTEXT_NUM_WORDS 5 -#define QDMA_PFETCH_CONTEXT_NUM_WORDS 2 -#define QDMA_CMPT_CONTEXT_NUM_WORDS 5 -#define QDMA_HW_CONTEXT_NUM_WORDS 2 -#define QDMA_CR_CONTEXT_NUM_WORDS 1 -#define QDMA_IND_INTR_CONTEXT_NUM_WORDS 3 -#define QDMA_REG_IND_CTXT_REG_COUNT 8 - - -#define QDMA_REG_GROUP_1_START_ADDR 0x000 -#define QDMA_REG_GROUP_2_START_ADDR 0x400 -#define QDMA_REG_GROUP_3_START_ADDR 0xB00 -#define QDMA_REG_GROUP_4_START_ADDR 0x1014 - -static void qdma_hw_st_h2c_err_process(void *dev_hndl); -static void qdma_hw_st_c2h_err_process(void *dev_hndl); -static void qdma_hw_desc_err_process(void *dev_hndl); -static void qdma_hw_trq_err_process(void *dev_hndl); -static void qdma_hw_ram_sbe_err_process(void *dev_hndl); -static void qdma_hw_ram_dbe_err_process(void *dev_hndl); - -static struct xreg_info qdma_config_regs[] = { - - /* QDMA_TRQ_SEL_GLBL1 (0x00000) */ - {"CFG_BLOCK_ID", - 0x00, 1, 0, 0, 0, 0, - QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, 0, NULL}, - {"CFG_BUSDEV", - 0x04, 1, 0, 0, 0, 0, - QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, 0, NULL}, - {"CFG_PCIE_MAX_PL_SZ", - 0x08, 1, 0, 0, 0, 0, - QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, 0, NULL}, - {"CFG_PCIE_MAX_RDRQ_SZ", - 0x0C, 1, 0, 0, 0, 0, - QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, 0, NULL}, - {"CFG_SYS_ID", - 0x10, 1, 0, 0, 0, 0, - QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, 0, NULL}, - {"CFG_MSI_EN", - 0x14, 1, 0, 0, 0, 0, - QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, 0, NULL}, - {"CFG_PCIE_DATA_WIDTH", - 0x18, 1, 0, 0, 0, 0, - QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, 0, NULL}, - {"CFG_PCIE_CTRL", - 0x1C, 1, 0, 0, 0, 0, - QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, 0, NULL}, - {"CFG_AXI_USR_MAX_PL_SZ", - 0x40, 1, 0, 0, 0, 0, - QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, 0, NULL}, - {"CFG_AXI_USR_MAX_RDRQ_SZ", - 0x44, 1, 0, 0, 0, 0, - QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, 0, NULL}, - {"CFG_MISC_CTRL", - 0x4C, 1, 0, 0, 0, 0, - QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, 0, NULL}, - {"CFG_SCRATCH_REG", - 0x80, 8, 0, 0, 0, 0, - QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, 0, NULL}, - {"QDMA_RAM_SBE_MSK_A", - 0xF0, 1, 0, 0, 0, 0, - QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, 0, NULL}, - {"QDMA_RAM_SBE_STS_A", - 0xF4, 1, 0, 0, 0, 0, - QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, 0, NULL}, - {"QDMA_RAM_DBE_MSK_A", - 0xF8, 1, 0, 0, 0, 0, - QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, 0, NULL}, - {"QDMA_RAM_DBE_STS_A", - 0xFC, 1, 0, 0, 0, 0, - QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, 0, NULL}, - - /* QDMA_TRQ_SEL_GLBL2 (0x00100) */ - {"GLBL2_ID", - 0x100, 1, 0, 0, 0, 0, - QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, 0, NULL}, - {"GLBL2_PF_BL_INT", - 0x104, 1, 0, 0, 0, 0, - QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, 0, NULL}, - {"GLBL2_PF_VF_BL_INT", - 0x108, 1, 0, 0, 0, 0, - QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, 0, NULL}, - {"GLBL2_PF_BL_EXT", - 0x10C, 1, 0, 0, 0, 0, - QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, 0, NULL}, - {"GLBL2_PF_VF_BL_EXT", - 0x110, 1, 0, 0, 0, 0, - QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, 0, NULL}, - {"GLBL2_CHNL_INST", - 0x114, 1, 0, 0, 0, 0, - QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, 0, NULL}, - {"GLBL2_CHNL_QDMA", - 0x118, 1, 0, 0, 0, 0, - QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, 0, NULL}, - {"GLBL2_CHNL_STRM", - 0x11C, 1, 0, 0, 0, 0, - QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, 0, NULL}, - {"GLBL2_QDMA_CAP", - 0x120, 1, 0, 0, 0, 0, - QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, 0, NULL}, - {"GLBL2_PASID_CAP", - 0x128, 1, 0, 0, 0, 0, - QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, 0, NULL}, - {"GLBL2_FUNC_RET", - 0x12C, 1, 0, 0, 0, 0, - QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, 0, NULL}, - {"GLBL2_SYS_ID", - 0x130, 1, 0, 0, 0, 0, - QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, 0, NULL}, - {"GLBL2_MISC_CAP", - 0x134, 1, 0, 0, 0, 0, - QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, 0, NULL}, - {"GLBL2_DBG_PCIE_RQ", - 0x1B8, 2, 0, 0, 0, 0, - QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, 0, NULL}, - {"GLBL2_DBG_AXIMM_WR", - 0x1C0, 2, 0, 0, 0, 0, - QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, 0, NULL}, - {"GLBL2_DBG_AXIMM_RD", - 0x1C8, 2, 0, 0, 0, 0, - QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, 0, NULL}, - - /* QDMA_TRQ_SEL_GLBL (0x00200) */ - {"GLBL_RNGSZ", - 0x204, 16, 1, 0, 0, 0, - QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, 0, NULL}, - {"GLBL_ERR_STAT", - 0x248, 1, 0, 0, 0, 0, - QDMA_MM_ST_MODE, QDMA_REG_READ_PF_VF, 0, NULL}, - {"GLBL_ERR_MASK", - 0x24C, 1, 0, 0, 0, 0, - QDMA_MM_ST_MODE, QDMA_REG_READ_PF_VF, 0, NULL}, - {"GLBL_DSC_CFG", - 0x250, 1, 0, 0, 0, 0, - QDMA_MM_ST_MODE, QDMA_REG_READ_PF_VF, 0, NULL}, - {"GLBL_DSC_ERR_STS", - 0x254, 1, 0, 0, 0, 0, - QDMA_MM_ST_MODE, QDMA_REG_READ_PF_VF, 0, NULL}, - {"GLBL_DSC_ERR_MSK", - 0x258, 1, 0, 0, 0, 0, - QDMA_MM_ST_MODE, QDMA_REG_READ_PF_VF, 0, NULL}, - {"GLBL_DSC_ERR_LOG", - 0x25C, 2, 0, 0, 0, 0, - QDMA_MM_ST_MODE, QDMA_REG_READ_PF_VF, 0, NULL}, - {"GLBL_TRQ_ERR_STS", - 0x264, 1, 0, 0, 0, 0, - QDMA_MM_ST_MODE, QDMA_REG_READ_PF_VF, 0, NULL}, - {"GLBL_TRQ_ERR_MSK", - 0x268, 1, 0, 0, 0, 0, - QDMA_MM_ST_MODE, QDMA_REG_READ_PF_VF, 0, NULL}, - {"GLBL_TRQ_ERR_LOG", - 0x26C, 1, 0, 0, 0, 0, - QDMA_MM_ST_MODE, QDMA_REG_READ_PF_VF, 0, NULL}, - {"GLBL_DSC_DBG_DAT", - 0x270, 2, 0, 0, 0, 0, - QDMA_MM_ST_MODE, QDMA_REG_READ_PF_VF, 0, NULL}, - {"GLBL_DSC_ERR_LOG2", - 0x27C, 1, 0, 0, 0, 0, - QDMA_MM_ST_MODE, QDMA_REG_READ_PF_VF, 0, NULL}, - {"GLBL_INTERRUPT_CFG", - 0x288, 1, 0, 0, 0, 0, - QDMA_MM_ST_MODE, QDMA_REG_READ_PF_VF, 0, NULL}, - - /* QDMA_TRQ_SEL_FMAP (0x00400 - 0x7FC) */ - /* TODO: max 256, display 4 for now */ - {"TRQ_SEL_FMAP", - 0x400, 4, 0, 0, 0, 0, - QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, 0, NULL}, - - /* QDMA_TRQ_SEL_IND (0x00800) */ - {"IND_CTXT_DATA", - 0x804, 8, 0, 0, 0, 0, - QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, 0, NULL}, - {"IND_CTXT_MASK", - 0x824, 8, 0, 0, 0, 0, - QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, 0, NULL}, - {"IND_CTXT_CMD", - 0x844, 1, 0, 0, 0, 0, - QDMA_MM_ST_MODE, QDMA_REG_READ_PF_ONLY, 0, NULL}, - - /* QDMA_TRQ_SEL_C2H (0x00A00) */ - {"C2H_TIMER_CNT", - 0xA00, 16, 0, 0, 0, 0, - QDMA_COMPLETION_MODE, QDMA_REG_READ_PF_ONLY, 0, NULL}, - {"C2H_CNT_THRESH", - 0xA40, 16, 0, 0, 0, 0, - QDMA_COMPLETION_MODE, QDMA_REG_READ_PF_ONLY, 0, NULL}, - {"C2H_STAT_S_AXIS_C2H_ACCEPTED", - 0xA88, 1, 0, 0, 0, 0, - QDMA_ST_MODE, QDMA_REG_READ_PF_VF, 0, NULL}, - {"C2H_STAT_S_AXIS_CMPT_ACCEPTED", - 0xA8C, 1, 0, 0, 0, 0, - QDMA_ST_MODE, QDMA_REG_READ_PF_VF, 0, NULL}, - {"C2H_STAT_DESC_RSP_PKT_ACCEPTED", - 0xA90, 1, 0, 0, 0, 0, - QDMA_ST_MODE, QDMA_REG_READ_PF_VF, 0, NULL}, - {"C2H_STAT_AXIS_PKG_CMP", - 0xA94, 1, 0, 0, 0, 0, - QDMA_ST_MODE, QDMA_REG_READ_PF_VF, 0, NULL}, - {"C2H_STAT_DESC_RSP_ACCEPTED", - 0xA98, 1, 0, 0, 0, 0, - QDMA_ST_MODE, QDMA_REG_READ_PF_VF, 0, NULL}, - {"C2H_STAT_DESC_RSP_CMP", - 0xA9C, 1, 0, 0, 0, 0, - QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, 0, NULL}, - {"C2H_STAT_WRQ_OUT", - 0xAA0, 1, 0, 0, 0, 0, - QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, 0, NULL}, - {"C2H_STAT_WPL_REN_ACCEPTED", - 0xAA4, 1, 0, 0, 0, 0, - QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, 0, NULL}, - {"C2H_STAT_TOTAL_WRQ_LEN", - 0xAA8, 1, 0, 0, 0, 0, - QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, 0, NULL}, - {"C2H_STAT_TOTAL_WPL_LEN", - 0xAAC, 1, 0, 0, 0, 0, - QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, 0, NULL}, - {"C2H_BUF_SZ", - 0xAB0, 16, 0, 0, 0, 0, - QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, 0, NULL}, - {"C2H_ERR_STAT", - 0xAF0, 1, 0, 0, 0, 0, - QDMA_ST_MODE, QDMA_REG_READ_PF_VF, 0, NULL}, - {"C2H_ERR_MASK", - 0xAF4, 1, 0, 0, 0, 0, - QDMA_ST_MODE, QDMA_REG_READ_PF_VF, 0, NULL}, - {"C2H_FATAL_ERR_STAT", - 0xAF8, 1, 0, 0, 0, 0, - QDMA_ST_MODE, QDMA_REG_READ_PF_VF, 0, NULL}, - {"C2H_FATAL_ERR_MASK", - 0xAFC, 1, 0, 0, 0, 0, - QDMA_ST_MODE, QDMA_REG_READ_PF_VF, 0, NULL}, - {"C2H_FATAL_ERR_ENABLE", - 0xB00, 1, 0, 0, 0, 0, - QDMA_ST_MODE, QDMA_REG_READ_PF_VF, 0, NULL}, - {"GLBL_ERR_INT", - 0xB04, 1, 0, 0, 0, 0, - QDMA_ST_MODE, QDMA_REG_READ_PF_VF, 0, NULL}, - {"C2H_PFCH_CFG", - 0xB08, 1, 0, 0, 0, 0, - QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, 0, NULL}, - {"C2H_INT_TIMER_TICK", - 0xB0C, 1, 0, 0, 0, 0, - QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, 0, NULL}, - {"C2H_STAT_DESC_RSP_DROP_ACCEPTED", - 0xB10, 1, 0, 0, 0, 0, - QDMA_ST_MODE, QDMA_REG_READ_PF_VF, 0, NULL}, - {"C2H_STAT_DESC_RSP_ERR_ACCEPTED", - 0xB14, 1, 0, 0, 0, 0, - QDMA_ST_MODE, QDMA_REG_READ_PF_VF, 0, NULL}, - {"C2H_STAT_DESC_REQ", - 0xB18, 1, 0, 0, 0, 0, - QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, 0, NULL}, - {"C2H_STAT_DEBUG_DMA_ENG", - 0xB1C, 4, 0, 0, 0, 0, - QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, 0, NULL}, - {"C2H_DBG_PFCH_ERR_CTXT", - 0xB2C, 1, 0, 0, 0, 0, - QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, 0, NULL}, - {"C2H_FIRST_ERR_QID", - 0xB30, 1, 0, 0, 0, 0, - QDMA_ST_MODE, QDMA_REG_READ_PF_VF, 0, NULL}, - {"STAT_NUM_CMPT_IN", - 0xB34, 1, 0, 0, 0, 0, - QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, 0, NULL}, - {"STAT_NUM_CMPT_OUT", - 0xB38, 1, 0, 0, 0, 0, - QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, 0, NULL}, - {"STAT_NUM_CMPT_DRP", - 0xB3C, 1, 0, 0, 0, 0, - QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, 0, NULL}, - {"STAT_NUM_STAT_DESC_OUT", - 0xB40, 1, 0, 0, 0, 0, - QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, 0, NULL}, - {"STAT_NUM_DSC_CRDT_SENT", - 0xB44, 1, 0, 0, 0, 0, - QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, 0, NULL}, - {"STAT_NUM_FCH_DSC_RCVD", - 0xB48, 1, 0, 0, 0, 0, - QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, 0, NULL}, - {"STAT_NUM_BYP_DSC_RCVD", - 0xB4C, 1, 0, 0, 0, 0, - QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, 0, NULL}, - {"C2H_CMPT_COAL_CFG", - 0xB50, 1, 0, 0, 0, 0, - QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, 0, NULL}, - {"C2H_INTR_H2C_REQ", - 0xB54, 1, 0, 0, 0, 0, - QDMA_ST_MODE, QDMA_REG_READ_PF_VF, 0, NULL}, - {"C2H_INTR_C2H_MM_REQ", - 0xB58, 1, 0, 0, 0, 0, - QDMA_ST_MODE, QDMA_REG_READ_PF_VF, 0, NULL}, - {"C2H_INTR_ERR_INT_REQ", - 0xB5C, 1, 0, 0, 0, 0, - QDMA_ST_MODE, QDMA_REG_READ_PF_VF, 0, NULL}, - {"C2H_INTR_C2H_ST_REQ", - 0xB60, 1, 0, 0, 0, 0, - QDMA_ST_MODE, QDMA_REG_READ_PF_VF, 0, NULL}, - {"C2H_INTR_H2C_ERR_MM_MSIX_ACK", - 0xB64, 1, 0, 0, 0, 0, - QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, 0, NULL}, - {"C2H_INTR_H2C_ERR_MM_MSIX_FAIL", - 0xB68, 1, 0, 0, 0, 0, - QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, 0, NULL}, - {"C2H_INTR_H2C_ERR_MM_NO_MSIX", - 0xB6C, 1, 0, 0, 0, 0, - QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, 0, NULL}, - {"C2H_INTR_H2C_ERR_MM_CTXT_INVAL", - 0xB70, 1, 0, 0, 0, 0, - QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, 0, NULL}, - {"C2H_INTR_C2H_ST_MSIX_ACK", - 0xB74, 1, 0, 0, 0, 0, - QDMA_ST_MODE, QDMA_REG_READ_PF_VF, 0, NULL}, - {"C2H_INTR_C2H_ST_MSIX_FAIL", - 0xB78, 1, 0, 0, 0, 0, - QDMA_ST_MODE, QDMA_REG_READ_PF_VF, 0, NULL}, - {"C2H_INTR_C2H_ST_NO_MSIX", - 0xB7C, 1, 0, 0, 0, 0, - QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, 0, NULL}, - {"C2H_INTR_C2H_ST_CTXT_INVAL", - 0xB80, 1, 0, 0, 0, 0, - QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, 0, NULL}, - {"C2H_STAT_WR_CMP", - 0xB84, 1, 0, 0, 0, 0, - QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, 0, NULL}, - {"C2H_STAT_DEBUG_DMA_ENG_4", - 0xB88, 1, 0, 0, 0, 0, - QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, 0, NULL}, - {"C2H_STAT_DEBUG_DMA_ENG_5", - 0xB8C, 1, 0, 0, 0, 0, - QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, 0, NULL}, - {"C2H_DBG_PFCH_QID", - 0xB90, 1, 0, 0, 0, 0, - QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, 0, NULL}, - {"C2H_DBG_PFCH", - 0xB94, 1, 0, 0, 0, 0, - QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, 0, NULL}, - {"C2H_INT_DEBUG", - 0xB98, 1, 0, 0, 0, 0, - QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, 0, NULL}, - {"C2H_STAT_IMM_ACCEPTED", - 0xB9C, 1, 0, 0, 0, 0, - QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, 0, NULL}, - {"C2H_STAT_MARKER_ACCEPTED", - 0xBA0, 1, 0, 0, 0, 0, - QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, 0, NULL}, - {"C2H_STAT_DISABLE_CMP_ACCEPTED", - 0xBA4, 1, 0, 0, 0, 0, - QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, 0, NULL}, - {"C2H_C2H_PAYLOAD_FIFO_CRDT_CNT", - 0xBA8, 1, 0, 0, 0, 0, - QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, 0, NULL}, - {"C2H_INTR_DYN_REQ", - 0xBAC, 1, 0, 0, 0, 0, - QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, 0, NULL}, - {"C2H_INTR_DYN_MSIX", - 0xBB0, 1, 0, 0, 0, 0, - QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, 0, NULL}, - {"C2H_DROP_LEN_MISMATCH", - 0xBB4, 1, 0, 0, 0, 0, - QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, 0, NULL}, - {"C2H_DROP_DESC_RSP_LEN", - 0xBB8, 1, 0, 0, 0, 0, - QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, 0, NULL}, - {"C2H_DROP_QID_FIFO_LEN", - 0xBBC, 1, 0, 0, 0, 0, - QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, 0, NULL}, - {"C2H_DROP_PAYLOAD_CNT", - 0xBC0, 1, 0, 0, 0, 0, - QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, 0, NULL}, - {"QDMA_C2H_CMPT_FORMAT", - 0xBC4, 7, 0, 0, 0, 0, - QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, 0, NULL}, - {"C2H_PFCH_CACHE_DEPTH", - 0xBE0, 1, 0, 0, 0, 0, - QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, 0, NULL}, - {"C2H_CMPT_COAL_BUF_DEPTH", - 0xBE4, 1, 0, 0, 0, 0, - QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, 0, NULL}, - {"C2H_PFCH_CRDT", - 0xBE8, 1, 0, 0, 0, 0, - QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, 0, NULL}, - - /* QDMA_TRQ_SEL_H2C(0x00E00) Register Space*/ - {"H2C_ERR_STAT", - 0xE00, 1, 0, 0, 0, 0, - QDMA_ST_MODE, QDMA_REG_READ_PF_VF, 0, NULL}, - {"H2C_ERR_MASK", - 0xE04, 1, 0, 0, 0, 0, - QDMA_ST_MODE, QDMA_REG_READ_PF_VF, 0, NULL}, - {"H2C_FIRST_ERR_QID", - 0xE08, 1, 0, 0, 0, 0, - QDMA_ST_MODE, QDMA_REG_READ_PF_VF, 0, NULL}, - {"H2C_DBG_REG", - 0xE0C, 5, 0, 0, 0, 0, - QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, 0, NULL}, - {"H2C_FATAL_ERR_EN", - 0xE20, 1, 0, 0, 0, 0, - QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, 0, NULL}, - {"H2C_REQ_THROT", - 0xE24, 1, 0, 0, 0, 0, - QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, 0, NULL}, - {"H2C_ALN_DBG_REG0", - 0xE28, 1, 0, 0, 0, 0, - QDMA_ST_MODE, QDMA_REG_READ_PF_ONLY, 0, NULL}, - - /* QDMA_TRQ_SEL_C2H_MM (0x1000) */ - {"C2H_MM_CONTROL", - 0x1004, 3, 0, 0, 0, 0, - QDMA_MM_MODE, QDMA_REG_READ_PF_ONLY, 0, NULL}, - {"C2H_MM_STATUS", - 0x1040, 2, 0, 0, 0, 0, - QDMA_MM_MODE, QDMA_REG_READ_PF_ONLY, 0, NULL}, - {"C2H_MM_CMPL_DSC_CNT", - 0x1048, 1, 0, 0, 0, 0, - QDMA_MM_MODE, QDMA_REG_READ_PF_ONLY, 0, NULL}, - {"C2H_MM_ERR_CODE_EN_MASK", - 0x1054, 1, 0, 0, 0, 0, - QDMA_MM_MODE, QDMA_REG_READ_PF_ONLY, 0, NULL}, - {"C2H_MM_ERR_CODE", - 0x1058, 1, 0, 0, 0, 0, - QDMA_MM_MODE, QDMA_REG_READ_PF_ONLY, 0, NULL}, - {"C2H_MM_ERR_INFO", - 0x105C, 1, 0, 0, 0, 0, - QDMA_MM_MODE, QDMA_REG_READ_PF_ONLY, 0, NULL}, - {"C2H_MM_PERF_MON_CTRL", - 0x10C0, 1, 0, 0, 0, 0, - QDMA_MM_MODE, QDMA_REG_READ_PF_ONLY, 0, NULL}, - {"C2H_MM_PERF_MON_CY_CNT", - 0x10C4, 2, 0, 0, 0, 0, - QDMA_MM_MODE, QDMA_REG_READ_PF_ONLY, 0, NULL}, - {"C2H_MM_PERF_MON_DATA_CNT", - 0x10CC, 2, 0, 0, 0, 0, - QDMA_MM_MODE, QDMA_REG_READ_PF_ONLY, 0, NULL}, - {"C2H_MM_DBG_INFO", - 0x10E8, 2, 0, 0, 0, 0, - QDMA_MM_MODE, QDMA_REG_READ_PF_ONLY, 0, NULL}, - - /* QDMA_TRQ_SEL_H2C_MM (0x1200)*/ - {"H2C_MM_CONTROL", - 0x1204, 3, 0, 0, 0, 0, - QDMA_MM_MODE, QDMA_REG_READ_PF_ONLY, 0, NULL}, - {"H2C_MM_STATUS", - 0x1240, 1, 0, 0, 0, 0, - QDMA_MM_MODE, QDMA_REG_READ_PF_ONLY, 0, NULL}, - {"H2C_MM_CMPL_DSC_CNT", - 0x1248, 1, 0, 0, 0, 0, - QDMA_MM_MODE, QDMA_REG_READ_PF_ONLY, 0, NULL}, - {"H2C_MM_ERR_CODE_EN_MASK", - 0x1254, 1, 0, 0, 0, 0, - QDMA_MM_MODE, QDMA_REG_READ_PF_ONLY, 0, NULL}, - {"H2C_MM_ERR_CODE", - 0x1258, 1, 0, 0, 0, 0, - QDMA_MM_MODE, QDMA_REG_READ_PF_ONLY, 0, NULL}, - {"H2C_MM_ERR_INFO", - 0x125C, 1, 0, 0, 0, 0, - QDMA_MM_MODE, QDMA_REG_READ_PF_ONLY, 0, NULL}, - {"H2C_MM_PERF_MON_CTRL", - 0x12C0, 1, 0, 0, 0, 0, - QDMA_MM_MODE, QDMA_REG_READ_PF_ONLY, 0, NULL}, - {"H2C_MM_PERF_MON_CY_CNT", - 0x12C4, 2, 0, 0, 0, 0, - QDMA_MM_MODE, QDMA_REG_READ_PF_ONLY, 0, NULL}, - {"H2C_MM_PERF_MON_DATA_CNT", - 0x12CC, 2, 0, 0, 0, 0, - QDMA_MM_MODE, QDMA_REG_READ_PF_ONLY, 0, NULL}, - {"H2C_MM_DBG_INFO", - 0x12E8, 1, 0, 0, 0, 0, - QDMA_MM_MODE, QDMA_REG_READ_PF_ONLY, 0, NULL}, - {"H2C_MM_REQ_THROT", - 0x12EC, 1, 0, 0, 0, 0, - QDMA_MM_MODE, QDMA_REG_READ_PF_ONLY, 0, NULL}, - - /* QDMA_PF_MAILBOX (0x2400) */ - {"FUNC_STATUS", - 0x2400, 1, 0, 0, 0, 0, - QDMA_MAILBOX, QDMA_REG_READ_PF_ONLY, 0, NULL}, - {"FUNC_CMD", - 0x2404, 1, 0, 0, 0, 0, - QDMA_MAILBOX, QDMA_REG_READ_PF_ONLY, 0, NULL}, - {"FUNC_INTR_VEC", - 0x2408, 1, 0, 0, 0, 0, - QDMA_MAILBOX, QDMA_REG_READ_PF_ONLY, 0, NULL}, - {"TARGET_FUNC", - 0x240C, 1, 0, 0, 0, 0, - QDMA_MAILBOX, QDMA_REG_READ_PF_ONLY, 0, NULL}, - {"INTR_CTRL", - 0x2410, 1, 0, 0, 0, 0, - QDMA_MAILBOX, QDMA_REG_READ_PF_ONLY, 0, NULL}, - {"PF_ACK", - 0x2420, 8, 0, 0, 0, 0, - QDMA_MAILBOX, QDMA_REG_READ_PF_ONLY, 0, NULL}, - {"FLR_CTRL_STATUS", - 0x2500, 1, 0, 0, 0, 0, - QDMA_MAILBOX, QDMA_REG_READ_PF_ONLY, 0, NULL}, - {"MSG_IN", - 0x2800, 32, 0, 0, 0, 0, - QDMA_MAILBOX, QDMA_REG_READ_PF_ONLY, 0, NULL}, - {"MSG_OUT", - 0x2C00, 32, 0, 0, 0, 0, - QDMA_MAILBOX, QDMA_REG_READ_PF_ONLY, 0, NULL}, - - {"", 0, 0, 0, 0, 0, 0, 0, 0, 0, NULL } -}; - - -static struct qdma_hw_err_info qdma_err_info[QDMA_ERRS_ALL] = { - /* Descriptor errors */ - { - QDMA_DSC_ERR_POISON, - "Poison error", - QDMA_OFFSET_GLBL_DSC_ERR_MASK, - QDMA_OFFSET_GLBL_DSC_ERR_STAT, - QDMA_GLBL_DSC_ERR_POISON_MASK, - QDMA_GLBL_ERR_DSC_MASK, - &qdma_hw_desc_err_process - }, - { - QDMA_DSC_ERR_UR_CA, - "Unsupported request or completer aborted error", - QDMA_OFFSET_GLBL_DSC_ERR_MASK, - QDMA_OFFSET_GLBL_DSC_ERR_STAT, - QDMA_GLBL_DSC_ERR_UR_CA_MASK, - QDMA_GLBL_ERR_DSC_MASK, - &qdma_hw_desc_err_process - }, - { - QDMA_DSC_ERR_PARAM, - "Parameter mismatch error", - QDMA_OFFSET_GLBL_DSC_ERR_MASK, - QDMA_OFFSET_GLBL_DSC_ERR_STAT, - QDMA_GLBL_DSC_ERR_PARAM_MASK, - QDMA_GLBL_ERR_DSC_MASK, - &qdma_hw_desc_err_process - }, - { - QDMA_DSC_ERR_ADDR, - "Address mismatch error", - QDMA_OFFSET_GLBL_DSC_ERR_MASK, - QDMA_OFFSET_GLBL_DSC_ERR_STAT, - QDMA_GLBL_DSC_ERR_ADDR_MASK, - QDMA_GLBL_ERR_DSC_MASK, - &qdma_hw_desc_err_process - }, - { - QDMA_DSC_ERR_TAG, - "Unexpected tag error", - QDMA_OFFSET_GLBL_DSC_ERR_MASK, - QDMA_OFFSET_GLBL_DSC_ERR_STAT, - QDMA_GLBL_DSC_ERR_TAG_MASK, - QDMA_GLBL_ERR_DSC_MASK, - &qdma_hw_desc_err_process - }, - { - QDMA_DSC_ERR_FLR, - "FLR error", - QDMA_OFFSET_GLBL_DSC_ERR_MASK, - QDMA_OFFSET_GLBL_DSC_ERR_STAT, - QDMA_GLBL_DSC_ERR_FLR_MASK, - QDMA_GLBL_ERR_DSC_MASK, - &qdma_hw_desc_err_process - }, - { - QDMA_DSC_ERR_TIMEOUT, - "Timed out error", - QDMA_OFFSET_GLBL_DSC_ERR_MASK, - QDMA_OFFSET_GLBL_DSC_ERR_STAT, - QDMA_GLBL_DSC_ERR_TIMEOUT_MASK, - QDMA_GLBL_ERR_DSC_MASK, - &qdma_hw_desc_err_process - }, - { - QDMA_DSC_ERR_DAT_POISON, - "Poison data error", - QDMA_OFFSET_GLBL_DSC_ERR_MASK, - QDMA_OFFSET_GLBL_DSC_ERR_STAT, - QDMA_GLBL_DSC_ERR_DAT_POISON_MASK, - QDMA_GLBL_ERR_DSC_MASK, - &qdma_hw_desc_err_process - }, - { - QDMA_DSC_ERR_FLR_CANCEL, - "Descriptor fetch cancelled due to FLR error", - QDMA_OFFSET_GLBL_DSC_ERR_MASK, - QDMA_OFFSET_GLBL_DSC_ERR_STAT, - QDMA_GLBL_DSC_ERR_FLR_CANCEL_MASK, - QDMA_GLBL_ERR_DSC_MASK, - &qdma_hw_desc_err_process - }, - { - QDMA_DSC_ERR_DMA, - "DMA engine error", - QDMA_OFFSET_GLBL_DSC_ERR_MASK, - QDMA_OFFSET_GLBL_DSC_ERR_STAT, - QDMA_GLBL_DSC_ERR_DMA_MASK, - QDMA_GLBL_ERR_DSC_MASK, - &qdma_hw_desc_err_process - }, - { - QDMA_DSC_ERR_DSC, - "Invalid PIDX update error", - QDMA_OFFSET_GLBL_DSC_ERR_MASK, - QDMA_OFFSET_GLBL_DSC_ERR_STAT, - QDMA_GLBL_DSC_ERR_DSC_MASK, - QDMA_GLBL_ERR_DSC_MASK, - &qdma_hw_desc_err_process - }, - { - QDMA_DSC_ERR_RQ_CANCEL, - "Descriptor fetch cancelled due to disable register status error", - QDMA_OFFSET_GLBL_DSC_ERR_MASK, - QDMA_OFFSET_GLBL_DSC_ERR_STAT, - QDMA_GLBL_DSC_ERR_RQ_CANCEL_MASK, - QDMA_GLBL_ERR_DSC_MASK, - &qdma_hw_desc_err_process - }, - { - QDMA_DSC_ERR_DBE, - "UNC_ERR_RAM_DBE error", - QDMA_OFFSET_GLBL_DSC_ERR_MASK, - QDMA_OFFSET_GLBL_DSC_ERR_STAT, - QDMA_GLBL_DSC_ERR_DBE_MASK, - QDMA_GLBL_ERR_DSC_MASK, - &qdma_hw_desc_err_process - }, - { - QDMA_DSC_ERR_SBE, - "UNC_ERR_RAM_SBE error", - QDMA_OFFSET_GLBL_DSC_ERR_MASK, - QDMA_OFFSET_GLBL_DSC_ERR_STAT, - QDMA_GLBL_DSC_ERR_SBE_MASK, - QDMA_GLBL_ERR_DSC_MASK, - &qdma_hw_desc_err_process - }, - { - QDMA_DSC_ERR_ALL, - "All Descriptor errors", - QDMA_OFFSET_GLBL_DSC_ERR_MASK, - QDMA_OFFSET_GLBL_DSC_ERR_STAT, - QDMA_GLBL_DSC_ERR_ALL_MASK, - QDMA_GLBL_ERR_DSC_MASK, - &qdma_hw_desc_err_process - }, - - /* TRQ errors */ - { - QDMA_TRQ_ERR_UNMAPPED, - "Access targeted unmapped register space error", - QDMA_OFFSET_GLBL_TRQ_ERR_MASK, - QDMA_OFFSET_GLBL_TRQ_ERR_STAT, - QDMA_GLBL_TRQ_ERR_UNMAPPED_MASK, - QDMA_GLBL_ERR_TRQ_MASK, - &qdma_hw_trq_err_process - }, - { - QDMA_TRQ_ERR_QID_RANGE, - "Qid range error", - QDMA_OFFSET_GLBL_TRQ_ERR_MASK, - QDMA_OFFSET_GLBL_TRQ_ERR_STAT, - QDMA_GLBL_TRQ_ERR_QID_RANGE_MASK, - QDMA_GLBL_ERR_TRQ_MASK, - &qdma_hw_trq_err_process - }, - { - QDMA_TRQ_ERR_VF_ACCESS, - "Invalid VF access error", - QDMA_OFFSET_GLBL_TRQ_ERR_MASK, - QDMA_OFFSET_GLBL_TRQ_ERR_STAT, - QDMA_GLBL_TRQ_ERR_VF_ACCESS_MASK, - QDMA_GLBL_ERR_TRQ_MASK, - &qdma_hw_trq_err_process - }, - { - QDMA_TRQ_ERR_TCP_TIMEOUT, - "Timeout on request error", - QDMA_OFFSET_GLBL_TRQ_ERR_MASK, - QDMA_OFFSET_GLBL_TRQ_ERR_STAT, - QDMA_GLBL_TRQ_ERR_TCP_TIMEOUT_MASK, - QDMA_GLBL_ERR_TRQ_MASK, - &qdma_hw_trq_err_process - }, - { - QDMA_TRQ_ERR_ALL, - "All TRQ errors", - QDMA_OFFSET_GLBL_TRQ_ERR_MASK, - QDMA_OFFSET_GLBL_TRQ_ERR_STAT, - QDMA_GLBL_TRQ_ERR_ALL_MASK, - QDMA_GLBL_ERR_TRQ_MASK, - &qdma_hw_trq_err_process - }, - - /* C2H Errors*/ - { - QDMA_ST_C2H_ERR_MTY_MISMATCH, - "MTY mismatch error", - QDMA_OFFSET_C2H_ERR_MASK, - QDMA_OFFSET_C2H_ERR_STAT, - QDMA_C2H_ERR_MTY_MISMATCH_MASK, - QDMA_GLBL_ERR_ST_C2H_MASK, - &qdma_hw_st_c2h_err_process - }, - { - QDMA_ST_C2H_ERR_LEN_MISMATCH, - "Packet length mismatch error", - QDMA_OFFSET_C2H_ERR_MASK, - QDMA_OFFSET_C2H_ERR_STAT, - QDMA_C2H_ERR_LEN_MISMATCH_MASK, - QDMA_GLBL_ERR_ST_C2H_MASK, - &qdma_hw_st_c2h_err_process - }, - { - QDMA_ST_C2H_ERR_QID_MISMATCH, - "Qid mismatch error", - QDMA_OFFSET_C2H_ERR_MASK, - QDMA_OFFSET_C2H_ERR_STAT, - QDMA_C2H_ERR_QID_MISMATCH_MASK, - QDMA_GLBL_ERR_ST_C2H_MASK, - &qdma_hw_st_c2h_err_process - }, - { - QDMA_ST_C2H_ERR_DESC_RSP_ERR, - "Descriptor error bit set", - QDMA_OFFSET_C2H_ERR_MASK, - QDMA_OFFSET_C2H_ERR_STAT, - QDMA_C2H_ERR_DESC_RSP_ERR_MASK, - QDMA_GLBL_ERR_ST_C2H_MASK, - &qdma_hw_st_c2h_err_process - }, - { - QDMA_ST_C2H_ERR_ENG_WPL_DATA_PAR_ERR, - "Data parity error", - QDMA_OFFSET_C2H_ERR_MASK, - QDMA_OFFSET_C2H_ERR_STAT, - QDMA_C2H_ERR_ENG_WPL_DATA_PAR_ERR_MASK, - QDMA_GLBL_ERR_ST_C2H_MASK, - &qdma_hw_st_c2h_err_process - }, - { - QDMA_ST_C2H_ERR_MSI_INT_FAIL, - "MSI got a fail response error", - QDMA_OFFSET_C2H_ERR_MASK, - QDMA_OFFSET_C2H_ERR_STAT, - QDMA_C2H_ERR_MSI_INT_FAIL_MASK, - QDMA_GLBL_ERR_ST_C2H_MASK, - &qdma_hw_st_c2h_err_process - }, - { - QDMA_ST_C2H_ERR_ERR_DESC_CNT, - "Descriptor count error", - QDMA_OFFSET_C2H_ERR_MASK, - QDMA_OFFSET_C2H_ERR_STAT, - QDMA_C2H_ERR_ERR_DESC_CNT_MASK, - QDMA_GLBL_ERR_ST_C2H_MASK, - &qdma_hw_st_c2h_err_process - }, - { - QDMA_ST_C2H_ERR_PORTID_CTXT_MISMATCH, - "Port id in packet and pfetch ctxt mismatch error", - QDMA_OFFSET_C2H_ERR_MASK, - QDMA_OFFSET_C2H_ERR_STAT, - QDMA_C2H_ERR_PORTID_CTXT_MISMATCH_MASK, - QDMA_GLBL_ERR_ST_C2H_MASK, - &qdma_hw_st_c2h_err_process - }, - { - QDMA_ST_C2H_ERR_PORTID_BYP_IN_MISMATCH, - "Port id in packet and bypass interface mismatch error", - QDMA_OFFSET_C2H_ERR_MASK, - QDMA_OFFSET_C2H_ERR_STAT, - QDMA_C2H_ERR_PORTID_BYP_IN_MISMATCH_MASK, - QDMA_GLBL_ERR_ST_C2H_MASK, - &qdma_hw_st_c2h_err_process - }, - { - QDMA_ST_C2H_ERR_CMPT_INV_Q_ERR, - "Writeback on invalid queue error", - QDMA_OFFSET_C2H_ERR_MASK, - QDMA_OFFSET_C2H_ERR_STAT, - QDMA_C2H_ERR_CMPT_INV_Q_ERR_MASK, - QDMA_GLBL_ERR_ST_C2H_MASK, - &qdma_hw_st_c2h_err_process - }, - { - QDMA_ST_C2H_ERR_CMPT_QFULL_ERR, - "Completion queue gets full error", - QDMA_OFFSET_C2H_ERR_MASK, - QDMA_OFFSET_C2H_ERR_STAT, - QDMA_C2H_ERR_CMPT_QFULL_ERR_MASK, - QDMA_GLBL_ERR_ST_C2H_MASK, - &qdma_hw_st_c2h_err_process - }, - { - QDMA_ST_C2H_ERR_CMPT_CIDX_ERR, - "Bad CIDX update by the software error", - QDMA_OFFSET_C2H_ERR_MASK, - QDMA_OFFSET_C2H_ERR_STAT, - QDMA_C2H_ERR_CMPT_CIDX_ERR_MASK, - QDMA_GLBL_ERR_ST_C2H_MASK, - &qdma_hw_st_c2h_err_process - }, - { - QDMA_ST_C2H_ERR_CMPT_PRTY_ERR, - "C2H completion Parity error", - QDMA_OFFSET_C2H_ERR_MASK, - QDMA_OFFSET_C2H_ERR_STAT, - QDMA_C2H_ERR_CMPT_PRTY_ERR_MASK, - QDMA_GLBL_ERR_ST_C2H_MASK, - &qdma_hw_st_c2h_err_process - }, - { - QDMA_ST_C2H_ERR_ALL, - "All C2h errors", - QDMA_OFFSET_C2H_ERR_MASK, - QDMA_OFFSET_C2H_ERR_STAT, - QDMA_C2H_ERR_ALL_MASK, - QDMA_GLBL_ERR_ST_C2H_MASK, - &qdma_hw_st_c2h_err_process - }, - - /* C2H fatal errors */ - { - QDMA_ST_FATAL_ERR_MTY_MISMATCH, - "Fatal MTY mismatch error", - QDMA_OFFSET_C2H_FATAL_ERR_MASK, - QDMA_OFFSET_C2H_FATAL_ERR_STAT, - QDMA_C2H_FATAL_ERR_MTY_MISMATCH_MASK, - QDMA_GLBL_ERR_ST_C2H_MASK, - &qdma_hw_st_c2h_err_process - }, - { - QDMA_ST_FATAL_ERR_LEN_MISMATCH, - "Fatal Len mismatch error", - QDMA_OFFSET_C2H_FATAL_ERR_MASK, - QDMA_OFFSET_C2H_FATAL_ERR_STAT, - QDMA_C2H_FATAL_ERR_LEN_MISMATCH_MASK, - QDMA_GLBL_ERR_ST_C2H_MASK, - &qdma_hw_st_c2h_err_process - }, - { - QDMA_ST_FATAL_ERR_QID_MISMATCH, - "Fatal Qid mismatch error", - QDMA_OFFSET_C2H_FATAL_ERR_MASK, - QDMA_OFFSET_C2H_FATAL_ERR_STAT, - QDMA_C2H_FATAL_ERR_QID_MISMATCH_MASK, - QDMA_GLBL_ERR_ST_C2H_MASK, - &qdma_hw_st_c2h_err_process - }, - { - QDMA_ST_FATAL_ERR_TIMER_FIFO_RAM_RDBE, - "RAM double bit fatal error", - QDMA_OFFSET_C2H_FATAL_ERR_MASK, - QDMA_OFFSET_C2H_FATAL_ERR_STAT, - QDMA_C2H_FATAL_ERR_TIMER_FIFO_RAM_RDBE_MASK, - QDMA_GLBL_ERR_ST_C2H_MASK, - &qdma_hw_st_c2h_err_process - }, - { - QDMA_ST_FATAL_ERR_PFCH_II_RAM_RDBE, - "RAM double bit fatal error", - QDMA_OFFSET_C2H_FATAL_ERR_MASK, - QDMA_OFFSET_C2H_FATAL_ERR_STAT, - QDMA_C2H_FATAL_ERR_PFCH_II_RAM_RDBE_MASK, - QDMA_GLBL_ERR_ST_C2H_MASK, - &qdma_hw_st_c2h_err_process - }, - { - QDMA_ST_FATAL_ERR_CMPT_CTXT_RAM_RDBE, - "RAM double bit fatal error", - QDMA_OFFSET_C2H_FATAL_ERR_MASK, - QDMA_OFFSET_C2H_FATAL_ERR_STAT, - QDMA_C2H_FATAL_ERR_CMPT_CTXT_RAM_RDBE_MASK, - QDMA_GLBL_ERR_ST_C2H_MASK, - &qdma_hw_st_c2h_err_process - }, - { - QDMA_ST_FATAL_ERR_PFCH_CTXT_RAM_RDBE, - "RAM double bit fatal error", - QDMA_OFFSET_C2H_FATAL_ERR_MASK, - QDMA_OFFSET_C2H_FATAL_ERR_STAT, - QDMA_C2H_FATAL_ERR_PFCH_CTXT_RAM_RDBE_MASK, - QDMA_GLBL_ERR_ST_C2H_MASK, - &qdma_hw_st_c2h_err_process - }, - { - QDMA_ST_FATAL_ERR_DESC_REQ_FIFO_RAM_RDBE, - "RAM double bit fatal error", - QDMA_OFFSET_C2H_FATAL_ERR_MASK, - QDMA_OFFSET_C2H_FATAL_ERR_STAT, - QDMA_C2H_FATAL_ERR_DESC_REQ_FIFO_RAM_RDBE_MASK, - QDMA_GLBL_ERR_ST_C2H_MASK, - &qdma_hw_st_c2h_err_process - }, - { - QDMA_ST_FATAL_ERR_INT_CTXT_RAM_RDBE, - "RAM double bit fatal error", - QDMA_OFFSET_C2H_FATAL_ERR_MASK, - QDMA_OFFSET_C2H_FATAL_ERR_STAT, - QDMA_C2H_FATAL_ERR_INT_CTXT_RAM_RDBE_MASK, - QDMA_GLBL_ERR_ST_C2H_MASK, - &qdma_hw_st_c2h_err_process - }, - { - QDMA_ST_FATAL_ERR_CMPT_COAL_DATA_RAM_RDBE, - "RAM double bit fatal error", - QDMA_OFFSET_C2H_FATAL_ERR_MASK, - QDMA_OFFSET_C2H_FATAL_ERR_STAT, - QDMA_C2H_FATAL_ERR_CMPT_COAL_DATA_RAM_RDBE_MASK, - QDMA_GLBL_ERR_ST_C2H_MASK, - &qdma_hw_st_c2h_err_process - }, - { - QDMA_ST_FATAL_ERR_TUSER_FIFO_RAM_RDBE, - "RAM double bit fatal error", - QDMA_OFFSET_C2H_FATAL_ERR_MASK, - QDMA_OFFSET_C2H_FATAL_ERR_STAT, - QDMA_C2H_FATAL_ERR_TUSER_FIFO_RAM_RDBE_MASK, - QDMA_GLBL_ERR_ST_C2H_MASK, - &qdma_hw_st_c2h_err_process - }, - { - QDMA_ST_FATAL_ERR_QID_FIFO_RAM_RDBE, - "RAM double bit fatal error", - QDMA_OFFSET_C2H_FATAL_ERR_MASK, - QDMA_OFFSET_C2H_FATAL_ERR_STAT, - QDMA_C2H_FATAL_ERR_QID_FIFO_RAM_RDBE_MASK, - QDMA_GLBL_ERR_ST_C2H_MASK, - &qdma_hw_st_c2h_err_process - }, - { - QDMA_ST_FATAL_ERR_PAYLOAD_FIFO_RAM_RDBE, - "RAM double bit fatal error", - QDMA_OFFSET_C2H_FATAL_ERR_MASK, - QDMA_OFFSET_C2H_FATAL_ERR_STAT, - QDMA_C2H_FATAL_ERR_PAYLOAD_FIFO_RAM_RDBE_MASK, - QDMA_GLBL_ERR_ST_C2H_MASK, - &qdma_hw_st_c2h_err_process - }, - { - QDMA_ST_FATAL_ERR_WPL_DATA_PAR, - "RAM double bit fatal error", - QDMA_OFFSET_C2H_FATAL_ERR_MASK, - QDMA_OFFSET_C2H_FATAL_ERR_STAT, - QDMA_C2H_FATAL_ERR_WPL_DATA_PAR_MASK, - QDMA_GLBL_ERR_ST_C2H_MASK, - &qdma_hw_st_c2h_err_process - }, - { - QDMA_ST_FATAL_ERR_ALL, - "All fatal errors", - QDMA_OFFSET_C2H_FATAL_ERR_MASK, - QDMA_OFFSET_C2H_FATAL_ERR_STAT, - QDMA_C2H_FATAL_ERR_ALL_MASK, - QDMA_GLBL_ERR_ST_C2H_MASK, - &qdma_hw_st_c2h_err_process - }, - - /* H2C St errors */ - { - QDMA_ST_H2C_ERR_ZERO_LEN_DESC, - "Zero length descriptor error", - QDMA_OFFSET_H2C_ERR_MASK, - QDMA_OFFSET_H2C_ERR_STAT, - QDMA_H2C_ERR_ZERO_LEN_DESC_MASK, - QDMA_GLBL_ERR_ST_H2C_MASK, - &qdma_hw_st_h2c_err_process - }, - { - QDMA_ST_H2C_ERR_CSI_MOP, - "Non EOP descriptor received error", - QDMA_OFFSET_H2C_ERR_MASK, - QDMA_OFFSET_H2C_ERR_STAT, - QDMA_H2C_ERR_CSI_MOP_MASK, - QDMA_GLBL_ERR_ST_H2C_MASK, - &qdma_hw_st_h2c_err_process - }, - { - QDMA_ST_H2C_ERR_NO_DMA_DSC, - "No DMA descriptor received error", - QDMA_OFFSET_H2C_ERR_MASK, - QDMA_OFFSET_H2C_ERR_STAT, - QDMA_H2C_ERR_NO_DMA_DSC_MASK, - QDMA_GLBL_ERR_ST_H2C_MASK, - &qdma_hw_st_h2c_err_process - }, - { - QDMA_ST_H2C_ERR_SBE, - "Single bit error detected on H2C-ST data error", - QDMA_OFFSET_H2C_ERR_MASK, - QDMA_OFFSET_H2C_ERR_STAT, - QDMA_H2C_ERR_SBE_MASK, - QDMA_GLBL_ERR_ST_H2C_MASK, - &qdma_hw_st_h2c_err_process - }, - { - QDMA_ST_H2C_ERR_DBE, - "Double bit error detected on H2C-ST data error", - QDMA_OFFSET_H2C_ERR_MASK, - QDMA_OFFSET_H2C_ERR_STAT, - QDMA_H2C_ERR_DBE_MASK, - QDMA_GLBL_ERR_ST_H2C_MASK, - &qdma_hw_st_h2c_err_process - }, - { - QDMA_ST_H2C_ERR_ALL, - "All H2C errors", - QDMA_OFFSET_H2C_ERR_MASK, - QDMA_OFFSET_H2C_ERR_STAT, - QDMA_H2C_ERR_ALL_MASK, - QDMA_GLBL_ERR_ST_H2C_MASK, - &qdma_hw_st_h2c_err_process - }, - - /* SBE errors */ - { - QDMA_SBE_ERR_MI_H2C0_DAT, - "H2C MM data buffer single bit ECC error", - QDMA_OFFSET_RAM_SBE_MASK, - QDMA_OFFSET_RAM_SBE_STAT, - QDMA_SBE_ERR_MI_H2C0_DAT_MASK, - QDMA_GLBL_ERR_RAM_SBE_MASK, - &qdma_hw_ram_sbe_err_process - }, - { - QDMA_SBE_ERR_MI_C2H0_DAT, - "C2H MM data buffer single bit ECC error", - QDMA_OFFSET_RAM_SBE_MASK, - QDMA_OFFSET_RAM_SBE_STAT, - QDMA_SBE_ERR_MI_C2H0_DAT_MASK, - QDMA_GLBL_ERR_RAM_SBE_MASK, - &qdma_hw_ram_sbe_err_process - }, - { - QDMA_SBE_ERR_H2C_RD_BRG_DAT, - "Bridge master read single bit ECC error", - QDMA_OFFSET_RAM_SBE_MASK, - QDMA_OFFSET_RAM_SBE_STAT, - QDMA_SBE_ERR_H2C_RD_BRG_DAT_MASK, - QDMA_GLBL_ERR_RAM_SBE_MASK, - &qdma_hw_ram_sbe_err_process - }, - { - QDMA_SBE_ERR_H2C_WR_BRG_DAT, - "Bridge master write single bit ECC error", - QDMA_OFFSET_RAM_SBE_MASK, - QDMA_OFFSET_RAM_SBE_STAT, - QDMA_SBE_ERR_H2C_WR_BRG_DAT_MASK, - QDMA_GLBL_ERR_RAM_SBE_MASK, - &qdma_hw_ram_sbe_err_process - }, - { - QDMA_SBE_ERR_C2H_RD_BRG_DAT, - "Bridge slave read data buffer single bit ECC error", - QDMA_OFFSET_RAM_SBE_MASK, - QDMA_OFFSET_RAM_SBE_STAT, - QDMA_SBE_ERR_C2H_RD_BRG_DAT_MASK, - QDMA_GLBL_ERR_RAM_SBE_MASK, - &qdma_hw_ram_sbe_err_process - }, - { - QDMA_SBE_ERR_C2H_WR_BRG_DAT, - "Bridge slave write data buffer single bit ECC error", - QDMA_OFFSET_RAM_SBE_MASK, - QDMA_OFFSET_RAM_SBE_STAT, - QDMA_SBE_ERR_C2H_WR_BRG_DAT_MASK, - QDMA_GLBL_ERR_RAM_SBE_MASK, - &qdma_hw_ram_sbe_err_process - }, - { - QDMA_SBE_ERR_FUNC_MAP, - "Function map RAM single bit ECC error", - QDMA_OFFSET_RAM_SBE_MASK, - QDMA_OFFSET_RAM_SBE_STAT, - QDMA_SBE_ERR_FUNC_MAP_MASK, - QDMA_GLBL_ERR_RAM_SBE_MASK, - &qdma_hw_ram_sbe_err_process - }, - { - QDMA_SBE_ERR_DSC_HW_CTXT, - "Descriptor engine hardware context RAM single bit ECC error", - QDMA_OFFSET_RAM_SBE_MASK, - QDMA_OFFSET_RAM_SBE_STAT, - QDMA_SBE_ERR_DSC_HW_CTXT_MASK, - QDMA_GLBL_ERR_RAM_SBE_MASK, - &qdma_hw_ram_sbe_err_process - }, - { - QDMA_SBE_ERR_DSC_CRD_RCV, - "Descriptor engine receive credit context RAM single bit ECC error", - QDMA_OFFSET_RAM_SBE_MASK, - QDMA_OFFSET_RAM_SBE_STAT, - QDMA_SBE_ERR_DSC_CRD_RCV_MASK, - QDMA_GLBL_ERR_RAM_SBE_MASK, - &qdma_hw_ram_sbe_err_process - }, - { - QDMA_SBE_ERR_DSC_SW_CTXT, - "Descriptor engine software context RAM single bit ECC error", - QDMA_OFFSET_RAM_SBE_MASK, - QDMA_OFFSET_RAM_SBE_STAT, - QDMA_SBE_ERR_DSC_SW_CTXT_MASK, - QDMA_GLBL_ERR_RAM_SBE_MASK, - &qdma_hw_ram_sbe_err_process - }, - { - QDMA_SBE_ERR_DSC_CPLI, - "Descriptor engine fetch completion information RAM single bit ECC error", - QDMA_OFFSET_RAM_SBE_MASK, - QDMA_OFFSET_RAM_SBE_STAT, - QDMA_SBE_ERR_DSC_CPLI_MASK, - QDMA_GLBL_ERR_RAM_SBE_MASK, - &qdma_hw_ram_sbe_err_process - }, - { - QDMA_SBE_ERR_DSC_CPLD, - "Descriptor engine fetch completion data RAM single bit ECC error", - QDMA_OFFSET_RAM_SBE_MASK, - QDMA_OFFSET_RAM_SBE_STAT, - QDMA_SBE_ERR_DSC_CPLD_MASK, - QDMA_GLBL_ERR_RAM_SBE_MASK, - &qdma_hw_ram_sbe_err_process - }, - { - QDMA_SBE_ERR_PASID_CTXT_RAM, - "PASID configuration RAM single bit ECC error", - QDMA_OFFSET_RAM_SBE_MASK, - QDMA_OFFSET_RAM_SBE_STAT, - QDMA_SBE_ERR_PASID_CTXT_RAM_MASK, - QDMA_GLBL_ERR_RAM_SBE_MASK, - &qdma_hw_ram_sbe_err_process - }, - { - QDMA_SBE_ERR_TIMER_FIFO_RAM, - "Timer fifo RAM single bit ECC error", - QDMA_OFFSET_RAM_SBE_MASK, - QDMA_OFFSET_RAM_SBE_STAT, - QDMA_SBE_ERR_TIMER_FIFO_RAM_MASK, - QDMA_GLBL_ERR_RAM_SBE_MASK, - &qdma_hw_ram_sbe_err_process - }, - { - QDMA_SBE_ERR_PAYLOAD_FIFO_RAM, - "C2H ST payload RAM single bit ECC error", - QDMA_OFFSET_RAM_SBE_MASK, - QDMA_OFFSET_RAM_SBE_STAT, - QDMA_SBE_ERR_PAYLOAD_FIFO_RAM_MASK, - QDMA_GLBL_ERR_RAM_SBE_MASK, - &qdma_hw_ram_sbe_err_process - }, - { - QDMA_SBE_ERR_QID_FIFO_RAM, - "C2H ST QID FIFO RAM single bit ECC error", - QDMA_OFFSET_RAM_SBE_MASK, - QDMA_OFFSET_RAM_SBE_STAT, - QDMA_SBE_ERR_QID_FIFO_RAM_MASK, - QDMA_GLBL_ERR_RAM_SBE_MASK, - &qdma_hw_ram_sbe_err_process - }, - { - QDMA_SBE_ERR_TUSER_FIFO_RAM, - "C2H ST TUSER RAM single bit ECC error", - QDMA_OFFSET_RAM_SBE_MASK, - QDMA_OFFSET_RAM_SBE_STAT, - QDMA_SBE_ERR_TUSER_FIFO_RAM_MASK, - QDMA_GLBL_ERR_RAM_SBE_MASK, - &qdma_hw_ram_sbe_err_process - }, - { - QDMA_SBE_ERR_WRB_COAL_DATA_RAM, - "Completion Coalescing RAM single bit ECC error", - QDMA_OFFSET_RAM_SBE_MASK, - QDMA_OFFSET_RAM_SBE_STAT, - QDMA_SBE_ERR_WRB_COAL_DATA_RAM_MASK, - QDMA_GLBL_ERR_RAM_SBE_MASK, - &qdma_hw_ram_sbe_err_process - }, - { - QDMA_SBE_ERR_INT_QID2VEC_RAM, - "Interrupt QID2VEC RAM single bit ECC error", - QDMA_OFFSET_RAM_SBE_MASK, - QDMA_OFFSET_RAM_SBE_STAT, - QDMA_SBE_ERR_INT_QID2VEC_RAM_MASK, - QDMA_GLBL_ERR_RAM_SBE_MASK, - &qdma_hw_ram_sbe_err_process - }, - { - QDMA_SBE_ERR_INT_CTXT_RAM, - "Interrupt context RAM single bit ECC error", - QDMA_OFFSET_RAM_SBE_MASK, - QDMA_OFFSET_RAM_SBE_STAT, - QDMA_SBE_ERR_INT_CTXT_RAM_MASK, - QDMA_GLBL_ERR_RAM_SBE_MASK, - &qdma_hw_ram_sbe_err_process - }, - { - QDMA_SBE_ERR_DESC_REQ_FIFO_RAM, - "C2H ST descriptor request RAM single bit ECC error", - QDMA_OFFSET_RAM_SBE_MASK, - QDMA_OFFSET_RAM_SBE_STAT, - QDMA_SBE_ERR_DESC_REQ_FIFO_RAM_MASK, - QDMA_GLBL_ERR_RAM_SBE_MASK, - &qdma_hw_ram_sbe_err_process - }, - { - QDMA_SBE_ERR_PFCH_CTXT_RAM, - "C2H ST prefetch RAM single bit ECC error", - QDMA_OFFSET_RAM_SBE_MASK, - QDMA_OFFSET_RAM_SBE_STAT, - QDMA_SBE_ERR_PFCH_CTXT_RAM_MASK, - QDMA_GLBL_ERR_RAM_SBE_MASK, - &qdma_hw_ram_sbe_err_process - }, - { - QDMA_SBE_ERR_WRB_CTXT_RAM, - "C2H ST completion context RAM single bit ECC error", - QDMA_OFFSET_RAM_SBE_MASK, - QDMA_OFFSET_RAM_SBE_STAT, - QDMA_SBE_ERR_WRB_CTXT_RAM_MASK, - QDMA_GLBL_ERR_RAM_SBE_MASK, - &qdma_hw_ram_sbe_err_process - }, - { - QDMA_SBE_ERR_PFCH_LL_RAM, - "C2H ST prefetch list RAM single bit ECC error", - QDMA_OFFSET_RAM_SBE_MASK, - QDMA_OFFSET_RAM_SBE_STAT, - QDMA_SBE_ERR_PFCH_LL_RAM_MASK, - QDMA_GLBL_ERR_RAM_SBE_MASK, - &qdma_hw_ram_sbe_err_process - }, - { - QDMA_SBE_ERR_H2C_PEND_FIFO, - "H2C ST pending fifo RAM single bit ECC error", - QDMA_OFFSET_RAM_SBE_MASK, - QDMA_OFFSET_RAM_SBE_STAT, - QDMA_SBE_ERR_H2C_PEND_FIFO_MASK, - QDMA_GLBL_ERR_RAM_SBE_MASK, - &qdma_hw_ram_sbe_err_process - }, - { - QDMA_SBE_ERR_ALL, - "All SBE errors", - QDMA_OFFSET_RAM_SBE_MASK, - QDMA_OFFSET_RAM_SBE_STAT, - QDMA_SBE_ERR_ALL_MASK, - QDMA_GLBL_ERR_RAM_SBE_MASK, - &qdma_hw_ram_sbe_err_process - }, - - - /* DBE Errors */ - { - QDMA_DBE_ERR_MI_H2C0_DAT, - "H2C MM data buffer double bit ECC error", - QDMA_OFFSET_RAM_DBE_MASK, - QDMA_OFFSET_RAM_DBE_STAT, - QDMA_DBE_ERR_MI_H2C0_DAT_MASK, - QDMA_GLBL_ERR_RAM_DBE_MASK, - &qdma_hw_ram_dbe_err_process - }, - { - QDMA_DBE_ERR_MI_C2H0_DAT, - "C2H MM data buffer double bit ECC error", - QDMA_OFFSET_RAM_DBE_MASK, - QDMA_OFFSET_RAM_DBE_STAT, - QDMA_DBE_ERR_MI_C2H0_DAT_MASK, - QDMA_GLBL_ERR_RAM_DBE_MASK, - &qdma_hw_ram_dbe_err_process - }, - { - QDMA_DBE_ERR_H2C_RD_BRG_DAT, - "Bridge master read double bit ECC error", - QDMA_OFFSET_RAM_DBE_MASK, - QDMA_OFFSET_RAM_DBE_STAT, - QDMA_DBE_ERR_H2C_RD_BRG_DAT_MASK, - QDMA_GLBL_ERR_RAM_DBE_MASK, - &qdma_hw_ram_dbe_err_process - }, - { - QDMA_DBE_ERR_H2C_WR_BRG_DAT, - "Bridge master write double bit ECC error", - QDMA_OFFSET_RAM_DBE_MASK, - QDMA_OFFSET_RAM_DBE_STAT, - QDMA_DBE_ERR_H2C_WR_BRG_DAT_MASK, - QDMA_GLBL_ERR_RAM_DBE_MASK, - &qdma_hw_ram_dbe_err_process - }, - { - QDMA_DBE_ERR_C2H_RD_BRG_DAT, - "Bridge slave read data buffer double bit ECC error", - QDMA_OFFSET_RAM_DBE_MASK, - QDMA_OFFSET_RAM_DBE_STAT, - QDMA_DBE_ERR_C2H_RD_BRG_DAT_MASK, - QDMA_GLBL_ERR_RAM_DBE_MASK, - &qdma_hw_ram_dbe_err_process - }, - { - QDMA_DBE_ERR_C2H_WR_BRG_DAT, - "Bridge slave write data buffer double bit ECC error", - QDMA_OFFSET_RAM_DBE_MASK, - QDMA_OFFSET_RAM_DBE_STAT, - QDMA_DBE_ERR_C2H_WR_BRG_DAT_MASK, - QDMA_GLBL_ERR_RAM_DBE_MASK, - &qdma_hw_ram_dbe_err_process - }, - { - QDMA_DBE_ERR_FUNC_MAP, - "Function map RAM double bit ECC error", - QDMA_OFFSET_RAM_DBE_MASK, - QDMA_OFFSET_RAM_DBE_STAT, - QDMA_DBE_ERR_FUNC_MAP_MASK, - QDMA_GLBL_ERR_RAM_DBE_MASK, - &qdma_hw_ram_dbe_err_process - }, - { - QDMA_DBE_ERR_DSC_HW_CTXT, - "Descriptor engine hardware context RAM double bit ECC error", - QDMA_OFFSET_RAM_DBE_MASK, - QDMA_OFFSET_RAM_DBE_STAT, - QDMA_DBE_ERR_DSC_HW_CTXT_MASK, - QDMA_GLBL_ERR_RAM_DBE_MASK, - &qdma_hw_ram_dbe_err_process - }, - { - QDMA_DBE_ERR_DSC_CRD_RCV, - "Descriptor engine receive credit context RAM double bit ECC error", - QDMA_OFFSET_RAM_DBE_MASK, - QDMA_OFFSET_RAM_DBE_STAT, - QDMA_DBE_ERR_DSC_CRD_RCV_MASK, - QDMA_GLBL_ERR_RAM_DBE_MASK, - &qdma_hw_ram_dbe_err_process - }, - { - QDMA_DBE_ERR_DSC_SW_CTXT, - "Descriptor engine software context RAM double bit ECC error", - QDMA_OFFSET_RAM_DBE_MASK, - QDMA_OFFSET_RAM_DBE_STAT, - QDMA_DBE_ERR_DSC_SW_CTXT_MASK, - QDMA_GLBL_ERR_RAM_DBE_MASK, - &qdma_hw_ram_dbe_err_process - }, - { - QDMA_DBE_ERR_DSC_CPLI, - "Descriptor engine fetch completion information RAM double bit ECC error", - QDMA_OFFSET_RAM_DBE_MASK, - QDMA_OFFSET_RAM_DBE_STAT, - QDMA_DBE_ERR_DSC_CPLI_MASK, - QDMA_GLBL_ERR_RAM_DBE_MASK, - &qdma_hw_ram_dbe_err_process - }, - { - QDMA_DBE_ERR_DSC_CPLD, - "Descriptor engine fetch completion data RAM double bit ECC error", - QDMA_OFFSET_RAM_DBE_MASK, - QDMA_OFFSET_RAM_DBE_STAT, - QDMA_DBE_ERR_DSC_CPLD_MASK, - QDMA_GLBL_ERR_RAM_DBE_MASK, - &qdma_hw_ram_dbe_err_process - }, - { - QDMA_DBE_ERR_PASID_CTXT_RAM, - "PASID configuration RAM double bit ECC error", - QDMA_OFFSET_RAM_DBE_MASK, - QDMA_OFFSET_RAM_DBE_STAT, - QDMA_DBE_ERR_PASID_CTXT_RAM_MASK, - QDMA_GLBL_ERR_RAM_DBE_MASK, - &qdma_hw_ram_dbe_err_process - }, - { - QDMA_DBE_ERR_TIMER_FIFO_RAM, - "Timer fifo RAM double bit ECC error", - QDMA_OFFSET_RAM_DBE_MASK, - QDMA_OFFSET_RAM_DBE_STAT, - QDMA_DBE_ERR_TIMER_FIFO_RAM_MASK, - QDMA_GLBL_ERR_RAM_DBE_MASK, - &qdma_hw_ram_dbe_err_process - }, - { - QDMA_DBE_ERR_PAYLOAD_FIFO_RAM, - "C2H ST payload RAM double bit ECC error", - QDMA_OFFSET_RAM_DBE_MASK, - QDMA_OFFSET_RAM_DBE_STAT, - QDMA_DBE_ERR_PAYLOAD_FIFO_RAM_MASK, - QDMA_GLBL_ERR_RAM_DBE_MASK, - &qdma_hw_ram_dbe_err_process - }, - { - QDMA_DBE_ERR_QID_FIFO_RAM, - "C2H ST QID FIFO RAM double bit ECC error", - QDMA_OFFSET_RAM_DBE_MASK, - QDMA_OFFSET_RAM_DBE_STAT, - QDMA_DBE_ERR_QID_FIFO_RAM_MASK, - QDMA_GLBL_ERR_RAM_DBE_MASK, - &qdma_hw_ram_dbe_err_process - }, - { - QDMA_DBE_ERR_TUSER_FIFO_RAM, - "C2H ST TUSER RAM double bit ECC error", - QDMA_OFFSET_RAM_DBE_MASK, - QDMA_OFFSET_RAM_DBE_STAT, - QDMA_DBE_ERR_TUSER_FIFO_RAM_MASK, - QDMA_GLBL_ERR_RAM_DBE_MASK, - &qdma_hw_ram_dbe_err_process - }, - { - QDMA_DBE_ERR_WRB_COAL_DATA_RAM, - "Completion Coalescing RAM double bit ECC error", - QDMA_OFFSET_RAM_DBE_MASK, - QDMA_OFFSET_RAM_DBE_STAT, - QDMA_DBE_ERR_WRB_COAL_DATA_RAM_MASK, - QDMA_GLBL_ERR_RAM_DBE_MASK, - &qdma_hw_ram_dbe_err_process - }, - { - QDMA_DBE_ERR_INT_QID2VEC_RAM, - "Interrupt QID2VEC RAM double bit ECC error", - QDMA_OFFSET_RAM_DBE_MASK, - QDMA_OFFSET_RAM_DBE_STAT, - QDMA_DBE_ERR_INT_QID2VEC_RAM_MASK, - QDMA_GLBL_ERR_RAM_DBE_MASK, - &qdma_hw_ram_dbe_err_process - }, - { - QDMA_DBE_ERR_INT_CTXT_RAM, - "Interrupt context RAM double bit ECC error", - QDMA_OFFSET_RAM_DBE_MASK, - QDMA_OFFSET_RAM_DBE_STAT, - QDMA_DBE_ERR_INT_CTXT_RAM_MASK, - QDMA_GLBL_ERR_RAM_DBE_MASK, - &qdma_hw_ram_dbe_err_process - }, - { - QDMA_DBE_ERR_DESC_REQ_FIFO_RAM, - "C2H ST descriptor request RAM double bit ECC error", - QDMA_OFFSET_RAM_DBE_MASK, - QDMA_OFFSET_RAM_DBE_STAT, - QDMA_DBE_ERR_DESC_REQ_FIFO_RAM_MASK, - QDMA_GLBL_ERR_RAM_DBE_MASK, - &qdma_hw_ram_dbe_err_process - }, - { - QDMA_DBE_ERR_PFCH_CTXT_RAM, - "C2H ST prefetch RAM double bit ECC error", - QDMA_OFFSET_RAM_DBE_MASK, - QDMA_OFFSET_RAM_DBE_STAT, - QDMA_DBE_ERR_PFCH_CTXT_RAM_MASK, - QDMA_GLBL_ERR_RAM_DBE_MASK, - &qdma_hw_ram_dbe_err_process - }, - { - QDMA_DBE_ERR_WRB_CTXT_RAM, - "C2H ST completion context RAM double bit ECC error", - QDMA_OFFSET_RAM_DBE_MASK, - QDMA_OFFSET_RAM_DBE_STAT, - QDMA_DBE_ERR_WRB_CTXT_RAM_MASK, - QDMA_GLBL_ERR_RAM_DBE_MASK, - &qdma_hw_ram_dbe_err_process - }, - { - QDMA_DBE_ERR_PFCH_LL_RAM, - "C2H ST prefetch list RAM double bit ECC error", - QDMA_OFFSET_RAM_DBE_MASK, - QDMA_OFFSET_RAM_DBE_STAT, - QDMA_DBE_ERR_PFCH_LL_RAM_MASK, - QDMA_GLBL_ERR_RAM_DBE_MASK, - &qdma_hw_ram_dbe_err_process - }, - { - QDMA_DBE_ERR_H2C_PEND_FIFO, - "H2C pending fifo RAM double bit ECC error", - QDMA_OFFSET_RAM_DBE_MASK, - QDMA_OFFSET_RAM_DBE_STAT, - QDMA_DBE_ERR_H2C_PEND_FIFO_MASK, - QDMA_GLBL_ERR_RAM_DBE_MASK, - &qdma_hw_ram_dbe_err_process - }, - { - QDMA_DBE_ERR_ALL, - "All DBE errors", - QDMA_OFFSET_RAM_DBE_MASK, - QDMA_OFFSET_RAM_DBE_STAT, - QDMA_DBE_ERR_ALL_MASK, - QDMA_GLBL_ERR_RAM_DBE_MASK, - &qdma_hw_ram_dbe_err_process - } -}; - -static int32_t all_hw_errs[TOTAL_LEAF_ERROR_AGGREGATORS] = { - - QDMA_DSC_ERR_ALL, - QDMA_TRQ_ERR_ALL, - QDMA_ST_C2H_ERR_ALL, - QDMA_ST_FATAL_ERR_ALL, - QDMA_ST_H2C_ERR_ALL, - QDMA_SBE_ERR_ALL, - QDMA_DBE_ERR_ALL -}; - -static int qdma_indirect_reg_invalidate(void *dev_hndl, - enum ind_ctxt_cmd_sel sel, uint16_t hw_qid); -static int qdma_indirect_reg_clear(void *dev_hndl, - enum ind_ctxt_cmd_sel sel, uint16_t hw_qid); -static int qdma_indirect_reg_read(void *dev_hndl, enum ind_ctxt_cmd_sel sel, - uint16_t hw_qid, uint32_t cnt, uint32_t *data); -static int qdma_indirect_reg_write(void *dev_hndl, enum ind_ctxt_cmd_sel sel, - uint16_t hw_qid, uint32_t *data, uint16_t cnt); - - -static struct qctx_entry sw_ctxt_entries[] = { - {"PIDX", 0}, - {"IRQ Arm", 0}, - {"Function Id", 0}, - {"Queue Enable", 0}, - {"Fetch Credit Enable", 0}, - {"Write back/Intr Check", 0}, - {"Write back/Intr Interval", 0}, - {"Address Translation", 0}, - {"Fetch Max", 0}, - {"Ring Size", 0}, - {"Descriptor Size", 0}, - {"Bypass Enable", 0}, - {"MM Channel", 0}, - {"Writeback Enable", 0}, - {"Interrupt Enable", 0}, - {"Port Id", 0}, - {"Interrupt No Last", 0}, - {"Error", 0}, - {"Writeback Error Sent", 0}, - {"IRQ Request", 0}, - {"Marker Disable", 0}, - {"Is Memory Mapped", 0}, - {"Descriptor Ring Base Addr (Low)", 0}, - {"Descriptor Ring Base Addr (High)", 0}, - {"Interrupt Vector/Ring Index", 0}, - {"Interrupt Aggregation", 0}, -}; - -static struct qctx_entry hw_ctxt_entries[] = { - {"CIDX", 0}, - {"Credits Consumed", 0}, - {"Descriptors Pending", 0}, - {"Queue Invalid No Desc Pending", 0}, - {"Eviction Pending", 0}, - {"Fetch Pending", 0}, -}; - -static struct qctx_entry credit_ctxt_entries[] = { - {"Credit", 0}, -}; - -static struct qctx_entry cmpt_ctxt_entries[] = { - {"Enable Status Desc Update", 0}, - {"Enable Interrupt", 0}, - {"Trigger Mode", 0}, - {"Function Id", 0}, - {"Counter Index", 0}, - {"Timer Index", 0}, - {"Interrupt State", 0}, - {"Color", 0}, - {"Ring Size", 0}, - {"Base Address (Low)", 0}, - {"Base Address (High)", 0}, - {"Descriptor Size", 0}, - {"PIDX", 0}, - {"CIDX", 0}, - {"Valid", 0}, - {"Error", 0}, - {"Trigger Pending", 0}, - {"Timer Running", 0}, - {"Full Update", 0}, - {"Over Flow Check Disable", 0}, - {"Address Translation", 0}, - {"Interrupt Vector/Ring Index", 0}, - {"Interrupt Aggregation", 0}, -}; - -static struct qctx_entry c2h_pftch_ctxt_entries[] = { - {"Bypass", 0}, - {"Buffer Size Index", 0}, - {"Port Id", 0}, - {"Error", 0}, - {"Prefetch Enable", 0}, - {"In Prefetch", 0}, - {"Software Credit", 0}, - {"Valid", 0}, -}; - -static struct qctx_entry ind_intr_ctxt_entries[] = { - {"valid", 0}, - {"vec", 0}, - {"int_st", 0}, - {"color", 0}, - {"baddr_4k (Low)", 0}, - {"baddr_4k (High)", 0}, - {"page_size", 0}, - {"pidx", 0}, - {"at", 0}, -}; - -uint32_t qdma_soft_reg_dump_buf_len(void) -{ - uint32_t length = ((sizeof(qdma_config_regs) / - sizeof(qdma_config_regs[0])) + 1) * - REG_DUMP_SIZE_PER_LINE; - return length; -} - -uint32_t qdma_get_config_num_regs(void) -{ - return (sizeof(qdma_config_regs)/ - sizeof(qdma_config_regs[0])); -} - -struct xreg_info *qdma_get_config_regs(void) -{ - return qdma_config_regs; -} - -int qdma_soft_context_buf_len(uint8_t st, - enum qdma_dev_q_type q_type, uint32_t *buflen) -{ - uint32_t len = 0; - int rv = 0; - - *buflen = 0; - - if (q_type == QDMA_DEV_Q_TYPE_CMPT) { - len += (((sizeof(cmpt_ctxt_entries) / - sizeof(cmpt_ctxt_entries[0])) + 1) * - REG_DUMP_SIZE_PER_LINE); - } else { - len += (((sizeof(sw_ctxt_entries) / - sizeof(sw_ctxt_entries[0])) + 1) * - REG_DUMP_SIZE_PER_LINE); - - len += (((sizeof(hw_ctxt_entries) / - sizeof(hw_ctxt_entries[0])) + 1) * - REG_DUMP_SIZE_PER_LINE); - - len += (((sizeof(credit_ctxt_entries) / - sizeof(credit_ctxt_entries[0])) + 1) * - REG_DUMP_SIZE_PER_LINE); - - if (st && (q_type == QDMA_DEV_Q_TYPE_C2H)) { - len += (((sizeof(cmpt_ctxt_entries) / - sizeof(cmpt_ctxt_entries[0])) + 1) * - REG_DUMP_SIZE_PER_LINE); - - len += (((sizeof(c2h_pftch_ctxt_entries) / - sizeof(c2h_pftch_ctxt_entries[0])) - + 1) * REG_DUMP_SIZE_PER_LINE); - } - } - - *buflen = len; - return rv; -} - -/* - * qdma_acc_fill_sw_ctxt() - Helper function to fill sw context into structure - * - */ -static void qdma_fill_sw_ctxt(struct qdma_descq_sw_ctxt *sw_ctxt) -{ - sw_ctxt_entries[0].value = sw_ctxt->pidx; - sw_ctxt_entries[1].value = sw_ctxt->irq_arm; - sw_ctxt_entries[2].value = sw_ctxt->fnc_id; - sw_ctxt_entries[3].value = sw_ctxt->qen; - sw_ctxt_entries[4].value = sw_ctxt->frcd_en; - sw_ctxt_entries[5].value = sw_ctxt->wbi_chk; - sw_ctxt_entries[6].value = sw_ctxt->wbi_intvl_en; - sw_ctxt_entries[7].value = sw_ctxt->at; - sw_ctxt_entries[8].value = sw_ctxt->fetch_max; - sw_ctxt_entries[9].value = sw_ctxt->rngsz_idx; - sw_ctxt_entries[10].value = sw_ctxt->desc_sz; - sw_ctxt_entries[11].value = sw_ctxt->bypass; - sw_ctxt_entries[12].value = sw_ctxt->mm_chn; - sw_ctxt_entries[13].value = sw_ctxt->wbk_en; - sw_ctxt_entries[14].value = sw_ctxt->irq_en; - sw_ctxt_entries[15].value = sw_ctxt->port_id; - sw_ctxt_entries[16].value = sw_ctxt->irq_no_last; - sw_ctxt_entries[17].value = sw_ctxt->err; - sw_ctxt_entries[18].value = sw_ctxt->err_wb_sent; - sw_ctxt_entries[19].value = sw_ctxt->irq_req; - sw_ctxt_entries[20].value = sw_ctxt->mrkr_dis; - sw_ctxt_entries[21].value = sw_ctxt->is_mm; - sw_ctxt_entries[22].value = sw_ctxt->ring_bs_addr & 0xFFFFFFFF; - sw_ctxt_entries[23].value = - (sw_ctxt->ring_bs_addr >> 32) & 0xFFFFFFFF; - sw_ctxt_entries[24].value = sw_ctxt->vec; - sw_ctxt_entries[25].value = sw_ctxt->intr_aggr; -} - -/* - * qdma_acc_fill_cmpt_ctxt() - Helper function to fill completion context - * into structure - * - */ -static void qdma_fill_cmpt_ctxt(struct qdma_descq_cmpt_ctxt *cmpt_ctxt) -{ - cmpt_ctxt_entries[0].value = cmpt_ctxt->en_stat_desc; - cmpt_ctxt_entries[1].value = cmpt_ctxt->en_int; - cmpt_ctxt_entries[2].value = cmpt_ctxt->trig_mode; - cmpt_ctxt_entries[3].value = cmpt_ctxt->fnc_id; - cmpt_ctxt_entries[4].value = cmpt_ctxt->counter_idx; - cmpt_ctxt_entries[5].value = cmpt_ctxt->timer_idx; - cmpt_ctxt_entries[6].value = cmpt_ctxt->in_st; - cmpt_ctxt_entries[7].value = cmpt_ctxt->color; - cmpt_ctxt_entries[8].value = cmpt_ctxt->ringsz_idx; - cmpt_ctxt_entries[9].value = cmpt_ctxt->bs_addr & 0xFFFFFFFF; - cmpt_ctxt_entries[10].value = - (cmpt_ctxt->bs_addr >> 32) & 0xFFFFFFFF; - cmpt_ctxt_entries[11].value = cmpt_ctxt->desc_sz; - cmpt_ctxt_entries[12].value = cmpt_ctxt->pidx; - cmpt_ctxt_entries[13].value = cmpt_ctxt->cidx; - cmpt_ctxt_entries[14].value = cmpt_ctxt->valid; - cmpt_ctxt_entries[15].value = cmpt_ctxt->err; - cmpt_ctxt_entries[16].value = cmpt_ctxt->user_trig_pend; - cmpt_ctxt_entries[17].value = cmpt_ctxt->timer_running; - cmpt_ctxt_entries[18].value = cmpt_ctxt->full_upd; - cmpt_ctxt_entries[19].value = cmpt_ctxt->ovf_chk_dis; - cmpt_ctxt_entries[20].value = cmpt_ctxt->at; - cmpt_ctxt_entries[21].value = cmpt_ctxt->vec; - cmpt_ctxt_entries[22].value = cmpt_ctxt->int_aggr; -} - -/* - * qdma_acc_fill_hw_ctxt() - Helper function to fill HW context into structure - * - */ -static void qdma_fill_hw_ctxt(struct qdma_descq_hw_ctxt *hw_ctxt) -{ - hw_ctxt_entries[0].value = hw_ctxt->cidx; - hw_ctxt_entries[1].value = hw_ctxt->crd_use; - hw_ctxt_entries[2].value = hw_ctxt->dsc_pend; - hw_ctxt_entries[3].value = hw_ctxt->idl_stp_b; - hw_ctxt_entries[4].value = hw_ctxt->evt_pnd; - hw_ctxt_entries[5].value = hw_ctxt->fetch_pnd; -} - -/* - * qdma_acc_fill_credit_ctxt() - Helper function to fill Credit context - * into structure - * - */ -static void qdma_fill_credit_ctxt(struct qdma_descq_credit_ctxt *cr_ctxt) -{ - credit_ctxt_entries[0].value = cr_ctxt->credit; -} - -/* - * qdma_acc_fill_pfetch_ctxt() - Helper function to fill Prefetch context - * into structure - * - */ -static void qdma_fill_pfetch_ctxt(struct qdma_descq_prefetch_ctxt *pfetch_ctxt) -{ - c2h_pftch_ctxt_entries[0].value = pfetch_ctxt->bypass; - c2h_pftch_ctxt_entries[1].value = pfetch_ctxt->bufsz_idx; - c2h_pftch_ctxt_entries[2].value = pfetch_ctxt->port_id; - c2h_pftch_ctxt_entries[3].value = pfetch_ctxt->err; - c2h_pftch_ctxt_entries[4].value = pfetch_ctxt->pfch_en; - c2h_pftch_ctxt_entries[5].value = pfetch_ctxt->pfch; - c2h_pftch_ctxt_entries[6].value = pfetch_ctxt->sw_crdt; - c2h_pftch_ctxt_entries[7].value = pfetch_ctxt->valid; -} - -/* - * dump_soft_context() - Helper function to dump queue context into string - * - * return len - length of the string copied into buffer - */ -static int dump_soft_context(struct qdma_descq_context *queue_context, - uint8_t st, enum qdma_dev_q_type q_type, - char *buf, int buf_sz) -{ - int i = 0; - int n; - int len = 0; - int rv; - char banner[DEBGFS_LINE_SZ]; - - if (queue_context == NULL) { - qdma_log_error("%s: queue_context is NULL, err:%d\n", - __func__, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - if (q_type == QDMA_DEV_Q_TYPE_CMPT) { - qdma_fill_cmpt_ctxt(&queue_context->cmpt_ctxt); - } else if (q_type == QDMA_DEV_Q_TYPE_H2C) { - qdma_fill_sw_ctxt(&queue_context->sw_ctxt); - qdma_fill_hw_ctxt(&queue_context->hw_ctxt); - qdma_fill_credit_ctxt(&queue_context->cr_ctxt); - } else if (q_type == QDMA_DEV_Q_TYPE_C2H) { - qdma_fill_sw_ctxt(&queue_context->sw_ctxt); - qdma_fill_hw_ctxt(&queue_context->hw_ctxt); - qdma_fill_credit_ctxt(&queue_context->cr_ctxt); - if (st) { - qdma_fill_pfetch_ctxt(&queue_context->pfetch_ctxt); - qdma_fill_cmpt_ctxt(&queue_context->cmpt_ctxt); - } - } - - for (i = 0; i < DEBGFS_LINE_SZ - 5; i++) { - rv = QDMA_SNPRINTF_S(banner + i, - (DEBGFS_LINE_SZ - i), - sizeof("-"), "-"); - if ((rv < 0) || (rv > (int)sizeof("-"))) { - qdma_log_error( - "%d:%s QDMA_SNPRINTF_S() failed, err:%d\n", - __LINE__, __func__, - rv); - goto INSUF_BUF_EXIT; - } - } - - if (q_type != QDMA_DEV_Q_TYPE_CMPT) { - /* SW context dump */ - n = sizeof(sw_ctxt_entries) / sizeof((sw_ctxt_entries)[0]); - for (i = 0; i < n; i++) { - if ((len >= buf_sz) || - ((len + DEBGFS_LINE_SZ) >= buf_sz)) - goto INSUF_BUF_EXIT; - - if (i == 0) { - if ((len + (3 * DEBGFS_LINE_SZ)) >= buf_sz) - goto INSUF_BUF_EXIT; - rv = QDMA_SNPRINTF_S(buf + len, (buf_sz - len), - DEBGFS_LINE_SZ, "\n%s", banner); - if ((rv < 0) || (rv > DEBGFS_LINE_SZ)) { - qdma_log_error( - "%d:%s QDMA_SNPRINTF_S() failed, err:%d\n", - __LINE__, __func__, - rv); - goto INSUF_BUF_EXIT; - } - len += rv; - - rv = QDMA_SNPRINTF_S(buf + len, (buf_sz - len), - DEBGFS_LINE_SZ, "\n%40s", "SW Context"); - if ((rv < 0) || (rv > DEBGFS_LINE_SZ)) { - qdma_log_error( - "%d:%s QDMA_SNPRINTF_S() failed, err:%d\n", - __LINE__, __func__, - rv); - goto INSUF_BUF_EXIT; - } - len += rv; - - rv = QDMA_SNPRINTF_S(buf + len, (buf_sz - len), - DEBGFS_LINE_SZ, "\n%s\n", banner); - if ((rv < 0) || (rv > DEBGFS_LINE_SZ)) { - qdma_log_error( - "%d:%s QDMA_SNPRINTF_S() failed, err:%d\n", - __LINE__, __func__, - rv); - goto INSUF_BUF_EXIT; - } - len += rv; - } - - rv = QDMA_SNPRINTF_S(buf + len, - (buf_sz - len), DEBGFS_LINE_SZ, - "%-47s %#-10x %u\n", - sw_ctxt_entries[i].name, - sw_ctxt_entries[i].value, - sw_ctxt_entries[i].value); - if ((rv < 0) || (rv > DEBGFS_LINE_SZ)) { - qdma_log_error( - "%d:%s QDMA_SNPRINTF_S() failed, err:%d\n", - __LINE__, __func__, - rv); - goto INSUF_BUF_EXIT; - } - len += rv; - } - - /* HW context dump */ - n = sizeof(hw_ctxt_entries) / sizeof((hw_ctxt_entries)[0]); - for (i = 0; i < n; i++) { - if ((len >= buf_sz) || - ((len + DEBGFS_LINE_SZ) >= buf_sz)) - goto INSUF_BUF_EXIT; - - if (i == 0) { - if ((len + (3 * DEBGFS_LINE_SZ)) >= buf_sz) - goto INSUF_BUF_EXIT; - - rv = QDMA_SNPRINTF_S(buf + len, (buf_sz - len), - DEBGFS_LINE_SZ, "\n%s", banner); - if ((rv < 0) || (rv > DEBGFS_LINE_SZ)) { - qdma_log_error( - "%d:%s QDMA_SNPRINTF_S() failed, err:%d\n", - __LINE__, __func__, - rv); - goto INSUF_BUF_EXIT; - } - len += rv; - - rv = QDMA_SNPRINTF_S(buf + len, (buf_sz - len), - DEBGFS_LINE_SZ, "\n%40s", "HW Context"); - if ((rv < 0) || (rv > DEBGFS_LINE_SZ)) { - qdma_log_error( - "%d:%s QDMA_SNPRINTF_S() failed, err:%d\n", - __LINE__, __func__, - rv); - goto INSUF_BUF_EXIT; - } - len += rv; - - rv = QDMA_SNPRINTF_S(buf + len, (buf_sz - len), - DEBGFS_LINE_SZ, "\n%s\n", banner); - if ((rv < 0) || (rv > DEBGFS_LINE_SZ)) { - qdma_log_error( - "%d:%s QDMA_SNPRINTF_S() failed, err:%d\n", - __LINE__, __func__, - rv); - goto INSUF_BUF_EXIT; - } - len += rv; - } - - rv = QDMA_SNPRINTF_S(buf + len, - (buf_sz - len), DEBGFS_LINE_SZ, - "%-47s %#-10x %u\n", - hw_ctxt_entries[i].name, - hw_ctxt_entries[i].value, - hw_ctxt_entries[i].value); - if ((rv < 0) || (rv > DEBGFS_LINE_SZ)) { - qdma_log_error( - "%d:%s QDMA_SNPRINTF_S() failed, err:%d\n", - __LINE__, __func__, - rv); - goto INSUF_BUF_EXIT; - } - len += rv; - } - - /* Credit context dump */ - n = sizeof(credit_ctxt_entries) / - sizeof((credit_ctxt_entries)[0]); - for (i = 0; i < n; i++) { - if ((len >= buf_sz) || - ((len + DEBGFS_LINE_SZ) >= buf_sz)) - goto INSUF_BUF_EXIT; - - if (i == 0) { - if ((len + (3 * DEBGFS_LINE_SZ)) >= buf_sz) - goto INSUF_BUF_EXIT; - - rv = QDMA_SNPRINTF_S(buf + len, (buf_sz - len), - DEBGFS_LINE_SZ, "\n%s", banner); - if ((rv < 0) || (rv > DEBGFS_LINE_SZ)) { - qdma_log_error( - "%d:%s QDMA_SNPRINTF_S() failed, err:%d\n", - __LINE__, __func__, - rv); - goto INSUF_BUF_EXIT; - } - len += rv; - - rv = QDMA_SNPRINTF_S(buf + len, (buf_sz - len), - DEBGFS_LINE_SZ, "\n%40s", - "Credit Context"); - if ((rv < 0) || (rv > DEBGFS_LINE_SZ)) { - qdma_log_error( - "%d:%s QDMA_SNPRINTF_S() failed, err:%d\n", - __LINE__, __func__, - rv); - goto INSUF_BUF_EXIT; - } - len += rv; - - rv = QDMA_SNPRINTF_S(buf + len, (buf_sz - len), - DEBGFS_LINE_SZ, "\n%s\n", banner); - if ((rv < 0) || (rv > DEBGFS_LINE_SZ)) { - qdma_log_error( - "%d:%s QDMA_SNPRINTF_S() failed, err:%d\n", - __LINE__, __func__, - rv); - goto INSUF_BUF_EXIT; - } - len += rv; - } - - rv = QDMA_SNPRINTF_S(buf + len, - (buf_sz - len), DEBGFS_LINE_SZ, - "%-47s %#-10x %u\n", - credit_ctxt_entries[i].name, - credit_ctxt_entries[i].value, - credit_ctxt_entries[i].value); - if ((rv < 0) || (rv > DEBGFS_LINE_SZ)) { - qdma_log_error( - "%d:%s QDMA_SNPRINTF_S() failed, err:%d\n", - __LINE__, __func__, - rv); - goto INSUF_BUF_EXIT; - } - len += rv; - } - } - - if ((q_type == QDMA_DEV_Q_TYPE_CMPT) || - (st && q_type == QDMA_DEV_Q_TYPE_C2H)) { - /* Completion context dump */ - n = sizeof(cmpt_ctxt_entries) / sizeof((cmpt_ctxt_entries)[0]); - for (i = 0; i < n; i++) { - if ((len >= buf_sz) || - ((len + DEBGFS_LINE_SZ) >= buf_sz)) - goto INSUF_BUF_EXIT; - - if (i == 0) { - if ((len + (3 * DEBGFS_LINE_SZ)) >= buf_sz) - goto INSUF_BUF_EXIT; - - rv = QDMA_SNPRINTF_S(buf + len, (buf_sz - len), - DEBGFS_LINE_SZ, "\n%s", banner); - if ((rv < 0) || (rv > DEBGFS_LINE_SZ)) { - qdma_log_error( - "%d:%s QDMA_SNPRINTF_S() failed, err:%d\n", - __LINE__, __func__, - rv); - goto INSUF_BUF_EXIT; - } - len += rv; - - rv = QDMA_SNPRINTF_S(buf + len, (buf_sz - len), - DEBGFS_LINE_SZ, "\n%40s", - "Completion Context"); - if ((rv < 0) || (rv > DEBGFS_LINE_SZ)) { - qdma_log_error( - "%d:%s QDMA_SNPRINTF_S() failed, err:%d\n", - __LINE__, __func__, - rv); - goto INSUF_BUF_EXIT; - } - len += rv; - - rv = QDMA_SNPRINTF_S(buf + len, (buf_sz - len), - DEBGFS_LINE_SZ, "\n%s\n", banner); - if ((rv < 0) || (rv > DEBGFS_LINE_SZ)) { - qdma_log_error( - "%d:%s QDMA_SNPRINTF_S() failed, err:%d\n", - __LINE__, __func__, - rv); - goto INSUF_BUF_EXIT; - } - len += rv; - } - - rv = QDMA_SNPRINTF_S(buf + len, - (buf_sz - len), DEBGFS_LINE_SZ, - "%-47s %#-10x %u\n", - cmpt_ctxt_entries[i].name, - cmpt_ctxt_entries[i].value, - cmpt_ctxt_entries[i].value); - if ((rv < 0) || (rv > DEBGFS_LINE_SZ)) { - qdma_log_error( - "%d:%s QDMA_SNPRINTF_S() failed, err:%d\n", - __LINE__, __func__, - rv); - goto INSUF_BUF_EXIT; - } - len += rv; - } - } - - if (st && q_type == QDMA_DEV_Q_TYPE_C2H) { - /* Prefetch context dump */ - n = sizeof(c2h_pftch_ctxt_entries) / - sizeof(c2h_pftch_ctxt_entries[0]); - for (i = 0; i < n; i++) { - if ((len >= buf_sz) || - ((len + DEBGFS_LINE_SZ) >= buf_sz)) - goto INSUF_BUF_EXIT; - - if (i == 0) { - if ((len + (3 * DEBGFS_LINE_SZ)) >= buf_sz) - goto INSUF_BUF_EXIT; - - rv = QDMA_SNPRINTF_S(buf + len, (buf_sz - len), - DEBGFS_LINE_SZ, "\n%s", banner); - if ((rv < 0) || (rv > DEBGFS_LINE_SZ)) { - qdma_log_error( - "%d:%s QDMA_SNPRINTF_S() failed, err:%d\n", - __LINE__, __func__, - rv); - goto INSUF_BUF_EXIT; - } - len += rv; - - rv = QDMA_SNPRINTF_S(buf + len, (buf_sz - len), - DEBGFS_LINE_SZ, "\n%40s", - "Prefetch Context"); - if ((rv < 0) || (rv > DEBGFS_LINE_SZ)) { - qdma_log_error( - "%d:%s QDMA_SNPRINTF_S() failed, err:%d\n", - __LINE__, __func__, - rv); - goto INSUF_BUF_EXIT; - } - len += rv; - - rv = QDMA_SNPRINTF_S(buf + len, (buf_sz - len), - DEBGFS_LINE_SZ, "\n%s\n", banner); - if ((rv < 0) || (rv > DEBGFS_LINE_SZ)) { - qdma_log_error( - "%d:%s QDMA_SNPRINTF_S() failed, err:%d\n", - __LINE__, __func__, - rv); - goto INSUF_BUF_EXIT; - } - len += rv; - } - - rv = QDMA_SNPRINTF_S(buf + len, - (buf_sz - len), DEBGFS_LINE_SZ, - "%-47s %#-10x %u\n", - c2h_pftch_ctxt_entries[i].name, - c2h_pftch_ctxt_entries[i].value, - c2h_pftch_ctxt_entries[i].value); - if ((rv < 0) || (rv > DEBGFS_LINE_SZ)) { - qdma_log_error( - "%d:%s QDMA_SNPRINTF_S() failed, err:%d\n", - __LINE__, __func__, - rv); - goto INSUF_BUF_EXIT; - } - len += rv; - } - } - - return len; - -INSUF_BUF_EXIT: - if (buf_sz > DEBGFS_LINE_SZ) { - rv = QDMA_SNPRINTF_S((buf + buf_sz - DEBGFS_LINE_SZ), - buf_sz, DEBGFS_LINE_SZ, - "\n\nInsufficient buffer size, partial context dump\n"); - if ((rv < 0) || (rv > DEBGFS_LINE_SZ)) { - qdma_log_error( - "%d:%s QDMA_SNPRINTF_S() failed, err:%d\n", - __LINE__, __func__, - rv); - } - } - - qdma_log_error("%s: Insufficient buffer size, err:%d\n", - __func__, -QDMA_ERR_NO_MEM); - - return -QDMA_ERR_NO_MEM; -} - -/* - * qdma_indirect_reg_invalidate() - helper function to invalidate indirect - * context registers. - * - * return -QDMA_ERR_HWACC_BUSY_TIMEOUT if register - * value didn't match, QDMA_SUCCESS other wise - */ -static int qdma_indirect_reg_invalidate(void *dev_hndl, - enum ind_ctxt_cmd_sel sel, uint16_t hw_qid) -{ - union qdma_ind_ctxt_cmd cmd; - - qdma_reg_access_lock(dev_hndl); - - /* set command register */ - cmd.word = 0; - cmd.bits.qid = hw_qid; - cmd.bits.op = QDMA_CTXT_CMD_INV; - cmd.bits.sel = sel; - qdma_reg_write(dev_hndl, QDMA_OFFSET_IND_CTXT_CMD, cmd.word); - - /* check if the operation went through well */ - if (hw_monitor_reg(dev_hndl, QDMA_OFFSET_IND_CTXT_CMD, - QDMA_IND_CTXT_CMD_BUSY_MASK, 0, - QDMA_REG_POLL_DFLT_INTERVAL_US, - QDMA_REG_POLL_DFLT_TIMEOUT_US)) { - qdma_reg_access_release(dev_hndl); - qdma_log_error("%s: hw_monitor_reg failed with err:%d\n", - __func__, - -QDMA_ERR_HWACC_BUSY_TIMEOUT); - return -QDMA_ERR_HWACC_BUSY_TIMEOUT; - } - - qdma_reg_access_release(dev_hndl); - - return QDMA_SUCCESS; -} - -/* - * qdma_indirect_reg_clear() - helper function to clear indirect - * context registers. - * - * return -QDMA_ERR_HWACC_BUSY_TIMEOUT if register - * value didn't match, QDMA_SUCCESS other wise - */ -static int qdma_indirect_reg_clear(void *dev_hndl, - enum ind_ctxt_cmd_sel sel, uint16_t hw_qid) -{ - union qdma_ind_ctxt_cmd cmd; - - qdma_reg_access_lock(dev_hndl); - - /* set command register */ - cmd.word = 0; - cmd.bits.qid = hw_qid; - cmd.bits.op = QDMA_CTXT_CMD_CLR; - cmd.bits.sel = sel; - qdma_reg_write(dev_hndl, QDMA_OFFSET_IND_CTXT_CMD, cmd.word); - - /* check if the operation went through well */ - if (hw_monitor_reg(dev_hndl, QDMA_OFFSET_IND_CTXT_CMD, - QDMA_IND_CTXT_CMD_BUSY_MASK, 0, - QDMA_REG_POLL_DFLT_INTERVAL_US, - QDMA_REG_POLL_DFLT_TIMEOUT_US)) { - qdma_reg_access_release(dev_hndl); - qdma_log_error("%s: hw_monitor_reg failed with err:%d\n", - __func__, - -QDMA_ERR_HWACC_BUSY_TIMEOUT); - return -QDMA_ERR_HWACC_BUSY_TIMEOUT; - } - - qdma_reg_access_release(dev_hndl); - - return QDMA_SUCCESS; -} - -/* - * qdma_indirect_reg_read() - helper function to read indirect - * context registers. - * - * return -QDMA_ERR_HWACC_BUSY_TIMEOUT if register - * value didn't match, QDMA_SUCCESS other wise - */ -static int qdma_indirect_reg_read(void *dev_hndl, enum ind_ctxt_cmd_sel sel, - uint16_t hw_qid, uint32_t cnt, uint32_t *data) -{ - uint32_t index = 0, reg_addr = QDMA_OFFSET_IND_CTXT_DATA; - union qdma_ind_ctxt_cmd cmd; - - qdma_reg_access_lock(dev_hndl); - - /* set command register */ - cmd.word = 0; - cmd.bits.qid = hw_qid; - cmd.bits.op = QDMA_CTXT_CMD_RD; - cmd.bits.sel = sel; - qdma_reg_write(dev_hndl, QDMA_OFFSET_IND_CTXT_CMD, cmd.word); - - /* check if the operation went through well */ - if (hw_monitor_reg(dev_hndl, QDMA_OFFSET_IND_CTXT_CMD, - QDMA_IND_CTXT_CMD_BUSY_MASK, 0, - QDMA_REG_POLL_DFLT_INTERVAL_US, - QDMA_REG_POLL_DFLT_TIMEOUT_US)) { - qdma_reg_access_release(dev_hndl); - qdma_log_error("%s: hw_monitor_reg failed with err:%d\n", - __func__, - -QDMA_ERR_HWACC_BUSY_TIMEOUT); - return -QDMA_ERR_HWACC_BUSY_TIMEOUT; - } - - for (index = 0; index < cnt; index++, reg_addr += sizeof(uint32_t)) - data[index] = qdma_reg_read(dev_hndl, reg_addr); - - qdma_reg_access_release(dev_hndl); - - return QDMA_SUCCESS; -} - -/* - * qdma_indirect_reg_write() - helper function to write indirect - * context registers. - * - * return -QDMA_ERR_HWACC_BUSY_TIMEOUT if register - * value didn't match, QDMA_SUCCESS other wise - */ -static int qdma_indirect_reg_write(void *dev_hndl, enum ind_ctxt_cmd_sel sel, - uint16_t hw_qid, uint32_t *data, uint16_t cnt) -{ - uint32_t index, reg_addr; - struct qdma_indirect_ctxt_regs regs; - uint32_t *wr_data = (uint32_t *)®s; - - qdma_reg_access_lock(dev_hndl); - - /* write the context data */ - for (index = 0; index < QDMA_IND_CTXT_DATA_NUM_REGS; index++) { - if (index < cnt) - regs.qdma_ind_ctxt_data[index] = data[index]; - else - regs.qdma_ind_ctxt_data[index] = 0; - regs.qdma_ind_ctxt_mask[index] = 0xFFFFFFFF; - } - - regs.cmd.word = 0; - regs.cmd.bits.qid = hw_qid; - regs.cmd.bits.op = QDMA_CTXT_CMD_WR; - regs.cmd.bits.sel = sel; - reg_addr = QDMA_OFFSET_IND_CTXT_DATA; - - for (index = 0; index < ((2 * QDMA_IND_CTXT_DATA_NUM_REGS) + 1); - index++, reg_addr += sizeof(uint32_t)) - qdma_reg_write(dev_hndl, reg_addr, wr_data[index]); - - /* check if the operation went through well */ - if (hw_monitor_reg(dev_hndl, QDMA_OFFSET_IND_CTXT_CMD, - QDMA_IND_CTXT_CMD_BUSY_MASK, 0, - QDMA_REG_POLL_DFLT_INTERVAL_US, - QDMA_REG_POLL_DFLT_TIMEOUT_US)) { - qdma_reg_access_release(dev_hndl); - qdma_log_error("%s: hw_monitor_reg failed with err:%d\n", - __func__, - -QDMA_ERR_HWACC_BUSY_TIMEOUT); - return -QDMA_ERR_HWACC_BUSY_TIMEOUT; - } - - qdma_reg_access_release(dev_hndl); - - return QDMA_SUCCESS; -} - -/*****************************************************************************/ -/** - * qdma_get_version() - Function to get the qdma version - * - * @dev_hndl: device handle - * @is_vf: Whether PF or VF - * @version_info: pointer to hold the version info - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -int qdma_get_version(void *dev_hndl, uint8_t is_vf, - struct qdma_hw_version_info *version_info) -{ - uint32_t reg_val = 0; - uint32_t reg_addr = (is_vf) ? QDMA_OFFSET_VF_VERSION : - QDMA_OFFSET_GLBL2_MISC_CAP; - - if (!dev_hndl) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - reg_val = qdma_reg_read(dev_hndl, reg_addr); - - qdma_fetch_version_details(is_vf, reg_val, version_info); - - return QDMA_SUCCESS; -} - -/*****************************************************************************/ -/** - * qdma_fmap_write() - create fmap context and program it - * - * @dev_hndl: device handle - * @func_id: function id of the device - * @config: pointer to the fmap data strucutre - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -static int qdma_fmap_write(void *dev_hndl, uint16_t func_id, - const struct qdma_fmap_cfg *config) -{ - uint32_t fmap[QDMA_FMAP_NUM_WORDS] = {0}; - uint16_t num_words_count = 0; - enum ind_ctxt_cmd_sel sel = QDMA_CTXT_SEL_FMAP; - - if (!dev_hndl || !config) { - qdma_log_error("%s: dev_handle=%p fmap=%p NULL, err:%d\n", - __func__, dev_hndl, config, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - qdma_log_debug("%s: func_id=%hu, qbase=%hu, qmax=%hu\n", __func__, - func_id, config->qbase, config->qmax); - fmap[num_words_count++] = - FIELD_SET(QDMA_FMAP_CTXT_W0_QID_MASK, config->qbase); - fmap[num_words_count++] = - FIELD_SET(QDMA_FMAP_CTXT_W1_QID_MAX_MASK, config->qmax); - - return qdma_indirect_reg_write(dev_hndl, sel, func_id, - fmap, num_words_count); -} - -/*****************************************************************************/ -/** - * qdma_fmap_read() - read fmap context - * - * @dev_hndl: device handle - * @func_id: function id of the device - * @config: pointer to the output fmap data - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -static int qdma_fmap_read(void *dev_hndl, uint16_t func_id, - struct qdma_fmap_cfg *config) -{ - int rv = QDMA_SUCCESS; - uint32_t fmap[QDMA_FMAP_NUM_WORDS] = {0}; - enum ind_ctxt_cmd_sel sel = QDMA_CTXT_SEL_FMAP; - - if (!dev_hndl || !config) { - qdma_log_error("%s: dev_handle=%p fmap=%p NULL, err:%d\n", - __func__, dev_hndl, config, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - rv = qdma_indirect_reg_read(dev_hndl, sel, func_id, - QDMA_FMAP_NUM_WORDS, fmap); - if (rv < 0) - return rv; - - config->qbase = FIELD_GET(QDMA_FMAP_CTXT_W0_QID_MASK, fmap[0]); - config->qmax = FIELD_GET(QDMA_FMAP_CTXT_W1_QID_MAX_MASK, fmap[1]); - - qdma_log_debug("%s: func_id=%hu, qbase=%hu, qmax=%hu\n", __func__, - func_id, config->qbase, config->qmax); - return QDMA_SUCCESS; -} - -/*****************************************************************************/ -/** - * qdma_fmap_clear() - clear fmap context - * - * @dev_hndl: device handle - * @func_id: function id of the device - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -static int qdma_fmap_clear(void *dev_hndl, uint16_t func_id) -{ - enum ind_ctxt_cmd_sel sel = QDMA_CTXT_SEL_FMAP; - - if (!dev_hndl) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", __func__, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - qdma_log_debug("%s: func_id=%hu\n", __func__, func_id); - return qdma_indirect_reg_clear(dev_hndl, sel, func_id); -} - -/*****************************************************************************/ -/** - * qdma_fmap_conf() - configure fmap context - * - * @dev_hndl: device handle - * @func_id: function id of the device - * @config: pointer to the fmap data - * @access_type HW access type (qdma_hw_access_type enum) value - * QDMA_HW_ACCESS_INVALIDATE Not supported - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -int qdma_fmap_conf(void *dev_hndl, uint16_t func_id, - struct qdma_fmap_cfg *config, - enum qdma_hw_access_type access_type) -{ - int rv = QDMA_SUCCESS; - - switch (access_type) { - case QDMA_HW_ACCESS_READ: - rv = qdma_fmap_read(dev_hndl, func_id, config); - break; - case QDMA_HW_ACCESS_WRITE: - rv = qdma_fmap_write(dev_hndl, func_id, config); - break; - case QDMA_HW_ACCESS_CLEAR: - rv = qdma_fmap_clear(dev_hndl, func_id); - break; - case QDMA_HW_ACCESS_INVALIDATE: - default: - qdma_log_error("%s: access_type(%d) invalid, err:%d\n", - __func__, - access_type, - -QDMA_ERR_INV_PARAM); - rv = -QDMA_ERR_INV_PARAM; - break; - } - - return rv; -} - -/*****************************************************************************/ -/** - * qdma_sw_context_write() - create sw context and program it - * - * @dev_hndl: device handle - * @c2h: is c2h queue - * @hw_qid: hardware qid of the queue - * @ctxt: pointer to the SW context data strucutre - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -static int qdma_sw_context_write(void *dev_hndl, uint8_t c2h, - uint16_t hw_qid, - const struct qdma_descq_sw_ctxt *ctxt) -{ - uint32_t sw_ctxt[QDMA_SW_CONTEXT_NUM_WORDS] = {0}; - uint16_t num_words_count = 0; - enum ind_ctxt_cmd_sel sel = c2h ? - QDMA_CTXT_SEL_SW_C2H : QDMA_CTXT_SEL_SW_H2C; - - /* Input args check */ - if (!dev_hndl || !ctxt) { - qdma_log_error("%s: dev_handle=%p sw_ctxt=%p NULL, err:%d\n", - __func__, dev_hndl, ctxt, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - sw_ctxt[num_words_count++] = - FIELD_SET(QDMA_SW_CTXT_W0_PIDX, ctxt->pidx) | - FIELD_SET(QDMA_SW_CTXT_W0_IRQ_ARM_MASK, ctxt->irq_arm) | - FIELD_SET(QDMA_SW_CTXT_W0_FUNC_ID_MASK, ctxt->fnc_id); - - qdma_log_debug("%s: pidx=%x, irq_arm=%x, fnc_id=%x\n", - __func__, ctxt->pidx, ctxt->irq_arm, ctxt->fnc_id); - - sw_ctxt[num_words_count++] = - FIELD_SET(QDMA_SW_CTXT_W1_QEN_MASK, ctxt->qen) | - FIELD_SET(QDMA_SW_CTXT_W1_FCRD_EN_MASK, ctxt->frcd_en) | - FIELD_SET(QDMA_SW_CTXT_W1_WBI_CHK_MASK, ctxt->wbi_chk) | - FIELD_SET(QDMA_SW_CTXT_W1_WB_INT_EN_MASK, ctxt->wbi_intvl_en) | - FIELD_SET(QDMA_SW_CTXT_W1_AT_MASK, ctxt->at) | - FIELD_SET(QDMA_SW_CTXT_W1_FETCH_MAX_MASK, ctxt->fetch_max) | - FIELD_SET(QDMA_SW_CTXT_W1_RNG_SZ_MASK, ctxt->rngsz_idx) | - FIELD_SET(QDMA_SW_CTXT_W1_DSC_SZ_MASK, ctxt->desc_sz) | - FIELD_SET(QDMA_SW_CTXT_W1_BYP_MASK, ctxt->bypass) | - FIELD_SET(QDMA_SW_CTXT_W1_MM_CHN_MASK, ctxt->mm_chn) | - FIELD_SET(QDMA_SW_CTXT_W1_WBK_EN_MASK, ctxt->wbk_en) | - FIELD_SET(QDMA_SW_CTXT_W1_IRQ_EN_MASK, ctxt->irq_en) | - FIELD_SET(QDMA_SW_CTXT_W1_PORT_ID_MASK, ctxt->port_id) | - FIELD_SET(QDMA_SW_CTXT_W1_IRQ_NO_LAST_MASK, ctxt->irq_no_last) | - FIELD_SET(QDMA_SW_CTXT_W1_ERR_MASK, ctxt->err) | - FIELD_SET(QDMA_SW_CTXT_W1_ERR_WB_SENT_MASK, ctxt->err_wb_sent) | - FIELD_SET(QDMA_SW_CTXT_W1_IRQ_REQ_MASK, ctxt->irq_req) | - FIELD_SET(QDMA_SW_CTXT_W1_MRKR_DIS_MASK, ctxt->mrkr_dis) | - FIELD_SET(QDMA_SW_CTXT_W1_IS_MM_MASK, ctxt->is_mm); - - qdma_log_debug("%s: qen=%x, frcd_en=%x, wbi_chk=%x, wbi_intvl_en=%x\n", - __func__, ctxt->qen, ctxt->frcd_en, ctxt->wbi_chk, - ctxt->wbi_intvl_en); - - qdma_log_debug("%s: at=%x, fetch_max=%x, rngsz_idx=%x, desc_sz=%x\n", - __func__, ctxt->at, ctxt->fetch_max, ctxt->rngsz_idx, - ctxt->desc_sz); - - qdma_log_debug("%s: bypass=%x, mm_chn=%x, wbk_en=%x, irq_en=%x\n", - __func__, ctxt->bypass, ctxt->mm_chn, ctxt->wbk_en, - ctxt->irq_en); - - qdma_log_debug("%s: port_id=%x, irq_no_last=%x,err=%x", - __func__, ctxt->port_id, ctxt->irq_no_last, ctxt->err); - qdma_log_debug(", err_wb_sent=%x\n", ctxt->err_wb_sent); - - qdma_log_debug("%s: irq_req=%x, mrkr_dis=%x, is_mm=%x\n", - __func__, ctxt->irq_req, ctxt->mrkr_dis, ctxt->is_mm); - - sw_ctxt[num_words_count++] = ctxt->ring_bs_addr & 0xffffffff; - sw_ctxt[num_words_count++] = (ctxt->ring_bs_addr >> 32) & 0xffffffff; - - sw_ctxt[num_words_count++] = - FIELD_SET(QDMA_SW_CTXT_W4_VEC_MASK, ctxt->vec) | - FIELD_SET(QDMA_SW_CTXT_W4_INTR_AGGR_MASK, ctxt->intr_aggr); - - qdma_log_debug("%s: vec=%x, intr_aggr=%x\n", - __func__, ctxt->vec, ctxt->intr_aggr); - - return qdma_indirect_reg_write(dev_hndl, sel, hw_qid, - sw_ctxt, num_words_count); -} - -/*****************************************************************************/ -/** - * qdma_sw_context_read() - read sw context - * - * @dev_hndl: device handle - * @c2h: is c2h queue - * @hw_qid: hardware qid of the queue - * @ctxt: pointer to the output context data - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -static int qdma_sw_context_read(void *dev_hndl, uint8_t c2h, - uint16_t hw_qid, - struct qdma_descq_sw_ctxt *ctxt) -{ - int rv = QDMA_SUCCESS; - uint32_t sw_ctxt[QDMA_SW_CONTEXT_NUM_WORDS] = {0}; - enum ind_ctxt_cmd_sel sel = c2h ? - QDMA_CTXT_SEL_SW_C2H : QDMA_CTXT_SEL_SW_H2C; - - if (!dev_hndl || !ctxt) { - qdma_log_error("%s: dev_handle=%p sw_ctxt=%p NULL, err:%d\n", - __func__, dev_hndl, ctxt, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - rv = qdma_indirect_reg_read(dev_hndl, sel, hw_qid, - QDMA_SW_CONTEXT_NUM_WORDS, sw_ctxt); - if (rv < 0) - return rv; - - ctxt->pidx = FIELD_GET(QDMA_SW_CTXT_W0_PIDX, sw_ctxt[0]); - ctxt->irq_arm = - (uint8_t)(FIELD_GET(QDMA_SW_CTXT_W0_IRQ_ARM_MASK, sw_ctxt[0])); - ctxt->fnc_id = - (uint8_t)(FIELD_GET(QDMA_SW_CTXT_W0_FUNC_ID_MASK, sw_ctxt[0])); - - qdma_log_debug("%s: pidx=%x, irq_arm=%x, fnc_id=%x", - __func__, ctxt->pidx, ctxt->irq_arm, ctxt->fnc_id); - - ctxt->qen = FIELD_GET(QDMA_SW_CTXT_W1_QEN_MASK, sw_ctxt[1]); - ctxt->frcd_en = FIELD_GET(QDMA_SW_CTXT_W1_FCRD_EN_MASK, sw_ctxt[1]); - ctxt->wbi_chk = FIELD_GET(QDMA_SW_CTXT_W1_WBI_CHK_MASK, sw_ctxt[1]); - ctxt->wbi_intvl_en = - FIELD_GET(QDMA_SW_CTXT_W1_WB_INT_EN_MASK, sw_ctxt[1]); - ctxt->at = FIELD_GET(QDMA_SW_CTXT_W1_AT_MASK, sw_ctxt[1]); - ctxt->fetch_max = - FIELD_GET(QDMA_SW_CTXT_W1_FETCH_MAX_MASK, sw_ctxt[1]); - ctxt->rngsz_idx = - (uint8_t)(FIELD_GET(QDMA_SW_CTXT_W1_RNG_SZ_MASK, sw_ctxt[1])); - ctxt->desc_sz = - (uint8_t)(FIELD_GET(QDMA_SW_CTXT_W1_DSC_SZ_MASK, sw_ctxt[1])); - ctxt->bypass = - (uint8_t)(FIELD_GET(QDMA_SW_CTXT_W1_BYP_MASK, sw_ctxt[1])); - ctxt->mm_chn = - (uint8_t)(FIELD_GET(QDMA_SW_CTXT_W1_MM_CHN_MASK, sw_ctxt[1])); - ctxt->wbk_en = - (uint8_t)(FIELD_GET(QDMA_SW_CTXT_W1_WBK_EN_MASK, sw_ctxt[1])); - ctxt->irq_en = - (uint8_t)(FIELD_GET(QDMA_SW_CTXT_W1_IRQ_EN_MASK, sw_ctxt[1])); - ctxt->port_id = - (uint8_t)(FIELD_GET(QDMA_SW_CTXT_W1_PORT_ID_MASK, sw_ctxt[1])); - ctxt->irq_no_last = - (uint8_t)(FIELD_GET(QDMA_SW_CTXT_W1_IRQ_NO_LAST_MASK, - sw_ctxt[1])); - ctxt->err = - (uint8_t)(FIELD_GET(QDMA_SW_CTXT_W1_ERR_MASK, sw_ctxt[1])); - ctxt->err_wb_sent = - (uint8_t)(FIELD_GET(QDMA_SW_CTXT_W1_ERR_WB_SENT_MASK, - sw_ctxt[1])); - ctxt->irq_req = - (uint8_t)(FIELD_GET(QDMA_SW_CTXT_W1_IRQ_REQ_MASK, sw_ctxt[1])); - ctxt->mrkr_dis = - (uint8_t)(FIELD_GET(QDMA_SW_CTXT_W1_MRKR_DIS_MASK, sw_ctxt[1])); - ctxt->is_mm = - (uint8_t)(FIELD_GET(QDMA_SW_CTXT_W1_IS_MM_MASK, sw_ctxt[1])); - - qdma_log_debug("%s: qen=%x, frcd_en=%x, wbi_chk=%x, wbi_intvl_en=%x\n", - __func__, ctxt->qen, ctxt->frcd_en, ctxt->wbi_chk, - ctxt->wbi_intvl_en); - qdma_log_debug("%s: at=%x, fetch_max=%x, rngsz_idx=%x, desc_sz=%x\n", - __func__, ctxt->at, ctxt->fetch_max, ctxt->rngsz_idx, - ctxt->desc_sz); - qdma_log_debug("%s: bypass=%x, mm_chn=%x, wbk_en=%x, irq_en=%x\n", - __func__, ctxt->bypass, ctxt->mm_chn, ctxt->wbk_en, - ctxt->irq_en); - qdma_log_debug("%s: port_id=%x, irq_no_last=%x,", - __func__, ctxt->port_id, ctxt->irq_no_last); - qdma_log_debug(" err=%x, err_wb_sent=%x\n", - ctxt->err, ctxt->err_wb_sent); - qdma_log_debug("%s: irq_req=%x, mrkr_dis=%x, is_mm=%x\n", - __func__, ctxt->irq_req, ctxt->mrkr_dis, ctxt->is_mm); - - ctxt->ring_bs_addr = ((uint64_t)sw_ctxt[3] << 32) | (sw_ctxt[2]); - - ctxt->vec = FIELD_GET(QDMA_SW_CTXT_W4_VEC_MASK, sw_ctxt[4]); - ctxt->intr_aggr = - (uint8_t)(FIELD_GET(QDMA_SW_CTXT_W4_INTR_AGGR_MASK, - sw_ctxt[4])); - - qdma_log_debug("%s: vec=%x, intr_aggr=%x\n", - __func__, ctxt->vec, ctxt->intr_aggr); - - return QDMA_SUCCESS; -} - -/*****************************************************************************/ -/** - * qdma_sw_context_clear() - clear sw context - * - * @dev_hndl: device handle - * @c2h: is c2h queue - * @hw_qid: hardware qid of the queue - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -static int qdma_sw_context_clear(void *dev_hndl, uint8_t c2h, - uint16_t hw_qid) -{ - enum ind_ctxt_cmd_sel sel = c2h ? - QDMA_CTXT_SEL_SW_C2H : QDMA_CTXT_SEL_SW_H2C; - - if (!dev_hndl) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", __func__, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - return qdma_indirect_reg_clear(dev_hndl, sel, hw_qid); -} - -/*****************************************************************************/ -/** - * qdma_sw_context_invalidate() - invalidate sw context - * - * @dev_hndl: device handle - * @c2h: is c2h queue - * @hw_qid: hardware qid of the queue - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -static int qdma_sw_context_invalidate(void *dev_hndl, uint8_t c2h, - uint16_t hw_qid) -{ - enum ind_ctxt_cmd_sel sel = c2h ? - QDMA_CTXT_SEL_SW_C2H : QDMA_CTXT_SEL_SW_H2C; - - if (!dev_hndl) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", __func__, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - return qdma_indirect_reg_invalidate(dev_hndl, sel, hw_qid); -} - -/*****************************************************************************/ -/** - * qdma_sw_ctx_conf() - configure SW context - * - * @dev_hndl: device handle - * @c2h: is c2h queue - * @hw_qid: hardware qid of the queue - * @ctxt: pointer to the context data - * @access_type HW access type (qdma_hw_access_type enum) value - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -int qdma_sw_ctx_conf(void *dev_hndl, uint8_t c2h, uint16_t hw_qid, - struct qdma_descq_sw_ctxt *ctxt, - enum qdma_hw_access_type access_type) -{ - int rv = QDMA_SUCCESS; - - /** ctxt requires only H2C-0 or C2H-1 - * return error for any other values - */ - if (c2h > 1) { - qdma_log_error("%s: c2h(%d) invalid, err:%d\n", - __func__, - c2h, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - switch (access_type) { - case QDMA_HW_ACCESS_READ: - rv = qdma_sw_context_read(dev_hndl, c2h, hw_qid, ctxt); - break; - case QDMA_HW_ACCESS_WRITE: - rv = qdma_sw_context_write(dev_hndl, c2h, hw_qid, ctxt); - break; - case QDMA_HW_ACCESS_CLEAR: - rv = qdma_sw_context_clear(dev_hndl, c2h, hw_qid); - break; - case QDMA_HW_ACCESS_INVALIDATE: - rv = qdma_sw_context_invalidate(dev_hndl, c2h, hw_qid); - break; - default: - qdma_log_error("%s: access_type(%d) invalid, err:%d\n", - __func__, - access_type, - -QDMA_ERR_INV_PARAM); - rv = -QDMA_ERR_INV_PARAM; - break; - } - - return rv; -} - -/*****************************************************************************/ -/** - * qdma_pfetch_context_write() - create prefetch context and program it - * - * @dev_hndl: device handle - * @hw_qid: hardware qid of the queue - * @ctxt: pointer to the prefetch context data strucutre - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -static int qdma_pfetch_context_write(void *dev_hndl, uint16_t hw_qid, - const struct qdma_descq_prefetch_ctxt *ctxt) -{ - uint32_t pfetch_ctxt[QDMA_PFETCH_CONTEXT_NUM_WORDS] = {0}; - enum ind_ctxt_cmd_sel sel = QDMA_CTXT_SEL_PFTCH; - uint32_t sw_crdt_l, sw_crdt_h; - uint16_t num_words_count = 0; - - if (!dev_hndl || !ctxt) { - qdma_log_error("%s: dev_handle or pfetch ctxt NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - sw_crdt_l = - FIELD_GET(QDMA_PFTCH_CTXT_SW_CRDT_GET_L_MASK, ctxt->sw_crdt); - sw_crdt_h = - FIELD_GET(QDMA_PFTCH_CTXT_SW_CRDT_GET_H_MASK, ctxt->sw_crdt); - - qdma_log_debug("%s: sw_crdt_l=%u, sw_crdt_h=%u, hw_qid=%hu\n", - __func__, sw_crdt_l, sw_crdt_h, hw_qid); - - pfetch_ctxt[num_words_count++] = - FIELD_SET(QDMA_PFTCH_CTXT_W0_BYPASS_MASK, ctxt->bypass) | - FIELD_SET(QDMA_PFTCH_CTXT_W0_BUF_SIZE_IDX_MASK, - ctxt->bufsz_idx) | - FIELD_SET(QDMA_PFTCH_CTXT_W0_PORT_ID_MASK, ctxt->port_id) | - FIELD_SET(QDMA_PFTCH_CTXT_W0_ERR_MASK, ctxt->err) | - FIELD_SET(QDMA_PFTCH_CTXT_W0_PFETCH_EN_MASK, ctxt->pfch_en) | - FIELD_SET(QDMA_PFTCH_CTXT_W0_Q_IN_PFETCH_MASK, ctxt->pfch) | - FIELD_SET(QDMA_PFTCH_CTXT_W0_SW_CRDT_L_MASK, sw_crdt_l); - - qdma_log_debug("%s: bypass=%x, bufsz_idx=%x, port_id=%x\n", - __func__, ctxt->bypass, ctxt->bufsz_idx, ctxt->port_id); - qdma_log_debug("%s: err=%x, pfch_en=%x, pfch=%x, ctxt->valid=%x\n", - __func__, ctxt->err, ctxt->pfch_en, ctxt->pfch, - ctxt->valid); - - pfetch_ctxt[num_words_count++] = - FIELD_SET(QDMA_PFTCH_CTXT_W1_SW_CRDT_H_MASK, sw_crdt_h) | - FIELD_SET(QDMA_PFTCH_CTXT_W1_VALID_MASK, ctxt->valid); - - return qdma_indirect_reg_write(dev_hndl, sel, hw_qid, - pfetch_ctxt, num_words_count); -} - -/*****************************************************************************/ -/** - * qdma_pfetch_context_read() - read prefetch context - * - * @dev_hndl: device handle - * @hw_qid: hardware qid of the queue - * @ctxt: pointer to the output context data - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -static int qdma_pfetch_context_read(void *dev_hndl, uint16_t hw_qid, - struct qdma_descq_prefetch_ctxt *ctxt) -{ - int rv = QDMA_SUCCESS; - uint32_t pfetch_ctxt[QDMA_PFETCH_CONTEXT_NUM_WORDS] = {0}; - enum ind_ctxt_cmd_sel sel = QDMA_CTXT_SEL_PFTCH; - uint32_t sw_crdt_l, sw_crdt_h; - - if (!dev_hndl || !ctxt) { - qdma_log_error("%s: dev_handle or pfetch ctxt NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - rv = qdma_indirect_reg_read(dev_hndl, sel, hw_qid, - QDMA_PFETCH_CONTEXT_NUM_WORDS, pfetch_ctxt); - if (rv < 0) - return rv; - - ctxt->bypass = - FIELD_GET(QDMA_PFTCH_CTXT_W0_BYPASS_MASK, pfetch_ctxt[0]); - ctxt->bufsz_idx = - FIELD_GET(QDMA_PFTCH_CTXT_W0_BUF_SIZE_IDX_MASK, pfetch_ctxt[0]); - ctxt->port_id = - FIELD_GET(QDMA_PFTCH_CTXT_W0_PORT_ID_MASK, pfetch_ctxt[0]); - ctxt->err = - (uint8_t)(FIELD_GET(QDMA_PFTCH_CTXT_W0_ERR_MASK, - pfetch_ctxt[0])); - ctxt->pfch_en = - (uint8_t)(FIELD_GET(QDMA_PFTCH_CTXT_W0_PFETCH_EN_MASK, - pfetch_ctxt[0])); - ctxt->pfch = - (uint8_t)(FIELD_GET(QDMA_PFTCH_CTXT_W0_Q_IN_PFETCH_MASK, - pfetch_ctxt[0])); - sw_crdt_l = - FIELD_GET(QDMA_PFTCH_CTXT_W0_SW_CRDT_L_MASK, pfetch_ctxt[0]); - - sw_crdt_h = - FIELD_GET(QDMA_PFTCH_CTXT_W1_SW_CRDT_H_MASK, pfetch_ctxt[1]); - ctxt->valid = - (uint8_t)(FIELD_GET(QDMA_PFTCH_CTXT_W1_VALID_MASK, - pfetch_ctxt[1])); - - ctxt->sw_crdt = - FIELD_SET(QDMA_PFTCH_CTXT_SW_CRDT_GET_L_MASK, sw_crdt_l) | - FIELD_SET(QDMA_PFTCH_CTXT_SW_CRDT_GET_H_MASK, sw_crdt_h); - - qdma_log_debug("%s: sw_crdt_l=%u, sw_crdt_h=%u, hw_qid=%hu\n", - __func__, sw_crdt_l, sw_crdt_h, hw_qid); - qdma_log_debug("%s: bypass=%x, bufsz_idx=%x, port_id=%x\n", - __func__, ctxt->bypass, ctxt->bufsz_idx, ctxt->port_id); - qdma_log_debug("%s: err=%x, pfch_en=%x, pfch=%x, ctxt->valid=%x\n", - __func__, ctxt->err, ctxt->pfch_en, ctxt->pfch, - ctxt->valid); - - return QDMA_SUCCESS; -} - -/*****************************************************************************/ -/** - * qdma_pfetch_context_clear() - clear prefetch context - * - * @dev_hndl: device handle - * @hw_qid: hardware qid of the queue - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -static int qdma_pfetch_context_clear(void *dev_hndl, uint16_t hw_qid) -{ - enum ind_ctxt_cmd_sel sel = QDMA_CTXT_SEL_PFTCH; - - if (!dev_hndl) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", __func__, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - return qdma_indirect_reg_clear(dev_hndl, sel, hw_qid); -} - -/*****************************************************************************/ -/** - * qdma_pfetch_context_invalidate() - invalidate prefetch context - * - * @dev_hndl: device handle - * @hw_qid: hardware qid of the queue - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -static int qdma_pfetch_context_invalidate(void *dev_hndl, uint16_t hw_qid) -{ - enum ind_ctxt_cmd_sel sel = QDMA_CTXT_SEL_PFTCH; - - if (!dev_hndl) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", __func__, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - return qdma_indirect_reg_invalidate(dev_hndl, sel, hw_qid); -} - -/*****************************************************************************/ -/** - * qdma_pfetch_ctx_conf() - configure prefetch context - * - * @dev_hndl: device handle - * @hw_qid: hardware qid of the queue - * @ctxt: pointer to context data - * @access_type HW access type (qdma_hw_access_type enum) value - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -int qdma_pfetch_ctx_conf(void *dev_hndl, uint16_t hw_qid, - struct qdma_descq_prefetch_ctxt *ctxt, - enum qdma_hw_access_type access_type) -{ - int rv = QDMA_SUCCESS; - - switch (access_type) { - case QDMA_HW_ACCESS_READ: - rv = qdma_pfetch_context_read(dev_hndl, hw_qid, ctxt); - break; - case QDMA_HW_ACCESS_WRITE: - rv = qdma_pfetch_context_write(dev_hndl, hw_qid, ctxt); - break; - case QDMA_HW_ACCESS_CLEAR: - rv = qdma_pfetch_context_clear(dev_hndl, hw_qid); - break; - case QDMA_HW_ACCESS_INVALIDATE: - rv = qdma_pfetch_context_invalidate(dev_hndl, hw_qid); - break; - default: - qdma_log_error("%s: access_type(%d) invalid, err:%d\n", - __func__, - access_type, - -QDMA_ERR_INV_PARAM); - rv = -QDMA_ERR_INV_PARAM; - break; - } - - return rv; -} - -/*****************************************************************************/ -/** - * qdma_cmpt_context_write() - create completion context and program it - * - * @dev_hndl: device handle - * @hw_qid: hardware qid of the queue - * @ctxt: pointer to the cmpt context data strucutre - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -static int qdma_cmpt_context_write(void *dev_hndl, uint16_t hw_qid, - const struct qdma_descq_cmpt_ctxt *ctxt) -{ - uint32_t cmpt_ctxt[QDMA_CMPT_CONTEXT_NUM_WORDS] = {0}; - uint16_t num_words_count = 0; - uint32_t baddr_l, baddr_h, pidx_l, pidx_h; - enum ind_ctxt_cmd_sel sel = QDMA_CTXT_SEL_CMPT; - - /* Input args check */ - if (!dev_hndl || !ctxt) { - qdma_log_error("%s: dev_handle or cmpt ctxt NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - if (ctxt->trig_mode > QDMA_CMPT_UPDATE_TRIG_MODE_TMR_CNTR) { - qdma_log_error("%s: trig_mode(%d) > (%d) is invalid, err:%d\n", - __func__, - ctxt->trig_mode, - QDMA_CMPT_UPDATE_TRIG_MODE_TMR_CNTR, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - baddr_l = (uint32_t)FIELD_GET(QDMA_COMPL_CTXT_BADDR_GET_L_MASK, - ctxt->bs_addr); - baddr_h = (uint32_t)FIELD_GET(QDMA_COMPL_CTXT_BADDR_GET_H_MASK, - ctxt->bs_addr); - pidx_l = FIELD_GET(QDMA_COMPL_CTXT_PIDX_GET_L_MASK, ctxt->pidx); - pidx_h = FIELD_GET(QDMA_COMPL_CTXT_PIDX_GET_H_MASK, ctxt->pidx); - - cmpt_ctxt[num_words_count++] = - FIELD_SET(QDMA_COMPL_CTXT_W0_EN_STAT_DESC_MASK, - ctxt->en_stat_desc) | - FIELD_SET(QDMA_COMPL_CTXT_W0_EN_INT_MASK, ctxt->en_int) | - FIELD_SET(QDMA_COMPL_CTXT_W0_TRIG_MODE_MASK, ctxt->trig_mode) | - FIELD_SET(QDMA_COMPL_CTXT_W0_FNC_ID_MASK, ctxt->fnc_id) | - FIELD_SET(QDMA_COMPL_CTXT_W0_COUNTER_IDX_MASK, - ctxt->counter_idx) | - FIELD_SET(QDMA_COMPL_CTXT_W0_TIMER_IDX_MASK, ctxt->timer_idx) | - FIELD_SET(QDMA_COMPL_CTXT_W0_INT_ST_MASK, ctxt->in_st) | - FIELD_SET(QDMA_COMPL_CTXT_W0_COLOR_MASK, ctxt->color) | - FIELD_SET(QDMA_COMPL_CTXT_W0_RING_SZ_MASK, ctxt->ringsz_idx); - - cmpt_ctxt[num_words_count++] = - FIELD_SET(QDMA_COMPL_CTXT_W1_BADDR_64_L_MASK, baddr_l); - - cmpt_ctxt[num_words_count++] = - FIELD_SET(QDMA_COMPL_CTXT_W2_BADDR_64_H_MASK, baddr_h) | - FIELD_SET(QDMA_COMPL_CTXT_W2_DESC_SIZE_MASK, ctxt->desc_sz) | - FIELD_SET(QDMA_COMPL_CTXT_W2_PIDX_L_MASK, pidx_l); - - - cmpt_ctxt[num_words_count++] = - FIELD_SET(QDMA_COMPL_CTXT_W3_PIDX_H_MASK, pidx_h) | - FIELD_SET(QDMA_COMPL_CTXT_W3_CIDX_MASK, ctxt->cidx) | - FIELD_SET(QDMA_COMPL_CTXT_W3_VALID_MASK, ctxt->valid) | - FIELD_SET(QDMA_COMPL_CTXT_W3_ERR_MASK, ctxt->err) | - FIELD_SET(QDMA_COMPL_CTXT_W3_USR_TRG_PND_MASK, - ctxt->user_trig_pend); - - cmpt_ctxt[num_words_count++] = - FIELD_SET(QDMA_COMPL_CTXT_W4_TMR_RUN_MASK, - ctxt->timer_running) | - FIELD_SET(QDMA_COMPL_CTXT_W4_FULL_UPDT_MASK, ctxt->full_upd) | - FIELD_SET(QDMA_COMPL_CTXT_W4_OVF_CHK_DIS_MASK, - ctxt->ovf_chk_dis) | - FIELD_SET(QDMA_COMPL_CTXT_W4_AT_MASK, ctxt->at) | - FIELD_SET(QDMA_COMPL_CTXT_W4_INTR_VEC_MASK, ctxt->vec) | - FIELD_SET(QDMA_COMPL_CTXT_W4_INTR_AGGR_MASK, ctxt->int_aggr); - - return qdma_indirect_reg_write(dev_hndl, sel, hw_qid, - cmpt_ctxt, num_words_count); -} - -/*****************************************************************************/ -/** - * qdma_cmpt_context_read() - read completion context - * - * @dev_hndl: device handle - * @hw_qid: hardware qid of the queue - * @ctxt: pointer to the context data - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -static int qdma_cmpt_context_read(void *dev_hndl, uint16_t hw_qid, - struct qdma_descq_cmpt_ctxt *ctxt) -{ - int rv = QDMA_SUCCESS; - uint32_t cmpt_ctxt[QDMA_CMPT_CONTEXT_NUM_WORDS] = {0}; - enum ind_ctxt_cmd_sel sel = QDMA_CTXT_SEL_CMPT; - uint32_t baddr_l, baddr_h, pidx_l, pidx_h; - - if (!dev_hndl || !ctxt) { - qdma_log_error("%s: dev_handle or cmpt ctxt NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - rv = qdma_indirect_reg_read(dev_hndl, sel, hw_qid, - QDMA_CMPT_CONTEXT_NUM_WORDS, cmpt_ctxt); - if (rv < 0) - return rv; - - ctxt->en_stat_desc = - FIELD_GET(QDMA_COMPL_CTXT_W0_EN_STAT_DESC_MASK, cmpt_ctxt[0]); - ctxt->en_int = FIELD_GET(QDMA_COMPL_CTXT_W0_EN_INT_MASK, cmpt_ctxt[0]); - ctxt->trig_mode = - FIELD_GET(QDMA_COMPL_CTXT_W0_TRIG_MODE_MASK, cmpt_ctxt[0]); - ctxt->fnc_id = - (uint8_t)(FIELD_GET(QDMA_COMPL_CTXT_W0_FNC_ID_MASK, - cmpt_ctxt[0])); - ctxt->counter_idx = - (uint8_t)(FIELD_GET(QDMA_COMPL_CTXT_W0_COUNTER_IDX_MASK, - cmpt_ctxt[0])); - ctxt->timer_idx = - (uint8_t)(FIELD_GET(QDMA_COMPL_CTXT_W0_TIMER_IDX_MASK, - cmpt_ctxt[0])); - ctxt->in_st = - (uint8_t)(FIELD_GET(QDMA_COMPL_CTXT_W0_INT_ST_MASK, - cmpt_ctxt[0])); - ctxt->color = - (uint8_t)(FIELD_GET(QDMA_COMPL_CTXT_W0_COLOR_MASK, - cmpt_ctxt[0])); - ctxt->ringsz_idx = - (uint8_t)(FIELD_GET(QDMA_COMPL_CTXT_W0_RING_SZ_MASK, - cmpt_ctxt[0])); - - baddr_l = FIELD_GET(QDMA_COMPL_CTXT_W1_BADDR_64_L_MASK, cmpt_ctxt[1]); - - baddr_h = FIELD_GET(QDMA_COMPL_CTXT_W2_BADDR_64_H_MASK, cmpt_ctxt[2]); - ctxt->desc_sz = - (uint8_t)(FIELD_GET(QDMA_COMPL_CTXT_W2_DESC_SIZE_MASK, - cmpt_ctxt[2])); - pidx_l = FIELD_GET(QDMA_COMPL_CTXT_W2_PIDX_L_MASK, cmpt_ctxt[2]); - - pidx_h = FIELD_GET(QDMA_COMPL_CTXT_W3_PIDX_H_MASK, cmpt_ctxt[3]); - ctxt->cidx = - (uint16_t)(FIELD_GET(QDMA_COMPL_CTXT_W3_CIDX_MASK, - cmpt_ctxt[3])); - ctxt->valid = - (uint8_t)(FIELD_GET(QDMA_COMPL_CTXT_W3_VALID_MASK, - cmpt_ctxt[3])); - ctxt->err = - (uint8_t)(FIELD_GET(QDMA_COMPL_CTXT_W3_ERR_MASK, cmpt_ctxt[3])); - ctxt->user_trig_pend = (uint8_t) - (FIELD_GET(QDMA_COMPL_CTXT_W3_USR_TRG_PND_MASK, cmpt_ctxt[3])); - - ctxt->timer_running = - FIELD_GET(QDMA_COMPL_CTXT_W4_TMR_RUN_MASK, cmpt_ctxt[4]); - ctxt->full_upd = - FIELD_GET(QDMA_COMPL_CTXT_W4_FULL_UPDT_MASK, cmpt_ctxt[4]); - ctxt->ovf_chk_dis = - FIELD_GET(QDMA_COMPL_CTXT_W4_OVF_CHK_DIS_MASK, cmpt_ctxt[4]); - ctxt->at = FIELD_GET(QDMA_COMPL_CTXT_W4_AT_MASK, cmpt_ctxt[4]); - ctxt->vec = FIELD_GET(QDMA_COMPL_CTXT_W4_INTR_VEC_MASK, cmpt_ctxt[4]); - ctxt->int_aggr = (uint8_t) - (FIELD_GET(QDMA_COMPL_CTXT_W4_INTR_AGGR_MASK, cmpt_ctxt[4])); - - ctxt->bs_addr = - FIELD_SET(QDMA_COMPL_CTXT_BADDR_GET_L_MASK, (uint64_t)baddr_l) | - FIELD_SET(QDMA_COMPL_CTXT_BADDR_GET_H_MASK, (uint64_t)baddr_h); - - ctxt->pidx = - FIELD_SET(QDMA_COMPL_CTXT_PIDX_GET_L_MASK, pidx_l) | - FIELD_SET(QDMA_COMPL_CTXT_PIDX_GET_H_MASK, pidx_h); - - return QDMA_SUCCESS; -} - -/*****************************************************************************/ -/** - * qdma_cmpt_context_clear() - clear completion context - * - * @dev_hndl: device handle - * @hw_qid: hardware qid of the queue - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -static int qdma_cmpt_context_clear(void *dev_hndl, uint16_t hw_qid) -{ - enum ind_ctxt_cmd_sel sel = QDMA_CTXT_SEL_CMPT; - - if (!dev_hndl) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", __func__, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - return qdma_indirect_reg_clear(dev_hndl, sel, hw_qid); -} - -/*****************************************************************************/ -/** - * qdma_cmpt_context_invalidate() - invalidate completion context - * - * @dev_hndl: device handle - * @hw_qid: hardware qid of the queue - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -static int qdma_cmpt_context_invalidate(void *dev_hndl, uint16_t hw_qid) -{ - enum ind_ctxt_cmd_sel sel = QDMA_CTXT_SEL_CMPT; - - if (!dev_hndl) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", __func__, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - return qdma_indirect_reg_invalidate(dev_hndl, sel, hw_qid); -} - -/*****************************************************************************/ -/** - * qdma_cmpt_ctx_conf() - configure completion context - * - * @dev_hndl: device handle - * @hw_qid: hardware qid of the queue - * @ctxt: pointer to context data - * @access_type HW access type (qdma_hw_access_type enum) value - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -int qdma_cmpt_ctx_conf(void *dev_hndl, uint16_t hw_qid, - struct qdma_descq_cmpt_ctxt *ctxt, - enum qdma_hw_access_type access_type) -{ - int rv = QDMA_SUCCESS; - - switch (access_type) { - case QDMA_HW_ACCESS_READ: - rv = qdma_cmpt_context_read(dev_hndl, hw_qid, ctxt); - break; - case QDMA_HW_ACCESS_WRITE: - rv = qdma_cmpt_context_write(dev_hndl, hw_qid, ctxt); - break; - case QDMA_HW_ACCESS_CLEAR: - rv = qdma_cmpt_context_clear(dev_hndl, hw_qid); - break; - case QDMA_HW_ACCESS_INVALIDATE: - rv = qdma_cmpt_context_invalidate(dev_hndl, hw_qid); - break; - default: - qdma_log_error("%s: access_type(%d) invalid, err:%d\n", - __func__, - access_type, - -QDMA_ERR_INV_PARAM); - rv = -QDMA_ERR_INV_PARAM; - break; - } - - return rv; -} - -/*****************************************************************************/ -/** - * qdma_hw_context_read() - read hardware context - * - * @dev_hndl: device handle - * @c2h: is c2h queue - * @hw_qid: hardware qid of the queue - * @ctxt: pointer to the output context data - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -static int qdma_hw_context_read(void *dev_hndl, uint8_t c2h, - uint16_t hw_qid, struct qdma_descq_hw_ctxt *ctxt) -{ - int rv = QDMA_SUCCESS; - uint32_t hw_ctxt[QDMA_HW_CONTEXT_NUM_WORDS] = {0}; - enum ind_ctxt_cmd_sel sel = c2h ? QDMA_CTXT_SEL_HW_C2H : - QDMA_CTXT_SEL_HW_H2C; - - if (!dev_hndl || !ctxt) { - qdma_log_error("%s: dev_handle or hw_ctxt NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - rv = qdma_indirect_reg_read(dev_hndl, sel, hw_qid, - QDMA_HW_CONTEXT_NUM_WORDS, hw_ctxt); - if (rv < 0) - return rv; - - ctxt->cidx = FIELD_GET(QDMA_HW_CTXT_W0_CIDX_MASK, hw_ctxt[0]); - ctxt->crd_use = - (uint16_t)(FIELD_GET(QDMA_HW_CTXT_W0_CRD_USE_MASK, hw_ctxt[0])); - - ctxt->dsc_pend = - (uint8_t)(FIELD_GET(QDMA_HW_CTXT_W1_DSC_PND_MASK, hw_ctxt[1])); - ctxt->idl_stp_b = - (uint8_t)(FIELD_GET(QDMA_HW_CTXT_W1_IDL_STP_B_MASK, - hw_ctxt[1])); - ctxt->evt_pnd = - (uint8_t)(FIELD_GET(QDMA_HW_CTXT_W1_EVENT_PEND_MASK, - hw_ctxt[1])); - ctxt->fetch_pnd = (uint8_t) - (FIELD_GET(QDMA_HW_CTXT_W1_FETCH_PEND_MASK, hw_ctxt[1])); - - qdma_log_debug("%s: cidx=%hu, crd_use=%hu, dsc_pend=%x\n", - __func__, ctxt->cidx, ctxt->crd_use, ctxt->dsc_pend); - qdma_log_debug("%s: idl_stp_b=%x, evt_pnd=%x, fetch_pnd=%x\n", - __func__, ctxt->idl_stp_b, ctxt->evt_pnd, - ctxt->fetch_pnd); - - return QDMA_SUCCESS; -} - -/*****************************************************************************/ -/** - * qdma_hw_context_clear() - clear hardware context - * - * @dev_hndl: device handle - * @c2h: is c2h queue - * @hw_qid: hardware qid of the queue - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -static int qdma_hw_context_clear(void *dev_hndl, uint8_t c2h, - uint16_t hw_qid) -{ - enum ind_ctxt_cmd_sel sel = c2h ? QDMA_CTXT_SEL_HW_C2H : - QDMA_CTXT_SEL_HW_H2C; - - if (!dev_hndl) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", __func__, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - return qdma_indirect_reg_clear(dev_hndl, sel, hw_qid); -} - -/*****************************************************************************/ -/** - * qdma_hw_context_invalidate() - invalidate hardware context - * - * @dev_hndl: device handle - * @c2h: is c2h queue - * @hw_qid: hardware qid of the queue - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -static int qdma_hw_context_invalidate(void *dev_hndl, uint8_t c2h, - uint16_t hw_qid) -{ - enum ind_ctxt_cmd_sel sel = c2h ? QDMA_CTXT_SEL_HW_C2H : - QDMA_CTXT_SEL_HW_H2C; - - if (!dev_hndl) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", __func__, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - return qdma_indirect_reg_invalidate(dev_hndl, sel, hw_qid); -} - -/*****************************************************************************/ -/** - * qdma_hw_ctx_conf() - configure HW context - * - * @dev_hndl: device handle - * @c2h: is c2h queue - * @hw_qid: hardware qid of the queue - * @ctxt: pointer to context data - * @access_type HW access type (qdma_hw_access_type enum) value - * QDMA_HW_ACCESS_WRITE Not supported - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -int qdma_hw_ctx_conf(void *dev_hndl, uint8_t c2h, uint16_t hw_qid, - struct qdma_descq_hw_ctxt *ctxt, - enum qdma_hw_access_type access_type) -{ - int rv = QDMA_SUCCESS; - - /** ctxt requires only H2C-0 or C2H-1 - * return error for any other values - */ - if (c2h > 1) { - qdma_log_error("%s: c2h(%d) invalid, err:%d\n", - __func__, - c2h, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - switch (access_type) { - case QDMA_HW_ACCESS_READ: - rv = qdma_hw_context_read(dev_hndl, c2h, hw_qid, ctxt); - break; - case QDMA_HW_ACCESS_CLEAR: - rv = qdma_hw_context_clear(dev_hndl, c2h, hw_qid); - break; - case QDMA_HW_ACCESS_INVALIDATE: - rv = qdma_hw_context_invalidate(dev_hndl, c2h, hw_qid); - break; - case QDMA_HW_ACCESS_WRITE: - default: - qdma_log_error("%s: access_type=%d is invalid, err:%d\n", - __func__, access_type, - -QDMA_ERR_INV_PARAM); - rv = -QDMA_ERR_INV_PARAM; - break; - } - - return rv; -} - -/*****************************************************************************/ -/** - * qdma_credit_context_read() - read credit context - * - * @dev_hndl: device handle - * @c2h: is c2h queue - * @hw_qid: hardware qid of the queue - * @ctxt: pointer to the context data - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -static int qdma_credit_context_read(void *dev_hndl, uint8_t c2h, - uint16_t hw_qid, - struct qdma_descq_credit_ctxt *ctxt) -{ - int rv = QDMA_SUCCESS; - uint32_t cr_ctxt[QDMA_CR_CONTEXT_NUM_WORDS] = {0}; - enum ind_ctxt_cmd_sel sel = c2h ? QDMA_CTXT_SEL_CR_C2H : - QDMA_CTXT_SEL_CR_H2C; - - if (!dev_hndl || !ctxt) { - qdma_log_error("%s: dev_hndl=%p credit_ctxt=%p, err:%d\n", - __func__, dev_hndl, ctxt, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - rv = qdma_indirect_reg_read(dev_hndl, sel, hw_qid, - QDMA_CR_CONTEXT_NUM_WORDS, cr_ctxt); - if (rv < 0) - return rv; - - ctxt->credit = FIELD_GET(QDMA_CR_CTXT_W0_CREDT_MASK, cr_ctxt[0]); - - qdma_log_debug("%s: credit=%u\n", __func__, ctxt->credit); - - return QDMA_SUCCESS; -} - -/*****************************************************************************/ -/** - * qdma_credit_context_clear() - clear credit context - * - * @dev_hndl: device handle - * @c2h: is c2h queue - * @hw_qid: hardware qid of the queue - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -static int qdma_credit_context_clear(void *dev_hndl, uint8_t c2h, - uint16_t hw_qid) -{ - enum ind_ctxt_cmd_sel sel = c2h ? QDMA_CTXT_SEL_CR_C2H : - QDMA_CTXT_SEL_CR_H2C; - - if (!dev_hndl) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", __func__, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - return qdma_indirect_reg_clear(dev_hndl, sel, hw_qid); -} - -/*****************************************************************************/ -/** - * qdma_credit_context_invalidate() - invalidate credit context - * - * @dev_hndl: device handle - * @c2h: is c2h queue - * @hw_qid: hardware qid of the queue - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -static int qdma_credit_context_invalidate(void *dev_hndl, uint8_t c2h, - uint16_t hw_qid) -{ - enum ind_ctxt_cmd_sel sel = c2h ? QDMA_CTXT_SEL_CR_C2H : - QDMA_CTXT_SEL_CR_H2C; - - if (!dev_hndl) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", __func__, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - return qdma_indirect_reg_invalidate(dev_hndl, sel, hw_qid); -} - -/*****************************************************************************/ -/** - * qdma_credit_ctx_conf() - configure credit context - * - * @dev_hndl: device handle - * @c2h: is c2h queue - * @hw_qid: hardware qid of the queue - * @ctxt: pointer to the context data - * @access_type HW access type (qdma_hw_access_type enum) value - * QDMA_HW_ACCESS_WRITE Not supported - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -int qdma_credit_ctx_conf(void *dev_hndl, uint8_t c2h, uint16_t hw_qid, - struct qdma_descq_credit_ctxt *ctxt, - enum qdma_hw_access_type access_type) -{ - int rv = QDMA_SUCCESS; - - /** ctxt requires only H2C-0 or C2H-1 - * return error for any other values - */ - if (c2h > 1) { - qdma_log_error("%s: c2h(%d) invalid, err:%d\n", - __func__, - c2h, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - switch (access_type) { - case QDMA_HW_ACCESS_READ: - rv = qdma_credit_context_read(dev_hndl, c2h, hw_qid, ctxt); - break; - case QDMA_HW_ACCESS_CLEAR: - rv = qdma_credit_context_clear(dev_hndl, c2h, hw_qid); - break; - case QDMA_HW_ACCESS_INVALIDATE: - rv = qdma_credit_context_invalidate(dev_hndl, c2h, hw_qid); - break; - case QDMA_HW_ACCESS_WRITE: - default: - qdma_log_error("%s: Invalid access type=%d, err:%d\n", - __func__, access_type, - -QDMA_ERR_INV_PARAM); - rv = -QDMA_ERR_INV_PARAM; - break; - } - - return rv; -} - -/*****************************************************************************/ -/** - * qdma_indirect_intr_context_write() - create indirect interrupt context - * and program it - * - * @dev_hndl: device handle - * @ring_index: indirect interrupt ring index - * @ctxt: pointer to the interrupt context data strucutre - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -static int qdma_indirect_intr_context_write(void *dev_hndl, uint16_t ring_index, - const struct qdma_indirect_intr_ctxt *ctxt) -{ - uint32_t intr_ctxt[QDMA_IND_INTR_CONTEXT_NUM_WORDS] = {0}; - enum ind_ctxt_cmd_sel sel = QDMA_CTXT_SEL_INT_COAL; - uint32_t baddr_l, baddr_m, baddr_h; - uint16_t num_words_count = 0; - - if (!dev_hndl || !ctxt) { - qdma_log_error("%s: dev_hndl=%p intr_ctxt=%p, err:%d\n", - __func__, dev_hndl, ctxt, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - baddr_l = (uint32_t)FIELD_GET(QDMA_INTR_CTXT_BADDR_GET_L_MASK, - ctxt->baddr_4k); - baddr_m = (uint32_t)FIELD_GET(QDMA_INTR_CTXT_BADDR_GET_M_MASK, - ctxt->baddr_4k); - baddr_h = (uint32_t)FIELD_GET(QDMA_INTR_CTXT_BADDR_GET_H_MASK, - ctxt->baddr_4k); - - intr_ctxt[num_words_count++] = - FIELD_SET(QDMA_INTR_CTXT_W0_VALID_MASK, ctxt->valid) | - FIELD_SET(QDMA_INTR_CTXT_W0_VEC_ID_MASK, ctxt->vec) | - FIELD_SET(QDMA_INTR_CTXT_W0_INT_ST_MASK, ctxt->int_st) | - FIELD_SET(QDMA_INTR_CTXT_W0_COLOR_MASK, ctxt->color) | - FIELD_SET(QDMA_INTR_CTXT_W0_BADDR_64_MASK, baddr_l); - - intr_ctxt[num_words_count++] = - FIELD_SET(QDMA_INTR_CTXT_W1_BADDR_64_MASK, baddr_m); - - intr_ctxt[num_words_count++] = - FIELD_SET(QDMA_INTR_CTXT_W2_BADDR_64_MASK, baddr_h) | - FIELD_SET(QDMA_INTR_CTXT_W2_PAGE_SIZE_MASK, ctxt->page_size) | - FIELD_SET(QDMA_INTR_CTXT_W2_PIDX_MASK, ctxt->pidx) | - FIELD_SET(QDMA_INTR_CTXT_W2_AT_MASK, ctxt->at); - - return qdma_indirect_reg_write(dev_hndl, sel, ring_index, - intr_ctxt, num_words_count); -} - -/*****************************************************************************/ -/** - * qdma_indirect_intr_context_read() - read indirect interrupt context - * - * @dev_hndl: device handle - * @ring_index: indirect interrupt ring index - * @ctxt: pointer to the output context data - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -static int qdma_indirect_intr_context_read(void *dev_hndl, uint16_t ring_index, - struct qdma_indirect_intr_ctxt *ctxt) -{ - int rv = QDMA_SUCCESS; - uint32_t intr_ctxt[QDMA_IND_INTR_CONTEXT_NUM_WORDS] = {0}; - enum ind_ctxt_cmd_sel sel = QDMA_CTXT_SEL_INT_COAL; - uint64_t baddr_l, baddr_m, baddr_h; - - if (!dev_hndl || !ctxt) { - qdma_log_error("%s: dev_hndl=%p intr_ctxt=%p, err:%d\n", - __func__, dev_hndl, ctxt, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - rv = qdma_indirect_reg_read(dev_hndl, sel, ring_index, - QDMA_IND_INTR_CONTEXT_NUM_WORDS, intr_ctxt); - if (rv < 0) - return rv; - - ctxt->valid = FIELD_GET(QDMA_INTR_CTXT_W0_VALID_MASK, intr_ctxt[0]); - ctxt->vec = FIELD_GET(QDMA_INTR_CTXT_W0_VEC_ID_MASK, intr_ctxt[0]); - ctxt->int_st = - (uint8_t)(FIELD_GET(QDMA_INTR_CTXT_W0_INT_ST_MASK, - intr_ctxt[0])); - ctxt->color = - (uint8_t)(FIELD_GET(QDMA_INTR_CTXT_W0_COLOR_MASK, - intr_ctxt[0])); - - baddr_l = FIELD_GET(QDMA_INTR_CTXT_W0_BADDR_64_MASK, intr_ctxt[0]); - - baddr_m = FIELD_GET(QDMA_INTR_CTXT_W1_BADDR_64_MASK, intr_ctxt[1]); - - baddr_h = FIELD_GET(QDMA_INTR_CTXT_W2_BADDR_64_MASK, intr_ctxt[2]); - ctxt->page_size = - FIELD_GET(QDMA_INTR_CTXT_W2_PAGE_SIZE_MASK, intr_ctxt[2]); - ctxt->pidx = - (uint16_t)(FIELD_GET(QDMA_INTR_CTXT_W2_PIDX_MASK, - intr_ctxt[2])); - ctxt->at = - (uint8_t)(FIELD_GET(QDMA_INTR_CTXT_W2_AT_MASK, intr_ctxt[2])); - - ctxt->baddr_4k = - FIELD_SET(QDMA_INTR_CTXT_BADDR_GET_L_MASK, baddr_l) | - FIELD_SET(QDMA_INTR_CTXT_BADDR_GET_M_MASK, baddr_m) | - FIELD_SET(QDMA_INTR_CTXT_BADDR_GET_H_MASK, baddr_h); - - return QDMA_SUCCESS; -} - -/*****************************************************************************/ -/** - * qdma_indirect_intr_context_clear() - clear indirect interrupt context - * - * @dev_hndl: device handle - * @ring_index: indirect interrupt ring index - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -static int qdma_indirect_intr_context_clear(void *dev_hndl, uint16_t ring_index) -{ - enum ind_ctxt_cmd_sel sel = QDMA_CTXT_SEL_INT_COAL; - - if (!dev_hndl) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", __func__, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - return qdma_indirect_reg_clear(dev_hndl, sel, ring_index); -} - -/*****************************************************************************/ -/** - * qdma_indirect_intr_context_invalidate() - invalidate indirect interrupt - * context - * - * @dev_hndl: device handle - * @ring_index: indirect interrupt ring index - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -static int qdma_indirect_intr_context_invalidate(void *dev_hndl, - uint16_t ring_index) -{ - enum ind_ctxt_cmd_sel sel = QDMA_CTXT_SEL_INT_COAL; - - if (!dev_hndl) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", __func__, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - return qdma_indirect_reg_invalidate(dev_hndl, sel, ring_index); -} - -/*****************************************************************************/ -/** - * qdma_indirect_intr_ctx_conf() - configure indirect interrupt context - * - * @dev_hndl: device handle - * @ring_index: indirect interrupt ring index - * @ctxt: pointer to context data - * @access_type HW access type (qdma_hw_access_type enum) value - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -int qdma_indirect_intr_ctx_conf(void *dev_hndl, uint16_t ring_index, - struct qdma_indirect_intr_ctxt *ctxt, - enum qdma_hw_access_type access_type) -{ - int rv = QDMA_SUCCESS; - - switch (access_type) { - case QDMA_HW_ACCESS_READ: - rv = qdma_indirect_intr_context_read(dev_hndl, ring_index, - ctxt); - break; - case QDMA_HW_ACCESS_WRITE: - rv = qdma_indirect_intr_context_write(dev_hndl, ring_index, - ctxt); - break; - case QDMA_HW_ACCESS_CLEAR: - rv = qdma_indirect_intr_context_clear(dev_hndl, - ring_index); - break; - case QDMA_HW_ACCESS_INVALIDATE: - rv = qdma_indirect_intr_context_invalidate(dev_hndl, - ring_index); - break; - default: - qdma_log_error("%s: access_type=%d is invalid, err:%d\n", - __func__, access_type, - -QDMA_ERR_INV_PARAM); - rv = -QDMA_ERR_INV_PARAM; - break; - } - - return rv; -} - -/*****************************************************************************/ -/** - * qdma_set_default_global_csr() - function to set the global CSR register to - * default values. The value can be modified later by using the set/get csr - * functions - * - * @dev_hndl: device handle - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -int qdma_set_default_global_csr(void *dev_hndl) -{ - /* Default values */ - uint32_t cfg_val = 0, reg_val = 0; - uint32_t rng_sz[QDMA_NUM_RING_SIZES] = {2049, 65, 129, 193, 257, 385, - 513, 769, 1025, 1537, 3073, 4097, 6145, 8193, 12289, 16385}; - uint32_t tmr_cnt[QDMA_NUM_C2H_TIMERS] = {1, 2, 4, 5, 8, 10, 15, 20, 25, - 30, 50, 75, 100, 125, 150, 200}; - uint32_t cnt_th[QDMA_NUM_C2H_COUNTERS] = {2, 4, 8, 16, 24, 32, 48, 64, - 80, 96, 112, 128, 144, 160, 176, 192}; - uint32_t buf_sz[QDMA_NUM_C2H_BUFFER_SIZES] = {4096, 256, 512, 1024, - 2048, 3968, 4096, 4096, 4096, 4096, 4096, 4096, 4096, 8192, - 9018, 16384}; - struct qdma_dev_attributes dev_cap; - - if (!dev_hndl) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", __func__, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - qdma_get_device_attributes(dev_hndl, &dev_cap); - - /* Configuring CSR registers */ - /* Global ring sizes */ - qdma_write_csr_values(dev_hndl, QDMA_OFFSET_GLBL_RNG_SZ, 0, - QDMA_NUM_RING_SIZES, rng_sz); - - if (dev_cap.st_en || dev_cap.mm_cmpt_en) { - /* Counter thresholds */ - qdma_write_csr_values(dev_hndl, QDMA_OFFSET_C2H_CNT_TH, 0, - QDMA_NUM_C2H_COUNTERS, cnt_th); - - /* Timer Counters */ - qdma_write_csr_values(dev_hndl, QDMA_OFFSET_C2H_TIMER_CNT, 0, - QDMA_NUM_C2H_TIMERS, tmr_cnt); - - - /* Writeback Interval */ - reg_val = - FIELD_SET(QDMA_GLBL_DSC_CFG_MAX_DSC_FETCH_MASK, - DEFAULT_MAX_DSC_FETCH) | - FIELD_SET(QDMA_GLBL_DSC_CFG_WB_ACC_INT_MASK, - DEFAULT_WRB_INT); - qdma_reg_write(dev_hndl, QDMA_OFFSET_GLBL_DSC_CFG, reg_val); - } - - if (dev_cap.st_en) { - /* Buffer Sizes */ - qdma_write_csr_values(dev_hndl, QDMA_OFFSET_C2H_BUF_SZ, 0, - QDMA_NUM_C2H_BUFFER_SIZES, buf_sz); - - /* Prefetch Configuration */ - cfg_val = qdma_reg_read(dev_hndl, - QDMA_OFFSET_C2H_PFETCH_CACHE_DEPTH); - reg_val = - FIELD_SET(QDMA_C2H_PFCH_FL_TH_MASK, - DEFAULT_PFCH_STOP_THRESH) | - FIELD_SET(QDMA_C2H_NUM_PFCH_MASK, - DEFAULT_PFCH_NUM_ENTRIES_PER_Q) | - FIELD_SET(QDMA_C2H_PFCH_QCNT_MASK, (cfg_val >> 1)) | - FIELD_SET(QDMA_C2H_EVT_QCNT_TH_MASK, - ((cfg_val >> 1) - 2)); - qdma_reg_write(dev_hndl, QDMA_OFFSET_C2H_PFETCH_CFG, reg_val); - - /* C2H interrupt timer tick */ - qdma_reg_write(dev_hndl, QDMA_OFFSET_C2H_INT_TIMER_TICK, - DEFAULT_C2H_INTR_TIMER_TICK); - - /* C2h Completion Coalesce Configuration */ - cfg_val = qdma_reg_read(dev_hndl, - QDMA_OFFSET_C2H_CMPT_COAL_BUF_DEPTH); - reg_val = - FIELD_SET(QDMA_C2H_TICK_CNT_MASK, - DEFAULT_CMPT_COAL_TIMER_CNT) | - FIELD_SET(QDMA_C2H_TICK_VAL_MASK, - DEFAULT_CMPT_COAL_TIMER_TICK) | - FIELD_SET(QDMA_C2H_MAX_BUF_SZ_MASK, cfg_val); - qdma_reg_write(dev_hndl, QDMA_OFFSET_C2H_WRB_COAL_CFG, reg_val); - - /* H2C throttle Configuration*/ - reg_val = - FIELD_SET(QDMA_H2C_DATA_THRESH_MASK, - QDMA_H2C_THROT_DATA_THRESH) | - FIELD_SET(QDMA_H2C_REQ_THROT_EN_DATA_MASK, - QDMA_THROT_EN_DATA) | - FIELD_SET(QDMA_H2C_REQ_THRESH_MASK, - QDMA_H2C_THROT_REQ_THRESH) | - FIELD_SET(QDMA_H2C_REQ_THROT_EN_REQ_MASK, - QDMA_THROT_EN_REQ); - qdma_reg_write(dev_hndl, QDMA_OFFSET_H2C_REQ_THROT, reg_val); - } - - return QDMA_SUCCESS; -} - -/*****************************************************************************/ -/** - * qdma_queue_pidx_update() - function to update the desc PIDX - * - * @dev_hndl: device handle - * @is_vf: Whether PF or VF - * @qid: Queue id relative to the PF/VF calling this API - * @is_c2h: Queue direction. Set 1 for C2H and 0 for H2C - * @reg_info: data needed for the PIDX register update - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -int qdma_queue_pidx_update(void *dev_hndl, uint8_t is_vf, uint16_t qid, - uint8_t is_c2h, const struct qdma_q_pidx_reg_info *reg_info) -{ - uint32_t reg_addr = 0; - uint32_t reg_val = 0; - - if (!dev_hndl) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", - __func__, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - if (!reg_info) { - qdma_log_error("%s: reg_info is NULL, err:%d\n", - __func__, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - if (!is_vf) { - reg_addr = (is_c2h) ? QDMA_OFFSET_DMAP_SEL_C2H_DSC_PIDX : - QDMA_OFFSET_DMAP_SEL_H2C_DSC_PIDX; - } else { - reg_addr = (is_c2h) ? QDMA_OFFSET_VF_DMAP_SEL_C2H_DSC_PIDX : - QDMA_OFFSET_VF_DMAP_SEL_H2C_DSC_PIDX; - } - - reg_addr += (qid * QDMA_PIDX_STEP); - - reg_val = FIELD_SET(QDMA_DMA_SEL_DESC_PIDX_MASK, reg_info->pidx) | - FIELD_SET(QDMA_DMA_SEL_IRQ_EN_MASK, - reg_info->irq_en); - - qdma_reg_write(dev_hndl, reg_addr, reg_val); - - return QDMA_SUCCESS; -} - -/*****************************************************************************/ -/** - * qdma_queue_cmpt_cidx_update() - function to update the CMPT CIDX update - * - * @dev_hndl: device handle - * @is_vf: Whether PF or VF - * @qid: Queue id relative to the PF/VF calling this API - * @reg_info: data needed for the CIDX register update - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -int qdma_queue_cmpt_cidx_update(void *dev_hndl, uint8_t is_vf, - uint16_t qid, const struct qdma_q_cmpt_cidx_reg_info *reg_info) -{ - uint32_t reg_addr = (is_vf) ? QDMA_OFFSET_VF_DMAP_SEL_CMPT_CIDX : - QDMA_OFFSET_DMAP_SEL_CMPT_CIDX; - uint32_t reg_val = 0; - - if (!dev_hndl) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", - __func__, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - if (!reg_info) { - qdma_log_error("%s: reg_info is NULL, err:%d\n", - __func__, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - reg_addr += (qid * QDMA_CMPT_CIDX_STEP); - - reg_val = - FIELD_SET(QDMA_DMAP_SEL_CMPT_WRB_CIDX_MASK, - reg_info->wrb_cidx) | - FIELD_SET(QDMA_DMAP_SEL_CMPT_CNT_THRESH_MASK, - reg_info->counter_idx) | - FIELD_SET(QDMA_DMAP_SEL_CMPT_TMR_CNT_MASK, - reg_info->timer_idx) | - FIELD_SET(QDMA_DMAP_SEL_CMPT_TRG_MODE_MASK, - reg_info->trig_mode) | - FIELD_SET(QDMA_DMAP_SEL_CMPT_STS_DESC_EN_MASK, - reg_info->wrb_en) | - FIELD_SET(QDMA_DMAP_SEL_CMPT_IRQ_EN_MASK, reg_info->irq_en); - - qdma_reg_write(dev_hndl, reg_addr, reg_val); - - return QDMA_SUCCESS; -} - -/*****************************************************************************/ -/** - * qdma_queue_intr_cidx_update() - function to update the CMPT CIDX update - * - * @dev_hndl: device handle - * @is_vf: Whether PF or VF - * @qid: Queue id relative to the PF/VF calling this API - * @reg_info: data needed for the CIDX register update - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -int qdma_queue_intr_cidx_update(void *dev_hndl, uint8_t is_vf, - uint16_t qid, const struct qdma_intr_cidx_reg_info *reg_info) -{ - uint32_t reg_addr = (is_vf) ? QDMA_OFFSET_VF_DMAP_SEL_INT_CIDX : - QDMA_OFFSET_DMAP_SEL_INT_CIDX; - uint32_t reg_val = 0; - - if (!dev_hndl) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - if (!reg_info) { - qdma_log_error("%s: reg_info is NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - reg_addr += qid * QDMA_INT_CIDX_STEP; - - reg_val = - FIELD_SET(QDMA_DMA_SEL_INT_SW_CIDX_MASK, reg_info->sw_cidx) | - FIELD_SET(QDMA_DMA_SEL_INT_RING_IDX_MASK, reg_info->rng_idx); - - qdma_reg_write(dev_hndl, reg_addr, reg_val); - - return QDMA_SUCCESS; -} - -/*****************************************************************************/ -/** - * qdma_get_user_bar() - Function to get the - * AXI Master Lite(user bar) number - * - * @dev_hndl: device handle - * @is_vf: Whether PF or VF - * @func_id: function id of the PF - * @user_bar: pointer to hold the AXI Master Lite number - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -int qdma_get_user_bar(void *dev_hndl, uint8_t is_vf, - uint8_t func_id, uint8_t *user_bar) -{ - uint8_t bar_found = 0; - uint8_t bar_idx = 0; - uint32_t user_bar_id = 0; - uint32_t reg_addr = (is_vf) ? QDMA_OFFSET_VF_USER_BAR_ID : - QDMA_OFFSET_GLBL2_PF_BARLITE_EXT; - - if (!dev_hndl) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - if (!user_bar) { - qdma_log_error("%s: user_bar is NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - user_bar_id = qdma_reg_read(dev_hndl, reg_addr); - - if (!is_vf) - user_bar_id = (user_bar_id >> (6 * func_id)) & 0x3F; - else - user_bar_id = user_bar_id & 0x3F; - - for (bar_idx = 0; bar_idx < QDMA_BAR_NUM; bar_idx++) { - if (user_bar_id & (1 << bar_idx)) { - *user_bar = bar_idx; - bar_found = 1; - break; - } - } - if (bar_found == 0) { - *user_bar = 0; - qdma_log_error("%s: Bar not found, vf:%d, usrbar:%d, err:%d\n", - __func__, - is_vf, - *user_bar, - -QDMA_ERR_HWACC_BAR_NOT_FOUND); - return -QDMA_ERR_HWACC_BAR_NOT_FOUND; - } - - return QDMA_SUCCESS; -} - -/*****************************************************************************/ -/** - * qdma_get_device_attributes() - Function to get the qdma device attributes - * - * @dev_hndl: device handle - * @dev_info: pointer to hold the device info - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -int qdma_get_device_attributes(void *dev_hndl, - struct qdma_dev_attributes *dev_info) -{ - uint8_t count = 0; - uint32_t reg_val = 0; - - if (!dev_hndl) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - if (!dev_info) { - qdma_log_error("%s: dev_info is NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - /* number of PFs */ - reg_val = qdma_reg_read(dev_hndl, QDMA_OFFSET_GLBL2_PF_BARLITE_INT); - if (FIELD_GET(QDMA_GLBL2_PF0_BAR_MAP_MASK, reg_val)) - count++; - if (FIELD_GET(QDMA_GLBL2_PF1_BAR_MAP_MASK, reg_val)) - count++; - if (FIELD_GET(QDMA_GLBL2_PF2_BAR_MAP_MASK, reg_val)) - count++; - if (FIELD_GET(QDMA_GLBL2_PF3_BAR_MAP_MASK, reg_val)) - count++; - dev_info->num_pfs = count; - - /* Number of Qs */ - reg_val = qdma_reg_read(dev_hndl, QDMA_OFFSET_GLBL2_CHANNEL_QDMA_CAP); - dev_info->num_qs = FIELD_GET(QDMA_GLBL2_MULTQ_MAX_MASK, reg_val); - - /* FLR present */ - reg_val = qdma_reg_read(dev_hndl, QDMA_OFFSET_GLBL2_MISC_CAP); - dev_info->mailbox_en = FIELD_GET(QDMA_GLBL2_MAILBOX_EN_MASK, reg_val); - dev_info->flr_present = FIELD_GET(QDMA_GLBL2_FLR_PRESENT_MASK, reg_val); - dev_info->mm_cmpt_en = FIELD_GET(QDMA_GLBL2_MM_CMPT_EN_MASK, reg_val); - - /* ST/MM enabled? */ - reg_val = qdma_reg_read(dev_hndl, QDMA_OFFSET_GLBL2_CHANNEL_MDMA); - dev_info->mm_en = (FIELD_GET(QDMA_GLBL2_MM_C2H_MASK, reg_val) - && FIELD_GET(QDMA_GLBL2_MM_H2C_MASK, reg_val)) ? 1 : 0; - dev_info->st_en = (FIELD_GET(QDMA_GLBL2_ST_C2H_MASK, reg_val) - && FIELD_GET(QDMA_GLBL2_ST_H2C_MASK, reg_val)) ? 1 : 0; - - /* num of mm channels */ - /* TODO : Register not yet defined for this. Hard coding it to 1.*/ - dev_info->mm_channel_max = 1; - - dev_info->debug_mode = 0; - dev_info->desc_eng_mode = 0; - dev_info->qid2vec_ctx = 0; - dev_info->cmpt_ovf_chk_dis = 1; - dev_info->mailbox_intr = 1; - dev_info->sw_desc_64b = 1; - dev_info->cmpt_desc_64b = 1; - dev_info->dynamic_bar = 1; - dev_info->legacy_intr = 1; - dev_info->cmpt_trig_count_timer = 1; - - return QDMA_SUCCESS; -} - -/*****************************************************************************/ -/** - * qdma_hw_ram_sbe_err_process() - Function to dump SBE error debug information - * - * @dev_hndl: device handle - * @buf: Bufffer for the debug info to be dumped in - * @buflen: Length of the buffer - * - * Return: void - *****************************************************************************/ -static void qdma_hw_ram_sbe_err_process(void *dev_hndl) -{ - qdma_dump_reg_info(dev_hndl, QDMA_OFFSET_RAM_SBE_STAT, - 1, NULL, 0); -} - -/*****************************************************************************/ -/** - * qdma_hw_ram_dbe_err_process() - Function to dump DBE error debug information - * - * @dev_hndl: device handle - * @buf: Bufffer for the debug info to be dumped in - * @buflen: Length of the buffer - * - * Return: void - *****************************************************************************/ -static void qdma_hw_ram_dbe_err_process(void *dev_hndl) -{ - qdma_dump_reg_info(dev_hndl, QDMA_OFFSET_RAM_DBE_STAT, - 1, NULL, 0); -} - -/*****************************************************************************/ -/** - * qdma_hw_desc_err_process() - Function to dump Descriptor Error information - * - * @dev_hndl: device handle - * @buf: Bufffer for the debug info to be dumped in - * @buflen: Length of the buffer - * - * Return: void - *****************************************************************************/ -static void qdma_hw_desc_err_process(void *dev_hndl) -{ - int i = 0; - uint32_t desc_err_reg_list[] = { - QDMA_OFFSET_GLBL_DSC_ERR_STS, - QDMA_OFFSET_GLBL_DSC_ERR_LOG0, - QDMA_OFFSET_GLBL_DSC_ERR_LOG1, - QDMA_OFFSET_GLBL_DSC_DBG_DAT0, - QDMA_OFFSET_GLBL_DSC_DBG_DAT1, - QDMA_OFFSET_GLBL_DSC_ERR_LOG2 - }; - int desc_err_num_regs = sizeof(desc_err_reg_list)/sizeof(uint32_t); - - for (i = 0; i < desc_err_num_regs; i++) { - qdma_dump_reg_info(dev_hndl, desc_err_reg_list[i], - 1, NULL, 0); - } -} - -/*****************************************************************************/ -/** - * qdma_hw_trq_err_process() - Function to dump Target Access Error information - * - * @dev_hndl: device handle - * @buf: Bufffer for the debug info to be dumped in - * @buflen: Length of the buffer - * - * Return: void - *****************************************************************************/ -static void qdma_hw_trq_err_process(void *dev_hndl) -{ - int i = 0; - uint32_t trq_err_reg_list[] = { - QDMA_OFFSET_GLBL_TRQ_ERR_STS, - QDMA_OFFSET_GLBL_TRQ_ERR_LOG - }; - int trq_err_reg_num_regs = sizeof(trq_err_reg_list)/sizeof(uint32_t); - - for (i = 0; i < trq_err_reg_num_regs; i++) { - qdma_dump_reg_info(dev_hndl, trq_err_reg_list[i], - 1, NULL, 0); - } - - -} - -/*****************************************************************************/ -/** - * qdma_hw_st_h2c_err_process() - Function to dump MM H2C Error information - * - * @dev_hndl: device handle - * @buf: Bufffer for the debug info to be dumped in - * @buflen: Length of the buffer - * - * Return: void - *****************************************************************************/ -static void qdma_hw_st_h2c_err_process(void *dev_hndl) -{ - int i = 0; - uint32_t st_h2c_err_reg_list[] = { - QDMA_OFFSET_H2C_ERR_STAT, - QDMA_OFFSET_H2C_FIRST_ERR_QID, - QDMA_OFFSET_H2C_DBG_REG0, - QDMA_OFFSET_H2C_DBG_REG1, - QDMA_OFFSET_H2C_DBG_REG2, - QDMA_OFFSET_H2C_DBG_REG3, - QDMA_OFFSET_H2C_DBG_REG4 - }; - int st_h2c_err_num_regs = sizeof(st_h2c_err_reg_list)/sizeof(uint32_t); - - for (i = 0; i < st_h2c_err_num_regs; i++) { - qdma_dump_reg_info(dev_hndl, st_h2c_err_reg_list[i], - 1, NULL, 0); - } -} - - -/*****************************************************************************/ -/** - * qdma_hw_st_c2h_err_process() - Function to dump MM H2C Error information - * - * @dev_hndl: device handle - * @buf: Bufffer for the debug info to be dumped in - * @buflen: Length of the buffer - * - * Return: void - *****************************************************************************/ -static void qdma_hw_st_c2h_err_process(void *dev_hndl) -{ - int i = 0; - uint32_t st_c2h_err_reg_list[] = { - QDMA_OFFSET_C2H_ERR_STAT, - QDMA_OFFSET_C2H_FATAL_ERR_STAT, - QDMA_OFFSET_C2H_FIRST_ERR_QID, - QDMA_OFFSET_C2H_STAT_S_AXIS_C2H_ACCEPTED, - QDMA_OFFSET_C2H_STAT_S_AXIS_CMPT_ACCEPTED, - QDMA_OFFSET_C2H_STAT_DESC_RSP_PKT_ACCEPTED, - QDMA_OFFSET_C2H_STAT_AXIS_PKG_CMP, - QDMA_OFFSET_C2H_STAT_DEBUG_DMA_ENG_0, - QDMA_OFFSET_C2H_STAT_DEBUG_DMA_ENG_1, - QDMA_OFFSET_C2H_STAT_DEBUG_DMA_ENG_2, - QDMA_OFFSET_C2H_STAT_DEBUG_DMA_ENG_3, - QDMA_OFFSET_C2H_STAT_DESC_RSP_DROP_ACCEPTED, - QDMA_OFFSET_C2H_STAT_DESC_RSP_ERR_ACCEPTED - }; - int st_c2h_err_num_regs = sizeof(st_c2h_err_reg_list)/sizeof(uint32_t); - - for (i = 0; i < st_c2h_err_num_regs; i++) { - qdma_dump_reg_info(dev_hndl, st_c2h_err_reg_list[i], - 1, NULL, 0); - } -} - - -/*****************************************************************************/ -/** - * qdma_hw_get_error_name() - Function to get the error in string format - * - * @err_idx: error index - * - * Return: string - success and NULL on failure - *****************************************************************************/ -const char *qdma_hw_get_error_name(uint32_t err_idx) -{ - if (err_idx >= QDMA_ERRS_ALL) { - qdma_log_error("%s: err_idx=%d is invalid, returning NULL\n", - __func__, (enum qdma_error_idx)err_idx); - return NULL; - } - - return qdma_err_info[(enum qdma_error_idx)err_idx].err_name; -} - -/*****************************************************************************/ -/** - * qdma_hw_error_process() - Function to find the error that got - * triggered and call the handler qdma_hw_error_handler of that - * particular error. - * - * @dev_hndl: device handle - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -int qdma_hw_error_process(void *dev_hndl) -{ - uint32_t glbl_err_stat = 0, err_stat = 0; - uint32_t bit = 0, i = 0; - int32_t idx = 0; - struct qdma_dev_attributes dev_cap; - uint32_t hw_err_position[TOTAL_LEAF_ERROR_AGGREGATORS] = { - QDMA_DSC_ERR_POISON, - QDMA_TRQ_ERR_UNMAPPED, - QDMA_ST_C2H_ERR_MTY_MISMATCH, - QDMA_ST_FATAL_ERR_MTY_MISMATCH, - QDMA_ST_H2C_ERR_ZERO_LEN_DESC, - QDMA_SBE_ERR_MI_H2C0_DAT, - QDMA_DBE_ERR_MI_H2C0_DAT - }; - - if (!dev_hndl) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - qdma_get_device_attributes(dev_hndl, &dev_cap); - - glbl_err_stat = qdma_reg_read(dev_hndl, QDMA_OFFSET_GLBL_ERR_STAT); - if (!glbl_err_stat) - return QDMA_HW_ERR_NOT_DETECTED; - - qdma_log_info("addr = 0x%08x val = 0x%08x", - QDMA_OFFSET_GLBL_ERR_STAT, - glbl_err_stat); - for (i = 0; i < TOTAL_LEAF_ERROR_AGGREGATORS; i++) { - bit = hw_err_position[i]; - - if ((!dev_cap.st_en) && (bit == QDMA_ST_C2H_ERR_MTY_MISMATCH || - bit == QDMA_ST_FATAL_ERR_MTY_MISMATCH || - bit == QDMA_ST_H2C_ERR_ZERO_LEN_DESC)) - continue; - - err_stat = qdma_reg_read(dev_hndl, - qdma_err_info[bit].stat_reg_addr); - - if (err_stat) { - qdma_log_info("addr = 0x%08x val = 0x%08x", - qdma_err_info[bit].stat_reg_addr, - err_stat); - - qdma_err_info[bit].qdma_hw_err_process( - dev_hndl); - - for (idx = bit; idx < all_hw_errs[i]; idx++) { - /* call the platform specific handler */ - if (err_stat & qdma_err_info[idx].leaf_err_mask) - qdma_log_error("%s detected %s", - __func__, - qdma_hw_get_error_name(idx)); - } - - qdma_reg_write(dev_hndl, - qdma_err_info[bit].stat_reg_addr, - err_stat); - - } - - } - - /* Write 1 to the global status register to clear the bits */ - qdma_reg_write(dev_hndl, QDMA_OFFSET_GLBL_ERR_STAT, glbl_err_stat); - - return QDMA_SUCCESS; -} - - -/*****************************************************************************/ -/** - * qdma_hw_error_enable() - Function to enable all or a specific error - * - * @dev_hndl: device handle - * @err_idx: error index - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -int qdma_hw_error_enable(void *dev_hndl, uint32_t err_idx) -{ - uint32_t idx = 0, i = 0; - uint32_t reg_val = 0; - struct qdma_dev_attributes dev_cap; - - if (!dev_hndl) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - if (err_idx > QDMA_ERRS_ALL) { - qdma_log_error("%s: err_idx=%d is invalid, err:%d\n", - __func__, err_idx, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - qdma_get_device_attributes(dev_hndl, &dev_cap); - - if (err_idx == QDMA_ERRS_ALL) { - for (i = 0; i < TOTAL_LEAF_ERROR_AGGREGATORS; i++) { - - idx = all_hw_errs[i]; - - /* Don't access streaming registers in - * MM only bitstreams - */ - if (!dev_cap.st_en) { - if (idx == QDMA_ST_C2H_ERR_ALL || - idx == QDMA_ST_FATAL_ERR_ALL || - idx == QDMA_ST_H2C_ERR_ALL) - continue; - } - - reg_val = qdma_err_info[idx].leaf_err_mask; - qdma_reg_write(dev_hndl, - qdma_err_info[idx].mask_reg_addr, reg_val); - - reg_val = qdma_reg_read(dev_hndl, - QDMA_OFFSET_GLBL_ERR_MASK); - reg_val |= FIELD_SET( - qdma_err_info[idx].global_err_mask, 1); - qdma_reg_write(dev_hndl, QDMA_OFFSET_GLBL_ERR_MASK, - reg_val); - } - - } else { - /* Don't access streaming registers in MM only bitstreams - * QDMA_C2H_ERR_MTY_MISMATCH to QDMA_H2C_ERR_ALL are all - * ST errors - */ - if (!dev_cap.st_en) { - if (err_idx >= QDMA_ST_C2H_ERR_MTY_MISMATCH && - err_idx <= QDMA_ST_H2C_ERR_ALL) - return QDMA_SUCCESS; - } - - reg_val = qdma_reg_read(dev_hndl, - qdma_err_info[err_idx].mask_reg_addr); - reg_val |= FIELD_SET(qdma_err_info[err_idx].leaf_err_mask, 1); - qdma_reg_write(dev_hndl, - qdma_err_info[err_idx].mask_reg_addr, reg_val); - - reg_val = qdma_reg_read(dev_hndl, QDMA_OFFSET_GLBL_ERR_MASK); - reg_val |= FIELD_SET(qdma_err_info[err_idx].global_err_mask, 1); - qdma_reg_write(dev_hndl, QDMA_OFFSET_GLBL_ERR_MASK, reg_val); - } - - return QDMA_SUCCESS; -} - - -/*****************************************************************************/ -/** - * qdma_soft_dump_config_regs() - Function to get qdma config register dump in a - * buffer - * - * @dev_hndl: device handle - * @is_vf: Whether PF or VF - * @buf : pointer to buffer to be filled - * @buflen : Length of the buffer - * - * Return: Length up-till the buffer is filled -success and < 0 - failure - *****************************************************************************/ -int qdma_soft_dump_config_regs(void *dev_hndl, uint8_t is_vf, - char *buf, uint32_t buflen) -{ - uint32_t i = 0, j = 0; - struct xreg_info *reg_info; - uint32_t num_regs = - sizeof(qdma_config_regs) / sizeof((qdma_config_regs)[0]); - uint32_t len = 0, val = 0; - int rv = QDMA_SUCCESS; - char name[DEBGFS_GEN_NAME_SZ] = ""; - struct qdma_dev_attributes dev_cap; - - if (!dev_hndl) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - if (buflen < qdma_soft_reg_dump_buf_len()) { - qdma_log_error("%s: Buffer too small, err:%d\n", - __func__, -QDMA_ERR_NO_MEM); - return -QDMA_ERR_NO_MEM; - } - - if (is_vf) { - qdma_log_error("%s: Wrong API used for VF, err:%d\n", - __func__, - -QDMA_ERR_HWACC_FEATURE_NOT_SUPPORTED); - return -QDMA_ERR_HWACC_FEATURE_NOT_SUPPORTED; - } - - qdma_get_device_attributes(dev_hndl, &dev_cap); - - reg_info = qdma_config_regs; - for (i = 0; i < num_regs; i++) { - if ((GET_CAPABILITY_MASK(dev_cap.mm_en, dev_cap.st_en, - dev_cap.mm_cmpt_en, dev_cap.mailbox_en) - & reg_info[i].mode) == 0) - continue; - - for (j = 0; j < reg_info[i].repeat; j++) { - rv = QDMA_SNPRINTF_S(name, DEBGFS_GEN_NAME_SZ, - DEBGFS_GEN_NAME_SZ, - "%s_%d", reg_info[i].name, j); - if ((rv < 0) || (rv > DEBGFS_GEN_NAME_SZ)) { - qdma_log_error( - "%d:%s QDMA_SNPRINTF_S() failed, err:%d\n", - __LINE__, __func__, - rv); - return -QDMA_ERR_NO_MEM; - } - val = qdma_reg_read(dev_hndl, - (reg_info[i].addr + (j * 4))); - rv = dump_reg(buf + len, buflen - len, - (reg_info[i].addr + (j * 4)), - name, val); - if (rv < 0) { - qdma_log_error( - "%s Buff too small, err:%d\n", - __func__, - -QDMA_ERR_NO_MEM); - return -QDMA_ERR_NO_MEM; - } - len += rv; - } - } - - return len; -} - -/* - * qdma_fill_intr_ctxt() - Helper function to fill interrupt context - * into structure - * - */ -static void qdma_fill_intr_ctxt(struct qdma_indirect_intr_ctxt *intr_ctxt) -{ - ind_intr_ctxt_entries[0].value = intr_ctxt->valid; - ind_intr_ctxt_entries[1].value = intr_ctxt->vec; - ind_intr_ctxt_entries[2].value = intr_ctxt->int_st; - ind_intr_ctxt_entries[3].value = intr_ctxt->color; - ind_intr_ctxt_entries[4].value = - intr_ctxt->baddr_4k & 0xFFFFFFFF; - ind_intr_ctxt_entries[5].value = - (intr_ctxt->baddr_4k >> 32) & 0xFFFFFFFF; - ind_intr_ctxt_entries[6].value = intr_ctxt->page_size; - ind_intr_ctxt_entries[7].value = intr_ctxt->pidx; - ind_intr_ctxt_entries[8].value = intr_ctxt->at; -} - - -static uint32_t qdma_intr_context_buf_len(void) -{ - uint32_t len = 0; - - len += (((sizeof(ind_intr_ctxt_entries) / - sizeof(ind_intr_ctxt_entries[0])) + 1) * - REG_DUMP_SIZE_PER_LINE); - return len; -} - -/* - * dump_intr_context() - Helper function to dump interrupt context into string - * - * return len - length of the string copied into buffer - */ -static int dump_intr_context(struct qdma_indirect_intr_ctxt *intr_ctx, - int ring_index, - char *buf, int buf_sz) -{ - int i = 0; - int n; - int len = 0; - int rv; - char banner[DEBGFS_LINE_SZ]; - - qdma_fill_intr_ctxt(intr_ctx); - - for (i = 0; i < DEBGFS_LINE_SZ - 5; i++) { - rv = QDMA_SNPRINTF_S(banner + i, - (DEBGFS_LINE_SZ - i), - sizeof("-"), "-"); - if ((rv < 0) || (rv > (int)sizeof("-"))) { - qdma_log_error( - "%d:%s QDMA_SNPRINTF_S() failed, err:%d\n", - __LINE__, __func__, - rv); - goto INSUF_BUF_EXIT; - } - } - - /* Interrupt context dump */ - n = sizeof(ind_intr_ctxt_entries) / - sizeof((ind_intr_ctxt_entries)[0]); - for (i = 0; i < n; i++) { - if ((len >= buf_sz) || ((len + DEBGFS_LINE_SZ) >= buf_sz)) - goto INSUF_BUF_EXIT; - - if (i == 0) { - if ((len + (3 * DEBGFS_LINE_SZ)) >= buf_sz) - goto INSUF_BUF_EXIT; - - rv = QDMA_SNPRINTF_S(buf + len, (buf_sz - len), - DEBGFS_LINE_SZ, "\n%s", banner); - if ((rv < 0) || (rv > DEBGFS_LINE_SZ)) { - qdma_log_error( - "%d:%s QDMA_SNPRINTF_S() failed, err:%d\n", - __LINE__, __func__, - rv); - goto INSUF_BUF_EXIT; - } - len += rv; - - rv = QDMA_SNPRINTF_S(buf + len, (buf_sz - len), - DEBGFS_LINE_SZ, "\n%50s %d", - "Interrupt Context for ring#", ring_index); - if ((rv < 0) || (rv > DEBGFS_LINE_SZ)) { - qdma_log_error( - "%d:%s QDMA_SNPRINTF_S() failed, err:%d\n", - __LINE__, __func__, - rv); - goto INSUF_BUF_EXIT; - } - len += rv; - - rv = QDMA_SNPRINTF_S(buf + len, (buf_sz - len), - DEBGFS_LINE_SZ, "\n%s\n", banner); - if ((rv < 0) || (rv > DEBGFS_LINE_SZ)) { - qdma_log_error( - "%d:%s QDMA_SNPRINTF_S() failed, err:%d\n", - __LINE__, __func__, - rv); - goto INSUF_BUF_EXIT; - } - len += rv; - } - - rv = QDMA_SNPRINTF_S(buf + len, (buf_sz - len), DEBGFS_LINE_SZ, - "%-47s %#-10x %u\n", - ind_intr_ctxt_entries[i].name, - ind_intr_ctxt_entries[i].value, - ind_intr_ctxt_entries[i].value); - if ((rv < 0) || (rv > DEBGFS_LINE_SZ)) { - qdma_log_error( - "%d:%s QDMA_SNPRINTF_S() failed, err:%d\n", - __LINE__, __func__, - rv); - goto INSUF_BUF_EXIT; - } - len += rv; - } - - return len; - -INSUF_BUF_EXIT: - if (buf_sz > DEBGFS_LINE_SZ) { - rv = QDMA_SNPRINTF_S((buf + buf_sz - DEBGFS_LINE_SZ), - buf_sz, DEBGFS_LINE_SZ, - "\n\nInsufficient buffer size, partial context dump\n"); - if ((rv < 0) || (rv > DEBGFS_LINE_SZ)) { - qdma_log_error( - "%d:%s QDMA_SNPRINTF_S() failed, err:%d\n", - __LINE__, __func__, - rv); - } - } - - qdma_log_error("%s: Insufficient buffer size, err:%d\n", - __func__, -QDMA_ERR_NO_MEM); - - return -QDMA_ERR_NO_MEM; -} - - -/*****************************************************************************/ -/** - * qdma_dump_intr_context() - Function to get qdma interrupt context dump in a - * buffer - * - * @dev_hndl: device handle - * @hw_qid: queue id - * @buf : pointer to buffer to be filled - * @buflen : Length of the buffer - * - * Return: Length up-till the buffer is filled -success and < 0 - failure - *****************************************************************************/ -int qdma_dump_intr_context(void *dev_hndl, - struct qdma_indirect_intr_ctxt *intr_ctx, - int ring_index, - char *buf, uint32_t buflen) -{ - int rv = 0; - uint32_t req_buflen = 0; - - if (!dev_hndl) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - - return -QDMA_ERR_INV_PARAM; - } - - if (!buf) { - qdma_log_error("%s: buf is NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - - return -QDMA_ERR_INV_PARAM; - } - - if (!intr_ctx) { - qdma_log_error("%s: intr_ctx is NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - - return -QDMA_ERR_INV_PARAM; - } - - req_buflen = qdma_intr_context_buf_len(); - if (buflen < req_buflen) { - qdma_log_error("%s: Too small buffer(%d), reqd(%d), err:%d\n", - __func__, buflen, req_buflen, -QDMA_ERR_NO_MEM); - return -QDMA_ERR_NO_MEM; - } - - rv = dump_intr_context(intr_ctx, ring_index, buf, buflen); - - return rv; -} - -/*****************************************************************************/ -/** - * qdma_soft_dump_queue_context() - Function to get qdma queue context dump in a - * buffer - * - * @dev_hndl: device handle - * @st: Queue Mode (ST or MM) - * @q_type: Queue Type - * @ctxt_data: Context Data - * @buf : pointer to buffer to be filled - * @buflen : Length of the buffer - * - * Return: Length up-till the buffer is filled -success and < 0 - failure - *****************************************************************************/ -int qdma_soft_dump_queue_context(void *dev_hndl, - uint8_t st, - enum qdma_dev_q_type q_type, - struct qdma_descq_context *ctxt_data, - char *buf, uint32_t buflen) -{ - int rv = 0; - uint32_t req_buflen = 0; - - if (!dev_hndl) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - - return -QDMA_ERR_INV_PARAM; - } - - if (!ctxt_data) { - qdma_log_error("%s: ctxt_data is NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - - return -QDMA_ERR_INV_PARAM; - } - - if (!buf) { - qdma_log_error("%s: buf is NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - - return -QDMA_ERR_INV_PARAM; - } - if (q_type >= QDMA_DEV_Q_TYPE_MAX) { - qdma_log_error("%s: invalid q_type, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - - return -QDMA_ERR_INV_PARAM; - } - - rv = qdma_soft_context_buf_len(st, q_type, &req_buflen); - if (rv != QDMA_SUCCESS) - return rv; - - if (buflen < req_buflen) { - qdma_log_error( - "%s: Too small buffer(%d), reqd(%d), err:%d\n", - __func__, buflen, req_buflen, -QDMA_ERR_NO_MEM); - return -QDMA_ERR_NO_MEM; - } - - rv = dump_soft_context(ctxt_data, st, q_type, buf, buflen); - - return rv; -} - -/*****************************************************************************/ -/** - * qdma_read_dump_queue_context() - Function to read and dump the queue - * context in the user-provided buffer. This API is valid only for PF and - * should not be used for VFs. For VF's use qdma_dump_queue_context() API - * after reading the context through mailbox. - * - * @dev_hndl: device handle - * @is_vf: VF or PF - * @hw_qid: queue id - * @st: Queue Mode(ST or MM) - * @q_type: Queue type(H2C/C2H/CMPT)* - * @buf : pointer to buffer to be filled - * @buflen : Length of the buffer - * - * Return: Length up-till the buffer is filled -success and < 0 - failure - *****************************************************************************/ -int qdma_soft_read_dump_queue_context(void *dev_hndl, - uint16_t qid_hw, - uint8_t st, - enum qdma_dev_q_type q_type, - char *buf, uint32_t buflen) -{ - int rv = QDMA_SUCCESS; - uint32_t req_buflen = 0; - struct qdma_descq_context context; - - if (!dev_hndl) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - - return -QDMA_ERR_INV_PARAM; - } - - if (!buf) { - qdma_log_error("%s: buf is NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - - return -QDMA_ERR_INV_PARAM; - } - - if (q_type >= QDMA_DEV_Q_TYPE_MAX) { - qdma_log_error("%s: Not supported for q_type, err = %d\n", - __func__, -QDMA_ERR_INV_PARAM); - - return -QDMA_ERR_INV_PARAM; - } - - rv = qdma_soft_context_buf_len(st, q_type, &req_buflen); - - if (rv != QDMA_SUCCESS) - return rv; - - if (buflen < req_buflen) { - qdma_log_error( - "%s: Too small buffer(%d), reqd(%d), err:%d\n", - __func__, buflen, req_buflen, -QDMA_ERR_NO_MEM); - return -QDMA_ERR_NO_MEM; - } - - qdma_memset(&context, 0, sizeof(struct qdma_descq_context)); - - if (q_type != QDMA_DEV_Q_TYPE_CMPT) { - rv = qdma_sw_ctx_conf(dev_hndl, (uint8_t)q_type, qid_hw, - &(context.sw_ctxt), - QDMA_HW_ACCESS_READ); - if (rv < 0) { - qdma_log_error("%s:sw ctxt read fail, err = %d", - __func__, rv); - return rv; - } - - rv = qdma_hw_ctx_conf(dev_hndl, (uint8_t)q_type, qid_hw, - &(context.hw_ctxt), - QDMA_HW_ACCESS_READ); - if (rv < 0) { - qdma_log_error("%s:hw ctxt read fail, err = %d", - __func__, rv); - return rv; - } - - rv = qdma_credit_ctx_conf(dev_hndl, (uint8_t)q_type, - qid_hw, - &(context.cr_ctxt), - QDMA_HW_ACCESS_READ); - if (rv < 0) { - qdma_log_error("%s:cr ctxt read fail, err = %d", - __func__, rv); - return rv; - } - - if (st && (q_type == QDMA_DEV_Q_TYPE_C2H)) { - rv = qdma_pfetch_ctx_conf(dev_hndl, - qid_hw, &(context.pfetch_ctxt), - QDMA_HW_ACCESS_READ); - if (rv < 0) { - qdma_log_error( - "%s:pftch ctxt read fail, err = %d", - __func__, rv); - return rv; - } - } - } - - if ((st && (q_type == QDMA_DEV_Q_TYPE_C2H)) || - (!st && (q_type == QDMA_DEV_Q_TYPE_CMPT))) { - rv = qdma_cmpt_ctx_conf(dev_hndl, qid_hw, - &(context.cmpt_ctxt), - QDMA_HW_ACCESS_READ); - if (rv < 0) { - qdma_log_error( - "%s:cmpt ctxt read fail, err = %d", - __func__, rv); - return rv; - } - } - - rv = dump_soft_context(&context, st, q_type, buf, buflen); - - return rv; -} -/*****************************************************************************/ -/** - * qdma_is_legacy_intr_pend() - function to get legacy_intr_pending status bit - * - * @dev_hndl: device handle - * - * Return: legacy interrupt pending status bit value - *****************************************************************************/ -int qdma_is_legacy_intr_pend(void *dev_hndl) -{ - uint32_t reg_val; - - if (!dev_hndl) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - reg_val = qdma_reg_read(dev_hndl, QDMA_OFFSET_GLBL_INTERRUPT_CFG); - if (FIELD_GET(QDMA_GLBL_INTR_LGCY_INTR_PEND_MASK, reg_val)) - return QDMA_SUCCESS; - - qdma_log_error("%s: no pending legacy intr, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_HWACC_NO_PEND_LEGCY_INTR; -} - -/*****************************************************************************/ -/** - * qdma_clear_pend_legacy_intr() - function to clear legacy_intr_pending bit - * - * @dev_hndl: device handle - * - * Return: void - *****************************************************************************/ -int qdma_clear_pend_legacy_intr(void *dev_hndl) -{ - uint32_t reg_val; - - if (!dev_hndl) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - reg_val = qdma_reg_read(dev_hndl, QDMA_OFFSET_GLBL_INTERRUPT_CFG); - reg_val |= FIELD_SET(QDMA_GLBL_INTR_LGCY_INTR_PEND_MASK, 1); - qdma_reg_write(dev_hndl, QDMA_OFFSET_GLBL_INTERRUPT_CFG, reg_val); - - return QDMA_SUCCESS; -} - -/*****************************************************************************/ -/** - * qdma_legacy_intr_conf() - function to disable/enable legacy interrupt - * - * @dev_hndl: device handle - * @enable: enable/disable flag. 1 - enable, 0 - disable - * - * Return: void - *****************************************************************************/ -int qdma_legacy_intr_conf(void *dev_hndl, enum status_type enable) -{ - uint32_t reg_val; - - if (!dev_hndl) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - reg_val = qdma_reg_read(dev_hndl, QDMA_OFFSET_GLBL_INTERRUPT_CFG); - reg_val |= FIELD_SET(QDMA_GLBL_INTR_CFG_EN_LGCY_INTR_MASK, enable); - qdma_reg_write(dev_hndl, QDMA_OFFSET_GLBL_INTERRUPT_CFG, reg_val); - - return QDMA_SUCCESS; -} - -/*****************************************************************************/ -/** - * qdma_init_ctxt_memory() - function to initialize the context memory - * - * @dev_hndl: device handle - * - * Return: returns the platform specific error code - *****************************************************************************/ -int qdma_init_ctxt_memory(void *dev_hndl) -{ -#ifdef ENABLE_INIT_CTXT_MEMORY - uint32_t data[QDMA_REG_IND_CTXT_REG_COUNT]; - uint16_t i = 0; - struct qdma_dev_attributes dev_info; - - if (!dev_hndl) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - qdma_memset(data, 0, sizeof(uint32_t) * QDMA_REG_IND_CTXT_REG_COUNT); - qdma_get_device_attributes(dev_hndl, &dev_info); - - for (; i < dev_info.num_qs; i++) { - int sel = QDMA_CTXT_SEL_SW_C2H; - int rv; - - for (; sel <= QDMA_CTXT_SEL_PFTCH; sel++) { - /** if the st mode(h2c/c2h) not enabled - * in the design, then skip the PFTCH - * and CMPT context setup - */ - if ((dev_info.st_en == 0) && - ((sel == QDMA_CTXT_SEL_PFTCH) || - (sel == QDMA_CTXT_SEL_CMPT))) { - qdma_log_debug("%s: ST context is skipped:", - __func__); - qdma_log_debug("sel = %d\n", sel); - continue; - } - - rv = qdma_indirect_reg_clear(dev_hndl, - (enum ind_ctxt_cmd_sel)sel, i); - if (rv < 0) - return rv; - } - } - - /* fmap */ - for (i = 0; i < dev_info.num_pfs; i++) - qdma_indirect_reg_clear(dev_hndl, - QDMA_CTXT_SEL_FMAP, i); - -#else - if (!dev_hndl) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } -#endif - return QDMA_SUCCESS; - -} - -static int get_reg_entry(uint32_t reg_addr, int *reg_entry) -{ - uint32_t i = 0; - struct xreg_info *reg_info; - uint32_t num_regs = - sizeof(qdma_config_regs)/ - sizeof((qdma_config_regs)[0]); - - reg_info = qdma_config_regs; - - for (i = 0; (i < num_regs - 1); i++) { - if (reg_info[i].addr == reg_addr) { - *reg_entry = i; - break; - } - } - - if (i >= num_regs - 1) { - qdma_log_error("%s: 0x%08x is missing register list, err:%d\n", - __func__, - reg_addr, - -QDMA_ERR_INV_PARAM); - *reg_entry = -1; - return -QDMA_ERR_INV_PARAM; - } - - return 0; -} - -/*****************************************************************************/ -/** - * qdma_soft_dump_config_reg_list() - Dump the registers - * - * @dev_hndl: device handle - * @total_regs : Max registers to read - * @reg_list : array of reg addr and reg values - * @buf : pointer to buffer to be filled - * @buflen : Length of the buffer - * - * Return: returns the platform specific error code - *****************************************************************************/ -int qdma_soft_dump_config_reg_list(void *dev_hndl, uint32_t total_regs, - struct qdma_reg_data *reg_list, char *buf, uint32_t buflen) -{ - uint32_t j = 0, len = 0; - uint32_t reg_count = 0; - int reg_data_entry; - int rv = 0; - char name[DEBGFS_GEN_NAME_SZ] = ""; - struct xreg_info *reg_info = qdma_config_regs; - - if (!dev_hndl) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - if (!buf) { - qdma_log_error("%s: buf is NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - for (reg_count = 0; - (reg_count < total_regs);) { - - rv = get_reg_entry(reg_list[reg_count].reg_addr, - ®_data_entry); - if (rv < 0) { - qdma_log_error("%s: register missing in list, err:%d\n", - __func__, - -QDMA_ERR_INV_PARAM); - return rv; - } - - for (j = 0; j < reg_info[reg_data_entry].repeat; j++) { - rv = QDMA_SNPRINTF_S(name, DEBGFS_GEN_NAME_SZ, - DEBGFS_GEN_NAME_SZ, - "%s_%d", - reg_info[reg_data_entry].name, j); - if ((rv < 0) || (rv > DEBGFS_GEN_NAME_SZ)) { - qdma_log_error( - "%d:%s snprintf failed, err:%d\n", - __LINE__, __func__, - rv); - return -QDMA_ERR_NO_MEM; - } - rv = dump_reg(buf + len, buflen - len, - (reg_info[reg_data_entry].addr + (j * 4)), - name, - reg_list[reg_count + j].reg_val); - if (rv < 0) { - qdma_log_error( - "%s Buff too small, err:%d\n", - __func__, - -QDMA_ERR_NO_MEM); - return -QDMA_ERR_NO_MEM; - } - len += rv; - } - reg_count += j; - } - - return len; -} - - -/*****************************************************************************/ -/** - * qdma_read_reg_list() - read the register values - * - * @dev_hndl: device handle - * @is_vf: Whether PF or VF - * @total_regs : Max registers to read - * @reg_list : array of reg addr and reg values - * - * Return: returns the platform specific error code - *****************************************************************************/ -int qdma_read_reg_list(void *dev_hndl, uint8_t is_vf, - uint16_t reg_rd_group, - uint16_t *total_regs, - struct qdma_reg_data *reg_list) -{ - uint16_t reg_count = 0, i = 0, j = 0; - struct xreg_info *reg_info; - uint32_t num_regs = - sizeof(qdma_config_regs)/ - sizeof((qdma_config_regs)[0]); - struct qdma_dev_attributes dev_cap; - uint32_t reg_start_addr = 0; - int reg_index = 0; - int rv = 0; - - if (!is_vf) { - qdma_log_error("%s: not supported for PF, err:%d\n", - __func__, - -QDMA_ERR_HWACC_FEATURE_NOT_SUPPORTED); - return -QDMA_ERR_HWACC_FEATURE_NOT_SUPPORTED; - } - - if (!dev_hndl) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - if (!reg_list) { - qdma_log_error("%s: reg_list is NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - qdma_get_device_attributes(dev_hndl, &dev_cap); - - switch (reg_rd_group) { - case QDMA_REG_READ_GROUP_1: - reg_start_addr = QDMA_REG_GROUP_1_START_ADDR; - break; - case QDMA_REG_READ_GROUP_2: - reg_start_addr = QDMA_REG_GROUP_2_START_ADDR; - break; - case QDMA_REG_READ_GROUP_3: - reg_start_addr = QDMA_REG_GROUP_3_START_ADDR; - break; - case QDMA_REG_READ_GROUP_4: - reg_start_addr = QDMA_REG_GROUP_4_START_ADDR; - break; - default: - qdma_log_error("%s: Invalid group received\n", - __func__); - return -QDMA_ERR_INV_PARAM; - } - - rv = get_reg_entry(reg_start_addr, ®_index); - if (rv < 0) { - qdma_log_error("%s: register missing in list, err:%d\n", - __func__, - -QDMA_ERR_INV_PARAM); - return rv; - } - reg_info = &qdma_config_regs[reg_index]; - - for (i = 0, reg_count = 0; - ((i < num_regs - 1 - reg_index) && - (reg_count < QDMA_MAX_REGISTER_DUMP)); i++) { - - if (((GET_CAPABILITY_MASK(dev_cap.mm_en, dev_cap.st_en, - dev_cap.mm_cmpt_en, dev_cap.mailbox_en) - & reg_info[i].mode) == 0) || - (reg_info[i].read_type == QDMA_REG_READ_PF_ONLY)) - continue; - - for (j = 0; j < reg_info[i].repeat && - (reg_count < QDMA_MAX_REGISTER_DUMP); - j++) { - reg_list[reg_count].reg_addr = - (reg_info[i].addr + (j * 4)); - reg_list[reg_count].reg_val = - qdma_reg_read(dev_hndl, - reg_list[reg_count].reg_addr); - reg_count++; - } - } - - *total_regs = reg_count; - return rv; -} - -/*****************************************************************************/ -/** - * qdma_write_global_ring_sizes() - function to set the global ring size array - * - * @dev_hndl: device handle - * @index: Index from where the values needs to written - * @count: number of entries to be written - * @glbl_rng_sz: pointer to the array having the values to write - * - * (index + count) shall not be more than 16 - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -static int qdma_write_global_ring_sizes(void *dev_hndl, uint8_t index, - uint8_t count, const uint32_t *glbl_rng_sz) -{ - if (!dev_hndl || !glbl_rng_sz || !count) { - qdma_log_error("%s: dev_hndl=%p glbl_rng_sz=%p, err:%d\n", - __func__, dev_hndl, glbl_rng_sz, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - if ((index + count) > QDMA_NUM_RING_SIZES) { - qdma_log_error("%s: index=%u count=%u > %d, err:%d\n", - __func__, index, count, - QDMA_NUM_RING_SIZES, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - qdma_write_csr_values(dev_hndl, QDMA_OFFSET_GLBL_RNG_SZ, index, count, - glbl_rng_sz); - - return QDMA_SUCCESS; -} - -/*****************************************************************************/ -/** - * qdma_read_global_ring_sizes() - function to get the global rng_sz array - * - * @dev_hndl: device handle - * @index: Index from where the values needs to read - * @count: number of entries to be read - * @glbl_rng_sz: pointer to array to hold the values read - * - * (index + count) shall not be more than 16 - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -static int qdma_read_global_ring_sizes(void *dev_hndl, uint8_t index, - uint8_t count, uint32_t *glbl_rng_sz) -{ - if (!dev_hndl || !glbl_rng_sz || !count) { - qdma_log_error("%s: dev_hndl=%p glbl_rng_sz=%p, err:%d\n", - __func__, dev_hndl, glbl_rng_sz, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - if ((index + count) > QDMA_NUM_RING_SIZES) { - qdma_log_error("%s: index=%u count=%u > %d, err:%d\n", - __func__, index, count, - QDMA_NUM_C2H_BUFFER_SIZES, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - qdma_read_csr_values(dev_hndl, QDMA_OFFSET_GLBL_RNG_SZ, index, count, - glbl_rng_sz); - - return QDMA_SUCCESS; -} - -/*****************************************************************************/ -/** - * qdma_write_global_timer_count() - function to set the timer values - * - * @dev_hndl: device handle - * @glbl_tmr_cnt: pointer to the array having the values to write - * @index: Index from where the values needs to written - * @count: number of entries to be written - * - * (index + count) shall not be more than 16 - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -static int qdma_write_global_timer_count(void *dev_hndl, uint8_t index, - uint8_t count, const uint32_t *glbl_tmr_cnt) -{ - struct qdma_dev_attributes dev_cap; - - - - if (!dev_hndl || !glbl_tmr_cnt || !count) { - qdma_log_error("%s: dev_hndl=%p glbl_tmr_cnt=%p, err:%d\n", - __func__, dev_hndl, glbl_tmr_cnt, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - if ((index + count) > QDMA_NUM_C2H_TIMERS) { - qdma_log_error("%s: index=%u count=%u > %d, err:%d\n", - __func__, index, count, - QDMA_NUM_C2H_TIMERS, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - qdma_get_device_attributes(dev_hndl, &dev_cap); - - if (dev_cap.st_en || dev_cap.mm_cmpt_en) - qdma_write_csr_values(dev_hndl, QDMA_OFFSET_C2H_TIMER_CNT, - index, count, glbl_tmr_cnt); - else { - qdma_log_error("%s: ST or MM cmpt not supported, err:%d\n", - __func__, - -QDMA_ERR_HWACC_FEATURE_NOT_SUPPORTED); - return -QDMA_ERR_HWACC_FEATURE_NOT_SUPPORTED; - } - - return QDMA_SUCCESS; -} - -/*****************************************************************************/ -/** - * qdma_read_global_timer_count() - function to get the timer values - * - * @dev_hndl: device handle - * @index: Index from where the values needs to read - * @count: number of entries to be read - * @glbl_tmr_cnt: pointer to array to hold the values read - * - * (index + count) shall not be more than 16 - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -static int qdma_read_global_timer_count(void *dev_hndl, uint8_t index, - uint8_t count, uint32_t *glbl_tmr_cnt) -{ - struct qdma_dev_attributes dev_cap; - - if (!dev_hndl || !glbl_tmr_cnt || !count) { - qdma_log_error("%s: dev_hndl=%p glbl_tmr_cnt=%p, err:%d\n", - __func__, dev_hndl, glbl_tmr_cnt, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - if ((index + count) > QDMA_NUM_C2H_TIMERS) { - qdma_log_error("%s: index=%u count=%u > %d, err:%d\n", - __func__, index, count, - QDMA_NUM_C2H_TIMERS, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - qdma_get_device_attributes(dev_hndl, &dev_cap); - - if (dev_cap.st_en || dev_cap.mm_cmpt_en) - qdma_read_csr_values(dev_hndl, - QDMA_OFFSET_C2H_TIMER_CNT, index, - count, glbl_tmr_cnt); - else { - qdma_log_error("%s: ST or MM cmpt not supported, err:%d\n", - __func__, - -QDMA_ERR_HWACC_FEATURE_NOT_SUPPORTED); - return -QDMA_ERR_HWACC_FEATURE_NOT_SUPPORTED; - } - - return QDMA_SUCCESS; -} - -/*****************************************************************************/ -/** - * qdma_write_global_counter_threshold() - function to set the counter - * threshold values - * - * @dev_hndl: device handle - * @index: Index from where the values needs to written - * @count: number of entries to be written - * @glbl_cnt_th: pointer to the array having the values to write - * - * (index + count) shall not be more than 16 - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -static int qdma_write_global_counter_threshold(void *dev_hndl, uint8_t index, - uint8_t count, const uint32_t *glbl_cnt_th) -{ - struct qdma_dev_attributes dev_cap; - - if (!dev_hndl || !glbl_cnt_th || !count) { - qdma_log_error("%s: dev_hndl=%p glbl_cnt_th=%p, err:%d\n", - __func__, dev_hndl, glbl_cnt_th, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - if ((index + count) > QDMA_NUM_C2H_COUNTERS) { - qdma_log_error("%s: index=%u count=%u > %d, err:%d\n", - __func__, index, count, - QDMA_NUM_C2H_BUFFER_SIZES, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - qdma_get_device_attributes(dev_hndl, &dev_cap); - - if (dev_cap.st_en || dev_cap.mm_cmpt_en) - qdma_write_csr_values(dev_hndl, QDMA_OFFSET_C2H_CNT_TH, index, - count, glbl_cnt_th); - else { - qdma_log_error("%s: ST or MM cmpt not supported, err:%d\n", - __func__, - -QDMA_ERR_HWACC_FEATURE_NOT_SUPPORTED); - return -QDMA_ERR_HWACC_FEATURE_NOT_SUPPORTED; - } - - return QDMA_SUCCESS; -} - -/*****************************************************************************/ -/** - * qdma_read_global_counter_threshold() - function to get the counter threshold - * values - * - * @dev_hndl: device handle - * @index: Index from where the values needs to read - * @count: number of entries to be read - * @glbl_cnt_th: pointer to array to hold the values read - * - * (index + count) shall not be more than 16 - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -static int qdma_read_global_counter_threshold(void *dev_hndl, uint8_t index, - uint8_t count, uint32_t *glbl_cnt_th) -{ - struct qdma_dev_attributes dev_cap; - - if (!dev_hndl || !glbl_cnt_th || !count) { - qdma_log_error("%s: dev_hndl=%p glbl_cnt_th=%p, err:%d\n", - __func__, dev_hndl, glbl_cnt_th, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - if ((index + count) > QDMA_NUM_C2H_COUNTERS) { - qdma_log_error("%s: index=%u count=%u > %d, err:%d\n", - __func__, index, count, - QDMA_NUM_C2H_COUNTERS, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - qdma_get_device_attributes(dev_hndl, &dev_cap); - - if (dev_cap.st_en || dev_cap.mm_cmpt_en) - qdma_read_csr_values(dev_hndl, QDMA_OFFSET_C2H_CNT_TH, index, - count, glbl_cnt_th); - else { - qdma_log_error("%s: ST or MM cmpt not supported, err:%d\n", - __func__, -QDMA_ERR_HWACC_FEATURE_NOT_SUPPORTED); - return -QDMA_ERR_HWACC_FEATURE_NOT_SUPPORTED; - } - - return QDMA_SUCCESS; -} - -/*****************************************************************************/ -/** - * qdma_write_global_buffer_sizes() - function to set the buffer sizes - * - * @dev_hndl: device handle - * @index: Index from where the values needs to written - * @count: number of entries to be written - * @glbl_buf_sz: pointer to the array having the values to write - * - * (index + count) shall not be more than 16 - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -static int qdma_write_global_buffer_sizes(void *dev_hndl, uint8_t index, - uint8_t count, const uint32_t *glbl_buf_sz) -{ - struct qdma_dev_attributes dev_cap; - - if (!dev_hndl || !glbl_buf_sz || !count) { - qdma_log_error("%s: dev_hndl=%p glbl_buf_sz=%p, err:%d\n", - __func__, dev_hndl, glbl_buf_sz, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - if ((index + count) > QDMA_NUM_C2H_BUFFER_SIZES) { - qdma_log_error("%s: index=%u count=%u > %d, err:%d\n", - __func__, index, count, - QDMA_NUM_C2H_BUFFER_SIZES, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - qdma_get_device_attributes(dev_hndl, &dev_cap); - - if (dev_cap.st_en) - qdma_write_csr_values(dev_hndl, QDMA_OFFSET_C2H_BUF_SZ, index, - count, glbl_buf_sz); - else { - qdma_log_error("%s: ST not supported, err:%d\n", - __func__, - -QDMA_ERR_HWACC_FEATURE_NOT_SUPPORTED); - return -QDMA_ERR_HWACC_FEATURE_NOT_SUPPORTED; - } - - return QDMA_SUCCESS; -} - -/*****************************************************************************/ -/** - * qdma_read_global_buffer_sizes() - function to get the buffer sizes - * - * @dev_hndl: device handle - * @index: Index from where the values needs to read - * @count: number of entries to be read - * @glbl_buf_sz: pointer to array to hold the values read - * - * (index + count) shall not be more than 16 - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -static int qdma_read_global_buffer_sizes(void *dev_hndl, uint8_t index, - uint8_t count, uint32_t *glbl_buf_sz) -{ - struct qdma_dev_attributes dev_cap; - - if (!dev_hndl || !glbl_buf_sz || !count) { - qdma_log_error("%s: dev_hndl=%p glbl_buf_sz=%p, err:%d\n", - __func__, dev_hndl, glbl_buf_sz, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - if ((index + count) > QDMA_NUM_C2H_BUFFER_SIZES) { - qdma_log_error("%s: index=%u count=%u > %d, err:%d\n", - __func__, index, count, - QDMA_NUM_C2H_BUFFER_SIZES, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - qdma_get_device_attributes(dev_hndl, &dev_cap); - - if (dev_cap.st_en) - qdma_read_csr_values(dev_hndl, QDMA_OFFSET_C2H_BUF_SZ, index, - count, glbl_buf_sz); - else { - qdma_log_error("%s: ST is not supported, err:%d\n", - __func__, - -QDMA_ERR_HWACC_FEATURE_NOT_SUPPORTED); - return -QDMA_ERR_HWACC_FEATURE_NOT_SUPPORTED; - } - - return QDMA_SUCCESS; -} - -/*****************************************************************************/ -/** - * qdma_global_csr_conf() - function to configure global csr - * - * @dev_hndl: device handle - * @index: Index from where the values needs to read - * @count: number of entries to be read - * @csr_val: uint32_t pointer to csr value - * @csr_type: Type of the CSR (qdma_global_csr_type enum) to configure - * @access_type HW access type (qdma_hw_access_type enum) value - * QDMA_HW_ACCESS_CLEAR - Not supported - * QDMA_HW_ACCESS_INVALIDATE - Not supported - * - * (index + count) shall not be more than 16 - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -int qdma_global_csr_conf(void *dev_hndl, uint8_t index, uint8_t count, - uint32_t *csr_val, - enum qdma_global_csr_type csr_type, - enum qdma_hw_access_type access_type) -{ - int rv = QDMA_SUCCESS; - - switch (csr_type) { - case QDMA_CSR_RING_SZ: - switch (access_type) { - case QDMA_HW_ACCESS_READ: - rv = qdma_read_global_ring_sizes( - dev_hndl, - index, - count, - csr_val); - break; - case QDMA_HW_ACCESS_WRITE: - rv = qdma_write_global_ring_sizes( - dev_hndl, - index, - count, - csr_val); - break; - default: - qdma_log_error("%s: access_type(%d) invalid, err:%d\n", - __func__, - access_type, - -QDMA_ERR_INV_PARAM); - rv = -QDMA_ERR_INV_PARAM; - break; - } - break; - case QDMA_CSR_TIMER_CNT: - switch (access_type) { - case QDMA_HW_ACCESS_READ: - rv = qdma_read_global_timer_count( - dev_hndl, - index, - count, - csr_val); - break; - case QDMA_HW_ACCESS_WRITE: - rv = qdma_write_global_timer_count( - dev_hndl, - index, - count, - csr_val); - break; - default: - qdma_log_error("%s: access_type(%d) invalid, err:%d\n", - __func__, - access_type, - -QDMA_ERR_INV_PARAM); - rv = -QDMA_ERR_INV_PARAM; - break; - } - break; - case QDMA_CSR_CNT_TH: - switch (access_type) { - case QDMA_HW_ACCESS_READ: - rv = - qdma_read_global_counter_threshold( - dev_hndl, - index, - count, - csr_val); - break; - case QDMA_HW_ACCESS_WRITE: - rv = - qdma_write_global_counter_threshold( - dev_hndl, - index, - count, - csr_val); - break; - default: - qdma_log_error("%s: access_type(%d) invalid, err:%d\n", - __func__, - access_type, - -QDMA_ERR_INV_PARAM); - rv = -QDMA_ERR_INV_PARAM; - break; - } - break; - case QDMA_CSR_BUF_SZ: - switch (access_type) { - case QDMA_HW_ACCESS_READ: - rv = - qdma_read_global_buffer_sizes(dev_hndl, - index, - count, - csr_val); - break; - case QDMA_HW_ACCESS_WRITE: - rv = - qdma_write_global_buffer_sizes(dev_hndl, - index, - count, - csr_val); - break; - default: - qdma_log_error("%s: access_type(%d) invalid, err:%d\n", - __func__, - access_type, - -QDMA_ERR_INV_PARAM); - rv = -QDMA_ERR_INV_PARAM; - break; - } - break; - default: - qdma_log_error("%s: csr_type(%d) invalid, err:%d\n", - __func__, - csr_type, - -QDMA_ERR_INV_PARAM); - rv = -QDMA_ERR_INV_PARAM; - break; - } - - return rv; -} - -/*****************************************************************************/ -/** - * qdma_global_writeback_interval_write() - function to set the writeback - * interval - * - * @dev_hndl device handle - * @wb_int: Writeback Interval - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -static int qdma_global_writeback_interval_write(void *dev_hndl, - enum qdma_wrb_interval wb_int) -{ - uint32_t reg_val; - struct qdma_dev_attributes dev_cap; - - if (!dev_hndl) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", __func__, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - if (wb_int >= QDMA_NUM_WRB_INTERVALS) { - qdma_log_error("%s: wb_int=%d is invalid, err:%d\n", - __func__, wb_int, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - qdma_get_device_attributes(dev_hndl, &dev_cap); - - if (dev_cap.st_en || dev_cap.mm_cmpt_en) { - reg_val = qdma_reg_read(dev_hndl, QDMA_OFFSET_GLBL_DSC_CFG); - reg_val |= FIELD_SET(QDMA_GLBL_DSC_CFG_WB_ACC_INT_MASK, wb_int); - - qdma_reg_write(dev_hndl, QDMA_OFFSET_GLBL_DSC_CFG, reg_val); - } else { - qdma_log_error("%s: ST or MM cmpt not supported, err:%d\n", - __func__, -QDMA_ERR_HWACC_FEATURE_NOT_SUPPORTED); - return -QDMA_ERR_HWACC_FEATURE_NOT_SUPPORTED; - } - - return QDMA_SUCCESS; -} - -/*****************************************************************************/ -/** - * qdma_global_writeback_interval_read() - function to get the writeback - * interval - * - * @dev_hndl: device handle - * @wb_int: pointer to the data to hold Writeback Interval - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -static int qdma_global_writeback_interval_read(void *dev_hndl, - enum qdma_wrb_interval *wb_int) -{ - uint32_t reg_val; - struct qdma_dev_attributes dev_cap; - - if (!dev_hndl) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", __func__, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - if (!wb_int) { - qdma_log_error("%s: wb_int is NULL, err:%d\n", __func__, - -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - qdma_get_device_attributes(dev_hndl, &dev_cap); - - if (dev_cap.st_en || dev_cap.mm_cmpt_en) { - reg_val = qdma_reg_read(dev_hndl, QDMA_OFFSET_GLBL_DSC_CFG); - *wb_int = (enum qdma_wrb_interval)FIELD_GET( - QDMA_GLBL_DSC_CFG_WB_ACC_INT_MASK, reg_val); - } else { - qdma_log_error("%s: ST or MM cmpt not supported, err:%d\n", - __func__, -QDMA_ERR_HWACC_FEATURE_NOT_SUPPORTED); - return -QDMA_ERR_HWACC_FEATURE_NOT_SUPPORTED; - } - - return QDMA_SUCCESS; -} - -/*****************************************************************************/ -/** - * qdma_global_writeback_interval_conf() - function to configure - * the writeback interval - * - * @dev_hndl: device handle - * @wb_int: pointer to the data to hold Writeback Interval - * @access_type HW access type (qdma_hw_access_type enum) value - * QDMA_HW_ACCESS_CLEAR - Not supported - * QDMA_HW_ACCESS_INVALIDATE - Not supported - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -int qdma_global_writeback_interval_conf(void *dev_hndl, - enum qdma_wrb_interval *wb_int, - enum qdma_hw_access_type access_type) -{ - int rv = QDMA_SUCCESS; - - switch (access_type) { - case QDMA_HW_ACCESS_READ: - rv = qdma_global_writeback_interval_read(dev_hndl, wb_int); - break; - case QDMA_HW_ACCESS_WRITE: - rv = qdma_global_writeback_interval_write(dev_hndl, *wb_int); - break; - case QDMA_HW_ACCESS_CLEAR: - case QDMA_HW_ACCESS_INVALIDATE: - default: - qdma_log_error("%s: access_type(%d) invalid, err:%d\n", - __func__, - access_type, - -QDMA_ERR_INV_PARAM); - rv = -QDMA_ERR_INV_PARAM; - break; - } - - return rv; -} - - -/*****************************************************************************/ -/** - * qdma_mm_channel_conf() - Function to enable/disable the MM channel - * - * @dev_hndl: device handle - * @channel: MM channel number - * @is_c2h: Queue direction. Set 1 for C2H and 0 for H2C - * @enable: Enable or disable MM channel - * - * Presently, we have only 1 MM channel - * - * Return: 0 - success and < 0 - failure - *****************************************************************************/ -int qdma_mm_channel_conf(void *dev_hndl, uint8_t channel, uint8_t is_c2h, - uint8_t enable) -{ - uint32_t reg_addr = (is_c2h) ? QDMA_OFFSET_C2H_MM_CONTROL : - QDMA_OFFSET_H2C_MM_CONTROL; - struct qdma_dev_attributes dev_cap; - - if (!dev_hndl) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - qdma_get_device_attributes(dev_hndl, &dev_cap); - - if (dev_cap.mm_en) { - qdma_reg_write(dev_hndl, - reg_addr + (channel * QDMA_MM_CONTROL_STEP), - enable); - } - - return QDMA_SUCCESS; -} - - -int qdma_dump_reg_info(void *dev_hndl, uint32_t reg_addr, - uint32_t num_regs, char *buf, uint32_t buflen) -{ - uint32_t total_num_regs = qdma_get_config_num_regs(); - struct xreg_info *config_regs = qdma_get_config_regs(); - const char *bitfield_name; - uint32_t i = 0, num_regs_idx = 0, k = 0, j = 0, - bitfield = 0, lsb = 0, msb = 31; - int rv = 0; - uint32_t reg_val; - uint32_t data_len = 0; - - if (!dev_hndl) { - qdma_log_error("%s: dev_handle is NULL, err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - return -QDMA_ERR_INV_PARAM; - } - - for (i = 0; i < total_num_regs; i++) { - if (reg_addr == config_regs[i].addr) { - j = i; - break; - } - } - - if (i == total_num_regs) { - qdma_log_error("%s: Register not found err:%d\n", - __func__, -QDMA_ERR_INV_PARAM); - if (buf) - QDMA_SNPRINTF_S(buf, buflen, - DEBGFS_LINE_SZ, - "Register not found 0x%x\n", reg_addr); - return -QDMA_ERR_INV_PARAM; - } - - num_regs_idx = (j + num_regs < total_num_regs) ? - (j + num_regs) : total_num_regs; - - for (; j < num_regs_idx ; j++) { - reg_val = qdma_reg_read(dev_hndl, - config_regs[j].addr); - - if (buf) { - rv = QDMA_SNPRINTF_S(buf, buflen, - DEBGFS_LINE_SZ, - "\n%-40s 0x%-7x %-#10x %-10d\n", - config_regs[j].name, - config_regs[j].addr, - reg_val, reg_val); - if ((rv < 0) || (rv > DEBGFS_LINE_SZ)) { - qdma_log_error( - "%s: Insufficient buffer, err:%d\n", - __func__, -QDMA_ERR_NO_MEM); - return -QDMA_ERR_NO_MEM; - } - buf += rv; - data_len += rv; - buflen -= rv; - } else - qdma_log_info("%-40s 0x%-7x %-#10x %-10d\n", - config_regs[j].name, - config_regs[j].addr, - reg_val, reg_val); - - - for (k = 0; - k < config_regs[j].num_bitfields; k++) { - - bitfield = - config_regs[j].bitfields[k].field_mask; - bitfield_name = - config_regs[i].bitfields[k].field_name; - lsb = 0; - msb = 31; - - while (!(BIT(lsb) & bitfield)) - lsb++; - - while (!(BIT(msb) & bitfield)) - msb--; - - if (msb != lsb) { - if (buf) { - rv = QDMA_SNPRINTF_S(buf, buflen, - DEBGFS_LINE_SZ, - "%-40s [%2u,%2u] %#-10x\n", - bitfield_name, - msb, lsb, - (reg_val & bitfield) >> - lsb); - if ((rv < 0) || (rv > DEBGFS_LINE_SZ)) { - qdma_log_error( - "%s: Insufficient buffer, err:%d\n", - __func__, - -QDMA_ERR_NO_MEM); - return -QDMA_ERR_NO_MEM; - } - buf += rv; - data_len += rv; - buflen -= rv; - } else - qdma_log_info( - "%-40s [%2u,%2u] %#-10x\n", - bitfield_name, - msb, lsb, - (reg_val & bitfield) >> lsb); - - - } else { - if (buf) { - rv = QDMA_SNPRINTF_S(buf, buflen, - DEBGFS_LINE_SZ, - "%-40s [%5u] %#-10x\n", - bitfield_name, - lsb, - (reg_val & bitfield) >> - lsb); - if ((rv < 0) || (rv > DEBGFS_LINE_SZ)) { - qdma_log_error( - "%s: Insufficient buffer, err:%d\n", - __func__, - -QDMA_ERR_NO_MEM); - return -QDMA_ERR_NO_MEM; - } - buf += rv; - data_len += rv; - buflen -= rv; - } else - qdma_log_info( - "%-40s [%5u] %#-10x\n", - bitfield_name, - lsb, - (reg_val & bitfield) >> lsb); - - } - } - } - - return data_len; - -} - diff --git a/QDMA/windows/sys/libqdma/source/qdma_access/qdma_soft_access/qdma_soft_access.h b/QDMA/windows/sys/libqdma/source/qdma_access/qdma_soft_access/qdma_soft_access.h deleted file mode 100644 index f71ee578c..000000000 --- a/QDMA/windows/sys/libqdma/source/qdma_access/qdma_soft_access/qdma_soft_access.h +++ /dev/null @@ -1,292 +0,0 @@ -/* - * Copyright (C) 2020 Xilinx, Inc - * - * Licensed under the Apache License, Version 2.0 (the "License"). You may - * not use this file except in compliance with the License. You may obtain - * a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - */ - -#ifndef __QDMA_SOFT_ACCESS_H_ -#define __QDMA_SOFT_ACCESS_H_ - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * DOC: QDMA common library interface definitions - * - * Header file *qdma_access.h* defines data structures and function signatures - * exported by QDMA common library. - */ - -#include "qdma_platform.h" - -/** - * enum qdma_error_idx - qdma errors - */ -enum qdma_error_idx { - /* Descriptor errors */ - QDMA_DSC_ERR_POISON, - QDMA_DSC_ERR_UR_CA, - QDMA_DSC_ERR_PARAM, - QDMA_DSC_ERR_ADDR, - QDMA_DSC_ERR_TAG, - QDMA_DSC_ERR_FLR, - QDMA_DSC_ERR_TIMEOUT, - QDMA_DSC_ERR_DAT_POISON, - QDMA_DSC_ERR_FLR_CANCEL, - QDMA_DSC_ERR_DMA, - QDMA_DSC_ERR_DSC, - QDMA_DSC_ERR_RQ_CANCEL, - QDMA_DSC_ERR_DBE, - QDMA_DSC_ERR_SBE, - QDMA_DSC_ERR_ALL, - - /* TRQ Errors */ - QDMA_TRQ_ERR_UNMAPPED, - QDMA_TRQ_ERR_QID_RANGE, - QDMA_TRQ_ERR_VF_ACCESS, - QDMA_TRQ_ERR_TCP_TIMEOUT, - QDMA_TRQ_ERR_ALL, - - /* C2H Errors */ - QDMA_ST_C2H_ERR_MTY_MISMATCH, - QDMA_ST_C2H_ERR_LEN_MISMATCH, - QDMA_ST_C2H_ERR_QID_MISMATCH, - QDMA_ST_C2H_ERR_DESC_RSP_ERR, - QDMA_ST_C2H_ERR_ENG_WPL_DATA_PAR_ERR, - QDMA_ST_C2H_ERR_MSI_INT_FAIL, - QDMA_ST_C2H_ERR_ERR_DESC_CNT, - QDMA_ST_C2H_ERR_PORTID_CTXT_MISMATCH, - QDMA_ST_C2H_ERR_PORTID_BYP_IN_MISMATCH, - QDMA_ST_C2H_ERR_CMPT_INV_Q_ERR, - QDMA_ST_C2H_ERR_CMPT_QFULL_ERR, - QDMA_ST_C2H_ERR_CMPT_CIDX_ERR, - QDMA_ST_C2H_ERR_CMPT_PRTY_ERR, - QDMA_ST_C2H_ERR_ALL, - - /* Fatal Errors */ - QDMA_ST_FATAL_ERR_MTY_MISMATCH, - QDMA_ST_FATAL_ERR_LEN_MISMATCH, - QDMA_ST_FATAL_ERR_QID_MISMATCH, - QDMA_ST_FATAL_ERR_TIMER_FIFO_RAM_RDBE, - QDMA_ST_FATAL_ERR_PFCH_II_RAM_RDBE, - QDMA_ST_FATAL_ERR_CMPT_CTXT_RAM_RDBE, - QDMA_ST_FATAL_ERR_PFCH_CTXT_RAM_RDBE, - QDMA_ST_FATAL_ERR_DESC_REQ_FIFO_RAM_RDBE, - QDMA_ST_FATAL_ERR_INT_CTXT_RAM_RDBE, - QDMA_ST_FATAL_ERR_CMPT_COAL_DATA_RAM_RDBE, - QDMA_ST_FATAL_ERR_TUSER_FIFO_RAM_RDBE, - QDMA_ST_FATAL_ERR_QID_FIFO_RAM_RDBE, - QDMA_ST_FATAL_ERR_PAYLOAD_FIFO_RAM_RDBE, - QDMA_ST_FATAL_ERR_WPL_DATA_PAR, - QDMA_ST_FATAL_ERR_ALL, - - /* H2C Errors */ - QDMA_ST_H2C_ERR_ZERO_LEN_DESC, - QDMA_ST_H2C_ERR_CSI_MOP, - QDMA_ST_H2C_ERR_NO_DMA_DSC, - QDMA_ST_H2C_ERR_SBE, - QDMA_ST_H2C_ERR_DBE, - QDMA_ST_H2C_ERR_ALL, - - /* Single bit errors */ - QDMA_SBE_ERR_MI_H2C0_DAT, - QDMA_SBE_ERR_MI_C2H0_DAT, - QDMA_SBE_ERR_H2C_RD_BRG_DAT, - QDMA_SBE_ERR_H2C_WR_BRG_DAT, - QDMA_SBE_ERR_C2H_RD_BRG_DAT, - QDMA_SBE_ERR_C2H_WR_BRG_DAT, - QDMA_SBE_ERR_FUNC_MAP, - QDMA_SBE_ERR_DSC_HW_CTXT, - QDMA_SBE_ERR_DSC_CRD_RCV, - QDMA_SBE_ERR_DSC_SW_CTXT, - QDMA_SBE_ERR_DSC_CPLI, - QDMA_SBE_ERR_DSC_CPLD, - QDMA_SBE_ERR_PASID_CTXT_RAM, - QDMA_SBE_ERR_TIMER_FIFO_RAM, - QDMA_SBE_ERR_PAYLOAD_FIFO_RAM, - QDMA_SBE_ERR_QID_FIFO_RAM, - QDMA_SBE_ERR_TUSER_FIFO_RAM, - QDMA_SBE_ERR_WRB_COAL_DATA_RAM, - QDMA_SBE_ERR_INT_QID2VEC_RAM, - QDMA_SBE_ERR_INT_CTXT_RAM, - QDMA_SBE_ERR_DESC_REQ_FIFO_RAM, - QDMA_SBE_ERR_PFCH_CTXT_RAM, - QDMA_SBE_ERR_WRB_CTXT_RAM, - QDMA_SBE_ERR_PFCH_LL_RAM, - QDMA_SBE_ERR_H2C_PEND_FIFO, - QDMA_SBE_ERR_ALL, - - /* Double bit Errors */ - QDMA_DBE_ERR_MI_H2C0_DAT, - QDMA_DBE_ERR_MI_C2H0_DAT, - QDMA_DBE_ERR_H2C_RD_BRG_DAT, - QDMA_DBE_ERR_H2C_WR_BRG_DAT, - QDMA_DBE_ERR_C2H_RD_BRG_DAT, - QDMA_DBE_ERR_C2H_WR_BRG_DAT, - QDMA_DBE_ERR_FUNC_MAP, - QDMA_DBE_ERR_DSC_HW_CTXT, - QDMA_DBE_ERR_DSC_CRD_RCV, - QDMA_DBE_ERR_DSC_SW_CTXT, - QDMA_DBE_ERR_DSC_CPLI, - QDMA_DBE_ERR_DSC_CPLD, - QDMA_DBE_ERR_PASID_CTXT_RAM, - QDMA_DBE_ERR_TIMER_FIFO_RAM, - QDMA_DBE_ERR_PAYLOAD_FIFO_RAM, - QDMA_DBE_ERR_QID_FIFO_RAM, - QDMA_DBE_ERR_TUSER_FIFO_RAM, - QDMA_DBE_ERR_WRB_COAL_DATA_RAM, - QDMA_DBE_ERR_INT_QID2VEC_RAM, - QDMA_DBE_ERR_INT_CTXT_RAM, - QDMA_DBE_ERR_DESC_REQ_FIFO_RAM, - QDMA_DBE_ERR_PFCH_CTXT_RAM, - QDMA_DBE_ERR_WRB_CTXT_RAM, - QDMA_DBE_ERR_PFCH_LL_RAM, - QDMA_DBE_ERR_H2C_PEND_FIFO, - QDMA_DBE_ERR_ALL, - - QDMA_ERRS_ALL -}; - -struct qdma_hw_err_info { - enum qdma_error_idx idx; - const char *err_name; - uint32_t mask_reg_addr; - uint32_t stat_reg_addr; - uint32_t leaf_err_mask; - uint32_t global_err_mask; - void (*qdma_hw_err_process)(void *dev_hndl); -}; - - -int qdma_set_default_global_csr(void *dev_hndl); - -int qdma_get_version(void *dev_hndl, uint8_t is_vf, - struct qdma_hw_version_info *version_info); - -int qdma_pfetch_ctx_conf(void *dev_hndl, uint16_t hw_qid, - struct qdma_descq_prefetch_ctxt *ctxt, - enum qdma_hw_access_type access_type); - -int qdma_sw_ctx_conf(void *dev_hndl, uint8_t c2h, uint16_t hw_qid, - struct qdma_descq_sw_ctxt *ctxt, - enum qdma_hw_access_type access_type); - -int qdma_fmap_conf(void *dev_hndl, uint16_t func_id, - struct qdma_fmap_cfg *config, - enum qdma_hw_access_type access_type); - -int qdma_cmpt_ctx_conf(void *dev_hndl, uint16_t hw_qid, - struct qdma_descq_cmpt_ctxt *ctxt, - enum qdma_hw_access_type access_type); - -int qdma_hw_ctx_conf(void *dev_hndl, uint8_t c2h, uint16_t hw_qid, - struct qdma_descq_hw_ctxt *ctxt, - enum qdma_hw_access_type access_type); - -int qdma_credit_ctx_conf(void *dev_hndl, uint8_t c2h, uint16_t hw_qid, - struct qdma_descq_credit_ctxt *ctxt, - enum qdma_hw_access_type access_type); - -int qdma_indirect_intr_ctx_conf(void *dev_hndl, uint16_t ring_index, - struct qdma_indirect_intr_ctxt *ctxt, - enum qdma_hw_access_type access_type); - -int qdma_queue_pidx_update(void *dev_hndl, uint8_t is_vf, uint16_t qid, - uint8_t is_c2h, const struct qdma_q_pidx_reg_info *reg_info); - -int qdma_queue_cmpt_cidx_update(void *dev_hndl, uint8_t is_vf, - uint16_t qid, const struct qdma_q_cmpt_cidx_reg_info *reg_info); - -int qdma_queue_intr_cidx_update(void *dev_hndl, uint8_t is_vf, - uint16_t qid, const struct qdma_intr_cidx_reg_info *reg_info); - -int qdma_init_ctxt_memory(void *dev_hndl); - -int qdma_legacy_intr_conf(void *dev_hndl, enum status_type enable); - -int qdma_clear_pend_legacy_intr(void *dev_hndl); - -int qdma_is_legacy_intr_pend(void *dev_hndl); - -int qdma_dump_intr_context(void *dev_hndl, - struct qdma_indirect_intr_ctxt *intr_ctx, - int ring_index, - char *buf, uint32_t buflen); - -uint32_t qdma_soft_reg_dump_buf_len(void); - -uint32_t qdma_get_config_num_regs(void); - -struct xreg_info *qdma_get_config_regs(void); - -int qdma_soft_context_buf_len(uint8_t st, - enum qdma_dev_q_type q_type, uint32_t *buflen); - -int qdma_soft_dump_config_regs(void *dev_hndl, uint8_t is_vf, - char *buf, uint32_t buflen); - -int qdma_soft_dump_queue_context(void *dev_hndl, - uint8_t st, - enum qdma_dev_q_type q_type, - struct qdma_descq_context *ctxt_data, - char *buf, uint32_t buflen); - -int qdma_soft_read_dump_queue_context(void *dev_hndl, - uint16_t qid_hw, - uint8_t st, - enum qdma_dev_q_type q_type, - char *buf, uint32_t buflen); - -int qdma_hw_error_process(void *dev_hndl); - -const char *qdma_hw_get_error_name(uint32_t err_idx); - -int qdma_hw_error_enable(void *dev_hndl, uint32_t err_idx); - -int qdma_get_device_attributes(void *dev_hndl, - struct qdma_dev_attributes *dev_info); - -int qdma_get_user_bar(void *dev_hndl, uint8_t is_vf, - uint8_t func_id, uint8_t *user_bar); - -int qdma_soft_dump_config_reg_list(void *dev_hndl, - uint32_t total_regs, - struct qdma_reg_data *reg_list, - char *buf, uint32_t buflen); - -int qdma_read_reg_list(void *dev_hndl, uint8_t is_vf, - uint16_t reg_rd_group, - uint16_t *total_regs, - struct qdma_reg_data *reg_list); - -int qdma_global_csr_conf(void *dev_hndl, uint8_t index, uint8_t count, - uint32_t *csr_val, - enum qdma_global_csr_type csr_type, - enum qdma_hw_access_type access_type); - -int qdma_global_writeback_interval_conf(void *dev_hndl, - enum qdma_wrb_interval *wb_int, - enum qdma_hw_access_type access_type); - -int qdma_mm_channel_conf(void *dev_hndl, uint8_t channel, uint8_t is_c2h, - uint8_t enable); - -int qdma_dump_reg_info(void *dev_hndl, uint32_t reg_addr, - uint32_t num_regs, char *buf, uint32_t buflen); - -#ifdef __cplusplus -} -#endif - -#endif /* __QDMA_SOFT_ACCESS_H_ */ diff --git a/QDMA/windows/sys/libqdma/source/qdma_access/qdma_soft_access/qdma_soft_reg.h b/QDMA/windows/sys/libqdma/source/qdma_access/qdma_soft_access/qdma_soft_reg.h deleted file mode 100644 index 38b35e9cf..000000000 --- a/QDMA/windows/sys/libqdma/source/qdma_access/qdma_soft_access/qdma_soft_reg.h +++ /dev/null @@ -1,582 +0,0 @@ -/* - * Copyright (C) 2020 Xilinx, Inc - * - * Licensed under the Apache License, Version 2.0 (the "License"). You may - * not use this file except in compliance with the License. You may obtain - * a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - */ - -#ifndef __QDMA_SOFT_REG_H__ -#define __QDMA_SOFT_REG_H__ - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * User defined helper macros for masks and shifts. If the same macros are - * defined in linux kernel code , then undefined them and used the user - * defined macros - */ -#ifdef CHAR_BIT -#undef CHAR_BIT -#endif -#define CHAR_BIT 8 - -#ifdef BIT -#undef BIT -#endif -#define BIT(n) (1u << (n)) - -#ifdef BITS_PER_BYTE -#undef BITS_PER_BYTE -#endif -#define BITS_PER_BYTE CHAR_BIT - -#ifdef BITS_PER_LONG -#undef BITS_PER_LONG -#endif -#define BITS_PER_LONG (sizeof(uint32_t) * BITS_PER_BYTE) - -#ifdef BITS_PER_LONG_LONG -#undef BITS_PER_LONG_LONG -#endif -#define BITS_PER_LONG_LONG (sizeof(uint64_t) * BITS_PER_BYTE) - -#ifdef GENMASK -#undef GENMASK -#endif -#define GENMASK(h, l) \ - ((0xFFFFFFFF << (l)) & (0xFFFFFFFF >> (BITS_PER_LONG - 1 - (h)))) - -#ifdef GENMASK_ULL -#undef GENMASK_ULL -#endif -#define GENMASK_ULL(h, l) \ - ((0xFFFFFFFFFFFFFFFF << (l)) & \ - (0xFFFFFFFFFFFFFFFF >> (BITS_PER_LONG_LONG - 1 - (h)))) - - -#define DEBGFS_LINE_SZ (81) - - -#define QDMA_H2C_THROT_DATA_THRESH 0x4000 -#define QDMA_THROT_EN_DATA 1 -#define QDMA_THROT_EN_REQ 0 -#define QDMA_H2C_THROT_REQ_THRESH 0x60 - -/* - * Q Context programming (indirect) - */ - -#define QDMA_REG_IND_CTXT_REG_COUNT 8 -#define QDMA_REG_IND_CTXT_WCNT_1 1 -#define QDMA_REG_IND_CTXT_WCNT_2 2 -#define QDMA_REG_IND_CTXT_WCNT_3 3 -#define QDMA_REG_IND_CTXT_WCNT_4 4 -#define QDMA_REG_IND_CTXT_WCNT_5 5 -#define QDMA_REG_IND_CTXT_WCNT_6 6 -#define QDMA_REG_IND_CTXT_WCNT_7 7 -#define QDMA_REG_IND_CTXT_WCNT_8 8 - -/* ------------------------- QDMA_TRQ_SEL_IND (0x00800) ----------------*/ -#define QDMA_OFFSET_IND_CTXT_DATA 0x804 -#define QDMA_OFFSET_IND_CTXT_MASK 0x824 -#define QDMA_OFFSET_IND_CTXT_CMD 0x844 -#define QDMA_IND_CTXT_CMD_BUSY_MASK 0x1 - -/** QDMA_IND_REG_SEL_FMAP */ -#define QDMA_FMAP_CTXT_W1_QID_MAX_MASK GENMASK(11, 0) -#define QDMA_FMAP_CTXT_W0_QID_MASK GENMASK(10, 0) - -/** QDMA_IND_REG_SEL_SW_C2H */ -/** QDMA_IND_REG_SEL_SW_H2C */ -#define QDMA_SW_CTXT_W4_INTR_AGGR_MASK BIT(11) -#define QDMA_SW_CTXT_W4_VEC_MASK GENMASK(10, 0) -#define QDMA_SW_CTXT_W3_DSC_H_MASK GENMASK(31, 0) -#define QDMA_SW_CTXT_W2_DSC_L_MASK GENMASK(31, 0) -#define QDMA_SW_CTXT_W1_IS_MM_MASK BIT(31) -#define QDMA_SW_CTXT_W1_MRKR_DIS_MASK BIT(30) -#define QDMA_SW_CTXT_W1_IRQ_REQ_MASK BIT(29) -#define QDMA_SW_CTXT_W1_ERR_WB_SENT_MASK BIT(28) -#define QDMA_SW_CTXT_W1_ERR_MASK GENMASK(27, 26) -#define QDMA_SW_CTXT_W1_IRQ_NO_LAST_MASK BIT(25) -#define QDMA_SW_CTXT_W1_PORT_ID_MASK GENMASK(24, 22) -#define QDMA_SW_CTXT_W1_IRQ_EN_MASK BIT(21) -#define QDMA_SW_CTXT_W1_WBK_EN_MASK BIT(20) -#define QDMA_SW_CTXT_W1_MM_CHN_MASK BIT(19) -#define QDMA_SW_CTXT_W1_BYP_MASK BIT(18) -#define QDMA_SW_CTXT_W1_DSC_SZ_MASK GENMASK(17, 16) -#define QDMA_SW_CTXT_W1_RNG_SZ_MASK GENMASK(15, 12) -#define QDMA_SW_CTXT_W1_FETCH_MAX_MASK GENMASK(7, 5) -#define QDMA_SW_CTXT_W1_AT_MASK BIT(4) -#define QDMA_SW_CTXT_W1_WB_INT_EN_MASK BIT(3) -#define QDMA_SW_CTXT_W1_WBI_CHK_MASK BIT(2) -#define QDMA_SW_CTXT_W1_FCRD_EN_MASK BIT(1) -#define QDMA_SW_CTXT_W1_QEN_MASK BIT(0) -#define QDMA_SW_CTXT_W0_FUNC_ID_MASK GENMASK(24, 17) -#define QDMA_SW_CTXT_W0_IRQ_ARM_MASK BIT(16) -#define QDMA_SW_CTXT_W0_PIDX GENMASK(15, 0) - - - -#define QDMA_PFTCH_CTXT_W1_VALID_MASK BIT(13) -#define QDMA_PFTCH_CTXT_W1_SW_CRDT_H_MASK GENMASK(12, 0) -#define QDMA_PFTCH_CTXT_W0_SW_CRDT_L_MASK GENMASK(31, 29) -#define QDMA_PFTCH_CTXT_W0_Q_IN_PFETCH_MASK BIT(28) -#define QDMA_PFTCH_CTXT_W0_PFETCH_EN_MASK BIT(27) -#define QDMA_PFTCH_CTXT_W0_ERR_MASK BIT(26) -#define QDMA_PFTCH_CTXT_W0_PORT_ID_MASK GENMASK(7, 5) -#define QDMA_PFTCH_CTXT_W0_BUF_SIZE_IDX_MASK GENMASK(4, 1) -#define QDMA_PFTCH_CTXT_W0_BYPASS_MASK BIT(0) - - - - -#define QDMA_COMPL_CTXT_W4_INTR_AGGR_MASK BIT(15) -#define QDMA_COMPL_CTXT_W4_INTR_VEC_MASK GENMASK(14, 4) -#define QDMA_COMPL_CTXT_W4_AT_MASK BIT(3) -#define QDMA_COMPL_CTXT_W4_OVF_CHK_DIS_MASK BIT(2) -#define QDMA_COMPL_CTXT_W4_FULL_UPDT_MASK BIT(1) -#define QDMA_COMPL_CTXT_W4_TMR_RUN_MASK BIT(0) -#define QDMA_COMPL_CTXT_W3_USR_TRG_PND_MASK BIT(31) -#define QDMA_COMPL_CTXT_W3_ERR_MASK GENMASK(30, 29) -#define QDMA_COMPL_CTXT_W3_VALID_MASK BIT(28) -#define QDMA_COMPL_CTXT_W3_CIDX_MASK GENMASK(27, 12) -#define QDMA_COMPL_CTXT_W3_PIDX_H_MASK GENMASK(11, 0) -#define QDMA_COMPL_CTXT_W2_PIDX_L_MASK GENMASK(31, 28) -#define QDMA_COMPL_CTXT_W2_DESC_SIZE_MASK GENMASK(27, 26) -#define QDMA_COMPL_CTXT_W2_BADDR_64_H_MASK GENMASK(25, 0) -#define QDMA_COMPL_CTXT_W1_BADDR_64_L_MASK GENMASK(31, 6) -#define QDMA_COMPL_CTXT_W0_RING_SZ_MASK GENMASK(31, 28) -#define QDMA_COMPL_CTXT_W0_COLOR_MASK BIT(27) -#define QDMA_COMPL_CTXT_W0_INT_ST_MASK GENMASK(26, 25) -#define QDMA_COMPL_CTXT_W0_TIMER_IDX_MASK GENMASK(24, 21) -#define QDMA_COMPL_CTXT_W0_COUNTER_IDX_MASK GENMASK(20, 17) -#define QDMA_COMPL_CTXT_W0_FNC_ID_MASK GENMASK(12, 5) -#define QDMA_COMPL_CTXT_W0_TRIG_MODE_MASK GENMASK(4, 2) -#define QDMA_COMPL_CTXT_W0_EN_INT_MASK BIT(1) -#define QDMA_COMPL_CTXT_W0_EN_STAT_DESC_MASK BIT(0) - -/** QDMA_IND_REG_SEL_HW_C2H */ -/** QDMA_IND_REG_SEL_HW_H2C */ -#define QDMA_HW_CTXT_W1_FETCH_PEND_MASK GENMASK(14, 11) -#define QDMA_HW_CTXT_W1_EVENT_PEND_MASK BIT(10) -#define QDMA_HW_CTXT_W1_IDL_STP_B_MASK BIT(9) -#define QDMA_HW_CTXT_W1_DSC_PND_MASK BIT(8) -#define QDMA_HW_CTXT_W0_CRD_USE_MASK GENMASK(31, 16) -#define QDMA_HW_CTXT_W0_CIDX_MASK GENMASK(15, 0) - -/** QDMA_IND_REG_SEL_CR_C2H */ -/** QDMA_IND_REG_SEL_CR_H2C */ -#define QDMA_CR_CTXT_W0_CREDT_MASK GENMASK(15, 0) - -/** QDMA_IND_REG_SEL_INTR */ - - -#define QDMA_INTR_CTXT_W2_AT_MASK BIT(18) -#define QDMA_INTR_CTXT_W2_PIDX_MASK GENMASK(17, 6) -#define QDMA_INTR_CTXT_W2_PAGE_SIZE_MASK GENMASK(5, 3) -#define QDMA_INTR_CTXT_W2_BADDR_64_MASK GENMASK(2, 0) -#define QDMA_INTR_CTXT_W1_BADDR_64_MASK GENMASK(31, 0) -#define QDMA_INTR_CTXT_W0_BADDR_64_MASK GENMASK(31, 15) -#define QDMA_INTR_CTXT_W0_COLOR_MASK BIT(14) -#define QDMA_INTR_CTXT_W0_INT_ST_MASK BIT(13) -#define QDMA_INTR_CTXT_W0_VEC_ID_MASK GENMASK(11, 1) -#define QDMA_INTR_CTXT_W0_VALID_MASK BIT(0) - - - - - -/* ------------------------ QDMA_TRQ_SEL_GLBL (0x00200)-------------------*/ -#define QDMA_OFFSET_GLBL_RNG_SZ 0x204 -#define QDMA_OFFSET_GLBL_SCRATCH 0x244 -#define QDMA_OFFSET_GLBL_ERR_STAT 0x248 -#define QDMA_OFFSET_GLBL_ERR_MASK 0x24C -#define QDMA_OFFSET_GLBL_DSC_CFG 0x250 -#define QDMA_GLBL_DSC_CFG_WB_ACC_INT_MASK GENMASK(2, 0) -#define QDMA_GLBL_DSC_CFG_MAX_DSC_FETCH_MASK GENMASK(5, 3) -#define QDMA_OFFSET_GLBL_DSC_ERR_STS 0x254 -#define QDMA_OFFSET_GLBL_DSC_ERR_MSK 0x258 -#define QDMA_OFFSET_GLBL_DSC_ERR_LOG0 0x25C -#define QDMA_OFFSET_GLBL_DSC_ERR_LOG1 0x260 -#define QDMA_OFFSET_GLBL_TRQ_ERR_STS 0x264 -#define QDMA_OFFSET_GLBL_TRQ_ERR_MSK 0x268 -#define QDMA_OFFSET_GLBL_TRQ_ERR_LOG 0x26C -#define QDMA_OFFSET_GLBL_DSC_DBG_DAT0 0x270 -#define QDMA_OFFSET_GLBL_DSC_DBG_DAT1 0x274 -#define QDMA_OFFSET_GLBL_DSC_ERR_LOG2 0x27C -#define QDMA_OFFSET_GLBL_INTERRUPT_CFG 0x2C4 -#define QDMA_GLBL_INTR_CFG_EN_LGCY_INTR_MASK BIT(0) -#define QDMA_GLBL_INTR_LGCY_INTR_PEND_MASK BIT(1) - -/* ------------------------- QDMA_TRQ_SEL_C2H (0x00A00) ------------------*/ -#define QDMA_OFFSET_C2H_TIMER_CNT 0xA00 -#define QDMA_OFFSET_C2H_CNT_TH 0xA40 -#define QDMA_OFFSET_C2H_QID2VEC_MAP_QID 0xA80 -#define QDMA_OFFSET_C2H_QID2VEC_MAP 0xA84 -#define QDMA_OFFSET_C2H_STAT_S_AXIS_C2H_ACCEPTED 0xA88 -#define QDMA_OFFSET_C2H_STAT_S_AXIS_CMPT_ACCEPTED 0xA8C -#define QDMA_OFFSET_C2H_STAT_DESC_RSP_PKT_ACCEPTED 0xA90 -#define QDMA_OFFSET_C2H_STAT_AXIS_PKG_CMP 0xA94 -#define QDMA_OFFSET_C2H_STAT_DESC_RSP_ACCEPTED 0xA98 -#define QDMA_OFFSET_C2H_STAT_DESC_RSP_CMP 0xA9C -#define QDMA_OFFSET_C2H_STAT_WRQ_OUT 0xAA0 -#define QDMA_OFFSET_C2H_STAT_WPL_REN_ACCEPTED 0xAA4 -#define QDMA_OFFSET_C2H_STAT_TOTAL_WRQ_LEN 0xAA8 -#define QDMA_OFFSET_C2H_STAT_TOTAL_WPL_LEN 0xAAC -#define QDMA_OFFSET_C2H_BUF_SZ 0xAB0 -#define QDMA_OFFSET_C2H_ERR_STAT 0xAF0 -#define QDMA_OFFSET_C2H_ERR_MASK 0xAF4 -#define QDMA_OFFSET_C2H_FATAL_ERR_STAT 0xAF8 -#define QDMA_OFFSET_C2H_FATAL_ERR_MASK 0xAFC -#define QDMA_OFFSET_C2H_FATAL_ERR_ENABLE 0xB00 -#define QDMA_OFFSET_C2H_ERR_INT 0xB04 -#define QDMA_OFFSET_C2H_PFETCH_CFG 0xB08 -#define QDMA_C2H_EVT_QCNT_TH_MASK GENMASK(31, 25) -#define QDMA_C2H_PFCH_QCNT_MASK GENMASK(24, 18) -#define QDMA_C2H_NUM_PFCH_MASK GENMASK(17, 9) -#define QDMA_C2H_PFCH_FL_TH_MASK GENMASK(8, 0) -#define QDMA_OFFSET_C2H_INT_TIMER_TICK 0xB0C -#define QDMA_OFFSET_C2H_STAT_DESC_RSP_DROP_ACCEPTED 0xB10 -#define QDMA_OFFSET_C2H_STAT_DESC_RSP_ERR_ACCEPTED 0xB14 -#define QDMA_OFFSET_C2H_STAT_DESC_REQ 0xB18 -#define QDMA_OFFSET_C2H_STAT_DEBUG_DMA_ENG_0 0xB1C -#define QDMA_OFFSET_C2H_STAT_DEBUG_DMA_ENG_1 0xB20 -#define QDMA_OFFSET_C2H_STAT_DEBUG_DMA_ENG_2 0xB24 -#define QDMA_OFFSET_C2H_STAT_DEBUG_DMA_ENG_3 0xB28 -#define QDMA_OFFSET_C2H_DBG_PFCH_ERR_CTXT 0xB2C -#define QDMA_OFFSET_C2H_FIRST_ERR_QID 0xB30 -#define QDMA_OFFSET_C2H_STAT_NUM_CMPT_IN 0xB34 -#define QDMA_OFFSET_C2H_STAT_NUM_CMPT_OUT 0xB38 -#define QDMA_OFFSET_C2H_STAT_NUM_CMPT_DRP 0xB3C -#define QDMA_OFFSET_C2H_STAT_NUM_STAT_DESC_OUT 0xB40 -#define QDMA_OFFSET_C2H_STAT_NUM_DSC_CRDT_SENT 0xB44 -#define QDMA_OFFSET_C2H_STAT_NUM_FCH_DSC_RCVD 0xB48 -#define QDMA_OFFSET_C2H_STAT_NUM_BYP_DSC_RCVD 0xB4C -#define QDMA_OFFSET_C2H_WRB_COAL_CFG 0xB50 -#define QDMA_C2H_MAX_BUF_SZ_MASK GENMASK(31, 26) -#define QDMA_C2H_TICK_VAL_MASK GENMASK(25, 14) -#define QDMA_C2H_TICK_CNT_MASK GENMASK(13, 2) -#define QDMA_C2H_SET_GLB_FLUSH_MASK BIT(1) -#define QDMA_C2H_DONE_GLB_FLUSH_MASK BIT(0) -#define QDMA_OFFSET_C2H_INTR_H2C_REQ 0xB54 -#define QDMA_OFFSET_C2H_INTR_C2H_MM_REQ 0xB58 -#define QDMA_OFFSET_C2H_INTR_ERR_INT_REQ 0xB5C -#define QDMA_OFFSET_C2H_INTR_C2H_ST_REQ 0xB60 -#define QDMA_OFFSET_C2H_INTR_H2C_ERR_C2H_MM_MSIX_ACK 0xB64 -#define QDMA_OFFSET_C2H_INTR_H2C_ERR_C2H_MM_MSIX_FAIL 0xB68 -#define QDMA_OFFSET_C2H_INTR_H2C_ERR_C2H_MM_MSIX_NO_MSIX 0xB6C -#define QDMA_OFFSET_C2H_INTR_H2C_ERR_C2H_MM_CTXT_INVAL 0xB70 -#define QDMA_OFFSET_C2H_INTR_C2H_ST_MSIX_ACK 0xB74 -#define QDMA_OFFSET_C2H_INTR_C2H_ST_MSIX_FAIL 0xB78 -#define QDMA_OFFSET_C2H_INTR_C2H_ST_NO_MSIX 0xB7C -#define QDMA_OFFSET_C2H_INTR_C2H_ST_CTXT_INVAL 0xB80 -#define QDMA_OFFSET_C2H_STAT_WR_CMP 0xB84 -#define QDMA_OFFSET_C2H_STAT_DEBUG_DMA_ENG_4 0xB88 -#define QDMA_OFFSET_C2H_STAT_DEBUG_DMA_ENG_5 0xB8C -#define QDMA_OFFSET_C2H_DBG_PFCH_QID 0xB90 -#define QDMA_OFFSET_C2H_DBG_PFCH 0xB94 -#define QDMA_OFFSET_C2H_INT_DEBUG 0xB98 -#define QDMA_OFFSET_C2H_STAT_IMM_ACCEPTED 0xB9C -#define QDMA_OFFSET_C2H_STAT_MARKER_ACCEPTED 0xBA0 -#define QDMA_OFFSET_C2H_STAT_DISABLE_CMP_ACCEPTED 0xBA4 -#define QDMA_OFFSET_C2H_PAYLOAD_FIFO_CRDT_CNT 0xBA8 -#define QDMA_OFFSET_C2H_PFETCH_CACHE_DEPTH 0xBE0 -#define QDMA_OFFSET_C2H_CMPT_COAL_BUF_DEPTH 0xBE4 - -/* ------------------------- QDMA_TRQ_SEL_H2C (0x00E00) ------------------*/ -#define QDMA_OFFSET_H2C_ERR_STAT 0xE00 -#define QDMA_OFFSET_H2C_ERR_MASK 0xE04 -#define QDMA_OFFSET_H2C_FIRST_ERR_QID 0xE08 -#define QDMA_OFFSET_H2C_DBG_REG0 0xE0C -#define QDMA_OFFSET_H2C_DBG_REG1 0xE10 -#define QDMA_OFFSET_H2C_DBG_REG2 0xE14 -#define QDMA_OFFSET_H2C_DBG_REG3 0xE18 -#define QDMA_OFFSET_H2C_DBG_REG4 0xE1C -#define QDMA_OFFSET_H2C_FATAL_ERR_EN 0xE20 -#define QDMA_OFFSET_H2C_REQ_THROT 0xE24 -#define QDMA_H2C_REQ_THROT_EN_REQ_MASK BIT(31) -#define QDMA_H2C_REQ_THRESH_MASK GENMASK(25, 17) -#define QDMA_H2C_REQ_THROT_EN_DATA_MASK BIT(16) -#define QDMA_H2C_DATA_THRESH_MASK GENMASK(15, 0) - - -/* ------------------------- QDMA_TRQ_SEL_H2C_MM (0x1200) ----------------*/ -#define QDMA_OFFSET_H2C_MM_CONTROL 0x1204 -#define QDMA_OFFSET_H2C_MM_CONTROL_W1S 0x1208 -#define QDMA_OFFSET_H2C_MM_CONTROL_W1C 0x120C -#define QDMA_OFFSET_H2C_MM_STATUS 0x1240 -#define QDMA_OFFSET_H2C_MM_STATUS_RC 0x1244 -#define QDMA_OFFSET_H2C_MM_COMPLETED_DESC_COUNT 0x1248 -#define QDMA_OFFSET_H2C_MM_ERR_CODE_EN_MASK 0x1254 -#define QDMA_OFFSET_H2C_MM_ERR_CODE 0x1258 -#define QDMA_OFFSET_H2C_MM_ERR_INFO 0x125C -#define QDMA_OFFSET_H2C_MM_PERF_MON_CONTROL 0x12C0 -#define QDMA_OFFSET_H2C_MM_PERF_MON_CYCLE_COUNT_0 0x12C4 -#define QDMA_OFFSET_H2C_MM_PERF_MON_CYCLE_COUNT_1 0x12C8 -#define QDMA_OFFSET_H2C_MM_PERF_MON_DATA_COUNT_0 0x12CC -#define QDMA_OFFSET_H2C_MM_PERF_MON_DATA_COUNT_1 0x12D0 -#define QDMA_OFFSET_H2C_MM_DEBUG 0x12E8 - -/* ------------------------- QDMA_TRQ_SEL_C2H_MM (0x1000) ----------------*/ -#define QDMA_OFFSET_C2H_MM_CONTROL 0x1004 -#define QDMA_OFFSET_C2H_MM_CONTROL_W1S 0x1008 -#define QDMA_OFFSET_C2H_MM_CONTROL_W1C 0x100C -#define QDMA_OFFSET_C2H_MM_STATUS 0x1040 -#define QDMA_OFFSET_C2H_MM_STATUS_RC 0x1044 -#define QDMA_OFFSET_C2H_MM_COMPLETED_DESC_COUNT 0x1048 -#define QDMA_OFFSET_C2H_MM_ERR_CODE_EN_MASK 0x1054 -#define QDMA_OFFSET_C2H_MM_ERR_CODE 0x1058 -#define QDMA_OFFSET_C2H_MM_ERR_INFO 0x105C -#define QDMA_OFFSET_C2H_MM_PERF_MON_CONTROL 0x10C0 -#define QDMA_OFFSET_C2H_MM_PERF_MON_CYCLE_COUNT_0 0x10C4 -#define QDMA_OFFSET_C2H_MM_PERF_MON_CYCLE_COUNT_1 0x10C8 -#define QDMA_OFFSET_C2H_MM_PERF_MON_DATA_COUNT_0 0x10CC -#define QDMA_OFFSET_C2H_MM_PERF_MON_DATA_COUNT_1 0x10D0 -#define QDMA_OFFSET_C2H_MM_DEBUG 0x10E8 - -/* ------------------------- QDMA_TRQ_SEL_GLBL1 (0x0) -----------------*/ -#define QDMA_OFFSET_CONFIG_BLOCK_ID 0x0 -#define QDMA_CONFIG_BLOCK_ID_MASK GENMASK(31, 16) - - -/* ------------------------- QDMA_TRQ_SEL_GLBL2 (0x00100) ----------------*/ -#define QDMA_OFFSET_GLBL2_ID 0x100 -#define QDMA_OFFSET_GLBL2_PF_BARLITE_INT 0x104 -#define QDMA_GLBL2_PF3_BAR_MAP_MASK GENMASK(23, 18) -#define QDMA_GLBL2_PF2_BAR_MAP_MASK GENMASK(17, 12) -#define QDMA_GLBL2_PF1_BAR_MAP_MASK GENMASK(11, 6) -#define QDMA_GLBL2_PF0_BAR_MAP_MASK GENMASK(5, 0) -#define QDMA_OFFSET_GLBL2_PF_VF_BARLITE_INT 0x108 -#define QDMA_OFFSET_GLBL2_PF_BARLITE_EXT 0x10C -#define QDMA_OFFSET_GLBL2_PF_VF_BARLITE_EXT 0x110 -#define QDMA_OFFSET_GLBL2_CHANNEL_INST 0x114 -#define QDMA_OFFSET_GLBL2_CHANNEL_MDMA 0x118 -#define QDMA_GLBL2_ST_C2H_MASK BIT(16) -#define QDMA_GLBL2_ST_H2C_MASK BIT(17) -#define QDMA_GLBL2_MM_C2H_MASK BIT(8) -#define QDMA_GLBL2_MM_H2C_MASK BIT(0) -#define QDMA_OFFSET_GLBL2_CHANNEL_STRM 0x11C -#define QDMA_OFFSET_GLBL2_CHANNEL_QDMA_CAP 0x120 -#define QDMA_GLBL2_MULTQ_MAX_MASK GENMASK(11, 0) -#define QDMA_OFFSET_GLBL2_CHANNEL_PASID_CAP 0x128 -#define QDMA_OFFSET_GLBL2_CHANNEL_FUNC_RET 0x12C -#define QDMA_OFFSET_GLBL2_SYSTEM_ID 0x130 -#define QDMA_OFFSET_GLBL2_MISC_CAP 0x134 - -#define QDMA_GLBL2_DEVICE_ID_MASK GENMASK(31, 28) -#define QDMA_GLBL2_VIVADO_RELEASE_MASK GENMASK(27, 24) -#define QDMA_GLBL2_VERSAL_IP_MASK GENMASK(23, 20) -#define QDMA_GLBL2_RTL_VERSION_MASK GENMASK(19, 16) -#define QDMA_OFFSET_GLBL2_DBG_PCIE_RQ0 0x1B8 -#define QDMA_OFFSET_GLBL2_DBG_PCIE_RQ1 0x1BC -#define QDMA_OFFSET_GLBL2_DBG_AXIMM_WR0 0x1C0 -#define QDMA_OFFSET_GLBL2_DBG_AXIMM_WR1 0x1C4 -#define QDMA_OFFSET_GLBL2_DBG_AXIMM_RD0 0x1C8 -#define QDMA_OFFSET_GLBL2_DBG_AXIMM_RD1 0x1CC - -/* used for VF bars identification */ -#define QDMA_OFFSET_VF_USER_BAR_ID 0x1018 -#define QDMA_OFFSET_VF_CONFIG_BAR_ID 0x1014 - -/* FLR programming */ -#define QDMA_OFFSET_VF_REG_FLR_STATUS 0x1100 -#define QDMA_OFFSET_PF_REG_FLR_STATUS 0x2500 -#define QDMA_FLR_STATUS_MASK 0x1 - -/* VF qdma version */ -#define QDMA_OFFSET_VF_VERSION 0x1014 -#define QDMA_OFFSET_PF_VERSION 0x2414 -#define QDMA_GLBL2_VF_UNIQUE_ID_MASK GENMASK(31, 16) -#define QDMA_GLBL2_VF_DEVICE_ID_MASK GENMASK(15, 12) -#define QDMA_GLBL2_VF_VIVADO_RELEASE_MASK GENMASK(11, 8) -#define QDMA_GLBL2_VF_VERSAL_IP_MASK GENMASK(7, 4) -#define QDMA_GLBL2_VF_RTL_VERSION_MASK GENMASK(3, 0) - - -/* ------------------------- QDMA_TRQ_SEL_QUEUE_PF (0x18000) ----------------*/ - -#define QDMA_OFFSET_DMAP_SEL_INT_CIDX 0x18000 -#define QDMA_OFFSET_DMAP_SEL_H2C_DSC_PIDX 0x18004 -#define QDMA_OFFSET_DMAP_SEL_C2H_DSC_PIDX 0x18008 -#define QDMA_OFFSET_DMAP_SEL_CMPT_CIDX 0x1800C - -#define QDMA_OFFSET_VF_DMAP_SEL_INT_CIDX 0x3000 -#define QDMA_OFFSET_VF_DMAP_SEL_H2C_DSC_PIDX 0x3004 -#define QDMA_OFFSET_VF_DMAP_SEL_C2H_DSC_PIDX 0x3008 -#define QDMA_OFFSET_VF_DMAP_SEL_CMPT_CIDX 0x300C - -#define QDMA_DMA_SEL_INT_SW_CIDX_MASK GENMASK(15, 0) -#define QDMA_DMA_SEL_INT_RING_IDX_MASK GENMASK(23, 16) -#define QDMA_DMA_SEL_DESC_PIDX_MASK GENMASK(15, 0) -#define QDMA_DMA_SEL_IRQ_EN_MASK BIT(16) -#define QDMA_DMAP_SEL_CMPT_IRQ_EN_MASK BIT(28) -#define QDMA_DMAP_SEL_CMPT_STS_DESC_EN_MASK BIT(27) -#define QDMA_DMAP_SEL_CMPT_TRG_MODE_MASK GENMASK(26, 24) -#define QDMA_DMAP_SEL_CMPT_TMR_CNT_MASK GENMASK(23, 20) -#define QDMA_DMAP_SEL_CMPT_CNT_THRESH_MASK GENMASK(19, 16) -#define QDMA_DMAP_SEL_CMPT_WRB_CIDX_MASK GENMASK(15, 0) - -/* ------------------------- Hardware Errors ------------------------------ */ -#define TOTAL_LEAF_ERROR_AGGREGATORS 7 - -#define QDMA_OFFSET_GLBL_ERR_INT 0xB04 -#define QDMA_GLBL_ERR_FUNC_MASK GENMASK(7, 0) -#define QDMA_GLBL_ERR_VEC_MASK GENMASK(22, 12) -#define QDMA_GLBL_ERR_ARM_MASK BIT(24) - -#define QDMA_OFFSET_GLBL_ERR_STAT 0x248 -#define QDMA_OFFSET_GLBL_ERR_MASK 0x24C -#define QDMA_GLBL_ERR_RAM_SBE_MASK BIT(0) -#define QDMA_GLBL_ERR_RAM_DBE_MASK BIT(1) -#define QDMA_GLBL_ERR_DSC_MASK BIT(2) -#define QDMA_GLBL_ERR_TRQ_MASK BIT(3) -#define QDMA_GLBL_ERR_ST_C2H_MASK BIT(8) -#define QDMA_GLBL_ERR_ST_H2C_MASK BIT(11) - -#define QDMA_OFFSET_C2H_ERR_STAT 0xAF0 -#define QDMA_OFFSET_C2H_ERR_MASK 0xAF4 -#define QDMA_C2H_ERR_MTY_MISMATCH_MASK BIT(0) -#define QDMA_C2H_ERR_LEN_MISMATCH_MASK BIT(1) -#define QDMA_C2H_ERR_QID_MISMATCH_MASK BIT(3) -#define QDMA_C2H_ERR_DESC_RSP_ERR_MASK BIT(4) -#define QDMA_C2H_ERR_ENG_WPL_DATA_PAR_ERR_MASK BIT(6) -#define QDMA_C2H_ERR_MSI_INT_FAIL_MASK BIT(7) -#define QDMA_C2H_ERR_ERR_DESC_CNT_MASK BIT(9) -#define QDMA_C2H_ERR_PORTID_CTXT_MISMATCH_MASK BIT(10) -#define QDMA_C2H_ERR_PORTID_BYP_IN_MISMATCH_MASK BIT(11) -#define QDMA_C2H_ERR_CMPT_INV_Q_ERR_MASK BIT(12) -#define QDMA_C2H_ERR_CMPT_QFULL_ERR_MASK BIT(13) -#define QDMA_C2H_ERR_CMPT_CIDX_ERR_MASK BIT(14) -#define QDMA_C2H_ERR_CMPT_PRTY_ERR_MASK BIT(15) -#define QDMA_C2H_ERR_ALL_MASK 0xFEDB - -#define QDMA_OFFSET_C2H_FATAL_ERR_STAT 0xAF8 -#define QDMA_OFFSET_C2H_FATAL_ERR_MASK 0xAFC -#define QDMA_C2H_FATAL_ERR_MTY_MISMATCH_MASK BIT(0) -#define QDMA_C2H_FATAL_ERR_LEN_MISMATCH_MASK BIT(1) -#define QDMA_C2H_FATAL_ERR_QID_MISMATCH_MASK BIT(3) -#define QDMA_C2H_FATAL_ERR_TIMER_FIFO_RAM_RDBE_MASK BIT(4) -#define QDMA_C2H_FATAL_ERR_PFCH_II_RAM_RDBE_MASK BIT(8) -#define QDMA_C2H_FATAL_ERR_CMPT_CTXT_RAM_RDBE_MASK BIT(9) -#define QDMA_C2H_FATAL_ERR_PFCH_CTXT_RAM_RDBE_MASK BIT(10) -#define QDMA_C2H_FATAL_ERR_DESC_REQ_FIFO_RAM_RDBE_MASK BIT(11) -#define QDMA_C2H_FATAL_ERR_INT_CTXT_RAM_RDBE_MASK BIT(12) -#define QDMA_C2H_FATAL_ERR_CMPT_COAL_DATA_RAM_RDBE_MASK BIT(14) -#define QDMA_C2H_FATAL_ERR_TUSER_FIFO_RAM_RDBE_MASK BIT(15) -#define QDMA_C2H_FATAL_ERR_QID_FIFO_RAM_RDBE_MASK BIT(16) -#define QDMA_C2H_FATAL_ERR_PAYLOAD_FIFO_RAM_RDBE_MASK BIT(17) -#define QDMA_C2H_FATAL_ERR_WPL_DATA_PAR_MASK BIT(18) -#define QDMA_C2H_FATAL_ERR_ALL_MASK 0x7DF1B - -#define QDMA_OFFSET_H2C_ERR_STAT 0xE00 -#define QDMA_OFFSET_H2C_ERR_MASK 0xE04 -#define QDMA_H2C_ERR_ZERO_LEN_DESC_MASK BIT(0) -#define QDMA_H2C_ERR_CSI_MOP_MASK BIT(1) -#define QDMA_H2C_ERR_NO_DMA_DSC_MASK BIT(2) -#define QDMA_H2C_ERR_SBE_MASK BIT(3) -#define QDMA_H2C_ERR_DBE_MASK BIT(4) -#define QDMA_H2C_ERR_ALL_MASK 0x1F - -#define QDMA_OFFSET_GLBL_DSC_ERR_STAT 0x254 -#define QDMA_OFFSET_GLBL_DSC_ERR_MASK 0x258 -#define QDMA_GLBL_DSC_ERR_POISON_MASK BIT(0) -#define QDMA_GLBL_DSC_ERR_UR_CA_MASK BIT(1) -#define QDMA_GLBL_DSC_ERR_PARAM_MASK BIT(2) -#define QDMA_GLBL_DSC_ERR_ADDR_MASK BIT(3) -#define QDMA_GLBL_DSC_ERR_TAG_MASK BIT(4) -#define QDMA_GLBL_DSC_ERR_FLR_MASK BIT(5) -#define QDMA_GLBL_DSC_ERR_TIMEOUT_MASK BIT(9) -#define QDMA_GLBL_DSC_ERR_DAT_POISON_MASK BIT(16) -#define QDMA_GLBL_DSC_ERR_FLR_CANCEL_MASK BIT(19) -#define QDMA_GLBL_DSC_ERR_DMA_MASK BIT(20) -#define QDMA_GLBL_DSC_ERR_DSC_MASK BIT(21) -#define QDMA_GLBL_DSC_ERR_RQ_CANCEL_MASK BIT(22) -#define QDMA_GLBL_DSC_ERR_DBE_MASK BIT(23) -#define QDMA_GLBL_DSC_ERR_SBE_MASK BIT(24) -#define QDMA_GLBL_DSC_ERR_ALL_MASK 0x1F9023F - -#define QDMA_OFFSET_GLBL_TRQ_ERR_STAT 0x264 -#define QDMA_OFFSET_GLBL_TRQ_ERR_MASK 0x268 -#define QDMA_GLBL_TRQ_ERR_UNMAPPED_MASK BIT(0) -#define QDMA_GLBL_TRQ_ERR_QID_RANGE_MASK BIT(1) -#define QDMA_GLBL_TRQ_ERR_VF_ACCESS_MASK BIT(2) -#define QDMA_GLBL_TRQ_ERR_TCP_TIMEOUT_MASK BIT(3) -#define QDMA_GLBL_TRQ_ERR_ALL_MASK 0xF - -#define QDMA_OFFSET_RAM_SBE_STAT 0xF4 -#define QDMA_OFFSET_RAM_SBE_MASK 0xF0 -#define QDMA_SBE_ERR_MI_H2C0_DAT_MASK BIT(0) -#define QDMA_SBE_ERR_MI_C2H0_DAT_MASK BIT(4) -#define QDMA_SBE_ERR_H2C_RD_BRG_DAT_MASK BIT(9) -#define QDMA_SBE_ERR_H2C_WR_BRG_DAT_MASK BIT(10) -#define QDMA_SBE_ERR_C2H_RD_BRG_DAT_MASK BIT(11) -#define QDMA_SBE_ERR_C2H_WR_BRG_DAT_MASK BIT(12) -#define QDMA_SBE_ERR_FUNC_MAP_MASK BIT(13) -#define QDMA_SBE_ERR_DSC_HW_CTXT_MASK BIT(14) -#define QDMA_SBE_ERR_DSC_CRD_RCV_MASK BIT(15) -#define QDMA_SBE_ERR_DSC_SW_CTXT_MASK BIT(16) -#define QDMA_SBE_ERR_DSC_CPLI_MASK BIT(17) -#define QDMA_SBE_ERR_DSC_CPLD_MASK BIT(18) -#define QDMA_SBE_ERR_PASID_CTXT_RAM_MASK BIT(19) -#define QDMA_SBE_ERR_TIMER_FIFO_RAM_MASK BIT(20) -#define QDMA_SBE_ERR_PAYLOAD_FIFO_RAM_MASK BIT(21) -#define QDMA_SBE_ERR_QID_FIFO_RAM_MASK BIT(22) -#define QDMA_SBE_ERR_TUSER_FIFO_RAM_MASK BIT(23) -#define QDMA_SBE_ERR_WRB_COAL_DATA_RAM_MASK BIT(24) -#define QDMA_SBE_ERR_INT_QID2VEC_RAM_MASK BIT(25) -#define QDMA_SBE_ERR_INT_CTXT_RAM_MASK BIT(26) -#define QDMA_SBE_ERR_DESC_REQ_FIFO_RAM_MASK BIT(27) -#define QDMA_SBE_ERR_PFCH_CTXT_RAM_MASK BIT(28) -#define QDMA_SBE_ERR_WRB_CTXT_RAM_MASK BIT(29) -#define QDMA_SBE_ERR_PFCH_LL_RAM_MASK BIT(30) -#define QDMA_SBE_ERR_H2C_PEND_FIFO_MASK BIT(31) -#define QDMA_SBE_ERR_ALL_MASK 0xFFFFFF11 - -#define QDMA_OFFSET_RAM_DBE_STAT 0xFC -#define QDMA_OFFSET_RAM_DBE_MASK 0xF8 -#define QDMA_DBE_ERR_MI_H2C0_DAT_MASK BIT(0) -#define QDMA_DBE_ERR_MI_C2H0_DAT_MASK BIT(4) -#define QDMA_DBE_ERR_H2C_RD_BRG_DAT_MASK BIT(9) -#define QDMA_DBE_ERR_H2C_WR_BRG_DAT_MASK BIT(10) -#define QDMA_DBE_ERR_C2H_RD_BRG_DAT_MASK BIT(11) -#define QDMA_DBE_ERR_C2H_WR_BRG_DAT_MASK BIT(12) -#define QDMA_DBE_ERR_FUNC_MAP_MASK BIT(13) -#define QDMA_DBE_ERR_DSC_HW_CTXT_MASK BIT(14) -#define QDMA_DBE_ERR_DSC_CRD_RCV_MASK BIT(15) -#define QDMA_DBE_ERR_DSC_SW_CTXT_MASK BIT(16) -#define QDMA_DBE_ERR_DSC_CPLI_MASK BIT(17) -#define QDMA_DBE_ERR_DSC_CPLD_MASK BIT(18) -#define QDMA_DBE_ERR_PASID_CTXT_RAM_MASK BIT(19) -#define QDMA_DBE_ERR_TIMER_FIFO_RAM_MASK BIT(20) -#define QDMA_DBE_ERR_PAYLOAD_FIFO_RAM_MASK BIT(21) -#define QDMA_DBE_ERR_QID_FIFO_RAM_MASK BIT(22) -#define QDMA_DBE_ERR_TUSER_FIFO_RAM_MASK BIT(23) -#define QDMA_DBE_ERR_WRB_COAL_DATA_RAM_MASK BIT(24) -#define QDMA_DBE_ERR_INT_QID2VEC_RAM_MASK BIT(25) -#define QDMA_DBE_ERR_INT_CTXT_RAM_MASK BIT(26) -#define QDMA_DBE_ERR_DESC_REQ_FIFO_RAM_MASK BIT(27) -#define QDMA_DBE_ERR_PFCH_CTXT_RAM_MASK BIT(28) -#define QDMA_DBE_ERR_WRB_CTXT_RAM_MASK BIT(29) -#define QDMA_DBE_ERR_PFCH_LL_RAM_MASK BIT(30) -#define QDMA_DBE_ERR_H2C_PEND_FIFO_MASK BIT(31) -#define QDMA_DBE_ERR_ALL_MASK 0xFFFFFF11 - -#define QDMA_OFFSET_MBOX_BASE_VF 0x1000 -#define QDMA_OFFSET_MBOX_BASE_PF 0x2400 - -#ifdef __cplusplus -} -#endif - -#endif /* __QDMA_SOFT_REG_H__ */ diff --git a/QDMA/windows/sys/libqdma/source/qdma_config.h b/QDMA/windows/sys/libqdma/source/qdma_config.h deleted file mode 100644 index 2cd71932b..000000000 --- a/QDMA/windows/sys/libqdma/source/qdma_config.h +++ /dev/null @@ -1,20 +0,0 @@ -/* - * Copyright (C) 2020 Xilinx, Inc - * - * Licensed under the Apache License, Version 2.0 (the "License"). You may - * not use this file except in compliance with the License. You may obtain - * a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - */ - -#pragma once - -#define QDMA_QBASE 0 -#define QDMA_TOTAL_Q 2048 diff --git a/QDMA/windows/sys/libqdma/source/qdma_license.h b/QDMA/windows/sys/libqdma/source/qdma_license.h deleted file mode 100644 index cca956a35..000000000 --- a/QDMA/windows/sys/libqdma/source/qdma_license.h +++ /dev/null @@ -1,18 +0,0 @@ -#ifndef LIBQDMA_QDMA_LICENSE_H_ -#define LIBQDMA_QDMA_LICENSE_H_ -/* - * Copyright (C) 2020 Xilinx, Inc - * - * Licensed under the Apache License, Version 2.0 (the "License"). You may - * not use this file except in compliance with the License. You may obtain - * a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - */ -#endif /* LIBQDMA_QDMA_LICENSE_H_ */ diff --git a/QDMA/windows/sys/libqdma/source/qdma_platform.cpp b/QDMA/windows/sys/libqdma/source/qdma_platform.cpp deleted file mode 100644 index e9400c7a9..000000000 --- a/QDMA/windows/sys/libqdma/source/qdma_platform.cpp +++ /dev/null @@ -1,180 +0,0 @@ -/* - * Copyright (C) 2020 Xilinx, Inc - * - * Licensed under the Apache License, Version 2.0 (the "License"). You may - * not use this file except in compliance with the License. You may obtain - * a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - */ - -#include "qdma.h" -#include "qdma_platform.h" -#include "qdma_access_errors.h" -#include "trace.h" - -#ifdef ENABLE_WPP_TRACING -#include "qdma_platform.tmh" -#endif - -using namespace xlnx; - -/** Xilinx TAG for tagged memory allocations */ -static constexpr ULONG QDMA_MEMPOOL_TAG = 'MADQ'; -static WDFSPINLOCK resource_manager_lock = nullptr; - -struct err_code_map error_code_map_list[] = { - {QDMA_SUCCESS, STATUS_SUCCESS}, - {QDMA_ERR_INV_PARAM, STATUS_INVALID_PARAMETER}, - {QDMA_ERR_NO_MEM, STATUS_BUFFER_TOO_SMALL}, - {QDMA_ERR_HWACC_BUSY_TIMEOUT, STATUS_IO_TIMEOUT}, - {QDMA_ERR_HWACC_INV_CONFIG_BAR, STATUS_INVALID_HW_PROFILE}, - {QDMA_ERR_HWACC_NO_PEND_LEGCY_INTR, STATUS_UNSUCCESSFUL}, - {QDMA_ERR_HWACC_BAR_NOT_FOUND, STATUS_NOT_FOUND}, - {QDMA_ERR_HWACC_FEATURE_NOT_SUPPORTED, STATUS_NOT_SUPPORTED}, - {QDMA_ERR_RM_RES_EXISTS, STATUS_UNSUCCESSFUL}, - {QDMA_ERR_RM_RES_NOT_EXISTS, STATUS_UNSUCCESSFUL}, - {QDMA_ERR_RM_DEV_EXISTS, STATUS_UNSUCCESSFUL}, - {QDMA_ERR_RM_DEV_NOT_EXISTS, STATUS_UNSUCCESSFUL}, - {QDMA_ERR_RM_NO_QUEUES_LEFT, STATUS_UNSUCCESSFUL}, - {QDMA_ERR_RM_QMAX_CONF_REJECTED, STATUS_UNSUCCESSFUL} -}; - - -void qdma_udelay( - UINT32 delay_us) -{ - KeStallExecutionProcessor(delay_us); -} - -/* Suppressing the static analysis tool reported warning. - * Common qdma_access.c file takes care of acquiring and - * releasing the locks properly via callbacks APIs - * NOTE: These callback funtions are intended to use only - * by HW access common code. - */ -#pragma warning(suppress: 28167) -int qdma_reg_access_lock( - void *dev_hndl) -{ - qdma_device *qdma_dev = static_cast(dev_hndl); - WdfSpinLockAcquire(qdma_dev->register_access_lock); - return 0; -} - -#pragma warning(suppress: 28167) -int qdma_reg_access_release( - void *dev_hndl) -{ - qdma_device *qdma_dev = static_cast(dev_hndl); - WdfSpinLockRelease(qdma_dev->register_access_lock); - return 0; -} - -void qdma_reg_write( - void *dev_hndl, - uint32_t reg_offset, - uint32_t val) -{ - qdma_device *qdma_dev = static_cast(dev_hndl); - qdma_dev->qdma_conf_reg_write(reg_offset, (ULONG)val); -} - -uint32_t qdma_reg_read( - void *dev_hndl, - uint32_t reg_offset) -{ - qdma_device *qdma_dev = static_cast(dev_hndl); - return qdma_dev->qdma_conf_reg_read(reg_offset); -} - -void qdma_get_hw_access( - void *dev_hndl, - struct qdma_hw_access **hw) -{ - qdma_device *qdma_dev = static_cast(dev_hndl); - *hw = &qdma_dev->hw; -} - -void qdma_strncpy( - char *dest, - const char *src, - size_t n) -{ - RtlStringCchPrintfA(dest, n, "%s", src); -} - -int qdma_get_err_code( - int acc_err_code) -{ - int n; - - if (acc_err_code < 0) - acc_err_code = -(acc_err_code); - - n = sizeof(error_code_map_list) / sizeof(error_code_map_list[0]); - if (acc_err_code < n) - return (error_code_map_list[acc_err_code].err_code); - else - return STATUS_UNSUCCESSFUL; -} - -void *qdma_calloc( - uint32_t num_blocks, - uint32_t size) -{ - size_t total_size = (size_t)num_blocks * size; - void *ptr = ExAllocatePoolWithTag(NonPagedPoolNx, total_size, QDMA_MEMPOOL_TAG); - if (ptr != NULL) { - RtlZeroMemory(ptr, total_size); - } - - return ptr; -} - -void qdma_memfree( - void *memptr) -{ - ExFreePoolWithTag(memptr, QDMA_MEMPOOL_TAG); -} - -int qdma_resource_lock_init(void) -{ - if (resource_manager_lock == nullptr) { - WDF_OBJECT_ATTRIBUTES attr; - WDF_OBJECT_ATTRIBUTES_INIT(&attr); - attr.ParentObject = WdfGetDriver(); - - NTSTATUS status = WdfSpinLockCreate(&attr, &resource_manager_lock); - if (!NT_SUCCESS(status)) { - TraceError(TRACE_QDMA, "Resource lock creation failed!"); - return -1; - } - } - - return 0; -} - -/* Suppressing the static analysis tool reported warning. - * Common qdma_access.c file takes care of acquiring and - * releasing the locks properly via callback APIs - * NOTE: These callback funtions are intended to use only - * by HW access common code. - */ -#pragma warning(suppress: 28167) -void qdma_resource_lock_take(void) -{ - WdfSpinLockAcquire(resource_manager_lock); -} - -#pragma warning(suppress: 28167) -void qdma_resource_lock_give(void) -{ - WdfSpinLockRelease(resource_manager_lock); -} diff --git a/QDMA/windows/sys/libqdma/source/qdma_platform_env.h b/QDMA/windows/sys/libqdma/source/qdma_platform_env.h deleted file mode 100644 index 3aeb023f1..000000000 --- a/QDMA/windows/sys/libqdma/source/qdma_platform_env.h +++ /dev/null @@ -1,43 +0,0 @@ -/* - * Copyright (C) 2020 Xilinx, Inc - * - * Licensed under the Apache License, Version 2.0 (the "License"). You may - * not use this file except in compliance with the License. You may obtain - * a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - */ - -#ifndef LIBQDMA_QDMA_PLATFORM_ENV_H_ -#define LIBQDMA_QDMA_PLATFORM_ENV_H_ - -#pragma once - -#ifndef STRICT -#define STRICT -#endif - -#include -#include -#include -#include -#include -#include - -#include "trace.h" - -#define QDMA_SNPRINTF_S _snprintf_s - -typedef UINT32 uint32_t; -typedef UINT8 uint8_t; -typedef UINT16 uint16_t; -typedef UINT64 uint64_t; -typedef INT32 int32_t; - -#endif /* LIBQDMA_QDMA_PLATFORM_ENV_H_ */ diff --git a/QDMA/windows/sys/libqdma/source/qdma_reg_ext.h b/QDMA/windows/sys/libqdma/source/qdma_reg_ext.h deleted file mode 100644 index caa068e8b..000000000 --- a/QDMA/windows/sys/libqdma/source/qdma_reg_ext.h +++ /dev/null @@ -1,171 +0,0 @@ -/* - * Copyright (C) 2020 Xilinx, Inc - * - * Licensed under the Apache License, Version 2.0 (the "License"). You may - * not use this file except in compliance with the License. You may obtain - * a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - */ - -#pragma once - -#include -#include - -namespace xlnx { - -/* ----------- constants ----------- */ -static constexpr UINT8 DEFAULT_USER_BAR = 1; - -/* register base address */ -static constexpr size_t qdma_trq_cmc_msix_table = 0x0000'2000; -static constexpr size_t qdma_msix_vectors_mask_step = 0x0000'000c; - -/* HW Config Constants */ -static constexpr size_t qdma_max_msix_vectors_per_pf = 8; - -/* ---------- struct definitions ---------- */ -#pragma pack(1) - -/* ---------- descriptor structures ---------- */ -struct c2h_descriptor { - UINT64 addr; -}; -static_assert(sizeof(c2h_descriptor) == (8 * sizeof(UINT8)), "c2h_descriptor must be 8 bytes wide!"); - -struct h2c_descriptor { - UINT16 cdh_flags; /**< Dont care bits */ - UINT16 pld_len; /**< Packet length in bytes */ - UINT16 length; - UINT16 sop : 1; - UINT16 eop : 1; - UINT16 reserved : 14; - UINT64 addr; -}; -static_assert(sizeof(h2c_descriptor) == (16 * sizeof(UINT8)), "h2c_descriptor must be 16 bytes wide!"); - -struct mm_descriptor { - UINT64 addr; - - UINT64 length : 28; - UINT64 valid : 1; - UINT64 sop : 1; - UINT64 eop : 1; - UINT64 reserved_0 : 33; - - UINT64 dest_addr; - - UINT64 reserved_1; -}; -static_assert(sizeof(mm_descriptor) == (32 * sizeof(UINT8)), "mm_descriptor must be 32 bytes wide!"); - -/* interrupt ring entry structure */ -struct intr_entry { - /* Desc bits */ - UINT32 desc_pidx : 16; - UINT32 desc_cidx : 16; - - UINT32 desc_color : 1; - UINT32 desc_int_state : 2; - UINT32 desc_err : 2; - /* source bits */ - UINT32 rsvd : 1; - UINT32 intr_type : 1; - UINT32 qid : 24; - UINT32 color : 1; -}; -static_assert(sizeof(intr_entry) == (8 * sizeof(UINT8)), "intr_entry must be 8 bytes wide!"); - -struct cpm_intr_entry { - /* Desc bits */ - UINT32 desc_pidx : 16; - UINT32 desc_cidx : 16; - - UINT32 desc_color : 1; - UINT32 desc_int_state : 2; - UINT32 desc_err : 4; - /* source bits */ - UINT32 rsvd : 11; - UINT32 err_int : 1; - UINT32 intr_type : 1; - UINT32 qid : 11; - UINT32 color : 1; -}; -static_assert(sizeof(cpm_intr_entry) == (8 * sizeof(UINT8)), "intr_entry must be 8 bytes wide!"); -/* ------ */ - -/* ---------- writeback structures ---------- */ - -/** c2h_wb_header_8B -- C2H Completion data structure - * This includes user defined data, optional color, err bits, etc.,. - * The user defined data has four size options: 8B, 16B, 32B and 64B - * - * The below format is specific to QDMA example design present in vivado - */ -struct c2h_wb_header_8B { - /** @data_frmt : 0 indicates valid length field is present */ - UINT64 data_frmt : 1; - /** @color : Indicates the validity of the entry */ - UINT64 color : 1; - /** @desc_error : Indicates the error status */ - UINT64 desc_error : 1; - /** @desc_used : Indicates whether data descriptor used */ - UINT64 desc_used : 1; - /** @length : Length of the completion entry */ - UINT64 length : 16; - /** @user_rsv : Reserved */ - UINT64 user_rsv : 4; - /** @user_defined_0 : User Defined Data (UDD) */ - UINT64 user_defined_0 : 40; -}; -static_assert(sizeof(c2h_wb_header_8B) == (8 * sizeof(UINT8)), "c2h_wb_header_8B must be 8 bytes wide!"); - -struct c2h_wb_header_16B : c2h_wb_header_8B { - /** @user_defined_1 : User Defined Data (UDD) for 16B completion size */ - UINT64 user_defined_1; -}; -static_assert(sizeof(c2h_wb_header_16B) == (16 * sizeof(UINT8)), "c2h_wb_header_16B must be 16 bytes wide!"); - -struct c2h_wb_header_32B : c2h_wb_header_16B { - /** @user_defined_2 : User Defined Data (UDD) for 32B completion size */ - UINT64 user_defined_2[2]; -}; -static_assert(sizeof(c2h_wb_header_32B) == (32 * sizeof(UINT8)), "c2h_wb_header_32B must be 32 bytes wide!"); - -struct c2h_wb_header_64B : c2h_wb_header_32B { - /** @user_defined_3 : User Defined Data (UDD) for 64B completion size */ - UINT64 user_defined_3[4]; -}; -static_assert(sizeof(c2h_wb_header_64B) == (64 * sizeof(UINT8)), "c2h_wb_header_64B must be 64 bytes wide!"); - - -struct wb_status_base { - UINT16 pidx; - UINT16 cidx; -}; - -struct c2h_wb_status : wb_status_base { - UINT32 color : 1; - UINT32 irq_state : 2; - UINT32 reserved : 29; -}; -static_assert(sizeof(c2h_wb_status) == (sizeof(UINT64)), "c2h_wb_status must be 64 bits wide!"); -static_assert(sizeof(c2h_wb_status) == (sizeof(c2h_wb_header_8B)), "c2h_wb_status and c2h_wb_header_8B must be same size!"); - -struct h2c_wb_status : wb_status_base { - UINT32 reserved_1; -}; -static_assert(sizeof(h2c_wb_status) == (sizeof(UINT64)), "h2c_wb_status must be 64 bits wide!"); - -using mm_wb_status = h2c_wb_status; /* MM wb status has same struct layout as h2c wb */ - -#pragma pack() - -} /* namespace xlnx */ diff --git a/QDMA/windows/sys/libqdma/source/thread.cpp b/QDMA/windows/sys/libqdma/source/thread.cpp deleted file mode 100644 index 65ec4b34e..000000000 --- a/QDMA/windows/sys/libqdma/source/thread.cpp +++ /dev/null @@ -1,341 +0,0 @@ -/* - * Copyright (C) 2020 Xilinx, Inc - * - * Licensed under the Apache License, Version 2.0 (the "License"). You may - * not use this file except in compliance with the License. You may obtain - * a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - */ - -#include "thread.h" -#include "qdma.h" -#include "trace.h" - -#ifdef ENABLE_WPP_TRACING -#include "thread.tmh" -#endif - -using namespace xlnx; -KDEFERRED_ROUTINE queueDataDpc; - -VOID qdma_poll_thread( - PVOID context) -{ - qdma_thread *th = (qdma_thread *)context; - KAFFINITY affinity = (KAFFINITY)1 << th->id; - KeSetSystemAffinityThread(affinity); - - TraceVerbose(TRACE_THREAD, "Thread active on CPU core : %lu", th->id); - - while (1) { - - KeWaitForSingleObject(&th->semaphore, - Executive, - KernelMode, - FALSE, - NULL); - - InterlockedDecrement(&th->sem_count); - - if (th->terminate) { - TraceVerbose(TRACE_THREAD, "Terminating thread on CPU core: %lu", th->id); - PsTerminateSystemThread(STATUS_SUCCESS); - } - - WdfSpinLockAcquire(th->lock); - - PLIST_ENTRY entry; - PLIST_ENTRY temp; - LIST_FOR_EACH_ENTRY_SAFE(&th->poll_ops_head, temp, entry) { - poll_operation_entry *poll_op = CONTAINING_RECORD(entry, poll_operation_entry, list_entry); - poll_op->op.fn(poll_op->op.arg); - } - - WdfSpinLockRelease(th->lock); - } -} - -ULONG thread_manager::get_active_proc_cnt(void) -{ - return KeQueryActiveProcessorCount(NULL); -} - -_Use_decl_annotations_ -VOID -queueDataDpc( - PKDPC dpc, - PVOID context, - PVOID arg1, - PVOID arg2) -{ - UNREFERENCED_PARAMETER(dpc); - UNREFERENCED_PARAMETER(context); - UNREFERENCED_PARAMETER(arg2); - - qdma_thread* thread = static_cast(arg1); - wakeup_thread(thread); -} - -void thread_manager::init_dpc(qdma_thread *thread) { - KeInitializeDpc(&thread->dpc, queueDataDpc, thread); -} - -NTSTATUS thread_manager::create_sys_threads(queue_op_mode mode) -{ - ULONG i = 0; - NTSTATUS status = STATUS_SUCCESS; - - active_processors = get_active_proc_cnt(); - - threads = static_cast(qdma_calloc(active_processors, sizeof(qdma_thread))); - if (nullptr == threads) { - return STATUS_INSUFFICIENT_RESOURCES; - } - - for (i = 0; i < active_processors; ++i) { - /* THREAD DATA INITIALIZATION */ - threads[i].weight = 0; - threads[i].id = i; - threads[i].terminate = false; - INIT_LIST_HEAD(&threads[i].poll_ops_head); - - KeInitializeSemaphore(&threads[i].semaphore, 0, MAXLONG); - - status = PsCreateSystemThread(&threads[i].th_handle, - (ACCESS_MASK)0, - NULL, - (HANDLE)0, - NULL, - qdma_poll_thread, - &threads[i]); - if (!NT_SUCCESS(status)) { - TraceError(TRACE_THREAD, "Failed to create thread on cpu core %d - %!STATUS!", i, status); - break; - } - - ObReferenceObjectByHandle(threads[i].th_handle, - THREAD_ALL_ACCESS, - NULL, - KernelMode, - &threads[i].th_object, - NULL); - - ZwClose(threads[i].th_handle); - - status = WdfSpinLockCreate(WDF_NO_OBJECT_ATTRIBUTES, &threads[i].lock); - if (!NT_SUCCESS(status)) { - TraceError(TRACE_THREAD, "Failed to create thread spinlock for CPU core %d - %!STATUS!", i, status); - active_threads = i + 1; - goto ErrExit; - } - - /* Per Thread DPC creation */ - if (mode != queue_op_mode::POLL_MODE) { - init_dpc(&threads[i]); - } - } - - active_threads = i; - - if ((ULONG)0 == active_threads) { - /* If no thread is active, then return failure. */ - goto ErrExit; - } - - status = WdfSpinLockCreate(WDF_NO_OBJECT_ATTRIBUTES, &lock); - if (!NT_SUCCESS(status)) { - TraceError(TRACE_THREAD, "Failed to create thread manager lock %!STATUS!", status); - goto ErrExit; - } - - TraceVerbose(TRACE_THREAD, "Active threads %lu", active_threads); - - return status; - -ErrExit: - terminate_sys_threads(); - return status; -} - -void thread_manager::terminate_sys_threads(void) -{ - if (nullptr == threads) - return; - - for (ULONG i = 0; i < active_threads; ++i) { - threads[i].terminate = true; - KeReleaseSemaphore(&threads[i].semaphore, 0, 1, FALSE); - } - - for (ULONG i = 0; i < active_threads; ++i) { - if (threads[i].lock) - WdfObjectDelete(threads[i].lock); - - KeWaitForSingleObject(threads[i].th_object, - Executive, - KernelMode, - FALSE, - NULL); - - ObDereferenceObject(threads[i].th_object); - } - - if (lock) { - WdfObjectDelete(lock); - lock = nullptr; - } - - qdma_memfree(threads); - threads = nullptr; -} - -void err_poll_thread(PVOID context) -{ - err_thread *ctx = (err_thread *)context; - LARGE_INTEGER Interval; - Interval.QuadPart = WDF_REL_TIMEOUT_IN_MS(1000); - - while (1) { - ctx->device->hw.qdma_hw_error_process(ctx->device); - - if (ctx->terminate) { - TraceVerbose(TRACE_THREAD, "ctx->terminate"); - PsTerminateSystemThread(STATUS_SUCCESS); - } - - KeDelayExecutionThread(KernelMode, FALSE, &Interval); - } -} - -NTSTATUS thread_manager::create_err_poll_thread(qdma_device *device) -{ - err_th_para = static_cast(qdma_calloc(1, sizeof(err_thread))); - if (nullptr == err_th_para) { - return STATUS_INSUFFICIENT_RESOURCES; - } - - /* THREAD DATA INITIALIZATION */ - err_th_para->terminate = false; - err_th_para->device = device; - - auto status = PsCreateSystemThread(&err_th_para->th_handle, - (ACCESS_MASK)0, - NULL, - (HANDLE)0, - NULL, - err_poll_thread, - err_th_para); - if (!NT_SUCCESS(status)) { - TraceError(TRACE_THREAD, "Failed to create Error handling thread - %!STATUS!", status); - qdma_memfree(err_th_para); - err_th_para = nullptr; - return status; - } - - ObReferenceObjectByHandle(err_th_para->th_handle, - THREAD_ALL_ACCESS, - NULL, - KernelMode, - &err_th_para->th_object, - NULL); - - ZwClose(err_th_para->th_handle); - - TraceVerbose(TRACE_THREAD, "Error handling Thread Active"); - - return STATUS_SUCCESS; -} - -void thread_manager::terminate_err_poll_thread(void) -{ - TraceVerbose(TRACE_THREAD, "terminating error handling thread"); - - if (err_th_para == nullptr) - return; - - err_th_para->terminate = true; - - KeWaitForSingleObject(err_th_para->th_object, - Executive, - KernelMode, - FALSE, - NULL); - - ObDereferenceObject(err_th_para->th_object); - - qdma_memfree(err_th_para); - err_th_para = nullptr; -} - -poll_operation_entry *thread_manager::register_poll_function(poll_op& ops) -{ - UINT32 weight; - UINT32 sel_weight_id; - - WdfSpinLockAcquire(lock); - - weight = threads[0].weight; - sel_weight_id = 0; - - for (ULONG i = 1; i < active_threads; ++i) { - if (weight > threads[i].weight) { - weight = threads[i].weight; - sel_weight_id = i; - } - } - - threads[sel_weight_id].weight++; - WdfSpinLockRelease(lock); - - poll_operation_entry *poll_op_entry = static_cast - (qdma_calloc(1, sizeof(poll_operation_entry))); - if (nullptr == poll_op_entry) { - return nullptr; - } - - poll_op_entry->op.fn = ops.fn; - poll_op_entry->op.arg = ops.arg; - poll_op_entry->thread = &threads[sel_weight_id]; - - /* To Avoid Visual studio static analysis reported warning */ - WDFSPINLOCK th_lock = threads[sel_weight_id].lock; - WdfSpinLockAcquire(th_lock); - LIST_ADD_TAIL(&threads[sel_weight_id].poll_ops_head, &poll_op_entry->list_entry); - WdfSpinLockRelease(th_lock); - - TraceVerbose(TRACE_THREAD, "Poll function registered for thread : %u New Weight : %u, Poll Handle : %p", - sel_weight_id, threads[sel_weight_id].weight, poll_op_entry); - - return poll_op_entry; -} - -void thread_manager::unregister_poll_function(poll_operation_entry *poll_entry) -{ - qdma_thread *thread = poll_entry->thread; - - WdfSpinLockAcquire(lock); - thread->weight--; - WdfSpinLockRelease(lock); - - WdfSpinLockAcquire(thread->lock); - PLIST_ENTRY entry = &(poll_entry->list_entry); - LIST_DEL_NODE(entry); - WdfSpinLockRelease(thread->lock); - - qdma_memfree(poll_entry); -} - -void xlnx::wakeup_thread(qdma_thread* thread) -{ - if (thread->sem_count <= 10) { - InterlockedIncrement(&thread->sem_count); - KeReleaseSemaphore(&thread->semaphore, 0, 1, FALSE); - } -} diff --git a/QDMA/windows/sys/libqdma/source/thread.h b/QDMA/windows/sys/libqdma/source/thread.h deleted file mode 100644 index 7600e80dc..000000000 --- a/QDMA/windows/sys/libqdma/source/thread.h +++ /dev/null @@ -1,86 +0,0 @@ -/* - * Copyright (C) 2020 Xilinx, Inc - * - * Licensed under the Apache License, Version 2.0 (the "License"). You may - * not use this file except in compliance with the License. You may obtain - * a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - */ - -#pragma once - -#include "qdma_platform_env.h" -#include "qdma_config.h" -#include "qdma_exports.h" -#include "qdma_reg_ext.h" - -namespace xlnx { -/* Forward declaration */ -class qdma_device; -struct queue_pair; - -typedef void (*poll_fn) (void *); - -struct poll_op { - poll_fn fn; - void *arg; -}; - -struct qdma_thread { - bool terminate; - ULONG id; - HANDLE th_handle; - KSEMAPHORE semaphore; - volatile LONG sem_count = 0; - void *th_object; - UINT32 weight; - WDFSPINLOCK lock; - /* Per thread DPC object to wake up the thread for completion processing */ - KDPC dpc; - LIST_ENTRY poll_ops_head; -}; - -struct poll_operation_entry { - poll_op op; - qdma_thread *thread; - LIST_ENTRY list_entry; -}; - -struct err_thread { - bool terminate; - HANDLE th_handle; - void *th_object; - qdma_device *device = nullptr; -}; - -struct thread_manager { - ULONG active_processors = 0; - ULONG active_threads = 0; - WDFSPINLOCK lock = nullptr; - - qdma_thread *threads = nullptr; - err_thread *err_th_para = nullptr; - - ULONG get_active_proc_cnt(void); - NTSTATUS create_sys_threads(queue_op_mode mode); - void terminate_sys_threads(void); - void init_dpc(qdma_thread *thread); - NTSTATUS create_err_poll_thread(qdma_device *device); - void terminate_err_poll_thread(void); - - poll_operation_entry *register_poll_function(poll_op& ops); - void unregister_poll_function(poll_operation_entry *poll_entry); -}; - -void wakeup_thread(qdma_thread *thread); - -} /* namespace xlnx */ - - diff --git a/QDMA/windows/sys/libqdma/source/trace.h b/QDMA/windows/sys/libqdma/source/trace.h deleted file mode 100644 index 1dcb7275e..000000000 --- a/QDMA/windows/sys/libqdma/source/trace.h +++ /dev/null @@ -1,94 +0,0 @@ -/* - * Copyright (C) 2020 Xilinx, Inc - * - * Licensed under the Apache License, Version 2.0 (the "License"). You may - * not use this file except in compliance with the License. You may obtain - * a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - */ - -#pragma once - -#if defined(DBG) || defined(ENABLE_WPP) -#define ENABLE_WPP_TRACING -#endif - -/** - * Define the tracing flags. - * - * Tracing GUID - 0bed1f17-aa40-5163-c038-33715b81ae49 - * Trace Name : 'Xilinx-QDMA-Debug' - */ -#define WPP_CONTROL_GUIDS \ - WPP_DEFINE_CONTROL_GUID( \ - QDMATraceGuid, (0bed1f17, aa40, 5163, c038, 33715b81ae49), \ - \ - WPP_DEFINE_BIT(TRACE_PCIE) \ - WPP_DEFINE_BIT(TRACE_INTR) \ - WPP_DEFINE_BIT(TRACE_THREAD) \ - WPP_DEFINE_BIT(TRACE_QDMA) \ - WPP_DEFINE_BIT(TRACE_DBG) \ - WPP_DEFINE_BIT(TRACE_QDMA_ACCESS) \ - ) - -/* WPP_LEVEL_FLAGS_LOGGER and WPP_LEVEL_FLAGS_ENABLED support trace functions - with LEVEL and FLAGS static parameters (in that order) prior to any dynamic - parameters (such as MSG) -*/ -#define WPP_LEVEL_FLAGS_LOGGER(level, flags) \ - WPP_LEVEL_LOGGER(flags) - -#define WPP_LEVEL_FLAGS_ENABLED(level, flags) \ - (WPP_LEVEL_ENABLED(flags) && WPP_CONTROL(WPP_BIT_ ## flags).Level >= level) - -/* Optimize WPP tracing call site conditional checks - - NOTE: This is only safe if we ensure no WPP tracing functions are called - before WPP_INIT_TRACING() or after WPP_CLEANUP(). -*/ -#define WPP_CHECK_INIT - - -// -// This comment block is scanned by the trace preprocessor to define our -// Trace functions. -// -// begin_wpp config -// FUNC TraceVerbose{LEVEL=TRACE_LEVEL_VERBOSE}(FLAGS, MSG, ...); -// FUNC TraceInfo{LEVEL=TRACE_LEVEL_INFORMATION}(FLAGS, MSG, ...); -// FUNC TraceWarning{LEVEL=TRACE_LEVEL_WARNING}(FLAGS, MSG, ...); -// FUNC TraceError{LEVEL=TRACE_LEVEL_ERROR}(FLAGS, MSG, ...); -// FUNC TraceEvents(LEVEL, FLAGS, MSG, ...); -// FUNC qdma_log_error{LEVEL=TRACE_LEVEL_ERROR, FLAGS=TRACE_QDMA_ACCESS}(MSG, ...); -// FUNC qdma_log_debug{LEVEL=TRACE_LEVEL_VERBOSE, FLAGS=TRACE_QDMA_ACCESS}(MSG, ...); -// FUNC qdma_log_info{LEVEL=TRACE_LEVEL_INFORMATION, FLAGS=TRACE_QDMA_ACCESS}(MSG, ...); -// FUNC qdma_log_warn{LEVEL=TRACE_LEVEL_WARNING, FLAGS=TRACE_QDMA_ACCESS}(MSG, ...); -// end_wpp -// - -/** WPP tracing is disabled by default in release configuration. - * so stub out definitions and functions - * - * To Enable WPP Tracing, Enable Run WPP Tracing in settings and - * define MACRO "ENABLE_WPP" - */ -#ifndef ENABLE_WPP_TRACING -#define WPP_INIT_TRACING(driver_object, registry_path) -#define WPP_CLEANUP(driver_object) -#define TraceVerbose(flags, ...) (__VA_ARGS__) -#define TraceInfo(flags, ...) (__VA_ARGS__) -#define TraceWarning(flags, ...) (__VA_ARGS__) -#define TraceError(flags, ...) (__VA_ARGS__) -#define TraceEvents(flags, ...) (__VA_ARGS__) -#define qdma_log_error(...) (__VA_ARGS__) -#define qdma_log_debug(...) (__VA_ARGS__) -#define qdma_log_info(...) (__VA_ARGS__) -#define qdma_log_warn(...) (__VA_ARGS__) -#endif diff --git a/QDMA/windows/sys/libqdma/source/xpcie.cpp b/QDMA/windows/sys/libqdma/source/xpcie.cpp deleted file mode 100644 index ad4ba7694..000000000 --- a/QDMA/windows/sys/libqdma/source/xpcie.cpp +++ /dev/null @@ -1,376 +0,0 @@ -/* - * Copyright (C) 2020 Xilinx, Inc - * - * Licensed under the Apache License, Version 2.0 (the "License"). You may - * not use this file except in compliance with the License. You may obtain - * a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - */ - -#include -#include "xpcie.hpp" -#include "qdma_reg_ext.h" -#include "trace.h" -#include - -#ifdef ENABLE_WPP_TRACING -#include "xpcie.tmh" -#endif - -using namespace xlnx; - -NTSTATUS xpcie_device::map( - const WDFCMRESLIST resources) -{ - num_bars = 0; - const ULONG num_resources = WdfCmResourceListGetCount(resources); - TraceVerbose(TRACE_PCIE, "# PCIe resources = %d", num_resources); - - for (ULONG i = 0; i < num_resources; i++) { - PCM_PARTIAL_RESOURCE_DESCRIPTOR resource = WdfCmResourceListGetDescriptor(resources, i); - if (resource == nullptr) { - TraceError(TRACE_PCIE, "WdfCmResourceListGetDescriptor() fails"); - return STATUS_DEVICE_CONFIGURATION_ERROR; - } - - if (resource->Type == CmResourceTypeMemory) { - /** index = 0 indictaes the first BAR details found in resource list, - index = 1 indicates the second BAR detauls found in resource list, etc., - - This index is not the BAR number. - */ - bars[num_bars].index = num_bars; - bars[num_bars].length = resource->u.Memory.Length; - bars[num_bars].base = static_cast(MmMapIoSpaceEx(resource->u.Memory.Start, - resource->u.Memory.Length, PAGE_READWRITE | PAGE_NOCACHE)); - - if (bars[num_bars].base == nullptr) { - TraceError(TRACE_PCIE, "MmMapIoSpace returned NULL! for BAR%u", num_bars); - return STATUS_DEVICE_CONFIGURATION_ERROR; - } - TraceVerbose(TRACE_PCIE, "MM BAR %d (addr:0x%lld, length:%llu) mapped at 0x%08p", - num_bars, resource->u.Memory.Start.QuadPart, bars[num_bars].length, bars[num_bars].base); - num_bars++; - } - } - - return STATUS_SUCCESS; -} - -void xpcie_device::unmap(void) -{ - /* Unmap any I/O ports. Disconnecting from the interrupt will be done automatically by the framework. */ - for (unsigned int i = 0; i < num_bars; i++) { - if (bars[i].base != nullptr) { - TraceVerbose(TRACE_PCIE, "Unmapping BAR%d, VA:(%p) Length %llu", i, bars[i].base, bars[i].length); - MmUnmapIoSpace(bars[i].base, bars[i].length); - bars[i].base = nullptr; - } - } -} - -NTSTATUS xpcie_device::get_bdf(const WDFDEVICE device, UINT32 &bdf) -{ - ULONG bus_number; - ULONG address; - NTSTATUS status; - ULONG length; - union pci_sbdf dev_sbdf; - - status = WdfDeviceQueryProperty(device, DevicePropertyBusNumber, - sizeof(bus_number), (PVOID)&bus_number, - &length); - if (!NT_SUCCESS(status)) { - TraceError(TRACE_PCIE, - "WdfDeviceQueryProperty failed for DevicePropertyBusNumber: %!STATUS!", - status); - return status; - } - - status = WdfDeviceQueryProperty(device, DevicePropertyAddress, - sizeof(address), (PVOID)&address, - &length); - if (!NT_SUCCESS(status)) { - TraceError(TRACE_PCIE, - "WdfDeviceQueryProperty failed for DevicePropertyAddress: %!STATUS!", - status); - return status; - } - - dev_sbdf.val = 0x0; - dev_sbdf.sbdf.seg_no = (bus_number >> 8) & 0xFFFF; - dev_sbdf.sbdf.bus_no = bus_number & 0xFF; - dev_sbdf.sbdf.dev_no = (address >> 16) & 0xFFFF; - dev_sbdf.sbdf.fun_no = address & 0xFFFF; - - TraceVerbose(TRACE_PCIE, - "PCIe Seg_No : 0x%X, Bus_No : 0x%X, Dev_No: 0x%X, Fun_No: 0x%X", - dev_sbdf.sbdf.seg_no, dev_sbdf.sbdf.bus_no, dev_sbdf.sbdf.dev_no, dev_sbdf.sbdf.fun_no); - - bdf = dev_sbdf.val; - - return STATUS_SUCCESS; -} - -ULONG xpcie_device::get_num_msix_vectors(void) const -{ - return msix_vectors; -} - -NTSTATUS xpcie_device::find_num_msix_vectors( - const WDFDEVICE device) -{ - NTSTATUS status; - ULONG intr_support; - ULONG intr_max; - ULONG length; - DEVPROPTYPE type; - WDF_DEVICE_PROPERTY_DATA dev_prop_data; - - msix_vectors = 0; - - WDF_DEVICE_PROPERTY_DATA_INIT(&dev_prop_data, &DEVPKEY_PciDevice_InterruptSupport); - - status = WdfDeviceQueryPropertyEx(device, &dev_prop_data, sizeof(intr_support), (PVOID)&intr_support, - &length, &type); - - if (!NT_SUCCESS(status)) { - TraceError(TRACE_PCIE, - "WdfDeviceQueryProperty failed for PciDevice_InterruptSupport: %!STATUS!", - status); - return status; - } - - TraceVerbose(TRACE_PCIE, "PciDevice_InterruptSupport: %d, type : %d", intr_support, type); - - if (!(intr_support & DevProp_PciDevice_InterruptType_MsiX)) { - TraceError(TRACE_PCIE, "MSI-X interrupts are not supported"); - return STATUS_NOT_SUPPORTED; - } - - WDF_DEVICE_PROPERTY_DATA_INIT(&dev_prop_data, &DEVPKEY_PciDevice_InterruptMessageMaximum); - - status = WdfDeviceQueryPropertyEx(device, &dev_prop_data, sizeof(intr_max), (PVOID)&intr_max, - &length, &type); - - if (!NT_SUCCESS(status)) { - TraceError(TRACE_PCIE, - "WdfDeviceQueryProperty failed for DEVPKEY_PciDevice_InterruptMessageMaximum: %!STATUS!", - status); - return status; - } - - TraceVerbose(TRACE_PCIE, "InterruptMessageMaximum: %d, type : %d", intr_max, type); - - msix_vectors = intr_max; - - return STATUS_SUCCESS; -} - -NTSTATUS xpcie_device::assign_config_bar(const UINT8 bar_idx) -{ - if (bar_idx > num_bars) - return STATUS_UNSUCCESSFUL; - - config_bar = &bars[bar_idx]; - return STATUS_SUCCESS; -} - - -NTSTATUS xpcie_device::assign_bar_types(const UINT8 user_bar_idx) -{ - UINT32 config_bar_idx = 0; - config_bar_idx = (UINT8)(config_bar - bars); - - if (num_bars > 1) { - user_bar = &bars[user_bar_idx]; - TraceInfo(TRACE_PCIE, "AXI Master Lite BAR %u", (user_bar_idx * 2)); - - if (num_bars > 2) { - for (auto i = 0u; i < num_bars; ++i) { - if (i == user_bar_idx || i == config_bar_idx) - continue; - - bypass_bar = &bars[i]; - TraceInfo(TRACE_PCIE, "AXI Bridge Master BAR %d", (i * 2)); - break; - } - } - } - - return STATUS_SUCCESS; -} - -NTSTATUS xpcie_device::read_bar( - qdma_bar_type bar_type, - size_t offset, - void* data, - size_t size) const -{ - xpcie_device::bar *bar = nullptr; - - if ((nullptr == data) || ((size_t)0 == size)) { - return STATUS_INVALID_PARAMETER; - } - - switch (bar_type) { - case qdma_bar_type::CONFIG_BAR: - bar = config_bar; - break; - case qdma_bar_type::USER_BAR: - bar = user_bar; - break; - case qdma_bar_type::BYPASS_BAR: - bar = bypass_bar; - break; - } - - if (nullptr == bar) - return STATUS_INVALID_PARAMETER; - - return bar->read(offset, data, size); -} - -NTSTATUS xpcie_device::write_bar( - qdma_bar_type bar_type, - size_t offset, - void* data, - size_t size) const -{ - xpcie_device::bar *bar = nullptr; - - if ((nullptr == data) || ((size_t)0 == size)) { - return STATUS_INVALID_PARAMETER; - } - - switch (bar_type) { - case qdma_bar_type::CONFIG_BAR: - bar = config_bar; - break; - case qdma_bar_type::USER_BAR: - bar = user_bar; - break; - case qdma_bar_type::BYPASS_BAR: - bar = bypass_bar; - break; - } - - if (nullptr == bar) - return STATUS_INVALID_PARAMETER; - - return bar->write(offset, data, size); -} - -NTSTATUS xpcie_device::get_bar_info( - qdma_bar_type bar_type, - PVOID &bar_base, - size_t &bar_length) const -{ - switch (bar_type) { - case qdma_bar_type::CONFIG_BAR: - bar_base = (PVOID)config_bar->base; - bar_length = config_bar->length; - break; - case qdma_bar_type::USER_BAR: - bar_base = (PVOID)user_bar->base; - bar_length = user_bar->length; - break; - case qdma_bar_type::BYPASS_BAR: - bar_base = (PVOID)bypass_bar->base; - bar_length = bypass_bar->length; - break; - default: - bar_base = NULL; - bar_length = (size_t)0; - return STATUS_INVALID_PARAMETER; - } - - return STATUS_SUCCESS; -} - -ULONG xpcie_device::conf_reg_read(size_t offset) const -{ - NT_ASSERTMSG("Error: BAR not assigned!", config_bar->base != nullptr); - NT_ASSERTMSG("Error: BAR overrun!", ((offset + sizeof(ULONG)) <= config_bar->length)); - - return READ_REGISTER_ULONG(reinterpret_cast(config_bar->base + offset)); -} - -void xpcie_device::conf_reg_write(size_t offset, ULONG data) const -{ - NT_ASSERTMSG("Error: BAR not assigned!", config_bar->base != nullptr); - NT_ASSERTMSG("Error: BAR overrun!", ((offset + sizeof(ULONG)) <= config_bar->length)); - - WRITE_REGISTER_ULONG(reinterpret_cast(config_bar->base + offset), data); -} - -NTSTATUS xpcie_device::bar::write( - const size_t offset, - void *data, - const size_t size) const -{ - if (base == nullptr) { - TraceError(TRACE_PCIE, "Attempted to access non-mapped BAR!"); - return STATUS_INVALID_ADDRESS; - } - - /* check if request runs over BAR address space */ - if ((offset + size) > length) { - TraceError(TRACE_PCIE, "Error: BAR overrun!"); - return STATUS_INVALID_PARAMETER; - } - - UCHAR *vaddr = base + offset; - - if (size % sizeof(ULONG64) == 0) { - WRITE_REGISTER_BUFFER_ULONG64(reinterpret_cast(vaddr), - static_cast(data), static_cast(size) / sizeof(ULONG64)); - } else if (size % sizeof(ULONG) == 0) { - WRITE_REGISTER_BUFFER_ULONG(reinterpret_cast(vaddr), - static_cast(data), static_cast(size) / sizeof(ULONG)); - } else if (size % sizeof(USHORT) == 0) { - WRITE_REGISTER_BUFFER_USHORT(reinterpret_cast(vaddr), - static_cast(data), static_cast(size) / sizeof(USHORT)); - } else { - WRITE_REGISTER_BUFFER_UCHAR(reinterpret_cast(vaddr), - static_cast(data), static_cast(size)); - } - - return STATUS_SUCCESS; -} - -NTSTATUS xpcie_device::bar::read( - const size_t offset, - void *data, - const size_t size) const -{ - if (base == nullptr) { - TraceError(TRACE_PCIE, "Attempted to access non-mapped BAR!"); - return STATUS_INVALID_ADDRESS; - } - - /* check if request runs over BAR address space */ - if ((offset + size) > length) { - TraceError(TRACE_PCIE, "Error: BAR overrun!"); - return STATUS_INVALID_PARAMETER; - } - - UCHAR* vaddr = base + offset; - - if (size % sizeof(ULONG) == 0) { - READ_REGISTER_BUFFER_ULONG(reinterpret_cast(vaddr), static_cast(data), static_cast(size) / sizeof(ULONG)); - } else if (size % sizeof(USHORT) == 0) { - READ_REGISTER_BUFFER_USHORT(reinterpret_cast(vaddr), static_cast(data), static_cast(size) / sizeof(USHORT)); - } else { - READ_REGISTER_BUFFER_UCHAR(vaddr, static_cast(data), static_cast(size)); - } - - return STATUS_SUCCESS; -} diff --git a/QDMA/windows/sys/libqdma/source/xpcie.hpp b/QDMA/windows/sys/libqdma/source/xpcie.hpp deleted file mode 100644 index 232c331a5..000000000 --- a/QDMA/windows/sys/libqdma/source/xpcie.hpp +++ /dev/null @@ -1,76 +0,0 @@ -/* - * Copyright (C) 2020 Xilinx, Inc - * - * Licensed under the Apache License, Version 2.0 (the "License"). You may - * not use this file except in compliance with the License. You may obtain - * a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - */ - -#pragma once - -#include "qdma_platform_env.h" -#include "qdma_exports.h" -#include -#include - -namespace xlnx { - -struct sbdf { - UINT32 fun_no : 3; - UINT32 dev_no : 5; - UINT32 bus_no : 8; - UINT32 seg_no : 16; -}; - -union pci_sbdf { - struct sbdf sbdf; - UINT32 val; -}; - -class xpcie_device { - struct bar { - /** kernel virtual address of pcie BAR */ - UCHAR *base = nullptr; - /** length of address space in Bytes */ - size_t length = 0; - /** BAR index, not to confuse with BAR number */ - unsigned int index = 0; - - NTSTATUS read(size_t offset, void* data, size_t size) const; - NTSTATUS write(size_t offset, void* data, size_t size) const; - }; - - static constexpr size_t MAX_NUM_BARS = 6; - ULONG msix_vectors = 0; - UINT32 num_bars = 0; - bar bars[MAX_NUM_BARS]; - bar* config_bar = nullptr; - bar* user_bar = nullptr; - bar* bypass_bar = nullptr; - -public: - NTSTATUS map(const WDFCMRESLIST resources); - void unmap(void); - NTSTATUS find_num_msix_vectors(const WDFDEVICE device); - ULONG get_num_msix_vectors(void) const; - NTSTATUS assign_config_bar(const UINT8 bar_idx); - NTSTATUS assign_bar_types(const UINT8 user_bar_idx); - NTSTATUS get_bdf(const WDFDEVICE device, UINT32 &bdf); - - NTSTATUS read_bar(qdma_bar_type bar_type, size_t offset, void* data, size_t size) const; - NTSTATUS write_bar(qdma_bar_type bar_type, size_t offset, void* data, size_t size) const; - ULONG conf_reg_read(size_t offset) const; - void conf_reg_write(size_t offset, ULONG data) const; - NTSTATUS get_bar_info(qdma_bar_type bar_type, PVOID &bar_base, size_t &bar_length) const; -}; -} /* namespace xlnx */ - - diff --git a/README.md b/README.md index 194a65fdf..92fdff4d5 100644 --- a/README.md +++ b/README.md @@ -1,33 +1,4 @@ # Xilinx DMA IP Reference drivers -## Xilinx QDMA - -The Xilinx PCI Express Multi Queue DMA (QDMA) IP provides high-performance direct memory access (DMA) via PCI Express. The PCIe QDMA can be implemented in UltraScale+ devices. - -Both the linux kernel driver and the DPDK driver can be run on a PCI Express root port host PC to interact with the QDMA endpoint IP via PCI Express. - -### Getting Started - -* [QDMA Reference Drivers Comprehensive documentation](https://xilinx.github.io/dma_ip_drivers/) - -## Xilinx-VSEC (XVSEC) - -Xilinx-VSEC (XVSEC) are Xilinx supported VSECs. The XVSEC Driver helps creating and deploying designs that may include the Xilinx VSEC PCIe Features. - -VSEC (Vendor Specific Extended Capability) is a feature of PCIe. - -The VSEC itself is implemented in the PCIe extended capability register in the FPGA hardware (as either soft or hard IP). The drivers and SW are created to interface with and use this hardware implemented feature. - -The XVSEC driver currently include the MCAP VSEC, but will be expanded to include the XVC VSEC and NULL VSEC. - -### Getting Started - -* [XVSEC Linux Kernel Reference Driver Comprehensive documentation](https://xilinx.github.io/dma_ip_drivers/) - -### Support - -Refer to Xilinx PCIe Forum for any queries/issues/support required w.r.t Xilinx's DMA IP Reference Drivers - -Note: Issues are disabled in github for these drivers. All the queries shall be redirected through Xilinx PCIe Forum link given below. - -* [Xilinx PCIe Forum](https://forums.xilinx.com/t5/PCIe-and-CPM/bd-p/PCIe) \ No newline at end of file +These drivers were taken from and +updated for the latest kernel (6.8.7). They work on Arch Linux as of 2024-04-25. diff --git a/XDMA/linux-kernel/RELEASE b/XDMA/linux-kernel/RELEASE index 2f6a92e9c..8637e8f4e 100644 --- a/XDMA/linux-kernel/RELEASE +++ b/XDMA/linux-kernel/RELEASE @@ -1,3 +1,7 @@ +gonsolo +======= +- updated to kernel 6.8.7 and make sure it works. + v2020.2.0 ========= - renamed module parameter "enable_credit_mp" to "enable_st_c2h_credit" to diff --git a/XDMA/linux-kernel/xdma/GONSOLO b/XDMA/linux-kernel/xdma/GONSOLO deleted file mode 100644 index 6be047b6c..000000000 --- a/XDMA/linux-kernel/xdma/GONSOLO +++ /dev/null @@ -1,8 +0,0 @@ -make -j10 DEBUG=1 -sudo make -j10 DEBUG=1 install -Boot with pci=nomsi -sudo insmod /lib/modules/$(uname -r)/xdma/xdma-gonsolo.ko poll_mode=1 interrupt_mode=2 -lsmod|grep xdma_gonsolo -sudo dmesg -sudo rmmod xdma_gonsolo -ls /dev/xdma* diff --git a/docs/source/includeme.rst b/docs/source/includeme.rst deleted file mode 100644 index 38ba8043d..000000000 --- a/docs/source/includeme.rst +++ /dev/null @@ -1 +0,0 @@ -.. include:: ../../README.rst \ No newline at end of file diff --git a/index.html b/index.html deleted file mode 100644 index 02b9c868f..000000000 --- a/index.html +++ /dev/null @@ -1,30 +0,0 @@ - - - - - Xilinx QDMA IP Drivers Documentation - - - - - - \ No newline at end of file From e2a5d5ee99b5f7de226cdfb335326dcef4a88f78 Mon Sep 17 00:00:00 2001 From: Gon Solo Date: Thu, 25 Apr 2024 18:54:54 +0200 Subject: [PATCH 16/22] Merge xvsec branch. These updates were taken from https://github.com/paulmnt/dma_ip_drivers. --- XVSEC/linux-kernel/.gitignore | 1 + XVSEC/linux-kernel/drv/Makefile | 4 +++- XVSEC/linux-kernel/drv/xvsec_drv.c | 14 ++++++++++-- .../drv/xvsec_mcap/us/xvsec_mcap_us.c | 4 ++++ .../drv/xvsec_mcap/versal/xvsec_mcap_versal.c | 8 +++++++ XVSEC/linux-kernel/drv/xvsec_util.c | 22 +++++++++++++++++-- XVSEC/linux-kernel/drv/xvsec_util.h | 4 ++++ 7 files changed, 52 insertions(+), 5 deletions(-) create mode 100644 XVSEC/linux-kernel/.gitignore diff --git a/XVSEC/linux-kernel/.gitignore b/XVSEC/linux-kernel/.gitignore new file mode 100644 index 000000000..567609b12 --- /dev/null +++ b/XVSEC/linux-kernel/.gitignore @@ -0,0 +1 @@ +build/ diff --git a/XVSEC/linux-kernel/drv/Makefile b/XVSEC/linux-kernel/drv/Makefile index 6e1a1b7f8..47571541a 100644 --- a/XVSEC/linux-kernel/drv/Makefile +++ b/XVSEC/linux-kernel/drv/Makefile @@ -29,7 +29,9 @@ all: @mv *.symvers $(module_path)/obj/ @mv *.mod* $(module_path)/obj/ @mv *.order* $(module_path)/obj/ - @mv .tmp* $(module_path)/obj/ + @if test -e .tmp*; then \ + mv .tmp* $(module_path)/obj/; \ + fi; @mv ./xvsec_mcap/*.o $(module_path)/obj/xvsec_mcap/ @mv ./xvsec_mcap/us/*.o $(module_path)/obj/xvsec_mcap/us/ @mv ./xvsec_mcap/versal/*.o $(module_path)/obj/xvsec_mcap/versal/ diff --git a/XVSEC/linux-kernel/drv/xvsec_drv.c b/XVSEC/linux-kernel/drv/xvsec_drv.c index 64d4b84c7..dd5b07345 100644 --- a/XVSEC/linux-kernel/drv/xvsec_drv.c +++ b/XVSEC/linux-kernel/drv/xvsec_drv.c @@ -354,14 +354,18 @@ static long xvsec_gen_ioctl(struct file *filep, uint32_t cmd, unsigned long arg) /** pcie device generic fops structure */ static const struct file_operations xvsec_gen_fops = { +#if LINUX_VERSION_CODE < KERNEL_VERSION(6, 4, 0) .owner = THIS_MODULE, +#endif .open = xvsec_gen_open, .release = xvsec_gen_close, .unlocked_ioctl = xvsec_gen_ioctl, }; -static int xvsec_initialize(struct pci_dev *pdev, struct context *dev_ctx) +int xvsec_initialize(struct pci_dev *pdev, struct context *dev_ctx); + +int xvsec_initialize(struct pci_dev *pdev, struct context *dev_ctx) { int ret = 0; int status; @@ -405,7 +409,9 @@ static int xvsec_initialize(struct pci_dev *pdev, struct context *dev_ctx) } EXPORT_SYMBOL_GPL(xvsec_initialize); -static int xvsec_deinitialize(struct context *dev_ctx) +int xvsec_deinitialize(struct context *dev_ctx); + +int xvsec_deinitialize(struct context *dev_ctx) { int ret = 0; uint16_t index; @@ -456,7 +462,11 @@ static int __init xvsec_drv_init(void) if (dev_count == 0) return 0; +#if LINUX_VERSION_CODE < KERNEL_VERSION(6, 4, 0) g_xvsec_class = class_create(THIS_MODULE, XVSEC_NODE_NAME); +#else + g_xvsec_class = class_create(XVSEC_NODE_NAME); +#endif if (IS_ERR(g_xvsec_class)) { pr_err("failed to create class"); ret = -(PTR_ERR(g_xvsec_class)); diff --git a/XVSEC/linux-kernel/drv/xvsec_mcap/us/xvsec_mcap_us.c b/XVSEC/linux-kernel/drv/xvsec_mcap/us/xvsec_mcap_us.c index 81cb53de3..ff3894d8e 100644 --- a/XVSEC/linux-kernel/drv/xvsec_mcap/us/xvsec_mcap_us.c +++ b/XVSEC/linux-kernel/drv/xvsec_mcap/us/xvsec_mcap_us.c @@ -916,9 +916,13 @@ static int xvsec_mcap_program(struct vsec_context *mcap_ctx, char *fname) pr_info("After fopen\n"); +#if LINUX_VERSION_CODE < KERNEL_VERSION(5,10,0) ret = xvsec_util_get_file_size(fname, &file_size); if (ret < 0) goto CLEANUP; +#else + file_size = xvsec_util_get_file_size(filep); +#endif pr_info("After getsize\n"); diff --git a/XVSEC/linux-kernel/drv/xvsec_mcap/versal/xvsec_mcap_versal.c b/XVSEC/linux-kernel/drv/xvsec_mcap/versal/xvsec_mcap_versal.c index 5827f82b9..6d5fdac37 100644 --- a/XVSEC/linux-kernel/drv/xvsec_mcap/versal/xvsec_mcap_versal.c +++ b/XVSEC/linux-kernel/drv/xvsec_mcap/versal/xvsec_mcap_versal.c @@ -390,9 +390,13 @@ int xvsec_mcapv2_file_download( if (filep == NULL) return -(ENOENT); +#if LINUX_VERSION_CODE < KERNEL_VERSION(5,10,0) ret = xvsec_util_get_file_size(fname, &file_size); if (ret < 0) goto CLEANUP_EXIT; +#else + file_size = xvsec_util_get_file_size(filep); +#endif if (file_size <= 0) { file_info->v2.op_status = FILE_OP_ZERO_FSIZE; @@ -739,9 +743,13 @@ int xvsec_mcapv2_file_upload( xvsec_util_fsync(filep); /** Compare the requested size with file size */ +#if LINUX_VERSION_CODE < KERNEL_VERSION(5,10,0) ret = xvsec_util_get_file_size(fname, &file_size); if (ret < 0) goto CLEANUP; +#else + file_size = xvsec_util_get_file_size(filep); +#endif if (file_size != file_info->v2.length) { pr_err("%s: Could not read complete requested length\n", diff --git a/XVSEC/linux-kernel/drv/xvsec_util.c b/XVSEC/linux-kernel/drv/xvsec_util.c index ff16de807..4ca312503 100644 --- a/XVSEC/linux-kernel/drv/xvsec_util.c +++ b/XVSEC/linux-kernel/drv/xvsec_util.c @@ -63,13 +63,17 @@ int xvsec_util_find_file_type(char *fname, const char *suffix) struct file *xvsec_util_fopen(const char *path, int flags, int rights) { struct file *filep; - mm_segment_t oldfs; int err = 0; +#if LINUX_VERSION_CODE < KERNEL_VERSION(5,10,0) + mm_segment_t oldfs; oldfs = get_fs(); set_fs(KERNEL_DS); +#endif filep = filp_open(path, (flags | O_LARGEFILE), rights); +#if LINUX_VERSION_CODE < KERNEL_VERSION(5,10,0) set_fs(oldfs); +#endif if (IS_ERR(filep) != 0) { err = PTR_ERR(filep); pr_err("%s : filp_open failed, err : 0x%X\n", __func__, err); @@ -87,17 +91,21 @@ int xvsec_util_fread(struct file *filep, uint64_t offset, uint8_t *data, uint32_t size) { int ret = 0; +#if LINUX_VERSION_CODE < KERNEL_VERSION(5,10,0) mm_segment_t oldfs; oldfs = get_fs(); set_fs(KERNEL_DS); +#endif #if KERNEL_VERSION(4, 14, 0) > LINUX_VERSION_CODE ret = vfs_read(filep, (char __user *)data, size, (loff_t *)&offset); #else ret = kernel_read(filep, (void *)data, size, (loff_t *)&offset); #endif filep->f_pos = offset; +#if LINUX_VERSION_CODE < KERNEL_VERSION(5,10,0) set_fs(oldfs); +#endif if (ret < 0) { #if KERNEL_VERSION(4, 14, 0) > LINUX_VERSION_CODE @@ -117,10 +125,12 @@ int xvsec_util_fwrite(struct file *filep, uint64_t offset, uint8_t *data, uint32_t size) { int ret = 0; +#if LINUX_VERSION_CODE < KERNEL_VERSION(5,10,0) mm_segment_t oldfs; oldfs = get_fs(); set_fs(KERNEL_DS); +#endif #if KERNEL_VERSION(4, 14, 0) > LINUX_VERSION_CODE ret = vfs_write(filep, (char __user *)data, size, (loff_t *)&offset); #else @@ -128,7 +138,9 @@ int xvsec_util_fwrite(struct file *filep, uint64_t offset, (loff_t *)&offset); #endif filep->f_pos = offset; +#if LINUX_VERSION_CODE < KERNEL_VERSION(5,10,0) set_fs(oldfs); +#endif if (ret < 0) { #if KERNEL_VERSION(4, 14, 0) > LINUX_VERSION_CODE @@ -148,6 +160,7 @@ int xvsec_util_fsync(struct file *filep) return 0; } +#if LINUX_VERSION_CODE < KERNEL_VERSION(5,10,0) int xvsec_util_get_file_size(const char *fname, loff_t *size) { int ret = 0; @@ -169,4 +182,9 @@ int xvsec_util_get_file_size(const char *fname, loff_t *size) return ret; } - +#else +loff_t xvsec_util_get_file_size(struct file *filep) +{ + return i_size_read(file_inode(filep)); +} +#endif diff --git a/XVSEC/linux-kernel/drv/xvsec_util.h b/XVSEC/linux-kernel/drv/xvsec_util.h index 2126ac9b2..daae94e32 100644 --- a/XVSEC/linux-kernel/drv/xvsec_util.h +++ b/XVSEC/linux-kernel/drv/xvsec_util.h @@ -40,6 +40,10 @@ int xvsec_util_fread(struct file *filep, uint64_t offset, int xvsec_util_fwrite(struct file *filep, uint64_t offset, uint8_t *data, uint32_t size); int xvsec_util_fsync(struct file *filep); +#if LINUX_VERSION_CODE < KERNEL_VERSION(5,10,0) int xvsec_util_get_file_size(const char *fname, loff_t *size); +#else +loff_t xvsec_util_get_file_size(struct file *filep); +#endif #endif /* __XVSEC_UTIL_H__ */ From d68fe679fe055d0a582f1073fdf4fb302ae13fe2 Mon Sep 17 00:00:00 2001 From: Gon Solo Date: Thu, 25 Apr 2024 19:10:21 +0200 Subject: [PATCH 17/22] Fix parallel build and ignore built files. --- XVSEC/linux-kernel/.gitignore | 1 + XVSEC/linux-kernel/Makefile | 3 +-- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/XVSEC/linux-kernel/.gitignore b/XVSEC/linux-kernel/.gitignore index 567609b12..3375df4f8 100644 --- a/XVSEC/linux-kernel/.gitignore +++ b/XVSEC/linux-kernel/.gitignore @@ -1 +1,2 @@ build/ +*.cmd diff --git a/XVSEC/linux-kernel/Makefile b/XVSEC/linux-kernel/Makefile index 0b574bfc7..7a98486e7 100644 --- a/XVSEC/linux-kernel/Makefile +++ b/XVSEC/linux-kernel/Makefile @@ -33,8 +33,7 @@ libxvsec : cd libxvsec && $(MAKE) .PHONY : tools -tools : libxvsec app -app : +tools : libxvsec @echo "#######################"; @echo "#### tools ####"; @echo "#######################"; From 0039503b12498911be41912976bff03b43cda900 Mon Sep 17 00:00:00 2001 From: Gon Solo Date: Thu, 25 Apr 2024 19:12:22 +0200 Subject: [PATCH 18/22] Clean up xvsec. --- XVSEC/linux-kernel/.gitignore | 2 -- {XVSEC/linux-kernel => xvsec}/COPYING | 0 {XVSEC/linux-kernel => xvsec}/LICENSE | 0 {XVSEC/linux-kernel => xvsec}/Makefile | 0 {XVSEC/linux-kernel => xvsec}/README | 0 {XVSEC/linux-kernel => xvsec}/RELEASE | 0 {XVSEC/linux-kernel => xvsec}/docs/README | 0 {XVSEC/linux-kernel => xvsec}/drv/Makefile | 0 {XVSEC/linux-kernel => xvsec}/drv/version.h | 0 {XVSEC/linux-kernel => xvsec}/drv/xvsec_cdev.c | 0 {XVSEC/linux-kernel => xvsec}/drv/xvsec_cdev.h | 0 {XVSEC/linux-kernel => xvsec}/drv/xvsec_drv.c | 0 {XVSEC/linux-kernel => xvsec}/drv/xvsec_drv.h | 0 {XVSEC/linux-kernel => xvsec}/drv/xvsec_drv_int.h | 0 {XVSEC/linux-kernel => xvsec}/drv/xvsec_mcap/us/xvsec_mcap_us.c | 0 {XVSEC/linux-kernel => xvsec}/drv/xvsec_mcap/us/xvsec_mcap_us.h | 0 .../drv/xvsec_mcap/versal/xvsec_mcap_versal.c | 0 .../drv/xvsec_mcap/versal/xvsec_mcap_versal.h | 0 {XVSEC/linux-kernel => xvsec}/drv/xvsec_mcap/xvsec_mcap.c | 0 {XVSEC/linux-kernel => xvsec}/drv/xvsec_mcap/xvsec_mcap.h | 0 {XVSEC/linux-kernel => xvsec}/drv/xvsec_util.c | 0 {XVSEC/linux-kernel => xvsec}/drv/xvsec_util.h | 0 {XVSEC/linux-kernel => xvsec}/libxvsec/Makefile | 0 {XVSEC/linux-kernel => xvsec}/libxvsec/version.h | 0 {XVSEC/linux-kernel => xvsec}/libxvsec/xvsec.c | 0 {XVSEC/linux-kernel => xvsec}/libxvsec/xvsec.h | 0 {XVSEC/linux-kernel => xvsec}/libxvsec/xvsec_int.h | 0 {XVSEC/linux-kernel => xvsec}/libxvsec/xvsec_mcap.c | 0 {XVSEC/linux-kernel => xvsec}/tools/Makefile | 0 {XVSEC/linux-kernel => xvsec}/tools/main.c | 0 {XVSEC/linux-kernel => xvsec}/tools/main.h | 0 {XVSEC/linux-kernel => xvsec}/tools/mcap_ops.c | 0 {XVSEC/linux-kernel => xvsec}/tools/mcap_ops.h | 0 {XVSEC/linux-kernel => xvsec}/tools/version.h | 0 {XVSEC/linux-kernel => xvsec}/tools/xvsec_parser.c | 0 {XVSEC/linux-kernel => xvsec}/tools/xvsec_parser.h | 0 36 files changed, 2 deletions(-) delete mode 100644 XVSEC/linux-kernel/.gitignore rename {XVSEC/linux-kernel => xvsec}/COPYING (100%) rename {XVSEC/linux-kernel => xvsec}/LICENSE (100%) rename {XVSEC/linux-kernel => xvsec}/Makefile (100%) rename {XVSEC/linux-kernel => xvsec}/README (100%) rename {XVSEC/linux-kernel => xvsec}/RELEASE (100%) rename {XVSEC/linux-kernel => xvsec}/docs/README (100%) rename {XVSEC/linux-kernel => xvsec}/drv/Makefile (100%) rename {XVSEC/linux-kernel => xvsec}/drv/version.h (100%) rename {XVSEC/linux-kernel => xvsec}/drv/xvsec_cdev.c (100%) rename {XVSEC/linux-kernel => xvsec}/drv/xvsec_cdev.h (100%) rename {XVSEC/linux-kernel => xvsec}/drv/xvsec_drv.c (100%) rename {XVSEC/linux-kernel => xvsec}/drv/xvsec_drv.h (100%) rename {XVSEC/linux-kernel => xvsec}/drv/xvsec_drv_int.h (100%) rename {XVSEC/linux-kernel => xvsec}/drv/xvsec_mcap/us/xvsec_mcap_us.c (100%) rename {XVSEC/linux-kernel => xvsec}/drv/xvsec_mcap/us/xvsec_mcap_us.h (100%) rename {XVSEC/linux-kernel => xvsec}/drv/xvsec_mcap/versal/xvsec_mcap_versal.c (100%) rename {XVSEC/linux-kernel => xvsec}/drv/xvsec_mcap/versal/xvsec_mcap_versal.h (100%) rename {XVSEC/linux-kernel => xvsec}/drv/xvsec_mcap/xvsec_mcap.c (100%) rename {XVSEC/linux-kernel => xvsec}/drv/xvsec_mcap/xvsec_mcap.h (100%) rename {XVSEC/linux-kernel => xvsec}/drv/xvsec_util.c (100%) rename {XVSEC/linux-kernel => xvsec}/drv/xvsec_util.h (100%) rename {XVSEC/linux-kernel => xvsec}/libxvsec/Makefile (100%) rename {XVSEC/linux-kernel => xvsec}/libxvsec/version.h (100%) rename {XVSEC/linux-kernel => xvsec}/libxvsec/xvsec.c (100%) rename {XVSEC/linux-kernel => xvsec}/libxvsec/xvsec.h (100%) rename {XVSEC/linux-kernel => xvsec}/libxvsec/xvsec_int.h (100%) rename {XVSEC/linux-kernel => xvsec}/libxvsec/xvsec_mcap.c (100%) rename {XVSEC/linux-kernel => xvsec}/tools/Makefile (100%) rename {XVSEC/linux-kernel => xvsec}/tools/main.c (100%) rename {XVSEC/linux-kernel => xvsec}/tools/main.h (100%) rename {XVSEC/linux-kernel => xvsec}/tools/mcap_ops.c (100%) rename {XVSEC/linux-kernel => xvsec}/tools/mcap_ops.h (100%) rename {XVSEC/linux-kernel => xvsec}/tools/version.h (100%) rename {XVSEC/linux-kernel => xvsec}/tools/xvsec_parser.c (100%) rename {XVSEC/linux-kernel => xvsec}/tools/xvsec_parser.h (100%) diff --git a/XVSEC/linux-kernel/.gitignore b/XVSEC/linux-kernel/.gitignore deleted file mode 100644 index 3375df4f8..000000000 --- a/XVSEC/linux-kernel/.gitignore +++ /dev/null @@ -1,2 +0,0 @@ -build/ -*.cmd diff --git a/XVSEC/linux-kernel/COPYING b/xvsec/COPYING similarity index 100% rename from XVSEC/linux-kernel/COPYING rename to xvsec/COPYING diff --git a/XVSEC/linux-kernel/LICENSE b/xvsec/LICENSE similarity index 100% rename from XVSEC/linux-kernel/LICENSE rename to xvsec/LICENSE diff --git a/XVSEC/linux-kernel/Makefile b/xvsec/Makefile similarity index 100% rename from XVSEC/linux-kernel/Makefile rename to xvsec/Makefile diff --git a/XVSEC/linux-kernel/README b/xvsec/README similarity index 100% rename from XVSEC/linux-kernel/README rename to xvsec/README diff --git a/XVSEC/linux-kernel/RELEASE b/xvsec/RELEASE similarity index 100% rename from XVSEC/linux-kernel/RELEASE rename to xvsec/RELEASE diff --git a/XVSEC/linux-kernel/docs/README b/xvsec/docs/README similarity index 100% rename from XVSEC/linux-kernel/docs/README rename to xvsec/docs/README diff --git a/XVSEC/linux-kernel/drv/Makefile b/xvsec/drv/Makefile similarity index 100% rename from XVSEC/linux-kernel/drv/Makefile rename to xvsec/drv/Makefile diff --git a/XVSEC/linux-kernel/drv/version.h b/xvsec/drv/version.h similarity index 100% rename from XVSEC/linux-kernel/drv/version.h rename to xvsec/drv/version.h diff --git a/XVSEC/linux-kernel/drv/xvsec_cdev.c b/xvsec/drv/xvsec_cdev.c similarity index 100% rename from XVSEC/linux-kernel/drv/xvsec_cdev.c rename to xvsec/drv/xvsec_cdev.c diff --git a/XVSEC/linux-kernel/drv/xvsec_cdev.h b/xvsec/drv/xvsec_cdev.h similarity index 100% rename from XVSEC/linux-kernel/drv/xvsec_cdev.h rename to xvsec/drv/xvsec_cdev.h diff --git a/XVSEC/linux-kernel/drv/xvsec_drv.c b/xvsec/drv/xvsec_drv.c similarity index 100% rename from XVSEC/linux-kernel/drv/xvsec_drv.c rename to xvsec/drv/xvsec_drv.c diff --git a/XVSEC/linux-kernel/drv/xvsec_drv.h b/xvsec/drv/xvsec_drv.h similarity index 100% rename from XVSEC/linux-kernel/drv/xvsec_drv.h rename to xvsec/drv/xvsec_drv.h diff --git a/XVSEC/linux-kernel/drv/xvsec_drv_int.h b/xvsec/drv/xvsec_drv_int.h similarity index 100% rename from XVSEC/linux-kernel/drv/xvsec_drv_int.h rename to xvsec/drv/xvsec_drv_int.h diff --git a/XVSEC/linux-kernel/drv/xvsec_mcap/us/xvsec_mcap_us.c b/xvsec/drv/xvsec_mcap/us/xvsec_mcap_us.c similarity index 100% rename from XVSEC/linux-kernel/drv/xvsec_mcap/us/xvsec_mcap_us.c rename to xvsec/drv/xvsec_mcap/us/xvsec_mcap_us.c diff --git a/XVSEC/linux-kernel/drv/xvsec_mcap/us/xvsec_mcap_us.h b/xvsec/drv/xvsec_mcap/us/xvsec_mcap_us.h similarity index 100% rename from XVSEC/linux-kernel/drv/xvsec_mcap/us/xvsec_mcap_us.h rename to xvsec/drv/xvsec_mcap/us/xvsec_mcap_us.h diff --git a/XVSEC/linux-kernel/drv/xvsec_mcap/versal/xvsec_mcap_versal.c b/xvsec/drv/xvsec_mcap/versal/xvsec_mcap_versal.c similarity index 100% rename from XVSEC/linux-kernel/drv/xvsec_mcap/versal/xvsec_mcap_versal.c rename to xvsec/drv/xvsec_mcap/versal/xvsec_mcap_versal.c diff --git a/XVSEC/linux-kernel/drv/xvsec_mcap/versal/xvsec_mcap_versal.h b/xvsec/drv/xvsec_mcap/versal/xvsec_mcap_versal.h similarity index 100% rename from XVSEC/linux-kernel/drv/xvsec_mcap/versal/xvsec_mcap_versal.h rename to xvsec/drv/xvsec_mcap/versal/xvsec_mcap_versal.h diff --git a/XVSEC/linux-kernel/drv/xvsec_mcap/xvsec_mcap.c b/xvsec/drv/xvsec_mcap/xvsec_mcap.c similarity index 100% rename from XVSEC/linux-kernel/drv/xvsec_mcap/xvsec_mcap.c rename to xvsec/drv/xvsec_mcap/xvsec_mcap.c diff --git a/XVSEC/linux-kernel/drv/xvsec_mcap/xvsec_mcap.h b/xvsec/drv/xvsec_mcap/xvsec_mcap.h similarity index 100% rename from XVSEC/linux-kernel/drv/xvsec_mcap/xvsec_mcap.h rename to xvsec/drv/xvsec_mcap/xvsec_mcap.h diff --git a/XVSEC/linux-kernel/drv/xvsec_util.c b/xvsec/drv/xvsec_util.c similarity index 100% rename from XVSEC/linux-kernel/drv/xvsec_util.c rename to xvsec/drv/xvsec_util.c diff --git a/XVSEC/linux-kernel/drv/xvsec_util.h b/xvsec/drv/xvsec_util.h similarity index 100% rename from XVSEC/linux-kernel/drv/xvsec_util.h rename to xvsec/drv/xvsec_util.h diff --git a/XVSEC/linux-kernel/libxvsec/Makefile b/xvsec/libxvsec/Makefile similarity index 100% rename from XVSEC/linux-kernel/libxvsec/Makefile rename to xvsec/libxvsec/Makefile diff --git a/XVSEC/linux-kernel/libxvsec/version.h b/xvsec/libxvsec/version.h similarity index 100% rename from XVSEC/linux-kernel/libxvsec/version.h rename to xvsec/libxvsec/version.h diff --git a/XVSEC/linux-kernel/libxvsec/xvsec.c b/xvsec/libxvsec/xvsec.c similarity index 100% rename from XVSEC/linux-kernel/libxvsec/xvsec.c rename to xvsec/libxvsec/xvsec.c diff --git a/XVSEC/linux-kernel/libxvsec/xvsec.h b/xvsec/libxvsec/xvsec.h similarity index 100% rename from XVSEC/linux-kernel/libxvsec/xvsec.h rename to xvsec/libxvsec/xvsec.h diff --git a/XVSEC/linux-kernel/libxvsec/xvsec_int.h b/xvsec/libxvsec/xvsec_int.h similarity index 100% rename from XVSEC/linux-kernel/libxvsec/xvsec_int.h rename to xvsec/libxvsec/xvsec_int.h diff --git a/XVSEC/linux-kernel/libxvsec/xvsec_mcap.c b/xvsec/libxvsec/xvsec_mcap.c similarity index 100% rename from XVSEC/linux-kernel/libxvsec/xvsec_mcap.c rename to xvsec/libxvsec/xvsec_mcap.c diff --git a/XVSEC/linux-kernel/tools/Makefile b/xvsec/tools/Makefile similarity index 100% rename from XVSEC/linux-kernel/tools/Makefile rename to xvsec/tools/Makefile diff --git a/XVSEC/linux-kernel/tools/main.c b/xvsec/tools/main.c similarity index 100% rename from XVSEC/linux-kernel/tools/main.c rename to xvsec/tools/main.c diff --git a/XVSEC/linux-kernel/tools/main.h b/xvsec/tools/main.h similarity index 100% rename from XVSEC/linux-kernel/tools/main.h rename to xvsec/tools/main.h diff --git a/XVSEC/linux-kernel/tools/mcap_ops.c b/xvsec/tools/mcap_ops.c similarity index 100% rename from XVSEC/linux-kernel/tools/mcap_ops.c rename to xvsec/tools/mcap_ops.c diff --git a/XVSEC/linux-kernel/tools/mcap_ops.h b/xvsec/tools/mcap_ops.h similarity index 100% rename from XVSEC/linux-kernel/tools/mcap_ops.h rename to xvsec/tools/mcap_ops.h diff --git a/XVSEC/linux-kernel/tools/version.h b/xvsec/tools/version.h similarity index 100% rename from XVSEC/linux-kernel/tools/version.h rename to xvsec/tools/version.h diff --git a/XVSEC/linux-kernel/tools/xvsec_parser.c b/xvsec/tools/xvsec_parser.c similarity index 100% rename from XVSEC/linux-kernel/tools/xvsec_parser.c rename to xvsec/tools/xvsec_parser.c diff --git a/XVSEC/linux-kernel/tools/xvsec_parser.h b/xvsec/tools/xvsec_parser.h similarity index 100% rename from XVSEC/linux-kernel/tools/xvsec_parser.h rename to xvsec/tools/xvsec_parser.h From 22e4fd42e9878c95d702610888ff3c0f930b6288 Mon Sep 17 00:00:00 2001 From: Gon Solo Date: Thu, 25 Apr 2024 19:14:11 +0200 Subject: [PATCH 19/22] Clean up xdma. --- {XDMA/linux-kernel => xdma}/COPYING | 0 {XDMA/linux-kernel => xdma}/LICENSE | 0 {XDMA/linux-kernel => xdma}/RELEASE | 0 {XDMA/linux-kernel => xdma}/include/libxdma_api.h | 0 {XDMA/linux-kernel => xdma}/readme.txt | 0 .../tests/data/datafile0_4K.bin | Bin .../tests/data/datafile1_4K.bin | Bin .../tests/data/datafile2_4K.bin | Bin .../tests/data/datafile3_4K.bin | Bin .../tests/data/datafile_256K.bin | Bin .../tests/data/datafile_32M.bin | Bin .../tests/data/datafile_8K.bin | Bin .../tests/dma_memory_mapped_test.sh | 0 .../tests/dma_streaming_test.sh | 0 {XDMA/linux-kernel => xdma}/tests/load_driver.sh | 0 .../linux-kernel => xdma}/tests/perform_hwcount.sh | 0 {XDMA/linux-kernel => xdma}/tests/run_test.sh | 0 .../tests/scripts_mm/fio_parse_result.sh | 0 .../tests/scripts_mm/fio_test.sh | 0 {XDMA/linux-kernel => xdma}/tests/scripts_mm/io.sh | 0 .../tests/scripts_mm/io_sweep.sh | 0 .../tests/scripts_mm/libtest.sh | 0 .../tests/scripts_mm/unaligned.sh | 0 .../tests/scripts_mm/xdma_mm.sh | 0 {XDMA/linux-kernel => xdma}/tools/.gitignore | 0 {XDMA/linux-kernel => xdma}/tools/Makefile | 0 {XDMA/linux-kernel => xdma}/tools/dma_from_device.c | 0 {XDMA/linux-kernel => xdma}/tools/dma_to_device.c | 0 {XDMA/linux-kernel => xdma}/tools/dma_utils.c | 0 {XDMA/linux-kernel => xdma}/tools/performance.c | 0 {XDMA/linux-kernel => xdma}/tools/reg_rw.c | 0 {XDMA/linux-kernel => xdma}/tools/test_chrdev.c | 0 {XDMA/linux-kernel => xdma}/xdma/.gitignore | 0 {XDMA/linux-kernel => xdma}/xdma/Makefile | 0 {XDMA/linux-kernel => xdma}/xdma/cdev_bypass.c | 0 {XDMA/linux-kernel => xdma}/xdma/cdev_ctrl.c | 0 {XDMA/linux-kernel => xdma}/xdma/cdev_ctrl.h | 0 {XDMA/linux-kernel => xdma}/xdma/cdev_events.c | 0 {XDMA/linux-kernel => xdma}/xdma/cdev_sgdma.c | 0 {XDMA/linux-kernel => xdma}/xdma/cdev_sgdma.h | 0 {XDMA/linux-kernel => xdma}/xdma/cdev_xvc.c | 0 {XDMA/linux-kernel => xdma}/xdma/cdev_xvc.h | 0 {XDMA/linux-kernel => xdma}/xdma/libxdma.c | 0 {XDMA/linux-kernel => xdma}/xdma/libxdma.h | 0 {XDMA/linux-kernel => xdma}/xdma/version.h | 0 {XDMA/linux-kernel => xdma}/xdma/xdma_cdev.c | 0 {XDMA/linux-kernel => xdma}/xdma/xdma_cdev.h | 0 {XDMA/linux-kernel => xdma}/xdma/xdma_mod.c | 0 {XDMA/linux-kernel => xdma}/xdma/xdma_mod.h | 0 {XDMA/linux-kernel => xdma}/xdma/xdma_thread.c | 0 {XDMA/linux-kernel => xdma}/xdma/xdma_thread.h | 0 51 files changed, 0 insertions(+), 0 deletions(-) rename {XDMA/linux-kernel => xdma}/COPYING (100%) rename {XDMA/linux-kernel => xdma}/LICENSE (100%) rename {XDMA/linux-kernel => xdma}/RELEASE (100%) rename {XDMA/linux-kernel => xdma}/include/libxdma_api.h (100%) rename {XDMA/linux-kernel => xdma}/readme.txt (100%) rename {XDMA/linux-kernel => xdma}/tests/data/datafile0_4K.bin (100%) rename {XDMA/linux-kernel => xdma}/tests/data/datafile1_4K.bin (100%) rename {XDMA/linux-kernel => xdma}/tests/data/datafile2_4K.bin (100%) rename {XDMA/linux-kernel => xdma}/tests/data/datafile3_4K.bin (100%) rename {XDMA/linux-kernel => xdma}/tests/data/datafile_256K.bin (100%) rename {XDMA/linux-kernel => xdma}/tests/data/datafile_32M.bin (100%) rename {XDMA/linux-kernel => xdma}/tests/data/datafile_8K.bin (100%) rename {XDMA/linux-kernel => xdma}/tests/dma_memory_mapped_test.sh (100%) rename {XDMA/linux-kernel => xdma}/tests/dma_streaming_test.sh (100%) rename {XDMA/linux-kernel => xdma}/tests/load_driver.sh (100%) rename {XDMA/linux-kernel => xdma}/tests/perform_hwcount.sh (100%) rename {XDMA/linux-kernel => xdma}/tests/run_test.sh (100%) rename {XDMA/linux-kernel => xdma}/tests/scripts_mm/fio_parse_result.sh (100%) rename {XDMA/linux-kernel => xdma}/tests/scripts_mm/fio_test.sh (100%) rename {XDMA/linux-kernel => xdma}/tests/scripts_mm/io.sh (100%) rename {XDMA/linux-kernel => xdma}/tests/scripts_mm/io_sweep.sh (100%) rename {XDMA/linux-kernel => xdma}/tests/scripts_mm/libtest.sh (100%) rename {XDMA/linux-kernel => xdma}/tests/scripts_mm/unaligned.sh (100%) rename {XDMA/linux-kernel => xdma}/tests/scripts_mm/xdma_mm.sh (100%) rename {XDMA/linux-kernel => xdma}/tools/.gitignore (100%) rename {XDMA/linux-kernel => xdma}/tools/Makefile (100%) rename {XDMA/linux-kernel => xdma}/tools/dma_from_device.c (100%) rename {XDMA/linux-kernel => xdma}/tools/dma_to_device.c (100%) rename {XDMA/linux-kernel => xdma}/tools/dma_utils.c (100%) rename {XDMA/linux-kernel => xdma}/tools/performance.c (100%) rename {XDMA/linux-kernel => xdma}/tools/reg_rw.c (100%) rename {XDMA/linux-kernel => xdma}/tools/test_chrdev.c (100%) rename {XDMA/linux-kernel => xdma}/xdma/.gitignore (100%) rename {XDMA/linux-kernel => xdma}/xdma/Makefile (100%) rename {XDMA/linux-kernel => xdma}/xdma/cdev_bypass.c (100%) rename {XDMA/linux-kernel => xdma}/xdma/cdev_ctrl.c (100%) rename {XDMA/linux-kernel => xdma}/xdma/cdev_ctrl.h (100%) rename {XDMA/linux-kernel => xdma}/xdma/cdev_events.c (100%) rename {XDMA/linux-kernel => xdma}/xdma/cdev_sgdma.c (100%) rename {XDMA/linux-kernel => xdma}/xdma/cdev_sgdma.h (100%) rename {XDMA/linux-kernel => xdma}/xdma/cdev_xvc.c (100%) rename {XDMA/linux-kernel => xdma}/xdma/cdev_xvc.h (100%) rename {XDMA/linux-kernel => xdma}/xdma/libxdma.c (100%) rename {XDMA/linux-kernel => xdma}/xdma/libxdma.h (100%) rename {XDMA/linux-kernel => xdma}/xdma/version.h (100%) rename {XDMA/linux-kernel => xdma}/xdma/xdma_cdev.c (100%) rename {XDMA/linux-kernel => xdma}/xdma/xdma_cdev.h (100%) rename {XDMA/linux-kernel => xdma}/xdma/xdma_mod.c (100%) rename {XDMA/linux-kernel => xdma}/xdma/xdma_mod.h (100%) rename {XDMA/linux-kernel => xdma}/xdma/xdma_thread.c (100%) rename {XDMA/linux-kernel => xdma}/xdma/xdma_thread.h (100%) diff --git a/XDMA/linux-kernel/COPYING b/xdma/COPYING similarity index 100% rename from XDMA/linux-kernel/COPYING rename to xdma/COPYING diff --git a/XDMA/linux-kernel/LICENSE b/xdma/LICENSE similarity index 100% rename from XDMA/linux-kernel/LICENSE rename to xdma/LICENSE diff --git a/XDMA/linux-kernel/RELEASE b/xdma/RELEASE similarity index 100% rename from XDMA/linux-kernel/RELEASE rename to xdma/RELEASE diff --git a/XDMA/linux-kernel/include/libxdma_api.h b/xdma/include/libxdma_api.h similarity index 100% rename from XDMA/linux-kernel/include/libxdma_api.h rename to xdma/include/libxdma_api.h diff --git a/XDMA/linux-kernel/readme.txt b/xdma/readme.txt similarity index 100% rename from XDMA/linux-kernel/readme.txt rename to xdma/readme.txt diff --git a/XDMA/linux-kernel/tests/data/datafile0_4K.bin b/xdma/tests/data/datafile0_4K.bin similarity index 100% rename from XDMA/linux-kernel/tests/data/datafile0_4K.bin rename to xdma/tests/data/datafile0_4K.bin diff --git a/XDMA/linux-kernel/tests/data/datafile1_4K.bin b/xdma/tests/data/datafile1_4K.bin similarity index 100% rename from XDMA/linux-kernel/tests/data/datafile1_4K.bin rename to xdma/tests/data/datafile1_4K.bin diff --git a/XDMA/linux-kernel/tests/data/datafile2_4K.bin b/xdma/tests/data/datafile2_4K.bin similarity index 100% rename from XDMA/linux-kernel/tests/data/datafile2_4K.bin rename to xdma/tests/data/datafile2_4K.bin diff --git a/XDMA/linux-kernel/tests/data/datafile3_4K.bin b/xdma/tests/data/datafile3_4K.bin similarity index 100% rename from XDMA/linux-kernel/tests/data/datafile3_4K.bin rename to xdma/tests/data/datafile3_4K.bin diff --git a/XDMA/linux-kernel/tests/data/datafile_256K.bin b/xdma/tests/data/datafile_256K.bin similarity index 100% rename from XDMA/linux-kernel/tests/data/datafile_256K.bin rename to xdma/tests/data/datafile_256K.bin diff --git a/XDMA/linux-kernel/tests/data/datafile_32M.bin b/xdma/tests/data/datafile_32M.bin similarity index 100% rename from XDMA/linux-kernel/tests/data/datafile_32M.bin rename to xdma/tests/data/datafile_32M.bin diff --git a/XDMA/linux-kernel/tests/data/datafile_8K.bin b/xdma/tests/data/datafile_8K.bin similarity index 100% rename from XDMA/linux-kernel/tests/data/datafile_8K.bin rename to xdma/tests/data/datafile_8K.bin diff --git a/XDMA/linux-kernel/tests/dma_memory_mapped_test.sh b/xdma/tests/dma_memory_mapped_test.sh similarity index 100% rename from XDMA/linux-kernel/tests/dma_memory_mapped_test.sh rename to xdma/tests/dma_memory_mapped_test.sh diff --git a/XDMA/linux-kernel/tests/dma_streaming_test.sh b/xdma/tests/dma_streaming_test.sh similarity index 100% rename from XDMA/linux-kernel/tests/dma_streaming_test.sh rename to xdma/tests/dma_streaming_test.sh diff --git a/XDMA/linux-kernel/tests/load_driver.sh b/xdma/tests/load_driver.sh similarity index 100% rename from XDMA/linux-kernel/tests/load_driver.sh rename to xdma/tests/load_driver.sh diff --git a/XDMA/linux-kernel/tests/perform_hwcount.sh b/xdma/tests/perform_hwcount.sh similarity index 100% rename from XDMA/linux-kernel/tests/perform_hwcount.sh rename to xdma/tests/perform_hwcount.sh diff --git a/XDMA/linux-kernel/tests/run_test.sh b/xdma/tests/run_test.sh similarity index 100% rename from XDMA/linux-kernel/tests/run_test.sh rename to xdma/tests/run_test.sh diff --git a/XDMA/linux-kernel/tests/scripts_mm/fio_parse_result.sh b/xdma/tests/scripts_mm/fio_parse_result.sh similarity index 100% rename from XDMA/linux-kernel/tests/scripts_mm/fio_parse_result.sh rename to xdma/tests/scripts_mm/fio_parse_result.sh diff --git a/XDMA/linux-kernel/tests/scripts_mm/fio_test.sh b/xdma/tests/scripts_mm/fio_test.sh similarity index 100% rename from XDMA/linux-kernel/tests/scripts_mm/fio_test.sh rename to xdma/tests/scripts_mm/fio_test.sh diff --git a/XDMA/linux-kernel/tests/scripts_mm/io.sh b/xdma/tests/scripts_mm/io.sh similarity index 100% rename from XDMA/linux-kernel/tests/scripts_mm/io.sh rename to xdma/tests/scripts_mm/io.sh diff --git a/XDMA/linux-kernel/tests/scripts_mm/io_sweep.sh b/xdma/tests/scripts_mm/io_sweep.sh similarity index 100% rename from XDMA/linux-kernel/tests/scripts_mm/io_sweep.sh rename to xdma/tests/scripts_mm/io_sweep.sh diff --git a/XDMA/linux-kernel/tests/scripts_mm/libtest.sh b/xdma/tests/scripts_mm/libtest.sh similarity index 100% rename from XDMA/linux-kernel/tests/scripts_mm/libtest.sh rename to xdma/tests/scripts_mm/libtest.sh diff --git a/XDMA/linux-kernel/tests/scripts_mm/unaligned.sh b/xdma/tests/scripts_mm/unaligned.sh similarity index 100% rename from XDMA/linux-kernel/tests/scripts_mm/unaligned.sh rename to xdma/tests/scripts_mm/unaligned.sh diff --git a/XDMA/linux-kernel/tests/scripts_mm/xdma_mm.sh b/xdma/tests/scripts_mm/xdma_mm.sh similarity index 100% rename from XDMA/linux-kernel/tests/scripts_mm/xdma_mm.sh rename to xdma/tests/scripts_mm/xdma_mm.sh diff --git a/XDMA/linux-kernel/tools/.gitignore b/xdma/tools/.gitignore similarity index 100% rename from XDMA/linux-kernel/tools/.gitignore rename to xdma/tools/.gitignore diff --git a/XDMA/linux-kernel/tools/Makefile b/xdma/tools/Makefile similarity index 100% rename from XDMA/linux-kernel/tools/Makefile rename to xdma/tools/Makefile diff --git a/XDMA/linux-kernel/tools/dma_from_device.c b/xdma/tools/dma_from_device.c similarity index 100% rename from XDMA/linux-kernel/tools/dma_from_device.c rename to xdma/tools/dma_from_device.c diff --git a/XDMA/linux-kernel/tools/dma_to_device.c b/xdma/tools/dma_to_device.c similarity index 100% rename from XDMA/linux-kernel/tools/dma_to_device.c rename to xdma/tools/dma_to_device.c diff --git a/XDMA/linux-kernel/tools/dma_utils.c b/xdma/tools/dma_utils.c similarity index 100% rename from XDMA/linux-kernel/tools/dma_utils.c rename to xdma/tools/dma_utils.c diff --git a/XDMA/linux-kernel/tools/performance.c b/xdma/tools/performance.c similarity index 100% rename from XDMA/linux-kernel/tools/performance.c rename to xdma/tools/performance.c diff --git a/XDMA/linux-kernel/tools/reg_rw.c b/xdma/tools/reg_rw.c similarity index 100% rename from XDMA/linux-kernel/tools/reg_rw.c rename to xdma/tools/reg_rw.c diff --git a/XDMA/linux-kernel/tools/test_chrdev.c b/xdma/tools/test_chrdev.c similarity index 100% rename from XDMA/linux-kernel/tools/test_chrdev.c rename to xdma/tools/test_chrdev.c diff --git a/XDMA/linux-kernel/xdma/.gitignore b/xdma/xdma/.gitignore similarity index 100% rename from XDMA/linux-kernel/xdma/.gitignore rename to xdma/xdma/.gitignore diff --git a/XDMA/linux-kernel/xdma/Makefile b/xdma/xdma/Makefile similarity index 100% rename from XDMA/linux-kernel/xdma/Makefile rename to xdma/xdma/Makefile diff --git a/XDMA/linux-kernel/xdma/cdev_bypass.c b/xdma/xdma/cdev_bypass.c similarity index 100% rename from XDMA/linux-kernel/xdma/cdev_bypass.c rename to xdma/xdma/cdev_bypass.c diff --git a/XDMA/linux-kernel/xdma/cdev_ctrl.c b/xdma/xdma/cdev_ctrl.c similarity index 100% rename from XDMA/linux-kernel/xdma/cdev_ctrl.c rename to xdma/xdma/cdev_ctrl.c diff --git a/XDMA/linux-kernel/xdma/cdev_ctrl.h b/xdma/xdma/cdev_ctrl.h similarity index 100% rename from XDMA/linux-kernel/xdma/cdev_ctrl.h rename to xdma/xdma/cdev_ctrl.h diff --git a/XDMA/linux-kernel/xdma/cdev_events.c b/xdma/xdma/cdev_events.c similarity index 100% rename from XDMA/linux-kernel/xdma/cdev_events.c rename to xdma/xdma/cdev_events.c diff --git a/XDMA/linux-kernel/xdma/cdev_sgdma.c b/xdma/xdma/cdev_sgdma.c similarity index 100% rename from XDMA/linux-kernel/xdma/cdev_sgdma.c rename to xdma/xdma/cdev_sgdma.c diff --git a/XDMA/linux-kernel/xdma/cdev_sgdma.h b/xdma/xdma/cdev_sgdma.h similarity index 100% rename from XDMA/linux-kernel/xdma/cdev_sgdma.h rename to xdma/xdma/cdev_sgdma.h diff --git a/XDMA/linux-kernel/xdma/cdev_xvc.c b/xdma/xdma/cdev_xvc.c similarity index 100% rename from XDMA/linux-kernel/xdma/cdev_xvc.c rename to xdma/xdma/cdev_xvc.c diff --git a/XDMA/linux-kernel/xdma/cdev_xvc.h b/xdma/xdma/cdev_xvc.h similarity index 100% rename from XDMA/linux-kernel/xdma/cdev_xvc.h rename to xdma/xdma/cdev_xvc.h diff --git a/XDMA/linux-kernel/xdma/libxdma.c b/xdma/xdma/libxdma.c similarity index 100% rename from XDMA/linux-kernel/xdma/libxdma.c rename to xdma/xdma/libxdma.c diff --git a/XDMA/linux-kernel/xdma/libxdma.h b/xdma/xdma/libxdma.h similarity index 100% rename from XDMA/linux-kernel/xdma/libxdma.h rename to xdma/xdma/libxdma.h diff --git a/XDMA/linux-kernel/xdma/version.h b/xdma/xdma/version.h similarity index 100% rename from XDMA/linux-kernel/xdma/version.h rename to xdma/xdma/version.h diff --git a/XDMA/linux-kernel/xdma/xdma_cdev.c b/xdma/xdma/xdma_cdev.c similarity index 100% rename from XDMA/linux-kernel/xdma/xdma_cdev.c rename to xdma/xdma/xdma_cdev.c diff --git a/XDMA/linux-kernel/xdma/xdma_cdev.h b/xdma/xdma/xdma_cdev.h similarity index 100% rename from XDMA/linux-kernel/xdma/xdma_cdev.h rename to xdma/xdma/xdma_cdev.h diff --git a/XDMA/linux-kernel/xdma/xdma_mod.c b/xdma/xdma/xdma_mod.c similarity index 100% rename from XDMA/linux-kernel/xdma/xdma_mod.c rename to xdma/xdma/xdma_mod.c diff --git a/XDMA/linux-kernel/xdma/xdma_mod.h b/xdma/xdma/xdma_mod.h similarity index 100% rename from XDMA/linux-kernel/xdma/xdma_mod.h rename to xdma/xdma/xdma_mod.h diff --git a/XDMA/linux-kernel/xdma/xdma_thread.c b/xdma/xdma/xdma_thread.c similarity index 100% rename from XDMA/linux-kernel/xdma/xdma_thread.c rename to xdma/xdma/xdma_thread.c diff --git a/XDMA/linux-kernel/xdma/xdma_thread.h b/xdma/xdma/xdma_thread.h similarity index 100% rename from XDMA/linux-kernel/xdma/xdma_thread.h rename to xdma/xdma/xdma_thread.h From 524fec5c7bdc72dc8121ba149d8c1bbdd65d7a14 Mon Sep 17 00:00:00 2001 From: Gon Solo Date: Thu, 25 Apr 2024 19:42:21 +0200 Subject: [PATCH 20/22] Ignore. --- xvsec/.gitignore | 2 ++ 1 file changed, 2 insertions(+) create mode 100644 xvsec/.gitignore diff --git a/xvsec/.gitignore b/xvsec/.gitignore new file mode 100644 index 000000000..fdbbe2629 --- /dev/null +++ b/xvsec/.gitignore @@ -0,0 +1,2 @@ +/build +*.cmd From fa7abf2c5f76929e1e366cefc67676ceb36f4d8e Mon Sep 17 00:00:00 2001 From: Gon Solo Date: Mon, 29 Apr 2024 09:58:55 +0200 Subject: [PATCH 21/22] Fix "module verification failed" message. --- xdma/xdma/Makefile | 1 + 1 file changed, 1 insertion(+) diff --git a/xdma/xdma/Makefile b/xdma/xdma/Makefile index 18e25f352..a77785fdd 100644 --- a/xdma/xdma/Makefile +++ b/xdma/xdma/Makefile @@ -1,3 +1,4 @@ +CONFIG_MODULE_SIG=n SHELL = /bin/bash # # optional makefile parameters: From 433c584e7b49ba62b1f5c7eff10f333bacbafbf1 Mon Sep 17 00:00:00 2001 From: Gon Solo Date: Wed, 1 May 2024 11:22:57 +0200 Subject: [PATCH 22/22] Add dependencies. "sudo make -j10 clean install" didn't work as intended. --- xvsec/Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/xvsec/Makefile b/xvsec/Makefile index 7a98486e7..6a3317a4a 100644 --- a/xvsec/Makefile +++ b/xvsec/Makefile @@ -54,7 +54,7 @@ clean : cd tools && $(MAKE) clean .PHONY : install -install : +install : tools drv @echo "installing kernel modules to $(kernel_install_path) ..." @mkdir -p -m 755 $(kernel_install_path) @install -v -m 644 $(BUILD_DIR)/modules/*.ko $(kernel_install_path)
-

Xilinx QDMA IP Drivers Documentation

-
-

- Xilinx QDMA IP Drivers documentation is organized by release version. -

-

Please use the following links to browse Xilinx QDMA IP Drivers documentation for a specific release. -

- -

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