drivers: iicps: Add support for 10-bit address in Master/Slave.

While addressing slave devices/setting up slave address in the I2C controller, the address setting(7/10-bit) is made configurable with SetOptions function. Signed-off-by: Raviteja Narayanam <raviteja.narayanam@xilinx.com> Acked-for-series: Shubhrajyoti Datta <shubhrajyoti.datta@xilinx.com>
Xilinx · Jan 13, 2020 · 2defed6 · 2defed6
1 parent 2c47319
commit 2defed6
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Showing 4 changed files with 41 additions and 9 deletions.
diff --git a/XilinxProcessorIPLib/drivers/iicps/src/xiicps.h b/XilinxProcessorIPLib/drivers/iicps/src/xiicps.h
@@ -185,7 +185,7 @@
 * 3.8   ask  08/01/18   Fix for Cppcheck and Doxygen warnings
 * 3.8   sd 09/06/18  Enable the Timeout interrupt
 * 3.9   sg 03/09/19  Added arbitration lost support in polled transfer
-*
+* 3.11  rna  12/23/19 Added 10 bit address support for Master/Slave
 * </pre>
 *
 ******************************************************************************/
@@ -295,6 +295,7 @@ typedef struct {
 	s32 UpdateTxSize;	/* If tx size register has to be updated */
 	s32 IsSend;		/* Whether master is sending or receiving */
 	s32 IsRepeatedStart;	/* Indicates if user set repeated start */
+	s32 Is10BitAddr;	/* Indicates if user set 10 bit address */
 
 	XIicPs_IntrHandler StatusHandler;  /* Event handler function */
 	void *CallBackRef;	/* Callback reference for event handler */

diff --git a/XilinxProcessorIPLib/drivers/iicps/src/xiicps_master.c b/XilinxProcessorIPLib/drivers/iicps/src/xiicps_master.c
@@ -62,6 +62,7 @@
 * 3.8   sd 09/06/18  Enable the Timeout interrupt
 * 3.9   sg 03/09/19  Added arbitration lost support in polled transfer
 * 3.11  rna 12/20/19 Clear the ISR before enabling interrupts in Send/Receive.
+*           12/23/19 Add 10 bit address support for Master/Slave
 * </pre>
 *
 ******************************************************************************/
@@ -612,10 +613,19 @@ void XIicPs_EnableSlaveMonitor(XIicPs *InstancePtr, u16 SlaveAddr)
 	 * Enable slave monitor mode in control register.
 	 */
 	ConfigReg = XIicPs_ReadReg(BaseAddr, (u32)XIICPS_CR_OFFSET);
-	ConfigReg |= (u32)XIICPS_CR_MS_MASK | (u32)XIICPS_CR_NEA_MASK |
-			(u32)XIICPS_CR_CLR_FIFO_MASK | (u32)XIICPS_CR_SLVMON_MASK;
+	ConfigReg |= (u32)XIICPS_CR_MS_MASK | (u32)XIICPS_CR_CLR_FIFO_MASK |
+			(u32)XIICPS_CR_SLVMON_MASK;
 	ConfigReg &= (u32)(~XIICPS_CR_RD_WR_MASK);
 
+	/*
+	 * Check if 10 bit address option is set.
+	 */
+	if (InstancePtr->Is10BitAddr == 1) {
+		ConfigReg &= (u32)(~XIICPS_CR_NEA_MASK);
+	} else {
+		ConfigReg |= (u32)(XIICPS_CR_NEA_MASK);
+	}
+
 	XIicPs_WriteReg(BaseAddr, (u32)XIICPS_CR_OFFSET, ConfigReg);
 
 	/*
@@ -974,10 +984,19 @@ static s32 XIicPs_SetupMaster(XIicPs *InstancePtr, s32 Role)
 	}
 
 	/*
-	 * Set up master, AckEn, nea and also clear fifo.
+	 * Set up master, AckEn, and also clear fifo.
 	 */
 	ControlReg |= (u32)XIICPS_CR_ACKEN_MASK | (u32)XIICPS_CR_CLR_FIFO_MASK |
-			(u32)XIICPS_CR_NEA_MASK | (u32)XIICPS_CR_MS_MASK;
+			(u32)XIICPS_CR_MS_MASK;
+
+	/*
+	 * Check if 10 bit address option is set. Clear/Set NEA accordingly.
+	 */
+	if (InstancePtr->Is10BitAddr == 1) {
+		ControlReg &= (u32)(~XIICPS_CR_NEA_MASK);
+	} else {
+		ControlReg |= (u32)(XIICPS_CR_NEA_MASK);
+	}
 
 	if (Role == RECVING_ROLE) {
 		ControlReg |= (u32)XIICPS_CR_RD_WR_MASK;

diff --git a/XilinxProcessorIPLib/drivers/iicps/src/xiicps_options.c b/XilinxProcessorIPLib/drivers/iicps/src/xiicps_options.c
@@ -50,7 +50,7 @@
 * 3.0	sk	12/06/14 Implemented Repeated start feature.
 *			01/31/15 Modified the code according to MISRAC 2012 Compliant.
 * 3.3   kvn 05/05/16 Modified latest code for MISRA-C:2012 Compliance.
-*
+* 3.11  rna 12/23/19 Add 10 bit address support for Master/Slave
 * </pre>
 *
 ******************************************************************************/
@@ -148,9 +148,11 @@ s32 XIicPs_SetOptions(XIicPs *InstancePtr, u32 Options)
 			if ((OptionsTable[Index].Option &
 				XIICPS_10_BIT_ADDR_OPTION) != (u32)0x0U) {
 				/* Turn 7-bit off */
+				InstancePtr->Is10BitAddr = 1;
 				ControlReg &= ~OptionsTable[Index].Mask;
 			} else {
 				/* Turn 7-bit on */
+				InstancePtr->Is10BitAddr = 0;
 				ControlReg |= OptionsTable[Index].Mask;
 			}
 		}
@@ -228,12 +230,13 @@ s32 XIicPs_ClearOptions(XIicPs *InstancePtr, u32 Options)
 			 */
 			if ((OptionsTable[Index].Option &
 				XIICPS_10_BIT_ADDR_OPTION) != (u32)0x0U) {
-
 				/* Turn 7-bit on */
+				InstancePtr->Is10BitAddr = 0;
 				ControlReg |= OptionsTable[Index].Mask;
 			} else {
 
 				/* Turn 7-bit off */
+				InstancePtr->Is10BitAddr = 1;
 				ControlReg &= ~OptionsTable[Index].Mask;
 			}
 		}

diff --git a/XilinxProcessorIPLib/drivers/iicps/src/xiicps_slave.c b/XilinxProcessorIPLib/drivers/iicps/src/xiicps_slave.c
@@ -42,6 +42,7 @@
 * 3.8   ask 08/01/18 Fix for Cppcheck and Doxygen warnings.
 * 3.10 sg   06/24/19 Fix for Slave send polled and interruput transfers.
 * 3.11  rna 12/20/19 Clear the ISR before enabling interrupts in Send/Receive.
+*           12/23/19 Add 10 bit address support for Master/Slave
 * </pre>
 *
 ******************************************************************************/
@@ -93,12 +94,20 @@ void XIicPs_SetupSlave(XIicPs *InstancePtr, u16 SlaveAddr)
 	ControlReg = XIicPs_In32(BaseAddr + XIICPS_CR_OFFSET);
 
 	/*
-	 * Set up master, AckEn, nea and also clear fifo.
+	 * Set up master, AckEn and also clear fifo.
 	 */
 	ControlReg |= (u32)XIICPS_CR_ACKEN_MASK | (u32)XIICPS_CR_CLR_FIFO_MASK;
-	ControlReg |= (u32)XIICPS_CR_NEA_MASK;
 	ControlReg &= (u32)(~XIICPS_CR_MS_MASK);
 
+	/*
+	 * Check if 10 bit address option is set. Clear/Set NEA accordingly.
+	 */
+	if (InstancePtr->Is10BitAddr == 1) {
+		ControlReg &= (u32)(~XIICPS_CR_NEA_MASK);
+	} else {
+		ControlReg |= (u32)(XIICPS_CR_NEA_MASK);
+	}
+
 	XIicPs_WriteReg(BaseAddr, XIICPS_CR_OFFSET,
 			  ControlReg);