diff --git a/XilinxProcessorIPLib/drivers/axidma/examples/xaxidma_example_multichan_sg_intr.c b/XilinxProcessorIPLib/drivers/axidma/examples/xaxidma_example_multichan_sg_intr.c
index c0a8528d3a7..b6805885711 100644
--- a/XilinxProcessorIPLib/drivers/axidma/examples/xaxidma_example_multichan_sg_intr.c
+++ b/XilinxProcessorIPLib/drivers/axidma/examples/xaxidma_example_multichan_sg_intr.c
@@ -76,6 +76,8 @@
  *                     available in all examples. This is a fix for CR-965028.
  *       ms   04/05/17 Added tabspace for return statements in functions
  *                     for proper documentation while generating doxygen.
+ * 9.6   rsp  02/14/18 Support data buffers above 4GB. Use UINTPTR for storing
+ *                     and typecasting buffer address(CR-992638).
  * </pre>
  *
  * ***************************************************************************
@@ -949,8 +951,8 @@ static int RxSetup(XAxiDma * AxiDmaInstPtr)
 	XAxiDma_Bd *BdCurPtr;
 	int BdCount;
 	int FreeBdCount;
-	u32 RxBufferPtr;
-	u32 RxBdSpacePtr;
+	UINTPTR RxBufferPtr;
+	UINTPTR RxBdSpacePtr;
 	int Index;
 	int RingIndex;
 
@@ -1109,14 +1111,14 @@ static int TxSetup(XAxiDma * AxiDmaInstPtr)
 	int Status;
 	u32 BdCount;
 
-	u32 TxBdSpacePtr = TX_BD_SPACE_BASE;
+	UINTPTR TxBdSpacePtr = TX_BD_SPACE_BASE;
 
 	/* Disable all TX interrupts before TxBD space setup */
 	XAxiDma_BdRingIntDisable(TxRingPtr, XAXIDMA_IRQ_ALL_MASK);
 
 	/* Setup TxBD space  */
 	BdCount = XAxiDma_BdRingCntCalc(XAXIDMA_BD_MINIMUM_ALIGNMENT,
-			(u32)TX_BD_SPACE_HIGH - (u32)TX_BD_SPACE_BASE + 1);
+			(UINTPTR)TX_BD_SPACE_HIGH - (UINTPTR)TX_BD_SPACE_BASE + 1);
 
 	Status = XAxiDma_BdRingCreate(TxRingPtr, TxBdSpacePtr,
 				TxBdSpacePtr,
@@ -1197,7 +1199,7 @@ static int SendPacket(XAxiDma * AxiDmaInstPtr, u8 TDest, u8 TId, u8 Value)
 	XAxiDma_Bd *BdPtr, *BdCurPtr;
 	int Status;
 	int Index, Pkts;
-	u32 BufferAddr;
+	UINTPTR BufferAddr;
 
 	/*
 	 * Each packet is limited to TxRingPtr->MaxTransferLen
diff --git a/XilinxProcessorIPLib/drivers/axidma/examples/xaxidma_example_poll_multi_pkts.c b/XilinxProcessorIPLib/drivers/axidma/examples/xaxidma_example_poll_multi_pkts.c
index bdfa3bcdd49..4ff9290a4af 100644
--- a/XilinxProcessorIPLib/drivers/axidma/examples/xaxidma_example_poll_multi_pkts.c
+++ b/XilinxProcessorIPLib/drivers/axidma/examples/xaxidma_example_poll_multi_pkts.c
@@ -76,6 +76,8 @@
  *                     for proper documentation while generating doxygen.
  * 9.5   adk  17/10/17 Marked the BD region as Normal Non-Cacheable for A53
  *		       (CR#987026).
+ * 9.6   rsp  02/14/18 Support data buffers above 4GB.Use UINTPTR for storing
+ *                     and typecasting buffer address(CR-992638).
  * </pre>
  *
  * ***************************************************************************
@@ -311,7 +313,7 @@ static int RxSetup(XAxiDma * AxiDmaInstPtr)
 	XAxiDma_Bd *BdCurPtr;
 	u32 BdCount;
 	u32 FreeBdCount;
-	u32 RxBufferPtr;
+	UINTPTR RxBufferPtr;
 	int i;
 
 	RxRingPtr = XAxiDma_GetRxRing(&AxiDma);
@@ -493,7 +495,7 @@ static int SendPackets(XAxiDma * AxiDmaInstPtr)
 	XAxiDma_Bd *BdPtr;
 	int Status;
 	int i;
-	u32 BufAddr;
+	UINTPTR BufAddr;
 	XAxiDma_Bd *CurBdPtr;
 
 	/* Create pattern in the packet to transmit
@@ -617,7 +619,7 @@ static int CheckData(void)
 	 * Data Cache is enabled
 	 */
 #ifndef __aarch64__
-	Xil_DCacheInvalidateRange((u32)RxPacket, MAX_PKT_LEN *
+	Xil_DCacheInvalidateRange((UINTPTR)RxPacket, MAX_PKT_LEN *
 								NUMBER_OF_PACKETS);
 #endif
 
diff --git a/XilinxProcessorIPLib/drivers/axidma/examples/xaxidma_example_sg_intr.c b/XilinxProcessorIPLib/drivers/axidma/examples/xaxidma_example_sg_intr.c
index ddf6a23ec6f..d5934b1e83d 100644
--- a/XilinxProcessorIPLib/drivers/axidma/examples/xaxidma_example_sg_intr.c
+++ b/XilinxProcessorIPLib/drivers/axidma/examples/xaxidma_example_sg_intr.c
@@ -80,6 +80,8 @@
  *                     available in all examples. This is a fix for CR-965028.
  *       ms   04/05/17 Added tabspace for return statements in functions
  *                     for proper documentation while generating doxygen.
+ * 9.6   rsp  02/14/18 Support data buffers above 4GB.Use UINTPTR for storing
+ *                     and typecasting buffer address(CR-992638).
  * </pre>
  *
  * ***************************************************************************
@@ -436,7 +438,7 @@ static int CheckData(int Length, u8 StartValue)
 	 * Data Cache is enabled
 	 */
 #ifndef __aarch64__
-	Xil_DCacheInvalidateRange((u32)RxPacket, Length);
+	Xil_DCacheInvalidateRange((UINTPTR)RxPacket, Length);
 #endif
 
 	for(Index = 0; Index < Length; Index++) {
@@ -881,7 +883,7 @@ static int RxSetup(XAxiDma * AxiDmaInstPtr)
 	XAxiDma_Bd *BdCurPtr;
 	int BdCount;
 	int FreeBdCount;
-	u32 RxBufferPtr;
+	UINTPTR RxBufferPtr;
 	int Index;
 
 	RxRingPtr = XAxiDma_GetRxRing(&AxiDma);
@@ -1013,7 +1015,7 @@ static int TxSetup(XAxiDma * AxiDmaInstPtr)
 
 	/* Setup TxBD space  */
 	BdCount = XAxiDma_BdRingCntCalc(XAXIDMA_BD_MINIMUM_ALIGNMENT,
-			(u32)TX_BD_SPACE_HIGH - (u32)TX_BD_SPACE_BASE + 1);
+			(UINTPTR)TX_BD_SPACE_HIGH - (UINTPTR)TX_BD_SPACE_BASE + 1);
 
 	Status = XAxiDma_BdRingCreate(TxRingPtr, TX_BD_SPACE_BASE,
 				     TX_BD_SPACE_BASE,
@@ -1088,7 +1090,7 @@ static int SendPacket(XAxiDma * AxiDmaInstPtr)
 	XAxiDma_Bd *BdPtr, *BdCurPtr;
 	int Status;
 	int Index, Pkts;
-	u32 BufferAddr;
+	UINTPTR BufferAddr;
 
 	/*
 	 * Each packet is limited to TxRingPtr->MaxTransferLen
diff --git a/XilinxProcessorIPLib/drivers/axidma/examples/xaxidma_example_sgcyclic_intr.c b/XilinxProcessorIPLib/drivers/axidma/examples/xaxidma_example_sgcyclic_intr.c
index 34dc6bf44bd..6530b865703 100644
--- a/XilinxProcessorIPLib/drivers/axidma/examples/xaxidma_example_sgcyclic_intr.c
+++ b/XilinxProcessorIPLib/drivers/axidma/examples/xaxidma_example_sgcyclic_intr.c
@@ -62,6 +62,8 @@
  * Ver   Who  Date     Changes
  * ----- ---- -------- -------------------------------------------------------
  * 9.4   adk  25/07/17 Initial version.
+ * 9.6   rsp  02/14/18 Support data buffers above 4GB.Use UINTPTR for storing
+ *                     and typecasting buffer address(CR-992638).
  * </pre>
  *
  * ***************************************************************************
@@ -423,7 +425,7 @@ static int CheckData(int Length, u8 StartValue)
 	 * Data Cache is enabled
 	 */
 #ifndef __aarch64__
-	Xil_DCacheInvalidateRange((u32)RxPacket, Length);
+	Xil_DCacheInvalidateRange((UINTPTR)RxPacket, Length);
 #endif
 
 	for(Index = 0; Index < Length; Index++) {
@@ -805,7 +807,7 @@ static int RxSetup(XAxiDma * AxiDmaInstPtr)
 	XAxiDma_Bd *BdCurPtr;
 	int BdCount;
 	int FreeBdCount;
-	u32 RxBufferPtr;
+	UINTPTR RxBufferPtr;
 	int Index;
 
 	RxRingPtr = XAxiDma_GetRxRing(&AxiDma);
@@ -1010,7 +1012,7 @@ static int SendPacket(XAxiDma * AxiDmaInstPtr)
 	XAxiDma_Bd *BdPtr, *BdCurPtr;
 	int Status;
 	int Index, Pkts;
-	u32 BufferAddr;
+	UINTPTR BufferAddr;
 
 	/*
 	 * Each packet is limited to TxRingPtr->MaxTransferLen
diff --git a/XilinxProcessorIPLib/drivers/axidma/examples/xaxidma_example_simple_intr.c b/XilinxProcessorIPLib/drivers/axidma/examples/xaxidma_example_simple_intr.c
index 2b80ff1f5ab..941fd6eb275 100644
--- a/XilinxProcessorIPLib/drivers/axidma/examples/xaxidma_example_simple_intr.c
+++ b/XilinxProcessorIPLib/drivers/axidma/examples/xaxidma_example_simple_intr.c
@@ -74,6 +74,8 @@
  * 9.3   ms   01/23/17 Modified xil_printf statement in main function to
  *                     ensure that "Successfully ran" and "Failed" strings are
  *                     available in all examples. This is a fix for CR-965028.
+ * 9.6   rsp  02/14/18 Support data buffers above 4GB.Use UINTPTR for typecasting
+ *                     buffer address (CR-992638).
  * </pre>
  *
  * ***************************************************************************
@@ -438,7 +440,7 @@ static int CheckData(int Length, u8 StartValue)
 	 * Data Cache is enabled
 	 */
 #ifndef __aarch64__
-	Xil_DCacheInvalidateRange((u32)RxPacket, Length);
+	Xil_DCacheInvalidateRange((UINTPTR)RxPacket, Length);
 #endif
 
 	for(Index = 0; Index < Length; Index++) {