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axicdma: Extend AXI CDMA examples to support data buffers above 4GB
Use UINTPTR for storing and typecasting buffer address.

Signed-off-by: Radhey Shyam Pandey <radheys@xilinx.com>

Acked-for-series: Kedareswara rao Appana <appanad@xilinx.com>

Acked-for-series: Kedareswara rao Appana <appanad@xilinx.com>
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radheyxilinx authored and saddepal committed Feb 25, 2018
1 parent 2726413 commit 9fab83a
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Showing 6 changed files with 40 additions and 30 deletions.
2 changes: 1 addition & 1 deletion XilinxProcessorIPLib/drivers/axicdma/data/axicdma.mdd
Expand Up @@ -36,7 +36,7 @@ BEGIN driver axicdma
OPTION supported_peripherals = (axi_cdma_v[3-9]_[0-9][0-9]_[a-z] axi_cdma_v[3-9]_[0-9]);
OPTION driver_state = ACTIVE;
OPTION copyfiles = all;
OPTION VERSION = 4.3;
OPTION VERSION = 4.4;
OPTION NAME = axicdma;

END driver
Expand Down
Expand Up @@ -76,6 +76,8 @@
* ms 04/05/17 Modified Comment lines in functions to
* recognize it as documentation block for doxygen
* generation of examples.
* 4.4 rsp 02/22/18 Support data buffers above 4GB.Use UINTPTR for storing
* and typecasting buffer address(CR-995116).
* </pre>
*
****************************************************************************/
Expand Down Expand Up @@ -321,7 +323,7 @@ static int SetupSgTransfer(XAxiCdma *InstancePtr)
/* Setup BD ring */
BdCount = XAxiCdma_BdRingCntCalc(XAXICDMA_BD_MINIMUM_ALIGNMENT,
BD_SPACE_HIGH - BD_SPACE_BASE + 1,
(u32)BD_SPACE_BASE);
(UINTPTR)BD_SPACE_BASE);

Status = XAxiCdma_BdRingCreate(InstancePtr, BD_SPACE_BASE,
BD_SPACE_BASE, XAXICDMA_BD_MINIMUM_ALIGNMENT, BdCount);
Expand Down Expand Up @@ -358,7 +360,7 @@ static int SetupSgTransfer(XAxiCdma *InstancePtr)
/* Flush the SrcBuffer before the DMA transfer, in case the Data Cache
* is enabled
*/
Xil_DCacheFlushRange((u32)TransmitBufferPtr,
Xil_DCacheFlushRange((UINTPTR)TransmitBufferPtr,
MAX_PKT_LEN * NUMBER_OF_BDS_TO_TRANSFER);

/* Setup interrupt coalescing and delay timer
Expand Down Expand Up @@ -497,7 +499,7 @@ static int CheckData(u8 *SrcPtr, u8 *DestPtr, int Length)
/* Invalidate the DestBuffer before receiving the data,
* in case the data cache is enabled
*/
Xil_DCacheInvalidateRange((u32)DestPtr, Length);
Xil_DCacheInvalidateRange((UINTPTR)DestPtr, Length);

for (Index = 0; Index < Length; Index++) {
if ( DestPtr[Index] != SrcPtr[Index]) {
Expand Down Expand Up @@ -746,15 +748,15 @@ static int DoSimpleTransfer(XAxiCdma *InstancePtr, int Length, int Retries)
/* Flush the SrcBuffer before the DMA transfer, in case the Data Cache
* is enabled
*/
Xil_DCacheFlushRange((u32)&SrcBuffer, Length);
Xil_DCacheFlushRange((UINTPTR)&SrcBuffer, Length);

/* Try to start the DMA transfer
*/
while (Retries) {
Retries -= 1;

Status = XAxiCdma_SimpleTransfer(InstancePtr, (u32)SrcBuffer,
(u32)DestBuffer, Length, Example_SimpleCallBack,
Status = XAxiCdma_SimpleTransfer(InstancePtr, (UINTPTR)SrcBuffer,
(UINTPTR)DestBuffer, Length, Example_SimpleCallBack,
InstancePtr);

if (Status == XST_SUCCESS) {
Expand Down Expand Up @@ -816,8 +818,8 @@ static int SubmitSgTransfer(XAxiCdma * InstancePtr)
XAxiCdma_Bd *BdCurPtr;
int Status;
int Index;
u32 SrcBufferAddr;
u32 DstBufferAddr;
UINTPTR SrcBufferAddr;
UINTPTR DstBufferAddr;
static int Counter = 0;

Status = XAxiCdma_BdRingAlloc(InstancePtr,
Expand All @@ -828,8 +830,8 @@ static int SubmitSgTransfer(XAxiCdma * InstancePtr)
return XST_FAILURE;
}

SrcBufferAddr = (u32)TransmitBufferPtr;
DstBufferAddr = (u32)ReceiveBufferPtr;
SrcBufferAddr = (UINTPTR)TransmitBufferPtr;
DstBufferAddr = (UINTPTR)ReceiveBufferPtr;
BdCurPtr = BdPtr;

/* Set up the BDs
Expand Down
Expand Up @@ -75,6 +75,8 @@
* ms 04/05/17 Modified Comment lines in functions to
* recognize it as documentation block for doxygen
* generation of examples.
* 4.4 rsp 02/22/18 Support data buffers above 4GB.Use UINTPTR for storing
* and typecasting buffer address(CR-995116).
* </pre>
*
****************************************************************************/
Expand Down Expand Up @@ -266,7 +268,7 @@ static int SetupSgTransfer(XAxiCdma *InstancePtr)
/* Setup BD ring */
BdCount = XAxiCdma_BdRingCntCalc(XAXICDMA_BD_MINIMUM_ALIGNMENT,
BD_SPACE_HIGH - BD_SPACE_BASE + 1,
(u32)BD_SPACE_BASE);
(UINTPTR)BD_SPACE_BASE);

Status = XAxiCdma_BdRingCreate(InstancePtr, BD_SPACE_BASE,
BD_SPACE_BASE, XAXICDMA_BD_MINIMUM_ALIGNMENT, BdCount);
Expand Down Expand Up @@ -302,7 +304,7 @@ static int SetupSgTransfer(XAxiCdma *InstancePtr)
/* Flush the SrcBuffer before the DMA transfer, in case the Data Cache
* is enabled
*/
Xil_DCacheFlushRange((u32)TransmitBufferPtr,
Xil_DCacheFlushRange((UINTPTR)TransmitBufferPtr,
MAX_PKT_LEN * NUMBER_OF_BDS_TO_TRANSFER);

return XST_SUCCESS;
Expand All @@ -327,8 +329,8 @@ static int SubmitSgTransfer(XAxiCdma *InstancePtr)
XAxiCdma_Bd *BdCurPtr;
int Status;
int Index;
u32 SrcBufferAddr;
u32 DstBufferAddr;
UINTPTR SrcBufferAddr;
UINTPTR DstBufferAddr;

Status = XAxiCdma_BdRingAlloc(InstancePtr,
NUMBER_OF_BDS_TO_TRANSFER, &BdPtr);
Expand All @@ -338,8 +340,8 @@ static int SubmitSgTransfer(XAxiCdma *InstancePtr)
return XST_FAILURE;
}

SrcBufferAddr = (u32)TransmitBufferPtr;
DstBufferAddr = (u32)ReceiveBufferPtr;
SrcBufferAddr = (UINTPTR)TransmitBufferPtr;
DstBufferAddr = (UINTPTR)ReceiveBufferPtr;
BdCurPtr = BdPtr;

/* Set up the BDs
Expand Down Expand Up @@ -482,7 +484,7 @@ static int CheckData(u8 *SrcPtr, u8 *DestPtr, int Length)
/* Invalidate the DestBuffer before receiving the data,
* in case the data cache is enabled
*/
Xil_DCacheInvalidateRange((u32)DestPtr, Length);
Xil_DCacheInvalidateRange((UINTPTR)DestPtr, Length);

for (Index = 0; Index < Length; Index++) {
if ( DestPtr[Index] != SrcPtr[Index]) {
Expand Down Expand Up @@ -533,15 +535,15 @@ static int DoSimplePollTransfer(XAxiCdma *InstancePtr, int Length, int Retries)
/* Flush the SrcBuffer before the DMA transfer, in case the Data Cache
* is enabled
*/
Xil_DCacheFlushRange((u32)&SrcBuffer, Length);
Xil_DCacheFlushRange((UINTPTR)&SrcBuffer, Length);

/* Try to start the DMA transfer
*/
while (Retries) {
Retries -= 1;

Status = XAxiCdma_SimpleTransfer(InstancePtr, (u32)SrcBuffer,
(u32)DestBuffer, Length, NULL, NULL);
Status = XAxiCdma_SimpleTransfer(InstancePtr, (UINTPTR)SrcBuffer,
(UINTPTR)DestBuffer, Length, NULL, NULL);
if (Status == XST_SUCCESS) {
break;
}
Expand Down
Expand Up @@ -70,6 +70,8 @@
* ms 04/05/17 Modified Comment lines in functions to
* recognize it as documentation block for doxygen
* generation of examples.
* 4.4 rsp 02/22/18 Support data buffers above 4GB.Use UINTPTR for storing
* and typecasting buffer address(CR-995116).
* </pre>
*
****************************************************************************/
Expand Down Expand Up @@ -578,7 +580,7 @@ static int SetupTransfer(XAxiCdma * InstancePtr)
/* Setup BD ring */
BdCount = XAxiCdma_BdRingCntCalc(XAXICDMA_BD_MINIMUM_ALIGNMENT,
BD_SPACE_HIGH - BD_SPACE_BASE + 1,
(u32)BD_SPACE_BASE);
(UINTPTR)BD_SPACE_BASE);

if (BdCount < 1) {
xdbg_printf(XDBG_DEBUG_ERROR, "Invalid buffer %x\r\n",
Expand Down Expand Up @@ -621,7 +623,7 @@ static int SetupTransfer(XAxiCdma * InstancePtr)
/* Flush the SrcBuffer before the DMA transfer, in case the Data Cache
* is enabled
*/
Xil_DCacheFlushRange((u32)TransmitBufferPtr,
Xil_DCacheFlushRange((UINTPTR)TransmitBufferPtr,
MAX_PKT_LEN * NUMBER_OF_BDS_TO_TRANSFER);
#ifdef __aarch64__
Xil_DCacheFlushRange((UINTPTR)ReceiveBufferPtr,
Expand Down Expand Up @@ -663,8 +665,8 @@ static int DoTransfer(XAxiCdma * InstancePtr)
XAxiCdma_Bd *BdCurPtr;
int Status;
int Index;
u32 SrcBufferAddr;
u32 DstBufferAddr;
UINTPTR SrcBufferAddr;
UINTPTR DstBufferAddr;
static int Counter = 0;

Status = XAxiCdma_BdRingAlloc(InstancePtr,
Expand All @@ -675,8 +677,8 @@ static int DoTransfer(XAxiCdma * InstancePtr)
return XST_FAILURE;
}

SrcBufferAddr = (u32)TransmitBufferPtr;
DstBufferAddr = (u32)ReceiveBufferPtr;
SrcBufferAddr = (UINTPTR)TransmitBufferPtr;
DstBufferAddr = (UINTPTR)ReceiveBufferPtr;
BdCurPtr = BdPtr;

/* Set up the BDs
Expand Down
Expand Up @@ -70,6 +70,8 @@
* ms 04/05/17 Modified Comment lines in functions to
* recognize it as documentation block for doxygen
* generation of examples.
* 4.4 rsp 02/22/18 Support data buffers above 4GB.Use UINTPTR for
* typecasting buffer address(CR-995116).
* </pre>
*
****************************************************************************/
Expand Down Expand Up @@ -330,7 +332,7 @@ static int SetupTransfer(XAxiCdma * InstancePtr)
/* Setup BD ring */
BdCount = XAxiCdma_BdRingCntCalc(XAXICDMA_BD_MINIMUM_ALIGNMENT,
BD_SPACE_HIGH - BD_SPACE_BASE + 1,
(u32)BD_SPACE_BASE);
(UINTPTR)BD_SPACE_BASE);

Status = XAxiCdma_BdRingCreate(InstancePtr, BD_SPACE_BASE,
BD_SPACE_BASE, XAXICDMA_BD_MINIMUM_ALIGNMENT, BdCount);
Expand Down
Expand Up @@ -70,6 +70,8 @@
* ms 04/05/17 Modified Comment lines in functions to
* recognize it as documentation block for doxygen
* generation of examples.
* 4.4 rsp 02/22/18 Support data buffers above 4GB.Use UINTPTR for
* typecasting buffer address(CR-995116).
* </pre>
*
****************************************************************************/
Expand Down Expand Up @@ -341,8 +343,8 @@ static int DoSimpleTransfer(XAxiCdma *InstancePtr, int Length, int Retries)
while (Retries) {
Retries -= 1;

Status = XAxiCdma_SimpleTransfer(InstancePtr, (u32)SrcBuffer,
(u32)DestBuffer, Length, Example_CallBack,
Status = XAxiCdma_SimpleTransfer(InstancePtr, (UINTPTR)SrcBuffer,
(UINTPTR)DestBuffer, Length, Example_CallBack,
(void *)InstancePtr);

if (Status == XST_SUCCESS) {
Expand Down

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