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sw_apps :zynqmp_fsbl: Remove USB Phy Reset code from FSBL

This is because the USB phy reset code is now added in psu_init code.
Code to provide reset to USB Phy was present in FSBL, under board
specific code. This code should ideally be active for all other Xilinx boards as for
all the Xilinx designs "bootmode pin" is used for reset of USB Phy.
However, we cannot hard code this in FSBL as in custom boards USB Phy
Reset can be implemented using different pin. Hence the code is moved to psu_init.

Signed-off-by: Vikram Sreenivasa Batchali <bvikram@xilinx.com>

Acked-by: Sarat Chand Savitala <saratcha@xilinx.com>
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b.vikram@xilinx.com Shireesha Kothakonda
b.vikram@xilinx.com authored and Shireesha Kothakonda committed Jun 18, 2018
1 parent 05ed173 commit c258818de03f7b7a0aa62aae9488c24b57ab4215
@@ -70,7 +70,6 @@ static u32 XFsbl_ReadMinMaxEepromVadj(XIicPs* I2c0InstancePtr, u32 *MinVadj, u32
static u32 XFsbl_CalVadj(u16 MinVoltage, u16 MaxVoltage);
#endif
static u32 XFsbl_BoardConfig(void);
static void XFsbl_UsbPhyReset(void);
static u32 XFsbl_FMCEnable(XIicPs* I2c0InstancePtr);
#if defined(XPS_BOARD_ZCU102)
static void XFsbl_PcieReset(void);
@@ -724,27 +723,6 @@ static u32 XFsbl_BoardConfig(void)

}

/*****************************************************************************/
/**
* This function is used to provide Reset to USB Phy on ZCU102 board.
*
* @param none
*
* @return none
*
*****************************************************************************/
static void XFsbl_UsbPhyReset(void)
{

/* USB PHY Reset */
XFsbl_Out32(CRL_APB_BOOT_PIN_CTRL, CRL_APB_BOOTMODE_1_HI);
(void)usleep(DELAY_1_US);
XFsbl_Out32(CRL_APB_BOOT_PIN_CTRL, CRL_APB_BOOTMODE_1_LO);
(void)usleep(DELAY_5_US);
XFsbl_Out32(CRL_APB_BOOT_PIN_CTRL, CRL_APB_BOOTMODE_1_HI);

}

#if defined(XPS_BOARD_ZCU102)
/*****************************************************************************/
/**
@@ -817,7 +795,6 @@ u32 XFsbl_BoardInit(void)
goto END;
}

XFsbl_UsbPhyReset();
#if defined(XPS_BOARD_ZCU102)
XFsbl_PcieReset();
#endif
@@ -69,9 +69,6 @@ extern "C" {
/************************** Constant Definitions *****************************/
#define GPIO_MIO31_MASK 0x00000020U

#define CRL_APB_BOOTMODE_1_HI 0x00000202U
#define CRL_APB_BOOTMODE_1_LO 0x00000002U

#define IIC_SCLK_RATE_IOEXP 400000U
#define IIC_SCLK_RATE_I2CMUX 600000U

@@ -283,8 +283,6 @@ extern "C" {
#define CRL_APB_RPLL_CTRL ( ( CRL_APB_BASEADDR ) + 0X00000030U )
#define CRL_APB_RPLL_CTRL_BYPASS_MASK 0X00000008U

/* Register: CRL_APB_BOOT_PIN_CTRL */
#define CRL_APB_BOOT_PIN_CTRL ( ( CRL_APB_BASEADDR ) + 0X00000250U)

/* apu */

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