From 76bc63621df9cfe525c140f2c762d802401b1d03 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Tue, 5 Dec 2023 11:36:35 -0800 Subject: [PATCH 1/5] Fix make.yml with "&& exit 1" instead of ! Signed-off-by: Eddie Hung --- .github/workflows/make.yml | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/.github/workflows/make.yml b/.github/workflows/make.yml index 8275f88..ab8df96 100644 --- a/.github/workflows/make.yml +++ b/.github/workflows/make.yml @@ -82,8 +82,8 @@ jobs: grep -H PASS *.check || ${{ secrets.REPORT_ROUTE_STATUS_URL == '' }} grep -H -e "# of nets with routing errors[. :]\+0" *.check.log || ${{ secrets.REPORT_ROUTE_STATUS_URL == '' }} # Check no multiple sources, no stubs - ! grep "UserWarning: Found [0-9]\+ sources" *.wirelength - ! grep "UserWarning: Found [0-9]\+ stubs" *.wirelength + grep "UserWarning: Found [0-9]\+ sources" *.wirelength && exit 1 + grep "UserWarning: Found [0-9]\+ stubs" *.wirelength && exit 1 # Check wirelength was computed grep "^Wirelength: [1-9][0-9]*" *.wirelength - name: Verify fail (nxroute-poc) @@ -93,7 +93,7 @@ jobs: # Allow following grep to fail if no URL grep -H -e "# of nets with routing errors[. :]\+[1-9]" -e "# of unrouted nets[. :]\+[1-9]" *.check.log || ${{ secrets.REPORT_ROUTE_STATUS_URL == '' }} # Check no multiple sources, but expect stubs - ! grep "UserWarning: Found [0-9]\+ sources" *.wirelength + grep "UserWarning: Found [0-9]\+ sources" *.wirelength && exit 1 grep "UserWarning: Found [0-9]\+ stubs" *.wirelength || ${{ matrix.benchmark == 'koios_dla_like_large' }} # Allow wirelength computation to fail since nxroute may not have routed anything or wirelength_analyzer was not run grep "^Wirelength: [1-9][0-9]*" *.wirelength || true From 3c57f02c1655de397e8ad829b56b227f2fab1123 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Tue, 5 Dec 2023 11:36:40 -0800 Subject: [PATCH 2/5] Use temp BENCHMARKS_URL Signed-off-by: Eddie Hung --- Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Makefile b/Makefile index d33af15..a955874 100644 --- a/Makefile +++ b/Makefile @@ -21,7 +21,7 @@ BENCHMARKS ?= boom_med_pb \ ispd16_example2 -BENCHMARKS_URL = https://github.com/Xilinx/fpga24_routing_contest/releases/latest/download/benchmarks.tar.gz +BENCHMARKS_URL = https://github.com/eddieh-xlnx/fpga24_routing_contest/releases/download/benchmarks/benchmarks.tar.gz # Inherit proxy settings from the host if they exist HTTPHOST=$(firstword $(subst :, ,$(subst http:,,$(subst /,,$(HTTP_PROXY))))) From cafc9741d679ded7ebffff601f1b69944f7ca02a Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Tue, 5 Dec 2023 11:53:57 -0800 Subject: [PATCH 3/5] Add INBUF as recognized cell for wa.py Signed-off-by: Eddie Hung --- docs/score.md | 4 ++-- wirelength_analyzer/xcvup_device_data.py | 1 + 2 files changed, 3 insertions(+), 2 deletions(-) diff --git a/docs/score.md b/docs/score.md index 7f77dd2..9f818db 100644 --- a/docs/score.md +++ b/docs/score.md @@ -119,7 +119,7 @@ BEL input and output pins for each type of PhysCell. |`LUT1`, `LUT2`, `LUT3`, `LUT4`, `LUT5`, `LUT6` | (all) <- (all) | Look Up Table | |`CARRY8` | [see table CARRY8](#carry8-connectivity) | Fast Carry Logic | |`MUXF7`, `MUXF8`, `MUXF9` | (all) <- (all) | Intrasite Mux | -|`IBUFCTRL` | (all) <- (all) | Input Buffer | +|`IBUFCTRL`, `INBUF` | (all) <- (all) | Input Buffer | |`DSP_A_B_DATA`, `DSP_C_DATA`, `DSP_M_DATA`,
`DSP_PREADD_DATA`, `DSP_OUTPUT`, `DSP_ALU` | (none) <- (none) [see note](#dsp-cell-connectivity) | DSP Logic | |`DSP_MULTIPLIER`, `DSP_PREADD` | (all) <- (all) [see note](#dsp-cell-connectivity) | DSP Logic | |`PCIE40E4` | (none) <- (none) | PCIe Hard Macro | @@ -130,7 +130,7 @@ BEL input and output pins for each type of PhysCell. | BEL output pin | BEL input pins | |------------|----------------------------------------| | `O0` | `CIN`, `S0` | -|`CO0` | {input pins from `O0`} and `DI0`, `AX` | +| `CO0` | {input pins from `O0`} and `DI0`, `AX` | | `O1` | {input pins from `CO0`} and `S1` | | `CO1` | {input pins from `O1`} and `DI1`, `BX` | | `O2` | {input pins from `C01`} and `S2` | diff --git a/wirelength_analyzer/xcvup_device_data.py b/wirelength_analyzer/xcvup_device_data.py index 7c49156..49568d4 100644 --- a/wirelength_analyzer/xcvup_device_data.py +++ b/wirelength_analyzer/xcvup_device_data.py @@ -79,6 +79,7 @@ def __contains__(self, item): 'MUXF9': self.all_to_all, 'IBUFCTRL': self.all_to_all, + 'INBUF': self.all_to_all, # The following cell types are BELs that make up a DSP macro. # Such DSPs contains a number of optional pipelining registers, From 889e8caa56558def524f95b0f59a1686f4ea56e5 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Tue, 5 Dec 2023 12:08:57 -0800 Subject: [PATCH 4/5] Add OUTBUF too Signed-off-by: Eddie Hung --- docs/score.md | 2 +- wirelength_analyzer/xcvup_device_data.py | 1 + 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/docs/score.md b/docs/score.md index 9f818db..390d63f 100644 --- a/docs/score.md +++ b/docs/score.md @@ -119,7 +119,7 @@ BEL input and output pins for each type of PhysCell. |`LUT1`, `LUT2`, `LUT3`, `LUT4`, `LUT5`, `LUT6` | (all) <- (all) | Look Up Table | |`CARRY8` | [see table CARRY8](#carry8-connectivity) | Fast Carry Logic | |`MUXF7`, `MUXF8`, `MUXF9` | (all) <- (all) | Intrasite Mux | -|`IBUFCTRL`, `INBUF` | (all) <- (all) | Input Buffer | +|`IBUFCTRL`, `INBUF`, `OUTBUF` | (all) <- (all) | I/O Buffer | |`DSP_A_B_DATA`, `DSP_C_DATA`, `DSP_M_DATA`,
`DSP_PREADD_DATA`, `DSP_OUTPUT`, `DSP_ALU` | (none) <- (none) [see note](#dsp-cell-connectivity) | DSP Logic | |`DSP_MULTIPLIER`, `DSP_PREADD` | (all) <- (all) [see note](#dsp-cell-connectivity) | DSP Logic | |`PCIE40E4` | (none) <- (none) | PCIe Hard Macro | diff --git a/wirelength_analyzer/xcvup_device_data.py b/wirelength_analyzer/xcvup_device_data.py index 49568d4..d484442 100644 --- a/wirelength_analyzer/xcvup_device_data.py +++ b/wirelength_analyzer/xcvup_device_data.py @@ -80,6 +80,7 @@ def __contains__(self, item): 'IBUFCTRL': self.all_to_all, 'INBUF': self.all_to_all, + 'OUTBUF': self.all_to_all, # The following cell types are BELs that make up a DSP macro. # Such DSPs contains a number of optional pipelining registers, From f1816b68c8e9972e37191b0f469315ee05c9a85a Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Tue, 5 Dec 2023 12:20:42 -0800 Subject: [PATCH 5/5] OUTBUF -> OBUFT Signed-off-by: Eddie Hung --- docs/score.md | 2 +- wirelength_analyzer/xcvup_device_data.py | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/docs/score.md b/docs/score.md index 390d63f..9902c5c 100644 --- a/docs/score.md +++ b/docs/score.md @@ -119,7 +119,7 @@ BEL input and output pins for each type of PhysCell. |`LUT1`, `LUT2`, `LUT3`, `LUT4`, `LUT5`, `LUT6` | (all) <- (all) | Look Up Table | |`CARRY8` | [see table CARRY8](#carry8-connectivity) | Fast Carry Logic | |`MUXF7`, `MUXF8`, `MUXF9` | (all) <- (all) | Intrasite Mux | -|`IBUFCTRL`, `INBUF`, `OUTBUF` | (all) <- (all) | I/O Buffer | +|`IBUFCTRL`, `INBUF`, `OBUFT` | (all) <- (all) | I/O Buffer | |`DSP_A_B_DATA`, `DSP_C_DATA`, `DSP_M_DATA`,
`DSP_PREADD_DATA`, `DSP_OUTPUT`, `DSP_ALU` | (none) <- (none) [see note](#dsp-cell-connectivity) | DSP Logic | |`DSP_MULTIPLIER`, `DSP_PREADD` | (all) <- (all) [see note](#dsp-cell-connectivity) | DSP Logic | |`PCIE40E4` | (none) <- (none) | PCIe Hard Macro | diff --git a/wirelength_analyzer/xcvup_device_data.py b/wirelength_analyzer/xcvup_device_data.py index d484442..259056b 100644 --- a/wirelength_analyzer/xcvup_device_data.py +++ b/wirelength_analyzer/xcvup_device_data.py @@ -80,7 +80,7 @@ def __contains__(self, item): 'IBUFCTRL': self.all_to_all, 'INBUF': self.all_to_all, - 'OUTBUF': self.all_to_all, + 'OBUFT': self.all_to_all, # The following cell types are BELs that make up a DSP macro. # Such DSPs contains a number of optional pipelining registers,