diff --git a/wirelength_analyzer/xcvup_device_data.py b/wirelength_analyzer/xcvup_device_data.py index 2ebcc31..c7508c0 100644 --- a/wirelength_analyzer/xcvup_device_data.py +++ b/wirelength_analyzer/xcvup_device_data.py @@ -104,6 +104,7 @@ def __contains__(self, item): # et al, link: https://www.rapidwright.io/docs/_downloads/6610b931d8a2e053e69a499d3923077f/FPT19-TimingModel.pdf self.pips = [ #intra-tile (zero wirelength) + # INT tiles (re.compile(r'LOGIC_OUTS_[LR]\d{1,2}'), 0), (re.compile(r'INT_NODE_SDQ_\d{1,2}_INT_OUT[01]'), 0), (re.compile(r'INT_NODE_IMUX_\d{1,2}_INT_OUT[01]'), 0), @@ -118,6 +119,13 @@ def __contains__(self, item): (re.compile(r'BOUNCE_[EW]_\d{1,2}_FT[01]'), 0), (re.compile(r'INODE_[EW]_\d{1,2}_FT[01]'), 0), (re.compile(r'SDQNODE_[EW]_\d{1,2}_FT[01]'), 0), + # LAG_LAG tiles + (re.compile(r'LAG_MUX_ATOM_\d{1,2}_TXOUT'), 0), + (re.compile(r'UBUMP\d{1,2}'), 0), # In multi-SLR devices, this wire is typically + # used to cross the SLR. Since the xcvu3p is + # a single SLR device, this wire can only be + # used as a 'U-turn' back into the same tile + (re.compile(r'RXD\d{1,2}'), 0), #single horizontal (re.compile(r'[EW]{2}1_[EW]_BEG[0-7]'), 1), @@ -155,7 +163,7 @@ def __contains__(self, item): self.tile_types = { 'CLEL_R', 'CLEM', 'CLEM_R', 'BRAM', 'DSP', 'XIPHY_BYTE_L', 'HPIO_L', 'CMT_L', 'URAM_URAM_FT', 'URAM_URAM_DELAY_FT', 'GTY_L', - 'GTY_R' + 'GTY_R', 'LAG_LAG' } # bels that drive global nets