From 6a0515bab19bb2568edb11692fda74db66b236dd Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Wed, 3 Jan 2024 14:21:05 -0800 Subject: [PATCH 1/4] [WirelengthAnalyzer] Support U-turns in Laguna tiles Since the xcvu3p is a single SLR device Signed-off-by: Eddie Hung --- wirelength_analyzer/xcvup_device_data.py | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/wirelength_analyzer/xcvup_device_data.py b/wirelength_analyzer/xcvup_device_data.py index 2ebcc31..7c33a91 100644 --- a/wirelength_analyzer/xcvup_device_data.py +++ b/wirelength_analyzer/xcvup_device_data.py @@ -104,6 +104,7 @@ def __contains__(self, item): # et al, link: https://www.rapidwright.io/docs/_downloads/6610b931d8a2e053e69a499d3923077f/FPT19-TimingModel.pdf self.pips = [ #intra-tile (zero wirelength) + # INT tiles (re.compile(r'LOGIC_OUTS_[LR]\d{1,2}'), 0), (re.compile(r'INT_NODE_SDQ_\d{1,2}_INT_OUT[01]'), 0), (re.compile(r'INT_NODE_IMUX_\d{1,2}_INT_OUT[01]'), 0), @@ -118,6 +119,13 @@ def __contains__(self, item): (re.compile(r'BOUNCE_[EW]_\d{1,2}_FT[01]'), 0), (re.compile(r'INODE_[EW]_\d{1,2}_FT[01]'), 0), (re.compile(r'SDQNODE_[EW]_\d{1,2}_FT[01]'), 0), + # LAG_LAG tiles + (re.compile(r'LAG_MUX_ATOM_\d{1,2}_TXOUT'), 0), + (re.compile(r'UBUMP\d{1,2}'), 0), # In multi-SLR devices, this wire is typically + # used to cross the SLR. Since the xcvu3p is + # a single SLR device, this wire can only be + # used as a 'U-turn' back into the same tile + (re.compile(r'RXD\d{1,2}'), 0), #single horizontal (re.compile(r'[EW]{2}1_[EW]_BEG[0-7]'), 1), From 3a7ee24e470b2392f91ff8bfc2f79a2b9b5e40c6 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Wed, 3 Jan 2024 15:47:59 -0800 Subject: [PATCH 2/4] Add LAG_LAG tile to whitelist Signed-off-by: Eddie Hung --- wirelength_analyzer/xcvup_device_data.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/wirelength_analyzer/xcvup_device_data.py b/wirelength_analyzer/xcvup_device_data.py index 7c33a91..c7508c0 100644 --- a/wirelength_analyzer/xcvup_device_data.py +++ b/wirelength_analyzer/xcvup_device_data.py @@ -163,7 +163,7 @@ def __contains__(self, item): self.tile_types = { 'CLEL_R', 'CLEM', 'CLEM_R', 'BRAM', 'DSP', 'XIPHY_BYTE_L', 'HPIO_L', 'CMT_L', 'URAM_URAM_FT', 'URAM_URAM_DELAY_FT', 'GTY_L', - 'GTY_R' + 'GTY_R', 'LAG_LAG' } # bels that drive global nets From 29d04a1d447da9970342014fbcba6cb04f2af7f7 Mon Sep 17 00:00:00 2001 From: eddieh-xlnx Date: Mon, 8 Jan 2024 14:14:12 -0800 Subject: [PATCH 3/4] [WirelengthAnalyzer] Add support for IBUFDS_GTE4 cells (#60) --- docs/score.md | 2 +- wirelength_analyzer/xcvup_device_data.py | 1 + 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/docs/score.md b/docs/score.md index 190c7b6..4614430 100644 --- a/docs/score.md +++ b/docs/score.md @@ -119,7 +119,7 @@ BEL input and output pins for each type of PhysCell. |`LUT1`, `LUT2`, `LUT3`, `LUT4`, `LUT5`, `LUT6` | (all) <- (all) | Look Up Table | |`CARRY8` | [see table CARRY8](#carry8-connectivity) | Fast Carry Logic | |`MUXF7`, `MUXF8`, `MUXF9` | (all) <- (all) | Intrasite Mux | -|`IBUFCTRL`, `INBUF`, `OBUFT`, `DIFFINBUF` | (all) <- (all) | I/O Buffer | +|`IBUFCTRL`, `INBUF`, `OBUFT`, `DIFFINBUF`, `IBUFDS_GTE4` | (all) <- (all) | I/O Buffer | |`DSP_A_B_DATA`, `DSP_C_DATA`, `DSP_M_DATA`,
`DSP_PREADD_DATA`, `DSP_OUTPUT`, `DSP_ALU` | (none) <- (none) [see note](#dsp-cell-connectivity) | DSP Logic | |`DSP_MULTIPLIER`, `DSP_PREADD` | (all) <- (all) [see note](#dsp-cell-connectivity) | DSP Logic | |`PCIE40E4` | (none) <- (none) | PCIe Hard Macro | diff --git a/wirelength_analyzer/xcvup_device_data.py b/wirelength_analyzer/xcvup_device_data.py index c7508c0..c5c826d 100644 --- a/wirelength_analyzer/xcvup_device_data.py +++ b/wirelength_analyzer/xcvup_device_data.py @@ -82,6 +82,7 @@ def __contains__(self, item): 'INBUF': self.all_to_all, 'OBUFT': self.all_to_all, 'DIFFINBUF': self.all_to_all, + 'IBUFDS_GTE4': self.all_to_all, # The following cell types are BELs that make up a DSP macro. # Such DSPs contains a number of optional pipelining registers, From f9be3f78ec1e43a247b0da76e786f247aa034b35 Mon Sep 17 00:00:00 2001 From: eddieh-xlnx Date: Mon, 8 Jan 2024 14:16:12 -0800 Subject: [PATCH 4/4] Revert "[WirelengthAnalyzer] Add support for IBUFDS_GTE4 cells (#60)" (#61) This reverts commit 29d04a1d447da9970342014fbcba6cb04f2af7f7. --- docs/score.md | 2 +- wirelength_analyzer/xcvup_device_data.py | 1 - 2 files changed, 1 insertion(+), 2 deletions(-) diff --git a/docs/score.md b/docs/score.md index 4614430..190c7b6 100644 --- a/docs/score.md +++ b/docs/score.md @@ -119,7 +119,7 @@ BEL input and output pins for each type of PhysCell. |`LUT1`, `LUT2`, `LUT3`, `LUT4`, `LUT5`, `LUT6` | (all) <- (all) | Look Up Table | |`CARRY8` | [see table CARRY8](#carry8-connectivity) | Fast Carry Logic | |`MUXF7`, `MUXF8`, `MUXF9` | (all) <- (all) | Intrasite Mux | -|`IBUFCTRL`, `INBUF`, `OBUFT`, `DIFFINBUF`, `IBUFDS_GTE4` | (all) <- (all) | I/O Buffer | +|`IBUFCTRL`, `INBUF`, `OBUFT`, `DIFFINBUF` | (all) <- (all) | I/O Buffer | |`DSP_A_B_DATA`, `DSP_C_DATA`, `DSP_M_DATA`,
`DSP_PREADD_DATA`, `DSP_OUTPUT`, `DSP_ALU` | (none) <- (none) [see note](#dsp-cell-connectivity) | DSP Logic | |`DSP_MULTIPLIER`, `DSP_PREADD` | (all) <- (all) [see note](#dsp-cell-connectivity) | DSP Logic | |`PCIE40E4` | (none) <- (none) | PCIe Hard Macro | diff --git a/wirelength_analyzer/xcvup_device_data.py b/wirelength_analyzer/xcvup_device_data.py index c5c826d..c7508c0 100644 --- a/wirelength_analyzer/xcvup_device_data.py +++ b/wirelength_analyzer/xcvup_device_data.py @@ -82,7 +82,6 @@ def __contains__(self, item): 'INBUF': self.all_to_all, 'OBUFT': self.all_to_all, 'DIFFINBUF': self.all_to_all, - 'IBUFDS_GTE4': self.all_to_all, # The following cell types are BELs that make up a DSP macro. # Such DSPs contains a number of optional pipelining registers,