From 07104695cb5761a792b45c18899a95feaa0c1ce4 Mon Sep 17 00:00:00 2001 From: eddieh-xlnx Date: Mon, 8 Jan 2024 14:15:57 -0800 Subject: [PATCH] Revert "[WirelengthAnalyzer] Add support for IBUFDS_GTE4 cells (#60)" This reverts commit 29d04a1d447da9970342014fbcba6cb04f2af7f7. --- docs/score.md | 2 +- wirelength_analyzer/xcvup_device_data.py | 1 - 2 files changed, 1 insertion(+), 2 deletions(-) diff --git a/docs/score.md b/docs/score.md index 4614430..190c7b6 100644 --- a/docs/score.md +++ b/docs/score.md @@ -119,7 +119,7 @@ BEL input and output pins for each type of PhysCell. |`LUT1`, `LUT2`, `LUT3`, `LUT4`, `LUT5`, `LUT6` | (all) <- (all) | Look Up Table | |`CARRY8` | [see table CARRY8](#carry8-connectivity) | Fast Carry Logic | |`MUXF7`, `MUXF8`, `MUXF9` | (all) <- (all) | Intrasite Mux | -|`IBUFCTRL`, `INBUF`, `OBUFT`, `DIFFINBUF`, `IBUFDS_GTE4` | (all) <- (all) | I/O Buffer | +|`IBUFCTRL`, `INBUF`, `OBUFT`, `DIFFINBUF` | (all) <- (all) | I/O Buffer | |`DSP_A_B_DATA`, `DSP_C_DATA`, `DSP_M_DATA`,
`DSP_PREADD_DATA`, `DSP_OUTPUT`, `DSP_ALU` | (none) <- (none) [see note](#dsp-cell-connectivity) | DSP Logic | |`DSP_MULTIPLIER`, `DSP_PREADD` | (all) <- (all) [see note](#dsp-cell-connectivity) | DSP Logic | |`PCIE40E4` | (none) <- (none) | PCIe Hard Macro | diff --git a/wirelength_analyzer/xcvup_device_data.py b/wirelength_analyzer/xcvup_device_data.py index c5c826d..c7508c0 100644 --- a/wirelength_analyzer/xcvup_device_data.py +++ b/wirelength_analyzer/xcvup_device_data.py @@ -82,7 +82,6 @@ def __contains__(self, item): 'INBUF': self.all_to_all, 'OBUFT': self.all_to_all, 'DIFFINBUF': self.all_to_all, - 'IBUFDS_GTE4': self.all_to_all, # The following cell types are BELs that make up a DSP macro. # Such DSPs contains a number of optional pipelining registers,