Permalink
This commit does not belong to any branch on this repository, and may belong to a fork outside of the repository.
Browse files
phy: zynqmp: Add phy driver for xilinx zynqmp phy core
ZynqMP SoC has a Gigabit Transceiver with four lanes. All the high speed peripherals such as USB, SATA, PCIE, Display Port and Ethernet SGMII can rely on any of the four GT lanes for PHY layer. This patch adds driver for that ZynqMP GT core. The DisplayPort requires programming of preemphasis / voltage swing value at runtime. These functions will be called from DisplayPort driver when required. The sata misc settings to use scrambler/descrambler and encoder/decoder functions. Because of functional issues in Silicon 1.0 (XCZU9EG) which doesn't do PMOS calibration properly, software needs to implement work around. As a software sequence of work around, need to programe any lane to a valid protocol. Currently serdes driver configures lane 0 (ICM_CFG0) to PCIe for fixing the above said calibration logic issue. Currently PCIe doesn't use serdes driver, instead it depends on fsbl for GT lane initialization. Since serdes driver is reintializing ICM_CFG0, PCIe is facing link down issues once linux boots. The patch fixes the above said issue by using ICM_CFG1 instead of ICM_CFG0 for fixing the PMOS calibration issue Signed-off-by: Anurag Kumar Vulisha <anurag.kumar.vulisha@xilinx.com> Signed-off-by: Hyun Kwon <hyun.kwon@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> Signed-off-by: Piyush Mehta <Piyush.Mehta@xilinx.com> Signed-off-by: Manish Narani <manish.narani@xilinx.com> Link: https://patchwork.kernel.org/cover/10735681/ https://patchwork.kernel.org/patch/10735683/ State: waiting (phy)
- Loading branch information