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+* Xilinx JESD204B Phy
+
+Description:
+The LogiCORE™ IP JESD204 PHY core implements a JESD204B Physical interface supporting
+line rates between 1.0 and 12.5 Gb/s on 1 to 12 lanes using GTX, GTH, or GTP transceivers.
+
+Required properties:
+- compatible = "xlnx,jesd204-phy-2.0"
+- reg = Should contain JESD204B phy registers location and length
+- xlnx,pll-selection = The PLL selection 3 for QPLL and 1 For CPLL
+- xlnx,lanes = No of Lanes
+- xlnx,gt-refclk-freq = Reference frequency in Hz
+- clocks = The phandle to the clock tree
+
+Example:
+++++++++
+	jesd204_phycores:phy@41e10000 {
+		compatible = "xlnx,jesd204-phy-2.0";
+		reg = <0x41e10000 0x10000>;
+		xlnx,gt-refclk-freq = "156250000";
+		xlnx,lanes = <0x1>;
+		xlnx,pll-selection = <0x3>;
+		clocks = <&si570>;
+	};