diff --git a/.github/workflows/release-tasks.yml b/.github/workflows/release-tasks.yml index ef1d57dc92c80..58a4e4f810cca 100644 --- a/.github/workflows/release-tasks.yml +++ b/.github/workflows/release-tasks.yml @@ -75,3 +75,36 @@ jobs: git config user.name "llvmbot" git commit -a -m "Add ${{ steps.validate-tag.outputs.release-version }} documentation" git push https://${{ secrets.WWW_RELEASES_TOKEN }}@github.com/${{ github.repository_owner }}/www-releases main:main + + release-lit: + runs-on: ubuntu-latest + if: github.repository == 'llvm/llvm-project' + steps: + - name: Checkout LLVM + uses: actions/checkout@v3 + + - name: Install dependencies + run: apt-get install -y python3-setuptools + + - name: Test lit + run: | + cd llvm/utils/lit + python3 lit.py tests + + - name: Package lit + run: | + cd llvm/utils/lit + # Remove 'dev' suffix from lit version. + sed -i "s/ + 'dev'//g" lit/__init__.py + python3 setup.py sdist + + - name: Upload lit to test.pypi.org + uses: pypa/gh-action-pypi-publish@release/v1 + with: + password: ${{ secrets.LLVM_LIT_TEST_PYPI_API_TOKEN }} + repository-url: https://test.pypi.org/legacy/ + + - name: Upload lit to pypi.org + uses: pypa/gh-action-pypi-publish@release/v1 + with: + password: ${{ secrets.LLVM_LIT_PYPI_API_TOKEN }} diff --git a/bolt/CMakeLists.txt b/bolt/CMakeLists.txt index a9bc770a95e93..2e702d40668b4 100644 --- a/bolt/CMakeLists.txt +++ b/bolt/CMakeLists.txt @@ -4,6 +4,9 @@ set(BOLT_SOURCE_DIR ${CMAKE_CURRENT_SOURCE_DIR}) set(BOLT_BINARY_DIR ${CMAKE_CURRENT_BINARY_DIR}) set(CMAKE_CXX_STANDARD 17) +# Add path for custom modules. +list(INSERT CMAKE_MODULE_PATH 0 "${BOLT_SOURCE_DIR}/cmake/modules") + # Determine default set of targets to build -- the intersection of # those BOLT supports and those LLVM is targeting. set(BOLT_TARGETS_TO_BUILD_all "AArch64;X86") @@ -111,6 +114,15 @@ endif() find_program(GNU_LD_EXECUTABLE NAMES ${LLVM_DEFAULT_TARGET_TRIPLE}-ld.bfd ld.bfd DOC "GNU ld") +include(AddBOLT) + +option(BOLT_BUILD_TOOLS + "Build the BOLT tools. If OFF, just generate build targets." ON) + +add_custom_target(bolt) +set_target_properties(bolt PROPERTIES FOLDER "BOLT") +add_llvm_install_targets(install-bolt DEPENDS bolt COMPONENT bolt) + include_directories( ${CMAKE_CURRENT_SOURCE_DIR}/include ${CMAKE_CURRENT_BINARY_DIR}/include diff --git a/bolt/cmake/modules/AddBOLT.cmake b/bolt/cmake/modules/AddBOLT.cmake new file mode 100644 index 0000000000000..1f69b9046320a --- /dev/null +++ b/bolt/cmake/modules/AddBOLT.cmake @@ -0,0 +1,36 @@ +include(GNUInstallDirs) +include(LLVMDistributionSupport) + +macro(add_bolt_executable name) + add_llvm_executable(${name} ${ARGN}) + set_target_properties(${name} PROPERTIES FOLDER "BOLT") +endmacro() + +macro(add_bolt_tool name) + if (NOT BOLT_BUILD_TOOLS) + set(EXCLUDE_FROM_ALL ON) + endif() + + add_bolt_executable(${name} ${ARGN}) + + if (BOLT_BUILD_TOOLS) + get_target_export_arg(${name} BOLT export_to_bolttargets) + install(TARGETS ${name} + ${export_to_bolttargets} + RUNTIME DESTINATION "${CMAKE_INSTALL_BINDIR}" + COMPONENT bolt) + + if(NOT LLVM_ENABLE_IDE) + add_llvm_install_targets(install-${name} + DEPENDS ${name} + COMPONENT bolt) + endif() + set_property(GLOBAL APPEND PROPERTY BOLT_EXPORTS ${name}) + endif() +endmacro() + +macro(add_bolt_tool_symlink name dest) + llvm_add_tool_symlink(BOLT ${name} ${dest} ALWAYS_GENERATE) + # Always generate install targets + llvm_install_symlink(BOLT ${name} ${dest} ALWAYS_GENERATE COMPONENT bolt) +endmacro() diff --git a/bolt/include/bolt/Profile/DataAggregator.h b/bolt/include/bolt/Profile/DataAggregator.h index 8b53666833125..cc237a6e642b8 100644 --- a/bolt/include/bolt/Profile/DataAggregator.h +++ b/bolt/include/bolt/Profile/DataAggregator.h @@ -199,10 +199,10 @@ class DataAggregator : public DataReader { /// execution order. /// /// Return true if the trace is valid, false otherwise. - bool recordTrace( - BinaryFunction &BF, const LBREntry &First, const LBREntry &Second, - uint64_t Count = 1, - SmallVector, 16> *Branches = nullptr) const; + bool + recordTrace(BinaryFunction &BF, const LBREntry &First, const LBREntry &Second, + uint64_t Count, + SmallVector, 16> &Branches) const; /// Return a vector of offsets corresponding to a trace in a function /// (see recordTrace() above). diff --git a/bolt/lib/Profile/DataAggregator.cpp b/bolt/lib/Profile/DataAggregator.cpp index 00ee56c31efb6..67bd2132b344c 100644 --- a/bolt/lib/Profile/DataAggregator.cpp +++ b/bolt/lib/Profile/DataAggregator.cpp @@ -838,11 +838,9 @@ bool DataAggregator::doTrace(const LBREntry &First, const LBREntry &Second, } bool DataAggregator::recordTrace( - BinaryFunction &BF, - const LBREntry &FirstLBR, - const LBREntry &SecondLBR, + BinaryFunction &BF, const LBREntry &FirstLBR, const LBREntry &SecondLBR, uint64_t Count, - SmallVector, 16> *Branches) const { + SmallVector, 16> &Branches) const { BinaryContext &BC = BF.getBinaryContext(); if (!BF.isSimple()) @@ -902,24 +900,27 @@ bool DataAggregator::recordTrace( return false; } - // Record fall-through jumps - BinaryBasicBlock::BinaryBranchInfo &BI = BB->getBranchInfo(*NextBB); - BI.Count += Count; - - if (Branches) { - const MCInst *Instr = BB->getLastNonPseudoInstr(); - uint64_t Offset = 0; - if (Instr) - Offset = BC.MIB->getOffsetWithDefault(*Instr, 0); - else - Offset = BB->getOffset(); + const MCInst *Instr = BB->getLastNonPseudoInstr(); + uint64_t Offset = 0; + if (Instr) + Offset = BC.MIB->getOffsetWithDefault(*Instr, 0); + else + Offset = BB->getOffset(); - Branches->emplace_back(Offset, NextBB->getOffset()); - } + Branches.emplace_back(Offset, NextBB->getOffset()); BB = NextBB; } + // Record fall-through jumps + for (const auto &[FromOffset, ToOffset] : Branches) { + BinaryBasicBlock *FromBB = BF.getBasicBlockContainingOffset(FromOffset); + BinaryBasicBlock *ToBB = BF.getBasicBlockAtOffset(ToOffset); + assert(FromBB && ToBB); + BinaryBasicBlock::BinaryBranchInfo &BI = FromBB->getBranchInfo(*ToBB); + BI.Count += Count; + } + return true; } @@ -930,7 +931,7 @@ DataAggregator::getFallthroughsInTrace(BinaryFunction &BF, uint64_t Count) const { SmallVector, 16> Res; - if (!recordTrace(BF, FirstLBR, SecondLBR, Count, &Res)) + if (!recordTrace(BF, FirstLBR, SecondLBR, Count, Res)) return std::nullopt; return Res; diff --git a/bolt/lib/Rewrite/BoltDiff.cpp b/bolt/lib/Rewrite/BoltDiff.cpp index 25b2fad25b3e7..69ba63a9e83a4 100644 --- a/bolt/lib/Rewrite/BoltDiff.cpp +++ b/bolt/lib/Rewrite/BoltDiff.cpp @@ -83,6 +83,11 @@ static cl::opt NormalizeByBin1( "collection time and sampling rate for this to make sense"), cl::cat(BoltDiffCategory)); +static cl::opt + SkipNonSimple("skip-non-simple", + cl::desc("skip non-simple functions in reporting"), + cl::ReallyHidden, cl::cat(BoltDiffCategory)); + } // end namespace opts namespace llvm { @@ -428,8 +433,10 @@ class RewriteInstanceDiff { llvm::make_second_range(llvm::reverse(LargestDiffs))) { const double Score2 = getNormalizedScore(*BB2, RI2); const double Score1 = getNormalizedScore(*BBMap[BB2], RI1); - outs() << "BB " << BB2->getName() << " from " - << BBToFuncMap[BB2]->getDemangledName() + const BinaryFunction *Func = BBToFuncMap[BB2]; + if (opts::SkipNonSimple && !Func->isSimple()) + continue; + outs() << "BB " << BB2->getName() << " from " << Func->getDemangledName() << "\n\tScore bin1 = " << format("%.4f", Score1 * 100.0) << "%\n\tScore bin2 = " << format("%.4f", Score2 * 100.0); outs() << "%\t(Difference: "; @@ -460,9 +467,12 @@ class RewriteInstanceDiff { EdgeTy &Edge1 = EI.second; const double Score2 = std::get<2>(Edge2); const double Score1 = std::get<2>(Edge1); + const BinaryFunction *Func = BBToFuncMap[std::get<0>(Edge2)]; + if (opts::SkipNonSimple && !Func->isSimple()) + continue; outs() << "Edge (" << std::get<0>(Edge2)->getName() << " -> " << std::get<1>(Edge2)->getName() << ") in " - << BBToFuncMap[std::get<0>(Edge2)]->getDemangledName() + << Func->getDemangledName() << "\n\tScore bin1 = " << format("%.4f", Score1 * 100.0) << "%\n\tScore bin2 = " << format("%.4f", Score2 * 100.0); outs() << "%\t(Difference: "; @@ -537,6 +547,8 @@ class RewriteInstanceDiff { Score2 = LTOAggregatedScore2[Iter2->second]; if (Score1 == 0.0 || Score2 == 0.0) continue; + if (opts::SkipNonSimple && !Func1->isSimple() && !Func2->isSimple()) + continue; LargestDiffs.insert( std::make_pair<>(std::abs(Score1 - Score2), MapEntry)); ScoreMap[Func2] = std::make_pair<>(Score1, Score2); diff --git a/bolt/lib/Rewrite/DWARFRewriter.cpp b/bolt/lib/Rewrite/DWARFRewriter.cpp index 749d907627315..6134b1c881ab9 100644 --- a/bolt/lib/Rewrite/DWARFRewriter.cpp +++ b/bolt/lib/Rewrite/DWARFRewriter.cpp @@ -407,6 +407,13 @@ void DWARFRewriter::updateUnitDebugInfo( DWARFAddressRangesVector &ModuleRanges = *ModuleRangesOrError; DebugAddressRangesVector OutputRanges = BC.translateModuleAddressRanges(ModuleRanges); + std::optional LowPCAttrInfo = + findAttributeInfo(DIE, dwarf::DW_AT_low_pc); + // For a case where LLD GCs only function used in the CU. + // If CU doesn't have DW_AT_low_pc we are not going to convert, + // so don't need to do anything. + if (OutputRanges.empty() && !Unit.isDWOUnit() && LowPCAttrInfo) + OutputRanges.push_back({0, 0}); const uint64_t RangesSectionOffset = RangesSectionWriter.addRanges(OutputRanges); if (!Unit.isDWOUnit()) diff --git a/bolt/test/CMakeLists.txt b/bolt/test/CMakeLists.txt index 216a785b7d69f..89862fd59eb8e 100644 --- a/bolt/test/CMakeLists.txt +++ b/bolt/test/CMakeLists.txt @@ -37,7 +37,6 @@ list(APPEND BOLT_TEST_DEPS lld llvm-config llvm-bolt - llvm-boltdiff llvm-bolt-heatmap llvm-bat-dump llvm-dwarfdump @@ -52,7 +51,6 @@ list(APPEND BOLT_TEST_DEPS llvm-objcopy merge-fdata not - perf2bolt split-file yaml2obj ) diff --git a/bolt/test/X86/Inputs/dwarf5-df-cu-function-gc-helper.s b/bolt/test/X86/Inputs/dwarf5-df-cu-function-gc-helper.s new file mode 100644 index 0000000000000..66d76cbb980db --- /dev/null +++ b/bolt/test/X86/Inputs/dwarf5-df-cu-function-gc-helper.s @@ -0,0 +1,227 @@ +# int helper() { +# return 1; +# } + + .text + .file "helper.cpp" + .section .text._Z6helperv,"ax",@progbits + .globl _Z6helperv # -- Begin function _Z6helperv + .p2align 4, 0x90 + .type _Z6helperv,@function +_Z6helperv: # @_Z6helperv +.Lfunc_begin0: + .file 0 "." "helper.cpp" md5 0xf0d02b43e83785dc27fc4814c9d9262b + .loc 0 1 0 # helper.cpp:1:0 + .cfi_startproc +# %bb.0: # %entry + pushq %rbp + .cfi_def_cfa_offset 16 + .cfi_offset %rbp, -16 + movq %rsp, %rbp + .cfi_def_cfa_register %rbp +.Ltmp0: + .loc 0 2 1 prologue_end # helper.cpp:2:1 + movl $1, %eax + .loc 0 2 1 epilogue_begin is_stmt 0 # helper.cpp:2:1 + popq %rbp + .cfi_def_cfa %rsp, 8 + retq +.Ltmp1: +.Lfunc_end0: + .size _Z6helperv, .Lfunc_end0-_Z6helperv + .cfi_endproc + # -- End function + .section .debug_abbrev,"",@progbits + .byte 1 # Abbreviation Code + .byte 74 # DW_TAG_skeleton_unit + .byte 0 # DW_CHILDREN_no + .byte 16 # DW_AT_stmt_list + .byte 23 # DW_FORM_sec_offset + .byte 114 # DW_AT_str_offsets_base + .byte 23 # DW_FORM_sec_offset + .byte 27 # DW_AT_comp_dir + .byte 37 # DW_FORM_strx1 + .ascii "\264B" # DW_AT_GNU_pubnames + .byte 25 # DW_FORM_flag_present + .byte 118 # DW_AT_dwo_name + .byte 37 # DW_FORM_strx1 + .byte 17 # DW_AT_low_pc + .byte 27 # DW_FORM_addrx + .byte 18 # DW_AT_high_pc + .byte 6 # DW_FORM_data4 + .byte 115 # DW_AT_addr_base + .byte 23 # DW_FORM_sec_offset + .byte 0 # EOM(1) + .byte 0 # EOM(2) + .byte 0 # EOM(3) + .section .debug_info,"",@progbits +.Lcu_begin0: + .long .Ldebug_info_end0-.Ldebug_info_start0 # Length of Unit +.Ldebug_info_start0: + .short 5 # DWARF version number + .byte 4 # DWARF Unit Type + .byte 8 # Address Size (in bytes) + .long .debug_abbrev # Offset Into Abbrev. Section + .quad -1286039323196723149 + .byte 1 # Abbrev [1] 0x14:0x14 DW_TAG_skeleton_unit + .long .Lline_table_start0 # DW_AT_stmt_list + .long .Lstr_offsets_base0 # DW_AT_str_offsets_base + .byte 0 # DW_AT_comp_dir + # DW_AT_GNU_pubnames + .byte 1 # DW_AT_dwo_name + .byte 0 # DW_AT_low_pc + .long .Lfunc_end0-.Lfunc_begin0 # DW_AT_high_pc + .long .Laddr_table_base0 # DW_AT_addr_base +.Ldebug_info_end0: + .section .debug_str_offsets,"",@progbits + .long 12 # Length of String Offsets Set + .short 5 + .short 0 +.Lstr_offsets_base0: + .section .debug_str,"MS",@progbits,1 +.Lskel_string0: + .asciz "." # string offset=0 +.Lskel_string1: + .asciz "helper.dwo" # string offset=50 + .section .debug_str_offsets,"",@progbits + .long .Lskel_string0 + .long .Lskel_string1 + .section .debug_str_offsets.dwo,"e",@progbits + .long 28 # Length of String Offsets Set + .short 5 + .short 0 + .section .debug_str.dwo,"eMS",@progbits,1 +.Linfo_string0: + .asciz "_Z6helperv" # string offset=0 +.Linfo_string1: + .asciz "helper" # string offset=11 +.Linfo_string2: + .asciz "int" # string offset=18 +.Linfo_string3: + .asciz "clang version 17.0.0 (https://github.com/llvm/llvm-project.git 640e07c49037cca41a1bfbeb916b569d8c950aea)" # string offset=22 +.Linfo_string4: + .asciz "helper.cpp" # string offset=127 +.Linfo_string5: + .asciz "helper.dwo" # string offset=138 + .section .debug_str_offsets.dwo,"e",@progbits + .long 0 + .long 11 + .long 18 + .long 22 + .long 127 + .long 138 + .section .debug_info.dwo,"e",@progbits + .long .Ldebug_info_dwo_end0-.Ldebug_info_dwo_start0 # Length of Unit +.Ldebug_info_dwo_start0: + .short 5 # DWARF version number + .byte 5 # DWARF Unit Type + .byte 8 # Address Size (in bytes) + .long 0 # Offset Into Abbrev. Section + .quad -1286039323196723149 + .byte 1 # Abbrev [1] 0x14:0x1b DW_TAG_compile_unit + .byte 3 # DW_AT_producer + .short 33 # DW_AT_language + .byte 4 # DW_AT_name + .byte 5 # DW_AT_dwo_name + .byte 2 # Abbrev [2] 0x1a:0x10 DW_TAG_subprogram + .byte 0 # DW_AT_low_pc + .long .Lfunc_end0-.Lfunc_begin0 # DW_AT_high_pc + .byte 1 # DW_AT_frame_base + .byte 86 + .byte 0 # DW_AT_linkage_name + .byte 1 # DW_AT_name + .byte 0 # DW_AT_decl_file + .byte 1 # DW_AT_decl_line + .long 42 # DW_AT_type + # DW_AT_external + .byte 3 # Abbrev [3] 0x2a:0x4 DW_TAG_base_type + .byte 2 # DW_AT_name + .byte 5 # DW_AT_encoding + .byte 4 # DW_AT_byte_size + .byte 0 # End Of Children Mark +.Ldebug_info_dwo_end0: + .section .debug_abbrev.dwo,"e",@progbits + .byte 1 # Abbreviation Code + .byte 17 # DW_TAG_compile_unit + .byte 1 # DW_CHILDREN_yes + .byte 37 # DW_AT_producer + .byte 37 # DW_FORM_strx1 + .byte 19 # DW_AT_language + .byte 5 # DW_FORM_data2 + .byte 3 # DW_AT_name + .byte 37 # DW_FORM_strx1 + .byte 118 # DW_AT_dwo_name + .byte 37 # DW_FORM_strx1 + .byte 0 # EOM(1) + .byte 0 # EOM(2) + .byte 2 # Abbreviation Code + .byte 46 # DW_TAG_subprogram + .byte 0 # DW_CHILDREN_no + .byte 17 # DW_AT_low_pc + .byte 27 # DW_FORM_addrx + .byte 18 # DW_AT_high_pc + .byte 6 # DW_FORM_data4 + .byte 64 # DW_AT_frame_base + .byte 24 # DW_FORM_exprloc + .byte 110 # DW_AT_linkage_name + .byte 37 # DW_FORM_strx1 + .byte 3 # DW_AT_name + .byte 37 # DW_FORM_strx1 + .byte 58 # DW_AT_decl_file + .byte 11 # DW_FORM_data1 + .byte 59 # DW_AT_decl_line + .byte 11 # DW_FORM_data1 + .byte 73 # DW_AT_type + .byte 19 # DW_FORM_ref4 + .byte 63 # DW_AT_external + .byte 25 # DW_FORM_flag_present + .byte 0 # EOM(1) + .byte 0 # EOM(2) + .byte 3 # Abbreviation Code + .byte 36 # DW_TAG_base_type + .byte 0 # DW_CHILDREN_no + .byte 3 # DW_AT_name + .byte 37 # DW_FORM_strx1 + .byte 62 # DW_AT_encoding + .byte 11 # DW_FORM_data1 + .byte 11 # DW_AT_byte_size + .byte 11 # DW_FORM_data1 + .byte 0 # EOM(1) + .byte 0 # EOM(2) + .byte 0 # EOM(3) + .section .debug_addr,"",@progbits + .long .Ldebug_addr_end0-.Ldebug_addr_start0 # Length of contribution +.Ldebug_addr_start0: + .short 5 # DWARF version number + .byte 8 # Address size + .byte 0 # Segment selector size +.Laddr_table_base0: + .quad .Lfunc_begin0 +.Ldebug_addr_end0: + .section .debug_gnu_pubnames,"",@progbits + .long .LpubNames_end0-.LpubNames_start0 # Length of Public Names Info +.LpubNames_start0: + .short 2 # DWARF Version + .long .Lcu_begin0 # Offset of Compilation Unit Info + .long 40 # Compilation Unit Length + .long 26 # DIE offset + .byte 48 # Attributes: FUNCTION, EXTERNAL + .asciz "helper" # External Name + .long 0 # End Mark +.LpubNames_end0: + .section .debug_gnu_pubtypes,"",@progbits + .long .LpubTypes_end0-.LpubTypes_start0 # Length of Public Types Info +.LpubTypes_start0: + .short 2 # DWARF Version + .long .Lcu_begin0 # Offset of Compilation Unit Info + .long 40 # Compilation Unit Length + .long 42 # DIE offset + .byte 144 # Attributes: TYPE, STATIC + .asciz "int" # External Name + .long 0 # End Mark +.LpubTypes_end0: + .ident "clang version 17.0.0 (https://github.com/llvm/llvm-project.git 640e07c49037cca41a1bfbeb916b569d8c950aea)" + .section ".note.GNU-stack","",@progbits + .addrsig + .section .debug_line,"",@progbits +.Lline_table_start0: diff --git a/bolt/test/X86/Inputs/dwarf5-df-cu-function-gc-main.s b/bolt/test/X86/Inputs/dwarf5-df-cu-function-gc-main.s new file mode 100644 index 0000000000000..a7d12b921ea3d --- /dev/null +++ b/bolt/test/X86/Inputs/dwarf5-df-cu-function-gc-main.s @@ -0,0 +1,222 @@ +# int main() { +# return 0; +# } + + .text + .file "main.cpp" + .section .text.main,"ax",@progbits + .globl main # -- Begin function main + .p2align 4, 0x90 + .type main,@function +main: # @main +.Lfunc_begin0: + .file 0 "." "main.cpp" md5 0xbb12fec8d002b1f0e06f7dee4604c6cc + .loc 0 1 0 # main.cpp:1:0 + .cfi_startproc +# %bb.0: # %entry + pushq %rbp + .cfi_def_cfa_offset 16 + .cfi_offset %rbp, -16 + movq %rsp, %rbp + .cfi_def_cfa_register %rbp + movl $0, -4(%rbp) +.Ltmp0: + .loc 0 2 3 prologue_end # main.cpp:2:3 + xorl %eax, %eax + .loc 0 2 3 epilogue_begin is_stmt 0 # main.cpp:2:3 + popq %rbp + .cfi_def_cfa %rsp, 8 + retq +.Ltmp1: +.Lfunc_end0: + .size main, .Lfunc_end0-main + .cfi_endproc + # -- End function + .section .debug_abbrev,"",@progbits + .byte 1 # Abbreviation Code + .byte 74 # DW_TAG_skeleton_unit + .byte 0 # DW_CHILDREN_no + .byte 16 # DW_AT_stmt_list + .byte 23 # DW_FORM_sec_offset + .byte 114 # DW_AT_str_offsets_base + .byte 23 # DW_FORM_sec_offset + .byte 27 # DW_AT_comp_dir + .byte 37 # DW_FORM_strx1 + .ascii "\264B" # DW_AT_GNU_pubnames + .byte 25 # DW_FORM_flag_present + .byte 118 # DW_AT_dwo_name + .byte 37 # DW_FORM_strx1 + .byte 17 # DW_AT_low_pc + .byte 27 # DW_FORM_addrx + .byte 18 # DW_AT_high_pc + .byte 6 # DW_FORM_data4 + .byte 115 # DW_AT_addr_base + .byte 23 # DW_FORM_sec_offset + .byte 0 # EOM(1) + .byte 0 # EOM(2) + .byte 0 # EOM(3) + .section .debug_info,"",@progbits +.Lcu_begin0: + .long .Ldebug_info_end0-.Ldebug_info_start0 # Length of Unit +.Ldebug_info_start0: + .short 5 # DWARF version number + .byte 4 # DWARF Unit Type + .byte 8 # Address Size (in bytes) + .long .debug_abbrev # Offset Into Abbrev. Section + .quad 6318074710904753300 + .byte 1 # Abbrev [1] 0x14:0x14 DW_TAG_skeleton_unit + .long .Lline_table_start0 # DW_AT_stmt_list + .long .Lstr_offsets_base0 # DW_AT_str_offsets_base + .byte 0 # DW_AT_comp_dir + # DW_AT_GNU_pubnames + .byte 1 # DW_AT_dwo_name + .byte 0 # DW_AT_low_pc + .long .Lfunc_end0-.Lfunc_begin0 # DW_AT_high_pc + .long .Laddr_table_base0 # DW_AT_addr_base +.Ldebug_info_end0: + .section .debug_str_offsets,"",@progbits + .long 12 # Length of String Offsets Set + .short 5 + .short 0 +.Lstr_offsets_base0: + .section .debug_str,"MS",@progbits,1 +.Lskel_string0: + .asciz "." # string offset=0 +.Lskel_string1: + .asciz "main.dwo" # string offset=50 + .section .debug_str_offsets,"",@progbits + .long .Lskel_string0 + .long .Lskel_string1 + .section .debug_str_offsets.dwo,"e",@progbits + .long 24 # Length of String Offsets Set + .short 5 + .short 0 + .section .debug_str.dwo,"eMS",@progbits,1 +.Linfo_string0: + .asciz "main" # string offset=0 +.Linfo_string1: + .asciz "int" # string offset=5 +.Linfo_string2: + .asciz "clang version 17.0.0 (https://github.com/llvm/llvm-project.git 640e07c49037cca41a1bfbeb916b569d8c950aea)" # string offset=9 +.Linfo_string3: + .asciz "main.cpp" # string offset=114 +.Linfo_string4: + .asciz "main.dwo" # string offset=123 + .section .debug_str_offsets.dwo,"e",@progbits + .long 0 + .long 5 + .long 9 + .long 114 + .long 123 + .section .debug_info.dwo,"e",@progbits + .long .Ldebug_info_dwo_end0-.Ldebug_info_dwo_start0 # Length of Unit +.Ldebug_info_dwo_start0: + .short 5 # DWARF version number + .byte 5 # DWARF Unit Type + .byte 8 # Address Size (in bytes) + .long 0 # Offset Into Abbrev. Section + .quad 6318074710904753300 + .byte 1 # Abbrev [1] 0x14:0x1a DW_TAG_compile_unit + .byte 2 # DW_AT_producer + .short 33 # DW_AT_language + .byte 3 # DW_AT_name + .byte 4 # DW_AT_dwo_name + .byte 2 # Abbrev [2] 0x1a:0xf DW_TAG_subprogram + .byte 0 # DW_AT_low_pc + .long .Lfunc_end0-.Lfunc_begin0 # DW_AT_high_pc + .byte 1 # DW_AT_frame_base + .byte 86 + .byte 0 # DW_AT_name + .byte 0 # DW_AT_decl_file + .byte 1 # DW_AT_decl_line + .long 41 # DW_AT_type + # DW_AT_external + .byte 3 # Abbrev [3] 0x29:0x4 DW_TAG_base_type + .byte 1 # DW_AT_name + .byte 5 # DW_AT_encoding + .byte 4 # DW_AT_byte_size + .byte 0 # End Of Children Mark +.Ldebug_info_dwo_end0: + .section .debug_abbrev.dwo,"e",@progbits + .byte 1 # Abbreviation Code + .byte 17 # DW_TAG_compile_unit + .byte 1 # DW_CHILDREN_yes + .byte 37 # DW_AT_producer + .byte 37 # DW_FORM_strx1 + .byte 19 # DW_AT_language + .byte 5 # DW_FORM_data2 + .byte 3 # DW_AT_name + .byte 37 # DW_FORM_strx1 + .byte 118 # DW_AT_dwo_name + .byte 37 # DW_FORM_strx1 + .byte 0 # EOM(1) + .byte 0 # EOM(2) + .byte 2 # Abbreviation Code + .byte 46 # DW_TAG_subprogram + .byte 0 # DW_CHILDREN_no + .byte 17 # DW_AT_low_pc + .byte 27 # DW_FORM_addrx + .byte 18 # DW_AT_high_pc + .byte 6 # DW_FORM_data4 + .byte 64 # DW_AT_frame_base + .byte 24 # DW_FORM_exprloc + .byte 3 # DW_AT_name + .byte 37 # DW_FORM_strx1 + .byte 58 # DW_AT_decl_file + .byte 11 # DW_FORM_data1 + .byte 59 # DW_AT_decl_line + .byte 11 # DW_FORM_data1 + .byte 73 # DW_AT_type + .byte 19 # DW_FORM_ref4 + .byte 63 # DW_AT_external + .byte 25 # DW_FORM_flag_present + .byte 0 # EOM(1) + .byte 0 # EOM(2) + .byte 3 # Abbreviation Code + .byte 36 # DW_TAG_base_type + .byte 0 # DW_CHILDREN_no + .byte 3 # DW_AT_name + .byte 37 # DW_FORM_strx1 + .byte 62 # DW_AT_encoding + .byte 11 # DW_FORM_data1 + .byte 11 # DW_AT_byte_size + .byte 11 # DW_FORM_data1 + .byte 0 # EOM(1) + .byte 0 # EOM(2) + .byte 0 # EOM(3) + .section .debug_addr,"",@progbits + .long .Ldebug_addr_end0-.Ldebug_addr_start0 # Length of contribution +.Ldebug_addr_start0: + .short 5 # DWARF version number + .byte 8 # Address size + .byte 0 # Segment selector size +.Laddr_table_base0: + .quad .Lfunc_begin0 +.Ldebug_addr_end0: + .section .debug_gnu_pubnames,"",@progbits + .long .LpubNames_end0-.LpubNames_start0 # Length of Public Names Info +.LpubNames_start0: + .short 2 # DWARF Version + .long .Lcu_begin0 # Offset of Compilation Unit Info + .long 40 # Compilation Unit Length + .long 26 # DIE offset + .byte 48 # Attributes: FUNCTION, EXTERNAL + .asciz "main" # External Name + .long 0 # End Mark +.LpubNames_end0: + .section .debug_gnu_pubtypes,"",@progbits + .long .LpubTypes_end0-.LpubTypes_start0 # Length of Public Types Info +.LpubTypes_start0: + .short 2 # DWARF Version + .long .Lcu_begin0 # Offset of Compilation Unit Info + .long 40 # Compilation Unit Length + .long 41 # DIE offset + .byte 144 # Attributes: TYPE, STATIC + .asciz "int" # External Name + .long 0 # End Mark +.LpubTypes_end0: + .ident "clang version 17.0.0 (https://github.com/llvm/llvm-project.git 640e07c49037cca41a1bfbeb916b569d8c950aea)" + .section ".note.GNU-stack","",@progbits + .addrsig + .section .debug_line,"",@progbits +.Lline_table_start0: diff --git a/bolt/test/X86/dwarf5-df-cu-function-gc.test b/bolt/test/X86/dwarf5-df-cu-function-gc.test new file mode 100644 index 0000000000000..62f75c2c75532 --- /dev/null +++ b/bolt/test/X86/dwarf5-df-cu-function-gc.test @@ -0,0 +1,27 @@ +# REQUIRES: system-linux +; RUN: rm -rf %t +; RUN: mkdir %t +; RUN: cd %t +; RUN: llvm-mc --split-dwarf-file=main.dwo --triple=x86_64-unknown-linux-gnu \ +; RUN: --filetype=obj %p/Inputs/dwarf5-df-cu-function-gc-main.s -o=main.o +; RUN: llvm-mc --split-dwarf-file=helper.dwo --triple=x86_64-unknown-linux-gnu \ +; RUN: --filetype=obj %p/Inputs/dwarf5-df-cu-function-gc-helper.s -o=helper.o +; RUN: %clang %cflags -gdwarf-5 -gsplit-dwarf=split -Wl,--entry=main -Wl,--gc-sections main.o helper.o -o main.exe +; RUN: llvm-bolt main.exe -o main.exe.bolt --update-debug-sections +; RUN: llvm-dwarfdump --debug-addr main.exe.bolt > addr.txt +; RUN: llvm-dwarfdump --show-form --verbose --debug-info main.exe.bolt >> addr.txt +; RUN: cat addr.txt | FileCheck -check-prefix=BOLT %s + +; Tests we generate range when linker GCs only function used in CU + +; BOLT: Addrs: +; BOLT-NEXT: 0x[[#%.16x,ADDR:]] +; BOLT: Addrs: +; BOLT-NEXT: 0x[[#%.16x,ADDR1:]] + +; BOLT: DW_TAG_skeleton_unit +; BOLT: DW_AT_ranges [DW_FORM_rnglistx] (indexed (0x0) rangelist = 0x00000010 +; BOLT-NEXT: [0x[[#ADDR]], 0x[[#ADDR + 0xf]])) +; BOLT: DW_TAG_skeleton_unit +; BOLT: DW_AT_ranges [DW_FORM_rnglistx] (indexed (0x0) rangelist = 0x00000024 +; BOLT-NEXT: [0x[[#ADDR1]], 0x[[#ADDR1]])) diff --git a/bolt/tools/CMakeLists.txt b/bolt/tools/CMakeLists.txt index 52050fb8b0056..22ea3b9bd805f 100644 --- a/bolt/tools/CMakeLists.txt +++ b/bolt/tools/CMakeLists.txt @@ -2,16 +2,6 @@ set(BOLT_TOOLS_INSTALL_DIR "${CMAKE_INSTALL_BINDIR}" CACHE PATH "Path for binary subdirectory (defaults to '${CMAKE_INSTALL_BINDIR}')") mark_as_advanced(BOLT_TOOLS_INSTALL_DIR) -# Move these macros to AddBolt if such a CMake module is ever created. - -macro(add_bolt_tool name) - llvm_add_tool(BOLT ${ARGV}) -endmacro() - -macro(add_bolt_tool_symlink name) - llvm_add_tool_symlink(BOLT ${ARGV}) -endmacro() - add_subdirectory(driver) add_subdirectory(llvm-bolt-fuzzer) add_subdirectory(bat-dump) diff --git a/bolt/tools/bat-dump/CMakeLists.txt b/bolt/tools/bat-dump/CMakeLists.txt index 71d4f3e64ccda..037b7d2662ae4 100644 --- a/bolt/tools/bat-dump/CMakeLists.txt +++ b/bolt/tools/bat-dump/CMakeLists.txt @@ -3,7 +3,7 @@ set(LLVM_LINK_COMPONENTS Support ) -add_llvm_tool(llvm-bat-dump +add_bolt_executable(llvm-bat-dump bat-dump.cpp DISABLE_LLVM_LINK_LLVM_DYLIB @@ -13,5 +13,3 @@ target_link_libraries(llvm-bat-dump PRIVATE LLVMBOLTProfile ) - -set_target_properties(llvm-bat-dump PROPERTIES FOLDER "BOLT") diff --git a/bolt/tools/driver/CMakeLists.txt b/bolt/tools/driver/CMakeLists.txt index 1c596194ffe80..9bf9ff85edc7b 100644 --- a/bolt/tools/driver/CMakeLists.txt +++ b/bolt/tools/driver/CMakeLists.txt @@ -30,22 +30,6 @@ target_link_libraries(llvm-bolt add_bolt_tool_symlink(perf2bolt llvm-bolt) add_bolt_tool_symlink(llvm-boltdiff llvm-bolt) -set(BOLT_DEPENDS - llvm-bolt - perf2bolt - llvm-boltdiff - ) - -add_custom_target(bolt DEPENDS ${BOLT_DEPENDS}) -install(PROGRAMS - ${CMAKE_BINARY_DIR}/bin/llvm-bolt - ${CMAKE_BINARY_DIR}/bin/perf2bolt - ${CMAKE_BINARY_DIR}/bin/llvm-boltdiff - DESTINATION ${CMAKE_INSTALL_BINDIR} - COMPONENT bolt - ) -add_llvm_install_targets(install-bolt DEPENDS bolt COMPONENT bolt) -set_target_properties(bolt PROPERTIES FOLDER "BOLT") -set_target_properties(install-bolt PROPERTIES FOLDER "BOLT") +add_dependencies(bolt llvm-bolt) -include_directories( ${BOLT_SOURCE_DIR}/lib ) +include_directories(${BOLT_SOURCE_DIR}/lib) diff --git a/bolt/tools/heatmap/CMakeLists.txt b/bolt/tools/heatmap/CMakeLists.txt index 9f52ddb02102e..acddc7a50e8b1 100644 --- a/bolt/tools/heatmap/CMakeLists.txt +++ b/bolt/tools/heatmap/CMakeLists.txt @@ -17,4 +17,4 @@ target_link_libraries(llvm-bolt-heatmap LLVMBOLTUtils ) -set_target_properties(llvm-bolt-heatmap PROPERTIES FOLDER "BOLT") +add_dependencies(bolt llvm-bolt-heatmap) diff --git a/bolt/tools/merge-fdata/CMakeLists.txt b/bolt/tools/merge-fdata/CMakeLists.txt index 9405acb6ab68d..f6a87a2268982 100644 --- a/bolt/tools/merge-fdata/CMakeLists.txt +++ b/bolt/tools/merge-fdata/CMakeLists.txt @@ -8,14 +8,8 @@ add_bolt_tool(merge-fdata DEPENDS intrinsics_gen ) -set_target_properties(merge-fdata PROPERTIES FOLDER "BOLT") add_dependencies(bolt merge-fdata) -install(PROGRAMS - ${CMAKE_BINARY_DIR}/bin/merge-fdata - DESTINATION ${CMAKE_INSTALL_BINDIR} - COMPONENT bolt - ) # Emit relocations for BOLT meta test (bolt/test/runtime/meta-merge-fdata.test) if (BOLT_INCLUDE_TESTS AND UNIX AND NOT APPLE) diff --git a/clang-tools-extra/clang-tidy/bugprone/BugproneTidyModule.cpp b/clang-tools-extra/clang-tidy/bugprone/BugproneTidyModule.cpp index 5e9c7d0add4f8..e62e536555c29 100644 --- a/clang-tools-extra/clang-tidy/bugprone/BugproneTidyModule.cpp +++ b/clang-tools-extra/clang-tidy/bugprone/BugproneTidyModule.cpp @@ -73,6 +73,7 @@ #include "UndelegatedConstructorCheck.h" #include "UnhandledExceptionAtNewCheck.h" #include "UnhandledSelfAssignmentCheck.h" +#include "UniquePtrArrayMismatchCheck.h" #include "UnsafeFunctionsCheck.h" #include "UnusedRaiiCheck.h" #include "UnusedReturnValueCheck.h" @@ -207,6 +208,8 @@ class BugproneModule : public ClangTidyModule { "bugprone-unhandled-self-assignment"); CheckFactories.registerCheck( "bugprone-unhandled-exception-at-new"); + CheckFactories.registerCheck( + "bugprone-unique-ptr-array-mismatch"); CheckFactories.registerCheck( "bugprone-unsafe-functions"); CheckFactories.registerCheck("bugprone-unused-raii"); diff --git a/clang-tools-extra/clang-tidy/bugprone/CMakeLists.txt b/clang-tools-extra/clang-tidy/bugprone/CMakeLists.txt index e70d1b426a1c6..363d1a85b0ae5 100644 --- a/clang-tools-extra/clang-tidy/bugprone/CMakeLists.txt +++ b/clang-tools-extra/clang-tidy/bugprone/CMakeLists.txt @@ -69,6 +69,7 @@ add_clang_library(clangTidyBugproneModule UndelegatedConstructorCheck.cpp UnhandledExceptionAtNewCheck.cpp UnhandledSelfAssignmentCheck.cpp + UniquePtrArrayMismatchCheck.cpp UnsafeFunctionsCheck.cpp UnusedRaiiCheck.cpp UnusedReturnValueCheck.cpp diff --git a/clang-tools-extra/clang-tidy/bugprone/UniquePtrArrayMismatchCheck.cpp b/clang-tools-extra/clang-tidy/bugprone/UniquePtrArrayMismatchCheck.cpp new file mode 100644 index 0000000000000..8d09b4b320c2c --- /dev/null +++ b/clang-tools-extra/clang-tidy/bugprone/UniquePtrArrayMismatchCheck.cpp @@ -0,0 +1,33 @@ +//===--- UniquePtrArrayMismatchCheck.cpp - clang-tidy ---------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#include "UniquePtrArrayMismatchCheck.h" + +using namespace clang::ast_matchers; + +namespace clang::tidy::bugprone { + +UniquePtrArrayMismatchCheck::UniquePtrArrayMismatchCheck( + StringRef Name, ClangTidyContext *Context) + : SmartPtrArrayMismatchCheck(Name, Context, "unique") {} + +UniquePtrArrayMismatchCheck::SmartPtrClassMatcher +UniquePtrArrayMismatchCheck::getSmartPointerClassMatcher() const { + auto DeleterDecl = classTemplateSpecializationDecl( + hasName("::std::default_delete"), templateArgumentCountIs(1), + hasTemplateArgument(0, templateArgument(refersToType( + qualType(equalsBoundNode(PointerTypeN)))))); + return classTemplateSpecializationDecl( + hasName("::std::unique_ptr"), templateArgumentCountIs(2), + hasTemplateArgument( + 0, templateArgument(refersToType(qualType().bind(PointerTypeN)))), + hasTemplateArgument(1, templateArgument(refersToType( + qualType(hasDeclaration(DeleterDecl)))))); +} + +} // namespace clang::tidy::bugprone diff --git a/clang-tools-extra/clang-tidy/bugprone/UniquePtrArrayMismatchCheck.h b/clang-tools-extra/clang-tidy/bugprone/UniquePtrArrayMismatchCheck.h new file mode 100644 index 0000000000000..fb7531ab146c6 --- /dev/null +++ b/clang-tools-extra/clang-tidy/bugprone/UniquePtrArrayMismatchCheck.h @@ -0,0 +1,34 @@ +//===--- UniquePtrArrayMismatchCheck.h - clang-tidy -------------*- C++ -*-===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#ifndef LLVM_CLANG_TOOLS_EXTRA_CLANG_TIDY_BUGPRONE_UNIQUEPTRARRAYMISMATCHCHECK_H +#define LLVM_CLANG_TOOLS_EXTRA_CLANG_TIDY_BUGPRONE_UNIQUEPTRARRAYMISMATCHCHECK_H + +#include "SmartPtrArrayMismatchCheck.h" + +namespace clang::tidy::bugprone { + +/// Finds initializations of C++ unique pointers to non-array type that are +/// initialized with an array. +/// +/// Example: +/// +/// \code +/// std::unique_ptr PtrArr{new int[10]}; +/// \endcode +class UniquePtrArrayMismatchCheck : public SmartPtrArrayMismatchCheck { +public: + UniquePtrArrayMismatchCheck(StringRef Name, ClangTidyContext *Context); + +protected: + SmartPtrClassMatcher getSmartPointerClassMatcher() const override; +}; + +} // namespace clang::tidy::bugprone + +#endif // LLVM_CLANG_TOOLS_EXTRA_CLANG_TIDY_BUGPRONE_UNIQUEPTRARRAYMISMATCHCHECK_H diff --git a/clang-tools-extra/clang-tidy/bugprone/UnusedReturnValueCheck.cpp b/clang-tools-extra/clang-tidy/bugprone/UnusedReturnValueCheck.cpp index f8139381d7e01..bdc601c2445f5 100644 --- a/clang-tools-extra/clang-tidy/bugprone/UnusedReturnValueCheck.cpp +++ b/clang-tools-extra/clang-tidy/bugprone/UnusedReturnValueCheck.cpp @@ -127,9 +127,10 @@ UnusedReturnValueCheck::UnusedReturnValueCheck(llvm::StringRef Name, "::ttyname")), CheckedReturnTypes(utils::options::parseStringList( Options.get("CheckedReturnTypes", "::std::error_code;" + "::std::error_condition;" + "::std::errc;" "::std::expected;" - "::boost::system::error_code;" - "::abseil::Status"))) {} + "::boost::system::error_code"))) {} void UnusedReturnValueCheck::storeOptions(ClangTidyOptions::OptionMap &Opts) { Options.store(Opts, "CheckedFunctions", CheckedFunctions); diff --git a/clang-tools-extra/clang-tidy/llvmlibc/InlineFunctionDeclCheck.h b/clang-tools-extra/clang-tidy/llvmlibc/InlineFunctionDeclCheck.h index 85d87a59e3733..662a592abd9be 100644 --- a/clang-tools-extra/clang-tidy/llvmlibc/InlineFunctionDeclCheck.h +++ b/clang-tools-extra/clang-tidy/llvmlibc/InlineFunctionDeclCheck.h @@ -18,7 +18,7 @@ namespace clang::tidy::llvm_libc { /// are tagged with the LIBC_INLINE macro. /// /// For more information about the LIBC_INLINE macro, see -/// https://libc.llvm.org/code_style.html. +/// https://libc.llvm.org/dev/code_style.html. /// /// For the user-facing documentation see: /// http://clang.llvm.org/extra/clang-tidy/checks/llvmlibc/inline-function-decl-check.html diff --git a/clang-tools-extra/clang-tidy/misc/CMakeLists.txt b/clang-tools-extra/clang-tidy/misc/CMakeLists.txt index a72362906e0b8..a37f7b29ec999 100644 --- a/clang-tools-extra/clang-tidy/misc/CMakeLists.txt +++ b/clang-tools-extra/clang-tidy/misc/CMakeLists.txt @@ -7,6 +7,7 @@ setup_host_tool(clang-tidy-confusable-chars-gen CLANG_TIDY_CONFUSABLE_CHARS_GEN add_subdirectory(ConfusableTable) +include_directories(BEFORE "${CMAKE_CURRENT_SOURCE_DIR}/../../include-cleaner/include") add_custom_command( OUTPUT Confusables.inc @@ -19,6 +20,7 @@ add_clang_library(clangTidyMiscModule ConstCorrectnessCheck.cpp DefinitionsInHeadersCheck.cpp ConfusableIdentifierCheck.cpp + IncludeCleanerCheck.cpp MiscTidyModule.cpp MisleadingBidirectional.cpp MisleadingIdentifier.cpp @@ -53,7 +55,14 @@ clang_target_link_libraries(clangTidyMiscModule clangAST clangASTMatchers clangBasic + clangFormat clangLex clangSerialization clangTooling + clangToolingInclusions + clangToolingInclusionsStdlib + ) +target_link_libraries(clangTidyMiscModule + PRIVATE + clangIncludeCleaner ) diff --git a/clang-tools-extra/clang-tidy/misc/IncludeCleanerCheck.cpp b/clang-tools-extra/clang-tidy/misc/IncludeCleanerCheck.cpp new file mode 100644 index 0000000000000..c7aca83f2ca8c --- /dev/null +++ b/clang-tools-extra/clang-tidy/misc/IncludeCleanerCheck.cpp @@ -0,0 +1,202 @@ +//===--- IncludeCleanerCheck.cpp - clang-tidy -----------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#include "IncludeCleanerCheck.h" +#include "../ClangTidyCheck.h" +#include "../ClangTidyDiagnosticConsumer.h" +#include "../ClangTidyOptions.h" +#include "../utils/OptionsUtils.h" +#include "clang-include-cleaner/Analysis.h" +#include "clang-include-cleaner/Record.h" +#include "clang-include-cleaner/Types.h" +#include "clang/AST/ASTContext.h" +#include "clang/AST/Decl.h" +#include "clang/AST/DeclBase.h" +#include "clang/ASTMatchers/ASTMatchFinder.h" +#include "clang/ASTMatchers/ASTMatchers.h" +#include "clang/Basic/Diagnostic.h" +#include "clang/Basic/FileEntry.h" +#include "clang/Basic/LLVM.h" +#include "clang/Basic/LangOptions.h" +#include "clang/Basic/SourceLocation.h" +#include "clang/Format/Format.h" +#include "clang/Lex/Preprocessor.h" +#include "clang/Tooling/Core/Replacement.h" +#include "clang/Tooling/Inclusions/HeaderIncludes.h" +#include "llvm/ADT/DenseSet.h" +#include "llvm/ADT/STLExtras.h" +#include "llvm/ADT/SmallVector.h" +#include "llvm/ADT/StringRef.h" +#include "llvm/Support/ErrorHandling.h" +#include "llvm/Support/Regex.h" +#include +#include +#include + +using namespace clang::ast_matchers; + +namespace clang::tidy::misc { + +namespace { +struct MissingIncludeInfo { + SourceLocation SymRefLocation; + include_cleaner::Header Missing; +}; +} // namespace + +IncludeCleanerCheck::IncludeCleanerCheck(StringRef Name, + ClangTidyContext *Context) + : ClangTidyCheck(Name, Context), + IgnoreHeaders(utils::options::parseStringList( + Options.getLocalOrGlobal("IgnoreHeaders", ""))) { + for (const auto &Header : IgnoreHeaders) { + if (!llvm::Regex{Header}.isValid()) + configurationDiag("Invalid ignore headers regex '%0'") << Header; + std::string HeaderSuffix{Header.str()}; + if (!Header.ends_with("$")) + HeaderSuffix += "$"; + IgnoreHeadersRegex.emplace_back(HeaderSuffix); + } +} + +void IncludeCleanerCheck::storeOptions(ClangTidyOptions::OptionMap &Opts) { + Options.store(Opts, "IgnoreHeaders", + utils::options::serializeStringList(IgnoreHeaders)); +} + +bool IncludeCleanerCheck::isLanguageVersionSupported( + const LangOptions &LangOpts) const { + return !LangOpts.ObjC; +} + +void IncludeCleanerCheck::registerMatchers(MatchFinder *Finder) { + Finder->addMatcher(translationUnitDecl().bind("top"), this); +} + +void IncludeCleanerCheck::registerPPCallbacks(const SourceManager &SM, + Preprocessor *PP, + Preprocessor *ModuleExpanderPP) { + PP->addPPCallbacks(RecordedPreprocessor.record(*PP)); + HS = &PP->getHeaderSearchInfo(); + RecordedPI.record(*PP); +} + +bool IncludeCleanerCheck::shouldIgnore(const include_cleaner::Header &H) { + return llvm::any_of(IgnoreHeadersRegex, [&H](const llvm::Regex &R) { + switch (H.kind()) { + case include_cleaner::Header::Standard: + return R.match(H.standard().name()); + case include_cleaner::Header::Verbatim: + return R.match(H.verbatim()); + case include_cleaner::Header::Physical: + return R.match(H.physical()->tryGetRealPathName()); + } + llvm_unreachable("Unknown Header kind."); + }); +} + +void IncludeCleanerCheck::check(const MatchFinder::MatchResult &Result) { + const SourceManager *SM = Result.SourceManager; + const FileEntry *MainFile = SM->getFileEntryForID(SM->getMainFileID()); + llvm::DenseSet Used; + std::vector Missing; + llvm::SmallVector MainFileDecls; + for (Decl *D : Result.Nodes.getNodeAs("top")->decls()) { + if (!SM->isWrittenInMainFile(SM->getExpansionLoc(D->getLocation()))) + continue; + // FIXME: Filter out implicit template specializations. + MainFileDecls.push_back(D); + } + // FIXME: Find a way to have less code duplication between include-cleaner + // analysis implementation and the below code. + walkUsed(MainFileDecls, RecordedPreprocessor.MacroReferences, &RecordedPI, + *SM, + [&](const include_cleaner::SymbolReference &Ref, + llvm::ArrayRef Providers) { + bool Satisfied = false; + for (const include_cleaner::Header &H : Providers) { + if (H.kind() == include_cleaner::Header::Physical && + H.physical() == MainFile) + Satisfied = true; + + for (const include_cleaner::Include *I : + RecordedPreprocessor.Includes.match(H)) { + Used.insert(I); + Satisfied = true; + } + } + if (!Satisfied && !Providers.empty() && + Ref.RT == include_cleaner::RefType::Explicit && + !shouldIgnore(Providers.front())) + Missing.push_back({Ref.RefLocation, Providers.front()}); + }); + + std::vector Unused; + for (const include_cleaner::Include &I : + RecordedPreprocessor.Includes.all()) { + if (Used.contains(&I) || !I.Resolved) + continue; + if (RecordedPI.shouldKeep(I.Line)) + continue; + // Check if main file is the public interface for a private header. If so + // we shouldn't diagnose it as unused. + if (auto PHeader = RecordedPI.getPublic(I.Resolved); !PHeader.empty()) { + PHeader = PHeader.trim("<>\""); + // Since most private -> public mappings happen in a verbatim way, we + // check textually here. This might go wrong in presence of symlinks or + // header mappings. But that's not different than rest of the places. + if (getCurrentMainFile().endswith(PHeader)) + continue; + } + + if (llvm::none_of(IgnoreHeadersRegex, + [Resolved = I.Resolved->tryGetRealPathName()]( + const llvm::Regex &R) { return R.match(Resolved); })) + Unused.push_back(&I); + } + + llvm::StringRef Code = SM->getBufferData(SM->getMainFileID()); + auto FileStyle = + format::getStyle(format::DefaultFormatStyle, getCurrentMainFile(), + format::DefaultFallbackStyle, Code, + &SM->getFileManager().getVirtualFileSystem()); + if (!FileStyle) + FileStyle = format::getLLVMStyle(); + + for (const auto *Inc : Unused) { + diag(Inc->HashLocation, "included header %0 is not used directly") + << Inc->quote() + << FixItHint::CreateRemoval(CharSourceRange::getCharRange( + SM->translateLineCol(SM->getMainFileID(), Inc->Line, 1), + SM->translateLineCol(SM->getMainFileID(), Inc->Line + 1, 1))); + } + + tooling::HeaderIncludes HeaderIncludes(getCurrentMainFile(), Code, + FileStyle->IncludeStyle); + for (const auto &Inc : Missing) { + std::string Spelling = + include_cleaner::spellHeader(Inc.Missing, *HS, MainFile); + bool Angled = llvm::StringRef{Spelling}.starts_with("<"); + // We might suggest insertion of an existing include in edge cases, e.g., + // include is present in a PP-disabled region, or spelling of the header + // turns out to be the same as one of the unresolved includes in the + // main file. + if (auto Replacement = + HeaderIncludes.insert(llvm::StringRef{Spelling}.trim("\"<>"), + Angled, tooling::IncludeDirective::Include)) + diag(SM->getSpellingLoc(Inc.SymRefLocation), + "no header providing %0 is directly included") + << Spelling + << FixItHint::CreateInsertion( + SM->getComposedLoc(SM->getMainFileID(), + Replacement->getOffset()), + Replacement->getReplacementText()); + } +} + +} // namespace clang::tidy::misc diff --git a/clang-tools-extra/clang-tidy/misc/IncludeCleanerCheck.h b/clang-tools-extra/clang-tidy/misc/IncludeCleanerCheck.h new file mode 100644 index 0000000000000..d5f75f2b1c7fa --- /dev/null +++ b/clang-tools-extra/clang-tidy/misc/IncludeCleanerCheck.h @@ -0,0 +1,53 @@ +//===--- IncludeCleanerCheck.h - clang-tidy ---------------------*- C++ -*-===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#ifndef LLVM_CLANG_TOOLS_EXTRA_CLANG_TIDY_MISC_INCLUDECLEANER_H +#define LLVM_CLANG_TOOLS_EXTRA_CLANG_TIDY_MISC_INCLUDECLEANER_H + +#include "../ClangTidyCheck.h" +#include "../ClangTidyDiagnosticConsumer.h" +#include "../ClangTidyOptions.h" +#include "clang-include-cleaner/Record.h" +#include "clang-include-cleaner/Types.h" +#include "clang/ASTMatchers/ASTMatchFinder.h" +#include "clang/Basic/LLVM.h" +#include "clang/Basic/SourceLocation.h" +#include "clang/Lex/HeaderSearch.h" +#include "llvm/Support/Regex.h" +#include + +namespace clang::tidy::misc { + +/// Checks for unused and missing includes. Generates findings only for +/// the main file of a translation unit. +/// Findings correspond to https://clangd.llvm.org/design/include-cleaner. +/// +/// For the user-facing documentation see: +/// http://clang.llvm.org/extra/clang-tidy/checks/misc/include-cleaner.html +class IncludeCleanerCheck : public ClangTidyCheck { +public: + IncludeCleanerCheck(StringRef Name, ClangTidyContext *Context); + void registerMatchers(ast_matchers::MatchFinder *Finder) override; + void check(const ast_matchers::MatchFinder::MatchResult &Result) override; + void registerPPCallbacks(const SourceManager &SM, Preprocessor *PP, + Preprocessor *ModuleExpanderPP) override; + void storeOptions(ClangTidyOptions::OptionMap &Opts) override; + bool isLanguageVersionSupported(const LangOptions &LangOpts) const override; + +private: + include_cleaner::RecordedPP RecordedPreprocessor; + include_cleaner::PragmaIncludes RecordedPI; + HeaderSearch *HS; + std::vector IgnoreHeaders; + llvm::SmallVector IgnoreHeadersRegex; + bool shouldIgnore(const include_cleaner::Header &H); +}; + +} // namespace clang::tidy::misc + +#endif // LLVM_CLANG_TOOLS_EXTRA_CLANG_TIDY_MISC_INCLUDECLEANER_H diff --git a/clang-tools-extra/clang-tidy/misc/MiscTidyModule.cpp b/clang-tools-extra/clang-tidy/misc/MiscTidyModule.cpp index 2ec61f8912632..f63c5ab543feb 100644 --- a/clang-tools-extra/clang-tidy/misc/MiscTidyModule.cpp +++ b/clang-tools-extra/clang-tidy/misc/MiscTidyModule.cpp @@ -12,6 +12,7 @@ #include "ConfusableIdentifierCheck.h" #include "ConstCorrectnessCheck.h" #include "DefinitionsInHeadersCheck.h" +#include "IncludeCleanerCheck.h" #include "MisleadingBidirectional.h" #include "MisleadingIdentifier.h" #include "MisplacedConstCheck.h" @@ -41,6 +42,7 @@ class MiscModule : public ClangTidyModule { "misc-const-correctness"); CheckFactories.registerCheck( "misc-definitions-in-headers"); + CheckFactories.registerCheck("misc-include-cleaner"); CheckFactories.registerCheck( "misc-misleading-bidirectional"); CheckFactories.registerCheck( diff --git a/clang-tools-extra/clang-tidy/utils/ExceptionAnalyzer.cpp b/clang-tools-extra/clang-tidy/utils/ExceptionAnalyzer.cpp index c862303706ccb..690e771414a75 100644 --- a/clang-tools-extra/clang-tidy/utils/ExceptionAnalyzer.cpp +++ b/clang-tools-extra/clang-tidy/utils/ExceptionAnalyzer.cpp @@ -523,6 +523,19 @@ ExceptionAnalyzer::ExceptionInfo ExceptionAnalyzer::throwsException( ExceptionInfo Excs = throwsException(DefaultInit->getExpr(), Caught, CallStack); Results.merge(Excs); + } else if (const auto *Coro = dyn_cast(St)) { + for (const Stmt *Child : Coro->childrenExclBody()) { + ExceptionInfo Excs = throwsException(Child, Caught, CallStack); + Results.merge(Excs); + } + ExceptionInfo Excs = throwsException(Coro->getBody(), Caught, CallStack); + for (const Type *Throwable : Excs.getExceptionTypes()) { + if (const auto ThrowableRec = Throwable->getAsCXXRecordDecl()) { + ExceptionInfo DestructorExcs = + throwsException(ThrowableRec->getDestructor(), CallStack); + Results.merge(DestructorExcs); + } + } } else { for (const Stmt *Child : St->children()) { ExceptionInfo Excs = throwsException(Child, Caught, CallStack); diff --git a/clang-tools-extra/clangd/ClangdServer.cpp b/clang-tools-extra/clangd/ClangdServer.cpp index 7c5042b8414b4..cd3a52249dfb7 100644 --- a/clang-tools-extra/clangd/ClangdServer.cpp +++ b/clang-tools-extra/clangd/ClangdServer.cpp @@ -116,8 +116,8 @@ struct UpdateIndexCallbacks : public ParsingCallbacks { ServerCallbacks->onDiagnosticsReady(Path, AST.version(), std::move(Diagnostics)); if (CollectInactiveRegions) { - ServerCallbacks->onInactiveRegionsReady( - Path, std::move(AST.getMacros().SkippedRanges)); + ServerCallbacks->onInactiveRegionsReady(Path, + getInactiveRegions(AST)); } }); } diff --git a/clang-tools-extra/clangd/Diagnostics.cpp b/clang-tools-extra/clangd/Diagnostics.cpp index 4c5def3063f1e..bae528a105c87 100644 --- a/clang-tools-extra/clangd/Diagnostics.cpp +++ b/clang-tools-extra/clangd/Diagnostics.cpp @@ -710,7 +710,7 @@ void StoreDiags::HandleDiagnostic(DiagnosticsEngine::Level DiagLevel, auto FID = SM.getFileID(Info.getLocation()); if (const auto FE = SM.getFileEntryRefForID(FID)) { D.File = FE->getName().str(); - D.AbsFile = getCanonicalPath(*FE, SM); + D.AbsFile = getCanonicalPath(*FE, SM.getFileManager()); } D.ID = Info.getID(); return D; diff --git a/clang-tools-extra/clangd/Headers.cpp b/clang-tools-extra/clangd/Headers.cpp index 344afdba9622a..f1838931f5a4d 100644 --- a/clang-tools-extra/clangd/Headers.cpp +++ b/clang-tools-extra/clangd/Headers.cpp @@ -29,7 +29,7 @@ class IncludeStructure::RecordHeaders : public PPCallbacks { public: RecordHeaders(const CompilerInstance &CI, IncludeStructure *Out) : SM(CI.getSourceManager()), - HeaderInfo(CI.getPreprocessor().getHeaderSearchInfo()), Out(Out) {} + Out(Out) {} // Record existing #includes - both written and resolved paths. Only #includes // in the main file are collected. @@ -119,7 +119,6 @@ class IncludeStructure::RecordHeaders : public PPCallbacks { bool inMainFile() const { return Level == 1; } const SourceManager &SM; - HeaderSearch &HeaderInfo; // Set after entering the file. FileID BuiltinFile; // Indicates whether file is part of include stack. diff --git a/clang-tools-extra/clangd/IncludeCleaner.cpp b/clang-tools-extra/clangd/IncludeCleaner.cpp index 18be1329f1fad..a3e08bc56b31d 100644 --- a/clang-tools-extra/clangd/IncludeCleaner.cpp +++ b/clang-tools-extra/clangd/IncludeCleaner.cpp @@ -336,7 +336,7 @@ std::string spellHeader(ParsedAST &AST, const FileEntry *MainFile, include_cleaner::Header Provider) { if (Provider.kind() == include_cleaner::Header::Physical) { if (auto CanonicalPath = getCanonicalPath(Provider.physical()->getLastRef(), - AST.getSourceManager())) { + AST.getSourceManager().getFileManager())) { std::string SpelledHeader = llvm::cantFail(URI::includeSpelling(URI::create(*CanonicalPath))); if (!SpelledHeader.empty()) diff --git a/clang-tools-extra/clangd/SemanticHighlighting.cpp b/clang-tools-extra/clangd/SemanticHighlighting.cpp index 34a0214b082bd..ec37476cf94ea 100644 --- a/clang-tools-extra/clangd/SemanticHighlighting.cpp +++ b/clang-tools-extra/clangd/SemanticHighlighting.cpp @@ -39,6 +39,17 @@ namespace clang { namespace clangd { namespace { +/// Get the last Position on a given line. +llvm::Expected endOfLine(llvm::StringRef Code, int Line) { + auto StartOfLine = positionToOffset(Code, Position{Line, 0}); + if (!StartOfLine) + return StartOfLine.takeError(); + StringRef LineText = Code.drop_front(*StartOfLine).take_until([](char C) { + return C == '\n'; + }); + return Position{Line, static_cast(lspLength(LineText))}; +} + /// Some names are not written in the source code and cannot be highlighted, /// e.g. anonymous classes. This function detects those cases. bool canHighlightName(DeclarationName Name) { @@ -516,38 +527,27 @@ class HighlightingsBuilder { // Merge token stream with "inactive line" markers. std::vector WithInactiveLines; - auto SortedSkippedRanges = AST.getMacros().SkippedRanges; - llvm::sort(SortedSkippedRanges); + auto SortedInactiveRegions = getInactiveRegions(AST); + llvm::sort(SortedInactiveRegions); auto It = NonConflicting.begin(); - for (const Range &R : SortedSkippedRanges) { - // Create one token for each line in the skipped range, so it works + for (const Range &R : SortedInactiveRegions) { + // Create one token for each line in the inactive range, so it works // with line-based diffing. assert(R.start.line <= R.end.line); for (int Line = R.start.line; Line <= R.end.line; ++Line) { - // If the end of the inactive range is at the beginning - // of a line, that line is not inactive. - if (Line == R.end.line && R.end.character == 0) - continue; // Copy tokens before the inactive line for (; It != NonConflicting.end() && It->R.start.line < Line; ++It) WithInactiveLines.push_back(std::move(*It)); // Add a token for the inactive line itself. - auto StartOfLine = positionToOffset(MainCode, Position{Line, 0}); - if (StartOfLine) { - StringRef LineText = - MainCode.drop_front(*StartOfLine).take_until([](char C) { - return C == '\n'; - }); + auto EndOfLine = endOfLine(MainCode, Line); + if (EndOfLine) { HighlightingToken HT; WithInactiveLines.emplace_back(); WithInactiveLines.back().Kind = HighlightingKind::InactiveCode; WithInactiveLines.back().R.start.line = Line; - WithInactiveLines.back().R.end.line = Line; - WithInactiveLines.back().R.end.character = - static_cast(lspLength(LineText)); + WithInactiveLines.back().R.end = *EndOfLine; } else { - elog("Failed to convert position to offset: {0}", - StartOfLine.takeError()); + elog("Failed to determine end of line: {0}", EndOfLine.takeError()); } // Skip any other tokens on the inactive line. e.g. @@ -1544,5 +1544,40 @@ diffTokens(llvm::ArrayRef Old, return {std::move(Edit)}; } +std::vector getInactiveRegions(ParsedAST &AST) { + std::vector SkippedRanges(std::move(AST.getMacros().SkippedRanges)); + const auto &SM = AST.getSourceManager(); + StringRef MainCode = SM.getBufferOrFake(SM.getMainFileID()).getBuffer(); + std::vector InactiveRegions; + for (const Range &Skipped : SkippedRanges) { + Range Inactive = Skipped; + // Sometimes, SkippedRanges contains a range ending at position 0 + // of a line. Clients that apply whole-line styles will treat that + // line as inactive which is not desirable, so adjust the ending + // position to be the end of the previous line. + if (Inactive.end.character == 0 && Inactive.end.line > 0) { + --Inactive.end.line; + } + // Exclude the directive lines themselves from the range. + if (Inactive.end.line >= Inactive.start.line + 2) { + ++Inactive.start.line; + --Inactive.end.line; + } else { + // range would be empty, e.g. #endif on next line after #ifdef + continue; + } + // Since we've adjusted the ending line, we need to recompute the + // column to reflect the end of that line. + if (auto EndOfLine = endOfLine(MainCode, Inactive.end.line)) { + Inactive.end = *EndOfLine; + } else { + elog("Failed to determine end of line: {0}", EndOfLine.takeError()); + continue; + } + InactiveRegions.push_back(Inactive); + } + return InactiveRegions; +} + } // namespace clangd } // namespace clang diff --git a/clang-tools-extra/clangd/SemanticHighlighting.h b/clang-tools-extra/clangd/SemanticHighlighting.h index ca90230dfb8fb..c9db598ff08c9 100644 --- a/clang-tools-extra/clangd/SemanticHighlighting.h +++ b/clang-tools-extra/clangd/SemanticHighlighting.h @@ -120,6 +120,11 @@ llvm::StringRef toSemanticTokenModifier(HighlightingModifier Modifier); std::vector diffTokens(llvm::ArrayRef Before, llvm::ArrayRef After); +// Returns ranges of the file that are inside an inactive preprocessor branch. +// The preprocessor directives at the beginning and end of a branch themselves +// are not included. +std::vector getInactiveRegions(ParsedAST &AST); + } // namespace clangd } // namespace clang diff --git a/clang-tools-extra/clangd/SourceCode.cpp b/clang-tools-extra/clangd/SourceCode.cpp index 831adc3d5fd8d..c460ae307f114 100644 --- a/clang-tools-extra/clangd/SourceCode.cpp +++ b/clang-tools-extra/clangd/SourceCode.cpp @@ -514,11 +514,11 @@ std::vector replacementsToEdits(llvm::StringRef Code, } std::optional getCanonicalPath(const FileEntryRef F, - const SourceManager &SourceMgr) { + FileManager &FileMgr) { llvm::SmallString<128> FilePath = F.getName(); if (!llvm::sys::path::is_absolute(FilePath)) { if (auto EC = - SourceMgr.getFileManager().getVirtualFileSystem().makeAbsolute( + FileMgr.getVirtualFileSystem().makeAbsolute( FilePath)) { elog("Could not turn relative path '{0}' to absolute: {1}", FilePath, EC.message()); @@ -537,10 +537,10 @@ std::optional getCanonicalPath(const FileEntryRef F, // // The file path of Symbol is "/project/src/foo.h" instead of // "/tmp/build/foo.h" - if (auto Dir = SourceMgr.getFileManager().getDirectory( + if (auto Dir = FileMgr.getDirectory( llvm::sys::path::parent_path(FilePath))) { llvm::SmallString<128> RealPath; - llvm::StringRef DirName = SourceMgr.getFileManager().getCanonicalName(*Dir); + llvm::StringRef DirName = FileMgr.getCanonicalName(*Dir); llvm::sys::path::append(RealPath, DirName, llvm::sys::path::filename(FilePath)); return RealPath.str().str(); diff --git a/clang-tools-extra/clangd/SourceCode.h b/clang-tools-extra/clangd/SourceCode.h index 8b7c028eb2478..3ba6f8b80ef37 100644 --- a/clang-tools-extra/clangd/SourceCode.h +++ b/clang-tools-extra/clangd/SourceCode.h @@ -164,7 +164,7 @@ TextEdit toTextEdit(const FixItHint &FixIt, const SourceManager &M, /// component that generate it, so that paths are normalized as much as /// possible. std::optional getCanonicalPath(const FileEntryRef F, - const SourceManager &SourceMgr); + FileManager &FileMgr); /// Choose the clang-format style we should apply to a certain file. /// This will usually use FS to look for .clang-format directories. diff --git a/clang-tools-extra/clangd/TUScheduler.cpp b/clang-tools-extra/clangd/TUScheduler.cpp index 126937ff49e90..5fc98eec3a2fd 100644 --- a/clang-tools-extra/clangd/TUScheduler.cpp +++ b/clang-tools-extra/clangd/TUScheduler.cpp @@ -635,10 +635,6 @@ class ASTWorker { std::shared_ptr Preamble, std::vector CIDiags, WantDiagnostics WantDiags); - /// Obtain a preamble reflecting all updates so far. Threadsafe. - /// It may be delivered immediately, or later on the worker thread. - void getCurrentPreamble( - llvm::unique_function)>); /// Returns compile command from the current file inputs. tooling::CompileCommand getCurrentCompileCommand() const; diff --git a/clang-tools-extra/clangd/TidyProvider.cpp b/clang-tools-extra/clangd/TidyProvider.cpp index e3a6d5af20ae2..f101199a20ceb 100644 --- a/clang-tools-extra/clangd/TidyProvider.cpp +++ b/clang-tools-extra/clangd/TidyProvider.cpp @@ -196,32 +196,35 @@ TidyProvider addTidyChecks(llvm::StringRef Checks, TidyProvider disableUnusableChecks(llvm::ArrayRef ExtraBadChecks) { constexpr llvm::StringLiteral Seperator(","); - static const std::string BadChecks = - llvm::join_items(Seperator, - // We want this list to start with a seperator to - // simplify appending in the lambda. So including an - // empty string here will force that. - "", - // ----- False Positives ----- - - // Check relies on seeing ifndef/define/endif directives, - // clangd doesn't replay those when using a preamble. - "-llvm-header-guard", "-modernize-macro-to-enum", - - // ----- Crashing Checks ----- - - // Check can choke on invalid (intermediate) c++ - // code, which is often the case when clangd - // tries to build an AST. - "-bugprone-use-after-move", - // Alias for bugprone-use-after-move. - "-hicpp-invalid-access-moved", - - // ----- Performance problems ----- - - // This check runs expensive analysis for each variable. - // It has been observed to increase reparse time by 10x. - "-misc-const-correctness"); + static const std::string BadChecks = llvm::join_items( + Seperator, + // We want this list to start with a seperator to + // simplify appending in the lambda. So including an + // empty string here will force that. + "", + // include-cleaner is directly integrated in IncludeCleaner.cpp + "-misc-include-cleaner", + + // ----- False Positives ----- + + // Check relies on seeing ifndef/define/endif directives, + // clangd doesn't replay those when using a preamble. + "-llvm-header-guard", "-modernize-macro-to-enum", + + // ----- Crashing Checks ----- + + // Check can choke on invalid (intermediate) c++ + // code, which is often the case when clangd + // tries to build an AST. + "-bugprone-use-after-move", + // Alias for bugprone-use-after-move. + "-hicpp-invalid-access-moved", + + // ----- Performance problems ----- + + // This check runs expensive analysis for each variable. + // It has been observed to increase reparse time by 10x. + "-misc-const-correctness"); size_t Size = BadChecks.size(); for (const std::string &Str : ExtraBadChecks) { diff --git a/clang-tools-extra/clangd/XRefs.cpp b/clang-tools-extra/clangd/XRefs.cpp index 51a3ef894c540..ad4819fe4b4db 100644 --- a/clang-tools-extra/clangd/XRefs.cpp +++ b/clang-tools-extra/clangd/XRefs.cpp @@ -217,7 +217,7 @@ std::optional makeLocation(const ASTContext &AST, SourceLocation Loc, const auto F = SM.getFileEntryRefForID(SM.getFileID(Loc)); if (!F) return std::nullopt; - auto FilePath = getCanonicalPath(*F, SM); + auto FilePath = getCanonicalPath(*F, SM.getFileManager()); if (!FilePath) { log("failed to get path!"); return std::nullopt; @@ -1688,7 +1688,7 @@ declToHierarchyItem(const NamedDecl &ND, llvm::StringRef TUPath) { const auto FE = SM.getFileEntryRefForID(SM.getFileID(NameLoc)); if (!FE) return std::nullopt; - auto FilePath = getCanonicalPath(*FE, SM); + auto FilePath = getCanonicalPath(*FE, SM.getFileManager()); if (!FilePath) return std::nullopt; // Not useful without a uri. diff --git a/clang-tools-extra/clangd/index/Background.cpp b/clang-tools-extra/clangd/index/Background.cpp index 73330b3ae6a86..c35de750435cc 100644 --- a/clang-tools-extra/clangd/index/Background.cpp +++ b/clang-tools-extra/clangd/index/Background.cpp @@ -291,7 +291,7 @@ llvm::Error BackgroundIndex::index(tooling::CompileCommand Cmd) { const auto F = SM.getFileEntryRefForID(FID); if (!F) return false; // Skip invalid files. - auto AbsPath = getCanonicalPath(*F, SM); + auto AbsPath = getCanonicalPath(*F, SM.getFileManager()); if (!AbsPath) return false; // Skip files without absolute path. auto Digest = digestFile(SM, FID); diff --git a/clang-tools-extra/clangd/index/StdLib.cpp b/clang-tools-extra/clangd/index/StdLib.cpp index 381d599e3d2aa..d9aa46d6b75b1 100644 --- a/clang-tools-extra/clangd/index/StdLib.cpp +++ b/clang-tools-extra/clangd/index/StdLib.cpp @@ -314,7 +314,7 @@ std::optional StdLibSet::add(const LangOptions &LO, llvm::make_range(HS.search_dir_begin(), HS.search_dir_end())) { switch (DL.getLookupType()) { case DirectoryLookup::LT_NormalDir: { - Path = DL.getDir()->getName(); + Path = DL.getDirRef()->getName(); llvm::sys::path::append(Path, ProbeHeader); llvm::vfs::Status Stat; if (!HS.getFileMgr().getNoncachedStatValue(Path, Stat) && diff --git a/clang-tools-extra/clangd/index/SymbolCollector.cpp b/clang-tools-extra/clangd/index/SymbolCollector.cpp index a2f8cd2a0cdaf..131d0a3d0391c 100644 --- a/clang-tools-extra/clangd/index/SymbolCollector.cpp +++ b/clang-tools-extra/clangd/index/SymbolCollector.cpp @@ -208,7 +208,7 @@ class SymbolCollector::HeaderFileURICache { const std::string &toURI(const FileEntryRef FE) { auto R = CacheFEToURI.try_emplace(FE); if (R.second) { - auto CanonPath = getCanonicalPath(FE, SM); + auto CanonPath = getCanonicalPath(FE, SM.getFileManager()); R.first->second = &toURIInternal(CanonPath ? *CanonPath : FE.getName()); } return *R.first->second; @@ -298,7 +298,7 @@ class SymbolCollector::HeaderFileURICache { // importing the header. std::optional getFrameworkUmbrellaSpelling( llvm::StringRef Framework, SrcMgr::CharacteristicKind HeadersDirKind, - HeaderSearch &HS, FrameworkHeaderPath &HeaderPath) { + const HeaderSearch &HS, FrameworkHeaderPath &HeaderPath) { auto Res = CacheFrameworkToUmbrellaHeaderSpelling.try_emplace(Framework); auto *CachedSpelling = &Res.first->second; if (!Res.second) { diff --git a/clang-tools-extra/clangd/indexer/IndexerMain.cpp b/clang-tools-extra/clangd/indexer/IndexerMain.cpp index a66ab91c04231..2717030e97963 100644 --- a/clang-tools-extra/clangd/indexer/IndexerMain.cpp +++ b/clang-tools-extra/clangd/indexer/IndexerMain.cpp @@ -49,7 +49,7 @@ class IndexActionFactory : public tooling::FrontendActionFactory { const auto F = SM.getFileEntryRefForID(FID); if (!F) return false; // Skip invalid files. - auto AbsPath = getCanonicalPath(*F, SM); + auto AbsPath = getCanonicalPath(*F, SM.getFileManager()); if (!AbsPath) return false; // Skip files without absolute path. std::lock_guard Lock(FilesMu); diff --git a/clang-tools-extra/clangd/refactor/Tweak.cpp b/clang-tools-extra/clangd/refactor/Tweak.cpp index bfa8bf6984f4b..840843d1bfc4b 100644 --- a/clang-tools-extra/clangd/refactor/Tweak.cpp +++ b/clang-tools-extra/clangd/refactor/Tweak.cpp @@ -105,7 +105,7 @@ Tweak::Effect::fileEdit(const SourceManager &SM, FileID FID, tooling::Replacements Replacements) { Edit Ed(SM.getBufferData(FID), std::move(Replacements)); if (const auto FE = SM.getFileEntryRefForID(FID)) - if (auto FilePath = getCanonicalPath(*FE, SM)) + if (auto FilePath = getCanonicalPath(*FE, SM.getFileManager())) return std::make_pair(*FilePath, std::move(Ed)); return error("Failed to get absolute path for edited file: {0}", SM.getFileEntryRefForID(FID)->getName()); diff --git a/clang-tools-extra/clangd/support/Function.h b/clang-tools-extra/clangd/support/Function.h index 5437729d91b62..a0bce839a77d8 100644 --- a/clang-tools-extra/clangd/support/Function.h +++ b/clang-tools-extra/clangd/support/Function.h @@ -97,7 +97,6 @@ template class Event { "use a plain type: event values are always passed by const&"); std::recursive_mutex ListenersMu; - bool IsBroadcasting = false; std::vector> Listeners; unsigned ListenerCount = 0; }; diff --git a/clang-tools-extra/clangd/unittests/ClangdTests.cpp b/clang-tools-extra/clangd/unittests/ClangdTests.cpp index c6b464fb78746..be6c2fba12d1c 100644 --- a/clang-tools-extra/clangd/unittests/ClangdTests.cpp +++ b/clang-tools-extra/clangd/unittests/ClangdTests.cpp @@ -1332,26 +1332,31 @@ TEST(ClangdServer, InactiveRegions) { #define PREAMBLEMACRO 42 #if PREAMBLEMACRO > 40 #define ACTIVE -$inactive1[[#else - #define INACTIVE -#endif]] +#else +$inactive1[[ #define INACTIVE]] +#endif int endPreamble; -$inactive2[[#ifndef CMDMACRO - int inactiveInt; -#endif]] +#ifndef CMDMACRO +$inactive2[[ int inactiveInt;]] +#endif #undef CMDMACRO -$inactive3[[#ifdef CMDMACRO - int inactiveInt2; -#else]] - int activeInt; +#ifdef CMDMACRO +$inactive3[[ int inactiveInt2;]] +#elif PREAMBLEMACRO > 0 + int activeInt1; + int activeInt2; +#else +$inactive4[[ int inactiveInt3;]] #endif +#ifdef CMDMACRO +#endif // empty inactive range, gets dropped )cpp"); Server.addDocument(testPath("foo.cpp"), Source.code()); ASSERT_TRUE(Server.blockUntilIdleForTest()); EXPECT_THAT(Callback.FoundInactiveRegions, - ElementsAre(ElementsAre(Source.range("inactive1"), - Source.range("inactive2"), - Source.range("inactive3")))); + ElementsAre(ElementsAre( + Source.range("inactive1"), Source.range("inactive2"), + Source.range("inactive3"), Source.range("inactive4")))); } } // namespace diff --git a/clang-tools-extra/clangd/unittests/SemanticHighlightingTests.cpp b/clang-tools-extra/clangd/unittests/SemanticHighlightingTests.cpp index c25dff810b764..9c6e5246f5c37 100644 --- a/clang-tools-extra/clangd/unittests/SemanticHighlightingTests.cpp +++ b/clang-tools-extra/clangd/unittests/SemanticHighlightingTests.cpp @@ -451,11 +451,11 @@ TEST(SemanticHighlighting, GetsCorrectTokens) { #define $Macro_decl[[test]] #undef $Macro[[test]] -$InactiveCode[[#ifdef test]] -$InactiveCode[[#endif]] + #ifdef $Macro[[test]] + #endif -$InactiveCode[[#if defined(test)]] -$InactiveCode[[#endif]] + #if defined($Macro[[test]]) + #endif )cpp", R"cpp( struct $Class_def[[S]] { @@ -562,8 +562,9 @@ TEST(SemanticHighlighting, GetsCorrectTokens) { R"cpp( // Code in the preamble. // Inactive lines get an empty InactiveCode token at the beginning. -$InactiveCode[[#ifdef test]] -$InactiveCode[[#endif]] + #ifdef $Macro[[test]] +$InactiveCode[[int Inactive1;]] + #endif // A declaration to cause the preamble to end. int $Variable_def[[EndPreamble]]; @@ -572,21 +573,21 @@ TEST(SemanticHighlighting, GetsCorrectTokens) { // Code inside inactive blocks does not get regular highlightings // because it's not part of the AST. #define $Macro_decl[[test2]] -$InactiveCode[[#if defined(test)]] + #if defined($Macro[[test]]) $InactiveCode[[int Inactive2;]] -$InactiveCode[[#elif defined(test2)]] + #elif defined($Macro[[test2]]) int $Variable_def[[Active1]]; -$InactiveCode[[#else]] + #else $InactiveCode[[int Inactive3;]] -$InactiveCode[[#endif]] + #endif #ifndef $Macro[[test]] int $Variable_def[[Active2]]; #endif -$InactiveCode[[#ifdef test]] + #ifdef $Macro[[test]] $InactiveCode[[int Inactive4;]] -$InactiveCode[[#else]] + #else int $Variable_def[[Active3]]; #endif )cpp", diff --git a/clang-tools-extra/docs/ReleaseNotes.rst b/clang-tools-extra/docs/ReleaseNotes.rst index 1eb8c5ba4b71b..077be93d8510f 100644 --- a/clang-tools-extra/docs/ReleaseNotes.rst +++ b/clang-tools-extra/docs/ReleaseNotes.rst @@ -121,6 +121,12 @@ New checks Detect implicit and explicit casts of ``enum`` type into ``bool`` where ``enum`` type doesn't have a zero-value enumerator. +- New :doc:`bugprone-unique-ptr-array-mismatch + ` check. + + Finds initializations of C++ unique pointers to non-array type that are + initialized with an array. + - New :doc:`bugprone-unsafe-functions ` check. @@ -159,6 +165,11 @@ New checks Checks that all implicit and explicit inline functions in header files are tagged with the ``LIBC_INLINE`` macro. +- New :doc:`misc-include-cleaner + ` check. + + Checks for unused and missing includes. + - New :doc:`modernize-type-traits ` check. @@ -395,6 +406,10 @@ Changes in existing checks `: warn on ``const &&`` constructors. +- Fixed :doc:`bugprone-exception-escape` + for coroutines where previously a warning would be emitted with coroutines + throwing exceptions in their bodies. + Removed checks ^^^^^^^^^^^^^^ diff --git a/clang-tools-extra/docs/clang-tidy/checks/bugprone/unique-ptr-array-mismatch.rst b/clang-tools-extra/docs/clang-tidy/checks/bugprone/unique-ptr-array-mismatch.rst new file mode 100644 index 0000000000000..c00385954b23c --- /dev/null +++ b/clang-tools-extra/docs/clang-tidy/checks/bugprone/unique-ptr-array-mismatch.rst @@ -0,0 +1,39 @@ +.. title:: clang-tidy - bugprone-unique-ptr-array-mismatch + +bugprone-unique-ptr-array-mismatch +================================== + +Finds initializations of C++ unique pointers to non-array type that are +initialized with an array. + +If a pointer ``std::unique_ptr`` is initialized with a new-expression +``new T[]`` the memory is not deallocated correctly. A plain ``delete`` is used +in this case to deallocate the target memory. Instead a ``delete[]`` call is +needed. A ``std::unique_ptr`` uses the correct delete operator. The check +does not emit warning if an ``unique_ptr`` with user-specified deleter type is +used. + +The check offers replacement of ``unique_ptr`` to ``unique_ptr`` if it +is used at a single variable declaration (one variable in one statement). + +Example: + +.. code-block:: c++ + + std::unique_ptr x(new Foo[10]); // -> std::unique_ptr x(new Foo[10]); + // ^ warning: unique pointer to non-array is initialized with array + std::unique_ptr x1(new Foo), x2(new Foo[10]); // no replacement + // ^ warning: unique pointer to non-array is initialized with array + + D d; + std::unique_ptr x3(new Foo[10], d); // no warning (custom deleter used) + + struct S { + std::unique_ptr x(new Foo[10]); // no replacement in this case + // ^ warning: unique pointer to non-array is initialized with array + }; + +This check partially covers the CERT C++ Coding Standard rule +`MEM51-CPP. Properly deallocate dynamically allocated resources +`_ +However, only the ``std::unique_ptr`` case is detected by this check. diff --git a/clang-tools-extra/docs/clang-tidy/checks/bugprone/unused-return-value.rst b/clang-tools-extra/docs/clang-tidy/checks/bugprone/unused-return-value.rst index 89c781b0fe714..c9b24dbcbb94f 100644 --- a/clang-tools-extra/docs/clang-tidy/checks/bugprone/unused-return-value.rst +++ b/clang-tools-extra/docs/clang-tidy/checks/bugprone/unused-return-value.rst @@ -50,7 +50,7 @@ Options Semicolon-separated list of function return types to check. By default the following function return types are checked: - `::std::error_code`, `::std::expected`, `::boost::system::error_code`, `::abseil::Status` + `::std::error_code`, `::std::error_condition`, `::std::errc`, `::std::expected`, `::boost::system::error_code` `cert-err33-c <../cert/err33-c.html>`_ is an alias of this check that checks a fixed and large set of standard library functions. diff --git a/clang-tools-extra/docs/clang-tidy/checks/list.rst b/clang-tools-extra/docs/clang-tidy/checks/list.rst index 055e6ae661f09..2b5f8e8291e0a 100644 --- a/clang-tools-extra/docs/clang-tidy/checks/list.rst +++ b/clang-tools-extra/docs/clang-tidy/checks/list.rst @@ -139,6 +139,7 @@ Clang-Tidy Checks `bugprone-undelegated-constructor `_, `bugprone-unhandled-exception-at-new `_, `bugprone-unhandled-self-assignment `_, + `bugprone-unique-ptr-array-mismatch `_, "Yes" `bugprone-unsafe-functions `_, `bugprone-unused-raii `_, "Yes" `bugprone-unused-return-value `_, @@ -254,6 +255,7 @@ Clang-Tidy Checks `misc-confusable-identifiers `_, `misc-const-correctness `_, "Yes" `misc-definitions-in-headers `_, "Yes" + `misc-include-cleaner `_, "Yes" `misc-misleading-bidirectional `_, `misc-misleading-identifier `_, `misc-misplaced-const `_, diff --git a/clang-tools-extra/docs/clang-tidy/checks/llvmlibc/inline-function-decl.rst b/clang-tools-extra/docs/clang-tidy/checks/llvmlibc/inline-function-decl.rst index da60a1fcdb112..101217b64c828 100644 --- a/clang-tools-extra/docs/clang-tidy/checks/llvmlibc/inline-function-decl.rst +++ b/clang-tools-extra/docs/clang-tidy/checks/llvmlibc/inline-function-decl.rst @@ -5,4 +5,4 @@ llvmlibc-inline-function-decl Checks that all implicit and explicit inline functions in header files are tagged with the ``LIBC_INLINE`` macro. See the `libc style guide -`_ for more information about this macro. +`_ for more information about this macro. diff --git a/clang-tools-extra/docs/clang-tidy/checks/misc/include-cleaner.rst b/clang-tools-extra/docs/clang-tidy/checks/misc/include-cleaner.rst new file mode 100644 index 0000000000000..3246fea78cd42 --- /dev/null +++ b/clang-tools-extra/docs/clang-tidy/checks/misc/include-cleaner.rst @@ -0,0 +1,35 @@ +.. title:: clang-tidy - misc-include-cleaner + +misc-include-cleaner +==================== + +Checks for unused and missing includes. Generates findings only for +the main file of a translation unit. +Findings correspond to https://clangd.llvm.org/design/include-cleaner. + +Example: + +.. code-block:: c++ + + // foo.h + class Foo{}; + // bar.h + #include "baz.h" + class Bar{}; + // baz.h + class Baz{}; + // main.cc + #include "bar.h" // OK: uses class Bar from bar.h + #include "foo.h" // warning: unused include "foo.h" + Bar bar; + Baz baz; // warning: missing include "baz.h" + +Options +------- + +.. option:: IgnoreHeaders + + A semicolon-separated list of regexes to disable insertion/removal of header + files that match this regex as a suffix. E.g., `foo/.*` disables + insertion/removal for all headers under the directory `foo`. By default, no + headers will be ignored. diff --git a/clang-tools-extra/include-cleaner/include/clang-include-cleaner/Analysis.h b/clang-tools-extra/include-cleaner/include/clang-include-cleaner/Analysis.h index 66916a52046cb..6d764c65a11b2 100644 --- a/clang-tools-extra/include-cleaner/include/clang-include-cleaner/Analysis.h +++ b/clang-tools-extra/include-cleaner/include/clang-include-cleaner/Analysis.h @@ -67,7 +67,7 @@ struct AnalysisResults { AnalysisResults analyze(llvm::ArrayRef ASTRoots, llvm::ArrayRef MacroRefs, const Includes &I, const PragmaIncludes *PI, - const SourceManager &SM, HeaderSearch &HS); + const SourceManager &SM, const HeaderSearch &HS); /// Removes unused includes and inserts missing ones in the main file. /// Returns the modified main-file code. @@ -75,7 +75,7 @@ AnalysisResults analyze(llvm::ArrayRef ASTRoots, std::string fixIncludes(const AnalysisResults &Results, llvm::StringRef Code, const format::FormatStyle &IncludeStyle); -std::string spellHeader(const Header &H, HeaderSearch &HS, +std::string spellHeader(const Header &H, const HeaderSearch &HS, const FileEntry *Main); /// Gets all the providers for a symbol by traversing each location. diff --git a/clang-tools-extra/include-cleaner/include/clang-include-cleaner/Record.h b/clang-tools-extra/include-cleaner/include/clang-include-cleaner/Record.h index 27a2270f7e362..ae11f49f83709 100644 --- a/clang-tools-extra/include-cleaner/include/clang-include-cleaner/Record.h +++ b/clang-tools-extra/include-cleaner/include/clang-include-cleaner/Record.h @@ -18,6 +18,7 @@ #define CLANG_INCLUDE_CLEANER_RECORD_H #include "clang-include-cleaner/Types.h" +#include "clang/Basic/SourceLocation.h" #include "llvm/ADT/DenseMap.h" #include "llvm/ADT/DenseSet.h" #include "llvm/ADT/SmallVector.h" @@ -52,6 +53,10 @@ class PragmaIncludes { /// to the structure. void record(const CompilerInstance &CI); + /// Installs an analysing PPCallback and CommentHandler and populates results + /// to the structure. + void record(Preprocessor &P); + /// Returns true if the given #include of the main-file should never be /// removed. bool shouldKeep(unsigned HashLineNumber) const { diff --git a/clang-tools-extra/include-cleaner/lib/Analysis.cpp b/clang-tools-extra/include-cleaner/lib/Analysis.cpp index 84f1f4cc2cf54..bf50e064e9811 100644 --- a/clang-tools-extra/include-cleaner/lib/Analysis.cpp +++ b/clang-tools-extra/include-cleaner/lib/Analysis.cpp @@ -53,7 +53,7 @@ void walkUsed(llvm::ArrayRef ASTRoots, } } -std::string spellHeader(const Header &H, HeaderSearch &HS, +std::string spellHeader(const Header &H, const HeaderSearch &HS, const FileEntry *Main) { switch (H.kind()) { case Header::Physical: { @@ -73,7 +73,7 @@ std::string spellHeader(const Header &H, HeaderSearch &HS, AnalysisResults analyze(llvm::ArrayRef ASTRoots, llvm::ArrayRef MacroRefs, const Includes &Inc, const PragmaIncludes *PI, - const SourceManager &SM, HeaderSearch &HS) { + const SourceManager &SM, const HeaderSearch &HS) { const FileEntry *MainFile = SM.getFileEntryForID(SM.getMainFileID()); llvm::DenseSet Used; llvm::StringSet<> Missing; diff --git a/clang-tools-extra/include-cleaner/lib/AnalysisInternal.h b/clang-tools-extra/include-cleaner/lib/AnalysisInternal.h index 6bfed91b584b3..cd796c2da7b80 100644 --- a/clang-tools-extra/include-cleaner/lib/AnalysisInternal.h +++ b/clang-tools-extra/include-cleaner/lib/AnalysisInternal.h @@ -63,7 +63,7 @@ std::vector> locateSymbol(const Symbol &S); void writeHTMLReport(FileID File, const Includes &, llvm::ArrayRef Roots, llvm::ArrayRef MacroRefs, ASTContext &Ctx, - HeaderSearch &HS, PragmaIncludes *PI, + const HeaderSearch &HS, PragmaIncludes *PI, llvm::raw_ostream &OS); } // namespace include_cleaner diff --git a/clang-tools-extra/include-cleaner/lib/HTMLReport.cpp b/clang-tools-extra/include-cleaner/lib/HTMLReport.cpp index c1d1982d4f487..65b82973c4290 100644 --- a/clang-tools-extra/include-cleaner/lib/HTMLReport.cpp +++ b/clang-tools-extra/include-cleaner/lib/HTMLReport.cpp @@ -134,7 +134,7 @@ class Reporter { llvm::raw_ostream &OS; const ASTContext &Ctx; const SourceManager &SM; - HeaderSearch &HS; + const HeaderSearch &HS; const include_cleaner::Includes &Includes; const PragmaIncludes *PI; FileID MainFile; @@ -208,7 +208,7 @@ class Reporter { } public: - Reporter(llvm::raw_ostream &OS, ASTContext &Ctx, HeaderSearch &HS, + Reporter(llvm::raw_ostream &OS, ASTContext &Ctx, const HeaderSearch &HS, const include_cleaner::Includes &Includes, const PragmaIncludes *PI, FileID MainFile) : OS(OS), Ctx(Ctx), SM(Ctx.getSourceManager()), HS(HS), @@ -513,7 +513,7 @@ class Reporter { void writeHTMLReport(FileID File, const include_cleaner::Includes &Includes, llvm::ArrayRef Roots, llvm::ArrayRef MacroRefs, ASTContext &Ctx, - HeaderSearch &HS, PragmaIncludes *PI, + const HeaderSearch &HS, PragmaIncludes *PI, llvm::raw_ostream &OS) { Reporter R(OS, Ctx, HS, Includes, PI, File); const auto& SM = Ctx.getSourceManager(); diff --git a/clang-tools-extra/include-cleaner/lib/Record.cpp b/clang-tools-extra/include-cleaner/lib/Record.cpp index ff29fda8663b9..e36753123392a 100644 --- a/clang-tools-extra/include-cleaner/lib/Record.cpp +++ b/clang-tools-extra/include-cleaner/lib/Record.cpp @@ -19,6 +19,8 @@ #include "clang/Lex/Preprocessor.h" #include "clang/Tooling/Inclusions/HeaderAnalysis.h" #include "clang/Tooling/Inclusions/StandardLibrary.h" +#include +#include namespace clang::include_cleaner { namespace { @@ -148,8 +150,9 @@ class PPRecorder : public PPCallbacks { class PragmaIncludes::RecordPragma : public PPCallbacks, public CommentHandler { public: RecordPragma(const CompilerInstance &CI, PragmaIncludes *Out) - : SM(CI.getSourceManager()), - HeaderInfo(CI.getPreprocessor().getHeaderSearchInfo()), Out(Out), + : RecordPragma(CI.getPreprocessor(), Out) {} + RecordPragma(const Preprocessor &P, PragmaIncludes *Out) + : SM(P.getSourceManager()), HeaderInfo(P.getHeaderSearchInfo()), Out(Out), UniqueStrings(Arena) {} void FileChanged(SourceLocation Loc, FileChangeReason Reason, @@ -305,7 +308,7 @@ class PragmaIncludes::RecordPragma : public PPCallbacks, public CommentHandler { bool InMainFile = false; const SourceManager &SM; - HeaderSearch &HeaderInfo; + const HeaderSearch &HeaderInfo; PragmaIncludes *Out; llvm::BumpPtrAllocator Arena; /// Intern table for strings. Contents are on the arena. @@ -342,6 +345,12 @@ void PragmaIncludes::record(const CompilerInstance &CI) { CI.getPreprocessor().addPPCallbacks(std::move(Record)); } +void PragmaIncludes::record(Preprocessor &P) { + auto Record = std::make_unique(P, this); + P.addCommentHandler(Record.get()); + P.addPPCallbacks(std::move(Record)); +} + llvm::StringRef PragmaIncludes::getPublic(const FileEntry *F) const { auto It = IWYUPublic.find(F->getUniqueID()); if (It == IWYUPublic.end()) @@ -350,8 +359,8 @@ llvm::StringRef PragmaIncludes::getPublic(const FileEntry *F) const { } static llvm::SmallVector -toFileEntries(llvm::ArrayRef FileNames, FileManager& FM) { - llvm::SmallVector Results; +toFileEntries(llvm::ArrayRef FileNames, FileManager &FM) { + llvm::SmallVector Results; for (auto FName : FileNames) { // FIMXE: log the failing cases? diff --git a/clang-tools-extra/modularize/CoverageChecker.cpp b/clang-tools-extra/modularize/CoverageChecker.cpp index 83c39e495c31a..d8445053872bf 100644 --- a/clang-tools-extra/modularize/CoverageChecker.cpp +++ b/clang-tools-extra/modularize/CoverageChecker.cpp @@ -207,25 +207,25 @@ void CoverageChecker::collectModuleHeaders() { // FIXME: Doesn't collect files from umbrella header. bool CoverageChecker::collectModuleHeaders(const Module &Mod) { - if (const FileEntry *UmbrellaHeader = - Mod.getUmbrellaHeaderAsWritten().Entry) { + if (std::optional UmbrellaHeader = + Mod.getUmbrellaHeaderAsWritten()) { // Collect umbrella header. - ModuleMapHeadersSet.insert(ModularizeUtilities::getCanonicalPath( - UmbrellaHeader->getName())); + ModuleMapHeadersSet.insert( + ModularizeUtilities::getCanonicalPath(UmbrellaHeader->Entry.getName())); // Preprocess umbrella header and collect the headers it references. - if (!collectUmbrellaHeaderHeaders(UmbrellaHeader->getName())) + if (!collectUmbrellaHeaderHeaders(UmbrellaHeader->Entry.getName())) return false; - } else if (const DirectoryEntry *UmbrellaDir = - Mod.getUmbrellaDirAsWritten().Entry) { + } else if (std::optional UmbrellaDir = + Mod.getUmbrellaDirAsWritten()) { // Collect headers in umbrella directory. - if (!collectUmbrellaHeaders(UmbrellaDir->getName())) + if (!collectUmbrellaHeaders(UmbrellaDir->Entry.getName())) return false; } for (auto &HeaderKind : Mod.Headers) for (auto &Header : HeaderKind) - ModuleMapHeadersSet.insert(ModularizeUtilities::getCanonicalPath( - Header.Entry->getName())); + ModuleMapHeadersSet.insert( + ModularizeUtilities::getCanonicalPath(Header.Entry.getName())); for (auto *Submodule : Mod.submodules()) collectModuleHeaders(*Submodule); diff --git a/clang-tools-extra/modularize/ModularizeUtilities.cpp b/clang-tools-extra/modularize/ModularizeUtilities.cpp index a7cadf818664a..3ef808d204c61 100644 --- a/clang-tools-extra/modularize/ModularizeUtilities.cpp +++ b/clang-tools-extra/modularize/ModularizeUtilities.cpp @@ -258,34 +258,33 @@ std::error_code ModularizeUtilities::loadProblemHeaderList( std::error_code ModularizeUtilities::loadModuleMap( llvm::StringRef InputPath) { // Get file entry for module.modulemap file. - auto ModuleMapEntryOrErr = - SourceMgr->getFileManager().getFile(InputPath); + auto ModuleMapEntryOrErr = SourceMgr->getFileManager().getFileRef(InputPath); // return error if not found. if (!ModuleMapEntryOrErr) { llvm::errs() << "error: File \"" << InputPath << "\" not found.\n"; - return ModuleMapEntryOrErr.getError(); + return errorToErrorCode(ModuleMapEntryOrErr.takeError()); } - const FileEntry *ModuleMapEntry = *ModuleMapEntryOrErr; + FileEntryRef ModuleMapEntry = *ModuleMapEntryOrErr; // Because the module map parser uses a ForwardingDiagnosticConsumer, // which doesn't forward the BeginSourceFile call, we do it explicitly here. DC.BeginSourceFile(*LangOpts, nullptr); // Figure out the home directory for the module map file. - const DirectoryEntry *Dir = ModuleMapEntry->getDir(); - StringRef DirName(Dir->getName()); + DirectoryEntryRef Dir = ModuleMapEntry.getDir(); + StringRef DirName(Dir.getName()); if (llvm::sys::path::filename(DirName) == "Modules") { DirName = llvm::sys::path::parent_path(DirName); if (DirName.endswith(".framework")) { - if (auto DirEntry = FileMgr->getDirectory(DirName)) - Dir = *DirEntry; - else - Dir = nullptr; + auto FrameworkDirOrErr = FileMgr->getDirectoryRef(DirName); + if (!FrameworkDirOrErr) { + // This can happen if there's a race between the above check and the + // removal of the directory. + return errorToErrorCode(FrameworkDirOrErr.takeError()); + } + Dir = *FrameworkDirOrErr; } - // FIXME: This assert can fail if there's a race between the above check - // and the removal of the directory. - assert(Dir && "parent must exist"); } std::unique_ptr ModMap; @@ -349,19 +348,20 @@ bool ModularizeUtilities::collectModuleHeaders(const clang::Module &Mod) { for (auto *Submodule : Mod.submodules()) collectModuleHeaders(*Submodule); - if (const FileEntry *UmbrellaHeader = - Mod.getUmbrellaHeaderAsWritten().Entry) { - std::string HeaderPath = getCanonicalPath(UmbrellaHeader->getName()); + if (std::optional UmbrellaHeader = + Mod.getUmbrellaHeaderAsWritten()) { + std::string HeaderPath = getCanonicalPath(UmbrellaHeader->Entry.getName()); // Collect umbrella header. HeaderFileNames.push_back(HeaderPath); // FUTURE: When needed, umbrella header header collection goes here. - } else if (const DirectoryEntry *UmbrellaDir = - Mod.getUmbrellaDirAsWritten().Entry) { + } else if (std::optional UmbrellaDir = + Mod.getUmbrellaDirAsWritten()) { // If there normal headers, assume these are umbrellas and skip collection. if (Mod.Headers->size() == 0) { // Collect headers in umbrella directory. - if (!collectUmbrellaHeaders(UmbrellaDir->getName(), UmbrellaDependents)) + if (!collectUmbrellaHeaders(UmbrellaDir->Entry.getName(), + UmbrellaDependents)) return false; } } @@ -378,7 +378,7 @@ bool ModularizeUtilities::collectModuleHeaders(const clang::Module &Mod) { // Collect normal header. const clang::Module::Header &Header( Mod.Headers[clang::Module::HK_Normal][Index]); - std::string HeaderPath = getCanonicalPath(Header.Entry->getName()); + std::string HeaderPath = getCanonicalPath(Header.Entry.getName()); HeaderFileNames.push_back(HeaderPath); } diff --git a/clang-tools-extra/pseudo/lib/grammar/CMakeLists.txt b/clang-tools-extra/pseudo/lib/grammar/CMakeLists.txt index f7ada93eeb60b..bb08ebab0fa62 100644 --- a/clang-tools-extra/pseudo/lib/grammar/CMakeLists.txt +++ b/clang-tools-extra/pseudo/lib/grammar/CMakeLists.txt @@ -1,10 +1,5 @@ set(LLVM_LINK_COMPONENTS Support) -# This library is used by the clang-pseudo-gen tool which runs at build time. -# Dependencies should be minimal to avoid long dep paths in the build graph. -# It does use clangBasic headers (tok::TokenKind), but linking is not needed. -# We have no transitive dependencies on tablegen files. -list(REMOVE_ITEM LLVM_COMMON_DEPENDS clang-tablegen-targets) add_clang_library(clangPseudoGrammar Grammar.cpp GrammarBNF.cpp diff --git a/clang-tools-extra/test/clang-tidy/checkers/bugprone/exception-escape-coro.cpp b/clang-tools-extra/test/clang-tidy/checkers/bugprone/exception-escape-coro.cpp new file mode 100644 index 0000000000000..9caafe7676f4e --- /dev/null +++ b/clang-tools-extra/test/clang-tidy/checkers/bugprone/exception-escape-coro.cpp @@ -0,0 +1,711 @@ +// RUN: %check_clang_tidy -std=c++20 %s bugprone-exception-escape %t -- \ +// RUN: -- -fexceptions + +namespace std { + +template struct coroutine_traits { + using promise_type = typename Ret::promise_type; +}; + +template struct coroutine_handle { + static coroutine_handle from_address(void *) noexcept; + static coroutine_handle from_promise(Promise &promise); + constexpr void *address() const noexcept; +}; + +template <> struct coroutine_handle { + template + coroutine_handle(coroutine_handle) noexcept; + static coroutine_handle from_address(void *); + constexpr void *address() const noexcept; +}; + +struct suspend_always { + bool await_ready() noexcept { return false; } + void await_suspend(coroutine_handle<>) noexcept {} + void await_resume() noexcept {} +}; + +struct suspend_never { + bool await_ready() noexcept { return true; } + void await_suspend(coroutine_handle<>) noexcept {} + void await_resume() noexcept {} +}; + +} // namespace std + +template +struct Promise; + +template < + typename T, bool ThrowInTaskConstructor = false, + bool ThrowInPromiseConstructor = false, bool ThrowInInitialSuspend = false, + bool ThrowInGetReturnObject = false, bool ThrowInUnhandledException = false> +struct Task { + using promise_type = + Promise; + + explicit Task(promise_type &p) { + if constexpr (ThrowInTaskConstructor) { + throw 1; + } + + p.return_val = this; + } + + bool await_ready() { return true; } + + void await_suspend(std::coroutine_handle<> h) {} + + void await_resume() {} + + T value; +}; + +template +struct Task { + using promise_type = + Promise; + + explicit Task(promise_type &p) { + if constexpr (ThrowInTaskConstructor) { + throw 1; + } + + p.return_val = this; + } + + bool await_ready() { return true; } + + void await_suspend(std::coroutine_handle<> h) {} + + void await_resume() {} +}; + +template +struct Promise { + Promise() { + if constexpr (ThrowInPromiseConstructor) { + throw 1; + } + } + + Task get_return_object() { + if constexpr (ThrowInGetReturnObject) { + throw 1; + } + + return Task{*this}; + } + + std::suspend_never initial_suspend() const { + if constexpr (ThrowInInitialSuspend) { + throw 1; + } + + return {}; + } + + std::suspend_never final_suspend() const noexcept { return {}; } + + template void return_value(U &&val) { + return_val->value = static_cast(val); + } + + template std::suspend_never yield_value(U &&val) { + return_val->value = static_cast(val); + return {}; + } + + void unhandled_exception() { + if constexpr (ThrowInUnhandledException) { + throw 1; + } + } + + Task *return_val; +}; + +template +struct Promise { + Promise() { + if constexpr (ThrowInPromiseConstructor) { + throw 1; + } + } + + Task get_return_object() { + if constexpr (ThrowInGetReturnObject) { + throw 1; + } + + return Task{*this}; + } + + std::suspend_never initial_suspend() const { + if constexpr (ThrowInInitialSuspend) { + throw 1; + } + + return {}; + } + + std::suspend_never final_suspend() const noexcept { return {}; } + + void return_void() {} + + void unhandled_exception() { + if constexpr (ThrowInUnhandledException) { + throw 1; + } + } + + Task *return_val; +}; + +struct Evil { + ~Evil() noexcept(false) { + // CHECK-MESSAGES: :[[@LINE-1]]:3: warning: an exception may be thrown in function '~Evil' which should not throw exceptions + throw 42; + } +}; + +Task returnOne() { co_return 1; } + +namespace function { + +namespace coreturn { + +Task a_ShouldNotDiag(const int a, const int b) { + if (b == 0) + throw b; + + co_return a / b; +} + +Task b_ShouldNotDiag(const int a, const int b) noexcept { + if (b == 0) + throw b; + + co_return a / b; +} + +Task c_ShouldNotDiag(const int a, const int b) { + if (b == 0) + throw Evil{}; + + co_return a / b; +} + +Task c_ShouldDiag(const int a, const int b) noexcept { + // CHECK-MESSAGES: :[[@LINE-1]]:11: warning: an exception may be thrown in function 'c_ShouldDiag' which should not throw exceptions + if (b == 0) + throw Evil{}; + + co_return a / b; +} + +Task d_ShouldNotDiag(const int a, const int b) { + co_return a / b; +} + +Task d_ShouldDiag(const int a, const int b) noexcept { + // CHECK-MESSAGES: :[[@LINE-1]]:17: warning: an exception may be thrown in function 'd_ShouldDiag' which should not throw exceptions + co_return a / b; +} + +Task e_ShouldNotDiag(const int a, const int b) { + co_return a / b; +} + +Task e_ShouldDiag(const int a, const int b) noexcept { + // CHECK-MESSAGES: :[[@LINE-1]]:24: warning: an exception may be thrown in function 'e_ShouldDiag' which should not throw exceptions + co_return a / b; +} + +Task f_ShouldNotDiag(const int a, const int b) { + co_return a / b; +} + +Task f_ShouldDiag(const int a, const int b) noexcept { + // CHECK-MESSAGES: :[[@LINE-1]]:31: warning: an exception may be thrown in function 'f_ShouldDiag' which should not throw exceptions + co_return a / b; +} + +Task g_ShouldNotDiag(const int a, const int b) { + co_return a / b; +} + +Task g_ShouldDiag(const int a, + const int b) noexcept { + // CHECK-MESSAGES: :[[@LINE-2]]:38: warning: an exception may be thrown in function 'g_ShouldDiag' which should not throw exceptions + co_return a / b; +} + +Task h_ShouldNotDiag(const int a, + const int b) { + co_return a / b; +} + +Task h_ShouldDiag(const int a, + const int b) noexcept { + // CHECK-MESSAGES: :[[@LINE-2]]:45: warning: an exception may be thrown in function 'h_ShouldDiag' which should not throw exceptions + co_return a / b; +} + +} // namespace coreturn + +namespace coyield { + +Task a_ShouldNotDiag(const int a, const int b) { + if (b == 0) + throw b; + + co_yield a / b; +} + +Task b_ShouldNotDiag(const int a, const int b) noexcept { + if (b == 0) + throw b; + + co_yield a / b; +} + +Task c_ShouldNotDiag(const int a, const int b) { + if (b == 0) + throw Evil{}; + + co_yield a / b; +} + +Task c_ShouldDiag(const int a, const int b) noexcept { + // CHECK-MESSAGES: :[[@LINE-1]]:11: warning: an exception may be thrown in function 'c_ShouldDiag' which should not throw exceptions + if (b == 0) + throw Evil{}; + + co_yield a / b; +} + +Task d_ShouldNotDiag(const int a, const int b) { + co_yield a / b; +} + +Task d_ShouldDiag(const int a, const int b) noexcept { + // CHECK-MESSAGES: :[[@LINE-1]]:17: warning: an exception may be thrown in function 'd_ShouldDiag' which should not throw exceptions + co_yield a / b; +} + +Task e_ShouldNotDiag(const int a, const int b) { + co_yield a / b; +} + +Task e_ShouldDiag(const int a, const int b) noexcept { + // CHECK-MESSAGES: :[[@LINE-1]]:24: warning: an exception may be thrown in function 'e_ShouldDiag' which should not throw exceptions + co_yield a / b; +} + +Task f_ShouldNotDiag(const int a, const int b) { + co_yield a / b; +} + +Task f_ShouldDiag(const int a, const int b) noexcept { + // CHECK-MESSAGES: :[[@LINE-1]]:31: warning: an exception may be thrown in function 'f_ShouldDiag' which should not throw exceptions + co_yield a / b; +} + +Task g_ShouldNotDiag(const int a, const int b) { + co_yield a / b; +} + +Task g_ShouldDiag(const int a, + const int b) noexcept { + // CHECK-MESSAGES: :[[@LINE-2]]:38: warning: an exception may be thrown in function 'g_ShouldDiag' which should not throw exceptions + co_yield a / b; +} + +Task h_ShouldNotDiag(const int a, + const int b) { + co_yield a / b; +} + +Task h_ShouldDiag(const int a, + const int b) noexcept { + // CHECK-MESSAGES: :[[@LINE-2]]:45: warning: an exception may be thrown in function 'h_ShouldDiag' which should not throw exceptions + co_yield a / b; +} + +} // namespace coyield + +namespace coawait { + +Task a_ShouldNotDiag(const int a, const int b) { + if (b == 0) + throw b; + + co_await returnOne(); +} + +Task b_ShouldNotDiag(const int a, const int b) noexcept { + if (b == 0) + throw b; + + co_await returnOne(); +} + +Task c_ShouldNotDiag(const int a, const int b) { + if (b == 0) + throw Evil{}; + + co_await returnOne(); +} + +Task c_ShouldDiag(const int a, const int b) noexcept { + // CHECK-MESSAGES: :[[@LINE-1]]:12: warning: an exception may be thrown in function 'c_ShouldDiag' which should not throw exceptions + if (b == 0) + throw Evil{}; + + co_await returnOne(); +} + +Task d_ShouldNotDiag(const int a, const int b) { + co_await returnOne(); +} + +Task d_ShouldDiag(const int a, const int b) noexcept { + // CHECK-MESSAGES: :[[@LINE-1]]:18: warning: an exception may be thrown in function 'd_ShouldDiag' which should not throw exceptions + co_await returnOne(); +} + +Task e_ShouldNotDiag(const int a, const int b) { + co_await returnOne(); +} + +Task e_ShouldDiag(const int a, const int b) noexcept { + // CHECK-MESSAGES: :[[@LINE-1]]:25: warning: an exception may be thrown in function 'e_ShouldDiag' which should not throw exceptions + co_await returnOne(); +} + +Task f_ShouldNotDiag(const int a, const int b) { + co_await returnOne(); +} + +Task f_ShouldDiag(const int a, const int b) noexcept { + // CHECK-MESSAGES: :[[@LINE-1]]:32: warning: an exception may be thrown in function 'f_ShouldDiag' which should not throw exceptions + co_await returnOne(); +} + +Task g_ShouldNotDiag(const int a, + const int b) { + co_await returnOne(); +} + +Task g_ShouldDiag(const int a, + const int b) noexcept { + // CHECK-MESSAGES: :[[@LINE-2]]:39: warning: an exception may be thrown in function 'g_ShouldDiag' which should not throw exceptions + co_await returnOne(); +} + +Task h_ShouldNotDiag(const int a, + const int b) { + co_await returnOne(); +} + +Task +h_ShouldDiag(const int a, const int b) noexcept { + // CHECK-MESSAGES: :[[@LINE-1]]:1: warning: an exception may be thrown in function 'h_ShouldDiag' which should not throw exceptions + co_await returnOne(); +} + +} // namespace coawait + +} // namespace function + +namespace lambda { + +namespace coreturn { + +const auto a_ShouldNotDiag = [](const int a, const int b) -> Task { + if (b == 0) + throw b; + + co_return a / b; +}; + +const auto b_ShouldNotDiag = [](const int a, + const int b) noexcept -> Task { + if (b == 0) + throw b; + + co_return a / b; +}; + +const auto c_ShouldNotDiag = [](const int a, const int b) -> Task { + if (b == 0) + throw Evil{}; + + co_return a / b; +}; + +const auto c_ShouldDiag = [](const int a, const int b) noexcept -> Task { + // CHECK-MESSAGES: :[[@LINE-1]]:27: warning: an exception may be thrown in function 'operator()' which should not throw exceptions + if (b == 0) + throw Evil{}; + + co_return a / b; +}; + +const auto d_ShouldNotDiag = [](const int a, const int b) -> Task { + co_return a / b; +}; + +const auto d_ShouldDiag = [](const int a, + const int b) noexcept -> Task { + // CHECK-MESSAGES: :[[@LINE-2]]:27: warning: an exception may be thrown in function 'operator()' which should not throw exceptions + co_return a / b; +}; + +const auto e_ShouldNotDiag = [](const int a, + const int b) -> Task { + co_return a / b; +}; + +const auto e_ShouldDiag = [](const int a, + const int b) noexcept -> Task { + // CHECK-MESSAGES: :[[@LINE-2]]:27: warning: an exception may be thrown in function 'operator()' which should not throw exceptions + co_return a / b; +}; + +const auto f_ShouldNotDiag = [](const int a, + const int b) -> Task { + co_return a / b; +}; + +const auto f_ShouldDiag = + [](const int a, const int b) noexcept -> Task { + // CHECK-MESSAGES: :[[@LINE-1]]:5: warning: an exception may be thrown in function 'operator()' which should not throw exceptions + co_return a / b; +}; + +const auto g_ShouldNotDiag = + [](const int a, const int b) -> Task { + co_return a / b; +}; + +const auto g_ShouldDiag = + [](const int a, + const int b) noexcept -> Task { + // CHECK-MESSAGES: :[[@LINE-2]]:5: warning: an exception may be thrown in function 'operator()' which should not throw exceptions + co_return a / b; +}; + +const auto h_ShouldNotDiag = + [](const int a, + const int b) -> Task { + co_return a / b; +}; + +const auto h_ShouldDiag = + [](const int a, + const int b) noexcept -> Task { + // CHECK-MESSAGES: :[[@LINE-2]]:5: warning: an exception may be thrown in function 'operator()' which should not throw exceptions + co_return a / b; +}; + +} // namespace coreturn + +namespace coyield { + +const auto a_ShouldNotDiag = [](const int a, const int b) -> Task { + if (b == 0) + throw b; + + co_yield a / b; +}; + +const auto b_ShouldNotDiag = [](const int a, + const int b) noexcept -> Task { + if (b == 0) + throw b; + + co_yield a / b; +}; + +const auto c_ShouldNotDiag = [](const int a, const int b) -> Task { + if (b == 0) + throw Evil{}; + + co_yield a / b; +}; + +const auto c_ShouldDiag = [](const int a, const int b) noexcept -> Task { + // CHECK-MESSAGES: :[[@LINE-1]]:27: warning: an exception may be thrown in function 'operator()' which should not throw exceptions + if (b == 0) + throw Evil{}; + + co_yield a / b; +}; + +const auto d_ShouldNotDiag = [](const int a, const int b) -> Task { + co_yield a / b; +}; + +const auto d_ShouldDiag = [](const int a, + const int b) noexcept -> Task { + // CHECK-MESSAGES: :[[@LINE-2]]:27: warning: an exception may be thrown in function 'operator()' which should not throw exceptions + co_yield a / b; +}; + +const auto e_ShouldNotDiag = [](const int a, + const int b) -> Task { + co_yield a / b; +}; + +const auto e_ShouldDiag = [](const int a, + const int b) noexcept -> Task { + // CHECK-MESSAGES: :[[@LINE-2]]:27: warning: an exception may be thrown in function 'operator()' which should not throw exceptions + co_yield a / b; +}; + +const auto f_ShouldNotDiag = [](const int a, + const int b) -> Task { + co_yield a / b; +}; + +const auto f_ShouldDiag = + [](const int a, const int b) noexcept -> Task { + // CHECK-MESSAGES: :[[@LINE-1]]:5: warning: an exception may be thrown in function 'operator()' which should not throw exceptions + co_yield a / b; +}; + +const auto g_ShouldNotDiag = + [](const int a, const int b) -> Task { + co_yield a / b; +}; + +const auto g_ShouldDiag = + [](const int a, + const int b) noexcept -> Task { + // CHECK-MESSAGES: :[[@LINE-2]]:5: warning: an exception may be thrown in function 'operator()' which should not throw exceptions + co_yield a / b; +}; + +const auto h_ShouldNotDiag = + [](const int a, + const int b) -> Task { + co_yield a / b; +}; + +const auto h_ShouldDiag = + [](const int a, + const int b) noexcept -> Task { + // CHECK-MESSAGES: :[[@LINE-2]]:5: warning: an exception may be thrown in function 'operator()' which should not throw exceptions + co_yield a / b; +}; + +} // namespace coyield + +namespace coawait { + +const auto a_ShouldNotDiag = [](const int a, const int b) -> Task { + if (b == 0) + throw b; + + co_await returnOne(); +}; + +const auto b_ShouldNotDiag = [](const int a, + const int b) noexcept -> Task { + if (b == 0) + throw b; + + co_await returnOne(); +}; + +const auto c_ShouldNotDiag = [](const int a, const int b) -> Task { + if (b == 0) + throw Evil{}; + + co_await returnOne(); +}; + +const auto c_ShouldDiag = [](const int a, const int b) noexcept -> Task { + // CHECK-MESSAGES: :[[@LINE-1]]:27: warning: an exception may be thrown in function 'operator()' which should not throw exceptions + if (b == 0) + throw Evil{}; + + co_await returnOne(); +}; + +const auto d_ShouldNotDiag = [](const int a, const int b) -> Task { + co_await returnOne(); +}; + +const auto d_ShouldDiag = [](const int a, + const int b) noexcept -> Task { + // CHECK-MESSAGES: :[[@LINE-2]]:27: warning: an exception may be thrown in function 'operator()' which should not throw exceptions + co_await returnOne(); +}; + +const auto e_ShouldNotDiag = [](const int a, + const int b) -> Task { + co_await returnOne(); +}; + +const auto e_ShouldDiag = [](const int a, + const int b) noexcept -> Task { + // CHECK-MESSAGES: :[[@LINE-2]]:27: warning: an exception may be thrown in function 'operator()' which should not throw exceptions + co_await returnOne(); +}; + +const auto f_ShouldNotDiag = [](const int a, + const int b) -> Task { + co_await returnOne(); +}; + +const auto f_ShouldDiag = + [](const int a, const int b) noexcept -> Task { + // CHECK-MESSAGES: :[[@LINE-1]]:5: warning: an exception may be thrown in function 'operator()' which should not throw exceptions + co_await returnOne(); +}; + +const auto g_ShouldNotDiag = + [](const int a, const int b) -> Task { + co_await returnOne(); +}; + +const auto g_ShouldDiag = + [](const int a, + const int b) noexcept -> Task { + // CHECK-MESSAGES: :[[@LINE-2]]:5: warning: an exception may be thrown in function 'operator()' which should not throw exceptions + co_await returnOne(); +}; + +const auto h_ShouldNotDiag = + [](const int a, + const int b) -> Task { + co_await returnOne(); +}; + +const auto h_ShouldDiag = + [](const int a, + const int b) noexcept -> Task { + // CHECK-MESSAGES: :[[@LINE-2]]:5: warning: an exception may be thrown in function 'operator()' which should not throw exceptions + co_await returnOne(); +}; + +} // namespace coawait + +} // namespace lambda diff --git a/clang-tools-extra/test/clang-tidy/checkers/bugprone/unique-ptr-array-mismatch.cpp b/clang-tools-extra/test/clang-tidy/checkers/bugprone/unique-ptr-array-mismatch.cpp new file mode 100644 index 0000000000000..494e83dce3720 --- /dev/null +++ b/clang-tools-extra/test/clang-tidy/checkers/bugprone/unique-ptr-array-mismatch.cpp @@ -0,0 +1,127 @@ +// RUN: %check_clang_tidy %s bugprone-unique-ptr-array-mismatch %t + +namespace std { + +template struct default_delete {}; +template struct default_delete {}; + +template> +class unique_ptr { +public: + explicit unique_ptr(T* p) noexcept; + unique_ptr(T* p, Deleter d1 ) noexcept; +}; + +template +class unique_ptr { +public: + template + explicit unique_ptr(U p) noexcept; + template + unique_ptr(U p, Deleter d1) noexcept; +}; + +} // namespace std + +struct A {}; + +using PtrT = std::unique_ptr; +using PtrTArr = std::unique_ptr; + +void f1() { + std::unique_ptr P1{new int}; + std::unique_ptr P2{new int[10]}; + // CHECK-MESSAGES: :[[@LINE-1]]:27: warning: unique pointer to non-array is initialized with array [bugprone-unique-ptr-array-mismatch] + // CHECK-FIXES: std::unique_ptr P2{new int[10]}; + // clang-format off + std::unique_ptr< int > P3{new int[10]}; + // CHECK-MESSAGES: :[[@LINE-1]]:31: warning: unique pointer to non-array is initialized with array [bugprone-unique-ptr-array-mismatch] + // CHECK-FIXES: std::unique_ptr< int[] > P3{new int[10]}; + // clang-format on + std::unique_ptr P4(new int[10]); + // CHECK-MESSAGES: :[[@LINE-1]]:27: warning: unique pointer to non-array is initialized with array [bugprone-unique-ptr-array-mismatch] + // CHECK-FIXES: std::unique_ptr P4(new int[10]); + new std::unique_ptr(new int[10]); + // CHECK-MESSAGES: :[[@LINE-1]]:28: warning: unique pointer to non-array is initialized with array [bugprone-unique-ptr-array-mismatch] + std::unique_ptr P5(new int[10]); + + A deleter; + std::unique_ptr P6(new int[10], deleter); + std::unique_ptr P7(new int[10]); + std::default_delete def_del; + std::unique_ptr> P8(new int[10], def_del); + + new PtrT(new A[10]); + // CHECK-MESSAGES: :[[@LINE-1]]:12: warning: unique pointer to non-array is initialized with array [bugprone-unique-ptr-array-mismatch] + new PtrTArr(new A[10]); +} + +void f2() { + std::unique_ptr P1(new A); + std::unique_ptr P2(new A[10]); + // CHECK-MESSAGES: :[[@LINE-1]]:25: warning: unique pointer to non-array is initialized with array [bugprone-unique-ptr-array-mismatch] + // CHECK-FIXES: std::unique_ptr P2(new A[10]); + std::unique_ptr P3(new A[10]); +} + +void f3() { + std::unique_ptr P1{new int}, P2{new int[10]}, P3{new int[10]}; + // CHECK-MESSAGES: :[[@LINE-1]]:40: warning: unique pointer to non-array is initialized with array [bugprone-unique-ptr-array-mismatch] + // CHECK-MESSAGES: :[[@LINE-2]]:57: warning: unique pointer to non-array is initialized with array [bugprone-unique-ptr-array-mismatch] +} + +struct S { + std::unique_ptr P1; + std::unique_ptr P2{new int[10]}; + // CHECK-MESSAGES: :[[@LINE-1]]:27: warning: unique pointer to non-array is initialized with array [bugprone-unique-ptr-array-mismatch] + std::unique_ptr P3{new int}, P4{new int[10]}; + // CHECK-MESSAGES: :[[@LINE-1]]:40: warning: unique pointer to non-array is initialized with array [bugprone-unique-ptr-array-mismatch] + S() : P1{new int[10]} {} + // CHECK-MESSAGES: :[[@LINE-1]]:12: warning: unique pointer to non-array is initialized with array [bugprone-unique-ptr-array-mismatch] +}; + +void f_parm(std::unique_ptr); + +void f4() { + f_parm(std::unique_ptr{new int[10]}); + // CHECK-MESSAGES: :[[@LINE-1]]:31: warning: unique pointer to non-array is initialized with array [bugprone-unique-ptr-array-mismatch] +} + +std::unique_ptr f_ret() { + return std::unique_ptr(new int[10]); + // CHECK-MESSAGES: :[[@LINE-1]]:31: warning: unique pointer to non-array is initialized with array [bugprone-unique-ptr-array-mismatch] +} + +template +void f_tmpl() { + std::unique_ptr P1{new T[10]}; + // CHECK-MESSAGES: :[[@LINE-1]]:25: warning: unique pointer to non-array is initialized with array [bugprone-unique-ptr-array-mismatch] + // CHECK-FIXES: std::unique_ptr P1{new T[10]}; +} + +void f5() { + f_tmpl(); +} + +template +void f_tmpl_1() { + std::unique_ptr P1{new T[10]}; + // FIXME_CHECK-MESSAGES: :[[@LINE-1]]:25: warning: unique pointer to non-array is initialized with array [bugprone-unique-ptr-array-mismatch] + // FIXME_CHECK-FIXES: std::unique_ptr P1{new T[10]}; +} + +#define CHAR_PTR_TYPE std::unique_ptr +#define CHAR_PTR_VAR(X) \ + X { new char[10] } +#define CHAR_PTR_INIT(X, Y) \ + std::unique_ptr X { Y } + +void f6() { + CHAR_PTR_TYPE P1{new char[10]}; + // CHECK-MESSAGES: :[[@LINE-1]]:20: warning: unique pointer to non-array is initialized with array [bugprone-unique-ptr-array-mismatch] + std::unique_ptr CHAR_PTR_VAR(P2); + // CHECK-MESSAGES: :[[@LINE-1]]:25: warning: unique pointer to non-array is initialized with array [bugprone-unique-ptr-array-mismatch] + // CHECK-FIXES: std::unique_ptr CHAR_PTR_VAR(P2); + CHAR_PTR_INIT(P3, new char[10]); + // CHECK-MESSAGES: :[[@LINE-1]]:21: warning: unique pointer to non-array is initialized with array [bugprone-unique-ptr-array-mismatch] +} diff --git a/clang-tools-extra/test/clang-tidy/checkers/cert/uppercase-literal-suffix-integer.cpp b/clang-tools-extra/test/clang-tidy/checkers/cert/uppercase-literal-suffix-integer.cpp index 0dc06df4f18b4..6fa700bf06d4f 100644 --- a/clang-tools-extra/test/clang-tidy/checkers/cert/uppercase-literal-suffix-integer.cpp +++ b/clang-tools-extra/test/clang-tidy/checkers/cert/uppercase-literal-suffix-integer.cpp @@ -31,7 +31,7 @@ void integer_suffix() { // CHECK-MESSAGES: :[[@LINE-1]]:30: warning: integer literal has suffix 'l', which is not uppercase // CHECK-MESSAGES-NEXT: static constexpr auto v5 = 1l; // CHECK-MESSAGES-NEXT: ^~ - // CHECK-MESSAGES-NEXT: {{^ *}}L{{$}} + // CHECK-MESSAGES-NEXT: {{^ *| *}}L{{$}} // CHECK-FIXES: static constexpr auto v5 = 1L; static_assert(is_same::value, ""); static_assert(v5 == 1, ""); @@ -46,7 +46,7 @@ void integer_suffix() { // CHECK-MESSAGES: :[[@LINE-1]]:30: warning: integer literal has suffix 'll', which is not uppercase // CHECK-MESSAGES-NEXT: static constexpr auto v7 = 1ll; // CHECK-MESSAGES-NEXT: ^~~ - // CHECK-MESSAGES-NEXT: {{^ *}}LL{{$}} + // CHECK-MESSAGES-NEXT: {{^ *| *}}LL{{$}} // CHECK-FIXES: static constexpr auto v7 = 1LL; static_assert(is_same::value, ""); static_assert(v7 == 1, ""); @@ -79,7 +79,7 @@ void integer_suffix() { // CHECK-MESSAGES: :[[@LINE-1]]:31: warning: integer literal has suffix 'lu', which is not uppercase // CHECK-MESSAGES-NEXT: static constexpr auto v13 = 1lu; // CHECK-MESSAGES-NEXT: ^~~ - // CHECK-MESSAGES-NEXT: {{^ *}}LU{{$}} + // CHECK-MESSAGES-NEXT: {{^ *| *}}LU{{$}} // CHECK-FIXES: static constexpr auto v13 = 1LU; static_assert(is_same::value, ""); static_assert(v13 == 1, ""); @@ -88,7 +88,7 @@ void integer_suffix() { // CHECK-MESSAGES: :[[@LINE-1]]:31: warning: integer literal has suffix 'Lu', which is not uppercase // CHECK-MESSAGES-NEXT: static constexpr auto v14 = 1Lu; // CHECK-MESSAGES-NEXT: ^~~ - // CHECK-MESSAGES-NEXT: {{^ *}}LU{{$}} + // CHECK-MESSAGES-NEXT: {{^ *| *}}LU{{$}} // CHECK-FIXES: static constexpr auto v14 = 1LU; static_assert(is_same::value, ""); static_assert(v14 == 1, ""); @@ -97,7 +97,7 @@ void integer_suffix() { // CHECK-MESSAGES: :[[@LINE-1]]:31: warning: integer literal has suffix 'lU', which is not uppercase // CHECK-MESSAGES-NEXT: static constexpr auto v15 = 1lU; // CHECK-MESSAGES-NEXT: ^~~ - // CHECK-MESSAGES-NEXT: {{^ *}}LU{{$}} + // CHECK-MESSAGES-NEXT: {{^ *| *}}LU{{$}} // CHECK-FIXES: static constexpr auto v15 = 1LU; static_assert(is_same::value, ""); static_assert(v15 == 1, ""); @@ -130,7 +130,7 @@ void integer_suffix() { // CHECK-MESSAGES: :[[@LINE-1]]:31: warning: integer literal has suffix 'llu', which is not uppercase // CHECK-MESSAGES-NEXT: static constexpr auto v21 = 1llu; // CHECK-MESSAGES-NEXT: ^~~~ - // CHECK-MESSAGES-NEXT: {{^ *}}LLU{{$}} + // CHECK-MESSAGES-NEXT: {{^ *| *}}LLU{{$}} // CHECK-FIXES: static constexpr auto v21 = 1LLU; static_assert(is_same::value, ""); static_assert(v21 == 1, ""); @@ -139,7 +139,7 @@ void integer_suffix() { // CHECK-MESSAGES: :[[@LINE-1]]:31: warning: integer literal has suffix 'LLu', which is not uppercase // CHECK-MESSAGES-NEXT: static constexpr auto v22 = 1LLu; // CHECK-MESSAGES-NEXT: ^~~~ - // CHECK-MESSAGES-NEXT: {{^ *}}LLU{{$}} + // CHECK-MESSAGES-NEXT: {{^ *| *}}LLU{{$}} // CHECK-FIXES: static constexpr auto v22 = 1LLU; static_assert(is_same::value, ""); static_assert(v22 == 1, ""); @@ -148,7 +148,7 @@ void integer_suffix() { // CHECK-MESSAGES: :[[@LINE-1]]:31: warning: integer literal has suffix 'llU', which is not uppercase // CHECK-MESSAGES-NEXT: static constexpr auto v23 = 1llU; // CHECK-MESSAGES-NEXT: ^~~~ - // CHECK-MESSAGES-NEXT: {{^ *}}LLU{{$}} + // CHECK-MESSAGES-NEXT: {{^ *| *}}LLU{{$}} // CHECK-FIXES: static constexpr auto v23 = 1LLU; static_assert(is_same::value, ""); static_assert(v23 == 1, ""); diff --git a/clang-tools-extra/test/clang-tidy/checkers/misc/Inputs/bar.h b/clang-tools-extra/test/clang-tidy/checkers/misc/Inputs/bar.h new file mode 100644 index 0000000000000..06e7156ea1254 --- /dev/null +++ b/clang-tools-extra/test/clang-tidy/checkers/misc/Inputs/bar.h @@ -0,0 +1,4 @@ +#pragma once +#include "baz.h" +#include "private.h" +int bar(); diff --git a/clang-tools-extra/test/clang-tidy/checkers/misc/Inputs/baz.h b/clang-tools-extra/test/clang-tidy/checkers/misc/Inputs/baz.h new file mode 100644 index 0000000000000..042e9ca404012 --- /dev/null +++ b/clang-tools-extra/test/clang-tidy/checkers/misc/Inputs/baz.h @@ -0,0 +1,2 @@ +#pragma once +int baz(); diff --git a/clang-tools-extra/test/clang-tidy/checkers/misc/Inputs/foo.h b/clang-tools-extra/test/clang-tidy/checkers/misc/Inputs/foo.h new file mode 100644 index 0000000000000..a158d915f0a1e --- /dev/null +++ b/clang-tools-extra/test/clang-tidy/checkers/misc/Inputs/foo.h @@ -0,0 +1,2 @@ +#pragma once +void foo(); diff --git a/clang-tools-extra/test/clang-tidy/checkers/misc/Inputs/private.h b/clang-tools-extra/test/clang-tidy/checkers/misc/Inputs/private.h new file mode 100644 index 0000000000000..318c9f06c0e2b --- /dev/null +++ b/clang-tools-extra/test/clang-tidy/checkers/misc/Inputs/private.h @@ -0,0 +1,2 @@ +// IWYU pragma: private, include "public.h" +int foobar(); diff --git a/clang-tools-extra/test/clang-tidy/checkers/misc/include-cleaner.cpp b/clang-tools-extra/test/clang-tidy/checkers/misc/include-cleaner.cpp new file mode 100644 index 0000000000000..0f4c7a8f4ad1c --- /dev/null +++ b/clang-tools-extra/test/clang-tidy/checkers/misc/include-cleaner.cpp @@ -0,0 +1,17 @@ +// RUN: %check_clang_tidy %s misc-include-cleaner %t -- -- -I%S/Inputs -isystem%S/system +#include "bar.h" +// CHECK-FIXES: {{^}}#include "baz.h"{{$}} +#include "foo.h" +// CHECK-MESSAGES: :[[@LINE-1]]:1: warning: included header "foo.h" is not used directly [misc-include-cleaner] +// CHECK-FIXES: {{^}} +// CHECK-FIXES: {{^}}#include {{$}} +#include +// CHECK-MESSAGES: :[[@LINE-1]]:1: warning: included header is not used directly [misc-include-cleaner] +// CHECK-FIXES: {{^}} +int BarResult = bar(); +int BazResult = baz(); +// CHECK-MESSAGES: :[[@LINE-1]]:17: warning: no header providing "baz.h" is directly included [misc-include-cleaner] +std::string HelloString; +// CHECK-MESSAGES: :[[@LINE-1]]:6: warning: no header providing is directly included [misc-include-cleaner] +int FooBarResult = foobar(); +// CHECK-MESSAGES: :[[@LINE-1]]:20: warning: no header providing "public.h" is directly included [misc-include-cleaner] diff --git a/clang-tools-extra/test/clang-tidy/checkers/misc/system/string.h b/clang-tools-extra/test/clang-tidy/checkers/misc/system/string.h new file mode 100644 index 0000000000000..9b23b425350ee --- /dev/null +++ b/clang-tools-extra/test/clang-tidy/checkers/misc/system/string.h @@ -0,0 +1,2 @@ +#pragma once +namespace std { class string {}; } diff --git a/clang-tools-extra/test/clang-tidy/checkers/misc/system/vector.h b/clang-tools-extra/test/clang-tidy/checkers/misc/system/vector.h new file mode 100644 index 0000000000000..2d7bb696bfd91 --- /dev/null +++ b/clang-tools-extra/test/clang-tidy/checkers/misc/system/vector.h @@ -0,0 +1,4 @@ +#pragma once +#include + +namespace std { class vector {}; } diff --git a/clang-tools-extra/test/clang-tidy/checkers/readability/uppercase-literal-suffix-float16.cpp b/clang-tools-extra/test/clang-tidy/checkers/readability/uppercase-literal-suffix-float16.cpp index a790597fcff51..46d7bc1347d0d 100644 --- a/clang-tools-extra/test/clang-tidy/checkers/readability/uppercase-literal-suffix-float16.cpp +++ b/clang-tools-extra/test/clang-tidy/checkers/readability/uppercase-literal-suffix-float16.cpp @@ -9,7 +9,7 @@ void float16_normal_literals() { // CHECK-MESSAGES: :[[@LINE-1]]:31: warning: floating point literal has suffix 'f16', which is not uppercase // CHECK-MESSAGES-NEXT: static constexpr auto v14 = 1.f16; // CHECK-MESSAGES-NEXT: ^ ~ - // CHECK-MESSAGES-NEXT: {{^ *}}F16{{$}} + // CHECK-MESSAGES-NEXT: F16{{$}} // CHECK-FIXES: static constexpr auto v14 = 1.F16; static_assert(is_same::value, ""); static_assert(v14 == 1.F16, ""); @@ -18,7 +18,7 @@ void float16_normal_literals() { // CHECK-MESSAGES: :[[@LINE-1]]:31: warning: floating point literal has suffix 'f16', which is not uppercase // CHECK-MESSAGES-NEXT: static constexpr auto v15 = 1.e0f16; // CHECK-MESSAGES-NEXT: ^ ~ - // CHECK-MESSAGES-NEXT: {{^ *}}F16{{$}} + // CHECK-MESSAGES-NEXT: F16{{$}} // CHECK-FIXES: static constexpr auto v15 = 1.e0F16; static_assert(is_same::value, ""); static_assert(v15 == 1.F16, ""); @@ -39,7 +39,7 @@ void float16_hexadecimal_literals() { // CHECK-MESSAGES: :[[@LINE-1]]:31: warning: floating point literal has suffix 'f16', which is not uppercase // CHECK-MESSAGES-NEXT: static constexpr auto v13 = 0xfp0f16; // CHECK-MESSAGES-NEXT: ^ ~ - // CHECK-MESSAGES-NEXT: {{^ *}}F16{{$}} + // CHECK-MESSAGES-NEXT: F16{{$}} // CHECK-FIXES: static constexpr auto v13 = 0xfp0F16; static_assert(is_same::value, ""); static_assert(v13 == 0xfp0F16, ""); diff --git a/clang-tools-extra/test/clang-tidy/checkers/readability/uppercase-literal-suffix-floating-point-opencl-half.cpp b/clang-tools-extra/test/clang-tidy/checkers/readability/uppercase-literal-suffix-floating-point-opencl-half.cpp index 8cea2a4d827cb..ef905da6e9f95 100644 --- a/clang-tools-extra/test/clang-tidy/checkers/readability/uppercase-literal-suffix-floating-point-opencl-half.cpp +++ b/clang-tools-extra/test/clang-tidy/checkers/readability/uppercase-literal-suffix-floating-point-opencl-half.cpp @@ -14,14 +14,14 @@ void floating_point_half_suffix() { // CHECK-MESSAGES: :[[@LINE-1]]:20: warning: floating point literal has suffix 'h', which is not uppercase // CHECK-MESSAGES-NEXT: static half v2 = 1.h; // CHECK-MESSAGES-NEXT: ^ ~ - // CHECK-MESSAGES-NEXT: {{^ *}}H{{$}} + // CHECK-MESSAGES-NEXT: H{{$}} // CHECK-HIXES: static half v2 = 1.H; static half v3 = 1.e0h; // CHECK-MESSAGES: :[[@LINE-1]]:20: warning: floating point literal has suffix 'h', which is not uppercase // CHECK-MESSAGES-NEXT: static half v3 = 1.e0h; // CHECK-MESSAGES-NEXT: ^ ~ - // CHECK-MESSAGES-NEXT: {{^ *}}H{{$}} + // CHECK-MESSAGES-NEXT: H{{$}} // CHECK-HIXES: static half v3 = 1.e0H; static half v4 = 1.H; // OK. diff --git a/clang-tools-extra/test/clang-tidy/checkers/readability/uppercase-literal-suffix-floating-point.cpp b/clang-tools-extra/test/clang-tidy/checkers/readability/uppercase-literal-suffix-floating-point.cpp index a0dcc38c8b231..d9f5bfbe3aa38 100644 --- a/clang-tools-extra/test/clang-tidy/checkers/readability/uppercase-literal-suffix-floating-point.cpp +++ b/clang-tools-extra/test/clang-tidy/checkers/readability/uppercase-literal-suffix-floating-point.cpp @@ -20,7 +20,7 @@ void floating_point_suffix() { // CHECK-MESSAGES: :[[@LINE-1]]:30: warning: floating point literal has suffix 'f', which is not uppercase // CHECK-MESSAGES-NEXT: static constexpr auto v2 = 1.f; // CHECK-MESSAGES-NEXT: ^ ~ - // CHECK-MESSAGES-NEXT: {{^ *}}F{{$}} + // CHECK-MESSAGES-NEXT: F{{$}} // CHECK-FIXES: static constexpr auto v2 = 1.F; static_assert(is_same::value, ""); static_assert(v2 == 1.0F, ""); @@ -29,7 +29,7 @@ void floating_point_suffix() { // CHECK-MESSAGES: :[[@LINE-1]]:30: warning: floating point literal has suffix 'f', which is not uppercase // CHECK-MESSAGES-NEXT: static constexpr auto v3 = 1.e0f; // CHECK-MESSAGES-NEXT: ^ ~ - // CHECK-MESSAGES-NEXT: {{^ *}}F{{$}} + // CHECK-MESSAGES-NEXT: F{{$}} // CHECK-FIXES: static constexpr auto v3 = 1.e0F; static_assert(is_same::value, ""); static_assert(v3 == 1.0F, ""); @@ -48,7 +48,7 @@ void floating_point_suffix() { // CHECK-MESSAGES: :[[@LINE-1]]:30: warning: floating point literal has suffix 'l', which is not uppercase // CHECK-MESSAGES-NEXT: static constexpr auto v6 = 1.l; // CHECK-MESSAGES-NEXT: ^ ~ - // CHECK-MESSAGES-NEXT: {{^ *}}L{{$}} + // CHECK-MESSAGES-NEXT: L{{$}} // CHECK-FIXES: static constexpr auto v6 = 1.L; static_assert(is_same::value, ""); static_assert(v6 == 1., ""); @@ -57,7 +57,7 @@ void floating_point_suffix() { // CHECK-MESSAGES: :[[@LINE-1]]:30: warning: floating point literal has suffix 'l', which is not uppercase // CHECK-MESSAGES-NEXT: static constexpr auto v7 = 1.e0l; // CHECK-MESSAGES-NEXT: ^ ~ - // CHECK-MESSAGES-NEXT: {{^ *}}L{{$}} + // CHECK-MESSAGES-NEXT: L{{$}} // CHECK-FIXES: static constexpr auto v7 = 1.e0L; static_assert(is_same::value, ""); static_assert(v7 == 1., ""); @@ -76,7 +76,7 @@ void floating_point_suffix() { // CHECK-MESSAGES: :[[@LINE-1]]:31: warning: floating point literal has suffix 'q', which is not uppercase // CHECK-MESSAGES-NEXT: static constexpr auto v10 = 1.q; // CHECK-MESSAGES-NEXT: ^ ~ - // CHECK-MESSAGES-NEXT: {{^ *}}Q{{$}} + // CHECK-MESSAGES-NEXT: Q{{$}} // CHECK-FIXES: static constexpr auto v10 = 1.Q; static_assert(is_same::value, ""); static_assert(v10 == 1., ""); @@ -85,7 +85,7 @@ void floating_point_suffix() { // CHECK-MESSAGES: :[[@LINE-1]]:31: warning: floating point literal has suffix 'q', which is not uppercase // CHECK-MESSAGES-NEXT: static constexpr auto v11 = 1.e0q; // CHECK-MESSAGES-NEXT: ^ ~ - // CHECK-MESSAGES-NEXT: {{^ *}}Q{{$}} + // CHECK-MESSAGES-NEXT: Q{{$}} // CHECK-FIXES: static constexpr auto v11 = 1.e0Q; static_assert(is_same::value, ""); static_assert(v11 == 1., ""); @@ -106,7 +106,7 @@ void floating_point_complex_suffix() { // CHECK-MESSAGES: :[[@LINE-1]]:31: warning: floating point literal has suffix 'i', which is not uppercase // CHECK-MESSAGES-NEXT: static constexpr auto v14 = 1.i; // CHECK-MESSAGES-NEXT: ^ ~ - // CHECK-MESSAGES-NEXT: {{^ *}}I{{$}} + // CHECK-MESSAGES-NEXT: I{{$}} // CHECK-FIXES: static constexpr auto v14 = 1.I; static_assert(is_same::value, ""); static_assert(v14 == 1.I, ""); @@ -115,7 +115,7 @@ void floating_point_complex_suffix() { // CHECK-MESSAGES: :[[@LINE-1]]:31: warning: floating point literal has suffix 'i', which is not uppercase // CHECK-MESSAGES-NEXT: static constexpr auto v15 = 1.e0i; // CHECK-MESSAGES-NEXT: ^ ~ - // CHECK-MESSAGES-NEXT: {{^ *}}I{{$}} + // CHECK-MESSAGES-NEXT: I{{$}} // CHECK-FIXES: static constexpr auto v15 = 1.e0I; static_assert(is_same::value, ""); static_assert(v15 == 1.I, ""); @@ -134,7 +134,7 @@ void floating_point_complex_suffix() { // CHECK-MESSAGES: :[[@LINE-1]]:31: warning: floating point literal has suffix 'j', which is not uppercase // CHECK-MESSAGES-NEXT: static constexpr auto v18 = 1.j; // CHECK-MESSAGES-NEXT: ^ ~ - // CHECK-MESSAGES-NEXT: {{^ *}}J{{$}} + // CHECK-MESSAGES-NEXT: J{{$}} // CHECK-FIXES: static constexpr auto v18 = 1.J; static_assert(is_same::value, ""); static_assert(v18 == 1.J, ""); @@ -143,7 +143,7 @@ void floating_point_complex_suffix() { // CHECK-MESSAGES: :[[@LINE-1]]:31: warning: floating point literal has suffix 'j', which is not uppercase // CHECK-MESSAGES-NEXT: static constexpr auto v19 = 1.e0j; // CHECK-MESSAGES-NEXT: ^ ~ - // CHECK-MESSAGES-NEXT: {{^ *}}J{{$}} + // CHECK-MESSAGES-NEXT: J{{$}} // CHECK-FIXES: static constexpr auto v19 = 1.e0J; static_assert(is_same::value, ""); static_assert(v19 == 1.J, ""); @@ -163,7 +163,7 @@ void macros() { // CHECK-MESSAGES: :[[@LINE-1]]:42: warning: floating point literal has suffix 'f', which is not uppercase // CHECK-MESSAGES-NEXT: static constexpr auto m0 = PASSTHROUGH(1.f); // CHECK-MESSAGES-NEXT: ^ ~ - // CHECK-MESSAGES-NEXT: {{^ *}}F{{$}} + // CHECK-MESSAGES-NEXT: F{{$}} // CHECK-FIXES: static constexpr auto m0 = PASSTHROUGH(1.F); static_assert(is_same::value, ""); static_assert(m0 == 1.0F, ""); diff --git a/clang-tools-extra/test/clang-tidy/checkers/readability/uppercase-literal-suffix-hexadecimal-floating-point.cpp b/clang-tools-extra/test/clang-tidy/checkers/readability/uppercase-literal-suffix-hexadecimal-floating-point.cpp index 57d24fb5712c4..72077153fb718 100644 --- a/clang-tools-extra/test/clang-tidy/checkers/readability/uppercase-literal-suffix-hexadecimal-floating-point.cpp +++ b/clang-tools-extra/test/clang-tidy/checkers/readability/uppercase-literal-suffix-hexadecimal-floating-point.cpp @@ -16,7 +16,7 @@ void floating_point_suffix() { // CHECK-MESSAGES: :[[@LINE-1]]:30: warning: floating point literal has suffix 'f', which is not uppercase // CHECK-MESSAGES-NEXT: static constexpr auto v1 = 0xfp0f; // CHECK-MESSAGES-NEXT: ^ ~ - // CHECK-MESSAGES-NEXT: {{^ *}}F{{$}} + // CHECK-MESSAGES-NEXT: F{{$}} // CHECK-FIXES: static constexpr auto v1 = 0xfp0F; static_assert(is_same::value, ""); static_assert(v1 == 15, ""); @@ -29,7 +29,7 @@ void floating_point_suffix() { // CHECK-MESSAGES: :[[@LINE-1]]:30: warning: floating point literal has suffix 'f', which is not uppercase // CHECK-MESSAGES-NEXT: static constexpr auto v3 = 0xfP0f; // CHECK-MESSAGES-NEXT: ^ ~ - // CHECK-MESSAGES-NEXT: {{^ *}}F{{$}} + // CHECK-MESSAGES-NEXT: F{{$}} // CHECK-FIXES: static constexpr auto v3 = 0xfP0F; static_assert(is_same::value, ""); static_assert(v3 == 15, ""); @@ -42,7 +42,7 @@ void floating_point_suffix() { // CHECK-MESSAGES: :[[@LINE-1]]:30: warning: floating point literal has suffix 'f', which is not uppercase // CHECK-MESSAGES-NEXT: static constexpr auto v5 = 0xFP0f; // CHECK-MESSAGES-NEXT: ^ ~ - // CHECK-MESSAGES-NEXT: {{^ *}}F{{$}} + // CHECK-MESSAGES-NEXT: F{{$}} // CHECK-FIXES: static constexpr auto v5 = 0xFP0F; static_assert(is_same::value, ""); static_assert(v5 == 15, ""); @@ -55,7 +55,7 @@ void floating_point_suffix() { // CHECK-MESSAGES: :[[@LINE-1]]:30: warning: floating point literal has suffix 'f', which is not uppercase // CHECK-MESSAGES-NEXT: static constexpr auto v7 = 0xFp0f; // CHECK-MESSAGES-NEXT: ^ ~ - // CHECK-MESSAGES-NEXT: {{^ *}}F{{$}} + // CHECK-MESSAGES-NEXT: F{{$}} // CHECK-FIXES: static constexpr auto v7 = 0xFp0F; static_assert(is_same::value, ""); static_assert(v7 == 15, ""); @@ -70,7 +70,7 @@ void floating_point_suffix() { // CHECK-MESSAGES: :[[@LINE-1]]:30: warning: floating point literal has suffix 'l', which is not uppercase // CHECK-MESSAGES-NEXT: static constexpr auto v9 = 0xfp0l; // CHECK-MESSAGES-NEXT: ^ ~ - // CHECK-MESSAGES-NEXT: {{^ *}}L{{$}} + // CHECK-MESSAGES-NEXT: L{{$}} // CHECK-FIXES: static constexpr auto v9 = 0xfp0L; static_assert(is_same::value, ""); static_assert(v9 == 0xfp0, ""); @@ -85,7 +85,7 @@ void floating_point_suffix() { // CHECK-MESSAGES: :[[@LINE-1]]:31: warning: floating point literal has suffix 'q', which is not uppercase // CHECK-MESSAGES-NEXT: static constexpr auto v11 = 0xfp0q; // CHECK-MESSAGES-NEXT: ^ ~ - // CHECK-MESSAGES-NEXT: {{^ *}}Q{{$}} + // CHECK-MESSAGES-NEXT: Q{{$}} // CHECK-FIXES: static constexpr auto v11 = 0xfp0Q; static_assert(is_same::value, ""); static_assert(v11 == 0xfp0, ""); @@ -102,7 +102,7 @@ void floating_point_complex_suffix() { // CHECK-MESSAGES: :[[@LINE-1]]:31: warning: floating point literal has suffix 'i', which is not uppercase // CHECK-MESSAGES-NEXT: static constexpr auto v14 = 0xfp0i; // CHECK-MESSAGES-NEXT: ^ ~ - // CHECK-MESSAGES-NEXT: {{^ *}}I{{$}} + // CHECK-MESSAGES-NEXT: I{{$}} // CHECK-FIXES: static constexpr auto v14 = 0xfp0I; static_assert(is_same::value, ""); static_assert(v14 == 0xfp0I, ""); @@ -117,7 +117,7 @@ void floating_point_complex_suffix() { // CHECK-MESSAGES: :[[@LINE-1]]:31: warning: floating point literal has suffix 'j', which is not uppercase // CHECK-MESSAGES-NEXT: static constexpr auto v18 = 0xfp0j; // CHECK-MESSAGES-NEXT: ^ ~ - // CHECK-MESSAGES-NEXT: {{^ *}}J{{$}} + // CHECK-MESSAGES-NEXT: J{{$}} // CHECK-FIXES: static constexpr auto v18 = 0xfp0J; static_assert(is_same::value, ""); static_assert(v18 == 0xfp0J, ""); @@ -133,7 +133,7 @@ void macros() { // CHECK-MESSAGES: :[[@LINE-1]]:42: warning: floating point literal has suffix 'f', which is not uppercase // CHECK-MESSAGES-NEXT: static constexpr auto m0 = PASSTHROUGH(0x0p0f); // CHECK-MESSAGES-NEXT: ^ ~ - // CHECK-MESSAGES-NEXT: {{^ *}}F{{$}} + // CHECK-MESSAGES-NEXT: F{{$}} // CHECK-FIXES: static constexpr auto m0 = PASSTHROUGH(0x0p0F); static_assert(is_same::value, ""); static_assert(m0 == 0x0p0F, ""); diff --git a/clang-tools-extra/test/clang-tidy/checkers/readability/uppercase-literal-suffix-integer-custom-list.cpp b/clang-tools-extra/test/clang-tidy/checkers/readability/uppercase-literal-suffix-integer-custom-list.cpp index c787cab1fc4a7..5ee09527999eb 100644 --- a/clang-tools-extra/test/clang-tidy/checkers/readability/uppercase-literal-suffix-integer-custom-list.cpp +++ b/clang-tools-extra/test/clang-tidy/checkers/readability/uppercase-literal-suffix-integer-custom-list.cpp @@ -22,7 +22,7 @@ void integer_suffix() { // CHECK-MESSAGES: :[[@LINE-1]]:30: warning: integer literal has suffix 'l', which is not uppercase // CHECK-MESSAGES-NEXT: static constexpr auto v5 = 1l; // CHECK-MESSAGES-NEXT: ^~ - // CHECK-MESSAGES-NEXT: {{^ *}}L{{$}} + // CHECK-MESSAGES-NEXT: L{{$}} // CHECK-FIXES: static constexpr auto v5 = 1L; static_assert(is_same::value, ""); static_assert(v5 == 1, ""); @@ -47,7 +47,7 @@ void integer_suffix() { // CHECK-MESSAGES: :[[@LINE-1]]:30: warning: integer literal has suffix 'ul', which is not uppercase // CHECK-MESSAGES-NEXT: static constexpr auto v9 = 1ul; // CHECK-MESSAGES-NEXT: ^~~ - // CHECK-MESSAGES-NEXT: {{^ *}}uL{{$}} + // CHECK-MESSAGES-NEXT: uL{{$}} // CHECK-FIXES: static constexpr auto v9 = 1uL; static_assert(is_same::value, ""); static_assert(v9 == 1, ""); @@ -60,7 +60,7 @@ void integer_suffix() { // CHECK-MESSAGES: :[[@LINE-1]]:31: warning: integer literal has suffix 'Ul', which is not uppercase // CHECK-MESSAGES-NEXT: static constexpr auto v11 = 1Ul; // CHECK-MESSAGES-NEXT: ^~~ - // CHECK-MESSAGES-NEXT: {{^ *}}uL{{$}} + // CHECK-MESSAGES-NEXT: uL{{$}} // CHECK-FIXES: static constexpr auto v11 = 1uL; static_assert(is_same::value, ""); static_assert(v11 == 1, ""); @@ -69,7 +69,7 @@ void integer_suffix() { // CHECK-MESSAGES: :[[@LINE-1]]:31: warning: integer literal has suffix 'UL', which is not uppercase // CHECK-MESSAGES-NEXT: static constexpr auto v12 = 1UL; // CHECK-MESSAGES-NEXT: ^~~ - // CHECK-MESSAGES-NEXT: {{^ *}}uL{{$}} + // CHECK-MESSAGES-NEXT: uL{{$}} // CHECK-FIXES: static constexpr auto v12 = 1uL; static_assert(is_same::value, ""); static_assert(v12 == 1, ""); diff --git a/clang-tools-extra/test/clang-tidy/checkers/readability/uppercase-literal-suffix-integer-ms.cpp b/clang-tools-extra/test/clang-tidy/checkers/readability/uppercase-literal-suffix-integer-ms.cpp index fe3269f2c506d..7ac4a7502e7b7 100644 --- a/clang-tools-extra/test/clang-tidy/checkers/readability/uppercase-literal-suffix-integer-ms.cpp +++ b/clang-tools-extra/test/clang-tidy/checkers/readability/uppercase-literal-suffix-integer-ms.cpp @@ -21,7 +21,7 @@ void integer_suffix() { // CHECK-MESSAGES: :[[@LINE-1]]:30: warning: integer literal has suffix 'i32', which is not uppercase // CHECK-MESSAGES-NEXT: static constexpr auto v3 = 1i32; // CHECK-MESSAGES-NEXT: ^~ - // CHECK-MESSAGES-NEXT: {{^ *}}I32{{$}} + // CHECK-MESSAGES-NEXT: I32{{$}} // CHECK-FIXES: static constexpr auto v3 = 1I32; static_assert(is_same::value, ""); static_assert(v3 == 1I32, ""); @@ -36,7 +36,7 @@ void integer_suffix() { // CHECK-MESSAGES: :[[@LINE-1]]:30: warning: integer literal has suffix 'i64', which is not uppercase // CHECK-MESSAGES-NEXT: static constexpr auto v5 = 1i64; // CHECK-MESSAGES-NEXT: ^~ - // CHECK-MESSAGES-NEXT: {{^ *}}I64{{$}} + // CHECK-MESSAGES-NEXT: I64{{$}} // CHECK-FIXES: static constexpr auto v5 = 1I64; static_assert(is_same::value, ""); static_assert(v5 == 1I64, ""); @@ -51,7 +51,7 @@ void integer_suffix() { // CHECK-MESSAGES: :[[@LINE-1]]:30: warning: integer literal has suffix 'i16', which is not uppercase // CHECK-MESSAGES-NEXT: static constexpr auto v7 = 1i16; // CHECK-MESSAGES-NEXT: ^~ - // CHECK-MESSAGES-NEXT: {{^ *}}I16{{$}} + // CHECK-MESSAGES-NEXT: I16{{$}} // CHECK-FIXES: static constexpr auto v7 = 1I16; static_assert(is_same::value, ""); static_assert(v7 == 1I16, ""); @@ -66,7 +66,7 @@ void integer_suffix() { // CHECK-MESSAGES: :[[@LINE-1]]:30: warning: integer literal has suffix 'i8', which is not uppercase // CHECK-MESSAGES-NEXT: static constexpr auto v9 = 1i8; // CHECK-MESSAGES-NEXT: ^~ - // CHECK-MESSAGES-NEXT: {{^ *}}I8{{$}} + // CHECK-MESSAGES-NEXT: I8{{$}} // CHECK-FIXES: static constexpr auto v9 = 1I8; static_assert(is_same::value, ""); static_assert(v9 == 1I8, ""); diff --git a/clang-tools-extra/test/clang-tidy/checkers/readability/uppercase-literal-suffix-integer.cpp b/clang-tools-extra/test/clang-tidy/checkers/readability/uppercase-literal-suffix-integer.cpp index c03ccc23992fc..084d9f68e0b5e 100644 --- a/clang-tools-extra/test/clang-tidy/checkers/readability/uppercase-literal-suffix-integer.cpp +++ b/clang-tools-extra/test/clang-tidy/checkers/readability/uppercase-literal-suffix-integer.cpp @@ -21,7 +21,7 @@ void integer_suffix() { // CHECK-MESSAGES: :[[@LINE-1]]:30: warning: integer literal has suffix 'u', which is not uppercase // CHECK-MESSAGES-NEXT: static constexpr auto v3 = 1u; // CHECK-MESSAGES-NEXT: ^~ - // CHECK-MESSAGES-NEXT: {{^ *}}U{{$}} + // CHECK-MESSAGES-NEXT: U{{$}} // CHECK-FIXES: static constexpr auto v3 = 1U; static_assert(is_same::value, ""); static_assert(v3 == 1, ""); @@ -36,7 +36,7 @@ void integer_suffix() { // CHECK-MESSAGES: :[[@LINE-1]]:30: warning: integer literal has suffix 'l', which is not uppercase // CHECK-MESSAGES-NEXT: static constexpr auto v5 = 1l; // CHECK-MESSAGES-NEXT: ^~ - // CHECK-MESSAGES-NEXT: {{^ *}}L{{$}} + // CHECK-MESSAGES-NEXT: L{{$}} // CHECK-FIXES: static constexpr auto v5 = 1L; static_assert(is_same::value, ""); static_assert(v5 == 1, ""); @@ -51,7 +51,7 @@ void integer_suffix() { // CHECK-MESSAGES: :[[@LINE-1]]:30: warning: integer literal has suffix 'll', which is not uppercase // CHECK-MESSAGES-NEXT: static constexpr auto v7 = 1ll; // CHECK-MESSAGES-NEXT: ^~~ - // CHECK-MESSAGES-NEXT: {{^ *}}LL{{$}} + // CHECK-MESSAGES-NEXT: LL{{$}} // CHECK-FIXES: static constexpr auto v7 = 1LL; static_assert(is_same::value, ""); static_assert(v7 == 1, ""); @@ -66,7 +66,7 @@ void integer_suffix() { // CHECK-MESSAGES: :[[@LINE-1]]:30: warning: integer literal has suffix 'ul', which is not uppercase // CHECK-MESSAGES-NEXT: static constexpr auto v9 = 1ul; // CHECK-MESSAGES-NEXT: ^~~ - // CHECK-MESSAGES-NEXT: {{^ *}}UL{{$}} + // CHECK-MESSAGES-NEXT: UL{{$}} // CHECK-FIXES: static constexpr auto v9 = 1UL; static_assert(is_same::value, ""); static_assert(v9 == 1, ""); @@ -75,7 +75,7 @@ void integer_suffix() { // CHECK-MESSAGES: :[[@LINE-1]]:31: warning: integer literal has suffix 'uL', which is not uppercase // CHECK-MESSAGES-NEXT: static constexpr auto v10 = 1uL; // CHECK-MESSAGES-NEXT: ^~~ - // CHECK-MESSAGES-NEXT: {{^ *}}UL{{$}} + // CHECK-MESSAGES-NEXT: UL{{$}} // CHECK-FIXES: static constexpr auto v10 = 1UL; static_assert(is_same::value, ""); static_assert(v10 == 1, ""); @@ -84,7 +84,7 @@ void integer_suffix() { // CHECK-MESSAGES: :[[@LINE-1]]:31: warning: integer literal has suffix 'Ul', which is not uppercase // CHECK-MESSAGES-NEXT: static constexpr auto v11 = 1Ul; // CHECK-MESSAGES-NEXT: ^~~ - // CHECK-MESSAGES-NEXT: {{^ *}}UL{{$}} + // CHECK-MESSAGES-NEXT: UL{{$}} // CHECK-FIXES: static constexpr auto v11 = 1UL; static_assert(is_same::value, ""); static_assert(v11 == 1, ""); @@ -99,7 +99,7 @@ void integer_suffix() { // CHECK-MESSAGES: :[[@LINE-1]]:31: warning: integer literal has suffix 'lu', which is not uppercase // CHECK-MESSAGES-NEXT: static constexpr auto v13 = 1lu; // CHECK-MESSAGES-NEXT: ^~~ - // CHECK-MESSAGES-NEXT: {{^ *}}LU{{$}} + // CHECK-MESSAGES-NEXT: LU{{$}} // CHECK-FIXES: static constexpr auto v13 = 1LU; static_assert(is_same::value, ""); static_assert(v13 == 1, ""); @@ -108,7 +108,7 @@ void integer_suffix() { // CHECK-MESSAGES: :[[@LINE-1]]:31: warning: integer literal has suffix 'Lu', which is not uppercase // CHECK-MESSAGES-NEXT: static constexpr auto v14 = 1Lu; // CHECK-MESSAGES-NEXT: ^~~ - // CHECK-MESSAGES-NEXT: {{^ *}}LU{{$}} + // CHECK-MESSAGES-NEXT: LU{{$}} // CHECK-FIXES: static constexpr auto v14 = 1LU; static_assert(is_same::value, ""); static_assert(v14 == 1, ""); @@ -117,7 +117,7 @@ void integer_suffix() { // CHECK-MESSAGES: :[[@LINE-1]]:31: warning: integer literal has suffix 'lU', which is not uppercase // CHECK-MESSAGES-NEXT: static constexpr auto v15 = 1lU; // CHECK-MESSAGES-NEXT: ^~~ - // CHECK-MESSAGES-NEXT: {{^ *}}LU{{$}} + // CHECK-MESSAGES-NEXT: LU{{$}} // CHECK-FIXES: static constexpr auto v15 = 1LU; static_assert(is_same::value, ""); static_assert(v15 == 1, ""); @@ -132,7 +132,7 @@ void integer_suffix() { // CHECK-MESSAGES: :[[@LINE-1]]:31: warning: integer literal has suffix 'ull', which is not uppercase // CHECK-MESSAGES-NEXT: static constexpr auto v17 = 1ull; // CHECK-MESSAGES-NEXT: ^~~~ - // CHECK-MESSAGES-NEXT: {{^ *}}ULL{{$}} + // CHECK-MESSAGES-NEXT: ULL{{$}} // CHECK-FIXES: static constexpr auto v17 = 1ULL; static_assert(is_same::value, ""); static_assert(v17 == 1, ""); @@ -141,7 +141,7 @@ void integer_suffix() { // CHECK-MESSAGES: :[[@LINE-1]]:31: warning: integer literal has suffix 'uLL', which is not uppercase // CHECK-MESSAGES-NEXT: static constexpr auto v18 = 1uLL; // CHECK-MESSAGES-NEXT: ^~~~ - // CHECK-MESSAGES-NEXT: {{^ *}}ULL{{$}} + // CHECK-MESSAGES-NEXT: ULL{{$}} // CHECK-FIXES: static constexpr auto v18 = 1ULL; static_assert(is_same::value, ""); static_assert(v18 == 1, ""); @@ -150,7 +150,7 @@ void integer_suffix() { // CHECK-MESSAGES: :[[@LINE-1]]:31: warning: integer literal has suffix 'Ull', which is not uppercase // CHECK-MESSAGES-NEXT: static constexpr auto v19 = 1Ull; // CHECK-MESSAGES-NEXT: ^~~~ - // CHECK-MESSAGES-NEXT: {{^ *}}ULL{{$}} + // CHECK-MESSAGES-NEXT: ULL{{$}} // CHECK-FIXES: static constexpr auto v19 = 1ULL; static_assert(is_same::value, ""); static_assert(v19 == 1, ""); @@ -165,7 +165,7 @@ void integer_suffix() { // CHECK-MESSAGES: :[[@LINE-1]]:31: warning: integer literal has suffix 'llu', which is not uppercase // CHECK-MESSAGES-NEXT: static constexpr auto v21 = 1llu; // CHECK-MESSAGES-NEXT: ^~~~ - // CHECK-MESSAGES-NEXT: {{^ *}}LLU{{$}} + // CHECK-MESSAGES-NEXT: LLU{{$}} // CHECK-FIXES: static constexpr auto v21 = 1LLU; static_assert(is_same::value, ""); static_assert(v21 == 1, ""); @@ -174,7 +174,7 @@ void integer_suffix() { // CHECK-MESSAGES: :[[@LINE-1]]:31: warning: integer literal has suffix 'LLu', which is not uppercase // CHECK-MESSAGES-NEXT: static constexpr auto v22 = 1LLu; // CHECK-MESSAGES-NEXT: ^~~~ - // CHECK-MESSAGES-NEXT: {{^ *}}LLU{{$}} + // CHECK-MESSAGES-NEXT: LLU{{$}} // CHECK-FIXES: static constexpr auto v22 = 1LLU; static_assert(is_same::value, ""); static_assert(v22 == 1, ""); @@ -183,7 +183,7 @@ void integer_suffix() { // CHECK-MESSAGES: :[[@LINE-1]]:31: warning: integer literal has suffix 'llU', which is not uppercase // CHECK-MESSAGES-NEXT: static constexpr auto v23 = 1llU; // CHECK-MESSAGES-NEXT: ^~~~ - // CHECK-MESSAGES-NEXT: {{^ *}}LLU{{$}} + // CHECK-MESSAGES-NEXT: LLU{{$}} // CHECK-FIXES: static constexpr auto v23 = 1LLU; static_assert(is_same::value, ""); static_assert(v23 == 1, ""); @@ -200,7 +200,7 @@ void integer_complex_suffix() { // CHECK-MESSAGES: :[[@LINE-1]]:31: warning: integer literal has suffix 'i', which is not uppercase // CHECK-MESSAGES-NEXT: static constexpr auto v25 = 1i; // CHECK-MESSAGES-NEXT: ^~ - // CHECK-MESSAGES-NEXT: {{^ *}}I{{$}} + // CHECK-MESSAGES-NEXT: I{{$}} // CHECK-FIXES: static constexpr auto v25 = 1I; static_assert(is_same::value, ""); static_assert(v25 == 1I, ""); @@ -215,7 +215,7 @@ void integer_complex_suffix() { // CHECK-MESSAGES: :[[@LINE-1]]:31: warning: integer literal has suffix 'j', which is not uppercase // CHECK-MESSAGES-NEXT: static constexpr auto v27 = 1j; // CHECK-MESSAGES-NEXT: ^~ - // CHECK-MESSAGES-NEXT: {{^ *}}J{{$}} + // CHECK-MESSAGES-NEXT: J{{$}} // CHECK-FIXES: static constexpr auto v27 = 1J; static_assert(is_same::value, ""); static_assert(v27 == 1J, ""); @@ -231,7 +231,7 @@ void macros() { // CHECK-MESSAGES: :[[@LINE-1]]:42: warning: integer literal has suffix 'u', which is not uppercase // CHECK-MESSAGES-NEXT: static constexpr auto m0 = PASSTHROUGH(1u); // CHECK-MESSAGES-NEXT: ^~ - // CHECK-MESSAGES-NEXT: {{^ *}}U{{$}} + // CHECK-MESSAGES-NEXT: U{{$}} // CHECK-FIXES: static constexpr auto m0 = PASSTHROUGH(1U); static_assert(is_same::value, ""); static_assert(m0 == 1, ""); diff --git a/clang-tools-extra/unittests/clang-tidy/CMakeLists.txt b/clang-tools-extra/unittests/clang-tidy/CMakeLists.txt index 336b773206832..3304924d39757 100644 --- a/clang-tools-extra/unittests/clang-tidy/CMakeLists.txt +++ b/clang-tools-extra/unittests/clang-tidy/CMakeLists.txt @@ -15,12 +15,14 @@ endif() get_filename_component(CLANG_LINT_SOURCE_DIR ${CMAKE_CURRENT_SOURCE_DIR}/../../clang-tidy REALPATH) include_directories(${CLANG_LINT_SOURCE_DIR}) +include_directories(BEFORE "${CMAKE_CURRENT_SOURCE_DIR}/../../include-cleaner/include") add_extra_unittest(ClangTidyTests AddConstTest.cpp ClangTidyDiagnosticConsumerTest.cpp ClangTidyOptionsTest.cpp DeclRefExprUtilsTest.cpp + IncludeCleanerTest.cpp IncludeInserterTest.cpp GlobListTest.cpp GoogleModuleTest.cpp @@ -46,12 +48,14 @@ clang_target_link_libraries(ClangTidyTests clangTooling clangToolingCore clangTransformer + clangIncludeCleaner ) target_link_libraries(ClangTidyTests PRIVATE clangTidy clangTidyAndroidModule clangTidyGoogleModule + clangTidyMiscModule clangTidyLLVMModule clangTidyModernizeModule clangTidyObjCModule diff --git a/clang-tools-extra/unittests/clang-tidy/IncludeCleanerTest.cpp b/clang-tools-extra/unittests/clang-tidy/IncludeCleanerTest.cpp new file mode 100644 index 0000000000000..db048f10a0c15 --- /dev/null +++ b/clang-tools-extra/unittests/clang-tidy/IncludeCleanerTest.cpp @@ -0,0 +1,236 @@ +//===--- IncludeCleanerTest.cpp - clang-tidy -----------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#include "ClangTidyDiagnosticConsumer.h" +#include "ClangTidyOptions.h" +#include "ClangTidyTest.h" +#include "misc/IncludeCleanerCheck.h" +#include "llvm/ADT/SmallString.h" +#include "llvm/ADT/StringRef.h" +#include "llvm/Support/FormatVariadic.h" +#include "llvm/Support/Path.h" +#include "llvm/Support/Regex.h" +#include "gtest/gtest.h" +#include + +#include +#include + +using namespace clang::tidy::misc; + +namespace clang { +namespace tidy { +namespace test { +namespace { + +std::string +appendPathFileSystemIndependent(std::initializer_list Segments) { + llvm::SmallString<32> Result; + for (const auto &Segment : Segments) + llvm::sys::path::append(Result, llvm::sys::path::Style::native, Segment); + return std::string(Result.str()); +} + +TEST(IncludeCleanerCheckTest, BasicUnusedIncludes) { + const char *PreCode = R"( +#include "bar.h" +#include +#include "bar.h" +)"; + const char *PostCode = "\n"; + + std::vector Errors; + EXPECT_EQ(PostCode, runCheckOnCode( + PreCode, &Errors, "file.cpp", std::nullopt, + ClangTidyOptions(), {{"bar.h", ""}, {"vector", ""}})); +} + +TEST(IncludeCleanerCheckTest, SuppressUnusedIncludes) { + const char *PreCode = R"( +#include "bar.h" +#include "foo/qux.h" +#include "baz/qux/qux.h" +#include +)"; + + const char *PostCode = R"( +#include "bar.h" +#include "foo/qux.h" +#include +)"; + + std::vector Errors; + ClangTidyOptions Opts; + Opts.CheckOptions["IgnoreHeaders"] = llvm::StringRef{llvm::formatv( + "bar.h;{0};{1};vector", + llvm::Regex::escape(appendPathFileSystemIndependent({"foo", "qux.h"})), + llvm::Regex::escape(appendPathFileSystemIndependent({"baz", "qux"})))}; + EXPECT_EQ( + PostCode, + runCheckOnCode( + PreCode, &Errors, "file.cpp", std::nullopt, Opts, + {{"bar.h", ""}, + {"vector", ""}, + {appendPathFileSystemIndependent({"foo", "qux.h"}), ""}, + {appendPathFileSystemIndependent({"baz", "qux", "qux.h"}), ""}})); +} + +TEST(IncludeCleanerCheckTest, BasicMissingIncludes) { + const char *PreCode = R"( +#include "bar.h" + +int BarResult = bar(); +int BazResult = baz(); +)"; + const char *PostCode = R"( +#include "bar.h" +#include "baz.h" + +int BarResult = bar(); +int BazResult = baz(); +)"; + + std::vector Errors; + EXPECT_EQ(PostCode, + runCheckOnCode( + PreCode, &Errors, "file.cpp", std::nullopt, ClangTidyOptions(), + {{"bar.h", R"(#pragma once + #include "baz.h" + int bar(); + )"}, + {"baz.h", R"(#pragma once + int baz(); + )"}})); +} + +TEST(IncludeCleanerCheckTest, SuppressMissingIncludes) { + const char *PreCode = R"( +#include "bar.h" + +int BarResult = bar(); +int BazResult = baz(); +int QuxResult = qux(); +)"; + + ClangTidyOptions Opts; + Opts.CheckOptions["IgnoreHeaders"] = llvm::StringRef{ + "baz.h;" + + llvm::Regex::escape(appendPathFileSystemIndependent({"foo", "qux.h"}))}; + std::vector Errors; + EXPECT_EQ(PreCode, runCheckOnCode( + PreCode, &Errors, "file.cpp", std::nullopt, Opts, + {{"bar.h", R"(#pragma once + #include "baz.h" + #include "foo/qux.h" + int bar(); + )"}, + {"baz.h", R"(#pragma once + int baz(); + )"}, + {appendPathFileSystemIndependent({"foo", "qux.h"}), + R"(#pragma once + int qux(); + )"}})); +} + +TEST(IncludeCleanerCheckTest, SystemMissingIncludes) { + const char *PreCode = R"( +#include + +std::string HelloString; +std::vector Vec; +)"; + const char *PostCode = R"( +#include +#include + +std::string HelloString; +std::vector Vec; +)"; + + std::vector Errors; + EXPECT_EQ(PostCode, + runCheckOnCode( + PreCode, &Errors, "file.cpp", std::nullopt, ClangTidyOptions(), + {{"string", R"(#pragma once + namespace std { class string {}; } + )"}, + {"vector", R"(#pragma once + #include + namespace std { class vector {}; } + )"}})); +} + +TEST(IncludeCleanerCheckTest, PragmaMissingIncludes) { + const char *PreCode = R"( +#include "bar.h" + +int BarResult = bar(); +int FooBarResult = foobar(); +)"; + const char *PostCode = R"( +#include "bar.h" +#include "public.h" + +int BarResult = bar(); +int FooBarResult = foobar(); +)"; + + std::vector Errors; + EXPECT_EQ(PostCode, + runCheckOnCode( + PreCode, &Errors, "file.cpp", std::nullopt, ClangTidyOptions(), + {{"bar.h", R"(#pragma once + #include "private.h" + int bar(); + )"}, + {"private.h", R"(#pragma once + // IWYU pragma: private, include "public.h" + int foobar(); + )"}})); +} + +TEST(IncludeCleanerCheckTest, DeclFromMacroExpansion) { + const char *PreCode = R"( +#include "foo.h" + +DECLARE(myfunc) { + int a; +} +)"; + + std::vector Errors; + EXPECT_EQ(PreCode, + runCheckOnCode( + PreCode, &Errors, "file.cpp", std::nullopt, ClangTidyOptions(), + {{"foo.h", + R"(#pragma once + #define DECLARE(X) void X() + )"}})); + + PreCode = R"( +#include "foo.h" + +DECLARE { + int a; +} +)"; + + EXPECT_EQ(PreCode, + runCheckOnCode( + PreCode, &Errors, "file.cpp", std::nullopt, ClangTidyOptions(), + {{"foo.h", + R"(#pragma once + #define DECLARE void myfunc() + )"}})); +} + +} // namespace +} // namespace test +} // namespace tidy +} // namespace clang diff --git a/clang/cmake/caches/Fuchsia-stage2.cmake b/clang/cmake/caches/Fuchsia-stage2.cmake index 8f5aa21be6fb8..b4bc8cb4eb64e 100644 --- a/clang/cmake/caches/Fuchsia-stage2.cmake +++ b/clang/cmake/caches/Fuchsia-stage2.cmake @@ -11,6 +11,7 @@ set(LLVM_ENABLE_RUNTIMES "compiler-rt;libcxx;libcxxabi;libunwind" CACHE STRING " set(LLVM_ENABLE_BACKTRACES OFF CACHE BOOL "") set(LLVM_ENABLE_DIA_SDK OFF CACHE BOOL "") +set(LLVM_ENABLE_HTTPLIB ON CACHE BOOL "") set(LLVM_ENABLE_LIBCXX ON CACHE BOOL "") set(LLVM_ENABLE_LIBEDIT OFF CACHE BOOL "") set(LLVM_ENABLE_LLD ON CACHE BOOL "") @@ -296,6 +297,7 @@ set(LLVM_TOOLCHAIN_TOOLS llvm-ar llvm-cov llvm-cxxfilt + llvm-debuginfod llvm-debuginfod-find llvm-dlltool ${LLVM_DRIVER_TARGET} diff --git a/clang/cmake/caches/Fuchsia.cmake b/clang/cmake/caches/Fuchsia.cmake index 5596cc61359cd..bd882647312b9 100644 --- a/clang/cmake/caches/Fuchsia.cmake +++ b/clang/cmake/caches/Fuchsia.cmake @@ -32,8 +32,10 @@ set(_FUCHSIA_BOOTSTRAP_PASSTHROUGH LLVM_ENABLE_LIBXML2 LibXml2_ROOT LLVM_ENABLE_CURL + LLVM_ENABLE_HTTPLIB CURL_ROOT OpenSSL_ROOT + httplib_ROOT FUCHSIA_ENABLE_LLDB LLDB_ENABLE_CURSES LLDB_ENABLE_LIBEDIT diff --git a/clang/docs/InternalsManual.rst b/clang/docs/InternalsManual.rst index 3ba8ed8c0ef6d..1698e11d7b3e2 100644 --- a/clang/docs/InternalsManual.rst +++ b/clang/docs/InternalsManual.rst @@ -2798,12 +2798,12 @@ and then the semantic handling of the attribute. Parsing of the attribute is determined by the various syntactic forms attributes can take, such as GNU, C++11, and Microsoft style attributes, as well as other information provided by the table definition of the attribute. Ultimately, the -parsed representation of an attribute object is an ``ParsedAttr`` object. +parsed representation of an attribute object is a ``ParsedAttr`` object. These parsed attributes chain together as a list of parsed attributes attached to a declarator or declaration specifier. The parsing of attributes is handled -automatically by Clang, except for attributes spelled as keywords. When -implementing a keyword attribute, the parsing of the keyword and creation of the -``ParsedAttr`` object must be done manually. +automatically by Clang, except for attributes spelled as so-called “custom” +keywords. When implementing a custom keyword attribute, the parsing of the +keyword and creation of the ``ParsedAttr`` object must be done manually. Eventually, ``Sema::ProcessDeclAttributeList()`` is called with a ``Decl`` and a ``ParsedAttr``, at which point the parsed attribute can be transformed @@ -2856,33 +2856,60 @@ may have a keyword spelling, as well as a C++11 spelling and a GNU spelling. An empty spelling list is also permissible and may be useful for attributes which are created implicitly. The following spellings are accepted: - ============ ================================================================ - Spelling Description - ============ ================================================================ - ``GNU`` Spelled with a GNU-style ``__attribute__((attr))`` syntax and - placement. - ``CXX11`` Spelled with a C++-style ``[[attr]]`` syntax with an optional - vendor-specific namespace. - ``C2x`` Spelled with a C-style ``[[attr]]`` syntax with an optional - vendor-specific namespace. - ``Declspec`` Spelled with a Microsoft-style ``__declspec(attr)`` syntax. - ``Keyword`` The attribute is spelled as a keyword, and required custom - parsing. - ``GCC`` Specifies two or three spellings: the first is a GNU-style - spelling, the second is a C++-style spelling with the ``gnu`` - namespace, and the third is an optional C-style spelling with - the ``gnu`` namespace. Attributes should only specify this - spelling for attributes supported by GCC. - ``Clang`` Specifies two or three spellings: the first is a GNU-style - spelling, the second is a C++-style spelling with the ``clang`` - namespace, and the third is an optional C-style spelling with - the ``clang`` namespace. By default, a C-style spelling is - provided. - ``Pragma`` The attribute is spelled as a ``#pragma``, and requires custom - processing within the preprocessor. If the attribute is meant to - be used by Clang, it should set the namespace to ``"clang"``. - Note that this spelling is not used for declaration attributes. - ============ ================================================================ + ================== ========================================================= + Spelling Description + ================== ========================================================= + ``GNU`` Spelled with a GNU-style ``__attribute__((attr))`` + syntax and placement. + ``CXX11`` Spelled with a C++-style ``[[attr]]`` syntax with an + optional vendor-specific namespace. + ``C2x`` Spelled with a C-style ``[[attr]]`` syntax with an + optional vendor-specific namespace. + ``Declspec`` Spelled with a Microsoft-style ``__declspec(attr)`` + syntax. + ``CustomKeyword`` The attribute is spelled as a keyword, and requires + custom parsing. + ``RegularKeyword`` The attribute is spelled as a keyword. It can be + used in exactly the places that the standard + ``[[attr]]`` syntax can be used, and appertains to + exactly the same thing that a standard attribute + would appertain to. Lexing and parsing of the keyword + are handled automatically. + ``GCC`` Specifies two or three spellings: the first is a + GNU-style spelling, the second is a C++-style spelling + with the ``gnu`` namespace, and the third is an optional + C-style spelling with the ``gnu`` namespace. Attributes + should only specify this spelling for attributes + supported by GCC. + ``Clang`` Specifies two or three spellings: the first is a + GNU-style spelling, the second is a C++-style spelling + with the ``clang`` namespace, and the third is an + optional C-style spelling with the ``clang`` namespace. + By default, a C-style spelling is provided. + ``Pragma`` The attribute is spelled as a ``#pragma``, and requires + custom processing within the preprocessor. If the + attribute is meant to be used by Clang, it should + set the namespace to ``"clang"``. Note that this + spelling is not used for declaration attributes. + ================== ========================================================= + +The C++ standard specifies that “any [non-standard attribute] that is not +recognized by the implementation is ignored” (``[dcl.attr.grammar]``). +The rule for C is similar. This makes ``CXX11`` and ``C2x`` spellings +unsuitable for attributes that affect the type system, that change the +binary interface of the code, or that have other similar semantic meaning. + +``RegularKeyword`` provides an alternative way of spelling such attributes. +It reuses the production rules for standard attributes, but it applies them +to plain keywords rather than to ``[[…]]`` sequences. Compilers that don't +recognize the keyword are likely to report an error of some kind. + +For example, the ``ArmStreaming`` function type attribute affects +both the type system and the binary interface of the function. +It cannot therefore be spelled ``[[arm::streaming]]``, since compilers +that don't understand ``arm::streaming`` would ignore it and miscompile +the code. ``ArmStreaming`` is instead spelled ``__arm_streaming``, but it +can appear wherever a hypothetical ``[[arm::streaming]]`` could appear. Subjects ~~~~~~~~ diff --git a/clang/docs/ReleaseNotes.rst b/clang/docs/ReleaseNotes.rst index 8a9dd04cda5bb..69ab645d49c23 100644 --- a/clang/docs/ReleaseNotes.rst +++ b/clang/docs/ReleaseNotes.rst @@ -314,6 +314,11 @@ Improvements to Clang's diagnostics is an incomplete type. (`#55175: `_, and fixes an incorrect mention of ``alignof`` in a diagnostic about ``alignas``). +- Clang will now show a margin with line numbers to the left of each line + of code it prints for diagnostics. This can be disabled using + ``-fno-diagnostics-show-line-numbers``. At the same time, the maximum + number of code lines it prints has been increased from 1 to 16. This + can be controlled using ``-fcaret-diagnostics-max-lines=``. Bug Fixes in This Version ------------------------- @@ -455,6 +460,9 @@ Bug Fixes in This Version - Fix crash when diagnosing default comparison method. (`#62791 `_) and (`#62102 `_). +- Fix crash when passing a braced initializer list to a parentehsized aggregate + initialization expression. + (`#63008 `_). Bug Fixes to Compiler Builtins ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -465,6 +473,10 @@ Bug Fixes to Attribute Support structs, unions, and scoped enums) were not properly ignored, resulting in misleading warning messages. Now, such attribute annotations are correctly ignored. (`#61660 `_) +- GNU attributes preceding C++ style attributes on templates were not properly + handled, resulting in compilation error. This has been corrected to match the + behavior exhibited by GCC, which permits mixed ordering of GNU and C++ + attributes. Bug Fixes to C++ Support ^^^^^^^^^^^^^^^^^^^^^^^^ diff --git a/clang/docs/UsersManual.rst b/clang/docs/UsersManual.rst index cee037a7ea89d..6b597242e3f93 100644 --- a/clang/docs/UsersManual.rst +++ b/clang/docs/UsersManual.rst @@ -575,6 +575,38 @@ output format of the diagnostics that it generates. [...]>>> +.. option:: -fcaret-diagnostics-max-lines: + + Controls how many lines of code clang prints for diagnostics. By default, + clang prints a maximum of 16 lines of code. + + +.. option:: -fdiagnostics-show-line-numbers: + + Controls whether clang will print a margin containing the line number on + the left of each line of code it prints for diagnostics. + + Default: + + :: + + test.cpp:5:1: error: 'main' must return 'int' + 5 | void main() {} + | ^~~~ + | int + + + With -fno-diagnostics-show-line-numbers: + + :: + + test.cpp:5:1: error: 'main' must return 'int' + void main() {} + ^~~~ + int + + + .. _cl_diag_warning_groups: Individual Warning Groups diff --git a/clang/docs/analyzer/checkers.rst b/clang/docs/analyzer/checkers.rst index e32f9c799240e..6494860915b93 100644 --- a/clang/docs/analyzer/checkers.rst +++ b/clang/docs/analyzer/checkers.rst @@ -2421,10 +2421,10 @@ For a more detailed description of configuration options, please see the :doc:`u alpha.unix ^^^^^^^^^^^ -.. _alpha-unix-StdCLibraryFunctionArgs: +.. _alpha-unix-StdCLibraryFunctions: -alpha.unix.StdCLibraryFunctionArgs (C) -"""""""""""""""""""""""""""""""""""""" +alpha.unix.StdCLibraryFunctions (C) +""""""""""""""""""""""""""""""""""" Check for calls of standard library functions that violate predefined argument constraints. For example, it is stated in the C standard that for the ``int isalnum(int ch)`` function the behavior is undefined if the value of ``ch`` is @@ -2457,6 +2457,12 @@ on standard library functions. Preconditions are checked, and when they are violated, a warning is emitted. Post conditions are added to the analysis, e.g. that the return value must be no greater than 255. +For example if an argument to a function must be in between 0 and 255, but the +value of the argument is unknown, the analyzer will conservatively assume that +it is in this interval. Similarly, if a function mustn't be called with a null +pointer and the null value of the argument can not be proven, the analyzer will +assume that it is non-null. + These are the possible checks on the values passed as function arguments: - The argument has an allowed range (or multiple ranges) of values. The checker can detect if a passed value is outside of the allowed range and show the @@ -2471,16 +2477,6 @@ These are the possible checks on the values passed as function arguments: checker can detect if the buffer size is too small and in optimal case show the size of the buffer and the values of the corresponding arguments. -If the user disables the checker then the argument violation warning is -suppressed. However, the assumption about the argument is still modeled. -For instance, if the argument to a function must be in between 0 and 255, -but the value of the argument is unknown, the analyzer will conservatively -assume that it is in this interval, even if warnings for this checker are -disabled. Similarly, if a function mustn't be called with a null pointer but it -is, analysis will stop on that execution path (similarly to a division by zero), -with or without a warning. If the null value of the argument can not be proven, -the analyzer will assume that it is non-null. - .. code-block:: c int test_alnum_symbolic(int x) { @@ -2493,6 +2489,13 @@ the analyzer will assume that it is non-null. return ret; } +Additionally to the argument and return value conditions, this checker also adds +state of the value ``errno`` if applicable to the analysis. Many system +functions set the ``errno`` value only if an error occurs (together with a +specific return value of the function), otherwise it becomes undefined. This +checker changes the analysis state to contain such information. This data is +used by other checkers, for example :ref:`alpha-unix-Errno`. + **Limitations** The checker can not always provide notes about the values of the arguments. @@ -2508,12 +2511,9 @@ range of the argument. **Parameters** The checker models functions (and emits diagnostics) from the C standard by -default. The ``apiModeling.StdCLibraryFunctions:ModelPOSIX`` option enables -modeling (and emit diagnostics) of additional functions that are defined in the -POSIX standard. This option is disabled by default. Note that this option -belongs to a separate built-in checker ``apiModeling.StdCLibraryFunctions`` and -can have effect on other checkers because it toggles modeling of the functions -in various aspects. +default. The ``ModelPOSIX`` option enables modeling (and emit diagnostics) of +additional functions that are defined in the POSIX standard. This option is +disabled by default. .. _alpha-unix-BlockInCriticalSection: @@ -2582,9 +2582,10 @@ pages of the functions and in the `POSIX standard (D)) { S.Diag(Attr.getLoc(), diag::warn_attribute_wrong_decl_type_str) - << Attr << "functions"; + << Attr << Attr.isRegularKeywordAttribute() << "functions"; return false; } return true; diff --git a/clang/examples/CallSuperAttribute/CallSuperAttrInfo.cpp b/clang/examples/CallSuperAttribute/CallSuperAttrInfo.cpp index 21460e4f6bd06..12d4c311586e6 100644 --- a/clang/examples/CallSuperAttribute/CallSuperAttrInfo.cpp +++ b/clang/examples/CallSuperAttribute/CallSuperAttrInfo.cpp @@ -169,7 +169,7 @@ struct CallSuperAttrInfo : public ParsedAttrInfo { const auto *TheMethod = dyn_cast_or_null(D); if (!TheMethod || !TheMethod->isVirtual()) { S.Diag(Attr.getLoc(), diag::warn_attribute_wrong_decl_type_str) - << Attr << "virtual functions"; + << Attr << Attr.isRegularKeywordAttribute() << "virtual functions"; return false; } MarkedMethods.insert(TheMethod); diff --git a/clang/include/clang/AST/DeclBase.h b/clang/include/clang/AST/DeclBase.h index f7d5b3a83141a..511afb1db5606 100644 --- a/clang/include/clang/AST/DeclBase.h +++ b/clang/include/clang/AST/DeclBase.h @@ -2602,14 +2602,6 @@ class DeclContext { void reconcileExternalVisibleStorage() const; bool LoadLexicalDeclsFromExternalStorage() const; - /// Makes a declaration visible within this context, but - /// suppresses searches for external declarations with the same - /// name. - /// - /// Analogous to makeDeclVisibleInContext, but for the exclusive - /// use of addDeclInternal(). - void makeDeclVisibleInContextInternal(NamedDecl *D); - StoredDeclsMap *CreateStoredDeclsMap(ASTContext &C) const; void loadLazyLocalLexicalLookups(); diff --git a/clang/include/clang/AST/StmtCXX.h b/clang/include/clang/AST/StmtCXX.h index 60fc3f3a63f49..8b4ef24ed376a 100644 --- a/clang/include/clang/AST/StmtCXX.h +++ b/clang/include/clang/AST/StmtCXX.h @@ -443,6 +443,17 @@ class CoroutineBodyStmt final NumParams); } + child_range childrenExclBody() { + return child_range(getStoredStmts() + SubStmt::Body + 1, + getStoredStmts() + SubStmt::FirstParamMove + NumParams); + } + + const_child_range childrenExclBody() const { + return const_child_range(getStoredStmts() + SubStmt::Body + 1, + getStoredStmts() + SubStmt::FirstParamMove + + NumParams); + } + static bool classof(const Stmt *T) { return T->getStmtClass() == CoroutineBodyStmtClass; } diff --git a/clang/include/clang/Analysis/FlowSensitive/ControlFlowContext.h b/clang/include/clang/Analysis/FlowSensitive/ControlFlowContext.h index f327011766069..bb36ed237c1e3 100644 --- a/clang/include/clang/Analysis/FlowSensitive/ControlFlowContext.h +++ b/clang/include/clang/Analysis/FlowSensitive/ControlFlowContext.h @@ -33,8 +33,7 @@ class ControlFlowContext { public: /// Builds a ControlFlowContext from a `FunctionDecl`. /// `Func.hasBody()` must be true, and `Func.isTemplated()` must be false. - static llvm::Expected build(const FunctionDecl &Func, - ASTContext &C); + static llvm::Expected build(const FunctionDecl &Func); /// Builds a ControlFlowContext from an AST node. `D` is the function in which /// `S` resides. `D.isTemplated()` must be false. diff --git a/clang/include/clang/Basic/Attr.td b/clang/include/clang/Basic/Attr.td index 8507e65137697..3fdd84d2b13b2 100644 --- a/clang/include/clang/Basic/Attr.td +++ b/clang/include/clang/Basic/Attr.td @@ -311,7 +311,20 @@ class C2x string Namespace = namespace; } -class Keyword : Spelling; +class Keyword + : Spelling { + bit HasOwnParseRules = hasOwnParseRules; +} + +// A keyword that can appear wherever a standard attribute can appear, +// and that appertains to whatever a standard attribute would appertain to. +// This is useful for things that affect semantics but that should otherwise +// be treated like standard attributes. +class RegularKeyword : Keyword {} + +// A keyword that has its own individual parsing rules. +class CustomKeyword : Keyword {} + class Pragma : Spelling { string Namespace = namespace; } @@ -709,13 +722,13 @@ def ArmBuiltinAlias : InheritableAttr, TargetSpecificAttr { } def Aligned : InheritableAttr { - let Spellings = [GCC<"aligned">, Declspec<"align">, Keyword<"alignas">, - Keyword<"_Alignas">]; + let Spellings = [GCC<"aligned">, Declspec<"align">, CustomKeyword<"alignas">, + CustomKeyword<"_Alignas">]; let Args = [AlignedArgument<"Alignment", 1>]; let Accessors = [Accessor<"isGNU", [GCC<"aligned">]>, - Accessor<"isC11", [Keyword<"_Alignas">]>, - Accessor<"isAlignas", [Keyword<"alignas">, - Keyword<"_Alignas">]>, + Accessor<"isC11", [CustomKeyword<"_Alignas">]>, + Accessor<"isAlignas", [CustomKeyword<"alignas">, + CustomKeyword<"_Alignas">]>, Accessor<"isDeclspec",[Declspec<"align">]>]; let Documentation = [Undocumented]; } @@ -756,7 +769,7 @@ def AlignNatural : InheritableAttr { def AlwaysInline : DeclOrStmtAttr { let Spellings = [GCC<"always_inline">, CXX11<"clang", "always_inline">, - C2x<"clang", "always_inline">, Keyword<"__forceinline">]; + C2x<"clang", "always_inline">, CustomKeyword<"__forceinline">]; let Accessors = [Accessor<"isClangAlwaysInline", [CXX11<"clang", "always_inline">, C2x<"clang", "always_inline">]>]; let Subjects = SubjectList<[Function, Stmt], WarnDiag, @@ -879,7 +892,7 @@ def AVRSignal : InheritableAttr, TargetSpecificAttr { } def AsmLabel : InheritableAttr { - let Spellings = [Keyword<"asm">, Keyword<"__asm__">]; + let Spellings = [CustomKeyword<"asm">, CustomKeyword<"__asm__">]; let Args = [ // Label specifies the mangled name for the decl. StringArgument<"Label">, @@ -997,7 +1010,7 @@ def CarriesDependency : InheritableParamAttr { } def CDecl : DeclOrTypeAttr { - let Spellings = [GCC<"cdecl">, Keyword<"__cdecl">, Keyword<"_cdecl">]; + let Spellings = [GCC<"cdecl">, CustomKeyword<"__cdecl">, CustomKeyword<"_cdecl">]; // let Subjects = [Function, ObjCMethod]; let Documentation = [Undocumented]; } @@ -1084,7 +1097,7 @@ def Cleanup : InheritableAttr { let Spellings = [GCC<"cleanup">]; let Args = [DeclArgument]; let Subjects = SubjectList<[LocalVar]>; - let Documentation = [Undocumented]; + let Documentation = [CleanupDocs]; } def CmseNSEntry : InheritableAttr, TargetSpecificAttr { @@ -1122,10 +1135,10 @@ def Const : InheritableAttr { def ConstInit : InheritableAttr { // This attribute does not have a C [[]] spelling because it requires the // CPlusPlus language option. - let Spellings = [Keyword<"constinit">, + let Spellings = [CustomKeyword<"constinit">, Clang<"require_constant_initialization", 0>]; let Subjects = SubjectList<[GlobalVar], ErrorDiag>; - let Accessors = [Accessor<"isConstinit", [Keyword<"constinit">]>]; + let Accessors = [Accessor<"isConstinit", [CustomKeyword<"constinit">]>]; let Documentation = [ConstInitDocs]; let LangOpts = [CPlusPlus]; let SimpleHandler = 1; @@ -1276,7 +1289,7 @@ def SYCLSpecialClass: InheritableAttr { } def C11NoReturn : InheritableAttr { - let Spellings = [Keyword<"_Noreturn">]; + let Spellings = [CustomKeyword<"_Noreturn">]; let Subjects = SubjectList<[Function], ErrorDiag>; let SemaHandler = 0; let Documentation = [C11NoReturnDocs]; @@ -1292,7 +1305,7 @@ def CXX11NoReturn : InheritableAttr { // Similar to CUDA, OpenCL attributes do not receive a [[]] spelling because // the specification does not expose them with one currently. def OpenCLKernel : InheritableAttr { - let Spellings = [Keyword<"__kernel">, Keyword<"kernel">]; + let Spellings = [CustomKeyword<"__kernel">, CustomKeyword<"kernel">]; let Subjects = SubjectList<[Function], ErrorDiag>; let Documentation = [Undocumented]; let SimpleHandler = 1; @@ -1316,26 +1329,28 @@ def OpenCLIntelReqdSubGroupSize: InheritableAttr { // This attribute is both a type attribute, and a declaration attribute (for // parameter variables). def OpenCLAccess : Attr { - let Spellings = [Keyword<"__read_only">, Keyword<"read_only">, - Keyword<"__write_only">, Keyword<"write_only">, - Keyword<"__read_write">, Keyword<"read_write">]; + let Spellings = [CustomKeyword<"__read_only">, CustomKeyword<"read_only">, + CustomKeyword<"__write_only">, CustomKeyword<"write_only">, + CustomKeyword<"__read_write">, CustomKeyword<"read_write">]; let Subjects = SubjectList<[ParmVar, TypedefName], ErrorDiag>; - let Accessors = [Accessor<"isReadOnly", [Keyword<"__read_only">, - Keyword<"read_only">]>, - Accessor<"isReadWrite", [Keyword<"__read_write">, - Keyword<"read_write">]>, - Accessor<"isWriteOnly", [Keyword<"__write_only">, - Keyword<"write_only">]>]; + let Accessors = [Accessor<"isReadOnly", [CustomKeyword<"__read_only">, + CustomKeyword<"read_only">]>, + Accessor<"isReadWrite", [CustomKeyword<"__read_write">, + CustomKeyword<"read_write">]>, + Accessor<"isWriteOnly", [CustomKeyword<"__write_only">, + CustomKeyword<"write_only">]>]; let Documentation = [OpenCLAccessDocs]; } def OpenCLPrivateAddressSpace : TypeAttr { - let Spellings = [Keyword<"__private">, Keyword<"private">, Clang<"opencl_private">]; + let Spellings = [CustomKeyword<"__private">, CustomKeyword<"private">, + Clang<"opencl_private">]; let Documentation = [OpenCLAddressSpacePrivateDocs]; } def OpenCLGlobalAddressSpace : TypeAttr { - let Spellings = [Keyword<"__global">, Keyword<"global">, Clang<"opencl_global">]; + let Spellings = [CustomKeyword<"__global">, CustomKeyword<"global">, + Clang<"opencl_global">]; let Documentation = [OpenCLAddressSpaceGlobalDocs]; } @@ -1350,17 +1365,20 @@ def OpenCLGlobalHostAddressSpace : TypeAttr { } def OpenCLLocalAddressSpace : TypeAttr { - let Spellings = [Keyword<"__local">, Keyword<"local">, Clang<"opencl_local">]; + let Spellings = [CustomKeyword<"__local">, CustomKeyword<"local">, + Clang<"opencl_local">]; let Documentation = [OpenCLAddressSpaceLocalDocs]; } def OpenCLConstantAddressSpace : TypeAttr { - let Spellings = [Keyword<"__constant">, Keyword<"constant">, Clang<"opencl_constant">]; + let Spellings = [CustomKeyword<"__constant">, CustomKeyword<"constant">, + Clang<"opencl_constant">]; let Documentation = [OpenCLAddressSpaceConstantDocs]; } def OpenCLGenericAddressSpace : TypeAttr { - let Spellings = [Keyword<"__generic">, Keyword<"generic">, Clang<"opencl_generic">]; + let Spellings = [CustomKeyword<"__generic">, CustomKeyword<"generic">, + Clang<"opencl_generic">]; let Documentation = [OpenCLAddressSpaceGenericDocs]; } @@ -1476,20 +1494,20 @@ def MustTail : StmtAttr { } def FastCall : DeclOrTypeAttr { - let Spellings = [GCC<"fastcall">, Keyword<"__fastcall">, - Keyword<"_fastcall">]; + let Spellings = [GCC<"fastcall">, CustomKeyword<"__fastcall">, + CustomKeyword<"_fastcall">]; // let Subjects = [Function, ObjCMethod]; let Documentation = [FastCallDocs]; } def RegCall : DeclOrTypeAttr { - let Spellings = [GCC<"regcall">, Keyword<"__regcall">]; + let Spellings = [GCC<"regcall">, CustomKeyword<"__regcall">]; let Documentation = [RegCallDocs]; } def Final : InheritableAttr { - let Spellings = [Keyword<"final">, Keyword<"sealed">]; - let Accessors = [Accessor<"isSpelledAsSealed", [Keyword<"sealed">]>]; + let Spellings = [CustomKeyword<"final">, CustomKeyword<"sealed">]; + let Accessors = [Accessor<"isSpelledAsSealed", [CustomKeyword<"sealed">]>]; let SemaHandler = 0; // Omitted from docs, since this is language syntax, not an attribute, as far // as users are concerned. @@ -1835,7 +1853,7 @@ def Convergent : InheritableAttr { } def NoInline : DeclOrStmtAttr { - let Spellings = [Keyword<"__noinline__">, GCC<"noinline">, + let Spellings = [CustomKeyword<"__noinline__">, GCC<"noinline">, CXX11<"clang", "noinline">, C2x<"clang", "noinline">, Declspec<"noinline">]; let Accessors = [Accessor<"isClangNoInline", [CXX11<"clang", "noinline">, @@ -2031,22 +2049,22 @@ def PassObjectSize : InheritableParamAttr { // Nullability type attributes. def TypeNonNull : TypeAttr { - let Spellings = [Keyword<"_Nonnull">]; + let Spellings = [CustomKeyword<"_Nonnull">]; let Documentation = [TypeNonNullDocs]; } def TypeNullable : TypeAttr { - let Spellings = [Keyword<"_Nullable">]; + let Spellings = [CustomKeyword<"_Nullable">]; let Documentation = [TypeNullableDocs]; } def TypeNullableResult : TypeAttr { - let Spellings = [Keyword<"_Nullable_result">]; + let Spellings = [CustomKeyword<"_Nullable_result">]; let Documentation = [TypeNullableResultDocs]; } def TypeNullUnspecified : TypeAttr { - let Spellings = [Keyword<"_Null_unspecified">]; + let Spellings = [CustomKeyword<"_Null_unspecified">]; let Documentation = [TypeNullUnspecifiedDocs]; } @@ -2054,12 +2072,12 @@ def TypeNullUnspecified : TypeAttr { // ignored because ARC is not enabled. The usual representation for this // qualifier is as an ObjCOwnership attribute with Kind == "none". def ObjCInertUnsafeUnretained : TypeAttr { - let Spellings = [Keyword<"__unsafe_unretained">]; + let Spellings = [CustomKeyword<"__unsafe_unretained">]; let Documentation = [InternalOnly]; } def ObjCKindOf : TypeAttr { - let Spellings = [Keyword<"__kindof">]; + let Spellings = [CustomKeyword<"__kindof">]; let Documentation = [Undocumented]; } @@ -2358,7 +2376,7 @@ def Overloadable : Attr { } def Override : InheritableAttr { - let Spellings = [Keyword<"override">]; + let Spellings = [CustomKeyword<"override">]; let SemaHandler = 0; // Omitted from docs, since this is language syntax, not an attribute, as far // as users are concerned. @@ -2416,6 +2434,11 @@ def AArch64SVEPcs: DeclOrTypeAttr { let Documentation = [AArch64SVEPcsDocs]; } +def ArmStreaming : TypeAttr, TargetSpecificAttr { + let Spellings = [RegularKeyword<"__arm_streaming">]; + let Documentation = [ArmStreamingDocs]; +} + def Pure : InheritableAttr { let Spellings = [GCC<"pure">]; let Documentation = [Undocumented]; @@ -2603,7 +2626,8 @@ def Sentinel : InheritableAttr { } def StdCall : DeclOrTypeAttr { - let Spellings = [GCC<"stdcall">, Keyword<"__stdcall">, Keyword<"_stdcall">]; + let Spellings = [GCC<"stdcall">, CustomKeyword<"__stdcall">, + CustomKeyword<"_stdcall">]; // let Subjects = [Function, ObjCMethod]; let Documentation = [StdCallDocs]; } @@ -2672,15 +2696,15 @@ def SysVABI : DeclOrTypeAttr { } def ThisCall : DeclOrTypeAttr { - let Spellings = [GCC<"thiscall">, Keyword<"__thiscall">, - Keyword<"_thiscall">]; + let Spellings = [GCC<"thiscall">, CustomKeyword<"__thiscall">, + CustomKeyword<"_thiscall">]; // let Subjects = [Function, ObjCMethod]; let Documentation = [ThisCallDocs]; } def VectorCall : DeclOrTypeAttr { - let Spellings = [Clang<"vectorcall">, Keyword<"__vectorcall">, - Keyword<"_vectorcall">]; + let Spellings = [Clang<"vectorcall">, CustomKeyword<"__vectorcall">, + CustomKeyword<"_vectorcall">]; // let Subjects = [Function, ObjCMethod]; let Documentation = [VectorCallDocs]; } @@ -2699,7 +2723,8 @@ def ZeroCallUsedRegs : InheritableAttr { } def Pascal : DeclOrTypeAttr { - let Spellings = [Clang<"pascal">, Keyword<"__pascal">, Keyword<"_pascal">]; + let Spellings = [Clang<"pascal">, CustomKeyword<"__pascal">, + CustomKeyword<"_pascal">]; // let Subjects = [Function, ObjCMethod]; let Documentation = [Undocumented]; } @@ -3596,37 +3621,37 @@ def Thread : Attr { } def Win64 : IgnoredAttr { - let Spellings = [Keyword<"__w64">]; + let Spellings = [CustomKeyword<"__w64">]; let LangOpts = [MicrosoftExt]; } def Ptr32 : TypeAttr { - let Spellings = [Keyword<"__ptr32">]; + let Spellings = [CustomKeyword<"__ptr32">]; let Documentation = [Ptr32Docs]; } def Ptr64 : TypeAttr { - let Spellings = [Keyword<"__ptr64">]; + let Spellings = [CustomKeyword<"__ptr64">]; let Documentation = [Ptr64Docs]; } def SPtr : TypeAttr { - let Spellings = [Keyword<"__sptr">]; + let Spellings = [CustomKeyword<"__sptr">]; let Documentation = [SPtrDocs]; } def UPtr : TypeAttr { - let Spellings = [Keyword<"__uptr">]; + let Spellings = [CustomKeyword<"__uptr">]; let Documentation = [UPtrDocs]; } def MSInheritance : InheritableAttr { let LangOpts = [MicrosoftExt]; let Args = [DefaultBoolArgument<"BestCase", /*default*/1, /*fake*/1>]; - let Spellings = [Keyword<"__single_inheritance">, - Keyword<"__multiple_inheritance">, - Keyword<"__virtual_inheritance">, - Keyword<"__unspecified_inheritance">]; + let Spellings = [CustomKeyword<"__single_inheritance">, + CustomKeyword<"__multiple_inheritance">, + CustomKeyword<"__virtual_inheritance">, + CustomKeyword<"__unspecified_inheritance">]; let AdditionalMembers = [{ MSInheritanceModel getInheritanceModel() const { // The spelling enum should agree with MSInheritanceModel. @@ -4126,7 +4151,7 @@ def HLSLResource : InheritableAttr { } def HLSLGroupSharedAddressSpace : TypeAttr { - let Spellings = [Keyword<"groupshared">]; + let Spellings = [CustomKeyword<"groupshared">]; let Subjects = SubjectList<[Var]>; let Documentation = [HLSLGroupSharedAddressSpaceDocs]; } @@ -4158,7 +4183,7 @@ def FunctionReturnThunks : InheritableAttr, } def WebAssemblyFuncref : TypeAttr, TargetSpecificAttr { - let Spellings = [Keyword<"__funcref">]; + let Spellings = [CustomKeyword<"__funcref">]; let Documentation = [WebAssemblyExportNameDocs]; let Subjects = SubjectList<[FunctionPointer], ErrorDiag>; } diff --git a/clang/include/clang/Basic/AttrDocs.td b/clang/include/clang/Basic/AttrDocs.td index f62350f33013c..e3d83234b316a 100644 --- a/clang/include/clang/Basic/AttrDocs.td +++ b/clang/include/clang/Basic/AttrDocs.td @@ -6551,6 +6551,41 @@ Requirements on Development Tools - Engineering Specification Documentation }]; } +def ArmStreamingDocs : Documentation { + let Category = DocCatType; + let Content = [{ +.. Note:: This attribute has not been implemented yet, but once it is + implemented, it will behave as described below. + +The ``__arm_streaming`` keyword is only available on AArch64 targets. +It applies to function types and specifies that the function has a +“streaming interface”. This means that: + +* the function requires the Scalable Matrix Extension (SME) + +* the function must be entered in streaming mode (that is, with PSTATE.SM + set to 1) + +* the function must return in streaming mode + +See `Procedure Call Standard for the Arm® 64-bit Architecture (AArch64) +`_ for more details about +streaming-interface functions. + +Clang manages PSTATE.SM automatically; it is not the source code's +responsibility to do this. For example, if a normal non-streaming +function calls an ``__arm_streaming`` function, Clang generates code +that switches into streaming mode before calling the function and +switches back to non-streaming mode on return. + +``__arm_streaming`` can appear anywhere that a standard ``[[…]]`` type +attribute can appear. + +See `Arm C Language Extensions `_ +for more details about this extension, and for other related SME features. + }]; +} + def AlwaysInlineDocs : Documentation { let Category = DocCatFunction; let Content = [{ @@ -6988,3 +7023,30 @@ This attribute may be attached to a function pointer type, where it modifies its underlying representation to be a WebAssembly ``funcref``. }]; } + +def CleanupDocs : Documentation { + let Category = DocCatType; + let Content = [{ +This attribute allows a function to be run when a local variable goes out of +scope. The attribute takes the identifier of a function with a parameter type +that is a pointer to the type with the attribute. + +.. code-block:: c + + static void foo (int *) { ... } + static void bar (int *) { ... } + void baz (void) { + int x __attribute__((cleanup(foo))); + { + int y __attribute__((cleanup(bar))); + } + } + +The above example will result in a call to ``bar`` being passed the address of +`y`` when ``y`` goes out of scope, then a call to ``foo`` being passed the +address of ``x`` when ``x`` goes out of scope. If two or more variables share +the same scope, their ``cleanup`` callbacks are invoked in the reverse order +the variables were declared in. It is not possible to check the return value +(if any) of these ``cleanup`` callback functions. +}]; +} diff --git a/clang/include/clang/Basic/AttributeCommonInfo.h b/clang/include/clang/Basic/AttributeCommonInfo.h index a92dc0dad5157..6396c0dc6ef02 100644 --- a/clang/include/clang/Basic/AttributeCommonInfo.h +++ b/clang/include/clang/Basic/AttributeCommonInfo.h @@ -77,6 +77,7 @@ class AttributeCommonInfo { unsigned SyntaxUsed : 4; unsigned SpellingIndex : 4; unsigned IsAlignas : 1; + unsigned IsRegularKeywordAttribute : 1; protected: static constexpr unsigned SpellingNotCalculated = 0xf; @@ -86,24 +87,29 @@ class AttributeCommonInfo { /// including its syntax and spelling. class Form { public: - constexpr Form(Syntax SyntaxUsed, unsigned SpellingIndex, bool IsAlignas) + constexpr Form(Syntax SyntaxUsed, unsigned SpellingIndex, bool IsAlignas, + bool IsRegularKeywordAttribute) : SyntaxUsed(SyntaxUsed), SpellingIndex(SpellingIndex), - IsAlignas(IsAlignas) {} + IsAlignas(IsAlignas), + IsRegularKeywordAttribute(IsRegularKeywordAttribute) {} constexpr Form(tok::TokenKind Tok) : SyntaxUsed(AS_Keyword), SpellingIndex(SpellingNotCalculated), - IsAlignas(Tok == tok::kw_alignas) {} + IsAlignas(Tok == tok::kw_alignas), + IsRegularKeywordAttribute(tok::isRegularKeywordAttribute(Tok)) {} Syntax getSyntax() const { return Syntax(SyntaxUsed); } unsigned getSpellingIndex() const { return SpellingIndex; } bool isAlignas() const { return IsAlignas; } + bool isRegularKeywordAttribute() const { return IsRegularKeywordAttribute; } static Form GNU() { return AS_GNU; } static Form CXX11() { return AS_CXX11; } static Form C2x() { return AS_C2x; } static Form Declspec() { return AS_Declspec; } static Form Microsoft() { return AS_Microsoft; } - static Form Keyword(bool IsAlignas) { - return Form(AS_Keyword, SpellingNotCalculated, IsAlignas); + static Form Keyword(bool IsAlignas, bool IsRegularKeywordAttribute) { + return Form(AS_Keyword, SpellingNotCalculated, IsAlignas, + IsRegularKeywordAttribute); } static Form Pragma() { return AS_Pragma; } static Form ContextSensitiveKeyword() { return AS_ContextSensitiveKeyword; } @@ -113,11 +119,12 @@ class AttributeCommonInfo { private: constexpr Form(Syntax SyntaxUsed) : SyntaxUsed(SyntaxUsed), SpellingIndex(SpellingNotCalculated), - IsAlignas(0) {} + IsAlignas(0), IsRegularKeywordAttribute(0) {} unsigned SyntaxUsed : 4; unsigned SpellingIndex : 4; unsigned IsAlignas : 1; + unsigned IsRegularKeywordAttribute : 1; }; AttributeCommonInfo(const IdentifierInfo *AttrName, @@ -127,7 +134,8 @@ class AttributeCommonInfo { ScopeLoc(ScopeLoc), AttrKind(AttrKind), SyntaxUsed(FormUsed.getSyntax()), SpellingIndex(FormUsed.getSpellingIndex()), - IsAlignas(FormUsed.isAlignas()) { + IsAlignas(FormUsed.isAlignas()), + IsRegularKeywordAttribute(FormUsed.isRegularKeywordAttribute()) { assert(SyntaxUsed >= AS_GNU && SyntaxUsed <= AS_Implicit && "Invalid syntax!"); } @@ -154,7 +162,10 @@ class AttributeCommonInfo { Kind getParsedKind() const { return Kind(AttrKind); } Syntax getSyntax() const { return Syntax(SyntaxUsed); } - Form getForm() const { return Form(getSyntax(), SpellingIndex, IsAlignas); } + Form getForm() const { + return Form(getSyntax(), SpellingIndex, IsAlignas, + IsRegularKeywordAttribute); + } const IdentifierInfo *getAttrName() const { return AttrName; } SourceLocation getLoc() const { return AttrRange.getBegin(); } SourceRange getRange() const { return AttrRange; } @@ -191,6 +202,8 @@ class AttributeCommonInfo { return SyntaxUsed == AS_Keyword || SyntaxUsed == AS_ContextSensitiveKeyword; } + bool isRegularKeywordAttribute() const { return IsRegularKeywordAttribute; } + bool isContextSensitiveKeywordAttribute() const { return SyntaxUsed == AS_ContextSensitiveKeyword; } diff --git a/clang/include/clang/Basic/Builtins.def b/clang/include/clang/Basic/Builtins.def index 15c69c2786476..c8f955a1f4b28 100644 --- a/clang/include/clang/Basic/Builtins.def +++ b/clang/include/clang/Basic/Builtins.def @@ -39,6 +39,8 @@ // A -> "reference" to __builtin_va_list // V -> Vector, followed by the number of elements and the base type. // q -> Scalable vector, followed by the number of elements and the base type. +// Q -> target builtin type, followed by a character to distinguish the builtin type +// Qa -> AArch64 svcount_t builtin type. // E -> ext_vector, followed by the number of elements and the base type. // X -> _Complex, followed by the base type. // Y -> ptrdiff_t @@ -910,6 +912,7 @@ ATOMIC_BUILTIN(__hip_atomic_compare_exchange_weak, "v.", "t") ATOMIC_BUILTIN(__hip_atomic_compare_exchange_strong, "v.", "t") ATOMIC_BUILTIN(__hip_atomic_exchange, "v.", "t") ATOMIC_BUILTIN(__hip_atomic_fetch_add, "v.", "t") +ATOMIC_BUILTIN(__hip_atomic_fetch_sub, "v.", "t") ATOMIC_BUILTIN(__hip_atomic_fetch_and, "v.", "t") ATOMIC_BUILTIN(__hip_atomic_fetch_or, "v.", "t") ATOMIC_BUILTIN(__hip_atomic_fetch_xor, "v.", "t") diff --git a/clang/include/clang/Basic/BuiltinsNVPTX.def b/clang/include/clang/Basic/BuiltinsNVPTX.def index 7ffb38d50a6cf..3275d50a85a4b 100644 --- a/clang/include/clang/Basic/BuiltinsNVPTX.def +++ b/clang/include/clang/Basic/BuiltinsNVPTX.def @@ -817,6 +817,7 @@ BUILTIN(__nvvm_compiler_error, "vcC*4", "n") BUILTIN(__nvvm_compiler_warn, "vcC*4", "n") BUILTIN(__nvvm_ldu_c, "ccC*", "") +BUILTIN(__nvvm_ldu_sc, "ScScC*", "") BUILTIN(__nvvm_ldu_s, "ssC*", "") BUILTIN(__nvvm_ldu_i, "iiC*", "") BUILTIN(__nvvm_ldu_l, "LiLiC*", "") @@ -833,11 +834,14 @@ BUILTIN(__nvvm_ldu_f, "ffC*", "") BUILTIN(__nvvm_ldu_d, "ddC*", "") BUILTIN(__nvvm_ldu_c2, "E2cE2cC*", "") +BUILTIN(__nvvm_ldu_sc2, "E2ScE2ScC*", "") BUILTIN(__nvvm_ldu_c4, "E4cE4cC*", "") +BUILTIN(__nvvm_ldu_sc4, "E4ScE4ScC*", "") BUILTIN(__nvvm_ldu_s2, "E2sE2sC*", "") BUILTIN(__nvvm_ldu_s4, "E4sE4sC*", "") BUILTIN(__nvvm_ldu_i2, "E2iE2iC*", "") BUILTIN(__nvvm_ldu_i4, "E4iE4iC*", "") +BUILTIN(__nvvm_ldu_l2, "E2LiE2LiC*", "") BUILTIN(__nvvm_ldu_ll2, "E2LLiE2LLiC*", "") BUILTIN(__nvvm_ldu_uc2, "E2UcE2UcC*", "") @@ -846,6 +850,7 @@ BUILTIN(__nvvm_ldu_us2, "E2UsE2UsC*", "") BUILTIN(__nvvm_ldu_us4, "E4UsE4UsC*", "") BUILTIN(__nvvm_ldu_ui2, "E2UiE2UiC*", "") BUILTIN(__nvvm_ldu_ui4, "E4UiE4UiC*", "") +BUILTIN(__nvvm_ldu_ul2, "E2ULiE2ULiC*", "") BUILTIN(__nvvm_ldu_ull2, "E2ULLiE2ULLiC*", "") BUILTIN(__nvvm_ldu_h2, "E2hE2hC*", "") @@ -854,6 +859,7 @@ BUILTIN(__nvvm_ldu_f4, "E4fE4fC*", "") BUILTIN(__nvvm_ldu_d2, "E2dE2dC*", "") BUILTIN(__nvvm_ldg_c, "ccC*", "") +BUILTIN(__nvvm_ldg_sc, "ScScC*", "") BUILTIN(__nvvm_ldg_s, "ssC*", "") BUILTIN(__nvvm_ldg_i, "iiC*", "") BUILTIN(__nvvm_ldg_l, "LiLiC*", "") @@ -870,11 +876,14 @@ BUILTIN(__nvvm_ldg_f, "ffC*", "") BUILTIN(__nvvm_ldg_d, "ddC*", "") BUILTIN(__nvvm_ldg_c2, "E2cE2cC*", "") +BUILTIN(__nvvm_ldg_sc2, "E2ScE2ScC*", "") BUILTIN(__nvvm_ldg_c4, "E4cE4cC*", "") +BUILTIN(__nvvm_ldg_sc4, "E4ScE4ScC*", "") BUILTIN(__nvvm_ldg_s2, "E2sE2sC*", "") BUILTIN(__nvvm_ldg_s4, "E4sE4sC*", "") BUILTIN(__nvvm_ldg_i2, "E2iE2iC*", "") BUILTIN(__nvvm_ldg_i4, "E4iE4iC*", "") +BUILTIN(__nvvm_ldg_l2, "E2LiE2LiC*", "") BUILTIN(__nvvm_ldg_ll2, "E2LLiE2LLiC*", "") BUILTIN(__nvvm_ldg_uc2, "E2UcE2UcC*", "") @@ -883,6 +892,7 @@ BUILTIN(__nvvm_ldg_us2, "E2UsE2UsC*", "") BUILTIN(__nvvm_ldg_us4, "E4UsE4UsC*", "") BUILTIN(__nvvm_ldg_ui2, "E2UiE2UiC*", "") BUILTIN(__nvvm_ldg_ui4, "E4UiE4UiC*", "") +BUILTIN(__nvvm_ldg_ul2, "E2ULiE2ULiC*", "") BUILTIN(__nvvm_ldg_ull2, "E2ULLiE2ULLiC*", "") BUILTIN(__nvvm_ldg_h2, "E2hE2hC*", "") diff --git a/clang/include/clang/Basic/CMakeLists.txt b/clang/include/clang/Basic/CMakeLists.txt index 67153da383f5a..f010e04f62cd8 100644 --- a/clang/include/clang/Basic/CMakeLists.txt +++ b/clang/include/clang/Basic/CMakeLists.txt @@ -35,6 +35,12 @@ clang_tablegen(AttrSubMatchRulesList.inc -gen-clang-attr-subject-match-rule-list SOURCE Attr.td TARGET ClangAttrSubjectMatchRuleList) +clang_tablegen(AttrTokenKinds.inc -gen-clang-attr-token-kinds + -I ${CMAKE_CURRENT_SOURCE_DIR}/../../ + SOURCE Attr.td + TARGET ClangAttrTokenKinds + ) + clang_tablegen(AttrHasAttributeImpl.inc -gen-clang-attr-has-attribute-impl -I ${CMAKE_CURRENT_SOURCE_DIR}/../../ SOURCE Attr.td diff --git a/clang/include/clang/Basic/DiagnosticCommonKinds.td b/clang/include/clang/Basic/DiagnosticCommonKinds.td index 42d8a0abfbceb..eb1649cc238a5 100644 --- a/clang/include/clang/Basic/DiagnosticCommonKinds.td +++ b/clang/include/clang/Basic/DiagnosticCommonKinds.td @@ -121,7 +121,7 @@ def note_pragma_entered_here : Note<"#pragma entered here">; def note_decl_hiding_tag_type : Note< "%1 %0 is hidden by a non-type declaration of %0 here">; def err_attribute_not_type_attr : Error< - "%0 attribute cannot be applied to types">; + "%0%select{ attribute|}1 cannot be applied to types">; def err_enum_template : Error<"enumeration cannot be a template">; def warn_cxx20_compat_consteval : Warning< @@ -175,6 +175,8 @@ def warn_unknown_attribute_ignored : Warning< "unknown attribute %0 ignored">, InGroup; def warn_attribute_ignored : Warning<"%0 attribute ignored">, InGroup; +def err_keyword_not_supported_on_target : Error< + "%0 is not supported on this target">; def err_use_of_tag_name_without_tag : Error< "must use '%1' tag to refer to type %0%select{| in this scope}2">; diff --git a/clang/include/clang/Basic/DiagnosticDriverKinds.td b/clang/include/clang/Basic/DiagnosticDriverKinds.td index d56708e3ee4fc..d7e59879cfa58 100644 --- a/clang/include/clang/Basic/DiagnosticDriverKinds.td +++ b/clang/include/clang/Basic/DiagnosticDriverKinds.td @@ -619,6 +619,9 @@ def warn_drv_darwin_sdk_invalid_settings : Warning< "SDK settings were ignored as 'SDKSettings.json' could not be parsed">, InGroup>; +def err_drv_darwin_sdk_missing_arclite : Error< + "SDK does not contain 'libarclite' at the path '%0'; try increasing the minimum deployment target">; + def err_drv_trivial_auto_var_init_stop_after_missing_dependency : Error< "'-ftrivial-auto-var-init-stop-after=*' is used without " "'-ftrivial-auto-var-init=zero' or '-ftrivial-auto-var-init=pattern'">; diff --git a/clang/include/clang/Basic/DiagnosticOptions.def b/clang/include/clang/Basic/DiagnosticOptions.def index 1d6d55a411e78..6d0c1b14acc12 100644 --- a/clang/include/clang/Basic/DiagnosticOptions.def +++ b/clang/include/clang/Basic/DiagnosticOptions.def @@ -90,6 +90,8 @@ VALUE_DIAGOPT(ConstexprBacktraceLimit, 32, DefaultConstexprBacktraceLimit) VALUE_DIAGOPT(SpellCheckingLimit, 32, DefaultSpellCheckingLimit) /// Limit number of lines shown in a snippet. VALUE_DIAGOPT(SnippetLineLimit, 32, DefaultSnippetLineLimit) +/// Show line number column on the left of snippets. +VALUE_DIAGOPT(ShowLineNumbers, 1, DefaultShowLineNumbers) VALUE_DIAGOPT(TabStop, 32, DefaultTabStop) /// The distance between tab stops. /// Column limit for formatting message diagnostics, or 0 if unused. diff --git a/clang/include/clang/Basic/DiagnosticOptions.h b/clang/include/clang/Basic/DiagnosticOptions.h index 4b0d45a3ff7c7..7e218b9c71e69 100644 --- a/clang/include/clang/Basic/DiagnosticOptions.h +++ b/clang/include/clang/Basic/DiagnosticOptions.h @@ -84,7 +84,8 @@ class DiagnosticOptions : public RefCountedBase{ DefaultTemplateBacktraceLimit = 10, DefaultConstexprBacktraceLimit = 10, DefaultSpellCheckingLimit = 50, - DefaultSnippetLineLimit = 1, + DefaultSnippetLineLimit = 16, + DefaultShowLineNumbers = 1, }; // Define simple diagnostic options (with no accessors). diff --git a/clang/include/clang/Basic/DiagnosticParseKinds.td b/clang/include/clang/Basic/DiagnosticParseKinds.td index 5d5048a7d2c04..d015628db7f23 100644 --- a/clang/include/clang/Basic/DiagnosticParseKinds.td +++ b/clang/include/clang/Basic/DiagnosticParseKinds.td @@ -733,10 +733,12 @@ def ext_using_attribute_ns : ExtWarn< def err_using_attribute_ns_conflict : Error< "attribute with scope specifier cannot follow default scope specifier">; def err_attributes_not_allowed : Error<"an attribute list cannot appear here">; +def err_keyword_not_allowed : Error<"%0 cannot appear here">; def ext_cxx11_attr_placement : ExtWarn< - "ISO C++ does not allow an attribute list to appear here">, + "ISO C++ does not allow %select{an attribute list|%0}1 to appear here">, InGroup>; def err_attributes_misplaced : Error<"misplaced attributes; expected attributes here">; +def err_keyword_misplaced : Error<"misplaced %0; expected %0 here">; def err_l_square_l_square_not_attribute : Error< "C++11 only allows consecutive left square brackets when " "introducing an attribute">; @@ -1014,14 +1016,15 @@ def err_lambda_capture_multiple_ellipses : Error< def err_capture_default_first : Error< "capture default must be first">; def ext_decl_attrs_on_lambda : ExtWarn< - "an attribute specifier sequence in this position is a C++23 extension">, - InGroup; + "%select{an attribute specifier sequence|%0}1 in this position " + "is a C++23 extension">, InGroup; def ext_lambda_missing_parens : ExtWarn< "lambda without a parameter clause is a C++23 extension">, InGroup; def warn_cxx20_compat_decl_attrs_on_lambda : Warning< - "an attribute specifier sequence in this position is incompatible with C++ " - "standards before C++23">, InGroup, DefaultIgnore; + "%select{an attribute specifier sequence|%1}0 in this position " + "is incompatible with C++ standards before C++23">, + InGroup, DefaultIgnore; // C++17 lambda expressions def err_expected_star_this_capture : Error< @@ -1582,8 +1585,12 @@ def err_module_expected_ident : Error< "expected a module name after '%select{module|import}0'">; def err_attribute_not_module_attr : Error< "%0 attribute cannot be applied to a module">; +def err_keyword_not_module_attr : Error< + "%0 cannot be applied to a module">; def err_attribute_not_import_attr : Error< "%0 attribute cannot be applied to a module import">; +def err_keyword_not_import_attr : Error< + "%0 cannot be applied to a module import">; def err_module_expected_semi : Error< "expected ';' after module name">; def err_global_module_introducer_not_at_start : Error< diff --git a/clang/include/clang/Basic/DiagnosticSemaKinds.td b/clang/include/clang/Basic/DiagnosticSemaKinds.td index 3edffbe190273..90ecbd623ceef 100644 --- a/clang/include/clang/Basic/DiagnosticSemaKinds.td +++ b/clang/include/clang/Basic/DiagnosticSemaKinds.td @@ -3022,7 +3022,7 @@ def err_musttail_no_variadic : Error< def err_nsobject_attribute : Error< "'NSObject' attribute is for pointer types only">; def err_attributes_are_not_compatible : Error< - "%0 and %1 attributes are not compatible">; + "%0 and %1%select{ attributes|}2 are not compatible">; def err_attribute_invalid_argument : Error< "%select{a reference type|an array type|a non-vector or " "non-vectorizable scalar type}0 is an invalid argument to attribute %1">; @@ -3430,9 +3430,9 @@ def warn_attribute_has_no_effect_on_compile_time_if : Warning< def note_attribute_has_no_effect_on_compile_time_if_here : Note< "annotating the 'if %select{constexpr|consteval}0' statement here">; def err_decl_attribute_invalid_on_stmt : Error< - "%0 attribute cannot be applied to a statement">; + "%0%select{ attribute|}1 cannot be applied to a statement">; def err_attribute_invalid_on_decl : Error< - "%0 attribute cannot be applied to a declaration">; + "%0%select{ attribute|}1 cannot be applied to a declaration">; def warn_type_attribute_deprecated_on_decl : Warning< "applying attribute %0 to a declaration is deprecated; apply it to the type instead">, InGroup; @@ -3440,6 +3440,10 @@ def warn_declspec_attribute_ignored : Warning< "attribute %0 is ignored, place it after " "\"%select{class|struct|interface|union|enum|enum class|enum struct}1\" to apply attribute to " "type declaration">, InGroup; +def err_declspec_keyword_has_no_effect : Error< + "%0 cannot appear here, place it after " + "\"%select{class|struct|interface|union|enum}1\" to apply it to the " + "type declaration">; def warn_attribute_precede_definition : Warning< "attribute declaration must precede definition">, InGroup; @@ -3538,11 +3542,11 @@ def err_attribute_weakref_without_alias : Error< def err_alias_not_supported_on_darwin : Error < "aliases are not supported on darwin">; def warn_attribute_wrong_decl_type_str : Warning< - "%0 attribute only applies to %1">, InGroup; + "%0%select{ attribute|}1 only applies to %2">, InGroup; def err_attribute_wrong_decl_type_str : Error< warn_attribute_wrong_decl_type_str.Summary>; def warn_attribute_wrong_decl_type : Warning< - "%0 attribute only applies to %select{" + "%0%select{ attribute|}1 only applies to %select{" "functions" "|unions" "|variables and functions" @@ -3555,13 +3559,15 @@ def warn_attribute_wrong_decl_type : Warning< "|types and namespaces" "|variables, functions and classes" "|kernel functions" - "|non-K&R-style functions}1">, + "|non-K&R-style functions}2">, InGroup; def err_attribute_wrong_decl_type : Error; def warn_type_attribute_wrong_type : Warning< "'%0' only applies to %select{function|pointer|" "Objective-C object or block pointer}1 types; type here is %2">, InGroup; +def err_type_attribute_wrong_type : Error< + warn_type_attribute_wrong_type.Summary>; def warn_incomplete_encoded_type : Warning< "encoding of %0 type is incomplete because %1 component has unknown encoding">, InGroup>; @@ -3612,7 +3618,7 @@ def err_invalid_pcs : Error<"invalid PCS type">; def warn_attribute_not_on_decl : Warning< "%0 attribute ignored when parsing type">, InGroup; def err_base_specifier_attribute : Error< - "%0 attribute cannot be applied to a base specifier">; + "%0%select{ attribute|}1 cannot be applied to a base specifier">; def warn_declspec_allocator_nonpointer : Warning< "ignoring __declspec(allocator) because the function return type %0 is not " "a pointer or reference type">, InGroup; @@ -8523,6 +8529,9 @@ def err_atomic_op_needs_atomic_int_ptr_or_fp : Error< def err_atomic_op_needs_atomic_int_or_ptr : Error< "address argument to atomic operation must be a pointer to %select{|atomic }0" "integer or pointer (%1 invalid)">; +def err_atomic_op_needs_atomic_int_or_fp : Error< + "address argument to atomic operation must be a pointer to %select{|atomic }0" + "integer or supported floating point type (%1 invalid)">; def err_atomic_op_needs_atomic_int : Error< "address argument to atomic operation must be a pointer to " "%select{|atomic }0integer (%1 invalid)">; diff --git a/clang/include/clang/Basic/Module.h b/clang/include/clang/Basic/Module.h index 128e2adc189b2..9625a682c3549 100644 --- a/clang/include/clang/Basic/Module.h +++ b/clang/include/clang/Basic/Module.h @@ -149,7 +149,7 @@ class alignas(8) Module { /// The build directory of this module. This is the directory in /// which the module is notionally built, and relative to which its headers /// are found. - const DirectoryEntry *Directory = nullptr; + OptionalDirectoryEntryRefDegradesToDirectoryEntryPtr Directory; /// The presumed file name for the module map defining this module. /// Only non-empty when building from preprocessed source. @@ -243,9 +243,7 @@ class alignas(8) Module { struct Header { std::string NameAsWritten; std::string PathRelativeToRootModuleDirectory; - OptionalFileEntryRefDegradesToFileEntryPtr Entry; - - explicit operator bool() { return Entry.has_value(); } + FileEntryRef Entry; }; /// Information about a directory name as found in the module map @@ -253,9 +251,7 @@ class alignas(8) Module { struct DirectoryName { std::string NameAsWritten; std::string PathRelativeToRootModuleDirectory; - OptionalDirectoryEntryRefDegradesToDirectoryEntryPtr Entry; - - explicit operator bool() { return Entry.has_value(); } + DirectoryEntryRef Entry; }; /// The headers that are part of this module. @@ -653,21 +649,21 @@ class alignas(8) Module { } /// Retrieve the umbrella directory as written. - DirectoryName getUmbrellaDirAsWritten() const { + std::optional getUmbrellaDirAsWritten() const { if (const auto *ME = Umbrella.dyn_cast()) return DirectoryName{UmbrellaAsWritten, UmbrellaRelativeToRootModuleDirectory, DirectoryEntryRef(*ME)}; - return DirectoryName{}; + return std::nullopt; } /// Retrieve the umbrella header as written. - Header getUmbrellaHeaderAsWritten() const { + std::optional
getUmbrellaHeaderAsWritten() const { if (const auto *ME = Umbrella.dyn_cast()) return Header{UmbrellaAsWritten, UmbrellaRelativeToRootModuleDirectory, FileEntryRef(*ME)}; - return Header{}; + return std::nullopt; } /// Get the effective umbrella directory for this module: either the one diff --git a/clang/include/clang/Basic/TokenKinds.def b/clang/include/clang/Basic/TokenKinds.def index 7c3a55cb76348..cad973f5e5e93 100644 --- a/clang/include/clang/Basic/TokenKinds.def +++ b/clang/include/clang/Basic/TokenKinds.def @@ -748,6 +748,12 @@ KEYWORD(__builtin_bit_cast , KEYALL) KEYWORD(__builtin_available , KEYALL) KEYWORD(__builtin_sycl_unique_stable_name, KEYSYCL) +// Keywords defined by Attr.td. +#ifndef KEYWORD_ATTRIBUTE +#define KEYWORD_ATTRIBUTE(X) KEYWORD(X, KEYALL) +#endif +#include "clang/Basic/AttrTokenKinds.inc" + // Clang-specific keywords enabled only in testing. TESTING_KEYWORD(__unknown_anytype , KEYALL) diff --git a/clang/include/clang/Basic/TokenKinds.h b/clang/include/clang/Basic/TokenKinds.h index 6b7006651f4eb..0f5164bd51b08 100644 --- a/clang/include/clang/Basic/TokenKinds.h +++ b/clang/include/clang/Basic/TokenKinds.h @@ -99,6 +99,13 @@ bool isAnnotation(TokenKind K); /// Return true if this is an annotation token representing a pragma. bool isPragmaAnnotation(TokenKind K); +inline constexpr bool isRegularKeywordAttribute(TokenKind K) { + return (false +#define KEYWORD_ATTRIBUTE(X) || (K == tok::kw_##X) +#include "clang/Basic/AttrTokenKinds.inc" + ); +} + } // end namespace tok } // end namespace clang diff --git a/clang/include/clang/Basic/arm_sve.td b/clang/include/clang/Basic/arm_sve.td index aa7c0553671a5..894a0a1296b04 100644 --- a/clang/include/clang/Basic/arm_sve.td +++ b/clang/include/clang/Basic/arm_sve.td @@ -1861,6 +1861,7 @@ def SVBGRP_N : SInst<"svbgrp[_n_{d}]", "dda", "UcUsUiUl", MergeNone, "aarch64_sv let TargetGuard = "sve2p1" in { def SVFCLAMP : SInst<"svclamp[_{d}]", "dddd", "hfd", MergeNone, "aarch64_sve_fclamp", [], []>; +def SVPTRUE_COUNT : SInst<"svptrue_{d}", "}v", "QcQsQiQl", MergeNone, "aarch64_sve_ptrue_{d}", [IsOverloadNone], []>; } let TargetGuard = "sve2p1" in { diff --git a/clang/include/clang/Basic/arm_sve_sme_incl.td b/clang/include/clang/Basic/arm_sve_sme_incl.td index f68140d386473..6b1541d334a25 100644 --- a/clang/include/clang/Basic/arm_sve_sme_incl.td +++ b/clang/include/clang/Basic/arm_sve_sme_incl.td @@ -55,6 +55,7 @@ // ------------------ // P: boolean // U: unsigned +// Q: svcount // Prototype modifiers // ------------------- @@ -124,6 +125,9 @@ // Y: const pointer to uint32_t // Z: const pointer to uint64_t +// Prototype modifiers added for SVE2p1 +// }: svcount_t + class MergeType { int Value = val; string Suffix = suffix; diff --git a/clang/include/clang/Driver/Job.h b/clang/include/clang/Driver/Job.h index e866679dc1a91..df9449463c53b 100644 --- a/clang/include/clang/Driver/Job.h +++ b/clang/include/clang/Driver/Job.h @@ -258,23 +258,6 @@ class CC1Command : public Command { void setEnvironment(llvm::ArrayRef NewEnvironment) override; }; -/// Like Command, but always pretends that the wrapped command succeeded. -class ForceSuccessCommand : public Command { -public: - ForceSuccessCommand(const Action &Source_, const Tool &Creator_, - ResponseFileSupport ResponseSupport, - const char *Executable_, - const llvm::opt::ArgStringList &Arguments_, - ArrayRef Inputs, - ArrayRef Outputs = std::nullopt); - - void Print(llvm::raw_ostream &OS, const char *Terminator, bool Quote, - CrashReportInfo *CrashInfo = nullptr) const override; - - int Execute(ArrayRef> Redirects, std::string *ErrMsg, - bool *ExecutionFailed) const override; -}; - /// JobList - A sequence of jobs to perform. class JobList { public: diff --git a/clang/include/clang/Driver/Options.h b/clang/include/clang/Driver/Options.h index f7ee154b7a7ab..54c6f5faa37c2 100644 --- a/clang/include/clang/Driver/Options.h +++ b/clang/include/clang/Driver/Options.h @@ -38,6 +38,7 @@ enum ClangFlags { DXCOption = (1 << 17), CLDXCOption = (1 << 18), Ignored = (1 << 19), + TargetSpecific = (1 << 20), }; enum ID { diff --git a/clang/include/clang/Driver/Options.td b/clang/include/clang/Driver/Options.td index 93732f2b0768a..29b41002cf37b 100644 --- a/clang/include/clang/Driver/Options.td +++ b/clang/include/clang/Driver/Options.td @@ -75,6 +75,10 @@ def FlangOnlyOption : OptionFlag; // FC1Option - This option should be accepted by flang -fc1. def FC1Option : OptionFlag; +// This is a target-specific option for compilation. Using it on an unsupported +// target will lead to an err_drv_unsupported_opt_for_target error. +def TargetSpecific : OptionFlag; + // A short name to show in documentation. The name will be interpreted as rST. class DocName { string DocName = name; } @@ -89,6 +93,8 @@ class DocFlatten { bit DocFlatten = 1; } // GCC compatibility. class IgnoredGCCCompat : Flags<[HelpHidden]> {} +class TargetSpecific : Flags<[TargetSpecific]> {} + ///////// // Groups @@ -2560,6 +2566,10 @@ defm operator_names : BoolFOption<"operator-names", def fdiagnostics_absolute_paths : Flag<["-"], "fdiagnostics-absolute-paths">, Group, Flags<[CC1Option, CoreOption]>, HelpText<"Print absolute paths in diagnostics">, MarshallingInfoFlag>; +defm diagnostics_show_line_numbers : BoolFOption<"diagnostics-show-line-numbers", + DiagnosticOpts<"ShowLineNumbers">, DefaultTrue, + NegFlag, + PosFlag>; def fno_stack_protector : Flag<["-"], "fno-stack-protector">, Group, HelpText<"Disable the use of stack protectors">; def fno_strict_aliasing : Flag<["-"], "fno-strict-aliasing">, Group, @@ -3123,7 +3133,7 @@ def mdefault_visibility_export_mapping_EQ : Joined<["-"], "mdefault-visibility-e NormalizedValuesScope<"LangOptions::DefaultVisiblityExportMapping">, NormalizedValues<["None", "Explicit", "All"]>, HelpText<"Mapping between default visibility and export">, - Group, Flags<[CC1Option]>, + Group, Flags<[CC1Option,TargetSpecific]>, MarshallingInfoEnum,"None">; defm new_infallible : BoolFOption<"new-infallible", LangOpts<"NewInfallible">, DefaultFalse, @@ -3381,7 +3391,7 @@ def headerpad__max__install__names : Joined<["-"], "headerpad_max_install_names" def help : Flag<["-", "--"], "help">, Flags<[CC1Option,CC1AsOption, FC1Option, FlangOption]>, HelpText<"Display available options">, MarshallingInfoFlag>; -def ibuiltininc : Flag<["-"], "ibuiltininc">, +def ibuiltininc : Flag<["-"], "ibuiltininc">, Group, HelpText<"Enable builtin #include directories even when -nostdinc is used " "before or after -ibuiltininc. " "Using -nobuiltininc after the option disables it">; @@ -3446,9 +3456,9 @@ def l : JoinedOrSeparate<["-"], "l">, Flags<[LinkerInput, RenderJoined]>, Group; def lazy__framework : Separate<["-"], "lazy_framework">, Flags<[LinkerInput]>; def lazy__library : Separate<["-"], "lazy_library">, Flags<[LinkerInput]>; -def mlittle_endian : Flag<["-"], "mlittle-endian">, Flags<[NoXarchOption]>; +def mlittle_endian : Flag<["-"], "mlittle-endian">, Flags<[NoXarchOption,TargetSpecific]>; def EL : Flag<["-"], "EL">, Alias; -def mbig_endian : Flag<["-"], "mbig-endian">, Flags<[NoXarchOption]>; +def mbig_endian : Flag<["-"], "mbig-endian">, Flags<[NoXarchOption,TargetSpecific]>; def EB : Flag<["-"], "EB">, Alias; def m16 : Flag<["-"], "m16">, Group, Flags<[NoXarchOption, CoreOption]>; def m32 : Flag<["-"], "m32">, Group, Flags<[NoXarchOption, CoreOption]>; @@ -3507,7 +3517,7 @@ def mappletvsimulator_version_min_EQ : Joined<["-"], "mappletvsimulator-version- def mwatchos_version_min_EQ : Joined<["-"], "mwatchos-version-min=">, Group; def mwatchos_simulator_version_min_EQ : Joined<["-"], "mwatchos-simulator-version-min=">; def mwatchsimulator_version_min_EQ : Joined<["-"], "mwatchsimulator-version-min=">, Alias; -def march_EQ : Joined<["-"], "march=">, Group, Flags<[CoreOption]>, +def march_EQ : Joined<["-"], "march=">, Group, Flags<[CoreOption,TargetSpecific]>, HelpText<"For a list of available architectures for the target use '-mcpu=help'">; def masm_EQ : Joined<["-"], "masm=">, Group, Flags<[NoXarchOption]>; def inline_asm_EQ : Joined<["-"], "inline-asm=">, Group, Flags<[CC1Option]>, @@ -3532,7 +3542,7 @@ def mthreads : Joined<["-"], "mthreads">, Group, Flags<[NoXarchOption]> def mguard_EQ : Joined<["-"], "mguard=">, Group, Flags<[NoXarchOption]>, HelpText<"Enable or disable Control Flow Guard checks and guard tables emission">, Values<"none,cf,cf-nochecks">; -def mcpu_EQ : Joined<["-"], "mcpu=">, Group, +def mcpu_EQ : Joined<["-"], "mcpu=">, Group, TargetSpecific, HelpText<"For a list of available CPUs for the target use '-mcpu=help'">; def mmcu_EQ : Joined<["-"], "mmcu=">, Group; def msim : Flag<["-"], "msim">, Group; @@ -3925,9 +3935,9 @@ def maix_struct_return : Flag<["-"], "maix-struct-return">, def msvr4_struct_return : Flag<["-"], "msvr4-struct-return">, Group, Flags<[CC1Option]>, HelpText<"Return small structs in registers (PPC32 only)">; -def mxcoff_roptr : Flag<["-"], "mxcoff-roptr">, Group, Flags<[CC1Option]>, +def mxcoff_roptr : Flag<["-"], "mxcoff-roptr">, Group, Flags<[CC1Option,TargetSpecific]>, HelpText<"Place constant objects with relocatable address values in the RO data section and add -bforceimprw to the linker flags (AIX only)">; -def mno_xcoff_roptr : Flag<["-"], "mno-xcoff-roptr">, Group; +def mno_xcoff_roptr : Flag<["-"], "mno-xcoff-roptr">, Group, TargetSpecific; def mvx : Flag<["-"], "mvx">, Group; def mno_vx : Flag<["-"], "mno-vx">, Group; @@ -3943,7 +3953,7 @@ def mxcoff_build_id_EQ : Joined<["-"], "mxcoff-build-id=">, Group, M HelpText<"On AIX, request creation of a build-id string, \"0xHEXSTRING\", in the string table of the loader section inside the linked binary">; def mignore_xcoff_visibility : Flag<["-"], "mignore-xcoff-visibility">, Group, HelpText<"Not emit the visibility attribute for asm in AIX OS or give all symbols 'unspecified' visibility in XCOFF object file">, - Flags<[CC1Option]>; + Flags<[CC1Option,TargetSpecific]>; defm backchain : BoolOption<"m", "backchain", CodeGenOpts<"Backchain">, DefaultFalse, PosFlag, @@ -4184,12 +4194,13 @@ def no_cpp_precomp : Flag<["-"], "no-cpp-precomp">, Group def no_integrated_cpp : Flag<["-", "--"], "no-integrated-cpp">, Flags<[NoXarchOption]>; def no_pedantic : Flag<["-", "--"], "no-pedantic">, Group; def no__dead__strip__inits__and__terms : Flag<["-"], "no_dead_strip_inits_and_terms">; -def nobuiltininc : Flag<["-"], "nobuiltininc">, Flags<[CC1Option, CoreOption]>, +def nobuiltininc : Flag<["-"], "nobuiltininc">, Flags<[CC1Option, CoreOption]>, Group, HelpText<"Disable builtin #include directories">, MarshallingInfoNegativeFlag>; -def nogpuinc : Flag<["-"], "nogpuinc">, HelpText<"Do not add include paths for CUDA/HIP and" +def nogpuinc : Flag<["-"], "nogpuinc">, Group, + HelpText<"Do not add include paths for CUDA/HIP and" " do not include the default CUDA/HIP wrapper headers">; -def nohipwrapperinc : Flag<["-"], "nohipwrapperinc">, +def nohipwrapperinc : Flag<["-"], "nohipwrapperinc">, Group, HelpText<"Do not include the default HIP wrapper headers and include paths">; def : Flag<["-"], "nocudainc">, Alias; def nogpulib : Flag<["-"], "nogpulib">, MarshallingInfoFlag>, @@ -4206,9 +4217,9 @@ def noprebind : Flag<["-"], "noprebind">; def noprofilelib : Flag<["-"], "noprofilelib">; def noseglinkedit : Flag<["-"], "noseglinkedit">; def nostartfiles : Flag<["-"], "nostartfiles">, Group; -def nostdinc : Flag<["-"], "nostdinc">, Flags<[CoreOption]>; -def nostdlibinc : Flag<["-"], "nostdlibinc">; -def nostdincxx : Flag<["-"], "nostdinc++">, Flags<[CC1Option]>, +def nostdinc : Flag<["-"], "nostdinc">, Flags<[CoreOption]>, Group; +def nostdlibinc : Flag<["-"], "nostdlibinc">, Group; +def nostdincxx : Flag<["-"], "nostdinc++">, Flags<[CC1Option]>, Group, HelpText<"Disable standard #include directories for the C++ standard library">, MarshallingInfoNegativeFlag>; def nostdlib : Flag<["-"], "nostdlib">, Group; @@ -5258,9 +5269,12 @@ def fno_reformat : Flag<["-"], "fno-reformat">, Group, HelpText<"Dump the cooked character stream in -E mode">; defm analyzed_objects_for_unparse : OptOutFC1FFlag<"analyzed-objects-for-unparse", "", "Do not use the analyzed objects when unparsing">; -def emit_mlir : Flag<["-"], "emit-mlir">, Group, - HelpText<"Build the parse tree, then lower it to MLIR">; -def emit_fir : Flag<["-"], "emit-fir">, Alias; +def emit_fir : Flag<["-"], "emit-fir">, Group, + HelpText<"Build the parse tree, then lower it to FIR">; +def emit_mlir : Flag<["-"], "emit-mlir">, Alias; + +def emit_hlfir : Flag<["-"], "emit-hlfir">, Group, + HelpText<"Build the parse tree, then lower it to HLFIR">; } // let Flags = [FC1Option, FlangOnlyOption] diff --git a/clang/include/clang/ExtractAPI/DeclarationFragments.h b/clang/include/clang/ExtractAPI/DeclarationFragments.h index 90121a138175c..82f0c42ab8aa0 100644 --- a/clang/include/clang/ExtractAPI/DeclarationFragments.h +++ b/clang/include/clang/ExtractAPI/DeclarationFragments.h @@ -97,27 +97,37 @@ class DeclarationFragments { Declaration(Declaration) {} }; + using FragmentIterator = std::vector::iterator; + using ConstFragmentIterator = std::vector::const_iterator; + const std::vector &getFragments() const { return Fragments; } - // Add a new Fragment to the beginning of the Fragments. - DeclarationFragments &appendFront(StringRef Spelling, FragmentKind Kind, - StringRef PreciseIdentifier = "", - const Decl *Declaration = nullptr) { - Fragments.emplace(Fragments.begin(), Spelling, Kind, PreciseIdentifier, - Declaration); + FragmentIterator begin() { return Fragments.begin(); } + + FragmentIterator end() { return Fragments.end(); } + + ConstFragmentIterator cbegin() const { return Fragments.cbegin(); } + + ConstFragmentIterator cend() const { return Fragments.cend(); } + + // Add a new Fragment at an arbitrary offset. + DeclarationFragments &insert(FragmentIterator It, StringRef Spelling, + FragmentKind Kind, + StringRef PreciseIdentifier = "", + const Decl *Declaration = nullptr) { + Fragments.insert(It, + Fragment(Spelling, Kind, PreciseIdentifier, Declaration)); return *this; } - DeclarationFragments &appendFront(DeclarationFragments &&Other) { - Fragments.insert(Fragments.begin(), - std::make_move_iterator(Other.Fragments.begin()), + DeclarationFragments &insert(FragmentIterator It, + DeclarationFragments &&Other) { + Fragments.insert(It, std::make_move_iterator(Other.Fragments.begin()), std::make_move_iterator(Other.Fragments.end())); Other.Fragments.clear(); return *this; } - void removeLast() { Fragments.pop_back(); } - /// Append a new Fragment to the end of the Fragments. /// /// \returns a reference to the DeclarationFragments object itself after diff --git a/clang/include/clang/ExtractAPI/ExtractAPIVisitor.h b/clang/include/clang/ExtractAPI/ExtractAPIVisitor.h index 8b3721a4d7adb..f0882afb5a61b 100644 --- a/clang/include/clang/ExtractAPI/ExtractAPIVisitor.h +++ b/clang/include/clang/ExtractAPI/ExtractAPIVisitor.h @@ -110,15 +110,16 @@ template static void modifyRecords(const T &Records, const StringRef &Name) { for (const auto &Record : Records) { if (Name == Record.second.get()->Name) { - Record.second.get()->Declaration.removeLast(); - Record.second.get() - ->Declaration - .appendFront(" ", DeclarationFragments::FragmentKind::Text) - .appendFront("typedef", DeclarationFragments::FragmentKind::Keyword, - "", nullptr) - .append(" { ... } ", DeclarationFragments::FragmentKind::Text) - .append(Name, DeclarationFragments::FragmentKind::Identifier) - .append(";", DeclarationFragments::FragmentKind::Text); + auto &DeclFragment = Record.second->Declaration; + DeclFragment.insert(DeclFragment.begin(), " ", + DeclarationFragments::FragmentKind::Text); + DeclFragment.insert(DeclFragment.begin(), "typedef", + DeclarationFragments::FragmentKind::Keyword, "", + nullptr); + DeclFragment.insert(--DeclFragment.end(), " { ... } ", + DeclarationFragments::FragmentKind::Text); + DeclFragment.insert(--DeclFragment.end(), Name, + DeclarationFragments::FragmentKind::Identifier); break; } } diff --git a/clang/include/clang/ExtractAPI/Serialization/SerializerBase.h b/clang/include/clang/ExtractAPI/Serialization/SerializerBase.h index d8aa826e3f4f6..006e92be29555 100644 --- a/clang/include/clang/ExtractAPI/Serialization/SerializerBase.h +++ b/clang/include/clang/ExtractAPI/Serialization/SerializerBase.h @@ -7,7 +7,7 @@ //===----------------------------------------------------------------------===// /// /// \file -/// This file defines the ExtractAPI APISerializer interface. +/// This file defines the ExtractAPI APISetVisitor interface. /// //===----------------------------------------------------------------------===// @@ -15,47 +15,107 @@ #define LLVM_CLANG_EXTRACTAPI_SERIALIZATION_SERIALIZERBASE_H #include "clang/ExtractAPI/API.h" -#include "clang/ExtractAPI/APIIgnoresList.h" -#include "llvm/Support/raw_ostream.h" namespace clang { namespace extractapi { -/// Common options to customize the serializer output. -struct APISerializerOption { - /// Do not include unnecessary whitespaces to save space. - bool Compact; -}; - -/// The base interface of serializers for API information. -class APISerializer { +/// The base interface of visitors for API information. +template class APISetVisitor { public: - /// Serialize the API information to \p os. - virtual void serialize(raw_ostream &os) = 0; + void traverseAPISet() { + getDerived()->traverseGlobalVariableRecords(); -protected: - const APISet &API; + getDerived()->traverseGlobalFunctionRecords(); + + getDerived()->traverseEnumRecords(); + + getDerived()->traverseStructRecords(); + + getDerived()->traverseObjCInterfaces(); + + getDerived()->traverseObjCProtocols(); + + getDerived()->traverseMacroDefinitionRecords(); + + getDerived()->traverseTypedefRecords(); + } + + void traverseGlobalFunctionRecords() { + for (const auto &GlobalFunction : API.getGlobalFunctions()) + getDerived()->visitGlobalFunctionRecord(*GlobalFunction.second); + } + + void traverseGlobalVariableRecords() { + for (const auto &GlobalVariable : API.getGlobalVariables()) + getDerived()->visitGlobalVariableRecord(*GlobalVariable.second); + } + + void traverseEnumRecords() { + for (const auto &Enum : API.getEnums()) + getDerived()->visitEnumRecord(*Enum.second); + } - /// The list of symbols to ignore. - /// - /// Note: This should be consulted before emitting a symbol. - const APIIgnoresList &IgnoresList; + void traverseStructRecords() { + for (const auto &Struct : API.getStructs()) + getDerived()->visitStructRecord(*Struct.second); + } - APISerializerOption Options; + void traverseObjCInterfaces() { + for (const auto &Interface : API.getObjCInterfaces()) + getDerived()->visitObjCContainerRecord(*Interface.second); + } + + void traverseObjCProtocols() { + for (const auto &Protocol : API.getObjCProtocols()) + getDerived()->visitObjCContainerRecord(*Protocol.second); + } + + void traverseMacroDefinitionRecords() { + for (const auto &Macro : API.getMacros()) + getDerived()->visitMacroDefinitionRecord(*Macro.second); + } + + void traverseTypedefRecords() { + for (const auto &Typedef : API.getTypedefs()) + getDerived()->visitTypedefRecord(*Typedef.second); + } + + /// Visit a global function record. + void visitGlobalFunctionRecord(const GlobalFunctionRecord &Record){}; + + /// Visit a global variable record. + void visitGlobalVariableRecord(const GlobalVariableRecord &Record){}; + + /// Visit an enum record. + void visitEnumRecord(const EnumRecord &Record){}; + + /// Visit a struct record. + void visitStructRecord(const StructRecord &Record){}; + + /// Visit an Objective-C container record. + void visitObjCContainerRecord(const ObjCContainerRecord &Record){}; + + /// Visit a macro definition record. + void visitMacroDefinitionRecord(const MacroDefinitionRecord &Record){}; + + /// Visit a typedef record. + void visitTypedefRecord(const TypedefRecord &Record){}; + +protected: + const APISet &API; public: - APISerializer() = delete; - APISerializer(const APISerializer &) = delete; - APISerializer(APISerializer &&) = delete; - APISerializer &operator=(const APISerializer &) = delete; - APISerializer &operator=(APISerializer &&) = delete; + APISetVisitor() = delete; + APISetVisitor(const APISetVisitor &) = delete; + APISetVisitor(APISetVisitor &&) = delete; + APISetVisitor &operator=(const APISetVisitor &) = delete; + APISetVisitor &operator=(APISetVisitor &&) = delete; protected: - APISerializer(const APISet &API, const APIIgnoresList &IgnoresList, - APISerializerOption Options = {}) - : API(API), IgnoresList(IgnoresList), Options(Options) {} + APISetVisitor(const APISet &API) : API(API) {} + ~APISetVisitor() = default; - virtual ~APISerializer() = default; + Derived *getDerived() { return static_cast(this); }; }; } // namespace extractapi diff --git a/clang/include/clang/ExtractAPI/Serialization/SymbolGraphSerializer.h b/clang/include/clang/ExtractAPI/Serialization/SymbolGraphSerializer.h index 6639082bbf332..e77903f8ba08f 100644 --- a/clang/include/clang/ExtractAPI/Serialization/SymbolGraphSerializer.h +++ b/clang/include/clang/ExtractAPI/Serialization/SymbolGraphSerializer.h @@ -9,8 +9,8 @@ /// \file /// This file defines the SymbolGraphSerializer class. /// -/// Implement an APISerializer for the Symbol Graph format for ExtractAPI. -/// See https://github.com/apple/swift-docc-symbolkit. +/// Implement an APISetVisitor to serialize the APISet into the Symbol Graph +/// format for ExtractAPI. See https://github.com/apple/swift-docc-symbolkit. /// //===----------------------------------------------------------------------===// @@ -31,14 +31,18 @@ namespace extractapi { using namespace llvm::json; -/// The serializer that organizes API information in the Symbol Graph format. +/// Common options to customize the visitor output. +struct SymbolGraphSerializerOption { + /// Do not include unnecessary whitespaces to save space. + bool Compact; +}; + +/// The visitor that organizes API information in the Symbol Graph format. /// /// The Symbol Graph format (https://github.com/apple/swift-docc-symbolkit) /// models an API set as a directed graph, where nodes are symbol declarations, /// and edges are relationships between the connected symbols. -class SymbolGraphSerializer : public APISerializer { - virtual void anchor(); - +class SymbolGraphSerializer : public APISetVisitor { /// A JSON array of formatted symbols in \c APISet. Array Symbols; @@ -48,7 +52,7 @@ class SymbolGraphSerializer : public APISerializer { /// The Symbol Graph format version used by this serializer. static const VersionTuple FormatVersion; - /// Indicates whether child symbols should be serialized. This is mainly + /// Indicates whether child symbols should be visited. This is mainly /// useful for \c serializeSingleSymbolSGF. bool ShouldRecurse; @@ -59,9 +63,8 @@ class SymbolGraphSerializer : public APISerializer { /// Symbol Graph. Object serialize(); - /// Implement the APISerializer::serialize interface. Wrap serialize(void) and - /// write out the serialized JSON object to \p os. - void serialize(raw_ostream &os) override; + /// Wrap serialize(void) and write out the serialized JSON object to \p os. + void serialize(raw_ostream &os); /// Serialize a single symbol SGF. This is primarily used for libclang. /// @@ -136,35 +139,44 @@ class SymbolGraphSerializer : public APISerializer { void serializeRelationship(RelationshipKind Kind, SymbolReference Source, SymbolReference Target); - /// Serialize a global function record. - void serializeGlobalFunctionRecord(const GlobalFunctionRecord &Record); +protected: + /// The list of symbols to ignore. + /// + /// Note: This should be consulted before emitting a symbol. + const APIIgnoresList &IgnoresList; + + SymbolGraphSerializerOption Options; + +public: + /// Visit a global function record. + void visitGlobalFunctionRecord(const GlobalFunctionRecord &Record); - /// Serialize a global variable record. - void serializeGlobalVariableRecord(const GlobalVariableRecord &Record); + /// Visit a global variable record. + void visitGlobalVariableRecord(const GlobalVariableRecord &Record); - /// Serialize an enum record. - void serializeEnumRecord(const EnumRecord &Record); + /// Visit an enum record. + void visitEnumRecord(const EnumRecord &Record); - /// Serialize a struct record. - void serializeStructRecord(const StructRecord &Record); + /// Visit a struct record. + void visitStructRecord(const StructRecord &Record); - /// Serialize an Objective-C container record. - void serializeObjCContainerRecord(const ObjCContainerRecord &Record); + /// Visit an Objective-C container record. + void visitObjCContainerRecord(const ObjCContainerRecord &Record); - /// Serialize a macro definition record. - void serializeMacroDefinitionRecord(const MacroDefinitionRecord &Record); + /// Visit a macro definition record. + void visitMacroDefinitionRecord(const MacroDefinitionRecord &Record); - /// Serialize a typedef record. - void serializeTypedefRecord(const TypedefRecord &Record); + /// Visit a typedef record. + void visitTypedefRecord(const TypedefRecord &Record); + /// Serialize a single record. void serializeSingleRecord(const APIRecord *Record); -public: SymbolGraphSerializer(const APISet &API, const APIIgnoresList &IgnoresList, - APISerializerOption Options = {}, + SymbolGraphSerializerOption Options = {}, bool ShouldRecurse = true) - : APISerializer(API, IgnoresList, Options), ShouldRecurse(ShouldRecurse) { - } + : APISetVisitor(API), ShouldRecurse(ShouldRecurse), + IgnoresList(IgnoresList), Options(Options) {} }; } // namespace extractapi diff --git a/clang/include/clang/Frontend/TextDiagnostic.h b/clang/include/clang/Frontend/TextDiagnostic.h index a2eec46beccd1..7eb0ab0cdc9bc 100644 --- a/clang/include/clang/Frontend/TextDiagnostic.h +++ b/clang/include/clang/Frontend/TextDiagnostic.h @@ -103,7 +103,8 @@ class TextDiagnostic : public DiagnosticRenderer { SmallVectorImpl &Ranges, ArrayRef Hints); - void emitSnippet(StringRef SourceLine); + void emitSnippet(StringRef SourceLine, unsigned MaxLineNoDisplayWidth, + unsigned LineNo); void emitParseableFixits(ArrayRef Hints, const SourceManager &SM); }; diff --git a/clang/include/clang/Lex/HeaderSearch.h b/clang/include/clang/Lex/HeaderSearch.h index 49fb99c1483ce..131dbdcc20007 100644 --- a/clang/include/clang/Lex/HeaderSearch.h +++ b/clang/include/clang/Lex/HeaderSearch.h @@ -482,7 +482,7 @@ class HeaderSearch { OptionalFileEntryRef LookupFile( StringRef Filename, SourceLocation IncludeLoc, bool isAngled, ConstSearchDirIterator FromDir, ConstSearchDirIterator *CurDir, - ArrayRef> Includers, + ArrayRef> Includers, SmallVectorImpl *SearchPath, SmallVectorImpl *RelativePath, Module *RequestingModule, ModuleMap::KnownHeader *SuggestedModule, bool *IsMapped, bool *IsFrameworkFound, bool SkipCache = false, @@ -553,10 +553,10 @@ class HeaderSearch { /// macro. /// /// This routine does not consider the effect of \#import - bool isFileMultipleIncludeGuarded(const FileEntry *File); + bool isFileMultipleIncludeGuarded(const FileEntry *File) const; /// Determine whether the given file is known to have ever been \#imported. - bool hasFileBeenImported(const FileEntry *File) { + bool hasFileBeenImported(const FileEntry *File) const { const HeaderFileInfo *FI = getExistingFileInfo(File); return FI && FI->isImport; } @@ -637,9 +637,9 @@ class HeaderSearch { bool AllowExtraModuleMapSearch = false); /// Try to find a module map file in the given directory, returning - /// \c nullptr if none is found. - const FileEntry *lookupModuleMapFile(const DirectoryEntry *Dir, - bool IsFramework); + /// \c nullopt if none is found. + OptionalFileEntryRef lookupModuleMapFile(const DirectoryEntry *Dir, + bool IsFramework); /// Determine whether there is a module map that may map the header /// with the given file name to a (sub)module. @@ -659,7 +659,7 @@ class HeaderSearch { /// /// \param File The header that we wish to map to a module. /// \param AllowTextual Whether we want to find textual headers too. - ModuleMap::KnownHeader findModuleForHeader(const FileEntry *File, + ModuleMap::KnownHeader findModuleForHeader(FileEntryRef File, bool AllowTextual = false, bool AllowExcluded = false) const; @@ -670,8 +670,12 @@ class HeaderSearch { /// /// \ref findModuleForHeader should typically be used instead of this. ArrayRef - findAllModulesForHeader(const FileEntry *File, - bool AllowCreation = true) const; + findAllModulesForHeader(FileEntryRef File) const; + + /// Like \ref findAllModulesForHeader, but do not attempt to infer module + /// ownership from umbrella headers if we've not already done so. + ArrayRef + findResolvedModulesForHeader(const FileEntry *File) const; /// Read the contents of the given module map file. /// @@ -686,8 +690,8 @@ class HeaderSearch { /// used to resolve paths within the module (this is required when /// building the module from preprocessed source). /// \returns true if an error occurred, false otherwise. - bool loadModuleMapFile(const FileEntry *File, bool IsSystem, - FileID ID = FileID(), unsigned *Offset = nullptr, + bool loadModuleMapFile(FileEntryRef File, bool IsSystem, FileID ID = FileID(), + unsigned *Offset = nullptr, StringRef OriginalModuleMapFile = StringRef()); /// Collect the set of all known, top-level modules. @@ -756,8 +760,7 @@ class HeaderSearch { /// /// \return \c true if the file can be used, \c false if we are not permitted to /// find this file due to requirements from \p RequestingModule. - bool findUsableModuleForHeader(const FileEntry *File, - const DirectoryEntry *Root, + bool findUsableModuleForHeader(FileEntryRef File, const DirectoryEntry *Root, Module *RequestingModule, ModuleMap::KnownHeader *SuggestedModule, bool IsSystemHeaderDir); @@ -768,7 +771,7 @@ class HeaderSearch { /// \return \c true if the file can be used, \c false if we are not permitted to /// find this file due to requirements from \p RequestingModule. bool findUsableModuleForFrameworkHeader( - const FileEntry *File, StringRef FrameworkName, Module *RequestingModule, + FileEntryRef File, StringRef FrameworkName, Module *RequestingModule, ModuleMap::KnownHeader *SuggestedModule, bool IsSystemFramework); /// Look up the file with the specified name and determine its owning @@ -867,7 +870,7 @@ class HeaderSearch { /// path is relative to a system header directory. std::string suggestPathToFileForDiagnostics(const FileEntry *File, llvm::StringRef MainFile, - bool *IsSystem = nullptr); + bool *IsSystem = nullptr) const; /// Suggest a path by which the specified file could be found, for use in /// diagnostics to suggest a #include. Returned path will only contain forward @@ -881,7 +884,7 @@ class HeaderSearch { std::string suggestPathToFileForDiagnostics(llvm::StringRef File, llvm::StringRef WorkingDir, llvm::StringRef MainFile, - bool *IsSystem = nullptr); + bool *IsSystem = nullptr) const; void PrintStats(); @@ -904,8 +907,7 @@ class HeaderSearch { LMM_InvalidModuleMap }; - LoadModuleMapResult loadModuleMapFileImpl(const FileEntry *File, - bool IsSystem, + LoadModuleMapResult loadModuleMapFileImpl(FileEntryRef File, bool IsSystem, DirectoryEntryRef Dir, FileID ID = FileID(), unsigned *Offset = nullptr); diff --git a/clang/include/clang/Lex/ModuleMap.h b/clang/include/clang/Lex/ModuleMap.h index 92697fe7deaa1..83c227b38e1bb 100644 --- a/clang/include/clang/Lex/ModuleMap.h +++ b/clang/include/clang/Lex/ModuleMap.h @@ -67,10 +67,8 @@ class ModuleMapCallbacks { /// Called when an umbrella header is added during module map parsing. /// - /// \param FileMgr FileManager instance /// \param Header The umbrella header to collect. - virtual void moduleMapAddUmbrellaHeader(FileManager *FileMgr, - const FileEntry *Header) {} + virtual void moduleMapAddUmbrellaHeader(FileEntryRef Header) {} }; class ModuleMap { @@ -84,7 +82,7 @@ class ModuleMap { /// The directory used for Clang-supplied, builtin include headers, /// such as "stdint.h". - const DirectoryEntry *BuiltinIncludeDir = nullptr; + OptionalDirectoryEntryRefDegradesToDirectoryEntryPtr BuiltinIncludeDir; /// Language options used to parse the module map itself. /// @@ -366,22 +364,22 @@ class ModuleMap { /// /// \param IntermediateDirs On success, contains the set of directories /// searched before finding \p File. - KnownHeader findHeaderInUmbrellaDirs(const FileEntry *File, - SmallVectorImpl &IntermediateDirs); + KnownHeader findHeaderInUmbrellaDirs( + FileEntryRef File, SmallVectorImpl &IntermediateDirs); /// Given that \p File is not in the Headers map, look it up within /// umbrella directories and find or create a module for it. - KnownHeader findOrCreateModuleForHeaderInUmbrellaDir(const FileEntry *File); + KnownHeader findOrCreateModuleForHeaderInUmbrellaDir(FileEntryRef File); /// A convenience method to determine if \p File is (possibly nested) /// in an umbrella directory. - bool isHeaderInUmbrellaDirs(const FileEntry *File) { - SmallVector IntermediateDirs; + bool isHeaderInUmbrellaDirs(FileEntryRef File) { + SmallVector IntermediateDirs; return static_cast(findHeaderInUmbrellaDirs(File, IntermediateDirs)); } - Module *inferFrameworkModule(const DirectoryEntry *FrameworkDir, - Attributes Attrs, Module *Parent); + Module *inferFrameworkModule(DirectoryEntryRef FrameworkDir, Attributes Attrs, + Module *Parent); public: /// Construct a new module map. @@ -407,7 +405,7 @@ class ModuleMap { /// Set the directory that contains Clang-supplied include /// files, such as our stdarg.h or tgmath.h. - void setBuiltinIncludeDir(const DirectoryEntry *Dir) { + void setBuiltinIncludeDir(DirectoryEntryRef Dir) { BuiltinIncludeDir = Dir; } @@ -439,8 +437,7 @@ class ModuleMap { /// \returns The module KnownHeader, which provides the module that owns the /// given header file. The KnownHeader is default constructed to indicate /// that no module owns this header file. - KnownHeader findModuleForHeader(const FileEntry *File, - bool AllowTextual = false, + KnownHeader findModuleForHeader(FileEntryRef File, bool AllowTextual = false, bool AllowExcluded = false); /// Retrieve all the modules that contain the given header file. Note that @@ -448,13 +445,9 @@ class ModuleMap { /// and does not consult the external source. (Those checks are the /// responsibility of \ref HeaderSearch.) /// - /// \param AllowCreation Whether to allow inference of a new submodule, or to - /// only return existing known modules. - /// /// Typically, \ref findModuleForHeader should be used instead, as it picks /// the preferred module for the header. - ArrayRef findAllModulesForHeader(const FileEntry *File, - bool AllowCreation = true); + ArrayRef findAllModulesForHeader(FileEntryRef File); /// Like \ref findAllModulesForHeader, but do not attempt to infer module /// ownership from umbrella headers if we've not already done so. @@ -591,8 +584,8 @@ class ModuleMap { /// Infer the contents of a framework module map from the given /// framework directory. - Module *inferFrameworkModule(const DirectoryEntry *FrameworkDir, - bool IsSystem, Module *Parent); + Module *inferFrameworkModule(DirectoryEntryRef FrameworkDir, bool IsSystem, + Module *Parent); /// Create a new top-level module that is shadowed by /// \p ShadowingModule. @@ -729,8 +722,8 @@ class ModuleMap { /// /// \returns true if an error occurred, false otherwise. bool parseModuleMapFile(const FileEntry *File, bool IsSystem, - const DirectoryEntry *HomeDir, - FileID ID = FileID(), unsigned *Offset = nullptr, + DirectoryEntryRef HomeDir, FileID ID = FileID(), + unsigned *Offset = nullptr, SourceLocation ExternModuleLoc = SourceLocation()); /// Dump the contents of the module map, for debugging purposes. diff --git a/clang/include/clang/Lex/Preprocessor.h b/clang/include/clang/Lex/Preprocessor.h index 8bdaf25e9b870..8fbc002059a86 100644 --- a/clang/include/clang/Lex/Preprocessor.h +++ b/clang/include/clang/Lex/Preprocessor.h @@ -625,7 +625,7 @@ class Preprocessor { /// The directory that the main file should be considered to occupy, /// if it does not correspond to a real file (as happens when building a /// module). - const DirectoryEntry *MainFileDir = nullptr; + OptionalDirectoryEntryRef MainFileDir; /// The number of bytes that we will initially skip when entering the /// main file, along with a flag that indicates whether skipping this number @@ -2012,9 +2012,7 @@ class Preprocessor { /// Set the directory in which the main file should be considered /// to have been found, if it is not a real file. - void setMainFileDir(const DirectoryEntry *Dir) { - MainFileDir = Dir; - } + void setMainFileDir(DirectoryEntryRef Dir) { MainFileDir = Dir; } /// Instruct the preprocessor to skip part of the main source file. /// diff --git a/clang/include/clang/Lex/Token.h b/clang/include/clang/Lex/Token.h index 7fd48b1b4391e..1409e2c58b550 100644 --- a/clang/include/clang/Lex/Token.h +++ b/clang/include/clang/Lex/Token.h @@ -117,8 +117,13 @@ class Token { } /// Return true if this is any of tok::annot_* kind tokens. - bool isAnnotation() const { - return tok::isAnnotation(getKind()); + bool isAnnotation() const { return tok::isAnnotation(getKind()); } + + /// Return true if the token is a keyword that is parsed in the same + /// position as a standard attribute, but that has semantic meaning + /// and so cannot be a true attribute. + bool isRegularKeywordAttribute() const { + return tok::isRegularKeywordAttribute(getKind()); } /// Return a source location identifier for the specified diff --git a/clang/include/clang/Parse/Parser.h b/clang/include/clang/Parse/Parser.h index 43ea50a71f744..992d92c990e11 100644 --- a/clang/include/clang/Parse/Parser.h +++ b/clang/include/clang/Parse/Parser.h @@ -2691,6 +2691,18 @@ class Parser : public CodeCompletionHandler { return LO.DoubleSquareBracketAttributes; } + /// Return true if the next token should be treated as a [[]] attribute, + /// or as a keyword that behaves like one. The former is only true if + /// [[]] attributes are enabled, whereas the latter is true whenever + /// such a keyword appears. The arguments are as for + /// isCXX11AttributeSpecifier. + bool isAllowedCXX11AttributeSpecifier(bool Disambiguate = false, + bool OuterMightBeMessageSend = false) { + return (Tok.isRegularKeywordAttribute() || + (standardAttributesAllowed() && + isCXX11AttributeSpecifier(Disambiguate, OuterMightBeMessageSend))); + } + // Check for the start of an attribute-specifier-seq in a context where an // attribute is not allowed. bool CheckProhibitedCXX11Attribute() { @@ -2703,11 +2715,13 @@ class Parser : public CodeCompletionHandler { bool DiagnoseProhibitedCXX11Attribute(); void CheckMisplacedCXX11Attribute(ParsedAttributes &Attrs, SourceLocation CorrectLocation) { - if (!standardAttributesAllowed()) - return; - if ((Tok.isNot(tok::l_square) || NextToken().isNot(tok::l_square)) && - Tok.isNot(tok::kw_alignas)) - return; + if (!Tok.isRegularKeywordAttribute()) { + if (!standardAttributesAllowed()) + return; + if ((Tok.isNot(tok::l_square) || NextToken().isNot(tok::l_square)) && + Tok.isNot(tok::kw_alignas)) + return; + } DiagnoseMisplacedCXX11Attribute(Attrs, CorrectLocation); } void DiagnoseMisplacedCXX11Attribute(ParsedAttributes &Attrs, @@ -2721,7 +2735,7 @@ class Parser : public CodeCompletionHandler { SourceLocation FixItLoc = SourceLocation()) { if (Attrs.Range.isInvalid()) return; - DiagnoseProhibitedAttributes(Attrs.Range, FixItLoc); + DiagnoseProhibitedAttributes(Attrs, FixItLoc); Attrs.clear(); } @@ -2729,10 +2743,10 @@ class Parser : public CodeCompletionHandler { SourceLocation FixItLoc = SourceLocation()) { if (Attrs.Range.isInvalid()) return; - DiagnoseProhibitedAttributes(Attrs.Range, FixItLoc); + DiagnoseProhibitedAttributes(Attrs, FixItLoc); Attrs.clearListOnly(); } - void DiagnoseProhibitedAttributes(const SourceRange &Range, + void DiagnoseProhibitedAttributes(const ParsedAttributesView &Attrs, SourceLocation FixItLoc); // Forbid C++11 and C2x attributes that appear on certain syntactic locations @@ -2741,7 +2755,8 @@ class Parser : public CodeCompletionHandler { // For the most cases we don't want to warn on unknown type attributes, but // left them to later diagnoses. However, for a few cases like module // declarations and module import declarations, we should do it. - void ProhibitCXX11Attributes(ParsedAttributes &Attrs, unsigned DiagID, + void ProhibitCXX11Attributes(ParsedAttributes &Attrs, unsigned AttrDiagID, + unsigned KeywordDiagId, bool DiagnoseEmptyAttrs = false, bool WarnOnUnknownAttrs = false); @@ -2795,7 +2810,7 @@ class Parser : public CodeCompletionHandler { bool MaybeParseAttributes(unsigned WhichAttrKinds, ParsedAttributes &Attrs, LateParsedAttrList *LateAttrs = nullptr) { if (Tok.isOneOf(tok::kw___attribute, tok::kw___declspec) || - (standardAttributesAllowed() && isCXX11AttributeSpecifier())) { + isAllowedCXX11AttributeSpecifier()) { ParseAttributes(WhichAttrKinds, Attrs, LateAttrs); return true; } @@ -2847,7 +2862,7 @@ class Parser : public CodeCompletionHandler { } } void MaybeParseCXX11Attributes(Declarator &D) { - if (standardAttributesAllowed() && isCXX11AttributeSpecifier()) { + if (isAllowedCXX11AttributeSpecifier()) { ParsedAttributes Attrs(AttrFactory); ParseCXX11Attributes(Attrs); D.takeAttributes(Attrs); @@ -2856,8 +2871,7 @@ class Parser : public CodeCompletionHandler { bool MaybeParseCXX11Attributes(ParsedAttributes &Attrs, bool OuterMightBeMessageSend = false) { - if (standardAttributesAllowed() && - isCXX11AttributeSpecifier(false, OuterMightBeMessageSend)) { + if (isAllowedCXX11AttributeSpecifier(false, OuterMightBeMessageSend)) { ParseCXX11Attributes(Attrs); return true; } diff --git a/clang/include/clang/Sema/DeclSpec.h b/clang/include/clang/Sema/DeclSpec.h index b0bf87dc18d79..c63378c732908 100644 --- a/clang/include/clang/Sema/DeclSpec.h +++ b/clang/include/clang/Sema/DeclSpec.h @@ -1972,9 +1972,10 @@ class Declarator { InventedTemplateParameterList(nullptr) { assert(llvm::all_of(DeclarationAttrs, [](const ParsedAttr &AL) { - return AL.isStandardAttributeSyntax(); + return (AL.isStandardAttributeSyntax() || + AL.isRegularKeywordAttribute()); }) && - "DeclarationAttrs may only contain [[]] attributes"); + "DeclarationAttrs may only contain [[]] and keyword attributes"); } ~Declarator() { @@ -2619,14 +2620,6 @@ class Declarator { return false; } - /// Return a source range list of C++11 attributes associated - /// with the declarator. - void getCXX11AttributeRanges(SmallVectorImpl &Ranges) { - for (const ParsedAttr &AL : Attrs) - if (AL.isCXX11Attribute()) - Ranges.push_back(AL.getRange()); - } - void setAsmLabel(Expr *E) { AsmLabel = E; } Expr *getAsmLabel() const { return AsmLabel; } diff --git a/clang/include/clang/Sema/Sema.h b/clang/include/clang/Sema/Sema.h index 7447755ef2df2..d2cb0ef261fbe 100644 --- a/clang/include/clang/Sema/Sema.h +++ b/clang/include/clang/Sema/Sema.h @@ -1624,7 +1624,7 @@ class Sema final { /// Indicate RISC-V vector builtin functions enabled or not. bool DeclareRISCVVBuiltins = false; - /// Indicate RISC-V Sifive vector builtin functions enabled or not. + /// Indicate RISC-V SiFive vector builtin functions enabled or not. bool DeclareRISCVVectorBuiltins = false; private: @@ -4153,10 +4153,9 @@ class Sema final { bool resolveAndFixAddressOfSingleOverloadCandidate( ExprResult &SrcExpr, bool DoFunctionPointerConversion = false); - FunctionDecl * - ResolveSingleFunctionTemplateSpecialization(OverloadExpr *ovl, - bool Complain = false, - DeclAccessPair *Found = nullptr); + FunctionDecl *ResolveSingleFunctionTemplateSpecialization( + OverloadExpr *ovl, bool Complain = false, DeclAccessPair *Found = nullptr, + TemplateSpecCandidateSet *FailedTSC = nullptr); bool ResolveAndFixSingleFunctionTemplateSpecialization( ExprResult &SrcExpr, bool DoFunctionPointerConversion = false, @@ -9140,11 +9139,12 @@ class Sema final { TypeSourceInfo *ReplaceAutoTypeSourceInfo(TypeSourceInfo *TypeWithAuto, QualType Replacement); - TemplateDeductionResult DeduceAutoType(TypeLoc AutoTypeLoc, Expr *Initializer, - QualType &Result, - sema::TemplateDeductionInfo &Info, - bool DependentDeduction = false, - bool IgnoreConstraints = false); + TemplateDeductionResult + DeduceAutoType(TypeLoc AutoTypeLoc, Expr *Initializer, QualType &Result, + sema::TemplateDeductionInfo &Info, + bool DependentDeduction = false, + bool IgnoreConstraints = false, + TemplateSpecCandidateSet *FailedTSC = nullptr); void DiagnoseAutoDeductionFailure(VarDecl *VDecl, Expr *Init); bool DeduceReturnType(FunctionDecl *FD, SourceLocation Loc, bool Diagnose = true); @@ -11324,6 +11324,11 @@ class Sema final { void checkDeclIsAllowedInOpenMPTarget(Expr *E, Decl *D, SourceLocation IdLoc = SourceLocation()); + + /// Adds OMPDeclareTargetDeclAttr to referenced variables in declare target + /// directive. + void ActOnOpenMPDeclareTargetInitializer(Decl *D); + /// Finishes analysis of the deferred functions calls that may be declared as /// host/nohost during device/host compilation. void finalizeOpenMPDelayedAnalysis(const FunctionDecl *Caller, @@ -13764,7 +13769,6 @@ class Sema final { Scope *CurScope; mutable IdentifierInfo *Ident_super; - mutable IdentifierInfo *Ident___float128; /// Nullability type specifiers. IdentifierInfo *Ident__Nonnull = nullptr; @@ -13813,7 +13817,6 @@ class Sema final { } IdentifierInfo *getSuperIdentifier() const; - IdentifierInfo *getFloat128Identifier() const; ObjCContainerDecl *getObjCDeclContext() const; diff --git a/clang/include/clang/Serialization/GlobalModuleIndex.h b/clang/include/clang/Serialization/GlobalModuleIndex.h index 9d6b52a97f52e..d82e0dd294b90 100644 --- a/clang/include/clang/Serialization/GlobalModuleIndex.h +++ b/clang/include/clang/Serialization/GlobalModuleIndex.h @@ -136,12 +136,6 @@ class GlobalModuleIndex { /// The caller accepts ownership of the returned object. IdentifierIterator *createIdentifierIterator() const; - /// Retrieve the set of modules that have up-to-date indexes. - /// - /// \param ModuleFiles Will be populated with the set of module files that - /// have been indexed. - void getKnownModules(llvm::SmallVectorImpl &ModuleFiles); - /// Retrieve the set of module files on which the given module file /// directly depends. void getModuleDependencies(ModuleFile *File, diff --git a/clang/include/clang/StaticAnalyzer/Checkers/Checkers.td b/clang/include/clang/StaticAnalyzer/Checkers/Checkers.td index 094b3a69c2302..74f3dad585ee7 100644 --- a/clang/include/clang/StaticAnalyzer/Checkers/Checkers.td +++ b/clang/include/clang/StaticAnalyzer/Checkers/Checkers.td @@ -359,29 +359,6 @@ def ErrnoModeling : Checker<"Errno">, HelpText<"Make the special value 'errno' available to other checkers.">, Documentation; -def StdCLibraryFunctionsChecker : Checker<"StdCLibraryFunctions">, - HelpText<"Improve modeling of the C standard library functions">, - // Uninitialized value check is a mandatory dependency. This Checker asserts - // that arguments are always initialized. - Dependencies<[CallAndMessageModeling]>, - CheckerOptions<[ - CmdLineOption, - CmdLineOption - ]>, - Documentation, - Hidden; - def TrustNonnullChecker : Checker<"TrustNonnull">, HelpText<"Trust that returns from framework methods annotated with _Nonnull " "are not null">, @@ -583,11 +560,24 @@ def BlockInCriticalSectionChecker : Checker<"BlockInCriticalSection">, HelpText<"Check for calls to blocking functions inside a critical section">, Documentation; -def StdCLibraryFunctionArgsChecker : Checker<"StdCLibraryFunctionArgs">, - HelpText<"Check constraints of arguments of C standard library functions, " - "such as whether the parameter of isalpha is in the range [0, 255] " - "or is EOF.">, - Dependencies<[StdCLibraryFunctionsChecker]>, +def StdCLibraryFunctionsChecker : Checker<"StdCLibraryFunctions">, + HelpText<"Check for invalid arguments of C standard library functions, " + "and apply relations between arguments and return value">, + CheckerOptions<[ + CmdLineOption, + CmdLineOption + ]>, WeakDependencies<[CallAndMessageChecker, NonNullParamChecker]>, Documentation; @@ -1618,7 +1608,6 @@ def DebugIteratorModeling : Checker<"DebugIteratorModeling">, def StdCLibraryFunctionsTesterChecker : Checker<"StdCLibraryFunctionsTester">, HelpText<"Add test functions to the summary map, so testing of individual " "summary constituents becomes possible.">, - Dependencies<[StdCLibraryFunctionsChecker]>, Documentation; } // end "debug" diff --git a/clang/include/clang/Tooling/Inclusions/HeaderAnalysis.h b/clang/include/clang/Tooling/Inclusions/HeaderAnalysis.h index 760b8dd0879c9..84d90c44de070 100644 --- a/clang/include/clang/Tooling/Inclusions/HeaderAnalysis.h +++ b/clang/include/clang/Tooling/Inclusions/HeaderAnalysis.h @@ -28,7 +28,7 @@ namespace tooling { /// This function can be expensive as it may scan the source code to find out /// dont-include-me pattern heuristically. bool isSelfContainedHeader(const FileEntry *FE, const SourceManager &SM, - HeaderSearch &HeaderInfo); + const HeaderSearch &HeaderInfo); /// This scans the given source code to see if it contains #import(s). bool codeContainsImports(llvm::StringRef Code); diff --git a/clang/include/clang/Tooling/Tooling.h b/clang/include/clang/Tooling/Tooling.h index 7a1c62e3a3d57..13c1b51bf85fb 100644 --- a/clang/include/clang/Tooling/Tooling.h +++ b/clang/include/clang/Tooling/Tooling.h @@ -361,11 +361,6 @@ class ClangTool { /// append them to ASTs. int buildASTs(std::vector> &ASTs); - /// Sets whether working directory should be restored after calling run(). By - /// default, working directory is restored. However, it could be useful to - /// turn this off when running on multiple threads to avoid the raciness. - void setRestoreWorkingDir(bool RestoreCWD); - /// Sets whether an error message should be printed out if an action fails. By /// default, if an action fails, a message is printed out to stderr. void setPrintErrorMessage(bool PrintErrorMessage); @@ -395,7 +390,6 @@ class ClangTool { DiagnosticConsumer *DiagConsumer = nullptr; - bool RestoreCWD = true; bool PrintErrorMessage = true; }; diff --git a/clang/include/module.modulemap b/clang/include/module.modulemap index 9fea3620100f4..6ea613c70306f 100644 --- a/clang/include/module.modulemap +++ b/clang/include/module.modulemap @@ -55,6 +55,7 @@ module Clang_Basic { textual header "clang/Basic/BuiltinsPPC.def" textual header "clang/Basic/BuiltinsRISCV.def" textual header "clang/Basic/BuiltinsRISCVVector.def" + textual header "clang/Basic/BuiltinsSME.def" textual header "clang/Basic/BuiltinsSVE.def" textual header "clang/Basic/BuiltinsSystemZ.def" textual header "clang/Basic/BuiltinsVE.def" diff --git a/clang/lib/AST/ASTContext.cpp b/clang/lib/AST/ASTContext.cpp index 7758c30725a3c..9af6fa67db1ef 100644 --- a/clang/lib/AST/ASTContext.cpp +++ b/clang/lib/AST/ASTContext.cpp @@ -499,10 +499,7 @@ const RawComment *ASTContext::getRawCommentForAnyRedecl( // Any redeclarations of D that we haven't checked for comments yet? // We can't use DenseMap::iterator directly since it'd get invalid. auto LastCheckedRedecl = [this, CanonicalD]() -> const Decl * { - auto LookupRes = CommentlessRedeclChains.find(CanonicalD); - if (LookupRes != CommentlessRedeclChains.end()) - return LookupRes->second; - return nullptr; + return CommentlessRedeclChains.lookup(CanonicalD); }(); for (const auto Redecl : D->redecls()) { @@ -1523,11 +1520,7 @@ ASTContext::setTemplateOrSpecializationInfo(VarDecl *Inst, NamedDecl * ASTContext::getInstantiatedFromUsingDecl(NamedDecl *UUD) { - auto Pos = InstantiatedFromUsingDecl.find(UUD); - if (Pos == InstantiatedFromUsingDecl.end()) - return nullptr; - - return Pos->second; + return InstantiatedFromUsingDecl.lookup(UUD); } void @@ -1546,11 +1539,7 @@ ASTContext::setInstantiatedFromUsingDecl(NamedDecl *Inst, NamedDecl *Pattern) { UsingEnumDecl * ASTContext::getInstantiatedFromUsingEnumDecl(UsingEnumDecl *UUD) { - auto Pos = InstantiatedFromUsingEnumDecl.find(UUD); - if (Pos == InstantiatedFromUsingEnumDecl.end()) - return nullptr; - - return Pos->second; + return InstantiatedFromUsingEnumDecl.lookup(UUD); } void ASTContext::setInstantiatedFromUsingEnumDecl(UsingEnumDecl *Inst, @@ -1561,12 +1550,7 @@ void ASTContext::setInstantiatedFromUsingEnumDecl(UsingEnumDecl *Inst, UsingShadowDecl * ASTContext::getInstantiatedFromUsingShadowDecl(UsingShadowDecl *Inst) { - llvm::DenseMap::const_iterator Pos - = InstantiatedFromUsingShadowDecl.find(Inst); - if (Pos == InstantiatedFromUsingShadowDecl.end()) - return nullptr; - - return Pos->second; + return InstantiatedFromUsingShadowDecl.lookup(Inst); } void @@ -1577,12 +1561,7 @@ ASTContext::setInstantiatedFromUsingShadowDecl(UsingShadowDecl *Inst, } FieldDecl *ASTContext::getInstantiatedFromUnnamedFieldDecl(FieldDecl *Field) { - llvm::DenseMap::iterator Pos - = InstantiatedFromUnnamedFieldDecl.find(Field); - if (Pos == InstantiatedFromUnnamedFieldDecl.end()) - return nullptr; - - return Pos->second; + return InstantiatedFromUnnamedFieldDecl.lookup(Field); } void ASTContext::setInstantiatedFromUnnamedFieldDecl(FieldDecl *Inst, @@ -11455,6 +11434,17 @@ static QualType DecodeTypeFromStr(const char *&Str, const ASTContext &Context, Type = Context.getScalableVectorType(ElementType, NumElements); break; } + case 'Q': { + switch (*Str++) { + case 'a': { + Type = Context.SveCountTy; + break; + } + default: + llvm_unreachable("Unexpected target builtin type"); + } + break; + } case 'V': { char *End; unsigned NumElements = strtoul(Str, &End, 10); diff --git a/clang/lib/AST/ASTImporter.cpp b/clang/lib/AST/ASTImporter.cpp index 6e2566b638609..6c04bc80270ae 100644 --- a/clang/lib/AST/ASTImporter.cpp +++ b/clang/lib/AST/ASTImporter.cpp @@ -8994,11 +8994,7 @@ Expected ASTImporter::Import(const Attr *FromAttr) { } Decl *ASTImporter::GetAlreadyImportedOrNull(const Decl *FromD) const { - auto Pos = ImportedDecls.find(FromD); - if (Pos != ImportedDecls.end()) - return Pos->second; - else - return nullptr; + return ImportedDecls.lookup(FromD); } TranslationUnitDecl *ASTImporter::GetFromTU(Decl *ToD) { diff --git a/clang/lib/AST/Decl.cpp b/clang/lib/AST/Decl.cpp index e441c338a2c76..85d8f11aafde2 100644 --- a/clang/lib/AST/Decl.cpp +++ b/clang/lib/AST/Decl.cpp @@ -3322,7 +3322,7 @@ bool FunctionDecl::isInlineBuiltinDeclaration() const { return false; ASTContext &Context = getASTContext(); - switch (Context.GetGVALinkageForFunction(this)) { + switch (Context.GetGVALinkageForFunction(Definition)) { case GVA_Internal: case GVA_DiscardableODR: case GVA_StrongODR: @@ -3331,6 +3331,7 @@ bool FunctionDecl::isInlineBuiltinDeclaration() const { case GVA_StrongExternal: return true; } + llvm_unreachable("Unknown GVALinkage"); } bool FunctionDecl::isDestroyingOperatorDelete() const { diff --git a/clang/lib/AST/Expr.cpp b/clang/lib/AST/Expr.cpp index 958f4e9042319..c3c00932cee4e 100644 --- a/clang/lib/AST/Expr.cpp +++ b/clang/lib/AST/Expr.cpp @@ -4857,6 +4857,7 @@ unsigned AtomicExpr::getNumSubExprs(AtomicOp Op) { case AO__hip_atomic_exchange: case AO__hip_atomic_fetch_add: + case AO__hip_atomic_fetch_sub: case AO__hip_atomic_fetch_and: case AO__hip_atomic_fetch_or: case AO__hip_atomic_fetch_xor: diff --git a/clang/lib/AST/ExternalASTMerger.cpp b/clang/lib/AST/ExternalASTMerger.cpp index a2ef270d7a9c5..8bad3b36244e1 100644 --- a/clang/lib/AST/ExternalASTMerger.cpp +++ b/clang/lib/AST/ExternalASTMerger.cpp @@ -187,10 +187,7 @@ class LazyASTImporter : public ASTImporter { /// Implements the ASTImporter interface for tracking back a declaration /// to its original declaration it came from. Decl *GetOriginalDecl(Decl *To) override { - auto It = ToOrigin.find(To); - if (It != ToOrigin.end()) - return It->second; - return nullptr; + return ToOrigin.lookup(To); } /// Whenever a DeclContext is imported, ensure that ExternalASTSource's origin @@ -541,4 +538,3 @@ void ExternalASTMerger::FindExternalLexicalDecls( return false; }); } - diff --git a/clang/lib/AST/Interp/ByteCodeExprGen.cpp b/clang/lib/AST/Interp/ByteCodeExprGen.cpp index df7c4a72f21a7..1be131be66e3b 100644 --- a/clang/lib/AST/Interp/ByteCodeExprGen.cpp +++ b/clang/lib/AST/Interp/ByteCodeExprGen.cpp @@ -237,19 +237,31 @@ bool ByteCodeExprGen::VisitBinaryOperator(const BinaryOperator *BO) { if (!visit(LHS) || !visit(RHS)) return false; + // For languages such as C, cast the result of one + // of our comparision opcodes to T (which is usually int). + auto MaybeCastToBool = [this, T, BO](bool Result) { + if (!Result) + return false; + if (DiscardResult) + return this->emitPop(*T, BO); + if (T != PT_Bool) + return this->emitCast(PT_Bool, *T, BO); + return true; + }; + switch (BO->getOpcode()) { case BO_EQ: - return Discard(this->emitEQ(*LT, BO)); + return MaybeCastToBool(this->emitEQ(*LT, BO)); case BO_NE: - return Discard(this->emitNE(*LT, BO)); + return MaybeCastToBool(this->emitNE(*LT, BO)); case BO_LT: - return Discard(this->emitLT(*LT, BO)); + return MaybeCastToBool(this->emitLT(*LT, BO)); case BO_LE: - return Discard(this->emitLE(*LT, BO)); + return MaybeCastToBool(this->emitLE(*LT, BO)); case BO_GT: - return Discard(this->emitGT(*LT, BO)); + return MaybeCastToBool(this->emitGT(*LT, BO)); case BO_GE: - return Discard(this->emitGE(*LT, BO)); + return MaybeCastToBool(this->emitGE(*LT, BO)); case BO_Sub: if (BO->getType()->isFloatingType()) return Discard(this->emitSubf(getRoundingMode(BO), BO)); @@ -925,6 +937,15 @@ bool ByteCodeExprGen::visitConditional( if (!this->visit(Condition)) return false; + + // C special case: Convert to bool because our jump ops need that. + // TODO: We probably want this to be done in visitBool(). + if (std::optional CondT = classify(Condition->getType()); + CondT && CondT != PT_Bool) { + if (!this->emitCast(*CondT, PT_Bool, E)) + return false; + } + if (!this->jumpFalse(LabelFalse)) return false; diff --git a/clang/lib/AST/Interp/Disasm.cpp b/clang/lib/AST/Interp/Disasm.cpp index 7a5da90cd9002..35ed5d1286971 100644 --- a/clang/lib/AST/Interp/Disasm.cpp +++ b/clang/lib/AST/Interp/Disasm.cpp @@ -42,9 +42,9 @@ LLVM_DUMP_METHOD void Function::dump(llvm::raw_ostream &OS) const { auto PrintName = [&OS](const char *Name) { OS << Name; - for (long I = 0, N = strlen(Name); I < 30 - N; ++I) { - OS << ' '; - } + long N = 30 - strlen(Name); + if (N > 0) + OS.indent(N); }; for (CodePtr Start = getCodeBegin(), PC = Start; PC != getCodeEnd();) { diff --git a/clang/lib/AST/Interp/FunctionPointer.h b/clang/lib/AST/Interp/FunctionPointer.h index 20d4d7793185c..4a3f993d4882e 100644 --- a/clang/lib/AST/Interp/FunctionPointer.h +++ b/clang/lib/AST/Interp/FunctionPointer.h @@ -1,4 +1,10 @@ - +//===--- FunctionPointer.h - Types for the constexpr VM ----------*- C++ -*-===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// #ifndef LLVM_CLANG_AST_INTERP_FUNCTION_POINTER_H #define LLVM_CLANG_AST_INTERP_FUNCTION_POINTER_H diff --git a/clang/lib/AST/Interp/Interp.cpp b/clang/lib/AST/Interp/Interp.cpp index 4d331467f8f2e..3798146b32d11 100644 --- a/clang/lib/AST/Interp/Interp.cpp +++ b/clang/lib/AST/Interp/Interp.cpp @@ -341,6 +341,17 @@ bool CheckCallable(InterpState &S, CodePtr OpPC, const Function *F) { return true; } +bool CheckCallDepth(InterpState &S, CodePtr OpPC) { + if ((S.Current->getDepth() + 1) > S.getLangOpts().ConstexprCallDepth) { + S.FFDiag(S.Current->getSource(OpPC), + diag::note_constexpr_depth_limit_exceeded) + << S.getLangOpts().ConstexprCallDepth; + return false; + } + + return true; +} + bool CheckThis(InterpState &S, CodePtr OpPC, const Pointer &This) { if (!This.isZero()) return true; @@ -386,7 +397,7 @@ static bool CheckArrayInitialized(InterpState &S, CodePtr OpPC, size_t NumElems = CAT->getSize().getZExtValue(); QualType ElemType = CAT->getElementType(); - if (isa(ElemType.getTypePtr())) { + if (ElemType->isRecordType()) { const Record *R = BasePtr.getElemRecord(); for (size_t I = 0; I != NumElems; ++I) { Pointer ElemPtr = BasePtr.atIndex(I).narrow(); diff --git a/clang/lib/AST/Interp/Interp.h b/clang/lib/AST/Interp/Interp.h index 64bdd872221ac..fd5ce3c325961 100644 --- a/clang/lib/AST/Interp/Interp.h +++ b/clang/lib/AST/Interp/Interp.h @@ -88,6 +88,10 @@ bool CheckInit(InterpState &S, CodePtr OpPC, const Pointer &Ptr); /// Checks if a method can be called. bool CheckCallable(InterpState &S, CodePtr OpPC, const Function *F); +/// Checks if calling the currently active function would exceed +/// the allowed call depth. +bool CheckCallDepth(InterpState &S, CodePtr OpPC); + /// Checks the 'this' pointer. bool CheckThis(InterpState &S, CodePtr OpPC, const Pointer &This); @@ -158,7 +162,6 @@ enum class ArithOp { Add, Sub }; template ::T> bool Ret(InterpState &S, CodePtr &PC, APValue &Result) { - S.CallStackDepth--; const T &Ret = S.Stk.pop(); assert(S.Current->getFrameOffset() == S.Stk.size() && "Invalid frame"); @@ -181,8 +184,6 @@ bool Ret(InterpState &S, CodePtr &PC, APValue &Result) { template inline bool RetVoid(InterpState &S, CodePtr &PC, APValue &Result) { - S.CallStackDepth--; - assert(S.Current->getFrameOffset() == S.Stk.size() && "Invalid frame"); if (Builtin || !S.checkingPotentialConstantExpression()) S.Current->popArgs(); @@ -1598,6 +1599,9 @@ inline bool Call(InterpState &S, CodePtr OpPC, const Function *Func) { if (!CheckCallable(S, OpPC, Func)) return false; + if (!CheckCallDepth(S, OpPC)) + return false; + auto NewFrame = std::make_unique(S, Func, OpPC); InterpFrame *FrameBefore = S.Current; S.Current = NewFrame.get(); diff --git a/clang/lib/AST/Interp/InterpFrame.cpp b/clang/lib/AST/Interp/InterpFrame.cpp index 6acfbd3fa6143..14b55bea88206 100644 --- a/clang/lib/AST/Interp/InterpFrame.cpp +++ b/clang/lib/AST/Interp/InterpFrame.cpp @@ -23,8 +23,8 @@ using namespace clang::interp; InterpFrame::InterpFrame(InterpState &S, const Function *Func, InterpFrame *Caller, CodePtr RetPC) - : Caller(Caller), S(S), Func(Func), RetPC(RetPC), - ArgSize(Func ? Func->getArgSize() : 0), + : Caller(Caller), S(S), Depth(Caller ? Caller->Depth + 1 : 0), Func(Func), + RetPC(RetPC), ArgSize(Func ? Func->getArgSize() : 0), Args(static_cast(S.Stk.top())), FrameOffset(S.Stk.size()) { if (!Func) return; @@ -98,20 +98,19 @@ void print(llvm::raw_ostream &OS, const Pointer &P, ASTContext &Ctx, return; } - auto printDesc = [&OS, &Ctx](Descriptor *Desc) { - if (auto *D = Desc->asDecl()) { + auto printDesc = [&OS, &Ctx](const Descriptor *Desc) { + if (const auto *D = Desc->asDecl()) { // Subfields or named values. - if (auto *VD = dyn_cast(D)) { + if (const auto *VD = dyn_cast(D)) { OS << *VD; return; } // Base classes. - if (isa(D)) { + if (isa(D)) return; - } } // Temporary expression. - if (auto *E = Desc->asExpr()) { + if (const auto *E = Desc->asExpr()) { E->printPretty(OS, nullptr, Ctx.getPrintingPolicy()); return; } diff --git a/clang/lib/AST/Interp/InterpFrame.h b/clang/lib/AST/Interp/InterpFrame.h index c0f4825096be9..7988e74a61fe8 100644 --- a/clang/lib/AST/Interp/InterpFrame.h +++ b/clang/lib/AST/Interp/InterpFrame.h @@ -15,7 +15,6 @@ #include "Frame.h" #include "Program.h" -#include "State.h" #include #include @@ -120,6 +119,8 @@ class InterpFrame final : public Frame { const Expr *getExpr(CodePtr PC) const; SourceLocation getLocation(CodePtr PC) const; + unsigned getDepth() const { return Depth; } + private: /// Returns an original argument from the stack. template const T &stackRef(unsigned Offset) const { @@ -145,6 +146,8 @@ class InterpFrame final : public Frame { private: /// Reference to the interpreter state. InterpState &S; + /// Depth of this frame. + unsigned Depth; /// Reference to the function being executed. const Function *Func; /// Current object pointer for methods. diff --git a/clang/lib/AST/Interp/InterpState.cpp b/clang/lib/AST/Interp/InterpState.cpp index 6ae4ecd78c0fa..bd7daf38796ca 100644 --- a/clang/lib/AST/Interp/InterpState.cpp +++ b/clang/lib/AST/Interp/InterpState.cpp @@ -17,8 +17,7 @@ using namespace clang::interp; InterpState::InterpState(State &Parent, Program &P, InterpStack &Stk, Context &Ctx, SourceMapper *M) - : Parent(Parent), M(M), P(P), Stk(Stk), Ctx(Ctx), Current(nullptr), - CallStackDepth(Parent.getCallStackDepth() + 1) {} + : Parent(Parent), M(M), P(P), Stk(Stk), Ctx(Ctx), Current(nullptr) {} InterpState::~InterpState() { while (Current) { diff --git a/clang/lib/AST/Interp/InterpState.h b/clang/lib/AST/Interp/InterpState.h index 0330806373856..74c4667bb0196 100644 --- a/clang/lib/AST/Interp/InterpState.h +++ b/clang/lib/AST/Interp/InterpState.h @@ -15,6 +15,7 @@ #include "Context.h" #include "Function.h" +#include "InterpFrame.h" #include "InterpStack.h" #include "State.h" #include "clang/AST/APValue.h" @@ -41,7 +42,9 @@ class InterpState final : public State, public SourceMapper { // Stack frame accessors. Frame *getSplitFrame() { return Parent.getCurrentFrame(); } Frame *getCurrentFrame() override; - unsigned getCallStackDepth() override { return CallStackDepth; } + unsigned getCallStackDepth() override { + return Current ? (Current->getDepth() + 1) : 1; + } const Frame *getBottomFrame() const override { return Parent.getBottomFrame(); } @@ -103,8 +106,6 @@ class InterpState final : public State, public SourceMapper { Context &Ctx; /// The current frame. InterpFrame *Current = nullptr; - /// Call stack depth. - unsigned CallStackDepth; }; } // namespace interp diff --git a/clang/lib/AST/Interp/Record.cpp b/clang/lib/AST/Interp/Record.cpp index c8cbdb314f512..909416e6e1a1a 100644 --- a/clang/lib/AST/Interp/Record.cpp +++ b/clang/lib/AST/Interp/Record.cpp @@ -44,9 +44,7 @@ const Record::Base *Record::getBase(QualType T) const { return nullptr; const RecordDecl *RD = T->getAs()->getDecl(); - if (auto It = BaseMap.find(RD); It != BaseMap.end()) - return It->second; - return nullptr; + return BaseMap.lookup(RD); } const Record::Base *Record::getVirtualBase(const RecordDecl *FD) const { diff --git a/clang/lib/AST/Type.cpp b/clang/lib/AST/Type.cpp index 51e206d8c4636..63a5159ba7035 100644 --- a/clang/lib/AST/Type.cpp +++ b/clang/lib/AST/Type.cpp @@ -18,6 +18,7 @@ #include "clang/AST/Decl.h" #include "clang/AST/DeclBase.h" #include "clang/AST/DeclCXX.h" +#include "clang/AST/DeclFriend.h" #include "clang/AST/DeclObjC.h" #include "clang/AST/DeclTemplate.h" #include "clang/AST/DependenceFlags.h" @@ -2434,7 +2435,7 @@ bool Type::isVLSTBuiltinType() const { QualType Type::getSveEltType(const ASTContext &Ctx) const { assert(isVLSTBuiltinType() && "unsupported type!"); - const BuiltinType *BTy = getAs(); + const BuiltinType *BTy = castAs(); if (BTy->getKind() == BuiltinType::SveBool) // Represent predicates as i8 rather than i1 to avoid any layout issues. // The type is bitcasted to a scalable predicate type when casting between @@ -2462,7 +2463,7 @@ bool Type::isRVVVLSBuiltinType() const { QualType Type::getRVVEltType(const ASTContext &Ctx) const { assert(isRVVVLSBuiltinType() && "unsupported type!"); - const BuiltinType *BTy = getAs(); + const BuiltinType *BTy = castAs(); return Ctx.getBuiltinVectorTypeInfo(BTy).ElementType; } @@ -2640,11 +2641,21 @@ HasNonDeletedDefaultedEqualityComparison(const CXXRecordDecl *Decl) { if (Decl->isUnion()) return false; - if (llvm::none_of(Decl->methods(), [](const CXXMethodDecl *MemberFunction) { - return MemberFunction->isOverloadedOperator() && - MemberFunction->getOverloadedOperator() == - OverloadedOperatorKind::OO_EqualEqual && - MemberFunction->isDefaulted(); + auto IsDefaultedOperatorEqualEqual = [&](const FunctionDecl *Function) { + return Function->getOverloadedOperator() == + OverloadedOperatorKind::OO_EqualEqual && + Function->isDefaulted() && Function->getNumParams() > 0 && + (Function->getParamDecl(0)->getType()->isReferenceType() || + Decl->isTriviallyCopyable()); + }; + + if (llvm::none_of(Decl->methods(), IsDefaultedOperatorEqualEqual) && + llvm::none_of(Decl->friends(), [&](const FriendDecl *Friend) { + if (NamedDecl *ND = Friend->getFriendDecl()) { + return ND->isFunctionOrFunctionTemplate() && + IsDefaultedOperatorEqualEqual(ND->getAsFunction()); + } + return false; })) return false; diff --git a/clang/lib/AST/TypePrinter.cpp b/clang/lib/AST/TypePrinter.cpp index 4444dedcfde17..00f5fe0da8cdf 100644 --- a/clang/lib/AST/TypePrinter.cpp +++ b/clang/lib/AST/TypePrinter.cpp @@ -1757,6 +1757,11 @@ void TypePrinter::printAttributedAfter(const AttributedType *T, return; } + if (T->getAttrKind() == attr::ArmStreaming) { + OS << "__arm_streaming"; + return; + } + OS << " __attribute__(("; switch (T->getAttrKind()) { #define TYPE_ATTR(NAME) @@ -1797,6 +1802,7 @@ void TypePrinter::printAttributedAfter(const AttributedType *T, case attr::CmseNSCall: case attr::AnnotateType: case attr::WebAssemblyFuncref: + case attr::ArmStreaming: llvm_unreachable("This attribute should have been handled already"); case attr::NSReturnsRetained: diff --git a/clang/lib/Analysis/CFG.cpp b/clang/lib/Analysis/CFG.cpp index 4c8ceb792d2a7..246bace4debcf 100644 --- a/clang/lib/Analysis/CFG.cpp +++ b/clang/lib/Analysis/CFG.cpp @@ -1992,8 +1992,7 @@ LocalScope* CFGBuilder::createOrReuseLocalScope(LocalScope* Scope) { if (Scope) return Scope; llvm::BumpPtrAllocator &alloc = cfg->getAllocator(); - return new (alloc.Allocate()) - LocalScope(BumpVectorContext(alloc), ScopePos); + return new (alloc) LocalScope(BumpVectorContext(alloc), ScopePos); } /// addLocalScopeForStmt - Add LocalScope to local scopes tree for statement @@ -5214,8 +5213,7 @@ CFGBlock *CFG::createBlock() { bool first_block = begin() == end(); // Create the block. - CFGBlock *Mem = getAllocator().Allocate(); - new (Mem) CFGBlock(NumBlockIDs++, BlkBVC, this); + CFGBlock *Mem = new (getAllocator()) CFGBlock(NumBlockIDs++, BlkBVC, this); Blocks.push_back(Mem, BlkBVC); // If this is the first block, set it as the Entry and Exit. diff --git a/clang/lib/Analysis/FlowSensitive/ControlFlowContext.cpp b/clang/lib/Analysis/FlowSensitive/ControlFlowContext.cpp index c62bff33524cf..c80525dc4f34f 100644 --- a/clang/lib/Analysis/FlowSensitive/ControlFlowContext.cpp +++ b/clang/lib/Analysis/FlowSensitive/ControlFlowContext.cpp @@ -68,13 +68,13 @@ static llvm::BitVector findReachableBlocks(const CFG &Cfg) { } llvm::Expected -ControlFlowContext::build(const FunctionDecl &Func, ASTContext &C) { +ControlFlowContext::build(const FunctionDecl &Func) { if (!Func.hasBody()) return llvm::createStringError( std::make_error_code(std::errc::invalid_argument), "Cannot analyze function without a body"); - return build(Func, *Func.getBody(), C); + return build(Func, *Func.getBody(), Func.getASTContext()); } llvm::Expected diff --git a/clang/lib/Analysis/FlowSensitive/DataflowAnalysisContext.cpp b/clang/lib/Analysis/FlowSensitive/DataflowAnalysisContext.cpp index 32612397ec024..27ec15adc5350 100644 --- a/clang/lib/Analysis/FlowSensitive/DataflowAnalysisContext.cpp +++ b/clang/lib/Analysis/FlowSensitive/DataflowAnalysisContext.cpp @@ -211,7 +211,7 @@ DataflowAnalysisContext::getControlFlowContext(const FunctionDecl *F) { return &It->second; if (F->hasBody()) { - auto CFCtx = ControlFlowContext::build(*F, F->getASTContext()); + auto CFCtx = ControlFlowContext::build(*F); // FIXME: Handle errors. assert(CFCtx); auto Result = FunctionContexts.insert({F, std::move(*CFCtx)}); diff --git a/clang/lib/Basic/Cuda.cpp b/clang/lib/Basic/Cuda.cpp index 7299b9f485ec2..356bfd6bd784f 100644 --- a/clang/lib/Basic/Cuda.cpp +++ b/clang/lib/Basic/Cuda.cpp @@ -222,7 +222,11 @@ CudaVersion MaxVersionForCudaArch(CudaArch A) { case CudaArch::SM_21: return CudaVersion::CUDA_80; case CudaArch::SM_30: - return CudaVersion::CUDA_110; + case CudaArch::SM_32: + return CudaVersion::CUDA_102; + case CudaArch::SM_35: + case CudaArch::SM_37: + return CudaVersion::CUDA_118; default: return CudaVersion::NEW; } diff --git a/clang/lib/Basic/Module.cpp b/clang/lib/Basic/Module.cpp index 3df376a32e53e..057fc77d0e993 100644 --- a/clang/lib/Basic/Module.cpp +++ b/clang/lib/Basic/Module.cpp @@ -483,15 +483,15 @@ void Module::print(raw_ostream &OS, unsigned Indent, bool Dump) const { OS << "\n"; } - if (Header H = getUmbrellaHeaderAsWritten()) { + if (std::optional
H = getUmbrellaHeaderAsWritten()) { OS.indent(Indent + 2); OS << "umbrella header \""; - OS.write_escaped(H.NameAsWritten); + OS.write_escaped(H->NameAsWritten); OS << "\"\n"; - } else if (DirectoryName D = getUmbrellaDirAsWritten()) { + } else if (std::optional D = getUmbrellaDirAsWritten()) { OS.indent(Indent + 2); OS << "umbrella \""; - OS.write_escaped(D.NameAsWritten); + OS.write_escaped(D->NameAsWritten); OS << "\"\n"; } @@ -523,8 +523,8 @@ void Module::print(raw_ostream &OS, unsigned Indent, bool Dump) const { OS.indent(Indent + 2); OS << K.Prefix << "header \""; OS.write_escaped(H.NameAsWritten); - OS << "\" { size " << H.Entry->getSize() - << " mtime " << H.Entry->getModificationTime() << " }\n"; + OS << "\" { size " << H.Entry.getSize() + << " mtime " << H.Entry.getModificationTime() << " }\n"; } } for (auto *Unresolved : {&UnresolvedHeaders, &MissingHeaders}) { diff --git a/clang/lib/CodeGen/CGAtomic.cpp b/clang/lib/CodeGen/CGAtomic.cpp index 8ef95bb808468..e2d23a7252613 100644 --- a/clang/lib/CodeGen/CGAtomic.cpp +++ b/clang/lib/CodeGen/CGAtomic.cpp @@ -623,6 +623,7 @@ static void EmitAtomicOp(CodeGenFunction &CGF, AtomicExpr *E, Address Dest, : llvm::Instruction::Sub; [[fallthrough]]; case AtomicExpr::AO__c11_atomic_fetch_sub: + case AtomicExpr::AO__hip_atomic_fetch_sub: case AtomicExpr::AO__opencl_atomic_fetch_sub: case AtomicExpr::AO__atomic_fetch_sub: Op = E->getValueType()->isFloatingType() ? llvm::AtomicRMWInst::FSub @@ -636,8 +637,11 @@ static void EmitAtomicOp(CodeGenFunction &CGF, AtomicExpr *E, Address Dest, case AtomicExpr::AO__hip_atomic_fetch_min: case AtomicExpr::AO__opencl_atomic_fetch_min: case AtomicExpr::AO__atomic_fetch_min: - Op = E->getValueType()->isSignedIntegerType() ? llvm::AtomicRMWInst::Min - : llvm::AtomicRMWInst::UMin; + Op = E->getValueType()->isFloatingType() + ? llvm::AtomicRMWInst::FMin + : (E->getValueType()->isSignedIntegerType() + ? llvm::AtomicRMWInst::Min + : llvm::AtomicRMWInst::UMin); break; case AtomicExpr::AO__atomic_max_fetch: @@ -647,8 +651,11 @@ static void EmitAtomicOp(CodeGenFunction &CGF, AtomicExpr *E, Address Dest, case AtomicExpr::AO__hip_atomic_fetch_max: case AtomicExpr::AO__opencl_atomic_fetch_max: case AtomicExpr::AO__atomic_fetch_max: - Op = E->getValueType()->isSignedIntegerType() ? llvm::AtomicRMWInst::Max - : llvm::AtomicRMWInst::UMax; + Op = E->getValueType()->isFloatingType() + ? llvm::AtomicRMWInst::FMax + : (E->getValueType()->isSignedIntegerType() + ? llvm::AtomicRMWInst::Max + : llvm::AtomicRMWInst::UMax); break; case AtomicExpr::AO__atomic_and_fetch: @@ -897,6 +904,7 @@ RValue CodeGenFunction::EmitAtomicExpr(AtomicExpr *E) { case AtomicExpr::AO__c11_atomic_fetch_add: case AtomicExpr::AO__c11_atomic_fetch_sub: case AtomicExpr::AO__hip_atomic_fetch_add: + case AtomicExpr::AO__hip_atomic_fetch_sub: case AtomicExpr::AO__opencl_atomic_fetch_add: case AtomicExpr::AO__opencl_atomic_fetch_sub: if (MemTy->isPointerType()) { @@ -916,9 +924,19 @@ RValue CodeGenFunction::EmitAtomicExpr(AtomicExpr *E) { } [[fallthrough]]; case AtomicExpr::AO__atomic_fetch_add: + case AtomicExpr::AO__atomic_fetch_max: + case AtomicExpr::AO__atomic_fetch_min: case AtomicExpr::AO__atomic_fetch_sub: case AtomicExpr::AO__atomic_add_fetch: + case AtomicExpr::AO__atomic_max_fetch: + case AtomicExpr::AO__atomic_min_fetch: case AtomicExpr::AO__atomic_sub_fetch: + case AtomicExpr::AO__c11_atomic_fetch_max: + case AtomicExpr::AO__c11_atomic_fetch_min: + case AtomicExpr::AO__opencl_atomic_fetch_max: + case AtomicExpr::AO__opencl_atomic_fetch_min: + case AtomicExpr::AO__hip_atomic_fetch_max: + case AtomicExpr::AO__hip_atomic_fetch_min: ShouldCastToIntPtrTy = !MemTy->isFloatingType(); [[fallthrough]]; @@ -934,13 +952,9 @@ RValue CodeGenFunction::EmitAtomicExpr(AtomicExpr *E) { case AtomicExpr::AO__c11_atomic_fetch_or: case AtomicExpr::AO__c11_atomic_fetch_xor: case AtomicExpr::AO__c11_atomic_fetch_nand: - case AtomicExpr::AO__c11_atomic_fetch_max: - case AtomicExpr::AO__c11_atomic_fetch_min: case AtomicExpr::AO__opencl_atomic_fetch_and: case AtomicExpr::AO__opencl_atomic_fetch_or: case AtomicExpr::AO__opencl_atomic_fetch_xor: - case AtomicExpr::AO__opencl_atomic_fetch_min: - case AtomicExpr::AO__opencl_atomic_fetch_max: case AtomicExpr::AO__atomic_fetch_and: case AtomicExpr::AO__hip_atomic_fetch_and: case AtomicExpr::AO__atomic_fetch_or: @@ -952,12 +966,6 @@ RValue CodeGenFunction::EmitAtomicExpr(AtomicExpr *E) { case AtomicExpr::AO__atomic_or_fetch: case AtomicExpr::AO__atomic_xor_fetch: case AtomicExpr::AO__atomic_nand_fetch: - case AtomicExpr::AO__atomic_max_fetch: - case AtomicExpr::AO__atomic_min_fetch: - case AtomicExpr::AO__atomic_fetch_max: - case AtomicExpr::AO__hip_atomic_fetch_max: - case AtomicExpr::AO__atomic_fetch_min: - case AtomicExpr::AO__hip_atomic_fetch_min: Val1 = EmitValToTemp(*this, E->getVal1()); break; } @@ -1013,6 +1021,7 @@ RValue CodeGenFunction::EmitAtomicExpr(AtomicExpr *E) { case AtomicExpr::AO__c11_atomic_fetch_sub: case AtomicExpr::AO__opencl_atomic_fetch_sub: case AtomicExpr::AO__atomic_fetch_sub: + case AtomicExpr::AO__hip_atomic_fetch_sub: case AtomicExpr::AO__c11_atomic_fetch_xor: case AtomicExpr::AO__opencl_atomic_fetch_xor: case AtomicExpr::AO__opencl_atomic_fetch_min: @@ -1218,6 +1227,7 @@ RValue CodeGenFunction::EmitAtomicExpr(AtomicExpr *E) { [[fallthrough]]; case AtomicExpr::AO__c11_atomic_fetch_sub: case AtomicExpr::AO__opencl_atomic_fetch_sub: + case AtomicExpr::AO__hip_atomic_fetch_sub: case AtomicExpr::AO__atomic_fetch_sub: LibCallName = "__atomic_fetch_sub"; AddDirectArgument(*this, Args, UseOptimizedLibcall, Val1.getPointer(), diff --git a/clang/lib/CodeGen/CGBuiltin.cpp b/clang/lib/CodeGen/CGBuiltin.cpp index 3a61fdd65592a..c09e5b5319ebe 100644 --- a/clang/lib/CodeGen/CGBuiltin.cpp +++ b/clang/lib/CodeGen/CGBuiltin.cpp @@ -1741,7 +1741,7 @@ Value *CodeGenFunction::EmitCheckedArgForBuiltin(const Expr *E, && "Unsupported builtin check kind"); Value *ArgValue = EmitScalarExpr(E); - if (!SanOpts.has(SanitizerKind::Builtin) || !getTarget().isCLZForZeroUndef()) + if (!SanOpts.has(SanitizerKind::Builtin)) return ArgValue; SanitizerScope SanScope(this); @@ -18422,8 +18422,11 @@ Value *CodeGenFunction::EmitNVPTXBuiltinExpr(unsigned BuiltinID, } case NVPTX::BI__nvvm_ldg_c: + case NVPTX::BI__nvvm_ldg_sc: case NVPTX::BI__nvvm_ldg_c2: + case NVPTX::BI__nvvm_ldg_sc2: case NVPTX::BI__nvvm_ldg_c4: + case NVPTX::BI__nvvm_ldg_sc4: case NVPTX::BI__nvvm_ldg_s: case NVPTX::BI__nvvm_ldg_s2: case NVPTX::BI__nvvm_ldg_s4: @@ -18431,6 +18434,7 @@ Value *CodeGenFunction::EmitNVPTXBuiltinExpr(unsigned BuiltinID, case NVPTX::BI__nvvm_ldg_i2: case NVPTX::BI__nvvm_ldg_i4: case NVPTX::BI__nvvm_ldg_l: + case NVPTX::BI__nvvm_ldg_l2: case NVPTX::BI__nvvm_ldg_ll: case NVPTX::BI__nvvm_ldg_ll2: case NVPTX::BI__nvvm_ldg_uc: @@ -18443,6 +18447,7 @@ Value *CodeGenFunction::EmitNVPTXBuiltinExpr(unsigned BuiltinID, case NVPTX::BI__nvvm_ldg_ui2: case NVPTX::BI__nvvm_ldg_ui4: case NVPTX::BI__nvvm_ldg_ul: + case NVPTX::BI__nvvm_ldg_ul2: case NVPTX::BI__nvvm_ldg_ull: case NVPTX::BI__nvvm_ldg_ull2: // PTX Interoperability section 2.2: "For a vector with an even number of @@ -18457,8 +18462,11 @@ Value *CodeGenFunction::EmitNVPTXBuiltinExpr(unsigned BuiltinID, return MakeLdgLdu(Intrinsic::nvvm_ldg_global_f, *this, E); case NVPTX::BI__nvvm_ldu_c: + case NVPTX::BI__nvvm_ldu_sc: case NVPTX::BI__nvvm_ldu_c2: + case NVPTX::BI__nvvm_ldu_sc2: case NVPTX::BI__nvvm_ldu_c4: + case NVPTX::BI__nvvm_ldu_sc4: case NVPTX::BI__nvvm_ldu_s: case NVPTX::BI__nvvm_ldu_s2: case NVPTX::BI__nvvm_ldu_s4: @@ -18466,6 +18474,7 @@ Value *CodeGenFunction::EmitNVPTXBuiltinExpr(unsigned BuiltinID, case NVPTX::BI__nvvm_ldu_i2: case NVPTX::BI__nvvm_ldu_i4: case NVPTX::BI__nvvm_ldu_l: + case NVPTX::BI__nvvm_ldu_l2: case NVPTX::BI__nvvm_ldu_ll: case NVPTX::BI__nvvm_ldu_ll2: case NVPTX::BI__nvvm_ldu_uc: @@ -18478,6 +18487,7 @@ Value *CodeGenFunction::EmitNVPTXBuiltinExpr(unsigned BuiltinID, case NVPTX::BI__nvvm_ldu_ui2: case NVPTX::BI__nvvm_ldu_ui4: case NVPTX::BI__nvvm_ldu_ul: + case NVPTX::BI__nvvm_ldu_ul2: case NVPTX::BI__nvvm_ldu_ull: case NVPTX::BI__nvvm_ldu_ull2: return MakeLdgLdu(Intrinsic::nvvm_ldu_global_i, *this, E); diff --git a/clang/lib/CodeGen/CGCall.cpp b/clang/lib/CodeGen/CGCall.cpp index ec28c1db207a6..b6b04fca66820 100644 --- a/clang/lib/CodeGen/CGCall.cpp +++ b/clang/lib/CodeGen/CGCall.cpp @@ -1751,7 +1751,7 @@ CodeGenTypes::GetFunctionType(const CGFunctionInfo &FI) { llvm::Type *CodeGenTypes::GetFunctionTypeForVTable(GlobalDecl GD) { const CXXMethodDecl *MD = cast(GD.getDecl()); - const FunctionProtoType *FPT = MD->getType()->getAs(); + const FunctionProtoType *FPT = MD->getType()->castAs(); if (!isFuncTypeConvertible(FPT)) return llvm::StructType::get(getLLVMContext()); @@ -5716,7 +5716,6 @@ RValue CodeGenFunction::EmitCall(const CGFunctionInfo &CallInfo, assert(unpaddedIndex == 0); Builder.CreateStore(elt, eltAddr); } - // FALLTHROUGH [[fallthrough]]; } diff --git a/clang/lib/CodeGen/CGDebugInfo.cpp b/clang/lib/CodeGen/CGDebugInfo.cpp index 2857ea20ba1d8..edef27bdf377c 100644 --- a/clang/lib/CodeGen/CGDebugInfo.cpp +++ b/clang/lib/CodeGen/CGDebugInfo.cpp @@ -3307,7 +3307,7 @@ llvm::DIType *CGDebugInfo::CreateType(const MemberPointerType *Ty, Flags); const FunctionProtoType *FPT = - Ty->getPointeeType()->getAs(); + Ty->getPointeeType()->castAs(); return DBuilder.createMemberPointerType( getOrCreateInstanceMethodType( CXXMethodDecl::getThisType(FPT, Ty->getMostRecentCXXRecordDecl()), diff --git a/clang/lib/CodeGen/CGObjC.cpp b/clang/lib/CodeGen/CGObjC.cpp index 7df2088a81d79..c8f0070192dd6 100644 --- a/clang/lib/CodeGen/CGObjC.cpp +++ b/clang/lib/CodeGen/CGObjC.cpp @@ -140,7 +140,7 @@ llvm::Value *CodeGenFunction::EmitObjCCollectionLiteral(const Expr *E, LValue LV = MakeNaturalAlignAddrLValue(Constant, IdTy); llvm::Value *Ptr = EmitLoadOfScalar(LV, E->getBeginLoc()); cast(Ptr)->setMetadata( - CGM.getModule().getMDKindID("invariant.load"), + llvm::LLVMContext::MD_invariant_load, llvm::MDNode::get(getLLVMContext(), std::nullopt)); return Builder.CreateBitCast(Ptr, ConvertType(E->getType())); } diff --git a/clang/lib/CodeGen/CGObjCMac.cpp b/clang/lib/CodeGen/CGObjCMac.cpp index 5f4cdc6d91f1d..d52e560234bdf 100644 --- a/clang/lib/CodeGen/CGObjCMac.cpp +++ b/clang/lib/CodeGen/CGObjCMac.cpp @@ -7229,7 +7229,7 @@ CGObjCNonFragileABIMac::EmitIvarOffset(CodeGen::CodeGenFunction &CGF, CGF.getSizeAlign(), "ivar"); if (IsIvarOffsetKnownIdempotent(CGF, Ivar)) cast(IvarOffsetValue) - ->setMetadata(CGM.getModule().getMDKindID("invariant.load"), + ->setMetadata(llvm::LLVMContext::MD_invariant_load, llvm::MDNode::get(VMContext, std::nullopt)); } @@ -7629,7 +7629,7 @@ llvm::Value *CGObjCNonFragileABIMac::EmitSelector(CodeGenFunction &CGF, Address Addr = EmitSelectorAddr(Sel); llvm::LoadInst* LI = CGF.Builder.CreateLoad(Addr); - LI->setMetadata(CGM.getModule().getMDKindID("invariant.load"), + LI->setMetadata(llvm::LLVMContext::MD_invariant_load, llvm::MDNode::get(VMContext, std::nullopt)); return LI; } diff --git a/clang/lib/CodeGen/CGOpenMPRuntime.cpp b/clang/lib/CodeGen/CGOpenMPRuntime.cpp index 1f1db83378233..2feab9e9a3322 100644 --- a/clang/lib/CodeGen/CGOpenMPRuntime.cpp +++ b/clang/lib/CodeGen/CGOpenMPRuntime.cpp @@ -2143,7 +2143,11 @@ Address CGOpenMPRuntime::emitThreadIDAddress(CodeGenFunction &CGF, llvm::Value *CGOpenMPRuntime::getCriticalRegionLock(StringRef CriticalName) { std::string Prefix = Twine("gomp_critical_user_", CriticalName).str(); std::string Name = getName({Prefix, "var"}); - return OMPBuilder.getOrCreateInternalVariable(KmpCriticalNameTy, Name); + llvm::GlobalVariable *G = OMPBuilder.getOrCreateInternalVariable(KmpCriticalNameTy, Name); + llvm::Align PtrAlign = OMPBuilder.M.getDataLayout().getPointerABIAlignment(G->getAddressSpace()); + if (PtrAlign > llvm::Align(G->getAlignment())) + G->setAlignment(PtrAlign); + return G; } namespace { @@ -6041,7 +6045,7 @@ void CGOpenMPRuntime::emitUsesAllocatorsInit(CodeGenFunction &CGF, CGM.getModule(), OMPRTL___kmpc_init_allocator), {ThreadId, MemSpaceHandle, NumTraits, Traits}); // Store to allocator. - CGF.EmitVarDecl(*cast( + CGF.EmitAutoVarAlloca(*cast( cast(Allocator->IgnoreParenImpCasts())->getDecl())); LValue AllocatorLVal = CGF.EmitLValue(Allocator->IgnoreParenImpCasts()); AllocatorVal = diff --git a/clang/lib/CodeGen/ItaniumCXXABI.cpp b/clang/lib/CodeGen/ItaniumCXXABI.cpp index 5dc21dd31e0ae..73137ea27222f 100644 --- a/clang/lib/CodeGen/ItaniumCXXABI.cpp +++ b/clang/lib/CodeGen/ItaniumCXXABI.cpp @@ -1587,12 +1587,14 @@ ItaniumCXXABI::buildStructorSignature(GlobalDecl GD, // All parameters are already in place except VTT, which goes after 'this'. // These are Clang types, so we don't need to worry about sret yet. - // Check if we need to add a VTT parameter (which has type void **). + // Check if we need to add a VTT parameter (which has type global void **). if ((isa(GD.getDecl()) ? GD.getCtorType() == Ctor_Base : GD.getDtorType() == Dtor_Base) && cast(GD.getDecl())->getParent()->getNumVBases() != 0) { + LangAS AS = CGM.GetGlobalVarAddressSpace(nullptr); + QualType Q = Context.getAddrSpaceQualType(Context.VoidPtrTy, AS); ArgTys.insert(ArgTys.begin() + 1, - Context.getPointerType(Context.VoidPtrTy)); + Context.getPointerType(CanQualType::CreateUnsafe(Q))); return AddedStructorArgCounts::prefix(1); } return AddedStructorArgCounts{}; @@ -1625,7 +1627,9 @@ void ItaniumCXXABI::addImplicitStructorParams(CodeGenFunction &CGF, ASTContext &Context = getContext(); // FIXME: avoid the fake decl - QualType T = Context.getPointerType(Context.VoidPtrTy); + LangAS AS = CGM.GetGlobalVarAddressSpace(nullptr); + QualType Q = Context.getAddrSpaceQualType(Context.VoidPtrTy, AS); + QualType T = Context.getPointerType(Q); auto *VTTDecl = ImplicitParamDecl::Create( Context, /*DC=*/nullptr, MD->getLocation(), &Context.Idents.get("vtt"), T, ImplicitParamDecl::CXXVTT); @@ -1667,10 +1671,14 @@ CGCXXABI::AddedStructorArgs ItaniumCXXABI::getImplicitConstructorArgs( if (!NeedsVTTParameter(GlobalDecl(D, Type))) return AddedStructorArgs{}; - // Insert the implicit 'vtt' argument as the second argument. + // Insert the implicit 'vtt' argument as the second argument. Make sure to + // correctly reflect its address space, which can differ from generic on + // some targets. llvm::Value *VTT = CGF.GetVTTParameter(GlobalDecl(D, Type), ForVirtualBase, Delegating); - QualType VTTTy = getContext().getPointerType(getContext().VoidPtrTy); + LangAS AS = CGM.GetGlobalVarAddressSpace(nullptr); + QualType Q = getContext().getAddrSpaceQualType(getContext().VoidPtrTy, AS); + QualType VTTTy = getContext().getPointerType(Q); return AddedStructorArgs::prefix({{VTT, VTTTy}}); } diff --git a/clang/lib/CodeGen/TargetInfo.cpp b/clang/lib/CodeGen/TargetInfo.cpp index 3d56d0e0b0128..fb0a7158d1a39 100644 --- a/clang/lib/CodeGen/TargetInfo.cpp +++ b/clang/lib/CodeGen/TargetInfo.cpp @@ -2543,6 +2543,7 @@ class X86_64TargetCodeGenInfo : public TargetCodeGenInfo { const FunctionDecl *Callee, const CallArgList &Args) const override; }; +} // namespace static void initFeatureMaps(const ASTContext &Ctx, llvm::StringMap &CallerMap, @@ -2641,7 +2642,7 @@ void X86_64TargetCodeGenInfo::checkFunctionCallABI( } } -static std::string qualifyWindowsLibrary(llvm::StringRef Lib) { +std::string TargetCodeGenInfo::qualifyWindowsLibrary(StringRef Lib) { // If the argument does not end in .lib, automatically add the suffix. // If the argument contains a space, enclose it in quotes. // This matches the behavior of MSVC. @@ -2654,6 +2655,7 @@ static std::string qualifyWindowsLibrary(llvm::StringRef Lib) { return ArgStr; } +namespace { class WinX86_32TargetCodeGenInfo : public X86_32TargetCodeGenInfo { public: WinX86_32TargetCodeGenInfo(CodeGen::CodeGenTypes &CGT, @@ -2677,11 +2679,11 @@ class WinX86_32TargetCodeGenInfo : public X86_32TargetCodeGenInfo { Opt = "/FAILIFMISMATCH:\"" + Name.str() + "=" + Value.str() + "\""; } }; +} // namespace -static void addStackProbeTargetAttributes(const Decl *D, llvm::GlobalValue *GV, - CodeGen::CodeGenModule &CGM) { +void TargetCodeGenInfo::addStackProbeTargetAttributes( + const Decl *D, llvm::GlobalValue *GV, CodeGen::CodeGenModule &CGM) const { if (llvm::Function *Fn = dyn_cast_or_null(GV)) { - if (CGM.getCodeGenOpts().StackProbeSize != 4096) Fn->addFnAttr("stack-probe-size", llvm::utostr(CGM.getCodeGenOpts().StackProbeSize)); @@ -2698,6 +2700,7 @@ void WinX86_32TargetCodeGenInfo::setTargetAttributes( addStackProbeTargetAttributes(D, GV, CGM); } +namespace { class WinX86_64TargetCodeGenInfo : public TargetCodeGenInfo { public: WinX86_64TargetCodeGenInfo(CodeGen::CodeGenTypes &CGT, @@ -2736,6 +2739,7 @@ class WinX86_64TargetCodeGenInfo : public TargetCodeGenInfo { Opt = "/FAILIFMISMATCH:\"" + Name.str() + "=" + Value.str() + "\""; } }; +} // namespace void WinX86_64TargetCodeGenInfo::setTargetAttributes( const Decl *D, llvm::GlobalValue *GV, CodeGen::CodeGenModule &CGM) const { @@ -2753,7 +2757,6 @@ void WinX86_64TargetCodeGenInfo::setTargetAttributes( addStackProbeTargetAttributes(D, GV, CGM); } -} void X86_64ABIInfo::postMerge(unsigned AggregateSize, Class &Lo, Class &Hi) const { diff --git a/clang/lib/CodeGen/TargetInfo.h b/clang/lib/CodeGen/TargetInfo.h index 7637e55ccf410..933a352595120 100644 --- a/clang/lib/CodeGen/TargetInfo.h +++ b/clang/lib/CodeGen/TargetInfo.h @@ -398,6 +398,12 @@ class TargetCodeGenInfo { virtual llvm::Type *getOpenCLType(CodeGenModule &CGM, const Type *T) const { return nullptr; } + +protected: + static std::string qualifyWindowsLibrary(StringRef Lib); + + void addStackProbeTargetAttributes(const Decl *D, llvm::GlobalValue *GV, + CodeGen::CodeGenModule &CGM) const; }; } // namespace CodeGen diff --git a/clang/lib/Driver/Driver.cpp b/clang/lib/Driver/Driver.cpp index 9f26ed676224b..fee14ba6faabe 100644 --- a/clang/lib/Driver/Driver.cpp +++ b/clang/lib/Driver/Driver.cpp @@ -559,16 +559,14 @@ static llvm::Triple computeTargetTriple(const Driver &D, // Handle pseudo-target flags '-mlittle-endian'/'-EL' and // '-mbig-endian'/'-EB'. - if (Arg *A = Args.getLastArg(options::OPT_mlittle_endian, - options::OPT_mbig_endian)) { - if (A->getOption().matches(options::OPT_mlittle_endian)) { - llvm::Triple LE = Target.getLittleEndianArchVariant(); - if (LE.getArch() != llvm::Triple::UnknownArch) - Target = std::move(LE); - } else { - llvm::Triple BE = Target.getBigEndianArchVariant(); - if (BE.getArch() != llvm::Triple::UnknownArch) - Target = std::move(BE); + if (Arg *A = Args.getLastArgNoClaim(options::OPT_mlittle_endian, + options::OPT_mbig_endian)) { + llvm::Triple T = A->getOption().matches(options::OPT_mlittle_endian) + ? Target.getLittleEndianArchVariant() + : Target.getBigEndianArchVariant(); + if (T.getArch() != llvm::Triple::UnknownArch) { + Target = std::move(T); + Args.claimAllArgs(options::OPT_mlittle_endian, options::OPT_mbig_endian); } } @@ -4885,9 +4883,15 @@ void Driver::BuildJobs(Compilation &C) const { // In clang-cl, don't mention unknown arguments here since they have // already been warned about. - if (!IsCLMode() || !A->getOption().matches(options::OPT_UNKNOWN)) - Diag(clang::diag::warn_drv_unused_argument) - << A->getAsString(C.getArgs()); + if (!IsCLMode() || !A->getOption().matches(options::OPT_UNKNOWN)) { + if (A->getOption().hasFlag(options::TargetSpecific)) { + Diag(diag::err_drv_unsupported_opt_for_target) + << A->getSpelling() << getTargetTriple(); + } else { + Diag(clang::diag::warn_drv_unused_argument) + << A->getAsString(C.getArgs()); + } + } } } } diff --git a/clang/lib/Driver/Job.cpp b/clang/lib/Driver/Job.cpp index f85f55cd1ff54..573e91856d776 100644 --- a/clang/lib/Driver/Job.cpp +++ b/clang/lib/Driver/Job.cpp @@ -449,30 +449,6 @@ void CC1Command::setEnvironment(llvm::ArrayRef NewEnvironment) { "The CC1Command doesn't support changing the environment vars!"); } -ForceSuccessCommand::ForceSuccessCommand( - const Action &Source_, const Tool &Creator_, - ResponseFileSupport ResponseSupport, const char *Executable_, - const llvm::opt::ArgStringList &Arguments_, ArrayRef Inputs, - ArrayRef Outputs) - : Command(Source_, Creator_, ResponseSupport, Executable_, Arguments_, - Inputs, Outputs) {} - -void ForceSuccessCommand::Print(raw_ostream &OS, const char *Terminator, - bool Quote, CrashReportInfo *CrashInfo) const { - Command::Print(OS, "", Quote, CrashInfo); - OS << " || (exit 0)" << Terminator; -} - -int ForceSuccessCommand::Execute(ArrayRef> Redirects, - std::string *ErrMsg, - bool *ExecutionFailed) const { - int Status = Command::Execute(Redirects, ErrMsg, ExecutionFailed); - (void)Status; - if (ExecutionFailed) - *ExecutionFailed = false; - return 0; -} - void JobList::Print(raw_ostream &OS, const char *Terminator, bool Quote, CrashReportInfo *CrashInfo) const { for (const auto &Job : *this) diff --git a/clang/lib/Driver/ToolChain.cpp b/clang/lib/Driver/ToolChain.cpp index 8bfa5baf92ff7..ccaebb384d4dc 100644 --- a/clang/lib/Driver/ToolChain.cpp +++ b/clang/lib/Driver/ToolChain.cpp @@ -662,7 +662,8 @@ Tool *ToolChain::SelectTool(const JobAction &JA) const { if (D.IsFlangMode() && getDriver().ShouldUseFlangCompiler(JA)) return getFlang(); if (getDriver().ShouldUseClangCompiler(JA)) return getClang(); Action::ActionClass AC = JA.getKind(); - if (AC == Action::AssembleJobClass && useIntegratedAs()) + if (AC == Action::AssembleJobClass && useIntegratedAs() && + !getTriple().isOSAIX()) return getClangAs(); return getTool(AC); } diff --git a/clang/lib/Driver/ToolChains/AIX.cpp b/clang/lib/Driver/ToolChains/AIX.cpp index 46ad8231764db..ad7f3edeb9384 100644 --- a/clang/lib/Driver/ToolChains/AIX.cpp +++ b/clang/lib/Driver/ToolChains/AIX.cpp @@ -409,6 +409,18 @@ void AIX::AddCXXStdlibLibArgs(const llvm::opt::ArgList &Args, llvm_unreachable("Unexpected C++ library type; only libc++ is supported."); } +void AIX::addClangTargetOptions( + const llvm::opt::ArgList &Args, llvm::opt::ArgStringList &CC1Args, + Action::OffloadKind DeviceOffloadingKind) const { + Args.AddLastArg(CC1Args, options::OPT_mignore_xcoff_visibility); + Args.AddLastArg(CC1Args, options::OPT_mdefault_visibility_export_mapping_EQ); + Args.addOptInFlag(CC1Args, options::OPT_mxcoff_roptr, options::OPT_mno_xcoff_roptr); + + if (Args.hasFlag(options::OPT_fxl_pragma_pack, + options::OPT_fno_xl_pragma_pack, true)) + CC1Args.push_back("-fxl-pragma-pack"); +} + void AIX::addProfileRTLibs(const llvm::opt::ArgList &Args, llvm::opt::ArgStringList &CmdArgs) const { // Add linker option -u__llvm_profile_runtime to cause runtime diff --git a/clang/lib/Driver/ToolChains/AIX.h b/clang/lib/Driver/ToolChains/AIX.h index e03aebcc3e7f0..cc74e5ea85efc 100644 --- a/clang/lib/Driver/ToolChains/AIX.h +++ b/clang/lib/Driver/ToolChains/AIX.h @@ -80,6 +80,10 @@ class LLVM_LIBRARY_VISIBILITY AIX : public ToolChain { void AddCXXStdlibLibArgs(const llvm::opt::ArgList &Args, llvm::opt::ArgStringList &CmdArgs) const override; + void addClangTargetOptions( + const llvm::opt::ArgList &Args, llvm::opt::ArgStringList &CC1Args, + Action::OffloadKind DeviceOffloadingKind) const override; + void addProfileRTLibs(const llvm::opt::ArgList &Args, llvm::opt::ArgStringList &CmdArgs) const override; diff --git a/clang/lib/Driver/ToolChains/Arch/PPC.cpp b/clang/lib/Driver/ToolChains/Arch/PPC.cpp index befbd365fd03f..ab24d14992cd7 100644 --- a/clang/lib/Driver/ToolChains/Arch/PPC.cpp +++ b/clang/lib/Driver/ToolChains/Arch/PPC.cpp @@ -87,10 +87,6 @@ std::string ppc::getPPCTuneCPU(const ArgList &Args, const llvm::Triple &T) { /// Get the (LLVM) name of the PowerPC cpu we are targeting. std::string ppc::getPPCTargetCPU(const Driver &D, const ArgList &Args, const llvm::Triple &T) { - if (const Arg *A = Args.getLastArg(clang::driver::options::OPT_march_EQ)) { - D.Diag(diag::err_drv_unsupported_opt_for_target) - << A->getSpelling() << T.getTriple(); - } if (Arg *A = Args.getLastArg(clang::driver::options::OPT_mcpu_EQ)) return normalizeCPUName(A->getValue(), T); return getPPCGenericTargetCPU(T); diff --git a/clang/lib/Driver/ToolChains/Arch/Sparc.cpp b/clang/lib/Driver/ToolChains/Arch/Sparc.cpp index e775599e8f5f7..11c9444fde2b1 100644 --- a/clang/lib/Driver/ToolChains/Arch/Sparc.cpp +++ b/clang/lib/Driver/ToolChains/Arch/Sparc.cpp @@ -118,12 +118,6 @@ sparc::FloatABI sparc::getSparcFloatABI(const Driver &D, std::string sparc::getSparcTargetCPU(const Driver &D, const ArgList &Args, const llvm::Triple &Triple) { - if (const Arg *A = Args.getLastArg(clang::driver::options::OPT_march_EQ)) { - D.Diag(diag::err_drv_unsupported_opt_for_target) - << A->getSpelling() << Triple.getTriple(); - return ""; - } - if (const Arg *A = Args.getLastArg(clang::driver::options::OPT_mcpu_EQ)) { StringRef CPUName = A->getValue(); if (CPUName == "native") { diff --git a/clang/lib/Driver/ToolChains/Clang.cpp b/clang/lib/Driver/ToolChains/Clang.cpp index e9d49fb556416..5a7dbe1debc65 100644 --- a/clang/lib/Driver/ToolChains/Clang.cpp +++ b/clang/lib/Driver/ToolChains/Clang.cpp @@ -716,12 +716,7 @@ static void addPGOAndCoverageFlags(const ToolChain &TC, Compilation &C, PGOGenerateArg->getOption().matches(options::OPT_fno_profile_generate)) PGOGenerateArg = nullptr; - auto *CSPGOGenerateArg = Args.getLastArg(options::OPT_fcs_profile_generate, - options::OPT_fcs_profile_generate_EQ, - options::OPT_fno_profile_generate); - if (CSPGOGenerateArg && - CSPGOGenerateArg->getOption().matches(options::OPT_fno_profile_generate)) - CSPGOGenerateArg = nullptr; + auto *CSPGOGenerateArg = getLastCSProfileGenerateArg(Args); auto *ProfileGenerateArg = Args.getLastArg( options::OPT_fprofile_instr_generate, @@ -4111,6 +4106,9 @@ static void RenderDiagnosticsOptions(const Driver &D, const ArgList &Args, Args.addOptOutFlag(CmdArgs, options::OPT_fshow_source_location, options::OPT_fno_show_source_location); + Args.addOptOutFlag(CmdArgs, options::OPT_fdiagnostics_show_line_numbers, + options::OPT_fno_diagnostics_show_line_numbers); + if (Args.hasArg(options::OPT_fdiagnostics_absolute_paths)) CmdArgs.push_back("-fdiagnostics-absolute-paths"); @@ -4158,9 +4156,9 @@ static void renderDwarfFormat(const Driver &D, const llvm::Triple &T, else if (!T.isArch64Bit()) D.Diag(diag::err_drv_argument_only_allowed_with) << DwarfFormatArg->getAsString(Args) << "64 bit architecture"; - else if (!(T.isOSBinFormatELF() || T.isOSBinFormatXCOFF())) + else if (!T.isOSBinFormatELF()) D.Diag(diag::err_drv_argument_only_allowed_with) - << DwarfFormatArg->getAsString(Args) << "ELF/XCOFF platforms"; + << DwarfFormatArg->getAsString(Args) << "ELF platforms"; } DwarfFormatArg->render(Args, CmdArgs); @@ -5275,19 +5273,6 @@ void Clang::ConstructJob(Compilation &C, const JobAction &JA, << A->getSpelling() << RawTriple.str(); } - if (Args.hasArg(options::OPT_mxcoff_roptr) || - Args.hasArg(options::OPT_mno_xcoff_roptr)) { - bool HasRoptr = Args.hasFlag(options::OPT_mxcoff_roptr, - options::OPT_mno_xcoff_roptr, false); - StringRef OptStr = HasRoptr ? "-mxcoff-roptr" : "-mno-xcoff-roptr"; - if (!Triple.isOSAIX()) - D.Diag(diag::err_drv_unsupported_opt_for_target) - << OptStr << RawTriple.str(); - - if (HasRoptr) - CmdArgs.push_back("-mxcoff-roptr"); - } - if (Arg *A = Args.getLastArg(options::OPT_Wframe_larger_than_EQ)) { StringRef V = A->getValue(), V1 = V; unsigned Size; @@ -6147,23 +6132,6 @@ void Clang::ConstructJob(Compilation &C, const JobAction &JA, } } - if (const Arg *A = Args.getLastArg(options::OPT_mignore_xcoff_visibility)) { - if (Triple.isOSAIX()) - CmdArgs.push_back("-mignore-xcoff-visibility"); - else - D.Diag(diag::err_drv_unsupported_opt_for_target) - << A->getAsString(Args) << TripleStr; - } - - if (const Arg *A = - Args.getLastArg(options::OPT_mdefault_visibility_export_mapping_EQ)) { - if (Triple.isOSAIX()) - A->render(Args, CmdArgs); - else - D.Diag(diag::err_drv_unsupported_opt_for_target) - << A->getAsString(Args) << TripleStr; - } - if (Args.hasFlag(options::OPT_fvisibility_inlines_hidden, options::OPT_fno_visibility_inlines_hidden, false)) CmdArgs.push_back("-fvisibility-inlines-hidden"); @@ -6976,10 +6944,6 @@ void Clang::ConstructJob(Compilation &C, const JobAction &JA, Args.addOptInFlag(CmdArgs, options::OPT_fapple_pragma_pack, options::OPT_fno_apple_pragma_pack); - if (Args.hasFlag(options::OPT_fxl_pragma_pack, - options::OPT_fno_xl_pragma_pack, RawTriple.isOSAIX())) - CmdArgs.push_back("-fxl-pragma-pack"); - // Remarks can be enabled with any of the `-f.*optimization-record.*` flags. if (willEmitRemarks(Args) && checkRemarksOptions(D, Args, Triple)) renderRemarksOptions(Args, CmdArgs, Triple, Input, Output, JA); diff --git a/clang/lib/Driver/ToolChains/CommonArgs.cpp b/clang/lib/Driver/ToolChains/CommonArgs.cpp index 1ed93ba8b61b8..a952fdbacb386 100644 --- a/clang/lib/Driver/ToolChains/CommonArgs.cpp +++ b/clang/lib/Driver/ToolChains/CommonArgs.cpp @@ -337,6 +337,7 @@ void tools::AddTargetFeature(const ArgList &Args, /// Get the (LLVM) name of the AMDGPU gpu we are targeting. static std::string getAMDGPUTargetGPU(const llvm::Triple &T, const ArgList &Args) { + Arg *MArch = Args.getLastArg(options::OPT_march_EQ); if (Arg *A = Args.getLastArg(options::OPT_mcpu_EQ)) { auto GPUName = getProcessorFromTargetID(T, A->getValue()); return llvm::StringSwitch(GPUName) @@ -349,9 +350,8 @@ static std::string getAMDGPUTargetGPU(const llvm::Triple &T, .Case("aruba", "cayman") .Default(GPUName.str()); } - if (Arg *A = Args.getLastArg(options::OPT_march_EQ)) { - return getProcessorFromTargetID(T, A->getValue()).str(); - } + if (MArch) + return getProcessorFromTargetID(T, MArch->getValue()).str(); return ""; } @@ -772,16 +772,7 @@ void tools::addLTOOptions(const ToolChain &ToolChain, const ArgList &Args, "sample-profile=" + FName)); } - auto *CSPGOGenerateArg = Args.getLastArg(options::OPT_fcs_profile_generate, - options::OPT_fcs_profile_generate_EQ, - options::OPT_fno_profile_generate); - if (CSPGOGenerateArg && - CSPGOGenerateArg->getOption().matches(options::OPT_fno_profile_generate)) - CSPGOGenerateArg = nullptr; - - auto *ProfileUseArg = getLastProfileUseArg(Args); - - if (CSPGOGenerateArg) { + if (auto *CSPGOGenerateArg = getLastCSProfileGenerateArg(Args)) { CmdArgs.push_back(Args.MakeArgString(Twine(PluginOptPrefix) + ExtraDash + "cs-profile-generate")); if (CSPGOGenerateArg->getOption().matches( @@ -794,7 +785,7 @@ void tools::addLTOOptions(const ToolChain &ToolChain, const ArgList &Args, CmdArgs.push_back( Args.MakeArgString(Twine(PluginOptPrefix) + ExtraDash + "cs-profile-path=default_%m.profraw")); - } else if (ProfileUseArg) { + } else if (auto *ProfileUseArg = getLastProfileUseArg(Args)) { SmallString<128> Path( ProfileUseArg->getNumValues() == 0 ? "" : ProfileUseArg->getValue()); if (Path.empty() || llvm::sys::fs::is_directory(Path)) @@ -1348,6 +1339,17 @@ void tools::claimNoWarnArgs(const ArgList &Args) { Args.ClaimAllArgs(options::OPT_fno_lto); } +Arg *tools::getLastCSProfileGenerateArg(const ArgList &Args) { + auto *CSPGOGenerateArg = Args.getLastArg(options::OPT_fcs_profile_generate, + options::OPT_fcs_profile_generate_EQ, + options::OPT_fno_profile_generate); + if (CSPGOGenerateArg && + CSPGOGenerateArg->getOption().matches(options::OPT_fno_profile_generate)) + CSPGOGenerateArg = nullptr; + + return CSPGOGenerateArg; +} + Arg *tools::getLastProfileUseArg(const ArgList &Args) { auto *ProfileUseArg = Args.getLastArg( options::OPT_fprofile_instr_use, options::OPT_fprofile_instr_use_EQ, diff --git a/clang/lib/Driver/ToolChains/CommonArgs.h b/clang/lib/Driver/ToolChains/CommonArgs.h index c196cbc28e218..66948f3f586ba 100644 --- a/clang/lib/Driver/ToolChains/CommonArgs.h +++ b/clang/lib/Driver/ToolChains/CommonArgs.h @@ -143,6 +143,7 @@ void addHIPRuntimeLibArgs(const ToolChain &TC, const llvm::opt::ArgList &Args, const char *getAsNeededOption(const ToolChain &TC, bool as_needed); +llvm::opt::Arg *getLastCSProfileGenerateArg(const llvm::opt::ArgList &Args); llvm::opt::Arg *getLastProfileUseArg(const llvm::opt::ArgList &Args); llvm::opt::Arg *getLastProfileSampleUseArg(const llvm::opt::ArgList &Args); diff --git a/clang/lib/Driver/ToolChains/Darwin.cpp b/clang/lib/Driver/ToolChains/Darwin.cpp index 3ab8bc8c8ec9f..922eb8a5eba8e 100644 --- a/clang/lib/Driver/ToolChains/Darwin.cpp +++ b/clang/lib/Driver/ToolChains/Darwin.cpp @@ -449,6 +449,23 @@ void darwin::Linker::AddLinkArgs(Compilation &C, const ArgList &Args, Args.AddAllArgs(CmdArgs, options::OPT_dylinker__install__name); Args.AddLastArg(CmdArgs, options::OPT_dylinker); Args.AddLastArg(CmdArgs, options::OPT_Mach); + + if (LinkerIsLLD) { + if (auto *CSPGOGenerateArg = getLastCSProfileGenerateArg(Args)) { + SmallString<128> Path(CSPGOGenerateArg->getNumValues() == 0 + ? "" + : CSPGOGenerateArg->getValue()); + llvm::sys::path::append(Path, "default_%m.profraw"); + CmdArgs.push_back("--cs-profile-generate"); + CmdArgs.push_back(Args.MakeArgString(Twine("--cs-profile-path=") + Path)); + } else if (auto *ProfileUseArg = getLastProfileUseArg(Args)) { + SmallString<128> Path( + ProfileUseArg->getNumValues() == 0 ? "" : ProfileUseArg->getValue()); + if (Path.empty() || llvm::sys::fs::is_directory(Path)) + llvm::sys::path::append(Path, "default.profdata"); + CmdArgs.push_back(Args.MakeArgString(Twine("--cs-profile-path=") + Path)); + } + } } /// Determine whether we are linking the ObjC runtime. @@ -1204,6 +1221,9 @@ void DarwinClang::AddLinkARCArgs(const ArgList &Args, P += "macosx"; P += ".a"; + if (!getVFS().exists(P)) + getDriver().Diag(clang::diag::err_drv_darwin_sdk_missing_arclite) << P; + CmdArgs.push_back(Args.MakeArgString(P)); } diff --git a/clang/lib/ExtractAPI/CMakeLists.txt b/clang/lib/ExtractAPI/CMakeLists.txt index 153d4b992fda7..b43fe742478ce 100644 --- a/clang/lib/ExtractAPI/CMakeLists.txt +++ b/clang/lib/ExtractAPI/CMakeLists.txt @@ -9,7 +9,6 @@ add_clang_library(clangExtractAPI AvailabilityInfo.cpp ExtractAPIConsumer.cpp DeclarationFragments.cpp - Serialization/SerializerBase.cpp Serialization/SymbolGraphSerializer.cpp TypedefUnderlyingTypeResolver.cpp diff --git a/clang/lib/ExtractAPI/Serialization/SerializerBase.cpp b/clang/lib/ExtractAPI/Serialization/SerializerBase.cpp deleted file mode 100644 index 71fd25b2b2abb..0000000000000 --- a/clang/lib/ExtractAPI/Serialization/SerializerBase.cpp +++ /dev/null @@ -1,19 +0,0 @@ -//===- ExtractAPI/Serialization/SerializerBase.cpp --------------*- C++ -*-===// -// -// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. -// See https://llvm.org/LICENSE.txt for license information. -// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -// -//===----------------------------------------------------------------------===// -/// -/// \file -/// This file implements the APISerializer interface. -/// -//===----------------------------------------------------------------------===// - -#include "clang/ExtractAPI/Serialization/SerializerBase.h" -#include "llvm/Support/raw_ostream.h" - -using namespace clang::extractapi; - -void APISerializer::serialize(llvm::raw_ostream &os) {} diff --git a/clang/lib/ExtractAPI/Serialization/SymbolGraphSerializer.cpp b/clang/lib/ExtractAPI/Serialization/SymbolGraphSerializer.cpp index 7676c74af6869..534e9288cc713 100644 --- a/clang/lib/ExtractAPI/Serialization/SymbolGraphSerializer.cpp +++ b/clang/lib/ExtractAPI/Serialization/SymbolGraphSerializer.cpp @@ -14,16 +14,11 @@ #include "clang/ExtractAPI/Serialization/SymbolGraphSerializer.h" #include "clang/Basic/SourceLocation.h" #include "clang/Basic/Version.h" -#include "clang/ExtractAPI/API.h" -#include "clang/ExtractAPI/APIIgnoresList.h" #include "clang/ExtractAPI/DeclarationFragments.h" -#include "clang/ExtractAPI/Serialization/SerializerBase.h" #include "llvm/ADT/STLExtras.h" #include "llvm/ADT/STLFunctionalExtras.h" -#include "llvm/ADT/SmallVector.h" #include "llvm/Support/Casting.h" #include "llvm/Support/Compiler.h" -#include "llvm/Support/JSON.h" #include "llvm/Support/Path.h" #include "llvm/Support/VersionTuple.h" #include @@ -541,19 +536,16 @@ template Array generateParentContexts(const RecordTy &Record, const APISet &API, Language Lang) { Array ParentContexts; - generatePathComponents(Record, API, - [Lang, &ParentContexts](const PathComponent &PC) { - ParentContexts.push_back( - serializeParentContext(PC, Lang)); - }); + generatePathComponents( + Record, API, [Lang, &ParentContexts](const PathComponent &PC) { + ParentContexts.push_back(serializeParentContext(PC, Lang)); + }); return ParentContexts; } } // namespace -void SymbolGraphSerializer::anchor() {} - /// Defines the format version emitted by SymbolGraphSerializer. const VersionTuple SymbolGraphSerializer::FormatVersion{0, 5, 3}; @@ -670,7 +662,7 @@ void SymbolGraphSerializer::serializeRelationship(RelationshipKind Kind, Relationships.emplace_back(std::move(Relationship)); } -void SymbolGraphSerializer::serializeGlobalFunctionRecord( +void SymbolGraphSerializer::visitGlobalFunctionRecord( const GlobalFunctionRecord &Record) { auto Obj = serializeAPIRecord(Record); if (!Obj) @@ -679,7 +671,7 @@ void SymbolGraphSerializer::serializeGlobalFunctionRecord( Symbols.emplace_back(std::move(*Obj)); } -void SymbolGraphSerializer::serializeGlobalVariableRecord( +void SymbolGraphSerializer::visitGlobalVariableRecord( const GlobalVariableRecord &Record) { auto Obj = serializeAPIRecord(Record); if (!Obj) @@ -688,7 +680,7 @@ void SymbolGraphSerializer::serializeGlobalVariableRecord( Symbols.emplace_back(std::move(*Obj)); } -void SymbolGraphSerializer::serializeEnumRecord(const EnumRecord &Record) { +void SymbolGraphSerializer::visitEnumRecord(const EnumRecord &Record) { auto Enum = serializeAPIRecord(Record); if (!Enum) return; @@ -697,7 +689,7 @@ void SymbolGraphSerializer::serializeEnumRecord(const EnumRecord &Record) { serializeMembers(Record, Record.Constants); } -void SymbolGraphSerializer::serializeStructRecord(const StructRecord &Record) { +void SymbolGraphSerializer::visitStructRecord(const StructRecord &Record) { auto Struct = serializeAPIRecord(Record); if (!Struct) return; @@ -706,7 +698,7 @@ void SymbolGraphSerializer::serializeStructRecord(const StructRecord &Record) { serializeMembers(Record, Record.Fields); } -void SymbolGraphSerializer::serializeObjCContainerRecord( +void SymbolGraphSerializer::visitObjCContainerRecord( const ObjCContainerRecord &Record) { auto ObjCContainer = serializeAPIRecord(Record); if (!ObjCContainer) @@ -743,7 +735,7 @@ void SymbolGraphSerializer::serializeObjCContainerRecord( } } -void SymbolGraphSerializer::serializeMacroDefinitionRecord( +void SymbolGraphSerializer::visitMacroDefinitionRecord( const MacroDefinitionRecord &Record) { auto Macro = serializeAPIRecord(Record); @@ -758,28 +750,28 @@ void SymbolGraphSerializer::serializeSingleRecord(const APIRecord *Record) { case APIRecord::RK_Unknown: llvm_unreachable("Records should have a known kind!"); case APIRecord::RK_GlobalFunction: - serializeGlobalFunctionRecord(*cast(Record)); + visitGlobalFunctionRecord(*cast(Record)); break; case APIRecord::RK_GlobalVariable: - serializeGlobalVariableRecord(*cast(Record)); + visitGlobalVariableRecord(*cast(Record)); break; case APIRecord::RK_Enum: - serializeEnumRecord(*cast(Record)); + visitEnumRecord(*cast(Record)); break; case APIRecord::RK_Struct: - serializeStructRecord(*cast(Record)); + visitStructRecord(*cast(Record)); break; case APIRecord::RK_ObjCInterface: - serializeObjCContainerRecord(*cast(Record)); + visitObjCContainerRecord(*cast(Record)); break; case APIRecord::RK_ObjCProtocol: - serializeObjCContainerRecord(*cast(Record)); + visitObjCContainerRecord(*cast(Record)); break; case APIRecord::RK_MacroDefinition: - serializeMacroDefinitionRecord(*cast(Record)); + visitMacroDefinitionRecord(*cast(Record)); break; case APIRecord::RK_Typedef: - serializeTypedefRecord(*cast(Record)); + visitTypedefRecord(*cast(Record)); break; default: if (auto Obj = serializeAPIRecord(*Record)) { @@ -793,8 +785,7 @@ void SymbolGraphSerializer::serializeSingleRecord(const APIRecord *Record) { } } -void SymbolGraphSerializer::serializeTypedefRecord( - const TypedefRecord &Record) { +void SymbolGraphSerializer::visitTypedefRecord(const TypedefRecord &Record) { // Typedefs of anonymous types have their entries unified with the underlying // type. bool ShouldDrop = Record.UnderlyingType.Name.empty(); @@ -814,35 +805,7 @@ void SymbolGraphSerializer::serializeTypedefRecord( } Object SymbolGraphSerializer::serialize() { - // Serialize global variables in the API set. - for (const auto &GlobalVar : API.getGlobalVariables()) - serializeGlobalVariableRecord(*GlobalVar.second); - - for (const auto &GlobalFunction : API.getGlobalFunctions()) - serializeGlobalFunctionRecord(*GlobalFunction.second); - - // Serialize enum records in the API set. - for (const auto &Enum : API.getEnums()) - serializeEnumRecord(*Enum.second); - - // Serialize struct records in the API set. - for (const auto &Struct : API.getStructs()) - serializeStructRecord(*Struct.second); - - // Serialize Objective-C interface records in the API set. - for (const auto &ObjCInterface : API.getObjCInterfaces()) - serializeObjCContainerRecord(*ObjCInterface.second); - - // Serialize Objective-C protocol records in the API set. - for (const auto &ObjCProtocol : API.getObjCProtocols()) - serializeObjCContainerRecord(*ObjCProtocol.second); - - for (const auto &Macro : API.getMacros()) - serializeMacroDefinitionRecord(*Macro.second); - - for (const auto &Typedef : API.getTypedefs()) - serializeTypedefRecord(*Typedef.second); - + traverseAPISet(); return serializeCurrentGraph(); } diff --git a/clang/lib/Format/Format.cpp b/clang/lib/Format/Format.cpp index 154e6a21981e8..6e2b6a662e7e1 100644 --- a/clang/lib/Format/Format.cpp +++ b/clang/lib/Format/Format.cpp @@ -375,6 +375,7 @@ template <> struct ScalarEnumerationTraits { IO.enumCase(Value, "TextProto", FormatStyle::LK_TextProto); IO.enumCase(Value, "CSharp", FormatStyle::LK_CSharp); IO.enumCase(Value, "Json", FormatStyle::LK_Json); + IO.enumCase(Value, "Verilog", FormatStyle::LK_Verilog); } }; @@ -2687,6 +2688,8 @@ class ObjCHeaderStyleGuesser : public TokenAnalyzer { "CGSizeMake", "CGVector", "CGVectorMake", + "FOUNDATION_EXPORT", // This is an alias for FOUNDATION_EXTERN. + "FOUNDATION_EXTERN", "NSAffineTransform", "NSArray", "NSAttributedString", @@ -2743,6 +2746,7 @@ class ObjCHeaderStyleGuesser : public TokenAnalyzer { "NSURLQueryItem", "NSUUID", "NSValue", + "NS_ASSUME_NONNULL_BEGIN", "UIImage", "UIView", }; diff --git a/clang/lib/Format/UnwrappedLineFormatter.cpp b/clang/lib/Format/UnwrappedLineFormatter.cpp index 33be74dfe1b9f..fc5d4150ed777 100644 --- a/clang/lib/Format/UnwrappedLineFormatter.cpp +++ b/clang/lib/Format/UnwrappedLineFormatter.cpp @@ -1418,19 +1418,12 @@ unsigned UnwrappedLineFormatter::format( return Penalty; } -void UnwrappedLineFormatter::formatFirstToken( - const AnnotatedLine &Line, const AnnotatedLine *PreviousLine, - const AnnotatedLine *PrevPrevLine, - const SmallVectorImpl &Lines, unsigned Indent, - unsigned NewlineIndent) { - FormatToken &RootToken = *Line.First; - if (RootToken.is(tok::eof)) { - unsigned Newlines = std::min(RootToken.NewlinesBefore, 1u); - unsigned TokenIndent = Newlines ? NewlineIndent : 0; - Whitespaces->replaceWhitespace(RootToken, Newlines, TokenIndent, - TokenIndent); - return; - } +static auto newlinesBeforeLine(const AnnotatedLine &Line, + const AnnotatedLine *PreviousLine, + const AnnotatedLine *PrevPrevLine, + const SmallVectorImpl &Lines, + const FormatStyle &Style) { + const auto &RootToken = *Line.First; unsigned Newlines = std::min(RootToken.NewlinesBefore, Style.MaxEmptyLinesToKeep + 1); // Remove empty lines before "}" where applicable. @@ -1510,6 +1503,27 @@ void UnwrappedLineFormatter::formatFirstToken( } } + return Newlines; +} + +void UnwrappedLineFormatter::formatFirstToken( + const AnnotatedLine &Line, const AnnotatedLine *PreviousLine, + const AnnotatedLine *PrevPrevLine, + const SmallVectorImpl &Lines, unsigned Indent, + unsigned NewlineIndent) { + FormatToken &RootToken = *Line.First; + if (RootToken.is(tok::eof)) { + unsigned Newlines = std::min(RootToken.NewlinesBefore, 1u); + unsigned TokenIndent = Newlines ? NewlineIndent : 0; + Whitespaces->replaceWhitespace(RootToken, Newlines, TokenIndent, + TokenIndent); + return; + } + + const auto Newlines = + RootToken.Finalized + ? RootToken.NewlinesBefore + : newlinesBeforeLine(Line, PreviousLine, PrevPrevLine, Lines, Style); if (Newlines) Indent = NewlineIndent; diff --git a/clang/lib/Frontend/CompilerInvocation.cpp b/clang/lib/Frontend/CompilerInvocation.cpp index a1d836feea9d5..f74bca3b33b1d 100644 --- a/clang/lib/Frontend/CompilerInvocation.cpp +++ b/clang/lib/Frontend/CompilerInvocation.cpp @@ -2394,9 +2394,9 @@ bool clang::ParseDiagnosticArgs(DiagnosticOptions &Opts, ArgList &Args, DiagMask = DiagnosticLevelMask::All; Opts.setVerifyIgnoreUnexpected(DiagMask); if (Opts.TabStop == 0 || Opts.TabStop > DiagnosticOptions::MaxTabStop) { - Opts.TabStop = DiagnosticOptions::DefaultTabStop; Diags->Report(diag::warn_ignoring_ftabstop_value) << Opts.TabStop << DiagnosticOptions::DefaultTabStop; + Opts.TabStop = DiagnosticOptions::DefaultTabStop; } addDiagnosticArgs(Args, OPT_W_Group, OPT_W_value_Group, Opts.Warnings); diff --git a/clang/lib/Frontend/FrontendAction.cpp b/clang/lib/Frontend/FrontendAction.cpp index bd6d1b03e8f30..cfac2f8c4e5a6 100644 --- a/clang/lib/Frontend/FrontendAction.cpp +++ b/clang/lib/Frontend/FrontendAction.cpp @@ -364,18 +364,19 @@ static std::error_code collectModuleHeaderIncludes( } // Note that Module->PrivateHeaders will not be a TopHeader. - if (Module::Header UmbrellaHeader = Module->getUmbrellaHeaderAsWritten()) { - Module->addTopHeader(UmbrellaHeader.Entry); + if (std::optional UmbrellaHeader = + Module->getUmbrellaHeaderAsWritten()) { + Module->addTopHeader(UmbrellaHeader->Entry); if (Module->Parent) // Include the umbrella header for submodules. - addHeaderInclude(UmbrellaHeader.PathRelativeToRootModuleDirectory, + addHeaderInclude(UmbrellaHeader->PathRelativeToRootModuleDirectory, Includes, LangOpts, Module->IsExternC); - } else if (Module::DirectoryName UmbrellaDir = + } else if (std::optional UmbrellaDir = Module->getUmbrellaDirAsWritten()) { // Add all of the headers we find in this subdirectory. std::error_code EC; SmallString<128> DirNative; - llvm::sys::path::native(UmbrellaDir.Entry->getName(), DirNative); + llvm::sys::path::native(UmbrellaDir->Entry.getName(), DirNative); llvm::vfs::FileSystem &FS = FileMgr.getVirtualFileSystem(); SmallVector< @@ -407,7 +408,7 @@ static std::error_code collectModuleHeaderIncludes( for (int I = 0; I != Dir.level() + 1; ++I, ++PathIt) Components.push_back(*PathIt); SmallString<128> RelativeHeader( - UmbrellaDir.PathRelativeToRootModuleDirectory); + UmbrellaDir->PathRelativeToRootModuleDirectory); for (auto It = Components.rbegin(), End = Components.rend(); It != End; ++It) llvm::sys::path::append(RelativeHeader, *It); @@ -447,7 +448,8 @@ static bool loadModuleMapForModuleBuild(CompilerInstance &CI, bool IsSystem, // Map the current input to a file. FileID ModuleMapID = SrcMgr.getMainFileID(); - const FileEntry *ModuleMap = SrcMgr.getFileEntryForID(ModuleMapID); + OptionalFileEntryRef ModuleMap = SrcMgr.getFileEntryRefForID(ModuleMapID); + assert(ModuleMap && "MainFileID without FileEntry"); // If the module map is preprocessed, handle the initial line marker; // line directives are not part of the module map syntax in general. @@ -460,7 +462,7 @@ static bool loadModuleMapForModuleBuild(CompilerInstance &CI, bool IsSystem, } // Load the module map file. - if (HS.loadModuleMapFile(ModuleMap, IsSystem, ModuleMapID, &Offset, + if (HS.loadModuleMapFile(*ModuleMap, IsSystem, ModuleMapID, &Offset, PresumedModuleMapFile)) return true; @@ -469,10 +471,11 @@ static bool loadModuleMapForModuleBuild(CompilerInstance &CI, bool IsSystem, // Infer framework module if possible. if (HS.getModuleMap().canInferFrameworkModule(ModuleMap->getDir())) { - SmallString<128> InferredFrameworkPath = ModuleMap->getDir()->getName(); + SmallString<128> InferredFrameworkPath = ModuleMap->getDir().getName(); llvm::sys::path::append(InferredFrameworkPath, CI.getLangOpts().ModuleName + ".framework"); - if (auto Dir = CI.getFileManager().getDirectory(InferredFrameworkPath)) + if (auto Dir = + CI.getFileManager().getOptionalDirectoryRef(InferredFrameworkPath)) (void)HS.getModuleMap().inferFrameworkModule(*Dir, IsSystem, nullptr); } @@ -509,7 +512,7 @@ static Module *prepareToBuildModule(CompilerInstance &CI, // Inform the preprocessor that includes from within the input buffer should // be resolved relative to the build directory of the module map file. - CI.getPreprocessor().setMainFileDir(M->Directory); + CI.getPreprocessor().setMainFileDir(*M->Directory); // If the module was inferred from a different module map (via an expanded // umbrella module definition), track that fact. @@ -551,8 +554,9 @@ getInputBufferForModule(CompilerInstance &CI, Module *M) { // Collect the set of #includes we need to build the module. SmallString<256> HeaderContents; std::error_code Err = std::error_code(); - if (Module::Header UmbrellaHeader = M->getUmbrellaHeaderAsWritten()) - addHeaderInclude(UmbrellaHeader.PathRelativeToRootModuleDirectory, + if (std::optional UmbrellaHeader = + M->getUmbrellaHeaderAsWritten()) + addHeaderInclude(UmbrellaHeader->PathRelativeToRootModuleDirectory, HeaderContents, CI.getLangOpts(), M->IsExternC); Err = collectModuleHeaderIncludes( CI.getLangOpts(), FileMgr, CI.getDiagnostics(), @@ -821,11 +825,9 @@ bool FrontendAction::BeginSourceFile(CompilerInstance &CI, "trying to build a header unit without a Pre-processor?"); HeaderSearch &HS = CI.getPreprocessor().getHeaderSearchInfo(); // Relative searches begin from CWD. - const DirectoryEntry *Dir = nullptr; - if (auto DirOrErr = CI.getFileManager().getDirectory(".")) - Dir = *DirOrErr; - SmallVector, 1> CWD; - CWD.push_back({nullptr, Dir}); + auto Dir = CI.getFileManager().getOptionalDirectoryRef("."); + SmallVector, 1> CWD; + CWD.push_back({nullptr, *Dir}); OptionalFileEntryRef FE = HS.LookupFile(FileName, SourceLocation(), /*Angled*/ Input.getKind().getHeaderUnitKind() == @@ -910,7 +912,7 @@ bool FrontendAction::BeginSourceFile(CompilerInstance &CI, // If we were asked to load any module map files, do so now. for (const auto &Filename : CI.getFrontendOpts().ModuleMapFiles) { - if (auto File = CI.getFileManager().getFile(Filename)) + if (auto File = CI.getFileManager().getOptionalFileRef(Filename)) CI.getPreprocessor().getHeaderSearchInfo().loadModuleMapFile( *File, /*IsSystem*/false); else diff --git a/clang/lib/Frontend/ModuleDependencyCollector.cpp b/clang/lib/Frontend/ModuleDependencyCollector.cpp index b4b312bc93b94..939e611e54899 100644 --- a/clang/lib/Frontend/ModuleDependencyCollector.cpp +++ b/clang/lib/Frontend/ModuleDependencyCollector.cpp @@ -72,37 +72,12 @@ struct ModuleDependencyMMCallbacks : public ModuleMapCallbacks { if (llvm::sys::path::is_absolute(HeaderPath)) Collector.addFile(HeaderPath); } - void moduleMapAddUmbrellaHeader(FileManager *FileMgr, - const FileEntry *Header) override { - StringRef HeaderFilename = Header->getName(); - moduleMapAddHeader(HeaderFilename); - // The FileManager can find and cache the symbolic link for a framework - // header before its real path, this means a module can have some of its - // headers to use other paths. Although this is usually not a problem, it's - // inconsistent, and not collecting the original path header leads to - // umbrella clashes while rebuilding modules in the crash reproducer. For - // example: - // ApplicationServices.framework/Frameworks/ImageIO.framework/ImageIO.h - // instead of: - // ImageIO.framework/ImageIO.h - // - // FIXME: this shouldn't be necessary once we have FileName instances - // around instead of FileEntry ones. For now, make sure we collect all - // that we need for the reproducer to work correctly. - StringRef UmbreallDirFromHeader = - llvm::sys::path::parent_path(HeaderFilename); - StringRef UmbrellaDir = Header->getDir()->getName(); - if (!UmbrellaDir.equals(UmbreallDirFromHeader)) { - SmallString<128> AltHeaderFilename; - llvm::sys::path::append(AltHeaderFilename, UmbrellaDir, - llvm::sys::path::filename(HeaderFilename)); - if (FileMgr->getFile(AltHeaderFilename)) - moduleMapAddHeader(AltHeaderFilename); - } + void moduleMapAddUmbrellaHeader(FileEntryRef Header) override { + moduleMapAddHeader(Header.getNameAsRequested()); } }; -} +} // namespace void ModuleDependencyCollector::attachToASTReader(ASTReader &R) { R.addListener( diff --git a/clang/lib/Frontend/PrecompiledPreamble.cpp b/clang/lib/Frontend/PrecompiledPreamble.cpp index a47d2b0be004c..5ffb54e2fdf65 100644 --- a/clang/lib/Frontend/PrecompiledPreamble.cpp +++ b/clang/lib/Frontend/PrecompiledPreamble.cpp @@ -113,16 +113,16 @@ class MissingFileCollector : public PPCallbacks { // Reconstruct the filenames that would satisfy this directive... llvm::SmallString<256> Buf; - auto NotFoundRelativeTo = [&](const DirectoryEntry *DE) { - Buf = DE->getName(); + auto NotFoundRelativeTo = [&](DirectoryEntryRef DE) { + Buf = DE.getName(); llvm::sys::path::append(Buf, FileName); llvm::sys::path::remove_dots(Buf, /*remove_dot_dot=*/true); Out.insert(Buf); }; // ...relative to the including file. if (!IsAngled) { - if (const FileEntry *IncludingFile = - SM.getFileEntryForID(SM.getFileID(IncludeTok.getLocation()))) + if (OptionalFileEntryRef IncludingFile = + SM.getFileEntryRefForID(SM.getFileID(IncludeTok.getLocation()))) if (IncludingFile->getDir()) NotFoundRelativeTo(IncludingFile->getDir()); } @@ -132,7 +132,7 @@ class MissingFileCollector : public PPCallbacks { Search.search_dir_end())) { // No support for frameworks or header maps yet. if (Dir.isNormalDir()) - NotFoundRelativeTo(Dir.getDir()); + NotFoundRelativeTo(*Dir.getDirRef()); } } }; diff --git a/clang/lib/Frontend/TextDiagnostic.cpp b/clang/lib/Frontend/TextDiagnostic.cpp index 08f84d28bb852..137001dc050d1 100644 --- a/clang/lib/Frontend/TextDiagnostic.cpp +++ b/clang/lib/Frontend/TextDiagnostic.cpp @@ -161,19 +161,33 @@ printableTextForNextCharacter(StringRef SourceLine, size_t *i, } static void expandTabs(std::string &SourceLine, unsigned TabStop) { - size_t i = SourceLine.size(); - while (i>0) { - i--; - if (SourceLine[i]!='\t') + size_t I = SourceLine.size(); + while (I > 0) { + I--; + if (SourceLine[I] != '\t') continue; - size_t tmp_i = i; - std::pair,bool> res - = printableTextForNextCharacter(SourceLine, &tmp_i, TabStop); - SourceLine.replace(i, 1, res.first.c_str()); + size_t TmpI = I; + auto [Str, Printable] = + printableTextForNextCharacter(SourceLine, &TmpI, TabStop); + SourceLine.replace(I, 1, Str.c_str()); } } -/// This function takes a raw source line and produces a mapping from the bytes +/// \p BytesOut: +/// A mapping from columns to the byte of the source line that produced the +/// character displaying at that column. This is the inverse of \p ColumnsOut. +/// +/// The last element in the array is the number of bytes in the source string. +/// +/// example: (given a tabstop of 8) +/// +/// "a \t \u3042" -> {0,1,2,-1,-1,-1,-1,-1,3,4,-1,7} +/// +/// (\\u3042 is represented in UTF-8 by three bytes and takes two columns to +/// display) +/// +/// \p ColumnsOut: +/// A mapping from the bytes /// of the printable representation of the line to the columns those printable /// characters will appear at (numbering the first column as 0). /// @@ -195,60 +209,34 @@ static void expandTabs(std::string &SourceLine, unsigned TabStop) { /// /// (\\u3042 is represented in UTF-8 by three bytes and takes two columns to /// display) -static void byteToColumn(StringRef SourceLine, unsigned TabStop, - SmallVectorImpl &out) { - out.clear(); +static void genColumnByteMapping(StringRef SourceLine, unsigned TabStop, + SmallVectorImpl &BytesOut, + SmallVectorImpl &ColumnsOut) { + assert(BytesOut.empty()); + assert(ColumnsOut.empty()); if (SourceLine.empty()) { - out.resize(1u,0); + BytesOut.resize(1u, 0); + ColumnsOut.resize(1u, 0); return; } - out.resize(SourceLine.size()+1, -1); - - int columns = 0; - size_t i = 0; - while (i,bool> res - = printableTextForNextCharacter(SourceLine, &i, TabStop); - columns += llvm::sys::locale::columnWidth(res.first); - } - out.back() = columns; -} - -/// This function takes a raw source line and produces a mapping from columns -/// to the byte of the source line that produced the character displaying at -/// that column. This is the inverse of the mapping produced by byteToColumn() -/// -/// The last element in the array is the number of bytes in the source string -/// -/// example: (given a tabstop of 8) -/// -/// "a \t \u3042" -> {0,1,2,-1,-1,-1,-1,-1,3,4,-1,7} -/// -/// (\\u3042 is represented in UTF-8 by three bytes and takes two columns to -/// display) -static void columnToByte(StringRef SourceLine, unsigned TabStop, - SmallVectorImpl &out) { - out.clear(); - - if (SourceLine.empty()) { - out.resize(1u, 0); - return; + ColumnsOut.resize(SourceLine.size() + 1, -1); + + int Columns = 0; + size_t I = 0; + while (I < SourceLine.size()) { + ColumnsOut[I] = Columns; + BytesOut.resize(Columns + 1, -1); + BytesOut.back() = I; + auto [Str, Printable] = + printableTextForNextCharacter(SourceLine, &I, TabStop); + Columns += llvm::sys::locale::columnWidth(Str); } - int columns = 0; - size_t i = 0; - while (i,bool> res - = printableTextForNextCharacter(SourceLine, &i, TabStop); - columns += llvm::sys::locale::columnWidth(res.first); - } - out.resize(columns+1, -1); - out.back() = i; + ColumnsOut.back() = Columns; + BytesOut.resize(Columns + 1, -1); + BytesOut.back() = I; } namespace { @@ -256,8 +244,7 @@ struct SourceColumnMap { SourceColumnMap(StringRef SourceLine, unsigned TabStop) : m_SourceLine(SourceLine) { - ::byteToColumn(SourceLine, TabStop, m_byteToColumn); - ::columnToByte(SourceLine, TabStop, m_columnToByte); + genColumnByteMapping(SourceLine, TabStop, m_columnToByte, m_byteToColumn); assert(m_byteToColumn.size()==SourceLine.size()+1); assert(0 < m_byteToColumn.size() && 0 < m_columnToByte.size()); @@ -471,9 +458,7 @@ static void selectInterestingSourceRegion(std::string &SourceLine, CaretEnd = map.byteToColumn(SourceEnd) + CaretColumnsOutsideSource; // [CaretStart, CaretEnd) is the slice we want. Update the various - // output lines to show only this slice, with two-space padding - // before the lines so that it looks nicer. - + // output lines to show only this slice. assert(CaretStart!=(unsigned)-1 && CaretEnd!=(unsigned)-1 && SourceStart!=(unsigned)-1 && SourceEnd!=(unsigned)-1); assert(SourceStart <= SourceEnd); @@ -605,21 +590,13 @@ static unsigned findEndOfWord(unsigned Start, StringRef Str, /// Str will be printed. This will be non-zero when part of the first /// line has already been printed. /// \param Bold if the current text should be bold -/// \param Indentation the number of spaces to indent any lines beyond -/// the first line. /// \returns true if word-wrapping was required, or false if the /// string fit on the first line. -static bool printWordWrapped(raw_ostream &OS, StringRef Str, - unsigned Columns, - unsigned Column = 0, - bool Bold = false, - unsigned Indentation = WordWrapIndentation) { +static bool printWordWrapped(raw_ostream &OS, StringRef Str, unsigned Columns, + unsigned Column, bool Bold) { const unsigned Length = std::min(Str.find('\n'), Str.size()); bool TextNormal = true; - // The string used to indent each line. - SmallString<16> IndentStr; - IndentStr.assign(Indentation, ' '); bool Wrapped = false; for (unsigned WordStart = 0, WordEnd; WordStart < Length; WordStart = WordEnd) { @@ -648,10 +625,10 @@ static bool printWordWrapped(raw_ostream &OS, StringRef Str, // This word does not fit on the current line, so wrap to the next // line. OS << '\n'; - OS.write(&IndentStr[0], Indentation); + OS.indent(WordWrapIndentation); applyTemplateHighlighting(OS, Str.substr(WordStart, WordLength), TextNormal, Bold); - Column = Indentation + WordLength; + Column = WordWrapIndentation + WordLength; Wrapped = true; } @@ -796,8 +773,7 @@ void TextDiagnostic::emitDiagnosticLoc(FullSourceLoc Loc, PresumedLoc PLoc, ArrayRef Ranges) { if (PLoc.isInvalid()) { // At least print the file name if available: - FileID FID = Loc.getFileID(); - if (FID.isValid()) { + if (FileID FID = Loc.getFileID(); FID.isValid()) { if (const FileEntry *FE = Loc.getFileEntry()) { emitFilename(FE->getName(), Loc.getManager()); OS << ": "; @@ -855,30 +831,26 @@ void TextDiagnostic::emitDiagnosticLoc(FullSourceLoc Loc, PresumedLoc PLoc, if (DiagOpts->ShowSourceRanges && !Ranges.empty()) { FileID CaretFileID = Loc.getExpansionLoc().getFileID(); bool PrintedRange = false; + const SourceManager &SM = Loc.getManager(); for (const auto &R : Ranges) { // Ignore invalid ranges. if (!R.isValid()) continue; - auto &SM = Loc.getManager(); SourceLocation B = SM.getExpansionLoc(R.getBegin()); CharSourceRange ERange = SM.getExpansionRange(R.getEnd()); SourceLocation E = ERange.getEnd(); - bool IsTokenRange = ERange.isTokenRange(); - - std::pair BInfo = SM.getDecomposedLoc(B); - std::pair EInfo = SM.getDecomposedLoc(E); - // If the start or end of the range is in another file, just discard - // it. - if (BInfo.first != CaretFileID || EInfo.first != CaretFileID) + // If the start or end of the range is in another file, just + // discard it. + if (SM.getFileID(B) != CaretFileID || SM.getFileID(E) != CaretFileID) continue; // Add in the length of the token, so that we cover multi-char // tokens. unsigned TokSize = 0; - if (IsTokenRange) + if (ERange.isTokenRange()) TokSize = Lexer::MeasureTokenLength(E, SM, LangOpts); FullSourceLoc BF(B, SM), EF(E, SM); @@ -1120,6 +1092,14 @@ static std::string buildFixItInsertionLine(FileID FID, return FixItInsertionLine; } +static unsigned getNumDisplayWidth(unsigned N) { + unsigned L = 1u, M = 10u; + while (M <= N && ++L != std::numeric_limits::digits10 + 1) + M *= 10u; + + return L; +} + /// Emit a code snippet and caret line. /// /// This routine emits a single line's code snippet and caret line.. @@ -1145,9 +1125,7 @@ void TextDiagnostic::emitSnippetAndCaret( (LastLevel != DiagnosticsEngine::Note || Level == LastLevel)) return; - // Decompose the location into a FID/Offset pair. - std::pair LocInfo = Loc.getDecomposedLoc(); - FileID FID = LocInfo.first; + FileID FID = Loc.getFileID(); const SourceManager &SM = Loc.getManager(); // Get information about the buffer it points into. @@ -1155,6 +1133,8 @@ void TextDiagnostic::emitSnippetAndCaret( StringRef BufData = Loc.getBufferData(&Invalid); if (Invalid) return; + const char *BufStart = BufData.data(); + const char *BufEnd = BufStart + BufData.size(); unsigned CaretLineNo = Loc.getLineNumber(); unsigned CaretColNo = Loc.getColumnNumber(); @@ -1172,10 +1152,22 @@ void TextDiagnostic::emitSnippetAndCaret( Lines = maybeAddRange(Lines, *OptionalRange, MaxLines); } - for (unsigned LineNo = Lines.first; LineNo != Lines.second + 1; ++LineNo) { - const char *BufStart = BufData.data(); - const char *BufEnd = BufStart + BufData.size(); - + // Our line numbers look like: + // " [number] | " + // Where [number] is MaxLineNoDisplayWidth columns + // and the full thing is therefore MaxLineNoDisplayWidth + 4 columns. + unsigned DisplayLineNo = Loc.getPresumedLoc().getLine(); + unsigned MaxLineNoDisplayWidth = + DiagOpts->ShowLineNumbers + ? std::max(4u, getNumDisplayWidth(DisplayLineNo + MaxLines)) + : 0; + auto indentForLineNumbers = [&] { + if (MaxLineNoDisplayWidth > 0) + OS.indent(MaxLineNoDisplayWidth + 2) << "| "; + }; + + for (unsigned LineNo = Lines.first; LineNo != Lines.second + 1; + ++LineNo, ++DisplayLineNo) { // Rewind from the current position to the start of the line. const char *LineStart = BufStart + @@ -1193,32 +1185,26 @@ void TextDiagnostic::emitSnippetAndCaret( if (size_t(LineEnd - LineStart) > MaxLineLengthToPrint) return; - // Trim trailing null-bytes. - StringRef Line(LineStart, LineEnd - LineStart); - while (!Line.empty() && Line.back() == '\0' && - (LineNo != CaretLineNo || Line.size() > CaretColNo)) - Line = Line.drop_back(); - // Copy the line of code into an std::string for ease of manipulation. - std::string SourceLine(Line.begin(), Line.end()); + std::string SourceLine(LineStart, LineEnd); + // Remove trailing null bytes. + while (!SourceLine.empty() && SourceLine.back() == '\0' && + (LineNo != CaretLineNo || SourceLine.size() > CaretColNo)) + SourceLine.pop_back(); // Build the byte to column map. const SourceColumnMap sourceColMap(SourceLine, DiagOpts->TabStop); - // Create a line for the caret that is filled with spaces that is the same - // number of columns as the line of source code. - std::string CaretLine(sourceColMap.columns(), ' '); - + std::string CaretLine; // Highlight all of the characters covered by Ranges with ~ characters. for (const auto &I : Ranges) highlightRange(I, LineNo, FID, sourceColMap, CaretLine, SM, LangOpts); // Next, insert the caret itself. if (CaretLineNo == LineNo) { - CaretColNo = sourceColMap.byteToContainingColumn(CaretColNo - 1); - if (CaretLine.size() < CaretColNo + 1) - CaretLine.resize(CaretColNo + 1, ' '); - CaretLine[CaretColNo] = '^'; + size_t Col = sourceColMap.byteToContainingColumn(CaretColNo - 1); + CaretLine.resize(std::max(Col + 1, CaretLine.size()), ' '); + CaretLine[Col] = '^'; } std::string FixItInsertionLine = buildFixItInsertionLine( @@ -1235,19 +1221,16 @@ void TextDiagnostic::emitSnippetAndCaret( // to produce easily machine parsable output. Add a space before the // source line and the caret to make it trivial to tell the main diagnostic // line from what the user is intended to see. - if (DiagOpts->ShowSourceRanges) { + if (DiagOpts->ShowSourceRanges && !SourceLine.empty()) { SourceLine = ' ' + SourceLine; CaretLine = ' ' + CaretLine; } - // Finally, remove any blank spaces from the end of CaretLine. - while (!CaretLine.empty() && CaretLine[CaretLine.size() - 1] == ' ') - CaretLine.erase(CaretLine.end() - 1); - // Emit what we have computed. - emitSnippet(SourceLine); + emitSnippet(SourceLine, MaxLineNoDisplayWidth, DisplayLineNo); if (!CaretLine.empty()) { + indentForLineNumbers(); if (DiagOpts->ShowColors) OS.changeColor(caretColor, true); OS << CaretLine << '\n'; @@ -1256,6 +1239,7 @@ void TextDiagnostic::emitSnippetAndCaret( } if (!FixItInsertionLine.empty()) { + indentForLineNumbers(); if (DiagOpts->ShowColors) // Print fixit line in color OS.changeColor(fixitColor, false); @@ -1271,37 +1255,37 @@ void TextDiagnostic::emitSnippetAndCaret( emitParseableFixits(Hints, SM); } -void TextDiagnostic::emitSnippet(StringRef line) { - if (line.empty()) - return; - - size_t i = 0; - - std::string to_print; - bool print_reversed = false; - - while (i,bool> res - = printableTextForNextCharacter(line, &i, DiagOpts->TabStop); - bool was_printable = res.second; +void TextDiagnostic::emitSnippet(StringRef SourceLine, + unsigned MaxLineNoDisplayWidth, + unsigned LineNo) { + // Emit line number. + if (MaxLineNoDisplayWidth > 0) { + unsigned LineNoDisplayWidth = getNumDisplayWidth(LineNo); + OS.indent(MaxLineNoDisplayWidth - LineNoDisplayWidth + 1) + << LineNo << " | "; + } - if (DiagOpts->ShowColors && was_printable == print_reversed) { - if (print_reversed) - OS.reverseColor(); - OS << to_print; - to_print.clear(); - if (DiagOpts->ShowColors) - OS.resetColor(); + // Print the source line one character at a time. + bool PrintReversed = false; + size_t I = 0; + while (I < SourceLine.size()) { + auto [Str, WasPrintable] = + printableTextForNextCharacter(SourceLine, &I, DiagOpts->TabStop); + + // Toggle inverted colors on or off for this character. + if (DiagOpts->ShowColors) { + if (WasPrintable == PrintReversed) { + PrintReversed = !PrintReversed; + if (PrintReversed) + OS.reverseColor(); + else + OS.resetColor(); + } } - - print_reversed = !was_printable; - to_print += res.first.str(); + OS << Str; } - if (print_reversed && DiagOpts->ShowColors) - OS.reverseColor(); - OS << to_print; - if (print_reversed && DiagOpts->ShowColors) + if (DiagOpts->ShowColors) OS.resetColor(); OS << '\n'; diff --git a/clang/lib/Frontend/VerifyDiagnosticConsumer.cpp b/clang/lib/Frontend/VerifyDiagnosticConsumer.cpp index 378f7ddd0159f..d57b27e9e36fc 100644 --- a/clang/lib/Frontend/VerifyDiagnosticConsumer.cpp +++ b/clang/lib/Frontend/VerifyDiagnosticConsumer.cpp @@ -737,12 +737,12 @@ void VerifyDiagnosticConsumer::HandleDiagnostic( Loc = SrcManager->getExpansionLoc(Loc); FileID FID = SrcManager->getFileID(Loc); - const FileEntry *FE = SrcManager->getFileEntryForID(FID); + auto FE = SrcManager->getFileEntryRefForID(FID); if (FE && CurrentPreprocessor && SrcManager->isLoadedFileID(FID)) { // If the file is a modules header file it shall not be parsed // for expected-* directives. HeaderSearch &HS = CurrentPreprocessor->getHeaderSearchInfo(); - if (HS.findModuleForHeader(FE)) + if (HS.findModuleForHeader(*FE)) PS = IsUnparsedNoDirectives; } diff --git a/clang/lib/Headers/CMakeLists.txt b/clang/lib/Headers/CMakeLists.txt index d41443f0b285c..f2ee2e036deb9 100644 --- a/clang/lib/Headers/CMakeLists.txt +++ b/clang/lib/Headers/CMakeLists.txt @@ -267,6 +267,9 @@ set(cuda_wrapper_files cuda_wrappers/cmath cuda_wrappers/complex cuda_wrappers/new +) + +set(cuda_wrapper_bits_files cuda_wrappers/bits/shared_ptr_base.h ) @@ -295,7 +298,8 @@ set(openmp_wrapper_files openmp_wrappers/new ) -set(output_dir ${LLVM_LIBRARY_OUTPUT_INTDIR}/clang/${CLANG_VERSION_MAJOR}/include) +include(GetClangResourceDir) +get_clang_resource_dir(output_dir PREFIX ${LLVM_LIBRARY_OUTPUT_INTDIR}/.. SUBDIR include) set(out_files) set(generated_files) @@ -328,7 +332,8 @@ endfunction(clang_generate_header) # Copy header files from the source directory to the build directory -foreach( f ${files} ${cuda_wrapper_files} ${ppc_wrapper_files} ${openmp_wrapper_files} ${hlsl_files}) +foreach( f ${files} ${cuda_wrapper_files} ${cuda_wrapper_bits_files} + ${ppc_wrapper_files} ${openmp_wrapper_files} ${hlsl_files}) copy_header_to_output_dir(${CMAKE_CURRENT_SOURCE_DIR} ${f}) endforeach( f ) @@ -432,7 +437,7 @@ add_header_target("arm-common-resource-headers" "${arm_common_files};${arm_commo # Architecture/platform specific targets add_header_target("arm-resource-headers" "${arm_only_files};${arm_only_generated_files}") add_header_target("aarch64-resource-headers" "${aarch64_only_files};${aarch64_only_generated_files}") -add_header_target("cuda-resource-headers" "${cuda_files};${cuda_wrapper_files}") +add_header_target("cuda-resource-headers" "${cuda_files};${cuda_wrapper_files};${cuda_wrapper_bits_files}") add_header_target("hexagon-resource-headers" "${hexagon_files}") add_header_target("hip-resource-headers" "${hip_files}") add_header_target("loongarch-resource-headers" "${loongarch_files}") @@ -452,7 +457,7 @@ add_header_target("openmp-resource-headers" ${openmp_wrapper_files}) add_header_target("windows-resource-headers" ${windows_only_files}) add_header_target("utility-resource-headers" ${utility_files}) -set(header_install_dir lib${LLVM_LIBDIR_SUFFIX}/clang/${CLANG_VERSION_MAJOR}/include) +get_clang_resource_dir(header_install_dir SUBDIR include) ############################################################# # Install rules for the catch-all clang-resource-headers target @@ -466,6 +471,11 @@ install( DESTINATION ${header_install_dir}/cuda_wrappers COMPONENT clang-resource-headers) +install( + FILES ${cuda_wrapper_bits_files} + DESTINATION ${header_install_dir}/cuda_wrappers/bits + COMPONENT clang-resource-headers) + install( FILES ${ppc_wrapper_files} DESTINATION ${header_install_dir}/ppc_wrappers @@ -508,6 +518,12 @@ install( EXCLUDE_FROM_ALL COMPONENT cuda-resource-headers) +install( + FILES ${cuda_wrapper_bits_files} + DESTINATION ${header_install_dir}/cuda_wrappers/bits + EXCLUDE_FROM_ALL + COMPONENT cuda-resource-headers) + install( FILES ${cuda_files} DESTINATION ${header_install_dir} diff --git a/clang/lib/Headers/avx2intrin.h b/clang/lib/Headers/avx2intrin.h index 1fbc4edafbd7f..5346a0209928e 100644 --- a/clang/lib/Headers/avx2intrin.h +++ b/clang/lib/Headers/avx2intrin.h @@ -41,78 +41,306 @@ _mm256_abs_epi32(__m256i __a) return (__m256i)__builtin_elementwise_abs((__v8si)__a); } +/// Converts the elements of two 256-bit vectors of [16 x i16] to 8-bit +/// integers using signed saturation, and returns the 256-bit result. +/// +/// \code{.operation} +/// FOR i := 0 TO 7 +/// j := i*16 +/// k := i*8 +/// result[7+k:k] := SATURATE8(__a[15+j:j]) +/// result[71+k:64+k] := SATURATE8(__b[15+j:j]) +/// result[135+k:128+k] := SATURATE8(__a[143+j:128+j]) +/// result[199+k:192+k] := SATURATE8(__b[143+j:128+j]) +/// ENDFOR +/// \endcode +/// +/// \headerfile +/// +/// This intrinsic corresponds to the \c VPACKSSWB instruction. +/// +/// \param __a +/// A 256-bit vector of [16 x i16] used to generate result[63:0] and +/// result[191:128]. +/// \param __b +/// A 256-bit vector of [16 x i16] used to generate result[127:64] and +/// result[255:192]. +/// \returns A 256-bit integer vector containing the result. static __inline__ __m256i __DEFAULT_FN_ATTRS256 _mm256_packs_epi16(__m256i __a, __m256i __b) { return (__m256i)__builtin_ia32_packsswb256((__v16hi)__a, (__v16hi)__b); } +/// Converts the elements of two 256-bit vectors of [8 x i32] to 16-bit +/// integers using signed saturation, and returns the resulting 256-bit +/// vector of [16 x i16]. +/// +/// \code{.operation} +/// FOR i := 0 TO 3 +/// j := i*32 +/// k := i*16 +/// result[15+k:k] := SATURATE16(__a[31+j:j]) +/// result[79+k:64+k] := SATURATE16(__b[31+j:j]) +/// result[143+k:128+k] := SATURATE16(__a[159+j:128+j]) +/// result[207+k:192+k] := SATURATE16(__b[159+j:128+j]) +/// ENDFOR +/// \endcode +/// +/// \headerfile +/// +/// This intrinsic corresponds to the \c VPACKSSDW instruction. +/// +/// \param __a +/// A 256-bit vector of [8 x i32] used to generate result[63:0] and +/// result[191:128]. +/// \param __b +/// A 256-bit vector of [8 x i32] used to generate result[127:64] and +/// result[255:192]. +/// \returns A 256-bit vector of [16 x i16] containing the result. static __inline__ __m256i __DEFAULT_FN_ATTRS256 _mm256_packs_epi32(__m256i __a, __m256i __b) { return (__m256i)__builtin_ia32_packssdw256((__v8si)__a, (__v8si)__b); } +/// Converts elements from two 256-bit vectors of [16 x i16] to 8-bit integers +/// using unsigned saturation, and returns the 256-bit result. +/// +/// \code{.operation} +/// FOR i := 0 TO 7 +/// j := i*16 +/// k := i*8 +/// result[7+k:k] := SATURATE8U(__a[15+j:j]) +/// result[71+k:64+k] := SATURATE8U(__b[15+j:j]) +/// result[135+k:128+k] := SATURATE8U(__a[143+j:128+j]) +/// result[199+k:192+k] := SATURATE8U(__b[143+j:128+j]) +/// ENDFOR +/// \endcode +/// +/// \headerfile +/// +/// This intrinsic corresponds to the \c VPACKUSWB instruction. +/// +/// \param __a +/// A 256-bit vector of [16 x i16] used to generate result[63:0] and +/// result[191:128]. +/// \param __b +/// A 256-bit vector of [16 x i16] used to generate result[127:64] and +/// result[255:192]. +/// \returns A 256-bit integer vector containing the result. static __inline__ __m256i __DEFAULT_FN_ATTRS256 _mm256_packus_epi16(__m256i __a, __m256i __b) { return (__m256i)__builtin_ia32_packuswb256((__v16hi)__a, (__v16hi)__b); } +/// Converts elements from two 256-bit vectors of [8 x i32] to 16-bit integers +/// using unsigned saturation, and returns the resulting 256-bit vector of +/// [16 x i16]. +/// +/// \code{.operation} +/// FOR i := 0 TO 3 +/// j := i*32 +/// k := i*16 +/// result[15+k:k] := SATURATE16U(__V1[31+j:j]) +/// result[79+k:64+k] := SATURATE16U(__V2[31+j:j]) +/// result[143+k:128+k] := SATURATE16U(__V1[159+j:128+j]) +/// result[207+k:192+k] := SATURATE16U(__V2[159+j:128+j]) +/// ENDFOR +/// \endcode +/// +/// \headerfile +/// +/// This intrinsic corresponds to the \c VPACKUSDW instruction. +/// +/// \param __V1 +/// A 256-bit vector of [8 x i32] used to generate result[63:0] and +/// result[191:128]. +/// \param __V2 +/// A 256-bit vector of [8 x i32] used to generate result[127:64] and +/// result[255:192]. +/// \returns A 256-bit vector of [16 x i16] containing the result. static __inline__ __m256i __DEFAULT_FN_ATTRS256 _mm256_packus_epi32(__m256i __V1, __m256i __V2) { return (__m256i) __builtin_ia32_packusdw256((__v8si)__V1, (__v8si)__V2); } +/// Adds 8-bit integers from corresponding bytes of two 256-bit integer +/// vectors and returns the lower 8 bits of each sum in the corresponding +/// byte of the 256-bit integer vector result (overflow is ignored). +/// +/// \headerfile +/// +/// This intrinsic corresponds to the \c VPADDB instruction. +/// +/// \param __a +/// A 256-bit integer vector containing one of the source operands. +/// \param __b +/// A 256-bit integer vector containing one of the source operands. +/// \returns A 256-bit integer vector containing the sums. static __inline__ __m256i __DEFAULT_FN_ATTRS256 _mm256_add_epi8(__m256i __a, __m256i __b) { return (__m256i)((__v32qu)__a + (__v32qu)__b); } +/// Adds 16-bit integers from corresponding elements of two 256-bit vectors of +/// [16 x i16] and returns the lower 16 bits of each sum in the +/// corresponding element of the [16 x i16] result (overflow is ignored). +/// +/// \headerfile +/// +/// This intrinsic corresponds to the \c VPADDW instruction. +/// +/// \param __a +/// A 256-bit vector of [16 x i16] containing one of the source operands. +/// \param __b +/// A 256-bit vector of [16 x i16] containing one of the source operands. +/// \returns A 256-bit vector of [16 x i16] containing the sums. static __inline__ __m256i __DEFAULT_FN_ATTRS256 _mm256_add_epi16(__m256i __a, __m256i __b) { return (__m256i)((__v16hu)__a + (__v16hu)__b); } +/// Adds 32-bit integers from corresponding elements of two 256-bit vectors of +/// [8 x i32] and returns the lower 32 bits of each sum in the corresponding +/// element of the [8 x i32] result (overflow is ignored). +/// +/// \headerfile +/// +/// This intrinsic corresponds to the \c VPADDD instruction. +/// +/// \param __a +/// A 256-bit vector of [8 x i32] containing one of the source operands. +/// \param __b +/// A 256-bit vector of [8 x i32] containing one of the source operands. +/// \returns A 256-bit vector of [8 x i32] containing the sums. static __inline__ __m256i __DEFAULT_FN_ATTRS256 _mm256_add_epi32(__m256i __a, __m256i __b) { return (__m256i)((__v8su)__a + (__v8su)__b); } +/// Adds 64-bit integers from corresponding elements of two 256-bit vectors of +/// [4 x i64] and returns the lower 64 bits of each sum in the corresponding +/// element of the [4 x i64] result (overflow is ignored). +/// +/// \headerfile +/// +/// This intrinsic corresponds to the \c VPADDQ instruction. +/// +/// \param __a +/// A 256-bit vector of [4 x i64] containing one of the source operands. +/// \param __b +/// A 256-bit vector of [4 x i64] containing one of the source operands. +/// \returns A 256-bit vector of [4 x i64] containing the sums. static __inline__ __m256i __DEFAULT_FN_ATTRS256 _mm256_add_epi64(__m256i __a, __m256i __b) { return (__m256i)((__v4du)__a + (__v4du)__b); } +/// Adds 8-bit integers from corresponding bytes of two 256-bit integer +/// vectors using signed saturation, and returns each sum in the +/// corresponding byte of the 256-bit integer vector result. +/// +/// \headerfile +/// +/// This intrinsic corresponds to the \c VPADDSB instruction. +/// +/// \param __a +/// A 256-bit integer vector containing one of the source operands. +/// \param __b +/// A 256-bit integer vector containing one of the source operands. +/// \returns A 256-bit integer vector containing the sums. static __inline__ __m256i __DEFAULT_FN_ATTRS256 _mm256_adds_epi8(__m256i __a, __m256i __b) { return (__m256i)__builtin_elementwise_add_sat((__v32qs)__a, (__v32qs)__b); } +/// Adds 16-bit integers from corresponding elements of two 256-bit vectors of +/// [16 x i16] using signed saturation, and returns the [16 x i16] result. +/// +/// \headerfile +/// +/// This intrinsic corresponds to the \c VPADDSW instruction. +/// +/// \param __a +/// A 256-bit vector of [16 x i16] containing one of the source operands. +/// \param __b +/// A 256-bit vector of [16 x i16] containing one of the source operands. +/// \returns A 256-bit vector of [16 x i16] containing the sums. static __inline__ __m256i __DEFAULT_FN_ATTRS256 _mm256_adds_epi16(__m256i __a, __m256i __b) { return (__m256i)__builtin_elementwise_add_sat((__v16hi)__a, (__v16hi)__b); } +/// Adds 8-bit integers from corresponding bytes of two 256-bit integer +/// vectors using unsigned saturation, and returns each sum in the +/// corresponding byte of the 256-bit integer vector result. +/// +/// \headerfile +/// +/// This intrinsic corresponds to the \c VPADDUSB instruction. +/// +/// \param __a +/// A 256-bit integer vector containing one of the source operands. +/// \param __b +/// A 256-bit integer vector containing one of the source operands. +/// \returns A 256-bit integer vector containing the sums. static __inline__ __m256i __DEFAULT_FN_ATTRS256 _mm256_adds_epu8(__m256i __a, __m256i __b) { return (__m256i)__builtin_elementwise_add_sat((__v32qu)__a, (__v32qu)__b); } +/// Adds 16-bit integers from corresponding elements of two 256-bit vectors of +/// [16 x i16] using unsigned saturation, and returns the [16 x i16] result. +/// +/// \headerfile +/// +/// This intrinsic corresponds to the \c VPADDUSW instruction. +/// +/// \param __a +/// A 256-bit vector of [16 x i16] containing one of the source operands. +/// \param __b +/// A 256-bit vector of [16 x i16] containing one of the source operands. +/// \returns A 256-bit vector of [16 x i16] containing the sums. static __inline__ __m256i __DEFAULT_FN_ATTRS256 _mm256_adds_epu16(__m256i __a, __m256i __b) { return (__m256i)__builtin_elementwise_add_sat((__v16hu)__a, (__v16hu)__b); } +/// Uses the lower half of the 256-bit vector \a a as the upper half of a +/// temporary 256-bit value, and the lower half of the 256-bit vector \a b +/// as the lower half of the temporary value. Right-shifts the temporary +/// value by \a n bytes, and uses the lower 16 bytes of the shifted value +/// as the lower 16 bytes of the result. Uses the upper halves of \a a and +/// \a b to make another temporary value, right shifts by \a n, and uses +/// the lower 16 bytes of the shifted value as the upper 16 bytes of the +/// result. +/// +/// \headerfile +/// +/// \code +/// __m256i _mm256_alignr_epi8(__m256i a, __m256i b, const int n); +/// \endcode +/// +/// This intrinsic corresponds to the \c VPALIGNR instruction. +/// +/// \param a +/// A 256-bit integer vector containing source values. +/// \param b +/// A 256-bit integer vector containing source values. +/// \param n +/// An immediate value specifying the number of bytes to shift. +/// \returns A 256-bit integer vector containing the result. #define _mm256_alignr_epi8(a, b, n) \ ((__m256i)__builtin_ia32_palignr256((__v32qi)(__m256i)(a), \ (__v32qi)(__m256i)(b), (n))) @@ -141,6 +369,35 @@ _mm256_avg_epu16(__m256i __a, __m256i __b) return (__m256i)__builtin_ia32_pavgw256((__v16hi)__a, (__v16hi)__b); } +/// Merges 8-bit integer values from either of the two 256-bit vectors +/// \a __V1 or \a __V2, as specified by the 256-bit mask \a __M and returns +/// the resulting 256-bit integer vector. +/// +/// \code{.operation} +/// FOR i := 0 TO 31 +/// j := i*8 +/// IF __M[7+i] == 0 +/// result[7+j:j] := __V1[7+j:j] +/// ELSE +/// result[7+j:j] := __V2[7+j:j] +/// FI +/// ENDFOR +/// \endcode +/// +/// \headerfile +/// +/// This intrinsic corresponds to the \c VPBLENDVB instruction. +/// +/// \param __V1 +/// A 256-bit integer vector containing source values. +/// \param __V2 +/// A 256-bit integer vector containing source values. +/// \param __M +/// A 256-bit integer vector, with bit [7] of each byte specifying the +/// source for each corresponding byte of the result. When the mask bit +/// is 0, the byte is copied from \a __V1; otherwise, it is copied from +/// \a __V2. +/// \returns A 256-bit integer vector containing the result. static __inline__ __m256i __DEFAULT_FN_ATTRS256 _mm256_blendv_epi8(__m256i __V1, __m256i __V2, __m256i __M) { @@ -148,6 +405,43 @@ _mm256_blendv_epi8(__m256i __V1, __m256i __V2, __m256i __M) (__v32qi)__M); } +/// Merges 16-bit integer values from either of the two 256-bit vectors +/// \a V1 or \a V2, as specified by the immediate integer operand \a M, +/// and returns the resulting 256-bit vector of [16 x i16]. +/// +/// \code{.operation} +/// FOR i := 0 TO 7 +/// j := i*16 +/// IF M[i] == 0 +/// result[7+j:j] := V1[7+j:j] +/// result[135+j:128+j] := V1[135+j:128+j] +/// ELSE +/// result[7+j:j] := V2[7+j:j] +/// result[135+j:128+j] := V2[135+j:128+j] +/// FI +/// ENDFOR +/// \endcode +/// +/// \headerfile +/// +/// \code +/// __m256i _mm256_blend_epi16(__m256i V1, __m256i V2, const int M); +/// \endcode +/// +/// This intrinsic corresponds to the \c VPBLENDW instruction. +/// +/// \param V1 +/// A 256-bit vector of [16 x i16] containing source values. +/// \param V2 +/// A 256-bit vector of [16 x i16] containing source values. +/// \param M +/// An immediate 8-bit integer operand, with bits [7:0] specifying the +/// source for each element of the result. The position of the mask bit +/// corresponds to the index of a copied value. When a mask bit is 0, the +/// element is copied from \a V1; otherwise, it is copied from \a V2. +/// \a M[0] determines the source for elements 0 and 8, \a M[1] for +/// elements 1 and 9, and so forth. +/// \returns A 256-bit vector of [16 x i16] containing the result. #define _mm256_blend_epi16(V1, V2, M) \ ((__m256i)__builtin_ia32_pblendw256((__v16hi)(__m256i)(V1), \ (__v16hi)(__m256i)(V2), (int)(M))) @@ -202,48 +496,269 @@ _mm256_cmpgt_epi64(__m256i __a, __m256i __b) return (__m256i)((__v4di)__a > (__v4di)__b); } +/// Horizontally adds the adjacent pairs of 16-bit integers from two 256-bit +/// vectors of [16 x i16] and returns the lower 16 bits of each sum in an +/// element of the [16 x i16] result (overflow is ignored). Sums from +/// \a __a are returned in the lower 64 bits of each 128-bit half of the +/// result; sums from \a __b are returned in the upper 64 bits of each +/// 128-bit half of the result. +/// +/// \code{.operation} +/// FOR i := 0 TO 1 +/// j := i*128 +/// result[j+15:j] := __a[j+15:j] + __a[j+31:j+16] +/// result[j+31:j+16] := __a[j+47:j+32] + __a[j+63:j+48] +/// result[j+47:j+32] := __a[j+79:j+64] + __a[j+95:j+80] +/// result[j+63:j+48] := __a[j+111:j+96] + __a[j+127:j+112] +/// result[j+79:j+64] := __b[j+15:j] + __b[j+31:j+16] +/// result[j+95:j+80] := __b[j+47:j+32] + __b[j+63:j+48] +/// result[j+111:j+96] := __b[j+79:j+64] + __b[j+95:j+80] +/// result[j+127:j+112] := __b[j+111:j+96] + __b[j+127:j+112] +/// ENDFOR +/// \endcode +/// +/// \headerfile +/// +/// This intrinsic corresponds to the \c VPHADDW instruction. +/// +/// \param __a +/// A 256-bit vector of [16 x i16] containing one of the source operands. +/// \param __b +/// A 256-bit vector of [16 x i16] containing one of the source operands. +/// \returns A 256-bit vector of [16 x i16] containing the sums. static __inline__ __m256i __DEFAULT_FN_ATTRS256 _mm256_hadd_epi16(__m256i __a, __m256i __b) { return (__m256i)__builtin_ia32_phaddw256((__v16hi)__a, (__v16hi)__b); } +/// Horizontally adds the adjacent pairs of 32-bit integers from two 256-bit +/// vectors of [8 x i32] and returns the lower 32 bits of each sum in an +/// element of the [8 x i32] result (overflow is ignored). Sums from \a __a +/// are returned in the lower 64 bits of each 128-bit half of the result; +/// sums from \a __b are returned in the upper 64 bits of each 128-bit half +/// of the result. +/// +/// \code{.operation} +/// FOR i := 0 TO 1 +/// j := i*128 +/// result[j+31:j] := __a[j+31:j] + __a[j+63:j+32] +/// result[j+63:j+32] := __a[j+95:j+64] + __a[j+127:j+96] +/// result[j+95:j+64] := __b[j+31:j] + __b[j+63:j+32] +/// result[j+127:j+96] := __b[j+95:j+64] + __b[j+127:j+96] +/// ENDFOR +/// \endcode +/// +/// \headerfile +/// +/// This intrinsic corresponds to the \c VPHADDD instruction. +/// +/// \param __a +/// A 256-bit vector of [8 x i32] containing one of the source operands. +/// \param __b +/// A 256-bit vector of [8 x i32] containing one of the source operands. +/// \returns A 256-bit vector of [8 x i32] containing the sums. static __inline__ __m256i __DEFAULT_FN_ATTRS256 _mm256_hadd_epi32(__m256i __a, __m256i __b) { return (__m256i)__builtin_ia32_phaddd256((__v8si)__a, (__v8si)__b); } +/// Horizontally adds the adjacent pairs of 16-bit integers from two 256-bit +/// vectors of [16 x i16] using signed saturation and returns each sum in +/// an element of the [16 x i16] result. Sums from \a __a are returned in +/// the lower 64 bits of each 128-bit half of the result; sums from \a __b +/// are returned in the upper 64 bits of each 128-bit half of the result. +/// +/// \code{.operation} +/// FOR i := 0 TO 1 +/// j := i*128 +/// result[j+15:j] := SATURATE16(__a[j+15:j] + __a[j+31:j+16]) +/// result[j+31:j+16] := SATURATE16(__a[j+47:j+32] + __a[j+63:j+48]) +/// result[j+47:j+32] := SATURATE16(__a[j+79:j+64] + __a[j+95:j+80]) +/// result[j+63:j+48] := SATURATE16(__a[j+111:j+96] + __a[j+127:j+112]) +/// result[j+79:j+64] := SATURATE16(__b[j+15:j] + __b[j+31:j+16]) +/// result[j+95:j+80] := SATURATE16(__b[j+47:j+32] + __b[j+63:j+48]) +/// result[j+111:j+96] := SATURATE16(__b[j+79:j+64] + __b[j+95:j+80]) +/// result[j+127:j+112] := SATURATE16(__b[j+111:j+96] + __b[j+127:j+112]) +/// ENDFOR +/// \endcode +/// +/// \headerfile +/// +/// This intrinsic corresponds to the \c VPHADDSW instruction. +/// +/// \param __a +/// A 256-bit vector of [16 x i16] containing one of the source operands. +/// \param __b +/// A 256-bit vector of [16 x i16] containing one of the source operands. +/// \returns A 256-bit vector of [16 x i16] containing the sums. static __inline__ __m256i __DEFAULT_FN_ATTRS256 _mm256_hadds_epi16(__m256i __a, __m256i __b) { return (__m256i)__builtin_ia32_phaddsw256((__v16hi)__a, (__v16hi)__b); } +/// Horizontally subtracts adjacent pairs of 16-bit integers from two 256-bit +/// vectors of [16 x i16] and returns the lower 16 bits of each difference +/// in an element of the [16 x i16] result (overflow is ignored). +/// Differences from \a __a are returned in the lower 64 bits of each +/// 128-bit half of the result; differences from \a __b are returned in the +/// upper 64 bits of each 128-bit half of the result. +/// +/// \code{.operation} +/// FOR i := 0 TO 1 +/// j := i*128 +/// result[j+15:j] := __a[j+15:j] - __a[j+31:j+16] +/// result[j+31:j+16] := __a[j+47:j+32] - __a[j+63:j+48] +/// result[j+47:j+32] := __a[j+79:j+64] - __a[j+95:j+80] +/// result[j+63:j+48] := __a[j+111:j+96] - __a[j+127:j+112] +/// result[j+79:j+64] := __b[j+15:j] - __b[j+31:j+16] +/// result[j+95:j+80] := __b[j+47:j+32] - __b[j+63:j+48] +/// result[j+111:j+96] := __b[j+79:j+64] - __b[j+95:j+80] +/// result[j+127:j+112] := __b[j+111:j+96] - __b[j+127:j+112] +/// ENDFOR +/// \endcode +/// +/// \headerfile +/// +/// This intrinsic corresponds to the \c VPHSUBW instruction. +/// +/// \param __a +/// A 256-bit vector of [16 x i16] containing one of the source operands. +/// \param __b +/// A 256-bit vector of [16 x i16] containing one of the source operands. +/// \returns A 256-bit vector of [16 x i16] containing the differences. static __inline__ __m256i __DEFAULT_FN_ATTRS256 _mm256_hsub_epi16(__m256i __a, __m256i __b) { return (__m256i)__builtin_ia32_phsubw256((__v16hi)__a, (__v16hi)__b); } +/// Horizontally subtracts adjacent pairs of 32-bit integers from two 256-bit +/// vectors of [8 x i32] and returns the lower 32 bits of each difference in +/// an element of the [8 x i32] result (overflow is ignored). Differences +/// from \a __a are returned in the lower 64 bits of each 128-bit half of +/// the result; differences from \a __b are returned in the upper 64 bits +/// of each 128-bit half of the result. +/// +/// \code{.operation} +/// FOR i := 0 TO 1 +/// j := i*128 +/// result[j+31:j] := __a[j+31:j] - __a[j+63:j+32] +/// result[j+63:j+32] := __a[j+95:j+64] - __a[j+127:j+96] +/// result[j+95:j+64] := __b[j+31:j] - __b[j+63:j+32] +/// result[j+127:j+96] := __b[j+95:j+64] - __b[j+127:j+96] +/// ENDFOR +/// \endcode +/// +/// \headerfile +/// +/// This intrinsic corresponds to the \c VPHSUBD instruction. +/// +/// \param __a +/// A 256-bit vector of [8 x i32] containing one of the source operands. +/// \param __b +/// A 256-bit vector of [8 x i32] containing one of the source operands. +/// \returns A 256-bit vector of [8 x i32] containing the differences. static __inline__ __m256i __DEFAULT_FN_ATTRS256 _mm256_hsub_epi32(__m256i __a, __m256i __b) { return (__m256i)__builtin_ia32_phsubd256((__v8si)__a, (__v8si)__b); } +/// Horizontally subtracts adjacent pairs of 16-bit integers from two 256-bit +/// vectors of [16 x i16] using signed saturation and returns each sum in +/// an element of the [16 x i16] result. Differences from \a __a are +/// returned in the lower 64 bits of each 128-bit half of the result; +/// differences from \a __b are returned in the upper 64 bits of each +/// 128-bit half of the result. +/// +/// \code{.operation} +/// FOR i := 0 TO 1 +/// j := i*128 +/// result[j+15:j] := SATURATE16(__a[j+15:j] - __a[j+31:j+16]) +/// result[j+31:j+16] := SATURATE16(__a[j+47:j+32] - __a[j+63:j+48]) +/// result[j+47:j+32] := SATURATE16(__a[j+79:j+64] - __a[j+95:j+80]) +/// result[j+63:j+48] := SATURATE16(__a[j+111:j+96] - __a[j+127:j+112]) +/// result[j+79:j+64] := SATURATE16(__b[j+15:j] - __b[j+31:j+16]) +/// result[j+95:j+80] := SATURATE16(__b[j+47:j+32] - __b[j+63:j+48]) +/// result[j+111:j+96] := SATURATE16(__b[j+79:j+64] - __b[j+95:j+80]) +/// result[j+127:j+112] := SATURATE16(__b[j+111:j+96] - __b[j+127:j+112]) +/// ENDFOR +/// \endcode +/// +/// \headerfile +/// +/// This intrinsic corresponds to the \c VPHSUBSW instruction. +/// +/// \param __a +/// A 256-bit vector of [16 x i16] containing one of the source operands. +/// \param __b +/// A 256-bit vector of [16 x i16] containing one of the source operands. +/// \returns A 256-bit vector of [16 x i16] containing the differences. static __inline__ __m256i __DEFAULT_FN_ATTRS256 _mm256_hsubs_epi16(__m256i __a, __m256i __b) { return (__m256i)__builtin_ia32_phsubsw256((__v16hi)__a, (__v16hi)__b); } +/// Multiplies each unsigned byte from the 256-bit integer vector in \a __a +/// with the corresponding signed byte from the 256-bit integer vector in +/// \a __b, forming signed 16-bit intermediate products. Adds adjacent +/// pairs of those products using signed saturation to form 16-bit sums +/// returned as elements of the [16 x i16] result. +/// +/// \code{.operation} +/// FOR i := 0 TO 15 +/// j := i*16 +/// temp1 := __a[j+7:j] * __b[j+7:j] +/// temp2 := __a[j+15:j+8] * __b[j+15:j+8] +/// result[j+15:j] := SATURATE16(temp1 + temp2) +/// ENDFOR +/// \endcode +/// +/// \headerfile +/// +/// This intrinsic corresponds to the \c VPMADDUBSW instruction. +/// +/// \param __a +/// A 256-bit vector containing one of the source operands. +/// \param __b +/// A 256-bit vector containing one of the source operands. +/// \returns A 256-bit vector of [16 x i16] containing the result. static __inline__ __m256i __DEFAULT_FN_ATTRS256 _mm256_maddubs_epi16(__m256i __a, __m256i __b) { return (__m256i)__builtin_ia32_pmaddubsw256((__v32qi)__a, (__v32qi)__b); } +/// Multiplies corresponding 16-bit elements of two 256-bit vectors of +/// [16 x i16], forming 32-bit intermediate products, and adds pairs of +/// those products to form 32-bit sums returned as elements of the +/// [8 x i32] result. +/// +/// There is only one wraparound case: when all four of the 16-bit sources +/// are \c 0x8000, the result will be \c 0x80000000. +/// +/// \code{.operation} +/// FOR i := 0 TO 7 +/// j := i*32 +/// temp1 := __a[j+15:j] * __b[j+15:j] +/// temp2 := __a[j+31:j+16] * __b[j+31:j+16] +/// result[j+31:j] := temp1 + temp2 +/// ENDFOR +/// \endcode +/// +/// \headerfile +/// +/// This intrinsic corresponds to the \c VPMADDWD instruction. +/// +/// \param __a +/// A 256-bit vector of [16 x i16] containing one of the source operands. +/// \param __b +/// A 256-bit vector of [16 x i16] containing one of the source operands. +/// \returns A 256-bit vector of [8 x i32] containing the result. static __inline__ __m256i __DEFAULT_FN_ATTRS256 _mm256_madd_epi16(__m256i __a, __m256i __b) { @@ -406,42 +921,155 @@ _mm256_cvtepu32_epi64(__m128i __V) return (__m256i)__builtin_convertvector((__v4su)__V, __v4di); } +/// Multiplies signed 32-bit integers from even-numbered elements of two +/// 256-bit vectors of [8 x i32] and returns the 64-bit products in the +/// [4 x i64] result. +/// +/// \code{.operation} +/// result[63:0] := __a[31:0] * __b[31:0] +/// result[127:64] := __a[95:64] * __b[95:64] +/// result[191:128] := __a[159:128] * __b[159:128] +/// result[255:192] := __a[223:192] * __b[223:192] +/// \endcode +/// +/// \headerfile +/// +/// This intrinsic corresponds to the \c VPMULDQ instruction. +/// +/// \param __a +/// A 256-bit vector of [8 x i32] containing one of the source operands. +/// \param __b +/// A 256-bit vector of [8 x i32] containing one of the source operands. +/// \returns A 256-bit vector of [4 x i64] containing the products. static __inline__ __m256i __DEFAULT_FN_ATTRS256 _mm256_mul_epi32(__m256i __a, __m256i __b) { return (__m256i)__builtin_ia32_pmuldq256((__v8si)__a, (__v8si)__b); } +/// Multiplies signed 16-bit integer elements of two 256-bit vectors of +/// [16 x i16], truncates the 32-bit results to the most significant 18 +/// bits, rounds by adding 1, and returns bits [16:1] of each rounded +/// product in the [16 x i16] result. +/// +/// \code{.operation} +/// FOR i := 0 TO 15 +/// j := i*16 +/// temp := ((__a[j+15:j] * __b[j+15:j]) >> 14) + 1 +/// result[j+15:j] := temp[16:1] +/// \endcode +/// +/// \headerfile +/// +/// This intrinsic corresponds to the \c VPMULHRSW instruction. +/// +/// \param __a +/// A 256-bit vector of [16 x i16] containing one of the source operands. +/// \param __b +/// A 256-bit vector of [16 x i16] containing one of the source operands. +/// \returns A 256-bit vector of [16 x i16] containing the rounded products. static __inline__ __m256i __DEFAULT_FN_ATTRS256 _mm256_mulhrs_epi16(__m256i __a, __m256i __b) { return (__m256i)__builtin_ia32_pmulhrsw256((__v16hi)__a, (__v16hi)__b); } +/// Multiplies unsigned 16-bit integer elements of two 256-bit vectors of +/// [16 x i16], and returns the upper 16 bits of each 32-bit product in the +/// [16 x i16] result. +/// +/// \headerfile +/// +/// This intrinsic corresponds to the \c VPMULHUW instruction. +/// +/// \param __a +/// A 256-bit vector of [16 x i16] containing one of the source operands. +/// \param __b +/// A 256-bit vector of [16 x i16] containing one of the source operands. +/// \returns A 256-bit vector of [16 x i16] containing the products. static __inline__ __m256i __DEFAULT_FN_ATTRS256 _mm256_mulhi_epu16(__m256i __a, __m256i __b) { return (__m256i)__builtin_ia32_pmulhuw256((__v16hi)__a, (__v16hi)__b); } +/// Multiplies signed 16-bit integer elements of two 256-bit vectors of +/// [16 x i16], and returns the upper 16 bits of each 32-bit product in the +/// [16 x i16] result. +/// +/// \headerfile +/// +/// This intrinsic corresponds to the \c VPMULHW instruction. +/// +/// \param __a +/// A 256-bit vector of [16 x i16] containing one of the source operands. +/// \param __b +/// A 256-bit vector of [16 x i16] containing one of the source operands. +/// \returns A 256-bit vector of [16 x i16] containing the products. static __inline__ __m256i __DEFAULT_FN_ATTRS256 _mm256_mulhi_epi16(__m256i __a, __m256i __b) { return (__m256i)__builtin_ia32_pmulhw256((__v16hi)__a, (__v16hi)__b); } +/// Multiplies signed 16-bit integer elements of two 256-bit vectors of +/// [16 x i16], and returns the lower 16 bits of each 32-bit product in the +/// [16 x i16] result. +/// +/// \headerfile +/// +/// This intrinsic corresponds to the \c VPMULLW instruction. +/// +/// \param __a +/// A 256-bit vector of [16 x i16] containing one of the source operands. +/// \param __b +/// A 256-bit vector of [16 x i16] containing one of the source operands. +/// \returns A 256-bit vector of [16 x i16] containing the products. static __inline__ __m256i __DEFAULT_FN_ATTRS256 _mm256_mullo_epi16(__m256i __a, __m256i __b) { return (__m256i)((__v16hu)__a * (__v16hu)__b); } +/// Multiplies signed 32-bit integer elements of two 256-bit vectors of +/// [8 x i32], and returns the lower 32 bits of each 64-bit product in the +/// [8 x i32] result. +/// +/// \headerfile +/// +/// This intrinsic corresponds to the \c VPMULLD instruction. +/// +/// \param __a +/// A 256-bit vector of [8 x i32] containing one of the source operands. +/// \param __b +/// A 256-bit vector of [8 x i32] containing one of the source operands. +/// \returns A 256-bit vector of [8 x i32] containing the products. static __inline__ __m256i __DEFAULT_FN_ATTRS256 _mm256_mullo_epi32 (__m256i __a, __m256i __b) { return (__m256i)((__v8su)__a * (__v8su)__b); } +/// Multiplies unsigned 32-bit integers from even-numered elements of two +/// 256-bit vectors of [8 x i32] and returns the 64-bit products in the +/// [4 x i64] result. +/// +/// \code{.operation} +/// result[63:0] := __a[31:0] * __b[31:0] +/// result[127:64] := __a[95:64] * __b[95:64] +/// result[191:128] := __a[159:128] * __b[159:128] +/// result[255:192] := __a[223:192] * __b[223:192] +/// \endcode +/// +/// \headerfile +/// +/// This intrinsic corresponds to the \c VPMULUDQ instruction. +/// +/// \param __a +/// A 256-bit vector of [8 x i32] containing one of the source operands. +/// \param __b +/// A 256-bit vector of [8 x i32] containing one of the source operands. +/// \returns A 256-bit vector of [4 x i64] containing the products. static __inline__ __m256i __DEFAULT_FN_ATTRS256 _mm256_mul_epu32(__m256i __a, __m256i __b) { @@ -460,18 +1088,148 @@ _mm256_sad_epu8(__m256i __a, __m256i __b) return __builtin_ia32_psadbw256((__v32qi)__a, (__v32qi)__b); } +/// Shuffles 8-bit integers in the 256-bit integer vector \a __a according +/// to control information in the 256-bit integer vector \a __b, and +/// returns the 256-bit result. In effect there are two separate 128-bit +/// shuffles in the lower and upper halves. +/// +/// \code{.operation} +/// FOR i := 0 TO 31 +/// j := i*8 +/// IF __b[j+7] == 1 +/// result[j+7:j] := 0 +/// ELSE +/// k := __b[j+3:j] * 8 +/// IF i > 15 +/// k := k + 128 +/// FI +/// result[j+7:j] := __a[k+7:k] +/// FI +/// ENDFOR +/// \endcode +/// +/// \headerfile +/// +/// This intrinsic corresponds to the \c VPSHUFB instruction. +/// +/// \param __a +/// A 256-bit integer vector containing source values. +/// \param __b +/// A 256-bit integer vector containing control information to determine +/// what goes into the corresponding byte of the result. If bit 7 of the +/// control byte is 1, the result byte is 0; otherwise, bits 3:0 of the +/// control byte specify the index (within the same 128-bit half) of \a __a +/// to copy to the result byte. +/// \returns A 256-bit integer vector containing the result. static __inline__ __m256i __DEFAULT_FN_ATTRS256 _mm256_shuffle_epi8(__m256i __a, __m256i __b) { return (__m256i)__builtin_ia32_pshufb256((__v32qi)__a, (__v32qi)__b); } +/// Shuffles 32-bit integers from the 256-bit vector of [8 x i32] in \a a +/// according to control information in the integer literal \a imm, and +/// returns the 256-bit result. In effect there are two parallel 128-bit +/// shuffles in the lower and upper halves. +/// +/// \code{.operation} +/// FOR i := 0 to 3 +/// j := i*32 +/// k := (imm >> i*2)[1:0] * 32 +/// result[j+31:j] := a[k+31:k] +/// result[128+j+31:128+j] := a[128+k+31:128+k] +/// ENDFOR +/// \endcode +/// +/// \headerfile +/// +/// \code +/// __m256i _mm256_shuffle_epi32(__m256i a, const int imm); +/// \endcode +/// +/// This intrinsic corresponds to the \c VPSHUFB instruction. +/// +/// \param a +/// A 256-bit vector of [8 x i32] containing source values. +/// \param imm +/// An immediate 8-bit value specifying which elements to copy from \a a. +/// \a imm[1:0] specifies the index in \a a for elements 0 and 4 of the +/// result, \a imm[3:2] specifies the index for elements 1 and 5, and so +/// forth. +/// \returns A 256-bit vector of [8 x i32] containing the result. #define _mm256_shuffle_epi32(a, imm) \ ((__m256i)__builtin_ia32_pshufd256((__v8si)(__m256i)(a), (int)(imm))) +/// Shuffles 16-bit integers from the 256-bit vector of [16 x i16] in \a a +/// according to control information in the integer literal \a imm, and +/// returns the 256-bit result. The upper 64 bits of each 128-bit half +/// are shuffled in parallel; the lower 64 bits of each 128-bit half are +/// copied from \a a unchanged. +/// +/// \code{.operation} +/// result[63:0] := a[63:0] +/// result[191:128] := a[191:128] +/// FOR i := 0 TO 3 +/// j := i * 16 + 64 +/// k := (imm >> i*2)[1:0] * 16 + 64 +/// result[j+15:j] := a[k+15:k] +/// result[128+j+15:128+j] := a[128+k+15:128+k] +/// ENDFOR +/// \endcode +/// +/// \headerfile +/// +/// \code +/// __m256i _mm256_shufflehi_epi16(__m256i a, const int imm); +/// \endcode +/// +/// This intrinsic corresponds to the \c VPSHUFHW instruction. +/// +/// \param a +/// A 256-bit vector of [16 x i16] containing source values. +/// \param imm +/// An immediate 8-bit value specifying which elements to copy from \a a. +/// \a imm[1:0] specifies the index in \a a for elements 4 and 8 of the +/// result, \a imm[3:2] specifies the index for elements 5 and 9, and so +/// forth. Indexes are offset by 4 (so 0 means index 4, and so forth). +/// \returns A 256-bit vector of [16 x i16] containing the result. #define _mm256_shufflehi_epi16(a, imm) \ ((__m256i)__builtin_ia32_pshufhw256((__v16hi)(__m256i)(a), (int)(imm))) +/// Shuffles 16-bit integers from the 256-bit vector of [16 x i16] \a a +/// according to control information in the integer literal \a imm, and +/// returns the 256-bit [16 x i16] result. The lower 64 bits of each +/// 128-bit half are shuffled; the upper 64 bits of each 128-bit half are +/// copied from \a a unchanged. +/// +/// \code{.operation} +/// result[127:64] := a[127:64] +/// result[255:192] := a[255:192] +/// FOR i := 0 TO 3 +/// j := i * 16 +/// k := (imm >> i*2)[1:0] * 16 +/// result[j+15:j] := a[k+15:k] +/// result[128+j+15:128+j] := a[128+k+15:128+k] +/// ENDFOR +/// \endcode +/// +/// \headerfile +/// +/// \code +/// __m256i _mm256_shufflelo_epi16(__m256i a, const int imm); +/// \endcode +/// +/// This intrinsic corresponds to the \c VPSHUFLW instruction. +/// +/// \param a +/// A 256-bit vector of [16 x i16] to use as a source of data for the +/// result. +/// \param imm +/// An immediate 8-bit value specifying which elements to copy from \a a. +/// \a imm[1:0] specifies the index in \a a for elements 0 and 8 of the +/// result, \a imm[3:2] specifies the index for elements 1 and 9, and so +/// forth. +/// \returns A 256-bit vector of [16 x i16] containing the result. #define _mm256_shufflelo_epi16(a, imm) \ ((__m256i)__builtin_ia32_pshuflw256((__v16hi)(__m256i)(a), (int)(imm))) @@ -897,96 +1655,477 @@ _mm256_srl_epi64(__m256i __a, __m128i __count) return __builtin_ia32_psrlq256((__v4di)__a, __count); } +/// Subtracts 8-bit integers from corresponding bytes of two 256-bit integer +/// vectors. Returns the lower 8 bits of each difference in the +/// corresponding byte of the 256-bit integer vector result (overflow is +/// ignored). +/// +/// \code{.operation} +/// FOR i := 0 TO 31 +/// j := i*8 +/// result[j+7:j] := __a[j+7:j] - __b[j+7:j] +/// ENDFOR +/// \endcode +/// +/// \headerfile +/// +/// This intrinsic corresponds to the \c VPSUBB instruction. +/// +/// \param __a +/// A 256-bit integer vector containing the minuends. +/// \param __b +/// A 256-bit integer vector containing the subtrahends. +/// \returns A 256-bit integer vector containing the differences. static __inline__ __m256i __DEFAULT_FN_ATTRS256 _mm256_sub_epi8(__m256i __a, __m256i __b) { return (__m256i)((__v32qu)__a - (__v32qu)__b); } +/// Subtracts 16-bit integers from corresponding elements of two 256-bit +/// vectors of [16 x i16]. Returns the lower 16 bits of each difference in +/// the corresponding element of the [16 x i16] result (overflow is +/// ignored). +/// +/// \code{.operation} +/// FOR i := 0 TO 15 +/// j := i*16 +/// result[j+15:j] := __a[j+15:j] - __b[j+15:j] +/// ENDFOR +/// \endcode +/// +/// \headerfile +/// +/// This intrinsic corresponds to the \c VPSUBW instruction. +/// +/// \param __a +/// A 256-bit vector of [16 x i16] containing the minuends. +/// \param __b +/// A 256-bit vector of [16 x i16] containing the subtrahends. +/// \returns A 256-bit vector of [16 x i16] containing the differences. static __inline__ __m256i __DEFAULT_FN_ATTRS256 _mm256_sub_epi16(__m256i __a, __m256i __b) { return (__m256i)((__v16hu)__a - (__v16hu)__b); } +/// Subtracts 32-bit integers from corresponding elements of two 256-bit +/// vectors of [8 x i32]. Returns the lower 32 bits of each difference in +/// the corresponding element of the [8 x i32] result (overflow is ignored). +/// +/// \code{.operation} +/// FOR i := 0 TO 7 +/// j := i*32 +/// result[j+31:j] := __a[j+31:j] - __b[j+31:j] +/// ENDFOR +/// \endcode +/// +/// \headerfile +/// +/// This intrinsic corresponds to the \c VPSUBD instruction. +/// +/// \param __a +/// A 256-bit vector of [8 x i32] containing the minuends. +/// \param __b +/// A 256-bit vector of [8 x i32] containing the subtrahends. +/// \returns A 256-bit vector of [8 x i32] containing the differences. static __inline__ __m256i __DEFAULT_FN_ATTRS256 _mm256_sub_epi32(__m256i __a, __m256i __b) { return (__m256i)((__v8su)__a - (__v8su)__b); } +/// Subtracts 64-bit integers from corresponding elements of two 256-bit +/// vectors of [4 x i64]. Returns the lower 64 bits of each difference in +/// the corresponding element of the [4 x i64] result (overflow is ignored). +/// +/// \code{.operation} +/// FOR i := 0 TO 3 +/// j := i*64 +/// result[j+63:j] := __a[j+63:j] - __b[j+63:j] +/// ENDFOR +/// \endcode +/// +/// \headerfile +/// +/// This intrinsic corresponds to the \c VPSUBQ instruction. +/// +/// \param __a +/// A 256-bit vector of [4 x i64] containing the minuends. +/// \param __b +/// A 256-bit vector of [4 x i64] containing the subtrahends. +/// \returns A 256-bit vector of [4 x i64] containing the differences. static __inline__ __m256i __DEFAULT_FN_ATTRS256 _mm256_sub_epi64(__m256i __a, __m256i __b) { return (__m256i)((__v4du)__a - (__v4du)__b); } +/// Subtracts 8-bit integers from corresponding bytes of two 256-bit integer +/// vectors using signed saturation, and returns each differences in the +/// corresponding byte of the 256-bit integer vector result. +/// +/// \code{.operation} +/// FOR i := 0 TO 31 +/// j := i*8 +/// result[j+7:j] := SATURATE8(__a[j+7:j] - __b[j+7:j]) +/// ENDFOR +/// \endcode +/// +/// \headerfile +/// +/// This intrinsic corresponds to the \c VPSUBSB instruction. +/// +/// \param __a +/// A 256-bit integer vector containing the minuends. +/// \param __b +/// A 256-bit integer vector containing the subtrahends. +/// \returns A 256-bit integer vector containing the differences. static __inline__ __m256i __DEFAULT_FN_ATTRS256 _mm256_subs_epi8(__m256i __a, __m256i __b) { return (__m256i)__builtin_elementwise_sub_sat((__v32qs)__a, (__v32qs)__b); } +/// Subtracts 16-bit integers from corresponding elements of two 256-bit +/// vectors of [16 x i16] using signed saturation, and returns each +/// difference in the corresponding element of the [16 x i16] result. +/// +/// \code{.operation} +/// FOR i := 0 TO 15 +/// j := i*16 +/// result[j+7:j] := SATURATE16(__a[j+7:j] - __b[j+7:j]) +/// ENDFOR +/// \endcode +/// +/// \headerfile +/// +/// This intrinsic corresponds to the \c VPSUBSW instruction. +/// +/// \param __a +/// A 256-bit vector of [16 x i16] containing the minuends. +/// \param __b +/// A 256-bit vector of [16 x i16] containing the subtrahends. +/// \returns A 256-bit vector of [16 x i16] containing the differences. static __inline__ __m256i __DEFAULT_FN_ATTRS256 _mm256_subs_epi16(__m256i __a, __m256i __b) { return (__m256i)__builtin_elementwise_sub_sat((__v16hi)__a, (__v16hi)__b); } +/// Subtracts 8-bit integers from corresponding bytes of two 256-bit integer +/// vectors using unsigned saturation, and returns each difference in the +/// corresponding byte of the 256-bit integer vector result. For each byte, +/// computes result = __a - __b . +/// +/// \code{.operation} +/// FOR i := 0 TO 31 +/// j := i*8 +/// result[j+7:j] := SATURATE8U(__a[j+7:j] - __b[j+7:j]) +/// ENDFOR +/// \endcode +/// +/// \headerfile +/// +/// This intrinsic corresponds to the \c VPSUBUSB instruction. +/// +/// \param __a +/// A 256-bit integer vector containing the minuends. +/// \param __b +/// A 256-bit integer vector containing the subtrahends. +/// \returns A 256-bit integer vector containing the differences. static __inline__ __m256i __DEFAULT_FN_ATTRS256 _mm256_subs_epu8(__m256i __a, __m256i __b) { return (__m256i)__builtin_elementwise_sub_sat((__v32qu)__a, (__v32qu)__b); } +/// Subtracts 16-bit integers from corresponding elements of two 256-bit +/// vectors of [16 x i16] using unsigned saturation, and returns each +/// difference in the corresponding element of the [16 x i16] result. +/// +/// \code{.operation} +/// FOR i := 0 TO 15 +/// j := i*16 +/// result[j+15:j] := SATURATE16U(__a[j+15:j] - __b[j+15:j]) +/// ENDFOR +/// \endcode +/// +/// \headerfile +/// +/// This intrinsic corresponds to the \c VPSUBUSW instruction. +/// +/// \param __a +/// A 256-bit vector of [16 x i16] containing the minuends. +/// \param __b +/// A 256-bit vector of [16 x i16] containing the subtrahends. +/// \returns A 256-bit vector of [16 x i16] containing the differences. static __inline__ __m256i __DEFAULT_FN_ATTRS256 _mm256_subs_epu16(__m256i __a, __m256i __b) { return (__m256i)__builtin_elementwise_sub_sat((__v16hu)__a, (__v16hu)__b); } +/// Unpacks and interleaves 8-bit integers from parts of the 256-bit integer +/// vectors in \a __a and \a __b to form the 256-bit result. Specifically, +/// uses the upper 64 bits of each 128-bit half of \a __a and \a __b as +/// input; other bits in these parameters are ignored. +/// +/// \code{.operation} +/// result[7:0] := __a[71:64] +/// result[15:8] := __b[71:64] +/// result[23:16] := __a[79:72] +/// result[31:24] := __b[79:72] +/// . . . +/// result[127:120] := __b[127:120] +/// result[135:128] := __a[199:192] +/// . . . +/// result[255:248] := __b[255:248] +/// \endcode +/// +/// \headerfile +/// +/// This intrinsic corresponds to the \c VPUNPCKHBW instruction. +/// +/// \param __a +/// A 256-bit integer vector used as the source for the even-numbered bytes +/// of the result. +/// \param __b +/// A 256-bit integer vector used as the source for the odd-numbered bytes +/// of the result. +/// \returns A 256-bit integer vector containing the result. static __inline__ __m256i __DEFAULT_FN_ATTRS256 _mm256_unpackhi_epi8(__m256i __a, __m256i __b) { return (__m256i)__builtin_shufflevector((__v32qi)__a, (__v32qi)__b, 8, 32+8, 9, 32+9, 10, 32+10, 11, 32+11, 12, 32+12, 13, 32+13, 14, 32+14, 15, 32+15, 24, 32+24, 25, 32+25, 26, 32+26, 27, 32+27, 28, 32+28, 29, 32+29, 30, 32+30, 31, 32+31); } +/// Unpacks and interleaves 16-bit integers from parts of the 256-bit vectors +/// of [16 x i16] in \a __a and \a __b to return the resulting 256-bit +/// vector of [16 x i16]. Specifically, uses the upper 64 bits of each +/// 128-bit half of \a __a and \a __b as input; other bits in these +/// parameters are ignored. +/// +/// \code{.operation} +/// result[15:0] := __a[79:64] +/// result[31:16] := __b[79:64] +/// result[47:32] := __a[95:80] +/// result[63:48] := __b[95:80] +/// . . . +/// result[127:112] := __b[127:112] +/// result[143:128] := __a[211:196] +/// . . . +/// result[255:240] := __b[255:240] +/// \endcode +/// +/// \headerfile +/// +/// This intrinsic corresponds to the \c VPUNPCKHWD instruction. +/// +/// \param __a +/// A 256-bit vector of [16 x i16] used as the source for the even-numbered +/// elements of the result. +/// \param __b +/// A 256-bit vector of [16 x i16] used as the source for the odd-numbered +/// elements of the result. +/// \returns A 256-bit vector of [16 x i16] containing the result. static __inline__ __m256i __DEFAULT_FN_ATTRS256 _mm256_unpackhi_epi16(__m256i __a, __m256i __b) { return (__m256i)__builtin_shufflevector((__v16hi)__a, (__v16hi)__b, 4, 16+4, 5, 16+5, 6, 16+6, 7, 16+7, 12, 16+12, 13, 16+13, 14, 16+14, 15, 16+15); } +/// Unpacks and interleaves 32-bit integers from parts of the 256-bit vectors +/// of [8 x i32] in \a __a and \a __b to return the resulting 256-bit vector +/// of [8 x i32]. Specifically, uses the upper 64 bits of each 128-bit half +/// of \a __a and \a __b as input; other bits in these parameters are +/// ignored. +/// +/// \code{.operation} +/// result[31:0] := __a[95:64] +/// result[63:32] := __b[95:64] +/// result[95:64] := __a[127:96] +/// result[127:96] := __b[127:96] +/// result[159:128] := __a[223:192] +/// result[191:160] := __b[223:192] +/// result[223:192] := __a[255:224] +/// result[255:224] := __b[255:224] +/// \endcode +/// +/// \headerfile +/// +/// This intrinsic corresponds to the \c VPUNPCKHDQ instruction. +/// +/// \param __a +/// A 256-bit vector of [8 x i32] used as the source for the even-numbered +/// elements of the result. +/// \param __b +/// A 256-bit vector of [8 x i32] used as the source for the odd-numbered +/// elements of the result. +/// \returns A 256-bit vector of [8 x i32] containing the result. static __inline__ __m256i __DEFAULT_FN_ATTRS256 _mm256_unpackhi_epi32(__m256i __a, __m256i __b) { return (__m256i)__builtin_shufflevector((__v8si)__a, (__v8si)__b, 2, 8+2, 3, 8+3, 6, 8+6, 7, 8+7); } +/// Unpacks and interleaves 64-bit integers from parts of the 256-bit vectors +/// of [4 x i64] in \a __a and \a __b to return the resulting 256-bit vector +/// of [4 x i64]. Specifically, uses the upper 64 bits of each 128-bit half +/// of \a __a and \a __b as input; other bits in these parameters are +/// ignored. +/// +/// \code{.operation} +/// result[63:0] := __a[127:64] +/// result[127:64] := __b[127:64] +/// result[191:128] := __a[255:192] +/// result[255:192] := __b[255:192] +/// \endcode +/// +/// \headerfile +/// +/// This intrinsic corresponds to the \c VPUNPCKHQDQ instruction. +/// +/// \param __a +/// A 256-bit vector of [4 x i64] used as the source for the even-numbered +/// elements of the result. +/// \param __b +/// A 256-bit vector of [4 x i64] used as the source for the odd-numbered +/// elements of the result. +/// \returns A 256-bit vector of [4 x i64] containing the result. static __inline__ __m256i __DEFAULT_FN_ATTRS256 _mm256_unpackhi_epi64(__m256i __a, __m256i __b) { return (__m256i)__builtin_shufflevector((__v4di)__a, (__v4di)__b, 1, 4+1, 3, 4+3); } +/// Unpacks and interleaves 8-bit integers from parts of the 256-bit integer +/// vectors in \a __a and \a __b to form the 256-bit result. Specifically, +/// uses the lower 64 bits of each 128-bit half of \a __a and \a __b as +/// input; other bits in these parameters are ignored. +/// +/// \code{.operation} +/// result[7:0] := __a[7:0] +/// result[15:8] := __b[7:0] +/// result[23:16] := __a[15:8] +/// result[31:24] := __b[15:8] +/// . . . +/// result[127:120] := __b[63:56] +/// result[135:128] := __a[135:128] +/// . . . +/// result[255:248] := __b[191:184] +/// \endcode +/// +/// \headerfile +/// +/// This intrinsic corresponds to the \c VPUNPCKLBW instruction. +/// +/// \param __a +/// A 256-bit integer vector used as the source for the even-numbered bytes +/// of the result. +/// \param __b +/// A 256-bit integer vector used as the source for the odd-numbered bytes +/// of the result. +/// \returns A 256-bit integer vector containing the result. static __inline__ __m256i __DEFAULT_FN_ATTRS256 _mm256_unpacklo_epi8(__m256i __a, __m256i __b) { return (__m256i)__builtin_shufflevector((__v32qi)__a, (__v32qi)__b, 0, 32+0, 1, 32+1, 2, 32+2, 3, 32+3, 4, 32+4, 5, 32+5, 6, 32+6, 7, 32+7, 16, 32+16, 17, 32+17, 18, 32+18, 19, 32+19, 20, 32+20, 21, 32+21, 22, 32+22, 23, 32+23); } +/// Unpacks and interleaves 16-bit integers from parts of the 256-bit vectors +/// of [16 x i16] in \a __a and \a __b to return the resulting 256-bit +/// vector of [16 x i16]. Specifically, uses the lower 64 bits of each +/// 128-bit half of \a __a and \a __b as input; other bits in these +/// parameters are ignored. +/// +/// \code{.operation} +/// result[15:0] := __a[15:0] +/// result[31:16] := __b[15:0] +/// result[47:32] := __a[31:16] +/// result[63:48] := __b[31:16] +/// . . . +/// result[127:112] := __b[63:48] +/// result[143:128] := __a[143:128] +/// . . . +/// result[255:239] := __b[191:176] +/// \endcode +/// +/// \headerfile +/// +/// This intrinsic corresponds to the \c VPUNPCKLWD instruction. +/// +/// \param __a +/// A 256-bit vector of [16 x i16] used as the source for the even-numbered +/// elements of the result. +/// \param __b +/// A 256-bit vector of [16 x i16] used as the source for the odd-numbered +/// elements of the result. +/// \returns A 256-bit vector of [16 x i16] containing the result. static __inline__ __m256i __DEFAULT_FN_ATTRS256 _mm256_unpacklo_epi16(__m256i __a, __m256i __b) { return (__m256i)__builtin_shufflevector((__v16hi)__a, (__v16hi)__b, 0, 16+0, 1, 16+1, 2, 16+2, 3, 16+3, 8, 16+8, 9, 16+9, 10, 16+10, 11, 16+11); } +/// Unpacks and interleaves 32-bit integers from parts of the 256-bit vectors +/// of [8 x i32] in \a __a and \a __b to return the resulting 256-bit vector +/// of [8 x i32]. Specifically, uses the lower 64 bits of each 128-bit half +/// of \a __a and \a __b as input; other bits in these parameters are +/// ignored. +/// +/// \code{.operation} +/// result[31:0] := __a[31:0] +/// result[63:32] := __b[31:0] +/// result[95:64] := __a[63:32] +/// result[127:96] := __b[63:32] +/// result[159:128] := __a[159:128] +/// result[191:160] := __b[159:128] +/// result[223:192] := __a[191:160] +/// result[255:224] := __b[191:190] +/// \endcode +/// +/// \headerfile +/// +/// This intrinsic corresponds to the \c VPUNPCKLDQ instruction. +/// +/// \param __a +/// A 256-bit vector of [8 x i32] used as the source for the even-numbered +/// elements of the result. +/// \param __b +/// A 256-bit vector of [8 x i32] used as the source for the odd-numbered +/// elements of the result. +/// \returns A 256-bit vector of [8 x i32] containing the result. static __inline__ __m256i __DEFAULT_FN_ATTRS256 _mm256_unpacklo_epi32(__m256i __a, __m256i __b) { return (__m256i)__builtin_shufflevector((__v8si)__a, (__v8si)__b, 0, 8+0, 1, 8+1, 4, 8+4, 5, 8+5); } +/// Unpacks and interleaves 64-bit integers from parts of the 256-bit vectors +/// of [4 x i64] in \a __a and \a __b to return the resulting 256-bit vector +/// of [4 x i64]. Specifically, uses the lower 64 bits of each 128-bit half +/// of \a __a and \a __b as input; other bits in these parameters are +/// ignored. +/// +/// \code{.operation} +/// result[63:0] := __a[63:0] +/// result[127:64] := __b[63:0] +/// result[191:128] := __a[191:128] +/// result[255:192] := __b[191:128] +/// \endcode +/// +/// \headerfile +/// +/// This intrinsic corresponds to the \c VPUNPCKLQDQ instruction. +/// +/// \param __a +/// A 256-bit vector of [4 x i64] used as the source for the even-numbered +/// elements of the result. +/// \param __b +/// A 256-bit vector of [4 x i64] used as the source for the odd-numbered +/// elements of the result. +/// \returns A 256-bit vector of [4 x i64] containing the result. static __inline__ __m256i __DEFAULT_FN_ATTRS256 _mm256_unpacklo_epi64(__m256i __a, __m256i __b) { @@ -1006,30 +2145,84 @@ _mm256_stream_load_si256(__m256i const *__V) return (__m256i)__builtin_nontemporal_load((const __v4di_aligned *)__V); } +/// Broadcasts the 32-bit floating-point value from the low element of the +/// 128-bit vector of [4 x float] in \a __X to all elements of the result's +/// 128-bit vector of [4 x float]. +/// +/// \headerfile +/// +/// This intrinsic corresponds to the \c VBROADCASTSS instruction. +/// +/// \param __X +/// A 128-bit vector of [4 x float] whose low element will be broadcast. +/// \returns A 128-bit vector of [4 x float] containing the result. static __inline__ __m128 __DEFAULT_FN_ATTRS128 _mm_broadcastss_ps(__m128 __X) { return (__m128)__builtin_shufflevector((__v4sf)__X, (__v4sf)__X, 0, 0, 0, 0); } +/// Broadcasts the 64-bit floating-point value from the low element of the +/// 128-bit vector of [2 x double] in \a __a to both elements of the +/// result's 128-bit vector of [2 x double]. +/// +/// \headerfile +/// +/// This intrinsic corresponds to the \c MOVDDUP instruction. +/// +/// \param __a +/// A 128-bit vector of [2 x double] whose low element will be broadcast. +/// \returns A 128-bit vector of [2 x double] containing the result. static __inline__ __m128d __DEFAULT_FN_ATTRS128 _mm_broadcastsd_pd(__m128d __a) { return __builtin_shufflevector((__v2df)__a, (__v2df)__a, 0, 0); } +/// Broadcasts the 32-bit floating-point value from the low element of the +/// 128-bit vector of [4 x float] in \a __X to all elements of the +/// result's 256-bit vector of [8 x float]. +/// +/// \headerfile +/// +/// This intrinsic corresponds to the \c VBROADCASTSS instruction. +/// +/// \param __X +/// A 128-bit vector of [4 x float] whose low element will be broadcast. +/// \returns A 256-bit vector of [8 x float] containing the result. static __inline__ __m256 __DEFAULT_FN_ATTRS256 _mm256_broadcastss_ps(__m128 __X) { return (__m256)__builtin_shufflevector((__v4sf)__X, (__v4sf)__X, 0, 0, 0, 0, 0, 0, 0, 0); } +/// Broadcasts the 64-bit floating-point value from the low element of the +/// 128-bit vector of [2 x double] in \a __X to all elements of the +/// result's 256-bit vector of [4 x double]. +/// +/// \headerfile +/// +/// This intrinsic corresponds to the \c VBROADCASTSD instruction. +/// +/// \param __X +/// A 128-bit vector of [2 x double] whose low element will be broadcast. +/// \returns A 256-bit vector of [4 x double] containing the result. static __inline__ __m256d __DEFAULT_FN_ATTRS256 _mm256_broadcastsd_pd(__m128d __X) { return (__m256d)__builtin_shufflevector((__v2df)__X, (__v2df)__X, 0, 0, 0, 0); } +/// Broadcasts the 128-bit integer data from \a __X to both the lower and +/// upper halves of the 256-bit result. +/// +/// \headerfile +/// +/// This intrinsic corresponds to the \c VBROADCASTI128 instruction. +/// +/// \param __X +/// A 128-bit integer vector to be broadcast. +/// \returns A 256-bit integer vector containing the result. static __inline__ __m256i __DEFAULT_FN_ATTRS256 _mm256_broadcastsi128_si256(__m128i __X) { @@ -1038,87 +2231,410 @@ _mm256_broadcastsi128_si256(__m128i __X) #define _mm_broadcastsi128_si256(X) _mm256_broadcastsi128_si256(X) +/// Merges 32-bit integer elements from either of the two 128-bit vectors of +/// [4 x i32] in \a V1 or \a V2 to the result's 128-bit vector of [4 x i32], +/// as specified by the immediate integer operand \a M. +/// +/// \code{.operation} +/// FOR i := 0 TO 3 +/// j := i*32 +/// IF M[i] == 0 +/// result[31+j:j] := V1[31+j:j] +/// ELSE +/// result[31+j:j] := V2[32+j:j] +/// FI +/// ENDFOR +/// \endcode +/// +/// \headerfile +/// +/// \code +/// __m128i _mm_blend_epi32(__m128i V1, __m128i V2, const int M); +/// \endcode +/// +/// This intrinsic corresponds to the \c VPBLENDDD instruction. +/// +/// \param V1 +/// A 128-bit vector of [4 x i32] containing source values. +/// \param V2 +/// A 128-bit vector of [4 x i32] containing source values. +/// \param M +/// An immediate 8-bit integer operand, with bits [3:0] specifying the +/// source for each element of the result. The position of the mask bit +/// corresponds to the index of a copied value. When a mask bit is 0, the +/// element is copied from \a V1; otherwise, it is copied from \a V2. +/// \returns A 128-bit vector of [4 x i32] containing the result. #define _mm_blend_epi32(V1, V2, M) \ ((__m128i)__builtin_ia32_pblendd128((__v4si)(__m128i)(V1), \ (__v4si)(__m128i)(V2), (int)(M))) +/// Merges 32-bit integer elements from either of the two 256-bit vectors of +/// [8 x i32] in \a V1 or \a V2 to return a 256-bit vector of [8 x i32], +/// as specified by the immediate integer operand \a M. +/// +/// \code{.operation} +/// FOR i := 0 TO 7 +/// j := i*32 +/// IF M[i] == 0 +/// result[31+j:j] := V1[31+j:j] +/// ELSE +/// result[31+j:j] := V2[32+j:j] +/// FI +/// ENDFOR +/// \endcode +/// +/// \headerfile +/// +/// \code +/// __m256i _mm256_blend_epi32(__m256i V1, __m256i V2, const int M); +/// \endcode +/// +/// This intrinsic corresponds to the \c VPBLENDDD instruction. +/// +/// \param V1 +/// A 256-bit vector of [8 x i32] containing source values. +/// \param V2 +/// A 256-bit vector of [8 x i32] containing source values. +/// \param M +/// An immediate 8-bit integer operand, with bits [7:0] specifying the +/// source for each element of the result. The position of the mask bit +/// corresponds to the index of a copied value. When a mask bit is 0, the +/// element is copied from \a V1; otherwise, it is is copied from \a V2. +/// \returns A 256-bit vector of [8 x i32] containing the result. #define _mm256_blend_epi32(V1, V2, M) \ ((__m256i)__builtin_ia32_pblendd256((__v8si)(__m256i)(V1), \ (__v8si)(__m256i)(V2), (int)(M))) +/// Broadcasts the low byte from the 128-bit integer vector in \a __X to all +/// bytes of the 256-bit result. +/// +/// \headerfile +/// +/// This intrinsic corresponds to the \c VPBROADCASTB instruction. +/// +/// \param __X +/// A 128-bit integer vector whose low byte will be broadcast. +/// \returns A 256-bit integer vector containing the result. static __inline__ __m256i __DEFAULT_FN_ATTRS256 _mm256_broadcastb_epi8(__m128i __X) { return (__m256i)__builtin_shufflevector((__v16qi)__X, (__v16qi)__X, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0); } +/// Broadcasts the low element from the 128-bit vector of [8 x i16] in \a __X +/// to all elements of the result's 256-bit vector of [16 x i16]. +/// +/// \headerfile +/// +/// This intrinsic corresponds to the \c VPBROADCASTW instruction. +/// +/// \param __X +/// A 128-bit vector of [8 x i16] whose low element will be broadcast. +/// \returns A 256-bit vector of [16 x i16] containing the result. static __inline__ __m256i __DEFAULT_FN_ATTRS256 _mm256_broadcastw_epi16(__m128i __X) { return (__m256i)__builtin_shufflevector((__v8hi)__X, (__v8hi)__X, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0); } +/// Broadcasts the low element from the 128-bit vector of [4 x i32] in \a __X +/// to all elements of the result's 256-bit vector of [8 x i32]. +/// +/// \headerfile +/// +/// This intrinsic corresponds to the \c VPBROADCASTD instruction. +/// +/// \param __X +/// A 128-bit vector of [4 x i32] whose low element will be broadcast. +/// \returns A 256-bit vector of [8 x i32] containing the result. static __inline__ __m256i __DEFAULT_FN_ATTRS256 _mm256_broadcastd_epi32(__m128i __X) { return (__m256i)__builtin_shufflevector((__v4si)__X, (__v4si)__X, 0, 0, 0, 0, 0, 0, 0, 0); } +/// Broadcasts the low element from the 128-bit vector of [2 x i64] in \a __X +/// to all elements of the result's 256-bit vector of [4 x i64]. +/// +/// \headerfile +/// +/// This intrinsic corresponds to the \c VPBROADCASTQ instruction. +/// +/// \param __X +/// A 128-bit vector of [2 x i64] whose low element will be broadcast. +/// \returns A 256-bit vector of [4 x i64] containing the result. static __inline__ __m256i __DEFAULT_FN_ATTRS256 _mm256_broadcastq_epi64(__m128i __X) { return (__m256i)__builtin_shufflevector((__v2di)__X, (__v2di)__X, 0, 0, 0, 0); } +/// Broadcasts the low byte from the 128-bit integer vector in \a __X to all +/// bytes of the 128-bit result. +/// +/// \headerfile +/// +/// This intrinsic corresponds to the \c VPBROADCASTB instruction. +/// +/// \param __X +/// A 128-bit integer vector whose low byte will be broadcast. +/// \returns A 128-bit integer vector containing the result. static __inline__ __m128i __DEFAULT_FN_ATTRS128 _mm_broadcastb_epi8(__m128i __X) { return (__m128i)__builtin_shufflevector((__v16qi)__X, (__v16qi)__X, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0); } +/// Broadcasts the low element from the 128-bit vector of [8 x i16] in +/// \a __X to all elements of the result's 128-bit vector of [8 x i16]. +/// +/// \headerfile +/// +/// This intrinsic corresponds to the \c VPBROADCASTW instruction. +/// +/// \param __X +/// A 128-bit vector of [8 x i16] whose low element will be broadcast. +/// \returns A 128-bit vector of [8 x i16] containing the result. static __inline__ __m128i __DEFAULT_FN_ATTRS128 _mm_broadcastw_epi16(__m128i __X) { return (__m128i)__builtin_shufflevector((__v8hi)__X, (__v8hi)__X, 0, 0, 0, 0, 0, 0, 0, 0); } - +/// Broadcasts the low element from the 128-bit vector of [4 x i32] in \a __X +/// to all elements of the result's vector of [4 x i32]. +/// +/// \headerfile +/// +/// This intrinsic corresponds to the \c VPBROADCASTD instruction. +/// +/// \param __X +/// A 128-bit vector of [4 x i32] whose low element will be broadcast. +/// \returns A 128-bit vector of [4 x i32] containing the result. static __inline__ __m128i __DEFAULT_FN_ATTRS128 _mm_broadcastd_epi32(__m128i __X) { return (__m128i)__builtin_shufflevector((__v4si)__X, (__v4si)__X, 0, 0, 0, 0); } +/// Broadcasts the low element from the 128-bit vector of [2 x i64] in \a __X +/// to both elements of the result's 128-bit vector of [2 x i64]. +/// +/// \headerfile +/// +/// This intrinsic corresponds to the \c VPBROADCASTQ instruction. +/// +/// \param __X +/// A 128-bit vector of [2 x i64] whose low element will be broadcast. +/// \returns A 128-bit vector of [2 x i64] containing the result. static __inline__ __m128i __DEFAULT_FN_ATTRS128 _mm_broadcastq_epi64(__m128i __X) { return (__m128i)__builtin_shufflevector((__v2di)__X, (__v2di)__X, 0, 0); } +/// Sets the result's 256-bit vector of [8 x i32] to copies of elements of the +/// 256-bit vector of [8 x i32] in \a __a as specified by indexes in the +/// elements of the 256-bit vector of [8 x i32] in \a __b. +/// +/// \code{.operation} +/// FOR i := 0 TO 7 +/// j := i*32 +/// k := __b[j+2:j] * 32 +/// result[j+31:j] := __a[k+31:k] +/// ENDFOR +/// \endcode +/// +/// \headerfile +/// +/// This intrinsic corresponds to the \c VPERMD instruction. +/// +/// \param __a +/// A 256-bit vector of [8 x i32] containing the source values. +/// \param __b +/// A 256-bit vector of [8 x i32] containing indexes of values to use from +/// \a __a. +/// \returns A 256-bit vector of [8 x i32] containing the result. static __inline__ __m256i __DEFAULT_FN_ATTRS256 _mm256_permutevar8x32_epi32(__m256i __a, __m256i __b) { return (__m256i)__builtin_ia32_permvarsi256((__v8si)__a, (__v8si)__b); } +/// Sets the result's 256-bit vector of [4 x double] to copies of elements of +/// the 256-bit vector of [4 x double] in \a V as specified by the +/// immediate value \a M. +/// +/// \code{.operation} +/// FOR i := 0 TO 3 +/// j := i*64 +/// k := (M >> i*2)[1:0] * 64 +/// result[j+63:j] := V[k+63:k] +/// ENDFOR +/// \endcode +/// +/// \headerfile +/// +/// \code +/// __m256d _mm256_permute4x64_pd(__m256d V, const int M); +/// \endcode +/// +/// This intrinsic corresponds to the \c VPERMPD instruction. +/// +/// \param V +/// A 256-bit vector of [4 x double] containing the source values. +/// \param M +/// An immediate 8-bit value specifying which elements to copy from \a V. +/// \a M[1:0] specifies the index in \a a for element 0 of the result, +/// \a M[3:2] specifies the index for element 1, and so forth. +/// \returns A 256-bit vector of [4 x double] containing the result. #define _mm256_permute4x64_pd(V, M) \ ((__m256d)__builtin_ia32_permdf256((__v4df)(__m256d)(V), (int)(M))) +/// Sets the result's 256-bit vector of [8 x float] to copies of elements of +/// the 256-bit vector of [8 x float] in \a __a as specified by indexes in +/// the elements of the 256-bit vector of [8 x i32] in \a __b. +/// +/// \code{.operation} +/// FOR i := 0 TO 7 +/// j := i*32 +/// k := __b[j+2:j] * 32 +/// result[j+31:j] := __a[k+31:k] +/// ENDFOR +/// \endcode +/// +/// \headerfile +/// +/// This intrinsic corresponds to the \c VPERMPS instruction. +/// +/// \param __a +/// A 256-bit vector of [8 x float] containing the source values. +/// \param __b +/// A 256-bit vector of [8 x i32] containing indexes of values to use from +/// \a __a. +/// \returns A 256-bit vector of [8 x float] containing the result. static __inline__ __m256 __DEFAULT_FN_ATTRS256 _mm256_permutevar8x32_ps(__m256 __a, __m256i __b) { return (__m256)__builtin_ia32_permvarsf256((__v8sf)__a, (__v8si)__b); } +/// Sets the result's 256-bit vector of [4 x i64] result to copies of elements +/// of the 256-bit vector of [4 x i64] in \a V as specified by the +/// immediate value \a M. +/// +/// \code{.operation} +/// FOR i := 0 TO 3 +/// j := i*64 +/// k := (M >> i*2)[1:0] * 64 +/// result[j+63:j] := V[k+63:k] +/// ENDFOR +/// \endcode +/// +/// \headerfile +/// +/// \code +/// __m256i _mm256_permute4x64_epi64(__m256i V, const int M); +/// \endcode +/// +/// This intrinsic corresponds to the \c VPERMQ instruction. +/// +/// \param V +/// A 256-bit vector of [4 x i64] containing the source values. +/// \param M +/// An immediate 8-bit value specifying which elements to copy from \a V. +/// \a M[1:0] specifies the index in \a a for element 0 of the result, +/// \a M[3:2] specifies the index for element 1, and so forth. +/// \returns A 256-bit vector of [4 x i64] containing the result. #define _mm256_permute4x64_epi64(V, M) \ ((__m256i)__builtin_ia32_permdi256((__v4di)(__m256i)(V), (int)(M))) +/// Sets each half of the 256-bit result either to zero or to one of the +/// four possible 128-bit halves of the 256-bit vectors \a V1 and \a V2, +/// as specified by the immediate value \a M. +/// +/// \code{.operation} +/// FOR i := 0 TO 1 +/// j := i*128 +/// k := M >> (i*4) +/// IF k[3] == 0 +/// CASE (k[1:0]) OF +/// 0: result[127+j:j] := V1[127:0] +/// 1: result[127+j:j] := V1[255:128] +/// 2: result[127+j:j] := V2[127:0] +/// 3: result[127+j:j] := V2[255:128] +/// ESAC +/// ELSE +/// result[127+j:j] := 0 +/// FI +/// ENDFOR +/// \endcode +/// +/// \headerfile +/// +/// \code +/// __m256i _mm256_permute2x128_si256(__m256i V1, __m256i V2, const int M); +/// \endcode +/// +/// This intrinsic corresponds to the \c VPERM2I128 instruction. +/// +/// \param V1 +/// A 256-bit integer vector containing source values. +/// \param V2 +/// A 256-bit integer vector containing source values. +/// \param M +/// An immediate value specifying how to form the result. Bits [3:0] +/// control the lower half of the result, bits [7:4] control the upper half. +/// Within each 4-bit control value, if bit 3 is 1, the result is zero, +/// otherwise bits [1:0] determine the source as follows. \n +/// 0: the lower half of \a V1 \n +/// 1: the upper half of \a V1 \n +/// 2: the lower half of \a V2 \n +/// 3: the upper half of \a V2 +/// \returns A 256-bit integer vector containing the result. #define _mm256_permute2x128_si256(V1, V2, M) \ ((__m256i)__builtin_ia32_permti256((__m256i)(V1), (__m256i)(V2), (int)(M))) +/// Extracts half of the 256-bit vector \a V to the 128-bit result. If bit 0 +/// of the immediate \a M is zero, extracts the lower half of the result; +/// otherwise, extracts the upper half. +/// +/// \headerfile +/// +/// \code +/// __m128i _mm256_extracti128_si256(__m256i V, const int M); +/// \endcode +/// +/// This intrinsic corresponds to the \c VEXTRACTI128 instruction. +/// +/// \param V +/// A 256-bit integer vector containing the source values. +/// \param M +/// An immediate value specifying which half of \a V to extract. +/// \returns A 128-bit integer vector containing the result. #define _mm256_extracti128_si256(V, M) \ ((__m128i)__builtin_ia32_extract128i256((__v4di)(__m256i)(V), (int)(M))) +/// Copies the 256-bit vector \a V1 to the result, then overwrites half of the +/// result with the 128-bit vector \a V2. If bit 0 of the immediate \a M +/// is zero, overwrites the lower half of the result; otherwise, +/// overwrites the upper half. +/// +/// \headerfile +/// +/// \code +/// __m256i _mm256_inserti128_si256(__m256i V1, __m128i V2, const int M); +/// \endcode +/// +/// This intrinsic corresponds to the \c VINSERTI128 instruction. +/// +/// \param V1 +/// A 256-bit integer vector containing a source value. +/// \param V2 +/// A 128-bit integer vector containing a source value. +/// \param M +/// An immediate value specifying where to put \a V2 in the result. +/// \returns A 256-bit integer vector containing the result. #define _mm256_inserti128_si256(V1, V2, M) \ ((__m256i)__builtin_ia32_insert128i256((__v4di)(__m256i)(V1), \ (__v2di)(__m128i)(V2), (int)(M))) diff --git a/clang/lib/Headers/opencl-c-base.h b/clang/lib/Headers/opencl-c-base.h index fad2f9c0272bf..af3deae892c7c 100644 --- a/clang/lib/Headers/opencl-c-base.h +++ b/clang/lib/Headers/opencl-c-base.h @@ -474,6 +474,9 @@ typedef enum memory_order #define CLK_HALF_FLOAT 0x10DD #define CLK_FLOAT 0x10DE #define CLK_UNORM_INT24 0x10DF +#if __OPENCL_C_VERSION__ >= CL_VERSION_3_0 +#define CLK_UNORM_INT_101010_2 0x10E0 +#endif // __OPENCL_C_VERSION__ >= CL_VERSION_3_0 // Channel order, numbering must be aligned with cl_channel_order in cl.h // diff --git a/clang/lib/Interpreter/Interpreter.cpp b/clang/lib/Interpreter/Interpreter.cpp index 82d4932faba84..4e1045298537b 100644 --- a/clang/lib/Interpreter/Interpreter.cpp +++ b/clang/lib/Interpreter/Interpreter.cpp @@ -768,7 +768,7 @@ static void SetValueDataBasedOnQualType(Value &V, unsigned long long Data) { if (const auto *ET = QT->getAs()) QT = ET->getDecl()->getIntegerType(); - switch (QT->getAs()->getKind()) { + switch (QT->castAs()->getKind()) { default: llvm_unreachable("unknown type kind!"); #define X(type, name) \ diff --git a/clang/lib/Interpreter/Value.cpp b/clang/lib/Interpreter/Value.cpp index fe37eebac5257..6d0eaf1b82e10 100644 --- a/clang/lib/Interpreter/Value.cpp +++ b/clang/lib/Interpreter/Value.cpp @@ -108,7 +108,7 @@ static Value::Kind ConvertQualTypeToKind(const ASTContext &Ctx, QualType QT) { if (!BT || BT->isNullPtrType()) return Value::K_PtrOrObj; - switch (QT->getAs()->getKind()) { + switch (QT->castAs()->getKind()) { default: assert(false && "Type not supported"); return Value::K_Unspecified; diff --git a/clang/lib/Lex/HeaderSearch.cpp b/clang/lib/Lex/HeaderSearch.cpp index d09d3ae12f581..d94fe09274ed6 100644 --- a/clang/lib/Lex/HeaderSearch.cpp +++ b/clang/lib/Lex/HeaderSearch.cpp @@ -311,7 +311,7 @@ Module *HeaderSearch::lookupModule(StringRef ModuleName, StringRef SearchName, // SearchName rather than ModuleName, to permit finding private modules // named FooPrivate in buggy frameworks named Foo. SmallString<128> FrameworkDirName; - FrameworkDirName += Dir.getFrameworkDir()->getName(); + FrameworkDirName += Dir.getFrameworkDirRef()->getName(); llvm::sys::path::append(FrameworkDirName, SearchName + ".framework"); if (auto FrameworkDir = FileMgr.getOptionalDirectoryRef(FrameworkDirName)) { @@ -345,7 +345,7 @@ Module *HeaderSearch::lookupModule(StringRef ModuleName, StringRef SearchName, // Search for a module map in a subdirectory with the same name as the // module. SmallString<128> NestedModuleMapDirName; - NestedModuleMapDirName = Dir.getDir()->getName(); + NestedModuleMapDirName = Dir.getDirRef()->getName(); llvm::sys::path::append(NestedModuleMapDirName, ModuleName); if (loadModuleMapFile(NestedModuleMapDirName, IsSystem, /*IsFramework*/false) == LMM_NewlyLoaded){ @@ -405,11 +405,10 @@ void HeaderSearch::indexInitialHeaderMaps() { /// getName - Return the directory or filename corresponding to this lookup /// object. StringRef DirectoryLookup::getName() const { - // FIXME: Use the name from \c DirectoryEntryRef. if (isNormalDir()) - return getDir()->getName(); + return getDirRef()->getName(); if (isFramework()) - return getFrameworkDir()->getName(); + return getFrameworkDirRef()->getName(); assert(isHeaderMap() && "Unknown DirectoryLookup"); return getHeaderMap()->getFileName(); } @@ -437,8 +436,8 @@ OptionalFileEntryRef HeaderSearch::getFileAndSuggestModule( // If there is a module that corresponds to this header, suggest it. if (!findUsableModuleForHeader( - &File->getFileEntry(), Dir ? Dir : File->getFileEntry().getDir(), - RequestingModule, SuggestedModule, IsSystemHeaderDir)) + *File, Dir ? Dir : File->getFileEntry().getDir(), RequestingModule, + SuggestedModule, IsSystemHeaderDir)) return std::nullopt; return *File; @@ -492,7 +491,7 @@ OptionalFileEntryRef DirectoryLookup::LookupFile( IsInHeaderMap = true; auto FixupSearchPathAndFindUsableModule = - [&](auto File) -> OptionalFileEntryRef { + [&](FileEntryRef File) -> OptionalFileEntryRef { if (SearchPath) { StringRef SearchPathRef(getName()); SearchPath->clear(); @@ -502,9 +501,9 @@ OptionalFileEntryRef DirectoryLookup::LookupFile( RelativePath->clear(); RelativePath->append(Filename.begin(), Filename.end()); } - if (!HS.findUsableModuleForHeader( - &File.getFileEntry(), File.getFileEntry().getDir(), - RequestingModule, SuggestedModule, isSystemHeaderDirectory())) { + if (!HS.findUsableModuleForHeader(File, File.getFileEntry().getDir(), + RequestingModule, SuggestedModule, + isSystemHeaderDirectory())) { return std::nullopt; } return File; @@ -691,7 +690,7 @@ OptionalFileEntryRef DirectoryLookup::DoFrameworkLookup( // If we found the header and are allowed to suggest a module, do so now. if (File && needModuleLookup(RequestingModule, SuggestedModule)) { // Find the framework in which this header occurs. - StringRef FrameworkPath = File->getFileEntry().getDir()->getName(); + StringRef FrameworkPath = File->getDir().getName(); bool FoundFramework = false; do { // Determine whether this directory exists. @@ -714,14 +713,13 @@ OptionalFileEntryRef DirectoryLookup::DoFrameworkLookup( bool IsSystem = getDirCharacteristic() != SrcMgr::C_User; if (FoundFramework) { - if (!HS.findUsableModuleForFrameworkHeader( - &File->getFileEntry(), FrameworkPath, RequestingModule, - SuggestedModule, IsSystem)) + if (!HS.findUsableModuleForFrameworkHeader(*File, FrameworkPath, + RequestingModule, + SuggestedModule, IsSystem)) return std::nullopt; } else { - if (!HS.findUsableModuleForHeader(&File->getFileEntry(), getDir(), - RequestingModule, SuggestedModule, - IsSystem)) + if (!HS.findUsableModuleForHeader(*File, getDir(), RequestingModule, + SuggestedModule, IsSystem)) return std::nullopt; } } @@ -863,7 +861,7 @@ diagnoseFrameworkInclude(DiagnosticsEngine &Diags, SourceLocation IncludeLoc, OptionalFileEntryRef HeaderSearch::LookupFile( StringRef Filename, SourceLocation IncludeLoc, bool isAngled, ConstSearchDirIterator FromDir, ConstSearchDirIterator *CurDirArg, - ArrayRef> Includers, + ArrayRef> Includers, SmallVectorImpl *SearchPath, SmallVectorImpl *RelativePath, Module *RequestingModule, ModuleMap::KnownHeader *SuggestedModule, bool *IsMapped, bool *IsFrameworkFound, bool SkipCache, @@ -918,7 +916,7 @@ OptionalFileEntryRef HeaderSearch::LookupFile( // Concatenate the requested file onto the directory. // FIXME: Portability. Filename concatenation should be in sys::Path. - TmpDir = IncluderAndDir.second->getName(); + TmpDir = IncluderAndDir.second.getName(); TmpDir.push_back('/'); TmpDir.append(Filename.begin(), Filename.end()); @@ -957,7 +955,7 @@ OptionalFileEntryRef HeaderSearch::LookupFile( ToHFI.Framework = Framework; if (SearchPath) { - StringRef SearchPathRef(IncluderAndDir.second->getName()); + StringRef SearchPathRef(IncluderAndDir.second.getName()); SearchPath->clear(); SearchPath->append(SearchPathRef.begin(), SearchPathRef.end()); } @@ -967,7 +965,7 @@ OptionalFileEntryRef HeaderSearch::LookupFile( } if (First) { diagnoseFrameworkInclude(Diags, IncludeLoc, - IncluderAndDir.second->getName(), Filename, + IncluderAndDir.second.getName(), Filename, &FE->getFileEntry()); return FE; } @@ -1122,7 +1120,7 @@ OptionalFileEntryRef HeaderSearch::LookupFile( bool FoundByHeaderMap = !IsMapped ? false : *IsMapped; if (!Includers.empty()) diagnoseFrameworkInclude( - Diags, IncludeLoc, Includers.front().second->getName(), Filename, + Diags, IncludeLoc, Includers.front().second.getName(), Filename, &File->getFileEntry(), isAngled, FoundByHeaderMap); // Remember this location for the next lookup we do. @@ -1280,7 +1278,7 @@ OptionalFileEntryRef HeaderSearch::LookupSubframeworkHeader( getFileInfo(&File->getFileEntry()).DirInfo = DirInfo; FrameworkName.pop_back(); // remove the trailing '/' - if (!findUsableModuleForFrameworkHeader(&File->getFileEntry(), FrameworkName, + if (!findUsableModuleForFrameworkHeader(*File, FrameworkName, RequestingModule, SuggestedModule, /*IsSystem*/ false)) return std::nullopt; @@ -1376,7 +1374,7 @@ HeaderSearch::getExistingFileInfo(const FileEntry *FE, return HFI; } -bool HeaderSearch::isFileMultipleIncludeGuarded(const FileEntry *File) { +bool HeaderSearch::isFileMultipleIncludeGuarded(const FileEntry *File) const { // Check if we've entered this file and found an include guard or #pragma // once. Note that we dor't check for #import, because that's not a property // of the file itself. @@ -1560,7 +1558,7 @@ bool HeaderSearch::hasModuleMap(StringRef FileName, } ModuleMap::KnownHeader -HeaderSearch::findModuleForHeader(const FileEntry *File, bool AllowTextual, +HeaderSearch::findModuleForHeader(FileEntryRef File, bool AllowTextual, bool AllowExcluded) const { if (ExternalSource) { // Make sure the external source has handled header info about this file, @@ -1571,17 +1569,26 @@ HeaderSearch::findModuleForHeader(const FileEntry *File, bool AllowTextual, } ArrayRef -HeaderSearch::findAllModulesForHeader(const FileEntry *File, - bool AllowCreation) const { +HeaderSearch::findAllModulesForHeader(FileEntryRef File) const { if (ExternalSource) { // Make sure the external source has handled header info about this file, // which includes whether the file is part of a module. (void)getExistingFileInfo(File); } - return ModMap.findAllModulesForHeader(File, AllowCreation); + return ModMap.findAllModulesForHeader(File); } -static bool suggestModule(HeaderSearch &HS, const FileEntry *File, +ArrayRef +HeaderSearch::findResolvedModulesForHeader(const FileEntry *File) const { + if (ExternalSource) { + // Make sure the external source has handled header info about this file, + // which includes whether the file is part of a module. + (void)getExistingFileInfo(File); + } + return ModMap.findResolvedModulesForHeader(File); +} + +static bool suggestModule(HeaderSearch &HS, FileEntryRef File, Module *RequestingModule, ModuleMap::KnownHeader *SuggestedModule) { ModuleMap::KnownHeader Module = @@ -1617,18 +1624,18 @@ static bool suggestModule(HeaderSearch &HS, const FileEntry *File, } bool HeaderSearch::findUsableModuleForHeader( - const FileEntry *File, const DirectoryEntry *Root, Module *RequestingModule, + FileEntryRef File, const DirectoryEntry *Root, Module *RequestingModule, ModuleMap::KnownHeader *SuggestedModule, bool IsSystemHeaderDir) { - if (File && needModuleLookup(RequestingModule, SuggestedModule)) { + if (needModuleLookup(RequestingModule, SuggestedModule)) { // If there is a module that corresponds to this header, suggest it. - hasModuleMap(File->getName(), Root, IsSystemHeaderDir); + hasModuleMap(File.getName(), Root, IsSystemHeaderDir); return suggestModule(*this, File, RequestingModule, SuggestedModule); } return true; } bool HeaderSearch::findUsableModuleForFrameworkHeader( - const FileEntry *File, StringRef FrameworkName, Module *RequestingModule, + FileEntryRef File, StringRef FrameworkName, Module *RequestingModule, ModuleMap::KnownHeader *SuggestedModule, bool IsSystemFramework) { // If we're supposed to suggest a module, look for one now. if (needModuleLookup(RequestingModule, SuggestedModule)) { @@ -1654,10 +1661,10 @@ bool HeaderSearch::findUsableModuleForFrameworkHeader( return true; } -static const FileEntry *getPrivateModuleMap(const FileEntry *File, +static const FileEntry *getPrivateModuleMap(FileEntryRef File, FileManager &FileMgr) { - StringRef Filename = llvm::sys::path::filename(File->getName()); - SmallString<128> PrivateFilename(File->getDir()->getName()); + StringRef Filename = llvm::sys::path::filename(File.getName()); + SmallString<128> PrivateFilename(File.getDir().getName()); if (Filename == "module.map") llvm::sys::path::append(PrivateFilename, "module_private.map"); else if (Filename == "module.modulemap") @@ -1669,7 +1676,7 @@ static const FileEntry *getPrivateModuleMap(const FileEntry *File, return nullptr; } -bool HeaderSearch::loadModuleMapFile(const FileEntry *File, bool IsSystem, +bool HeaderSearch::loadModuleMapFile(FileEntryRef File, bool IsSystem, FileID ID, unsigned *Offset, StringRef OriginalModuleMapFile) { // Find the directory for the module. For frameworks, that may require going @@ -1688,9 +1695,7 @@ bool HeaderSearch::loadModuleMapFile(const FileEntry *File, bool IsSystem, Dir = FakeFile.getDir(); } } else { - // TODO: Replace with `Dir = File.getDir()` when `File` is switched to - // `FileEntryRef`. - Dir = FileMgr.getOptionalDirectoryRef(File->getDir()->getName()); + Dir = File.getDir(); } assert(Dir && "parent must exist"); @@ -1719,11 +1724,9 @@ bool HeaderSearch::loadModuleMapFile(const FileEntry *File, bool IsSystem, } HeaderSearch::LoadModuleMapResult -HeaderSearch::loadModuleMapFileImpl(const FileEntry *File, bool IsSystem, +HeaderSearch::loadModuleMapFileImpl(FileEntryRef File, bool IsSystem, DirectoryEntryRef Dir, FileID ID, unsigned *Offset) { - assert(File && "expected FileEntry"); - // Check whether we've already loaded this module map, and mark it as being // loaded in case we recursively try to load it from itself. auto AddResult = LoadedModuleMaps.insert(std::make_pair(File, true)); @@ -1747,23 +1750,23 @@ HeaderSearch::loadModuleMapFileImpl(const FileEntry *File, bool IsSystem, return LMM_NewlyLoaded; } -const FileEntry * +OptionalFileEntryRef HeaderSearch::lookupModuleMapFile(const DirectoryEntry *Dir, bool IsFramework) { if (!HSOpts->ImplicitModuleMaps) - return nullptr; + return std::nullopt; // For frameworks, the preferred spelling is Modules/module.modulemap, but // module.map at the framework root is also accepted. SmallString<128> ModuleMapFileName(Dir->getName()); if (IsFramework) llvm::sys::path::append(ModuleMapFileName, "Modules"); llvm::sys::path::append(ModuleMapFileName, "module.modulemap"); - if (auto F = FileMgr.getFile(ModuleMapFileName)) + if (auto F = FileMgr.getOptionalFileRef(ModuleMapFileName)) return *F; // Continue to allow module.map ModuleMapFileName = Dir->getName(); llvm::sys::path::append(ModuleMapFileName, "module.map"); - if (auto F = FileMgr.getFile(ModuleMapFileName)) + if (auto F = FileMgr.getOptionalFileRef(ModuleMapFileName)) return *F; // For frameworks, allow to have a private module map with a preferred @@ -1772,10 +1775,10 @@ HeaderSearch::lookupModuleMapFile(const DirectoryEntry *Dir, bool IsFramework) { ModuleMapFileName = Dir->getName(); llvm::sys::path::append(ModuleMapFileName, "Modules", "module.private.modulemap"); - if (auto F = FileMgr.getFile(ModuleMapFileName)) + if (auto F = FileMgr.getOptionalFileRef(ModuleMapFileName)) return *F; } - return nullptr; + return std::nullopt; } Module *HeaderSearch::loadFrameworkModule(StringRef Name, DirectoryEntryRef Dir, @@ -1818,9 +1821,10 @@ HeaderSearch::loadModuleMapFile(DirectoryEntryRef Dir, bool IsSystem, if (KnownDir != DirectoryHasModuleMap.end()) return KnownDir->second ? LMM_AlreadyLoaded : LMM_InvalidModuleMap; - if (const FileEntry *ModuleMapFile = lookupModuleMapFile(Dir, IsFramework)) { + if (OptionalFileEntryRef ModuleMapFile = + lookupModuleMapFile(Dir, IsFramework)) { LoadModuleMapResult Result = - loadModuleMapFileImpl(ModuleMapFile, IsSystem, Dir); + loadModuleMapFileImpl(*ModuleMapFile, IsSystem, Dir); // Add Dir explicitly in case ModuleMapFile is in a subdirectory. // E.g. Foo.framework/Modules/module.modulemap // ^Dir ^ModuleMapFile @@ -1843,7 +1847,7 @@ void HeaderSearch::collectAllModules(SmallVectorImpl &Modules) { if (DL.isFramework()) { std::error_code EC; SmallString<128> DirNative; - llvm::sys::path::native(DL.getFrameworkDir()->getName(), DirNative); + llvm::sys::path::native(DL.getFrameworkDirRef()->getName(), DirNative); // Search each of the ".framework" directories to load them as modules. llvm::vfs::FileSystem &FS = FileMgr.getVirtualFileSystem(); @@ -1906,7 +1910,7 @@ void HeaderSearch::loadSubdirectoryModuleMaps(DirectoryLookup &SearchDir) { return; std::error_code EC; - SmallString<128> Dir = SearchDir.getDir()->getName(); + SmallString<128> Dir = SearchDir.getDirRef()->getName(); FileMgr.makeAbsolutePath(Dir); SmallString<128> DirNative; llvm::sys::path::native(Dir, DirNative); @@ -1923,7 +1927,7 @@ void HeaderSearch::loadSubdirectoryModuleMaps(DirectoryLookup &SearchDir) { } std::string HeaderSearch::suggestPathToFileForDiagnostics( - const FileEntry *File, llvm::StringRef MainFile, bool *IsSystem) { + const FileEntry *File, llvm::StringRef MainFile, bool *IsSystem) const { // FIXME: We assume that the path name currently cached in the FileEntry is // the most appropriate one for this analysis (and that it's spelled the // same way as the corresponding header search path). @@ -1933,7 +1937,7 @@ std::string HeaderSearch::suggestPathToFileForDiagnostics( std::string HeaderSearch::suggestPathToFileForDiagnostics( llvm::StringRef File, llvm::StringRef WorkingDir, llvm::StringRef MainFile, - bool *IsSystem) { + bool *IsSystem) const { using namespace llvm::sys; llvm::SmallString<32> FilePath = File; @@ -1989,14 +1993,14 @@ std::string HeaderSearch::suggestPathToFileForDiagnostics( bool BestPrefixIsFramework = false; for (const DirectoryLookup &DL : search_dir_range()) { if (DL.isNormalDir()) { - StringRef Dir = DL.getDir()->getName(); + StringRef Dir = DL.getDirRef()->getName(); if (CheckDir(Dir)) { if (IsSystem) *IsSystem = BestPrefixLength && isSystem(DL.getDirCharacteristic()); BestPrefixIsFramework = false; } } else if (DL.isFramework()) { - StringRef Dir = DL.getFrameworkDir()->getName(); + StringRef Dir = DL.getFrameworkDirRef()->getName(); if (CheckDir(Dir)) { if (IsSystem) *IsSystem = BestPrefixLength && isSystem(DL.getDirCharacteristic()); diff --git a/clang/lib/Lex/InitHeaderSearch.cpp b/clang/lib/Lex/InitHeaderSearch.cpp index 313efb36bcc93..41382d7cb3fc6 100644 --- a/clang/lib/Lex/InitHeaderSearch.cpp +++ b/clang/lib/Lex/InitHeaderSearch.cpp @@ -652,7 +652,7 @@ void clang::ApplyHeaderSearchOptions(HeaderSearch &HS, // Set up the builtin include directory in the module map. SmallString<128> P = StringRef(HSOpts.ResourceDir); llvm::sys::path::append(P, "include"); - if (auto Dir = HS.getFileMgr().getDirectory(P)) + if (auto Dir = HS.getFileMgr().getOptionalDirectoryRef(P)) HS.getModuleMap().setBuiltinIncludeDir(*Dir); } diff --git a/clang/lib/Lex/ModuleMap.cpp b/clang/lib/Lex/ModuleMap.cpp index 0db7ebff29174..c620eb7769742 100644 --- a/clang/lib/Lex/ModuleMap.cpp +++ b/clang/lib/Lex/ModuleMap.cpp @@ -181,7 +181,7 @@ OptionalFileEntryRef ModuleMap::findHeader( Module *M, const Module::UnresolvedHeaderDirective &Header, SmallVectorImpl &RelativePathName, bool &NeedsFramework) { // Search for the header file within the module's home directory. - auto *Directory = M->Directory; + auto Directory = M->Directory; SmallString<128> FullPathName(Directory->getName()); auto GetFile = [&](StringRef Filename) -> OptionalFileEntryRef { @@ -409,29 +409,27 @@ ModuleMap::findKnownHeader(const FileEntry *File) { return Known; } -ModuleMap::KnownHeader -ModuleMap::findHeaderInUmbrellaDirs(const FileEntry *File, - SmallVectorImpl &IntermediateDirs) { +ModuleMap::KnownHeader ModuleMap::findHeaderInUmbrellaDirs( + FileEntryRef File, SmallVectorImpl &IntermediateDirs) { if (UmbrellaDirs.empty()) return {}; - const DirectoryEntry *Dir = File->getDir(); - assert(Dir && "file in no directory"); + OptionalDirectoryEntryRef Dir = File.getDir(); // Note: as an egregious but useful hack we use the real path here, because // frameworks moving from top-level frameworks to embedded frameworks tend // to be symlinked from the top-level location to the embedded location, // and we need to resolve lookups as if we had found the embedded location. - StringRef DirName = SourceMgr.getFileManager().getCanonicalName(Dir); + StringRef DirName = SourceMgr.getFileManager().getCanonicalName(*Dir); // Keep walking up the directory hierarchy, looking for a directory with // an umbrella header. do { - auto KnownDir = UmbrellaDirs.find(Dir); + auto KnownDir = UmbrellaDirs.find(*Dir); if (KnownDir != UmbrellaDirs.end()) return KnownHeader(KnownDir->second, NormalHeader); - IntermediateDirs.push_back(Dir); + IntermediateDirs.push_back(*Dir); // Retrieve our parent path. DirName = llvm::sys::path::parent_path(DirName); @@ -439,10 +437,7 @@ ModuleMap::findHeaderInUmbrellaDirs(const FileEntry *File, break; // Resolve the parent path to a directory entry. - if (auto DirEntry = SourceMgr.getFileManager().getDirectory(DirName)) - Dir = *DirEntry; - else - Dir = nullptr; + Dir = SourceMgr.getFileManager().getOptionalDirectoryRef(DirName); } while (Dir); return {}; } @@ -582,7 +577,7 @@ static bool isBetterKnownHeader(const ModuleMap::KnownHeader &New, return false; } -ModuleMap::KnownHeader ModuleMap::findModuleForHeader(const FileEntry *File, +ModuleMap::KnownHeader ModuleMap::findModuleForHeader(FileEntryRef File, bool AllowTextual, bool AllowExcluded) { auto MakeResult = [&](ModuleMap::KnownHeader R) -> ModuleMap::KnownHeader { @@ -612,10 +607,10 @@ ModuleMap::KnownHeader ModuleMap::findModuleForHeader(const FileEntry *File, } ModuleMap::KnownHeader -ModuleMap::findOrCreateModuleForHeaderInUmbrellaDir(const FileEntry *File) { +ModuleMap::findOrCreateModuleForHeaderInUmbrellaDir(FileEntryRef File) { assert(!Headers.count(File) && "already have a module for this header"); - SmallVector SkippedDirs; + SmallVector SkippedDirs; KnownHeader H = findHeaderInUmbrellaDirs(File, SkippedDirs); if (H) { Module *Result = H.getModule(); @@ -635,11 +630,11 @@ ModuleMap::findOrCreateModuleForHeaderInUmbrellaDir(const FileEntry *File) { // the actual header is located. bool Explicit = UmbrellaModule->InferExplicitSubmodules; - for (const DirectoryEntry *SkippedDir : llvm::reverse(SkippedDirs)) { + for (DirectoryEntryRef SkippedDir : llvm::reverse(SkippedDirs)) { // Find or create the module that corresponds to this directory name. SmallString<32> NameBuf; StringRef Name = sanitizeFilenameAsIdentifier( - llvm::sys::path::stem(SkippedDir->getName()), NameBuf); + llvm::sys::path::stem(SkippedDir.getName()), NameBuf); Result = findOrCreateModule(Name, Result, /*IsFramework=*/false, Explicit).first; InferredModuleAllowedBy[Result] = UmbrellaModuleMap; @@ -657,7 +652,7 @@ ModuleMap::findOrCreateModuleForHeaderInUmbrellaDir(const FileEntry *File) { // Infer a submodule with the same name as this header file. SmallString<32> NameBuf; StringRef Name = sanitizeFilenameAsIdentifier( - llvm::sys::path::stem(File->getName()), NameBuf); + llvm::sys::path::stem(File.getName()), NameBuf); Result = findOrCreateModule(Name, Result, /*IsFramework=*/false, Explicit).first; InferredModuleAllowedBy[Result] = UmbrellaModuleMap; @@ -684,12 +679,12 @@ ModuleMap::findOrCreateModuleForHeaderInUmbrellaDir(const FileEntry *File) { } ArrayRef -ModuleMap::findAllModulesForHeader(const FileEntry *File, bool AllowCreation) { +ModuleMap::findAllModulesForHeader(FileEntryRef File) { HeadersMap::iterator Known = findKnownHeader(File); if (Known != Headers.end()) return Known->second; - if (AllowCreation && findOrCreateModuleForHeaderInUmbrellaDir(File)) + if (findOrCreateModuleForHeaderInUmbrellaDir(File)) return Headers.find(File)->second; return std::nullopt; @@ -972,14 +967,14 @@ static void inferFrameworkLink(Module *Mod) { /*IsFramework=*/true)); } -Module *ModuleMap::inferFrameworkModule(const DirectoryEntry *FrameworkDir, +Module *ModuleMap::inferFrameworkModule(DirectoryEntryRef FrameworkDir, bool IsSystem, Module *Parent) { Attributes Attrs; Attrs.IsSystem = IsSystem; return inferFrameworkModule(FrameworkDir, Attrs, Parent); } -Module *ModuleMap::inferFrameworkModule(const DirectoryEntry *FrameworkDir, +Module *ModuleMap::inferFrameworkModule(DirectoryEntryRef FrameworkDir, Attributes Attrs, Module *Parent) { // Note: as an egregious but useful hack we use the real path here, because // we might be looking at an embedded framework that symlinks out to a @@ -1010,7 +1005,7 @@ Module *ModuleMap::inferFrameworkModule(const DirectoryEntry *FrameworkDir, if (llvm::sys::path::has_parent_path(FrameworkDirName)) { // Figure out the parent path. StringRef Parent = llvm::sys::path::parent_path(FrameworkDirName); - if (auto ParentDir = FileMgr.getDirectory(Parent)) { + if (auto ParentDir = FileMgr.getOptionalDirectoryRef(Parent)) { // Check whether we have already looked into the parent directory // for a module map. llvm::DenseMap::const_iterator @@ -1019,9 +1014,9 @@ Module *ModuleMap::inferFrameworkModule(const DirectoryEntry *FrameworkDir, // We haven't looked here before. Load a module map, if there is // one. bool IsFrameworkDir = Parent.endswith(".framework"); - if (const FileEntry *ModMapFile = - HeaderInfo.lookupModuleMapFile(*ParentDir, IsFrameworkDir)) { - parseModuleMapFile(ModMapFile, Attrs.IsSystem, *ParentDir); + if (OptionalFileEntryRef ModMapFile = + HeaderInfo.lookupModuleMapFile(*ParentDir, IsFrameworkDir)) { + parseModuleMapFile(*ModMapFile, Attrs.IsSystem, *ParentDir); inferred = InferredDirectories.find(*ParentDir); } @@ -1057,7 +1052,7 @@ Module *ModuleMap::inferFrameworkModule(const DirectoryEntry *FrameworkDir, } // Look for an umbrella header. - SmallString<128> UmbrellaName = StringRef(FrameworkDir->getName()); + SmallString<128> UmbrellaName = FrameworkDir.getName(); llvm::sys::path::append(UmbrellaName, "Headers", ModuleName + ".h"); auto UmbrellaHeader = FileMgr.getOptionalFileRef(UmbrellaName); @@ -1103,8 +1098,7 @@ Module *ModuleMap::inferFrameworkModule(const DirectoryEntry *FrameworkDir, // Look for subframeworks. std::error_code EC; - SmallString<128> SubframeworksDirName - = StringRef(FrameworkDir->getName()); + SmallString<128> SubframeworksDirName = FrameworkDir.getName(); llvm::sys::path::append(SubframeworksDirName, "Frameworks"); llvm::sys::path::native(SubframeworksDirName); llvm::vfs::FileSystem &FS = FileMgr.getVirtualFileSystem(); @@ -1115,8 +1109,7 @@ Module *ModuleMap::inferFrameworkModule(const DirectoryEntry *FrameworkDir, if (!StringRef(Dir->path()).endswith(".framework")) continue; - if (auto SubframeworkDir = - FileMgr.getDirectory(Dir->path())) { + if (auto SubframeworkDir = FileMgr.getOptionalDirectoryRef(Dir->path())) { // Note: as an egregious but useful hack, we use the real path here and // check whether it is actually a subdirectory of the parent directory. // This will not be the case if the 'subframework' is actually a symlink @@ -1182,7 +1175,7 @@ void ModuleMap::setUmbrellaHeaderAsWritten( // Notify callbacks that we just added a new header. for (const auto &Cb : Callbacks) - Cb->moduleMapAddUmbrellaHeader(&SourceMgr.getFileManager(), UmbrellaHeader); + Cb->moduleMapAddUmbrellaHeader(UmbrellaHeader); } void ModuleMap::setUmbrellaDirAsWritten( @@ -1291,7 +1284,7 @@ void ModuleMap::addHeader(Module *Mod, Module::Header Header, // Notify callbacks that we just added a new header. for (const auto &Cb : Callbacks) - Cb->moduleMapAddHeader(Header.Entry->getName()); + Cb->moduleMapAddHeader(Header.Entry.getName()); } OptionalFileEntryRef @@ -1520,7 +1513,7 @@ namespace clang { /// The directory that file names in this module map file should /// be resolved relative to. - const DirectoryEntry *Directory; + DirectoryEntryRef Directory; /// Whether this module map is in a system header directory. bool IsSystem; @@ -1586,7 +1579,7 @@ namespace clang { explicit ModuleMapParser(Lexer &L, SourceManager &SourceMgr, const TargetInfo *Target, DiagnosticsEngine &Diags, ModuleMap &Map, const FileEntry *ModuleMapFile, - const DirectoryEntry *Directory, bool IsSystem) + DirectoryEntryRef Directory, bool IsSystem) : L(L), SourceMgr(SourceMgr), Target(Target), Diags(Diags), Map(Map), ModuleMapFile(ModuleMapFile), Directory(Directory), IsSystem(IsSystem) { @@ -2256,16 +2249,16 @@ void ModuleMapParser::parseExternModuleDecl() { StringRef FileNameRef = FileName; SmallString<128> ModuleMapFileName; if (llvm::sys::path::is_relative(FileNameRef)) { - ModuleMapFileName += Directory->getName(); + ModuleMapFileName += Directory.getName(); llvm::sys::path::append(ModuleMapFileName, FileName); FileNameRef = ModuleMapFileName; } - if (auto File = SourceMgr.getFileManager().getFile(FileNameRef)) + if (auto File = SourceMgr.getFileManager().getOptionalFileRef(FileNameRef)) Map.parseModuleMapFile( *File, IsSystem, Map.HeaderInfo.getHeaderSearchOpts().ModuleMapFileHomeIsCwd ? Directory - : (*File)->getDir(), + : File->getDir(), FileID(), nullptr, ExternLoc); } @@ -2520,7 +2513,7 @@ void ModuleMapParser::parseUmbrellaDirDecl(SourceLocation UmbrellaLoc) { Dir = SourceMgr.getFileManager().getOptionalDirectoryRef(DirName); } else { SmallString<128> PathName; - PathName = Directory->getName(); + PathName = Directory.getName(); llvm::sys::path::append(PathName, DirName); Dir = SourceMgr.getFileManager().getOptionalDirectoryRef(PathName); } @@ -2543,7 +2536,7 @@ void ModuleMapParser::parseUmbrellaDirDecl(SourceLocation UmbrellaLoc) { for (llvm::vfs::recursive_directory_iterator I(FS, Dir->getName(), EC), E; I != E && !EC; I.increment(EC)) { if (auto FE = SourceMgr.getFileManager().getOptionalFileRef(I->path())) { - Module::Header Header = {"", std::string(I->path()), FE}; + Module::Header Header = {"", std::string(I->path()), *FE}; Headers.push_back(std::move(Header)); } } @@ -3082,7 +3075,7 @@ bool ModuleMapParser::parseModuleMapFile() { } bool ModuleMap::parseModuleMapFile(const FileEntry *File, bool IsSystem, - const DirectoryEntry *Dir, FileID ID, + DirectoryEntryRef Dir, FileID ID, unsigned *Offset, SourceLocation ExternModuleLoc) { assert(Target && "Missing target information"); diff --git a/clang/lib/Lex/PPDirectives.cpp b/clang/lib/Lex/PPDirectives.cpp index 2066c61748efa..f133a50dd2ab6 100644 --- a/clang/lib/Lex/PPDirectives.cpp +++ b/clang/lib/Lex/PPDirectives.cpp @@ -150,6 +150,30 @@ static bool isFeatureTestMacro(StringRef MacroName) { MacroName); } +static bool isLanguageDefinedBuiltin(const SourceManager &SourceMgr, + const MacroInfo *MI, + const StringRef MacroName) { + // If this is a macro with special handling (like __LINE__) then it's language + // defined. + if (MI->isBuiltinMacro()) + return true; + // Builtin macros are defined in the builtin file + if (!SourceMgr.isWrittenInBuiltinFile(MI->getDefinitionLoc())) + return false; + // C defines macros starting with __STDC, and C++ defines macros starting with + // __STDCPP + if (MacroName.startswith("__STDC")) + return true; + // C++ defines the __cplusplus macro + if (MacroName == "__cplusplus") + return true; + // C++ defines various feature-test macros starting with __cpp + if (MacroName.startswith("__cpp")) + return true; + // Anything else isn't language-defined + return false; +} + static MacroDiag shouldWarnOnMacroDef(Preprocessor &PP, IdentifierInfo *II) { const LangOptions &Lang = PP.getLangOpts(); StringRef Text = II->getName(); @@ -833,10 +857,10 @@ Module *Preprocessor::getModuleForLocation(SourceLocation Loc, // Try to determine the module of the include directive. // FIXME: Look into directly passing the FileEntry from LookupFile instead. FileID IDOfIncl = SourceMgr.getFileID(SourceMgr.getExpansionLoc(Loc)); - if (const FileEntry *EntryOfIncl = SourceMgr.getFileEntryForID(IDOfIncl)) { + if (auto EntryOfIncl = SourceMgr.getFileEntryRefForID(IDOfIncl)) { // The include comes from an included file. return HeaderInfo.getModuleMap() - .findModuleForHeader(EntryOfIncl, AllowTextual) + .findModuleForHeader(*EntryOfIncl, AllowTextual) .getModule(); } } @@ -861,7 +885,7 @@ Preprocessor::getHeaderToIncludeForDiagnostics(SourceLocation IncLoc, auto &SM = getSourceManager(); while (!Loc.isInvalid() && !SM.isInMainFile(Loc)) { auto ID = SM.getFileID(SM.getExpansionLoc(Loc)); - auto *FE = SM.getFileEntryForID(ID); + auto FE = SM.getFileEntryRefForID(ID); if (!FE) break; @@ -871,7 +895,7 @@ Preprocessor::getHeaderToIncludeForDiagnostics(SourceLocation IncLoc, SourceMgr.isInSystemHeader(Loc)); bool InPrivateHeader = false; - for (auto Header : HeaderInfo.findAllModulesForHeader(FE)) { + for (auto Header : HeaderInfo.findAllModulesForHeader(*FE)) { if (!Header.isAccessibleFrom(IncM)) { // It's in a private header; we can't #include it. // FIXME: If there's a public header in some module that re-exports it, @@ -899,7 +923,7 @@ Preprocessor::getHeaderToIncludeForDiagnostics(SourceLocation IncLoc, // If this is an accessible, non-textual header of M's top-level module // that transitively includes the given location and makes the // corresponding module visible, this is the thing to #include. - return FE; + return *FE; } // FIXME: If we're bailing out due to a private header, we shouldn't suggest @@ -910,8 +934,8 @@ Preprocessor::getHeaderToIncludeForDiagnostics(SourceLocation IncLoc, // If the header is includable and has an include guard, assume the // intended way to expose its contents is by #include, not by importing a // module that transitively includes it. - if (getHeaderSearchInfo().isFileMultipleIncludeGuarded(FE)) - return FE; + if (getHeaderSearchInfo().isFileMultipleIncludeGuarded(*FE)) + return *FE; Loc = SM.getIncludeLoc(ID); } @@ -935,12 +959,11 @@ OptionalFileEntryRef Preprocessor::LookupFile( // If the header lookup mechanism may be relative to the current inclusion // stack, record the parent #includes. - SmallVector, 16> - Includers; + SmallVector, 16> Includers; bool BuildSystemModule = false; if (!FromDir && !FromFile) { FileID FID = getCurrentFileLexer()->getFileID(); - const FileEntry *FileEnt = SourceMgr.getFileEntryForID(FID); + OptionalFileEntryRef FileEnt = SourceMgr.getFileEntryRefForID(FID); // If there is no file entry associated with this file, it must be the // predefines buffer or the module includes buffer. Any other file is not @@ -956,13 +979,15 @@ OptionalFileEntryRef Preprocessor::LookupFile( // map file. if (!FileEnt) { if (FID == SourceMgr.getMainFileID() && MainFileDir) { - Includers.push_back(std::make_pair(nullptr, MainFileDir)); + Includers.push_back(std::make_pair(nullptr, *MainFileDir)); BuildSystemModule = getCurrentModule()->IsSystem; - } else if ((FileEnt = - SourceMgr.getFileEntryForID(SourceMgr.getMainFileID()))) - Includers.push_back(std::make_pair(FileEnt, *FileMgr.getDirectory("."))); + } else if ((FileEnt = SourceMgr.getFileEntryRefForID( + SourceMgr.getMainFileID()))) { + auto CWD = FileMgr.getOptionalDirectoryRef("."); + Includers.push_back(std::make_pair(*FileEnt, *CWD)); + } } else { - Includers.push_back(std::make_pair(FileEnt, FileEnt->getDir())); + Includers.push_back(std::make_pair(*FileEnt, FileEnt->getDir())); } // MSVC searches the current include stack from top to bottom for @@ -972,7 +997,7 @@ OptionalFileEntryRef Preprocessor::LookupFile( for (IncludeStackInfo &ISEntry : llvm::reverse(IncludeMacroStack)) { if (IsFileLexer(ISEntry)) if ((FileEnt = ISEntry.ThePPLexer->getFileEntry())) - Includers.push_back(std::make_pair(FileEnt, FileEnt->getDir())); + Includers.push_back(std::make_pair(*FileEnt, FileEnt->getDir())); } } } @@ -3106,9 +3131,7 @@ void Preprocessor::HandleDefineDirective( // Warn if defining "__LINE__" and other builtins, per C99 6.10.8/4 and // C++ [cpp.predefined]p4, but allow it as an extension. - if (OtherMI->isBuiltinMacro() || - (SourceMgr.isWrittenInBuiltinFile(OtherMI->getDefinitionLoc()) && - !isFeatureTestMacro(MacroNameTok.getIdentifierInfo()->getName()))) + if (isLanguageDefinedBuiltin(SourceMgr, OtherMI, II->getName())) Diag(MacroNameTok, diag::ext_pp_redef_builtin_macro); // Macros must be identical. This means all tokens and whitespace // separation must be the same. C99 6.10.3p2. @@ -3189,11 +3212,8 @@ void Preprocessor::HandleUndefDirective() { Diag(MI->getDefinitionLoc(), diag::pp_macro_not_used); // Warn if undefining "__LINE__" and other builtins, per C99 6.10.8/4 and - // C++ [cpp.predefined]p4, but allow it as an extension. Don't warn if this - // is an Objective-C builtin macro though. - if ((MI->isBuiltinMacro() || - SourceMgr.isWrittenInBuiltinFile(MI->getDefinitionLoc())) && - !(getLangOpts().ObjC && isObjCProtectedMacro(II))) + // C++ [cpp.predefined]p4, but allow it as an extension. + if (isLanguageDefinedBuiltin(SourceMgr, MI, II->getName())) Diag(MacroNameTok, diag::ext_pp_undef_builtin_macro); if (MI->isWarnIfUnused()) diff --git a/clang/lib/Lex/PPLexerChange.cpp b/clang/lib/Lex/PPLexerChange.cpp index 4103cfe178b29..ab005381adfaf 100644 --- a/clang/lib/Lex/PPLexerChange.cpp +++ b/clang/lib/Lex/PPLexerChange.cpp @@ -223,18 +223,17 @@ void Preprocessor::EnterTokenStream(const Token *Toks, unsigned NumToks, /// Compute the relative path that names the given file relative to /// the given directory. static void computeRelativePath(FileManager &FM, const DirectoryEntry *Dir, - const FileEntry *File, - SmallString<128> &Result) { + FileEntryRef File, SmallString<128> &Result) { Result.clear(); - StringRef FilePath = File->getDir()->getName(); + StringRef FilePath = File.getDir().getName(); StringRef Path = FilePath; while (!Path.empty()) { if (auto CurDir = FM.getDirectory(Path)) { if (*CurDir == Dir) { Result = FilePath.substr(Path.size()); llvm::sys::path::append(Result, - llvm::sys::path::filename(File->getName())); + llvm::sys::path::filename(File.getName())); return; } } @@ -242,7 +241,7 @@ static void computeRelativePath(FileManager &FM, const DirectoryEntry *Dir, Path = llvm::sys::path::parent_path(Path); } - Result = File->getName(); + Result = File.getName(); } void Preprocessor::PropagateLineStartLeadingSpaceInfo(Token &Result) { @@ -289,9 +288,10 @@ static void collectAllSubModulesWithUmbrellaHeader( } void Preprocessor::diagnoseMissingHeaderInUmbrellaDir(const Module &Mod) { - Module::Header UmbrellaHeader = Mod.getUmbrellaHeaderAsWritten(); - assert(UmbrellaHeader.Entry && "Module must use umbrella header"); - const FileID &File = SourceMgr.translateFile(UmbrellaHeader.Entry); + std::optional UmbrellaHeader = + Mod.getUmbrellaHeaderAsWritten(); + assert(UmbrellaHeader && "Module must use umbrella header"); + const FileID &File = SourceMgr.translateFile(UmbrellaHeader->Entry); SourceLocation ExpectedHeadersLoc = SourceMgr.getLocForEndOfFile(File); if (getDiagnostics().isIgnored(diag::warn_uncovered_module_header, ExpectedHeadersLoc)) @@ -313,7 +313,7 @@ void Preprocessor::diagnoseMissingHeaderInUmbrellaDir(const Module &Mod) { .Default(false)) continue; - if (auto Header = getFileManager().getFile(Entry->path())) + if (auto Header = getFileManager().getOptionalFileRef(Entry->path())) if (!getSourceManager().hasFileInfo(*Header)) { if (!ModMap.isHeaderInUnavailableModule(*Header)) { // Find the relative path that would access this header. diff --git a/clang/lib/Parse/ParseDecl.cpp b/clang/lib/Parse/ParseDecl.cpp index 0e62f0dff980f..da1d17d14c4c8 100644 --- a/clang/lib/Parse/ParseDecl.cpp +++ b/clang/lib/Parse/ParseDecl.cpp @@ -1693,30 +1693,43 @@ bool Parser::DiagnoseProhibitedCXX11Attribute() { void Parser::DiagnoseMisplacedCXX11Attribute(ParsedAttributes &Attrs, SourceLocation CorrectLocation) { assert((Tok.is(tok::l_square) && NextToken().is(tok::l_square)) || - Tok.is(tok::kw_alignas)); + Tok.is(tok::kw_alignas) || Tok.isRegularKeywordAttribute()); // Consume the attributes. + auto Keyword = + Tok.isRegularKeywordAttribute() ? Tok.getIdentifierInfo() : nullptr; SourceLocation Loc = Tok.getLocation(); ParseCXX11Attributes(Attrs); CharSourceRange AttrRange(SourceRange(Loc, Attrs.Range.getEnd()), true); // FIXME: use err_attributes_misplaced - Diag(Loc, diag::err_attributes_not_allowed) - << FixItHint::CreateInsertionFromRange(CorrectLocation, AttrRange) - << FixItHint::CreateRemoval(AttrRange); + (Keyword ? Diag(Loc, diag::err_keyword_not_allowed) << Keyword + : Diag(Loc, diag::err_attributes_not_allowed)) + << FixItHint::CreateInsertionFromRange(CorrectLocation, AttrRange) + << FixItHint::CreateRemoval(AttrRange); } void Parser::DiagnoseProhibitedAttributes( - const SourceRange &Range, const SourceLocation CorrectLocation) { + const ParsedAttributesView &Attrs, const SourceLocation CorrectLocation) { + auto *FirstAttr = Attrs.empty() ? nullptr : &Attrs.front(); if (CorrectLocation.isValid()) { - CharSourceRange AttrRange(Range, true); - Diag(CorrectLocation, diag::err_attributes_misplaced) + CharSourceRange AttrRange(Attrs.Range, true); + (FirstAttr && FirstAttr->isRegularKeywordAttribute() + ? Diag(CorrectLocation, diag::err_keyword_misplaced) << FirstAttr + : Diag(CorrectLocation, diag::err_attributes_misplaced)) << FixItHint::CreateInsertionFromRange(CorrectLocation, AttrRange) << FixItHint::CreateRemoval(AttrRange); - } else - Diag(Range.getBegin(), diag::err_attributes_not_allowed) << Range; + } else { + const SourceRange &Range = Attrs.Range; + (FirstAttr && FirstAttr->isRegularKeywordAttribute() + ? Diag(Range.getBegin(), diag::err_keyword_not_allowed) << FirstAttr + : Diag(Range.getBegin(), diag::err_attributes_not_allowed)) + << Range; + } } -void Parser::ProhibitCXX11Attributes(ParsedAttributes &Attrs, unsigned DiagID, +void Parser::ProhibitCXX11Attributes(ParsedAttributes &Attrs, + unsigned AttrDiagID, + unsigned KeywordDiagID, bool DiagnoseEmptyAttrs, bool WarnOnUnknownAttrs) { @@ -1736,13 +1749,18 @@ void Parser::ProhibitCXX11Attributes(ParsedAttributes &Attrs, unsigned DiagID, // The attribute range starts with [[, but is empty. So this must // be [[]], which we are supposed to diagnose because // DiagnoseEmptyAttrs is true. - Diag(Attrs.Range.getBegin(), DiagID) << Attrs.Range; + Diag(Attrs.Range.getBegin(), AttrDiagID) << Attrs.Range; return; } } } for (const ParsedAttr &AL : Attrs) { + if (AL.isRegularKeywordAttribute()) { + Diag(AL.getLoc(), KeywordDiagID) << AL; + AL.setInvalid(); + continue; + } if (!AL.isCXX11Attribute() && !AL.isC2xAttribute()) continue; if (AL.getKind() == ParsedAttr::UnknownAttribute) { @@ -1750,7 +1768,7 @@ void Parser::ProhibitCXX11Attributes(ParsedAttributes &Attrs, unsigned DiagID, Diag(AL.getLoc(), diag::warn_unknown_attribute_ignored) << AL << AL.getRange(); } else { - Diag(AL.getLoc(), DiagID) << AL; + Diag(AL.getLoc(), AttrDiagID) << AL; AL.setInvalid(); } } @@ -1758,8 +1776,10 @@ void Parser::ProhibitCXX11Attributes(ParsedAttributes &Attrs, unsigned DiagID, void Parser::DiagnoseCXX11AttributeExtension(ParsedAttributes &Attrs) { for (const ParsedAttr &PA : Attrs) { - if (PA.isCXX11Attribute() || PA.isC2xAttribute()) - Diag(PA.getLoc(), diag::ext_cxx11_attr_placement) << PA << PA.getRange(); + if (PA.isCXX11Attribute() || PA.isC2xAttribute() || + PA.isRegularKeywordAttribute()) + Diag(PA.getLoc(), diag::ext_cxx11_attr_placement) + << PA << PA.isRegularKeywordAttribute() << PA.getRange(); } } @@ -1991,11 +2011,11 @@ bool Parser::MightBeDeclarator(DeclaratorContext Context) { return getLangOpts().CPlusPlus11 && isCXX11VirtSpecifier(NextToken()); default: - return false; + return Tok.isRegularKeywordAttribute(); } default: - return false; + return Tok.isRegularKeywordAttribute(); } } @@ -3298,13 +3318,17 @@ void Parser::ParseDeclarationSpecifiers( switch (Tok.getKind()) { default: + if (Tok.isRegularKeywordAttribute()) + goto Attribute; + DoneWithDeclSpec: if (!AttrsLastTime) ProhibitAttributes(attrs); else { // Reject C++11 / C2x attributes that aren't type attributes. for (const ParsedAttr &PA : attrs) { - if (!PA.isCXX11Attribute() && !PA.isC2xAttribute()) + if (!PA.isCXX11Attribute() && !PA.isC2xAttribute() && + !PA.isRegularKeywordAttribute()) continue; if (PA.getKind() == ParsedAttr::UnknownAttribute) // We will warn about the unknown attribute elsewhere (in @@ -3323,7 +3347,8 @@ void Parser::ParseDeclarationSpecifiers( if (PA.isTypeAttr() && PA.getKind() != ParsedAttr::AT_LifetimeBound && PA.getKind() != ParsedAttr::AT_AnyX86NoCfCheck) continue; - Diag(PA.getLoc(), diag::err_attribute_not_type_attr) << PA; + Diag(PA.getLoc(), diag::err_attribute_not_type_attr) + << PA << PA.isRegularKeywordAttribute(); PA.setInvalid(); } @@ -3337,9 +3362,10 @@ void Parser::ParseDeclarationSpecifiers( case tok::l_square: case tok::kw_alignas: - if (!standardAttributesAllowed() || !isCXX11AttributeSpecifier()) + if (!isAllowedCXX11AttributeSpecifier()) goto DoneWithDeclSpec; + Attribute: ProhibitAttributes(attrs); // FIXME: It would be good to recover by accepting the attributes, // but attempting to do that now would cause serious @@ -5015,6 +5041,7 @@ void Parser::ParseEnumSpecifier(SourceLocation StartLoc, DeclSpec &DS, if (IsElaboratedTypeSpecifier && !getLangOpts().MicrosoftExt && !getLangOpts().ObjC) { ProhibitCXX11Attributes(attrs, diag::err_attributes_not_allowed, + diag::err_keyword_not_allowed, /*DiagnoseEmptyAttrs=*/true); if (BaseType.isUsable()) Diag(BaseRange.getBegin(), diag::ext_enum_base_in_type_specifier) @@ -5160,7 +5187,7 @@ void Parser::ParseEnumBody(SourceLocation StartLoc, Decl *EnumDecl) { // If attributes exist after the enumerator, parse them. ParsedAttributes attrs(AttrFactory); MaybeParseGNUAttributes(attrs); - if (standardAttributesAllowed() && isCXX11AttributeSpecifier()) { + if (isAllowedCXX11AttributeSpecifier()) { if (getLangOpts().CPlusPlus) Diag(Tok.getLocation(), getLangOpts().CPlusPlus17 ? diag::warn_cxx14_compat_ns_enum_attribute @@ -5885,8 +5912,8 @@ void Parser::ParseTypeQualifierListOpt( DeclSpec &DS, unsigned AttrReqs, bool AtomicAllowed, bool IdentifierRequired, std::optional> CodeCompletionHandler) { - if (standardAttributesAllowed() && (AttrReqs & AR_CXX11AttributesParsed) && - isCXX11AttributeSpecifier()) { + if ((AttrReqs & AR_CXX11AttributesParsed) && + isAllowedCXX11AttributeSpecifier()) { ParsedAttributes Attrs(AttrFactory); ParseCXX11Attributes(Attrs); DS.takeAttributesFrom(Attrs); @@ -6660,6 +6687,10 @@ void Parser::ParseDirectDeclarator(Declarator &D) { PrototypeScope.Exit(); } else if (Tok.is(tok::l_square)) { ParseBracketDeclarator(D); + } else if (Tok.isRegularKeywordAttribute()) { + // For consistency with attribute parsing. + Diag(Tok, diag::err_keyword_not_allowed) << Tok.getIdentifierInfo(); + ConsumeToken(); } else if (Tok.is(tok::kw_requires) && D.hasGroupingParens()) { // This declarator is declaring a function, but the requires clause is // in the wrong place: @@ -7064,7 +7095,7 @@ void Parser::ParseFunctionDeclarator(Declarator &D, TrailingReturnTypeLoc = Range.getBegin(); EndLoc = Range.getEnd(); } - } else if (standardAttributesAllowed()) { + } else { MaybeParseCXX11Attributes(FnAttrs); } } diff --git a/clang/lib/Parse/ParseDeclCXX.cpp b/clang/lib/Parse/ParseDeclCXX.cpp index 717c014520892..32c928e5031b2 100644 --- a/clang/lib/Parse/ParseDeclCXX.cpp +++ b/clang/lib/Parse/ParseDeclCXX.cpp @@ -635,6 +635,7 @@ bool Parser::ParseUsingDeclarator(DeclaratorContext Context, Tok.is(tok::identifier) && (NextToken().is(tok::semi) || NextToken().is(tok::comma) || NextToken().is(tok::ellipsis) || NextToken().is(tok::l_square) || + NextToken().isRegularKeywordAttribute() || NextToken().is(tok::kw___attribute)) && D.SS.isNotEmpty() && LastII == Tok.getIdentifierInfo() && !D.SS.getScopeRep()->getAsNamespace() && @@ -767,11 +768,15 @@ Parser::DeclGroupPtrTy Parser::ParseUsingDeclaration( // If we had any misplaced attributes from earlier, this is where they // should have been written. if (MisplacedAttrs.Range.isValid()) { - Diag(MisplacedAttrs.Range.getBegin(), diag::err_attributes_not_allowed) + auto *FirstAttr = + MisplacedAttrs.empty() ? nullptr : &MisplacedAttrs.front(); + auto &Range = MisplacedAttrs.Range; + (FirstAttr && FirstAttr->isRegularKeywordAttribute() + ? Diag(Range.getBegin(), diag::err_keyword_not_allowed) << FirstAttr + : Diag(Range.getBegin(), diag::err_attributes_not_allowed)) << FixItHint::CreateInsertionFromRange( - Tok.getLocation(), - CharSourceRange::getTokenRange(MisplacedAttrs.Range)) - << FixItHint::CreateRemoval(MisplacedAttrs.Range); + Tok.getLocation(), CharSourceRange::getTokenRange(Range)) + << FixItHint::CreateRemoval(Range); Attrs.takeAllFrom(MisplacedAttrs); } @@ -1384,6 +1389,8 @@ bool Parser::isValidAfterTypeSpecifier(bool CouldBeBitfield) { // This switch enumerates the valid "follow" set for type-specifiers. switch (Tok.getKind()) { default: + if (Tok.isRegularKeywordAttribute()) + return true; break; case tok::semi: // struct foo {...} ; case tok::star: // struct foo {...} * P; @@ -1841,6 +1848,7 @@ void Parser::ParseClassSpecifier(tok::TokenKind TagTokKind, } else if (isClassCompatibleKeyword() && (NextToken().is(tok::l_square) || NextToken().is(tok::kw_alignas) || + NextToken().isRegularKeywordAttribute() || isCXX11VirtSpecifier(NextToken()) != VirtSpecifiers::VS_None)) { // We can't tell if this is a definition or reference // until we skipped the 'final' and C++11 attribute specifiers. @@ -1862,6 +1870,8 @@ void Parser::ParseClassSpecifier(tok::TokenKind TagTokKind, ConsumeParen(); if (!SkipUntil(tok::r_paren, StopAtSemi)) break; + } else if (Tok.isRegularKeywordAttribute()) { + ConsumeToken(); } else { break; } @@ -1898,7 +1908,11 @@ void Parser::ParseClassSpecifier(tok::TokenKind TagTokKind, // them to the right place. SourceRange AttrRange = Attributes.Range; if (AttrRange.isValid()) { - Diag(AttrRange.getBegin(), diag::err_attributes_not_allowed) + auto *FirstAttr = Attributes.empty() ? nullptr : &Attributes.front(); + auto Loc = AttrRange.getBegin(); + (FirstAttr && FirstAttr->isRegularKeywordAttribute() + ? Diag(Loc, diag::err_keyword_not_allowed) << FirstAttr + : Diag(Loc, diag::err_attributes_not_allowed)) << AttrRange << FixItHint::CreateInsertionFromRange( AttrFixitLoc, CharSourceRange(AttrRange, true)) @@ -1946,6 +1960,7 @@ void Parser::ParseClassSpecifier(tok::TokenKind TagTokKind, TUK == Sema::TUK_Declaration) { // This is an explicit instantiation of a class template. ProhibitCXX11Attributes(attrs, diag::err_attributes_not_allowed, + diag::err_keyword_not_allowed, /*DiagnoseEmptyAttrs=*/true); TagOrTempResult = Actions.ActOnExplicitInstantiation( @@ -1962,6 +1977,7 @@ void Parser::ParseClassSpecifier(tok::TokenKind TagTokKind, (TUK == Sema::TUK_Friend && TemplateInfo.Kind == ParsedTemplateInfo::NonTemplate)) { ProhibitCXX11Attributes(attrs, diag::err_attributes_not_allowed, + diag::err_keyword_not_allowed, /*DiagnoseEmptyAttrs=*/true); TypeResult = Actions.ActOnTagTemplateIdType( TUK, TagType, StartLoc, SS, TemplateId->TemplateKWLoc, @@ -2031,6 +2047,7 @@ void Parser::ParseClassSpecifier(tok::TokenKind TagTokKind, } else if (TUK == Sema::TUK_Friend && TemplateInfo.Kind != ParsedTemplateInfo::NonTemplate) { ProhibitCXX11Attributes(attrs, diag::err_attributes_not_allowed, + diag::err_keyword_not_allowed, /*DiagnoseEmptyAttrs=*/true); TagOrTempResult = Actions.ActOnTemplatedFriendTag( @@ -2041,6 +2058,7 @@ void Parser::ParseClassSpecifier(tok::TokenKind TagTokKind, } else { if (TUK != Sema::TUK_Declaration && TUK != Sema::TUK_Definition) ProhibitCXX11Attributes(attrs, diag::err_attributes_not_allowed, + diag::err_keyword_not_allowed, /* DiagnoseEmptyAttrs=*/true); if (TUK == Sema::TUK_Definition && @@ -3017,12 +3035,14 @@ Parser::ParseCXXClassMemberDeclaration(AccessSpecifier AS, // // Diagnose attributes that appear in a friend member function declarator: // friend int foo [[]] (); - SmallVector Ranges; - DeclaratorInfo.getCXX11AttributeRanges(Ranges); - for (SmallVectorImpl::iterator I = Ranges.begin(), - E = Ranges.end(); - I != E; ++I) - Diag((*I).getBegin(), diag::err_attributes_not_allowed) << *I; + for (const ParsedAttr &AL : DeclaratorInfo.getAttributes()) + if (AL.isCXX11Attribute() || AL.isRegularKeywordAttribute()) { + auto Loc = AL.getRange().getBegin(); + (AL.isRegularKeywordAttribute() + ? Diag(Loc, diag::err_keyword_not_allowed) << AL + : Diag(Loc, diag::err_attributes_not_allowed)) + << AL.getRange(); + } ThisDecl = Actions.ActOnFriendFunctionDecl(getCurScope(), DeclaratorInfo, TemplateParams); @@ -4470,6 +4490,14 @@ void Parser::ParseCXX11AttributeSpecifierInternal(ParsedAttributes &Attrs, return; } + if (Tok.isRegularKeywordAttribute()) { + SourceLocation Loc = Tok.getLocation(); + IdentifierInfo *AttrName = Tok.getIdentifierInfo(); + Attrs.addNew(AttrName, Loc, nullptr, Loc, nullptr, 0, Tok.getKind()); + ConsumeToken(); + return; + } + assert(Tok.is(tok::l_square) && NextToken().is(tok::l_square) && "Not a double square bracket attribute list"); @@ -4589,26 +4617,30 @@ void Parser::ParseCXX11AttributeSpecifierInternal(ParsedAttributes &Attrs, /// attribute-specifier-seq: /// attribute-specifier-seq[opt] attribute-specifier void Parser::ParseCXX11Attributes(ParsedAttributes &Attrs) { - assert(standardAttributesAllowed()); + assert(standardAttributesAllowed() || Tok.isRegularKeywordAttribute()); SourceLocation StartLoc = Tok.getLocation(); SourceLocation EndLoc = StartLoc; do { ParseCXX11AttributeSpecifier(Attrs, &EndLoc); - } while (isCXX11AttributeSpecifier()); + } while (isAllowedCXX11AttributeSpecifier()); Attrs.Range = SourceRange(StartLoc, EndLoc); } void Parser::DiagnoseAndSkipCXX11Attributes() { + auto Keyword = + Tok.isRegularKeywordAttribute() ? Tok.getIdentifierInfo() : nullptr; // Start and end location of an attribute or an attribute list. SourceLocation StartLoc = Tok.getLocation(); SourceLocation EndLoc = SkipCXX11Attributes(); if (EndLoc.isValid()) { SourceRange Range(StartLoc, EndLoc); - Diag(StartLoc, diag::err_attributes_not_allowed) << Range; + (Keyword ? Diag(StartLoc, diag::err_keyword_not_allowed) << Keyword + : Diag(StartLoc, diag::err_attributes_not_allowed)) + << Range; } } @@ -4624,6 +4656,9 @@ SourceLocation Parser::SkipCXX11Attributes() { T.consumeOpen(); T.skipToEnd(); EndLoc = T.getCloseLocation(); + } else if (Tok.isRegularKeywordAttribute()) { + EndLoc = Tok.getLocation(); + ConsumeToken(); } else { assert(Tok.is(tok::kw_alignas) && "not an attribute specifier"); ConsumeToken(); diff --git a/clang/lib/Parse/ParseExprCXX.cpp b/clang/lib/Parse/ParseExprCXX.cpp index 123cf432b0969..037dc923c47eb 100644 --- a/clang/lib/Parse/ParseExprCXX.cpp +++ b/clang/lib/Parse/ParseExprCXX.cpp @@ -1364,7 +1364,8 @@ ExprResult Parser::ParseLambdaExpressionAfterIntroducer( if (isCXX11AttributeSpecifier()) { Diag(Tok, getLangOpts().CPlusPlus23 ? diag::warn_cxx20_compat_decl_attrs_on_lambda - : diag::ext_decl_attrs_on_lambda); + : diag::ext_decl_attrs_on_lambda) + << Tok.getIdentifierInfo() << Tok.isRegularKeywordAttribute(); MaybeParseCXX11Attributes(D); } @@ -1499,6 +1500,7 @@ ExprResult Parser::ParseLambdaExpressionAfterIntroducer( tok::kw___private, tok::kw___global, tok::kw___local, tok::kw___constant, tok::kw___generic, tok::kw_groupshared, tok::kw_requires, tok::kw_noexcept) || + Tok.isRegularKeywordAttribute() || (Tok.is(tok::l_square) && NextToken().is(tok::l_square)); if (HasSpecifiers && !HasParentheses && !getLangOpts().CPlusPlus23) { diff --git a/clang/lib/Parse/ParsePragma.cpp b/clang/lib/Parse/ParsePragma.cpp index 8c3da9a7438e8..79707bc297f43 100644 --- a/clang/lib/Parse/ParsePragma.cpp +++ b/clang/lib/Parse/ParsePragma.cpp @@ -1819,7 +1819,8 @@ void Parser::HandlePragmaAttribute() { ConsumeToken(); }; - if (Tok.is(tok::l_square) && NextToken().is(tok::l_square)) { + if ((Tok.is(tok::l_square) && NextToken().is(tok::l_square)) || + Tok.isRegularKeywordAttribute()) { // Parse the CXX11 style attribute. ParseCXX11AttributeSpecifier(Attrs); } else if (Tok.is(tok::kw___attribute)) { diff --git a/clang/lib/Parse/ParseStmt.cpp b/clang/lib/Parse/ParseStmt.cpp index bde9df0877382..aea810e8cf45c 100644 --- a/clang/lib/Parse/ParseStmt.cpp +++ b/clang/lib/Parse/ParseStmt.cpp @@ -335,7 +335,12 @@ StmtResult Parser::ParseStatementOrDeclarationAfterAttributes( case tok::kw_asm: { for (const ParsedAttr &AL : CXX11Attrs) - Diag(AL.getRange().getBegin(), diag::warn_attribute_ignored) << AL; + // Could be relaxed if asm-related regular keyword attributes are + // added later. + (AL.isRegularKeywordAttribute() + ? Diag(AL.getRange().getBegin(), diag::err_keyword_not_allowed) + : Diag(AL.getRange().getBegin(), diag::warn_attribute_ignored)) + << AL; // Prevent these from being interpreted as statement attributes later on. CXX11Attrs.clear(); ProhibitAttributes(GNUAttrs); diff --git a/clang/lib/Parse/ParseTemplate.cpp b/clang/lib/Parse/ParseTemplate.cpp index 79f4ab683281e..d2e8a81ad521a 100644 --- a/clang/lib/Parse/ParseTemplate.cpp +++ b/clang/lib/Parse/ParseTemplate.cpp @@ -210,7 +210,15 @@ Decl *Parser::ParseSingleDeclarationAfterTemplate( } ParsedAttributes prefixAttrs(AttrFactory); - MaybeParseCXX11Attributes(prefixAttrs); + ParsedAttributes DeclSpecAttrs(AttrFactory); + + // GNU attributes are applied to the declaration specification while the + // standard attributes are applied to the declaration. We parse the two + // attribute sets into different containters so we can apply them during + // the regular parsing process. + while (MaybeParseCXX11Attributes(prefixAttrs) || + MaybeParseGNUAttributes(DeclSpecAttrs)) + ; if (Tok.is(tok::kw_using)) { auto usingDeclPtr = ParseUsingDirectiveOrDeclaration(Context, TemplateInfo, DeclEnd, @@ -223,6 +231,9 @@ Decl *Parser::ParseSingleDeclarationAfterTemplate( // Parse the declaration specifiers, stealing any diagnostics from // the template parameters. ParsingDeclSpec DS(*this, &DiagsFromTParams); + DS.SetRangeStart(DeclSpecAttrs.Range.getBegin()); + DS.SetRangeEnd(DeclSpecAttrs.Range.getEnd()); + DS.takeAttributesFrom(DeclSpecAttrs); ParseDeclarationSpecifiers(DS, TemplateInfo, AS, getDeclSpecContextFromDeclaratorContext(Context)); diff --git a/clang/lib/Parse/ParseTentative.cpp b/clang/lib/Parse/ParseTentative.cpp index ef1f3ca548f6a..e36ce8aa2bfe4 100644 --- a/clang/lib/Parse/ParseTentative.cpp +++ b/clang/lib/Parse/ParseTentative.cpp @@ -723,6 +723,9 @@ Parser::isCXX11AttributeSpecifier(bool Disambiguate, if (Tok.is(tok::kw_alignas)) return CAK_AttributeSpecifier; + if (Tok.isRegularKeywordAttribute()) + return CAK_AttributeSpecifier; + if (Tok.isNot(tok::l_square) || NextToken().isNot(tok::l_square)) return CAK_NotAttributeSpecifier; @@ -862,7 +865,8 @@ Parser::isCXX11AttributeSpecifier(bool Disambiguate, bool Parser::TrySkipAttributes() { while (Tok.isOneOf(tok::l_square, tok::kw___attribute, tok::kw___declspec, - tok::kw_alignas)) { + tok::kw_alignas) || + Tok.isRegularKeywordAttribute()) { if (Tok.is(tok::l_square)) { ConsumeBracket(); if (Tok.isNot(tok::l_square)) @@ -873,6 +877,8 @@ bool Parser::TrySkipAttributes() { // Note that explicitly checking for `[[` and `]]` allows to fail as // expected in the case of the Objective-C message send syntax. ConsumeBracket(); + } else if (Tok.isRegularKeywordAttribute()) { + ConsumeToken(); } else { ConsumeToken(); if (Tok.isNot(tok::l_paren)) diff --git a/clang/lib/Parse/Parser.cpp b/clang/lib/Parse/Parser.cpp index 6e44d5f4892be..b1ccbeb99e589 100644 --- a/clang/lib/Parse/Parser.cpp +++ b/clang/lib/Parse/Parser.cpp @@ -2461,6 +2461,7 @@ Parser::ParseModuleDecl(Sema::ModuleImportState &ImportState) { ParsedAttributes Attrs(AttrFactory); MaybeParseCXX11Attributes(Attrs); ProhibitCXX11Attributes(Attrs, diag::err_attribute_not_module_attr, + diag::err_keyword_not_module_attr, /*DiagnoseEmptyAttrs=*/false, /*WarnOnUnknownAttrs=*/true); @@ -2530,6 +2531,7 @@ Decl *Parser::ParseModuleImport(SourceLocation AtLoc, MaybeParseCXX11Attributes(Attrs); // We don't support any module import attributes yet. ProhibitCXX11Attributes(Attrs, diag::err_attribute_not_import_attr, + diag::err_keyword_not_import_attr, /*DiagnoseEmptyAttrs=*/false, /*WarnOnUnknownAttrs=*/true); diff --git a/clang/lib/Sema/ParsedAttr.cpp b/clang/lib/Sema/ParsedAttr.cpp index 2af688fb58c8a..d7acb589172b5 100644 --- a/clang/lib/Sema/ParsedAttr.cpp +++ b/clang/lib/Sema/ParsedAttr.cpp @@ -203,6 +203,11 @@ bool ParsedAttr::isSupportedByPragmaAttribute() const { } bool ParsedAttr::slidesFromDeclToDeclSpecLegacyBehavior() const { + if (isRegularKeywordAttribute()) + // The appurtenance rules are applied strictly for all regular keyword + // atributes. + return false; + assert(isStandardAttributeSyntax()); // We have historically allowed some type attributes with standard attribute diff --git a/clang/lib/Sema/Sema.cpp b/clang/lib/Sema/Sema.cpp index 9c6db547dbefd..532fb834bcf4f 100644 --- a/clang/lib/Sema/Sema.cpp +++ b/clang/lib/Sema/Sema.cpp @@ -219,7 +219,7 @@ Sema::Sema(Preprocessor &pp, ASTContext &ctxt, ASTConsumer &consumer, ArgumentPackSubstitutionIndex(-1), CurrentInstantiationScope(nullptr), DisableTypoCorrection(false), TyposCorrected(0), AnalysisWarnings(*this), ThreadSafetyDeclCache(nullptr), VarDataSharingAttributesStack(nullptr), - CurScope(nullptr), Ident_super(nullptr), Ident___float128(nullptr) { + CurScope(nullptr), Ident_super(nullptr) { assert(pp.TUKind == TUKind); TUScope = nullptr; isConstantEvaluatedOverride = false; @@ -1184,7 +1184,7 @@ void Sema::ActOnEndOfTranslationUnit() { !(isa(PrevDecl) || isa(PrevDecl))) for (const auto &WI : WeakIDs.second) Diag(WI.getLocation(), diag::warn_attribute_wrong_decl_type) - << "'weak'" << ExpectedVariableOrFunction; + << "'weak'" << /*isRegularKeyword=*/0 << ExpectedVariableOrFunction; else for (const auto &WI : WeakIDs.second) Diag(WI.getLocation(), diag::warn_weak_identifier_undeclared) @@ -2685,12 +2685,6 @@ IdentifierInfo *Sema::getSuperIdentifier() const { return Ident_super; } -IdentifierInfo *Sema::getFloat128Identifier() const { - if (!Ident___float128) - Ident___float128 = &Context.Idents.get("__float128"); - return Ident___float128; -} - void Sema::PushCapturedRegionScope(Scope *S, CapturedDecl *CD, RecordDecl *RD, CapturedRegionKind K, unsigned OpenMPCaptureLevel) { diff --git a/clang/lib/Sema/SemaChecking.cpp b/clang/lib/Sema/SemaChecking.cpp index d94e1d0beeaef..c4544f1a07b8b 100644 --- a/clang/lib/Sema/SemaChecking.cpp +++ b/clang/lib/Sema/SemaChecking.cpp @@ -6411,7 +6411,15 @@ ExprResult Sema::BuildAtomicExpr(SourceRange CallRange, SourceRange ExprRange, Op == AtomicExpr::AO__atomic_store_n || Op == AtomicExpr::AO__atomic_exchange_n || Op == AtomicExpr::AO__atomic_compare_exchange_n; - bool IsAddSub = false; + // Bit mask for extra allowed value types other than integers for atomic + // arithmetic operations. Add/sub allow pointer and floating point. Min/max + // allow floating point. + enum ArithOpExtraValueType { + AOEVT_None = 0, + AOEVT_Pointer = 1, + AOEVT_FP = 2, + }; + unsigned ArithAllows = AOEVT_None; switch (Op) { case AtomicExpr::AO__c11_atomic_init: @@ -6437,18 +6445,30 @@ ExprResult Sema::BuildAtomicExpr(SourceRange CallRange, SourceRange ExprRange, case AtomicExpr::AO__atomic_store_n: Form = Copy; break; - case AtomicExpr::AO__hip_atomic_fetch_add: - case AtomicExpr::AO__hip_atomic_fetch_min: - case AtomicExpr::AO__hip_atomic_fetch_max: - case AtomicExpr::AO__c11_atomic_fetch_add: - case AtomicExpr::AO__c11_atomic_fetch_sub: - case AtomicExpr::AO__opencl_atomic_fetch_add: - case AtomicExpr::AO__opencl_atomic_fetch_sub: case AtomicExpr::AO__atomic_fetch_add: case AtomicExpr::AO__atomic_fetch_sub: case AtomicExpr::AO__atomic_add_fetch: case AtomicExpr::AO__atomic_sub_fetch: - IsAddSub = true; + case AtomicExpr::AO__c11_atomic_fetch_add: + case AtomicExpr::AO__c11_atomic_fetch_sub: + case AtomicExpr::AO__opencl_atomic_fetch_add: + case AtomicExpr::AO__opencl_atomic_fetch_sub: + case AtomicExpr::AO__hip_atomic_fetch_add: + case AtomicExpr::AO__hip_atomic_fetch_sub: + ArithAllows = AOEVT_Pointer | AOEVT_FP; + Form = Arithmetic; + break; + case AtomicExpr::AO__atomic_fetch_max: + case AtomicExpr::AO__atomic_fetch_min: + case AtomicExpr::AO__atomic_max_fetch: + case AtomicExpr::AO__atomic_min_fetch: + case AtomicExpr::AO__c11_atomic_fetch_max: + case AtomicExpr::AO__c11_atomic_fetch_min: + case AtomicExpr::AO__opencl_atomic_fetch_max: + case AtomicExpr::AO__opencl_atomic_fetch_min: + case AtomicExpr::AO__hip_atomic_fetch_max: + case AtomicExpr::AO__hip_atomic_fetch_min: + ArithAllows = AOEVT_FP; Form = Arithmetic; break; case AtomicExpr::AO__c11_atomic_fetch_and: @@ -6471,16 +6491,6 @@ ExprResult Sema::BuildAtomicExpr(SourceRange CallRange, SourceRange ExprRange, case AtomicExpr::AO__atomic_nand_fetch: Form = Arithmetic; break; - case AtomicExpr::AO__c11_atomic_fetch_min: - case AtomicExpr::AO__c11_atomic_fetch_max: - case AtomicExpr::AO__opencl_atomic_fetch_min: - case AtomicExpr::AO__opencl_atomic_fetch_max: - case AtomicExpr::AO__atomic_min_fetch: - case AtomicExpr::AO__atomic_max_fetch: - case AtomicExpr::AO__atomic_fetch_min: - case AtomicExpr::AO__atomic_fetch_max: - Form = Arithmetic; - break; case AtomicExpr::AO__c11_atomic_exchange: case AtomicExpr::AO__hip_atomic_exchange: @@ -6568,12 +6578,13 @@ ExprResult Sema::BuildAtomicExpr(SourceRange CallRange, SourceRange ExprRange, if (Form == Arithmetic) { // GCC does not enforce these rules for GNU atomics, but we do to help catch // trivial type errors. - auto IsAllowedValueType = [&](QualType ValType) { + auto IsAllowedValueType = [&](QualType ValType, + unsigned AllowedType) -> bool { if (ValType->isIntegerType()) return true; if (ValType->isPointerType()) - return true; - if (!ValType->isFloatingType()) + return AllowedType & AOEVT_Pointer; + if (!(ValType->isFloatingType() && (AllowedType & AOEVT_FP))) return false; // LLVM Parser does not allow atomicrmw with x86_fp80 type. if (ValType->isSpecificBuiltinType(BuiltinType::LongDouble) && @@ -6582,13 +6593,13 @@ ExprResult Sema::BuildAtomicExpr(SourceRange CallRange, SourceRange ExprRange, return false; return true; }; - if (IsAddSub && !IsAllowedValueType(ValType)) { - Diag(ExprRange.getBegin(), diag::err_atomic_op_needs_atomic_int_ptr_or_fp) - << IsC11 << Ptr->getType() << Ptr->getSourceRange(); - return ExprError(); - } - if (!IsAddSub && !ValType->isIntegerType()) { - Diag(ExprRange.getBegin(), diag::err_atomic_op_needs_atomic_int) + if (!IsAllowedValueType(ValType, ArithAllows)) { + auto DID = ArithAllows & AOEVT_FP + ? (ArithAllows & AOEVT_Pointer + ? diag::err_atomic_op_needs_atomic_int_ptr_or_fp + : diag::err_atomic_op_needs_atomic_int_or_fp) + : diag::err_atomic_op_needs_atomic_int; + Diag(ExprRange.getBegin(), DID) << IsC11 << Ptr->getType() << Ptr->getSourceRange(); return ExprError(); } diff --git a/clang/lib/Sema/SemaCodeComplete.cpp b/clang/lib/Sema/SemaCodeComplete.cpp index 22d8b5eb44e8d..8c166570265c1 100644 --- a/clang/lib/Sema/SemaCodeComplete.cpp +++ b/clang/lib/Sema/SemaCodeComplete.cpp @@ -10055,12 +10055,12 @@ void Sema::CodeCompleteIncludedFile(llvm::StringRef Dir, bool Angled) { // header maps are not (currently) enumerable. break; case DirectoryLookup::LT_NormalDir: - AddFilesFromIncludeDir(IncludeDir.getDir()->getName(), IsSystem, + AddFilesFromIncludeDir(IncludeDir.getDirRef()->getName(), IsSystem, DirectoryLookup::LT_NormalDir); break; case DirectoryLookup::LT_Framework: - AddFilesFromIncludeDir(IncludeDir.getFrameworkDir()->getName(), IsSystem, - DirectoryLookup::LT_Framework); + AddFilesFromIncludeDir(IncludeDir.getFrameworkDirRef()->getName(), + IsSystem, DirectoryLookup::LT_Framework); break; } }; @@ -10072,9 +10072,8 @@ void Sema::CodeCompleteIncludedFile(llvm::StringRef Dir, bool Angled) { using llvm::make_range; if (!Angled) { // The current directory is on the include path for "quoted" includes. - const FileEntry *CurFile = PP.getCurrentFileLexer()->getFileEntry(); - if (CurFile && CurFile->getDir()) - AddFilesFromIncludeDir(CurFile->getDir()->getName(), false, + if (auto CurFile = PP.getCurrentFileLexer()->getFileEntry()) + AddFilesFromIncludeDir(CurFile->getDir().getName(), false, DirectoryLookup::LT_NormalDir); for (const auto &D : make_range(S.quoted_dir_begin(), S.quoted_dir_end())) AddFilesFromDirLookup(D, false); diff --git a/clang/lib/Sema/SemaDecl.cpp b/clang/lib/Sema/SemaDecl.cpp index aac57196012aa..b8aba816283d6 100644 --- a/clang/lib/Sema/SemaDecl.cpp +++ b/clang/lib/Sema/SemaDecl.cpp @@ -5315,10 +5315,14 @@ Decl *Sema::ParsedFreeStandingDeclSpec(Scope *S, AccessSpecifier AS, TypeSpecType == DeclSpec::TST_union || TypeSpecType == DeclSpec::TST_enum) { for (const ParsedAttr &AL : DS.getAttributes()) - Diag(AL.getLoc(), diag::warn_declspec_attribute_ignored) + Diag(AL.getLoc(), AL.isRegularKeywordAttribute() + ? diag::err_declspec_keyword_has_no_effect + : diag::warn_declspec_attribute_ignored) << AL << GetDiagnosticTypeSpecifierID(DS); for (const ParsedAttr &AL : DeclAttrs) - Diag(AL.getLoc(), diag::warn_declspec_attribute_ignored) + Diag(AL.getLoc(), AL.isRegularKeywordAttribute() + ? diag::err_declspec_keyword_has_no_effect + : diag::warn_declspec_attribute_ignored) << AL << GetDiagnosticTypeSpecifierID(DS); } } @@ -14472,6 +14476,12 @@ Sema::DeclGroupPtrTy Sema::FinalizeDeclaratorGroup(Scope *S, const DeclSpec &DS, for (unsigned i = 0, e = Group.size(); i != e; ++i) { if (Decl *D = Group[i]) { + // Check if the Decl has been declared in '#pragma omp declare target' + // directive and has static storage duration. + if (auto *VD = dyn_cast(D); + LangOpts.OpenMP && VD && VD->hasAttr() && + VD->hasGlobalStorage()) + ActOnOpenMPDeclareTargetInitializer(D); // For declarators, there are some additional syntactic-ish checks we need // to perform. if (auto *DD = dyn_cast(D)) { diff --git a/clang/lib/Sema/SemaDeclAttr.cpp b/clang/lib/Sema/SemaDeclAttr.cpp index 4da5a370f949f..1e48d078a61bb 100644 --- a/clang/lib/Sema/SemaDeclAttr.cpp +++ b/clang/lib/Sema/SemaDeclAttr.cpp @@ -273,7 +273,9 @@ static bool checkPositiveIntArgument(Sema &S, const AttrInfo &AI, const Expr *Ex template static bool checkAttrMutualExclusion(Sema &S, Decl *D, const ParsedAttr &AL) { if (const auto *A = D->getAttr()) { - S.Diag(AL.getLoc(), diag::err_attributes_are_not_compatible) << AL << A; + S.Diag(AL.getLoc(), diag::err_attributes_are_not_compatible) + << AL << A + << (AL.isRegularKeywordAttribute() || A->isRegularKeywordAttribute()); S.Diag(A->getLocation(), diag::note_conflicting_attribute); return true; } @@ -283,8 +285,9 @@ static bool checkAttrMutualExclusion(Sema &S, Decl *D, const ParsedAttr &AL) { template static bool checkAttrMutualExclusion(Sema &S, Decl *D, const Attr &AL) { if (const auto *A = D->getAttr()) { - S.Diag(AL.getLocation(), diag::err_attributes_are_not_compatible) << &AL - << A; + S.Diag(AL.getLocation(), diag::err_attributes_are_not_compatible) + << &AL << A + << (AL.isRegularKeywordAttribute() || A->isRegularKeywordAttribute()); S.Diag(A->getLocation(), diag::note_conflicting_attribute); return true; } @@ -1878,8 +1881,11 @@ static void handleOwnershipAttr(Sema &S, Decl *D, const ParsedAttr &AL) { // Cannot have two ownership attributes of different kinds for the same // index. if (I->getOwnKind() != K && llvm::is_contained(I->args(), Idx)) { - S.Diag(AL.getLoc(), diag::err_attributes_are_not_compatible) << AL << I; - return; + S.Diag(AL.getLoc(), diag::err_attributes_are_not_compatible) + << AL << I + << (AL.isRegularKeywordAttribute() || + I->isRegularKeywordAttribute()); + return; } else if (K == OwnershipAttr::Returns && I->getOwnKind() == OwnershipAttr::Returns) { // A returns attribute conflicts with any other returns attribute using @@ -2164,7 +2170,7 @@ static void handleNakedAttr(Sema &S, Decl *D, const ParsedAttr &AL) { // nonstatic) when in Microsoft compatibility mode. if (S.getLangOpts().MSVCCompat && isa(D)) { S.Diag(AL.getLoc(), diag::err_attribute_wrong_decl_type_str) - << AL << "non-member functions"; + << AL << AL.isRegularKeywordAttribute() << "non-member functions"; return; } } @@ -2177,7 +2183,8 @@ static void handleNoReturnAttr(Sema &S, Decl *D, const ParsedAttr &Attrs) { if (!isa(D)) { S.Diag(Attrs.getLoc(), diag::warn_attribute_wrong_decl_type) - << Attrs << ExpectedFunctionOrMethod; + << Attrs << Attrs.isRegularKeywordAttribute() + << ExpectedFunctionOrMethod; return; } @@ -2218,7 +2225,9 @@ bool Sema::CheckAttrNoArgs(const ParsedAttr &Attrs) { bool Sema::CheckAttrTarget(const ParsedAttr &AL) { // Check whether the attribute is valid on the current target. if (!AL.existsInTarget(Context.getTargetInfo())) { - Diag(AL.getLoc(), diag::warn_unknown_attribute_ignored) + Diag(AL.getLoc(), AL.isRegularKeywordAttribute() + ? diag::err_keyword_not_supported_on_target + : diag::warn_unknown_attribute_ignored) << AL << AL.getRange(); AL.setInvalid(); return true; @@ -2238,7 +2247,8 @@ static void handleAnalyzerNoReturnAttr(Sema &S, Decl *D, const ParsedAttr &AL) { S.Diag(AL.getLoc(), AL.isStandardAttributeSyntax() ? diag::err_attribute_wrong_decl_type : diag::warn_attribute_wrong_decl_type) - << AL << ExpectedFunctionMethodOrBlock; + << AL << AL.isRegularKeywordAttribute() + << ExpectedFunctionMethodOrBlock; return; } } @@ -2888,12 +2898,10 @@ static void handleVisibilityAttr(Sema &S, Decl *D, const ParsedAttr &AL, } // 'type_visibility' can only go on a type or namespace. - if (isTypeVisibility && - !(isa(D) || - isa(D) || - isa(D))) { + if (isTypeVisibility && !(isa(D) || isa(D) || + isa(D))) { S.Diag(AL.getRange().getBegin(), diag::err_attribute_wrong_decl_type) - << AL << ExpectedTypeOrNamespace; + << AL << AL.isRegularKeywordAttribute() << ExpectedTypeOrNamespace; return; } @@ -3112,12 +3120,14 @@ static void handleSentinelAttr(Sema &S, Decl *D, const ParsedAttr &AL) { } } else { S.Diag(AL.getLoc(), diag::warn_attribute_wrong_decl_type) - << AL << ExpectedFunctionMethodOrBlock; + << AL << AL.isRegularKeywordAttribute() + << ExpectedFunctionMethodOrBlock; return; } } else { S.Diag(AL.getLoc(), diag::warn_attribute_wrong_decl_type) - << AL << ExpectedFunctionMethodOrBlock; + << AL << AL.isRegularKeywordAttribute() + << ExpectedFunctionMethodOrBlock; return; } D->addAttr(::new (S.Context) SentinelAttr(S.Context, AL, sentinel, nullPos)); @@ -3142,7 +3152,8 @@ static void handleWarnUnusedResult(Sema &S, Decl *D, const ParsedAttr &AL) { // as a function pointer. if (isa(D)) S.Diag(AL.getLoc(), diag::warn_attribute_wrong_decl_type_str) - << AL << "functions, classes, or enumerations"; + << AL << AL.isRegularKeywordAttribute() + << "functions, classes, or enumerations"; // If this is spelled as the standard C++17 attribute, but not in C++17, // warn about using it as an extension. If there are attribute arguments, @@ -3188,7 +3199,7 @@ static void handleWeakImportAttr(Sema &S, Decl *D, const ParsedAttr &AL) { // Nothing to warn about here. } else S.Diag(AL.getLoc(), diag::warn_attribute_wrong_decl_type) - << AL << ExpectedVariableOrFunction; + << AL << AL.isRegularKeywordAttribute() << ExpectedVariableOrFunction; return; } @@ -3884,7 +3895,9 @@ ErrorAttr *Sema::mergeErrorAttr(Decl *D, const AttributeCommonInfo &CI, (EA->isWarning() && NewAttr == "warning"); if (!Match) { Diag(EA->getLocation(), diag::err_attributes_are_not_compatible) - << CI << EA; + << CI << EA + << (CI.isRegularKeywordAttribute() || + EA->isRegularKeywordAttribute()); Diag(CI.getLoc(), diag::note_conflicting_attribute); return nullptr; } @@ -4201,8 +4214,8 @@ static void handleTransparentUnionAttr(Sema &S, Decl *D, const ParsedAttr &AL) { RD = dyn_cast(D); if (!RD || !RD->isUnion()) { - S.Diag(AL.getLoc(), diag::warn_attribute_wrong_decl_type) << AL - << ExpectedUnion; + S.Diag(AL.getLoc(), diag::warn_attribute_wrong_decl_type) + << AL << AL.isRegularKeywordAttribute() << ExpectedUnion; return; } @@ -4413,7 +4426,7 @@ static bool validateAlignasAppliedType(Sema &S, Decl *D, DiagKind = 4; } else if (!isa(D)) { return S.Diag(AttrLoc, diag::err_attribute_wrong_decl_type) - << &Attr + << &Attr << Attr.isRegularKeywordAttribute() << (Attr.isC11() ? ExpectedVariableOrField : ExpectedVariableFieldOrTag); } @@ -4888,8 +4901,9 @@ InternalLinkageAttr *Sema::mergeInternalLinkageAttr(Decl *D, // ImplicitParm or VarTemplateSpecialization). if (VD->getKind() != Decl::Var) { Diag(AL.getLoc(), diag::warn_attribute_wrong_decl_type) - << AL << (getLangOpts().CPlusPlus ? ExpectedFunctionVariableOrClass - : ExpectedVariableOrFunction); + << AL << AL.isRegularKeywordAttribute() + << (getLangOpts().CPlusPlus ? ExpectedFunctionVariableOrClass + : ExpectedVariableOrFunction); return nullptr; } // Attribute does not apply to non-static local variables. @@ -4908,8 +4922,9 @@ Sema::mergeInternalLinkageAttr(Decl *D, const InternalLinkageAttr &AL) { // ImplicitParm or VarTemplateSpecialization). if (VD->getKind() != Decl::Var) { Diag(AL.getLocation(), diag::warn_attribute_wrong_decl_type) - << &AL << (getLangOpts().CPlusPlus ? ExpectedFunctionVariableOrClass - : ExpectedVariableOrFunction); + << &AL << AL.isRegularKeywordAttribute() + << (getLangOpts().CPlusPlus ? ExpectedFunctionVariableOrClass + : ExpectedVariableOrFunction); return nullptr; } // Attribute does not apply to non-static local variables. @@ -4940,7 +4955,9 @@ SwiftNameAttr *Sema::mergeSwiftNameAttr(Decl *D, const SwiftNameAttr &SNA, if (const auto *PrevSNA = D->getAttr()) { if (PrevSNA->getName() != Name && !PrevSNA->isImplicit()) { Diag(PrevSNA->getLocation(), diag::err_attributes_are_not_compatible) - << PrevSNA << &SNA; + << PrevSNA << &SNA + << (PrevSNA->isRegularKeywordAttribute() || + SNA.isRegularKeywordAttribute()); Diag(SNA.getLoc(), diag::note_conflicting_attribute); } @@ -5105,7 +5122,7 @@ static void handleCallConvAttr(Sema &S, Decl *D, const ParsedAttr &AL) { if (!isa(D)) { S.Diag(AL.getLoc(), diag::warn_attribute_wrong_decl_type) - << AL << ExpectedFunctionOrMethod; + << AL << AL.isRegularKeywordAttribute() << ExpectedFunctionOrMethod; return; } @@ -5236,7 +5253,9 @@ static void handleLifetimeCategoryAttr(Sema &S, Decl *D, const ParsedAttr &AL) { : nullptr; if (ExistingDerefType != ParmType.getTypePtrOrNull()) { S.Diag(AL.getLoc(), diag::err_attributes_are_not_compatible) - << AL << OAttr; + << AL << OAttr + << (AL.isRegularKeywordAttribute() || + OAttr->isRegularKeywordAttribute()); S.Diag(OAttr->getLocation(), diag::note_conflicting_attribute); } return; @@ -5253,7 +5272,9 @@ static void handleLifetimeCategoryAttr(Sema &S, Decl *D, const ParsedAttr &AL) { : nullptr; if (ExistingDerefType != ParmType.getTypePtrOrNull()) { S.Diag(AL.getLoc(), diag::err_attributes_are_not_compatible) - << AL << PAttr; + << AL << PAttr + << (AL.isRegularKeywordAttribute() || + PAttr->isRegularKeywordAttribute()); S.Diag(PAttr->getLocation(), diag::note_conflicting_attribute); } return; @@ -5328,6 +5349,9 @@ bool Sema::CheckCallingConvAttr(const ParsedAttr &Attrs, CallingConv &CC, case ParsedAttr::AT_AArch64SVEPcs: CC = CC_AArch64SVEPCS; break; + case ParsedAttr::AT_ArmStreaming: + CC = CC_C; // FIXME: placeholder until real SME support is added. + break; case ParsedAttr::AT_AMDGPUKernelCall: CC = CC_AMDGPUKernelCall; break; @@ -5485,7 +5509,9 @@ void Sema::AddParameterABIAttr(Decl *D, const AttributeCommonInfo &CI, if (auto existingAttr = D->getAttr()) { if (existingAttr->getABI() != abi) { Diag(CI.getLoc(), diag::err_attributes_are_not_compatible) - << getParameterABISpelling(abi) << existingAttr; + << getParameterABISpelling(abi) << existingAttr + << (CI.isRegularKeywordAttribute() || + existingAttr->isRegularKeywordAttribute()); Diag(existingAttr->getLocation(), diag::note_conflicting_attribute); return; } @@ -5677,7 +5703,7 @@ static void handleTypeTagForDatatypeAttr(Sema &S, Decl *D, if (!isa(D)) { S.Diag(AL.getLoc(), diag::err_attribute_wrong_decl_type) - << AL << ExpectedVariable; + << AL << AL.isRegularKeywordAttribute() << ExpectedVariable; return; } @@ -5983,7 +6009,8 @@ static void handleXReturnsXRetainedAttr(Sema &S, Decl *D, break; } S.Diag(D->getBeginLoc(), diag::warn_attribute_wrong_decl_type) - << AL.getRange() << AL << ExpectedDeclKind; + << AL.getRange() << AL << AL.isRegularKeywordAttribute() + << ExpectedDeclKind; return; } @@ -6255,10 +6282,12 @@ static void handleObjCBoxable(Sema &S, Decl *D, const ParsedAttr &AL) { } static void handleObjCOwnershipAttr(Sema &S, Decl *D, const ParsedAttr &AL) { - if (hasDeclarator(D)) return; + if (hasDeclarator(D)) + return; S.Diag(D->getBeginLoc(), diag::err_attribute_wrong_decl_type) - << AL.getRange() << AL << ExpectedVariable; + << AL.getRange() << AL << AL.isRegularKeywordAttribute() + << ExpectedVariable; } static void handleObjCPreciseLifetimeAttr(Sema &S, Decl *D, @@ -6751,7 +6780,8 @@ bool Sema::DiagnoseSwiftName(Decl *D, StringRef Name, SourceLocation Loc, Params = F->parameters(); if (!F->hasWrittenPrototype()) { - Diag(Loc, diag::warn_attribute_wrong_decl_type) << AL + Diag(Loc, diag::warn_attribute_wrong_decl_type) + << AL << AL.isRegularKeywordAttribute() << ExpectedFunctionWithProtoType; return false; } @@ -6872,7 +6902,7 @@ static void handleSwiftNewType(Sema &S, Decl *D, const ParsedAttr &AL) { if (!isa(D)) { S.Diag(AL.getLoc(), diag::warn_attribute_wrong_decl_type_str) - << AL << "typedefs"; + << AL << AL.isRegularKeywordAttribute() << "typedefs"; return; } @@ -7347,7 +7377,7 @@ static void handleMSP430InterruptAttr(Sema &S, Decl *D, const ParsedAttr &AL) { // a function with no parameters and void return type. if (!isFunctionOrMethod(D)) { S.Diag(D->getLocation(), diag::warn_attribute_wrong_decl_type) - << "'interrupt'" << ExpectedFunctionOrMethod; + << AL << AL.isRegularKeywordAttribute() << ExpectedFunctionOrMethod; return; } @@ -7420,7 +7450,7 @@ static void handleMipsInterruptAttr(Sema &S, Decl *D, const ParsedAttr &AL) { if (!isFunctionOrMethod(D)) { S.Diag(D->getLocation(), diag::warn_attribute_wrong_decl_type) - << "'interrupt'" << ExpectedFunctionOrMethod; + << AL << AL.isRegularKeywordAttribute() << ExpectedFunctionOrMethod; return; } @@ -7495,7 +7525,8 @@ static void handleAnyX86InterruptAttr(Sema &S, Decl *D, const ParsedAttr &AL) { CXXMethodDecl::isStaticOverloadedOperator( cast(D)->getDeclName().getCXXOverloadedOperator())) { S.Diag(AL.getLoc(), diag::warn_attribute_wrong_decl_type) - << AL << ExpectedFunctionWithProtoType; + << AL << AL.isRegularKeywordAttribute() + << ExpectedFunctionWithProtoType; return; } // Interrupt handler must have void return type. @@ -7551,7 +7582,7 @@ static void handleAnyX86InterruptAttr(Sema &S, Decl *D, const ParsedAttr &AL) { static void handleAVRInterruptAttr(Sema &S, Decl *D, const ParsedAttr &AL) { if (!isFunctionOrMethod(D)) { S.Diag(D->getLocation(), diag::warn_attribute_wrong_decl_type) - << "'interrupt'" << ExpectedFunction; + << AL << AL.isRegularKeywordAttribute() << ExpectedFunction; return; } @@ -7564,7 +7595,7 @@ static void handleAVRInterruptAttr(Sema &S, Decl *D, const ParsedAttr &AL) { static void handleAVRSignalAttr(Sema &S, Decl *D, const ParsedAttr &AL) { if (!isFunctionOrMethod(D)) { S.Diag(D->getLocation(), diag::warn_attribute_wrong_decl_type) - << "'signal'" << ExpectedFunction; + << AL << AL.isRegularKeywordAttribute() << ExpectedFunction; return; } @@ -7617,10 +7648,11 @@ BTFDeclTagAttr *Sema::mergeBTFDeclTagAttr(Decl *D, const BTFDeclTagAttr &AL) { return ::new (Context) BTFDeclTagAttr(Context, AL, AL.getBTFDeclTag()); } -static void handleWebAssemblyExportNameAttr(Sema &S, Decl *D, const ParsedAttr &AL) { +static void handleWebAssemblyExportNameAttr(Sema &S, Decl *D, + const ParsedAttr &AL) { if (!isFunctionOrMethod(D)) { S.Diag(D->getLocation(), diag::warn_attribute_wrong_decl_type) - << "'export_name'" << ExpectedFunction; + << AL << AL.isRegularKeywordAttribute() << ExpectedFunction; return; } @@ -7744,7 +7776,7 @@ static void handleRISCVInterruptAttr(Sema &S, Decl *D, if (D->getFunctionType() == nullptr) { S.Diag(D->getLocation(), diag::warn_attribute_wrong_decl_type) - << "'interrupt'" << ExpectedFunction; + << AL << AL.isRegularKeywordAttribute() << ExpectedFunction; return; } @@ -7939,7 +7971,7 @@ static void handleX86ForceAlignArgPointerAttr(Sema &S, Decl *D, // Attribute can only be applied to function types. if (!isa(D)) { S.Diag(AL.getLoc(), diag::warn_attribute_wrong_decl_type) - << AL << ExpectedFunction; + << AL << AL.isRegularKeywordAttribute() << ExpectedFunction; return; } @@ -8218,7 +8250,7 @@ static void handleNoSanitizeSpecificAttr(Sema &S, Decl *D, .Case("no_sanitize_memory", "memory"); if (isGlobalVar(D) && SanitizerName != "address") S.Diag(D->getLocation(), diag::err_attribute_wrong_decl_type) - << AL << ExpectedFunction; + << AL << AL.isRegularKeywordAttribute() << ExpectedFunction; // FIXME: Rather than create a NoSanitizeSpecificAttr, this creates a // NoSanitizeAttr object; but we need to calculate the correct spelling list @@ -8679,7 +8711,9 @@ ProcessDeclAttribute(Sema &S, Scope *scope, Decl *D, const ParsedAttr &AL, if (AL.getKind() == ParsedAttr::UnknownAttribute || !AL.existsInTarget(S.Context.getTargetInfo())) { S.Diag(AL.getLoc(), - AL.isDeclspecAttribute() + AL.isRegularKeywordAttribute() + ? (unsigned)diag::err_keyword_not_supported_on_target + : AL.isDeclspecAttribute() ? (unsigned)diag::warn_unhandled_ms_attribute_ignored : (unsigned)diag::warn_unknown_attribute_ignored) << AL << AL.getRange(); @@ -8708,7 +8742,7 @@ ProcessDeclAttribute(Sema &S, Scope *scope, Decl *D, const ParsedAttr &AL, if (AL.isTypeAttr()) { if (Options.IgnoreTypeAttributes) break; - if (!AL.isStandardAttributeSyntax()) { + if (!AL.isStandardAttributeSyntax() && !AL.isRegularKeywordAttribute()) { // Non-[[]] type attributes are handled in processTypeAttrs(); silently // move on. break; @@ -8773,7 +8807,7 @@ ProcessDeclAttribute(Sema &S, Scope *scope, Decl *D, const ParsedAttr &AL, // needed for type attributes as well as statement attributes in Attr.td // that do not list any subjects. S.Diag(AL.getLoc(), diag::err_attribute_invalid_on_decl) - << AL << D->getLocation(); + << AL << AL.isRegularKeywordAttribute() << D->getLocation(); break; case ParsedAttr::AT_Interrupt: handleInterruptAttr(S, D, AL); @@ -9484,19 +9518,19 @@ void Sema::ProcessDeclAttributeList( } else if (!D->hasAttr()) { if (const auto *A = D->getAttr()) { Diag(D->getLocation(), diag::err_attribute_wrong_decl_type) - << A << ExpectedKernelFunction; + << A << A->isRegularKeywordAttribute() << ExpectedKernelFunction; D->setInvalidDecl(); } else if (const auto *A = D->getAttr()) { Diag(D->getLocation(), diag::err_attribute_wrong_decl_type) - << A << ExpectedKernelFunction; + << A << A->isRegularKeywordAttribute() << ExpectedKernelFunction; D->setInvalidDecl(); } else if (const auto *A = D->getAttr()) { Diag(D->getLocation(), diag::err_attribute_wrong_decl_type) - << A << ExpectedKernelFunction; + << A << A->isRegularKeywordAttribute() << ExpectedKernelFunction; D->setInvalidDecl(); } else if (const auto *A = D->getAttr()) { Diag(D->getLocation(), diag::err_attribute_wrong_decl_type) - << A << ExpectedKernelFunction; + << A << A->isRegularKeywordAttribute() << ExpectedKernelFunction; D->setInvalidDecl(); } } diff --git a/clang/lib/Sema/SemaDeclCXX.cpp b/clang/lib/Sema/SemaDeclCXX.cpp index 65122c04c4b35..3169b381071bb 100644 --- a/clang/lib/Sema/SemaDeclCXX.cpp +++ b/clang/lib/Sema/SemaDeclCXX.cpp @@ -2710,10 +2710,12 @@ BaseResult Sema::ActOnBaseSpecifier(Decl *classdecl, SourceRange SpecifierRange, for (const ParsedAttr &AL : Attributes) { if (AL.isInvalid() || AL.getKind() == ParsedAttr::IgnoredAttribute) continue; - Diag(AL.getLoc(), AL.getKind() == ParsedAttr::UnknownAttribute - ? (unsigned)diag::warn_unknown_attribute_ignored - : (unsigned)diag::err_base_specifier_attribute) - << AL << AL.getRange(); + if (AL.getKind() == ParsedAttr::UnknownAttribute) + Diag(AL.getLoc(), diag::warn_unknown_attribute_ignored) + << AL << AL.getRange(); + else + Diag(AL.getLoc(), diag::err_base_specifier_attribute) + << AL << AL.isRegularKeywordAttribute() << AL.getRange(); } TypeSourceInfo *TInfo = nullptr; diff --git a/clang/lib/Sema/SemaInit.cpp b/clang/lib/Sema/SemaInit.cpp index eaddba3e7c75d..f617cd021e594 100644 --- a/clang/lib/Sema/SemaInit.cpp +++ b/clang/lib/Sema/SemaInit.cpp @@ -1158,6 +1158,7 @@ static void warnBracedScalarInit(Sema &S, const InitializedEntity &Entity, case InitializedEntity::EK_Parameter_CF_Audited: case InitializedEntity::EK_TemplateParameter: case InitializedEntity::EK_Result: + case InitializedEntity::EK_ParenAggInitMember: // Extra braces here are suspicious. DiagID = diag::warn_braces_around_init; break; @@ -1192,7 +1193,6 @@ static void warnBracedScalarInit(Sema &S, const InitializedEntity &Entity, case InitializedEntity::EK_LambdaToBlockConversionBlockElement: case InitializedEntity::EK_Binding: case InitializedEntity::EK_StmtExprResult: - case InitializedEntity::EK_ParenAggInitMember: llvm_unreachable("unexpected braced scalar init"); } diff --git a/clang/lib/Sema/SemaOpenMP.cpp b/clang/lib/Sema/SemaOpenMP.cpp index 45cbfa6eeff13..0b6f5be9f0447 100644 --- a/clang/lib/Sema/SemaOpenMP.cpp +++ b/clang/lib/Sema/SemaOpenMP.cpp @@ -2551,7 +2551,8 @@ OpenMPClauseKind Sema::isOpenMPPrivateDecl(ValueDecl *D, unsigned Level, } } } - if (isOpenMPLoopDirective(DSAStack->getCurrentDirective())) { + if (isOpenMPLoopDirective(DSAStack->getCurrentDirective()) && + !isOpenMPLoopTransformationDirective(DSAStack->getCurrentDirective())) { if (DSAStack->getAssociatedLoops() > 0 && !DSAStack->isLoopStarted()) { DSAStack->resetPossibleLoopCounter(D); DSAStack->loopStart(); @@ -23100,6 +23101,55 @@ void Sema::checkDeclIsAllowedInOpenMPTarget(Expr *E, Decl *D, checkDeclInTargetContext(E->getExprLoc(), E->getSourceRange(), *this, D); } +/// This class visits every VarDecl that the initializer references and adds +/// OMPDeclareTargetDeclAttr to each of them. +class GlobalDeclRefChecker final + : public StmtVisitor { + SmallVector DeclVector; + Attr *A; + +public: + /// A StmtVisitor class function that visits all DeclRefExpr and adds + /// OMPDeclareTargetDeclAttr to them. + void VisitDeclRefExpr(DeclRefExpr *Node) { + if (auto *VD = dyn_cast(Node->getDecl())) { + VD->addAttr(A); + DeclVector.push_back(VD); + } + } + /// A function that iterates across each of the Expr's children. + void VisitExpr(Expr *Ex) { + for (auto *Child : Ex->children()) { + Visit(Child); + } + } + /// A function that keeps a record of all the Decls that are variables, has + /// OMPDeclareTargetDeclAttr, and has global storage in the DeclVector. Pop + /// each Decl one at a time and use the inherited 'visit' functions to look + /// for DeclRefExpr. + void declareTargetInitializer(Decl *TD) { + A = TD->getAttr(); + DeclVector.push_back(cast(TD)); + while (!DeclVector.empty()) { + VarDecl *TargetVarDecl = DeclVector.pop_back_val(); + if (TargetVarDecl->hasAttr() && + TargetVarDecl->hasInit() && TargetVarDecl->hasGlobalStorage()) { + if (Expr *Ex = TargetVarDecl->getInit()) + Visit(Ex); + } + } + } +}; + +/// Adding OMPDeclareTargetDeclAttr to variables with static storage +/// duration that are referenced in the initializer expression list of +/// variables with static storage duration in declare target directive. +void Sema::ActOnOpenMPDeclareTargetInitializer(Decl *TargetDecl) { + GlobalDeclRefChecker Checker; + if (auto *TargetVarDecl = dyn_cast_or_null(TargetDecl)) + Checker.declareTargetInitializer(TargetDecl); +} + OMPClause *Sema::ActOnOpenMPToClause( ArrayRef MotionModifiers, ArrayRef MotionModifiersLoc, diff --git a/clang/lib/Sema/SemaOverload.cpp b/clang/lib/Sema/SemaOverload.cpp index 5308934ed1e3b..71359f13d3a4e 100644 --- a/clang/lib/Sema/SemaOverload.cpp +++ b/clang/lib/Sema/SemaOverload.cpp @@ -12797,10 +12797,9 @@ bool Sema::resolveAndFixAddressOfSingleOverloadCandidate( /// /// If no template-ids are found, no diagnostics are emitted and NULL is /// returned. -FunctionDecl * -Sema::ResolveSingleFunctionTemplateSpecialization(OverloadExpr *ovl, - bool Complain, - DeclAccessPair *FoundResult) { +FunctionDecl *Sema::ResolveSingleFunctionTemplateSpecialization( + OverloadExpr *ovl, bool Complain, DeclAccessPair *FoundResult, + TemplateSpecCandidateSet *FailedTSC) { // C++ [over.over]p1: // [...] [Note: any redundant set of parentheses surrounding the // overloaded function name is ignored (5.1). ] @@ -12814,7 +12813,6 @@ Sema::ResolveSingleFunctionTemplateSpecialization(OverloadExpr *ovl, TemplateArgumentListInfo ExplicitTemplateArgs; ovl->copyTemplateArgumentsInto(ExplicitTemplateArgs); - TemplateSpecCandidateSet FailedCandidates(ovl->getNameLoc()); // Look through all of the overloaded functions, searching for one // whose type matches exactly. @@ -12837,16 +12835,16 @@ Sema::ResolveSingleFunctionTemplateSpecialization(OverloadExpr *ovl, // function template specialization, which is added to the set of // overloaded functions considered. FunctionDecl *Specialization = nullptr; - TemplateDeductionInfo Info(FailedCandidates.getLocation()); + TemplateDeductionInfo Info(ovl->getNameLoc()); if (TemplateDeductionResult Result = DeduceTemplateArguments(FunctionTemplate, &ExplicitTemplateArgs, Specialization, Info, /*IsAddressOfFunction*/true)) { // Make a note of the failed deduction for diagnostics. - // TODO: Actually use the failed-deduction info? - FailedCandidates.addCandidate() - .set(I.getPair(), FunctionTemplate->getTemplatedDecl(), - MakeDeductionFailureInfo(Context, Result, Info)); + if (FailedTSC) + FailedTSC->addCandidate().set( + I.getPair(), FunctionTemplate->getTemplatedDecl(), + MakeDeductionFailureInfo(Context, Result, Info)); continue; } diff --git a/clang/lib/Sema/SemaStmt.cpp b/clang/lib/Sema/SemaStmt.cpp index 7daebbd914024..2c9a17a1fab68 100644 --- a/clang/lib/Sema/SemaStmt.cpp +++ b/clang/lib/Sema/SemaStmt.cpp @@ -3825,9 +3825,18 @@ bool Sema::DeduceFunctionTypeFromReturnExpr(FunctionDecl *FD, { // Otherwise, [...] deduce a value for U using the rules of template // argument deduction. - TemplateDeductionInfo Info(RetExpr->getExprLoc()); - TemplateDeductionResult Res = - DeduceAutoType(OrigResultType, RetExpr, Deduced, Info); + auto RetExprLoc = RetExpr->getExprLoc(); + TemplateDeductionInfo Info(RetExprLoc); + SourceLocation TemplateSpecLoc; + if (RetExpr->getType() == Context.OverloadTy) { + auto FindResult = OverloadExpr::find(RetExpr); + if (FindResult.Expression) + TemplateSpecLoc = FindResult.Expression->getNameLoc(); + } + TemplateSpecCandidateSet FailedTSC(TemplateSpecLoc); + TemplateDeductionResult Res = DeduceAutoType( + OrigResultType, RetExpr, Deduced, Info, /*DependentDeduction=*/false, + /*IgnoreConstraints=*/false, &FailedTSC); if (Res != TDK_Success && FD->isInvalidDecl()) return true; switch (Res) { @@ -3853,6 +3862,7 @@ bool Sema::DeduceFunctionTypeFromReturnExpr(FunctionDecl *FD, default: Diag(RetExpr->getExprLoc(), diag::err_auto_fn_deduction_failure) << OrigResultType.getType() << RetExpr->getType(); + FailedTSC.NoteCandidates(*this, RetExprLoc); return true; } } diff --git a/clang/lib/Sema/SemaStmtAttr.cpp b/clang/lib/Sema/SemaStmtAttr.cpp index 860a5a8524ec7..ad20bc8871f10 100644 --- a/clang/lib/Sema/SemaStmtAttr.cpp +++ b/clang/lib/Sema/SemaStmtAttr.cpp @@ -490,7 +490,9 @@ static Attr *ProcessStmtAttribute(Sema &S, Stmt *St, const ParsedAttr &A, !(A.existsInTarget(S.Context.getTargetInfo()) || (S.Context.getLangOpts().SYCLIsDevice && Aux && A.existsInTarget(*Aux)))) { - S.Diag(A.getLoc(), A.isDeclspecAttribute() + S.Diag(A.getLoc(), A.isRegularKeywordAttribute() + ? (unsigned)diag::err_keyword_not_supported_on_target + : A.isDeclspecAttribute() ? (unsigned)diag::warn_unhandled_ms_attribute_ignored : (unsigned)diag::warn_unknown_attribute_ignored) << A << A.getRange(); @@ -526,7 +528,7 @@ static Attr *ProcessStmtAttribute(Sema &S, Stmt *St, const ParsedAttr &A, // declaration attribute is not written on a statement, but this code is // needed for attributes in Attr.td that do not list any subjects. S.Diag(A.getRange().getBegin(), diag::err_decl_attribute_invalid_on_stmt) - << A << St->getBeginLoc(); + << A << A.isRegularKeywordAttribute() << St->getBeginLoc(); return nullptr; } } diff --git a/clang/lib/Sema/SemaTemplateDeduction.cpp b/clang/lib/Sema/SemaTemplateDeduction.cpp index db72b8b3089e6..b3dc61a74364a 100644 --- a/clang/lib/Sema/SemaTemplateDeduction.cpp +++ b/clang/lib/Sema/SemaTemplateDeduction.cpp @@ -1703,10 +1703,12 @@ static Sema::TemplateDeductionResult DeduceTemplateArgumentsByTypeMatch( if (!IAA) return Sema::TDK_NonDeducedMismatch; + const auto *IAP = S.Context.getAsIncompleteArrayType(P); + assert(IAP && "Template parameter not of incomplete array type"); + return DeduceTemplateArgumentsByTypeMatch( - S, TemplateParams, - S.Context.getAsIncompleteArrayType(P)->getElementType(), - IAA->getElementType(), Info, Deduced, TDF & TDF_IgnoreQualifiers); + S, TemplateParams, IAP->getElementType(), IAA->getElementType(), Info, + Deduced, TDF & TDF_IgnoreQualifiers); } // T [integer-constant] @@ -3749,7 +3751,8 @@ static QualType GetTypeOfFunction(Sema &S, const OverloadExpr::FindResult &R, static QualType ResolveOverloadForDeduction(Sema &S, TemplateParameterList *TemplateParams, Expr *Arg, QualType ParamType, - bool ParamWasReference) { + bool ParamWasReference, + TemplateSpecCandidateSet *FailedTSC = nullptr) { OverloadExpr::FindResult R = OverloadExpr::find(Arg); @@ -3771,8 +3774,10 @@ ResolveOverloadForDeduction(Sema &S, TemplateParameterList *TemplateParams, !ParamType->isMemberFunctionPointerType()) { if (Ovl->hasExplicitTemplateArgs()) { // But we can still look for an explicit specialization. - if (FunctionDecl *ExplicitSpec - = S.ResolveSingleFunctionTemplateSpecialization(Ovl)) + if (FunctionDecl *ExplicitSpec = + S.ResolveSingleFunctionTemplateSpecialization( + Ovl, /*Complain=*/false, + /*FoundDeclAccessPair=*/nullptr, FailedTSC)) return GetTypeOfFunction(S, R, ExplicitSpec); } @@ -3854,7 +3859,8 @@ ResolveOverloadForDeduction(Sema &S, TemplateParameterList *TemplateParams, /// overloaded function set that could not be resolved. static bool AdjustFunctionParmAndArgTypesForDeduction( Sema &S, TemplateParameterList *TemplateParams, unsigned FirstInnerIndex, - QualType &ParamType, QualType &ArgType, Expr *Arg, unsigned &TDF) { + QualType &ParamType, QualType &ArgType, Expr *Arg, unsigned &TDF, + TemplateSpecCandidateSet *FailedTSC = nullptr) { // C++0x [temp.deduct.call]p3: // If P is a cv-qualified type, the top level cv-qualifiers of P's type // are ignored for type deduction. @@ -3871,9 +3877,8 @@ static bool AdjustFunctionParmAndArgTypesForDeduction( // but there are sometimes special circumstances. Typically // involving a template-id-expr. if (ArgType == S.Context.OverloadTy) { - ArgType = ResolveOverloadForDeduction(S, TemplateParams, - Arg, ParamType, - ParamRefType != nullptr); + ArgType = ResolveOverloadForDeduction(S, TemplateParams, Arg, ParamType, + ParamRefType != nullptr, FailedTSC); if (ArgType.isNull()) return true; } @@ -3951,7 +3956,8 @@ static Sema::TemplateDeductionResult DeduceTemplateArgumentsFromCallArgument( QualType ParamType, Expr *Arg, TemplateDeductionInfo &Info, SmallVectorImpl &Deduced, SmallVectorImpl &OriginalCallArgs, - bool DecomposedParam, unsigned ArgIdx, unsigned TDF); + bool DecomposedParam, unsigned ArgIdx, unsigned TDF, + TemplateSpecCandidateSet *FailedTSC = nullptr); /// Attempt template argument deduction from an initializer list /// deemed to be an argument in a function call. @@ -4027,14 +4033,16 @@ static Sema::TemplateDeductionResult DeduceTemplateArgumentsFromCallArgument( QualType ParamType, Expr *Arg, TemplateDeductionInfo &Info, SmallVectorImpl &Deduced, SmallVectorImpl &OriginalCallArgs, - bool DecomposedParam, unsigned ArgIdx, unsigned TDF) { + bool DecomposedParam, unsigned ArgIdx, unsigned TDF, + TemplateSpecCandidateSet *FailedTSC) { QualType ArgType = Arg->getType(); QualType OrigParamType = ParamType; // If P is a reference type [...] // If P is a cv-qualified type [...] - if (AdjustFunctionParmAndArgTypesForDeduction( - S, TemplateParams, FirstInnerIndex, ParamType, ArgType, Arg, TDF)) + if (AdjustFunctionParmAndArgTypesForDeduction(S, TemplateParams, + FirstInnerIndex, ParamType, + ArgType, Arg, TDF, FailedTSC)) return Sema::TDK_Success; // If [...] the argument is a non-empty initializer list [...] @@ -4717,11 +4725,11 @@ static bool CheckDeducedPlaceholderConstraints(Sema &S, const AutoType &Type, /// should be specified in the 'Info' parameter. /// \param IgnoreConstraints Set if we should not fail if the deduced type does /// not satisfy the type-constraint in the auto type. -Sema::TemplateDeductionResult Sema::DeduceAutoType(TypeLoc Type, Expr *Init, - QualType &Result, - TemplateDeductionInfo &Info, - bool DependentDeduction, - bool IgnoreConstraints) { +Sema::TemplateDeductionResult +Sema::DeduceAutoType(TypeLoc Type, Expr *Init, QualType &Result, + TemplateDeductionInfo &Info, bool DependentDeduction, + bool IgnoreConstraints, + TemplateSpecCandidateSet *FailedTSC) { assert(DependentDeduction || Info.getDeducedDepth() == 0); if (Init->containsErrors()) return TDK_AlreadyDiagnosed; @@ -4835,7 +4843,8 @@ Sema::TemplateDeductionResult Sema::DeduceAutoType(TypeLoc Type, Expr *Init, "substituting template parameter for 'auto' failed"); if (auto TDK = DeduceTemplateArgumentsFromCallArgument( *this, TemplateParamsSt.get(), 0, FuncParam, Init, Info, Deduced, - OriginalCallArgs, /*Decomposed=*/false, /*ArgIdx=*/0, /*TDF=*/0)) + OriginalCallArgs, /*Decomposed=*/false, /*ArgIdx=*/0, /*TDF=*/0, + FailedTSC)) return DeductionFailed(TDK); } diff --git a/clang/lib/Sema/SemaType.cpp b/clang/lib/Sema/SemaType.cpp index 06efb3dfef8e6..f844048889b50 100644 --- a/clang/lib/Sema/SemaType.cpp +++ b/clang/lib/Sema/SemaType.cpp @@ -103,8 +103,10 @@ static void diagnoseBadTypeAttribute(Sema &S, const ParsedAttr &attr, } } - S.Diag(loc, diag::warn_type_attribute_wrong_type) << name << WhichType - << type; + S.Diag(loc, attr.isRegularKeywordAttribute() + ? diag::err_type_attribute_wrong_type + : diag::warn_type_attribute_wrong_type) + << name << WhichType << type; } // objc_gc applies to Objective-C pointers or, otherwise, to the @@ -126,6 +128,7 @@ static void diagnoseBadTypeAttribute(Sema &S, const ParsedAttr &attr, case ParsedAttr::AT_VectorCall: \ case ParsedAttr::AT_AArch64VectorPcs: \ case ParsedAttr::AT_AArch64SVEPcs: \ + case ParsedAttr::AT_ArmStreaming: \ case ParsedAttr::AT_AMDGPUKernelCall: \ case ParsedAttr::AT_MSABI: \ case ParsedAttr::AT_SysVABI: \ @@ -684,7 +687,7 @@ static void distributeTypeAttrsFromDeclarator(TypeProcessingState &state, for (ParsedAttr &attr : AttrsCopy) { // Do not distribute [[]] attributes. They have strict rules for what // they appertain to. - if (attr.isStandardAttributeSyntax()) + if (attr.isStandardAttributeSyntax() || attr.isRegularKeywordAttribute()) continue; switch (attr.getKind()) { @@ -947,7 +950,7 @@ static QualType applyObjCTypeArgs(Sema &S, SourceLocation loc, QualType type, // Retrieve the bound. QualType bound = typeParam->getUnderlyingType(); - const auto *boundObjC = bound->getAs(); + const auto *boundObjC = bound->castAs(); // Determine whether the type argument is substitutable for the bound. if (typeArgObjC->isObjCIdType()) { @@ -4895,8 +4898,10 @@ static TypeSourceInfo *GetFullTypeForDeclarator(TypeProcessingState &state, // If we're supposed to infer nullability, do so now. if (inferNullability && !inferNullabilityInnerOnlyComplete) { ParsedAttr::Form form = - inferNullabilityCS ? ParsedAttr::Form::ContextSensitiveKeyword() - : ParsedAttr::Form::Keyword(false /*IsAlignAs*/); + inferNullabilityCS + ? ParsedAttr::Form::ContextSensitiveKeyword() + : ParsedAttr::Form::Keyword(false /*IsAlignAs*/, + false /*IsRegularKeywordAttribute*/); ParsedAttr *nullabilityAttr = Pool.create( S.getNullabilityKeyword(*inferNullability), SourceRange(pointerLoc), nullptr, SourceLocation(), nullptr, 0, form); @@ -7331,12 +7336,12 @@ static bool handleMSPointerTypeQualifierAttr(TypeProcessingState &State, if (Attrs[attr::Ptr32] && Attrs[attr::Ptr64]) { S.Diag(PAttr.getLoc(), diag::err_attributes_are_not_compatible) << "'__ptr32'" - << "'__ptr64'"; + << "'__ptr64'" << /*isRegularKeyword=*/0; return true; } else if (Attrs[attr::SPtr] && Attrs[attr::UPtr]) { S.Diag(PAttr.getLoc(), diag::err_attributes_are_not_compatible) << "'__sptr'" - << "'__uptr'"; + << "'__uptr'" << /*isRegularKeyword=*/0; return true; } @@ -7710,6 +7715,8 @@ static Attr *getCCTypeAttr(ASTContext &Ctx, ParsedAttr &Attr) { return createSimpleAttr(Ctx, Attr); case ParsedAttr::AT_AArch64SVEPcs: return createSimpleAttr(Ctx, Attr); + case ParsedAttr::AT_ArmStreaming: + return createSimpleAttr(Ctx, Attr); case ParsedAttr::AT_AMDGPUKernelCall: return createSimpleAttr(Ctx, Attr); case ParsedAttr::AT_Pcs: { @@ -7857,8 +7864,8 @@ static bool handleFunctionTypeAttr(TypeProcessingState &state, ParsedAttr &attr, CallingConv CC = fn->getCallConv(); if (CC == CC_X86FastCall) { S.Diag(attr.getLoc(), diag::err_attributes_are_not_compatible) - << FunctionType::getNameForCallConv(CC) - << "regparm"; + << FunctionType::getNameForCallConv(CC) << "regparm" + << attr.isRegularKeywordAttribute(); attr.setInvalid(); return true; } @@ -7937,8 +7944,9 @@ static bool handleFunctionTypeAttr(TypeProcessingState &state, ParsedAttr &attr, // and the CCs don't match. if (S.getCallingConvAttributedType(type)) { S.Diag(attr.getLoc(), diag::err_attributes_are_not_compatible) - << FunctionType::getNameForCallConv(CC) - << FunctionType::getNameForCallConv(CCOld); + << FunctionType::getNameForCallConv(CC) + << FunctionType::getNameForCallConv(CCOld) + << attr.isRegularKeywordAttribute(); attr.setInvalid(); return true; } @@ -7970,7 +7978,8 @@ static bool handleFunctionTypeAttr(TypeProcessingState &state, ParsedAttr &attr, // Also diagnose fastcall with regparm. if (CC == CC_X86FastCall && fn->getHasRegParm()) { S.Diag(attr.getLoc(), diag::err_attributes_are_not_compatible) - << "regparm" << FunctionType::getNameForCallConv(CC_X86FastCall); + << "regparm" << FunctionType::getNameForCallConv(CC_X86FastCall) + << attr.isRegularKeywordAttribute(); attr.setInvalid(); return true; } @@ -8331,7 +8340,7 @@ static void HandleRISCVRVVVectorBitsTypeAttr(QualType &CurType, unsigned VecSize = static_cast(RVVVectorSizeInBits.getZExtValue()); ASTContext::BuiltinVectorTypeInfo Info = - S.Context.getBuiltinVectorTypeInfo(CurType->getAs()); + S.Context.getBuiltinVectorTypeInfo(CurType->castAs()); unsigned EltSize = S.Context.getTypeSize(Info.ElementType); unsigned MinElts = Info.EC.getKnownMinValue(); @@ -8486,12 +8495,13 @@ static void processTypeAttrs(TypeProcessingState &state, QualType &type, if (attr.isInvalid()) continue; - if (attr.isStandardAttributeSyntax()) { + if (attr.isStandardAttributeSyntax() || attr.isRegularKeywordAttribute()) { // [[gnu::...]] attributes are treated as declaration attributes, so may // not appertain to a DeclaratorChunk. If we handle them as type // attributes, accept them in that position and diagnose the GCC // incompatibility. if (attr.isGNUScope()) { + assert(attr.isStandardAttributeSyntax()); bool IsTypeAttr = attr.isTypeAttr(); if (TAL == TAL_DeclChunk) { state.getSema().Diag(attr.getLoc(), @@ -8519,9 +8529,11 @@ static void processTypeAttrs(TypeProcessingState &state, QualType &type, switch (attr.getKind()) { default: // A [[]] attribute on a declarator chunk must appertain to a type. - if (attr.isStandardAttributeSyntax() && TAL == TAL_DeclChunk) { + if ((attr.isStandardAttributeSyntax() || + attr.isRegularKeywordAttribute()) && + TAL == TAL_DeclChunk) { state.getSema().Diag(attr.getLoc(), diag::err_attribute_not_type_attr) - << attr; + << attr << attr.isRegularKeywordAttribute(); attr.setUsedAsTypeAttr(); } break; @@ -8702,7 +8714,8 @@ static void processTypeAttrs(TypeProcessingState &state, QualType &type, // Attributes with standard syntax have strict rules for what they // appertain to and hence should not use the "distribution" logic below. - if (attr.isStandardAttributeSyntax()) { + if (attr.isStandardAttributeSyntax() || + attr.isRegularKeywordAttribute()) { if (!handleFunctionTypeAttr(state, attr, type)) { diagnoseBadTypeAttribute(state.getSema(), attr, type); attr.setInvalid(); diff --git a/clang/lib/Serialization/ASTReader.cpp b/clang/lib/Serialization/ASTReader.cpp index f6251fb03ccf2..a0ccc5aa4a741 100644 --- a/clang/lib/Serialization/ASTReader.cpp +++ b/clang/lib/Serialization/ASTReader.cpp @@ -1973,10 +1973,11 @@ HeaderFileInfoTrait::ReadData(internal_key_ref key, const unsigned char *d, std::string Filename = std::string(key.Filename); if (key.Imported) Reader.ResolveImportedPath(M, Filename); - // FIXME: NameAsWritten - Module::Header H = {std::string(key.Filename), "", - FileMgr.getOptionalFileRef(Filename)}; - ModMap.addHeader(Mod, H, HeaderRole, /*Imported*/true); + if (auto FE = FileMgr.getOptionalFileRef(Filename)) { + // FIXME: NameAsWritten + Module::Header H = {std::string(key.Filename), "", *FE}; + ModMap.addHeader(Mod, H, HeaderRole, /*Imported=*/true); + } HFI.isModuleHeader |= ModuleMap::isModular(HeaderRole); } diff --git a/clang/lib/Serialization/ASTReaderDecl.cpp b/clang/lib/Serialization/ASTReaderDecl.cpp index fb8677769d09b..2c1c43dad1603 100644 --- a/clang/lib/Serialization/ASTReaderDecl.cpp +++ b/clang/lib/Serialization/ASTReaderDecl.cpp @@ -3101,11 +3101,12 @@ Attr *ASTRecordReader::readAttr() { bool IsAlignas = (ParsedKind == AttributeCommonInfo::AT_Aligned && Syntax == AttributeCommonInfo::AS_Keyword && SpellingIndex == AlignedAttr::Keyword_alignas); + bool IsRegularKeywordAttribute = Record.readBool(); - AttributeCommonInfo Info( - AttrName, ScopeName, AttrRange, ScopeLoc, - AttributeCommonInfo::Kind(ParsedKind), - {AttributeCommonInfo::Syntax(Syntax), SpellingIndex, IsAlignas}); + AttributeCommonInfo Info(AttrName, ScopeName, AttrRange, ScopeLoc, + AttributeCommonInfo::Kind(ParsedKind), + {AttributeCommonInfo::Syntax(Syntax), SpellingIndex, + IsAlignas, IsRegularKeywordAttribute}); #include "clang/Serialization/AttrPCHRead.inc" diff --git a/clang/lib/Serialization/ASTWriter.cpp b/clang/lib/Serialization/ASTWriter.cpp index 96b087ed57933..ee636028b8e25 100644 --- a/clang/lib/Serialization/ASTWriter.cpp +++ b/clang/lib/Serialization/ASTWriter.cpp @@ -185,8 +185,7 @@ std::set GetAffectingModuleMaps(const Preprocessor &PP, if (!HFI || (HFI->isModuleHeader && !HFI->isCompilingModuleHeader)) continue; - for (const auto &KH : - HS.findAllModulesForHeader(File, /*AllowCreation=*/false)) { + for (const auto &KH : HS.findResolvedModulesForHeader(File)) { if (!KH.getModule()) continue; ModulesToProcess.push_back(KH.getModule()); @@ -1280,8 +1279,9 @@ void ASTWriter::WriteControlBlock(Preprocessor &PP, ASTContext &Context, SmallString<128> BaseDir; if (PP.getHeaderSearchInfo().getHeaderSearchOpts().ModuleFileHomeIsCwd) { // Use the current working directory as the base path for all inputs. - auto *CWD = - Context.getSourceManager().getFileManager().getDirectory(".").get(); + auto CWD = + Context.getSourceManager().getFileManager().getOptionalDirectoryRef( + "."); BaseDir.assign(CWD->getName()); } else { BaseDir.assign(WritingModule->Directory->getName()); @@ -2846,15 +2846,16 @@ void ASTWriter::WriteSubmodules(Module *WritingModule) { } // Emit the umbrella header, if there is one. - if (Module::Header UmbrellaHeader = Mod->getUmbrellaHeaderAsWritten()) { + if (std::optional UmbrellaHeader = + Mod->getUmbrellaHeaderAsWritten()) { RecordData::value_type Record[] = {SUBMODULE_UMBRELLA_HEADER}; Stream.EmitRecordWithBlob(UmbrellaAbbrev, Record, - UmbrellaHeader.NameAsWritten); - } else if (Module::DirectoryName UmbrellaDir = + UmbrellaHeader->NameAsWritten); + } else if (std::optional UmbrellaDir = Mod->getUmbrellaDirAsWritten()) { RecordData::value_type Record[] = {SUBMODULE_UMBRELLA_DIR}; Stream.EmitRecordWithBlob(UmbrellaDirAbbrev, Record, - UmbrellaDir.NameAsWritten); + UmbrellaDir->NameAsWritten); } // Emit the headers. @@ -4379,6 +4380,7 @@ void ASTRecordWriter::AddAttr(const Attr *A) { Record.push_back(A->getParsedKind()); Record.push_back(A->getSyntax()); Record.push_back(A->getAttributeSpellingListIndexRaw()); + Record.push_back(A->isRegularKeywordAttribute()); #include "clang/Serialization/AttrPCHWrite.inc" } diff --git a/clang/lib/Serialization/ASTWriterDecl.cpp b/clang/lib/Serialization/ASTWriterDecl.cpp index 54b5e3877782d..bd935472bcef4 100644 --- a/clang/lib/Serialization/ASTWriterDecl.cpp +++ b/clang/lib/Serialization/ASTWriterDecl.cpp @@ -1136,10 +1136,10 @@ void ASTDeclWriter::VisitVarDecl(VarDecl *D) { !D->isConstexpr() && !D->isInitCapture() && !D->isPreviousDeclInSameBlockScope() && - !D->hasAttr() && !D->isEscapingByref() && !HasDeducedType && D->getStorageDuration() != SD_Static && + !D->getDescribedVarTemplate() && !D->getMemberSpecializationInfo()) AbbrevToUse = Writer.getDeclVarAbbrev(); @@ -2244,8 +2244,8 @@ void ASTWriter::WriteDeclAbbrevs() { Abv->Add(BitCodeAbbrevOp(0)); // InitStyle Abv->Add(BitCodeAbbrevOp(BitCodeAbbrevOp::Fixed, 1)); // isARCPseudoStrong Abv->Add(BitCodeAbbrevOp(0)); // Linkage - Abv->Add(BitCodeAbbrevOp(0)); // HasInit - Abv->Add(BitCodeAbbrevOp(0)); // HasMemberSpecializationInfo + Abv->Add(BitCodeAbbrevOp(0)); // ModulesCodegen + Abv->Add(BitCodeAbbrevOp(0)); // VarKind (local enum) // ParmVarDecl Abv->Add(BitCodeAbbrevOp(BitCodeAbbrevOp::Fixed, 1)); // IsObjCMethodParameter Abv->Add(BitCodeAbbrevOp(0)); // ScopeDepth @@ -2334,8 +2334,8 @@ void ASTWriter::WriteDeclAbbrevs() { Abv->Add(BitCodeAbbrevOp(0)); // EscapingByref Abv->Add(BitCodeAbbrevOp(0)); // HasDeducedType Abv->Add(BitCodeAbbrevOp(BitCodeAbbrevOp::Fixed, 3)); // Linkage - Abv->Add(BitCodeAbbrevOp(BitCodeAbbrevOp::Fixed, 3)); // HasConstant* - Abv->Add(BitCodeAbbrevOp(BitCodeAbbrevOp::Fixed, 2)); // VarKind (local enum) + Abv->Add(BitCodeAbbrevOp(0)); // ModulesCodeGen + Abv->Add(BitCodeAbbrevOp(0)); // VarKind (local enum) // Type Source Info Abv->Add(BitCodeAbbrevOp(BitCodeAbbrevOp::Array)); Abv->Add(BitCodeAbbrevOp(BitCodeAbbrevOp::VBR, 6)); // TypeLoc diff --git a/clang/lib/Serialization/GlobalModuleIndex.cpp b/clang/lib/Serialization/GlobalModuleIndex.cpp index 307a1477213c8..1b8c1303a2886 100644 --- a/clang/lib/Serialization/GlobalModuleIndex.cpp +++ b/clang/lib/Serialization/GlobalModuleIndex.cpp @@ -281,15 +281,6 @@ GlobalModuleIndex::readIndex(StringRef Path) { llvm::Error::success()); } -void -GlobalModuleIndex::getKnownModules(SmallVectorImpl &ModuleFiles) { - ModuleFiles.clear(); - for (unsigned I = 0, N = Modules.size(); I != N; ++I) { - if (ModuleFile *MF = Modules[I].File) - ModuleFiles.push_back(MF); - } -} - void GlobalModuleIndex::getModuleDependencies( ModuleFile *File, SmallVectorImpl &Dependencies) { diff --git a/clang/lib/StaticAnalyzer/Checkers/CStringChecker.cpp b/clang/lib/StaticAnalyzer/Checkers/CStringChecker.cpp index 12b948a65261f..01a35505a90a2 100644 --- a/clang/lib/StaticAnalyzer/Checkers/CStringChecker.cpp +++ b/clang/lib/StaticAnalyzer/Checkers/CStringChecker.cpp @@ -12,6 +12,7 @@ //===----------------------------------------------------------------------===// #include "InterCheckerAPI.h" +#include "clang/Basic/Builtins.h" #include "clang/Basic/CharInfo.h" #include "clang/StaticAnalyzer/Checkers/BuiltinCheckerRegistration.h" #include "clang/StaticAnalyzer/Core/BugReporter/BugType.h" @@ -175,6 +176,8 @@ class CStringChecker : public Checker< eval::Call, std::bind(&CStringChecker::evalMemcmp, _1, _2, _3, CK_Regular)}, {{CDF_MaybeBuiltin, {"bzero"}, 2}, &CStringChecker::evalBzero}, {{CDF_MaybeBuiltin, {"explicit_bzero"}, 2}, &CStringChecker::evalBzero}, + {{CDF_MaybeBuiltin, {"sprintf"}, 2}, &CStringChecker::evalSprintf}, + {{CDF_MaybeBuiltin, {"snprintf"}, 2}, &CStringChecker::evalSnprintf}, }; // These require a bit of special handling. @@ -228,6 +231,11 @@ class CStringChecker : public Checker< eval::Call, void evalMemset(CheckerContext &C, const CallExpr *CE) const; void evalBzero(CheckerContext &C, const CallExpr *CE) const; + void evalSprintf(CheckerContext &C, const CallExpr *CE) const; + void evalSnprintf(CheckerContext &C, const CallExpr *CE) const; + void evalSprintfCommon(CheckerContext &C, const CallExpr *CE, bool IsBounded, + bool IsBuiltin) const; + // Utility methods std::pair static assumeZero(CheckerContext &C, @@ -2352,6 +2360,51 @@ void CStringChecker::evalBzero(CheckerContext &C, const CallExpr *CE) const { C.addTransition(State); } +void CStringChecker::evalSprintf(CheckerContext &C, const CallExpr *CE) const { + CurrentFunctionDescription = "'sprintf'"; + bool IsBI = CE->getBuiltinCallee() == Builtin::BI__builtin___sprintf_chk; + evalSprintfCommon(C, CE, /* IsBounded */ false, IsBI); +} + +void CStringChecker::evalSnprintf(CheckerContext &C, const CallExpr *CE) const { + CurrentFunctionDescription = "'snprintf'"; + bool IsBI = CE->getBuiltinCallee() == Builtin::BI__builtin___snprintf_chk; + evalSprintfCommon(C, CE, /* IsBounded */ true, IsBI); +} + +void CStringChecker::evalSprintfCommon(CheckerContext &C, const CallExpr *CE, + bool IsBounded, bool IsBuiltin) const { + ProgramStateRef State = C.getState(); + DestinationArgExpr Dest = {CE->getArg(0), 0}; + + const auto NumParams = CE->getCalleeDecl()->getAsFunction()->getNumParams(); + assert(CE->getNumArgs() >= NumParams); + + const auto AllArguments = + llvm::make_range(CE->getArgs(), CE->getArgs() + CE->getNumArgs()); + const auto VariadicArguments = drop_begin(enumerate(AllArguments), NumParams); + + for (const auto &[ArgIdx, ArgExpr] : VariadicArguments) { + // We consider only string buffers + if (const QualType type = ArgExpr->getType(); + !type->isAnyPointerType() || + !type->getPointeeType()->isAnyCharacterType()) + continue; + SourceArgExpr Source = {ArgExpr, unsigned(ArgIdx)}; + + // Ensure the buffers do not overlap. + SizeArgExpr SrcExprAsSizeDummy = {Source.Expression, Source.ArgumentIndex}; + State = CheckOverlap( + C, State, + (IsBounded ? SizeArgExpr{CE->getArg(1), 1} : SrcExprAsSizeDummy), Dest, + Source); + if (!State) + return; + } + + C.addTransition(State); +} + //===----------------------------------------------------------------------===// // The driver method, and other Checker callbacks. //===----------------------------------------------------------------------===// diff --git a/clang/lib/StaticAnalyzer/Checkers/NullabilityChecker.cpp b/clang/lib/StaticAnalyzer/Checkers/NullabilityChecker.cpp index da8529f4ea813..11d5e77db0c73 100644 --- a/clang/lib/StaticAnalyzer/Checkers/NullabilityChecker.cpp +++ b/clang/lib/StaticAnalyzer/Checkers/NullabilityChecker.cpp @@ -306,6 +306,10 @@ static NullConstraint getNullConstraint(DefinedOrUnknownSVal Val, return NullConstraint::Unknown; } +static bool isValidPointerType(QualType T) { + return T->isAnyPointerType() || T->isBlockPointerType(); +} + const SymbolicRegion * NullabilityChecker::getTrackRegion(SVal Val, bool CheckSuperRegion) const { if (!NeedTracking) @@ -621,7 +625,7 @@ void NullabilityChecker::checkPreStmt(const ReturnStmt *S, if (!RetExpr) return; - if (!RetExpr->getType()->isAnyPointerType()) + if (!isValidPointerType(RetExpr->getType())) return; ProgramStateRef State = C.getState(); @@ -754,7 +758,7 @@ void NullabilityChecker::checkPreCall(const CallEvent &Call, if (!ArgSVal) continue; - if (!Param->getType()->isAnyPointerType() && + if (!isValidPointerType(Param->getType()) && !Param->getType()->isReferenceType()) continue; @@ -841,7 +845,7 @@ void NullabilityChecker::checkPostCall(const CallEvent &Call, if (!FuncType) return; QualType ReturnType = FuncType->getReturnType(); - if (!ReturnType->isAnyPointerType()) + if (!isValidPointerType(ReturnType)) return; ProgramStateRef State = C.getState(); if (State->get()) @@ -935,7 +939,7 @@ void NullabilityChecker::checkPostObjCMessage(const ObjCMethodCall &M, if (!Decl) return; QualType RetType = Decl->getReturnType(); - if (!RetType->isAnyPointerType()) + if (!isValidPointerType(RetType)) return; ProgramStateRef State = C.getState(); @@ -1089,9 +1093,9 @@ void NullabilityChecker::checkPostStmt(const ExplicitCastExpr *CE, CheckerContext &C) const { QualType OriginType = CE->getSubExpr()->getType(); QualType DestType = CE->getType(); - if (!OriginType->isAnyPointerType()) + if (!isValidPointerType(OriginType)) return; - if (!DestType->isAnyPointerType()) + if (!isValidPointerType(DestType)) return; ProgramStateRef State = C.getState(); @@ -1215,7 +1219,7 @@ void NullabilityChecker::checkBind(SVal L, SVal V, const Stmt *S, return; QualType LocType = TVR->getValueType(); - if (!LocType->isAnyPointerType()) + if (!isValidPointerType(LocType)) return; ProgramStateRef State = C.getState(); diff --git a/clang/lib/StaticAnalyzer/Checkers/StdLibraryFunctionsChecker.cpp b/clang/lib/StaticAnalyzer/Checkers/StdLibraryFunctionsChecker.cpp index 1d6f97f1b702c..57d3c99e4dcfa 100644 --- a/clang/lib/StaticAnalyzer/Checkers/StdLibraryFunctionsChecker.cpp +++ b/clang/lib/StaticAnalyzer/Checkers/StdLibraryFunctionsChecker.cpp @@ -790,13 +790,8 @@ class StdLibraryFunctionsChecker void checkPostCall(const CallEvent &Call, CheckerContext &C) const; bool evalCall(const CallEvent &Call, CheckerContext &C) const; - enum CheckKind { - CK_StdCLibraryFunctionArgsChecker, - CK_StdCLibraryFunctionsTesterChecker, - CK_NumCheckKinds - }; - bool ChecksEnabled[CK_NumCheckKinds] = {false}; - CheckerNameRef CheckNames[CK_NumCheckKinds]; + CheckerNameRef CheckName; + bool AddTestFunctions = false; bool DisplayLoadedSummaries = false; bool ModelPOSIX = false; @@ -813,8 +808,6 @@ class StdLibraryFunctionsChecker void reportBug(const CallEvent &Call, ExplodedNode *N, const ValueConstraint *VC, const ValueConstraint *NegatedVC, const Summary &Summary, CheckerContext &C) const { - if (!ChecksEnabled[CK_StdCLibraryFunctionArgsChecker]) - return; assert(Call.getDecl() && "Function found in summary must have a declaration available"); SmallString<256> Msg; @@ -834,8 +827,8 @@ class StdLibraryFunctionsChecker Msg[0] = toupper(Msg[0]); if (!BT_InvalidArg) BT_InvalidArg = std::make_unique( - CheckNames[CK_StdCLibraryFunctionArgsChecker], - "Function call with invalid argument", categories::LogicError); + CheckName, "Function call with invalid argument", + categories::LogicError); auto R = std::make_unique(*BT_InvalidArg, Msg, N); for (ArgNo ArgN : VC->getArgsToTrack()) { @@ -1423,6 +1416,7 @@ void StdLibraryFunctionsChecker::initFunctionSummaries( CheckerContext &C) const { if (SummariesInitialized) return; + SummariesInitialized = true; SValBuilder &SVB = C.getSValBuilder(); BasicValueFactory &BVF = SVB.getBasicValueFactory(); @@ -3370,7 +3364,7 @@ void StdLibraryFunctionsChecker::initFunctionSummaries( } // Functions for testing. - if (ChecksEnabled[CK_StdCLibraryFunctionsTesterChecker]) { + if (AddTestFunctions) { const RangeInt IntMin = BVF.getMinValue(IntTy).getLimitedValue(); addToFunctionSummaryMap( @@ -3594,12 +3588,11 @@ void StdLibraryFunctionsChecker::initFunctionSummaries( ReturnValueCondition(WithinRange, SingleValue(4))}, ErrnoIrrelevant)); } - - SummariesInitialized = true; } void ento::registerStdCLibraryFunctionsChecker(CheckerManager &mgr) { auto *Checker = mgr.registerChecker(); + Checker->CheckName = mgr.getCurrentCheckerName(); const AnalyzerOptions &Opts = mgr.getAnalyzerOptions(); Checker->DisplayLoadedSummaries = Opts.getCheckerBooleanOption(Checker, "DisplayLoadedSummaries"); @@ -3613,16 +3606,12 @@ bool ento::shouldRegisterStdCLibraryFunctionsChecker( return true; } -#define REGISTER_CHECKER(name) \ - void ento::register##name(CheckerManager &mgr) { \ - StdLibraryFunctionsChecker *checker = \ - mgr.getChecker(); \ - checker->ChecksEnabled[StdLibraryFunctionsChecker::CK_##name] = true; \ - checker->CheckNames[StdLibraryFunctionsChecker::CK_##name] = \ - mgr.getCurrentCheckerName(); \ - } \ - \ - bool ento::shouldRegister##name(const CheckerManager &mgr) { return true; } - -REGISTER_CHECKER(StdCLibraryFunctionArgsChecker) -REGISTER_CHECKER(StdCLibraryFunctionsTesterChecker) +void ento::registerStdCLibraryFunctionsTesterChecker(CheckerManager &mgr) { + auto *Checker = mgr.getChecker(); + Checker->AddTestFunctions = true; +} + +bool ento::shouldRegisterStdCLibraryFunctionsTesterChecker( + const CheckerManager &mgr) { + return true; +} diff --git a/clang/lib/StaticAnalyzer/Core/BasicValueFactory.cpp b/clang/lib/StaticAnalyzer/Core/BasicValueFactory.cpp index fc736dd452aab..5924f6a671c2a 100644 --- a/clang/lib/StaticAnalyzer/Core/BasicValueFactory.cpp +++ b/clang/lib/StaticAnalyzer/Core/BasicValueFactory.cpp @@ -97,8 +97,7 @@ const llvm::APSInt& BasicValueFactory::getValue(const llvm::APSInt& X) { FoldNodeTy* P = APSIntSet.FindNodeOrInsertPos(ID, InsertPos); if (!P) { - P = (FoldNodeTy*) BPAlloc.Allocate(); - new (P) FoldNodeTy(X); + P = new (BPAlloc) FoldNodeTy(X); APSIntSet.InsertNode(P, InsertPos); } @@ -132,8 +131,7 @@ BasicValueFactory::getCompoundValData(QualType T, CompoundValData* D = CompoundValDataSet.FindNodeOrInsertPos(ID, InsertPos); if (!D) { - D = (CompoundValData*) BPAlloc.Allocate(); - new (D) CompoundValData(T, Vals); + D = new (BPAlloc) CompoundValData(T, Vals); CompoundValDataSet.InsertNode(D, InsertPos); } @@ -151,8 +149,7 @@ BasicValueFactory::getLazyCompoundValData(const StoreRef &store, LazyCompoundValDataSet.FindNodeOrInsertPos(ID, InsertPos); if (!D) { - D = (LazyCompoundValData*) BPAlloc.Allocate(); - new (D) LazyCompoundValData(store, region); + D = new (BPAlloc) LazyCompoundValData(store, region); LazyCompoundValDataSet.InsertNode(D, InsertPos); } @@ -169,8 +166,7 @@ const PointerToMemberData *BasicValueFactory::getPointerToMemberData( PointerToMemberDataSet.FindNodeOrInsertPos(ID, InsertPos); if (!D) { - D = (PointerToMemberData *)BPAlloc.Allocate(); - new (D) PointerToMemberData(ND, L); + D = new (BPAlloc) PointerToMemberData(ND, L); PointerToMemberDataSet.InsertNode(D, InsertPos); } @@ -358,8 +354,7 @@ BasicValueFactory::getPersistentSValWithData(const SVal& V, uintptr_t Data) { FoldNodeTy* P = Map.FindNodeOrInsertPos(ID, InsertPos); if (!P) { - P = (FoldNodeTy*) BPAlloc.Allocate(); - new (P) FoldNodeTy(std::make_pair(V, Data)); + P = new (BPAlloc) FoldNodeTy(std::make_pair(V, Data)); Map.InsertNode(P, InsertPos); } @@ -383,8 +378,7 @@ BasicValueFactory::getPersistentSValPair(const SVal& V1, const SVal& V2) { FoldNodeTy* P = Map.FindNodeOrInsertPos(ID, InsertPos); if (!P) { - P = (FoldNodeTy*) BPAlloc.Allocate(); - new (P) FoldNodeTy(std::make_pair(V1, V2)); + P = new (BPAlloc) FoldNodeTy(std::make_pair(V1, V2)); Map.InsertNode(P, InsertPos); } diff --git a/clang/lib/StaticAnalyzer/Core/ExplodedGraph.cpp b/clang/lib/StaticAnalyzer/Core/ExplodedGraph.cpp index cac7ec3f8cf7f..e1f26a50cbc5e 100644 --- a/clang/lib/StaticAnalyzer/Core/ExplodedGraph.cpp +++ b/clang/lib/StaticAnalyzer/Core/ExplodedGraph.cpp @@ -233,8 +233,7 @@ void ExplodedNode::NodeGroup::addNode(ExplodedNode *N, ExplodedGraph &G) { ExplodedNode *Old = Storage.get(); BumpVectorContext &Ctx = G.getNodeAllocator(); - V = G.getAllocator().Allocate(); - new (V) ExplodedNodeVector(Ctx, 4); + V = new (G.getAllocator()) ExplodedNodeVector(Ctx, 4); V->push_back(Old, Ctx); Storage = V; @@ -408,7 +407,7 @@ ExplodedNode *ExplodedGraph::getNode(const ProgramPoint &L, } else { // Allocate a new node. - V = (NodeTy*) getAllocator().Allocate(); + V = getAllocator().Allocate(); } ++NumNodes; @@ -432,7 +431,7 @@ ExplodedNode *ExplodedGraph::createUncachedNode(const ProgramPoint &L, ProgramStateRef State, int64_t Id, bool IsSink) { - NodeTy *V = (NodeTy *) getAllocator().Allocate(); + NodeTy *V = getAllocator().Allocate(); new (V) NodeTy(L, State, Id, IsSink); return V; } diff --git a/clang/lib/StaticAnalyzer/Core/ExprEngine.cpp b/clang/lib/StaticAnalyzer/Core/ExprEngine.cpp index bd5781a81bb5b..194a592fc019a 100644 --- a/clang/lib/StaticAnalyzer/Core/ExprEngine.cpp +++ b/clang/lib/StaticAnalyzer/Core/ExprEngine.cpp @@ -2121,7 +2121,6 @@ void ExprEngine::Visit(const Stmt *S, ExplodedNode *Pred, } } } - // FALLTHROUGH [[fallthrough]]; } diff --git a/clang/lib/StaticAnalyzer/Core/MemRegion.cpp b/clang/lib/StaticAnalyzer/Core/MemRegion.cpp index 0c126a632f745..7cda64d6a028a 100644 --- a/clang/lib/StaticAnalyzer/Core/MemRegion.cpp +++ b/clang/lib/StaticAnalyzer/Core/MemRegion.cpp @@ -73,8 +73,7 @@ RegionTy* MemRegionManager::getSubRegion(const Arg1Ty arg1, auto *R = cast_or_null(Regions.FindNodeOrInsertPos(ID, InsertPos)); if (!R) { - R = A.Allocate(); - new (R) RegionTy(arg1, superRegion); + R = new (A) RegionTy(arg1, superRegion); Regions.InsertNode(R, InsertPos); } @@ -90,8 +89,7 @@ RegionTy* MemRegionManager::getSubRegion(const Arg1Ty arg1, const Arg2Ty arg2, auto *R = cast_or_null(Regions.FindNodeOrInsertPos(ID, InsertPos)); if (!R) { - R = A.Allocate(); - new (R) RegionTy(arg1, arg2, superRegion); + R = new (A) RegionTy(arg1, arg2, superRegion); Regions.InsertNode(R, InsertPos); } @@ -109,8 +107,7 @@ RegionTy* MemRegionManager::getSubRegion(const Arg1Ty arg1, const Arg2Ty arg2, auto *R = cast_or_null(Regions.FindNodeOrInsertPos(ID, InsertPos)); if (!R) { - R = A.Allocate(); - new (R) RegionTy(arg1, arg2, arg3, superRegion); + R = new (A) RegionTy(arg1, arg2, arg3, superRegion); Regions.InsertNode(R, InsertPos); } @@ -712,21 +709,17 @@ std::string MemRegion::getDescriptiveName(bool UseQuotes) const { } SourceRange MemRegion::sourceRange() const { - const auto *const VR = dyn_cast(this->getBaseRegion()); - const auto *const FR = dyn_cast(this); - // Check for more specific regions first. - // FieldRegion - if (FR) { + if (auto *FR = dyn_cast(this)) { return FR->getDecl()->getSourceRange(); } - // VarRegion - else if (VR) { + + if (auto *VR = dyn_cast(this->getBaseRegion())) { return VR->getDecl()->getSourceRange(); } + // Return invalid source range (can be checked by client). - else - return {}; + return {}; } //===----------------------------------------------------------------------===// @@ -838,8 +831,7 @@ DefinedOrUnknownSVal MemRegionManager::getStaticSize(const MemRegion *MR, template const REG *MemRegionManager::LazyAllocate(REG*& region) { if (!region) { - region = A.Allocate(); - new (region) REG(*this); + region = new (A) REG(*this); } return region; @@ -848,8 +840,7 @@ const REG *MemRegionManager::LazyAllocate(REG*& region) { template const REG *MemRegionManager::LazyAllocate(REG*& region, ARG a) { if (!region) { - region = A.Allocate(); - new (region) REG(this, a); + region = new (A) REG(this, a); } return region; @@ -863,8 +854,7 @@ MemRegionManager::getStackLocalsRegion(const StackFrameContext *STC) { if (R) return R; - R = A.Allocate(); - new (R) StackLocalsSpaceRegion(*this, STC); + R = new (A) StackLocalsSpaceRegion(*this, STC); return R; } @@ -876,8 +866,7 @@ MemRegionManager::getStackArgumentsRegion(const StackFrameContext *STC) { if (R) return R; - R = A.Allocate(); - new (R) StackArgumentsSpaceRegion(*this, STC); + R = new (A) StackArgumentsSpaceRegion(*this, STC); return R; } @@ -898,8 +887,7 @@ const GlobalsSpaceRegion if (R) return R; - R = A.Allocate(); - new (R) StaticGlobalSpaceRegion(*this, CR); + R = new (A) StaticGlobalSpaceRegion(*this, CR); return R; } @@ -1145,8 +1133,7 @@ MemRegionManager::getElementRegion(QualType elementType, NonLoc Idx, auto *R = cast_or_null(data); if (!R) { - R = A.Allocate(); - new (R) ElementRegion(T, Idx, superRegion); + R = new (A) ElementRegion(T, Idx, superRegion); Regions.InsertNode(R, InsertPos); } @@ -1283,7 +1270,7 @@ const MemSpaceRegion *MemRegion::getMemorySpace() const { SR = dyn_cast(R); } - return dyn_cast(R); + return cast(R); } bool MemRegion::hasStackStorage() const { @@ -1664,10 +1651,8 @@ void BlockDataRegion::LazyInitializeReferencedVars() { using VarVec = BumpVector; - auto *BV = A.Allocate(); - new (BV) VarVec(BC, NumBlockVars); - auto *BVOriginal = A.Allocate(); - new (BVOriginal) VarVec(BC, NumBlockVars); + auto *BV = new (A) VarVec(BC, NumBlockVars); + auto *BVOriginal = new (A) VarVec(BC, NumBlockVars); for (const auto *VD : ReferencedBlockVars) { const VarRegion *VR = nullptr; diff --git a/clang/lib/StaticAnalyzer/Core/ProgramState.cpp b/clang/lib/StaticAnalyzer/Core/ProgramState.cpp index 90ebbaad2bf3a..e90ebab43c78e 100644 --- a/clang/lib/StaticAnalyzer/Core/ProgramState.cpp +++ b/clang/lib/StaticAnalyzer/Core/ProgramState.cpp @@ -424,7 +424,7 @@ ProgramStateRef ProgramStateManager::getPersistentState(ProgramState &State) { freeStates.pop_back(); } else { - newState = (ProgramState*) Alloc.Allocate(); + newState = Alloc.Allocate(); } new (newState) ProgramState(State); StateSet.InsertNode(newState, InsertPos); diff --git a/clang/lib/StaticAnalyzer/Core/SValBuilder.cpp b/clang/lib/StaticAnalyzer/Core/SValBuilder.cpp index fed17c77f03d0..4fe828bdf7681 100644 --- a/clang/lib/StaticAnalyzer/Core/SValBuilder.cpp +++ b/clang/lib/StaticAnalyzer/Core/SValBuilder.cpp @@ -395,7 +395,6 @@ std::optional SValBuilder::getConstantVal(const Expr *E) { return evalCast(*Val, CE->getType(), SE->getType()); } } - // FALLTHROUGH [[fallthrough]]; } diff --git a/clang/lib/StaticAnalyzer/Core/SymbolManager.cpp b/clang/lib/StaticAnalyzer/Core/SymbolManager.cpp index 032605ffe7a23..b484557ec7394 100644 --- a/clang/lib/StaticAnalyzer/Core/SymbolManager.cpp +++ b/clang/lib/StaticAnalyzer/Core/SymbolManager.cpp @@ -170,8 +170,7 @@ SymbolManager::getRegionValueSymbol(const TypedValueRegion* R) { void *InsertPos; SymExpr *SD = DataSet.FindNodeOrInsertPos(profile, InsertPos); if (!SD) { - SD = (SymExpr*) BPAlloc.Allocate(); - new (SD) SymbolRegionValue(SymbolCounter, R); + SD = new (BPAlloc) SymbolRegionValue(SymbolCounter, R); DataSet.InsertNode(SD, InsertPos); ++SymbolCounter; } @@ -189,8 +188,7 @@ const SymbolConjured* SymbolManager::conjureSymbol(const Stmt *E, void *InsertPos; SymExpr *SD = DataSet.FindNodeOrInsertPos(profile, InsertPos); if (!SD) { - SD = (SymExpr*) BPAlloc.Allocate(); - new (SD) SymbolConjured(SymbolCounter, E, LCtx, T, Count, SymbolTag); + SD = new (BPAlloc) SymbolConjured(SymbolCounter, E, LCtx, T, Count, SymbolTag); DataSet.InsertNode(SD, InsertPos); ++SymbolCounter; } @@ -206,8 +204,7 @@ SymbolManager::getDerivedSymbol(SymbolRef parentSymbol, void *InsertPos; SymExpr *SD = DataSet.FindNodeOrInsertPos(profile, InsertPos); if (!SD) { - SD = (SymExpr*) BPAlloc.Allocate(); - new (SD) SymbolDerived(SymbolCounter, parentSymbol, R); + SD = new (BPAlloc) SymbolDerived(SymbolCounter, parentSymbol, R); DataSet.InsertNode(SD, InsertPos); ++SymbolCounter; } @@ -222,8 +219,7 @@ SymbolManager::getExtentSymbol(const SubRegion *R) { void *InsertPos; SymExpr *SD = DataSet.FindNodeOrInsertPos(profile, InsertPos); if (!SD) { - SD = (SymExpr*) BPAlloc.Allocate(); - new (SD) SymbolExtent(SymbolCounter, R); + SD = new (BPAlloc) SymbolExtent(SymbolCounter, R); DataSet.InsertNode(SD, InsertPos); ++SymbolCounter; } @@ -240,8 +236,7 @@ SymbolManager::getMetadataSymbol(const MemRegion* R, const Stmt *S, QualType T, void *InsertPos; SymExpr *SD = DataSet.FindNodeOrInsertPos(profile, InsertPos); if (!SD) { - SD = (SymExpr*) BPAlloc.Allocate(); - new (SD) SymbolMetadata(SymbolCounter, R, S, T, LCtx, Count, SymbolTag); + SD = new (BPAlloc) SymbolMetadata(SymbolCounter, R, S, T, LCtx, Count, SymbolTag); DataSet.InsertNode(SD, InsertPos); ++SymbolCounter; } @@ -257,8 +252,7 @@ SymbolManager::getCastSymbol(const SymExpr *Op, void *InsertPos; SymExpr *data = DataSet.FindNodeOrInsertPos(ID, InsertPos); if (!data) { - data = (SymbolCast*) BPAlloc.Allocate(); - new (data) SymbolCast(Op, From, To); + data = new (BPAlloc) SymbolCast(Op, From, To); DataSet.InsertNode(data, InsertPos); } @@ -275,8 +269,7 @@ const SymIntExpr *SymbolManager::getSymIntExpr(const SymExpr *lhs, SymExpr *data = DataSet.FindNodeOrInsertPos(ID, InsertPos); if (!data) { - data = (SymIntExpr*) BPAlloc.Allocate(); - new (data) SymIntExpr(lhs, op, v, t); + data = new (BPAlloc) SymIntExpr(lhs, op, v, t); DataSet.InsertNode(data, InsertPos); } @@ -293,8 +286,7 @@ const IntSymExpr *SymbolManager::getIntSymExpr(const llvm::APSInt& lhs, SymExpr *data = DataSet.FindNodeOrInsertPos(ID, InsertPos); if (!data) { - data = (IntSymExpr*) BPAlloc.Allocate(); - new (data) IntSymExpr(lhs, op, rhs, t); + data = new (BPAlloc) IntSymExpr(lhs, op, rhs, t); DataSet.InsertNode(data, InsertPos); } @@ -311,8 +303,7 @@ const SymSymExpr *SymbolManager::getSymSymExpr(const SymExpr *lhs, SymExpr *data = DataSet.FindNodeOrInsertPos(ID, InsertPos); if (!data) { - data = (SymSymExpr*) BPAlloc.Allocate(); - new (data) SymSymExpr(lhs, op, rhs, t); + data = new (BPAlloc) SymSymExpr(lhs, op, rhs, t); DataSet.InsertNode(data, InsertPos); } @@ -327,8 +318,7 @@ const UnarySymExpr *SymbolManager::getUnarySymExpr(const SymExpr *Operand, void *InsertPos; SymExpr *data = DataSet.FindNodeOrInsertPos(ID, InsertPos); if (!data) { - data = (UnarySymExpr *)BPAlloc.Allocate(); - new (data) UnarySymExpr(Operand, Opc, T); + data = new (BPAlloc) UnarySymExpr(Operand, Opc, T); DataSet.InsertNode(data, InsertPos); } diff --git a/clang/lib/Tooling/CMakeLists.txt b/clang/lib/Tooling/CMakeLists.txt index e4ce43762d6b6..aff39e4de13c0 100644 --- a/clang/lib/Tooling/CMakeLists.txt +++ b/clang/lib/Tooling/CMakeLists.txt @@ -53,6 +53,8 @@ else() list(APPEND implicitDirs -I ${implicitDir}) endforeach() + include(GetClangResourceDir) + get_clang_resource_dir(resource_dir PREFIX ${LLVM_BINARY_DIR}) add_custom_command( COMMENT Generate ASTNodeAPI.json OUTPUT ${CMAKE_CURRENT_BINARY_DIR}/ASTNodeAPI.json @@ -61,7 +63,7 @@ else() $ # Skip this in debug mode because parsing AST.h is too slow --skip-processing=${skip_expensive_processing} - -I ${LLVM_BINARY_DIR}/lib/clang/${CLANG_VERSION_MAJOR}/include + -I ${resource_dir}/include -I ${CLANG_SOURCE_DIR}/include -I ${LLVM_BINARY_DIR}/tools/clang/include -I ${LLVM_BINARY_DIR}/include diff --git a/clang/lib/Tooling/Inclusions/HeaderAnalysis.cpp b/clang/lib/Tooling/Inclusions/HeaderAnalysis.cpp index 49d23908d33b7..f83e19f10cbab 100644 --- a/clang/lib/Tooling/Inclusions/HeaderAnalysis.cpp +++ b/clang/lib/Tooling/Inclusions/HeaderAnalysis.cpp @@ -67,7 +67,7 @@ llvm::StringRef getFileContents(const FileEntry *FE, const SourceManager &SM) { } // namespace bool isSelfContainedHeader(const FileEntry *FE, const SourceManager &SM, - HeaderSearch &HeaderInfo) { + const HeaderSearch &HeaderInfo) { assert(FE); if (!HeaderInfo.isFileMultipleIncludeGuarded(FE) && !HeaderInfo.hasFileBeenImported(FE) && diff --git a/clang/lib/Tooling/Tooling.cpp b/clang/lib/Tooling/Tooling.cpp index dd22cfedd0ffe..46a784e44b931 100644 --- a/clang/lib/Tooling/Tooling.cpp +++ b/clang/lib/Tooling/Tooling.cpp @@ -542,13 +542,11 @@ int ClangTool::run(ToolAction *Action) { // Remember the working directory in case we need to restore it. std::string InitialWorkingDir; - if (RestoreCWD) { - if (auto CWD = OverlayFileSystem->getCurrentWorkingDirectory()) { - InitialWorkingDir = std::move(*CWD); - } else { - llvm::errs() << "Could not get working directory: " - << CWD.getError().message() << "\n"; - } + if (auto CWD = OverlayFileSystem->getCurrentWorkingDirectory()) { + InitialWorkingDir = std::move(*CWD); + } else { + llvm::errs() << "Could not get working directory: " + << CWD.getError().message() << "\n"; } for (llvm::StringRef File : AbsolutePaths) { @@ -662,10 +660,6 @@ int ClangTool::buildASTs(std::vector> &ASTs) { return run(&Action); } -void ClangTool::setRestoreWorkingDir(bool RestoreCWD) { - this->RestoreCWD = RestoreCWD; -} - void ClangTool::setPrintErrorMessage(bool PrintErrorMessage) { this->PrintErrorMessage = PrintErrorMessage; } diff --git a/clang/runtime/CMakeLists.txt b/clang/runtime/CMakeLists.txt index 94b5d783ce361..2dd305428c9ac 100644 --- a/clang/runtime/CMakeLists.txt +++ b/clang/runtime/CMakeLists.txt @@ -66,6 +66,9 @@ if(LLVM_BUILD_EXTERNAL_COMPILER_RT AND EXISTS ${COMPILER_RT_SRC_ROOT}/) list(APPEND compiler_rt_configure_deps LLVMTestingSupport) endif() + include(GetClangResourceDir) + get_clang_resource_dir(output_resource_dir PREFIX ${LLVM_BINARY_DIR}) + get_clang_resource_dir(install_resource_dir) ExternalProject_Add(compiler-rt DEPENDS llvm-config clang ${compiler_rt_configure_deps} PREFIX ${COMPILER_RT_PREFIX} @@ -82,9 +85,9 @@ if(LLVM_BUILD_EXTERNAL_COMPILER_RT AND EXISTS ${COMPILER_RT_SRC_ROOT}/) -DCMAKE_CXX_COMPILER_LAUNCHER=${CMAKE_CXX_COMPILER_LAUNCHER} -DLLVM_CONFIG_PATH=${LLVM_RUNTIME_OUTPUT_INTDIR}/llvm-config -DLLVM_LIT_ARGS=${LLVM_LIT_ARGS} - -DCOMPILER_RT_OUTPUT_DIR=${LLVM_LIBRARY_OUTPUT_INTDIR}/clang/${CLANG_VERSION_MAJOR} + -DCOMPILER_RT_OUTPUT_DIR=${output_resource_dir} -DCOMPILER_RT_EXEC_OUTPUT_DIR=${LLVM_RUNTIME_OUTPUT_INTDIR} - -DCOMPILER_RT_INSTALL_PATH:PATH=lib${LLVM_LIBDIR_SUFFIX}/clang/${CLANG_VERSION_MAJOR} + -DCOMPILER_RT_INSTALL_PATH:PATH=${install_resource_dir} -DCOMPILER_RT_INCLUDE_TESTS=${LLVM_INCLUDE_TESTS} -DCMAKE_INSTALL_PREFIX=${CMAKE_INSTALL_PREFIX} -DLLVM_LIBDIR_SUFFIX=${LLVM_LIBDIR_SUFFIX} diff --git a/clang/test/AST/Interp/c.c b/clang/test/AST/Interp/c.c new file mode 100644 index 0000000000000..fe794bb014e7c --- /dev/null +++ b/clang/test/AST/Interp/c.c @@ -0,0 +1,12 @@ +// RUN: %clang_cc1 -fexperimental-new-constant-interpreter -verify %s +// RUN: %clang_cc1 -verify=ref %s + +/// expected-no-diagnostics +/// ref-no-diagnostics + +_Static_assert(1, ""); +_Static_assert(0 != 1, ""); +_Static_assert(1.0 == 1.0, ""); +_Static_assert( (5 > 4) + (3 > 2) == 2, ""); + +int a = (1 == 1 ? 5 : 3); diff --git a/clang/test/AST/Interp/cxx20.cpp b/clang/test/AST/Interp/cxx20.cpp index 2bf935ef2375b..5d9fa90b482ea 100644 --- a/clang/test/AST/Interp/cxx20.cpp +++ b/clang/test/AST/Interp/cxx20.cpp @@ -138,8 +138,8 @@ static_assert(!b4); // ref-error {{not an integral constant expression}} \ namespace UninitializedFields { class A { public: - int a; // expected-note 2{{subobject declared here}} \ - // ref-note 2{{subobject declared here}} + int a; // expected-note 3{{subobject declared here}} \ + // ref-note 3{{subobject declared here}} constexpr A() {} }; constexpr A a; // expected-error {{must be initialized by a constant expression}} \ @@ -174,19 +174,15 @@ namespace UninitializedFields { // ref-error {{must be initialized by a constant expression}} \ // ref-note {{subobject 'a' is not initialized}} - - // FIXME: These two are currently disabled because the array fields - // cannot be initialized. -#if 0 class C3 { public: A a[2]; constexpr C3() {} }; constexpr C3 c3; // expected-error {{must be initialized by a constant expression}} \ - // expected-note {{subobject of type 'int' is not initialized}} \ + // expected-note {{subobject 'a' is not initialized}} \ // ref-error {{must be initialized by a constant expression}} \ - // ref-note {{subobject of type 'int' is not initialized}} + // ref-note {{subobject 'a' is not initialized}} class C4 { public: @@ -195,10 +191,9 @@ namespace UninitializedFields { constexpr C4(){} }; constexpr C4 c4; // expected-error {{must be initialized by a constant expression}} \ - // expected-note {{subobject of type 'bool' is not initialized}} \ + // expected-note {{subobject 'B' is not initialized}} \ // ref-error {{must be initialized by a constant expression}} \ - // ref-note {{subobject of type 'bool' is not initialized}} -#endif + // ref-note {{subobject 'B' is not initialized}} }; namespace ConstThis { diff --git a/clang/test/AST/Interp/depth-limit.cpp b/clang/test/AST/Interp/depth-limit.cpp new file mode 100644 index 0000000000000..a6d5e56b141c3 --- /dev/null +++ b/clang/test/AST/Interp/depth-limit.cpp @@ -0,0 +1,35 @@ +// RUN: %clang_cc1 -fexperimental-new-constant-interpreter -fconstexpr-depth 100 -verify %s +// RUN: %clang_cc1 -fconstexpr-depth 100 -verify=ref %s + +constexpr int f(int a) { + if (a == 100) + return 1 / 0; // expected-warning {{division by zero is undefined}} \ + // ref-warning {{division by zero is undefined}} + + return f(a + 1); // ref-note {{exceeded maximum depth of 100 calls}} \ + // ref-note {{in call to 'f(99)'}} \ + // ref-note {{in call to 'f(98)'}} \ + // ref-note {{in call to 'f(97)'}} \ + // ref-note {{in call to 'f(96)'}} \ + // ref-note {{in call to 'f(95)'}} \ + // ref-note {{skipping 90 calls in backtrace}} \ + // ref-note {{in call to 'f(4)'}} \ + // ref-note {{in call to 'f(3)'}} \ + // ref-note {{in call to 'f(2)'}} \ + // ref-note {{in call to 'f(1)'}} \ + // expected-note {{exceeded maximum depth of 100 calls}} \ + // expected-note {{in call to 'f(99)'}} \ + // expected-note {{in call to 'f(98)'}} \ + // expected-note {{in call to 'f(97)'}} \ + // expected-note {{in call to 'f(96)'}} \ + // expected-note {{in call to 'f(95)'}} \ + // expected-note {{skipping 90 calls in backtrace}} \ + // expected-note {{in call to 'f(4)'}} \ + // expected-note {{in call to 'f(3)'}} \ + // expected-note {{in call to 'f(2)'}} \ + // expected-note {{in call to 'f(1)'}} +} +static_assert(f(0) == 100, ""); // ref-error {{not an integral constant expression}} \ + // ref-note {{in call to 'f(0)'}} \ + // expected-error {{not an integral constant expression}} \ + // expected-note {{in call to 'f(0)'}} diff --git a/clang/test/AST/Interp/depth-limit2.cpp b/clang/test/AST/Interp/depth-limit2.cpp new file mode 100644 index 0000000000000..3f6e64a5cf67f --- /dev/null +++ b/clang/test/AST/Interp/depth-limit2.cpp @@ -0,0 +1,23 @@ +// RUN: %clang_cc1 -fexperimental-new-constant-interpreter -fconstexpr-depth 2 -verify %s +// RUN: %clang_cc1 -fconstexpr-depth 2 -verify=ref %s + + +constexpr int func() { + return 12; +} + +constexpr int foo() { + return func(); // expected-note {{exceeded maximum depth of 2 calls}} \ + // ref-note {{exceeded maximum depth of 2 calls}} +} + +constexpr int bar() { + return foo(); // expected-note {{in call to 'foo()'}} \ + // ref-note {{in call to 'foo()'}} +} + +static_assert(bar() == 12, ""); // expected-error {{not an integral constant expression}} \ + // expected-note {{in call to 'bar()'}} \ + // ref-error {{not an integral constant expression}} \ + // ref-note {{in call to 'bar()'}} + diff --git a/clang/test/Analysis/Checkers/WebKit/uncounted-lambda-captures.cpp b/clang/test/Analysis/Checkers/WebKit/uncounted-lambda-captures.cpp index 85dd77f9a8774..30798793ceab1 100644 --- a/clang/test/Analysis/Checkers/WebKit/uncounted-lambda-captures.cpp +++ b/clang/test/Analysis/Checkers/WebKit/uncounted-lambda-captures.cpp @@ -5,14 +5,14 @@ void raw_ptr() { RefCountable* ref_countable = nullptr; auto foo1 = [ref_countable](){}; // CHECK: warning: Captured raw-pointer 'ref_countable' to uncounted type is unsafe [webkit.UncountedLambdaCapturesChecker] - // CHECK-NEXT:{{^}} auto foo1 = [ref_countable](){}; - // CHECK-NEXT:{{^}} ^ + // CHECK-NEXT:{{^ 6 | }} auto foo1 = [ref_countable](){}; + // CHECK-NEXT:{{^ | }} ^ auto foo2 = [&ref_countable](){}; // CHECK: warning: Captured raw-pointer 'ref_countable' to uncounted type is unsafe [webkit.UncountedLambdaCapturesChecker] auto foo3 = [&](){ ref_countable = nullptr; }; // CHECK: warning: Implicitly captured raw-pointer 'ref_countable' to uncounted type is unsafe [webkit.UncountedLambdaCapturesChecker] - // CHECK-NEXT:{{^}} auto foo3 = [&](){ ref_countable = nullptr; }; - // CHECK-NEXT:{{^}} ^ + // CHECK-NEXT:{{^ 12 | }} auto foo3 = [&](){ ref_countable = nullptr; }; + // CHECK-NEXT:{{^ | }} ^ auto foo4 = [=](){ (void) ref_countable; }; // CHECK: warning: Implicitly captured raw-pointer 'ref_countable' to uncounted type is unsafe [webkit.UncountedLambdaCapturesChecker] } diff --git a/clang/test/Analysis/PR49642.c b/clang/test/Analysis/PR49642.c index 6d8c65814b7af..c21050fd4a5c8 100644 --- a/clang/test/Analysis/PR49642.c +++ b/clang/test/Analysis/PR49642.c @@ -1,6 +1,6 @@ // RUN: %clang_analyze_cc1 -Wno-implicit-function-declaration -Wno-implicit-int -w -verify %s \ // RUN: -analyzer-checker=core \ -// RUN: -analyzer-checker=apiModeling.StdCLibraryFunctions +// RUN: -analyzer-checker=alpha.unix.StdCLibraryFunctions // expected-no-diagnostics diff --git a/clang/test/Analysis/analyzer-config.c b/clang/test/Analysis/analyzer-config.c index f6ebfbcd2660c..ed5e6c8cca63c 100644 --- a/clang/test/Analysis/analyzer-config.c +++ b/clang/test/Analysis/analyzer-config.c @@ -13,8 +13,8 @@ // CHECK-NEXT: alpha.security.MmapWriteExec:MmapProtRead = 0x01 // CHECK-NEXT: alpha.security.taint.TaintPropagation:Config = "" // CHECK-NEXT: alpha.unix.Errno:AllowErrnoReadOutsideConditionExpressions = true -// CHECK-NEXT: apiModeling.StdCLibraryFunctions:DisplayLoadedSummaries = false -// CHECK-NEXT: apiModeling.StdCLibraryFunctions:ModelPOSIX = false +// CHECK-NEXT: alpha.unix.StdCLibraryFunctions:DisplayLoadedSummaries = false +// CHECK-NEXT: alpha.unix.StdCLibraryFunctions:ModelPOSIX = false // CHECK-NEXT: apply-fixits = false // CHECK-NEXT: assume-controlled-environment = false // CHECK-NEXT: avoid-suppressing-null-argument-paths = false diff --git a/clang/test/Analysis/analyzer-enabled-checkers.c b/clang/test/Analysis/analyzer-enabled-checkers.c index fa306d78d5553..ca6aa7c8cea28 100644 --- a/clang/test/Analysis/analyzer-enabled-checkers.c +++ b/clang/test/Analysis/analyzer-enabled-checkers.c @@ -7,12 +7,11 @@ // CHECK: OVERVIEW: Clang Static Analyzer Enabled Checkers List // CHECK-EMPTY: // CHECK-NEXT: apiModeling.Errno -// CHECK-NEXT: core.CallAndMessageModeling -// CHECK-NEXT: apiModeling.StdCLibraryFunctions // CHECK-NEXT: apiModeling.TrustNonnull // CHECK-NEXT: apiModeling.TrustReturnsNonnull // CHECK-NEXT: apiModeling.llvm.CastValue // CHECK-NEXT: apiModeling.llvm.ReturnValue +// CHECK-NEXT: core.CallAndMessageModeling // CHECK-NEXT: core.CallAndMessage // CHECK-NEXT: core.DivideZero // CHECK-NEXT: core.DynamicTypePropagation diff --git a/clang/test/Analysis/buffer-overlap.c b/clang/test/Analysis/buffer-overlap.c new file mode 100644 index 0000000000000..8414a764541e2 --- /dev/null +++ b/clang/test/Analysis/buffer-overlap.c @@ -0,0 +1,98 @@ +// RUN: %clang_analyze_cc1 -verify %s \ +// RUN: -analyzer-checker=alpha.unix.cstring.BufferOverlap +// +// RUN: %clang_analyze_cc1 -verify %s -DUSE_BUILTINS \ +// RUN: -analyzer-checker=alpha.unix.cstring.BufferOverlap +// +// RUN: %clang_analyze_cc1 -verify %s -DVARIANT \ +// RUN: -analyzer-checker=alpha.unix.cstring.BufferOverlap +// +// RUN: %clang_analyze_cc1 -verify %s -DVARIANT -DUSE_BUILTINS \ +// RUN: -analyzer-checker=alpha.unix.cstring.BufferOverlap + +// This provides us with four possible sprintf() definitions. + +#ifdef USE_BUILTINS +#define BUILTIN(f) __builtin_##f +#else /* USE_BUILTINS */ +#define BUILTIN(f) f +#endif /* USE_BUILTINS */ + +typedef typeof(sizeof(int)) size_t; + +#ifdef VARIANT + +#define __sprintf_chk BUILTIN(__sprintf_chk) +#define __snprintf_chk BUILTIN(__snprintf_chk) +int __sprintf_chk (char * __restrict str, int flag, size_t os, + const char * __restrict fmt, ...); +int __snprintf_chk (char * __restrict str, size_t len, int flag, size_t os, + const char * __restrict fmt, ...); + +#define sprintf(str, ...) __sprintf_chk(str, 0, __builtin_object_size(str, 0), __VA_ARGS__) +#define snprintf(str, len, ...) __snprintf_chk(str, len, 0, __builtin_object_size(str, 0), __VA_ARGS__) + +#else /* VARIANT */ + +#define sprintf BUILTIN(sprintf) +int sprintf(char *restrict buffer, const char *restrict format, ... ); +int snprintf(char *restrict buffer, size_t bufsz, + const char *restrict format, ... ); +#endif /* VARIANT */ + +void test_sprintf1() { + char a[4] = {0}; + sprintf(a, "%d/%s", 1, a); // expected-warning{{Arguments must not be overlapping buffers}} +} + +void test_sprintf2() { + char a[4] = {0}; + sprintf(a, "%s", a); // expected-warning{{Arguments must not be overlapping buffers}} +} + +void test_sprintf3() { + char a[4] = {0}; + sprintf(a, "%s/%s", a, a); // expected-warning{{Arguments must not be overlapping buffers}} +} + +void test_sprintf4() { + char a[4] = {0}; + sprintf(a, "%d", 42); // no-warning +} + +void test_sprintf5() { + char a[4] = {0}; + char b[4] = {0}; + sprintf(a, "%s", b); // no-warning +} + +void test_snprintf1() { + char a[4] = {0}; + snprintf(a, sizeof(a), "%d/%s", 1, a); // expected-warning{{Arguments must not be overlapping buffers}} +} + +void test_snprintf2() { + char a[4] = {0}; + snprintf(a+1, sizeof(a)-1, "%d/%s", 1, a); // expected-warning{{Arguments must not be overlapping buffers}} +} + +void test_snprintf3() { + char a[4] = {0}; + snprintf(a, sizeof(a), "%s", a); // expected-warning{{Arguments must not be overlapping buffers}} +} + +void test_snprintf4() { + char a[4] = {0}; + snprintf(a, sizeof(a), "%s/%s", a, a); // expected-warning{{Arguments must not be overlapping buffers}} +} + +void test_snprintf5() { + char a[4] = {0}; + snprintf(a, sizeof(a), "%d", 42); // no-warning +} + +void test_snprintf6() { + char a[4] = {0}; + char b[4] = {0}; + snprintf(a, sizeof(a), "%s", b); // no-warning +} diff --git a/clang/test/Analysis/conversion.c b/clang/test/Analysis/conversion.c index 78b614516b63e..0d2e005550b16 100644 --- a/clang/test/Analysis/conversion.c +++ b/clang/test/Analysis/conversion.c @@ -1,6 +1,6 @@ // RUN: %clang_analyze_cc1 %s \ // RUN: -Wno-conversion -Wno-tautological-constant-compare \ -// RUN: -analyzer-checker=core,apiModeling,alpha.core.Conversion \ +// RUN: -analyzer-checker=core,apiModeling,alpha.unix.StdCLibraryFunctions,alpha.core.Conversion \ // RUN: -verify unsigned char U8; @@ -187,7 +187,7 @@ char dontwarn10(long long x) { } -// C library functions, handled via apiModeling.StdCLibraryFunctions +// C library functions, handled via alpha.unix.StdCLibraryFunctions int isascii(int c); void libraryFunction1(void) { diff --git a/clang/test/Analysis/errno-stdlibraryfunctions-notes.c b/clang/test/Analysis/errno-stdlibraryfunctions-notes.c index 54820d4566703..4172935e1e3f6 100644 --- a/clang/test/Analysis/errno-stdlibraryfunctions-notes.c +++ b/clang/test/Analysis/errno-stdlibraryfunctions-notes.c @@ -1,10 +1,10 @@ // RUN: %clang_analyze_cc1 -verify -analyzer-output text %s \ // RUN: -analyzer-checker=core \ // RUN: -analyzer-checker=debug.ExprInspection \ -// RUN: -analyzer-checker=apiModeling.StdCLibraryFunctions \ +// RUN: -analyzer-checker=alpha.unix.StdCLibraryFunctions \ // RUN: -analyzer-checker=apiModeling.Errno \ // RUN: -analyzer-checker=alpha.unix.Errno \ -// RUN: -analyzer-config apiModeling.StdCLibraryFunctions:ModelPOSIX=true +// RUN: -analyzer-config alpha.unix.StdCLibraryFunctions:ModelPOSIX=true #include "Inputs/errno_var.h" diff --git a/clang/test/Analysis/errno-stdlibraryfunctions.c b/clang/test/Analysis/errno-stdlibraryfunctions.c index db34e3f6f6ef9..a3b42f4425c35 100644 --- a/clang/test/Analysis/errno-stdlibraryfunctions.c +++ b/clang/test/Analysis/errno-stdlibraryfunctions.c @@ -1,10 +1,10 @@ // RUN: %clang_analyze_cc1 -verify %s \ // RUN: -analyzer-checker=core \ // RUN: -analyzer-checker=debug.ExprInspection \ -// RUN: -analyzer-checker=apiModeling.StdCLibraryFunctions \ +// RUN: -analyzer-checker=alpha.unix.StdCLibraryFunctions \ // RUN: -analyzer-checker=apiModeling.Errno \ // RUN: -analyzer-checker=alpha.unix.Errno \ -// RUN: -analyzer-config apiModeling.StdCLibraryFunctions:ModelPOSIX=true +// RUN: -analyzer-config alpha.unix.StdCLibraryFunctions:ModelPOSIX=true #include "Inputs/errno_var.h" diff --git a/clang/test/Analysis/nullability.mm b/clang/test/Analysis/nullability.mm index f9b3fc60c5a02..44c241e07ee50 100644 --- a/clang/test/Analysis/nullability.mm +++ b/clang/test/Analysis/nullability.mm @@ -46,10 +46,13 @@ - (int *_Nonnull)returnsNonnull; - (int *_Nullable)returnsNullable; - (int *)returnsUnspecified; - (void)takesNonnull:(int *_Nonnull)p; +- (void)takesNonnullBlock:(void (^ _Nonnull)(void))block; - (void)takesNullable:(int *_Nullable)p; - (void)takesUnspecified:(int *)p; @property(readonly, strong) NSString *stuff; @property(readonly, nonnull) int *propReturnsNonnull; +@property(readonly, nonnull) void (^propReturnsNonnullBlock)(void); +@property(readonly, nullable) void (^propReturnsNullableBlock)(void); @property(readonly, nullable) int *propReturnsNullable; @property(readonly) int *propReturnsUnspecified; @end @@ -65,6 +68,7 @@ - (void)takesUnspecified:(int *)p; void takesNullable(Dummy *_Nullable); void takesNonnull(Dummy *_Nonnull); void takesUnspecified(Dummy *); +void takesNonnullBlock(void (^ _Nonnull)(void)); Dummy *_Nullable returnsNullable(); Dummy *_Nonnull returnsNonnull(); @@ -197,6 +201,7 @@ void testObjCPropertyReadNullability() { switch (getRandom()) { case 0: [o takesNonnull:o.propReturnsNonnull]; // no-warning + [o takesNonnullBlock:o.propReturnsNonnullBlock]; // no-warning break; case 1: [o takesNonnull:o.propReturnsUnspecified]; // no-warning @@ -236,6 +241,9 @@ void testObjCPropertyReadNullability() { assert(o.propReturnsNullable); [o takesNonnull:o.propReturnsNullable]; // no-warning break; + case 8: + [o takesNonnullBlock:o.propReturnsNullableBlock]; // expected-warning {{Nullable pointer is passed to a callee that requires a non-null 1st parameter}} + break; } } @@ -308,6 +316,11 @@ void testIndirectNilPassToNonnull() { takesNonnull(p); // expected-warning {{Null passed to a callee that requires a non-null 1st parameter}} } +void testBlockIndirectNilPassToNonnull() { + void (^p)(void) = nil; + takesNonnullBlock(p); // expected-warning {{Null passed to a callee that requires a non-null 1st parameter}} +} + void testConditionalNilPassToNonnull(Dummy *p) { if (!p) { takesNonnull(p); // expected-warning {{Null passed to a callee that requires a non-null 1st parameter}} diff --git a/clang/test/Analysis/std-c-library-functions-POSIX-lookup.c b/clang/test/Analysis/std-c-library-functions-POSIX-lookup.c index 09e481574827a..22f752fee0ece 100644 --- a/clang/test/Analysis/std-c-library-functions-POSIX-lookup.c +++ b/clang/test/Analysis/std-c-library-functions-POSIX-lookup.c @@ -1,8 +1,8 @@ // RUN: %clang_analyze_cc1 %s \ // RUN: -analyzer-checker=core \ -// RUN: -analyzer-checker=apiModeling.StdCLibraryFunctions \ -// RUN: -analyzer-config apiModeling.StdCLibraryFunctions:ModelPOSIX=true \ -// RUN: -analyzer-config apiModeling.StdCLibraryFunctions:DisplayLoadedSummaries=true \ +// RUN: -analyzer-checker=alpha.unix.StdCLibraryFunctions \ +// RUN: -analyzer-config alpha.unix.StdCLibraryFunctions:ModelPOSIX=true \ +// RUN: -analyzer-config alpha.unix.StdCLibraryFunctions:DisplayLoadedSummaries=true \ // RUN: -analyzer-checker=debug.ExprInspection \ // RUN: -analyzer-config eagerly-assume=false \ // RUN: -triple i686-unknown-linux 2>&1 | FileCheck %s --allow-empty diff --git a/clang/test/Analysis/std-c-library-functions-POSIX-socket-sockaddr.cpp b/clang/test/Analysis/std-c-library-functions-POSIX-socket-sockaddr.cpp index a35bb5cdc3a04..c835b80960c39 100644 --- a/clang/test/Analysis/std-c-library-functions-POSIX-socket-sockaddr.cpp +++ b/clang/test/Analysis/std-c-library-functions-POSIX-socket-sockaddr.cpp @@ -1,8 +1,8 @@ // RUN: %clang_analyze_cc1 %s \ // RUN: -analyzer-checker=core \ -// RUN: -analyzer-checker=apiModeling.StdCLibraryFunctions \ -// RUN: -analyzer-config apiModeling.StdCLibraryFunctions:ModelPOSIX=true \ -// RUN: -analyzer-config apiModeling.StdCLibraryFunctions:DisplayLoadedSummaries=true \ +// RUN: -analyzer-checker=alpha.unix.StdCLibraryFunctions \ +// RUN: -analyzer-config alpha.unix.StdCLibraryFunctions:ModelPOSIX=true \ +// RUN: -analyzer-config alpha.unix.StdCLibraryFunctions:DisplayLoadedSummaries=true \ // RUN: -analyzer-checker=debug.ExprInspection \ // RUN: -analyzer-config eagerly-assume=false \ // RUN: -triple i686-unknown-linux 2>&1 | FileCheck %s diff --git a/clang/test/Analysis/std-c-library-functions-POSIX.c b/clang/test/Analysis/std-c-library-functions-POSIX.c index a646e63b856e6..e8f2e67edb749 100644 --- a/clang/test/Analysis/std-c-library-functions-POSIX.c +++ b/clang/test/Analysis/std-c-library-functions-POSIX.c @@ -1,8 +1,8 @@ // RUN: %clang_analyze_cc1 %s \ // RUN: -analyzer-checker=core \ -// RUN: -analyzer-checker=apiModeling.StdCLibraryFunctions \ -// RUN: -analyzer-config apiModeling.StdCLibraryFunctions:ModelPOSIX=true \ -// RUN: -analyzer-config apiModeling.StdCLibraryFunctions:DisplayLoadedSummaries=true \ +// RUN: -analyzer-checker=alpha.unix.StdCLibraryFunctions \ +// RUN: -analyzer-config alpha.unix.StdCLibraryFunctions:ModelPOSIX=true \ +// RUN: -analyzer-config alpha.unix.StdCLibraryFunctions:DisplayLoadedSummaries=true \ // RUN: -analyzer-checker=debug.ExprInspection \ // RUN: -analyzer-config eagerly-assume=false \ // RUN: -triple i686-unknown-linux 2>&1 | FileCheck %s diff --git a/clang/test/Analysis/std-c-library-functions-arg-constraints-note-tags.cpp b/clang/test/Analysis/std-c-library-functions-arg-constraints-note-tags.cpp index f9d901fca9da1..f31ce589072ab 100644 --- a/clang/test/Analysis/std-c-library-functions-arg-constraints-note-tags.cpp +++ b/clang/test/Analysis/std-c-library-functions-arg-constraints-note-tags.cpp @@ -1,9 +1,8 @@ // RUN: %clang_analyze_cc1 %s \ // RUN: -analyzer-checker=core \ -// RUN: -analyzer-checker=apiModeling.StdCLibraryFunctions \ -// RUN: -analyzer-checker=alpha.unix.StdCLibraryFunctionArgs \ +// RUN: -analyzer-checker=alpha.unix.StdCLibraryFunctions \ // RUN: -analyzer-checker=debug.StdCLibraryFunctionsTester \ -// RUN: -analyzer-config apiModeling.StdCLibraryFunctions:DisplayLoadedSummaries=true \ +// RUN: -analyzer-config alpha.unix.StdCLibraryFunctions:DisplayLoadedSummaries=true \ // RUN: -analyzer-checker=debug.ExprInspection \ // RUN: -analyzer-config eagerly-assume=false \ // RUN: -triple i686-unknown-linux \ diff --git a/clang/test/Analysis/std-c-library-functions-arg-constraints-notes.cpp b/clang/test/Analysis/std-c-library-functions-arg-constraints-notes.cpp index 156b80a5488ac..781b96d53103a 100644 --- a/clang/test/Analysis/std-c-library-functions-arg-constraints-notes.cpp +++ b/clang/test/Analysis/std-c-library-functions-arg-constraints-notes.cpp @@ -1,9 +1,8 @@ // RUN: %clang_analyze_cc1 %s \ // RUN: -analyzer-checker=core \ -// RUN: -analyzer-checker=apiModeling.StdCLibraryFunctions \ -// RUN: -analyzer-checker=alpha.unix.StdCLibraryFunctionArgs \ +// RUN: -analyzer-checker=alpha.unix.StdCLibraryFunctions \ // RUN: -analyzer-checker=debug.StdCLibraryFunctionsTester \ -// RUN: -analyzer-config apiModeling.StdCLibraryFunctions:DisplayLoadedSummaries=true \ +// RUN: -analyzer-config alpha.unix.StdCLibraryFunctions:DisplayLoadedSummaries=true \ // RUN: -analyzer-checker=debug.ExprInspection \ // RUN: -analyzer-config eagerly-assume=false \ // RUN: -triple i686-unknown-linux \ diff --git a/clang/test/Analysis/std-c-library-functions-arg-constraints-tracking-notes.c b/clang/test/Analysis/std-c-library-functions-arg-constraints-tracking-notes.c index 766b0c58910cb..d497b87c48473 100644 --- a/clang/test/Analysis/std-c-library-functions-arg-constraints-tracking-notes.c +++ b/clang/test/Analysis/std-c-library-functions-arg-constraints-tracking-notes.c @@ -1,8 +1,7 @@ // Check the bugpath related to the reports. // RUN: %clang_analyze_cc1 %s \ // RUN: -analyzer-checker=core \ -// RUN: -analyzer-checker=apiModeling.StdCLibraryFunctions \ -// RUN: -analyzer-checker=alpha.unix.StdCLibraryFunctionArgs \ +// RUN: -analyzer-checker=alpha.unix.StdCLibraryFunctions \ // RUN: -analyzer-checker=debug.StdCLibraryFunctionsTester \ // RUN: -analyzer-checker=debug.ExprInspection \ // RUN: -triple x86_64-unknown-linux-gnu \ diff --git a/clang/test/Analysis/std-c-library-functions-arg-constraints.c b/clang/test/Analysis/std-c-library-functions-arg-constraints.c index 615f84047af59..6a5f9454fd1ee 100644 --- a/clang/test/Analysis/std-c-library-functions-arg-constraints.c +++ b/clang/test/Analysis/std-c-library-functions-arg-constraints.c @@ -1,9 +1,8 @@ // Check the basic reporting/warning and the application of constraints. // RUN: %clang_analyze_cc1 %s \ // RUN: -analyzer-checker=core \ -// RUN: -analyzer-checker=apiModeling.StdCLibraryFunctions \ -// RUN: -analyzer-checker=alpha.unix.StdCLibraryFunctionArgs \ -// RUN: -analyzer-config apiModeling.StdCLibraryFunctions:ModelPOSIX=true \ +// RUN: -analyzer-checker=alpha.unix.StdCLibraryFunctions \ +// RUN: -analyzer-config alpha.unix.StdCLibraryFunctions:ModelPOSIX=true \ // RUN: -analyzer-checker=debug.StdCLibraryFunctionsTester \ // RUN: -analyzer-checker=debug.ExprInspection \ // RUN: -triple x86_64-unknown-linux-gnu \ @@ -12,9 +11,8 @@ // Check the bugpath related to the reports. // RUN: %clang_analyze_cc1 %s \ // RUN: -analyzer-checker=core \ -// RUN: -analyzer-checker=apiModeling.StdCLibraryFunctions \ -// RUN: -analyzer-checker=alpha.unix.StdCLibraryFunctionArgs \ -// RUN: -analyzer-config apiModeling.StdCLibraryFunctions:ModelPOSIX=true \ +// RUN: -analyzer-checker=alpha.unix.StdCLibraryFunctions \ +// RUN: -analyzer-config alpha.unix.StdCLibraryFunctions:ModelPOSIX=true \ // RUN: -analyzer-checker=debug.StdCLibraryFunctionsTester \ // RUN: -analyzer-checker=debug.ExprInspection \ // RUN: -triple x86_64-unknown-linux-gnu \ diff --git a/clang/test/Analysis/std-c-library-functions-arg-constraints.cpp b/clang/test/Analysis/std-c-library-functions-arg-constraints.cpp index 48060bf052737..80a680eb55842 100644 --- a/clang/test/Analysis/std-c-library-functions-arg-constraints.cpp +++ b/clang/test/Analysis/std-c-library-functions-arg-constraints.cpp @@ -1,7 +1,6 @@ // RUN: %clang_analyze_cc1 %s \ // RUN: -analyzer-checker=core \ -// RUN: -analyzer-checker=apiModeling.StdCLibraryFunctions \ -// RUN: -analyzer-checker=alpha.unix.StdCLibraryFunctionArgs \ +// RUN: -analyzer-checker=alpha.unix.StdCLibraryFunctions \ // RUN: -analyzer-checker=debug.StdCLibraryFunctionsTester \ // RUN: -analyzer-checker=debug.ExprInspection \ // RUN: -analyzer-config eagerly-assume=false \ diff --git a/clang/test/Analysis/std-c-library-functions-arg-cstring-dependency.c b/clang/test/Analysis/std-c-library-functions-arg-cstring-dependency.c index 37425e4e3e169..5ebb07e524753 100644 --- a/clang/test/Analysis/std-c-library-functions-arg-cstring-dependency.c +++ b/clang/test/Analysis/std-c-library-functions-arg-cstring-dependency.c @@ -5,10 +5,9 @@ // RUN: %clang_analyze_cc1 %s \ // RUN: -analyzer-checker=core \ -// RUN: -analyzer-checker=apiModeling.StdCLibraryFunctions \ +// RUN: -analyzer-checker=alpha.unix.StdCLibraryFunctions \ // RUN: -analyzer-checker=unix.cstring.NullArg \ -// RUN: -analyzer-config apiModeling.StdCLibraryFunctions:ModelPOSIX=true \ -// RUN: -analyzer-checker=alpha.unix.StdCLibraryFunctionArgs \ +// RUN: -analyzer-config alpha.unix.StdCLibraryFunctions:ModelPOSIX=true \ // RUN: -triple x86_64-unknown-linux-gnu \ // RUN: -verify diff --git a/clang/test/Analysis/std-c-library-functions-arg-enabled-checkers.c b/clang/test/Analysis/std-c-library-functions-arg-enabled-checkers.c index 4e5c66a8a0a40..6965c311eeae4 100644 --- a/clang/test/Analysis/std-c-library-functions-arg-enabled-checkers.c +++ b/clang/test/Analysis/std-c-library-functions-arg-enabled-checkers.c @@ -1,12 +1,11 @@ -// Here we test the order of the Checkers when StdCLibraryFunctionArgs is +// Here we test the order of the Checkers when StdCLibraryFunctions is // enabled. // RUN: %clang --analyze %s --target=x86_64-pc-linux-gnu \ // RUN: -Xclang -analyzer-checker=core \ -// RUN: -Xclang -analyzer-checker=apiModeling.StdCLibraryFunctions \ +// RUN: -Xclang -analyzer-checker=alpha.unix.StdCLibraryFunctions \ // RUN: -Xclang -analyzer-config \ -// RUN: -Xclang apiModeling.StdCLibraryFunctions:ModelPOSIX=true \ -// RUN: -Xclang -analyzer-checker=alpha.unix.StdCLibraryFunctionArgs \ +// RUN: -Xclang alpha.unix.StdCLibraryFunctions:ModelPOSIX=true \ // RUN: -Xclang -analyzer-checker=alpha.unix.Stream \ // RUN: -Xclang -analyzer-list-enabled-checkers \ // RUN: -Xclang -analyzer-display-progress \ @@ -18,8 +17,7 @@ // CHECK-NEXT: core.CallAndMessageModeling // CHECK-NEXT: core.CallAndMessage // CHECK-NEXT: core.NonNullParamChecker -// CHECK-NEXT: apiModeling.StdCLibraryFunctions -// CHECK-NEXT: alpha.unix.StdCLibraryFunctionArgs +// CHECK-NEXT: alpha.unix.StdCLibraryFunctions // CHECK-NEXT: alpha.unix.Stream // CHECK-NEXT: apiModeling.Errno // CHECK-NEXT: apiModeling.TrustNonnull diff --git a/clang/test/Analysis/std-c-library-functions-arg-weakdeps.c b/clang/test/Analysis/std-c-library-functions-arg-weakdeps.c index 3d2d5a6aae2b2..6f95563d045fb 100644 --- a/clang/test/Analysis/std-c-library-functions-arg-weakdeps.c +++ b/clang/test/Analysis/std-c-library-functions-arg-weakdeps.c @@ -1,11 +1,10 @@ // Check that the more specific checkers report and not the generic -// StdCLibraryFunctionArgs checker. +// StdCLibraryFunctions checker. // RUN: %clang_analyze_cc1 %s \ // RUN: -analyzer-checker=core \ -// RUN: -analyzer-checker=apiModeling.StdCLibraryFunctions \ -// RUN: -analyzer-config apiModeling.StdCLibraryFunctions:ModelPOSIX=true \ -// RUN: -analyzer-checker=alpha.unix.StdCLibraryFunctionArgs \ +// RUN: -analyzer-checker=alpha.unix.StdCLibraryFunctions \ +// RUN: -analyzer-config alpha.unix.StdCLibraryFunctions:ModelPOSIX=true \ // RUN: -triple x86_64-unknown-linux-gnu \ // RUN: -verify @@ -14,10 +13,9 @@ // RUN: %clang_analyze_cc1 %s \ // RUN: -analyzer-checker=core \ -// RUN: -analyzer-checker=apiModeling.StdCLibraryFunctions \ -// RUN: -analyzer-config apiModeling.StdCLibraryFunctions:ModelPOSIX=true \ -// RUN: -analyzer-checker=alpha.unix.StdCLibraryFunctionArgs \ -// RUN: -analyzer-config apiModeling.StdCLibraryFunctions:DisplayLoadedSummaries=true \ +// RUN: -analyzer-checker=alpha.unix.StdCLibraryFunctions \ +// RUN: -analyzer-config alpha.unix.StdCLibraryFunctions:ModelPOSIX=true \ +// RUN: -analyzer-config alpha.unix.StdCLibraryFunctions:DisplayLoadedSummaries=true \ // RUN: -triple x86_64-unknown-linux 2>&1 | FileCheck %s // CHECK: Loaded summary for: int isalnum(int) diff --git a/clang/test/Analysis/std-c-library-functions-eof.c b/clang/test/Analysis/std-c-library-functions-eof.c index 0b09a1c63d97b..0050bf2d9bee2 100644 --- a/clang/test/Analysis/std-c-library-functions-eof.c +++ b/clang/test/Analysis/std-c-library-functions-eof.c @@ -1,8 +1,8 @@ -// RUN: %clang_analyze_cc1 -analyzer-checker=core,apiModeling.StdCLibraryFunctions,debug.ExprInspection -verify -analyzer-config eagerly-assume=false %s -// RUN: %clang_analyze_cc1 -triple i686-unknown-linux -analyzer-checker=core,apiModeling.StdCLibraryFunctions,debug.ExprInspection -verify -analyzer-config eagerly-assume=false %s -// RUN: %clang_analyze_cc1 -triple x86_64-unknown-linux -analyzer-checker=core,apiModeling.StdCLibraryFunctions,debug.ExprInspection -verify -analyzer-config eagerly-assume=false %s -// RUN: %clang_analyze_cc1 -triple armv7-a15-linux -analyzer-checker=core,apiModeling.StdCLibraryFunctions,debug.ExprInspection -verify -analyzer-config eagerly-assume=false %s -// RUN: %clang_analyze_cc1 -triple thumbv7-a15-linux -analyzer-checker=core,apiModeling.StdCLibraryFunctions,debug.ExprInspection -verify -analyzer-config eagerly-assume=false %s +// RUN: %clang_analyze_cc1 -analyzer-checker=core,alpha.unix.StdCLibraryFunctions,debug.ExprInspection -verify -analyzer-config eagerly-assume=false %s +// RUN: %clang_analyze_cc1 -triple i686-unknown-linux -analyzer-checker=core,alpha.unix.StdCLibraryFunctions,debug.ExprInspection -verify -analyzer-config eagerly-assume=false %s +// RUN: %clang_analyze_cc1 -triple x86_64-unknown-linux -analyzer-checker=core,alpha.unix.StdCLibraryFunctions,debug.ExprInspection -verify -analyzer-config eagerly-assume=false %s +// RUN: %clang_analyze_cc1 -triple armv7-a15-linux -analyzer-checker=core,alpha.unix.StdCLibraryFunctions,debug.ExprInspection -verify -analyzer-config eagerly-assume=false %s +// RUN: %clang_analyze_cc1 -triple thumbv7-a15-linux -analyzer-checker=core,alpha.unix.StdCLibraryFunctions,debug.ExprInspection -verify -analyzer-config eagerly-assume=false %s void clang_analyzer_eval(int); diff --git a/clang/test/Analysis/std-c-library-functions-inlined.c b/clang/test/Analysis/std-c-library-functions-inlined.c index e22df14085723..e40f5204f6321 100644 --- a/clang/test/Analysis/std-c-library-functions-inlined.c +++ b/clang/test/Analysis/std-c-library-functions-inlined.c @@ -1,8 +1,8 @@ -// RUN: %clang_analyze_cc1 -analyzer-checker=apiModeling.StdCLibraryFunctions -verify %s -// RUN: %clang_analyze_cc1 -triple i686-unknown-linux -analyzer-checker=apiModeling.StdCLibraryFunctions -verify %s -// RUN: %clang_analyze_cc1 -triple x86_64-unknown-linux -analyzer-checker=apiModeling.StdCLibraryFunctions -verify %s -// RUN: %clang_analyze_cc1 -triple armv7-a15-linux -analyzer-checker=apiModeling.StdCLibraryFunctions -verify %s -// RUN: %clang_analyze_cc1 -triple thumbv7-a15-linux -analyzer-checker=apiModeling.StdCLibraryFunctions -verify %s +// RUN: %clang_analyze_cc1 -analyzer-checker=alpha.unix.StdCLibraryFunctions -verify %s +// RUN: %clang_analyze_cc1 -triple i686-unknown-linux -analyzer-checker=alpha.unix.StdCLibraryFunctions -verify %s +// RUN: %clang_analyze_cc1 -triple x86_64-unknown-linux -analyzer-checker=alpha.unix.StdCLibraryFunctions -verify %s +// RUN: %clang_analyze_cc1 -triple armv7-a15-linux -analyzer-checker=alpha.unix.StdCLibraryFunctions -verify %s +// RUN: %clang_analyze_cc1 -triple thumbv7-a15-linux -analyzer-checker=alpha.unix.StdCLibraryFunctions -verify %s // This test tests crashes that occur when standard functions are available // for inlining. diff --git a/clang/test/Analysis/std-c-library-functions-lookup.c b/clang/test/Analysis/std-c-library-functions-lookup.c index df40b1af015da..7032dca1b8baa 100644 --- a/clang/test/Analysis/std-c-library-functions-lookup.c +++ b/clang/test/Analysis/std-c-library-functions-lookup.c @@ -1,7 +1,7 @@ // RUN: %clang_analyze_cc1 %s \ // RUN: -analyzer-checker=core \ -// RUN: -analyzer-checker=apiModeling.StdCLibraryFunctions \ -// RUN: -analyzer-config apiModeling.StdCLibraryFunctions:DisplayLoadedSummaries=true \ +// RUN: -analyzer-checker=alpha.unix.StdCLibraryFunctions \ +// RUN: -analyzer-config alpha.unix.StdCLibraryFunctions:DisplayLoadedSummaries=true \ // RUN: -analyzer-checker=debug.ExprInspection \ // RUN: -analyzer-config eagerly-assume=false \ // RUN: -triple i686-unknown-linux 2>&1 | FileCheck %s diff --git a/clang/test/Analysis/std-c-library-functions-lookup.cpp b/clang/test/Analysis/std-c-library-functions-lookup.cpp index 888ab27d501fc..22778b2fdefbd 100644 --- a/clang/test/Analysis/std-c-library-functions-lookup.cpp +++ b/clang/test/Analysis/std-c-library-functions-lookup.cpp @@ -1,7 +1,7 @@ // RUN: %clang_analyze_cc1 %s \ // RUN: -analyzer-checker=core \ -// RUN: -analyzer-checker=apiModeling.StdCLibraryFunctions \ -// RUN: -analyzer-config apiModeling.StdCLibraryFunctions:DisplayLoadedSummaries=true \ +// RUN: -analyzer-checker=alpha.unix.StdCLibraryFunctions \ +// RUN: -analyzer-config alpha.unix.StdCLibraryFunctions:DisplayLoadedSummaries=true \ // RUN: -analyzer-checker=debug.ExprInspection \ // RUN: -analyzer-config eagerly-assume=false \ // RUN: -triple i686-unknown-linux 2>&1 | FileCheck %s diff --git a/clang/test/Analysis/std-c-library-functions-path-notes.c b/clang/test/Analysis/std-c-library-functions-path-notes.c index bc4e9035b15fe..98772fa6a11e5 100644 --- a/clang/test/Analysis/std-c-library-functions-path-notes.c +++ b/clang/test/Analysis/std-c-library-functions-path-notes.c @@ -1,5 +1,5 @@ // RUN: %clang_analyze_cc1 -verify %s \ -// RUN: -analyzer-checker=core,apiModeling \ +// RUN: -analyzer-checker=core,alpha.unix.StdCLibraryFunctions \ // RUN: -analyzer-output=text #define NULL ((void *)0) diff --git a/clang/test/Analysis/std-c-library-functions-restrict.c b/clang/test/Analysis/std-c-library-functions-restrict.c index 865fa0b06f86f..6260f851cdfa5 100644 --- a/clang/test/Analysis/std-c-library-functions-restrict.c +++ b/clang/test/Analysis/std-c-library-functions-restrict.c @@ -1,8 +1,8 @@ // RUN: %clang_analyze_cc1 %s \ // RUN: -analyzer-checker=core \ -// RUN: -analyzer-checker=apiModeling.StdCLibraryFunctions \ +// RUN: -analyzer-checker=alpha.unix.StdCLibraryFunctions \ // RUN: -analyzer-checker=debug.StdCLibraryFunctionsTester \ -// RUN: -analyzer-config apiModeling.StdCLibraryFunctions:DisplayLoadedSummaries=true \ +// RUN: -analyzer-config alpha.unix.StdCLibraryFunctions:DisplayLoadedSummaries=true \ // RUN: -triple i686-unknown-linux 2>&1 | FileCheck %s // The signatures for these functions are the same and they specify their diff --git a/clang/test/Analysis/std-c-library-functions-restrict.cpp b/clang/test/Analysis/std-c-library-functions-restrict.cpp index d1cd090f5ef85..e431b14b19525 100644 --- a/clang/test/Analysis/std-c-library-functions-restrict.cpp +++ b/clang/test/Analysis/std-c-library-functions-restrict.cpp @@ -1,8 +1,8 @@ // RUN: %clang_analyze_cc1 %s \ // RUN: -analyzer-checker=core \ -// RUN: -analyzer-checker=apiModeling.StdCLibraryFunctions \ +// RUN: -analyzer-checker=alpha.unix.StdCLibraryFunctions \ // RUN: -analyzer-checker=debug.StdCLibraryFunctionsTester \ -// RUN: -analyzer-config apiModeling.StdCLibraryFunctions:DisplayLoadedSummaries=true \ +// RUN: -analyzer-config alpha.unix.StdCLibraryFunctions:DisplayLoadedSummaries=true \ // RUN: -triple i686-unknown-linux 2>&1 | FileCheck %s // The signatures for these functions are the same and they specify their diff --git a/clang/test/Analysis/std-c-library-functions-vs-stream-checker.c b/clang/test/Analysis/std-c-library-functions-vs-stream-checker.c index 9e6cebd28dda8..4df46207da70d 100644 --- a/clang/test/Analysis/std-c-library-functions-vs-stream-checker.c +++ b/clang/test/Analysis/std-c-library-functions-vs-stream-checker.c @@ -8,8 +8,8 @@ // Check the case when only the StdLibraryFunctionsChecker is enabled. // RUN: %clang_analyze_cc1 %s \ -// RUN: -analyzer-checker=apiModeling.StdCLibraryFunctions \ -// RUN: -analyzer-config apiModeling.StdCLibraryFunctions:DisplayLoadedSummaries=true \ +// RUN: -analyzer-checker=alpha.unix.StdCLibraryFunctions \ +// RUN: -analyzer-config alpha.unix.StdCLibraryFunctions:DisplayLoadedSummaries=true \ // RUN: -analyzer-checker=debug.ExprInspection \ // RUN: -analyzer-config eagerly-assume=false \ // RUN: -triple x86_64-unknown-linux \ @@ -19,8 +19,8 @@ // StdLibraryFunctionsChecker are enabled. // RUN: %clang_analyze_cc1 %s \ // RUN: -analyzer-checker=core,alpha.unix.Stream \ -// RUN: -analyzer-checker=apiModeling.StdCLibraryFunctions \ -// RUN: -analyzer-config apiModeling.StdCLibraryFunctions:DisplayLoadedSummaries=true \ +// RUN: -analyzer-checker=alpha.unix.StdCLibraryFunctions \ +// RUN: -analyzer-config alpha.unix.StdCLibraryFunctions:DisplayLoadedSummaries=true \ // RUN: -analyzer-checker=debug.ExprInspection \ // RUN: -analyzer-config eagerly-assume=false \ // RUN: -triple x86_64-unknown-linux \ diff --git a/clang/test/Analysis/std-c-library-functions.c b/clang/test/Analysis/std-c-library-functions.c index 419f98b7a6bbb..392784722d385 100644 --- a/clang/test/Analysis/std-c-library-functions.c +++ b/clang/test/Analysis/std-c-library-functions.c @@ -1,6 +1,6 @@ // RUN: %clang_analyze_cc1 %s \ // RUN: -analyzer-checker=core \ -// RUN: -analyzer-checker=apiModeling.StdCLibraryFunctions \ +// RUN: -analyzer-checker=alpha.unix.StdCLibraryFunctions \ // RUN: -analyzer-checker=debug.ExprInspection \ // RUN: -analyzer-config eagerly-assume=false \ // RUN: -triple i686-unknown-linux \ @@ -8,7 +8,7 @@ // RUN: %clang_analyze_cc1 %s \ // RUN: -analyzer-checker=core \ -// RUN: -analyzer-checker=apiModeling.StdCLibraryFunctions \ +// RUN: -analyzer-checker=alpha.unix.StdCLibraryFunctions \ // RUN: -analyzer-checker=debug.ExprInspection \ // RUN: -analyzer-config eagerly-assume=false \ // RUN: -triple x86_64-unknown-linux \ @@ -16,7 +16,7 @@ // RUN: %clang_analyze_cc1 %s \ // RUN: -analyzer-checker=core \ -// RUN: -analyzer-checker=apiModeling.StdCLibraryFunctions \ +// RUN: -analyzer-checker=alpha.unix.StdCLibraryFunctions \ // RUN: -analyzer-checker=debug.ExprInspection \ // RUN: -analyzer-config eagerly-assume=false \ // RUN: -triple armv7-a15-linux \ @@ -24,7 +24,7 @@ // RUN: %clang_analyze_cc1 %s \ // RUN: -analyzer-checker=core \ -// RUN: -analyzer-checker=apiModeling.StdCLibraryFunctions \ +// RUN: -analyzer-checker=alpha.unix.StdCLibraryFunctions \ // RUN: -analyzer-checker=debug.ExprInspection \ // RUN: -analyzer-config eagerly-assume=false \ // RUN: -triple thumbv7-a15-linux \ @@ -32,8 +32,8 @@ // RUN: %clang_analyze_cc1 %s \ // RUN: -analyzer-checker=core \ -// RUN: -analyzer-checker=apiModeling.StdCLibraryFunctions \ -// RUN: -analyzer-config apiModeling.StdCLibraryFunctions:DisplayLoadedSummaries=true \ +// RUN: -analyzer-checker=alpha.unix.StdCLibraryFunctions \ +// RUN: -analyzer-config alpha.unix.StdCLibraryFunctions:DisplayLoadedSummaries=true \ // RUN: -analyzer-checker=debug.ExprInspection \ // RUN: -analyzer-config eagerly-assume=false \ // RUN: -triple i686-unknown-linux 2>&1 | FileCheck %s diff --git a/clang/test/Analysis/std-c-library-functions.cpp b/clang/test/Analysis/std-c-library-functions.cpp index 87f84fa881186..2da01d6351997 100644 --- a/clang/test/Analysis/std-c-library-functions.cpp +++ b/clang/test/Analysis/std-c-library-functions.cpp @@ -1,4 +1,4 @@ -// RUN: %clang_analyze_cc1 -triple x86_64-unknown-linux -analyzer-checker=apiModeling.StdCLibraryFunctions,debug.ExprInspection -verify %s +// RUN: %clang_analyze_cc1 -triple x86_64-unknown-linux -analyzer-checker=alpha.unix.StdCLibraryFunctions,debug.ExprInspection -verify %s // Test that we don't model functions with broken prototypes. // Because they probably work differently as well. diff --git a/clang/test/Analysis/std-c-library-posix-crash.c b/clang/test/Analysis/std-c-library-posix-crash.c index 23321d548d6d8..66e7bf4656b34 100644 --- a/clang/test/Analysis/std-c-library-posix-crash.c +++ b/clang/test/Analysis/std-c-library-posix-crash.c @@ -1,6 +1,6 @@ // RUN: %clang_analyze_cc1 \ -// RUN: -analyzer-checker=core,apiModeling.StdCLibraryFunctions \ -// RUN: -analyzer-config apiModeling.StdCLibraryFunctions:ModelPOSIX=true \ +// RUN: -analyzer-checker=core,alpha.unix.StdCLibraryFunctions \ +// RUN: -analyzer-config alpha.unix.StdCLibraryFunctions:ModelPOSIX=true \ // RUN: -verify %s // // expected-no-diagnostics diff --git a/clang/test/Analysis/stream-errno-note.c b/clang/test/Analysis/stream-errno-note.c index 87b052bda1c0a..111841efe0e5a 100644 --- a/clang/test/Analysis/stream-errno-note.c +++ b/clang/test/Analysis/stream-errno-note.c @@ -1,8 +1,8 @@ // RUN: %clang_analyze_cc1 -analyzer-checker=core \ // RUN: -analyzer-checker=alpha.unix.Stream \ // RUN: -analyzer-checker=alpha.unix.Errno \ -// RUN: -analyzer-checker=apiModeling.StdCLibraryFunctions \ -// RUN: -analyzer-config apiModeling.StdCLibraryFunctions:ModelPOSIX=true \ +// RUN: -analyzer-checker=alpha.unix.StdCLibraryFunctions \ +// RUN: -analyzer-config alpha.unix.StdCLibraryFunctions:ModelPOSIX=true \ // RUN: -analyzer-output text -verify %s #include "Inputs/system-header-simulator.h" diff --git a/clang/test/Analysis/stream-errno.c b/clang/test/Analysis/stream-errno.c index 42369677eaa48..d8c0c8223ad20 100644 --- a/clang/test/Analysis/stream-errno.c +++ b/clang/test/Analysis/stream-errno.c @@ -1,5 +1,5 @@ -// RUN: %clang_analyze_cc1 -analyzer-checker=core,alpha.unix.Stream,alpha.unix.Errno,apiModeling.StdCLibraryFunctions,debug.ExprInspection \ -// RUN: -analyzer-config apiModeling.StdCLibraryFunctions:ModelPOSIX=true -verify %s +// RUN: %clang_analyze_cc1 -analyzer-checker=core,alpha.unix.Stream,alpha.unix.Errno,alpha.unix.StdCLibraryFunctions,debug.ExprInspection \ +// RUN: -analyzer-config alpha.unix.StdCLibraryFunctions:ModelPOSIX=true -verify %s #include "Inputs/system-header-simulator.h" #include "Inputs/errno_func.h" diff --git a/clang/test/Analysis/stream-noopen.c b/clang/test/Analysis/stream-noopen.c index bc1d768987f76..03784603d9fcc 100644 --- a/clang/test/Analysis/stream-noopen.c +++ b/clang/test/Analysis/stream-noopen.c @@ -2,16 +2,16 @@ // RUN: -analyzer-checker=core \ // RUN: -analyzer-checker=alpha.unix.Errno \ // RUN: -analyzer-checker=alpha.unix.Stream \ -// RUN: -analyzer-checker=apiModeling.StdCLibraryFunctions \ -// RUN: -analyzer-config apiModeling.StdCLibraryFunctions:ModelPOSIX=true \ +// RUN: -analyzer-checker=alpha.unix.StdCLibraryFunctions \ +// RUN: -analyzer-config alpha.unix.StdCLibraryFunctions:ModelPOSIX=true \ // RUN: -analyzer-checker=debug.ExprInspection // enable only StdCLibraryFunctions checker // RUN: %clang_analyze_cc1 -verify %s \ // RUN: -analyzer-checker=core \ // RUN: -analyzer-checker=alpha.unix.Errno \ -// RUN: -analyzer-checker=apiModeling.StdCLibraryFunctions \ -// RUN: -analyzer-config apiModeling.StdCLibraryFunctions:ModelPOSIX=true \ +// RUN: -analyzer-checker=alpha.unix.StdCLibraryFunctions \ +// RUN: -analyzer-config alpha.unix.StdCLibraryFunctions:ModelPOSIX=true \ // RUN: -analyzer-checker=debug.ExprInspection #include "Inputs/system-header-simulator.h" diff --git a/clang/test/Analysis/stream-note.c b/clang/test/Analysis/stream-note.c index 199d208cbde82..61dd17446da43 100644 --- a/clang/test/Analysis/stream-note.c +++ b/clang/test/Analysis/stream-note.c @@ -1,7 +1,7 @@ // RUN: %clang_analyze_cc1 -analyzer-checker=core,alpha.unix.Stream -analyzer-output text \ // RUN: -verify %s -// RUN: %clang_analyze_cc1 -analyzer-checker=core,alpha.unix.Stream,alpha.unix.StdCLibraryFunctionArgs -analyzer-output text \ -// RUN: -analyzer-config apiModeling.StdCLibraryFunctions:ModelPOSIX=true -verify=expected,stdargs %s +// RUN: %clang_analyze_cc1 -analyzer-checker=core,alpha.unix.Stream,alpha.unix.StdCLibraryFunctions -analyzer-output text \ +// RUN: -analyzer-config alpha.unix.StdCLibraryFunctions:ModelPOSIX=true -verify=expected,stdargs %s #include "Inputs/system-header-simulator.h" diff --git a/clang/test/Analysis/stream-stdlibraryfunctionargs.c b/clang/test/Analysis/stream-stdlibraryfunctionargs.c index 6b4a6d10a8f61..6180b30ae1788 100644 --- a/clang/test/Analysis/stream-stdlibraryfunctionargs.c +++ b/clang/test/Analysis/stream-stdlibraryfunctionargs.c @@ -1,11 +1,11 @@ -// RUN: %clang_analyze_cc1 -analyzer-checker=core,alpha.unix.Stream,alpha.unix.StdCLibraryFunctionArgs,debug.ExprInspection \ -// RUN: -analyzer-config apiModeling.StdCLibraryFunctions:ModelPOSIX=true -verify=stdargs,any %s +// RUN: %clang_analyze_cc1 -analyzer-checker=core,alpha.unix.Stream,alpha.unix.StdCLibraryFunctions,debug.ExprInspection \ +// RUN: -analyzer-config alpha.unix.StdCLibraryFunctions:ModelPOSIX=true -verify=stdargs,any %s // RUN: %clang_analyze_cc1 -analyzer-checker=core,alpha.unix.Stream,debug.ExprInspection \ -// RUN: -analyzer-config apiModeling.StdCLibraryFunctions:ModelPOSIX=true -verify=any %s +// RUN: -analyzer-config alpha.unix.StdCLibraryFunctions:ModelPOSIX=true -verify=any %s -// RUN: %clang_analyze_cc1 -analyzer-checker=core,alpha.unix.StdCLibraryFunctionArgs,debug.ExprInspection \ -// RUN: -analyzer-config apiModeling.StdCLibraryFunctions:ModelPOSIX=true -verify=stdargs,any %s +// RUN: %clang_analyze_cc1 -analyzer-checker=core,alpha.unix.StdCLibraryFunctions,debug.ExprInspection \ +// RUN: -analyzer-config alpha.unix.StdCLibraryFunctions:ModelPOSIX=true -verify=stdargs,any %s #include "Inputs/system-header-simulator.h" diff --git a/clang/test/Analysis/weak-dependencies.c b/clang/test/Analysis/weak-dependencies.c index 62cb10b5b5235..9946af8f4dfae 100644 --- a/clang/test/Analysis/weak-dependencies.c +++ b/clang/test/Analysis/weak-dependencies.c @@ -1,5 +1,5 @@ // RUN: %clang_analyze_cc1 %s -verify \ -// RUN: -analyzer-checker=alpha.unix.StdCLibraryFunctionArgs \ +// RUN: -analyzer-checker=alpha.unix.StdCLibraryFunctions \ // RUN: -analyzer-checker=core typedef __typeof(sizeof(int)) size_t; diff --git a/clang/test/CXX/drs/dr13xx.cpp b/clang/test/CXX/drs/dr13xx.cpp index 65eb8a293276f..feaf523c44fc2 100644 --- a/clang/test/CXX/drs/dr13xx.cpp +++ b/clang/test/CXX/drs/dr13xx.cpp @@ -480,6 +480,23 @@ namespace dr1395 { // dr1395: 16 #endif } +namespace dr1397 { // dr1397: 3.2 +#if __cplusplus >= 201103L +struct A { // #dr1397-struct-A + void *p = A{}; // #dr1397-void-p +#if __cplusplus == 201103L + // expected-error@#dr1397-struct-A {{default member initializer for 'p' needed within definition of enclosing class 'A' outside of member functions}} + // expected-note@#dr1397-void-p {{in evaluation of exception specification for 'dr1397::A::A' needed here}} + // expected-note@#dr1397-void-p {{default member initializer declared here}} +#elif __cplusplus >= 201402L + // expected-error@#dr1397-void-p {{default member initializer for 'p' needed within definition of enclosing class 'A' outside of member functions}} + // expected-note@#dr1397-void-p {{default member initializer declared here}} +#endif + operator void*() const { return nullptr; } +}; +#endif +} // namespace dr1397 + namespace dr1399 { // dr1399: dup 1388 template void f(T..., int, T...) {} // expected-note {{candidate}} expected-error 0-1{{C++11}} void g() { diff --git a/clang/test/CXX/drs/dr6xx.cpp b/clang/test/CXX/drs/dr6xx.cpp index 59331e7de7687..a08f55dd562a4 100644 --- a/clang/test/CXX/drs/dr6xx.cpp +++ b/clang/test/CXX/drs/dr6xx.cpp @@ -234,7 +234,7 @@ namespace dr619 { // dr619: yes // dr620: dup 568 -namespace dr621 { +namespace dr621 { // dr621: yes template T f(); template<> int f() {} // expected-note {{previous}} template<> int f() {} // expected-error {{redefinition}} diff --git a/clang/test/CXX/drs/dr8xx.cpp b/clang/test/CXX/drs/dr8xx.cpp new file mode 100644 index 0000000000000..d79430f9e03ca --- /dev/null +++ b/clang/test/CXX/drs/dr8xx.cpp @@ -0,0 +1,30 @@ +// RUN: %clang_cc1 -std=c++98 -triple x86_64-unknown-unknown %s -verify -fexceptions -fcxx-exceptions -pedantic-errors +// RUN: %clang_cc1 -std=c++11 -triple x86_64-unknown-unknown %s -verify -fexceptions -fcxx-exceptions -pedantic-errors 2>&1 | FileCheck %s +// RUN: %clang_cc1 -std=c++14 -triple x86_64-unknown-unknown %s -verify -fexceptions -fcxx-exceptions -pedantic-errors 2>&1 | FileCheck %s +// RUN: %clang_cc1 -std=c++17 -triple x86_64-unknown-unknown %s -verify -fexceptions -fcxx-exceptions -pedantic-errors 2>&1 | FileCheck %s +// RUN: %clang_cc1 -std=c++20 -triple x86_64-unknown-unknown %s -verify -fexceptions -fcxx-exceptions -pedantic-errors 2>&1 | FileCheck %s +// RUN: %clang_cc1 -std=c++23 -triple x86_64-unknown-unknown %s -verify -fexceptions -fcxx-exceptions -pedantic-errors 2>&1 | FileCheck %s +// RUN: %clang_cc1 -std=c++2c -triple x86_64-unknown-unknown %s -verify -fexceptions -fcxx-exceptions -pedantic-errors 2>&1 | FileCheck %s + +// expected-no-diagnostics + +namespace dr873 { // dr873: yes +#if __cplusplus >= 201103L +template void f(T &&); +template <> void f(int &) {} // #1 +template <> void f(int &&) {} // #2 +void g(int i) { + f(i); // calls f(int&), i.e., #1 +#pragma clang __debug dump f(i) + // CHECK: CallExpr {{.*}} + // CHECK-NEXT: |-ImplicitCastExpr {{.*}} + // CHECK-NEXT: | `-DeclRefExpr {{.*}} 'f' 'void (int &)' {{.*}} + + f(0); // calls f(int&&), i.e., #2 +#pragma clang __debug dump f(0) + // CHECK: CallExpr {{.*}} + // CHECK-NEXT: |-ImplicitCastExpr {{.*}} + // CHECK-NEXT: | `-DeclRefExpr {{.*}} 'f' 'void (int &&)' {{.*}} +} +#endif +} // namespace dr873 diff --git a/clang/test/CXX/drs/dr9xx.cpp b/clang/test/CXX/drs/dr9xx.cpp index 4dfb98e5ec11e..fb13ef2967f88 100644 --- a/clang/test/CXX/drs/dr9xx.cpp +++ b/clang/test/CXX/drs/dr9xx.cpp @@ -92,7 +92,7 @@ namespace dr974 { // dr974: yes namespace dr977 { // dr977: yes enum E { e = E() }; -#ifndef _WIN32 +#if !defined(_WIN32) || defined(__MINGW32__) // expected-error@-2 {{invalid use of incomplete type 'E'}} // expected-note@-3 {{definition of 'dr977::E' is not complete until the closing '}'}} #endif diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vid.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vid.c index 6e67ba57d4999..ae74ff8a7a7d6 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vid.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vid.c @@ -666,3 +666,223 @@ vuint64m8_t test_vid_v_u64m8_tumu(vbool8_t mask, vuint64m8_t maskedoff, size_t v return __riscv_vid_tumu(mask, maskedoff, vl); } +// CHECK-RV64-LABEL: define dso_local @test_vid_v_u8mf8_mu +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[MASKEDOFF:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vid.mask.nxv1i8.i64( [[MASKEDOFF]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint8mf8_t test_vid_v_u8mf8_mu(vbool64_t mask, vuint8mf8_t maskedoff, size_t vl) { + return __riscv_vid_mu(mask, maskedoff, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vid_v_u8mf4_mu +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[MASKEDOFF:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vid.mask.nxv2i8.i64( [[MASKEDOFF]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint8mf4_t test_vid_v_u8mf4_mu(vbool32_t mask, vuint8mf4_t maskedoff, size_t vl) { + return __riscv_vid_mu(mask, maskedoff, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vid_v_u8mf2_mu +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[MASKEDOFF:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vid.mask.nxv4i8.i64( [[MASKEDOFF]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint8mf2_t test_vid_v_u8mf2_mu(vbool16_t mask, vuint8mf2_t maskedoff, size_t vl) { + return __riscv_vid_mu(mask, maskedoff, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vid_v_u8m1_mu +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[MASKEDOFF:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vid.mask.nxv8i8.i64( [[MASKEDOFF]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint8m1_t test_vid_v_u8m1_mu(vbool8_t mask, vuint8m1_t maskedoff, size_t vl) { + return __riscv_vid_mu(mask, maskedoff, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vid_v_u8m2_mu +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[MASKEDOFF:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vid.mask.nxv16i8.i64( [[MASKEDOFF]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint8m2_t test_vid_v_u8m2_mu(vbool4_t mask, vuint8m2_t maskedoff, size_t vl) { + return __riscv_vid_mu(mask, maskedoff, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vid_v_u8m4_mu +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[MASKEDOFF:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vid.mask.nxv32i8.i64( [[MASKEDOFF]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint8m4_t test_vid_v_u8m4_mu(vbool2_t mask, vuint8m4_t maskedoff, size_t vl) { + return __riscv_vid_mu(mask, maskedoff, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vid_v_u8m8_mu +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[MASKEDOFF:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vid.mask.nxv64i8.i64( [[MASKEDOFF]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint8m8_t test_vid_v_u8m8_mu(vbool1_t mask, vuint8m8_t maskedoff, size_t vl) { + return __riscv_vid_mu(mask, maskedoff, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vid_v_u16mf4_mu +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[MASKEDOFF:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vid.mask.nxv1i16.i64( [[MASKEDOFF]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint16mf4_t test_vid_v_u16mf4_mu(vbool64_t mask, vuint16mf4_t maskedoff, size_t vl) { + return __riscv_vid_mu(mask, maskedoff, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vid_v_u16mf2_mu +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[MASKEDOFF:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vid.mask.nxv2i16.i64( [[MASKEDOFF]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint16mf2_t test_vid_v_u16mf2_mu(vbool32_t mask, vuint16mf2_t maskedoff, size_t vl) { + return __riscv_vid_mu(mask, maskedoff, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vid_v_u16m1_mu +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[MASKEDOFF:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vid.mask.nxv4i16.i64( [[MASKEDOFF]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint16m1_t test_vid_v_u16m1_mu(vbool16_t mask, vuint16m1_t maskedoff, size_t vl) { + return __riscv_vid_mu(mask, maskedoff, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vid_v_u16m2_mu +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[MASKEDOFF:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vid.mask.nxv8i16.i64( [[MASKEDOFF]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint16m2_t test_vid_v_u16m2_mu(vbool8_t mask, vuint16m2_t maskedoff, size_t vl) { + return __riscv_vid_mu(mask, maskedoff, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vid_v_u16m4_mu +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[MASKEDOFF:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vid.mask.nxv16i16.i64( [[MASKEDOFF]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint16m4_t test_vid_v_u16m4_mu(vbool4_t mask, vuint16m4_t maskedoff, size_t vl) { + return __riscv_vid_mu(mask, maskedoff, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vid_v_u16m8_mu +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[MASKEDOFF:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vid.mask.nxv32i16.i64( [[MASKEDOFF]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint16m8_t test_vid_v_u16m8_mu(vbool2_t mask, vuint16m8_t maskedoff, size_t vl) { + return __riscv_vid_mu(mask, maskedoff, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vid_v_u32mf2_mu +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[MASKEDOFF:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vid.mask.nxv1i32.i64( [[MASKEDOFF]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint32mf2_t test_vid_v_u32mf2_mu(vbool64_t mask, vuint32mf2_t maskedoff, size_t vl) { + return __riscv_vid_mu(mask, maskedoff, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vid_v_u32m1_mu +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[MASKEDOFF:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vid.mask.nxv2i32.i64( [[MASKEDOFF]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint32m1_t test_vid_v_u32m1_mu(vbool32_t mask, vuint32m1_t maskedoff, size_t vl) { + return __riscv_vid_mu(mask, maskedoff, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vid_v_u32m2_mu +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[MASKEDOFF:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vid.mask.nxv4i32.i64( [[MASKEDOFF]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint32m2_t test_vid_v_u32m2_mu(vbool16_t mask, vuint32m2_t maskedoff, size_t vl) { + return __riscv_vid_mu(mask, maskedoff, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vid_v_u32m4_mu +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[MASKEDOFF:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vid.mask.nxv8i32.i64( [[MASKEDOFF]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint32m4_t test_vid_v_u32m4_mu(vbool8_t mask, vuint32m4_t maskedoff, size_t vl) { + return __riscv_vid_mu(mask, maskedoff, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vid_v_u32m8_mu +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[MASKEDOFF:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vid.mask.nxv16i32.i64( [[MASKEDOFF]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint32m8_t test_vid_v_u32m8_mu(vbool4_t mask, vuint32m8_t maskedoff, size_t vl) { + return __riscv_vid_mu(mask, maskedoff, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vid_v_u64m1_mu +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[MASKEDOFF:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vid.mask.nxv1i64.i64( [[MASKEDOFF]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint64m1_t test_vid_v_u64m1_mu(vbool64_t mask, vuint64m1_t maskedoff, size_t vl) { + return __riscv_vid_mu(mask, maskedoff, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vid_v_u64m2_mu +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[MASKEDOFF:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vid.mask.nxv2i64.i64( [[MASKEDOFF]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint64m2_t test_vid_v_u64m2_mu(vbool32_t mask, vuint64m2_t maskedoff, size_t vl) { + return __riscv_vid_mu(mask, maskedoff, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vid_v_u64m4_mu +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[MASKEDOFF:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vid.mask.nxv4i64.i64( [[MASKEDOFF]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint64m4_t test_vid_v_u64m4_mu(vbool16_t mask, vuint64m4_t maskedoff, size_t vl) { + return __riscv_vid_mu(mask, maskedoff, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vid_v_u64m8_mu +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[MASKEDOFF:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vid.mask.nxv8i64.i64( [[MASKEDOFF]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint64m8_t test_vid_v_u64m8_mu(vbool8_t mask, vuint64m8_t maskedoff, size_t vl) { + return __riscv_vid_mu(mask, maskedoff, vl); +} + diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/viota.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/viota.c index 8d247cc20798f..a721cba3ea7e2 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/viota.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/viota.c @@ -666,3 +666,223 @@ vuint64m8_t test_viota_m_u64m8_tumu(vbool8_t mask, vuint64m8_t maskedoff, vbool8 return __riscv_viota_tumu(mask, maskedoff, op1, vl); } +// CHECK-RV64-LABEL: define dso_local @test_viota_m_u8mf8_mu +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[MASKEDOFF:%.*]], [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.viota.mask.nxv1i8.i64( [[MASKEDOFF]], [[OP1]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint8mf8_t test_viota_m_u8mf8_mu(vbool64_t mask, vuint8mf8_t maskedoff, vbool64_t op1, size_t vl) { + return __riscv_viota_mu(mask, maskedoff, op1, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_viota_m_u8mf4_mu +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[MASKEDOFF:%.*]], [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.viota.mask.nxv2i8.i64( [[MASKEDOFF]], [[OP1]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint8mf4_t test_viota_m_u8mf4_mu(vbool32_t mask, vuint8mf4_t maskedoff, vbool32_t op1, size_t vl) { + return __riscv_viota_mu(mask, maskedoff, op1, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_viota_m_u8mf2_mu +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[MASKEDOFF:%.*]], [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.viota.mask.nxv4i8.i64( [[MASKEDOFF]], [[OP1]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint8mf2_t test_viota_m_u8mf2_mu(vbool16_t mask, vuint8mf2_t maskedoff, vbool16_t op1, size_t vl) { + return __riscv_viota_mu(mask, maskedoff, op1, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_viota_m_u8m1_mu +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[MASKEDOFF:%.*]], [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.viota.mask.nxv8i8.i64( [[MASKEDOFF]], [[OP1]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint8m1_t test_viota_m_u8m1_mu(vbool8_t mask, vuint8m1_t maskedoff, vbool8_t op1, size_t vl) { + return __riscv_viota_mu(mask, maskedoff, op1, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_viota_m_u8m2_mu +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[MASKEDOFF:%.*]], [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.viota.mask.nxv16i8.i64( [[MASKEDOFF]], [[OP1]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint8m2_t test_viota_m_u8m2_mu(vbool4_t mask, vuint8m2_t maskedoff, vbool4_t op1, size_t vl) { + return __riscv_viota_mu(mask, maskedoff, op1, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_viota_m_u8m4_mu +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[MASKEDOFF:%.*]], [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.viota.mask.nxv32i8.i64( [[MASKEDOFF]], [[OP1]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint8m4_t test_viota_m_u8m4_mu(vbool2_t mask, vuint8m4_t maskedoff, vbool2_t op1, size_t vl) { + return __riscv_viota_mu(mask, maskedoff, op1, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_viota_m_u8m8_mu +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[MASKEDOFF:%.*]], [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.viota.mask.nxv64i8.i64( [[MASKEDOFF]], [[OP1]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint8m8_t test_viota_m_u8m8_mu(vbool1_t mask, vuint8m8_t maskedoff, vbool1_t op1, size_t vl) { + return __riscv_viota_mu(mask, maskedoff, op1, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_viota_m_u16mf4_mu +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[MASKEDOFF:%.*]], [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.viota.mask.nxv1i16.i64( [[MASKEDOFF]], [[OP1]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint16mf4_t test_viota_m_u16mf4_mu(vbool64_t mask, vuint16mf4_t maskedoff, vbool64_t op1, size_t vl) { + return __riscv_viota_mu(mask, maskedoff, op1, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_viota_m_u16mf2_mu +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[MASKEDOFF:%.*]], [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.viota.mask.nxv2i16.i64( [[MASKEDOFF]], [[OP1]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint16mf2_t test_viota_m_u16mf2_mu(vbool32_t mask, vuint16mf2_t maskedoff, vbool32_t op1, size_t vl) { + return __riscv_viota_mu(mask, maskedoff, op1, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_viota_m_u16m1_mu +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[MASKEDOFF:%.*]], [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.viota.mask.nxv4i16.i64( [[MASKEDOFF]], [[OP1]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint16m1_t test_viota_m_u16m1_mu(vbool16_t mask, vuint16m1_t maskedoff, vbool16_t op1, size_t vl) { + return __riscv_viota_mu(mask, maskedoff, op1, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_viota_m_u16m2_mu +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[MASKEDOFF:%.*]], [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.viota.mask.nxv8i16.i64( [[MASKEDOFF]], [[OP1]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint16m2_t test_viota_m_u16m2_mu(vbool8_t mask, vuint16m2_t maskedoff, vbool8_t op1, size_t vl) { + return __riscv_viota_mu(mask, maskedoff, op1, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_viota_m_u16m4_mu +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[MASKEDOFF:%.*]], [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.viota.mask.nxv16i16.i64( [[MASKEDOFF]], [[OP1]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint16m4_t test_viota_m_u16m4_mu(vbool4_t mask, vuint16m4_t maskedoff, vbool4_t op1, size_t vl) { + return __riscv_viota_mu(mask, maskedoff, op1, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_viota_m_u16m8_mu +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[MASKEDOFF:%.*]], [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.viota.mask.nxv32i16.i64( [[MASKEDOFF]], [[OP1]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint16m8_t test_viota_m_u16m8_mu(vbool2_t mask, vuint16m8_t maskedoff, vbool2_t op1, size_t vl) { + return __riscv_viota_mu(mask, maskedoff, op1, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_viota_m_u32mf2_mu +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[MASKEDOFF:%.*]], [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.viota.mask.nxv1i32.i64( [[MASKEDOFF]], [[OP1]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint32mf2_t test_viota_m_u32mf2_mu(vbool64_t mask, vuint32mf2_t maskedoff, vbool64_t op1, size_t vl) { + return __riscv_viota_mu(mask, maskedoff, op1, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_viota_m_u32m1_mu +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[MASKEDOFF:%.*]], [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.viota.mask.nxv2i32.i64( [[MASKEDOFF]], [[OP1]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint32m1_t test_viota_m_u32m1_mu(vbool32_t mask, vuint32m1_t maskedoff, vbool32_t op1, size_t vl) { + return __riscv_viota_mu(mask, maskedoff, op1, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_viota_m_u32m2_mu +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[MASKEDOFF:%.*]], [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.viota.mask.nxv4i32.i64( [[MASKEDOFF]], [[OP1]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint32m2_t test_viota_m_u32m2_mu(vbool16_t mask, vuint32m2_t maskedoff, vbool16_t op1, size_t vl) { + return __riscv_viota_mu(mask, maskedoff, op1, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_viota_m_u32m4_mu +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[MASKEDOFF:%.*]], [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.viota.mask.nxv8i32.i64( [[MASKEDOFF]], [[OP1]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint32m4_t test_viota_m_u32m4_mu(vbool8_t mask, vuint32m4_t maskedoff, vbool8_t op1, size_t vl) { + return __riscv_viota_mu(mask, maskedoff, op1, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_viota_m_u32m8_mu +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[MASKEDOFF:%.*]], [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.viota.mask.nxv16i32.i64( [[MASKEDOFF]], [[OP1]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint32m8_t test_viota_m_u32m8_mu(vbool4_t mask, vuint32m8_t maskedoff, vbool4_t op1, size_t vl) { + return __riscv_viota_mu(mask, maskedoff, op1, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_viota_m_u64m1_mu +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[MASKEDOFF:%.*]], [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.viota.mask.nxv1i64.i64( [[MASKEDOFF]], [[OP1]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint64m1_t test_viota_m_u64m1_mu(vbool64_t mask, vuint64m1_t maskedoff, vbool64_t op1, size_t vl) { + return __riscv_viota_mu(mask, maskedoff, op1, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_viota_m_u64m2_mu +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[MASKEDOFF:%.*]], [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.viota.mask.nxv2i64.i64( [[MASKEDOFF]], [[OP1]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint64m2_t test_viota_m_u64m2_mu(vbool32_t mask, vuint64m2_t maskedoff, vbool32_t op1, size_t vl) { + return __riscv_viota_mu(mask, maskedoff, op1, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_viota_m_u64m4_mu +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[MASKEDOFF:%.*]], [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.viota.mask.nxv4i64.i64( [[MASKEDOFF]], [[OP1]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint64m4_t test_viota_m_u64m4_mu(vbool16_t mask, vuint64m4_t maskedoff, vbool16_t op1, size_t vl) { + return __riscv_viota_mu(mask, maskedoff, op1, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_viota_m_u64m8_mu +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[MASKEDOFF:%.*]], [[OP1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.viota.mask.nxv8i64.i64( [[MASKEDOFF]], [[OP1]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint64m8_t test_viota_m_u64m8_mu(vbool8_t mask, vuint64m8_t maskedoff, vbool8_t op1, size_t vl) { + return __riscv_viota_mu(mask, maskedoff, op1, vl); +} + diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle16.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle16.c index 82ababc30cb75..74fa4f8a57a96 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle16.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle16.c @@ -547,3 +547,183 @@ vuint16m8_t test_vle16_v_u16m8_tumu(vbool2_t mask, vuint16m8_t maskedoff, const return __riscv_vle16_tumu(mask, maskedoff, base, vl); } +// CHECK-RV64-LABEL: define dso_local @test_vle16_v_f16mf4_mu +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[MASKEDOFF:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vle.mask.nxv1f16.i64( [[MASKEDOFF]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vfloat16mf4_t test_vle16_v_f16mf4_mu(vbool64_t mask, vfloat16mf4_t maskedoff, const _Float16 *base, size_t vl) { + return __riscv_vle16_mu(mask, maskedoff, base, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vle16_v_f16mf2_mu +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[MASKEDOFF:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vle.mask.nxv2f16.i64( [[MASKEDOFF]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vfloat16mf2_t test_vle16_v_f16mf2_mu(vbool32_t mask, vfloat16mf2_t maskedoff, const _Float16 *base, size_t vl) { + return __riscv_vle16_mu(mask, maskedoff, base, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vle16_v_f16m1_mu +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[MASKEDOFF:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vle.mask.nxv4f16.i64( [[MASKEDOFF]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vfloat16m1_t test_vle16_v_f16m1_mu(vbool16_t mask, vfloat16m1_t maskedoff, const _Float16 *base, size_t vl) { + return __riscv_vle16_mu(mask, maskedoff, base, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vle16_v_f16m2_mu +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[MASKEDOFF:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vle.mask.nxv8f16.i64( [[MASKEDOFF]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vfloat16m2_t test_vle16_v_f16m2_mu(vbool8_t mask, vfloat16m2_t maskedoff, const _Float16 *base, size_t vl) { + return __riscv_vle16_mu(mask, maskedoff, base, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vle16_v_f16m4_mu +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[MASKEDOFF:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vle.mask.nxv16f16.i64( [[MASKEDOFF]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vfloat16m4_t test_vle16_v_f16m4_mu(vbool4_t mask, vfloat16m4_t maskedoff, const _Float16 *base, size_t vl) { + return __riscv_vle16_mu(mask, maskedoff, base, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vle16_v_f16m8_mu +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[MASKEDOFF:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vle.mask.nxv32f16.i64( [[MASKEDOFF]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vfloat16m8_t test_vle16_v_f16m8_mu(vbool2_t mask, vfloat16m8_t maskedoff, const _Float16 *base, size_t vl) { + return __riscv_vle16_mu(mask, maskedoff, base, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vle16_v_i16mf4_mu +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[MASKEDOFF:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vle.mask.nxv1i16.i64( [[MASKEDOFF]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint16mf4_t test_vle16_v_i16mf4_mu(vbool64_t mask, vint16mf4_t maskedoff, const int16_t *base, size_t vl) { + return __riscv_vle16_mu(mask, maskedoff, base, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vle16_v_i16mf2_mu +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[MASKEDOFF:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vle.mask.nxv2i16.i64( [[MASKEDOFF]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint16mf2_t test_vle16_v_i16mf2_mu(vbool32_t mask, vint16mf2_t maskedoff, const int16_t *base, size_t vl) { + return __riscv_vle16_mu(mask, maskedoff, base, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vle16_v_i16m1_mu +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[MASKEDOFF:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vle.mask.nxv4i16.i64( [[MASKEDOFF]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint16m1_t test_vle16_v_i16m1_mu(vbool16_t mask, vint16m1_t maskedoff, const int16_t *base, size_t vl) { + return __riscv_vle16_mu(mask, maskedoff, base, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vle16_v_i16m2_mu +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[MASKEDOFF:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vle.mask.nxv8i16.i64( [[MASKEDOFF]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint16m2_t test_vle16_v_i16m2_mu(vbool8_t mask, vint16m2_t maskedoff, const int16_t *base, size_t vl) { + return __riscv_vle16_mu(mask, maskedoff, base, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vle16_v_i16m4_mu +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[MASKEDOFF:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vle.mask.nxv16i16.i64( [[MASKEDOFF]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint16m4_t test_vle16_v_i16m4_mu(vbool4_t mask, vint16m4_t maskedoff, const int16_t *base, size_t vl) { + return __riscv_vle16_mu(mask, maskedoff, base, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vle16_v_i16m8_mu +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[MASKEDOFF:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vle.mask.nxv32i16.i64( [[MASKEDOFF]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint16m8_t test_vle16_v_i16m8_mu(vbool2_t mask, vint16m8_t maskedoff, const int16_t *base, size_t vl) { + return __riscv_vle16_mu(mask, maskedoff, base, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vle16_v_u16mf4_mu +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[MASKEDOFF:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vle.mask.nxv1i16.i64( [[MASKEDOFF]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint16mf4_t test_vle16_v_u16mf4_mu(vbool64_t mask, vuint16mf4_t maskedoff, const uint16_t *base, size_t vl) { + return __riscv_vle16_mu(mask, maskedoff, base, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vle16_v_u16mf2_mu +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[MASKEDOFF:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vle.mask.nxv2i16.i64( [[MASKEDOFF]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint16mf2_t test_vle16_v_u16mf2_mu(vbool32_t mask, vuint16mf2_t maskedoff, const uint16_t *base, size_t vl) { + return __riscv_vle16_mu(mask, maskedoff, base, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vle16_v_u16m1_mu +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[MASKEDOFF:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vle.mask.nxv4i16.i64( [[MASKEDOFF]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint16m1_t test_vle16_v_u16m1_mu(vbool16_t mask, vuint16m1_t maskedoff, const uint16_t *base, size_t vl) { + return __riscv_vle16_mu(mask, maskedoff, base, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vle16_v_u16m2_mu +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[MASKEDOFF:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vle.mask.nxv8i16.i64( [[MASKEDOFF]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint16m2_t test_vle16_v_u16m2_mu(vbool8_t mask, vuint16m2_t maskedoff, const uint16_t *base, size_t vl) { + return __riscv_vle16_mu(mask, maskedoff, base, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vle16_v_u16m4_mu +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[MASKEDOFF:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vle.mask.nxv16i16.i64( [[MASKEDOFF]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint16m4_t test_vle16_v_u16m4_mu(vbool4_t mask, vuint16m4_t maskedoff, const uint16_t *base, size_t vl) { + return __riscv_vle16_mu(mask, maskedoff, base, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vle16_v_u16m8_mu +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[MASKEDOFF:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vle.mask.nxv32i16.i64( [[MASKEDOFF]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint16m8_t test_vle16_v_u16m8_mu(vbool2_t mask, vuint16m8_t maskedoff, const uint16_t *base, size_t vl) { + return __riscv_vle16_mu(mask, maskedoff, base, vl); +} + diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle16ff.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle16ff.c index 4bb713ae81df0..76674f0afd454 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle16ff.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle16ff.c @@ -709,3 +709,237 @@ vuint16m8_t test_vle16ff_v_u16m8_tumu(vbool2_t mask, vuint16m8_t maskedoff, cons return __riscv_vle16ff_tumu(mask, maskedoff, base, new_vl, vl); } +// CHECK-RV64-LABEL: define dso_local @test_vle16ff_v_f16mf4_mu +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[MASKEDOFF:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , i64 } @llvm.riscv.vleff.mask.nxv1f16.i64( [[MASKEDOFF]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: store i64 [[TMP2]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret [[TMP1]] +// +vfloat16mf4_t test_vle16ff_v_f16mf4_mu(vbool64_t mask, vfloat16mf4_t maskedoff, const _Float16 *base, size_t *new_vl, size_t vl) { + return __riscv_vle16ff_mu(mask, maskedoff, base, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vle16ff_v_f16mf2_mu +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[MASKEDOFF:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , i64 } @llvm.riscv.vleff.mask.nxv2f16.i64( [[MASKEDOFF]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: store i64 [[TMP2]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret [[TMP1]] +// +vfloat16mf2_t test_vle16ff_v_f16mf2_mu(vbool32_t mask, vfloat16mf2_t maskedoff, const _Float16 *base, size_t *new_vl, size_t vl) { + return __riscv_vle16ff_mu(mask, maskedoff, base, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vle16ff_v_f16m1_mu +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[MASKEDOFF:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , i64 } @llvm.riscv.vleff.mask.nxv4f16.i64( [[MASKEDOFF]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: store i64 [[TMP2]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret [[TMP1]] +// +vfloat16m1_t test_vle16ff_v_f16m1_mu(vbool16_t mask, vfloat16m1_t maskedoff, const _Float16 *base, size_t *new_vl, size_t vl) { + return __riscv_vle16ff_mu(mask, maskedoff, base, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vle16ff_v_f16m2_mu +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[MASKEDOFF:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , i64 } @llvm.riscv.vleff.mask.nxv8f16.i64( [[MASKEDOFF]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: store i64 [[TMP2]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret [[TMP1]] +// +vfloat16m2_t test_vle16ff_v_f16m2_mu(vbool8_t mask, vfloat16m2_t maskedoff, const _Float16 *base, size_t *new_vl, size_t vl) { + return __riscv_vle16ff_mu(mask, maskedoff, base, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vle16ff_v_f16m4_mu +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[MASKEDOFF:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , i64 } @llvm.riscv.vleff.mask.nxv16f16.i64( [[MASKEDOFF]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: store i64 [[TMP2]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret [[TMP1]] +// +vfloat16m4_t test_vle16ff_v_f16m4_mu(vbool4_t mask, vfloat16m4_t maskedoff, const _Float16 *base, size_t *new_vl, size_t vl) { + return __riscv_vle16ff_mu(mask, maskedoff, base, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vle16ff_v_f16m8_mu +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[MASKEDOFF:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , i64 } @llvm.riscv.vleff.mask.nxv32f16.i64( [[MASKEDOFF]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: store i64 [[TMP2]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret [[TMP1]] +// +vfloat16m8_t test_vle16ff_v_f16m8_mu(vbool2_t mask, vfloat16m8_t maskedoff, const _Float16 *base, size_t *new_vl, size_t vl) { + return __riscv_vle16ff_mu(mask, maskedoff, base, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vle16ff_v_i16mf4_mu +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[MASKEDOFF:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , i64 } @llvm.riscv.vleff.mask.nxv1i16.i64( [[MASKEDOFF]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: store i64 [[TMP2]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret [[TMP1]] +// +vint16mf4_t test_vle16ff_v_i16mf4_mu(vbool64_t mask, vint16mf4_t maskedoff, const int16_t *base, size_t *new_vl, size_t vl) { + return __riscv_vle16ff_mu(mask, maskedoff, base, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vle16ff_v_i16mf2_mu +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[MASKEDOFF:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , i64 } @llvm.riscv.vleff.mask.nxv2i16.i64( [[MASKEDOFF]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: store i64 [[TMP2]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret [[TMP1]] +// +vint16mf2_t test_vle16ff_v_i16mf2_mu(vbool32_t mask, vint16mf2_t maskedoff, const int16_t *base, size_t *new_vl, size_t vl) { + return __riscv_vle16ff_mu(mask, maskedoff, base, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vle16ff_v_i16m1_mu +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[MASKEDOFF:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , i64 } @llvm.riscv.vleff.mask.nxv4i16.i64( [[MASKEDOFF]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: store i64 [[TMP2]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret [[TMP1]] +// +vint16m1_t test_vle16ff_v_i16m1_mu(vbool16_t mask, vint16m1_t maskedoff, const int16_t *base, size_t *new_vl, size_t vl) { + return __riscv_vle16ff_mu(mask, maskedoff, base, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vle16ff_v_i16m2_mu +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[MASKEDOFF:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , i64 } @llvm.riscv.vleff.mask.nxv8i16.i64( [[MASKEDOFF]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: store i64 [[TMP2]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret [[TMP1]] +// +vint16m2_t test_vle16ff_v_i16m2_mu(vbool8_t mask, vint16m2_t maskedoff, const int16_t *base, size_t *new_vl, size_t vl) { + return __riscv_vle16ff_mu(mask, maskedoff, base, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vle16ff_v_i16m4_mu +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[MASKEDOFF:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , i64 } @llvm.riscv.vleff.mask.nxv16i16.i64( [[MASKEDOFF]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: store i64 [[TMP2]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret [[TMP1]] +// +vint16m4_t test_vle16ff_v_i16m4_mu(vbool4_t mask, vint16m4_t maskedoff, const int16_t *base, size_t *new_vl, size_t vl) { + return __riscv_vle16ff_mu(mask, maskedoff, base, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vle16ff_v_i16m8_mu +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[MASKEDOFF:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , i64 } @llvm.riscv.vleff.mask.nxv32i16.i64( [[MASKEDOFF]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: store i64 [[TMP2]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret [[TMP1]] +// +vint16m8_t test_vle16ff_v_i16m8_mu(vbool2_t mask, vint16m8_t maskedoff, const int16_t *base, size_t *new_vl, size_t vl) { + return __riscv_vle16ff_mu(mask, maskedoff, base, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vle16ff_v_u16mf4_mu +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[MASKEDOFF:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , i64 } @llvm.riscv.vleff.mask.nxv1i16.i64( [[MASKEDOFF]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: store i64 [[TMP2]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret [[TMP1]] +// +vuint16mf4_t test_vle16ff_v_u16mf4_mu(vbool64_t mask, vuint16mf4_t maskedoff, const uint16_t *base, size_t *new_vl, size_t vl) { + return __riscv_vle16ff_mu(mask, maskedoff, base, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vle16ff_v_u16mf2_mu +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[MASKEDOFF:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , i64 } @llvm.riscv.vleff.mask.nxv2i16.i64( [[MASKEDOFF]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: store i64 [[TMP2]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret [[TMP1]] +// +vuint16mf2_t test_vle16ff_v_u16mf2_mu(vbool32_t mask, vuint16mf2_t maskedoff, const uint16_t *base, size_t *new_vl, size_t vl) { + return __riscv_vle16ff_mu(mask, maskedoff, base, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vle16ff_v_u16m1_mu +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[MASKEDOFF:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , i64 } @llvm.riscv.vleff.mask.nxv4i16.i64( [[MASKEDOFF]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: store i64 [[TMP2]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret [[TMP1]] +// +vuint16m1_t test_vle16ff_v_u16m1_mu(vbool16_t mask, vuint16m1_t maskedoff, const uint16_t *base, size_t *new_vl, size_t vl) { + return __riscv_vle16ff_mu(mask, maskedoff, base, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vle16ff_v_u16m2_mu +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[MASKEDOFF:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , i64 } @llvm.riscv.vleff.mask.nxv8i16.i64( [[MASKEDOFF]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: store i64 [[TMP2]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret [[TMP1]] +// +vuint16m2_t test_vle16ff_v_u16m2_mu(vbool8_t mask, vuint16m2_t maskedoff, const uint16_t *base, size_t *new_vl, size_t vl) { + return __riscv_vle16ff_mu(mask, maskedoff, base, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vle16ff_v_u16m4_mu +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[MASKEDOFF:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , i64 } @llvm.riscv.vleff.mask.nxv16i16.i64( [[MASKEDOFF]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: store i64 [[TMP2]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret [[TMP1]] +// +vuint16m4_t test_vle16ff_v_u16m4_mu(vbool4_t mask, vuint16m4_t maskedoff, const uint16_t *base, size_t *new_vl, size_t vl) { + return __riscv_vle16ff_mu(mask, maskedoff, base, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vle16ff_v_u16m8_mu +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[MASKEDOFF:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , i64 } @llvm.riscv.vleff.mask.nxv32i16.i64( [[MASKEDOFF]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: store i64 [[TMP2]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret [[TMP1]] +// +vuint16m8_t test_vle16ff_v_u16m8_mu(vbool2_t mask, vuint16m8_t maskedoff, const uint16_t *base, size_t *new_vl, size_t vl) { + return __riscv_vle16ff_mu(mask, maskedoff, base, new_vl, vl); +} + diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle32.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle32.c index 7f5902f1708df..0f51dbec518af 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle32.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle32.c @@ -457,3 +457,153 @@ vuint32m8_t test_vle32_v_u32m8_tumu(vbool4_t mask, vuint32m8_t maskedoff, const return __riscv_vle32_tumu(mask, maskedoff, base, vl); } +// CHECK-RV64-LABEL: define dso_local @test_vle32_v_f32mf2_mu +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[MASKEDOFF:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vle.mask.nxv1f32.i64( [[MASKEDOFF]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vfloat32mf2_t test_vle32_v_f32mf2_mu(vbool64_t mask, vfloat32mf2_t maskedoff, const float *base, size_t vl) { + return __riscv_vle32_mu(mask, maskedoff, base, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vle32_v_f32m1_mu +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[MASKEDOFF:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vle.mask.nxv2f32.i64( [[MASKEDOFF]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vfloat32m1_t test_vle32_v_f32m1_mu(vbool32_t mask, vfloat32m1_t maskedoff, const float *base, size_t vl) { + return __riscv_vle32_mu(mask, maskedoff, base, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vle32_v_f32m2_mu +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[MASKEDOFF:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vle.mask.nxv4f32.i64( [[MASKEDOFF]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vfloat32m2_t test_vle32_v_f32m2_mu(vbool16_t mask, vfloat32m2_t maskedoff, const float *base, size_t vl) { + return __riscv_vle32_mu(mask, maskedoff, base, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vle32_v_f32m4_mu +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[MASKEDOFF:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vle.mask.nxv8f32.i64( [[MASKEDOFF]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vfloat32m4_t test_vle32_v_f32m4_mu(vbool8_t mask, vfloat32m4_t maskedoff, const float *base, size_t vl) { + return __riscv_vle32_mu(mask, maskedoff, base, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vle32_v_f32m8_mu +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[MASKEDOFF:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vle.mask.nxv16f32.i64( [[MASKEDOFF]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vfloat32m8_t test_vle32_v_f32m8_mu(vbool4_t mask, vfloat32m8_t maskedoff, const float *base, size_t vl) { + return __riscv_vle32_mu(mask, maskedoff, base, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vle32_v_i32mf2_mu +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[MASKEDOFF:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vle.mask.nxv1i32.i64( [[MASKEDOFF]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint32mf2_t test_vle32_v_i32mf2_mu(vbool64_t mask, vint32mf2_t maskedoff, const int32_t *base, size_t vl) { + return __riscv_vle32_mu(mask, maskedoff, base, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vle32_v_i32m1_mu +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[MASKEDOFF:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vle.mask.nxv2i32.i64( [[MASKEDOFF]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint32m1_t test_vle32_v_i32m1_mu(vbool32_t mask, vint32m1_t maskedoff, const int32_t *base, size_t vl) { + return __riscv_vle32_mu(mask, maskedoff, base, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vle32_v_i32m2_mu +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[MASKEDOFF:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vle.mask.nxv4i32.i64( [[MASKEDOFF]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint32m2_t test_vle32_v_i32m2_mu(vbool16_t mask, vint32m2_t maskedoff, const int32_t *base, size_t vl) { + return __riscv_vle32_mu(mask, maskedoff, base, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vle32_v_i32m4_mu +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[MASKEDOFF:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vle.mask.nxv8i32.i64( [[MASKEDOFF]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint32m4_t test_vle32_v_i32m4_mu(vbool8_t mask, vint32m4_t maskedoff, const int32_t *base, size_t vl) { + return __riscv_vle32_mu(mask, maskedoff, base, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vle32_v_i32m8_mu +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[MASKEDOFF:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vle.mask.nxv16i32.i64( [[MASKEDOFF]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint32m8_t test_vle32_v_i32m8_mu(vbool4_t mask, vint32m8_t maskedoff, const int32_t *base, size_t vl) { + return __riscv_vle32_mu(mask, maskedoff, base, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vle32_v_u32mf2_mu +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[MASKEDOFF:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vle.mask.nxv1i32.i64( [[MASKEDOFF]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint32mf2_t test_vle32_v_u32mf2_mu(vbool64_t mask, vuint32mf2_t maskedoff, const uint32_t *base, size_t vl) { + return __riscv_vle32_mu(mask, maskedoff, base, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vle32_v_u32m1_mu +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[MASKEDOFF:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vle.mask.nxv2i32.i64( [[MASKEDOFF]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint32m1_t test_vle32_v_u32m1_mu(vbool32_t mask, vuint32m1_t maskedoff, const uint32_t *base, size_t vl) { + return __riscv_vle32_mu(mask, maskedoff, base, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vle32_v_u32m2_mu +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[MASKEDOFF:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vle.mask.nxv4i32.i64( [[MASKEDOFF]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint32m2_t test_vle32_v_u32m2_mu(vbool16_t mask, vuint32m2_t maskedoff, const uint32_t *base, size_t vl) { + return __riscv_vle32_mu(mask, maskedoff, base, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vle32_v_u32m4_mu +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[MASKEDOFF:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vle.mask.nxv8i32.i64( [[MASKEDOFF]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint32m4_t test_vle32_v_u32m4_mu(vbool8_t mask, vuint32m4_t maskedoff, const uint32_t *base, size_t vl) { + return __riscv_vle32_mu(mask, maskedoff, base, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vle32_v_u32m8_mu +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[MASKEDOFF:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vle.mask.nxv16i32.i64( [[MASKEDOFF]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint32m8_t test_vle32_v_u32m8_mu(vbool4_t mask, vuint32m8_t maskedoff, const uint32_t *base, size_t vl) { + return __riscv_vle32_mu(mask, maskedoff, base, vl); +} + diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle32ff.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle32ff.c index a8a24aad5d337..94adfcc7aa3a7 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle32ff.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle32ff.c @@ -592,3 +592,198 @@ vuint32m8_t test_vle32ff_v_u32m8_tumu(vbool4_t mask, vuint32m8_t maskedoff, cons return __riscv_vle32ff_tumu(mask, maskedoff, base, new_vl, vl); } +// CHECK-RV64-LABEL: define dso_local @test_vle32ff_v_f32mf2_mu +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[MASKEDOFF:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , i64 } @llvm.riscv.vleff.mask.nxv1f32.i64( [[MASKEDOFF]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: store i64 [[TMP2]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret [[TMP1]] +// +vfloat32mf2_t test_vle32ff_v_f32mf2_mu(vbool64_t mask, vfloat32mf2_t maskedoff, const float *base, size_t *new_vl, size_t vl) { + return __riscv_vle32ff_mu(mask, maskedoff, base, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vle32ff_v_f32m1_mu +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[MASKEDOFF:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , i64 } @llvm.riscv.vleff.mask.nxv2f32.i64( [[MASKEDOFF]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: store i64 [[TMP2]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret [[TMP1]] +// +vfloat32m1_t test_vle32ff_v_f32m1_mu(vbool32_t mask, vfloat32m1_t maskedoff, const float *base, size_t *new_vl, size_t vl) { + return __riscv_vle32ff_mu(mask, maskedoff, base, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vle32ff_v_f32m2_mu +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[MASKEDOFF:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , i64 } @llvm.riscv.vleff.mask.nxv4f32.i64( [[MASKEDOFF]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: store i64 [[TMP2]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret [[TMP1]] +// +vfloat32m2_t test_vle32ff_v_f32m2_mu(vbool16_t mask, vfloat32m2_t maskedoff, const float *base, size_t *new_vl, size_t vl) { + return __riscv_vle32ff_mu(mask, maskedoff, base, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vle32ff_v_f32m4_mu +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[MASKEDOFF:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , i64 } @llvm.riscv.vleff.mask.nxv8f32.i64( [[MASKEDOFF]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: store i64 [[TMP2]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret [[TMP1]] +// +vfloat32m4_t test_vle32ff_v_f32m4_mu(vbool8_t mask, vfloat32m4_t maskedoff, const float *base, size_t *new_vl, size_t vl) { + return __riscv_vle32ff_mu(mask, maskedoff, base, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vle32ff_v_f32m8_mu +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[MASKEDOFF:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , i64 } @llvm.riscv.vleff.mask.nxv16f32.i64( [[MASKEDOFF]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: store i64 [[TMP2]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret [[TMP1]] +// +vfloat32m8_t test_vle32ff_v_f32m8_mu(vbool4_t mask, vfloat32m8_t maskedoff, const float *base, size_t *new_vl, size_t vl) { + return __riscv_vle32ff_mu(mask, maskedoff, base, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vle32ff_v_i32mf2_mu +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[MASKEDOFF:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , i64 } @llvm.riscv.vleff.mask.nxv1i32.i64( [[MASKEDOFF]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: store i64 [[TMP2]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret [[TMP1]] +// +vint32mf2_t test_vle32ff_v_i32mf2_mu(vbool64_t mask, vint32mf2_t maskedoff, const int32_t *base, size_t *new_vl, size_t vl) { + return __riscv_vle32ff_mu(mask, maskedoff, base, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vle32ff_v_i32m1_mu +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[MASKEDOFF:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , i64 } @llvm.riscv.vleff.mask.nxv2i32.i64( [[MASKEDOFF]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: store i64 [[TMP2]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret [[TMP1]] +// +vint32m1_t test_vle32ff_v_i32m1_mu(vbool32_t mask, vint32m1_t maskedoff, const int32_t *base, size_t *new_vl, size_t vl) { + return __riscv_vle32ff_mu(mask, maskedoff, base, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vle32ff_v_i32m2_mu +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[MASKEDOFF:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , i64 } @llvm.riscv.vleff.mask.nxv4i32.i64( [[MASKEDOFF]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: store i64 [[TMP2]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret [[TMP1]] +// +vint32m2_t test_vle32ff_v_i32m2_mu(vbool16_t mask, vint32m2_t maskedoff, const int32_t *base, size_t *new_vl, size_t vl) { + return __riscv_vle32ff_mu(mask, maskedoff, base, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vle32ff_v_i32m4_mu +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[MASKEDOFF:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , i64 } @llvm.riscv.vleff.mask.nxv8i32.i64( [[MASKEDOFF]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: store i64 [[TMP2]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret [[TMP1]] +// +vint32m4_t test_vle32ff_v_i32m4_mu(vbool8_t mask, vint32m4_t maskedoff, const int32_t *base, size_t *new_vl, size_t vl) { + return __riscv_vle32ff_mu(mask, maskedoff, base, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vle32ff_v_i32m8_mu +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[MASKEDOFF:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , i64 } @llvm.riscv.vleff.mask.nxv16i32.i64( [[MASKEDOFF]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: store i64 [[TMP2]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret [[TMP1]] +// +vint32m8_t test_vle32ff_v_i32m8_mu(vbool4_t mask, vint32m8_t maskedoff, const int32_t *base, size_t *new_vl, size_t vl) { + return __riscv_vle32ff_mu(mask, maskedoff, base, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vle32ff_v_u32mf2_mu +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[MASKEDOFF:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , i64 } @llvm.riscv.vleff.mask.nxv1i32.i64( [[MASKEDOFF]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: store i64 [[TMP2]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret [[TMP1]] +// +vuint32mf2_t test_vle32ff_v_u32mf2_mu(vbool64_t mask, vuint32mf2_t maskedoff, const uint32_t *base, size_t *new_vl, size_t vl) { + return __riscv_vle32ff_mu(mask, maskedoff, base, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vle32ff_v_u32m1_mu +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[MASKEDOFF:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , i64 } @llvm.riscv.vleff.mask.nxv2i32.i64( [[MASKEDOFF]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: store i64 [[TMP2]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret [[TMP1]] +// +vuint32m1_t test_vle32ff_v_u32m1_mu(vbool32_t mask, vuint32m1_t maskedoff, const uint32_t *base, size_t *new_vl, size_t vl) { + return __riscv_vle32ff_mu(mask, maskedoff, base, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vle32ff_v_u32m2_mu +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[MASKEDOFF:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , i64 } @llvm.riscv.vleff.mask.nxv4i32.i64( [[MASKEDOFF]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: store i64 [[TMP2]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret [[TMP1]] +// +vuint32m2_t test_vle32ff_v_u32m2_mu(vbool16_t mask, vuint32m2_t maskedoff, const uint32_t *base, size_t *new_vl, size_t vl) { + return __riscv_vle32ff_mu(mask, maskedoff, base, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vle32ff_v_u32m4_mu +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[MASKEDOFF:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , i64 } @llvm.riscv.vleff.mask.nxv8i32.i64( [[MASKEDOFF]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: store i64 [[TMP2]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret [[TMP1]] +// +vuint32m4_t test_vle32ff_v_u32m4_mu(vbool8_t mask, vuint32m4_t maskedoff, const uint32_t *base, size_t *new_vl, size_t vl) { + return __riscv_vle32ff_mu(mask, maskedoff, base, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vle32ff_v_u32m8_mu +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[MASKEDOFF:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , i64 } @llvm.riscv.vleff.mask.nxv16i32.i64( [[MASKEDOFF]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: store i64 [[TMP2]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret [[TMP1]] +// +vuint32m8_t test_vle32ff_v_u32m8_mu(vbool4_t mask, vuint32m8_t maskedoff, const uint32_t *base, size_t *new_vl, size_t vl) { + return __riscv_vle32ff_mu(mask, maskedoff, base, new_vl, vl); +} + diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle64.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle64.c index 6ad67d77df5c3..823823edd5747 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle64.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle64.c @@ -367,3 +367,123 @@ vuint64m8_t test_vle64_v_u64m8_tumu(vbool8_t mask, vuint64m8_t maskedoff, const return __riscv_vle64_tumu(mask, maskedoff, base, vl); } +// CHECK-RV64-LABEL: define dso_local @test_vle64_v_f64m1_mu +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[MASKEDOFF:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vle.mask.nxv1f64.i64( [[MASKEDOFF]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vfloat64m1_t test_vle64_v_f64m1_mu(vbool64_t mask, vfloat64m1_t maskedoff, const double *base, size_t vl) { + return __riscv_vle64_mu(mask, maskedoff, base, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vle64_v_f64m2_mu +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[MASKEDOFF:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vle.mask.nxv2f64.i64( [[MASKEDOFF]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vfloat64m2_t test_vle64_v_f64m2_mu(vbool32_t mask, vfloat64m2_t maskedoff, const double *base, size_t vl) { + return __riscv_vle64_mu(mask, maskedoff, base, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vle64_v_f64m4_mu +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[MASKEDOFF:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vle.mask.nxv4f64.i64( [[MASKEDOFF]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vfloat64m4_t test_vle64_v_f64m4_mu(vbool16_t mask, vfloat64m4_t maskedoff, const double *base, size_t vl) { + return __riscv_vle64_mu(mask, maskedoff, base, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vle64_v_f64m8_mu +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[MASKEDOFF:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vle.mask.nxv8f64.i64( [[MASKEDOFF]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vfloat64m8_t test_vle64_v_f64m8_mu(vbool8_t mask, vfloat64m8_t maskedoff, const double *base, size_t vl) { + return __riscv_vle64_mu(mask, maskedoff, base, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vle64_v_i64m1_mu +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[MASKEDOFF:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vle.mask.nxv1i64.i64( [[MASKEDOFF]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint64m1_t test_vle64_v_i64m1_mu(vbool64_t mask, vint64m1_t maskedoff, const int64_t *base, size_t vl) { + return __riscv_vle64_mu(mask, maskedoff, base, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vle64_v_i64m2_mu +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[MASKEDOFF:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vle.mask.nxv2i64.i64( [[MASKEDOFF]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint64m2_t test_vle64_v_i64m2_mu(vbool32_t mask, vint64m2_t maskedoff, const int64_t *base, size_t vl) { + return __riscv_vle64_mu(mask, maskedoff, base, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vle64_v_i64m4_mu +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[MASKEDOFF:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vle.mask.nxv4i64.i64( [[MASKEDOFF]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint64m4_t test_vle64_v_i64m4_mu(vbool16_t mask, vint64m4_t maskedoff, const int64_t *base, size_t vl) { + return __riscv_vle64_mu(mask, maskedoff, base, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vle64_v_i64m8_mu +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[MASKEDOFF:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vle.mask.nxv8i64.i64( [[MASKEDOFF]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint64m8_t test_vle64_v_i64m8_mu(vbool8_t mask, vint64m8_t maskedoff, const int64_t *base, size_t vl) { + return __riscv_vle64_mu(mask, maskedoff, base, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vle64_v_u64m1_mu +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[MASKEDOFF:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vle.mask.nxv1i64.i64( [[MASKEDOFF]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint64m1_t test_vle64_v_u64m1_mu(vbool64_t mask, vuint64m1_t maskedoff, const uint64_t *base, size_t vl) { + return __riscv_vle64_mu(mask, maskedoff, base, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vle64_v_u64m2_mu +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[MASKEDOFF:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vle.mask.nxv2i64.i64( [[MASKEDOFF]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint64m2_t test_vle64_v_u64m2_mu(vbool32_t mask, vuint64m2_t maskedoff, const uint64_t *base, size_t vl) { + return __riscv_vle64_mu(mask, maskedoff, base, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vle64_v_u64m4_mu +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[MASKEDOFF:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vle.mask.nxv4i64.i64( [[MASKEDOFF]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint64m4_t test_vle64_v_u64m4_mu(vbool16_t mask, vuint64m4_t maskedoff, const uint64_t *base, size_t vl) { + return __riscv_vle64_mu(mask, maskedoff, base, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vle64_v_u64m8_mu +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[MASKEDOFF:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vle.mask.nxv8i64.i64( [[MASKEDOFF]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint64m8_t test_vle64_v_u64m8_mu(vbool8_t mask, vuint64m8_t maskedoff, const uint64_t *base, size_t vl) { + return __riscv_vle64_mu(mask, maskedoff, base, vl); +} + diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle64ff.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle64ff.c index 1084e2fc1d527..92563dcc3a357 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle64ff.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle64ff.c @@ -475,3 +475,159 @@ vuint64m8_t test_vle64ff_v_u64m8_tumu(vbool8_t mask, vuint64m8_t maskedoff, cons return __riscv_vle64ff_tumu(mask, maskedoff, base, new_vl, vl); } +// CHECK-RV64-LABEL: define dso_local @test_vle64ff_v_f64m1_mu +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[MASKEDOFF:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , i64 } @llvm.riscv.vleff.mask.nxv1f64.i64( [[MASKEDOFF]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: store i64 [[TMP2]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret [[TMP1]] +// +vfloat64m1_t test_vle64ff_v_f64m1_mu(vbool64_t mask, vfloat64m1_t maskedoff, const double *base, size_t *new_vl, size_t vl) { + return __riscv_vle64ff_mu(mask, maskedoff, base, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vle64ff_v_f64m2_mu +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[MASKEDOFF:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , i64 } @llvm.riscv.vleff.mask.nxv2f64.i64( [[MASKEDOFF]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: store i64 [[TMP2]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret [[TMP1]] +// +vfloat64m2_t test_vle64ff_v_f64m2_mu(vbool32_t mask, vfloat64m2_t maskedoff, const double *base, size_t *new_vl, size_t vl) { + return __riscv_vle64ff_mu(mask, maskedoff, base, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vle64ff_v_f64m4_mu +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[MASKEDOFF:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , i64 } @llvm.riscv.vleff.mask.nxv4f64.i64( [[MASKEDOFF]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: store i64 [[TMP2]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret [[TMP1]] +// +vfloat64m4_t test_vle64ff_v_f64m4_mu(vbool16_t mask, vfloat64m4_t maskedoff, const double *base, size_t *new_vl, size_t vl) { + return __riscv_vle64ff_mu(mask, maskedoff, base, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vle64ff_v_f64m8_mu +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[MASKEDOFF:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , i64 } @llvm.riscv.vleff.mask.nxv8f64.i64( [[MASKEDOFF]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: store i64 [[TMP2]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret [[TMP1]] +// +vfloat64m8_t test_vle64ff_v_f64m8_mu(vbool8_t mask, vfloat64m8_t maskedoff, const double *base, size_t *new_vl, size_t vl) { + return __riscv_vle64ff_mu(mask, maskedoff, base, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vle64ff_v_i64m1_mu +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[MASKEDOFF:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , i64 } @llvm.riscv.vleff.mask.nxv1i64.i64( [[MASKEDOFF]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: store i64 [[TMP2]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret [[TMP1]] +// +vint64m1_t test_vle64ff_v_i64m1_mu(vbool64_t mask, vint64m1_t maskedoff, const int64_t *base, size_t *new_vl, size_t vl) { + return __riscv_vle64ff_mu(mask, maskedoff, base, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vle64ff_v_i64m2_mu +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[MASKEDOFF:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , i64 } @llvm.riscv.vleff.mask.nxv2i64.i64( [[MASKEDOFF]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: store i64 [[TMP2]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret [[TMP1]] +// +vint64m2_t test_vle64ff_v_i64m2_mu(vbool32_t mask, vint64m2_t maskedoff, const int64_t *base, size_t *new_vl, size_t vl) { + return __riscv_vle64ff_mu(mask, maskedoff, base, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vle64ff_v_i64m4_mu +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[MASKEDOFF:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , i64 } @llvm.riscv.vleff.mask.nxv4i64.i64( [[MASKEDOFF]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: store i64 [[TMP2]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret [[TMP1]] +// +vint64m4_t test_vle64ff_v_i64m4_mu(vbool16_t mask, vint64m4_t maskedoff, const int64_t *base, size_t *new_vl, size_t vl) { + return __riscv_vle64ff_mu(mask, maskedoff, base, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vle64ff_v_i64m8_mu +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[MASKEDOFF:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , i64 } @llvm.riscv.vleff.mask.nxv8i64.i64( [[MASKEDOFF]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: store i64 [[TMP2]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret [[TMP1]] +// +vint64m8_t test_vle64ff_v_i64m8_mu(vbool8_t mask, vint64m8_t maskedoff, const int64_t *base, size_t *new_vl, size_t vl) { + return __riscv_vle64ff_mu(mask, maskedoff, base, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vle64ff_v_u64m1_mu +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[MASKEDOFF:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , i64 } @llvm.riscv.vleff.mask.nxv1i64.i64( [[MASKEDOFF]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: store i64 [[TMP2]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret [[TMP1]] +// +vuint64m1_t test_vle64ff_v_u64m1_mu(vbool64_t mask, vuint64m1_t maskedoff, const uint64_t *base, size_t *new_vl, size_t vl) { + return __riscv_vle64ff_mu(mask, maskedoff, base, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vle64ff_v_u64m2_mu +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[MASKEDOFF:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , i64 } @llvm.riscv.vleff.mask.nxv2i64.i64( [[MASKEDOFF]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: store i64 [[TMP2]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret [[TMP1]] +// +vuint64m2_t test_vle64ff_v_u64m2_mu(vbool32_t mask, vuint64m2_t maskedoff, const uint64_t *base, size_t *new_vl, size_t vl) { + return __riscv_vle64ff_mu(mask, maskedoff, base, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vle64ff_v_u64m4_mu +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[MASKEDOFF:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , i64 } @llvm.riscv.vleff.mask.nxv4i64.i64( [[MASKEDOFF]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: store i64 [[TMP2]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret [[TMP1]] +// +vuint64m4_t test_vle64ff_v_u64m4_mu(vbool16_t mask, vuint64m4_t maskedoff, const uint64_t *base, size_t *new_vl, size_t vl) { + return __riscv_vle64ff_mu(mask, maskedoff, base, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vle64ff_v_u64m8_mu +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[MASKEDOFF:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , i64 } @llvm.riscv.vleff.mask.nxv8i64.i64( [[MASKEDOFF]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: store i64 [[TMP2]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret [[TMP1]] +// +vuint64m8_t test_vle64ff_v_u64m8_mu(vbool8_t mask, vuint64m8_t maskedoff, const uint64_t *base, size_t *new_vl, size_t vl) { + return __riscv_vle64ff_mu(mask, maskedoff, base, new_vl, vl); +} + diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle8.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle8.c index 7c63d96671927..63ace907a2620 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle8.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle8.c @@ -427,3 +427,143 @@ vuint8m8_t test_vle8_v_u8m8_tumu(vbool1_t mask, vuint8m8_t maskedoff, const uint return __riscv_vle8_tumu(mask, maskedoff, base, vl); } +// CHECK-RV64-LABEL: define dso_local @test_vle8_v_i8mf8_mu +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[MASKEDOFF:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vle.mask.nxv1i8.i64( [[MASKEDOFF]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint8mf8_t test_vle8_v_i8mf8_mu(vbool64_t mask, vint8mf8_t maskedoff, const int8_t *base, size_t vl) { + return __riscv_vle8_mu(mask, maskedoff, base, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vle8_v_i8mf4_mu +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[MASKEDOFF:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vle.mask.nxv2i8.i64( [[MASKEDOFF]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint8mf4_t test_vle8_v_i8mf4_mu(vbool32_t mask, vint8mf4_t maskedoff, const int8_t *base, size_t vl) { + return __riscv_vle8_mu(mask, maskedoff, base, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vle8_v_i8mf2_mu +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[MASKEDOFF:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vle.mask.nxv4i8.i64( [[MASKEDOFF]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint8mf2_t test_vle8_v_i8mf2_mu(vbool16_t mask, vint8mf2_t maskedoff, const int8_t *base, size_t vl) { + return __riscv_vle8_mu(mask, maskedoff, base, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vle8_v_i8m1_mu +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[MASKEDOFF:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vle.mask.nxv8i8.i64( [[MASKEDOFF]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint8m1_t test_vle8_v_i8m1_mu(vbool8_t mask, vint8m1_t maskedoff, const int8_t *base, size_t vl) { + return __riscv_vle8_mu(mask, maskedoff, base, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vle8_v_i8m2_mu +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[MASKEDOFF:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vle.mask.nxv16i8.i64( [[MASKEDOFF]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint8m2_t test_vle8_v_i8m2_mu(vbool4_t mask, vint8m2_t maskedoff, const int8_t *base, size_t vl) { + return __riscv_vle8_mu(mask, maskedoff, base, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vle8_v_i8m4_mu +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[MASKEDOFF:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vle.mask.nxv32i8.i64( [[MASKEDOFF]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint8m4_t test_vle8_v_i8m4_mu(vbool2_t mask, vint8m4_t maskedoff, const int8_t *base, size_t vl) { + return __riscv_vle8_mu(mask, maskedoff, base, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vle8_v_i8m8_mu +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[MASKEDOFF:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vle.mask.nxv64i8.i64( [[MASKEDOFF]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint8m8_t test_vle8_v_i8m8_mu(vbool1_t mask, vint8m8_t maskedoff, const int8_t *base, size_t vl) { + return __riscv_vle8_mu(mask, maskedoff, base, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vle8_v_u8mf8_mu +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[MASKEDOFF:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vle.mask.nxv1i8.i64( [[MASKEDOFF]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint8mf8_t test_vle8_v_u8mf8_mu(vbool64_t mask, vuint8mf8_t maskedoff, const uint8_t *base, size_t vl) { + return __riscv_vle8_mu(mask, maskedoff, base, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vle8_v_u8mf4_mu +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[MASKEDOFF:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vle.mask.nxv2i8.i64( [[MASKEDOFF]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint8mf4_t test_vle8_v_u8mf4_mu(vbool32_t mask, vuint8mf4_t maskedoff, const uint8_t *base, size_t vl) { + return __riscv_vle8_mu(mask, maskedoff, base, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vle8_v_u8mf2_mu +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[MASKEDOFF:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vle.mask.nxv4i8.i64( [[MASKEDOFF]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint8mf2_t test_vle8_v_u8mf2_mu(vbool16_t mask, vuint8mf2_t maskedoff, const uint8_t *base, size_t vl) { + return __riscv_vle8_mu(mask, maskedoff, base, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vle8_v_u8m1_mu +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[MASKEDOFF:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vle.mask.nxv8i8.i64( [[MASKEDOFF]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint8m1_t test_vle8_v_u8m1_mu(vbool8_t mask, vuint8m1_t maskedoff, const uint8_t *base, size_t vl) { + return __riscv_vle8_mu(mask, maskedoff, base, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vle8_v_u8m2_mu +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[MASKEDOFF:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vle.mask.nxv16i8.i64( [[MASKEDOFF]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint8m2_t test_vle8_v_u8m2_mu(vbool4_t mask, vuint8m2_t maskedoff, const uint8_t *base, size_t vl) { + return __riscv_vle8_mu(mask, maskedoff, base, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vle8_v_u8m4_mu +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[MASKEDOFF:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vle.mask.nxv32i8.i64( [[MASKEDOFF]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint8m4_t test_vle8_v_u8m4_mu(vbool2_t mask, vuint8m4_t maskedoff, const uint8_t *base, size_t vl) { + return __riscv_vle8_mu(mask, maskedoff, base, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vle8_v_u8m8_mu +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[MASKEDOFF:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vle.mask.nxv64i8.i64( [[MASKEDOFF]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint8m8_t test_vle8_v_u8m8_mu(vbool1_t mask, vuint8m8_t maskedoff, const uint8_t *base, size_t vl) { + return __riscv_vle8_mu(mask, maskedoff, base, vl); +} + diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle8ff.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle8ff.c index a3311112dcc72..4fd0ce7b222ce 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle8ff.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vle8ff.c @@ -553,3 +553,185 @@ vuint8m8_t test_vle8ff_v_u8m8_tumu(vbool1_t mask, vuint8m8_t maskedoff, const ui return __riscv_vle8ff_tumu(mask, maskedoff, base, new_vl, vl); } +// CHECK-RV64-LABEL: define dso_local @test_vle8ff_v_i8mf8_mu +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[MASKEDOFF:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , i64 } @llvm.riscv.vleff.mask.nxv1i8.i64( [[MASKEDOFF]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: store i64 [[TMP2]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret [[TMP1]] +// +vint8mf8_t test_vle8ff_v_i8mf8_mu(vbool64_t mask, vint8mf8_t maskedoff, const int8_t *base, size_t *new_vl, size_t vl) { + return __riscv_vle8ff_mu(mask, maskedoff, base, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vle8ff_v_i8mf4_mu +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[MASKEDOFF:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , i64 } @llvm.riscv.vleff.mask.nxv2i8.i64( [[MASKEDOFF]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: store i64 [[TMP2]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret [[TMP1]] +// +vint8mf4_t test_vle8ff_v_i8mf4_mu(vbool32_t mask, vint8mf4_t maskedoff, const int8_t *base, size_t *new_vl, size_t vl) { + return __riscv_vle8ff_mu(mask, maskedoff, base, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vle8ff_v_i8mf2_mu +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[MASKEDOFF:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , i64 } @llvm.riscv.vleff.mask.nxv4i8.i64( [[MASKEDOFF]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: store i64 [[TMP2]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret [[TMP1]] +// +vint8mf2_t test_vle8ff_v_i8mf2_mu(vbool16_t mask, vint8mf2_t maskedoff, const int8_t *base, size_t *new_vl, size_t vl) { + return __riscv_vle8ff_mu(mask, maskedoff, base, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vle8ff_v_i8m1_mu +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[MASKEDOFF:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , i64 } @llvm.riscv.vleff.mask.nxv8i8.i64( [[MASKEDOFF]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: store i64 [[TMP2]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret [[TMP1]] +// +vint8m1_t test_vle8ff_v_i8m1_mu(vbool8_t mask, vint8m1_t maskedoff, const int8_t *base, size_t *new_vl, size_t vl) { + return __riscv_vle8ff_mu(mask, maskedoff, base, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vle8ff_v_i8m2_mu +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[MASKEDOFF:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , i64 } @llvm.riscv.vleff.mask.nxv16i8.i64( [[MASKEDOFF]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: store i64 [[TMP2]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret [[TMP1]] +// +vint8m2_t test_vle8ff_v_i8m2_mu(vbool4_t mask, vint8m2_t maskedoff, const int8_t *base, size_t *new_vl, size_t vl) { + return __riscv_vle8ff_mu(mask, maskedoff, base, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vle8ff_v_i8m4_mu +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[MASKEDOFF:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , i64 } @llvm.riscv.vleff.mask.nxv32i8.i64( [[MASKEDOFF]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: store i64 [[TMP2]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret [[TMP1]] +// +vint8m4_t test_vle8ff_v_i8m4_mu(vbool2_t mask, vint8m4_t maskedoff, const int8_t *base, size_t *new_vl, size_t vl) { + return __riscv_vle8ff_mu(mask, maskedoff, base, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vle8ff_v_i8m8_mu +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[MASKEDOFF:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , i64 } @llvm.riscv.vleff.mask.nxv64i8.i64( [[MASKEDOFF]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: store i64 [[TMP2]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret [[TMP1]] +// +vint8m8_t test_vle8ff_v_i8m8_mu(vbool1_t mask, vint8m8_t maskedoff, const int8_t *base, size_t *new_vl, size_t vl) { + return __riscv_vle8ff_mu(mask, maskedoff, base, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vle8ff_v_u8mf8_mu +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[MASKEDOFF:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , i64 } @llvm.riscv.vleff.mask.nxv1i8.i64( [[MASKEDOFF]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: store i64 [[TMP2]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret [[TMP1]] +// +vuint8mf8_t test_vle8ff_v_u8mf8_mu(vbool64_t mask, vuint8mf8_t maskedoff, const uint8_t *base, size_t *new_vl, size_t vl) { + return __riscv_vle8ff_mu(mask, maskedoff, base, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vle8ff_v_u8mf4_mu +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[MASKEDOFF:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , i64 } @llvm.riscv.vleff.mask.nxv2i8.i64( [[MASKEDOFF]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: store i64 [[TMP2]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret [[TMP1]] +// +vuint8mf4_t test_vle8ff_v_u8mf4_mu(vbool32_t mask, vuint8mf4_t maskedoff, const uint8_t *base, size_t *new_vl, size_t vl) { + return __riscv_vle8ff_mu(mask, maskedoff, base, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vle8ff_v_u8mf2_mu +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[MASKEDOFF:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , i64 } @llvm.riscv.vleff.mask.nxv4i8.i64( [[MASKEDOFF]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: store i64 [[TMP2]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret [[TMP1]] +// +vuint8mf2_t test_vle8ff_v_u8mf2_mu(vbool16_t mask, vuint8mf2_t maskedoff, const uint8_t *base, size_t *new_vl, size_t vl) { + return __riscv_vle8ff_mu(mask, maskedoff, base, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vle8ff_v_u8m1_mu +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[MASKEDOFF:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , i64 } @llvm.riscv.vleff.mask.nxv8i8.i64( [[MASKEDOFF]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: store i64 [[TMP2]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret [[TMP1]] +// +vuint8m1_t test_vle8ff_v_u8m1_mu(vbool8_t mask, vuint8m1_t maskedoff, const uint8_t *base, size_t *new_vl, size_t vl) { + return __riscv_vle8ff_mu(mask, maskedoff, base, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vle8ff_v_u8m2_mu +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[MASKEDOFF:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , i64 } @llvm.riscv.vleff.mask.nxv16i8.i64( [[MASKEDOFF]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: store i64 [[TMP2]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret [[TMP1]] +// +vuint8m2_t test_vle8ff_v_u8m2_mu(vbool4_t mask, vuint8m2_t maskedoff, const uint8_t *base, size_t *new_vl, size_t vl) { + return __riscv_vle8ff_mu(mask, maskedoff, base, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vle8ff_v_u8m4_mu +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[MASKEDOFF:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , i64 } @llvm.riscv.vleff.mask.nxv32i8.i64( [[MASKEDOFF]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: store i64 [[TMP2]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret [[TMP1]] +// +vuint8m4_t test_vle8ff_v_u8m4_mu(vbool2_t mask, vuint8m4_t maskedoff, const uint8_t *base, size_t *new_vl, size_t vl) { + return __riscv_vle8ff_mu(mask, maskedoff, base, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vle8ff_v_u8m8_mu +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[MASKEDOFF:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , i64 } @llvm.riscv.vleff.mask.nxv64i8.i64( [[MASKEDOFF]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: store i64 [[TMP2]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret [[TMP1]] +// +vuint8m8_t test_vle8ff_v_u8m8_mu(vbool1_t mask, vuint8m8_t maskedoff, const uint8_t *base, size_t *new_vl, size_t vl) { + return __riscv_vle8ff_mu(mask, maskedoff, base, new_vl, vl); +} + diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlse16.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlse16.c index d9d3518d2e6be..764ae093f3044 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlse16.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlse16.c @@ -547,3 +547,183 @@ vuint16m8_t test_vlse16_v_u16m8_tumu(vbool2_t mask, vuint16m8_t maskedoff, const return __riscv_vlse16_tumu(mask, maskedoff, base, bstride, vl); } +// CHECK-RV64-LABEL: define dso_local @test_vlse16_v_f16mf4_mu +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[MASKEDOFF:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[BSTRIDE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vlse.mask.nxv1f16.i64( [[MASKEDOFF]], ptr [[BASE]], i64 [[BSTRIDE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vfloat16mf4_t test_vlse16_v_f16mf4_mu(vbool64_t mask, vfloat16mf4_t maskedoff, const _Float16 *base, ptrdiff_t bstride, size_t vl) { + return __riscv_vlse16_mu(mask, maskedoff, base, bstride, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vlse16_v_f16mf2_mu +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[MASKEDOFF:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[BSTRIDE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vlse.mask.nxv2f16.i64( [[MASKEDOFF]], ptr [[BASE]], i64 [[BSTRIDE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vfloat16mf2_t test_vlse16_v_f16mf2_mu(vbool32_t mask, vfloat16mf2_t maskedoff, const _Float16 *base, ptrdiff_t bstride, size_t vl) { + return __riscv_vlse16_mu(mask, maskedoff, base, bstride, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vlse16_v_f16m1_mu +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[MASKEDOFF:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[BSTRIDE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vlse.mask.nxv4f16.i64( [[MASKEDOFF]], ptr [[BASE]], i64 [[BSTRIDE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vfloat16m1_t test_vlse16_v_f16m1_mu(vbool16_t mask, vfloat16m1_t maskedoff, const _Float16 *base, ptrdiff_t bstride, size_t vl) { + return __riscv_vlse16_mu(mask, maskedoff, base, bstride, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vlse16_v_f16m2_mu +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[MASKEDOFF:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[BSTRIDE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vlse.mask.nxv8f16.i64( [[MASKEDOFF]], ptr [[BASE]], i64 [[BSTRIDE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vfloat16m2_t test_vlse16_v_f16m2_mu(vbool8_t mask, vfloat16m2_t maskedoff, const _Float16 *base, ptrdiff_t bstride, size_t vl) { + return __riscv_vlse16_mu(mask, maskedoff, base, bstride, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vlse16_v_f16m4_mu +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[MASKEDOFF:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[BSTRIDE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vlse.mask.nxv16f16.i64( [[MASKEDOFF]], ptr [[BASE]], i64 [[BSTRIDE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vfloat16m4_t test_vlse16_v_f16m4_mu(vbool4_t mask, vfloat16m4_t maskedoff, const _Float16 *base, ptrdiff_t bstride, size_t vl) { + return __riscv_vlse16_mu(mask, maskedoff, base, bstride, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vlse16_v_f16m8_mu +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[MASKEDOFF:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[BSTRIDE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vlse.mask.nxv32f16.i64( [[MASKEDOFF]], ptr [[BASE]], i64 [[BSTRIDE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vfloat16m8_t test_vlse16_v_f16m8_mu(vbool2_t mask, vfloat16m8_t maskedoff, const _Float16 *base, ptrdiff_t bstride, size_t vl) { + return __riscv_vlse16_mu(mask, maskedoff, base, bstride, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vlse16_v_i16mf4_mu +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[MASKEDOFF:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[BSTRIDE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vlse.mask.nxv1i16.i64( [[MASKEDOFF]], ptr [[BASE]], i64 [[BSTRIDE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint16mf4_t test_vlse16_v_i16mf4_mu(vbool64_t mask, vint16mf4_t maskedoff, const int16_t *base, ptrdiff_t bstride, size_t vl) { + return __riscv_vlse16_mu(mask, maskedoff, base, bstride, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vlse16_v_i16mf2_mu +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[MASKEDOFF:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[BSTRIDE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vlse.mask.nxv2i16.i64( [[MASKEDOFF]], ptr [[BASE]], i64 [[BSTRIDE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint16mf2_t test_vlse16_v_i16mf2_mu(vbool32_t mask, vint16mf2_t maskedoff, const int16_t *base, ptrdiff_t bstride, size_t vl) { + return __riscv_vlse16_mu(mask, maskedoff, base, bstride, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vlse16_v_i16m1_mu +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[MASKEDOFF:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[BSTRIDE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vlse.mask.nxv4i16.i64( [[MASKEDOFF]], ptr [[BASE]], i64 [[BSTRIDE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint16m1_t test_vlse16_v_i16m1_mu(vbool16_t mask, vint16m1_t maskedoff, const int16_t *base, ptrdiff_t bstride, size_t vl) { + return __riscv_vlse16_mu(mask, maskedoff, base, bstride, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vlse16_v_i16m2_mu +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[MASKEDOFF:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[BSTRIDE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vlse.mask.nxv8i16.i64( [[MASKEDOFF]], ptr [[BASE]], i64 [[BSTRIDE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint16m2_t test_vlse16_v_i16m2_mu(vbool8_t mask, vint16m2_t maskedoff, const int16_t *base, ptrdiff_t bstride, size_t vl) { + return __riscv_vlse16_mu(mask, maskedoff, base, bstride, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vlse16_v_i16m4_mu +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[MASKEDOFF:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[BSTRIDE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vlse.mask.nxv16i16.i64( [[MASKEDOFF]], ptr [[BASE]], i64 [[BSTRIDE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint16m4_t test_vlse16_v_i16m4_mu(vbool4_t mask, vint16m4_t maskedoff, const int16_t *base, ptrdiff_t bstride, size_t vl) { + return __riscv_vlse16_mu(mask, maskedoff, base, bstride, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vlse16_v_i16m8_mu +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[MASKEDOFF:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[BSTRIDE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vlse.mask.nxv32i16.i64( [[MASKEDOFF]], ptr [[BASE]], i64 [[BSTRIDE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint16m8_t test_vlse16_v_i16m8_mu(vbool2_t mask, vint16m8_t maskedoff, const int16_t *base, ptrdiff_t bstride, size_t vl) { + return __riscv_vlse16_mu(mask, maskedoff, base, bstride, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vlse16_v_u16mf4_mu +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[MASKEDOFF:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[BSTRIDE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vlse.mask.nxv1i16.i64( [[MASKEDOFF]], ptr [[BASE]], i64 [[BSTRIDE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint16mf4_t test_vlse16_v_u16mf4_mu(vbool64_t mask, vuint16mf4_t maskedoff, const uint16_t *base, ptrdiff_t bstride, size_t vl) { + return __riscv_vlse16_mu(mask, maskedoff, base, bstride, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vlse16_v_u16mf2_mu +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[MASKEDOFF:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[BSTRIDE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vlse.mask.nxv2i16.i64( [[MASKEDOFF]], ptr [[BASE]], i64 [[BSTRIDE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint16mf2_t test_vlse16_v_u16mf2_mu(vbool32_t mask, vuint16mf2_t maskedoff, const uint16_t *base, ptrdiff_t bstride, size_t vl) { + return __riscv_vlse16_mu(mask, maskedoff, base, bstride, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vlse16_v_u16m1_mu +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[MASKEDOFF:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[BSTRIDE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vlse.mask.nxv4i16.i64( [[MASKEDOFF]], ptr [[BASE]], i64 [[BSTRIDE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint16m1_t test_vlse16_v_u16m1_mu(vbool16_t mask, vuint16m1_t maskedoff, const uint16_t *base, ptrdiff_t bstride, size_t vl) { + return __riscv_vlse16_mu(mask, maskedoff, base, bstride, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vlse16_v_u16m2_mu +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[MASKEDOFF:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[BSTRIDE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vlse.mask.nxv8i16.i64( [[MASKEDOFF]], ptr [[BASE]], i64 [[BSTRIDE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint16m2_t test_vlse16_v_u16m2_mu(vbool8_t mask, vuint16m2_t maskedoff, const uint16_t *base, ptrdiff_t bstride, size_t vl) { + return __riscv_vlse16_mu(mask, maskedoff, base, bstride, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vlse16_v_u16m4_mu +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[MASKEDOFF:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[BSTRIDE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vlse.mask.nxv16i16.i64( [[MASKEDOFF]], ptr [[BASE]], i64 [[BSTRIDE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint16m4_t test_vlse16_v_u16m4_mu(vbool4_t mask, vuint16m4_t maskedoff, const uint16_t *base, ptrdiff_t bstride, size_t vl) { + return __riscv_vlse16_mu(mask, maskedoff, base, bstride, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vlse16_v_u16m8_mu +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[MASKEDOFF:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[BSTRIDE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vlse.mask.nxv32i16.i64( [[MASKEDOFF]], ptr [[BASE]], i64 [[BSTRIDE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint16m8_t test_vlse16_v_u16m8_mu(vbool2_t mask, vuint16m8_t maskedoff, const uint16_t *base, ptrdiff_t bstride, size_t vl) { + return __riscv_vlse16_mu(mask, maskedoff, base, bstride, vl); +} + diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlse32.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlse32.c index d880cd4d11553..2eca352a36385 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlse32.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlse32.c @@ -457,3 +457,153 @@ vuint32m8_t test_vlse32_v_u32m8_tumu(vbool4_t mask, vuint32m8_t maskedoff, const return __riscv_vlse32_tumu(mask, maskedoff, base, bstride, vl); } +// CHECK-RV64-LABEL: define dso_local @test_vlse32_v_f32mf2_mu +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[MASKEDOFF:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[BSTRIDE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vlse.mask.nxv1f32.i64( [[MASKEDOFF]], ptr [[BASE]], i64 [[BSTRIDE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vfloat32mf2_t test_vlse32_v_f32mf2_mu(vbool64_t mask, vfloat32mf2_t maskedoff, const float *base, ptrdiff_t bstride, size_t vl) { + return __riscv_vlse32_mu(mask, maskedoff, base, bstride, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vlse32_v_f32m1_mu +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[MASKEDOFF:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[BSTRIDE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vlse.mask.nxv2f32.i64( [[MASKEDOFF]], ptr [[BASE]], i64 [[BSTRIDE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vfloat32m1_t test_vlse32_v_f32m1_mu(vbool32_t mask, vfloat32m1_t maskedoff, const float *base, ptrdiff_t bstride, size_t vl) { + return __riscv_vlse32_mu(mask, maskedoff, base, bstride, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vlse32_v_f32m2_mu +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[MASKEDOFF:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[BSTRIDE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vlse.mask.nxv4f32.i64( [[MASKEDOFF]], ptr [[BASE]], i64 [[BSTRIDE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vfloat32m2_t test_vlse32_v_f32m2_mu(vbool16_t mask, vfloat32m2_t maskedoff, const float *base, ptrdiff_t bstride, size_t vl) { + return __riscv_vlse32_mu(mask, maskedoff, base, bstride, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vlse32_v_f32m4_mu +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[MASKEDOFF:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[BSTRIDE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vlse.mask.nxv8f32.i64( [[MASKEDOFF]], ptr [[BASE]], i64 [[BSTRIDE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vfloat32m4_t test_vlse32_v_f32m4_mu(vbool8_t mask, vfloat32m4_t maskedoff, const float *base, ptrdiff_t bstride, size_t vl) { + return __riscv_vlse32_mu(mask, maskedoff, base, bstride, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vlse32_v_f32m8_mu +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[MASKEDOFF:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[BSTRIDE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vlse.mask.nxv16f32.i64( [[MASKEDOFF]], ptr [[BASE]], i64 [[BSTRIDE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vfloat32m8_t test_vlse32_v_f32m8_mu(vbool4_t mask, vfloat32m8_t maskedoff, const float *base, ptrdiff_t bstride, size_t vl) { + return __riscv_vlse32_mu(mask, maskedoff, base, bstride, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vlse32_v_i32mf2_mu +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[MASKEDOFF:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[BSTRIDE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vlse.mask.nxv1i32.i64( [[MASKEDOFF]], ptr [[BASE]], i64 [[BSTRIDE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint32mf2_t test_vlse32_v_i32mf2_mu(vbool64_t mask, vint32mf2_t maskedoff, const int32_t *base, ptrdiff_t bstride, size_t vl) { + return __riscv_vlse32_mu(mask, maskedoff, base, bstride, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vlse32_v_i32m1_mu +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[MASKEDOFF:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[BSTRIDE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vlse.mask.nxv2i32.i64( [[MASKEDOFF]], ptr [[BASE]], i64 [[BSTRIDE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint32m1_t test_vlse32_v_i32m1_mu(vbool32_t mask, vint32m1_t maskedoff, const int32_t *base, ptrdiff_t bstride, size_t vl) { + return __riscv_vlse32_mu(mask, maskedoff, base, bstride, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vlse32_v_i32m2_mu +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[MASKEDOFF:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[BSTRIDE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vlse.mask.nxv4i32.i64( [[MASKEDOFF]], ptr [[BASE]], i64 [[BSTRIDE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint32m2_t test_vlse32_v_i32m2_mu(vbool16_t mask, vint32m2_t maskedoff, const int32_t *base, ptrdiff_t bstride, size_t vl) { + return __riscv_vlse32_mu(mask, maskedoff, base, bstride, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vlse32_v_i32m4_mu +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[MASKEDOFF:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[BSTRIDE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vlse.mask.nxv8i32.i64( [[MASKEDOFF]], ptr [[BASE]], i64 [[BSTRIDE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint32m4_t test_vlse32_v_i32m4_mu(vbool8_t mask, vint32m4_t maskedoff, const int32_t *base, ptrdiff_t bstride, size_t vl) { + return __riscv_vlse32_mu(mask, maskedoff, base, bstride, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vlse32_v_i32m8_mu +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[MASKEDOFF:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[BSTRIDE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vlse.mask.nxv16i32.i64( [[MASKEDOFF]], ptr [[BASE]], i64 [[BSTRIDE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint32m8_t test_vlse32_v_i32m8_mu(vbool4_t mask, vint32m8_t maskedoff, const int32_t *base, ptrdiff_t bstride, size_t vl) { + return __riscv_vlse32_mu(mask, maskedoff, base, bstride, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vlse32_v_u32mf2_mu +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[MASKEDOFF:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[BSTRIDE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vlse.mask.nxv1i32.i64( [[MASKEDOFF]], ptr [[BASE]], i64 [[BSTRIDE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint32mf2_t test_vlse32_v_u32mf2_mu(vbool64_t mask, vuint32mf2_t maskedoff, const uint32_t *base, ptrdiff_t bstride, size_t vl) { + return __riscv_vlse32_mu(mask, maskedoff, base, bstride, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vlse32_v_u32m1_mu +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[MASKEDOFF:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[BSTRIDE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vlse.mask.nxv2i32.i64( [[MASKEDOFF]], ptr [[BASE]], i64 [[BSTRIDE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint32m1_t test_vlse32_v_u32m1_mu(vbool32_t mask, vuint32m1_t maskedoff, const uint32_t *base, ptrdiff_t bstride, size_t vl) { + return __riscv_vlse32_mu(mask, maskedoff, base, bstride, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vlse32_v_u32m2_mu +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[MASKEDOFF:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[BSTRIDE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vlse.mask.nxv4i32.i64( [[MASKEDOFF]], ptr [[BASE]], i64 [[BSTRIDE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint32m2_t test_vlse32_v_u32m2_mu(vbool16_t mask, vuint32m2_t maskedoff, const uint32_t *base, ptrdiff_t bstride, size_t vl) { + return __riscv_vlse32_mu(mask, maskedoff, base, bstride, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vlse32_v_u32m4_mu +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[MASKEDOFF:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[BSTRIDE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vlse.mask.nxv8i32.i64( [[MASKEDOFF]], ptr [[BASE]], i64 [[BSTRIDE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint32m4_t test_vlse32_v_u32m4_mu(vbool8_t mask, vuint32m4_t maskedoff, const uint32_t *base, ptrdiff_t bstride, size_t vl) { + return __riscv_vlse32_mu(mask, maskedoff, base, bstride, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vlse32_v_u32m8_mu +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[MASKEDOFF:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[BSTRIDE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vlse.mask.nxv16i32.i64( [[MASKEDOFF]], ptr [[BASE]], i64 [[BSTRIDE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint32m8_t test_vlse32_v_u32m8_mu(vbool4_t mask, vuint32m8_t maskedoff, const uint32_t *base, ptrdiff_t bstride, size_t vl) { + return __riscv_vlse32_mu(mask, maskedoff, base, bstride, vl); +} + diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlse64.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlse64.c index 434168c95cada..6ec1e01fa34e2 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlse64.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlse64.c @@ -367,3 +367,123 @@ vuint64m8_t test_vlse64_v_u64m8_tumu(vbool8_t mask, vuint64m8_t maskedoff, const return __riscv_vlse64_tumu(mask, maskedoff, base, bstride, vl); } +// CHECK-RV64-LABEL: define dso_local @test_vlse64_v_f64m1_mu +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[MASKEDOFF:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[BSTRIDE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vlse.mask.nxv1f64.i64( [[MASKEDOFF]], ptr [[BASE]], i64 [[BSTRIDE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vfloat64m1_t test_vlse64_v_f64m1_mu(vbool64_t mask, vfloat64m1_t maskedoff, const double *base, ptrdiff_t bstride, size_t vl) { + return __riscv_vlse64_mu(mask, maskedoff, base, bstride, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vlse64_v_f64m2_mu +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[MASKEDOFF:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[BSTRIDE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vlse.mask.nxv2f64.i64( [[MASKEDOFF]], ptr [[BASE]], i64 [[BSTRIDE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vfloat64m2_t test_vlse64_v_f64m2_mu(vbool32_t mask, vfloat64m2_t maskedoff, const double *base, ptrdiff_t bstride, size_t vl) { + return __riscv_vlse64_mu(mask, maskedoff, base, bstride, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vlse64_v_f64m4_mu +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[MASKEDOFF:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[BSTRIDE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vlse.mask.nxv4f64.i64( [[MASKEDOFF]], ptr [[BASE]], i64 [[BSTRIDE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vfloat64m4_t test_vlse64_v_f64m4_mu(vbool16_t mask, vfloat64m4_t maskedoff, const double *base, ptrdiff_t bstride, size_t vl) { + return __riscv_vlse64_mu(mask, maskedoff, base, bstride, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vlse64_v_f64m8_mu +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[MASKEDOFF:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[BSTRIDE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vlse.mask.nxv8f64.i64( [[MASKEDOFF]], ptr [[BASE]], i64 [[BSTRIDE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vfloat64m8_t test_vlse64_v_f64m8_mu(vbool8_t mask, vfloat64m8_t maskedoff, const double *base, ptrdiff_t bstride, size_t vl) { + return __riscv_vlse64_mu(mask, maskedoff, base, bstride, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vlse64_v_i64m1_mu +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[MASKEDOFF:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[BSTRIDE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vlse.mask.nxv1i64.i64( [[MASKEDOFF]], ptr [[BASE]], i64 [[BSTRIDE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint64m1_t test_vlse64_v_i64m1_mu(vbool64_t mask, vint64m1_t maskedoff, const int64_t *base, ptrdiff_t bstride, size_t vl) { + return __riscv_vlse64_mu(mask, maskedoff, base, bstride, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vlse64_v_i64m2_mu +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[MASKEDOFF:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[BSTRIDE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vlse.mask.nxv2i64.i64( [[MASKEDOFF]], ptr [[BASE]], i64 [[BSTRIDE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint64m2_t test_vlse64_v_i64m2_mu(vbool32_t mask, vint64m2_t maskedoff, const int64_t *base, ptrdiff_t bstride, size_t vl) { + return __riscv_vlse64_mu(mask, maskedoff, base, bstride, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vlse64_v_i64m4_mu +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[MASKEDOFF:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[BSTRIDE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vlse.mask.nxv4i64.i64( [[MASKEDOFF]], ptr [[BASE]], i64 [[BSTRIDE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint64m4_t test_vlse64_v_i64m4_mu(vbool16_t mask, vint64m4_t maskedoff, const int64_t *base, ptrdiff_t bstride, size_t vl) { + return __riscv_vlse64_mu(mask, maskedoff, base, bstride, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vlse64_v_i64m8_mu +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[MASKEDOFF:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[BSTRIDE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vlse.mask.nxv8i64.i64( [[MASKEDOFF]], ptr [[BASE]], i64 [[BSTRIDE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint64m8_t test_vlse64_v_i64m8_mu(vbool8_t mask, vint64m8_t maskedoff, const int64_t *base, ptrdiff_t bstride, size_t vl) { + return __riscv_vlse64_mu(mask, maskedoff, base, bstride, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vlse64_v_u64m1_mu +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[MASKEDOFF:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[BSTRIDE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vlse.mask.nxv1i64.i64( [[MASKEDOFF]], ptr [[BASE]], i64 [[BSTRIDE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint64m1_t test_vlse64_v_u64m1_mu(vbool64_t mask, vuint64m1_t maskedoff, const uint64_t *base, ptrdiff_t bstride, size_t vl) { + return __riscv_vlse64_mu(mask, maskedoff, base, bstride, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vlse64_v_u64m2_mu +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[MASKEDOFF:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[BSTRIDE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vlse.mask.nxv2i64.i64( [[MASKEDOFF]], ptr [[BASE]], i64 [[BSTRIDE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint64m2_t test_vlse64_v_u64m2_mu(vbool32_t mask, vuint64m2_t maskedoff, const uint64_t *base, ptrdiff_t bstride, size_t vl) { + return __riscv_vlse64_mu(mask, maskedoff, base, bstride, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vlse64_v_u64m4_mu +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[MASKEDOFF:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[BSTRIDE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vlse.mask.nxv4i64.i64( [[MASKEDOFF]], ptr [[BASE]], i64 [[BSTRIDE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint64m4_t test_vlse64_v_u64m4_mu(vbool16_t mask, vuint64m4_t maskedoff, const uint64_t *base, ptrdiff_t bstride, size_t vl) { + return __riscv_vlse64_mu(mask, maskedoff, base, bstride, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vlse64_v_u64m8_mu +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[MASKEDOFF:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[BSTRIDE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vlse.mask.nxv8i64.i64( [[MASKEDOFF]], ptr [[BASE]], i64 [[BSTRIDE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint64m8_t test_vlse64_v_u64m8_mu(vbool8_t mask, vuint64m8_t maskedoff, const uint64_t *base, ptrdiff_t bstride, size_t vl) { + return __riscv_vlse64_mu(mask, maskedoff, base, bstride, vl); +} + diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlse8.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlse8.c index 08d00b0adeace..bab9c58d7c76a 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlse8.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlse8.c @@ -426,3 +426,143 @@ vuint8m8_t test_vlse8_v_u8m8_tumu(vbool1_t mask, vuint8m8_t maskedoff, const uin return __riscv_vlse8_tumu(mask, maskedoff, base, bstride, vl); } +// CHECK-RV64-LABEL: define dso_local @test_vlse8_v_i8mf8_mu +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[MASKEDOFF:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[BSTRIDE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vlse.mask.nxv1i8.i64( [[MASKEDOFF]], ptr [[BASE]], i64 [[BSTRIDE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint8mf8_t test_vlse8_v_i8mf8_mu(vbool64_t mask, vint8mf8_t maskedoff, const int8_t *base, ptrdiff_t bstride, size_t vl) { + return __riscv_vlse8_mu(mask, maskedoff, base, bstride, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vlse8_v_i8mf4_mu +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[MASKEDOFF:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[BSTRIDE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vlse.mask.nxv2i8.i64( [[MASKEDOFF]], ptr [[BASE]], i64 [[BSTRIDE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint8mf4_t test_vlse8_v_i8mf4_mu(vbool32_t mask, vint8mf4_t maskedoff, const int8_t *base, ptrdiff_t bstride, size_t vl) { + return __riscv_vlse8_mu(mask, maskedoff, base, bstride, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vlse8_v_i8mf2_mu +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[MASKEDOFF:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[BSTRIDE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vlse.mask.nxv4i8.i64( [[MASKEDOFF]], ptr [[BASE]], i64 [[BSTRIDE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint8mf2_t test_vlse8_v_i8mf2_mu(vbool16_t mask, vint8mf2_t maskedoff, const int8_t *base, ptrdiff_t bstride, size_t vl) { + return __riscv_vlse8_mu(mask, maskedoff, base, bstride, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vlse8_v_i8m1_mu +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[MASKEDOFF:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[BSTRIDE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vlse.mask.nxv8i8.i64( [[MASKEDOFF]], ptr [[BASE]], i64 [[BSTRIDE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint8m1_t test_vlse8_v_i8m1_mu(vbool8_t mask, vint8m1_t maskedoff, const int8_t *base, ptrdiff_t bstride, size_t vl) { + return __riscv_vlse8_mu(mask, maskedoff, base, bstride, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vlse8_v_i8m2_mu +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[MASKEDOFF:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[BSTRIDE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vlse.mask.nxv16i8.i64( [[MASKEDOFF]], ptr [[BASE]], i64 [[BSTRIDE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint8m2_t test_vlse8_v_i8m2_mu(vbool4_t mask, vint8m2_t maskedoff, const int8_t *base, ptrdiff_t bstride, size_t vl) { + return __riscv_vlse8_mu(mask, maskedoff, base, bstride, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vlse8_v_i8m4_mu +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[MASKEDOFF:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[BSTRIDE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vlse.mask.nxv32i8.i64( [[MASKEDOFF]], ptr [[BASE]], i64 [[BSTRIDE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint8m4_t test_vlse8_v_i8m4_mu(vbool2_t mask, vint8m4_t maskedoff, const int8_t *base, ptrdiff_t bstride, size_t vl) { + return __riscv_vlse8_mu(mask, maskedoff, base, bstride, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vlse8_v_i8m8_mu +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[MASKEDOFF:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[BSTRIDE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vlse.mask.nxv64i8.i64( [[MASKEDOFF]], ptr [[BASE]], i64 [[BSTRIDE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint8m8_t test_vlse8_v_i8m8_mu(vbool1_t mask, vint8m8_t maskedoff, const int8_t *base, ptrdiff_t bstride, size_t vl) { + return __riscv_vlse8_mu(mask, maskedoff, base, bstride, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vlse8_v_u8mf8_mu +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[MASKEDOFF:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[BSTRIDE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vlse.mask.nxv1i8.i64( [[MASKEDOFF]], ptr [[BASE]], i64 [[BSTRIDE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint8mf8_t test_vlse8_v_u8mf8_mu(vbool64_t mask, vuint8mf8_t maskedoff, const uint8_t *base, ptrdiff_t bstride, size_t vl) { + return __riscv_vlse8_mu(mask, maskedoff, base, bstride, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vlse8_v_u8mf4_mu +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[MASKEDOFF:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[BSTRIDE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vlse.mask.nxv2i8.i64( [[MASKEDOFF]], ptr [[BASE]], i64 [[BSTRIDE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint8mf4_t test_vlse8_v_u8mf4_mu(vbool32_t mask, vuint8mf4_t maskedoff, const uint8_t *base, ptrdiff_t bstride, size_t vl) { + return __riscv_vlse8_mu(mask, maskedoff, base, bstride, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vlse8_v_u8mf2_mu +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[MASKEDOFF:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[BSTRIDE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vlse.mask.nxv4i8.i64( [[MASKEDOFF]], ptr [[BASE]], i64 [[BSTRIDE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint8mf2_t test_vlse8_v_u8mf2_mu(vbool16_t mask, vuint8mf2_t maskedoff, const uint8_t *base, ptrdiff_t bstride, size_t vl) { + return __riscv_vlse8_mu(mask, maskedoff, base, bstride, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vlse8_v_u8m1_mu +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[MASKEDOFF:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[BSTRIDE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vlse.mask.nxv8i8.i64( [[MASKEDOFF]], ptr [[BASE]], i64 [[BSTRIDE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint8m1_t test_vlse8_v_u8m1_mu(vbool8_t mask, vuint8m1_t maskedoff, const uint8_t *base, ptrdiff_t bstride, size_t vl) { + return __riscv_vlse8_mu(mask, maskedoff, base, bstride, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vlse8_v_u8m2_mu +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[MASKEDOFF:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[BSTRIDE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vlse.mask.nxv16i8.i64( [[MASKEDOFF]], ptr [[BASE]], i64 [[BSTRIDE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint8m2_t test_vlse8_v_u8m2_mu(vbool4_t mask, vuint8m2_t maskedoff, const uint8_t *base, ptrdiff_t bstride, size_t vl) { + return __riscv_vlse8_mu(mask, maskedoff, base, bstride, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vlse8_v_u8m4_mu +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[MASKEDOFF:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[BSTRIDE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vlse.mask.nxv32i8.i64( [[MASKEDOFF]], ptr [[BASE]], i64 [[BSTRIDE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint8m4_t test_vlse8_v_u8m4_mu(vbool2_t mask, vuint8m4_t maskedoff, const uint8_t *base, ptrdiff_t bstride, size_t vl) { + return __riscv_vlse8_mu(mask, maskedoff, base, bstride, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vlse8_v_u8m8_mu +// CHECK-RV64-SAME: ( [[MASK:%.*]], [[MASKEDOFF:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[BSTRIDE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vlse.mask.nxv64i8.i64( [[MASKEDOFF]], ptr [[BASE]], i64 [[BSTRIDE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint8m8_t test_vlse8_v_u8m8_mu(vbool1_t mask, vuint8m8_t maskedoff, const uint8_t *base, ptrdiff_t bstride, size_t vl) { + return __riscv_vlse8_mu(mask, maskedoff, base, bstride, vl); +} + diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e16.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e16.c index 01c300b112629..a2ea835b6dcd2 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e16.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e16.c @@ -637,3 +637,213 @@ void test_vlseg2e16_v_u16m4_tumu(vuint16m4_t *v0, vuint16m4_t *v1, vbool4_t mask return __riscv_vlseg2e16_tumu(v0, v1, mask, maskedoff0, maskedoff1, base, vl); } +// CHECK-RV64-LABEL: define dso_local void @test_vlseg2e16_v_f16mf4_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vlseg2.mask.nxv1f16.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 2 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 2 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg2e16_v_f16mf4_mu(vfloat16mf4_t *v0, vfloat16mf4_t *v1, vbool64_t mask, vfloat16mf4_t maskedoff0, vfloat16mf4_t maskedoff1, const _Float16 *base, size_t vl) { + return __riscv_vlseg2e16_mu(v0, v1, mask, maskedoff0, maskedoff1, base, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlseg2e16_v_f16mf2_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vlseg2.mask.nxv2f16.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 2 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 2 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg2e16_v_f16mf2_mu(vfloat16mf2_t *v0, vfloat16mf2_t *v1, vbool32_t mask, vfloat16mf2_t maskedoff0, vfloat16mf2_t maskedoff1, const _Float16 *base, size_t vl) { + return __riscv_vlseg2e16_mu(v0, v1, mask, maskedoff0, maskedoff1, base, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlseg2e16_v_f16m1_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vlseg2.mask.nxv4f16.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 2 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 2 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg2e16_v_f16m1_mu(vfloat16m1_t *v0, vfloat16m1_t *v1, vbool16_t mask, vfloat16m1_t maskedoff0, vfloat16m1_t maskedoff1, const _Float16 *base, size_t vl) { + return __riscv_vlseg2e16_mu(v0, v1, mask, maskedoff0, maskedoff1, base, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlseg2e16_v_f16m2_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vlseg2.mask.nxv8f16.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 2 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 2 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg2e16_v_f16m2_mu(vfloat16m2_t *v0, vfloat16m2_t *v1, vbool8_t mask, vfloat16m2_t maskedoff0, vfloat16m2_t maskedoff1, const _Float16 *base, size_t vl) { + return __riscv_vlseg2e16_mu(v0, v1, mask, maskedoff0, maskedoff1, base, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlseg2e16_v_f16m4_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vlseg2.mask.nxv16f16.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 2 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 2 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg2e16_v_f16m4_mu(vfloat16m4_t *v0, vfloat16m4_t *v1, vbool4_t mask, vfloat16m4_t maskedoff0, vfloat16m4_t maskedoff1, const _Float16 *base, size_t vl) { + return __riscv_vlseg2e16_mu(v0, v1, mask, maskedoff0, maskedoff1, base, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlseg2e16_v_i16mf4_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vlseg2.mask.nxv1i16.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 2 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 2 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg2e16_v_i16mf4_mu(vint16mf4_t *v0, vint16mf4_t *v1, vbool64_t mask, vint16mf4_t maskedoff0, vint16mf4_t maskedoff1, const int16_t *base, size_t vl) { + return __riscv_vlseg2e16_mu(v0, v1, mask, maskedoff0, maskedoff1, base, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlseg2e16_v_i16mf2_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vlseg2.mask.nxv2i16.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 2 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 2 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg2e16_v_i16mf2_mu(vint16mf2_t *v0, vint16mf2_t *v1, vbool32_t mask, vint16mf2_t maskedoff0, vint16mf2_t maskedoff1, const int16_t *base, size_t vl) { + return __riscv_vlseg2e16_mu(v0, v1, mask, maskedoff0, maskedoff1, base, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlseg2e16_v_i16m1_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vlseg2.mask.nxv4i16.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 2 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 2 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg2e16_v_i16m1_mu(vint16m1_t *v0, vint16m1_t *v1, vbool16_t mask, vint16m1_t maskedoff0, vint16m1_t maskedoff1, const int16_t *base, size_t vl) { + return __riscv_vlseg2e16_mu(v0, v1, mask, maskedoff0, maskedoff1, base, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlseg2e16_v_i16m2_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vlseg2.mask.nxv8i16.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 2 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 2 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg2e16_v_i16m2_mu(vint16m2_t *v0, vint16m2_t *v1, vbool8_t mask, vint16m2_t maskedoff0, vint16m2_t maskedoff1, const int16_t *base, size_t vl) { + return __riscv_vlseg2e16_mu(v0, v1, mask, maskedoff0, maskedoff1, base, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlseg2e16_v_i16m4_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vlseg2.mask.nxv16i16.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 2 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 2 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg2e16_v_i16m4_mu(vint16m4_t *v0, vint16m4_t *v1, vbool4_t mask, vint16m4_t maskedoff0, vint16m4_t maskedoff1, const int16_t *base, size_t vl) { + return __riscv_vlseg2e16_mu(v0, v1, mask, maskedoff0, maskedoff1, base, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlseg2e16_v_u16mf4_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vlseg2.mask.nxv1i16.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 2 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 2 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg2e16_v_u16mf4_mu(vuint16mf4_t *v0, vuint16mf4_t *v1, vbool64_t mask, vuint16mf4_t maskedoff0, vuint16mf4_t maskedoff1, const uint16_t *base, size_t vl) { + return __riscv_vlseg2e16_mu(v0, v1, mask, maskedoff0, maskedoff1, base, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlseg2e16_v_u16mf2_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vlseg2.mask.nxv2i16.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 2 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 2 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg2e16_v_u16mf2_mu(vuint16mf2_t *v0, vuint16mf2_t *v1, vbool32_t mask, vuint16mf2_t maskedoff0, vuint16mf2_t maskedoff1, const uint16_t *base, size_t vl) { + return __riscv_vlseg2e16_mu(v0, v1, mask, maskedoff0, maskedoff1, base, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlseg2e16_v_u16m1_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vlseg2.mask.nxv4i16.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 2 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 2 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg2e16_v_u16m1_mu(vuint16m1_t *v0, vuint16m1_t *v1, vbool16_t mask, vuint16m1_t maskedoff0, vuint16m1_t maskedoff1, const uint16_t *base, size_t vl) { + return __riscv_vlseg2e16_mu(v0, v1, mask, maskedoff0, maskedoff1, base, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlseg2e16_v_u16m2_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vlseg2.mask.nxv8i16.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 2 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 2 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg2e16_v_u16m2_mu(vuint16m2_t *v0, vuint16m2_t *v1, vbool8_t mask, vuint16m2_t maskedoff0, vuint16m2_t maskedoff1, const uint16_t *base, size_t vl) { + return __riscv_vlseg2e16_mu(v0, v1, mask, maskedoff0, maskedoff1, base, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlseg2e16_v_u16m4_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vlseg2.mask.nxv16i16.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 2 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 2 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg2e16_v_u16m4_mu(vuint16m4_t *v0, vuint16m4_t *v1, vbool4_t mask, vuint16m4_t maskedoff0, vuint16m4_t maskedoff1, const uint16_t *base, size_t vl) { + return __riscv_vlseg2e16_mu(v0, v1, mask, maskedoff0, maskedoff1, base, vl); +} + diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e16ff.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e16ff.c index af5d2600cbb4f..46cb85f8beada 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e16ff.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e16ff.c @@ -727,3 +727,243 @@ void test_vlseg2e16ff_v_u16m4_tumu(vuint16m4_t *v0, vuint16m4_t *v1, vbool4_t ma return __riscv_vlseg2e16ff_tumu(v0, v1, mask, maskedoff0, maskedoff1, base, new_vl, vl); } +// CHECK-RV64-LABEL: define dso_local void @test_vlseg2e16ff_v_f16mf4_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , i64 } @llvm.riscv.vlseg2ff.mask.nxv1f16.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 2 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: store i64 [[TMP3]], ptr [[NEW_VL]], align 2 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg2e16ff_v_f16mf4_mu(vfloat16mf4_t *v0, vfloat16mf4_t *v1, vbool64_t mask, vfloat16mf4_t maskedoff0, vfloat16mf4_t maskedoff1, const _Float16 *base, size_t *new_vl, size_t vl) { + return __riscv_vlseg2e16ff_mu(v0, v1, mask, maskedoff0, maskedoff1, base, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlseg2e16ff_v_f16mf2_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , i64 } @llvm.riscv.vlseg2ff.mask.nxv2f16.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 2 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: store i64 [[TMP3]], ptr [[NEW_VL]], align 2 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg2e16ff_v_f16mf2_mu(vfloat16mf2_t *v0, vfloat16mf2_t *v1, vbool32_t mask, vfloat16mf2_t maskedoff0, vfloat16mf2_t maskedoff1, const _Float16 *base, size_t *new_vl, size_t vl) { + return __riscv_vlseg2e16ff_mu(v0, v1, mask, maskedoff0, maskedoff1, base, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlseg2e16ff_v_f16m1_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , i64 } @llvm.riscv.vlseg2ff.mask.nxv4f16.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 2 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: store i64 [[TMP3]], ptr [[NEW_VL]], align 2 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg2e16ff_v_f16m1_mu(vfloat16m1_t *v0, vfloat16m1_t *v1, vbool16_t mask, vfloat16m1_t maskedoff0, vfloat16m1_t maskedoff1, const _Float16 *base, size_t *new_vl, size_t vl) { + return __riscv_vlseg2e16ff_mu(v0, v1, mask, maskedoff0, maskedoff1, base, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlseg2e16ff_v_f16m2_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , i64 } @llvm.riscv.vlseg2ff.mask.nxv8f16.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 2 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: store i64 [[TMP3]], ptr [[NEW_VL]], align 2 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg2e16ff_v_f16m2_mu(vfloat16m2_t *v0, vfloat16m2_t *v1, vbool8_t mask, vfloat16m2_t maskedoff0, vfloat16m2_t maskedoff1, const _Float16 *base, size_t *new_vl, size_t vl) { + return __riscv_vlseg2e16ff_mu(v0, v1, mask, maskedoff0, maskedoff1, base, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlseg2e16ff_v_f16m4_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , i64 } @llvm.riscv.vlseg2ff.mask.nxv16f16.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 2 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: store i64 [[TMP3]], ptr [[NEW_VL]], align 2 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg2e16ff_v_f16m4_mu(vfloat16m4_t *v0, vfloat16m4_t *v1, vbool4_t mask, vfloat16m4_t maskedoff0, vfloat16m4_t maskedoff1, const _Float16 *base, size_t *new_vl, size_t vl) { + return __riscv_vlseg2e16ff_mu(v0, v1, mask, maskedoff0, maskedoff1, base, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlseg2e16ff_v_i16mf4_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , i64 } @llvm.riscv.vlseg2ff.mask.nxv1i16.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 2 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: store i64 [[TMP3]], ptr [[NEW_VL]], align 2 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg2e16ff_v_i16mf4_mu(vint16mf4_t *v0, vint16mf4_t *v1, vbool64_t mask, vint16mf4_t maskedoff0, vint16mf4_t maskedoff1, const int16_t *base, size_t *new_vl, size_t vl) { + return __riscv_vlseg2e16ff_mu(v0, v1, mask, maskedoff0, maskedoff1, base, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlseg2e16ff_v_i16mf2_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , i64 } @llvm.riscv.vlseg2ff.mask.nxv2i16.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 2 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: store i64 [[TMP3]], ptr [[NEW_VL]], align 2 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg2e16ff_v_i16mf2_mu(vint16mf2_t *v0, vint16mf2_t *v1, vbool32_t mask, vint16mf2_t maskedoff0, vint16mf2_t maskedoff1, const int16_t *base, size_t *new_vl, size_t vl) { + return __riscv_vlseg2e16ff_mu(v0, v1, mask, maskedoff0, maskedoff1, base, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlseg2e16ff_v_i16m1_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , i64 } @llvm.riscv.vlseg2ff.mask.nxv4i16.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 2 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: store i64 [[TMP3]], ptr [[NEW_VL]], align 2 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg2e16ff_v_i16m1_mu(vint16m1_t *v0, vint16m1_t *v1, vbool16_t mask, vint16m1_t maskedoff0, vint16m1_t maskedoff1, const int16_t *base, size_t *new_vl, size_t vl) { + return __riscv_vlseg2e16ff_mu(v0, v1, mask, maskedoff0, maskedoff1, base, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlseg2e16ff_v_i16m2_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , i64 } @llvm.riscv.vlseg2ff.mask.nxv8i16.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 2 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: store i64 [[TMP3]], ptr [[NEW_VL]], align 2 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg2e16ff_v_i16m2_mu(vint16m2_t *v0, vint16m2_t *v1, vbool8_t mask, vint16m2_t maskedoff0, vint16m2_t maskedoff1, const int16_t *base, size_t *new_vl, size_t vl) { + return __riscv_vlseg2e16ff_mu(v0, v1, mask, maskedoff0, maskedoff1, base, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlseg2e16ff_v_i16m4_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , i64 } @llvm.riscv.vlseg2ff.mask.nxv16i16.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 2 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: store i64 [[TMP3]], ptr [[NEW_VL]], align 2 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg2e16ff_v_i16m4_mu(vint16m4_t *v0, vint16m4_t *v1, vbool4_t mask, vint16m4_t maskedoff0, vint16m4_t maskedoff1, const int16_t *base, size_t *new_vl, size_t vl) { + return __riscv_vlseg2e16ff_mu(v0, v1, mask, maskedoff0, maskedoff1, base, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlseg2e16ff_v_u16mf4_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , i64 } @llvm.riscv.vlseg2ff.mask.nxv1i16.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 2 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: store i64 [[TMP3]], ptr [[NEW_VL]], align 2 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg2e16ff_v_u16mf4_mu(vuint16mf4_t *v0, vuint16mf4_t *v1, vbool64_t mask, vuint16mf4_t maskedoff0, vuint16mf4_t maskedoff1, const uint16_t *base, size_t *new_vl, size_t vl) { + return __riscv_vlseg2e16ff_mu(v0, v1, mask, maskedoff0, maskedoff1, base, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlseg2e16ff_v_u16mf2_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , i64 } @llvm.riscv.vlseg2ff.mask.nxv2i16.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 2 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: store i64 [[TMP3]], ptr [[NEW_VL]], align 2 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg2e16ff_v_u16mf2_mu(vuint16mf2_t *v0, vuint16mf2_t *v1, vbool32_t mask, vuint16mf2_t maskedoff0, vuint16mf2_t maskedoff1, const uint16_t *base, size_t *new_vl, size_t vl) { + return __riscv_vlseg2e16ff_mu(v0, v1, mask, maskedoff0, maskedoff1, base, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlseg2e16ff_v_u16m1_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , i64 } @llvm.riscv.vlseg2ff.mask.nxv4i16.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 2 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: store i64 [[TMP3]], ptr [[NEW_VL]], align 2 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg2e16ff_v_u16m1_mu(vuint16m1_t *v0, vuint16m1_t *v1, vbool16_t mask, vuint16m1_t maskedoff0, vuint16m1_t maskedoff1, const uint16_t *base, size_t *new_vl, size_t vl) { + return __riscv_vlseg2e16ff_mu(v0, v1, mask, maskedoff0, maskedoff1, base, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlseg2e16ff_v_u16m2_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , i64 } @llvm.riscv.vlseg2ff.mask.nxv8i16.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 2 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: store i64 [[TMP3]], ptr [[NEW_VL]], align 2 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg2e16ff_v_u16m2_mu(vuint16m2_t *v0, vuint16m2_t *v1, vbool8_t mask, vuint16m2_t maskedoff0, vuint16m2_t maskedoff1, const uint16_t *base, size_t *new_vl, size_t vl) { + return __riscv_vlseg2e16ff_mu(v0, v1, mask, maskedoff0, maskedoff1, base, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlseg2e16ff_v_u16m4_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , i64 } @llvm.riscv.vlseg2ff.mask.nxv16i16.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 2 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: store i64 [[TMP3]], ptr [[NEW_VL]], align 2 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg2e16ff_v_u16m4_mu(vuint16m4_t *v0, vuint16m4_t *v1, vbool4_t mask, vuint16m4_t maskedoff0, vuint16m4_t maskedoff1, const uint16_t *base, size_t *new_vl, size_t vl) { + return __riscv_vlseg2e16ff_mu(v0, v1, mask, maskedoff0, maskedoff1, base, new_vl, vl); +} + diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e32.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e32.c index 13d392edd48d7..3a8212efd02f1 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e32.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e32.c @@ -511,3 +511,171 @@ void test_vlseg2e32_v_u32m4_tumu(vuint32m4_t *v0, vuint32m4_t *v1, vbool8_t mask return __riscv_vlseg2e32_tumu(v0, v1, mask, maskedoff0, maskedoff1, base, vl); } +// CHECK-RV64-LABEL: define dso_local void @test_vlseg2e32_v_f32mf2_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vlseg2.mask.nxv1f32.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 4 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 4 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg2e32_v_f32mf2_mu(vfloat32mf2_t *v0, vfloat32mf2_t *v1, vbool64_t mask, vfloat32mf2_t maskedoff0, vfloat32mf2_t maskedoff1, const float *base, size_t vl) { + return __riscv_vlseg2e32_mu(v0, v1, mask, maskedoff0, maskedoff1, base, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlseg2e32_v_f32m1_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vlseg2.mask.nxv2f32.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 4 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 4 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg2e32_v_f32m1_mu(vfloat32m1_t *v0, vfloat32m1_t *v1, vbool32_t mask, vfloat32m1_t maskedoff0, vfloat32m1_t maskedoff1, const float *base, size_t vl) { + return __riscv_vlseg2e32_mu(v0, v1, mask, maskedoff0, maskedoff1, base, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlseg2e32_v_f32m2_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vlseg2.mask.nxv4f32.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 4 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 4 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg2e32_v_f32m2_mu(vfloat32m2_t *v0, vfloat32m2_t *v1, vbool16_t mask, vfloat32m2_t maskedoff0, vfloat32m2_t maskedoff1, const float *base, size_t vl) { + return __riscv_vlseg2e32_mu(v0, v1, mask, maskedoff0, maskedoff1, base, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlseg2e32_v_f32m4_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vlseg2.mask.nxv8f32.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 4 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 4 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg2e32_v_f32m4_mu(vfloat32m4_t *v0, vfloat32m4_t *v1, vbool8_t mask, vfloat32m4_t maskedoff0, vfloat32m4_t maskedoff1, const float *base, size_t vl) { + return __riscv_vlseg2e32_mu(v0, v1, mask, maskedoff0, maskedoff1, base, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlseg2e32_v_i32mf2_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vlseg2.mask.nxv1i32.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 4 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 4 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg2e32_v_i32mf2_mu(vint32mf2_t *v0, vint32mf2_t *v1, vbool64_t mask, vint32mf2_t maskedoff0, vint32mf2_t maskedoff1, const int32_t *base, size_t vl) { + return __riscv_vlseg2e32_mu(v0, v1, mask, maskedoff0, maskedoff1, base, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlseg2e32_v_i32m1_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vlseg2.mask.nxv2i32.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 4 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 4 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg2e32_v_i32m1_mu(vint32m1_t *v0, vint32m1_t *v1, vbool32_t mask, vint32m1_t maskedoff0, vint32m1_t maskedoff1, const int32_t *base, size_t vl) { + return __riscv_vlseg2e32_mu(v0, v1, mask, maskedoff0, maskedoff1, base, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlseg2e32_v_i32m2_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vlseg2.mask.nxv4i32.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 4 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 4 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg2e32_v_i32m2_mu(vint32m2_t *v0, vint32m2_t *v1, vbool16_t mask, vint32m2_t maskedoff0, vint32m2_t maskedoff1, const int32_t *base, size_t vl) { + return __riscv_vlseg2e32_mu(v0, v1, mask, maskedoff0, maskedoff1, base, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlseg2e32_v_i32m4_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vlseg2.mask.nxv8i32.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 4 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 4 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg2e32_v_i32m4_mu(vint32m4_t *v0, vint32m4_t *v1, vbool8_t mask, vint32m4_t maskedoff0, vint32m4_t maskedoff1, const int32_t *base, size_t vl) { + return __riscv_vlseg2e32_mu(v0, v1, mask, maskedoff0, maskedoff1, base, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlseg2e32_v_u32mf2_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vlseg2.mask.nxv1i32.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 4 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 4 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg2e32_v_u32mf2_mu(vuint32mf2_t *v0, vuint32mf2_t *v1, vbool64_t mask, vuint32mf2_t maskedoff0, vuint32mf2_t maskedoff1, const uint32_t *base, size_t vl) { + return __riscv_vlseg2e32_mu(v0, v1, mask, maskedoff0, maskedoff1, base, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlseg2e32_v_u32m1_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vlseg2.mask.nxv2i32.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 4 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 4 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg2e32_v_u32m1_mu(vuint32m1_t *v0, vuint32m1_t *v1, vbool32_t mask, vuint32m1_t maskedoff0, vuint32m1_t maskedoff1, const uint32_t *base, size_t vl) { + return __riscv_vlseg2e32_mu(v0, v1, mask, maskedoff0, maskedoff1, base, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlseg2e32_v_u32m2_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vlseg2.mask.nxv4i32.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 4 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 4 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg2e32_v_u32m2_mu(vuint32m2_t *v0, vuint32m2_t *v1, vbool16_t mask, vuint32m2_t maskedoff0, vuint32m2_t maskedoff1, const uint32_t *base, size_t vl) { + return __riscv_vlseg2e32_mu(v0, v1, mask, maskedoff0, maskedoff1, base, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlseg2e32_v_u32m4_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vlseg2.mask.nxv8i32.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 4 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 4 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg2e32_v_u32m4_mu(vuint32m4_t *v0, vuint32m4_t *v1, vbool8_t mask, vuint32m4_t maskedoff0, vuint32m4_t maskedoff1, const uint32_t *base, size_t vl) { + return __riscv_vlseg2e32_mu(v0, v1, mask, maskedoff0, maskedoff1, base, vl); +} + diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e32ff.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e32ff.c index 42a676453f9b1..7357452128834 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e32ff.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e32ff.c @@ -583,3 +583,195 @@ void test_vlseg2e32ff_v_u32m4_tumu(vuint32m4_t *v0, vuint32m4_t *v1, vbool8_t ma return __riscv_vlseg2e32ff_tumu(v0, v1, mask, maskedoff0, maskedoff1, base, new_vl, vl); } +// CHECK-RV64-LABEL: define dso_local void @test_vlseg2e32ff_v_f32mf2_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , i64 } @llvm.riscv.vlseg2ff.mask.nxv1f32.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 4 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 4 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: store i64 [[TMP3]], ptr [[NEW_VL]], align 4 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg2e32ff_v_f32mf2_mu(vfloat32mf2_t *v0, vfloat32mf2_t *v1, vbool64_t mask, vfloat32mf2_t maskedoff0, vfloat32mf2_t maskedoff1, const float *base, size_t *new_vl, size_t vl) { + return __riscv_vlseg2e32ff_mu(v0, v1, mask, maskedoff0, maskedoff1, base, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlseg2e32ff_v_f32m1_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , i64 } @llvm.riscv.vlseg2ff.mask.nxv2f32.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 4 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 4 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: store i64 [[TMP3]], ptr [[NEW_VL]], align 4 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg2e32ff_v_f32m1_mu(vfloat32m1_t *v0, vfloat32m1_t *v1, vbool32_t mask, vfloat32m1_t maskedoff0, vfloat32m1_t maskedoff1, const float *base, size_t *new_vl, size_t vl) { + return __riscv_vlseg2e32ff_mu(v0, v1, mask, maskedoff0, maskedoff1, base, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlseg2e32ff_v_f32m2_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , i64 } @llvm.riscv.vlseg2ff.mask.nxv4f32.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 4 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 4 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: store i64 [[TMP3]], ptr [[NEW_VL]], align 4 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg2e32ff_v_f32m2_mu(vfloat32m2_t *v0, vfloat32m2_t *v1, vbool16_t mask, vfloat32m2_t maskedoff0, vfloat32m2_t maskedoff1, const float *base, size_t *new_vl, size_t vl) { + return __riscv_vlseg2e32ff_mu(v0, v1, mask, maskedoff0, maskedoff1, base, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlseg2e32ff_v_f32m4_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , i64 } @llvm.riscv.vlseg2ff.mask.nxv8f32.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 4 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 4 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: store i64 [[TMP3]], ptr [[NEW_VL]], align 4 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg2e32ff_v_f32m4_mu(vfloat32m4_t *v0, vfloat32m4_t *v1, vbool8_t mask, vfloat32m4_t maskedoff0, vfloat32m4_t maskedoff1, const float *base, size_t *new_vl, size_t vl) { + return __riscv_vlseg2e32ff_mu(v0, v1, mask, maskedoff0, maskedoff1, base, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlseg2e32ff_v_i32mf2_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , i64 } @llvm.riscv.vlseg2ff.mask.nxv1i32.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 4 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 4 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: store i64 [[TMP3]], ptr [[NEW_VL]], align 4 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg2e32ff_v_i32mf2_mu(vint32mf2_t *v0, vint32mf2_t *v1, vbool64_t mask, vint32mf2_t maskedoff0, vint32mf2_t maskedoff1, const int32_t *base, size_t *new_vl, size_t vl) { + return __riscv_vlseg2e32ff_mu(v0, v1, mask, maskedoff0, maskedoff1, base, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlseg2e32ff_v_i32m1_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , i64 } @llvm.riscv.vlseg2ff.mask.nxv2i32.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 4 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 4 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: store i64 [[TMP3]], ptr [[NEW_VL]], align 4 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg2e32ff_v_i32m1_mu(vint32m1_t *v0, vint32m1_t *v1, vbool32_t mask, vint32m1_t maskedoff0, vint32m1_t maskedoff1, const int32_t *base, size_t *new_vl, size_t vl) { + return __riscv_vlseg2e32ff_mu(v0, v1, mask, maskedoff0, maskedoff1, base, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlseg2e32ff_v_i32m2_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , i64 } @llvm.riscv.vlseg2ff.mask.nxv4i32.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 4 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 4 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: store i64 [[TMP3]], ptr [[NEW_VL]], align 4 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg2e32ff_v_i32m2_mu(vint32m2_t *v0, vint32m2_t *v1, vbool16_t mask, vint32m2_t maskedoff0, vint32m2_t maskedoff1, const int32_t *base, size_t *new_vl, size_t vl) { + return __riscv_vlseg2e32ff_mu(v0, v1, mask, maskedoff0, maskedoff1, base, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlseg2e32ff_v_i32m4_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , i64 } @llvm.riscv.vlseg2ff.mask.nxv8i32.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 4 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 4 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: store i64 [[TMP3]], ptr [[NEW_VL]], align 4 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg2e32ff_v_i32m4_mu(vint32m4_t *v0, vint32m4_t *v1, vbool8_t mask, vint32m4_t maskedoff0, vint32m4_t maskedoff1, const int32_t *base, size_t *new_vl, size_t vl) { + return __riscv_vlseg2e32ff_mu(v0, v1, mask, maskedoff0, maskedoff1, base, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlseg2e32ff_v_u32mf2_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , i64 } @llvm.riscv.vlseg2ff.mask.nxv1i32.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 4 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 4 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: store i64 [[TMP3]], ptr [[NEW_VL]], align 4 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg2e32ff_v_u32mf2_mu(vuint32mf2_t *v0, vuint32mf2_t *v1, vbool64_t mask, vuint32mf2_t maskedoff0, vuint32mf2_t maskedoff1, const uint32_t *base, size_t *new_vl, size_t vl) { + return __riscv_vlseg2e32ff_mu(v0, v1, mask, maskedoff0, maskedoff1, base, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlseg2e32ff_v_u32m1_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , i64 } @llvm.riscv.vlseg2ff.mask.nxv2i32.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 4 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 4 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: store i64 [[TMP3]], ptr [[NEW_VL]], align 4 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg2e32ff_v_u32m1_mu(vuint32m1_t *v0, vuint32m1_t *v1, vbool32_t mask, vuint32m1_t maskedoff0, vuint32m1_t maskedoff1, const uint32_t *base, size_t *new_vl, size_t vl) { + return __riscv_vlseg2e32ff_mu(v0, v1, mask, maskedoff0, maskedoff1, base, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlseg2e32ff_v_u32m2_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , i64 } @llvm.riscv.vlseg2ff.mask.nxv4i32.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 4 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 4 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: store i64 [[TMP3]], ptr [[NEW_VL]], align 4 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg2e32ff_v_u32m2_mu(vuint32m2_t *v0, vuint32m2_t *v1, vbool16_t mask, vuint32m2_t maskedoff0, vuint32m2_t maskedoff1, const uint32_t *base, size_t *new_vl, size_t vl) { + return __riscv_vlseg2e32ff_mu(v0, v1, mask, maskedoff0, maskedoff1, base, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlseg2e32ff_v_u32m4_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , i64 } @llvm.riscv.vlseg2ff.mask.nxv8i32.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 4 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 4 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: store i64 [[TMP3]], ptr [[NEW_VL]], align 4 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg2e32ff_v_u32m4_mu(vuint32m4_t *v0, vuint32m4_t *v1, vbool8_t mask, vuint32m4_t maskedoff0, vuint32m4_t maskedoff1, const uint32_t *base, size_t *new_vl, size_t vl) { + return __riscv_vlseg2e32ff_mu(v0, v1, mask, maskedoff0, maskedoff1, base, new_vl, vl); +} + diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e64.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e64.c index 2ecb62be92643..14819e8488dad 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e64.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e64.c @@ -385,3 +385,129 @@ void test_vlseg2e64_v_u64m4_tumu(vuint64m4_t *v0, vuint64m4_t *v1, vbool16_t mas return __riscv_vlseg2e64_tumu(v0, v1, mask, maskedoff0, maskedoff1, base, vl); } +// CHECK-RV64-LABEL: define dso_local void @test_vlseg2e64_v_f64m1_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vlseg2.mask.nxv1f64.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 8 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 8 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg2e64_v_f64m1_mu(vfloat64m1_t *v0, vfloat64m1_t *v1, vbool64_t mask, vfloat64m1_t maskedoff0, vfloat64m1_t maskedoff1, const double *base, size_t vl) { + return __riscv_vlseg2e64_mu(v0, v1, mask, maskedoff0, maskedoff1, base, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlseg2e64_v_f64m2_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vlseg2.mask.nxv2f64.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 8 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 8 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg2e64_v_f64m2_mu(vfloat64m2_t *v0, vfloat64m2_t *v1, vbool32_t mask, vfloat64m2_t maskedoff0, vfloat64m2_t maskedoff1, const double *base, size_t vl) { + return __riscv_vlseg2e64_mu(v0, v1, mask, maskedoff0, maskedoff1, base, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlseg2e64_v_f64m4_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vlseg2.mask.nxv4f64.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 8 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 8 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg2e64_v_f64m4_mu(vfloat64m4_t *v0, vfloat64m4_t *v1, vbool16_t mask, vfloat64m4_t maskedoff0, vfloat64m4_t maskedoff1, const double *base, size_t vl) { + return __riscv_vlseg2e64_mu(v0, v1, mask, maskedoff0, maskedoff1, base, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlseg2e64_v_i64m1_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vlseg2.mask.nxv1i64.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 8 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 8 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg2e64_v_i64m1_mu(vint64m1_t *v0, vint64m1_t *v1, vbool64_t mask, vint64m1_t maskedoff0, vint64m1_t maskedoff1, const int64_t *base, size_t vl) { + return __riscv_vlseg2e64_mu(v0, v1, mask, maskedoff0, maskedoff1, base, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlseg2e64_v_i64m2_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vlseg2.mask.nxv2i64.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 8 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 8 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg2e64_v_i64m2_mu(vint64m2_t *v0, vint64m2_t *v1, vbool32_t mask, vint64m2_t maskedoff0, vint64m2_t maskedoff1, const int64_t *base, size_t vl) { + return __riscv_vlseg2e64_mu(v0, v1, mask, maskedoff0, maskedoff1, base, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlseg2e64_v_i64m4_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vlseg2.mask.nxv4i64.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 8 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 8 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg2e64_v_i64m4_mu(vint64m4_t *v0, vint64m4_t *v1, vbool16_t mask, vint64m4_t maskedoff0, vint64m4_t maskedoff1, const int64_t *base, size_t vl) { + return __riscv_vlseg2e64_mu(v0, v1, mask, maskedoff0, maskedoff1, base, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlseg2e64_v_u64m1_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vlseg2.mask.nxv1i64.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 8 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 8 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg2e64_v_u64m1_mu(vuint64m1_t *v0, vuint64m1_t *v1, vbool64_t mask, vuint64m1_t maskedoff0, vuint64m1_t maskedoff1, const uint64_t *base, size_t vl) { + return __riscv_vlseg2e64_mu(v0, v1, mask, maskedoff0, maskedoff1, base, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlseg2e64_v_u64m2_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vlseg2.mask.nxv2i64.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 8 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 8 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg2e64_v_u64m2_mu(vuint64m2_t *v0, vuint64m2_t *v1, vbool32_t mask, vuint64m2_t maskedoff0, vuint64m2_t maskedoff1, const uint64_t *base, size_t vl) { + return __riscv_vlseg2e64_mu(v0, v1, mask, maskedoff0, maskedoff1, base, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlseg2e64_v_u64m4_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vlseg2.mask.nxv4i64.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 8 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 8 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg2e64_v_u64m4_mu(vuint64m4_t *v0, vuint64m4_t *v1, vbool16_t mask, vuint64m4_t maskedoff0, vuint64m4_t maskedoff1, const uint64_t *base, size_t vl) { + return __riscv_vlseg2e64_mu(v0, v1, mask, maskedoff0, maskedoff1, base, vl); +} + diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e64ff.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e64ff.c index ebb24f2dedc3e..2cd70ae67867f 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e64ff.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e64ff.c @@ -439,3 +439,147 @@ void test_vlseg2e64ff_v_u64m4_tumu(vuint64m4_t *v0, vuint64m4_t *v1, vbool16_t m return __riscv_vlseg2e64ff_tumu(v0, v1, mask, maskedoff0, maskedoff1, base, new_vl, vl); } +// CHECK-RV64-LABEL: define dso_local void @test_vlseg2e64ff_v_f64m1_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , i64 } @llvm.riscv.vlseg2ff.mask.nxv1f64.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 8 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 8 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: store i64 [[TMP3]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg2e64ff_v_f64m1_mu(vfloat64m1_t *v0, vfloat64m1_t *v1, vbool64_t mask, vfloat64m1_t maskedoff0, vfloat64m1_t maskedoff1, const double *base, size_t *new_vl, size_t vl) { + return __riscv_vlseg2e64ff_mu(v0, v1, mask, maskedoff0, maskedoff1, base, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlseg2e64ff_v_f64m2_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , i64 } @llvm.riscv.vlseg2ff.mask.nxv2f64.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 8 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 8 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: store i64 [[TMP3]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg2e64ff_v_f64m2_mu(vfloat64m2_t *v0, vfloat64m2_t *v1, vbool32_t mask, vfloat64m2_t maskedoff0, vfloat64m2_t maskedoff1, const double *base, size_t *new_vl, size_t vl) { + return __riscv_vlseg2e64ff_mu(v0, v1, mask, maskedoff0, maskedoff1, base, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlseg2e64ff_v_f64m4_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , i64 } @llvm.riscv.vlseg2ff.mask.nxv4f64.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 8 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 8 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: store i64 [[TMP3]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg2e64ff_v_f64m4_mu(vfloat64m4_t *v0, vfloat64m4_t *v1, vbool16_t mask, vfloat64m4_t maskedoff0, vfloat64m4_t maskedoff1, const double *base, size_t *new_vl, size_t vl) { + return __riscv_vlseg2e64ff_mu(v0, v1, mask, maskedoff0, maskedoff1, base, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlseg2e64ff_v_i64m1_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , i64 } @llvm.riscv.vlseg2ff.mask.nxv1i64.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 8 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 8 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: store i64 [[TMP3]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg2e64ff_v_i64m1_mu(vint64m1_t *v0, vint64m1_t *v1, vbool64_t mask, vint64m1_t maskedoff0, vint64m1_t maskedoff1, const int64_t *base, size_t *new_vl, size_t vl) { + return __riscv_vlseg2e64ff_mu(v0, v1, mask, maskedoff0, maskedoff1, base, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlseg2e64ff_v_i64m2_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , i64 } @llvm.riscv.vlseg2ff.mask.nxv2i64.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 8 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 8 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: store i64 [[TMP3]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg2e64ff_v_i64m2_mu(vint64m2_t *v0, vint64m2_t *v1, vbool32_t mask, vint64m2_t maskedoff0, vint64m2_t maskedoff1, const int64_t *base, size_t *new_vl, size_t vl) { + return __riscv_vlseg2e64ff_mu(v0, v1, mask, maskedoff0, maskedoff1, base, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlseg2e64ff_v_i64m4_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , i64 } @llvm.riscv.vlseg2ff.mask.nxv4i64.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 8 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 8 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: store i64 [[TMP3]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg2e64ff_v_i64m4_mu(vint64m4_t *v0, vint64m4_t *v1, vbool16_t mask, vint64m4_t maskedoff0, vint64m4_t maskedoff1, const int64_t *base, size_t *new_vl, size_t vl) { + return __riscv_vlseg2e64ff_mu(v0, v1, mask, maskedoff0, maskedoff1, base, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlseg2e64ff_v_u64m1_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , i64 } @llvm.riscv.vlseg2ff.mask.nxv1i64.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 8 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 8 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: store i64 [[TMP3]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg2e64ff_v_u64m1_mu(vuint64m1_t *v0, vuint64m1_t *v1, vbool64_t mask, vuint64m1_t maskedoff0, vuint64m1_t maskedoff1, const uint64_t *base, size_t *new_vl, size_t vl) { + return __riscv_vlseg2e64ff_mu(v0, v1, mask, maskedoff0, maskedoff1, base, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlseg2e64ff_v_u64m2_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , i64 } @llvm.riscv.vlseg2ff.mask.nxv2i64.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 8 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 8 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: store i64 [[TMP3]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg2e64ff_v_u64m2_mu(vuint64m2_t *v0, vuint64m2_t *v1, vbool32_t mask, vuint64m2_t maskedoff0, vuint64m2_t maskedoff1, const uint64_t *base, size_t *new_vl, size_t vl) { + return __riscv_vlseg2e64ff_mu(v0, v1, mask, maskedoff0, maskedoff1, base, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlseg2e64ff_v_u64m4_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , i64 } @llvm.riscv.vlseg2ff.mask.nxv4i64.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 8 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 8 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: store i64 [[TMP3]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg2e64ff_v_u64m4_mu(vuint64m4_t *v0, vuint64m4_t *v1, vbool16_t mask, vuint64m4_t maskedoff0, vuint64m4_t maskedoff1, const uint64_t *base, size_t *new_vl, size_t vl) { + return __riscv_vlseg2e64ff_mu(v0, v1, mask, maskedoff0, maskedoff1, base, new_vl, vl); +} + diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e8.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e8.c index af3ad5fb569f3..9d8a3ae5d82c9 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e8.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e8.c @@ -510,3 +510,171 @@ void test_vlseg2e8_v_u8m4_tumu(vuint8m4_t *v0, vuint8m4_t *v1, vbool2_t mask, vu return __riscv_vlseg2e8_tumu(v0, v1, mask, maskedoff0, maskedoff1, base, vl); } +// CHECK-RV64-LABEL: define dso_local void @test_vlseg2e8_v_i8mf8_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vlseg2.mask.nxv1i8.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 1 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg2e8_v_i8mf8_mu(vint8mf8_t *v0, vint8mf8_t *v1, vbool64_t mask, vint8mf8_t maskedoff0, vint8mf8_t maskedoff1, const int8_t *base, size_t vl) { + return __riscv_vlseg2e8_mu(v0, v1, mask, maskedoff0, maskedoff1, base, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlseg2e8_v_i8mf4_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vlseg2.mask.nxv2i8.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 1 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg2e8_v_i8mf4_mu(vint8mf4_t *v0, vint8mf4_t *v1, vbool32_t mask, vint8mf4_t maskedoff0, vint8mf4_t maskedoff1, const int8_t *base, size_t vl) { + return __riscv_vlseg2e8_mu(v0, v1, mask, maskedoff0, maskedoff1, base, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlseg2e8_v_i8mf2_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vlseg2.mask.nxv4i8.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 1 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg2e8_v_i8mf2_mu(vint8mf2_t *v0, vint8mf2_t *v1, vbool16_t mask, vint8mf2_t maskedoff0, vint8mf2_t maskedoff1, const int8_t *base, size_t vl) { + return __riscv_vlseg2e8_mu(v0, v1, mask, maskedoff0, maskedoff1, base, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlseg2e8_v_i8m1_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vlseg2.mask.nxv8i8.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 1 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg2e8_v_i8m1_mu(vint8m1_t *v0, vint8m1_t *v1, vbool8_t mask, vint8m1_t maskedoff0, vint8m1_t maskedoff1, const int8_t *base, size_t vl) { + return __riscv_vlseg2e8_mu(v0, v1, mask, maskedoff0, maskedoff1, base, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlseg2e8_v_i8m2_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vlseg2.mask.nxv16i8.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 1 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg2e8_v_i8m2_mu(vint8m2_t *v0, vint8m2_t *v1, vbool4_t mask, vint8m2_t maskedoff0, vint8m2_t maskedoff1, const int8_t *base, size_t vl) { + return __riscv_vlseg2e8_mu(v0, v1, mask, maskedoff0, maskedoff1, base, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlseg2e8_v_i8m4_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vlseg2.mask.nxv32i8.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 1 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg2e8_v_i8m4_mu(vint8m4_t *v0, vint8m4_t *v1, vbool2_t mask, vint8m4_t maskedoff0, vint8m4_t maskedoff1, const int8_t *base, size_t vl) { + return __riscv_vlseg2e8_mu(v0, v1, mask, maskedoff0, maskedoff1, base, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlseg2e8_v_u8mf8_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vlseg2.mask.nxv1i8.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 1 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg2e8_v_u8mf8_mu(vuint8mf8_t *v0, vuint8mf8_t *v1, vbool64_t mask, vuint8mf8_t maskedoff0, vuint8mf8_t maskedoff1, const uint8_t *base, size_t vl) { + return __riscv_vlseg2e8_mu(v0, v1, mask, maskedoff0, maskedoff1, base, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlseg2e8_v_u8mf4_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vlseg2.mask.nxv2i8.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 1 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg2e8_v_u8mf4_mu(vuint8mf4_t *v0, vuint8mf4_t *v1, vbool32_t mask, vuint8mf4_t maskedoff0, vuint8mf4_t maskedoff1, const uint8_t *base, size_t vl) { + return __riscv_vlseg2e8_mu(v0, v1, mask, maskedoff0, maskedoff1, base, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlseg2e8_v_u8mf2_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vlseg2.mask.nxv4i8.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 1 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg2e8_v_u8mf2_mu(vuint8mf2_t *v0, vuint8mf2_t *v1, vbool16_t mask, vuint8mf2_t maskedoff0, vuint8mf2_t maskedoff1, const uint8_t *base, size_t vl) { + return __riscv_vlseg2e8_mu(v0, v1, mask, maskedoff0, maskedoff1, base, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlseg2e8_v_u8m1_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vlseg2.mask.nxv8i8.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 1 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg2e8_v_u8m1_mu(vuint8m1_t *v0, vuint8m1_t *v1, vbool8_t mask, vuint8m1_t maskedoff0, vuint8m1_t maskedoff1, const uint8_t *base, size_t vl) { + return __riscv_vlseg2e8_mu(v0, v1, mask, maskedoff0, maskedoff1, base, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlseg2e8_v_u8m2_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vlseg2.mask.nxv16i8.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 1 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg2e8_v_u8m2_mu(vuint8m2_t *v0, vuint8m2_t *v1, vbool4_t mask, vuint8m2_t maskedoff0, vuint8m2_t maskedoff1, const uint8_t *base, size_t vl) { + return __riscv_vlseg2e8_mu(v0, v1, mask, maskedoff0, maskedoff1, base, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlseg2e8_v_u8m4_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vlseg2.mask.nxv32i8.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 1 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg2e8_v_u8m4_mu(vuint8m4_t *v0, vuint8m4_t *v1, vbool2_t mask, vuint8m4_t maskedoff0, vuint8m4_t maskedoff1, const uint8_t *base, size_t vl) { + return __riscv_vlseg2e8_mu(v0, v1, mask, maskedoff0, maskedoff1, base, vl); +} + diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e8ff.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e8ff.c index d494adfc57b44..6e21ab536faed 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e8ff.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e8ff.c @@ -583,3 +583,195 @@ void test_vlseg2e8ff_v_u8m4_tumu(vuint8m4_t *v0, vuint8m4_t *v1, vbool2_t mask, return __riscv_vlseg2e8ff_tumu(v0, v1, mask, maskedoff0, maskedoff1, base, new_vl, vl); } +// CHECK-RV64-LABEL: define dso_local void @test_vlseg2e8ff_v_i8mf8_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , i64 } @llvm.riscv.vlseg2ff.mask.nxv1i8.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 1 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: store i64 [[TMP3]], ptr [[NEW_VL]], align 1 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg2e8ff_v_i8mf8_mu(vint8mf8_t *v0, vint8mf8_t *v1, vbool64_t mask, vint8mf8_t maskedoff0, vint8mf8_t maskedoff1, const int8_t *base, size_t *new_vl, size_t vl) { + return __riscv_vlseg2e8ff_mu(v0, v1, mask, maskedoff0, maskedoff1, base, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlseg2e8ff_v_i8mf4_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , i64 } @llvm.riscv.vlseg2ff.mask.nxv2i8.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 1 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: store i64 [[TMP3]], ptr [[NEW_VL]], align 1 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg2e8ff_v_i8mf4_mu(vint8mf4_t *v0, vint8mf4_t *v1, vbool32_t mask, vint8mf4_t maskedoff0, vint8mf4_t maskedoff1, const int8_t *base, size_t *new_vl, size_t vl) { + return __riscv_vlseg2e8ff_mu(v0, v1, mask, maskedoff0, maskedoff1, base, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlseg2e8ff_v_i8mf2_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , i64 } @llvm.riscv.vlseg2ff.mask.nxv4i8.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 1 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: store i64 [[TMP3]], ptr [[NEW_VL]], align 1 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg2e8ff_v_i8mf2_mu(vint8mf2_t *v0, vint8mf2_t *v1, vbool16_t mask, vint8mf2_t maskedoff0, vint8mf2_t maskedoff1, const int8_t *base, size_t *new_vl, size_t vl) { + return __riscv_vlseg2e8ff_mu(v0, v1, mask, maskedoff0, maskedoff1, base, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlseg2e8ff_v_i8m1_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , i64 } @llvm.riscv.vlseg2ff.mask.nxv8i8.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 1 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: store i64 [[TMP3]], ptr [[NEW_VL]], align 1 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg2e8ff_v_i8m1_mu(vint8m1_t *v0, vint8m1_t *v1, vbool8_t mask, vint8m1_t maskedoff0, vint8m1_t maskedoff1, const int8_t *base, size_t *new_vl, size_t vl) { + return __riscv_vlseg2e8ff_mu(v0, v1, mask, maskedoff0, maskedoff1, base, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlseg2e8ff_v_i8m2_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , i64 } @llvm.riscv.vlseg2ff.mask.nxv16i8.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 1 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: store i64 [[TMP3]], ptr [[NEW_VL]], align 1 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg2e8ff_v_i8m2_mu(vint8m2_t *v0, vint8m2_t *v1, vbool4_t mask, vint8m2_t maskedoff0, vint8m2_t maskedoff1, const int8_t *base, size_t *new_vl, size_t vl) { + return __riscv_vlseg2e8ff_mu(v0, v1, mask, maskedoff0, maskedoff1, base, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlseg2e8ff_v_i8m4_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , i64 } @llvm.riscv.vlseg2ff.mask.nxv32i8.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 1 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: store i64 [[TMP3]], ptr [[NEW_VL]], align 1 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg2e8ff_v_i8m4_mu(vint8m4_t *v0, vint8m4_t *v1, vbool2_t mask, vint8m4_t maskedoff0, vint8m4_t maskedoff1, const int8_t *base, size_t *new_vl, size_t vl) { + return __riscv_vlseg2e8ff_mu(v0, v1, mask, maskedoff0, maskedoff1, base, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlseg2e8ff_v_u8mf8_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , i64 } @llvm.riscv.vlseg2ff.mask.nxv1i8.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 1 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: store i64 [[TMP3]], ptr [[NEW_VL]], align 1 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg2e8ff_v_u8mf8_mu(vuint8mf8_t *v0, vuint8mf8_t *v1, vbool64_t mask, vuint8mf8_t maskedoff0, vuint8mf8_t maskedoff1, const uint8_t *base, size_t *new_vl, size_t vl) { + return __riscv_vlseg2e8ff_mu(v0, v1, mask, maskedoff0, maskedoff1, base, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlseg2e8ff_v_u8mf4_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , i64 } @llvm.riscv.vlseg2ff.mask.nxv2i8.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 1 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: store i64 [[TMP3]], ptr [[NEW_VL]], align 1 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg2e8ff_v_u8mf4_mu(vuint8mf4_t *v0, vuint8mf4_t *v1, vbool32_t mask, vuint8mf4_t maskedoff0, vuint8mf4_t maskedoff1, const uint8_t *base, size_t *new_vl, size_t vl) { + return __riscv_vlseg2e8ff_mu(v0, v1, mask, maskedoff0, maskedoff1, base, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlseg2e8ff_v_u8mf2_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , i64 } @llvm.riscv.vlseg2ff.mask.nxv4i8.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 1 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: store i64 [[TMP3]], ptr [[NEW_VL]], align 1 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg2e8ff_v_u8mf2_mu(vuint8mf2_t *v0, vuint8mf2_t *v1, vbool16_t mask, vuint8mf2_t maskedoff0, vuint8mf2_t maskedoff1, const uint8_t *base, size_t *new_vl, size_t vl) { + return __riscv_vlseg2e8ff_mu(v0, v1, mask, maskedoff0, maskedoff1, base, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlseg2e8ff_v_u8m1_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , i64 } @llvm.riscv.vlseg2ff.mask.nxv8i8.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 1 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: store i64 [[TMP3]], ptr [[NEW_VL]], align 1 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg2e8ff_v_u8m1_mu(vuint8m1_t *v0, vuint8m1_t *v1, vbool8_t mask, vuint8m1_t maskedoff0, vuint8m1_t maskedoff1, const uint8_t *base, size_t *new_vl, size_t vl) { + return __riscv_vlseg2e8ff_mu(v0, v1, mask, maskedoff0, maskedoff1, base, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlseg2e8ff_v_u8m2_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , i64 } @llvm.riscv.vlseg2ff.mask.nxv16i8.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 1 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: store i64 [[TMP3]], ptr [[NEW_VL]], align 1 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg2e8ff_v_u8m2_mu(vuint8m2_t *v0, vuint8m2_t *v1, vbool4_t mask, vuint8m2_t maskedoff0, vuint8m2_t maskedoff1, const uint8_t *base, size_t *new_vl, size_t vl) { + return __riscv_vlseg2e8ff_mu(v0, v1, mask, maskedoff0, maskedoff1, base, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlseg2e8ff_v_u8m4_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , i64 } @llvm.riscv.vlseg2ff.mask.nxv32i8.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 1 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: store i64 [[TMP3]], ptr [[NEW_VL]], align 1 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg2e8ff_v_u8m4_mu(vuint8m4_t *v0, vuint8m4_t *v1, vbool2_t mask, vuint8m4_t maskedoff0, vuint8m4_t maskedoff1, const uint8_t *base, size_t *new_vl, size_t vl) { + return __riscv_vlseg2e8ff_mu(v0, v1, mask, maskedoff0, maskedoff1, base, new_vl, vl); +} + diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e16.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e16.c index 6a1d16bf3c090..c5714e5f7b72b 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e16.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e16.c @@ -583,3 +583,195 @@ void test_vlseg3e16_v_u16m2_tumu(vuint16m2_t *v0, vuint16m2_t *v1, vuint16m2_t * return __riscv_vlseg3e16_tumu(v0, v1, v2, mask, maskedoff0, maskedoff1, maskedoff2, base, vl); } +// CHECK-RV64-LABEL: define dso_local void @test_vlseg3e16_v_f16mf4_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vlseg3.mask.nxv1f16.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 2 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 2 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg3e16_v_f16mf4_mu(vfloat16mf4_t *v0, vfloat16mf4_t *v1, vfloat16mf4_t *v2, vbool64_t mask, vfloat16mf4_t maskedoff0, vfloat16mf4_t maskedoff1, vfloat16mf4_t maskedoff2, const _Float16 *base, size_t vl) { + return __riscv_vlseg3e16_mu(v0, v1, v2, mask, maskedoff0, maskedoff1, maskedoff2, base, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlseg3e16_v_f16mf2_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vlseg3.mask.nxv2f16.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 2 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 2 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg3e16_v_f16mf2_mu(vfloat16mf2_t *v0, vfloat16mf2_t *v1, vfloat16mf2_t *v2, vbool32_t mask, vfloat16mf2_t maskedoff0, vfloat16mf2_t maskedoff1, vfloat16mf2_t maskedoff2, const _Float16 *base, size_t vl) { + return __riscv_vlseg3e16_mu(v0, v1, v2, mask, maskedoff0, maskedoff1, maskedoff2, base, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlseg3e16_v_f16m1_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vlseg3.mask.nxv4f16.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 2 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 2 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg3e16_v_f16m1_mu(vfloat16m1_t *v0, vfloat16m1_t *v1, vfloat16m1_t *v2, vbool16_t mask, vfloat16m1_t maskedoff0, vfloat16m1_t maskedoff1, vfloat16m1_t maskedoff2, const _Float16 *base, size_t vl) { + return __riscv_vlseg3e16_mu(v0, v1, v2, mask, maskedoff0, maskedoff1, maskedoff2, base, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlseg3e16_v_f16m2_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vlseg3.mask.nxv8f16.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 2 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 2 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg3e16_v_f16m2_mu(vfloat16m2_t *v0, vfloat16m2_t *v1, vfloat16m2_t *v2, vbool8_t mask, vfloat16m2_t maskedoff0, vfloat16m2_t maskedoff1, vfloat16m2_t maskedoff2, const _Float16 *base, size_t vl) { + return __riscv_vlseg3e16_mu(v0, v1, v2, mask, maskedoff0, maskedoff1, maskedoff2, base, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlseg3e16_v_i16mf4_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vlseg3.mask.nxv1i16.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 2 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 2 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg3e16_v_i16mf4_mu(vint16mf4_t *v0, vint16mf4_t *v1, vint16mf4_t *v2, vbool64_t mask, vint16mf4_t maskedoff0, vint16mf4_t maskedoff1, vint16mf4_t maskedoff2, const int16_t *base, size_t vl) { + return __riscv_vlseg3e16_mu(v0, v1, v2, mask, maskedoff0, maskedoff1, maskedoff2, base, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlseg3e16_v_i16mf2_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vlseg3.mask.nxv2i16.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 2 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 2 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg3e16_v_i16mf2_mu(vint16mf2_t *v0, vint16mf2_t *v1, vint16mf2_t *v2, vbool32_t mask, vint16mf2_t maskedoff0, vint16mf2_t maskedoff1, vint16mf2_t maskedoff2, const int16_t *base, size_t vl) { + return __riscv_vlseg3e16_mu(v0, v1, v2, mask, maskedoff0, maskedoff1, maskedoff2, base, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlseg3e16_v_i16m1_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vlseg3.mask.nxv4i16.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 2 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 2 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg3e16_v_i16m1_mu(vint16m1_t *v0, vint16m1_t *v1, vint16m1_t *v2, vbool16_t mask, vint16m1_t maskedoff0, vint16m1_t maskedoff1, vint16m1_t maskedoff2, const int16_t *base, size_t vl) { + return __riscv_vlseg3e16_mu(v0, v1, v2, mask, maskedoff0, maskedoff1, maskedoff2, base, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlseg3e16_v_i16m2_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vlseg3.mask.nxv8i16.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 2 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 2 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg3e16_v_i16m2_mu(vint16m2_t *v0, vint16m2_t *v1, vint16m2_t *v2, vbool8_t mask, vint16m2_t maskedoff0, vint16m2_t maskedoff1, vint16m2_t maskedoff2, const int16_t *base, size_t vl) { + return __riscv_vlseg3e16_mu(v0, v1, v2, mask, maskedoff0, maskedoff1, maskedoff2, base, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlseg3e16_v_u16mf4_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vlseg3.mask.nxv1i16.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 2 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 2 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg3e16_v_u16mf4_mu(vuint16mf4_t *v0, vuint16mf4_t *v1, vuint16mf4_t *v2, vbool64_t mask, vuint16mf4_t maskedoff0, vuint16mf4_t maskedoff1, vuint16mf4_t maskedoff2, const uint16_t *base, size_t vl) { + return __riscv_vlseg3e16_mu(v0, v1, v2, mask, maskedoff0, maskedoff1, maskedoff2, base, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlseg3e16_v_u16mf2_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vlseg3.mask.nxv2i16.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 2 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 2 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg3e16_v_u16mf2_mu(vuint16mf2_t *v0, vuint16mf2_t *v1, vuint16mf2_t *v2, vbool32_t mask, vuint16mf2_t maskedoff0, vuint16mf2_t maskedoff1, vuint16mf2_t maskedoff2, const uint16_t *base, size_t vl) { + return __riscv_vlseg3e16_mu(v0, v1, v2, mask, maskedoff0, maskedoff1, maskedoff2, base, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlseg3e16_v_u16m1_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vlseg3.mask.nxv4i16.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 2 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 2 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg3e16_v_u16m1_mu(vuint16m1_t *v0, vuint16m1_t *v1, vuint16m1_t *v2, vbool16_t mask, vuint16m1_t maskedoff0, vuint16m1_t maskedoff1, vuint16m1_t maskedoff2, const uint16_t *base, size_t vl) { + return __riscv_vlseg3e16_mu(v0, v1, v2, mask, maskedoff0, maskedoff1, maskedoff2, base, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlseg3e16_v_u16m2_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vlseg3.mask.nxv8i16.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 2 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 2 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg3e16_v_u16m2_mu(vuint16m2_t *v0, vuint16m2_t *v1, vuint16m2_t *v2, vbool8_t mask, vuint16m2_t maskedoff0, vuint16m2_t maskedoff1, vuint16m2_t maskedoff2, const uint16_t *base, size_t vl) { + return __riscv_vlseg3e16_mu(v0, v1, v2, mask, maskedoff0, maskedoff1, maskedoff2, base, vl); +} + diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e16ff.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e16ff.c index 0944fb4e5130a..ad501f523cb18 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e16ff.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e16ff.c @@ -655,3 +655,219 @@ void test_vlseg3e16ff_v_u16m2_tumu(vuint16m2_t *v0, vuint16m2_t *v1, vuint16m2_t return __riscv_vlseg3e16ff_tumu(v0, v1, v2, mask, maskedoff0, maskedoff1, maskedoff2, base, new_vl, vl); } +// CHECK-RV64-LABEL: define dso_local void @test_vlseg3e16ff_v_f16mf4_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , i64 } @llvm.riscv.vlseg3ff.mask.nxv1f16.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 2 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 2 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , i64 } [[TMP0]], 3 +// CHECK-RV64-NEXT: store i64 [[TMP4]], ptr [[NEW_VL]], align 2 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg3e16ff_v_f16mf4_mu(vfloat16mf4_t *v0, vfloat16mf4_t *v1, vfloat16mf4_t *v2, vbool64_t mask, vfloat16mf4_t maskedoff0, vfloat16mf4_t maskedoff1, vfloat16mf4_t maskedoff2, const _Float16 *base, size_t *new_vl, size_t vl) { + return __riscv_vlseg3e16ff_mu(v0, v1, v2, mask, maskedoff0, maskedoff1, maskedoff2, base, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlseg3e16ff_v_f16mf2_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , i64 } @llvm.riscv.vlseg3ff.mask.nxv2f16.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 2 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 2 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , i64 } [[TMP0]], 3 +// CHECK-RV64-NEXT: store i64 [[TMP4]], ptr [[NEW_VL]], align 2 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg3e16ff_v_f16mf2_mu(vfloat16mf2_t *v0, vfloat16mf2_t *v1, vfloat16mf2_t *v2, vbool32_t mask, vfloat16mf2_t maskedoff0, vfloat16mf2_t maskedoff1, vfloat16mf2_t maskedoff2, const _Float16 *base, size_t *new_vl, size_t vl) { + return __riscv_vlseg3e16ff_mu(v0, v1, v2, mask, maskedoff0, maskedoff1, maskedoff2, base, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlseg3e16ff_v_f16m1_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , i64 } @llvm.riscv.vlseg3ff.mask.nxv4f16.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 2 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 2 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , i64 } [[TMP0]], 3 +// CHECK-RV64-NEXT: store i64 [[TMP4]], ptr [[NEW_VL]], align 2 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg3e16ff_v_f16m1_mu(vfloat16m1_t *v0, vfloat16m1_t *v1, vfloat16m1_t *v2, vbool16_t mask, vfloat16m1_t maskedoff0, vfloat16m1_t maskedoff1, vfloat16m1_t maskedoff2, const _Float16 *base, size_t *new_vl, size_t vl) { + return __riscv_vlseg3e16ff_mu(v0, v1, v2, mask, maskedoff0, maskedoff1, maskedoff2, base, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlseg3e16ff_v_f16m2_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , i64 } @llvm.riscv.vlseg3ff.mask.nxv8f16.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 2 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 2 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , i64 } [[TMP0]], 3 +// CHECK-RV64-NEXT: store i64 [[TMP4]], ptr [[NEW_VL]], align 2 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg3e16ff_v_f16m2_mu(vfloat16m2_t *v0, vfloat16m2_t *v1, vfloat16m2_t *v2, vbool8_t mask, vfloat16m2_t maskedoff0, vfloat16m2_t maskedoff1, vfloat16m2_t maskedoff2, const _Float16 *base, size_t *new_vl, size_t vl) { + return __riscv_vlseg3e16ff_mu(v0, v1, v2, mask, maskedoff0, maskedoff1, maskedoff2, base, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlseg3e16ff_v_i16mf4_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , i64 } @llvm.riscv.vlseg3ff.mask.nxv1i16.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 2 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 2 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , i64 } [[TMP0]], 3 +// CHECK-RV64-NEXT: store i64 [[TMP4]], ptr [[NEW_VL]], align 2 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg3e16ff_v_i16mf4_mu(vint16mf4_t *v0, vint16mf4_t *v1, vint16mf4_t *v2, vbool64_t mask, vint16mf4_t maskedoff0, vint16mf4_t maskedoff1, vint16mf4_t maskedoff2, const int16_t *base, size_t *new_vl, size_t vl) { + return __riscv_vlseg3e16ff_mu(v0, v1, v2, mask, maskedoff0, maskedoff1, maskedoff2, base, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlseg3e16ff_v_i16mf2_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , i64 } @llvm.riscv.vlseg3ff.mask.nxv2i16.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 2 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 2 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , i64 } [[TMP0]], 3 +// CHECK-RV64-NEXT: store i64 [[TMP4]], ptr [[NEW_VL]], align 2 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg3e16ff_v_i16mf2_mu(vint16mf2_t *v0, vint16mf2_t *v1, vint16mf2_t *v2, vbool32_t mask, vint16mf2_t maskedoff0, vint16mf2_t maskedoff1, vint16mf2_t maskedoff2, const int16_t *base, size_t *new_vl, size_t vl) { + return __riscv_vlseg3e16ff_mu(v0, v1, v2, mask, maskedoff0, maskedoff1, maskedoff2, base, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlseg3e16ff_v_i16m1_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , i64 } @llvm.riscv.vlseg3ff.mask.nxv4i16.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 2 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 2 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , i64 } [[TMP0]], 3 +// CHECK-RV64-NEXT: store i64 [[TMP4]], ptr [[NEW_VL]], align 2 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg3e16ff_v_i16m1_mu(vint16m1_t *v0, vint16m1_t *v1, vint16m1_t *v2, vbool16_t mask, vint16m1_t maskedoff0, vint16m1_t maskedoff1, vint16m1_t maskedoff2, const int16_t *base, size_t *new_vl, size_t vl) { + return __riscv_vlseg3e16ff_mu(v0, v1, v2, mask, maskedoff0, maskedoff1, maskedoff2, base, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlseg3e16ff_v_i16m2_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , i64 } @llvm.riscv.vlseg3ff.mask.nxv8i16.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 2 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 2 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , i64 } [[TMP0]], 3 +// CHECK-RV64-NEXT: store i64 [[TMP4]], ptr [[NEW_VL]], align 2 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg3e16ff_v_i16m2_mu(vint16m2_t *v0, vint16m2_t *v1, vint16m2_t *v2, vbool8_t mask, vint16m2_t maskedoff0, vint16m2_t maskedoff1, vint16m2_t maskedoff2, const int16_t *base, size_t *new_vl, size_t vl) { + return __riscv_vlseg3e16ff_mu(v0, v1, v2, mask, maskedoff0, maskedoff1, maskedoff2, base, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlseg3e16ff_v_u16mf4_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , i64 } @llvm.riscv.vlseg3ff.mask.nxv1i16.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 2 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 2 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , i64 } [[TMP0]], 3 +// CHECK-RV64-NEXT: store i64 [[TMP4]], ptr [[NEW_VL]], align 2 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg3e16ff_v_u16mf4_mu(vuint16mf4_t *v0, vuint16mf4_t *v1, vuint16mf4_t *v2, vbool64_t mask, vuint16mf4_t maskedoff0, vuint16mf4_t maskedoff1, vuint16mf4_t maskedoff2, const uint16_t *base, size_t *new_vl, size_t vl) { + return __riscv_vlseg3e16ff_mu(v0, v1, v2, mask, maskedoff0, maskedoff1, maskedoff2, base, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlseg3e16ff_v_u16mf2_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , i64 } @llvm.riscv.vlseg3ff.mask.nxv2i16.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 2 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 2 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , i64 } [[TMP0]], 3 +// CHECK-RV64-NEXT: store i64 [[TMP4]], ptr [[NEW_VL]], align 2 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg3e16ff_v_u16mf2_mu(vuint16mf2_t *v0, vuint16mf2_t *v1, vuint16mf2_t *v2, vbool32_t mask, vuint16mf2_t maskedoff0, vuint16mf2_t maskedoff1, vuint16mf2_t maskedoff2, const uint16_t *base, size_t *new_vl, size_t vl) { + return __riscv_vlseg3e16ff_mu(v0, v1, v2, mask, maskedoff0, maskedoff1, maskedoff2, base, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlseg3e16ff_v_u16m1_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , i64 } @llvm.riscv.vlseg3ff.mask.nxv4i16.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 2 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 2 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , i64 } [[TMP0]], 3 +// CHECK-RV64-NEXT: store i64 [[TMP4]], ptr [[NEW_VL]], align 2 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg3e16ff_v_u16m1_mu(vuint16m1_t *v0, vuint16m1_t *v1, vuint16m1_t *v2, vbool16_t mask, vuint16m1_t maskedoff0, vuint16m1_t maskedoff1, vuint16m1_t maskedoff2, const uint16_t *base, size_t *new_vl, size_t vl) { + return __riscv_vlseg3e16ff_mu(v0, v1, v2, mask, maskedoff0, maskedoff1, maskedoff2, base, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlseg3e16ff_v_u16m2_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , i64 } @llvm.riscv.vlseg3ff.mask.nxv8i16.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 2 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 2 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , i64 } [[TMP0]], 3 +// CHECK-RV64-NEXT: store i64 [[TMP4]], ptr [[NEW_VL]], align 2 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg3e16ff_v_u16m2_mu(vuint16m2_t *v0, vuint16m2_t *v1, vuint16m2_t *v2, vbool8_t mask, vuint16m2_t maskedoff0, vuint16m2_t maskedoff1, vuint16m2_t maskedoff2, const uint16_t *base, size_t *new_vl, size_t vl) { + return __riscv_vlseg3e16ff_mu(v0, v1, v2, mask, maskedoff0, maskedoff1, maskedoff2, base, new_vl, vl); +} + diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e32.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e32.c index 8afae2c86cac5..95ed62c5287d5 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e32.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e32.c @@ -439,3 +439,147 @@ void test_vlseg3e32_v_u32m2_tumu(vuint32m2_t *v0, vuint32m2_t *v1, vuint32m2_t * return __riscv_vlseg3e32_tumu(v0, v1, v2, mask, maskedoff0, maskedoff1, maskedoff2, base, vl); } +// CHECK-RV64-LABEL: define dso_local void @test_vlseg3e32_v_f32mf2_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vlseg3.mask.nxv1f32.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 4 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 4 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 4 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg3e32_v_f32mf2_mu(vfloat32mf2_t *v0, vfloat32mf2_t *v1, vfloat32mf2_t *v2, vbool64_t mask, vfloat32mf2_t maskedoff0, vfloat32mf2_t maskedoff1, vfloat32mf2_t maskedoff2, const float *base, size_t vl) { + return __riscv_vlseg3e32_mu(v0, v1, v2, mask, maskedoff0, maskedoff1, maskedoff2, base, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlseg3e32_v_f32m1_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vlseg3.mask.nxv2f32.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 4 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 4 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 4 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg3e32_v_f32m1_mu(vfloat32m1_t *v0, vfloat32m1_t *v1, vfloat32m1_t *v2, vbool32_t mask, vfloat32m1_t maskedoff0, vfloat32m1_t maskedoff1, vfloat32m1_t maskedoff2, const float *base, size_t vl) { + return __riscv_vlseg3e32_mu(v0, v1, v2, mask, maskedoff0, maskedoff1, maskedoff2, base, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlseg3e32_v_f32m2_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vlseg3.mask.nxv4f32.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 4 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 4 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 4 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg3e32_v_f32m2_mu(vfloat32m2_t *v0, vfloat32m2_t *v1, vfloat32m2_t *v2, vbool16_t mask, vfloat32m2_t maskedoff0, vfloat32m2_t maskedoff1, vfloat32m2_t maskedoff2, const float *base, size_t vl) { + return __riscv_vlseg3e32_mu(v0, v1, v2, mask, maskedoff0, maskedoff1, maskedoff2, base, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlseg3e32_v_i32mf2_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vlseg3.mask.nxv1i32.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 4 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 4 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 4 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg3e32_v_i32mf2_mu(vint32mf2_t *v0, vint32mf2_t *v1, vint32mf2_t *v2, vbool64_t mask, vint32mf2_t maskedoff0, vint32mf2_t maskedoff1, vint32mf2_t maskedoff2, const int32_t *base, size_t vl) { + return __riscv_vlseg3e32_mu(v0, v1, v2, mask, maskedoff0, maskedoff1, maskedoff2, base, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlseg3e32_v_i32m1_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vlseg3.mask.nxv2i32.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 4 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 4 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 4 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg3e32_v_i32m1_mu(vint32m1_t *v0, vint32m1_t *v1, vint32m1_t *v2, vbool32_t mask, vint32m1_t maskedoff0, vint32m1_t maskedoff1, vint32m1_t maskedoff2, const int32_t *base, size_t vl) { + return __riscv_vlseg3e32_mu(v0, v1, v2, mask, maskedoff0, maskedoff1, maskedoff2, base, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlseg3e32_v_i32m2_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vlseg3.mask.nxv4i32.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 4 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 4 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 4 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg3e32_v_i32m2_mu(vint32m2_t *v0, vint32m2_t *v1, vint32m2_t *v2, vbool16_t mask, vint32m2_t maskedoff0, vint32m2_t maskedoff1, vint32m2_t maskedoff2, const int32_t *base, size_t vl) { + return __riscv_vlseg3e32_mu(v0, v1, v2, mask, maskedoff0, maskedoff1, maskedoff2, base, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlseg3e32_v_u32mf2_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vlseg3.mask.nxv1i32.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 4 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 4 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 4 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg3e32_v_u32mf2_mu(vuint32mf2_t *v0, vuint32mf2_t *v1, vuint32mf2_t *v2, vbool64_t mask, vuint32mf2_t maskedoff0, vuint32mf2_t maskedoff1, vuint32mf2_t maskedoff2, const uint32_t *base, size_t vl) { + return __riscv_vlseg3e32_mu(v0, v1, v2, mask, maskedoff0, maskedoff1, maskedoff2, base, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlseg3e32_v_u32m1_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vlseg3.mask.nxv2i32.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 4 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 4 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 4 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg3e32_v_u32m1_mu(vuint32m1_t *v0, vuint32m1_t *v1, vuint32m1_t *v2, vbool32_t mask, vuint32m1_t maskedoff0, vuint32m1_t maskedoff1, vuint32m1_t maskedoff2, const uint32_t *base, size_t vl) { + return __riscv_vlseg3e32_mu(v0, v1, v2, mask, maskedoff0, maskedoff1, maskedoff2, base, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlseg3e32_v_u32m2_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vlseg3.mask.nxv4i32.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 4 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 4 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 4 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg3e32_v_u32m2_mu(vuint32m2_t *v0, vuint32m2_t *v1, vuint32m2_t *v2, vbool16_t mask, vuint32m2_t maskedoff0, vuint32m2_t maskedoff1, vuint32m2_t maskedoff2, const uint32_t *base, size_t vl) { + return __riscv_vlseg3e32_mu(v0, v1, v2, mask, maskedoff0, maskedoff1, maskedoff2, base, vl); +} + diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e32ff.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e32ff.c index c77bb1f458892..ead18fe78396b 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e32ff.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e32ff.c @@ -493,3 +493,165 @@ void test_vlseg3e32ff_v_u32m2_tumu(vuint32m2_t *v0, vuint32m2_t *v1, vuint32m2_t return __riscv_vlseg3e32ff_tumu(v0, v1, v2, mask, maskedoff0, maskedoff1, maskedoff2, base, new_vl, vl); } +// CHECK-RV64-LABEL: define dso_local void @test_vlseg3e32ff_v_f32mf2_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , i64 } @llvm.riscv.vlseg3ff.mask.nxv1f32.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 4 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 4 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 4 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , i64 } [[TMP0]], 3 +// CHECK-RV64-NEXT: store i64 [[TMP4]], ptr [[NEW_VL]], align 4 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg3e32ff_v_f32mf2_mu(vfloat32mf2_t *v0, vfloat32mf2_t *v1, vfloat32mf2_t *v2, vbool64_t mask, vfloat32mf2_t maskedoff0, vfloat32mf2_t maskedoff1, vfloat32mf2_t maskedoff2, const float *base, size_t *new_vl, size_t vl) { + return __riscv_vlseg3e32ff_mu(v0, v1, v2, mask, maskedoff0, maskedoff1, maskedoff2, base, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlseg3e32ff_v_f32m1_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , i64 } @llvm.riscv.vlseg3ff.mask.nxv2f32.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 4 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 4 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 4 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , i64 } [[TMP0]], 3 +// CHECK-RV64-NEXT: store i64 [[TMP4]], ptr [[NEW_VL]], align 4 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg3e32ff_v_f32m1_mu(vfloat32m1_t *v0, vfloat32m1_t *v1, vfloat32m1_t *v2, vbool32_t mask, vfloat32m1_t maskedoff0, vfloat32m1_t maskedoff1, vfloat32m1_t maskedoff2, const float *base, size_t *new_vl, size_t vl) { + return __riscv_vlseg3e32ff_mu(v0, v1, v2, mask, maskedoff0, maskedoff1, maskedoff2, base, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlseg3e32ff_v_f32m2_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , i64 } @llvm.riscv.vlseg3ff.mask.nxv4f32.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 4 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 4 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 4 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , i64 } [[TMP0]], 3 +// CHECK-RV64-NEXT: store i64 [[TMP4]], ptr [[NEW_VL]], align 4 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg3e32ff_v_f32m2_mu(vfloat32m2_t *v0, vfloat32m2_t *v1, vfloat32m2_t *v2, vbool16_t mask, vfloat32m2_t maskedoff0, vfloat32m2_t maskedoff1, vfloat32m2_t maskedoff2, const float *base, size_t *new_vl, size_t vl) { + return __riscv_vlseg3e32ff_mu(v0, v1, v2, mask, maskedoff0, maskedoff1, maskedoff2, base, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlseg3e32ff_v_i32mf2_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , i64 } @llvm.riscv.vlseg3ff.mask.nxv1i32.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 4 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 4 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 4 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , i64 } [[TMP0]], 3 +// CHECK-RV64-NEXT: store i64 [[TMP4]], ptr [[NEW_VL]], align 4 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg3e32ff_v_i32mf2_mu(vint32mf2_t *v0, vint32mf2_t *v1, vint32mf2_t *v2, vbool64_t mask, vint32mf2_t maskedoff0, vint32mf2_t maskedoff1, vint32mf2_t maskedoff2, const int32_t *base, size_t *new_vl, size_t vl) { + return __riscv_vlseg3e32ff_mu(v0, v1, v2, mask, maskedoff0, maskedoff1, maskedoff2, base, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlseg3e32ff_v_i32m1_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , i64 } @llvm.riscv.vlseg3ff.mask.nxv2i32.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 4 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 4 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 4 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , i64 } [[TMP0]], 3 +// CHECK-RV64-NEXT: store i64 [[TMP4]], ptr [[NEW_VL]], align 4 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg3e32ff_v_i32m1_mu(vint32m1_t *v0, vint32m1_t *v1, vint32m1_t *v2, vbool32_t mask, vint32m1_t maskedoff0, vint32m1_t maskedoff1, vint32m1_t maskedoff2, const int32_t *base, size_t *new_vl, size_t vl) { + return __riscv_vlseg3e32ff_mu(v0, v1, v2, mask, maskedoff0, maskedoff1, maskedoff2, base, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlseg3e32ff_v_i32m2_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , i64 } @llvm.riscv.vlseg3ff.mask.nxv4i32.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 4 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 4 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 4 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , i64 } [[TMP0]], 3 +// CHECK-RV64-NEXT: store i64 [[TMP4]], ptr [[NEW_VL]], align 4 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg3e32ff_v_i32m2_mu(vint32m2_t *v0, vint32m2_t *v1, vint32m2_t *v2, vbool16_t mask, vint32m2_t maskedoff0, vint32m2_t maskedoff1, vint32m2_t maskedoff2, const int32_t *base, size_t *new_vl, size_t vl) { + return __riscv_vlseg3e32ff_mu(v0, v1, v2, mask, maskedoff0, maskedoff1, maskedoff2, base, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlseg3e32ff_v_u32mf2_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , i64 } @llvm.riscv.vlseg3ff.mask.nxv1i32.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 4 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 4 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 4 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , i64 } [[TMP0]], 3 +// CHECK-RV64-NEXT: store i64 [[TMP4]], ptr [[NEW_VL]], align 4 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg3e32ff_v_u32mf2_mu(vuint32mf2_t *v0, vuint32mf2_t *v1, vuint32mf2_t *v2, vbool64_t mask, vuint32mf2_t maskedoff0, vuint32mf2_t maskedoff1, vuint32mf2_t maskedoff2, const uint32_t *base, size_t *new_vl, size_t vl) { + return __riscv_vlseg3e32ff_mu(v0, v1, v2, mask, maskedoff0, maskedoff1, maskedoff2, base, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlseg3e32ff_v_u32m1_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , i64 } @llvm.riscv.vlseg3ff.mask.nxv2i32.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 4 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 4 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 4 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , i64 } [[TMP0]], 3 +// CHECK-RV64-NEXT: store i64 [[TMP4]], ptr [[NEW_VL]], align 4 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg3e32ff_v_u32m1_mu(vuint32m1_t *v0, vuint32m1_t *v1, vuint32m1_t *v2, vbool32_t mask, vuint32m1_t maskedoff0, vuint32m1_t maskedoff1, vuint32m1_t maskedoff2, const uint32_t *base, size_t *new_vl, size_t vl) { + return __riscv_vlseg3e32ff_mu(v0, v1, v2, mask, maskedoff0, maskedoff1, maskedoff2, base, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlseg3e32ff_v_u32m2_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , i64 } @llvm.riscv.vlseg3ff.mask.nxv4i32.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 4 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 4 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 4 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , i64 } [[TMP0]], 3 +// CHECK-RV64-NEXT: store i64 [[TMP4]], ptr [[NEW_VL]], align 4 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg3e32ff_v_u32m2_mu(vuint32m2_t *v0, vuint32m2_t *v1, vuint32m2_t *v2, vbool16_t mask, vuint32m2_t maskedoff0, vuint32m2_t maskedoff1, vuint32m2_t maskedoff2, const uint32_t *base, size_t *new_vl, size_t vl) { + return __riscv_vlseg3e32ff_mu(v0, v1, v2, mask, maskedoff0, maskedoff1, maskedoff2, base, new_vl, vl); +} + diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e64.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e64.c index 819a87776d535..186c43d0bc313 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e64.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e64.c @@ -295,3 +295,99 @@ void test_vlseg3e64_v_u64m2_tumu(vuint64m2_t *v0, vuint64m2_t *v1, vuint64m2_t * return __riscv_vlseg3e64_tumu(v0, v1, v2, mask, maskedoff0, maskedoff1, maskedoff2, base, vl); } +// CHECK-RV64-LABEL: define dso_local void @test_vlseg3e64_v_f64m1_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vlseg3.mask.nxv1f64.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 8 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 8 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 8 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg3e64_v_f64m1_mu(vfloat64m1_t *v0, vfloat64m1_t *v1, vfloat64m1_t *v2, vbool64_t mask, vfloat64m1_t maskedoff0, vfloat64m1_t maskedoff1, vfloat64m1_t maskedoff2, const double *base, size_t vl) { + return __riscv_vlseg3e64_mu(v0, v1, v2, mask, maskedoff0, maskedoff1, maskedoff2, base, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlseg3e64_v_f64m2_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vlseg3.mask.nxv2f64.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 8 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 8 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 8 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg3e64_v_f64m2_mu(vfloat64m2_t *v0, vfloat64m2_t *v1, vfloat64m2_t *v2, vbool32_t mask, vfloat64m2_t maskedoff0, vfloat64m2_t maskedoff1, vfloat64m2_t maskedoff2, const double *base, size_t vl) { + return __riscv_vlseg3e64_mu(v0, v1, v2, mask, maskedoff0, maskedoff1, maskedoff2, base, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlseg3e64_v_i64m1_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vlseg3.mask.nxv1i64.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 8 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 8 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 8 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg3e64_v_i64m1_mu(vint64m1_t *v0, vint64m1_t *v1, vint64m1_t *v2, vbool64_t mask, vint64m1_t maskedoff0, vint64m1_t maskedoff1, vint64m1_t maskedoff2, const int64_t *base, size_t vl) { + return __riscv_vlseg3e64_mu(v0, v1, v2, mask, maskedoff0, maskedoff1, maskedoff2, base, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlseg3e64_v_i64m2_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vlseg3.mask.nxv2i64.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 8 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 8 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 8 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg3e64_v_i64m2_mu(vint64m2_t *v0, vint64m2_t *v1, vint64m2_t *v2, vbool32_t mask, vint64m2_t maskedoff0, vint64m2_t maskedoff1, vint64m2_t maskedoff2, const int64_t *base, size_t vl) { + return __riscv_vlseg3e64_mu(v0, v1, v2, mask, maskedoff0, maskedoff1, maskedoff2, base, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlseg3e64_v_u64m1_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vlseg3.mask.nxv1i64.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 8 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 8 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 8 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg3e64_v_u64m1_mu(vuint64m1_t *v0, vuint64m1_t *v1, vuint64m1_t *v2, vbool64_t mask, vuint64m1_t maskedoff0, vuint64m1_t maskedoff1, vuint64m1_t maskedoff2, const uint64_t *base, size_t vl) { + return __riscv_vlseg3e64_mu(v0, v1, v2, mask, maskedoff0, maskedoff1, maskedoff2, base, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlseg3e64_v_u64m2_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vlseg3.mask.nxv2i64.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 8 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 8 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 8 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg3e64_v_u64m2_mu(vuint64m2_t *v0, vuint64m2_t *v1, vuint64m2_t *v2, vbool32_t mask, vuint64m2_t maskedoff0, vuint64m2_t maskedoff1, vuint64m2_t maskedoff2, const uint64_t *base, size_t vl) { + return __riscv_vlseg3e64_mu(v0, v1, v2, mask, maskedoff0, maskedoff1, maskedoff2, base, vl); +} + diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e64ff.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e64ff.c index 7f094da110402..528d4d04ae72e 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e64ff.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e64ff.c @@ -331,3 +331,111 @@ void test_vlseg3e64ff_v_u64m2_tumu(vuint64m2_t *v0, vuint64m2_t *v1, vuint64m2_t return __riscv_vlseg3e64ff_tumu(v0, v1, v2, mask, maskedoff0, maskedoff1, maskedoff2, base, new_vl, vl); } +// CHECK-RV64-LABEL: define dso_local void @test_vlseg3e64ff_v_f64m1_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , i64 } @llvm.riscv.vlseg3ff.mask.nxv1f64.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 8 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 8 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 8 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , i64 } [[TMP0]], 3 +// CHECK-RV64-NEXT: store i64 [[TMP4]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg3e64ff_v_f64m1_mu(vfloat64m1_t *v0, vfloat64m1_t *v1, vfloat64m1_t *v2, vbool64_t mask, vfloat64m1_t maskedoff0, vfloat64m1_t maskedoff1, vfloat64m1_t maskedoff2, const double *base, size_t *new_vl, size_t vl) { + return __riscv_vlseg3e64ff_mu(v0, v1, v2, mask, maskedoff0, maskedoff1, maskedoff2, base, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlseg3e64ff_v_f64m2_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , i64 } @llvm.riscv.vlseg3ff.mask.nxv2f64.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 8 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 8 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 8 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , i64 } [[TMP0]], 3 +// CHECK-RV64-NEXT: store i64 [[TMP4]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg3e64ff_v_f64m2_mu(vfloat64m2_t *v0, vfloat64m2_t *v1, vfloat64m2_t *v2, vbool32_t mask, vfloat64m2_t maskedoff0, vfloat64m2_t maskedoff1, vfloat64m2_t maskedoff2, const double *base, size_t *new_vl, size_t vl) { + return __riscv_vlseg3e64ff_mu(v0, v1, v2, mask, maskedoff0, maskedoff1, maskedoff2, base, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlseg3e64ff_v_i64m1_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , i64 } @llvm.riscv.vlseg3ff.mask.nxv1i64.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 8 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 8 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 8 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , i64 } [[TMP0]], 3 +// CHECK-RV64-NEXT: store i64 [[TMP4]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg3e64ff_v_i64m1_mu(vint64m1_t *v0, vint64m1_t *v1, vint64m1_t *v2, vbool64_t mask, vint64m1_t maskedoff0, vint64m1_t maskedoff1, vint64m1_t maskedoff2, const int64_t *base, size_t *new_vl, size_t vl) { + return __riscv_vlseg3e64ff_mu(v0, v1, v2, mask, maskedoff0, maskedoff1, maskedoff2, base, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlseg3e64ff_v_i64m2_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , i64 } @llvm.riscv.vlseg3ff.mask.nxv2i64.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 8 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 8 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 8 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , i64 } [[TMP0]], 3 +// CHECK-RV64-NEXT: store i64 [[TMP4]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg3e64ff_v_i64m2_mu(vint64m2_t *v0, vint64m2_t *v1, vint64m2_t *v2, vbool32_t mask, vint64m2_t maskedoff0, vint64m2_t maskedoff1, vint64m2_t maskedoff2, const int64_t *base, size_t *new_vl, size_t vl) { + return __riscv_vlseg3e64ff_mu(v0, v1, v2, mask, maskedoff0, maskedoff1, maskedoff2, base, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlseg3e64ff_v_u64m1_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , i64 } @llvm.riscv.vlseg3ff.mask.nxv1i64.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 8 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 8 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 8 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , i64 } [[TMP0]], 3 +// CHECK-RV64-NEXT: store i64 [[TMP4]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg3e64ff_v_u64m1_mu(vuint64m1_t *v0, vuint64m1_t *v1, vuint64m1_t *v2, vbool64_t mask, vuint64m1_t maskedoff0, vuint64m1_t maskedoff1, vuint64m1_t maskedoff2, const uint64_t *base, size_t *new_vl, size_t vl) { + return __riscv_vlseg3e64ff_mu(v0, v1, v2, mask, maskedoff0, maskedoff1, maskedoff2, base, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlseg3e64ff_v_u64m2_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , i64 } @llvm.riscv.vlseg3ff.mask.nxv2i64.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 8 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 8 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 8 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , i64 } [[TMP0]], 3 +// CHECK-RV64-NEXT: store i64 [[TMP4]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg3e64ff_v_u64m2_mu(vuint64m2_t *v0, vuint64m2_t *v1, vuint64m2_t *v2, vbool32_t mask, vuint64m2_t maskedoff0, vuint64m2_t maskedoff1, vuint64m2_t maskedoff2, const uint64_t *base, size_t *new_vl, size_t vl) { + return __riscv_vlseg3e64ff_mu(v0, v1, v2, mask, maskedoff0, maskedoff1, maskedoff2, base, new_vl, vl); +} + diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e8.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e8.c index 8390c6078ce6e..0b5eb32960d15 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e8.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e8.c @@ -486,3 +486,163 @@ void test_vlseg3e8_v_u8m2_tumu(vuint8m2_t *v0, vuint8m2_t *v1, vuint8m2_t *v2, v return __riscv_vlseg3e8_tumu(v0, v1, v2, mask, maskedoff0, maskedoff1, maskedoff2, base, vl); } +// CHECK-RV64-LABEL: define dso_local void @test_vlseg3e8_v_i8mf8_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vlseg3.mask.nxv1i8.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 1 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 1 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg3e8_v_i8mf8_mu(vint8mf8_t *v0, vint8mf8_t *v1, vint8mf8_t *v2, vbool64_t mask, vint8mf8_t maskedoff0, vint8mf8_t maskedoff1, vint8mf8_t maskedoff2, const int8_t *base, size_t vl) { + return __riscv_vlseg3e8_mu(v0, v1, v2, mask, maskedoff0, maskedoff1, maskedoff2, base, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlseg3e8_v_i8mf4_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vlseg3.mask.nxv2i8.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 1 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 1 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg3e8_v_i8mf4_mu(vint8mf4_t *v0, vint8mf4_t *v1, vint8mf4_t *v2, vbool32_t mask, vint8mf4_t maskedoff0, vint8mf4_t maskedoff1, vint8mf4_t maskedoff2, const int8_t *base, size_t vl) { + return __riscv_vlseg3e8_mu(v0, v1, v2, mask, maskedoff0, maskedoff1, maskedoff2, base, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlseg3e8_v_i8mf2_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vlseg3.mask.nxv4i8.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 1 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 1 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg3e8_v_i8mf2_mu(vint8mf2_t *v0, vint8mf2_t *v1, vint8mf2_t *v2, vbool16_t mask, vint8mf2_t maskedoff0, vint8mf2_t maskedoff1, vint8mf2_t maskedoff2, const int8_t *base, size_t vl) { + return __riscv_vlseg3e8_mu(v0, v1, v2, mask, maskedoff0, maskedoff1, maskedoff2, base, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlseg3e8_v_i8m1_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vlseg3.mask.nxv8i8.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 1 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 1 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg3e8_v_i8m1_mu(vint8m1_t *v0, vint8m1_t *v1, vint8m1_t *v2, vbool8_t mask, vint8m1_t maskedoff0, vint8m1_t maskedoff1, vint8m1_t maskedoff2, const int8_t *base, size_t vl) { + return __riscv_vlseg3e8_mu(v0, v1, v2, mask, maskedoff0, maskedoff1, maskedoff2, base, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlseg3e8_v_i8m2_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vlseg3.mask.nxv16i8.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 1 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 1 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg3e8_v_i8m2_mu(vint8m2_t *v0, vint8m2_t *v1, vint8m2_t *v2, vbool4_t mask, vint8m2_t maskedoff0, vint8m2_t maskedoff1, vint8m2_t maskedoff2, const int8_t *base, size_t vl) { + return __riscv_vlseg3e8_mu(v0, v1, v2, mask, maskedoff0, maskedoff1, maskedoff2, base, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlseg3e8_v_u8mf8_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vlseg3.mask.nxv1i8.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 1 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 1 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg3e8_v_u8mf8_mu(vuint8mf8_t *v0, vuint8mf8_t *v1, vuint8mf8_t *v2, vbool64_t mask, vuint8mf8_t maskedoff0, vuint8mf8_t maskedoff1, vuint8mf8_t maskedoff2, const uint8_t *base, size_t vl) { + return __riscv_vlseg3e8_mu(v0, v1, v2, mask, maskedoff0, maskedoff1, maskedoff2, base, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlseg3e8_v_u8mf4_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vlseg3.mask.nxv2i8.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 1 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 1 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg3e8_v_u8mf4_mu(vuint8mf4_t *v0, vuint8mf4_t *v1, vuint8mf4_t *v2, vbool32_t mask, vuint8mf4_t maskedoff0, vuint8mf4_t maskedoff1, vuint8mf4_t maskedoff2, const uint8_t *base, size_t vl) { + return __riscv_vlseg3e8_mu(v0, v1, v2, mask, maskedoff0, maskedoff1, maskedoff2, base, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlseg3e8_v_u8mf2_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vlseg3.mask.nxv4i8.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 1 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 1 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg3e8_v_u8mf2_mu(vuint8mf2_t *v0, vuint8mf2_t *v1, vuint8mf2_t *v2, vbool16_t mask, vuint8mf2_t maskedoff0, vuint8mf2_t maskedoff1, vuint8mf2_t maskedoff2, const uint8_t *base, size_t vl) { + return __riscv_vlseg3e8_mu(v0, v1, v2, mask, maskedoff0, maskedoff1, maskedoff2, base, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlseg3e8_v_u8m1_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vlseg3.mask.nxv8i8.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 1 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 1 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg3e8_v_u8m1_mu(vuint8m1_t *v0, vuint8m1_t *v1, vuint8m1_t *v2, vbool8_t mask, vuint8m1_t maskedoff0, vuint8m1_t maskedoff1, vuint8m1_t maskedoff2, const uint8_t *base, size_t vl) { + return __riscv_vlseg3e8_mu(v0, v1, v2, mask, maskedoff0, maskedoff1, maskedoff2, base, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlseg3e8_v_u8m2_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vlseg3.mask.nxv16i8.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 1 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 1 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg3e8_v_u8m2_mu(vuint8m2_t *v0, vuint8m2_t *v1, vuint8m2_t *v2, vbool4_t mask, vuint8m2_t maskedoff0, vuint8m2_t maskedoff1, vuint8m2_t maskedoff2, const uint8_t *base, size_t vl) { + return __riscv_vlseg3e8_mu(v0, v1, v2, mask, maskedoff0, maskedoff1, maskedoff2, base, vl); +} + diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e8ff.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e8ff.c index bb7a264d1d5d6..25192537898d8 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e8ff.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e8ff.c @@ -547,3 +547,183 @@ void test_vlseg3e8ff_v_u8m2_tumu(vuint8m2_t *v0, vuint8m2_t *v1, vuint8m2_t *v2, return __riscv_vlseg3e8ff_tumu(v0, v1, v2, mask, maskedoff0, maskedoff1, maskedoff2, base, new_vl, vl); } +// CHECK-RV64-LABEL: define dso_local void @test_vlseg3e8ff_v_i8mf8_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , i64 } @llvm.riscv.vlseg3ff.mask.nxv1i8.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 1 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 1 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , i64 } [[TMP0]], 3 +// CHECK-RV64-NEXT: store i64 [[TMP4]], ptr [[NEW_VL]], align 1 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg3e8ff_v_i8mf8_mu(vint8mf8_t *v0, vint8mf8_t *v1, vint8mf8_t *v2, vbool64_t mask, vint8mf8_t maskedoff0, vint8mf8_t maskedoff1, vint8mf8_t maskedoff2, const int8_t *base, size_t *new_vl, size_t vl) { + return __riscv_vlseg3e8ff_mu(v0, v1, v2, mask, maskedoff0, maskedoff1, maskedoff2, base, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlseg3e8ff_v_i8mf4_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , i64 } @llvm.riscv.vlseg3ff.mask.nxv2i8.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 1 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 1 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , i64 } [[TMP0]], 3 +// CHECK-RV64-NEXT: store i64 [[TMP4]], ptr [[NEW_VL]], align 1 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg3e8ff_v_i8mf4_mu(vint8mf4_t *v0, vint8mf4_t *v1, vint8mf4_t *v2, vbool32_t mask, vint8mf4_t maskedoff0, vint8mf4_t maskedoff1, vint8mf4_t maskedoff2, const int8_t *base, size_t *new_vl, size_t vl) { + return __riscv_vlseg3e8ff_mu(v0, v1, v2, mask, maskedoff0, maskedoff1, maskedoff2, base, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlseg3e8ff_v_i8mf2_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , i64 } @llvm.riscv.vlseg3ff.mask.nxv4i8.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 1 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 1 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , i64 } [[TMP0]], 3 +// CHECK-RV64-NEXT: store i64 [[TMP4]], ptr [[NEW_VL]], align 1 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg3e8ff_v_i8mf2_mu(vint8mf2_t *v0, vint8mf2_t *v1, vint8mf2_t *v2, vbool16_t mask, vint8mf2_t maskedoff0, vint8mf2_t maskedoff1, vint8mf2_t maskedoff2, const int8_t *base, size_t *new_vl, size_t vl) { + return __riscv_vlseg3e8ff_mu(v0, v1, v2, mask, maskedoff0, maskedoff1, maskedoff2, base, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlseg3e8ff_v_i8m1_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , i64 } @llvm.riscv.vlseg3ff.mask.nxv8i8.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 1 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 1 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , i64 } [[TMP0]], 3 +// CHECK-RV64-NEXT: store i64 [[TMP4]], ptr [[NEW_VL]], align 1 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg3e8ff_v_i8m1_mu(vint8m1_t *v0, vint8m1_t *v1, vint8m1_t *v2, vbool8_t mask, vint8m1_t maskedoff0, vint8m1_t maskedoff1, vint8m1_t maskedoff2, const int8_t *base, size_t *new_vl, size_t vl) { + return __riscv_vlseg3e8ff_mu(v0, v1, v2, mask, maskedoff0, maskedoff1, maskedoff2, base, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlseg3e8ff_v_i8m2_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , i64 } @llvm.riscv.vlseg3ff.mask.nxv16i8.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 1 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 1 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , i64 } [[TMP0]], 3 +// CHECK-RV64-NEXT: store i64 [[TMP4]], ptr [[NEW_VL]], align 1 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg3e8ff_v_i8m2_mu(vint8m2_t *v0, vint8m2_t *v1, vint8m2_t *v2, vbool4_t mask, vint8m2_t maskedoff0, vint8m2_t maskedoff1, vint8m2_t maskedoff2, const int8_t *base, size_t *new_vl, size_t vl) { + return __riscv_vlseg3e8ff_mu(v0, v1, v2, mask, maskedoff0, maskedoff1, maskedoff2, base, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlseg3e8ff_v_u8mf8_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , i64 } @llvm.riscv.vlseg3ff.mask.nxv1i8.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 1 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 1 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , i64 } [[TMP0]], 3 +// CHECK-RV64-NEXT: store i64 [[TMP4]], ptr [[NEW_VL]], align 1 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg3e8ff_v_u8mf8_mu(vuint8mf8_t *v0, vuint8mf8_t *v1, vuint8mf8_t *v2, vbool64_t mask, vuint8mf8_t maskedoff0, vuint8mf8_t maskedoff1, vuint8mf8_t maskedoff2, const uint8_t *base, size_t *new_vl, size_t vl) { + return __riscv_vlseg3e8ff_mu(v0, v1, v2, mask, maskedoff0, maskedoff1, maskedoff2, base, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlseg3e8ff_v_u8mf4_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , i64 } @llvm.riscv.vlseg3ff.mask.nxv2i8.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 1 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 1 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , i64 } [[TMP0]], 3 +// CHECK-RV64-NEXT: store i64 [[TMP4]], ptr [[NEW_VL]], align 1 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg3e8ff_v_u8mf4_mu(vuint8mf4_t *v0, vuint8mf4_t *v1, vuint8mf4_t *v2, vbool32_t mask, vuint8mf4_t maskedoff0, vuint8mf4_t maskedoff1, vuint8mf4_t maskedoff2, const uint8_t *base, size_t *new_vl, size_t vl) { + return __riscv_vlseg3e8ff_mu(v0, v1, v2, mask, maskedoff0, maskedoff1, maskedoff2, base, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlseg3e8ff_v_u8mf2_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , i64 } @llvm.riscv.vlseg3ff.mask.nxv4i8.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 1 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 1 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , i64 } [[TMP0]], 3 +// CHECK-RV64-NEXT: store i64 [[TMP4]], ptr [[NEW_VL]], align 1 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg3e8ff_v_u8mf2_mu(vuint8mf2_t *v0, vuint8mf2_t *v1, vuint8mf2_t *v2, vbool16_t mask, vuint8mf2_t maskedoff0, vuint8mf2_t maskedoff1, vuint8mf2_t maskedoff2, const uint8_t *base, size_t *new_vl, size_t vl) { + return __riscv_vlseg3e8ff_mu(v0, v1, v2, mask, maskedoff0, maskedoff1, maskedoff2, base, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlseg3e8ff_v_u8m1_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , i64 } @llvm.riscv.vlseg3ff.mask.nxv8i8.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 1 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 1 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , i64 } [[TMP0]], 3 +// CHECK-RV64-NEXT: store i64 [[TMP4]], ptr [[NEW_VL]], align 1 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg3e8ff_v_u8m1_mu(vuint8m1_t *v0, vuint8m1_t *v1, vuint8m1_t *v2, vbool8_t mask, vuint8m1_t maskedoff0, vuint8m1_t maskedoff1, vuint8m1_t maskedoff2, const uint8_t *base, size_t *new_vl, size_t vl) { + return __riscv_vlseg3e8ff_mu(v0, v1, v2, mask, maskedoff0, maskedoff1, maskedoff2, base, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlseg3e8ff_v_u8m2_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , i64 } @llvm.riscv.vlseg3ff.mask.nxv16i8.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 1 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 1 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , i64 } [[TMP0]], 3 +// CHECK-RV64-NEXT: store i64 [[TMP4]], ptr [[NEW_VL]], align 1 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg3e8ff_v_u8m2_mu(vuint8m2_t *v0, vuint8m2_t *v1, vuint8m2_t *v2, vbool4_t mask, vuint8m2_t maskedoff0, vuint8m2_t maskedoff1, vuint8m2_t maskedoff2, const uint8_t *base, size_t *new_vl, size_t vl) { + return __riscv_vlseg3e8ff_mu(v0, v1, v2, mask, maskedoff0, maskedoff1, maskedoff2, base, new_vl, vl); +} + diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e16.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e16.c index 211994b8d780d..fc7443078acf7 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e16.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e16.c @@ -655,3 +655,219 @@ void test_vlseg4e16_v_u16m2_tumu(vuint16m2_t *v0, vuint16m2_t *v1, vuint16m2_t * return __riscv_vlseg4e16_tumu(v0, v1, v2, v3, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, base, vl); } +// CHECK-RV64-LABEL: define dso_local void @test_vlseg4e16_v_f16mf4_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vlseg4.mask.nxv1f16.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 2 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 2 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 2 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg4e16_v_f16mf4_mu(vfloat16mf4_t *v0, vfloat16mf4_t *v1, vfloat16mf4_t *v2, vfloat16mf4_t *v3, vbool64_t mask, vfloat16mf4_t maskedoff0, vfloat16mf4_t maskedoff1, vfloat16mf4_t maskedoff2, vfloat16mf4_t maskedoff3, const _Float16 *base, size_t vl) { + return __riscv_vlseg4e16_mu(v0, v1, v2, v3, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, base, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlseg4e16_v_f16mf2_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vlseg4.mask.nxv2f16.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 2 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 2 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 2 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg4e16_v_f16mf2_mu(vfloat16mf2_t *v0, vfloat16mf2_t *v1, vfloat16mf2_t *v2, vfloat16mf2_t *v3, vbool32_t mask, vfloat16mf2_t maskedoff0, vfloat16mf2_t maskedoff1, vfloat16mf2_t maskedoff2, vfloat16mf2_t maskedoff3, const _Float16 *base, size_t vl) { + return __riscv_vlseg4e16_mu(v0, v1, v2, v3, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, base, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlseg4e16_v_f16m1_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vlseg4.mask.nxv4f16.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 2 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 2 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 2 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg4e16_v_f16m1_mu(vfloat16m1_t *v0, vfloat16m1_t *v1, vfloat16m1_t *v2, vfloat16m1_t *v3, vbool16_t mask, vfloat16m1_t maskedoff0, vfloat16m1_t maskedoff1, vfloat16m1_t maskedoff2, vfloat16m1_t maskedoff3, const _Float16 *base, size_t vl) { + return __riscv_vlseg4e16_mu(v0, v1, v2, v3, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, base, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlseg4e16_v_f16m2_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vlseg4.mask.nxv8f16.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 2 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 2 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 2 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg4e16_v_f16m2_mu(vfloat16m2_t *v0, vfloat16m2_t *v1, vfloat16m2_t *v2, vfloat16m2_t *v3, vbool8_t mask, vfloat16m2_t maskedoff0, vfloat16m2_t maskedoff1, vfloat16m2_t maskedoff2, vfloat16m2_t maskedoff3, const _Float16 *base, size_t vl) { + return __riscv_vlseg4e16_mu(v0, v1, v2, v3, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, base, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlseg4e16_v_i16mf4_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vlseg4.mask.nxv1i16.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 2 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 2 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 2 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg4e16_v_i16mf4_mu(vint16mf4_t *v0, vint16mf4_t *v1, vint16mf4_t *v2, vint16mf4_t *v3, vbool64_t mask, vint16mf4_t maskedoff0, vint16mf4_t maskedoff1, vint16mf4_t maskedoff2, vint16mf4_t maskedoff3, const int16_t *base, size_t vl) { + return __riscv_vlseg4e16_mu(v0, v1, v2, v3, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, base, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlseg4e16_v_i16mf2_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vlseg4.mask.nxv2i16.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 2 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 2 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 2 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg4e16_v_i16mf2_mu(vint16mf2_t *v0, vint16mf2_t *v1, vint16mf2_t *v2, vint16mf2_t *v3, vbool32_t mask, vint16mf2_t maskedoff0, vint16mf2_t maskedoff1, vint16mf2_t maskedoff2, vint16mf2_t maskedoff3, const int16_t *base, size_t vl) { + return __riscv_vlseg4e16_mu(v0, v1, v2, v3, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, base, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlseg4e16_v_i16m1_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vlseg4.mask.nxv4i16.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 2 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 2 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 2 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg4e16_v_i16m1_mu(vint16m1_t *v0, vint16m1_t *v1, vint16m1_t *v2, vint16m1_t *v3, vbool16_t mask, vint16m1_t maskedoff0, vint16m1_t maskedoff1, vint16m1_t maskedoff2, vint16m1_t maskedoff3, const int16_t *base, size_t vl) { + return __riscv_vlseg4e16_mu(v0, v1, v2, v3, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, base, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlseg4e16_v_i16m2_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vlseg4.mask.nxv8i16.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 2 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 2 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 2 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg4e16_v_i16m2_mu(vint16m2_t *v0, vint16m2_t *v1, vint16m2_t *v2, vint16m2_t *v3, vbool8_t mask, vint16m2_t maskedoff0, vint16m2_t maskedoff1, vint16m2_t maskedoff2, vint16m2_t maskedoff3, const int16_t *base, size_t vl) { + return __riscv_vlseg4e16_mu(v0, v1, v2, v3, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, base, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlseg4e16_v_u16mf4_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vlseg4.mask.nxv1i16.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 2 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 2 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 2 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg4e16_v_u16mf4_mu(vuint16mf4_t *v0, vuint16mf4_t *v1, vuint16mf4_t *v2, vuint16mf4_t *v3, vbool64_t mask, vuint16mf4_t maskedoff0, vuint16mf4_t maskedoff1, vuint16mf4_t maskedoff2, vuint16mf4_t maskedoff3, const uint16_t *base, size_t vl) { + return __riscv_vlseg4e16_mu(v0, v1, v2, v3, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, base, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlseg4e16_v_u16mf2_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vlseg4.mask.nxv2i16.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 2 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 2 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 2 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg4e16_v_u16mf2_mu(vuint16mf2_t *v0, vuint16mf2_t *v1, vuint16mf2_t *v2, vuint16mf2_t *v3, vbool32_t mask, vuint16mf2_t maskedoff0, vuint16mf2_t maskedoff1, vuint16mf2_t maskedoff2, vuint16mf2_t maskedoff3, const uint16_t *base, size_t vl) { + return __riscv_vlseg4e16_mu(v0, v1, v2, v3, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, base, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlseg4e16_v_u16m1_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vlseg4.mask.nxv4i16.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 2 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 2 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 2 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg4e16_v_u16m1_mu(vuint16m1_t *v0, vuint16m1_t *v1, vuint16m1_t *v2, vuint16m1_t *v3, vbool16_t mask, vuint16m1_t maskedoff0, vuint16m1_t maskedoff1, vuint16m1_t maskedoff2, vuint16m1_t maskedoff3, const uint16_t *base, size_t vl) { + return __riscv_vlseg4e16_mu(v0, v1, v2, v3, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, base, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlseg4e16_v_u16m2_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vlseg4.mask.nxv8i16.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 2 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 2 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 2 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg4e16_v_u16m2_mu(vuint16m2_t *v0, vuint16m2_t *v1, vuint16m2_t *v2, vuint16m2_t *v3, vbool8_t mask, vuint16m2_t maskedoff0, vuint16m2_t maskedoff1, vuint16m2_t maskedoff2, vuint16m2_t maskedoff3, const uint16_t *base, size_t vl) { + return __riscv_vlseg4e16_mu(v0, v1, v2, v3, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, base, vl); +} + diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e16ff.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e16ff.c index cff856ed4e699..7dbbd186092b6 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e16ff.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e16ff.c @@ -727,3 +727,243 @@ void test_vlseg4e16ff_v_u16m2_tumu(vuint16m2_t *v0, vuint16m2_t *v1, vuint16m2_t return __riscv_vlseg4e16ff_tumu(v0, v1, v2, v3, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, base, new_vl, vl); } +// CHECK-RV64-LABEL: define dso_local void @test_vlseg4e16ff_v_f16mf4_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , i64 } @llvm.riscv.vlseg4ff.mask.nxv1f16.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 2 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 2 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 2 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 4 +// CHECK-RV64-NEXT: store i64 [[TMP5]], ptr [[NEW_VL]], align 2 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg4e16ff_v_f16mf4_mu(vfloat16mf4_t *v0, vfloat16mf4_t *v1, vfloat16mf4_t *v2, vfloat16mf4_t *v3, vbool64_t mask, vfloat16mf4_t maskedoff0, vfloat16mf4_t maskedoff1, vfloat16mf4_t maskedoff2, vfloat16mf4_t maskedoff3, const _Float16 *base, size_t *new_vl, size_t vl) { + return __riscv_vlseg4e16ff_mu(v0, v1, v2, v3, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, base, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlseg4e16ff_v_f16mf2_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , i64 } @llvm.riscv.vlseg4ff.mask.nxv2f16.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 2 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 2 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 2 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 4 +// CHECK-RV64-NEXT: store i64 [[TMP5]], ptr [[NEW_VL]], align 2 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg4e16ff_v_f16mf2_mu(vfloat16mf2_t *v0, vfloat16mf2_t *v1, vfloat16mf2_t *v2, vfloat16mf2_t *v3, vbool32_t mask, vfloat16mf2_t maskedoff0, vfloat16mf2_t maskedoff1, vfloat16mf2_t maskedoff2, vfloat16mf2_t maskedoff3, const _Float16 *base, size_t *new_vl, size_t vl) { + return __riscv_vlseg4e16ff_mu(v0, v1, v2, v3, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, base, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlseg4e16ff_v_f16m1_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , i64 } @llvm.riscv.vlseg4ff.mask.nxv4f16.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 2 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 2 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 2 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 4 +// CHECK-RV64-NEXT: store i64 [[TMP5]], ptr [[NEW_VL]], align 2 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg4e16ff_v_f16m1_mu(vfloat16m1_t *v0, vfloat16m1_t *v1, vfloat16m1_t *v2, vfloat16m1_t *v3, vbool16_t mask, vfloat16m1_t maskedoff0, vfloat16m1_t maskedoff1, vfloat16m1_t maskedoff2, vfloat16m1_t maskedoff3, const _Float16 *base, size_t *new_vl, size_t vl) { + return __riscv_vlseg4e16ff_mu(v0, v1, v2, v3, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, base, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlseg4e16ff_v_f16m2_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , i64 } @llvm.riscv.vlseg4ff.mask.nxv8f16.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 2 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 2 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 2 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 4 +// CHECK-RV64-NEXT: store i64 [[TMP5]], ptr [[NEW_VL]], align 2 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg4e16ff_v_f16m2_mu(vfloat16m2_t *v0, vfloat16m2_t *v1, vfloat16m2_t *v2, vfloat16m2_t *v3, vbool8_t mask, vfloat16m2_t maskedoff0, vfloat16m2_t maskedoff1, vfloat16m2_t maskedoff2, vfloat16m2_t maskedoff3, const _Float16 *base, size_t *new_vl, size_t vl) { + return __riscv_vlseg4e16ff_mu(v0, v1, v2, v3, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, base, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlseg4e16ff_v_i16mf4_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , i64 } @llvm.riscv.vlseg4ff.mask.nxv1i16.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 2 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 2 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 2 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 4 +// CHECK-RV64-NEXT: store i64 [[TMP5]], ptr [[NEW_VL]], align 2 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg4e16ff_v_i16mf4_mu(vint16mf4_t *v0, vint16mf4_t *v1, vint16mf4_t *v2, vint16mf4_t *v3, vbool64_t mask, vint16mf4_t maskedoff0, vint16mf4_t maskedoff1, vint16mf4_t maskedoff2, vint16mf4_t maskedoff3, const int16_t *base, size_t *new_vl, size_t vl) { + return __riscv_vlseg4e16ff_mu(v0, v1, v2, v3, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, base, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlseg4e16ff_v_i16mf2_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , i64 } @llvm.riscv.vlseg4ff.mask.nxv2i16.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 2 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 2 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 2 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 4 +// CHECK-RV64-NEXT: store i64 [[TMP5]], ptr [[NEW_VL]], align 2 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg4e16ff_v_i16mf2_mu(vint16mf2_t *v0, vint16mf2_t *v1, vint16mf2_t *v2, vint16mf2_t *v3, vbool32_t mask, vint16mf2_t maskedoff0, vint16mf2_t maskedoff1, vint16mf2_t maskedoff2, vint16mf2_t maskedoff3, const int16_t *base, size_t *new_vl, size_t vl) { + return __riscv_vlseg4e16ff_mu(v0, v1, v2, v3, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, base, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlseg4e16ff_v_i16m1_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , i64 } @llvm.riscv.vlseg4ff.mask.nxv4i16.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 2 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 2 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 2 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 4 +// CHECK-RV64-NEXT: store i64 [[TMP5]], ptr [[NEW_VL]], align 2 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg4e16ff_v_i16m1_mu(vint16m1_t *v0, vint16m1_t *v1, vint16m1_t *v2, vint16m1_t *v3, vbool16_t mask, vint16m1_t maskedoff0, vint16m1_t maskedoff1, vint16m1_t maskedoff2, vint16m1_t maskedoff3, const int16_t *base, size_t *new_vl, size_t vl) { + return __riscv_vlseg4e16ff_mu(v0, v1, v2, v3, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, base, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlseg4e16ff_v_i16m2_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , i64 } @llvm.riscv.vlseg4ff.mask.nxv8i16.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 2 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 2 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 2 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 4 +// CHECK-RV64-NEXT: store i64 [[TMP5]], ptr [[NEW_VL]], align 2 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg4e16ff_v_i16m2_mu(vint16m2_t *v0, vint16m2_t *v1, vint16m2_t *v2, vint16m2_t *v3, vbool8_t mask, vint16m2_t maskedoff0, vint16m2_t maskedoff1, vint16m2_t maskedoff2, vint16m2_t maskedoff3, const int16_t *base, size_t *new_vl, size_t vl) { + return __riscv_vlseg4e16ff_mu(v0, v1, v2, v3, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, base, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlseg4e16ff_v_u16mf4_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , i64 } @llvm.riscv.vlseg4ff.mask.nxv1i16.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 2 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 2 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 2 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 4 +// CHECK-RV64-NEXT: store i64 [[TMP5]], ptr [[NEW_VL]], align 2 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg4e16ff_v_u16mf4_mu(vuint16mf4_t *v0, vuint16mf4_t *v1, vuint16mf4_t *v2, vuint16mf4_t *v3, vbool64_t mask, vuint16mf4_t maskedoff0, vuint16mf4_t maskedoff1, vuint16mf4_t maskedoff2, vuint16mf4_t maskedoff3, const uint16_t *base, size_t *new_vl, size_t vl) { + return __riscv_vlseg4e16ff_mu(v0, v1, v2, v3, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, base, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlseg4e16ff_v_u16mf2_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , i64 } @llvm.riscv.vlseg4ff.mask.nxv2i16.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 2 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 2 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 2 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 4 +// CHECK-RV64-NEXT: store i64 [[TMP5]], ptr [[NEW_VL]], align 2 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg4e16ff_v_u16mf2_mu(vuint16mf2_t *v0, vuint16mf2_t *v1, vuint16mf2_t *v2, vuint16mf2_t *v3, vbool32_t mask, vuint16mf2_t maskedoff0, vuint16mf2_t maskedoff1, vuint16mf2_t maskedoff2, vuint16mf2_t maskedoff3, const uint16_t *base, size_t *new_vl, size_t vl) { + return __riscv_vlseg4e16ff_mu(v0, v1, v2, v3, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, base, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlseg4e16ff_v_u16m1_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , i64 } @llvm.riscv.vlseg4ff.mask.nxv4i16.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 2 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 2 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 2 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 4 +// CHECK-RV64-NEXT: store i64 [[TMP5]], ptr [[NEW_VL]], align 2 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg4e16ff_v_u16m1_mu(vuint16m1_t *v0, vuint16m1_t *v1, vuint16m1_t *v2, vuint16m1_t *v3, vbool16_t mask, vuint16m1_t maskedoff0, vuint16m1_t maskedoff1, vuint16m1_t maskedoff2, vuint16m1_t maskedoff3, const uint16_t *base, size_t *new_vl, size_t vl) { + return __riscv_vlseg4e16ff_mu(v0, v1, v2, v3, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, base, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlseg4e16ff_v_u16m2_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , i64 } @llvm.riscv.vlseg4ff.mask.nxv8i16.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 2 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 2 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 2 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 4 +// CHECK-RV64-NEXT: store i64 [[TMP5]], ptr [[NEW_VL]], align 2 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg4e16ff_v_u16m2_mu(vuint16m2_t *v0, vuint16m2_t *v1, vuint16m2_t *v2, vuint16m2_t *v3, vbool8_t mask, vuint16m2_t maskedoff0, vuint16m2_t maskedoff1, vuint16m2_t maskedoff2, vuint16m2_t maskedoff3, const uint16_t *base, size_t *new_vl, size_t vl) { + return __riscv_vlseg4e16ff_mu(v0, v1, v2, v3, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, base, new_vl, vl); +} + diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e32.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e32.c index d7d848df927d2..f8bcfd4944372 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e32.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e32.c @@ -493,3 +493,165 @@ void test_vlseg4e32_v_u32m2_tumu(vuint32m2_t *v0, vuint32m2_t *v1, vuint32m2_t * return __riscv_vlseg4e32_tumu(v0, v1, v2, v3, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, base, vl); } +// CHECK-RV64-LABEL: define dso_local void @test_vlseg4e32_v_f32mf2_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vlseg4.mask.nxv1f32.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 4 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 4 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 4 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 4 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg4e32_v_f32mf2_mu(vfloat32mf2_t *v0, vfloat32mf2_t *v1, vfloat32mf2_t *v2, vfloat32mf2_t *v3, vbool64_t mask, vfloat32mf2_t maskedoff0, vfloat32mf2_t maskedoff1, vfloat32mf2_t maskedoff2, vfloat32mf2_t maskedoff3, const float *base, size_t vl) { + return __riscv_vlseg4e32_mu(v0, v1, v2, v3, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, base, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlseg4e32_v_f32m1_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vlseg4.mask.nxv2f32.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 4 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 4 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 4 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 4 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg4e32_v_f32m1_mu(vfloat32m1_t *v0, vfloat32m1_t *v1, vfloat32m1_t *v2, vfloat32m1_t *v3, vbool32_t mask, vfloat32m1_t maskedoff0, vfloat32m1_t maskedoff1, vfloat32m1_t maskedoff2, vfloat32m1_t maskedoff3, const float *base, size_t vl) { + return __riscv_vlseg4e32_mu(v0, v1, v2, v3, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, base, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlseg4e32_v_f32m2_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vlseg4.mask.nxv4f32.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 4 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 4 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 4 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 4 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg4e32_v_f32m2_mu(vfloat32m2_t *v0, vfloat32m2_t *v1, vfloat32m2_t *v2, vfloat32m2_t *v3, vbool16_t mask, vfloat32m2_t maskedoff0, vfloat32m2_t maskedoff1, vfloat32m2_t maskedoff2, vfloat32m2_t maskedoff3, const float *base, size_t vl) { + return __riscv_vlseg4e32_mu(v0, v1, v2, v3, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, base, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlseg4e32_v_i32mf2_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vlseg4.mask.nxv1i32.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 4 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 4 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 4 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 4 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg4e32_v_i32mf2_mu(vint32mf2_t *v0, vint32mf2_t *v1, vint32mf2_t *v2, vint32mf2_t *v3, vbool64_t mask, vint32mf2_t maskedoff0, vint32mf2_t maskedoff1, vint32mf2_t maskedoff2, vint32mf2_t maskedoff3, const int32_t *base, size_t vl) { + return __riscv_vlseg4e32_mu(v0, v1, v2, v3, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, base, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlseg4e32_v_i32m1_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vlseg4.mask.nxv2i32.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 4 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 4 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 4 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 4 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg4e32_v_i32m1_mu(vint32m1_t *v0, vint32m1_t *v1, vint32m1_t *v2, vint32m1_t *v3, vbool32_t mask, vint32m1_t maskedoff0, vint32m1_t maskedoff1, vint32m1_t maskedoff2, vint32m1_t maskedoff3, const int32_t *base, size_t vl) { + return __riscv_vlseg4e32_mu(v0, v1, v2, v3, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, base, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlseg4e32_v_i32m2_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vlseg4.mask.nxv4i32.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 4 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 4 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 4 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 4 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg4e32_v_i32m2_mu(vint32m2_t *v0, vint32m2_t *v1, vint32m2_t *v2, vint32m2_t *v3, vbool16_t mask, vint32m2_t maskedoff0, vint32m2_t maskedoff1, vint32m2_t maskedoff2, vint32m2_t maskedoff3, const int32_t *base, size_t vl) { + return __riscv_vlseg4e32_mu(v0, v1, v2, v3, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, base, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlseg4e32_v_u32mf2_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vlseg4.mask.nxv1i32.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 4 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 4 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 4 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 4 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg4e32_v_u32mf2_mu(vuint32mf2_t *v0, vuint32mf2_t *v1, vuint32mf2_t *v2, vuint32mf2_t *v3, vbool64_t mask, vuint32mf2_t maskedoff0, vuint32mf2_t maskedoff1, vuint32mf2_t maskedoff2, vuint32mf2_t maskedoff3, const uint32_t *base, size_t vl) { + return __riscv_vlseg4e32_mu(v0, v1, v2, v3, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, base, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlseg4e32_v_u32m1_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vlseg4.mask.nxv2i32.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 4 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 4 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 4 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 4 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg4e32_v_u32m1_mu(vuint32m1_t *v0, vuint32m1_t *v1, vuint32m1_t *v2, vuint32m1_t *v3, vbool32_t mask, vuint32m1_t maskedoff0, vuint32m1_t maskedoff1, vuint32m1_t maskedoff2, vuint32m1_t maskedoff3, const uint32_t *base, size_t vl) { + return __riscv_vlseg4e32_mu(v0, v1, v2, v3, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, base, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlseg4e32_v_u32m2_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vlseg4.mask.nxv4i32.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 4 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 4 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 4 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 4 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg4e32_v_u32m2_mu(vuint32m2_t *v0, vuint32m2_t *v1, vuint32m2_t *v2, vuint32m2_t *v3, vbool16_t mask, vuint32m2_t maskedoff0, vuint32m2_t maskedoff1, vuint32m2_t maskedoff2, vuint32m2_t maskedoff3, const uint32_t *base, size_t vl) { + return __riscv_vlseg4e32_mu(v0, v1, v2, v3, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, base, vl); +} + diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e32ff.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e32ff.c index 37c19cd77a576..d2dddaf357c18 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e32ff.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e32ff.c @@ -547,3 +547,183 @@ void test_vlseg4e32ff_v_u32m2_tumu(vuint32m2_t *v0, vuint32m2_t *v1, vuint32m2_t return __riscv_vlseg4e32ff_tumu(v0, v1, v2, v3, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, base, new_vl, vl); } +// CHECK-RV64-LABEL: define dso_local void @test_vlseg4e32ff_v_f32mf2_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , i64 } @llvm.riscv.vlseg4ff.mask.nxv1f32.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 4 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 4 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 4 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 4 +// CHECK-RV64-NEXT: store i64 [[TMP5]], ptr [[NEW_VL]], align 4 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg4e32ff_v_f32mf2_mu(vfloat32mf2_t *v0, vfloat32mf2_t *v1, vfloat32mf2_t *v2, vfloat32mf2_t *v3, vbool64_t mask, vfloat32mf2_t maskedoff0, vfloat32mf2_t maskedoff1, vfloat32mf2_t maskedoff2, vfloat32mf2_t maskedoff3, const float *base, size_t *new_vl, size_t vl) { + return __riscv_vlseg4e32ff_mu(v0, v1, v2, v3, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, base, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlseg4e32ff_v_f32m1_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , i64 } @llvm.riscv.vlseg4ff.mask.nxv2f32.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 4 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 4 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 4 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 4 +// CHECK-RV64-NEXT: store i64 [[TMP5]], ptr [[NEW_VL]], align 4 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg4e32ff_v_f32m1_mu(vfloat32m1_t *v0, vfloat32m1_t *v1, vfloat32m1_t *v2, vfloat32m1_t *v3, vbool32_t mask, vfloat32m1_t maskedoff0, vfloat32m1_t maskedoff1, vfloat32m1_t maskedoff2, vfloat32m1_t maskedoff3, const float *base, size_t *new_vl, size_t vl) { + return __riscv_vlseg4e32ff_mu(v0, v1, v2, v3, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, base, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlseg4e32ff_v_f32m2_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , i64 } @llvm.riscv.vlseg4ff.mask.nxv4f32.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 4 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 4 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 4 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 4 +// CHECK-RV64-NEXT: store i64 [[TMP5]], ptr [[NEW_VL]], align 4 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg4e32ff_v_f32m2_mu(vfloat32m2_t *v0, vfloat32m2_t *v1, vfloat32m2_t *v2, vfloat32m2_t *v3, vbool16_t mask, vfloat32m2_t maskedoff0, vfloat32m2_t maskedoff1, vfloat32m2_t maskedoff2, vfloat32m2_t maskedoff3, const float *base, size_t *new_vl, size_t vl) { + return __riscv_vlseg4e32ff_mu(v0, v1, v2, v3, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, base, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlseg4e32ff_v_i32mf2_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , i64 } @llvm.riscv.vlseg4ff.mask.nxv1i32.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 4 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 4 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 4 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 4 +// CHECK-RV64-NEXT: store i64 [[TMP5]], ptr [[NEW_VL]], align 4 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg4e32ff_v_i32mf2_mu(vint32mf2_t *v0, vint32mf2_t *v1, vint32mf2_t *v2, vint32mf2_t *v3, vbool64_t mask, vint32mf2_t maskedoff0, vint32mf2_t maskedoff1, vint32mf2_t maskedoff2, vint32mf2_t maskedoff3, const int32_t *base, size_t *new_vl, size_t vl) { + return __riscv_vlseg4e32ff_mu(v0, v1, v2, v3, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, base, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlseg4e32ff_v_i32m1_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , i64 } @llvm.riscv.vlseg4ff.mask.nxv2i32.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 4 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 4 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 4 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 4 +// CHECK-RV64-NEXT: store i64 [[TMP5]], ptr [[NEW_VL]], align 4 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg4e32ff_v_i32m1_mu(vint32m1_t *v0, vint32m1_t *v1, vint32m1_t *v2, vint32m1_t *v3, vbool32_t mask, vint32m1_t maskedoff0, vint32m1_t maskedoff1, vint32m1_t maskedoff2, vint32m1_t maskedoff3, const int32_t *base, size_t *new_vl, size_t vl) { + return __riscv_vlseg4e32ff_mu(v0, v1, v2, v3, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, base, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlseg4e32ff_v_i32m2_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , i64 } @llvm.riscv.vlseg4ff.mask.nxv4i32.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 4 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 4 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 4 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 4 +// CHECK-RV64-NEXT: store i64 [[TMP5]], ptr [[NEW_VL]], align 4 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg4e32ff_v_i32m2_mu(vint32m2_t *v0, vint32m2_t *v1, vint32m2_t *v2, vint32m2_t *v3, vbool16_t mask, vint32m2_t maskedoff0, vint32m2_t maskedoff1, vint32m2_t maskedoff2, vint32m2_t maskedoff3, const int32_t *base, size_t *new_vl, size_t vl) { + return __riscv_vlseg4e32ff_mu(v0, v1, v2, v3, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, base, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlseg4e32ff_v_u32mf2_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , i64 } @llvm.riscv.vlseg4ff.mask.nxv1i32.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 4 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 4 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 4 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 4 +// CHECK-RV64-NEXT: store i64 [[TMP5]], ptr [[NEW_VL]], align 4 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg4e32ff_v_u32mf2_mu(vuint32mf2_t *v0, vuint32mf2_t *v1, vuint32mf2_t *v2, vuint32mf2_t *v3, vbool64_t mask, vuint32mf2_t maskedoff0, vuint32mf2_t maskedoff1, vuint32mf2_t maskedoff2, vuint32mf2_t maskedoff3, const uint32_t *base, size_t *new_vl, size_t vl) { + return __riscv_vlseg4e32ff_mu(v0, v1, v2, v3, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, base, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlseg4e32ff_v_u32m1_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , i64 } @llvm.riscv.vlseg4ff.mask.nxv2i32.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 4 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 4 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 4 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 4 +// CHECK-RV64-NEXT: store i64 [[TMP5]], ptr [[NEW_VL]], align 4 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg4e32ff_v_u32m1_mu(vuint32m1_t *v0, vuint32m1_t *v1, vuint32m1_t *v2, vuint32m1_t *v3, vbool32_t mask, vuint32m1_t maskedoff0, vuint32m1_t maskedoff1, vuint32m1_t maskedoff2, vuint32m1_t maskedoff3, const uint32_t *base, size_t *new_vl, size_t vl) { + return __riscv_vlseg4e32ff_mu(v0, v1, v2, v3, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, base, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlseg4e32ff_v_u32m2_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , i64 } @llvm.riscv.vlseg4ff.mask.nxv4i32.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 4 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 4 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 4 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 4 +// CHECK-RV64-NEXT: store i64 [[TMP5]], ptr [[NEW_VL]], align 4 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg4e32ff_v_u32m2_mu(vuint32m2_t *v0, vuint32m2_t *v1, vuint32m2_t *v2, vuint32m2_t *v3, vbool16_t mask, vuint32m2_t maskedoff0, vuint32m2_t maskedoff1, vuint32m2_t maskedoff2, vuint32m2_t maskedoff3, const uint32_t *base, size_t *new_vl, size_t vl) { + return __riscv_vlseg4e32ff_mu(v0, v1, v2, v3, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, base, new_vl, vl); +} + diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e64.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e64.c index 364bdaab7d631..2b01c6d687e0a 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e64.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e64.c @@ -331,3 +331,111 @@ void test_vlseg4e64_v_u64m2_tumu(vuint64m2_t *v0, vuint64m2_t *v1, vuint64m2_t * return __riscv_vlseg4e64_tumu(v0, v1, v2, v3, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, base, vl); } +// CHECK-RV64-LABEL: define dso_local void @test_vlseg4e64_v_f64m1_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vlseg4.mask.nxv1f64.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 8 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 8 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 8 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 8 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg4e64_v_f64m1_mu(vfloat64m1_t *v0, vfloat64m1_t *v1, vfloat64m1_t *v2, vfloat64m1_t *v3, vbool64_t mask, vfloat64m1_t maskedoff0, vfloat64m1_t maskedoff1, vfloat64m1_t maskedoff2, vfloat64m1_t maskedoff3, const double *base, size_t vl) { + return __riscv_vlseg4e64_mu(v0, v1, v2, v3, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, base, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlseg4e64_v_f64m2_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vlseg4.mask.nxv2f64.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 8 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 8 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 8 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 8 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg4e64_v_f64m2_mu(vfloat64m2_t *v0, vfloat64m2_t *v1, vfloat64m2_t *v2, vfloat64m2_t *v3, vbool32_t mask, vfloat64m2_t maskedoff0, vfloat64m2_t maskedoff1, vfloat64m2_t maskedoff2, vfloat64m2_t maskedoff3, const double *base, size_t vl) { + return __riscv_vlseg4e64_mu(v0, v1, v2, v3, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, base, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlseg4e64_v_i64m1_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vlseg4.mask.nxv1i64.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 8 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 8 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 8 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 8 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg4e64_v_i64m1_mu(vint64m1_t *v0, vint64m1_t *v1, vint64m1_t *v2, vint64m1_t *v3, vbool64_t mask, vint64m1_t maskedoff0, vint64m1_t maskedoff1, vint64m1_t maskedoff2, vint64m1_t maskedoff3, const int64_t *base, size_t vl) { + return __riscv_vlseg4e64_mu(v0, v1, v2, v3, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, base, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlseg4e64_v_i64m2_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vlseg4.mask.nxv2i64.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 8 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 8 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 8 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 8 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg4e64_v_i64m2_mu(vint64m2_t *v0, vint64m2_t *v1, vint64m2_t *v2, vint64m2_t *v3, vbool32_t mask, vint64m2_t maskedoff0, vint64m2_t maskedoff1, vint64m2_t maskedoff2, vint64m2_t maskedoff3, const int64_t *base, size_t vl) { + return __riscv_vlseg4e64_mu(v0, v1, v2, v3, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, base, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlseg4e64_v_u64m1_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vlseg4.mask.nxv1i64.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 8 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 8 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 8 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 8 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg4e64_v_u64m1_mu(vuint64m1_t *v0, vuint64m1_t *v1, vuint64m1_t *v2, vuint64m1_t *v3, vbool64_t mask, vuint64m1_t maskedoff0, vuint64m1_t maskedoff1, vuint64m1_t maskedoff2, vuint64m1_t maskedoff3, const uint64_t *base, size_t vl) { + return __riscv_vlseg4e64_mu(v0, v1, v2, v3, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, base, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlseg4e64_v_u64m2_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vlseg4.mask.nxv2i64.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 8 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 8 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 8 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 8 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg4e64_v_u64m2_mu(vuint64m2_t *v0, vuint64m2_t *v1, vuint64m2_t *v2, vuint64m2_t *v3, vbool32_t mask, vuint64m2_t maskedoff0, vuint64m2_t maskedoff1, vuint64m2_t maskedoff2, vuint64m2_t maskedoff3, const uint64_t *base, size_t vl) { + return __riscv_vlseg4e64_mu(v0, v1, v2, v3, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, base, vl); +} + diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e64ff.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e64ff.c index 5a380569b7893..f7ebf55a05df4 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e64ff.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e64ff.c @@ -367,3 +367,123 @@ void test_vlseg4e64ff_v_u64m2_tumu(vuint64m2_t *v0, vuint64m2_t *v1, vuint64m2_t return __riscv_vlseg4e64ff_tumu(v0, v1, v2, v3, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, base, new_vl, vl); } +// CHECK-RV64-LABEL: define dso_local void @test_vlseg4e64ff_v_f64m1_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , i64 } @llvm.riscv.vlseg4ff.mask.nxv1f64.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 8 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 8 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 8 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 8 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 4 +// CHECK-RV64-NEXT: store i64 [[TMP5]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg4e64ff_v_f64m1_mu(vfloat64m1_t *v0, vfloat64m1_t *v1, vfloat64m1_t *v2, vfloat64m1_t *v3, vbool64_t mask, vfloat64m1_t maskedoff0, vfloat64m1_t maskedoff1, vfloat64m1_t maskedoff2, vfloat64m1_t maskedoff3, const double *base, size_t *new_vl, size_t vl) { + return __riscv_vlseg4e64ff_mu(v0, v1, v2, v3, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, base, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlseg4e64ff_v_f64m2_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , i64 } @llvm.riscv.vlseg4ff.mask.nxv2f64.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 8 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 8 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 8 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 8 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 4 +// CHECK-RV64-NEXT: store i64 [[TMP5]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg4e64ff_v_f64m2_mu(vfloat64m2_t *v0, vfloat64m2_t *v1, vfloat64m2_t *v2, vfloat64m2_t *v3, vbool32_t mask, vfloat64m2_t maskedoff0, vfloat64m2_t maskedoff1, vfloat64m2_t maskedoff2, vfloat64m2_t maskedoff3, const double *base, size_t *new_vl, size_t vl) { + return __riscv_vlseg4e64ff_mu(v0, v1, v2, v3, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, base, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlseg4e64ff_v_i64m1_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , i64 } @llvm.riscv.vlseg4ff.mask.nxv1i64.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 8 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 8 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 8 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 8 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 4 +// CHECK-RV64-NEXT: store i64 [[TMP5]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg4e64ff_v_i64m1_mu(vint64m1_t *v0, vint64m1_t *v1, vint64m1_t *v2, vint64m1_t *v3, vbool64_t mask, vint64m1_t maskedoff0, vint64m1_t maskedoff1, vint64m1_t maskedoff2, vint64m1_t maskedoff3, const int64_t *base, size_t *new_vl, size_t vl) { + return __riscv_vlseg4e64ff_mu(v0, v1, v2, v3, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, base, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlseg4e64ff_v_i64m2_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , i64 } @llvm.riscv.vlseg4ff.mask.nxv2i64.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 8 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 8 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 8 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 8 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 4 +// CHECK-RV64-NEXT: store i64 [[TMP5]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg4e64ff_v_i64m2_mu(vint64m2_t *v0, vint64m2_t *v1, vint64m2_t *v2, vint64m2_t *v3, vbool32_t mask, vint64m2_t maskedoff0, vint64m2_t maskedoff1, vint64m2_t maskedoff2, vint64m2_t maskedoff3, const int64_t *base, size_t *new_vl, size_t vl) { + return __riscv_vlseg4e64ff_mu(v0, v1, v2, v3, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, base, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlseg4e64ff_v_u64m1_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , i64 } @llvm.riscv.vlseg4ff.mask.nxv1i64.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 8 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 8 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 8 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 8 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 4 +// CHECK-RV64-NEXT: store i64 [[TMP5]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg4e64ff_v_u64m1_mu(vuint64m1_t *v0, vuint64m1_t *v1, vuint64m1_t *v2, vuint64m1_t *v3, vbool64_t mask, vuint64m1_t maskedoff0, vuint64m1_t maskedoff1, vuint64m1_t maskedoff2, vuint64m1_t maskedoff3, const uint64_t *base, size_t *new_vl, size_t vl) { + return __riscv_vlseg4e64ff_mu(v0, v1, v2, v3, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, base, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlseg4e64ff_v_u64m2_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , i64 } @llvm.riscv.vlseg4ff.mask.nxv2i64.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 8 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 8 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 8 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 8 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 4 +// CHECK-RV64-NEXT: store i64 [[TMP5]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg4e64ff_v_u64m2_mu(vuint64m2_t *v0, vuint64m2_t *v1, vuint64m2_t *v2, vuint64m2_t *v3, vbool32_t mask, vuint64m2_t maskedoff0, vuint64m2_t maskedoff1, vuint64m2_t maskedoff2, vuint64m2_t maskedoff3, const uint64_t *base, size_t *new_vl, size_t vl) { + return __riscv_vlseg4e64ff_mu(v0, v1, v2, v3, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, base, new_vl, vl); +} + diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e8.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e8.c index f14fa57bda5bf..8d9f1f21bf511 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e8.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e8.c @@ -546,3 +546,183 @@ void test_vlseg4e8_v_u8m2_tumu(vuint8m2_t *v0, vuint8m2_t *v1, vuint8m2_t *v2, v return __riscv_vlseg4e8_tumu(v0, v1, v2, v3, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, base, vl); } +// CHECK-RV64-LABEL: define dso_local void @test_vlseg4e8_v_i8mf8_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vlseg4.mask.nxv1i8.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 1 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 1 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 1 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg4e8_v_i8mf8_mu(vint8mf8_t *v0, vint8mf8_t *v1, vint8mf8_t *v2, vint8mf8_t *v3, vbool64_t mask, vint8mf8_t maskedoff0, vint8mf8_t maskedoff1, vint8mf8_t maskedoff2, vint8mf8_t maskedoff3, const int8_t *base, size_t vl) { + return __riscv_vlseg4e8_mu(v0, v1, v2, v3, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, base, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlseg4e8_v_i8mf4_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vlseg4.mask.nxv2i8.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 1 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 1 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 1 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg4e8_v_i8mf4_mu(vint8mf4_t *v0, vint8mf4_t *v1, vint8mf4_t *v2, vint8mf4_t *v3, vbool32_t mask, vint8mf4_t maskedoff0, vint8mf4_t maskedoff1, vint8mf4_t maskedoff2, vint8mf4_t maskedoff3, const int8_t *base, size_t vl) { + return __riscv_vlseg4e8_mu(v0, v1, v2, v3, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, base, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlseg4e8_v_i8mf2_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vlseg4.mask.nxv4i8.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 1 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 1 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 1 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg4e8_v_i8mf2_mu(vint8mf2_t *v0, vint8mf2_t *v1, vint8mf2_t *v2, vint8mf2_t *v3, vbool16_t mask, vint8mf2_t maskedoff0, vint8mf2_t maskedoff1, vint8mf2_t maskedoff2, vint8mf2_t maskedoff3, const int8_t *base, size_t vl) { + return __riscv_vlseg4e8_mu(v0, v1, v2, v3, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, base, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlseg4e8_v_i8m1_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vlseg4.mask.nxv8i8.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 1 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 1 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 1 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg4e8_v_i8m1_mu(vint8m1_t *v0, vint8m1_t *v1, vint8m1_t *v2, vint8m1_t *v3, vbool8_t mask, vint8m1_t maskedoff0, vint8m1_t maskedoff1, vint8m1_t maskedoff2, vint8m1_t maskedoff3, const int8_t *base, size_t vl) { + return __riscv_vlseg4e8_mu(v0, v1, v2, v3, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, base, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlseg4e8_v_i8m2_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vlseg4.mask.nxv16i8.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 1 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 1 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 1 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg4e8_v_i8m2_mu(vint8m2_t *v0, vint8m2_t *v1, vint8m2_t *v2, vint8m2_t *v3, vbool4_t mask, vint8m2_t maskedoff0, vint8m2_t maskedoff1, vint8m2_t maskedoff2, vint8m2_t maskedoff3, const int8_t *base, size_t vl) { + return __riscv_vlseg4e8_mu(v0, v1, v2, v3, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, base, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlseg4e8_v_u8mf8_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vlseg4.mask.nxv1i8.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 1 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 1 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 1 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg4e8_v_u8mf8_mu(vuint8mf8_t *v0, vuint8mf8_t *v1, vuint8mf8_t *v2, vuint8mf8_t *v3, vbool64_t mask, vuint8mf8_t maskedoff0, vuint8mf8_t maskedoff1, vuint8mf8_t maskedoff2, vuint8mf8_t maskedoff3, const uint8_t *base, size_t vl) { + return __riscv_vlseg4e8_mu(v0, v1, v2, v3, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, base, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlseg4e8_v_u8mf4_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vlseg4.mask.nxv2i8.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 1 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 1 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 1 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg4e8_v_u8mf4_mu(vuint8mf4_t *v0, vuint8mf4_t *v1, vuint8mf4_t *v2, vuint8mf4_t *v3, vbool32_t mask, vuint8mf4_t maskedoff0, vuint8mf4_t maskedoff1, vuint8mf4_t maskedoff2, vuint8mf4_t maskedoff3, const uint8_t *base, size_t vl) { + return __riscv_vlseg4e8_mu(v0, v1, v2, v3, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, base, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlseg4e8_v_u8mf2_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vlseg4.mask.nxv4i8.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 1 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 1 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 1 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg4e8_v_u8mf2_mu(vuint8mf2_t *v0, vuint8mf2_t *v1, vuint8mf2_t *v2, vuint8mf2_t *v3, vbool16_t mask, vuint8mf2_t maskedoff0, vuint8mf2_t maskedoff1, vuint8mf2_t maskedoff2, vuint8mf2_t maskedoff3, const uint8_t *base, size_t vl) { + return __riscv_vlseg4e8_mu(v0, v1, v2, v3, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, base, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlseg4e8_v_u8m1_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vlseg4.mask.nxv8i8.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 1 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 1 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 1 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg4e8_v_u8m1_mu(vuint8m1_t *v0, vuint8m1_t *v1, vuint8m1_t *v2, vuint8m1_t *v3, vbool8_t mask, vuint8m1_t maskedoff0, vuint8m1_t maskedoff1, vuint8m1_t maskedoff2, vuint8m1_t maskedoff3, const uint8_t *base, size_t vl) { + return __riscv_vlseg4e8_mu(v0, v1, v2, v3, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, base, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlseg4e8_v_u8m2_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vlseg4.mask.nxv16i8.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 1 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 1 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 1 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg4e8_v_u8m2_mu(vuint8m2_t *v0, vuint8m2_t *v1, vuint8m2_t *v2, vuint8m2_t *v3, vbool4_t mask, vuint8m2_t maskedoff0, vuint8m2_t maskedoff1, vuint8m2_t maskedoff2, vuint8m2_t maskedoff3, const uint8_t *base, size_t vl) { + return __riscv_vlseg4e8_mu(v0, v1, v2, v3, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, base, vl); +} + diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e8ff.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e8ff.c index 07b05351cb8ce..d5763fff2c5a8 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e8ff.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e8ff.c @@ -607,3 +607,203 @@ void test_vlseg4e8ff_v_u8m2_tumu(vuint8m2_t *v0, vuint8m2_t *v1, vuint8m2_t *v2, return __riscv_vlseg4e8ff_tumu(v0, v1, v2, v3, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, base, new_vl, vl); } +// CHECK-RV64-LABEL: define dso_local void @test_vlseg4e8ff_v_i8mf8_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , i64 } @llvm.riscv.vlseg4ff.mask.nxv1i8.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 1 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 1 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 1 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 4 +// CHECK-RV64-NEXT: store i64 [[TMP5]], ptr [[NEW_VL]], align 1 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg4e8ff_v_i8mf8_mu(vint8mf8_t *v0, vint8mf8_t *v1, vint8mf8_t *v2, vint8mf8_t *v3, vbool64_t mask, vint8mf8_t maskedoff0, vint8mf8_t maskedoff1, vint8mf8_t maskedoff2, vint8mf8_t maskedoff3, const int8_t *base, size_t *new_vl, size_t vl) { + return __riscv_vlseg4e8ff_mu(v0, v1, v2, v3, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, base, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlseg4e8ff_v_i8mf4_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , i64 } @llvm.riscv.vlseg4ff.mask.nxv2i8.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 1 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 1 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 1 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 4 +// CHECK-RV64-NEXT: store i64 [[TMP5]], ptr [[NEW_VL]], align 1 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg4e8ff_v_i8mf4_mu(vint8mf4_t *v0, vint8mf4_t *v1, vint8mf4_t *v2, vint8mf4_t *v3, vbool32_t mask, vint8mf4_t maskedoff0, vint8mf4_t maskedoff1, vint8mf4_t maskedoff2, vint8mf4_t maskedoff3, const int8_t *base, size_t *new_vl, size_t vl) { + return __riscv_vlseg4e8ff_mu(v0, v1, v2, v3, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, base, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlseg4e8ff_v_i8mf2_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , i64 } @llvm.riscv.vlseg4ff.mask.nxv4i8.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 1 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 1 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 1 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 4 +// CHECK-RV64-NEXT: store i64 [[TMP5]], ptr [[NEW_VL]], align 1 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg4e8ff_v_i8mf2_mu(vint8mf2_t *v0, vint8mf2_t *v1, vint8mf2_t *v2, vint8mf2_t *v3, vbool16_t mask, vint8mf2_t maskedoff0, vint8mf2_t maskedoff1, vint8mf2_t maskedoff2, vint8mf2_t maskedoff3, const int8_t *base, size_t *new_vl, size_t vl) { + return __riscv_vlseg4e8ff_mu(v0, v1, v2, v3, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, base, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlseg4e8ff_v_i8m1_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , i64 } @llvm.riscv.vlseg4ff.mask.nxv8i8.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 1 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 1 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 1 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 4 +// CHECK-RV64-NEXT: store i64 [[TMP5]], ptr [[NEW_VL]], align 1 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg4e8ff_v_i8m1_mu(vint8m1_t *v0, vint8m1_t *v1, vint8m1_t *v2, vint8m1_t *v3, vbool8_t mask, vint8m1_t maskedoff0, vint8m1_t maskedoff1, vint8m1_t maskedoff2, vint8m1_t maskedoff3, const int8_t *base, size_t *new_vl, size_t vl) { + return __riscv_vlseg4e8ff_mu(v0, v1, v2, v3, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, base, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlseg4e8ff_v_i8m2_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , i64 } @llvm.riscv.vlseg4ff.mask.nxv16i8.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 1 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 1 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 1 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 4 +// CHECK-RV64-NEXT: store i64 [[TMP5]], ptr [[NEW_VL]], align 1 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg4e8ff_v_i8m2_mu(vint8m2_t *v0, vint8m2_t *v1, vint8m2_t *v2, vint8m2_t *v3, vbool4_t mask, vint8m2_t maskedoff0, vint8m2_t maskedoff1, vint8m2_t maskedoff2, vint8m2_t maskedoff3, const int8_t *base, size_t *new_vl, size_t vl) { + return __riscv_vlseg4e8ff_mu(v0, v1, v2, v3, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, base, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlseg4e8ff_v_u8mf8_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , i64 } @llvm.riscv.vlseg4ff.mask.nxv1i8.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 1 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 1 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 1 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 4 +// CHECK-RV64-NEXT: store i64 [[TMP5]], ptr [[NEW_VL]], align 1 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg4e8ff_v_u8mf8_mu(vuint8mf8_t *v0, vuint8mf8_t *v1, vuint8mf8_t *v2, vuint8mf8_t *v3, vbool64_t mask, vuint8mf8_t maskedoff0, vuint8mf8_t maskedoff1, vuint8mf8_t maskedoff2, vuint8mf8_t maskedoff3, const uint8_t *base, size_t *new_vl, size_t vl) { + return __riscv_vlseg4e8ff_mu(v0, v1, v2, v3, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, base, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlseg4e8ff_v_u8mf4_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , i64 } @llvm.riscv.vlseg4ff.mask.nxv2i8.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 1 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 1 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 1 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 4 +// CHECK-RV64-NEXT: store i64 [[TMP5]], ptr [[NEW_VL]], align 1 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg4e8ff_v_u8mf4_mu(vuint8mf4_t *v0, vuint8mf4_t *v1, vuint8mf4_t *v2, vuint8mf4_t *v3, vbool32_t mask, vuint8mf4_t maskedoff0, vuint8mf4_t maskedoff1, vuint8mf4_t maskedoff2, vuint8mf4_t maskedoff3, const uint8_t *base, size_t *new_vl, size_t vl) { + return __riscv_vlseg4e8ff_mu(v0, v1, v2, v3, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, base, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlseg4e8ff_v_u8mf2_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , i64 } @llvm.riscv.vlseg4ff.mask.nxv4i8.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 1 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 1 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 1 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 4 +// CHECK-RV64-NEXT: store i64 [[TMP5]], ptr [[NEW_VL]], align 1 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg4e8ff_v_u8mf2_mu(vuint8mf2_t *v0, vuint8mf2_t *v1, vuint8mf2_t *v2, vuint8mf2_t *v3, vbool16_t mask, vuint8mf2_t maskedoff0, vuint8mf2_t maskedoff1, vuint8mf2_t maskedoff2, vuint8mf2_t maskedoff3, const uint8_t *base, size_t *new_vl, size_t vl) { + return __riscv_vlseg4e8ff_mu(v0, v1, v2, v3, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, base, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlseg4e8ff_v_u8m1_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , i64 } @llvm.riscv.vlseg4ff.mask.nxv8i8.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 1 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 1 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 1 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 4 +// CHECK-RV64-NEXT: store i64 [[TMP5]], ptr [[NEW_VL]], align 1 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg4e8ff_v_u8m1_mu(vuint8m1_t *v0, vuint8m1_t *v1, vuint8m1_t *v2, vuint8m1_t *v3, vbool8_t mask, vuint8m1_t maskedoff0, vuint8m1_t maskedoff1, vuint8m1_t maskedoff2, vuint8m1_t maskedoff3, const uint8_t *base, size_t *new_vl, size_t vl) { + return __riscv_vlseg4e8ff_mu(v0, v1, v2, v3, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, base, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlseg4e8ff_v_u8m2_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , i64 } @llvm.riscv.vlseg4ff.mask.nxv16i8.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 1 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 1 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 1 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 4 +// CHECK-RV64-NEXT: store i64 [[TMP5]], ptr [[NEW_VL]], align 1 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg4e8ff_v_u8m2_mu(vuint8m2_t *v0, vuint8m2_t *v1, vuint8m2_t *v2, vuint8m2_t *v3, vbool4_t mask, vuint8m2_t maskedoff0, vuint8m2_t maskedoff1, vuint8m2_t maskedoff2, vuint8m2_t maskedoff3, const uint8_t *base, size_t *new_vl, size_t vl) { + return __riscv_vlseg4e8ff_mu(v0, v1, v2, v3, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, base, new_vl, vl); +} + diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e16.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e16.c index a72e987f0c50b..38e8a39a36bc6 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e16.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e16.c @@ -547,3 +547,183 @@ void test_vlseg5e16_v_u16m1_tumu(vuint16m1_t *v0, vuint16m1_t *v1, vuint16m1_t * return __riscv_vlseg5e16_tumu(v0, v1, v2, v3, v4, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, maskedoff4, base, vl); } +// CHECK-RV64-LABEL: define dso_local void @test_vlseg5e16_v_f16mf4_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], ptr noundef [[V4:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], [[MASKEDOFF4:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vlseg5.mask.nxv1f16.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], [[MASKEDOFF4]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 2 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 2 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 2 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , } [[TMP0]], 4 +// CHECK-RV64-NEXT: store [[TMP5]], ptr [[V4]], align 2 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg5e16_v_f16mf4_mu(vfloat16mf4_t *v0, vfloat16mf4_t *v1, vfloat16mf4_t *v2, vfloat16mf4_t *v3, vfloat16mf4_t *v4, vbool64_t mask, vfloat16mf4_t maskedoff0, vfloat16mf4_t maskedoff1, vfloat16mf4_t maskedoff2, vfloat16mf4_t maskedoff3, vfloat16mf4_t maskedoff4, const _Float16 *base, size_t vl) { + return __riscv_vlseg5e16_mu(v0, v1, v2, v3, v4, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, maskedoff4, base, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlseg5e16_v_f16mf2_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], ptr noundef [[V4:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], [[MASKEDOFF4:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vlseg5.mask.nxv2f16.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], [[MASKEDOFF4]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 2 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 2 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 2 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , } [[TMP0]], 4 +// CHECK-RV64-NEXT: store [[TMP5]], ptr [[V4]], align 2 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg5e16_v_f16mf2_mu(vfloat16mf2_t *v0, vfloat16mf2_t *v1, vfloat16mf2_t *v2, vfloat16mf2_t *v3, vfloat16mf2_t *v4, vbool32_t mask, vfloat16mf2_t maskedoff0, vfloat16mf2_t maskedoff1, vfloat16mf2_t maskedoff2, vfloat16mf2_t maskedoff3, vfloat16mf2_t maskedoff4, const _Float16 *base, size_t vl) { + return __riscv_vlseg5e16_mu(v0, v1, v2, v3, v4, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, maskedoff4, base, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlseg5e16_v_f16m1_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], ptr noundef [[V4:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], [[MASKEDOFF4:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vlseg5.mask.nxv4f16.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], [[MASKEDOFF4]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 2 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 2 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 2 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , } [[TMP0]], 4 +// CHECK-RV64-NEXT: store [[TMP5]], ptr [[V4]], align 2 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg5e16_v_f16m1_mu(vfloat16m1_t *v0, vfloat16m1_t *v1, vfloat16m1_t *v2, vfloat16m1_t *v3, vfloat16m1_t *v4, vbool16_t mask, vfloat16m1_t maskedoff0, vfloat16m1_t maskedoff1, vfloat16m1_t maskedoff2, vfloat16m1_t maskedoff3, vfloat16m1_t maskedoff4, const _Float16 *base, size_t vl) { + return __riscv_vlseg5e16_mu(v0, v1, v2, v3, v4, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, maskedoff4, base, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlseg5e16_v_i16mf4_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], ptr noundef [[V4:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], [[MASKEDOFF4:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vlseg5.mask.nxv1i16.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], [[MASKEDOFF4]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 2 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 2 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 2 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , } [[TMP0]], 4 +// CHECK-RV64-NEXT: store [[TMP5]], ptr [[V4]], align 2 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg5e16_v_i16mf4_mu(vint16mf4_t *v0, vint16mf4_t *v1, vint16mf4_t *v2, vint16mf4_t *v3, vint16mf4_t *v4, vbool64_t mask, vint16mf4_t maskedoff0, vint16mf4_t maskedoff1, vint16mf4_t maskedoff2, vint16mf4_t maskedoff3, vint16mf4_t maskedoff4, const int16_t *base, size_t vl) { + return __riscv_vlseg5e16_mu(v0, v1, v2, v3, v4, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, maskedoff4, base, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlseg5e16_v_i16mf2_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], ptr noundef [[V4:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], [[MASKEDOFF4:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vlseg5.mask.nxv2i16.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], [[MASKEDOFF4]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 2 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 2 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 2 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , } [[TMP0]], 4 +// CHECK-RV64-NEXT: store [[TMP5]], ptr [[V4]], align 2 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg5e16_v_i16mf2_mu(vint16mf2_t *v0, vint16mf2_t *v1, vint16mf2_t *v2, vint16mf2_t *v3, vint16mf2_t *v4, vbool32_t mask, vint16mf2_t maskedoff0, vint16mf2_t maskedoff1, vint16mf2_t maskedoff2, vint16mf2_t maskedoff3, vint16mf2_t maskedoff4, const int16_t *base, size_t vl) { + return __riscv_vlseg5e16_mu(v0, v1, v2, v3, v4, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, maskedoff4, base, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlseg5e16_v_i16m1_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], ptr noundef [[V4:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], [[MASKEDOFF4:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vlseg5.mask.nxv4i16.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], [[MASKEDOFF4]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 2 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 2 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 2 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , } [[TMP0]], 4 +// CHECK-RV64-NEXT: store [[TMP5]], ptr [[V4]], align 2 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg5e16_v_i16m1_mu(vint16m1_t *v0, vint16m1_t *v1, vint16m1_t *v2, vint16m1_t *v3, vint16m1_t *v4, vbool16_t mask, vint16m1_t maskedoff0, vint16m1_t maskedoff1, vint16m1_t maskedoff2, vint16m1_t maskedoff3, vint16m1_t maskedoff4, const int16_t *base, size_t vl) { + return __riscv_vlseg5e16_mu(v0, v1, v2, v3, v4, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, maskedoff4, base, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlseg5e16_v_u16mf4_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], ptr noundef [[V4:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], [[MASKEDOFF4:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vlseg5.mask.nxv1i16.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], [[MASKEDOFF4]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 2 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 2 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 2 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , } [[TMP0]], 4 +// CHECK-RV64-NEXT: store [[TMP5]], ptr [[V4]], align 2 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg5e16_v_u16mf4_mu(vuint16mf4_t *v0, vuint16mf4_t *v1, vuint16mf4_t *v2, vuint16mf4_t *v3, vuint16mf4_t *v4, vbool64_t mask, vuint16mf4_t maskedoff0, vuint16mf4_t maskedoff1, vuint16mf4_t maskedoff2, vuint16mf4_t maskedoff3, vuint16mf4_t maskedoff4, const uint16_t *base, size_t vl) { + return __riscv_vlseg5e16_mu(v0, v1, v2, v3, v4, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, maskedoff4, base, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlseg5e16_v_u16mf2_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], ptr noundef [[V4:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], [[MASKEDOFF4:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vlseg5.mask.nxv2i16.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], [[MASKEDOFF4]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 2 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 2 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 2 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , } [[TMP0]], 4 +// CHECK-RV64-NEXT: store [[TMP5]], ptr [[V4]], align 2 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg5e16_v_u16mf2_mu(vuint16mf2_t *v0, vuint16mf2_t *v1, vuint16mf2_t *v2, vuint16mf2_t *v3, vuint16mf2_t *v4, vbool32_t mask, vuint16mf2_t maskedoff0, vuint16mf2_t maskedoff1, vuint16mf2_t maskedoff2, vuint16mf2_t maskedoff3, vuint16mf2_t maskedoff4, const uint16_t *base, size_t vl) { + return __riscv_vlseg5e16_mu(v0, v1, v2, v3, v4, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, maskedoff4, base, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlseg5e16_v_u16m1_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], ptr noundef [[V4:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], [[MASKEDOFF4:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vlseg5.mask.nxv4i16.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], [[MASKEDOFF4]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 2 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 2 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 2 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , } [[TMP0]], 4 +// CHECK-RV64-NEXT: store [[TMP5]], ptr [[V4]], align 2 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg5e16_v_u16m1_mu(vuint16m1_t *v0, vuint16m1_t *v1, vuint16m1_t *v2, vuint16m1_t *v3, vuint16m1_t *v4, vbool16_t mask, vuint16m1_t maskedoff0, vuint16m1_t maskedoff1, vuint16m1_t maskedoff2, vuint16m1_t maskedoff3, vuint16m1_t maskedoff4, const uint16_t *base, size_t vl) { + return __riscv_vlseg5e16_mu(v0, v1, v2, v3, v4, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, maskedoff4, base, vl); +} + diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e16ff.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e16ff.c index 76e5a9dbc1fd5..aed9e2db86a54 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e16ff.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e16ff.c @@ -601,3 +601,201 @@ void test_vlseg5e16ff_v_u16m1_tumu(vuint16m1_t *v0, vuint16m1_t *v1, vuint16m1_t return __riscv_vlseg5e16ff_tumu(v0, v1, v2, v3, v4, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, maskedoff4, base, new_vl, vl); } +// CHECK-RV64-LABEL: define dso_local void @test_vlseg5e16ff_v_f16mf4_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], ptr noundef [[V4:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], [[MASKEDOFF4:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , i64 } @llvm.riscv.vlseg5ff.mask.nxv1f16.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], [[MASKEDOFF4]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 2 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 2 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , i64 } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 2 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , i64 } [[TMP0]], 4 +// CHECK-RV64-NEXT: store [[TMP5]], ptr [[V4]], align 2 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , i64 } [[TMP0]], 5 +// CHECK-RV64-NEXT: store i64 [[TMP6]], ptr [[NEW_VL]], align 2 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg5e16ff_v_f16mf4_mu(vfloat16mf4_t *v0, vfloat16mf4_t *v1, vfloat16mf4_t *v2, vfloat16mf4_t *v3, vfloat16mf4_t *v4, vbool64_t mask, vfloat16mf4_t maskedoff0, vfloat16mf4_t maskedoff1, vfloat16mf4_t maskedoff2, vfloat16mf4_t maskedoff3, vfloat16mf4_t maskedoff4, const _Float16 *base, size_t *new_vl, size_t vl) { + return __riscv_vlseg5e16ff_mu(v0, v1, v2, v3, v4, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, maskedoff4, base, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlseg5e16ff_v_f16mf2_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], ptr noundef [[V4:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], [[MASKEDOFF4:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , i64 } @llvm.riscv.vlseg5ff.mask.nxv2f16.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], [[MASKEDOFF4]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 2 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 2 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , i64 } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 2 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , i64 } [[TMP0]], 4 +// CHECK-RV64-NEXT: store [[TMP5]], ptr [[V4]], align 2 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , i64 } [[TMP0]], 5 +// CHECK-RV64-NEXT: store i64 [[TMP6]], ptr [[NEW_VL]], align 2 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg5e16ff_v_f16mf2_mu(vfloat16mf2_t *v0, vfloat16mf2_t *v1, vfloat16mf2_t *v2, vfloat16mf2_t *v3, vfloat16mf2_t *v4, vbool32_t mask, vfloat16mf2_t maskedoff0, vfloat16mf2_t maskedoff1, vfloat16mf2_t maskedoff2, vfloat16mf2_t maskedoff3, vfloat16mf2_t maskedoff4, const _Float16 *base, size_t *new_vl, size_t vl) { + return __riscv_vlseg5e16ff_mu(v0, v1, v2, v3, v4, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, maskedoff4, base, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlseg5e16ff_v_f16m1_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], ptr noundef [[V4:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], [[MASKEDOFF4:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , i64 } @llvm.riscv.vlseg5ff.mask.nxv4f16.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], [[MASKEDOFF4]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 2 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 2 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , i64 } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 2 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , i64 } [[TMP0]], 4 +// CHECK-RV64-NEXT: store [[TMP5]], ptr [[V4]], align 2 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , i64 } [[TMP0]], 5 +// CHECK-RV64-NEXT: store i64 [[TMP6]], ptr [[NEW_VL]], align 2 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg5e16ff_v_f16m1_mu(vfloat16m1_t *v0, vfloat16m1_t *v1, vfloat16m1_t *v2, vfloat16m1_t *v3, vfloat16m1_t *v4, vbool16_t mask, vfloat16m1_t maskedoff0, vfloat16m1_t maskedoff1, vfloat16m1_t maskedoff2, vfloat16m1_t maskedoff3, vfloat16m1_t maskedoff4, const _Float16 *base, size_t *new_vl, size_t vl) { + return __riscv_vlseg5e16ff_mu(v0, v1, v2, v3, v4, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, maskedoff4, base, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlseg5e16ff_v_i16mf4_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], ptr noundef [[V4:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], [[MASKEDOFF4:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , i64 } @llvm.riscv.vlseg5ff.mask.nxv1i16.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], [[MASKEDOFF4]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 2 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 2 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , i64 } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 2 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , i64 } [[TMP0]], 4 +// CHECK-RV64-NEXT: store [[TMP5]], ptr [[V4]], align 2 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , i64 } [[TMP0]], 5 +// CHECK-RV64-NEXT: store i64 [[TMP6]], ptr [[NEW_VL]], align 2 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg5e16ff_v_i16mf4_mu(vint16mf4_t *v0, vint16mf4_t *v1, vint16mf4_t *v2, vint16mf4_t *v3, vint16mf4_t *v4, vbool64_t mask, vint16mf4_t maskedoff0, vint16mf4_t maskedoff1, vint16mf4_t maskedoff2, vint16mf4_t maskedoff3, vint16mf4_t maskedoff4, const int16_t *base, size_t *new_vl, size_t vl) { + return __riscv_vlseg5e16ff_mu(v0, v1, v2, v3, v4, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, maskedoff4, base, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlseg5e16ff_v_i16mf2_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], ptr noundef [[V4:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], [[MASKEDOFF4:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , i64 } @llvm.riscv.vlseg5ff.mask.nxv2i16.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], [[MASKEDOFF4]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 2 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 2 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , i64 } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 2 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , i64 } [[TMP0]], 4 +// CHECK-RV64-NEXT: store [[TMP5]], ptr [[V4]], align 2 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , i64 } [[TMP0]], 5 +// CHECK-RV64-NEXT: store i64 [[TMP6]], ptr [[NEW_VL]], align 2 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg5e16ff_v_i16mf2_mu(vint16mf2_t *v0, vint16mf2_t *v1, vint16mf2_t *v2, vint16mf2_t *v3, vint16mf2_t *v4, vbool32_t mask, vint16mf2_t maskedoff0, vint16mf2_t maskedoff1, vint16mf2_t maskedoff2, vint16mf2_t maskedoff3, vint16mf2_t maskedoff4, const int16_t *base, size_t *new_vl, size_t vl) { + return __riscv_vlseg5e16ff_mu(v0, v1, v2, v3, v4, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, maskedoff4, base, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlseg5e16ff_v_i16m1_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], ptr noundef [[V4:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], [[MASKEDOFF4:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , i64 } @llvm.riscv.vlseg5ff.mask.nxv4i16.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], [[MASKEDOFF4]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 2 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 2 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , i64 } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 2 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , i64 } [[TMP0]], 4 +// CHECK-RV64-NEXT: store [[TMP5]], ptr [[V4]], align 2 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , i64 } [[TMP0]], 5 +// CHECK-RV64-NEXT: store i64 [[TMP6]], ptr [[NEW_VL]], align 2 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg5e16ff_v_i16m1_mu(vint16m1_t *v0, vint16m1_t *v1, vint16m1_t *v2, vint16m1_t *v3, vint16m1_t *v4, vbool16_t mask, vint16m1_t maskedoff0, vint16m1_t maskedoff1, vint16m1_t maskedoff2, vint16m1_t maskedoff3, vint16m1_t maskedoff4, const int16_t *base, size_t *new_vl, size_t vl) { + return __riscv_vlseg5e16ff_mu(v0, v1, v2, v3, v4, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, maskedoff4, base, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlseg5e16ff_v_u16mf4_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], ptr noundef [[V4:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], [[MASKEDOFF4:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , i64 } @llvm.riscv.vlseg5ff.mask.nxv1i16.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], [[MASKEDOFF4]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 2 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 2 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , i64 } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 2 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , i64 } [[TMP0]], 4 +// CHECK-RV64-NEXT: store [[TMP5]], ptr [[V4]], align 2 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , i64 } [[TMP0]], 5 +// CHECK-RV64-NEXT: store i64 [[TMP6]], ptr [[NEW_VL]], align 2 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg5e16ff_v_u16mf4_mu(vuint16mf4_t *v0, vuint16mf4_t *v1, vuint16mf4_t *v2, vuint16mf4_t *v3, vuint16mf4_t *v4, vbool64_t mask, vuint16mf4_t maskedoff0, vuint16mf4_t maskedoff1, vuint16mf4_t maskedoff2, vuint16mf4_t maskedoff3, vuint16mf4_t maskedoff4, const uint16_t *base, size_t *new_vl, size_t vl) { + return __riscv_vlseg5e16ff_mu(v0, v1, v2, v3, v4, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, maskedoff4, base, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlseg5e16ff_v_u16mf2_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], ptr noundef [[V4:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], [[MASKEDOFF4:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , i64 } @llvm.riscv.vlseg5ff.mask.nxv2i16.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], [[MASKEDOFF4]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 2 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 2 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , i64 } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 2 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , i64 } [[TMP0]], 4 +// CHECK-RV64-NEXT: store [[TMP5]], ptr [[V4]], align 2 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , i64 } [[TMP0]], 5 +// CHECK-RV64-NEXT: store i64 [[TMP6]], ptr [[NEW_VL]], align 2 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg5e16ff_v_u16mf2_mu(vuint16mf2_t *v0, vuint16mf2_t *v1, vuint16mf2_t *v2, vuint16mf2_t *v3, vuint16mf2_t *v4, vbool32_t mask, vuint16mf2_t maskedoff0, vuint16mf2_t maskedoff1, vuint16mf2_t maskedoff2, vuint16mf2_t maskedoff3, vuint16mf2_t maskedoff4, const uint16_t *base, size_t *new_vl, size_t vl) { + return __riscv_vlseg5e16ff_mu(v0, v1, v2, v3, v4, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, maskedoff4, base, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlseg5e16ff_v_u16m1_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], ptr noundef [[V4:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], [[MASKEDOFF4:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , i64 } @llvm.riscv.vlseg5ff.mask.nxv4i16.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], [[MASKEDOFF4]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 2 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 2 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , i64 } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 2 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , i64 } [[TMP0]], 4 +// CHECK-RV64-NEXT: store [[TMP5]], ptr [[V4]], align 2 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , i64 } [[TMP0]], 5 +// CHECK-RV64-NEXT: store i64 [[TMP6]], ptr [[NEW_VL]], align 2 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg5e16ff_v_u16m1_mu(vuint16m1_t *v0, vuint16m1_t *v1, vuint16m1_t *v2, vuint16m1_t *v3, vuint16m1_t *v4, vbool16_t mask, vuint16m1_t maskedoff0, vuint16m1_t maskedoff1, vuint16m1_t maskedoff2, vuint16m1_t maskedoff3, vuint16m1_t maskedoff4, const uint16_t *base, size_t *new_vl, size_t vl) { + return __riscv_vlseg5e16ff_mu(v0, v1, v2, v3, v4, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, maskedoff4, base, new_vl, vl); +} + diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e32.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e32.c index dc24e87c1850d..5b725d4819a31 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e32.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e32.c @@ -367,3 +367,123 @@ void test_vlseg5e32_v_u32m1_tumu(vuint32m1_t *v0, vuint32m1_t *v1, vuint32m1_t * return __riscv_vlseg5e32_tumu(v0, v1, v2, v3, v4, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, maskedoff4, base, vl); } +// CHECK-RV64-LABEL: define dso_local void @test_vlseg5e32_v_f32mf2_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], ptr noundef [[V4:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], [[MASKEDOFF4:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vlseg5.mask.nxv1f32.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], [[MASKEDOFF4]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 4 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 4 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 4 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , } [[TMP0]], 4 +// CHECK-RV64-NEXT: store [[TMP5]], ptr [[V4]], align 4 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg5e32_v_f32mf2_mu(vfloat32mf2_t *v0, vfloat32mf2_t *v1, vfloat32mf2_t *v2, vfloat32mf2_t *v3, vfloat32mf2_t *v4, vbool64_t mask, vfloat32mf2_t maskedoff0, vfloat32mf2_t maskedoff1, vfloat32mf2_t maskedoff2, vfloat32mf2_t maskedoff3, vfloat32mf2_t maskedoff4, const float *base, size_t vl) { + return __riscv_vlseg5e32_mu(v0, v1, v2, v3, v4, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, maskedoff4, base, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlseg5e32_v_f32m1_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], ptr noundef [[V4:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], [[MASKEDOFF4:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vlseg5.mask.nxv2f32.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], [[MASKEDOFF4]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 4 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 4 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 4 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , } [[TMP0]], 4 +// CHECK-RV64-NEXT: store [[TMP5]], ptr [[V4]], align 4 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg5e32_v_f32m1_mu(vfloat32m1_t *v0, vfloat32m1_t *v1, vfloat32m1_t *v2, vfloat32m1_t *v3, vfloat32m1_t *v4, vbool32_t mask, vfloat32m1_t maskedoff0, vfloat32m1_t maskedoff1, vfloat32m1_t maskedoff2, vfloat32m1_t maskedoff3, vfloat32m1_t maskedoff4, const float *base, size_t vl) { + return __riscv_vlseg5e32_mu(v0, v1, v2, v3, v4, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, maskedoff4, base, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlseg5e32_v_i32mf2_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], ptr noundef [[V4:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], [[MASKEDOFF4:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vlseg5.mask.nxv1i32.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], [[MASKEDOFF4]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 4 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 4 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 4 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , } [[TMP0]], 4 +// CHECK-RV64-NEXT: store [[TMP5]], ptr [[V4]], align 4 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg5e32_v_i32mf2_mu(vint32mf2_t *v0, vint32mf2_t *v1, vint32mf2_t *v2, vint32mf2_t *v3, vint32mf2_t *v4, vbool64_t mask, vint32mf2_t maskedoff0, vint32mf2_t maskedoff1, vint32mf2_t maskedoff2, vint32mf2_t maskedoff3, vint32mf2_t maskedoff4, const int32_t *base, size_t vl) { + return __riscv_vlseg5e32_mu(v0, v1, v2, v3, v4, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, maskedoff4, base, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlseg5e32_v_i32m1_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], ptr noundef [[V4:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], [[MASKEDOFF4:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vlseg5.mask.nxv2i32.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], [[MASKEDOFF4]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 4 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 4 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 4 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , } [[TMP0]], 4 +// CHECK-RV64-NEXT: store [[TMP5]], ptr [[V4]], align 4 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg5e32_v_i32m1_mu(vint32m1_t *v0, vint32m1_t *v1, vint32m1_t *v2, vint32m1_t *v3, vint32m1_t *v4, vbool32_t mask, vint32m1_t maskedoff0, vint32m1_t maskedoff1, vint32m1_t maskedoff2, vint32m1_t maskedoff3, vint32m1_t maskedoff4, const int32_t *base, size_t vl) { + return __riscv_vlseg5e32_mu(v0, v1, v2, v3, v4, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, maskedoff4, base, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlseg5e32_v_u32mf2_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], ptr noundef [[V4:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], [[MASKEDOFF4:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vlseg5.mask.nxv1i32.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], [[MASKEDOFF4]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 4 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 4 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 4 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , } [[TMP0]], 4 +// CHECK-RV64-NEXT: store [[TMP5]], ptr [[V4]], align 4 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg5e32_v_u32mf2_mu(vuint32mf2_t *v0, vuint32mf2_t *v1, vuint32mf2_t *v2, vuint32mf2_t *v3, vuint32mf2_t *v4, vbool64_t mask, vuint32mf2_t maskedoff0, vuint32mf2_t maskedoff1, vuint32mf2_t maskedoff2, vuint32mf2_t maskedoff3, vuint32mf2_t maskedoff4, const uint32_t *base, size_t vl) { + return __riscv_vlseg5e32_mu(v0, v1, v2, v3, v4, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, maskedoff4, base, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlseg5e32_v_u32m1_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], ptr noundef [[V4:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], [[MASKEDOFF4:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vlseg5.mask.nxv2i32.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], [[MASKEDOFF4]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 4 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 4 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 4 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , } [[TMP0]], 4 +// CHECK-RV64-NEXT: store [[TMP5]], ptr [[V4]], align 4 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg5e32_v_u32m1_mu(vuint32m1_t *v0, vuint32m1_t *v1, vuint32m1_t *v2, vuint32m1_t *v3, vuint32m1_t *v4, vbool32_t mask, vuint32m1_t maskedoff0, vuint32m1_t maskedoff1, vuint32m1_t maskedoff2, vuint32m1_t maskedoff3, vuint32m1_t maskedoff4, const uint32_t *base, size_t vl) { + return __riscv_vlseg5e32_mu(v0, v1, v2, v3, v4, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, maskedoff4, base, vl); +} + diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e32ff.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e32ff.c index ded79537af0d1..f3110448082c3 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e32ff.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e32ff.c @@ -403,3 +403,135 @@ void test_vlseg5e32ff_v_u32m1_tumu(vuint32m1_t *v0, vuint32m1_t *v1, vuint32m1_t return __riscv_vlseg5e32ff_tumu(v0, v1, v2, v3, v4, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, maskedoff4, base, new_vl, vl); } +// CHECK-RV64-LABEL: define dso_local void @test_vlseg5e32ff_v_f32mf2_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], ptr noundef [[V4:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], [[MASKEDOFF4:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , i64 } @llvm.riscv.vlseg5ff.mask.nxv1f32.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], [[MASKEDOFF4]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 4 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 4 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 4 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , i64 } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , i64 } [[TMP0]], 4 +// CHECK-RV64-NEXT: store [[TMP5]], ptr [[V4]], align 4 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , i64 } [[TMP0]], 5 +// CHECK-RV64-NEXT: store i64 [[TMP6]], ptr [[NEW_VL]], align 4 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg5e32ff_v_f32mf2_mu(vfloat32mf2_t *v0, vfloat32mf2_t *v1, vfloat32mf2_t *v2, vfloat32mf2_t *v3, vfloat32mf2_t *v4, vbool64_t mask, vfloat32mf2_t maskedoff0, vfloat32mf2_t maskedoff1, vfloat32mf2_t maskedoff2, vfloat32mf2_t maskedoff3, vfloat32mf2_t maskedoff4, const float *base, size_t *new_vl, size_t vl) { + return __riscv_vlseg5e32ff_mu(v0, v1, v2, v3, v4, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, maskedoff4, base, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlseg5e32ff_v_f32m1_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], ptr noundef [[V4:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], [[MASKEDOFF4:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , i64 } @llvm.riscv.vlseg5ff.mask.nxv2f32.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], [[MASKEDOFF4]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 4 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 4 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 4 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , i64 } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , i64 } [[TMP0]], 4 +// CHECK-RV64-NEXT: store [[TMP5]], ptr [[V4]], align 4 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , i64 } [[TMP0]], 5 +// CHECK-RV64-NEXT: store i64 [[TMP6]], ptr [[NEW_VL]], align 4 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg5e32ff_v_f32m1_mu(vfloat32m1_t *v0, vfloat32m1_t *v1, vfloat32m1_t *v2, vfloat32m1_t *v3, vfloat32m1_t *v4, vbool32_t mask, vfloat32m1_t maskedoff0, vfloat32m1_t maskedoff1, vfloat32m1_t maskedoff2, vfloat32m1_t maskedoff3, vfloat32m1_t maskedoff4, const float *base, size_t *new_vl, size_t vl) { + return __riscv_vlseg5e32ff_mu(v0, v1, v2, v3, v4, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, maskedoff4, base, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlseg5e32ff_v_i32mf2_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], ptr noundef [[V4:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], [[MASKEDOFF4:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , i64 } @llvm.riscv.vlseg5ff.mask.nxv1i32.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], [[MASKEDOFF4]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 4 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 4 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 4 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , i64 } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , i64 } [[TMP0]], 4 +// CHECK-RV64-NEXT: store [[TMP5]], ptr [[V4]], align 4 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , i64 } [[TMP0]], 5 +// CHECK-RV64-NEXT: store i64 [[TMP6]], ptr [[NEW_VL]], align 4 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg5e32ff_v_i32mf2_mu(vint32mf2_t *v0, vint32mf2_t *v1, vint32mf2_t *v2, vint32mf2_t *v3, vint32mf2_t *v4, vbool64_t mask, vint32mf2_t maskedoff0, vint32mf2_t maskedoff1, vint32mf2_t maskedoff2, vint32mf2_t maskedoff3, vint32mf2_t maskedoff4, const int32_t *base, size_t *new_vl, size_t vl) { + return __riscv_vlseg5e32ff_mu(v0, v1, v2, v3, v4, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, maskedoff4, base, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlseg5e32ff_v_i32m1_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], ptr noundef [[V4:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], [[MASKEDOFF4:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , i64 } @llvm.riscv.vlseg5ff.mask.nxv2i32.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], [[MASKEDOFF4]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 4 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 4 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 4 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , i64 } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , i64 } [[TMP0]], 4 +// CHECK-RV64-NEXT: store [[TMP5]], ptr [[V4]], align 4 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , i64 } [[TMP0]], 5 +// CHECK-RV64-NEXT: store i64 [[TMP6]], ptr [[NEW_VL]], align 4 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg5e32ff_v_i32m1_mu(vint32m1_t *v0, vint32m1_t *v1, vint32m1_t *v2, vint32m1_t *v3, vint32m1_t *v4, vbool32_t mask, vint32m1_t maskedoff0, vint32m1_t maskedoff1, vint32m1_t maskedoff2, vint32m1_t maskedoff3, vint32m1_t maskedoff4, const int32_t *base, size_t *new_vl, size_t vl) { + return __riscv_vlseg5e32ff_mu(v0, v1, v2, v3, v4, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, maskedoff4, base, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlseg5e32ff_v_u32mf2_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], ptr noundef [[V4:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], [[MASKEDOFF4:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , i64 } @llvm.riscv.vlseg5ff.mask.nxv1i32.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], [[MASKEDOFF4]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 4 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 4 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 4 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , i64 } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , i64 } [[TMP0]], 4 +// CHECK-RV64-NEXT: store [[TMP5]], ptr [[V4]], align 4 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , i64 } [[TMP0]], 5 +// CHECK-RV64-NEXT: store i64 [[TMP6]], ptr [[NEW_VL]], align 4 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg5e32ff_v_u32mf2_mu(vuint32mf2_t *v0, vuint32mf2_t *v1, vuint32mf2_t *v2, vuint32mf2_t *v3, vuint32mf2_t *v4, vbool64_t mask, vuint32mf2_t maskedoff0, vuint32mf2_t maskedoff1, vuint32mf2_t maskedoff2, vuint32mf2_t maskedoff3, vuint32mf2_t maskedoff4, const uint32_t *base, size_t *new_vl, size_t vl) { + return __riscv_vlseg5e32ff_mu(v0, v1, v2, v3, v4, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, maskedoff4, base, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlseg5e32ff_v_u32m1_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], ptr noundef [[V4:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], [[MASKEDOFF4:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , i64 } @llvm.riscv.vlseg5ff.mask.nxv2i32.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], [[MASKEDOFF4]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 4 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 4 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 4 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , i64 } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , i64 } [[TMP0]], 4 +// CHECK-RV64-NEXT: store [[TMP5]], ptr [[V4]], align 4 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , i64 } [[TMP0]], 5 +// CHECK-RV64-NEXT: store i64 [[TMP6]], ptr [[NEW_VL]], align 4 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg5e32ff_v_u32m1_mu(vuint32m1_t *v0, vuint32m1_t *v1, vuint32m1_t *v2, vuint32m1_t *v3, vuint32m1_t *v4, vbool32_t mask, vuint32m1_t maskedoff0, vuint32m1_t maskedoff1, vuint32m1_t maskedoff2, vuint32m1_t maskedoff3, vuint32m1_t maskedoff4, const uint32_t *base, size_t *new_vl, size_t vl) { + return __riscv_vlseg5e32ff_mu(v0, v1, v2, v3, v4, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, maskedoff4, base, new_vl, vl); +} + diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e64.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e64.c index b336587874d93..e43cf7872d2c4 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e64.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e64.c @@ -187,3 +187,63 @@ void test_vlseg5e64_v_u64m1_tumu(vuint64m1_t *v0, vuint64m1_t *v1, vuint64m1_t * return __riscv_vlseg5e64_tumu(v0, v1, v2, v3, v4, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, maskedoff4, base, vl); } +// CHECK-RV64-LABEL: define dso_local void @test_vlseg5e64_v_f64m1_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], ptr noundef [[V4:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], [[MASKEDOFF4:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vlseg5.mask.nxv1f64.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], [[MASKEDOFF4]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 8 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 8 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 8 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 8 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , } [[TMP0]], 4 +// CHECK-RV64-NEXT: store [[TMP5]], ptr [[V4]], align 8 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg5e64_v_f64m1_mu(vfloat64m1_t *v0, vfloat64m1_t *v1, vfloat64m1_t *v2, vfloat64m1_t *v3, vfloat64m1_t *v4, vbool64_t mask, vfloat64m1_t maskedoff0, vfloat64m1_t maskedoff1, vfloat64m1_t maskedoff2, vfloat64m1_t maskedoff3, vfloat64m1_t maskedoff4, const double *base, size_t vl) { + return __riscv_vlseg5e64_mu(v0, v1, v2, v3, v4, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, maskedoff4, base, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlseg5e64_v_i64m1_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], ptr noundef [[V4:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], [[MASKEDOFF4:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vlseg5.mask.nxv1i64.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], [[MASKEDOFF4]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 8 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 8 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 8 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 8 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , } [[TMP0]], 4 +// CHECK-RV64-NEXT: store [[TMP5]], ptr [[V4]], align 8 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg5e64_v_i64m1_mu(vint64m1_t *v0, vint64m1_t *v1, vint64m1_t *v2, vint64m1_t *v3, vint64m1_t *v4, vbool64_t mask, vint64m1_t maskedoff0, vint64m1_t maskedoff1, vint64m1_t maskedoff2, vint64m1_t maskedoff3, vint64m1_t maskedoff4, const int64_t *base, size_t vl) { + return __riscv_vlseg5e64_mu(v0, v1, v2, v3, v4, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, maskedoff4, base, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlseg5e64_v_u64m1_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], ptr noundef [[V4:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], [[MASKEDOFF4:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vlseg5.mask.nxv1i64.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], [[MASKEDOFF4]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 8 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 8 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 8 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 8 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , } [[TMP0]], 4 +// CHECK-RV64-NEXT: store [[TMP5]], ptr [[V4]], align 8 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg5e64_v_u64m1_mu(vuint64m1_t *v0, vuint64m1_t *v1, vuint64m1_t *v2, vuint64m1_t *v3, vuint64m1_t *v4, vbool64_t mask, vuint64m1_t maskedoff0, vuint64m1_t maskedoff1, vuint64m1_t maskedoff2, vuint64m1_t maskedoff3, vuint64m1_t maskedoff4, const uint64_t *base, size_t vl) { + return __riscv_vlseg5e64_mu(v0, v1, v2, v3, v4, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, maskedoff4, base, vl); +} + diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e64ff.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e64ff.c index fab97e0feb384..b99a8692f3061 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e64ff.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e64ff.c @@ -205,3 +205,69 @@ void test_vlseg5e64ff_v_u64m1_tumu(vuint64m1_t *v0, vuint64m1_t *v1, vuint64m1_t return __riscv_vlseg5e64ff_tumu(v0, v1, v2, v3, v4, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, maskedoff4, base, new_vl, vl); } +// CHECK-RV64-LABEL: define dso_local void @test_vlseg5e64ff_v_f64m1_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], ptr noundef [[V4:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], [[MASKEDOFF4:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , i64 } @llvm.riscv.vlseg5ff.mask.nxv1f64.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], [[MASKEDOFF4]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 8 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 8 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 8 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , i64 } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 8 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , i64 } [[TMP0]], 4 +// CHECK-RV64-NEXT: store [[TMP5]], ptr [[V4]], align 8 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , i64 } [[TMP0]], 5 +// CHECK-RV64-NEXT: store i64 [[TMP6]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg5e64ff_v_f64m1_mu(vfloat64m1_t *v0, vfloat64m1_t *v1, vfloat64m1_t *v2, vfloat64m1_t *v3, vfloat64m1_t *v4, vbool64_t mask, vfloat64m1_t maskedoff0, vfloat64m1_t maskedoff1, vfloat64m1_t maskedoff2, vfloat64m1_t maskedoff3, vfloat64m1_t maskedoff4, const double *base, size_t *new_vl, size_t vl) { + return __riscv_vlseg5e64ff_mu(v0, v1, v2, v3, v4, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, maskedoff4, base, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlseg5e64ff_v_i64m1_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], ptr noundef [[V4:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], [[MASKEDOFF4:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , i64 } @llvm.riscv.vlseg5ff.mask.nxv1i64.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], [[MASKEDOFF4]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 8 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 8 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 8 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , i64 } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 8 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , i64 } [[TMP0]], 4 +// CHECK-RV64-NEXT: store [[TMP5]], ptr [[V4]], align 8 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , i64 } [[TMP0]], 5 +// CHECK-RV64-NEXT: store i64 [[TMP6]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg5e64ff_v_i64m1_mu(vint64m1_t *v0, vint64m1_t *v1, vint64m1_t *v2, vint64m1_t *v3, vint64m1_t *v4, vbool64_t mask, vint64m1_t maskedoff0, vint64m1_t maskedoff1, vint64m1_t maskedoff2, vint64m1_t maskedoff3, vint64m1_t maskedoff4, const int64_t *base, size_t *new_vl, size_t vl) { + return __riscv_vlseg5e64ff_mu(v0, v1, v2, v3, v4, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, maskedoff4, base, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlseg5e64ff_v_u64m1_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], ptr noundef [[V4:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], [[MASKEDOFF4:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , i64 } @llvm.riscv.vlseg5ff.mask.nxv1i64.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], [[MASKEDOFF4]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 8 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 8 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 8 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , i64 } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 8 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , i64 } [[TMP0]], 4 +// CHECK-RV64-NEXT: store [[TMP5]], ptr [[V4]], align 8 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , i64 } [[TMP0]], 5 +// CHECK-RV64-NEXT: store i64 [[TMP6]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg5e64ff_v_u64m1_mu(vuint64m1_t *v0, vuint64m1_t *v1, vuint64m1_t *v2, vuint64m1_t *v3, vuint64m1_t *v4, vbool64_t mask, vuint64m1_t maskedoff0, vuint64m1_t maskedoff1, vuint64m1_t maskedoff2, vuint64m1_t maskedoff3, vuint64m1_t maskedoff4, const uint64_t *base, size_t *new_vl, size_t vl) { + return __riscv_vlseg5e64ff_mu(v0, v1, v2, v3, v4, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, maskedoff4, base, new_vl, vl); +} + diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e8.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e8.c index 98a606a0e7c09..2d433d3ac912b 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e8.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e8.c @@ -486,3 +486,163 @@ void test_vlseg5e8_v_u8m1_tumu(vuint8m1_t *v0, vuint8m1_t *v1, vuint8m1_t *v2, v return __riscv_vlseg5e8_tumu(v0, v1, v2, v3, v4, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, maskedoff4, base, vl); } +// CHECK-RV64-LABEL: define dso_local void @test_vlseg5e8_v_i8mf8_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], ptr noundef [[V4:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], [[MASKEDOFF4:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vlseg5.mask.nxv1i8.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], [[MASKEDOFF4]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 1 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 1 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 1 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , } [[TMP0]], 4 +// CHECK-RV64-NEXT: store [[TMP5]], ptr [[V4]], align 1 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg5e8_v_i8mf8_mu(vint8mf8_t *v0, vint8mf8_t *v1, vint8mf8_t *v2, vint8mf8_t *v3, vint8mf8_t *v4, vbool64_t mask, vint8mf8_t maskedoff0, vint8mf8_t maskedoff1, vint8mf8_t maskedoff2, vint8mf8_t maskedoff3, vint8mf8_t maskedoff4, const int8_t *base, size_t vl) { + return __riscv_vlseg5e8_mu(v0, v1, v2, v3, v4, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, maskedoff4, base, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlseg5e8_v_i8mf4_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], ptr noundef [[V4:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], [[MASKEDOFF4:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vlseg5.mask.nxv2i8.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], [[MASKEDOFF4]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 1 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 1 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 1 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , } [[TMP0]], 4 +// CHECK-RV64-NEXT: store [[TMP5]], ptr [[V4]], align 1 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg5e8_v_i8mf4_mu(vint8mf4_t *v0, vint8mf4_t *v1, vint8mf4_t *v2, vint8mf4_t *v3, vint8mf4_t *v4, vbool32_t mask, vint8mf4_t maskedoff0, vint8mf4_t maskedoff1, vint8mf4_t maskedoff2, vint8mf4_t maskedoff3, vint8mf4_t maskedoff4, const int8_t *base, size_t vl) { + return __riscv_vlseg5e8_mu(v0, v1, v2, v3, v4, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, maskedoff4, base, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlseg5e8_v_i8mf2_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], ptr noundef [[V4:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], [[MASKEDOFF4:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vlseg5.mask.nxv4i8.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], [[MASKEDOFF4]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 1 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 1 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 1 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , } [[TMP0]], 4 +// CHECK-RV64-NEXT: store [[TMP5]], ptr [[V4]], align 1 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg5e8_v_i8mf2_mu(vint8mf2_t *v0, vint8mf2_t *v1, vint8mf2_t *v2, vint8mf2_t *v3, vint8mf2_t *v4, vbool16_t mask, vint8mf2_t maskedoff0, vint8mf2_t maskedoff1, vint8mf2_t maskedoff2, vint8mf2_t maskedoff3, vint8mf2_t maskedoff4, const int8_t *base, size_t vl) { + return __riscv_vlseg5e8_mu(v0, v1, v2, v3, v4, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, maskedoff4, base, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlseg5e8_v_i8m1_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], ptr noundef [[V4:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], [[MASKEDOFF4:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vlseg5.mask.nxv8i8.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], [[MASKEDOFF4]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 1 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 1 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 1 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , } [[TMP0]], 4 +// CHECK-RV64-NEXT: store [[TMP5]], ptr [[V4]], align 1 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg5e8_v_i8m1_mu(vint8m1_t *v0, vint8m1_t *v1, vint8m1_t *v2, vint8m1_t *v3, vint8m1_t *v4, vbool8_t mask, vint8m1_t maskedoff0, vint8m1_t maskedoff1, vint8m1_t maskedoff2, vint8m1_t maskedoff3, vint8m1_t maskedoff4, const int8_t *base, size_t vl) { + return __riscv_vlseg5e8_mu(v0, v1, v2, v3, v4, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, maskedoff4, base, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlseg5e8_v_u8mf8_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], ptr noundef [[V4:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], [[MASKEDOFF4:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vlseg5.mask.nxv1i8.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], [[MASKEDOFF4]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 1 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 1 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 1 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , } [[TMP0]], 4 +// CHECK-RV64-NEXT: store [[TMP5]], ptr [[V4]], align 1 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg5e8_v_u8mf8_mu(vuint8mf8_t *v0, vuint8mf8_t *v1, vuint8mf8_t *v2, vuint8mf8_t *v3, vuint8mf8_t *v4, vbool64_t mask, vuint8mf8_t maskedoff0, vuint8mf8_t maskedoff1, vuint8mf8_t maskedoff2, vuint8mf8_t maskedoff3, vuint8mf8_t maskedoff4, const uint8_t *base, size_t vl) { + return __riscv_vlseg5e8_mu(v0, v1, v2, v3, v4, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, maskedoff4, base, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlseg5e8_v_u8mf4_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], ptr noundef [[V4:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], [[MASKEDOFF4:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vlseg5.mask.nxv2i8.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], [[MASKEDOFF4]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 1 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 1 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 1 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , } [[TMP0]], 4 +// CHECK-RV64-NEXT: store [[TMP5]], ptr [[V4]], align 1 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg5e8_v_u8mf4_mu(vuint8mf4_t *v0, vuint8mf4_t *v1, vuint8mf4_t *v2, vuint8mf4_t *v3, vuint8mf4_t *v4, vbool32_t mask, vuint8mf4_t maskedoff0, vuint8mf4_t maskedoff1, vuint8mf4_t maskedoff2, vuint8mf4_t maskedoff3, vuint8mf4_t maskedoff4, const uint8_t *base, size_t vl) { + return __riscv_vlseg5e8_mu(v0, v1, v2, v3, v4, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, maskedoff4, base, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlseg5e8_v_u8mf2_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], ptr noundef [[V4:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], [[MASKEDOFF4:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vlseg5.mask.nxv4i8.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], [[MASKEDOFF4]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 1 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 1 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 1 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , } [[TMP0]], 4 +// CHECK-RV64-NEXT: store [[TMP5]], ptr [[V4]], align 1 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg5e8_v_u8mf2_mu(vuint8mf2_t *v0, vuint8mf2_t *v1, vuint8mf2_t *v2, vuint8mf2_t *v3, vuint8mf2_t *v4, vbool16_t mask, vuint8mf2_t maskedoff0, vuint8mf2_t maskedoff1, vuint8mf2_t maskedoff2, vuint8mf2_t maskedoff3, vuint8mf2_t maskedoff4, const uint8_t *base, size_t vl) { + return __riscv_vlseg5e8_mu(v0, v1, v2, v3, v4, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, maskedoff4, base, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlseg5e8_v_u8m1_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], ptr noundef [[V4:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], [[MASKEDOFF4:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vlseg5.mask.nxv8i8.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], [[MASKEDOFF4]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 1 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 1 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 1 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , } [[TMP0]], 4 +// CHECK-RV64-NEXT: store [[TMP5]], ptr [[V4]], align 1 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg5e8_v_u8m1_mu(vuint8m1_t *v0, vuint8m1_t *v1, vuint8m1_t *v2, vuint8m1_t *v3, vuint8m1_t *v4, vbool8_t mask, vuint8m1_t maskedoff0, vuint8m1_t maskedoff1, vuint8m1_t maskedoff2, vuint8m1_t maskedoff3, vuint8m1_t maskedoff4, const uint8_t *base, size_t vl) { + return __riscv_vlseg5e8_mu(v0, v1, v2, v3, v4, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, maskedoff4, base, vl); +} + diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e8ff.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e8ff.c index e44451780e83a..d3d3fe3f4d0d6 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e8ff.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e8ff.c @@ -535,3 +535,179 @@ void test_vlseg5e8ff_v_u8m1_tumu(vuint8m1_t *v0, vuint8m1_t *v1, vuint8m1_t *v2, return __riscv_vlseg5e8ff_tumu(v0, v1, v2, v3, v4, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, maskedoff4, base, new_vl, vl); } +// CHECK-RV64-LABEL: define dso_local void @test_vlseg5e8ff_v_i8mf8_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], ptr noundef [[V4:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], [[MASKEDOFF4:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , i64 } @llvm.riscv.vlseg5ff.mask.nxv1i8.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], [[MASKEDOFF4]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 1 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 1 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , i64 } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 1 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , i64 } [[TMP0]], 4 +// CHECK-RV64-NEXT: store [[TMP5]], ptr [[V4]], align 1 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , i64 } [[TMP0]], 5 +// CHECK-RV64-NEXT: store i64 [[TMP6]], ptr [[NEW_VL]], align 1 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg5e8ff_v_i8mf8_mu(vint8mf8_t *v0, vint8mf8_t *v1, vint8mf8_t *v2, vint8mf8_t *v3, vint8mf8_t *v4, vbool64_t mask, vint8mf8_t maskedoff0, vint8mf8_t maskedoff1, vint8mf8_t maskedoff2, vint8mf8_t maskedoff3, vint8mf8_t maskedoff4, const int8_t *base, size_t *new_vl, size_t vl) { + return __riscv_vlseg5e8ff_mu(v0, v1, v2, v3, v4, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, maskedoff4, base, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlseg5e8ff_v_i8mf4_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], ptr noundef [[V4:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], [[MASKEDOFF4:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , i64 } @llvm.riscv.vlseg5ff.mask.nxv2i8.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], [[MASKEDOFF4]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 1 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 1 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , i64 } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 1 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , i64 } [[TMP0]], 4 +// CHECK-RV64-NEXT: store [[TMP5]], ptr [[V4]], align 1 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , i64 } [[TMP0]], 5 +// CHECK-RV64-NEXT: store i64 [[TMP6]], ptr [[NEW_VL]], align 1 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg5e8ff_v_i8mf4_mu(vint8mf4_t *v0, vint8mf4_t *v1, vint8mf4_t *v2, vint8mf4_t *v3, vint8mf4_t *v4, vbool32_t mask, vint8mf4_t maskedoff0, vint8mf4_t maskedoff1, vint8mf4_t maskedoff2, vint8mf4_t maskedoff3, vint8mf4_t maskedoff4, const int8_t *base, size_t *new_vl, size_t vl) { + return __riscv_vlseg5e8ff_mu(v0, v1, v2, v3, v4, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, maskedoff4, base, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlseg5e8ff_v_i8mf2_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], ptr noundef [[V4:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], [[MASKEDOFF4:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , i64 } @llvm.riscv.vlseg5ff.mask.nxv4i8.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], [[MASKEDOFF4]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 1 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 1 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , i64 } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 1 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , i64 } [[TMP0]], 4 +// CHECK-RV64-NEXT: store [[TMP5]], ptr [[V4]], align 1 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , i64 } [[TMP0]], 5 +// CHECK-RV64-NEXT: store i64 [[TMP6]], ptr [[NEW_VL]], align 1 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg5e8ff_v_i8mf2_mu(vint8mf2_t *v0, vint8mf2_t *v1, vint8mf2_t *v2, vint8mf2_t *v3, vint8mf2_t *v4, vbool16_t mask, vint8mf2_t maskedoff0, vint8mf2_t maskedoff1, vint8mf2_t maskedoff2, vint8mf2_t maskedoff3, vint8mf2_t maskedoff4, const int8_t *base, size_t *new_vl, size_t vl) { + return __riscv_vlseg5e8ff_mu(v0, v1, v2, v3, v4, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, maskedoff4, base, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlseg5e8ff_v_i8m1_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], ptr noundef [[V4:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], [[MASKEDOFF4:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , i64 } @llvm.riscv.vlseg5ff.mask.nxv8i8.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], [[MASKEDOFF4]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 1 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 1 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , i64 } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 1 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , i64 } [[TMP0]], 4 +// CHECK-RV64-NEXT: store [[TMP5]], ptr [[V4]], align 1 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , i64 } [[TMP0]], 5 +// CHECK-RV64-NEXT: store i64 [[TMP6]], ptr [[NEW_VL]], align 1 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg5e8ff_v_i8m1_mu(vint8m1_t *v0, vint8m1_t *v1, vint8m1_t *v2, vint8m1_t *v3, vint8m1_t *v4, vbool8_t mask, vint8m1_t maskedoff0, vint8m1_t maskedoff1, vint8m1_t maskedoff2, vint8m1_t maskedoff3, vint8m1_t maskedoff4, const int8_t *base, size_t *new_vl, size_t vl) { + return __riscv_vlseg5e8ff_mu(v0, v1, v2, v3, v4, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, maskedoff4, base, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlseg5e8ff_v_u8mf8_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], ptr noundef [[V4:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], [[MASKEDOFF4:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , i64 } @llvm.riscv.vlseg5ff.mask.nxv1i8.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], [[MASKEDOFF4]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 1 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 1 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , i64 } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 1 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , i64 } [[TMP0]], 4 +// CHECK-RV64-NEXT: store [[TMP5]], ptr [[V4]], align 1 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , i64 } [[TMP0]], 5 +// CHECK-RV64-NEXT: store i64 [[TMP6]], ptr [[NEW_VL]], align 1 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg5e8ff_v_u8mf8_mu(vuint8mf8_t *v0, vuint8mf8_t *v1, vuint8mf8_t *v2, vuint8mf8_t *v3, vuint8mf8_t *v4, vbool64_t mask, vuint8mf8_t maskedoff0, vuint8mf8_t maskedoff1, vuint8mf8_t maskedoff2, vuint8mf8_t maskedoff3, vuint8mf8_t maskedoff4, const uint8_t *base, size_t *new_vl, size_t vl) { + return __riscv_vlseg5e8ff_mu(v0, v1, v2, v3, v4, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, maskedoff4, base, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlseg5e8ff_v_u8mf4_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], ptr noundef [[V4:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], [[MASKEDOFF4:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , i64 } @llvm.riscv.vlseg5ff.mask.nxv2i8.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], [[MASKEDOFF4]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 1 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 1 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , i64 } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 1 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , i64 } [[TMP0]], 4 +// CHECK-RV64-NEXT: store [[TMP5]], ptr [[V4]], align 1 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , i64 } [[TMP0]], 5 +// CHECK-RV64-NEXT: store i64 [[TMP6]], ptr [[NEW_VL]], align 1 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg5e8ff_v_u8mf4_mu(vuint8mf4_t *v0, vuint8mf4_t *v1, vuint8mf4_t *v2, vuint8mf4_t *v3, vuint8mf4_t *v4, vbool32_t mask, vuint8mf4_t maskedoff0, vuint8mf4_t maskedoff1, vuint8mf4_t maskedoff2, vuint8mf4_t maskedoff3, vuint8mf4_t maskedoff4, const uint8_t *base, size_t *new_vl, size_t vl) { + return __riscv_vlseg5e8ff_mu(v0, v1, v2, v3, v4, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, maskedoff4, base, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlseg5e8ff_v_u8mf2_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], ptr noundef [[V4:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], [[MASKEDOFF4:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , i64 } @llvm.riscv.vlseg5ff.mask.nxv4i8.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], [[MASKEDOFF4]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 1 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 1 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , i64 } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 1 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , i64 } [[TMP0]], 4 +// CHECK-RV64-NEXT: store [[TMP5]], ptr [[V4]], align 1 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , i64 } [[TMP0]], 5 +// CHECK-RV64-NEXT: store i64 [[TMP6]], ptr [[NEW_VL]], align 1 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg5e8ff_v_u8mf2_mu(vuint8mf2_t *v0, vuint8mf2_t *v1, vuint8mf2_t *v2, vuint8mf2_t *v3, vuint8mf2_t *v4, vbool16_t mask, vuint8mf2_t maskedoff0, vuint8mf2_t maskedoff1, vuint8mf2_t maskedoff2, vuint8mf2_t maskedoff3, vuint8mf2_t maskedoff4, const uint8_t *base, size_t *new_vl, size_t vl) { + return __riscv_vlseg5e8ff_mu(v0, v1, v2, v3, v4, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, maskedoff4, base, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlseg5e8ff_v_u8m1_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], ptr noundef [[V4:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], [[MASKEDOFF4:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , i64 } @llvm.riscv.vlseg5ff.mask.nxv8i8.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], [[MASKEDOFF4]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 1 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 1 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , i64 } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 1 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , i64 } [[TMP0]], 4 +// CHECK-RV64-NEXT: store [[TMP5]], ptr [[V4]], align 1 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , i64 } [[TMP0]], 5 +// CHECK-RV64-NEXT: store i64 [[TMP6]], ptr [[NEW_VL]], align 1 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg5e8ff_v_u8m1_mu(vuint8m1_t *v0, vuint8m1_t *v1, vuint8m1_t *v2, vuint8m1_t *v3, vuint8m1_t *v4, vbool8_t mask, vuint8m1_t maskedoff0, vuint8m1_t maskedoff1, vuint8m1_t maskedoff2, vuint8m1_t maskedoff3, vuint8m1_t maskedoff4, const uint8_t *base, size_t *new_vl, size_t vl) { + return __riscv_vlseg5e8ff_mu(v0, v1, v2, v3, v4, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, maskedoff4, base, new_vl, vl); +} + diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e16.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e16.c index b4468ad728e66..e0a99dc6e8a90 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e16.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e16.c @@ -601,3 +601,201 @@ void test_vlseg6e16_v_u16m1_tumu(vuint16m1_t *v0, vuint16m1_t *v1, vuint16m1_t * return __riscv_vlseg6e16_tumu(v0, v1, v2, v3, v4, v5, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, maskedoff4, maskedoff5, base, vl); } +// CHECK-RV64-LABEL: define dso_local void @test_vlseg6e16_v_f16mf4_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], ptr noundef [[V4:%.*]], ptr noundef [[V5:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], [[MASKEDOFF4:%.*]], [[MASKEDOFF5:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vlseg6.mask.nxv1f16.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], [[MASKEDOFF4]], [[MASKEDOFF5]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 2 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 2 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 2 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , } [[TMP0]], 4 +// CHECK-RV64-NEXT: store [[TMP5]], ptr [[V4]], align 2 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , } [[TMP0]], 5 +// CHECK-RV64-NEXT: store [[TMP6]], ptr [[V5]], align 2 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg6e16_v_f16mf4_mu(vfloat16mf4_t *v0, vfloat16mf4_t *v1, vfloat16mf4_t *v2, vfloat16mf4_t *v3, vfloat16mf4_t *v4, vfloat16mf4_t *v5, vbool64_t mask, vfloat16mf4_t maskedoff0, vfloat16mf4_t maskedoff1, vfloat16mf4_t maskedoff2, vfloat16mf4_t maskedoff3, vfloat16mf4_t maskedoff4, vfloat16mf4_t maskedoff5, const _Float16 *base, size_t vl) { + return __riscv_vlseg6e16_mu(v0, v1, v2, v3, v4, v5, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, maskedoff4, maskedoff5, base, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlseg6e16_v_f16mf2_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], ptr noundef [[V4:%.*]], ptr noundef [[V5:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], [[MASKEDOFF4:%.*]], [[MASKEDOFF5:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vlseg6.mask.nxv2f16.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], [[MASKEDOFF4]], [[MASKEDOFF5]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 2 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 2 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 2 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , } [[TMP0]], 4 +// CHECK-RV64-NEXT: store [[TMP5]], ptr [[V4]], align 2 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , } [[TMP0]], 5 +// CHECK-RV64-NEXT: store [[TMP6]], ptr [[V5]], align 2 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg6e16_v_f16mf2_mu(vfloat16mf2_t *v0, vfloat16mf2_t *v1, vfloat16mf2_t *v2, vfloat16mf2_t *v3, vfloat16mf2_t *v4, vfloat16mf2_t *v5, vbool32_t mask, vfloat16mf2_t maskedoff0, vfloat16mf2_t maskedoff1, vfloat16mf2_t maskedoff2, vfloat16mf2_t maskedoff3, vfloat16mf2_t maskedoff4, vfloat16mf2_t maskedoff5, const _Float16 *base, size_t vl) { + return __riscv_vlseg6e16_mu(v0, v1, v2, v3, v4, v5, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, maskedoff4, maskedoff5, base, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlseg6e16_v_f16m1_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], ptr noundef [[V4:%.*]], ptr noundef [[V5:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], [[MASKEDOFF4:%.*]], [[MASKEDOFF5:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vlseg6.mask.nxv4f16.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], [[MASKEDOFF4]], [[MASKEDOFF5]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 2 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 2 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 2 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , } [[TMP0]], 4 +// CHECK-RV64-NEXT: store [[TMP5]], ptr [[V4]], align 2 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , } [[TMP0]], 5 +// CHECK-RV64-NEXT: store [[TMP6]], ptr [[V5]], align 2 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg6e16_v_f16m1_mu(vfloat16m1_t *v0, vfloat16m1_t *v1, vfloat16m1_t *v2, vfloat16m1_t *v3, vfloat16m1_t *v4, vfloat16m1_t *v5, vbool16_t mask, vfloat16m1_t maskedoff0, vfloat16m1_t maskedoff1, vfloat16m1_t maskedoff2, vfloat16m1_t maskedoff3, vfloat16m1_t maskedoff4, vfloat16m1_t maskedoff5, const _Float16 *base, size_t vl) { + return __riscv_vlseg6e16_mu(v0, v1, v2, v3, v4, v5, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, maskedoff4, maskedoff5, base, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlseg6e16_v_i16mf4_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], ptr noundef [[V4:%.*]], ptr noundef [[V5:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], [[MASKEDOFF4:%.*]], [[MASKEDOFF5:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vlseg6.mask.nxv1i16.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], [[MASKEDOFF4]], [[MASKEDOFF5]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 2 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 2 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 2 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , } [[TMP0]], 4 +// CHECK-RV64-NEXT: store [[TMP5]], ptr [[V4]], align 2 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , } [[TMP0]], 5 +// CHECK-RV64-NEXT: store [[TMP6]], ptr [[V5]], align 2 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg6e16_v_i16mf4_mu(vint16mf4_t *v0, vint16mf4_t *v1, vint16mf4_t *v2, vint16mf4_t *v3, vint16mf4_t *v4, vint16mf4_t *v5, vbool64_t mask, vint16mf4_t maskedoff0, vint16mf4_t maskedoff1, vint16mf4_t maskedoff2, vint16mf4_t maskedoff3, vint16mf4_t maskedoff4, vint16mf4_t maskedoff5, const int16_t *base, size_t vl) { + return __riscv_vlseg6e16_mu(v0, v1, v2, v3, v4, v5, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, maskedoff4, maskedoff5, base, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlseg6e16_v_i16mf2_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], ptr noundef [[V4:%.*]], ptr noundef [[V5:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], [[MASKEDOFF4:%.*]], [[MASKEDOFF5:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vlseg6.mask.nxv2i16.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], [[MASKEDOFF4]], [[MASKEDOFF5]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 2 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 2 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 2 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , } [[TMP0]], 4 +// CHECK-RV64-NEXT: store [[TMP5]], ptr [[V4]], align 2 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , } [[TMP0]], 5 +// CHECK-RV64-NEXT: store [[TMP6]], ptr [[V5]], align 2 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg6e16_v_i16mf2_mu(vint16mf2_t *v0, vint16mf2_t *v1, vint16mf2_t *v2, vint16mf2_t *v3, vint16mf2_t *v4, vint16mf2_t *v5, vbool32_t mask, vint16mf2_t maskedoff0, vint16mf2_t maskedoff1, vint16mf2_t maskedoff2, vint16mf2_t maskedoff3, vint16mf2_t maskedoff4, vint16mf2_t maskedoff5, const int16_t *base, size_t vl) { + return __riscv_vlseg6e16_mu(v0, v1, v2, v3, v4, v5, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, maskedoff4, maskedoff5, base, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlseg6e16_v_i16m1_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], ptr noundef [[V4:%.*]], ptr noundef [[V5:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], [[MASKEDOFF4:%.*]], [[MASKEDOFF5:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vlseg6.mask.nxv4i16.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], [[MASKEDOFF4]], [[MASKEDOFF5]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 2 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 2 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 2 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , } [[TMP0]], 4 +// CHECK-RV64-NEXT: store [[TMP5]], ptr [[V4]], align 2 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , } [[TMP0]], 5 +// CHECK-RV64-NEXT: store [[TMP6]], ptr [[V5]], align 2 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg6e16_v_i16m1_mu(vint16m1_t *v0, vint16m1_t *v1, vint16m1_t *v2, vint16m1_t *v3, vint16m1_t *v4, vint16m1_t *v5, vbool16_t mask, vint16m1_t maskedoff0, vint16m1_t maskedoff1, vint16m1_t maskedoff2, vint16m1_t maskedoff3, vint16m1_t maskedoff4, vint16m1_t maskedoff5, const int16_t *base, size_t vl) { + return __riscv_vlseg6e16_mu(v0, v1, v2, v3, v4, v5, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, maskedoff4, maskedoff5, base, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlseg6e16_v_u16mf4_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], ptr noundef [[V4:%.*]], ptr noundef [[V5:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], [[MASKEDOFF4:%.*]], [[MASKEDOFF5:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vlseg6.mask.nxv1i16.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], [[MASKEDOFF4]], [[MASKEDOFF5]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 2 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 2 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 2 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , } [[TMP0]], 4 +// CHECK-RV64-NEXT: store [[TMP5]], ptr [[V4]], align 2 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , } [[TMP0]], 5 +// CHECK-RV64-NEXT: store [[TMP6]], ptr [[V5]], align 2 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg6e16_v_u16mf4_mu(vuint16mf4_t *v0, vuint16mf4_t *v1, vuint16mf4_t *v2, vuint16mf4_t *v3, vuint16mf4_t *v4, vuint16mf4_t *v5, vbool64_t mask, vuint16mf4_t maskedoff0, vuint16mf4_t maskedoff1, vuint16mf4_t maskedoff2, vuint16mf4_t maskedoff3, vuint16mf4_t maskedoff4, vuint16mf4_t maskedoff5, const uint16_t *base, size_t vl) { + return __riscv_vlseg6e16_mu(v0, v1, v2, v3, v4, v5, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, maskedoff4, maskedoff5, base, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlseg6e16_v_u16mf2_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], ptr noundef [[V4:%.*]], ptr noundef [[V5:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], [[MASKEDOFF4:%.*]], [[MASKEDOFF5:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vlseg6.mask.nxv2i16.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], [[MASKEDOFF4]], [[MASKEDOFF5]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 2 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 2 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 2 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , } [[TMP0]], 4 +// CHECK-RV64-NEXT: store [[TMP5]], ptr [[V4]], align 2 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , } [[TMP0]], 5 +// CHECK-RV64-NEXT: store [[TMP6]], ptr [[V5]], align 2 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg6e16_v_u16mf2_mu(vuint16mf2_t *v0, vuint16mf2_t *v1, vuint16mf2_t *v2, vuint16mf2_t *v3, vuint16mf2_t *v4, vuint16mf2_t *v5, vbool32_t mask, vuint16mf2_t maskedoff0, vuint16mf2_t maskedoff1, vuint16mf2_t maskedoff2, vuint16mf2_t maskedoff3, vuint16mf2_t maskedoff4, vuint16mf2_t maskedoff5, const uint16_t *base, size_t vl) { + return __riscv_vlseg6e16_mu(v0, v1, v2, v3, v4, v5, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, maskedoff4, maskedoff5, base, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlseg6e16_v_u16m1_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], ptr noundef [[V4:%.*]], ptr noundef [[V5:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], [[MASKEDOFF4:%.*]], [[MASKEDOFF5:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vlseg6.mask.nxv4i16.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], [[MASKEDOFF4]], [[MASKEDOFF5]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 2 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 2 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 2 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , } [[TMP0]], 4 +// CHECK-RV64-NEXT: store [[TMP5]], ptr [[V4]], align 2 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , } [[TMP0]], 5 +// CHECK-RV64-NEXT: store [[TMP6]], ptr [[V5]], align 2 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg6e16_v_u16m1_mu(vuint16m1_t *v0, vuint16m1_t *v1, vuint16m1_t *v2, vuint16m1_t *v3, vuint16m1_t *v4, vuint16m1_t *v5, vbool16_t mask, vuint16m1_t maskedoff0, vuint16m1_t maskedoff1, vuint16m1_t maskedoff2, vuint16m1_t maskedoff3, vuint16m1_t maskedoff4, vuint16m1_t maskedoff5, const uint16_t *base, size_t vl) { + return __riscv_vlseg6e16_mu(v0, v1, v2, v3, v4, v5, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, maskedoff4, maskedoff5, base, vl); +} + diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e16ff.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e16ff.c index e354e6e745cd6..5e85cf210ba89 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e16ff.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e16ff.c @@ -655,3 +655,219 @@ void test_vlseg6e16ff_v_u16m1_tumu(vuint16m1_t *v0, vuint16m1_t *v1, vuint16m1_t return __riscv_vlseg6e16ff_tumu(v0, v1, v2, v3, v4, v5, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, maskedoff4, maskedoff5, base, new_vl, vl); } +// CHECK-RV64-LABEL: define dso_local void @test_vlseg6e16ff_v_f16mf4_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], ptr noundef [[V4:%.*]], ptr noundef [[V5:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], [[MASKEDOFF4:%.*]], [[MASKEDOFF5:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , i64 } @llvm.riscv.vlseg6ff.mask.nxv1f16.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], [[MASKEDOFF4]], [[MASKEDOFF5]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 2 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 2 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , i64 } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 2 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , i64 } [[TMP0]], 4 +// CHECK-RV64-NEXT: store [[TMP5]], ptr [[V4]], align 2 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , i64 } [[TMP0]], 5 +// CHECK-RV64-NEXT: store [[TMP6]], ptr [[V5]], align 2 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , i64 } [[TMP0]], 6 +// CHECK-RV64-NEXT: store i64 [[TMP7]], ptr [[NEW_VL]], align 2 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg6e16ff_v_f16mf4_mu(vfloat16mf4_t *v0, vfloat16mf4_t *v1, vfloat16mf4_t *v2, vfloat16mf4_t *v3, vfloat16mf4_t *v4, vfloat16mf4_t *v5, vbool64_t mask, vfloat16mf4_t maskedoff0, vfloat16mf4_t maskedoff1, vfloat16mf4_t maskedoff2, vfloat16mf4_t maskedoff3, vfloat16mf4_t maskedoff4, vfloat16mf4_t maskedoff5, const _Float16 *base, size_t *new_vl, size_t vl) { + return __riscv_vlseg6e16ff_mu(v0, v1, v2, v3, v4, v5, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, maskedoff4, maskedoff5, base, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlseg6e16ff_v_f16mf2_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], ptr noundef [[V4:%.*]], ptr noundef [[V5:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], [[MASKEDOFF4:%.*]], [[MASKEDOFF5:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , i64 } @llvm.riscv.vlseg6ff.mask.nxv2f16.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], [[MASKEDOFF4]], [[MASKEDOFF5]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 2 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 2 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , i64 } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 2 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , i64 } [[TMP0]], 4 +// CHECK-RV64-NEXT: store [[TMP5]], ptr [[V4]], align 2 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , i64 } [[TMP0]], 5 +// CHECK-RV64-NEXT: store [[TMP6]], ptr [[V5]], align 2 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , i64 } [[TMP0]], 6 +// CHECK-RV64-NEXT: store i64 [[TMP7]], ptr [[NEW_VL]], align 2 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg6e16ff_v_f16mf2_mu(vfloat16mf2_t *v0, vfloat16mf2_t *v1, vfloat16mf2_t *v2, vfloat16mf2_t *v3, vfloat16mf2_t *v4, vfloat16mf2_t *v5, vbool32_t mask, vfloat16mf2_t maskedoff0, vfloat16mf2_t maskedoff1, vfloat16mf2_t maskedoff2, vfloat16mf2_t maskedoff3, vfloat16mf2_t maskedoff4, vfloat16mf2_t maskedoff5, const _Float16 *base, size_t *new_vl, size_t vl) { + return __riscv_vlseg6e16ff_mu(v0, v1, v2, v3, v4, v5, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, maskedoff4, maskedoff5, base, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlseg6e16ff_v_f16m1_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], ptr noundef [[V4:%.*]], ptr noundef [[V5:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], [[MASKEDOFF4:%.*]], [[MASKEDOFF5:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , i64 } @llvm.riscv.vlseg6ff.mask.nxv4f16.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], [[MASKEDOFF4]], [[MASKEDOFF5]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 2 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 2 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , i64 } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 2 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , i64 } [[TMP0]], 4 +// CHECK-RV64-NEXT: store [[TMP5]], ptr [[V4]], align 2 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , i64 } [[TMP0]], 5 +// CHECK-RV64-NEXT: store [[TMP6]], ptr [[V5]], align 2 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , i64 } [[TMP0]], 6 +// CHECK-RV64-NEXT: store i64 [[TMP7]], ptr [[NEW_VL]], align 2 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg6e16ff_v_f16m1_mu(vfloat16m1_t *v0, vfloat16m1_t *v1, vfloat16m1_t *v2, vfloat16m1_t *v3, vfloat16m1_t *v4, vfloat16m1_t *v5, vbool16_t mask, vfloat16m1_t maskedoff0, vfloat16m1_t maskedoff1, vfloat16m1_t maskedoff2, vfloat16m1_t maskedoff3, vfloat16m1_t maskedoff4, vfloat16m1_t maskedoff5, const _Float16 *base, size_t *new_vl, size_t vl) { + return __riscv_vlseg6e16ff_mu(v0, v1, v2, v3, v4, v5, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, maskedoff4, maskedoff5, base, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlseg6e16ff_v_i16mf4_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], ptr noundef [[V4:%.*]], ptr noundef [[V5:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], [[MASKEDOFF4:%.*]], [[MASKEDOFF5:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , i64 } @llvm.riscv.vlseg6ff.mask.nxv1i16.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], [[MASKEDOFF4]], [[MASKEDOFF5]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 2 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 2 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , i64 } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 2 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , i64 } [[TMP0]], 4 +// CHECK-RV64-NEXT: store [[TMP5]], ptr [[V4]], align 2 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , i64 } [[TMP0]], 5 +// CHECK-RV64-NEXT: store [[TMP6]], ptr [[V5]], align 2 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , i64 } [[TMP0]], 6 +// CHECK-RV64-NEXT: store i64 [[TMP7]], ptr [[NEW_VL]], align 2 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg6e16ff_v_i16mf4_mu(vint16mf4_t *v0, vint16mf4_t *v1, vint16mf4_t *v2, vint16mf4_t *v3, vint16mf4_t *v4, vint16mf4_t *v5, vbool64_t mask, vint16mf4_t maskedoff0, vint16mf4_t maskedoff1, vint16mf4_t maskedoff2, vint16mf4_t maskedoff3, vint16mf4_t maskedoff4, vint16mf4_t maskedoff5, const int16_t *base, size_t *new_vl, size_t vl) { + return __riscv_vlseg6e16ff_mu(v0, v1, v2, v3, v4, v5, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, maskedoff4, maskedoff5, base, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlseg6e16ff_v_i16mf2_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], ptr noundef [[V4:%.*]], ptr noundef [[V5:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], [[MASKEDOFF4:%.*]], [[MASKEDOFF5:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , i64 } @llvm.riscv.vlseg6ff.mask.nxv2i16.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], [[MASKEDOFF4]], [[MASKEDOFF5]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 2 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 2 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , i64 } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 2 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , i64 } [[TMP0]], 4 +// CHECK-RV64-NEXT: store [[TMP5]], ptr [[V4]], align 2 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , i64 } [[TMP0]], 5 +// CHECK-RV64-NEXT: store [[TMP6]], ptr [[V5]], align 2 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , i64 } [[TMP0]], 6 +// CHECK-RV64-NEXT: store i64 [[TMP7]], ptr [[NEW_VL]], align 2 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg6e16ff_v_i16mf2_mu(vint16mf2_t *v0, vint16mf2_t *v1, vint16mf2_t *v2, vint16mf2_t *v3, vint16mf2_t *v4, vint16mf2_t *v5, vbool32_t mask, vint16mf2_t maskedoff0, vint16mf2_t maskedoff1, vint16mf2_t maskedoff2, vint16mf2_t maskedoff3, vint16mf2_t maskedoff4, vint16mf2_t maskedoff5, const int16_t *base, size_t *new_vl, size_t vl) { + return __riscv_vlseg6e16ff_mu(v0, v1, v2, v3, v4, v5, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, maskedoff4, maskedoff5, base, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlseg6e16ff_v_i16m1_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], ptr noundef [[V4:%.*]], ptr noundef [[V5:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], [[MASKEDOFF4:%.*]], [[MASKEDOFF5:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , i64 } @llvm.riscv.vlseg6ff.mask.nxv4i16.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], [[MASKEDOFF4]], [[MASKEDOFF5]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 2 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 2 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , i64 } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 2 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , i64 } [[TMP0]], 4 +// CHECK-RV64-NEXT: store [[TMP5]], ptr [[V4]], align 2 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , i64 } [[TMP0]], 5 +// CHECK-RV64-NEXT: store [[TMP6]], ptr [[V5]], align 2 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , i64 } [[TMP0]], 6 +// CHECK-RV64-NEXT: store i64 [[TMP7]], ptr [[NEW_VL]], align 2 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg6e16ff_v_i16m1_mu(vint16m1_t *v0, vint16m1_t *v1, vint16m1_t *v2, vint16m1_t *v3, vint16m1_t *v4, vint16m1_t *v5, vbool16_t mask, vint16m1_t maskedoff0, vint16m1_t maskedoff1, vint16m1_t maskedoff2, vint16m1_t maskedoff3, vint16m1_t maskedoff4, vint16m1_t maskedoff5, const int16_t *base, size_t *new_vl, size_t vl) { + return __riscv_vlseg6e16ff_mu(v0, v1, v2, v3, v4, v5, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, maskedoff4, maskedoff5, base, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlseg6e16ff_v_u16mf4_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], ptr noundef [[V4:%.*]], ptr noundef [[V5:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], [[MASKEDOFF4:%.*]], [[MASKEDOFF5:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , i64 } @llvm.riscv.vlseg6ff.mask.nxv1i16.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], [[MASKEDOFF4]], [[MASKEDOFF5]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 2 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 2 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , i64 } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 2 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , i64 } [[TMP0]], 4 +// CHECK-RV64-NEXT: store [[TMP5]], ptr [[V4]], align 2 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , i64 } [[TMP0]], 5 +// CHECK-RV64-NEXT: store [[TMP6]], ptr [[V5]], align 2 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , i64 } [[TMP0]], 6 +// CHECK-RV64-NEXT: store i64 [[TMP7]], ptr [[NEW_VL]], align 2 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg6e16ff_v_u16mf4_mu(vuint16mf4_t *v0, vuint16mf4_t *v1, vuint16mf4_t *v2, vuint16mf4_t *v3, vuint16mf4_t *v4, vuint16mf4_t *v5, vbool64_t mask, vuint16mf4_t maskedoff0, vuint16mf4_t maskedoff1, vuint16mf4_t maskedoff2, vuint16mf4_t maskedoff3, vuint16mf4_t maskedoff4, vuint16mf4_t maskedoff5, const uint16_t *base, size_t *new_vl, size_t vl) { + return __riscv_vlseg6e16ff_mu(v0, v1, v2, v3, v4, v5, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, maskedoff4, maskedoff5, base, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlseg6e16ff_v_u16mf2_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], ptr noundef [[V4:%.*]], ptr noundef [[V5:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], [[MASKEDOFF4:%.*]], [[MASKEDOFF5:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , i64 } @llvm.riscv.vlseg6ff.mask.nxv2i16.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], [[MASKEDOFF4]], [[MASKEDOFF5]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 2 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 2 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , i64 } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 2 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , i64 } [[TMP0]], 4 +// CHECK-RV64-NEXT: store [[TMP5]], ptr [[V4]], align 2 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , i64 } [[TMP0]], 5 +// CHECK-RV64-NEXT: store [[TMP6]], ptr [[V5]], align 2 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , i64 } [[TMP0]], 6 +// CHECK-RV64-NEXT: store i64 [[TMP7]], ptr [[NEW_VL]], align 2 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg6e16ff_v_u16mf2_mu(vuint16mf2_t *v0, vuint16mf2_t *v1, vuint16mf2_t *v2, vuint16mf2_t *v3, vuint16mf2_t *v4, vuint16mf2_t *v5, vbool32_t mask, vuint16mf2_t maskedoff0, vuint16mf2_t maskedoff1, vuint16mf2_t maskedoff2, vuint16mf2_t maskedoff3, vuint16mf2_t maskedoff4, vuint16mf2_t maskedoff5, const uint16_t *base, size_t *new_vl, size_t vl) { + return __riscv_vlseg6e16ff_mu(v0, v1, v2, v3, v4, v5, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, maskedoff4, maskedoff5, base, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlseg6e16ff_v_u16m1_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], ptr noundef [[V4:%.*]], ptr noundef [[V5:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], [[MASKEDOFF4:%.*]], [[MASKEDOFF5:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , i64 } @llvm.riscv.vlseg6ff.mask.nxv4i16.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], [[MASKEDOFF4]], [[MASKEDOFF5]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 2 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 2 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , i64 } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 2 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , i64 } [[TMP0]], 4 +// CHECK-RV64-NEXT: store [[TMP5]], ptr [[V4]], align 2 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , i64 } [[TMP0]], 5 +// CHECK-RV64-NEXT: store [[TMP6]], ptr [[V5]], align 2 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , i64 } [[TMP0]], 6 +// CHECK-RV64-NEXT: store i64 [[TMP7]], ptr [[NEW_VL]], align 2 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg6e16ff_v_u16m1_mu(vuint16m1_t *v0, vuint16m1_t *v1, vuint16m1_t *v2, vuint16m1_t *v3, vuint16m1_t *v4, vuint16m1_t *v5, vbool16_t mask, vuint16m1_t maskedoff0, vuint16m1_t maskedoff1, vuint16m1_t maskedoff2, vuint16m1_t maskedoff3, vuint16m1_t maskedoff4, vuint16m1_t maskedoff5, const uint16_t *base, size_t *new_vl, size_t vl) { + return __riscv_vlseg6e16ff_mu(v0, v1, v2, v3, v4, v5, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, maskedoff4, maskedoff5, base, new_vl, vl); +} + diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e32.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e32.c index f1394a2f78ba3..f71e7b53b6e00 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e32.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e32.c @@ -403,3 +403,135 @@ void test_vlseg6e32_v_u32m1_tumu(vuint32m1_t *v0, vuint32m1_t *v1, vuint32m1_t * return __riscv_vlseg6e32_tumu(v0, v1, v2, v3, v4, v5, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, maskedoff4, maskedoff5, base, vl); } +// CHECK-RV64-LABEL: define dso_local void @test_vlseg6e32_v_f32mf2_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], ptr noundef [[V4:%.*]], ptr noundef [[V5:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], [[MASKEDOFF4:%.*]], [[MASKEDOFF5:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vlseg6.mask.nxv1f32.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], [[MASKEDOFF4]], [[MASKEDOFF5]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 4 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 4 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 4 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , } [[TMP0]], 4 +// CHECK-RV64-NEXT: store [[TMP5]], ptr [[V4]], align 4 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , } [[TMP0]], 5 +// CHECK-RV64-NEXT: store [[TMP6]], ptr [[V5]], align 4 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg6e32_v_f32mf2_mu(vfloat32mf2_t *v0, vfloat32mf2_t *v1, vfloat32mf2_t *v2, vfloat32mf2_t *v3, vfloat32mf2_t *v4, vfloat32mf2_t *v5, vbool64_t mask, vfloat32mf2_t maskedoff0, vfloat32mf2_t maskedoff1, vfloat32mf2_t maskedoff2, vfloat32mf2_t maskedoff3, vfloat32mf2_t maskedoff4, vfloat32mf2_t maskedoff5, const float *base, size_t vl) { + return __riscv_vlseg6e32_mu(v0, v1, v2, v3, v4, v5, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, maskedoff4, maskedoff5, base, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlseg6e32_v_f32m1_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], ptr noundef [[V4:%.*]], ptr noundef [[V5:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], [[MASKEDOFF4:%.*]], [[MASKEDOFF5:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vlseg6.mask.nxv2f32.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], [[MASKEDOFF4]], [[MASKEDOFF5]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 4 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 4 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 4 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , } [[TMP0]], 4 +// CHECK-RV64-NEXT: store [[TMP5]], ptr [[V4]], align 4 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , } [[TMP0]], 5 +// CHECK-RV64-NEXT: store [[TMP6]], ptr [[V5]], align 4 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg6e32_v_f32m1_mu(vfloat32m1_t *v0, vfloat32m1_t *v1, vfloat32m1_t *v2, vfloat32m1_t *v3, vfloat32m1_t *v4, vfloat32m1_t *v5, vbool32_t mask, vfloat32m1_t maskedoff0, vfloat32m1_t maskedoff1, vfloat32m1_t maskedoff2, vfloat32m1_t maskedoff3, vfloat32m1_t maskedoff4, vfloat32m1_t maskedoff5, const float *base, size_t vl) { + return __riscv_vlseg6e32_mu(v0, v1, v2, v3, v4, v5, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, maskedoff4, maskedoff5, base, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlseg6e32_v_i32mf2_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], ptr noundef [[V4:%.*]], ptr noundef [[V5:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], [[MASKEDOFF4:%.*]], [[MASKEDOFF5:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vlseg6.mask.nxv1i32.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], [[MASKEDOFF4]], [[MASKEDOFF5]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 4 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 4 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 4 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , } [[TMP0]], 4 +// CHECK-RV64-NEXT: store [[TMP5]], ptr [[V4]], align 4 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , } [[TMP0]], 5 +// CHECK-RV64-NEXT: store [[TMP6]], ptr [[V5]], align 4 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg6e32_v_i32mf2_mu(vint32mf2_t *v0, vint32mf2_t *v1, vint32mf2_t *v2, vint32mf2_t *v3, vint32mf2_t *v4, vint32mf2_t *v5, vbool64_t mask, vint32mf2_t maskedoff0, vint32mf2_t maskedoff1, vint32mf2_t maskedoff2, vint32mf2_t maskedoff3, vint32mf2_t maskedoff4, vint32mf2_t maskedoff5, const int32_t *base, size_t vl) { + return __riscv_vlseg6e32_mu(v0, v1, v2, v3, v4, v5, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, maskedoff4, maskedoff5, base, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlseg6e32_v_i32m1_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], ptr noundef [[V4:%.*]], ptr noundef [[V5:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], [[MASKEDOFF4:%.*]], [[MASKEDOFF5:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vlseg6.mask.nxv2i32.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], [[MASKEDOFF4]], [[MASKEDOFF5]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 4 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 4 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 4 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , } [[TMP0]], 4 +// CHECK-RV64-NEXT: store [[TMP5]], ptr [[V4]], align 4 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , } [[TMP0]], 5 +// CHECK-RV64-NEXT: store [[TMP6]], ptr [[V5]], align 4 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg6e32_v_i32m1_mu(vint32m1_t *v0, vint32m1_t *v1, vint32m1_t *v2, vint32m1_t *v3, vint32m1_t *v4, vint32m1_t *v5, vbool32_t mask, vint32m1_t maskedoff0, vint32m1_t maskedoff1, vint32m1_t maskedoff2, vint32m1_t maskedoff3, vint32m1_t maskedoff4, vint32m1_t maskedoff5, const int32_t *base, size_t vl) { + return __riscv_vlseg6e32_mu(v0, v1, v2, v3, v4, v5, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, maskedoff4, maskedoff5, base, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlseg6e32_v_u32mf2_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], ptr noundef [[V4:%.*]], ptr noundef [[V5:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], [[MASKEDOFF4:%.*]], [[MASKEDOFF5:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vlseg6.mask.nxv1i32.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], [[MASKEDOFF4]], [[MASKEDOFF5]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 4 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 4 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 4 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , } [[TMP0]], 4 +// CHECK-RV64-NEXT: store [[TMP5]], ptr [[V4]], align 4 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , } [[TMP0]], 5 +// CHECK-RV64-NEXT: store [[TMP6]], ptr [[V5]], align 4 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg6e32_v_u32mf2_mu(vuint32mf2_t *v0, vuint32mf2_t *v1, vuint32mf2_t *v2, vuint32mf2_t *v3, vuint32mf2_t *v4, vuint32mf2_t *v5, vbool64_t mask, vuint32mf2_t maskedoff0, vuint32mf2_t maskedoff1, vuint32mf2_t maskedoff2, vuint32mf2_t maskedoff3, vuint32mf2_t maskedoff4, vuint32mf2_t maskedoff5, const uint32_t *base, size_t vl) { + return __riscv_vlseg6e32_mu(v0, v1, v2, v3, v4, v5, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, maskedoff4, maskedoff5, base, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlseg6e32_v_u32m1_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], ptr noundef [[V4:%.*]], ptr noundef [[V5:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], [[MASKEDOFF4:%.*]], [[MASKEDOFF5:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vlseg6.mask.nxv2i32.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], [[MASKEDOFF4]], [[MASKEDOFF5]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 4 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 4 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 4 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , } [[TMP0]], 4 +// CHECK-RV64-NEXT: store [[TMP5]], ptr [[V4]], align 4 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , } [[TMP0]], 5 +// CHECK-RV64-NEXT: store [[TMP6]], ptr [[V5]], align 4 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg6e32_v_u32m1_mu(vuint32m1_t *v0, vuint32m1_t *v1, vuint32m1_t *v2, vuint32m1_t *v3, vuint32m1_t *v4, vuint32m1_t *v5, vbool32_t mask, vuint32m1_t maskedoff0, vuint32m1_t maskedoff1, vuint32m1_t maskedoff2, vuint32m1_t maskedoff3, vuint32m1_t maskedoff4, vuint32m1_t maskedoff5, const uint32_t *base, size_t vl) { + return __riscv_vlseg6e32_mu(v0, v1, v2, v3, v4, v5, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, maskedoff4, maskedoff5, base, vl); +} + diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e32ff.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e32ff.c index dcaece3e55ee5..a2b8a949db3e6 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e32ff.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e32ff.c @@ -439,3 +439,147 @@ void test_vlseg6e32ff_v_u32m1_tumu(vuint32m1_t *v0, vuint32m1_t *v1, vuint32m1_t return __riscv_vlseg6e32ff_tumu(v0, v1, v2, v3, v4, v5, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, maskedoff4, maskedoff5, base, new_vl, vl); } +// CHECK-RV64-LABEL: define dso_local void @test_vlseg6e32ff_v_f32mf2_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], ptr noundef [[V4:%.*]], ptr noundef [[V5:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], [[MASKEDOFF4:%.*]], [[MASKEDOFF5:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , i64 } @llvm.riscv.vlseg6ff.mask.nxv1f32.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], [[MASKEDOFF4]], [[MASKEDOFF5]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 4 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 4 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 4 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , i64 } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , i64 } [[TMP0]], 4 +// CHECK-RV64-NEXT: store [[TMP5]], ptr [[V4]], align 4 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , i64 } [[TMP0]], 5 +// CHECK-RV64-NEXT: store [[TMP6]], ptr [[V5]], align 4 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , i64 } [[TMP0]], 6 +// CHECK-RV64-NEXT: store i64 [[TMP7]], ptr [[NEW_VL]], align 4 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg6e32ff_v_f32mf2_mu(vfloat32mf2_t *v0, vfloat32mf2_t *v1, vfloat32mf2_t *v2, vfloat32mf2_t *v3, vfloat32mf2_t *v4, vfloat32mf2_t *v5, vbool64_t mask, vfloat32mf2_t maskedoff0, vfloat32mf2_t maskedoff1, vfloat32mf2_t maskedoff2, vfloat32mf2_t maskedoff3, vfloat32mf2_t maskedoff4, vfloat32mf2_t maskedoff5, const float *base, size_t *new_vl, size_t vl) { + return __riscv_vlseg6e32ff_mu(v0, v1, v2, v3, v4, v5, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, maskedoff4, maskedoff5, base, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlseg6e32ff_v_f32m1_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], ptr noundef [[V4:%.*]], ptr noundef [[V5:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], [[MASKEDOFF4:%.*]], [[MASKEDOFF5:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , i64 } @llvm.riscv.vlseg6ff.mask.nxv2f32.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], [[MASKEDOFF4]], [[MASKEDOFF5]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 4 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 4 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 4 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , i64 } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , i64 } [[TMP0]], 4 +// CHECK-RV64-NEXT: store [[TMP5]], ptr [[V4]], align 4 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , i64 } [[TMP0]], 5 +// CHECK-RV64-NEXT: store [[TMP6]], ptr [[V5]], align 4 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , i64 } [[TMP0]], 6 +// CHECK-RV64-NEXT: store i64 [[TMP7]], ptr [[NEW_VL]], align 4 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg6e32ff_v_f32m1_mu(vfloat32m1_t *v0, vfloat32m1_t *v1, vfloat32m1_t *v2, vfloat32m1_t *v3, vfloat32m1_t *v4, vfloat32m1_t *v5, vbool32_t mask, vfloat32m1_t maskedoff0, vfloat32m1_t maskedoff1, vfloat32m1_t maskedoff2, vfloat32m1_t maskedoff3, vfloat32m1_t maskedoff4, vfloat32m1_t maskedoff5, const float *base, size_t *new_vl, size_t vl) { + return __riscv_vlseg6e32ff_mu(v0, v1, v2, v3, v4, v5, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, maskedoff4, maskedoff5, base, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlseg6e32ff_v_i32mf2_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], ptr noundef [[V4:%.*]], ptr noundef [[V5:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], [[MASKEDOFF4:%.*]], [[MASKEDOFF5:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , i64 } @llvm.riscv.vlseg6ff.mask.nxv1i32.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], [[MASKEDOFF4]], [[MASKEDOFF5]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 4 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 4 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 4 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , i64 } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , i64 } [[TMP0]], 4 +// CHECK-RV64-NEXT: store [[TMP5]], ptr [[V4]], align 4 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , i64 } [[TMP0]], 5 +// CHECK-RV64-NEXT: store [[TMP6]], ptr [[V5]], align 4 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , i64 } [[TMP0]], 6 +// CHECK-RV64-NEXT: store i64 [[TMP7]], ptr [[NEW_VL]], align 4 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg6e32ff_v_i32mf2_mu(vint32mf2_t *v0, vint32mf2_t *v1, vint32mf2_t *v2, vint32mf2_t *v3, vint32mf2_t *v4, vint32mf2_t *v5, vbool64_t mask, vint32mf2_t maskedoff0, vint32mf2_t maskedoff1, vint32mf2_t maskedoff2, vint32mf2_t maskedoff3, vint32mf2_t maskedoff4, vint32mf2_t maskedoff5, const int32_t *base, size_t *new_vl, size_t vl) { + return __riscv_vlseg6e32ff_mu(v0, v1, v2, v3, v4, v5, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, maskedoff4, maskedoff5, base, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlseg6e32ff_v_i32m1_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], ptr noundef [[V4:%.*]], ptr noundef [[V5:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], [[MASKEDOFF4:%.*]], [[MASKEDOFF5:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , i64 } @llvm.riscv.vlseg6ff.mask.nxv2i32.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], [[MASKEDOFF4]], [[MASKEDOFF5]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 4 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 4 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 4 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , i64 } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , i64 } [[TMP0]], 4 +// CHECK-RV64-NEXT: store [[TMP5]], ptr [[V4]], align 4 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , i64 } [[TMP0]], 5 +// CHECK-RV64-NEXT: store [[TMP6]], ptr [[V5]], align 4 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , i64 } [[TMP0]], 6 +// CHECK-RV64-NEXT: store i64 [[TMP7]], ptr [[NEW_VL]], align 4 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg6e32ff_v_i32m1_mu(vint32m1_t *v0, vint32m1_t *v1, vint32m1_t *v2, vint32m1_t *v3, vint32m1_t *v4, vint32m1_t *v5, vbool32_t mask, vint32m1_t maskedoff0, vint32m1_t maskedoff1, vint32m1_t maskedoff2, vint32m1_t maskedoff3, vint32m1_t maskedoff4, vint32m1_t maskedoff5, const int32_t *base, size_t *new_vl, size_t vl) { + return __riscv_vlseg6e32ff_mu(v0, v1, v2, v3, v4, v5, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, maskedoff4, maskedoff5, base, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlseg6e32ff_v_u32mf2_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], ptr noundef [[V4:%.*]], ptr noundef [[V5:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], [[MASKEDOFF4:%.*]], [[MASKEDOFF5:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , i64 } @llvm.riscv.vlseg6ff.mask.nxv1i32.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], [[MASKEDOFF4]], [[MASKEDOFF5]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 4 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 4 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 4 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , i64 } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , i64 } [[TMP0]], 4 +// CHECK-RV64-NEXT: store [[TMP5]], ptr [[V4]], align 4 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , i64 } [[TMP0]], 5 +// CHECK-RV64-NEXT: store [[TMP6]], ptr [[V5]], align 4 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , i64 } [[TMP0]], 6 +// CHECK-RV64-NEXT: store i64 [[TMP7]], ptr [[NEW_VL]], align 4 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg6e32ff_v_u32mf2_mu(vuint32mf2_t *v0, vuint32mf2_t *v1, vuint32mf2_t *v2, vuint32mf2_t *v3, vuint32mf2_t *v4, vuint32mf2_t *v5, vbool64_t mask, vuint32mf2_t maskedoff0, vuint32mf2_t maskedoff1, vuint32mf2_t maskedoff2, vuint32mf2_t maskedoff3, vuint32mf2_t maskedoff4, vuint32mf2_t maskedoff5, const uint32_t *base, size_t *new_vl, size_t vl) { + return __riscv_vlseg6e32ff_mu(v0, v1, v2, v3, v4, v5, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, maskedoff4, maskedoff5, base, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlseg6e32ff_v_u32m1_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], ptr noundef [[V4:%.*]], ptr noundef [[V5:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], [[MASKEDOFF4:%.*]], [[MASKEDOFF5:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , i64 } @llvm.riscv.vlseg6ff.mask.nxv2i32.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], [[MASKEDOFF4]], [[MASKEDOFF5]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 4 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 4 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 4 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , i64 } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , i64 } [[TMP0]], 4 +// CHECK-RV64-NEXT: store [[TMP5]], ptr [[V4]], align 4 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , i64 } [[TMP0]], 5 +// CHECK-RV64-NEXT: store [[TMP6]], ptr [[V5]], align 4 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , i64 } [[TMP0]], 6 +// CHECK-RV64-NEXT: store i64 [[TMP7]], ptr [[NEW_VL]], align 4 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg6e32ff_v_u32m1_mu(vuint32m1_t *v0, vuint32m1_t *v1, vuint32m1_t *v2, vuint32m1_t *v3, vuint32m1_t *v4, vuint32m1_t *v5, vbool32_t mask, vuint32m1_t maskedoff0, vuint32m1_t maskedoff1, vuint32m1_t maskedoff2, vuint32m1_t maskedoff3, vuint32m1_t maskedoff4, vuint32m1_t maskedoff5, const uint32_t *base, size_t *new_vl, size_t vl) { + return __riscv_vlseg6e32ff_mu(v0, v1, v2, v3, v4, v5, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, maskedoff4, maskedoff5, base, new_vl, vl); +} + diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e64.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e64.c index 95f38c56ea0f7..0d59a9013258f 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e64.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e64.c @@ -205,3 +205,69 @@ void test_vlseg6e64_v_u64m1_tumu(vuint64m1_t *v0, vuint64m1_t *v1, vuint64m1_t * return __riscv_vlseg6e64_tumu(v0, v1, v2, v3, v4, v5, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, maskedoff4, maskedoff5, base, vl); } +// CHECK-RV64-LABEL: define dso_local void @test_vlseg6e64_v_f64m1_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], ptr noundef [[V4:%.*]], ptr noundef [[V5:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], [[MASKEDOFF4:%.*]], [[MASKEDOFF5:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vlseg6.mask.nxv1f64.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], [[MASKEDOFF4]], [[MASKEDOFF5]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 8 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 8 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 8 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 8 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , } [[TMP0]], 4 +// CHECK-RV64-NEXT: store [[TMP5]], ptr [[V4]], align 8 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , } [[TMP0]], 5 +// CHECK-RV64-NEXT: store [[TMP6]], ptr [[V5]], align 8 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg6e64_v_f64m1_mu(vfloat64m1_t *v0, vfloat64m1_t *v1, vfloat64m1_t *v2, vfloat64m1_t *v3, vfloat64m1_t *v4, vfloat64m1_t *v5, vbool64_t mask, vfloat64m1_t maskedoff0, vfloat64m1_t maskedoff1, vfloat64m1_t maskedoff2, vfloat64m1_t maskedoff3, vfloat64m1_t maskedoff4, vfloat64m1_t maskedoff5, const double *base, size_t vl) { + return __riscv_vlseg6e64_mu(v0, v1, v2, v3, v4, v5, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, maskedoff4, maskedoff5, base, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlseg6e64_v_i64m1_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], ptr noundef [[V4:%.*]], ptr noundef [[V5:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], [[MASKEDOFF4:%.*]], [[MASKEDOFF5:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vlseg6.mask.nxv1i64.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], [[MASKEDOFF4]], [[MASKEDOFF5]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 8 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 8 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 8 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 8 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , } [[TMP0]], 4 +// CHECK-RV64-NEXT: store [[TMP5]], ptr [[V4]], align 8 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , } [[TMP0]], 5 +// CHECK-RV64-NEXT: store [[TMP6]], ptr [[V5]], align 8 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg6e64_v_i64m1_mu(vint64m1_t *v0, vint64m1_t *v1, vint64m1_t *v2, vint64m1_t *v3, vint64m1_t *v4, vint64m1_t *v5, vbool64_t mask, vint64m1_t maskedoff0, vint64m1_t maskedoff1, vint64m1_t maskedoff2, vint64m1_t maskedoff3, vint64m1_t maskedoff4, vint64m1_t maskedoff5, const int64_t *base, size_t vl) { + return __riscv_vlseg6e64_mu(v0, v1, v2, v3, v4, v5, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, maskedoff4, maskedoff5, base, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlseg6e64_v_u64m1_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], ptr noundef [[V4:%.*]], ptr noundef [[V5:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], [[MASKEDOFF4:%.*]], [[MASKEDOFF5:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vlseg6.mask.nxv1i64.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], [[MASKEDOFF4]], [[MASKEDOFF5]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 8 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 8 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 8 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 8 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , } [[TMP0]], 4 +// CHECK-RV64-NEXT: store [[TMP5]], ptr [[V4]], align 8 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , } [[TMP0]], 5 +// CHECK-RV64-NEXT: store [[TMP6]], ptr [[V5]], align 8 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg6e64_v_u64m1_mu(vuint64m1_t *v0, vuint64m1_t *v1, vuint64m1_t *v2, vuint64m1_t *v3, vuint64m1_t *v4, vuint64m1_t *v5, vbool64_t mask, vuint64m1_t maskedoff0, vuint64m1_t maskedoff1, vuint64m1_t maskedoff2, vuint64m1_t maskedoff3, vuint64m1_t maskedoff4, vuint64m1_t maskedoff5, const uint64_t *base, size_t vl) { + return __riscv_vlseg6e64_mu(v0, v1, v2, v3, v4, v5, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, maskedoff4, maskedoff5, base, vl); +} + diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e64ff.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e64ff.c index 6aae1667bf5b5..dc63f93c232b9 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e64ff.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e64ff.c @@ -223,3 +223,75 @@ void test_vlseg6e64ff_v_u64m1_tumu(vuint64m1_t *v0, vuint64m1_t *v1, vuint64m1_t return __riscv_vlseg6e64ff_tumu(v0, v1, v2, v3, v4, v5, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, maskedoff4, maskedoff5, base, new_vl, vl); } +// CHECK-RV64-LABEL: define dso_local void @test_vlseg6e64ff_v_f64m1_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], ptr noundef [[V4:%.*]], ptr noundef [[V5:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], [[MASKEDOFF4:%.*]], [[MASKEDOFF5:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , i64 } @llvm.riscv.vlseg6ff.mask.nxv1f64.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], [[MASKEDOFF4]], [[MASKEDOFF5]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 8 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 8 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 8 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , i64 } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 8 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , i64 } [[TMP0]], 4 +// CHECK-RV64-NEXT: store [[TMP5]], ptr [[V4]], align 8 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , i64 } [[TMP0]], 5 +// CHECK-RV64-NEXT: store [[TMP6]], ptr [[V5]], align 8 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , i64 } [[TMP0]], 6 +// CHECK-RV64-NEXT: store i64 [[TMP7]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg6e64ff_v_f64m1_mu(vfloat64m1_t *v0, vfloat64m1_t *v1, vfloat64m1_t *v2, vfloat64m1_t *v3, vfloat64m1_t *v4, vfloat64m1_t *v5, vbool64_t mask, vfloat64m1_t maskedoff0, vfloat64m1_t maskedoff1, vfloat64m1_t maskedoff2, vfloat64m1_t maskedoff3, vfloat64m1_t maskedoff4, vfloat64m1_t maskedoff5, const double *base, size_t *new_vl, size_t vl) { + return __riscv_vlseg6e64ff_mu(v0, v1, v2, v3, v4, v5, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, maskedoff4, maskedoff5, base, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlseg6e64ff_v_i64m1_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], ptr noundef [[V4:%.*]], ptr noundef [[V5:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], [[MASKEDOFF4:%.*]], [[MASKEDOFF5:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , i64 } @llvm.riscv.vlseg6ff.mask.nxv1i64.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], [[MASKEDOFF4]], [[MASKEDOFF5]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 8 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 8 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 8 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , i64 } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 8 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , i64 } [[TMP0]], 4 +// CHECK-RV64-NEXT: store [[TMP5]], ptr [[V4]], align 8 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , i64 } [[TMP0]], 5 +// CHECK-RV64-NEXT: store [[TMP6]], ptr [[V5]], align 8 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , i64 } [[TMP0]], 6 +// CHECK-RV64-NEXT: store i64 [[TMP7]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg6e64ff_v_i64m1_mu(vint64m1_t *v0, vint64m1_t *v1, vint64m1_t *v2, vint64m1_t *v3, vint64m1_t *v4, vint64m1_t *v5, vbool64_t mask, vint64m1_t maskedoff0, vint64m1_t maskedoff1, vint64m1_t maskedoff2, vint64m1_t maskedoff3, vint64m1_t maskedoff4, vint64m1_t maskedoff5, const int64_t *base, size_t *new_vl, size_t vl) { + return __riscv_vlseg6e64ff_mu(v0, v1, v2, v3, v4, v5, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, maskedoff4, maskedoff5, base, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlseg6e64ff_v_u64m1_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], ptr noundef [[V4:%.*]], ptr noundef [[V5:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], [[MASKEDOFF4:%.*]], [[MASKEDOFF5:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , i64 } @llvm.riscv.vlseg6ff.mask.nxv1i64.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], [[MASKEDOFF4]], [[MASKEDOFF5]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 8 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 8 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 8 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , i64 } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 8 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , i64 } [[TMP0]], 4 +// CHECK-RV64-NEXT: store [[TMP5]], ptr [[V4]], align 8 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , i64 } [[TMP0]], 5 +// CHECK-RV64-NEXT: store [[TMP6]], ptr [[V5]], align 8 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , i64 } [[TMP0]], 6 +// CHECK-RV64-NEXT: store i64 [[TMP7]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg6e64ff_v_u64m1_mu(vuint64m1_t *v0, vuint64m1_t *v1, vuint64m1_t *v2, vuint64m1_t *v3, vuint64m1_t *v4, vuint64m1_t *v5, vbool64_t mask, vuint64m1_t maskedoff0, vuint64m1_t maskedoff1, vuint64m1_t maskedoff2, vuint64m1_t maskedoff3, vuint64m1_t maskedoff4, vuint64m1_t maskedoff5, const uint64_t *base, size_t *new_vl, size_t vl) { + return __riscv_vlseg6e64ff_mu(v0, v1, v2, v3, v4, v5, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, maskedoff4, maskedoff5, base, new_vl, vl); +} + diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e8.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e8.c index db98dd59d9953..917a7815daa12 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e8.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e8.c @@ -534,3 +534,179 @@ void test_vlseg6e8_v_u8m1_tumu(vuint8m1_t *v0, vuint8m1_t *v1, vuint8m1_t *v2, v return __riscv_vlseg6e8_tumu(v0, v1, v2, v3, v4, v5, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, maskedoff4, maskedoff5, base, vl); } +// CHECK-RV64-LABEL: define dso_local void @test_vlseg6e8_v_i8mf8_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], ptr noundef [[V4:%.*]], ptr noundef [[V5:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], [[MASKEDOFF4:%.*]], [[MASKEDOFF5:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vlseg6.mask.nxv1i8.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], [[MASKEDOFF4]], [[MASKEDOFF5]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 1 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 1 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 1 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , } [[TMP0]], 4 +// CHECK-RV64-NEXT: store [[TMP5]], ptr [[V4]], align 1 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , } [[TMP0]], 5 +// CHECK-RV64-NEXT: store [[TMP6]], ptr [[V5]], align 1 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg6e8_v_i8mf8_mu(vint8mf8_t *v0, vint8mf8_t *v1, vint8mf8_t *v2, vint8mf8_t *v3, vint8mf8_t *v4, vint8mf8_t *v5, vbool64_t mask, vint8mf8_t maskedoff0, vint8mf8_t maskedoff1, vint8mf8_t maskedoff2, vint8mf8_t maskedoff3, vint8mf8_t maskedoff4, vint8mf8_t maskedoff5, const int8_t *base, size_t vl) { + return __riscv_vlseg6e8_mu(v0, v1, v2, v3, v4, v5, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, maskedoff4, maskedoff5, base, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlseg6e8_v_i8mf4_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], ptr noundef [[V4:%.*]], ptr noundef [[V5:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], [[MASKEDOFF4:%.*]], [[MASKEDOFF5:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vlseg6.mask.nxv2i8.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], [[MASKEDOFF4]], [[MASKEDOFF5]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 1 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 1 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 1 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , } [[TMP0]], 4 +// CHECK-RV64-NEXT: store [[TMP5]], ptr [[V4]], align 1 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , } [[TMP0]], 5 +// CHECK-RV64-NEXT: store [[TMP6]], ptr [[V5]], align 1 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg6e8_v_i8mf4_mu(vint8mf4_t *v0, vint8mf4_t *v1, vint8mf4_t *v2, vint8mf4_t *v3, vint8mf4_t *v4, vint8mf4_t *v5, vbool32_t mask, vint8mf4_t maskedoff0, vint8mf4_t maskedoff1, vint8mf4_t maskedoff2, vint8mf4_t maskedoff3, vint8mf4_t maskedoff4, vint8mf4_t maskedoff5, const int8_t *base, size_t vl) { + return __riscv_vlseg6e8_mu(v0, v1, v2, v3, v4, v5, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, maskedoff4, maskedoff5, base, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlseg6e8_v_i8mf2_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], ptr noundef [[V4:%.*]], ptr noundef [[V5:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], [[MASKEDOFF4:%.*]], [[MASKEDOFF5:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vlseg6.mask.nxv4i8.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], [[MASKEDOFF4]], [[MASKEDOFF5]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 1 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 1 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 1 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , } [[TMP0]], 4 +// CHECK-RV64-NEXT: store [[TMP5]], ptr [[V4]], align 1 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , } [[TMP0]], 5 +// CHECK-RV64-NEXT: store [[TMP6]], ptr [[V5]], align 1 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg6e8_v_i8mf2_mu(vint8mf2_t *v0, vint8mf2_t *v1, vint8mf2_t *v2, vint8mf2_t *v3, vint8mf2_t *v4, vint8mf2_t *v5, vbool16_t mask, vint8mf2_t maskedoff0, vint8mf2_t maskedoff1, vint8mf2_t maskedoff2, vint8mf2_t maskedoff3, vint8mf2_t maskedoff4, vint8mf2_t maskedoff5, const int8_t *base, size_t vl) { + return __riscv_vlseg6e8_mu(v0, v1, v2, v3, v4, v5, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, maskedoff4, maskedoff5, base, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlseg6e8_v_i8m1_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], ptr noundef [[V4:%.*]], ptr noundef [[V5:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], [[MASKEDOFF4:%.*]], [[MASKEDOFF5:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vlseg6.mask.nxv8i8.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], [[MASKEDOFF4]], [[MASKEDOFF5]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 1 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 1 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 1 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , } [[TMP0]], 4 +// CHECK-RV64-NEXT: store [[TMP5]], ptr [[V4]], align 1 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , } [[TMP0]], 5 +// CHECK-RV64-NEXT: store [[TMP6]], ptr [[V5]], align 1 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg6e8_v_i8m1_mu(vint8m1_t *v0, vint8m1_t *v1, vint8m1_t *v2, vint8m1_t *v3, vint8m1_t *v4, vint8m1_t *v5, vbool8_t mask, vint8m1_t maskedoff0, vint8m1_t maskedoff1, vint8m1_t maskedoff2, vint8m1_t maskedoff3, vint8m1_t maskedoff4, vint8m1_t maskedoff5, const int8_t *base, size_t vl) { + return __riscv_vlseg6e8_mu(v0, v1, v2, v3, v4, v5, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, maskedoff4, maskedoff5, base, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlseg6e8_v_u8mf8_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], ptr noundef [[V4:%.*]], ptr noundef [[V5:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], [[MASKEDOFF4:%.*]], [[MASKEDOFF5:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vlseg6.mask.nxv1i8.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], [[MASKEDOFF4]], [[MASKEDOFF5]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 1 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 1 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 1 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , } [[TMP0]], 4 +// CHECK-RV64-NEXT: store [[TMP5]], ptr [[V4]], align 1 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , } [[TMP0]], 5 +// CHECK-RV64-NEXT: store [[TMP6]], ptr [[V5]], align 1 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg6e8_v_u8mf8_mu(vuint8mf8_t *v0, vuint8mf8_t *v1, vuint8mf8_t *v2, vuint8mf8_t *v3, vuint8mf8_t *v4, vuint8mf8_t *v5, vbool64_t mask, vuint8mf8_t maskedoff0, vuint8mf8_t maskedoff1, vuint8mf8_t maskedoff2, vuint8mf8_t maskedoff3, vuint8mf8_t maskedoff4, vuint8mf8_t maskedoff5, const uint8_t *base, size_t vl) { + return __riscv_vlseg6e8_mu(v0, v1, v2, v3, v4, v5, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, maskedoff4, maskedoff5, base, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlseg6e8_v_u8mf4_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], ptr noundef [[V4:%.*]], ptr noundef [[V5:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], [[MASKEDOFF4:%.*]], [[MASKEDOFF5:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vlseg6.mask.nxv2i8.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], [[MASKEDOFF4]], [[MASKEDOFF5]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 1 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 1 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 1 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , } [[TMP0]], 4 +// CHECK-RV64-NEXT: store [[TMP5]], ptr [[V4]], align 1 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , } [[TMP0]], 5 +// CHECK-RV64-NEXT: store [[TMP6]], ptr [[V5]], align 1 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg6e8_v_u8mf4_mu(vuint8mf4_t *v0, vuint8mf4_t *v1, vuint8mf4_t *v2, vuint8mf4_t *v3, vuint8mf4_t *v4, vuint8mf4_t *v5, vbool32_t mask, vuint8mf4_t maskedoff0, vuint8mf4_t maskedoff1, vuint8mf4_t maskedoff2, vuint8mf4_t maskedoff3, vuint8mf4_t maskedoff4, vuint8mf4_t maskedoff5, const uint8_t *base, size_t vl) { + return __riscv_vlseg6e8_mu(v0, v1, v2, v3, v4, v5, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, maskedoff4, maskedoff5, base, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlseg6e8_v_u8mf2_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], ptr noundef [[V4:%.*]], ptr noundef [[V5:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], [[MASKEDOFF4:%.*]], [[MASKEDOFF5:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vlseg6.mask.nxv4i8.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], [[MASKEDOFF4]], [[MASKEDOFF5]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 1 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 1 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 1 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , } [[TMP0]], 4 +// CHECK-RV64-NEXT: store [[TMP5]], ptr [[V4]], align 1 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , } [[TMP0]], 5 +// CHECK-RV64-NEXT: store [[TMP6]], ptr [[V5]], align 1 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg6e8_v_u8mf2_mu(vuint8mf2_t *v0, vuint8mf2_t *v1, vuint8mf2_t *v2, vuint8mf2_t *v3, vuint8mf2_t *v4, vuint8mf2_t *v5, vbool16_t mask, vuint8mf2_t maskedoff0, vuint8mf2_t maskedoff1, vuint8mf2_t maskedoff2, vuint8mf2_t maskedoff3, vuint8mf2_t maskedoff4, vuint8mf2_t maskedoff5, const uint8_t *base, size_t vl) { + return __riscv_vlseg6e8_mu(v0, v1, v2, v3, v4, v5, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, maskedoff4, maskedoff5, base, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlseg6e8_v_u8m1_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], ptr noundef [[V4:%.*]], ptr noundef [[V5:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], [[MASKEDOFF4:%.*]], [[MASKEDOFF5:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vlseg6.mask.nxv8i8.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], [[MASKEDOFF4]], [[MASKEDOFF5]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 1 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 1 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 1 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , } [[TMP0]], 4 +// CHECK-RV64-NEXT: store [[TMP5]], ptr [[V4]], align 1 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , } [[TMP0]], 5 +// CHECK-RV64-NEXT: store [[TMP6]], ptr [[V5]], align 1 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg6e8_v_u8m1_mu(vuint8m1_t *v0, vuint8m1_t *v1, vuint8m1_t *v2, vuint8m1_t *v3, vuint8m1_t *v4, vuint8m1_t *v5, vbool8_t mask, vuint8m1_t maskedoff0, vuint8m1_t maskedoff1, vuint8m1_t maskedoff2, vuint8m1_t maskedoff3, vuint8m1_t maskedoff4, vuint8m1_t maskedoff5, const uint8_t *base, size_t vl) { + return __riscv_vlseg6e8_mu(v0, v1, v2, v3, v4, v5, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, maskedoff4, maskedoff5, base, vl); +} + diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e8ff.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e8ff.c index 07cfe823f5f52..b7c177a1ef751 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e8ff.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e8ff.c @@ -583,3 +583,195 @@ void test_vlseg6e8ff_v_u8m1_tumu(vuint8m1_t *v0, vuint8m1_t *v1, vuint8m1_t *v2, return __riscv_vlseg6e8ff_tumu(v0, v1, v2, v3, v4, v5, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, maskedoff4, maskedoff5, base, new_vl, vl); } +// CHECK-RV64-LABEL: define dso_local void @test_vlseg6e8ff_v_i8mf8_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], ptr noundef [[V4:%.*]], ptr noundef [[V5:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], [[MASKEDOFF4:%.*]], [[MASKEDOFF5:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , i64 } @llvm.riscv.vlseg6ff.mask.nxv1i8.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], [[MASKEDOFF4]], [[MASKEDOFF5]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 1 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 1 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , i64 } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 1 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , i64 } [[TMP0]], 4 +// CHECK-RV64-NEXT: store [[TMP5]], ptr [[V4]], align 1 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , i64 } [[TMP0]], 5 +// CHECK-RV64-NEXT: store [[TMP6]], ptr [[V5]], align 1 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , i64 } [[TMP0]], 6 +// CHECK-RV64-NEXT: store i64 [[TMP7]], ptr [[NEW_VL]], align 1 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg6e8ff_v_i8mf8_mu(vint8mf8_t *v0, vint8mf8_t *v1, vint8mf8_t *v2, vint8mf8_t *v3, vint8mf8_t *v4, vint8mf8_t *v5, vbool64_t mask, vint8mf8_t maskedoff0, vint8mf8_t maskedoff1, vint8mf8_t maskedoff2, vint8mf8_t maskedoff3, vint8mf8_t maskedoff4, vint8mf8_t maskedoff5, const int8_t *base, size_t *new_vl, size_t vl) { + return __riscv_vlseg6e8ff_mu(v0, v1, v2, v3, v4, v5, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, maskedoff4, maskedoff5, base, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlseg6e8ff_v_i8mf4_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], ptr noundef [[V4:%.*]], ptr noundef [[V5:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], [[MASKEDOFF4:%.*]], [[MASKEDOFF5:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , i64 } @llvm.riscv.vlseg6ff.mask.nxv2i8.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], [[MASKEDOFF4]], [[MASKEDOFF5]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 1 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 1 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , i64 } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 1 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , i64 } [[TMP0]], 4 +// CHECK-RV64-NEXT: store [[TMP5]], ptr [[V4]], align 1 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , i64 } [[TMP0]], 5 +// CHECK-RV64-NEXT: store [[TMP6]], ptr [[V5]], align 1 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , i64 } [[TMP0]], 6 +// CHECK-RV64-NEXT: store i64 [[TMP7]], ptr [[NEW_VL]], align 1 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg6e8ff_v_i8mf4_mu(vint8mf4_t *v0, vint8mf4_t *v1, vint8mf4_t *v2, vint8mf4_t *v3, vint8mf4_t *v4, vint8mf4_t *v5, vbool32_t mask, vint8mf4_t maskedoff0, vint8mf4_t maskedoff1, vint8mf4_t maskedoff2, vint8mf4_t maskedoff3, vint8mf4_t maskedoff4, vint8mf4_t maskedoff5, const int8_t *base, size_t *new_vl, size_t vl) { + return __riscv_vlseg6e8ff_mu(v0, v1, v2, v3, v4, v5, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, maskedoff4, maskedoff5, base, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlseg6e8ff_v_i8mf2_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], ptr noundef [[V4:%.*]], ptr noundef [[V5:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], [[MASKEDOFF4:%.*]], [[MASKEDOFF5:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , i64 } @llvm.riscv.vlseg6ff.mask.nxv4i8.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], [[MASKEDOFF4]], [[MASKEDOFF5]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 1 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 1 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , i64 } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 1 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , i64 } [[TMP0]], 4 +// CHECK-RV64-NEXT: store [[TMP5]], ptr [[V4]], align 1 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , i64 } [[TMP0]], 5 +// CHECK-RV64-NEXT: store [[TMP6]], ptr [[V5]], align 1 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , i64 } [[TMP0]], 6 +// CHECK-RV64-NEXT: store i64 [[TMP7]], ptr [[NEW_VL]], align 1 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg6e8ff_v_i8mf2_mu(vint8mf2_t *v0, vint8mf2_t *v1, vint8mf2_t *v2, vint8mf2_t *v3, vint8mf2_t *v4, vint8mf2_t *v5, vbool16_t mask, vint8mf2_t maskedoff0, vint8mf2_t maskedoff1, vint8mf2_t maskedoff2, vint8mf2_t maskedoff3, vint8mf2_t maskedoff4, vint8mf2_t maskedoff5, const int8_t *base, size_t *new_vl, size_t vl) { + return __riscv_vlseg6e8ff_mu(v0, v1, v2, v3, v4, v5, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, maskedoff4, maskedoff5, base, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlseg6e8ff_v_i8m1_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], ptr noundef [[V4:%.*]], ptr noundef [[V5:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], [[MASKEDOFF4:%.*]], [[MASKEDOFF5:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , i64 } @llvm.riscv.vlseg6ff.mask.nxv8i8.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], [[MASKEDOFF4]], [[MASKEDOFF5]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 1 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 1 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , i64 } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 1 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , i64 } [[TMP0]], 4 +// CHECK-RV64-NEXT: store [[TMP5]], ptr [[V4]], align 1 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , i64 } [[TMP0]], 5 +// CHECK-RV64-NEXT: store [[TMP6]], ptr [[V5]], align 1 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , i64 } [[TMP0]], 6 +// CHECK-RV64-NEXT: store i64 [[TMP7]], ptr [[NEW_VL]], align 1 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg6e8ff_v_i8m1_mu(vint8m1_t *v0, vint8m1_t *v1, vint8m1_t *v2, vint8m1_t *v3, vint8m1_t *v4, vint8m1_t *v5, vbool8_t mask, vint8m1_t maskedoff0, vint8m1_t maskedoff1, vint8m1_t maskedoff2, vint8m1_t maskedoff3, vint8m1_t maskedoff4, vint8m1_t maskedoff5, const int8_t *base, size_t *new_vl, size_t vl) { + return __riscv_vlseg6e8ff_mu(v0, v1, v2, v3, v4, v5, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, maskedoff4, maskedoff5, base, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlseg6e8ff_v_u8mf8_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], ptr noundef [[V4:%.*]], ptr noundef [[V5:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], [[MASKEDOFF4:%.*]], [[MASKEDOFF5:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , i64 } @llvm.riscv.vlseg6ff.mask.nxv1i8.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], [[MASKEDOFF4]], [[MASKEDOFF5]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 1 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 1 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , i64 } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 1 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , i64 } [[TMP0]], 4 +// CHECK-RV64-NEXT: store [[TMP5]], ptr [[V4]], align 1 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , i64 } [[TMP0]], 5 +// CHECK-RV64-NEXT: store [[TMP6]], ptr [[V5]], align 1 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , i64 } [[TMP0]], 6 +// CHECK-RV64-NEXT: store i64 [[TMP7]], ptr [[NEW_VL]], align 1 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg6e8ff_v_u8mf8_mu(vuint8mf8_t *v0, vuint8mf8_t *v1, vuint8mf8_t *v2, vuint8mf8_t *v3, vuint8mf8_t *v4, vuint8mf8_t *v5, vbool64_t mask, vuint8mf8_t maskedoff0, vuint8mf8_t maskedoff1, vuint8mf8_t maskedoff2, vuint8mf8_t maskedoff3, vuint8mf8_t maskedoff4, vuint8mf8_t maskedoff5, const uint8_t *base, size_t *new_vl, size_t vl) { + return __riscv_vlseg6e8ff_mu(v0, v1, v2, v3, v4, v5, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, maskedoff4, maskedoff5, base, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlseg6e8ff_v_u8mf4_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], ptr noundef [[V4:%.*]], ptr noundef [[V5:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], [[MASKEDOFF4:%.*]], [[MASKEDOFF5:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , i64 } @llvm.riscv.vlseg6ff.mask.nxv2i8.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], [[MASKEDOFF4]], [[MASKEDOFF5]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 1 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 1 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , i64 } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 1 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , i64 } [[TMP0]], 4 +// CHECK-RV64-NEXT: store [[TMP5]], ptr [[V4]], align 1 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , i64 } [[TMP0]], 5 +// CHECK-RV64-NEXT: store [[TMP6]], ptr [[V5]], align 1 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , i64 } [[TMP0]], 6 +// CHECK-RV64-NEXT: store i64 [[TMP7]], ptr [[NEW_VL]], align 1 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg6e8ff_v_u8mf4_mu(vuint8mf4_t *v0, vuint8mf4_t *v1, vuint8mf4_t *v2, vuint8mf4_t *v3, vuint8mf4_t *v4, vuint8mf4_t *v5, vbool32_t mask, vuint8mf4_t maskedoff0, vuint8mf4_t maskedoff1, vuint8mf4_t maskedoff2, vuint8mf4_t maskedoff3, vuint8mf4_t maskedoff4, vuint8mf4_t maskedoff5, const uint8_t *base, size_t *new_vl, size_t vl) { + return __riscv_vlseg6e8ff_mu(v0, v1, v2, v3, v4, v5, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, maskedoff4, maskedoff5, base, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlseg6e8ff_v_u8mf2_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], ptr noundef [[V4:%.*]], ptr noundef [[V5:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], [[MASKEDOFF4:%.*]], [[MASKEDOFF5:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , i64 } @llvm.riscv.vlseg6ff.mask.nxv4i8.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], [[MASKEDOFF4]], [[MASKEDOFF5]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 1 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 1 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , i64 } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 1 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , i64 } [[TMP0]], 4 +// CHECK-RV64-NEXT: store [[TMP5]], ptr [[V4]], align 1 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , i64 } [[TMP0]], 5 +// CHECK-RV64-NEXT: store [[TMP6]], ptr [[V5]], align 1 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , i64 } [[TMP0]], 6 +// CHECK-RV64-NEXT: store i64 [[TMP7]], ptr [[NEW_VL]], align 1 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg6e8ff_v_u8mf2_mu(vuint8mf2_t *v0, vuint8mf2_t *v1, vuint8mf2_t *v2, vuint8mf2_t *v3, vuint8mf2_t *v4, vuint8mf2_t *v5, vbool16_t mask, vuint8mf2_t maskedoff0, vuint8mf2_t maskedoff1, vuint8mf2_t maskedoff2, vuint8mf2_t maskedoff3, vuint8mf2_t maskedoff4, vuint8mf2_t maskedoff5, const uint8_t *base, size_t *new_vl, size_t vl) { + return __riscv_vlseg6e8ff_mu(v0, v1, v2, v3, v4, v5, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, maskedoff4, maskedoff5, base, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlseg6e8ff_v_u8m1_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], ptr noundef [[V4:%.*]], ptr noundef [[V5:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], [[MASKEDOFF4:%.*]], [[MASKEDOFF5:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , i64 } @llvm.riscv.vlseg6ff.mask.nxv8i8.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], [[MASKEDOFF4]], [[MASKEDOFF5]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 1 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 1 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , i64 } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 1 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , i64 } [[TMP0]], 4 +// CHECK-RV64-NEXT: store [[TMP5]], ptr [[V4]], align 1 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , i64 } [[TMP0]], 5 +// CHECK-RV64-NEXT: store [[TMP6]], ptr [[V5]], align 1 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , i64 } [[TMP0]], 6 +// CHECK-RV64-NEXT: store i64 [[TMP7]], ptr [[NEW_VL]], align 1 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg6e8ff_v_u8m1_mu(vuint8m1_t *v0, vuint8m1_t *v1, vuint8m1_t *v2, vuint8m1_t *v3, vuint8m1_t *v4, vuint8m1_t *v5, vbool8_t mask, vuint8m1_t maskedoff0, vuint8m1_t maskedoff1, vuint8m1_t maskedoff2, vuint8m1_t maskedoff3, vuint8m1_t maskedoff4, vuint8m1_t maskedoff5, const uint8_t *base, size_t *new_vl, size_t vl) { + return __riscv_vlseg6e8ff_mu(v0, v1, v2, v3, v4, v5, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, maskedoff4, maskedoff5, base, new_vl, vl); +} + diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e16.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e16.c index ed6068459544a..2d46494f1e1fd 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e16.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e16.c @@ -655,3 +655,219 @@ void test_vlseg7e16_v_u16m1_tumu(vuint16m1_t *v0, vuint16m1_t *v1, vuint16m1_t * return __riscv_vlseg7e16_tumu(v0, v1, v2, v3, v4, v5, v6, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, maskedoff4, maskedoff5, maskedoff6, base, vl); } +// CHECK-RV64-LABEL: define dso_local void @test_vlseg7e16_v_f16mf4_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], ptr noundef [[V4:%.*]], ptr noundef [[V5:%.*]], ptr noundef [[V6:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], [[MASKEDOFF4:%.*]], [[MASKEDOFF5:%.*]], [[MASKEDOFF6:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vlseg7.mask.nxv1f16.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], [[MASKEDOFF4]], [[MASKEDOFF5]], [[MASKEDOFF6]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 2 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 2 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 2 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , } [[TMP0]], 4 +// CHECK-RV64-NEXT: store [[TMP5]], ptr [[V4]], align 2 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , } [[TMP0]], 5 +// CHECK-RV64-NEXT: store [[TMP6]], ptr [[V5]], align 2 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , } [[TMP0]], 6 +// CHECK-RV64-NEXT: store [[TMP7]], ptr [[V6]], align 2 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg7e16_v_f16mf4_mu(vfloat16mf4_t *v0, vfloat16mf4_t *v1, vfloat16mf4_t *v2, vfloat16mf4_t *v3, vfloat16mf4_t *v4, vfloat16mf4_t *v5, vfloat16mf4_t *v6, vbool64_t mask, vfloat16mf4_t maskedoff0, vfloat16mf4_t maskedoff1, vfloat16mf4_t maskedoff2, vfloat16mf4_t maskedoff3, vfloat16mf4_t maskedoff4, vfloat16mf4_t maskedoff5, vfloat16mf4_t maskedoff6, const _Float16 *base, size_t vl) { + return __riscv_vlseg7e16_mu(v0, v1, v2, v3, v4, v5, v6, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, maskedoff4, maskedoff5, maskedoff6, base, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlseg7e16_v_f16mf2_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], ptr noundef [[V4:%.*]], ptr noundef [[V5:%.*]], ptr noundef [[V6:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], [[MASKEDOFF4:%.*]], [[MASKEDOFF5:%.*]], [[MASKEDOFF6:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vlseg7.mask.nxv2f16.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], [[MASKEDOFF4]], [[MASKEDOFF5]], [[MASKEDOFF6]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 2 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 2 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 2 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , } [[TMP0]], 4 +// CHECK-RV64-NEXT: store [[TMP5]], ptr [[V4]], align 2 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , } [[TMP0]], 5 +// CHECK-RV64-NEXT: store [[TMP6]], ptr [[V5]], align 2 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , } [[TMP0]], 6 +// CHECK-RV64-NEXT: store [[TMP7]], ptr [[V6]], align 2 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg7e16_v_f16mf2_mu(vfloat16mf2_t *v0, vfloat16mf2_t *v1, vfloat16mf2_t *v2, vfloat16mf2_t *v3, vfloat16mf2_t *v4, vfloat16mf2_t *v5, vfloat16mf2_t *v6, vbool32_t mask, vfloat16mf2_t maskedoff0, vfloat16mf2_t maskedoff1, vfloat16mf2_t maskedoff2, vfloat16mf2_t maskedoff3, vfloat16mf2_t maskedoff4, vfloat16mf2_t maskedoff5, vfloat16mf2_t maskedoff6, const _Float16 *base, size_t vl) { + return __riscv_vlseg7e16_mu(v0, v1, v2, v3, v4, v5, v6, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, maskedoff4, maskedoff5, maskedoff6, base, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlseg7e16_v_f16m1_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], ptr noundef [[V4:%.*]], ptr noundef [[V5:%.*]], ptr noundef [[V6:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], [[MASKEDOFF4:%.*]], [[MASKEDOFF5:%.*]], [[MASKEDOFF6:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vlseg7.mask.nxv4f16.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], [[MASKEDOFF4]], [[MASKEDOFF5]], [[MASKEDOFF6]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 2 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 2 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 2 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , } [[TMP0]], 4 +// CHECK-RV64-NEXT: store [[TMP5]], ptr [[V4]], align 2 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , } [[TMP0]], 5 +// CHECK-RV64-NEXT: store [[TMP6]], ptr [[V5]], align 2 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , } [[TMP0]], 6 +// CHECK-RV64-NEXT: store [[TMP7]], ptr [[V6]], align 2 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg7e16_v_f16m1_mu(vfloat16m1_t *v0, vfloat16m1_t *v1, vfloat16m1_t *v2, vfloat16m1_t *v3, vfloat16m1_t *v4, vfloat16m1_t *v5, vfloat16m1_t *v6, vbool16_t mask, vfloat16m1_t maskedoff0, vfloat16m1_t maskedoff1, vfloat16m1_t maskedoff2, vfloat16m1_t maskedoff3, vfloat16m1_t maskedoff4, vfloat16m1_t maskedoff5, vfloat16m1_t maskedoff6, const _Float16 *base, size_t vl) { + return __riscv_vlseg7e16_mu(v0, v1, v2, v3, v4, v5, v6, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, maskedoff4, maskedoff5, maskedoff6, base, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlseg7e16_v_i16mf4_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], ptr noundef [[V4:%.*]], ptr noundef [[V5:%.*]], ptr noundef [[V6:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], [[MASKEDOFF4:%.*]], [[MASKEDOFF5:%.*]], [[MASKEDOFF6:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vlseg7.mask.nxv1i16.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], [[MASKEDOFF4]], [[MASKEDOFF5]], [[MASKEDOFF6]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 2 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 2 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 2 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , } [[TMP0]], 4 +// CHECK-RV64-NEXT: store [[TMP5]], ptr [[V4]], align 2 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , } [[TMP0]], 5 +// CHECK-RV64-NEXT: store [[TMP6]], ptr [[V5]], align 2 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , } [[TMP0]], 6 +// CHECK-RV64-NEXT: store [[TMP7]], ptr [[V6]], align 2 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg7e16_v_i16mf4_mu(vint16mf4_t *v0, vint16mf4_t *v1, vint16mf4_t *v2, vint16mf4_t *v3, vint16mf4_t *v4, vint16mf4_t *v5, vint16mf4_t *v6, vbool64_t mask, vint16mf4_t maskedoff0, vint16mf4_t maskedoff1, vint16mf4_t maskedoff2, vint16mf4_t maskedoff3, vint16mf4_t maskedoff4, vint16mf4_t maskedoff5, vint16mf4_t maskedoff6, const int16_t *base, size_t vl) { + return __riscv_vlseg7e16_mu(v0, v1, v2, v3, v4, v5, v6, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, maskedoff4, maskedoff5, maskedoff6, base, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlseg7e16_v_i16mf2_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], ptr noundef [[V4:%.*]], ptr noundef [[V5:%.*]], ptr noundef [[V6:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], [[MASKEDOFF4:%.*]], [[MASKEDOFF5:%.*]], [[MASKEDOFF6:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vlseg7.mask.nxv2i16.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], [[MASKEDOFF4]], [[MASKEDOFF5]], [[MASKEDOFF6]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 2 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 2 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 2 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , } [[TMP0]], 4 +// CHECK-RV64-NEXT: store [[TMP5]], ptr [[V4]], align 2 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , } [[TMP0]], 5 +// CHECK-RV64-NEXT: store [[TMP6]], ptr [[V5]], align 2 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , } [[TMP0]], 6 +// CHECK-RV64-NEXT: store [[TMP7]], ptr [[V6]], align 2 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg7e16_v_i16mf2_mu(vint16mf2_t *v0, vint16mf2_t *v1, vint16mf2_t *v2, vint16mf2_t *v3, vint16mf2_t *v4, vint16mf2_t *v5, vint16mf2_t *v6, vbool32_t mask, vint16mf2_t maskedoff0, vint16mf2_t maskedoff1, vint16mf2_t maskedoff2, vint16mf2_t maskedoff3, vint16mf2_t maskedoff4, vint16mf2_t maskedoff5, vint16mf2_t maskedoff6, const int16_t *base, size_t vl) { + return __riscv_vlseg7e16_mu(v0, v1, v2, v3, v4, v5, v6, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, maskedoff4, maskedoff5, maskedoff6, base, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlseg7e16_v_i16m1_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], ptr noundef [[V4:%.*]], ptr noundef [[V5:%.*]], ptr noundef [[V6:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], [[MASKEDOFF4:%.*]], [[MASKEDOFF5:%.*]], [[MASKEDOFF6:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vlseg7.mask.nxv4i16.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], [[MASKEDOFF4]], [[MASKEDOFF5]], [[MASKEDOFF6]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 2 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 2 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 2 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , } [[TMP0]], 4 +// CHECK-RV64-NEXT: store [[TMP5]], ptr [[V4]], align 2 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , } [[TMP0]], 5 +// CHECK-RV64-NEXT: store [[TMP6]], ptr [[V5]], align 2 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , } [[TMP0]], 6 +// CHECK-RV64-NEXT: store [[TMP7]], ptr [[V6]], align 2 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg7e16_v_i16m1_mu(vint16m1_t *v0, vint16m1_t *v1, vint16m1_t *v2, vint16m1_t *v3, vint16m1_t *v4, vint16m1_t *v5, vint16m1_t *v6, vbool16_t mask, vint16m1_t maskedoff0, vint16m1_t maskedoff1, vint16m1_t maskedoff2, vint16m1_t maskedoff3, vint16m1_t maskedoff4, vint16m1_t maskedoff5, vint16m1_t maskedoff6, const int16_t *base, size_t vl) { + return __riscv_vlseg7e16_mu(v0, v1, v2, v3, v4, v5, v6, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, maskedoff4, maskedoff5, maskedoff6, base, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlseg7e16_v_u16mf4_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], ptr noundef [[V4:%.*]], ptr noundef [[V5:%.*]], ptr noundef [[V6:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], [[MASKEDOFF4:%.*]], [[MASKEDOFF5:%.*]], [[MASKEDOFF6:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vlseg7.mask.nxv1i16.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], [[MASKEDOFF4]], [[MASKEDOFF5]], [[MASKEDOFF6]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 2 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 2 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 2 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , } [[TMP0]], 4 +// CHECK-RV64-NEXT: store [[TMP5]], ptr [[V4]], align 2 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , } [[TMP0]], 5 +// CHECK-RV64-NEXT: store [[TMP6]], ptr [[V5]], align 2 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , } [[TMP0]], 6 +// CHECK-RV64-NEXT: store [[TMP7]], ptr [[V6]], align 2 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg7e16_v_u16mf4_mu(vuint16mf4_t *v0, vuint16mf4_t *v1, vuint16mf4_t *v2, vuint16mf4_t *v3, vuint16mf4_t *v4, vuint16mf4_t *v5, vuint16mf4_t *v6, vbool64_t mask, vuint16mf4_t maskedoff0, vuint16mf4_t maskedoff1, vuint16mf4_t maskedoff2, vuint16mf4_t maskedoff3, vuint16mf4_t maskedoff4, vuint16mf4_t maskedoff5, vuint16mf4_t maskedoff6, const uint16_t *base, size_t vl) { + return __riscv_vlseg7e16_mu(v0, v1, v2, v3, v4, v5, v6, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, maskedoff4, maskedoff5, maskedoff6, base, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlseg7e16_v_u16mf2_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], ptr noundef [[V4:%.*]], ptr noundef [[V5:%.*]], ptr noundef [[V6:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], [[MASKEDOFF4:%.*]], [[MASKEDOFF5:%.*]], [[MASKEDOFF6:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vlseg7.mask.nxv2i16.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], [[MASKEDOFF4]], [[MASKEDOFF5]], [[MASKEDOFF6]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 2 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 2 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 2 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , } [[TMP0]], 4 +// CHECK-RV64-NEXT: store [[TMP5]], ptr [[V4]], align 2 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , } [[TMP0]], 5 +// CHECK-RV64-NEXT: store [[TMP6]], ptr [[V5]], align 2 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , } [[TMP0]], 6 +// CHECK-RV64-NEXT: store [[TMP7]], ptr [[V6]], align 2 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg7e16_v_u16mf2_mu(vuint16mf2_t *v0, vuint16mf2_t *v1, vuint16mf2_t *v2, vuint16mf2_t *v3, vuint16mf2_t *v4, vuint16mf2_t *v5, vuint16mf2_t *v6, vbool32_t mask, vuint16mf2_t maskedoff0, vuint16mf2_t maskedoff1, vuint16mf2_t maskedoff2, vuint16mf2_t maskedoff3, vuint16mf2_t maskedoff4, vuint16mf2_t maskedoff5, vuint16mf2_t maskedoff6, const uint16_t *base, size_t vl) { + return __riscv_vlseg7e16_mu(v0, v1, v2, v3, v4, v5, v6, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, maskedoff4, maskedoff5, maskedoff6, base, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlseg7e16_v_u16m1_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], ptr noundef [[V4:%.*]], ptr noundef [[V5:%.*]], ptr noundef [[V6:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], [[MASKEDOFF4:%.*]], [[MASKEDOFF5:%.*]], [[MASKEDOFF6:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vlseg7.mask.nxv4i16.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], [[MASKEDOFF4]], [[MASKEDOFF5]], [[MASKEDOFF6]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 2 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 2 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 2 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , } [[TMP0]], 4 +// CHECK-RV64-NEXT: store [[TMP5]], ptr [[V4]], align 2 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , } [[TMP0]], 5 +// CHECK-RV64-NEXT: store [[TMP6]], ptr [[V5]], align 2 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , } [[TMP0]], 6 +// CHECK-RV64-NEXT: store [[TMP7]], ptr [[V6]], align 2 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg7e16_v_u16m1_mu(vuint16m1_t *v0, vuint16m1_t *v1, vuint16m1_t *v2, vuint16m1_t *v3, vuint16m1_t *v4, vuint16m1_t *v5, vuint16m1_t *v6, vbool16_t mask, vuint16m1_t maskedoff0, vuint16m1_t maskedoff1, vuint16m1_t maskedoff2, vuint16m1_t maskedoff3, vuint16m1_t maskedoff4, vuint16m1_t maskedoff5, vuint16m1_t maskedoff6, const uint16_t *base, size_t vl) { + return __riscv_vlseg7e16_mu(v0, v1, v2, v3, v4, v5, v6, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, maskedoff4, maskedoff5, maskedoff6, base, vl); +} + diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e16ff.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e16ff.c index 8af8a9e4d8bc8..ff0e6dccaf989 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e16ff.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e16ff.c @@ -709,3 +709,237 @@ void test_vlseg7e16ff_v_u16m1_tumu(vuint16m1_t *v0, vuint16m1_t *v1, vuint16m1_t return __riscv_vlseg7e16ff_tumu(v0, v1, v2, v3, v4, v5, v6, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, maskedoff4, maskedoff5, maskedoff6, base, new_vl, vl); } +// CHECK-RV64-LABEL: define dso_local void @test_vlseg7e16ff_v_f16mf4_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], ptr noundef [[V4:%.*]], ptr noundef [[V5:%.*]], ptr noundef [[V6:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], [[MASKEDOFF4:%.*]], [[MASKEDOFF5:%.*]], [[MASKEDOFF6:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , i64 } @llvm.riscv.vlseg7ff.mask.nxv1f16.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], [[MASKEDOFF4]], [[MASKEDOFF5]], [[MASKEDOFF6]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 2 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 2 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 2 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 4 +// CHECK-RV64-NEXT: store [[TMP5]], ptr [[V4]], align 2 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 5 +// CHECK-RV64-NEXT: store [[TMP6]], ptr [[V5]], align 2 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 6 +// CHECK-RV64-NEXT: store [[TMP7]], ptr [[V6]], align 2 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 7 +// CHECK-RV64-NEXT: store i64 [[TMP8]], ptr [[NEW_VL]], align 2 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg7e16ff_v_f16mf4_mu(vfloat16mf4_t *v0, vfloat16mf4_t *v1, vfloat16mf4_t *v2, vfloat16mf4_t *v3, vfloat16mf4_t *v4, vfloat16mf4_t *v5, vfloat16mf4_t *v6, vbool64_t mask, vfloat16mf4_t maskedoff0, vfloat16mf4_t maskedoff1, vfloat16mf4_t maskedoff2, vfloat16mf4_t maskedoff3, vfloat16mf4_t maskedoff4, vfloat16mf4_t maskedoff5, vfloat16mf4_t maskedoff6, const _Float16 *base, size_t *new_vl, size_t vl) { + return __riscv_vlseg7e16ff_mu(v0, v1, v2, v3, v4, v5, v6, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, maskedoff4, maskedoff5, maskedoff6, base, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlseg7e16ff_v_f16mf2_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], ptr noundef [[V4:%.*]], ptr noundef [[V5:%.*]], ptr noundef [[V6:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], [[MASKEDOFF4:%.*]], [[MASKEDOFF5:%.*]], [[MASKEDOFF6:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , i64 } @llvm.riscv.vlseg7ff.mask.nxv2f16.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], [[MASKEDOFF4]], [[MASKEDOFF5]], [[MASKEDOFF6]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 2 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 2 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 2 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 4 +// CHECK-RV64-NEXT: store [[TMP5]], ptr [[V4]], align 2 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 5 +// CHECK-RV64-NEXT: store [[TMP6]], ptr [[V5]], align 2 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 6 +// CHECK-RV64-NEXT: store [[TMP7]], ptr [[V6]], align 2 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 7 +// CHECK-RV64-NEXT: store i64 [[TMP8]], ptr [[NEW_VL]], align 2 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg7e16ff_v_f16mf2_mu(vfloat16mf2_t *v0, vfloat16mf2_t *v1, vfloat16mf2_t *v2, vfloat16mf2_t *v3, vfloat16mf2_t *v4, vfloat16mf2_t *v5, vfloat16mf2_t *v6, vbool32_t mask, vfloat16mf2_t maskedoff0, vfloat16mf2_t maskedoff1, vfloat16mf2_t maskedoff2, vfloat16mf2_t maskedoff3, vfloat16mf2_t maskedoff4, vfloat16mf2_t maskedoff5, vfloat16mf2_t maskedoff6, const _Float16 *base, size_t *new_vl, size_t vl) { + return __riscv_vlseg7e16ff_mu(v0, v1, v2, v3, v4, v5, v6, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, maskedoff4, maskedoff5, maskedoff6, base, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlseg7e16ff_v_f16m1_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], ptr noundef [[V4:%.*]], ptr noundef [[V5:%.*]], ptr noundef [[V6:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], [[MASKEDOFF4:%.*]], [[MASKEDOFF5:%.*]], [[MASKEDOFF6:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , i64 } @llvm.riscv.vlseg7ff.mask.nxv4f16.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], [[MASKEDOFF4]], [[MASKEDOFF5]], [[MASKEDOFF6]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 2 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 2 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 2 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 4 +// CHECK-RV64-NEXT: store [[TMP5]], ptr [[V4]], align 2 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 5 +// CHECK-RV64-NEXT: store [[TMP6]], ptr [[V5]], align 2 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 6 +// CHECK-RV64-NEXT: store [[TMP7]], ptr [[V6]], align 2 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 7 +// CHECK-RV64-NEXT: store i64 [[TMP8]], ptr [[NEW_VL]], align 2 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg7e16ff_v_f16m1_mu(vfloat16m1_t *v0, vfloat16m1_t *v1, vfloat16m1_t *v2, vfloat16m1_t *v3, vfloat16m1_t *v4, vfloat16m1_t *v5, vfloat16m1_t *v6, vbool16_t mask, vfloat16m1_t maskedoff0, vfloat16m1_t maskedoff1, vfloat16m1_t maskedoff2, vfloat16m1_t maskedoff3, vfloat16m1_t maskedoff4, vfloat16m1_t maskedoff5, vfloat16m1_t maskedoff6, const _Float16 *base, size_t *new_vl, size_t vl) { + return __riscv_vlseg7e16ff_mu(v0, v1, v2, v3, v4, v5, v6, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, maskedoff4, maskedoff5, maskedoff6, base, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlseg7e16ff_v_i16mf4_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], ptr noundef [[V4:%.*]], ptr noundef [[V5:%.*]], ptr noundef [[V6:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], [[MASKEDOFF4:%.*]], [[MASKEDOFF5:%.*]], [[MASKEDOFF6:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , i64 } @llvm.riscv.vlseg7ff.mask.nxv1i16.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], [[MASKEDOFF4]], [[MASKEDOFF5]], [[MASKEDOFF6]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 2 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 2 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 2 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 4 +// CHECK-RV64-NEXT: store [[TMP5]], ptr [[V4]], align 2 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 5 +// CHECK-RV64-NEXT: store [[TMP6]], ptr [[V5]], align 2 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 6 +// CHECK-RV64-NEXT: store [[TMP7]], ptr [[V6]], align 2 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 7 +// CHECK-RV64-NEXT: store i64 [[TMP8]], ptr [[NEW_VL]], align 2 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg7e16ff_v_i16mf4_mu(vint16mf4_t *v0, vint16mf4_t *v1, vint16mf4_t *v2, vint16mf4_t *v3, vint16mf4_t *v4, vint16mf4_t *v5, vint16mf4_t *v6, vbool64_t mask, vint16mf4_t maskedoff0, vint16mf4_t maskedoff1, vint16mf4_t maskedoff2, vint16mf4_t maskedoff3, vint16mf4_t maskedoff4, vint16mf4_t maskedoff5, vint16mf4_t maskedoff6, const int16_t *base, size_t *new_vl, size_t vl) { + return __riscv_vlseg7e16ff_mu(v0, v1, v2, v3, v4, v5, v6, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, maskedoff4, maskedoff5, maskedoff6, base, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlseg7e16ff_v_i16mf2_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], ptr noundef [[V4:%.*]], ptr noundef [[V5:%.*]], ptr noundef [[V6:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], [[MASKEDOFF4:%.*]], [[MASKEDOFF5:%.*]], [[MASKEDOFF6:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , i64 } @llvm.riscv.vlseg7ff.mask.nxv2i16.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], [[MASKEDOFF4]], [[MASKEDOFF5]], [[MASKEDOFF6]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 2 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 2 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 2 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 4 +// CHECK-RV64-NEXT: store [[TMP5]], ptr [[V4]], align 2 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 5 +// CHECK-RV64-NEXT: store [[TMP6]], ptr [[V5]], align 2 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 6 +// CHECK-RV64-NEXT: store [[TMP7]], ptr [[V6]], align 2 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 7 +// CHECK-RV64-NEXT: store i64 [[TMP8]], ptr [[NEW_VL]], align 2 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg7e16ff_v_i16mf2_mu(vint16mf2_t *v0, vint16mf2_t *v1, vint16mf2_t *v2, vint16mf2_t *v3, vint16mf2_t *v4, vint16mf2_t *v5, vint16mf2_t *v6, vbool32_t mask, vint16mf2_t maskedoff0, vint16mf2_t maskedoff1, vint16mf2_t maskedoff2, vint16mf2_t maskedoff3, vint16mf2_t maskedoff4, vint16mf2_t maskedoff5, vint16mf2_t maskedoff6, const int16_t *base, size_t *new_vl, size_t vl) { + return __riscv_vlseg7e16ff_mu(v0, v1, v2, v3, v4, v5, v6, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, maskedoff4, maskedoff5, maskedoff6, base, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlseg7e16ff_v_i16m1_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], ptr noundef [[V4:%.*]], ptr noundef [[V5:%.*]], ptr noundef [[V6:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], [[MASKEDOFF4:%.*]], [[MASKEDOFF5:%.*]], [[MASKEDOFF6:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , i64 } @llvm.riscv.vlseg7ff.mask.nxv4i16.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], [[MASKEDOFF4]], [[MASKEDOFF5]], [[MASKEDOFF6]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 2 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 2 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 2 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 4 +// CHECK-RV64-NEXT: store [[TMP5]], ptr [[V4]], align 2 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 5 +// CHECK-RV64-NEXT: store [[TMP6]], ptr [[V5]], align 2 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 6 +// CHECK-RV64-NEXT: store [[TMP7]], ptr [[V6]], align 2 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 7 +// CHECK-RV64-NEXT: store i64 [[TMP8]], ptr [[NEW_VL]], align 2 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg7e16ff_v_i16m1_mu(vint16m1_t *v0, vint16m1_t *v1, vint16m1_t *v2, vint16m1_t *v3, vint16m1_t *v4, vint16m1_t *v5, vint16m1_t *v6, vbool16_t mask, vint16m1_t maskedoff0, vint16m1_t maskedoff1, vint16m1_t maskedoff2, vint16m1_t maskedoff3, vint16m1_t maskedoff4, vint16m1_t maskedoff5, vint16m1_t maskedoff6, const int16_t *base, size_t *new_vl, size_t vl) { + return __riscv_vlseg7e16ff_mu(v0, v1, v2, v3, v4, v5, v6, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, maskedoff4, maskedoff5, maskedoff6, base, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlseg7e16ff_v_u16mf4_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], ptr noundef [[V4:%.*]], ptr noundef [[V5:%.*]], ptr noundef [[V6:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], [[MASKEDOFF4:%.*]], [[MASKEDOFF5:%.*]], [[MASKEDOFF6:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , i64 } @llvm.riscv.vlseg7ff.mask.nxv1i16.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], [[MASKEDOFF4]], [[MASKEDOFF5]], [[MASKEDOFF6]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 2 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 2 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 2 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 4 +// CHECK-RV64-NEXT: store [[TMP5]], ptr [[V4]], align 2 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 5 +// CHECK-RV64-NEXT: store [[TMP6]], ptr [[V5]], align 2 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 6 +// CHECK-RV64-NEXT: store [[TMP7]], ptr [[V6]], align 2 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 7 +// CHECK-RV64-NEXT: store i64 [[TMP8]], ptr [[NEW_VL]], align 2 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg7e16ff_v_u16mf4_mu(vuint16mf4_t *v0, vuint16mf4_t *v1, vuint16mf4_t *v2, vuint16mf4_t *v3, vuint16mf4_t *v4, vuint16mf4_t *v5, vuint16mf4_t *v6, vbool64_t mask, vuint16mf4_t maskedoff0, vuint16mf4_t maskedoff1, vuint16mf4_t maskedoff2, vuint16mf4_t maskedoff3, vuint16mf4_t maskedoff4, vuint16mf4_t maskedoff5, vuint16mf4_t maskedoff6, const uint16_t *base, size_t *new_vl, size_t vl) { + return __riscv_vlseg7e16ff_mu(v0, v1, v2, v3, v4, v5, v6, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, maskedoff4, maskedoff5, maskedoff6, base, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlseg7e16ff_v_u16mf2_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], ptr noundef [[V4:%.*]], ptr noundef [[V5:%.*]], ptr noundef [[V6:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], [[MASKEDOFF4:%.*]], [[MASKEDOFF5:%.*]], [[MASKEDOFF6:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , i64 } @llvm.riscv.vlseg7ff.mask.nxv2i16.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], [[MASKEDOFF4]], [[MASKEDOFF5]], [[MASKEDOFF6]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 2 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 2 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 2 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 4 +// CHECK-RV64-NEXT: store [[TMP5]], ptr [[V4]], align 2 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 5 +// CHECK-RV64-NEXT: store [[TMP6]], ptr [[V5]], align 2 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 6 +// CHECK-RV64-NEXT: store [[TMP7]], ptr [[V6]], align 2 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 7 +// CHECK-RV64-NEXT: store i64 [[TMP8]], ptr [[NEW_VL]], align 2 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg7e16ff_v_u16mf2_mu(vuint16mf2_t *v0, vuint16mf2_t *v1, vuint16mf2_t *v2, vuint16mf2_t *v3, vuint16mf2_t *v4, vuint16mf2_t *v5, vuint16mf2_t *v6, vbool32_t mask, vuint16mf2_t maskedoff0, vuint16mf2_t maskedoff1, vuint16mf2_t maskedoff2, vuint16mf2_t maskedoff3, vuint16mf2_t maskedoff4, vuint16mf2_t maskedoff5, vuint16mf2_t maskedoff6, const uint16_t *base, size_t *new_vl, size_t vl) { + return __riscv_vlseg7e16ff_mu(v0, v1, v2, v3, v4, v5, v6, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, maskedoff4, maskedoff5, maskedoff6, base, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlseg7e16ff_v_u16m1_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], ptr noundef [[V4:%.*]], ptr noundef [[V5:%.*]], ptr noundef [[V6:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], [[MASKEDOFF4:%.*]], [[MASKEDOFF5:%.*]], [[MASKEDOFF6:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , i64 } @llvm.riscv.vlseg7ff.mask.nxv4i16.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], [[MASKEDOFF4]], [[MASKEDOFF5]], [[MASKEDOFF6]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 2 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 2 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 2 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 4 +// CHECK-RV64-NEXT: store [[TMP5]], ptr [[V4]], align 2 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 5 +// CHECK-RV64-NEXT: store [[TMP6]], ptr [[V5]], align 2 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 6 +// CHECK-RV64-NEXT: store [[TMP7]], ptr [[V6]], align 2 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 7 +// CHECK-RV64-NEXT: store i64 [[TMP8]], ptr [[NEW_VL]], align 2 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg7e16ff_v_u16m1_mu(vuint16m1_t *v0, vuint16m1_t *v1, vuint16m1_t *v2, vuint16m1_t *v3, vuint16m1_t *v4, vuint16m1_t *v5, vuint16m1_t *v6, vbool16_t mask, vuint16m1_t maskedoff0, vuint16m1_t maskedoff1, vuint16m1_t maskedoff2, vuint16m1_t maskedoff3, vuint16m1_t maskedoff4, vuint16m1_t maskedoff5, vuint16m1_t maskedoff6, const uint16_t *base, size_t *new_vl, size_t vl) { + return __riscv_vlseg7e16ff_mu(v0, v1, v2, v3, v4, v5, v6, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, maskedoff4, maskedoff5, maskedoff6, base, new_vl, vl); +} + diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e32.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e32.c index 2fff47f923a3f..5ebb288dcf97e 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e32.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e32.c @@ -439,3 +439,147 @@ void test_vlseg7e32_v_u32m1_tumu(vuint32m1_t *v0, vuint32m1_t *v1, vuint32m1_t * return __riscv_vlseg7e32_tumu(v0, v1, v2, v3, v4, v5, v6, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, maskedoff4, maskedoff5, maskedoff6, base, vl); } +// CHECK-RV64-LABEL: define dso_local void @test_vlseg7e32_v_f32mf2_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], ptr noundef [[V4:%.*]], ptr noundef [[V5:%.*]], ptr noundef [[V6:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], [[MASKEDOFF4:%.*]], [[MASKEDOFF5:%.*]], [[MASKEDOFF6:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vlseg7.mask.nxv1f32.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], [[MASKEDOFF4]], [[MASKEDOFF5]], [[MASKEDOFF6]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 4 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 4 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 4 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , } [[TMP0]], 4 +// CHECK-RV64-NEXT: store [[TMP5]], ptr [[V4]], align 4 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , } [[TMP0]], 5 +// CHECK-RV64-NEXT: store [[TMP6]], ptr [[V5]], align 4 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , } [[TMP0]], 6 +// CHECK-RV64-NEXT: store [[TMP7]], ptr [[V6]], align 4 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg7e32_v_f32mf2_mu(vfloat32mf2_t *v0, vfloat32mf2_t *v1, vfloat32mf2_t *v2, vfloat32mf2_t *v3, vfloat32mf2_t *v4, vfloat32mf2_t *v5, vfloat32mf2_t *v6, vbool64_t mask, vfloat32mf2_t maskedoff0, vfloat32mf2_t maskedoff1, vfloat32mf2_t maskedoff2, vfloat32mf2_t maskedoff3, vfloat32mf2_t maskedoff4, vfloat32mf2_t maskedoff5, vfloat32mf2_t maskedoff6, const float *base, size_t vl) { + return __riscv_vlseg7e32_mu(v0, v1, v2, v3, v4, v5, v6, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, maskedoff4, maskedoff5, maskedoff6, base, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlseg7e32_v_f32m1_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], ptr noundef [[V4:%.*]], ptr noundef [[V5:%.*]], ptr noundef [[V6:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], [[MASKEDOFF4:%.*]], [[MASKEDOFF5:%.*]], [[MASKEDOFF6:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vlseg7.mask.nxv2f32.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], [[MASKEDOFF4]], [[MASKEDOFF5]], [[MASKEDOFF6]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 4 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 4 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 4 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , } [[TMP0]], 4 +// CHECK-RV64-NEXT: store [[TMP5]], ptr [[V4]], align 4 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , } [[TMP0]], 5 +// CHECK-RV64-NEXT: store [[TMP6]], ptr [[V5]], align 4 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , } [[TMP0]], 6 +// CHECK-RV64-NEXT: store [[TMP7]], ptr [[V6]], align 4 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg7e32_v_f32m1_mu(vfloat32m1_t *v0, vfloat32m1_t *v1, vfloat32m1_t *v2, vfloat32m1_t *v3, vfloat32m1_t *v4, vfloat32m1_t *v5, vfloat32m1_t *v6, vbool32_t mask, vfloat32m1_t maskedoff0, vfloat32m1_t maskedoff1, vfloat32m1_t maskedoff2, vfloat32m1_t maskedoff3, vfloat32m1_t maskedoff4, vfloat32m1_t maskedoff5, vfloat32m1_t maskedoff6, const float *base, size_t vl) { + return __riscv_vlseg7e32_mu(v0, v1, v2, v3, v4, v5, v6, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, maskedoff4, maskedoff5, maskedoff6, base, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlseg7e32_v_i32mf2_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], ptr noundef [[V4:%.*]], ptr noundef [[V5:%.*]], ptr noundef [[V6:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], [[MASKEDOFF4:%.*]], [[MASKEDOFF5:%.*]], [[MASKEDOFF6:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vlseg7.mask.nxv1i32.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], [[MASKEDOFF4]], [[MASKEDOFF5]], [[MASKEDOFF6]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 4 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 4 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 4 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , } [[TMP0]], 4 +// CHECK-RV64-NEXT: store [[TMP5]], ptr [[V4]], align 4 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , } [[TMP0]], 5 +// CHECK-RV64-NEXT: store [[TMP6]], ptr [[V5]], align 4 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , } [[TMP0]], 6 +// CHECK-RV64-NEXT: store [[TMP7]], ptr [[V6]], align 4 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg7e32_v_i32mf2_mu(vint32mf2_t *v0, vint32mf2_t *v1, vint32mf2_t *v2, vint32mf2_t *v3, vint32mf2_t *v4, vint32mf2_t *v5, vint32mf2_t *v6, vbool64_t mask, vint32mf2_t maskedoff0, vint32mf2_t maskedoff1, vint32mf2_t maskedoff2, vint32mf2_t maskedoff3, vint32mf2_t maskedoff4, vint32mf2_t maskedoff5, vint32mf2_t maskedoff6, const int32_t *base, size_t vl) { + return __riscv_vlseg7e32_mu(v0, v1, v2, v3, v4, v5, v6, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, maskedoff4, maskedoff5, maskedoff6, base, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlseg7e32_v_i32m1_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], ptr noundef [[V4:%.*]], ptr noundef [[V5:%.*]], ptr noundef [[V6:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], [[MASKEDOFF4:%.*]], [[MASKEDOFF5:%.*]], [[MASKEDOFF6:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vlseg7.mask.nxv2i32.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], [[MASKEDOFF4]], [[MASKEDOFF5]], [[MASKEDOFF6]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 4 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 4 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 4 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , } [[TMP0]], 4 +// CHECK-RV64-NEXT: store [[TMP5]], ptr [[V4]], align 4 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , } [[TMP0]], 5 +// CHECK-RV64-NEXT: store [[TMP6]], ptr [[V5]], align 4 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , } [[TMP0]], 6 +// CHECK-RV64-NEXT: store [[TMP7]], ptr [[V6]], align 4 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg7e32_v_i32m1_mu(vint32m1_t *v0, vint32m1_t *v1, vint32m1_t *v2, vint32m1_t *v3, vint32m1_t *v4, vint32m1_t *v5, vint32m1_t *v6, vbool32_t mask, vint32m1_t maskedoff0, vint32m1_t maskedoff1, vint32m1_t maskedoff2, vint32m1_t maskedoff3, vint32m1_t maskedoff4, vint32m1_t maskedoff5, vint32m1_t maskedoff6, const int32_t *base, size_t vl) { + return __riscv_vlseg7e32_mu(v0, v1, v2, v3, v4, v5, v6, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, maskedoff4, maskedoff5, maskedoff6, base, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlseg7e32_v_u32mf2_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], ptr noundef [[V4:%.*]], ptr noundef [[V5:%.*]], ptr noundef [[V6:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], [[MASKEDOFF4:%.*]], [[MASKEDOFF5:%.*]], [[MASKEDOFF6:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vlseg7.mask.nxv1i32.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], [[MASKEDOFF4]], [[MASKEDOFF5]], [[MASKEDOFF6]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 4 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 4 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 4 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , } [[TMP0]], 4 +// CHECK-RV64-NEXT: store [[TMP5]], ptr [[V4]], align 4 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , } [[TMP0]], 5 +// CHECK-RV64-NEXT: store [[TMP6]], ptr [[V5]], align 4 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , } [[TMP0]], 6 +// CHECK-RV64-NEXT: store [[TMP7]], ptr [[V6]], align 4 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg7e32_v_u32mf2_mu(vuint32mf2_t *v0, vuint32mf2_t *v1, vuint32mf2_t *v2, vuint32mf2_t *v3, vuint32mf2_t *v4, vuint32mf2_t *v5, vuint32mf2_t *v6, vbool64_t mask, vuint32mf2_t maskedoff0, vuint32mf2_t maskedoff1, vuint32mf2_t maskedoff2, vuint32mf2_t maskedoff3, vuint32mf2_t maskedoff4, vuint32mf2_t maskedoff5, vuint32mf2_t maskedoff6, const uint32_t *base, size_t vl) { + return __riscv_vlseg7e32_mu(v0, v1, v2, v3, v4, v5, v6, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, maskedoff4, maskedoff5, maskedoff6, base, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlseg7e32_v_u32m1_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], ptr noundef [[V4:%.*]], ptr noundef [[V5:%.*]], ptr noundef [[V6:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], [[MASKEDOFF4:%.*]], [[MASKEDOFF5:%.*]], [[MASKEDOFF6:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vlseg7.mask.nxv2i32.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], [[MASKEDOFF4]], [[MASKEDOFF5]], [[MASKEDOFF6]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 4 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 4 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 4 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , } [[TMP0]], 4 +// CHECK-RV64-NEXT: store [[TMP5]], ptr [[V4]], align 4 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , } [[TMP0]], 5 +// CHECK-RV64-NEXT: store [[TMP6]], ptr [[V5]], align 4 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , } [[TMP0]], 6 +// CHECK-RV64-NEXT: store [[TMP7]], ptr [[V6]], align 4 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg7e32_v_u32m1_mu(vuint32m1_t *v0, vuint32m1_t *v1, vuint32m1_t *v2, vuint32m1_t *v3, vuint32m1_t *v4, vuint32m1_t *v5, vuint32m1_t *v6, vbool32_t mask, vuint32m1_t maskedoff0, vuint32m1_t maskedoff1, vuint32m1_t maskedoff2, vuint32m1_t maskedoff3, vuint32m1_t maskedoff4, vuint32m1_t maskedoff5, vuint32m1_t maskedoff6, const uint32_t *base, size_t vl) { + return __riscv_vlseg7e32_mu(v0, v1, v2, v3, v4, v5, v6, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, maskedoff4, maskedoff5, maskedoff6, base, vl); +} + diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e32ff.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e32ff.c index 22cbbf225770f..a5897f3f8dcba 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e32ff.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e32ff.c @@ -475,3 +475,159 @@ void test_vlseg7e32ff_v_u32m1_tumu(vuint32m1_t *v0, vuint32m1_t *v1, vuint32m1_t return __riscv_vlseg7e32ff_tumu(v0, v1, v2, v3, v4, v5, v6, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, maskedoff4, maskedoff5, maskedoff6, base, new_vl, vl); } +// CHECK-RV64-LABEL: define dso_local void @test_vlseg7e32ff_v_f32mf2_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], ptr noundef [[V4:%.*]], ptr noundef [[V5:%.*]], ptr noundef [[V6:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], [[MASKEDOFF4:%.*]], [[MASKEDOFF5:%.*]], [[MASKEDOFF6:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , i64 } @llvm.riscv.vlseg7ff.mask.nxv1f32.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], [[MASKEDOFF4]], [[MASKEDOFF5]], [[MASKEDOFF6]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 4 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 4 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 4 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 4 +// CHECK-RV64-NEXT: store [[TMP5]], ptr [[V4]], align 4 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 5 +// CHECK-RV64-NEXT: store [[TMP6]], ptr [[V5]], align 4 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 6 +// CHECK-RV64-NEXT: store [[TMP7]], ptr [[V6]], align 4 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 7 +// CHECK-RV64-NEXT: store i64 [[TMP8]], ptr [[NEW_VL]], align 4 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg7e32ff_v_f32mf2_mu(vfloat32mf2_t *v0, vfloat32mf2_t *v1, vfloat32mf2_t *v2, vfloat32mf2_t *v3, vfloat32mf2_t *v4, vfloat32mf2_t *v5, vfloat32mf2_t *v6, vbool64_t mask, vfloat32mf2_t maskedoff0, vfloat32mf2_t maskedoff1, vfloat32mf2_t maskedoff2, vfloat32mf2_t maskedoff3, vfloat32mf2_t maskedoff4, vfloat32mf2_t maskedoff5, vfloat32mf2_t maskedoff6, const float *base, size_t *new_vl, size_t vl) { + return __riscv_vlseg7e32ff_mu(v0, v1, v2, v3, v4, v5, v6, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, maskedoff4, maskedoff5, maskedoff6, base, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlseg7e32ff_v_f32m1_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], ptr noundef [[V4:%.*]], ptr noundef [[V5:%.*]], ptr noundef [[V6:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], [[MASKEDOFF4:%.*]], [[MASKEDOFF5:%.*]], [[MASKEDOFF6:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , i64 } @llvm.riscv.vlseg7ff.mask.nxv2f32.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], [[MASKEDOFF4]], [[MASKEDOFF5]], [[MASKEDOFF6]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 4 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 4 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 4 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 4 +// CHECK-RV64-NEXT: store [[TMP5]], ptr [[V4]], align 4 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 5 +// CHECK-RV64-NEXT: store [[TMP6]], ptr [[V5]], align 4 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 6 +// CHECK-RV64-NEXT: store [[TMP7]], ptr [[V6]], align 4 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 7 +// CHECK-RV64-NEXT: store i64 [[TMP8]], ptr [[NEW_VL]], align 4 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg7e32ff_v_f32m1_mu(vfloat32m1_t *v0, vfloat32m1_t *v1, vfloat32m1_t *v2, vfloat32m1_t *v3, vfloat32m1_t *v4, vfloat32m1_t *v5, vfloat32m1_t *v6, vbool32_t mask, vfloat32m1_t maskedoff0, vfloat32m1_t maskedoff1, vfloat32m1_t maskedoff2, vfloat32m1_t maskedoff3, vfloat32m1_t maskedoff4, vfloat32m1_t maskedoff5, vfloat32m1_t maskedoff6, const float *base, size_t *new_vl, size_t vl) { + return __riscv_vlseg7e32ff_mu(v0, v1, v2, v3, v4, v5, v6, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, maskedoff4, maskedoff5, maskedoff6, base, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlseg7e32ff_v_i32mf2_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], ptr noundef [[V4:%.*]], ptr noundef [[V5:%.*]], ptr noundef [[V6:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], [[MASKEDOFF4:%.*]], [[MASKEDOFF5:%.*]], [[MASKEDOFF6:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , i64 } @llvm.riscv.vlseg7ff.mask.nxv1i32.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], [[MASKEDOFF4]], [[MASKEDOFF5]], [[MASKEDOFF6]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 4 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 4 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 4 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 4 +// CHECK-RV64-NEXT: store [[TMP5]], ptr [[V4]], align 4 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 5 +// CHECK-RV64-NEXT: store [[TMP6]], ptr [[V5]], align 4 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 6 +// CHECK-RV64-NEXT: store [[TMP7]], ptr [[V6]], align 4 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 7 +// CHECK-RV64-NEXT: store i64 [[TMP8]], ptr [[NEW_VL]], align 4 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg7e32ff_v_i32mf2_mu(vint32mf2_t *v0, vint32mf2_t *v1, vint32mf2_t *v2, vint32mf2_t *v3, vint32mf2_t *v4, vint32mf2_t *v5, vint32mf2_t *v6, vbool64_t mask, vint32mf2_t maskedoff0, vint32mf2_t maskedoff1, vint32mf2_t maskedoff2, vint32mf2_t maskedoff3, vint32mf2_t maskedoff4, vint32mf2_t maskedoff5, vint32mf2_t maskedoff6, const int32_t *base, size_t *new_vl, size_t vl) { + return __riscv_vlseg7e32ff_mu(v0, v1, v2, v3, v4, v5, v6, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, maskedoff4, maskedoff5, maskedoff6, base, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlseg7e32ff_v_i32m1_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], ptr noundef [[V4:%.*]], ptr noundef [[V5:%.*]], ptr noundef [[V6:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], [[MASKEDOFF4:%.*]], [[MASKEDOFF5:%.*]], [[MASKEDOFF6:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , i64 } @llvm.riscv.vlseg7ff.mask.nxv2i32.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], [[MASKEDOFF4]], [[MASKEDOFF5]], [[MASKEDOFF6]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 4 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 4 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 4 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 4 +// CHECK-RV64-NEXT: store [[TMP5]], ptr [[V4]], align 4 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 5 +// CHECK-RV64-NEXT: store [[TMP6]], ptr [[V5]], align 4 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 6 +// CHECK-RV64-NEXT: store [[TMP7]], ptr [[V6]], align 4 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 7 +// CHECK-RV64-NEXT: store i64 [[TMP8]], ptr [[NEW_VL]], align 4 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg7e32ff_v_i32m1_mu(vint32m1_t *v0, vint32m1_t *v1, vint32m1_t *v2, vint32m1_t *v3, vint32m1_t *v4, vint32m1_t *v5, vint32m1_t *v6, vbool32_t mask, vint32m1_t maskedoff0, vint32m1_t maskedoff1, vint32m1_t maskedoff2, vint32m1_t maskedoff3, vint32m1_t maskedoff4, vint32m1_t maskedoff5, vint32m1_t maskedoff6, const int32_t *base, size_t *new_vl, size_t vl) { + return __riscv_vlseg7e32ff_mu(v0, v1, v2, v3, v4, v5, v6, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, maskedoff4, maskedoff5, maskedoff6, base, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlseg7e32ff_v_u32mf2_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], ptr noundef [[V4:%.*]], ptr noundef [[V5:%.*]], ptr noundef [[V6:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], [[MASKEDOFF4:%.*]], [[MASKEDOFF5:%.*]], [[MASKEDOFF6:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , i64 } @llvm.riscv.vlseg7ff.mask.nxv1i32.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], [[MASKEDOFF4]], [[MASKEDOFF5]], [[MASKEDOFF6]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 4 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 4 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 4 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 4 +// CHECK-RV64-NEXT: store [[TMP5]], ptr [[V4]], align 4 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 5 +// CHECK-RV64-NEXT: store [[TMP6]], ptr [[V5]], align 4 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 6 +// CHECK-RV64-NEXT: store [[TMP7]], ptr [[V6]], align 4 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 7 +// CHECK-RV64-NEXT: store i64 [[TMP8]], ptr [[NEW_VL]], align 4 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg7e32ff_v_u32mf2_mu(vuint32mf2_t *v0, vuint32mf2_t *v1, vuint32mf2_t *v2, vuint32mf2_t *v3, vuint32mf2_t *v4, vuint32mf2_t *v5, vuint32mf2_t *v6, vbool64_t mask, vuint32mf2_t maskedoff0, vuint32mf2_t maskedoff1, vuint32mf2_t maskedoff2, vuint32mf2_t maskedoff3, vuint32mf2_t maskedoff4, vuint32mf2_t maskedoff5, vuint32mf2_t maskedoff6, const uint32_t *base, size_t *new_vl, size_t vl) { + return __riscv_vlseg7e32ff_mu(v0, v1, v2, v3, v4, v5, v6, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, maskedoff4, maskedoff5, maskedoff6, base, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlseg7e32ff_v_u32m1_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], ptr noundef [[V4:%.*]], ptr noundef [[V5:%.*]], ptr noundef [[V6:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], [[MASKEDOFF4:%.*]], [[MASKEDOFF5:%.*]], [[MASKEDOFF6:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , i64 } @llvm.riscv.vlseg7ff.mask.nxv2i32.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], [[MASKEDOFF4]], [[MASKEDOFF5]], [[MASKEDOFF6]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 4 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 4 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 4 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 4 +// CHECK-RV64-NEXT: store [[TMP5]], ptr [[V4]], align 4 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 5 +// CHECK-RV64-NEXT: store [[TMP6]], ptr [[V5]], align 4 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 6 +// CHECK-RV64-NEXT: store [[TMP7]], ptr [[V6]], align 4 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 7 +// CHECK-RV64-NEXT: store i64 [[TMP8]], ptr [[NEW_VL]], align 4 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg7e32ff_v_u32m1_mu(vuint32m1_t *v0, vuint32m1_t *v1, vuint32m1_t *v2, vuint32m1_t *v3, vuint32m1_t *v4, vuint32m1_t *v5, vuint32m1_t *v6, vbool32_t mask, vuint32m1_t maskedoff0, vuint32m1_t maskedoff1, vuint32m1_t maskedoff2, vuint32m1_t maskedoff3, vuint32m1_t maskedoff4, vuint32m1_t maskedoff5, vuint32m1_t maskedoff6, const uint32_t *base, size_t *new_vl, size_t vl) { + return __riscv_vlseg7e32ff_mu(v0, v1, v2, v3, v4, v5, v6, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, maskedoff4, maskedoff5, maskedoff6, base, new_vl, vl); +} + diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e64.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e64.c index 46d503b469a2d..1b956bf640373 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e64.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e64.c @@ -223,3 +223,75 @@ void test_vlseg7e64_v_u64m1_tumu(vuint64m1_t *v0, vuint64m1_t *v1, vuint64m1_t * return __riscv_vlseg7e64_tumu(v0, v1, v2, v3, v4, v5, v6, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, maskedoff4, maskedoff5, maskedoff6, base, vl); } +// CHECK-RV64-LABEL: define dso_local void @test_vlseg7e64_v_f64m1_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], ptr noundef [[V4:%.*]], ptr noundef [[V5:%.*]], ptr noundef [[V6:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], [[MASKEDOFF4:%.*]], [[MASKEDOFF5:%.*]], [[MASKEDOFF6:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vlseg7.mask.nxv1f64.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], [[MASKEDOFF4]], [[MASKEDOFF5]], [[MASKEDOFF6]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 8 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 8 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 8 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 8 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , } [[TMP0]], 4 +// CHECK-RV64-NEXT: store [[TMP5]], ptr [[V4]], align 8 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , } [[TMP0]], 5 +// CHECK-RV64-NEXT: store [[TMP6]], ptr [[V5]], align 8 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , } [[TMP0]], 6 +// CHECK-RV64-NEXT: store [[TMP7]], ptr [[V6]], align 8 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg7e64_v_f64m1_mu(vfloat64m1_t *v0, vfloat64m1_t *v1, vfloat64m1_t *v2, vfloat64m1_t *v3, vfloat64m1_t *v4, vfloat64m1_t *v5, vfloat64m1_t *v6, vbool64_t mask, vfloat64m1_t maskedoff0, vfloat64m1_t maskedoff1, vfloat64m1_t maskedoff2, vfloat64m1_t maskedoff3, vfloat64m1_t maskedoff4, vfloat64m1_t maskedoff5, vfloat64m1_t maskedoff6, const double *base, size_t vl) { + return __riscv_vlseg7e64_mu(v0, v1, v2, v3, v4, v5, v6, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, maskedoff4, maskedoff5, maskedoff6, base, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlseg7e64_v_i64m1_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], ptr noundef [[V4:%.*]], ptr noundef [[V5:%.*]], ptr noundef [[V6:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], [[MASKEDOFF4:%.*]], [[MASKEDOFF5:%.*]], [[MASKEDOFF6:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vlseg7.mask.nxv1i64.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], [[MASKEDOFF4]], [[MASKEDOFF5]], [[MASKEDOFF6]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 8 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 8 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 8 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 8 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , } [[TMP0]], 4 +// CHECK-RV64-NEXT: store [[TMP5]], ptr [[V4]], align 8 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , } [[TMP0]], 5 +// CHECK-RV64-NEXT: store [[TMP6]], ptr [[V5]], align 8 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , } [[TMP0]], 6 +// CHECK-RV64-NEXT: store [[TMP7]], ptr [[V6]], align 8 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg7e64_v_i64m1_mu(vint64m1_t *v0, vint64m1_t *v1, vint64m1_t *v2, vint64m1_t *v3, vint64m1_t *v4, vint64m1_t *v5, vint64m1_t *v6, vbool64_t mask, vint64m1_t maskedoff0, vint64m1_t maskedoff1, vint64m1_t maskedoff2, vint64m1_t maskedoff3, vint64m1_t maskedoff4, vint64m1_t maskedoff5, vint64m1_t maskedoff6, const int64_t *base, size_t vl) { + return __riscv_vlseg7e64_mu(v0, v1, v2, v3, v4, v5, v6, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, maskedoff4, maskedoff5, maskedoff6, base, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlseg7e64_v_u64m1_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], ptr noundef [[V4:%.*]], ptr noundef [[V5:%.*]], ptr noundef [[V6:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], [[MASKEDOFF4:%.*]], [[MASKEDOFF5:%.*]], [[MASKEDOFF6:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vlseg7.mask.nxv1i64.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], [[MASKEDOFF4]], [[MASKEDOFF5]], [[MASKEDOFF6]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 8 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 8 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 8 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 8 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , } [[TMP0]], 4 +// CHECK-RV64-NEXT: store [[TMP5]], ptr [[V4]], align 8 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , } [[TMP0]], 5 +// CHECK-RV64-NEXT: store [[TMP6]], ptr [[V5]], align 8 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , } [[TMP0]], 6 +// CHECK-RV64-NEXT: store [[TMP7]], ptr [[V6]], align 8 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg7e64_v_u64m1_mu(vuint64m1_t *v0, vuint64m1_t *v1, vuint64m1_t *v2, vuint64m1_t *v3, vuint64m1_t *v4, vuint64m1_t *v5, vuint64m1_t *v6, vbool64_t mask, vuint64m1_t maskedoff0, vuint64m1_t maskedoff1, vuint64m1_t maskedoff2, vuint64m1_t maskedoff3, vuint64m1_t maskedoff4, vuint64m1_t maskedoff5, vuint64m1_t maskedoff6, const uint64_t *base, size_t vl) { + return __riscv_vlseg7e64_mu(v0, v1, v2, v3, v4, v5, v6, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, maskedoff4, maskedoff5, maskedoff6, base, vl); +} + diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e64ff.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e64ff.c index eddc77e147386..0c1ac1d3b7ffe 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e64ff.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e64ff.c @@ -241,3 +241,81 @@ void test_vlseg7e64ff_v_u64m1_tumu(vuint64m1_t *v0, vuint64m1_t *v1, vuint64m1_t return __riscv_vlseg7e64ff_tumu(v0, v1, v2, v3, v4, v5, v6, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, maskedoff4, maskedoff5, maskedoff6, base, new_vl, vl); } +// CHECK-RV64-LABEL: define dso_local void @test_vlseg7e64ff_v_f64m1_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], ptr noundef [[V4:%.*]], ptr noundef [[V5:%.*]], ptr noundef [[V6:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], [[MASKEDOFF4:%.*]], [[MASKEDOFF5:%.*]], [[MASKEDOFF6:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , i64 } @llvm.riscv.vlseg7ff.mask.nxv1f64.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], [[MASKEDOFF4]], [[MASKEDOFF5]], [[MASKEDOFF6]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 8 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 8 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 8 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 8 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 4 +// CHECK-RV64-NEXT: store [[TMP5]], ptr [[V4]], align 8 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 5 +// CHECK-RV64-NEXT: store [[TMP6]], ptr [[V5]], align 8 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 6 +// CHECK-RV64-NEXT: store [[TMP7]], ptr [[V6]], align 8 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 7 +// CHECK-RV64-NEXT: store i64 [[TMP8]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg7e64ff_v_f64m1_mu(vfloat64m1_t *v0, vfloat64m1_t *v1, vfloat64m1_t *v2, vfloat64m1_t *v3, vfloat64m1_t *v4, vfloat64m1_t *v5, vfloat64m1_t *v6, vbool64_t mask, vfloat64m1_t maskedoff0, vfloat64m1_t maskedoff1, vfloat64m1_t maskedoff2, vfloat64m1_t maskedoff3, vfloat64m1_t maskedoff4, vfloat64m1_t maskedoff5, vfloat64m1_t maskedoff6, const double *base, size_t *new_vl, size_t vl) { + return __riscv_vlseg7e64ff_mu(v0, v1, v2, v3, v4, v5, v6, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, maskedoff4, maskedoff5, maskedoff6, base, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlseg7e64ff_v_i64m1_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], ptr noundef [[V4:%.*]], ptr noundef [[V5:%.*]], ptr noundef [[V6:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], [[MASKEDOFF4:%.*]], [[MASKEDOFF5:%.*]], [[MASKEDOFF6:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , i64 } @llvm.riscv.vlseg7ff.mask.nxv1i64.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], [[MASKEDOFF4]], [[MASKEDOFF5]], [[MASKEDOFF6]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 8 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 8 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 8 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 8 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 4 +// CHECK-RV64-NEXT: store [[TMP5]], ptr [[V4]], align 8 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 5 +// CHECK-RV64-NEXT: store [[TMP6]], ptr [[V5]], align 8 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 6 +// CHECK-RV64-NEXT: store [[TMP7]], ptr [[V6]], align 8 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 7 +// CHECK-RV64-NEXT: store i64 [[TMP8]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg7e64ff_v_i64m1_mu(vint64m1_t *v0, vint64m1_t *v1, vint64m1_t *v2, vint64m1_t *v3, vint64m1_t *v4, vint64m1_t *v5, vint64m1_t *v6, vbool64_t mask, vint64m1_t maskedoff0, vint64m1_t maskedoff1, vint64m1_t maskedoff2, vint64m1_t maskedoff3, vint64m1_t maskedoff4, vint64m1_t maskedoff5, vint64m1_t maskedoff6, const int64_t *base, size_t *new_vl, size_t vl) { + return __riscv_vlseg7e64ff_mu(v0, v1, v2, v3, v4, v5, v6, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, maskedoff4, maskedoff5, maskedoff6, base, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlseg7e64ff_v_u64m1_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], ptr noundef [[V4:%.*]], ptr noundef [[V5:%.*]], ptr noundef [[V6:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], [[MASKEDOFF4:%.*]], [[MASKEDOFF5:%.*]], [[MASKEDOFF6:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , i64 } @llvm.riscv.vlseg7ff.mask.nxv1i64.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], [[MASKEDOFF4]], [[MASKEDOFF5]], [[MASKEDOFF6]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 8 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 8 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 8 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 8 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 4 +// CHECK-RV64-NEXT: store [[TMP5]], ptr [[V4]], align 8 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 5 +// CHECK-RV64-NEXT: store [[TMP6]], ptr [[V5]], align 8 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 6 +// CHECK-RV64-NEXT: store [[TMP7]], ptr [[V6]], align 8 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 7 +// CHECK-RV64-NEXT: store i64 [[TMP8]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg7e64ff_v_u64m1_mu(vuint64m1_t *v0, vuint64m1_t *v1, vuint64m1_t *v2, vuint64m1_t *v3, vuint64m1_t *v4, vuint64m1_t *v5, vuint64m1_t *v6, vbool64_t mask, vuint64m1_t maskedoff0, vuint64m1_t maskedoff1, vuint64m1_t maskedoff2, vuint64m1_t maskedoff3, vuint64m1_t maskedoff4, vuint64m1_t maskedoff5, vuint64m1_t maskedoff6, const uint64_t *base, size_t *new_vl, size_t vl) { + return __riscv_vlseg7e64ff_mu(v0, v1, v2, v3, v4, v5, v6, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, maskedoff4, maskedoff5, maskedoff6, base, new_vl, vl); +} + diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e8.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e8.c index 36a83d5d2e2b9..e870a54fd7dcd 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e8.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e8.c @@ -582,3 +582,195 @@ void test_vlseg7e8_v_u8m1_tumu(vuint8m1_t *v0, vuint8m1_t *v1, vuint8m1_t *v2, v return __riscv_vlseg7e8_tumu(v0, v1, v2, v3, v4, v5, v6, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, maskedoff4, maskedoff5, maskedoff6, base, vl); } +// CHECK-RV64-LABEL: define dso_local void @test_vlseg7e8_v_i8mf8_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], ptr noundef [[V4:%.*]], ptr noundef [[V5:%.*]], ptr noundef [[V6:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], [[MASKEDOFF4:%.*]], [[MASKEDOFF5:%.*]], [[MASKEDOFF6:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vlseg7.mask.nxv1i8.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], [[MASKEDOFF4]], [[MASKEDOFF5]], [[MASKEDOFF6]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 1 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 1 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 1 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , } [[TMP0]], 4 +// CHECK-RV64-NEXT: store [[TMP5]], ptr [[V4]], align 1 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , } [[TMP0]], 5 +// CHECK-RV64-NEXT: store [[TMP6]], ptr [[V5]], align 1 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , } [[TMP0]], 6 +// CHECK-RV64-NEXT: store [[TMP7]], ptr [[V6]], align 1 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg7e8_v_i8mf8_mu(vint8mf8_t *v0, vint8mf8_t *v1, vint8mf8_t *v2, vint8mf8_t *v3, vint8mf8_t *v4, vint8mf8_t *v5, vint8mf8_t *v6, vbool64_t mask, vint8mf8_t maskedoff0, vint8mf8_t maskedoff1, vint8mf8_t maskedoff2, vint8mf8_t maskedoff3, vint8mf8_t maskedoff4, vint8mf8_t maskedoff5, vint8mf8_t maskedoff6, const int8_t *base, size_t vl) { + return __riscv_vlseg7e8_mu(v0, v1, v2, v3, v4, v5, v6, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, maskedoff4, maskedoff5, maskedoff6, base, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlseg7e8_v_i8mf4_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], ptr noundef [[V4:%.*]], ptr noundef [[V5:%.*]], ptr noundef [[V6:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], [[MASKEDOFF4:%.*]], [[MASKEDOFF5:%.*]], [[MASKEDOFF6:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vlseg7.mask.nxv2i8.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], [[MASKEDOFF4]], [[MASKEDOFF5]], [[MASKEDOFF6]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 1 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 1 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 1 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , } [[TMP0]], 4 +// CHECK-RV64-NEXT: store [[TMP5]], ptr [[V4]], align 1 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , } [[TMP0]], 5 +// CHECK-RV64-NEXT: store [[TMP6]], ptr [[V5]], align 1 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , } [[TMP0]], 6 +// CHECK-RV64-NEXT: store [[TMP7]], ptr [[V6]], align 1 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg7e8_v_i8mf4_mu(vint8mf4_t *v0, vint8mf4_t *v1, vint8mf4_t *v2, vint8mf4_t *v3, vint8mf4_t *v4, vint8mf4_t *v5, vint8mf4_t *v6, vbool32_t mask, vint8mf4_t maskedoff0, vint8mf4_t maskedoff1, vint8mf4_t maskedoff2, vint8mf4_t maskedoff3, vint8mf4_t maskedoff4, vint8mf4_t maskedoff5, vint8mf4_t maskedoff6, const int8_t *base, size_t vl) { + return __riscv_vlseg7e8_mu(v0, v1, v2, v3, v4, v5, v6, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, maskedoff4, maskedoff5, maskedoff6, base, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlseg7e8_v_i8mf2_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], ptr noundef [[V4:%.*]], ptr noundef [[V5:%.*]], ptr noundef [[V6:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], [[MASKEDOFF4:%.*]], [[MASKEDOFF5:%.*]], [[MASKEDOFF6:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vlseg7.mask.nxv4i8.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], [[MASKEDOFF4]], [[MASKEDOFF5]], [[MASKEDOFF6]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 1 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 1 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 1 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , } [[TMP0]], 4 +// CHECK-RV64-NEXT: store [[TMP5]], ptr [[V4]], align 1 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , } [[TMP0]], 5 +// CHECK-RV64-NEXT: store [[TMP6]], ptr [[V5]], align 1 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , } [[TMP0]], 6 +// CHECK-RV64-NEXT: store [[TMP7]], ptr [[V6]], align 1 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg7e8_v_i8mf2_mu(vint8mf2_t *v0, vint8mf2_t *v1, vint8mf2_t *v2, vint8mf2_t *v3, vint8mf2_t *v4, vint8mf2_t *v5, vint8mf2_t *v6, vbool16_t mask, vint8mf2_t maskedoff0, vint8mf2_t maskedoff1, vint8mf2_t maskedoff2, vint8mf2_t maskedoff3, vint8mf2_t maskedoff4, vint8mf2_t maskedoff5, vint8mf2_t maskedoff6, const int8_t *base, size_t vl) { + return __riscv_vlseg7e8_mu(v0, v1, v2, v3, v4, v5, v6, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, maskedoff4, maskedoff5, maskedoff6, base, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlseg7e8_v_i8m1_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], ptr noundef [[V4:%.*]], ptr noundef [[V5:%.*]], ptr noundef [[V6:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], [[MASKEDOFF4:%.*]], [[MASKEDOFF5:%.*]], [[MASKEDOFF6:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vlseg7.mask.nxv8i8.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], [[MASKEDOFF4]], [[MASKEDOFF5]], [[MASKEDOFF6]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 1 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 1 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 1 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , } [[TMP0]], 4 +// CHECK-RV64-NEXT: store [[TMP5]], ptr [[V4]], align 1 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , } [[TMP0]], 5 +// CHECK-RV64-NEXT: store [[TMP6]], ptr [[V5]], align 1 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , } [[TMP0]], 6 +// CHECK-RV64-NEXT: store [[TMP7]], ptr [[V6]], align 1 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg7e8_v_i8m1_mu(vint8m1_t *v0, vint8m1_t *v1, vint8m1_t *v2, vint8m1_t *v3, vint8m1_t *v4, vint8m1_t *v5, vint8m1_t *v6, vbool8_t mask, vint8m1_t maskedoff0, vint8m1_t maskedoff1, vint8m1_t maskedoff2, vint8m1_t maskedoff3, vint8m1_t maskedoff4, vint8m1_t maskedoff5, vint8m1_t maskedoff6, const int8_t *base, size_t vl) { + return __riscv_vlseg7e8_mu(v0, v1, v2, v3, v4, v5, v6, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, maskedoff4, maskedoff5, maskedoff6, base, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlseg7e8_v_u8mf8_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], ptr noundef [[V4:%.*]], ptr noundef [[V5:%.*]], ptr noundef [[V6:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], [[MASKEDOFF4:%.*]], [[MASKEDOFF5:%.*]], [[MASKEDOFF6:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vlseg7.mask.nxv1i8.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], [[MASKEDOFF4]], [[MASKEDOFF5]], [[MASKEDOFF6]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 1 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 1 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 1 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , } [[TMP0]], 4 +// CHECK-RV64-NEXT: store [[TMP5]], ptr [[V4]], align 1 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , } [[TMP0]], 5 +// CHECK-RV64-NEXT: store [[TMP6]], ptr [[V5]], align 1 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , } [[TMP0]], 6 +// CHECK-RV64-NEXT: store [[TMP7]], ptr [[V6]], align 1 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg7e8_v_u8mf8_mu(vuint8mf8_t *v0, vuint8mf8_t *v1, vuint8mf8_t *v2, vuint8mf8_t *v3, vuint8mf8_t *v4, vuint8mf8_t *v5, vuint8mf8_t *v6, vbool64_t mask, vuint8mf8_t maskedoff0, vuint8mf8_t maskedoff1, vuint8mf8_t maskedoff2, vuint8mf8_t maskedoff3, vuint8mf8_t maskedoff4, vuint8mf8_t maskedoff5, vuint8mf8_t maskedoff6, const uint8_t *base, size_t vl) { + return __riscv_vlseg7e8_mu(v0, v1, v2, v3, v4, v5, v6, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, maskedoff4, maskedoff5, maskedoff6, base, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlseg7e8_v_u8mf4_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], ptr noundef [[V4:%.*]], ptr noundef [[V5:%.*]], ptr noundef [[V6:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], [[MASKEDOFF4:%.*]], [[MASKEDOFF5:%.*]], [[MASKEDOFF6:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vlseg7.mask.nxv2i8.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], [[MASKEDOFF4]], [[MASKEDOFF5]], [[MASKEDOFF6]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 1 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 1 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 1 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , } [[TMP0]], 4 +// CHECK-RV64-NEXT: store [[TMP5]], ptr [[V4]], align 1 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , } [[TMP0]], 5 +// CHECK-RV64-NEXT: store [[TMP6]], ptr [[V5]], align 1 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , } [[TMP0]], 6 +// CHECK-RV64-NEXT: store [[TMP7]], ptr [[V6]], align 1 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg7e8_v_u8mf4_mu(vuint8mf4_t *v0, vuint8mf4_t *v1, vuint8mf4_t *v2, vuint8mf4_t *v3, vuint8mf4_t *v4, vuint8mf4_t *v5, vuint8mf4_t *v6, vbool32_t mask, vuint8mf4_t maskedoff0, vuint8mf4_t maskedoff1, vuint8mf4_t maskedoff2, vuint8mf4_t maskedoff3, vuint8mf4_t maskedoff4, vuint8mf4_t maskedoff5, vuint8mf4_t maskedoff6, const uint8_t *base, size_t vl) { + return __riscv_vlseg7e8_mu(v0, v1, v2, v3, v4, v5, v6, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, maskedoff4, maskedoff5, maskedoff6, base, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlseg7e8_v_u8mf2_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], ptr noundef [[V4:%.*]], ptr noundef [[V5:%.*]], ptr noundef [[V6:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], [[MASKEDOFF4:%.*]], [[MASKEDOFF5:%.*]], [[MASKEDOFF6:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vlseg7.mask.nxv4i8.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], [[MASKEDOFF4]], [[MASKEDOFF5]], [[MASKEDOFF6]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 1 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 1 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 1 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , } [[TMP0]], 4 +// CHECK-RV64-NEXT: store [[TMP5]], ptr [[V4]], align 1 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , } [[TMP0]], 5 +// CHECK-RV64-NEXT: store [[TMP6]], ptr [[V5]], align 1 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , } [[TMP0]], 6 +// CHECK-RV64-NEXT: store [[TMP7]], ptr [[V6]], align 1 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg7e8_v_u8mf2_mu(vuint8mf2_t *v0, vuint8mf2_t *v1, vuint8mf2_t *v2, vuint8mf2_t *v3, vuint8mf2_t *v4, vuint8mf2_t *v5, vuint8mf2_t *v6, vbool16_t mask, vuint8mf2_t maskedoff0, vuint8mf2_t maskedoff1, vuint8mf2_t maskedoff2, vuint8mf2_t maskedoff3, vuint8mf2_t maskedoff4, vuint8mf2_t maskedoff5, vuint8mf2_t maskedoff6, const uint8_t *base, size_t vl) { + return __riscv_vlseg7e8_mu(v0, v1, v2, v3, v4, v5, v6, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, maskedoff4, maskedoff5, maskedoff6, base, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlseg7e8_v_u8m1_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], ptr noundef [[V4:%.*]], ptr noundef [[V5:%.*]], ptr noundef [[V6:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], [[MASKEDOFF4:%.*]], [[MASKEDOFF5:%.*]], [[MASKEDOFF6:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vlseg7.mask.nxv8i8.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], [[MASKEDOFF4]], [[MASKEDOFF5]], [[MASKEDOFF6]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 1 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 1 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 1 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , } [[TMP0]], 4 +// CHECK-RV64-NEXT: store [[TMP5]], ptr [[V4]], align 1 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , } [[TMP0]], 5 +// CHECK-RV64-NEXT: store [[TMP6]], ptr [[V5]], align 1 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , } [[TMP0]], 6 +// CHECK-RV64-NEXT: store [[TMP7]], ptr [[V6]], align 1 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg7e8_v_u8m1_mu(vuint8m1_t *v0, vuint8m1_t *v1, vuint8m1_t *v2, vuint8m1_t *v3, vuint8m1_t *v4, vuint8m1_t *v5, vuint8m1_t *v6, vbool8_t mask, vuint8m1_t maskedoff0, vuint8m1_t maskedoff1, vuint8m1_t maskedoff2, vuint8m1_t maskedoff3, vuint8m1_t maskedoff4, vuint8m1_t maskedoff5, vuint8m1_t maskedoff6, const uint8_t *base, size_t vl) { + return __riscv_vlseg7e8_mu(v0, v1, v2, v3, v4, v5, v6, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, maskedoff4, maskedoff5, maskedoff6, base, vl); +} + diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e8ff.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e8ff.c index 1cb2d4d7fbeea..3c37942ff505b 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e8ff.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e8ff.c @@ -631,3 +631,211 @@ void test_vlseg7e8ff_v_u8m1_tumu(vuint8m1_t *v0, vuint8m1_t *v1, vuint8m1_t *v2, return __riscv_vlseg7e8ff_tumu(v0, v1, v2, v3, v4, v5, v6, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, maskedoff4, maskedoff5, maskedoff6, base, new_vl, vl); } +// CHECK-RV64-LABEL: define dso_local void @test_vlseg7e8ff_v_i8mf8_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], ptr noundef [[V4:%.*]], ptr noundef [[V5:%.*]], ptr noundef [[V6:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], [[MASKEDOFF4:%.*]], [[MASKEDOFF5:%.*]], [[MASKEDOFF6:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , i64 } @llvm.riscv.vlseg7ff.mask.nxv1i8.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], [[MASKEDOFF4]], [[MASKEDOFF5]], [[MASKEDOFF6]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 1 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 1 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 1 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 4 +// CHECK-RV64-NEXT: store [[TMP5]], ptr [[V4]], align 1 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 5 +// CHECK-RV64-NEXT: store [[TMP6]], ptr [[V5]], align 1 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 6 +// CHECK-RV64-NEXT: store [[TMP7]], ptr [[V6]], align 1 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 7 +// CHECK-RV64-NEXT: store i64 [[TMP8]], ptr [[NEW_VL]], align 1 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg7e8ff_v_i8mf8_mu(vint8mf8_t *v0, vint8mf8_t *v1, vint8mf8_t *v2, vint8mf8_t *v3, vint8mf8_t *v4, vint8mf8_t *v5, vint8mf8_t *v6, vbool64_t mask, vint8mf8_t maskedoff0, vint8mf8_t maskedoff1, vint8mf8_t maskedoff2, vint8mf8_t maskedoff3, vint8mf8_t maskedoff4, vint8mf8_t maskedoff5, vint8mf8_t maskedoff6, const int8_t *base, size_t *new_vl, size_t vl) { + return __riscv_vlseg7e8ff_mu(v0, v1, v2, v3, v4, v5, v6, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, maskedoff4, maskedoff5, maskedoff6, base, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlseg7e8ff_v_i8mf4_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], ptr noundef [[V4:%.*]], ptr noundef [[V5:%.*]], ptr noundef [[V6:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], [[MASKEDOFF4:%.*]], [[MASKEDOFF5:%.*]], [[MASKEDOFF6:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , i64 } @llvm.riscv.vlseg7ff.mask.nxv2i8.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], [[MASKEDOFF4]], [[MASKEDOFF5]], [[MASKEDOFF6]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 1 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 1 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 1 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 4 +// CHECK-RV64-NEXT: store [[TMP5]], ptr [[V4]], align 1 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 5 +// CHECK-RV64-NEXT: store [[TMP6]], ptr [[V5]], align 1 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 6 +// CHECK-RV64-NEXT: store [[TMP7]], ptr [[V6]], align 1 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 7 +// CHECK-RV64-NEXT: store i64 [[TMP8]], ptr [[NEW_VL]], align 1 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg7e8ff_v_i8mf4_mu(vint8mf4_t *v0, vint8mf4_t *v1, vint8mf4_t *v2, vint8mf4_t *v3, vint8mf4_t *v4, vint8mf4_t *v5, vint8mf4_t *v6, vbool32_t mask, vint8mf4_t maskedoff0, vint8mf4_t maskedoff1, vint8mf4_t maskedoff2, vint8mf4_t maskedoff3, vint8mf4_t maskedoff4, vint8mf4_t maskedoff5, vint8mf4_t maskedoff6, const int8_t *base, size_t *new_vl, size_t vl) { + return __riscv_vlseg7e8ff_mu(v0, v1, v2, v3, v4, v5, v6, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, maskedoff4, maskedoff5, maskedoff6, base, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlseg7e8ff_v_i8mf2_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], ptr noundef [[V4:%.*]], ptr noundef [[V5:%.*]], ptr noundef [[V6:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], [[MASKEDOFF4:%.*]], [[MASKEDOFF5:%.*]], [[MASKEDOFF6:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , i64 } @llvm.riscv.vlseg7ff.mask.nxv4i8.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], [[MASKEDOFF4]], [[MASKEDOFF5]], [[MASKEDOFF6]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 1 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 1 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 1 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 4 +// CHECK-RV64-NEXT: store [[TMP5]], ptr [[V4]], align 1 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 5 +// CHECK-RV64-NEXT: store [[TMP6]], ptr [[V5]], align 1 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 6 +// CHECK-RV64-NEXT: store [[TMP7]], ptr [[V6]], align 1 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 7 +// CHECK-RV64-NEXT: store i64 [[TMP8]], ptr [[NEW_VL]], align 1 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg7e8ff_v_i8mf2_mu(vint8mf2_t *v0, vint8mf2_t *v1, vint8mf2_t *v2, vint8mf2_t *v3, vint8mf2_t *v4, vint8mf2_t *v5, vint8mf2_t *v6, vbool16_t mask, vint8mf2_t maskedoff0, vint8mf2_t maskedoff1, vint8mf2_t maskedoff2, vint8mf2_t maskedoff3, vint8mf2_t maskedoff4, vint8mf2_t maskedoff5, vint8mf2_t maskedoff6, const int8_t *base, size_t *new_vl, size_t vl) { + return __riscv_vlseg7e8ff_mu(v0, v1, v2, v3, v4, v5, v6, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, maskedoff4, maskedoff5, maskedoff6, base, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlseg7e8ff_v_i8m1_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], ptr noundef [[V4:%.*]], ptr noundef [[V5:%.*]], ptr noundef [[V6:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], [[MASKEDOFF4:%.*]], [[MASKEDOFF5:%.*]], [[MASKEDOFF6:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , i64 } @llvm.riscv.vlseg7ff.mask.nxv8i8.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], [[MASKEDOFF4]], [[MASKEDOFF5]], [[MASKEDOFF6]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 1 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 1 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 1 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 4 +// CHECK-RV64-NEXT: store [[TMP5]], ptr [[V4]], align 1 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 5 +// CHECK-RV64-NEXT: store [[TMP6]], ptr [[V5]], align 1 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 6 +// CHECK-RV64-NEXT: store [[TMP7]], ptr [[V6]], align 1 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 7 +// CHECK-RV64-NEXT: store i64 [[TMP8]], ptr [[NEW_VL]], align 1 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg7e8ff_v_i8m1_mu(vint8m1_t *v0, vint8m1_t *v1, vint8m1_t *v2, vint8m1_t *v3, vint8m1_t *v4, vint8m1_t *v5, vint8m1_t *v6, vbool8_t mask, vint8m1_t maskedoff0, vint8m1_t maskedoff1, vint8m1_t maskedoff2, vint8m1_t maskedoff3, vint8m1_t maskedoff4, vint8m1_t maskedoff5, vint8m1_t maskedoff6, const int8_t *base, size_t *new_vl, size_t vl) { + return __riscv_vlseg7e8ff_mu(v0, v1, v2, v3, v4, v5, v6, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, maskedoff4, maskedoff5, maskedoff6, base, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlseg7e8ff_v_u8mf8_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], ptr noundef [[V4:%.*]], ptr noundef [[V5:%.*]], ptr noundef [[V6:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], [[MASKEDOFF4:%.*]], [[MASKEDOFF5:%.*]], [[MASKEDOFF6:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , i64 } @llvm.riscv.vlseg7ff.mask.nxv1i8.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], [[MASKEDOFF4]], [[MASKEDOFF5]], [[MASKEDOFF6]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 1 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 1 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 1 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 4 +// CHECK-RV64-NEXT: store [[TMP5]], ptr [[V4]], align 1 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 5 +// CHECK-RV64-NEXT: store [[TMP6]], ptr [[V5]], align 1 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 6 +// CHECK-RV64-NEXT: store [[TMP7]], ptr [[V6]], align 1 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 7 +// CHECK-RV64-NEXT: store i64 [[TMP8]], ptr [[NEW_VL]], align 1 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg7e8ff_v_u8mf8_mu(vuint8mf8_t *v0, vuint8mf8_t *v1, vuint8mf8_t *v2, vuint8mf8_t *v3, vuint8mf8_t *v4, vuint8mf8_t *v5, vuint8mf8_t *v6, vbool64_t mask, vuint8mf8_t maskedoff0, vuint8mf8_t maskedoff1, vuint8mf8_t maskedoff2, vuint8mf8_t maskedoff3, vuint8mf8_t maskedoff4, vuint8mf8_t maskedoff5, vuint8mf8_t maskedoff6, const uint8_t *base, size_t *new_vl, size_t vl) { + return __riscv_vlseg7e8ff_mu(v0, v1, v2, v3, v4, v5, v6, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, maskedoff4, maskedoff5, maskedoff6, base, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlseg7e8ff_v_u8mf4_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], ptr noundef [[V4:%.*]], ptr noundef [[V5:%.*]], ptr noundef [[V6:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], [[MASKEDOFF4:%.*]], [[MASKEDOFF5:%.*]], [[MASKEDOFF6:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , i64 } @llvm.riscv.vlseg7ff.mask.nxv2i8.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], [[MASKEDOFF4]], [[MASKEDOFF5]], [[MASKEDOFF6]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 1 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 1 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 1 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 4 +// CHECK-RV64-NEXT: store [[TMP5]], ptr [[V4]], align 1 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 5 +// CHECK-RV64-NEXT: store [[TMP6]], ptr [[V5]], align 1 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 6 +// CHECK-RV64-NEXT: store [[TMP7]], ptr [[V6]], align 1 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 7 +// CHECK-RV64-NEXT: store i64 [[TMP8]], ptr [[NEW_VL]], align 1 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg7e8ff_v_u8mf4_mu(vuint8mf4_t *v0, vuint8mf4_t *v1, vuint8mf4_t *v2, vuint8mf4_t *v3, vuint8mf4_t *v4, vuint8mf4_t *v5, vuint8mf4_t *v6, vbool32_t mask, vuint8mf4_t maskedoff0, vuint8mf4_t maskedoff1, vuint8mf4_t maskedoff2, vuint8mf4_t maskedoff3, vuint8mf4_t maskedoff4, vuint8mf4_t maskedoff5, vuint8mf4_t maskedoff6, const uint8_t *base, size_t *new_vl, size_t vl) { + return __riscv_vlseg7e8ff_mu(v0, v1, v2, v3, v4, v5, v6, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, maskedoff4, maskedoff5, maskedoff6, base, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlseg7e8ff_v_u8mf2_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], ptr noundef [[V4:%.*]], ptr noundef [[V5:%.*]], ptr noundef [[V6:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], [[MASKEDOFF4:%.*]], [[MASKEDOFF5:%.*]], [[MASKEDOFF6:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , i64 } @llvm.riscv.vlseg7ff.mask.nxv4i8.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], [[MASKEDOFF4]], [[MASKEDOFF5]], [[MASKEDOFF6]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 1 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 1 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 1 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 4 +// CHECK-RV64-NEXT: store [[TMP5]], ptr [[V4]], align 1 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 5 +// CHECK-RV64-NEXT: store [[TMP6]], ptr [[V5]], align 1 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 6 +// CHECK-RV64-NEXT: store [[TMP7]], ptr [[V6]], align 1 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 7 +// CHECK-RV64-NEXT: store i64 [[TMP8]], ptr [[NEW_VL]], align 1 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg7e8ff_v_u8mf2_mu(vuint8mf2_t *v0, vuint8mf2_t *v1, vuint8mf2_t *v2, vuint8mf2_t *v3, vuint8mf2_t *v4, vuint8mf2_t *v5, vuint8mf2_t *v6, vbool16_t mask, vuint8mf2_t maskedoff0, vuint8mf2_t maskedoff1, vuint8mf2_t maskedoff2, vuint8mf2_t maskedoff3, vuint8mf2_t maskedoff4, vuint8mf2_t maskedoff5, vuint8mf2_t maskedoff6, const uint8_t *base, size_t *new_vl, size_t vl) { + return __riscv_vlseg7e8ff_mu(v0, v1, v2, v3, v4, v5, v6, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, maskedoff4, maskedoff5, maskedoff6, base, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlseg7e8ff_v_u8m1_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], ptr noundef [[V4:%.*]], ptr noundef [[V5:%.*]], ptr noundef [[V6:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], [[MASKEDOFF4:%.*]], [[MASKEDOFF5:%.*]], [[MASKEDOFF6:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , i64 } @llvm.riscv.vlseg7ff.mask.nxv8i8.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], [[MASKEDOFF4]], [[MASKEDOFF5]], [[MASKEDOFF6]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 1 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 1 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 1 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 4 +// CHECK-RV64-NEXT: store [[TMP5]], ptr [[V4]], align 1 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 5 +// CHECK-RV64-NEXT: store [[TMP6]], ptr [[V5]], align 1 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 6 +// CHECK-RV64-NEXT: store [[TMP7]], ptr [[V6]], align 1 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 7 +// CHECK-RV64-NEXT: store i64 [[TMP8]], ptr [[NEW_VL]], align 1 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg7e8ff_v_u8m1_mu(vuint8m1_t *v0, vuint8m1_t *v1, vuint8m1_t *v2, vuint8m1_t *v3, vuint8m1_t *v4, vuint8m1_t *v5, vuint8m1_t *v6, vbool8_t mask, vuint8m1_t maskedoff0, vuint8m1_t maskedoff1, vuint8m1_t maskedoff2, vuint8m1_t maskedoff3, vuint8m1_t maskedoff4, vuint8m1_t maskedoff5, vuint8m1_t maskedoff6, const uint8_t *base, size_t *new_vl, size_t vl) { + return __riscv_vlseg7e8ff_mu(v0, v1, v2, v3, v4, v5, v6, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, maskedoff4, maskedoff5, maskedoff6, base, new_vl, vl); +} + diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e16.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e16.c index 046fb5e7dc80d..f37bc9859a6ff 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e16.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e16.c @@ -709,3 +709,237 @@ void test_vlseg8e16_v_u16m1_tumu(vuint16m1_t *v0, vuint16m1_t *v1, vuint16m1_t * return __riscv_vlseg8e16_tumu(v0, v1, v2, v3, v4, v5, v6, v7, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, maskedoff4, maskedoff5, maskedoff6, maskedoff7, base, vl); } +// CHECK-RV64-LABEL: define dso_local void @test_vlseg8e16_v_f16mf4_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], ptr noundef [[V4:%.*]], ptr noundef [[V5:%.*]], ptr noundef [[V6:%.*]], ptr noundef [[V7:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], [[MASKEDOFF4:%.*]], [[MASKEDOFF5:%.*]], [[MASKEDOFF6:%.*]], [[MASKEDOFF7:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vlseg8.mask.nxv1f16.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], [[MASKEDOFF4]], [[MASKEDOFF5]], [[MASKEDOFF6]], [[MASKEDOFF7]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 2 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 2 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 2 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 4 +// CHECK-RV64-NEXT: store [[TMP5]], ptr [[V4]], align 2 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 5 +// CHECK-RV64-NEXT: store [[TMP6]], ptr [[V5]], align 2 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 6 +// CHECK-RV64-NEXT: store [[TMP7]], ptr [[V6]], align 2 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 7 +// CHECK-RV64-NEXT: store [[TMP8]], ptr [[V7]], align 2 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg8e16_v_f16mf4_mu(vfloat16mf4_t *v0, vfloat16mf4_t *v1, vfloat16mf4_t *v2, vfloat16mf4_t *v3, vfloat16mf4_t *v4, vfloat16mf4_t *v5, vfloat16mf4_t *v6, vfloat16mf4_t *v7, vbool64_t mask, vfloat16mf4_t maskedoff0, vfloat16mf4_t maskedoff1, vfloat16mf4_t maskedoff2, vfloat16mf4_t maskedoff3, vfloat16mf4_t maskedoff4, vfloat16mf4_t maskedoff5, vfloat16mf4_t maskedoff6, vfloat16mf4_t maskedoff7, const _Float16 *base, size_t vl) { + return __riscv_vlseg8e16_mu(v0, v1, v2, v3, v4, v5, v6, v7, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, maskedoff4, maskedoff5, maskedoff6, maskedoff7, base, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlseg8e16_v_f16mf2_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], ptr noundef [[V4:%.*]], ptr noundef [[V5:%.*]], ptr noundef [[V6:%.*]], ptr noundef [[V7:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], [[MASKEDOFF4:%.*]], [[MASKEDOFF5:%.*]], [[MASKEDOFF6:%.*]], [[MASKEDOFF7:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vlseg8.mask.nxv2f16.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], [[MASKEDOFF4]], [[MASKEDOFF5]], [[MASKEDOFF6]], [[MASKEDOFF7]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 2 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 2 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 2 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 4 +// CHECK-RV64-NEXT: store [[TMP5]], ptr [[V4]], align 2 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 5 +// CHECK-RV64-NEXT: store [[TMP6]], ptr [[V5]], align 2 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 6 +// CHECK-RV64-NEXT: store [[TMP7]], ptr [[V6]], align 2 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 7 +// CHECK-RV64-NEXT: store [[TMP8]], ptr [[V7]], align 2 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg8e16_v_f16mf2_mu(vfloat16mf2_t *v0, vfloat16mf2_t *v1, vfloat16mf2_t *v2, vfloat16mf2_t *v3, vfloat16mf2_t *v4, vfloat16mf2_t *v5, vfloat16mf2_t *v6, vfloat16mf2_t *v7, vbool32_t mask, vfloat16mf2_t maskedoff0, vfloat16mf2_t maskedoff1, vfloat16mf2_t maskedoff2, vfloat16mf2_t maskedoff3, vfloat16mf2_t maskedoff4, vfloat16mf2_t maskedoff5, vfloat16mf2_t maskedoff6, vfloat16mf2_t maskedoff7, const _Float16 *base, size_t vl) { + return __riscv_vlseg8e16_mu(v0, v1, v2, v3, v4, v5, v6, v7, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, maskedoff4, maskedoff5, maskedoff6, maskedoff7, base, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlseg8e16_v_f16m1_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], ptr noundef [[V4:%.*]], ptr noundef [[V5:%.*]], ptr noundef [[V6:%.*]], ptr noundef [[V7:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], [[MASKEDOFF4:%.*]], [[MASKEDOFF5:%.*]], [[MASKEDOFF6:%.*]], [[MASKEDOFF7:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vlseg8.mask.nxv4f16.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], [[MASKEDOFF4]], [[MASKEDOFF5]], [[MASKEDOFF6]], [[MASKEDOFF7]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 2 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 2 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 2 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 4 +// CHECK-RV64-NEXT: store [[TMP5]], ptr [[V4]], align 2 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 5 +// CHECK-RV64-NEXT: store [[TMP6]], ptr [[V5]], align 2 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 6 +// CHECK-RV64-NEXT: store [[TMP7]], ptr [[V6]], align 2 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 7 +// CHECK-RV64-NEXT: store [[TMP8]], ptr [[V7]], align 2 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg8e16_v_f16m1_mu(vfloat16m1_t *v0, vfloat16m1_t *v1, vfloat16m1_t *v2, vfloat16m1_t *v3, vfloat16m1_t *v4, vfloat16m1_t *v5, vfloat16m1_t *v6, vfloat16m1_t *v7, vbool16_t mask, vfloat16m1_t maskedoff0, vfloat16m1_t maskedoff1, vfloat16m1_t maskedoff2, vfloat16m1_t maskedoff3, vfloat16m1_t maskedoff4, vfloat16m1_t maskedoff5, vfloat16m1_t maskedoff6, vfloat16m1_t maskedoff7, const _Float16 *base, size_t vl) { + return __riscv_vlseg8e16_mu(v0, v1, v2, v3, v4, v5, v6, v7, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, maskedoff4, maskedoff5, maskedoff6, maskedoff7, base, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlseg8e16_v_i16mf4_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], ptr noundef [[V4:%.*]], ptr noundef [[V5:%.*]], ptr noundef [[V6:%.*]], ptr noundef [[V7:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], [[MASKEDOFF4:%.*]], [[MASKEDOFF5:%.*]], [[MASKEDOFF6:%.*]], [[MASKEDOFF7:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vlseg8.mask.nxv1i16.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], [[MASKEDOFF4]], [[MASKEDOFF5]], [[MASKEDOFF6]], [[MASKEDOFF7]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 2 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 2 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 2 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 4 +// CHECK-RV64-NEXT: store [[TMP5]], ptr [[V4]], align 2 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 5 +// CHECK-RV64-NEXT: store [[TMP6]], ptr [[V5]], align 2 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 6 +// CHECK-RV64-NEXT: store [[TMP7]], ptr [[V6]], align 2 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 7 +// CHECK-RV64-NEXT: store [[TMP8]], ptr [[V7]], align 2 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg8e16_v_i16mf4_mu(vint16mf4_t *v0, vint16mf4_t *v1, vint16mf4_t *v2, vint16mf4_t *v3, vint16mf4_t *v4, vint16mf4_t *v5, vint16mf4_t *v6, vint16mf4_t *v7, vbool64_t mask, vint16mf4_t maskedoff0, vint16mf4_t maskedoff1, vint16mf4_t maskedoff2, vint16mf4_t maskedoff3, vint16mf4_t maskedoff4, vint16mf4_t maskedoff5, vint16mf4_t maskedoff6, vint16mf4_t maskedoff7, const int16_t *base, size_t vl) { + return __riscv_vlseg8e16_mu(v0, v1, v2, v3, v4, v5, v6, v7, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, maskedoff4, maskedoff5, maskedoff6, maskedoff7, base, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlseg8e16_v_i16mf2_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], ptr noundef [[V4:%.*]], ptr noundef [[V5:%.*]], ptr noundef [[V6:%.*]], ptr noundef [[V7:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], [[MASKEDOFF4:%.*]], [[MASKEDOFF5:%.*]], [[MASKEDOFF6:%.*]], [[MASKEDOFF7:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vlseg8.mask.nxv2i16.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], [[MASKEDOFF4]], [[MASKEDOFF5]], [[MASKEDOFF6]], [[MASKEDOFF7]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 2 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 2 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 2 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 4 +// CHECK-RV64-NEXT: store [[TMP5]], ptr [[V4]], align 2 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 5 +// CHECK-RV64-NEXT: store [[TMP6]], ptr [[V5]], align 2 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 6 +// CHECK-RV64-NEXT: store [[TMP7]], ptr [[V6]], align 2 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 7 +// CHECK-RV64-NEXT: store [[TMP8]], ptr [[V7]], align 2 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg8e16_v_i16mf2_mu(vint16mf2_t *v0, vint16mf2_t *v1, vint16mf2_t *v2, vint16mf2_t *v3, vint16mf2_t *v4, vint16mf2_t *v5, vint16mf2_t *v6, vint16mf2_t *v7, vbool32_t mask, vint16mf2_t maskedoff0, vint16mf2_t maskedoff1, vint16mf2_t maskedoff2, vint16mf2_t maskedoff3, vint16mf2_t maskedoff4, vint16mf2_t maskedoff5, vint16mf2_t maskedoff6, vint16mf2_t maskedoff7, const int16_t *base, size_t vl) { + return __riscv_vlseg8e16_mu(v0, v1, v2, v3, v4, v5, v6, v7, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, maskedoff4, maskedoff5, maskedoff6, maskedoff7, base, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlseg8e16_v_i16m1_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], ptr noundef [[V4:%.*]], ptr noundef [[V5:%.*]], ptr noundef [[V6:%.*]], ptr noundef [[V7:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], [[MASKEDOFF4:%.*]], [[MASKEDOFF5:%.*]], [[MASKEDOFF6:%.*]], [[MASKEDOFF7:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vlseg8.mask.nxv4i16.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], [[MASKEDOFF4]], [[MASKEDOFF5]], [[MASKEDOFF6]], [[MASKEDOFF7]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 2 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 2 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 2 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 4 +// CHECK-RV64-NEXT: store [[TMP5]], ptr [[V4]], align 2 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 5 +// CHECK-RV64-NEXT: store [[TMP6]], ptr [[V5]], align 2 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 6 +// CHECK-RV64-NEXT: store [[TMP7]], ptr [[V6]], align 2 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 7 +// CHECK-RV64-NEXT: store [[TMP8]], ptr [[V7]], align 2 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg8e16_v_i16m1_mu(vint16m1_t *v0, vint16m1_t *v1, vint16m1_t *v2, vint16m1_t *v3, vint16m1_t *v4, vint16m1_t *v5, vint16m1_t *v6, vint16m1_t *v7, vbool16_t mask, vint16m1_t maskedoff0, vint16m1_t maskedoff1, vint16m1_t maskedoff2, vint16m1_t maskedoff3, vint16m1_t maskedoff4, vint16m1_t maskedoff5, vint16m1_t maskedoff6, vint16m1_t maskedoff7, const int16_t *base, size_t vl) { + return __riscv_vlseg8e16_mu(v0, v1, v2, v3, v4, v5, v6, v7, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, maskedoff4, maskedoff5, maskedoff6, maskedoff7, base, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlseg8e16_v_u16mf4_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], ptr noundef [[V4:%.*]], ptr noundef [[V5:%.*]], ptr noundef [[V6:%.*]], ptr noundef [[V7:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], [[MASKEDOFF4:%.*]], [[MASKEDOFF5:%.*]], [[MASKEDOFF6:%.*]], [[MASKEDOFF7:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vlseg8.mask.nxv1i16.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], [[MASKEDOFF4]], [[MASKEDOFF5]], [[MASKEDOFF6]], [[MASKEDOFF7]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 2 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 2 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 2 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 4 +// CHECK-RV64-NEXT: store [[TMP5]], ptr [[V4]], align 2 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 5 +// CHECK-RV64-NEXT: store [[TMP6]], ptr [[V5]], align 2 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 6 +// CHECK-RV64-NEXT: store [[TMP7]], ptr [[V6]], align 2 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 7 +// CHECK-RV64-NEXT: store [[TMP8]], ptr [[V7]], align 2 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg8e16_v_u16mf4_mu(vuint16mf4_t *v0, vuint16mf4_t *v1, vuint16mf4_t *v2, vuint16mf4_t *v3, vuint16mf4_t *v4, vuint16mf4_t *v5, vuint16mf4_t *v6, vuint16mf4_t *v7, vbool64_t mask, vuint16mf4_t maskedoff0, vuint16mf4_t maskedoff1, vuint16mf4_t maskedoff2, vuint16mf4_t maskedoff3, vuint16mf4_t maskedoff4, vuint16mf4_t maskedoff5, vuint16mf4_t maskedoff6, vuint16mf4_t maskedoff7, const uint16_t *base, size_t vl) { + return __riscv_vlseg8e16_mu(v0, v1, v2, v3, v4, v5, v6, v7, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, maskedoff4, maskedoff5, maskedoff6, maskedoff7, base, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlseg8e16_v_u16mf2_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], ptr noundef [[V4:%.*]], ptr noundef [[V5:%.*]], ptr noundef [[V6:%.*]], ptr noundef [[V7:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], [[MASKEDOFF4:%.*]], [[MASKEDOFF5:%.*]], [[MASKEDOFF6:%.*]], [[MASKEDOFF7:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vlseg8.mask.nxv2i16.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], [[MASKEDOFF4]], [[MASKEDOFF5]], [[MASKEDOFF6]], [[MASKEDOFF7]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 2 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 2 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 2 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 4 +// CHECK-RV64-NEXT: store [[TMP5]], ptr [[V4]], align 2 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 5 +// CHECK-RV64-NEXT: store [[TMP6]], ptr [[V5]], align 2 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 6 +// CHECK-RV64-NEXT: store [[TMP7]], ptr [[V6]], align 2 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 7 +// CHECK-RV64-NEXT: store [[TMP8]], ptr [[V7]], align 2 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg8e16_v_u16mf2_mu(vuint16mf2_t *v0, vuint16mf2_t *v1, vuint16mf2_t *v2, vuint16mf2_t *v3, vuint16mf2_t *v4, vuint16mf2_t *v5, vuint16mf2_t *v6, vuint16mf2_t *v7, vbool32_t mask, vuint16mf2_t maskedoff0, vuint16mf2_t maskedoff1, vuint16mf2_t maskedoff2, vuint16mf2_t maskedoff3, vuint16mf2_t maskedoff4, vuint16mf2_t maskedoff5, vuint16mf2_t maskedoff6, vuint16mf2_t maskedoff7, const uint16_t *base, size_t vl) { + return __riscv_vlseg8e16_mu(v0, v1, v2, v3, v4, v5, v6, v7, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, maskedoff4, maskedoff5, maskedoff6, maskedoff7, base, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlseg8e16_v_u16m1_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], ptr noundef [[V4:%.*]], ptr noundef [[V5:%.*]], ptr noundef [[V6:%.*]], ptr noundef [[V7:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], [[MASKEDOFF4:%.*]], [[MASKEDOFF5:%.*]], [[MASKEDOFF6:%.*]], [[MASKEDOFF7:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vlseg8.mask.nxv4i16.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], [[MASKEDOFF4]], [[MASKEDOFF5]], [[MASKEDOFF6]], [[MASKEDOFF7]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 2 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 2 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 2 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 4 +// CHECK-RV64-NEXT: store [[TMP5]], ptr [[V4]], align 2 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 5 +// CHECK-RV64-NEXT: store [[TMP6]], ptr [[V5]], align 2 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 6 +// CHECK-RV64-NEXT: store [[TMP7]], ptr [[V6]], align 2 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 7 +// CHECK-RV64-NEXT: store [[TMP8]], ptr [[V7]], align 2 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg8e16_v_u16m1_mu(vuint16m1_t *v0, vuint16m1_t *v1, vuint16m1_t *v2, vuint16m1_t *v3, vuint16m1_t *v4, vuint16m1_t *v5, vuint16m1_t *v6, vuint16m1_t *v7, vbool16_t mask, vuint16m1_t maskedoff0, vuint16m1_t maskedoff1, vuint16m1_t maskedoff2, vuint16m1_t maskedoff3, vuint16m1_t maskedoff4, vuint16m1_t maskedoff5, vuint16m1_t maskedoff6, vuint16m1_t maskedoff7, const uint16_t *base, size_t vl) { + return __riscv_vlseg8e16_mu(v0, v1, v2, v3, v4, v5, v6, v7, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, maskedoff4, maskedoff5, maskedoff6, maskedoff7, base, vl); +} + diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e16ff.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e16ff.c index 2f2055b86a0d4..6ce8d95e2ebd5 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e16ff.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e16ff.c @@ -763,3 +763,255 @@ void test_vlseg8e16ff_v_u16m1_tumu(vuint16m1_t *v0, vuint16m1_t *v1, vuint16m1_t return __riscv_vlseg8e16ff_tumu(v0, v1, v2, v3, v4, v5, v6, v7, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, maskedoff4, maskedoff5, maskedoff6, maskedoff7, base, new_vl, vl); } +// CHECK-RV64-LABEL: define dso_local void @test_vlseg8e16ff_v_f16mf4_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], ptr noundef [[V4:%.*]], ptr noundef [[V5:%.*]], ptr noundef [[V6:%.*]], ptr noundef [[V7:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], [[MASKEDOFF4:%.*]], [[MASKEDOFF5:%.*]], [[MASKEDOFF6:%.*]], [[MASKEDOFF7:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , , i64 } @llvm.riscv.vlseg8ff.mask.nxv1f16.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], [[MASKEDOFF4]], [[MASKEDOFF5]], [[MASKEDOFF6]], [[MASKEDOFF7]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 2 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 2 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 2 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 4 +// CHECK-RV64-NEXT: store [[TMP5]], ptr [[V4]], align 2 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 5 +// CHECK-RV64-NEXT: store [[TMP6]], ptr [[V5]], align 2 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 6 +// CHECK-RV64-NEXT: store [[TMP7]], ptr [[V6]], align 2 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 7 +// CHECK-RV64-NEXT: store [[TMP8]], ptr [[V7]], align 2 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 8 +// CHECK-RV64-NEXT: store i64 [[TMP9]], ptr [[NEW_VL]], align 2 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg8e16ff_v_f16mf4_mu(vfloat16mf4_t *v0, vfloat16mf4_t *v1, vfloat16mf4_t *v2, vfloat16mf4_t *v3, vfloat16mf4_t *v4, vfloat16mf4_t *v5, vfloat16mf4_t *v6, vfloat16mf4_t *v7, vbool64_t mask, vfloat16mf4_t maskedoff0, vfloat16mf4_t maskedoff1, vfloat16mf4_t maskedoff2, vfloat16mf4_t maskedoff3, vfloat16mf4_t maskedoff4, vfloat16mf4_t maskedoff5, vfloat16mf4_t maskedoff6, vfloat16mf4_t maskedoff7, const _Float16 *base, size_t *new_vl, size_t vl) { + return __riscv_vlseg8e16ff_mu(v0, v1, v2, v3, v4, v5, v6, v7, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, maskedoff4, maskedoff5, maskedoff6, maskedoff7, base, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlseg8e16ff_v_f16mf2_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], ptr noundef [[V4:%.*]], ptr noundef [[V5:%.*]], ptr noundef [[V6:%.*]], ptr noundef [[V7:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], [[MASKEDOFF4:%.*]], [[MASKEDOFF5:%.*]], [[MASKEDOFF6:%.*]], [[MASKEDOFF7:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , , i64 } @llvm.riscv.vlseg8ff.mask.nxv2f16.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], [[MASKEDOFF4]], [[MASKEDOFF5]], [[MASKEDOFF6]], [[MASKEDOFF7]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 2 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 2 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 2 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 4 +// CHECK-RV64-NEXT: store [[TMP5]], ptr [[V4]], align 2 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 5 +// CHECK-RV64-NEXT: store [[TMP6]], ptr [[V5]], align 2 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 6 +// CHECK-RV64-NEXT: store [[TMP7]], ptr [[V6]], align 2 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 7 +// CHECK-RV64-NEXT: store [[TMP8]], ptr [[V7]], align 2 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 8 +// CHECK-RV64-NEXT: store i64 [[TMP9]], ptr [[NEW_VL]], align 2 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg8e16ff_v_f16mf2_mu(vfloat16mf2_t *v0, vfloat16mf2_t *v1, vfloat16mf2_t *v2, vfloat16mf2_t *v3, vfloat16mf2_t *v4, vfloat16mf2_t *v5, vfloat16mf2_t *v6, vfloat16mf2_t *v7, vbool32_t mask, vfloat16mf2_t maskedoff0, vfloat16mf2_t maskedoff1, vfloat16mf2_t maskedoff2, vfloat16mf2_t maskedoff3, vfloat16mf2_t maskedoff4, vfloat16mf2_t maskedoff5, vfloat16mf2_t maskedoff6, vfloat16mf2_t maskedoff7, const _Float16 *base, size_t *new_vl, size_t vl) { + return __riscv_vlseg8e16ff_mu(v0, v1, v2, v3, v4, v5, v6, v7, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, maskedoff4, maskedoff5, maskedoff6, maskedoff7, base, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlseg8e16ff_v_f16m1_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], ptr noundef [[V4:%.*]], ptr noundef [[V5:%.*]], ptr noundef [[V6:%.*]], ptr noundef [[V7:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], [[MASKEDOFF4:%.*]], [[MASKEDOFF5:%.*]], [[MASKEDOFF6:%.*]], [[MASKEDOFF7:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , , i64 } @llvm.riscv.vlseg8ff.mask.nxv4f16.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], [[MASKEDOFF4]], [[MASKEDOFF5]], [[MASKEDOFF6]], [[MASKEDOFF7]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 2 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 2 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 2 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 4 +// CHECK-RV64-NEXT: store [[TMP5]], ptr [[V4]], align 2 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 5 +// CHECK-RV64-NEXT: store [[TMP6]], ptr [[V5]], align 2 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 6 +// CHECK-RV64-NEXT: store [[TMP7]], ptr [[V6]], align 2 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 7 +// CHECK-RV64-NEXT: store [[TMP8]], ptr [[V7]], align 2 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 8 +// CHECK-RV64-NEXT: store i64 [[TMP9]], ptr [[NEW_VL]], align 2 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg8e16ff_v_f16m1_mu(vfloat16m1_t *v0, vfloat16m1_t *v1, vfloat16m1_t *v2, vfloat16m1_t *v3, vfloat16m1_t *v4, vfloat16m1_t *v5, vfloat16m1_t *v6, vfloat16m1_t *v7, vbool16_t mask, vfloat16m1_t maskedoff0, vfloat16m1_t maskedoff1, vfloat16m1_t maskedoff2, vfloat16m1_t maskedoff3, vfloat16m1_t maskedoff4, vfloat16m1_t maskedoff5, vfloat16m1_t maskedoff6, vfloat16m1_t maskedoff7, const _Float16 *base, size_t *new_vl, size_t vl) { + return __riscv_vlseg8e16ff_mu(v0, v1, v2, v3, v4, v5, v6, v7, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, maskedoff4, maskedoff5, maskedoff6, maskedoff7, base, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlseg8e16ff_v_i16mf4_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], ptr noundef [[V4:%.*]], ptr noundef [[V5:%.*]], ptr noundef [[V6:%.*]], ptr noundef [[V7:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], [[MASKEDOFF4:%.*]], [[MASKEDOFF5:%.*]], [[MASKEDOFF6:%.*]], [[MASKEDOFF7:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , , i64 } @llvm.riscv.vlseg8ff.mask.nxv1i16.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], [[MASKEDOFF4]], [[MASKEDOFF5]], [[MASKEDOFF6]], [[MASKEDOFF7]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 2 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 2 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 2 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 4 +// CHECK-RV64-NEXT: store [[TMP5]], ptr [[V4]], align 2 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 5 +// CHECK-RV64-NEXT: store [[TMP6]], ptr [[V5]], align 2 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 6 +// CHECK-RV64-NEXT: store [[TMP7]], ptr [[V6]], align 2 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 7 +// CHECK-RV64-NEXT: store [[TMP8]], ptr [[V7]], align 2 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 8 +// CHECK-RV64-NEXT: store i64 [[TMP9]], ptr [[NEW_VL]], align 2 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg8e16ff_v_i16mf4_mu(vint16mf4_t *v0, vint16mf4_t *v1, vint16mf4_t *v2, vint16mf4_t *v3, vint16mf4_t *v4, vint16mf4_t *v5, vint16mf4_t *v6, vint16mf4_t *v7, vbool64_t mask, vint16mf4_t maskedoff0, vint16mf4_t maskedoff1, vint16mf4_t maskedoff2, vint16mf4_t maskedoff3, vint16mf4_t maskedoff4, vint16mf4_t maskedoff5, vint16mf4_t maskedoff6, vint16mf4_t maskedoff7, const int16_t *base, size_t *new_vl, size_t vl) { + return __riscv_vlseg8e16ff_mu(v0, v1, v2, v3, v4, v5, v6, v7, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, maskedoff4, maskedoff5, maskedoff6, maskedoff7, base, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlseg8e16ff_v_i16mf2_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], ptr noundef [[V4:%.*]], ptr noundef [[V5:%.*]], ptr noundef [[V6:%.*]], ptr noundef [[V7:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], [[MASKEDOFF4:%.*]], [[MASKEDOFF5:%.*]], [[MASKEDOFF6:%.*]], [[MASKEDOFF7:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , , i64 } @llvm.riscv.vlseg8ff.mask.nxv2i16.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], [[MASKEDOFF4]], [[MASKEDOFF5]], [[MASKEDOFF6]], [[MASKEDOFF7]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 2 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 2 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 2 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 4 +// CHECK-RV64-NEXT: store [[TMP5]], ptr [[V4]], align 2 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 5 +// CHECK-RV64-NEXT: store [[TMP6]], ptr [[V5]], align 2 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 6 +// CHECK-RV64-NEXT: store [[TMP7]], ptr [[V6]], align 2 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 7 +// CHECK-RV64-NEXT: store [[TMP8]], ptr [[V7]], align 2 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 8 +// CHECK-RV64-NEXT: store i64 [[TMP9]], ptr [[NEW_VL]], align 2 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg8e16ff_v_i16mf2_mu(vint16mf2_t *v0, vint16mf2_t *v1, vint16mf2_t *v2, vint16mf2_t *v3, vint16mf2_t *v4, vint16mf2_t *v5, vint16mf2_t *v6, vint16mf2_t *v7, vbool32_t mask, vint16mf2_t maskedoff0, vint16mf2_t maskedoff1, vint16mf2_t maskedoff2, vint16mf2_t maskedoff3, vint16mf2_t maskedoff4, vint16mf2_t maskedoff5, vint16mf2_t maskedoff6, vint16mf2_t maskedoff7, const int16_t *base, size_t *new_vl, size_t vl) { + return __riscv_vlseg8e16ff_mu(v0, v1, v2, v3, v4, v5, v6, v7, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, maskedoff4, maskedoff5, maskedoff6, maskedoff7, base, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlseg8e16ff_v_i16m1_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], ptr noundef [[V4:%.*]], ptr noundef [[V5:%.*]], ptr noundef [[V6:%.*]], ptr noundef [[V7:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], [[MASKEDOFF4:%.*]], [[MASKEDOFF5:%.*]], [[MASKEDOFF6:%.*]], [[MASKEDOFF7:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , , i64 } @llvm.riscv.vlseg8ff.mask.nxv4i16.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], [[MASKEDOFF4]], [[MASKEDOFF5]], [[MASKEDOFF6]], [[MASKEDOFF7]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 2 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 2 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 2 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 4 +// CHECK-RV64-NEXT: store [[TMP5]], ptr [[V4]], align 2 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 5 +// CHECK-RV64-NEXT: store [[TMP6]], ptr [[V5]], align 2 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 6 +// CHECK-RV64-NEXT: store [[TMP7]], ptr [[V6]], align 2 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 7 +// CHECK-RV64-NEXT: store [[TMP8]], ptr [[V7]], align 2 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 8 +// CHECK-RV64-NEXT: store i64 [[TMP9]], ptr [[NEW_VL]], align 2 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg8e16ff_v_i16m1_mu(vint16m1_t *v0, vint16m1_t *v1, vint16m1_t *v2, vint16m1_t *v3, vint16m1_t *v4, vint16m1_t *v5, vint16m1_t *v6, vint16m1_t *v7, vbool16_t mask, vint16m1_t maskedoff0, vint16m1_t maskedoff1, vint16m1_t maskedoff2, vint16m1_t maskedoff3, vint16m1_t maskedoff4, vint16m1_t maskedoff5, vint16m1_t maskedoff6, vint16m1_t maskedoff7, const int16_t *base, size_t *new_vl, size_t vl) { + return __riscv_vlseg8e16ff_mu(v0, v1, v2, v3, v4, v5, v6, v7, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, maskedoff4, maskedoff5, maskedoff6, maskedoff7, base, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlseg8e16ff_v_u16mf4_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], ptr noundef [[V4:%.*]], ptr noundef [[V5:%.*]], ptr noundef [[V6:%.*]], ptr noundef [[V7:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], [[MASKEDOFF4:%.*]], [[MASKEDOFF5:%.*]], [[MASKEDOFF6:%.*]], [[MASKEDOFF7:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , , i64 } @llvm.riscv.vlseg8ff.mask.nxv1i16.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], [[MASKEDOFF4]], [[MASKEDOFF5]], [[MASKEDOFF6]], [[MASKEDOFF7]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 2 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 2 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 2 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 4 +// CHECK-RV64-NEXT: store [[TMP5]], ptr [[V4]], align 2 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 5 +// CHECK-RV64-NEXT: store [[TMP6]], ptr [[V5]], align 2 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 6 +// CHECK-RV64-NEXT: store [[TMP7]], ptr [[V6]], align 2 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 7 +// CHECK-RV64-NEXT: store [[TMP8]], ptr [[V7]], align 2 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 8 +// CHECK-RV64-NEXT: store i64 [[TMP9]], ptr [[NEW_VL]], align 2 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg8e16ff_v_u16mf4_mu(vuint16mf4_t *v0, vuint16mf4_t *v1, vuint16mf4_t *v2, vuint16mf4_t *v3, vuint16mf4_t *v4, vuint16mf4_t *v5, vuint16mf4_t *v6, vuint16mf4_t *v7, vbool64_t mask, vuint16mf4_t maskedoff0, vuint16mf4_t maskedoff1, vuint16mf4_t maskedoff2, vuint16mf4_t maskedoff3, vuint16mf4_t maskedoff4, vuint16mf4_t maskedoff5, vuint16mf4_t maskedoff6, vuint16mf4_t maskedoff7, const uint16_t *base, size_t *new_vl, size_t vl) { + return __riscv_vlseg8e16ff_mu(v0, v1, v2, v3, v4, v5, v6, v7, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, maskedoff4, maskedoff5, maskedoff6, maskedoff7, base, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlseg8e16ff_v_u16mf2_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], ptr noundef [[V4:%.*]], ptr noundef [[V5:%.*]], ptr noundef [[V6:%.*]], ptr noundef [[V7:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], [[MASKEDOFF4:%.*]], [[MASKEDOFF5:%.*]], [[MASKEDOFF6:%.*]], [[MASKEDOFF7:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , , i64 } @llvm.riscv.vlseg8ff.mask.nxv2i16.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], [[MASKEDOFF4]], [[MASKEDOFF5]], [[MASKEDOFF6]], [[MASKEDOFF7]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 2 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 2 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 2 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 4 +// CHECK-RV64-NEXT: store [[TMP5]], ptr [[V4]], align 2 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 5 +// CHECK-RV64-NEXT: store [[TMP6]], ptr [[V5]], align 2 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 6 +// CHECK-RV64-NEXT: store [[TMP7]], ptr [[V6]], align 2 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 7 +// CHECK-RV64-NEXT: store [[TMP8]], ptr [[V7]], align 2 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 8 +// CHECK-RV64-NEXT: store i64 [[TMP9]], ptr [[NEW_VL]], align 2 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg8e16ff_v_u16mf2_mu(vuint16mf2_t *v0, vuint16mf2_t *v1, vuint16mf2_t *v2, vuint16mf2_t *v3, vuint16mf2_t *v4, vuint16mf2_t *v5, vuint16mf2_t *v6, vuint16mf2_t *v7, vbool32_t mask, vuint16mf2_t maskedoff0, vuint16mf2_t maskedoff1, vuint16mf2_t maskedoff2, vuint16mf2_t maskedoff3, vuint16mf2_t maskedoff4, vuint16mf2_t maskedoff5, vuint16mf2_t maskedoff6, vuint16mf2_t maskedoff7, const uint16_t *base, size_t *new_vl, size_t vl) { + return __riscv_vlseg8e16ff_mu(v0, v1, v2, v3, v4, v5, v6, v7, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, maskedoff4, maskedoff5, maskedoff6, maskedoff7, base, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlseg8e16ff_v_u16m1_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], ptr noundef [[V4:%.*]], ptr noundef [[V5:%.*]], ptr noundef [[V6:%.*]], ptr noundef [[V7:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], [[MASKEDOFF4:%.*]], [[MASKEDOFF5:%.*]], [[MASKEDOFF6:%.*]], [[MASKEDOFF7:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , , i64 } @llvm.riscv.vlseg8ff.mask.nxv4i16.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], [[MASKEDOFF4]], [[MASKEDOFF5]], [[MASKEDOFF6]], [[MASKEDOFF7]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 2 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 2 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 2 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 4 +// CHECK-RV64-NEXT: store [[TMP5]], ptr [[V4]], align 2 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 5 +// CHECK-RV64-NEXT: store [[TMP6]], ptr [[V5]], align 2 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 6 +// CHECK-RV64-NEXT: store [[TMP7]], ptr [[V6]], align 2 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 7 +// CHECK-RV64-NEXT: store [[TMP8]], ptr [[V7]], align 2 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 8 +// CHECK-RV64-NEXT: store i64 [[TMP9]], ptr [[NEW_VL]], align 2 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg8e16ff_v_u16m1_mu(vuint16m1_t *v0, vuint16m1_t *v1, vuint16m1_t *v2, vuint16m1_t *v3, vuint16m1_t *v4, vuint16m1_t *v5, vuint16m1_t *v6, vuint16m1_t *v7, vbool16_t mask, vuint16m1_t maskedoff0, vuint16m1_t maskedoff1, vuint16m1_t maskedoff2, vuint16m1_t maskedoff3, vuint16m1_t maskedoff4, vuint16m1_t maskedoff5, vuint16m1_t maskedoff6, vuint16m1_t maskedoff7, const uint16_t *base, size_t *new_vl, size_t vl) { + return __riscv_vlseg8e16ff_mu(v0, v1, v2, v3, v4, v5, v6, v7, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, maskedoff4, maskedoff5, maskedoff6, maskedoff7, base, new_vl, vl); +} + diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e32.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e32.c index 03bbe59f6f539..da8df380df802 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e32.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e32.c @@ -475,3 +475,159 @@ void test_vlseg8e32_v_u32m1_tumu(vuint32m1_t *v0, vuint32m1_t *v1, vuint32m1_t * return __riscv_vlseg8e32_tumu(v0, v1, v2, v3, v4, v5, v6, v7, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, maskedoff4, maskedoff5, maskedoff6, maskedoff7, base, vl); } +// CHECK-RV64-LABEL: define dso_local void @test_vlseg8e32_v_f32mf2_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], ptr noundef [[V4:%.*]], ptr noundef [[V5:%.*]], ptr noundef [[V6:%.*]], ptr noundef [[V7:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], [[MASKEDOFF4:%.*]], [[MASKEDOFF5:%.*]], [[MASKEDOFF6:%.*]], [[MASKEDOFF7:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vlseg8.mask.nxv1f32.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], [[MASKEDOFF4]], [[MASKEDOFF5]], [[MASKEDOFF6]], [[MASKEDOFF7]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 4 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 4 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 4 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 4 +// CHECK-RV64-NEXT: store [[TMP5]], ptr [[V4]], align 4 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 5 +// CHECK-RV64-NEXT: store [[TMP6]], ptr [[V5]], align 4 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 6 +// CHECK-RV64-NEXT: store [[TMP7]], ptr [[V6]], align 4 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 7 +// CHECK-RV64-NEXT: store [[TMP8]], ptr [[V7]], align 4 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg8e32_v_f32mf2_mu(vfloat32mf2_t *v0, vfloat32mf2_t *v1, vfloat32mf2_t *v2, vfloat32mf2_t *v3, vfloat32mf2_t *v4, vfloat32mf2_t *v5, vfloat32mf2_t *v6, vfloat32mf2_t *v7, vbool64_t mask, vfloat32mf2_t maskedoff0, vfloat32mf2_t maskedoff1, vfloat32mf2_t maskedoff2, vfloat32mf2_t maskedoff3, vfloat32mf2_t maskedoff4, vfloat32mf2_t maskedoff5, vfloat32mf2_t maskedoff6, vfloat32mf2_t maskedoff7, const float *base, size_t vl) { + return __riscv_vlseg8e32_mu(v0, v1, v2, v3, v4, v5, v6, v7, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, maskedoff4, maskedoff5, maskedoff6, maskedoff7, base, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlseg8e32_v_f32m1_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], ptr noundef [[V4:%.*]], ptr noundef [[V5:%.*]], ptr noundef [[V6:%.*]], ptr noundef [[V7:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], [[MASKEDOFF4:%.*]], [[MASKEDOFF5:%.*]], [[MASKEDOFF6:%.*]], [[MASKEDOFF7:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vlseg8.mask.nxv2f32.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], [[MASKEDOFF4]], [[MASKEDOFF5]], [[MASKEDOFF6]], [[MASKEDOFF7]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 4 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 4 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 4 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 4 +// CHECK-RV64-NEXT: store [[TMP5]], ptr [[V4]], align 4 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 5 +// CHECK-RV64-NEXT: store [[TMP6]], ptr [[V5]], align 4 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 6 +// CHECK-RV64-NEXT: store [[TMP7]], ptr [[V6]], align 4 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 7 +// CHECK-RV64-NEXT: store [[TMP8]], ptr [[V7]], align 4 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg8e32_v_f32m1_mu(vfloat32m1_t *v0, vfloat32m1_t *v1, vfloat32m1_t *v2, vfloat32m1_t *v3, vfloat32m1_t *v4, vfloat32m1_t *v5, vfloat32m1_t *v6, vfloat32m1_t *v7, vbool32_t mask, vfloat32m1_t maskedoff0, vfloat32m1_t maskedoff1, vfloat32m1_t maskedoff2, vfloat32m1_t maskedoff3, vfloat32m1_t maskedoff4, vfloat32m1_t maskedoff5, vfloat32m1_t maskedoff6, vfloat32m1_t maskedoff7, const float *base, size_t vl) { + return __riscv_vlseg8e32_mu(v0, v1, v2, v3, v4, v5, v6, v7, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, maskedoff4, maskedoff5, maskedoff6, maskedoff7, base, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlseg8e32_v_i32mf2_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], ptr noundef [[V4:%.*]], ptr noundef [[V5:%.*]], ptr noundef [[V6:%.*]], ptr noundef [[V7:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], [[MASKEDOFF4:%.*]], [[MASKEDOFF5:%.*]], [[MASKEDOFF6:%.*]], [[MASKEDOFF7:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vlseg8.mask.nxv1i32.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], [[MASKEDOFF4]], [[MASKEDOFF5]], [[MASKEDOFF6]], [[MASKEDOFF7]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 4 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 4 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 4 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 4 +// CHECK-RV64-NEXT: store [[TMP5]], ptr [[V4]], align 4 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 5 +// CHECK-RV64-NEXT: store [[TMP6]], ptr [[V5]], align 4 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 6 +// CHECK-RV64-NEXT: store [[TMP7]], ptr [[V6]], align 4 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 7 +// CHECK-RV64-NEXT: store [[TMP8]], ptr [[V7]], align 4 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg8e32_v_i32mf2_mu(vint32mf2_t *v0, vint32mf2_t *v1, vint32mf2_t *v2, vint32mf2_t *v3, vint32mf2_t *v4, vint32mf2_t *v5, vint32mf2_t *v6, vint32mf2_t *v7, vbool64_t mask, vint32mf2_t maskedoff0, vint32mf2_t maskedoff1, vint32mf2_t maskedoff2, vint32mf2_t maskedoff3, vint32mf2_t maskedoff4, vint32mf2_t maskedoff5, vint32mf2_t maskedoff6, vint32mf2_t maskedoff7, const int32_t *base, size_t vl) { + return __riscv_vlseg8e32_mu(v0, v1, v2, v3, v4, v5, v6, v7, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, maskedoff4, maskedoff5, maskedoff6, maskedoff7, base, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlseg8e32_v_i32m1_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], ptr noundef [[V4:%.*]], ptr noundef [[V5:%.*]], ptr noundef [[V6:%.*]], ptr noundef [[V7:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], [[MASKEDOFF4:%.*]], [[MASKEDOFF5:%.*]], [[MASKEDOFF6:%.*]], [[MASKEDOFF7:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vlseg8.mask.nxv2i32.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], [[MASKEDOFF4]], [[MASKEDOFF5]], [[MASKEDOFF6]], [[MASKEDOFF7]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 4 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 4 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 4 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 4 +// CHECK-RV64-NEXT: store [[TMP5]], ptr [[V4]], align 4 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 5 +// CHECK-RV64-NEXT: store [[TMP6]], ptr [[V5]], align 4 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 6 +// CHECK-RV64-NEXT: store [[TMP7]], ptr [[V6]], align 4 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 7 +// CHECK-RV64-NEXT: store [[TMP8]], ptr [[V7]], align 4 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg8e32_v_i32m1_mu(vint32m1_t *v0, vint32m1_t *v1, vint32m1_t *v2, vint32m1_t *v3, vint32m1_t *v4, vint32m1_t *v5, vint32m1_t *v6, vint32m1_t *v7, vbool32_t mask, vint32m1_t maskedoff0, vint32m1_t maskedoff1, vint32m1_t maskedoff2, vint32m1_t maskedoff3, vint32m1_t maskedoff4, vint32m1_t maskedoff5, vint32m1_t maskedoff6, vint32m1_t maskedoff7, const int32_t *base, size_t vl) { + return __riscv_vlseg8e32_mu(v0, v1, v2, v3, v4, v5, v6, v7, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, maskedoff4, maskedoff5, maskedoff6, maskedoff7, base, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlseg8e32_v_u32mf2_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], ptr noundef [[V4:%.*]], ptr noundef [[V5:%.*]], ptr noundef [[V6:%.*]], ptr noundef [[V7:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], [[MASKEDOFF4:%.*]], [[MASKEDOFF5:%.*]], [[MASKEDOFF6:%.*]], [[MASKEDOFF7:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vlseg8.mask.nxv1i32.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], [[MASKEDOFF4]], [[MASKEDOFF5]], [[MASKEDOFF6]], [[MASKEDOFF7]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 4 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 4 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 4 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 4 +// CHECK-RV64-NEXT: store [[TMP5]], ptr [[V4]], align 4 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 5 +// CHECK-RV64-NEXT: store [[TMP6]], ptr [[V5]], align 4 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 6 +// CHECK-RV64-NEXT: store [[TMP7]], ptr [[V6]], align 4 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 7 +// CHECK-RV64-NEXT: store [[TMP8]], ptr [[V7]], align 4 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg8e32_v_u32mf2_mu(vuint32mf2_t *v0, vuint32mf2_t *v1, vuint32mf2_t *v2, vuint32mf2_t *v3, vuint32mf2_t *v4, vuint32mf2_t *v5, vuint32mf2_t *v6, vuint32mf2_t *v7, vbool64_t mask, vuint32mf2_t maskedoff0, vuint32mf2_t maskedoff1, vuint32mf2_t maskedoff2, vuint32mf2_t maskedoff3, vuint32mf2_t maskedoff4, vuint32mf2_t maskedoff5, vuint32mf2_t maskedoff6, vuint32mf2_t maskedoff7, const uint32_t *base, size_t vl) { + return __riscv_vlseg8e32_mu(v0, v1, v2, v3, v4, v5, v6, v7, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, maskedoff4, maskedoff5, maskedoff6, maskedoff7, base, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlseg8e32_v_u32m1_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], ptr noundef [[V4:%.*]], ptr noundef [[V5:%.*]], ptr noundef [[V6:%.*]], ptr noundef [[V7:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], [[MASKEDOFF4:%.*]], [[MASKEDOFF5:%.*]], [[MASKEDOFF6:%.*]], [[MASKEDOFF7:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vlseg8.mask.nxv2i32.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], [[MASKEDOFF4]], [[MASKEDOFF5]], [[MASKEDOFF6]], [[MASKEDOFF7]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 4 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 4 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 4 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 4 +// CHECK-RV64-NEXT: store [[TMP5]], ptr [[V4]], align 4 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 5 +// CHECK-RV64-NEXT: store [[TMP6]], ptr [[V5]], align 4 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 6 +// CHECK-RV64-NEXT: store [[TMP7]], ptr [[V6]], align 4 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 7 +// CHECK-RV64-NEXT: store [[TMP8]], ptr [[V7]], align 4 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg8e32_v_u32m1_mu(vuint32m1_t *v0, vuint32m1_t *v1, vuint32m1_t *v2, vuint32m1_t *v3, vuint32m1_t *v4, vuint32m1_t *v5, vuint32m1_t *v6, vuint32m1_t *v7, vbool32_t mask, vuint32m1_t maskedoff0, vuint32m1_t maskedoff1, vuint32m1_t maskedoff2, vuint32m1_t maskedoff3, vuint32m1_t maskedoff4, vuint32m1_t maskedoff5, vuint32m1_t maskedoff6, vuint32m1_t maskedoff7, const uint32_t *base, size_t vl) { + return __riscv_vlseg8e32_mu(v0, v1, v2, v3, v4, v5, v6, v7, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, maskedoff4, maskedoff5, maskedoff6, maskedoff7, base, vl); +} + diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e32ff.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e32ff.c index 34eead4fb1baa..800f944ae9741 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e32ff.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e32ff.c @@ -511,3 +511,171 @@ void test_vlseg8e32ff_v_u32m1_tumu(vuint32m1_t *v0, vuint32m1_t *v1, vuint32m1_t return __riscv_vlseg8e32ff_tumu(v0, v1, v2, v3, v4, v5, v6, v7, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, maskedoff4, maskedoff5, maskedoff6, maskedoff7, base, new_vl, vl); } +// CHECK-RV64-LABEL: define dso_local void @test_vlseg8e32ff_v_f32mf2_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], ptr noundef [[V4:%.*]], ptr noundef [[V5:%.*]], ptr noundef [[V6:%.*]], ptr noundef [[V7:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], [[MASKEDOFF4:%.*]], [[MASKEDOFF5:%.*]], [[MASKEDOFF6:%.*]], [[MASKEDOFF7:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , , i64 } @llvm.riscv.vlseg8ff.mask.nxv1f32.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], [[MASKEDOFF4]], [[MASKEDOFF5]], [[MASKEDOFF6]], [[MASKEDOFF7]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 4 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 4 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 4 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 4 +// CHECK-RV64-NEXT: store [[TMP5]], ptr [[V4]], align 4 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 5 +// CHECK-RV64-NEXT: store [[TMP6]], ptr [[V5]], align 4 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 6 +// CHECK-RV64-NEXT: store [[TMP7]], ptr [[V6]], align 4 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 7 +// CHECK-RV64-NEXT: store [[TMP8]], ptr [[V7]], align 4 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 8 +// CHECK-RV64-NEXT: store i64 [[TMP9]], ptr [[NEW_VL]], align 4 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg8e32ff_v_f32mf2_mu(vfloat32mf2_t *v0, vfloat32mf2_t *v1, vfloat32mf2_t *v2, vfloat32mf2_t *v3, vfloat32mf2_t *v4, vfloat32mf2_t *v5, vfloat32mf2_t *v6, vfloat32mf2_t *v7, vbool64_t mask, vfloat32mf2_t maskedoff0, vfloat32mf2_t maskedoff1, vfloat32mf2_t maskedoff2, vfloat32mf2_t maskedoff3, vfloat32mf2_t maskedoff4, vfloat32mf2_t maskedoff5, vfloat32mf2_t maskedoff6, vfloat32mf2_t maskedoff7, const float *base, size_t *new_vl, size_t vl) { + return __riscv_vlseg8e32ff_mu(v0, v1, v2, v3, v4, v5, v6, v7, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, maskedoff4, maskedoff5, maskedoff6, maskedoff7, base, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlseg8e32ff_v_f32m1_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], ptr noundef [[V4:%.*]], ptr noundef [[V5:%.*]], ptr noundef [[V6:%.*]], ptr noundef [[V7:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], [[MASKEDOFF4:%.*]], [[MASKEDOFF5:%.*]], [[MASKEDOFF6:%.*]], [[MASKEDOFF7:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , , i64 } @llvm.riscv.vlseg8ff.mask.nxv2f32.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], [[MASKEDOFF4]], [[MASKEDOFF5]], [[MASKEDOFF6]], [[MASKEDOFF7]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 4 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 4 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 4 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 4 +// CHECK-RV64-NEXT: store [[TMP5]], ptr [[V4]], align 4 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 5 +// CHECK-RV64-NEXT: store [[TMP6]], ptr [[V5]], align 4 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 6 +// CHECK-RV64-NEXT: store [[TMP7]], ptr [[V6]], align 4 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 7 +// CHECK-RV64-NEXT: store [[TMP8]], ptr [[V7]], align 4 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 8 +// CHECK-RV64-NEXT: store i64 [[TMP9]], ptr [[NEW_VL]], align 4 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg8e32ff_v_f32m1_mu(vfloat32m1_t *v0, vfloat32m1_t *v1, vfloat32m1_t *v2, vfloat32m1_t *v3, vfloat32m1_t *v4, vfloat32m1_t *v5, vfloat32m1_t *v6, vfloat32m1_t *v7, vbool32_t mask, vfloat32m1_t maskedoff0, vfloat32m1_t maskedoff1, vfloat32m1_t maskedoff2, vfloat32m1_t maskedoff3, vfloat32m1_t maskedoff4, vfloat32m1_t maskedoff5, vfloat32m1_t maskedoff6, vfloat32m1_t maskedoff7, const float *base, size_t *new_vl, size_t vl) { + return __riscv_vlseg8e32ff_mu(v0, v1, v2, v3, v4, v5, v6, v7, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, maskedoff4, maskedoff5, maskedoff6, maskedoff7, base, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlseg8e32ff_v_i32mf2_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], ptr noundef [[V4:%.*]], ptr noundef [[V5:%.*]], ptr noundef [[V6:%.*]], ptr noundef [[V7:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], [[MASKEDOFF4:%.*]], [[MASKEDOFF5:%.*]], [[MASKEDOFF6:%.*]], [[MASKEDOFF7:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , , i64 } @llvm.riscv.vlseg8ff.mask.nxv1i32.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], [[MASKEDOFF4]], [[MASKEDOFF5]], [[MASKEDOFF6]], [[MASKEDOFF7]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 4 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 4 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 4 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 4 +// CHECK-RV64-NEXT: store [[TMP5]], ptr [[V4]], align 4 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 5 +// CHECK-RV64-NEXT: store [[TMP6]], ptr [[V5]], align 4 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 6 +// CHECK-RV64-NEXT: store [[TMP7]], ptr [[V6]], align 4 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 7 +// CHECK-RV64-NEXT: store [[TMP8]], ptr [[V7]], align 4 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 8 +// CHECK-RV64-NEXT: store i64 [[TMP9]], ptr [[NEW_VL]], align 4 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg8e32ff_v_i32mf2_mu(vint32mf2_t *v0, vint32mf2_t *v1, vint32mf2_t *v2, vint32mf2_t *v3, vint32mf2_t *v4, vint32mf2_t *v5, vint32mf2_t *v6, vint32mf2_t *v7, vbool64_t mask, vint32mf2_t maskedoff0, vint32mf2_t maskedoff1, vint32mf2_t maskedoff2, vint32mf2_t maskedoff3, vint32mf2_t maskedoff4, vint32mf2_t maskedoff5, vint32mf2_t maskedoff6, vint32mf2_t maskedoff7, const int32_t *base, size_t *new_vl, size_t vl) { + return __riscv_vlseg8e32ff_mu(v0, v1, v2, v3, v4, v5, v6, v7, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, maskedoff4, maskedoff5, maskedoff6, maskedoff7, base, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlseg8e32ff_v_i32m1_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], ptr noundef [[V4:%.*]], ptr noundef [[V5:%.*]], ptr noundef [[V6:%.*]], ptr noundef [[V7:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], [[MASKEDOFF4:%.*]], [[MASKEDOFF5:%.*]], [[MASKEDOFF6:%.*]], [[MASKEDOFF7:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , , i64 } @llvm.riscv.vlseg8ff.mask.nxv2i32.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], [[MASKEDOFF4]], [[MASKEDOFF5]], [[MASKEDOFF6]], [[MASKEDOFF7]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 4 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 4 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 4 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 4 +// CHECK-RV64-NEXT: store [[TMP5]], ptr [[V4]], align 4 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 5 +// CHECK-RV64-NEXT: store [[TMP6]], ptr [[V5]], align 4 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 6 +// CHECK-RV64-NEXT: store [[TMP7]], ptr [[V6]], align 4 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 7 +// CHECK-RV64-NEXT: store [[TMP8]], ptr [[V7]], align 4 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 8 +// CHECK-RV64-NEXT: store i64 [[TMP9]], ptr [[NEW_VL]], align 4 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg8e32ff_v_i32m1_mu(vint32m1_t *v0, vint32m1_t *v1, vint32m1_t *v2, vint32m1_t *v3, vint32m1_t *v4, vint32m1_t *v5, vint32m1_t *v6, vint32m1_t *v7, vbool32_t mask, vint32m1_t maskedoff0, vint32m1_t maskedoff1, vint32m1_t maskedoff2, vint32m1_t maskedoff3, vint32m1_t maskedoff4, vint32m1_t maskedoff5, vint32m1_t maskedoff6, vint32m1_t maskedoff7, const int32_t *base, size_t *new_vl, size_t vl) { + return __riscv_vlseg8e32ff_mu(v0, v1, v2, v3, v4, v5, v6, v7, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, maskedoff4, maskedoff5, maskedoff6, maskedoff7, base, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlseg8e32ff_v_u32mf2_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], ptr noundef [[V4:%.*]], ptr noundef [[V5:%.*]], ptr noundef [[V6:%.*]], ptr noundef [[V7:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], [[MASKEDOFF4:%.*]], [[MASKEDOFF5:%.*]], [[MASKEDOFF6:%.*]], [[MASKEDOFF7:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , , i64 } @llvm.riscv.vlseg8ff.mask.nxv1i32.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], [[MASKEDOFF4]], [[MASKEDOFF5]], [[MASKEDOFF6]], [[MASKEDOFF7]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 4 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 4 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 4 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 4 +// CHECK-RV64-NEXT: store [[TMP5]], ptr [[V4]], align 4 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 5 +// CHECK-RV64-NEXT: store [[TMP6]], ptr [[V5]], align 4 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 6 +// CHECK-RV64-NEXT: store [[TMP7]], ptr [[V6]], align 4 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 7 +// CHECK-RV64-NEXT: store [[TMP8]], ptr [[V7]], align 4 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 8 +// CHECK-RV64-NEXT: store i64 [[TMP9]], ptr [[NEW_VL]], align 4 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg8e32ff_v_u32mf2_mu(vuint32mf2_t *v0, vuint32mf2_t *v1, vuint32mf2_t *v2, vuint32mf2_t *v3, vuint32mf2_t *v4, vuint32mf2_t *v5, vuint32mf2_t *v6, vuint32mf2_t *v7, vbool64_t mask, vuint32mf2_t maskedoff0, vuint32mf2_t maskedoff1, vuint32mf2_t maskedoff2, vuint32mf2_t maskedoff3, vuint32mf2_t maskedoff4, vuint32mf2_t maskedoff5, vuint32mf2_t maskedoff6, vuint32mf2_t maskedoff7, const uint32_t *base, size_t *new_vl, size_t vl) { + return __riscv_vlseg8e32ff_mu(v0, v1, v2, v3, v4, v5, v6, v7, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, maskedoff4, maskedoff5, maskedoff6, maskedoff7, base, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlseg8e32ff_v_u32m1_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], ptr noundef [[V4:%.*]], ptr noundef [[V5:%.*]], ptr noundef [[V6:%.*]], ptr noundef [[V7:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], [[MASKEDOFF4:%.*]], [[MASKEDOFF5:%.*]], [[MASKEDOFF6:%.*]], [[MASKEDOFF7:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , , i64 } @llvm.riscv.vlseg8ff.mask.nxv2i32.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], [[MASKEDOFF4]], [[MASKEDOFF5]], [[MASKEDOFF6]], [[MASKEDOFF7]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 4 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 4 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 4 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 4 +// CHECK-RV64-NEXT: store [[TMP5]], ptr [[V4]], align 4 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 5 +// CHECK-RV64-NEXT: store [[TMP6]], ptr [[V5]], align 4 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 6 +// CHECK-RV64-NEXT: store [[TMP7]], ptr [[V6]], align 4 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 7 +// CHECK-RV64-NEXT: store [[TMP8]], ptr [[V7]], align 4 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 8 +// CHECK-RV64-NEXT: store i64 [[TMP9]], ptr [[NEW_VL]], align 4 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg8e32ff_v_u32m1_mu(vuint32m1_t *v0, vuint32m1_t *v1, vuint32m1_t *v2, vuint32m1_t *v3, vuint32m1_t *v4, vuint32m1_t *v5, vuint32m1_t *v6, vuint32m1_t *v7, vbool32_t mask, vuint32m1_t maskedoff0, vuint32m1_t maskedoff1, vuint32m1_t maskedoff2, vuint32m1_t maskedoff3, vuint32m1_t maskedoff4, vuint32m1_t maskedoff5, vuint32m1_t maskedoff6, vuint32m1_t maskedoff7, const uint32_t *base, size_t *new_vl, size_t vl) { + return __riscv_vlseg8e32ff_mu(v0, v1, v2, v3, v4, v5, v6, v7, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, maskedoff4, maskedoff5, maskedoff6, maskedoff7, base, new_vl, vl); +} + diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e64.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e64.c index 1f447b43437e3..90e3772b236a3 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e64.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e64.c @@ -241,3 +241,81 @@ void test_vlseg8e64_v_u64m1_tumu(vuint64m1_t *v0, vuint64m1_t *v1, vuint64m1_t * return __riscv_vlseg8e64_tumu(v0, v1, v2, v3, v4, v5, v6, v7, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, maskedoff4, maskedoff5, maskedoff6, maskedoff7, base, vl); } +// CHECK-RV64-LABEL: define dso_local void @test_vlseg8e64_v_f64m1_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], ptr noundef [[V4:%.*]], ptr noundef [[V5:%.*]], ptr noundef [[V6:%.*]], ptr noundef [[V7:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], [[MASKEDOFF4:%.*]], [[MASKEDOFF5:%.*]], [[MASKEDOFF6:%.*]], [[MASKEDOFF7:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vlseg8.mask.nxv1f64.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], [[MASKEDOFF4]], [[MASKEDOFF5]], [[MASKEDOFF6]], [[MASKEDOFF7]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 8 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 8 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 8 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 8 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 4 +// CHECK-RV64-NEXT: store [[TMP5]], ptr [[V4]], align 8 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 5 +// CHECK-RV64-NEXT: store [[TMP6]], ptr [[V5]], align 8 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 6 +// CHECK-RV64-NEXT: store [[TMP7]], ptr [[V6]], align 8 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 7 +// CHECK-RV64-NEXT: store [[TMP8]], ptr [[V7]], align 8 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg8e64_v_f64m1_mu(vfloat64m1_t *v0, vfloat64m1_t *v1, vfloat64m1_t *v2, vfloat64m1_t *v3, vfloat64m1_t *v4, vfloat64m1_t *v5, vfloat64m1_t *v6, vfloat64m1_t *v7, vbool64_t mask, vfloat64m1_t maskedoff0, vfloat64m1_t maskedoff1, vfloat64m1_t maskedoff2, vfloat64m1_t maskedoff3, vfloat64m1_t maskedoff4, vfloat64m1_t maskedoff5, vfloat64m1_t maskedoff6, vfloat64m1_t maskedoff7, const double *base, size_t vl) { + return __riscv_vlseg8e64_mu(v0, v1, v2, v3, v4, v5, v6, v7, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, maskedoff4, maskedoff5, maskedoff6, maskedoff7, base, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlseg8e64_v_i64m1_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], ptr noundef [[V4:%.*]], ptr noundef [[V5:%.*]], ptr noundef [[V6:%.*]], ptr noundef [[V7:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], [[MASKEDOFF4:%.*]], [[MASKEDOFF5:%.*]], [[MASKEDOFF6:%.*]], [[MASKEDOFF7:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vlseg8.mask.nxv1i64.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], [[MASKEDOFF4]], [[MASKEDOFF5]], [[MASKEDOFF6]], [[MASKEDOFF7]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 8 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 8 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 8 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 8 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 4 +// CHECK-RV64-NEXT: store [[TMP5]], ptr [[V4]], align 8 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 5 +// CHECK-RV64-NEXT: store [[TMP6]], ptr [[V5]], align 8 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 6 +// CHECK-RV64-NEXT: store [[TMP7]], ptr [[V6]], align 8 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 7 +// CHECK-RV64-NEXT: store [[TMP8]], ptr [[V7]], align 8 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg8e64_v_i64m1_mu(vint64m1_t *v0, vint64m1_t *v1, vint64m1_t *v2, vint64m1_t *v3, vint64m1_t *v4, vint64m1_t *v5, vint64m1_t *v6, vint64m1_t *v7, vbool64_t mask, vint64m1_t maskedoff0, vint64m1_t maskedoff1, vint64m1_t maskedoff2, vint64m1_t maskedoff3, vint64m1_t maskedoff4, vint64m1_t maskedoff5, vint64m1_t maskedoff6, vint64m1_t maskedoff7, const int64_t *base, size_t vl) { + return __riscv_vlseg8e64_mu(v0, v1, v2, v3, v4, v5, v6, v7, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, maskedoff4, maskedoff5, maskedoff6, maskedoff7, base, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlseg8e64_v_u64m1_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], ptr noundef [[V4:%.*]], ptr noundef [[V5:%.*]], ptr noundef [[V6:%.*]], ptr noundef [[V7:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], [[MASKEDOFF4:%.*]], [[MASKEDOFF5:%.*]], [[MASKEDOFF6:%.*]], [[MASKEDOFF7:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vlseg8.mask.nxv1i64.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], [[MASKEDOFF4]], [[MASKEDOFF5]], [[MASKEDOFF6]], [[MASKEDOFF7]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 8 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 8 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 8 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 8 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 4 +// CHECK-RV64-NEXT: store [[TMP5]], ptr [[V4]], align 8 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 5 +// CHECK-RV64-NEXT: store [[TMP6]], ptr [[V5]], align 8 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 6 +// CHECK-RV64-NEXT: store [[TMP7]], ptr [[V6]], align 8 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 7 +// CHECK-RV64-NEXT: store [[TMP8]], ptr [[V7]], align 8 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg8e64_v_u64m1_mu(vuint64m1_t *v0, vuint64m1_t *v1, vuint64m1_t *v2, vuint64m1_t *v3, vuint64m1_t *v4, vuint64m1_t *v5, vuint64m1_t *v6, vuint64m1_t *v7, vbool64_t mask, vuint64m1_t maskedoff0, vuint64m1_t maskedoff1, vuint64m1_t maskedoff2, vuint64m1_t maskedoff3, vuint64m1_t maskedoff4, vuint64m1_t maskedoff5, vuint64m1_t maskedoff6, vuint64m1_t maskedoff7, const uint64_t *base, size_t vl) { + return __riscv_vlseg8e64_mu(v0, v1, v2, v3, v4, v5, v6, v7, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, maskedoff4, maskedoff5, maskedoff6, maskedoff7, base, vl); +} + diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e64ff.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e64ff.c index d7cd265b95b85..c1e59a765eaf7 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e64ff.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e64ff.c @@ -259,3 +259,87 @@ void test_vlseg8e64ff_v_u64m1_tumu(vuint64m1_t *v0, vuint64m1_t *v1, vuint64m1_t return __riscv_vlseg8e64ff_tumu(v0, v1, v2, v3, v4, v5, v6, v7, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, maskedoff4, maskedoff5, maskedoff6, maskedoff7, base, new_vl, vl); } +// CHECK-RV64-LABEL: define dso_local void @test_vlseg8e64ff_v_f64m1_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], ptr noundef [[V4:%.*]], ptr noundef [[V5:%.*]], ptr noundef [[V6:%.*]], ptr noundef [[V7:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], [[MASKEDOFF4:%.*]], [[MASKEDOFF5:%.*]], [[MASKEDOFF6:%.*]], [[MASKEDOFF7:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , , i64 } @llvm.riscv.vlseg8ff.mask.nxv1f64.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], [[MASKEDOFF4]], [[MASKEDOFF5]], [[MASKEDOFF6]], [[MASKEDOFF7]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 8 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 8 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 8 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 8 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 4 +// CHECK-RV64-NEXT: store [[TMP5]], ptr [[V4]], align 8 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 5 +// CHECK-RV64-NEXT: store [[TMP6]], ptr [[V5]], align 8 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 6 +// CHECK-RV64-NEXT: store [[TMP7]], ptr [[V6]], align 8 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 7 +// CHECK-RV64-NEXT: store [[TMP8]], ptr [[V7]], align 8 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 8 +// CHECK-RV64-NEXT: store i64 [[TMP9]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg8e64ff_v_f64m1_mu(vfloat64m1_t *v0, vfloat64m1_t *v1, vfloat64m1_t *v2, vfloat64m1_t *v3, vfloat64m1_t *v4, vfloat64m1_t *v5, vfloat64m1_t *v6, vfloat64m1_t *v7, vbool64_t mask, vfloat64m1_t maskedoff0, vfloat64m1_t maskedoff1, vfloat64m1_t maskedoff2, vfloat64m1_t maskedoff3, vfloat64m1_t maskedoff4, vfloat64m1_t maskedoff5, vfloat64m1_t maskedoff6, vfloat64m1_t maskedoff7, const double *base, size_t *new_vl, size_t vl) { + return __riscv_vlseg8e64ff_mu(v0, v1, v2, v3, v4, v5, v6, v7, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, maskedoff4, maskedoff5, maskedoff6, maskedoff7, base, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlseg8e64ff_v_i64m1_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], ptr noundef [[V4:%.*]], ptr noundef [[V5:%.*]], ptr noundef [[V6:%.*]], ptr noundef [[V7:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], [[MASKEDOFF4:%.*]], [[MASKEDOFF5:%.*]], [[MASKEDOFF6:%.*]], [[MASKEDOFF7:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , , i64 } @llvm.riscv.vlseg8ff.mask.nxv1i64.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], [[MASKEDOFF4]], [[MASKEDOFF5]], [[MASKEDOFF6]], [[MASKEDOFF7]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 8 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 8 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 8 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 8 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 4 +// CHECK-RV64-NEXT: store [[TMP5]], ptr [[V4]], align 8 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 5 +// CHECK-RV64-NEXT: store [[TMP6]], ptr [[V5]], align 8 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 6 +// CHECK-RV64-NEXT: store [[TMP7]], ptr [[V6]], align 8 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 7 +// CHECK-RV64-NEXT: store [[TMP8]], ptr [[V7]], align 8 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 8 +// CHECK-RV64-NEXT: store i64 [[TMP9]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg8e64ff_v_i64m1_mu(vint64m1_t *v0, vint64m1_t *v1, vint64m1_t *v2, vint64m1_t *v3, vint64m1_t *v4, vint64m1_t *v5, vint64m1_t *v6, vint64m1_t *v7, vbool64_t mask, vint64m1_t maskedoff0, vint64m1_t maskedoff1, vint64m1_t maskedoff2, vint64m1_t maskedoff3, vint64m1_t maskedoff4, vint64m1_t maskedoff5, vint64m1_t maskedoff6, vint64m1_t maskedoff7, const int64_t *base, size_t *new_vl, size_t vl) { + return __riscv_vlseg8e64ff_mu(v0, v1, v2, v3, v4, v5, v6, v7, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, maskedoff4, maskedoff5, maskedoff6, maskedoff7, base, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlseg8e64ff_v_u64m1_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], ptr noundef [[V4:%.*]], ptr noundef [[V5:%.*]], ptr noundef [[V6:%.*]], ptr noundef [[V7:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], [[MASKEDOFF4:%.*]], [[MASKEDOFF5:%.*]], [[MASKEDOFF6:%.*]], [[MASKEDOFF7:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , , i64 } @llvm.riscv.vlseg8ff.mask.nxv1i64.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], [[MASKEDOFF4]], [[MASKEDOFF5]], [[MASKEDOFF6]], [[MASKEDOFF7]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 8 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 8 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 8 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 8 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 4 +// CHECK-RV64-NEXT: store [[TMP5]], ptr [[V4]], align 8 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 5 +// CHECK-RV64-NEXT: store [[TMP6]], ptr [[V5]], align 8 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 6 +// CHECK-RV64-NEXT: store [[TMP7]], ptr [[V6]], align 8 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 7 +// CHECK-RV64-NEXT: store [[TMP8]], ptr [[V7]], align 8 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 8 +// CHECK-RV64-NEXT: store i64 [[TMP9]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg8e64ff_v_u64m1_mu(vuint64m1_t *v0, vuint64m1_t *v1, vuint64m1_t *v2, vuint64m1_t *v3, vuint64m1_t *v4, vuint64m1_t *v5, vuint64m1_t *v6, vuint64m1_t *v7, vbool64_t mask, vuint64m1_t maskedoff0, vuint64m1_t maskedoff1, vuint64m1_t maskedoff2, vuint64m1_t maskedoff3, vuint64m1_t maskedoff4, vuint64m1_t maskedoff5, vuint64m1_t maskedoff6, vuint64m1_t maskedoff7, const uint64_t *base, size_t *new_vl, size_t vl) { + return __riscv_vlseg8e64ff_mu(v0, v1, v2, v3, v4, v5, v6, v7, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, maskedoff4, maskedoff5, maskedoff6, maskedoff7, base, new_vl, vl); +} + diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e8.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e8.c index 019a723b165c1..fee7c63e44cb8 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e8.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e8.c @@ -630,3 +630,211 @@ void test_vlseg8e8_v_u8m1_tumu(vuint8m1_t *v0, vuint8m1_t *v1, vuint8m1_t *v2, v return __riscv_vlseg8e8_tumu(v0, v1, v2, v3, v4, v5, v6, v7, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, maskedoff4, maskedoff5, maskedoff6, maskedoff7, base, vl); } +// CHECK-RV64-LABEL: define dso_local void @test_vlseg8e8_v_i8mf8_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], ptr noundef [[V4:%.*]], ptr noundef [[V5:%.*]], ptr noundef [[V6:%.*]], ptr noundef [[V7:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], [[MASKEDOFF4:%.*]], [[MASKEDOFF5:%.*]], [[MASKEDOFF6:%.*]], [[MASKEDOFF7:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vlseg8.mask.nxv1i8.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], [[MASKEDOFF4]], [[MASKEDOFF5]], [[MASKEDOFF6]], [[MASKEDOFF7]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 1 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 1 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 1 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 4 +// CHECK-RV64-NEXT: store [[TMP5]], ptr [[V4]], align 1 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 5 +// CHECK-RV64-NEXT: store [[TMP6]], ptr [[V5]], align 1 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 6 +// CHECK-RV64-NEXT: store [[TMP7]], ptr [[V6]], align 1 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 7 +// CHECK-RV64-NEXT: store [[TMP8]], ptr [[V7]], align 1 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg8e8_v_i8mf8_mu(vint8mf8_t *v0, vint8mf8_t *v1, vint8mf8_t *v2, vint8mf8_t *v3, vint8mf8_t *v4, vint8mf8_t *v5, vint8mf8_t *v6, vint8mf8_t *v7, vbool64_t mask, vint8mf8_t maskedoff0, vint8mf8_t maskedoff1, vint8mf8_t maskedoff2, vint8mf8_t maskedoff3, vint8mf8_t maskedoff4, vint8mf8_t maskedoff5, vint8mf8_t maskedoff6, vint8mf8_t maskedoff7, const int8_t *base, size_t vl) { + return __riscv_vlseg8e8_mu(v0, v1, v2, v3, v4, v5, v6, v7, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, maskedoff4, maskedoff5, maskedoff6, maskedoff7, base, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlseg8e8_v_i8mf4_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], ptr noundef [[V4:%.*]], ptr noundef [[V5:%.*]], ptr noundef [[V6:%.*]], ptr noundef [[V7:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], [[MASKEDOFF4:%.*]], [[MASKEDOFF5:%.*]], [[MASKEDOFF6:%.*]], [[MASKEDOFF7:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vlseg8.mask.nxv2i8.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], [[MASKEDOFF4]], [[MASKEDOFF5]], [[MASKEDOFF6]], [[MASKEDOFF7]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 1 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 1 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 1 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 4 +// CHECK-RV64-NEXT: store [[TMP5]], ptr [[V4]], align 1 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 5 +// CHECK-RV64-NEXT: store [[TMP6]], ptr [[V5]], align 1 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 6 +// CHECK-RV64-NEXT: store [[TMP7]], ptr [[V6]], align 1 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 7 +// CHECK-RV64-NEXT: store [[TMP8]], ptr [[V7]], align 1 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg8e8_v_i8mf4_mu(vint8mf4_t *v0, vint8mf4_t *v1, vint8mf4_t *v2, vint8mf4_t *v3, vint8mf4_t *v4, vint8mf4_t *v5, vint8mf4_t *v6, vint8mf4_t *v7, vbool32_t mask, vint8mf4_t maskedoff0, vint8mf4_t maskedoff1, vint8mf4_t maskedoff2, vint8mf4_t maskedoff3, vint8mf4_t maskedoff4, vint8mf4_t maskedoff5, vint8mf4_t maskedoff6, vint8mf4_t maskedoff7, const int8_t *base, size_t vl) { + return __riscv_vlseg8e8_mu(v0, v1, v2, v3, v4, v5, v6, v7, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, maskedoff4, maskedoff5, maskedoff6, maskedoff7, base, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlseg8e8_v_i8mf2_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], ptr noundef [[V4:%.*]], ptr noundef [[V5:%.*]], ptr noundef [[V6:%.*]], ptr noundef [[V7:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], [[MASKEDOFF4:%.*]], [[MASKEDOFF5:%.*]], [[MASKEDOFF6:%.*]], [[MASKEDOFF7:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vlseg8.mask.nxv4i8.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], [[MASKEDOFF4]], [[MASKEDOFF5]], [[MASKEDOFF6]], [[MASKEDOFF7]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 1 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 1 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 1 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 4 +// CHECK-RV64-NEXT: store [[TMP5]], ptr [[V4]], align 1 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 5 +// CHECK-RV64-NEXT: store [[TMP6]], ptr [[V5]], align 1 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 6 +// CHECK-RV64-NEXT: store [[TMP7]], ptr [[V6]], align 1 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 7 +// CHECK-RV64-NEXT: store [[TMP8]], ptr [[V7]], align 1 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg8e8_v_i8mf2_mu(vint8mf2_t *v0, vint8mf2_t *v1, vint8mf2_t *v2, vint8mf2_t *v3, vint8mf2_t *v4, vint8mf2_t *v5, vint8mf2_t *v6, vint8mf2_t *v7, vbool16_t mask, vint8mf2_t maskedoff0, vint8mf2_t maskedoff1, vint8mf2_t maskedoff2, vint8mf2_t maskedoff3, vint8mf2_t maskedoff4, vint8mf2_t maskedoff5, vint8mf2_t maskedoff6, vint8mf2_t maskedoff7, const int8_t *base, size_t vl) { + return __riscv_vlseg8e8_mu(v0, v1, v2, v3, v4, v5, v6, v7, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, maskedoff4, maskedoff5, maskedoff6, maskedoff7, base, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlseg8e8_v_i8m1_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], ptr noundef [[V4:%.*]], ptr noundef [[V5:%.*]], ptr noundef [[V6:%.*]], ptr noundef [[V7:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], [[MASKEDOFF4:%.*]], [[MASKEDOFF5:%.*]], [[MASKEDOFF6:%.*]], [[MASKEDOFF7:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vlseg8.mask.nxv8i8.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], [[MASKEDOFF4]], [[MASKEDOFF5]], [[MASKEDOFF6]], [[MASKEDOFF7]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 1 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 1 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 1 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 4 +// CHECK-RV64-NEXT: store [[TMP5]], ptr [[V4]], align 1 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 5 +// CHECK-RV64-NEXT: store [[TMP6]], ptr [[V5]], align 1 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 6 +// CHECK-RV64-NEXT: store [[TMP7]], ptr [[V6]], align 1 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 7 +// CHECK-RV64-NEXT: store [[TMP8]], ptr [[V7]], align 1 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg8e8_v_i8m1_mu(vint8m1_t *v0, vint8m1_t *v1, vint8m1_t *v2, vint8m1_t *v3, vint8m1_t *v4, vint8m1_t *v5, vint8m1_t *v6, vint8m1_t *v7, vbool8_t mask, vint8m1_t maskedoff0, vint8m1_t maskedoff1, vint8m1_t maskedoff2, vint8m1_t maskedoff3, vint8m1_t maskedoff4, vint8m1_t maskedoff5, vint8m1_t maskedoff6, vint8m1_t maskedoff7, const int8_t *base, size_t vl) { + return __riscv_vlseg8e8_mu(v0, v1, v2, v3, v4, v5, v6, v7, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, maskedoff4, maskedoff5, maskedoff6, maskedoff7, base, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlseg8e8_v_u8mf8_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], ptr noundef [[V4:%.*]], ptr noundef [[V5:%.*]], ptr noundef [[V6:%.*]], ptr noundef [[V7:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], [[MASKEDOFF4:%.*]], [[MASKEDOFF5:%.*]], [[MASKEDOFF6:%.*]], [[MASKEDOFF7:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vlseg8.mask.nxv1i8.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], [[MASKEDOFF4]], [[MASKEDOFF5]], [[MASKEDOFF6]], [[MASKEDOFF7]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 1 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 1 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 1 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 4 +// CHECK-RV64-NEXT: store [[TMP5]], ptr [[V4]], align 1 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 5 +// CHECK-RV64-NEXT: store [[TMP6]], ptr [[V5]], align 1 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 6 +// CHECK-RV64-NEXT: store [[TMP7]], ptr [[V6]], align 1 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 7 +// CHECK-RV64-NEXT: store [[TMP8]], ptr [[V7]], align 1 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg8e8_v_u8mf8_mu(vuint8mf8_t *v0, vuint8mf8_t *v1, vuint8mf8_t *v2, vuint8mf8_t *v3, vuint8mf8_t *v4, vuint8mf8_t *v5, vuint8mf8_t *v6, vuint8mf8_t *v7, vbool64_t mask, vuint8mf8_t maskedoff0, vuint8mf8_t maskedoff1, vuint8mf8_t maskedoff2, vuint8mf8_t maskedoff3, vuint8mf8_t maskedoff4, vuint8mf8_t maskedoff5, vuint8mf8_t maskedoff6, vuint8mf8_t maskedoff7, const uint8_t *base, size_t vl) { + return __riscv_vlseg8e8_mu(v0, v1, v2, v3, v4, v5, v6, v7, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, maskedoff4, maskedoff5, maskedoff6, maskedoff7, base, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlseg8e8_v_u8mf4_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], ptr noundef [[V4:%.*]], ptr noundef [[V5:%.*]], ptr noundef [[V6:%.*]], ptr noundef [[V7:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], [[MASKEDOFF4:%.*]], [[MASKEDOFF5:%.*]], [[MASKEDOFF6:%.*]], [[MASKEDOFF7:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vlseg8.mask.nxv2i8.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], [[MASKEDOFF4]], [[MASKEDOFF5]], [[MASKEDOFF6]], [[MASKEDOFF7]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 1 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 1 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 1 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 4 +// CHECK-RV64-NEXT: store [[TMP5]], ptr [[V4]], align 1 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 5 +// CHECK-RV64-NEXT: store [[TMP6]], ptr [[V5]], align 1 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 6 +// CHECK-RV64-NEXT: store [[TMP7]], ptr [[V6]], align 1 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 7 +// CHECK-RV64-NEXT: store [[TMP8]], ptr [[V7]], align 1 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg8e8_v_u8mf4_mu(vuint8mf4_t *v0, vuint8mf4_t *v1, vuint8mf4_t *v2, vuint8mf4_t *v3, vuint8mf4_t *v4, vuint8mf4_t *v5, vuint8mf4_t *v6, vuint8mf4_t *v7, vbool32_t mask, vuint8mf4_t maskedoff0, vuint8mf4_t maskedoff1, vuint8mf4_t maskedoff2, vuint8mf4_t maskedoff3, vuint8mf4_t maskedoff4, vuint8mf4_t maskedoff5, vuint8mf4_t maskedoff6, vuint8mf4_t maskedoff7, const uint8_t *base, size_t vl) { + return __riscv_vlseg8e8_mu(v0, v1, v2, v3, v4, v5, v6, v7, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, maskedoff4, maskedoff5, maskedoff6, maskedoff7, base, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlseg8e8_v_u8mf2_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], ptr noundef [[V4:%.*]], ptr noundef [[V5:%.*]], ptr noundef [[V6:%.*]], ptr noundef [[V7:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], [[MASKEDOFF4:%.*]], [[MASKEDOFF5:%.*]], [[MASKEDOFF6:%.*]], [[MASKEDOFF7:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vlseg8.mask.nxv4i8.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], [[MASKEDOFF4]], [[MASKEDOFF5]], [[MASKEDOFF6]], [[MASKEDOFF7]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 1 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 1 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 1 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 4 +// CHECK-RV64-NEXT: store [[TMP5]], ptr [[V4]], align 1 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 5 +// CHECK-RV64-NEXT: store [[TMP6]], ptr [[V5]], align 1 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 6 +// CHECK-RV64-NEXT: store [[TMP7]], ptr [[V6]], align 1 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 7 +// CHECK-RV64-NEXT: store [[TMP8]], ptr [[V7]], align 1 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg8e8_v_u8mf2_mu(vuint8mf2_t *v0, vuint8mf2_t *v1, vuint8mf2_t *v2, vuint8mf2_t *v3, vuint8mf2_t *v4, vuint8mf2_t *v5, vuint8mf2_t *v6, vuint8mf2_t *v7, vbool16_t mask, vuint8mf2_t maskedoff0, vuint8mf2_t maskedoff1, vuint8mf2_t maskedoff2, vuint8mf2_t maskedoff3, vuint8mf2_t maskedoff4, vuint8mf2_t maskedoff5, vuint8mf2_t maskedoff6, vuint8mf2_t maskedoff7, const uint8_t *base, size_t vl) { + return __riscv_vlseg8e8_mu(v0, v1, v2, v3, v4, v5, v6, v7, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, maskedoff4, maskedoff5, maskedoff6, maskedoff7, base, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlseg8e8_v_u8m1_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], ptr noundef [[V4:%.*]], ptr noundef [[V5:%.*]], ptr noundef [[V6:%.*]], ptr noundef [[V7:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], [[MASKEDOFF4:%.*]], [[MASKEDOFF5:%.*]], [[MASKEDOFF6:%.*]], [[MASKEDOFF7:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vlseg8.mask.nxv8i8.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], [[MASKEDOFF4]], [[MASKEDOFF5]], [[MASKEDOFF6]], [[MASKEDOFF7]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 1 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 1 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 1 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 4 +// CHECK-RV64-NEXT: store [[TMP5]], ptr [[V4]], align 1 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 5 +// CHECK-RV64-NEXT: store [[TMP6]], ptr [[V5]], align 1 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 6 +// CHECK-RV64-NEXT: store [[TMP7]], ptr [[V6]], align 1 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 7 +// CHECK-RV64-NEXT: store [[TMP8]], ptr [[V7]], align 1 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg8e8_v_u8m1_mu(vuint8m1_t *v0, vuint8m1_t *v1, vuint8m1_t *v2, vuint8m1_t *v3, vuint8m1_t *v4, vuint8m1_t *v5, vuint8m1_t *v6, vuint8m1_t *v7, vbool8_t mask, vuint8m1_t maskedoff0, vuint8m1_t maskedoff1, vuint8m1_t maskedoff2, vuint8m1_t maskedoff3, vuint8m1_t maskedoff4, vuint8m1_t maskedoff5, vuint8m1_t maskedoff6, vuint8m1_t maskedoff7, const uint8_t *base, size_t vl) { + return __riscv_vlseg8e8_mu(v0, v1, v2, v3, v4, v5, v6, v7, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, maskedoff4, maskedoff5, maskedoff6, maskedoff7, base, vl); +} + diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e8ff.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e8ff.c index 7f86990842427..5a5db4f4a6811 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e8ff.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e8ff.c @@ -679,3 +679,227 @@ void test_vlseg8e8ff_v_u8m1_tumu(vuint8m1_t *v0, vuint8m1_t *v1, vuint8m1_t *v2, return __riscv_vlseg8e8ff_tumu(v0, v1, v2, v3, v4, v5, v6, v7, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, maskedoff4, maskedoff5, maskedoff6, maskedoff7, base, new_vl, vl); } +// CHECK-RV64-LABEL: define dso_local void @test_vlseg8e8ff_v_i8mf8_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], ptr noundef [[V4:%.*]], ptr noundef [[V5:%.*]], ptr noundef [[V6:%.*]], ptr noundef [[V7:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], [[MASKEDOFF4:%.*]], [[MASKEDOFF5:%.*]], [[MASKEDOFF6:%.*]], [[MASKEDOFF7:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , , i64 } @llvm.riscv.vlseg8ff.mask.nxv1i8.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], [[MASKEDOFF4]], [[MASKEDOFF5]], [[MASKEDOFF6]], [[MASKEDOFF7]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 1 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 1 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 1 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 4 +// CHECK-RV64-NEXT: store [[TMP5]], ptr [[V4]], align 1 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 5 +// CHECK-RV64-NEXT: store [[TMP6]], ptr [[V5]], align 1 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 6 +// CHECK-RV64-NEXT: store [[TMP7]], ptr [[V6]], align 1 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 7 +// CHECK-RV64-NEXT: store [[TMP8]], ptr [[V7]], align 1 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 8 +// CHECK-RV64-NEXT: store i64 [[TMP9]], ptr [[NEW_VL]], align 1 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg8e8ff_v_i8mf8_mu(vint8mf8_t *v0, vint8mf8_t *v1, vint8mf8_t *v2, vint8mf8_t *v3, vint8mf8_t *v4, vint8mf8_t *v5, vint8mf8_t *v6, vint8mf8_t *v7, vbool64_t mask, vint8mf8_t maskedoff0, vint8mf8_t maskedoff1, vint8mf8_t maskedoff2, vint8mf8_t maskedoff3, vint8mf8_t maskedoff4, vint8mf8_t maskedoff5, vint8mf8_t maskedoff6, vint8mf8_t maskedoff7, const int8_t *base, size_t *new_vl, size_t vl) { + return __riscv_vlseg8e8ff_mu(v0, v1, v2, v3, v4, v5, v6, v7, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, maskedoff4, maskedoff5, maskedoff6, maskedoff7, base, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlseg8e8ff_v_i8mf4_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], ptr noundef [[V4:%.*]], ptr noundef [[V5:%.*]], ptr noundef [[V6:%.*]], ptr noundef [[V7:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], [[MASKEDOFF4:%.*]], [[MASKEDOFF5:%.*]], [[MASKEDOFF6:%.*]], [[MASKEDOFF7:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , , i64 } @llvm.riscv.vlseg8ff.mask.nxv2i8.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], [[MASKEDOFF4]], [[MASKEDOFF5]], [[MASKEDOFF6]], [[MASKEDOFF7]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 1 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 1 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 1 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 4 +// CHECK-RV64-NEXT: store [[TMP5]], ptr [[V4]], align 1 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 5 +// CHECK-RV64-NEXT: store [[TMP6]], ptr [[V5]], align 1 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 6 +// CHECK-RV64-NEXT: store [[TMP7]], ptr [[V6]], align 1 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 7 +// CHECK-RV64-NEXT: store [[TMP8]], ptr [[V7]], align 1 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 8 +// CHECK-RV64-NEXT: store i64 [[TMP9]], ptr [[NEW_VL]], align 1 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg8e8ff_v_i8mf4_mu(vint8mf4_t *v0, vint8mf4_t *v1, vint8mf4_t *v2, vint8mf4_t *v3, vint8mf4_t *v4, vint8mf4_t *v5, vint8mf4_t *v6, vint8mf4_t *v7, vbool32_t mask, vint8mf4_t maskedoff0, vint8mf4_t maskedoff1, vint8mf4_t maskedoff2, vint8mf4_t maskedoff3, vint8mf4_t maskedoff4, vint8mf4_t maskedoff5, vint8mf4_t maskedoff6, vint8mf4_t maskedoff7, const int8_t *base, size_t *new_vl, size_t vl) { + return __riscv_vlseg8e8ff_mu(v0, v1, v2, v3, v4, v5, v6, v7, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, maskedoff4, maskedoff5, maskedoff6, maskedoff7, base, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlseg8e8ff_v_i8mf2_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], ptr noundef [[V4:%.*]], ptr noundef [[V5:%.*]], ptr noundef [[V6:%.*]], ptr noundef [[V7:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], [[MASKEDOFF4:%.*]], [[MASKEDOFF5:%.*]], [[MASKEDOFF6:%.*]], [[MASKEDOFF7:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , , i64 } @llvm.riscv.vlseg8ff.mask.nxv4i8.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], [[MASKEDOFF4]], [[MASKEDOFF5]], [[MASKEDOFF6]], [[MASKEDOFF7]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 1 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 1 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 1 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 4 +// CHECK-RV64-NEXT: store [[TMP5]], ptr [[V4]], align 1 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 5 +// CHECK-RV64-NEXT: store [[TMP6]], ptr [[V5]], align 1 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 6 +// CHECK-RV64-NEXT: store [[TMP7]], ptr [[V6]], align 1 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 7 +// CHECK-RV64-NEXT: store [[TMP8]], ptr [[V7]], align 1 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 8 +// CHECK-RV64-NEXT: store i64 [[TMP9]], ptr [[NEW_VL]], align 1 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg8e8ff_v_i8mf2_mu(vint8mf2_t *v0, vint8mf2_t *v1, vint8mf2_t *v2, vint8mf2_t *v3, vint8mf2_t *v4, vint8mf2_t *v5, vint8mf2_t *v6, vint8mf2_t *v7, vbool16_t mask, vint8mf2_t maskedoff0, vint8mf2_t maskedoff1, vint8mf2_t maskedoff2, vint8mf2_t maskedoff3, vint8mf2_t maskedoff4, vint8mf2_t maskedoff5, vint8mf2_t maskedoff6, vint8mf2_t maskedoff7, const int8_t *base, size_t *new_vl, size_t vl) { + return __riscv_vlseg8e8ff_mu(v0, v1, v2, v3, v4, v5, v6, v7, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, maskedoff4, maskedoff5, maskedoff6, maskedoff7, base, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlseg8e8ff_v_i8m1_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], ptr noundef [[V4:%.*]], ptr noundef [[V5:%.*]], ptr noundef [[V6:%.*]], ptr noundef [[V7:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], [[MASKEDOFF4:%.*]], [[MASKEDOFF5:%.*]], [[MASKEDOFF6:%.*]], [[MASKEDOFF7:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , , i64 } @llvm.riscv.vlseg8ff.mask.nxv8i8.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], [[MASKEDOFF4]], [[MASKEDOFF5]], [[MASKEDOFF6]], [[MASKEDOFF7]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 1 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 1 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 1 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 4 +// CHECK-RV64-NEXT: store [[TMP5]], ptr [[V4]], align 1 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 5 +// CHECK-RV64-NEXT: store [[TMP6]], ptr [[V5]], align 1 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 6 +// CHECK-RV64-NEXT: store [[TMP7]], ptr [[V6]], align 1 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 7 +// CHECK-RV64-NEXT: store [[TMP8]], ptr [[V7]], align 1 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 8 +// CHECK-RV64-NEXT: store i64 [[TMP9]], ptr [[NEW_VL]], align 1 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg8e8ff_v_i8m1_mu(vint8m1_t *v0, vint8m1_t *v1, vint8m1_t *v2, vint8m1_t *v3, vint8m1_t *v4, vint8m1_t *v5, vint8m1_t *v6, vint8m1_t *v7, vbool8_t mask, vint8m1_t maskedoff0, vint8m1_t maskedoff1, vint8m1_t maskedoff2, vint8m1_t maskedoff3, vint8m1_t maskedoff4, vint8m1_t maskedoff5, vint8m1_t maskedoff6, vint8m1_t maskedoff7, const int8_t *base, size_t *new_vl, size_t vl) { + return __riscv_vlseg8e8ff_mu(v0, v1, v2, v3, v4, v5, v6, v7, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, maskedoff4, maskedoff5, maskedoff6, maskedoff7, base, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlseg8e8ff_v_u8mf8_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], ptr noundef [[V4:%.*]], ptr noundef [[V5:%.*]], ptr noundef [[V6:%.*]], ptr noundef [[V7:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], [[MASKEDOFF4:%.*]], [[MASKEDOFF5:%.*]], [[MASKEDOFF6:%.*]], [[MASKEDOFF7:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , , i64 } @llvm.riscv.vlseg8ff.mask.nxv1i8.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], [[MASKEDOFF4]], [[MASKEDOFF5]], [[MASKEDOFF6]], [[MASKEDOFF7]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 1 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 1 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 1 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 4 +// CHECK-RV64-NEXT: store [[TMP5]], ptr [[V4]], align 1 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 5 +// CHECK-RV64-NEXT: store [[TMP6]], ptr [[V5]], align 1 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 6 +// CHECK-RV64-NEXT: store [[TMP7]], ptr [[V6]], align 1 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 7 +// CHECK-RV64-NEXT: store [[TMP8]], ptr [[V7]], align 1 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 8 +// CHECK-RV64-NEXT: store i64 [[TMP9]], ptr [[NEW_VL]], align 1 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg8e8ff_v_u8mf8_mu(vuint8mf8_t *v0, vuint8mf8_t *v1, vuint8mf8_t *v2, vuint8mf8_t *v3, vuint8mf8_t *v4, vuint8mf8_t *v5, vuint8mf8_t *v6, vuint8mf8_t *v7, vbool64_t mask, vuint8mf8_t maskedoff0, vuint8mf8_t maskedoff1, vuint8mf8_t maskedoff2, vuint8mf8_t maskedoff3, vuint8mf8_t maskedoff4, vuint8mf8_t maskedoff5, vuint8mf8_t maskedoff6, vuint8mf8_t maskedoff7, const uint8_t *base, size_t *new_vl, size_t vl) { + return __riscv_vlseg8e8ff_mu(v0, v1, v2, v3, v4, v5, v6, v7, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, maskedoff4, maskedoff5, maskedoff6, maskedoff7, base, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlseg8e8ff_v_u8mf4_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], ptr noundef [[V4:%.*]], ptr noundef [[V5:%.*]], ptr noundef [[V6:%.*]], ptr noundef [[V7:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], [[MASKEDOFF4:%.*]], [[MASKEDOFF5:%.*]], [[MASKEDOFF6:%.*]], [[MASKEDOFF7:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , , i64 } @llvm.riscv.vlseg8ff.mask.nxv2i8.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], [[MASKEDOFF4]], [[MASKEDOFF5]], [[MASKEDOFF6]], [[MASKEDOFF7]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 1 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 1 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 1 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 4 +// CHECK-RV64-NEXT: store [[TMP5]], ptr [[V4]], align 1 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 5 +// CHECK-RV64-NEXT: store [[TMP6]], ptr [[V5]], align 1 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 6 +// CHECK-RV64-NEXT: store [[TMP7]], ptr [[V6]], align 1 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 7 +// CHECK-RV64-NEXT: store [[TMP8]], ptr [[V7]], align 1 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 8 +// CHECK-RV64-NEXT: store i64 [[TMP9]], ptr [[NEW_VL]], align 1 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg8e8ff_v_u8mf4_mu(vuint8mf4_t *v0, vuint8mf4_t *v1, vuint8mf4_t *v2, vuint8mf4_t *v3, vuint8mf4_t *v4, vuint8mf4_t *v5, vuint8mf4_t *v6, vuint8mf4_t *v7, vbool32_t mask, vuint8mf4_t maskedoff0, vuint8mf4_t maskedoff1, vuint8mf4_t maskedoff2, vuint8mf4_t maskedoff3, vuint8mf4_t maskedoff4, vuint8mf4_t maskedoff5, vuint8mf4_t maskedoff6, vuint8mf4_t maskedoff7, const uint8_t *base, size_t *new_vl, size_t vl) { + return __riscv_vlseg8e8ff_mu(v0, v1, v2, v3, v4, v5, v6, v7, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, maskedoff4, maskedoff5, maskedoff6, maskedoff7, base, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlseg8e8ff_v_u8mf2_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], ptr noundef [[V4:%.*]], ptr noundef [[V5:%.*]], ptr noundef [[V6:%.*]], ptr noundef [[V7:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], [[MASKEDOFF4:%.*]], [[MASKEDOFF5:%.*]], [[MASKEDOFF6:%.*]], [[MASKEDOFF7:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , , i64 } @llvm.riscv.vlseg8ff.mask.nxv4i8.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], [[MASKEDOFF4]], [[MASKEDOFF5]], [[MASKEDOFF6]], [[MASKEDOFF7]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 1 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 1 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 1 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 4 +// CHECK-RV64-NEXT: store [[TMP5]], ptr [[V4]], align 1 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 5 +// CHECK-RV64-NEXT: store [[TMP6]], ptr [[V5]], align 1 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 6 +// CHECK-RV64-NEXT: store [[TMP7]], ptr [[V6]], align 1 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 7 +// CHECK-RV64-NEXT: store [[TMP8]], ptr [[V7]], align 1 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 8 +// CHECK-RV64-NEXT: store i64 [[TMP9]], ptr [[NEW_VL]], align 1 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg8e8ff_v_u8mf2_mu(vuint8mf2_t *v0, vuint8mf2_t *v1, vuint8mf2_t *v2, vuint8mf2_t *v3, vuint8mf2_t *v4, vuint8mf2_t *v5, vuint8mf2_t *v6, vuint8mf2_t *v7, vbool16_t mask, vuint8mf2_t maskedoff0, vuint8mf2_t maskedoff1, vuint8mf2_t maskedoff2, vuint8mf2_t maskedoff3, vuint8mf2_t maskedoff4, vuint8mf2_t maskedoff5, vuint8mf2_t maskedoff6, vuint8mf2_t maskedoff7, const uint8_t *base, size_t *new_vl, size_t vl) { + return __riscv_vlseg8e8ff_mu(v0, v1, v2, v3, v4, v5, v6, v7, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, maskedoff4, maskedoff5, maskedoff6, maskedoff7, base, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlseg8e8ff_v_u8m1_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], ptr noundef [[V4:%.*]], ptr noundef [[V5:%.*]], ptr noundef [[V6:%.*]], ptr noundef [[V7:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], [[MASKEDOFF4:%.*]], [[MASKEDOFF5:%.*]], [[MASKEDOFF6:%.*]], [[MASKEDOFF7:%.*]], ptr noundef [[BASE:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , , i64 } @llvm.riscv.vlseg8ff.mask.nxv8i8.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], [[MASKEDOFF4]], [[MASKEDOFF5]], [[MASKEDOFF6]], [[MASKEDOFF7]], ptr [[BASE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 1 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 1 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 1 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 4 +// CHECK-RV64-NEXT: store [[TMP5]], ptr [[V4]], align 1 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 5 +// CHECK-RV64-NEXT: store [[TMP6]], ptr [[V5]], align 1 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 6 +// CHECK-RV64-NEXT: store [[TMP7]], ptr [[V6]], align 1 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 7 +// CHECK-RV64-NEXT: store [[TMP8]], ptr [[V7]], align 1 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 8 +// CHECK-RV64-NEXT: store i64 [[TMP9]], ptr [[NEW_VL]], align 1 +// CHECK-RV64-NEXT: ret void +// +void test_vlseg8e8ff_v_u8m1_mu(vuint8m1_t *v0, vuint8m1_t *v1, vuint8m1_t *v2, vuint8m1_t *v3, vuint8m1_t *v4, vuint8m1_t *v5, vuint8m1_t *v6, vuint8m1_t *v7, vbool8_t mask, vuint8m1_t maskedoff0, vuint8m1_t maskedoff1, vuint8m1_t maskedoff2, vuint8m1_t maskedoff3, vuint8m1_t maskedoff4, vuint8m1_t maskedoff5, vuint8m1_t maskedoff6, vuint8m1_t maskedoff7, const uint8_t *base, size_t *new_vl, size_t vl) { + return __riscv_vlseg8e8ff_mu(v0, v1, v2, v3, v4, v5, v6, v7, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, maskedoff4, maskedoff5, maskedoff6, maskedoff7, base, new_vl, vl); +} + diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg2e16.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg2e16.c index 6734a724a2a23..8e5c40dedf0ee 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg2e16.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg2e16.c @@ -637,3 +637,213 @@ void test_vlsseg2e16_v_u16m4_tumu(vuint16m4_t *v0, vuint16m4_t *v1, vbool4_t mas return __riscv_vlsseg2e16_tumu(v0, v1, mask, maskedoff0, maskedoff1, base, bstride, vl); } +// CHECK-RV64-LABEL: define dso_local void @test_vlsseg2e16_v_f16mf4_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[BSTRIDE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vlsseg2.mask.nxv1f16.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], ptr [[BASE]], i64 [[BSTRIDE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 2 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 2 +// CHECK-RV64-NEXT: ret void +// +void test_vlsseg2e16_v_f16mf4_mu(vfloat16mf4_t *v0, vfloat16mf4_t *v1, vbool64_t mask, vfloat16mf4_t maskedoff0, vfloat16mf4_t maskedoff1, const _Float16 *base, ptrdiff_t bstride, size_t vl) { + return __riscv_vlsseg2e16_mu(v0, v1, mask, maskedoff0, maskedoff1, base, bstride, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlsseg2e16_v_f16mf2_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[BSTRIDE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vlsseg2.mask.nxv2f16.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], ptr [[BASE]], i64 [[BSTRIDE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 2 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 2 +// CHECK-RV64-NEXT: ret void +// +void test_vlsseg2e16_v_f16mf2_mu(vfloat16mf2_t *v0, vfloat16mf2_t *v1, vbool32_t mask, vfloat16mf2_t maskedoff0, vfloat16mf2_t maskedoff1, const _Float16 *base, ptrdiff_t bstride, size_t vl) { + return __riscv_vlsseg2e16_mu(v0, v1, mask, maskedoff0, maskedoff1, base, bstride, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlsseg2e16_v_f16m1_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[BSTRIDE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vlsseg2.mask.nxv4f16.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], ptr [[BASE]], i64 [[BSTRIDE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 2 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 2 +// CHECK-RV64-NEXT: ret void +// +void test_vlsseg2e16_v_f16m1_mu(vfloat16m1_t *v0, vfloat16m1_t *v1, vbool16_t mask, vfloat16m1_t maskedoff0, vfloat16m1_t maskedoff1, const _Float16 *base, ptrdiff_t bstride, size_t vl) { + return __riscv_vlsseg2e16_mu(v0, v1, mask, maskedoff0, maskedoff1, base, bstride, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlsseg2e16_v_f16m2_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[BSTRIDE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vlsseg2.mask.nxv8f16.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], ptr [[BASE]], i64 [[BSTRIDE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 2 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 2 +// CHECK-RV64-NEXT: ret void +// +void test_vlsseg2e16_v_f16m2_mu(vfloat16m2_t *v0, vfloat16m2_t *v1, vbool8_t mask, vfloat16m2_t maskedoff0, vfloat16m2_t maskedoff1, const _Float16 *base, ptrdiff_t bstride, size_t vl) { + return __riscv_vlsseg2e16_mu(v0, v1, mask, maskedoff0, maskedoff1, base, bstride, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlsseg2e16_v_f16m4_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[BSTRIDE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vlsseg2.mask.nxv16f16.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], ptr [[BASE]], i64 [[BSTRIDE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 2 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 2 +// CHECK-RV64-NEXT: ret void +// +void test_vlsseg2e16_v_f16m4_mu(vfloat16m4_t *v0, vfloat16m4_t *v1, vbool4_t mask, vfloat16m4_t maskedoff0, vfloat16m4_t maskedoff1, const _Float16 *base, ptrdiff_t bstride, size_t vl) { + return __riscv_vlsseg2e16_mu(v0, v1, mask, maskedoff0, maskedoff1, base, bstride, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlsseg2e16_v_i16mf4_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[BSTRIDE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vlsseg2.mask.nxv1i16.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], ptr [[BASE]], i64 [[BSTRIDE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 2 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 2 +// CHECK-RV64-NEXT: ret void +// +void test_vlsseg2e16_v_i16mf4_mu(vint16mf4_t *v0, vint16mf4_t *v1, vbool64_t mask, vint16mf4_t maskedoff0, vint16mf4_t maskedoff1, const int16_t *base, ptrdiff_t bstride, size_t vl) { + return __riscv_vlsseg2e16_mu(v0, v1, mask, maskedoff0, maskedoff1, base, bstride, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlsseg2e16_v_i16mf2_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[BSTRIDE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vlsseg2.mask.nxv2i16.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], ptr [[BASE]], i64 [[BSTRIDE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 2 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 2 +// CHECK-RV64-NEXT: ret void +// +void test_vlsseg2e16_v_i16mf2_mu(vint16mf2_t *v0, vint16mf2_t *v1, vbool32_t mask, vint16mf2_t maskedoff0, vint16mf2_t maskedoff1, const int16_t *base, ptrdiff_t bstride, size_t vl) { + return __riscv_vlsseg2e16_mu(v0, v1, mask, maskedoff0, maskedoff1, base, bstride, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlsseg2e16_v_i16m1_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[BSTRIDE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vlsseg2.mask.nxv4i16.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], ptr [[BASE]], i64 [[BSTRIDE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 2 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 2 +// CHECK-RV64-NEXT: ret void +// +void test_vlsseg2e16_v_i16m1_mu(vint16m1_t *v0, vint16m1_t *v1, vbool16_t mask, vint16m1_t maskedoff0, vint16m1_t maskedoff1, const int16_t *base, ptrdiff_t bstride, size_t vl) { + return __riscv_vlsseg2e16_mu(v0, v1, mask, maskedoff0, maskedoff1, base, bstride, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlsseg2e16_v_i16m2_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[BSTRIDE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vlsseg2.mask.nxv8i16.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], ptr [[BASE]], i64 [[BSTRIDE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 2 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 2 +// CHECK-RV64-NEXT: ret void +// +void test_vlsseg2e16_v_i16m2_mu(vint16m2_t *v0, vint16m2_t *v1, vbool8_t mask, vint16m2_t maskedoff0, vint16m2_t maskedoff1, const int16_t *base, ptrdiff_t bstride, size_t vl) { + return __riscv_vlsseg2e16_mu(v0, v1, mask, maskedoff0, maskedoff1, base, bstride, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlsseg2e16_v_i16m4_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[BSTRIDE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vlsseg2.mask.nxv16i16.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], ptr [[BASE]], i64 [[BSTRIDE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 2 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 2 +// CHECK-RV64-NEXT: ret void +// +void test_vlsseg2e16_v_i16m4_mu(vint16m4_t *v0, vint16m4_t *v1, vbool4_t mask, vint16m4_t maskedoff0, vint16m4_t maskedoff1, const int16_t *base, ptrdiff_t bstride, size_t vl) { + return __riscv_vlsseg2e16_mu(v0, v1, mask, maskedoff0, maskedoff1, base, bstride, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlsseg2e16_v_u16mf4_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[BSTRIDE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vlsseg2.mask.nxv1i16.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], ptr [[BASE]], i64 [[BSTRIDE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 2 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 2 +// CHECK-RV64-NEXT: ret void +// +void test_vlsseg2e16_v_u16mf4_mu(vuint16mf4_t *v0, vuint16mf4_t *v1, vbool64_t mask, vuint16mf4_t maskedoff0, vuint16mf4_t maskedoff1, const uint16_t *base, ptrdiff_t bstride, size_t vl) { + return __riscv_vlsseg2e16_mu(v0, v1, mask, maskedoff0, maskedoff1, base, bstride, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlsseg2e16_v_u16mf2_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[BSTRIDE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vlsseg2.mask.nxv2i16.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], ptr [[BASE]], i64 [[BSTRIDE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 2 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 2 +// CHECK-RV64-NEXT: ret void +// +void test_vlsseg2e16_v_u16mf2_mu(vuint16mf2_t *v0, vuint16mf2_t *v1, vbool32_t mask, vuint16mf2_t maskedoff0, vuint16mf2_t maskedoff1, const uint16_t *base, ptrdiff_t bstride, size_t vl) { + return __riscv_vlsseg2e16_mu(v0, v1, mask, maskedoff0, maskedoff1, base, bstride, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlsseg2e16_v_u16m1_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[BSTRIDE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vlsseg2.mask.nxv4i16.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], ptr [[BASE]], i64 [[BSTRIDE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 2 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 2 +// CHECK-RV64-NEXT: ret void +// +void test_vlsseg2e16_v_u16m1_mu(vuint16m1_t *v0, vuint16m1_t *v1, vbool16_t mask, vuint16m1_t maskedoff0, vuint16m1_t maskedoff1, const uint16_t *base, ptrdiff_t bstride, size_t vl) { + return __riscv_vlsseg2e16_mu(v0, v1, mask, maskedoff0, maskedoff1, base, bstride, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlsseg2e16_v_u16m2_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[BSTRIDE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vlsseg2.mask.nxv8i16.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], ptr [[BASE]], i64 [[BSTRIDE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 2 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 2 +// CHECK-RV64-NEXT: ret void +// +void test_vlsseg2e16_v_u16m2_mu(vuint16m2_t *v0, vuint16m2_t *v1, vbool8_t mask, vuint16m2_t maskedoff0, vuint16m2_t maskedoff1, const uint16_t *base, ptrdiff_t bstride, size_t vl) { + return __riscv_vlsseg2e16_mu(v0, v1, mask, maskedoff0, maskedoff1, base, bstride, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlsseg2e16_v_u16m4_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[BSTRIDE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vlsseg2.mask.nxv16i16.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], ptr [[BASE]], i64 [[BSTRIDE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 2 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 2 +// CHECK-RV64-NEXT: ret void +// +void test_vlsseg2e16_v_u16m4_mu(vuint16m4_t *v0, vuint16m4_t *v1, vbool4_t mask, vuint16m4_t maskedoff0, vuint16m4_t maskedoff1, const uint16_t *base, ptrdiff_t bstride, size_t vl) { + return __riscv_vlsseg2e16_mu(v0, v1, mask, maskedoff0, maskedoff1, base, bstride, vl); +} + diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg2e32.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg2e32.c index 7dbc38b3335c3..4a7d3ce81bc53 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg2e32.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg2e32.c @@ -511,3 +511,171 @@ void test_vlsseg2e32_v_u32m4_tumu(vuint32m4_t *v0, vuint32m4_t *v1, vbool8_t mas return __riscv_vlsseg2e32_tumu(v0, v1, mask, maskedoff0, maskedoff1, base, bstride, vl); } +// CHECK-RV64-LABEL: define dso_local void @test_vlsseg2e32_v_f32mf2_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[BSTRIDE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vlsseg2.mask.nxv1f32.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], ptr [[BASE]], i64 [[BSTRIDE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 4 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 4 +// CHECK-RV64-NEXT: ret void +// +void test_vlsseg2e32_v_f32mf2_mu(vfloat32mf2_t *v0, vfloat32mf2_t *v1, vbool64_t mask, vfloat32mf2_t maskedoff0, vfloat32mf2_t maskedoff1, const float *base, ptrdiff_t bstride, size_t vl) { + return __riscv_vlsseg2e32_mu(v0, v1, mask, maskedoff0, maskedoff1, base, bstride, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlsseg2e32_v_f32m1_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[BSTRIDE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vlsseg2.mask.nxv2f32.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], ptr [[BASE]], i64 [[BSTRIDE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 4 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 4 +// CHECK-RV64-NEXT: ret void +// +void test_vlsseg2e32_v_f32m1_mu(vfloat32m1_t *v0, vfloat32m1_t *v1, vbool32_t mask, vfloat32m1_t maskedoff0, vfloat32m1_t maskedoff1, const float *base, ptrdiff_t bstride, size_t vl) { + return __riscv_vlsseg2e32_mu(v0, v1, mask, maskedoff0, maskedoff1, base, bstride, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlsseg2e32_v_f32m2_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[BSTRIDE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vlsseg2.mask.nxv4f32.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], ptr [[BASE]], i64 [[BSTRIDE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 4 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 4 +// CHECK-RV64-NEXT: ret void +// +void test_vlsseg2e32_v_f32m2_mu(vfloat32m2_t *v0, vfloat32m2_t *v1, vbool16_t mask, vfloat32m2_t maskedoff0, vfloat32m2_t maskedoff1, const float *base, ptrdiff_t bstride, size_t vl) { + return __riscv_vlsseg2e32_mu(v0, v1, mask, maskedoff0, maskedoff1, base, bstride, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlsseg2e32_v_f32m4_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[BSTRIDE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vlsseg2.mask.nxv8f32.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], ptr [[BASE]], i64 [[BSTRIDE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 4 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 4 +// CHECK-RV64-NEXT: ret void +// +void test_vlsseg2e32_v_f32m4_mu(vfloat32m4_t *v0, vfloat32m4_t *v1, vbool8_t mask, vfloat32m4_t maskedoff0, vfloat32m4_t maskedoff1, const float *base, ptrdiff_t bstride, size_t vl) { + return __riscv_vlsseg2e32_mu(v0, v1, mask, maskedoff0, maskedoff1, base, bstride, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlsseg2e32_v_i32mf2_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[BSTRIDE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vlsseg2.mask.nxv1i32.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], ptr [[BASE]], i64 [[BSTRIDE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 4 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 4 +// CHECK-RV64-NEXT: ret void +// +void test_vlsseg2e32_v_i32mf2_mu(vint32mf2_t *v0, vint32mf2_t *v1, vbool64_t mask, vint32mf2_t maskedoff0, vint32mf2_t maskedoff1, const int32_t *base, ptrdiff_t bstride, size_t vl) { + return __riscv_vlsseg2e32_mu(v0, v1, mask, maskedoff0, maskedoff1, base, bstride, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlsseg2e32_v_i32m1_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[BSTRIDE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vlsseg2.mask.nxv2i32.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], ptr [[BASE]], i64 [[BSTRIDE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 4 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 4 +// CHECK-RV64-NEXT: ret void +// +void test_vlsseg2e32_v_i32m1_mu(vint32m1_t *v0, vint32m1_t *v1, vbool32_t mask, vint32m1_t maskedoff0, vint32m1_t maskedoff1, const int32_t *base, ptrdiff_t bstride, size_t vl) { + return __riscv_vlsseg2e32_mu(v0, v1, mask, maskedoff0, maskedoff1, base, bstride, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlsseg2e32_v_i32m2_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[BSTRIDE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vlsseg2.mask.nxv4i32.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], ptr [[BASE]], i64 [[BSTRIDE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 4 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 4 +// CHECK-RV64-NEXT: ret void +// +void test_vlsseg2e32_v_i32m2_mu(vint32m2_t *v0, vint32m2_t *v1, vbool16_t mask, vint32m2_t maskedoff0, vint32m2_t maskedoff1, const int32_t *base, ptrdiff_t bstride, size_t vl) { + return __riscv_vlsseg2e32_mu(v0, v1, mask, maskedoff0, maskedoff1, base, bstride, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlsseg2e32_v_i32m4_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[BSTRIDE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vlsseg2.mask.nxv8i32.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], ptr [[BASE]], i64 [[BSTRIDE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 4 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 4 +// CHECK-RV64-NEXT: ret void +// +void test_vlsseg2e32_v_i32m4_mu(vint32m4_t *v0, vint32m4_t *v1, vbool8_t mask, vint32m4_t maskedoff0, vint32m4_t maskedoff1, const int32_t *base, ptrdiff_t bstride, size_t vl) { + return __riscv_vlsseg2e32_mu(v0, v1, mask, maskedoff0, maskedoff1, base, bstride, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlsseg2e32_v_u32mf2_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[BSTRIDE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vlsseg2.mask.nxv1i32.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], ptr [[BASE]], i64 [[BSTRIDE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 4 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 4 +// CHECK-RV64-NEXT: ret void +// +void test_vlsseg2e32_v_u32mf2_mu(vuint32mf2_t *v0, vuint32mf2_t *v1, vbool64_t mask, vuint32mf2_t maskedoff0, vuint32mf2_t maskedoff1, const uint32_t *base, ptrdiff_t bstride, size_t vl) { + return __riscv_vlsseg2e32_mu(v0, v1, mask, maskedoff0, maskedoff1, base, bstride, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlsseg2e32_v_u32m1_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[BSTRIDE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vlsseg2.mask.nxv2i32.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], ptr [[BASE]], i64 [[BSTRIDE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 4 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 4 +// CHECK-RV64-NEXT: ret void +// +void test_vlsseg2e32_v_u32m1_mu(vuint32m1_t *v0, vuint32m1_t *v1, vbool32_t mask, vuint32m1_t maskedoff0, vuint32m1_t maskedoff1, const uint32_t *base, ptrdiff_t bstride, size_t vl) { + return __riscv_vlsseg2e32_mu(v0, v1, mask, maskedoff0, maskedoff1, base, bstride, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlsseg2e32_v_u32m2_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[BSTRIDE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vlsseg2.mask.nxv4i32.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], ptr [[BASE]], i64 [[BSTRIDE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 4 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 4 +// CHECK-RV64-NEXT: ret void +// +void test_vlsseg2e32_v_u32m2_mu(vuint32m2_t *v0, vuint32m2_t *v1, vbool16_t mask, vuint32m2_t maskedoff0, vuint32m2_t maskedoff1, const uint32_t *base, ptrdiff_t bstride, size_t vl) { + return __riscv_vlsseg2e32_mu(v0, v1, mask, maskedoff0, maskedoff1, base, bstride, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlsseg2e32_v_u32m4_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[BSTRIDE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vlsseg2.mask.nxv8i32.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], ptr [[BASE]], i64 [[BSTRIDE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 4 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 4 +// CHECK-RV64-NEXT: ret void +// +void test_vlsseg2e32_v_u32m4_mu(vuint32m4_t *v0, vuint32m4_t *v1, vbool8_t mask, vuint32m4_t maskedoff0, vuint32m4_t maskedoff1, const uint32_t *base, ptrdiff_t bstride, size_t vl) { + return __riscv_vlsseg2e32_mu(v0, v1, mask, maskedoff0, maskedoff1, base, bstride, vl); +} + diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg2e64.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg2e64.c index eb354caa1b11e..34d00f525c3e1 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg2e64.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg2e64.c @@ -385,3 +385,129 @@ void test_vlsseg2e64_v_u64m4_tumu(vuint64m4_t *v0, vuint64m4_t *v1, vbool16_t ma return __riscv_vlsseg2e64_tumu(v0, v1, mask, maskedoff0, maskedoff1, base, bstride, vl); } +// CHECK-RV64-LABEL: define dso_local void @test_vlsseg2e64_v_f64m1_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[BSTRIDE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vlsseg2.mask.nxv1f64.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], ptr [[BASE]], i64 [[BSTRIDE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 8 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 8 +// CHECK-RV64-NEXT: ret void +// +void test_vlsseg2e64_v_f64m1_mu(vfloat64m1_t *v0, vfloat64m1_t *v1, vbool64_t mask, vfloat64m1_t maskedoff0, vfloat64m1_t maskedoff1, const double *base, ptrdiff_t bstride, size_t vl) { + return __riscv_vlsseg2e64_mu(v0, v1, mask, maskedoff0, maskedoff1, base, bstride, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlsseg2e64_v_f64m2_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[BSTRIDE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vlsseg2.mask.nxv2f64.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], ptr [[BASE]], i64 [[BSTRIDE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 8 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 8 +// CHECK-RV64-NEXT: ret void +// +void test_vlsseg2e64_v_f64m2_mu(vfloat64m2_t *v0, vfloat64m2_t *v1, vbool32_t mask, vfloat64m2_t maskedoff0, vfloat64m2_t maskedoff1, const double *base, ptrdiff_t bstride, size_t vl) { + return __riscv_vlsseg2e64_mu(v0, v1, mask, maskedoff0, maskedoff1, base, bstride, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlsseg2e64_v_f64m4_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[BSTRIDE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vlsseg2.mask.nxv4f64.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], ptr [[BASE]], i64 [[BSTRIDE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 8 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 8 +// CHECK-RV64-NEXT: ret void +// +void test_vlsseg2e64_v_f64m4_mu(vfloat64m4_t *v0, vfloat64m4_t *v1, vbool16_t mask, vfloat64m4_t maskedoff0, vfloat64m4_t maskedoff1, const double *base, ptrdiff_t bstride, size_t vl) { + return __riscv_vlsseg2e64_mu(v0, v1, mask, maskedoff0, maskedoff1, base, bstride, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlsseg2e64_v_i64m1_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[BSTRIDE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vlsseg2.mask.nxv1i64.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], ptr [[BASE]], i64 [[BSTRIDE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 8 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 8 +// CHECK-RV64-NEXT: ret void +// +void test_vlsseg2e64_v_i64m1_mu(vint64m1_t *v0, vint64m1_t *v1, vbool64_t mask, vint64m1_t maskedoff0, vint64m1_t maskedoff1, const int64_t *base, ptrdiff_t bstride, size_t vl) { + return __riscv_vlsseg2e64_mu(v0, v1, mask, maskedoff0, maskedoff1, base, bstride, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlsseg2e64_v_i64m2_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[BSTRIDE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vlsseg2.mask.nxv2i64.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], ptr [[BASE]], i64 [[BSTRIDE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 8 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 8 +// CHECK-RV64-NEXT: ret void +// +void test_vlsseg2e64_v_i64m2_mu(vint64m2_t *v0, vint64m2_t *v1, vbool32_t mask, vint64m2_t maskedoff0, vint64m2_t maskedoff1, const int64_t *base, ptrdiff_t bstride, size_t vl) { + return __riscv_vlsseg2e64_mu(v0, v1, mask, maskedoff0, maskedoff1, base, bstride, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlsseg2e64_v_i64m4_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[BSTRIDE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vlsseg2.mask.nxv4i64.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], ptr [[BASE]], i64 [[BSTRIDE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 8 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 8 +// CHECK-RV64-NEXT: ret void +// +void test_vlsseg2e64_v_i64m4_mu(vint64m4_t *v0, vint64m4_t *v1, vbool16_t mask, vint64m4_t maskedoff0, vint64m4_t maskedoff1, const int64_t *base, ptrdiff_t bstride, size_t vl) { + return __riscv_vlsseg2e64_mu(v0, v1, mask, maskedoff0, maskedoff1, base, bstride, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlsseg2e64_v_u64m1_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[BSTRIDE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vlsseg2.mask.nxv1i64.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], ptr [[BASE]], i64 [[BSTRIDE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 8 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 8 +// CHECK-RV64-NEXT: ret void +// +void test_vlsseg2e64_v_u64m1_mu(vuint64m1_t *v0, vuint64m1_t *v1, vbool64_t mask, vuint64m1_t maskedoff0, vuint64m1_t maskedoff1, const uint64_t *base, ptrdiff_t bstride, size_t vl) { + return __riscv_vlsseg2e64_mu(v0, v1, mask, maskedoff0, maskedoff1, base, bstride, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlsseg2e64_v_u64m2_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[BSTRIDE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vlsseg2.mask.nxv2i64.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], ptr [[BASE]], i64 [[BSTRIDE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 8 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 8 +// CHECK-RV64-NEXT: ret void +// +void test_vlsseg2e64_v_u64m2_mu(vuint64m2_t *v0, vuint64m2_t *v1, vbool32_t mask, vuint64m2_t maskedoff0, vuint64m2_t maskedoff1, const uint64_t *base, ptrdiff_t bstride, size_t vl) { + return __riscv_vlsseg2e64_mu(v0, v1, mask, maskedoff0, maskedoff1, base, bstride, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlsseg2e64_v_u64m4_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[BSTRIDE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vlsseg2.mask.nxv4i64.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], ptr [[BASE]], i64 [[BSTRIDE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 8 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 8 +// CHECK-RV64-NEXT: ret void +// +void test_vlsseg2e64_v_u64m4_mu(vuint64m4_t *v0, vuint64m4_t *v1, vbool16_t mask, vuint64m4_t maskedoff0, vuint64m4_t maskedoff1, const uint64_t *base, ptrdiff_t bstride, size_t vl) { + return __riscv_vlsseg2e64_mu(v0, v1, mask, maskedoff0, maskedoff1, base, bstride, vl); +} + diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg2e8.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg2e8.c index cae7067d64cc4..c5b31c38ce967 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg2e8.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg2e8.c @@ -510,3 +510,171 @@ void test_vlsseg2e8_v_u8m4_tumu(vuint8m4_t *v0, vuint8m4_t *v1, vbool2_t mask, v return __riscv_vlsseg2e8_tumu(v0, v1, mask, maskedoff0, maskedoff1, base, bstride, vl); } +// CHECK-RV64-LABEL: define dso_local void @test_vlsseg2e8_v_i8mf8_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[BSTRIDE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vlsseg2.mask.nxv1i8.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], ptr [[BASE]], i64 [[BSTRIDE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 1 +// CHECK-RV64-NEXT: ret void +// +void test_vlsseg2e8_v_i8mf8_mu(vint8mf8_t *v0, vint8mf8_t *v1, vbool64_t mask, vint8mf8_t maskedoff0, vint8mf8_t maskedoff1, const int8_t *base, ptrdiff_t bstride, size_t vl) { + return __riscv_vlsseg2e8_mu(v0, v1, mask, maskedoff0, maskedoff1, base, bstride, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlsseg2e8_v_i8mf4_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[BSTRIDE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vlsseg2.mask.nxv2i8.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], ptr [[BASE]], i64 [[BSTRIDE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 1 +// CHECK-RV64-NEXT: ret void +// +void test_vlsseg2e8_v_i8mf4_mu(vint8mf4_t *v0, vint8mf4_t *v1, vbool32_t mask, vint8mf4_t maskedoff0, vint8mf4_t maskedoff1, const int8_t *base, ptrdiff_t bstride, size_t vl) { + return __riscv_vlsseg2e8_mu(v0, v1, mask, maskedoff0, maskedoff1, base, bstride, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlsseg2e8_v_i8mf2_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[BSTRIDE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vlsseg2.mask.nxv4i8.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], ptr [[BASE]], i64 [[BSTRIDE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 1 +// CHECK-RV64-NEXT: ret void +// +void test_vlsseg2e8_v_i8mf2_mu(vint8mf2_t *v0, vint8mf2_t *v1, vbool16_t mask, vint8mf2_t maskedoff0, vint8mf2_t maskedoff1, const int8_t *base, ptrdiff_t bstride, size_t vl) { + return __riscv_vlsseg2e8_mu(v0, v1, mask, maskedoff0, maskedoff1, base, bstride, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlsseg2e8_v_i8m1_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[BSTRIDE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vlsseg2.mask.nxv8i8.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], ptr [[BASE]], i64 [[BSTRIDE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 1 +// CHECK-RV64-NEXT: ret void +// +void test_vlsseg2e8_v_i8m1_mu(vint8m1_t *v0, vint8m1_t *v1, vbool8_t mask, vint8m1_t maskedoff0, vint8m1_t maskedoff1, const int8_t *base, ptrdiff_t bstride, size_t vl) { + return __riscv_vlsseg2e8_mu(v0, v1, mask, maskedoff0, maskedoff1, base, bstride, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlsseg2e8_v_i8m2_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[BSTRIDE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vlsseg2.mask.nxv16i8.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], ptr [[BASE]], i64 [[BSTRIDE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 1 +// CHECK-RV64-NEXT: ret void +// +void test_vlsseg2e8_v_i8m2_mu(vint8m2_t *v0, vint8m2_t *v1, vbool4_t mask, vint8m2_t maskedoff0, vint8m2_t maskedoff1, const int8_t *base, ptrdiff_t bstride, size_t vl) { + return __riscv_vlsseg2e8_mu(v0, v1, mask, maskedoff0, maskedoff1, base, bstride, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlsseg2e8_v_i8m4_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[BSTRIDE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vlsseg2.mask.nxv32i8.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], ptr [[BASE]], i64 [[BSTRIDE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 1 +// CHECK-RV64-NEXT: ret void +// +void test_vlsseg2e8_v_i8m4_mu(vint8m4_t *v0, vint8m4_t *v1, vbool2_t mask, vint8m4_t maskedoff0, vint8m4_t maskedoff1, const int8_t *base, ptrdiff_t bstride, size_t vl) { + return __riscv_vlsseg2e8_mu(v0, v1, mask, maskedoff0, maskedoff1, base, bstride, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlsseg2e8_v_u8mf8_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[BSTRIDE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vlsseg2.mask.nxv1i8.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], ptr [[BASE]], i64 [[BSTRIDE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 1 +// CHECK-RV64-NEXT: ret void +// +void test_vlsseg2e8_v_u8mf8_mu(vuint8mf8_t *v0, vuint8mf8_t *v1, vbool64_t mask, vuint8mf8_t maskedoff0, vuint8mf8_t maskedoff1, const uint8_t *base, ptrdiff_t bstride, size_t vl) { + return __riscv_vlsseg2e8_mu(v0, v1, mask, maskedoff0, maskedoff1, base, bstride, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlsseg2e8_v_u8mf4_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[BSTRIDE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vlsseg2.mask.nxv2i8.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], ptr [[BASE]], i64 [[BSTRIDE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 1 +// CHECK-RV64-NEXT: ret void +// +void test_vlsseg2e8_v_u8mf4_mu(vuint8mf4_t *v0, vuint8mf4_t *v1, vbool32_t mask, vuint8mf4_t maskedoff0, vuint8mf4_t maskedoff1, const uint8_t *base, ptrdiff_t bstride, size_t vl) { + return __riscv_vlsseg2e8_mu(v0, v1, mask, maskedoff0, maskedoff1, base, bstride, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlsseg2e8_v_u8mf2_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[BSTRIDE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vlsseg2.mask.nxv4i8.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], ptr [[BASE]], i64 [[BSTRIDE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 1 +// CHECK-RV64-NEXT: ret void +// +void test_vlsseg2e8_v_u8mf2_mu(vuint8mf2_t *v0, vuint8mf2_t *v1, vbool16_t mask, vuint8mf2_t maskedoff0, vuint8mf2_t maskedoff1, const uint8_t *base, ptrdiff_t bstride, size_t vl) { + return __riscv_vlsseg2e8_mu(v0, v1, mask, maskedoff0, maskedoff1, base, bstride, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlsseg2e8_v_u8m1_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[BSTRIDE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vlsseg2.mask.nxv8i8.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], ptr [[BASE]], i64 [[BSTRIDE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 1 +// CHECK-RV64-NEXT: ret void +// +void test_vlsseg2e8_v_u8m1_mu(vuint8m1_t *v0, vuint8m1_t *v1, vbool8_t mask, vuint8m1_t maskedoff0, vuint8m1_t maskedoff1, const uint8_t *base, ptrdiff_t bstride, size_t vl) { + return __riscv_vlsseg2e8_mu(v0, v1, mask, maskedoff0, maskedoff1, base, bstride, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlsseg2e8_v_u8m2_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[BSTRIDE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vlsseg2.mask.nxv16i8.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], ptr [[BASE]], i64 [[BSTRIDE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 1 +// CHECK-RV64-NEXT: ret void +// +void test_vlsseg2e8_v_u8m2_mu(vuint8m2_t *v0, vuint8m2_t *v1, vbool4_t mask, vuint8m2_t maskedoff0, vuint8m2_t maskedoff1, const uint8_t *base, ptrdiff_t bstride, size_t vl) { + return __riscv_vlsseg2e8_mu(v0, v1, mask, maskedoff0, maskedoff1, base, bstride, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlsseg2e8_v_u8m4_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[BSTRIDE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vlsseg2.mask.nxv32i8.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], ptr [[BASE]], i64 [[BSTRIDE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 1 +// CHECK-RV64-NEXT: ret void +// +void test_vlsseg2e8_v_u8m4_mu(vuint8m4_t *v0, vuint8m4_t *v1, vbool2_t mask, vuint8m4_t maskedoff0, vuint8m4_t maskedoff1, const uint8_t *base, ptrdiff_t bstride, size_t vl) { + return __riscv_vlsseg2e8_mu(v0, v1, mask, maskedoff0, maskedoff1, base, bstride, vl); +} + diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg3e16.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg3e16.c index 29f845331008f..9a6e4218ef78d 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg3e16.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg3e16.c @@ -583,3 +583,195 @@ void test_vlsseg3e16_v_u16m2_tumu(vuint16m2_t *v0, vuint16m2_t *v1, vuint16m2_t return __riscv_vlsseg3e16_tumu(v0, v1, v2, mask, maskedoff0, maskedoff1, maskedoff2, base, bstride, vl); } +// CHECK-RV64-LABEL: define dso_local void @test_vlsseg3e16_v_f16mf4_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[BSTRIDE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vlsseg3.mask.nxv1f16.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], ptr [[BASE]], i64 [[BSTRIDE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 2 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 2 +// CHECK-RV64-NEXT: ret void +// +void test_vlsseg3e16_v_f16mf4_mu(vfloat16mf4_t *v0, vfloat16mf4_t *v1, vfloat16mf4_t *v2, vbool64_t mask, vfloat16mf4_t maskedoff0, vfloat16mf4_t maskedoff1, vfloat16mf4_t maskedoff2, const _Float16 *base, ptrdiff_t bstride, size_t vl) { + return __riscv_vlsseg3e16_mu(v0, v1, v2, mask, maskedoff0, maskedoff1, maskedoff2, base, bstride, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlsseg3e16_v_f16mf2_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[BSTRIDE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vlsseg3.mask.nxv2f16.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], ptr [[BASE]], i64 [[BSTRIDE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 2 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 2 +// CHECK-RV64-NEXT: ret void +// +void test_vlsseg3e16_v_f16mf2_mu(vfloat16mf2_t *v0, vfloat16mf2_t *v1, vfloat16mf2_t *v2, vbool32_t mask, vfloat16mf2_t maskedoff0, vfloat16mf2_t maskedoff1, vfloat16mf2_t maskedoff2, const _Float16 *base, ptrdiff_t bstride, size_t vl) { + return __riscv_vlsseg3e16_mu(v0, v1, v2, mask, maskedoff0, maskedoff1, maskedoff2, base, bstride, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlsseg3e16_v_f16m1_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[BSTRIDE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vlsseg3.mask.nxv4f16.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], ptr [[BASE]], i64 [[BSTRIDE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 2 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 2 +// CHECK-RV64-NEXT: ret void +// +void test_vlsseg3e16_v_f16m1_mu(vfloat16m1_t *v0, vfloat16m1_t *v1, vfloat16m1_t *v2, vbool16_t mask, vfloat16m1_t maskedoff0, vfloat16m1_t maskedoff1, vfloat16m1_t maskedoff2, const _Float16 *base, ptrdiff_t bstride, size_t vl) { + return __riscv_vlsseg3e16_mu(v0, v1, v2, mask, maskedoff0, maskedoff1, maskedoff2, base, bstride, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlsseg3e16_v_f16m2_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[BSTRIDE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vlsseg3.mask.nxv8f16.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], ptr [[BASE]], i64 [[BSTRIDE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 2 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 2 +// CHECK-RV64-NEXT: ret void +// +void test_vlsseg3e16_v_f16m2_mu(vfloat16m2_t *v0, vfloat16m2_t *v1, vfloat16m2_t *v2, vbool8_t mask, vfloat16m2_t maskedoff0, vfloat16m2_t maskedoff1, vfloat16m2_t maskedoff2, const _Float16 *base, ptrdiff_t bstride, size_t vl) { + return __riscv_vlsseg3e16_mu(v0, v1, v2, mask, maskedoff0, maskedoff1, maskedoff2, base, bstride, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlsseg3e16_v_i16mf4_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[BSTRIDE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vlsseg3.mask.nxv1i16.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], ptr [[BASE]], i64 [[BSTRIDE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 2 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 2 +// CHECK-RV64-NEXT: ret void +// +void test_vlsseg3e16_v_i16mf4_mu(vint16mf4_t *v0, vint16mf4_t *v1, vint16mf4_t *v2, vbool64_t mask, vint16mf4_t maskedoff0, vint16mf4_t maskedoff1, vint16mf4_t maskedoff2, const int16_t *base, ptrdiff_t bstride, size_t vl) { + return __riscv_vlsseg3e16_mu(v0, v1, v2, mask, maskedoff0, maskedoff1, maskedoff2, base, bstride, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlsseg3e16_v_i16mf2_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[BSTRIDE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vlsseg3.mask.nxv2i16.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], ptr [[BASE]], i64 [[BSTRIDE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 2 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 2 +// CHECK-RV64-NEXT: ret void +// +void test_vlsseg3e16_v_i16mf2_mu(vint16mf2_t *v0, vint16mf2_t *v1, vint16mf2_t *v2, vbool32_t mask, vint16mf2_t maskedoff0, vint16mf2_t maskedoff1, vint16mf2_t maskedoff2, const int16_t *base, ptrdiff_t bstride, size_t vl) { + return __riscv_vlsseg3e16_mu(v0, v1, v2, mask, maskedoff0, maskedoff1, maskedoff2, base, bstride, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlsseg3e16_v_i16m1_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[BSTRIDE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vlsseg3.mask.nxv4i16.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], ptr [[BASE]], i64 [[BSTRIDE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 2 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 2 +// CHECK-RV64-NEXT: ret void +// +void test_vlsseg3e16_v_i16m1_mu(vint16m1_t *v0, vint16m1_t *v1, vint16m1_t *v2, vbool16_t mask, vint16m1_t maskedoff0, vint16m1_t maskedoff1, vint16m1_t maskedoff2, const int16_t *base, ptrdiff_t bstride, size_t vl) { + return __riscv_vlsseg3e16_mu(v0, v1, v2, mask, maskedoff0, maskedoff1, maskedoff2, base, bstride, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlsseg3e16_v_i16m2_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[BSTRIDE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vlsseg3.mask.nxv8i16.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], ptr [[BASE]], i64 [[BSTRIDE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 2 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 2 +// CHECK-RV64-NEXT: ret void +// +void test_vlsseg3e16_v_i16m2_mu(vint16m2_t *v0, vint16m2_t *v1, vint16m2_t *v2, vbool8_t mask, vint16m2_t maskedoff0, vint16m2_t maskedoff1, vint16m2_t maskedoff2, const int16_t *base, ptrdiff_t bstride, size_t vl) { + return __riscv_vlsseg3e16_mu(v0, v1, v2, mask, maskedoff0, maskedoff1, maskedoff2, base, bstride, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlsseg3e16_v_u16mf4_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[BSTRIDE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vlsseg3.mask.nxv1i16.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], ptr [[BASE]], i64 [[BSTRIDE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 2 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 2 +// CHECK-RV64-NEXT: ret void +// +void test_vlsseg3e16_v_u16mf4_mu(vuint16mf4_t *v0, vuint16mf4_t *v1, vuint16mf4_t *v2, vbool64_t mask, vuint16mf4_t maskedoff0, vuint16mf4_t maskedoff1, vuint16mf4_t maskedoff2, const uint16_t *base, ptrdiff_t bstride, size_t vl) { + return __riscv_vlsseg3e16_mu(v0, v1, v2, mask, maskedoff0, maskedoff1, maskedoff2, base, bstride, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlsseg3e16_v_u16mf2_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[BSTRIDE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vlsseg3.mask.nxv2i16.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], ptr [[BASE]], i64 [[BSTRIDE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 2 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 2 +// CHECK-RV64-NEXT: ret void +// +void test_vlsseg3e16_v_u16mf2_mu(vuint16mf2_t *v0, vuint16mf2_t *v1, vuint16mf2_t *v2, vbool32_t mask, vuint16mf2_t maskedoff0, vuint16mf2_t maskedoff1, vuint16mf2_t maskedoff2, const uint16_t *base, ptrdiff_t bstride, size_t vl) { + return __riscv_vlsseg3e16_mu(v0, v1, v2, mask, maskedoff0, maskedoff1, maskedoff2, base, bstride, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlsseg3e16_v_u16m1_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[BSTRIDE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vlsseg3.mask.nxv4i16.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], ptr [[BASE]], i64 [[BSTRIDE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 2 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 2 +// CHECK-RV64-NEXT: ret void +// +void test_vlsseg3e16_v_u16m1_mu(vuint16m1_t *v0, vuint16m1_t *v1, vuint16m1_t *v2, vbool16_t mask, vuint16m1_t maskedoff0, vuint16m1_t maskedoff1, vuint16m1_t maskedoff2, const uint16_t *base, ptrdiff_t bstride, size_t vl) { + return __riscv_vlsseg3e16_mu(v0, v1, v2, mask, maskedoff0, maskedoff1, maskedoff2, base, bstride, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlsseg3e16_v_u16m2_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[BSTRIDE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vlsseg3.mask.nxv8i16.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], ptr [[BASE]], i64 [[BSTRIDE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 2 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 2 +// CHECK-RV64-NEXT: ret void +// +void test_vlsseg3e16_v_u16m2_mu(vuint16m2_t *v0, vuint16m2_t *v1, vuint16m2_t *v2, vbool8_t mask, vuint16m2_t maskedoff0, vuint16m2_t maskedoff1, vuint16m2_t maskedoff2, const uint16_t *base, ptrdiff_t bstride, size_t vl) { + return __riscv_vlsseg3e16_mu(v0, v1, v2, mask, maskedoff0, maskedoff1, maskedoff2, base, bstride, vl); +} + diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg3e32.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg3e32.c index e7d9182fce47a..f1b315f863ec9 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg3e32.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg3e32.c @@ -439,3 +439,147 @@ void test_vlsseg3e32_v_u32m2_tumu(vuint32m2_t *v0, vuint32m2_t *v1, vuint32m2_t return __riscv_vlsseg3e32_tumu(v0, v1, v2, mask, maskedoff0, maskedoff1, maskedoff2, base, bstride, vl); } +// CHECK-RV64-LABEL: define dso_local void @test_vlsseg3e32_v_f32mf2_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[BSTRIDE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vlsseg3.mask.nxv1f32.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], ptr [[BASE]], i64 [[BSTRIDE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 4 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 4 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 4 +// CHECK-RV64-NEXT: ret void +// +void test_vlsseg3e32_v_f32mf2_mu(vfloat32mf2_t *v0, vfloat32mf2_t *v1, vfloat32mf2_t *v2, vbool64_t mask, vfloat32mf2_t maskedoff0, vfloat32mf2_t maskedoff1, vfloat32mf2_t maskedoff2, const float *base, ptrdiff_t bstride, size_t vl) { + return __riscv_vlsseg3e32_mu(v0, v1, v2, mask, maskedoff0, maskedoff1, maskedoff2, base, bstride, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlsseg3e32_v_f32m1_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[BSTRIDE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vlsseg3.mask.nxv2f32.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], ptr [[BASE]], i64 [[BSTRIDE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 4 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 4 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 4 +// CHECK-RV64-NEXT: ret void +// +void test_vlsseg3e32_v_f32m1_mu(vfloat32m1_t *v0, vfloat32m1_t *v1, vfloat32m1_t *v2, vbool32_t mask, vfloat32m1_t maskedoff0, vfloat32m1_t maskedoff1, vfloat32m1_t maskedoff2, const float *base, ptrdiff_t bstride, size_t vl) { + return __riscv_vlsseg3e32_mu(v0, v1, v2, mask, maskedoff0, maskedoff1, maskedoff2, base, bstride, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlsseg3e32_v_f32m2_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[BSTRIDE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vlsseg3.mask.nxv4f32.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], ptr [[BASE]], i64 [[BSTRIDE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 4 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 4 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 4 +// CHECK-RV64-NEXT: ret void +// +void test_vlsseg3e32_v_f32m2_mu(vfloat32m2_t *v0, vfloat32m2_t *v1, vfloat32m2_t *v2, vbool16_t mask, vfloat32m2_t maskedoff0, vfloat32m2_t maskedoff1, vfloat32m2_t maskedoff2, const float *base, ptrdiff_t bstride, size_t vl) { + return __riscv_vlsseg3e32_mu(v0, v1, v2, mask, maskedoff0, maskedoff1, maskedoff2, base, bstride, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlsseg3e32_v_i32mf2_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[BSTRIDE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vlsseg3.mask.nxv1i32.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], ptr [[BASE]], i64 [[BSTRIDE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 4 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 4 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 4 +// CHECK-RV64-NEXT: ret void +// +void test_vlsseg3e32_v_i32mf2_mu(vint32mf2_t *v0, vint32mf2_t *v1, vint32mf2_t *v2, vbool64_t mask, vint32mf2_t maskedoff0, vint32mf2_t maskedoff1, vint32mf2_t maskedoff2, const int32_t *base, ptrdiff_t bstride, size_t vl) { + return __riscv_vlsseg3e32_mu(v0, v1, v2, mask, maskedoff0, maskedoff1, maskedoff2, base, bstride, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlsseg3e32_v_i32m1_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[BSTRIDE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vlsseg3.mask.nxv2i32.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], ptr [[BASE]], i64 [[BSTRIDE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 4 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 4 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 4 +// CHECK-RV64-NEXT: ret void +// +void test_vlsseg3e32_v_i32m1_mu(vint32m1_t *v0, vint32m1_t *v1, vint32m1_t *v2, vbool32_t mask, vint32m1_t maskedoff0, vint32m1_t maskedoff1, vint32m1_t maskedoff2, const int32_t *base, ptrdiff_t bstride, size_t vl) { + return __riscv_vlsseg3e32_mu(v0, v1, v2, mask, maskedoff0, maskedoff1, maskedoff2, base, bstride, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlsseg3e32_v_i32m2_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[BSTRIDE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vlsseg3.mask.nxv4i32.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], ptr [[BASE]], i64 [[BSTRIDE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 4 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 4 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 4 +// CHECK-RV64-NEXT: ret void +// +void test_vlsseg3e32_v_i32m2_mu(vint32m2_t *v0, vint32m2_t *v1, vint32m2_t *v2, vbool16_t mask, vint32m2_t maskedoff0, vint32m2_t maskedoff1, vint32m2_t maskedoff2, const int32_t *base, ptrdiff_t bstride, size_t vl) { + return __riscv_vlsseg3e32_mu(v0, v1, v2, mask, maskedoff0, maskedoff1, maskedoff2, base, bstride, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlsseg3e32_v_u32mf2_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[BSTRIDE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vlsseg3.mask.nxv1i32.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], ptr [[BASE]], i64 [[BSTRIDE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 4 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 4 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 4 +// CHECK-RV64-NEXT: ret void +// +void test_vlsseg3e32_v_u32mf2_mu(vuint32mf2_t *v0, vuint32mf2_t *v1, vuint32mf2_t *v2, vbool64_t mask, vuint32mf2_t maskedoff0, vuint32mf2_t maskedoff1, vuint32mf2_t maskedoff2, const uint32_t *base, ptrdiff_t bstride, size_t vl) { + return __riscv_vlsseg3e32_mu(v0, v1, v2, mask, maskedoff0, maskedoff1, maskedoff2, base, bstride, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlsseg3e32_v_u32m1_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[BSTRIDE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vlsseg3.mask.nxv2i32.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], ptr [[BASE]], i64 [[BSTRIDE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 4 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 4 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 4 +// CHECK-RV64-NEXT: ret void +// +void test_vlsseg3e32_v_u32m1_mu(vuint32m1_t *v0, vuint32m1_t *v1, vuint32m1_t *v2, vbool32_t mask, vuint32m1_t maskedoff0, vuint32m1_t maskedoff1, vuint32m1_t maskedoff2, const uint32_t *base, ptrdiff_t bstride, size_t vl) { + return __riscv_vlsseg3e32_mu(v0, v1, v2, mask, maskedoff0, maskedoff1, maskedoff2, base, bstride, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlsseg3e32_v_u32m2_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[BSTRIDE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vlsseg3.mask.nxv4i32.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], ptr [[BASE]], i64 [[BSTRIDE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 4 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 4 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 4 +// CHECK-RV64-NEXT: ret void +// +void test_vlsseg3e32_v_u32m2_mu(vuint32m2_t *v0, vuint32m2_t *v1, vuint32m2_t *v2, vbool16_t mask, vuint32m2_t maskedoff0, vuint32m2_t maskedoff1, vuint32m2_t maskedoff2, const uint32_t *base, ptrdiff_t bstride, size_t vl) { + return __riscv_vlsseg3e32_mu(v0, v1, v2, mask, maskedoff0, maskedoff1, maskedoff2, base, bstride, vl); +} + diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg3e64.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg3e64.c index fda921d9b098b..4f399d307f155 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg3e64.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg3e64.c @@ -295,3 +295,99 @@ void test_vlsseg3e64_v_u64m2_tumu(vuint64m2_t *v0, vuint64m2_t *v1, vuint64m2_t return __riscv_vlsseg3e64_tumu(v0, v1, v2, mask, maskedoff0, maskedoff1, maskedoff2, base, bstride, vl); } +// CHECK-RV64-LABEL: define dso_local void @test_vlsseg3e64_v_f64m1_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[BSTRIDE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vlsseg3.mask.nxv1f64.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], ptr [[BASE]], i64 [[BSTRIDE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 8 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 8 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 8 +// CHECK-RV64-NEXT: ret void +// +void test_vlsseg3e64_v_f64m1_mu(vfloat64m1_t *v0, vfloat64m1_t *v1, vfloat64m1_t *v2, vbool64_t mask, vfloat64m1_t maskedoff0, vfloat64m1_t maskedoff1, vfloat64m1_t maskedoff2, const double *base, ptrdiff_t bstride, size_t vl) { + return __riscv_vlsseg3e64_mu(v0, v1, v2, mask, maskedoff0, maskedoff1, maskedoff2, base, bstride, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlsseg3e64_v_f64m2_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[BSTRIDE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vlsseg3.mask.nxv2f64.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], ptr [[BASE]], i64 [[BSTRIDE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 8 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 8 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 8 +// CHECK-RV64-NEXT: ret void +// +void test_vlsseg3e64_v_f64m2_mu(vfloat64m2_t *v0, vfloat64m2_t *v1, vfloat64m2_t *v2, vbool32_t mask, vfloat64m2_t maskedoff0, vfloat64m2_t maskedoff1, vfloat64m2_t maskedoff2, const double *base, ptrdiff_t bstride, size_t vl) { + return __riscv_vlsseg3e64_mu(v0, v1, v2, mask, maskedoff0, maskedoff1, maskedoff2, base, bstride, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlsseg3e64_v_i64m1_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[BSTRIDE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vlsseg3.mask.nxv1i64.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], ptr [[BASE]], i64 [[BSTRIDE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 8 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 8 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 8 +// CHECK-RV64-NEXT: ret void +// +void test_vlsseg3e64_v_i64m1_mu(vint64m1_t *v0, vint64m1_t *v1, vint64m1_t *v2, vbool64_t mask, vint64m1_t maskedoff0, vint64m1_t maskedoff1, vint64m1_t maskedoff2, const int64_t *base, ptrdiff_t bstride, size_t vl) { + return __riscv_vlsseg3e64_mu(v0, v1, v2, mask, maskedoff0, maskedoff1, maskedoff2, base, bstride, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlsseg3e64_v_i64m2_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[BSTRIDE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vlsseg3.mask.nxv2i64.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], ptr [[BASE]], i64 [[BSTRIDE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 8 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 8 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 8 +// CHECK-RV64-NEXT: ret void +// +void test_vlsseg3e64_v_i64m2_mu(vint64m2_t *v0, vint64m2_t *v1, vint64m2_t *v2, vbool32_t mask, vint64m2_t maskedoff0, vint64m2_t maskedoff1, vint64m2_t maskedoff2, const int64_t *base, ptrdiff_t bstride, size_t vl) { + return __riscv_vlsseg3e64_mu(v0, v1, v2, mask, maskedoff0, maskedoff1, maskedoff2, base, bstride, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlsseg3e64_v_u64m1_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[BSTRIDE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vlsseg3.mask.nxv1i64.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], ptr [[BASE]], i64 [[BSTRIDE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 8 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 8 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 8 +// CHECK-RV64-NEXT: ret void +// +void test_vlsseg3e64_v_u64m1_mu(vuint64m1_t *v0, vuint64m1_t *v1, vuint64m1_t *v2, vbool64_t mask, vuint64m1_t maskedoff0, vuint64m1_t maskedoff1, vuint64m1_t maskedoff2, const uint64_t *base, ptrdiff_t bstride, size_t vl) { + return __riscv_vlsseg3e64_mu(v0, v1, v2, mask, maskedoff0, maskedoff1, maskedoff2, base, bstride, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlsseg3e64_v_u64m2_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[BSTRIDE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vlsseg3.mask.nxv2i64.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], ptr [[BASE]], i64 [[BSTRIDE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 8 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 8 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 8 +// CHECK-RV64-NEXT: ret void +// +void test_vlsseg3e64_v_u64m2_mu(vuint64m2_t *v0, vuint64m2_t *v1, vuint64m2_t *v2, vbool32_t mask, vuint64m2_t maskedoff0, vuint64m2_t maskedoff1, vuint64m2_t maskedoff2, const uint64_t *base, ptrdiff_t bstride, size_t vl) { + return __riscv_vlsseg3e64_mu(v0, v1, v2, mask, maskedoff0, maskedoff1, maskedoff2, base, bstride, vl); +} + diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg3e8.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg3e8.c index 6173b24bf1e41..7e74f5efb5bab 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg3e8.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg3e8.c @@ -486,3 +486,163 @@ void test_vlsseg3e8_v_u8m2_tumu(vuint8m2_t *v0, vuint8m2_t *v1, vuint8m2_t *v2, return __riscv_vlsseg3e8_tumu(v0, v1, v2, mask, maskedoff0, maskedoff1, maskedoff2, base, bstride, vl); } +// CHECK-RV64-LABEL: define dso_local void @test_vlsseg3e8_v_i8mf8_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[BSTRIDE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vlsseg3.mask.nxv1i8.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], ptr [[BASE]], i64 [[BSTRIDE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 1 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 1 +// CHECK-RV64-NEXT: ret void +// +void test_vlsseg3e8_v_i8mf8_mu(vint8mf8_t *v0, vint8mf8_t *v1, vint8mf8_t *v2, vbool64_t mask, vint8mf8_t maskedoff0, vint8mf8_t maskedoff1, vint8mf8_t maskedoff2, const int8_t *base, ptrdiff_t bstride, size_t vl) { + return __riscv_vlsseg3e8_mu(v0, v1, v2, mask, maskedoff0, maskedoff1, maskedoff2, base, bstride, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlsseg3e8_v_i8mf4_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[BSTRIDE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vlsseg3.mask.nxv2i8.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], ptr [[BASE]], i64 [[BSTRIDE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 1 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 1 +// CHECK-RV64-NEXT: ret void +// +void test_vlsseg3e8_v_i8mf4_mu(vint8mf4_t *v0, vint8mf4_t *v1, vint8mf4_t *v2, vbool32_t mask, vint8mf4_t maskedoff0, vint8mf4_t maskedoff1, vint8mf4_t maskedoff2, const int8_t *base, ptrdiff_t bstride, size_t vl) { + return __riscv_vlsseg3e8_mu(v0, v1, v2, mask, maskedoff0, maskedoff1, maskedoff2, base, bstride, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlsseg3e8_v_i8mf2_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[BSTRIDE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vlsseg3.mask.nxv4i8.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], ptr [[BASE]], i64 [[BSTRIDE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 1 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 1 +// CHECK-RV64-NEXT: ret void +// +void test_vlsseg3e8_v_i8mf2_mu(vint8mf2_t *v0, vint8mf2_t *v1, vint8mf2_t *v2, vbool16_t mask, vint8mf2_t maskedoff0, vint8mf2_t maskedoff1, vint8mf2_t maskedoff2, const int8_t *base, ptrdiff_t bstride, size_t vl) { + return __riscv_vlsseg3e8_mu(v0, v1, v2, mask, maskedoff0, maskedoff1, maskedoff2, base, bstride, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlsseg3e8_v_i8m1_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[BSTRIDE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vlsseg3.mask.nxv8i8.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], ptr [[BASE]], i64 [[BSTRIDE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 1 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 1 +// CHECK-RV64-NEXT: ret void +// +void test_vlsseg3e8_v_i8m1_mu(vint8m1_t *v0, vint8m1_t *v1, vint8m1_t *v2, vbool8_t mask, vint8m1_t maskedoff0, vint8m1_t maskedoff1, vint8m1_t maskedoff2, const int8_t *base, ptrdiff_t bstride, size_t vl) { + return __riscv_vlsseg3e8_mu(v0, v1, v2, mask, maskedoff0, maskedoff1, maskedoff2, base, bstride, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlsseg3e8_v_i8m2_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[BSTRIDE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vlsseg3.mask.nxv16i8.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], ptr [[BASE]], i64 [[BSTRIDE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 1 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 1 +// CHECK-RV64-NEXT: ret void +// +void test_vlsseg3e8_v_i8m2_mu(vint8m2_t *v0, vint8m2_t *v1, vint8m2_t *v2, vbool4_t mask, vint8m2_t maskedoff0, vint8m2_t maskedoff1, vint8m2_t maskedoff2, const int8_t *base, ptrdiff_t bstride, size_t vl) { + return __riscv_vlsseg3e8_mu(v0, v1, v2, mask, maskedoff0, maskedoff1, maskedoff2, base, bstride, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlsseg3e8_v_u8mf8_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[BSTRIDE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vlsseg3.mask.nxv1i8.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], ptr [[BASE]], i64 [[BSTRIDE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 1 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 1 +// CHECK-RV64-NEXT: ret void +// +void test_vlsseg3e8_v_u8mf8_mu(vuint8mf8_t *v0, vuint8mf8_t *v1, vuint8mf8_t *v2, vbool64_t mask, vuint8mf8_t maskedoff0, vuint8mf8_t maskedoff1, vuint8mf8_t maskedoff2, const uint8_t *base, ptrdiff_t bstride, size_t vl) { + return __riscv_vlsseg3e8_mu(v0, v1, v2, mask, maskedoff0, maskedoff1, maskedoff2, base, bstride, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlsseg3e8_v_u8mf4_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[BSTRIDE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vlsseg3.mask.nxv2i8.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], ptr [[BASE]], i64 [[BSTRIDE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 1 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 1 +// CHECK-RV64-NEXT: ret void +// +void test_vlsseg3e8_v_u8mf4_mu(vuint8mf4_t *v0, vuint8mf4_t *v1, vuint8mf4_t *v2, vbool32_t mask, vuint8mf4_t maskedoff0, vuint8mf4_t maskedoff1, vuint8mf4_t maskedoff2, const uint8_t *base, ptrdiff_t bstride, size_t vl) { + return __riscv_vlsseg3e8_mu(v0, v1, v2, mask, maskedoff0, maskedoff1, maskedoff2, base, bstride, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlsseg3e8_v_u8mf2_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[BSTRIDE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vlsseg3.mask.nxv4i8.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], ptr [[BASE]], i64 [[BSTRIDE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 1 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 1 +// CHECK-RV64-NEXT: ret void +// +void test_vlsseg3e8_v_u8mf2_mu(vuint8mf2_t *v0, vuint8mf2_t *v1, vuint8mf2_t *v2, vbool16_t mask, vuint8mf2_t maskedoff0, vuint8mf2_t maskedoff1, vuint8mf2_t maskedoff2, const uint8_t *base, ptrdiff_t bstride, size_t vl) { + return __riscv_vlsseg3e8_mu(v0, v1, v2, mask, maskedoff0, maskedoff1, maskedoff2, base, bstride, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlsseg3e8_v_u8m1_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[BSTRIDE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vlsseg3.mask.nxv8i8.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], ptr [[BASE]], i64 [[BSTRIDE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 1 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 1 +// CHECK-RV64-NEXT: ret void +// +void test_vlsseg3e8_v_u8m1_mu(vuint8m1_t *v0, vuint8m1_t *v1, vuint8m1_t *v2, vbool8_t mask, vuint8m1_t maskedoff0, vuint8m1_t maskedoff1, vuint8m1_t maskedoff2, const uint8_t *base, ptrdiff_t bstride, size_t vl) { + return __riscv_vlsseg3e8_mu(v0, v1, v2, mask, maskedoff0, maskedoff1, maskedoff2, base, bstride, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlsseg3e8_v_u8m2_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[BSTRIDE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vlsseg3.mask.nxv16i8.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], ptr [[BASE]], i64 [[BSTRIDE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 1 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 1 +// CHECK-RV64-NEXT: ret void +// +void test_vlsseg3e8_v_u8m2_mu(vuint8m2_t *v0, vuint8m2_t *v1, vuint8m2_t *v2, vbool4_t mask, vuint8m2_t maskedoff0, vuint8m2_t maskedoff1, vuint8m2_t maskedoff2, const uint8_t *base, ptrdiff_t bstride, size_t vl) { + return __riscv_vlsseg3e8_mu(v0, v1, v2, mask, maskedoff0, maskedoff1, maskedoff2, base, bstride, vl); +} + diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg4e16.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg4e16.c index 1a0e2716c5ec5..749debacf6ba5 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg4e16.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg4e16.c @@ -655,3 +655,219 @@ void test_vlsseg4e16_v_u16m2_tumu(vuint16m2_t *v0, vuint16m2_t *v1, vuint16m2_t return __riscv_vlsseg4e16_tumu(v0, v1, v2, v3, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, base, bstride, vl); } +// CHECK-RV64-LABEL: define dso_local void @test_vlsseg4e16_v_f16mf4_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[BSTRIDE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vlsseg4.mask.nxv1f16.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], ptr [[BASE]], i64 [[BSTRIDE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 2 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 2 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 2 +// CHECK-RV64-NEXT: ret void +// +void test_vlsseg4e16_v_f16mf4_mu(vfloat16mf4_t *v0, vfloat16mf4_t *v1, vfloat16mf4_t *v2, vfloat16mf4_t *v3, vbool64_t mask, vfloat16mf4_t maskedoff0, vfloat16mf4_t maskedoff1, vfloat16mf4_t maskedoff2, vfloat16mf4_t maskedoff3, const _Float16 *base, ptrdiff_t bstride, size_t vl) { + return __riscv_vlsseg4e16_mu(v0, v1, v2, v3, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, base, bstride, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlsseg4e16_v_f16mf2_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[BSTRIDE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vlsseg4.mask.nxv2f16.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], ptr [[BASE]], i64 [[BSTRIDE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 2 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 2 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 2 +// CHECK-RV64-NEXT: ret void +// +void test_vlsseg4e16_v_f16mf2_mu(vfloat16mf2_t *v0, vfloat16mf2_t *v1, vfloat16mf2_t *v2, vfloat16mf2_t *v3, vbool32_t mask, vfloat16mf2_t maskedoff0, vfloat16mf2_t maskedoff1, vfloat16mf2_t maskedoff2, vfloat16mf2_t maskedoff3, const _Float16 *base, ptrdiff_t bstride, size_t vl) { + return __riscv_vlsseg4e16_mu(v0, v1, v2, v3, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, base, bstride, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlsseg4e16_v_f16m1_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[BSTRIDE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vlsseg4.mask.nxv4f16.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], ptr [[BASE]], i64 [[BSTRIDE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 2 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 2 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 2 +// CHECK-RV64-NEXT: ret void +// +void test_vlsseg4e16_v_f16m1_mu(vfloat16m1_t *v0, vfloat16m1_t *v1, vfloat16m1_t *v2, vfloat16m1_t *v3, vbool16_t mask, vfloat16m1_t maskedoff0, vfloat16m1_t maskedoff1, vfloat16m1_t maskedoff2, vfloat16m1_t maskedoff3, const _Float16 *base, ptrdiff_t bstride, size_t vl) { + return __riscv_vlsseg4e16_mu(v0, v1, v2, v3, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, base, bstride, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlsseg4e16_v_f16m2_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[BSTRIDE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vlsseg4.mask.nxv8f16.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], ptr [[BASE]], i64 [[BSTRIDE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 2 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 2 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 2 +// CHECK-RV64-NEXT: ret void +// +void test_vlsseg4e16_v_f16m2_mu(vfloat16m2_t *v0, vfloat16m2_t *v1, vfloat16m2_t *v2, vfloat16m2_t *v3, vbool8_t mask, vfloat16m2_t maskedoff0, vfloat16m2_t maskedoff1, vfloat16m2_t maskedoff2, vfloat16m2_t maskedoff3, const _Float16 *base, ptrdiff_t bstride, size_t vl) { + return __riscv_vlsseg4e16_mu(v0, v1, v2, v3, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, base, bstride, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlsseg4e16_v_i16mf4_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[BSTRIDE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vlsseg4.mask.nxv1i16.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], ptr [[BASE]], i64 [[BSTRIDE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 2 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 2 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 2 +// CHECK-RV64-NEXT: ret void +// +void test_vlsseg4e16_v_i16mf4_mu(vint16mf4_t *v0, vint16mf4_t *v1, vint16mf4_t *v2, vint16mf4_t *v3, vbool64_t mask, vint16mf4_t maskedoff0, vint16mf4_t maskedoff1, vint16mf4_t maskedoff2, vint16mf4_t maskedoff3, const int16_t *base, ptrdiff_t bstride, size_t vl) { + return __riscv_vlsseg4e16_mu(v0, v1, v2, v3, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, base, bstride, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlsseg4e16_v_i16mf2_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[BSTRIDE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vlsseg4.mask.nxv2i16.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], ptr [[BASE]], i64 [[BSTRIDE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 2 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 2 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 2 +// CHECK-RV64-NEXT: ret void +// +void test_vlsseg4e16_v_i16mf2_mu(vint16mf2_t *v0, vint16mf2_t *v1, vint16mf2_t *v2, vint16mf2_t *v3, vbool32_t mask, vint16mf2_t maskedoff0, vint16mf2_t maskedoff1, vint16mf2_t maskedoff2, vint16mf2_t maskedoff3, const int16_t *base, ptrdiff_t bstride, size_t vl) { + return __riscv_vlsseg4e16_mu(v0, v1, v2, v3, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, base, bstride, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlsseg4e16_v_i16m1_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[BSTRIDE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vlsseg4.mask.nxv4i16.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], ptr [[BASE]], i64 [[BSTRIDE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 2 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 2 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 2 +// CHECK-RV64-NEXT: ret void +// +void test_vlsseg4e16_v_i16m1_mu(vint16m1_t *v0, vint16m1_t *v1, vint16m1_t *v2, vint16m1_t *v3, vbool16_t mask, vint16m1_t maskedoff0, vint16m1_t maskedoff1, vint16m1_t maskedoff2, vint16m1_t maskedoff3, const int16_t *base, ptrdiff_t bstride, size_t vl) { + return __riscv_vlsseg4e16_mu(v0, v1, v2, v3, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, base, bstride, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlsseg4e16_v_i16m2_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[BSTRIDE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vlsseg4.mask.nxv8i16.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], ptr [[BASE]], i64 [[BSTRIDE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 2 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 2 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 2 +// CHECK-RV64-NEXT: ret void +// +void test_vlsseg4e16_v_i16m2_mu(vint16m2_t *v0, vint16m2_t *v1, vint16m2_t *v2, vint16m2_t *v3, vbool8_t mask, vint16m2_t maskedoff0, vint16m2_t maskedoff1, vint16m2_t maskedoff2, vint16m2_t maskedoff3, const int16_t *base, ptrdiff_t bstride, size_t vl) { + return __riscv_vlsseg4e16_mu(v0, v1, v2, v3, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, base, bstride, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlsseg4e16_v_u16mf4_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[BSTRIDE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vlsseg4.mask.nxv1i16.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], ptr [[BASE]], i64 [[BSTRIDE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 2 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 2 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 2 +// CHECK-RV64-NEXT: ret void +// +void test_vlsseg4e16_v_u16mf4_mu(vuint16mf4_t *v0, vuint16mf4_t *v1, vuint16mf4_t *v2, vuint16mf4_t *v3, vbool64_t mask, vuint16mf4_t maskedoff0, vuint16mf4_t maskedoff1, vuint16mf4_t maskedoff2, vuint16mf4_t maskedoff3, const uint16_t *base, ptrdiff_t bstride, size_t vl) { + return __riscv_vlsseg4e16_mu(v0, v1, v2, v3, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, base, bstride, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlsseg4e16_v_u16mf2_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[BSTRIDE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vlsseg4.mask.nxv2i16.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], ptr [[BASE]], i64 [[BSTRIDE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 2 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 2 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 2 +// CHECK-RV64-NEXT: ret void +// +void test_vlsseg4e16_v_u16mf2_mu(vuint16mf2_t *v0, vuint16mf2_t *v1, vuint16mf2_t *v2, vuint16mf2_t *v3, vbool32_t mask, vuint16mf2_t maskedoff0, vuint16mf2_t maskedoff1, vuint16mf2_t maskedoff2, vuint16mf2_t maskedoff3, const uint16_t *base, ptrdiff_t bstride, size_t vl) { + return __riscv_vlsseg4e16_mu(v0, v1, v2, v3, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, base, bstride, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlsseg4e16_v_u16m1_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[BSTRIDE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vlsseg4.mask.nxv4i16.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], ptr [[BASE]], i64 [[BSTRIDE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 2 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 2 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 2 +// CHECK-RV64-NEXT: ret void +// +void test_vlsseg4e16_v_u16m1_mu(vuint16m1_t *v0, vuint16m1_t *v1, vuint16m1_t *v2, vuint16m1_t *v3, vbool16_t mask, vuint16m1_t maskedoff0, vuint16m1_t maskedoff1, vuint16m1_t maskedoff2, vuint16m1_t maskedoff3, const uint16_t *base, ptrdiff_t bstride, size_t vl) { + return __riscv_vlsseg4e16_mu(v0, v1, v2, v3, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, base, bstride, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlsseg4e16_v_u16m2_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[BSTRIDE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vlsseg4.mask.nxv8i16.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], ptr [[BASE]], i64 [[BSTRIDE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 2 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 2 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 2 +// CHECK-RV64-NEXT: ret void +// +void test_vlsseg4e16_v_u16m2_mu(vuint16m2_t *v0, vuint16m2_t *v1, vuint16m2_t *v2, vuint16m2_t *v3, vbool8_t mask, vuint16m2_t maskedoff0, vuint16m2_t maskedoff1, vuint16m2_t maskedoff2, vuint16m2_t maskedoff3, const uint16_t *base, ptrdiff_t bstride, size_t vl) { + return __riscv_vlsseg4e16_mu(v0, v1, v2, v3, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, base, bstride, vl); +} + diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg4e32.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg4e32.c index 6f9ad72495bb9..137a9d00cbb1a 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg4e32.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg4e32.c @@ -493,3 +493,165 @@ void test_vlsseg4e32_v_u32m2_tumu(vuint32m2_t *v0, vuint32m2_t *v1, vuint32m2_t return __riscv_vlsseg4e32_tumu(v0, v1, v2, v3, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, base, bstride, vl); } +// CHECK-RV64-LABEL: define dso_local void @test_vlsseg4e32_v_f32mf2_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[BSTRIDE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vlsseg4.mask.nxv1f32.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], ptr [[BASE]], i64 [[BSTRIDE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 4 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 4 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 4 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 4 +// CHECK-RV64-NEXT: ret void +// +void test_vlsseg4e32_v_f32mf2_mu(vfloat32mf2_t *v0, vfloat32mf2_t *v1, vfloat32mf2_t *v2, vfloat32mf2_t *v3, vbool64_t mask, vfloat32mf2_t maskedoff0, vfloat32mf2_t maskedoff1, vfloat32mf2_t maskedoff2, vfloat32mf2_t maskedoff3, const float *base, ptrdiff_t bstride, size_t vl) { + return __riscv_vlsseg4e32_mu(v0, v1, v2, v3, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, base, bstride, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlsseg4e32_v_f32m1_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[BSTRIDE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vlsseg4.mask.nxv2f32.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], ptr [[BASE]], i64 [[BSTRIDE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 4 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 4 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 4 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 4 +// CHECK-RV64-NEXT: ret void +// +void test_vlsseg4e32_v_f32m1_mu(vfloat32m1_t *v0, vfloat32m1_t *v1, vfloat32m1_t *v2, vfloat32m1_t *v3, vbool32_t mask, vfloat32m1_t maskedoff0, vfloat32m1_t maskedoff1, vfloat32m1_t maskedoff2, vfloat32m1_t maskedoff3, const float *base, ptrdiff_t bstride, size_t vl) { + return __riscv_vlsseg4e32_mu(v0, v1, v2, v3, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, base, bstride, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlsseg4e32_v_f32m2_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[BSTRIDE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vlsseg4.mask.nxv4f32.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], ptr [[BASE]], i64 [[BSTRIDE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 4 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 4 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 4 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 4 +// CHECK-RV64-NEXT: ret void +// +void test_vlsseg4e32_v_f32m2_mu(vfloat32m2_t *v0, vfloat32m2_t *v1, vfloat32m2_t *v2, vfloat32m2_t *v3, vbool16_t mask, vfloat32m2_t maskedoff0, vfloat32m2_t maskedoff1, vfloat32m2_t maskedoff2, vfloat32m2_t maskedoff3, const float *base, ptrdiff_t bstride, size_t vl) { + return __riscv_vlsseg4e32_mu(v0, v1, v2, v3, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, base, bstride, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlsseg4e32_v_i32mf2_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[BSTRIDE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vlsseg4.mask.nxv1i32.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], ptr [[BASE]], i64 [[BSTRIDE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 4 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 4 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 4 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 4 +// CHECK-RV64-NEXT: ret void +// +void test_vlsseg4e32_v_i32mf2_mu(vint32mf2_t *v0, vint32mf2_t *v1, vint32mf2_t *v2, vint32mf2_t *v3, vbool64_t mask, vint32mf2_t maskedoff0, vint32mf2_t maskedoff1, vint32mf2_t maskedoff2, vint32mf2_t maskedoff3, const int32_t *base, ptrdiff_t bstride, size_t vl) { + return __riscv_vlsseg4e32_mu(v0, v1, v2, v3, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, base, bstride, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlsseg4e32_v_i32m1_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[BSTRIDE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vlsseg4.mask.nxv2i32.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], ptr [[BASE]], i64 [[BSTRIDE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 4 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 4 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 4 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 4 +// CHECK-RV64-NEXT: ret void +// +void test_vlsseg4e32_v_i32m1_mu(vint32m1_t *v0, vint32m1_t *v1, vint32m1_t *v2, vint32m1_t *v3, vbool32_t mask, vint32m1_t maskedoff0, vint32m1_t maskedoff1, vint32m1_t maskedoff2, vint32m1_t maskedoff3, const int32_t *base, ptrdiff_t bstride, size_t vl) { + return __riscv_vlsseg4e32_mu(v0, v1, v2, v3, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, base, bstride, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlsseg4e32_v_i32m2_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[BSTRIDE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vlsseg4.mask.nxv4i32.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], ptr [[BASE]], i64 [[BSTRIDE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 4 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 4 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 4 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 4 +// CHECK-RV64-NEXT: ret void +// +void test_vlsseg4e32_v_i32m2_mu(vint32m2_t *v0, vint32m2_t *v1, vint32m2_t *v2, vint32m2_t *v3, vbool16_t mask, vint32m2_t maskedoff0, vint32m2_t maskedoff1, vint32m2_t maskedoff2, vint32m2_t maskedoff3, const int32_t *base, ptrdiff_t bstride, size_t vl) { + return __riscv_vlsseg4e32_mu(v0, v1, v2, v3, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, base, bstride, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlsseg4e32_v_u32mf2_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[BSTRIDE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vlsseg4.mask.nxv1i32.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], ptr [[BASE]], i64 [[BSTRIDE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 4 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 4 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 4 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 4 +// CHECK-RV64-NEXT: ret void +// +void test_vlsseg4e32_v_u32mf2_mu(vuint32mf2_t *v0, vuint32mf2_t *v1, vuint32mf2_t *v2, vuint32mf2_t *v3, vbool64_t mask, vuint32mf2_t maskedoff0, vuint32mf2_t maskedoff1, vuint32mf2_t maskedoff2, vuint32mf2_t maskedoff3, const uint32_t *base, ptrdiff_t bstride, size_t vl) { + return __riscv_vlsseg4e32_mu(v0, v1, v2, v3, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, base, bstride, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlsseg4e32_v_u32m1_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[BSTRIDE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vlsseg4.mask.nxv2i32.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], ptr [[BASE]], i64 [[BSTRIDE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 4 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 4 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 4 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 4 +// CHECK-RV64-NEXT: ret void +// +void test_vlsseg4e32_v_u32m1_mu(vuint32m1_t *v0, vuint32m1_t *v1, vuint32m1_t *v2, vuint32m1_t *v3, vbool32_t mask, vuint32m1_t maskedoff0, vuint32m1_t maskedoff1, vuint32m1_t maskedoff2, vuint32m1_t maskedoff3, const uint32_t *base, ptrdiff_t bstride, size_t vl) { + return __riscv_vlsseg4e32_mu(v0, v1, v2, v3, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, base, bstride, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlsseg4e32_v_u32m2_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[BSTRIDE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vlsseg4.mask.nxv4i32.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], ptr [[BASE]], i64 [[BSTRIDE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 4 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 4 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 4 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 4 +// CHECK-RV64-NEXT: ret void +// +void test_vlsseg4e32_v_u32m2_mu(vuint32m2_t *v0, vuint32m2_t *v1, vuint32m2_t *v2, vuint32m2_t *v3, vbool16_t mask, vuint32m2_t maskedoff0, vuint32m2_t maskedoff1, vuint32m2_t maskedoff2, vuint32m2_t maskedoff3, const uint32_t *base, ptrdiff_t bstride, size_t vl) { + return __riscv_vlsseg4e32_mu(v0, v1, v2, v3, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, base, bstride, vl); +} + diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg4e64.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg4e64.c index d8d749cc05491..fa4116dfd4e4f 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg4e64.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg4e64.c @@ -331,3 +331,111 @@ void test_vlsseg4e64_v_u64m2_tumu(vuint64m2_t *v0, vuint64m2_t *v1, vuint64m2_t return __riscv_vlsseg4e64_tumu(v0, v1, v2, v3, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, base, bstride, vl); } +// CHECK-RV64-LABEL: define dso_local void @test_vlsseg4e64_v_f64m1_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[BSTRIDE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vlsseg4.mask.nxv1f64.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], ptr [[BASE]], i64 [[BSTRIDE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 8 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 8 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 8 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 8 +// CHECK-RV64-NEXT: ret void +// +void test_vlsseg4e64_v_f64m1_mu(vfloat64m1_t *v0, vfloat64m1_t *v1, vfloat64m1_t *v2, vfloat64m1_t *v3, vbool64_t mask, vfloat64m1_t maskedoff0, vfloat64m1_t maskedoff1, vfloat64m1_t maskedoff2, vfloat64m1_t maskedoff3, const double *base, ptrdiff_t bstride, size_t vl) { + return __riscv_vlsseg4e64_mu(v0, v1, v2, v3, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, base, bstride, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlsseg4e64_v_f64m2_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[BSTRIDE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vlsseg4.mask.nxv2f64.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], ptr [[BASE]], i64 [[BSTRIDE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 8 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 8 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 8 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 8 +// CHECK-RV64-NEXT: ret void +// +void test_vlsseg4e64_v_f64m2_mu(vfloat64m2_t *v0, vfloat64m2_t *v1, vfloat64m2_t *v2, vfloat64m2_t *v3, vbool32_t mask, vfloat64m2_t maskedoff0, vfloat64m2_t maskedoff1, vfloat64m2_t maskedoff2, vfloat64m2_t maskedoff3, const double *base, ptrdiff_t bstride, size_t vl) { + return __riscv_vlsseg4e64_mu(v0, v1, v2, v3, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, base, bstride, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlsseg4e64_v_i64m1_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[BSTRIDE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vlsseg4.mask.nxv1i64.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], ptr [[BASE]], i64 [[BSTRIDE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 8 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 8 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 8 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 8 +// CHECK-RV64-NEXT: ret void +// +void test_vlsseg4e64_v_i64m1_mu(vint64m1_t *v0, vint64m1_t *v1, vint64m1_t *v2, vint64m1_t *v3, vbool64_t mask, vint64m1_t maskedoff0, vint64m1_t maskedoff1, vint64m1_t maskedoff2, vint64m1_t maskedoff3, const int64_t *base, ptrdiff_t bstride, size_t vl) { + return __riscv_vlsseg4e64_mu(v0, v1, v2, v3, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, base, bstride, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlsseg4e64_v_i64m2_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[BSTRIDE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vlsseg4.mask.nxv2i64.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], ptr [[BASE]], i64 [[BSTRIDE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 8 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 8 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 8 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 8 +// CHECK-RV64-NEXT: ret void +// +void test_vlsseg4e64_v_i64m2_mu(vint64m2_t *v0, vint64m2_t *v1, vint64m2_t *v2, vint64m2_t *v3, vbool32_t mask, vint64m2_t maskedoff0, vint64m2_t maskedoff1, vint64m2_t maskedoff2, vint64m2_t maskedoff3, const int64_t *base, ptrdiff_t bstride, size_t vl) { + return __riscv_vlsseg4e64_mu(v0, v1, v2, v3, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, base, bstride, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlsseg4e64_v_u64m1_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[BSTRIDE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vlsseg4.mask.nxv1i64.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], ptr [[BASE]], i64 [[BSTRIDE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 8 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 8 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 8 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 8 +// CHECK-RV64-NEXT: ret void +// +void test_vlsseg4e64_v_u64m1_mu(vuint64m1_t *v0, vuint64m1_t *v1, vuint64m1_t *v2, vuint64m1_t *v3, vbool64_t mask, vuint64m1_t maskedoff0, vuint64m1_t maskedoff1, vuint64m1_t maskedoff2, vuint64m1_t maskedoff3, const uint64_t *base, ptrdiff_t bstride, size_t vl) { + return __riscv_vlsseg4e64_mu(v0, v1, v2, v3, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, base, bstride, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlsseg4e64_v_u64m2_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[BSTRIDE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vlsseg4.mask.nxv2i64.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], ptr [[BASE]], i64 [[BSTRIDE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 8 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 8 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 8 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 8 +// CHECK-RV64-NEXT: ret void +// +void test_vlsseg4e64_v_u64m2_mu(vuint64m2_t *v0, vuint64m2_t *v1, vuint64m2_t *v2, vuint64m2_t *v3, vbool32_t mask, vuint64m2_t maskedoff0, vuint64m2_t maskedoff1, vuint64m2_t maskedoff2, vuint64m2_t maskedoff3, const uint64_t *base, ptrdiff_t bstride, size_t vl) { + return __riscv_vlsseg4e64_mu(v0, v1, v2, v3, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, base, bstride, vl); +} + diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg4e8.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg4e8.c index dec9b52a13632..4f8a663a14f90 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg4e8.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg4e8.c @@ -546,3 +546,183 @@ void test_vlsseg4e8_v_u8m2_tumu(vuint8m2_t *v0, vuint8m2_t *v1, vuint8m2_t *v2, return __riscv_vlsseg4e8_tumu(v0, v1, v2, v3, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, base, bstride, vl); } +// CHECK-RV64-LABEL: define dso_local void @test_vlsseg4e8_v_i8mf8_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[BSTRIDE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vlsseg4.mask.nxv1i8.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], ptr [[BASE]], i64 [[BSTRIDE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 1 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 1 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 1 +// CHECK-RV64-NEXT: ret void +// +void test_vlsseg4e8_v_i8mf8_mu(vint8mf8_t *v0, vint8mf8_t *v1, vint8mf8_t *v2, vint8mf8_t *v3, vbool64_t mask, vint8mf8_t maskedoff0, vint8mf8_t maskedoff1, vint8mf8_t maskedoff2, vint8mf8_t maskedoff3, const int8_t *base, ptrdiff_t bstride, size_t vl) { + return __riscv_vlsseg4e8_mu(v0, v1, v2, v3, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, base, bstride, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlsseg4e8_v_i8mf4_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[BSTRIDE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vlsseg4.mask.nxv2i8.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], ptr [[BASE]], i64 [[BSTRIDE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 1 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 1 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 1 +// CHECK-RV64-NEXT: ret void +// +void test_vlsseg4e8_v_i8mf4_mu(vint8mf4_t *v0, vint8mf4_t *v1, vint8mf4_t *v2, vint8mf4_t *v3, vbool32_t mask, vint8mf4_t maskedoff0, vint8mf4_t maskedoff1, vint8mf4_t maskedoff2, vint8mf4_t maskedoff3, const int8_t *base, ptrdiff_t bstride, size_t vl) { + return __riscv_vlsseg4e8_mu(v0, v1, v2, v3, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, base, bstride, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlsseg4e8_v_i8mf2_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[BSTRIDE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vlsseg4.mask.nxv4i8.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], ptr [[BASE]], i64 [[BSTRIDE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 1 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 1 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 1 +// CHECK-RV64-NEXT: ret void +// +void test_vlsseg4e8_v_i8mf2_mu(vint8mf2_t *v0, vint8mf2_t *v1, vint8mf2_t *v2, vint8mf2_t *v3, vbool16_t mask, vint8mf2_t maskedoff0, vint8mf2_t maskedoff1, vint8mf2_t maskedoff2, vint8mf2_t maskedoff3, const int8_t *base, ptrdiff_t bstride, size_t vl) { + return __riscv_vlsseg4e8_mu(v0, v1, v2, v3, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, base, bstride, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlsseg4e8_v_i8m1_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[BSTRIDE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vlsseg4.mask.nxv8i8.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], ptr [[BASE]], i64 [[BSTRIDE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 1 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 1 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 1 +// CHECK-RV64-NEXT: ret void +// +void test_vlsseg4e8_v_i8m1_mu(vint8m1_t *v0, vint8m1_t *v1, vint8m1_t *v2, vint8m1_t *v3, vbool8_t mask, vint8m1_t maskedoff0, vint8m1_t maskedoff1, vint8m1_t maskedoff2, vint8m1_t maskedoff3, const int8_t *base, ptrdiff_t bstride, size_t vl) { + return __riscv_vlsseg4e8_mu(v0, v1, v2, v3, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, base, bstride, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlsseg4e8_v_i8m2_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[BSTRIDE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vlsseg4.mask.nxv16i8.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], ptr [[BASE]], i64 [[BSTRIDE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 1 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 1 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 1 +// CHECK-RV64-NEXT: ret void +// +void test_vlsseg4e8_v_i8m2_mu(vint8m2_t *v0, vint8m2_t *v1, vint8m2_t *v2, vint8m2_t *v3, vbool4_t mask, vint8m2_t maskedoff0, vint8m2_t maskedoff1, vint8m2_t maskedoff2, vint8m2_t maskedoff3, const int8_t *base, ptrdiff_t bstride, size_t vl) { + return __riscv_vlsseg4e8_mu(v0, v1, v2, v3, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, base, bstride, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlsseg4e8_v_u8mf8_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[BSTRIDE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vlsseg4.mask.nxv1i8.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], ptr [[BASE]], i64 [[BSTRIDE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 1 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 1 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 1 +// CHECK-RV64-NEXT: ret void +// +void test_vlsseg4e8_v_u8mf8_mu(vuint8mf8_t *v0, vuint8mf8_t *v1, vuint8mf8_t *v2, vuint8mf8_t *v3, vbool64_t mask, vuint8mf8_t maskedoff0, vuint8mf8_t maskedoff1, vuint8mf8_t maskedoff2, vuint8mf8_t maskedoff3, const uint8_t *base, ptrdiff_t bstride, size_t vl) { + return __riscv_vlsseg4e8_mu(v0, v1, v2, v3, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, base, bstride, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlsseg4e8_v_u8mf4_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[BSTRIDE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vlsseg4.mask.nxv2i8.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], ptr [[BASE]], i64 [[BSTRIDE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 1 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 1 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 1 +// CHECK-RV64-NEXT: ret void +// +void test_vlsseg4e8_v_u8mf4_mu(vuint8mf4_t *v0, vuint8mf4_t *v1, vuint8mf4_t *v2, vuint8mf4_t *v3, vbool32_t mask, vuint8mf4_t maskedoff0, vuint8mf4_t maskedoff1, vuint8mf4_t maskedoff2, vuint8mf4_t maskedoff3, const uint8_t *base, ptrdiff_t bstride, size_t vl) { + return __riscv_vlsseg4e8_mu(v0, v1, v2, v3, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, base, bstride, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlsseg4e8_v_u8mf2_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[BSTRIDE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vlsseg4.mask.nxv4i8.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], ptr [[BASE]], i64 [[BSTRIDE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 1 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 1 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 1 +// CHECK-RV64-NEXT: ret void +// +void test_vlsseg4e8_v_u8mf2_mu(vuint8mf2_t *v0, vuint8mf2_t *v1, vuint8mf2_t *v2, vuint8mf2_t *v3, vbool16_t mask, vuint8mf2_t maskedoff0, vuint8mf2_t maskedoff1, vuint8mf2_t maskedoff2, vuint8mf2_t maskedoff3, const uint8_t *base, ptrdiff_t bstride, size_t vl) { + return __riscv_vlsseg4e8_mu(v0, v1, v2, v3, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, base, bstride, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlsseg4e8_v_u8m1_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[BSTRIDE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vlsseg4.mask.nxv8i8.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], ptr [[BASE]], i64 [[BSTRIDE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 1 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 1 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 1 +// CHECK-RV64-NEXT: ret void +// +void test_vlsseg4e8_v_u8m1_mu(vuint8m1_t *v0, vuint8m1_t *v1, vuint8m1_t *v2, vuint8m1_t *v3, vbool8_t mask, vuint8m1_t maskedoff0, vuint8m1_t maskedoff1, vuint8m1_t maskedoff2, vuint8m1_t maskedoff3, const uint8_t *base, ptrdiff_t bstride, size_t vl) { + return __riscv_vlsseg4e8_mu(v0, v1, v2, v3, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, base, bstride, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlsseg4e8_v_u8m2_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[BSTRIDE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vlsseg4.mask.nxv16i8.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], ptr [[BASE]], i64 [[BSTRIDE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 1 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 1 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 1 +// CHECK-RV64-NEXT: ret void +// +void test_vlsseg4e8_v_u8m2_mu(vuint8m2_t *v0, vuint8m2_t *v1, vuint8m2_t *v2, vuint8m2_t *v3, vbool4_t mask, vuint8m2_t maskedoff0, vuint8m2_t maskedoff1, vuint8m2_t maskedoff2, vuint8m2_t maskedoff3, const uint8_t *base, ptrdiff_t bstride, size_t vl) { + return __riscv_vlsseg4e8_mu(v0, v1, v2, v3, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, base, bstride, vl); +} + diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg5e16.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg5e16.c index 2cf5dda2bfa70..a23b266491375 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg5e16.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg5e16.c @@ -547,3 +547,183 @@ void test_vlsseg5e16_v_u16m1_tumu(vuint16m1_t *v0, vuint16m1_t *v1, vuint16m1_t return __riscv_vlsseg5e16_tumu(v0, v1, v2, v3, v4, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, maskedoff4, base, bstride, vl); } +// CHECK-RV64-LABEL: define dso_local void @test_vlsseg5e16_v_f16mf4_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], ptr noundef [[V4:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], [[MASKEDOFF4:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[BSTRIDE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vlsseg5.mask.nxv1f16.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], [[MASKEDOFF4]], ptr [[BASE]], i64 [[BSTRIDE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 2 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 2 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 2 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , } [[TMP0]], 4 +// CHECK-RV64-NEXT: store [[TMP5]], ptr [[V4]], align 2 +// CHECK-RV64-NEXT: ret void +// +void test_vlsseg5e16_v_f16mf4_mu(vfloat16mf4_t *v0, vfloat16mf4_t *v1, vfloat16mf4_t *v2, vfloat16mf4_t *v3, vfloat16mf4_t *v4, vbool64_t mask, vfloat16mf4_t maskedoff0, vfloat16mf4_t maskedoff1, vfloat16mf4_t maskedoff2, vfloat16mf4_t maskedoff3, vfloat16mf4_t maskedoff4, const _Float16 *base, ptrdiff_t bstride, size_t vl) { + return __riscv_vlsseg5e16_mu(v0, v1, v2, v3, v4, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, maskedoff4, base, bstride, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlsseg5e16_v_f16mf2_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], ptr noundef [[V4:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], [[MASKEDOFF4:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[BSTRIDE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vlsseg5.mask.nxv2f16.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], [[MASKEDOFF4]], ptr [[BASE]], i64 [[BSTRIDE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 2 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 2 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 2 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , } [[TMP0]], 4 +// CHECK-RV64-NEXT: store [[TMP5]], ptr [[V4]], align 2 +// CHECK-RV64-NEXT: ret void +// +void test_vlsseg5e16_v_f16mf2_mu(vfloat16mf2_t *v0, vfloat16mf2_t *v1, vfloat16mf2_t *v2, vfloat16mf2_t *v3, vfloat16mf2_t *v4, vbool32_t mask, vfloat16mf2_t maskedoff0, vfloat16mf2_t maskedoff1, vfloat16mf2_t maskedoff2, vfloat16mf2_t maskedoff3, vfloat16mf2_t maskedoff4, const _Float16 *base, ptrdiff_t bstride, size_t vl) { + return __riscv_vlsseg5e16_mu(v0, v1, v2, v3, v4, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, maskedoff4, base, bstride, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlsseg5e16_v_f16m1_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], ptr noundef [[V4:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], [[MASKEDOFF4:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[BSTRIDE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vlsseg5.mask.nxv4f16.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], [[MASKEDOFF4]], ptr [[BASE]], i64 [[BSTRIDE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 2 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 2 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 2 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , } [[TMP0]], 4 +// CHECK-RV64-NEXT: store [[TMP5]], ptr [[V4]], align 2 +// CHECK-RV64-NEXT: ret void +// +void test_vlsseg5e16_v_f16m1_mu(vfloat16m1_t *v0, vfloat16m1_t *v1, vfloat16m1_t *v2, vfloat16m1_t *v3, vfloat16m1_t *v4, vbool16_t mask, vfloat16m1_t maskedoff0, vfloat16m1_t maskedoff1, vfloat16m1_t maskedoff2, vfloat16m1_t maskedoff3, vfloat16m1_t maskedoff4, const _Float16 *base, ptrdiff_t bstride, size_t vl) { + return __riscv_vlsseg5e16_mu(v0, v1, v2, v3, v4, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, maskedoff4, base, bstride, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlsseg5e16_v_i16mf4_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], ptr noundef [[V4:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], [[MASKEDOFF4:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[BSTRIDE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vlsseg5.mask.nxv1i16.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], [[MASKEDOFF4]], ptr [[BASE]], i64 [[BSTRIDE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 2 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 2 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 2 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , } [[TMP0]], 4 +// CHECK-RV64-NEXT: store [[TMP5]], ptr [[V4]], align 2 +// CHECK-RV64-NEXT: ret void +// +void test_vlsseg5e16_v_i16mf4_mu(vint16mf4_t *v0, vint16mf4_t *v1, vint16mf4_t *v2, vint16mf4_t *v3, vint16mf4_t *v4, vbool64_t mask, vint16mf4_t maskedoff0, vint16mf4_t maskedoff1, vint16mf4_t maskedoff2, vint16mf4_t maskedoff3, vint16mf4_t maskedoff4, const int16_t *base, ptrdiff_t bstride, size_t vl) { + return __riscv_vlsseg5e16_mu(v0, v1, v2, v3, v4, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, maskedoff4, base, bstride, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlsseg5e16_v_i16mf2_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], ptr noundef [[V4:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], [[MASKEDOFF4:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[BSTRIDE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vlsseg5.mask.nxv2i16.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], [[MASKEDOFF4]], ptr [[BASE]], i64 [[BSTRIDE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 2 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 2 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 2 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , } [[TMP0]], 4 +// CHECK-RV64-NEXT: store [[TMP5]], ptr [[V4]], align 2 +// CHECK-RV64-NEXT: ret void +// +void test_vlsseg5e16_v_i16mf2_mu(vint16mf2_t *v0, vint16mf2_t *v1, vint16mf2_t *v2, vint16mf2_t *v3, vint16mf2_t *v4, vbool32_t mask, vint16mf2_t maskedoff0, vint16mf2_t maskedoff1, vint16mf2_t maskedoff2, vint16mf2_t maskedoff3, vint16mf2_t maskedoff4, const int16_t *base, ptrdiff_t bstride, size_t vl) { + return __riscv_vlsseg5e16_mu(v0, v1, v2, v3, v4, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, maskedoff4, base, bstride, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlsseg5e16_v_i16m1_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], ptr noundef [[V4:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], [[MASKEDOFF4:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[BSTRIDE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vlsseg5.mask.nxv4i16.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], [[MASKEDOFF4]], ptr [[BASE]], i64 [[BSTRIDE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 2 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 2 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 2 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , } [[TMP0]], 4 +// CHECK-RV64-NEXT: store [[TMP5]], ptr [[V4]], align 2 +// CHECK-RV64-NEXT: ret void +// +void test_vlsseg5e16_v_i16m1_mu(vint16m1_t *v0, vint16m1_t *v1, vint16m1_t *v2, vint16m1_t *v3, vint16m1_t *v4, vbool16_t mask, vint16m1_t maskedoff0, vint16m1_t maskedoff1, vint16m1_t maskedoff2, vint16m1_t maskedoff3, vint16m1_t maskedoff4, const int16_t *base, ptrdiff_t bstride, size_t vl) { + return __riscv_vlsseg5e16_mu(v0, v1, v2, v3, v4, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, maskedoff4, base, bstride, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlsseg5e16_v_u16mf4_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], ptr noundef [[V4:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], [[MASKEDOFF4:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[BSTRIDE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vlsseg5.mask.nxv1i16.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], [[MASKEDOFF4]], ptr [[BASE]], i64 [[BSTRIDE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 2 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 2 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 2 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , } [[TMP0]], 4 +// CHECK-RV64-NEXT: store [[TMP5]], ptr [[V4]], align 2 +// CHECK-RV64-NEXT: ret void +// +void test_vlsseg5e16_v_u16mf4_mu(vuint16mf4_t *v0, vuint16mf4_t *v1, vuint16mf4_t *v2, vuint16mf4_t *v3, vuint16mf4_t *v4, vbool64_t mask, vuint16mf4_t maskedoff0, vuint16mf4_t maskedoff1, vuint16mf4_t maskedoff2, vuint16mf4_t maskedoff3, vuint16mf4_t maskedoff4, const uint16_t *base, ptrdiff_t bstride, size_t vl) { + return __riscv_vlsseg5e16_mu(v0, v1, v2, v3, v4, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, maskedoff4, base, bstride, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlsseg5e16_v_u16mf2_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], ptr noundef [[V4:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], [[MASKEDOFF4:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[BSTRIDE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vlsseg5.mask.nxv2i16.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], [[MASKEDOFF4]], ptr [[BASE]], i64 [[BSTRIDE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 2 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 2 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 2 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , } [[TMP0]], 4 +// CHECK-RV64-NEXT: store [[TMP5]], ptr [[V4]], align 2 +// CHECK-RV64-NEXT: ret void +// +void test_vlsseg5e16_v_u16mf2_mu(vuint16mf2_t *v0, vuint16mf2_t *v1, vuint16mf2_t *v2, vuint16mf2_t *v3, vuint16mf2_t *v4, vbool32_t mask, vuint16mf2_t maskedoff0, vuint16mf2_t maskedoff1, vuint16mf2_t maskedoff2, vuint16mf2_t maskedoff3, vuint16mf2_t maskedoff4, const uint16_t *base, ptrdiff_t bstride, size_t vl) { + return __riscv_vlsseg5e16_mu(v0, v1, v2, v3, v4, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, maskedoff4, base, bstride, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlsseg5e16_v_u16m1_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], ptr noundef [[V4:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], [[MASKEDOFF4:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[BSTRIDE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vlsseg5.mask.nxv4i16.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], [[MASKEDOFF4]], ptr [[BASE]], i64 [[BSTRIDE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 2 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 2 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 2 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , } [[TMP0]], 4 +// CHECK-RV64-NEXT: store [[TMP5]], ptr [[V4]], align 2 +// CHECK-RV64-NEXT: ret void +// +void test_vlsseg5e16_v_u16m1_mu(vuint16m1_t *v0, vuint16m1_t *v1, vuint16m1_t *v2, vuint16m1_t *v3, vuint16m1_t *v4, vbool16_t mask, vuint16m1_t maskedoff0, vuint16m1_t maskedoff1, vuint16m1_t maskedoff2, vuint16m1_t maskedoff3, vuint16m1_t maskedoff4, const uint16_t *base, ptrdiff_t bstride, size_t vl) { + return __riscv_vlsseg5e16_mu(v0, v1, v2, v3, v4, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, maskedoff4, base, bstride, vl); +} + diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg5e32.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg5e32.c index 8a16d87e2a687..75c4022b3992d 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg5e32.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg5e32.c @@ -367,3 +367,123 @@ void test_vlsseg5e32_v_u32m1_tumu(vuint32m1_t *v0, vuint32m1_t *v1, vuint32m1_t return __riscv_vlsseg5e32_tumu(v0, v1, v2, v3, v4, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, maskedoff4, base, bstride, vl); } +// CHECK-RV64-LABEL: define dso_local void @test_vlsseg5e32_v_f32mf2_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], ptr noundef [[V4:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], [[MASKEDOFF4:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[BSTRIDE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vlsseg5.mask.nxv1f32.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], [[MASKEDOFF4]], ptr [[BASE]], i64 [[BSTRIDE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 4 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 4 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 4 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , } [[TMP0]], 4 +// CHECK-RV64-NEXT: store [[TMP5]], ptr [[V4]], align 4 +// CHECK-RV64-NEXT: ret void +// +void test_vlsseg5e32_v_f32mf2_mu(vfloat32mf2_t *v0, vfloat32mf2_t *v1, vfloat32mf2_t *v2, vfloat32mf2_t *v3, vfloat32mf2_t *v4, vbool64_t mask, vfloat32mf2_t maskedoff0, vfloat32mf2_t maskedoff1, vfloat32mf2_t maskedoff2, vfloat32mf2_t maskedoff3, vfloat32mf2_t maskedoff4, const float *base, ptrdiff_t bstride, size_t vl) { + return __riscv_vlsseg5e32_mu(v0, v1, v2, v3, v4, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, maskedoff4, base, bstride, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlsseg5e32_v_f32m1_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], ptr noundef [[V4:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], [[MASKEDOFF4:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[BSTRIDE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vlsseg5.mask.nxv2f32.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], [[MASKEDOFF4]], ptr [[BASE]], i64 [[BSTRIDE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 4 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 4 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 4 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , } [[TMP0]], 4 +// CHECK-RV64-NEXT: store [[TMP5]], ptr [[V4]], align 4 +// CHECK-RV64-NEXT: ret void +// +void test_vlsseg5e32_v_f32m1_mu(vfloat32m1_t *v0, vfloat32m1_t *v1, vfloat32m1_t *v2, vfloat32m1_t *v3, vfloat32m1_t *v4, vbool32_t mask, vfloat32m1_t maskedoff0, vfloat32m1_t maskedoff1, vfloat32m1_t maskedoff2, vfloat32m1_t maskedoff3, vfloat32m1_t maskedoff4, const float *base, ptrdiff_t bstride, size_t vl) { + return __riscv_vlsseg5e32_mu(v0, v1, v2, v3, v4, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, maskedoff4, base, bstride, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlsseg5e32_v_i32mf2_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], ptr noundef [[V4:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], [[MASKEDOFF4:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[BSTRIDE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vlsseg5.mask.nxv1i32.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], [[MASKEDOFF4]], ptr [[BASE]], i64 [[BSTRIDE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 4 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 4 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 4 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , } [[TMP0]], 4 +// CHECK-RV64-NEXT: store [[TMP5]], ptr [[V4]], align 4 +// CHECK-RV64-NEXT: ret void +// +void test_vlsseg5e32_v_i32mf2_mu(vint32mf2_t *v0, vint32mf2_t *v1, vint32mf2_t *v2, vint32mf2_t *v3, vint32mf2_t *v4, vbool64_t mask, vint32mf2_t maskedoff0, vint32mf2_t maskedoff1, vint32mf2_t maskedoff2, vint32mf2_t maskedoff3, vint32mf2_t maskedoff4, const int32_t *base, ptrdiff_t bstride, size_t vl) { + return __riscv_vlsseg5e32_mu(v0, v1, v2, v3, v4, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, maskedoff4, base, bstride, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlsseg5e32_v_i32m1_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], ptr noundef [[V4:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], [[MASKEDOFF4:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[BSTRIDE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vlsseg5.mask.nxv2i32.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], [[MASKEDOFF4]], ptr [[BASE]], i64 [[BSTRIDE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 4 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 4 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 4 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , } [[TMP0]], 4 +// CHECK-RV64-NEXT: store [[TMP5]], ptr [[V4]], align 4 +// CHECK-RV64-NEXT: ret void +// +void test_vlsseg5e32_v_i32m1_mu(vint32m1_t *v0, vint32m1_t *v1, vint32m1_t *v2, vint32m1_t *v3, vint32m1_t *v4, vbool32_t mask, vint32m1_t maskedoff0, vint32m1_t maskedoff1, vint32m1_t maskedoff2, vint32m1_t maskedoff3, vint32m1_t maskedoff4, const int32_t *base, ptrdiff_t bstride, size_t vl) { + return __riscv_vlsseg5e32_mu(v0, v1, v2, v3, v4, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, maskedoff4, base, bstride, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlsseg5e32_v_u32mf2_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], ptr noundef [[V4:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], [[MASKEDOFF4:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[BSTRIDE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vlsseg5.mask.nxv1i32.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], [[MASKEDOFF4]], ptr [[BASE]], i64 [[BSTRIDE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 4 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 4 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 4 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , } [[TMP0]], 4 +// CHECK-RV64-NEXT: store [[TMP5]], ptr [[V4]], align 4 +// CHECK-RV64-NEXT: ret void +// +void test_vlsseg5e32_v_u32mf2_mu(vuint32mf2_t *v0, vuint32mf2_t *v1, vuint32mf2_t *v2, vuint32mf2_t *v3, vuint32mf2_t *v4, vbool64_t mask, vuint32mf2_t maskedoff0, vuint32mf2_t maskedoff1, vuint32mf2_t maskedoff2, vuint32mf2_t maskedoff3, vuint32mf2_t maskedoff4, const uint32_t *base, ptrdiff_t bstride, size_t vl) { + return __riscv_vlsseg5e32_mu(v0, v1, v2, v3, v4, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, maskedoff4, base, bstride, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlsseg5e32_v_u32m1_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], ptr noundef [[V4:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], [[MASKEDOFF4:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[BSTRIDE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vlsseg5.mask.nxv2i32.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], [[MASKEDOFF4]], ptr [[BASE]], i64 [[BSTRIDE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 4 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 4 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 4 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , } [[TMP0]], 4 +// CHECK-RV64-NEXT: store [[TMP5]], ptr [[V4]], align 4 +// CHECK-RV64-NEXT: ret void +// +void test_vlsseg5e32_v_u32m1_mu(vuint32m1_t *v0, vuint32m1_t *v1, vuint32m1_t *v2, vuint32m1_t *v3, vuint32m1_t *v4, vbool32_t mask, vuint32m1_t maskedoff0, vuint32m1_t maskedoff1, vuint32m1_t maskedoff2, vuint32m1_t maskedoff3, vuint32m1_t maskedoff4, const uint32_t *base, ptrdiff_t bstride, size_t vl) { + return __riscv_vlsseg5e32_mu(v0, v1, v2, v3, v4, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, maskedoff4, base, bstride, vl); +} + diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg5e64.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg5e64.c index 6383fa0bef1f8..5c97572801a08 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg5e64.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg5e64.c @@ -187,3 +187,63 @@ void test_vlsseg5e64_v_u64m1_tumu(vuint64m1_t *v0, vuint64m1_t *v1, vuint64m1_t return __riscv_vlsseg5e64_tumu(v0, v1, v2, v3, v4, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, maskedoff4, base, bstride, vl); } +// CHECK-RV64-LABEL: define dso_local void @test_vlsseg5e64_v_f64m1_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], ptr noundef [[V4:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], [[MASKEDOFF4:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[BSTRIDE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vlsseg5.mask.nxv1f64.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], [[MASKEDOFF4]], ptr [[BASE]], i64 [[BSTRIDE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 8 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 8 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 8 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 8 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , } [[TMP0]], 4 +// CHECK-RV64-NEXT: store [[TMP5]], ptr [[V4]], align 8 +// CHECK-RV64-NEXT: ret void +// +void test_vlsseg5e64_v_f64m1_mu(vfloat64m1_t *v0, vfloat64m1_t *v1, vfloat64m1_t *v2, vfloat64m1_t *v3, vfloat64m1_t *v4, vbool64_t mask, vfloat64m1_t maskedoff0, vfloat64m1_t maskedoff1, vfloat64m1_t maskedoff2, vfloat64m1_t maskedoff3, vfloat64m1_t maskedoff4, const double *base, ptrdiff_t bstride, size_t vl) { + return __riscv_vlsseg5e64_mu(v0, v1, v2, v3, v4, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, maskedoff4, base, bstride, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlsseg5e64_v_i64m1_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], ptr noundef [[V4:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], [[MASKEDOFF4:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[BSTRIDE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vlsseg5.mask.nxv1i64.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], [[MASKEDOFF4]], ptr [[BASE]], i64 [[BSTRIDE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 8 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 8 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 8 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 8 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , } [[TMP0]], 4 +// CHECK-RV64-NEXT: store [[TMP5]], ptr [[V4]], align 8 +// CHECK-RV64-NEXT: ret void +// +void test_vlsseg5e64_v_i64m1_mu(vint64m1_t *v0, vint64m1_t *v1, vint64m1_t *v2, vint64m1_t *v3, vint64m1_t *v4, vbool64_t mask, vint64m1_t maskedoff0, vint64m1_t maskedoff1, vint64m1_t maskedoff2, vint64m1_t maskedoff3, vint64m1_t maskedoff4, const int64_t *base, ptrdiff_t bstride, size_t vl) { + return __riscv_vlsseg5e64_mu(v0, v1, v2, v3, v4, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, maskedoff4, base, bstride, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlsseg5e64_v_u64m1_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], ptr noundef [[V4:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], [[MASKEDOFF4:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[BSTRIDE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vlsseg5.mask.nxv1i64.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], [[MASKEDOFF4]], ptr [[BASE]], i64 [[BSTRIDE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 8 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 8 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 8 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 8 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , } [[TMP0]], 4 +// CHECK-RV64-NEXT: store [[TMP5]], ptr [[V4]], align 8 +// CHECK-RV64-NEXT: ret void +// +void test_vlsseg5e64_v_u64m1_mu(vuint64m1_t *v0, vuint64m1_t *v1, vuint64m1_t *v2, vuint64m1_t *v3, vuint64m1_t *v4, vbool64_t mask, vuint64m1_t maskedoff0, vuint64m1_t maskedoff1, vuint64m1_t maskedoff2, vuint64m1_t maskedoff3, vuint64m1_t maskedoff4, const uint64_t *base, ptrdiff_t bstride, size_t vl) { + return __riscv_vlsseg5e64_mu(v0, v1, v2, v3, v4, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, maskedoff4, base, bstride, vl); +} + diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg5e8.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg5e8.c index cbff1790de4ec..fa21ff9aa0b9f 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg5e8.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg5e8.c @@ -486,3 +486,163 @@ void test_vlsseg5e8_v_u8m1_tumu(vuint8m1_t *v0, vuint8m1_t *v1, vuint8m1_t *v2, return __riscv_vlsseg5e8_tumu(v0, v1, v2, v3, v4, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, maskedoff4, base, bstride, vl); } +// CHECK-RV64-LABEL: define dso_local void @test_vlsseg5e8_v_i8mf8_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], ptr noundef [[V4:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], [[MASKEDOFF4:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[BSTRIDE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vlsseg5.mask.nxv1i8.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], [[MASKEDOFF4]], ptr [[BASE]], i64 [[BSTRIDE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 1 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 1 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 1 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , } [[TMP0]], 4 +// CHECK-RV64-NEXT: store [[TMP5]], ptr [[V4]], align 1 +// CHECK-RV64-NEXT: ret void +// +void test_vlsseg5e8_v_i8mf8_mu(vint8mf8_t *v0, vint8mf8_t *v1, vint8mf8_t *v2, vint8mf8_t *v3, vint8mf8_t *v4, vbool64_t mask, vint8mf8_t maskedoff0, vint8mf8_t maskedoff1, vint8mf8_t maskedoff2, vint8mf8_t maskedoff3, vint8mf8_t maskedoff4, const int8_t *base, ptrdiff_t bstride, size_t vl) { + return __riscv_vlsseg5e8_mu(v0, v1, v2, v3, v4, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, maskedoff4, base, bstride, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlsseg5e8_v_i8mf4_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], ptr noundef [[V4:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], [[MASKEDOFF4:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[BSTRIDE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vlsseg5.mask.nxv2i8.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], [[MASKEDOFF4]], ptr [[BASE]], i64 [[BSTRIDE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 1 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 1 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 1 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , } [[TMP0]], 4 +// CHECK-RV64-NEXT: store [[TMP5]], ptr [[V4]], align 1 +// CHECK-RV64-NEXT: ret void +// +void test_vlsseg5e8_v_i8mf4_mu(vint8mf4_t *v0, vint8mf4_t *v1, vint8mf4_t *v2, vint8mf4_t *v3, vint8mf4_t *v4, vbool32_t mask, vint8mf4_t maskedoff0, vint8mf4_t maskedoff1, vint8mf4_t maskedoff2, vint8mf4_t maskedoff3, vint8mf4_t maskedoff4, const int8_t *base, ptrdiff_t bstride, size_t vl) { + return __riscv_vlsseg5e8_mu(v0, v1, v2, v3, v4, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, maskedoff4, base, bstride, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlsseg5e8_v_i8mf2_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], ptr noundef [[V4:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], [[MASKEDOFF4:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[BSTRIDE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vlsseg5.mask.nxv4i8.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], [[MASKEDOFF4]], ptr [[BASE]], i64 [[BSTRIDE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 1 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 1 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 1 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , } [[TMP0]], 4 +// CHECK-RV64-NEXT: store [[TMP5]], ptr [[V4]], align 1 +// CHECK-RV64-NEXT: ret void +// +void test_vlsseg5e8_v_i8mf2_mu(vint8mf2_t *v0, vint8mf2_t *v1, vint8mf2_t *v2, vint8mf2_t *v3, vint8mf2_t *v4, vbool16_t mask, vint8mf2_t maskedoff0, vint8mf2_t maskedoff1, vint8mf2_t maskedoff2, vint8mf2_t maskedoff3, vint8mf2_t maskedoff4, const int8_t *base, ptrdiff_t bstride, size_t vl) { + return __riscv_vlsseg5e8_mu(v0, v1, v2, v3, v4, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, maskedoff4, base, bstride, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlsseg5e8_v_i8m1_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], ptr noundef [[V4:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], [[MASKEDOFF4:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[BSTRIDE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vlsseg5.mask.nxv8i8.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], [[MASKEDOFF4]], ptr [[BASE]], i64 [[BSTRIDE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 1 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 1 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 1 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , } [[TMP0]], 4 +// CHECK-RV64-NEXT: store [[TMP5]], ptr [[V4]], align 1 +// CHECK-RV64-NEXT: ret void +// +void test_vlsseg5e8_v_i8m1_mu(vint8m1_t *v0, vint8m1_t *v1, vint8m1_t *v2, vint8m1_t *v3, vint8m1_t *v4, vbool8_t mask, vint8m1_t maskedoff0, vint8m1_t maskedoff1, vint8m1_t maskedoff2, vint8m1_t maskedoff3, vint8m1_t maskedoff4, const int8_t *base, ptrdiff_t bstride, size_t vl) { + return __riscv_vlsseg5e8_mu(v0, v1, v2, v3, v4, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, maskedoff4, base, bstride, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlsseg5e8_v_u8mf8_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], ptr noundef [[V4:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], [[MASKEDOFF4:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[BSTRIDE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vlsseg5.mask.nxv1i8.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], [[MASKEDOFF4]], ptr [[BASE]], i64 [[BSTRIDE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 1 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 1 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 1 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , } [[TMP0]], 4 +// CHECK-RV64-NEXT: store [[TMP5]], ptr [[V4]], align 1 +// CHECK-RV64-NEXT: ret void +// +void test_vlsseg5e8_v_u8mf8_mu(vuint8mf8_t *v0, vuint8mf8_t *v1, vuint8mf8_t *v2, vuint8mf8_t *v3, vuint8mf8_t *v4, vbool64_t mask, vuint8mf8_t maskedoff0, vuint8mf8_t maskedoff1, vuint8mf8_t maskedoff2, vuint8mf8_t maskedoff3, vuint8mf8_t maskedoff4, const uint8_t *base, ptrdiff_t bstride, size_t vl) { + return __riscv_vlsseg5e8_mu(v0, v1, v2, v3, v4, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, maskedoff4, base, bstride, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlsseg5e8_v_u8mf4_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], ptr noundef [[V4:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], [[MASKEDOFF4:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[BSTRIDE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vlsseg5.mask.nxv2i8.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], [[MASKEDOFF4]], ptr [[BASE]], i64 [[BSTRIDE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 1 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 1 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 1 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , } [[TMP0]], 4 +// CHECK-RV64-NEXT: store [[TMP5]], ptr [[V4]], align 1 +// CHECK-RV64-NEXT: ret void +// +void test_vlsseg5e8_v_u8mf4_mu(vuint8mf4_t *v0, vuint8mf4_t *v1, vuint8mf4_t *v2, vuint8mf4_t *v3, vuint8mf4_t *v4, vbool32_t mask, vuint8mf4_t maskedoff0, vuint8mf4_t maskedoff1, vuint8mf4_t maskedoff2, vuint8mf4_t maskedoff3, vuint8mf4_t maskedoff4, const uint8_t *base, ptrdiff_t bstride, size_t vl) { + return __riscv_vlsseg5e8_mu(v0, v1, v2, v3, v4, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, maskedoff4, base, bstride, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlsseg5e8_v_u8mf2_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], ptr noundef [[V4:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], [[MASKEDOFF4:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[BSTRIDE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vlsseg5.mask.nxv4i8.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], [[MASKEDOFF4]], ptr [[BASE]], i64 [[BSTRIDE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 1 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 1 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 1 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , } [[TMP0]], 4 +// CHECK-RV64-NEXT: store [[TMP5]], ptr [[V4]], align 1 +// CHECK-RV64-NEXT: ret void +// +void test_vlsseg5e8_v_u8mf2_mu(vuint8mf2_t *v0, vuint8mf2_t *v1, vuint8mf2_t *v2, vuint8mf2_t *v3, vuint8mf2_t *v4, vbool16_t mask, vuint8mf2_t maskedoff0, vuint8mf2_t maskedoff1, vuint8mf2_t maskedoff2, vuint8mf2_t maskedoff3, vuint8mf2_t maskedoff4, const uint8_t *base, ptrdiff_t bstride, size_t vl) { + return __riscv_vlsseg5e8_mu(v0, v1, v2, v3, v4, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, maskedoff4, base, bstride, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlsseg5e8_v_u8m1_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], ptr noundef [[V4:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], [[MASKEDOFF4:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[BSTRIDE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vlsseg5.mask.nxv8i8.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], [[MASKEDOFF4]], ptr [[BASE]], i64 [[BSTRIDE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 1 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 1 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 1 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , } [[TMP0]], 4 +// CHECK-RV64-NEXT: store [[TMP5]], ptr [[V4]], align 1 +// CHECK-RV64-NEXT: ret void +// +void test_vlsseg5e8_v_u8m1_mu(vuint8m1_t *v0, vuint8m1_t *v1, vuint8m1_t *v2, vuint8m1_t *v3, vuint8m1_t *v4, vbool8_t mask, vuint8m1_t maskedoff0, vuint8m1_t maskedoff1, vuint8m1_t maskedoff2, vuint8m1_t maskedoff3, vuint8m1_t maskedoff4, const uint8_t *base, ptrdiff_t bstride, size_t vl) { + return __riscv_vlsseg5e8_mu(v0, v1, v2, v3, v4, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, maskedoff4, base, bstride, vl); +} + diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg6e16.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg6e16.c index 59fa7d30ea29d..0bb9934ae8d1e 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg6e16.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg6e16.c @@ -601,3 +601,201 @@ void test_vlsseg6e16_v_u16m1_tumu(vuint16m1_t *v0, vuint16m1_t *v1, vuint16m1_t return __riscv_vlsseg6e16_tumu(v0, v1, v2, v3, v4, v5, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, maskedoff4, maskedoff5, base, bstride, vl); } +// CHECK-RV64-LABEL: define dso_local void @test_vlsseg6e16_v_f16mf4_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], ptr noundef [[V4:%.*]], ptr noundef [[V5:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], [[MASKEDOFF4:%.*]], [[MASKEDOFF5:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[BSTRIDE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vlsseg6.mask.nxv1f16.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], [[MASKEDOFF4]], [[MASKEDOFF5]], ptr [[BASE]], i64 [[BSTRIDE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 2 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 2 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 2 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , } [[TMP0]], 4 +// CHECK-RV64-NEXT: store [[TMP5]], ptr [[V4]], align 2 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , } [[TMP0]], 5 +// CHECK-RV64-NEXT: store [[TMP6]], ptr [[V5]], align 2 +// CHECK-RV64-NEXT: ret void +// +void test_vlsseg6e16_v_f16mf4_mu(vfloat16mf4_t *v0, vfloat16mf4_t *v1, vfloat16mf4_t *v2, vfloat16mf4_t *v3, vfloat16mf4_t *v4, vfloat16mf4_t *v5, vbool64_t mask, vfloat16mf4_t maskedoff0, vfloat16mf4_t maskedoff1, vfloat16mf4_t maskedoff2, vfloat16mf4_t maskedoff3, vfloat16mf4_t maskedoff4, vfloat16mf4_t maskedoff5, const _Float16 *base, ptrdiff_t bstride, size_t vl) { + return __riscv_vlsseg6e16_mu(v0, v1, v2, v3, v4, v5, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, maskedoff4, maskedoff5, base, bstride, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlsseg6e16_v_f16mf2_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], ptr noundef [[V4:%.*]], ptr noundef [[V5:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], [[MASKEDOFF4:%.*]], [[MASKEDOFF5:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[BSTRIDE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vlsseg6.mask.nxv2f16.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], [[MASKEDOFF4]], [[MASKEDOFF5]], ptr [[BASE]], i64 [[BSTRIDE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 2 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 2 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 2 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , } [[TMP0]], 4 +// CHECK-RV64-NEXT: store [[TMP5]], ptr [[V4]], align 2 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , } [[TMP0]], 5 +// CHECK-RV64-NEXT: store [[TMP6]], ptr [[V5]], align 2 +// CHECK-RV64-NEXT: ret void +// +void test_vlsseg6e16_v_f16mf2_mu(vfloat16mf2_t *v0, vfloat16mf2_t *v1, vfloat16mf2_t *v2, vfloat16mf2_t *v3, vfloat16mf2_t *v4, vfloat16mf2_t *v5, vbool32_t mask, vfloat16mf2_t maskedoff0, vfloat16mf2_t maskedoff1, vfloat16mf2_t maskedoff2, vfloat16mf2_t maskedoff3, vfloat16mf2_t maskedoff4, vfloat16mf2_t maskedoff5, const _Float16 *base, ptrdiff_t bstride, size_t vl) { + return __riscv_vlsseg6e16_mu(v0, v1, v2, v3, v4, v5, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, maskedoff4, maskedoff5, base, bstride, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlsseg6e16_v_f16m1_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], ptr noundef [[V4:%.*]], ptr noundef [[V5:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], [[MASKEDOFF4:%.*]], [[MASKEDOFF5:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[BSTRIDE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vlsseg6.mask.nxv4f16.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], [[MASKEDOFF4]], [[MASKEDOFF5]], ptr [[BASE]], i64 [[BSTRIDE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 2 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 2 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 2 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , } [[TMP0]], 4 +// CHECK-RV64-NEXT: store [[TMP5]], ptr [[V4]], align 2 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , } [[TMP0]], 5 +// CHECK-RV64-NEXT: store [[TMP6]], ptr [[V5]], align 2 +// CHECK-RV64-NEXT: ret void +// +void test_vlsseg6e16_v_f16m1_mu(vfloat16m1_t *v0, vfloat16m1_t *v1, vfloat16m1_t *v2, vfloat16m1_t *v3, vfloat16m1_t *v4, vfloat16m1_t *v5, vbool16_t mask, vfloat16m1_t maskedoff0, vfloat16m1_t maskedoff1, vfloat16m1_t maskedoff2, vfloat16m1_t maskedoff3, vfloat16m1_t maskedoff4, vfloat16m1_t maskedoff5, const _Float16 *base, ptrdiff_t bstride, size_t vl) { + return __riscv_vlsseg6e16_mu(v0, v1, v2, v3, v4, v5, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, maskedoff4, maskedoff5, base, bstride, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlsseg6e16_v_i16mf4_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], ptr noundef [[V4:%.*]], ptr noundef [[V5:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], [[MASKEDOFF4:%.*]], [[MASKEDOFF5:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[BSTRIDE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vlsseg6.mask.nxv1i16.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], [[MASKEDOFF4]], [[MASKEDOFF5]], ptr [[BASE]], i64 [[BSTRIDE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 2 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 2 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 2 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , } [[TMP0]], 4 +// CHECK-RV64-NEXT: store [[TMP5]], ptr [[V4]], align 2 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , } [[TMP0]], 5 +// CHECK-RV64-NEXT: store [[TMP6]], ptr [[V5]], align 2 +// CHECK-RV64-NEXT: ret void +// +void test_vlsseg6e16_v_i16mf4_mu(vint16mf4_t *v0, vint16mf4_t *v1, vint16mf4_t *v2, vint16mf4_t *v3, vint16mf4_t *v4, vint16mf4_t *v5, vbool64_t mask, vint16mf4_t maskedoff0, vint16mf4_t maskedoff1, vint16mf4_t maskedoff2, vint16mf4_t maskedoff3, vint16mf4_t maskedoff4, vint16mf4_t maskedoff5, const int16_t *base, ptrdiff_t bstride, size_t vl) { + return __riscv_vlsseg6e16_mu(v0, v1, v2, v3, v4, v5, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, maskedoff4, maskedoff5, base, bstride, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlsseg6e16_v_i16mf2_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], ptr noundef [[V4:%.*]], ptr noundef [[V5:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], [[MASKEDOFF4:%.*]], [[MASKEDOFF5:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[BSTRIDE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vlsseg6.mask.nxv2i16.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], [[MASKEDOFF4]], [[MASKEDOFF5]], ptr [[BASE]], i64 [[BSTRIDE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 2 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 2 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 2 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , } [[TMP0]], 4 +// CHECK-RV64-NEXT: store [[TMP5]], ptr [[V4]], align 2 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , } [[TMP0]], 5 +// CHECK-RV64-NEXT: store [[TMP6]], ptr [[V5]], align 2 +// CHECK-RV64-NEXT: ret void +// +void test_vlsseg6e16_v_i16mf2_mu(vint16mf2_t *v0, vint16mf2_t *v1, vint16mf2_t *v2, vint16mf2_t *v3, vint16mf2_t *v4, vint16mf2_t *v5, vbool32_t mask, vint16mf2_t maskedoff0, vint16mf2_t maskedoff1, vint16mf2_t maskedoff2, vint16mf2_t maskedoff3, vint16mf2_t maskedoff4, vint16mf2_t maskedoff5, const int16_t *base, ptrdiff_t bstride, size_t vl) { + return __riscv_vlsseg6e16_mu(v0, v1, v2, v3, v4, v5, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, maskedoff4, maskedoff5, base, bstride, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlsseg6e16_v_i16m1_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], ptr noundef [[V4:%.*]], ptr noundef [[V5:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], [[MASKEDOFF4:%.*]], [[MASKEDOFF5:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[BSTRIDE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vlsseg6.mask.nxv4i16.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], [[MASKEDOFF4]], [[MASKEDOFF5]], ptr [[BASE]], i64 [[BSTRIDE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 2 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 2 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 2 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , } [[TMP0]], 4 +// CHECK-RV64-NEXT: store [[TMP5]], ptr [[V4]], align 2 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , } [[TMP0]], 5 +// CHECK-RV64-NEXT: store [[TMP6]], ptr [[V5]], align 2 +// CHECK-RV64-NEXT: ret void +// +void test_vlsseg6e16_v_i16m1_mu(vint16m1_t *v0, vint16m1_t *v1, vint16m1_t *v2, vint16m1_t *v3, vint16m1_t *v4, vint16m1_t *v5, vbool16_t mask, vint16m1_t maskedoff0, vint16m1_t maskedoff1, vint16m1_t maskedoff2, vint16m1_t maskedoff3, vint16m1_t maskedoff4, vint16m1_t maskedoff5, const int16_t *base, ptrdiff_t bstride, size_t vl) { + return __riscv_vlsseg6e16_mu(v0, v1, v2, v3, v4, v5, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, maskedoff4, maskedoff5, base, bstride, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlsseg6e16_v_u16mf4_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], ptr noundef [[V4:%.*]], ptr noundef [[V5:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], [[MASKEDOFF4:%.*]], [[MASKEDOFF5:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[BSTRIDE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vlsseg6.mask.nxv1i16.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], [[MASKEDOFF4]], [[MASKEDOFF5]], ptr [[BASE]], i64 [[BSTRIDE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 2 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 2 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 2 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , } [[TMP0]], 4 +// CHECK-RV64-NEXT: store [[TMP5]], ptr [[V4]], align 2 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , } [[TMP0]], 5 +// CHECK-RV64-NEXT: store [[TMP6]], ptr [[V5]], align 2 +// CHECK-RV64-NEXT: ret void +// +void test_vlsseg6e16_v_u16mf4_mu(vuint16mf4_t *v0, vuint16mf4_t *v1, vuint16mf4_t *v2, vuint16mf4_t *v3, vuint16mf4_t *v4, vuint16mf4_t *v5, vbool64_t mask, vuint16mf4_t maskedoff0, vuint16mf4_t maskedoff1, vuint16mf4_t maskedoff2, vuint16mf4_t maskedoff3, vuint16mf4_t maskedoff4, vuint16mf4_t maskedoff5, const uint16_t *base, ptrdiff_t bstride, size_t vl) { + return __riscv_vlsseg6e16_mu(v0, v1, v2, v3, v4, v5, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, maskedoff4, maskedoff5, base, bstride, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlsseg6e16_v_u16mf2_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], ptr noundef [[V4:%.*]], ptr noundef [[V5:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], [[MASKEDOFF4:%.*]], [[MASKEDOFF5:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[BSTRIDE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vlsseg6.mask.nxv2i16.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], [[MASKEDOFF4]], [[MASKEDOFF5]], ptr [[BASE]], i64 [[BSTRIDE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 2 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 2 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 2 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , } [[TMP0]], 4 +// CHECK-RV64-NEXT: store [[TMP5]], ptr [[V4]], align 2 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , } [[TMP0]], 5 +// CHECK-RV64-NEXT: store [[TMP6]], ptr [[V5]], align 2 +// CHECK-RV64-NEXT: ret void +// +void test_vlsseg6e16_v_u16mf2_mu(vuint16mf2_t *v0, vuint16mf2_t *v1, vuint16mf2_t *v2, vuint16mf2_t *v3, vuint16mf2_t *v4, vuint16mf2_t *v5, vbool32_t mask, vuint16mf2_t maskedoff0, vuint16mf2_t maskedoff1, vuint16mf2_t maskedoff2, vuint16mf2_t maskedoff3, vuint16mf2_t maskedoff4, vuint16mf2_t maskedoff5, const uint16_t *base, ptrdiff_t bstride, size_t vl) { + return __riscv_vlsseg6e16_mu(v0, v1, v2, v3, v4, v5, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, maskedoff4, maskedoff5, base, bstride, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlsseg6e16_v_u16m1_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], ptr noundef [[V4:%.*]], ptr noundef [[V5:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], [[MASKEDOFF4:%.*]], [[MASKEDOFF5:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[BSTRIDE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vlsseg6.mask.nxv4i16.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], [[MASKEDOFF4]], [[MASKEDOFF5]], ptr [[BASE]], i64 [[BSTRIDE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 2 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 2 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 2 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , } [[TMP0]], 4 +// CHECK-RV64-NEXT: store [[TMP5]], ptr [[V4]], align 2 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , } [[TMP0]], 5 +// CHECK-RV64-NEXT: store [[TMP6]], ptr [[V5]], align 2 +// CHECK-RV64-NEXT: ret void +// +void test_vlsseg6e16_v_u16m1_mu(vuint16m1_t *v0, vuint16m1_t *v1, vuint16m1_t *v2, vuint16m1_t *v3, vuint16m1_t *v4, vuint16m1_t *v5, vbool16_t mask, vuint16m1_t maskedoff0, vuint16m1_t maskedoff1, vuint16m1_t maskedoff2, vuint16m1_t maskedoff3, vuint16m1_t maskedoff4, vuint16m1_t maskedoff5, const uint16_t *base, ptrdiff_t bstride, size_t vl) { + return __riscv_vlsseg6e16_mu(v0, v1, v2, v3, v4, v5, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, maskedoff4, maskedoff5, base, bstride, vl); +} + diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg6e32.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg6e32.c index b9506c7e1f230..23deb0ae3d2ef 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg6e32.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg6e32.c @@ -403,3 +403,135 @@ void test_vlsseg6e32_v_u32m1_tumu(vuint32m1_t *v0, vuint32m1_t *v1, vuint32m1_t return __riscv_vlsseg6e32_tumu(v0, v1, v2, v3, v4, v5, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, maskedoff4, maskedoff5, base, bstride, vl); } +// CHECK-RV64-LABEL: define dso_local void @test_vlsseg6e32_v_f32mf2_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], ptr noundef [[V4:%.*]], ptr noundef [[V5:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], [[MASKEDOFF4:%.*]], [[MASKEDOFF5:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[BSTRIDE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vlsseg6.mask.nxv1f32.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], [[MASKEDOFF4]], [[MASKEDOFF5]], ptr [[BASE]], i64 [[BSTRIDE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 4 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 4 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 4 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , } [[TMP0]], 4 +// CHECK-RV64-NEXT: store [[TMP5]], ptr [[V4]], align 4 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , } [[TMP0]], 5 +// CHECK-RV64-NEXT: store [[TMP6]], ptr [[V5]], align 4 +// CHECK-RV64-NEXT: ret void +// +void test_vlsseg6e32_v_f32mf2_mu(vfloat32mf2_t *v0, vfloat32mf2_t *v1, vfloat32mf2_t *v2, vfloat32mf2_t *v3, vfloat32mf2_t *v4, vfloat32mf2_t *v5, vbool64_t mask, vfloat32mf2_t maskedoff0, vfloat32mf2_t maskedoff1, vfloat32mf2_t maskedoff2, vfloat32mf2_t maskedoff3, vfloat32mf2_t maskedoff4, vfloat32mf2_t maskedoff5, const float *base, ptrdiff_t bstride, size_t vl) { + return __riscv_vlsseg6e32_mu(v0, v1, v2, v3, v4, v5, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, maskedoff4, maskedoff5, base, bstride, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlsseg6e32_v_f32m1_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], ptr noundef [[V4:%.*]], ptr noundef [[V5:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], [[MASKEDOFF4:%.*]], [[MASKEDOFF5:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[BSTRIDE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vlsseg6.mask.nxv2f32.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], [[MASKEDOFF4]], [[MASKEDOFF5]], ptr [[BASE]], i64 [[BSTRIDE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 4 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 4 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 4 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , } [[TMP0]], 4 +// CHECK-RV64-NEXT: store [[TMP5]], ptr [[V4]], align 4 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , } [[TMP0]], 5 +// CHECK-RV64-NEXT: store [[TMP6]], ptr [[V5]], align 4 +// CHECK-RV64-NEXT: ret void +// +void test_vlsseg6e32_v_f32m1_mu(vfloat32m1_t *v0, vfloat32m1_t *v1, vfloat32m1_t *v2, vfloat32m1_t *v3, vfloat32m1_t *v4, vfloat32m1_t *v5, vbool32_t mask, vfloat32m1_t maskedoff0, vfloat32m1_t maskedoff1, vfloat32m1_t maskedoff2, vfloat32m1_t maskedoff3, vfloat32m1_t maskedoff4, vfloat32m1_t maskedoff5, const float *base, ptrdiff_t bstride, size_t vl) { + return __riscv_vlsseg6e32_mu(v0, v1, v2, v3, v4, v5, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, maskedoff4, maskedoff5, base, bstride, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlsseg6e32_v_i32mf2_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], ptr noundef [[V4:%.*]], ptr noundef [[V5:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], [[MASKEDOFF4:%.*]], [[MASKEDOFF5:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[BSTRIDE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vlsseg6.mask.nxv1i32.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], [[MASKEDOFF4]], [[MASKEDOFF5]], ptr [[BASE]], i64 [[BSTRIDE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 4 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 4 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 4 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , } [[TMP0]], 4 +// CHECK-RV64-NEXT: store [[TMP5]], ptr [[V4]], align 4 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , } [[TMP0]], 5 +// CHECK-RV64-NEXT: store [[TMP6]], ptr [[V5]], align 4 +// CHECK-RV64-NEXT: ret void +// +void test_vlsseg6e32_v_i32mf2_mu(vint32mf2_t *v0, vint32mf2_t *v1, vint32mf2_t *v2, vint32mf2_t *v3, vint32mf2_t *v4, vint32mf2_t *v5, vbool64_t mask, vint32mf2_t maskedoff0, vint32mf2_t maskedoff1, vint32mf2_t maskedoff2, vint32mf2_t maskedoff3, vint32mf2_t maskedoff4, vint32mf2_t maskedoff5, const int32_t *base, ptrdiff_t bstride, size_t vl) { + return __riscv_vlsseg6e32_mu(v0, v1, v2, v3, v4, v5, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, maskedoff4, maskedoff5, base, bstride, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlsseg6e32_v_i32m1_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], ptr noundef [[V4:%.*]], ptr noundef [[V5:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], [[MASKEDOFF4:%.*]], [[MASKEDOFF5:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[BSTRIDE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vlsseg6.mask.nxv2i32.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], [[MASKEDOFF4]], [[MASKEDOFF5]], ptr [[BASE]], i64 [[BSTRIDE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 4 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 4 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 4 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , } [[TMP0]], 4 +// CHECK-RV64-NEXT: store [[TMP5]], ptr [[V4]], align 4 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , } [[TMP0]], 5 +// CHECK-RV64-NEXT: store [[TMP6]], ptr [[V5]], align 4 +// CHECK-RV64-NEXT: ret void +// +void test_vlsseg6e32_v_i32m1_mu(vint32m1_t *v0, vint32m1_t *v1, vint32m1_t *v2, vint32m1_t *v3, vint32m1_t *v4, vint32m1_t *v5, vbool32_t mask, vint32m1_t maskedoff0, vint32m1_t maskedoff1, vint32m1_t maskedoff2, vint32m1_t maskedoff3, vint32m1_t maskedoff4, vint32m1_t maskedoff5, const int32_t *base, ptrdiff_t bstride, size_t vl) { + return __riscv_vlsseg6e32_mu(v0, v1, v2, v3, v4, v5, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, maskedoff4, maskedoff5, base, bstride, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlsseg6e32_v_u32mf2_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], ptr noundef [[V4:%.*]], ptr noundef [[V5:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], [[MASKEDOFF4:%.*]], [[MASKEDOFF5:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[BSTRIDE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vlsseg6.mask.nxv1i32.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], [[MASKEDOFF4]], [[MASKEDOFF5]], ptr [[BASE]], i64 [[BSTRIDE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 4 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 4 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 4 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , } [[TMP0]], 4 +// CHECK-RV64-NEXT: store [[TMP5]], ptr [[V4]], align 4 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , } [[TMP0]], 5 +// CHECK-RV64-NEXT: store [[TMP6]], ptr [[V5]], align 4 +// CHECK-RV64-NEXT: ret void +// +void test_vlsseg6e32_v_u32mf2_mu(vuint32mf2_t *v0, vuint32mf2_t *v1, vuint32mf2_t *v2, vuint32mf2_t *v3, vuint32mf2_t *v4, vuint32mf2_t *v5, vbool64_t mask, vuint32mf2_t maskedoff0, vuint32mf2_t maskedoff1, vuint32mf2_t maskedoff2, vuint32mf2_t maskedoff3, vuint32mf2_t maskedoff4, vuint32mf2_t maskedoff5, const uint32_t *base, ptrdiff_t bstride, size_t vl) { + return __riscv_vlsseg6e32_mu(v0, v1, v2, v3, v4, v5, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, maskedoff4, maskedoff5, base, bstride, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlsseg6e32_v_u32m1_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], ptr noundef [[V4:%.*]], ptr noundef [[V5:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], [[MASKEDOFF4:%.*]], [[MASKEDOFF5:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[BSTRIDE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vlsseg6.mask.nxv2i32.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], [[MASKEDOFF4]], [[MASKEDOFF5]], ptr [[BASE]], i64 [[BSTRIDE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 4 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 4 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 4 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , } [[TMP0]], 4 +// CHECK-RV64-NEXT: store [[TMP5]], ptr [[V4]], align 4 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , } [[TMP0]], 5 +// CHECK-RV64-NEXT: store [[TMP6]], ptr [[V5]], align 4 +// CHECK-RV64-NEXT: ret void +// +void test_vlsseg6e32_v_u32m1_mu(vuint32m1_t *v0, vuint32m1_t *v1, vuint32m1_t *v2, vuint32m1_t *v3, vuint32m1_t *v4, vuint32m1_t *v5, vbool32_t mask, vuint32m1_t maskedoff0, vuint32m1_t maskedoff1, vuint32m1_t maskedoff2, vuint32m1_t maskedoff3, vuint32m1_t maskedoff4, vuint32m1_t maskedoff5, const uint32_t *base, ptrdiff_t bstride, size_t vl) { + return __riscv_vlsseg6e32_mu(v0, v1, v2, v3, v4, v5, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, maskedoff4, maskedoff5, base, bstride, vl); +} + diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg6e64.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg6e64.c index 3b7e92dd15120..156f505d07520 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg6e64.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg6e64.c @@ -205,3 +205,69 @@ void test_vlsseg6e64_v_u64m1_tumu(vuint64m1_t *v0, vuint64m1_t *v1, vuint64m1_t return __riscv_vlsseg6e64_tumu(v0, v1, v2, v3, v4, v5, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, maskedoff4, maskedoff5, base, bstride, vl); } +// CHECK-RV64-LABEL: define dso_local void @test_vlsseg6e64_v_f64m1_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], ptr noundef [[V4:%.*]], ptr noundef [[V5:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], [[MASKEDOFF4:%.*]], [[MASKEDOFF5:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[BSTRIDE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vlsseg6.mask.nxv1f64.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], [[MASKEDOFF4]], [[MASKEDOFF5]], ptr [[BASE]], i64 [[BSTRIDE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 8 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 8 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 8 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 8 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , } [[TMP0]], 4 +// CHECK-RV64-NEXT: store [[TMP5]], ptr [[V4]], align 8 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , } [[TMP0]], 5 +// CHECK-RV64-NEXT: store [[TMP6]], ptr [[V5]], align 8 +// CHECK-RV64-NEXT: ret void +// +void test_vlsseg6e64_v_f64m1_mu(vfloat64m1_t *v0, vfloat64m1_t *v1, vfloat64m1_t *v2, vfloat64m1_t *v3, vfloat64m1_t *v4, vfloat64m1_t *v5, vbool64_t mask, vfloat64m1_t maskedoff0, vfloat64m1_t maskedoff1, vfloat64m1_t maskedoff2, vfloat64m1_t maskedoff3, vfloat64m1_t maskedoff4, vfloat64m1_t maskedoff5, const double *base, ptrdiff_t bstride, size_t vl) { + return __riscv_vlsseg6e64_mu(v0, v1, v2, v3, v4, v5, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, maskedoff4, maskedoff5, base, bstride, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlsseg6e64_v_i64m1_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], ptr noundef [[V4:%.*]], ptr noundef [[V5:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], [[MASKEDOFF4:%.*]], [[MASKEDOFF5:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[BSTRIDE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vlsseg6.mask.nxv1i64.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], [[MASKEDOFF4]], [[MASKEDOFF5]], ptr [[BASE]], i64 [[BSTRIDE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 8 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 8 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 8 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 8 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , } [[TMP0]], 4 +// CHECK-RV64-NEXT: store [[TMP5]], ptr [[V4]], align 8 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , } [[TMP0]], 5 +// CHECK-RV64-NEXT: store [[TMP6]], ptr [[V5]], align 8 +// CHECK-RV64-NEXT: ret void +// +void test_vlsseg6e64_v_i64m1_mu(vint64m1_t *v0, vint64m1_t *v1, vint64m1_t *v2, vint64m1_t *v3, vint64m1_t *v4, vint64m1_t *v5, vbool64_t mask, vint64m1_t maskedoff0, vint64m1_t maskedoff1, vint64m1_t maskedoff2, vint64m1_t maskedoff3, vint64m1_t maskedoff4, vint64m1_t maskedoff5, const int64_t *base, ptrdiff_t bstride, size_t vl) { + return __riscv_vlsseg6e64_mu(v0, v1, v2, v3, v4, v5, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, maskedoff4, maskedoff5, base, bstride, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlsseg6e64_v_u64m1_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], ptr noundef [[V4:%.*]], ptr noundef [[V5:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], [[MASKEDOFF4:%.*]], [[MASKEDOFF5:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[BSTRIDE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vlsseg6.mask.nxv1i64.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], [[MASKEDOFF4]], [[MASKEDOFF5]], ptr [[BASE]], i64 [[BSTRIDE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 8 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 8 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 8 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 8 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , } [[TMP0]], 4 +// CHECK-RV64-NEXT: store [[TMP5]], ptr [[V4]], align 8 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , } [[TMP0]], 5 +// CHECK-RV64-NEXT: store [[TMP6]], ptr [[V5]], align 8 +// CHECK-RV64-NEXT: ret void +// +void test_vlsseg6e64_v_u64m1_mu(vuint64m1_t *v0, vuint64m1_t *v1, vuint64m1_t *v2, vuint64m1_t *v3, vuint64m1_t *v4, vuint64m1_t *v5, vbool64_t mask, vuint64m1_t maskedoff0, vuint64m1_t maskedoff1, vuint64m1_t maskedoff2, vuint64m1_t maskedoff3, vuint64m1_t maskedoff4, vuint64m1_t maskedoff5, const uint64_t *base, ptrdiff_t bstride, size_t vl) { + return __riscv_vlsseg6e64_mu(v0, v1, v2, v3, v4, v5, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, maskedoff4, maskedoff5, base, bstride, vl); +} + diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg6e8.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg6e8.c index ce8e87c44de4e..dbf7a410a7fb8 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg6e8.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg6e8.c @@ -534,3 +534,179 @@ void test_vlsseg6e8_v_u8m1_tumu(vuint8m1_t *v0, vuint8m1_t *v1, vuint8m1_t *v2, return __riscv_vlsseg6e8_tumu(v0, v1, v2, v3, v4, v5, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, maskedoff4, maskedoff5, base, bstride, vl); } +// CHECK-RV64-LABEL: define dso_local void @test_vlsseg6e8_v_i8mf8_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], ptr noundef [[V4:%.*]], ptr noundef [[V5:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], [[MASKEDOFF4:%.*]], [[MASKEDOFF5:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[BSTRIDE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vlsseg6.mask.nxv1i8.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], [[MASKEDOFF4]], [[MASKEDOFF5]], ptr [[BASE]], i64 [[BSTRIDE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 1 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 1 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 1 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , } [[TMP0]], 4 +// CHECK-RV64-NEXT: store [[TMP5]], ptr [[V4]], align 1 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , } [[TMP0]], 5 +// CHECK-RV64-NEXT: store [[TMP6]], ptr [[V5]], align 1 +// CHECK-RV64-NEXT: ret void +// +void test_vlsseg6e8_v_i8mf8_mu(vint8mf8_t *v0, vint8mf8_t *v1, vint8mf8_t *v2, vint8mf8_t *v3, vint8mf8_t *v4, vint8mf8_t *v5, vbool64_t mask, vint8mf8_t maskedoff0, vint8mf8_t maskedoff1, vint8mf8_t maskedoff2, vint8mf8_t maskedoff3, vint8mf8_t maskedoff4, vint8mf8_t maskedoff5, const int8_t *base, ptrdiff_t bstride, size_t vl) { + return __riscv_vlsseg6e8_mu(v0, v1, v2, v3, v4, v5, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, maskedoff4, maskedoff5, base, bstride, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlsseg6e8_v_i8mf4_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], ptr noundef [[V4:%.*]], ptr noundef [[V5:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], [[MASKEDOFF4:%.*]], [[MASKEDOFF5:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[BSTRIDE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vlsseg6.mask.nxv2i8.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], [[MASKEDOFF4]], [[MASKEDOFF5]], ptr [[BASE]], i64 [[BSTRIDE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 1 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 1 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 1 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , } [[TMP0]], 4 +// CHECK-RV64-NEXT: store [[TMP5]], ptr [[V4]], align 1 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , } [[TMP0]], 5 +// CHECK-RV64-NEXT: store [[TMP6]], ptr [[V5]], align 1 +// CHECK-RV64-NEXT: ret void +// +void test_vlsseg6e8_v_i8mf4_mu(vint8mf4_t *v0, vint8mf4_t *v1, vint8mf4_t *v2, vint8mf4_t *v3, vint8mf4_t *v4, vint8mf4_t *v5, vbool32_t mask, vint8mf4_t maskedoff0, vint8mf4_t maskedoff1, vint8mf4_t maskedoff2, vint8mf4_t maskedoff3, vint8mf4_t maskedoff4, vint8mf4_t maskedoff5, const int8_t *base, ptrdiff_t bstride, size_t vl) { + return __riscv_vlsseg6e8_mu(v0, v1, v2, v3, v4, v5, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, maskedoff4, maskedoff5, base, bstride, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlsseg6e8_v_i8mf2_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], ptr noundef [[V4:%.*]], ptr noundef [[V5:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], [[MASKEDOFF4:%.*]], [[MASKEDOFF5:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[BSTRIDE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vlsseg6.mask.nxv4i8.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], [[MASKEDOFF4]], [[MASKEDOFF5]], ptr [[BASE]], i64 [[BSTRIDE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 1 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 1 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 1 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , } [[TMP0]], 4 +// CHECK-RV64-NEXT: store [[TMP5]], ptr [[V4]], align 1 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , } [[TMP0]], 5 +// CHECK-RV64-NEXT: store [[TMP6]], ptr [[V5]], align 1 +// CHECK-RV64-NEXT: ret void +// +void test_vlsseg6e8_v_i8mf2_mu(vint8mf2_t *v0, vint8mf2_t *v1, vint8mf2_t *v2, vint8mf2_t *v3, vint8mf2_t *v4, vint8mf2_t *v5, vbool16_t mask, vint8mf2_t maskedoff0, vint8mf2_t maskedoff1, vint8mf2_t maskedoff2, vint8mf2_t maskedoff3, vint8mf2_t maskedoff4, vint8mf2_t maskedoff5, const int8_t *base, ptrdiff_t bstride, size_t vl) { + return __riscv_vlsseg6e8_mu(v0, v1, v2, v3, v4, v5, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, maskedoff4, maskedoff5, base, bstride, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlsseg6e8_v_i8m1_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], ptr noundef [[V4:%.*]], ptr noundef [[V5:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], [[MASKEDOFF4:%.*]], [[MASKEDOFF5:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[BSTRIDE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vlsseg6.mask.nxv8i8.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], [[MASKEDOFF4]], [[MASKEDOFF5]], ptr [[BASE]], i64 [[BSTRIDE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 1 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 1 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 1 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , } [[TMP0]], 4 +// CHECK-RV64-NEXT: store [[TMP5]], ptr [[V4]], align 1 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , } [[TMP0]], 5 +// CHECK-RV64-NEXT: store [[TMP6]], ptr [[V5]], align 1 +// CHECK-RV64-NEXT: ret void +// +void test_vlsseg6e8_v_i8m1_mu(vint8m1_t *v0, vint8m1_t *v1, vint8m1_t *v2, vint8m1_t *v3, vint8m1_t *v4, vint8m1_t *v5, vbool8_t mask, vint8m1_t maskedoff0, vint8m1_t maskedoff1, vint8m1_t maskedoff2, vint8m1_t maskedoff3, vint8m1_t maskedoff4, vint8m1_t maskedoff5, const int8_t *base, ptrdiff_t bstride, size_t vl) { + return __riscv_vlsseg6e8_mu(v0, v1, v2, v3, v4, v5, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, maskedoff4, maskedoff5, base, bstride, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlsseg6e8_v_u8mf8_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], ptr noundef [[V4:%.*]], ptr noundef [[V5:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], [[MASKEDOFF4:%.*]], [[MASKEDOFF5:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[BSTRIDE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vlsseg6.mask.nxv1i8.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], [[MASKEDOFF4]], [[MASKEDOFF5]], ptr [[BASE]], i64 [[BSTRIDE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 1 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 1 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 1 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , } [[TMP0]], 4 +// CHECK-RV64-NEXT: store [[TMP5]], ptr [[V4]], align 1 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , } [[TMP0]], 5 +// CHECK-RV64-NEXT: store [[TMP6]], ptr [[V5]], align 1 +// CHECK-RV64-NEXT: ret void +// +void test_vlsseg6e8_v_u8mf8_mu(vuint8mf8_t *v0, vuint8mf8_t *v1, vuint8mf8_t *v2, vuint8mf8_t *v3, vuint8mf8_t *v4, vuint8mf8_t *v5, vbool64_t mask, vuint8mf8_t maskedoff0, vuint8mf8_t maskedoff1, vuint8mf8_t maskedoff2, vuint8mf8_t maskedoff3, vuint8mf8_t maskedoff4, vuint8mf8_t maskedoff5, const uint8_t *base, ptrdiff_t bstride, size_t vl) { + return __riscv_vlsseg6e8_mu(v0, v1, v2, v3, v4, v5, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, maskedoff4, maskedoff5, base, bstride, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlsseg6e8_v_u8mf4_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], ptr noundef [[V4:%.*]], ptr noundef [[V5:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], [[MASKEDOFF4:%.*]], [[MASKEDOFF5:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[BSTRIDE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vlsseg6.mask.nxv2i8.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], [[MASKEDOFF4]], [[MASKEDOFF5]], ptr [[BASE]], i64 [[BSTRIDE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 1 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 1 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 1 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , } [[TMP0]], 4 +// CHECK-RV64-NEXT: store [[TMP5]], ptr [[V4]], align 1 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , } [[TMP0]], 5 +// CHECK-RV64-NEXT: store [[TMP6]], ptr [[V5]], align 1 +// CHECK-RV64-NEXT: ret void +// +void test_vlsseg6e8_v_u8mf4_mu(vuint8mf4_t *v0, vuint8mf4_t *v1, vuint8mf4_t *v2, vuint8mf4_t *v3, vuint8mf4_t *v4, vuint8mf4_t *v5, vbool32_t mask, vuint8mf4_t maskedoff0, vuint8mf4_t maskedoff1, vuint8mf4_t maskedoff2, vuint8mf4_t maskedoff3, vuint8mf4_t maskedoff4, vuint8mf4_t maskedoff5, const uint8_t *base, ptrdiff_t bstride, size_t vl) { + return __riscv_vlsseg6e8_mu(v0, v1, v2, v3, v4, v5, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, maskedoff4, maskedoff5, base, bstride, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlsseg6e8_v_u8mf2_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], ptr noundef [[V4:%.*]], ptr noundef [[V5:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], [[MASKEDOFF4:%.*]], [[MASKEDOFF5:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[BSTRIDE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vlsseg6.mask.nxv4i8.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], [[MASKEDOFF4]], [[MASKEDOFF5]], ptr [[BASE]], i64 [[BSTRIDE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 1 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 1 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 1 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , } [[TMP0]], 4 +// CHECK-RV64-NEXT: store [[TMP5]], ptr [[V4]], align 1 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , } [[TMP0]], 5 +// CHECK-RV64-NEXT: store [[TMP6]], ptr [[V5]], align 1 +// CHECK-RV64-NEXT: ret void +// +void test_vlsseg6e8_v_u8mf2_mu(vuint8mf2_t *v0, vuint8mf2_t *v1, vuint8mf2_t *v2, vuint8mf2_t *v3, vuint8mf2_t *v4, vuint8mf2_t *v5, vbool16_t mask, vuint8mf2_t maskedoff0, vuint8mf2_t maskedoff1, vuint8mf2_t maskedoff2, vuint8mf2_t maskedoff3, vuint8mf2_t maskedoff4, vuint8mf2_t maskedoff5, const uint8_t *base, ptrdiff_t bstride, size_t vl) { + return __riscv_vlsseg6e8_mu(v0, v1, v2, v3, v4, v5, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, maskedoff4, maskedoff5, base, bstride, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlsseg6e8_v_u8m1_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], ptr noundef [[V4:%.*]], ptr noundef [[V5:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], [[MASKEDOFF4:%.*]], [[MASKEDOFF5:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[BSTRIDE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vlsseg6.mask.nxv8i8.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], [[MASKEDOFF4]], [[MASKEDOFF5]], ptr [[BASE]], i64 [[BSTRIDE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 1 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 1 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 1 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , } [[TMP0]], 4 +// CHECK-RV64-NEXT: store [[TMP5]], ptr [[V4]], align 1 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , } [[TMP0]], 5 +// CHECK-RV64-NEXT: store [[TMP6]], ptr [[V5]], align 1 +// CHECK-RV64-NEXT: ret void +// +void test_vlsseg6e8_v_u8m1_mu(vuint8m1_t *v0, vuint8m1_t *v1, vuint8m1_t *v2, vuint8m1_t *v3, vuint8m1_t *v4, vuint8m1_t *v5, vbool8_t mask, vuint8m1_t maskedoff0, vuint8m1_t maskedoff1, vuint8m1_t maskedoff2, vuint8m1_t maskedoff3, vuint8m1_t maskedoff4, vuint8m1_t maskedoff5, const uint8_t *base, ptrdiff_t bstride, size_t vl) { + return __riscv_vlsseg6e8_mu(v0, v1, v2, v3, v4, v5, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, maskedoff4, maskedoff5, base, bstride, vl); +} + diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg7e16.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg7e16.c index 30ea2a334deeb..194aed96b182e 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg7e16.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg7e16.c @@ -655,3 +655,219 @@ void test_vlsseg7e16_v_u16m1_tumu(vuint16m1_t *v0, vuint16m1_t *v1, vuint16m1_t return __riscv_vlsseg7e16_tumu(v0, v1, v2, v3, v4, v5, v6, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, maskedoff4, maskedoff5, maskedoff6, base, bstride, vl); } +// CHECK-RV64-LABEL: define dso_local void @test_vlsseg7e16_v_f16mf4_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], ptr noundef [[V4:%.*]], ptr noundef [[V5:%.*]], ptr noundef [[V6:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], [[MASKEDOFF4:%.*]], [[MASKEDOFF5:%.*]], [[MASKEDOFF6:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[BSTRIDE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vlsseg7.mask.nxv1f16.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], [[MASKEDOFF4]], [[MASKEDOFF5]], [[MASKEDOFF6]], ptr [[BASE]], i64 [[BSTRIDE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 2 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 2 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 2 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , } [[TMP0]], 4 +// CHECK-RV64-NEXT: store [[TMP5]], ptr [[V4]], align 2 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , } [[TMP0]], 5 +// CHECK-RV64-NEXT: store [[TMP6]], ptr [[V5]], align 2 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , } [[TMP0]], 6 +// CHECK-RV64-NEXT: store [[TMP7]], ptr [[V6]], align 2 +// CHECK-RV64-NEXT: ret void +// +void test_vlsseg7e16_v_f16mf4_mu(vfloat16mf4_t *v0, vfloat16mf4_t *v1, vfloat16mf4_t *v2, vfloat16mf4_t *v3, vfloat16mf4_t *v4, vfloat16mf4_t *v5, vfloat16mf4_t *v6, vbool64_t mask, vfloat16mf4_t maskedoff0, vfloat16mf4_t maskedoff1, vfloat16mf4_t maskedoff2, vfloat16mf4_t maskedoff3, vfloat16mf4_t maskedoff4, vfloat16mf4_t maskedoff5, vfloat16mf4_t maskedoff6, const _Float16 *base, ptrdiff_t bstride, size_t vl) { + return __riscv_vlsseg7e16_mu(v0, v1, v2, v3, v4, v5, v6, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, maskedoff4, maskedoff5, maskedoff6, base, bstride, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlsseg7e16_v_f16mf2_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], ptr noundef [[V4:%.*]], ptr noundef [[V5:%.*]], ptr noundef [[V6:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], [[MASKEDOFF4:%.*]], [[MASKEDOFF5:%.*]], [[MASKEDOFF6:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[BSTRIDE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vlsseg7.mask.nxv2f16.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], [[MASKEDOFF4]], [[MASKEDOFF5]], [[MASKEDOFF6]], ptr [[BASE]], i64 [[BSTRIDE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 2 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 2 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 2 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , } [[TMP0]], 4 +// CHECK-RV64-NEXT: store [[TMP5]], ptr [[V4]], align 2 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , } [[TMP0]], 5 +// CHECK-RV64-NEXT: store [[TMP6]], ptr [[V5]], align 2 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , } [[TMP0]], 6 +// CHECK-RV64-NEXT: store [[TMP7]], ptr [[V6]], align 2 +// CHECK-RV64-NEXT: ret void +// +void test_vlsseg7e16_v_f16mf2_mu(vfloat16mf2_t *v0, vfloat16mf2_t *v1, vfloat16mf2_t *v2, vfloat16mf2_t *v3, vfloat16mf2_t *v4, vfloat16mf2_t *v5, vfloat16mf2_t *v6, vbool32_t mask, vfloat16mf2_t maskedoff0, vfloat16mf2_t maskedoff1, vfloat16mf2_t maskedoff2, vfloat16mf2_t maskedoff3, vfloat16mf2_t maskedoff4, vfloat16mf2_t maskedoff5, vfloat16mf2_t maskedoff6, const _Float16 *base, ptrdiff_t bstride, size_t vl) { + return __riscv_vlsseg7e16_mu(v0, v1, v2, v3, v4, v5, v6, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, maskedoff4, maskedoff5, maskedoff6, base, bstride, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlsseg7e16_v_f16m1_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], ptr noundef [[V4:%.*]], ptr noundef [[V5:%.*]], ptr noundef [[V6:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], [[MASKEDOFF4:%.*]], [[MASKEDOFF5:%.*]], [[MASKEDOFF6:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[BSTRIDE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vlsseg7.mask.nxv4f16.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], [[MASKEDOFF4]], [[MASKEDOFF5]], [[MASKEDOFF6]], ptr [[BASE]], i64 [[BSTRIDE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 2 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 2 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 2 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , } [[TMP0]], 4 +// CHECK-RV64-NEXT: store [[TMP5]], ptr [[V4]], align 2 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , } [[TMP0]], 5 +// CHECK-RV64-NEXT: store [[TMP6]], ptr [[V5]], align 2 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , } [[TMP0]], 6 +// CHECK-RV64-NEXT: store [[TMP7]], ptr [[V6]], align 2 +// CHECK-RV64-NEXT: ret void +// +void test_vlsseg7e16_v_f16m1_mu(vfloat16m1_t *v0, vfloat16m1_t *v1, vfloat16m1_t *v2, vfloat16m1_t *v3, vfloat16m1_t *v4, vfloat16m1_t *v5, vfloat16m1_t *v6, vbool16_t mask, vfloat16m1_t maskedoff0, vfloat16m1_t maskedoff1, vfloat16m1_t maskedoff2, vfloat16m1_t maskedoff3, vfloat16m1_t maskedoff4, vfloat16m1_t maskedoff5, vfloat16m1_t maskedoff6, const _Float16 *base, ptrdiff_t bstride, size_t vl) { + return __riscv_vlsseg7e16_mu(v0, v1, v2, v3, v4, v5, v6, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, maskedoff4, maskedoff5, maskedoff6, base, bstride, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlsseg7e16_v_i16mf4_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], ptr noundef [[V4:%.*]], ptr noundef [[V5:%.*]], ptr noundef [[V6:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], [[MASKEDOFF4:%.*]], [[MASKEDOFF5:%.*]], [[MASKEDOFF6:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[BSTRIDE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vlsseg7.mask.nxv1i16.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], [[MASKEDOFF4]], [[MASKEDOFF5]], [[MASKEDOFF6]], ptr [[BASE]], i64 [[BSTRIDE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 2 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 2 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 2 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , } [[TMP0]], 4 +// CHECK-RV64-NEXT: store [[TMP5]], ptr [[V4]], align 2 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , } [[TMP0]], 5 +// CHECK-RV64-NEXT: store [[TMP6]], ptr [[V5]], align 2 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , } [[TMP0]], 6 +// CHECK-RV64-NEXT: store [[TMP7]], ptr [[V6]], align 2 +// CHECK-RV64-NEXT: ret void +// +void test_vlsseg7e16_v_i16mf4_mu(vint16mf4_t *v0, vint16mf4_t *v1, vint16mf4_t *v2, vint16mf4_t *v3, vint16mf4_t *v4, vint16mf4_t *v5, vint16mf4_t *v6, vbool64_t mask, vint16mf4_t maskedoff0, vint16mf4_t maskedoff1, vint16mf4_t maskedoff2, vint16mf4_t maskedoff3, vint16mf4_t maskedoff4, vint16mf4_t maskedoff5, vint16mf4_t maskedoff6, const int16_t *base, ptrdiff_t bstride, size_t vl) { + return __riscv_vlsseg7e16_mu(v0, v1, v2, v3, v4, v5, v6, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, maskedoff4, maskedoff5, maskedoff6, base, bstride, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlsseg7e16_v_i16mf2_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], ptr noundef [[V4:%.*]], ptr noundef [[V5:%.*]], ptr noundef [[V6:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], [[MASKEDOFF4:%.*]], [[MASKEDOFF5:%.*]], [[MASKEDOFF6:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[BSTRIDE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vlsseg7.mask.nxv2i16.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], [[MASKEDOFF4]], [[MASKEDOFF5]], [[MASKEDOFF6]], ptr [[BASE]], i64 [[BSTRIDE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 2 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 2 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 2 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , } [[TMP0]], 4 +// CHECK-RV64-NEXT: store [[TMP5]], ptr [[V4]], align 2 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , } [[TMP0]], 5 +// CHECK-RV64-NEXT: store [[TMP6]], ptr [[V5]], align 2 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , } [[TMP0]], 6 +// CHECK-RV64-NEXT: store [[TMP7]], ptr [[V6]], align 2 +// CHECK-RV64-NEXT: ret void +// +void test_vlsseg7e16_v_i16mf2_mu(vint16mf2_t *v0, vint16mf2_t *v1, vint16mf2_t *v2, vint16mf2_t *v3, vint16mf2_t *v4, vint16mf2_t *v5, vint16mf2_t *v6, vbool32_t mask, vint16mf2_t maskedoff0, vint16mf2_t maskedoff1, vint16mf2_t maskedoff2, vint16mf2_t maskedoff3, vint16mf2_t maskedoff4, vint16mf2_t maskedoff5, vint16mf2_t maskedoff6, const int16_t *base, ptrdiff_t bstride, size_t vl) { + return __riscv_vlsseg7e16_mu(v0, v1, v2, v3, v4, v5, v6, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, maskedoff4, maskedoff5, maskedoff6, base, bstride, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlsseg7e16_v_i16m1_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], ptr noundef [[V4:%.*]], ptr noundef [[V5:%.*]], ptr noundef [[V6:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], [[MASKEDOFF4:%.*]], [[MASKEDOFF5:%.*]], [[MASKEDOFF6:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[BSTRIDE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vlsseg7.mask.nxv4i16.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], [[MASKEDOFF4]], [[MASKEDOFF5]], [[MASKEDOFF6]], ptr [[BASE]], i64 [[BSTRIDE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 2 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 2 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 2 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , } [[TMP0]], 4 +// CHECK-RV64-NEXT: store [[TMP5]], ptr [[V4]], align 2 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , } [[TMP0]], 5 +// CHECK-RV64-NEXT: store [[TMP6]], ptr [[V5]], align 2 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , } [[TMP0]], 6 +// CHECK-RV64-NEXT: store [[TMP7]], ptr [[V6]], align 2 +// CHECK-RV64-NEXT: ret void +// +void test_vlsseg7e16_v_i16m1_mu(vint16m1_t *v0, vint16m1_t *v1, vint16m1_t *v2, vint16m1_t *v3, vint16m1_t *v4, vint16m1_t *v5, vint16m1_t *v6, vbool16_t mask, vint16m1_t maskedoff0, vint16m1_t maskedoff1, vint16m1_t maskedoff2, vint16m1_t maskedoff3, vint16m1_t maskedoff4, vint16m1_t maskedoff5, vint16m1_t maskedoff6, const int16_t *base, ptrdiff_t bstride, size_t vl) { + return __riscv_vlsseg7e16_mu(v0, v1, v2, v3, v4, v5, v6, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, maskedoff4, maskedoff5, maskedoff6, base, bstride, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlsseg7e16_v_u16mf4_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], ptr noundef [[V4:%.*]], ptr noundef [[V5:%.*]], ptr noundef [[V6:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], [[MASKEDOFF4:%.*]], [[MASKEDOFF5:%.*]], [[MASKEDOFF6:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[BSTRIDE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vlsseg7.mask.nxv1i16.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], [[MASKEDOFF4]], [[MASKEDOFF5]], [[MASKEDOFF6]], ptr [[BASE]], i64 [[BSTRIDE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 2 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 2 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 2 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , } [[TMP0]], 4 +// CHECK-RV64-NEXT: store [[TMP5]], ptr [[V4]], align 2 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , } [[TMP0]], 5 +// CHECK-RV64-NEXT: store [[TMP6]], ptr [[V5]], align 2 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , } [[TMP0]], 6 +// CHECK-RV64-NEXT: store [[TMP7]], ptr [[V6]], align 2 +// CHECK-RV64-NEXT: ret void +// +void test_vlsseg7e16_v_u16mf4_mu(vuint16mf4_t *v0, vuint16mf4_t *v1, vuint16mf4_t *v2, vuint16mf4_t *v3, vuint16mf4_t *v4, vuint16mf4_t *v5, vuint16mf4_t *v6, vbool64_t mask, vuint16mf4_t maskedoff0, vuint16mf4_t maskedoff1, vuint16mf4_t maskedoff2, vuint16mf4_t maskedoff3, vuint16mf4_t maskedoff4, vuint16mf4_t maskedoff5, vuint16mf4_t maskedoff6, const uint16_t *base, ptrdiff_t bstride, size_t vl) { + return __riscv_vlsseg7e16_mu(v0, v1, v2, v3, v4, v5, v6, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, maskedoff4, maskedoff5, maskedoff6, base, bstride, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlsseg7e16_v_u16mf2_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], ptr noundef [[V4:%.*]], ptr noundef [[V5:%.*]], ptr noundef [[V6:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], [[MASKEDOFF4:%.*]], [[MASKEDOFF5:%.*]], [[MASKEDOFF6:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[BSTRIDE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vlsseg7.mask.nxv2i16.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], [[MASKEDOFF4]], [[MASKEDOFF5]], [[MASKEDOFF6]], ptr [[BASE]], i64 [[BSTRIDE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 2 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 2 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 2 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , } [[TMP0]], 4 +// CHECK-RV64-NEXT: store [[TMP5]], ptr [[V4]], align 2 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , } [[TMP0]], 5 +// CHECK-RV64-NEXT: store [[TMP6]], ptr [[V5]], align 2 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , } [[TMP0]], 6 +// CHECK-RV64-NEXT: store [[TMP7]], ptr [[V6]], align 2 +// CHECK-RV64-NEXT: ret void +// +void test_vlsseg7e16_v_u16mf2_mu(vuint16mf2_t *v0, vuint16mf2_t *v1, vuint16mf2_t *v2, vuint16mf2_t *v3, vuint16mf2_t *v4, vuint16mf2_t *v5, vuint16mf2_t *v6, vbool32_t mask, vuint16mf2_t maskedoff0, vuint16mf2_t maskedoff1, vuint16mf2_t maskedoff2, vuint16mf2_t maskedoff3, vuint16mf2_t maskedoff4, vuint16mf2_t maskedoff5, vuint16mf2_t maskedoff6, const uint16_t *base, ptrdiff_t bstride, size_t vl) { + return __riscv_vlsseg7e16_mu(v0, v1, v2, v3, v4, v5, v6, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, maskedoff4, maskedoff5, maskedoff6, base, bstride, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlsseg7e16_v_u16m1_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], ptr noundef [[V4:%.*]], ptr noundef [[V5:%.*]], ptr noundef [[V6:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], [[MASKEDOFF4:%.*]], [[MASKEDOFF5:%.*]], [[MASKEDOFF6:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[BSTRIDE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vlsseg7.mask.nxv4i16.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], [[MASKEDOFF4]], [[MASKEDOFF5]], [[MASKEDOFF6]], ptr [[BASE]], i64 [[BSTRIDE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 2 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 2 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 2 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , } [[TMP0]], 4 +// CHECK-RV64-NEXT: store [[TMP5]], ptr [[V4]], align 2 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , } [[TMP0]], 5 +// CHECK-RV64-NEXT: store [[TMP6]], ptr [[V5]], align 2 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , } [[TMP0]], 6 +// CHECK-RV64-NEXT: store [[TMP7]], ptr [[V6]], align 2 +// CHECK-RV64-NEXT: ret void +// +void test_vlsseg7e16_v_u16m1_mu(vuint16m1_t *v0, vuint16m1_t *v1, vuint16m1_t *v2, vuint16m1_t *v3, vuint16m1_t *v4, vuint16m1_t *v5, vuint16m1_t *v6, vbool16_t mask, vuint16m1_t maskedoff0, vuint16m1_t maskedoff1, vuint16m1_t maskedoff2, vuint16m1_t maskedoff3, vuint16m1_t maskedoff4, vuint16m1_t maskedoff5, vuint16m1_t maskedoff6, const uint16_t *base, ptrdiff_t bstride, size_t vl) { + return __riscv_vlsseg7e16_mu(v0, v1, v2, v3, v4, v5, v6, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, maskedoff4, maskedoff5, maskedoff6, base, bstride, vl); +} + diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg7e32.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg7e32.c index 688a3d0d423c6..83f9b819ce4b2 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg7e32.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg7e32.c @@ -439,3 +439,147 @@ void test_vlsseg7e32_v_u32m1_tumu(vuint32m1_t *v0, vuint32m1_t *v1, vuint32m1_t return __riscv_vlsseg7e32_tumu(v0, v1, v2, v3, v4, v5, v6, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, maskedoff4, maskedoff5, maskedoff6, base, bstride, vl); } +// CHECK-RV64-LABEL: define dso_local void @test_vlsseg7e32_v_f32mf2_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], ptr noundef [[V4:%.*]], ptr noundef [[V5:%.*]], ptr noundef [[V6:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], [[MASKEDOFF4:%.*]], [[MASKEDOFF5:%.*]], [[MASKEDOFF6:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[BSTRIDE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vlsseg7.mask.nxv1f32.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], [[MASKEDOFF4]], [[MASKEDOFF5]], [[MASKEDOFF6]], ptr [[BASE]], i64 [[BSTRIDE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 4 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 4 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 4 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , } [[TMP0]], 4 +// CHECK-RV64-NEXT: store [[TMP5]], ptr [[V4]], align 4 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , } [[TMP0]], 5 +// CHECK-RV64-NEXT: store [[TMP6]], ptr [[V5]], align 4 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , } [[TMP0]], 6 +// CHECK-RV64-NEXT: store [[TMP7]], ptr [[V6]], align 4 +// CHECK-RV64-NEXT: ret void +// +void test_vlsseg7e32_v_f32mf2_mu(vfloat32mf2_t *v0, vfloat32mf2_t *v1, vfloat32mf2_t *v2, vfloat32mf2_t *v3, vfloat32mf2_t *v4, vfloat32mf2_t *v5, vfloat32mf2_t *v6, vbool64_t mask, vfloat32mf2_t maskedoff0, vfloat32mf2_t maskedoff1, vfloat32mf2_t maskedoff2, vfloat32mf2_t maskedoff3, vfloat32mf2_t maskedoff4, vfloat32mf2_t maskedoff5, vfloat32mf2_t maskedoff6, const float *base, ptrdiff_t bstride, size_t vl) { + return __riscv_vlsseg7e32_mu(v0, v1, v2, v3, v4, v5, v6, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, maskedoff4, maskedoff5, maskedoff6, base, bstride, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlsseg7e32_v_f32m1_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], ptr noundef [[V4:%.*]], ptr noundef [[V5:%.*]], ptr noundef [[V6:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], [[MASKEDOFF4:%.*]], [[MASKEDOFF5:%.*]], [[MASKEDOFF6:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[BSTRIDE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vlsseg7.mask.nxv2f32.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], [[MASKEDOFF4]], [[MASKEDOFF5]], [[MASKEDOFF6]], ptr [[BASE]], i64 [[BSTRIDE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 4 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 4 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 4 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , } [[TMP0]], 4 +// CHECK-RV64-NEXT: store [[TMP5]], ptr [[V4]], align 4 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , } [[TMP0]], 5 +// CHECK-RV64-NEXT: store [[TMP6]], ptr [[V5]], align 4 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , } [[TMP0]], 6 +// CHECK-RV64-NEXT: store [[TMP7]], ptr [[V6]], align 4 +// CHECK-RV64-NEXT: ret void +// +void test_vlsseg7e32_v_f32m1_mu(vfloat32m1_t *v0, vfloat32m1_t *v1, vfloat32m1_t *v2, vfloat32m1_t *v3, vfloat32m1_t *v4, vfloat32m1_t *v5, vfloat32m1_t *v6, vbool32_t mask, vfloat32m1_t maskedoff0, vfloat32m1_t maskedoff1, vfloat32m1_t maskedoff2, vfloat32m1_t maskedoff3, vfloat32m1_t maskedoff4, vfloat32m1_t maskedoff5, vfloat32m1_t maskedoff6, const float *base, ptrdiff_t bstride, size_t vl) { + return __riscv_vlsseg7e32_mu(v0, v1, v2, v3, v4, v5, v6, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, maskedoff4, maskedoff5, maskedoff6, base, bstride, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlsseg7e32_v_i32mf2_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], ptr noundef [[V4:%.*]], ptr noundef [[V5:%.*]], ptr noundef [[V6:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], [[MASKEDOFF4:%.*]], [[MASKEDOFF5:%.*]], [[MASKEDOFF6:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[BSTRIDE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vlsseg7.mask.nxv1i32.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], [[MASKEDOFF4]], [[MASKEDOFF5]], [[MASKEDOFF6]], ptr [[BASE]], i64 [[BSTRIDE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 4 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 4 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 4 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , } [[TMP0]], 4 +// CHECK-RV64-NEXT: store [[TMP5]], ptr [[V4]], align 4 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , } [[TMP0]], 5 +// CHECK-RV64-NEXT: store [[TMP6]], ptr [[V5]], align 4 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , } [[TMP0]], 6 +// CHECK-RV64-NEXT: store [[TMP7]], ptr [[V6]], align 4 +// CHECK-RV64-NEXT: ret void +// +void test_vlsseg7e32_v_i32mf2_mu(vint32mf2_t *v0, vint32mf2_t *v1, vint32mf2_t *v2, vint32mf2_t *v3, vint32mf2_t *v4, vint32mf2_t *v5, vint32mf2_t *v6, vbool64_t mask, vint32mf2_t maskedoff0, vint32mf2_t maskedoff1, vint32mf2_t maskedoff2, vint32mf2_t maskedoff3, vint32mf2_t maskedoff4, vint32mf2_t maskedoff5, vint32mf2_t maskedoff6, const int32_t *base, ptrdiff_t bstride, size_t vl) { + return __riscv_vlsseg7e32_mu(v0, v1, v2, v3, v4, v5, v6, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, maskedoff4, maskedoff5, maskedoff6, base, bstride, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlsseg7e32_v_i32m1_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], ptr noundef [[V4:%.*]], ptr noundef [[V5:%.*]], ptr noundef [[V6:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], [[MASKEDOFF4:%.*]], [[MASKEDOFF5:%.*]], [[MASKEDOFF6:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[BSTRIDE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vlsseg7.mask.nxv2i32.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], [[MASKEDOFF4]], [[MASKEDOFF5]], [[MASKEDOFF6]], ptr [[BASE]], i64 [[BSTRIDE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 4 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 4 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 4 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , } [[TMP0]], 4 +// CHECK-RV64-NEXT: store [[TMP5]], ptr [[V4]], align 4 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , } [[TMP0]], 5 +// CHECK-RV64-NEXT: store [[TMP6]], ptr [[V5]], align 4 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , } [[TMP0]], 6 +// CHECK-RV64-NEXT: store [[TMP7]], ptr [[V6]], align 4 +// CHECK-RV64-NEXT: ret void +// +void test_vlsseg7e32_v_i32m1_mu(vint32m1_t *v0, vint32m1_t *v1, vint32m1_t *v2, vint32m1_t *v3, vint32m1_t *v4, vint32m1_t *v5, vint32m1_t *v6, vbool32_t mask, vint32m1_t maskedoff0, vint32m1_t maskedoff1, vint32m1_t maskedoff2, vint32m1_t maskedoff3, vint32m1_t maskedoff4, vint32m1_t maskedoff5, vint32m1_t maskedoff6, const int32_t *base, ptrdiff_t bstride, size_t vl) { + return __riscv_vlsseg7e32_mu(v0, v1, v2, v3, v4, v5, v6, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, maskedoff4, maskedoff5, maskedoff6, base, bstride, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlsseg7e32_v_u32mf2_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], ptr noundef [[V4:%.*]], ptr noundef [[V5:%.*]], ptr noundef [[V6:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], [[MASKEDOFF4:%.*]], [[MASKEDOFF5:%.*]], [[MASKEDOFF6:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[BSTRIDE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vlsseg7.mask.nxv1i32.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], [[MASKEDOFF4]], [[MASKEDOFF5]], [[MASKEDOFF6]], ptr [[BASE]], i64 [[BSTRIDE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 4 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 4 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 4 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , } [[TMP0]], 4 +// CHECK-RV64-NEXT: store [[TMP5]], ptr [[V4]], align 4 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , } [[TMP0]], 5 +// CHECK-RV64-NEXT: store [[TMP6]], ptr [[V5]], align 4 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , } [[TMP0]], 6 +// CHECK-RV64-NEXT: store [[TMP7]], ptr [[V6]], align 4 +// CHECK-RV64-NEXT: ret void +// +void test_vlsseg7e32_v_u32mf2_mu(vuint32mf2_t *v0, vuint32mf2_t *v1, vuint32mf2_t *v2, vuint32mf2_t *v3, vuint32mf2_t *v4, vuint32mf2_t *v5, vuint32mf2_t *v6, vbool64_t mask, vuint32mf2_t maskedoff0, vuint32mf2_t maskedoff1, vuint32mf2_t maskedoff2, vuint32mf2_t maskedoff3, vuint32mf2_t maskedoff4, vuint32mf2_t maskedoff5, vuint32mf2_t maskedoff6, const uint32_t *base, ptrdiff_t bstride, size_t vl) { + return __riscv_vlsseg7e32_mu(v0, v1, v2, v3, v4, v5, v6, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, maskedoff4, maskedoff5, maskedoff6, base, bstride, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlsseg7e32_v_u32m1_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], ptr noundef [[V4:%.*]], ptr noundef [[V5:%.*]], ptr noundef [[V6:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], [[MASKEDOFF4:%.*]], [[MASKEDOFF5:%.*]], [[MASKEDOFF6:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[BSTRIDE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vlsseg7.mask.nxv2i32.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], [[MASKEDOFF4]], [[MASKEDOFF5]], [[MASKEDOFF6]], ptr [[BASE]], i64 [[BSTRIDE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 4 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 4 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 4 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , } [[TMP0]], 4 +// CHECK-RV64-NEXT: store [[TMP5]], ptr [[V4]], align 4 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , } [[TMP0]], 5 +// CHECK-RV64-NEXT: store [[TMP6]], ptr [[V5]], align 4 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , } [[TMP0]], 6 +// CHECK-RV64-NEXT: store [[TMP7]], ptr [[V6]], align 4 +// CHECK-RV64-NEXT: ret void +// +void test_vlsseg7e32_v_u32m1_mu(vuint32m1_t *v0, vuint32m1_t *v1, vuint32m1_t *v2, vuint32m1_t *v3, vuint32m1_t *v4, vuint32m1_t *v5, vuint32m1_t *v6, vbool32_t mask, vuint32m1_t maskedoff0, vuint32m1_t maskedoff1, vuint32m1_t maskedoff2, vuint32m1_t maskedoff3, vuint32m1_t maskedoff4, vuint32m1_t maskedoff5, vuint32m1_t maskedoff6, const uint32_t *base, ptrdiff_t bstride, size_t vl) { + return __riscv_vlsseg7e32_mu(v0, v1, v2, v3, v4, v5, v6, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, maskedoff4, maskedoff5, maskedoff6, base, bstride, vl); +} + diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg7e64.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg7e64.c index ebc5fdeb21679..160edc5c5160e 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg7e64.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg7e64.c @@ -223,3 +223,75 @@ void test_vlsseg7e64_v_u64m1_tumu(vuint64m1_t *v0, vuint64m1_t *v1, vuint64m1_t return __riscv_vlsseg7e64_tumu(v0, v1, v2, v3, v4, v5, v6, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, maskedoff4, maskedoff5, maskedoff6, base, bstride, vl); } +// CHECK-RV64-LABEL: define dso_local void @test_vlsseg7e64_v_f64m1_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], ptr noundef [[V4:%.*]], ptr noundef [[V5:%.*]], ptr noundef [[V6:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], [[MASKEDOFF4:%.*]], [[MASKEDOFF5:%.*]], [[MASKEDOFF6:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[BSTRIDE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vlsseg7.mask.nxv1f64.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], [[MASKEDOFF4]], [[MASKEDOFF5]], [[MASKEDOFF6]], ptr [[BASE]], i64 [[BSTRIDE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 8 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 8 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 8 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 8 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , } [[TMP0]], 4 +// CHECK-RV64-NEXT: store [[TMP5]], ptr [[V4]], align 8 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , } [[TMP0]], 5 +// CHECK-RV64-NEXT: store [[TMP6]], ptr [[V5]], align 8 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , } [[TMP0]], 6 +// CHECK-RV64-NEXT: store [[TMP7]], ptr [[V6]], align 8 +// CHECK-RV64-NEXT: ret void +// +void test_vlsseg7e64_v_f64m1_mu(vfloat64m1_t *v0, vfloat64m1_t *v1, vfloat64m1_t *v2, vfloat64m1_t *v3, vfloat64m1_t *v4, vfloat64m1_t *v5, vfloat64m1_t *v6, vbool64_t mask, vfloat64m1_t maskedoff0, vfloat64m1_t maskedoff1, vfloat64m1_t maskedoff2, vfloat64m1_t maskedoff3, vfloat64m1_t maskedoff4, vfloat64m1_t maskedoff5, vfloat64m1_t maskedoff6, const double *base, ptrdiff_t bstride, size_t vl) { + return __riscv_vlsseg7e64_mu(v0, v1, v2, v3, v4, v5, v6, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, maskedoff4, maskedoff5, maskedoff6, base, bstride, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlsseg7e64_v_i64m1_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], ptr noundef [[V4:%.*]], ptr noundef [[V5:%.*]], ptr noundef [[V6:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], [[MASKEDOFF4:%.*]], [[MASKEDOFF5:%.*]], [[MASKEDOFF6:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[BSTRIDE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vlsseg7.mask.nxv1i64.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], [[MASKEDOFF4]], [[MASKEDOFF5]], [[MASKEDOFF6]], ptr [[BASE]], i64 [[BSTRIDE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 8 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 8 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 8 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 8 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , } [[TMP0]], 4 +// CHECK-RV64-NEXT: store [[TMP5]], ptr [[V4]], align 8 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , } [[TMP0]], 5 +// CHECK-RV64-NEXT: store [[TMP6]], ptr [[V5]], align 8 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , } [[TMP0]], 6 +// CHECK-RV64-NEXT: store [[TMP7]], ptr [[V6]], align 8 +// CHECK-RV64-NEXT: ret void +// +void test_vlsseg7e64_v_i64m1_mu(vint64m1_t *v0, vint64m1_t *v1, vint64m1_t *v2, vint64m1_t *v3, vint64m1_t *v4, vint64m1_t *v5, vint64m1_t *v6, vbool64_t mask, vint64m1_t maskedoff0, vint64m1_t maskedoff1, vint64m1_t maskedoff2, vint64m1_t maskedoff3, vint64m1_t maskedoff4, vint64m1_t maskedoff5, vint64m1_t maskedoff6, const int64_t *base, ptrdiff_t bstride, size_t vl) { + return __riscv_vlsseg7e64_mu(v0, v1, v2, v3, v4, v5, v6, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, maskedoff4, maskedoff5, maskedoff6, base, bstride, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlsseg7e64_v_u64m1_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], ptr noundef [[V4:%.*]], ptr noundef [[V5:%.*]], ptr noundef [[V6:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], [[MASKEDOFF4:%.*]], [[MASKEDOFF5:%.*]], [[MASKEDOFF6:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[BSTRIDE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vlsseg7.mask.nxv1i64.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], [[MASKEDOFF4]], [[MASKEDOFF5]], [[MASKEDOFF6]], ptr [[BASE]], i64 [[BSTRIDE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 8 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 8 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 8 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 8 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , } [[TMP0]], 4 +// CHECK-RV64-NEXT: store [[TMP5]], ptr [[V4]], align 8 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , } [[TMP0]], 5 +// CHECK-RV64-NEXT: store [[TMP6]], ptr [[V5]], align 8 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , } [[TMP0]], 6 +// CHECK-RV64-NEXT: store [[TMP7]], ptr [[V6]], align 8 +// CHECK-RV64-NEXT: ret void +// +void test_vlsseg7e64_v_u64m1_mu(vuint64m1_t *v0, vuint64m1_t *v1, vuint64m1_t *v2, vuint64m1_t *v3, vuint64m1_t *v4, vuint64m1_t *v5, vuint64m1_t *v6, vbool64_t mask, vuint64m1_t maskedoff0, vuint64m1_t maskedoff1, vuint64m1_t maskedoff2, vuint64m1_t maskedoff3, vuint64m1_t maskedoff4, vuint64m1_t maskedoff5, vuint64m1_t maskedoff6, const uint64_t *base, ptrdiff_t bstride, size_t vl) { + return __riscv_vlsseg7e64_mu(v0, v1, v2, v3, v4, v5, v6, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, maskedoff4, maskedoff5, maskedoff6, base, bstride, vl); +} + diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg7e8.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg7e8.c index c7321893ec138..a14b5a59b90ff 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg7e8.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg7e8.c @@ -582,3 +582,195 @@ void test_vlsseg7e8_v_u8m1_tumu(vuint8m1_t *v0, vuint8m1_t *v1, vuint8m1_t *v2, return __riscv_vlsseg7e8_tumu(v0, v1, v2, v3, v4, v5, v6, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, maskedoff4, maskedoff5, maskedoff6, base, bstride, vl); } +// CHECK-RV64-LABEL: define dso_local void @test_vlsseg7e8_v_i8mf8_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], ptr noundef [[V4:%.*]], ptr noundef [[V5:%.*]], ptr noundef [[V6:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], [[MASKEDOFF4:%.*]], [[MASKEDOFF5:%.*]], [[MASKEDOFF6:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[BSTRIDE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vlsseg7.mask.nxv1i8.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], [[MASKEDOFF4]], [[MASKEDOFF5]], [[MASKEDOFF6]], ptr [[BASE]], i64 [[BSTRIDE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 1 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 1 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 1 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , } [[TMP0]], 4 +// CHECK-RV64-NEXT: store [[TMP5]], ptr [[V4]], align 1 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , } [[TMP0]], 5 +// CHECK-RV64-NEXT: store [[TMP6]], ptr [[V5]], align 1 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , } [[TMP0]], 6 +// CHECK-RV64-NEXT: store [[TMP7]], ptr [[V6]], align 1 +// CHECK-RV64-NEXT: ret void +// +void test_vlsseg7e8_v_i8mf8_mu(vint8mf8_t *v0, vint8mf8_t *v1, vint8mf8_t *v2, vint8mf8_t *v3, vint8mf8_t *v4, vint8mf8_t *v5, vint8mf8_t *v6, vbool64_t mask, vint8mf8_t maskedoff0, vint8mf8_t maskedoff1, vint8mf8_t maskedoff2, vint8mf8_t maskedoff3, vint8mf8_t maskedoff4, vint8mf8_t maskedoff5, vint8mf8_t maskedoff6, const int8_t *base, ptrdiff_t bstride, size_t vl) { + return __riscv_vlsseg7e8_mu(v0, v1, v2, v3, v4, v5, v6, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, maskedoff4, maskedoff5, maskedoff6, base, bstride, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlsseg7e8_v_i8mf4_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], ptr noundef [[V4:%.*]], ptr noundef [[V5:%.*]], ptr noundef [[V6:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], [[MASKEDOFF4:%.*]], [[MASKEDOFF5:%.*]], [[MASKEDOFF6:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[BSTRIDE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vlsseg7.mask.nxv2i8.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], [[MASKEDOFF4]], [[MASKEDOFF5]], [[MASKEDOFF6]], ptr [[BASE]], i64 [[BSTRIDE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 1 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 1 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 1 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , } [[TMP0]], 4 +// CHECK-RV64-NEXT: store [[TMP5]], ptr [[V4]], align 1 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , } [[TMP0]], 5 +// CHECK-RV64-NEXT: store [[TMP6]], ptr [[V5]], align 1 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , } [[TMP0]], 6 +// CHECK-RV64-NEXT: store [[TMP7]], ptr [[V6]], align 1 +// CHECK-RV64-NEXT: ret void +// +void test_vlsseg7e8_v_i8mf4_mu(vint8mf4_t *v0, vint8mf4_t *v1, vint8mf4_t *v2, vint8mf4_t *v3, vint8mf4_t *v4, vint8mf4_t *v5, vint8mf4_t *v6, vbool32_t mask, vint8mf4_t maskedoff0, vint8mf4_t maskedoff1, vint8mf4_t maskedoff2, vint8mf4_t maskedoff3, vint8mf4_t maskedoff4, vint8mf4_t maskedoff5, vint8mf4_t maskedoff6, const int8_t *base, ptrdiff_t bstride, size_t vl) { + return __riscv_vlsseg7e8_mu(v0, v1, v2, v3, v4, v5, v6, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, maskedoff4, maskedoff5, maskedoff6, base, bstride, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlsseg7e8_v_i8mf2_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], ptr noundef [[V4:%.*]], ptr noundef [[V5:%.*]], ptr noundef [[V6:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], [[MASKEDOFF4:%.*]], [[MASKEDOFF5:%.*]], [[MASKEDOFF6:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[BSTRIDE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vlsseg7.mask.nxv4i8.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], [[MASKEDOFF4]], [[MASKEDOFF5]], [[MASKEDOFF6]], ptr [[BASE]], i64 [[BSTRIDE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 1 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 1 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 1 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , } [[TMP0]], 4 +// CHECK-RV64-NEXT: store [[TMP5]], ptr [[V4]], align 1 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , } [[TMP0]], 5 +// CHECK-RV64-NEXT: store [[TMP6]], ptr [[V5]], align 1 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , } [[TMP0]], 6 +// CHECK-RV64-NEXT: store [[TMP7]], ptr [[V6]], align 1 +// CHECK-RV64-NEXT: ret void +// +void test_vlsseg7e8_v_i8mf2_mu(vint8mf2_t *v0, vint8mf2_t *v1, vint8mf2_t *v2, vint8mf2_t *v3, vint8mf2_t *v4, vint8mf2_t *v5, vint8mf2_t *v6, vbool16_t mask, vint8mf2_t maskedoff0, vint8mf2_t maskedoff1, vint8mf2_t maskedoff2, vint8mf2_t maskedoff3, vint8mf2_t maskedoff4, vint8mf2_t maskedoff5, vint8mf2_t maskedoff6, const int8_t *base, ptrdiff_t bstride, size_t vl) { + return __riscv_vlsseg7e8_mu(v0, v1, v2, v3, v4, v5, v6, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, maskedoff4, maskedoff5, maskedoff6, base, bstride, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlsseg7e8_v_i8m1_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], ptr noundef [[V4:%.*]], ptr noundef [[V5:%.*]], ptr noundef [[V6:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], [[MASKEDOFF4:%.*]], [[MASKEDOFF5:%.*]], [[MASKEDOFF6:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[BSTRIDE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vlsseg7.mask.nxv8i8.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], [[MASKEDOFF4]], [[MASKEDOFF5]], [[MASKEDOFF6]], ptr [[BASE]], i64 [[BSTRIDE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 1 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 1 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 1 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , } [[TMP0]], 4 +// CHECK-RV64-NEXT: store [[TMP5]], ptr [[V4]], align 1 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , } [[TMP0]], 5 +// CHECK-RV64-NEXT: store [[TMP6]], ptr [[V5]], align 1 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , } [[TMP0]], 6 +// CHECK-RV64-NEXT: store [[TMP7]], ptr [[V6]], align 1 +// CHECK-RV64-NEXT: ret void +// +void test_vlsseg7e8_v_i8m1_mu(vint8m1_t *v0, vint8m1_t *v1, vint8m1_t *v2, vint8m1_t *v3, vint8m1_t *v4, vint8m1_t *v5, vint8m1_t *v6, vbool8_t mask, vint8m1_t maskedoff0, vint8m1_t maskedoff1, vint8m1_t maskedoff2, vint8m1_t maskedoff3, vint8m1_t maskedoff4, vint8m1_t maskedoff5, vint8m1_t maskedoff6, const int8_t *base, ptrdiff_t bstride, size_t vl) { + return __riscv_vlsseg7e8_mu(v0, v1, v2, v3, v4, v5, v6, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, maskedoff4, maskedoff5, maskedoff6, base, bstride, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlsseg7e8_v_u8mf8_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], ptr noundef [[V4:%.*]], ptr noundef [[V5:%.*]], ptr noundef [[V6:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], [[MASKEDOFF4:%.*]], [[MASKEDOFF5:%.*]], [[MASKEDOFF6:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[BSTRIDE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vlsseg7.mask.nxv1i8.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], [[MASKEDOFF4]], [[MASKEDOFF5]], [[MASKEDOFF6]], ptr [[BASE]], i64 [[BSTRIDE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 1 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 1 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 1 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , } [[TMP0]], 4 +// CHECK-RV64-NEXT: store [[TMP5]], ptr [[V4]], align 1 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , } [[TMP0]], 5 +// CHECK-RV64-NEXT: store [[TMP6]], ptr [[V5]], align 1 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , } [[TMP0]], 6 +// CHECK-RV64-NEXT: store [[TMP7]], ptr [[V6]], align 1 +// CHECK-RV64-NEXT: ret void +// +void test_vlsseg7e8_v_u8mf8_mu(vuint8mf8_t *v0, vuint8mf8_t *v1, vuint8mf8_t *v2, vuint8mf8_t *v3, vuint8mf8_t *v4, vuint8mf8_t *v5, vuint8mf8_t *v6, vbool64_t mask, vuint8mf8_t maskedoff0, vuint8mf8_t maskedoff1, vuint8mf8_t maskedoff2, vuint8mf8_t maskedoff3, vuint8mf8_t maskedoff4, vuint8mf8_t maskedoff5, vuint8mf8_t maskedoff6, const uint8_t *base, ptrdiff_t bstride, size_t vl) { + return __riscv_vlsseg7e8_mu(v0, v1, v2, v3, v4, v5, v6, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, maskedoff4, maskedoff5, maskedoff6, base, bstride, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlsseg7e8_v_u8mf4_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], ptr noundef [[V4:%.*]], ptr noundef [[V5:%.*]], ptr noundef [[V6:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], [[MASKEDOFF4:%.*]], [[MASKEDOFF5:%.*]], [[MASKEDOFF6:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[BSTRIDE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vlsseg7.mask.nxv2i8.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], [[MASKEDOFF4]], [[MASKEDOFF5]], [[MASKEDOFF6]], ptr [[BASE]], i64 [[BSTRIDE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 1 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 1 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 1 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , } [[TMP0]], 4 +// CHECK-RV64-NEXT: store [[TMP5]], ptr [[V4]], align 1 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , } [[TMP0]], 5 +// CHECK-RV64-NEXT: store [[TMP6]], ptr [[V5]], align 1 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , } [[TMP0]], 6 +// CHECK-RV64-NEXT: store [[TMP7]], ptr [[V6]], align 1 +// CHECK-RV64-NEXT: ret void +// +void test_vlsseg7e8_v_u8mf4_mu(vuint8mf4_t *v0, vuint8mf4_t *v1, vuint8mf4_t *v2, vuint8mf4_t *v3, vuint8mf4_t *v4, vuint8mf4_t *v5, vuint8mf4_t *v6, vbool32_t mask, vuint8mf4_t maskedoff0, vuint8mf4_t maskedoff1, vuint8mf4_t maskedoff2, vuint8mf4_t maskedoff3, vuint8mf4_t maskedoff4, vuint8mf4_t maskedoff5, vuint8mf4_t maskedoff6, const uint8_t *base, ptrdiff_t bstride, size_t vl) { + return __riscv_vlsseg7e8_mu(v0, v1, v2, v3, v4, v5, v6, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, maskedoff4, maskedoff5, maskedoff6, base, bstride, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlsseg7e8_v_u8mf2_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], ptr noundef [[V4:%.*]], ptr noundef [[V5:%.*]], ptr noundef [[V6:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], [[MASKEDOFF4:%.*]], [[MASKEDOFF5:%.*]], [[MASKEDOFF6:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[BSTRIDE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vlsseg7.mask.nxv4i8.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], [[MASKEDOFF4]], [[MASKEDOFF5]], [[MASKEDOFF6]], ptr [[BASE]], i64 [[BSTRIDE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 1 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 1 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 1 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , } [[TMP0]], 4 +// CHECK-RV64-NEXT: store [[TMP5]], ptr [[V4]], align 1 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , } [[TMP0]], 5 +// CHECK-RV64-NEXT: store [[TMP6]], ptr [[V5]], align 1 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , } [[TMP0]], 6 +// CHECK-RV64-NEXT: store [[TMP7]], ptr [[V6]], align 1 +// CHECK-RV64-NEXT: ret void +// +void test_vlsseg7e8_v_u8mf2_mu(vuint8mf2_t *v0, vuint8mf2_t *v1, vuint8mf2_t *v2, vuint8mf2_t *v3, vuint8mf2_t *v4, vuint8mf2_t *v5, vuint8mf2_t *v6, vbool16_t mask, vuint8mf2_t maskedoff0, vuint8mf2_t maskedoff1, vuint8mf2_t maskedoff2, vuint8mf2_t maskedoff3, vuint8mf2_t maskedoff4, vuint8mf2_t maskedoff5, vuint8mf2_t maskedoff6, const uint8_t *base, ptrdiff_t bstride, size_t vl) { + return __riscv_vlsseg7e8_mu(v0, v1, v2, v3, v4, v5, v6, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, maskedoff4, maskedoff5, maskedoff6, base, bstride, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlsseg7e8_v_u8m1_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], ptr noundef [[V4:%.*]], ptr noundef [[V5:%.*]], ptr noundef [[V6:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], [[MASKEDOFF4:%.*]], [[MASKEDOFF5:%.*]], [[MASKEDOFF6:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[BSTRIDE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vlsseg7.mask.nxv8i8.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], [[MASKEDOFF4]], [[MASKEDOFF5]], [[MASKEDOFF6]], ptr [[BASE]], i64 [[BSTRIDE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 1 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 1 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 1 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , } [[TMP0]], 4 +// CHECK-RV64-NEXT: store [[TMP5]], ptr [[V4]], align 1 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , } [[TMP0]], 5 +// CHECK-RV64-NEXT: store [[TMP6]], ptr [[V5]], align 1 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , } [[TMP0]], 6 +// CHECK-RV64-NEXT: store [[TMP7]], ptr [[V6]], align 1 +// CHECK-RV64-NEXT: ret void +// +void test_vlsseg7e8_v_u8m1_mu(vuint8m1_t *v0, vuint8m1_t *v1, vuint8m1_t *v2, vuint8m1_t *v3, vuint8m1_t *v4, vuint8m1_t *v5, vuint8m1_t *v6, vbool8_t mask, vuint8m1_t maskedoff0, vuint8m1_t maskedoff1, vuint8m1_t maskedoff2, vuint8m1_t maskedoff3, vuint8m1_t maskedoff4, vuint8m1_t maskedoff5, vuint8m1_t maskedoff6, const uint8_t *base, ptrdiff_t bstride, size_t vl) { + return __riscv_vlsseg7e8_mu(v0, v1, v2, v3, v4, v5, v6, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, maskedoff4, maskedoff5, maskedoff6, base, bstride, vl); +} + diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg8e16.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg8e16.c index 99be0055cea2a..5c4485f2e0028 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg8e16.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg8e16.c @@ -709,3 +709,237 @@ void test_vlsseg8e16_v_u16m1_tumu(vuint16m1_t *v0, vuint16m1_t *v1, vuint16m1_t return __riscv_vlsseg8e16_tumu(v0, v1, v2, v3, v4, v5, v6, v7, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, maskedoff4, maskedoff5, maskedoff6, maskedoff7, base, bstride, vl); } +// CHECK-RV64-LABEL: define dso_local void @test_vlsseg8e16_v_f16mf4_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], ptr noundef [[V4:%.*]], ptr noundef [[V5:%.*]], ptr noundef [[V6:%.*]], ptr noundef [[V7:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], [[MASKEDOFF4:%.*]], [[MASKEDOFF5:%.*]], [[MASKEDOFF6:%.*]], [[MASKEDOFF7:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[BSTRIDE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vlsseg8.mask.nxv1f16.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], [[MASKEDOFF4]], [[MASKEDOFF5]], [[MASKEDOFF6]], [[MASKEDOFF7]], ptr [[BASE]], i64 [[BSTRIDE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 2 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 2 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 2 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 4 +// CHECK-RV64-NEXT: store [[TMP5]], ptr [[V4]], align 2 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 5 +// CHECK-RV64-NEXT: store [[TMP6]], ptr [[V5]], align 2 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 6 +// CHECK-RV64-NEXT: store [[TMP7]], ptr [[V6]], align 2 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 7 +// CHECK-RV64-NEXT: store [[TMP8]], ptr [[V7]], align 2 +// CHECK-RV64-NEXT: ret void +// +void test_vlsseg8e16_v_f16mf4_mu(vfloat16mf4_t *v0, vfloat16mf4_t *v1, vfloat16mf4_t *v2, vfloat16mf4_t *v3, vfloat16mf4_t *v4, vfloat16mf4_t *v5, vfloat16mf4_t *v6, vfloat16mf4_t *v7, vbool64_t mask, vfloat16mf4_t maskedoff0, vfloat16mf4_t maskedoff1, vfloat16mf4_t maskedoff2, vfloat16mf4_t maskedoff3, vfloat16mf4_t maskedoff4, vfloat16mf4_t maskedoff5, vfloat16mf4_t maskedoff6, vfloat16mf4_t maskedoff7, const _Float16 *base, ptrdiff_t bstride, size_t vl) { + return __riscv_vlsseg8e16_mu(v0, v1, v2, v3, v4, v5, v6, v7, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, maskedoff4, maskedoff5, maskedoff6, maskedoff7, base, bstride, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlsseg8e16_v_f16mf2_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], ptr noundef [[V4:%.*]], ptr noundef [[V5:%.*]], ptr noundef [[V6:%.*]], ptr noundef [[V7:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], [[MASKEDOFF4:%.*]], [[MASKEDOFF5:%.*]], [[MASKEDOFF6:%.*]], [[MASKEDOFF7:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[BSTRIDE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vlsseg8.mask.nxv2f16.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], [[MASKEDOFF4]], [[MASKEDOFF5]], [[MASKEDOFF6]], [[MASKEDOFF7]], ptr [[BASE]], i64 [[BSTRIDE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 2 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 2 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 2 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 4 +// CHECK-RV64-NEXT: store [[TMP5]], ptr [[V4]], align 2 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 5 +// CHECK-RV64-NEXT: store [[TMP6]], ptr [[V5]], align 2 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 6 +// CHECK-RV64-NEXT: store [[TMP7]], ptr [[V6]], align 2 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 7 +// CHECK-RV64-NEXT: store [[TMP8]], ptr [[V7]], align 2 +// CHECK-RV64-NEXT: ret void +// +void test_vlsseg8e16_v_f16mf2_mu(vfloat16mf2_t *v0, vfloat16mf2_t *v1, vfloat16mf2_t *v2, vfloat16mf2_t *v3, vfloat16mf2_t *v4, vfloat16mf2_t *v5, vfloat16mf2_t *v6, vfloat16mf2_t *v7, vbool32_t mask, vfloat16mf2_t maskedoff0, vfloat16mf2_t maskedoff1, vfloat16mf2_t maskedoff2, vfloat16mf2_t maskedoff3, vfloat16mf2_t maskedoff4, vfloat16mf2_t maskedoff5, vfloat16mf2_t maskedoff6, vfloat16mf2_t maskedoff7, const _Float16 *base, ptrdiff_t bstride, size_t vl) { + return __riscv_vlsseg8e16_mu(v0, v1, v2, v3, v4, v5, v6, v7, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, maskedoff4, maskedoff5, maskedoff6, maskedoff7, base, bstride, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlsseg8e16_v_f16m1_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], ptr noundef [[V4:%.*]], ptr noundef [[V5:%.*]], ptr noundef [[V6:%.*]], ptr noundef [[V7:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], [[MASKEDOFF4:%.*]], [[MASKEDOFF5:%.*]], [[MASKEDOFF6:%.*]], [[MASKEDOFF7:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[BSTRIDE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vlsseg8.mask.nxv4f16.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], [[MASKEDOFF4]], [[MASKEDOFF5]], [[MASKEDOFF6]], [[MASKEDOFF7]], ptr [[BASE]], i64 [[BSTRIDE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 2 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 2 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 2 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 4 +// CHECK-RV64-NEXT: store [[TMP5]], ptr [[V4]], align 2 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 5 +// CHECK-RV64-NEXT: store [[TMP6]], ptr [[V5]], align 2 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 6 +// CHECK-RV64-NEXT: store [[TMP7]], ptr [[V6]], align 2 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 7 +// CHECK-RV64-NEXT: store [[TMP8]], ptr [[V7]], align 2 +// CHECK-RV64-NEXT: ret void +// +void test_vlsseg8e16_v_f16m1_mu(vfloat16m1_t *v0, vfloat16m1_t *v1, vfloat16m1_t *v2, vfloat16m1_t *v3, vfloat16m1_t *v4, vfloat16m1_t *v5, vfloat16m1_t *v6, vfloat16m1_t *v7, vbool16_t mask, vfloat16m1_t maskedoff0, vfloat16m1_t maskedoff1, vfloat16m1_t maskedoff2, vfloat16m1_t maskedoff3, vfloat16m1_t maskedoff4, vfloat16m1_t maskedoff5, vfloat16m1_t maskedoff6, vfloat16m1_t maskedoff7, const _Float16 *base, ptrdiff_t bstride, size_t vl) { + return __riscv_vlsseg8e16_mu(v0, v1, v2, v3, v4, v5, v6, v7, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, maskedoff4, maskedoff5, maskedoff6, maskedoff7, base, bstride, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlsseg8e16_v_i16mf4_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], ptr noundef [[V4:%.*]], ptr noundef [[V5:%.*]], ptr noundef [[V6:%.*]], ptr noundef [[V7:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], [[MASKEDOFF4:%.*]], [[MASKEDOFF5:%.*]], [[MASKEDOFF6:%.*]], [[MASKEDOFF7:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[BSTRIDE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vlsseg8.mask.nxv1i16.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], [[MASKEDOFF4]], [[MASKEDOFF5]], [[MASKEDOFF6]], [[MASKEDOFF7]], ptr [[BASE]], i64 [[BSTRIDE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 2 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 2 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 2 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 4 +// CHECK-RV64-NEXT: store [[TMP5]], ptr [[V4]], align 2 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 5 +// CHECK-RV64-NEXT: store [[TMP6]], ptr [[V5]], align 2 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 6 +// CHECK-RV64-NEXT: store [[TMP7]], ptr [[V6]], align 2 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 7 +// CHECK-RV64-NEXT: store [[TMP8]], ptr [[V7]], align 2 +// CHECK-RV64-NEXT: ret void +// +void test_vlsseg8e16_v_i16mf4_mu(vint16mf4_t *v0, vint16mf4_t *v1, vint16mf4_t *v2, vint16mf4_t *v3, vint16mf4_t *v4, vint16mf4_t *v5, vint16mf4_t *v6, vint16mf4_t *v7, vbool64_t mask, vint16mf4_t maskedoff0, vint16mf4_t maskedoff1, vint16mf4_t maskedoff2, vint16mf4_t maskedoff3, vint16mf4_t maskedoff4, vint16mf4_t maskedoff5, vint16mf4_t maskedoff6, vint16mf4_t maskedoff7, const int16_t *base, ptrdiff_t bstride, size_t vl) { + return __riscv_vlsseg8e16_mu(v0, v1, v2, v3, v4, v5, v6, v7, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, maskedoff4, maskedoff5, maskedoff6, maskedoff7, base, bstride, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlsseg8e16_v_i16mf2_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], ptr noundef [[V4:%.*]], ptr noundef [[V5:%.*]], ptr noundef [[V6:%.*]], ptr noundef [[V7:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], [[MASKEDOFF4:%.*]], [[MASKEDOFF5:%.*]], [[MASKEDOFF6:%.*]], [[MASKEDOFF7:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[BSTRIDE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vlsseg8.mask.nxv2i16.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], [[MASKEDOFF4]], [[MASKEDOFF5]], [[MASKEDOFF6]], [[MASKEDOFF7]], ptr [[BASE]], i64 [[BSTRIDE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 2 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 2 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 2 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 4 +// CHECK-RV64-NEXT: store [[TMP5]], ptr [[V4]], align 2 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 5 +// CHECK-RV64-NEXT: store [[TMP6]], ptr [[V5]], align 2 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 6 +// CHECK-RV64-NEXT: store [[TMP7]], ptr [[V6]], align 2 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 7 +// CHECK-RV64-NEXT: store [[TMP8]], ptr [[V7]], align 2 +// CHECK-RV64-NEXT: ret void +// +void test_vlsseg8e16_v_i16mf2_mu(vint16mf2_t *v0, vint16mf2_t *v1, vint16mf2_t *v2, vint16mf2_t *v3, vint16mf2_t *v4, vint16mf2_t *v5, vint16mf2_t *v6, vint16mf2_t *v7, vbool32_t mask, vint16mf2_t maskedoff0, vint16mf2_t maskedoff1, vint16mf2_t maskedoff2, vint16mf2_t maskedoff3, vint16mf2_t maskedoff4, vint16mf2_t maskedoff5, vint16mf2_t maskedoff6, vint16mf2_t maskedoff7, const int16_t *base, ptrdiff_t bstride, size_t vl) { + return __riscv_vlsseg8e16_mu(v0, v1, v2, v3, v4, v5, v6, v7, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, maskedoff4, maskedoff5, maskedoff6, maskedoff7, base, bstride, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlsseg8e16_v_i16m1_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], ptr noundef [[V4:%.*]], ptr noundef [[V5:%.*]], ptr noundef [[V6:%.*]], ptr noundef [[V7:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], [[MASKEDOFF4:%.*]], [[MASKEDOFF5:%.*]], [[MASKEDOFF6:%.*]], [[MASKEDOFF7:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[BSTRIDE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vlsseg8.mask.nxv4i16.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], [[MASKEDOFF4]], [[MASKEDOFF5]], [[MASKEDOFF6]], [[MASKEDOFF7]], ptr [[BASE]], i64 [[BSTRIDE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 2 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 2 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 2 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 4 +// CHECK-RV64-NEXT: store [[TMP5]], ptr [[V4]], align 2 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 5 +// CHECK-RV64-NEXT: store [[TMP6]], ptr [[V5]], align 2 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 6 +// CHECK-RV64-NEXT: store [[TMP7]], ptr [[V6]], align 2 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 7 +// CHECK-RV64-NEXT: store [[TMP8]], ptr [[V7]], align 2 +// CHECK-RV64-NEXT: ret void +// +void test_vlsseg8e16_v_i16m1_mu(vint16m1_t *v0, vint16m1_t *v1, vint16m1_t *v2, vint16m1_t *v3, vint16m1_t *v4, vint16m1_t *v5, vint16m1_t *v6, vint16m1_t *v7, vbool16_t mask, vint16m1_t maskedoff0, vint16m1_t maskedoff1, vint16m1_t maskedoff2, vint16m1_t maskedoff3, vint16m1_t maskedoff4, vint16m1_t maskedoff5, vint16m1_t maskedoff6, vint16m1_t maskedoff7, const int16_t *base, ptrdiff_t bstride, size_t vl) { + return __riscv_vlsseg8e16_mu(v0, v1, v2, v3, v4, v5, v6, v7, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, maskedoff4, maskedoff5, maskedoff6, maskedoff7, base, bstride, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlsseg8e16_v_u16mf4_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], ptr noundef [[V4:%.*]], ptr noundef [[V5:%.*]], ptr noundef [[V6:%.*]], ptr noundef [[V7:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], [[MASKEDOFF4:%.*]], [[MASKEDOFF5:%.*]], [[MASKEDOFF6:%.*]], [[MASKEDOFF7:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[BSTRIDE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vlsseg8.mask.nxv1i16.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], [[MASKEDOFF4]], [[MASKEDOFF5]], [[MASKEDOFF6]], [[MASKEDOFF7]], ptr [[BASE]], i64 [[BSTRIDE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 2 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 2 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 2 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 4 +// CHECK-RV64-NEXT: store [[TMP5]], ptr [[V4]], align 2 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 5 +// CHECK-RV64-NEXT: store [[TMP6]], ptr [[V5]], align 2 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 6 +// CHECK-RV64-NEXT: store [[TMP7]], ptr [[V6]], align 2 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 7 +// CHECK-RV64-NEXT: store [[TMP8]], ptr [[V7]], align 2 +// CHECK-RV64-NEXT: ret void +// +void test_vlsseg8e16_v_u16mf4_mu(vuint16mf4_t *v0, vuint16mf4_t *v1, vuint16mf4_t *v2, vuint16mf4_t *v3, vuint16mf4_t *v4, vuint16mf4_t *v5, vuint16mf4_t *v6, vuint16mf4_t *v7, vbool64_t mask, vuint16mf4_t maskedoff0, vuint16mf4_t maskedoff1, vuint16mf4_t maskedoff2, vuint16mf4_t maskedoff3, vuint16mf4_t maskedoff4, vuint16mf4_t maskedoff5, vuint16mf4_t maskedoff6, vuint16mf4_t maskedoff7, const uint16_t *base, ptrdiff_t bstride, size_t vl) { + return __riscv_vlsseg8e16_mu(v0, v1, v2, v3, v4, v5, v6, v7, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, maskedoff4, maskedoff5, maskedoff6, maskedoff7, base, bstride, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlsseg8e16_v_u16mf2_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], ptr noundef [[V4:%.*]], ptr noundef [[V5:%.*]], ptr noundef [[V6:%.*]], ptr noundef [[V7:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], [[MASKEDOFF4:%.*]], [[MASKEDOFF5:%.*]], [[MASKEDOFF6:%.*]], [[MASKEDOFF7:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[BSTRIDE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vlsseg8.mask.nxv2i16.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], [[MASKEDOFF4]], [[MASKEDOFF5]], [[MASKEDOFF6]], [[MASKEDOFF7]], ptr [[BASE]], i64 [[BSTRIDE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 2 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 2 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 2 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 4 +// CHECK-RV64-NEXT: store [[TMP5]], ptr [[V4]], align 2 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 5 +// CHECK-RV64-NEXT: store [[TMP6]], ptr [[V5]], align 2 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 6 +// CHECK-RV64-NEXT: store [[TMP7]], ptr [[V6]], align 2 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 7 +// CHECK-RV64-NEXT: store [[TMP8]], ptr [[V7]], align 2 +// CHECK-RV64-NEXT: ret void +// +void test_vlsseg8e16_v_u16mf2_mu(vuint16mf2_t *v0, vuint16mf2_t *v1, vuint16mf2_t *v2, vuint16mf2_t *v3, vuint16mf2_t *v4, vuint16mf2_t *v5, vuint16mf2_t *v6, vuint16mf2_t *v7, vbool32_t mask, vuint16mf2_t maskedoff0, vuint16mf2_t maskedoff1, vuint16mf2_t maskedoff2, vuint16mf2_t maskedoff3, vuint16mf2_t maskedoff4, vuint16mf2_t maskedoff5, vuint16mf2_t maskedoff6, vuint16mf2_t maskedoff7, const uint16_t *base, ptrdiff_t bstride, size_t vl) { + return __riscv_vlsseg8e16_mu(v0, v1, v2, v3, v4, v5, v6, v7, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, maskedoff4, maskedoff5, maskedoff6, maskedoff7, base, bstride, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlsseg8e16_v_u16m1_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], ptr noundef [[V4:%.*]], ptr noundef [[V5:%.*]], ptr noundef [[V6:%.*]], ptr noundef [[V7:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], [[MASKEDOFF4:%.*]], [[MASKEDOFF5:%.*]], [[MASKEDOFF6:%.*]], [[MASKEDOFF7:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[BSTRIDE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vlsseg8.mask.nxv4i16.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], [[MASKEDOFF4]], [[MASKEDOFF5]], [[MASKEDOFF6]], [[MASKEDOFF7]], ptr [[BASE]], i64 [[BSTRIDE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 2 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 2 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 2 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 4 +// CHECK-RV64-NEXT: store [[TMP5]], ptr [[V4]], align 2 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 5 +// CHECK-RV64-NEXT: store [[TMP6]], ptr [[V5]], align 2 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 6 +// CHECK-RV64-NEXT: store [[TMP7]], ptr [[V6]], align 2 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 7 +// CHECK-RV64-NEXT: store [[TMP8]], ptr [[V7]], align 2 +// CHECK-RV64-NEXT: ret void +// +void test_vlsseg8e16_v_u16m1_mu(vuint16m1_t *v0, vuint16m1_t *v1, vuint16m1_t *v2, vuint16m1_t *v3, vuint16m1_t *v4, vuint16m1_t *v5, vuint16m1_t *v6, vuint16m1_t *v7, vbool16_t mask, vuint16m1_t maskedoff0, vuint16m1_t maskedoff1, vuint16m1_t maskedoff2, vuint16m1_t maskedoff3, vuint16m1_t maskedoff4, vuint16m1_t maskedoff5, vuint16m1_t maskedoff6, vuint16m1_t maskedoff7, const uint16_t *base, ptrdiff_t bstride, size_t vl) { + return __riscv_vlsseg8e16_mu(v0, v1, v2, v3, v4, v5, v6, v7, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, maskedoff4, maskedoff5, maskedoff6, maskedoff7, base, bstride, vl); +} + diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg8e32.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg8e32.c index bef2feb7f4f50..066e71ed19a49 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg8e32.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg8e32.c @@ -475,3 +475,159 @@ void test_vlsseg8e32_v_u32m1_tumu(vuint32m1_t *v0, vuint32m1_t *v1, vuint32m1_t return __riscv_vlsseg8e32_tumu(v0, v1, v2, v3, v4, v5, v6, v7, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, maskedoff4, maskedoff5, maskedoff6, maskedoff7, base, bstride, vl); } +// CHECK-RV64-LABEL: define dso_local void @test_vlsseg8e32_v_f32mf2_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], ptr noundef [[V4:%.*]], ptr noundef [[V5:%.*]], ptr noundef [[V6:%.*]], ptr noundef [[V7:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], [[MASKEDOFF4:%.*]], [[MASKEDOFF5:%.*]], [[MASKEDOFF6:%.*]], [[MASKEDOFF7:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[BSTRIDE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vlsseg8.mask.nxv1f32.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], [[MASKEDOFF4]], [[MASKEDOFF5]], [[MASKEDOFF6]], [[MASKEDOFF7]], ptr [[BASE]], i64 [[BSTRIDE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 4 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 4 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 4 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 4 +// CHECK-RV64-NEXT: store [[TMP5]], ptr [[V4]], align 4 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 5 +// CHECK-RV64-NEXT: store [[TMP6]], ptr [[V5]], align 4 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 6 +// CHECK-RV64-NEXT: store [[TMP7]], ptr [[V6]], align 4 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 7 +// CHECK-RV64-NEXT: store [[TMP8]], ptr [[V7]], align 4 +// CHECK-RV64-NEXT: ret void +// +void test_vlsseg8e32_v_f32mf2_mu(vfloat32mf2_t *v0, vfloat32mf2_t *v1, vfloat32mf2_t *v2, vfloat32mf2_t *v3, vfloat32mf2_t *v4, vfloat32mf2_t *v5, vfloat32mf2_t *v6, vfloat32mf2_t *v7, vbool64_t mask, vfloat32mf2_t maskedoff0, vfloat32mf2_t maskedoff1, vfloat32mf2_t maskedoff2, vfloat32mf2_t maskedoff3, vfloat32mf2_t maskedoff4, vfloat32mf2_t maskedoff5, vfloat32mf2_t maskedoff6, vfloat32mf2_t maskedoff7, const float *base, ptrdiff_t bstride, size_t vl) { + return __riscv_vlsseg8e32_mu(v0, v1, v2, v3, v4, v5, v6, v7, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, maskedoff4, maskedoff5, maskedoff6, maskedoff7, base, bstride, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlsseg8e32_v_f32m1_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], ptr noundef [[V4:%.*]], ptr noundef [[V5:%.*]], ptr noundef [[V6:%.*]], ptr noundef [[V7:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], [[MASKEDOFF4:%.*]], [[MASKEDOFF5:%.*]], [[MASKEDOFF6:%.*]], [[MASKEDOFF7:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[BSTRIDE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vlsseg8.mask.nxv2f32.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], [[MASKEDOFF4]], [[MASKEDOFF5]], [[MASKEDOFF6]], [[MASKEDOFF7]], ptr [[BASE]], i64 [[BSTRIDE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 4 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 4 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 4 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 4 +// CHECK-RV64-NEXT: store [[TMP5]], ptr [[V4]], align 4 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 5 +// CHECK-RV64-NEXT: store [[TMP6]], ptr [[V5]], align 4 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 6 +// CHECK-RV64-NEXT: store [[TMP7]], ptr [[V6]], align 4 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 7 +// CHECK-RV64-NEXT: store [[TMP8]], ptr [[V7]], align 4 +// CHECK-RV64-NEXT: ret void +// +void test_vlsseg8e32_v_f32m1_mu(vfloat32m1_t *v0, vfloat32m1_t *v1, vfloat32m1_t *v2, vfloat32m1_t *v3, vfloat32m1_t *v4, vfloat32m1_t *v5, vfloat32m1_t *v6, vfloat32m1_t *v7, vbool32_t mask, vfloat32m1_t maskedoff0, vfloat32m1_t maskedoff1, vfloat32m1_t maskedoff2, vfloat32m1_t maskedoff3, vfloat32m1_t maskedoff4, vfloat32m1_t maskedoff5, vfloat32m1_t maskedoff6, vfloat32m1_t maskedoff7, const float *base, ptrdiff_t bstride, size_t vl) { + return __riscv_vlsseg8e32_mu(v0, v1, v2, v3, v4, v5, v6, v7, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, maskedoff4, maskedoff5, maskedoff6, maskedoff7, base, bstride, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlsseg8e32_v_i32mf2_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], ptr noundef [[V4:%.*]], ptr noundef [[V5:%.*]], ptr noundef [[V6:%.*]], ptr noundef [[V7:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], [[MASKEDOFF4:%.*]], [[MASKEDOFF5:%.*]], [[MASKEDOFF6:%.*]], [[MASKEDOFF7:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[BSTRIDE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vlsseg8.mask.nxv1i32.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], [[MASKEDOFF4]], [[MASKEDOFF5]], [[MASKEDOFF6]], [[MASKEDOFF7]], ptr [[BASE]], i64 [[BSTRIDE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 4 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 4 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 4 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 4 +// CHECK-RV64-NEXT: store [[TMP5]], ptr [[V4]], align 4 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 5 +// CHECK-RV64-NEXT: store [[TMP6]], ptr [[V5]], align 4 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 6 +// CHECK-RV64-NEXT: store [[TMP7]], ptr [[V6]], align 4 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 7 +// CHECK-RV64-NEXT: store [[TMP8]], ptr [[V7]], align 4 +// CHECK-RV64-NEXT: ret void +// +void test_vlsseg8e32_v_i32mf2_mu(vint32mf2_t *v0, vint32mf2_t *v1, vint32mf2_t *v2, vint32mf2_t *v3, vint32mf2_t *v4, vint32mf2_t *v5, vint32mf2_t *v6, vint32mf2_t *v7, vbool64_t mask, vint32mf2_t maskedoff0, vint32mf2_t maskedoff1, vint32mf2_t maskedoff2, vint32mf2_t maskedoff3, vint32mf2_t maskedoff4, vint32mf2_t maskedoff5, vint32mf2_t maskedoff6, vint32mf2_t maskedoff7, const int32_t *base, ptrdiff_t bstride, size_t vl) { + return __riscv_vlsseg8e32_mu(v0, v1, v2, v3, v4, v5, v6, v7, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, maskedoff4, maskedoff5, maskedoff6, maskedoff7, base, bstride, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlsseg8e32_v_i32m1_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], ptr noundef [[V4:%.*]], ptr noundef [[V5:%.*]], ptr noundef [[V6:%.*]], ptr noundef [[V7:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], [[MASKEDOFF4:%.*]], [[MASKEDOFF5:%.*]], [[MASKEDOFF6:%.*]], [[MASKEDOFF7:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[BSTRIDE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vlsseg8.mask.nxv2i32.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], [[MASKEDOFF4]], [[MASKEDOFF5]], [[MASKEDOFF6]], [[MASKEDOFF7]], ptr [[BASE]], i64 [[BSTRIDE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 4 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 4 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 4 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 4 +// CHECK-RV64-NEXT: store [[TMP5]], ptr [[V4]], align 4 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 5 +// CHECK-RV64-NEXT: store [[TMP6]], ptr [[V5]], align 4 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 6 +// CHECK-RV64-NEXT: store [[TMP7]], ptr [[V6]], align 4 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 7 +// CHECK-RV64-NEXT: store [[TMP8]], ptr [[V7]], align 4 +// CHECK-RV64-NEXT: ret void +// +void test_vlsseg8e32_v_i32m1_mu(vint32m1_t *v0, vint32m1_t *v1, vint32m1_t *v2, vint32m1_t *v3, vint32m1_t *v4, vint32m1_t *v5, vint32m1_t *v6, vint32m1_t *v7, vbool32_t mask, vint32m1_t maskedoff0, vint32m1_t maskedoff1, vint32m1_t maskedoff2, vint32m1_t maskedoff3, vint32m1_t maskedoff4, vint32m1_t maskedoff5, vint32m1_t maskedoff6, vint32m1_t maskedoff7, const int32_t *base, ptrdiff_t bstride, size_t vl) { + return __riscv_vlsseg8e32_mu(v0, v1, v2, v3, v4, v5, v6, v7, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, maskedoff4, maskedoff5, maskedoff6, maskedoff7, base, bstride, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlsseg8e32_v_u32mf2_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], ptr noundef [[V4:%.*]], ptr noundef [[V5:%.*]], ptr noundef [[V6:%.*]], ptr noundef [[V7:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], [[MASKEDOFF4:%.*]], [[MASKEDOFF5:%.*]], [[MASKEDOFF6:%.*]], [[MASKEDOFF7:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[BSTRIDE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vlsseg8.mask.nxv1i32.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], [[MASKEDOFF4]], [[MASKEDOFF5]], [[MASKEDOFF6]], [[MASKEDOFF7]], ptr [[BASE]], i64 [[BSTRIDE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 4 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 4 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 4 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 4 +// CHECK-RV64-NEXT: store [[TMP5]], ptr [[V4]], align 4 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 5 +// CHECK-RV64-NEXT: store [[TMP6]], ptr [[V5]], align 4 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 6 +// CHECK-RV64-NEXT: store [[TMP7]], ptr [[V6]], align 4 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 7 +// CHECK-RV64-NEXT: store [[TMP8]], ptr [[V7]], align 4 +// CHECK-RV64-NEXT: ret void +// +void test_vlsseg8e32_v_u32mf2_mu(vuint32mf2_t *v0, vuint32mf2_t *v1, vuint32mf2_t *v2, vuint32mf2_t *v3, vuint32mf2_t *v4, vuint32mf2_t *v5, vuint32mf2_t *v6, vuint32mf2_t *v7, vbool64_t mask, vuint32mf2_t maskedoff0, vuint32mf2_t maskedoff1, vuint32mf2_t maskedoff2, vuint32mf2_t maskedoff3, vuint32mf2_t maskedoff4, vuint32mf2_t maskedoff5, vuint32mf2_t maskedoff6, vuint32mf2_t maskedoff7, const uint32_t *base, ptrdiff_t bstride, size_t vl) { + return __riscv_vlsseg8e32_mu(v0, v1, v2, v3, v4, v5, v6, v7, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, maskedoff4, maskedoff5, maskedoff6, maskedoff7, base, bstride, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlsseg8e32_v_u32m1_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], ptr noundef [[V4:%.*]], ptr noundef [[V5:%.*]], ptr noundef [[V6:%.*]], ptr noundef [[V7:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], [[MASKEDOFF4:%.*]], [[MASKEDOFF5:%.*]], [[MASKEDOFF6:%.*]], [[MASKEDOFF7:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[BSTRIDE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vlsseg8.mask.nxv2i32.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], [[MASKEDOFF4]], [[MASKEDOFF5]], [[MASKEDOFF6]], [[MASKEDOFF7]], ptr [[BASE]], i64 [[BSTRIDE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 4 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 4 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 4 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 4 +// CHECK-RV64-NEXT: store [[TMP5]], ptr [[V4]], align 4 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 5 +// CHECK-RV64-NEXT: store [[TMP6]], ptr [[V5]], align 4 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 6 +// CHECK-RV64-NEXT: store [[TMP7]], ptr [[V6]], align 4 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 7 +// CHECK-RV64-NEXT: store [[TMP8]], ptr [[V7]], align 4 +// CHECK-RV64-NEXT: ret void +// +void test_vlsseg8e32_v_u32m1_mu(vuint32m1_t *v0, vuint32m1_t *v1, vuint32m1_t *v2, vuint32m1_t *v3, vuint32m1_t *v4, vuint32m1_t *v5, vuint32m1_t *v6, vuint32m1_t *v7, vbool32_t mask, vuint32m1_t maskedoff0, vuint32m1_t maskedoff1, vuint32m1_t maskedoff2, vuint32m1_t maskedoff3, vuint32m1_t maskedoff4, vuint32m1_t maskedoff5, vuint32m1_t maskedoff6, vuint32m1_t maskedoff7, const uint32_t *base, ptrdiff_t bstride, size_t vl) { + return __riscv_vlsseg8e32_mu(v0, v1, v2, v3, v4, v5, v6, v7, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, maskedoff4, maskedoff5, maskedoff6, maskedoff7, base, bstride, vl); +} + diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg8e64.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg8e64.c index 2f10b10fc0853..33eb4a2a072a9 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg8e64.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg8e64.c @@ -241,3 +241,81 @@ void test_vlsseg8e64_v_u64m1_tumu(vuint64m1_t *v0, vuint64m1_t *v1, vuint64m1_t return __riscv_vlsseg8e64_tumu(v0, v1, v2, v3, v4, v5, v6, v7, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, maskedoff4, maskedoff5, maskedoff6, maskedoff7, base, bstride, vl); } +// CHECK-RV64-LABEL: define dso_local void @test_vlsseg8e64_v_f64m1_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], ptr noundef [[V4:%.*]], ptr noundef [[V5:%.*]], ptr noundef [[V6:%.*]], ptr noundef [[V7:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], [[MASKEDOFF4:%.*]], [[MASKEDOFF5:%.*]], [[MASKEDOFF6:%.*]], [[MASKEDOFF7:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[BSTRIDE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vlsseg8.mask.nxv1f64.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], [[MASKEDOFF4]], [[MASKEDOFF5]], [[MASKEDOFF6]], [[MASKEDOFF7]], ptr [[BASE]], i64 [[BSTRIDE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 8 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 8 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 8 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 8 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 4 +// CHECK-RV64-NEXT: store [[TMP5]], ptr [[V4]], align 8 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 5 +// CHECK-RV64-NEXT: store [[TMP6]], ptr [[V5]], align 8 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 6 +// CHECK-RV64-NEXT: store [[TMP7]], ptr [[V6]], align 8 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 7 +// CHECK-RV64-NEXT: store [[TMP8]], ptr [[V7]], align 8 +// CHECK-RV64-NEXT: ret void +// +void test_vlsseg8e64_v_f64m1_mu(vfloat64m1_t *v0, vfloat64m1_t *v1, vfloat64m1_t *v2, vfloat64m1_t *v3, vfloat64m1_t *v4, vfloat64m1_t *v5, vfloat64m1_t *v6, vfloat64m1_t *v7, vbool64_t mask, vfloat64m1_t maskedoff0, vfloat64m1_t maskedoff1, vfloat64m1_t maskedoff2, vfloat64m1_t maskedoff3, vfloat64m1_t maskedoff4, vfloat64m1_t maskedoff5, vfloat64m1_t maskedoff6, vfloat64m1_t maskedoff7, const double *base, ptrdiff_t bstride, size_t vl) { + return __riscv_vlsseg8e64_mu(v0, v1, v2, v3, v4, v5, v6, v7, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, maskedoff4, maskedoff5, maskedoff6, maskedoff7, base, bstride, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlsseg8e64_v_i64m1_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], ptr noundef [[V4:%.*]], ptr noundef [[V5:%.*]], ptr noundef [[V6:%.*]], ptr noundef [[V7:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], [[MASKEDOFF4:%.*]], [[MASKEDOFF5:%.*]], [[MASKEDOFF6:%.*]], [[MASKEDOFF7:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[BSTRIDE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vlsseg8.mask.nxv1i64.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], [[MASKEDOFF4]], [[MASKEDOFF5]], [[MASKEDOFF6]], [[MASKEDOFF7]], ptr [[BASE]], i64 [[BSTRIDE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 8 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 8 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 8 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 8 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 4 +// CHECK-RV64-NEXT: store [[TMP5]], ptr [[V4]], align 8 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 5 +// CHECK-RV64-NEXT: store [[TMP6]], ptr [[V5]], align 8 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 6 +// CHECK-RV64-NEXT: store [[TMP7]], ptr [[V6]], align 8 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 7 +// CHECK-RV64-NEXT: store [[TMP8]], ptr [[V7]], align 8 +// CHECK-RV64-NEXT: ret void +// +void test_vlsseg8e64_v_i64m1_mu(vint64m1_t *v0, vint64m1_t *v1, vint64m1_t *v2, vint64m1_t *v3, vint64m1_t *v4, vint64m1_t *v5, vint64m1_t *v6, vint64m1_t *v7, vbool64_t mask, vint64m1_t maskedoff0, vint64m1_t maskedoff1, vint64m1_t maskedoff2, vint64m1_t maskedoff3, vint64m1_t maskedoff4, vint64m1_t maskedoff5, vint64m1_t maskedoff6, vint64m1_t maskedoff7, const int64_t *base, ptrdiff_t bstride, size_t vl) { + return __riscv_vlsseg8e64_mu(v0, v1, v2, v3, v4, v5, v6, v7, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, maskedoff4, maskedoff5, maskedoff6, maskedoff7, base, bstride, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlsseg8e64_v_u64m1_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], ptr noundef [[V4:%.*]], ptr noundef [[V5:%.*]], ptr noundef [[V6:%.*]], ptr noundef [[V7:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], [[MASKEDOFF4:%.*]], [[MASKEDOFF5:%.*]], [[MASKEDOFF6:%.*]], [[MASKEDOFF7:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[BSTRIDE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vlsseg8.mask.nxv1i64.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], [[MASKEDOFF4]], [[MASKEDOFF5]], [[MASKEDOFF6]], [[MASKEDOFF7]], ptr [[BASE]], i64 [[BSTRIDE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 8 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 8 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 8 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 8 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 4 +// CHECK-RV64-NEXT: store [[TMP5]], ptr [[V4]], align 8 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 5 +// CHECK-RV64-NEXT: store [[TMP6]], ptr [[V5]], align 8 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 6 +// CHECK-RV64-NEXT: store [[TMP7]], ptr [[V6]], align 8 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 7 +// CHECK-RV64-NEXT: store [[TMP8]], ptr [[V7]], align 8 +// CHECK-RV64-NEXT: ret void +// +void test_vlsseg8e64_v_u64m1_mu(vuint64m1_t *v0, vuint64m1_t *v1, vuint64m1_t *v2, vuint64m1_t *v3, vuint64m1_t *v4, vuint64m1_t *v5, vuint64m1_t *v6, vuint64m1_t *v7, vbool64_t mask, vuint64m1_t maskedoff0, vuint64m1_t maskedoff1, vuint64m1_t maskedoff2, vuint64m1_t maskedoff3, vuint64m1_t maskedoff4, vuint64m1_t maskedoff5, vuint64m1_t maskedoff6, vuint64m1_t maskedoff7, const uint64_t *base, ptrdiff_t bstride, size_t vl) { + return __riscv_vlsseg8e64_mu(v0, v1, v2, v3, v4, v5, v6, v7, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, maskedoff4, maskedoff5, maskedoff6, maskedoff7, base, bstride, vl); +} + diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg8e8.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg8e8.c index d4ace1f8dcee3..25d501ded86b5 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg8e8.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg8e8.c @@ -630,3 +630,211 @@ void test_vlsseg8e8_v_u8m1_tumu(vuint8m1_t *v0, vuint8m1_t *v1, vuint8m1_t *v2, return __riscv_vlsseg8e8_tumu(v0, v1, v2, v3, v4, v5, v6, v7, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, maskedoff4, maskedoff5, maskedoff6, maskedoff7, base, bstride, vl); } +// CHECK-RV64-LABEL: define dso_local void @test_vlsseg8e8_v_i8mf8_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], ptr noundef [[V4:%.*]], ptr noundef [[V5:%.*]], ptr noundef [[V6:%.*]], ptr noundef [[V7:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], [[MASKEDOFF4:%.*]], [[MASKEDOFF5:%.*]], [[MASKEDOFF6:%.*]], [[MASKEDOFF7:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[BSTRIDE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vlsseg8.mask.nxv1i8.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], [[MASKEDOFF4]], [[MASKEDOFF5]], [[MASKEDOFF6]], [[MASKEDOFF7]], ptr [[BASE]], i64 [[BSTRIDE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 1 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 1 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 1 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 4 +// CHECK-RV64-NEXT: store [[TMP5]], ptr [[V4]], align 1 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 5 +// CHECK-RV64-NEXT: store [[TMP6]], ptr [[V5]], align 1 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 6 +// CHECK-RV64-NEXT: store [[TMP7]], ptr [[V6]], align 1 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 7 +// CHECK-RV64-NEXT: store [[TMP8]], ptr [[V7]], align 1 +// CHECK-RV64-NEXT: ret void +// +void test_vlsseg8e8_v_i8mf8_mu(vint8mf8_t *v0, vint8mf8_t *v1, vint8mf8_t *v2, vint8mf8_t *v3, vint8mf8_t *v4, vint8mf8_t *v5, vint8mf8_t *v6, vint8mf8_t *v7, vbool64_t mask, vint8mf8_t maskedoff0, vint8mf8_t maskedoff1, vint8mf8_t maskedoff2, vint8mf8_t maskedoff3, vint8mf8_t maskedoff4, vint8mf8_t maskedoff5, vint8mf8_t maskedoff6, vint8mf8_t maskedoff7, const int8_t *base, ptrdiff_t bstride, size_t vl) { + return __riscv_vlsseg8e8_mu(v0, v1, v2, v3, v4, v5, v6, v7, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, maskedoff4, maskedoff5, maskedoff6, maskedoff7, base, bstride, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlsseg8e8_v_i8mf4_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], ptr noundef [[V4:%.*]], ptr noundef [[V5:%.*]], ptr noundef [[V6:%.*]], ptr noundef [[V7:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], [[MASKEDOFF4:%.*]], [[MASKEDOFF5:%.*]], [[MASKEDOFF6:%.*]], [[MASKEDOFF7:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[BSTRIDE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vlsseg8.mask.nxv2i8.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], [[MASKEDOFF4]], [[MASKEDOFF5]], [[MASKEDOFF6]], [[MASKEDOFF7]], ptr [[BASE]], i64 [[BSTRIDE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 1 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 1 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 1 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 4 +// CHECK-RV64-NEXT: store [[TMP5]], ptr [[V4]], align 1 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 5 +// CHECK-RV64-NEXT: store [[TMP6]], ptr [[V5]], align 1 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 6 +// CHECK-RV64-NEXT: store [[TMP7]], ptr [[V6]], align 1 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 7 +// CHECK-RV64-NEXT: store [[TMP8]], ptr [[V7]], align 1 +// CHECK-RV64-NEXT: ret void +// +void test_vlsseg8e8_v_i8mf4_mu(vint8mf4_t *v0, vint8mf4_t *v1, vint8mf4_t *v2, vint8mf4_t *v3, vint8mf4_t *v4, vint8mf4_t *v5, vint8mf4_t *v6, vint8mf4_t *v7, vbool32_t mask, vint8mf4_t maskedoff0, vint8mf4_t maskedoff1, vint8mf4_t maskedoff2, vint8mf4_t maskedoff3, vint8mf4_t maskedoff4, vint8mf4_t maskedoff5, vint8mf4_t maskedoff6, vint8mf4_t maskedoff7, const int8_t *base, ptrdiff_t bstride, size_t vl) { + return __riscv_vlsseg8e8_mu(v0, v1, v2, v3, v4, v5, v6, v7, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, maskedoff4, maskedoff5, maskedoff6, maskedoff7, base, bstride, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlsseg8e8_v_i8mf2_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], ptr noundef [[V4:%.*]], ptr noundef [[V5:%.*]], ptr noundef [[V6:%.*]], ptr noundef [[V7:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], [[MASKEDOFF4:%.*]], [[MASKEDOFF5:%.*]], [[MASKEDOFF6:%.*]], [[MASKEDOFF7:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[BSTRIDE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vlsseg8.mask.nxv4i8.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], [[MASKEDOFF4]], [[MASKEDOFF5]], [[MASKEDOFF6]], [[MASKEDOFF7]], ptr [[BASE]], i64 [[BSTRIDE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 1 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 1 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 1 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 4 +// CHECK-RV64-NEXT: store [[TMP5]], ptr [[V4]], align 1 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 5 +// CHECK-RV64-NEXT: store [[TMP6]], ptr [[V5]], align 1 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 6 +// CHECK-RV64-NEXT: store [[TMP7]], ptr [[V6]], align 1 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 7 +// CHECK-RV64-NEXT: store [[TMP8]], ptr [[V7]], align 1 +// CHECK-RV64-NEXT: ret void +// +void test_vlsseg8e8_v_i8mf2_mu(vint8mf2_t *v0, vint8mf2_t *v1, vint8mf2_t *v2, vint8mf2_t *v3, vint8mf2_t *v4, vint8mf2_t *v5, vint8mf2_t *v6, vint8mf2_t *v7, vbool16_t mask, vint8mf2_t maskedoff0, vint8mf2_t maskedoff1, vint8mf2_t maskedoff2, vint8mf2_t maskedoff3, vint8mf2_t maskedoff4, vint8mf2_t maskedoff5, vint8mf2_t maskedoff6, vint8mf2_t maskedoff7, const int8_t *base, ptrdiff_t bstride, size_t vl) { + return __riscv_vlsseg8e8_mu(v0, v1, v2, v3, v4, v5, v6, v7, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, maskedoff4, maskedoff5, maskedoff6, maskedoff7, base, bstride, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlsseg8e8_v_i8m1_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], ptr noundef [[V4:%.*]], ptr noundef [[V5:%.*]], ptr noundef [[V6:%.*]], ptr noundef [[V7:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], [[MASKEDOFF4:%.*]], [[MASKEDOFF5:%.*]], [[MASKEDOFF6:%.*]], [[MASKEDOFF7:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[BSTRIDE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vlsseg8.mask.nxv8i8.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], [[MASKEDOFF4]], [[MASKEDOFF5]], [[MASKEDOFF6]], [[MASKEDOFF7]], ptr [[BASE]], i64 [[BSTRIDE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 1 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 1 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 1 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 4 +// CHECK-RV64-NEXT: store [[TMP5]], ptr [[V4]], align 1 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 5 +// CHECK-RV64-NEXT: store [[TMP6]], ptr [[V5]], align 1 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 6 +// CHECK-RV64-NEXT: store [[TMP7]], ptr [[V6]], align 1 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 7 +// CHECK-RV64-NEXT: store [[TMP8]], ptr [[V7]], align 1 +// CHECK-RV64-NEXT: ret void +// +void test_vlsseg8e8_v_i8m1_mu(vint8m1_t *v0, vint8m1_t *v1, vint8m1_t *v2, vint8m1_t *v3, vint8m1_t *v4, vint8m1_t *v5, vint8m1_t *v6, vint8m1_t *v7, vbool8_t mask, vint8m1_t maskedoff0, vint8m1_t maskedoff1, vint8m1_t maskedoff2, vint8m1_t maskedoff3, vint8m1_t maskedoff4, vint8m1_t maskedoff5, vint8m1_t maskedoff6, vint8m1_t maskedoff7, const int8_t *base, ptrdiff_t bstride, size_t vl) { + return __riscv_vlsseg8e8_mu(v0, v1, v2, v3, v4, v5, v6, v7, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, maskedoff4, maskedoff5, maskedoff6, maskedoff7, base, bstride, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlsseg8e8_v_u8mf8_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], ptr noundef [[V4:%.*]], ptr noundef [[V5:%.*]], ptr noundef [[V6:%.*]], ptr noundef [[V7:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], [[MASKEDOFF4:%.*]], [[MASKEDOFF5:%.*]], [[MASKEDOFF6:%.*]], [[MASKEDOFF7:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[BSTRIDE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vlsseg8.mask.nxv1i8.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], [[MASKEDOFF4]], [[MASKEDOFF5]], [[MASKEDOFF6]], [[MASKEDOFF7]], ptr [[BASE]], i64 [[BSTRIDE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 1 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 1 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 1 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 4 +// CHECK-RV64-NEXT: store [[TMP5]], ptr [[V4]], align 1 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 5 +// CHECK-RV64-NEXT: store [[TMP6]], ptr [[V5]], align 1 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 6 +// CHECK-RV64-NEXT: store [[TMP7]], ptr [[V6]], align 1 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 7 +// CHECK-RV64-NEXT: store [[TMP8]], ptr [[V7]], align 1 +// CHECK-RV64-NEXT: ret void +// +void test_vlsseg8e8_v_u8mf8_mu(vuint8mf8_t *v0, vuint8mf8_t *v1, vuint8mf8_t *v2, vuint8mf8_t *v3, vuint8mf8_t *v4, vuint8mf8_t *v5, vuint8mf8_t *v6, vuint8mf8_t *v7, vbool64_t mask, vuint8mf8_t maskedoff0, vuint8mf8_t maskedoff1, vuint8mf8_t maskedoff2, vuint8mf8_t maskedoff3, vuint8mf8_t maskedoff4, vuint8mf8_t maskedoff5, vuint8mf8_t maskedoff6, vuint8mf8_t maskedoff7, const uint8_t *base, ptrdiff_t bstride, size_t vl) { + return __riscv_vlsseg8e8_mu(v0, v1, v2, v3, v4, v5, v6, v7, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, maskedoff4, maskedoff5, maskedoff6, maskedoff7, base, bstride, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlsseg8e8_v_u8mf4_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], ptr noundef [[V4:%.*]], ptr noundef [[V5:%.*]], ptr noundef [[V6:%.*]], ptr noundef [[V7:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], [[MASKEDOFF4:%.*]], [[MASKEDOFF5:%.*]], [[MASKEDOFF6:%.*]], [[MASKEDOFF7:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[BSTRIDE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vlsseg8.mask.nxv2i8.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], [[MASKEDOFF4]], [[MASKEDOFF5]], [[MASKEDOFF6]], [[MASKEDOFF7]], ptr [[BASE]], i64 [[BSTRIDE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 1 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 1 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 1 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 4 +// CHECK-RV64-NEXT: store [[TMP5]], ptr [[V4]], align 1 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 5 +// CHECK-RV64-NEXT: store [[TMP6]], ptr [[V5]], align 1 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 6 +// CHECK-RV64-NEXT: store [[TMP7]], ptr [[V6]], align 1 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 7 +// CHECK-RV64-NEXT: store [[TMP8]], ptr [[V7]], align 1 +// CHECK-RV64-NEXT: ret void +// +void test_vlsseg8e8_v_u8mf4_mu(vuint8mf4_t *v0, vuint8mf4_t *v1, vuint8mf4_t *v2, vuint8mf4_t *v3, vuint8mf4_t *v4, vuint8mf4_t *v5, vuint8mf4_t *v6, vuint8mf4_t *v7, vbool32_t mask, vuint8mf4_t maskedoff0, vuint8mf4_t maskedoff1, vuint8mf4_t maskedoff2, vuint8mf4_t maskedoff3, vuint8mf4_t maskedoff4, vuint8mf4_t maskedoff5, vuint8mf4_t maskedoff6, vuint8mf4_t maskedoff7, const uint8_t *base, ptrdiff_t bstride, size_t vl) { + return __riscv_vlsseg8e8_mu(v0, v1, v2, v3, v4, v5, v6, v7, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, maskedoff4, maskedoff5, maskedoff6, maskedoff7, base, bstride, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlsseg8e8_v_u8mf2_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], ptr noundef [[V4:%.*]], ptr noundef [[V5:%.*]], ptr noundef [[V6:%.*]], ptr noundef [[V7:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], [[MASKEDOFF4:%.*]], [[MASKEDOFF5:%.*]], [[MASKEDOFF6:%.*]], [[MASKEDOFF7:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[BSTRIDE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vlsseg8.mask.nxv4i8.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], [[MASKEDOFF4]], [[MASKEDOFF5]], [[MASKEDOFF6]], [[MASKEDOFF7]], ptr [[BASE]], i64 [[BSTRIDE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 1 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 1 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 1 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 4 +// CHECK-RV64-NEXT: store [[TMP5]], ptr [[V4]], align 1 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 5 +// CHECK-RV64-NEXT: store [[TMP6]], ptr [[V5]], align 1 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 6 +// CHECK-RV64-NEXT: store [[TMP7]], ptr [[V6]], align 1 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 7 +// CHECK-RV64-NEXT: store [[TMP8]], ptr [[V7]], align 1 +// CHECK-RV64-NEXT: ret void +// +void test_vlsseg8e8_v_u8mf2_mu(vuint8mf2_t *v0, vuint8mf2_t *v1, vuint8mf2_t *v2, vuint8mf2_t *v3, vuint8mf2_t *v4, vuint8mf2_t *v5, vuint8mf2_t *v6, vuint8mf2_t *v7, vbool16_t mask, vuint8mf2_t maskedoff0, vuint8mf2_t maskedoff1, vuint8mf2_t maskedoff2, vuint8mf2_t maskedoff3, vuint8mf2_t maskedoff4, vuint8mf2_t maskedoff5, vuint8mf2_t maskedoff6, vuint8mf2_t maskedoff7, const uint8_t *base, ptrdiff_t bstride, size_t vl) { + return __riscv_vlsseg8e8_mu(v0, v1, v2, v3, v4, v5, v6, v7, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, maskedoff4, maskedoff5, maskedoff6, maskedoff7, base, bstride, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vlsseg8e8_v_u8m1_mu +// CHECK-RV64-SAME: (ptr noundef [[V0:%.*]], ptr noundef [[V1:%.*]], ptr noundef [[V2:%.*]], ptr noundef [[V3:%.*]], ptr noundef [[V4:%.*]], ptr noundef [[V5:%.*]], ptr noundef [[V6:%.*]], ptr noundef [[V7:%.*]], [[MASK:%.*]], [[MASKEDOFF0:%.*]], [[MASKEDOFF1:%.*]], [[MASKEDOFF2:%.*]], [[MASKEDOFF3:%.*]], [[MASKEDOFF4:%.*]], [[MASKEDOFF5:%.*]], [[MASKEDOFF6:%.*]], [[MASKEDOFF7:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[BSTRIDE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vlsseg8.mask.nxv8i8.i64( [[MASKEDOFF0]], [[MASKEDOFF1]], [[MASKEDOFF2]], [[MASKEDOFF3]], [[MASKEDOFF4]], [[MASKEDOFF5]], [[MASKEDOFF6]], [[MASKEDOFF7]], ptr [[BASE]], i64 [[BSTRIDE]], [[MASK]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 0 +// CHECK-RV64-NEXT: store [[TMP1]], ptr [[V0]], align 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 1 +// CHECK-RV64-NEXT: store [[TMP2]], ptr [[V1]], align 1 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 2 +// CHECK-RV64-NEXT: store [[TMP3]], ptr [[V2]], align 1 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 3 +// CHECK-RV64-NEXT: store [[TMP4]], ptr [[V3]], align 1 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 4 +// CHECK-RV64-NEXT: store [[TMP5]], ptr [[V4]], align 1 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 5 +// CHECK-RV64-NEXT: store [[TMP6]], ptr [[V5]], align 1 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 6 +// CHECK-RV64-NEXT: store [[TMP7]], ptr [[V6]], align 1 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = extractvalue { , , , , , , , } [[TMP0]], 7 +// CHECK-RV64-NEXT: store [[TMP8]], ptr [[V7]], align 1 +// CHECK-RV64-NEXT: ret void +// +void test_vlsseg8e8_v_u8m1_mu(vuint8m1_t *v0, vuint8m1_t *v1, vuint8m1_t *v2, vuint8m1_t *v3, vuint8m1_t *v4, vuint8m1_t *v5, vuint8m1_t *v6, vuint8m1_t *v7, vbool8_t mask, vuint8m1_t maskedoff0, vuint8m1_t maskedoff1, vuint8m1_t maskedoff2, vuint8m1_t maskedoff3, vuint8m1_t maskedoff4, vuint8m1_t maskedoff5, vuint8m1_t maskedoff6, vuint8m1_t maskedoff7, const uint8_t *base, ptrdiff_t bstride, size_t vl) { + return __riscv_vlsseg8e8_mu(v0, v1, v2, v3, v4, v5, v6, v7, mask, maskedoff0, maskedoff1, maskedoff2, maskedoff3, maskedoff4, maskedoff5, maskedoff6, maskedoff7, base, bstride, vl); +} + diff --git a/clang/test/CodeGen/aarch64-sve2p1-intrinsics/acle_sve2p1_ptrue.c b/clang/test/CodeGen/aarch64-sve2p1-intrinsics/acle_sve2p1_ptrue.c new file mode 100644 index 0000000000000..c8fd843500560 --- /dev/null +++ b/clang/test/CodeGen/aarch64-sve2p1-intrinsics/acle_sve2p1_ptrue.c @@ -0,0 +1,62 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py +// REQUIRES: aarch64-registered-target +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve2p1 -S -O1 -Werror -emit-llvm -o - %s | FileCheck %s +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve2p1 -S -O1 -Werror -emit-llvm -o - -x c++ %s | FileCheck %s -check-prefix=CPP-CHECK + +#include + +// CHECK-LABEL: @test_svptrue_c8( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = tail call target("aarch64.svcount") @llvm.aarch64.sve.ptrue.c8() +// CHECK-NEXT: ret target("aarch64.svcount") [[TMP0]] +// +// CPP-CHECK-LABEL: @_Z15test_svptrue_c8v( +// CPP-CHECK-NEXT: entry: +// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call target("aarch64.svcount") @llvm.aarch64.sve.ptrue.c8() +// CPP-CHECK-NEXT: ret target("aarch64.svcount") [[TMP0]] +// +svcount_t test_svptrue_c8(void) { + return svptrue_c8(); +} + +// CHECK-LABEL: @test_svptrue_c16( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = tail call target("aarch64.svcount") @llvm.aarch64.sve.ptrue.c16() +// CHECK-NEXT: ret target("aarch64.svcount") [[TMP0]] +// +// CPP-CHECK-LABEL: @_Z16test_svptrue_c16v( +// CPP-CHECK-NEXT: entry: +// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call target("aarch64.svcount") @llvm.aarch64.sve.ptrue.c16() +// CPP-CHECK-NEXT: ret target("aarch64.svcount") [[TMP0]] +// +svcount_t test_svptrue_c16(void) { + return svptrue_c16(); +} + +// CHECK-LABEL: @test_svptrue_c32( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = tail call target("aarch64.svcount") @llvm.aarch64.sve.ptrue.c32() +// CHECK-NEXT: ret target("aarch64.svcount") [[TMP0]] +// +// CPP-CHECK-LABEL: @_Z16test_svptrue_c32v( +// CPP-CHECK-NEXT: entry: +// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call target("aarch64.svcount") @llvm.aarch64.sve.ptrue.c32() +// CPP-CHECK-NEXT: ret target("aarch64.svcount") [[TMP0]] +// +svcount_t test_svptrue_c32(void) { + return svptrue_c32(); +} + +// CHECK-LABEL: @test_svptrue_c64( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = tail call target("aarch64.svcount") @llvm.aarch64.sve.ptrue.c64() +// CHECK-NEXT: ret target("aarch64.svcount") [[TMP0]] +// +// CPP-CHECK-LABEL: @_Z16test_svptrue_c64v( +// CPP-CHECK-NEXT: entry: +// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call target("aarch64.svcount") @llvm.aarch64.sve.ptrue.c64() +// CPP-CHECK-NEXT: ret target("aarch64.svcount") [[TMP0]] +// +svcount_t test_svptrue_c64(void) { + return svptrue_c64(); +} diff --git a/clang/test/CodeGen/arm_acle.c b/clang/test/CodeGen/arm_acle.c index d3ea9ded6583d..742570d32789d 100644 --- a/clang/test/CodeGen/arm_acle.c +++ b/clang/test/CodeGen/arm_acle.c @@ -145,7 +145,7 @@ void test_dbg(void) { // AArch32-NEXT: [[LDREX_I:%.*]] = call i32 @llvm.arm.ldrex.p0(ptr elementtype(i32) [[P:%.*]]) // AArch32-NEXT: [[STREX_I:%.*]] = call i32 @llvm.arm.strex.p0(i32 [[X:%.*]], ptr elementtype(i32) [[P]]) // AArch32-NEXT: [[TOBOOL_I:%.*]] = icmp ne i32 [[STREX_I]], 0 -// AArch32-NEXT: br i1 [[TOBOOL_I]], label [[DO_BODY_I]], label [[__SWP_EXIT:%.*]], !llvm.loop [[LOOP7:![0-9]+]] +// AArch32-NEXT: br i1 [[TOBOOL_I]], label [[DO_BODY_I]], label [[__SWP_EXIT:%.*]], !llvm.loop [[LOOP3:![0-9]+]] // AArch32: __swp.exit: // AArch32-NEXT: ret void // @@ -154,11 +154,11 @@ void test_dbg(void) { // AArch64-NEXT: br label [[DO_BODY_I:%.*]] // AArch64: do.body.i: // AArch64-NEXT: [[LDXR_I:%.*]] = call i64 @llvm.aarch64.ldxr.p0(ptr elementtype(i32) [[P:%.*]]) -// AArch64-NEXT: [[TMP1:%.*]] = trunc i64 [[LDXR_I]] to i32 -// AArch64-NEXT: [[TMP2:%.*]] = zext i32 [[X:%.*]] to i64 -// AArch64-NEXT: [[STXR_I:%.*]] = call i32 @llvm.aarch64.stxr.p0(i64 [[TMP2]], ptr elementtype(i32) [[P]]) +// AArch64-NEXT: [[TMP0:%.*]] = trunc i64 [[LDXR_I]] to i32 +// AArch64-NEXT: [[TMP1:%.*]] = zext i32 [[X:%.*]] to i64 +// AArch64-NEXT: [[STXR_I:%.*]] = call i32 @llvm.aarch64.stxr.p0(i64 [[TMP1]], ptr elementtype(i32) [[P]]) // AArch64-NEXT: [[TOBOOL_I:%.*]] = icmp ne i32 [[STXR_I]], 0 -// AArch64-NEXT: br i1 [[TOBOOL_I]], label [[DO_BODY_I]], label [[__SWP_EXIT:%.*]], !llvm.loop [[LOOP6:![0-9]+]] +// AArch64-NEXT: br i1 [[TOBOOL_I]], label [[DO_BODY_I]], label [[__SWP_EXIT:%.*]], !llvm.loop [[LOOP2:![0-9]+]] // AArch64: __swp.exit: // AArch64-NEXT: ret void // @@ -484,17 +484,17 @@ uint32_t test_rev16(uint32_t t) { // AArch64-NEXT: [[TMP0:%.*]] = call i32 @llvm.bswap.i32(i32 [[CONV_I]]) // AArch64-NEXT: [[REM_I_I10_I:%.*]] = urem i32 16, 32 // AArch64-NEXT: [[CMP_I_I11_I:%.*]] = icmp eq i32 [[REM_I_I10_I]], 0 -// AArch64-NEXT: br i1 [[CMP_I_I11_I]], label [[IF_THEN_I_I12_I:%.*]], label [[IF_END_I_I17_I:%.*]] -// AArch64: if.then.i.i12.i: +// AArch64-NEXT: br i1 [[CMP_I_I11_I]], label [[IF_THEN_I_I17_I:%.*]], label [[IF_END_I_I12_I:%.*]] +// AArch64: if.then.i.i17.i: // AArch64-NEXT: br label [[__REV16_EXIT18_I:%.*]] -// AArch64: if.end.i.i17.i: +// AArch64: if.end.i.i12.i: // AArch64-NEXT: [[SHR_I_I13_I:%.*]] = lshr i32 [[TMP0]], [[REM_I_I10_I]] // AArch64-NEXT: [[SUB_I_I14_I:%.*]] = sub i32 32, [[REM_I_I10_I]] // AArch64-NEXT: [[SHL_I_I15_I:%.*]] = shl i32 [[TMP0]], [[SUB_I_I14_I]] // AArch64-NEXT: [[OR_I_I16_I:%.*]] = or i32 [[SHR_I_I13_I]], [[SHL_I_I15_I]] // AArch64-NEXT: br label [[__REV16_EXIT18_I]] // AArch64: __rev16.exit18.i: -// AArch64-NEXT: [[RETVAL_I_I6_I_0:%.*]] = phi i32 [ [[TMP0]], [[IF_THEN_I_I12_I]] ], [ [[OR_I_I16_I]], [[IF_END_I_I17_I]] ] +// AArch64-NEXT: [[RETVAL_I_I6_I_0:%.*]] = phi i32 [ [[TMP0]], [[IF_THEN_I_I17_I]] ], [ [[OR_I_I16_I]], [[IF_END_I_I12_I]] ] // AArch64-NEXT: [[CONV1_I:%.*]] = zext i32 [[RETVAL_I_I6_I_0]] to i64 // AArch64-NEXT: [[SHL_I:%.*]] = shl i64 [[CONV1_I]], 32 // AArch64-NEXT: [[CONV2_I:%.*]] = trunc i64 [[T]] to i32 @@ -527,17 +527,17 @@ long test_rev16l(long t) { // ARM-NEXT: [[TMP0:%.*]] = call i32 @llvm.bswap.i32(i32 [[CONV_I]]) // ARM-NEXT: [[REM_I_I10_I:%.*]] = urem i32 16, 32 // ARM-NEXT: [[CMP_I_I11_I:%.*]] = icmp eq i32 [[REM_I_I10_I]], 0 -// ARM-NEXT: br i1 [[CMP_I_I11_I]], label [[IF_THEN_I_I12_I:%.*]], label [[IF_END_I_I17_I:%.*]] -// ARM: if.then.i.i12.i: +// ARM-NEXT: br i1 [[CMP_I_I11_I]], label [[IF_THEN_I_I17_I:%.*]], label [[IF_END_I_I12_I:%.*]] +// ARM: if.then.i.i17.i: // ARM-NEXT: br label [[__REV16_EXIT18_I:%.*]] -// ARM: if.end.i.i17.i: +// ARM: if.end.i.i12.i: // ARM-NEXT: [[SHR_I_I13_I:%.*]] = lshr i32 [[TMP0]], [[REM_I_I10_I]] // ARM-NEXT: [[SUB_I_I14_I:%.*]] = sub i32 32, [[REM_I_I10_I]] // ARM-NEXT: [[SHL_I_I15_I:%.*]] = shl i32 [[TMP0]], [[SUB_I_I14_I]] // ARM-NEXT: [[OR_I_I16_I:%.*]] = or i32 [[SHR_I_I13_I]], [[SHL_I_I15_I]] // ARM-NEXT: br label [[__REV16_EXIT18_I]] // ARM: __rev16.exit18.i: -// ARM-NEXT: [[RETVAL_I_I6_I_0:%.*]] = phi i32 [ [[TMP0]], [[IF_THEN_I_I12_I]] ], [ [[OR_I_I16_I]], [[IF_END_I_I17_I]] ] +// ARM-NEXT: [[RETVAL_I_I6_I_0:%.*]] = phi i32 [ [[TMP0]], [[IF_THEN_I_I17_I]] ], [ [[OR_I_I16_I]], [[IF_END_I_I12_I]] ] // ARM-NEXT: [[CONV1_I:%.*]] = zext i32 [[RETVAL_I_I6_I_0]] to i64 // ARM-NEXT: [[SHL_I:%.*]] = shl i64 [[CONV1_I]], 32 // ARM-NEXT: [[CONV2_I:%.*]] = trunc i64 [[T]] to i32 @@ -662,7 +662,7 @@ int32_t test_qsub(int32_t a, int32_t b) { extern int32_t f(); // AArch32-LABEL: @test_qdbl( // AArch32-NEXT: entry: -// AArch32-NEXT: [[CALL:%.*]] = call i32 @f() #[[ATTR7:[0-9]+]] +// AArch32-NEXT: [[CALL:%.*]] = call i32 @f() #[[ATTR9:[0-9]+]] // AArch32-NEXT: [[TMP0:%.*]] = call i32 @llvm.arm.qadd(i32 [[CALL]], i32 [[CALL]]) // AArch32-NEXT: ret i32 [[TMP0]] // @@ -1456,12 +1456,12 @@ uint32_t test_crc32cd(uint32_t a, uint64_t b) { /* 10.1 Special register intrinsics */ // AArch32-LABEL: @test_rsr( // AArch32-NEXT: entry: -// AArch32-NEXT: [[TMP0:%.*]] = call i32 @llvm.read_volatile_register.i32(metadata [[META9:![0-9]+]]) +// AArch32-NEXT: [[TMP0:%.*]] = call i32 @llvm.read_volatile_register.i32(metadata [[META5:![0-9]+]]) // AArch32-NEXT: ret i32 [[TMP0]] // // AArch64-LABEL: @test_rsr( // AArch64-NEXT: entry: -// AArch64-NEXT: [[TMP0:%.*]] = call i64 @llvm.read_volatile_register.i64(metadata [[META8:![0-9]+]]) +// AArch64-NEXT: [[TMP0:%.*]] = call i64 @llvm.read_volatile_register.i64(metadata [[META4:![0-9]+]]) // AArch64-NEXT: [[TMP1:%.*]] = trunc i64 [[TMP0]] to i32 // AArch64-NEXT: ret i32 [[TMP1]] // @@ -1475,12 +1475,12 @@ uint32_t test_rsr() { // AArch32-LABEL: @test_rsr64( // AArch32-NEXT: entry: -// AArch32-NEXT: [[TMP0:%.*]] = call i64 @llvm.read_volatile_register.i64(metadata [[META10:![0-9]+]]) +// AArch32-NEXT: [[TMP0:%.*]] = call i64 @llvm.read_volatile_register.i64(metadata [[META6:![0-9]+]]) // AArch32-NEXT: ret i64 [[TMP0]] // // AArch64-LABEL: @test_rsr64( // AArch64-NEXT: entry: -// AArch64-NEXT: [[TMP0:%.*]] = call i64 @llvm.read_volatile_register.i64(metadata [[META8]]) +// AArch64-NEXT: [[TMP0:%.*]] = call i64 @llvm.read_volatile_register.i64(metadata [[META4]]) // AArch64-NEXT: ret i64 [[TMP0]] // uint64_t test_rsr64() { @@ -1494,7 +1494,7 @@ uint64_t test_rsr64() { #ifdef __ARM_FEATURE_SYSREG128 // AArch6494D128-LABEL: @test_rsr128( // AArch6494D128-NEXT: entry: -// AArch6494D128-NEXT: [[TMP0:%.*]] = call i128 @llvm.read_volatile_register.i128(metadata [[META8]]) +// AArch6494D128-NEXT: [[TMP0:%.*]] = call i128 @llvm.read_volatile_register.i128(metadata [[META4]]) // AArch6494D128-NEXT: ret i128 [[TMP0]] // __uint128_t test_rsr128() { @@ -1504,13 +1504,13 @@ __uint128_t test_rsr128() { // AArch32-LABEL: @test_rsrp( // AArch32-NEXT: entry: -// AArch32-NEXT: [[TMP0:%.*]] = call i32 @llvm.read_volatile_register.i32(metadata [[META11:![0-9]+]]) +// AArch32-NEXT: [[TMP0:%.*]] = call i32 @llvm.read_volatile_register.i32(metadata [[META7:![0-9]+]]) // AArch32-NEXT: [[TMP1:%.*]] = inttoptr i32 [[TMP0]] to ptr // AArch32-NEXT: ret ptr [[TMP1]] // // AArch64-LABEL: @test_rsrp( // AArch64-NEXT: entry: -// AArch64-NEXT: [[TMP0:%.*]] = call i64 @llvm.read_volatile_register.i64(metadata [[META9:![0-9]+]]) +// AArch64-NEXT: [[TMP0:%.*]] = call i64 @llvm.read_volatile_register.i64(metadata [[META5:![0-9]+]]) // AArch64-NEXT: [[TMP1:%.*]] = inttoptr i64 [[TMP0]] to ptr // AArch64-NEXT: ret ptr [[TMP1]] // @@ -1520,13 +1520,13 @@ void *test_rsrp() { // AArch32-LABEL: @test_wsr( // AArch32-NEXT: entry: -// AArch32-NEXT: call void @llvm.write_register.i32(metadata [[META9]], i32 [[V:%.*]]) +// AArch32-NEXT: call void @llvm.write_register.i32(metadata [[META5]], i32 [[V:%.*]]) // AArch32-NEXT: ret void // // AArch64-LABEL: @test_wsr( // AArch64-NEXT: entry: // AArch64-NEXT: [[TMP0:%.*]] = zext i32 [[V:%.*]] to i64 -// AArch64-NEXT: call void @llvm.write_register.i64(metadata [[META8]], i64 [[TMP0]]) +// AArch64-NEXT: call void @llvm.write_register.i64(metadata [[META4]], i64 [[TMP0]]) // AArch64-NEXT: ret void // void test_wsr(uint32_t v) { @@ -1539,12 +1539,12 @@ void test_wsr(uint32_t v) { // AArch32-LABEL: @test_wsr64( // AArch32-NEXT: entry: -// AArch32-NEXT: call void @llvm.write_register.i64(metadata [[META10]], i64 [[V:%.*]]) +// AArch32-NEXT: call void @llvm.write_register.i64(metadata [[META6]], i64 [[V:%.*]]) // AArch32-NEXT: ret void // // AArch64-LABEL: @test_wsr64( // AArch64-NEXT: entry: -// AArch64-NEXT: call void @llvm.write_register.i64(metadata [[META8]], i64 [[V:%.*]]) +// AArch64-NEXT: call void @llvm.write_register.i64(metadata [[META4]], i64 [[V:%.*]]) // AArch64-NEXT: ret void // void test_wsr64(uint64_t v) { @@ -1558,7 +1558,7 @@ void test_wsr64(uint64_t v) { #ifdef __ARM_FEATURE_SYSREG128 // AArch6494D128-LABEL: @test_wsr128( // AArch6494D128-NEXT: entry: -// AArch6494D128-NEXT: call void @llvm.write_register.i128(metadata [[META8]], i128 [[V:%.*]]) +// AArch6494D128-NEXT: call void @llvm.write_register.i128(metadata [[META4]], i128 [[V:%.*]]) // AArch6494D128-NEXT: ret void // void test_wsr128(__uint128_t v) { @@ -1570,13 +1570,13 @@ void test_wsr128(__uint128_t v) { // AArch32-LABEL: @test_wsrp( // AArch32-NEXT: entry: // AArch32-NEXT: [[TMP0:%.*]] = ptrtoint ptr [[V:%.*]] to i32 -// AArch32-NEXT: call void @llvm.write_register.i32(metadata [[META11]], i32 [[TMP0]]) +// AArch32-NEXT: call void @llvm.write_register.i32(metadata [[META7]], i32 [[TMP0]]) // AArch32-NEXT: ret void // // AArch64-LABEL: @test_wsrp( // AArch64-NEXT: entry: // AArch64-NEXT: [[TMP0:%.*]] = ptrtoint ptr [[V:%.*]] to i64 -// AArch64-NEXT: call void @llvm.write_register.i64(metadata [[META9]], i64 [[TMP0]]) +// AArch64-NEXT: call void @llvm.write_register.i64(metadata [[META5]], i64 [[TMP0]]) // AArch64-NEXT: ret void // void test_wsrp(void *v) { @@ -1586,19 +1586,19 @@ void test_wsrp(void *v) { // AArch32-LABEL: @test_rsrf( // AArch32-NEXT: entry: // AArch32-NEXT: [[REF_TMP:%.*]] = alloca i32, align 4 -// AArch32-NEXT: [[TMP0:%.*]] = call i32 @llvm.read_volatile_register.i32(metadata [[META9]]) +// AArch32-NEXT: [[TMP0:%.*]] = call i32 @llvm.read_volatile_register.i32(metadata [[META5]]) // AArch32-NEXT: store i32 [[TMP0]], ptr [[REF_TMP]], align 4 -// AArch32-NEXT: [[TMP2:%.*]] = load float, ptr [[REF_TMP]], align 4 -// AArch32-NEXT: ret float [[TMP2]] +// AArch32-NEXT: [[TMP1:%.*]] = load float, ptr [[REF_TMP]], align 4 +// AArch32-NEXT: ret float [[TMP1]] // // AArch64-LABEL: @test_rsrf( // AArch64-NEXT: entry: // AArch64-NEXT: [[REF_TMP:%.*]] = alloca i32, align 4 -// AArch64-NEXT: [[TMP0:%.*]] = call i64 @llvm.read_volatile_register.i64(metadata [[META8]]) +// AArch64-NEXT: [[TMP0:%.*]] = call i64 @llvm.read_volatile_register.i64(metadata [[META4]]) // AArch64-NEXT: [[TMP1:%.*]] = trunc i64 [[TMP0]] to i32 // AArch64-NEXT: store i32 [[TMP1]], ptr [[REF_TMP]], align 4 -// AArch64-NEXT: [[TMP3:%.*]] = load float, ptr [[REF_TMP]], align 4 -// AArch64-NEXT: ret float [[TMP3]] +// AArch64-NEXT: [[TMP2:%.*]] = load float, ptr [[REF_TMP]], align 4 +// AArch64-NEXT: ret float [[TMP2]] // float test_rsrf() { #ifdef __ARM_32BIT_STATE @@ -1611,18 +1611,18 @@ float test_rsrf() { // AArch32-LABEL: @test_rsrf64( // AArch32-NEXT: entry: // AArch32-NEXT: [[REF_TMP:%.*]] = alloca i64, align 8 -// AArch32-NEXT: [[TMP0:%.*]] = call i64 @llvm.read_volatile_register.i64(metadata [[META10]]) +// AArch32-NEXT: [[TMP0:%.*]] = call i64 @llvm.read_volatile_register.i64(metadata [[META6]]) // AArch32-NEXT: store i64 [[TMP0]], ptr [[REF_TMP]], align 8 -// AArch32-NEXT: [[TMP2:%.*]] = load double, ptr [[REF_TMP]], align 8 -// AArch32-NEXT: ret double [[TMP2]] +// AArch32-NEXT: [[TMP1:%.*]] = load double, ptr [[REF_TMP]], align 8 +// AArch32-NEXT: ret double [[TMP1]] // // AArch64-LABEL: @test_rsrf64( // AArch64-NEXT: entry: // AArch64-NEXT: [[REF_TMP:%.*]] = alloca i64, align 8 -// AArch64-NEXT: [[TMP0:%.*]] = call i64 @llvm.read_volatile_register.i64(metadata [[META8]]) +// AArch64-NEXT: [[TMP0:%.*]] = call i64 @llvm.read_volatile_register.i64(metadata [[META4]]) // AArch64-NEXT: store i64 [[TMP0]], ptr [[REF_TMP]], align 8 -// AArch64-NEXT: [[TMP2:%.*]] = load double, ptr [[REF_TMP]], align 8 -// AArch64-NEXT: ret double [[TMP2]] +// AArch64-NEXT: [[TMP1:%.*]] = load double, ptr [[REF_TMP]], align 8 +// AArch64-NEXT: ret double [[TMP1]] // double test_rsrf64() { #ifdef __ARM_32BIT_STATE @@ -1636,17 +1636,17 @@ double test_rsrf64() { // AArch32-NEXT: entry: // AArch32-NEXT: [[V_ADDR:%.*]] = alloca float, align 4 // AArch32-NEXT: store float [[V:%.*]], ptr [[V_ADDR]], align 4 -// AArch32-NEXT: [[TMP1:%.*]] = load i32, ptr [[V_ADDR]], align 4 -// AArch32-NEXT: call void @llvm.write_register.i32(metadata [[META9]], i32 [[TMP1]]) +// AArch32-NEXT: [[TMP0:%.*]] = load i32, ptr [[V_ADDR]], align 4 +// AArch32-NEXT: call void @llvm.write_register.i32(metadata [[META5]], i32 [[TMP0]]) // AArch32-NEXT: ret void // // AArch64-LABEL: @test_wsrf( // AArch64-NEXT: entry: // AArch64-NEXT: [[V_ADDR:%.*]] = alloca float, align 4 // AArch64-NEXT: store float [[V:%.*]], ptr [[V_ADDR]], align 4 -// AArch64-NEXT: [[TMP1:%.*]] = load i32, ptr [[V_ADDR]], align 4 -// AArch64-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64 -// AArch64-NEXT: call void @llvm.write_register.i64(metadata [[META8]], i64 [[TMP2]]) +// AArch64-NEXT: [[TMP0:%.*]] = load i32, ptr [[V_ADDR]], align 4 +// AArch64-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 +// AArch64-NEXT: call void @llvm.write_register.i64(metadata [[META4]], i64 [[TMP1]]) // AArch64-NEXT: ret void // void test_wsrf(float v) { @@ -1661,16 +1661,16 @@ void test_wsrf(float v) { // AArch32-NEXT: entry: // AArch32-NEXT: [[V_ADDR:%.*]] = alloca double, align 8 // AArch32-NEXT: store double [[V:%.*]], ptr [[V_ADDR]], align 8 -// AArch32-NEXT: [[TMP1:%.*]] = load i64, ptr [[V_ADDR]], align 8 -// AArch32-NEXT: call void @llvm.write_register.i64(metadata [[META10]], i64 [[TMP1]]) +// AArch32-NEXT: [[TMP0:%.*]] = load i64, ptr [[V_ADDR]], align 8 +// AArch32-NEXT: call void @llvm.write_register.i64(metadata [[META6]], i64 [[TMP0]]) // AArch32-NEXT: ret void // // AArch64-LABEL: @test_wsrf64( // AArch64-NEXT: entry: // AArch64-NEXT: [[V_ADDR:%.*]] = alloca double, align 8 // AArch64-NEXT: store double [[V:%.*]], ptr [[V_ADDR]], align 8 -// AArch64-NEXT: [[TMP1:%.*]] = load i64, ptr [[V_ADDR]], align 8 -// AArch64-NEXT: call void @llvm.write_register.i64(metadata [[META8]], i64 [[TMP1]]) +// AArch64-NEXT: [[TMP0:%.*]] = load i64, ptr [[V_ADDR]], align 8 +// AArch64-NEXT: call void @llvm.write_register.i64(metadata [[META4]], i64 [[TMP0]]) // AArch64-NEXT: ret void // void test_wsrf64(double v) { diff --git a/clang/test/CodeGen/builtins-nvptx.c b/clang/test/CodeGen/builtins-nvptx.c index df8085bd2559b..75cb6835049c6 100644 --- a/clang/test/CodeGen/builtins-nvptx.c +++ b/clang/test/CodeGen/builtins-nvptx.c @@ -554,10 +554,12 @@ __device__ void nvvm_atom(float *fp, float f, double *dfp, double df, int *ip, // CHECK-LABEL: nvvm_ldg __device__ void nvvm_ldg(const void *p) { + // CHECK: call i8 @llvm.nvvm.ldg.global.i.i8.p0(ptr {{%[0-9]+}}, i32 1) // CHECK: call i8 @llvm.nvvm.ldg.global.i.i8.p0(ptr {{%[0-9]+}}, i32 1) // CHECK: call i8 @llvm.nvvm.ldg.global.i.i8.p0(ptr {{%[0-9]+}}, i32 1) __nvvm_ldg_c((const char *)p); __nvvm_ldg_uc((const unsigned char *)p); + __nvvm_ldg_sc((const signed char *)p); // CHECK: call i16 @llvm.nvvm.ldg.global.i.i16.p0(ptr {{%[0-9]+}}, i32 2) // CHECK: call i16 @llvm.nvvm.ldg.global.i.i16.p0(ptr {{%[0-9]+}}, i32 2) @@ -590,19 +592,25 @@ __device__ void nvvm_ldg(const void *p) { // elements, its alignment is set to number of elements times the alignment of // its member: n*alignof(t)." + // CHECK: call <2 x i8> @llvm.nvvm.ldg.global.i.v2i8.p0(ptr {{%[0-9]+}}, i32 2) // CHECK: call <2 x i8> @llvm.nvvm.ldg.global.i.v2i8.p0(ptr {{%[0-9]+}}, i32 2) // CHECK: call <2 x i8> @llvm.nvvm.ldg.global.i.v2i8.p0(ptr {{%[0-9]+}}, i32 2) typedef char char2 __attribute__((ext_vector_type(2))); typedef unsigned char uchar2 __attribute__((ext_vector_type(2))); + typedef signed char schar2 __attribute__((ext_vector_type(2))); __nvvm_ldg_c2((const char2 *)p); __nvvm_ldg_uc2((const uchar2 *)p); + __nvvm_ldg_sc2((const schar2 *)p); + // CHECK: call <4 x i8> @llvm.nvvm.ldg.global.i.v4i8.p0(ptr {{%[0-9]+}}, i32 4) // CHECK: call <4 x i8> @llvm.nvvm.ldg.global.i.v4i8.p0(ptr {{%[0-9]+}}, i32 4) // CHECK: call <4 x i8> @llvm.nvvm.ldg.global.i.v4i8.p0(ptr {{%[0-9]+}}, i32 4) typedef char char4 __attribute__((ext_vector_type(4))); typedef unsigned char uchar4 __attribute__((ext_vector_type(4))); + typedef signed char schar4 __attribute__((ext_vector_type(4))); __nvvm_ldg_c4((const char4 *)p); __nvvm_ldg_uc4((const uchar4 *)p); + __nvvm_ldg_sc4((const schar4 *)p); // CHECK: call <2 x i16> @llvm.nvvm.ldg.global.i.v2i16.p0(ptr {{%[0-9]+}}, i32 4) // CHECK: call <2 x i16> @llvm.nvvm.ldg.global.i.v2i16.p0(ptr {{%[0-9]+}}, i32 4) @@ -632,6 +640,15 @@ __device__ void nvvm_ldg(const void *p) { __nvvm_ldg_i4((const int4 *)p); __nvvm_ldg_ui4((const uint4 *)p); + // LP32: call <2 x i32> @llvm.nvvm.ldg.global.i.v2i32.p0(ptr {{%[0-9]+}}, i32 8) + // LP32: call <2 x i32> @llvm.nvvm.ldg.global.i.v2i32.p0(ptr {{%[0-9]+}}, i32 8) + // LP64: call <2 x i64> @llvm.nvvm.ldg.global.i.v2i64.p0(ptr {{%[0-9]+}}, i32 16) + // LP64: call <2 x i64> @llvm.nvvm.ldg.global.i.v2i64.p0(ptr {{%[0-9]+}}, i32 16) + typedef long long2 __attribute__((ext_vector_type(2))); + typedef unsigned long ulong2 __attribute__((ext_vector_type(2))); + __nvvm_ldg_l2((const long2 *)p); + __nvvm_ldg_ul2((const ulong2 *)p); + // CHECK: call <2 x i64> @llvm.nvvm.ldg.global.i.v2i64.p0(ptr {{%[0-9]+}}, i32 16) // CHECK: call <2 x i64> @llvm.nvvm.ldg.global.i.v2i64.p0(ptr {{%[0-9]+}}, i32 16) typedef long long longlong2 __attribute__((ext_vector_type(2))); @@ -654,10 +671,12 @@ __device__ void nvvm_ldg(const void *p) { // CHECK-LABEL: nvvm_ldu __device__ void nvvm_ldu(const void *p) { + // CHECK: call i8 @llvm.nvvm.ldu.global.i.i8.p0(ptr {{%[0-9]+}}, i32 1) // CHECK: call i8 @llvm.nvvm.ldu.global.i.i8.p0(ptr {{%[0-9]+}}, i32 1) // CHECK: call i8 @llvm.nvvm.ldu.global.i.i8.p0(ptr {{%[0-9]+}}, i32 1) __nvvm_ldu_c((const char *)p); __nvvm_ldu_uc((const unsigned char *)p); + __nvvm_ldu_sc((const signed char *)p); // CHECK: call i16 @llvm.nvvm.ldu.global.i.i16.p0(ptr {{%[0-9]+}}, i32 2) // CHECK: call i16 @llvm.nvvm.ldu.global.i.i16.p0(ptr {{%[0-9]+}}, i32 2) @@ -681,19 +700,25 @@ __device__ void nvvm_ldu(const void *p) { // CHECK: call double @llvm.nvvm.ldu.global.f.f64.p0(ptr {{%[0-9]+}}, i32 8) __nvvm_ldu_d((const double *)p); + // CHECK: call <2 x i8> @llvm.nvvm.ldu.global.i.v2i8.p0(ptr {{%[0-9]+}}, i32 2) // CHECK: call <2 x i8> @llvm.nvvm.ldu.global.i.v2i8.p0(ptr {{%[0-9]+}}, i32 2) // CHECK: call <2 x i8> @llvm.nvvm.ldu.global.i.v2i8.p0(ptr {{%[0-9]+}}, i32 2) typedef char char2 __attribute__((ext_vector_type(2))); typedef unsigned char uchar2 __attribute__((ext_vector_type(2))); + typedef signed char schar2 __attribute__((ext_vector_type(2))); __nvvm_ldu_c2((const char2 *)p); __nvvm_ldu_uc2((const uchar2 *)p); + __nvvm_ldu_sc2((const schar2 *)p); + // CHECK: call <4 x i8> @llvm.nvvm.ldu.global.i.v4i8.p0(ptr {{%[0-9]+}}, i32 4) // CHECK: call <4 x i8> @llvm.nvvm.ldu.global.i.v4i8.p0(ptr {{%[0-9]+}}, i32 4) // CHECK: call <4 x i8> @llvm.nvvm.ldu.global.i.v4i8.p0(ptr {{%[0-9]+}}, i32 4) typedef char char4 __attribute__((ext_vector_type(4))); typedef unsigned char uchar4 __attribute__((ext_vector_type(4))); + typedef signed char schar4 __attribute__((ext_vector_type(4))); __nvvm_ldu_c4((const char4 *)p); __nvvm_ldu_uc4((const uchar4 *)p); + __nvvm_ldu_sc4((const schar4 *)p); // CHECK: call <2 x i16> @llvm.nvvm.ldu.global.i.v2i16.p0(ptr {{%[0-9]+}}, i32 4) // CHECK: call <2 x i16> @llvm.nvvm.ldu.global.i.v2i16.p0(ptr {{%[0-9]+}}, i32 4) @@ -723,6 +748,15 @@ __device__ void nvvm_ldu(const void *p) { __nvvm_ldu_i4((const int4 *)p); __nvvm_ldu_ui4((const uint4 *)p); + // LP32: call <2 x i32> @llvm.nvvm.ldu.global.i.v2i32.p0(ptr {{%[0-9]+}}, i32 8) + // LP32: call <2 x i32> @llvm.nvvm.ldu.global.i.v2i32.p0(ptr {{%[0-9]+}}, i32 8) + // LP64: call <2 x i64> @llvm.nvvm.ldu.global.i.v2i64.p0(ptr {{%[0-9]+}}, i32 16) + // LP64: call <2 x i64> @llvm.nvvm.ldu.global.i.v2i64.p0(ptr {{%[0-9]+}}, i32 16) + typedef long long2 __attribute__((ext_vector_type(2))); + typedef unsigned long ulong2 __attribute__((ext_vector_type(2))); + __nvvm_ldu_l2((const long2 *)p); + __nvvm_ldu_ul2((const ulong2 *)p); + // CHECK: call <2 x i64> @llvm.nvvm.ldu.global.i.v2i64.p0(ptr {{%[0-9]+}}, i32 16) // CHECK: call <2 x i64> @llvm.nvvm.ldu.global.i.v2i64.p0(ptr {{%[0-9]+}}, i32 16) typedef long long longlong2 __attribute__((ext_vector_type(2))); diff --git a/clang/test/CodeGen/mdefault-visibility-export-mapping.c b/clang/test/CodeGen/mdefault-visibility-export-mapping.c index 18c6302d9f655..7f39050907fff 100644 --- a/clang/test/CodeGen/mdefault-visibility-export-mapping.c +++ b/clang/test/CodeGen/mdefault-visibility-export-mapping.c @@ -9,10 +9,6 @@ // RUN: %clang -target powerpc-ibm-aix %s -mdefault-visibility-export-mapping=all -fvisibility=hidden -S -emit-llvm -o - | \ // RUN: FileCheck -check-prefixes=UNSPECIFIED-HID,EXPLICIT-EXP %s -// RUN: not %clang -mdefault-visibility-export-mapping=explicit -target powerpc-unknown-linux %s 2>&1 | \ -// RUN: FileCheck -check-prefix=ERROR %s -// ERROR: unsupported option '-mdefault-visibility-export-mapping=explicit' for target 'powerpc-unknown-linux' - // UNSPECIFIED-DEF: define void @func() // UNSPECIFIED-HID: define hidden void @func() // UNSPECIFIED-EXP: define dllexport void @func() diff --git a/clang/test/CodeGen/memcpy-inline-builtin-mutliple-decl.c b/clang/test/CodeGen/memcpy-inline-builtin-mutliple-decl.c new file mode 100644 index 0000000000000..39a964c51c7d2 --- /dev/null +++ b/clang/test/CodeGen/memcpy-inline-builtin-mutliple-decl.c @@ -0,0 +1,29 @@ +// RUN: %clang_cc1 -triple i686-w64-mingw32 -S -emit-llvm -disable-llvm-passes -o - %s | FileCheck %s +// +// Verifies that clang detects memcpy inline version and uses it instead of the builtin. +// Checks that clang correctly walks through multiple forward declaration. + +typedef unsigned int size_t; + +void *memcpy(void *_Dst, const void *_Src, size_t _Size); + +extern __inline__ __attribute__((__always_inline__, __gnu_inline__)) __attribute__((__artificial__)) +void *memcpy(void *__dst, const void *__src, size_t __n) +{ + return __builtin___memcpy_chk(__dst, __src, __n, __builtin_object_size((__dst), ((0) > 0) && (2 > 1))); +} + +void *memcpy(void *_Dst, const void *_Src, size_t _Size); + +char *a, *b; +void func(void) { + memcpy(a, b, 42); +} + +// CHECK-LABEL: define {{.*}} @func( +// CHECK: call ptr @memcpy.inline + +// CHECK-LABEL: declare {{.*}} @memcpy( + +// CHECK-LABEL: define {{.*}} @memcpy.inline( +// CHECK: call ptr @__memcpy_chk diff --git a/clang/test/CodeGen/ubsan-builtin-checks.c b/clang/test/CodeGen/ubsan-builtin-checks.c index eb6ff11f4cebb..2bc32d8df4850 100644 --- a/clang/test/CodeGen/ubsan-builtin-checks.c +++ b/clang/test/CodeGen/ubsan-builtin-checks.c @@ -1,7 +1,8 @@ -// RUN: %clang_cc1 -triple x86_64-apple-darwin10 -w -emit-llvm -o - %s -fsanitize=builtin | FileCheck %s -// RUN: %clang_cc1 -triple arm64-none-linux-gnu -w -emit-llvm -o - %s -fsanitize=builtin | FileCheck %s --check-prefix=NOT-UB +// RUN: %clang_cc1 -triple x86_64-apple-darwin10 -w -emit-llvm -o - %s -fsanitize=builtin | FileCheck %s --check-prefixes=CHECK,POISON +// RUN: %clang_cc1 -triple arm64-none-linux-gnu -w -emit-llvm -o - %s -fsanitize=builtin | FileCheck %s --check-prefixes=CHECK,NOPOISON -// NOT-UB-NOT: __ubsan_handle_invalid_builtin +// A zero input to __bultin_ctz/clz is considered UB even if the target does not +// want to optimize based on zero input being undefined. // CHECK: define{{.*}} void @check_ctz void check_ctz(int n) { @@ -13,7 +14,8 @@ void check_ctz(int n) { // CHECK-NEXT: unreachable // // Continuation block: - // CHECK: call i32 @llvm.cttz.i32(i32 [[N]], i1 true) + // POISON: call i32 @llvm.cttz.i32(i32 [[N]], i1 true) + // NOPOISON: call i32 @llvm.cttz.i32(i32 [[N]], i1 false) __builtin_ctz(n); // CHECK: call void @__ubsan_handle_invalid_builtin @@ -33,7 +35,8 @@ void check_clz(int n) { // CHECK-NEXT: unreachable // // Continuation block: - // CHECK: call i32 @llvm.ctlz.i32(i32 [[N]], i1 true) + // POISON: call i32 @llvm.ctlz.i32(i32 [[N]], i1 true) + // NOPOISON: call i32 @llvm.ctlz.i32(i32 [[N]], i1 false) __builtin_clz(n); // CHECK: call void @__ubsan_handle_invalid_builtin diff --git a/clang/test/CodeGenCUDA/amdgpu-atomic-ops.cu b/clang/test/CodeGenCUDA/amdgpu-atomic-ops.cu index 2e303dcebacc6..57557bf09f411 100644 --- a/clang/test/CodeGenCUDA/amdgpu-atomic-ops.cu +++ b/clang/test/CodeGenCUDA/amdgpu-atomic-ops.cu @@ -1,29 +1,98 @@ -// RUN: %clang_cc1 %s -emit-llvm -o - -triple=amdgcn-amd-amdhsa \ +// RUN: %clang_cc1 -x hip %s -emit-llvm -o - -triple=amdgcn-amd-amdhsa \ // RUN: -fcuda-is-device -target-cpu gfx906 -fnative-half-type \ // RUN: -fnative-half-arguments-and-returns | FileCheck %s +// RUN: %clang_cc1 -x hip %s -O3 -S -o - -triple=amdgcn-amd-amdhsa \ +// RUN: -fcuda-is-device -target-cpu gfx1100 -fnative-half-type \ +// RUN: -fnative-half-arguments-and-returns | FileCheck -check-prefix=SAFE %s + +// RUN: %clang_cc1 -x hip %s -O3 -S -o - -triple=amdgcn-amd-amdhsa \ +// RUN: -fcuda-is-device -target-cpu gfx940 -fnative-half-type \ +// RUN: -fnative-half-arguments-and-returns -munsafe-fp-atomics \ +// RUN: | FileCheck -check-prefix=UNSAFE %s + // REQUIRES: amdgpu-registered-target #include "Inputs/cuda.h" #include -__device__ float ffp1(float *p) { +__global__ void ffp1(float *p) { // CHECK-LABEL: @_Z4ffp1Pf // CHECK: atomicrmw fadd ptr {{.*}} monotonic - return __atomic_fetch_add(p, 1.0f, memory_order_relaxed); + // CHECK: atomicrmw fmax ptr {{.*}} monotonic + // CHECK: atomicrmw fmin ptr {{.*}} monotonic + // CHECK: atomicrmw fmax ptr {{.*}} syncscope("agent-one-as") monotonic + // CHECK: atomicrmw fmin ptr {{.*}} syncscope("workgroup-one-as") monotonic + // SAFE: _Z4ffp1Pf + // SAFE: global_atomic_cmpswap + // SAFE: global_atomic_cmpswap + // SAFE: global_atomic_cmpswap + // SAFE: global_atomic_cmpswap + // SAFE: global_atomic_cmpswap + // UNSAFE: _Z4ffp1Pf + // UNSAFE: global_atomic_add_f32 + // UNSAFE: global_atomic_cmpswap + // UNSAFE: global_atomic_cmpswap + // UNSAFE: global_atomic_cmpswap + // UNSAFE: global_atomic_cmpswap + __atomic_fetch_add(p, 1.0f, memory_order_relaxed); + __atomic_fetch_max(p, 1.0f, memory_order_relaxed); + __atomic_fetch_min(p, 1.0f, memory_order_relaxed); + __hip_atomic_fetch_max(p, 1.0f, memory_order_relaxed, __HIP_MEMORY_SCOPE_AGENT); + __hip_atomic_fetch_min(p, 1.0f, memory_order_relaxed, __HIP_MEMORY_SCOPE_WORKGROUP); } -__device__ double ffp2(double *p) { +__global__ void ffp2(double *p) { // CHECK-LABEL: @_Z4ffp2Pd // CHECK: atomicrmw fsub ptr {{.*}} monotonic - return __atomic_fetch_sub(p, 1.0, memory_order_relaxed); + // CHECK: atomicrmw fmax ptr {{.*}} monotonic + // CHECK: atomicrmw fmin ptr {{.*}} monotonic + // CHECK: atomicrmw fmax ptr {{.*}} syncscope("agent-one-as") monotonic + // CHECK: atomicrmw fmin ptr {{.*}} syncscope("workgroup-one-as") monotonic + // SAFE: _Z4ffp2Pd + // SAFE: global_atomic_cmpswap_b64 + // SAFE: global_atomic_cmpswap_b64 + // SAFE: global_atomic_cmpswap_b64 + // SAFE: global_atomic_cmpswap_b64 + // SAFE: global_atomic_cmpswap_b64 + // UNSAFE: _Z4ffp2Pd + // UNSAFE: global_atomic_cmpswap_x2 + // UNSAFE: global_atomic_cmpswap_x2 + // UNSAFE: global_atomic_cmpswap_x2 + // UNSAFE: global_atomic_cmpswap_x2 + // UNSAFE: global_atomic_cmpswap_x2 + __atomic_fetch_sub(p, 1.0, memory_order_relaxed); + __atomic_fetch_max(p, 1.0, memory_order_relaxed); + __atomic_fetch_min(p, 1.0, memory_order_relaxed); + __hip_atomic_fetch_max(p, 1.0f, memory_order_relaxed, __HIP_MEMORY_SCOPE_AGENT); + __hip_atomic_fetch_min(p, 1.0f, memory_order_relaxed, __HIP_MEMORY_SCOPE_WORKGROUP); } // long double is the same as double for amdgcn. -__device__ long double ffp3(long double *p) { +__global__ void ffp3(long double *p) { // CHECK-LABEL: @_Z4ffp3Pe // CHECK: atomicrmw fsub ptr {{.*}} monotonic - return __atomic_fetch_sub(p, 1.0L, memory_order_relaxed); + // CHECK: atomicrmw fmax ptr {{.*}} monotonic + // CHECK: atomicrmw fmin ptr {{.*}} monotonic + // CHECK: atomicrmw fmax ptr {{.*}} syncscope("agent-one-as") monotonic + // CHECK: atomicrmw fmin ptr {{.*}} syncscope("workgroup-one-as") monotonic + // SAFE: _Z4ffp3Pe + // SAFE: global_atomic_cmpswap_b64 + // SAFE: global_atomic_cmpswap_b64 + // SAFE: global_atomic_cmpswap_b64 + // SAFE: global_atomic_cmpswap_b64 + // SAFE: global_atomic_cmpswap_b64 + // UNSAFE: _Z4ffp3Pe + // UNSAFE: global_atomic_cmpswap_x2 + // UNSAFE: global_atomic_cmpswap_x2 + // UNSAFE: global_atomic_cmpswap_x2 + // UNSAFE: global_atomic_cmpswap_x2 + // UNSAFE: global_atomic_cmpswap_x2 + __atomic_fetch_sub(p, 1.0L, memory_order_relaxed); + __atomic_fetch_max(p, 1.0L, memory_order_relaxed); + __atomic_fetch_min(p, 1.0L, memory_order_relaxed); + __hip_atomic_fetch_max(p, 1.0f, memory_order_relaxed, __HIP_MEMORY_SCOPE_AGENT); + __hip_atomic_fetch_min(p, 1.0f, memory_order_relaxed, __HIP_MEMORY_SCOPE_WORKGROUP); } __device__ double ffp4(double *p, float f) { @@ -39,3 +108,29 @@ __device__ double ffp5(double *p, int i) { // CHECK: atomicrmw fsub ptr {{.*}} monotonic return __atomic_fetch_sub(p, i, memory_order_relaxed); } + +__global__ void ffp6(_Float16 *p) { + // CHECK-LABEL: @_Z4ffp6PDF16 + // CHECK: atomicrmw fadd ptr {{.*}} monotonic + // CHECK: atomicrmw fmax ptr {{.*}} monotonic + // CHECK: atomicrmw fmin ptr {{.*}} monotonic + // CHECK: atomicrmw fmax ptr {{.*}} syncscope("agent-one-as") monotonic + // CHECK: atomicrmw fmin ptr {{.*}} syncscope("workgroup-one-as") monotonic + // SAFE: _Z4ffp6PDF16 + // SAFE: global_atomic_cmpswap + // SAFE: global_atomic_cmpswap + // SAFE: global_atomic_cmpswap + // SAFE: global_atomic_cmpswap + // SAFE: global_atomic_cmpswap + // UNSAFE: _Z4ffp6PDF16 + // UNSAFE: global_atomic_cmpswap + // UNSAFE: global_atomic_cmpswap + // UNSAFE: global_atomic_cmpswap + // UNSAFE: global_atomic_cmpswap + // UNSAFE: global_atomic_cmpswap + __atomic_fetch_add(p, 1.0, memory_order_relaxed); + __atomic_fetch_max(p, 1.0, memory_order_relaxed); + __atomic_fetch_min(p, 1.0, memory_order_relaxed); + __hip_atomic_fetch_max(p, 1.0f, memory_order_relaxed, __HIP_MEMORY_SCOPE_AGENT); + __hip_atomic_fetch_min(p, 1.0f, memory_order_relaxed, __HIP_MEMORY_SCOPE_WORKGROUP); +} diff --git a/clang/test/CodeGenCUDA/atomic-ops.cu b/clang/test/CodeGenCUDA/atomic-ops.cu index 13f4a015386cb..fbc042caa809f 100644 --- a/clang/test/CodeGenCUDA/atomic-ops.cu +++ b/clang/test/CodeGenCUDA/atomic-ops.cu @@ -6,6 +6,7 @@ // CHECK: cmpxchg weak ptr {{%[0-9]+}}, i32 {{%[0-9]+}}, i32 {{%[0-9]+}} syncscope("singlethread-one-as") monotonic monotonic, align 4 // CHECK: atomicrmw xchg ptr {{%[0-9]+}}, i32 {{%[0-9]+}} syncscope("singlethread-one-as") // CHECK: atomicrmw add ptr {{%[0-9]+}}, i32 {{%[0-9]+}} syncscope("singlethread-one-as") +// CHECK: atomicrmw sub ptr {{%[0-9]+}}, i32 {{%[0-9]+}} syncscope("singlethread-one-as") // CHECK: atomicrmw and ptr {{%[0-9]+}}, i32 {{%[0-9]+}} syncscope("singlethread-one-as") // CHECK: atomicrmw or ptr {{%[0-9]+}}, i32 {{%[0-9]+}} syncscope("singlethread-one-as") // CHECK: atomicrmw xor ptr {{%[0-9]+}}, i32 {{%[0-9]+}} syncscope("singlethread-one-as") @@ -18,6 +19,7 @@ __device__ int atomic32_op_singlethread(int *ptr, int val, int desired) { flag = __hip_atomic_compare_exchange_weak(ptr, &val, desired, __ATOMIC_RELAXED, __ATOMIC_RELAXED, __HIP_MEMORY_SCOPE_SINGLETHREAD); val = __hip_atomic_exchange(ptr, val, __ATOMIC_RELAXED, __HIP_MEMORY_SCOPE_SINGLETHREAD); val = __hip_atomic_fetch_add(ptr, val, __ATOMIC_RELAXED, __HIP_MEMORY_SCOPE_SINGLETHREAD); + val = __hip_atomic_fetch_sub(ptr, val, __ATOMIC_RELAXED, __HIP_MEMORY_SCOPE_SINGLETHREAD); val = __hip_atomic_fetch_and(ptr, val, __ATOMIC_RELAXED, __HIP_MEMORY_SCOPE_SINGLETHREAD); val = __hip_atomic_fetch_or(ptr, val, __ATOMIC_RELAXED, __HIP_MEMORY_SCOPE_SINGLETHREAD); val = __hip_atomic_fetch_xor(ptr, val, __ATOMIC_RELAXED, __HIP_MEMORY_SCOPE_SINGLETHREAD); @@ -42,6 +44,7 @@ __device__ unsigned int atomicu32_op_singlethread(unsigned int *ptr, unsigned in // CHECK: cmpxchg weak ptr {{%[0-9]+}}, i32 {{%[0-9]+}}, i32 {{%[0-9]+}} syncscope("wavefront-one-as") monotonic monotonic, align 4 // CHECK: atomicrmw xchg ptr {{%[0-9]+}}, i32 {{%[0-9]+}} syncscope("wavefront-one-as") // CHECK: atomicrmw add ptr {{%[0-9]+}}, i32 {{%[0-9]+}} syncscope("wavefront-one-as") +// CHECK: atomicrmw sub ptr {{%[0-9]+}}, i32 {{%[0-9]+}} syncscope("wavefront-one-as") // CHECK: atomicrmw and ptr {{%[0-9]+}}, i32 {{%[0-9]+}} syncscope("wavefront-one-as") // CHECK: atomicrmw or ptr {{%[0-9]+}}, i32 {{%[0-9]+}} syncscope("wavefront-one-as") // CHECK: atomicrmw xor ptr {{%[0-9]+}}, i32 {{%[0-9]+}} syncscope("wavefront-one-as") @@ -54,6 +57,7 @@ __device__ int atomic32_op_wavefront(int *ptr, int val, int desired) { flag = __hip_atomic_compare_exchange_weak(ptr, &val, desired, __ATOMIC_RELAXED, __ATOMIC_RELAXED, __HIP_MEMORY_SCOPE_WAVEFRONT); val = __hip_atomic_exchange(ptr, val, __ATOMIC_RELAXED, __HIP_MEMORY_SCOPE_WAVEFRONT); val = __hip_atomic_fetch_add(ptr, val, __ATOMIC_RELAXED, __HIP_MEMORY_SCOPE_WAVEFRONT); + val = __hip_atomic_fetch_sub(ptr, val, __ATOMIC_RELAXED, __HIP_MEMORY_SCOPE_WAVEFRONT); val = __hip_atomic_fetch_and(ptr, val, __ATOMIC_RELAXED, __HIP_MEMORY_SCOPE_WAVEFRONT); val = __hip_atomic_fetch_or(ptr, val, __ATOMIC_RELAXED, __HIP_MEMORY_SCOPE_WAVEFRONT); val = __hip_atomic_fetch_xor(ptr, val, __ATOMIC_RELAXED, __HIP_MEMORY_SCOPE_WAVEFRONT); @@ -78,6 +82,7 @@ __device__ unsigned int atomicu32_op_wavefront(unsigned int *ptr, unsigned int v // CHECK: cmpxchg weak ptr {{%[0-9]+}}, i32 {{%[0-9]+}}, i32 {{%[0-9]+}} syncscope("workgroup-one-as") monotonic monotonic, align 4 // CHECK: atomicrmw xchg ptr {{%[0-9]+}}, i32 {{%[0-9]+}} syncscope("workgroup-one-as") // CHECK: atomicrmw add ptr {{%[0-9]+}}, i32 {{%[0-9]+}} syncscope("workgroup-one-as") +// CHECK: atomicrmw sub ptr {{%[0-9]+}}, i32 {{%[0-9]+}} syncscope("workgroup-one-as") // CHECK: atomicrmw and ptr {{%[0-9]+}}, i32 {{%[0-9]+}} syncscope("workgroup-one-as") // CHECK: atomicrmw or ptr {{%[0-9]+}}, i32 {{%[0-9]+}} syncscope("workgroup-one-as") // CHECK: atomicrmw xor ptr {{%[0-9]+}}, i32 {{%[0-9]+}} syncscope("workgroup-one-as") @@ -89,6 +94,7 @@ __device__ int atomic32_op_workgroup(int *ptr, int val, int desired) { flag = __hip_atomic_compare_exchange_weak(ptr, &val, desired, __ATOMIC_RELAXED, __ATOMIC_RELAXED, __HIP_MEMORY_SCOPE_WORKGROUP); val = __hip_atomic_exchange(ptr, val, __ATOMIC_RELAXED, __HIP_MEMORY_SCOPE_WORKGROUP); val = __hip_atomic_fetch_add(ptr, val, __ATOMIC_RELAXED, __HIP_MEMORY_SCOPE_WORKGROUP); + val = __hip_atomic_fetch_sub(ptr, val, __ATOMIC_RELAXED, __HIP_MEMORY_SCOPE_WORKGROUP); val = __hip_atomic_fetch_and(ptr, val, __ATOMIC_RELAXED, __HIP_MEMORY_SCOPE_WORKGROUP); val = __hip_atomic_fetch_or(ptr, val, __ATOMIC_RELAXED, __HIP_MEMORY_SCOPE_WORKGROUP); val = __hip_atomic_fetch_xor(ptr, val, __ATOMIC_RELAXED, __HIP_MEMORY_SCOPE_WORKGROUP); @@ -112,6 +118,7 @@ __device__ unsigned int atomicu32_op_workgroup(unsigned int *ptr, unsigned int v // CHECK: cmpxchg weak ptr {{%[0-9]+}}, i32 {{%[0-9]+}}, i32 {{%[0-9]+}} syncscope("agent-one-as") monotonic monotonic, align 4 // CHECK: atomicrmw xchg ptr {{%[0-9]+}}, i32 {{%[0-9]+}} syncscope("agent-one-as") // CHECK: atomicrmw add ptr {{%[0-9]+}}, i32 {{%[0-9]+}} syncscope("agent-one-as") +// CHECK: atomicrmw sub ptr {{%[0-9]+}}, i32 {{%[0-9]+}} syncscope("agent-one-as") // CHECK: atomicrmw and ptr {{%[0-9]+}}, i32 {{%[0-9]+}} syncscope("agent-one-as") // CHECK: atomicrmw or ptr {{%[0-9]+}}, i32 {{%[0-9]+}} syncscope("agent-one-as") // CHECK: atomicrmw xor ptr {{%[0-9]+}}, i32 {{%[0-9]+}} syncscope("agent-one-as") @@ -123,6 +130,7 @@ __device__ int atomic32_op_agent(int *ptr, int val, int desired) { flag = __hip_atomic_compare_exchange_weak(ptr, &val, desired, __ATOMIC_RELAXED, __ATOMIC_RELAXED, __HIP_MEMORY_SCOPE_AGENT); val = __hip_atomic_exchange(ptr, val, __ATOMIC_RELAXED, __HIP_MEMORY_SCOPE_AGENT); val = __hip_atomic_fetch_add(ptr, val, __ATOMIC_RELAXED, __HIP_MEMORY_SCOPE_AGENT); + val = __hip_atomic_fetch_sub(ptr, val, __ATOMIC_RELAXED, __HIP_MEMORY_SCOPE_AGENT); val = __hip_atomic_fetch_and(ptr, val, __ATOMIC_RELAXED, __HIP_MEMORY_SCOPE_AGENT); val = __hip_atomic_fetch_or(ptr, val, __ATOMIC_RELAXED, __HIP_MEMORY_SCOPE_AGENT); val = __hip_atomic_fetch_xor(ptr, val, __ATOMIC_RELAXED, __HIP_MEMORY_SCOPE_AGENT); @@ -146,6 +154,7 @@ __device__ unsigned int atomicu32_op_agent(unsigned int *ptr, unsigned int val, // CHECK: cmpxchg weak ptr {{%[0-9]+}}, i32 {{%[0-9]+}}, i32 {{%[0-9]+}} syncscope("one-as") monotonic monotonic, align 4 // CHECK: atomicrmw xchg ptr {{%[0-9]+}}, i32 {{%[0-9]+}} syncscope("one-as") // CHECK: atomicrmw add ptr {{%[0-9]+}}, i32 {{%[0-9]+}} syncscope("one-as") +// CHECK: atomicrmw sub ptr {{%[0-9]+}}, i32 {{%[0-9]+}} syncscope("one-as") // CHECK: atomicrmw and ptr {{%[0-9]+}}, i32 {{%[0-9]+}} syncscope("one-as") // CHECK: atomicrmw or ptr {{%[0-9]+}}, i32 {{%[0-9]+}} syncscope("one-as") // CHECK: atomicrmw xor ptr {{%[0-9]+}}, i32 {{%[0-9]+}} syncscope("one-as") @@ -158,6 +167,7 @@ __device__ int atomic32_op_system(int *ptr, int val, int desired) { flag = __hip_atomic_compare_exchange_weak(ptr, &val, desired, __ATOMIC_RELAXED, __ATOMIC_RELAXED, __HIP_MEMORY_SCOPE_SYSTEM); val = __hip_atomic_exchange(ptr, val, __ATOMIC_RELAXED, __HIP_MEMORY_SCOPE_SYSTEM); val = __hip_atomic_fetch_add(ptr, val, __ATOMIC_RELAXED, __HIP_MEMORY_SCOPE_SYSTEM); + val = __hip_atomic_fetch_sub(ptr, val, __ATOMIC_RELAXED, __HIP_MEMORY_SCOPE_SYSTEM); val = __hip_atomic_fetch_and(ptr, val, __ATOMIC_RELAXED, __HIP_MEMORY_SCOPE_SYSTEM); val = __hip_atomic_fetch_or(ptr, val, __ATOMIC_RELAXED, __HIP_MEMORY_SCOPE_SYSTEM); val = __hip_atomic_fetch_xor(ptr, val, __ATOMIC_RELAXED, __HIP_MEMORY_SCOPE_SYSTEM); @@ -182,6 +192,7 @@ __device__ unsigned int atomicu32_op_system(unsigned int *ptr, unsigned int val, // CHECK: cmpxchg weak ptr {{%[0-9]+}}, i64 {{%[0-9]+}}, i64 {{%[0-9]+}} syncscope("singlethread-one-as") monotonic monotonic, align 8 // CHECK: atomicrmw xchg ptr {{%[0-9]+}}, i64 {{%[0-9]+}} syncscope("singlethread-one-as") // CHECK: atomicrmw add ptr {{%[0-9]+}}, i64 {{%[0-9]+}} syncscope("singlethread-one-as") +// CHECK: atomicrmw sub ptr {{%[0-9]+}}, i64 {{%[0-9]+}} syncscope("singlethread-one-as") // CHECK: atomicrmw and ptr {{%[0-9]+}}, i64 {{%[0-9]+}} syncscope("singlethread-one-as") // CHECK: atomicrmw or ptr {{%[0-9]+}}, i64 {{%[0-9]+}} syncscope("singlethread-one-as") // CHECK: atomicrmw xor ptr {{%[0-9]+}}, i64 {{%[0-9]+}} syncscope("singlethread-one-as") @@ -193,6 +204,7 @@ __device__ long long atomic64_op_singlethread(long long *ptr, long long *ptr2, l flag = __hip_atomic_compare_exchange_weak(ptr, &val, desired, __ATOMIC_RELAXED, __ATOMIC_RELAXED, __HIP_MEMORY_SCOPE_SINGLETHREAD); val = __hip_atomic_exchange(ptr, val, __ATOMIC_RELAXED, __HIP_MEMORY_SCOPE_SINGLETHREAD); val = __hip_atomic_fetch_add(ptr, val, __ATOMIC_RELAXED, __HIP_MEMORY_SCOPE_SINGLETHREAD); + val = __hip_atomic_fetch_sub(ptr, val, __ATOMIC_RELAXED, __HIP_MEMORY_SCOPE_SINGLETHREAD); val = __hip_atomic_fetch_and(ptr, val, __ATOMIC_RELAXED, __HIP_MEMORY_SCOPE_SINGLETHREAD); val = __hip_atomic_fetch_or(ptr, val, __ATOMIC_RELAXED, __HIP_MEMORY_SCOPE_SINGLETHREAD); val = __hip_atomic_fetch_xor(ptr, val, __ATOMIC_RELAXED, __HIP_MEMORY_SCOPE_SINGLETHREAD); @@ -220,6 +232,7 @@ __device__ unsigned long long atomicu64_op_singlethread(unsigned long long *ptr, // CHECK: cmpxchg weak ptr {{%[0-9]+}}, i64 {{%[0-9]+}}, i64 {{%[0-9]+}} syncscope("wavefront-one-as") monotonic monotonic, align 8 // CHECK: atomicrmw xchg ptr {{%[0-9]+}}, i64 {{%[0-9]+}} syncscope("wavefront-one-as") // CHECK: atomicrmw add ptr {{%[0-9]+}}, i64 {{%[0-9]+}} syncscope("wavefront-one-as") +// CHECK: atomicrmw sub ptr {{%[0-9]+}}, i64 {{%[0-9]+}} syncscope("wavefront-one-as") // CHECK: atomicrmw and ptr {{%[0-9]+}}, i64 {{%[0-9]+}} syncscope("wavefront-one-as") // CHECK: atomicrmw or ptr {{%[0-9]+}}, i64 {{%[0-9]+}} syncscope("wavefront-one-as") // CHECK: atomicrmw xor ptr {{%[0-9]+}}, i64 {{%[0-9]+}} syncscope("wavefront-one-as") @@ -232,6 +245,7 @@ __device__ long long atomic64_op_wavefront(long long *ptr, long long *ptr2, long flag = __hip_atomic_compare_exchange_weak(ptr, &val, desired, __ATOMIC_RELAXED, __ATOMIC_RELAXED, __HIP_MEMORY_SCOPE_WAVEFRONT); val = __hip_atomic_exchange(ptr, val, __ATOMIC_RELAXED, __HIP_MEMORY_SCOPE_WAVEFRONT); val = __hip_atomic_fetch_add(ptr, val, __ATOMIC_RELAXED, __HIP_MEMORY_SCOPE_WAVEFRONT); + val = __hip_atomic_fetch_sub(ptr, val, __ATOMIC_RELAXED, __HIP_MEMORY_SCOPE_WAVEFRONT); val = __hip_atomic_fetch_and(ptr, val, __ATOMIC_RELAXED, __HIP_MEMORY_SCOPE_WAVEFRONT); val = __hip_atomic_fetch_or(ptr, val, __ATOMIC_RELAXED, __HIP_MEMORY_SCOPE_WAVEFRONT); val = __hip_atomic_fetch_xor(ptr, val, __ATOMIC_RELAXED, __HIP_MEMORY_SCOPE_WAVEFRONT); @@ -260,6 +274,7 @@ __device__ unsigned long long atomicu64_op_wavefront(unsigned long long *ptr, un // CHECK: cmpxchg weak ptr {{%[0-9]+}}, i64 {{%[0-9]+}}, i64 {{%[0-9]+}} syncscope("workgroup-one-as") monotonic monotonic, align 8 // CHECK: atomicrmw xchg ptr {{%[0-9]+}}, i64 {{%[0-9]+}} syncscope("workgroup-one-as") // CHECK: atomicrmw add ptr {{%[0-9]+}}, i64 {{%[0-9]+}} syncscope("workgroup-one-as") +// CHECK: atomicrmw sub ptr {{%[0-9]+}}, i64 {{%[0-9]+}} syncscope("workgroup-one-as") // CHECK: atomicrmw and ptr {{%[0-9]+}}, i64 {{%[0-9]+}} syncscope("workgroup-one-as") // CHECK: atomicrmw or ptr {{%[0-9]+}}, i64 {{%[0-9]+}} syncscope("workgroup-one-as") // CHECK: atomicrmw xor ptr {{%[0-9]+}}, i64 {{%[0-9]+}} syncscope("workgroup-one-as") @@ -271,6 +286,7 @@ __device__ long long atomic64_op_workgroup(long long *ptr, long long *ptr2, long flag = __hip_atomic_compare_exchange_weak(ptr, &val, desired, __ATOMIC_RELAXED, __ATOMIC_RELAXED, __HIP_MEMORY_SCOPE_WORKGROUP); val = __hip_atomic_exchange(ptr, val, __ATOMIC_RELAXED, __HIP_MEMORY_SCOPE_WORKGROUP); val = __hip_atomic_fetch_add(ptr, val, __ATOMIC_RELAXED, __HIP_MEMORY_SCOPE_WORKGROUP); + val = __hip_atomic_fetch_sub(ptr, val, __ATOMIC_RELAXED, __HIP_MEMORY_SCOPE_WORKGROUP); val = __hip_atomic_fetch_and(ptr, val, __ATOMIC_RELAXED, __HIP_MEMORY_SCOPE_WORKGROUP); val = __hip_atomic_fetch_or(ptr, val, __ATOMIC_RELAXED, __HIP_MEMORY_SCOPE_WORKGROUP); val = __hip_atomic_fetch_xor(ptr, val, __ATOMIC_RELAXED, __HIP_MEMORY_SCOPE_WORKGROUP); @@ -296,6 +312,7 @@ __device__ unsigned long long atomicu64_op_workgroup(unsigned long long *ptr, un // CHECK: cmpxchg weak ptr {{%[0-9]+}}, i64 {{%[0-9]+}}, i64 {{%[0-9]+}} syncscope("agent-one-as") monotonic monotonic, align 8 // CHECK: atomicrmw xchg ptr {{%[0-9]+}}, i64 {{%[0-9]+}} syncscope("agent-one-as") // CHECK: atomicrmw add ptr {{%[0-9]+}}, i64 {{%[0-9]+}} syncscope("agent-one-as") +// CHECK: atomicrmw sub ptr {{%[0-9]+}}, i64 {{%[0-9]+}} syncscope("agent-one-as") // CHECK: atomicrmw and ptr {{%[0-9]+}}, i64 {{%[0-9]+}} syncscope("agent-one-as") // CHECK: atomicrmw or ptr {{%[0-9]+}}, i64 {{%[0-9]+}} syncscope("agent-one-as") // CHECK: atomicrmw xor ptr {{%[0-9]+}}, i64 {{%[0-9]+}} syncscope("agent-one-as") @@ -307,6 +324,7 @@ __device__ long long atomic64_op_agent(long long *ptr, long long *ptr2, long lon flag = __hip_atomic_compare_exchange_weak(ptr, &val, desired, __ATOMIC_RELAXED, __ATOMIC_RELAXED, __HIP_MEMORY_SCOPE_AGENT); val = __hip_atomic_exchange(ptr, val, __ATOMIC_RELAXED, __HIP_MEMORY_SCOPE_AGENT); val = __hip_atomic_fetch_add(ptr, val, __ATOMIC_RELAXED, __HIP_MEMORY_SCOPE_AGENT); + val = __hip_atomic_fetch_sub(ptr, val, __ATOMIC_RELAXED, __HIP_MEMORY_SCOPE_AGENT); val = __hip_atomic_fetch_and(ptr, val, __ATOMIC_RELAXED, __HIP_MEMORY_SCOPE_AGENT); val = __hip_atomic_fetch_or(ptr, val, __ATOMIC_RELAXED, __HIP_MEMORY_SCOPE_AGENT); val = __hip_atomic_fetch_xor(ptr, val, __ATOMIC_RELAXED, __HIP_MEMORY_SCOPE_AGENT); @@ -332,6 +350,7 @@ __device__ unsigned long long atomicu64_op_agent(unsigned long long *ptr, unsign // CHECK: cmpxchg weak ptr {{%[0-9]+}}, i64 {{%[0-9]+}}, i64 {{%[0-9]+}} syncscope("one-as") monotonic monotonic, align 8 // CHECK: atomicrmw xchg ptr {{%[0-9]+}}, i64 {{%[0-9]+}} syncscope("one-as") // CHECK: atomicrmw add ptr {{%[0-9]+}}, i64 {{%[0-9]+}} syncscope("one-as") +// CHECK: atomicrmw sub ptr {{%[0-9]+}}, i64 {{%[0-9]+}} syncscope("one-as") // CHECK: atomicrmw and ptr {{%[0-9]+}}, i64 {{%[0-9]+}} syncscope("one-as") // CHECK: atomicrmw or ptr {{%[0-9]+}}, i64 {{%[0-9]+}} syncscope("one-as") // CHECK: atomicrmw xor ptr {{%[0-9]+}}, i64 {{%[0-9]+}} syncscope("one-as") @@ -344,6 +363,7 @@ __device__ long long atomic64_op_system(long long *ptr, long long *ptr2, long lo flag = __hip_atomic_compare_exchange_weak(ptr, &val, desired, __ATOMIC_RELAXED, __ATOMIC_RELAXED, __HIP_MEMORY_SCOPE_SYSTEM); val = __hip_atomic_exchange(ptr, val, __ATOMIC_RELAXED, __HIP_MEMORY_SCOPE_SYSTEM); val = __hip_atomic_fetch_add(ptr, val, __ATOMIC_RELAXED, __HIP_MEMORY_SCOPE_SYSTEM); + val = __hip_atomic_fetch_sub(ptr, val, __ATOMIC_RELAXED, __HIP_MEMORY_SCOPE_SYSTEM); val = __hip_atomic_fetch_and(ptr, val, __ATOMIC_RELAXED, __HIP_MEMORY_SCOPE_SYSTEM); val = __hip_atomic_fetch_or(ptr, val, __ATOMIC_RELAXED, __HIP_MEMORY_SCOPE_SYSTEM); val = __hip_atomic_fetch_xor(ptr, val, __ATOMIC_RELAXED, __HIP_MEMORY_SCOPE_SYSTEM); diff --git a/clang/test/CodeGenCXX/pr59765-modules-global-ctor-dtor.cppm b/clang/test/CodeGenCXX/pr59765-modules-global-ctor-dtor.cppm index 1a9384bf0bc9a..9956348f87ff4 100644 --- a/clang/test/CodeGenCXX/pr59765-modules-global-ctor-dtor.cppm +++ b/clang/test/CodeGenCXX/pr59765-modules-global-ctor-dtor.cppm @@ -1,9 +1,9 @@ // https://github.com/llvm/llvm-project/issues/59765 // FIXME: Since the signature of the constructors/destructors is // different in different targets. The current CHECK can't work -// well when targeting or running on AIX. +// well when targeting or running on AIX and z/OS. // It would be better to add the corresponding test for other test. -// UNSUPPORTED: system-aix +// UNSUPPORTED: system-zos, system-aix // // RUN: rm -rf %t // RUN: mkdir %t diff --git a/clang/test/CodeGenCXX/vtt-address-space.cpp b/clang/test/CodeGenCXX/vtt-address-space.cpp new file mode 100644 index 0000000000000..595587923d5f6 --- /dev/null +++ b/clang/test/CodeGenCXX/vtt-address-space.cpp @@ -0,0 +1,30 @@ +// RUN: %clang_cc1 %s -triple=amdgcn-amd-amdhsa -std=c++11 -emit-llvm -o - | FileCheck %s +// This is temporarily disabled as it requires fixing typeinfo & vptr handling +// as well; it will be enabled once those fixes are in. +// XFAIL: * + +// This is the sample from the C++ Itanium ABI, p2.6.2. +namespace Test { + class A1 { int i; }; + class A2 { int i; virtual void f(); }; + class V1 : public A1, public A2 { int i; }; + class B1 { int i; }; + class B2 { int i; }; + class V2 : public B1, public B2, public virtual V1 { int i; }; + class V3 { virtual void g(); }; + class C1 : public virtual V1 { int i; }; + class C2 : public virtual V3, virtual V2 { int i; }; + class X1 { int i; }; + class C3 : public X1 { int i; }; + class D : public C1, public C2, public C3 { int i; }; + + D d; +} + +// CHECK: @_ZTTN4Test1DE = linkonce_odr unnamed_addr addrspace(1) constant [13 x ptr] [ptr addrspacecast (ptr addrspace(1) getelementptr inbounds ({ [5 x ptr], [7 x ptr], [4 x ptr], [3 x ptr] }, ptr addrspace(1) @_ZTVN4Test1DE, i32 0, inrange i32 0, i32 5) to ptr), ptr addrspacecast (ptr addrspace(1) getelementptr inbounds ({ [3 x ptr], [4 x ptr] }, ptr addrspace(1) @_ZTCN4Test1DE0_NS_2C1E, i32 0, inrange i32 0, i32 3) to ptr), ptr addrspacecast (ptr addrspace(1) getelementptr inbounds ({ [3 x ptr], [4 x ptr] }, ptr addrspace(1) @_ZTCN4Test1DE0_NS_2C1E, i32 0, inrange i32 1, i32 3) to ptr), ptr addrspacecast (ptr addrspace(1) getelementptr inbounds ({ [7 x ptr], [3 x ptr], [4 x ptr] }, ptr addrspace(1) @_ZTCN4Test1DE16_NS_2C2E, i32 0, inrange i32 0, i32 6) to ptr), ptr addrspacecast (ptr addrspace(1) getelementptr inbounds ({ [7 x ptr], [3 x ptr], [4 x ptr] }, ptr addrspace(1) @_ZTCN4Test1DE16_NS_2C2E, i32 0, inrange i32 0, i32 6) to ptr), ptr addrspacecast (ptr addrspace(1) getelementptr inbounds ({ [7 x ptr], [3 x ptr], [4 x ptr] }, ptr addrspace(1) @_ZTCN4Test1DE16_NS_2C2E, i32 0, inrange i32 1, i32 3) to ptr), ptr addrspacecast (ptr addrspace(1) getelementptr inbounds ({ [7 x ptr], [3 x ptr], [4 x ptr] }, ptr addrspace(1) @_ZTCN4Test1DE16_NS_2C2E, i32 0, inrange i32 2, i32 3) to ptr), ptr addrspacecast (ptr addrspace(1) getelementptr inbounds ({ [5 x ptr], [7 x ptr], [4 x ptr], [3 x ptr] }, ptr addrspace(1) @_ZTVN4Test1DE, i32 0, inrange i32 2, i32 3) to ptr), ptr addrspacecast (ptr addrspace(1) getelementptr inbounds ({ [5 x ptr], [7 x ptr], [4 x ptr], [3 x ptr] }, ptr addrspace(1) @_ZTVN4Test1DE, i32 0, inrange i32 1, i32 6) to ptr), ptr addrspacecast (ptr addrspace(1) getelementptr inbounds ({ [5 x ptr], [7 x ptr], [4 x ptr], [3 x ptr] }, ptr addrspace(1) @_ZTVN4Test1DE, i32 0, inrange i32 1, i32 6) to ptr), ptr addrspacecast (ptr addrspace(1) getelementptr inbounds ({ [5 x ptr], [7 x ptr], [4 x ptr], [3 x ptr] }, ptr addrspace(1) @_ZTVN4Test1DE, i32 0, inrange i32 3, i32 3) to ptr), ptr addrspacecast (ptr addrspace(1) getelementptr inbounds ({ [3 x ptr], [4 x ptr] }, ptr addrspace(1) @_ZTCN4Test1DE64_NS_2V2E, i32 0, inrange i32 0, i32 3) to ptr), ptr addrspacecast (ptr addrspace(1) getelementptr inbounds ({ [3 x ptr], [4 x ptr] }, ptr addrspace(1) @_ZTCN4Test1DE64_NS_2V2E, i32 0, inrange i32 1, i32 3) to ptr)], comdat, align 8 +// CHECK: call void @_ZN4Test2V2C2Ev(ptr noundef nonnull align 8 dereferenceable(20) %2, ptr addrspace(1) noundef getelementptr inbounds ([13 x ptr], ptr addrspace(1) @_ZTTN4Test1DE, i64 0, i64 11)) +// CHECK: call void @_ZN4Test2C1C2Ev(ptr noundef nonnull align 8 dereferenceable(12) %this1, ptr addrspace(1) noundef getelementptr inbounds ([13 x ptr], ptr addrspace(1) @_ZTTN4Test1DE, i64 0, i64 1)) +// CHECK: call void @_ZN4Test2C2C2Ev(ptr noundef nonnull align 8 dereferenceable(12) %3, ptr addrspace(1) noundef getelementptr inbounds ([13 x ptr], ptr addrspace(1) @_ZTTN4Test1DE, i64 0, i64 3)) +// CHECK-NEXT: define linkonce_odr void @_ZN4Test2V2C2Ev(ptr noundef nonnull align 8 dereferenceable(20) %this, ptr addrspace(1) noundef %vtt) +// CHECK-NEXT: define linkonce_odr void @_ZN4Test2C1C2Ev(ptr noundef nonnull align 8 dereferenceable(12) %this, ptr addrspace(1) noundef %vtt) +// CHECK-NEXT: define linkonce_odr void @_ZN4Test2C2C2Ev(ptr noundef nonnull align 8 dereferenceable(12) %this, ptr addrspace(1) noundef %vtt) diff --git a/clang/test/CodeGenObjCXX/property-dot-reference.mm b/clang/test/CodeGenObjCXX/property-dot-reference.mm index 126676d4f0346..9fb35858219f8 100644 --- a/clang/test/CodeGenObjCXX/property-dot-reference.mm +++ b/clang/test/CodeGenObjCXX/property-dot-reference.mm @@ -1,4 +1,4 @@ -// RUN: %clang_cc1 -no-opaque-pointers -triple x86_64-apple-darwin10 -emit-llvm -fexceptions -o - %s | FileCheck %s +// RUN: %clang_cc1 -triple x86_64-apple-darwin10 -emit-llvm -fexceptions -o - %s | FileCheck %s // rdar://8409336 struct TFENode { @@ -11,8 +11,8 @@ @interface TNodeIconAndNameCell @implementation TNodeIconAndNameCell - (const TFENode&) node { -// CHECK: call noundef nonnull align {{[0-9]+}} dereferenceable({{[0-9]+}}) %struct.TFENode* bitcast (i8* (i8*, i8*, ...)* @objc_msgSend -// CHECK-NEXT: call void @_ZNK7TFENode6GetURLEv(%struct.TFENode* {{[^,]*}} %{{.*}}) +// CHECK: call noundef nonnull align {{[0-9]+}} dereferenceable({{[0-9]+}}) ptr @objc_msgSend +// CHECK-NEXT: call void @_ZNK7TFENode6GetURLEv(ptr {{[^,]*}} %{{.*}}) self.node.GetURL(); } // expected-warning {{non-void function does not return a value}} @end @@ -27,12 +27,12 @@ @interface A - (const X&) target; @end void f1(A *a) { -// CHECK: [[PRP:%.*]] = call noundef nonnull align {{[0-9]+}} dereferenceable({{[0-9]+}}) %struct.X* bitcast (i8* (i8*, i8*, ...)* @objc_msgSend -// CHECK-NEXT:call void @_Z2f0RK1X(%struct.X* noundef nonnull align {{[0-9]+}} dereferenceable({{[0-9]+}}) [[PRP]]) +// CHECK: [[PRP:%.*]] = call noundef nonnull align {{[0-9]+}} dereferenceable({{[0-9]+}}) ptr @objc_msgSend +// CHECK-NEXT:call void @_Z2f0RK1X(ptr noundef nonnull align {{[0-9]+}} dereferenceable({{[0-9]+}}) [[PRP]]) f0(a.target); -// CHECK: [[MSG:%.*]] = call noundef nonnull align {{[0-9]+}} dereferenceable({{[0-9]+}}) %struct.X* bitcast (i8* (i8*, i8*, ...)* @objc_msgSend -// CHECK-NEXT:call void @_Z2f0RK1X(%struct.X* noundef nonnull align {{[0-9]+}} dereferenceable({{[0-9]+}}) [[MSG]]) +// CHECK: [[MSG:%.*]] = call noundef nonnull align {{[0-9]+}} dereferenceable({{[0-9]+}}) ptr @objc_msgSend +// CHECK-NEXT:call void @_Z2f0RK1X(ptr noundef nonnull align {{[0-9]+}} dereferenceable({{[0-9]+}}) [[MSG]]) f0([a target]); } @@ -51,12 +51,12 @@ void test2() { void(obj.myGetter); } // CHECK-LABEL: define{{.*}} void @_Z5test2v() -// CHECK: call noundef i32 bitcast -// CHECK: call noundef double bitcast -// CHECK: call noundef i32 bitcast -// CHECK: call noundef double bitcast -// CHECK: call noundef i32 bitcast -// CHECK: call noundef double bitcast +// CHECK: call noundef i32 +// CHECK: call noundef double +// CHECK: call noundef i32 +// CHECK: call noundef double +// CHECK: call noundef i32 +// CHECK: call noundef double // PR8751 int test3(Test2 *obj) { return obj.myProperty; } diff --git a/clang/test/CodeGenObjCXX/property-lvalue-lambda.mm b/clang/test/CodeGenObjCXX/property-lvalue-lambda.mm index 1253ae6d45b04..ddb0bf5570926 100644 --- a/clang/test/CodeGenObjCXX/property-lvalue-lambda.mm +++ b/clang/test/CodeGenObjCXX/property-lvalue-lambda.mm @@ -1,4 +1,4 @@ -// RUN: %clang_cc1 -no-opaque-pointers -no-enable-noundef-analysis -fblocks -disable-llvm-passes -triple x86_64-apple-darwin10 -std=c++17 -emit-llvm -o - %s | FileCheck %s +// RUN: %clang_cc1 -no-enable-noundef-analysis -fblocks -disable-llvm-passes -triple x86_64-apple-darwin10 -std=c++17 -emit-llvm -o - %s | FileCheck %s typedef void (^blk_t)(); typedef void (*fnptr_t)(); @@ -19,12 +19,12 @@ void t1(X *x) { // Check that we call lambda.operator blk_t(), and that we send that result to // the setter. - // CHECK: [[CALL:%.*]] = call void ()* @"_ZZ2t1P1XENK3$_0cvU13block_pointerFvvEEv" - // CHECK: call void{{.*}}@objc_msgSend{{.*}}({{.*}} void ()* [[CALL]]) + // CHECK: [[CALL:%.*]] = call ptr @"_ZZ2t1P1XENK3$_0cvU13block_pointerFvvEEv" + // CHECK: call void{{.*}}@objc_msgSend{{.*}}({{.*}} ptr [[CALL]]) x.blk = [] {}; - // CHECK: [[CALL2:%.*]] = call void ()* @"_ZZ2t1P1XENK3$_1cvPFvvEEv" - // CHECK: call void{{.*}}@objc_msgSend{{.*}}({{.*}} void ()* [[CALL2]]) + // CHECK: [[CALL2:%.*]] = call ptr @"_ZZ2t1P1XENK3$_1cvPFvvEEv" + // CHECK: call void{{.*}}@objc_msgSend{{.*}}({{.*}} ptr [[CALL2]]) x.fnptr = [] {}; } @@ -35,13 +35,13 @@ void t2(X *x) { // [x setBlk: operator+([x blk], [] {})] - // CHECK: call void{{.*}}@objc_msgSend{{.*}} - // CHECK: [[PLUS:%.*]] = call void ()* @"_ZplIZ2t2P1XE3$_0EU13block_pointerFvvES4_T_" + // CHECK: call ptr{{.*}}@objc_msgSend{{.*}} + // CHECK: [[PLUS:%.*]] = call ptr @"_ZplIZ2t2P1XE3$_0EU13block_pointerFvvES4_T_" // CHECK: call void{{.*}}@objc_msgSend{{.*}}({{.*}} [[PLUS]]) x.blk += [] {}; - // CHECK: call void{{.*}}@objc_msgSend{{.*}} - // CHECK: [[PLUS:%.*]] = call void ()* @"_ZplIZ2t2P1XE3$_1EPFvvES4_T_" + // CHECK: call ptr{{.*}}@objc_msgSend{{.*}} + // CHECK: [[PLUS:%.*]] = call ptr @"_ZplIZ2t2P1XE3$_1EPFvvES4_T_" // CHECK: call void{{.*}}@objc_msgSend{{.*}}({{.*}} [[PLUS]]) x.fnptr += [] {}; } diff --git a/clang/test/CodeGenObjCXX/property-object-conditional-exp.mm b/clang/test/CodeGenObjCXX/property-object-conditional-exp.mm index 3fb75d9a3e41e..892f46f5733a2 100644 --- a/clang/test/CodeGenObjCXX/property-object-conditional-exp.mm +++ b/clang/test/CodeGenObjCXX/property-object-conditional-exp.mm @@ -1,4 +1,4 @@ -// RUN: %clang_cc1 -no-opaque-pointers -triple x86_64-apple-darwin10 -fobjc-runtime=macosx-fragile-10.5 -emit-llvm -o - %s | FileCheck %s +// RUN: %clang_cc1 -triple x86_64-apple-darwin10 -fobjc-runtime=macosx-fragile-10.5 -emit-llvm -o - %s | FileCheck %s struct CGRect { char* origin; @@ -22,12 +22,11 @@ - (void)bar { CGRect dataRect; CGRect virtualBounds; -// CHECK: [[SRC:%.*]] = call { i8*, i32 } bitcast (i8* (i8*, i8*, ...)* @objc_msgSend -// CHECK-NEXT: bitcast -// CHECK-NEXT:getelementptr inbounds { i8*, i32 }, { i8*, i32 }* [[SRC:%.*]] +// CHECK: [[SRC:%.*]] = call { ptr, i32 } @objc_msgSend +// CHECK-NEXT:getelementptr inbounds { ptr, i32 }, ptr [[SRC:%.*]] // CHECK-NEXT:extractvalue // CHECK-NEXT:store -// CHECK-NEXT:getelementptr inbounds { i8*, i32 }, { i8*, i32 }* [[SRC:%.*]] +// CHECK-NEXT:getelementptr inbounds { ptr, i32 }, ptr [[SRC:%.*]] // CHECK-NEXT:extractvalue // CHECK-NEXT:store dataRect = CGRectIsEmpty(virtualBounds) ? self.bounds : virtualBounds; diff --git a/clang/test/CodeGenObjCXX/property-object-reference-1.mm b/clang/test/CodeGenObjCXX/property-object-reference-1.mm index 7830b12f6e98c..ccbbec388362f 100644 --- a/clang/test/CodeGenObjCXX/property-object-reference-1.mm +++ b/clang/test/CodeGenObjCXX/property-object-reference-1.mm @@ -1,4 +1,4 @@ -// RUN: %clang_cc1 -no-opaque-pointers -x objective-c++ %s -triple x86_64-apple-darwin10 -emit-llvm -o - | FileCheck %s +// RUN: %clang_cc1 -x objective-c++ %s -triple x86_64-apple-darwin10 -emit-llvm -o - | FileCheck %s // rdar://6137845 struct TCPPObject @@ -24,8 +24,7 @@ @implementation MyDocument @end -// CHECK: [[cppObjectaddr:%.*]] = alloca %struct.TCPPObject*, align 8 -// CHECK: store %struct.TCPPObject* [[cppObject:%.*]], %struct.TCPPObject** [[cppObjectaddr]], align 8 -// CHECK: [[THREE:%.*]] = load %struct.TCPPObject*, %struct.TCPPObject** [[cppObjectaddr]], align 8 -// CHECK: [[FOUR:%.*]] = bitcast %struct.TCPPObject* [[THREE]] to i8* -// CHECK: call void @objc_copyStruct(i8* noundef [[TWO:%.*]], i8* noundef [[FOUR]], i64 noundef 256, i1 noundef zeroext true, i1 noundef zeroext false) +// CHECK: [[cppObjectaddr:%cppObject.addr]] = alloca ptr, align 8 +// CHECK: store ptr [[cppObject:%.*]], ptr [[cppObjectaddr]], align 8 +// CHECK: [[THREE:%.*]] = load ptr, ptr [[cppObjectaddr]], align 8 +// CHECK: call void @objc_copyStruct(ptr noundef [[TWO:%.*]], ptr noundef [[THREE]], i64 noundef 256, i1 noundef zeroext true, i1 noundef zeroext false) diff --git a/clang/test/CodeGenObjCXX/property-object-reference.mm b/clang/test/CodeGenObjCXX/property-object-reference.mm index 12449b867a863..f31371cf5231f 100644 --- a/clang/test/CodeGenObjCXX/property-object-reference.mm +++ b/clang/test/CodeGenObjCXX/property-object-reference.mm @@ -1,4 +1,4 @@ -// RUN: %clang_cc1 -no-opaque-pointers %s -triple x86_64-apple-darwin10 -fobjc-runtime=macosx-fragile-10.5 -emit-llvm -o - | FileCheck %s +// RUN: %clang_cc1 %s -triple x86_64-apple-darwin10 -fobjc-runtime=macosx-fragile-10.5 -emit-llvm -o - | FileCheck %s // rdar://10188258 struct Foo {int i;}; @@ -24,12 +24,10 @@ -(void) test { - (void)setFooProperty : (Foo &) arg { }; @end -// CHECK: [[T0:%.*]] = load {{%.*}} [[S0:%.*]] -// CHECK: [[T2:%.*]] = bitcast {{%.*}} [[T0]] to i8* -// CHECK: load i8*, i8** @OBJC_SELECTOR_REFERENCES_ +// CHECK: [[T0:%.*]] = load {{.*}} [[S0:%.*]] +// CHECK: load ptr, ptr @OBJC_SELECTOR_REFERENCES_ // CHECK: @objc_msgSend -// CHECK: [[R0:%.*]] = load {{%.*}} [[U0:%.*]] -// CHECK: [[R2:%.*]] = bitcast {{%.*}} [[R0]] to i8* -// CHECK: load i8*, i8** @OBJC_SELECTOR_REFERENCES_ +// CHECK: [[R0:%.*]] = load {{.*}} [[U0:%.*]] +// CHECK: load ptr, ptr @OBJC_SELECTOR_REFERENCES_ // CHECK: @objc_msgSend diff --git a/clang/test/CodeGenObjCXX/property-objects.mm b/clang/test/CodeGenObjCXX/property-objects.mm index 5c6e87796a559..5ef535f48a4ae 100644 --- a/clang/test/CodeGenObjCXX/property-objects.mm +++ b/clang/test/CodeGenObjCXX/property-objects.mm @@ -1,4 +1,4 @@ -// RUN: %clang_cc1 -no-opaque-pointers %s -triple=x86_64-apple-darwin10 -std=c++11 -emit-llvm -debug-info-kind=limited -o - | FileCheck %s +// RUN: %clang_cc1 %s -triple=x86_64-apple-darwin10 -std=c++11 -emit-llvm -debug-info-kind=limited -o - | FileCheck %s class S { public: @@ -32,7 +32,7 @@ @implementation I @synthesize frame; // CHECK: define internal void @"\01-[I setPosition:]" -// CHECK: call noundef nonnull align {{[0-9]+}} dereferenceable({{[0-9]+}}) %class.S* @_ZN1SaSERKS_ +// CHECK: call noundef nonnull align {{[0-9]+}} dereferenceable({{[0-9]+}}) ptr @_ZN1SaSERKS_ // CHECK-NEXT: ret void // Don't attach debug locations to the prologue instructions. These were @@ -60,8 +60,8 @@ - (struct CGRect)extent {return bounds;} @end // CHECK-LABEL: define{{.*}} i32 @main -// CHECK: call void @_ZN1SC1ERKS_(%class.S* {{[^,]*}} [[AGGTMP:%[a-zA-Z0-9\.]+]], %class.S* noundef nonnull align {{[0-9]+}} dereferenceable({{[0-9]+}}) {{%[a-zA-Z0-9\.]+}}) -// CHECK: call void bitcast (i8* (i8*, i8*, ...)* @objc_msgSend to void (i8*, i8*, %class.S*)*)(i8* noundef {{%[a-zA-Z0-9\.]+}}, i8* noundef {{%[a-zA-Z0-9\.]+}}, %class.S* noundef [[AGGTMP]]) +// CHECK: call void @_ZN1SC1ERKS_(ptr {{[^,]*}} [[AGGTMP:%[a-zA-Z0-9\.]+]], ptr noundef nonnull align {{[0-9]+}} dereferenceable({{[0-9]+}}) {{%[a-zA-Z0-9\.]+}}) +// CHECK: call void @objc_msgSend(ptr noundef {{%[a-zA-Z0-9\.]+}}, ptr noundef {{%[a-zA-Z0-9\.]+}}, ptr noundef [[AGGTMP]]) // CHECK-NEXT: ret i32 0 int main() { I *i; @@ -72,9 +72,9 @@ int main() { // rdar://8379892 // CHECK-LABEL: define{{.*}} void @_Z1fP1A -// CHECK: call void @_ZN1XC1Ev(%struct.X* {{[^,]*}} [[LVTEMP:%[a-zA-Z0-9\.]+]]) -// CHECK: call void @_ZN1XC1ERKS_(%struct.X* {{[^,]*}} [[AGGTMP:%[a-zA-Z0-9\.]+]], %struct.X* noundef nonnull align {{[0-9]+}} dereferenceable({{[0-9]+}}) [[LVTEMP]]) -// CHECK: call void bitcast (i8* (i8*, i8*, ...)* @objc_msgSend to void (i8*, i8*, %struct.X*)*)({{.*}} %struct.X* noundef [[AGGTMP]]) +// CHECK: call void @_ZN1XC1Ev(ptr {{[^,]*}} [[LVTEMP:%[a-zA-Z0-9\.]+]]) +// CHECK: call void @_ZN1XC1ERKS_(ptr {{[^,]*}} [[AGGTMP:%[a-zA-Z0-9\.]+]], ptr noundef nonnull align {{[0-9]+}} dereferenceable({{[0-9]+}}) [[LVTEMP]]) +// CHECK: call void @objc_msgSend({{.*}} ptr noundef [[AGGTMP]]) struct X { X(); X(const X&); @@ -116,32 +116,32 @@ void testB0(B *b) { void testB1(B *b) { b.b1 += { b_makeInt() }; } -// CHECK: define{{.*}} void @_Z6testB0P1B([[B:%.*]]* -// CHECK: [[BVAR:%.*]] = alloca [[B]]*, align 8 +// CHECK: define{{.*}} void @_Z6testB0P1B(ptr +// CHECK: [[BVAR:%.*]] = alloca ptr, align 8 // CHECK: [[TEMP:%.*]] = alloca [[B0:%.*]], align 8 -// CHECK: [[X:%.*]] = getelementptr inbounds [[B0]], [[B0]]* [[TEMP]], i32 0, i32 0 +// CHECK: [[X:%.*]] = getelementptr inbounds [[B0]], ptr [[TEMP]], i32 0, i32 0 // CHECK-NEXT: [[T0:%.*]] = call noundef i32 @_Z9b_makeIntv() // CHECK-NEXT: [[T1:%.*]] = sext i32 [[T0]] to i64 -// CHECK-NEXT: store i64 [[T1]], i64* [[X]], align 8 -// CHECK: load [[B]]*, [[B]]** [[BVAR]] +// CHECK-NEXT: store i64 [[T1]], ptr [[X]], align 8 +// CHECK: load ptr, ptr [[BVAR]] // CHECK-NOT: call // CHECK: call void @llvm.memcpy // CHECK-NOT: call -// CHECK: call void bitcast {{.*}} @objc_msgSend +// CHECK: call void @objc_msgSend // CHECK-NOT: call // CHECK: ret void -// CHECK: define{{.*}} void @_Z6testB1P1B([[B]]* -// CHECK: [[BVAR:%.*]] = alloca [[B]]*, align 8 -// CHECK: load [[B]]*, [[B]]** [[BVAR]] +// CHECK: define{{.*}} void @_Z6testB1P1B(ptr +// CHECK: [[BVAR:%.*]] = alloca ptr, align 8 +// CHECK: load ptr, ptr [[BVAR]] // CHECK-NOT: call -// CHECK: [[T0:%.*]] = call i64 bitcast {{.*}} @objc_msgSend +// CHECK: [[T0:%.*]] = call i64 @objc_msgSend // CHECK-NOT: call // CHECK: store i64 [[T0]], // CHECK-NOT: call // CHECK: [[T0:%.*]] = call noundef i32 @_Z9b_makeIntv() // CHECK-NEXT: [[T1:%.*]] = sext i32 [[T0]] to i64 -// CHECK-NEXT: store i64 [[T1]], i64* {{.*}}, align 8 +// CHECK-NEXT: store i64 [[T1]], ptr {{.*}}, align 8 // CHECK-NOT: call // CHECK: [[T0:%.*]] = call i64 @_Zpl2B1S_ // CHECK-NOT: call @@ -149,7 +149,7 @@ void testB1(B *b) { // CHECK-NOT: call // CHECK: call void @llvm.memcpy // CHECK-NOT: call -// CHECK: call void bitcast {{.*}} @objc_msgSend +// CHECK: call void @objc_msgSend // CHECK-NOT: call // CHECK: ret void @@ -159,18 +159,18 @@ void testB2(B *b) { b.b2 = { B3() }; } -// CHECK: define{{.*}} void @_Z6testB2P1B([[B]]* -// CHECK: [[BVAR:%.*]] = alloca [[B]]*, align 8 +// CHECK: define{{.*}} void @_Z6testB2P1B(ptr +// CHECK: [[BVAR:%.*]] = alloca ptr, align 8 // CHECK: call void @llvm.dbg.declare( // CHECK: call void @_ZN2B3C1Ev( // CHECK-NEXT: [[T0:%.*]] = call i64 @_ZN2B3cv2B1Ev( // CHECK-NOT: call // CHECK: store i64 [[T0]], -// CHECK: load [[B]]*, [[B]]** [[BVAR]] +// CHECK: load ptr, ptr [[BVAR]] // CHECK-NOT: call // CHECK: call void @llvm.memcpy // CHECK-NOT: call -// CHECK: call void bitcast {{.*}} @objc_msgSend +// CHECK: call void @objc_msgSend // CHECK-NOT: call // CHECK: ret void @@ -191,24 +191,24 @@ void testC0(C *c) { c.c0 = c_helper; c.c0 = &c_helper; } -// CHECK: define{{.*}} void @_Z6testC0P1C([[C:%.*]]* -// CHECK: [[CVAR:%.*]] = alloca [[C]]*, align 8 -// CHECK: load [[C]]*, [[C]]** [[CVAR]] +// CHECK: define{{.*}} void @_Z6testC0P1C(ptr +// CHECK: [[CVAR:%.*]] = alloca ptr, align 8 +// CHECK: load ptr, ptr [[CVAR]] // CHECK-NOT: call -// CHECK: call void bitcast {{.*}} @objc_msgSend {{.*}} @_Z8c_helperv +// CHECK: call void @objc_msgSend({{.*}} @_Z8c_helperv // CHECK-NOT: call -// CHECK: call void bitcast {{.*}} @objc_msgSend {{.*}} @_Z8c_helperv +// CHECK: call void @objc_msgSend({{.*}} @_Z8c_helperv // CHECK-NOT: call // CHECK: ret void void testC1(C *c) { c.c1 += c_helper; } -// CHECK: define{{.*}} void @_Z6testC1P1C([[C]]* -// CHECK: [[CVAR:%.*]] = alloca [[C]]*, align 8 -// CHECK: load [[C]]*, [[C]]** [[CVAR]] +// CHECK: define{{.*}} void @_Z6testC1P1C(ptr +// CHECK: [[CVAR:%.*]] = alloca ptr, align 8 +// CHECK: load ptr, ptr [[CVAR]] // CHECK-NOT: call -// CHECK: [[T0:%.*]] = call i32 bitcast {{.*}} @objc_msgSend +// CHECK: [[T0:%.*]] = call i32 @objc_msgSend // CHECK-NOT: call // CHECK: store i32 [[T0]], // CHECK-NOT: call @@ -218,6 +218,6 @@ void testC1(C *c) { // CHECK-NOT: call // CHECK: call void @llvm.memcpy // CHECK-NOT: call -// CHECK: call void bitcast {{.*}} @objc_msgSend +// CHECK: call void @objc_msgSend // CHECK-NOT: call // CHECK: ret void diff --git a/clang/test/CodeGenObjCXX/property-reference.mm b/clang/test/CodeGenObjCXX/property-reference.mm index c07ecd9a95548..43d7570b545ce 100644 --- a/clang/test/CodeGenObjCXX/property-reference.mm +++ b/clang/test/CodeGenObjCXX/property-reference.mm @@ -1,4 +1,4 @@ -// RUN: %clang_cc1 -no-opaque-pointers %s -triple x86_64-apple-darwin10 -fobjc-runtime=macosx-fragile-10.5 -emit-llvm -o - | FileCheck %s +// RUN: %clang_cc1 %s -triple x86_64-apple-darwin10 -fobjc-runtime=macosx-fragile-10.5 -emit-llvm -o - | FileCheck %s // rdar://9208606 struct MyStruct { @@ -26,8 +26,8 @@ void test0() { const MyStruct& currentMyStruct = myClass.foo; } -// CHECK: [[C:%.*]] = call noundef nonnull align {{[0-9]+}} dereferenceable({{[0-9]+}}) %struct.MyStruct* bitcast (i8* (i8*, i8*, ...)* @objc_msgSend -// CHECK: store %struct.MyStruct* [[C]], %struct.MyStruct** [[D:%.*]] +// CHECK: [[C:%.*]] = call noundef nonnull align {{[0-9]+}} dereferenceable({{[0-9]+}}) ptr @objc_msgSend +// CHECK: store ptr [[C]], ptr [[D:%.*]] namespace test1 { struct A { A(); A(const A&); A&operator=(const A&); ~A(); }; @@ -40,16 +40,14 @@ @interface Test1 { @implementation Test1 @synthesize prop1 = ivar; @end -// CHECK: define internal noundef nonnull align {{[0-9]+}} dereferenceable({{[0-9]+}}) [[A:%.*]]* @"\01-[Test1 prop1]"( -// CHECK: [[SELF:%.*]] = alloca [[TEST1:%.*]]*, align 8 -// CHECK: [[T0:%.*]] = load [[TEST1]]*, [[TEST1]]** [[SELF]] -// CHECK-NEXT: [[T1:%.*]] = bitcast [[TEST1]]* [[T0]] to i8* -// CHECK-NEXT: [[T2:%.*]] = getelementptr inbounds i8, i8* [[T1]], i64 0 -// CHECK-NEXT: [[T3:%.*]] = bitcast i8* [[T2]] to [[A]]* -// CHECK-NEXT: ret [[A]]* [[T3]] +// CHECK: define internal noundef nonnull align {{[0-9]+}} dereferenceable({{[0-9]+}}) ptr @"\01-[Test1 prop1]"( +// CHECK: [[SELF:%.*]] = alloca ptr, align 8 +// CHECK: [[T0:%.*]] = load ptr, ptr [[SELF]] +// CHECK-NEXT: [[T2:%.*]] = getelementptr inbounds i8, ptr [[T0]], i64 0 +// CHECK-NEXT: ret ptr [[T2]] // CHECK: define internal void @"\01-[Test1 setProp1:]"( -// CHECK: call noundef nonnull align {{[0-9]+}} dereferenceable({{[0-9]+}}) [[A]]* @_ZN5test11AaSERKS0_( +// CHECK: call noundef nonnull align {{[0-9]+}} dereferenceable({{[0-9]+}}) ptr @_ZN5test11AaSERKS0_( // CHECK-NEXT: ret void // rdar://problem/10497174 @@ -67,11 +65,11 @@ @interface Test2 // CHECK-LABEL: define weak_odr void @_Z5test2IiEvP5Test2( // CHECK: [[X:%.*]] = alloca i32, // CHECK: @objc_msgSend -// CHECK: store i32 {{%.*}}, i32* [[X]], -// CHECK: load i32, i32* [[X]], +// CHECK: store i32 {{%.*}}, ptr [[X]], +// CHECK: load i32, ptr [[X]], // CHECK: @objc_msgSend // CHECK: @objc_msgSend -// CHECK: load i32, i32* [[X]], +// CHECK: load i32, ptr [[X]], // CHECK-NEXT: add nsw // CHECK: @objc_msgSend // CHECK-NEXT: ret void @@ -86,11 +84,11 @@ @interface Test2 // CHECK-LABEL: define weak_odr void @_Z5test3IiEvP5Test2( // CHECK: [[X:%.*]] = alloca i32, // CHECK: @objc_msgSend -// CHECK: store i32 {{%.*}}, i32* [[X]], -// CHECK: load i32, i32* [[X]], +// CHECK: store i32 {{%.*}}, ptr [[X]], +// CHECK: load i32, ptr [[X]], // CHECK: @objc_msgSend // CHECK: @objc_msgSend -// CHECK: load i32, i32* [[X]], +// CHECK: load i32, ptr [[X]], // CHECK-NEXT: add nsw // CHECK: @objc_msgSend // CHECK-NEXT: ret void diff --git a/clang/test/Driver/aix-as.c b/clang/test/Driver/aix-as.c index 9412604c2e84f..c6aeae4c10183 100644 --- a/clang/test/Driver/aix-as.c +++ b/clang/test/Driver/aix-as.c @@ -1,22 +1,40 @@ // General tests that as(1) invocations on AIX targets are sane. Note that we // only test assembler functionalities in this suite. +// Check powerpc-ibm-aix7.1.0.0, system assembler is used for assembly files, 32-bit. +// RUN: %clang -x assembler %s -### -c -fintegrated-as 2>&1 \ +// RUN: --target=powerpc-ibm-aix7.1.0.0 \ +// RUN: | FileCheck --check-prefix=CHECK-AS32 %s +// +// RUN: %clang -x assembler %s -### -c 2>&1 -fno-integrated-as \ +// RUN: --target=powerpc-ibm-aix7.1.0.0 \ +// RUN: | FileCheck --check-prefix=CHECK-AS32 %s + // Check powerpc-ibm-aix7.1.0.0, 32-bit. // RUN: %clang %s -### -c 2>&1 \ // RUN: --target=powerpc-ibm-aix7.1.0.0 \ -// RUN: | FileCheck --check-prefix=CHECK-AS32 %s +// RUN: | FileCheck --check-prefixes=CHECK-AS32,CHECK-AS32-CC1 %s // CHECK-AS32-NOT: warning: -// CHECK-AS32: "-cc1" "-triple" "powerpc-ibm-aix7.1.0.0" +// CHECK-AS32-CC1: "-cc1" "-triple" "powerpc-ibm-aix7.1.0.0" // CHECK-AS32: "{{.*}}as{{(.exe)?}}" // CHECK-AS32: "-a32" // CHECK-AS32: "-many" +// Check powerpc64-ibm-aix7.1.0.0, system assembler is used for assembly files, 64-bit. +// RUN: %clang -x assembler %s -### -c -fintegrated-as 2>&1 \ +// RUN: --target=powerpc64-ibm-aix7.1.0.0 \ +// RUN: | FileCheck --check-prefix=CHECK-AS64 %s +// +// RUN: %clang -x assembler %s -### -c -fno-integrated-as 2>&1 \ +// RUN: --target=powerpc64-ibm-aix7.1.0.0 \ +// RUN: | FileCheck --check-prefix=CHECK-AS64 %s + // Check powerpc64-ibm-aix7.1.0.0, 64-bit. // RUN: %clang %s -### -c 2>&1 \ // RUN: --target=powerpc64-ibm-aix7.1.0.0 \ -// RUN: | FileCheck --check-prefix=CHECK-AS64 %s +// RUN: | FileCheck --check-prefixes=CHECK-AS64,CHECK-AS64-CC1 %s // CHECK-AS64-NOT: warning: -// CHECK-AS64: "-cc1" "-triple" "powerpc64-ibm-aix7.1.0.0" +// CHECK-AS64-CC1: "-cc1" "-triple" "powerpc64-ibm-aix7.1.0.0" // CHECK-AS64: "{{.*}}as{{(.exe)?}}" // CHECK-AS64: "-a64" // CHECK-AS64: "-many" diff --git a/clang/test/Driver/arclite-link-external-toolchain.c b/clang/test/Driver/arclite-link-external-toolchain.c index cc62cd1a48445..8391a8507d8f8 100644 --- a/clang/test/Driver/arclite-link-external-toolchain.c +++ b/clang/test/Driver/arclite-link-external-toolchain.c @@ -4,5 +4,8 @@ // RUN: -isysroot %t.tmpdir/Xcode.app/Contents/Developers/Platforms/MacOSX.platform/Developer/SDKs/MacOSX10.14.sdk \ // RUN: %s 2>&1 | FileCheck %s +// CHECK: error: SDK does not contain 'libarclite' at the path ' +// CHECK: .tmpdir/Xcode.app/{{.*}}libarclite_macosx.a'; +// CHECK: try increasing the minimum deployment target // CHECK: -lfoo // CHECK: .tmpdir/Xcode.app/{{.*}}libarclite_macosx.a diff --git a/clang/test/Driver/arclite-link.c b/clang/test/Driver/arclite-link.c index e8cee3e042d3e..595ca0b538eec 100644 --- a/clang/test/Driver/arclite-link.c +++ b/clang/test/Driver/arclite-link.c @@ -1,9 +1,13 @@ // RUN: touch %t.o -// RUN: %clang -### -target x86_64-apple-darwin10 -fobjc-link-runtime -lfoo -mmacosx-version-min=10.10 %t.o 2>&1 | FileCheck -check-prefix=CHECK-ARCLITE-OSX %s +// RUN: mkdir -p %t.tmpdir/Xcode.app/Contents/Developers/Platforms/MacOSX.platform/Developer/SDKs/MacOSX10.14.sdk +// RUN: %clang -### -target x86_64-apple-darwin10 -fobjc-link-runtime -lfoo -mmacosx-version-min=10.10 %t.o \ +// RUN: -isysroot %t.tmpdir/Xcode.app/Contents/Developers/Platforms/MacOSX.platform/Developer/SDKs/MacOSX10.14.sdk 2>&1 | FileCheck -check-prefix=CHECK-ARCLITE-OSX %s // RUN: %clang -### -target x86_64-apple-darwin10 -fobjc-link-runtime -mmacosx-version-min=10.11 %t.o 2>&1 | FileCheck -check-prefix=CHECK-NOARCLITE %s // RUN: %clang -### -target i386-apple-darwin10 -fobjc-link-runtime -mmacosx-version-min=10.7 %t.o 2>&1 | FileCheck -check-prefix=CHECK-NOARCLITE %s // RUN: %clang -### -target x86_64-apple-darwin10 -fobjc-link-runtime -nostdlib %t.o 2>&1 | FileCheck -check-prefix=CHECK-NOSTDLIB %s +// CHECK-ARCLITE-OSX: .tmpdir/Xcode.app/{{.*}}libarclite_macosx.a'; +// CHECK-ARCLITE-OSX: try increasing the minimum deployment target // CHECK-ARCLITE-OSX: -lfoo // CHECK-ARCLITE-OSX: libarclite_macosx.a // CHECK-ARCLITE-OSX: -framework diff --git a/clang/test/Driver/as-version.s b/clang/test/Driver/as-version.s index a96b2b5762c65..5003819372be2 100644 --- a/clang/test/Driver/as-version.s +++ b/clang/test/Driver/as-version.s @@ -1,6 +1,6 @@ // Test version information. -// UNSUPPORTED: target={{.*}}-zos{{.*}} +// UNSUPPORTED: target={{.*}}-zos{{.*}}, target={{.*}}-aix{{.*}} // RUN: %clang -Wa,--version -c -fintegrated-as %s -o /dev/null \ // RUN: | FileCheck --check-prefix=IAS %s // IAS: clang version diff --git a/clang/test/Driver/clang_f_opts.c b/clang/test/Driver/clang_f_opts.c index 67ec82a09f852..8060e52d5e8fd 100644 --- a/clang/test/Driver/clang_f_opts.c +++ b/clang/test/Driver/clang_f_opts.c @@ -517,15 +517,6 @@ // CHECK-CF-PROTECTION-BRANCH: -fcf-protection=branch // CHECK-NO-CF-PROTECTION-BRANCH-NOT: -fcf-protection=branch -// RUN: %clang -### -S -fdebug-compilation-dir . %s 2>&1 | FileCheck -check-prefix=CHECK-DEBUG-COMPILATION-DIR %s -// RUN: %clang -### -S -fdebug-compilation-dir=. %s 2>&1 | FileCheck -check-prefix=CHECK-DEBUG-COMPILATION-DIR %s -// RUN: %clang -### -integrated-as -fdebug-compilation-dir . -x assembler %s 2>&1 | FileCheck -check-prefix=CHECK-DEBUG-COMPILATION-DIR %s -// RUN: %clang -### -integrated-as -fdebug-compilation-dir=. -x assembler %s 2>&1 | FileCheck -check-prefix=CHECK-DEBUG-COMPILATION-DIR %s -// RUN: %clang -### -S -ffile-compilation-dir=. %s 2>&1 | FileCheck -check-prefix=CHECK-DEBUG-COMPILATION-DIR %s -// RUN: %clang -### -integrated-as -ffile-compilation-dir=. -x assembler %s 2>&1 | FileCheck -check-prefixes=CHECK-DEBUG-COMPILATION-DIR %s -// CHECK-DEBUG-COMPILATION-DIR: "-fdebug-compilation-dir=." -// CHECK-DEBUG-COMPILATION-DIR-NOT: "-ffile-compilation-dir=." - // RUN: %clang -### -S -fprofile-instr-generate -fcoverage-compilation-dir=. %s 2>&1 | FileCheck -check-prefix=CHECK-COVERAGE-COMPILATION-DIR %s // RUN: %clang -### -S -fprofile-instr-generate -ffile-compilation-dir=. %s 2>&1 | FileCheck -check-prefix=CHECK-COVERAGE-COMPILATION-DIR %s // CHECK-COVERAGE-COMPILATION-DIR: "-fcoverage-compilation-dir=." diff --git a/clang/test/Driver/compilation-dir.c b/clang/test/Driver/compilation-dir.c new file mode 100644 index 0000000000000..dbe801c9f5fcb --- /dev/null +++ b/clang/test/Driver/compilation-dir.c @@ -0,0 +1,10 @@ +// XFAIL: target={{.*}}-aix{{.*}} + +// RUN: %clang -### -S -fdebug-compilation-dir . %s 2>&1 | FileCheck -check-prefix=CHECK-DEBUG-COMPILATION-DIR %s +// RUN: %clang -### -S -fdebug-compilation-dir=. %s 2>&1 | FileCheck -check-prefix=CHECK-DEBUG-COMPILATION-DIR %s +// RUN: %clang -### -integrated-as -fdebug-compilation-dir . -x assembler %s 2>&1 | FileCheck -check-prefix=CHECK-DEBUG-COMPILATION-DIR %s +// RUN: %clang -### -integrated-as -fdebug-compilation-dir=. -x assembler %s 2>&1 | FileCheck -check-prefix=CHECK-DEBUG-COMPILATION-DIR %s +// RUN: %clang -### -S -ffile-compilation-dir=. %s 2>&1 | FileCheck -check-prefix=CHECK-DEBUG-COMPILATION-DIR %s +// RUN: %clang -### -integrated-as -ffile-compilation-dir=. -x assembler %s 2>&1 | FileCheck -check-prefixes=CHECK-DEBUG-COMPILATION-DIR %s +// CHECK-DEBUG-COMPILATION-DIR: "-fdebug-compilation-dir=." +// CHECK-DEBUG-COMPILATION-DIR-NOT: "-ffile-compilation-dir=." diff --git a/clang/test/Driver/compress-unavailable.s b/clang/test/Driver/compress-unavailable.s index e44fcb4ce9d5e..de422fb088b7d 100644 --- a/clang/test/Driver/compress-unavailable.s +++ b/clang/test/Driver/compress-unavailable.s @@ -1,3 +1,5 @@ +// XFAIL: target={{.*}}-aix{{.*}} + // RUN: %clang -### -fintegrated-as -gz=none -c %s 2>&1 | FileCheck %s --check-prefix=NOWARN // NOWARN-NOT: warning: cannot compress debug sections (zlib not enabled) diff --git a/clang/test/Driver/cspgo-lto.c b/clang/test/Driver/cspgo-lto.c index d793400889d85..232d21bbf948a 100644 --- a/clang/test/Driver/cspgo-lto.c +++ b/clang/test/Driver/cspgo-lto.c @@ -4,3 +4,17 @@ // RUN: -fprofile-use 2>&1 | FileCheck %s // CHECK: -plugin-opt=cs-profile-path=default.profdata + +// RUN: %clang --target=apple-arm64-ios -### %t.o -flto=thin -fuse-ld=lld -B%S/Inputs/lld -fprofile-use 2>&1 | FileCheck %s --check-prefix=DARWIN-USE1 +// RUN: %clang --target=apple-arm64-ios -### %t.o -flto=thin -fuse-ld=lld -B%S/Inputs/lld -fprofile-use=a.profdata 2>&1 | FileCheck %s --check-prefix=DARWIN-USE2 + +// DARWIN-USE1: "--cs-profile-path=default.profdata" +// DARWIN-USE2: "--cs-profile-path=a.profdata" + +// RUN: %clang --target=apple-arm64-ios -### %t.o -flto=thin -fuse-ld=lld -B%S/Inputs/lld -fcs-profile-generate 2>&1 | FileCheck %s --check-prefix=DARWIN-GEN1 +// RUN: %clang --target=apple-arm64-ios -### %t.o -flto=thin -fuse-ld=lld -B%S/Inputs/lld -fcs-profile-generate=directory 2>&1 | FileCheck %s --check-prefix=DARWIN-GEN2 + +// DARWIN-GEN1: "--cs-profile-generate" +// DARWIN-GEN1-SAME: "--cs-profile-path=default_%m.profraw" +// DARWIN-GEN2: "--cs-profile-generate" +// DARWIN-GEN2-SAME: "--cs-profile-path=directory{{(/|\\\\)}}default_%m.profraw" diff --git a/clang/test/Driver/debug-options-as.c b/clang/test/Driver/debug-options-as.c index baa6bf1e70f1a..259ad583edaa4 100644 --- a/clang/test/Driver/debug-options-as.c +++ b/clang/test/Driver/debug-options-as.c @@ -1,3 +1,5 @@ +// XFAIL: target={{.*}}-aix{{.*}} + // Check to make sure clang is somewhat picky about -g options. // (Delived from debug-options.c) // rdar://10383444 @@ -59,7 +61,7 @@ // // GDWARF64_VER: error: invalid argument '-gdwarf64' only allowed with 'DWARFv3 or greater' // GDWARF64_32ARCH: error: invalid argument '-gdwarf64' only allowed with '64 bit architecture' -// GDWARF64_ELF: error: invalid argument '-gdwarf64' only allowed with 'ELF/XCOFF platforms' +// GDWARF64_ELF: error: invalid argument '-gdwarf64' only allowed with 'ELF platforms' // Check that -gdwarf-N can be placed before other options of the "-g" group. // RUN: %clang -### -c -g -gdwarf-3 -target %itanium_abi_triple -fintegrated-as -x assembler %s 2>&1 \ diff --git a/clang/test/Driver/debug-options.c b/clang/test/Driver/debug-options.c index 1799f2cc1492b..8617949cea1c8 100644 --- a/clang/test/Driver/debug-options.c +++ b/clang/test/Driver/debug-options.c @@ -462,7 +462,7 @@ // GDWARF64_ON: "-gdwarf64" // GDWARF64_VER: error: invalid argument '-gdwarf64' only allowed with 'DWARFv3 or greater' // GDWARF64_32ARCH: error: invalid argument '-gdwarf64' only allowed with '64 bit architecture' -// GDWARF64_ELF: error: invalid argument '-gdwarf64' only allowed with 'ELF/XCOFF platforms' +// GDWARF64_ELF: error: invalid argument '-gdwarf64' only allowed with 'ELF platforms' /// Default to -fno-dwarf-directory-asm for -fno-integrated-as before DWARF v5. // RUN: %clang -### -target x86_64 -c -gdwarf-2 %s 2>&1 | FileCheck --check-prefix=DIRECTORY %s diff --git a/clang/test/Driver/debug-prefix-map.S b/clang/test/Driver/debug-prefix-map.S index 6dd1ded9bfdfa..febf608690420 100644 --- a/clang/test/Driver/debug-prefix-map.S +++ b/clang/test/Driver/debug-prefix-map.S @@ -1,3 +1,5 @@ +// XFAIL: target={{.*}}-aix{{.*}} + // RUN: %clang -### -g -fintegrated-as -fdebug-prefix-map=old=new %s 2>&1 | FileCheck %s // RUN: %clang -### -g -fintegrated-as -ffile-prefix-map=old=new %s 2>&1 | FileCheck %s diff --git a/clang/test/Driver/defsym.s b/clang/test/Driver/defsym.s index ae2b1fd919479..165c71b2eae97 100644 --- a/clang/test/Driver/defsym.s +++ b/clang/test/Driver/defsym.s @@ -1,3 +1,5 @@ +// XFAIL: target={{.*}}-aix{{.*}} + // RUN: %clang -### -c -integrated-as %s \ // RUN: -Wa,-defsym,abc=5 -Wa,-defsym,xyz=0xa \ // RUN: 2>&1 | FileCheck %s --check-prefix=CHECK-DEFSYM1 diff --git a/clang/test/Driver/embed-bitcode.c b/clang/test/Driver/embed-bitcode.c index 07e4378dc0940..0dadfa4e2cb45 100644 --- a/clang/test/Driver/embed-bitcode.c +++ b/clang/test/Driver/embed-bitcode.c @@ -16,7 +16,7 @@ // CHECK-BITCODE: -emit-obj // CHECK-BITCODE: -fembed-bitcode=bitcode // -// RUN: %clang %s -c -save-temps -fembed-bitcode -fintegrated-as 2>&1 -### | FileCheck %s -check-prefix=CHECK-SAVE-TEMP +// RUN: %clang %s -c -target powerpc-ibm-aix -save-temps -fembed-bitcode -fintegrated-as 2>&1 -### | FileCheck %s -check-prefix=CHECK-SAVE-TEMP // CHECK-SAVE-TEMP: -cc1 // CHECK-SAVE-TEMP: -E // CHECK-SAVE-TEMP: -cc1 @@ -24,7 +24,7 @@ // CHECK-SAVE-TEMP: -cc1 // CHECK-SAVE-TEMP: -S // CHECK-SAVE-TEMP: -fembed-bitcode=all -// CHECK-SAVE-TEMP: -cc1as +// CHECK-SAVE-TEMP: "{{.*}}as{{(.exe)?}}" // RUN: %clang -c %s -flto -fembed-bitcode 2>&1 -### | FileCheck %s -check-prefix=CHECK-LTO // RUN: %clang -c %s -flto=full -fembed-bitcode 2>&1 -### | FileCheck %s -check-prefix=CHECK-LTO diff --git a/clang/test/Driver/endian.c b/clang/test/Driver/endian.c new file mode 100644 index 0000000000000..7fddbc93e9cd6 --- /dev/null +++ b/clang/test/Driver/endian.c @@ -0,0 +1,5 @@ +// RUN: %clang -### -c --target=x86_64 -mbig-endian -mlittle-endian %s 2>&1 | FileCheck /dev/null --implicit-check-not=error: +// RUN: %clang -### -c --target=x86_64 -mlittle-endian -mbig-endian %s 2>&1 | FileCheck %s --implicit-check-not=error: + +// CHECK: error: unsupported option '-mlittle-endian' for target 'x86_64' +// CHECK: error: unsupported option '-mbig-endian' for target 'x86_64' diff --git a/clang/test/Driver/integrated-as.c b/clang/test/Driver/integrated-as.c index 55334ed71e59a..d7658fdfd6337 100644 --- a/clang/test/Driver/integrated-as.c +++ b/clang/test/Driver/integrated-as.c @@ -1,3 +1,5 @@ +// XFAIL: target={{.*}}-aix{{.*}} + // RUN: %clang -### -c -save-temps -integrated-as %s 2>&1 | FileCheck %s // CHECK: cc1as diff --git a/clang/test/Driver/linker-opts.c b/clang/test/Driver/linker-opts.c index e3c4e00ea0c75..181aeadb8dc97 100644 --- a/clang/test/Driver/linker-opts.c +++ b/clang/test/Driver/linker-opts.c @@ -15,9 +15,8 @@ // // Make sure that we don't warn on unused compiler arguments. // RUN: %clang -Xclang -I. -x c %s -c -o %t/tmp.o -// RUN: %clang -Xclang -I. %t/tmp.o -o %t/tmp -### 2>&1 | FileCheck %s --check-prefix=NO-UNUSED -// NO-UNUSED-NOT: warning:{{.*}}unused -// +// RUN: %clang -### -I. -ibuiltininc -nobuiltininc -nostdinc -nostdinc++ -nostdlibinc -nogpuinc %t/tmp.o -Wno-msvc-not-found -o /dev/null 2>&1 | FileCheck /dev/null --implicit-check-not=warning: + // Make sure that we do warn in other cases. // RUN: %clang %s -lfoo -c -o %t/tmp2.o -### 2>&1 | FileCheck %s --check-prefix=UNUSED // UNUSED: warning:{{.*}}unused diff --git a/clang/test/Driver/linker-wrapper-libs.c b/clang/test/Driver/linker-wrapper-libs.c index acb7c38165d04..2073092bdbcf9 100644 --- a/clang/test/Driver/linker-wrapper-libs.c +++ b/clang/test/Driver/linker-wrapper-libs.c @@ -12,6 +12,9 @@ int __attribute__((visibility("protected"))) global; int __attribute__((visibility("hidden"))) weak; #elif defined(HIDDEN) int __attribute__((visibility("hidden"))) hidden; +#elif defined(UNDEFINED) +extern int sym; +int baz() { return sym; } #else extern int sym; @@ -26,7 +29,11 @@ int bar() { return weak; } // // RUN: %clang -cc1 %s -triple nvptx64-nvidia-cuda -emit-llvm-bc -DRESOLVES -o %t.nvptx.resolves.bc // RUN: %clang -cc1 %s -triple amdgcn-amd-amdhsa -emit-llvm-bc -DRESOLVES -o %t.amdgpu.resolves.bc +// RUN: %clang -cc1 %s -triple nvptx64-nvidia-cuda -emit-llvm-bc -DUNDEFINED -o %t.nvptx.undefined.bc +// RUN: %clang -cc1 %s -triple amdgcn-amd-amdhsa -emit-llvm-bc -DUNDEFINED -o %t.amdgpu.undefined.bc // RUN: clang-offload-packager -o %t-lib.out \ +// RUN: --image=file=%t.nvptx.undefined.bc,kind=openmp,triple=nvptx64-nvidia-cuda,arch=sm_70 \ +// RUN: --image=file=%t.amdgpu.undefined.bc,kind=openmp,triple=amdgcn-amd-amdhsa,arch=gfx1030 \ // RUN: --image=file=%t.nvptx.resolves.bc,kind=openmp,triple=nvptx64-nvidia-cuda,arch=sm_70 \ // RUN: --image=file=%t.amdgpu.resolves.bc,kind=openmp,triple=amdgcn-amd-amdhsa,arch=gfx1030 // RUN: %clang -cc1 %s -triple x86_64-unknown-linux-gnu -emit-obj -o %t.o -fembed-offload-object=%t-lib.out diff --git a/clang/test/Driver/mdefault-visibility-export-mapping.c b/clang/test/Driver/mdefault-visibility-export-mapping.c new file mode 100644 index 0000000000000..2f8f246373d57 --- /dev/null +++ b/clang/test/Driver/mdefault-visibility-export-mapping.c @@ -0,0 +1,7 @@ +// RUN: %clang -### -S -mdefault-visibility-export-mapping=explicit --target=powerpc-ibm-aix %s 2>&1 | FileCheck %s +// RUN: %clang -### -S -mdefault-visibility-export-mapping=explicit --target=powerpc-unknown-linux %s 2>&1 | \ +// RUN: FileCheck -check-prefix=ERROR %s + +// CHECK: "-mdefault-visibility-export-mapping=explicit" + +// ERROR: error: unsupported option '-mdefault-visibility-export-mapping=' for target 'powerpc-unknown-linux' diff --git a/clang/test/Driver/ppc-endian.c b/clang/test/Driver/ppc-endian.c index 00c1c25bb358f..5854fa63fdc83 100644 --- a/clang/test/Driver/ppc-endian.c +++ b/clang/test/Driver/ppc-endian.c @@ -1,5 +1,5 @@ // RUN: %clang -target powerpc-unknown -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-BE32 %s -// RUN: %clang -target powerpc-unknown -mbig-endian -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-BE32 %s +// RUN: %clang --target=powerpc-unknown -mbig-endian -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-BE32 %s --implicit-check-not=error: // RUN: %clang -target powerpcle-unknown -mbig-endian -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-BE32 %s // CHECK-BE32: "-cc1"{{.*}} "-triple" "powerpc-{{.*}}" diff --git a/clang/test/Driver/relax.s b/clang/test/Driver/relax.s index 01ae9d87c39b2..154d4db0a3138 100644 --- a/clang/test/Driver/relax.s +++ b/clang/test/Driver/relax.s @@ -1,5 +1,5 @@ // REQUIRES: x86-registered-target -// RUN: %clang -### -c -integrated-as -Wa,--mrelax-relocations=no %s 2>&1 | FileCheck %s +// RUN: %clang -### -c -target x86_64-pc-linux -integrated-as -Wa,--mrelax-relocations=no %s 2>&1 | FileCheck %s // CHECK: "-cc1as" // CHECK: "-mrelax-relocations=no" diff --git a/clang/test/FixIt/fixit-function-call.cpp b/clang/test/FixIt/fixit-function-call.cpp index 88f636ea5859d..17c50adffc4a2 100644 --- a/clang/test/FixIt/fixit-function-call.cpp +++ b/clang/test/FixIt/fixit-function-call.cpp @@ -1,4 +1,4 @@ -// RUN: not %clang_cc1 -fdiagnostics-parseable-fixits -x c++ %s 2> %t +// RUN: not %clang_cc1 -fdiagnostics-parseable-fixits -fno-diagnostics-show-line-numbers -fcaret-diagnostics-max-lines 1 -x c++ %s 2> %t // RUN: FileCheck %s < %t // PR5941 // END. diff --git a/clang/test/FixIt/fixit-newline-style.c b/clang/test/FixIt/fixit-newline-style.c index 8c5f424c39873..091b79426bcdf 100644 --- a/clang/test/FixIt/fixit-newline-style.c +++ b/clang/test/FixIt/fixit-newline-style.c @@ -1,4 +1,4 @@ -// RUN: %clang_cc1 -pedantic -Wunused-label -x c %s 2>&1 | FileCheck %s -strict-whitespace +// RUN: %clang_cc1 -pedantic -Wunused-label -fno-diagnostics-show-line-numbers -x c %s 2>&1 | FileCheck %s -strict-whitespace // This file intentionally uses a CRLF newline style // diff --git a/clang/test/FixIt/fixit-unicode-with-utf8-output.c b/clang/test/FixIt/fixit-unicode-with-utf8-output.c index a1a7bb7338095..f5aec89939adf 100644 --- a/clang/test/FixIt/fixit-unicode-with-utf8-output.c +++ b/clang/test/FixIt/fixit-unicode-with-utf8-output.c @@ -1,7 +1,7 @@ // This test is an additional set of checks for the fixit-unicode.c test for // systems capable of outputting Unicode characters to the standard output in // the UTF-8 encoding. -// RUN: not %clang_cc1 -fsyntax-only %S/fixit-unicode.c 2>&1 | FileCheck -strict-whitespace %s +// RUN: not %clang_cc1 -fsyntax-only -fno-diagnostics-show-line-numbers %S/fixit-unicode.c 2>&1 | FileCheck -strict-whitespace %s // REQUIRES: utf8-capable-terminal // CHECK: warning: format specifies type 'int' but the argument has type 'long' diff --git a/clang/test/FixIt/fixit-unicode.c b/clang/test/FixIt/fixit-unicode.c index 70c9751a2bcd6..87819cdfbea17 100644 --- a/clang/test/FixIt/fixit-unicode.c +++ b/clang/test/FixIt/fixit-unicode.c @@ -2,8 +2,8 @@ // There's a set of additional checks for systems with proper support of UTF-8 // on the standard output in fixit-unicode-with-utf8-output.c. -// RUN: not %clang_cc1 -fsyntax-only %s 2>&1 | FileCheck -strict-whitespace %s -// RUN: not %clang_cc1 -fsyntax-only -fdiagnostics-parseable-fixits %s 2>&1 | FileCheck -check-prefix=CHECK-MACHINE %s +// RUN: not %clang_cc1 -fsyntax-only -fno-diagnostics-show-line-numbers %s 2>&1 | FileCheck -strict-whitespace %s +// RUN: not %clang_cc1 -fsyntax-only -fno-diagnostics-show-line-numbers -fdiagnostics-parseable-fixits %s 2>&1 | FileCheck -check-prefix=CHECK-MACHINE %s struct Foo { int bar; diff --git a/clang/test/Format/dump-config-objc-macros.h b/clang/test/Format/dump-config-objc-macros.h new file mode 100644 index 0000000000000..c90aa6067b1f4 --- /dev/null +++ b/clang/test/Format/dump-config-objc-macros.h @@ -0,0 +1,8 @@ +// RUN: clang-format -dump-config %s | FileCheck %s + +// CHECK: Language: ObjC +NS_ASSUME_NONNULL_BEGIN + +FOUNDATION_EXTERN int kConstant; + +NS_ASSUME_NONNULL_END diff --git a/clang/test/Frontend/source-col-map.c b/clang/test/Frontend/source-col-map.c index b257261b8b2bc..20030a28f5c19 100644 --- a/clang/test/Frontend/source-col-map.c +++ b/clang/test/Frontend/source-col-map.c @@ -1,4 +1,4 @@ -// RUN: not %clang_cc1 -fsyntax-only -fmessage-length=75 -o /dev/null -x c < %s 2>&1 | FileCheck %s -strict-whitespace +// RUN: not %clang_cc1 -fsyntax-only -fno-diagnostics-show-line-numbers -fmessage-length=75 -o /dev/null -x c < %s 2>&1 | FileCheck %s -strict-whitespace // REQUIRES: utf8-capable-terminal // Test case for the text diagnostics source column conversion crash. diff --git a/clang/test/Headers/__clang_hip_math.hip b/clang/test/Headers/__clang_hip_math.hip index e546ce5ac24ab..2a60cbaf5f440 100644 --- a/clang/test/Headers/__clang_hip_math.hip +++ b/clang/test/Headers/__clang_hip_math.hip @@ -130,11 +130,11 @@ extern "C" __device__ uint64_t test___make_mantissa_base16(const char *p) { // CHECK-NEXT: entry: // CHECK-NEXT: [[TMP0:%.*]] = load i8, ptr [[P:%.*]], align 1, !tbaa [[TBAA3]] // CHECK-NEXT: [[CMP_I:%.*]] = icmp eq i8 [[TMP0]], 48 -// CHECK-NEXT: br i1 [[CMP_I]], label [[IF_THEN_I:%.*]], label [[WHILE_COND_I33_I:%.*]] +// CHECK-NEXT: br i1 [[CMP_I]], label [[IF_THEN_I:%.*]], label [[WHILE_COND_I30_I:%.*]] // CHECK: if.then.i: // CHECK-NEXT: [[INCDEC_PTR_I:%.*]] = getelementptr inbounds i8, ptr [[P]], i64 1 // CHECK-NEXT: [[TMP1:%.*]] = load i8, ptr [[INCDEC_PTR_I]], align 1, !tbaa [[TBAA3]] -// CHECK-NEXT: switch i8 [[TMP1]], label [[WHILE_COND_I17_I:%.*]] [ +// CHECK-NEXT: switch i8 [[TMP1]], label [[WHILE_COND_I14_I:%.*]] [ // CHECK-NEXT: i8 120, label [[WHILE_COND_I_I_PREHEADER:%.*]] // CHECK-NEXT: i8 88, label [[WHILE_COND_I_I_PREHEADER]] // CHECK-NEXT: ] @@ -171,50 +171,50 @@ extern "C" __device__ uint64_t test___make_mantissa_base16(const char *p) { // CHECK-NEXT: [[__R_2_I_I]] = phi i64 [ [[ADD28_I_I]], [[IF_END31_I_I]] ], [ [[__R_0_I_I]], [[IF_ELSE17_I_I]] ] // CHECK-NEXT: [[COND_I_I:%.*]] = phi i1 [ true, [[IF_END31_I_I]] ], [ false, [[IF_ELSE17_I_I]] ] // CHECK-NEXT: br i1 [[COND_I_I]], label [[WHILE_COND_I_I]], label [[_ZL15__MAKE_MANTISSAPKC_EXIT]], !llvm.loop [[LOOP10]] -// CHECK: while.cond.i17.i: -// CHECK-NEXT: [[__TAGP_ADDR_0_I14_I:%.*]] = phi ptr [ [[__TAGP_ADDR_1_I26_I:%.*]], [[CLEANUP_I28_I:%.*]] ], [ [[INCDEC_PTR_I]], [[IF_THEN_I]] ] -// CHECK-NEXT: [[__R_0_I15_I:%.*]] = phi i64 [ [[__R_1_I27_I:%.*]], [[CLEANUP_I28_I]] ], [ 0, [[IF_THEN_I]] ] -// CHECK-NEXT: [[TMP6:%.*]] = load i8, ptr [[__TAGP_ADDR_0_I14_I]], align 1, !tbaa [[TBAA3]] -// CHECK-NEXT: [[CMP_NOT_I16_I:%.*]] = icmp eq i8 [[TMP6]], 0 -// CHECK-NEXT: br i1 [[CMP_NOT_I16_I]], label [[_ZL15__MAKE_MANTISSAPKC_EXIT]], label [[WHILE_BODY_I19_I:%.*]] -// CHECK: while.body.i19.i: +// CHECK: while.cond.i14.i: +// CHECK-NEXT: [[__TAGP_ADDR_0_I15_I:%.*]] = phi ptr [ [[__TAGP_ADDR_1_I21_I:%.*]], [[CLEANUP_I20_I:%.*]] ], [ [[INCDEC_PTR_I]], [[IF_THEN_I]] ] +// CHECK-NEXT: [[__R_0_I16_I:%.*]] = phi i64 [ [[__R_1_I22_I:%.*]], [[CLEANUP_I20_I]] ], [ 0, [[IF_THEN_I]] ] +// CHECK-NEXT: [[TMP6:%.*]] = load i8, ptr [[__TAGP_ADDR_0_I15_I]], align 1, !tbaa [[TBAA3]] +// CHECK-NEXT: [[CMP_NOT_I17_I:%.*]] = icmp eq i8 [[TMP6]], 0 +// CHECK-NEXT: br i1 [[CMP_NOT_I17_I]], label [[_ZL15__MAKE_MANTISSAPKC_EXIT]], label [[WHILE_BODY_I18_I:%.*]] +// CHECK: while.body.i18.i: // CHECK-NEXT: [[TMP7:%.*]] = and i8 [[TMP6]], -8 -// CHECK-NEXT: [[OR_COND_I18_I:%.*]] = icmp eq i8 [[TMP7]], 48 -// CHECK-NEXT: br i1 [[OR_COND_I18_I]], label [[IF_THEN_I25_I:%.*]], label [[CLEANUP_I28_I]] -// CHECK: if.then.i25.i: -// CHECK-NEXT: [[MUL_I20_I:%.*]] = shl i64 [[__R_0_I15_I]], 3 -// CHECK-NEXT: [[CONV5_I21_I:%.*]] = sext i8 [[TMP6]] to i64 -// CHECK-NEXT: [[ADD_I22_I:%.*]] = add i64 [[MUL_I20_I]], -48 -// CHECK-NEXT: [[SUB_I23_I:%.*]] = add i64 [[ADD_I22_I]], [[CONV5_I21_I]] -// CHECK-NEXT: [[INCDEC_PTR_I24_I:%.*]] = getelementptr inbounds i8, ptr [[__TAGP_ADDR_0_I14_I]], i64 1 -// CHECK-NEXT: br label [[CLEANUP_I28_I]] -// CHECK: cleanup.i28.i: -// CHECK-NEXT: [[__TAGP_ADDR_1_I26_I]] = phi ptr [ [[INCDEC_PTR_I24_I]], [[IF_THEN_I25_I]] ], [ [[__TAGP_ADDR_0_I14_I]], [[WHILE_BODY_I19_I]] ] -// CHECK-NEXT: [[__R_1_I27_I]] = phi i64 [ [[SUB_I23_I]], [[IF_THEN_I25_I]] ], [ [[__R_0_I15_I]], [[WHILE_BODY_I19_I]] ] -// CHECK-NEXT: br i1 [[OR_COND_I18_I]], label [[WHILE_COND_I17_I]], label [[_ZL15__MAKE_MANTISSAPKC_EXIT]], !llvm.loop [[LOOP6]] -// CHECK: while.cond.i33.i: -// CHECK-NEXT: [[__TAGP_ADDR_0_I30_I:%.*]] = phi ptr [ [[__TAGP_ADDR_1_I42_I:%.*]], [[CLEANUP_I44_I:%.*]] ], [ [[P]], [[ENTRY:%.*]] ] -// CHECK-NEXT: [[__R_0_I31_I:%.*]] = phi i64 [ [[__R_1_I43_I:%.*]], [[CLEANUP_I44_I]] ], [ 0, [[ENTRY]] ] -// CHECK-NEXT: [[TMP8:%.*]] = load i8, ptr [[__TAGP_ADDR_0_I30_I]], align 1, !tbaa [[TBAA3]] -// CHECK-NEXT: [[CMP_NOT_I32_I:%.*]] = icmp eq i8 [[TMP8]], 0 -// CHECK-NEXT: br i1 [[CMP_NOT_I32_I]], label [[_ZL15__MAKE_MANTISSAPKC_EXIT]], label [[WHILE_BODY_I35_I:%.*]] -// CHECK: while.body.i35.i: +// CHECK-NEXT: [[OR_COND_I19_I:%.*]] = icmp eq i8 [[TMP7]], 48 +// CHECK-NEXT: br i1 [[OR_COND_I19_I]], label [[IF_THEN_I24_I:%.*]], label [[CLEANUP_I20_I]] +// CHECK: if.then.i24.i: +// CHECK-NEXT: [[MUL_I25_I:%.*]] = shl i64 [[__R_0_I16_I]], 3 +// CHECK-NEXT: [[CONV5_I26_I:%.*]] = sext i8 [[TMP6]] to i64 +// CHECK-NEXT: [[ADD_I27_I:%.*]] = add i64 [[MUL_I25_I]], -48 +// CHECK-NEXT: [[SUB_I28_I:%.*]] = add i64 [[ADD_I27_I]], [[CONV5_I26_I]] +// CHECK-NEXT: [[INCDEC_PTR_I29_I:%.*]] = getelementptr inbounds i8, ptr [[__TAGP_ADDR_0_I15_I]], i64 1 +// CHECK-NEXT: br label [[CLEANUP_I20_I]] +// CHECK: cleanup.i20.i: +// CHECK-NEXT: [[__TAGP_ADDR_1_I21_I]] = phi ptr [ [[INCDEC_PTR_I29_I]], [[IF_THEN_I24_I]] ], [ [[__TAGP_ADDR_0_I15_I]], [[WHILE_BODY_I18_I]] ] +// CHECK-NEXT: [[__R_1_I22_I]] = phi i64 [ [[SUB_I28_I]], [[IF_THEN_I24_I]] ], [ [[__R_0_I16_I]], [[WHILE_BODY_I18_I]] ] +// CHECK-NEXT: br i1 [[OR_COND_I19_I]], label [[WHILE_COND_I14_I]], label [[_ZL15__MAKE_MANTISSAPKC_EXIT]], !llvm.loop [[LOOP6]] +// CHECK: while.cond.i30.i: +// CHECK-NEXT: [[__TAGP_ADDR_0_I31_I:%.*]] = phi ptr [ [[__TAGP_ADDR_1_I37_I:%.*]], [[CLEANUP_I36_I:%.*]] ], [ [[P]], [[ENTRY:%.*]] ] +// CHECK-NEXT: [[__R_0_I32_I:%.*]] = phi i64 [ [[__R_1_I38_I:%.*]], [[CLEANUP_I36_I]] ], [ 0, [[ENTRY]] ] +// CHECK-NEXT: [[TMP8:%.*]] = load i8, ptr [[__TAGP_ADDR_0_I31_I]], align 1, !tbaa [[TBAA3]] +// CHECK-NEXT: [[CMP_NOT_I33_I:%.*]] = icmp eq i8 [[TMP8]], 0 +// CHECK-NEXT: br i1 [[CMP_NOT_I33_I]], label [[_ZL15__MAKE_MANTISSAPKC_EXIT]], label [[WHILE_BODY_I34_I:%.*]] +// CHECK: while.body.i34.i: // CHECK-NEXT: [[TMP9:%.*]] = add i8 [[TMP8]], -48 -// CHECK-NEXT: [[OR_COND_I34_I:%.*]] = icmp ult i8 [[TMP9]], 10 -// CHECK-NEXT: br i1 [[OR_COND_I34_I]], label [[IF_THEN_I41_I:%.*]], label [[CLEANUP_I44_I]] -// CHECK: if.then.i41.i: -// CHECK-NEXT: [[MUL_I36_I:%.*]] = mul i64 [[__R_0_I31_I]], 10 -// CHECK-NEXT: [[CONV5_I37_I:%.*]] = sext i8 [[TMP8]] to i64 -// CHECK-NEXT: [[ADD_I38_I:%.*]] = add i64 [[MUL_I36_I]], -48 -// CHECK-NEXT: [[SUB_I39_I:%.*]] = add i64 [[ADD_I38_I]], [[CONV5_I37_I]] -// CHECK-NEXT: [[INCDEC_PTR_I40_I:%.*]] = getelementptr inbounds i8, ptr [[__TAGP_ADDR_0_I30_I]], i64 1 -// CHECK-NEXT: br label [[CLEANUP_I44_I]] -// CHECK: cleanup.i44.i: -// CHECK-NEXT: [[__TAGP_ADDR_1_I42_I]] = phi ptr [ [[INCDEC_PTR_I40_I]], [[IF_THEN_I41_I]] ], [ [[__TAGP_ADDR_0_I30_I]], [[WHILE_BODY_I35_I]] ] -// CHECK-NEXT: [[__R_1_I43_I]] = phi i64 [ [[SUB_I39_I]], [[IF_THEN_I41_I]] ], [ [[__R_0_I31_I]], [[WHILE_BODY_I35_I]] ] -// CHECK-NEXT: br i1 [[OR_COND_I34_I]], label [[WHILE_COND_I33_I]], label [[_ZL15__MAKE_MANTISSAPKC_EXIT]], !llvm.loop [[LOOP9]] +// CHECK-NEXT: [[OR_COND_I35_I:%.*]] = icmp ult i8 [[TMP9]], 10 +// CHECK-NEXT: br i1 [[OR_COND_I35_I]], label [[IF_THEN_I40_I:%.*]], label [[CLEANUP_I36_I]] +// CHECK: if.then.i40.i: +// CHECK-NEXT: [[MUL_I41_I:%.*]] = mul i64 [[__R_0_I32_I]], 10 +// CHECK-NEXT: [[CONV5_I42_I:%.*]] = sext i8 [[TMP8]] to i64 +// CHECK-NEXT: [[ADD_I43_I:%.*]] = add i64 [[MUL_I41_I]], -48 +// CHECK-NEXT: [[SUB_I44_I:%.*]] = add i64 [[ADD_I43_I]], [[CONV5_I42_I]] +// CHECK-NEXT: [[INCDEC_PTR_I45_I:%.*]] = getelementptr inbounds i8, ptr [[__TAGP_ADDR_0_I31_I]], i64 1 +// CHECK-NEXT: br label [[CLEANUP_I36_I]] +// CHECK: cleanup.i36.i: +// CHECK-NEXT: [[__TAGP_ADDR_1_I37_I]] = phi ptr [ [[INCDEC_PTR_I45_I]], [[IF_THEN_I40_I]] ], [ [[__TAGP_ADDR_0_I31_I]], [[WHILE_BODY_I34_I]] ] +// CHECK-NEXT: [[__R_1_I38_I]] = phi i64 [ [[SUB_I44_I]], [[IF_THEN_I40_I]] ], [ [[__R_0_I32_I]], [[WHILE_BODY_I34_I]] ] +// CHECK-NEXT: br i1 [[OR_COND_I35_I]], label [[WHILE_COND_I30_I]], label [[_ZL15__MAKE_MANTISSAPKC_EXIT]], !llvm.loop [[LOOP9]] // CHECK: _ZL15__make_mantissaPKc.exit: -// CHECK-NEXT: [[RETVAL_0_I:%.*]] = phi i64 [ 0, [[CLEANUP_I28_I]] ], [ [[__R_0_I15_I]], [[WHILE_COND_I17_I]] ], [ 0, [[CLEANUP_I_I]] ], [ [[__R_0_I_I]], [[WHILE_COND_I_I]] ], [ 0, [[CLEANUP_I44_I]] ], [ [[__R_0_I31_I]], [[WHILE_COND_I33_I]] ] +// CHECK-NEXT: [[RETVAL_0_I:%.*]] = phi i64 [ 0, [[CLEANUP_I20_I]] ], [ [[__R_0_I16_I]], [[WHILE_COND_I14_I]] ], [ 0, [[CLEANUP_I_I]] ], [ [[__R_0_I_I]], [[WHILE_COND_I_I]] ], [ 0, [[CLEANUP_I36_I]] ], [ [[__R_0_I32_I]], [[WHILE_COND_I30_I]] ] // CHECK-NEXT: ret i64 [[RETVAL_0_I]] // extern "C" __device__ uint64_t test___make_mantissa(const char *p) { @@ -767,7 +767,6 @@ extern "C" __device__ float test_exp2f(float x) { return exp2f(x); } -// // DEFAULT-LABEL: @test_exp2( // DEFAULT-NEXT: entry: // DEFAULT-NEXT: [[CALL_I:%.*]] = tail call contract double @__ocml_exp2_f64(double noundef [[X:%.*]]) #[[ATTR14]] @@ -1818,11 +1817,11 @@ extern "C" __device__ double test_modf(double x, double* y) { // CHECK-NEXT: entry: // CHECK-NEXT: [[TMP0:%.*]] = load i8, ptr [[TAG:%.*]], align 1, !tbaa [[TBAA3]] // CHECK-NEXT: [[CMP_I_I:%.*]] = icmp eq i8 [[TMP0]], 48 -// CHECK-NEXT: br i1 [[CMP_I_I]], label [[IF_THEN_I_I:%.*]], label [[WHILE_COND_I33_I_I:%.*]] +// CHECK-NEXT: br i1 [[CMP_I_I]], label [[IF_THEN_I_I:%.*]], label [[WHILE_COND_I30_I_I:%.*]] // CHECK: if.then.i.i: // CHECK-NEXT: [[INCDEC_PTR_I_I:%.*]] = getelementptr inbounds i8, ptr [[TAG]], i64 1 // CHECK-NEXT: [[TMP1:%.*]] = load i8, ptr [[INCDEC_PTR_I_I]], align 1, !tbaa [[TBAA3]] -// CHECK-NEXT: switch i8 [[TMP1]], label [[WHILE_COND_I17_I_I:%.*]] [ +// CHECK-NEXT: switch i8 [[TMP1]], label [[WHILE_COND_I14_I_I:%.*]] [ // CHECK-NEXT: i8 120, label [[WHILE_COND_I_I_I_PREHEADER:%.*]] // CHECK-NEXT: i8 88, label [[WHILE_COND_I_I_I_PREHEADER]] // CHECK-NEXT: ] @@ -1859,50 +1858,50 @@ extern "C" __device__ double test_modf(double x, double* y) { // CHECK-NEXT: [[__R_2_I_I_I]] = phi i64 [ [[ADD28_I_I_I]], [[IF_END31_I_I_I]] ], [ [[__R_0_I_I_I]], [[IF_ELSE17_I_I_I]] ] // CHECK-NEXT: [[COND_I_I_I:%.*]] = phi i1 [ true, [[IF_END31_I_I_I]] ], [ false, [[IF_ELSE17_I_I_I]] ] // CHECK-NEXT: br i1 [[COND_I_I_I]], label [[WHILE_COND_I_I_I]], label [[_ZL4NANFPKC_EXIT]], !llvm.loop [[LOOP10]] -// CHECK: while.cond.i17.i.i: -// CHECK-NEXT: [[__TAGP_ADDR_0_I14_I_I:%.*]] = phi ptr [ [[__TAGP_ADDR_1_I26_I_I:%.*]], [[CLEANUP_I28_I_I:%.*]] ], [ [[INCDEC_PTR_I_I]], [[IF_THEN_I_I]] ] -// CHECK-NEXT: [[__R_0_I15_I_I:%.*]] = phi i64 [ [[__R_1_I27_I_I:%.*]], [[CLEANUP_I28_I_I]] ], [ 0, [[IF_THEN_I_I]] ] -// CHECK-NEXT: [[TMP6:%.*]] = load i8, ptr [[__TAGP_ADDR_0_I14_I_I]], align 1, !tbaa [[TBAA3]] -// CHECK-NEXT: [[CMP_NOT_I16_I_I:%.*]] = icmp eq i8 [[TMP6]], 0 -// CHECK-NEXT: br i1 [[CMP_NOT_I16_I_I]], label [[_ZL4NANFPKC_EXIT]], label [[WHILE_BODY_I19_I_I:%.*]] -// CHECK: while.body.i19.i.i: +// CHECK: while.cond.i14.i.i: +// CHECK-NEXT: [[__TAGP_ADDR_0_I15_I_I:%.*]] = phi ptr [ [[__TAGP_ADDR_1_I21_I_I:%.*]], [[CLEANUP_I20_I_I:%.*]] ], [ [[INCDEC_PTR_I_I]], [[IF_THEN_I_I]] ] +// CHECK-NEXT: [[__R_0_I16_I_I:%.*]] = phi i64 [ [[__R_1_I22_I_I:%.*]], [[CLEANUP_I20_I_I]] ], [ 0, [[IF_THEN_I_I]] ] +// CHECK-NEXT: [[TMP6:%.*]] = load i8, ptr [[__TAGP_ADDR_0_I15_I_I]], align 1, !tbaa [[TBAA3]] +// CHECK-NEXT: [[CMP_NOT_I17_I_I:%.*]] = icmp eq i8 [[TMP6]], 0 +// CHECK-NEXT: br i1 [[CMP_NOT_I17_I_I]], label [[_ZL4NANFPKC_EXIT]], label [[WHILE_BODY_I18_I_I:%.*]] +// CHECK: while.body.i18.i.i: // CHECK-NEXT: [[TMP7:%.*]] = and i8 [[TMP6]], -8 -// CHECK-NEXT: [[OR_COND_I18_I_I:%.*]] = icmp eq i8 [[TMP7]], 48 -// CHECK-NEXT: br i1 [[OR_COND_I18_I_I]], label [[IF_THEN_I25_I_I:%.*]], label [[CLEANUP_I28_I_I]] -// CHECK: if.then.i25.i.i: -// CHECK-NEXT: [[MUL_I20_I_I:%.*]] = shl i64 [[__R_0_I15_I_I]], 3 -// CHECK-NEXT: [[CONV5_I21_I_I:%.*]] = sext i8 [[TMP6]] to i64 -// CHECK-NEXT: [[ADD_I22_I_I:%.*]] = add i64 [[MUL_I20_I_I]], -48 -// CHECK-NEXT: [[SUB_I23_I_I:%.*]] = add i64 [[ADD_I22_I_I]], [[CONV5_I21_I_I]] -// CHECK-NEXT: [[INCDEC_PTR_I24_I_I:%.*]] = getelementptr inbounds i8, ptr [[__TAGP_ADDR_0_I14_I_I]], i64 1 -// CHECK-NEXT: br label [[CLEANUP_I28_I_I]] -// CHECK: cleanup.i28.i.i: -// CHECK-NEXT: [[__TAGP_ADDR_1_I26_I_I]] = phi ptr [ [[INCDEC_PTR_I24_I_I]], [[IF_THEN_I25_I_I]] ], [ [[__TAGP_ADDR_0_I14_I_I]], [[WHILE_BODY_I19_I_I]] ] -// CHECK-NEXT: [[__R_1_I27_I_I]] = phi i64 [ [[SUB_I23_I_I]], [[IF_THEN_I25_I_I]] ], [ [[__R_0_I15_I_I]], [[WHILE_BODY_I19_I_I]] ] -// CHECK-NEXT: br i1 [[OR_COND_I18_I_I]], label [[WHILE_COND_I17_I_I]], label [[_ZL4NANFPKC_EXIT]], !llvm.loop [[LOOP6]] -// CHECK: while.cond.i33.i.i: -// CHECK-NEXT: [[__TAGP_ADDR_0_I30_I_I:%.*]] = phi ptr [ [[__TAGP_ADDR_1_I42_I_I:%.*]], [[CLEANUP_I44_I_I:%.*]] ], [ [[TAG]], [[ENTRY:%.*]] ] -// CHECK-NEXT: [[__R_0_I31_I_I:%.*]] = phi i64 [ [[__R_1_I43_I_I:%.*]], [[CLEANUP_I44_I_I]] ], [ 0, [[ENTRY]] ] -// CHECK-NEXT: [[TMP8:%.*]] = load i8, ptr [[__TAGP_ADDR_0_I30_I_I]], align 1, !tbaa [[TBAA3]] -// CHECK-NEXT: [[CMP_NOT_I32_I_I:%.*]] = icmp eq i8 [[TMP8]], 0 -// CHECK-NEXT: br i1 [[CMP_NOT_I32_I_I]], label [[_ZL4NANFPKC_EXIT]], label [[WHILE_BODY_I35_I_I:%.*]] -// CHECK: while.body.i35.i.i: +// CHECK-NEXT: [[OR_COND_I19_I_I:%.*]] = icmp eq i8 [[TMP7]], 48 +// CHECK-NEXT: br i1 [[OR_COND_I19_I_I]], label [[IF_THEN_I24_I_I:%.*]], label [[CLEANUP_I20_I_I]] +// CHECK: if.then.i24.i.i: +// CHECK-NEXT: [[MUL_I25_I_I:%.*]] = shl i64 [[__R_0_I16_I_I]], 3 +// CHECK-NEXT: [[CONV5_I26_I_I:%.*]] = sext i8 [[TMP6]] to i64 +// CHECK-NEXT: [[ADD_I27_I_I:%.*]] = add i64 [[MUL_I25_I_I]], -48 +// CHECK-NEXT: [[SUB_I28_I_I:%.*]] = add i64 [[ADD_I27_I_I]], [[CONV5_I26_I_I]] +// CHECK-NEXT: [[INCDEC_PTR_I29_I_I:%.*]] = getelementptr inbounds i8, ptr [[__TAGP_ADDR_0_I15_I_I]], i64 1 +// CHECK-NEXT: br label [[CLEANUP_I20_I_I]] +// CHECK: cleanup.i20.i.i: +// CHECK-NEXT: [[__TAGP_ADDR_1_I21_I_I]] = phi ptr [ [[INCDEC_PTR_I29_I_I]], [[IF_THEN_I24_I_I]] ], [ [[__TAGP_ADDR_0_I15_I_I]], [[WHILE_BODY_I18_I_I]] ] +// CHECK-NEXT: [[__R_1_I22_I_I]] = phi i64 [ [[SUB_I28_I_I]], [[IF_THEN_I24_I_I]] ], [ [[__R_0_I16_I_I]], [[WHILE_BODY_I18_I_I]] ] +// CHECK-NEXT: br i1 [[OR_COND_I19_I_I]], label [[WHILE_COND_I14_I_I]], label [[_ZL4NANFPKC_EXIT]], !llvm.loop [[LOOP6]] +// CHECK: while.cond.i30.i.i: +// CHECK-NEXT: [[__TAGP_ADDR_0_I31_I_I:%.*]] = phi ptr [ [[__TAGP_ADDR_1_I37_I_I:%.*]], [[CLEANUP_I36_I_I:%.*]] ], [ [[TAG]], [[ENTRY:%.*]] ] +// CHECK-NEXT: [[__R_0_I32_I_I:%.*]] = phi i64 [ [[__R_1_I38_I_I:%.*]], [[CLEANUP_I36_I_I]] ], [ 0, [[ENTRY]] ] +// CHECK-NEXT: [[TMP8:%.*]] = load i8, ptr [[__TAGP_ADDR_0_I31_I_I]], align 1, !tbaa [[TBAA3]] +// CHECK-NEXT: [[CMP_NOT_I33_I_I:%.*]] = icmp eq i8 [[TMP8]], 0 +// CHECK-NEXT: br i1 [[CMP_NOT_I33_I_I]], label [[_ZL4NANFPKC_EXIT]], label [[WHILE_BODY_I34_I_I:%.*]] +// CHECK: while.body.i34.i.i: // CHECK-NEXT: [[TMP9:%.*]] = add i8 [[TMP8]], -48 -// CHECK-NEXT: [[OR_COND_I34_I_I:%.*]] = icmp ult i8 [[TMP9]], 10 -// CHECK-NEXT: br i1 [[OR_COND_I34_I_I]], label [[IF_THEN_I41_I_I:%.*]], label [[CLEANUP_I44_I_I]] -// CHECK: if.then.i41.i.i: -// CHECK-NEXT: [[MUL_I36_I_I:%.*]] = mul i64 [[__R_0_I31_I_I]], 10 -// CHECK-NEXT: [[CONV5_I37_I_I:%.*]] = sext i8 [[TMP8]] to i64 -// CHECK-NEXT: [[ADD_I38_I_I:%.*]] = add i64 [[MUL_I36_I_I]], -48 -// CHECK-NEXT: [[SUB_I39_I_I:%.*]] = add i64 [[ADD_I38_I_I]], [[CONV5_I37_I_I]] -// CHECK-NEXT: [[INCDEC_PTR_I40_I_I:%.*]] = getelementptr inbounds i8, ptr [[__TAGP_ADDR_0_I30_I_I]], i64 1 -// CHECK-NEXT: br label [[CLEANUP_I44_I_I]] -// CHECK: cleanup.i44.i.i: -// CHECK-NEXT: [[__TAGP_ADDR_1_I42_I_I]] = phi ptr [ [[INCDEC_PTR_I40_I_I]], [[IF_THEN_I41_I_I]] ], [ [[__TAGP_ADDR_0_I30_I_I]], [[WHILE_BODY_I35_I_I]] ] -// CHECK-NEXT: [[__R_1_I43_I_I]] = phi i64 [ [[SUB_I39_I_I]], [[IF_THEN_I41_I_I]] ], [ [[__R_0_I31_I_I]], [[WHILE_BODY_I35_I_I]] ] -// CHECK-NEXT: br i1 [[OR_COND_I34_I_I]], label [[WHILE_COND_I33_I_I]], label [[_ZL4NANFPKC_EXIT]], !llvm.loop [[LOOP9]] +// CHECK-NEXT: [[OR_COND_I35_I_I:%.*]] = icmp ult i8 [[TMP9]], 10 +// CHECK-NEXT: br i1 [[OR_COND_I35_I_I]], label [[IF_THEN_I40_I_I:%.*]], label [[CLEANUP_I36_I_I]] +// CHECK: if.then.i40.i.i: +// CHECK-NEXT: [[MUL_I41_I_I:%.*]] = mul i64 [[__R_0_I32_I_I]], 10 +// CHECK-NEXT: [[CONV5_I42_I_I:%.*]] = sext i8 [[TMP8]] to i64 +// CHECK-NEXT: [[ADD_I43_I_I:%.*]] = add i64 [[MUL_I41_I_I]], -48 +// CHECK-NEXT: [[SUB_I44_I_I:%.*]] = add i64 [[ADD_I43_I_I]], [[CONV5_I42_I_I]] +// CHECK-NEXT: [[INCDEC_PTR_I45_I_I:%.*]] = getelementptr inbounds i8, ptr [[__TAGP_ADDR_0_I31_I_I]], i64 1 +// CHECK-NEXT: br label [[CLEANUP_I36_I_I]] +// CHECK: cleanup.i36.i.i: +// CHECK-NEXT: [[__TAGP_ADDR_1_I37_I_I]] = phi ptr [ [[INCDEC_PTR_I45_I_I]], [[IF_THEN_I40_I_I]] ], [ [[__TAGP_ADDR_0_I31_I_I]], [[WHILE_BODY_I34_I_I]] ] +// CHECK-NEXT: [[__R_1_I38_I_I]] = phi i64 [ [[SUB_I44_I_I]], [[IF_THEN_I40_I_I]] ], [ [[__R_0_I32_I_I]], [[WHILE_BODY_I34_I_I]] ] +// CHECK-NEXT: br i1 [[OR_COND_I35_I_I]], label [[WHILE_COND_I30_I_I]], label [[_ZL4NANFPKC_EXIT]], !llvm.loop [[LOOP9]] // CHECK: _ZL4nanfPKc.exit: -// CHECK-NEXT: [[RETVAL_0_I_I:%.*]] = phi i64 [ 0, [[CLEANUP_I28_I_I]] ], [ [[__R_0_I15_I_I]], [[WHILE_COND_I17_I_I]] ], [ 0, [[CLEANUP_I_I_I]] ], [ [[__R_0_I_I_I]], [[WHILE_COND_I_I_I]] ], [ 0, [[CLEANUP_I44_I_I]] ], [ [[__R_0_I31_I_I]], [[WHILE_COND_I33_I_I]] ] +// CHECK-NEXT: [[RETVAL_0_I_I:%.*]] = phi i64 [ 0, [[CLEANUP_I20_I_I]] ], [ [[__R_0_I16_I_I]], [[WHILE_COND_I14_I_I]] ], [ 0, [[CLEANUP_I_I_I]] ], [ [[__R_0_I_I_I]], [[WHILE_COND_I_I_I]] ], [ 0, [[CLEANUP_I36_I_I]] ], [ [[__R_0_I32_I_I]], [[WHILE_COND_I30_I_I]] ] // CHECK-NEXT: [[CONV_I:%.*]] = trunc i64 [[RETVAL_0_I_I]] to i32 // CHECK-NEXT: [[BF_VALUE_I:%.*]] = and i32 [[CONV_I]], 4194303 // CHECK-NEXT: [[BF_SET9_I:%.*]] = or i32 [[BF_VALUE_I]], 2143289344 @@ -1917,11 +1916,11 @@ extern "C" __device__ float test_nanf(const char *tag) { // CHECK-NEXT: entry: // CHECK-NEXT: [[TMP0:%.*]] = load i8, ptr [[TAG:%.*]], align 1, !tbaa [[TBAA3]] // CHECK-NEXT: [[CMP_I_I:%.*]] = icmp eq i8 [[TMP0]], 48 -// CHECK-NEXT: br i1 [[CMP_I_I]], label [[IF_THEN_I_I:%.*]], label [[WHILE_COND_I33_I_I:%.*]] +// CHECK-NEXT: br i1 [[CMP_I_I]], label [[IF_THEN_I_I:%.*]], label [[WHILE_COND_I30_I_I:%.*]] // CHECK: if.then.i.i: // CHECK-NEXT: [[INCDEC_PTR_I_I:%.*]] = getelementptr inbounds i8, ptr [[TAG]], i64 1 // CHECK-NEXT: [[TMP1:%.*]] = load i8, ptr [[INCDEC_PTR_I_I]], align 1, !tbaa [[TBAA3]] -// CHECK-NEXT: switch i8 [[TMP1]], label [[WHILE_COND_I17_I_I:%.*]] [ +// CHECK-NEXT: switch i8 [[TMP1]], label [[WHILE_COND_I14_I_I:%.*]] [ // CHECK-NEXT: i8 120, label [[WHILE_COND_I_I_I_PREHEADER:%.*]] // CHECK-NEXT: i8 88, label [[WHILE_COND_I_I_I_PREHEADER]] // CHECK-NEXT: ] @@ -1958,50 +1957,50 @@ extern "C" __device__ float test_nanf(const char *tag) { // CHECK-NEXT: [[__R_2_I_I_I]] = phi i64 [ [[ADD28_I_I_I]], [[IF_END31_I_I_I]] ], [ [[__R_0_I_I_I]], [[IF_ELSE17_I_I_I]] ] // CHECK-NEXT: [[COND_I_I_I:%.*]] = phi i1 [ true, [[IF_END31_I_I_I]] ], [ false, [[IF_ELSE17_I_I_I]] ] // CHECK-NEXT: br i1 [[COND_I_I_I]], label [[WHILE_COND_I_I_I]], label [[_ZL3NANPKC_EXIT]], !llvm.loop [[LOOP10]] -// CHECK: while.cond.i17.i.i: -// CHECK-NEXT: [[__TAGP_ADDR_0_I14_I_I:%.*]] = phi ptr [ [[__TAGP_ADDR_1_I26_I_I:%.*]], [[CLEANUP_I28_I_I:%.*]] ], [ [[INCDEC_PTR_I_I]], [[IF_THEN_I_I]] ] -// CHECK-NEXT: [[__R_0_I15_I_I:%.*]] = phi i64 [ [[__R_1_I27_I_I:%.*]], [[CLEANUP_I28_I_I]] ], [ 0, [[IF_THEN_I_I]] ] -// CHECK-NEXT: [[TMP6:%.*]] = load i8, ptr [[__TAGP_ADDR_0_I14_I_I]], align 1, !tbaa [[TBAA3]] -// CHECK-NEXT: [[CMP_NOT_I16_I_I:%.*]] = icmp eq i8 [[TMP6]], 0 -// CHECK-NEXT: br i1 [[CMP_NOT_I16_I_I]], label [[_ZL3NANPKC_EXIT]], label [[WHILE_BODY_I19_I_I:%.*]] -// CHECK: while.body.i19.i.i: +// CHECK: while.cond.i14.i.i: +// CHECK-NEXT: [[__TAGP_ADDR_0_I15_I_I:%.*]] = phi ptr [ [[__TAGP_ADDR_1_I21_I_I:%.*]], [[CLEANUP_I20_I_I:%.*]] ], [ [[INCDEC_PTR_I_I]], [[IF_THEN_I_I]] ] +// CHECK-NEXT: [[__R_0_I16_I_I:%.*]] = phi i64 [ [[__R_1_I22_I_I:%.*]], [[CLEANUP_I20_I_I]] ], [ 0, [[IF_THEN_I_I]] ] +// CHECK-NEXT: [[TMP6:%.*]] = load i8, ptr [[__TAGP_ADDR_0_I15_I_I]], align 1, !tbaa [[TBAA3]] +// CHECK-NEXT: [[CMP_NOT_I17_I_I:%.*]] = icmp eq i8 [[TMP6]], 0 +// CHECK-NEXT: br i1 [[CMP_NOT_I17_I_I]], label [[_ZL3NANPKC_EXIT]], label [[WHILE_BODY_I18_I_I:%.*]] +// CHECK: while.body.i18.i.i: // CHECK-NEXT: [[TMP7:%.*]] = and i8 [[TMP6]], -8 -// CHECK-NEXT: [[OR_COND_I18_I_I:%.*]] = icmp eq i8 [[TMP7]], 48 -// CHECK-NEXT: br i1 [[OR_COND_I18_I_I]], label [[IF_THEN_I25_I_I:%.*]], label [[CLEANUP_I28_I_I]] -// CHECK: if.then.i25.i.i: -// CHECK-NEXT: [[MUL_I20_I_I:%.*]] = shl i64 [[__R_0_I15_I_I]], 3 -// CHECK-NEXT: [[CONV5_I21_I_I:%.*]] = sext i8 [[TMP6]] to i64 -// CHECK-NEXT: [[ADD_I22_I_I:%.*]] = add i64 [[MUL_I20_I_I]], -48 -// CHECK-NEXT: [[SUB_I23_I_I:%.*]] = add i64 [[ADD_I22_I_I]], [[CONV5_I21_I_I]] -// CHECK-NEXT: [[INCDEC_PTR_I24_I_I:%.*]] = getelementptr inbounds i8, ptr [[__TAGP_ADDR_0_I14_I_I]], i64 1 -// CHECK-NEXT: br label [[CLEANUP_I28_I_I]] -// CHECK: cleanup.i28.i.i: -// CHECK-NEXT: [[__TAGP_ADDR_1_I26_I_I]] = phi ptr [ [[INCDEC_PTR_I24_I_I]], [[IF_THEN_I25_I_I]] ], [ [[__TAGP_ADDR_0_I14_I_I]], [[WHILE_BODY_I19_I_I]] ] -// CHECK-NEXT: [[__R_1_I27_I_I]] = phi i64 [ [[SUB_I23_I_I]], [[IF_THEN_I25_I_I]] ], [ [[__R_0_I15_I_I]], [[WHILE_BODY_I19_I_I]] ] -// CHECK-NEXT: br i1 [[OR_COND_I18_I_I]], label [[WHILE_COND_I17_I_I]], label [[_ZL3NANPKC_EXIT]], !llvm.loop [[LOOP6]] -// CHECK: while.cond.i33.i.i: -// CHECK-NEXT: [[__TAGP_ADDR_0_I30_I_I:%.*]] = phi ptr [ [[__TAGP_ADDR_1_I42_I_I:%.*]], [[CLEANUP_I44_I_I:%.*]] ], [ [[TAG]], [[ENTRY:%.*]] ] -// CHECK-NEXT: [[__R_0_I31_I_I:%.*]] = phi i64 [ [[__R_1_I43_I_I:%.*]], [[CLEANUP_I44_I_I]] ], [ 0, [[ENTRY]] ] -// CHECK-NEXT: [[TMP8:%.*]] = load i8, ptr [[__TAGP_ADDR_0_I30_I_I]], align 1, !tbaa [[TBAA3]] -// CHECK-NEXT: [[CMP_NOT_I32_I_I:%.*]] = icmp eq i8 [[TMP8]], 0 -// CHECK-NEXT: br i1 [[CMP_NOT_I32_I_I]], label [[_ZL3NANPKC_EXIT]], label [[WHILE_BODY_I35_I_I:%.*]] -// CHECK: while.body.i35.i.i: +// CHECK-NEXT: [[OR_COND_I19_I_I:%.*]] = icmp eq i8 [[TMP7]], 48 +// CHECK-NEXT: br i1 [[OR_COND_I19_I_I]], label [[IF_THEN_I24_I_I:%.*]], label [[CLEANUP_I20_I_I]] +// CHECK: if.then.i24.i.i: +// CHECK-NEXT: [[MUL_I25_I_I:%.*]] = shl i64 [[__R_0_I16_I_I]], 3 +// CHECK-NEXT: [[CONV5_I26_I_I:%.*]] = sext i8 [[TMP6]] to i64 +// CHECK-NEXT: [[ADD_I27_I_I:%.*]] = add i64 [[MUL_I25_I_I]], -48 +// CHECK-NEXT: [[SUB_I28_I_I:%.*]] = add i64 [[ADD_I27_I_I]], [[CONV5_I26_I_I]] +// CHECK-NEXT: [[INCDEC_PTR_I29_I_I:%.*]] = getelementptr inbounds i8, ptr [[__TAGP_ADDR_0_I15_I_I]], i64 1 +// CHECK-NEXT: br label [[CLEANUP_I20_I_I]] +// CHECK: cleanup.i20.i.i: +// CHECK-NEXT: [[__TAGP_ADDR_1_I21_I_I]] = phi ptr [ [[INCDEC_PTR_I29_I_I]], [[IF_THEN_I24_I_I]] ], [ [[__TAGP_ADDR_0_I15_I_I]], [[WHILE_BODY_I18_I_I]] ] +// CHECK-NEXT: [[__R_1_I22_I_I]] = phi i64 [ [[SUB_I28_I_I]], [[IF_THEN_I24_I_I]] ], [ [[__R_0_I16_I_I]], [[WHILE_BODY_I18_I_I]] ] +// CHECK-NEXT: br i1 [[OR_COND_I19_I_I]], label [[WHILE_COND_I14_I_I]], label [[_ZL3NANPKC_EXIT]], !llvm.loop [[LOOP6]] +// CHECK: while.cond.i30.i.i: +// CHECK-NEXT: [[__TAGP_ADDR_0_I31_I_I:%.*]] = phi ptr [ [[__TAGP_ADDR_1_I37_I_I:%.*]], [[CLEANUP_I36_I_I:%.*]] ], [ [[TAG]], [[ENTRY:%.*]] ] +// CHECK-NEXT: [[__R_0_I32_I_I:%.*]] = phi i64 [ [[__R_1_I38_I_I:%.*]], [[CLEANUP_I36_I_I]] ], [ 0, [[ENTRY]] ] +// CHECK-NEXT: [[TMP8:%.*]] = load i8, ptr [[__TAGP_ADDR_0_I31_I_I]], align 1, !tbaa [[TBAA3]] +// CHECK-NEXT: [[CMP_NOT_I33_I_I:%.*]] = icmp eq i8 [[TMP8]], 0 +// CHECK-NEXT: br i1 [[CMP_NOT_I33_I_I]], label [[_ZL3NANPKC_EXIT]], label [[WHILE_BODY_I34_I_I:%.*]] +// CHECK: while.body.i34.i.i: // CHECK-NEXT: [[TMP9:%.*]] = add i8 [[TMP8]], -48 -// CHECK-NEXT: [[OR_COND_I34_I_I:%.*]] = icmp ult i8 [[TMP9]], 10 -// CHECK-NEXT: br i1 [[OR_COND_I34_I_I]], label [[IF_THEN_I41_I_I:%.*]], label [[CLEANUP_I44_I_I]] -// CHECK: if.then.i41.i.i: -// CHECK-NEXT: [[MUL_I36_I_I:%.*]] = mul i64 [[__R_0_I31_I_I]], 10 -// CHECK-NEXT: [[CONV5_I37_I_I:%.*]] = sext i8 [[TMP8]] to i64 -// CHECK-NEXT: [[ADD_I38_I_I:%.*]] = add i64 [[MUL_I36_I_I]], -48 -// CHECK-NEXT: [[SUB_I39_I_I:%.*]] = add i64 [[ADD_I38_I_I]], [[CONV5_I37_I_I]] -// CHECK-NEXT: [[INCDEC_PTR_I40_I_I:%.*]] = getelementptr inbounds i8, ptr [[__TAGP_ADDR_0_I30_I_I]], i64 1 -// CHECK-NEXT: br label [[CLEANUP_I44_I_I]] -// CHECK: cleanup.i44.i.i: -// CHECK-NEXT: [[__TAGP_ADDR_1_I42_I_I]] = phi ptr [ [[INCDEC_PTR_I40_I_I]], [[IF_THEN_I41_I_I]] ], [ [[__TAGP_ADDR_0_I30_I_I]], [[WHILE_BODY_I35_I_I]] ] -// CHECK-NEXT: [[__R_1_I43_I_I]] = phi i64 [ [[SUB_I39_I_I]], [[IF_THEN_I41_I_I]] ], [ [[__R_0_I31_I_I]], [[WHILE_BODY_I35_I_I]] ] -// CHECK-NEXT: br i1 [[OR_COND_I34_I_I]], label [[WHILE_COND_I33_I_I]], label [[_ZL3NANPKC_EXIT]], !llvm.loop [[LOOP9]] +// CHECK-NEXT: [[OR_COND_I35_I_I:%.*]] = icmp ult i8 [[TMP9]], 10 +// CHECK-NEXT: br i1 [[OR_COND_I35_I_I]], label [[IF_THEN_I40_I_I:%.*]], label [[CLEANUP_I36_I_I]] +// CHECK: if.then.i40.i.i: +// CHECK-NEXT: [[MUL_I41_I_I:%.*]] = mul i64 [[__R_0_I32_I_I]], 10 +// CHECK-NEXT: [[CONV5_I42_I_I:%.*]] = sext i8 [[TMP8]] to i64 +// CHECK-NEXT: [[ADD_I43_I_I:%.*]] = add i64 [[MUL_I41_I_I]], -48 +// CHECK-NEXT: [[SUB_I44_I_I:%.*]] = add i64 [[ADD_I43_I_I]], [[CONV5_I42_I_I]] +// CHECK-NEXT: [[INCDEC_PTR_I45_I_I:%.*]] = getelementptr inbounds i8, ptr [[__TAGP_ADDR_0_I31_I_I]], i64 1 +// CHECK-NEXT: br label [[CLEANUP_I36_I_I]] +// CHECK: cleanup.i36.i.i: +// CHECK-NEXT: [[__TAGP_ADDR_1_I37_I_I]] = phi ptr [ [[INCDEC_PTR_I45_I_I]], [[IF_THEN_I40_I_I]] ], [ [[__TAGP_ADDR_0_I31_I_I]], [[WHILE_BODY_I34_I_I]] ] +// CHECK-NEXT: [[__R_1_I38_I_I]] = phi i64 [ [[SUB_I44_I_I]], [[IF_THEN_I40_I_I]] ], [ [[__R_0_I32_I_I]], [[WHILE_BODY_I34_I_I]] ] +// CHECK-NEXT: br i1 [[OR_COND_I35_I_I]], label [[WHILE_COND_I30_I_I]], label [[_ZL3NANPKC_EXIT]], !llvm.loop [[LOOP9]] // CHECK: _ZL3nanPKc.exit: -// CHECK-NEXT: [[RETVAL_0_I_I:%.*]] = phi i64 [ 0, [[CLEANUP_I28_I_I]] ], [ [[__R_0_I15_I_I]], [[WHILE_COND_I17_I_I]] ], [ 0, [[CLEANUP_I_I_I]] ], [ [[__R_0_I_I_I]], [[WHILE_COND_I_I_I]] ], [ 0, [[CLEANUP_I44_I_I]] ], [ [[__R_0_I31_I_I]], [[WHILE_COND_I33_I_I]] ] +// CHECK-NEXT: [[RETVAL_0_I_I:%.*]] = phi i64 [ 0, [[CLEANUP_I20_I_I]] ], [ [[__R_0_I16_I_I]], [[WHILE_COND_I14_I_I]] ], [ 0, [[CLEANUP_I_I_I]] ], [ [[__R_0_I_I_I]], [[WHILE_COND_I_I_I]] ], [ 0, [[CLEANUP_I36_I_I]] ], [ [[__R_0_I32_I_I]], [[WHILE_COND_I30_I_I]] ] // CHECK-NEXT: [[BF_VALUE_I:%.*]] = and i64 [[RETVAL_0_I_I]], 2251799813685247 // CHECK-NEXT: [[BF_SET9_I:%.*]] = or i64 [[BF_VALUE_I]], 9221120237041090560 // CHECK-NEXT: [[TMP10:%.*]] = bitcast i64 [[BF_SET9_I]] to double diff --git a/clang/test/Lexer/header.cpp b/clang/test/Lexer/header.cpp index f02b1e69db439..34ed2686b0e72 100644 --- a/clang/test/Lexer/header.cpp +++ b/clang/test/Lexer/header.cpp @@ -1,5 +1,5 @@ // RUN: %clang_cc1 -fsyntax-only -Wno-header-guard %s -// RUN: %clang_cc1 -fsyntax-only -Wheader-guard %s 2>&1 | FileCheck %s +// RUN: %clang_cc1 -fsyntax-only -Wheader-guard -fno-diagnostics-show-line-numbers %s 2>&1 | FileCheck %s #include "Inputs/good-header-guard.h" #include "Inputs/no-define.h" diff --git a/clang/test/Lexer/string-literal-errors.cpp b/clang/test/Lexer/string-literal-errors.cpp index 223dca4b94f62..c819ba435dbd2 100644 --- a/clang/test/Lexer/string-literal-errors.cpp +++ b/clang/test/Lexer/string-literal-errors.cpp @@ -1,4 +1,4 @@ -// RUN: not %clang_cc1 -fsyntax-only %s 2>&1 | FileCheck -strict-whitespace %s +// RUN: not %clang_cc1 -fsyntax-only -fno-diagnostics-show-line-numbers %s 2>&1 | FileCheck -strict-whitespace %s void foo() { (void)"\q \u123z \x \U \U123 \U12345 \u123 \xyzzy \777 \U" diff --git a/clang/test/Misc/caret-diags-macros.c b/clang/test/Misc/caret-diags-macros.c index e60ed389e656c..13b084b853acc 100644 --- a/clang/test/Misc/caret-diags-macros.c +++ b/clang/test/Misc/caret-diags-macros.c @@ -1,4 +1,4 @@ -// RUN: %clang_cc1 -fsyntax-only %s 2>&1 | FileCheck %s -strict-whitespace +// RUN: %clang_cc1 -fsyntax-only -fno-diagnostics-show-line-numbers %s 2>&1 | FileCheck %s -strict-whitespace #define M1(x) x #define M2 1; diff --git a/clang/test/Misc/caret-diags-multiline.cpp b/clang/test/Misc/caret-diags-multiline.cpp index 90b50ff398ace..baf8e5a219be3 100644 --- a/clang/test/Misc/caret-diags-multiline.cpp +++ b/clang/test/Misc/caret-diags-multiline.cpp @@ -1,4 +1,4 @@ -// RUN: not %clang_cc1 -std=c++11 -fcaret-diagnostics-max-lines 5 -Wsometimes-uninitialized %s 2>&1 | FileCheck %s --strict-whitespace +// RUN: not %clang_cc1 -std=c++11 -fno-diagnostics-show-line-numbers -fcaret-diagnostics-max-lines 5 -Wsometimes-uninitialized %s 2>&1 | FileCheck %s --strict-whitespace void line(int); diff --git a/clang/test/Misc/diag-macro-backtrace.c b/clang/test/Misc/diag-macro-backtrace.c index 8d7d5726ad82d..0eb7bbb9f3355 100644 --- a/clang/test/Misc/diag-macro-backtrace.c +++ b/clang/test/Misc/diag-macro-backtrace.c @@ -1,4 +1,4 @@ -// RUN: not %clang -fsyntax-only -fmacro-backtrace-limit=0 %s 2>&1 | FileCheck %s +// RUN: not %clang -fsyntax-only -fno-diagnostics-show-line-numbers -fmacro-backtrace-limit=0 %s 2>&1 | FileCheck %s #define FOO 1+"hi" #define BAR FOO diff --git a/clang/test/Misc/diag-style.cpp b/clang/test/Misc/diag-style.cpp new file mode 100644 index 0000000000000..b12afb2cd9238 --- /dev/null +++ b/clang/test/Misc/diag-style.cpp @@ -0,0 +1,12 @@ +// RUN: not %clang_cc1 -fsyntax-only %s 2>&1 | FileCheck -strict-whitespace %s + +/// empty lines in multi-line diagnostic snippets are preserved. +static_assert(false && + + true, ""); +// CHECK: static assertion failed +// CHECK-NEXT: {{^}} 4 | static_assert(false &&{{$}} +// CHECK-NEXT: {{^}} | ^~~~~~~~{{$}} +// CHECK-NEXT: {{^}} 5 | {{$}} +// CHECK-NEXT: {{^}} 6 | true, "");{{$}} +// CHECK-NEXT: {{^}} | ~~~~{{$}} diff --git a/clang/test/Misc/message-length.c b/clang/test/Misc/message-length.c index 1e0b4edb7c032..4e2818121a132 100644 --- a/clang/test/Misc/message-length.c +++ b/clang/test/Misc/message-length.c @@ -28,7 +28,7 @@ void a_very_long_line(int *ip, float *FloatPointer) { #pragma STDC CX_LIMITED_RANGE // some long comment text and a brace, eh {} // CHECK: FILE:23:78 -// CHECK: {{^ ...// some long comment text and a brace, eh {}}} +// CHECK: {{^ 23 | ...// some long comment text and a brace, eh {}}} struct A { int x; }; void h(struct A *a) { diff --git a/clang/test/Misc/tabstop.c b/clang/test/Misc/tabstop.c index 5b9bda9e541c0..834d1839a3d8b 100644 --- a/clang/test/Misc/tabstop.c +++ b/clang/test/Misc/tabstop.c @@ -1,6 +1,7 @@ -// RUN: %clang_cc1 -ftabstop 3 -fsyntax-only -Wno-error=int-conversion %s 2>&1 | FileCheck -check-prefix=CHECK-3 -strict-whitespace %s -// RUN: %clang_cc1 -ftabstop 4 -fsyntax-only -Wno-error=int-conversion %s 2>&1 | FileCheck -check-prefix=CHECK-4 -strict-whitespace %s -// RUN: %clang_cc1 -ftabstop 5 -fsyntax-only -Wno-error=int-conversion %s 2>&1 | FileCheck -check-prefix=CHECK-5 -strict-whitespace %s +// RUN: %clang_cc1 -ftabstop 3 -fsyntax-only -Wno-error=int-conversion -fno-diagnostics-show-line-numbers %s 2>&1 | FileCheck -check-prefix=CHECK-3 -strict-whitespace %s +// RUN: %clang_cc1 -ftabstop 4 -fsyntax-only -Wno-error=int-conversion -fno-diagnostics-show-line-numbers %s 2>&1 | FileCheck -check-prefix=CHECK-4 -strict-whitespace %s +// RUN: %clang_cc1 -ftabstop 5 -fsyntax-only -Wno-error=int-conversion -fno-diagnostics-show-line-numbers %s 2>&1 | FileCheck -check-prefix=CHECK-5 -strict-whitespace %s +// RUN: %clang_cc1 -ftabstop 101 -fsyntax-only -Wno-error=int-conversion -fno-diagnostics-show-line-numbers %s 2>&1 | FileCheck -check-prefix=CHECK-101 -strict-whitespace %s // tab void* a = 1; @@ -54,3 +55,5 @@ void f(void) // CHECK-5: {{^ }} ( ) // CHECK-5: {{^ }}if (1 == 0 & 1) // CHECK-5: {{^ }} ( ) + +// CHECK-101: warning: ignoring invalid -ftabstop value '101', using default value 8 diff --git a/clang/test/Misc/unnecessary-elipses.cpp b/clang/test/Misc/unnecessary-elipses.cpp index c8c178c37f6c6..b9f7cb7d3e00e 100644 --- a/clang/test/Misc/unnecessary-elipses.cpp +++ b/clang/test/Misc/unnecessary-elipses.cpp @@ -1,4 +1,4 @@ -// RUN: %clang_cc1 -fsyntax-only -fmessage-length=80 %s 2>&1 | FileCheck -strict-whitespace %s +// RUN: %clang_cc1 -fsyntax-only -fmessage-length=80 -fno-diagnostics-show-line-numbers %s 2>&1 | FileCheck -strict-whitespace %s int main() { "xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx"; diff --git a/clang/test/Misc/unprintable.c b/clang/test/Misc/unprintable.c index 30e4494566300..02402cdfa6693 100644 --- a/clang/test/Misc/unprintable.c +++ b/clang/test/Misc/unprintable.c @@ -1,4 +1,4 @@ -// RUN: not %clang_cc1 %s -fmessage-length=40 2>&1 | FileCheck -strict-whitespace %s +// RUN: not %clang_cc1 %s -fmessage-length=40 -fno-diagnostics-show-line-numbers 2>&1 | FileCheck -strict-whitespace %s int main() { int i; diff --git a/clang/test/Misc/wrong-encoding.c b/clang/test/Misc/wrong-encoding.c index 4d8aa94ffffb2..98c1ecb9b5a66 100644 --- a/clang/test/Misc/wrong-encoding.c +++ b/clang/test/Misc/wrong-encoding.c @@ -1,4 +1,4 @@ -// RUN: %clang_cc1 -fsyntax-only -Wno-unused-value %s 2>&1 | FileCheck %s +// RUN: %clang_cc1 -fsyntax-only -Wno-unused-value -fno-diagnostics-show-line-numbers %s 2>&1 | FileCheck %s // REQUIRES: asserts void foo(void) { diff --git a/clang/test/Modules/Inputs/filename/a.h b/clang/test/Modules/Inputs/filename/a.h deleted file mode 100644 index 8f896a9ba8f41..0000000000000 --- a/clang/test/Modules/Inputs/filename/a.h +++ /dev/null @@ -1 +0,0 @@ -const char *p = __FILE__; diff --git a/clang/test/Modules/Inputs/filename/module.map b/clang/test/Modules/Inputs/filename/module.map deleted file mode 100644 index ff164ad7bac8e..0000000000000 --- a/clang/test/Modules/Inputs/filename/module.map +++ /dev/null @@ -1,3 +0,0 @@ -module "A" { - header "a.h" -} diff --git a/clang/test/Modules/filename.cpp b/clang/test/Modules/filename.cpp index e2b5ad141891f..7c42a7eddee38 100644 --- a/clang/test/Modules/filename.cpp +++ b/clang/test/Modules/filename.cpp @@ -1,8 +1,17 @@ -// RUN: cd %S -// RUN: %clang_cc1 -I. -fmodule-name=A -fmodule-map-file=%S/Inputs/filename/module.map %s -E | FileCheck %s +// RUN: rm -rf %t +// RUN: split-file %s %t -#include "Inputs/filename/a.h" +//--- include/a.h +const char *p = __FILE__; +//--- include/module.modulemap +module "A" { header "a.h" } +//--- src/tu.cpp +#include "a.h" + +// RUN: cd %t +// RUN: %clang_cc1 -I ./include -fmodule-name=A -fmodule-map-file=%t/include/module.modulemap %t/src/tu.cpp -E | FileCheck %s // Make sure that headers that are referenced by module maps have __FILE__ -// reflect the include path they were found with. -// CHECK: const char *p = "./Inputs/filename/a.h" +// reflect the include path they were found with. (We make sure they cannot be +// found relative to the includer.) +// CHECK: const char *p = "./include{{/|\\\\}}a.h" diff --git a/clang/test/Modules/implicit-module-header-maps.cpp b/clang/test/Modules/implicit-module-header-maps.cpp index a190ff78f306f..bd4aeb640fb3c 100644 --- a/clang/test/Modules/implicit-module-header-maps.cpp +++ b/clang/test/Modules/implicit-module-header-maps.cpp @@ -7,6 +7,7 @@ // // RUN: %clang -Rmodule-build -fmodules -fimplicit-modules -fimplicit-module-maps -fmodule-map-file=module.modulemap -fsyntax-only -I hmap -fmodules-cache-path=%t test.cpp // +// RUN: cd %T // RUN: rm -rf %t // RUN: split-file %s %t // RUN: cd %t diff --git a/clang/test/OpenMP/declare_target_messages.cpp b/clang/test/OpenMP/declare_target_messages.cpp index ed011a8c3a593..482d3dc8cff30 100644 --- a/clang/test/OpenMP/declare_target_messages.cpp +++ b/clang/test/OpenMP/declare_target_messages.cpp @@ -233,6 +233,42 @@ int MultiDevTy; #pragma omp declare target to(MultiDevTy) device_type(host) // omp45-error {{unexpected 'device_type' clause, only 'to' or 'link' clauses expected}} omp5-error {{'device_type(host)' does not match previously specified 'device_type(any)' for the same declaration}} omp51-error {{'device_type(host)' does not match previously specified 'device_type(any)' for the same declaration}} omp52-error {{unexpected 'to' clause, use 'enter' instead}} omp52-error {{expected at least one 'enter', 'link' or 'indirect' clause}} #pragma omp declare target to(MultiDevTy) device_type(nohost) // omp45-error {{unexpected 'device_type' clause, only 'to' or 'link' clauses expected}} omp5-error {{'device_type(nohost)' does not match previously specified 'device_type(any)' for the same declaration}} // omp51-error {{'device_type(nohost)' does not match previously specified 'device_type(any)' for the same declaration}} omp52-error {{unexpected 'to' clause, use 'enter' instead}} omp52-error {{expected at least one 'enter', 'link' or 'indirect' clause}} +static int variable = 100; //expected-warning {{declaration is not declared in any declare target region}} +static float variable1 = 200; +static float variable2 = variable1; //expected-warning {{declaration is not declared in any declare target region}} + +static int var = 1; //expected-warning {{declaration is not declared in any declare target region}} + +static int var1 = 10; +static int *var2 = &var1; +static int **ptr1 = &var2; //expected-warning {{declaration is not declared in any declare target region}} + +int arr[2] = {1,2}; +int (*arrptr)[2] = &arr; //expected-warning {{declaration is not declared in any declare target region}} + +class declare{ + public: int x; + void print(); +}; +declare obj1; +declare *obj2 = &obj1; //expected-warning {{declaration is not declared in any declare target region}} + +struct target{ + int x; + void print(); +}; +static target S; //expected-warning {{declaration is not declared in any declare target region}} + +#pragma omp declare target +int target_var = variable; //expected-note {{used here}} +float target_var1 = variable2; //expected-note {{used here}} +int *ptr = &var; //expected-note {{used here}} +int ***ptr2 = &ptr1; //expected-note {{used here}} +int (**ptr3)[2] = &arrptr; //expected-note {{used here}} +declare **obj3 = &obj2; //expected-note {{used here}} +target *S1 = &S; //expected-note {{used here}} +#pragma omp end declare target + #if TESTENDINC #include "unterminated_declare_target_include.h" #elif TESTEND diff --git a/clang/test/OpenMP/declare_target_variables_ast_print.cpp b/clang/test/OpenMP/declare_target_variables_ast_print.cpp new file mode 100644 index 0000000000000..1e37efe20989c --- /dev/null +++ b/clang/test/OpenMP/declare_target_variables_ast_print.cpp @@ -0,0 +1,112 @@ +// RUN: %clang_cc1 -w -verify -fopenmp -I %S/Inputs -ast-print %s | FileCheck %s --check-prefix=CHECK +// expected-no-diagnostics + +static int variable = 100; +static float variable1 = 200; +static float variable2 = variable1; + +static int var = 1; + +static int var1 = 10; +static int *var2 = &var1; +static int **ptr1 = &var2; + +int arr[2] = {1,2}; +int (*arrptr)[2] = &arr; + +class declare{ + public: int x; + void print(); +}; +declare obj1; +declare *obj2 = &obj1; + +struct target{ + int x; + void print(); +}; +static target S; + +#pragma omp declare target +int target_var = variable; +float target_var1 = variable2; +int *ptr = &var; +int ***ptr2 = &ptr1; +int (**ptr3)[2] = &arrptr; +declare **obj3 = &obj2; +target *S1 = &S; +#pragma omp end declare target +// CHECK: #pragma omp declare target +// CHECK-NEXT: static int variable = 100; +// CHECK-NEXT: #pragma omp end declare target + +// CHECK-NEXT: #pragma omp declare target +// CHECK-NEXT: static float variable1 = 200; +// CHECK-NEXT: #pragma omp end declare target +// CHECK-NEXT: #pragma omp declare target +// CHECK-NEXT: static float variable2 = variable1; +// CHECK-NEXT: #pragma omp end declare target + +// CHECK: #pragma omp declare target +// CHECK-NEXT: static int var = 1; +// CHECK-NEXT: #pragma omp end declare target + +// CHECK-NEXT: #pragma omp declare target +// CHECK-NEXT: static int var1 = 10; +// CHECK-NEXT: #pragma omp end declare target +// CHECK-NEXT: #pragma omp declare target +// CHECK-NEXT: static int *var2 = &var1; +// CHECK-NEXT: #pragma omp end declare target +// CHECK-NEXT: #pragma omp declare target +// CHECK-NEXT: static int **ptr1 = &var2; +// CHECK-NEXT: #pragma omp end declare target + +// CHECK-NEXT: #pragma omp declare target +// CHECK-NEXT: int arr[2] = {1, 2}; +// CHECK-NEXT: #pragma omp end declare target +// CHECK-NEXT: #pragma omp declare target +// CHECK-NEXT: int (*arrptr)[2] = &arr; +// CHECK-NEXT: #pragma omp end declare target + +// CHECK-NEXT: class declare { +// CHECK-NEXT: public: +// CHECK-NEXT: int x; +// CHECK-NEXT: void print(); +// CHECK-NEXT: }; +// CHECK-NEXT: #pragma omp declare target +// CHECK-NEXT: declare obj1; +// CHECK-NEXT: #pragma omp end declare target +// CHECK-NEXT: #pragma omp declare target +// CHECK-NEXT: declare *obj2 = &obj1; +// CHECK-NEXT: #pragma omp end declare target + +// CHECK-NEXT: struct target { +// CHECK-NEXT: int x; +// CHECK-NEXT: void print(); +// CHECK-NEXT: }; +// CHECK-NEXT: #pragma omp declare target +// CHECK-NEXT: static target S; +// CHECK-NEXT: #pragma omp end declare target + +// CHECK-NEXT: #pragma omp declare target +// CHECK-NEXT: int target_var = variable; +// CHECK-NEXT: #pragma omp end declare target +// CHECK-NEXT: #pragma omp declare target +// CHECK-NEXT: float target_var1 = variable2; +// CHECK-NEXT: #pragma omp end declare target +// CHECK-NEXT: #pragma omp declare target +// CHECK-NEXT: int *ptr = &var; +// CHECK-NEXT: #pragma omp end declare target +// CHECK-NEXT: #pragma omp declare target +// CHECK-NEXT: int ***ptr2 = &ptr1; +// CHECK-NEXT: #pragma omp end declare target +// CHECK-NEXT: #pragma omp declare target +// CHECK-NEXT: int (**ptr3)[2] = &arrptr; +// CHECK-NEXT: #pragma omp end declare target +// CHECK-NEXT: #pragma omp declare target +// CHECK-NEXT: declare **obj3 = &obj2; +// CHECK-NEXT: #pragma omp end declare target +// CHECK-NEXT: #pragma omp declare target +// CHECK-NEXT: target *S1 = &S; +// CHECK-NEXT: #pragma omp end declare target + diff --git a/clang/test/OpenMP/for_reduction_codegen.cpp b/clang/test/OpenMP/for_reduction_codegen.cpp index 9c3bc03c2e16e..2866a79f6de4b 100644 --- a/clang/test/OpenMP/for_reduction_codegen.cpp +++ b/clang/test/OpenMP/for_reduction_codegen.cpp @@ -1,4 +1,4 @@ -// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --function-signature --include-generated-funcs --replace-value-regex "__omp_offloading_[0-9a-z]+_[0-9a-z]+" "reduction_size[.].+[.]" "pl_cond[.].+[.|,]" --prefix-filecheck-ir-name _ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --function-signature --check-globals --include-generated-funcs --replace-value-regex "__omp_offloading_[0-9a-z]+_[0-9a-z]+" "reduction_size[.].+[.]" "pl_cond[.].+[.|,]" --prefix-filecheck-ir-name _ --global-value-regex ".gomp_critical_user[a-zA-Z_.]+" // RUN: %clang_cc1 -verify -fopenmp -x c++ -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK1 // RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple x86_64-apple-darwin10 -emit-pch -o %t %s // RUN: %clang_cc1 -fopenmp -x c++ -triple x86_64-apple-darwin10 -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK1 @@ -527,6 +527,14 @@ int main() { #endif +//. +// CHECK1: @.gomp_critical_user_.reduction.var = common global [8 x i32] zeroinitializer, align 8 +// CHECK1: @.gomp_critical_user_.atomic_reduction.var = common global [8 x i32] zeroinitializer, align 8 +//. +// CHECK3: @.gomp_critical_user_.reduction.var = common global [8 x i32] zeroinitializer, align 8 +//. +// CHECK4: @.gomp_critical_user_.reduction.var = common global [8 x i32] zeroinitializer, align 8 +//. // CHECK1-LABEL: define {{[^@]+}}@main // CHECK1-SAME: () #[[ATTR0:[0-9]+]] { // CHECK1-NEXT: entry: diff --git a/clang/test/OpenMP/nvptx_target_exceptions_messages.cpp b/clang/test/OpenMP/nvptx_target_exceptions_messages.cpp index 87ea00a90822e..a0e9b98d837aa 100644 --- a/clang/test/OpenMP/nvptx_target_exceptions_messages.cpp +++ b/clang/test/OpenMP/nvptx_target_exceptions_messages.cpp @@ -95,7 +95,7 @@ int (*C)() = &foobar3; // expected-warning {{declaration is not declared in any int (*D)() = C; // expected-note {{used here}} // host-note@-1 {{used here}} #pragma omp end declare target -int foobar3() { throw 1; } +int foobar3() { throw 1; } // expected-error {{cannot use 'throw' with exceptions disabled}} // Check no infinite recursion in deferred diagnostic emitter. long E = (long)&E; diff --git a/clang/test/OpenMP/target_uses_allocators.c b/clang/test/OpenMP/target_uses_allocators.c index eab202671e793..0352a5874bf12 100644 --- a/clang/test/OpenMP/target_uses_allocators.c +++ b/clang/test/OpenMP/target_uses_allocators.c @@ -64,6 +64,35 @@ void fie(void) { {} } +typedef enum omp_memspace_handle_t { + omp_default_mem_space = 0, + omp_large_cap_mem_space = 1, + omp_const_mem_space = 2, + omp_high_bw_mem_space = 3, + omp_low_lat_mem_space = 4, + llvm_omp_target_host_mem_space = 100, + llvm_omp_target_shared_mem_space = 101, + llvm_omp_target_device_mem_space = 102, + KMP_MEMSPACE_MAX_HANDLE = __UINTPTR_MAX__ +} omp_memspace_handle_t; + +extern omp_allocator_handle_t +omp_init_allocator(omp_memspace_handle_t memspace, int ntraits, + const omp_alloctrait_t traits[]); + +void *omp_aligned_alloc(unsigned long alignment, unsigned long size, + omp_allocator_handle_t allocator); +extern void * omp_alloc(int size, omp_allocator_handle_t a); +#define N 1024 + +void foo() { + int errors = 0; + omp_memspace_handle_t memspace = omp_default_mem_space; + omp_alloctrait_t traits[1] = {{omp_atk_alignment, 64}}; + omp_allocator_handle_t alloc = omp_init_allocator(memspace,1,traits); + #pragma omp target map(tofrom: errors) uses_allocators(alloc(traits)) + { } +} #endif // CHECK: %[[#R0:]] = call i32 @__kmpc_global_thread_num(ptr @1) @@ -140,3 +169,15 @@ void fie(void) { // CHECK: [[ALLOCATOR:%.+]] = load i64, ptr [[MY_ALLOCATOR_ADDR]], // CHECK: [[CONV:%.+]] = inttoptr i64 [[ALLOCATOR]] to ptr // CHECK: call void @__kmpc_destroy_allocator(i32 %{{.+}}, ptr [[CONV]]) + +// CHECK: [[TRAITS_ADDR_REF:%.+]] = alloca ptr, +// CHECK: [[MY_ALLOCATOR_ADDR:%alloc]] = alloca i64, +// CHECK: [[TRAITS_ADDR:%.+]] = load ptr, ptr [[TRAITS_ADDR_REF]], +// CHECK: [[ALLOCATOR:%.+]] = call ptr @__kmpc_init_allocator(i32 %{{.+}}, ptr null, i32 1, ptr [[TRAITS_ADDR]]) +// CHECK: [[CONV:%.+]] = ptrtoint ptr [[ALLOCATOR]] to i64 +// CHECK: store i64 [[CONV]], ptr [[MY_ALLOCATOR_ADDR]], + +// Destroy allocator upon exit from the region. +// CHECK: [[ALLOCATOR:%.+]] = load i64, ptr [[MY_ALLOCATOR_ADDR]], +// CHECK: [[CONV1:%.+]] = inttoptr i64 [[ALLOCATOR]] to ptr +// CHECK: call void @__kmpc_destroy_allocator(i32 %{{.+}}, ptr [[CONV1]]) diff --git a/clang/test/OpenMP/unroll_codegen_parallel_for_factor.cpp b/clang/test/OpenMP/unroll_codegen_parallel_for_factor.cpp index 44127525b2527..a710d889a0b6d 100644 --- a/clang/test/OpenMP/unroll_codegen_parallel_for_factor.cpp +++ b/clang/test/OpenMP/unroll_codegen_parallel_for_factor.cpp @@ -21,7 +21,7 @@ extern "C" void body(...) {} // IR-NEXT: store i32 %[[START:.+]], ptr %[[START_ADDR]], align 4 // IR-NEXT: store i32 %[[END:.+]], ptr %[[END_ADDR]], align 4 // IR-NEXT: store i32 %[[STEP:.+]], ptr %[[STEP_ADDR]], align 4 -// IR-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @2, i32 3, ptr @func.omp_outlined, ptr %[[END_ADDR]], ptr %[[STEP_ADDR]], ptr %[[START_ADDR]]) +// IR-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @2, i32 3, ptr @func.omp_outlined, ptr %[[START_ADDR]], ptr %[[END_ADDR]], ptr %[[STEP_ADDR]]) // IR-NEXT: ret void // IR-NEXT: } extern "C" void func(int start, int end, int step) { @@ -36,9 +36,9 @@ extern "C" void func(int start, int end, int step) { // IR-NEXT: [[ENTRY:.*]]: // IR-NEXT: %[[DOTGLOBAL_TID__ADDR:.+]] = alloca ptr, align 8 // IR-NEXT: %[[DOTBOUND_TID__ADDR:.+]] = alloca ptr, align 8 +// IR-NEXT: %[[START_ADDR:.+]] = alloca ptr, align 8 // IR-NEXT: %[[END_ADDR:.+]] = alloca ptr, align 8 // IR-NEXT: %[[STEP_ADDR:.+]] = alloca ptr, align 8 -// IR-NEXT: %[[START_ADDR:.+]] = alloca ptr, align 8 // IR-NEXT: %[[DOTOMP_IV:.+]] = alloca i32, align 4 // IR-NEXT: %[[TMP:.+]] = alloca i32, align 4 // IR-NEXT: %[[I:.+]] = alloca i32, align 4 @@ -57,12 +57,12 @@ extern "C" void func(int start, int end, int step) { // IR-NEXT: %[[DOTUNROLL_INNER_IV_I:.+]] = alloca i32, align 4 // IR-NEXT: store ptr %[[DOTGLOBAL_TID_:.+]], ptr %[[DOTGLOBAL_TID__ADDR]], align 8 // IR-NEXT: store ptr %[[DOTBOUND_TID_:.+]], ptr %[[DOTBOUND_TID__ADDR]], align 8 +// IR-NEXT: store ptr %[[START:.+]], ptr %[[START_ADDR]], align 8 // IR-NEXT: store ptr %[[END:.+]], ptr %[[END_ADDR]], align 8 // IR-NEXT: store ptr %[[STEP:.+]], ptr %[[STEP_ADDR]], align 8 -// IR-NEXT: store ptr %[[START:.+]], ptr %[[START_ADDR]], align 8 +// IR-NEXT: %[[TMP2:.+]] = load ptr, ptr %[[START_ADDR]], align 8 // IR-NEXT: %[[TMP0:.+]] = load ptr, ptr %[[END_ADDR]], align 8 // IR-NEXT: %[[TMP1:.+]] = load ptr, ptr %[[STEP_ADDR]], align 8 -// IR-NEXT: %[[TMP2:.+]] = load ptr, ptr %[[START_ADDR]], align 8 // IR-NEXT: %[[TMP3:.+]] = load i32, ptr %[[TMP2]], align 4 // IR-NEXT: store i32 %[[TMP3]], ptr %[[I]], align 4 // IR-NEXT: %[[TMP4:.+]] = load i32, ptr %[[TMP2]], align 4 diff --git a/clang/test/Parser/attr-order.cpp b/clang/test/Parser/attr-order.cpp index 9a8490d819ee3..10bad38cac644 100644 --- a/clang/test/Parser/attr-order.cpp +++ b/clang/test/Parser/attr-order.cpp @@ -13,12 +13,21 @@ struct [[]] __attribute__((lockable)) [[]] __declspec(dllexport) H {}; // ok [[noreturn]] __declspec(dllexport) __attribute__((cdecl)) void b(); // ok [[]] [[noreturn]] __attribute__((cdecl)) __declspec(dllexport) void c(); // ok -// [[]] attributes before a declaration must be at the start of the line. __declspec(dllexport) [[noreturn]] __attribute__((cdecl)) void d(); // expected-error {{an attribute list cannot appear here}} __declspec(dllexport) __attribute__((cdecl)) [[noreturn]] void e(); // expected-error {{an attribute list cannot appear here}} __attribute__((cdecl)) __declspec(dllexport) [[noreturn]] void f(); // expected-error {{an attribute list cannot appear here}} -__attribute__((cdecl)) [[noreturn]] __declspec(dllexport) void g(); + +__attribute__((cdecl)) [[noreturn]] __declspec(dllexport) void g(); // ok [[noreturn]] __attribute__((cdecl)) [[]] __declspec(dllexport) void h(); + +template +__attribute__((cdecl)) [[noreturn]] __declspec(dllexport) void i(); // ok + +template +[[]] [[noreturn]] __attribute__((cdecl)) __declspec(dllexport) void j(); // ok + +template +[[noreturn]] __declspec(dllexport) __attribute__((cdecl)) void k(); // ok diff --git a/clang/test/Parser/brackets.c b/clang/test/Parser/brackets.c index a651c35d073a8..1821747d13515 100644 --- a/clang/test/Parser/brackets.c +++ b/clang/test/Parser/brackets.c @@ -2,7 +2,7 @@ // RUN: cp %s %t // RUN: not %clang_cc1 -fixit %t -x c -DFIXIT // RUN: %clang_cc1 -fsyntax-only %t -x c -DFIXIT -// RUN: not %clang_cc1 -fsyntax-only -fdiagnostics-parseable-fixits %s 2>&1 | FileCheck %s -strict-whitespace +// RUN: not %clang_cc1 -fsyntax-only -fdiagnostics-parseable-fixits -fno-diagnostics-show-line-numbers %s 2>&1 | FileCheck %s -strict-whitespace void test1(void) { int a[] = {0,1,1,2,3}; diff --git a/clang/test/Parser/brackets.cpp b/clang/test/Parser/brackets.cpp index 415cbdda83f5f..40b08c37a06a1 100644 --- a/clang/test/Parser/brackets.cpp +++ b/clang/test/Parser/brackets.cpp @@ -2,7 +2,7 @@ // RUN: cp %s %t // RUN: not %clang_cc1 -fixit %t -x c++ -DFIXIT // RUN: %clang_cc1 -fsyntax-only %t -x c++ -DFIXIT -// RUN: not %clang_cc1 -fsyntax-only -fdiagnostics-parseable-fixits %s 2>&1 | FileCheck %s -strict-whitespace +// RUN: not %clang_cc1 -fsyntax-only -fdiagnostics-parseable-fixits -fno-diagnostics-show-line-numbers %s 2>&1 | FileCheck %s -strict-whitespace void test1() { int a[] = {0,1,1,2,3}; diff --git a/clang/test/Parser/c2x-attribute-keywords.c b/clang/test/Parser/c2x-attribute-keywords.c new file mode 100644 index 0000000000000..757dc82860110 --- /dev/null +++ b/clang/test/Parser/c2x-attribute-keywords.c @@ -0,0 +1,119 @@ +// RUN: %clang_cc1 -fsyntax-only -triple aarch64-none-linux-gnu -target-feature +sme -verify=expected,notc2x -Wno-strict-prototypes %s +// RUN: %clang_cc1 -fsyntax-only -triple aarch64-none-linux-gnu -target-feature +sme -verify=expected,c2x %s + +enum __arm_streaming E { // expected-error {{'__arm_streaming' cannot be applied to a declaration}} + One __arm_streaming, // expected-error {{'__arm_streaming' cannot be applied to a declaration}} + Two, + Three __arm_streaming // expected-error {{'__arm_streaming' cannot be applied to a declaration}} +}; + +enum __arm_streaming { Four }; // expected-error {{'__arm_streaming' cannot be applied to a declaration}} +__arm_streaming enum E2 { Five }; // expected-error {{misplaced '__arm_streaming'}} + +// FIXME: this diagnostic can be improved. +enum { __arm_streaming Six }; // expected-error {{expected identifier}} + +// FIXME: this diagnostic can be improved. +enum E3 __arm_streaming { Seven }; // expected-error {{expected identifier or '('}} + +struct __arm_streaming S1 { // expected-error {{'__arm_streaming' cannot be applied to a declaration}} + int i __arm_streaming; // expected-error {{'__arm_streaming' only applies to function types}} + int __arm_streaming j; // expected-error {{'__arm_streaming' only applies to function types}} + int k[10] __arm_streaming; // expected-error {{'__arm_streaming' only applies to function types}} + int l __arm_streaming[10]; // expected-error {{'__arm_streaming' only applies to function types}} + __arm_streaming int m, n; // expected-error {{'__arm_streaming' only applies to function types}} + int o __arm_streaming : 12; // expected-error {{'__arm_streaming' only applies to function types}} + int __arm_streaming : 0; // expected-error {{'__arm_streaming' only applies to function types}} + int p, __arm_streaming : 0; // expected-error {{'__arm_streaming' cannot appear here}} + int q, __arm_streaming r; // expected-error {{'__arm_streaming' cannot appear here}} + __arm_streaming int; // expected-error {{'__arm_streaming' cannot appear here}} \ + // expected-warning {{declaration does not declare anything}} +}; + +__arm_streaming struct S2 { int a; }; // expected-error {{misplaced '__arm_streaming'}} +struct S3 __arm_streaming { int a; }; // expected-error {{'__arm_streaming' cannot appear here}} \ + expected-error {{'__arm_streaming' cannot be applied to a declaration}} + +union __arm_streaming U { // expected-error {{'__arm_streaming' cannot be applied to a declaration}} + double d __arm_streaming; // expected-error {{'__arm_streaming' only applies to function types; type here is 'double'}} + __arm_streaming int i; // expected-error {{'__arm_streaming' only applies to function types; type here is 'int'}} +}; + +__arm_streaming union U2 { double d; }; // expected-error {{misplaced '__arm_streaming'}} +union U3 __arm_streaming { double d; }; // expected-error {{'__arm_streaming' cannot appear here}} \ + expected-error {{'__arm_streaming' cannot be applied to a declaration}} + +struct __arm_streaming IncompleteStruct; // expected-error {{'__arm_streaming' cannot be applied to a declaration}} +union __arm_streaming IncompleteUnion; // expected-error {{'__arm_streaming' cannot be applied to a declaration}} +enum __arm_streaming IncompleteEnum; // expected-error {{'__arm_streaming' cannot be applied to a declaration}} + +__arm_streaming void f1(void); // expected-error {{'__arm_streaming' cannot be applied to a declaration}} +void __arm_streaming f2(void); // expected-error {{'__arm_streaming' only applies to function types}} +void f3 __arm_streaming (void); // expected-error {{'__arm_streaming' cannot be applied to a declaration}} +void f4(void) __arm_streaming; + +void f5(int i __arm_streaming, __arm_streaming int j, int __arm_streaming k); // expected-error 3 {{'__arm_streaming' only applies to function types}} + +void f6(a, b) __arm_streaming int a; int b; { // expected-error {{'__arm_streaming' cannot appear here}} \ + c2x-warning {{deprecated}} +} + +// FIXME: technically, an attribute list cannot appear here, but we currently +// parse it as part of the return type of the function, which is reasonable +// behavior given that we *don't* want to parse it as part of the K&R parameter +// declarations. It is disallowed to avoid a parsing ambiguity we already +// handle well. +int (*f7(a, b))(int, int) __arm_streaming int a; int b; { // c2x-warning {{deprecated}} + return 0; +} + +__arm_streaming int a, b; // expected-error {{'__arm_streaming' only applies to function types}} +int c __arm_streaming, d __arm_streaming; // expected-error 2 {{'__arm_streaming' only applies to function types}} + +void f8(void) __arm_streaming { + __arm_streaming int i, j; // expected-error {{'__arm_streaming' only applies to function types}} + int k, l __arm_streaming; // expected-error {{'__arm_streaming' only applies to function types}} +} + +__arm_streaming void f9(void) { // expected-error {{'__arm_streaming' cannot be applied to a declaration}} + int i[10] __arm_streaming; // expected-error {{'__arm_streaming' only applies to function types}} + int (*fp1)(void)__arm_streaming; + int (*fp2 __arm_streaming)(void); // expected-error {{'__arm_streaming' cannot be applied to a declaration}} + + int * __arm_streaming *ipp; // expected-error {{'__arm_streaming' only applies to function types}} +} + +void f10(int j[static 10] __arm_streaming, int k[*] __arm_streaming); // expected-error 2 {{'__arm_streaming' only applies to function types}} + +void f11(void) { + __arm_streaming {} // expected-error {{'__arm_streaming' cannot be applied to a statement}} + __arm_streaming if (1) {} // expected-error {{'__arm_streaming' cannot be applied to a statement}} + + __arm_streaming switch (1) { // expected-error {{'__arm_streaming' cannot be applied to a statement}} + __arm_streaming case 1: __arm_streaming break; // expected-error 2 {{'__arm_streaming' cannot be applied to a statement}} + __arm_streaming default: break; // expected-error {{'__arm_streaming' cannot be applied to a statement}} + } + + goto foo; + __arm_streaming foo: (void)1; // expected-error {{'__arm_streaming' cannot be applied to a declaration}} + + __arm_streaming for (;;); // expected-error {{'__arm_streaming' cannot be applied to a statement}} + __arm_streaming while (1); // expected-error {{'__arm_streaming' cannot be applied to a statement}} + __arm_streaming do __arm_streaming { } while(1); // expected-error 2 {{'__arm_streaming' cannot be applied to a statement}} + + __arm_streaming (void)1; // expected-error {{'__arm_streaming' cannot be applied to a statement}} + + __arm_streaming; // expected-error {{'__arm_streaming' cannot be applied to a statement}} + + (void)sizeof(int [4]__arm_streaming); // expected-error {{'__arm_streaming' only applies to function types}} + (void)sizeof(struct __arm_streaming S3 { int a __arm_streaming; }); // expected-error {{'__arm_streaming' cannot be applied to a declaration}} \ + // expected-error {{'__arm_streaming' only applies to function types; type here is 'int'}} + + __arm_streaming return; // expected-error {{'__arm_streaming' cannot be applied to a statement}} + + __arm_streaming asm (""); // expected-error {{'__arm_streaming' cannot appear here}} +} + +struct __arm_streaming S4 *s; // expected-error {{'__arm_streaming' cannot appear here}} +struct S5 {}; +int c = sizeof(struct __arm_streaming S5); // expected-error {{'__arm_streaming' cannot appear here}} diff --git a/clang/test/Parser/c2x-attribute-keywords.m b/clang/test/Parser/c2x-attribute-keywords.m new file mode 100644 index 0000000000000..d1c45da34fbc6 --- /dev/null +++ b/clang/test/Parser/c2x-attribute-keywords.m @@ -0,0 +1,19 @@ +// RUN: %clang_cc1 -fsyntax-only -triple aarch64-none-linux-gnu -target-feature +sme -verify %s + +enum __arm_streaming E1 : int; // expected-error {{'__arm_streaming' cannot be applied to a declaration}} + +@interface Base +@end + +@interface S : Base +- (void) bar; +@end + +@interface T : Base +- (S *) foo; +@end + + +void f(T *t) { + __arm_streaming[[t foo] bar]; // expected-error {{'__arm_streaming' cannot be applied to a statement}} +} diff --git a/clang/test/Parser/cxx0x-keyword-attributes.cpp b/clang/test/Parser/cxx0x-keyword-attributes.cpp new file mode 100644 index 0000000000000..256a834e9e546 --- /dev/null +++ b/clang/test/Parser/cxx0x-keyword-attributes.cpp @@ -0,0 +1,345 @@ +// RUN: %clang_cc1 -fcxx-exceptions -fdeclspec -fexceptions -fsyntax-only -verify -std=c++11 -Wc++14-compat -Wc++14-extensions -Wc++17-extensions -triple aarch64-none-linux-gnu %s + +// Need std::initializer_list +namespace std { + typedef decltype(sizeof(int)) size_t; + + // libc++'s implementation + template + class initializer_list + { + const _E* __begin_; + size_t __size_; + + initializer_list(const _E* __b, size_t __s) + : __begin_(__b), + __size_(__s) + {} + + public: + typedef _E value_type; + typedef const _E& reference; + typedef const _E& const_reference; + typedef size_t size_type; + + typedef const _E* iterator; + typedef const _E* const_iterator; + + initializer_list() : __begin_(nullptr), __size_(0) {} + + size_t size() const {return __size_;} + const _E* begin() const {return __begin_;} + const _E* end() const {return __begin_ + __size_;} + }; +} + + +// Declaration syntax checks +__arm_streaming int before_attr; // expected-error {{'__arm_streaming' only applies to function types}} +int __arm_streaming between_attr; // expected-error {{'__arm_streaming' only applies to function types}} +const __arm_streaming int between_attr_2 = 0; // expected-error {{'__arm_streaming' cannot appear here}} +int after_attr __arm_streaming; // expected-error {{'__arm_streaming' only applies to function types}} +int * __arm_streaming ptr_attr; // expected-error {{'__arm_streaming' only applies to function types}} +int & __arm_streaming ref_attr = after_attr; // expected-error {{'__arm_streaming' only applies to function types}} +int && __arm_streaming rref_attr = 0; // expected-error {{'__arm_streaming' only applies to function types}} +int array_attr [1] __arm_streaming; // expected-error {{'__arm_streaming' only applies to function types}} +void fn_attr () __arm_streaming; +void noexcept_fn_attr () noexcept __arm_streaming; +struct MemberFnOrder { + virtual void f() const volatile && noexcept __arm_streaming final = 0; +}; +struct __arm_streaming struct_attr; // expected-error {{'__arm_streaming' cannot be applied to a declaration}} +class __arm_streaming class_attr {}; // expected-error {{'__arm_streaming' cannot be applied to a declaration}} +union __arm_streaming union_attr; // expected-error {{'__arm_streaming' cannot be applied to a declaration}} +enum __arm_streaming E { }; // expected-error {{'__arm_streaming' cannot be applied to a declaration}} +namespace test_misplacement { +__arm_streaming struct struct_attr2; // expected-error {{misplaced '__arm_streaming'}} +__arm_streaming class class_attr2; // expected-error {{misplaced '__arm_streaming'}} +__arm_streaming union union_attr2; // expected-error {{misplaced '__arm_streaming'}} +__arm_streaming enum E2 { }; // expected-error {{misplaced '__arm_streaming'}} +} + +// Checks attributes placed at wrong syntactic locations of class specifiers. +class __arm_streaming __arm_streaming // expected-error 2 {{'__arm_streaming' cannot be applied to a declaration}} + attr_after_class_name_decl __arm_streaming __arm_streaming; // expected-error {{'__arm_streaming' cannot appear here}} \ + expected-error 2 {{'__arm_streaming' cannot be applied to a declaration}} + +class __arm_streaming __arm_streaming // expected-error 2 {{'__arm_streaming' cannot be applied to a declaration}} + attr_after_class_name_definition __arm_streaming __arm_streaming __arm_streaming{}; // expected-error {{'__arm_streaming' cannot appear here}} \ + expected-error 3 {{'__arm_streaming' cannot be applied to a declaration}} + +class __arm_streaming c {}; // expected-error {{'__arm_streaming' cannot be applied to a declaration}} +class c __arm_streaming __arm_streaming x; // expected-error 2 {{'__arm_streaming' only applies to function types}} +class c __arm_streaming __arm_streaming y __arm_streaming __arm_streaming; // expected-error 4 {{'__arm_streaming' only applies to function types}} +class c final [(int){0}]; + +class base {}; +class __arm_streaming __arm_streaming final_class // expected-error 2 {{'__arm_streaming' cannot be applied to a declaration}} + __arm_streaming alignas(float) final // expected-error {{'__arm_streaming' cannot appear here}} \ + expected-error {{'__arm_streaming' cannot be applied to a declaration}} + __arm_streaming alignas(float) __arm_streaming alignas(float): base{}; // expected-error {{'__arm_streaming' cannot appear here}} + +class __arm_streaming __arm_streaming final_class_another // expected-error 2 {{'__arm_streaming' cannot be applied to a declaration}} + __arm_streaming __arm_streaming alignas(16) final // expected-error {{'__arm_streaming' cannot appear here}} \ + expected-error 2 {{'__arm_streaming' cannot be applied to a declaration}} + __arm_streaming __arm_streaming alignas(16) __arm_streaming{}; // expected-error {{'__arm_streaming' cannot appear here}} + +class after_class_close {} __arm_streaming; // expected-error {{'__arm_streaming' cannot appear here, place it after "class" to apply it to the type declaration}} + +class C {}; + +__arm_streaming struct with_init_declarators {} init_declarator; // expected-error {{'__arm_streaming' only applies to function types}} +__arm_streaming struct no_init_declarators; // expected-error {{misplaced '__arm_streaming'}} +template __arm_streaming struct no_init_declarators_template; // expected-error {{'__arm_streaming' cannot appear here}} +void fn_with_structs() { + __arm_streaming struct with_init_declarators {} init_declarator; // expected-error {{'__arm_streaming' only applies to function types}} + __arm_streaming struct no_init_declarators; // expected-error {{'__arm_streaming' cannot appear here}} +} +__arm_streaming; // expected-error {{'__arm_streaming' cannot be applied to a declaration}} +struct ctordtor { + __arm_streaming ctordtor __arm_streaming () __arm_streaming; // expected-error 2 {{'__arm_streaming' cannot be applied to a declaration}} + ctordtor (C) __arm_streaming; + __arm_streaming ~ctordtor __arm_streaming () __arm_streaming; // expected-error 2 {{'__arm_streaming' cannot be applied to a declaration}} +}; +__arm_streaming ctordtor::ctordtor __arm_streaming () __arm_streaming {} // expected-error 2 {{'__arm_streaming' cannot be applied to a declaration}} +__arm_streaming ctordtor::ctordtor (C) __arm_streaming try {} catch (...) {} // expected-error {{'__arm_streaming' cannot be applied to a declaration}} +__arm_streaming ctordtor::~ctordtor __arm_streaming () __arm_streaming {} // expected-error 2 {{'__arm_streaming' cannot be applied to a declaration}} +extern "C++" __arm_streaming int extern_attr; // expected-error {{'__arm_streaming' only applies to function types}} +template __arm_streaming void template_attr (); // expected-error {{'__arm_streaming' cannot be applied to a declaration}} +__arm_streaming __arm_streaming int __arm_streaming __arm_streaming multi_attr __arm_streaming __arm_streaming; // expected-error 6 {{'__arm_streaming' only applies to function types}} + +int (paren_attr) __arm_streaming; // expected-error {{'__arm_streaming' cannot appear here}} +unsigned __arm_streaming int attr_in_decl_spec; // expected-error {{'__arm_streaming' cannot appear here}} +unsigned __arm_streaming int __arm_streaming const double_decl_spec = 0; // expected-error 2 {{'__arm_streaming' cannot appear here}} +class foo { + void const_after_attr () __arm_streaming const; // expected-error {{expected ';'}} +}; +extern "C++" __arm_streaming { } // expected-error {{'__arm_streaming' cannot appear here}} +__arm_streaming extern "C++" { } // expected-error {{'__arm_streaming' cannot appear here}} +__arm_streaming template void before_template_attr (); // expected-error {{'__arm_streaming' cannot appear here}} +__arm_streaming namespace ns { int i; } // expected-error {{'__arm_streaming' cannot appear here}} +__arm_streaming static_assert(true, ""); //expected-error {{'__arm_streaming' cannot appear here}} +__arm_streaming asm(""); // expected-error {{'__arm_streaming' cannot appear here}} + +__arm_streaming using ns::i; // expected-warning {{ISO C++}} \ + expected-error {{'__arm_streaming' cannot be applied to a declaration}} +__arm_streaming using namespace ns; // expected-error {{'__arm_streaming' cannot be applied to a declaration}} +namespace __arm_streaming ns2 {} // expected-warning {{attributes on a namespace declaration are a C++17 extension}} \ + expected-error {{'__arm_streaming' cannot be applied to a declaration}} + +using __arm_streaming alignas(4)__arm_streaming ns::i; // expected-warning 2 {{ISO C++}} \ + expected-error {{'__arm_streaming' cannot appear here}} \ + expected-error {{'alignas' attribute only applies to variables, data members and tag types}} \ + expected-warning {{ISO C++}} \ + expected-error 2 {{'__arm_streaming' cannot be applied to a declaration}} +using __arm_streaming alignas(4) __arm_streaming foobar = int; // expected-error {{'__arm_streaming' cannot appear here}} \ + expected-error {{'alignas' attribute only applies to}} \ + expected-error 2 {{'__arm_streaming' only applies to function types}} + +__arm_streaming using T = int; // expected-error {{'__arm_streaming' cannot appear here}} +using T __arm_streaming = int; // expected-error {{'__arm_streaming' only applies to function types}} +template using U __arm_streaming = T; // expected-error {{'__arm_streaming' only applies to function types}} +using ns::i __arm_streaming; // expected-warning {{ISO C++}} \ + expected-error {{'__arm_streaming' cannot be applied to a declaration}} +using ns::i __arm_streaming, ns::i __arm_streaming; // expected-warning 2 {{ISO C++}} \ + expected-warning {{use of multiple declarators in a single using declaration is a C++17 extension}} \ + expected-error 2 {{'__arm_streaming' cannot be applied to a declaration}} +struct using_in_struct_base { + typedef int i, j, k, l; +}; +struct using_in_struct : using_in_struct_base { + __arm_streaming using using_in_struct_base::i; // expected-warning {{ISO C++}} \ + expected-error {{'__arm_streaming' cannot be applied to a declaration}} + using using_in_struct_base::j __arm_streaming; // expected-warning {{ISO C++}} \ + expected-error {{'__arm_streaming' cannot be applied to a declaration}} + __arm_streaming using using_in_struct_base::k __arm_streaming, using_in_struct_base::l __arm_streaming; // expected-warning 3 {{ISO C++}} \ + expected-warning {{use of multiple declarators in a single using declaration is a C++17 extension}} \ + expected-error 4 {{'__arm_streaming' cannot be applied to a declaration}} +}; +using __arm_streaming ns::i; // expected-warning {{ISO C++}} \ + expected-error {{'__arm_streaming' cannot appear here}} \ + expected-error {{'__arm_streaming' cannot be applied to a declaration}} +using T __arm_streaming = int; // expected-error {{'__arm_streaming' only applies to function types}} + +auto trailing() -> __arm_streaming const int; // expected-error {{'__arm_streaming' cannot appear here}} +auto trailing() -> const __arm_streaming int; // expected-error {{'__arm_streaming' cannot appear here}} +auto trailing() -> const int __arm_streaming; // expected-error {{'__arm_streaming' only applies to function types}} +auto trailing_2() -> struct struct_attr __arm_streaming; // expected-error {{'__arm_streaming' only applies to function types}} + +namespace N { + struct S {}; +}; +template struct Template {}; + +// FIXME: Improve this diagnostic +struct __arm_streaming N::S s; // expected-error {{'__arm_streaming' cannot appear here}} +struct __arm_streaming Template t; // expected-error {{'__arm_streaming' cannot appear here}} +struct __arm_streaming ::template Template u; // expected-error {{'__arm_streaming' cannot appear here}} +template struct __arm_streaming Template; // expected-error {{'__arm_streaming' cannot appear here}} +template struct __attribute__((pure)) Template; // We still allow GNU-style attributes here +template <> struct __arm_streaming Template; // expected-error {{'__arm_streaming' cannot be applied to a declaration}} + +enum __arm_streaming E1 {}; // expected-error {{'__arm_streaming' cannot be applied to a declaration}} +enum __arm_streaming E2; // expected-error {{forbids forward references}} \ + expected-error {{'__arm_streaming' cannot be applied to a declaration}} +enum __arm_streaming E1; // expected-error {{'__arm_streaming' cannot be applied to a declaration}} +enum __arm_streaming E3 : int; // expected-error {{'__arm_streaming' cannot be applied to a declaration}} +enum __arm_streaming { // expected-error {{'__arm_streaming' cannot be applied to a declaration}} + k_123 __arm_streaming = 123 // expected-warning {{attributes on an enumerator declaration are a C++17 extension}} \ + expected-error {{'__arm_streaming' cannot be applied to a declaration}} +}; +enum __arm_streaming E1 e; // expected-error {{'__arm_streaming' cannot appear here}} +enum __arm_streaming class E4 { }; // expected-error {{'__arm_streaming' cannot appear here}} +enum struct __arm_streaming E5; // expected-error {{'__arm_streaming' cannot be applied to a declaration}} +enum E6 {} __arm_streaming; // expected-error {{'__arm_streaming' cannot appear here, place it after "enum" to apply it to the type declaration}} + +struct S { + friend int f __arm_streaming (); // expected-error {{'__arm_streaming' cannot appear here}} \ + expected-error {{'__arm_streaming' cannot be applied to a declaration}} + friend int f2 __arm_streaming () {} // expected-error {{'__arm_streaming' cannot be applied to a declaration}} + __arm_streaming friend int g(); // expected-error {{'__arm_streaming' cannot appear here}} + __arm_streaming friend int h() { // expected-error {{'__arm_streaming' cannot be applied to a declaration}} + } + __arm_streaming friend int f3(), f4(), f5(); // expected-error {{'__arm_streaming' cannot appear here}} + friend int f6 __arm_streaming (), f7 __arm_streaming (), f8 __arm_streaming (); // expected-error3 {{'__arm_streaming' cannot appear here}} \ + expected-error 3 {{'__arm_streaming' cannot be applied to a declaration}} + friend class __arm_streaming C; // expected-error {{'__arm_streaming' cannot appear here}} + __arm_streaming friend class D; // expected-error {{'__arm_streaming' cannot appear here}} + __arm_streaming friend int; // expected-error {{'__arm_streaming' cannot appear here}} +}; +template void tmpl (T) {} +template __arm_streaming void tmpl(char); // expected-error {{'__arm_streaming' cannot appear here}} +template void __arm_streaming tmpl(short); // expected-error {{'__arm_streaming' only applies to function types}} + +// Statement tests +void foo () { + __arm_streaming ; // expected-error {{'__arm_streaming' cannot be applied to a statement}} + __arm_streaming { } // expected-error {{'__arm_streaming' cannot be applied to a statement}} + __arm_streaming if (0) { } // expected-error {{'__arm_streaming' cannot be applied to a statement}} + __arm_streaming for (;;); // expected-error {{'__arm_streaming' cannot be applied to a statement}} + __arm_streaming do { // expected-error {{'__arm_streaming' cannot be applied to a statement}} + __arm_streaming continue; // expected-error {{'__arm_streaming' cannot be applied to a statement}} + } while (0); + __arm_streaming while (0); // expected-error {{'__arm_streaming' cannot be applied to a statement}} + + __arm_streaming switch (i) { // expected-error {{'__arm_streaming' cannot be applied to a statement}} + __arm_streaming case 0: // expected-error {{'__arm_streaming' cannot be applied to a statement}} + __arm_streaming default: // expected-error {{'__arm_streaming' cannot be applied to a statement}} + __arm_streaming break; // expected-error {{'__arm_streaming' cannot be applied to a statement}} + } + + __arm_streaming goto there; // expected-error {{'__arm_streaming' cannot be applied to a statement}} + __arm_streaming there: // expected-error {{'__arm_streaming' cannot be applied to a declaration}} + + __arm_streaming try { // expected-error {{'__arm_streaming' cannot be applied to a statement}} + } __arm_streaming catch (...) { // expected-error {{'__arm_streaming' cannot appear here}} + } + + void bar __arm_streaming (__arm_streaming int i, __arm_streaming int j); // expected-error 2 {{'__arm_streaming' only applies to function types}} \ + expected-error {{'__arm_streaming' cannot be applied to a declaration}} + using FuncType = void (__arm_streaming int); // expected-error {{'__arm_streaming' only applies to function types}} + void baz(__arm_streaming...); // expected-error {{expected parameter declarator}} + + __arm_streaming return; // expected-error {{'__arm_streaming' cannot be applied to a statement}} +} + +// Expression tests +void bar () { + new int[42]__arm_streaming[5]__arm_streaming{}; // expected-error {{'__arm_streaming' only applies to function types}} +} + +// Condition tests +void baz () { + if (__arm_streaming bool b = true) { // expected-error {{'__arm_streaming' only applies to function types}} + switch (__arm_streaming int n { 42 }) { // expected-error {{'__arm_streaming' only applies to function types}} + default: + for (__arm_streaming int n = 0; __arm_streaming char b = n < 5; ++b) { // expected-error 2 {{'__arm_streaming' only applies to function types}} + } + } + } + int x; + // An attribute can be applied to an expression-statement, such as the first + // statement in a for. But it can't be applied to a condition which is an + // expression. + for (__arm_streaming x = 0; ; ) {} // expected-error {{'__arm_streaming' cannot appear here}} + for (; __arm_streaming x < 5; ) {} // expected-error {{'__arm_streaming' cannot appear here}} + while (__arm_streaming bool k { false }) { // expected-error {{'__arm_streaming' only applies to function types}} + } + while (__arm_streaming true) { // expected-error {{'__arm_streaming' cannot appear here}} + } + do { + } while (__arm_streaming false); // expected-error {{'__arm_streaming' cannot appear here}} + + for (__arm_streaming int n : { 1, 2, 3 }) { // expected-error {{'__arm_streaming' only applies to function types}} + } +} + +enum class __attribute__((visibility("hidden"))) SecretKeepers { + one, /* rest are deprecated */ two, three +}; +enum class __arm_streaming EvenMoreSecrets {}; // expected-error {{'__arm_streaming' cannot be applied to a declaration}} + +// Forbid attributes on decl specifiers. +unsigned __arm_streaming static int __arm_streaming v1; // expected-error {{'__arm_streaming' only applies to function types}} \ + expected-error {{'__arm_streaming' cannot appear here}} +typedef __arm_streaming unsigned long __arm_streaming v2; // expected-error {{'__arm_streaming' only applies to function types}} \ + expected-error {{'__arm_streaming' cannot appear here}} +int __arm_streaming foo(int __arm_streaming x); // expected-error 2 {{'__arm_streaming' only applies to function types}} + +__arm_streaming; // expected-error {{'__arm_streaming' cannot be applied to a declaration}} + +class A { + A(__arm_streaming int a); // expected-error {{'__arm_streaming' only applies to function types}} +}; +A::A(__arm_streaming int a) {} // expected-error {{'__arm_streaming' only applies to function types}} + +template struct TemplateStruct {}; +class FriendClassesWithAttributes { + // We allow GNU-style attributes here + template friend class __attribute__((__type_visibility__("default"))) vector; + template friend class __declspec(code_seg("foo,whatever")) vector2; + // But not C++11 ones + template friend class __arm_streaming vector3; // expected-error {{'__arm_streaming' cannot appear here}} + + // Also allowed + friend struct __attribute__((__type_visibility__("default"))) TemplateStruct; + friend struct __declspec(code_seg("foo,whatever")) TemplateStruct; + friend struct __arm_streaming TemplateStruct; // expected-error {{'__arm_streaming' cannot appear here}} +}; + +// Check ordering: C++11 attributes must appear before GNU attributes. +class Ordering { + void f1( + int (__arm_streaming __attribute__(()) int n) // expected-error {{'__arm_streaming' only applies to function types}} + ) { + } + + void f2( + int (*)(__arm_streaming __attribute__(()) int n) // expected-error {{'__arm_streaming' only applies to function types}} + ) { + } + + void f3( + int (__attribute__(()) __arm_streaming int n) // expected-error {{'__arm_streaming' cannot appear here}} + ) { + } + + void f4( + int (*)(__attribute__(()) __arm_streaming int n) // expected-error {{'__arm_streaming' cannot appear here}} + ) { + } +}; + +namespace base_specs { +struct A {}; +struct B : __arm_streaming A {}; // expected-error {{'__arm_streaming' cannot be applied to a base specifier}} +struct C : __arm_streaming virtual A {}; // expected-error {{'__arm_streaming' cannot be applied to a base specifier}} +struct D : __arm_streaming public virtual A {}; // expected-error {{'__arm_streaming' cannot be applied to a base specifier}} +struct E : public __arm_streaming virtual A {}; // expected-error {{'__arm_streaming' cannot appear here}} \ + expected-error {{'__arm_streaming' cannot be applied to a base specifier}} +struct F : virtual __arm_streaming public A {}; // expected-error {{'__arm_streaming' cannot appear here}} \ + expected-error {{'__arm_streaming' cannot be applied to a base specifier}} +} + +namespace __arm_streaming ns_attr {}; // expected-error {{'__arm_streaming' cannot be applied to a declaration}} \ + expected-warning {{attributes on a namespace declaration are a C++17 extension}} diff --git a/clang/test/Preprocessor/macro-reserved.c b/clang/test/Preprocessor/macro-reserved.c index 14dbc9119943f..6026a9f60730e 100644 --- a/clang/test/Preprocessor/macro-reserved.c +++ b/clang/test/Preprocessor/macro-reserved.c @@ -7,6 +7,7 @@ #define _HAVE_X 0 #define X__Y #define __STDC__ 1 // expected-warning {{redefining builtin macro}} +#define __clang__ 1 #undef for #undef final @@ -15,6 +16,12 @@ #undef _HAVE_X #undef X__Y #undef __STDC_HOSTED__ // expected-warning {{undefining builtin macro}} +#undef __INT32_TYPE__ +#undef __UINT32_TYPE__ +#undef __UINTPTR_TYPE__ +#undef __UINT64_TYPE__ +#undef __INT64_TYPE__ +#undef __OPTIMIZE__ // allowlisted definitions #define while while diff --git a/clang/test/Preprocessor/ucn-pp-identifier.c b/clang/test/Preprocessor/ucn-pp-identifier.c index e1bcdfdcaa364..0cdff6e9db568 100644 --- a/clang/test/Preprocessor/ucn-pp-identifier.c +++ b/clang/test/Preprocessor/ucn-pp-identifier.c @@ -112,9 +112,9 @@ C 1 #define capital_u_\U00FC // expected-warning@-1 {{incomplete universal character name}} expected-note@-1 {{did you mean to use '\u'?}} expected-warning@-1 {{whitespace}} // CHECK: note: did you mean to use '\u'? -// CHECK-NEXT: #define capital_u_\U00FC -// CHECK-NEXT: {{^ \^}} -// CHECK-NEXT: {{^ u}} +// CHECK-NEXT: {{^ 112 | #define capital_u_\U00FC}} +// CHECK-NEXT: {{^ | \^}} +// CHECK-NEXT: {{^ | u}} #define \u{} // expected-warning {{empty delimited universal character name; treating as '\' 'u' '{' '}'}} expected-error {{macro name must be an identifier}} #define \u1{123} // expected-warning {{incomplete universal character name; treating as '\' followed by identifier}} expected-error {{macro name must be an identifier}} diff --git a/clang/test/Preprocessor/undef-x86.c b/clang/test/Preprocessor/undef-x86.c new file mode 100644 index 0000000000000..91f16d3aae3ab --- /dev/null +++ b/clang/test/Preprocessor/undef-x86.c @@ -0,0 +1,12 @@ +// RUN: %clang_cc1 -triple=i386-none-none -fsyntax-only -verify %s +// RUN: %clang_cc1 -triple=x86_64-none-none -fsyntax-only -verify %s + +// Check that we can undefine triple-specific defines without warning +// expected-no-diagnostics +#undef __i386 +#undef __i386__ +#undef i386 +#undef __amd64 +#undef __amd64__ +#undef __x86_64 +#undef __x86_64__ diff --git a/clang/test/Sema/atomic-ops.c b/clang/test/Sema/atomic-ops.c index 6ac47e12f2446..4fa1223b3038f 100644 --- a/clang/test/Sema/atomic-ops.c +++ b/clang/test/Sema/atomic-ops.c @@ -131,7 +131,7 @@ void f(_Atomic(int) *i, const _Atomic(int) *ci, _Atomic(int*) *p, _Atomic(float) *f, _Atomic(double) *d, _Atomic(long double) *ld, int *I, const int *CI, - int **P, float *D, struct S *s1, struct S *s2) { + int **P, float *F, double *D, struct S *s1, struct S *s2) { __c11_atomic_init(I, 5); // expected-error {{pointer to _Atomic}} __c11_atomic_init(ci, 5); // expected-error {{address argument to atomic operation must be a pointer to non-const _Atomic type ('const _Atomic(int) *' invalid)}} @@ -199,14 +199,27 @@ void f(_Atomic(int) *i, const _Atomic(int) *ci, __c11_atomic_fetch_add(f, 1.0f, memory_order_seq_cst); __c11_atomic_fetch_add(d, 1.0, memory_order_seq_cst); __c11_atomic_fetch_add(ld, 1.0, memory_order_seq_cst); // fp80-error {{must be a pointer to atomic integer, pointer or supported floating point type}} + __c11_atomic_fetch_min(i, 1, memory_order_seq_cst); + __c11_atomic_fetch_min(p, 1, memory_order_seq_cst); // expected-error {{must be a pointer to atomic integer or supported floating point type}} + __c11_atomic_fetch_min(f, 1.0f, memory_order_seq_cst); + __c11_atomic_fetch_min(d, 1.0, memory_order_seq_cst); + __c11_atomic_fetch_min(ld, 1.0, memory_order_seq_cst); // fp80-error {{must be a pointer to atomic integer or supported floating point type}} + __c11_atomic_fetch_max(i, 1, memory_order_seq_cst); + __c11_atomic_fetch_max(p, 1, memory_order_seq_cst); // expected-error {{must be a pointer to atomic integer or supported floating point type}} + __c11_atomic_fetch_max(f, 1.0f, memory_order_seq_cst); + __c11_atomic_fetch_max(d, 1.0, memory_order_seq_cst); + __c11_atomic_fetch_max(ld, 1.0, memory_order_seq_cst); // fp80-error {{must be a pointer to atomic integer or supported floating point type}} __atomic_fetch_add(i, 3, memory_order_seq_cst); // expected-error {{pointer to integer, pointer or supported floating point type}} __atomic_fetch_sub(I, 3, memory_order_seq_cst); __atomic_fetch_sub(P, 3, memory_order_seq_cst); - __atomic_fetch_sub(D, 3, memory_order_seq_cst); + __atomic_fetch_sub(F, 3, memory_order_seq_cst); __atomic_fetch_sub(s1, 3, memory_order_seq_cst); // expected-error {{must be a pointer to integer, pointer or supported floating point type}} - __atomic_fetch_min(D, 3, memory_order_seq_cst); // expected-error {{must be a pointer to integer}} - __atomic_fetch_max(P, 3, memory_order_seq_cst); // expected-error {{must be a pointer to integer}} + __atomic_fetch_min(F, 3, memory_order_seq_cst); + __atomic_fetch_min(D, 3, memory_order_seq_cst); + __atomic_fetch_max(F, 3, memory_order_seq_cst); + __atomic_fetch_max(D, 3, memory_order_seq_cst); + __atomic_fetch_max(P, 3, memory_order_seq_cst); // expected-error {{must be a pointer to integer or supported floating point type}} __atomic_fetch_max(p, 3); // expected-error {{too few arguments to function call, expected 3, have 2}} __c11_atomic_fetch_and(i, 1, memory_order_seq_cst); @@ -216,7 +229,7 @@ void f(_Atomic(int) *i, const _Atomic(int) *ci, __atomic_fetch_and(i, 3, memory_order_seq_cst); // expected-error {{pointer to integer}} __atomic_fetch_or(I, 3, memory_order_seq_cst); __atomic_fetch_xor(P, 3, memory_order_seq_cst); // expected-error {{must be a pointer to integer}} - __atomic_fetch_or(D, 3, memory_order_seq_cst); // expected-error {{must be a pointer to integer}} + __atomic_fetch_or(F, 3, memory_order_seq_cst); // expected-error {{must be a pointer to integer}} __atomic_fetch_and(s1, 3, memory_order_seq_cst); // expected-error {{must be a pointer to integer}} _Bool cmpexch_1 = __c11_atomic_compare_exchange_strong(i, I, 1, memory_order_seq_cst, memory_order_seq_cst); diff --git a/clang/test/Sema/caret-diags-complex-init.cpp b/clang/test/Sema/caret-diags-complex-init.cpp index d8a1b7837a640..83aab5c4e0b7d 100644 --- a/clang/test/Sema/caret-diags-complex-init.cpp +++ b/clang/test/Sema/caret-diags-complex-init.cpp @@ -1,4 +1,4 @@ -// RUN: not %clang_cc1 -std=c++11 -fsyntax-only -fcaret-diagnostics-max-lines 5 %s 2>&1 | FileCheck %s -strict-whitespace +// RUN: not %clang_cc1 -std=c++11 -fsyntax-only -fno-diagnostics-show-line-numbers -fcaret-diagnostics-max-lines 5 %s 2>&1 | FileCheck %s -strict-whitespace //CHECK: {{.*}}: error: excess elements in scalar initializer diff --git a/clang/test/SemaCXX/auto-type-from-cxx.cpp b/clang/test/SemaCXX/auto-type-from-cxx.cpp index 21620f73be7e9..5cd48991ffb7a 100644 --- a/clang/test/SemaCXX/auto-type-from-cxx.cpp +++ b/clang/test/SemaCXX/auto-type-from-cxx.cpp @@ -18,3 +18,21 @@ int d() { new __auto_type; // expected-error {{'__auto_type' not allowed in type allocated by 'new'}} } +namespace TestDeductionFail { + +template +void caller(T x) {x.fun();} // expected-note {{candidate template ignored: substitution failure [with T = TestDeductionFail::Abstract]: parameter type 'TestDeductionFail::Abstract' is an abstract class}} + +template +auto getCaller(){ + return caller; // expected-error {{cannot deduce return type 'auto' from returned value of type ''}} +} + +class Abstract{ + public: + void fun(); + virtual void vfun()=0; + void call(){getCaller()(*this);} // expected-note {{in instantiation of function template specialization 'TestDeductionFail::getCaller' requested here}} +}; + +} diff --git a/clang/test/SemaCXX/paren-list-agg-init.cpp b/clang/test/SemaCXX/paren-list-agg-init.cpp index 7bdf49b8fd0c1..042ce3b3ddce2 100644 --- a/clang/test/SemaCXX/paren-list-agg-init.cpp +++ b/clang/test/SemaCXX/paren-list-agg-init.cpp @@ -266,3 +266,9 @@ O o2(0, 0); // no-error O o3(0); // expected-error@-1 {{reference member of type 'int &&' uninitialized}} } + +namespace gh63008 { +auto a = new A('a', {1.1}); +// expected-warning@-1 {{braces around scalar init}} +// beforecxx20-warning@-2 {{aggregate initialization of type 'A' from a parenthesized list of values is a C++20 extension}} +} diff --git a/clang/test/SemaCXX/struct-class-redecl.cpp b/clang/test/SemaCXX/struct-class-redecl.cpp index 622d5a0b652a7..ab6488b237f55 100644 --- a/clang/test/SemaCXX/struct-class-redecl.cpp +++ b/clang/test/SemaCXX/struct-class-redecl.cpp @@ -1,5 +1,5 @@ -// RUN: %clang_cc1 -fsyntax-only -Wmismatched-tags -verify %s -// RUN: not %clang_cc1 -fsyntax-only -Wmismatched-tags %s 2>&1 | FileCheck %s +// RUN: %clang_cc1 -fsyntax-only -Wmismatched-tags -fno-diagnostics-show-line-numbers -verify %s +// RUN: not %clang_cc1 -fsyntax-only -Wmismatched-tags -fno-diagnostics-show-line-numbers %s 2>&1 | FileCheck %s class X; // expected-note 2{{here}} typedef struct X * X_t; // expected-warning{{previously declared}} union X { int x; float y; }; // expected-error{{use of 'X' with tag type that does not match previous declaration}} diff --git a/clang/test/SemaCXX/type-traits.cpp b/clang/test/SemaCXX/type-traits.cpp index 75f172d1c3452..d5388d4eb89be 100644 --- a/clang/test/SemaCXX/type-traits.cpp +++ b/clang/test/SemaCXX/type-traits.cpp @@ -3270,6 +3270,172 @@ struct NotTriviallyEqualityComparableHasEnum { }; static_assert(!__is_trivially_equality_comparable(NotTriviallyEqualityComparableHasEnum)); +namespace hidden_friend { + +struct TriviallyEqualityComparable { + int i; + int j; + + void func(); + bool operator==(int) const { return false; } + + friend bool operator==(const TriviallyEqualityComparable&, const TriviallyEqualityComparable&) = default; +}; +static_assert(__is_trivially_equality_comparable(TriviallyEqualityComparable), ""); + +struct TriviallyEqualityComparableNonTriviallyCopyable { + TriviallyEqualityComparableNonTriviallyCopyable(const TriviallyEqualityComparableNonTriviallyCopyable&); + ~TriviallyEqualityComparableNonTriviallyCopyable(); + friend bool operator==(const TriviallyEqualityComparableNonTriviallyCopyable&, const TriviallyEqualityComparableNonTriviallyCopyable&) = default; + int i; +}; +static_assert(__is_trivially_equality_comparable(TriviallyEqualityComparableNonTriviallyCopyable)); + +struct NotTriviallyEqualityComparableHasPadding { + short i; + int j; + + friend bool operator==(const NotTriviallyEqualityComparableHasPadding&, const NotTriviallyEqualityComparableHasPadding&) = default; +}; +static_assert(!__is_trivially_equality_comparable(NotTriviallyEqualityComparableHasPadding), ""); + +struct NotTriviallyEqualityComparableHasFloat { + float i; + int j; + + friend bool operator==(const NotTriviallyEqualityComparableHasFloat&, const NotTriviallyEqualityComparableHasFloat&) = default; +}; +static_assert(!__is_trivially_equality_comparable(NotTriviallyEqualityComparableHasFloat), ""); + +struct NotTriviallyEqualityComparableHasTailPadding { + int i; + char j; + + friend bool operator==(const NotTriviallyEqualityComparableHasTailPadding&, const NotTriviallyEqualityComparableHasTailPadding&) = default; +}; +static_assert(!__is_trivially_equality_comparable(NotTriviallyEqualityComparableHasTailPadding), ""); + +struct NotTriviallyEqualityComparableBase : NotTriviallyEqualityComparableHasTailPadding { + char j; + + friend bool operator==(const NotTriviallyEqualityComparableBase&, const NotTriviallyEqualityComparableBase&) = default; +}; +static_assert(!__is_trivially_equality_comparable(NotTriviallyEqualityComparableBase), ""); + +class TriviallyEqualityComparablePaddedOutBase { + int i; + char c; + +public: + friend bool operator==(const TriviallyEqualityComparablePaddedOutBase&, const TriviallyEqualityComparablePaddedOutBase&) = default; +}; +static_assert(!__is_trivially_equality_comparable(TriviallyEqualityComparablePaddedOutBase), ""); + +struct TriviallyEqualityComparablePaddedOut : TriviallyEqualityComparablePaddedOutBase { + char j[3]; + + friend bool operator==(const TriviallyEqualityComparablePaddedOut&, const TriviallyEqualityComparablePaddedOut&) = default; +}; +static_assert(__is_trivially_equality_comparable(TriviallyEqualityComparablePaddedOut), ""); + +struct TriviallyEqualityComparable1 { + char i; + + friend bool operator==(const TriviallyEqualityComparable1&, const TriviallyEqualityComparable1&) = default; +}; +static_assert(__is_trivially_equality_comparable(TriviallyEqualityComparable1)); + +struct TriviallyEqualityComparable2 { + int i; + + friend bool operator==(const TriviallyEqualityComparable2&, const TriviallyEqualityComparable2&) = default; +}; +static_assert(__is_trivially_equality_comparable(TriviallyEqualityComparable2)); + +struct NotTriviallyEqualityComparableTriviallyEqualityComparableBases + : TriviallyEqualityComparable1, TriviallyEqualityComparable2 { + friend bool operator==(const NotTriviallyEqualityComparableTriviallyEqualityComparableBases&, const NotTriviallyEqualityComparableTriviallyEqualityComparableBases&) = default; +}; +static_assert(!__is_trivially_equality_comparable(NotTriviallyEqualityComparableTriviallyEqualityComparableBases)); + +struct NotTriviallyEqualityComparableBitfield { + int i : 1; + + friend bool operator==(const NotTriviallyEqualityComparableBitfield&, const NotTriviallyEqualityComparableBitfield&) = default; +}; +static_assert(!__is_trivially_equality_comparable(NotTriviallyEqualityComparableBitfield)); + +// TODO: This is trivially equality comparable +struct NotTriviallyEqualityComparableBitfieldFilled { + char i : __CHAR_BIT__; + + friend bool operator==(const NotTriviallyEqualityComparableBitfieldFilled&, const NotTriviallyEqualityComparableBitfieldFilled&) = default; +}; +static_assert(!__is_trivially_equality_comparable(NotTriviallyEqualityComparableBitfield)); + +union U { + int i; + + friend bool operator==(const U&, const U&) = default; +}; + +struct NotTriviallyEqualityComparableImplicitlyDeletedOperatorByUnion { + U u; + + friend bool operator==(const NotTriviallyEqualityComparableImplicitlyDeletedOperatorByUnion&, const NotTriviallyEqualityComparableImplicitlyDeletedOperatorByUnion&) = default; +}; +static_assert(!__is_trivially_equality_comparable(NotTriviallyEqualityComparableImplicitlyDeletedOperatorByUnion)); + +struct NotTriviallyEqualityComparableExplicitlyDeleted { + int i; + + friend bool operator==(const NotTriviallyEqualityComparableExplicitlyDeleted&, const NotTriviallyEqualityComparableExplicitlyDeleted&) = delete; +}; + +struct NotTriviallyEqualityComparableImplicitlyDeletedOperatorByStruct { + NotTriviallyEqualityComparableExplicitlyDeleted u; + + friend bool operator==(const NotTriviallyEqualityComparableImplicitlyDeletedOperatorByStruct&, const NotTriviallyEqualityComparableImplicitlyDeletedOperatorByStruct&) = default; +}; +static_assert(!__is_trivially_equality_comparable(NotTriviallyEqualityComparableImplicitlyDeletedOperatorByStruct)); + +struct NotTriviallyEqualityComparableHasReferenceMember { + int& i; + + friend bool operator==(const NotTriviallyEqualityComparableHasReferenceMember&, const NotTriviallyEqualityComparableHasReferenceMember&) = default; +}; +static_assert(!__is_trivially_equality_comparable(NotTriviallyEqualityComparableHasReferenceMember)); + +enum E { + a, + b +}; +bool operator==(E, E) { return false; } +static_assert(!__is_trivially_equality_comparable(E)); + +struct NotTriviallyEqualityComparableHasEnum { + E e; + friend bool operator==(const NotTriviallyEqualityComparableHasEnum&, const NotTriviallyEqualityComparableHasEnum&) = default; +}; +static_assert(!__is_trivially_equality_comparable(NotTriviallyEqualityComparableHasEnum)); + +struct NonTriviallyEqualityComparableValueComparisonNonTriviallyCopyable { + int i; + NonTriviallyEqualityComparableValueComparisonNonTriviallyCopyable(const NonTriviallyEqualityComparableValueComparisonNonTriviallyCopyable&); + + friend bool operator==(NonTriviallyEqualityComparableValueComparisonNonTriviallyCopyable, NonTriviallyEqualityComparableValueComparisonNonTriviallyCopyable) = default; +}; +static_assert(!__is_trivially_equality_comparable(NonTriviallyEqualityComparableValueComparisonNonTriviallyCopyable)); + +struct TriviallyEqualityComparableRefComparisonNonTriviallyCopyable { + int i; + TriviallyEqualityComparableRefComparisonNonTriviallyCopyable(const TriviallyEqualityComparableRefComparisonNonTriviallyCopyable&); + + friend bool operator==(const TriviallyEqualityComparableRefComparisonNonTriviallyCopyable&, const TriviallyEqualityComparableRefComparisonNonTriviallyCopyable&) = default; +}; +static_assert(__is_trivially_equality_comparable(TriviallyEqualityComparableRefComparisonNonTriviallyCopyable)); +} + #endif // __cplusplus >= 202002L }; diff --git a/clang/test/SemaOpenCL/atomic-ops.cl b/clang/test/SemaOpenCL/atomic-ops.cl index fedf776d32b8a..209de22ecdf57 100644 --- a/clang/test/SemaOpenCL/atomic-ops.cl +++ b/clang/test/SemaOpenCL/atomic-ops.cl @@ -61,8 +61,10 @@ void f(atomic_int *i, const atomic_int *ci, __opencl_atomic_fetch_min(i, 1, memory_order_seq_cst, memory_scope_work_group); __opencl_atomic_fetch_max(i, 1, memory_order_seq_cst, memory_scope_work_group); - __opencl_atomic_fetch_min(f, 1, memory_order_seq_cst, memory_scope_work_group); // expected-error {{address argument to atomic operation must be a pointer to atomic integer ('__generic atomic_float *' (aka '__generic _Atomic(float) *') invalid)}} - __opencl_atomic_fetch_max(f, 1, memory_order_seq_cst, memory_scope_work_group); // expected-error {{address argument to atomic operation must be a pointer to atomic integer ('__generic atomic_float *' (aka '__generic _Atomic(float) *') invalid)}} + __opencl_atomic_fetch_min(f, 1, memory_order_seq_cst, memory_scope_work_group); + __opencl_atomic_fetch_max(f, 1, memory_order_seq_cst, memory_scope_work_group); + __opencl_atomic_fetch_min(d, 1, memory_order_seq_cst, memory_scope_work_group); + __opencl_atomic_fetch_max(d, 1, memory_order_seq_cst, memory_scope_work_group); bool cmpexch_1 = __opencl_atomic_compare_exchange_strong(i, I, 1, memory_order_seq_cst, memory_order_seq_cst, memory_scope_work_group); bool cmpexch_2 = __opencl_atomic_compare_exchange_strong(p, P, 1, memory_order_seq_cst, memory_order_seq_cst, memory_scope_work_group); diff --git a/clang/tools/clang-linker-wrapper/ClangLinkerWrapper.cpp b/clang/tools/clang-linker-wrapper/ClangLinkerWrapper.cpp index 2d96e0a344e11..0af0f2e371b18 100644 --- a/clang/tools/clang-linker-wrapper/ClangLinkerWrapper.cpp +++ b/clang/tools/clang-linker-wrapper/ClangLinkerWrapper.cpp @@ -1163,20 +1163,21 @@ enum Symbol : uint32_t { /// Scan the symbols from a BitcodeFile \p Buffer and record if we need to /// extract any symbols from it. Expected getSymbolsFromBitcode(MemoryBufferRef Buffer, OffloadKind Kind, - StringSaver &Saver, + bool IsArchive, StringSaver &Saver, DenseMap &Syms) { Expected IRSymtabOrErr = readIRSymtab(Buffer); if (!IRSymtabOrErr) return IRSymtabOrErr.takeError(); - bool ShouldExtract = false; + bool ShouldExtract = !IsArchive; + DenseMap TmpSyms; for (unsigned I = 0; I != IRSymtabOrErr->Mods.size(); ++I) { for (const auto &Sym : IRSymtabOrErr->TheReader.module_symbols(I)) { if (Sym.isFormatSpecific() || !Sym.isGlobal()) continue; bool NewSymbol = Syms.count(Sym.getName()) == 0; - auto &OldSym = Syms[Saver.save(Sym.getName())]; + auto OldSym = NewSymbol ? Sym_None : Syms[Sym.getName()]; // We will extract if it defines a currenlty undefined non-weak symbol. bool ResolvesStrongReference = @@ -1192,23 +1193,31 @@ Expected getSymbolsFromBitcode(MemoryBufferRef Buffer, OffloadKind Kind, // Update this symbol in the "table" with the new information. if (OldSym & Sym_Undefined && !Sym.isUndefined()) - OldSym = static_cast(OldSym & ~Sym_Undefined); + TmpSyms[Saver.save(Sym.getName())] = + static_cast(OldSym & ~Sym_Undefined); if (Sym.isUndefined() && NewSymbol) - OldSym = static_cast(OldSym | Sym_Undefined); + TmpSyms[Saver.save(Sym.getName())] = + static_cast(OldSym | Sym_Undefined); if (Sym.isWeak()) - OldSym = static_cast(OldSym | Sym_Weak); + TmpSyms[Saver.save(Sym.getName())] = + static_cast(OldSym | Sym_Weak); } } + // If the file gets extracted we update the table with the new symbols. + if (ShouldExtract) + Syms.insert(std::begin(TmpSyms), std::end(TmpSyms)); + return ShouldExtract; } /// Scan the symbols from an ObjectFile \p Obj and record if we need to extract /// any symbols from it. Expected getSymbolsFromObject(const ObjectFile &Obj, OffloadKind Kind, - StringSaver &Saver, + bool IsArchive, StringSaver &Saver, DenseMap &Syms) { - bool ShouldExtract = false; + bool ShouldExtract = !IsArchive; + DenseMap TmpSyms; for (SymbolRef Sym : Obj.symbols()) { auto FlagsOrErr = Sym.getFlags(); if (!FlagsOrErr) @@ -1223,7 +1232,7 @@ Expected getSymbolsFromObject(const ObjectFile &Obj, OffloadKind Kind, return NameOrErr.takeError(); bool NewSymbol = Syms.count(*NameOrErr) == 0; - auto &OldSym = Syms[Saver.save(*NameOrErr)]; + auto OldSym = NewSymbol ? Sym_None : Syms[*NameOrErr]; // We will extract if it defines a currenlty undefined non-weak symbol. bool ResolvesStrongReference = (OldSym & Sym_Undefined) && @@ -1240,12 +1249,19 @@ Expected getSymbolsFromObject(const ObjectFile &Obj, OffloadKind Kind, // Update this symbol in the "table" with the new information. if (OldSym & Sym_Undefined && !(*FlagsOrErr & SymbolRef::SF_Undefined)) - OldSym = static_cast(OldSym & ~Sym_Undefined); + TmpSyms[Saver.save(*NameOrErr)] = + static_cast(OldSym & ~Sym_Undefined); if (*FlagsOrErr & SymbolRef::SF_Undefined && NewSymbol) - OldSym = static_cast(OldSym | Sym_Undefined); + TmpSyms[Saver.save(*NameOrErr)] = + static_cast(OldSym | Sym_Undefined); if (*FlagsOrErr & SymbolRef::SF_Weak) - OldSym = static_cast(OldSym | Sym_Weak); + TmpSyms[Saver.save(*NameOrErr)] = static_cast(OldSym | Sym_Weak); } + + // If the file gets extracted we update the table with the new symbols. + if (ShouldExtract) + Syms.insert(std::begin(TmpSyms), std::end(TmpSyms)); + return ShouldExtract; } @@ -1255,18 +1271,19 @@ Expected getSymbolsFromObject(const ObjectFile &Obj, OffloadKind Kind, /// 1) It defines an undefined symbol in a regular object filie. /// 2) It defines a global symbol without hidden visibility that has not /// yet been defined. -Expected getSymbols(StringRef Image, OffloadKind Kind, StringSaver &Saver, +Expected getSymbols(StringRef Image, OffloadKind Kind, bool IsArchive, + StringSaver &Saver, DenseMap &Syms) { MemoryBufferRef Buffer = MemoryBufferRef(Image, ""); switch (identify_magic(Image)) { case file_magic::bitcode: - return getSymbolsFromBitcode(Buffer, Kind, Saver, Syms); + return getSymbolsFromBitcode(Buffer, Kind, IsArchive, Saver, Syms); case file_magic::elf_relocatable: { Expected> ObjFile = ObjectFile::createObjectFile(Buffer); if (!ObjFile) return ObjFile.takeError(); - return getSymbolsFromObject(**ObjFile, Kind, Saver, Syms); + return getSymbolsFromObject(**ObjFile, Kind, IsArchive, Saver, Syms); } default: return false; @@ -1341,13 +1358,14 @@ Expected> getDeviceInput(const ArgList &Args) { if (IsArchive && !WholeArchive && !Syms.count(Binary)) continue; - Expected ExtractOrErr = getSymbols( - Binary.getBinary()->getImage(), - Binary.getBinary()->getOffloadKind(), Saver, Syms[Binary]); + Expected ExtractOrErr = + getSymbols(Binary.getBinary()->getImage(), + Binary.getBinary()->getOffloadKind(), IsArchive, Saver, + Syms[Binary]); if (!ExtractOrErr) return ExtractOrErr.takeError(); - Extracted = IsArchive && !WholeArchive && *ExtractOrErr; + Extracted = !WholeArchive && *ExtractOrErr; if (!IsArchive || WholeArchive || Extracted) InputFiles.emplace_back(std::move(Binary)); diff --git a/clang/tools/libclang/CIndex.cpp b/clang/tools/libclang/CIndex.cpp index ed2ca6ae2cfe1..f7321f0efe6ef 100644 --- a/clang/tools/libclang/CIndex.cpp +++ b/clang/tools/libclang/CIndex.cpp @@ -8799,7 +8799,8 @@ CXModule clang_getModuleForFile(CXTranslationUnit TU, CXFile File) { ASTUnit &Unit = *cxtu::getASTUnit(TU); HeaderSearch &HS = Unit.getPreprocessor().getHeaderSearchInfo(); - ModuleMap::KnownHeader Header = HS.findModuleForHeader(FE); + // TODO: Make CXFile a FileEntryRef. + ModuleMap::KnownHeader Header = HS.findModuleForHeader(FE->getLastRef()); return Header.getModule(); } diff --git a/clang/unittests/AST/AttrTest.cpp b/clang/unittests/AST/AttrTest.cpp index 500e9cfa528b7..fac77ff461924 100644 --- a/clang/unittests/AST/AttrTest.cpp +++ b/clang/unittests/AST/AttrTest.cpp @@ -168,4 +168,16 @@ TEST(Attr, AnnotateType) { } } +TEST(Attr, RegularKeywordAttribute) { + auto AST = clang::tooling::buildASTFromCode(""); + auto &Ctx = AST->getASTContext(); + auto Funcref = clang::WebAssemblyFuncrefAttr::CreateImplicit(Ctx); + EXPECT_EQ(Funcref->getSyntax(), clang::AttributeCommonInfo::AS_Keyword); + ASSERT_FALSE(Funcref->isRegularKeywordAttribute()); + + auto Streaming = clang::ArmStreamingAttr::CreateImplicit(Ctx); + EXPECT_EQ(Streaming->getSyntax(), clang::AttributeCommonInfo::AS_Keyword); + ASSERT_TRUE(Streaming->isRegularKeywordAttribute()); +} + } // namespace diff --git a/clang/unittests/Analysis/FlowSensitive/TestingSupport.h b/clang/unittests/Analysis/FlowSensitive/TestingSupport.h index d5591bee12dc2..aa2b2a241b224 100644 --- a/clang/unittests/Analysis/FlowSensitive/TestingSupport.h +++ b/clang/unittests/Analysis/FlowSensitive/TestingSupport.h @@ -241,7 +241,7 @@ checkDataflow(AnalysisInputs AI, llvm::errc::invalid_argument, "Could not find the target function."); // Build the control flow graph for the target function. - auto MaybeCFCtx = ControlFlowContext::build(*Target, Context); + auto MaybeCFCtx = ControlFlowContext::build(*Target); if (!MaybeCFCtx) return MaybeCFCtx.takeError(); auto &CFCtx = *MaybeCFCtx; diff --git a/clang/unittests/Analysis/FlowSensitive/TypeErasedDataflowAnalysisTest.cpp b/clang/unittests/Analysis/FlowSensitive/TypeErasedDataflowAnalysisTest.cpp index 1d94b69cfce81..473750ad7a6cb 100644 --- a/clang/unittests/Analysis/FlowSensitive/TypeErasedDataflowAnalysisTest.cpp +++ b/clang/unittests/Analysis/FlowSensitive/TypeErasedDataflowAnalysisTest.cpp @@ -65,7 +65,7 @@ runAnalysis(llvm::StringRef Code, AnalysisT (*MakeAnalysis)(ASTContext &)) { assert(Func != nullptr); auto CFCtx = - llvm::cantFail(ControlFlowContext::build(*Func, AST->getASTContext())); + llvm::cantFail(ControlFlowContext::build(*Func)); AnalysisT Analysis = MakeAnalysis(AST->getASTContext()); DataflowAnalysisContext DACtx(std::make_unique()); diff --git a/clang/unittests/Format/ConfigParseTest.cpp b/clang/unittests/Format/ConfigParseTest.cpp index 0e47abed12472..169c93d1143eb 100644 --- a/clang/unittests/Format/ConfigParseTest.cpp +++ b/clang/unittests/Format/ConfigParseTest.cpp @@ -1022,6 +1022,23 @@ TEST(ConfigParseTest, ParsesConfigurationWithLanguages) { ParseError::Error); EXPECT_EQ(FormatStyle::LK_Cpp, Style.Language); + + Style.Language = FormatStyle::LK_Verilog; + CHECK_PARSE("---\n" + "Language: Verilog\n" + "IndentWidth: 12\n" + "---\n" + "Language: Cpp\n" + "IndentWidth: 34\n" + "...\n", + IndentWidth, 12u); + CHECK_PARSE("---\n" + "IndentWidth: 78\n" + "---\n" + "Language: Verilog\n" + "IndentWidth: 56\n" + "...\n", + IndentWidth, 56u); } TEST(ConfigParseTest, UsesLanguageForBasedOnStyle) { diff --git a/clang/unittests/Format/FormatTest.cpp b/clang/unittests/Format/FormatTest.cpp index 28a4008080566..f188ab6f581cf 100644 --- a/clang/unittests/Format/FormatTest.cpp +++ b/clang/unittests/Format/FormatTest.cpp @@ -12856,6 +12856,22 @@ TEST_F(FormatTest, FormatsAfterAccessModifiers) { " void f() {}\n" "};\n", Style); + verifyFormat("struct foo {\n" + "#ifdef FOO\n" + "#else\n" + "private:\n" + "\n" + "#endif\n" + "};", + "struct foo {\n" + "#ifdef FOO\n" + "#else\n" + "private:\n" + "\n" + "\n" + "#endif\n" + "};", + Style); Style.EmptyLineAfterAccessModifier = FormatStyle::ELAAMS_Always; verifyFormat("struct foo {\n" diff --git a/clang/unittests/Format/FormatTestObjC.cpp b/clang/unittests/Format/FormatTestObjC.cpp index 55969ff6fd4a9..0cae6e2950fe6 100644 --- a/clang/unittests/Format/FormatTestObjC.cpp +++ b/clang/unittests/Format/FormatTestObjC.cpp @@ -94,6 +94,26 @@ TEST(FormatTestObjCStyle, DetectsObjCInHeaders) { ASSERT_TRUE((bool)Style); EXPECT_EQ(FormatStyle::LK_ObjC, Style->Language); + Style = getStyle("{}", "a.h", "none", R"objc( +NS_ASSUME_NONNULL_BEGIN +extern int i; +NS_ASSUME_NONNULL_END +)objc"); + ASSERT_TRUE((bool)Style); + EXPECT_EQ(FormatStyle::LK_ObjC, Style->Language); + + Style = getStyle("{}", "a.h", "none", R"objc( +FOUNDATION_EXTERN void DoStuff(void); +)objc"); + ASSERT_TRUE((bool)Style); + EXPECT_EQ(FormatStyle::LK_ObjC, Style->Language); + + Style = getStyle("{}", "a.h", "none", R"objc( +FOUNDATION_EXPORT void DoStuff(void); +)objc"); + ASSERT_TRUE((bool)Style); + EXPECT_EQ(FormatStyle::LK_ObjC, Style->Language); + Style = getStyle("{}", "a.h", "none", "enum Foo {};"); ASSERT_TRUE((bool)Style); EXPECT_EQ(FormatStyle::LK_Cpp, Style->Language); diff --git a/clang/utils/TableGen/ClangAttrEmitter.cpp b/clang/utils/TableGen/ClangAttrEmitter.cpp index b0afcb03ec269..dc3434d61d329 100644 --- a/clang/utils/TableGen/ClangAttrEmitter.cpp +++ b/clang/utils/TableGen/ClangAttrEmitter.cpp @@ -2381,6 +2381,11 @@ static void emitClangAttrAcceptsExprPack(RecordKeeper &Records, OS << "#endif // CLANG_ATTR_ACCEPTS_EXPR_PACK\n\n"; } +static bool isRegularKeywordAttribute(const FlattenedSpelling &S) { + return (S.variety() == "Keyword" && + !S.getSpellingRecord().getValueAsBit("HasOwnParseRules")); +} + static void emitFormInitializer(raw_ostream &OS, const FlattenedSpelling &Spelling, StringRef SpellingIndex) { @@ -2388,7 +2393,9 @@ static void emitFormInitializer(raw_ostream &OS, (Spelling.variety() == "Keyword" && Spelling.name() == "alignas"); OS << "{AttributeCommonInfo::AS_" << Spelling.variety() << ", " << SpellingIndex << ", " << (IsAlignas ? "true" : "false") - << " /*IsAlignas*/}"; + << " /*IsAlignas*/, " + << (isRegularKeywordAttribute(Spelling) ? "true" : "false") + << " /*IsRegularKeywordAttribute*/}"; } static void emitAttributes(RecordKeeper &Records, raw_ostream &OS, @@ -3407,6 +3414,26 @@ static void GenerateHasAttrSpellingStringSwitch( OS << " .Default(0);\n"; } +// Emits the list of tokens for regular keyword attributes. +void EmitClangAttrTokenKinds(RecordKeeper &Records, raw_ostream &OS) { + emitSourceFileHeader("A list of tokens generated from the attribute" + " definitions", + OS); + // Assume for now that the same token is not used in multiple regular + // keyword attributes. + for (auto *R : Records.getAllDerivedDefinitions("Attr")) + for (const auto &S : GetFlattenedSpellings(*R)) + if (isRegularKeywordAttribute(S)) { + if (!R->getValueAsListOfDefs("Args").empty()) + PrintError(R->getLoc(), + "RegularKeyword attributes with arguments are not " + "yet supported"); + OS << "KEYWORD_ATTRIBUTE(" + << S.getSpellingRecord().getValueAsString("Name") << ")\n"; + } + OS << "#undef KEYWORD_ATTRIBUTE\n"; +} + // Emits the list of spellings for attributes. void EmitClangAttrHasAttrImpl(RecordKeeper &Records, raw_ostream &OS) { emitSourceFileHeader("Code to implement the __has_attribute logic", OS); @@ -3855,7 +3882,8 @@ static void GenerateAppertainsTo(const Record &Attr, raw_ostream &OS) { OS << "bool diagAppertainsToDecl(Sema &S, const ParsedAttr &AL, "; OS << "const Decl *D) const override {\n"; OS << " S.Diag(AL.getLoc(), diag::err_attribute_invalid_on_decl)\n"; - OS << " << AL << D->getLocation();\n"; + OS << " << AL << AL.isRegularKeywordAttribute() << " + "D->getLocation();\n"; OS << " return false;\n"; OS << "}\n\n"; } @@ -3884,7 +3912,7 @@ static void GenerateAppertainsTo(const Record &Attr, raw_ostream &OS) { OS << (Warn ? "warn_attribute_wrong_decl_type_str" : "err_attribute_wrong_decl_type_str"); OS << ")\n"; - OS << " << Attr << "; + OS << " << Attr << Attr.isRegularKeywordAttribute() << "; OS << CalculateDiagnostic(*SubjectObj) << ";\n"; OS << " return false;\n"; OS << " }\n"; @@ -3899,7 +3927,8 @@ static void GenerateAppertainsTo(const Record &Attr, raw_ostream &OS) { OS << "bool diagAppertainsToStmt(Sema &S, const ParsedAttr &AL, "; OS << "const Stmt *St) const override {\n"; OS << " S.Diag(AL.getLoc(), diag::err_decl_attribute_invalid_on_stmt)\n"; - OS << " << AL << St->getBeginLoc();\n"; + OS << " << AL << AL.isRegularKeywordAttribute() << " + "St->getBeginLoc();\n"; OS << " return false;\n"; OS << "}\n\n"; } @@ -3918,7 +3947,7 @@ static void GenerateAppertainsTo(const Record &Attr, raw_ostream &OS) { OS << (Warn ? "warn_attribute_wrong_decl_type_str" : "err_attribute_wrong_decl_type_str"); OS << ")\n"; - OS << " << Attr << "; + OS << " << Attr << Attr.isRegularKeywordAttribute() << "; OS << CalculateDiagnostic(*SubjectObj) << ";\n"; OS << " return false;\n"; OS << " }\n"; @@ -3989,7 +4018,8 @@ static void GenerateMutualExclusionsChecks(const Record &Attr, for (const std::string &A : DeclAttrs) { OS << " if (const auto *A = D->getAttr<" << A << ">()) {\n"; OS << " S.Diag(AL.getLoc(), diag::err_attributes_are_not_compatible)" - << " << AL << A;\n"; + << " << AL << A << (AL.isRegularKeywordAttribute() ||" + << " A->isRegularKeywordAttribute());\n"; OS << " S.Diag(A->getLocation(), diag::note_conflicting_attribute);"; OS << " \nreturn false;\n"; OS << " }\n"; @@ -4010,7 +4040,8 @@ static void GenerateMutualExclusionsChecks(const Record &Attr, << ">()) {\n"; MergeDeclOS << " S.Diag(First->getLocation(), " << "diag::err_attributes_are_not_compatible) << First << " - << "Second;\n"; + << "Second << (First->isRegularKeywordAttribute() || " + << "Second->isRegularKeywordAttribute());\n"; MergeDeclOS << " S.Diag(Second->getLocation(), " << "diag::note_conflicting_attribute);\n"; MergeDeclOS << " return false;\n"; @@ -4050,7 +4081,8 @@ static void GenerateMutualExclusionsChecks(const Record &Attr, MergeStmtOS << " if (Iter != C.end()) {\n"; MergeStmtOS << " S.Diag((*Iter)->getLocation(), " << "diag::err_attributes_are_not_compatible) << *Iter << " - << "Second;\n"; + << "Second << ((*Iter)->isRegularKeywordAttribute() || " + << "Second->isRegularKeywordAttribute());\n"; MergeStmtOS << " S.Diag(Second->getLocation(), " << "diag::note_conflicting_attribute);\n"; MergeStmtOS << " return false;\n"; diff --git a/clang/utils/TableGen/ClangOpcodesEmitter.cpp b/clang/utils/TableGen/ClangOpcodesEmitter.cpp index aa012233c46ee..db88c990d5f9b 100644 --- a/clang/utils/TableGen/ClangOpcodesEmitter.cpp +++ b/clang/utils/TableGen/ClangOpcodesEmitter.cpp @@ -21,7 +21,7 @@ using namespace llvm; namespace { class ClangOpcodesEmitter { RecordKeeper &Records; - Record Root; + const Record Root; unsigned NumTypes; public: @@ -34,33 +34,32 @@ class ClangOpcodesEmitter { private: /// Emits the opcode name for the opcode enum. /// The name is obtained by concatenating the name with the list of types. - void EmitEnum(raw_ostream &OS, StringRef N, Record *R); + void EmitEnum(raw_ostream &OS, StringRef N, const Record *R); /// Emits the switch case and the invocation in the interpreter. - void EmitInterp(raw_ostream &OS, StringRef N, Record *R); + void EmitInterp(raw_ostream &OS, StringRef N, const Record *R); /// Emits the disassembler. - void EmitDisasm(raw_ostream &OS, StringRef N, Record *R); + void EmitDisasm(raw_ostream &OS, StringRef N, const Record *R); /// Emits the byte code emitter method. - void EmitEmitter(raw_ostream &OS, StringRef N, Record *R); + void EmitEmitter(raw_ostream &OS, StringRef N, const Record *R); /// Emits the prototype. - void EmitProto(raw_ostream &OS, StringRef N, Record *R); + void EmitProto(raw_ostream &OS, StringRef N, const Record *R); /// Emits the prototype to dispatch from a type. - void EmitGroup(raw_ostream &OS, StringRef N, Record *R); + void EmitGroup(raw_ostream &OS, StringRef N, const Record *R); /// Emits the evaluator method. - void EmitEval(raw_ostream &OS, StringRef N, Record *R); + void EmitEval(raw_ostream &OS, StringRef N, const Record *R); - void PrintTypes(raw_ostream &OS, ArrayRef Types); + void PrintTypes(raw_ostream &OS, ArrayRef Types); }; -void Enumerate(const Record *R, - StringRef N, - std::function, Twine)> &&F) { - llvm::SmallVector TypePath; +void Enumerate(const Record *R, StringRef N, + std::function, Twine)> &&F) { + llvm::SmallVector TypePath; auto *Types = R->getValueAsListInit("Types"); std::function Rec; @@ -102,67 +101,72 @@ void ClangOpcodesEmitter::run(raw_ostream &OS) { } } -void ClangOpcodesEmitter::EmitEnum(raw_ostream &OS, StringRef N, Record *R) { +void ClangOpcodesEmitter::EmitEnum(raw_ostream &OS, StringRef N, + const Record *R) { OS << "#ifdef GET_OPCODE_NAMES\n"; - Enumerate(R, N, [&OS](ArrayRef, const Twine &ID) { + Enumerate(R, N, [&OS](ArrayRef, const Twine &ID) { OS << "OP_" << ID << ",\n"; }); OS << "#endif\n"; } -void ClangOpcodesEmitter::EmitInterp(raw_ostream &OS, StringRef N, Record *R) { +void ClangOpcodesEmitter::EmitInterp(raw_ostream &OS, StringRef N, + const Record *R) { OS << "#ifdef GET_INTERP\n"; - Enumerate(R, N, [this, R, &OS, &N](ArrayRef TS, const Twine &ID) { - bool CanReturn = R->getValueAsBit("CanReturn"); - bool ChangesPC = R->getValueAsBit("ChangesPC"); - auto Args = R->getValueAsListOfDefs("Args"); - - OS << "case OP_" << ID << ": {\n"; - - if (CanReturn) - OS << " bool DoReturn = (S.Current == StartFrame);\n"; - - // Emit calls to read arguments. - for (size_t I = 0, N = Args.size(); I < N; ++I) { - OS << " auto V" << I; - OS << " = "; - OS << "ReadArg<" << Args[I]->getValueAsString("Name") << ">(S, PC);\n"; - } - - // Emit a call to the template method and pass arguments. - OS << " if (!" << N; - PrintTypes(OS, TS); - OS << "(S"; - if (ChangesPC) - OS << ", PC"; - else - OS << ", OpPC"; - if (CanReturn) - OS << ", Result"; - for (size_t I = 0, N = Args.size(); I < N; ++I) - OS << ", V" << I; - OS << "))\n"; - OS << " return false;\n"; - - // Bail out if interpreter returned. - if (CanReturn) { - OS << " if (!S.Current || S.Current->isRoot())\n"; - OS << " return true;\n"; - - OS << " if (DoReturn)\n"; - OS << " return true;\n"; - } - - OS << " continue;\n"; - OS << "}\n"; - }); + Enumerate(R, N, + [this, R, &OS, &N](ArrayRef TS, const Twine &ID) { + bool CanReturn = R->getValueAsBit("CanReturn"); + bool ChangesPC = R->getValueAsBit("ChangesPC"); + auto Args = R->getValueAsListOfDefs("Args"); + + OS << "case OP_" << ID << ": {\n"; + + if (CanReturn) + OS << " bool DoReturn = (S.Current == StartFrame);\n"; + + // Emit calls to read arguments. + for (size_t I = 0, N = Args.size(); I < N; ++I) { + OS << " auto V" << I; + OS << " = "; + OS << "ReadArg<" << Args[I]->getValueAsString("Name") + << ">(S, PC);\n"; + } + + // Emit a call to the template method and pass arguments. + OS << " if (!" << N; + PrintTypes(OS, TS); + OS << "(S"; + if (ChangesPC) + OS << ", PC"; + else + OS << ", OpPC"; + if (CanReturn) + OS << ", Result"; + for (size_t I = 0, N = Args.size(); I < N; ++I) + OS << ", V" << I; + OS << "))\n"; + OS << " return false;\n"; + + // Bail out if interpreter returned. + if (CanReturn) { + OS << " if (!S.Current || S.Current->isRoot())\n"; + OS << " return true;\n"; + + OS << " if (DoReturn)\n"; + OS << " return true;\n"; + } + + OS << " continue;\n"; + OS << "}\n"; + }); OS << "#endif\n"; } -void ClangOpcodesEmitter::EmitDisasm(raw_ostream &OS, StringRef N, Record *R) { +void ClangOpcodesEmitter::EmitDisasm(raw_ostream &OS, StringRef N, + const Record *R) { OS << "#ifdef GET_DISASM\n"; - Enumerate(R, N, [R, &OS](ArrayRef, const Twine &ID) { + Enumerate(R, N, [R, &OS](ArrayRef, const Twine &ID) { OS << "case OP_" << ID << ":\n"; OS << " PrintName(\"" << ID << "\");\n"; OS << " OS << \"\\t\""; @@ -178,12 +182,13 @@ void ClangOpcodesEmitter::EmitDisasm(raw_ostream &OS, StringRef N, Record *R) { OS << "#endif\n"; } -void ClangOpcodesEmitter::EmitEmitter(raw_ostream &OS, StringRef N, Record *R) { +void ClangOpcodesEmitter::EmitEmitter(raw_ostream &OS, StringRef N, + const Record *R) { if (R->getValueAsBit("HasCustomLink")) return; OS << "#ifdef GET_LINK_IMPL\n"; - Enumerate(R, N, [R, &OS](ArrayRef, const Twine &ID) { + Enumerate(R, N, [R, &OS](ArrayRef, const Twine &ID) { auto Args = R->getValueAsListOfDefs("Args"); // Emit the list of arguments. @@ -208,10 +213,11 @@ void ClangOpcodesEmitter::EmitEmitter(raw_ostream &OS, StringRef N, Record *R) { OS << "#endif\n"; } -void ClangOpcodesEmitter::EmitProto(raw_ostream &OS, StringRef N, Record *R) { +void ClangOpcodesEmitter::EmitProto(raw_ostream &OS, StringRef N, + const Record *R) { OS << "#if defined(GET_EVAL_PROTO) || defined(GET_LINK_PROTO)\n"; auto Args = R->getValueAsListOfDefs("Args"); - Enumerate(R, N, [&OS, &Args](ArrayRef TS, const Twine &ID) { + Enumerate(R, N, [&OS, &Args](ArrayRef TS, const Twine &ID) { OS << "bool emit" << ID << "("; for (auto *Arg : Args) OS << Arg->getValueAsString("Name") << ", "; @@ -239,16 +245,19 @@ void ClangOpcodesEmitter::EmitProto(raw_ostream &OS, StringRef N, Record *R) { OS << "#endif\n"; } -void ClangOpcodesEmitter::EmitGroup(raw_ostream &OS, StringRef N, Record *R) { +void ClangOpcodesEmitter::EmitGroup(raw_ostream &OS, StringRef N, + const Record *R) { if (!R->getValueAsBit("HasGroup")) return; auto *Types = R->getValueAsListInit("Types"); auto Args = R->getValueAsListOfDefs("Args"); + Twine EmitFuncName = "emit" + N; + // Emit the prototype of the group emitter in the header. OS << "#if defined(GET_EVAL_PROTO) || defined(GET_LINK_PROTO)\n"; - OS << "bool emit" << N << "("; + OS << "bool " << EmitFuncName << "("; for (size_t I = 0, N = Types->size(); I < N; ++I) OS << "PrimType, "; for (auto *Arg : Args) @@ -264,7 +273,7 @@ void ClangOpcodesEmitter::EmitGroup(raw_ostream &OS, StringRef N, Record *R) { OS << "#else\n"; OS << "ByteCodeEmitter\n"; OS << "#endif\n"; - OS << "::emit" << N << "("; + OS << "::" << EmitFuncName << "("; for (size_t I = 0, N = Types->size(); I < N; ++I) OS << "PrimType T" << I << ", "; for (size_t I = 0, N = Args.size(); I < N; ++I) @@ -272,8 +281,9 @@ void ClangOpcodesEmitter::EmitGroup(raw_ostream &OS, StringRef N, Record *R) { OS << "const SourceInfo &I) {\n"; std::function Rec; - llvm::SmallVector TS; - Rec = [this, &Rec, &OS, Types, &Args, R, &TS, N](size_t I, const Twine &ID) { + llvm::SmallVector TS; + Rec = [this, &Rec, &OS, Types, &Args, R, &TS, N, + EmitFuncName](size_t I, const Twine &ID) { if (I >= Types->size()) { // Print a call to the emitter method. // Custom evaluator methods dispatch to template methods. @@ -309,7 +319,8 @@ void ClangOpcodesEmitter::EmitGroup(raw_ostream &OS, StringRef N, Record *R) { } // Emit a default case if not all types are present. if (Cases.size() < NumTypes) - OS << " default: llvm_unreachable(\"invalid type\");\n"; + OS << " default: llvm_unreachable(\"invalid type: " << EmitFuncName + << "\");\n"; OS << " }\n"; OS << " llvm_unreachable(\"invalid enum value\");\n"; } else { @@ -322,34 +333,37 @@ void ClangOpcodesEmitter::EmitGroup(raw_ostream &OS, StringRef N, Record *R) { OS << "#endif\n"; } -void ClangOpcodesEmitter::EmitEval(raw_ostream &OS, StringRef N, Record *R) { +void ClangOpcodesEmitter::EmitEval(raw_ostream &OS, StringRef N, + const Record *R) { if (R->getValueAsBit("HasCustomEval")) return; OS << "#ifdef GET_EVAL_IMPL\n"; - Enumerate(R, N, [this, R, &N, &OS](ArrayRef TS, const Twine &ID) { - auto Args = R->getValueAsListOfDefs("Args"); - - OS << "bool EvalEmitter::emit" << ID << "("; - for (size_t I = 0, N = Args.size(); I < N; ++I) - OS << Args[I]->getValueAsString("Name") << " A" << I << ", "; - OS << "const SourceInfo &L) {\n"; - OS << " if (!isActive()) return true;\n"; - OS << " CurrentSource = L;\n"; - - OS << " return " << N; - PrintTypes(OS, TS); - OS << "(S, OpPC"; - for (size_t I = 0, N = Args.size(); I < N; ++I) - OS << ", A" << I; - OS << ");\n"; - OS << "}\n"; - }); + Enumerate(R, N, + [this, R, &N, &OS](ArrayRef TS, const Twine &ID) { + auto Args = R->getValueAsListOfDefs("Args"); + + OS << "bool EvalEmitter::emit" << ID << "("; + for (size_t I = 0, N = Args.size(); I < N; ++I) + OS << Args[I]->getValueAsString("Name") << " A" << I << ", "; + OS << "const SourceInfo &L) {\n"; + OS << " if (!isActive()) return true;\n"; + OS << " CurrentSource = L;\n"; + + OS << " return " << N; + PrintTypes(OS, TS); + OS << "(S, OpPC"; + for (size_t I = 0, N = Args.size(); I < N; ++I) + OS << ", A" << I; + OS << ");\n"; + OS << "}\n"; + }); OS << "#endif\n"; } -void ClangOpcodesEmitter::PrintTypes(raw_ostream &OS, ArrayRef Types) { +void ClangOpcodesEmitter::PrintTypes(raw_ostream &OS, + ArrayRef Types) { if (Types.empty()) return; OS << "<"; diff --git a/clang/utils/TableGen/RISCVVEmitter.cpp b/clang/utils/TableGen/RISCVVEmitter.cpp index 35b2203cecf34..a20d7f5eba385 100644 --- a/clang/utils/TableGen/RISCVVEmitter.cpp +++ b/clang/utils/TableGen/RISCVVEmitter.cpp @@ -533,9 +533,11 @@ void RVVEmitter::createRVVIntrinsics( BasicPrototype, /*IsMasked=*/false, /*HasMaskedOffOperand=*/false, HasVL, NF, UnMaskedPolicyScheme, DefaultPolicy, IsTuple); - auto MaskedPrototype = RVVIntrinsic::computeBuiltinTypes( - BasicPrototype, /*IsMasked=*/true, HasMaskedOffOperand, HasVL, NF, - MaskedPolicyScheme, DefaultPolicy, IsTuple); + llvm::SmallVector MaskedPrototype; + if (HasMasked) + MaskedPrototype = RVVIntrinsic::computeBuiltinTypes( + BasicPrototype, /*IsMasked=*/true, HasMaskedOffOperand, HasVL, NF, + MaskedPolicyScheme, DefaultPolicy, IsTuple); // Create Intrinsics for each type and LMUL. for (char I : TypeRange) { diff --git a/clang/utils/TableGen/SveEmitter.cpp b/clang/utils/TableGen/SveEmitter.cpp index 55a298eebfcf9..c423e35b5e3b6 100644 --- a/clang/utils/TableGen/SveEmitter.cpp +++ b/clang/utils/TableGen/SveEmitter.cpp @@ -66,7 +66,8 @@ class ImmCheck { class SVEType { TypeSpec TS; bool Float, Signed, Immediate, Void, Constant, Pointer, BFloat; - bool DefaultType, IsScalable, Predicate, PredicatePattern, PrefetchOp; + bool DefaultType, IsScalable, Predicate, PredicatePattern, PrefetchOp, + Svcount; unsigned Bitwidth, ElementBitwidth, NumVectors; public: @@ -76,7 +77,8 @@ class SVEType { : TS(TS), Float(false), Signed(true), Immediate(false), Void(false), Constant(false), Pointer(false), BFloat(false), DefaultType(false), IsScalable(true), Predicate(false), PredicatePattern(false), - PrefetchOp(false), Bitwidth(128), ElementBitwidth(~0U), NumVectors(1) { + PrefetchOp(false), Svcount(false), Bitwidth(128), ElementBitwidth(~0U), + NumVectors(1) { if (!TS.empty()) applyTypespec(); applyModifier(CharMod); @@ -95,13 +97,16 @@ class SVEType { bool isFloat() const { return Float && !BFloat; } bool isBFloat() const { return BFloat && !Float; } bool isFloatingPoint() const { return Float || BFloat; } - bool isInteger() const { return !isFloatingPoint() && !Predicate; } + bool isInteger() const { + return !isFloatingPoint() && !Predicate && !Svcount; + } bool isScalarPredicate() const { return !isFloatingPoint() && Predicate && NumVectors == 0; } bool isPredicateVector() const { return Predicate; } bool isPredicatePattern() const { return PredicatePattern; } bool isPrefetchOp() const { return PrefetchOp; } + bool isSvcount() const { return Svcount; } bool isConstant() const { return Constant; } unsigned getElementSizeInBits() const { return ElementBitwidth; } unsigned getNumVectors() const { return NumVectors; } @@ -203,6 +208,9 @@ class Intrinsic { /// ClassS, so will add type suffixes such as _u32/_s32. std::string getMangledName() const { return mangleName(ClassS); } + /// As above, but mangles the LLVM name instead. + std::string getMangledLLVMName() const { return mangleLLVMName(); } + /// Returns true if the intrinsic is overloaded, in that it should also generate /// a short form without the type-specifiers, e.g. 'svld1(..)' instead of /// 'svld1_u32(..)'. @@ -233,6 +241,7 @@ class Intrinsic { private: std::string getMergeSuffix() const { return MergeSuffix; } std::string mangleName(ClassKind LocalCK) const; + std::string mangleLLVMName() const; std::string replaceTemplatedArgs(std::string Name, TypeSpec TS, std::string Proto) const; }; @@ -379,6 +388,9 @@ std::string SVEType::builtin_str() const { if (isScalarPredicate()) return "b"; + if (isSvcount()) + return "Qa"; + if (isVoidPointer()) S += "v"; else if (!isFloatingPoint()) @@ -442,13 +454,15 @@ std::string SVEType::str() const { if (Void) S += "void"; else { - if (isScalableVector()) + if (isScalableVector() || isSvcount()) S += "sv"; if (!Signed && !isFloatingPoint()) S += "u"; if (Float) S += "float"; + else if (isSvcount()) + S += "count"; else if (isScalarPredicate() || isPredicateVector()) S += "bool"; else if (isBFloat()) @@ -456,7 +470,7 @@ std::string SVEType::str() const { else S += "int"; - if (!isScalarPredicate() && !isPredicateVector()) + if (!isScalarPredicate() && !isPredicateVector() && !isSvcount()) S += utostr(ElementBitwidth); if (!isScalableVector() && isVector()) S += "x" + utostr(getNumElements()); @@ -476,6 +490,9 @@ std::string SVEType::str() const { void SVEType::applyTypespec() { for (char I : TS) { switch (I) { + case 'Q': + Svcount = true; + break; case 'P': Predicate = true; break; @@ -570,6 +587,7 @@ void SVEType::applyModifier(char Mod) { Float = false; BFloat = false; Predicate = true; + Svcount = false; Bitwidth = 16; ElementBitwidth = 1; break; @@ -609,18 +627,21 @@ void SVEType::applyModifier(char Mod) { break; case 'u': Predicate = false; + Svcount = false; Signed = false; Float = false; BFloat = false; break; case 'x': Predicate = false; + Svcount = false; Signed = true; Float = false; BFloat = false; break; case 'i': Predicate = false; + Svcount = false; Float = false; BFloat = false; ElementBitwidth = Bitwidth = 64; @@ -630,6 +651,7 @@ void SVEType::applyModifier(char Mod) { break; case 'I': Predicate = false; + Svcount = false; Float = false; BFloat = false; ElementBitwidth = Bitwidth = 32; @@ -640,6 +662,7 @@ void SVEType::applyModifier(char Mod) { break; case 'J': Predicate = false; + Svcount = false; Float = false; BFloat = false; ElementBitwidth = Bitwidth = 32; @@ -650,6 +673,7 @@ void SVEType::applyModifier(char Mod) { break; case 'k': Predicate = false; + Svcount = false; Signed = true; Float = false; BFloat = false; @@ -658,6 +682,7 @@ void SVEType::applyModifier(char Mod) { break; case 'l': Predicate = false; + Svcount = false; Signed = true; Float = false; BFloat = false; @@ -666,6 +691,7 @@ void SVEType::applyModifier(char Mod) { break; case 'm': Predicate = false; + Svcount = false; Signed = false; Float = false; BFloat = false; @@ -674,6 +700,7 @@ void SVEType::applyModifier(char Mod) { break; case 'n': Predicate = false; + Svcount = false; Signed = false; Float = false; BFloat = false; @@ -712,17 +739,20 @@ void SVEType::applyModifier(char Mod) { break; case 'O': Predicate = false; + Svcount = false; Float = true; ElementBitwidth = 16; break; case 'M': Predicate = false; + Svcount = false; Float = true; BFloat = false; ElementBitwidth = 32; break; case 'N': Predicate = false; + Svcount = false; Float = true; ElementBitwidth = 64; break; @@ -821,6 +851,14 @@ void SVEType::applyModifier(char Mod) { NumVectors = 0; Signed = false; break; + case '}': + Predicate = false; + Signed = true; + Svcount = true; + NumVectors = 0; + Float = false; + BFloat = false; + break; default: llvm_unreachable("Unhandled character!"); } @@ -901,6 +939,8 @@ std::string Intrinsic::replaceTemplatedArgs(std::string Name, TypeSpec TS, std::string TypeCode; if (T.isInteger()) TypeCode = T.isSigned() ? 's' : 'u'; + else if (T.isSvcount()) + TypeCode = 'c'; else if (T.isPredicateVector()) TypeCode = 'b'; else if (T.isBFloat()) @@ -913,6 +953,13 @@ std::string Intrinsic::replaceTemplatedArgs(std::string Name, TypeSpec TS, return Ret; } +std::string Intrinsic::mangleLLVMName() const { + std::string S = getLLVMName(); + + // Replace all {d} like expressions with e.g. 'u32' + return replaceTemplatedArgs(S, getBaseTypeSpec(), getProto()); +} + std::string Intrinsic::mangleName(ClassKind LocalCK) const { std::string S = getName(); @@ -995,7 +1042,7 @@ uint64_t SVEEmitter::encodeTypeFlags(const SVEType &T) { return encodeEltType("EltTyBFloat16"); } - if (T.isPredicateVector()) { + if (T.isPredicateVector() || T.isSvcount()) { switch (T.getElementSizeInBits()) { case 8: return encodeEltType("EltTyBool8"); @@ -1185,6 +1232,8 @@ void SVEEmitter::createHeader(raw_ostream &OS) { OS << "typedef __clang_svbfloat16x3_t svbfloat16x3_t;\n"; OS << "typedef __clang_svbfloat16x4_t svbfloat16x4_t;\n"; + OS << "typedef __SVCount_t svcount_t;\n\n"; + OS << "enum svpattern\n"; OS << "{\n"; OS << " SV_POW2 = 0,\n"; @@ -1340,7 +1389,7 @@ void SVEEmitter::createCodeGenMap(raw_ostream &OS) { uint64_t Flags = Def->getFlags(); auto FlagString = std::to_string(Flags); - std::string LLVMName = Def->getLLVMName(); + std::string LLVMName = Def->getMangledLLVMName(); std::string Builtin = Def->getMangledName(); if (!LLVMName.empty()) OS << "SVEMAP1(" << Builtin << ", " << LLVMName << ", " << FlagString diff --git a/clang/utils/TableGen/TableGen.cpp b/clang/utils/TableGen/TableGen.cpp index 1ce8d6b046118..38215abd9d9b7 100644 --- a/clang/utils/TableGen/TableGen.cpp +++ b/clang/utils/TableGen/TableGen.cpp @@ -35,6 +35,7 @@ enum ActionType { GenClangAttrSubjectMatchRuleList, GenClangAttrPCHRead, GenClangAttrPCHWrite, + GenClangAttrTokenKinds, GenClangAttrHasAttributeImpl, GenClangAttrSpellingListIndex, GenClangAttrASTVisitor, @@ -135,6 +136,8 @@ cl::opt Action( "Generate clang PCH attribute reader"), clEnumValN(GenClangAttrPCHWrite, "gen-clang-attr-pch-write", "Generate clang PCH attribute writer"), + clEnumValN(GenClangAttrTokenKinds, "gen-clang-attr-token-kinds", + "Generate a list of attribute-related clang tokens"), clEnumValN(GenClangAttrHasAttributeImpl, "gen-clang-attr-has-attribute-impl", "Generate a clang attribute spelling list"), @@ -324,6 +327,9 @@ bool ClangTableGenMain(raw_ostream &OS, RecordKeeper &Records) { case GenClangAttrPCHWrite: EmitClangAttrPCHWrite(Records, OS); break; + case GenClangAttrTokenKinds: + EmitClangAttrTokenKinds(Records, OS); + break; case GenClangAttrHasAttributeImpl: EmitClangAttrHasAttrImpl(Records, OS); break; diff --git a/clang/utils/TableGen/TableGenBackends.h b/clang/utils/TableGen/TableGenBackends.h index 9474c47a340ac..8265a531a98fb 100644 --- a/clang/utils/TableGen/TableGenBackends.h +++ b/clang/utils/TableGen/TableGenBackends.h @@ -43,6 +43,8 @@ void EmitClangAttrSubjectMatchRuleList(llvm::RecordKeeper &Records, llvm::raw_ostream &OS); void EmitClangAttrPCHRead(llvm::RecordKeeper &Records, llvm::raw_ostream &OS); void EmitClangAttrPCHWrite(llvm::RecordKeeper &Records, llvm::raw_ostream &OS); +void EmitClangAttrTokenKinds(llvm::RecordKeeper &Records, + llvm::raw_ostream &OS); void EmitClangAttrHasAttrImpl(llvm::RecordKeeper &Records, llvm::raw_ostream &OS); void EmitClangAttrSpellingListIndex(llvm::RecordKeeper &Records, diff --git a/clang/www/cxx_dr_status.html b/clang/www/cxx_dr_status.html index 59a0b0c05295c..77790bceea851 100755 --- a/clang/www/cxx_dr_status.html +++ b/clang/www/cxx_dr_status.html @@ -3767,7 +3767,7 @@

C++ defect report implementation status

621 C++11 Template argument deduction from function return types - Unknown + Yes 622 @@ -5117,7 +5117,7 @@

C++ defect report implementation status

873 C++11 Deducing rvalue references in declarative contexts - Unknown + Yes 874 @@ -8189,7 +8189,7 @@

C++ defect report implementation status

1397 CD4 Class completeness in non-static data member initializers - Unknown + Clang 3.2 1398 diff --git a/clang/www/cxx_status.html b/clang/www/cxx_status.html index 91706be09f158..26b4e55cf180e 100755 --- a/clang/www/cxx_status.html +++ b/clang/www/cxx_status.html @@ -686,7 +686,7 @@

C++20 implementation status

Parenthesized initialization of aggregates P0960R3 - No + Clang 16 P1975R0 diff --git a/cmake/Modules/GetClangResourceDir.cmake b/cmake/Modules/GetClangResourceDir.cmake new file mode 100644 index 0000000000000..fb56e611a0e88 --- /dev/null +++ b/cmake/Modules/GetClangResourceDir.cmake @@ -0,0 +1,27 @@ +# get clang resource directory +# +# usage: +# get_clang_resource_dir(out_var [PREFIX prefix] [SUBDIR subdirectory]) +# +# user can use `PREFIX` to prepend some path to it or use `SUBDIR` to +# get subdirectory under clang resource dir + +function(get_clang_resource_dir out_var) + cmake_parse_arguments(ARG "" "PREFIX;SUBDIR" "" ${ARGN}) + + if(DEFINED CLANG_RESOURCE_DIR AND NOT CLANG_RESOURCE_DIR STREQUAL "") + set(ret_dir bin/${CLANG_RESOURCE_DIR}) + else() + string(REGEX MATCH "^[0-9]+" CLANG_VERSION_MAJOR ${PACKAGE_VERSION}) + set(ret_dir lib${LLVM_LIBDIR_SUFFIX}/clang/${CLANG_VERSION_MAJOR}) + endif() + + if(ARG_PREFIX) + set(ret_dir ${ARG_PREFIX}/${ret_dir}) + endif() + if(ARG_SUBDIR) + set(ret_dir ${ret_dir}/${ARG_SUBDIR}) + endif() + + set(${out_var} ${ret_dir} PARENT_SCOPE) +endfunction() diff --git a/compiler-rt/cmake/Modules/AllSupportedArchDefs.cmake b/compiler-rt/cmake/Modules/AllSupportedArchDefs.cmake index 3892dd7a6f453..15c39233685cc 100644 --- a/compiler-rt/cmake/Modules/AllSupportedArchDefs.cmake +++ b/compiler-rt/cmake/Modules/AllSupportedArchDefs.cmake @@ -29,6 +29,7 @@ set(ALL_SANITIZER_COMMON_SUPPORTED_ARCH ${X86} ${X86_64} ${PPC64} ${RISCV64} set(ALL_ASAN_SUPPORTED_ARCH ${X86} ${X86_64} ${ARM32} ${ARM64} ${RISCV64} ${MIPS32} ${MIPS64} ${PPC64} ${S390X} ${SPARC} ${SPARCV9} ${HEXAGON} ${LOONGARCH64}) +set(ALL_ASAN_ABI_SUPPORTED_ARCH ${X86_64} ${ARM64}) set(ALL_DFSAN_SUPPORTED_ARCH ${X86_64} ${MIPS64} ${ARM64}) if(ANDROID) diff --git a/compiler-rt/cmake/base-config-ix.cmake b/compiler-rt/cmake/base-config-ix.cmake index c6e95055b0028..ede8428c39382 100644 --- a/compiler-rt/cmake/base-config-ix.cmake +++ b/compiler-rt/cmake/base-config-ix.cmake @@ -7,6 +7,7 @@ include(BuiltinTests) include(CheckIncludeFile) include(CheckCXXSourceCompiles) include(GNUInstallDirs) +include(GetClangResourceDir) include(ExtendPath) include(CompilerRTDarwinUtils) @@ -38,15 +39,10 @@ if (LLVM_LIBRARY_OUTPUT_INTDIR AND LLVM_RUNTIME_OUTPUT_INTDIR AND PACKAGE_VERSIO endif() if (LLVM_TREE_AVAILABLE) - # Compute the Clang version from the LLVM version. - # FIXME: We should be able to reuse CLANG_VERSION_MAJOR variable calculated - # in Clang cmake files, instead of copying the rules here. - string(REGEX MATCH "^[0-9]+" CLANG_VERSION_MAJOR - ${PACKAGE_VERSION}) # Setup the paths where compiler-rt runtimes and headers should be stored. - set(COMPILER_RT_OUTPUT_DIR ${LLVM_LIBRARY_OUTPUT_INTDIR}/clang/${CLANG_VERSION_MAJOR}) + get_clang_resource_dir(COMPILER_RT_OUTPUT_DIR PREFIX ${LLVM_LIBRARY_OUTPUT_INTDIR}/..) set(COMPILER_RT_EXEC_OUTPUT_DIR ${LLVM_RUNTIME_OUTPUT_INTDIR}) - set(COMPILER_RT_INSTALL_PATH lib${LLVM_LIBDIR_SUFFIX}/clang/${CLANG_VERSION_MAJOR}) + get_clang_resource_dir(COMPILER_RT_INSTALL_PATH) option(COMPILER_RT_INCLUDE_TESTS "Generate and build compiler-rt unit tests." ${LLVM_INCLUDE_TESTS}) option(COMPILER_RT_ENABLE_WERROR "Fail and stop if warning is triggered" diff --git a/compiler-rt/cmake/config-ix.cmake b/compiler-rt/cmake/config-ix.cmake index df1598dade737..1b8d6640eb443 100644 --- a/compiler-rt/cmake/config-ix.cmake +++ b/compiler-rt/cmake/config-ix.cmake @@ -590,6 +590,7 @@ if(APPLE) ) set(LSAN_COMMON_SUPPORTED_ARCH ${SANITIZER_COMMON_SUPPORTED_ARCH}) set(UBSAN_COMMON_SUPPORTED_ARCH ${SANITIZER_COMMON_SUPPORTED_ARCH}) + set(ASAN_ABI_SUPPORTED_ARCH ${ALL_ASAN_ABI_SUPPORTED_ARCH}) list_intersect(ASAN_SUPPORTED_ARCH ALL_ASAN_SUPPORTED_ARCH SANITIZER_COMMON_SUPPORTED_ARCH) diff --git a/compiler-rt/include/sanitizer/tsan_interface.h b/compiler-rt/include/sanitizer/tsan_interface.h index 58f2513734ecb..f19c79d79ba62 100644 --- a/compiler-rt/include/sanitizer/tsan_interface.h +++ b/compiler-rt/include/sanitizer/tsan_interface.h @@ -178,6 +178,123 @@ const char* __tsan_default_options(void); // User-provided default TSAN suppressions. const char* __tsan_default_suppressions(void); +/// Returns a report's description. +/// +/// Returns a report's description (issue type), number of duplicate issues +/// found, counts of array data (stack traces, memory operations, locations, +/// mutexes, threads, unique thread IDs) and a stack trace of a sleep() +/// call (if one was involved in the issue). +/// +/// \param report Opaque pointer to the current report. +/// \param[out] description Report type description. +/// \param[out] count Count of duplicate issues. +/// \param[out] stack_count Count of stack traces. +/// \param[out] mop_count Count of memory operations. +/// \param[out] loc_count Count of locations. +/// \param[out] mutex_count Count of mutexes. +/// \param[out] thread_count Count of threads. +/// \param[out] unique_tid_count Count of unique thread IDs. +/// \param sleep_trace A buffer to store the stack trace of a sleep() +/// call. +/// \param trace_size Size in bytes of the trace buffer. +/// \returns Returns 1 if successful, 0 if not. +int __tsan_get_report_data(void *report, const char **description, int *count, + int *stack_count, int *mop_count, int *loc_count, + int *mutex_count, int *thread_count, + int *unique_tid_count, void **sleep_trace, + unsigned long trace_size); + +/// Returns information about stack traces included in the report. +/// +/// \param report Opaque pointer to the current report. +/// \param idx Index to the report's stacks. +/// \param trace A buffer to store the stack trace. +/// \param trace_size Size in bytes of the trace buffer. +/// \returns Returns 1 if successful, 0 if not. +int __tsan_get_report_stack(void *report, unsigned long idx, void **trace, + unsigned long trace_size); + +/// Returns information about memory operations included in the report. +/// +/// \param report Opaque pointer to the current report. +/// \param idx Index to the report's memory operations. +/// \param[out] tid Thread ID of the memory operation. +/// \param[out] addr Address of the memory operation. +/// \param[out] size Size of the memory operation. +/// \param[out] write Write flag of the memory operation. +/// \param[out] atomic Atomicity flag of the memory operation. +/// \param trace A buffer to store the stack trace. +/// \param trace_size Size in bytes of the trace buffer. +/// \returns Returns 1 if successful, 0 if not. +int __tsan_get_report_mop(void *report, unsigned long idx, int *tid, + void **addr, int *size, int *write, int *atomic, + void **trace, unsigned long trace_size); + +/// Returns information about locations included in the report. +/// +/// \param report Opaque pointer to the current report. +/// \param idx Index to the report's locations. +/// \param[out] type Type of the location. +/// \param[out] addr Address of the location. +/// \param[out] start Start of the location. +/// \param[out] size Size of the location. +/// \param[out] tid Thread ID of the location. +/// \param[out] fd File descriptor of the location. +/// \param[out] suppressable Suppressable flag. +/// \param trace A buffer to store the stack trace. +/// \param trace_size Size in bytes of the trace buffer. +/// \returns Returns 1 if successful, 0 if not. +int __tsan_get_report_loc(void *report, unsigned long idx, const char **type, + void **addr, void **start, unsigned long *size, + int *tid, int *fd, int *suppressable, void **trace, + unsigned long trace_size); + +/// Returns information about mutexes included in the report. +/// +/// \param report Opaque pointer to the current report. +/// \param idx Index to the report's mutexes. +/// \param[out] mutex_id Id of the mutex. +/// \param[out] addr Address of the mutex. +/// \param[out] destroyed Destroyed mutex flag. +/// \param trace A buffer to store the stack trace. +/// \param trace_size Size in bytes of the trace buffer. +/// \returns Returns 1 if successful, 0 if not. +int __tsan_get_report_mutex(void *report, unsigned long idx, uint64_t *mutex_id, + void **addr, int *destroyed, void **trace, + unsigned long trace_size); + +/// Returns information about threads included in the report. +/// +/// \param report Opaque pointer to the current report. +/// \param idx Index to the report's threads. +/// \param[out] tid Thread ID of the thread. +/// \param[out] os_id Operating system's ID of the thread. +/// \param[out] running Running flag of the thread. +/// \param[out] name Name of the thread. +/// \param[out] parent_tid ID of the parent thread. +/// \param trace A buffer to store the stack trace. +/// \param trace_size Size in bytes of the trace buffer. +/// \returns Returns 1 if successful, 0 if not. +int __tsan_get_report_thread(void *report, unsigned long idx, int *tid, + uint64_t *os_id, int *running, const char **name, + int *parent_tid, void **trace, + unsigned long trace_size); + +/// Returns information about unique thread IDs included in the report. +/// +/// \param report Opaque pointer to the current report. +/// \param idx Index to the report's unique thread IDs. +/// \param[out] tid Unique thread ID of the report. +/// \returns Returns 1 if successful, 0 if not. +int __tsan_get_report_unique_tid(void *report, unsigned long idx, int *tid); + +/// Returns the current report. +/// +/// If TSan is currently reporting a detected issue on the current thread, +/// returns an opaque pointer to the current report. Otherwise returns NULL. +/// \returns An opaque pointer to the current report. Otherwise returns NULL. +void *__tsan_get_current_report(); + #ifdef __cplusplus } // extern "C" #endif diff --git a/compiler-rt/lib/asan/asan_interceptors.cpp b/compiler-rt/lib/asan/asan_interceptors.cpp index ad11c822be802..7aedefe81f95f 100644 --- a/compiler-rt/lib/asan/asan_interceptors.cpp +++ b/compiler-rt/lib/asan/asan_interceptors.cpp @@ -87,12 +87,6 @@ using namespace __asan; DECLARE_REAL_AND_INTERCEPTOR(void *, malloc, uptr) DECLARE_REAL_AND_INTERCEPTOR(void, free, void *) -#define ASAN_INTERCEPTOR_ENTER(ctx, func) \ - AsanInterceptorContext _ctx = {#func}; \ - ctx = (void *)&_ctx; \ - (void) ctx; \ - -#define COMMON_INTERCEPT_FUNCTION(name) ASAN_INTERCEPT_FUNC(name) #define COMMON_INTERCEPT_FUNCTION_VER(name, ver) \ ASAN_INTERCEPT_FUNC_VER(name, ver) #define COMMON_INTERCEPT_FUNCTION_VER_UNVERSIONED_FALLBACK(name, ver) \ @@ -152,24 +146,6 @@ DECLARE_REAL_AND_INTERCEPTOR(void, free, void *) *begin = *end = 0; \ } -#define COMMON_INTERCEPTOR_MEMMOVE_IMPL(ctx, to, from, size) \ - do { \ - ASAN_INTERCEPTOR_ENTER(ctx, memmove); \ - ASAN_MEMMOVE_IMPL(ctx, to, from, size); \ - } while (false) - -#define COMMON_INTERCEPTOR_MEMCPY_IMPL(ctx, to, from, size) \ - do { \ - ASAN_INTERCEPTOR_ENTER(ctx, memcpy); \ - ASAN_MEMCPY_IMPL(ctx, to, from, size); \ - } while (false) - -#define COMMON_INTERCEPTOR_MEMSET_IMPL(ctx, block, c, size) \ - do { \ - ASAN_INTERCEPTOR_ENTER(ctx, memset); \ - ASAN_MEMSET_IMPL(ctx, block, c, size); \ - } while (false) - #if CAN_SANITIZE_LEAKS #define COMMON_INTERCEPTOR_STRERROR() \ __lsan::ScopedInterceptorDisabler disabler diff --git a/compiler-rt/lib/asan/asan_interceptors.h b/compiler-rt/lib/asan/asan_interceptors.h index 93e8b8e1d545e..268096fea5e7e 100644 --- a/compiler-rt/lib/asan/asan_interceptors.h +++ b/compiler-rt/lib/asan/asan_interceptors.h @@ -166,6 +166,12 @@ DECLARE_REAL(char*, strstr, const char *s1, const char *s2) # define ASAN_INTERCEPT_FUNC(name) # endif // SANITIZER_APPLE +#define ASAN_INTERCEPTOR_ENTER(ctx, func) \ + AsanInterceptorContext _ctx = {#func}; \ + ctx = (void *)&_ctx; \ + (void) ctx; +#define COMMON_INTERCEPT_FUNCTION(name) ASAN_INTERCEPT_FUNC(name) + #endif // !SANITIZER_FUCHSIA #endif // ASAN_INTERCEPTORS_H diff --git a/compiler-rt/lib/asan/asan_interceptors_memintrinsics.cpp b/compiler-rt/lib/asan/asan_interceptors_memintrinsics.cpp index 9c316bb957493..9d1452482d3af 100644 --- a/compiler-rt/lib/asan/asan_interceptors_memintrinsics.cpp +++ b/compiler-rt/lib/asan/asan_interceptors_memintrinsics.cpp @@ -12,12 +12,51 @@ //===---------------------------------------------------------------------===// #include "asan_interceptors_memintrinsics.h" + +#include "asan_interceptors.h" #include "asan_report.h" #include "asan_stack.h" #include "asan_suppressions.h" using namespace __asan; +// memcpy is called during __asan_init() from the internals of printf(...). +// We do not treat memcpy with to==from as a bug. +// See http://llvm.org/bugs/show_bug.cgi?id=11763. +#define ASAN_MEMCPY_IMPL(ctx, to, from, size) \ + do { \ + if (LIKELY(replace_intrin_cached)) { \ + if (LIKELY(to != from)) { \ + CHECK_RANGES_OVERLAP("memcpy", to, size, from, size); \ + } \ + ASAN_READ_RANGE(ctx, from, size); \ + ASAN_WRITE_RANGE(ctx, to, size); \ + } else if (UNLIKELY(!asan_inited)) { \ + return internal_memcpy(to, from, size); \ + } \ + return REAL(memcpy)(to, from, size); \ + } while (0) + +// memset is called inside Printf. +#define ASAN_MEMSET_IMPL(ctx, block, c, size) \ + do { \ + if (LIKELY(replace_intrin_cached)) { \ + ASAN_WRITE_RANGE(ctx, block, size); \ + } else if (UNLIKELY(!asan_inited)) { \ + return internal_memset(block, c, size); \ + } \ + return REAL(memset)(block, c, size); \ + } while (0) + +#define ASAN_MEMMOVE_IMPL(ctx, to, from, size) \ + do { \ + if (LIKELY(replace_intrin_cached)) { \ + ASAN_READ_RANGE(ctx, from, size); \ + ASAN_WRITE_RANGE(ctx, to, size); \ + } \ + return internal_memmove(to, from, size); \ + } while (0) + void *__asan_memcpy(void *to, const void *from, uptr size) { ASAN_MEMCPY_IMPL(nullptr, to, from, size); } @@ -40,4 +79,26 @@ extern "C" decltype(__asan_memcpy) memcpy[[gnu::alias("__asan_memcpy")]]; extern "C" decltype(__asan_memmove) memmove[[gnu::alias("__asan_memmove")]]; extern "C" decltype(__asan_memset) memset[[gnu::alias("__asan_memset")]]; +#else // SANITIZER_FUCHSIA + +#define COMMON_INTERCEPTOR_MEMMOVE_IMPL(ctx, to, from, size) \ + do { \ + ASAN_INTERCEPTOR_ENTER(ctx, memmove); \ + ASAN_MEMMOVE_IMPL(ctx, to, from, size); \ + } while (false) + +#define COMMON_INTERCEPTOR_MEMCPY_IMPL(ctx, to, from, size) \ + do { \ + ASAN_INTERCEPTOR_ENTER(ctx, memcpy); \ + ASAN_MEMCPY_IMPL(ctx, to, from, size); \ + } while (false) + +#define COMMON_INTERCEPTOR_MEMSET_IMPL(ctx, block, c, size) \ + do { \ + ASAN_INTERCEPTOR_ENTER(ctx, memset); \ + ASAN_MEMSET_IMPL(ctx, block, c, size); \ + } while (false) + +#include "sanitizer_common/sanitizer_common_interceptors_memintrinsics.inc" + #endif // SANITIZER_FUCHSIA diff --git a/compiler-rt/lib/asan/asan_interceptors_memintrinsics.h b/compiler-rt/lib/asan/asan_interceptors_memintrinsics.h index bbc5390ceaa40..eb44f8f2f729b 100644 --- a/compiler-rt/lib/asan/asan_interceptors_memintrinsics.h +++ b/compiler-rt/lib/asan/asan_interceptors_memintrinsics.h @@ -79,43 +79,6 @@ struct AsanInterceptorContext { } \ } while (0) -// memcpy is called during __asan_init() from the internals of printf(...). -// We do not treat memcpy with to==from as a bug. -// See http://llvm.org/bugs/show_bug.cgi?id=11763. -#define ASAN_MEMCPY_IMPL(ctx, to, from, size) \ - do { \ - if (LIKELY(replace_intrin_cached)) { \ - if (LIKELY(to != from)) { \ - CHECK_RANGES_OVERLAP("memcpy", to, size, from, size); \ - } \ - ASAN_READ_RANGE(ctx, from, size); \ - ASAN_WRITE_RANGE(ctx, to, size); \ - } else if (UNLIKELY(!asan_inited)) { \ - return internal_memcpy(to, from, size); \ - } \ - return REAL(memcpy)(to, from, size); \ - } while (0) - -// memset is called inside Printf. -#define ASAN_MEMSET_IMPL(ctx, block, c, size) \ - do { \ - if (LIKELY(replace_intrin_cached)) { \ - ASAN_WRITE_RANGE(ctx, block, size); \ - } else if (UNLIKELY(!asan_inited)) { \ - return internal_memset(block, c, size); \ - } \ - return REAL(memset)(block, c, size); \ - } while (0) - -#define ASAN_MEMMOVE_IMPL(ctx, to, from, size) \ - do { \ - if (LIKELY(replace_intrin_cached)) { \ - ASAN_READ_RANGE(ctx, from, size); \ - ASAN_WRITE_RANGE(ctx, to, size); \ - } \ - return internal_memmove(to, from, size); \ - } while (0) - #define ASAN_READ_RANGE(ctx, offset, size) \ ACCESS_MEMORY_RANGE(ctx, offset, size, false) #define ASAN_WRITE_RANGE(ctx, offset, size) \ diff --git a/compiler-rt/lib/asan/asan_stack.h b/compiler-rt/lib/asan/asan_stack.h index b9575d2f427ee..02a76af847ae6 100644 --- a/compiler-rt/lib/asan/asan_stack.h +++ b/compiler-rt/lib/asan/asan_stack.h @@ -32,24 +32,24 @@ u32 GetMallocContextSize(); // as early as possible (in functions exposed to the user), as we generally // don't want stack trace to contain functions from ASan internals. -#define GET_STACK_TRACE(max_size, fast) \ - BufferedStackTrace stack; \ - if (max_size <= 2) { \ - stack.size = max_size; \ - if (max_size > 0) { \ - stack.top_frame_bp = GET_CURRENT_FRAME(); \ - stack.trace_buffer[0] = StackTrace::GetCurrentPc(); \ - if (max_size > 1) stack.trace_buffer[1] = GET_CALLER_PC(); \ - } \ - } else { \ - stack.Unwind(StackTrace::GetCurrentPc(), \ - GET_CURRENT_FRAME(), nullptr, fast, max_size); \ +#define GET_STACK_TRACE(max_size, fast) \ + UNINITIALIZED BufferedStackTrace stack; \ + if (max_size <= 2) { \ + stack.size = max_size; \ + if (max_size > 0) { \ + stack.top_frame_bp = GET_CURRENT_FRAME(); \ + stack.trace_buffer[0] = StackTrace::GetCurrentPc(); \ + if (max_size > 1) \ + stack.trace_buffer[1] = GET_CALLER_PC(); \ + } \ + } else { \ + stack.Unwind(StackTrace::GetCurrentPc(), GET_CURRENT_FRAME(), nullptr, \ + fast, max_size); \ } -#define GET_STACK_TRACE_FATAL(pc, bp) \ - BufferedStackTrace stack; \ - stack.Unwind(pc, bp, nullptr, \ - common_flags()->fast_unwind_on_fatal) +#define GET_STACK_TRACE_FATAL(pc, bp) \ + UNINITIALIZED BufferedStackTrace stack; \ + stack.Unwind(pc, bp, nullptr, common_flags()->fast_unwind_on_fatal) #define GET_STACK_TRACE_FATAL_HERE \ GET_STACK_TRACE(kStackTraceMax, common_flags()->fast_unwind_on_fatal) diff --git a/compiler-rt/lib/asan_abi/CMakeLists.txt b/compiler-rt/lib/asan_abi/CMakeLists.txt index 62d5537348144..b2f5ddba8b085 100644 --- a/compiler-rt/lib/asan_abi/CMakeLists.txt +++ b/compiler-rt/lib/asan_abi/CMakeLists.txt @@ -15,11 +15,10 @@ add_compiler_rt_component(asan_abi) if (APPLE) # TODO: set in config-ix.cmake set(ASAN_ABI_SUPPORTED_OS osx) - set(ASAN_ABI_SUPPORTED_ARCHS ${X86_64} ${ARM64}) # Compile Stable API sources into an object library. add_compiler_rt_object_libraries(RTASAN_ABI OS ${ASAN_ABI_SUPPORTED_OS} - ARCHS ${ASAN_ABI_SUPPORTED_ARCHS} + ARCHS ${ASAN_ABI_SUPPORTED_ARCH} SOURCES ${ASAN_ABI_SOURCES} ADDITIONAL_HEADERS ${ASAN_ABI_HEADERS} CFLAGS ${SANITIZER_COMMON_CFLAGS}) @@ -27,7 +26,7 @@ if (APPLE) add_compiler_rt_runtime(clang_rt.asan_abi STATIC OS ${ASAN_ABI_SUPPORTED_OS} - ARCHS ${ASAN_ABI_SUPPORTED_ARCHS} + ARCHS ${ASAN_ABI_SUPPORTED_ARCH} OBJECT_LIBS RTASAN_ABI CFLAGS ${SANITIZER_COMMON_CFLAGS} LINK_FLAGS ${WEAK_SYMBOL_LINK_FLAGS} diff --git a/compiler-rt/lib/builtins/CMakeLists.txt b/compiler-rt/lib/builtins/CMakeLists.txt index c3e22a8f354fc..66d11938d38ac 100644 --- a/compiler-rt/lib/builtins/CMakeLists.txt +++ b/compiler-rt/lib/builtins/CMakeLists.txt @@ -861,19 +861,17 @@ option(COMPILER_RT_BUILD_STANDALONE_LIBATOMIC if(COMPILER_RT_BUILD_STANDALONE_LIBATOMIC) add_custom_target(builtins-standalone-atomic) - set(BUILTIN_DEPS "") set(BUILTIN_TYPE SHARED) if(${CMAKE_SYSTEM_NAME} MATCHES "AIX") if(NOT COMPILER_RT_LIBATOMIC_LINK_FLAGS) get_aix_libatomic_default_link_flags(COMPILER_RT_LIBATOMIC_LINK_FLAGS "${CMAKE_CURRENT_SOURCE_DIR}/ppc/atomic.exp") endif() - # The compiler needs builtins to link any other binaries, so let - # clang_rt.atomic be built after builtins. - set(BUILTIN_DEPS builtins) # For different versions of cmake, SHARED behaves differently. For some # versions, we might need MODULE rather than SHARED. get_aix_libatomic_type(BUILTIN_TYPE) + else() + list(APPEND COMPILER_RT_LIBATOMIC_LINK_FLAGS -nodefaultlibs) endif() foreach (arch ${BUILTIN_SUPPORTED_ARCH}) if(CAN_TARGET_${arch}) @@ -882,7 +880,7 @@ if(COMPILER_RT_BUILD_STANDALONE_LIBATOMIC) ARCHS ${arch} SOURCES atomic.c LINK_FLAGS ${COMPILER_RT_LIBATOMIC_LINK_FLAGS} - DEPS ${BUILTIN_DEPS} + DEPS builtins PARENT_TARGET builtins-standalone-atomic) endif() endforeach() diff --git a/compiler-rt/lib/hwasan/hwasan_allocator.cpp b/compiler-rt/lib/hwasan/hwasan_allocator.cpp index 6e6e63517b762..48f1873ed6821 100644 --- a/compiler-rt/lib/hwasan/hwasan_allocator.cpp +++ b/compiler-rt/lib/hwasan/hwasan_allocator.cpp @@ -265,7 +265,7 @@ static void *HwasanAllocate(StackTrace *stack, uptr orig_size, uptr alignment, : __lsan::kDirectlyLeaked); #endif meta->SetAllocated(StackDepotPut(*stack), orig_size); - RunMallocHooks(user_ptr, size); + RunMallocHooks(user_ptr, orig_size); return user_ptr; } diff --git a/compiler-rt/lib/hwasan/hwasan_exceptions.cpp b/compiler-rt/lib/hwasan/hwasan_exceptions.cpp index c9968a5e36037..bf700bf568389 100644 --- a/compiler-rt/lib/hwasan/hwasan_exceptions.cpp +++ b/compiler-rt/lib/hwasan/hwasan_exceptions.cpp @@ -62,7 +62,8 @@ __hwasan_personality_wrapper(int version, _Unwind_Action actions, #error Unsupported architecture #endif uptr sp = get_cfa(context); - TagMemory(sp, fp - sp, 0); + TagMemory(UntagAddr(sp), UntagAddr(fp) - UntagAddr(sp), + GetTagFromPointer(sp)); } return rc; diff --git a/compiler-rt/lib/hwasan/hwasan_interceptors.cpp b/compiler-rt/lib/hwasan/hwasan_interceptors.cpp index f50a42d9d94ea..26109332a1dce 100644 --- a/compiler-rt/lib/hwasan/hwasan_interceptors.cpp +++ b/compiler-rt/lib/hwasan/hwasan_interceptors.cpp @@ -216,6 +216,7 @@ static void *mmap_interceptor(Mmap real_mmap, void *addr, SIZE_T length, return mmap_interceptor(REAL(mmap), addr, sz, prot, flags, fd, off); \ } while (false) +# include "sanitizer_common/sanitizer_common_interceptors_memintrinsics.inc" # include "sanitizer_common/sanitizer_common_interceptors.inc" struct ThreadStartArg { @@ -224,8 +225,8 @@ struct ThreadStartArg { static void *HwasanThreadStartFunc(void *arg) { __hwasan_thread_enter(); - ThreadStartArg A = *reinterpret_cast(arg); - SetSigProcMask(&A.starting_sigset_, nullptr); + SetSigProcMask(&reinterpret_cast(arg)->starting_sigset_, + nullptr); InternalFree(arg); auto self = GetThreadSelf(); auto args = hwasanThreadArgRetval().GetArgs(self); diff --git a/compiler-rt/lib/hwasan/hwasan_thread.cpp b/compiler-rt/lib/hwasan/hwasan_thread.cpp index c4ab091d956c5..2346c46e5bff3 100644 --- a/compiler-rt/lib/hwasan/hwasan_thread.cpp +++ b/compiler-rt/lib/hwasan/hwasan_thread.cpp @@ -93,7 +93,9 @@ void Thread::InitStackRingBuffer(uptr stack_buffer_start, void Thread::ClearShadowForThreadStackAndTLS() { if (stack_top_ != stack_bottom_) - TagMemory(stack_bottom_, stack_top_ - stack_bottom_, 0); + TagMemory(UntagAddr(stack_bottom_), + UntagAddr(stack_top_) - UntagAddr(stack_bottom_), + GetTagFromPointer(stack_top_)); if (tls_begin_ != tls_end_) TagMemory(tls_begin_, tls_end_ - tls_begin_, 0); } diff --git a/compiler-rt/lib/lsan/lsan_common.cpp b/compiler-rt/lib/lsan/lsan_common.cpp index 2a6b53ddf0b1e..92496422607d9 100644 --- a/compiler-rt/lib/lsan/lsan_common.cpp +++ b/compiler-rt/lib/lsan/lsan_common.cpp @@ -241,8 +241,6 @@ static LeakSuppressionContext *GetSuppressionContext() { return suppression_ctx; } -static InternalMmapVectorNoCtor root_regions; - void InitCommonLsan() { if (common_flags()->detect_leaks) { // Initialization which can fail or print warnings should only be done if @@ -523,32 +521,39 @@ static void ProcessThreads(SuspendedThreadsList const &suspended_threads, # endif // SANITIZER_FUCHSIA -bool HasRootRegions() { return !root_regions.empty(); } +// A map that contains [region_begin, region_end) pairs. +using RootRegions = DenseMap, uptr>; -static void ScanRootRegion(Frontier *frontier, const Region &root_region, - uptr region_begin, uptr region_end, - bool is_readable) { - uptr intersection_begin = Max(root_region.begin, region_begin); - uptr intersection_end = Min(region_end, root_region.end); - if (intersection_begin >= intersection_end) - return; - LOG_POINTERS("Root region %p-%p intersects with mapped region %p-%p (%s)\n", - (void *)root_region.begin, (void *)root_region.end, - (void *)region_begin, (void *)region_end, - is_readable ? "readable" : "unreadable"); - if (is_readable) - ScanRangeForPointers(intersection_begin, intersection_end, frontier, "ROOT", - kReachable); +static RootRegions &GetRootRegionsLocked() { + global_mutex.CheckLocked(); + static RootRegions *regions = nullptr; + alignas(RootRegions) static char placeholder[sizeof(RootRegions)]; + if (!regions) + regions = new (placeholder) RootRegions(); + return *regions; } +bool HasRootRegions() { return !GetRootRegionsLocked().empty(); } + void ScanRootRegions(Frontier *frontier, const InternalMmapVectorNoCtor &mapped_regions) { - if (!flags()->use_root_regions || mapped_regions.empty()) + if (!flags()->use_root_regions) return; - for (const auto &m : mapped_regions) - for (const auto &r : root_regions) - ScanRootRegion(frontier, r, m.begin, m.end, true); + InternalMmapVector regions; + GetRootRegionsLocked().forEach([&](const auto &kv) { + regions.push_back({kv.first.first, kv.first.second}); + return true; + }); + + InternalMmapVector intersection; + Intersect(mapped_regions, regions, intersection); + + for (const Region &r : intersection) { + LOG_POINTERS("Root region intersects with mapped region at %p-%p\n", + (void *)r.begin, (void *)r.end); + ScanRangeForPointers(r.begin, r.end, frontier, "ROOT", kReachable); + } } // Scans root regions for heap pointers. @@ -1022,7 +1027,7 @@ void __lsan_register_root_region(const void *begin, uptr size) { CHECK_LT(b, e); Lock l(&global_mutex); - root_regions.push_back({b, e}); + ++GetRootRegionsLocked()[{b, e}]; #endif // CAN_SANITIZE_LEAKS } @@ -1032,18 +1037,14 @@ void __lsan_unregister_root_region(const void *begin, uptr size) { uptr b = reinterpret_cast(begin); uptr e = b + size; CHECK_LT(b, e); + VReport(1, "Unregistered root region at %p of size %zu\n", begin, size); { Lock l(&global_mutex); - for (uptr i = 0; i < root_regions.size(); i++) { - Region region = root_regions[i]; - if (region.begin == b && region.end == e) { - uptr last_index = root_regions.size() - 1; - root_regions[i] = root_regions[last_index]; - root_regions.pop_back(); - VReport(1, "Unregistered root region at %p of size %zu\n", begin, size); - return; - } + if (auto *f = GetRootRegionsLocked().find({b, e})) { + if (--(f->second) == 0) + GetRootRegionsLocked().erase(f); + return; } } Report( diff --git a/compiler-rt/lib/lsan/lsan_common.h b/compiler-rt/lib/lsan/lsan_common.h index 0ef74bbc1050d..93204462f6a04 100644 --- a/compiler-rt/lib/lsan/lsan_common.h +++ b/compiler-rt/lib/lsan/lsan_common.h @@ -16,6 +16,7 @@ #include "sanitizer_common/sanitizer_allocator.h" #include "sanitizer_common/sanitizer_common.h" +#include "sanitizer_common/sanitizer_common_range.h" #include "sanitizer_common/sanitizer_internal_defs.h" #include "sanitizer_common/sanitizer_platform.h" #include "sanitizer_common/sanitizer_stackdepot.h" @@ -79,11 +80,6 @@ enum IgnoreObjectResult { kIgnoreObjectInvalid }; -struct Range { - uptr begin; - uptr end; -}; - //// -------------------------------------------------------------------------- //// Poisoning prototypes. //// -------------------------------------------------------------------------- @@ -239,11 +235,6 @@ void InitializePlatformSpecificModules(); void ProcessGlobalRegions(Frontier *frontier); void ProcessPlatformSpecificAllocations(Frontier *frontier); -struct Region { - uptr begin; - uptr end; -}; - // LockStuffAndStopTheWorld can start to use Scan* calls to collect into // this Frontier vector before the StopTheWorldCallback actually runs. // This is used when the OS has a unified callback API for suspending @@ -256,6 +247,8 @@ struct CheckForLeaksParam { bool success = false; }; +using Region = Range; + bool HasRootRegions(); void ScanRootRegions(Frontier *frontier, const InternalMmapVectorNoCtor ®ion); diff --git a/compiler-rt/lib/lsan/lsan_interceptors.cpp b/compiler-rt/lib/lsan/lsan_interceptors.cpp index fe852b9fcfa8d..ade9dfdab40c4 100644 --- a/compiler-rt/lib/lsan/lsan_interceptors.cpp +++ b/compiler-rt/lib/lsan/lsan_interceptors.cpp @@ -415,8 +415,10 @@ INTERCEPTOR(char *, strerror, int errnum) { #if SANITIZER_POSIX -extern "C" void *__lsan_thread_start_func(void *arg) { - atomic_uintptr_t *atomic_tid = (atomic_uintptr_t *)arg; +template +static void *ThreadStartFunc(void *arg) { + u32 parent_tid = (uptr)arg; + uptr tid = ThreadCreate(parent_tid, Detached); // Wait until the last iteration to maximize the chance that we are the last // destructor to run. #if !SANITIZER_NETBSD && !SANITIZER_FREEBSD @@ -425,12 +427,8 @@ extern "C" void *__lsan_thread_start_func(void *arg) { Report("LeakSanitizer: failed to set thread key.\n"); Die(); } -#endif - int tid = 0; - while ((tid = atomic_load(atomic_tid, memory_order_acquire)) == 0) - internal_sched_yield(); +# endif ThreadStart(tid, GetTid()); - atomic_store(atomic_tid, 0, memory_order_release); auto self = GetThreadSelf(); auto args = GetThreadArgRetval().GetArgs(self); void *retval = (*args.routine)(args.arg_retval); @@ -442,17 +440,19 @@ INTERCEPTOR(int, pthread_create, void *th, void *attr, void *(*callback)(void *), void *param) { ENSURE_LSAN_INITED; EnsureMainThreadIDIsCorrect(); + bool detached = [attr]() { int d = 0; return attr && !pthread_attr_getdetachstate(attr, &d) && IsStateDetached(d); }(); + __sanitizer_pthread_attr_t myattr; if (!attr) { pthread_attr_init(&myattr); attr = &myattr; } AdjustStackSize(attr); - atomic_uintptr_t atomic_tid = {}; + uptr this_tid = GetCurrentThreadId(); int result; { // Ignore all allocations made by pthread_create: thread stack/TLS may be @@ -461,18 +461,12 @@ INTERCEPTOR(int, pthread_create, void *th, void *attr, // objects, the latter are calculated by obscure pointer arithmetic. ScopedInterceptorDisabler disabler; GetThreadArgRetval().Create(detached, {callback, param}, [&]() -> uptr { - result = - REAL(pthread_create)(th, attr, __lsan_thread_start_func, &atomic_tid); + result = REAL(pthread_create)( + th, attr, detached ? ThreadStartFunc : ThreadStartFunc, + (void *)this_tid); return result ? 0 : *(uptr *)(th); }); } - if (result == 0) { - int tid = ThreadCreate(GetCurrentThreadId(), detached); - CHECK_NE(tid, kMainTid); - atomic_store(&atomic_tid, tid, memory_order_release); - while (atomic_load(&atomic_tid, memory_order_acquire) != 0) - internal_sched_yield(); - } if (attr == &myattr) pthread_attr_destroy(&myattr); return result; diff --git a/compiler-rt/lib/memprof/memprof_interceptors.cpp b/compiler-rt/lib/memprof/memprof_interceptors.cpp index 31392a58f3dab..8925ec5bbaa37 100644 --- a/compiler-rt/lib/memprof/memprof_interceptors.cpp +++ b/compiler-rt/lib/memprof/memprof_interceptors.cpp @@ -52,11 +52,6 @@ using namespace __memprof; DECLARE_REAL_AND_INTERCEPTOR(void *, malloc, uptr) DECLARE_REAL_AND_INTERCEPTOR(void, free, void *) -#define MEMPROF_INTERCEPTOR_ENTER(ctx, func) \ - ctx = 0; \ - (void)ctx; - -#define COMMON_INTERCEPT_FUNCTION(name) MEMPROF_INTERCEPT_FUNC(name) #define COMMON_INTERCEPT_FUNCTION_VER(name, ver) \ MEMPROF_INTERCEPT_FUNC_VER(name, ver) #define COMMON_INTERCEPT_FUNCTION_VER_UNVERSIONED_FALLBACK(name, ver) \ @@ -105,24 +100,6 @@ DECLARE_REAL_AND_INTERCEPTOR(void, free, void *) *begin = *end = 0; \ } -#define COMMON_INTERCEPTOR_MEMMOVE_IMPL(ctx, to, from, size) \ - do { \ - MEMPROF_INTERCEPTOR_ENTER(ctx, memmove); \ - MEMPROF_MEMMOVE_IMPL(to, from, size); \ - } while (false) - -#define COMMON_INTERCEPTOR_MEMCPY_IMPL(ctx, to, from, size) \ - do { \ - MEMPROF_INTERCEPTOR_ENTER(ctx, memcpy); \ - MEMPROF_MEMCPY_IMPL(to, from, size); \ - } while (false) - -#define COMMON_INTERCEPTOR_MEMSET_IMPL(ctx, block, c, size) \ - do { \ - MEMPROF_INTERCEPTOR_ENTER(ctx, memset); \ - MEMPROF_MEMSET_IMPL(block, c, size); \ - } while (false) - #include "sanitizer_common/sanitizer_common_interceptors.inc" #define COMMON_SYSCALL_PRE_READ_RANGE(p, s) MEMPROF_READ_RANGE(p, s) diff --git a/compiler-rt/lib/memprof/memprof_interceptors.h b/compiler-rt/lib/memprof/memprof_interceptors.h index 879a1e1061e5e..20edef42a5150 100644 --- a/compiler-rt/lib/memprof/memprof_interceptors.h +++ b/compiler-rt/lib/memprof/memprof_interceptors.h @@ -57,4 +57,10 @@ DECLARE_REAL(char *, strstr, const char *s1, const char *s2) ver, #name); \ } while (0) +#define MEMPROF_INTERCEPTOR_ENTER(ctx, func) \ + ctx = 0; \ + (void)ctx; + +#define COMMON_INTERCEPT_FUNCTION(name) MEMPROF_INTERCEPT_FUNC(name) + #endif // MEMPROF_INTERCEPTORS_H diff --git a/compiler-rt/lib/memprof/memprof_interceptors_memintrinsics.cpp b/compiler-rt/lib/memprof/memprof_interceptors_memintrinsics.cpp index 4eb409362b57f..dae2ab5dbb9bc 100644 --- a/compiler-rt/lib/memprof/memprof_interceptors_memintrinsics.cpp +++ b/compiler-rt/lib/memprof/memprof_interceptors_memintrinsics.cpp @@ -12,10 +12,71 @@ //===---------------------------------------------------------------------===// #include "memprof_interceptors_memintrinsics.h" + +#include "memprof_interceptors.h" #include "memprof_stack.h" using namespace __memprof; +// memcpy is called during __memprof_init() from the internals of printf(...). +// We do not treat memcpy with to==from as a bug. +// See http://llvm.org/bugs/show_bug.cgi?id=11763. +#define MEMPROF_MEMCPY_IMPL(to, from, size) \ + do { \ + if (UNLIKELY(!memprof_inited)) \ + return internal_memcpy(to, from, size); \ + if (memprof_init_is_running) { \ + return REAL(memcpy)(to, from, size); \ + } \ + ENSURE_MEMPROF_INITED(); \ + MEMPROF_READ_RANGE(from, size); \ + MEMPROF_WRITE_RANGE(to, size); \ + return REAL(memcpy)(to, from, size); \ + } while (0) + +// memset is called inside Printf. +#define MEMPROF_MEMSET_IMPL(block, c, size) \ + do { \ + if (UNLIKELY(!memprof_inited)) \ + return internal_memset(block, c, size); \ + if (memprof_init_is_running) { \ + return REAL(memset)(block, c, size); \ + } \ + ENSURE_MEMPROF_INITED(); \ + MEMPROF_WRITE_RANGE(block, size); \ + return REAL(memset)(block, c, size); \ + } while (0) + +#define MEMPROF_MEMMOVE_IMPL(to, from, size) \ + do { \ + if (UNLIKELY(!memprof_inited)) \ + return internal_memmove(to, from, size); \ + ENSURE_MEMPROF_INITED(); \ + MEMPROF_READ_RANGE(from, size); \ + MEMPROF_WRITE_RANGE(to, size); \ + return internal_memmove(to, from, size); \ + } while (0) + +#define COMMON_INTERCEPTOR_MEMMOVE_IMPL(ctx, to, from, size) \ + do { \ + MEMPROF_INTERCEPTOR_ENTER(ctx, memmove); \ + MEMPROF_MEMMOVE_IMPL(to, from, size); \ + } while (false) + +#define COMMON_INTERCEPTOR_MEMCPY_IMPL(ctx, to, from, size) \ + do { \ + MEMPROF_INTERCEPTOR_ENTER(ctx, memcpy); \ + MEMPROF_MEMCPY_IMPL(to, from, size); \ + } while (false) + +#define COMMON_INTERCEPTOR_MEMSET_IMPL(ctx, block, c, size) \ + do { \ + MEMPROF_INTERCEPTOR_ENTER(ctx, memset); \ + MEMPROF_MEMSET_IMPL(block, c, size); \ + } while (false) + +#include "sanitizer_common/sanitizer_common_interceptors_memintrinsics.inc" + void *__memprof_memcpy(void *to, const void *from, uptr size) { MEMPROF_MEMCPY_IMPL(to, from, size); } diff --git a/compiler-rt/lib/memprof/memprof_interceptors_memintrinsics.h b/compiler-rt/lib/memprof/memprof_interceptors_memintrinsics.h index 348461d55c414..0b87a6f3522af 100644 --- a/compiler-rt/lib/memprof/memprof_interceptors_memintrinsics.h +++ b/compiler-rt/lib/memprof/memprof_interceptors_memintrinsics.h @@ -32,45 +32,6 @@ namespace __memprof { __memprof_record_access_range(offset, size); \ } while (0) -// memcpy is called during __memprof_init() from the internals of printf(...). -// We do not treat memcpy with to==from as a bug. -// See http://llvm.org/bugs/show_bug.cgi?id=11763. -#define MEMPROF_MEMCPY_IMPL(to, from, size) \ - do { \ - if (UNLIKELY(!memprof_inited)) \ - return internal_memcpy(to, from, size); \ - if (memprof_init_is_running) { \ - return REAL(memcpy)(to, from, size); \ - } \ - ENSURE_MEMPROF_INITED(); \ - MEMPROF_READ_RANGE(from, size); \ - MEMPROF_WRITE_RANGE(to, size); \ - return REAL(memcpy)(to, from, size); \ - } while (0) - -// memset is called inside Printf. -#define MEMPROF_MEMSET_IMPL(block, c, size) \ - do { \ - if (UNLIKELY(!memprof_inited)) \ - return internal_memset(block, c, size); \ - if (memprof_init_is_running) { \ - return REAL(memset)(block, c, size); \ - } \ - ENSURE_MEMPROF_INITED(); \ - MEMPROF_WRITE_RANGE(block, size); \ - return REAL(memset)(block, c, size); \ - } while (0) - -#define MEMPROF_MEMMOVE_IMPL(to, from, size) \ - do { \ - if (UNLIKELY(!memprof_inited)) \ - return internal_memmove(to, from, size); \ - ENSURE_MEMPROF_INITED(); \ - MEMPROF_READ_RANGE(from, size); \ - MEMPROF_WRITE_RANGE(to, size); \ - return internal_memmove(to, from, size); \ - } while (0) - #define MEMPROF_READ_RANGE(offset, size) ACCESS_MEMORY_RANGE(offset, size) #define MEMPROF_WRITE_RANGE(offset, size) ACCESS_MEMORY_RANGE(offset, size) diff --git a/compiler-rt/lib/msan/msan.h b/compiler-rt/lib/msan/msan.h index 5d8ea52668abe..50cbc5fe44d37 100644 --- a/compiler-rt/lib/msan/msan.h +++ b/compiler-rt/lib/msan/msan.h @@ -269,31 +269,33 @@ const int STACK_TRACE_TAG_POISON = StackTrace::TAG_CUSTOM + 1; const int STACK_TRACE_TAG_FIELDS = STACK_TRACE_TAG_POISON + 1; const int STACK_TRACE_TAG_VPTR = STACK_TRACE_TAG_FIELDS + 1; -#define GET_MALLOC_STACK_TRACE \ - BufferedStackTrace stack; \ - if (__msan_get_track_origins() && msan_inited) \ - stack.Unwind(StackTrace::GetCurrentPc(), GET_CURRENT_FRAME(), \ - nullptr, common_flags()->fast_unwind_on_malloc, \ - common_flags()->malloc_context_size) +#define GET_MALLOC_STACK_TRACE \ + UNINITIALIZED BufferedStackTrace stack; \ + if (__msan_get_track_origins() && msan_inited) { \ + stack.Unwind(StackTrace::GetCurrentPc(), GET_CURRENT_FRAME(), nullptr, \ + common_flags()->fast_unwind_on_malloc, \ + common_flags()->malloc_context_size); \ + } // For platforms which support slow unwinder only, we restrict the store context // size to 1, basically only storing the current pc. We do this because the slow // unwinder which is based on libunwind is not async signal safe and causes // random freezes in forking applications as well as in signal handlers. -#define GET_STORE_STACK_TRACE_PC_BP(pc, bp) \ - BufferedStackTrace stack; \ - if (__msan_get_track_origins() > 1 && msan_inited) { \ - int size = flags()->store_context_size; \ - if (!SANITIZER_CAN_FAST_UNWIND) \ - size = Min(size, 1); \ - stack.Unwind(pc, bp, nullptr, common_flags()->fast_unwind_on_malloc, size);\ +#define GET_STORE_STACK_TRACE_PC_BP(pc, bp) \ + UNINITIALIZED BufferedStackTrace stack; \ + if (__msan_get_track_origins() > 1 && msan_inited) { \ + int size = flags()->store_context_size; \ + if (!SANITIZER_CAN_FAST_UNWIND) \ + size = Min(size, 1); \ + stack.Unwind(pc, bp, nullptr, common_flags()->fast_unwind_on_malloc, \ + size); \ } #define GET_STORE_STACK_TRACE \ GET_STORE_STACK_TRACE_PC_BP(StackTrace::GetCurrentPc(), GET_CURRENT_FRAME()) #define GET_FATAL_STACK_TRACE_PC_BP(pc, bp) \ - BufferedStackTrace stack; \ + UNINITIALIZED BufferedStackTrace stack; \ if (msan_inited) { \ stack.Unwind(pc, bp, nullptr, common_flags()->fast_unwind_on_fatal); \ } diff --git a/compiler-rt/lib/msan/msan_interceptors.cpp b/compiler-rt/lib/msan/msan_interceptors.cpp index ed5e91483ae93..96abc47305cad 100644 --- a/compiler-rt/lib/msan/msan_interceptors.cpp +++ b/compiler-rt/lib/msan/msan_interceptors.cpp @@ -1421,6 +1421,7 @@ int OnExit() { } while (false) #include "sanitizer_common/sanitizer_platform_interceptors.h" +#include "sanitizer_common/sanitizer_common_interceptors_memintrinsics.inc" #include "sanitizer_common/sanitizer_common_interceptors.inc" static uptr signal_impl(int signo, uptr cb); diff --git a/compiler-rt/lib/sanitizer_common/CMakeLists.txt b/compiler-rt/lib/sanitizer_common/CMakeLists.txt index 614e63d5f9eb5..d4187a925d39a 100644 --- a/compiler-rt/lib/sanitizer_common/CMakeLists.txt +++ b/compiler-rt/lib/sanitizer_common/CMakeLists.txt @@ -3,6 +3,7 @@ set(SANITIZER_SOURCES_NOTERMINATION sanitizer_allocator.cpp + sanitizer_common_range.cpp sanitizer_common.cpp sanitizer_deadlock_detector1.cpp sanitizer_deadlock_detector2.cpp @@ -127,6 +128,7 @@ set(SANITIZER_IMPL_HEADERS sanitizer_common_interceptors.inc sanitizer_common_interceptors_format.inc sanitizer_common_interceptors_ioctl.inc + sanitizer_common_interceptors_memintrinsics.inc sanitizer_common_interface.inc sanitizer_common_interface_posix.inc sanitizer_common_syscalls.inc diff --git a/compiler-rt/lib/sanitizer_common/sanitizer_allocator_primary32.h b/compiler-rt/lib/sanitizer_common/sanitizer_allocator_primary32.h index f2471efced613..52fe3fe3d15bd 100644 --- a/compiler-rt/lib/sanitizer_common/sanitizer_allocator_primary32.h +++ b/compiler-rt/lib/sanitizer_common/sanitizer_allocator_primary32.h @@ -353,7 +353,7 @@ class SizeClassAllocator32 { DCHECK_GT(max_count, 0); TransferBatch *b = nullptr; constexpr uptr kShuffleArraySize = 48; - uptr shuffle_array[kShuffleArraySize]; + UNINITIALIZED uptr shuffle_array[kShuffleArraySize]; uptr count = 0; for (uptr i = region; i < region + n_chunks * size; i += size) { shuffle_array[count++] = i; diff --git a/compiler-rt/lib/sanitizer_common/sanitizer_common.h b/compiler-rt/lib/sanitizer_common/sanitizer_common.h index afd1a786d5d33..302b4437d64bd 100644 --- a/compiler-rt/lib/sanitizer_common/sanitizer_common.h +++ b/compiler-rt/lib/sanitizer_common/sanitizer_common.h @@ -1083,14 +1083,21 @@ template class ArrayRef { public: ArrayRef() {} - ArrayRef(T *begin, T *end) : begin_(begin), end_(end) {} + ArrayRef(const T *begin, const T *end) : begin_(begin), end_(end) {} - T *begin() { return begin_; } - T *end() { return end_; } + template + ArrayRef(const C &src) : ArrayRef(src.data(), src.data() + src.size()) {} + + const T *begin() const { return begin_; } + const T *end() const { return end_; } + + bool empty() const { return begin_ == end_; } + + uptr size() const { return end_ - begin_; } private: - T *begin_ = nullptr; - T *end_ = nullptr; + const T *begin_ = nullptr; + const T *end_ = nullptr; }; } // namespace __sanitizer diff --git a/compiler-rt/lib/sanitizer_common/sanitizer_common_interceptors.inc b/compiler-rt/lib/sanitizer_common/sanitizer_common_interceptors.inc index db090d2d8fa27..efd7c75a18209 100644 --- a/compiler-rt/lib/sanitizer_common/sanitizer_common_interceptors.inc +++ b/compiler-rt/lib/sanitizer_common/sanitizer_common_interceptors.inc @@ -26,9 +26,6 @@ // COMMON_INTERCEPTOR_SET_PTHREAD_NAME // COMMON_INTERCEPTOR_HANDLE_RECVMSG // COMMON_INTERCEPTOR_NOTHING_IS_INITIALIZED -// COMMON_INTERCEPTOR_MEMSET_IMPL -// COMMON_INTERCEPTOR_MEMMOVE_IMPL -// COMMON_INTERCEPTOR_MEMCPY_IMPL // COMMON_INTERCEPTOR_MMAP_IMPL // COMMON_INTERCEPTOR_COPY_STRING // COMMON_INTERCEPTOR_STRNDUP_IMPL @@ -198,15 +195,6 @@ extern const short *_tolower_tab_; #define wait4 __wait4_time64 #endif -// Platform-specific options. -#if SANITIZER_APPLE -#define PLATFORM_HAS_DIFFERENT_MEMCPY_AND_MEMMOVE 0 -#elif SANITIZER_WINDOWS64 -#define PLATFORM_HAS_DIFFERENT_MEMCPY_AND_MEMMOVE 0 -#else -#define PLATFORM_HAS_DIFFERENT_MEMCPY_AND_MEMMOVE 1 -#endif // SANITIZER_APPLE - #ifndef COMMON_INTERCEPTOR_INITIALIZE_RANGE #define COMMON_INTERCEPTOR_INITIALIZE_RANGE(p, size) {} #endif @@ -302,47 +290,6 @@ extern const short *_tolower_tab_; COMMON_INTERCEPT_FUNCTION(fn) #endif -#ifndef COMMON_INTERCEPTOR_MEMSET_IMPL -#define COMMON_INTERCEPTOR_MEMSET_IMPL(ctx, dst, v, size) \ - { \ - if (COMMON_INTERCEPTOR_NOTHING_IS_INITIALIZED) \ - return internal_memset(dst, v, size); \ - COMMON_INTERCEPTOR_ENTER(ctx, memset, dst, v, size); \ - if (common_flags()->intercept_intrin) \ - COMMON_INTERCEPTOR_WRITE_RANGE(ctx, dst, size); \ - return REAL(memset)(dst, v, size); \ - } -#endif - -#ifndef COMMON_INTERCEPTOR_MEMMOVE_IMPL -#define COMMON_INTERCEPTOR_MEMMOVE_IMPL(ctx, dst, src, size) \ - { \ - if (COMMON_INTERCEPTOR_NOTHING_IS_INITIALIZED) \ - return internal_memmove(dst, src, size); \ - COMMON_INTERCEPTOR_ENTER(ctx, memmove, dst, src, size); \ - if (common_flags()->intercept_intrin) { \ - COMMON_INTERCEPTOR_WRITE_RANGE(ctx, dst, size); \ - COMMON_INTERCEPTOR_READ_RANGE(ctx, src, size); \ - } \ - return REAL(memmove)(dst, src, size); \ - } -#endif - -#ifndef COMMON_INTERCEPTOR_MEMCPY_IMPL -#define COMMON_INTERCEPTOR_MEMCPY_IMPL(ctx, dst, src, size) \ - { \ - if (COMMON_INTERCEPTOR_NOTHING_IS_INITIALIZED) { \ - return internal_memmove(dst, src, size); \ - } \ - COMMON_INTERCEPTOR_ENTER(ctx, memcpy, dst, src, size); \ - if (common_flags()->intercept_intrin) { \ - COMMON_INTERCEPTOR_WRITE_RANGE(ctx, dst, size); \ - COMMON_INTERCEPTOR_READ_RANGE(ctx, src, size); \ - } \ - return REAL(memcpy)(dst, src, size); \ - } -#endif - #ifndef COMMON_INTERCEPTOR_MMAP_IMPL #define COMMON_INTERCEPTOR_MMAP_IMPL(ctx, mmap, addr, sz, prot, flags, fd, \ off) \ @@ -841,57 +788,6 @@ INTERCEPTOR(char *, strpbrk, const char *s1, const char *s2) { #define INIT_STRPBRK #endif -#if SANITIZER_INTERCEPT_MEMSET -INTERCEPTOR(void *, memset, void *dst, int v, uptr size) { - void *ctx; - COMMON_INTERCEPTOR_MEMSET_IMPL(ctx, dst, v, size); -} - -#define INIT_MEMSET COMMON_INTERCEPT_FUNCTION(memset) -#else -#define INIT_MEMSET -#endif - -#if SANITIZER_INTERCEPT_MEMMOVE -INTERCEPTOR(void *, memmove, void *dst, const void *src, uptr size) { - void *ctx; - COMMON_INTERCEPTOR_MEMMOVE_IMPL(ctx, dst, src, size); -} - -#define INIT_MEMMOVE COMMON_INTERCEPT_FUNCTION(memmove) -#else -#define INIT_MEMMOVE -#endif - -#if SANITIZER_INTERCEPT_MEMCPY -INTERCEPTOR(void *, memcpy, void *dst, const void *src, uptr size) { - // On OS X, calling internal_memcpy here will cause memory corruptions, - // because memcpy and memmove are actually aliases of the same - // implementation. We need to use internal_memmove here. - // N.B.: If we switch this to internal_ we'll have to use internal_memmove - // due to memcpy being an alias of memmove on OS X. - void *ctx; -#if PLATFORM_HAS_DIFFERENT_MEMCPY_AND_MEMMOVE - COMMON_INTERCEPTOR_MEMCPY_IMPL(ctx, dst, src, size); -#else - COMMON_INTERCEPTOR_MEMMOVE_IMPL(ctx, dst, src, size); -#endif -} - -#define INIT_MEMCPY \ - do { \ - if (PLATFORM_HAS_DIFFERENT_MEMCPY_AND_MEMMOVE) { \ - COMMON_INTERCEPT_FUNCTION(memcpy); \ - } else { \ - ASSIGN_REAL(memcpy, memmove); \ - } \ - CHECK(REAL(memcpy)); \ - } while (false) - -#else -#define INIT_MEMCPY -#endif - #if SANITIZER_INTERCEPT_MEMCMP DECLARE_WEAK_INTERCEPTOR_HOOK(__sanitizer_weak_hook_memcmp, uptr called_pc, const void *s1, const void *s2, uptr n, @@ -5791,105 +5687,6 @@ INTERCEPTOR(int, capset, void *hdrp, const void *datap) { #define INIT_CAPGET #endif -#if SANITIZER_INTERCEPT_AEABI_MEM -INTERCEPTOR(void *, __aeabi_memmove, void *to, const void *from, uptr size) { - void *ctx; - COMMON_INTERCEPTOR_MEMMOVE_IMPL(ctx, to, from, size); -} - -INTERCEPTOR(void *, __aeabi_memmove4, void *to, const void *from, uptr size) { - void *ctx; - COMMON_INTERCEPTOR_MEMMOVE_IMPL(ctx, to, from, size); -} - -INTERCEPTOR(void *, __aeabi_memmove8, void *to, const void *from, uptr size) { - void *ctx; - COMMON_INTERCEPTOR_MEMMOVE_IMPL(ctx, to, from, size); -} - -INTERCEPTOR(void *, __aeabi_memcpy, void *to, const void *from, uptr size) { - void *ctx; - COMMON_INTERCEPTOR_MEMCPY_IMPL(ctx, to, from, size); -} - -INTERCEPTOR(void *, __aeabi_memcpy4, void *to, const void *from, uptr size) { - void *ctx; - COMMON_INTERCEPTOR_MEMCPY_IMPL(ctx, to, from, size); -} - -INTERCEPTOR(void *, __aeabi_memcpy8, void *to, const void *from, uptr size) { - void *ctx; - COMMON_INTERCEPTOR_MEMCPY_IMPL(ctx, to, from, size); -} - -// Note the argument order. -INTERCEPTOR(void *, __aeabi_memset, void *block, uptr size, int c) { - void *ctx; - COMMON_INTERCEPTOR_MEMSET_IMPL(ctx, block, c, size); -} - -INTERCEPTOR(void *, __aeabi_memset4, void *block, uptr size, int c) { - void *ctx; - COMMON_INTERCEPTOR_MEMSET_IMPL(ctx, block, c, size); -} - -INTERCEPTOR(void *, __aeabi_memset8, void *block, uptr size, int c) { - void *ctx; - COMMON_INTERCEPTOR_MEMSET_IMPL(ctx, block, c, size); -} - -INTERCEPTOR(void *, __aeabi_memclr, void *block, uptr size) { - void *ctx; - COMMON_INTERCEPTOR_MEMSET_IMPL(ctx, block, 0, size); -} - -INTERCEPTOR(void *, __aeabi_memclr4, void *block, uptr size) { - void *ctx; - COMMON_INTERCEPTOR_MEMSET_IMPL(ctx, block, 0, size); -} - -INTERCEPTOR(void *, __aeabi_memclr8, void *block, uptr size) { - void *ctx; - COMMON_INTERCEPTOR_MEMSET_IMPL(ctx, block, 0, size); -} - -#define INIT_AEABI_MEM \ - COMMON_INTERCEPT_FUNCTION(__aeabi_memmove); \ - COMMON_INTERCEPT_FUNCTION(__aeabi_memmove4); \ - COMMON_INTERCEPT_FUNCTION(__aeabi_memmove8); \ - COMMON_INTERCEPT_FUNCTION(__aeabi_memcpy); \ - COMMON_INTERCEPT_FUNCTION(__aeabi_memcpy4); \ - COMMON_INTERCEPT_FUNCTION(__aeabi_memcpy8); \ - COMMON_INTERCEPT_FUNCTION(__aeabi_memset); \ - COMMON_INTERCEPT_FUNCTION(__aeabi_memset4); \ - COMMON_INTERCEPT_FUNCTION(__aeabi_memset8); \ - COMMON_INTERCEPT_FUNCTION(__aeabi_memclr); \ - COMMON_INTERCEPT_FUNCTION(__aeabi_memclr4); \ - COMMON_INTERCEPT_FUNCTION(__aeabi_memclr8); -#else -#define INIT_AEABI_MEM -#endif // SANITIZER_INTERCEPT_AEABI_MEM - -#if SANITIZER_INTERCEPT___BZERO -INTERCEPTOR(void *, __bzero, void *block, uptr size) { - void *ctx; - COMMON_INTERCEPTOR_MEMSET_IMPL(ctx, block, 0, size); -} -#define INIT___BZERO COMMON_INTERCEPT_FUNCTION(__bzero); -#else -#define INIT___BZERO -#endif // SANITIZER_INTERCEPT___BZERO - -#if SANITIZER_INTERCEPT_BZERO -INTERCEPTOR(void *, bzero, void *block, uptr size) { - void *ctx; - COMMON_INTERCEPTOR_MEMSET_IMPL(ctx, block, 0, size); -} -#define INIT_BZERO COMMON_INTERCEPT_FUNCTION(bzero); -#else -#define INIT_BZERO -#endif // SANITIZER_INTERCEPT_BZERO - #if SANITIZER_INTERCEPT_FTIME INTERCEPTOR(int, ftime, __sanitizer_timeb *tp) { void *ctx; @@ -10362,12 +10159,18 @@ INTERCEPTOR(int, argp_parse, const struct argp *argp, int argc, char **argv, #include "sanitizer_common_interceptors_netbsd_compat.inc" +namespace __sanitizer { +void InitializeMemintrinsicInterceptors(); +} // namespace __sanitizer + static void InitializeCommonInterceptors() { #if SI_POSIX static u64 metadata_mem[sizeof(MetadataHashMap) / sizeof(u64) + 1]; interceptor_metadata_map = new ((void *)&metadata_mem) MetadataHashMap(); #endif + __sanitizer::InitializeMemintrinsicInterceptors(); + INIT_MMAP; INIT_MMAP64; INIT_TEXTDOMAIN; @@ -10389,9 +10192,6 @@ static void InitializeCommonInterceptors() { INIT_STRPBRK; INIT_STRXFRM; INIT___STRXFRM_L; - INIT_MEMSET; - INIT_MEMMOVE; - INIT_MEMCPY; INIT_MEMCHR; INIT_MEMCMP; INIT_BCMP; @@ -10563,9 +10363,6 @@ static void InitializeCommonInterceptors() { INIT_GETIFADDRS; INIT_IF_INDEXTONAME; INIT_CAPGET; - INIT_AEABI_MEM; - INIT___BZERO; - INIT_BZERO; INIT_FTIME; INIT_XDR; INIT_XDRREC_LINUX; diff --git a/compiler-rt/lib/sanitizer_common/sanitizer_common_interceptors_memintrinsics.inc b/compiler-rt/lib/sanitizer_common/sanitizer_common_interceptors_memintrinsics.inc new file mode 100644 index 0000000000000..e6b967c48b2e1 --- /dev/null +++ b/compiler-rt/lib/sanitizer_common/sanitizer_common_interceptors_memintrinsics.inc @@ -0,0 +1,236 @@ +//===-- sanitizer_common_interceptors_memintrinsics.inc ---------*- C++ -*-===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// +// +// Memintrinsic function interceptors for tools like AddressSanitizer, +// ThreadSanitizer, MemorySanitizer, etc. +// +// This file should be included into the tool's memintrinsic interceptor file, +// which has to define its own macros: +// COMMON_INTERCEPTOR_ENTER +// COMMON_INTERCEPTOR_READ_RANGE +// COMMON_INTERCEPTOR_WRITE_RANGE +// COMMON_INTERCEPTOR_MEMSET_IMPL +// COMMON_INTERCEPTOR_MEMMOVE_IMPL +// COMMON_INTERCEPTOR_MEMCPY_IMPL +// COMMON_INTERCEPTOR_NOTHING_IS_INITIALIZED +//===----------------------------------------------------------------------===// + +#include "interception/interception.h" +#include "sanitizer_platform_interceptors.h" + +// Platform-specific options. +#if SANITIZER_APPLE +#define PLATFORM_HAS_DIFFERENT_MEMCPY_AND_MEMMOVE 0 +#elif SANITIZER_WINDOWS64 +#define PLATFORM_HAS_DIFFERENT_MEMCPY_AND_MEMMOVE 0 +#else +#define PLATFORM_HAS_DIFFERENT_MEMCPY_AND_MEMMOVE 1 +#endif // SANITIZER_APPLE + +#ifndef COMMON_INTERCEPTOR_MEMSET_IMPL +#define COMMON_INTERCEPTOR_MEMSET_IMPL(ctx, dst, v, size) \ + { \ + if (COMMON_INTERCEPTOR_NOTHING_IS_INITIALIZED) \ + return internal_memset(dst, v, size); \ + COMMON_INTERCEPTOR_ENTER(ctx, memset, dst, v, size); \ + if (common_flags()->intercept_intrin) \ + COMMON_INTERCEPTOR_WRITE_RANGE(ctx, dst, size); \ + return REAL(memset)(dst, v, size); \ + } +#endif + +#ifndef COMMON_INTERCEPTOR_MEMMOVE_IMPL +#define COMMON_INTERCEPTOR_MEMMOVE_IMPL(ctx, dst, src, size) \ + { \ + if (COMMON_INTERCEPTOR_NOTHING_IS_INITIALIZED) \ + return internal_memmove(dst, src, size); \ + COMMON_INTERCEPTOR_ENTER(ctx, memmove, dst, src, size); \ + if (common_flags()->intercept_intrin) { \ + COMMON_INTERCEPTOR_WRITE_RANGE(ctx, dst, size); \ + COMMON_INTERCEPTOR_READ_RANGE(ctx, src, size); \ + } \ + return REAL(memmove)(dst, src, size); \ + } +#endif + +#ifndef COMMON_INTERCEPTOR_MEMCPY_IMPL +#define COMMON_INTERCEPTOR_MEMCPY_IMPL(ctx, dst, src, size) \ + { \ + if (COMMON_INTERCEPTOR_NOTHING_IS_INITIALIZED) { \ + return internal_memmove(dst, src, size); \ + } \ + COMMON_INTERCEPTOR_ENTER(ctx, memcpy, dst, src, size); \ + if (common_flags()->intercept_intrin) { \ + COMMON_INTERCEPTOR_WRITE_RANGE(ctx, dst, size); \ + COMMON_INTERCEPTOR_READ_RANGE(ctx, src, size); \ + } \ + return REAL(memcpy)(dst, src, size); \ + } +#endif + +#if SANITIZER_INTERCEPT_MEMSET +INTERCEPTOR(void *, memset, void *dst, int v, uptr size) { + void *ctx; + COMMON_INTERCEPTOR_MEMSET_IMPL(ctx, dst, v, size); +} + +#define INIT_MEMSET COMMON_INTERCEPT_FUNCTION(memset) +#else +#define INIT_MEMSET +#endif + +#if SANITIZER_INTERCEPT_MEMMOVE +INTERCEPTOR(void *, memmove, void *dst, const void *src, uptr size) { + void *ctx; + COMMON_INTERCEPTOR_MEMMOVE_IMPL(ctx, dst, src, size); +} + +#define INIT_MEMMOVE COMMON_INTERCEPT_FUNCTION(memmove) +#else +#define INIT_MEMMOVE +#endif + +#if SANITIZER_INTERCEPT_MEMCPY +INTERCEPTOR(void *, memcpy, void *dst, const void *src, uptr size) { + // On OS X, calling internal_memcpy here will cause memory corruptions, + // because memcpy and memmove are actually aliases of the same + // implementation. We need to use internal_memmove here. + // N.B.: If we switch this to internal_ we'll have to use internal_memmove + // due to memcpy being an alias of memmove on OS X. + void *ctx; +#if PLATFORM_HAS_DIFFERENT_MEMCPY_AND_MEMMOVE + COMMON_INTERCEPTOR_MEMCPY_IMPL(ctx, dst, src, size); +#else + COMMON_INTERCEPTOR_MEMMOVE_IMPL(ctx, dst, src, size); +#endif +} + +#define INIT_MEMCPY \ + do { \ + if (PLATFORM_HAS_DIFFERENT_MEMCPY_AND_MEMMOVE) { \ + COMMON_INTERCEPT_FUNCTION(memcpy); \ + } else { \ + ASSIGN_REAL(memcpy, memmove); \ + } \ + CHECK(REAL(memcpy)); \ + } while (false) + +#else +#define INIT_MEMCPY +#endif + +#if SANITIZER_INTERCEPT_AEABI_MEM +INTERCEPTOR(void *, __aeabi_memmove, void *to, const void *from, uptr size) { + void *ctx; + COMMON_INTERCEPTOR_MEMMOVE_IMPL(ctx, to, from, size); +} + +INTERCEPTOR(void *, __aeabi_memmove4, void *to, const void *from, uptr size) { + void *ctx; + COMMON_INTERCEPTOR_MEMMOVE_IMPL(ctx, to, from, size); +} + +INTERCEPTOR(void *, __aeabi_memmove8, void *to, const void *from, uptr size) { + void *ctx; + COMMON_INTERCEPTOR_MEMMOVE_IMPL(ctx, to, from, size); +} + +INTERCEPTOR(void *, __aeabi_memcpy, void *to, const void *from, uptr size) { + void *ctx; + COMMON_INTERCEPTOR_MEMCPY_IMPL(ctx, to, from, size); +} + +INTERCEPTOR(void *, __aeabi_memcpy4, void *to, const void *from, uptr size) { + void *ctx; + COMMON_INTERCEPTOR_MEMCPY_IMPL(ctx, to, from, size); +} + +INTERCEPTOR(void *, __aeabi_memcpy8, void *to, const void *from, uptr size) { + void *ctx; + COMMON_INTERCEPTOR_MEMCPY_IMPL(ctx, to, from, size); +} + +// Note the argument order. +INTERCEPTOR(void *, __aeabi_memset, void *block, uptr size, int c) { + void *ctx; + COMMON_INTERCEPTOR_MEMSET_IMPL(ctx, block, c, size); +} + +INTERCEPTOR(void *, __aeabi_memset4, void *block, uptr size, int c) { + void *ctx; + COMMON_INTERCEPTOR_MEMSET_IMPL(ctx, block, c, size); +} + +INTERCEPTOR(void *, __aeabi_memset8, void *block, uptr size, int c) { + void *ctx; + COMMON_INTERCEPTOR_MEMSET_IMPL(ctx, block, c, size); +} + +INTERCEPTOR(void *, __aeabi_memclr, void *block, uptr size) { + void *ctx; + COMMON_INTERCEPTOR_MEMSET_IMPL(ctx, block, 0, size); +} + +INTERCEPTOR(void *, __aeabi_memclr4, void *block, uptr size) { + void *ctx; + COMMON_INTERCEPTOR_MEMSET_IMPL(ctx, block, 0, size); +} + +INTERCEPTOR(void *, __aeabi_memclr8, void *block, uptr size) { + void *ctx; + COMMON_INTERCEPTOR_MEMSET_IMPL(ctx, block, 0, size); +} + +#define INIT_AEABI_MEM \ + COMMON_INTERCEPT_FUNCTION(__aeabi_memmove); \ + COMMON_INTERCEPT_FUNCTION(__aeabi_memmove4); \ + COMMON_INTERCEPT_FUNCTION(__aeabi_memmove8); \ + COMMON_INTERCEPT_FUNCTION(__aeabi_memcpy); \ + COMMON_INTERCEPT_FUNCTION(__aeabi_memcpy4); \ + COMMON_INTERCEPT_FUNCTION(__aeabi_memcpy8); \ + COMMON_INTERCEPT_FUNCTION(__aeabi_memset); \ + COMMON_INTERCEPT_FUNCTION(__aeabi_memset4); \ + COMMON_INTERCEPT_FUNCTION(__aeabi_memset8); \ + COMMON_INTERCEPT_FUNCTION(__aeabi_memclr); \ + COMMON_INTERCEPT_FUNCTION(__aeabi_memclr4); \ + COMMON_INTERCEPT_FUNCTION(__aeabi_memclr8); +#else +#define INIT_AEABI_MEM +#endif // SANITIZER_INTERCEPT_AEABI_MEM + +#if SANITIZER_INTERCEPT___BZERO +INTERCEPTOR(void *, __bzero, void *block, uptr size) { + void *ctx; + COMMON_INTERCEPTOR_MEMSET_IMPL(ctx, block, 0, size); +} +#define INIT___BZERO COMMON_INTERCEPT_FUNCTION(__bzero); +#else +#define INIT___BZERO +#endif // SANITIZER_INTERCEPT___BZERO + +#if SANITIZER_INTERCEPT_BZERO +INTERCEPTOR(void *, bzero, void *block, uptr size) { + void *ctx; + COMMON_INTERCEPTOR_MEMSET_IMPL(ctx, block, 0, size); +} +#define INIT_BZERO COMMON_INTERCEPT_FUNCTION(bzero); +#else +#define INIT_BZERO +#endif // SANITIZER_INTERCEPT_BZERO + +namespace __sanitizer { +// This does not need to be called if InitializeCommonInterceptors() is called. +void InitializeMemintrinsicInterceptors() { + INIT_MEMSET; + INIT_MEMMOVE; + INIT_MEMCPY; + INIT_AEABI_MEM; + INIT___BZERO; + INIT_BZERO; +} +} // namespace __sanitizer diff --git a/compiler-rt/lib/sanitizer_common/sanitizer_common_range.cpp b/compiler-rt/lib/sanitizer_common/sanitizer_common_range.cpp new file mode 100644 index 0000000000000..fcdb928a33b4c --- /dev/null +++ b/compiler-rt/lib/sanitizer_common/sanitizer_common_range.cpp @@ -0,0 +1,60 @@ +//===-- sanitizer_common_range.cpp ----------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#include "sanitizer_common_range.h" + +namespace __sanitizer { + +void Intersect(ArrayRef a, ArrayRef b, + InternalMmapVectorNoCtor &output) { + output.clear(); + + struct Event { + uptr val; + s8 diff1; + s8 diff2; + }; + + InternalMmapVector events; + for (const Range &r : a) { + CHECK_LE(r.begin, r.end); + events.push_back({r.begin, 1, 0}); + events.push_back({r.end, -1, 0}); + } + + for (const Range &r : b) { + CHECK_LE(r.begin, r.end); + events.push_back({r.begin, 0, 1}); + events.push_back({r.end, 0, -1}); + } + + Sort(events.data(), events.size(), + [](const Event &lh, const Event &rh) { return lh.val < rh.val; }); + + uptr start = 0; + sptr state1 = 0; + sptr state2 = 0; + for (const auto &e : events) { + if (e.val != start) { + DCHECK_GE(state1, 0); + DCHECK_GE(state2, 0); + if (state1 && state2) { + if (!output.empty() && start == output.back().end) + output.back().end = e.val; + else + output.push_back({start, e.val}); + } + start = e.val; + } + + state1 += e.diff1; + state2 += e.diff2; + } +} + +} // namespace __sanitizer diff --git a/compiler-rt/lib/sanitizer_common/sanitizer_common_range.h b/compiler-rt/lib/sanitizer_common/sanitizer_common_range.h new file mode 100644 index 0000000000000..76e3d04b2cebb --- /dev/null +++ b/compiler-rt/lib/sanitizer_common/sanitizer_common_range.h @@ -0,0 +1,39 @@ +//===-- sanitizer_common_range.h --------------------------------*- C++ -*-===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// +// +// Contais Range and related utilities. +// +//===----------------------------------------------------------------------===// + +#ifndef SANITIZER_COMMON_REGION_H +#define SANITIZER_COMMON_REGION_H + +#include "sanitizer_common.h" + +namespace __sanitizer { + +struct Range { + uptr begin; + uptr end; +}; + +inline bool operator==(const Range &lhs, const Range &rhs) { + return lhs.begin == rhs.begin && lhs.end == rhs.end; +} + +inline bool operator!=(const Range &lhs, const Range &rhs) { + return !(lhs == rhs); +} + +// Calculates intersection of two sets of regions in O(N log N) time. +void Intersect(ArrayRef a, ArrayRef b, + InternalMmapVectorNoCtor &output); + +} // namespace __sanitizer + +#endif // SANITIZER_COMMON_REGION_H diff --git a/compiler-rt/lib/sanitizer_common/sanitizer_internal_defs.h b/compiler-rt/lib/sanitizer_common/sanitizer_internal_defs.h index ee1b3156c779e..95f4760cffd74 100644 --- a/compiler-rt/lib/sanitizer_common/sanitizer_internal_defs.h +++ b/compiler-rt/lib/sanitizer_common/sanitizer_internal_defs.h @@ -215,6 +215,7 @@ typedef u64 tid_t; # define UNLIKELY(x) (x) # define PREFETCH(x) /* _mm_prefetch(x, _MM_HINT_NTA) */ (void)0 # define WARN_UNUSED_RESULT +# define UNINITIALIZED #else // _MSC_VER # define ALWAYS_INLINE inline __attribute__((always_inline)) # define ALIAS(x) __attribute__((alias(SANITIZER_STRINGIFY(x)))) @@ -234,6 +235,11 @@ typedef u64 tid_t; # define PREFETCH(x) __builtin_prefetch(x) # endif # define WARN_UNUSED_RESULT __attribute__((warn_unused_result)) +# if __has_attribute(uninitialized) +# define UNINITIALIZED __attribute__((uninitialized)) +# else // __has_attribute(uninitialized) +# define UNINITIALIZED +# endif // __has_attribute(uninitialized) #endif // _MSC_VER #if !defined(_MSC_VER) || defined(__clang__) diff --git a/compiler-rt/lib/sanitizer_common/tests/CMakeLists.txt b/compiler-rt/lib/sanitizer_common/tests/CMakeLists.txt index 40aa8e703b6c7..4924a9e32d774 100644 --- a/compiler-rt/lib/sanitizer_common/tests/CMakeLists.txt +++ b/compiler-rt/lib/sanitizer_common/tests/CMakeLists.txt @@ -16,6 +16,7 @@ set(SANITIZER_UNITTESTS sanitizer_bitvector_test.cpp sanitizer_bvgraph_test.cpp sanitizer_chained_origin_depot_test.cpp + sanitizer_common_range_test.cpp sanitizer_common_test.cpp sanitizer_deadlock_detector_test.cpp sanitizer_dense_map_test.cpp diff --git a/compiler-rt/lib/sanitizer_common/tests/sanitizer_common_range_test.cpp b/compiler-rt/lib/sanitizer_common/tests/sanitizer_common_range_test.cpp new file mode 100644 index 0000000000000..2a2e1de2a6dd5 --- /dev/null +++ b/compiler-rt/lib/sanitizer_common/tests/sanitizer_common_range_test.cpp @@ -0,0 +1,66 @@ +//===-- sanitizer_common_region_test.cpp ----------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// +// +// This file is a part of ThreadSanitizer/AddressSanitizer runtime. +// +//===----------------------------------------------------------------------===// +#include "sanitizer_common/sanitizer_common_range.h" + +#include + +#include "gtest/gtest.h" +#include "sanitizer_common/sanitizer_common.h" + +namespace __sanitizer { + +class SanitizerCommon + : public testing::TestWithParam, std::vector, std::vector>> {}; + +TEST_P(SanitizerCommon, Intersect) { + { + InternalMmapVector output; + Intersect(std::get<0>(GetParam()), std::get<1>(GetParam()), output); + EXPECT_EQ(std::get<2>(GetParam()), + std::vector(output.begin(), output.end())); + } + { + InternalMmapVector output; + Intersect(std::get<1>(GetParam()), std::get<0>(GetParam()), output); + EXPECT_EQ(std::get<2>(GetParam()), + std::vector(output.begin(), output.end())); + } +} + +static void PrintTo(const Range &r, std::ostream *os) { + *os << "[" << r.begin << ", " << r.end << ")"; +} + +static const std::tuple, std::vector, + std::vector> + kTests[] = { + {{}, {}, {}}, + {{{100, 1000}}, {{5000, 10000}}, {}}, + {{{100, 1000}, {200, 2000}}, {{5000, 10000}, {6000, 11000}}, {}}, + {{{100, 1000}}, {{100, 1000}}, {{100, 1000}}}, + {{{100, 1000}}, {{50, 150}}, {{100, 150}}}, + {{{100, 1000}}, {{150, 250}}, {{150, 250}}}, + {{{100, 1000}, {100, 1000}}, {{100, 1000}}, {{100, 1000}}}, + {{{100, 1000}}, {{500, 1500}}, {{500, 1000}}}, + {{{100, 200}}, {{200, 300}, {1, 1000}}, {{100, 200}}}, + {{{100, 200}, {200, 300}}, {{100, 300}}, {{100, 300}}}, + {{{100, 200}, {200, 300}, {300, 400}}, {{150, 350}}, {{150, 350}}}, + {{{100, 200}, {300, 400}, {500, 600}}, + {{0, 1000}}, + {{100, 200}, {300, 400}, {500, 600}}}, +}; + +INSTANTIATE_TEST_SUITE_P(SanitizerCommonEmpty, SanitizerCommon, + testing::ValuesIn(kTests)); + +} // namespace __sanitizer diff --git a/compiler-rt/lib/scudo/standalone/allocator_config.h b/compiler-rt/lib/scudo/standalone/allocator_config.h index d06f6dfe4e0a9..df972d1ea5d22 100644 --- a/compiler-rt/lib/scudo/standalone/allocator_config.h +++ b/compiler-rt/lib/scudo/standalone/allocator_config.h @@ -19,6 +19,22 @@ #include "tsd_exclusive.h" #include "tsd_shared.h" +// To import a custom configuration, define `SCUDO_USE_CUSTOM_CONFIG` and +// aliasing the `Config` like: +// +// namespace scudo { +// // The instance of Scudo will be initiated with `Config`. +// typedef CustomConfig Config; +// // Aliasing as default configuration to run the tests with this config. +// typedef CustomConfig DefaultConfig; +// } // namespace scudo +// +// Put them in the header `custom_scudo_config.h` then you will be using the +// custom configuration and able to run all the tests as well. +#ifdef SCUDO_USE_CUSTOM_CONFIG +#include "custom_scudo_config.h" +#endif + namespace scudo { // The combined allocator uses a structure as a template argument that @@ -26,191 +42,265 @@ namespace scudo { // allocator. // // struct ExampleConfig { -// // SizeClassMap to use with the Primary. -// using SizeClassMap = DefaultSizeClassMap; // // Indicates possible support for Memory Tagging. // static const bool MaySupportMemoryTagging = false; -// // Defines the Primary allocator to use. -// typedef SizeClassAllocator64 Primary; -// // Log2 of the size of a size class region, as used by the Primary. -// static const uptr PrimaryRegionSizeLog = 30U; -// // Log2 of the size of block group, as used by the Primary. Each group -// // contains a range of memory addresses, blocks in the range will belong to -// // the same group. In general, single region may have 1 or 2MB group size. -// // Multiple regions will have the group size equal to the region size -// // because the region size is usually smaller than 1 MB. -// // Smaller value gives fine-grained control of memory usage but the trade -// // off is that it may take longer time of deallocation. -// static const uptr PrimaryGroupSizeLog = 20U; -// // Defines the type and scale of a compact pointer. A compact pointer can -// // be understood as the offset of a pointer within the region it belongs -// // to, in increments of a power-of-2 scale. -// // eg: Ptr = Base + (CompactPtr << Scale). -// typedef u32 PrimaryCompactPtrT; -// static const uptr PrimaryCompactPtrScale = SCUDO_MIN_ALIGNMENT_LOG; -// // Indicates support for offsetting the start of a region by -// // a random number of pages. Only used with primary64. -// static const bool PrimaryEnableRandomOffset = true; -// // Call map for user memory with at least this size. Only used with -// // primary64. -// static const uptr PrimaryMapSizeIncrement = 1UL << 18; -// // Defines the minimal & maximal release interval that can be set. -// static const s32 PrimaryMinReleaseToOsIntervalMs = INT32_MIN; -// static const s32 PrimaryMaxReleaseToOsIntervalMs = INT32_MAX; -// // Defines the type of cache used by the Secondary. Some additional -// // configuration entries can be necessary depending on the Cache. -// typedef MapAllocatorNoCache SecondaryCache; +// // // Thread-Specific Data Registry used, shared or exclusive. // template using TSDRegistryT = TSDRegistrySharedT; +// +// struct Primary { +// // SizeClassMap to use with the Primary. +// using SizeClassMap = DefaultSizeClassMap; +// +// // Log2 of the size of a size class region, as used by the Primary. +// static const uptr RegionSizeLog = 30U; +// +// // Log2 of the size of block group, as used by the Primary. Each group +// // contains a range of memory addresses, blocks in the range will belong +// // to the same group. In general, single region may have 1 or 2MB group +// // size. Multiple regions will have the group size equal to the region +// // size because the region size is usually smaller than 1 MB. +// // Smaller value gives fine-grained control of memory usage but the +// // trade-off is that it may take longer time of deallocation. +// static const uptr GroupSizeLog = 20U; +// +// // Defines the type and scale of a compact pointer. A compact pointer can +// // be understood as the offset of a pointer within the region it belongs +// // to, in increments of a power-of-2 scale. +// // eg: Ptr = Base + (CompactPtr << Scale). +// typedef u32 CompactPtrT; +// static const uptr CompactPtrScale = SCUDO_MIN_ALIGNMENT_LOG; +// +// // Indicates support for offsetting the start of a region by +// // a random number of pages. Only used with primary64. +// static const bool EnableRandomOffset = true; +// +// // Call map for user memory with at least this size. Only used with +// // primary64. +// static const uptr MapSizeIncrement = 1UL << 18; +// +// // Defines the minimal & maximal release interval that can be set. +// static const s32 MinReleaseToOsIntervalMs = INT32_MIN; +// static const s32 MaxReleaseToOsIntervalMs = INT32_MAX; +// }; +// // Defines the type of Primary allocator to use. +// template using PrimaryT = SizeClassAllocator64; +// +// // Defines the type of cache used by the Secondary. Some additional +// // configuration entries can be necessary depending on the Cache. +// struct Secondary { +// struct Cache { +// static const u32 EntriesArraySize = 32U; +// static const u32 QuarantineSize = 0U; +// static const u32 DefaultMaxEntriesCount = 32U; +// static const uptr DefaultMaxEntrySize = 1UL << 19; +// static const s32 MinReleaseToOsIntervalMs = INT32_MIN; +// static const s32 MaxReleaseToOsIntervalMs = INT32_MAX; +// }; +// // Defines the type of Secondary Cache to use. +// template using CacheT = MapAllocatorCache; +// }; +// // Defines the type of Secondary allocator to use. +// template using SecondaryT = MapAllocator; // }; -// Default configurations for various platforms. +#ifndef SCUDO_USE_CUSTOM_CONFIG +// Default configurations for various platforms. Note this is only enabled when +// there's no custom configuration in the build system. struct DefaultConfig { - using SizeClassMap = DefaultSizeClassMap; static const bool MaySupportMemoryTagging = true; + template using TSDRegistryT = TSDRegistryExT; // Exclusive + struct Primary { + using SizeClassMap = DefaultSizeClassMap; +#if SCUDO_CAN_USE_PRIMARY64 + static const uptr RegionSizeLog = 32U; + static const uptr GroupSizeLog = 21U; + typedef uptr CompactPtrT; + static const uptr CompactPtrScale = 0; + static const bool EnableRandomOffset = true; + static const uptr MapSizeIncrement = 1UL << 18; +#else + static const uptr RegionSizeLog = 19U; + static const uptr GroupSizeLog = 19U; + typedef uptr CompactPtrT; +#endif + static const s32 MinReleaseToOsIntervalMs = INT32_MIN; + static const s32 MaxReleaseToOsIntervalMs = INT32_MAX; + }; #if SCUDO_CAN_USE_PRIMARY64 - typedef SizeClassAllocator64 Primary; - static const uptr PrimaryRegionSizeLog = 32U; - static const uptr PrimaryGroupSizeLog = 21U; - typedef uptr PrimaryCompactPtrT; - static const uptr PrimaryCompactPtrScale = 0; - static const bool PrimaryEnableRandomOffset = true; - static const uptr PrimaryMapSizeIncrement = 1UL << 18; + template using PrimaryT = SizeClassAllocator64; #else - typedef SizeClassAllocator32 Primary; - static const uptr PrimaryRegionSizeLog = 19U; - static const uptr PrimaryGroupSizeLog = 19U; - typedef uptr PrimaryCompactPtrT; + template using PrimaryT = SizeClassAllocator32; #endif - static const s32 PrimaryMinReleaseToOsIntervalMs = INT32_MIN; - static const s32 PrimaryMaxReleaseToOsIntervalMs = INT32_MAX; - typedef MapAllocatorCache SecondaryCache; - static const u32 SecondaryCacheEntriesArraySize = 32U; - static const u32 SecondaryCacheQuarantineSize = 0U; - static const u32 SecondaryCacheDefaultMaxEntriesCount = 32U; - static const uptr SecondaryCacheDefaultMaxEntrySize = 1UL << 19; - static const s32 SecondaryCacheMinReleaseToOsIntervalMs = INT32_MIN; - static const s32 SecondaryCacheMaxReleaseToOsIntervalMs = INT32_MAX; + struct Secondary { + struct Cache { + static const u32 EntriesArraySize = 32U; + static const u32 QuarantineSize = 0U; + static const u32 DefaultMaxEntriesCount = 32U; + static const uptr DefaultMaxEntrySize = 1UL << 19; + static const s32 MinReleaseToOsIntervalMs = INT32_MIN; + static const s32 MaxReleaseToOsIntervalMs = INT32_MAX; + }; + template using CacheT = MapAllocatorCache; + }; - template using TSDRegistryT = TSDRegistryExT; // Exclusive + template using SecondaryT = MapAllocator; }; + +#endif // SCUDO_USE_CUSTOM_CONFIG + struct AndroidConfig { - using SizeClassMap = AndroidSizeClassMap; static const bool MaySupportMemoryTagging = true; + template + using TSDRegistryT = TSDRegistrySharedT; // Shared, max 8 TSDs. + struct Primary { + using SizeClassMap = AndroidSizeClassMap; +#if SCUDO_CAN_USE_PRIMARY64 + static const uptr RegionSizeLog = 28U; + typedef u32 CompactPtrT; + static const uptr CompactPtrScale = SCUDO_MIN_ALIGNMENT_LOG; + static const uptr GroupSizeLog = 20U; + static const bool EnableRandomOffset = true; + static const uptr MapSizeIncrement = 1UL << 18; +#else + static const uptr RegionSizeLog = 18U; + static const uptr GroupSizeLog = 18U; + typedef uptr CompactPtrT; +#endif + static const s32 MinReleaseToOsIntervalMs = 1000; + static const s32 MaxReleaseToOsIntervalMs = 1000; + }; #if SCUDO_CAN_USE_PRIMARY64 - typedef SizeClassAllocator64 Primary; - static const uptr PrimaryRegionSizeLog = 28U; - typedef u32 PrimaryCompactPtrT; - static const uptr PrimaryCompactPtrScale = SCUDO_MIN_ALIGNMENT_LOG; - static const uptr PrimaryGroupSizeLog = 20U; - static const bool PrimaryEnableRandomOffset = true; - static const uptr PrimaryMapSizeIncrement = 1UL << 18; + template using PrimaryT = SizeClassAllocator64; #else - typedef SizeClassAllocator32 Primary; - static const uptr PrimaryRegionSizeLog = 18U; - static const uptr PrimaryGroupSizeLog = 18U; - typedef uptr PrimaryCompactPtrT; + template using PrimaryT = SizeClassAllocator32; #endif - static const s32 PrimaryMinReleaseToOsIntervalMs = 1000; - static const s32 PrimaryMaxReleaseToOsIntervalMs = 1000; - typedef MapAllocatorCache SecondaryCache; - static const u32 SecondaryCacheEntriesArraySize = 256U; - static const u32 SecondaryCacheQuarantineSize = 32U; - static const u32 SecondaryCacheDefaultMaxEntriesCount = 32U; - static const uptr SecondaryCacheDefaultMaxEntrySize = 2UL << 20; - static const s32 SecondaryCacheMinReleaseToOsIntervalMs = 0; - static const s32 SecondaryCacheMaxReleaseToOsIntervalMs = 1000; + struct Secondary { + struct Cache { + static const u32 EntriesArraySize = 256U; + static const u32 QuarantineSize = 32U; + static const u32 DefaultMaxEntriesCount = 32U; + static const uptr DefaultMaxEntrySize = 2UL << 20; + static const s32 MinReleaseToOsIntervalMs = 0; + static const s32 MaxReleaseToOsIntervalMs = 1000; + }; + template using CacheT = MapAllocatorCache; + }; - template - using TSDRegistryT = TSDRegistrySharedT; // Shared, max 8 TSDs. + template using SecondaryT = MapAllocator; }; struct AndroidSvelteConfig { - using SizeClassMap = SvelteSizeClassMap; static const bool MaySupportMemoryTagging = false; + template + using TSDRegistryT = TSDRegistrySharedT; // Shared, max 2 TSDs. + struct Primary { + using SizeClassMap = SvelteSizeClassMap; #if SCUDO_CAN_USE_PRIMARY64 - typedef SizeClassAllocator64 Primary; - static const uptr PrimaryRegionSizeLog = 27U; - typedef u32 PrimaryCompactPtrT; - static const uptr PrimaryCompactPtrScale = SCUDO_MIN_ALIGNMENT_LOG; - static const uptr PrimaryGroupSizeLog = 18U; - static const bool PrimaryEnableRandomOffset = true; - static const uptr PrimaryMapSizeIncrement = 1UL << 18; + static const uptr RegionSizeLog = 27U; + typedef u32 CompactPtrT; + static const uptr CompactPtrScale = SCUDO_MIN_ALIGNMENT_LOG; + static const uptr GroupSizeLog = 18U; + static const bool EnableRandomOffset = true; + static const uptr MapSizeIncrement = 1UL << 18; #else - typedef SizeClassAllocator32 Primary; - static const uptr PrimaryRegionSizeLog = 16U; - static const uptr PrimaryGroupSizeLog = 16U; - typedef uptr PrimaryCompactPtrT; + static const uptr RegionSizeLog = 16U; + static const uptr GroupSizeLog = 16U; + typedef uptr CompactPtrT; #endif - static const s32 PrimaryMinReleaseToOsIntervalMs = 1000; - static const s32 PrimaryMaxReleaseToOsIntervalMs = 1000; + static const s32 MinReleaseToOsIntervalMs = 1000; + static const s32 MaxReleaseToOsIntervalMs = 1000; + }; - typedef MapAllocatorCache SecondaryCache; - static const u32 SecondaryCacheEntriesArraySize = 16U; - static const u32 SecondaryCacheQuarantineSize = 32U; - static const u32 SecondaryCacheDefaultMaxEntriesCount = 4U; - static const uptr SecondaryCacheDefaultMaxEntrySize = 1UL << 18; - static const s32 SecondaryCacheMinReleaseToOsIntervalMs = 0; - static const s32 SecondaryCacheMaxReleaseToOsIntervalMs = 0; +#if SCUDO_CAN_USE_PRIMARY64 + template using PrimaryT = SizeClassAllocator64; +#else + template using PrimaryT = SizeClassAllocator32; +#endif - template - using TSDRegistryT = TSDRegistrySharedT; // Shared, max 2 TSDs. + struct Secondary { + struct Cache { + static const u32 EntriesArraySize = 16U; + static const u32 QuarantineSize = 32U; + static const u32 DefaultMaxEntriesCount = 4U; + static const uptr DefaultMaxEntrySize = 1UL << 18; + static const s32 MinReleaseToOsIntervalMs = 0; + static const s32 MaxReleaseToOsIntervalMs = 0; + }; + template using CacheT = MapAllocatorCache; + }; + + template using SecondaryT = MapAllocator; }; #if SCUDO_CAN_USE_PRIMARY64 struct FuchsiaConfig { - using SizeClassMap = FuchsiaSizeClassMap; static const bool MaySupportMemoryTagging = false; + template + using TSDRegistryT = TSDRegistrySharedT; // Shared, max 8 TSDs. - typedef SizeClassAllocator64 Primary; -// Support 39-bit VMA for riscv-64 + struct Primary { + using SizeClassMap = FuchsiaSizeClassMap; #if SCUDO_RISCV64 - static const uptr PrimaryRegionSizeLog = 28U; - static const uptr PrimaryGroupSizeLog = 19U; + // Support 39-bit VMA for riscv-64 + static const uptr RegionSizeLog = 28U; + static const uptr GroupSizeLog = 19U; #else - static const uptr PrimaryRegionSizeLog = 30U; - static const uptr PrimaryGroupSizeLog = 21U; + static const uptr RegionSizeLog = 30U; + static const uptr GroupSizeLog = 21U; #endif - typedef u32 PrimaryCompactPtrT; - static const bool PrimaryEnableRandomOffset = true; - static const uptr PrimaryMapSizeIncrement = 1UL << 18; - static const uptr PrimaryCompactPtrScale = SCUDO_MIN_ALIGNMENT_LOG; - static const s32 PrimaryMinReleaseToOsIntervalMs = INT32_MIN; - static const s32 PrimaryMaxReleaseToOsIntervalMs = INT32_MAX; - - typedef MapAllocatorNoCache SecondaryCache; - template - using TSDRegistryT = TSDRegistrySharedT; // Shared, max 8 TSDs. + typedef u32 CompactPtrT; + static const bool EnableRandomOffset = true; + static const uptr MapSizeIncrement = 1UL << 18; + static const uptr CompactPtrScale = SCUDO_MIN_ALIGNMENT_LOG; + static const s32 MinReleaseToOsIntervalMs = INT32_MIN; + static const s32 MaxReleaseToOsIntervalMs = INT32_MAX; + }; + template using PrimaryT = SizeClassAllocator64; + + struct Secondary { + template using CacheT = MapAllocatorNoCache; + }; + template using SecondaryT = MapAllocator; }; struct TrustyConfig { - using SizeClassMap = TrustySizeClassMap; static const bool MaySupportMemoryTagging = false; - - typedef SizeClassAllocator64 Primary; - // Some apps have 1 page of heap total so small regions are necessary. - static const uptr PrimaryRegionSizeLog = 10U; - static const uptr PrimaryGroupSizeLog = 10U; - typedef u32 PrimaryCompactPtrT; - static const bool PrimaryEnableRandomOffset = false; - // Trusty is extremely memory-constrained so minimally round up map calls. - static const uptr PrimaryMapSizeIncrement = 1UL << 4; - static const uptr PrimaryCompactPtrScale = SCUDO_MIN_ALIGNMENT_LOG; - static const s32 PrimaryMinReleaseToOsIntervalMs = INT32_MIN; - static const s32 PrimaryMaxReleaseToOsIntervalMs = INT32_MAX; - - typedef MapAllocatorNoCache SecondaryCache; template using TSDRegistryT = TSDRegistrySharedT; // Shared, max 1 TSD. + + struct Primary { + static const bool MaySupportMemoryTagging = false; + using SizeClassMap = TrustySizeClassMap; + // Some apps have 1 page of heap total so small regions are necessary. + static const uptr RegionSizeLog = 10U; + static const uptr GroupSizeLog = 10U; + typedef u32 CompactPtrT; + static const bool EnableRandomOffset = false; + // Trusty is extremely memory-constrained so minimally round up map calls. + static const uptr MapSizeIncrement = 1UL << 4; + static const uptr CompactPtrScale = SCUDO_MIN_ALIGNMENT_LOG; + static const s32 MinReleaseToOsIntervalMs = INT32_MIN; + static const s32 MaxReleaseToOsIntervalMs = INT32_MAX; + }; + template using PrimaryT = SizeClassAllocator64; + + struct Secondary { + template using CacheT = MapAllocatorNoCache; + }; + + template using SecondaryT = MapAllocator; }; #endif +#ifndef SCUDO_USE_CUSTOM_CONFIG + #if SCUDO_ANDROID typedef AndroidConfig Config; #elif SCUDO_FUCHSIA @@ -221,6 +311,8 @@ typedef TrustyConfig Config; typedef DefaultConfig Config; #endif +#endif // SCUDO_USE_CUSTOM_CONFIG + } // namespace scudo #endif // SCUDO_ALLOCATOR_CONFIG_H_ diff --git a/compiler-rt/lib/scudo/standalone/combined.h b/compiler-rt/lib/scudo/standalone/combined.h index 52e2674400fb7..e3ec72d4ea1e1 100644 --- a/compiler-rt/lib/scudo/standalone/combined.h +++ b/compiler-rt/lib/scudo/standalone/combined.h @@ -43,13 +43,14 @@ extern "C" size_t android_unsafe_frame_pointer_chase(scudo::uptr *buf, namespace scudo { -template +template class Allocator { public: - using PrimaryT = typename Params::Primary; + using PrimaryT = typename Config::template PrimaryT; + using SecondaryT = typename Config::template SecondaryT; using CacheT = typename PrimaryT::CacheT; - typedef Allocator ThisT; - typedef typename Params::template TSDRegistryT TSDRegistryT; + typedef Allocator ThisT; + typedef typename Config::template TSDRegistryT TSDRegistryT; void callPostInitCallback() { pthread_once(&PostInitNonce, PostInitCallback); @@ -71,7 +72,7 @@ class Allocator { NewHeader.State = Chunk::State::Available; Chunk::compareExchangeHeader(Allocator.Cookie, Ptr, &NewHeader, &Header); - if (allocatorSupportsMemoryTagging()) + if (allocatorSupportsMemoryTagging()) Ptr = untagPointer(Ptr); void *BlockBegin = Allocator::getBlockBegin(Ptr, &NewHeader); Cache.deallocate(NewHeader.ClassId, BlockBegin); @@ -98,7 +99,7 @@ class Allocator { // Reset tag to 0 as this chunk may have been previously used for a tagged // user allocation. - if (UNLIKELY(useMemoryTagging(Allocator.Primary.Options.load()))) + if (UNLIKELY(useMemoryTagging(Allocator.Primary.Options.load()))) storeTags(reinterpret_cast(Ptr), reinterpret_cast(Ptr) + sizeof(QuarantineBatch)); @@ -162,7 +163,7 @@ class Allocator { Primary.Options.set(OptionBit::DeallocTypeMismatch); if (getFlags()->delete_size_mismatch) Primary.Options.set(OptionBit::DeleteSizeMismatch); - if (allocatorSupportsMemoryTagging() && + if (allocatorSupportsMemoryTagging() && systemSupportsMemoryTagging()) Primary.Options.set(OptionBit::UseMemoryTagging); Primary.Options.set(OptionBit::UseOddEvenTags); @@ -264,7 +265,7 @@ class Allocator { void drainCaches() { TSDRegistry.drainCaches(this); } ALWAYS_INLINE void *getHeaderTaggedPointer(void *Ptr) { - if (!allocatorSupportsMemoryTagging()) + if (!allocatorSupportsMemoryTagging()) return Ptr; auto UntaggedPtr = untagPointer(Ptr); if (UntaggedPtr != Ptr) @@ -276,7 +277,7 @@ class Allocator { } ALWAYS_INLINE uptr addHeaderTag(uptr Ptr) { - if (!allocatorSupportsMemoryTagging()) + if (!allocatorSupportsMemoryTagging()) return Ptr; return addFixedTag(Ptr, 2); } @@ -427,7 +428,7 @@ class Allocator { // // When memory tagging is enabled, zeroing the contents is done as part of // setting the tag. - if (UNLIKELY(useMemoryTagging(Options))) { + if (UNLIKELY(useMemoryTagging(Options))) { uptr PrevUserPtr; Chunk::UnpackedHeader Header; const uptr BlockSize = PrimaryT::getSizeByClassId(ClassId); @@ -509,7 +510,7 @@ class Allocator { } else { Block = addHeaderTag(Block); Ptr = addHeaderTag(Ptr); - if (UNLIKELY(useMemoryTagging(Options))) { + if (UNLIKELY(useMemoryTagging(Options))) { storeTags(reinterpret_cast(Block), reinterpret_cast(Ptr)); storeSecondaryAllocationStackMaybe(Options, Ptr, Size); } @@ -676,7 +677,7 @@ class Allocator { (reinterpret_cast(OldTaggedPtr) + NewSize)) & Chunk::SizeOrUnusedBytesMask; Chunk::compareExchangeHeader(Cookie, OldPtr, &NewHeader, &OldHeader); - if (UNLIKELY(useMemoryTagging(Options))) { + if (UNLIKELY(useMemoryTagging(Options))) { if (ClassId) { resizeTaggedChunk(reinterpret_cast(OldTaggedPtr) + OldSize, reinterpret_cast(OldTaggedPtr) + NewSize, @@ -772,7 +773,7 @@ class Allocator { Base = untagPointer(Base); const uptr From = Base; const uptr To = Base + Size; - bool MayHaveTaggedPrimary = allocatorSupportsMemoryTagging() && + bool MayHaveTaggedPrimary = allocatorSupportsMemoryTagging() && systemSupportsMemoryTagging(); auto Lambda = [this, From, To, MayHaveTaggedPrimary, Callback, Arg](uptr Block) { @@ -794,9 +795,9 @@ class Allocator { } if (Header.State == Chunk::State::Allocated) { uptr TaggedChunk = Chunk; - if (allocatorSupportsMemoryTagging()) + if (allocatorSupportsMemoryTagging()) TaggedChunk = untagPointer(TaggedChunk); - if (useMemoryTagging(Primary.Options.load())) + if (useMemoryTagging(Primary.Options.load())) TaggedChunk = loadTag(Chunk); Callback(TaggedChunk, getSize(reinterpret_cast(Chunk), &Header), Arg); @@ -895,7 +896,7 @@ class Allocator { } bool useMemoryTaggingTestOnly() const { - return useMemoryTagging(Primary.Options.load()); + return useMemoryTagging(Primary.Options.load()); } void disableMemoryTagging() { // If we haven't been initialized yet, we need to initialize now in order to @@ -905,7 +906,7 @@ class Allocator { // callback), which may cause mappings to be created with memory tagging // enabled. TSDRegistry.initOnceMaybe(this); - if (allocatorSupportsMemoryTagging()) { + if (allocatorSupportsMemoryTagging()) { Secondary.disableMemoryTagging(); Primary.Options.clear(OptionBit::UseMemoryTagging); } @@ -989,7 +990,7 @@ class Allocator { const char *Memory, const char *MemoryTags, uintptr_t MemoryAddr, size_t MemorySize) { *ErrorInfo = {}; - if (!allocatorSupportsMemoryTagging() || + if (!allocatorSupportsMemoryTagging() || MemoryAddr + MemorySize < MemoryAddr) return; @@ -1017,7 +1018,6 @@ class Allocator { } private: - using SecondaryT = MapAllocator; typedef typename PrimaryT::SizeClassMap SizeClassMap; static const uptr MinAlignmentLog = SCUDO_MIN_ALIGNMENT_LOG; @@ -1029,7 +1029,7 @@ class Allocator { static_assert(MinAlignment >= sizeof(Chunk::PackedHeader), "Minimal alignment must at least cover a chunk header."); - static_assert(!allocatorSupportsMemoryTagging() || + static_assert(!allocatorSupportsMemoryTagging() || MinAlignment >= archMemoryTagGranuleSize(), ""); @@ -1129,7 +1129,7 @@ class Allocator { const uptr SizeOrUnusedBytes = Header->SizeOrUnusedBytes; if (LIKELY(Header->ClassId)) return SizeOrUnusedBytes; - if (allocatorSupportsMemoryTagging()) + if (allocatorSupportsMemoryTagging()) Ptr = untagPointer(const_cast(Ptr)); return SecondaryT::getBlockEnd(getBlockBegin(Ptr, Header)) - reinterpret_cast(Ptr) - SizeOrUnusedBytes; @@ -1150,12 +1150,12 @@ class Allocator { NewHeader.State = Chunk::State::Available; else NewHeader.State = Chunk::State::Quarantined; - NewHeader.OriginOrWasZeroed = useMemoryTagging(Options) && + NewHeader.OriginOrWasZeroed = useMemoryTagging(Options) && NewHeader.ClassId && !TSDRegistry.getDisableMemInit(); Chunk::compareExchangeHeader(Cookie, Ptr, &NewHeader, Header); - if (UNLIKELY(useMemoryTagging(Options))) { + if (UNLIKELY(useMemoryTagging(Options))) { u8 PrevTag = extractTag(reinterpret_cast(TaggedPtr)); storeDeallocationStackMaybe(Options, Ptr, PrevTag, Size); if (NewHeader.ClassId) { @@ -1172,7 +1172,7 @@ class Allocator { } } if (BypassQuarantine) { - if (allocatorSupportsMemoryTagging()) + if (allocatorSupportsMemoryTagging()) Ptr = untagPointer(Ptr); void *BlockBegin = getBlockBegin(Ptr, &NewHeader); const uptr ClassId = NewHeader.ClassId; @@ -1183,7 +1183,7 @@ class Allocator { if (UnlockRequired) TSD->unlock(); } else { - if (UNLIKELY(useMemoryTagging(Options))) + if (UNLIKELY(useMemoryTagging(Options))) storeTags(reinterpret_cast(BlockBegin), reinterpret_cast(Ptr)); Secondary.deallocate(Options, BlockBegin); diff --git a/compiler-rt/lib/scudo/standalone/primary32.h b/compiler-rt/lib/scudo/standalone/primary32.h index b3d6e53dfca26..f67a0498ada87 100644 --- a/compiler-rt/lib/scudo/standalone/primary32.h +++ b/compiler-rt/lib/scudo/standalone/primary32.h @@ -42,13 +42,14 @@ namespace scudo { template class SizeClassAllocator32 { public: - typedef typename Config::PrimaryCompactPtrT CompactPtrT; - typedef typename Config::SizeClassMap SizeClassMap; - static const uptr GroupSizeLog = Config::PrimaryGroupSizeLog; + typedef typename Config::Primary::CompactPtrT CompactPtrT; + typedef typename Config::Primary::SizeClassMap SizeClassMap; + static const uptr GroupSizeLog = Config::Primary::GroupSizeLog; // The bytemap can only track UINT8_MAX - 1 classes. static_assert(SizeClassMap::LargestClassId <= (UINT8_MAX - 1), ""); // Regions should be large enough to hold the largest Block. - static_assert((1UL << Config::PrimaryRegionSizeLog) >= SizeClassMap::MaxSize, + static_assert((1UL << Config::Primary::RegionSizeLog) >= + SizeClassMap::MaxSize, ""); typedef SizeClassAllocator32 ThisT; typedef SizeClassAllocatorLocalCache CacheT; @@ -131,6 +132,16 @@ template class SizeClassAllocator32 { return CompactPtrGroupBase; } + ALWAYS_INLINE static bool isSmallBlock(uptr BlockSize) { + const uptr PageSize = getPageSizeCached(); + return BlockSize < PageSize / 16U; + } + + ALWAYS_INLINE static bool isLargeBlock(uptr BlockSize) { + const uptr PageSize = getPageSizeCached(); + return BlockSize > PageSize; + } + TransferBatch *popBatch(CacheT *C, uptr ClassId) { DCHECK_LT(ClassId, NumClasses); SizeClassInfo *Sci = getSizeClassInfo(ClassId); @@ -271,9 +282,9 @@ template class SizeClassAllocator32 { bool setOption(Option O, sptr Value) { if (O == Option::ReleaseInterval) { - const s32 Interval = Max( - Min(static_cast(Value), Config::PrimaryMaxReleaseToOsIntervalMs), - Config::PrimaryMinReleaseToOsIntervalMs); + const s32 Interval = Max(Min(static_cast(Value), + Config::Primary::MaxReleaseToOsIntervalMs), + Config::Primary::MinReleaseToOsIntervalMs); atomic_store_relaxed(&ReleaseToOsIntervalMs, Interval); return true; } @@ -305,9 +316,9 @@ template class SizeClassAllocator32 { private: static const uptr NumClasses = SizeClassMap::NumClasses; - static const uptr RegionSize = 1UL << Config::PrimaryRegionSizeLog; + static const uptr RegionSize = 1UL << Config::Primary::RegionSizeLog; static const uptr NumRegions = - SCUDO_MMAP_RANGE_SIZE >> Config::PrimaryRegionSizeLog; + SCUDO_MMAP_RANGE_SIZE >> Config::Primary::RegionSizeLog; static const u32 MaxNumBatches = SCUDO_ANDROID ? 4U : 8U; typedef FlatByteMap ByteMap; @@ -340,7 +351,7 @@ template class SizeClassAllocator32 { static_assert(sizeof(SizeClassInfo) % SCUDO_CACHE_LINE_SIZE == 0, ""); uptr computeRegionId(uptr Mem) { - const uptr Id = Mem >> Config::PrimaryRegionSizeLog; + const uptr Id = Mem >> Config::Primary::RegionSizeLog; CHECK_LT(Id, NumRegions); return Id; } @@ -369,7 +380,7 @@ template class SizeClassAllocator32 { unmap(reinterpret_cast(End), MapEnd - End); DCHECK_EQ(Region % RegionSize, 0U); - static_assert(Config::PrimaryRegionSizeLog == GroupSizeLog, + static_assert(Config::Primary::RegionSizeLog == GroupSizeLog, "Memory group should be the same size as Region"); return Region; @@ -740,12 +751,8 @@ template class SizeClassAllocator32 { if (UNLIKELY(BytesInFreeList == 0)) return 0; - bool MaySkip = false; - - if (BytesInFreeList <= Sci->ReleaseInfo.BytesInFreeListAtLastCheckpoint) { + if (BytesInFreeList <= Sci->ReleaseInfo.BytesInFreeListAtLastCheckpoint) Sci->ReleaseInfo.BytesInFreeListAtLastCheckpoint = BytesInFreeList; - MaySkip = true; - } // Always update `BytesInFreeListAtLastCheckpoint` with the smallest value // so that we won't underestimate the releasable pages. For example, the @@ -765,34 +772,38 @@ template class SizeClassAllocator32 { // (BytesInFreeListAtLastCheckpoint - BytesInFreeList). const uptr PushedBytesDelta = BytesInFreeList - Sci->ReleaseInfo.BytesInFreeListAtLastCheckpoint; - if (PushedBytesDelta < PageSize) - MaySkip = true; + if (PushedBytesDelta < PageSize && ReleaseType != ReleaseToOS::ForceAll) + return 0; const bool CheckDensity = - BlockSize < PageSize / 16U && ReleaseType != ReleaseToOS::ForceAll; + isSmallBlock(BlockSize) && ReleaseType != ReleaseToOS::ForceAll; // Releasing smaller blocks is expensive, so we want to make sure that a // significant amount of bytes are free, and that there has been a good // amount of batches pushed to the freelist before attempting to release. - if (CheckDensity) { - if (ReleaseType == ReleaseToOS::Normal && - PushedBytesDelta < Sci->AllocatedUser / 16U) { - MaySkip = true; - } - } - - if (MaySkip && ReleaseType != ReleaseToOS::ForceAll) - return 0; + if (CheckDensity && ReleaseType == ReleaseToOS::Normal) + if (PushedBytesDelta < Sci->AllocatedUser / 16U) + return 0; if (ReleaseType == ReleaseToOS::Normal) { const s32 IntervalMs = atomic_load_relaxed(&ReleaseToOsIntervalMs); if (IntervalMs < 0) return 0; - if (Sci->ReleaseInfo.LastReleaseAtNs + - static_cast(IntervalMs) * 1000000 > - getMonotonicTimeFast()) { - return 0; // Memory was returned recently. + + // The constant 8 here is selected from profiling some apps and the number + // of unreleased pages in the large size classes is around 16 pages or + // more. Choose half of it as a heuristic and which also avoids page + // release every time for every pushBlocks() attempt by large blocks. + const bool ByPassReleaseInterval = + isLargeBlock(BlockSize) && PushedBytesDelta > 8 * PageSize; + if (!ByPassReleaseInterval) { + if (Sci->ReleaseInfo.LastReleaseAtNs + + static_cast(IntervalMs) * 1000000 > + getMonotonicTimeFast()) { + // Memory was returned recently. + return 0; + } } - } + } // if (ReleaseType == ReleaseToOS::Normal) const uptr First = Sci->MinRegionIndex; const uptr Last = Sci->MaxRegionIndex; @@ -835,7 +846,7 @@ template class SizeClassAllocator32 { continue; } const uptr PushedBytesDelta = BytesInBG - BG.BytesInBGAtLastCheckpoint; - if (PushedBytesDelta < PageSize) + if (ReleaseType != ReleaseToOS::ForceAll && PushedBytesDelta < PageSize) continue; // Given the randomness property, we try to release the pages only if the diff --git a/compiler-rt/lib/scudo/standalone/primary64.h b/compiler-rt/lib/scudo/standalone/primary64.h index d3a1aea740033..209dfc90c65b7 100644 --- a/compiler-rt/lib/scudo/standalone/primary64.h +++ b/compiler-rt/lib/scudo/standalone/primary64.h @@ -45,11 +45,11 @@ namespace scudo { template class SizeClassAllocator64 { public: - typedef typename Config::PrimaryCompactPtrT CompactPtrT; - static const uptr CompactPtrScale = Config::PrimaryCompactPtrScale; - static const uptr GroupSizeLog = Config::PrimaryGroupSizeLog; + typedef typename Config::Primary::CompactPtrT CompactPtrT; + typedef typename Config::Primary::SizeClassMap SizeClassMap; + static const uptr CompactPtrScale = Config::Primary::CompactPtrScale; + static const uptr GroupSizeLog = Config::Primary::GroupSizeLog; static const uptr GroupScale = GroupSizeLog - CompactPtrScale; - typedef typename Config::SizeClassMap SizeClassMap; typedef SizeClassAllocator64 ThisT; typedef SizeClassAllocatorLocalCache CacheT; typedef typename CacheT::TransferBatch TransferBatch; @@ -119,10 +119,11 @@ template class SizeClassAllocator64 { RegionInfo *Region = getRegionInfo(I); // The actual start of a region is offset by a random number of pages // when PrimaryEnableRandomOffset is set. - Region->RegionBeg = (PrimaryBase + (I << Config::PrimaryRegionSizeLog)) + - (Config::PrimaryEnableRandomOffset - ? ((getRandomModN(&Seed, 16) + 1) * PageSize) - : 0); + Region->RegionBeg = + (PrimaryBase + (I << Config::Primary::RegionSizeLog)) + + (Config::Primary::EnableRandomOffset + ? ((getRandomModN(&Seed, 16) + 1) * PageSize) + : 0); Region->RandState = getRandomU32(&Seed); // Releasing small blocks is expensive, set a higher threshold to avoid // frequent page releases. @@ -322,9 +323,9 @@ template class SizeClassAllocator64 { bool setOption(Option O, sptr Value) { if (O == Option::ReleaseInterval) { - const s32 Interval = Max( - Min(static_cast(Value), Config::PrimaryMaxReleaseToOsIntervalMs), - Config::PrimaryMinReleaseToOsIntervalMs); + const s32 Interval = Max(Min(static_cast(Value), + Config::Primary::MaxReleaseToOsIntervalMs), + Config::Primary::MinReleaseToOsIntervalMs); atomic_store_relaxed(&ReleaseToOsIntervalMs, Interval); return true; } @@ -420,11 +421,11 @@ template class SizeClassAllocator64 { AtomicOptions Options; private: - static const uptr RegionSize = 1UL << Config::PrimaryRegionSizeLog; + static const uptr RegionSize = 1UL << Config::Primary::RegionSizeLog; static const uptr NumClasses = SizeClassMap::NumClasses; static const uptr PrimarySize = RegionSize * NumClasses; - static const uptr MapSizeIncrement = Config::PrimaryMapSizeIncrement; + static const uptr MapSizeIncrement = Config::Primary::MapSizeIncrement; // Fill at most this number of batches from the newly map'd memory. static const u32 MaxNumBatches = SCUDO_ANDROID ? 4U : 8U; @@ -506,6 +507,11 @@ template class SizeClassAllocator64 { return BlockSize < PageSize / 16U; } + ALWAYS_INLINE static bool isLargeBlock(uptr BlockSize) { + const uptr PageSize = getPageSizeCached(); + return BlockSize > PageSize; + } + // Push the blocks to their batch group. The layout will be like, // // FreeList - > BG -> BG -> BG @@ -848,8 +854,6 @@ template class SizeClassAllocator64 { if (UNLIKELY(BytesInFreeList == 0)) return 0; - bool MaySkip = false; - // Always update `BytesInFreeListAtLastCheckpoint` with the smallest value // so that we won't underestimate the releasable pages. For example, the // following is the region usage, @@ -869,38 +873,43 @@ template class SizeClassAllocator64 { if (BytesInFreeList <= Region->ReleaseInfo.BytesInFreeListAtLastCheckpoint) { Region->ReleaseInfo.BytesInFreeListAtLastCheckpoint = BytesInFreeList; - MaySkip = true; } const uptr RegionPushedBytesDelta = BytesInFreeList - Region->ReleaseInfo.BytesInFreeListAtLastCheckpoint; - if (RegionPushedBytesDelta < PageSize) - MaySkip = true; + if (RegionPushedBytesDelta < PageSize && + ReleaseType != ReleaseToOS::ForceAll) { + return 0; + } const bool CheckDensity = isSmallBlock(BlockSize); // Releasing smaller blocks is expensive, so we want to make sure that a // significant amount of bytes are free, and that there has been a good // amount of batches pushed to the freelist before attempting to release. - if (CheckDensity) { - if (ReleaseType == ReleaseToOS::Normal && - RegionPushedBytesDelta < Region->TryReleaseThreshold) { - MaySkip = true; - } - } - - if (MaySkip && ReleaseType != ReleaseToOS::ForceAll) - return 0; + if (CheckDensity && ReleaseType == ReleaseToOS::Normal) + if (RegionPushedBytesDelta < Region->TryReleaseThreshold) + return 0; if (ReleaseType == ReleaseToOS::Normal) { const s32 IntervalMs = atomic_load_relaxed(&ReleaseToOsIntervalMs); if (IntervalMs < 0) return 0; - if (Region->ReleaseInfo.LastReleaseAtNs + - static_cast(IntervalMs) * 1000000 > - getMonotonicTimeFast()) { - return 0; // Memory was returned recently. + + // The constant 8 here is selected from profiling some apps and the number + // of unreleased pages in the large size classes is around 16 pages or + // more. Choose half of it as a heuristic and which also avoids page + // release every time for every pushBlocks() attempt by large blocks. + const bool ByPassReleaseInterval = + isLargeBlock(BlockSize) && RegionPushedBytesDelta > 8 * PageSize; + if (!ByPassReleaseInterval) { + if (Region->ReleaseInfo.LastReleaseAtNs + + static_cast(IntervalMs) * 1000000 > + getMonotonicTimeFast()) { + // Memory was returned recently. + return 0; + } } - } + } // if (ReleaseType == ReleaseToOS::Normal) const uptr GroupSize = (1U << GroupSizeLog); const uptr AllocatedUserEnd = Region->AllocatedUser + Region->RegionBeg; diff --git a/compiler-rt/lib/scudo/standalone/secondary.h b/compiler-rt/lib/scudo/standalone/secondary.h index 94009f5fa9c65..a259cb71e164c 100644 --- a/compiler-rt/lib/scudo/standalone/secondary.h +++ b/compiler-rt/lib/scudo/standalone/secondary.h @@ -64,7 +64,7 @@ template static Header *getHeader(const void *Ptr) { } // namespace LargeBlock -static void unmap(LargeBlock::Header *H) { +static inline void unmap(LargeBlock::Header *H) { // Note that the `H->MapMap` is stored on the pages managed by itself. Take // over the ownership before unmap() so that any operation along with unmap() // won't touch inaccessible pages. @@ -72,7 +72,7 @@ static void unmap(LargeBlock::Header *H) { MemMap.unmap(MemMap.getBase(), MemMap.getCapacity()); } -class MapAllocatorNoCache { +template class MapAllocatorNoCache { public: void init(UNUSED s32 ReleaseToOsInterval) {} bool retrieve(UNUSED Options Options, UNUSED uptr Size, UNUSED uptr Alignment, @@ -130,17 +130,18 @@ template class NonZeroLengthArray { template class MapAllocatorCache { public: + using CacheConfig = typename Config::Secondary::Cache; // Ensure the default maximum specified fits the array. - static_assert(Config::SecondaryCacheDefaultMaxEntriesCount <= - Config::SecondaryCacheEntriesArraySize, + static_assert(CacheConfig::DefaultMaxEntriesCount <= + CacheConfig::EntriesArraySize, ""); void init(s32 ReleaseToOsInterval) NO_THREAD_SAFETY_ANALYSIS { DCHECK_EQ(EntriesCount, 0U); setOption(Option::MaxCacheEntriesCount, - static_cast(Config::SecondaryCacheDefaultMaxEntriesCount)); + static_cast(CacheConfig::DefaultMaxEntriesCount)); setOption(Option::MaxCacheEntrySize, - static_cast(Config::SecondaryCacheDefaultMaxEntrySize)); + static_cast(CacheConfig::DefaultMaxEntrySize)); setOption(Option::ReleaseInterval, static_cast(ReleaseToOsInterval)); } @@ -185,10 +186,9 @@ template class MapAllocatorCache { // just unmap it. break; } - if (Config::SecondaryCacheQuarantineSize && - useMemoryTagging(Options)) { + if (CacheConfig::QuarantineSize && useMemoryTagging(Options)) { QuarantinePos = - (QuarantinePos + 1) % Max(Config::SecondaryCacheQuarantineSize, 1u); + (QuarantinePos + 1) % Max(CacheConfig::QuarantineSize, 1u); if (!Quarantine[QuarantinePos].CommitBase) { Quarantine[QuarantinePos] = Entry; return; @@ -291,16 +291,15 @@ template class MapAllocatorCache { bool setOption(Option O, sptr Value) { if (O == Option::ReleaseInterval) { - const s32 Interval = - Max(Min(static_cast(Value), - Config::SecondaryCacheMaxReleaseToOsIntervalMs), - Config::SecondaryCacheMinReleaseToOsIntervalMs); + const s32 Interval = Max( + Min(static_cast(Value), CacheConfig::MaxReleaseToOsIntervalMs), + CacheConfig::MinReleaseToOsIntervalMs); atomic_store_relaxed(&ReleaseToOsIntervalMs, Interval); return true; } if (O == Option::MaxCacheEntriesCount) { const u32 MaxCount = static_cast(Value); - if (MaxCount > Config::SecondaryCacheEntriesArraySize) + if (MaxCount > CacheConfig::EntriesArraySize) return false; atomic_store_relaxed(&MaxEntriesCount, MaxCount); return true; @@ -317,7 +316,7 @@ template class MapAllocatorCache { void disableMemoryTagging() EXCLUDES(Mutex) { ScopedLock L(Mutex); - for (u32 I = 0; I != Config::SecondaryCacheQuarantineSize; ++I) { + for (u32 I = 0; I != CacheConfig::QuarantineSize; ++I) { if (Quarantine[I].CommitBase) { MemMapT &MemMap = Quarantine[I].MemMap; MemMap.unmap(MemMap.getBase(), MemMap.getCapacity()); @@ -342,11 +341,11 @@ template class MapAllocatorCache { private: void empty() { - MemMapT MapInfo[Config::SecondaryCacheEntriesArraySize]; + MemMapT MapInfo[CacheConfig::EntriesArraySize]; uptr N = 0; { ScopedLock L(Mutex); - for (uptr I = 0; I < Config::SecondaryCacheEntriesArraySize; I++) { + for (uptr I = 0; I < CacheConfig::EntriesArraySize; I++) { if (!Entries[I].CommitBase) continue; MapInfo[N] = Entries[I].MemMap; @@ -387,9 +386,9 @@ template class MapAllocatorCache { if (!EntriesCount || OldestTime == 0 || OldestTime > Time) return; OldestTime = 0; - for (uptr I = 0; I < Config::SecondaryCacheQuarantineSize; I++) + for (uptr I = 0; I < CacheConfig::QuarantineSize; I++) releaseIfOlderThan(Quarantine[I], Time); - for (uptr I = 0; I < Config::SecondaryCacheEntriesArraySize; I++) + for (uptr I = 0; I < CacheConfig::EntriesArraySize; I++) releaseIfOlderThan(Entries[I], Time); } @@ -402,9 +401,8 @@ template class MapAllocatorCache { u32 IsFullEvents GUARDED_BY(Mutex) = 0; atomic_s32 ReleaseToOsIntervalMs = {}; - CachedBlock - Entries[Config::SecondaryCacheEntriesArraySize] GUARDED_BY(Mutex) = {}; - NonZeroLengthArray + CachedBlock Entries[CacheConfig::EntriesArraySize] GUARDED_BY(Mutex) = {}; + NonZeroLengthArray Quarantine GUARDED_BY(Mutex) = {}; }; @@ -469,7 +467,7 @@ template class MapAllocator { void unmapTestOnly() { Cache.unmapTestOnly(); } private: - typename Config::SecondaryCache Cache; + typename Config::Secondary::template CacheT Cache; mutable HybridMutex Mutex; DoublyLinkedList InUseBlocks GUARDED_BY(Mutex); diff --git a/compiler-rt/lib/scudo/standalone/tests/combined_test.cpp b/compiler-rt/lib/scudo/standalone/tests/combined_test.cpp index 44ba639f7aa24..a4916d0ba027e 100644 --- a/compiler-rt/lib/scudo/standalone/tests/combined_test.cpp +++ b/compiler-rt/lib/scudo/standalone/tests/combined_test.cpp @@ -541,21 +541,29 @@ struct DeathSizeClassConfig { static const scudo::uptr DeathRegionSizeLog = 21U; struct DeathConfig { static const bool MaySupportMemoryTagging = false; - - // Tiny allocator, its Primary only serves chunks of four sizes. - using SizeClassMap = scudo::FixedSizeClassMap; - typedef scudo::SizeClassAllocator64 Primary; - static const scudo::uptr PrimaryRegionSizeLog = DeathRegionSizeLog; - static const scudo::s32 PrimaryMinReleaseToOsIntervalMs = INT32_MIN; - static const scudo::s32 PrimaryMaxReleaseToOsIntervalMs = INT32_MAX; - typedef scudo::uptr PrimaryCompactPtrT; - static const scudo::uptr PrimaryCompactPtrScale = 0; - static const bool PrimaryEnableRandomOffset = true; - static const scudo::uptr PrimaryMapSizeIncrement = 1UL << 18; - static const scudo::uptr PrimaryGroupSizeLog = 18; - - typedef scudo::MapAllocatorNoCache SecondaryCache; template using TSDRegistryT = scudo::TSDRegistrySharedT; + + struct Primary { + // Tiny allocator, its Primary only serves chunks of four sizes. + using SizeClassMap = scudo::FixedSizeClassMap; + static const scudo::uptr RegionSizeLog = DeathRegionSizeLog; + static const scudo::s32 MinReleaseToOsIntervalMs = INT32_MIN; + static const scudo::s32 MaxReleaseToOsIntervalMs = INT32_MAX; + typedef scudo::uptr CompactPtrT; + static const scudo::uptr CompactPtrScale = 0; + static const bool EnableRandomOffset = true; + static const scudo::uptr MapSizeIncrement = 1UL << 18; + static const scudo::uptr GroupSizeLog = 18; + }; + template + using PrimaryT = scudo::SizeClassAllocator64; + + struct Secondary { + template + using CacheT = scudo::MapAllocatorNoCache; + }; + + template using SecondaryT = scudo::MapAllocator; }; TEST(ScudoCombinedDeathTest, DeathCombined) { @@ -600,13 +608,14 @@ TEST(ScudoCombinedTest, FullRegion) { std::vector V; scudo::uptr FailedAllocationsCount = 0; for (scudo::uptr ClassId = 1U; - ClassId <= DeathConfig::SizeClassMap::LargestClassId; ClassId++) { + ClassId <= DeathConfig::Primary::SizeClassMap::LargestClassId; + ClassId++) { const scudo::uptr Size = - DeathConfig::SizeClassMap::getSizeByClassId(ClassId); + DeathConfig::Primary::SizeClassMap::getSizeByClassId(ClassId); // Allocate enough to fill all of the regions above this one. const scudo::uptr MaxNumberOfChunks = ((1U << DeathRegionSizeLog) / Size) * - (DeathConfig::SizeClassMap::LargestClassId - ClassId + 1); + (DeathConfig::Primary::SizeClassMap::LargestClassId - ClassId + 1); void *P; for (scudo::uptr I = 0; I <= MaxNumberOfChunks; I++) { P = Allocator->allocate(Size - 64U, Origin); diff --git a/compiler-rt/lib/scudo/standalone/tests/primary_test.cpp b/compiler-rt/lib/scudo/standalone/tests/primary_test.cpp index 51a7038ac7870..fb67d448331f5 100644 --- a/compiler-rt/lib/scudo/standalone/tests/primary_test.cpp +++ b/compiler-rt/lib/scudo/standalone/tests/primary_test.cpp @@ -25,82 +25,96 @@ // 32-bit architectures. It's not something we want to encourage, but we still // should ensure the tests pass. -struct TestConfig1 { - static const scudo::uptr PrimaryRegionSizeLog = 18U; - static const scudo::uptr PrimaryGroupSizeLog = 18U; - static const scudo::s32 PrimaryMinReleaseToOsIntervalMs = INT32_MIN; - static const scudo::s32 PrimaryMaxReleaseToOsIntervalMs = INT32_MAX; +template struct TestConfig1 { static const bool MaySupportMemoryTagging = false; - typedef scudo::uptr PrimaryCompactPtrT; - static const scudo::uptr PrimaryCompactPtrScale = 0; - static const bool PrimaryEnableRandomOffset = true; - static const scudo::uptr PrimaryMapSizeIncrement = 1UL << 18; + + struct Primary { + using SizeClassMap = SizeClassMapT; + static const scudo::uptr RegionSizeLog = 18U; + static const scudo::uptr GroupSizeLog = 18U; + static const scudo::s32 MinReleaseToOsIntervalMs = INT32_MIN; + static const scudo::s32 MaxReleaseToOsIntervalMs = INT32_MAX; + typedef scudo::uptr CompactPtrT; + static const scudo::uptr CompactPtrScale = 0; + static const bool EnableRandomOffset = true; + static const scudo::uptr MapSizeIncrement = 1UL << 18; + }; }; -struct TestConfig2 { +template struct TestConfig2 { + static const bool MaySupportMemoryTagging = false; + + struct Primary { + using SizeClassMap = SizeClassMapT; #if defined(__mips__) - // Unable to allocate greater size on QEMU-user. - static const scudo::uptr PrimaryRegionSizeLog = 23U; + // Unable to allocate greater size on QEMU-user. + static const scudo::uptr RegionSizeLog = 23U; #else - static const scudo::uptr PrimaryRegionSizeLog = 24U; + static const scudo::uptr RegionSizeLog = 24U; #endif - static const scudo::uptr PrimaryGroupSizeLog = 20U; - static const scudo::s32 PrimaryMinReleaseToOsIntervalMs = INT32_MIN; - static const scudo::s32 PrimaryMaxReleaseToOsIntervalMs = INT32_MAX; - static const bool MaySupportMemoryTagging = false; - typedef scudo::uptr PrimaryCompactPtrT; - static const scudo::uptr PrimaryCompactPtrScale = 0; - static const bool PrimaryEnableRandomOffset = true; - static const scudo::uptr PrimaryMapSizeIncrement = 1UL << 18; + static const scudo::uptr GroupSizeLog = 20U; + static const scudo::s32 MinReleaseToOsIntervalMs = INT32_MIN; + static const scudo::s32 MaxReleaseToOsIntervalMs = INT32_MAX; + typedef scudo::uptr CompactPtrT; + static const scudo::uptr CompactPtrScale = 0; + static const bool EnableRandomOffset = true; + static const scudo::uptr MapSizeIncrement = 1UL << 18; + }; }; -struct TestConfig3 { +template struct TestConfig3 { + static const bool MaySupportMemoryTagging = true; + + struct Primary { + using SizeClassMap = SizeClassMapT; #if defined(__mips__) - // Unable to allocate greater size on QEMU-user. - static const scudo::uptr PrimaryRegionSizeLog = 23U; + // Unable to allocate greater size on QEMU-user. + static const scudo::uptr RegionSizeLog = 23U; #else - static const scudo::uptr PrimaryRegionSizeLog = 24U; + static const scudo::uptr RegionSizeLog = 24U; #endif - static const scudo::uptr PrimaryGroupSizeLog = 20U; - static const scudo::s32 PrimaryMinReleaseToOsIntervalMs = INT32_MIN; - static const scudo::s32 PrimaryMaxReleaseToOsIntervalMs = INT32_MAX; - static const bool MaySupportMemoryTagging = true; - typedef scudo::uptr PrimaryCompactPtrT; - static const scudo::uptr PrimaryCompactPtrScale = 0; - static const bool PrimaryEnableRandomOffset = true; - static const scudo::uptr PrimaryMapSizeIncrement = 1UL << 18; + static const scudo::uptr GroupSizeLog = 20U; + static const scudo::s32 MinReleaseToOsIntervalMs = INT32_MIN; + static const scudo::s32 MaxReleaseToOsIntervalMs = INT32_MAX; + typedef scudo::uptr CompactPtrT; + static const scudo::uptr CompactPtrScale = 0; + static const bool EnableRandomOffset = true; + static const scudo::uptr MapSizeIncrement = 1UL << 18; + }; }; -struct TestConfig4 { +template struct TestConfig4 { + static const bool MaySupportMemoryTagging = true; + + struct Primary { + using SizeClassMap = SizeClassMapT; #if defined(__mips__) - // Unable to allocate greater size on QEMU-user. - static const scudo::uptr PrimaryRegionSizeLog = 23U; + // Unable to allocate greater size on QEMU-user. + static const scudo::uptr RegionSizeLog = 23U; #else - static const scudo::uptr PrimaryRegionSizeLog = 24U; + static const scudo::uptr RegionSizeLog = 24U; #endif - static const scudo::s32 PrimaryMinReleaseToOsIntervalMs = INT32_MIN; - static const scudo::s32 PrimaryMaxReleaseToOsIntervalMs = INT32_MAX; - static const bool MaySupportMemoryTagging = true; - static const scudo::uptr PrimaryCompactPtrScale = 3U; - static const scudo::uptr PrimaryGroupSizeLog = 20U; - typedef scudo::u32 PrimaryCompactPtrT; - static const bool PrimaryEnableRandomOffset = true; - static const scudo::uptr PrimaryMapSizeIncrement = 1UL << 18; + static const scudo::s32 MinReleaseToOsIntervalMs = INT32_MIN; + static const scudo::s32 MaxReleaseToOsIntervalMs = INT32_MAX; + static const scudo::uptr CompactPtrScale = 3U; + static const scudo::uptr GroupSizeLog = 20U; + typedef scudo::u32 CompactPtrT; + static const bool EnableRandomOffset = true; + static const scudo::uptr MapSizeIncrement = 1UL << 18; + }; }; -template -struct Config : public BaseConfig { - using SizeClassMap = SizeClassMapT; -}; +template