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Changed the PWM speed for port C and D in split mode to 1KHz to match…

… the other ports.

Inspired by russellmcc commit 9db4415.
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1 parent b3bbefb commit 1fc5636da2ae209f8e0698620b940556b3c56df5 @karlbackstrom karlbackstrom committed Mar 17, 2012
Showing with 6 additions and 1 deletion.
  1. +5 −0 hardware/xmegaduino/cores/xmega/wiring.c
  2. +1 −1 hardware/xmegaduino/cores/xmega/wiring_analog.c
@@ -298,6 +298,11 @@ void init()
TCF1.CTRLD = TC_EVACT_UPDOWN_gc | TC1_EVDLY_bm;
TCF1.INTCTRLA = TC_OVFINTLVL_HI_gc;
#endif
+
+#if defined(TCC2) || defined(TCD2)
+ // port C&D pwm uses EVCH7 for a div128 prescaled clock.
+ EVSYS.CH7MUX = EVSYS_CHMUX_PRESCALER_128_gc;
+#endif
/*************************************/
/* Init I/O ports */
@@ -225,7 +225,7 @@ void analogWrite(uint8_t pin, int val)
tc2->CTRLE = TC2_BYTEM_SPLITMODE_gc;
tc2->LPER = 0xFF;
tc2->HPER = 0xFF;
- tc2->CTRLA = TC2_CLKSEL_DIV64_gc;
+ tc2->CTRLA = TC2_CLKSEL_EVCH7_gc; // wiring.c sets EVCH7 as a /128 prescaled clock.
tc2->CTRLB |= 1 << channel;
}
#endif

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