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Merge branch 'omap-fixes-for-linus' of git://git.kernel.org/pub/scm/l…
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…inux/kernel/git/tmlind/linux-omap-2.6

* 'omap-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap-2.6: (25 commits)
  OMAP2/3: DMTIMER: Clear pending interrupts when stopping a timer
  PM debug: Fix warning when no CONFIG_DEBUG_FS
  OMAP3: PM: DSS PM_WKEN to refill DMA
  OMAP: timekeeping: time should not stop during suspend
  OMAP3: PM: Force write last pad config register into save area
  OMAP: omap3_pm_get_suspend_state() error ignored in pwrdm_suspend_get()
  OMAP3: PM: Enable wake-up from McBSP2, 3 and 4 modules
  OMAP3: PM debug: fix build error when !CONFIG_DEBUG_FS
  OMAP3: PM: Removing redundant and potentially dangerous PRCM configration
  OMAP3: Fixed ARM aux ctrl register save/restore
  OMAP3: CPUidle: Fixed timer resolution
  OMAP3: PM: Remove duplicate code blocks
  OMAP3: PM: Disable interrupt controller AUTOIDLE before WFI
  OMAP3: PM: Enable system control module autoidle
  OMAP3: PM: Ack pending interrupts before entering suspend
  omap: Enable GPMC clock in gpmc_init
  OMAP1 clock: fix for "BUG: spinlock lockup on CPU#0"
  OMAP4: clocks: Fix the clksel_rate struct DPLL divs
  OMAP4: PRCM: Fix the base address for CHIRONSS reg defines
  OMAP: dma_chan[lch_head].flag & OMAP_DMA_ACTIVE tested twice in omap_dma_unlink_lch()
  ...
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@torvalds
torvalds committed Jan 26, 2010
2 parents f6760aa + 5c3db36 commit 4f4e65d
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Showing 23 changed files with 229 additions and 131 deletions.
6 changes: 3 additions & 3 deletions arch/arm/mach-omap1/clock.c
View file
Expand Up @@ -214,8 +214,8 @@ int omap1_select_table_rate(struct clk *clk, unsigned long rate)
struct mpu_rate * ptr;
unsigned long dpll1_rate, ref_rate;

dpll1_rate = clk_get_rate(ck_dpll1_p);
ref_rate = clk_get_rate(ck_ref_p);
dpll1_rate = ck_dpll1_p->rate;
ref_rate = ck_ref_p->rate;

for (ptr = omap1_rate_table; ptr->rate; ptr++) {
if (ptr->xtal != ref_rate)
Expand Down Expand Up @@ -306,7 +306,7 @@ long omap1_round_to_table_rate(struct clk *clk, unsigned long rate)
long highest_rate;
unsigned long ref_rate;

ref_rate = clk_get_rate(ck_ref_p);
ref_rate = ck_ref_p->rate;

highest_rate = -EINVAL;

Expand Down
4 changes: 0 additions & 4 deletions arch/arm/mach-omap2/clock34xx_data.c
View file
Expand Up @@ -671,7 +671,6 @@ static struct clk dpll4_m3x2_ck = {
.name = "dpll4_m3x2_ck",
.ops = &clkops_omap2_dflt_wait,
.parent = &dpll4_m3_ck,
.init = &omap2_init_clksel_parent,
.enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
.enable_bit = OMAP3430_PWRDN_TV_SHIFT,
.flags = INVERT_ENABLE,
Expand Down Expand Up @@ -811,7 +810,6 @@ static struct clk dpll4_m6x2_ck = {
.name = "dpll4_m6x2_ck",
.ops = &clkops_omap2_dflt_wait,
.parent = &dpll4_m6_ck,
.init = &omap2_init_clksel_parent,
.enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
.enable_bit = OMAP3430_PWRDN_EMU_PERIPH_SHIFT,
.flags = INVERT_ENABLE,
Expand Down Expand Up @@ -1047,7 +1045,6 @@ static struct clk iva2_ck = {
.name = "iva2_ck",
.ops = &clkops_omap2_dflt_wait,
.parent = &dpll2_m2_ck,
.init = &omap2_init_clksel_parent,
.enable_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, CM_FCLKEN),
.enable_bit = OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_SHIFT,
.clkdm_name = "iva2_clkdm",
Expand Down Expand Up @@ -1121,7 +1118,6 @@ static struct clk gfx_l3_ck = {
.name = "gfx_l3_ck",
.ops = &clkops_omap2_dflt_wait,
.parent = &l3_ick,
.init = &omap2_init_clksel_parent,
.enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_ICLKEN),
.enable_bit = OMAP_EN_GFX_SHIFT,
.recalc = &followparent_recalc,
Expand Down
62 changes: 31 additions & 31 deletions arch/arm/mach-omap2/clock44xx_data.c
View file
Expand Up @@ -346,37 +346,37 @@ static struct clk aess_fclk = {
};

static const struct clksel_rate div31_1to31_rates[] = {
{ .div = 1, .val = 0, .flags = RATE_IN_4430 },
{ .div = 2, .val = 1, .flags = RATE_IN_4430 },
{ .div = 3, .val = 2, .flags = RATE_IN_4430 },
{ .div = 4, .val = 3, .flags = RATE_IN_4430 },
{ .div = 5, .val = 4, .flags = RATE_IN_4430 },
{ .div = 6, .val = 5, .flags = RATE_IN_4430 },
{ .div = 7, .val = 6, .flags = RATE_IN_4430 },
{ .div = 8, .val = 7, .flags = RATE_IN_4430 },
{ .div = 9, .val = 8, .flags = RATE_IN_4430 },
{ .div = 10, .val = 9, .flags = RATE_IN_4430 },
{ .div = 11, .val = 10, .flags = RATE_IN_4430 },
{ .div = 12, .val = 11, .flags = RATE_IN_4430 },
{ .div = 13, .val = 12, .flags = RATE_IN_4430 },
{ .div = 14, .val = 13, .flags = RATE_IN_4430 },
{ .div = 15, .val = 14, .flags = RATE_IN_4430 },
{ .div = 16, .val = 15, .flags = RATE_IN_4430 },
{ .div = 17, .val = 16, .flags = RATE_IN_4430 },
{ .div = 18, .val = 17, .flags = RATE_IN_4430 },
{ .div = 19, .val = 18, .flags = RATE_IN_4430 },
{ .div = 20, .val = 19, .flags = RATE_IN_4430 },
{ .div = 21, .val = 20, .flags = RATE_IN_4430 },
{ .div = 22, .val = 21, .flags = RATE_IN_4430 },
{ .div = 23, .val = 22, .flags = RATE_IN_4430 },
{ .div = 24, .val = 23, .flags = RATE_IN_4430 },
{ .div = 25, .val = 24, .flags = RATE_IN_4430 },
{ .div = 26, .val = 25, .flags = RATE_IN_4430 },
{ .div = 27, .val = 26, .flags = RATE_IN_4430 },
{ .div = 28, .val = 27, .flags = RATE_IN_4430 },
{ .div = 29, .val = 28, .flags = RATE_IN_4430 },
{ .div = 30, .val = 29, .flags = RATE_IN_4430 },
{ .div = 31, .val = 30, .flags = RATE_IN_4430 },
{ .div = 1, .val = 1, .flags = RATE_IN_4430 },
{ .div = 2, .val = 2, .flags = RATE_IN_4430 },
{ .div = 3, .val = 3, .flags = RATE_IN_4430 },
{ .div = 4, .val = 4, .flags = RATE_IN_4430 },
{ .div = 5, .val = 5, .flags = RATE_IN_4430 },
{ .div = 6, .val = 6, .flags = RATE_IN_4430 },
{ .div = 7, .val = 7, .flags = RATE_IN_4430 },
{ .div = 8, .val = 8, .flags = RATE_IN_4430 },
{ .div = 9, .val = 9, .flags = RATE_IN_4430 },
{ .div = 10, .val = 10, .flags = RATE_IN_4430 },
{ .div = 11, .val = 11, .flags = RATE_IN_4430 },
{ .div = 12, .val = 12, .flags = RATE_IN_4430 },
{ .div = 13, .val = 13, .flags = RATE_IN_4430 },
{ .div = 14, .val = 14, .flags = RATE_IN_4430 },
{ .div = 15, .val = 15, .flags = RATE_IN_4430 },
{ .div = 16, .val = 16, .flags = RATE_IN_4430 },
{ .div = 17, .val = 17, .flags = RATE_IN_4430 },
{ .div = 18, .val = 18, .flags = RATE_IN_4430 },
{ .div = 19, .val = 19, .flags = RATE_IN_4430 },
{ .div = 20, .val = 20, .flags = RATE_IN_4430 },
{ .div = 21, .val = 21, .flags = RATE_IN_4430 },
{ .div = 22, .val = 22, .flags = RATE_IN_4430 },
{ .div = 23, .val = 23, .flags = RATE_IN_4430 },
{ .div = 24, .val = 24, .flags = RATE_IN_4430 },
{ .div = 25, .val = 25, .flags = RATE_IN_4430 },
{ .div = 26, .val = 26, .flags = RATE_IN_4430 },
{ .div = 27, .val = 27, .flags = RATE_IN_4430 },
{ .div = 28, .val = 28, .flags = RATE_IN_4430 },
{ .div = 29, .val = 29, .flags = RATE_IN_4430 },
{ .div = 30, .val = 30, .flags = RATE_IN_4430 },
{ .div = 31, .val = 31, .flags = RATE_IN_4430 },
{ .div = 0 },
};

Expand Down
2 changes: 1 addition & 1 deletion arch/arm/mach-omap2/cpuidle34xx.c
View file
Expand Up @@ -137,7 +137,7 @@ static int omap3_enter_idle(struct cpuidle_device *dev,
local_irq_enable();
local_fiq_enable();

return (u32)timespec_to_ns(&ts_idle)/1000;
return ts_idle.tv_nsec / NSEC_PER_USEC + ts_idle.tv_sec * USEC_PER_SEC;
}

/**
Expand Down
2 changes: 2 additions & 0 deletions arch/arm/mach-omap2/gpmc.c
View file
Expand Up @@ -534,6 +534,8 @@ void __init gpmc_init(void)
BUG();
}

clk_enable(gpmc_l3_clk);

l = gpmc_read_reg(GPMC_REVISION);
printk(KERN_INFO "GPMC revision %d.%d\n", (l >> 4) & 0x0f, l & 0x0f);
/* Set smart idle mode and automatic L3 clock gating */
Expand Down
41 changes: 23 additions & 18 deletions arch/arm/mach-omap2/id.c
View file
Expand Up @@ -188,6 +188,8 @@ void __init omap3_check_revision(void)
u16 hawkeye;
u8 rev;

omap_chip.oc = CHIP_IS_OMAP3430;

/*
* We cannot access revision registers on ES1.0.
* If the processor type is Cortex-A8 and the revision is 0x0
Expand All @@ -196,6 +198,7 @@ void __init omap3_check_revision(void)
cpuid = read_cpuid(CPUID_ID);
if ((((cpuid >> 4) & 0xfff) == 0xc08) && ((cpuid & 0xf) == 0x0)) {
omap_revision = OMAP3430_REV_ES1_0;
omap_chip.oc |= CHIP_IS_OMAP3430ES1;
return;
}

Expand All @@ -216,33 +219,47 @@ void __init omap3_check_revision(void)
case 0: /* Take care of early samples */
case 1:
omap_revision = OMAP3430_REV_ES2_0;
omap_chip.oc |= CHIP_IS_OMAP3430ES2;
break;
case 2:
omap_revision = OMAP3430_REV_ES2_1;
omap_chip.oc |= CHIP_IS_OMAP3430ES2;
break;
case 3:
omap_revision = OMAP3430_REV_ES3_0;
omap_chip.oc |= CHIP_IS_OMAP3430ES3_0;
break;
case 4:
omap_revision = OMAP3430_REV_ES3_1;
omap_chip.oc |= CHIP_IS_OMAP3430ES3_1;
break;
case 7:
/* FALLTHROUGH */
default:
/* Use the latest known revision as default */
omap_revision = OMAP3430_REV_ES3_1;
omap_revision = OMAP3430_REV_ES3_1_2;

/* REVISIT: Add CHIP_IS_OMAP3430ES3_1_2? */
omap_chip.oc |= CHIP_IS_OMAP3430ES3_1;
}
break;
case 0xb868:
/* Handle OMAP35xx/AM35xx devices
*
* Set the device to be OMAP3505 here. Actual device
* is identified later based on the features.
*
* REVISIT: AM3505/AM3517 should have their own CHIP_IS
*/
omap_revision = OMAP3505_REV(rev);
omap_chip.oc |= CHIP_IS_OMAP3430ES3_1;
break;
case 0xb891:
/* FALLTHROUGH */
default:
/* Unknown default to latest silicon rev as default*/
omap_revision = OMAP3630_REV_ES1_0;
omap_chip.oc |= CHIP_IS_OMAP3630ES1;
}
}

Expand Down Expand Up @@ -360,6 +377,7 @@ void __init omap2_check_revision(void)
omap3_check_revision();
omap3_check_features();
omap3_cpuinfo();
return;
} else if (cpu_is_omap44xx()) {
omap4_check_revision();
return;
Expand All @@ -374,27 +392,14 @@ void __init omap2_check_revision(void)
if (cpu_is_omap243x()) {
/* Currently only supports 2430ES2.1 and 2430-all */
omap_chip.oc |= CHIP_IS_OMAP2430;
return;
} else if (cpu_is_omap242x()) {
/* Currently only supports 2420ES2.1.1 and 2420-all */
omap_chip.oc |= CHIP_IS_OMAP2420;
} else if (cpu_is_omap3505() || cpu_is_omap3517()) {
omap_chip.oc = CHIP_IS_OMAP3430 | CHIP_IS_OMAP3430ES3_1;
} else if (cpu_is_omap343x()) {
omap_chip.oc = CHIP_IS_OMAP3430;
if (omap_rev() == OMAP3430_REV_ES1_0)
omap_chip.oc |= CHIP_IS_OMAP3430ES1;
else if (omap_rev() >= OMAP3430_REV_ES2_0 &&
omap_rev() <= OMAP3430_REV_ES2_1)
omap_chip.oc |= CHIP_IS_OMAP3430ES2;
else if (omap_rev() == OMAP3430_REV_ES3_0)
omap_chip.oc |= CHIP_IS_OMAP3430ES3_0;
else if (omap_rev() == OMAP3430_REV_ES3_1)
omap_chip.oc |= CHIP_IS_OMAP3430ES3_1;
else if (omap_rev() == OMAP3630_REV_ES1_0)
omap_chip.oc |= CHIP_IS_OMAP3630ES1;
} else {
pr_err("Uninitialized omap_chip, please fix!\n");
return;
}

pr_err("Uninitialized omap_chip, please fix!\n");
}

/*
Expand Down
18 changes: 18 additions & 0 deletions arch/arm/mach-omap2/irq.c
View file
Expand Up @@ -274,4 +274,22 @@ void omap_intc_restore_context(void)
}
/* MIRs are saved and restore with other PRCM registers */
}

void omap3_intc_suspend(void)
{
/* A pending interrupt would prevent OMAP from entering suspend */
omap_ack_irq(0);
}

void omap3_intc_prepare_idle(void)
{
/* Disable autoidle as it can stall interrupt controller */
intc_bank_write_reg(0, &irq_banks[0], INTC_SYSCONFIG);
}

void omap3_intc_resume_idle(void)
{
/* Re-enable autoidle */
intc_bank_write_reg(1, &irq_banks[0], INTC_SYSCONFIG);
}
#endif /* CONFIG_ARCH_OMAP3 */
27 changes: 15 additions & 12 deletions arch/arm/mach-omap2/mux.c
View file
Expand Up @@ -51,22 +51,30 @@ struct omap_mux_entry {
static unsigned long mux_phys;
static void __iomem *mux_base;

static inline u16 omap_mux_read(u16 reg)
u16 omap_mux_read(u16 reg)
{
if (cpu_is_omap24xx())
return __raw_readb(mux_base + reg);
else
return __raw_readw(mux_base + reg);
}

static inline void omap_mux_write(u16 val, u16 reg)
void omap_mux_write(u16 val, u16 reg)
{
if (cpu_is_omap24xx())
__raw_writeb(val, mux_base + reg);
else
__raw_writew(val, mux_base + reg);
}

void omap_mux_write_array(struct omap_board_mux *board_mux)
{
while (board_mux->reg_offset != OMAP_MUX_TERMINATOR) {
omap_mux_write(board_mux->value, board_mux->reg_offset);
board_mux++;
}
}

#if defined(CONFIG_ARCH_OMAP24XX) && defined(CONFIG_OMAP_MUX)

static struct omap_mux_cfg arch_mux_cfg;
Expand Down Expand Up @@ -833,14 +841,6 @@ static void __init omap_mux_set_cmdline_signals(void)
kfree(options);
}

static void __init omap_mux_set_board_signals(struct omap_board_mux *board_mux)
{
while (board_mux->reg_offset != OMAP_MUX_TERMINATOR) {
omap_mux_write(board_mux->value, board_mux->reg_offset);
board_mux++;
}
}

static int __init omap_mux_copy_names(struct omap_mux *src,
struct omap_mux *dst)
{
Expand Down Expand Up @@ -998,12 +998,15 @@ int __init omap_mux_init(u32 mux_pbase, u32 mux_size,
omap_mux_package_fixup(package_subset, superset);
if (package_balls)
omap_mux_package_init_balls(package_balls, superset);
omap_mux_set_cmdline_signals();
omap_mux_set_board_signals(board_mux);
#endif

omap_mux_init_list(superset);

#ifdef CONFIG_OMAP_MUX
omap_mux_set_cmdline_signals();
omap_mux_write_array(board_mux);
#endif

return 0;
}

Expand Down
24 changes: 24 additions & 0 deletions arch/arm/mach-omap2/mux.h
View file
Expand Up @@ -146,6 +146,30 @@ u16 omap_mux_get_gpio(int gpio);
*/
void omap_mux_set_gpio(u16 val, int gpio);

/**
* omap_mux_read() - read mux register
* @mux_offset: Offset of the mux register
*
*/
u16 omap_mux_read(u16 mux_offset);

/**
* omap_mux_write() - write mux register
* @val: New mux register value
* @mux_offset: Offset of the mux register
*
* This should be only needed for dynamic remuxing of non-gpio signals.
*/
void omap_mux_write(u16 val, u16 mux_offset);

/**
* omap_mux_write_array() - write an array of mux registers
* @board_mux: Array of mux registers terminated by MAP_MUX_TERMINATOR
*
* This should be only needed for dynamic remuxing of non-gpio signals.
*/
void omap_mux_write_array(struct omap_board_mux *board_mux);

/**
* omap3_mux_init() - initialize mux system with board specific set
* @board_mux: Board specific mux table
Expand Down
3 changes: 2 additions & 1 deletion arch/arm/mach-omap2/omap_hwmod.c
View file
Expand Up @@ -94,7 +94,8 @@ static int _update_sysc_cache(struct omap_hwmod *oh)

oh->_sysc_cache = omap_hwmod_readl(oh, oh->sysconfig->sysc_offs);

oh->_int_flags |= _HWMOD_SYSCONFIG_LOADED;
if (!(oh->sysconfig->sysc_flags & SYSC_NO_CACHE))
oh->_int_flags |= _HWMOD_SYSCONFIG_LOADED;

return 0;
}
Expand Down

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