{"payload":{"header_redesign_enabled":false,"results":[{"id":"547773213","archived":false,"color":"#b2b7f8","followers":0,"has_funding_file":false,"hl_name":"YCCDSZXH/FPGA","hl_trunc_description":null,"language":"Verilog","mirror":false,"owned_by_organization":false,"public":true,"repo":{"repository":{"id":547773213,"name":"FPGA","owner_id":94218957,"owner_login":"YCCDSZXH","updated_at":"2022-11-26T05:37:07.349Z","has_issues":true}},"sponsorable":false,"topics":[],"type":"Public","help_wanted_issues_count":0,"good_first_issue_issues_count":0,"starred_by_current_user":false}],"type":"repositories","page":1,"page_count":1,"elapsed_millis":57,"errors":[],"result_count":1,"facets":[],"protected_org_logins":[],"topics":null,"query_id":"","logged_in":false,"sign_up_path":"/signup?source=code_search_results","sign_in_path":"/login?return_to=https%3A%2F%2Fgithub.com%2Fsearch%3Fq%3Drepo%253AYCCDSZXH%252FFPGA%2B%2Blanguage%253AVerilog","metadata":null,"csrf_tokens":{"/YCCDSZXH/FPGA/star":{"post":"tCqMeq6Ki0TpK9phZKnTEJkHYW2Vp4QWKdh0DRScko2ANtt9D8-gd3-q-1EMzokLhpsPstzHH1Z76YwwZM32zw"},"/YCCDSZXH/FPGA/unstar":{"post":"gIttEAUpWR5BjDdmI243NNSvwsSapu6WISPeIOyy8EtvbSY323tDbeYj5sqFjTMZ7y0zca-rrD9idKmGUBH6Jg"},"/sponsors/batch_deferred_sponsor_buttons":{"post":"Wx2PuidyCZXEHTQv_X_m11Q2I23m6n5365I_9pA5dsC6UV1e6prCL32LbhHAmD1950_fZWs2YCoWDYKAJqsqjQ"}}},"title":"Repository search results"}