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Update upstream code
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- CHANGELOG+2-1
- Makefile+3-1
- backends/smt2/smt2.cc+13
- backends/smt2/smtbmc.py+2-2
- backends/smt2/smtio.py+19-5
- kernel/celltypes.h+4-4
- kernel/constids.inc+1
- kernel/ff.h+440
- kernel/ffinit.h+146
- kernel/satgen.cc+1.2k
- kernel/satgen.h+13-1.2k
- passes/memory/memory_dff.cc+115-21
- passes/opt/pmux2shiftx.cc+4-15
- passes/opt/wreduce.cc+7-37
- passes/proc/proc_dlatch.cc+8-28
- passes/sat/async2sync.cc+11-53
- passes/sat/clk2fflogic.cc+122-200
- passes/sat/qbfsat.cc+14-1
- passes/sat/qbfsat.h+1
- passes/techmap/abc.cc+6-25
- passes/techmap/dffinit.cc+7-41
- passes/techmap/dfflegalize.cc+25-80
- passes/techmap/shregmap.cc+10-39
- passes/techmap/techmap.cc+10-41
- passes/techmap/zinit.cc+11-43
- techlibs/intel_alm/common/alm_sim.v+45-35
- techlibs/intel_alm/common/dff_sim.v+28-27
- techlibs/intel_alm/common/dsp_sim.v+9-6
- techlibs/intel_alm/common/mem_sim.v+9-4
- techlibs/xilinx/arith_map.v+1-113
- techlibs/xilinx/cells_sim.v-23
- techlibs/xilinx/synth_xilinx.cc+1-14
- tests/arch/intel_alm/mux.ys+4-6
- tests/arch/xilinx/pmgen_xilinx_srl.ys-2
- tests/opt/opt_rmdff.ys-1
- tests/sat/dff.ys+21
- tests/techmap/cellname.ys+41
- tests/techmap/dfflegalize_adff.ys+4-4
- tests/techmap/dfflegalize_adff_init.ys+12-12
- tests/techmap/dfflegalize_adlatch.ys+2-2
- tests/techmap/dfflegalize_adlatch_init.ys+6-6
- tests/techmap/dfflegalize_dff.ys+9-9
- tests/techmap/dfflegalize_dff_init.ys+28-28
- tests/techmap/dfflegalize_dffsr.ys+4-4
- tests/techmap/dfflegalize_dffsr_init.ys+12-12
- tests/techmap/dfflegalize_dlatch.ys+3-3
- tests/techmap/dfflegalize_dlatch_const.ys+4-4
- tests/techmap/dfflegalize_dlatch_init.ys+8-8
- tests/techmap/dfflegalize_dlatchsr.ys+2-2
- tests/techmap/dfflegalize_dlatchsr_init.ys+6-6
- tests/techmap/dfflegalize_inv.ys+3-3
- tests/techmap/dfflegalize_mince.ys+1-1
- tests/techmap/dfflegalize_minsrst.ys+1-1
- tests/techmap/dfflegalize_sr.ys+6-6
- tests/techmap/dfflegalize_sr_init.ys+12-12
- tests/techmap/zinit.ys+2-2
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