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Update upstream code
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github-actions committed Jul 26, 2020
1 parent 2f7882d commit e5e262ce505dd0f39d295ec69d49b9839aa4b0e4
Showing with 1 addition and 1 deletion.
  1. +1 −1 yosys-src
Submodule yosys-src updated 56 files
+2 −1 CHANGELOG
+3 −1 Makefile
+13 −0 backends/smt2/smt2.cc
+2 −2 backends/smt2/smtbmc.py
+19 −5 backends/smt2/smtio.py
+4 −4 kernel/celltypes.h
+1 −0 kernel/constids.inc
+440 −0 kernel/ff.h
+146 −0 kernel/ffinit.h
+1,239 −0 kernel/satgen.cc
+13 −1,165 kernel/satgen.h
+115 −21 passes/memory/memory_dff.cc
+4 −15 passes/opt/pmux2shiftx.cc
+7 −37 passes/opt/wreduce.cc
+8 −28 passes/proc/proc_dlatch.cc
+11 −53 passes/sat/async2sync.cc
+122 −200 passes/sat/clk2fflogic.cc
+14 −1 passes/sat/qbfsat.cc
+1 −0 passes/sat/qbfsat.h
+6 −25 passes/techmap/abc.cc
+7 −41 passes/techmap/dffinit.cc
+25 −80 passes/techmap/dfflegalize.cc
+10 −39 passes/techmap/shregmap.cc
+10 −41 passes/techmap/techmap.cc
+11 −43 passes/techmap/zinit.cc
+45 −35 techlibs/intel_alm/common/alm_sim.v
+28 −27 techlibs/intel_alm/common/dff_sim.v
+9 −6 techlibs/intel_alm/common/dsp_sim.v
+9 −4 techlibs/intel_alm/common/mem_sim.v
+1 −113 techlibs/xilinx/arith_map.v
+0 −23 techlibs/xilinx/cells_sim.v
+1 −14 techlibs/xilinx/synth_xilinx.cc
+4 −6 tests/arch/intel_alm/mux.ys
+0 −2 tests/arch/xilinx/pmgen_xilinx_srl.ys
+0 −1 tests/opt/opt_rmdff.ys
+21 −0 tests/sat/dff.ys
+41 −0 tests/techmap/cellname.ys
+4 −4 tests/techmap/dfflegalize_adff.ys
+12 −12 tests/techmap/dfflegalize_adff_init.ys
+2 −2 tests/techmap/dfflegalize_adlatch.ys
+6 −6 tests/techmap/dfflegalize_adlatch_init.ys
+9 −9 tests/techmap/dfflegalize_dff.ys
+28 −28 tests/techmap/dfflegalize_dff_init.ys
+4 −4 tests/techmap/dfflegalize_dffsr.ys
+12 −12 tests/techmap/dfflegalize_dffsr_init.ys
+3 −3 tests/techmap/dfflegalize_dlatch.ys
+4 −4 tests/techmap/dfflegalize_dlatch_const.ys
+8 −8 tests/techmap/dfflegalize_dlatch_init.ys
+2 −2 tests/techmap/dfflegalize_dlatchsr.ys
+6 −6 tests/techmap/dfflegalize_dlatchsr_init.ys
+3 −3 tests/techmap/dfflegalize_inv.ys
+1 −1 tests/techmap/dfflegalize_mince.ys
+1 −1 tests/techmap/dfflegalize_minsrst.ys
+6 −6 tests/techmap/dfflegalize_sr.ys
+12 −12 tests/techmap/dfflegalize_sr_init.ys
+2 −2 tests/techmap/zinit.ys

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