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Issues list

Out-of-bounds write for stray % pending-verification This issue is pending verification and/or reproduction
#3484 opened Sep 17, 2022 by Ravenslofty
Checksum changed for archived release 0.18-dev pending-verification This issue is pending verification and/or reproduction
#3479 opened Sep 9, 2022 by j2kun
abc leaves assign statements in generated netlist pending-verification This issue is pending verification and/or reproduction
#3475 opened Sep 7, 2022 by davideschiavone
latch inferred when indexing with incremented integer discuss to be discussed at next dev jour fixe (see #devel-discuss at https://yosyshq.slack.com/) SystemVerilog Issues and questions related to SystemVerilog
#3456 opened Aug 23, 2022 by kranerup
Commit a04b025ab broke my design. needs-info Issue needs more context/information in order to be resolved
#3455 opened Aug 23, 2022 by M3m3M4n
for loop consumes extreme amount of memory SystemVerilog Issues and questions related to SystemVerilog
#3447 opened Aug 17, 2022 by kranerup
Equivalence checking issue discuss to be discussed at next dev jour fixe (see #devel-discuss at https://yosyshq.slack.com/)
#3428 opened Jul 29, 2022 by alaindargelas
synth error question
#3412 opened Jul 14, 2022 by RanChenRivai
About synth xilinx dsp
#3401 opened Jul 5, 2022 by KKtiandao
Write Aiger Stack Overflow bug
#3355 opened Jun 2, 2022 by ALGCDG
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