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Synthesis issue with shift and multiplication #1047

ymherklotz opened this issue May 28, 2019 · 1 comment · Fixed by #1049

Synthesis issue with shift and multiplication #1047

ymherklotz opened this issue May 28, 2019 · 1 comment · Fixed by #1049


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@ymherklotz ymherklotz commented May 28, 2019

Steps to reproduce the issue

Consider the following Verilog code

module top (y, w);
   output y;
   input [2:0] w;
   assign y = 1'b1 >> (w * (3'b110));

Run with yosys version

Generated by Yosys 0.8+498 (git sha1 92dde319, clang 8.0.0 -fPIC -Os)

and the following command

yosys -p 'read -formal rtl.v; synth; write_verilog -noattr syn_yosys.v'

Expected behavior

When passing the input 3'b100, I would expect the output to give 1'b1, as 3'b100 * 3'b110 = 3'b000.

Actual behavior

The synthesised output is the following, which when given 3'b100 gives 1'b0 as output.

module top(y, w);
  wire _0_;
  input [2:0] w;
  output y;
  assign _0_ = ~(w[1] | w[0]);
  assign y = _0_ & ~(w[2]);

I have included a testbench with iverilog and SymbiYosys script that compares the RTL to the synthesised Verilog. To run everything, run ./

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@cliffordwolf cliffordwolf commented May 28, 2019

Thanks for reporting this issue. #1049 will fix this.

cliffordwolf added a commit that referenced this issue May 28, 2019

Signed-off-by: Clifford Wolf <>
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