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Override verilog parameters #132

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olofk opened this Issue Mar 21, 2016 · 2 comments

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@olofk
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olofk commented Mar 21, 2016

I can't find information on how to override verilog parameters with yosys. This is commonly used to set top-level parameters at synthesis-time.

@cliffordwolf

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cliffordwolf commented Mar 21, 2016

The command you are looking for is chparam. However there was a problem with combining chparam and read_verilog -defer. I've now fixed that in commit 2c7e107.

Example Verilog code:

module submod(input [7:0] a, output [7:0] y);
  parameter integer increment = 0;
  initial begin
    if (increment == 0) begin
      $display("increment parameter must have a non-zero value!");
      $stop;
    end
  end
  assign y = a + increment;
endmodule

module topmod(input [7:0] a, output [7:0] y);
  parameter integer incr = 0;
  submod #(incr) submod_instance (a, y);
endmodule

Yosys script using chparam and read_verilog -defer:

read_verilog -defer test.v
chparam -set incr 42 topmod
synth -top topmod

Work-around for Yosys 0.6 (this also works with git head):

read_verilog -defer test.v
chparam -set incr 42 $abstract\topmod
synth -top topmod
@adumont

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adumont commented Jul 10, 2018

I was facing a similar need. This question showed up while I was working on a solution. I ended up with a different approach though:

I'm creating a wrapper to my top module, written in m4 language. It's very simple, it overrides the parameters value, and then includes my top module definition.

Then in the Makefile, I process the wrapper.m4 file, to create the resulting wrapper.v file, that will be input to yosys.

I have detailled my approach here, in case it can be useful anyone.

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