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Override verilog parameters #132
Example Verilog code:
Yosys script using
Work-around for Yosys 0.6 (this also works with git head):
I was facing a similar need. This question showed up while I was working on a solution. I ended up with a different approach though:
I'm creating a wrapper to my top module, written in m4 language. It's very simple, it overrides the parameters value, and then includes my top module definition.
Then in the Makefile, I process the wrapper.m4 file, to create the resulting wrapper.v file, that will be input to yosys.
I have detailled my approach here, in case it can be useful anyone.