Clock in interface port mis-synthesized away (but accepted in modport)

[tux3]

Steps to reproduce the issue

Attachment interface_clk_issue.zip contains good.sv, bad.sv, and a Makefile.
Run make good to observe the expected output, and make bad to reproduce the mis-synthesis.
This is reproduced on the current master (aa1adb0), using synth_ice40.

The file bad.sv connects a clock to the interface instance:

interface dummybus(input clk, input rst);
    modport host(input clk, input rst);
    modport device(input clk, input rst);
endinterface

module top(input clk, input rst);
    dummybus bus(.clk, .rst); // bus driven here
    device dev(.bus);
    host host(.clk, .rst, .bus);
endmodule

module host(input clk, input rst, dummybus.host bus);
    // This page intentionally left blank
endmodule

module device(dummybus.device bus);
    (* keep *)
    logic [63:0] keep;
    always @(posedge bus.clk)
        if (bus.rst) begin
            keep <= 'b0;
        end else begin
            keep <= keep + 'b1;
        end
endmodule

And good.sv connects the clock to a modport, which works as expected:

interface dummybus();
    logic clk;
    logic rst;
    modport host(output clk, output rst);
    modport device(input clk, input rst);
endinterface

module top(input clk, input rst);
    dummybus bus();
    device dev(.bus);
    host host(.clk, .rst, .bus);
endmodule

module host(input clk, input rst, dummybus.host bus);
    // This works, the clock is recognized
    assign bus.clk = clk;
    assign bus.rst = rst;
endmodule

module device (dummybus.device bus);
    (* keep *)
    logic [63:0] keep;
    always @(posedge bus.clk)
        if (bus.rst) begin
            keep <= 'b0;
        end else begin
            keep <= keep + 'b1;
        end
endmodule

The result of synthetizing bad.sv is zero cells and a warning that the bus clock has no drivers.
Simulation in ALDEC shows the same expected behavior for both files (keep is incremented).

Expected behavior

Yosys should see that the clock in bad.sv is driven from the top.
Synthesis results for bad.sv should be functionally equivalent to good.sv.

Actual behavior

Yosys misses the clock in bad.sv and removes live code.

Warning: Wire top.\bus.rst is used but has no driver.
Warning: Wire top.\dev.bus.clk is used but has no driver.

Number of processes: 0
Number of cells: 0

Also note that there are the same type of warnings as in #1053 in both good.sv and bad.sv, but this may not be related to this issue:

good.sv:16: Warning: Identifier '\bus.clk' is implicitly declared.
good.sv:17: Warning: Identifier '\bus.rst' is implicitly declared.