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Missing edge-sensitive event for signal #662

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mngr0 opened this Issue Oct 14, 2018 · 0 comments

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mngr0 commented Oct 14, 2018

Here I have some Verilog code
error.zip
and I am running yosys on it, but it gives an error
ERROR: Missing edge-sensitive event for this signal!

that is caused by the very last always block in the code

always @(posedge sck, negedge spibus_csn) begin: SPI_SLAVE_LED_SPI_SLAVE_FIFO0_CSN_FALLS
    if (sck) begin
        spi_slave_fifo0_spi_start <= 1'b0;
    end
    else if ((!spibus_csn)) begin
        spi_slave_fifo0_spi_start <= 1'b1;
    end
end

I don't understand the problem, if I change to
always @(posedge sck, posedge spibus_csn) begin:
it compiles.

This verilog code is generated using MyHDL

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