Implement a CPU which supports a subset of MIPS operations using Verilog HDL for MS108 (Computer Architecture), ACM Class, SJTU.
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doc
testBenches
utilities
.gitignore
ALU.v
BranchControl.v
EX.v
EX_MEM.v
ForwardControl.v
HazardControl.v
ID.v
ID_EX.v
IF.v
IF_ID.v
LICENSE
MEM.v
MEM_WB.v
README.md
RM_ctrl.v
WM_ctrl.v
decoder.v
define.v
hilo_reg.v
pipeline_CPU.v
regfile.v

README.md

MIPS_CPU

Implement a CPU which supports a subset of MIPS operations using Verilog HDL

The pipeline supports all MIPS standard integer instructions except those related to coprocessors, and the forwarding, hazard control and branch control techniques are all fully implemented. Project report is available here.

Status

  1. finish construction
    • decoder.v
    • BranchControl.v
    • HazardControl.v
    • RM_ctrl.v
    • WM_ctrl.v
    • solve div function
  2. fully review the pipeline code
  3. test
    • write virtual memory, rom
    • test on instrctions
      • ori
      • arithmetic operations
      • memory store/load
      • logic operations
      • bitwise operations
      • hi/lo operations
      • dependency test (forwarding)
      • jump operations
      • overall test
  4. optional improvement
    • add cache
    • implement CP0
  5. report
    • clearly outline the supported instructions