Fixes to interrupt handling

[Uthedris]

Fixes:

• riscv32_common.zig is_pending function need a compare to return a bool.
• hazard3.zig interrupt priority registers were incorrect.
• hazard3.zig removed an interrupt enable that tact1m4n3 didn't like.

[tact1m4n3]

Nice catch! Don't know why I used meifa to set priorities 😆. Also, some riscv examples are broken, please change the examples using external interrupts to enable the MachineExternal interrupt on riscv.

[Uthedris]

I updated the interrupt example. The only other examples I found that used interrupts were RP2040 only, so don't need riscv support.