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  • Gisselquist Technology, LLC

Pinned repositories

  1. openarty

    An Open Source configuration of the Arty platform

    Verilog 40 9

  2. s6soc

    CMod-S6 SoC

    Verilog 15 3

  3. wb2axip

    A pipelined wishbone to AXI converter

    Verilog 18

  4. wbuart32

    A simple UART controller that can easily be wishbone controlled.

    Verilog 33 9

  5. zipcpu

    A small, light weight, RISC CPU soft core

    Verilog 176 20

  6. autofpga

    A utility for Composing FPGA designs from Peripherals

    C++ 41 5

758 contributions in the last year

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Contribution activity

September 2018

Created an issue in YosysHQ/SymbiYosys that received 1 comment

Unexpected behavior with tasks

Problem: If an .sby file references an undefined task, the commands associated with that task are executed by default Example SymbiYosys script: [t…

1 comment

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