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/*******************************************************************************
*
* Filename: sdram.ld
*
* Project: ArrowZip, a demonstration of the Arrow MAX1000 FPGA board
*
* DO NOT EDIT THIS FILE!
* Computer Generated: This file is computer generated by AUTOFPGA. DO NOT EDIT.
* DO NOT EDIT THIS FILE!
*
* CmdLine: autofpga autofpga -d -o . clock.txt global.txt dlyarbiter.txt version.txt buserr.txt pic.txt pwrcount.txt spio.txt rtclight.txt hbconsole.txt bkram.txt flexpress.txt sdram.txt zipbones.txt sdramscope.txt mem_flash_bkram.txt mem_bkram_only.txt mem_sdram_bkram.txt
*
* Creator: Dan Gisselquist, Ph.D.
* Gisselquist Technology, LLC
*
/*******************************************************************************
*
* Copyright (C) 2018-2019, Gisselquist Technology, LLC
*
* This program is free software (firmware): you can redistribute it and/or
* modify it under the terms of the GNU General Public License as published
* by the Free Software Foundation, either version 3 of the License, or (at
* your option) any later version.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
* for more details.
*
* You should have received a copy of the GNU General Public License along
* with this program. (It's in the $(ROOT)/doc directory. Run make with no
* target there if the PDF file isn't present.) If not, see
* <http://www.gnu.org/licenses/> for a copy.
*
* License: GPL, v3, as defined and found on www.gnu.org,
* http://www.gnu.org/licenses/gpl.html
*
*
/*******************************************************************************
*
*
*/
ENTRY(_start)
MEMORY
{
/* To be listed here, a slave must be of type MEMORY. If the slave
* has a defined name in its @LD.NAME tag, it will be listed here
* under that name. The permissions are given by the @LD.PERM tag.
* If no permission tag exists, a permission of 'r' will be assumed.
*/
bkram(wx) : ORIGIN = 0x00c00000, LENGTH = 0x00008000
flash(rx) : ORIGIN = 0x01000000, LENGTH = 0x00800000
sdram(rwx) : ORIGIN = 0x01800000, LENGTH = 0x00800000
}
/* For each defined memory peripheral, we also define a pointer to that
* memory. The name of this pointer is given by the @LD.NAME tag within
* the memory peripheral's configuration
*/
_bkram = ORIGIN(bkram);
_flash = ORIGIN(flash);
_sdram = ORIGIN(sdram);
/* LD.DEFNS from zipmaster.txt */
_kram = ORIGIN(bkram); /* No high-speed kernel RAM */
_ram = ORIGIN(sdram);
_rom = 0;
_top_of_stack = ORIGIN(bkram) + LENGTH(bkram);
/* LD.SCRIPT from zipmaster.txt */
SECTIONS
{
.rocode ORIGIN(bkram): ALIGN(4) {
_boot_address = .;
*(.start) *(.boot)
} > bkram
_kram_start = . ;
.kernel : ALIGN_WITH_INPUT {
*(.kernel)
*(.text.startup)
_kram_end = . ;
}> bkram
_ram_image_start = . ;
.ramcod : ALIGN_WITH_INPUT {
*(.text*)
*(.rodata*) *(.strings)
*(.data) *(COMMON)
_ram_image_end = . ;
}> sdram
.bss : ALIGN_WITH_INPUT {
*(.bss)
_bss_image_end = . ;
} > sdram
_top_of_heap = .;
}
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