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////////////////////////////////////////////////////////////////////////////////
//
// Filename: ./regdefs.h
//
// Project: ArrowZip, a demonstration of the Arrow MAX1000 FPGA board
//
// DO NOT EDIT THIS FILE!
// Computer Generated: This file is computer generated by AUTOFPGA. DO NOT EDIT.
// DO NOT EDIT THIS FILE!
//
// CmdLine: autofpga autofpga -d -o . clock.txt global.txt dlyarbiter.txt version.txt buserr.txt pic.txt pwrcount.txt spio.txt memsdev.txt rtclight.txt hbconsole.txt bkram.txt flexpress.txt sdram.txt zipbones.txt memsscope.txt mem_all.txt mem_flash_bkram.txt mem_bkram_only.txt mem_sdram_bkram.txt
//
// Creator: Dan Gisselquist, Ph.D.
// Gisselquist Technology, LLC
//
////////////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2018-2019, Gisselquist Technology, LLC
//
// This program is free software (firmware): you can redistribute it and/or
// modify it under the terms of the GNU General Public License as published
// by the Free Software Foundation, either version 3 of the License, or (at
// your option) any later version.
//
// This program is distributed in the hope that it will be useful, but WITHOUT
// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with this program. (It's in the $(ROOT)/doc directory. Run make with no
// target there if the PDF file isn't present.) If not, see
// <http://www.gnu.org/licenses/> for a copy.
//
// License: GPL, v3, as defined and found on www.gnu.org,
// http://www.gnu.org/licenses/gpl.html
//
//
////////////////////////////////////////////////////////////////////////////////
//
//
#ifndef REGDEFS_H
#define REGDEFS_H
//
// The @REGDEFS.H.INCLUDE tag
//
// @REGDEFS.H.INCLUDE for masters
// @REGDEFS.H.INCLUDE for peripherals
// And finally any master REGDEFS.H.INCLUDE tags
// End of definitions from REGDEFS.H.INCLUDE
//
// Register address definitions, from @REGS.#d
//
// FLASH erase/program configuration registers
#define R_FLASHCFG 0x00200000 // 00200000, wbregs names: FLASHCFG, QSPIC
// memsdbg compressed scope
#define R_MEMSSCOPE 0x00400000 // 00400000, wbregs names: MEMSSCOPE
#define R_MEMSSCOPED 0x00400004 // 00400000, wbregs names: MEMSSCOPED
// CONSOLE registers
#define R_CONSOLE_FIFO 0x00600004 // 00600000, wbregs names: UFIFO
#define R_CONSOLE_UARTRX 0x00600008 // 00600000, wbregs names: RX
#define R_CONSOLE_UARTTX 0x0060000c // 00600000, wbregs names: TX
#define R_BUILDTIME 0x00800000 // 00800000, wbregs names: BUILDTIME
#define R_BUILDTIME 0x00800000 // 00800000, wbregs names: BUILDTIME
#define R_BUSERR 0x00800004 // 00800004, wbregs names: BUSERR
#define R_BUSERR 0x00800004 // 00800004, wbregs names: BUSERR
#define R_PIC 0x00800008 // 00800008, wbregs names: PIC
#define R_PIC 0x00800008 // 00800008, wbregs names: PIC
#define R_PWRCOUNT 0x0080000c // 0080000c, wbregs names: PWRCOUNT
#define R_PWRCOUNT 0x0080000c // 0080000c, wbregs names: PWRCOUNT
#define R_SPIO 0x00800010 // 00800010, wbregs names: SPIO
#define R_SPIO 0x00800010 // 00800010, wbregs names: SPIO
#define R_VERSION 0x00800014 // 00800014, wbregs names: VERSION
#define R_VERSION 0x00800014 // 00800014, wbregs names: VERSION
// The bus timer
#define R_BUSTIMER 0x00a00000 // 00a00000, wbregs names: BUSTIMER
// The bus timer
#define R_BUSTIMER 0x00a00000 // 00a00000, wbregs names: BUSTIMER
// The watchdog timer
#define R_WATCHDOG 0x00a00400 // 00a00400, wbregs names: WATCHDOG
// The watchdog timer
#define R_WATCHDOG 0x00a00400 // 00a00400, wbregs names: WATCHDOG
// RTC clock registers
#define R_CLOCK 0x00a00800 // 00a00800, wbregs names: CLOCK
#define R_TIMER 0x00a00804 // 00a00800, wbregs names: TIMER
#define R_STOPWATCH 0x00a00808 // 00a00800, wbregs names: STOPWATCH
#define R_CKALARM 0x00a0080c // 00a00800, wbregs names: ALARM, CKALARM
#define R_CKSPEED 0x00a00810 // 00a00800, wbregs names: CKSPEED
// RTC clock registers
#define R_CLOCK 0x00a00800 // 00a00800, wbregs names: CLOCK
#define R_TIMER 0x00a00804 // 00a00800, wbregs names: TIMER
#define R_STOPWATCH 0x00a00808 // 00a00800, wbregs names: STOPWATCH
#define R_CKALARM 0x00a0080c // 00a00800, wbregs names: ALARM, CKALARM
#define R_CKSPEED 0x00a00810 // 00a00800, wbregs names: CKSPEED
// MEMS register(s)
#define R_MEMS 0x00a00c00 // 00a00c00, wbregs names: $(DEVID)
#define R_MEMSAUX 0x00a00c1c // 00a00c00, wbregs names: MEMSAUX
#define R_MEMS_WHOAMI 0x00a00c3c // 00a00c00, wbregs names: MEMSWHOAMI, WHOAMI
#define R_ADC1 0x00a00d20 // 00a00c00, wbregs names: ADC1
#define R_ADC2 0x00a00d28 // 00a00c00, wbregs names: ADC2
#define R_ADC3 0x00a00d30 // 00a00c00, wbregs names: ADC3
#define R_MEMSCTRL0 0x00a00c78 // 00a00c00, wbregs names: MEMSCTRL0
#define R_MEMSCTRL1 0x00a00c80 // 00a00c00, wbregs names: MEMSCTRL1
#define R_MEMSCTRL2 0x00a00c84 // 00a00c00, wbregs names: MEMSCTRL2
#define R_MEMSCTRL3 0x00a00c88 // 00a00c00, wbregs names: MEMSCTRL3
#define R_MEMSCTRL4 0x00a00c8c // 00a00c00, wbregs names: MEMSCTRL4
#define R_MEMSCTRL5 0x00a00c90 // 00a00c00, wbregs names: MEMSCTRL5
#define R_MEMSCTRL6 0x00a00c94 // 00a00c00, wbregs names: MEMSCTRL6
#define R_MEMSREF 0x00a00c98 // 00a00c00, wbregs names: MEMSREF
#define R_MEMSSTAT 0x00a00c9c // 00a00c00, wbregs names: MEMSSTAT
#define R_MEMSX 0x00a00d70 // 00a00c00, wbregs names: MEMSX
#define R_MEMSY 0x00a00d78 // 00a00c00, wbregs names: MEMSY
#define R_MEMSZ 0x00a00d78 // 00a00c00, wbregs names: MEMSZ
#define R_MEMSFIFOC 0x00a00cb8 // 00a00c00, wbregs names: MEMSFIFOC
#define R_MEMSFIFOS 0x00a00cbc // 00a00c00, wbregs names: MEMSFIFOS
#define R_MEMSINT1C 0x00a00cc0 // 00a00c00, wbregs names: MEMSINT1C
#define R_MEMSINT1S 0x00a00cc4 // 00a00c00, wbregs names: MEMSINT1S
#define R_MEMSINT1TH 0x00a00cc8 // 00a00c00, wbregs names: MEMSINT1TH
#define R_MEMSINT1D 0x00a00ccc // 00a00c00, wbregs names: MEMSINT1D
#define R_MEMSINT2C 0x00a00cd0 // 00a00c00, wbregs names: MEMSINT2C
#define R_MEMSINT2S 0x00a00cd4 // 00a00c00, wbregs names: MEMSINT2S
#define R_MEMSINT2TH 0x00a00cd8 // 00a00c00, wbregs names: MEMSINT2TH
#define R_MEMSINT2D 0x00a00cdc // 00a00c00, wbregs names: MEMSINT2D
#define R_MEMSCKCFG 0x00a00ce0 // 00a00c00, wbregs names: MEMSCKCFG
#define R_MEMSCKSRC 0x00a00ce4 // 00a00c00, wbregs names: MEMSCKSRC
#define R_MEMSCKTHS 0x00a00ce8 // 00a00c00, wbregs names: MEMSCKTHS
#define R_MEMSTMLIMIT 0x00a00cec // 00a00c00, wbregs names: MEMSTMLIMIT
#define R_MEMSLATENCY 0x00a00cf0 // 00a00c00, wbregs names: MEMSLATENCY
#define R_MEMSWINDOW 0x00a00cf4 // 00a00c00, wbregs names: MEMSWINDOW
#define R_MEMSACTTHS 0x00a00cf8 // 00a00c00, wbregs names: MEMSACTTHS
#define R_MEMSACTDUR 0x00a00cfc // 00a00c00, wbregs names: MEMSACTDUR
// MEMS register(s)
#define R_MEMS 0x00a00c00 // 00a00c00, wbregs names: $(DEVID)
#define R_MEMSAUX 0x00a00c1c // 00a00c00, wbregs names: MEMSAUX
#define R_MEMS_WHOAMI 0x00a00c3c // 00a00c00, wbregs names: MEMSWHOAMI, WHOAMI
#define R_ADC1 0x00a00d20 // 00a00c00, wbregs names: ADC1
#define R_ADC2 0x00a00d28 // 00a00c00, wbregs names: ADC2
#define R_ADC3 0x00a00d30 // 00a00c00, wbregs names: ADC3
#define R_MEMSCTRL0 0x00a00c78 // 00a00c00, wbregs names: MEMSCTRL0
#define R_MEMSCTRL1 0x00a00c80 // 00a00c00, wbregs names: MEMSCTRL1
#define R_MEMSCTRL2 0x00a00c84 // 00a00c00, wbregs names: MEMSCTRL2
#define R_MEMSCTRL3 0x00a00c88 // 00a00c00, wbregs names: MEMSCTRL3
#define R_MEMSCTRL4 0x00a00c8c // 00a00c00, wbregs names: MEMSCTRL4
#define R_MEMSCTRL5 0x00a00c90 // 00a00c00, wbregs names: MEMSCTRL5
#define R_MEMSCTRL6 0x00a00c94 // 00a00c00, wbregs names: MEMSCTRL6
#define R_MEMSREF 0x00a00c98 // 00a00c00, wbregs names: MEMSREF
#define R_MEMSSTAT 0x00a00c9c // 00a00c00, wbregs names: MEMSSTAT
#define R_MEMSX 0x00a00d70 // 00a00c00, wbregs names: MEMSX
#define R_MEMSY 0x00a00d78 // 00a00c00, wbregs names: MEMSY
#define R_MEMSZ 0x00a00d78 // 00a00c00, wbregs names: MEMSZ
#define R_MEMSFIFOC 0x00a00cb8 // 00a00c00, wbregs names: MEMSFIFOC
#define R_MEMSFIFOS 0x00a00cbc // 00a00c00, wbregs names: MEMSFIFOS
#define R_MEMSINT1C 0x00a00cc0 // 00a00c00, wbregs names: MEMSINT1C
#define R_MEMSINT1S 0x00a00cc4 // 00a00c00, wbregs names: MEMSINT1S
#define R_MEMSINT1TH 0x00a00cc8 // 00a00c00, wbregs names: MEMSINT1TH
#define R_MEMSINT1D 0x00a00ccc // 00a00c00, wbregs names: MEMSINT1D
#define R_MEMSINT2C 0x00a00cd0 // 00a00c00, wbregs names: MEMSINT2C
#define R_MEMSINT2S 0x00a00cd4 // 00a00c00, wbregs names: MEMSINT2S
#define R_MEMSINT2TH 0x00a00cd8 // 00a00c00, wbregs names: MEMSINT2TH
#define R_MEMSINT2D 0x00a00cdc // 00a00c00, wbregs names: MEMSINT2D
#define R_MEMSCKCFG 0x00a00ce0 // 00a00c00, wbregs names: MEMSCKCFG
#define R_MEMSCKSRC 0x00a00ce4 // 00a00c00, wbregs names: MEMSCKSRC
#define R_MEMSCKTHS 0x00a00ce8 // 00a00c00, wbregs names: MEMSCKTHS
#define R_MEMSTMLIMIT 0x00a00cec // 00a00c00, wbregs names: MEMSTMLIMIT
#define R_MEMSLATENCY 0x00a00cf0 // 00a00c00, wbregs names: MEMSLATENCY
#define R_MEMSWINDOW 0x00a00cf4 // 00a00c00, wbregs names: MEMSWINDOW
#define R_MEMSACTTHS 0x00a00cf8 // 00a00c00, wbregs names: MEMSACTTHS
#define R_MEMSACTDUR 0x00a00cfc // 00a00c00, wbregs names: MEMSACTDUR
#define R_BKRAM 0x00c00000 // 00c00000, wbregs names: RAM
#define R_FLASH 0x01000000 // 01000000, wbregs names: FLASH
#define R_SDRAM 0x01800000 // 01800000, wbregs names: SDRAM
//
// The @REGDEFS.H.DEFNS tag
//
// @REGDEFS.H.DEFNS for masters
#define CLKFREQHZ 80000000
#define R_ZIPCTRL 0x02000000
#define R_ZIPDATA 0x02000004
#define BAUDRATE 1000000
// @REGDEFS.H.DEFNS for peripherals
#define BKRAMBASE 0x00c00000
#define BKRAMLEN 0x00008000
#define SDRAMBASE 0x01800000
#define SDRAMLEN 0x00800000
#define DSPI_FLASH
#define FLASHBASE 0x01000000
#define FLASHLEN 0x00800000
#define FLASHLGLEN 23
// No defines yet
// @REGDEFS.H.DEFNS at the top level
// End of definitions from REGDEFS.H.DEFNS
//
// The @REGDEFS.H.INSERT tag
//
// @REGDEFS.H.INSERT for masters
#define CPU_GO 0x0000
#define CPU_RESET 0x0040
#define CPU_INT 0x0080
#define CPU_STEP 0x0100
#define CPU_STALL 0x0200
#define CPU_HALT 0x0400
#define CPU_CLRCACHE 0x0800
#define CPU_sR0 0x0000
#define CPU_sSP 0x000d
#define CPU_sCC 0x000e
#define CPU_sPC 0x000f
#define CPU_uR0 0x0010
#define CPU_uSP 0x001d
#define CPU_uCC 0x001e
#define CPU_uPC 0x001f
#define RESET_ADDRESS 0x01000000
// @REGDEFS.H.INSERT for peripherals
// Flash control constants
#define DSPI_FLASH // This core and hardware support a Dual SPI flash
#define SZPAGEB 256
#define PGLENB 256
#define SZPAGEW 64
#define PGLENW 64
#define NPAGES 256
#define SECTORSZB (NPAGES * SZPAGEB) // In bytes, not words!!
#define SECTORSZW (NPAGES * SZPAGEW) // In words
#define NSECTORS 64
#define SECTOROF(A) ((A) & (-1<<16))
#define SUBSECTOROF(A) ((A) & (-1<<12))
#define PAGEOF(A) ((A) & (-1<<8))
// @REGDEFS.H.INSERT from the top level
typedef struct {
unsigned m_addr;
const char *m_name;
} REGNAME;
extern const REGNAME *bregs;
extern const int NREGS;
// #define NREGS (sizeof(bregs)/sizeof(bregs[0]))
extern unsigned addrdecode(const char *v);
extern const char *addrname(const unsigned v);
// End of definitions from REGDEFS.H.INSERT
#endif // REGDEFS_H
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