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Commits on May 11, 2018
Commits on Oct 4, 2017
Commits on Aug 8, 2017
  1. Added a master makefile

    ZipCPU committed Aug 8, 2017
Commits on Aug 3, 2017
Commits on Jul 14, 2017
  1. Found and fixed a multiple space bug in hexbus S/W

    ZipCPU committed Jul 14, 2017
    The hexbus decoding software was decoding multiple spaces into multiple
    zero values.  This fix changes things so that two white space characters in a
    row will not produce values.  (The first white space character will still
    end the previous value, the second white space character, though, will not
    create a new value--unless a number is passed in between.)
  2. Adjusted the testbus: halts and wires v regs

    ZipCPU committed Jul 14, 2017
    Surrounded o_halt in the design by `ifdef VERILOG, so it is only active
    if Verilog is installed.
    Fixed register vs wire declarations that Verilator didn't find.
Commits on Jul 1, 2017
Commits on Jun 29, 2017
Commits on Jun 28, 2017
Commits on Jun 27, 2017
Commits on Jun 26, 2017
Commits on Jun 22, 2017
  1. Added two new registers, adjusted build date

    ZipCPU committed Jun 22, 2017
    Added the bus error register and the power count register, and adjusted the
    build date to be 20170622.
Commits on Jun 20, 2017