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Added a master Makefile, and subdir makefile structure
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ZipCPU committed Jul 17, 2018
1 parent 92caf67 commit 296bf66
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Showing 3 changed files with 65 additions and 2 deletions.
58 changes: 58 additions & 0 deletions Makefile
@@ -0,0 +1,58 @@
###############################################################################
##
## Filename: Makefile
##
## Project: DSP Filtering Example Project
##
## Purpose: This is the master project makefile, building simulation
## components for all of the cores that exist in bench/cpp.
##
## Targets: The default target, all, builds all subdirectory targets.
##
## Creator: Dan Gisselquist, Ph.D.
## Gisselquist Technology, LLC
##
################################################################################
##
## Copyright (C) 2018, Gisselquist Technology, LLC
##
## This program is free software (firmware): you can redistribute it and/or
## modify it under the terms of the GNU General Public License as published
## by the Free Software Foundation, either version 3 of the License, or (at
## your option) any later version.
##
## This program is distributed in the hope that it will be useful, but WITHOUT
## ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
## for more details.
##
## You should have received a copy of the GNU General Public License along
## with this program. (It's in the $(ROOT)/doc directory. Run make with no
## target there if the PDF file isn't present.) If not, see
## <http://www.gnu.org/licenses/> for a copy.
##
## License: GPL, v3, as defined and found on www.gnu.org,
## http://www.gnu.org/licenses/gpl.html
##
################################################################################
##
##
all: benchcpp
SUBMAKE := make --no-print-directory -C

rtld:
$(SUBMAKE) rtl

benchrtl: rtld
$(SUBMAKE) bench/rtl

benchcpp: benchrtl rtl
$(SUBMAKE) bench/cpp

formal: rtld
$(SUBMAKE) formal

clean:
$(SUBMAKE) rtl clean
$(SUBMAKE) bench/rtl clean
$(SUBMAKE) bench/cpp clean
7 changes: 6 additions & 1 deletion bench/cpp/Makefile
Expand Up @@ -50,7 +50,7 @@ export $(VERILATOR)
VROOT := $(VERILATOR_ROOT)
VDEFS := $(shell ./vversion.sh)
INCS := -I$(RTLD)/obj_dir/ -I$(VROOT)/include -I../rtl/obj_dir
PROGRAMS := slowsymf_tb genericfir_tb fastfir_tb boxcar_tb lfsr_gal_tb lfsr_fib_tb delayw_tb slowfil_tb shalfband_tb # symfil_tb
PROGRAMS := slowsymf_tb genericfir_tb fastfir_tb boxcar_tb lfsr_gal_tb lfsr_fib_tb delayw_tb slowfil_tb shalfband_tb lfsr_tb # symfil_tb
SOURCES := $(addsuffix .cpp,$(PROGRAMS)) filtertb.cpp
VOBJDR := $(RTLD)/obj_dir
SYSVDR := $(VROOT)/include
Expand Down Expand Up @@ -134,5 +134,10 @@ tags: $(SOURCES) $(HEADERS)
clean:
rm -f $(PROGRAMS)
rm -rf $(OBJDIR)/
rm -rf *.vcd
rm -rf filter_tb.dbl dsp.64t
rm -rf tags

ifneq ($(MAKECMDGOALS),clean)
-include $(OBJDIR)/depends.txt
endif
2 changes: 1 addition & 1 deletion bench/formal/Makefile
Expand Up @@ -97,5 +97,5 @@ clean:
rm -f $(LFSR).smt2 $(LFSR)*.vcd $(LFSR).yslog
rm -f $(EQUIV).smt2 $(EQUIV)*.vcd $(EQUIV).yslog
rm -f $(DELAY).smt2 $(DELAY)*.vcd $(DELAY).yslog
rm -rf $(FFIR)/
rm -rf $(FFIR)_first/ $(FFIR)_second/
rm -f *.check

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